Commit | Line | Data |
---|---|---|
b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
f17c130b | 2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
b43420e6 | 3 | 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
b99bd4ef NC |
4 | Free Software Foundation, Inc. |
5 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) | |
6 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 7 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
8 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
9 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
10 | |
11 | This file is part of GAS, the GNU Assembler. | |
12 | ||
13 | GAS is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 15 | the Free Software Foundation; either version 3, or (at your option) |
b99bd4ef NC |
16 | any later version. |
17 | ||
18 | GAS is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
21 | GNU General Public License for more details. |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
25 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
26 | 02110-1301, USA. */ | |
b99bd4ef | 27 | |
42a68e18 | 28 | #include "as.h" |
5287ad62 | 29 | #include <limits.h> |
037e8744 | 30 | #include <stdarg.h> |
c19d1205 | 31 | #define NO_RELOC 0 |
3882b010 | 32 | #include "safe-ctype.h" |
b99bd4ef NC |
33 | #include "subsegs.h" |
34 | #include "obstack.h" | |
b99bd4ef | 35 | |
f263249b RE |
36 | #include "opcode/arm.h" |
37 | ||
b99bd4ef NC |
38 | #ifdef OBJ_ELF |
39 | #include "elf/arm.h" | |
a394c00f | 40 | #include "dw2gencfi.h" |
b99bd4ef NC |
41 | #endif |
42 | ||
f0927246 NC |
43 | #include "dwarf2dbg.h" |
44 | ||
7ed4c4c5 NC |
45 | #ifdef OBJ_ELF |
46 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
47 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
48 | ||
49 | /* This structure holds the unwinding state. */ | |
50 | ||
51 | static struct | |
52 | { | |
c19d1205 ZW |
53 | symbolS * proc_start; |
54 | symbolS * table_entry; | |
55 | symbolS * personality_routine; | |
56 | int personality_index; | |
7ed4c4c5 | 57 | /* The segment containing the function. */ |
c19d1205 ZW |
58 | segT saved_seg; |
59 | subsegT saved_subseg; | |
7ed4c4c5 NC |
60 | /* Opcodes generated from this function. */ |
61 | unsigned char * opcodes; | |
c19d1205 ZW |
62 | int opcode_count; |
63 | int opcode_alloc; | |
7ed4c4c5 | 64 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 65 | offsetT frame_size; |
7ed4c4c5 NC |
66 | /* We don't add stack adjustment opcodes immediately so that we can merge |
67 | multiple adjustments. We can also omit the final adjustment | |
68 | when using a frame pointer. */ | |
c19d1205 | 69 | offsetT pending_offset; |
7ed4c4c5 | 70 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
71 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
72 | offsetT fp_offset; | |
73 | int fp_reg; | |
7ed4c4c5 | 74 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 75 | unsigned fp_used:1; |
7ed4c4c5 | 76 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 77 | unsigned sp_restored:1; |
7ed4c4c5 NC |
78 | } unwind; |
79 | ||
8b1ad454 NC |
80 | #endif /* OBJ_ELF */ |
81 | ||
4962c51a MS |
82 | /* Results from operand parsing worker functions. */ |
83 | ||
84 | typedef enum | |
85 | { | |
86 | PARSE_OPERAND_SUCCESS, | |
87 | PARSE_OPERAND_FAIL, | |
88 | PARSE_OPERAND_FAIL_NO_BACKTRACK | |
89 | } parse_operand_result; | |
90 | ||
33a392fb PB |
91 | enum arm_float_abi |
92 | { | |
93 | ARM_FLOAT_ABI_HARD, | |
94 | ARM_FLOAT_ABI_SOFTFP, | |
95 | ARM_FLOAT_ABI_SOFT | |
96 | }; | |
97 | ||
c19d1205 | 98 | /* Types of processor to assemble for. */ |
b99bd4ef | 99 | #ifndef CPU_DEFAULT |
8a59fff3 MGD |
100 | /* The code that was here used to select a default CPU depending on compiler |
101 | pre-defines which were only present when doing native builds, thus | |
102 | changing gas' default behaviour depending upon the build host. | |
103 | ||
104 | If you have a target that requires a default CPU option then the you | |
105 | should define CPU_DEFAULT here. */ | |
b99bd4ef NC |
106 | #endif |
107 | ||
108 | #ifndef FPU_DEFAULT | |
c820d418 MM |
109 | # ifdef TE_LINUX |
110 | # define FPU_DEFAULT FPU_ARCH_FPA | |
111 | # elif defined (TE_NetBSD) | |
112 | # ifdef OBJ_ELF | |
113 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
114 | # else | |
115 | /* Legacy a.out format. */ | |
116 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
117 | # endif | |
4e7fd91e PB |
118 | # elif defined (TE_VXWORKS) |
119 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
120 | # else |
121 | /* For backwards compatibility, default to FPA. */ | |
122 | # define FPU_DEFAULT FPU_ARCH_FPA | |
123 | # endif | |
124 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 125 | |
c19d1205 | 126 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 127 | |
e74cfd16 PB |
128 | static arm_feature_set cpu_variant; |
129 | static arm_feature_set arm_arch_used; | |
130 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 131 | |
b99bd4ef | 132 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
133 | static int uses_apcs_26 = FALSE; |
134 | static int atpcs = FALSE; | |
b34976b6 AM |
135 | static int support_interwork = FALSE; |
136 | static int uses_apcs_float = FALSE; | |
c19d1205 | 137 | static int pic_code = FALSE; |
845b51d6 | 138 | static int fix_v4bx = FALSE; |
278df34e NS |
139 | /* Warn on using deprecated features. */ |
140 | static int warn_on_deprecated = TRUE; | |
141 | ||
03b1477f RE |
142 | |
143 | /* Variables that we set while parsing command-line options. Once all | |
144 | options have been read we re-process these values to set the real | |
145 | assembly flags. */ | |
e74cfd16 PB |
146 | static const arm_feature_set *legacy_cpu = NULL; |
147 | static const arm_feature_set *legacy_fpu = NULL; | |
148 | ||
149 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
150 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
151 | static const arm_feature_set *march_cpu_opt = NULL; | |
152 | static const arm_feature_set *march_fpu_opt = NULL; | |
153 | static const arm_feature_set *mfpu_opt = NULL; | |
7a1d4c38 | 154 | static const arm_feature_set *object_arch = NULL; |
e74cfd16 PB |
155 | |
156 | /* Constants for known architecture features. */ | |
157 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
158 | static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; | |
159 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; | |
5287ad62 JB |
160 | static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; |
161 | static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; | |
e74cfd16 PB |
162 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
163 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
164 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; | |
165 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; | |
166 | ||
167 | #ifdef CPU_DEFAULT | |
168 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
169 | #endif | |
170 | ||
171 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); | |
172 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); | |
173 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); | |
174 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); | |
175 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); | |
176 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); | |
177 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); | |
178 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); | |
179 | static const arm_feature_set arm_ext_v4t_5 = | |
180 | ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); | |
181 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); | |
182 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); | |
183 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); | |
184 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); | |
185 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); | |
186 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); | |
187 | static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0); | |
188 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); | |
62b3e311 | 189 | static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); |
9e3c6df6 | 190 | static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0); |
7e806470 PB |
191 | static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0); |
192 | static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0); | |
62b3e311 PB |
193 | static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); |
194 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); | |
195 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); | |
196 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); | |
9e3c6df6 | 197 | static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); |
7e806470 PB |
198 | static const arm_feature_set arm_ext_m = |
199 | ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_V7M, 0); | |
e74cfd16 PB |
200 | |
201 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
202 | static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); | |
203 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; | |
204 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
205 | ||
2d447fca JM |
206 | static const arm_feature_set arm_cext_iwmmxt2 = |
207 | ARM_FEATURE (0, ARM_CEXT_IWMMXT2); | |
e74cfd16 PB |
208 | static const arm_feature_set arm_cext_iwmmxt = |
209 | ARM_FEATURE (0, ARM_CEXT_IWMMXT); | |
210 | static const arm_feature_set arm_cext_xscale = | |
211 | ARM_FEATURE (0, ARM_CEXT_XSCALE); | |
212 | static const arm_feature_set arm_cext_maverick = | |
213 | ARM_FEATURE (0, ARM_CEXT_MAVERICK); | |
214 | static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); | |
215 | static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); | |
216 | static const arm_feature_set fpu_vfp_ext_v1xd = | |
217 | ARM_FEATURE (0, FPU_VFP_EXT_V1xD); | |
218 | static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); | |
219 | static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); | |
62f3b8c8 | 220 | static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD); |
5287ad62 | 221 | static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); |
b1cc4aeb PB |
222 | static const arm_feature_set fpu_vfp_ext_d32 = |
223 | ARM_FEATURE (0, FPU_VFP_EXT_D32); | |
5287ad62 JB |
224 | static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); |
225 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = | |
226 | ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); | |
62f3b8c8 PB |
227 | static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16); |
228 | static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA); | |
229 | static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA); | |
e74cfd16 | 230 | |
33a392fb | 231 | static int mfloat_abi_opt = -1; |
e74cfd16 PB |
232 | /* Record user cpu selection for object attributes. */ |
233 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; | |
ee065d83 PB |
234 | /* Must be long enough to hold any of the names in arm_cpus. */ |
235 | static char selected_cpu_name[16]; | |
7cc69913 | 236 | #ifdef OBJ_ELF |
deeaaff8 DJ |
237 | # ifdef EABI_DEFAULT |
238 | static int meabi_flags = EABI_DEFAULT; | |
239 | # else | |
d507cf36 | 240 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 241 | # endif |
e1da3f5b | 242 | |
ee3c0378 AS |
243 | static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; |
244 | ||
e1da3f5b | 245 | bfd_boolean |
5f4273c7 | 246 | arm_is_eabi (void) |
e1da3f5b PB |
247 | { |
248 | return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); | |
249 | } | |
7cc69913 | 250 | #endif |
b99bd4ef | 251 | |
b99bd4ef | 252 | #ifdef OBJ_ELF |
c19d1205 | 253 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
254 | symbolS * GOT_symbol; |
255 | #endif | |
256 | ||
b99bd4ef NC |
257 | /* 0: assemble for ARM, |
258 | 1: assemble for Thumb, | |
259 | 2: assemble for Thumb even though target CPU does not support thumb | |
260 | instructions. */ | |
261 | static int thumb_mode = 0; | |
8dc2430f NC |
262 | /* A value distinct from the possible values for thumb_mode that we |
263 | can use to record whether thumb_mode has been copied into the | |
264 | tc_frag_data field of a frag. */ | |
265 | #define MODE_RECORDED (1 << 4) | |
b99bd4ef | 266 | |
e07e6e58 NC |
267 | /* Specifies the intrinsic IT insn behavior mode. */ |
268 | enum implicit_it_mode | |
269 | { | |
270 | IMPLICIT_IT_MODE_NEVER = 0x00, | |
271 | IMPLICIT_IT_MODE_ARM = 0x01, | |
272 | IMPLICIT_IT_MODE_THUMB = 0x02, | |
273 | IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) | |
274 | }; | |
275 | static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
276 | ||
c19d1205 ZW |
277 | /* If unified_syntax is true, we are processing the new unified |
278 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
279 | ||
280 | - Immediate operands do not require a # prefix. | |
281 | - Conditional affixes always appear at the end of the | |
282 | instruction. (For backward compatibility, those instructions | |
283 | that formerly had them in the middle, continue to accept them | |
284 | there.) | |
285 | - The IT instruction may appear, and if it does is validated | |
286 | against subsequent conditional affixes. It does not generate | |
287 | machine code. | |
288 | ||
289 | Important differences from the old Thumb mode: | |
290 | ||
291 | - Immediate operands do not require a # prefix. | |
292 | - Most of the V6T2 instructions are only available in unified mode. | |
293 | - The .N and .W suffixes are recognized and honored (it is an error | |
294 | if they cannot be honored). | |
295 | - All instructions set the flags if and only if they have an 's' affix. | |
296 | - Conditional affixes may be used. They are validated against | |
297 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
298 | conditional affix except in the scope of an IT instruction. */ | |
299 | ||
300 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef | 301 | |
5287ad62 JB |
302 | enum neon_el_type |
303 | { | |
dcbf9037 | 304 | NT_invtype, |
5287ad62 JB |
305 | NT_untyped, |
306 | NT_integer, | |
307 | NT_float, | |
308 | NT_poly, | |
309 | NT_signed, | |
dcbf9037 | 310 | NT_unsigned |
5287ad62 JB |
311 | }; |
312 | ||
313 | struct neon_type_el | |
314 | { | |
315 | enum neon_el_type type; | |
316 | unsigned size; | |
317 | }; | |
318 | ||
319 | #define NEON_MAX_TYPE_ELS 4 | |
320 | ||
321 | struct neon_type | |
322 | { | |
323 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; | |
324 | unsigned elems; | |
325 | }; | |
326 | ||
e07e6e58 NC |
327 | enum it_instruction_type |
328 | { | |
329 | OUTSIDE_IT_INSN, | |
330 | INSIDE_IT_INSN, | |
331 | INSIDE_IT_LAST_INSN, | |
332 | IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; | |
333 | if inside, should be the last one. */ | |
334 | NEUTRAL_IT_INSN, /* This could be either inside or outside, | |
335 | i.e. BKPT and NOP. */ | |
336 | IT_INSN /* The IT insn has been parsed. */ | |
337 | }; | |
338 | ||
b99bd4ef NC |
339 | struct arm_it |
340 | { | |
c19d1205 | 341 | const char * error; |
b99bd4ef | 342 | unsigned long instruction; |
c19d1205 ZW |
343 | int size; |
344 | int size_req; | |
345 | int cond; | |
037e8744 JB |
346 | /* "uncond_value" is set to the value in place of the conditional field in |
347 | unconditional versions of the instruction, or -1 if nothing is | |
348 | appropriate. */ | |
349 | int uncond_value; | |
5287ad62 | 350 | struct neon_type vectype; |
88714cb8 DG |
351 | /* This does not indicate an actual NEON instruction, only that |
352 | the mnemonic accepts neon-style type suffixes. */ | |
353 | int is_neon; | |
0110f2b8 PB |
354 | /* Set to the opcode if the instruction needs relaxation. |
355 | Zero if the instruction is not relaxed. */ | |
356 | unsigned long relax; | |
b99bd4ef NC |
357 | struct |
358 | { | |
359 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
360 | expressionS exp; |
361 | int pc_rel; | |
b99bd4ef | 362 | } reloc; |
b99bd4ef | 363 | |
e07e6e58 NC |
364 | enum it_instruction_type it_insn_type; |
365 | ||
c19d1205 ZW |
366 | struct |
367 | { | |
368 | unsigned reg; | |
ca3f61f7 | 369 | signed int imm; |
dcbf9037 | 370 | struct neon_type_el vectype; |
ca3f61f7 NC |
371 | unsigned present : 1; /* Operand present. */ |
372 | unsigned isreg : 1; /* Operand was a register. */ | |
373 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
5287ad62 JB |
374 | unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ |
375 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ | |
c96612cc | 376 | unsigned immisfloat : 1; /* Immediate was parsed as a float. */ |
5287ad62 JB |
377 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV |
378 | instructions. This allows us to disambiguate ARM <-> vector insns. */ | |
379 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ | |
037e8744 | 380 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
5287ad62 | 381 | unsigned isquad : 1; /* Operand is Neon quad-precision register. */ |
037e8744 | 382 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
ca3f61f7 NC |
383 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
384 | unsigned writeback : 1; /* Operand has trailing ! */ | |
385 | unsigned preind : 1; /* Preindexed address. */ | |
386 | unsigned postind : 1; /* Postindexed address. */ | |
387 | unsigned negative : 1; /* Index register was negated. */ | |
388 | unsigned shifted : 1; /* Shift applied to operation. */ | |
389 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
c19d1205 | 390 | } operands[6]; |
b99bd4ef NC |
391 | }; |
392 | ||
c19d1205 | 393 | static struct arm_it inst; |
b99bd4ef NC |
394 | |
395 | #define NUM_FLOAT_VALS 8 | |
396 | ||
05d2d07e | 397 | const char * fp_const[] = |
b99bd4ef NC |
398 | { |
399 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
400 | }; | |
401 | ||
c19d1205 | 402 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
403 | #define MAX_LITTLENUMS 6 |
404 | ||
405 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
406 | ||
407 | #define FAIL (-1) | |
408 | #define SUCCESS (0) | |
409 | ||
410 | #define SUFF_S 1 | |
411 | #define SUFF_D 2 | |
412 | #define SUFF_E 3 | |
413 | #define SUFF_P 4 | |
414 | ||
c19d1205 ZW |
415 | #define CP_T_X 0x00008000 |
416 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 417 | |
c19d1205 ZW |
418 | #define CONDS_BIT 0x00100000 |
419 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
420 | |
421 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
422 | ||
423 | struct asm_cond | |
424 | { | |
d3ce72d0 | 425 | const char * template_name; |
c921be7d | 426 | unsigned long value; |
b99bd4ef NC |
427 | }; |
428 | ||
c19d1205 | 429 | #define COND_ALWAYS 0xE |
b99bd4ef | 430 | |
b99bd4ef NC |
431 | struct asm_psr |
432 | { | |
d3ce72d0 | 433 | const char * template_name; |
c921be7d | 434 | unsigned long field; |
b99bd4ef NC |
435 | }; |
436 | ||
62b3e311 PB |
437 | struct asm_barrier_opt |
438 | { | |
d3ce72d0 | 439 | const char * template_name; |
c921be7d | 440 | unsigned long value; |
62b3e311 PB |
441 | }; |
442 | ||
2d2255b5 | 443 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
444 | #define SPSR_BIT (1 << 22) |
445 | ||
c19d1205 ZW |
446 | /* The individual PSR flag bits. */ |
447 | #define PSR_c (1 << 16) | |
448 | #define PSR_x (1 << 17) | |
449 | #define PSR_s (1 << 18) | |
450 | #define PSR_f (1 << 19) | |
b99bd4ef | 451 | |
c19d1205 | 452 | struct reloc_entry |
bfae80f2 | 453 | { |
c921be7d NC |
454 | char * name; |
455 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
456 | }; |
457 | ||
5287ad62 | 458 | enum vfp_reg_pos |
bfae80f2 | 459 | { |
5287ad62 JB |
460 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
461 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn | |
bfae80f2 RE |
462 | }; |
463 | ||
464 | enum vfp_ldstm_type | |
465 | { | |
466 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
467 | }; | |
468 | ||
dcbf9037 JB |
469 | /* Bits for DEFINED field in neon_typed_alias. */ |
470 | #define NTA_HASTYPE 1 | |
471 | #define NTA_HASINDEX 2 | |
472 | ||
473 | struct neon_typed_alias | |
474 | { | |
c921be7d NC |
475 | unsigned char defined; |
476 | unsigned char index; | |
477 | struct neon_type_el eltype; | |
dcbf9037 JB |
478 | }; |
479 | ||
c19d1205 ZW |
480 | /* ARM register categories. This includes coprocessor numbers and various |
481 | architecture extensions' registers. */ | |
482 | enum arm_reg_type | |
bfae80f2 | 483 | { |
c19d1205 ZW |
484 | REG_TYPE_RN, |
485 | REG_TYPE_CP, | |
486 | REG_TYPE_CN, | |
487 | REG_TYPE_FN, | |
488 | REG_TYPE_VFS, | |
489 | REG_TYPE_VFD, | |
5287ad62 | 490 | REG_TYPE_NQ, |
037e8744 | 491 | REG_TYPE_VFSD, |
5287ad62 | 492 | REG_TYPE_NDQ, |
037e8744 | 493 | REG_TYPE_NSDQ, |
c19d1205 ZW |
494 | REG_TYPE_VFC, |
495 | REG_TYPE_MVF, | |
496 | REG_TYPE_MVD, | |
497 | REG_TYPE_MVFX, | |
498 | REG_TYPE_MVDX, | |
499 | REG_TYPE_MVAX, | |
500 | REG_TYPE_DSPSC, | |
501 | REG_TYPE_MMXWR, | |
502 | REG_TYPE_MMXWC, | |
503 | REG_TYPE_MMXWCG, | |
504 | REG_TYPE_XSCALE, | |
bfae80f2 RE |
505 | }; |
506 | ||
dcbf9037 JB |
507 | /* Structure for a hash table entry for a register. |
508 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra | |
509 | information which states whether a vector type or index is specified (for a | |
510 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ | |
6c43fab6 RE |
511 | struct reg_entry |
512 | { | |
c921be7d NC |
513 | const char * name; |
514 | unsigned char number; | |
515 | unsigned char type; | |
516 | unsigned char builtin; | |
517 | struct neon_typed_alias * neon; | |
6c43fab6 RE |
518 | }; |
519 | ||
c19d1205 | 520 | /* Diagnostics used when we don't get a register of the expected type. */ |
c921be7d | 521 | const char * const reg_expected_msgs[] = |
c19d1205 ZW |
522 | { |
523 | N_("ARM register expected"), | |
524 | N_("bad or missing co-processor number"), | |
525 | N_("co-processor register expected"), | |
526 | N_("FPA register expected"), | |
527 | N_("VFP single precision register expected"), | |
5287ad62 JB |
528 | N_("VFP/Neon double precision register expected"), |
529 | N_("Neon quad precision register expected"), | |
037e8744 | 530 | N_("VFP single or double precision register expected"), |
5287ad62 | 531 | N_("Neon double or quad precision register expected"), |
037e8744 | 532 | N_("VFP single, double or Neon quad precision register expected"), |
c19d1205 ZW |
533 | N_("VFP system register expected"), |
534 | N_("Maverick MVF register expected"), | |
535 | N_("Maverick MVD register expected"), | |
536 | N_("Maverick MVFX register expected"), | |
537 | N_("Maverick MVDX register expected"), | |
538 | N_("Maverick MVAX register expected"), | |
539 | N_("Maverick DSPSC register expected"), | |
540 | N_("iWMMXt data register expected"), | |
541 | N_("iWMMXt control register expected"), | |
542 | N_("iWMMXt scalar register expected"), | |
543 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
544 | }; |
545 | ||
c19d1205 ZW |
546 | /* Some well known registers that we refer to directly elsewhere. */ |
547 | #define REG_SP 13 | |
548 | #define REG_LR 14 | |
549 | #define REG_PC 15 | |
404ff6b5 | 550 | |
b99bd4ef NC |
551 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
552 | take 2: */ | |
c19d1205 | 553 | #define INSN_SIZE 4 |
b99bd4ef NC |
554 | |
555 | struct asm_opcode | |
556 | { | |
557 | /* Basic string to match. */ | |
d3ce72d0 | 558 | const char * template_name; |
c19d1205 ZW |
559 | |
560 | /* Parameters to instruction. */ | |
5be8be5d | 561 | unsigned int operands[8]; |
c19d1205 ZW |
562 | |
563 | /* Conditional tag - see opcode_lookup. */ | |
564 | unsigned int tag : 4; | |
b99bd4ef NC |
565 | |
566 | /* Basic instruction code. */ | |
c19d1205 | 567 | unsigned int avalue : 28; |
b99bd4ef | 568 | |
c19d1205 ZW |
569 | /* Thumb-format instruction code. */ |
570 | unsigned int tvalue; | |
b99bd4ef | 571 | |
90e4755a | 572 | /* Which architecture variant provides this instruction. */ |
c921be7d NC |
573 | const arm_feature_set * avariant; |
574 | const arm_feature_set * tvariant; | |
c19d1205 ZW |
575 | |
576 | /* Function to call to encode instruction in ARM format. */ | |
577 | void (* aencode) (void); | |
b99bd4ef | 578 | |
c19d1205 ZW |
579 | /* Function to call to encode instruction in Thumb format. */ |
580 | void (* tencode) (void); | |
b99bd4ef NC |
581 | }; |
582 | ||
a737bd4d NC |
583 | /* Defines for various bits that we will want to toggle. */ |
584 | #define INST_IMMEDIATE 0x02000000 | |
585 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 586 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
587 | #define SHIFT_BY_REG 0x00000010 |
588 | #define PRE_INDEX 0x01000000 | |
589 | #define INDEX_UP 0x00800000 | |
590 | #define WRITE_BACK 0x00200000 | |
591 | #define LDM_TYPE_2_OR_3 0x00400000 | |
a028a6f5 | 592 | #define CPSI_MMOD 0x00020000 |
90e4755a | 593 | |
a737bd4d NC |
594 | #define LITERAL_MASK 0xf000f000 |
595 | #define OPCODE_MASK 0xfe1fffff | |
596 | #define V4_STR_BIT 0x00000020 | |
90e4755a | 597 | |
efd81785 PB |
598 | #define T2_SUBS_PC_LR 0xf3de8f00 |
599 | ||
a737bd4d | 600 | #define DATA_OP_SHIFT 21 |
90e4755a | 601 | |
ef8d22e6 PB |
602 | #define T2_OPCODE_MASK 0xfe1fffff |
603 | #define T2_DATA_OP_SHIFT 21 | |
604 | ||
a737bd4d NC |
605 | /* Codes to distinguish the arithmetic instructions. */ |
606 | #define OPCODE_AND 0 | |
607 | #define OPCODE_EOR 1 | |
608 | #define OPCODE_SUB 2 | |
609 | #define OPCODE_RSB 3 | |
610 | #define OPCODE_ADD 4 | |
611 | #define OPCODE_ADC 5 | |
612 | #define OPCODE_SBC 6 | |
613 | #define OPCODE_RSC 7 | |
614 | #define OPCODE_TST 8 | |
615 | #define OPCODE_TEQ 9 | |
616 | #define OPCODE_CMP 10 | |
617 | #define OPCODE_CMN 11 | |
618 | #define OPCODE_ORR 12 | |
619 | #define OPCODE_MOV 13 | |
620 | #define OPCODE_BIC 14 | |
621 | #define OPCODE_MVN 15 | |
90e4755a | 622 | |
ef8d22e6 PB |
623 | #define T2_OPCODE_AND 0 |
624 | #define T2_OPCODE_BIC 1 | |
625 | #define T2_OPCODE_ORR 2 | |
626 | #define T2_OPCODE_ORN 3 | |
627 | #define T2_OPCODE_EOR 4 | |
628 | #define T2_OPCODE_ADD 8 | |
629 | #define T2_OPCODE_ADC 10 | |
630 | #define T2_OPCODE_SBC 11 | |
631 | #define T2_OPCODE_SUB 13 | |
632 | #define T2_OPCODE_RSB 14 | |
633 | ||
a737bd4d NC |
634 | #define T_OPCODE_MUL 0x4340 |
635 | #define T_OPCODE_TST 0x4200 | |
636 | #define T_OPCODE_CMN 0x42c0 | |
637 | #define T_OPCODE_NEG 0x4240 | |
638 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 639 | |
a737bd4d NC |
640 | #define T_OPCODE_ADD_R3 0x1800 |
641 | #define T_OPCODE_SUB_R3 0x1a00 | |
642 | #define T_OPCODE_ADD_HI 0x4400 | |
643 | #define T_OPCODE_ADD_ST 0xb000 | |
644 | #define T_OPCODE_SUB_ST 0xb080 | |
645 | #define T_OPCODE_ADD_SP 0xa800 | |
646 | #define T_OPCODE_ADD_PC 0xa000 | |
647 | #define T_OPCODE_ADD_I8 0x3000 | |
648 | #define T_OPCODE_SUB_I8 0x3800 | |
649 | #define T_OPCODE_ADD_I3 0x1c00 | |
650 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 651 | |
a737bd4d NC |
652 | #define T_OPCODE_ASR_R 0x4100 |
653 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
654 | #define T_OPCODE_LSR_R 0x40c0 |
655 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
656 | #define T_OPCODE_ASR_I 0x1000 |
657 | #define T_OPCODE_LSL_I 0x0000 | |
658 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 659 | |
a737bd4d NC |
660 | #define T_OPCODE_MOV_I8 0x2000 |
661 | #define T_OPCODE_CMP_I8 0x2800 | |
662 | #define T_OPCODE_CMP_LR 0x4280 | |
663 | #define T_OPCODE_MOV_HR 0x4600 | |
664 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 665 | |
a737bd4d NC |
666 | #define T_OPCODE_LDR_PC 0x4800 |
667 | #define T_OPCODE_LDR_SP 0x9800 | |
668 | #define T_OPCODE_STR_SP 0x9000 | |
669 | #define T_OPCODE_LDR_IW 0x6800 | |
670 | #define T_OPCODE_STR_IW 0x6000 | |
671 | #define T_OPCODE_LDR_IH 0x8800 | |
672 | #define T_OPCODE_STR_IH 0x8000 | |
673 | #define T_OPCODE_LDR_IB 0x7800 | |
674 | #define T_OPCODE_STR_IB 0x7000 | |
675 | #define T_OPCODE_LDR_RW 0x5800 | |
676 | #define T_OPCODE_STR_RW 0x5000 | |
677 | #define T_OPCODE_LDR_RH 0x5a00 | |
678 | #define T_OPCODE_STR_RH 0x5200 | |
679 | #define T_OPCODE_LDR_RB 0x5c00 | |
680 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 681 | |
a737bd4d NC |
682 | #define T_OPCODE_PUSH 0xb400 |
683 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 684 | |
2fc8bdac | 685 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 686 | |
a737bd4d | 687 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 688 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 689 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 690 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 ZW |
691 | |
692 | #define BAD_ARGS _("bad arguments to instruction") | |
fdfde340 | 693 | #define BAD_SP _("r13 not allowed here") |
c19d1205 ZW |
694 | #define BAD_PC _("r15 not allowed here") |
695 | #define BAD_COND _("instruction cannot be conditional") | |
696 | #define BAD_OVERLAP _("registers may not be the same") | |
697 | #define BAD_HIREG _("lo register required") | |
698 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
01cfc07f | 699 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); |
dfa9f0d5 PB |
700 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
701 | #define BAD_NOT_IT _("instruction not allowed in IT block") | |
037e8744 | 702 | #define BAD_FPU _("selected FPU does not support instruction") |
e07e6e58 NC |
703 | #define BAD_OUT_IT _("thumb conditional instruction should be in IT block") |
704 | #define BAD_IT_COND _("incorrect condition in IT block") | |
705 | #define BAD_IT_IT _("IT falling in the range of a previous IT block") | |
921e5f0a | 706 | #define MISSING_FNSTART _("missing .fnstart before unwinding directive") |
5be8be5d DG |
707 | #define BAD_PC_ADDRESSING \ |
708 | _("cannot use register index with PC-relative addressing") | |
709 | #define BAD_PC_WRITEBACK \ | |
710 | _("cannot use writeback with PC-relative addressing") | |
c19d1205 | 711 | |
c921be7d NC |
712 | static struct hash_control * arm_ops_hsh; |
713 | static struct hash_control * arm_cond_hsh; | |
714 | static struct hash_control * arm_shift_hsh; | |
715 | static struct hash_control * arm_psr_hsh; | |
716 | static struct hash_control * arm_v7m_psr_hsh; | |
717 | static struct hash_control * arm_reg_hsh; | |
718 | static struct hash_control * arm_reloc_hsh; | |
719 | static struct hash_control * arm_barrier_opt_hsh; | |
b99bd4ef | 720 | |
b99bd4ef NC |
721 | /* Stuff needed to resolve the label ambiguity |
722 | As: | |
723 | ... | |
724 | label: <insn> | |
725 | may differ from: | |
726 | ... | |
727 | label: | |
5f4273c7 | 728 | <insn> */ |
b99bd4ef NC |
729 | |
730 | symbolS * last_label_seen; | |
b34976b6 | 731 | static int label_is_thumb_function_name = FALSE; |
e07e6e58 | 732 | |
3d0c9500 NC |
733 | /* Literal pool structure. Held on a per-section |
734 | and per-sub-section basis. */ | |
a737bd4d | 735 | |
c19d1205 | 736 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 737 | typedef struct literal_pool |
b99bd4ef | 738 | { |
c921be7d NC |
739 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
740 | unsigned int next_free_entry; | |
741 | unsigned int id; | |
742 | symbolS * symbol; | |
743 | segT section; | |
744 | subsegT sub_section; | |
745 | struct literal_pool * next; | |
3d0c9500 | 746 | } literal_pool; |
b99bd4ef | 747 | |
3d0c9500 NC |
748 | /* Pointer to a linked list of literal pools. */ |
749 | literal_pool * list_of_pools = NULL; | |
e27ec89e | 750 | |
e07e6e58 NC |
751 | #ifdef OBJ_ELF |
752 | # define now_it seg_info (now_seg)->tc_segment_info_data.current_it | |
753 | #else | |
754 | static struct current_it now_it; | |
755 | #endif | |
756 | ||
757 | static inline int | |
758 | now_it_compatible (int cond) | |
759 | { | |
760 | return (cond & ~1) == (now_it.cc & ~1); | |
761 | } | |
762 | ||
763 | static inline int | |
764 | conditional_insn (void) | |
765 | { | |
766 | return inst.cond != COND_ALWAYS; | |
767 | } | |
768 | ||
769 | static int in_it_block (void); | |
770 | ||
771 | static int handle_it_state (void); | |
772 | ||
773 | static void force_automatic_it_block_close (void); | |
774 | ||
c921be7d NC |
775 | static void it_fsm_post_encode (void); |
776 | ||
e07e6e58 NC |
777 | #define set_it_insn_type(type) \ |
778 | do \ | |
779 | { \ | |
780 | inst.it_insn_type = type; \ | |
781 | if (handle_it_state () == FAIL) \ | |
782 | return; \ | |
783 | } \ | |
784 | while (0) | |
785 | ||
c921be7d NC |
786 | #define set_it_insn_type_nonvoid(type, failret) \ |
787 | do \ | |
788 | { \ | |
789 | inst.it_insn_type = type; \ | |
790 | if (handle_it_state () == FAIL) \ | |
791 | return failret; \ | |
792 | } \ | |
793 | while(0) | |
794 | ||
e07e6e58 NC |
795 | #define set_it_insn_type_last() \ |
796 | do \ | |
797 | { \ | |
798 | if (inst.cond == COND_ALWAYS) \ | |
799 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \ | |
800 | else \ | |
801 | set_it_insn_type (INSIDE_IT_LAST_INSN); \ | |
802 | } \ | |
803 | while (0) | |
804 | ||
c19d1205 | 805 | /* Pure syntax. */ |
b99bd4ef | 806 | |
c19d1205 ZW |
807 | /* This array holds the chars that always start a comment. If the |
808 | pre-processor is disabled, these aren't very useful. */ | |
809 | const char comment_chars[] = "@"; | |
3d0c9500 | 810 | |
c19d1205 ZW |
811 | /* This array holds the chars that only start a comment at the beginning of |
812 | a line. If the line seems to have the form '# 123 filename' | |
813 | .line and .file directives will appear in the pre-processed output. */ | |
814 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
815 | first line of the input file. This is because the compiler outputs | |
816 | #NO_APP at the beginning of its output. */ | |
817 | /* Also note that comments like this one will always work. */ | |
818 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 819 | |
c19d1205 | 820 | const char line_separator_chars[] = ";"; |
b99bd4ef | 821 | |
c19d1205 ZW |
822 | /* Chars that can be used to separate mant |
823 | from exp in floating point numbers. */ | |
824 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 825 | |
c19d1205 ZW |
826 | /* Chars that mean this number is a floating point constant. */ |
827 | /* As in 0f12.456 */ | |
828 | /* or 0d1.2345e12 */ | |
b99bd4ef | 829 | |
c19d1205 | 830 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 831 | |
c19d1205 ZW |
832 | /* Prefix characters that indicate the start of an immediate |
833 | value. */ | |
834 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 835 | |
c19d1205 ZW |
836 | /* Separator character handling. */ |
837 | ||
838 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
839 | ||
840 | static inline int | |
841 | skip_past_char (char ** str, char c) | |
842 | { | |
843 | if (**str == c) | |
844 | { | |
845 | (*str)++; | |
846 | return SUCCESS; | |
3d0c9500 | 847 | } |
c19d1205 ZW |
848 | else |
849 | return FAIL; | |
850 | } | |
c921be7d | 851 | |
c19d1205 | 852 | #define skip_past_comma(str) skip_past_char (str, ',') |
3d0c9500 | 853 | |
c19d1205 ZW |
854 | /* Arithmetic expressions (possibly involving symbols). */ |
855 | ||
856 | /* Return TRUE if anything in the expression is a bignum. */ | |
857 | ||
858 | static int | |
859 | walk_no_bignums (symbolS * sp) | |
860 | { | |
861 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
862 | return 1; | |
863 | ||
864 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 865 | { |
c19d1205 ZW |
866 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
867 | || (symbol_get_value_expression (sp)->X_op_symbol | |
868 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
869 | } |
870 | ||
c19d1205 | 871 | return 0; |
3d0c9500 NC |
872 | } |
873 | ||
c19d1205 ZW |
874 | static int in_my_get_expression = 0; |
875 | ||
876 | /* Third argument to my_get_expression. */ | |
877 | #define GE_NO_PREFIX 0 | |
878 | #define GE_IMM_PREFIX 1 | |
879 | #define GE_OPT_PREFIX 2 | |
5287ad62 JB |
880 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
881 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ | |
882 | #define GE_OPT_PREFIX_BIG 3 | |
a737bd4d | 883 | |
b99bd4ef | 884 | static int |
c19d1205 | 885 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 886 | { |
c19d1205 ZW |
887 | char * save_in; |
888 | segT seg; | |
b99bd4ef | 889 | |
c19d1205 ZW |
890 | /* In unified syntax, all prefixes are optional. */ |
891 | if (unified_syntax) | |
5287ad62 JB |
892 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
893 | : GE_OPT_PREFIX; | |
b99bd4ef | 894 | |
c19d1205 | 895 | switch (prefix_mode) |
b99bd4ef | 896 | { |
c19d1205 ZW |
897 | case GE_NO_PREFIX: break; |
898 | case GE_IMM_PREFIX: | |
899 | if (!is_immediate_prefix (**str)) | |
900 | { | |
901 | inst.error = _("immediate expression requires a # prefix"); | |
902 | return FAIL; | |
903 | } | |
904 | (*str)++; | |
905 | break; | |
906 | case GE_OPT_PREFIX: | |
5287ad62 | 907 | case GE_OPT_PREFIX_BIG: |
c19d1205 ZW |
908 | if (is_immediate_prefix (**str)) |
909 | (*str)++; | |
910 | break; | |
911 | default: abort (); | |
912 | } | |
b99bd4ef | 913 | |
c19d1205 | 914 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 915 | |
c19d1205 ZW |
916 | save_in = input_line_pointer; |
917 | input_line_pointer = *str; | |
918 | in_my_get_expression = 1; | |
919 | seg = expression (ep); | |
920 | in_my_get_expression = 0; | |
921 | ||
f86adc07 | 922 | if (ep->X_op == O_illegal || ep->X_op == O_absent) |
b99bd4ef | 923 | { |
f86adc07 | 924 | /* We found a bad or missing expression in md_operand(). */ |
c19d1205 ZW |
925 | *str = input_line_pointer; |
926 | input_line_pointer = save_in; | |
927 | if (inst.error == NULL) | |
f86adc07 NS |
928 | inst.error = (ep->X_op == O_absent |
929 | ? _("missing expression") :_("bad expression")); | |
c19d1205 ZW |
930 | return 1; |
931 | } | |
b99bd4ef | 932 | |
c19d1205 ZW |
933 | #ifdef OBJ_AOUT |
934 | if (seg != absolute_section | |
935 | && seg != text_section | |
936 | && seg != data_section | |
937 | && seg != bss_section | |
938 | && seg != undefined_section) | |
939 | { | |
940 | inst.error = _("bad segment"); | |
941 | *str = input_line_pointer; | |
942 | input_line_pointer = save_in; | |
943 | return 1; | |
b99bd4ef | 944 | } |
c19d1205 | 945 | #endif |
b99bd4ef | 946 | |
c19d1205 ZW |
947 | /* Get rid of any bignums now, so that we don't generate an error for which |
948 | we can't establish a line number later on. Big numbers are never valid | |
949 | in instructions, which is where this routine is always called. */ | |
5287ad62 JB |
950 | if (prefix_mode != GE_OPT_PREFIX_BIG |
951 | && (ep->X_op == O_big | |
952 | || (ep->X_add_symbol | |
953 | && (walk_no_bignums (ep->X_add_symbol) | |
954 | || (ep->X_op_symbol | |
955 | && walk_no_bignums (ep->X_op_symbol)))))) | |
c19d1205 ZW |
956 | { |
957 | inst.error = _("invalid constant"); | |
958 | *str = input_line_pointer; | |
959 | input_line_pointer = save_in; | |
960 | return 1; | |
961 | } | |
b99bd4ef | 962 | |
c19d1205 ZW |
963 | *str = input_line_pointer; |
964 | input_line_pointer = save_in; | |
965 | return 0; | |
b99bd4ef NC |
966 | } |
967 | ||
c19d1205 ZW |
968 | /* Turn a string in input_line_pointer into a floating point constant |
969 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
970 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
971 | returned, or NULL on OK. | |
b99bd4ef | 972 | |
c19d1205 ZW |
973 | Note that fp constants aren't represent in the normal way on the ARM. |
974 | In big endian mode, things are as expected. However, in little endian | |
975 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
976 | within the words. For example, (double) 1.1 in big endian mode is | |
977 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
978 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 979 | |
c19d1205 | 980 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 981 | |
c19d1205 ZW |
982 | char * |
983 | md_atof (int type, char * litP, int * sizeP) | |
984 | { | |
985 | int prec; | |
986 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
987 | char *t; | |
988 | int i; | |
b99bd4ef | 989 | |
c19d1205 ZW |
990 | switch (type) |
991 | { | |
992 | case 'f': | |
993 | case 'F': | |
994 | case 's': | |
995 | case 'S': | |
996 | prec = 2; | |
997 | break; | |
b99bd4ef | 998 | |
c19d1205 ZW |
999 | case 'd': |
1000 | case 'D': | |
1001 | case 'r': | |
1002 | case 'R': | |
1003 | prec = 4; | |
1004 | break; | |
b99bd4ef | 1005 | |
c19d1205 ZW |
1006 | case 'x': |
1007 | case 'X': | |
499ac353 | 1008 | prec = 5; |
c19d1205 | 1009 | break; |
b99bd4ef | 1010 | |
c19d1205 ZW |
1011 | case 'p': |
1012 | case 'P': | |
499ac353 | 1013 | prec = 5; |
c19d1205 | 1014 | break; |
a737bd4d | 1015 | |
c19d1205 ZW |
1016 | default: |
1017 | *sizeP = 0; | |
499ac353 | 1018 | return _("Unrecognized or unsupported floating point constant"); |
c19d1205 | 1019 | } |
b99bd4ef | 1020 | |
c19d1205 ZW |
1021 | t = atof_ieee (input_line_pointer, type, words); |
1022 | if (t) | |
1023 | input_line_pointer = t; | |
499ac353 | 1024 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
b99bd4ef | 1025 | |
c19d1205 ZW |
1026 | if (target_big_endian) |
1027 | { | |
1028 | for (i = 0; i < prec; i++) | |
1029 | { | |
499ac353 NC |
1030 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1031 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1032 | } |
1033 | } | |
1034 | else | |
1035 | { | |
e74cfd16 | 1036 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
1037 | for (i = prec - 1; i >= 0; i--) |
1038 | { | |
499ac353 NC |
1039 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1040 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1041 | } |
1042 | else | |
1043 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
1044 | For an 8 byte float the order is 1 0 3 2. */ | |
1045 | for (i = 0; i < prec; i += 2) | |
1046 | { | |
499ac353 NC |
1047 | md_number_to_chars (litP, (valueT) words[i + 1], |
1048 | sizeof (LITTLENUM_TYPE)); | |
1049 | md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), | |
1050 | (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1051 | litP += 2 * sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1052 | } |
1053 | } | |
b99bd4ef | 1054 | |
499ac353 | 1055 | return NULL; |
c19d1205 | 1056 | } |
b99bd4ef | 1057 | |
c19d1205 ZW |
1058 | /* We handle all bad expressions here, so that we can report the faulty |
1059 | instruction in the error message. */ | |
1060 | void | |
91d6fa6a | 1061 | md_operand (expressionS * exp) |
c19d1205 ZW |
1062 | { |
1063 | if (in_my_get_expression) | |
91d6fa6a | 1064 | exp->X_op = O_illegal; |
b99bd4ef NC |
1065 | } |
1066 | ||
c19d1205 | 1067 | /* Immediate values. */ |
b99bd4ef | 1068 | |
c19d1205 ZW |
1069 | /* Generic immediate-value read function for use in directives. |
1070 | Accepts anything that 'expression' can fold to a constant. | |
1071 | *val receives the number. */ | |
1072 | #ifdef OBJ_ELF | |
1073 | static int | |
1074 | immediate_for_directive (int *val) | |
b99bd4ef | 1075 | { |
c19d1205 ZW |
1076 | expressionS exp; |
1077 | exp.X_op = O_illegal; | |
b99bd4ef | 1078 | |
c19d1205 ZW |
1079 | if (is_immediate_prefix (*input_line_pointer)) |
1080 | { | |
1081 | input_line_pointer++; | |
1082 | expression (&exp); | |
1083 | } | |
b99bd4ef | 1084 | |
c19d1205 ZW |
1085 | if (exp.X_op != O_constant) |
1086 | { | |
1087 | as_bad (_("expected #constant")); | |
1088 | ignore_rest_of_line (); | |
1089 | return FAIL; | |
1090 | } | |
1091 | *val = exp.X_add_number; | |
1092 | return SUCCESS; | |
b99bd4ef | 1093 | } |
c19d1205 | 1094 | #endif |
b99bd4ef | 1095 | |
c19d1205 | 1096 | /* Register parsing. */ |
b99bd4ef | 1097 | |
c19d1205 ZW |
1098 | /* Generic register parser. CCP points to what should be the |
1099 | beginning of a register name. If it is indeed a valid register | |
1100 | name, advance CCP over it and return the reg_entry structure; | |
1101 | otherwise return NULL. Does not issue diagnostics. */ | |
1102 | ||
1103 | static struct reg_entry * | |
1104 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 1105 | { |
c19d1205 ZW |
1106 | char *start = *ccp; |
1107 | char *p; | |
1108 | struct reg_entry *reg; | |
b99bd4ef | 1109 | |
c19d1205 ZW |
1110 | #ifdef REGISTER_PREFIX |
1111 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 1112 | return NULL; |
c19d1205 ZW |
1113 | start++; |
1114 | #endif | |
1115 | #ifdef OPTIONAL_REGISTER_PREFIX | |
1116 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
1117 | start++; | |
1118 | #endif | |
b99bd4ef | 1119 | |
c19d1205 ZW |
1120 | p = start; |
1121 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
1122 | return NULL; | |
b99bd4ef | 1123 | |
c19d1205 ZW |
1124 | do |
1125 | p++; | |
1126 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
1127 | ||
1128 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
1129 | ||
1130 | if (!reg) | |
1131 | return NULL; | |
1132 | ||
1133 | *ccp = p; | |
1134 | return reg; | |
b99bd4ef NC |
1135 | } |
1136 | ||
1137 | static int | |
dcbf9037 JB |
1138 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
1139 | enum arm_reg_type type) | |
b99bd4ef | 1140 | { |
c19d1205 ZW |
1141 | /* Alternative syntaxes are accepted for a few register classes. */ |
1142 | switch (type) | |
1143 | { | |
1144 | case REG_TYPE_MVF: | |
1145 | case REG_TYPE_MVD: | |
1146 | case REG_TYPE_MVFX: | |
1147 | case REG_TYPE_MVDX: | |
1148 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 1149 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
1150 | return reg->number; |
1151 | break; | |
69b97547 | 1152 | |
c19d1205 ZW |
1153 | case REG_TYPE_CP: |
1154 | /* For backward compatibility, a bare number is valid here. */ | |
1155 | { | |
1156 | unsigned long processor = strtoul (start, ccp, 10); | |
1157 | if (*ccp != start && processor <= 15) | |
1158 | return processor; | |
1159 | } | |
6057a28f | 1160 | |
c19d1205 ZW |
1161 | case REG_TYPE_MMXWC: |
1162 | /* WC includes WCG. ??? I'm not sure this is true for all | |
1163 | instructions that take WC registers. */ | |
79134647 | 1164 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 1165 | return reg->number; |
6057a28f | 1166 | break; |
c19d1205 | 1167 | |
6057a28f | 1168 | default: |
c19d1205 | 1169 | break; |
6057a28f NC |
1170 | } |
1171 | ||
dcbf9037 JB |
1172 | return FAIL; |
1173 | } | |
1174 | ||
1175 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the | |
1176 | return value is the register number or FAIL. */ | |
1177 | ||
1178 | static int | |
1179 | arm_reg_parse (char **ccp, enum arm_reg_type type) | |
1180 | { | |
1181 | char *start = *ccp; | |
1182 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
1183 | int ret; | |
1184 | ||
1185 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1186 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) | |
1187 | return FAIL; | |
1188 | ||
1189 | if (reg && reg->type == type) | |
1190 | return reg->number; | |
1191 | ||
1192 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) | |
1193 | return ret; | |
1194 | ||
c19d1205 ZW |
1195 | *ccp = start; |
1196 | return FAIL; | |
1197 | } | |
69b97547 | 1198 | |
dcbf9037 JB |
1199 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
1200 | character. Does no verification at this stage that the type fits the opcode | |
1201 | properly. E.g., | |
1202 | ||
1203 | .i32.i32.s16 | |
1204 | .s32.f32 | |
1205 | .u16 | |
1206 | ||
1207 | Can all be legally parsed by this function. | |
1208 | ||
1209 | Fills in neon_type struct pointer with parsed information, and updates STR | |
1210 | to point after the parsed type specifier. Returns SUCCESS if this was a legal | |
1211 | type, FAIL if not. */ | |
1212 | ||
1213 | static int | |
1214 | parse_neon_type (struct neon_type *type, char **str) | |
1215 | { | |
1216 | char *ptr = *str; | |
1217 | ||
1218 | if (type) | |
1219 | type->elems = 0; | |
1220 | ||
1221 | while (type->elems < NEON_MAX_TYPE_ELS) | |
1222 | { | |
1223 | enum neon_el_type thistype = NT_untyped; | |
1224 | unsigned thissize = -1u; | |
1225 | ||
1226 | if (*ptr != '.') | |
1227 | break; | |
1228 | ||
1229 | ptr++; | |
1230 | ||
1231 | /* Just a size without an explicit type. */ | |
1232 | if (ISDIGIT (*ptr)) | |
1233 | goto parsesize; | |
1234 | ||
1235 | switch (TOLOWER (*ptr)) | |
1236 | { | |
1237 | case 'i': thistype = NT_integer; break; | |
1238 | case 'f': thistype = NT_float; break; | |
1239 | case 'p': thistype = NT_poly; break; | |
1240 | case 's': thistype = NT_signed; break; | |
1241 | case 'u': thistype = NT_unsigned; break; | |
037e8744 JB |
1242 | case 'd': |
1243 | thistype = NT_float; | |
1244 | thissize = 64; | |
1245 | ptr++; | |
1246 | goto done; | |
dcbf9037 JB |
1247 | default: |
1248 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); | |
1249 | return FAIL; | |
1250 | } | |
1251 | ||
1252 | ptr++; | |
1253 | ||
1254 | /* .f is an abbreviation for .f32. */ | |
1255 | if (thistype == NT_float && !ISDIGIT (*ptr)) | |
1256 | thissize = 32; | |
1257 | else | |
1258 | { | |
1259 | parsesize: | |
1260 | thissize = strtoul (ptr, &ptr, 10); | |
1261 | ||
1262 | if (thissize != 8 && thissize != 16 && thissize != 32 | |
1263 | && thissize != 64) | |
1264 | { | |
1265 | as_bad (_("bad size %d in type specifier"), thissize); | |
1266 | return FAIL; | |
1267 | } | |
1268 | } | |
1269 | ||
037e8744 | 1270 | done: |
dcbf9037 JB |
1271 | if (type) |
1272 | { | |
1273 | type->el[type->elems].type = thistype; | |
1274 | type->el[type->elems].size = thissize; | |
1275 | type->elems++; | |
1276 | } | |
1277 | } | |
1278 | ||
1279 | /* Empty/missing type is not a successful parse. */ | |
1280 | if (type->elems == 0) | |
1281 | return FAIL; | |
1282 | ||
1283 | *str = ptr; | |
1284 | ||
1285 | return SUCCESS; | |
1286 | } | |
1287 | ||
1288 | /* Errors may be set multiple times during parsing or bit encoding | |
1289 | (particularly in the Neon bits), but usually the earliest error which is set | |
1290 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
1291 | errors by calling this function. */ | |
1292 | ||
1293 | static void | |
1294 | first_error (const char *err) | |
1295 | { | |
1296 | if (!inst.error) | |
1297 | inst.error = err; | |
1298 | } | |
1299 | ||
1300 | /* Parse a single type, e.g. ".s32", leading period included. */ | |
1301 | static int | |
1302 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) | |
1303 | { | |
1304 | char *str = *ccp; | |
1305 | struct neon_type optype; | |
1306 | ||
1307 | if (*str == '.') | |
1308 | { | |
1309 | if (parse_neon_type (&optype, &str) == SUCCESS) | |
1310 | { | |
1311 | if (optype.elems == 1) | |
1312 | *vectype = optype.el[0]; | |
1313 | else | |
1314 | { | |
1315 | first_error (_("only one type should be specified for operand")); | |
1316 | return FAIL; | |
1317 | } | |
1318 | } | |
1319 | else | |
1320 | { | |
1321 | first_error (_("vector type expected")); | |
1322 | return FAIL; | |
1323 | } | |
1324 | } | |
1325 | else | |
1326 | return FAIL; | |
5f4273c7 | 1327 | |
dcbf9037 | 1328 | *ccp = str; |
5f4273c7 | 1329 | |
dcbf9037 JB |
1330 | return SUCCESS; |
1331 | } | |
1332 | ||
1333 | /* Special meanings for indices (which have a range of 0-7), which will fit into | |
1334 | a 4-bit integer. */ | |
1335 | ||
1336 | #define NEON_ALL_LANES 15 | |
1337 | #define NEON_INTERLEAVE_LANES 14 | |
1338 | ||
1339 | /* Parse either a register or a scalar, with an optional type. Return the | |
1340 | register number, and optionally fill in the actual type of the register | |
1341 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and | |
1342 | type/index information in *TYPEINFO. */ | |
1343 | ||
1344 | static int | |
1345 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, | |
1346 | enum arm_reg_type *rtype, | |
1347 | struct neon_typed_alias *typeinfo) | |
1348 | { | |
1349 | char *str = *ccp; | |
1350 | struct reg_entry *reg = arm_reg_parse_multi (&str); | |
1351 | struct neon_typed_alias atype; | |
1352 | struct neon_type_el parsetype; | |
1353 | ||
1354 | atype.defined = 0; | |
1355 | atype.index = -1; | |
1356 | atype.eltype.type = NT_invtype; | |
1357 | atype.eltype.size = -1; | |
1358 | ||
1359 | /* Try alternate syntax for some types of register. Note these are mutually | |
1360 | exclusive with the Neon syntax extensions. */ | |
1361 | if (reg == NULL) | |
1362 | { | |
1363 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); | |
1364 | if (altreg != FAIL) | |
1365 | *ccp = str; | |
1366 | if (typeinfo) | |
1367 | *typeinfo = atype; | |
1368 | return altreg; | |
1369 | } | |
1370 | ||
037e8744 JB |
1371 | /* Undo polymorphism when a set of register types may be accepted. */ |
1372 | if ((type == REG_TYPE_NDQ | |
1373 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) | |
1374 | || (type == REG_TYPE_VFSD | |
1375 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) | |
1376 | || (type == REG_TYPE_NSDQ | |
1377 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD | |
f512f76f NC |
1378 | || reg->type == REG_TYPE_NQ)) |
1379 | || (type == REG_TYPE_MMXWC | |
1380 | && (reg->type == REG_TYPE_MMXWCG))) | |
21d799b5 | 1381 | type = (enum arm_reg_type) reg->type; |
dcbf9037 JB |
1382 | |
1383 | if (type != reg->type) | |
1384 | return FAIL; | |
1385 | ||
1386 | if (reg->neon) | |
1387 | atype = *reg->neon; | |
5f4273c7 | 1388 | |
dcbf9037 JB |
1389 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) |
1390 | { | |
1391 | if ((atype.defined & NTA_HASTYPE) != 0) | |
1392 | { | |
1393 | first_error (_("can't redefine type for operand")); | |
1394 | return FAIL; | |
1395 | } | |
1396 | atype.defined |= NTA_HASTYPE; | |
1397 | atype.eltype = parsetype; | |
1398 | } | |
5f4273c7 | 1399 | |
dcbf9037 JB |
1400 | if (skip_past_char (&str, '[') == SUCCESS) |
1401 | { | |
1402 | if (type != REG_TYPE_VFD) | |
1403 | { | |
1404 | first_error (_("only D registers may be indexed")); | |
1405 | return FAIL; | |
1406 | } | |
5f4273c7 | 1407 | |
dcbf9037 JB |
1408 | if ((atype.defined & NTA_HASINDEX) != 0) |
1409 | { | |
1410 | first_error (_("can't change index for operand")); | |
1411 | return FAIL; | |
1412 | } | |
1413 | ||
1414 | atype.defined |= NTA_HASINDEX; | |
1415 | ||
1416 | if (skip_past_char (&str, ']') == SUCCESS) | |
1417 | atype.index = NEON_ALL_LANES; | |
1418 | else | |
1419 | { | |
1420 | expressionS exp; | |
1421 | ||
1422 | my_get_expression (&exp, &str, GE_NO_PREFIX); | |
1423 | ||
1424 | if (exp.X_op != O_constant) | |
1425 | { | |
1426 | first_error (_("constant expression required")); | |
1427 | return FAIL; | |
1428 | } | |
1429 | ||
1430 | if (skip_past_char (&str, ']') == FAIL) | |
1431 | return FAIL; | |
1432 | ||
1433 | atype.index = exp.X_add_number; | |
1434 | } | |
1435 | } | |
5f4273c7 | 1436 | |
dcbf9037 JB |
1437 | if (typeinfo) |
1438 | *typeinfo = atype; | |
5f4273c7 | 1439 | |
dcbf9037 JB |
1440 | if (rtype) |
1441 | *rtype = type; | |
5f4273c7 | 1442 | |
dcbf9037 | 1443 | *ccp = str; |
5f4273c7 | 1444 | |
dcbf9037 JB |
1445 | return reg->number; |
1446 | } | |
1447 | ||
1448 | /* Like arm_reg_parse, but allow allow the following extra features: | |
1449 | - If RTYPE is non-zero, return the (possibly restricted) type of the | |
1450 | register (e.g. Neon double or quad reg when either has been requested). | |
1451 | - If this is a Neon vector type with additional type information, fill | |
1452 | in the struct pointed to by VECTYPE (if non-NULL). | |
5f4273c7 | 1453 | This function will fault on encountering a scalar. */ |
dcbf9037 JB |
1454 | |
1455 | static int | |
1456 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, | |
1457 | enum arm_reg_type *rtype, struct neon_type_el *vectype) | |
1458 | { | |
1459 | struct neon_typed_alias atype; | |
1460 | char *str = *ccp; | |
1461 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); | |
1462 | ||
1463 | if (reg == FAIL) | |
1464 | return FAIL; | |
1465 | ||
1466 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1467 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1468 | { | |
1469 | first_error (_("register operand expected, but got scalar")); | |
1470 | return FAIL; | |
1471 | } | |
1472 | ||
1473 | if (vectype) | |
1474 | *vectype = atype.eltype; | |
1475 | ||
1476 | *ccp = str; | |
1477 | ||
1478 | return reg; | |
1479 | } | |
1480 | ||
1481 | #define NEON_SCALAR_REG(X) ((X) >> 4) | |
1482 | #define NEON_SCALAR_INDEX(X) ((X) & 15) | |
1483 | ||
5287ad62 JB |
1484 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
1485 | have enough information to be able to do a good job bounds-checking. So, we | |
1486 | just do easy checks here, and do further checks later. */ | |
1487 | ||
1488 | static int | |
dcbf9037 | 1489 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type) |
5287ad62 | 1490 | { |
dcbf9037 | 1491 | int reg; |
5287ad62 | 1492 | char *str = *ccp; |
dcbf9037 | 1493 | struct neon_typed_alias atype; |
5f4273c7 | 1494 | |
dcbf9037 | 1495 | reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); |
5f4273c7 | 1496 | |
dcbf9037 | 1497 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
5287ad62 | 1498 | return FAIL; |
5f4273c7 | 1499 | |
dcbf9037 | 1500 | if (atype.index == NEON_ALL_LANES) |
5287ad62 | 1501 | { |
dcbf9037 | 1502 | first_error (_("scalar must have an index")); |
5287ad62 JB |
1503 | return FAIL; |
1504 | } | |
dcbf9037 | 1505 | else if (atype.index >= 64 / elsize) |
5287ad62 | 1506 | { |
dcbf9037 | 1507 | first_error (_("scalar index out of range")); |
5287ad62 JB |
1508 | return FAIL; |
1509 | } | |
5f4273c7 | 1510 | |
dcbf9037 JB |
1511 | if (type) |
1512 | *type = atype.eltype; | |
5f4273c7 | 1513 | |
5287ad62 | 1514 | *ccp = str; |
5f4273c7 | 1515 | |
dcbf9037 | 1516 | return reg * 16 + atype.index; |
5287ad62 JB |
1517 | } |
1518 | ||
c19d1205 | 1519 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
e07e6e58 | 1520 | |
c19d1205 ZW |
1521 | static long |
1522 | parse_reg_list (char ** strp) | |
1523 | { | |
1524 | char * str = * strp; | |
1525 | long range = 0; | |
1526 | int another_range; | |
a737bd4d | 1527 | |
c19d1205 ZW |
1528 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
1529 | do | |
6057a28f | 1530 | { |
c19d1205 | 1531 | another_range = 0; |
a737bd4d | 1532 | |
c19d1205 ZW |
1533 | if (*str == '{') |
1534 | { | |
1535 | int in_range = 0; | |
1536 | int cur_reg = -1; | |
a737bd4d | 1537 | |
c19d1205 ZW |
1538 | str++; |
1539 | do | |
1540 | { | |
1541 | int reg; | |
6057a28f | 1542 | |
dcbf9037 | 1543 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
c19d1205 | 1544 | { |
dcbf9037 | 1545 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 ZW |
1546 | return FAIL; |
1547 | } | |
a737bd4d | 1548 | |
c19d1205 ZW |
1549 | if (in_range) |
1550 | { | |
1551 | int i; | |
a737bd4d | 1552 | |
c19d1205 ZW |
1553 | if (reg <= cur_reg) |
1554 | { | |
dcbf9037 | 1555 | first_error (_("bad range in register list")); |
c19d1205 ZW |
1556 | return FAIL; |
1557 | } | |
40a18ebd | 1558 | |
c19d1205 ZW |
1559 | for (i = cur_reg + 1; i < reg; i++) |
1560 | { | |
1561 | if (range & (1 << i)) | |
1562 | as_tsktsk | |
1563 | (_("Warning: duplicated register (r%d) in register list"), | |
1564 | i); | |
1565 | else | |
1566 | range |= 1 << i; | |
1567 | } | |
1568 | in_range = 0; | |
1569 | } | |
a737bd4d | 1570 | |
c19d1205 ZW |
1571 | if (range & (1 << reg)) |
1572 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1573 | reg); | |
1574 | else if (reg <= cur_reg) | |
1575 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1576 | |
c19d1205 ZW |
1577 | range |= 1 << reg; |
1578 | cur_reg = reg; | |
1579 | } | |
1580 | while (skip_past_comma (&str) != FAIL | |
1581 | || (in_range = 1, *str++ == '-')); | |
1582 | str--; | |
a737bd4d | 1583 | |
c19d1205 ZW |
1584 | if (*str++ != '}') |
1585 | { | |
dcbf9037 | 1586 | first_error (_("missing `}'")); |
c19d1205 ZW |
1587 | return FAIL; |
1588 | } | |
1589 | } | |
1590 | else | |
1591 | { | |
91d6fa6a | 1592 | expressionS exp; |
40a18ebd | 1593 | |
91d6fa6a | 1594 | if (my_get_expression (&exp, &str, GE_NO_PREFIX)) |
c19d1205 | 1595 | return FAIL; |
40a18ebd | 1596 | |
91d6fa6a | 1597 | if (exp.X_op == O_constant) |
c19d1205 | 1598 | { |
91d6fa6a NC |
1599 | if (exp.X_add_number |
1600 | != (exp.X_add_number & 0x0000ffff)) | |
c19d1205 ZW |
1601 | { |
1602 | inst.error = _("invalid register mask"); | |
1603 | return FAIL; | |
1604 | } | |
a737bd4d | 1605 | |
91d6fa6a | 1606 | if ((range & exp.X_add_number) != 0) |
c19d1205 | 1607 | { |
91d6fa6a | 1608 | int regno = range & exp.X_add_number; |
a737bd4d | 1609 | |
c19d1205 ZW |
1610 | regno &= -regno; |
1611 | regno = (1 << regno) - 1; | |
1612 | as_tsktsk | |
1613 | (_("Warning: duplicated register (r%d) in register list"), | |
1614 | regno); | |
1615 | } | |
a737bd4d | 1616 | |
91d6fa6a | 1617 | range |= exp.X_add_number; |
c19d1205 ZW |
1618 | } |
1619 | else | |
1620 | { | |
1621 | if (inst.reloc.type != 0) | |
1622 | { | |
1623 | inst.error = _("expression too complex"); | |
1624 | return FAIL; | |
1625 | } | |
a737bd4d | 1626 | |
91d6fa6a | 1627 | memcpy (&inst.reloc.exp, &exp, sizeof (expressionS)); |
c19d1205 ZW |
1628 | inst.reloc.type = BFD_RELOC_ARM_MULTI; |
1629 | inst.reloc.pc_rel = 0; | |
1630 | } | |
1631 | } | |
a737bd4d | 1632 | |
c19d1205 ZW |
1633 | if (*str == '|' || *str == '+') |
1634 | { | |
1635 | str++; | |
1636 | another_range = 1; | |
1637 | } | |
a737bd4d | 1638 | } |
c19d1205 | 1639 | while (another_range); |
a737bd4d | 1640 | |
c19d1205 ZW |
1641 | *strp = str; |
1642 | return range; | |
a737bd4d NC |
1643 | } |
1644 | ||
5287ad62 JB |
1645 | /* Types of registers in a list. */ |
1646 | ||
1647 | enum reg_list_els | |
1648 | { | |
1649 | REGLIST_VFP_S, | |
1650 | REGLIST_VFP_D, | |
1651 | REGLIST_NEON_D | |
1652 | }; | |
1653 | ||
c19d1205 ZW |
1654 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1655 | Otherwise return the number of registers, and set PBASE to the first | |
5287ad62 JB |
1656 | register. Parses registers of type ETYPE. |
1657 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: | |
1658 | - Q registers can be used to specify pairs of D registers | |
1659 | - { } can be omitted from around a singleton register list | |
1660 | FIXME: This is not implemented, as it would require backtracking in | |
1661 | some cases, e.g.: | |
1662 | vtbl.8 d3,d4,d5 | |
1663 | This could be done (the meaning isn't really ambiguous), but doesn't | |
1664 | fit in well with the current parsing framework. | |
dcbf9037 JB |
1665 | - 32 D registers may be used (also true for VFPv3). |
1666 | FIXME: Types are ignored in these register lists, which is probably a | |
1667 | bug. */ | |
6057a28f | 1668 | |
c19d1205 | 1669 | static int |
037e8744 | 1670 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) |
6057a28f | 1671 | { |
037e8744 | 1672 | char *str = *ccp; |
c19d1205 ZW |
1673 | int base_reg; |
1674 | int new_base; | |
21d799b5 | 1675 | enum arm_reg_type regtype = (enum arm_reg_type) 0; |
5287ad62 | 1676 | int max_regs = 0; |
c19d1205 ZW |
1677 | int count = 0; |
1678 | int warned = 0; | |
1679 | unsigned long mask = 0; | |
a737bd4d | 1680 | int i; |
6057a28f | 1681 | |
037e8744 | 1682 | if (*str != '{') |
5287ad62 JB |
1683 | { |
1684 | inst.error = _("expecting {"); | |
1685 | return FAIL; | |
1686 | } | |
6057a28f | 1687 | |
037e8744 | 1688 | str++; |
6057a28f | 1689 | |
5287ad62 | 1690 | switch (etype) |
c19d1205 | 1691 | { |
5287ad62 | 1692 | case REGLIST_VFP_S: |
c19d1205 ZW |
1693 | regtype = REG_TYPE_VFS; |
1694 | max_regs = 32; | |
5287ad62 | 1695 | break; |
5f4273c7 | 1696 | |
5287ad62 JB |
1697 | case REGLIST_VFP_D: |
1698 | regtype = REG_TYPE_VFD; | |
b7fc2769 | 1699 | break; |
5f4273c7 | 1700 | |
b7fc2769 JB |
1701 | case REGLIST_NEON_D: |
1702 | regtype = REG_TYPE_NDQ; | |
1703 | break; | |
1704 | } | |
1705 | ||
1706 | if (etype != REGLIST_VFP_S) | |
1707 | { | |
b1cc4aeb PB |
1708 | /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ |
1709 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) | |
5287ad62 JB |
1710 | { |
1711 | max_regs = 32; | |
1712 | if (thumb_mode) | |
1713 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 1714 | fpu_vfp_ext_d32); |
5287ad62 JB |
1715 | else |
1716 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 1717 | fpu_vfp_ext_d32); |
5287ad62 JB |
1718 | } |
1719 | else | |
1720 | max_regs = 16; | |
c19d1205 | 1721 | } |
6057a28f | 1722 | |
c19d1205 | 1723 | base_reg = max_regs; |
a737bd4d | 1724 | |
c19d1205 ZW |
1725 | do |
1726 | { | |
5287ad62 | 1727 | int setmask = 1, addregs = 1; |
dcbf9037 | 1728 | |
037e8744 | 1729 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
dcbf9037 | 1730 | |
c19d1205 | 1731 | if (new_base == FAIL) |
a737bd4d | 1732 | { |
dcbf9037 | 1733 | first_error (_(reg_expected_msgs[regtype])); |
c19d1205 ZW |
1734 | return FAIL; |
1735 | } | |
5f4273c7 | 1736 | |
b7fc2769 JB |
1737 | if (new_base >= max_regs) |
1738 | { | |
1739 | first_error (_("register out of range in list")); | |
1740 | return FAIL; | |
1741 | } | |
5f4273c7 | 1742 | |
5287ad62 JB |
1743 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
1744 | if (regtype == REG_TYPE_NQ) | |
1745 | { | |
1746 | setmask = 3; | |
1747 | addregs = 2; | |
1748 | } | |
1749 | ||
c19d1205 ZW |
1750 | if (new_base < base_reg) |
1751 | base_reg = new_base; | |
a737bd4d | 1752 | |
5287ad62 | 1753 | if (mask & (setmask << new_base)) |
c19d1205 | 1754 | { |
dcbf9037 | 1755 | first_error (_("invalid register list")); |
c19d1205 | 1756 | return FAIL; |
a737bd4d | 1757 | } |
a737bd4d | 1758 | |
c19d1205 ZW |
1759 | if ((mask >> new_base) != 0 && ! warned) |
1760 | { | |
1761 | as_tsktsk (_("register list not in ascending order")); | |
1762 | warned = 1; | |
1763 | } | |
0bbf2aa4 | 1764 | |
5287ad62 JB |
1765 | mask |= setmask << new_base; |
1766 | count += addregs; | |
0bbf2aa4 | 1767 | |
037e8744 | 1768 | if (*str == '-') /* We have the start of a range expression */ |
c19d1205 ZW |
1769 | { |
1770 | int high_range; | |
0bbf2aa4 | 1771 | |
037e8744 | 1772 | str++; |
0bbf2aa4 | 1773 | |
037e8744 | 1774 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
dcbf9037 | 1775 | == FAIL) |
c19d1205 ZW |
1776 | { |
1777 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1778 | return FAIL; | |
1779 | } | |
0bbf2aa4 | 1780 | |
b7fc2769 JB |
1781 | if (high_range >= max_regs) |
1782 | { | |
1783 | first_error (_("register out of range in list")); | |
1784 | return FAIL; | |
1785 | } | |
1786 | ||
5287ad62 JB |
1787 | if (regtype == REG_TYPE_NQ) |
1788 | high_range = high_range + 1; | |
1789 | ||
c19d1205 ZW |
1790 | if (high_range <= new_base) |
1791 | { | |
1792 | inst.error = _("register range not in ascending order"); | |
1793 | return FAIL; | |
1794 | } | |
0bbf2aa4 | 1795 | |
5287ad62 | 1796 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
0bbf2aa4 | 1797 | { |
5287ad62 | 1798 | if (mask & (setmask << new_base)) |
0bbf2aa4 | 1799 | { |
c19d1205 ZW |
1800 | inst.error = _("invalid register list"); |
1801 | return FAIL; | |
0bbf2aa4 | 1802 | } |
c19d1205 | 1803 | |
5287ad62 JB |
1804 | mask |= setmask << new_base; |
1805 | count += addregs; | |
0bbf2aa4 | 1806 | } |
0bbf2aa4 | 1807 | } |
0bbf2aa4 | 1808 | } |
037e8744 | 1809 | while (skip_past_comma (&str) != FAIL); |
0bbf2aa4 | 1810 | |
037e8744 | 1811 | str++; |
0bbf2aa4 | 1812 | |
c19d1205 ZW |
1813 | /* Sanity check -- should have raised a parse error above. */ |
1814 | if (count == 0 || count > max_regs) | |
1815 | abort (); | |
1816 | ||
1817 | *pbase = base_reg; | |
1818 | ||
1819 | /* Final test -- the registers must be consecutive. */ | |
1820 | mask >>= base_reg; | |
1821 | for (i = 0; i < count; i++) | |
1822 | { | |
1823 | if ((mask & (1u << i)) == 0) | |
1824 | { | |
1825 | inst.error = _("non-contiguous register range"); | |
1826 | return FAIL; | |
1827 | } | |
1828 | } | |
1829 | ||
037e8744 JB |
1830 | *ccp = str; |
1831 | ||
c19d1205 | 1832 | return count; |
b99bd4ef NC |
1833 | } |
1834 | ||
dcbf9037 JB |
1835 | /* True if two alias types are the same. */ |
1836 | ||
c921be7d | 1837 | static bfd_boolean |
dcbf9037 JB |
1838 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) |
1839 | { | |
1840 | if (!a && !b) | |
c921be7d | 1841 | return TRUE; |
5f4273c7 | 1842 | |
dcbf9037 | 1843 | if (!a || !b) |
c921be7d | 1844 | return FALSE; |
dcbf9037 JB |
1845 | |
1846 | if (a->defined != b->defined) | |
c921be7d | 1847 | return FALSE; |
5f4273c7 | 1848 | |
dcbf9037 JB |
1849 | if ((a->defined & NTA_HASTYPE) != 0 |
1850 | && (a->eltype.type != b->eltype.type | |
1851 | || a->eltype.size != b->eltype.size)) | |
c921be7d | 1852 | return FALSE; |
dcbf9037 JB |
1853 | |
1854 | if ((a->defined & NTA_HASINDEX) != 0 | |
1855 | && (a->index != b->index)) | |
c921be7d | 1856 | return FALSE; |
5f4273c7 | 1857 | |
c921be7d | 1858 | return TRUE; |
dcbf9037 JB |
1859 | } |
1860 | ||
5287ad62 JB |
1861 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
1862 | The base register is put in *PBASE. | |
dcbf9037 | 1863 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
5287ad62 JB |
1864 | the return value. |
1865 | The register stride (minus one) is put in bit 4 of the return value. | |
dcbf9037 JB |
1866 | Bits [6:5] encode the list length (minus one). |
1867 | The type of the list elements is put in *ELTYPE, if non-NULL. */ | |
5287ad62 | 1868 | |
5287ad62 | 1869 | #define NEON_LANE(X) ((X) & 0xf) |
dcbf9037 | 1870 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
5287ad62 JB |
1871 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
1872 | ||
1873 | static int | |
dcbf9037 JB |
1874 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
1875 | struct neon_type_el *eltype) | |
5287ad62 JB |
1876 | { |
1877 | char *ptr = *str; | |
1878 | int base_reg = -1; | |
1879 | int reg_incr = -1; | |
1880 | int count = 0; | |
1881 | int lane = -1; | |
1882 | int leading_brace = 0; | |
1883 | enum arm_reg_type rtype = REG_TYPE_NDQ; | |
1884 | int addregs = 1; | |
20203fb9 NC |
1885 | const char *const incr_error = _("register stride must be 1 or 2"); |
1886 | const char *const type_error = _("mismatched element/structure types in list"); | |
dcbf9037 | 1887 | struct neon_typed_alias firsttype; |
5f4273c7 | 1888 | |
5287ad62 JB |
1889 | if (skip_past_char (&ptr, '{') == SUCCESS) |
1890 | leading_brace = 1; | |
5f4273c7 | 1891 | |
5287ad62 JB |
1892 | do |
1893 | { | |
dcbf9037 JB |
1894 | struct neon_typed_alias atype; |
1895 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); | |
1896 | ||
5287ad62 JB |
1897 | if (getreg == FAIL) |
1898 | { | |
dcbf9037 | 1899 | first_error (_(reg_expected_msgs[rtype])); |
5287ad62 JB |
1900 | return FAIL; |
1901 | } | |
5f4273c7 | 1902 | |
5287ad62 JB |
1903 | if (base_reg == -1) |
1904 | { | |
1905 | base_reg = getreg; | |
1906 | if (rtype == REG_TYPE_NQ) | |
1907 | { | |
1908 | reg_incr = 1; | |
1909 | addregs = 2; | |
1910 | } | |
dcbf9037 | 1911 | firsttype = atype; |
5287ad62 JB |
1912 | } |
1913 | else if (reg_incr == -1) | |
1914 | { | |
1915 | reg_incr = getreg - base_reg; | |
1916 | if (reg_incr < 1 || reg_incr > 2) | |
1917 | { | |
dcbf9037 | 1918 | first_error (_(incr_error)); |
5287ad62 JB |
1919 | return FAIL; |
1920 | } | |
1921 | } | |
1922 | else if (getreg != base_reg + reg_incr * count) | |
1923 | { | |
dcbf9037 JB |
1924 | first_error (_(incr_error)); |
1925 | return FAIL; | |
1926 | } | |
1927 | ||
c921be7d | 1928 | if (! neon_alias_types_same (&atype, &firsttype)) |
dcbf9037 JB |
1929 | { |
1930 | first_error (_(type_error)); | |
5287ad62 JB |
1931 | return FAIL; |
1932 | } | |
5f4273c7 | 1933 | |
5287ad62 JB |
1934 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list |
1935 | modes. */ | |
1936 | if (ptr[0] == '-') | |
1937 | { | |
dcbf9037 | 1938 | struct neon_typed_alias htype; |
5287ad62 JB |
1939 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; |
1940 | if (lane == -1) | |
1941 | lane = NEON_INTERLEAVE_LANES; | |
1942 | else if (lane != NEON_INTERLEAVE_LANES) | |
1943 | { | |
dcbf9037 | 1944 | first_error (_(type_error)); |
5287ad62 JB |
1945 | return FAIL; |
1946 | } | |
1947 | if (reg_incr == -1) | |
1948 | reg_incr = 1; | |
1949 | else if (reg_incr != 1) | |
1950 | { | |
dcbf9037 | 1951 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); |
5287ad62 JB |
1952 | return FAIL; |
1953 | } | |
1954 | ptr++; | |
dcbf9037 | 1955 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); |
5287ad62 JB |
1956 | if (hireg == FAIL) |
1957 | { | |
dcbf9037 JB |
1958 | first_error (_(reg_expected_msgs[rtype])); |
1959 | return FAIL; | |
1960 | } | |
c921be7d | 1961 | if (! neon_alias_types_same (&htype, &firsttype)) |
dcbf9037 JB |
1962 | { |
1963 | first_error (_(type_error)); | |
5287ad62 JB |
1964 | return FAIL; |
1965 | } | |
1966 | count += hireg + dregs - getreg; | |
1967 | continue; | |
1968 | } | |
5f4273c7 | 1969 | |
5287ad62 JB |
1970 | /* If we're using Q registers, we can't use [] or [n] syntax. */ |
1971 | if (rtype == REG_TYPE_NQ) | |
1972 | { | |
1973 | count += 2; | |
1974 | continue; | |
1975 | } | |
5f4273c7 | 1976 | |
dcbf9037 | 1977 | if ((atype.defined & NTA_HASINDEX) != 0) |
5287ad62 | 1978 | { |
dcbf9037 JB |
1979 | if (lane == -1) |
1980 | lane = atype.index; | |
1981 | else if (lane != atype.index) | |
5287ad62 | 1982 | { |
dcbf9037 JB |
1983 | first_error (_(type_error)); |
1984 | return FAIL; | |
5287ad62 JB |
1985 | } |
1986 | } | |
1987 | else if (lane == -1) | |
1988 | lane = NEON_INTERLEAVE_LANES; | |
1989 | else if (lane != NEON_INTERLEAVE_LANES) | |
1990 | { | |
dcbf9037 | 1991 | first_error (_(type_error)); |
5287ad62 JB |
1992 | return FAIL; |
1993 | } | |
1994 | count++; | |
1995 | } | |
1996 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); | |
5f4273c7 | 1997 | |
5287ad62 JB |
1998 | /* No lane set by [x]. We must be interleaving structures. */ |
1999 | if (lane == -1) | |
2000 | lane = NEON_INTERLEAVE_LANES; | |
5f4273c7 | 2001 | |
5287ad62 JB |
2002 | /* Sanity check. */ |
2003 | if (lane == -1 || base_reg == -1 || count < 1 || count > 4 | |
2004 | || (count > 1 && reg_incr == -1)) | |
2005 | { | |
dcbf9037 | 2006 | first_error (_("error parsing element/structure list")); |
5287ad62 JB |
2007 | return FAIL; |
2008 | } | |
2009 | ||
2010 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) | |
2011 | { | |
dcbf9037 | 2012 | first_error (_("expected }")); |
5287ad62 JB |
2013 | return FAIL; |
2014 | } | |
5f4273c7 | 2015 | |
5287ad62 JB |
2016 | if (reg_incr == -1) |
2017 | reg_incr = 1; | |
2018 | ||
dcbf9037 JB |
2019 | if (eltype) |
2020 | *eltype = firsttype.eltype; | |
2021 | ||
5287ad62 JB |
2022 | *pbase = base_reg; |
2023 | *str = ptr; | |
5f4273c7 | 2024 | |
5287ad62 JB |
2025 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); |
2026 | } | |
2027 | ||
c19d1205 ZW |
2028 | /* Parse an explicit relocation suffix on an expression. This is |
2029 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
2030 | arm_reloc_hsh contains no entries, so this function can only | |
2031 | succeed if there is no () after the word. Returns -1 on error, | |
2032 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
2033 | static int | |
2034 | parse_reloc (char **str) | |
b99bd4ef | 2035 | { |
c19d1205 ZW |
2036 | struct reloc_entry *r; |
2037 | char *p, *q; | |
b99bd4ef | 2038 | |
c19d1205 ZW |
2039 | if (**str != '(') |
2040 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 2041 | |
c19d1205 ZW |
2042 | p = *str + 1; |
2043 | q = p; | |
2044 | ||
2045 | while (*q && *q != ')' && *q != ',') | |
2046 | q++; | |
2047 | if (*q != ')') | |
2048 | return -1; | |
2049 | ||
21d799b5 NC |
2050 | if ((r = (struct reloc_entry *) |
2051 | hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
c19d1205 ZW |
2052 | return -1; |
2053 | ||
2054 | *str = q + 1; | |
2055 | return r->reloc; | |
b99bd4ef NC |
2056 | } |
2057 | ||
c19d1205 ZW |
2058 | /* Directives: register aliases. */ |
2059 | ||
dcbf9037 | 2060 | static struct reg_entry * |
c19d1205 | 2061 | insert_reg_alias (char *str, int number, int type) |
b99bd4ef | 2062 | { |
d3ce72d0 | 2063 | struct reg_entry *new_reg; |
c19d1205 | 2064 | const char *name; |
b99bd4ef | 2065 | |
d3ce72d0 | 2066 | if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) |
c19d1205 | 2067 | { |
d3ce72d0 | 2068 | if (new_reg->builtin) |
c19d1205 | 2069 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); |
b99bd4ef | 2070 | |
c19d1205 ZW |
2071 | /* Only warn about a redefinition if it's not defined as the |
2072 | same register. */ | |
d3ce72d0 | 2073 | else if (new_reg->number != number || new_reg->type != type) |
c19d1205 | 2074 | as_warn (_("ignoring redefinition of register alias '%s'"), str); |
69b97547 | 2075 | |
d929913e | 2076 | return NULL; |
c19d1205 | 2077 | } |
b99bd4ef | 2078 | |
c19d1205 | 2079 | name = xstrdup (str); |
d3ce72d0 | 2080 | new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry)); |
b99bd4ef | 2081 | |
d3ce72d0 NC |
2082 | new_reg->name = name; |
2083 | new_reg->number = number; | |
2084 | new_reg->type = type; | |
2085 | new_reg->builtin = FALSE; | |
2086 | new_reg->neon = NULL; | |
b99bd4ef | 2087 | |
d3ce72d0 | 2088 | if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) |
c19d1205 | 2089 | abort (); |
5f4273c7 | 2090 | |
d3ce72d0 | 2091 | return new_reg; |
dcbf9037 JB |
2092 | } |
2093 | ||
2094 | static void | |
2095 | insert_neon_reg_alias (char *str, int number, int type, | |
2096 | struct neon_typed_alias *atype) | |
2097 | { | |
2098 | struct reg_entry *reg = insert_reg_alias (str, number, type); | |
5f4273c7 | 2099 | |
dcbf9037 JB |
2100 | if (!reg) |
2101 | { | |
2102 | first_error (_("attempt to redefine typed alias")); | |
2103 | return; | |
2104 | } | |
5f4273c7 | 2105 | |
dcbf9037 JB |
2106 | if (atype) |
2107 | { | |
21d799b5 NC |
2108 | reg->neon = (struct neon_typed_alias *) |
2109 | xmalloc (sizeof (struct neon_typed_alias)); | |
dcbf9037 JB |
2110 | *reg->neon = *atype; |
2111 | } | |
c19d1205 | 2112 | } |
b99bd4ef | 2113 | |
c19d1205 | 2114 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 2115 | |
c19d1205 | 2116 | new_register_name .req existing_register_name |
b99bd4ef | 2117 | |
c19d1205 | 2118 | If we find one, or if it looks sufficiently like one that we want to |
d929913e | 2119 | handle any error here, return TRUE. Otherwise return FALSE. */ |
b99bd4ef | 2120 | |
d929913e | 2121 | static bfd_boolean |
c19d1205 ZW |
2122 | create_register_alias (char * newname, char *p) |
2123 | { | |
2124 | struct reg_entry *old; | |
2125 | char *oldname, *nbuf; | |
2126 | size_t nlen; | |
b99bd4ef | 2127 | |
c19d1205 ZW |
2128 | /* The input scrubber ensures that whitespace after the mnemonic is |
2129 | collapsed to single spaces. */ | |
2130 | oldname = p; | |
2131 | if (strncmp (oldname, " .req ", 6) != 0) | |
d929913e | 2132 | return FALSE; |
b99bd4ef | 2133 | |
c19d1205 ZW |
2134 | oldname += 6; |
2135 | if (*oldname == '\0') | |
d929913e | 2136 | return FALSE; |
b99bd4ef | 2137 | |
21d799b5 | 2138 | old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname); |
c19d1205 | 2139 | if (!old) |
b99bd4ef | 2140 | { |
c19d1205 | 2141 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
d929913e | 2142 | return TRUE; |
b99bd4ef NC |
2143 | } |
2144 | ||
c19d1205 ZW |
2145 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2146 | the desired alias name, and p points to its end. If not, then | |
2147 | the desired alias name is in the global original_case_string. */ | |
2148 | #ifdef TC_CASE_SENSITIVE | |
2149 | nlen = p - newname; | |
2150 | #else | |
2151 | newname = original_case_string; | |
2152 | nlen = strlen (newname); | |
2153 | #endif | |
b99bd4ef | 2154 | |
21d799b5 | 2155 | nbuf = (char *) alloca (nlen + 1); |
c19d1205 ZW |
2156 | memcpy (nbuf, newname, nlen); |
2157 | nbuf[nlen] = '\0'; | |
b99bd4ef | 2158 | |
c19d1205 ZW |
2159 | /* Create aliases under the new name as stated; an all-lowercase |
2160 | version of the new name; and an all-uppercase version of the new | |
2161 | name. */ | |
d929913e NC |
2162 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) |
2163 | { | |
2164 | for (p = nbuf; *p; p++) | |
2165 | *p = TOUPPER (*p); | |
c19d1205 | 2166 | |
d929913e NC |
2167 | if (strncmp (nbuf, newname, nlen)) |
2168 | { | |
2169 | /* If this attempt to create an additional alias fails, do not bother | |
2170 | trying to create the all-lower case alias. We will fail and issue | |
2171 | a second, duplicate error message. This situation arises when the | |
2172 | programmer does something like: | |
2173 | foo .req r0 | |
2174 | Foo .req r1 | |
2175 | The second .req creates the "Foo" alias but then fails to create | |
5f4273c7 | 2176 | the artificial FOO alias because it has already been created by the |
d929913e NC |
2177 | first .req. */ |
2178 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
2179 | return TRUE; | |
2180 | } | |
c19d1205 | 2181 | |
d929913e NC |
2182 | for (p = nbuf; *p; p++) |
2183 | *p = TOLOWER (*p); | |
c19d1205 | 2184 | |
d929913e NC |
2185 | if (strncmp (nbuf, newname, nlen)) |
2186 | insert_reg_alias (nbuf, old->number, old->type); | |
2187 | } | |
c19d1205 | 2188 | |
d929913e | 2189 | return TRUE; |
b99bd4ef NC |
2190 | } |
2191 | ||
dcbf9037 JB |
2192 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
2193 | X .dn d5.s32[1] | |
2194 | Y .qn 6.s16 | |
2195 | Z .dn d7 | |
2196 | T .dn Z[0] | |
2197 | These typed registers can be used instead of the types specified after the | |
2198 | Neon mnemonic, so long as all operands given have types. Types can also be | |
2199 | specified directly, e.g.: | |
5f4273c7 | 2200 | vadd d0.s32, d1.s32, d2.s32 */ |
dcbf9037 | 2201 | |
c921be7d | 2202 | static bfd_boolean |
dcbf9037 JB |
2203 | create_neon_reg_alias (char *newname, char *p) |
2204 | { | |
2205 | enum arm_reg_type basetype; | |
2206 | struct reg_entry *basereg; | |
2207 | struct reg_entry mybasereg; | |
2208 | struct neon_type ntype; | |
2209 | struct neon_typed_alias typeinfo; | |
2210 | char *namebuf, *nameend; | |
2211 | int namelen; | |
5f4273c7 | 2212 | |
dcbf9037 JB |
2213 | typeinfo.defined = 0; |
2214 | typeinfo.eltype.type = NT_invtype; | |
2215 | typeinfo.eltype.size = -1; | |
2216 | typeinfo.index = -1; | |
5f4273c7 | 2217 | |
dcbf9037 | 2218 | nameend = p; |
5f4273c7 | 2219 | |
dcbf9037 JB |
2220 | if (strncmp (p, " .dn ", 5) == 0) |
2221 | basetype = REG_TYPE_VFD; | |
2222 | else if (strncmp (p, " .qn ", 5) == 0) | |
2223 | basetype = REG_TYPE_NQ; | |
2224 | else | |
c921be7d | 2225 | return FALSE; |
5f4273c7 | 2226 | |
dcbf9037 | 2227 | p += 5; |
5f4273c7 | 2228 | |
dcbf9037 | 2229 | if (*p == '\0') |
c921be7d | 2230 | return FALSE; |
5f4273c7 | 2231 | |
dcbf9037 JB |
2232 | basereg = arm_reg_parse_multi (&p); |
2233 | ||
2234 | if (basereg && basereg->type != basetype) | |
2235 | { | |
2236 | as_bad (_("bad type for register")); | |
c921be7d | 2237 | return FALSE; |
dcbf9037 JB |
2238 | } |
2239 | ||
2240 | if (basereg == NULL) | |
2241 | { | |
2242 | expressionS exp; | |
2243 | /* Try parsing as an integer. */ | |
2244 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2245 | if (exp.X_op != O_constant) | |
2246 | { | |
2247 | as_bad (_("expression must be constant")); | |
c921be7d | 2248 | return FALSE; |
dcbf9037 JB |
2249 | } |
2250 | basereg = &mybasereg; | |
2251 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 | |
2252 | : exp.X_add_number; | |
2253 | basereg->neon = 0; | |
2254 | } | |
2255 | ||
2256 | if (basereg->neon) | |
2257 | typeinfo = *basereg->neon; | |
2258 | ||
2259 | if (parse_neon_type (&ntype, &p) == SUCCESS) | |
2260 | { | |
2261 | /* We got a type. */ | |
2262 | if (typeinfo.defined & NTA_HASTYPE) | |
2263 | { | |
2264 | as_bad (_("can't redefine the type of a register alias")); | |
c921be7d | 2265 | return FALSE; |
dcbf9037 | 2266 | } |
5f4273c7 | 2267 | |
dcbf9037 JB |
2268 | typeinfo.defined |= NTA_HASTYPE; |
2269 | if (ntype.elems != 1) | |
2270 | { | |
2271 | as_bad (_("you must specify a single type only")); | |
c921be7d | 2272 | return FALSE; |
dcbf9037 JB |
2273 | } |
2274 | typeinfo.eltype = ntype.el[0]; | |
2275 | } | |
5f4273c7 | 2276 | |
dcbf9037 JB |
2277 | if (skip_past_char (&p, '[') == SUCCESS) |
2278 | { | |
2279 | expressionS exp; | |
2280 | /* We got a scalar index. */ | |
5f4273c7 | 2281 | |
dcbf9037 JB |
2282 | if (typeinfo.defined & NTA_HASINDEX) |
2283 | { | |
2284 | as_bad (_("can't redefine the index of a scalar alias")); | |
c921be7d | 2285 | return FALSE; |
dcbf9037 | 2286 | } |
5f4273c7 | 2287 | |
dcbf9037 | 2288 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
5f4273c7 | 2289 | |
dcbf9037 JB |
2290 | if (exp.X_op != O_constant) |
2291 | { | |
2292 | as_bad (_("scalar index must be constant")); | |
c921be7d | 2293 | return FALSE; |
dcbf9037 | 2294 | } |
5f4273c7 | 2295 | |
dcbf9037 JB |
2296 | typeinfo.defined |= NTA_HASINDEX; |
2297 | typeinfo.index = exp.X_add_number; | |
5f4273c7 | 2298 | |
dcbf9037 JB |
2299 | if (skip_past_char (&p, ']') == FAIL) |
2300 | { | |
2301 | as_bad (_("expecting ]")); | |
c921be7d | 2302 | return FALSE; |
dcbf9037 JB |
2303 | } |
2304 | } | |
2305 | ||
2306 | namelen = nameend - newname; | |
21d799b5 | 2307 | namebuf = (char *) alloca (namelen + 1); |
dcbf9037 JB |
2308 | strncpy (namebuf, newname, namelen); |
2309 | namebuf[namelen] = '\0'; | |
5f4273c7 | 2310 | |
dcbf9037 JB |
2311 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
2312 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2313 | |
dcbf9037 JB |
2314 | /* Insert name in all uppercase. */ |
2315 | for (p = namebuf; *p; p++) | |
2316 | *p = TOUPPER (*p); | |
5f4273c7 | 2317 | |
dcbf9037 JB |
2318 | if (strncmp (namebuf, newname, namelen)) |
2319 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2320 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2321 | |
dcbf9037 JB |
2322 | /* Insert name in all lowercase. */ |
2323 | for (p = namebuf; *p; p++) | |
2324 | *p = TOLOWER (*p); | |
5f4273c7 | 2325 | |
dcbf9037 JB |
2326 | if (strncmp (namebuf, newname, namelen)) |
2327 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2328 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2329 | |
c921be7d | 2330 | return TRUE; |
dcbf9037 JB |
2331 | } |
2332 | ||
c19d1205 ZW |
2333 | /* Should never be called, as .req goes between the alias and the |
2334 | register name, not at the beginning of the line. */ | |
c921be7d | 2335 | |
b99bd4ef | 2336 | static void |
c19d1205 | 2337 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2338 | { |
c19d1205 ZW |
2339 | as_bad (_("invalid syntax for .req directive")); |
2340 | } | |
b99bd4ef | 2341 | |
dcbf9037 JB |
2342 | static void |
2343 | s_dn (int a ATTRIBUTE_UNUSED) | |
2344 | { | |
2345 | as_bad (_("invalid syntax for .dn directive")); | |
2346 | } | |
2347 | ||
2348 | static void | |
2349 | s_qn (int a ATTRIBUTE_UNUSED) | |
2350 | { | |
2351 | as_bad (_("invalid syntax for .qn directive")); | |
2352 | } | |
2353 | ||
c19d1205 ZW |
2354 | /* The .unreq directive deletes an alias which was previously defined |
2355 | by .req. For example: | |
b99bd4ef | 2356 | |
c19d1205 ZW |
2357 | my_alias .req r11 |
2358 | .unreq my_alias */ | |
b99bd4ef NC |
2359 | |
2360 | static void | |
c19d1205 | 2361 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2362 | { |
c19d1205 ZW |
2363 | char * name; |
2364 | char saved_char; | |
b99bd4ef | 2365 | |
c19d1205 ZW |
2366 | name = input_line_pointer; |
2367 | ||
2368 | while (*input_line_pointer != 0 | |
2369 | && *input_line_pointer != ' ' | |
2370 | && *input_line_pointer != '\n') | |
2371 | ++input_line_pointer; | |
2372 | ||
2373 | saved_char = *input_line_pointer; | |
2374 | *input_line_pointer = 0; | |
2375 | ||
2376 | if (!*name) | |
2377 | as_bad (_("invalid syntax for .unreq directive")); | |
2378 | else | |
2379 | { | |
21d799b5 NC |
2380 | struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh, |
2381 | name); | |
c19d1205 ZW |
2382 | |
2383 | if (!reg) | |
2384 | as_bad (_("unknown register alias '%s'"), name); | |
2385 | else if (reg->builtin) | |
2386 | as_warn (_("ignoring attempt to undefine built-in register '%s'"), | |
2387 | name); | |
2388 | else | |
2389 | { | |
d929913e NC |
2390 | char * p; |
2391 | char * nbuf; | |
2392 | ||
db0bc284 | 2393 | hash_delete (arm_reg_hsh, name, FALSE); |
c19d1205 | 2394 | free ((char *) reg->name); |
dcbf9037 JB |
2395 | if (reg->neon) |
2396 | free (reg->neon); | |
c19d1205 | 2397 | free (reg); |
d929913e NC |
2398 | |
2399 | /* Also locate the all upper case and all lower case versions. | |
2400 | Do not complain if we cannot find one or the other as it | |
2401 | was probably deleted above. */ | |
5f4273c7 | 2402 | |
d929913e NC |
2403 | nbuf = strdup (name); |
2404 | for (p = nbuf; *p; p++) | |
2405 | *p = TOUPPER (*p); | |
21d799b5 | 2406 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2407 | if (reg) |
2408 | { | |
db0bc284 | 2409 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2410 | free ((char *) reg->name); |
2411 | if (reg->neon) | |
2412 | free (reg->neon); | |
2413 | free (reg); | |
2414 | } | |
2415 | ||
2416 | for (p = nbuf; *p; p++) | |
2417 | *p = TOLOWER (*p); | |
21d799b5 | 2418 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2419 | if (reg) |
2420 | { | |
db0bc284 | 2421 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2422 | free ((char *) reg->name); |
2423 | if (reg->neon) | |
2424 | free (reg->neon); | |
2425 | free (reg); | |
2426 | } | |
2427 | ||
2428 | free (nbuf); | |
c19d1205 ZW |
2429 | } |
2430 | } | |
b99bd4ef | 2431 | |
c19d1205 | 2432 | *input_line_pointer = saved_char; |
b99bd4ef NC |
2433 | demand_empty_rest_of_line (); |
2434 | } | |
2435 | ||
c19d1205 ZW |
2436 | /* Directives: Instruction set selection. */ |
2437 | ||
2438 | #ifdef OBJ_ELF | |
2439 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
2440 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
2441 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
2442 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
2443 | ||
cd000bff DJ |
2444 | /* Create a new mapping symbol for the transition to STATE. */ |
2445 | ||
2446 | static void | |
2447 | make_mapping_symbol (enum mstate state, valueT value, fragS *frag) | |
b99bd4ef | 2448 | { |
a737bd4d | 2449 | symbolS * symbolP; |
c19d1205 ZW |
2450 | const char * symname; |
2451 | int type; | |
b99bd4ef | 2452 | |
c19d1205 | 2453 | switch (state) |
b99bd4ef | 2454 | { |
c19d1205 ZW |
2455 | case MAP_DATA: |
2456 | symname = "$d"; | |
2457 | type = BSF_NO_FLAGS; | |
2458 | break; | |
2459 | case MAP_ARM: | |
2460 | symname = "$a"; | |
2461 | type = BSF_NO_FLAGS; | |
2462 | break; | |
2463 | case MAP_THUMB: | |
2464 | symname = "$t"; | |
2465 | type = BSF_NO_FLAGS; | |
2466 | break; | |
c19d1205 ZW |
2467 | default: |
2468 | abort (); | |
2469 | } | |
2470 | ||
cd000bff | 2471 | symbolP = symbol_new (symname, now_seg, value, frag); |
c19d1205 ZW |
2472 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; |
2473 | ||
2474 | switch (state) | |
2475 | { | |
2476 | case MAP_ARM: | |
2477 | THUMB_SET_FUNC (symbolP, 0); | |
2478 | ARM_SET_THUMB (symbolP, 0); | |
2479 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2480 | break; | |
2481 | ||
2482 | case MAP_THUMB: | |
2483 | THUMB_SET_FUNC (symbolP, 1); | |
2484 | ARM_SET_THUMB (symbolP, 1); | |
2485 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2486 | break; | |
2487 | ||
2488 | case MAP_DATA: | |
2489 | default: | |
cd000bff DJ |
2490 | break; |
2491 | } | |
2492 | ||
2493 | /* Save the mapping symbols for future reference. Also check that | |
2494 | we do not place two mapping symbols at the same offset within a | |
2495 | frag. We'll handle overlap between frags in | |
2de7820f JZ |
2496 | check_mapping_symbols. |
2497 | ||
2498 | If .fill or other data filling directive generates zero sized data, | |
2499 | the mapping symbol for the following code will have the same value | |
2500 | as the one generated for the data filling directive. In this case, | |
2501 | we replace the old symbol with the new one at the same address. */ | |
cd000bff DJ |
2502 | if (value == 0) |
2503 | { | |
2de7820f JZ |
2504 | if (frag->tc_frag_data.first_map != NULL) |
2505 | { | |
2506 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); | |
2507 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP); | |
2508 | } | |
cd000bff DJ |
2509 | frag->tc_frag_data.first_map = symbolP; |
2510 | } | |
2511 | if (frag->tc_frag_data.last_map != NULL) | |
0f020cef JZ |
2512 | { |
2513 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP)); | |
0f020cef JZ |
2514 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) |
2515 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP); | |
2516 | } | |
cd000bff DJ |
2517 | frag->tc_frag_data.last_map = symbolP; |
2518 | } | |
2519 | ||
2520 | /* We must sometimes convert a region marked as code to data during | |
2521 | code alignment, if an odd number of bytes have to be padded. The | |
2522 | code mapping symbol is pushed to an aligned address. */ | |
2523 | ||
2524 | static void | |
2525 | insert_data_mapping_symbol (enum mstate state, | |
2526 | valueT value, fragS *frag, offsetT bytes) | |
2527 | { | |
2528 | /* If there was already a mapping symbol, remove it. */ | |
2529 | if (frag->tc_frag_data.last_map != NULL | |
2530 | && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) | |
2531 | { | |
2532 | symbolS *symp = frag->tc_frag_data.last_map; | |
2533 | ||
2534 | if (value == 0) | |
2535 | { | |
2536 | know (frag->tc_frag_data.first_map == symp); | |
2537 | frag->tc_frag_data.first_map = NULL; | |
2538 | } | |
2539 | frag->tc_frag_data.last_map = NULL; | |
2540 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
c19d1205 | 2541 | } |
cd000bff DJ |
2542 | |
2543 | make_mapping_symbol (MAP_DATA, value, frag); | |
2544 | make_mapping_symbol (state, value + bytes, frag); | |
2545 | } | |
2546 | ||
2547 | static void mapping_state_2 (enum mstate state, int max_chars); | |
2548 | ||
2549 | /* Set the mapping state to STATE. Only call this when about to | |
2550 | emit some STATE bytes to the file. */ | |
2551 | ||
2552 | void | |
2553 | mapping_state (enum mstate state) | |
2554 | { | |
940b5ce0 DJ |
2555 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2556 | ||
cd000bff DJ |
2557 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
2558 | ||
2559 | if (mapstate == state) | |
2560 | /* The mapping symbol has already been emitted. | |
2561 | There is nothing else to do. */ | |
2562 | return; | |
2563 | else if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) | |
2564 | /* This case will be evaluated later in the next else. */ | |
2565 | return; | |
2566 | else if (TRANSITION (MAP_UNDEFINED, MAP_ARM) | |
2567 | || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) | |
2568 | { | |
2569 | /* Only add the symbol if the offset is > 0: | |
2570 | if we're at the first frag, check it's size > 0; | |
2571 | if we're not at the first frag, then for sure | |
2572 | the offset is > 0. */ | |
2573 | struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; | |
2574 | const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); | |
2575 | ||
2576 | if (add_symbol) | |
2577 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); | |
2578 | } | |
2579 | ||
2580 | mapping_state_2 (state, 0); | |
2581 | #undef TRANSITION | |
2582 | } | |
2583 | ||
2584 | /* Same as mapping_state, but MAX_CHARS bytes have already been | |
2585 | allocated. Put the mapping symbol that far back. */ | |
2586 | ||
2587 | static void | |
2588 | mapping_state_2 (enum mstate state, int max_chars) | |
2589 | { | |
940b5ce0 DJ |
2590 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2591 | ||
2592 | if (!SEG_NORMAL (now_seg)) | |
2593 | return; | |
2594 | ||
cd000bff DJ |
2595 | if (mapstate == state) |
2596 | /* The mapping symbol has already been emitted. | |
2597 | There is nothing else to do. */ | |
2598 | return; | |
2599 | ||
cd000bff DJ |
2600 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; |
2601 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); | |
c19d1205 ZW |
2602 | } |
2603 | #else | |
d3106081 NS |
2604 | #define mapping_state(x) ((void)0) |
2605 | #define mapping_state_2(x, y) ((void)0) | |
c19d1205 ZW |
2606 | #endif |
2607 | ||
2608 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
2609 | ||
4343666d | 2610 | #ifdef OBJ_COFF |
c19d1205 ZW |
2611 | static symbolS * |
2612 | find_real_start (symbolS * symbolP) | |
2613 | { | |
2614 | char * real_start; | |
2615 | const char * name = S_GET_NAME (symbolP); | |
2616 | symbolS * new_target; | |
2617 | ||
2618 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
2619 | #define STUB_NAME ".real_start_of" | |
2620 | ||
2621 | if (name == NULL) | |
2622 | abort (); | |
2623 | ||
37f6032b ZW |
2624 | /* The compiler may generate BL instructions to local labels because |
2625 | it needs to perform a branch to a far away location. These labels | |
2626 | do not have a corresponding ".real_start_of" label. We check | |
2627 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
2628 | the ".real_start_of" convention for nonlocal branches. */ | |
2629 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
2630 | return symbolP; |
2631 | ||
37f6032b | 2632 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
2633 | new_target = symbol_find (real_start); |
2634 | ||
2635 | if (new_target == NULL) | |
2636 | { | |
bd3ba5d1 | 2637 | as_warn (_("Failed to find real start of function: %s\n"), name); |
c19d1205 ZW |
2638 | new_target = symbolP; |
2639 | } | |
2640 | ||
c19d1205 ZW |
2641 | return new_target; |
2642 | } | |
4343666d | 2643 | #endif |
c19d1205 ZW |
2644 | |
2645 | static void | |
2646 | opcode_select (int width) | |
2647 | { | |
2648 | switch (width) | |
2649 | { | |
2650 | case 16: | |
2651 | if (! thumb_mode) | |
2652 | { | |
e74cfd16 | 2653 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
2654 | as_bad (_("selected processor does not support THUMB opcodes")); |
2655 | ||
2656 | thumb_mode = 1; | |
2657 | /* No need to force the alignment, since we will have been | |
2658 | coming from ARM mode, which is word-aligned. */ | |
2659 | record_alignment (now_seg, 1); | |
2660 | } | |
c19d1205 ZW |
2661 | break; |
2662 | ||
2663 | case 32: | |
2664 | if (thumb_mode) | |
2665 | { | |
e74cfd16 | 2666 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
2667 | as_bad (_("selected processor does not support ARM opcodes")); |
2668 | ||
2669 | thumb_mode = 0; | |
2670 | ||
2671 | if (!need_pass_2) | |
2672 | frag_align (2, 0, 0); | |
2673 | ||
2674 | record_alignment (now_seg, 1); | |
2675 | } | |
c19d1205 ZW |
2676 | break; |
2677 | ||
2678 | default: | |
2679 | as_bad (_("invalid instruction size selected (%d)"), width); | |
2680 | } | |
2681 | } | |
2682 | ||
2683 | static void | |
2684 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
2685 | { | |
2686 | opcode_select (32); | |
2687 | demand_empty_rest_of_line (); | |
2688 | } | |
2689 | ||
2690 | static void | |
2691 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
2692 | { | |
2693 | opcode_select (16); | |
2694 | demand_empty_rest_of_line (); | |
2695 | } | |
2696 | ||
2697 | static void | |
2698 | s_code (int unused ATTRIBUTE_UNUSED) | |
2699 | { | |
2700 | int temp; | |
2701 | ||
2702 | temp = get_absolute_expression (); | |
2703 | switch (temp) | |
2704 | { | |
2705 | case 16: | |
2706 | case 32: | |
2707 | opcode_select (temp); | |
2708 | break; | |
2709 | ||
2710 | default: | |
2711 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
2712 | } | |
2713 | } | |
2714 | ||
2715 | static void | |
2716 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
2717 | { | |
2718 | /* If we are not already in thumb mode go into it, EVEN if | |
2719 | the target processor does not support thumb instructions. | |
2720 | This is used by gcc/config/arm/lib1funcs.asm for example | |
2721 | to compile interworking support functions even if the | |
2722 | target processor should not support interworking. */ | |
2723 | if (! thumb_mode) | |
2724 | { | |
2725 | thumb_mode = 2; | |
2726 | record_alignment (now_seg, 1); | |
2727 | } | |
2728 | ||
2729 | demand_empty_rest_of_line (); | |
2730 | } | |
2731 | ||
2732 | static void | |
2733 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
2734 | { | |
2735 | s_thumb (0); | |
2736 | ||
2737 | /* The following label is the name/address of the start of a Thumb function. | |
2738 | We need to know this for the interworking support. */ | |
2739 | label_is_thumb_function_name = TRUE; | |
2740 | } | |
2741 | ||
2742 | /* Perform a .set directive, but also mark the alias as | |
2743 | being a thumb function. */ | |
2744 | ||
2745 | static void | |
2746 | s_thumb_set (int equiv) | |
2747 | { | |
2748 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
2749 | We cannot just call that code as we need to get at the symbol that | |
2750 | is created. */ | |
2751 | char * name; | |
2752 | char delim; | |
2753 | char * end_name; | |
2754 | symbolS * symbolP; | |
2755 | ||
2756 | /* Especial apologies for the random logic: | |
2757 | This just grew, and could be parsed much more simply! | |
2758 | Dean - in haste. */ | |
2759 | name = input_line_pointer; | |
2760 | delim = get_symbol_end (); | |
2761 | end_name = input_line_pointer; | |
2762 | *end_name = delim; | |
2763 | ||
2764 | if (*input_line_pointer != ',') | |
2765 | { | |
2766 | *end_name = 0; | |
2767 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
2768 | *end_name = delim; |
2769 | ignore_rest_of_line (); | |
2770 | return; | |
2771 | } | |
2772 | ||
2773 | input_line_pointer++; | |
2774 | *end_name = 0; | |
2775 | ||
2776 | if (name[0] == '.' && name[1] == '\0') | |
2777 | { | |
2778 | /* XXX - this should not happen to .thumb_set. */ | |
2779 | abort (); | |
2780 | } | |
2781 | ||
2782 | if ((symbolP = symbol_find (name)) == NULL | |
2783 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
2784 | { | |
2785 | #ifndef NO_LISTING | |
2786 | /* When doing symbol listings, play games with dummy fragments living | |
2787 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 2788 | for this symbol. */ |
b99bd4ef NC |
2789 | if (listing & LISTING_SYMBOLS) |
2790 | { | |
2791 | extern struct list_info_struct * listing_tail; | |
21d799b5 | 2792 | fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS)); |
b99bd4ef NC |
2793 | |
2794 | memset (dummy_frag, 0, sizeof (fragS)); | |
2795 | dummy_frag->fr_type = rs_fill; | |
2796 | dummy_frag->line = listing_tail; | |
2797 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
2798 | dummy_frag->fr_symbol = symbolP; | |
2799 | } | |
2800 | else | |
2801 | #endif | |
2802 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
2803 | ||
2804 | #ifdef OBJ_COFF | |
2805 | /* "set" symbols are local unless otherwise specified. */ | |
2806 | SF_SET_LOCAL (symbolP); | |
2807 | #endif /* OBJ_COFF */ | |
2808 | } /* Make a new symbol. */ | |
2809 | ||
2810 | symbol_table_insert (symbolP); | |
2811 | ||
2812 | * end_name = delim; | |
2813 | ||
2814 | if (equiv | |
2815 | && S_IS_DEFINED (symbolP) | |
2816 | && S_GET_SEGMENT (symbolP) != reg_section) | |
2817 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
2818 | ||
2819 | pseudo_set (symbolP); | |
2820 | ||
2821 | demand_empty_rest_of_line (); | |
2822 | ||
c19d1205 | 2823 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
2824 | |
2825 | THUMB_SET_FUNC (symbolP, 1); | |
2826 | ARM_SET_THUMB (symbolP, 1); | |
2827 | #if defined OBJ_ELF || defined OBJ_COFF | |
2828 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2829 | #endif | |
2830 | } | |
2831 | ||
c19d1205 | 2832 | /* Directives: Mode selection. */ |
b99bd4ef | 2833 | |
c19d1205 ZW |
2834 | /* .syntax [unified|divided] - choose the new unified syntax |
2835 | (same for Arm and Thumb encoding, modulo slight differences in what | |
2836 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 2837 | static void |
c19d1205 | 2838 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2839 | { |
c19d1205 ZW |
2840 | char *name, delim; |
2841 | ||
2842 | name = input_line_pointer; | |
2843 | delim = get_symbol_end (); | |
2844 | ||
2845 | if (!strcasecmp (name, "unified")) | |
2846 | unified_syntax = TRUE; | |
2847 | else if (!strcasecmp (name, "divided")) | |
2848 | unified_syntax = FALSE; | |
2849 | else | |
2850 | { | |
2851 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
2852 | return; | |
2853 | } | |
2854 | *input_line_pointer = delim; | |
b99bd4ef NC |
2855 | demand_empty_rest_of_line (); |
2856 | } | |
2857 | ||
c19d1205 ZW |
2858 | /* Directives: sectioning and alignment. */ |
2859 | ||
2860 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
2861 | ||
b99bd4ef | 2862 | static void |
c19d1205 | 2863 | s_align (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2864 | { |
a737bd4d | 2865 | int temp; |
dce323d1 | 2866 | bfd_boolean fill_p; |
c19d1205 ZW |
2867 | long temp_fill; |
2868 | long max_alignment = 15; | |
b99bd4ef NC |
2869 | |
2870 | temp = get_absolute_expression (); | |
c19d1205 ZW |
2871 | if (temp > max_alignment) |
2872 | as_bad (_("alignment too large: %d assumed"), temp = max_alignment); | |
2873 | else if (temp < 0) | |
b99bd4ef | 2874 | { |
c19d1205 ZW |
2875 | as_bad (_("alignment negative. 0 assumed.")); |
2876 | temp = 0; | |
2877 | } | |
b99bd4ef | 2878 | |
c19d1205 ZW |
2879 | if (*input_line_pointer == ',') |
2880 | { | |
2881 | input_line_pointer++; | |
2882 | temp_fill = get_absolute_expression (); | |
dce323d1 | 2883 | fill_p = TRUE; |
b99bd4ef | 2884 | } |
c19d1205 | 2885 | else |
dce323d1 PB |
2886 | { |
2887 | fill_p = FALSE; | |
2888 | temp_fill = 0; | |
2889 | } | |
b99bd4ef | 2890 | |
c19d1205 ZW |
2891 | if (!temp) |
2892 | temp = 2; | |
b99bd4ef | 2893 | |
c19d1205 ZW |
2894 | /* Only make a frag if we HAVE to. */ |
2895 | if (temp && !need_pass_2) | |
dce323d1 PB |
2896 | { |
2897 | if (!fill_p && subseg_text_p (now_seg)) | |
2898 | frag_align_code (temp, 0); | |
2899 | else | |
2900 | frag_align (temp, (int) temp_fill, 0); | |
2901 | } | |
c19d1205 ZW |
2902 | demand_empty_rest_of_line (); |
2903 | ||
2904 | record_alignment (now_seg, temp); | |
b99bd4ef NC |
2905 | } |
2906 | ||
c19d1205 ZW |
2907 | static void |
2908 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 2909 | { |
c19d1205 ZW |
2910 | /* We don't support putting frags in the BSS segment, we fake it by |
2911 | marking in_bss, then looking at s_skip for clues. */ | |
2912 | subseg_set (bss_section, 0); | |
2913 | demand_empty_rest_of_line (); | |
cd000bff DJ |
2914 | |
2915 | #ifdef md_elf_section_change_hook | |
2916 | md_elf_section_change_hook (); | |
2917 | #endif | |
c19d1205 | 2918 | } |
b99bd4ef | 2919 | |
c19d1205 ZW |
2920 | static void |
2921 | s_even (int ignore ATTRIBUTE_UNUSED) | |
2922 | { | |
2923 | /* Never make frag if expect extra pass. */ | |
2924 | if (!need_pass_2) | |
2925 | frag_align (1, 0, 0); | |
b99bd4ef | 2926 | |
c19d1205 | 2927 | record_alignment (now_seg, 1); |
b99bd4ef | 2928 | |
c19d1205 | 2929 | demand_empty_rest_of_line (); |
b99bd4ef NC |
2930 | } |
2931 | ||
c19d1205 | 2932 | /* Directives: Literal pools. */ |
a737bd4d | 2933 | |
c19d1205 ZW |
2934 | static literal_pool * |
2935 | find_literal_pool (void) | |
a737bd4d | 2936 | { |
c19d1205 | 2937 | literal_pool * pool; |
a737bd4d | 2938 | |
c19d1205 | 2939 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 2940 | { |
c19d1205 ZW |
2941 | if (pool->section == now_seg |
2942 | && pool->sub_section == now_subseg) | |
2943 | break; | |
a737bd4d NC |
2944 | } |
2945 | ||
c19d1205 | 2946 | return pool; |
a737bd4d NC |
2947 | } |
2948 | ||
c19d1205 ZW |
2949 | static literal_pool * |
2950 | find_or_make_literal_pool (void) | |
a737bd4d | 2951 | { |
c19d1205 ZW |
2952 | /* Next literal pool ID number. */ |
2953 | static unsigned int latest_pool_num = 1; | |
2954 | literal_pool * pool; | |
a737bd4d | 2955 | |
c19d1205 | 2956 | pool = find_literal_pool (); |
a737bd4d | 2957 | |
c19d1205 | 2958 | if (pool == NULL) |
a737bd4d | 2959 | { |
c19d1205 | 2960 | /* Create a new pool. */ |
21d799b5 | 2961 | pool = (literal_pool *) xmalloc (sizeof (* pool)); |
c19d1205 ZW |
2962 | if (! pool) |
2963 | return NULL; | |
a737bd4d | 2964 | |
c19d1205 ZW |
2965 | pool->next_free_entry = 0; |
2966 | pool->section = now_seg; | |
2967 | pool->sub_section = now_subseg; | |
2968 | pool->next = list_of_pools; | |
2969 | pool->symbol = NULL; | |
2970 | ||
2971 | /* Add it to the list. */ | |
2972 | list_of_pools = pool; | |
a737bd4d | 2973 | } |
a737bd4d | 2974 | |
c19d1205 ZW |
2975 | /* New pools, and emptied pools, will have a NULL symbol. */ |
2976 | if (pool->symbol == NULL) | |
a737bd4d | 2977 | { |
c19d1205 ZW |
2978 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
2979 | (valueT) 0, &zero_address_frag); | |
2980 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
2981 | } |
2982 | ||
c19d1205 ZW |
2983 | /* Done. */ |
2984 | return pool; | |
a737bd4d NC |
2985 | } |
2986 | ||
c19d1205 | 2987 | /* Add the literal in the global 'inst' |
5f4273c7 | 2988 | structure to the relevant literal pool. */ |
b99bd4ef NC |
2989 | |
2990 | static int | |
c19d1205 | 2991 | add_to_lit_pool (void) |
b99bd4ef | 2992 | { |
c19d1205 ZW |
2993 | literal_pool * pool; |
2994 | unsigned int entry; | |
b99bd4ef | 2995 | |
c19d1205 ZW |
2996 | pool = find_or_make_literal_pool (); |
2997 | ||
2998 | /* Check if this literal value is already in the pool. */ | |
2999 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 3000 | { |
c19d1205 ZW |
3001 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) |
3002 | && (inst.reloc.exp.X_op == O_constant) | |
3003 | && (pool->literals[entry].X_add_number | |
3004 | == inst.reloc.exp.X_add_number) | |
3005 | && (pool->literals[entry].X_unsigned | |
3006 | == inst.reloc.exp.X_unsigned)) | |
3007 | break; | |
3008 | ||
3009 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3010 | && (inst.reloc.exp.X_op == O_symbol) | |
3011 | && (pool->literals[entry].X_add_number | |
3012 | == inst.reloc.exp.X_add_number) | |
3013 | && (pool->literals[entry].X_add_symbol | |
3014 | == inst.reloc.exp.X_add_symbol) | |
3015 | && (pool->literals[entry].X_op_symbol | |
3016 | == inst.reloc.exp.X_op_symbol)) | |
3017 | break; | |
b99bd4ef NC |
3018 | } |
3019 | ||
c19d1205 ZW |
3020 | /* Do we need to create a new entry? */ |
3021 | if (entry == pool->next_free_entry) | |
3022 | { | |
3023 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
3024 | { | |
3025 | inst.error = _("literal pool overflow"); | |
3026 | return FAIL; | |
3027 | } | |
3028 | ||
3029 | pool->literals[entry] = inst.reloc.exp; | |
3030 | pool->next_free_entry += 1; | |
3031 | } | |
b99bd4ef | 3032 | |
c19d1205 ZW |
3033 | inst.reloc.exp.X_op = O_symbol; |
3034 | inst.reloc.exp.X_add_number = ((int) entry) * 4; | |
3035 | inst.reloc.exp.X_add_symbol = pool->symbol; | |
b99bd4ef | 3036 | |
c19d1205 | 3037 | return SUCCESS; |
b99bd4ef NC |
3038 | } |
3039 | ||
c19d1205 ZW |
3040 | /* Can't use symbol_new here, so have to create a symbol and then at |
3041 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 3042 | |
c19d1205 ZW |
3043 | static void |
3044 | symbol_locate (symbolS * symbolP, | |
3045 | const char * name, /* It is copied, the caller can modify. */ | |
3046 | segT segment, /* Segment identifier (SEG_<something>). */ | |
3047 | valueT valu, /* Symbol value. */ | |
3048 | fragS * frag) /* Associated fragment. */ | |
3049 | { | |
3050 | unsigned int name_length; | |
3051 | char * preserved_copy_of_name; | |
e16bb312 | 3052 | |
c19d1205 ZW |
3053 | name_length = strlen (name) + 1; /* +1 for \0. */ |
3054 | obstack_grow (¬es, name, name_length); | |
21d799b5 | 3055 | preserved_copy_of_name = (char *) obstack_finish (¬es); |
e16bb312 | 3056 | |
c19d1205 ZW |
3057 | #ifdef tc_canonicalize_symbol_name |
3058 | preserved_copy_of_name = | |
3059 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
3060 | #endif | |
b99bd4ef | 3061 | |
c19d1205 | 3062 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 3063 | |
c19d1205 ZW |
3064 | S_SET_SEGMENT (symbolP, segment); |
3065 | S_SET_VALUE (symbolP, valu); | |
3066 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 3067 | |
c19d1205 | 3068 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 3069 | |
c19d1205 ZW |
3070 | /* Link to end of symbol chain. */ |
3071 | { | |
3072 | extern int symbol_table_frozen; | |
b99bd4ef | 3073 | |
c19d1205 ZW |
3074 | if (symbol_table_frozen) |
3075 | abort (); | |
3076 | } | |
b99bd4ef | 3077 | |
c19d1205 | 3078 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 3079 | |
c19d1205 | 3080 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 3081 | |
c19d1205 ZW |
3082 | #ifdef tc_symbol_new_hook |
3083 | tc_symbol_new_hook (symbolP); | |
3084 | #endif | |
3085 | ||
3086 | #ifdef DEBUG_SYMS | |
3087 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
3088 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
3089 | } |
3090 | ||
b99bd4ef | 3091 | |
c19d1205 ZW |
3092 | static void |
3093 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 3094 | { |
c19d1205 ZW |
3095 | unsigned int entry; |
3096 | literal_pool * pool; | |
3097 | char sym_name[20]; | |
b99bd4ef | 3098 | |
c19d1205 ZW |
3099 | pool = find_literal_pool (); |
3100 | if (pool == NULL | |
3101 | || pool->symbol == NULL | |
3102 | || pool->next_free_entry == 0) | |
3103 | return; | |
b99bd4ef | 3104 | |
c19d1205 | 3105 | mapping_state (MAP_DATA); |
b99bd4ef | 3106 | |
c19d1205 ZW |
3107 | /* Align pool as you have word accesses. |
3108 | Only make a frag if we have to. */ | |
3109 | if (!need_pass_2) | |
3110 | frag_align (2, 0, 0); | |
b99bd4ef | 3111 | |
c19d1205 | 3112 | record_alignment (now_seg, 2); |
b99bd4ef | 3113 | |
c19d1205 | 3114 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 3115 | |
c19d1205 ZW |
3116 | symbol_locate (pool->symbol, sym_name, now_seg, |
3117 | (valueT) frag_now_fix (), frag_now); | |
3118 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 3119 | |
c19d1205 | 3120 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 3121 | |
c19d1205 ZW |
3122 | #if defined OBJ_COFF || defined OBJ_ELF |
3123 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
3124 | #endif | |
6c43fab6 | 3125 | |
c19d1205 ZW |
3126 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
3127 | /* First output the expression in the instruction to the pool. */ | |
3128 | emit_expr (&(pool->literals[entry]), 4); /* .word */ | |
b99bd4ef | 3129 | |
c19d1205 ZW |
3130 | /* Mark the pool as empty. */ |
3131 | pool->next_free_entry = 0; | |
3132 | pool->symbol = NULL; | |
b99bd4ef NC |
3133 | } |
3134 | ||
c19d1205 ZW |
3135 | #ifdef OBJ_ELF |
3136 | /* Forward declarations for functions below, in the MD interface | |
3137 | section. */ | |
3138 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
3139 | static valueT create_unwind_entry (int); | |
3140 | static void start_unwind_section (const segT, int); | |
3141 | static void add_unwind_opcode (valueT, int); | |
3142 | static void flush_pending_unwind (void); | |
b99bd4ef | 3143 | |
c19d1205 | 3144 | /* Directives: Data. */ |
b99bd4ef | 3145 | |
c19d1205 ZW |
3146 | static void |
3147 | s_arm_elf_cons (int nbytes) | |
3148 | { | |
3149 | expressionS exp; | |
b99bd4ef | 3150 | |
c19d1205 ZW |
3151 | #ifdef md_flush_pending_output |
3152 | md_flush_pending_output (); | |
3153 | #endif | |
b99bd4ef | 3154 | |
c19d1205 | 3155 | if (is_it_end_of_statement ()) |
b99bd4ef | 3156 | { |
c19d1205 ZW |
3157 | demand_empty_rest_of_line (); |
3158 | return; | |
b99bd4ef NC |
3159 | } |
3160 | ||
c19d1205 ZW |
3161 | #ifdef md_cons_align |
3162 | md_cons_align (nbytes); | |
3163 | #endif | |
b99bd4ef | 3164 | |
c19d1205 ZW |
3165 | mapping_state (MAP_DATA); |
3166 | do | |
b99bd4ef | 3167 | { |
c19d1205 ZW |
3168 | int reloc; |
3169 | char *base = input_line_pointer; | |
b99bd4ef | 3170 | |
c19d1205 | 3171 | expression (& exp); |
b99bd4ef | 3172 | |
c19d1205 ZW |
3173 | if (exp.X_op != O_symbol) |
3174 | emit_expr (&exp, (unsigned int) nbytes); | |
3175 | else | |
3176 | { | |
3177 | char *before_reloc = input_line_pointer; | |
3178 | reloc = parse_reloc (&input_line_pointer); | |
3179 | if (reloc == -1) | |
3180 | { | |
3181 | as_bad (_("unrecognized relocation suffix")); | |
3182 | ignore_rest_of_line (); | |
3183 | return; | |
3184 | } | |
3185 | else if (reloc == BFD_RELOC_UNUSED) | |
3186 | emit_expr (&exp, (unsigned int) nbytes); | |
3187 | else | |
3188 | { | |
21d799b5 NC |
3189 | reloc_howto_type *howto = (reloc_howto_type *) |
3190 | bfd_reloc_type_lookup (stdoutput, | |
3191 | (bfd_reloc_code_real_type) reloc); | |
c19d1205 | 3192 | int size = bfd_get_reloc_size (howto); |
b99bd4ef | 3193 | |
2fc8bdac ZW |
3194 | if (reloc == BFD_RELOC_ARM_PLT32) |
3195 | { | |
3196 | as_bad (_("(plt) is only valid on branch targets")); | |
3197 | reloc = BFD_RELOC_UNUSED; | |
3198 | size = 0; | |
3199 | } | |
3200 | ||
c19d1205 | 3201 | if (size > nbytes) |
2fc8bdac | 3202 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
3203 | howto->name, nbytes); |
3204 | else | |
3205 | { | |
3206 | /* We've parsed an expression stopping at O_symbol. | |
3207 | But there may be more expression left now that we | |
3208 | have parsed the relocation marker. Parse it again. | |
3209 | XXX Surely there is a cleaner way to do this. */ | |
3210 | char *p = input_line_pointer; | |
3211 | int offset; | |
21d799b5 | 3212 | char *save_buf = (char *) alloca (input_line_pointer - base); |
c19d1205 ZW |
3213 | memcpy (save_buf, base, input_line_pointer - base); |
3214 | memmove (base + (input_line_pointer - before_reloc), | |
3215 | base, before_reloc - base); | |
3216 | ||
3217 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
3218 | expression (&exp); | |
3219 | memcpy (base, save_buf, p - base); | |
3220 | ||
3221 | offset = nbytes - size; | |
3222 | p = frag_more ((int) nbytes); | |
3223 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, | |
21d799b5 | 3224 | size, &exp, 0, (enum bfd_reloc_code_real) reloc); |
c19d1205 ZW |
3225 | } |
3226 | } | |
3227 | } | |
b99bd4ef | 3228 | } |
c19d1205 | 3229 | while (*input_line_pointer++ == ','); |
b99bd4ef | 3230 | |
c19d1205 ZW |
3231 | /* Put terminator back into stream. */ |
3232 | input_line_pointer --; | |
3233 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
3234 | } |
3235 | ||
c921be7d NC |
3236 | /* Emit an expression containing a 32-bit thumb instruction. |
3237 | Implementation based on put_thumb32_insn. */ | |
3238 | ||
3239 | static void | |
3240 | emit_thumb32_expr (expressionS * exp) | |
3241 | { | |
3242 | expressionS exp_high = *exp; | |
3243 | ||
3244 | exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; | |
3245 | emit_expr (& exp_high, (unsigned int) THUMB_SIZE); | |
3246 | exp->X_add_number &= 0xffff; | |
3247 | emit_expr (exp, (unsigned int) THUMB_SIZE); | |
3248 | } | |
3249 | ||
3250 | /* Guess the instruction size based on the opcode. */ | |
3251 | ||
3252 | static int | |
3253 | thumb_insn_size (int opcode) | |
3254 | { | |
3255 | if ((unsigned int) opcode < 0xe800u) | |
3256 | return 2; | |
3257 | else if ((unsigned int) opcode >= 0xe8000000u) | |
3258 | return 4; | |
3259 | else | |
3260 | return 0; | |
3261 | } | |
3262 | ||
3263 | static bfd_boolean | |
3264 | emit_insn (expressionS *exp, int nbytes) | |
3265 | { | |
3266 | int size = 0; | |
3267 | ||
3268 | if (exp->X_op == O_constant) | |
3269 | { | |
3270 | size = nbytes; | |
3271 | ||
3272 | if (size == 0) | |
3273 | size = thumb_insn_size (exp->X_add_number); | |
3274 | ||
3275 | if (size != 0) | |
3276 | { | |
3277 | if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) | |
3278 | { | |
3279 | as_bad (_(".inst.n operand too big. "\ | |
3280 | "Use .inst.w instead")); | |
3281 | size = 0; | |
3282 | } | |
3283 | else | |
3284 | { | |
3285 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
3286 | set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0); | |
3287 | else | |
3288 | set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); | |
3289 | ||
3290 | if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) | |
3291 | emit_thumb32_expr (exp); | |
3292 | else | |
3293 | emit_expr (exp, (unsigned int) size); | |
3294 | ||
3295 | it_fsm_post_encode (); | |
3296 | } | |
3297 | } | |
3298 | else | |
3299 | as_bad (_("cannot determine Thumb instruction size. " \ | |
3300 | "Use .inst.n/.inst.w instead")); | |
3301 | } | |
3302 | else | |
3303 | as_bad (_("constant expression required")); | |
3304 | ||
3305 | return (size != 0); | |
3306 | } | |
3307 | ||
3308 | /* Like s_arm_elf_cons but do not use md_cons_align and | |
3309 | set the mapping state to MAP_ARM/MAP_THUMB. */ | |
3310 | ||
3311 | static void | |
3312 | s_arm_elf_inst (int nbytes) | |
3313 | { | |
3314 | if (is_it_end_of_statement ()) | |
3315 | { | |
3316 | demand_empty_rest_of_line (); | |
3317 | return; | |
3318 | } | |
3319 | ||
3320 | /* Calling mapping_state () here will not change ARM/THUMB, | |
3321 | but will ensure not to be in DATA state. */ | |
3322 | ||
3323 | if (thumb_mode) | |
3324 | mapping_state (MAP_THUMB); | |
3325 | else | |
3326 | { | |
3327 | if (nbytes != 0) | |
3328 | { | |
3329 | as_bad (_("width suffixes are invalid in ARM mode")); | |
3330 | ignore_rest_of_line (); | |
3331 | return; | |
3332 | } | |
3333 | ||
3334 | nbytes = 4; | |
3335 | ||
3336 | mapping_state (MAP_ARM); | |
3337 | } | |
3338 | ||
3339 | do | |
3340 | { | |
3341 | expressionS exp; | |
3342 | ||
3343 | expression (& exp); | |
3344 | ||
3345 | if (! emit_insn (& exp, nbytes)) | |
3346 | { | |
3347 | ignore_rest_of_line (); | |
3348 | return; | |
3349 | } | |
3350 | } | |
3351 | while (*input_line_pointer++ == ','); | |
3352 | ||
3353 | /* Put terminator back into stream. */ | |
3354 | input_line_pointer --; | |
3355 | demand_empty_rest_of_line (); | |
3356 | } | |
b99bd4ef | 3357 | |
c19d1205 | 3358 | /* Parse a .rel31 directive. */ |
b99bd4ef | 3359 | |
c19d1205 ZW |
3360 | static void |
3361 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
3362 | { | |
3363 | expressionS exp; | |
3364 | char *p; | |
3365 | valueT highbit; | |
b99bd4ef | 3366 | |
c19d1205 ZW |
3367 | highbit = 0; |
3368 | if (*input_line_pointer == '1') | |
3369 | highbit = 0x80000000; | |
3370 | else if (*input_line_pointer != '0') | |
3371 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 3372 | |
c19d1205 ZW |
3373 | input_line_pointer++; |
3374 | if (*input_line_pointer != ',') | |
3375 | as_bad (_("missing comma")); | |
3376 | input_line_pointer++; | |
b99bd4ef | 3377 | |
c19d1205 ZW |
3378 | #ifdef md_flush_pending_output |
3379 | md_flush_pending_output (); | |
3380 | #endif | |
b99bd4ef | 3381 | |
c19d1205 ZW |
3382 | #ifdef md_cons_align |
3383 | md_cons_align (4); | |
3384 | #endif | |
b99bd4ef | 3385 | |
c19d1205 | 3386 | mapping_state (MAP_DATA); |
b99bd4ef | 3387 | |
c19d1205 | 3388 | expression (&exp); |
b99bd4ef | 3389 | |
c19d1205 ZW |
3390 | p = frag_more (4); |
3391 | md_number_to_chars (p, highbit, 4); | |
3392 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
3393 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 3394 | |
c19d1205 | 3395 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3396 | } |
3397 | ||
c19d1205 | 3398 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 3399 | |
c19d1205 | 3400 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 3401 | |
c19d1205 ZW |
3402 | static void |
3403 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
3404 | { | |
3405 | demand_empty_rest_of_line (); | |
921e5f0a PB |
3406 | if (unwind.proc_start) |
3407 | { | |
c921be7d | 3408 | as_bad (_("duplicate .fnstart directive")); |
921e5f0a PB |
3409 | return; |
3410 | } | |
3411 | ||
c19d1205 ZW |
3412 | /* Mark the start of the function. */ |
3413 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 3414 | |
c19d1205 ZW |
3415 | /* Reset the rest of the unwind info. */ |
3416 | unwind.opcode_count = 0; | |
3417 | unwind.table_entry = NULL; | |
3418 | unwind.personality_routine = NULL; | |
3419 | unwind.personality_index = -1; | |
3420 | unwind.frame_size = 0; | |
3421 | unwind.fp_offset = 0; | |
fdfde340 | 3422 | unwind.fp_reg = REG_SP; |
c19d1205 ZW |
3423 | unwind.fp_used = 0; |
3424 | unwind.sp_restored = 0; | |
3425 | } | |
b99bd4ef | 3426 | |
b99bd4ef | 3427 | |
c19d1205 ZW |
3428 | /* Parse a handlerdata directive. Creates the exception handling table entry |
3429 | for the function. */ | |
b99bd4ef | 3430 | |
c19d1205 ZW |
3431 | static void |
3432 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
3433 | { | |
3434 | demand_empty_rest_of_line (); | |
921e5f0a | 3435 | if (!unwind.proc_start) |
c921be7d | 3436 | as_bad (MISSING_FNSTART); |
921e5f0a | 3437 | |
c19d1205 | 3438 | if (unwind.table_entry) |
6decc662 | 3439 | as_bad (_("duplicate .handlerdata directive")); |
f02232aa | 3440 | |
c19d1205 ZW |
3441 | create_unwind_entry (1); |
3442 | } | |
a737bd4d | 3443 | |
c19d1205 | 3444 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 3445 | |
c19d1205 ZW |
3446 | static void |
3447 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
3448 | { | |
3449 | long where; | |
3450 | char *ptr; | |
3451 | valueT val; | |
940b5ce0 | 3452 | unsigned int marked_pr_dependency; |
f02232aa | 3453 | |
c19d1205 | 3454 | demand_empty_rest_of_line (); |
f02232aa | 3455 | |
921e5f0a PB |
3456 | if (!unwind.proc_start) |
3457 | { | |
c921be7d | 3458 | as_bad (_(".fnend directive without .fnstart")); |
921e5f0a PB |
3459 | return; |
3460 | } | |
3461 | ||
c19d1205 ZW |
3462 | /* Add eh table entry. */ |
3463 | if (unwind.table_entry == NULL) | |
3464 | val = create_unwind_entry (0); | |
3465 | else | |
3466 | val = 0; | |
f02232aa | 3467 | |
c19d1205 ZW |
3468 | /* Add index table entry. This is two words. */ |
3469 | start_unwind_section (unwind.saved_seg, 1); | |
3470 | frag_align (2, 0, 0); | |
3471 | record_alignment (now_seg, 2); | |
b99bd4ef | 3472 | |
c19d1205 ZW |
3473 | ptr = frag_more (8); |
3474 | where = frag_now_fix () - 8; | |
f02232aa | 3475 | |
c19d1205 ZW |
3476 | /* Self relative offset of the function start. */ |
3477 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
3478 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3479 | |
c19d1205 ZW |
3480 | /* Indicate dependency on EHABI-defined personality routines to the |
3481 | linker, if it hasn't been done already. */ | |
940b5ce0 DJ |
3482 | marked_pr_dependency |
3483 | = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; | |
c19d1205 ZW |
3484 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 |
3485 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
3486 | { | |
5f4273c7 NC |
3487 | static const char *const name[] = |
3488 | { | |
3489 | "__aeabi_unwind_cpp_pr0", | |
3490 | "__aeabi_unwind_cpp_pr1", | |
3491 | "__aeabi_unwind_cpp_pr2" | |
3492 | }; | |
c19d1205 ZW |
3493 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); |
3494 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
c19d1205 | 3495 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency |
940b5ce0 | 3496 | |= 1 << unwind.personality_index; |
c19d1205 | 3497 | } |
f02232aa | 3498 | |
c19d1205 ZW |
3499 | if (val) |
3500 | /* Inline exception table entry. */ | |
3501 | md_number_to_chars (ptr + 4, val, 4); | |
3502 | else | |
3503 | /* Self relative offset of the table entry. */ | |
3504 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
3505 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3506 | |
c19d1205 ZW |
3507 | /* Restore the original section. */ |
3508 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
921e5f0a PB |
3509 | |
3510 | unwind.proc_start = NULL; | |
c19d1205 | 3511 | } |
f02232aa | 3512 | |
f02232aa | 3513 | |
c19d1205 | 3514 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 3515 | |
c19d1205 ZW |
3516 | static void |
3517 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
3518 | { | |
3519 | demand_empty_rest_of_line (); | |
921e5f0a | 3520 | if (!unwind.proc_start) |
c921be7d | 3521 | as_bad (MISSING_FNSTART); |
921e5f0a | 3522 | |
c19d1205 ZW |
3523 | if (unwind.personality_routine || unwind.personality_index != -1) |
3524 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 3525 | |
c19d1205 ZW |
3526 | unwind.personality_index = -2; |
3527 | } | |
b99bd4ef | 3528 | |
b99bd4ef | 3529 | |
c19d1205 | 3530 | /* Parse a personalityindex directive. */ |
b99bd4ef | 3531 | |
c19d1205 ZW |
3532 | static void |
3533 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
3534 | { | |
3535 | expressionS exp; | |
b99bd4ef | 3536 | |
921e5f0a | 3537 | if (!unwind.proc_start) |
c921be7d | 3538 | as_bad (MISSING_FNSTART); |
921e5f0a | 3539 | |
c19d1205 ZW |
3540 | if (unwind.personality_routine || unwind.personality_index != -1) |
3541 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 3542 | |
c19d1205 | 3543 | expression (&exp); |
b99bd4ef | 3544 | |
c19d1205 ZW |
3545 | if (exp.X_op != O_constant |
3546 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 3547 | { |
c19d1205 ZW |
3548 | as_bad (_("bad personality routine number")); |
3549 | ignore_rest_of_line (); | |
3550 | return; | |
b99bd4ef NC |
3551 | } |
3552 | ||
c19d1205 | 3553 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 3554 | |
c19d1205 ZW |
3555 | demand_empty_rest_of_line (); |
3556 | } | |
e16bb312 | 3557 | |
e16bb312 | 3558 | |
c19d1205 | 3559 | /* Parse a personality directive. */ |
e16bb312 | 3560 | |
c19d1205 ZW |
3561 | static void |
3562 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
3563 | { | |
3564 | char *name, *p, c; | |
a737bd4d | 3565 | |
921e5f0a | 3566 | if (!unwind.proc_start) |
c921be7d | 3567 | as_bad (MISSING_FNSTART); |
921e5f0a | 3568 | |
c19d1205 ZW |
3569 | if (unwind.personality_routine || unwind.personality_index != -1) |
3570 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 3571 | |
c19d1205 ZW |
3572 | name = input_line_pointer; |
3573 | c = get_symbol_end (); | |
3574 | p = input_line_pointer; | |
3575 | unwind.personality_routine = symbol_find_or_make (name); | |
3576 | *p = c; | |
3577 | demand_empty_rest_of_line (); | |
3578 | } | |
e16bb312 | 3579 | |
e16bb312 | 3580 | |
c19d1205 | 3581 | /* Parse a directive saving core registers. */ |
e16bb312 | 3582 | |
c19d1205 ZW |
3583 | static void |
3584 | s_arm_unwind_save_core (void) | |
e16bb312 | 3585 | { |
c19d1205 ZW |
3586 | valueT op; |
3587 | long range; | |
3588 | int n; | |
e16bb312 | 3589 | |
c19d1205 ZW |
3590 | range = parse_reg_list (&input_line_pointer); |
3591 | if (range == FAIL) | |
e16bb312 | 3592 | { |
c19d1205 ZW |
3593 | as_bad (_("expected register list")); |
3594 | ignore_rest_of_line (); | |
3595 | return; | |
3596 | } | |
e16bb312 | 3597 | |
c19d1205 | 3598 | demand_empty_rest_of_line (); |
e16bb312 | 3599 | |
c19d1205 ZW |
3600 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
3601 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
3602 | ip because it is clobbered by calls. */ | |
3603 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
3604 | && (range & 0x3000) == 0x1000) | |
3605 | { | |
3606 | unwind.opcode_count--; | |
3607 | unwind.sp_restored = 0; | |
3608 | range = (range | 0x2000) & ~0x1000; | |
3609 | unwind.pending_offset = 0; | |
3610 | } | |
e16bb312 | 3611 | |
01ae4198 DJ |
3612 | /* Pop r4-r15. */ |
3613 | if (range & 0xfff0) | |
c19d1205 | 3614 | { |
01ae4198 DJ |
3615 | /* See if we can use the short opcodes. These pop a block of up to 8 |
3616 | registers starting with r4, plus maybe r14. */ | |
3617 | for (n = 0; n < 8; n++) | |
3618 | { | |
3619 | /* Break at the first non-saved register. */ | |
3620 | if ((range & (1 << (n + 4))) == 0) | |
3621 | break; | |
3622 | } | |
3623 | /* See if there are any other bits set. */ | |
3624 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
3625 | { | |
3626 | /* Use the long form. */ | |
3627 | op = 0x8000 | ((range >> 4) & 0xfff); | |
3628 | add_unwind_opcode (op, 2); | |
3629 | } | |
0dd132b6 | 3630 | else |
01ae4198 DJ |
3631 | { |
3632 | /* Use the short form. */ | |
3633 | if (range & 0x4000) | |
3634 | op = 0xa8; /* Pop r14. */ | |
3635 | else | |
3636 | op = 0xa0; /* Do not pop r14. */ | |
3637 | op |= (n - 1); | |
3638 | add_unwind_opcode (op, 1); | |
3639 | } | |
c19d1205 | 3640 | } |
0dd132b6 | 3641 | |
c19d1205 ZW |
3642 | /* Pop r0-r3. */ |
3643 | if (range & 0xf) | |
3644 | { | |
3645 | op = 0xb100 | (range & 0xf); | |
3646 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
3647 | } |
3648 | ||
c19d1205 ZW |
3649 | /* Record the number of bytes pushed. */ |
3650 | for (n = 0; n < 16; n++) | |
3651 | { | |
3652 | if (range & (1 << n)) | |
3653 | unwind.frame_size += 4; | |
3654 | } | |
0dd132b6 NC |
3655 | } |
3656 | ||
c19d1205 ZW |
3657 | |
3658 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
3659 | |
3660 | static void | |
c19d1205 | 3661 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 3662 | { |
c19d1205 ZW |
3663 | expressionS exp; |
3664 | int num_regs; | |
3665 | valueT op; | |
b99bd4ef | 3666 | |
c19d1205 ZW |
3667 | /* Get Number of registers to transfer. */ |
3668 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
3669 | expression (&exp); | |
3670 | else | |
3671 | exp.X_op = O_illegal; | |
b99bd4ef | 3672 | |
c19d1205 | 3673 | if (exp.X_op != O_constant) |
b99bd4ef | 3674 | { |
c19d1205 ZW |
3675 | as_bad (_("expected , <constant>")); |
3676 | ignore_rest_of_line (); | |
b99bd4ef NC |
3677 | return; |
3678 | } | |
3679 | ||
c19d1205 ZW |
3680 | num_regs = exp.X_add_number; |
3681 | ||
3682 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 3683 | { |
c19d1205 ZW |
3684 | as_bad (_("number of registers must be in the range [1:4]")); |
3685 | ignore_rest_of_line (); | |
b99bd4ef NC |
3686 | return; |
3687 | } | |
3688 | ||
c19d1205 | 3689 | demand_empty_rest_of_line (); |
b99bd4ef | 3690 | |
c19d1205 ZW |
3691 | if (reg == 4) |
3692 | { | |
3693 | /* Short form. */ | |
3694 | op = 0xb4 | (num_regs - 1); | |
3695 | add_unwind_opcode (op, 1); | |
3696 | } | |
b99bd4ef NC |
3697 | else |
3698 | { | |
c19d1205 ZW |
3699 | /* Long form. */ |
3700 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
3701 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3702 | } |
c19d1205 | 3703 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
3704 | } |
3705 | ||
c19d1205 | 3706 | |
fa073d69 MS |
3707 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
3708 | ||
3709 | static void | |
3710 | s_arm_unwind_save_vfp_armv6 (void) | |
3711 | { | |
3712 | int count; | |
3713 | unsigned int start; | |
3714 | valueT op; | |
3715 | int num_vfpv3_regs = 0; | |
3716 | int num_regs_below_16; | |
3717 | ||
3718 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); | |
3719 | if (count == FAIL) | |
3720 | { | |
3721 | as_bad (_("expected register list")); | |
3722 | ignore_rest_of_line (); | |
3723 | return; | |
3724 | } | |
3725 | ||
3726 | demand_empty_rest_of_line (); | |
3727 | ||
3728 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather | |
3729 | than FSTMX/FLDMX-style ones). */ | |
3730 | ||
3731 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ | |
3732 | if (start >= 16) | |
3733 | num_vfpv3_regs = count; | |
3734 | else if (start + count > 16) | |
3735 | num_vfpv3_regs = start + count - 16; | |
3736 | ||
3737 | if (num_vfpv3_regs > 0) | |
3738 | { | |
3739 | int start_offset = start > 16 ? start - 16 : 0; | |
3740 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); | |
3741 | add_unwind_opcode (op, 2); | |
3742 | } | |
3743 | ||
3744 | /* Generate opcode for registers numbered in the range 0 .. 15. */ | |
3745 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; | |
9c2799c2 | 3746 | gas_assert (num_regs_below_16 + num_vfpv3_regs == count); |
fa073d69 MS |
3747 | if (num_regs_below_16 > 0) |
3748 | { | |
3749 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); | |
3750 | add_unwind_opcode (op, 2); | |
3751 | } | |
3752 | ||
3753 | unwind.frame_size += count * 8; | |
3754 | } | |
3755 | ||
3756 | ||
3757 | /* Parse a directive saving VFP registers for pre-ARMv6. */ | |
b99bd4ef NC |
3758 | |
3759 | static void | |
c19d1205 | 3760 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 3761 | { |
c19d1205 | 3762 | int count; |
ca3f61f7 | 3763 | unsigned int reg; |
c19d1205 | 3764 | valueT op; |
b99bd4ef | 3765 | |
5287ad62 | 3766 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); |
c19d1205 | 3767 | if (count == FAIL) |
b99bd4ef | 3768 | { |
c19d1205 ZW |
3769 | as_bad (_("expected register list")); |
3770 | ignore_rest_of_line (); | |
b99bd4ef NC |
3771 | return; |
3772 | } | |
3773 | ||
c19d1205 | 3774 | demand_empty_rest_of_line (); |
b99bd4ef | 3775 | |
c19d1205 | 3776 | if (reg == 8) |
b99bd4ef | 3777 | { |
c19d1205 ZW |
3778 | /* Short form. */ |
3779 | op = 0xb8 | (count - 1); | |
3780 | add_unwind_opcode (op, 1); | |
b99bd4ef | 3781 | } |
c19d1205 | 3782 | else |
b99bd4ef | 3783 | { |
c19d1205 ZW |
3784 | /* Long form. */ |
3785 | op = 0xb300 | (reg << 4) | (count - 1); | |
3786 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3787 | } |
c19d1205 ZW |
3788 | unwind.frame_size += count * 8 + 4; |
3789 | } | |
b99bd4ef | 3790 | |
b99bd4ef | 3791 | |
c19d1205 ZW |
3792 | /* Parse a directive saving iWMMXt data registers. */ |
3793 | ||
3794 | static void | |
3795 | s_arm_unwind_save_mmxwr (void) | |
3796 | { | |
3797 | int reg; | |
3798 | int hi_reg; | |
3799 | int i; | |
3800 | unsigned mask = 0; | |
3801 | valueT op; | |
b99bd4ef | 3802 | |
c19d1205 ZW |
3803 | if (*input_line_pointer == '{') |
3804 | input_line_pointer++; | |
b99bd4ef | 3805 | |
c19d1205 | 3806 | do |
b99bd4ef | 3807 | { |
dcbf9037 | 3808 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 3809 | |
c19d1205 | 3810 | if (reg == FAIL) |
b99bd4ef | 3811 | { |
9b7132d3 | 3812 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 | 3813 | goto error; |
b99bd4ef NC |
3814 | } |
3815 | ||
c19d1205 ZW |
3816 | if (mask >> reg) |
3817 | as_tsktsk (_("register list not in ascending order")); | |
3818 | mask |= 1 << reg; | |
b99bd4ef | 3819 | |
c19d1205 ZW |
3820 | if (*input_line_pointer == '-') |
3821 | { | |
3822 | input_line_pointer++; | |
dcbf9037 | 3823 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
c19d1205 ZW |
3824 | if (hi_reg == FAIL) |
3825 | { | |
9b7132d3 | 3826 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 ZW |
3827 | goto error; |
3828 | } | |
3829 | else if (reg >= hi_reg) | |
3830 | { | |
3831 | as_bad (_("bad register range")); | |
3832 | goto error; | |
3833 | } | |
3834 | for (; reg < hi_reg; reg++) | |
3835 | mask |= 1 << reg; | |
3836 | } | |
3837 | } | |
3838 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 3839 | |
c19d1205 ZW |
3840 | if (*input_line_pointer == '}') |
3841 | input_line_pointer++; | |
b99bd4ef | 3842 | |
c19d1205 | 3843 | demand_empty_rest_of_line (); |
b99bd4ef | 3844 | |
708587a4 | 3845 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
3846 | the list. */ |
3847 | flush_pending_unwind (); | |
b99bd4ef | 3848 | |
c19d1205 | 3849 | for (i = 0; i < 16; i++) |
b99bd4ef | 3850 | { |
c19d1205 ZW |
3851 | if (mask & (1 << i)) |
3852 | unwind.frame_size += 8; | |
b99bd4ef NC |
3853 | } |
3854 | ||
c19d1205 ZW |
3855 | /* Attempt to combine with a previous opcode. We do this because gcc |
3856 | likes to output separate unwind directives for a single block of | |
3857 | registers. */ | |
3858 | if (unwind.opcode_count > 0) | |
b99bd4ef | 3859 | { |
c19d1205 ZW |
3860 | i = unwind.opcodes[unwind.opcode_count - 1]; |
3861 | if ((i & 0xf8) == 0xc0) | |
3862 | { | |
3863 | i &= 7; | |
3864 | /* Only merge if the blocks are contiguous. */ | |
3865 | if (i < 6) | |
3866 | { | |
3867 | if ((mask & 0xfe00) == (1 << 9)) | |
3868 | { | |
3869 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
3870 | unwind.opcode_count--; | |
3871 | } | |
3872 | } | |
3873 | else if (i == 6 && unwind.opcode_count >= 2) | |
3874 | { | |
3875 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
3876 | reg = i >> 4; | |
3877 | i &= 0xf; | |
b99bd4ef | 3878 | |
c19d1205 ZW |
3879 | op = 0xffff << (reg - 1); |
3880 | if (reg > 0 | |
87a1fd79 | 3881 | && ((mask & op) == (1u << (reg - 1)))) |
c19d1205 ZW |
3882 | { |
3883 | op = (1 << (reg + i + 1)) - 1; | |
3884 | op &= ~((1 << reg) - 1); | |
3885 | mask |= op; | |
3886 | unwind.opcode_count -= 2; | |
3887 | } | |
3888 | } | |
3889 | } | |
b99bd4ef NC |
3890 | } |
3891 | ||
c19d1205 ZW |
3892 | hi_reg = 15; |
3893 | /* We want to generate opcodes in the order the registers have been | |
3894 | saved, ie. descending order. */ | |
3895 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 3896 | { |
c19d1205 ZW |
3897 | /* Save registers in blocks. */ |
3898 | if (reg < 0 | |
3899 | || !(mask & (1 << reg))) | |
3900 | { | |
3901 | /* We found an unsaved reg. Generate opcodes to save the | |
5f4273c7 | 3902 | preceding block. */ |
c19d1205 ZW |
3903 | if (reg != hi_reg) |
3904 | { | |
3905 | if (reg == 9) | |
3906 | { | |
3907 | /* Short form. */ | |
3908 | op = 0xc0 | (hi_reg - 10); | |
3909 | add_unwind_opcode (op, 1); | |
3910 | } | |
3911 | else | |
3912 | { | |
3913 | /* Long form. */ | |
3914 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
3915 | add_unwind_opcode (op, 2); | |
3916 | } | |
3917 | } | |
3918 | hi_reg = reg - 1; | |
3919 | } | |
b99bd4ef NC |
3920 | } |
3921 | ||
c19d1205 ZW |
3922 | return; |
3923 | error: | |
3924 | ignore_rest_of_line (); | |
b99bd4ef NC |
3925 | } |
3926 | ||
3927 | static void | |
c19d1205 | 3928 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 3929 | { |
c19d1205 ZW |
3930 | int reg; |
3931 | int hi_reg; | |
3932 | unsigned mask = 0; | |
3933 | valueT op; | |
b99bd4ef | 3934 | |
c19d1205 ZW |
3935 | if (*input_line_pointer == '{') |
3936 | input_line_pointer++; | |
b99bd4ef | 3937 | |
c19d1205 | 3938 | do |
b99bd4ef | 3939 | { |
dcbf9037 | 3940 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 3941 | |
c19d1205 ZW |
3942 | if (reg == FAIL) |
3943 | { | |
9b7132d3 | 3944 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
3945 | goto error; |
3946 | } | |
b99bd4ef | 3947 | |
c19d1205 ZW |
3948 | reg -= 8; |
3949 | if (mask >> reg) | |
3950 | as_tsktsk (_("register list not in ascending order")); | |
3951 | mask |= 1 << reg; | |
b99bd4ef | 3952 | |
c19d1205 ZW |
3953 | if (*input_line_pointer == '-') |
3954 | { | |
3955 | input_line_pointer++; | |
dcbf9037 | 3956 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
c19d1205 ZW |
3957 | if (hi_reg == FAIL) |
3958 | { | |
9b7132d3 | 3959 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
3960 | goto error; |
3961 | } | |
3962 | else if (reg >= hi_reg) | |
3963 | { | |
3964 | as_bad (_("bad register range")); | |
3965 | goto error; | |
3966 | } | |
3967 | for (; reg < hi_reg; reg++) | |
3968 | mask |= 1 << reg; | |
3969 | } | |
b99bd4ef | 3970 | } |
c19d1205 | 3971 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 3972 | |
c19d1205 ZW |
3973 | if (*input_line_pointer == '}') |
3974 | input_line_pointer++; | |
b99bd4ef | 3975 | |
c19d1205 ZW |
3976 | demand_empty_rest_of_line (); |
3977 | ||
708587a4 | 3978 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
3979 | the list. */ |
3980 | flush_pending_unwind (); | |
b99bd4ef | 3981 | |
c19d1205 | 3982 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 3983 | { |
c19d1205 ZW |
3984 | if (mask & (1 << reg)) |
3985 | unwind.frame_size += 4; | |
b99bd4ef | 3986 | } |
c19d1205 ZW |
3987 | op = 0xc700 | mask; |
3988 | add_unwind_opcode (op, 2); | |
3989 | return; | |
3990 | error: | |
3991 | ignore_rest_of_line (); | |
b99bd4ef NC |
3992 | } |
3993 | ||
c19d1205 | 3994 | |
fa073d69 MS |
3995 | /* Parse an unwind_save directive. |
3996 | If the argument is non-zero, this is a .vsave directive. */ | |
c19d1205 | 3997 | |
b99bd4ef | 3998 | static void |
fa073d69 | 3999 | s_arm_unwind_save (int arch_v6) |
b99bd4ef | 4000 | { |
c19d1205 ZW |
4001 | char *peek; |
4002 | struct reg_entry *reg; | |
4003 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 4004 | |
921e5f0a | 4005 | if (!unwind.proc_start) |
c921be7d | 4006 | as_bad (MISSING_FNSTART); |
921e5f0a | 4007 | |
c19d1205 ZW |
4008 | /* Figure out what sort of save we have. */ |
4009 | peek = input_line_pointer; | |
b99bd4ef | 4010 | |
c19d1205 | 4011 | if (*peek == '{') |
b99bd4ef | 4012 | { |
c19d1205 ZW |
4013 | had_brace = TRUE; |
4014 | peek++; | |
b99bd4ef NC |
4015 | } |
4016 | ||
c19d1205 | 4017 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 4018 | |
c19d1205 | 4019 | if (!reg) |
b99bd4ef | 4020 | { |
c19d1205 ZW |
4021 | as_bad (_("register expected")); |
4022 | ignore_rest_of_line (); | |
b99bd4ef NC |
4023 | return; |
4024 | } | |
4025 | ||
c19d1205 | 4026 | switch (reg->type) |
b99bd4ef | 4027 | { |
c19d1205 ZW |
4028 | case REG_TYPE_FN: |
4029 | if (had_brace) | |
4030 | { | |
4031 | as_bad (_("FPA .unwind_save does not take a register list")); | |
4032 | ignore_rest_of_line (); | |
4033 | return; | |
4034 | } | |
93ac2687 | 4035 | input_line_pointer = peek; |
c19d1205 | 4036 | s_arm_unwind_save_fpa (reg->number); |
b99bd4ef | 4037 | return; |
c19d1205 ZW |
4038 | |
4039 | case REG_TYPE_RN: s_arm_unwind_save_core (); return; | |
fa073d69 MS |
4040 | case REG_TYPE_VFD: |
4041 | if (arch_v6) | |
4042 | s_arm_unwind_save_vfp_armv6 (); | |
4043 | else | |
4044 | s_arm_unwind_save_vfp (); | |
4045 | return; | |
c19d1205 ZW |
4046 | case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; |
4047 | case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; | |
4048 | ||
4049 | default: | |
4050 | as_bad (_(".unwind_save does not support this kind of register")); | |
4051 | ignore_rest_of_line (); | |
b99bd4ef | 4052 | } |
c19d1205 | 4053 | } |
b99bd4ef | 4054 | |
b99bd4ef | 4055 | |
c19d1205 ZW |
4056 | /* Parse an unwind_movsp directive. */ |
4057 | ||
4058 | static void | |
4059 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
4060 | { | |
4061 | int reg; | |
4062 | valueT op; | |
4fa3602b | 4063 | int offset; |
c19d1205 | 4064 | |
921e5f0a | 4065 | if (!unwind.proc_start) |
c921be7d | 4066 | as_bad (MISSING_FNSTART); |
921e5f0a | 4067 | |
dcbf9037 | 4068 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 | 4069 | if (reg == FAIL) |
b99bd4ef | 4070 | { |
9b7132d3 | 4071 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 | 4072 | ignore_rest_of_line (); |
b99bd4ef NC |
4073 | return; |
4074 | } | |
4fa3602b PB |
4075 | |
4076 | /* Optional constant. */ | |
4077 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4078 | { | |
4079 | if (immediate_for_directive (&offset) == FAIL) | |
4080 | return; | |
4081 | } | |
4082 | else | |
4083 | offset = 0; | |
4084 | ||
c19d1205 | 4085 | demand_empty_rest_of_line (); |
b99bd4ef | 4086 | |
c19d1205 | 4087 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 4088 | { |
c19d1205 | 4089 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
4090 | return; |
4091 | } | |
4092 | ||
c19d1205 ZW |
4093 | if (unwind.fp_reg != REG_SP) |
4094 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 4095 | |
c19d1205 ZW |
4096 | /* Generate opcode to restore the value. */ |
4097 | op = 0x90 | reg; | |
4098 | add_unwind_opcode (op, 1); | |
4099 | ||
4100 | /* Record the information for later. */ | |
4101 | unwind.fp_reg = reg; | |
4fa3602b | 4102 | unwind.fp_offset = unwind.frame_size - offset; |
c19d1205 | 4103 | unwind.sp_restored = 1; |
b05fe5cf ZW |
4104 | } |
4105 | ||
c19d1205 ZW |
4106 | /* Parse an unwind_pad directive. */ |
4107 | ||
b05fe5cf | 4108 | static void |
c19d1205 | 4109 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 4110 | { |
c19d1205 | 4111 | int offset; |
b05fe5cf | 4112 | |
921e5f0a | 4113 | if (!unwind.proc_start) |
c921be7d | 4114 | as_bad (MISSING_FNSTART); |
921e5f0a | 4115 | |
c19d1205 ZW |
4116 | if (immediate_for_directive (&offset) == FAIL) |
4117 | return; | |
b99bd4ef | 4118 | |
c19d1205 ZW |
4119 | if (offset & 3) |
4120 | { | |
4121 | as_bad (_("stack increment must be multiple of 4")); | |
4122 | ignore_rest_of_line (); | |
4123 | return; | |
4124 | } | |
b99bd4ef | 4125 | |
c19d1205 ZW |
4126 | /* Don't generate any opcodes, just record the details for later. */ |
4127 | unwind.frame_size += offset; | |
4128 | unwind.pending_offset += offset; | |
4129 | ||
4130 | demand_empty_rest_of_line (); | |
4131 | } | |
4132 | ||
4133 | /* Parse an unwind_setfp directive. */ | |
4134 | ||
4135 | static void | |
4136 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 4137 | { |
c19d1205 ZW |
4138 | int sp_reg; |
4139 | int fp_reg; | |
4140 | int offset; | |
4141 | ||
921e5f0a | 4142 | if (!unwind.proc_start) |
c921be7d | 4143 | as_bad (MISSING_FNSTART); |
921e5f0a | 4144 | |
dcbf9037 | 4145 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 ZW |
4146 | if (skip_past_comma (&input_line_pointer) == FAIL) |
4147 | sp_reg = FAIL; | |
4148 | else | |
dcbf9037 | 4149 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
b99bd4ef | 4150 | |
c19d1205 ZW |
4151 | if (fp_reg == FAIL || sp_reg == FAIL) |
4152 | { | |
4153 | as_bad (_("expected <reg>, <reg>")); | |
4154 | ignore_rest_of_line (); | |
4155 | return; | |
4156 | } | |
b99bd4ef | 4157 | |
c19d1205 ZW |
4158 | /* Optional constant. */ |
4159 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4160 | { | |
4161 | if (immediate_for_directive (&offset) == FAIL) | |
4162 | return; | |
4163 | } | |
4164 | else | |
4165 | offset = 0; | |
a737bd4d | 4166 | |
c19d1205 | 4167 | demand_empty_rest_of_line (); |
a737bd4d | 4168 | |
fdfde340 | 4169 | if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) |
a737bd4d | 4170 | { |
c19d1205 ZW |
4171 | as_bad (_("register must be either sp or set by a previous" |
4172 | "unwind_movsp directive")); | |
4173 | return; | |
a737bd4d NC |
4174 | } |
4175 | ||
c19d1205 ZW |
4176 | /* Don't generate any opcodes, just record the information for later. */ |
4177 | unwind.fp_reg = fp_reg; | |
4178 | unwind.fp_used = 1; | |
fdfde340 | 4179 | if (sp_reg == REG_SP) |
c19d1205 ZW |
4180 | unwind.fp_offset = unwind.frame_size - offset; |
4181 | else | |
4182 | unwind.fp_offset -= offset; | |
a737bd4d NC |
4183 | } |
4184 | ||
c19d1205 ZW |
4185 | /* Parse an unwind_raw directive. */ |
4186 | ||
4187 | static void | |
4188 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 4189 | { |
c19d1205 | 4190 | expressionS exp; |
708587a4 | 4191 | /* This is an arbitrary limit. */ |
c19d1205 ZW |
4192 | unsigned char op[16]; |
4193 | int count; | |
a737bd4d | 4194 | |
921e5f0a | 4195 | if (!unwind.proc_start) |
c921be7d | 4196 | as_bad (MISSING_FNSTART); |
921e5f0a | 4197 | |
c19d1205 ZW |
4198 | expression (&exp); |
4199 | if (exp.X_op == O_constant | |
4200 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 4201 | { |
c19d1205 ZW |
4202 | unwind.frame_size += exp.X_add_number; |
4203 | expression (&exp); | |
4204 | } | |
4205 | else | |
4206 | exp.X_op = O_illegal; | |
a737bd4d | 4207 | |
c19d1205 ZW |
4208 | if (exp.X_op != O_constant) |
4209 | { | |
4210 | as_bad (_("expected <offset>, <opcode>")); | |
4211 | ignore_rest_of_line (); | |
4212 | return; | |
4213 | } | |
a737bd4d | 4214 | |
c19d1205 | 4215 | count = 0; |
a737bd4d | 4216 | |
c19d1205 ZW |
4217 | /* Parse the opcode. */ |
4218 | for (;;) | |
4219 | { | |
4220 | if (count >= 16) | |
4221 | { | |
4222 | as_bad (_("unwind opcode too long")); | |
4223 | ignore_rest_of_line (); | |
a737bd4d | 4224 | } |
c19d1205 | 4225 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 4226 | { |
c19d1205 ZW |
4227 | as_bad (_("invalid unwind opcode")); |
4228 | ignore_rest_of_line (); | |
4229 | return; | |
a737bd4d | 4230 | } |
c19d1205 | 4231 | op[count++] = exp.X_add_number; |
a737bd4d | 4232 | |
c19d1205 ZW |
4233 | /* Parse the next byte. */ |
4234 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
4235 | break; | |
a737bd4d | 4236 | |
c19d1205 ZW |
4237 | expression (&exp); |
4238 | } | |
b99bd4ef | 4239 | |
c19d1205 ZW |
4240 | /* Add the opcode bytes in reverse order. */ |
4241 | while (count--) | |
4242 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 4243 | |
c19d1205 | 4244 | demand_empty_rest_of_line (); |
b99bd4ef | 4245 | } |
ee065d83 PB |
4246 | |
4247 | ||
4248 | /* Parse a .eabi_attribute directive. */ | |
4249 | ||
4250 | static void | |
4251 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
4252 | { | |
ee3c0378 AS |
4253 | int tag = s_vendor_attribute (OBJ_ATTR_PROC); |
4254 | ||
4255 | if (tag < NUM_KNOWN_OBJ_ATTRIBUTES) | |
4256 | attributes_set_explicitly[tag] = 1; | |
ee065d83 | 4257 | } |
8463be01 | 4258 | #endif /* OBJ_ELF */ |
ee065d83 PB |
4259 | |
4260 | static void s_arm_arch (int); | |
7a1d4c38 | 4261 | static void s_arm_object_arch (int); |
ee065d83 PB |
4262 | static void s_arm_cpu (int); |
4263 | static void s_arm_fpu (int); | |
b99bd4ef | 4264 | |
f0927246 NC |
4265 | #ifdef TE_PE |
4266 | ||
4267 | static void | |
5f4273c7 | 4268 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
f0927246 NC |
4269 | { |
4270 | expressionS exp; | |
4271 | ||
4272 | do | |
4273 | { | |
4274 | expression (&exp); | |
4275 | if (exp.X_op == O_symbol) | |
4276 | exp.X_op = O_secrel; | |
4277 | ||
4278 | emit_expr (&exp, 4); | |
4279 | } | |
4280 | while (*input_line_pointer++ == ','); | |
4281 | ||
4282 | input_line_pointer--; | |
4283 | demand_empty_rest_of_line (); | |
4284 | } | |
4285 | #endif /* TE_PE */ | |
4286 | ||
c19d1205 ZW |
4287 | /* This table describes all the machine specific pseudo-ops the assembler |
4288 | has to support. The fields are: | |
4289 | pseudo-op name without dot | |
4290 | function to call to execute this pseudo-op | |
4291 | Integer arg to pass to the function. */ | |
b99bd4ef | 4292 | |
c19d1205 | 4293 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 4294 | { |
c19d1205 ZW |
4295 | /* Never called because '.req' does not start a line. */ |
4296 | { "req", s_req, 0 }, | |
dcbf9037 JB |
4297 | /* Following two are likewise never called. */ |
4298 | { "dn", s_dn, 0 }, | |
4299 | { "qn", s_qn, 0 }, | |
c19d1205 ZW |
4300 | { "unreq", s_unreq, 0 }, |
4301 | { "bss", s_bss, 0 }, | |
4302 | { "align", s_align, 0 }, | |
4303 | { "arm", s_arm, 0 }, | |
4304 | { "thumb", s_thumb, 0 }, | |
4305 | { "code", s_code, 0 }, | |
4306 | { "force_thumb", s_force_thumb, 0 }, | |
4307 | { "thumb_func", s_thumb_func, 0 }, | |
4308 | { "thumb_set", s_thumb_set, 0 }, | |
4309 | { "even", s_even, 0 }, | |
4310 | { "ltorg", s_ltorg, 0 }, | |
4311 | { "pool", s_ltorg, 0 }, | |
4312 | { "syntax", s_syntax, 0 }, | |
8463be01 PB |
4313 | { "cpu", s_arm_cpu, 0 }, |
4314 | { "arch", s_arm_arch, 0 }, | |
7a1d4c38 | 4315 | { "object_arch", s_arm_object_arch, 0 }, |
8463be01 | 4316 | { "fpu", s_arm_fpu, 0 }, |
c19d1205 | 4317 | #ifdef OBJ_ELF |
c921be7d NC |
4318 | { "word", s_arm_elf_cons, 4 }, |
4319 | { "long", s_arm_elf_cons, 4 }, | |
4320 | { "inst.n", s_arm_elf_inst, 2 }, | |
4321 | { "inst.w", s_arm_elf_inst, 4 }, | |
4322 | { "inst", s_arm_elf_inst, 0 }, | |
4323 | { "rel31", s_arm_rel31, 0 }, | |
c19d1205 ZW |
4324 | { "fnstart", s_arm_unwind_fnstart, 0 }, |
4325 | { "fnend", s_arm_unwind_fnend, 0 }, | |
4326 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
4327 | { "personality", s_arm_unwind_personality, 0 }, | |
4328 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
4329 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
4330 | { "save", s_arm_unwind_save, 0 }, | |
fa073d69 | 4331 | { "vsave", s_arm_unwind_save, 1 }, |
c19d1205 ZW |
4332 | { "movsp", s_arm_unwind_movsp, 0 }, |
4333 | { "pad", s_arm_unwind_pad, 0 }, | |
4334 | { "setfp", s_arm_unwind_setfp, 0 }, | |
4335 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 | 4336 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
c19d1205 ZW |
4337 | #else |
4338 | { "word", cons, 4}, | |
f0927246 NC |
4339 | |
4340 | /* These are used for dwarf. */ | |
4341 | {"2byte", cons, 2}, | |
4342 | {"4byte", cons, 4}, | |
4343 | {"8byte", cons, 8}, | |
4344 | /* These are used for dwarf2. */ | |
4345 | { "file", (void (*) (int)) dwarf2_directive_file, 0 }, | |
4346 | { "loc", dwarf2_directive_loc, 0 }, | |
4347 | { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, | |
c19d1205 ZW |
4348 | #endif |
4349 | { "extend", float_cons, 'x' }, | |
4350 | { "ldouble", float_cons, 'x' }, | |
4351 | { "packed", float_cons, 'p' }, | |
f0927246 NC |
4352 | #ifdef TE_PE |
4353 | {"secrel32", pe_directive_secrel, 0}, | |
4354 | #endif | |
c19d1205 ZW |
4355 | { 0, 0, 0 } |
4356 | }; | |
4357 | \f | |
4358 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 4359 | |
c19d1205 ZW |
4360 | /* Generic immediate-value read function for use in insn parsing. |
4361 | STR points to the beginning of the immediate (the leading #); | |
4362 | VAL receives the value; if the value is outside [MIN, MAX] | |
4363 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
4364 | optional. */ | |
b99bd4ef | 4365 | |
c19d1205 ZW |
4366 | static int |
4367 | parse_immediate (char **str, int *val, int min, int max, | |
4368 | bfd_boolean prefix_opt) | |
4369 | { | |
4370 | expressionS exp; | |
4371 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
4372 | if (exp.X_op != O_constant) | |
b99bd4ef | 4373 | { |
c19d1205 ZW |
4374 | inst.error = _("constant expression required"); |
4375 | return FAIL; | |
4376 | } | |
b99bd4ef | 4377 | |
c19d1205 ZW |
4378 | if (exp.X_add_number < min || exp.X_add_number > max) |
4379 | { | |
4380 | inst.error = _("immediate value out of range"); | |
4381 | return FAIL; | |
4382 | } | |
b99bd4ef | 4383 | |
c19d1205 ZW |
4384 | *val = exp.X_add_number; |
4385 | return SUCCESS; | |
4386 | } | |
b99bd4ef | 4387 | |
5287ad62 | 4388 | /* Less-generic immediate-value read function with the possibility of loading a |
036dc3f7 | 4389 | big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate |
5287ad62 JB |
4390 | instructions. Puts the result directly in inst.operands[i]. */ |
4391 | ||
4392 | static int | |
4393 | parse_big_immediate (char **str, int i) | |
4394 | { | |
4395 | expressionS exp; | |
4396 | char *ptr = *str; | |
4397 | ||
4398 | my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); | |
4399 | ||
4400 | if (exp.X_op == O_constant) | |
036dc3f7 PB |
4401 | { |
4402 | inst.operands[i].imm = exp.X_add_number & 0xffffffff; | |
4403 | /* If we're on a 64-bit host, then a 64-bit number can be returned using | |
4404 | O_constant. We have to be careful not to break compilation for | |
4405 | 32-bit X_add_number, though. */ | |
4406 | if ((exp.X_add_number & ~0xffffffffl) != 0) | |
4407 | { | |
4408 | /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ | |
4409 | inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; | |
4410 | inst.operands[i].regisimm = 1; | |
4411 | } | |
4412 | } | |
5287ad62 JB |
4413 | else if (exp.X_op == O_big |
4414 | && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32 | |
4415 | && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64) | |
4416 | { | |
4417 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; | |
4418 | /* Bignums have their least significant bits in | |
4419 | generic_bignum[0]. Make sure we put 32 bits in imm and | |
4420 | 32 bits in reg, in a (hopefully) portable way. */ | |
9c2799c2 | 4421 | gas_assert (parts != 0); |
5287ad62 JB |
4422 | inst.operands[i].imm = 0; |
4423 | for (j = 0; j < parts; j++, idx++) | |
4424 | inst.operands[i].imm |= generic_bignum[idx] | |
4425 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4426 | inst.operands[i].reg = 0; | |
4427 | for (j = 0; j < parts; j++, idx++) | |
4428 | inst.operands[i].reg |= generic_bignum[idx] | |
4429 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4430 | inst.operands[i].regisimm = 1; | |
4431 | } | |
4432 | else | |
4433 | return FAIL; | |
5f4273c7 | 4434 | |
5287ad62 JB |
4435 | *str = ptr; |
4436 | ||
4437 | return SUCCESS; | |
4438 | } | |
4439 | ||
c19d1205 ZW |
4440 | /* Returns the pseudo-register number of an FPA immediate constant, |
4441 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 4442 | |
c19d1205 ZW |
4443 | static int |
4444 | parse_fpa_immediate (char ** str) | |
4445 | { | |
4446 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4447 | char * save_in; | |
4448 | expressionS exp; | |
4449 | int i; | |
4450 | int j; | |
b99bd4ef | 4451 | |
c19d1205 ZW |
4452 | /* First try and match exact strings, this is to guarantee |
4453 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 4454 | |
c19d1205 ZW |
4455 | for (i = 0; fp_const[i]; i++) |
4456 | { | |
4457 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 4458 | { |
c19d1205 | 4459 | char *start = *str; |
b99bd4ef | 4460 | |
c19d1205 ZW |
4461 | *str += strlen (fp_const[i]); |
4462 | if (is_end_of_line[(unsigned char) **str]) | |
4463 | return i + 8; | |
4464 | *str = start; | |
4465 | } | |
4466 | } | |
b99bd4ef | 4467 | |
c19d1205 ZW |
4468 | /* Just because we didn't get a match doesn't mean that the constant |
4469 | isn't valid, just that it is in a format that we don't | |
4470 | automatically recognize. Try parsing it with the standard | |
4471 | expression routines. */ | |
b99bd4ef | 4472 | |
c19d1205 | 4473 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 4474 | |
c19d1205 ZW |
4475 | /* Look for a raw floating point number. */ |
4476 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
4477 | && is_end_of_line[(unsigned char) *save_in]) | |
4478 | { | |
4479 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4480 | { | |
4481 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 4482 | { |
c19d1205 ZW |
4483 | if (words[j] != fp_values[i][j]) |
4484 | break; | |
b99bd4ef NC |
4485 | } |
4486 | ||
c19d1205 | 4487 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 4488 | { |
c19d1205 ZW |
4489 | *str = save_in; |
4490 | return i + 8; | |
b99bd4ef NC |
4491 | } |
4492 | } | |
4493 | } | |
b99bd4ef | 4494 | |
c19d1205 ZW |
4495 | /* Try and parse a more complex expression, this will probably fail |
4496 | unless the code uses a floating point prefix (eg "0f"). */ | |
4497 | save_in = input_line_pointer; | |
4498 | input_line_pointer = *str; | |
4499 | if (expression (&exp) == absolute_section | |
4500 | && exp.X_op == O_big | |
4501 | && exp.X_add_number < 0) | |
4502 | { | |
4503 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
4504 | Ditto for 15. */ | |
4505 | if (gen_to_words (words, 5, (long) 15) == 0) | |
4506 | { | |
4507 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4508 | { | |
4509 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
4510 | { | |
4511 | if (words[j] != fp_values[i][j]) | |
4512 | break; | |
4513 | } | |
b99bd4ef | 4514 | |
c19d1205 ZW |
4515 | if (j == MAX_LITTLENUMS) |
4516 | { | |
4517 | *str = input_line_pointer; | |
4518 | input_line_pointer = save_in; | |
4519 | return i + 8; | |
4520 | } | |
4521 | } | |
4522 | } | |
b99bd4ef NC |
4523 | } |
4524 | ||
c19d1205 ZW |
4525 | *str = input_line_pointer; |
4526 | input_line_pointer = save_in; | |
4527 | inst.error = _("invalid FPA immediate expression"); | |
4528 | return FAIL; | |
b99bd4ef NC |
4529 | } |
4530 | ||
136da414 JB |
4531 | /* Returns 1 if a number has "quarter-precision" float format |
4532 | 0baBbbbbbc defgh000 00000000 00000000. */ | |
4533 | ||
4534 | static int | |
4535 | is_quarter_float (unsigned imm) | |
4536 | { | |
4537 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; | |
4538 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; | |
4539 | } | |
4540 | ||
4541 | /* Parse an 8-bit "quarter-precision" floating point number of the form: | |
4542 | 0baBbbbbbc defgh000 00000000 00000000. | |
c96612cc JB |
4543 | The zero and minus-zero cases need special handling, since they can't be |
4544 | encoded in the "quarter-precision" float format, but can nonetheless be | |
4545 | loaded as integer constants. */ | |
136da414 JB |
4546 | |
4547 | static unsigned | |
4548 | parse_qfloat_immediate (char **ccp, int *immed) | |
4549 | { | |
4550 | char *str = *ccp; | |
c96612cc | 4551 | char *fpnum; |
136da414 | 4552 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
c96612cc | 4553 | int found_fpchar = 0; |
5f4273c7 | 4554 | |
136da414 | 4555 | skip_past_char (&str, '#'); |
5f4273c7 | 4556 | |
c96612cc JB |
4557 | /* We must not accidentally parse an integer as a floating-point number. Make |
4558 | sure that the value we parse is not an integer by checking for special | |
4559 | characters '.' or 'e'. | |
4560 | FIXME: This is a horrible hack, but doing better is tricky because type | |
4561 | information isn't in a very usable state at parse time. */ | |
4562 | fpnum = str; | |
4563 | skip_whitespace (fpnum); | |
4564 | ||
4565 | if (strncmp (fpnum, "0x", 2) == 0) | |
4566 | return FAIL; | |
4567 | else | |
4568 | { | |
4569 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) | |
4570 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') | |
4571 | { | |
4572 | found_fpchar = 1; | |
4573 | break; | |
4574 | } | |
4575 | ||
4576 | if (!found_fpchar) | |
4577 | return FAIL; | |
4578 | } | |
5f4273c7 | 4579 | |
136da414 JB |
4580 | if ((str = atof_ieee (str, 's', words)) != NULL) |
4581 | { | |
4582 | unsigned fpword = 0; | |
4583 | int i; | |
5f4273c7 | 4584 | |
136da414 JB |
4585 | /* Our FP word must be 32 bits (single-precision FP). */ |
4586 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
4587 | { | |
4588 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
4589 | fpword |= words[i]; | |
4590 | } | |
5f4273c7 | 4591 | |
c96612cc | 4592 | if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) |
136da414 JB |
4593 | *immed = fpword; |
4594 | else | |
4595 | return FAIL; | |
4596 | ||
4597 | *ccp = str; | |
5f4273c7 | 4598 | |
136da414 JB |
4599 | return SUCCESS; |
4600 | } | |
5f4273c7 | 4601 | |
136da414 JB |
4602 | return FAIL; |
4603 | } | |
4604 | ||
c19d1205 ZW |
4605 | /* Shift operands. */ |
4606 | enum shift_kind | |
b99bd4ef | 4607 | { |
c19d1205 ZW |
4608 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
4609 | }; | |
b99bd4ef | 4610 | |
c19d1205 ZW |
4611 | struct asm_shift_name |
4612 | { | |
4613 | const char *name; | |
4614 | enum shift_kind kind; | |
4615 | }; | |
b99bd4ef | 4616 | |
c19d1205 ZW |
4617 | /* Third argument to parse_shift. */ |
4618 | enum parse_shift_mode | |
4619 | { | |
4620 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
4621 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
4622 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
4623 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
4624 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
4625 | }; | |
b99bd4ef | 4626 | |
c19d1205 ZW |
4627 | /* Parse a <shift> specifier on an ARM data processing instruction. |
4628 | This has three forms: | |
b99bd4ef | 4629 | |
c19d1205 ZW |
4630 | (LSL|LSR|ASL|ASR|ROR) Rs |
4631 | (LSL|LSR|ASL|ASR|ROR) #imm | |
4632 | RRX | |
b99bd4ef | 4633 | |
c19d1205 ZW |
4634 | Note that ASL is assimilated to LSL in the instruction encoding, and |
4635 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 4636 | |
c19d1205 ZW |
4637 | static int |
4638 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 4639 | { |
c19d1205 ZW |
4640 | const struct asm_shift_name *shift_name; |
4641 | enum shift_kind shift; | |
4642 | char *s = *str; | |
4643 | char *p = s; | |
4644 | int reg; | |
b99bd4ef | 4645 | |
c19d1205 ZW |
4646 | for (p = *str; ISALPHA (*p); p++) |
4647 | ; | |
b99bd4ef | 4648 | |
c19d1205 | 4649 | if (p == *str) |
b99bd4ef | 4650 | { |
c19d1205 ZW |
4651 | inst.error = _("shift expression expected"); |
4652 | return FAIL; | |
b99bd4ef NC |
4653 | } |
4654 | ||
21d799b5 NC |
4655 | shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str, |
4656 | p - *str); | |
c19d1205 ZW |
4657 | |
4658 | if (shift_name == NULL) | |
b99bd4ef | 4659 | { |
c19d1205 ZW |
4660 | inst.error = _("shift expression expected"); |
4661 | return FAIL; | |
b99bd4ef NC |
4662 | } |
4663 | ||
c19d1205 | 4664 | shift = shift_name->kind; |
b99bd4ef | 4665 | |
c19d1205 ZW |
4666 | switch (mode) |
4667 | { | |
4668 | case NO_SHIFT_RESTRICT: | |
4669 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 4670 | |
c19d1205 ZW |
4671 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
4672 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
4673 | { | |
4674 | inst.error = _("'LSL' or 'ASR' required"); | |
4675 | return FAIL; | |
4676 | } | |
4677 | break; | |
b99bd4ef | 4678 | |
c19d1205 ZW |
4679 | case SHIFT_LSL_IMMEDIATE: |
4680 | if (shift != SHIFT_LSL) | |
4681 | { | |
4682 | inst.error = _("'LSL' required"); | |
4683 | return FAIL; | |
4684 | } | |
4685 | break; | |
b99bd4ef | 4686 | |
c19d1205 ZW |
4687 | case SHIFT_ASR_IMMEDIATE: |
4688 | if (shift != SHIFT_ASR) | |
4689 | { | |
4690 | inst.error = _("'ASR' required"); | |
4691 | return FAIL; | |
4692 | } | |
4693 | break; | |
b99bd4ef | 4694 | |
c19d1205 ZW |
4695 | default: abort (); |
4696 | } | |
b99bd4ef | 4697 | |
c19d1205 ZW |
4698 | if (shift != SHIFT_RRX) |
4699 | { | |
4700 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
4701 | skip_whitespace (p); | |
b99bd4ef | 4702 | |
c19d1205 | 4703 | if (mode == NO_SHIFT_RESTRICT |
dcbf9037 | 4704 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4705 | { |
4706 | inst.operands[i].imm = reg; | |
4707 | inst.operands[i].immisreg = 1; | |
4708 | } | |
4709 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4710 | return FAIL; | |
4711 | } | |
4712 | inst.operands[i].shift_kind = shift; | |
4713 | inst.operands[i].shifted = 1; | |
4714 | *str = p; | |
4715 | return SUCCESS; | |
b99bd4ef NC |
4716 | } |
4717 | ||
c19d1205 | 4718 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 4719 | |
c19d1205 ZW |
4720 | #<immediate> |
4721 | #<immediate>, <rotate> | |
4722 | <Rm> | |
4723 | <Rm>, <shift> | |
b99bd4ef | 4724 | |
c19d1205 ZW |
4725 | where <shift> is defined by parse_shift above, and <rotate> is a |
4726 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 4727 | is deferred to md_apply_fix. */ |
b99bd4ef | 4728 | |
c19d1205 ZW |
4729 | static int |
4730 | parse_shifter_operand (char **str, int i) | |
4731 | { | |
4732 | int value; | |
91d6fa6a | 4733 | expressionS exp; |
b99bd4ef | 4734 | |
dcbf9037 | 4735 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4736 | { |
4737 | inst.operands[i].reg = value; | |
4738 | inst.operands[i].isreg = 1; | |
b99bd4ef | 4739 | |
c19d1205 ZW |
4740 | /* parse_shift will override this if appropriate */ |
4741 | inst.reloc.exp.X_op = O_constant; | |
4742 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 4743 | |
c19d1205 ZW |
4744 | if (skip_past_comma (str) == FAIL) |
4745 | return SUCCESS; | |
b99bd4ef | 4746 | |
c19d1205 ZW |
4747 | /* Shift operation on register. */ |
4748 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
4749 | } |
4750 | ||
c19d1205 ZW |
4751 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
4752 | return FAIL; | |
b99bd4ef | 4753 | |
c19d1205 | 4754 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 4755 | { |
c19d1205 | 4756 | /* #x, y -- ie explicit rotation by Y. */ |
91d6fa6a | 4757 | if (my_get_expression (&exp, str, GE_NO_PREFIX)) |
c19d1205 | 4758 | return FAIL; |
b99bd4ef | 4759 | |
91d6fa6a | 4760 | if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
c19d1205 ZW |
4761 | { |
4762 | inst.error = _("constant expression expected"); | |
4763 | return FAIL; | |
4764 | } | |
b99bd4ef | 4765 | |
91d6fa6a | 4766 | value = exp.X_add_number; |
c19d1205 ZW |
4767 | if (value < 0 || value > 30 || value % 2 != 0) |
4768 | { | |
4769 | inst.error = _("invalid rotation"); | |
4770 | return FAIL; | |
4771 | } | |
4772 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
4773 | { | |
4774 | inst.error = _("invalid constant"); | |
4775 | return FAIL; | |
4776 | } | |
09d92015 | 4777 | |
55cf6793 | 4778 | /* Convert to decoded value. md_apply_fix will put it back. */ |
c19d1205 ZW |
4779 | inst.reloc.exp.X_add_number |
4780 | = (((inst.reloc.exp.X_add_number << (32 - value)) | |
4781 | | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); | |
09d92015 MM |
4782 | } |
4783 | ||
c19d1205 ZW |
4784 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
4785 | inst.reloc.pc_rel = 0; | |
4786 | return SUCCESS; | |
09d92015 MM |
4787 | } |
4788 | ||
4962c51a MS |
4789 | /* Group relocation information. Each entry in the table contains the |
4790 | textual name of the relocation as may appear in assembler source | |
4791 | and must end with a colon. | |
4792 | Along with this textual name are the relocation codes to be used if | |
4793 | the corresponding instruction is an ALU instruction (ADD or SUB only), | |
4794 | an LDR, an LDRS, or an LDC. */ | |
4795 | ||
4796 | struct group_reloc_table_entry | |
4797 | { | |
4798 | const char *name; | |
4799 | int alu_code; | |
4800 | int ldr_code; | |
4801 | int ldrs_code; | |
4802 | int ldc_code; | |
4803 | }; | |
4804 | ||
4805 | typedef enum | |
4806 | { | |
4807 | /* Varieties of non-ALU group relocation. */ | |
4808 | ||
4809 | GROUP_LDR, | |
4810 | GROUP_LDRS, | |
4811 | GROUP_LDC | |
4812 | } group_reloc_type; | |
4813 | ||
4814 | static struct group_reloc_table_entry group_reloc_table[] = | |
4815 | { /* Program counter relative: */ | |
4816 | { "pc_g0_nc", | |
4817 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ | |
4818 | 0, /* LDR */ | |
4819 | 0, /* LDRS */ | |
4820 | 0 }, /* LDC */ | |
4821 | { "pc_g0", | |
4822 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ | |
4823 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ | |
4824 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ | |
4825 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ | |
4826 | { "pc_g1_nc", | |
4827 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ | |
4828 | 0, /* LDR */ | |
4829 | 0, /* LDRS */ | |
4830 | 0 }, /* LDC */ | |
4831 | { "pc_g1", | |
4832 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ | |
4833 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ | |
4834 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ | |
4835 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ | |
4836 | { "pc_g2", | |
4837 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ | |
4838 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ | |
4839 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ | |
4840 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ | |
4841 | /* Section base relative */ | |
4842 | { "sb_g0_nc", | |
4843 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ | |
4844 | 0, /* LDR */ | |
4845 | 0, /* LDRS */ | |
4846 | 0 }, /* LDC */ | |
4847 | { "sb_g0", | |
4848 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ | |
4849 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ | |
4850 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ | |
4851 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ | |
4852 | { "sb_g1_nc", | |
4853 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ | |
4854 | 0, /* LDR */ | |
4855 | 0, /* LDRS */ | |
4856 | 0 }, /* LDC */ | |
4857 | { "sb_g1", | |
4858 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ | |
4859 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ | |
4860 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ | |
4861 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ | |
4862 | { "sb_g2", | |
4863 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ | |
4864 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ | |
4865 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ | |
4866 | BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ | |
4867 | ||
4868 | /* Given the address of a pointer pointing to the textual name of a group | |
4869 | relocation as may appear in assembler source, attempt to find its details | |
4870 | in group_reloc_table. The pointer will be updated to the character after | |
4871 | the trailing colon. On failure, FAIL will be returned; SUCCESS | |
4872 | otherwise. On success, *entry will be updated to point at the relevant | |
4873 | group_reloc_table entry. */ | |
4874 | ||
4875 | static int | |
4876 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) | |
4877 | { | |
4878 | unsigned int i; | |
4879 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) | |
4880 | { | |
4881 | int length = strlen (group_reloc_table[i].name); | |
4882 | ||
5f4273c7 NC |
4883 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 |
4884 | && (*str)[length] == ':') | |
4962c51a MS |
4885 | { |
4886 | *out = &group_reloc_table[i]; | |
4887 | *str += (length + 1); | |
4888 | return SUCCESS; | |
4889 | } | |
4890 | } | |
4891 | ||
4892 | return FAIL; | |
4893 | } | |
4894 | ||
4895 | /* Parse a <shifter_operand> for an ARM data processing instruction | |
4896 | (as for parse_shifter_operand) where group relocations are allowed: | |
4897 | ||
4898 | #<immediate> | |
4899 | #<immediate>, <rotate> | |
4900 | #:<group_reloc>:<expression> | |
4901 | <Rm> | |
4902 | <Rm>, <shift> | |
4903 | ||
4904 | where <group_reloc> is one of the strings defined in group_reloc_table. | |
4905 | The hashes are optional. | |
4906 | ||
4907 | Everything else is as for parse_shifter_operand. */ | |
4908 | ||
4909 | static parse_operand_result | |
4910 | parse_shifter_operand_group_reloc (char **str, int i) | |
4911 | { | |
4912 | /* Determine if we have the sequence of characters #: or just : | |
4913 | coming next. If we do, then we check for a group relocation. | |
4914 | If we don't, punt the whole lot to parse_shifter_operand. */ | |
4915 | ||
4916 | if (((*str)[0] == '#' && (*str)[1] == ':') | |
4917 | || (*str)[0] == ':') | |
4918 | { | |
4919 | struct group_reloc_table_entry *entry; | |
4920 | ||
4921 | if ((*str)[0] == '#') | |
4922 | (*str) += 2; | |
4923 | else | |
4924 | (*str)++; | |
4925 | ||
4926 | /* Try to parse a group relocation. Anything else is an error. */ | |
4927 | if (find_group_reloc_table_entry (str, &entry) == FAIL) | |
4928 | { | |
4929 | inst.error = _("unknown group relocation"); | |
4930 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
4931 | } | |
4932 | ||
4933 | /* We now have the group relocation table entry corresponding to | |
4934 | the name in the assembler source. Next, we parse the expression. */ | |
4935 | if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) | |
4936 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
4937 | ||
4938 | /* Record the relocation type (always the ALU variant here). */ | |
21d799b5 | 4939 | inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code; |
9c2799c2 | 4940 | gas_assert (inst.reloc.type != 0); |
4962c51a MS |
4941 | |
4942 | return PARSE_OPERAND_SUCCESS; | |
4943 | } | |
4944 | else | |
4945 | return parse_shifter_operand (str, i) == SUCCESS | |
4946 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; | |
4947 | ||
4948 | /* Never reached. */ | |
4949 | } | |
4950 | ||
c19d1205 ZW |
4951 | /* Parse all forms of an ARM address expression. Information is written |
4952 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 4953 | |
c19d1205 | 4954 | Preindexed addressing (.preind=1): |
09d92015 | 4955 | |
c19d1205 ZW |
4956 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
4957 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
4958 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
4959 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 4960 | |
c19d1205 | 4961 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 4962 | |
c19d1205 | 4963 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 4964 | |
c19d1205 ZW |
4965 | [Rn], #offset .reg=Rn .reloc.exp=offset |
4966 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
4967 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
4968 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 4969 | |
c19d1205 | 4970 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 4971 | |
c19d1205 | 4972 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 4973 | |
c19d1205 | 4974 | Other: |
09d92015 | 4975 | |
c19d1205 ZW |
4976 | [Rn]{!} shorthand for [Rn,#0]{!} |
4977 | =immediate .isreg=0 .reloc.exp=immediate | |
4978 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 4979 | |
c19d1205 ZW |
4980 | It is the caller's responsibility to check for addressing modes not |
4981 | supported by the instruction, and to set inst.reloc.type. */ | |
4982 | ||
4962c51a MS |
4983 | static parse_operand_result |
4984 | parse_address_main (char **str, int i, int group_relocations, | |
4985 | group_reloc_type group_type) | |
09d92015 | 4986 | { |
c19d1205 ZW |
4987 | char *p = *str; |
4988 | int reg; | |
09d92015 | 4989 | |
c19d1205 | 4990 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 4991 | { |
c19d1205 ZW |
4992 | if (skip_past_char (&p, '=') == FAIL) |
4993 | { | |
974da60d | 4994 | /* Bare address - translate to PC-relative offset. */ |
c19d1205 ZW |
4995 | inst.reloc.pc_rel = 1; |
4996 | inst.operands[i].reg = REG_PC; | |
4997 | inst.operands[i].isreg = 1; | |
4998 | inst.operands[i].preind = 1; | |
4999 | } | |
974da60d | 5000 | /* Otherwise a load-constant pseudo op, no special treatment needed here. */ |
09d92015 | 5001 | |
c19d1205 | 5002 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
4962c51a | 5003 | return PARSE_OPERAND_FAIL; |
09d92015 | 5004 | |
c19d1205 | 5005 | *str = p; |
4962c51a | 5006 | return PARSE_OPERAND_SUCCESS; |
09d92015 MM |
5007 | } |
5008 | ||
dcbf9037 | 5009 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 5010 | { |
c19d1205 | 5011 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
4962c51a | 5012 | return PARSE_OPERAND_FAIL; |
09d92015 | 5013 | } |
c19d1205 ZW |
5014 | inst.operands[i].reg = reg; |
5015 | inst.operands[i].isreg = 1; | |
09d92015 | 5016 | |
c19d1205 | 5017 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5018 | { |
c19d1205 | 5019 | inst.operands[i].preind = 1; |
09d92015 | 5020 | |
c19d1205 ZW |
5021 | if (*p == '+') p++; |
5022 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
5023 | ||
dcbf9037 | 5024 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
09d92015 | 5025 | { |
c19d1205 ZW |
5026 | inst.operands[i].imm = reg; |
5027 | inst.operands[i].immisreg = 1; | |
5028 | ||
5029 | if (skip_past_comma (&p) == SUCCESS) | |
5030 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5031 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5032 | } |
5287ad62 JB |
5033 | else if (skip_past_char (&p, ':') == SUCCESS) |
5034 | { | |
5035 | /* FIXME: '@' should be used here, but it's filtered out by generic | |
5036 | code before we get to see it here. This may be subject to | |
5037 | change. */ | |
5038 | expressionS exp; | |
5039 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
5040 | if (exp.X_op != O_constant) | |
5041 | { | |
5042 | inst.error = _("alignment must be constant"); | |
4962c51a | 5043 | return PARSE_OPERAND_FAIL; |
5287ad62 JB |
5044 | } |
5045 | inst.operands[i].imm = exp.X_add_number << 8; | |
5046 | inst.operands[i].immisalign = 1; | |
5047 | /* Alignments are not pre-indexes. */ | |
5048 | inst.operands[i].preind = 0; | |
5049 | } | |
c19d1205 ZW |
5050 | else |
5051 | { | |
5052 | if (inst.operands[i].negative) | |
5053 | { | |
5054 | inst.operands[i].negative = 0; | |
5055 | p--; | |
5056 | } | |
4962c51a | 5057 | |
5f4273c7 NC |
5058 | if (group_relocations |
5059 | && ((*p == '#' && *(p + 1) == ':') || *p == ':')) | |
4962c51a MS |
5060 | { |
5061 | struct group_reloc_table_entry *entry; | |
5062 | ||
5063 | /* Skip over the #: or : sequence. */ | |
5064 | if (*p == '#') | |
5065 | p += 2; | |
5066 | else | |
5067 | p++; | |
5068 | ||
5069 | /* Try to parse a group relocation. Anything else is an | |
5070 | error. */ | |
5071 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) | |
5072 | { | |
5073 | inst.error = _("unknown group relocation"); | |
5074 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5075 | } | |
5076 | ||
5077 | /* We now have the group relocation table entry corresponding to | |
5078 | the name in the assembler source. Next, we parse the | |
5079 | expression. */ | |
5080 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5081 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5082 | ||
5083 | /* Record the relocation type. */ | |
5084 | switch (group_type) | |
5085 | { | |
5086 | case GROUP_LDR: | |
21d799b5 | 5087 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code; |
4962c51a MS |
5088 | break; |
5089 | ||
5090 | case GROUP_LDRS: | |
21d799b5 | 5091 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code; |
4962c51a MS |
5092 | break; |
5093 | ||
5094 | case GROUP_LDC: | |
21d799b5 | 5095 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code; |
4962c51a MS |
5096 | break; |
5097 | ||
5098 | default: | |
9c2799c2 | 5099 | gas_assert (0); |
4962c51a MS |
5100 | } |
5101 | ||
5102 | if (inst.reloc.type == 0) | |
5103 | { | |
5104 | inst.error = _("this group relocation is not allowed on this instruction"); | |
5105 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5106 | } | |
5107 | } | |
5108 | else | |
5109 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
5110 | return PARSE_OPERAND_FAIL; | |
09d92015 MM |
5111 | } |
5112 | } | |
5113 | ||
c19d1205 | 5114 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 5115 | { |
c19d1205 | 5116 | inst.error = _("']' expected"); |
4962c51a | 5117 | return PARSE_OPERAND_FAIL; |
09d92015 MM |
5118 | } |
5119 | ||
c19d1205 ZW |
5120 | if (skip_past_char (&p, '!') == SUCCESS) |
5121 | inst.operands[i].writeback = 1; | |
09d92015 | 5122 | |
c19d1205 | 5123 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5124 | { |
c19d1205 ZW |
5125 | if (skip_past_char (&p, '{') == SUCCESS) |
5126 | { | |
5127 | /* [Rn], {expr} - unindexed, with option */ | |
5128 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 5129 | 0, 255, TRUE) == FAIL) |
4962c51a | 5130 | return PARSE_OPERAND_FAIL; |
09d92015 | 5131 | |
c19d1205 ZW |
5132 | if (skip_past_char (&p, '}') == FAIL) |
5133 | { | |
5134 | inst.error = _("'}' expected at end of 'option' field"); | |
4962c51a | 5135 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5136 | } |
5137 | if (inst.operands[i].preind) | |
5138 | { | |
5139 | inst.error = _("cannot combine index with option"); | |
4962c51a | 5140 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5141 | } |
5142 | *str = p; | |
4962c51a | 5143 | return PARSE_OPERAND_SUCCESS; |
09d92015 | 5144 | } |
c19d1205 ZW |
5145 | else |
5146 | { | |
5147 | inst.operands[i].postind = 1; | |
5148 | inst.operands[i].writeback = 1; | |
09d92015 | 5149 | |
c19d1205 ZW |
5150 | if (inst.operands[i].preind) |
5151 | { | |
5152 | inst.error = _("cannot combine pre- and post-indexing"); | |
4962c51a | 5153 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5154 | } |
09d92015 | 5155 | |
c19d1205 ZW |
5156 | if (*p == '+') p++; |
5157 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 5158 | |
dcbf9037 | 5159 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 | 5160 | { |
5287ad62 JB |
5161 | /* We might be using the immediate for alignment already. If we |
5162 | are, OR the register number into the low-order bits. */ | |
5163 | if (inst.operands[i].immisalign) | |
5164 | inst.operands[i].imm |= reg; | |
5165 | else | |
5166 | inst.operands[i].imm = reg; | |
c19d1205 | 5167 | inst.operands[i].immisreg = 1; |
a737bd4d | 5168 | |
c19d1205 ZW |
5169 | if (skip_past_comma (&p) == SUCCESS) |
5170 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5171 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5172 | } |
5173 | else | |
5174 | { | |
5175 | if (inst.operands[i].negative) | |
5176 | { | |
5177 | inst.operands[i].negative = 0; | |
5178 | p--; | |
5179 | } | |
5180 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4962c51a | 5181 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5182 | } |
5183 | } | |
a737bd4d NC |
5184 | } |
5185 | ||
c19d1205 ZW |
5186 | /* If at this point neither .preind nor .postind is set, we have a |
5187 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
5188 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
5189 | { | |
5190 | inst.operands[i].preind = 1; | |
5191 | inst.reloc.exp.X_op = O_constant; | |
5192 | inst.reloc.exp.X_add_number = 0; | |
5193 | } | |
5194 | *str = p; | |
4962c51a MS |
5195 | return PARSE_OPERAND_SUCCESS; |
5196 | } | |
5197 | ||
5198 | static int | |
5199 | parse_address (char **str, int i) | |
5200 | { | |
21d799b5 | 5201 | return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS |
4962c51a MS |
5202 | ? SUCCESS : FAIL; |
5203 | } | |
5204 | ||
5205 | static parse_operand_result | |
5206 | parse_address_group_reloc (char **str, int i, group_reloc_type type) | |
5207 | { | |
5208 | return parse_address_main (str, i, 1, type); | |
a737bd4d NC |
5209 | } |
5210 | ||
b6895b4f PB |
5211 | /* Parse an operand for a MOVW or MOVT instruction. */ |
5212 | static int | |
5213 | parse_half (char **str) | |
5214 | { | |
5215 | char * p; | |
5f4273c7 | 5216 | |
b6895b4f PB |
5217 | p = *str; |
5218 | skip_past_char (&p, '#'); | |
5f4273c7 | 5219 | if (strncasecmp (p, ":lower16:", 9) == 0) |
b6895b4f PB |
5220 | inst.reloc.type = BFD_RELOC_ARM_MOVW; |
5221 | else if (strncasecmp (p, ":upper16:", 9) == 0) | |
5222 | inst.reloc.type = BFD_RELOC_ARM_MOVT; | |
5223 | ||
5224 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
5225 | { | |
5226 | p += 9; | |
5f4273c7 | 5227 | skip_whitespace (p); |
b6895b4f PB |
5228 | } |
5229 | ||
5230 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5231 | return FAIL; | |
5232 | ||
5233 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
5234 | { | |
5235 | if (inst.reloc.exp.X_op != O_constant) | |
5236 | { | |
5237 | inst.error = _("constant expression expected"); | |
5238 | return FAIL; | |
5239 | } | |
5240 | if (inst.reloc.exp.X_add_number < 0 | |
5241 | || inst.reloc.exp.X_add_number > 0xffff) | |
5242 | { | |
5243 | inst.error = _("immediate value out of range"); | |
5244 | return FAIL; | |
5245 | } | |
5246 | } | |
5247 | *str = p; | |
5248 | return SUCCESS; | |
5249 | } | |
5250 | ||
c19d1205 | 5251 | /* Miscellaneous. */ |
a737bd4d | 5252 | |
c19d1205 ZW |
5253 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
5254 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
5255 | static int | |
5256 | parse_psr (char **str) | |
09d92015 | 5257 | { |
c19d1205 ZW |
5258 | char *p; |
5259 | unsigned long psr_field; | |
62b3e311 PB |
5260 | const struct asm_psr *psr; |
5261 | char *start; | |
09d92015 | 5262 | |
c19d1205 ZW |
5263 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
5264 | feature for ease of use and backwards compatibility. */ | |
5265 | p = *str; | |
62b3e311 | 5266 | if (strncasecmp (p, "SPSR", 4) == 0) |
c19d1205 | 5267 | psr_field = SPSR_BIT; |
62b3e311 | 5268 | else if (strncasecmp (p, "CPSR", 4) == 0) |
c19d1205 ZW |
5269 | psr_field = 0; |
5270 | else | |
62b3e311 PB |
5271 | { |
5272 | start = p; | |
5273 | do | |
5274 | p++; | |
5275 | while (ISALNUM (*p) || *p == '_'); | |
5276 | ||
21d799b5 NC |
5277 | psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start, |
5278 | p - start); | |
62b3e311 PB |
5279 | if (!psr) |
5280 | return FAIL; | |
09d92015 | 5281 | |
62b3e311 PB |
5282 | *str = p; |
5283 | return psr->field; | |
5284 | } | |
09d92015 | 5285 | |
62b3e311 | 5286 | p += 4; |
c19d1205 ZW |
5287 | if (*p == '_') |
5288 | { | |
5289 | /* A suffix follows. */ | |
c19d1205 ZW |
5290 | p++; |
5291 | start = p; | |
a737bd4d | 5292 | |
c19d1205 ZW |
5293 | do |
5294 | p++; | |
5295 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 5296 | |
21d799b5 NC |
5297 | psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start, |
5298 | p - start); | |
c19d1205 ZW |
5299 | if (!psr) |
5300 | goto error; | |
a737bd4d | 5301 | |
c19d1205 | 5302 | psr_field |= psr->field; |
a737bd4d | 5303 | } |
c19d1205 | 5304 | else |
a737bd4d | 5305 | { |
c19d1205 ZW |
5306 | if (ISALNUM (*p)) |
5307 | goto error; /* Garbage after "[CS]PSR". */ | |
5308 | ||
5309 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 5310 | } |
c19d1205 ZW |
5311 | *str = p; |
5312 | return psr_field; | |
a737bd4d | 5313 | |
c19d1205 ZW |
5314 | error: |
5315 | inst.error = _("flag for {c}psr instruction expected"); | |
5316 | return FAIL; | |
a737bd4d NC |
5317 | } |
5318 | ||
c19d1205 ZW |
5319 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
5320 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 5321 | |
c19d1205 ZW |
5322 | static int |
5323 | parse_cps_flags (char **str) | |
a737bd4d | 5324 | { |
c19d1205 ZW |
5325 | int val = 0; |
5326 | int saw_a_flag = 0; | |
5327 | char *s = *str; | |
a737bd4d | 5328 | |
c19d1205 ZW |
5329 | for (;;) |
5330 | switch (*s++) | |
5331 | { | |
5332 | case '\0': case ',': | |
5333 | goto done; | |
a737bd4d | 5334 | |
c19d1205 ZW |
5335 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
5336 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
5337 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 5338 | |
c19d1205 ZW |
5339 | default: |
5340 | inst.error = _("unrecognized CPS flag"); | |
5341 | return FAIL; | |
5342 | } | |
a737bd4d | 5343 | |
c19d1205 ZW |
5344 | done: |
5345 | if (saw_a_flag == 0) | |
a737bd4d | 5346 | { |
c19d1205 ZW |
5347 | inst.error = _("missing CPS flags"); |
5348 | return FAIL; | |
a737bd4d | 5349 | } |
a737bd4d | 5350 | |
c19d1205 ZW |
5351 | *str = s - 1; |
5352 | return val; | |
a737bd4d NC |
5353 | } |
5354 | ||
c19d1205 ZW |
5355 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
5356 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
5357 | |
5358 | static int | |
c19d1205 | 5359 | parse_endian_specifier (char **str) |
a737bd4d | 5360 | { |
c19d1205 ZW |
5361 | int little_endian; |
5362 | char *s = *str; | |
a737bd4d | 5363 | |
c19d1205 ZW |
5364 | if (strncasecmp (s, "BE", 2)) |
5365 | little_endian = 0; | |
5366 | else if (strncasecmp (s, "LE", 2)) | |
5367 | little_endian = 1; | |
5368 | else | |
a737bd4d | 5369 | { |
c19d1205 | 5370 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5371 | return FAIL; |
5372 | } | |
5373 | ||
c19d1205 | 5374 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 5375 | { |
c19d1205 | 5376 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5377 | return FAIL; |
5378 | } | |
5379 | ||
c19d1205 ZW |
5380 | *str = s + 2; |
5381 | return little_endian; | |
5382 | } | |
a737bd4d | 5383 | |
c19d1205 ZW |
5384 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
5385 | value suitable for poking into the rotate field of an sxt or sxta | |
5386 | instruction, or FAIL on error. */ | |
5387 | ||
5388 | static int | |
5389 | parse_ror (char **str) | |
5390 | { | |
5391 | int rot; | |
5392 | char *s = *str; | |
5393 | ||
5394 | if (strncasecmp (s, "ROR", 3) == 0) | |
5395 | s += 3; | |
5396 | else | |
a737bd4d | 5397 | { |
c19d1205 | 5398 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
5399 | return FAIL; |
5400 | } | |
c19d1205 ZW |
5401 | |
5402 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
5403 | return FAIL; | |
5404 | ||
5405 | switch (rot) | |
a737bd4d | 5406 | { |
c19d1205 ZW |
5407 | case 0: *str = s; return 0x0; |
5408 | case 8: *str = s; return 0x1; | |
5409 | case 16: *str = s; return 0x2; | |
5410 | case 24: *str = s; return 0x3; | |
5411 | ||
5412 | default: | |
5413 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
5414 | return FAIL; |
5415 | } | |
c19d1205 | 5416 | } |
a737bd4d | 5417 | |
c19d1205 ZW |
5418 | /* Parse a conditional code (from conds[] below). The value returned is in the |
5419 | range 0 .. 14, or FAIL. */ | |
5420 | static int | |
5421 | parse_cond (char **str) | |
5422 | { | |
c462b453 | 5423 | char *q; |
c19d1205 | 5424 | const struct asm_cond *c; |
c462b453 PB |
5425 | int n; |
5426 | /* Condition codes are always 2 characters, so matching up to | |
5427 | 3 characters is sufficient. */ | |
5428 | char cond[3]; | |
a737bd4d | 5429 | |
c462b453 PB |
5430 | q = *str; |
5431 | n = 0; | |
5432 | while (ISALPHA (*q) && n < 3) | |
5433 | { | |
e07e6e58 | 5434 | cond[n] = TOLOWER (*q); |
c462b453 PB |
5435 | q++; |
5436 | n++; | |
5437 | } | |
a737bd4d | 5438 | |
21d799b5 | 5439 | c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n); |
c19d1205 | 5440 | if (!c) |
a737bd4d | 5441 | { |
c19d1205 | 5442 | inst.error = _("condition required"); |
a737bd4d NC |
5443 | return FAIL; |
5444 | } | |
5445 | ||
c19d1205 ZW |
5446 | *str = q; |
5447 | return c->value; | |
5448 | } | |
5449 | ||
62b3e311 PB |
5450 | /* Parse an option for a barrier instruction. Returns the encoding for the |
5451 | option, or FAIL. */ | |
5452 | static int | |
5453 | parse_barrier (char **str) | |
5454 | { | |
5455 | char *p, *q; | |
5456 | const struct asm_barrier_opt *o; | |
5457 | ||
5458 | p = q = *str; | |
5459 | while (ISALPHA (*q)) | |
5460 | q++; | |
5461 | ||
21d799b5 NC |
5462 | o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p, |
5463 | q - p); | |
62b3e311 PB |
5464 | if (!o) |
5465 | return FAIL; | |
5466 | ||
5467 | *str = q; | |
5468 | return o->value; | |
5469 | } | |
5470 | ||
92e90b6e PB |
5471 | /* Parse the operands of a table branch instruction. Similar to a memory |
5472 | operand. */ | |
5473 | static int | |
5474 | parse_tb (char **str) | |
5475 | { | |
5476 | char * p = *str; | |
5477 | int reg; | |
5478 | ||
5479 | if (skip_past_char (&p, '[') == FAIL) | |
ab1eb5fe PB |
5480 | { |
5481 | inst.error = _("'[' expected"); | |
5482 | return FAIL; | |
5483 | } | |
92e90b6e | 5484 | |
dcbf9037 | 5485 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5486 | { |
5487 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5488 | return FAIL; | |
5489 | } | |
5490 | inst.operands[0].reg = reg; | |
5491 | ||
5492 | if (skip_past_comma (&p) == FAIL) | |
ab1eb5fe PB |
5493 | { |
5494 | inst.error = _("',' expected"); | |
5495 | return FAIL; | |
5496 | } | |
5f4273c7 | 5497 | |
dcbf9037 | 5498 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5499 | { |
5500 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5501 | return FAIL; | |
5502 | } | |
5503 | inst.operands[0].imm = reg; | |
5504 | ||
5505 | if (skip_past_comma (&p) == SUCCESS) | |
5506 | { | |
5507 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
5508 | return FAIL; | |
5509 | if (inst.reloc.exp.X_add_number != 1) | |
5510 | { | |
5511 | inst.error = _("invalid shift"); | |
5512 | return FAIL; | |
5513 | } | |
5514 | inst.operands[0].shifted = 1; | |
5515 | } | |
5516 | ||
5517 | if (skip_past_char (&p, ']') == FAIL) | |
5518 | { | |
5519 | inst.error = _("']' expected"); | |
5520 | return FAIL; | |
5521 | } | |
5522 | *str = p; | |
5523 | return SUCCESS; | |
5524 | } | |
5525 | ||
5287ad62 JB |
5526 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
5527 | information on the types the operands can take and how they are encoded. | |
037e8744 JB |
5528 | Up to four operands may be read; this function handles setting the |
5529 | ".present" field for each read operand itself. | |
5287ad62 JB |
5530 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
5531 | else returns FAIL. */ | |
5532 | ||
5533 | static int | |
5534 | parse_neon_mov (char **str, int *which_operand) | |
5535 | { | |
5536 | int i = *which_operand, val; | |
5537 | enum arm_reg_type rtype; | |
5538 | char *ptr = *str; | |
dcbf9037 | 5539 | struct neon_type_el optype; |
5f4273c7 | 5540 | |
dcbf9037 | 5541 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5542 | { |
5543 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ | |
5544 | inst.operands[i].reg = val; | |
5545 | inst.operands[i].isscalar = 1; | |
dcbf9037 | 5546 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5547 | inst.operands[i++].present = 1; |
5548 | ||
5549 | if (skip_past_comma (&ptr) == FAIL) | |
5550 | goto wanted_comma; | |
5f4273c7 | 5551 | |
dcbf9037 | 5552 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5287ad62 | 5553 | goto wanted_arm; |
5f4273c7 | 5554 | |
5287ad62 JB |
5555 | inst.operands[i].reg = val; |
5556 | inst.operands[i].isreg = 1; | |
5557 | inst.operands[i].present = 1; | |
5558 | } | |
037e8744 | 5559 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
dcbf9037 | 5560 | != FAIL) |
5287ad62 JB |
5561 | { |
5562 | /* Cases 0, 1, 2, 3, 5 (D only). */ | |
5563 | if (skip_past_comma (&ptr) == FAIL) | |
5564 | goto wanted_comma; | |
5f4273c7 | 5565 | |
5287ad62 JB |
5566 | inst.operands[i].reg = val; |
5567 | inst.operands[i].isreg = 1; | |
5568 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5569 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5570 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5571 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5572 | inst.operands[i++].present = 1; |
5573 | ||
dcbf9037 | 5574 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 | 5575 | { |
037e8744 JB |
5576 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. |
5577 | Case 13: VMOV <Sd>, <Rm> */ | |
5287ad62 JB |
5578 | inst.operands[i].reg = val; |
5579 | inst.operands[i].isreg = 1; | |
037e8744 | 5580 | inst.operands[i].present = 1; |
5287ad62 JB |
5581 | |
5582 | if (rtype == REG_TYPE_NQ) | |
5583 | { | |
dcbf9037 | 5584 | first_error (_("can't use Neon quad register here")); |
5287ad62 JB |
5585 | return FAIL; |
5586 | } | |
037e8744 JB |
5587 | else if (rtype != REG_TYPE_VFS) |
5588 | { | |
5589 | i++; | |
5590 | if (skip_past_comma (&ptr) == FAIL) | |
5591 | goto wanted_comma; | |
5592 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5593 | goto wanted_arm; | |
5594 | inst.operands[i].reg = val; | |
5595 | inst.operands[i].isreg = 1; | |
5596 | inst.operands[i].present = 1; | |
5597 | } | |
5287ad62 | 5598 | } |
037e8744 JB |
5599 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, |
5600 | &optype)) != FAIL) | |
5287ad62 JB |
5601 | { |
5602 | /* Case 0: VMOV<c><q> <Qd>, <Qm> | |
037e8744 JB |
5603 | Case 1: VMOV<c><q> <Dd>, <Dm> |
5604 | Case 8: VMOV.F32 <Sd>, <Sm> | |
5605 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ | |
5287ad62 JB |
5606 | |
5607 | inst.operands[i].reg = val; | |
5608 | inst.operands[i].isreg = 1; | |
5609 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5610 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5611 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5612 | inst.operands[i].vectype = optype; |
5287ad62 | 5613 | inst.operands[i].present = 1; |
5f4273c7 | 5614 | |
037e8744 JB |
5615 | if (skip_past_comma (&ptr) == SUCCESS) |
5616 | { | |
5617 | /* Case 15. */ | |
5618 | i++; | |
5619 | ||
5620 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5621 | goto wanted_arm; | |
5622 | ||
5623 | inst.operands[i].reg = val; | |
5624 | inst.operands[i].isreg = 1; | |
5625 | inst.operands[i++].present = 1; | |
5f4273c7 | 5626 | |
037e8744 JB |
5627 | if (skip_past_comma (&ptr) == FAIL) |
5628 | goto wanted_comma; | |
5f4273c7 | 5629 | |
037e8744 JB |
5630 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5631 | goto wanted_arm; | |
5f4273c7 | 5632 | |
037e8744 JB |
5633 | inst.operands[i].reg = val; |
5634 | inst.operands[i].isreg = 1; | |
5635 | inst.operands[i++].present = 1; | |
5636 | } | |
5287ad62 | 5637 | } |
4641781c PB |
5638 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
5639 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> | |
5640 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> | |
5641 | Case 10: VMOV.F32 <Sd>, #<imm> | |
5642 | Case 11: VMOV.F64 <Dd>, #<imm> */ | |
5643 | inst.operands[i].immisfloat = 1; | |
5644 | else if (parse_big_immediate (&ptr, i) == SUCCESS) | |
5645 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> | |
5646 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ | |
5647 | ; | |
5287ad62 JB |
5648 | else |
5649 | { | |
dcbf9037 | 5650 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); |
5287ad62 JB |
5651 | return FAIL; |
5652 | } | |
5653 | } | |
dcbf9037 | 5654 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5655 | { |
5656 | /* Cases 6, 7. */ | |
5657 | inst.operands[i].reg = val; | |
5658 | inst.operands[i].isreg = 1; | |
5659 | inst.operands[i++].present = 1; | |
5f4273c7 | 5660 | |
5287ad62 JB |
5661 | if (skip_past_comma (&ptr) == FAIL) |
5662 | goto wanted_comma; | |
5f4273c7 | 5663 | |
dcbf9037 | 5664 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5665 | { |
5666 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ | |
5667 | inst.operands[i].reg = val; | |
5668 | inst.operands[i].isscalar = 1; | |
5669 | inst.operands[i].present = 1; | |
dcbf9037 | 5670 | inst.operands[i].vectype = optype; |
5287ad62 | 5671 | } |
dcbf9037 | 5672 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5673 | { |
5674 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ | |
5675 | inst.operands[i].reg = val; | |
5676 | inst.operands[i].isreg = 1; | |
5677 | inst.operands[i++].present = 1; | |
5f4273c7 | 5678 | |
5287ad62 JB |
5679 | if (skip_past_comma (&ptr) == FAIL) |
5680 | goto wanted_comma; | |
5f4273c7 | 5681 | |
037e8744 | 5682 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) |
dcbf9037 | 5683 | == FAIL) |
5287ad62 | 5684 | { |
037e8744 | 5685 | first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); |
5287ad62 JB |
5686 | return FAIL; |
5687 | } | |
5688 | ||
5689 | inst.operands[i].reg = val; | |
5690 | inst.operands[i].isreg = 1; | |
037e8744 JB |
5691 | inst.operands[i].isvec = 1; |
5692 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
dcbf9037 | 5693 | inst.operands[i].vectype = optype; |
5287ad62 | 5694 | inst.operands[i].present = 1; |
5f4273c7 | 5695 | |
037e8744 JB |
5696 | if (rtype == REG_TYPE_VFS) |
5697 | { | |
5698 | /* Case 14. */ | |
5699 | i++; | |
5700 | if (skip_past_comma (&ptr) == FAIL) | |
5701 | goto wanted_comma; | |
5702 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, | |
5703 | &optype)) == FAIL) | |
5704 | { | |
5705 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); | |
5706 | return FAIL; | |
5707 | } | |
5708 | inst.operands[i].reg = val; | |
5709 | inst.operands[i].isreg = 1; | |
5710 | inst.operands[i].isvec = 1; | |
5711 | inst.operands[i].issingle = 1; | |
5712 | inst.operands[i].vectype = optype; | |
5713 | inst.operands[i].present = 1; | |
5714 | } | |
5715 | } | |
5716 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) | |
5717 | != FAIL) | |
5718 | { | |
5719 | /* Case 13. */ | |
5720 | inst.operands[i].reg = val; | |
5721 | inst.operands[i].isreg = 1; | |
5722 | inst.operands[i].isvec = 1; | |
5723 | inst.operands[i].issingle = 1; | |
5724 | inst.operands[i].vectype = optype; | |
5725 | inst.operands[i++].present = 1; | |
5287ad62 JB |
5726 | } |
5727 | } | |
5728 | else | |
5729 | { | |
dcbf9037 | 5730 | first_error (_("parse error")); |
5287ad62 JB |
5731 | return FAIL; |
5732 | } | |
5733 | ||
5734 | /* Successfully parsed the operands. Update args. */ | |
5735 | *which_operand = i; | |
5736 | *str = ptr; | |
5737 | return SUCCESS; | |
5738 | ||
5f4273c7 | 5739 | wanted_comma: |
dcbf9037 | 5740 | first_error (_("expected comma")); |
5287ad62 | 5741 | return FAIL; |
5f4273c7 NC |
5742 | |
5743 | wanted_arm: | |
dcbf9037 | 5744 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
5287ad62 | 5745 | return FAIL; |
5287ad62 JB |
5746 | } |
5747 | ||
5be8be5d DG |
5748 | /* Use this macro when the operand constraints are different |
5749 | for ARM and THUMB (e.g. ldrd). */ | |
5750 | #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \ | |
5751 | ((arm_operand) | ((thumb_operand) << 16)) | |
5752 | ||
c19d1205 ZW |
5753 | /* Matcher codes for parse_operands. */ |
5754 | enum operand_parse_code | |
5755 | { | |
5756 | OP_stop, /* end of line */ | |
5757 | ||
5758 | OP_RR, /* ARM register */ | |
5759 | OP_RRnpc, /* ARM register, not r15 */ | |
5be8be5d | 5760 | OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */ |
c19d1205 ZW |
5761 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ |
5762 | OP_RRw, /* ARM register, not r15, optional trailing ! */ | |
5763 | OP_RCP, /* Coprocessor number */ | |
5764 | OP_RCN, /* Coprocessor register */ | |
5765 | OP_RF, /* FPA register */ | |
5766 | OP_RVS, /* VFP single precision register */ | |
5287ad62 JB |
5767 | OP_RVD, /* VFP double precision register (0..15) */ |
5768 | OP_RND, /* Neon double precision register (0..31) */ | |
5769 | OP_RNQ, /* Neon quad precision register */ | |
037e8744 | 5770 | OP_RVSD, /* VFP single or double precision register */ |
5287ad62 | 5771 | OP_RNDQ, /* Neon double or quad precision register */ |
037e8744 | 5772 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
5287ad62 | 5773 | OP_RNSC, /* Neon scalar D[X] */ |
c19d1205 ZW |
5774 | OP_RVC, /* VFP control register */ |
5775 | OP_RMF, /* Maverick F register */ | |
5776 | OP_RMD, /* Maverick D register */ | |
5777 | OP_RMFX, /* Maverick FX register */ | |
5778 | OP_RMDX, /* Maverick DX register */ | |
5779 | OP_RMAX, /* Maverick AX register */ | |
5780 | OP_RMDS, /* Maverick DSPSC register */ | |
5781 | OP_RIWR, /* iWMMXt wR register */ | |
5782 | OP_RIWC, /* iWMMXt wC register */ | |
5783 | OP_RIWG, /* iWMMXt wCG register */ | |
5784 | OP_RXA, /* XScale accumulator register */ | |
5785 | ||
5786 | OP_REGLST, /* ARM register list */ | |
5787 | OP_VRSLST, /* VFP single-precision register list */ | |
5788 | OP_VRDLST, /* VFP double-precision register list */ | |
037e8744 | 5789 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
5287ad62 JB |
5790 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
5791 | OP_NSTRLST, /* Neon element/structure list */ | |
5792 | ||
5287ad62 | 5793 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ |
037e8744 | 5794 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
5287ad62 | 5795 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
037e8744 | 5796 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
5287ad62 JB |
5797 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
5798 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ | |
5799 | OP_VMOV, /* Neon VMOV operands. */ | |
4316f0d2 | 5800 | OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ |
5287ad62 | 5801 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ |
2d447fca | 5802 | OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ |
5287ad62 JB |
5803 | |
5804 | OP_I0, /* immediate zero */ | |
c19d1205 ZW |
5805 | OP_I7, /* immediate value 0 .. 7 */ |
5806 | OP_I15, /* 0 .. 15 */ | |
5807 | OP_I16, /* 1 .. 16 */ | |
5287ad62 | 5808 | OP_I16z, /* 0 .. 16 */ |
c19d1205 ZW |
5809 | OP_I31, /* 0 .. 31 */ |
5810 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
5811 | OP_I32, /* 1 .. 32 */ | |
5287ad62 JB |
5812 | OP_I32z, /* 0 .. 32 */ |
5813 | OP_I63, /* 0 .. 63 */ | |
c19d1205 | 5814 | OP_I63s, /* -64 .. 63 */ |
5287ad62 JB |
5815 | OP_I64, /* 1 .. 64 */ |
5816 | OP_I64z, /* 0 .. 64 */ | |
c19d1205 | 5817 | OP_I255, /* 0 .. 255 */ |
c19d1205 ZW |
5818 | |
5819 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
5820 | OP_I7b, /* 0 .. 7 */ | |
5821 | OP_I15b, /* 0 .. 15 */ | |
5822 | OP_I31b, /* 0 .. 31 */ | |
5823 | ||
5824 | OP_SH, /* shifter operand */ | |
4962c51a | 5825 | OP_SHG, /* shifter operand with possible group relocation */ |
c19d1205 | 5826 | OP_ADDR, /* Memory address expression (any mode) */ |
4962c51a MS |
5827 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
5828 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ | |
5829 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ | |
c19d1205 ZW |
5830 | OP_EXP, /* arbitrary expression */ |
5831 | OP_EXPi, /* same, with optional immediate prefix */ | |
5832 | OP_EXPr, /* same, with optional relocation suffix */ | |
b6895b4f | 5833 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
c19d1205 ZW |
5834 | |
5835 | OP_CPSF, /* CPS flags */ | |
5836 | OP_ENDI, /* Endianness specifier */ | |
5837 | OP_PSR, /* CPSR/SPSR mask for msr */ | |
5838 | OP_COND, /* conditional code */ | |
92e90b6e | 5839 | OP_TB, /* Table branch. */ |
c19d1205 | 5840 | |
037e8744 JB |
5841 | OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */ |
5842 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ | |
5843 | ||
c19d1205 ZW |
5844 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
5845 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
5846 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
5847 | OP_RF_IF, /* FPA register or immediate */ | |
5848 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
41adaa5c | 5849 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
c19d1205 ZW |
5850 | |
5851 | /* Optional operands. */ | |
5852 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
5853 | OP_oI31b, /* 0 .. 31 */ | |
5287ad62 | 5854 | OP_oI32b, /* 1 .. 32 */ |
c19d1205 ZW |
5855 | OP_oIffffb, /* 0 .. 65535 */ |
5856 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
5857 | ||
5858 | OP_oRR, /* ARM register */ | |
5859 | OP_oRRnpc, /* ARM register, not the PC */ | |
5be8be5d | 5860 | OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ |
b6702015 | 5861 | OP_oRRw, /* ARM register, not r15, optional trailing ! */ |
5287ad62 JB |
5862 | OP_oRND, /* Optional Neon double precision register */ |
5863 | OP_oRNQ, /* Optional Neon quad precision register */ | |
5864 | OP_oRNDQ, /* Optional Neon double or quad precision register */ | |
037e8744 | 5865 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
c19d1205 ZW |
5866 | OP_oSHll, /* LSL immediate */ |
5867 | OP_oSHar, /* ASR immediate */ | |
5868 | OP_oSHllar, /* LSL or ASR immediate */ | |
5869 | OP_oROR, /* ROR 0/8/16/24 */ | |
62b3e311 | 5870 | OP_oBARRIER, /* Option argument for a barrier instruction. */ |
c19d1205 | 5871 | |
5be8be5d DG |
5872 | /* Some pre-defined mixed (ARM/THUMB) operands. */ |
5873 | OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp), | |
5874 | OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp), | |
5875 | OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp), | |
5876 | ||
c19d1205 ZW |
5877 | OP_FIRST_OPTIONAL = OP_oI7b |
5878 | }; | |
a737bd4d | 5879 | |
c19d1205 ZW |
5880 | /* Generic instruction operand parser. This does no encoding and no |
5881 | semantic validation; it merely squirrels values away in the inst | |
5882 | structure. Returns SUCCESS or FAIL depending on whether the | |
5883 | specified grammar matched. */ | |
5884 | static int | |
5be8be5d | 5885 | parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) |
c19d1205 | 5886 | { |
5be8be5d | 5887 | unsigned const int *upat = pattern; |
c19d1205 ZW |
5888 | char *backtrack_pos = 0; |
5889 | const char *backtrack_error = 0; | |
5890 | int i, val, backtrack_index = 0; | |
5287ad62 | 5891 | enum arm_reg_type rtype; |
4962c51a | 5892 | parse_operand_result result; |
5be8be5d | 5893 | unsigned int op_parse_code; |
c19d1205 | 5894 | |
e07e6e58 NC |
5895 | #define po_char_or_fail(chr) \ |
5896 | do \ | |
5897 | { \ | |
5898 | if (skip_past_char (&str, chr) == FAIL) \ | |
5899 | goto bad_args; \ | |
5900 | } \ | |
5901 | while (0) | |
c19d1205 | 5902 | |
e07e6e58 NC |
5903 | #define po_reg_or_fail(regtype) \ |
5904 | do \ | |
dcbf9037 | 5905 | { \ |
e07e6e58 NC |
5906 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
5907 | & inst.operands[i].vectype); \ | |
5908 | if (val == FAIL) \ | |
5909 | { \ | |
5910 | first_error (_(reg_expected_msgs[regtype])); \ | |
5911 | goto failure; \ | |
5912 | } \ | |
5913 | inst.operands[i].reg = val; \ | |
5914 | inst.operands[i].isreg = 1; \ | |
5915 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
5916 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
5917 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
5918 | || rtype == REG_TYPE_VFD \ | |
5919 | || rtype == REG_TYPE_NQ); \ | |
dcbf9037 | 5920 | } \ |
e07e6e58 NC |
5921 | while (0) |
5922 | ||
5923 | #define po_reg_or_goto(regtype, label) \ | |
5924 | do \ | |
5925 | { \ | |
5926 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ | |
5927 | & inst.operands[i].vectype); \ | |
5928 | if (val == FAIL) \ | |
5929 | goto label; \ | |
dcbf9037 | 5930 | \ |
e07e6e58 NC |
5931 | inst.operands[i].reg = val; \ |
5932 | inst.operands[i].isreg = 1; \ | |
5933 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
5934 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
5935 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
5936 | || rtype == REG_TYPE_VFD \ | |
5937 | || rtype == REG_TYPE_NQ); \ | |
5938 | } \ | |
5939 | while (0) | |
5940 | ||
5941 | #define po_imm_or_fail(min, max, popt) \ | |
5942 | do \ | |
5943 | { \ | |
5944 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
5945 | goto failure; \ | |
5946 | inst.operands[i].imm = val; \ | |
5947 | } \ | |
5948 | while (0) | |
5949 | ||
5950 | #define po_scalar_or_goto(elsz, label) \ | |
5951 | do \ | |
5952 | { \ | |
5953 | val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \ | |
5954 | if (val == FAIL) \ | |
5955 | goto label; \ | |
5956 | inst.operands[i].reg = val; \ | |
5957 | inst.operands[i].isscalar = 1; \ | |
5958 | } \ | |
5959 | while (0) | |
5960 | ||
5961 | #define po_misc_or_fail(expr) \ | |
5962 | do \ | |
5963 | { \ | |
5964 | if (expr) \ | |
5965 | goto failure; \ | |
5966 | } \ | |
5967 | while (0) | |
5968 | ||
5969 | #define po_misc_or_fail_no_backtrack(expr) \ | |
5970 | do \ | |
5971 | { \ | |
5972 | result = expr; \ | |
5973 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ | |
5974 | backtrack_pos = 0; \ | |
5975 | if (result != PARSE_OPERAND_SUCCESS) \ | |
5976 | goto failure; \ | |
5977 | } \ | |
5978 | while (0) | |
4962c51a | 5979 | |
c19d1205 ZW |
5980 | skip_whitespace (str); |
5981 | ||
5982 | for (i = 0; upat[i] != OP_stop; i++) | |
5983 | { | |
5be8be5d DG |
5984 | op_parse_code = upat[i]; |
5985 | if (op_parse_code >= 1<<16) | |
5986 | op_parse_code = thumb ? (op_parse_code >> 16) | |
5987 | : (op_parse_code & ((1<<16)-1)); | |
5988 | ||
5989 | if (op_parse_code >= OP_FIRST_OPTIONAL) | |
c19d1205 ZW |
5990 | { |
5991 | /* Remember where we are in case we need to backtrack. */ | |
9c2799c2 | 5992 | gas_assert (!backtrack_pos); |
c19d1205 ZW |
5993 | backtrack_pos = str; |
5994 | backtrack_error = inst.error; | |
5995 | backtrack_index = i; | |
5996 | } | |
5997 | ||
b6702015 | 5998 | if (i > 0 && (i > 1 || inst.operands[0].present)) |
c19d1205 ZW |
5999 | po_char_or_fail (','); |
6000 | ||
5be8be5d | 6001 | switch (op_parse_code) |
c19d1205 ZW |
6002 | { |
6003 | /* Registers */ | |
6004 | case OP_oRRnpc: | |
5be8be5d | 6005 | case OP_oRRnpcsp: |
c19d1205 | 6006 | case OP_RRnpc: |
5be8be5d | 6007 | case OP_RRnpcsp: |
c19d1205 ZW |
6008 | case OP_oRR: |
6009 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
6010 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
6011 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
6012 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
6013 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
6014 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
5287ad62 JB |
6015 | case OP_oRND: |
6016 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; | |
cd2cf30b PB |
6017 | case OP_RVC: |
6018 | po_reg_or_goto (REG_TYPE_VFC, coproc_reg); | |
6019 | break; | |
6020 | /* Also accept generic coprocessor regs for unknown registers. */ | |
6021 | coproc_reg: | |
6022 | po_reg_or_fail (REG_TYPE_CN); | |
6023 | break; | |
c19d1205 ZW |
6024 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; |
6025 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
6026 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
6027 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
6028 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
6029 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
6030 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
6031 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
6032 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
6033 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
5287ad62 JB |
6034 | case OP_oRNQ: |
6035 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; | |
6036 | case OP_oRNDQ: | |
6037 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; | |
037e8744 JB |
6038 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
6039 | case OP_oRNSDQ: | |
6040 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; | |
5287ad62 JB |
6041 | |
6042 | /* Neon scalar. Using an element size of 8 means that some invalid | |
6043 | scalars are accepted here, so deal with those in later code. */ | |
6044 | case OP_RNSC: po_scalar_or_goto (8, failure); break; | |
6045 | ||
5287ad62 JB |
6046 | case OP_RNDQ_I0: |
6047 | { | |
6048 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); | |
6049 | break; | |
6050 | try_imm0: | |
6051 | po_imm_or_fail (0, 0, TRUE); | |
6052 | } | |
6053 | break; | |
6054 | ||
037e8744 JB |
6055 | case OP_RVSD_I0: |
6056 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); | |
6057 | break; | |
6058 | ||
5287ad62 JB |
6059 | case OP_RR_RNSC: |
6060 | { | |
6061 | po_scalar_or_goto (8, try_rr); | |
6062 | break; | |
6063 | try_rr: | |
6064 | po_reg_or_fail (REG_TYPE_RN); | |
6065 | } | |
6066 | break; | |
6067 | ||
037e8744 JB |
6068 | case OP_RNSDQ_RNSC: |
6069 | { | |
6070 | po_scalar_or_goto (8, try_nsdq); | |
6071 | break; | |
6072 | try_nsdq: | |
6073 | po_reg_or_fail (REG_TYPE_NSDQ); | |
6074 | } | |
6075 | break; | |
6076 | ||
5287ad62 JB |
6077 | case OP_RNDQ_RNSC: |
6078 | { | |
6079 | po_scalar_or_goto (8, try_ndq); | |
6080 | break; | |
6081 | try_ndq: | |
6082 | po_reg_or_fail (REG_TYPE_NDQ); | |
6083 | } | |
6084 | break; | |
6085 | ||
6086 | case OP_RND_RNSC: | |
6087 | { | |
6088 | po_scalar_or_goto (8, try_vfd); | |
6089 | break; | |
6090 | try_vfd: | |
6091 | po_reg_or_fail (REG_TYPE_VFD); | |
6092 | } | |
6093 | break; | |
6094 | ||
6095 | case OP_VMOV: | |
6096 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're | |
6097 | not careful then bad things might happen. */ | |
6098 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); | |
6099 | break; | |
6100 | ||
4316f0d2 | 6101 | case OP_RNDQ_Ibig: |
5287ad62 | 6102 | { |
4316f0d2 | 6103 | po_reg_or_goto (REG_TYPE_NDQ, try_immbig); |
5287ad62 | 6104 | break; |
4316f0d2 | 6105 | try_immbig: |
5287ad62 JB |
6106 | /* There's a possibility of getting a 64-bit immediate here, so |
6107 | we need special handling. */ | |
6108 | if (parse_big_immediate (&str, i) == FAIL) | |
6109 | { | |
6110 | inst.error = _("immediate value is out of range"); | |
6111 | goto failure; | |
6112 | } | |
6113 | } | |
6114 | break; | |
6115 | ||
6116 | case OP_RNDQ_I63b: | |
6117 | { | |
6118 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); | |
6119 | break; | |
6120 | try_shimm: | |
6121 | po_imm_or_fail (0, 63, TRUE); | |
6122 | } | |
6123 | break; | |
c19d1205 ZW |
6124 | |
6125 | case OP_RRnpcb: | |
6126 | po_char_or_fail ('['); | |
6127 | po_reg_or_fail (REG_TYPE_RN); | |
6128 | po_char_or_fail (']'); | |
6129 | break; | |
a737bd4d | 6130 | |
c19d1205 | 6131 | case OP_RRw: |
b6702015 | 6132 | case OP_oRRw: |
c19d1205 ZW |
6133 | po_reg_or_fail (REG_TYPE_RN); |
6134 | if (skip_past_char (&str, '!') == SUCCESS) | |
6135 | inst.operands[i].writeback = 1; | |
6136 | break; | |
6137 | ||
6138 | /* Immediates */ | |
6139 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
6140 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
6141 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
5287ad62 | 6142 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
c19d1205 ZW |
6143 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
6144 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
5287ad62 | 6145 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
c19d1205 | 6146 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
5287ad62 JB |
6147 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
6148 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; | |
6149 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; | |
c19d1205 | 6150 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
c19d1205 ZW |
6151 | |
6152 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
6153 | case OP_oI7b: | |
6154 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
6155 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
6156 | case OP_oI31b: | |
6157 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
5287ad62 | 6158 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
c19d1205 ZW |
6159 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
6160 | ||
6161 | /* Immediate variants */ | |
6162 | case OP_oI255c: | |
6163 | po_char_or_fail ('{'); | |
6164 | po_imm_or_fail (0, 255, TRUE); | |
6165 | po_char_or_fail ('}'); | |
6166 | break; | |
6167 | ||
6168 | case OP_I31w: | |
6169 | /* The expression parser chokes on a trailing !, so we have | |
6170 | to find it first and zap it. */ | |
6171 | { | |
6172 | char *s = str; | |
6173 | while (*s && *s != ',') | |
6174 | s++; | |
6175 | if (s[-1] == '!') | |
6176 | { | |
6177 | s[-1] = '\0'; | |
6178 | inst.operands[i].writeback = 1; | |
6179 | } | |
6180 | po_imm_or_fail (0, 31, TRUE); | |
6181 | if (str == s - 1) | |
6182 | str = s; | |
6183 | } | |
6184 | break; | |
6185 | ||
6186 | /* Expressions */ | |
6187 | case OP_EXPi: EXPi: | |
6188 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6189 | GE_OPT_PREFIX)); | |
6190 | break; | |
6191 | ||
6192 | case OP_EXP: | |
6193 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6194 | GE_NO_PREFIX)); | |
6195 | break; | |
6196 | ||
6197 | case OP_EXPr: EXPr: | |
6198 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6199 | GE_NO_PREFIX)); | |
6200 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 6201 | { |
c19d1205 ZW |
6202 | val = parse_reloc (&str); |
6203 | if (val == -1) | |
6204 | { | |
6205 | inst.error = _("unrecognized relocation suffix"); | |
6206 | goto failure; | |
6207 | } | |
6208 | else if (val != BFD_RELOC_UNUSED) | |
6209 | { | |
6210 | inst.operands[i].imm = val; | |
6211 | inst.operands[i].hasreloc = 1; | |
6212 | } | |
a737bd4d | 6213 | } |
c19d1205 | 6214 | break; |
a737bd4d | 6215 | |
b6895b4f PB |
6216 | /* Operand for MOVW or MOVT. */ |
6217 | case OP_HALF: | |
6218 | po_misc_or_fail (parse_half (&str)); | |
6219 | break; | |
6220 | ||
e07e6e58 | 6221 | /* Register or expression. */ |
c19d1205 ZW |
6222 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; |
6223 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 6224 | |
e07e6e58 | 6225 | /* Register or immediate. */ |
c19d1205 ZW |
6226 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; |
6227 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 6228 | |
c19d1205 ZW |
6229 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
6230 | IF: | |
6231 | if (!is_immediate_prefix (*str)) | |
6232 | goto bad_args; | |
6233 | str++; | |
6234 | val = parse_fpa_immediate (&str); | |
6235 | if (val == FAIL) | |
6236 | goto failure; | |
6237 | /* FPA immediates are encoded as registers 8-15. | |
6238 | parse_fpa_immediate has already applied the offset. */ | |
6239 | inst.operands[i].reg = val; | |
6240 | inst.operands[i].isreg = 1; | |
6241 | break; | |
09d92015 | 6242 | |
2d447fca JM |
6243 | case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; |
6244 | I32z: po_imm_or_fail (0, 32, FALSE); break; | |
6245 | ||
e07e6e58 | 6246 | /* Two kinds of register. */ |
c19d1205 ZW |
6247 | case OP_RIWR_RIWC: |
6248 | { | |
6249 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
97f87066 JM |
6250 | if (!rege |
6251 | || (rege->type != REG_TYPE_MMXWR | |
6252 | && rege->type != REG_TYPE_MMXWC | |
6253 | && rege->type != REG_TYPE_MMXWCG)) | |
c19d1205 ZW |
6254 | { |
6255 | inst.error = _("iWMMXt data or control register expected"); | |
6256 | goto failure; | |
6257 | } | |
6258 | inst.operands[i].reg = rege->number; | |
6259 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
6260 | } | |
6261 | break; | |
09d92015 | 6262 | |
41adaa5c JM |
6263 | case OP_RIWC_RIWG: |
6264 | { | |
6265 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
6266 | if (!rege | |
6267 | || (rege->type != REG_TYPE_MMXWC | |
6268 | && rege->type != REG_TYPE_MMXWCG)) | |
6269 | { | |
6270 | inst.error = _("iWMMXt control register expected"); | |
6271 | goto failure; | |
6272 | } | |
6273 | inst.operands[i].reg = rege->number; | |
6274 | inst.operands[i].isreg = 1; | |
6275 | } | |
6276 | break; | |
6277 | ||
c19d1205 ZW |
6278 | /* Misc */ |
6279 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
6280 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
6281 | case OP_oROR: val = parse_ror (&str); break; | |
6282 | case OP_PSR: val = parse_psr (&str); break; | |
6283 | case OP_COND: val = parse_cond (&str); break; | |
62b3e311 | 6284 | case OP_oBARRIER:val = parse_barrier (&str); break; |
c19d1205 | 6285 | |
037e8744 JB |
6286 | case OP_RVC_PSR: |
6287 | po_reg_or_goto (REG_TYPE_VFC, try_psr); | |
6288 | inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */ | |
6289 | break; | |
6290 | try_psr: | |
6291 | val = parse_psr (&str); | |
6292 | break; | |
6293 | ||
6294 | case OP_APSR_RR: | |
6295 | po_reg_or_goto (REG_TYPE_RN, try_apsr); | |
6296 | break; | |
6297 | try_apsr: | |
6298 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS | |
6299 | instruction). */ | |
6300 | if (strncasecmp (str, "APSR_", 5) == 0) | |
6301 | { | |
6302 | unsigned found = 0; | |
6303 | str += 5; | |
6304 | while (found < 15) | |
6305 | switch (*str++) | |
6306 | { | |
6307 | case 'c': found = (found & 1) ? 16 : found | 1; break; | |
6308 | case 'n': found = (found & 2) ? 16 : found | 2; break; | |
6309 | case 'z': found = (found & 4) ? 16 : found | 4; break; | |
6310 | case 'v': found = (found & 8) ? 16 : found | 8; break; | |
6311 | default: found = 16; | |
6312 | } | |
6313 | if (found != 15) | |
6314 | goto failure; | |
6315 | inst.operands[i].isvec = 1; | |
f7c21dc7 NC |
6316 | /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */ |
6317 | inst.operands[i].reg = REG_PC; | |
037e8744 JB |
6318 | } |
6319 | else | |
6320 | goto failure; | |
6321 | break; | |
6322 | ||
92e90b6e PB |
6323 | case OP_TB: |
6324 | po_misc_or_fail (parse_tb (&str)); | |
6325 | break; | |
6326 | ||
e07e6e58 | 6327 | /* Register lists. */ |
c19d1205 ZW |
6328 | case OP_REGLST: |
6329 | val = parse_reg_list (&str); | |
6330 | if (*str == '^') | |
6331 | { | |
6332 | inst.operands[1].writeback = 1; | |
6333 | str++; | |
6334 | } | |
6335 | break; | |
09d92015 | 6336 | |
c19d1205 | 6337 | case OP_VRSLST: |
5287ad62 | 6338 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); |
c19d1205 | 6339 | break; |
09d92015 | 6340 | |
c19d1205 | 6341 | case OP_VRDLST: |
5287ad62 | 6342 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); |
c19d1205 | 6343 | break; |
a737bd4d | 6344 | |
037e8744 JB |
6345 | case OP_VRSDLST: |
6346 | /* Allow Q registers too. */ | |
6347 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6348 | REGLIST_NEON_D); | |
6349 | if (val == FAIL) | |
6350 | { | |
6351 | inst.error = NULL; | |
6352 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6353 | REGLIST_VFP_S); | |
6354 | inst.operands[i].issingle = 1; | |
6355 | } | |
6356 | break; | |
6357 | ||
5287ad62 JB |
6358 | case OP_NRDLST: |
6359 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6360 | REGLIST_NEON_D); | |
6361 | break; | |
6362 | ||
6363 | case OP_NSTRLST: | |
dcbf9037 JB |
6364 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
6365 | &inst.operands[i].vectype); | |
5287ad62 JB |
6366 | break; |
6367 | ||
c19d1205 ZW |
6368 | /* Addressing modes */ |
6369 | case OP_ADDR: | |
6370 | po_misc_or_fail (parse_address (&str, i)); | |
6371 | break; | |
09d92015 | 6372 | |
4962c51a MS |
6373 | case OP_ADDRGLDR: |
6374 | po_misc_or_fail_no_backtrack ( | |
6375 | parse_address_group_reloc (&str, i, GROUP_LDR)); | |
6376 | break; | |
6377 | ||
6378 | case OP_ADDRGLDRS: | |
6379 | po_misc_or_fail_no_backtrack ( | |
6380 | parse_address_group_reloc (&str, i, GROUP_LDRS)); | |
6381 | break; | |
6382 | ||
6383 | case OP_ADDRGLDC: | |
6384 | po_misc_or_fail_no_backtrack ( | |
6385 | parse_address_group_reloc (&str, i, GROUP_LDC)); | |
6386 | break; | |
6387 | ||
c19d1205 ZW |
6388 | case OP_SH: |
6389 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
6390 | break; | |
09d92015 | 6391 | |
4962c51a MS |
6392 | case OP_SHG: |
6393 | po_misc_or_fail_no_backtrack ( | |
6394 | parse_shifter_operand_group_reloc (&str, i)); | |
6395 | break; | |
6396 | ||
c19d1205 ZW |
6397 | case OP_oSHll: |
6398 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
6399 | break; | |
09d92015 | 6400 | |
c19d1205 ZW |
6401 | case OP_oSHar: |
6402 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
6403 | break; | |
09d92015 | 6404 | |
c19d1205 ZW |
6405 | case OP_oSHllar: |
6406 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
6407 | break; | |
09d92015 | 6408 | |
c19d1205 | 6409 | default: |
5be8be5d | 6410 | as_fatal (_("unhandled operand code %d"), op_parse_code); |
c19d1205 | 6411 | } |
09d92015 | 6412 | |
c19d1205 ZW |
6413 | /* Various value-based sanity checks and shared operations. We |
6414 | do not signal immediate failures for the register constraints; | |
6415 | this allows a syntax error to take precedence. */ | |
5be8be5d | 6416 | switch (op_parse_code) |
c19d1205 ZW |
6417 | { |
6418 | case OP_oRRnpc: | |
6419 | case OP_RRnpc: | |
6420 | case OP_RRnpcb: | |
6421 | case OP_RRw: | |
b6702015 | 6422 | case OP_oRRw: |
c19d1205 ZW |
6423 | case OP_RRnpc_I0: |
6424 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
6425 | inst.error = BAD_PC; | |
6426 | break; | |
09d92015 | 6427 | |
5be8be5d DG |
6428 | case OP_oRRnpcsp: |
6429 | case OP_RRnpcsp: | |
6430 | if (inst.operands[i].isreg) | |
6431 | { | |
6432 | if (inst.operands[i].reg == REG_PC) | |
6433 | inst.error = BAD_PC; | |
6434 | else if (inst.operands[i].reg == REG_SP) | |
6435 | inst.error = BAD_SP; | |
6436 | } | |
6437 | break; | |
6438 | ||
c19d1205 ZW |
6439 | case OP_CPSF: |
6440 | case OP_ENDI: | |
6441 | case OP_oROR: | |
6442 | case OP_PSR: | |
037e8744 | 6443 | case OP_RVC_PSR: |
c19d1205 | 6444 | case OP_COND: |
62b3e311 | 6445 | case OP_oBARRIER: |
c19d1205 ZW |
6446 | case OP_REGLST: |
6447 | case OP_VRSLST: | |
6448 | case OP_VRDLST: | |
037e8744 | 6449 | case OP_VRSDLST: |
5287ad62 JB |
6450 | case OP_NRDLST: |
6451 | case OP_NSTRLST: | |
c19d1205 ZW |
6452 | if (val == FAIL) |
6453 | goto failure; | |
6454 | inst.operands[i].imm = val; | |
6455 | break; | |
a737bd4d | 6456 | |
c19d1205 ZW |
6457 | default: |
6458 | break; | |
6459 | } | |
09d92015 | 6460 | |
c19d1205 ZW |
6461 | /* If we get here, this operand was successfully parsed. */ |
6462 | inst.operands[i].present = 1; | |
6463 | continue; | |
09d92015 | 6464 | |
c19d1205 | 6465 | bad_args: |
09d92015 | 6466 | inst.error = BAD_ARGS; |
c19d1205 ZW |
6467 | |
6468 | failure: | |
6469 | if (!backtrack_pos) | |
d252fdde PB |
6470 | { |
6471 | /* The parse routine should already have set inst.error, but set a | |
5f4273c7 | 6472 | default here just in case. */ |
d252fdde PB |
6473 | if (!inst.error) |
6474 | inst.error = _("syntax error"); | |
6475 | return FAIL; | |
6476 | } | |
c19d1205 ZW |
6477 | |
6478 | /* Do not backtrack over a trailing optional argument that | |
6479 | absorbed some text. We will only fail again, with the | |
6480 | 'garbage following instruction' error message, which is | |
6481 | probably less helpful than the current one. */ | |
6482 | if (backtrack_index == i && backtrack_pos != str | |
6483 | && upat[i+1] == OP_stop) | |
d252fdde PB |
6484 | { |
6485 | if (!inst.error) | |
6486 | inst.error = _("syntax error"); | |
6487 | return FAIL; | |
6488 | } | |
c19d1205 ZW |
6489 | |
6490 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
6491 | str = backtrack_pos; | |
6492 | inst.error = backtrack_error; | |
6493 | inst.operands[backtrack_index].present = 0; | |
6494 | i = backtrack_index; | |
6495 | backtrack_pos = 0; | |
09d92015 | 6496 | } |
09d92015 | 6497 | |
c19d1205 ZW |
6498 | /* Check that we have parsed all the arguments. */ |
6499 | if (*str != '\0' && !inst.error) | |
6500 | inst.error = _("garbage following instruction"); | |
09d92015 | 6501 | |
c19d1205 | 6502 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
6503 | } |
6504 | ||
c19d1205 ZW |
6505 | #undef po_char_or_fail |
6506 | #undef po_reg_or_fail | |
6507 | #undef po_reg_or_goto | |
6508 | #undef po_imm_or_fail | |
5287ad62 | 6509 | #undef po_scalar_or_fail |
e07e6e58 | 6510 | |
c19d1205 | 6511 | /* Shorthand macro for instruction encoding functions issuing errors. */ |
e07e6e58 NC |
6512 | #define constraint(expr, err) \ |
6513 | do \ | |
c19d1205 | 6514 | { \ |
e07e6e58 NC |
6515 | if (expr) \ |
6516 | { \ | |
6517 | inst.error = err; \ | |
6518 | return; \ | |
6519 | } \ | |
c19d1205 | 6520 | } \ |
e07e6e58 | 6521 | while (0) |
c19d1205 | 6522 | |
fdfde340 JM |
6523 | /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 |
6524 | instructions are unpredictable if these registers are used. This | |
6525 | is the BadReg predicate in ARM's Thumb-2 documentation. */ | |
6526 | #define reject_bad_reg(reg) \ | |
6527 | do \ | |
6528 | if (reg == REG_SP || reg == REG_PC) \ | |
6529 | { \ | |
6530 | inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \ | |
6531 | return; \ | |
6532 | } \ | |
6533 | while (0) | |
6534 | ||
94206790 MM |
6535 | /* If REG is R13 (the stack pointer), warn that its use is |
6536 | deprecated. */ | |
6537 | #define warn_deprecated_sp(reg) \ | |
6538 | do \ | |
6539 | if (warn_on_deprecated && reg == REG_SP) \ | |
6540 | as_warn (_("use of r13 is deprecated")); \ | |
6541 | while (0) | |
6542 | ||
c19d1205 ZW |
6543 | /* Functions for operand encoding. ARM, then Thumb. */ |
6544 | ||
6545 | #define rotate_left(v, n) (v << n | v >> (32 - n)) | |
6546 | ||
6547 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
6548 | return the encoded form. Otherwise, return FAIL. */ | |
6549 | ||
6550 | static unsigned int | |
6551 | encode_arm_immediate (unsigned int val) | |
09d92015 | 6552 | { |
c19d1205 ZW |
6553 | unsigned int a, i; |
6554 | ||
6555 | for (i = 0; i < 32; i += 2) | |
6556 | if ((a = rotate_left (val, i)) <= 0xff) | |
6557 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
6558 | ||
6559 | return FAIL; | |
09d92015 MM |
6560 | } |
6561 | ||
c19d1205 ZW |
6562 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
6563 | return the encoded form. Otherwise, return FAIL. */ | |
6564 | static unsigned int | |
6565 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 6566 | { |
c19d1205 | 6567 | unsigned int a, i; |
09d92015 | 6568 | |
9c3c69f2 | 6569 | if (val <= 0xff) |
c19d1205 | 6570 | return val; |
a737bd4d | 6571 | |
9c3c69f2 | 6572 | for (i = 1; i <= 24; i++) |
09d92015 | 6573 | { |
9c3c69f2 PB |
6574 | a = val >> i; |
6575 | if ((val & ~(0xff << i)) == 0) | |
6576 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 6577 | } |
a737bd4d | 6578 | |
c19d1205 ZW |
6579 | a = val & 0xff; |
6580 | if (val == ((a << 16) | a)) | |
6581 | return 0x100 | a; | |
6582 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
6583 | return 0x300 | a; | |
09d92015 | 6584 | |
c19d1205 ZW |
6585 | a = val & 0xff00; |
6586 | if (val == ((a << 16) | a)) | |
6587 | return 0x200 | (a >> 8); | |
a737bd4d | 6588 | |
c19d1205 | 6589 | return FAIL; |
09d92015 | 6590 | } |
5287ad62 | 6591 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
09d92015 MM |
6592 | |
6593 | static void | |
5287ad62 JB |
6594 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
6595 | { | |
6596 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) | |
6597 | && reg > 15) | |
6598 | { | |
b1cc4aeb | 6599 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
5287ad62 JB |
6600 | { |
6601 | if (thumb_mode) | |
6602 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 6603 | fpu_vfp_ext_d32); |
5287ad62 JB |
6604 | else |
6605 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 6606 | fpu_vfp_ext_d32); |
5287ad62 JB |
6607 | } |
6608 | else | |
6609 | { | |
dcbf9037 | 6610 | first_error (_("D register out of range for selected VFP version")); |
5287ad62 JB |
6611 | return; |
6612 | } | |
6613 | } | |
6614 | ||
c19d1205 | 6615 | switch (pos) |
09d92015 | 6616 | { |
c19d1205 ZW |
6617 | case VFP_REG_Sd: |
6618 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
6619 | break; | |
6620 | ||
6621 | case VFP_REG_Sn: | |
6622 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
6623 | break; | |
6624 | ||
6625 | case VFP_REG_Sm: | |
6626 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
6627 | break; | |
6628 | ||
5287ad62 JB |
6629 | case VFP_REG_Dd: |
6630 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); | |
6631 | break; | |
5f4273c7 | 6632 | |
5287ad62 JB |
6633 | case VFP_REG_Dn: |
6634 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); | |
6635 | break; | |
5f4273c7 | 6636 | |
5287ad62 JB |
6637 | case VFP_REG_Dm: |
6638 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); | |
6639 | break; | |
6640 | ||
c19d1205 ZW |
6641 | default: |
6642 | abort (); | |
09d92015 | 6643 | } |
09d92015 MM |
6644 | } |
6645 | ||
c19d1205 | 6646 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 6647 | if any, is handled by md_apply_fix. */ |
09d92015 | 6648 | static void |
c19d1205 | 6649 | encode_arm_shift (int i) |
09d92015 | 6650 | { |
c19d1205 ZW |
6651 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
6652 | inst.instruction |= SHIFT_ROR << 5; | |
6653 | else | |
09d92015 | 6654 | { |
c19d1205 ZW |
6655 | inst.instruction |= inst.operands[i].shift_kind << 5; |
6656 | if (inst.operands[i].immisreg) | |
6657 | { | |
6658 | inst.instruction |= SHIFT_BY_REG; | |
6659 | inst.instruction |= inst.operands[i].imm << 8; | |
6660 | } | |
6661 | else | |
6662 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 6663 | } |
c19d1205 | 6664 | } |
09d92015 | 6665 | |
c19d1205 ZW |
6666 | static void |
6667 | encode_arm_shifter_operand (int i) | |
6668 | { | |
6669 | if (inst.operands[i].isreg) | |
09d92015 | 6670 | { |
c19d1205 ZW |
6671 | inst.instruction |= inst.operands[i].reg; |
6672 | encode_arm_shift (i); | |
09d92015 | 6673 | } |
c19d1205 ZW |
6674 | else |
6675 | inst.instruction |= INST_IMMEDIATE; | |
09d92015 MM |
6676 | } |
6677 | ||
c19d1205 | 6678 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 6679 | static void |
c19d1205 | 6680 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 6681 | { |
9c2799c2 | 6682 | gas_assert (inst.operands[i].isreg); |
c19d1205 | 6683 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 6684 | |
c19d1205 | 6685 | if (inst.operands[i].preind) |
09d92015 | 6686 | { |
c19d1205 ZW |
6687 | if (is_t) |
6688 | { | |
6689 | inst.error = _("instruction does not accept preindexed addressing"); | |
6690 | return; | |
6691 | } | |
6692 | inst.instruction |= PRE_INDEX; | |
6693 | if (inst.operands[i].writeback) | |
6694 | inst.instruction |= WRITE_BACK; | |
09d92015 | 6695 | |
c19d1205 ZW |
6696 | } |
6697 | else if (inst.operands[i].postind) | |
6698 | { | |
9c2799c2 | 6699 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
6700 | if (is_t) |
6701 | inst.instruction |= WRITE_BACK; | |
6702 | } | |
6703 | else /* unindexed - only for coprocessor */ | |
09d92015 | 6704 | { |
c19d1205 | 6705 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
6706 | return; |
6707 | } | |
6708 | ||
c19d1205 ZW |
6709 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
6710 | && (((inst.instruction & 0x000f0000) >> 16) | |
6711 | == ((inst.instruction & 0x0000f000) >> 12))) | |
6712 | as_warn ((inst.instruction & LOAD_BIT) | |
6713 | ? _("destination register same as write-back base") | |
6714 | : _("source register same as write-back base")); | |
09d92015 MM |
6715 | } |
6716 | ||
c19d1205 ZW |
6717 | /* inst.operands[i] was set up by parse_address. Encode it into an |
6718 | ARM-format mode 2 load or store instruction. If is_t is true, | |
6719 | reject forms that cannot be used with a T instruction (i.e. not | |
6720 | post-indexed). */ | |
a737bd4d | 6721 | static void |
c19d1205 | 6722 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 6723 | { |
5be8be5d DG |
6724 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
6725 | ||
c19d1205 | 6726 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 6727 | |
c19d1205 | 6728 | if (inst.operands[i].immisreg) |
09d92015 | 6729 | { |
5be8be5d DG |
6730 | constraint ((inst.operands[i].imm == REG_PC |
6731 | || (is_pc && inst.operands[i].writeback)), | |
6732 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
6733 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
6734 | inst.instruction |= inst.operands[i].imm; | |
6735 | if (!inst.operands[i].negative) | |
6736 | inst.instruction |= INDEX_UP; | |
6737 | if (inst.operands[i].shifted) | |
6738 | { | |
6739 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
6740 | inst.instruction |= SHIFT_ROR << 5; | |
6741 | else | |
6742 | { | |
6743 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
6744 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
6745 | } | |
6746 | } | |
09d92015 | 6747 | } |
c19d1205 | 6748 | else /* immediate offset in inst.reloc */ |
09d92015 | 6749 | { |
5be8be5d DG |
6750 | if (is_pc && !inst.reloc.pc_rel) |
6751 | { | |
6752 | const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0); | |
6753 | /* BAD_PC_ADDRESSING Condition = | |
6754 | is_load => is_t | |
6755 | which becomes !is_load || is_t. */ | |
6756 | constraint ((!is_load || is_t), | |
6757 | BAD_PC_ADDRESSING); | |
6758 | } | |
6759 | ||
c19d1205 ZW |
6760 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
6761 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
09d92015 | 6762 | } |
09d92015 MM |
6763 | } |
6764 | ||
c19d1205 ZW |
6765 | /* inst.operands[i] was set up by parse_address. Encode it into an |
6766 | ARM-format mode 3 load or store instruction. Reject forms that | |
6767 | cannot be used with such instructions. If is_t is true, reject | |
6768 | forms that cannot be used with a T instruction (i.e. not | |
6769 | post-indexed). */ | |
6770 | static void | |
6771 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 6772 | { |
c19d1205 | 6773 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 6774 | { |
c19d1205 ZW |
6775 | inst.error = _("instruction does not accept scaled register index"); |
6776 | return; | |
09d92015 | 6777 | } |
a737bd4d | 6778 | |
c19d1205 | 6779 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 6780 | |
c19d1205 ZW |
6781 | if (inst.operands[i].immisreg) |
6782 | { | |
5be8be5d DG |
6783 | constraint ((inst.operands[i].imm == REG_PC |
6784 | || inst.operands[i].reg == REG_PC), | |
6785 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
6786 | inst.instruction |= inst.operands[i].imm; |
6787 | if (!inst.operands[i].negative) | |
6788 | inst.instruction |= INDEX_UP; | |
6789 | } | |
6790 | else /* immediate offset in inst.reloc */ | |
6791 | { | |
5be8be5d DG |
6792 | constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel |
6793 | && inst.operands[i].writeback), | |
6794 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
6795 | inst.instruction |= HWOFFSET_IMM; |
6796 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
6797 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
c19d1205 | 6798 | } |
a737bd4d NC |
6799 | } |
6800 | ||
c19d1205 ZW |
6801 | /* inst.operands[i] was set up by parse_address. Encode it into an |
6802 | ARM-format instruction. Reject all forms which cannot be encoded | |
6803 | into a coprocessor load/store instruction. If wb_ok is false, | |
6804 | reject use of writeback; if unind_ok is false, reject use of | |
6805 | unindexed addressing. If reloc_override is not 0, use it instead | |
4962c51a MS |
6806 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one |
6807 | (in which case it is preserved). */ | |
09d92015 | 6808 | |
c19d1205 ZW |
6809 | static int |
6810 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
09d92015 | 6811 | { |
c19d1205 | 6812 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 6813 | |
9c2799c2 | 6814 | gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); |
09d92015 | 6815 | |
c19d1205 | 6816 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ |
09d92015 | 6817 | { |
9c2799c2 | 6818 | gas_assert (!inst.operands[i].writeback); |
c19d1205 ZW |
6819 | if (!unind_ok) |
6820 | { | |
6821 | inst.error = _("instruction does not support unindexed addressing"); | |
6822 | return FAIL; | |
6823 | } | |
6824 | inst.instruction |= inst.operands[i].imm; | |
6825 | inst.instruction |= INDEX_UP; | |
6826 | return SUCCESS; | |
09d92015 | 6827 | } |
a737bd4d | 6828 | |
c19d1205 ZW |
6829 | if (inst.operands[i].preind) |
6830 | inst.instruction |= PRE_INDEX; | |
a737bd4d | 6831 | |
c19d1205 | 6832 | if (inst.operands[i].writeback) |
09d92015 | 6833 | { |
c19d1205 ZW |
6834 | if (inst.operands[i].reg == REG_PC) |
6835 | { | |
6836 | inst.error = _("pc may not be used with write-back"); | |
6837 | return FAIL; | |
6838 | } | |
6839 | if (!wb_ok) | |
6840 | { | |
6841 | inst.error = _("instruction does not support writeback"); | |
6842 | return FAIL; | |
6843 | } | |
6844 | inst.instruction |= WRITE_BACK; | |
09d92015 | 6845 | } |
a737bd4d | 6846 | |
c19d1205 | 6847 | if (reloc_override) |
21d799b5 | 6848 | inst.reloc.type = (bfd_reloc_code_real_type) reloc_override; |
4962c51a MS |
6849 | else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC |
6850 | || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) | |
6851 | && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) | |
6852 | { | |
6853 | if (thumb_mode) | |
6854 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
6855 | else | |
6856 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
6857 | } | |
6858 | ||
c19d1205 ZW |
6859 | return SUCCESS; |
6860 | } | |
a737bd4d | 6861 | |
c19d1205 ZW |
6862 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
6863 | Determine whether it can be performed with a move instruction; if | |
6864 | it can, convert inst.instruction to that move instruction and | |
c921be7d NC |
6865 | return TRUE; if it can't, convert inst.instruction to a literal-pool |
6866 | load and return FALSE. If this is not a valid thing to do in the | |
6867 | current context, set inst.error and return TRUE. | |
a737bd4d | 6868 | |
c19d1205 ZW |
6869 | inst.operands[i] describes the destination register. */ |
6870 | ||
c921be7d | 6871 | static bfd_boolean |
c19d1205 ZW |
6872 | move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) |
6873 | { | |
53365c0d PB |
6874 | unsigned long tbit; |
6875 | ||
6876 | if (thumb_p) | |
6877 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
6878 | else | |
6879 | tbit = LOAD_BIT; | |
6880 | ||
6881 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 6882 | { |
c19d1205 | 6883 | inst.error = _("invalid pseudo operation"); |
c921be7d | 6884 | return TRUE; |
09d92015 | 6885 | } |
c19d1205 | 6886 | if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) |
09d92015 MM |
6887 | { |
6888 | inst.error = _("constant expression expected"); | |
c921be7d | 6889 | return TRUE; |
09d92015 | 6890 | } |
c19d1205 | 6891 | if (inst.reloc.exp.X_op == O_constant) |
09d92015 | 6892 | { |
c19d1205 ZW |
6893 | if (thumb_p) |
6894 | { | |
53365c0d | 6895 | if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) |
c19d1205 ZW |
6896 | { |
6897 | /* This can be done with a mov(1) instruction. */ | |
6898 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
6899 | inst.instruction |= inst.reloc.exp.X_add_number; | |
c921be7d | 6900 | return TRUE; |
c19d1205 ZW |
6901 | } |
6902 | } | |
6903 | else | |
6904 | { | |
6905 | int value = encode_arm_immediate (inst.reloc.exp.X_add_number); | |
6906 | if (value != FAIL) | |
6907 | { | |
6908 | /* This can be done with a mov instruction. */ | |
6909 | inst.instruction &= LITERAL_MASK; | |
6910 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
6911 | inst.instruction |= value & 0xfff; | |
c921be7d | 6912 | return TRUE; |
c19d1205 | 6913 | } |
09d92015 | 6914 | |
c19d1205 ZW |
6915 | value = encode_arm_immediate (~inst.reloc.exp.X_add_number); |
6916 | if (value != FAIL) | |
6917 | { | |
6918 | /* This can be done with a mvn instruction. */ | |
6919 | inst.instruction &= LITERAL_MASK; | |
6920 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
6921 | inst.instruction |= value & 0xfff; | |
c921be7d | 6922 | return TRUE; |
c19d1205 ZW |
6923 | } |
6924 | } | |
09d92015 MM |
6925 | } |
6926 | ||
c19d1205 ZW |
6927 | if (add_to_lit_pool () == FAIL) |
6928 | { | |
6929 | inst.error = _("literal pool insertion failed"); | |
c921be7d | 6930 | return TRUE; |
c19d1205 ZW |
6931 | } |
6932 | inst.operands[1].reg = REG_PC; | |
6933 | inst.operands[1].isreg = 1; | |
6934 | inst.operands[1].preind = 1; | |
6935 | inst.reloc.pc_rel = 1; | |
6936 | inst.reloc.type = (thumb_p | |
6937 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
6938 | : (mode_3 | |
6939 | ? BFD_RELOC_ARM_HWLITERAL | |
6940 | : BFD_RELOC_ARM_LITERAL)); | |
c921be7d | 6941 | return FALSE; |
09d92015 MM |
6942 | } |
6943 | ||
5f4273c7 | 6944 | /* Functions for instruction encoding, sorted by sub-architecture. |
c19d1205 ZW |
6945 | First some generics; their names are taken from the conventional |
6946 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 6947 | |
a737bd4d | 6948 | static void |
c19d1205 | 6949 | do_noargs (void) |
09d92015 | 6950 | { |
c19d1205 | 6951 | } |
a737bd4d | 6952 | |
c19d1205 ZW |
6953 | static void |
6954 | do_rd (void) | |
6955 | { | |
6956 | inst.instruction |= inst.operands[0].reg << 12; | |
6957 | } | |
a737bd4d | 6958 | |
c19d1205 ZW |
6959 | static void |
6960 | do_rd_rm (void) | |
6961 | { | |
6962 | inst.instruction |= inst.operands[0].reg << 12; | |
6963 | inst.instruction |= inst.operands[1].reg; | |
6964 | } | |
09d92015 | 6965 | |
c19d1205 ZW |
6966 | static void |
6967 | do_rd_rn (void) | |
6968 | { | |
6969 | inst.instruction |= inst.operands[0].reg << 12; | |
6970 | inst.instruction |= inst.operands[1].reg << 16; | |
6971 | } | |
a737bd4d | 6972 | |
c19d1205 ZW |
6973 | static void |
6974 | do_rn_rd (void) | |
6975 | { | |
6976 | inst.instruction |= inst.operands[0].reg << 16; | |
6977 | inst.instruction |= inst.operands[1].reg << 12; | |
6978 | } | |
09d92015 | 6979 | |
c19d1205 ZW |
6980 | static void |
6981 | do_rd_rm_rn (void) | |
6982 | { | |
9a64e435 | 6983 | unsigned Rn = inst.operands[2].reg; |
708587a4 | 6984 | /* Enforce restrictions on SWP instruction. */ |
9a64e435 | 6985 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
56adecf4 DG |
6986 | { |
6987 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
6988 | _("Rn must not overlap other operands")); | |
6989 | ||
6990 | /* SWP{b} is deprecated for ARMv6* and ARMv7. */ | |
6991 | if (warn_on_deprecated | |
6992 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
6993 | as_warn (_("swp{b} use is deprecated for this architecture")); | |
6994 | ||
6995 | } | |
c19d1205 ZW |
6996 | inst.instruction |= inst.operands[0].reg << 12; |
6997 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 6998 | inst.instruction |= Rn << 16; |
c19d1205 | 6999 | } |
09d92015 | 7000 | |
c19d1205 ZW |
7001 | static void |
7002 | do_rd_rn_rm (void) | |
7003 | { | |
7004 | inst.instruction |= inst.operands[0].reg << 12; | |
7005 | inst.instruction |= inst.operands[1].reg << 16; | |
7006 | inst.instruction |= inst.operands[2].reg; | |
7007 | } | |
a737bd4d | 7008 | |
c19d1205 ZW |
7009 | static void |
7010 | do_rm_rd_rn (void) | |
7011 | { | |
5be8be5d DG |
7012 | constraint ((inst.operands[2].reg == REG_PC), BAD_PC); |
7013 | constraint (((inst.reloc.exp.X_op != O_constant | |
7014 | && inst.reloc.exp.X_op != O_illegal) | |
7015 | || inst.reloc.exp.X_add_number != 0), | |
7016 | BAD_ADDR_MODE); | |
c19d1205 ZW |
7017 | inst.instruction |= inst.operands[0].reg; |
7018 | inst.instruction |= inst.operands[1].reg << 12; | |
7019 | inst.instruction |= inst.operands[2].reg << 16; | |
7020 | } | |
09d92015 | 7021 | |
c19d1205 ZW |
7022 | static void |
7023 | do_imm0 (void) | |
7024 | { | |
7025 | inst.instruction |= inst.operands[0].imm; | |
7026 | } | |
09d92015 | 7027 | |
c19d1205 ZW |
7028 | static void |
7029 | do_rd_cpaddr (void) | |
7030 | { | |
7031 | inst.instruction |= inst.operands[0].reg << 12; | |
7032 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 7033 | } |
a737bd4d | 7034 | |
c19d1205 ZW |
7035 | /* ARM instructions, in alphabetical order by function name (except |
7036 | that wrapper functions appear immediately after the function they | |
7037 | wrap). */ | |
09d92015 | 7038 | |
c19d1205 ZW |
7039 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
7040 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
7041 | |
7042 | static void | |
c19d1205 | 7043 | do_adr (void) |
09d92015 | 7044 | { |
c19d1205 | 7045 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 7046 | |
c19d1205 ZW |
7047 | /* Frag hacking will turn this into a sub instruction if the offset turns |
7048 | out to be negative. */ | |
7049 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 7050 | inst.reloc.pc_rel = 1; |
2fc8bdac | 7051 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 7052 | } |
b99bd4ef | 7053 | |
c19d1205 ZW |
7054 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
7055 | into a relative address of the form: | |
7056 | add rd, pc, #low(label-.-8)" | |
7057 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 7058 | |
c19d1205 ZW |
7059 | static void |
7060 | do_adrl (void) | |
7061 | { | |
7062 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 7063 | |
c19d1205 ZW |
7064 | /* Frag hacking will turn this into a sub instruction if the offset turns |
7065 | out to be negative. */ | |
7066 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
7067 | inst.reloc.pc_rel = 1; |
7068 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 7069 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
7070 | } |
7071 | ||
b99bd4ef | 7072 | static void |
c19d1205 | 7073 | do_arit (void) |
b99bd4ef | 7074 | { |
c19d1205 ZW |
7075 | if (!inst.operands[1].present) |
7076 | inst.operands[1].reg = inst.operands[0].reg; | |
7077 | inst.instruction |= inst.operands[0].reg << 12; | |
7078 | inst.instruction |= inst.operands[1].reg << 16; | |
7079 | encode_arm_shifter_operand (2); | |
7080 | } | |
b99bd4ef | 7081 | |
62b3e311 PB |
7082 | static void |
7083 | do_barrier (void) | |
7084 | { | |
7085 | if (inst.operands[0].present) | |
7086 | { | |
7087 | constraint ((inst.instruction & 0xf0) != 0x40 | |
7088 | && inst.operands[0].imm != 0xf, | |
bd3ba5d1 | 7089 | _("bad barrier type")); |
62b3e311 PB |
7090 | inst.instruction |= inst.operands[0].imm; |
7091 | } | |
7092 | else | |
7093 | inst.instruction |= 0xf; | |
7094 | } | |
7095 | ||
c19d1205 ZW |
7096 | static void |
7097 | do_bfc (void) | |
7098 | { | |
7099 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
7100 | constraint (msb > 32, _("bit-field extends past end of register")); | |
7101 | /* The instruction encoding stores the LSB and MSB, | |
7102 | not the LSB and width. */ | |
7103 | inst.instruction |= inst.operands[0].reg << 12; | |
7104 | inst.instruction |= inst.operands[1].imm << 7; | |
7105 | inst.instruction |= (msb - 1) << 16; | |
7106 | } | |
b99bd4ef | 7107 | |
c19d1205 ZW |
7108 | static void |
7109 | do_bfi (void) | |
7110 | { | |
7111 | unsigned int msb; | |
b99bd4ef | 7112 | |
c19d1205 ZW |
7113 | /* #0 in second position is alternative syntax for bfc, which is |
7114 | the same instruction but with REG_PC in the Rm field. */ | |
7115 | if (!inst.operands[1].isreg) | |
7116 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 7117 | |
c19d1205 ZW |
7118 | msb = inst.operands[2].imm + inst.operands[3].imm; |
7119 | constraint (msb > 32, _("bit-field extends past end of register")); | |
7120 | /* The instruction encoding stores the LSB and MSB, | |
7121 | not the LSB and width. */ | |
7122 | inst.instruction |= inst.operands[0].reg << 12; | |
7123 | inst.instruction |= inst.operands[1].reg; | |
7124 | inst.instruction |= inst.operands[2].imm << 7; | |
7125 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
7126 | } |
7127 | ||
b99bd4ef | 7128 | static void |
c19d1205 | 7129 | do_bfx (void) |
b99bd4ef | 7130 | { |
c19d1205 ZW |
7131 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
7132 | _("bit-field extends past end of register")); | |
7133 | inst.instruction |= inst.operands[0].reg << 12; | |
7134 | inst.instruction |= inst.operands[1].reg; | |
7135 | inst.instruction |= inst.operands[2].imm << 7; | |
7136 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
7137 | } | |
09d92015 | 7138 | |
c19d1205 ZW |
7139 | /* ARM V5 breakpoint instruction (argument parse) |
7140 | BKPT <16 bit unsigned immediate> | |
7141 | Instruction is not conditional. | |
7142 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
7143 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 7144 | |
c19d1205 ZW |
7145 | static void |
7146 | do_bkpt (void) | |
7147 | { | |
7148 | /* Top 12 of 16 bits to bits 19:8. */ | |
7149 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 7150 | |
c19d1205 ZW |
7151 | /* Bottom 4 of 16 bits to bits 3:0. */ |
7152 | inst.instruction |= inst.operands[0].imm & 0xf; | |
7153 | } | |
09d92015 | 7154 | |
c19d1205 ZW |
7155 | static void |
7156 | encode_branch (int default_reloc) | |
7157 | { | |
7158 | if (inst.operands[0].hasreloc) | |
7159 | { | |
7160 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, | |
7161 | _("the only suffix valid here is '(plt)'")); | |
267bf995 | 7162 | inst.reloc.type = BFD_RELOC_ARM_PLT32; |
c19d1205 | 7163 | } |
b99bd4ef | 7164 | else |
c19d1205 | 7165 | { |
21d799b5 | 7166 | inst.reloc.type = (bfd_reloc_code_real_type) default_reloc; |
c19d1205 | 7167 | } |
2fc8bdac | 7168 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
7169 | } |
7170 | ||
b99bd4ef | 7171 | static void |
c19d1205 | 7172 | do_branch (void) |
b99bd4ef | 7173 | { |
39b41c9c PB |
7174 | #ifdef OBJ_ELF |
7175 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
7176 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
7177 | else | |
7178 | #endif | |
7179 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
7180 | } | |
7181 | ||
7182 | static void | |
7183 | do_bl (void) | |
7184 | { | |
7185 | #ifdef OBJ_ELF | |
7186 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
7187 | { | |
7188 | if (inst.cond == COND_ALWAYS) | |
7189 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
7190 | else | |
7191 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
7192 | } | |
7193 | else | |
7194 | #endif | |
7195 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 7196 | } |
b99bd4ef | 7197 | |
c19d1205 ZW |
7198 | /* ARM V5 branch-link-exchange instruction (argument parse) |
7199 | BLX <target_addr> ie BLX(1) | |
7200 | BLX{<condition>} <Rm> ie BLX(2) | |
7201 | Unfortunately, there are two different opcodes for this mnemonic. | |
7202 | So, the insns[].value is not used, and the code here zaps values | |
7203 | into inst.instruction. | |
7204 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 7205 | |
c19d1205 ZW |
7206 | static void |
7207 | do_blx (void) | |
7208 | { | |
7209 | if (inst.operands[0].isreg) | |
b99bd4ef | 7210 | { |
c19d1205 ZW |
7211 | /* Arg is a register; the opcode provided by insns[] is correct. |
7212 | It is not illegal to do "blx pc", just useless. */ | |
7213 | if (inst.operands[0].reg == REG_PC) | |
7214 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 7215 | |
c19d1205 ZW |
7216 | inst.instruction |= inst.operands[0].reg; |
7217 | } | |
7218 | else | |
b99bd4ef | 7219 | { |
c19d1205 | 7220 | /* Arg is an address; this instruction cannot be executed |
267bf995 RR |
7221 | conditionally, and the opcode must be adjusted. |
7222 | We retain the BFD_RELOC_ARM_PCREL_BLX till the very end | |
7223 | where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ | |
c19d1205 | 7224 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
2fc8bdac | 7225 | inst.instruction = 0xfa000000; |
267bf995 | 7226 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 7227 | } |
c19d1205 ZW |
7228 | } |
7229 | ||
7230 | static void | |
7231 | do_bx (void) | |
7232 | { | |
845b51d6 PB |
7233 | bfd_boolean want_reloc; |
7234 | ||
c19d1205 ZW |
7235 | if (inst.operands[0].reg == REG_PC) |
7236 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 7237 | |
c19d1205 | 7238 | inst.instruction |= inst.operands[0].reg; |
845b51d6 PB |
7239 | /* Output R_ARM_V4BX relocations if is an EABI object that looks like |
7240 | it is for ARMv4t or earlier. */ | |
7241 | want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); | |
7242 | if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5)) | |
7243 | want_reloc = TRUE; | |
7244 | ||
5ad34203 | 7245 | #ifdef OBJ_ELF |
845b51d6 | 7246 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
5ad34203 | 7247 | #endif |
584206db | 7248 | want_reloc = FALSE; |
845b51d6 PB |
7249 | |
7250 | if (want_reloc) | |
7251 | inst.reloc.type = BFD_RELOC_ARM_V4BX; | |
09d92015 MM |
7252 | } |
7253 | ||
c19d1205 ZW |
7254 | |
7255 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
7256 | |
7257 | static void | |
c19d1205 | 7258 | do_bxj (void) |
a737bd4d | 7259 | { |
c19d1205 ZW |
7260 | if (inst.operands[0].reg == REG_PC) |
7261 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
7262 | ||
7263 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
7264 | } |
7265 | ||
c19d1205 ZW |
7266 | /* Co-processor data operation: |
7267 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
7268 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
7269 | static void | |
7270 | do_cdp (void) | |
7271 | { | |
7272 | inst.instruction |= inst.operands[0].reg << 8; | |
7273 | inst.instruction |= inst.operands[1].imm << 20; | |
7274 | inst.instruction |= inst.operands[2].reg << 12; | |
7275 | inst.instruction |= inst.operands[3].reg << 16; | |
7276 | inst.instruction |= inst.operands[4].reg; | |
7277 | inst.instruction |= inst.operands[5].imm << 5; | |
7278 | } | |
a737bd4d NC |
7279 | |
7280 | static void | |
c19d1205 | 7281 | do_cmp (void) |
a737bd4d | 7282 | { |
c19d1205 ZW |
7283 | inst.instruction |= inst.operands[0].reg << 16; |
7284 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
7285 | } |
7286 | ||
c19d1205 ZW |
7287 | /* Transfer between coprocessor and ARM registers. |
7288 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
7289 | MRC2 | |
7290 | MCR{cond} | |
7291 | MCR2 | |
7292 | ||
7293 | No special properties. */ | |
09d92015 MM |
7294 | |
7295 | static void | |
c19d1205 | 7296 | do_co_reg (void) |
09d92015 | 7297 | { |
fdfde340 JM |
7298 | unsigned Rd; |
7299 | ||
7300 | Rd = inst.operands[2].reg; | |
7301 | if (thumb_mode) | |
7302 | { | |
7303 | if (inst.instruction == 0xee000010 | |
7304 | || inst.instruction == 0xfe000010) | |
7305 | /* MCR, MCR2 */ | |
7306 | reject_bad_reg (Rd); | |
7307 | else | |
7308 | /* MRC, MRC2 */ | |
7309 | constraint (Rd == REG_SP, BAD_SP); | |
7310 | } | |
7311 | else | |
7312 | { | |
7313 | /* MCR */ | |
7314 | if (inst.instruction == 0xe000010) | |
7315 | constraint (Rd == REG_PC, BAD_PC); | |
7316 | } | |
7317 | ||
7318 | ||
c19d1205 ZW |
7319 | inst.instruction |= inst.operands[0].reg << 8; |
7320 | inst.instruction |= inst.operands[1].imm << 21; | |
fdfde340 | 7321 | inst.instruction |= Rd << 12; |
c19d1205 ZW |
7322 | inst.instruction |= inst.operands[3].reg << 16; |
7323 | inst.instruction |= inst.operands[4].reg; | |
7324 | inst.instruction |= inst.operands[5].imm << 5; | |
7325 | } | |
09d92015 | 7326 | |
c19d1205 ZW |
7327 | /* Transfer between coprocessor register and pair of ARM registers. |
7328 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
7329 | MCRR2 | |
7330 | MRRC{cond} | |
7331 | MRRC2 | |
b99bd4ef | 7332 | |
c19d1205 | 7333 | Two XScale instructions are special cases of these: |
09d92015 | 7334 | |
c19d1205 ZW |
7335 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
7336 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 7337 | |
5f4273c7 | 7338 | Result unpredictable if Rd or Rn is R15. */ |
a737bd4d | 7339 | |
c19d1205 ZW |
7340 | static void |
7341 | do_co_reg2c (void) | |
7342 | { | |
fdfde340 JM |
7343 | unsigned Rd, Rn; |
7344 | ||
7345 | Rd = inst.operands[2].reg; | |
7346 | Rn = inst.operands[3].reg; | |
7347 | ||
7348 | if (thumb_mode) | |
7349 | { | |
7350 | reject_bad_reg (Rd); | |
7351 | reject_bad_reg (Rn); | |
7352 | } | |
7353 | else | |
7354 | { | |
7355 | constraint (Rd == REG_PC, BAD_PC); | |
7356 | constraint (Rn == REG_PC, BAD_PC); | |
7357 | } | |
7358 | ||
c19d1205 ZW |
7359 | inst.instruction |= inst.operands[0].reg << 8; |
7360 | inst.instruction |= inst.operands[1].imm << 4; | |
fdfde340 JM |
7361 | inst.instruction |= Rd << 12; |
7362 | inst.instruction |= Rn << 16; | |
c19d1205 | 7363 | inst.instruction |= inst.operands[4].reg; |
b99bd4ef NC |
7364 | } |
7365 | ||
c19d1205 ZW |
7366 | static void |
7367 | do_cpsi (void) | |
7368 | { | |
7369 | inst.instruction |= inst.operands[0].imm << 6; | |
a028a6f5 PB |
7370 | if (inst.operands[1].present) |
7371 | { | |
7372 | inst.instruction |= CPSI_MMOD; | |
7373 | inst.instruction |= inst.operands[1].imm; | |
7374 | } | |
c19d1205 | 7375 | } |
b99bd4ef | 7376 | |
62b3e311 PB |
7377 | static void |
7378 | do_dbg (void) | |
7379 | { | |
7380 | inst.instruction |= inst.operands[0].imm; | |
7381 | } | |
7382 | ||
b99bd4ef | 7383 | static void |
c19d1205 | 7384 | do_it (void) |
b99bd4ef | 7385 | { |
c19d1205 | 7386 | /* There is no IT instruction in ARM mode. We |
e07e6e58 NC |
7387 | process it to do the validation as if in |
7388 | thumb mode, just in case the code gets | |
7389 | assembled for thumb using the unified syntax. */ | |
7390 | ||
c19d1205 | 7391 | inst.size = 0; |
e07e6e58 NC |
7392 | if (unified_syntax) |
7393 | { | |
7394 | set_it_insn_type (IT_INSN); | |
7395 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
7396 | now_it.cc = inst.operands[0].imm; | |
7397 | } | |
09d92015 | 7398 | } |
b99bd4ef | 7399 | |
09d92015 | 7400 | static void |
c19d1205 | 7401 | do_ldmstm (void) |
ea6ef066 | 7402 | { |
c19d1205 ZW |
7403 | int base_reg = inst.operands[0].reg; |
7404 | int range = inst.operands[1].imm; | |
ea6ef066 | 7405 | |
c19d1205 ZW |
7406 | inst.instruction |= base_reg << 16; |
7407 | inst.instruction |= range; | |
ea6ef066 | 7408 | |
c19d1205 ZW |
7409 | if (inst.operands[1].writeback) |
7410 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 7411 | |
c19d1205 | 7412 | if (inst.operands[0].writeback) |
ea6ef066 | 7413 | { |
c19d1205 ZW |
7414 | inst.instruction |= WRITE_BACK; |
7415 | /* Check for unpredictable uses of writeback. */ | |
7416 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 7417 | { |
c19d1205 ZW |
7418 | /* Not allowed in LDM type 2. */ |
7419 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
7420 | && ((range & (1 << REG_PC)) == 0)) | |
7421 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7422 | /* Only allowed if base reg not in list for other types. */ | |
7423 | else if (range & (1 << base_reg)) | |
7424 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
7425 | } | |
7426 | else /* STM. */ | |
7427 | { | |
7428 | /* Not allowed for type 2. */ | |
7429 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
7430 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7431 | /* Only allowed if base reg not in list, or first in list. */ | |
7432 | else if ((range & (1 << base_reg)) | |
7433 | && (range & ((1 << base_reg) - 1))) | |
7434 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 7435 | } |
ea6ef066 | 7436 | } |
a737bd4d NC |
7437 | } |
7438 | ||
c19d1205 ZW |
7439 | /* ARMv5TE load-consecutive (argument parse) |
7440 | Mode is like LDRH. | |
7441 | ||
7442 | LDRccD R, mode | |
7443 | STRccD R, mode. */ | |
7444 | ||
a737bd4d | 7445 | static void |
c19d1205 | 7446 | do_ldrd (void) |
a737bd4d | 7447 | { |
c19d1205 ZW |
7448 | constraint (inst.operands[0].reg % 2 != 0, |
7449 | _("first destination register must be even")); | |
7450 | constraint (inst.operands[1].present | |
7451 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
7452 | _("can only load two consecutive registers")); | |
7453 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
7454 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 7455 | |
c19d1205 ZW |
7456 | if (!inst.operands[1].present) |
7457 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
5f4273c7 | 7458 | |
c19d1205 | 7459 | if (inst.instruction & LOAD_BIT) |
a737bd4d | 7460 | { |
c19d1205 ZW |
7461 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
7462 | register and the first register written; we have to diagnose | |
7463 | overlap between the base and the second register written here. */ | |
ea6ef066 | 7464 | |
c19d1205 ZW |
7465 | if (inst.operands[2].reg == inst.operands[1].reg |
7466 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
7467 | as_warn (_("base register written back, and overlaps " | |
7468 | "second destination register")); | |
b05fe5cf | 7469 | |
c19d1205 ZW |
7470 | /* For an index-register load, the index register must not overlap the |
7471 | destination (even if not write-back). */ | |
7472 | else if (inst.operands[2].immisreg | |
ca3f61f7 NC |
7473 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg |
7474 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
c19d1205 | 7475 | as_warn (_("index register overlaps destination register")); |
b05fe5cf | 7476 | } |
c19d1205 ZW |
7477 | |
7478 | inst.instruction |= inst.operands[0].reg << 12; | |
7479 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
7480 | } |
7481 | ||
7482 | static void | |
c19d1205 | 7483 | do_ldrex (void) |
b05fe5cf | 7484 | { |
c19d1205 ZW |
7485 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
7486 | || inst.operands[1].postind || inst.operands[1].writeback | |
7487 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
7488 | || inst.operands[1].negative |
7489 | /* This can arise if the programmer has written | |
7490 | strex rN, rM, foo | |
7491 | or if they have mistakenly used a register name as the last | |
7492 | operand, eg: | |
7493 | strex rN, rM, rX | |
7494 | It is very difficult to distinguish between these two cases | |
7495 | because "rX" might actually be a label. ie the register | |
7496 | name has been occluded by a symbol of the same name. So we | |
7497 | just generate a general 'bad addressing mode' type error | |
7498 | message and leave it up to the programmer to discover the | |
7499 | true cause and fix their mistake. */ | |
7500 | || (inst.operands[1].reg == REG_PC), | |
7501 | BAD_ADDR_MODE); | |
b05fe5cf | 7502 | |
c19d1205 ZW |
7503 | constraint (inst.reloc.exp.X_op != O_constant |
7504 | || inst.reloc.exp.X_add_number != 0, | |
7505 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 7506 | |
5be8be5d DG |
7507 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
7508 | ||
c19d1205 ZW |
7509 | inst.instruction |= inst.operands[0].reg << 12; |
7510 | inst.instruction |= inst.operands[1].reg << 16; | |
7511 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
7512 | } |
7513 | ||
7514 | static void | |
c19d1205 | 7515 | do_ldrexd (void) |
b05fe5cf | 7516 | { |
c19d1205 ZW |
7517 | constraint (inst.operands[0].reg % 2 != 0, |
7518 | _("even register required")); | |
7519 | constraint (inst.operands[1].present | |
7520 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
7521 | _("can only load two consecutive registers")); | |
7522 | /* If op 1 were present and equal to PC, this function wouldn't | |
7523 | have been called in the first place. */ | |
7524 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 7525 | |
c19d1205 ZW |
7526 | inst.instruction |= inst.operands[0].reg << 12; |
7527 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
7528 | } |
7529 | ||
7530 | static void | |
c19d1205 | 7531 | do_ldst (void) |
b05fe5cf | 7532 | { |
c19d1205 ZW |
7533 | inst.instruction |= inst.operands[0].reg << 12; |
7534 | if (!inst.operands[1].isreg) | |
7535 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) | |
b05fe5cf | 7536 | return; |
c19d1205 | 7537 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
7538 | } |
7539 | ||
7540 | static void | |
c19d1205 | 7541 | do_ldstt (void) |
b05fe5cf | 7542 | { |
c19d1205 ZW |
7543 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
7544 | reject [Rn,...]. */ | |
7545 | if (inst.operands[1].preind) | |
b05fe5cf | 7546 | { |
bd3ba5d1 NC |
7547 | constraint (inst.reloc.exp.X_op != O_constant |
7548 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 7549 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 7550 | |
c19d1205 ZW |
7551 | inst.operands[1].preind = 0; |
7552 | inst.operands[1].postind = 1; | |
7553 | inst.operands[1].writeback = 1; | |
b05fe5cf | 7554 | } |
c19d1205 ZW |
7555 | inst.instruction |= inst.operands[0].reg << 12; |
7556 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
7557 | } | |
b05fe5cf | 7558 | |
c19d1205 | 7559 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 7560 | |
c19d1205 ZW |
7561 | static void |
7562 | do_ldstv4 (void) | |
7563 | { | |
ff4a8d2b | 7564 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
7565 | inst.instruction |= inst.operands[0].reg << 12; |
7566 | if (!inst.operands[1].isreg) | |
7567 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) | |
b05fe5cf | 7568 | return; |
c19d1205 | 7569 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
7570 | } |
7571 | ||
7572 | static void | |
c19d1205 | 7573 | do_ldsttv4 (void) |
b05fe5cf | 7574 | { |
c19d1205 ZW |
7575 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
7576 | reject [Rn,...]. */ | |
7577 | if (inst.operands[1].preind) | |
b05fe5cf | 7578 | { |
bd3ba5d1 NC |
7579 | constraint (inst.reloc.exp.X_op != O_constant |
7580 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 7581 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 7582 | |
c19d1205 ZW |
7583 | inst.operands[1].preind = 0; |
7584 | inst.operands[1].postind = 1; | |
7585 | inst.operands[1].writeback = 1; | |
b05fe5cf | 7586 | } |
c19d1205 ZW |
7587 | inst.instruction |= inst.operands[0].reg << 12; |
7588 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
7589 | } | |
b05fe5cf | 7590 | |
c19d1205 ZW |
7591 | /* Co-processor register load/store. |
7592 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
7593 | static void | |
7594 | do_lstc (void) | |
7595 | { | |
7596 | inst.instruction |= inst.operands[0].reg << 8; | |
7597 | inst.instruction |= inst.operands[1].reg << 12; | |
7598 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
7599 | } |
7600 | ||
b05fe5cf | 7601 | static void |
c19d1205 | 7602 | do_mlas (void) |
b05fe5cf | 7603 | { |
8fb9d7b9 | 7604 | /* This restriction does not apply to mls (nor to mla in v6 or later). */ |
c19d1205 | 7605 | if (inst.operands[0].reg == inst.operands[1].reg |
8fb9d7b9 | 7606 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) |
c19d1205 | 7607 | && !(inst.instruction & 0x00400000)) |
8fb9d7b9 | 7608 | as_tsktsk (_("Rd and Rm should be different in mla")); |
b05fe5cf | 7609 | |
c19d1205 ZW |
7610 | inst.instruction |= inst.operands[0].reg << 16; |
7611 | inst.instruction |= inst.operands[1].reg; | |
7612 | inst.instruction |= inst.operands[2].reg << 8; | |
7613 | inst.instruction |= inst.operands[3].reg << 12; | |
c19d1205 | 7614 | } |
b05fe5cf | 7615 | |
c19d1205 ZW |
7616 | static void |
7617 | do_mov (void) | |
7618 | { | |
7619 | inst.instruction |= inst.operands[0].reg << 12; | |
7620 | encode_arm_shifter_operand (1); | |
7621 | } | |
b05fe5cf | 7622 | |
c19d1205 ZW |
7623 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
7624 | static void | |
7625 | do_mov16 (void) | |
7626 | { | |
b6895b4f PB |
7627 | bfd_vma imm; |
7628 | bfd_boolean top; | |
7629 | ||
7630 | top = (inst.instruction & 0x00400000) != 0; | |
7631 | constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, | |
7632 | _(":lower16: not allowed this instruction")); | |
7633 | constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, | |
7634 | _(":upper16: not allowed instruction")); | |
c19d1205 | 7635 | inst.instruction |= inst.operands[0].reg << 12; |
b6895b4f PB |
7636 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
7637 | { | |
7638 | imm = inst.reloc.exp.X_add_number; | |
7639 | /* The value is in two pieces: 0:11, 16:19. */ | |
7640 | inst.instruction |= (imm & 0x00000fff); | |
7641 | inst.instruction |= (imm & 0x0000f000) << 4; | |
7642 | } | |
b05fe5cf | 7643 | } |
b99bd4ef | 7644 | |
037e8744 JB |
7645 | static void do_vfp_nsyn_opcode (const char *); |
7646 | ||
7647 | static int | |
7648 | do_vfp_nsyn_mrs (void) | |
7649 | { | |
7650 | if (inst.operands[0].isvec) | |
7651 | { | |
7652 | if (inst.operands[1].reg != 1) | |
7653 | first_error (_("operand 1 must be FPSCR")); | |
7654 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
7655 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); | |
7656 | do_vfp_nsyn_opcode ("fmstat"); | |
7657 | } | |
7658 | else if (inst.operands[1].isvec) | |
7659 | do_vfp_nsyn_opcode ("fmrx"); | |
7660 | else | |
7661 | return FAIL; | |
5f4273c7 | 7662 | |
037e8744 JB |
7663 | return SUCCESS; |
7664 | } | |
7665 | ||
7666 | static int | |
7667 | do_vfp_nsyn_msr (void) | |
7668 | { | |
7669 | if (inst.operands[0].isvec) | |
7670 | do_vfp_nsyn_opcode ("fmxr"); | |
7671 | else | |
7672 | return FAIL; | |
7673 | ||
7674 | return SUCCESS; | |
7675 | } | |
7676 | ||
f7c21dc7 NC |
7677 | static void |
7678 | do_vmrs (void) | |
7679 | { | |
7680 | unsigned Rt = inst.operands[0].reg; | |
7681 | ||
7682 | if (thumb_mode && inst.operands[0].reg == REG_SP) | |
7683 | { | |
7684 | inst.error = BAD_SP; | |
7685 | return; | |
7686 | } | |
7687 | ||
7688 | /* APSR_ sets isvec. All other refs to PC are illegal. */ | |
7689 | if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC) | |
7690 | { | |
7691 | inst.error = BAD_PC; | |
7692 | return; | |
7693 | } | |
7694 | ||
7695 | if (inst.operands[1].reg != 1) | |
7696 | first_error (_("operand 1 must be FPSCR")); | |
7697 | ||
7698 | inst.instruction |= (Rt << 12); | |
7699 | } | |
7700 | ||
7701 | static void | |
7702 | do_vmsr (void) | |
7703 | { | |
7704 | unsigned Rt = inst.operands[1].reg; | |
7705 | ||
7706 | if (thumb_mode) | |
7707 | reject_bad_reg (Rt); | |
7708 | else if (Rt == REG_PC) | |
7709 | { | |
7710 | inst.error = BAD_PC; | |
7711 | return; | |
7712 | } | |
7713 | ||
7714 | if (inst.operands[0].reg != 1) | |
7715 | first_error (_("operand 0 must be FPSCR")); | |
7716 | ||
7717 | inst.instruction |= (Rt << 12); | |
7718 | } | |
7719 | ||
b99bd4ef | 7720 | static void |
c19d1205 | 7721 | do_mrs (void) |
b99bd4ef | 7722 | { |
037e8744 JB |
7723 | if (do_vfp_nsyn_mrs () == SUCCESS) |
7724 | return; | |
7725 | ||
c19d1205 ZW |
7726 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ |
7727 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
7728 | != (PSR_c|PSR_f), | |
7729 | _("'CPSR' or 'SPSR' expected")); | |
ff4a8d2b | 7730 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
7731 | inst.instruction |= inst.operands[0].reg << 12; |
7732 | inst.instruction |= (inst.operands[1].imm & SPSR_BIT); | |
7733 | } | |
b99bd4ef | 7734 | |
c19d1205 ZW |
7735 | /* Two possible forms: |
7736 | "{C|S}PSR_<field>, Rm", | |
7737 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 7738 | |
c19d1205 ZW |
7739 | static void |
7740 | do_msr (void) | |
7741 | { | |
037e8744 JB |
7742 | if (do_vfp_nsyn_msr () == SUCCESS) |
7743 | return; | |
7744 | ||
c19d1205 ZW |
7745 | inst.instruction |= inst.operands[0].imm; |
7746 | if (inst.operands[1].isreg) | |
7747 | inst.instruction |= inst.operands[1].reg; | |
7748 | else | |
b99bd4ef | 7749 | { |
c19d1205 ZW |
7750 | inst.instruction |= INST_IMMEDIATE; |
7751 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
7752 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 7753 | } |
b99bd4ef NC |
7754 | } |
7755 | ||
c19d1205 ZW |
7756 | static void |
7757 | do_mul (void) | |
a737bd4d | 7758 | { |
ff4a8d2b NC |
7759 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
7760 | ||
c19d1205 ZW |
7761 | if (!inst.operands[2].present) |
7762 | inst.operands[2].reg = inst.operands[0].reg; | |
7763 | inst.instruction |= inst.operands[0].reg << 16; | |
7764 | inst.instruction |= inst.operands[1].reg; | |
7765 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 7766 | |
8fb9d7b9 MS |
7767 | if (inst.operands[0].reg == inst.operands[1].reg |
7768 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
7769 | as_tsktsk (_("Rd and Rm should be different in mul")); | |
a737bd4d NC |
7770 | } |
7771 | ||
c19d1205 ZW |
7772 | /* Long Multiply Parser |
7773 | UMULL RdLo, RdHi, Rm, Rs | |
7774 | SMULL RdLo, RdHi, Rm, Rs | |
7775 | UMLAL RdLo, RdHi, Rm, Rs | |
7776 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
7777 | |
7778 | static void | |
c19d1205 | 7779 | do_mull (void) |
b99bd4ef | 7780 | { |
c19d1205 ZW |
7781 | inst.instruction |= inst.operands[0].reg << 12; |
7782 | inst.instruction |= inst.operands[1].reg << 16; | |
7783 | inst.instruction |= inst.operands[2].reg; | |
7784 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 7785 | |
682b27ad PB |
7786 | /* rdhi and rdlo must be different. */ |
7787 | if (inst.operands[0].reg == inst.operands[1].reg) | |
7788 | as_tsktsk (_("rdhi and rdlo must be different")); | |
7789 | ||
7790 | /* rdhi, rdlo and rm must all be different before armv6. */ | |
7791 | if ((inst.operands[0].reg == inst.operands[2].reg | |
c19d1205 | 7792 | || inst.operands[1].reg == inst.operands[2].reg) |
682b27ad | 7793 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
c19d1205 ZW |
7794 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); |
7795 | } | |
b99bd4ef | 7796 | |
c19d1205 ZW |
7797 | static void |
7798 | do_nop (void) | |
7799 | { | |
e7495e45 NS |
7800 | if (inst.operands[0].present |
7801 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) | |
c19d1205 ZW |
7802 | { |
7803 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
7804 | inst.instruction &= 0xf0000000; | |
e7495e45 NS |
7805 | inst.instruction |= 0x0320f000; |
7806 | if (inst.operands[0].present) | |
7807 | inst.instruction |= inst.operands[0].imm; | |
c19d1205 | 7808 | } |
b99bd4ef NC |
7809 | } |
7810 | ||
c19d1205 ZW |
7811 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
7812 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
7813 | Condition defaults to COND_ALWAYS. | |
7814 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
7815 | |
7816 | static void | |
c19d1205 | 7817 | do_pkhbt (void) |
b99bd4ef | 7818 | { |
c19d1205 ZW |
7819 | inst.instruction |= inst.operands[0].reg << 12; |
7820 | inst.instruction |= inst.operands[1].reg << 16; | |
7821 | inst.instruction |= inst.operands[2].reg; | |
7822 | if (inst.operands[3].present) | |
7823 | encode_arm_shift (3); | |
7824 | } | |
b99bd4ef | 7825 | |
c19d1205 | 7826 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 7827 | |
c19d1205 ZW |
7828 | static void |
7829 | do_pkhtb (void) | |
7830 | { | |
7831 | if (!inst.operands[3].present) | |
b99bd4ef | 7832 | { |
c19d1205 ZW |
7833 | /* If the shift specifier is omitted, turn the instruction |
7834 | into pkhbt rd, rm, rn. */ | |
7835 | inst.instruction &= 0xfff00010; | |
7836 | inst.instruction |= inst.operands[0].reg << 12; | |
7837 | inst.instruction |= inst.operands[1].reg; | |
7838 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
7839 | } |
7840 | else | |
7841 | { | |
c19d1205 ZW |
7842 | inst.instruction |= inst.operands[0].reg << 12; |
7843 | inst.instruction |= inst.operands[1].reg << 16; | |
7844 | inst.instruction |= inst.operands[2].reg; | |
7845 | encode_arm_shift (3); | |
b99bd4ef NC |
7846 | } |
7847 | } | |
7848 | ||
c19d1205 ZW |
7849 | /* ARMv5TE: Preload-Cache |
7850 | ||
7851 | PLD <addr_mode> | |
7852 | ||
7853 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
7854 | |
7855 | static void | |
c19d1205 | 7856 | do_pld (void) |
b99bd4ef | 7857 | { |
c19d1205 ZW |
7858 | constraint (!inst.operands[0].isreg, |
7859 | _("'[' expected after PLD mnemonic")); | |
7860 | constraint (inst.operands[0].postind, | |
7861 | _("post-indexed expression used in preload instruction")); | |
7862 | constraint (inst.operands[0].writeback, | |
7863 | _("writeback used in preload instruction")); | |
7864 | constraint (!inst.operands[0].preind, | |
7865 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
7866 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
7867 | } | |
b99bd4ef | 7868 | |
62b3e311 PB |
7869 | /* ARMv7: PLI <addr_mode> */ |
7870 | static void | |
7871 | do_pli (void) | |
7872 | { | |
7873 | constraint (!inst.operands[0].isreg, | |
7874 | _("'[' expected after PLI mnemonic")); | |
7875 | constraint (inst.operands[0].postind, | |
7876 | _("post-indexed expression used in preload instruction")); | |
7877 | constraint (inst.operands[0].writeback, | |
7878 | _("writeback used in preload instruction")); | |
7879 | constraint (!inst.operands[0].preind, | |
7880 | _("unindexed addressing used in preload instruction")); | |
7881 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
7882 | inst.instruction &= ~PRE_INDEX; | |
7883 | } | |
7884 | ||
c19d1205 ZW |
7885 | static void |
7886 | do_push_pop (void) | |
7887 | { | |
7888 | inst.operands[1] = inst.operands[0]; | |
7889 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
7890 | inst.operands[0].isreg = 1; | |
7891 | inst.operands[0].writeback = 1; | |
7892 | inst.operands[0].reg = REG_SP; | |
7893 | do_ldmstm (); | |
7894 | } | |
b99bd4ef | 7895 | |
c19d1205 ZW |
7896 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
7897 | word at the specified address and the following word | |
7898 | respectively. | |
7899 | Unconditionally executed. | |
7900 | Error if Rn is R15. */ | |
b99bd4ef | 7901 | |
c19d1205 ZW |
7902 | static void |
7903 | do_rfe (void) | |
7904 | { | |
7905 | inst.instruction |= inst.operands[0].reg << 16; | |
7906 | if (inst.operands[0].writeback) | |
7907 | inst.instruction |= WRITE_BACK; | |
7908 | } | |
b99bd4ef | 7909 | |
c19d1205 | 7910 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 7911 | |
c19d1205 ZW |
7912 | static void |
7913 | do_ssat (void) | |
7914 | { | |
7915 | inst.instruction |= inst.operands[0].reg << 12; | |
7916 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
7917 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 7918 | |
c19d1205 ZW |
7919 | if (inst.operands[3].present) |
7920 | encode_arm_shift (3); | |
b99bd4ef NC |
7921 | } |
7922 | ||
c19d1205 | 7923 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
7924 | |
7925 | static void | |
c19d1205 | 7926 | do_usat (void) |
b99bd4ef | 7927 | { |
c19d1205 ZW |
7928 | inst.instruction |= inst.operands[0].reg << 12; |
7929 | inst.instruction |= inst.operands[1].imm << 16; | |
7930 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 7931 | |
c19d1205 ZW |
7932 | if (inst.operands[3].present) |
7933 | encode_arm_shift (3); | |
b99bd4ef NC |
7934 | } |
7935 | ||
c19d1205 | 7936 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
7937 | |
7938 | static void | |
c19d1205 | 7939 | do_ssat16 (void) |
09d92015 | 7940 | { |
c19d1205 ZW |
7941 | inst.instruction |= inst.operands[0].reg << 12; |
7942 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
7943 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
7944 | } |
7945 | ||
c19d1205 ZW |
7946 | static void |
7947 | do_usat16 (void) | |
a737bd4d | 7948 | { |
c19d1205 ZW |
7949 | inst.instruction |= inst.operands[0].reg << 12; |
7950 | inst.instruction |= inst.operands[1].imm << 16; | |
7951 | inst.instruction |= inst.operands[2].reg; | |
7952 | } | |
a737bd4d | 7953 | |
c19d1205 ZW |
7954 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
7955 | preserving the other bits. | |
a737bd4d | 7956 | |
c19d1205 ZW |
7957 | setend <endian_specifier>, where <endian_specifier> is either |
7958 | BE or LE. */ | |
a737bd4d | 7959 | |
c19d1205 ZW |
7960 | static void |
7961 | do_setend (void) | |
7962 | { | |
7963 | if (inst.operands[0].imm) | |
7964 | inst.instruction |= 0x200; | |
a737bd4d NC |
7965 | } |
7966 | ||
7967 | static void | |
c19d1205 | 7968 | do_shift (void) |
a737bd4d | 7969 | { |
c19d1205 ZW |
7970 | unsigned int Rm = (inst.operands[1].present |
7971 | ? inst.operands[1].reg | |
7972 | : inst.operands[0].reg); | |
a737bd4d | 7973 | |
c19d1205 ZW |
7974 | inst.instruction |= inst.operands[0].reg << 12; |
7975 | inst.instruction |= Rm; | |
7976 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 7977 | { |
c19d1205 ZW |
7978 | inst.instruction |= inst.operands[2].reg << 8; |
7979 | inst.instruction |= SHIFT_BY_REG; | |
a737bd4d NC |
7980 | } |
7981 | else | |
c19d1205 | 7982 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
7983 | } |
7984 | ||
09d92015 | 7985 | static void |
3eb17e6b | 7986 | do_smc (void) |
09d92015 | 7987 | { |
3eb17e6b | 7988 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 7989 | inst.reloc.pc_rel = 0; |
09d92015 MM |
7990 | } |
7991 | ||
09d92015 | 7992 | static void |
c19d1205 | 7993 | do_swi (void) |
09d92015 | 7994 | { |
c19d1205 ZW |
7995 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
7996 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
7997 | } |
7998 | ||
c19d1205 ZW |
7999 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
8000 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
8001 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
8002 | Error if any register is R15. */ | |
e16bb312 | 8003 | |
c19d1205 ZW |
8004 | static void |
8005 | do_smla (void) | |
e16bb312 | 8006 | { |
c19d1205 ZW |
8007 | inst.instruction |= inst.operands[0].reg << 16; |
8008 | inst.instruction |= inst.operands[1].reg; | |
8009 | inst.instruction |= inst.operands[2].reg << 8; | |
8010 | inst.instruction |= inst.operands[3].reg << 12; | |
8011 | } | |
a737bd4d | 8012 | |
c19d1205 ZW |
8013 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
8014 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
8015 | Error if any register is R15. | |
8016 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 8017 | |
c19d1205 ZW |
8018 | static void |
8019 | do_smlal (void) | |
8020 | { | |
8021 | inst.instruction |= inst.operands[0].reg << 12; | |
8022 | inst.instruction |= inst.operands[1].reg << 16; | |
8023 | inst.instruction |= inst.operands[2].reg; | |
8024 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 8025 | |
c19d1205 ZW |
8026 | if (inst.operands[0].reg == inst.operands[1].reg) |
8027 | as_tsktsk (_("rdhi and rdlo must be different")); | |
8028 | } | |
a737bd4d | 8029 | |
c19d1205 ZW |
8030 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
8031 | SMULxy{cond} Rd,Rm,Rs | |
8032 | Error if any register is R15. */ | |
a737bd4d | 8033 | |
c19d1205 ZW |
8034 | static void |
8035 | do_smul (void) | |
8036 | { | |
8037 | inst.instruction |= inst.operands[0].reg << 16; | |
8038 | inst.instruction |= inst.operands[1].reg; | |
8039 | inst.instruction |= inst.operands[2].reg << 8; | |
8040 | } | |
a737bd4d | 8041 | |
b6702015 PB |
8042 | /* ARM V6 srs (argument parse). The variable fields in the encoding are |
8043 | the same for both ARM and Thumb-2. */ | |
a737bd4d | 8044 | |
c19d1205 ZW |
8045 | static void |
8046 | do_srs (void) | |
8047 | { | |
b6702015 PB |
8048 | int reg; |
8049 | ||
8050 | if (inst.operands[0].present) | |
8051 | { | |
8052 | reg = inst.operands[0].reg; | |
fdfde340 | 8053 | constraint (reg != REG_SP, _("SRS base register must be r13")); |
b6702015 PB |
8054 | } |
8055 | else | |
fdfde340 | 8056 | reg = REG_SP; |
b6702015 PB |
8057 | |
8058 | inst.instruction |= reg << 16; | |
8059 | inst.instruction |= inst.operands[1].imm; | |
8060 | if (inst.operands[0].writeback || inst.operands[1].writeback) | |
c19d1205 ZW |
8061 | inst.instruction |= WRITE_BACK; |
8062 | } | |
a737bd4d | 8063 | |
c19d1205 | 8064 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 8065 | |
c19d1205 ZW |
8066 | static void |
8067 | do_strex (void) | |
8068 | { | |
8069 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
8070 | || inst.operands[2].postind || inst.operands[2].writeback | |
8071 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
8072 | || inst.operands[2].negative |
8073 | /* See comment in do_ldrex(). */ | |
8074 | || (inst.operands[2].reg == REG_PC), | |
8075 | BAD_ADDR_MODE); | |
a737bd4d | 8076 | |
c19d1205 ZW |
8077 | constraint (inst.operands[0].reg == inst.operands[1].reg |
8078 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 8079 | |
c19d1205 ZW |
8080 | constraint (inst.reloc.exp.X_op != O_constant |
8081 | || inst.reloc.exp.X_add_number != 0, | |
8082 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 8083 | |
c19d1205 ZW |
8084 | inst.instruction |= inst.operands[0].reg << 12; |
8085 | inst.instruction |= inst.operands[1].reg; | |
8086 | inst.instruction |= inst.operands[2].reg << 16; | |
8087 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
8088 | } |
8089 | ||
8090 | static void | |
c19d1205 | 8091 | do_strexd (void) |
e16bb312 | 8092 | { |
c19d1205 ZW |
8093 | constraint (inst.operands[1].reg % 2 != 0, |
8094 | _("even register required")); | |
8095 | constraint (inst.operands[2].present | |
8096 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
8097 | _("can only store two consecutive registers")); | |
8098 | /* If op 2 were present and equal to PC, this function wouldn't | |
8099 | have been called in the first place. */ | |
8100 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 8101 | |
c19d1205 ZW |
8102 | constraint (inst.operands[0].reg == inst.operands[1].reg |
8103 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
8104 | || inst.operands[0].reg == inst.operands[3].reg, | |
8105 | BAD_OVERLAP); | |
e16bb312 | 8106 | |
c19d1205 ZW |
8107 | inst.instruction |= inst.operands[0].reg << 12; |
8108 | inst.instruction |= inst.operands[1].reg; | |
8109 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
8110 | } |
8111 | ||
c19d1205 ZW |
8112 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
8113 | extends it to 32-bits, and adds the result to a value in another | |
8114 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
8115 | before extracting the 16-bit value. | |
8116 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
8117 | Condition defaults to COND_ALWAYS. | |
8118 | Error if any register uses R15. */ | |
8119 | ||
e16bb312 | 8120 | static void |
c19d1205 | 8121 | do_sxtah (void) |
e16bb312 | 8122 | { |
c19d1205 ZW |
8123 | inst.instruction |= inst.operands[0].reg << 12; |
8124 | inst.instruction |= inst.operands[1].reg << 16; | |
8125 | inst.instruction |= inst.operands[2].reg; | |
8126 | inst.instruction |= inst.operands[3].imm << 10; | |
8127 | } | |
e16bb312 | 8128 | |
c19d1205 | 8129 | /* ARM V6 SXTH. |
e16bb312 | 8130 | |
c19d1205 ZW |
8131 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
8132 | Condition defaults to COND_ALWAYS. | |
8133 | Error if any register uses R15. */ | |
e16bb312 NC |
8134 | |
8135 | static void | |
c19d1205 | 8136 | do_sxth (void) |
e16bb312 | 8137 | { |
c19d1205 ZW |
8138 | inst.instruction |= inst.operands[0].reg << 12; |
8139 | inst.instruction |= inst.operands[1].reg; | |
8140 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 8141 | } |
c19d1205 ZW |
8142 | \f |
8143 | /* VFP instructions. In a logical order: SP variant first, monad | |
8144 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
8145 | |
8146 | static void | |
c19d1205 | 8147 | do_vfp_sp_monadic (void) |
e16bb312 | 8148 | { |
5287ad62 JB |
8149 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8150 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
8151 | } |
8152 | ||
8153 | static void | |
c19d1205 | 8154 | do_vfp_sp_dyadic (void) |
e16bb312 | 8155 | { |
5287ad62 JB |
8156 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8157 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
8158 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
8159 | } |
8160 | ||
8161 | static void | |
c19d1205 | 8162 | do_vfp_sp_compare_z (void) |
e16bb312 | 8163 | { |
5287ad62 | 8164 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
8165 | } |
8166 | ||
8167 | static void | |
c19d1205 | 8168 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 8169 | { |
5287ad62 JB |
8170 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
8171 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
8172 | } |
8173 | ||
8174 | static void | |
c19d1205 | 8175 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 8176 | { |
5287ad62 JB |
8177 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8178 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
e16bb312 NC |
8179 | } |
8180 | ||
8181 | static void | |
c19d1205 | 8182 | do_vfp_reg_from_sp (void) |
e16bb312 | 8183 | { |
c19d1205 | 8184 | inst.instruction |= inst.operands[0].reg << 12; |
5287ad62 | 8185 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
e16bb312 NC |
8186 | } |
8187 | ||
8188 | static void | |
c19d1205 | 8189 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 8190 | { |
c19d1205 ZW |
8191 | constraint (inst.operands[2].imm != 2, |
8192 | _("only two consecutive VFP SP registers allowed here")); | |
8193 | inst.instruction |= inst.operands[0].reg << 12; | |
8194 | inst.instruction |= inst.operands[1].reg << 16; | |
5287ad62 | 8195 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
e16bb312 NC |
8196 | } |
8197 | ||
8198 | static void | |
c19d1205 | 8199 | do_vfp_sp_from_reg (void) |
e16bb312 | 8200 | { |
5287ad62 | 8201 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
c19d1205 | 8202 | inst.instruction |= inst.operands[1].reg << 12; |
e16bb312 NC |
8203 | } |
8204 | ||
8205 | static void | |
c19d1205 | 8206 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 8207 | { |
c19d1205 ZW |
8208 | constraint (inst.operands[0].imm != 2, |
8209 | _("only two consecutive VFP SP registers allowed here")); | |
5287ad62 | 8210 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
c19d1205 ZW |
8211 | inst.instruction |= inst.operands[1].reg << 12; |
8212 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
8213 | } |
8214 | ||
8215 | static void | |
c19d1205 | 8216 | do_vfp_sp_ldst (void) |
e16bb312 | 8217 | { |
5287ad62 | 8218 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
c19d1205 | 8219 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
8220 | } |
8221 | ||
8222 | static void | |
c19d1205 | 8223 | do_vfp_dp_ldst (void) |
e16bb312 | 8224 | { |
5287ad62 | 8225 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
c19d1205 | 8226 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
8227 | } |
8228 | ||
c19d1205 | 8229 | |
e16bb312 | 8230 | static void |
c19d1205 | 8231 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 8232 | { |
c19d1205 ZW |
8233 | if (inst.operands[0].writeback) |
8234 | inst.instruction |= WRITE_BACK; | |
8235 | else | |
8236 | constraint (ldstm_type != VFP_LDSTMIA, | |
8237 | _("this addressing mode requires base-register writeback")); | |
8238 | inst.instruction |= inst.operands[0].reg << 16; | |
5287ad62 | 8239 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
c19d1205 | 8240 | inst.instruction |= inst.operands[1].imm; |
e16bb312 NC |
8241 | } |
8242 | ||
8243 | static void | |
c19d1205 | 8244 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 8245 | { |
c19d1205 | 8246 | int count; |
e16bb312 | 8247 | |
c19d1205 ZW |
8248 | if (inst.operands[0].writeback) |
8249 | inst.instruction |= WRITE_BACK; | |
8250 | else | |
8251 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
8252 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 8253 | |
c19d1205 | 8254 | inst.instruction |= inst.operands[0].reg << 16; |
5287ad62 | 8255 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
e16bb312 | 8256 | |
c19d1205 ZW |
8257 | count = inst.operands[1].imm << 1; |
8258 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
8259 | count += 1; | |
e16bb312 | 8260 | |
c19d1205 | 8261 | inst.instruction |= count; |
e16bb312 NC |
8262 | } |
8263 | ||
8264 | static void | |
c19d1205 | 8265 | do_vfp_sp_ldstmia (void) |
e16bb312 | 8266 | { |
c19d1205 | 8267 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
8268 | } |
8269 | ||
8270 | static void | |
c19d1205 | 8271 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 8272 | { |
c19d1205 | 8273 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
8274 | } |
8275 | ||
8276 | static void | |
c19d1205 | 8277 | do_vfp_dp_ldstmia (void) |
e16bb312 | 8278 | { |
c19d1205 | 8279 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
8280 | } |
8281 | ||
8282 | static void | |
c19d1205 | 8283 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 8284 | { |
c19d1205 | 8285 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
8286 | } |
8287 | ||
8288 | static void | |
c19d1205 | 8289 | do_vfp_xp_ldstmia (void) |
e16bb312 | 8290 | { |
c19d1205 ZW |
8291 | vfp_dp_ldstm (VFP_LDSTMIAX); |
8292 | } | |
e16bb312 | 8293 | |
c19d1205 ZW |
8294 | static void |
8295 | do_vfp_xp_ldstmdb (void) | |
8296 | { | |
8297 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 8298 | } |
5287ad62 JB |
8299 | |
8300 | static void | |
8301 | do_vfp_dp_rd_rm (void) | |
8302 | { | |
8303 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8304 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
8305 | } | |
8306 | ||
8307 | static void | |
8308 | do_vfp_dp_rn_rd (void) | |
8309 | { | |
8310 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); | |
8311 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
8312 | } | |
8313 | ||
8314 | static void | |
8315 | do_vfp_dp_rd_rn (void) | |
8316 | { | |
8317 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8318 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
8319 | } | |
8320 | ||
8321 | static void | |
8322 | do_vfp_dp_rd_rn_rm (void) | |
8323 | { | |
8324 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8325 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
8326 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); | |
8327 | } | |
8328 | ||
8329 | static void | |
8330 | do_vfp_dp_rd (void) | |
8331 | { | |
8332 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8333 | } | |
8334 | ||
8335 | static void | |
8336 | do_vfp_dp_rm_rd_rn (void) | |
8337 | { | |
8338 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); | |
8339 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
8340 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); | |
8341 | } | |
8342 | ||
8343 | /* VFPv3 instructions. */ | |
8344 | static void | |
8345 | do_vfp_sp_const (void) | |
8346 | { | |
8347 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
00249aaa PB |
8348 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
8349 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
8350 | } |
8351 | ||
8352 | static void | |
8353 | do_vfp_dp_const (void) | |
8354 | { | |
8355 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
00249aaa PB |
8356 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
8357 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
8358 | } |
8359 | ||
8360 | static void | |
8361 | vfp_conv (int srcsize) | |
8362 | { | |
8363 | unsigned immbits = srcsize - inst.operands[1].imm; | |
8364 | inst.instruction |= (immbits & 1) << 5; | |
8365 | inst.instruction |= (immbits >> 1); | |
8366 | } | |
8367 | ||
8368 | static void | |
8369 | do_vfp_sp_conv_16 (void) | |
8370 | { | |
8371 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
8372 | vfp_conv (16); | |
8373 | } | |
8374 | ||
8375 | static void | |
8376 | do_vfp_dp_conv_16 (void) | |
8377 | { | |
8378 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8379 | vfp_conv (16); | |
8380 | } | |
8381 | ||
8382 | static void | |
8383 | do_vfp_sp_conv_32 (void) | |
8384 | { | |
8385 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
8386 | vfp_conv (32); | |
8387 | } | |
8388 | ||
8389 | static void | |
8390 | do_vfp_dp_conv_32 (void) | |
8391 | { | |
8392 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8393 | vfp_conv (32); | |
8394 | } | |
c19d1205 ZW |
8395 | \f |
8396 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 8397 | |
c19d1205 ZW |
8398 | static void |
8399 | do_fpa_cmp (void) | |
8400 | { | |
8401 | inst.instruction |= inst.operands[0].reg << 16; | |
8402 | inst.instruction |= inst.operands[1].reg; | |
8403 | } | |
b99bd4ef NC |
8404 | |
8405 | static void | |
c19d1205 | 8406 | do_fpa_ldmstm (void) |
b99bd4ef | 8407 | { |
c19d1205 ZW |
8408 | inst.instruction |= inst.operands[0].reg << 12; |
8409 | switch (inst.operands[1].imm) | |
8410 | { | |
8411 | case 1: inst.instruction |= CP_T_X; break; | |
8412 | case 2: inst.instruction |= CP_T_Y; break; | |
8413 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
8414 | case 4: break; | |
8415 | default: abort (); | |
8416 | } | |
b99bd4ef | 8417 | |
c19d1205 ZW |
8418 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
8419 | { | |
8420 | /* The instruction specified "ea" or "fd", so we can only accept | |
8421 | [Rn]{!}. The instruction does not really support stacking or | |
8422 | unstacking, so we have to emulate these by setting appropriate | |
8423 | bits and offsets. */ | |
8424 | constraint (inst.reloc.exp.X_op != O_constant | |
8425 | || inst.reloc.exp.X_add_number != 0, | |
8426 | _("this instruction does not support indexing")); | |
b99bd4ef | 8427 | |
c19d1205 ZW |
8428 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
8429 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 8430 | |
c19d1205 ZW |
8431 | if (!(inst.instruction & INDEX_UP)) |
8432 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 8433 | |
c19d1205 ZW |
8434 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
8435 | { | |
8436 | inst.operands[2].preind = 0; | |
8437 | inst.operands[2].postind = 1; | |
8438 | } | |
8439 | } | |
b99bd4ef | 8440 | |
c19d1205 | 8441 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 8442 | } |
c19d1205 ZW |
8443 | \f |
8444 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 8445 | |
c19d1205 ZW |
8446 | static void |
8447 | do_iwmmxt_tandorc (void) | |
8448 | { | |
8449 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
8450 | } | |
b99bd4ef | 8451 | |
c19d1205 ZW |
8452 | static void |
8453 | do_iwmmxt_textrc (void) | |
8454 | { | |
8455 | inst.instruction |= inst.operands[0].reg << 12; | |
8456 | inst.instruction |= inst.operands[1].imm; | |
8457 | } | |
b99bd4ef NC |
8458 | |
8459 | static void | |
c19d1205 | 8460 | do_iwmmxt_textrm (void) |
b99bd4ef | 8461 | { |
c19d1205 ZW |
8462 | inst.instruction |= inst.operands[0].reg << 12; |
8463 | inst.instruction |= inst.operands[1].reg << 16; | |
8464 | inst.instruction |= inst.operands[2].imm; | |
8465 | } | |
b99bd4ef | 8466 | |
c19d1205 ZW |
8467 | static void |
8468 | do_iwmmxt_tinsr (void) | |
8469 | { | |
8470 | inst.instruction |= inst.operands[0].reg << 16; | |
8471 | inst.instruction |= inst.operands[1].reg << 12; | |
8472 | inst.instruction |= inst.operands[2].imm; | |
8473 | } | |
b99bd4ef | 8474 | |
c19d1205 ZW |
8475 | static void |
8476 | do_iwmmxt_tmia (void) | |
8477 | { | |
8478 | inst.instruction |= inst.operands[0].reg << 5; | |
8479 | inst.instruction |= inst.operands[1].reg; | |
8480 | inst.instruction |= inst.operands[2].reg << 12; | |
8481 | } | |
b99bd4ef | 8482 | |
c19d1205 ZW |
8483 | static void |
8484 | do_iwmmxt_waligni (void) | |
8485 | { | |
8486 | inst.instruction |= inst.operands[0].reg << 12; | |
8487 | inst.instruction |= inst.operands[1].reg << 16; | |
8488 | inst.instruction |= inst.operands[2].reg; | |
8489 | inst.instruction |= inst.operands[3].imm << 20; | |
8490 | } | |
b99bd4ef | 8491 | |
2d447fca JM |
8492 | static void |
8493 | do_iwmmxt_wmerge (void) | |
8494 | { | |
8495 | inst.instruction |= inst.operands[0].reg << 12; | |
8496 | inst.instruction |= inst.operands[1].reg << 16; | |
8497 | inst.instruction |= inst.operands[2].reg; | |
8498 | inst.instruction |= inst.operands[3].imm << 21; | |
8499 | } | |
8500 | ||
c19d1205 ZW |
8501 | static void |
8502 | do_iwmmxt_wmov (void) | |
8503 | { | |
8504 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
8505 | inst.instruction |= inst.operands[0].reg << 12; | |
8506 | inst.instruction |= inst.operands[1].reg << 16; | |
8507 | inst.instruction |= inst.operands[1].reg; | |
8508 | } | |
b99bd4ef | 8509 | |
c19d1205 ZW |
8510 | static void |
8511 | do_iwmmxt_wldstbh (void) | |
8512 | { | |
8f06b2d8 | 8513 | int reloc; |
c19d1205 | 8514 | inst.instruction |= inst.operands[0].reg << 12; |
8f06b2d8 PB |
8515 | if (thumb_mode) |
8516 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
8517 | else | |
8518 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
8519 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
8520 | } |
8521 | ||
c19d1205 ZW |
8522 | static void |
8523 | do_iwmmxt_wldstw (void) | |
8524 | { | |
8525 | /* RIWR_RIWC clears .isreg for a control register. */ | |
8526 | if (!inst.operands[0].isreg) | |
8527 | { | |
8528 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
8529 | inst.instruction |= 0xf0000000; | |
8530 | } | |
b99bd4ef | 8531 | |
c19d1205 ZW |
8532 | inst.instruction |= inst.operands[0].reg << 12; |
8533 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
8534 | } | |
b99bd4ef NC |
8535 | |
8536 | static void | |
c19d1205 | 8537 | do_iwmmxt_wldstd (void) |
b99bd4ef | 8538 | { |
c19d1205 | 8539 | inst.instruction |= inst.operands[0].reg << 12; |
2d447fca JM |
8540 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) |
8541 | && inst.operands[1].immisreg) | |
8542 | { | |
8543 | inst.instruction &= ~0x1a000ff; | |
8544 | inst.instruction |= (0xf << 28); | |
8545 | if (inst.operands[1].preind) | |
8546 | inst.instruction |= PRE_INDEX; | |
8547 | if (!inst.operands[1].negative) | |
8548 | inst.instruction |= INDEX_UP; | |
8549 | if (inst.operands[1].writeback) | |
8550 | inst.instruction |= WRITE_BACK; | |
8551 | inst.instruction |= inst.operands[1].reg << 16; | |
8552 | inst.instruction |= inst.reloc.exp.X_add_number << 4; | |
8553 | inst.instruction |= inst.operands[1].imm; | |
8554 | } | |
8555 | else | |
8556 | encode_arm_cp_address (1, TRUE, FALSE, 0); | |
c19d1205 | 8557 | } |
b99bd4ef | 8558 | |
c19d1205 ZW |
8559 | static void |
8560 | do_iwmmxt_wshufh (void) | |
8561 | { | |
8562 | inst.instruction |= inst.operands[0].reg << 12; | |
8563 | inst.instruction |= inst.operands[1].reg << 16; | |
8564 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
8565 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
8566 | } | |
b99bd4ef | 8567 | |
c19d1205 ZW |
8568 | static void |
8569 | do_iwmmxt_wzero (void) | |
8570 | { | |
8571 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
8572 | inst.instruction |= inst.operands[0].reg; | |
8573 | inst.instruction |= inst.operands[0].reg << 12; | |
8574 | inst.instruction |= inst.operands[0].reg << 16; | |
8575 | } | |
2d447fca JM |
8576 | |
8577 | static void | |
8578 | do_iwmmxt_wrwrwr_or_imm5 (void) | |
8579 | { | |
8580 | if (inst.operands[2].isreg) | |
8581 | do_rd_rn_rm (); | |
8582 | else { | |
8583 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), | |
8584 | _("immediate operand requires iWMMXt2")); | |
8585 | do_rd_rn (); | |
8586 | if (inst.operands[2].imm == 0) | |
8587 | { | |
8588 | switch ((inst.instruction >> 20) & 0xf) | |
8589 | { | |
8590 | case 4: | |
8591 | case 5: | |
8592 | case 6: | |
5f4273c7 | 8593 | case 7: |
2d447fca JM |
8594 | /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ |
8595 | inst.operands[2].imm = 16; | |
8596 | inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); | |
8597 | break; | |
8598 | case 8: | |
8599 | case 9: | |
8600 | case 10: | |
8601 | case 11: | |
8602 | /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ | |
8603 | inst.operands[2].imm = 32; | |
8604 | inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); | |
8605 | break; | |
8606 | case 12: | |
8607 | case 13: | |
8608 | case 14: | |
8609 | case 15: | |
8610 | { | |
8611 | /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ | |
8612 | unsigned long wrn; | |
8613 | wrn = (inst.instruction >> 16) & 0xf; | |
8614 | inst.instruction &= 0xff0fff0f; | |
8615 | inst.instruction |= wrn; | |
8616 | /* Bail out here; the instruction is now assembled. */ | |
8617 | return; | |
8618 | } | |
8619 | } | |
8620 | } | |
8621 | /* Map 32 -> 0, etc. */ | |
8622 | inst.operands[2].imm &= 0x1f; | |
8623 | inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); | |
8624 | } | |
8625 | } | |
c19d1205 ZW |
8626 | \f |
8627 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
8628 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 8629 | |
c19d1205 | 8630 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 8631 | |
c19d1205 ZW |
8632 | static void |
8633 | do_mav_triple (void) | |
8634 | { | |
8635 | inst.instruction |= inst.operands[0].reg << 16; | |
8636 | inst.instruction |= inst.operands[1].reg; | |
8637 | inst.instruction |= inst.operands[2].reg << 12; | |
8638 | } | |
b99bd4ef | 8639 | |
c19d1205 ZW |
8640 | /* Insns like "foo W,X,Y,Z". |
8641 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 8642 | |
c19d1205 ZW |
8643 | static void |
8644 | do_mav_quad (void) | |
8645 | { | |
8646 | inst.instruction |= inst.operands[0].reg << 5; | |
8647 | inst.instruction |= inst.operands[1].reg << 12; | |
8648 | inst.instruction |= inst.operands[2].reg << 16; | |
8649 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
8650 | } |
8651 | ||
c19d1205 ZW |
8652 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
8653 | static void | |
8654 | do_mav_dspsc (void) | |
a737bd4d | 8655 | { |
c19d1205 ZW |
8656 | inst.instruction |= inst.operands[1].reg << 12; |
8657 | } | |
a737bd4d | 8658 | |
c19d1205 ZW |
8659 | /* Maverick shift immediate instructions. |
8660 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
8661 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 8662 | |
c19d1205 ZW |
8663 | static void |
8664 | do_mav_shift (void) | |
8665 | { | |
8666 | int imm = inst.operands[2].imm; | |
a737bd4d | 8667 | |
c19d1205 ZW |
8668 | inst.instruction |= inst.operands[0].reg << 12; |
8669 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 8670 | |
c19d1205 ZW |
8671 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
8672 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
8673 | Bit 4 should be 0. */ | |
8674 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 8675 | |
c19d1205 ZW |
8676 | inst.instruction |= imm; |
8677 | } | |
8678 | \f | |
8679 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 8680 | |
c19d1205 ZW |
8681 | /* Xscale multiply-accumulate (argument parse) |
8682 | MIAcc acc0,Rm,Rs | |
8683 | MIAPHcc acc0,Rm,Rs | |
8684 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 8685 | |
c19d1205 ZW |
8686 | static void |
8687 | do_xsc_mia (void) | |
8688 | { | |
8689 | inst.instruction |= inst.operands[1].reg; | |
8690 | inst.instruction |= inst.operands[2].reg << 12; | |
8691 | } | |
a737bd4d | 8692 | |
c19d1205 | 8693 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 8694 | |
c19d1205 | 8695 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 8696 | |
c19d1205 ZW |
8697 | static void |
8698 | do_xsc_mar (void) | |
8699 | { | |
8700 | inst.instruction |= inst.operands[1].reg << 12; | |
8701 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
8702 | } |
8703 | ||
c19d1205 | 8704 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 8705 | |
c19d1205 | 8706 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
8707 | |
8708 | static void | |
c19d1205 | 8709 | do_xsc_mra (void) |
b99bd4ef | 8710 | { |
c19d1205 ZW |
8711 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
8712 | inst.instruction |= inst.operands[0].reg << 12; | |
8713 | inst.instruction |= inst.operands[1].reg << 16; | |
8714 | } | |
8715 | \f | |
8716 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 8717 | |
c19d1205 ZW |
8718 | /* inst.operands[i] is a shifted-register operand; encode |
8719 | it into inst.instruction in the format used by Thumb32. */ | |
8720 | ||
8721 | static void | |
8722 | encode_thumb32_shifted_operand (int i) | |
8723 | { | |
8724 | unsigned int value = inst.reloc.exp.X_add_number; | |
8725 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 8726 | |
9c3c69f2 PB |
8727 | constraint (inst.operands[i].immisreg, |
8728 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
8729 | inst.instruction |= inst.operands[i].reg; |
8730 | if (shift == SHIFT_RRX) | |
8731 | inst.instruction |= SHIFT_ROR << 4; | |
8732 | else | |
b99bd4ef | 8733 | { |
c19d1205 ZW |
8734 | constraint (inst.reloc.exp.X_op != O_constant, |
8735 | _("expression too complex")); | |
8736 | ||
8737 | constraint (value > 32 | |
8738 | || (value == 32 && (shift == SHIFT_LSL | |
8739 | || shift == SHIFT_ROR)), | |
8740 | _("shift expression is too large")); | |
8741 | ||
8742 | if (value == 0) | |
8743 | shift = SHIFT_LSL; | |
8744 | else if (value == 32) | |
8745 | value = 0; | |
8746 | ||
8747 | inst.instruction |= shift << 4; | |
8748 | inst.instruction |= (value & 0x1c) << 10; | |
8749 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 8750 | } |
c19d1205 | 8751 | } |
b99bd4ef | 8752 | |
b99bd4ef | 8753 | |
c19d1205 ZW |
8754 | /* inst.operands[i] was set up by parse_address. Encode it into a |
8755 | Thumb32 format load or store instruction. Reject forms that cannot | |
8756 | be used with such instructions. If is_t is true, reject forms that | |
8757 | cannot be used with a T instruction; if is_d is true, reject forms | |
5be8be5d DG |
8758 | that cannot be used with a D instruction. If it is a store insn, |
8759 | reject PC in Rn. */ | |
b99bd4ef | 8760 | |
c19d1205 ZW |
8761 | static void |
8762 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
8763 | { | |
5be8be5d | 8764 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
c19d1205 ZW |
8765 | |
8766 | constraint (!inst.operands[i].isreg, | |
53365c0d | 8767 | _("Instruction does not support =N addresses")); |
b99bd4ef | 8768 | |
c19d1205 ZW |
8769 | inst.instruction |= inst.operands[i].reg << 16; |
8770 | if (inst.operands[i].immisreg) | |
b99bd4ef | 8771 | { |
5be8be5d | 8772 | constraint (is_pc, BAD_PC_ADDRESSING); |
c19d1205 ZW |
8773 | constraint (is_t || is_d, _("cannot use register index with this instruction")); |
8774 | constraint (inst.operands[i].negative, | |
8775 | _("Thumb does not support negative register indexing")); | |
8776 | constraint (inst.operands[i].postind, | |
8777 | _("Thumb does not support register post-indexing")); | |
8778 | constraint (inst.operands[i].writeback, | |
8779 | _("Thumb does not support register indexing with writeback")); | |
8780 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
8781 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 8782 | |
f40d1643 | 8783 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 8784 | if (inst.operands[i].shifted) |
b99bd4ef | 8785 | { |
c19d1205 ZW |
8786 | constraint (inst.reloc.exp.X_op != O_constant, |
8787 | _("expression too complex")); | |
9c3c69f2 PB |
8788 | constraint (inst.reloc.exp.X_add_number < 0 |
8789 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 8790 | _("shift out of range")); |
9c3c69f2 | 8791 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
8792 | } |
8793 | inst.reloc.type = BFD_RELOC_UNUSED; | |
8794 | } | |
8795 | else if (inst.operands[i].preind) | |
8796 | { | |
5be8be5d | 8797 | constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); |
f40d1643 | 8798 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 | 8799 | _("cannot use writeback with this instruction")); |
5be8be5d DG |
8800 | constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0) |
8801 | && !inst.reloc.pc_rel, BAD_PC_ADDRESSING); | |
c19d1205 ZW |
8802 | |
8803 | if (is_d) | |
8804 | { | |
8805 | inst.instruction |= 0x01000000; | |
8806 | if (inst.operands[i].writeback) | |
8807 | inst.instruction |= 0x00200000; | |
b99bd4ef | 8808 | } |
c19d1205 | 8809 | else |
b99bd4ef | 8810 | { |
c19d1205 ZW |
8811 | inst.instruction |= 0x00000c00; |
8812 | if (inst.operands[i].writeback) | |
8813 | inst.instruction |= 0x00000100; | |
b99bd4ef | 8814 | } |
c19d1205 | 8815 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 8816 | } |
c19d1205 | 8817 | else if (inst.operands[i].postind) |
b99bd4ef | 8818 | { |
9c2799c2 | 8819 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
8820 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); |
8821 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
8822 | ||
8823 | if (is_d) | |
8824 | inst.instruction |= 0x00200000; | |
8825 | else | |
8826 | inst.instruction |= 0x00000900; | |
8827 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
8828 | } | |
8829 | else /* unindexed - only for coprocessor */ | |
8830 | inst.error = _("instruction does not accept unindexed addressing"); | |
8831 | } | |
8832 | ||
8833 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
8834 | encodings (the latter only in post-V6T2 cores). The index is the | |
8835 | value used in the insns table below. When there is more than one | |
8836 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
8837 | holds variant (1). |
8838 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 | 8839 | #define T16_32_TAB \ |
21d799b5 NC |
8840 | X(_adc, 4140, eb400000), \ |
8841 | X(_adcs, 4140, eb500000), \ | |
8842 | X(_add, 1c00, eb000000), \ | |
8843 | X(_adds, 1c00, eb100000), \ | |
8844 | X(_addi, 0000, f1000000), \ | |
8845 | X(_addis, 0000, f1100000), \ | |
8846 | X(_add_pc,000f, f20f0000), \ | |
8847 | X(_add_sp,000d, f10d0000), \ | |
8848 | X(_adr, 000f, f20f0000), \ | |
8849 | X(_and, 4000, ea000000), \ | |
8850 | X(_ands, 4000, ea100000), \ | |
8851 | X(_asr, 1000, fa40f000), \ | |
8852 | X(_asrs, 1000, fa50f000), \ | |
8853 | X(_b, e000, f000b000), \ | |
8854 | X(_bcond, d000, f0008000), \ | |
8855 | X(_bic, 4380, ea200000), \ | |
8856 | X(_bics, 4380, ea300000), \ | |
8857 | X(_cmn, 42c0, eb100f00), \ | |
8858 | X(_cmp, 2800, ebb00f00), \ | |
8859 | X(_cpsie, b660, f3af8400), \ | |
8860 | X(_cpsid, b670, f3af8600), \ | |
8861 | X(_cpy, 4600, ea4f0000), \ | |
8862 | X(_dec_sp,80dd, f1ad0d00), \ | |
8863 | X(_eor, 4040, ea800000), \ | |
8864 | X(_eors, 4040, ea900000), \ | |
8865 | X(_inc_sp,00dd, f10d0d00), \ | |
8866 | X(_ldmia, c800, e8900000), \ | |
8867 | X(_ldr, 6800, f8500000), \ | |
8868 | X(_ldrb, 7800, f8100000), \ | |
8869 | X(_ldrh, 8800, f8300000), \ | |
8870 | X(_ldrsb, 5600, f9100000), \ | |
8871 | X(_ldrsh, 5e00, f9300000), \ | |
8872 | X(_ldr_pc,4800, f85f0000), \ | |
8873 | X(_ldr_pc2,4800, f85f0000), \ | |
8874 | X(_ldr_sp,9800, f85d0000), \ | |
8875 | X(_lsl, 0000, fa00f000), \ | |
8876 | X(_lsls, 0000, fa10f000), \ | |
8877 | X(_lsr, 0800, fa20f000), \ | |
8878 | X(_lsrs, 0800, fa30f000), \ | |
8879 | X(_mov, 2000, ea4f0000), \ | |
8880 | X(_movs, 2000, ea5f0000), \ | |
8881 | X(_mul, 4340, fb00f000), \ | |
8882 | X(_muls, 4340, ffffffff), /* no 32b muls */ \ | |
8883 | X(_mvn, 43c0, ea6f0000), \ | |
8884 | X(_mvns, 43c0, ea7f0000), \ | |
8885 | X(_neg, 4240, f1c00000), /* rsb #0 */ \ | |
8886 | X(_negs, 4240, f1d00000), /* rsbs #0 */ \ | |
8887 | X(_orr, 4300, ea400000), \ | |
8888 | X(_orrs, 4300, ea500000), \ | |
8889 | X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \ | |
8890 | X(_push, b400, e92d0000), /* stmdb sp!,... */ \ | |
8891 | X(_rev, ba00, fa90f080), \ | |
8892 | X(_rev16, ba40, fa90f090), \ | |
8893 | X(_revsh, bac0, fa90f0b0), \ | |
8894 | X(_ror, 41c0, fa60f000), \ | |
8895 | X(_rors, 41c0, fa70f000), \ | |
8896 | X(_sbc, 4180, eb600000), \ | |
8897 | X(_sbcs, 4180, eb700000), \ | |
8898 | X(_stmia, c000, e8800000), \ | |
8899 | X(_str, 6000, f8400000), \ | |
8900 | X(_strb, 7000, f8000000), \ | |
8901 | X(_strh, 8000, f8200000), \ | |
8902 | X(_str_sp,9000, f84d0000), \ | |
8903 | X(_sub, 1e00, eba00000), \ | |
8904 | X(_subs, 1e00, ebb00000), \ | |
8905 | X(_subi, 8000, f1a00000), \ | |
8906 | X(_subis, 8000, f1b00000), \ | |
8907 | X(_sxtb, b240, fa4ff080), \ | |
8908 | X(_sxth, b200, fa0ff080), \ | |
8909 | X(_tst, 4200, ea100f00), \ | |
8910 | X(_uxtb, b2c0, fa5ff080), \ | |
8911 | X(_uxth, b280, fa1ff080), \ | |
8912 | X(_nop, bf00, f3af8000), \ | |
8913 | X(_yield, bf10, f3af8001), \ | |
8914 | X(_wfe, bf20, f3af8002), \ | |
8915 | X(_wfi, bf30, f3af8003), \ | |
8916 | X(_sev, bf40, f3af8004), | |
c19d1205 ZW |
8917 | |
8918 | /* To catch errors in encoding functions, the codes are all offset by | |
8919 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
8920 | as 16-bit instructions. */ | |
21d799b5 | 8921 | #define X(a,b,c) T_MNEM##a |
c19d1205 ZW |
8922 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; |
8923 | #undef X | |
8924 | ||
8925 | #define X(a,b,c) 0x##b | |
8926 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
8927 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
8928 | #undef X | |
8929 | ||
8930 | #define X(a,b,c) 0x##c | |
8931 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
c921be7d NC |
8932 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) |
8933 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
c19d1205 ZW |
8934 | #undef X |
8935 | #undef T16_32_TAB | |
8936 | ||
8937 | /* Thumb instruction encoders, in alphabetical order. */ | |
8938 | ||
92e90b6e | 8939 | /* ADDW or SUBW. */ |
c921be7d | 8940 | |
92e90b6e PB |
8941 | static void |
8942 | do_t_add_sub_w (void) | |
8943 | { | |
8944 | int Rd, Rn; | |
8945 | ||
8946 | Rd = inst.operands[0].reg; | |
8947 | Rn = inst.operands[1].reg; | |
8948 | ||
539d4391 NC |
8949 | /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this |
8950 | is the SP-{plus,minus}-immediate form of the instruction. */ | |
8951 | if (Rn == REG_SP) | |
8952 | constraint (Rd == REG_PC, BAD_PC); | |
8953 | else | |
8954 | reject_bad_reg (Rd); | |
fdfde340 | 8955 | |
92e90b6e PB |
8956 | inst.instruction |= (Rn << 16) | (Rd << 8); |
8957 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
8958 | } | |
8959 | ||
c19d1205 ZW |
8960 | /* Parse an add or subtract instruction. We get here with inst.instruction |
8961 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
8962 | ||
8963 | static void | |
8964 | do_t_add_sub (void) | |
8965 | { | |
8966 | int Rd, Rs, Rn; | |
8967 | ||
8968 | Rd = inst.operands[0].reg; | |
8969 | Rs = (inst.operands[1].present | |
8970 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
8971 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
8972 | ||
e07e6e58 NC |
8973 | if (Rd == REG_PC) |
8974 | set_it_insn_type_last (); | |
8975 | ||
c19d1205 ZW |
8976 | if (unified_syntax) |
8977 | { | |
0110f2b8 PB |
8978 | bfd_boolean flags; |
8979 | bfd_boolean narrow; | |
8980 | int opcode; | |
8981 | ||
8982 | flags = (inst.instruction == T_MNEM_adds | |
8983 | || inst.instruction == T_MNEM_subs); | |
8984 | if (flags) | |
e07e6e58 | 8985 | narrow = !in_it_block (); |
0110f2b8 | 8986 | else |
e07e6e58 | 8987 | narrow = in_it_block (); |
c19d1205 | 8988 | if (!inst.operands[2].isreg) |
b99bd4ef | 8989 | { |
16805f35 PB |
8990 | int add; |
8991 | ||
fdfde340 JM |
8992 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); |
8993 | ||
16805f35 PB |
8994 | add = (inst.instruction == T_MNEM_add |
8995 | || inst.instruction == T_MNEM_adds); | |
0110f2b8 PB |
8996 | opcode = 0; |
8997 | if (inst.size_req != 4) | |
8998 | { | |
0110f2b8 PB |
8999 | /* Attempt to use a narrow opcode, with relaxation if |
9000 | appropriate. */ | |
9001 | if (Rd == REG_SP && Rs == REG_SP && !flags) | |
9002 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
9003 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
9004 | opcode = T_MNEM_add_sp; | |
9005 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
9006 | opcode = T_MNEM_add_pc; | |
9007 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
9008 | { | |
9009 | if (flags) | |
9010 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
9011 | else | |
9012 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
9013 | } | |
9014 | if (opcode) | |
9015 | { | |
9016 | inst.instruction = THUMB_OP16(opcode); | |
9017 | inst.instruction |= (Rd << 4) | Rs; | |
9018 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
9019 | if (inst.size_req != 2) | |
9020 | inst.relax = opcode; | |
9021 | } | |
9022 | else | |
9023 | constraint (inst.size_req == 2, BAD_HIREG); | |
9024 | } | |
9025 | if (inst.size_req == 4 | |
9026 | || (inst.size_req != 2 && !opcode)) | |
9027 | { | |
efd81785 PB |
9028 | if (Rd == REG_PC) |
9029 | { | |
fdfde340 | 9030 | constraint (add, BAD_PC); |
efd81785 PB |
9031 | constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, |
9032 | _("only SUBS PC, LR, #const allowed")); | |
9033 | constraint (inst.reloc.exp.X_op != O_constant, | |
9034 | _("expression too complex")); | |
9035 | constraint (inst.reloc.exp.X_add_number < 0 | |
9036 | || inst.reloc.exp.X_add_number > 0xff, | |
9037 | _("immediate value out of range")); | |
9038 | inst.instruction = T2_SUBS_PC_LR | |
9039 | | inst.reloc.exp.X_add_number; | |
9040 | inst.reloc.type = BFD_RELOC_UNUSED; | |
9041 | return; | |
9042 | } | |
9043 | else if (Rs == REG_PC) | |
16805f35 PB |
9044 | { |
9045 | /* Always use addw/subw. */ | |
9046 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; | |
9047 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
9048 | } | |
9049 | else | |
9050 | { | |
9051 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9052 | inst.instruction = (inst.instruction & 0xe1ffffff) | |
9053 | | 0x10000000; | |
9054 | if (flags) | |
9055 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9056 | else | |
9057 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; | |
9058 | } | |
dc4503c6 PB |
9059 | inst.instruction |= Rd << 8; |
9060 | inst.instruction |= Rs << 16; | |
0110f2b8 | 9061 | } |
b99bd4ef | 9062 | } |
c19d1205 ZW |
9063 | else |
9064 | { | |
9065 | Rn = inst.operands[2].reg; | |
9066 | /* See if we can do this with a 16-bit instruction. */ | |
9067 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
9068 | { | |
e27ec89e PB |
9069 | if (Rd > 7 || Rs > 7 || Rn > 7) |
9070 | narrow = FALSE; | |
9071 | ||
9072 | if (narrow) | |
c19d1205 | 9073 | { |
e27ec89e PB |
9074 | inst.instruction = ((inst.instruction == T_MNEM_adds |
9075 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
9076 | ? T_OPCODE_ADD_R3 |
9077 | : T_OPCODE_SUB_R3); | |
9078 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
9079 | return; | |
9080 | } | |
b99bd4ef | 9081 | |
7e806470 | 9082 | if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) |
c19d1205 | 9083 | { |
7e806470 PB |
9084 | /* Thumb-1 cores (except v6-M) require at least one high |
9085 | register in a narrow non flag setting add. */ | |
9086 | if (Rd > 7 || Rn > 7 | |
9087 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) | |
9088 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) | |
c19d1205 | 9089 | { |
7e806470 PB |
9090 | if (Rd == Rn) |
9091 | { | |
9092 | Rn = Rs; | |
9093 | Rs = Rd; | |
9094 | } | |
c19d1205 ZW |
9095 | inst.instruction = T_OPCODE_ADD_HI; |
9096 | inst.instruction |= (Rd & 8) << 4; | |
9097 | inst.instruction |= (Rd & 7); | |
9098 | inst.instruction |= Rn << 3; | |
9099 | return; | |
9100 | } | |
c19d1205 ZW |
9101 | } |
9102 | } | |
c921be7d | 9103 | |
fdfde340 JM |
9104 | constraint (Rd == REG_PC, BAD_PC); |
9105 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
9106 | constraint (Rs == REG_PC, BAD_PC); | |
9107 | reject_bad_reg (Rn); | |
9108 | ||
c19d1205 ZW |
9109 | /* If we get here, it can't be done in 16 bits. */ |
9110 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
9111 | _("shift must be constant")); | |
9112 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9113 | inst.instruction |= Rd << 8; | |
9114 | inst.instruction |= Rs << 16; | |
9115 | encode_thumb32_shifted_operand (2); | |
9116 | } | |
9117 | } | |
9118 | else | |
9119 | { | |
9120 | constraint (inst.instruction == T_MNEM_adds | |
9121 | || inst.instruction == T_MNEM_subs, | |
9122 | BAD_THUMB32); | |
b99bd4ef | 9123 | |
c19d1205 | 9124 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 9125 | { |
c19d1205 ZW |
9126 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
9127 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
9128 | BAD_HIREG); | |
9129 | ||
9130 | inst.instruction = (inst.instruction == T_MNEM_add | |
9131 | ? 0x0000 : 0x8000); | |
9132 | inst.instruction |= (Rd << 4) | Rs; | |
9133 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
9134 | return; |
9135 | } | |
9136 | ||
c19d1205 ZW |
9137 | Rn = inst.operands[2].reg; |
9138 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 9139 | |
c19d1205 ZW |
9140 | /* We now have Rd, Rs, and Rn set to registers. */ |
9141 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 9142 | { |
c19d1205 ZW |
9143 | /* Can't do this for SUB. */ |
9144 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
9145 | inst.instruction = T_OPCODE_ADD_HI; | |
9146 | inst.instruction |= (Rd & 8) << 4; | |
9147 | inst.instruction |= (Rd & 7); | |
9148 | if (Rs == Rd) | |
9149 | inst.instruction |= Rn << 3; | |
9150 | else if (Rn == Rd) | |
9151 | inst.instruction |= Rs << 3; | |
9152 | else | |
9153 | constraint (1, _("dest must overlap one source register")); | |
9154 | } | |
9155 | else | |
9156 | { | |
9157 | inst.instruction = (inst.instruction == T_MNEM_add | |
9158 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
9159 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 9160 | } |
b99bd4ef | 9161 | } |
b99bd4ef NC |
9162 | } |
9163 | ||
c19d1205 ZW |
9164 | static void |
9165 | do_t_adr (void) | |
9166 | { | |
fdfde340 JM |
9167 | unsigned Rd; |
9168 | ||
9169 | Rd = inst.operands[0].reg; | |
9170 | reject_bad_reg (Rd); | |
9171 | ||
9172 | if (unified_syntax && inst.size_req == 0 && Rd <= 7) | |
0110f2b8 PB |
9173 | { |
9174 | /* Defer to section relaxation. */ | |
9175 | inst.relax = inst.instruction; | |
9176 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 | 9177 | inst.instruction |= Rd << 4; |
0110f2b8 PB |
9178 | } |
9179 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 9180 | { |
0110f2b8 | 9181 | /* Generate a 32-bit opcode. */ |
e9f89963 | 9182 | inst.instruction = THUMB_OP32 (inst.instruction); |
fdfde340 | 9183 | inst.instruction |= Rd << 8; |
e9f89963 PB |
9184 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; |
9185 | inst.reloc.pc_rel = 1; | |
9186 | } | |
9187 | else | |
9188 | { | |
0110f2b8 | 9189 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
9190 | inst.instruction = THUMB_OP16 (inst.instruction); |
9191 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
9192 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
9193 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 9194 | |
fdfde340 | 9195 | inst.instruction |= Rd << 4; |
e9f89963 | 9196 | } |
c19d1205 | 9197 | } |
b99bd4ef | 9198 | |
c19d1205 ZW |
9199 | /* Arithmetic instructions for which there is just one 16-bit |
9200 | instruction encoding, and it allows only two low registers. | |
9201 | For maximal compatibility with ARM syntax, we allow three register | |
9202 | operands even when Thumb-32 instructions are not available, as long | |
9203 | as the first two are identical. For instance, both "sbc r0,r1" and | |
9204 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 9205 | static void |
c19d1205 | 9206 | do_t_arit3 (void) |
b99bd4ef | 9207 | { |
c19d1205 | 9208 | int Rd, Rs, Rn; |
b99bd4ef | 9209 | |
c19d1205 ZW |
9210 | Rd = inst.operands[0].reg; |
9211 | Rs = (inst.operands[1].present | |
9212 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9213 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9214 | Rn = inst.operands[2].reg; | |
b99bd4ef | 9215 | |
fdfde340 JM |
9216 | reject_bad_reg (Rd); |
9217 | reject_bad_reg (Rs); | |
9218 | if (inst.operands[2].isreg) | |
9219 | reject_bad_reg (Rn); | |
9220 | ||
c19d1205 | 9221 | if (unified_syntax) |
b99bd4ef | 9222 | { |
c19d1205 ZW |
9223 | if (!inst.operands[2].isreg) |
9224 | { | |
9225 | /* For an immediate, we always generate a 32-bit opcode; | |
9226 | section relaxation will shrink it later if possible. */ | |
9227 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9228 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9229 | inst.instruction |= Rd << 8; | |
9230 | inst.instruction |= Rs << 16; | |
9231 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9232 | } | |
9233 | else | |
9234 | { | |
e27ec89e PB |
9235 | bfd_boolean narrow; |
9236 | ||
c19d1205 | 9237 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 9238 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 9239 | narrow = !in_it_block (); |
e27ec89e | 9240 | else |
e07e6e58 | 9241 | narrow = in_it_block (); |
e27ec89e PB |
9242 | |
9243 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
9244 | narrow = FALSE; | |
9245 | if (inst.operands[2].shifted) | |
9246 | narrow = FALSE; | |
9247 | if (inst.size_req == 4) | |
9248 | narrow = FALSE; | |
9249 | ||
9250 | if (narrow | |
c19d1205 ZW |
9251 | && Rd == Rs) |
9252 | { | |
9253 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9254 | inst.instruction |= Rd; | |
9255 | inst.instruction |= Rn << 3; | |
9256 | return; | |
9257 | } | |
b99bd4ef | 9258 | |
c19d1205 ZW |
9259 | /* If we get here, it can't be done in 16 bits. */ |
9260 | constraint (inst.operands[2].shifted | |
9261 | && inst.operands[2].immisreg, | |
9262 | _("shift must be constant")); | |
9263 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9264 | inst.instruction |= Rd << 8; | |
9265 | inst.instruction |= Rs << 16; | |
9266 | encode_thumb32_shifted_operand (2); | |
9267 | } | |
a737bd4d | 9268 | } |
c19d1205 | 9269 | else |
b99bd4ef | 9270 | { |
c19d1205 ZW |
9271 | /* On its face this is a lie - the instruction does set the |
9272 | flags. However, the only supported mnemonic in this mode | |
9273 | says it doesn't. */ | |
9274 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 9275 | |
c19d1205 ZW |
9276 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
9277 | _("unshifted register required")); | |
9278 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
9279 | constraint (Rd != Rs, | |
9280 | _("dest and source1 must be the same register")); | |
a737bd4d | 9281 | |
c19d1205 ZW |
9282 | inst.instruction = THUMB_OP16 (inst.instruction); |
9283 | inst.instruction |= Rd; | |
9284 | inst.instruction |= Rn << 3; | |
b99bd4ef | 9285 | } |
a737bd4d | 9286 | } |
b99bd4ef | 9287 | |
c19d1205 ZW |
9288 | /* Similarly, but for instructions where the arithmetic operation is |
9289 | commutative, so we can allow either of them to be different from | |
9290 | the destination operand in a 16-bit instruction. For instance, all | |
9291 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
9292 | accepted. */ | |
9293 | static void | |
9294 | do_t_arit3c (void) | |
a737bd4d | 9295 | { |
c19d1205 | 9296 | int Rd, Rs, Rn; |
b99bd4ef | 9297 | |
c19d1205 ZW |
9298 | Rd = inst.operands[0].reg; |
9299 | Rs = (inst.operands[1].present | |
9300 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9301 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9302 | Rn = inst.operands[2].reg; | |
c921be7d | 9303 | |
fdfde340 JM |
9304 | reject_bad_reg (Rd); |
9305 | reject_bad_reg (Rs); | |
9306 | if (inst.operands[2].isreg) | |
9307 | reject_bad_reg (Rn); | |
a737bd4d | 9308 | |
c19d1205 | 9309 | if (unified_syntax) |
a737bd4d | 9310 | { |
c19d1205 | 9311 | if (!inst.operands[2].isreg) |
b99bd4ef | 9312 | { |
c19d1205 ZW |
9313 | /* For an immediate, we always generate a 32-bit opcode; |
9314 | section relaxation will shrink it later if possible. */ | |
9315 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9316 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9317 | inst.instruction |= Rd << 8; | |
9318 | inst.instruction |= Rs << 16; | |
9319 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 9320 | } |
c19d1205 | 9321 | else |
a737bd4d | 9322 | { |
e27ec89e PB |
9323 | bfd_boolean narrow; |
9324 | ||
c19d1205 | 9325 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 9326 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 9327 | narrow = !in_it_block (); |
e27ec89e | 9328 | else |
e07e6e58 | 9329 | narrow = in_it_block (); |
e27ec89e PB |
9330 | |
9331 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
9332 | narrow = FALSE; | |
9333 | if (inst.operands[2].shifted) | |
9334 | narrow = FALSE; | |
9335 | if (inst.size_req == 4) | |
9336 | narrow = FALSE; | |
9337 | ||
9338 | if (narrow) | |
a737bd4d | 9339 | { |
c19d1205 | 9340 | if (Rd == Rs) |
a737bd4d | 9341 | { |
c19d1205 ZW |
9342 | inst.instruction = THUMB_OP16 (inst.instruction); |
9343 | inst.instruction |= Rd; | |
9344 | inst.instruction |= Rn << 3; | |
9345 | return; | |
a737bd4d | 9346 | } |
c19d1205 | 9347 | if (Rd == Rn) |
a737bd4d | 9348 | { |
c19d1205 ZW |
9349 | inst.instruction = THUMB_OP16 (inst.instruction); |
9350 | inst.instruction |= Rd; | |
9351 | inst.instruction |= Rs << 3; | |
9352 | return; | |
a737bd4d NC |
9353 | } |
9354 | } | |
c19d1205 ZW |
9355 | |
9356 | /* If we get here, it can't be done in 16 bits. */ | |
9357 | constraint (inst.operands[2].shifted | |
9358 | && inst.operands[2].immisreg, | |
9359 | _("shift must be constant")); | |
9360 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9361 | inst.instruction |= Rd << 8; | |
9362 | inst.instruction |= Rs << 16; | |
9363 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 9364 | } |
b99bd4ef | 9365 | } |
c19d1205 ZW |
9366 | else |
9367 | { | |
9368 | /* On its face this is a lie - the instruction does set the | |
9369 | flags. However, the only supported mnemonic in this mode | |
9370 | says it doesn't. */ | |
9371 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 9372 | |
c19d1205 ZW |
9373 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
9374 | _("unshifted register required")); | |
9375 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
9376 | ||
9377 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9378 | inst.instruction |= Rd; | |
9379 | ||
9380 | if (Rd == Rs) | |
9381 | inst.instruction |= Rn << 3; | |
9382 | else if (Rd == Rn) | |
9383 | inst.instruction |= Rs << 3; | |
9384 | else | |
9385 | constraint (1, _("dest must overlap one source register")); | |
9386 | } | |
a737bd4d NC |
9387 | } |
9388 | ||
62b3e311 PB |
9389 | static void |
9390 | do_t_barrier (void) | |
9391 | { | |
9392 | if (inst.operands[0].present) | |
9393 | { | |
9394 | constraint ((inst.instruction & 0xf0) != 0x40 | |
9395 | && inst.operands[0].imm != 0xf, | |
bd3ba5d1 | 9396 | _("bad barrier type")); |
62b3e311 PB |
9397 | inst.instruction |= inst.operands[0].imm; |
9398 | } | |
9399 | else | |
9400 | inst.instruction |= 0xf; | |
9401 | } | |
9402 | ||
c19d1205 ZW |
9403 | static void |
9404 | do_t_bfc (void) | |
a737bd4d | 9405 | { |
fdfde340 | 9406 | unsigned Rd; |
c19d1205 ZW |
9407 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
9408 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9409 | /* The instruction encoding stores the LSB and MSB, | |
9410 | not the LSB and width. */ | |
fdfde340 JM |
9411 | Rd = inst.operands[0].reg; |
9412 | reject_bad_reg (Rd); | |
9413 | inst.instruction |= Rd << 8; | |
c19d1205 ZW |
9414 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; |
9415 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
9416 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
9417 | } |
9418 | ||
c19d1205 ZW |
9419 | static void |
9420 | do_t_bfi (void) | |
b99bd4ef | 9421 | { |
fdfde340 | 9422 | int Rd, Rn; |
c19d1205 | 9423 | unsigned int msb; |
b99bd4ef | 9424 | |
fdfde340 JM |
9425 | Rd = inst.operands[0].reg; |
9426 | reject_bad_reg (Rd); | |
9427 | ||
c19d1205 ZW |
9428 | /* #0 in second position is alternative syntax for bfc, which is |
9429 | the same instruction but with REG_PC in the Rm field. */ | |
9430 | if (!inst.operands[1].isreg) | |
fdfde340 JM |
9431 | Rn = REG_PC; |
9432 | else | |
9433 | { | |
9434 | Rn = inst.operands[1].reg; | |
9435 | reject_bad_reg (Rn); | |
9436 | } | |
b99bd4ef | 9437 | |
c19d1205 ZW |
9438 | msb = inst.operands[2].imm + inst.operands[3].imm; |
9439 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9440 | /* The instruction encoding stores the LSB and MSB, | |
9441 | not the LSB and width. */ | |
fdfde340 JM |
9442 | inst.instruction |= Rd << 8; |
9443 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
9444 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
9445 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
9446 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
9447 | } |
9448 | ||
c19d1205 ZW |
9449 | static void |
9450 | do_t_bfx (void) | |
b99bd4ef | 9451 | { |
fdfde340 JM |
9452 | unsigned Rd, Rn; |
9453 | ||
9454 | Rd = inst.operands[0].reg; | |
9455 | Rn = inst.operands[1].reg; | |
9456 | ||
9457 | reject_bad_reg (Rd); | |
9458 | reject_bad_reg (Rn); | |
9459 | ||
c19d1205 ZW |
9460 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
9461 | _("bit-field extends past end of register")); | |
fdfde340 JM |
9462 | inst.instruction |= Rd << 8; |
9463 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
9464 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
9465 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
9466 | inst.instruction |= inst.operands[3].imm - 1; | |
9467 | } | |
b99bd4ef | 9468 | |
c19d1205 ZW |
9469 | /* ARM V5 Thumb BLX (argument parse) |
9470 | BLX <target_addr> which is BLX(1) | |
9471 | BLX <Rm> which is BLX(2) | |
9472 | Unfortunately, there are two different opcodes for this mnemonic. | |
9473 | So, the insns[].value is not used, and the code here zaps values | |
9474 | into inst.instruction. | |
b99bd4ef | 9475 | |
c19d1205 ZW |
9476 | ??? How to take advantage of the additional two bits of displacement |
9477 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 9478 | |
c19d1205 ZW |
9479 | static void |
9480 | do_t_blx (void) | |
9481 | { | |
e07e6e58 NC |
9482 | set_it_insn_type_last (); |
9483 | ||
c19d1205 | 9484 | if (inst.operands[0].isreg) |
fdfde340 JM |
9485 | { |
9486 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); | |
9487 | /* We have a register, so this is BLX(2). */ | |
9488 | inst.instruction |= inst.operands[0].reg << 3; | |
9489 | } | |
b99bd4ef NC |
9490 | else |
9491 | { | |
c19d1205 | 9492 | /* No register. This must be BLX(1). */ |
2fc8bdac | 9493 | inst.instruction = 0xf000e800; |
00adf2d4 | 9494 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; |
c19d1205 | 9495 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
9496 | } |
9497 | } | |
9498 | ||
c19d1205 ZW |
9499 | static void |
9500 | do_t_branch (void) | |
b99bd4ef | 9501 | { |
0110f2b8 | 9502 | int opcode; |
dfa9f0d5 PB |
9503 | int cond; |
9504 | ||
e07e6e58 NC |
9505 | cond = inst.cond; |
9506 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); | |
9507 | ||
9508 | if (in_it_block ()) | |
dfa9f0d5 PB |
9509 | { |
9510 | /* Conditional branches inside IT blocks are encoded as unconditional | |
9511 | branches. */ | |
9512 | cond = COND_ALWAYS; | |
dfa9f0d5 PB |
9513 | } |
9514 | else | |
9515 | cond = inst.cond; | |
9516 | ||
9517 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
9518 | opcode = T_MNEM_bcond; |
9519 | else | |
9520 | opcode = inst.instruction; | |
9521 | ||
9522 | if (unified_syntax && inst.size_req == 4) | |
c19d1205 | 9523 | { |
0110f2b8 | 9524 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 9525 | if (cond == COND_ALWAYS) |
0110f2b8 | 9526 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
9527 | else |
9528 | { | |
9c2799c2 | 9529 | gas_assert (cond != 0xF); |
dfa9f0d5 | 9530 | inst.instruction |= cond << 22; |
c19d1205 ZW |
9531 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20; |
9532 | } | |
9533 | } | |
b99bd4ef NC |
9534 | else |
9535 | { | |
0110f2b8 | 9536 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 9537 | if (cond == COND_ALWAYS) |
c19d1205 ZW |
9538 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; |
9539 | else | |
b99bd4ef | 9540 | { |
dfa9f0d5 | 9541 | inst.instruction |= cond << 8; |
c19d1205 | 9542 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 9543 | } |
0110f2b8 PB |
9544 | /* Allow section relaxation. */ |
9545 | if (unified_syntax && inst.size_req != 2) | |
9546 | inst.relax = opcode; | |
b99bd4ef | 9547 | } |
c19d1205 ZW |
9548 | |
9549 | inst.reloc.pc_rel = 1; | |
b99bd4ef NC |
9550 | } |
9551 | ||
9552 | static void | |
c19d1205 | 9553 | do_t_bkpt (void) |
b99bd4ef | 9554 | { |
dfa9f0d5 PB |
9555 | constraint (inst.cond != COND_ALWAYS, |
9556 | _("instruction is always unconditional")); | |
c19d1205 | 9557 | if (inst.operands[0].present) |
b99bd4ef | 9558 | { |
c19d1205 ZW |
9559 | constraint (inst.operands[0].imm > 255, |
9560 | _("immediate value out of range")); | |
9561 | inst.instruction |= inst.operands[0].imm; | |
e07e6e58 | 9562 | set_it_insn_type (NEUTRAL_IT_INSN); |
b99bd4ef | 9563 | } |
b99bd4ef NC |
9564 | } |
9565 | ||
9566 | static void | |
c19d1205 | 9567 | do_t_branch23 (void) |
b99bd4ef | 9568 | { |
e07e6e58 | 9569 | set_it_insn_type_last (); |
c19d1205 | 9570 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; |
90e4755a RE |
9571 | inst.reloc.pc_rel = 1; |
9572 | ||
4343666d | 9573 | #if defined(OBJ_COFF) |
c19d1205 ZW |
9574 | /* If the destination of the branch is a defined symbol which does not have |
9575 | the THUMB_FUNC attribute, then we must be calling a function which has | |
9576 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
9577 | function and change the branch to refer to that function instead. */ | |
9578 | if ( inst.reloc.exp.X_op == O_symbol | |
9579 | && inst.reloc.exp.X_add_symbol != NULL | |
9580 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
9581 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
9582 | inst.reloc.exp.X_add_symbol = | |
9583 | find_real_start (inst.reloc.exp.X_add_symbol); | |
4343666d | 9584 | #endif |
90e4755a RE |
9585 | } |
9586 | ||
9587 | static void | |
c19d1205 | 9588 | do_t_bx (void) |
90e4755a | 9589 | { |
e07e6e58 | 9590 | set_it_insn_type_last (); |
c19d1205 ZW |
9591 | inst.instruction |= inst.operands[0].reg << 3; |
9592 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
9593 | should cause the alignment to be checked once it is known. This is | |
9594 | because BX PC only works if the instruction is word aligned. */ | |
9595 | } | |
90e4755a | 9596 | |
c19d1205 ZW |
9597 | static void |
9598 | do_t_bxj (void) | |
9599 | { | |
fdfde340 | 9600 | int Rm; |
90e4755a | 9601 | |
e07e6e58 | 9602 | set_it_insn_type_last (); |
fdfde340 JM |
9603 | Rm = inst.operands[0].reg; |
9604 | reject_bad_reg (Rm); | |
9605 | inst.instruction |= Rm << 16; | |
90e4755a RE |
9606 | } |
9607 | ||
9608 | static void | |
c19d1205 | 9609 | do_t_clz (void) |
90e4755a | 9610 | { |
fdfde340 JM |
9611 | unsigned Rd; |
9612 | unsigned Rm; | |
9613 | ||
9614 | Rd = inst.operands[0].reg; | |
9615 | Rm = inst.operands[1].reg; | |
9616 | ||
9617 | reject_bad_reg (Rd); | |
9618 | reject_bad_reg (Rm); | |
9619 | ||
9620 | inst.instruction |= Rd << 8; | |
9621 | inst.instruction |= Rm << 16; | |
9622 | inst.instruction |= Rm; | |
c19d1205 | 9623 | } |
90e4755a | 9624 | |
dfa9f0d5 PB |
9625 | static void |
9626 | do_t_cps (void) | |
9627 | { | |
e07e6e58 | 9628 | set_it_insn_type (OUTSIDE_IT_INSN); |
dfa9f0d5 PB |
9629 | inst.instruction |= inst.operands[0].imm; |
9630 | } | |
9631 | ||
c19d1205 ZW |
9632 | static void |
9633 | do_t_cpsi (void) | |
9634 | { | |
e07e6e58 | 9635 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 | 9636 | if (unified_syntax |
62b3e311 PB |
9637 | && (inst.operands[1].present || inst.size_req == 4) |
9638 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 9639 | { |
c19d1205 ZW |
9640 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
9641 | inst.instruction = 0xf3af8000; | |
9642 | inst.instruction |= imod << 9; | |
9643 | inst.instruction |= inst.operands[0].imm << 5; | |
9644 | if (inst.operands[1].present) | |
9645 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 9646 | } |
c19d1205 | 9647 | else |
90e4755a | 9648 | { |
62b3e311 PB |
9649 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
9650 | && (inst.operands[0].imm & 4), | |
9651 | _("selected processor does not support 'A' form " | |
9652 | "of this instruction")); | |
9653 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
9654 | _("Thumb does not support the 2-argument " |
9655 | "form of this instruction")); | |
9656 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 9657 | } |
90e4755a RE |
9658 | } |
9659 | ||
c19d1205 ZW |
9660 | /* THUMB CPY instruction (argument parse). */ |
9661 | ||
90e4755a | 9662 | static void |
c19d1205 | 9663 | do_t_cpy (void) |
90e4755a | 9664 | { |
c19d1205 | 9665 | if (inst.size_req == 4) |
90e4755a | 9666 | { |
c19d1205 ZW |
9667 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
9668 | inst.instruction |= inst.operands[0].reg << 8; | |
9669 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 9670 | } |
c19d1205 | 9671 | else |
90e4755a | 9672 | { |
c19d1205 ZW |
9673 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
9674 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
9675 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 9676 | } |
90e4755a RE |
9677 | } |
9678 | ||
90e4755a | 9679 | static void |
25fe350b | 9680 | do_t_cbz (void) |
90e4755a | 9681 | { |
e07e6e58 | 9682 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
9683 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
9684 | inst.instruction |= inst.operands[0].reg; | |
9685 | inst.reloc.pc_rel = 1; | |
9686 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
9687 | } | |
90e4755a | 9688 | |
62b3e311 PB |
9689 | static void |
9690 | do_t_dbg (void) | |
9691 | { | |
9692 | inst.instruction |= inst.operands[0].imm; | |
9693 | } | |
9694 | ||
9695 | static void | |
9696 | do_t_div (void) | |
9697 | { | |
fdfde340 JM |
9698 | unsigned Rd, Rn, Rm; |
9699 | ||
9700 | Rd = inst.operands[0].reg; | |
9701 | Rn = (inst.operands[1].present | |
9702 | ? inst.operands[1].reg : Rd); | |
9703 | Rm = inst.operands[2].reg; | |
9704 | ||
9705 | reject_bad_reg (Rd); | |
9706 | reject_bad_reg (Rn); | |
9707 | reject_bad_reg (Rm); | |
9708 | ||
9709 | inst.instruction |= Rd << 8; | |
9710 | inst.instruction |= Rn << 16; | |
9711 | inst.instruction |= Rm; | |
62b3e311 PB |
9712 | } |
9713 | ||
c19d1205 ZW |
9714 | static void |
9715 | do_t_hint (void) | |
9716 | { | |
9717 | if (unified_syntax && inst.size_req == 4) | |
9718 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9719 | else | |
9720 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9721 | } | |
90e4755a | 9722 | |
c19d1205 ZW |
9723 | static void |
9724 | do_t_it (void) | |
9725 | { | |
9726 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 9727 | |
e07e6e58 NC |
9728 | set_it_insn_type (IT_INSN); |
9729 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
9730 | now_it.cc = cond; | |
e27ec89e PB |
9731 | |
9732 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 9733 | if ((cond & 0x1) == 0x0) |
90e4755a | 9734 | { |
c19d1205 | 9735 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 9736 | |
c19d1205 ZW |
9737 | if ((mask & 0x7) == 0) |
9738 | /* no conversion needed */; | |
9739 | else if ((mask & 0x3) == 0) | |
e27ec89e PB |
9740 | mask ^= 0x8; |
9741 | else if ((mask & 0x1) == 0) | |
9742 | mask ^= 0xC; | |
c19d1205 | 9743 | else |
e27ec89e | 9744 | mask ^= 0xE; |
90e4755a | 9745 | |
e27ec89e PB |
9746 | inst.instruction &= 0xfff0; |
9747 | inst.instruction |= mask; | |
c19d1205 | 9748 | } |
90e4755a | 9749 | |
c19d1205 ZW |
9750 | inst.instruction |= cond << 4; |
9751 | } | |
90e4755a | 9752 | |
3c707909 PB |
9753 | /* Helper function used for both push/pop and ldm/stm. */ |
9754 | static void | |
9755 | encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) | |
9756 | { | |
9757 | bfd_boolean load; | |
9758 | ||
9759 | load = (inst.instruction & (1 << 20)) != 0; | |
9760 | ||
9761 | if (mask & (1 << 13)) | |
9762 | inst.error = _("SP not allowed in register list"); | |
9763 | if (load) | |
9764 | { | |
e07e6e58 NC |
9765 | if (mask & (1 << 15)) |
9766 | { | |
9767 | if (mask & (1 << 14)) | |
9768 | inst.error = _("LR and PC should not both be in register list"); | |
9769 | else | |
9770 | set_it_insn_type_last (); | |
9771 | } | |
3c707909 PB |
9772 | |
9773 | if ((mask & (1 << base)) != 0 | |
9774 | && writeback) | |
9775 | as_warn (_("base register should not be in register list " | |
9776 | "when written back")); | |
9777 | } | |
9778 | else | |
9779 | { | |
9780 | if (mask & (1 << 15)) | |
9781 | inst.error = _("PC not allowed in register list"); | |
9782 | ||
9783 | if (mask & (1 << base)) | |
9784 | as_warn (_("value stored for r%d is UNPREDICTABLE"), base); | |
9785 | } | |
9786 | ||
9787 | if ((mask & (mask - 1)) == 0) | |
9788 | { | |
9789 | /* Single register transfers implemented as str/ldr. */ | |
9790 | if (writeback) | |
9791 | { | |
9792 | if (inst.instruction & (1 << 23)) | |
9793 | inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ | |
9794 | else | |
9795 | inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ | |
9796 | } | |
9797 | else | |
9798 | { | |
9799 | if (inst.instruction & (1 << 23)) | |
9800 | inst.instruction = 0x00800000; /* ia -> [base] */ | |
9801 | else | |
9802 | inst.instruction = 0x00000c04; /* db -> [base, #-4] */ | |
9803 | } | |
9804 | ||
9805 | inst.instruction |= 0xf8400000; | |
9806 | if (load) | |
9807 | inst.instruction |= 0x00100000; | |
9808 | ||
5f4273c7 | 9809 | mask = ffs (mask) - 1; |
3c707909 PB |
9810 | mask <<= 12; |
9811 | } | |
9812 | else if (writeback) | |
9813 | inst.instruction |= WRITE_BACK; | |
9814 | ||
9815 | inst.instruction |= mask; | |
9816 | inst.instruction |= base << 16; | |
9817 | } | |
9818 | ||
c19d1205 ZW |
9819 | static void |
9820 | do_t_ldmstm (void) | |
9821 | { | |
9822 | /* This really doesn't seem worth it. */ | |
9823 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
9824 | _("expression too complex")); | |
9825 | constraint (inst.operands[1].writeback, | |
9826 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 9827 | |
c19d1205 ZW |
9828 | if (unified_syntax) |
9829 | { | |
3c707909 PB |
9830 | bfd_boolean narrow; |
9831 | unsigned mask; | |
9832 | ||
9833 | narrow = FALSE; | |
c19d1205 ZW |
9834 | /* See if we can use a 16-bit instruction. */ |
9835 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
9836 | && inst.size_req != 4 | |
3c707909 | 9837 | && !(inst.operands[1].imm & ~0xff)) |
90e4755a | 9838 | { |
3c707909 | 9839 | mask = 1 << inst.operands[0].reg; |
90e4755a | 9840 | |
3c707909 PB |
9841 | if (inst.operands[0].reg <= 7 |
9842 | && (inst.instruction == T_MNEM_stmia | |
9843 | ? inst.operands[0].writeback | |
9844 | : (inst.operands[0].writeback | |
9845 | == !(inst.operands[1].imm & mask)))) | |
90e4755a | 9846 | { |
3c707909 PB |
9847 | if (inst.instruction == T_MNEM_stmia |
9848 | && (inst.operands[1].imm & mask) | |
9849 | && (inst.operands[1].imm & (mask - 1))) | |
c19d1205 ZW |
9850 | as_warn (_("value stored for r%d is UNPREDICTABLE"), |
9851 | inst.operands[0].reg); | |
3c707909 PB |
9852 | |
9853 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9854 | inst.instruction |= inst.operands[0].reg << 8; | |
9855 | inst.instruction |= inst.operands[1].imm; | |
9856 | narrow = TRUE; | |
90e4755a | 9857 | } |
3c707909 PB |
9858 | else if (inst.operands[0] .reg == REG_SP |
9859 | && inst.operands[0].writeback) | |
90e4755a | 9860 | { |
3c707909 PB |
9861 | inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia |
9862 | ? T_MNEM_push : T_MNEM_pop); | |
9863 | inst.instruction |= inst.operands[1].imm; | |
9864 | narrow = TRUE; | |
90e4755a | 9865 | } |
3c707909 PB |
9866 | } |
9867 | ||
9868 | if (!narrow) | |
9869 | { | |
c19d1205 ZW |
9870 | if (inst.instruction < 0xffff) |
9871 | inst.instruction = THUMB_OP32 (inst.instruction); | |
3c707909 | 9872 | |
5f4273c7 NC |
9873 | encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm, |
9874 | inst.operands[0].writeback); | |
90e4755a RE |
9875 | } |
9876 | } | |
c19d1205 | 9877 | else |
90e4755a | 9878 | { |
c19d1205 ZW |
9879 | constraint (inst.operands[0].reg > 7 |
9880 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
1198ca51 PB |
9881 | constraint (inst.instruction != T_MNEM_ldmia |
9882 | && inst.instruction != T_MNEM_stmia, | |
9883 | _("Thumb-2 instruction only valid in unified syntax")); | |
c19d1205 | 9884 | if (inst.instruction == T_MNEM_stmia) |
f03698e6 | 9885 | { |
c19d1205 ZW |
9886 | if (!inst.operands[0].writeback) |
9887 | as_warn (_("this instruction will write back the base register")); | |
9888 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
9889 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
9890 | as_warn (_("value stored for r%d is UNPREDICTABLE"), | |
9891 | inst.operands[0].reg); | |
f03698e6 | 9892 | } |
c19d1205 | 9893 | else |
90e4755a | 9894 | { |
c19d1205 ZW |
9895 | if (!inst.operands[0].writeback |
9896 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
9897 | as_warn (_("this instruction will write back the base register")); | |
9898 | else if (inst.operands[0].writeback | |
9899 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
9900 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
9901 | } |
9902 | ||
c19d1205 ZW |
9903 | inst.instruction = THUMB_OP16 (inst.instruction); |
9904 | inst.instruction |= inst.operands[0].reg << 8; | |
9905 | inst.instruction |= inst.operands[1].imm; | |
9906 | } | |
9907 | } | |
e28cd48c | 9908 | |
c19d1205 ZW |
9909 | static void |
9910 | do_t_ldrex (void) | |
9911 | { | |
9912 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
9913 | || inst.operands[1].postind || inst.operands[1].writeback | |
9914 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
9915 | || inst.operands[1].negative, | |
01cfc07f | 9916 | BAD_ADDR_MODE); |
e28cd48c | 9917 | |
5be8be5d DG |
9918 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
9919 | ||
c19d1205 ZW |
9920 | inst.instruction |= inst.operands[0].reg << 12; |
9921 | inst.instruction |= inst.operands[1].reg << 16; | |
9922 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
9923 | } | |
e28cd48c | 9924 | |
c19d1205 ZW |
9925 | static void |
9926 | do_t_ldrexd (void) | |
9927 | { | |
9928 | if (!inst.operands[1].present) | |
1cac9012 | 9929 | { |
c19d1205 ZW |
9930 | constraint (inst.operands[0].reg == REG_LR, |
9931 | _("r14 not allowed as first register " | |
9932 | "when second register is omitted")); | |
9933 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 9934 | } |
c19d1205 ZW |
9935 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
9936 | BAD_OVERLAP); | |
b99bd4ef | 9937 | |
c19d1205 ZW |
9938 | inst.instruction |= inst.operands[0].reg << 12; |
9939 | inst.instruction |= inst.operands[1].reg << 8; | |
9940 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
9941 | } |
9942 | ||
9943 | static void | |
c19d1205 | 9944 | do_t_ldst (void) |
b99bd4ef | 9945 | { |
0110f2b8 PB |
9946 | unsigned long opcode; |
9947 | int Rn; | |
9948 | ||
e07e6e58 NC |
9949 | if (inst.operands[0].isreg |
9950 | && !inst.operands[0].preind | |
9951 | && inst.operands[0].reg == REG_PC) | |
9952 | set_it_insn_type_last (); | |
9953 | ||
0110f2b8 | 9954 | opcode = inst.instruction; |
c19d1205 | 9955 | if (unified_syntax) |
b99bd4ef | 9956 | { |
53365c0d PB |
9957 | if (!inst.operands[1].isreg) |
9958 | { | |
9959 | if (opcode <= 0xffff) | |
9960 | inst.instruction = THUMB_OP32 (opcode); | |
9961 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
9962 | return; | |
9963 | } | |
0110f2b8 PB |
9964 | if (inst.operands[1].isreg |
9965 | && !inst.operands[1].writeback | |
c19d1205 ZW |
9966 | && !inst.operands[1].shifted && !inst.operands[1].postind |
9967 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
9968 | && opcode <= 0xffff |
9969 | && inst.size_req != 4) | |
c19d1205 | 9970 | { |
0110f2b8 PB |
9971 | /* Insn may have a 16-bit form. */ |
9972 | Rn = inst.operands[1].reg; | |
9973 | if (inst.operands[1].immisreg) | |
9974 | { | |
9975 | inst.instruction = THUMB_OP16 (opcode); | |
5f4273c7 | 9976 | /* [Rn, Rik] */ |
0110f2b8 PB |
9977 | if (Rn <= 7 && inst.operands[1].imm <= 7) |
9978 | goto op16; | |
5be8be5d DG |
9979 | else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str) |
9980 | reject_bad_reg (inst.operands[1].imm); | |
0110f2b8 PB |
9981 | } |
9982 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
9983 | && opcode != T_MNEM_ldrsb) | |
9984 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
9985 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
9986 | { | |
9987 | /* [Rn, #const] */ | |
9988 | if (Rn > 7) | |
9989 | { | |
9990 | if (Rn == REG_PC) | |
9991 | { | |
9992 | if (inst.reloc.pc_rel) | |
9993 | opcode = T_MNEM_ldr_pc2; | |
9994 | else | |
9995 | opcode = T_MNEM_ldr_pc; | |
9996 | } | |
9997 | else | |
9998 | { | |
9999 | if (opcode == T_MNEM_ldr) | |
10000 | opcode = T_MNEM_ldr_sp; | |
10001 | else | |
10002 | opcode = T_MNEM_str_sp; | |
10003 | } | |
10004 | inst.instruction = inst.operands[0].reg << 8; | |
10005 | } | |
10006 | else | |
10007 | { | |
10008 | inst.instruction = inst.operands[0].reg; | |
10009 | inst.instruction |= inst.operands[1].reg << 3; | |
10010 | } | |
10011 | inst.instruction |= THUMB_OP16 (opcode); | |
10012 | if (inst.size_req == 2) | |
10013 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10014 | else | |
10015 | inst.relax = opcode; | |
10016 | return; | |
10017 | } | |
c19d1205 | 10018 | } |
0110f2b8 | 10019 | /* Definitely a 32-bit variant. */ |
5be8be5d DG |
10020 | |
10021 | /* Do some validations regarding addressing modes. */ | |
10022 | if (inst.operands[1].immisreg && opcode != T_MNEM_ldr | |
10023 | && opcode != T_MNEM_str) | |
10024 | reject_bad_reg (inst.operands[1].imm); | |
10025 | ||
0110f2b8 | 10026 | inst.instruction = THUMB_OP32 (opcode); |
c19d1205 ZW |
10027 | inst.instruction |= inst.operands[0].reg << 12; |
10028 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
b99bd4ef NC |
10029 | return; |
10030 | } | |
10031 | ||
c19d1205 ZW |
10032 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
10033 | ||
10034 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 10035 | { |
c19d1205 ZW |
10036 | /* Only [Rn,Rm] is acceptable. */ |
10037 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
10038 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
10039 | || inst.operands[1].postind || inst.operands[1].shifted | |
10040 | || inst.operands[1].negative, | |
10041 | _("Thumb does not support this addressing mode")); | |
10042 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10043 | goto op16; | |
b99bd4ef | 10044 | } |
5f4273c7 | 10045 | |
c19d1205 ZW |
10046 | inst.instruction = THUMB_OP16 (inst.instruction); |
10047 | if (!inst.operands[1].isreg) | |
10048 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
10049 | return; | |
b99bd4ef | 10050 | |
c19d1205 ZW |
10051 | constraint (!inst.operands[1].preind |
10052 | || inst.operands[1].shifted | |
10053 | || inst.operands[1].writeback, | |
10054 | _("Thumb does not support this addressing mode")); | |
10055 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 10056 | { |
c19d1205 ZW |
10057 | constraint (inst.instruction & 0x0600, |
10058 | _("byte or halfword not valid for base register")); | |
10059 | constraint (inst.operands[1].reg == REG_PC | |
10060 | && !(inst.instruction & THUMB_LOAD_BIT), | |
10061 | _("r15 based store not allowed")); | |
10062 | constraint (inst.operands[1].immisreg, | |
10063 | _("invalid base register for register offset")); | |
b99bd4ef | 10064 | |
c19d1205 ZW |
10065 | if (inst.operands[1].reg == REG_PC) |
10066 | inst.instruction = T_OPCODE_LDR_PC; | |
10067 | else if (inst.instruction & THUMB_LOAD_BIT) | |
10068 | inst.instruction = T_OPCODE_LDR_SP; | |
10069 | else | |
10070 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 10071 | |
c19d1205 ZW |
10072 | inst.instruction |= inst.operands[0].reg << 8; |
10073 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10074 | return; | |
10075 | } | |
90e4755a | 10076 | |
c19d1205 ZW |
10077 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
10078 | if (!inst.operands[1].immisreg) | |
10079 | { | |
10080 | /* Immediate offset. */ | |
10081 | inst.instruction |= inst.operands[0].reg; | |
10082 | inst.instruction |= inst.operands[1].reg << 3; | |
10083 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10084 | return; | |
10085 | } | |
90e4755a | 10086 | |
c19d1205 ZW |
10087 | /* Register offset. */ |
10088 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
10089 | constraint (inst.operands[1].negative, | |
10090 | _("Thumb does not support this addressing mode")); | |
90e4755a | 10091 | |
c19d1205 ZW |
10092 | op16: |
10093 | switch (inst.instruction) | |
10094 | { | |
10095 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
10096 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
10097 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
10098 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
10099 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
10100 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
10101 | case 0x5600 /* ldrsb */: | |
10102 | case 0x5e00 /* ldrsh */: break; | |
10103 | default: abort (); | |
10104 | } | |
90e4755a | 10105 | |
c19d1205 ZW |
10106 | inst.instruction |= inst.operands[0].reg; |
10107 | inst.instruction |= inst.operands[1].reg << 3; | |
10108 | inst.instruction |= inst.operands[1].imm << 6; | |
10109 | } | |
90e4755a | 10110 | |
c19d1205 ZW |
10111 | static void |
10112 | do_t_ldstd (void) | |
10113 | { | |
10114 | if (!inst.operands[1].present) | |
b99bd4ef | 10115 | { |
c19d1205 ZW |
10116 | inst.operands[1].reg = inst.operands[0].reg + 1; |
10117 | constraint (inst.operands[0].reg == REG_LR, | |
10118 | _("r14 not allowed here")); | |
b99bd4ef | 10119 | } |
c19d1205 ZW |
10120 | inst.instruction |= inst.operands[0].reg << 12; |
10121 | inst.instruction |= inst.operands[1].reg << 8; | |
10122 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
b99bd4ef NC |
10123 | } |
10124 | ||
c19d1205 ZW |
10125 | static void |
10126 | do_t_ldstt (void) | |
10127 | { | |
10128 | inst.instruction |= inst.operands[0].reg << 12; | |
10129 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
10130 | } | |
a737bd4d | 10131 | |
b99bd4ef | 10132 | static void |
c19d1205 | 10133 | do_t_mla (void) |
b99bd4ef | 10134 | { |
fdfde340 | 10135 | unsigned Rd, Rn, Rm, Ra; |
c921be7d | 10136 | |
fdfde340 JM |
10137 | Rd = inst.operands[0].reg; |
10138 | Rn = inst.operands[1].reg; | |
10139 | Rm = inst.operands[2].reg; | |
10140 | Ra = inst.operands[3].reg; | |
10141 | ||
10142 | reject_bad_reg (Rd); | |
10143 | reject_bad_reg (Rn); | |
10144 | reject_bad_reg (Rm); | |
10145 | reject_bad_reg (Ra); | |
10146 | ||
10147 | inst.instruction |= Rd << 8; | |
10148 | inst.instruction |= Rn << 16; | |
10149 | inst.instruction |= Rm; | |
10150 | inst.instruction |= Ra << 12; | |
c19d1205 | 10151 | } |
b99bd4ef | 10152 | |
c19d1205 ZW |
10153 | static void |
10154 | do_t_mlal (void) | |
10155 | { | |
fdfde340 JM |
10156 | unsigned RdLo, RdHi, Rn, Rm; |
10157 | ||
10158 | RdLo = inst.operands[0].reg; | |
10159 | RdHi = inst.operands[1].reg; | |
10160 | Rn = inst.operands[2].reg; | |
10161 | Rm = inst.operands[3].reg; | |
10162 | ||
10163 | reject_bad_reg (RdLo); | |
10164 | reject_bad_reg (RdHi); | |
10165 | reject_bad_reg (Rn); | |
10166 | reject_bad_reg (Rm); | |
10167 | ||
10168 | inst.instruction |= RdLo << 12; | |
10169 | inst.instruction |= RdHi << 8; | |
10170 | inst.instruction |= Rn << 16; | |
10171 | inst.instruction |= Rm; | |
c19d1205 | 10172 | } |
b99bd4ef | 10173 | |
c19d1205 ZW |
10174 | static void |
10175 | do_t_mov_cmp (void) | |
10176 | { | |
fdfde340 JM |
10177 | unsigned Rn, Rm; |
10178 | ||
10179 | Rn = inst.operands[0].reg; | |
10180 | Rm = inst.operands[1].reg; | |
10181 | ||
e07e6e58 NC |
10182 | if (Rn == REG_PC) |
10183 | set_it_insn_type_last (); | |
10184 | ||
c19d1205 | 10185 | if (unified_syntax) |
b99bd4ef | 10186 | { |
c19d1205 ZW |
10187 | int r0off = (inst.instruction == T_MNEM_mov |
10188 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 10189 | unsigned long opcode; |
3d388997 PB |
10190 | bfd_boolean narrow; |
10191 | bfd_boolean low_regs; | |
10192 | ||
fdfde340 | 10193 | low_regs = (Rn <= 7 && Rm <= 7); |
0110f2b8 | 10194 | opcode = inst.instruction; |
e07e6e58 | 10195 | if (in_it_block ()) |
0110f2b8 | 10196 | narrow = opcode != T_MNEM_movs; |
3d388997 | 10197 | else |
0110f2b8 | 10198 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
10199 | if (inst.size_req == 4 |
10200 | || inst.operands[1].shifted) | |
10201 | narrow = FALSE; | |
10202 | ||
efd81785 PB |
10203 | /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ |
10204 | if (opcode == T_MNEM_movs && inst.operands[1].isreg | |
10205 | && !inst.operands[1].shifted | |
fdfde340 JM |
10206 | && Rn == REG_PC |
10207 | && Rm == REG_LR) | |
efd81785 PB |
10208 | { |
10209 | inst.instruction = T2_SUBS_PC_LR; | |
10210 | return; | |
10211 | } | |
10212 | ||
fdfde340 JM |
10213 | if (opcode == T_MNEM_cmp) |
10214 | { | |
10215 | constraint (Rn == REG_PC, BAD_PC); | |
94206790 MM |
10216 | if (narrow) |
10217 | { | |
10218 | /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, | |
10219 | but valid. */ | |
10220 | warn_deprecated_sp (Rm); | |
10221 | /* R15 was documented as a valid choice for Rm in ARMv6, | |
10222 | but as UNPREDICTABLE in ARMv7. ARM's proprietary | |
10223 | tools reject R15, so we do too. */ | |
10224 | constraint (Rm == REG_PC, BAD_PC); | |
10225 | } | |
10226 | else | |
10227 | reject_bad_reg (Rm); | |
fdfde340 JM |
10228 | } |
10229 | else if (opcode == T_MNEM_mov | |
10230 | || opcode == T_MNEM_movs) | |
10231 | { | |
10232 | if (inst.operands[1].isreg) | |
10233 | { | |
10234 | if (opcode == T_MNEM_movs) | |
10235 | { | |
10236 | reject_bad_reg (Rn); | |
10237 | reject_bad_reg (Rm); | |
10238 | } | |
10239 | else if ((Rn == REG_SP || Rn == REG_PC) | |
10240 | && (Rm == REG_SP || Rm == REG_PC)) | |
10241 | reject_bad_reg (Rm); | |
10242 | } | |
10243 | else | |
10244 | reject_bad_reg (Rn); | |
10245 | } | |
10246 | ||
c19d1205 ZW |
10247 | if (!inst.operands[1].isreg) |
10248 | { | |
0110f2b8 | 10249 | /* Immediate operand. */ |
e07e6e58 | 10250 | if (!in_it_block () && opcode == T_MNEM_mov) |
0110f2b8 PB |
10251 | narrow = 0; |
10252 | if (low_regs && narrow) | |
10253 | { | |
10254 | inst.instruction = THUMB_OP16 (opcode); | |
fdfde340 | 10255 | inst.instruction |= Rn << 8; |
0110f2b8 PB |
10256 | if (inst.size_req == 2) |
10257 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
10258 | else | |
10259 | inst.relax = opcode; | |
10260 | } | |
10261 | else | |
10262 | { | |
10263 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10264 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 10265 | inst.instruction |= Rn << r0off; |
0110f2b8 PB |
10266 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
10267 | } | |
c19d1205 | 10268 | } |
728ca7c9 PB |
10269 | else if (inst.operands[1].shifted && inst.operands[1].immisreg |
10270 | && (inst.instruction == T_MNEM_mov | |
10271 | || inst.instruction == T_MNEM_movs)) | |
10272 | { | |
10273 | /* Register shifts are encoded as separate shift instructions. */ | |
10274 | bfd_boolean flags = (inst.instruction == T_MNEM_movs); | |
10275 | ||
e07e6e58 | 10276 | if (in_it_block ()) |
728ca7c9 PB |
10277 | narrow = !flags; |
10278 | else | |
10279 | narrow = flags; | |
10280 | ||
10281 | if (inst.size_req == 4) | |
10282 | narrow = FALSE; | |
10283 | ||
10284 | if (!low_regs || inst.operands[1].imm > 7) | |
10285 | narrow = FALSE; | |
10286 | ||
fdfde340 | 10287 | if (Rn != Rm) |
728ca7c9 PB |
10288 | narrow = FALSE; |
10289 | ||
10290 | switch (inst.operands[1].shift_kind) | |
10291 | { | |
10292 | case SHIFT_LSL: | |
10293 | opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); | |
10294 | break; | |
10295 | case SHIFT_ASR: | |
10296 | opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); | |
10297 | break; | |
10298 | case SHIFT_LSR: | |
10299 | opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); | |
10300 | break; | |
10301 | case SHIFT_ROR: | |
10302 | opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); | |
10303 | break; | |
10304 | default: | |
5f4273c7 | 10305 | abort (); |
728ca7c9 PB |
10306 | } |
10307 | ||
10308 | inst.instruction = opcode; | |
10309 | if (narrow) | |
10310 | { | |
fdfde340 | 10311 | inst.instruction |= Rn; |
728ca7c9 PB |
10312 | inst.instruction |= inst.operands[1].imm << 3; |
10313 | } | |
10314 | else | |
10315 | { | |
10316 | if (flags) | |
10317 | inst.instruction |= CONDS_BIT; | |
10318 | ||
fdfde340 JM |
10319 | inst.instruction |= Rn << 8; |
10320 | inst.instruction |= Rm << 16; | |
728ca7c9 PB |
10321 | inst.instruction |= inst.operands[1].imm; |
10322 | } | |
10323 | } | |
3d388997 | 10324 | else if (!narrow) |
c19d1205 | 10325 | { |
728ca7c9 PB |
10326 | /* Some mov with immediate shift have narrow variants. |
10327 | Register shifts are handled above. */ | |
10328 | if (low_regs && inst.operands[1].shifted | |
10329 | && (inst.instruction == T_MNEM_mov | |
10330 | || inst.instruction == T_MNEM_movs)) | |
10331 | { | |
e07e6e58 | 10332 | if (in_it_block ()) |
728ca7c9 PB |
10333 | narrow = (inst.instruction == T_MNEM_mov); |
10334 | else | |
10335 | narrow = (inst.instruction == T_MNEM_movs); | |
10336 | } | |
10337 | ||
10338 | if (narrow) | |
10339 | { | |
10340 | switch (inst.operands[1].shift_kind) | |
10341 | { | |
10342 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
10343 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
10344 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
10345 | default: narrow = FALSE; break; | |
10346 | } | |
10347 | } | |
10348 | ||
10349 | if (narrow) | |
10350 | { | |
fdfde340 JM |
10351 | inst.instruction |= Rn; |
10352 | inst.instruction |= Rm << 3; | |
728ca7c9 PB |
10353 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
10354 | } | |
10355 | else | |
10356 | { | |
10357 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 10358 | inst.instruction |= Rn << r0off; |
728ca7c9 PB |
10359 | encode_thumb32_shifted_operand (1); |
10360 | } | |
c19d1205 ZW |
10361 | } |
10362 | else | |
10363 | switch (inst.instruction) | |
10364 | { | |
10365 | case T_MNEM_mov: | |
10366 | inst.instruction = T_OPCODE_MOV_HR; | |
fdfde340 JM |
10367 | inst.instruction |= (Rn & 0x8) << 4; |
10368 | inst.instruction |= (Rn & 0x7); | |
10369 | inst.instruction |= Rm << 3; | |
c19d1205 | 10370 | break; |
b99bd4ef | 10371 | |
c19d1205 ZW |
10372 | case T_MNEM_movs: |
10373 | /* We know we have low registers at this point. | |
10374 | Generate ADD Rd, Rs, #0. */ | |
10375 | inst.instruction = T_OPCODE_ADD_I3; | |
fdfde340 JM |
10376 | inst.instruction |= Rn; |
10377 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10378 | break; |
10379 | ||
10380 | case T_MNEM_cmp: | |
3d388997 | 10381 | if (low_regs) |
c19d1205 ZW |
10382 | { |
10383 | inst.instruction = T_OPCODE_CMP_LR; | |
fdfde340 JM |
10384 | inst.instruction |= Rn; |
10385 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10386 | } |
10387 | else | |
10388 | { | |
10389 | inst.instruction = T_OPCODE_CMP_HR; | |
fdfde340 JM |
10390 | inst.instruction |= (Rn & 0x8) << 4; |
10391 | inst.instruction |= (Rn & 0x7); | |
10392 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10393 | } |
10394 | break; | |
10395 | } | |
b99bd4ef NC |
10396 | return; |
10397 | } | |
10398 | ||
c19d1205 | 10399 | inst.instruction = THUMB_OP16 (inst.instruction); |
539d4391 NC |
10400 | |
10401 | /* PR 10443: Do not silently ignore shifted operands. */ | |
10402 | constraint (inst.operands[1].shifted, | |
10403 | _("shifts in CMP/MOV instructions are only supported in unified syntax")); | |
10404 | ||
c19d1205 | 10405 | if (inst.operands[1].isreg) |
b99bd4ef | 10406 | { |
fdfde340 | 10407 | if (Rn < 8 && Rm < 8) |
b99bd4ef | 10408 | { |
c19d1205 ZW |
10409 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
10410 | since a MOV instruction produces unpredictable results. */ | |
10411 | if (inst.instruction == T_OPCODE_MOV_I8) | |
10412 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 10413 | else |
c19d1205 | 10414 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 10415 | |
fdfde340 JM |
10416 | inst.instruction |= Rn; |
10417 | inst.instruction |= Rm << 3; | |
b99bd4ef NC |
10418 | } |
10419 | else | |
10420 | { | |
c19d1205 ZW |
10421 | if (inst.instruction == T_OPCODE_MOV_I8) |
10422 | inst.instruction = T_OPCODE_MOV_HR; | |
10423 | else | |
10424 | inst.instruction = T_OPCODE_CMP_HR; | |
10425 | do_t_cpy (); | |
b99bd4ef NC |
10426 | } |
10427 | } | |
c19d1205 | 10428 | else |
b99bd4ef | 10429 | { |
fdfde340 | 10430 | constraint (Rn > 7, |
c19d1205 | 10431 | _("only lo regs allowed with immediate")); |
fdfde340 | 10432 | inst.instruction |= Rn << 8; |
c19d1205 ZW |
10433 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; |
10434 | } | |
10435 | } | |
b99bd4ef | 10436 | |
c19d1205 ZW |
10437 | static void |
10438 | do_t_mov16 (void) | |
10439 | { | |
fdfde340 | 10440 | unsigned Rd; |
b6895b4f PB |
10441 | bfd_vma imm; |
10442 | bfd_boolean top; | |
10443 | ||
10444 | top = (inst.instruction & 0x00800000) != 0; | |
10445 | if (inst.reloc.type == BFD_RELOC_ARM_MOVW) | |
10446 | { | |
10447 | constraint (top, _(":lower16: not allowed this instruction")); | |
10448 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; | |
10449 | } | |
10450 | else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) | |
10451 | { | |
10452 | constraint (!top, _(":upper16: not allowed this instruction")); | |
10453 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; | |
10454 | } | |
10455 | ||
fdfde340 JM |
10456 | Rd = inst.operands[0].reg; |
10457 | reject_bad_reg (Rd); | |
10458 | ||
10459 | inst.instruction |= Rd << 8; | |
b6895b4f PB |
10460 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
10461 | { | |
10462 | imm = inst.reloc.exp.X_add_number; | |
10463 | inst.instruction |= (imm & 0xf000) << 4; | |
10464 | inst.instruction |= (imm & 0x0800) << 15; | |
10465 | inst.instruction |= (imm & 0x0700) << 4; | |
10466 | inst.instruction |= (imm & 0x00ff); | |
10467 | } | |
c19d1205 | 10468 | } |
b99bd4ef | 10469 | |
c19d1205 ZW |
10470 | static void |
10471 | do_t_mvn_tst (void) | |
10472 | { | |
fdfde340 | 10473 | unsigned Rn, Rm; |
c921be7d | 10474 | |
fdfde340 JM |
10475 | Rn = inst.operands[0].reg; |
10476 | Rm = inst.operands[1].reg; | |
10477 | ||
10478 | if (inst.instruction == T_MNEM_cmp | |
10479 | || inst.instruction == T_MNEM_cmn) | |
10480 | constraint (Rn == REG_PC, BAD_PC); | |
10481 | else | |
10482 | reject_bad_reg (Rn); | |
10483 | reject_bad_reg (Rm); | |
10484 | ||
c19d1205 ZW |
10485 | if (unified_syntax) |
10486 | { | |
10487 | int r0off = (inst.instruction == T_MNEM_mvn | |
10488 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
10489 | bfd_boolean narrow; |
10490 | ||
10491 | if (inst.size_req == 4 | |
10492 | || inst.instruction > 0xffff | |
10493 | || inst.operands[1].shifted | |
fdfde340 | 10494 | || Rn > 7 || Rm > 7) |
3d388997 PB |
10495 | narrow = FALSE; |
10496 | else if (inst.instruction == T_MNEM_cmn) | |
10497 | narrow = TRUE; | |
10498 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 10499 | narrow = !in_it_block (); |
3d388997 | 10500 | else |
e07e6e58 | 10501 | narrow = in_it_block (); |
3d388997 | 10502 | |
c19d1205 | 10503 | if (!inst.operands[1].isreg) |
b99bd4ef | 10504 | { |
c19d1205 ZW |
10505 | /* For an immediate, we always generate a 32-bit opcode; |
10506 | section relaxation will shrink it later if possible. */ | |
10507 | if (inst.instruction < 0xffff) | |
10508 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10509 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 10510 | inst.instruction |= Rn << r0off; |
c19d1205 | 10511 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 10512 | } |
c19d1205 | 10513 | else |
b99bd4ef | 10514 | { |
c19d1205 | 10515 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 10516 | if (narrow) |
b99bd4ef | 10517 | { |
c19d1205 | 10518 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
10519 | inst.instruction |= Rn; |
10520 | inst.instruction |= Rm << 3; | |
b99bd4ef | 10521 | } |
c19d1205 | 10522 | else |
b99bd4ef | 10523 | { |
c19d1205 ZW |
10524 | constraint (inst.operands[1].shifted |
10525 | && inst.operands[1].immisreg, | |
10526 | _("shift must be constant")); | |
10527 | if (inst.instruction < 0xffff) | |
10528 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 10529 | inst.instruction |= Rn << r0off; |
c19d1205 | 10530 | encode_thumb32_shifted_operand (1); |
b99bd4ef | 10531 | } |
b99bd4ef NC |
10532 | } |
10533 | } | |
10534 | else | |
10535 | { | |
c19d1205 ZW |
10536 | constraint (inst.instruction > 0xffff |
10537 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
10538 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
10539 | _("unshifted register required")); | |
fdfde340 | 10540 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 10541 | BAD_HIREG); |
b99bd4ef | 10542 | |
c19d1205 | 10543 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
10544 | inst.instruction |= Rn; |
10545 | inst.instruction |= Rm << 3; | |
b99bd4ef | 10546 | } |
b99bd4ef NC |
10547 | } |
10548 | ||
b05fe5cf | 10549 | static void |
c19d1205 | 10550 | do_t_mrs (void) |
b05fe5cf | 10551 | { |
fdfde340 | 10552 | unsigned Rd; |
62b3e311 | 10553 | int flags; |
037e8744 JB |
10554 | |
10555 | if (do_vfp_nsyn_mrs () == SUCCESS) | |
10556 | return; | |
10557 | ||
62b3e311 PB |
10558 | flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
10559 | if (flags == 0) | |
10560 | { | |
7e806470 | 10561 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m), |
62b3e311 PB |
10562 | _("selected processor does not support " |
10563 | "requested special purpose register")); | |
10564 | } | |
10565 | else | |
10566 | { | |
10567 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), | |
10568 | _("selected processor does not support " | |
44bf2362 | 10569 | "requested special purpose register")); |
62b3e311 PB |
10570 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ |
10571 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
10572 | _("'CPSR' or 'SPSR' expected")); | |
10573 | } | |
5f4273c7 | 10574 | |
fdfde340 JM |
10575 | Rd = inst.operands[0].reg; |
10576 | reject_bad_reg (Rd); | |
10577 | ||
10578 | inst.instruction |= Rd << 8; | |
62b3e311 PB |
10579 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
10580 | inst.instruction |= inst.operands[1].imm & 0xff; | |
c19d1205 | 10581 | } |
b05fe5cf | 10582 | |
c19d1205 ZW |
10583 | static void |
10584 | do_t_msr (void) | |
10585 | { | |
62b3e311 | 10586 | int flags; |
fdfde340 | 10587 | unsigned Rn; |
62b3e311 | 10588 | |
037e8744 JB |
10589 | if (do_vfp_nsyn_msr () == SUCCESS) |
10590 | return; | |
10591 | ||
c19d1205 ZW |
10592 | constraint (!inst.operands[1].isreg, |
10593 | _("Thumb encoding does not support an immediate here")); | |
62b3e311 PB |
10594 | flags = inst.operands[0].imm; |
10595 | if (flags & ~0xff) | |
10596 | { | |
10597 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), | |
10598 | _("selected processor does not support " | |
10599 | "requested special purpose register")); | |
10600 | } | |
10601 | else | |
10602 | { | |
7e806470 | 10603 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m), |
62b3e311 PB |
10604 | _("selected processor does not support " |
10605 | "requested special purpose register")); | |
10606 | flags |= PSR_f; | |
10607 | } | |
c921be7d | 10608 | |
fdfde340 JM |
10609 | Rn = inst.operands[1].reg; |
10610 | reject_bad_reg (Rn); | |
10611 | ||
62b3e311 PB |
10612 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
10613 | inst.instruction |= (flags & ~SPSR_BIT) >> 8; | |
10614 | inst.instruction |= (flags & 0xff); | |
fdfde340 | 10615 | inst.instruction |= Rn << 16; |
c19d1205 | 10616 | } |
b05fe5cf | 10617 | |
c19d1205 ZW |
10618 | static void |
10619 | do_t_mul (void) | |
10620 | { | |
17828f45 | 10621 | bfd_boolean narrow; |
fdfde340 | 10622 | unsigned Rd, Rn, Rm; |
17828f45 | 10623 | |
c19d1205 ZW |
10624 | if (!inst.operands[2].present) |
10625 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 10626 | |
fdfde340 JM |
10627 | Rd = inst.operands[0].reg; |
10628 | Rn = inst.operands[1].reg; | |
10629 | Rm = inst.operands[2].reg; | |
10630 | ||
17828f45 | 10631 | if (unified_syntax) |
b05fe5cf | 10632 | { |
17828f45 | 10633 | if (inst.size_req == 4 |
fdfde340 JM |
10634 | || (Rd != Rn |
10635 | && Rd != Rm) | |
10636 | || Rn > 7 | |
10637 | || Rm > 7) | |
17828f45 JM |
10638 | narrow = FALSE; |
10639 | else if (inst.instruction == T_MNEM_muls) | |
e07e6e58 | 10640 | narrow = !in_it_block (); |
17828f45 | 10641 | else |
e07e6e58 | 10642 | narrow = in_it_block (); |
b05fe5cf | 10643 | } |
c19d1205 | 10644 | else |
b05fe5cf | 10645 | { |
17828f45 | 10646 | constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); |
fdfde340 | 10647 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 10648 | BAD_HIREG); |
17828f45 JM |
10649 | narrow = TRUE; |
10650 | } | |
b05fe5cf | 10651 | |
17828f45 JM |
10652 | if (narrow) |
10653 | { | |
10654 | /* 16-bit MULS/Conditional MUL. */ | |
c19d1205 | 10655 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 | 10656 | inst.instruction |= Rd; |
b05fe5cf | 10657 | |
fdfde340 JM |
10658 | if (Rd == Rn) |
10659 | inst.instruction |= Rm << 3; | |
10660 | else if (Rd == Rm) | |
10661 | inst.instruction |= Rn << 3; | |
c19d1205 ZW |
10662 | else |
10663 | constraint (1, _("dest must overlap one source register")); | |
10664 | } | |
17828f45 JM |
10665 | else |
10666 | { | |
e07e6e58 NC |
10667 | constraint (inst.instruction != T_MNEM_mul, |
10668 | _("Thumb-2 MUL must not set flags")); | |
17828f45 JM |
10669 | /* 32-bit MUL. */ |
10670 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
10671 | inst.instruction |= Rd << 8; |
10672 | inst.instruction |= Rn << 16; | |
10673 | inst.instruction |= Rm << 0; | |
10674 | ||
10675 | reject_bad_reg (Rd); | |
10676 | reject_bad_reg (Rn); | |
10677 | reject_bad_reg (Rm); | |
17828f45 | 10678 | } |
c19d1205 | 10679 | } |
b05fe5cf | 10680 | |
c19d1205 ZW |
10681 | static void |
10682 | do_t_mull (void) | |
10683 | { | |
fdfde340 | 10684 | unsigned RdLo, RdHi, Rn, Rm; |
b05fe5cf | 10685 | |
fdfde340 JM |
10686 | RdLo = inst.operands[0].reg; |
10687 | RdHi = inst.operands[1].reg; | |
10688 | Rn = inst.operands[2].reg; | |
10689 | Rm = inst.operands[3].reg; | |
10690 | ||
10691 | reject_bad_reg (RdLo); | |
10692 | reject_bad_reg (RdHi); | |
10693 | reject_bad_reg (Rn); | |
10694 | reject_bad_reg (Rm); | |
10695 | ||
10696 | inst.instruction |= RdLo << 12; | |
10697 | inst.instruction |= RdHi << 8; | |
10698 | inst.instruction |= Rn << 16; | |
10699 | inst.instruction |= Rm; | |
10700 | ||
10701 | if (RdLo == RdHi) | |
c19d1205 ZW |
10702 | as_tsktsk (_("rdhi and rdlo must be different")); |
10703 | } | |
b05fe5cf | 10704 | |
c19d1205 ZW |
10705 | static void |
10706 | do_t_nop (void) | |
10707 | { | |
e07e6e58 NC |
10708 | set_it_insn_type (NEUTRAL_IT_INSN); |
10709 | ||
c19d1205 ZW |
10710 | if (unified_syntax) |
10711 | { | |
10712 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 10713 | { |
c19d1205 ZW |
10714 | inst.instruction = THUMB_OP32 (inst.instruction); |
10715 | inst.instruction |= inst.operands[0].imm; | |
10716 | } | |
10717 | else | |
10718 | { | |
bc2d1808 NC |
10719 | /* PR9722: Check for Thumb2 availability before |
10720 | generating a thumb2 nop instruction. */ | |
afa62d5e | 10721 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
bc2d1808 NC |
10722 | { |
10723 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10724 | inst.instruction |= inst.operands[0].imm << 4; | |
10725 | } | |
10726 | else | |
10727 | inst.instruction = 0x46c0; | |
c19d1205 ZW |
10728 | } |
10729 | } | |
10730 | else | |
10731 | { | |
10732 | constraint (inst.operands[0].present, | |
10733 | _("Thumb does not support NOP with hints")); | |
10734 | inst.instruction = 0x46c0; | |
10735 | } | |
10736 | } | |
b05fe5cf | 10737 | |
c19d1205 ZW |
10738 | static void |
10739 | do_t_neg (void) | |
10740 | { | |
10741 | if (unified_syntax) | |
10742 | { | |
3d388997 PB |
10743 | bfd_boolean narrow; |
10744 | ||
10745 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 10746 | narrow = !in_it_block (); |
3d388997 | 10747 | else |
e07e6e58 | 10748 | narrow = in_it_block (); |
3d388997 PB |
10749 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
10750 | narrow = FALSE; | |
10751 | if (inst.size_req == 4) | |
10752 | narrow = FALSE; | |
10753 | ||
10754 | if (!narrow) | |
c19d1205 ZW |
10755 | { |
10756 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10757 | inst.instruction |= inst.operands[0].reg << 8; | |
10758 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
10759 | } |
10760 | else | |
10761 | { | |
c19d1205 ZW |
10762 | inst.instruction = THUMB_OP16 (inst.instruction); |
10763 | inst.instruction |= inst.operands[0].reg; | |
10764 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
10765 | } |
10766 | } | |
10767 | else | |
10768 | { | |
c19d1205 ZW |
10769 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
10770 | BAD_HIREG); | |
10771 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
10772 | ||
10773 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10774 | inst.instruction |= inst.operands[0].reg; | |
10775 | inst.instruction |= inst.operands[1].reg << 3; | |
10776 | } | |
10777 | } | |
10778 | ||
1c444d06 JM |
10779 | static void |
10780 | do_t_orn (void) | |
10781 | { | |
10782 | unsigned Rd, Rn; | |
10783 | ||
10784 | Rd = inst.operands[0].reg; | |
10785 | Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; | |
10786 | ||
fdfde340 JM |
10787 | reject_bad_reg (Rd); |
10788 | /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ | |
10789 | reject_bad_reg (Rn); | |
10790 | ||
1c444d06 JM |
10791 | inst.instruction |= Rd << 8; |
10792 | inst.instruction |= Rn << 16; | |
10793 | ||
10794 | if (!inst.operands[2].isreg) | |
10795 | { | |
10796 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
10797 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10798 | } | |
10799 | else | |
10800 | { | |
10801 | unsigned Rm; | |
10802 | ||
10803 | Rm = inst.operands[2].reg; | |
fdfde340 | 10804 | reject_bad_reg (Rm); |
1c444d06 JM |
10805 | |
10806 | constraint (inst.operands[2].shifted | |
10807 | && inst.operands[2].immisreg, | |
10808 | _("shift must be constant")); | |
10809 | encode_thumb32_shifted_operand (2); | |
10810 | } | |
10811 | } | |
10812 | ||
c19d1205 ZW |
10813 | static void |
10814 | do_t_pkhbt (void) | |
10815 | { | |
fdfde340 JM |
10816 | unsigned Rd, Rn, Rm; |
10817 | ||
10818 | Rd = inst.operands[0].reg; | |
10819 | Rn = inst.operands[1].reg; | |
10820 | Rm = inst.operands[2].reg; | |
10821 | ||
10822 | reject_bad_reg (Rd); | |
10823 | reject_bad_reg (Rn); | |
10824 | reject_bad_reg (Rm); | |
10825 | ||
10826 | inst.instruction |= Rd << 8; | |
10827 | inst.instruction |= Rn << 16; | |
10828 | inst.instruction |= Rm; | |
c19d1205 ZW |
10829 | if (inst.operands[3].present) |
10830 | { | |
10831 | unsigned int val = inst.reloc.exp.X_add_number; | |
10832 | constraint (inst.reloc.exp.X_op != O_constant, | |
10833 | _("expression too complex")); | |
10834 | inst.instruction |= (val & 0x1c) << 10; | |
10835 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 10836 | } |
c19d1205 | 10837 | } |
b05fe5cf | 10838 | |
c19d1205 ZW |
10839 | static void |
10840 | do_t_pkhtb (void) | |
10841 | { | |
10842 | if (!inst.operands[3].present) | |
1ef52f49 NC |
10843 | { |
10844 | unsigned Rtmp; | |
10845 | ||
10846 | inst.instruction &= ~0x00000020; | |
10847 | ||
10848 | /* PR 10168. Swap the Rm and Rn registers. */ | |
10849 | Rtmp = inst.operands[1].reg; | |
10850 | inst.operands[1].reg = inst.operands[2].reg; | |
10851 | inst.operands[2].reg = Rtmp; | |
10852 | } | |
c19d1205 | 10853 | do_t_pkhbt (); |
b05fe5cf ZW |
10854 | } |
10855 | ||
c19d1205 ZW |
10856 | static void |
10857 | do_t_pld (void) | |
10858 | { | |
fdfde340 JM |
10859 | if (inst.operands[0].immisreg) |
10860 | reject_bad_reg (inst.operands[0].imm); | |
10861 | ||
c19d1205 ZW |
10862 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); |
10863 | } | |
b05fe5cf | 10864 | |
c19d1205 ZW |
10865 | static void |
10866 | do_t_push_pop (void) | |
b99bd4ef | 10867 | { |
e9f89963 | 10868 | unsigned mask; |
5f4273c7 | 10869 | |
c19d1205 ZW |
10870 | constraint (inst.operands[0].writeback, |
10871 | _("push/pop do not support {reglist}^")); | |
10872 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
10873 | _("expression too complex")); | |
b99bd4ef | 10874 | |
e9f89963 PB |
10875 | mask = inst.operands[0].imm; |
10876 | if ((mask & ~0xff) == 0) | |
3c707909 | 10877 | inst.instruction = THUMB_OP16 (inst.instruction) | mask; |
c19d1205 | 10878 | else if ((inst.instruction == T_MNEM_push |
e9f89963 | 10879 | && (mask & ~0xff) == 1 << REG_LR) |
c19d1205 | 10880 | || (inst.instruction == T_MNEM_pop |
e9f89963 | 10881 | && (mask & ~0xff) == 1 << REG_PC)) |
b99bd4ef | 10882 | { |
c19d1205 ZW |
10883 | inst.instruction = THUMB_OP16 (inst.instruction); |
10884 | inst.instruction |= THUMB_PP_PC_LR; | |
3c707909 | 10885 | inst.instruction |= mask & 0xff; |
c19d1205 ZW |
10886 | } |
10887 | else if (unified_syntax) | |
10888 | { | |
3c707909 | 10889 | inst.instruction = THUMB_OP32 (inst.instruction); |
5f4273c7 | 10890 | encode_thumb2_ldmstm (13, mask, TRUE); |
c19d1205 ZW |
10891 | } |
10892 | else | |
10893 | { | |
10894 | inst.error = _("invalid register list to push/pop instruction"); | |
10895 | return; | |
10896 | } | |
c19d1205 | 10897 | } |
b99bd4ef | 10898 | |
c19d1205 ZW |
10899 | static void |
10900 | do_t_rbit (void) | |
10901 | { | |
fdfde340 JM |
10902 | unsigned Rd, Rm; |
10903 | ||
10904 | Rd = inst.operands[0].reg; | |
10905 | Rm = inst.operands[1].reg; | |
10906 | ||
10907 | reject_bad_reg (Rd); | |
10908 | reject_bad_reg (Rm); | |
10909 | ||
10910 | inst.instruction |= Rd << 8; | |
10911 | inst.instruction |= Rm << 16; | |
10912 | inst.instruction |= Rm; | |
c19d1205 | 10913 | } |
b99bd4ef | 10914 | |
c19d1205 ZW |
10915 | static void |
10916 | do_t_rev (void) | |
10917 | { | |
fdfde340 JM |
10918 | unsigned Rd, Rm; |
10919 | ||
10920 | Rd = inst.operands[0].reg; | |
10921 | Rm = inst.operands[1].reg; | |
10922 | ||
10923 | reject_bad_reg (Rd); | |
10924 | reject_bad_reg (Rm); | |
10925 | ||
10926 | if (Rd <= 7 && Rm <= 7 | |
c19d1205 ZW |
10927 | && inst.size_req != 4) |
10928 | { | |
10929 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 JM |
10930 | inst.instruction |= Rd; |
10931 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10932 | } |
10933 | else if (unified_syntax) | |
10934 | { | |
10935 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
10936 | inst.instruction |= Rd << 8; |
10937 | inst.instruction |= Rm << 16; | |
10938 | inst.instruction |= Rm; | |
c19d1205 ZW |
10939 | } |
10940 | else | |
10941 | inst.error = BAD_HIREG; | |
10942 | } | |
b99bd4ef | 10943 | |
1c444d06 JM |
10944 | static void |
10945 | do_t_rrx (void) | |
10946 | { | |
10947 | unsigned Rd, Rm; | |
10948 | ||
10949 | Rd = inst.operands[0].reg; | |
10950 | Rm = inst.operands[1].reg; | |
10951 | ||
fdfde340 JM |
10952 | reject_bad_reg (Rd); |
10953 | reject_bad_reg (Rm); | |
c921be7d | 10954 | |
1c444d06 JM |
10955 | inst.instruction |= Rd << 8; |
10956 | inst.instruction |= Rm; | |
10957 | } | |
10958 | ||
c19d1205 ZW |
10959 | static void |
10960 | do_t_rsb (void) | |
10961 | { | |
fdfde340 | 10962 | unsigned Rd, Rs; |
b99bd4ef | 10963 | |
c19d1205 ZW |
10964 | Rd = inst.operands[0].reg; |
10965 | Rs = (inst.operands[1].present | |
10966 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
10967 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 10968 | |
fdfde340 JM |
10969 | reject_bad_reg (Rd); |
10970 | reject_bad_reg (Rs); | |
10971 | if (inst.operands[2].isreg) | |
10972 | reject_bad_reg (inst.operands[2].reg); | |
10973 | ||
c19d1205 ZW |
10974 | inst.instruction |= Rd << 8; |
10975 | inst.instruction |= Rs << 16; | |
10976 | if (!inst.operands[2].isreg) | |
10977 | { | |
026d3abb PB |
10978 | bfd_boolean narrow; |
10979 | ||
10980 | if ((inst.instruction & 0x00100000) != 0) | |
e07e6e58 | 10981 | narrow = !in_it_block (); |
026d3abb | 10982 | else |
e07e6e58 | 10983 | narrow = in_it_block (); |
026d3abb PB |
10984 | |
10985 | if (Rd > 7 || Rs > 7) | |
10986 | narrow = FALSE; | |
10987 | ||
10988 | if (inst.size_req == 4 || !unified_syntax) | |
10989 | narrow = FALSE; | |
10990 | ||
10991 | if (inst.reloc.exp.X_op != O_constant | |
10992 | || inst.reloc.exp.X_add_number != 0) | |
10993 | narrow = FALSE; | |
10994 | ||
10995 | /* Turn rsb #0 into 16-bit neg. We should probably do this via | |
10996 | relaxation, but it doesn't seem worth the hassle. */ | |
10997 | if (narrow) | |
10998 | { | |
10999 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11000 | inst.instruction = THUMB_OP16 (T_MNEM_negs); | |
11001 | inst.instruction |= Rs << 3; | |
11002 | inst.instruction |= Rd; | |
11003 | } | |
11004 | else | |
11005 | { | |
11006 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
11007 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
11008 | } | |
c19d1205 ZW |
11009 | } |
11010 | else | |
11011 | encode_thumb32_shifted_operand (2); | |
11012 | } | |
b99bd4ef | 11013 | |
c19d1205 ZW |
11014 | static void |
11015 | do_t_setend (void) | |
11016 | { | |
e07e6e58 | 11017 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
11018 | if (inst.operands[0].imm) |
11019 | inst.instruction |= 0x8; | |
11020 | } | |
b99bd4ef | 11021 | |
c19d1205 ZW |
11022 | static void |
11023 | do_t_shift (void) | |
11024 | { | |
11025 | if (!inst.operands[1].present) | |
11026 | inst.operands[1].reg = inst.operands[0].reg; | |
11027 | ||
11028 | if (unified_syntax) | |
11029 | { | |
3d388997 PB |
11030 | bfd_boolean narrow; |
11031 | int shift_kind; | |
11032 | ||
11033 | switch (inst.instruction) | |
11034 | { | |
11035 | case T_MNEM_asr: | |
11036 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
11037 | case T_MNEM_lsl: | |
11038 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
11039 | case T_MNEM_lsr: | |
11040 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
11041 | case T_MNEM_ror: | |
11042 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
11043 | default: abort (); | |
11044 | } | |
11045 | ||
11046 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11047 | narrow = !in_it_block (); |
3d388997 | 11048 | else |
e07e6e58 | 11049 | narrow = in_it_block (); |
3d388997 PB |
11050 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
11051 | narrow = FALSE; | |
11052 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
11053 | narrow = FALSE; | |
11054 | if (inst.operands[2].isreg | |
11055 | && (inst.operands[1].reg != inst.operands[0].reg | |
11056 | || inst.operands[2].reg > 7)) | |
11057 | narrow = FALSE; | |
11058 | if (inst.size_req == 4) | |
11059 | narrow = FALSE; | |
11060 | ||
fdfde340 JM |
11061 | reject_bad_reg (inst.operands[0].reg); |
11062 | reject_bad_reg (inst.operands[1].reg); | |
c921be7d | 11063 | |
3d388997 | 11064 | if (!narrow) |
c19d1205 ZW |
11065 | { |
11066 | if (inst.operands[2].isreg) | |
b99bd4ef | 11067 | { |
fdfde340 | 11068 | reject_bad_reg (inst.operands[2].reg); |
c19d1205 ZW |
11069 | inst.instruction = THUMB_OP32 (inst.instruction); |
11070 | inst.instruction |= inst.operands[0].reg << 8; | |
11071 | inst.instruction |= inst.operands[1].reg << 16; | |
11072 | inst.instruction |= inst.operands[2].reg; | |
11073 | } | |
11074 | else | |
11075 | { | |
11076 | inst.operands[1].shifted = 1; | |
3d388997 | 11077 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
11078 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
11079 | ? T_MNEM_movs : T_MNEM_mov); | |
11080 | inst.instruction |= inst.operands[0].reg << 8; | |
11081 | encode_thumb32_shifted_operand (1); | |
11082 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
11083 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
11084 | } |
11085 | } | |
11086 | else | |
11087 | { | |
c19d1205 | 11088 | if (inst.operands[2].isreg) |
b99bd4ef | 11089 | { |
3d388997 | 11090 | switch (shift_kind) |
b99bd4ef | 11091 | { |
3d388997 PB |
11092 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
11093 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
11094 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
11095 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 11096 | default: abort (); |
b99bd4ef | 11097 | } |
5f4273c7 | 11098 | |
c19d1205 ZW |
11099 | inst.instruction |= inst.operands[0].reg; |
11100 | inst.instruction |= inst.operands[2].reg << 3; | |
b99bd4ef NC |
11101 | } |
11102 | else | |
11103 | { | |
3d388997 | 11104 | switch (shift_kind) |
b99bd4ef | 11105 | { |
3d388997 PB |
11106 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
11107 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
11108 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 11109 | default: abort (); |
b99bd4ef | 11110 | } |
c19d1205 ZW |
11111 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
11112 | inst.instruction |= inst.operands[0].reg; | |
11113 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
11114 | } |
11115 | } | |
c19d1205 ZW |
11116 | } |
11117 | else | |
11118 | { | |
11119 | constraint (inst.operands[0].reg > 7 | |
11120 | || inst.operands[1].reg > 7, BAD_HIREG); | |
11121 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 11122 | |
c19d1205 ZW |
11123 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
11124 | { | |
11125 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
11126 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
11127 | _("source1 and dest must be same register")); | |
b99bd4ef | 11128 | |
c19d1205 ZW |
11129 | switch (inst.instruction) |
11130 | { | |
11131 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
11132 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
11133 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
11134 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
11135 | default: abort (); | |
11136 | } | |
5f4273c7 | 11137 | |
c19d1205 ZW |
11138 | inst.instruction |= inst.operands[0].reg; |
11139 | inst.instruction |= inst.operands[2].reg << 3; | |
11140 | } | |
11141 | else | |
b99bd4ef | 11142 | { |
c19d1205 ZW |
11143 | switch (inst.instruction) |
11144 | { | |
11145 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
11146 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
11147 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
11148 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
11149 | default: abort (); | |
11150 | } | |
11151 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
11152 | inst.instruction |= inst.operands[0].reg; | |
11153 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
11154 | } |
11155 | } | |
b99bd4ef NC |
11156 | } |
11157 | ||
11158 | static void | |
c19d1205 | 11159 | do_t_simd (void) |
b99bd4ef | 11160 | { |
fdfde340 JM |
11161 | unsigned Rd, Rn, Rm; |
11162 | ||
11163 | Rd = inst.operands[0].reg; | |
11164 | Rn = inst.operands[1].reg; | |
11165 | Rm = inst.operands[2].reg; | |
11166 | ||
11167 | reject_bad_reg (Rd); | |
11168 | reject_bad_reg (Rn); | |
11169 | reject_bad_reg (Rm); | |
11170 | ||
11171 | inst.instruction |= Rd << 8; | |
11172 | inst.instruction |= Rn << 16; | |
11173 | inst.instruction |= Rm; | |
c19d1205 | 11174 | } |
b99bd4ef | 11175 | |
03ee1b7f NC |
11176 | static void |
11177 | do_t_simd2 (void) | |
11178 | { | |
11179 | unsigned Rd, Rn, Rm; | |
11180 | ||
11181 | Rd = inst.operands[0].reg; | |
11182 | Rm = inst.operands[1].reg; | |
11183 | Rn = inst.operands[2].reg; | |
11184 | ||
11185 | reject_bad_reg (Rd); | |
11186 | reject_bad_reg (Rn); | |
11187 | reject_bad_reg (Rm); | |
11188 | ||
11189 | inst.instruction |= Rd << 8; | |
11190 | inst.instruction |= Rn << 16; | |
11191 | inst.instruction |= Rm; | |
11192 | } | |
11193 | ||
c19d1205 | 11194 | static void |
3eb17e6b | 11195 | do_t_smc (void) |
c19d1205 ZW |
11196 | { |
11197 | unsigned int value = inst.reloc.exp.X_add_number; | |
11198 | constraint (inst.reloc.exp.X_op != O_constant, | |
11199 | _("expression too complex")); | |
11200 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11201 | inst.instruction |= (value & 0xf000) >> 12; | |
11202 | inst.instruction |= (value & 0x0ff0); | |
11203 | inst.instruction |= (value & 0x000f) << 16; | |
11204 | } | |
b99bd4ef | 11205 | |
c19d1205 | 11206 | static void |
3a21c15a | 11207 | do_t_ssat_usat (int bias) |
c19d1205 | 11208 | { |
fdfde340 JM |
11209 | unsigned Rd, Rn; |
11210 | ||
11211 | Rd = inst.operands[0].reg; | |
11212 | Rn = inst.operands[2].reg; | |
11213 | ||
11214 | reject_bad_reg (Rd); | |
11215 | reject_bad_reg (Rn); | |
11216 | ||
11217 | inst.instruction |= Rd << 8; | |
3a21c15a | 11218 | inst.instruction |= inst.operands[1].imm - bias; |
fdfde340 | 11219 | inst.instruction |= Rn << 16; |
b99bd4ef | 11220 | |
c19d1205 | 11221 | if (inst.operands[3].present) |
b99bd4ef | 11222 | { |
3a21c15a NC |
11223 | offsetT shift_amount = inst.reloc.exp.X_add_number; |
11224 | ||
11225 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11226 | ||
c19d1205 ZW |
11227 | constraint (inst.reloc.exp.X_op != O_constant, |
11228 | _("expression too complex")); | |
b99bd4ef | 11229 | |
3a21c15a | 11230 | if (shift_amount != 0) |
6189168b | 11231 | { |
3a21c15a NC |
11232 | constraint (shift_amount > 31, |
11233 | _("shift expression is too large")); | |
11234 | ||
c19d1205 | 11235 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
3a21c15a NC |
11236 | inst.instruction |= 0x00200000; /* sh bit. */ |
11237 | ||
11238 | inst.instruction |= (shift_amount & 0x1c) << 10; | |
11239 | inst.instruction |= (shift_amount & 0x03) << 6; | |
6189168b NC |
11240 | } |
11241 | } | |
b99bd4ef | 11242 | } |
c921be7d | 11243 | |
3a21c15a NC |
11244 | static void |
11245 | do_t_ssat (void) | |
11246 | { | |
11247 | do_t_ssat_usat (1); | |
11248 | } | |
b99bd4ef | 11249 | |
0dd132b6 | 11250 | static void |
c19d1205 | 11251 | do_t_ssat16 (void) |
0dd132b6 | 11252 | { |
fdfde340 JM |
11253 | unsigned Rd, Rn; |
11254 | ||
11255 | Rd = inst.operands[0].reg; | |
11256 | Rn = inst.operands[2].reg; | |
11257 | ||
11258 | reject_bad_reg (Rd); | |
11259 | reject_bad_reg (Rn); | |
11260 | ||
11261 | inst.instruction |= Rd << 8; | |
c19d1205 | 11262 | inst.instruction |= inst.operands[1].imm - 1; |
fdfde340 | 11263 | inst.instruction |= Rn << 16; |
c19d1205 | 11264 | } |
0dd132b6 | 11265 | |
c19d1205 ZW |
11266 | static void |
11267 | do_t_strex (void) | |
11268 | { | |
11269 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
11270 | || inst.operands[2].postind || inst.operands[2].writeback | |
11271 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
11272 | || inst.operands[2].negative, | |
01cfc07f | 11273 | BAD_ADDR_MODE); |
0dd132b6 | 11274 | |
5be8be5d DG |
11275 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
11276 | ||
c19d1205 ZW |
11277 | inst.instruction |= inst.operands[0].reg << 8; |
11278 | inst.instruction |= inst.operands[1].reg << 12; | |
11279 | inst.instruction |= inst.operands[2].reg << 16; | |
11280 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
11281 | } |
11282 | ||
b99bd4ef | 11283 | static void |
c19d1205 | 11284 | do_t_strexd (void) |
b99bd4ef | 11285 | { |
c19d1205 ZW |
11286 | if (!inst.operands[2].present) |
11287 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 11288 | |
c19d1205 ZW |
11289 | constraint (inst.operands[0].reg == inst.operands[1].reg |
11290 | || inst.operands[0].reg == inst.operands[2].reg | |
f8a8e9d6 | 11291 | || inst.operands[0].reg == inst.operands[3].reg, |
c19d1205 | 11292 | BAD_OVERLAP); |
b99bd4ef | 11293 | |
c19d1205 ZW |
11294 | inst.instruction |= inst.operands[0].reg; |
11295 | inst.instruction |= inst.operands[1].reg << 12; | |
11296 | inst.instruction |= inst.operands[2].reg << 8; | |
11297 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
11298 | } |
11299 | ||
11300 | static void | |
c19d1205 | 11301 | do_t_sxtah (void) |
b99bd4ef | 11302 | { |
fdfde340 JM |
11303 | unsigned Rd, Rn, Rm; |
11304 | ||
11305 | Rd = inst.operands[0].reg; | |
11306 | Rn = inst.operands[1].reg; | |
11307 | Rm = inst.operands[2].reg; | |
11308 | ||
11309 | reject_bad_reg (Rd); | |
11310 | reject_bad_reg (Rn); | |
11311 | reject_bad_reg (Rm); | |
11312 | ||
11313 | inst.instruction |= Rd << 8; | |
11314 | inst.instruction |= Rn << 16; | |
11315 | inst.instruction |= Rm; | |
c19d1205 ZW |
11316 | inst.instruction |= inst.operands[3].imm << 4; |
11317 | } | |
b99bd4ef | 11318 | |
c19d1205 ZW |
11319 | static void |
11320 | do_t_sxth (void) | |
11321 | { | |
fdfde340 JM |
11322 | unsigned Rd, Rm; |
11323 | ||
11324 | Rd = inst.operands[0].reg; | |
11325 | Rm = inst.operands[1].reg; | |
11326 | ||
11327 | reject_bad_reg (Rd); | |
11328 | reject_bad_reg (Rm); | |
c921be7d NC |
11329 | |
11330 | if (inst.instruction <= 0xffff | |
11331 | && inst.size_req != 4 | |
fdfde340 | 11332 | && Rd <= 7 && Rm <= 7 |
c19d1205 | 11333 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) |
b99bd4ef | 11334 | { |
c19d1205 | 11335 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
11336 | inst.instruction |= Rd; |
11337 | inst.instruction |= Rm << 3; | |
b99bd4ef | 11338 | } |
c19d1205 | 11339 | else if (unified_syntax) |
b99bd4ef | 11340 | { |
c19d1205 ZW |
11341 | if (inst.instruction <= 0xffff) |
11342 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
11343 | inst.instruction |= Rd << 8; |
11344 | inst.instruction |= Rm; | |
c19d1205 | 11345 | inst.instruction |= inst.operands[2].imm << 4; |
b99bd4ef | 11346 | } |
c19d1205 | 11347 | else |
b99bd4ef | 11348 | { |
c19d1205 ZW |
11349 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
11350 | _("Thumb encoding does not support rotation")); | |
11351 | constraint (1, BAD_HIREG); | |
b99bd4ef | 11352 | } |
c19d1205 | 11353 | } |
b99bd4ef | 11354 | |
c19d1205 ZW |
11355 | static void |
11356 | do_t_swi (void) | |
11357 | { | |
11358 | inst.reloc.type = BFD_RELOC_ARM_SWI; | |
11359 | } | |
b99bd4ef | 11360 | |
92e90b6e PB |
11361 | static void |
11362 | do_t_tb (void) | |
11363 | { | |
fdfde340 | 11364 | unsigned Rn, Rm; |
92e90b6e PB |
11365 | int half; |
11366 | ||
11367 | half = (inst.instruction & 0x10) != 0; | |
e07e6e58 | 11368 | set_it_insn_type_last (); |
dfa9f0d5 PB |
11369 | constraint (inst.operands[0].immisreg, |
11370 | _("instruction requires register index")); | |
fdfde340 JM |
11371 | |
11372 | Rn = inst.operands[0].reg; | |
11373 | Rm = inst.operands[0].imm; | |
c921be7d | 11374 | |
fdfde340 JM |
11375 | constraint (Rn == REG_SP, BAD_SP); |
11376 | reject_bad_reg (Rm); | |
11377 | ||
92e90b6e PB |
11378 | constraint (!half && inst.operands[0].shifted, |
11379 | _("instruction does not allow shifted index")); | |
fdfde340 | 11380 | inst.instruction |= (Rn << 16) | Rm; |
92e90b6e PB |
11381 | } |
11382 | ||
c19d1205 ZW |
11383 | static void |
11384 | do_t_usat (void) | |
11385 | { | |
3a21c15a | 11386 | do_t_ssat_usat (0); |
b99bd4ef NC |
11387 | } |
11388 | ||
11389 | static void | |
c19d1205 | 11390 | do_t_usat16 (void) |
b99bd4ef | 11391 | { |
fdfde340 JM |
11392 | unsigned Rd, Rn; |
11393 | ||
11394 | Rd = inst.operands[0].reg; | |
11395 | Rn = inst.operands[2].reg; | |
11396 | ||
11397 | reject_bad_reg (Rd); | |
11398 | reject_bad_reg (Rn); | |
11399 | ||
11400 | inst.instruction |= Rd << 8; | |
c19d1205 | 11401 | inst.instruction |= inst.operands[1].imm; |
fdfde340 | 11402 | inst.instruction |= Rn << 16; |
b99bd4ef | 11403 | } |
c19d1205 | 11404 | |
5287ad62 | 11405 | /* Neon instruction encoder helpers. */ |
5f4273c7 | 11406 | |
5287ad62 | 11407 | /* Encodings for the different types for various Neon opcodes. */ |
b99bd4ef | 11408 | |
5287ad62 JB |
11409 | /* An "invalid" code for the following tables. */ |
11410 | #define N_INV -1u | |
11411 | ||
11412 | struct neon_tab_entry | |
b99bd4ef | 11413 | { |
5287ad62 JB |
11414 | unsigned integer; |
11415 | unsigned float_or_poly; | |
11416 | unsigned scalar_or_imm; | |
11417 | }; | |
5f4273c7 | 11418 | |
5287ad62 JB |
11419 | /* Map overloaded Neon opcodes to their respective encodings. */ |
11420 | #define NEON_ENC_TAB \ | |
11421 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ | |
11422 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ | |
11423 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ | |
11424 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ | |
11425 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ | |
11426 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ | |
11427 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ | |
11428 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ | |
11429 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ | |
11430 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ | |
11431 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ | |
11432 | /* Register variants of the following two instructions are encoded as | |
e07e6e58 | 11433 | vcge / vcgt with the operands reversed. */ \ |
92559b5b PB |
11434 | X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ |
11435 | X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ | |
62f3b8c8 PB |
11436 | X(vfma, N_INV, 0x0000c10, N_INV), \ |
11437 | X(vfms, N_INV, 0x0200c10, N_INV), \ | |
5287ad62 JB |
11438 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ |
11439 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ | |
11440 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ | |
11441 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ | |
11442 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ | |
11443 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ | |
11444 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ | |
11445 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ | |
11446 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ | |
11447 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ | |
11448 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ | |
11449 | X(vshl, 0x0000400, N_INV, 0x0800510), \ | |
11450 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ | |
11451 | X(vand, 0x0000110, N_INV, 0x0800030), \ | |
11452 | X(vbic, 0x0100110, N_INV, 0x0800030), \ | |
11453 | X(veor, 0x1000110, N_INV, N_INV), \ | |
11454 | X(vorn, 0x0300110, N_INV, 0x0800010), \ | |
11455 | X(vorr, 0x0200110, N_INV, 0x0800010), \ | |
11456 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ | |
11457 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ | |
11458 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ | |
11459 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ | |
11460 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ | |
11461 | X(vst1, 0x0000000, 0x0800000, N_INV), \ | |
11462 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ | |
11463 | X(vst2, 0x0000100, 0x0800100, N_INV), \ | |
11464 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ | |
11465 | X(vst3, 0x0000200, 0x0800200, N_INV), \ | |
11466 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ | |
11467 | X(vst4, 0x0000300, 0x0800300, N_INV), \ | |
11468 | X(vmovn, 0x1b20200, N_INV, N_INV), \ | |
11469 | X(vtrn, 0x1b20080, N_INV, N_INV), \ | |
11470 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ | |
037e8744 JB |
11471 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
11472 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ | |
e6655fda PB |
11473 | X(vnmla, 0xe100a40, 0xe100b40, N_INV), \ |
11474 | X(vnmls, 0xe100a00, 0xe100b00, N_INV), \ | |
62f3b8c8 PB |
11475 | X(vfnma, 0xe900a40, 0xe900b40, N_INV), \ |
11476 | X(vfnms, 0xe900a00, 0xe900b00, N_INV), \ | |
037e8744 JB |
11477 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ |
11478 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ | |
11479 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ | |
11480 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) | |
5287ad62 JB |
11481 | |
11482 | enum neon_opc | |
11483 | { | |
11484 | #define X(OPC,I,F,S) N_MNEM_##OPC | |
11485 | NEON_ENC_TAB | |
11486 | #undef X | |
11487 | }; | |
b99bd4ef | 11488 | |
5287ad62 JB |
11489 | static const struct neon_tab_entry neon_enc_tab[] = |
11490 | { | |
11491 | #define X(OPC,I,F,S) { (I), (F), (S) } | |
11492 | NEON_ENC_TAB | |
11493 | #undef X | |
11494 | }; | |
b99bd4ef | 11495 | |
88714cb8 DG |
11496 | /* Do not use these macros; instead, use NEON_ENCODE defined below. */ |
11497 | #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
11498 | #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
11499 | #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11500 | #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11501 | #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
11502 | #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
11503 | #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
11504 | #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11505 | #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
11506 | #define NEON_ENC_SINGLE_(X) \ | |
037e8744 | 11507 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) |
88714cb8 | 11508 | #define NEON_ENC_DOUBLE_(X) \ |
037e8744 | 11509 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) |
5287ad62 | 11510 | |
88714cb8 DG |
11511 | #define NEON_ENCODE(type, inst) \ |
11512 | do \ | |
11513 | { \ | |
11514 | inst.instruction = NEON_ENC_##type##_ (inst.instruction); \ | |
11515 | inst.is_neon = 1; \ | |
11516 | } \ | |
11517 | while (0) | |
11518 | ||
11519 | #define check_neon_suffixes \ | |
11520 | do \ | |
11521 | { \ | |
11522 | if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \ | |
11523 | { \ | |
11524 | as_bad (_("invalid neon suffix for non neon instruction")); \ | |
11525 | return; \ | |
11526 | } \ | |
11527 | } \ | |
11528 | while (0) | |
11529 | ||
037e8744 JB |
11530 | /* Define shapes for instruction operands. The following mnemonic characters |
11531 | are used in this table: | |
5287ad62 | 11532 | |
037e8744 | 11533 | F - VFP S<n> register |
5287ad62 JB |
11534 | D - Neon D<n> register |
11535 | Q - Neon Q<n> register | |
11536 | I - Immediate | |
11537 | S - Scalar | |
11538 | R - ARM register | |
11539 | L - D<n> register list | |
5f4273c7 | 11540 | |
037e8744 JB |
11541 | This table is used to generate various data: |
11542 | - enumerations of the form NS_DDR to be used as arguments to | |
11543 | neon_select_shape. | |
11544 | - a table classifying shapes into single, double, quad, mixed. | |
5f4273c7 | 11545 | - a table used to drive neon_select_shape. */ |
b99bd4ef | 11546 | |
037e8744 JB |
11547 | #define NEON_SHAPE_DEF \ |
11548 | X(3, (D, D, D), DOUBLE), \ | |
11549 | X(3, (Q, Q, Q), QUAD), \ | |
11550 | X(3, (D, D, I), DOUBLE), \ | |
11551 | X(3, (Q, Q, I), QUAD), \ | |
11552 | X(3, (D, D, S), DOUBLE), \ | |
11553 | X(3, (Q, Q, S), QUAD), \ | |
11554 | X(2, (D, D), DOUBLE), \ | |
11555 | X(2, (Q, Q), QUAD), \ | |
11556 | X(2, (D, S), DOUBLE), \ | |
11557 | X(2, (Q, S), QUAD), \ | |
11558 | X(2, (D, R), DOUBLE), \ | |
11559 | X(2, (Q, R), QUAD), \ | |
11560 | X(2, (D, I), DOUBLE), \ | |
11561 | X(2, (Q, I), QUAD), \ | |
11562 | X(3, (D, L, D), DOUBLE), \ | |
11563 | X(2, (D, Q), MIXED), \ | |
11564 | X(2, (Q, D), MIXED), \ | |
11565 | X(3, (D, Q, I), MIXED), \ | |
11566 | X(3, (Q, D, I), MIXED), \ | |
11567 | X(3, (Q, D, D), MIXED), \ | |
11568 | X(3, (D, Q, Q), MIXED), \ | |
11569 | X(3, (Q, Q, D), MIXED), \ | |
11570 | X(3, (Q, D, S), MIXED), \ | |
11571 | X(3, (D, Q, S), MIXED), \ | |
11572 | X(4, (D, D, D, I), DOUBLE), \ | |
11573 | X(4, (Q, Q, Q, I), QUAD), \ | |
11574 | X(2, (F, F), SINGLE), \ | |
11575 | X(3, (F, F, F), SINGLE), \ | |
11576 | X(2, (F, I), SINGLE), \ | |
11577 | X(2, (F, D), MIXED), \ | |
11578 | X(2, (D, F), MIXED), \ | |
11579 | X(3, (F, F, I), MIXED), \ | |
11580 | X(4, (R, R, F, F), SINGLE), \ | |
11581 | X(4, (F, F, R, R), SINGLE), \ | |
11582 | X(3, (D, R, R), DOUBLE), \ | |
11583 | X(3, (R, R, D), DOUBLE), \ | |
11584 | X(2, (S, R), SINGLE), \ | |
11585 | X(2, (R, S), SINGLE), \ | |
11586 | X(2, (F, R), SINGLE), \ | |
11587 | X(2, (R, F), SINGLE) | |
11588 | ||
11589 | #define S2(A,B) NS_##A##B | |
11590 | #define S3(A,B,C) NS_##A##B##C | |
11591 | #define S4(A,B,C,D) NS_##A##B##C##D | |
11592 | ||
11593 | #define X(N, L, C) S##N L | |
11594 | ||
5287ad62 JB |
11595 | enum neon_shape |
11596 | { | |
037e8744 JB |
11597 | NEON_SHAPE_DEF, |
11598 | NS_NULL | |
5287ad62 | 11599 | }; |
b99bd4ef | 11600 | |
037e8744 JB |
11601 | #undef X |
11602 | #undef S2 | |
11603 | #undef S3 | |
11604 | #undef S4 | |
11605 | ||
11606 | enum neon_shape_class | |
11607 | { | |
11608 | SC_SINGLE, | |
11609 | SC_DOUBLE, | |
11610 | SC_QUAD, | |
11611 | SC_MIXED | |
11612 | }; | |
11613 | ||
11614 | #define X(N, L, C) SC_##C | |
11615 | ||
11616 | static enum neon_shape_class neon_shape_class[] = | |
11617 | { | |
11618 | NEON_SHAPE_DEF | |
11619 | }; | |
11620 | ||
11621 | #undef X | |
11622 | ||
11623 | enum neon_shape_el | |
11624 | { | |
11625 | SE_F, | |
11626 | SE_D, | |
11627 | SE_Q, | |
11628 | SE_I, | |
11629 | SE_S, | |
11630 | SE_R, | |
11631 | SE_L | |
11632 | }; | |
11633 | ||
11634 | /* Register widths of above. */ | |
11635 | static unsigned neon_shape_el_size[] = | |
11636 | { | |
11637 | 32, | |
11638 | 64, | |
11639 | 128, | |
11640 | 0, | |
11641 | 32, | |
11642 | 32, | |
11643 | 0 | |
11644 | }; | |
11645 | ||
11646 | struct neon_shape_info | |
11647 | { | |
11648 | unsigned els; | |
11649 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; | |
11650 | }; | |
11651 | ||
11652 | #define S2(A,B) { SE_##A, SE_##B } | |
11653 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } | |
11654 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } | |
11655 | ||
11656 | #define X(N, L, C) { N, S##N L } | |
11657 | ||
11658 | static struct neon_shape_info neon_shape_tab[] = | |
11659 | { | |
11660 | NEON_SHAPE_DEF | |
11661 | }; | |
11662 | ||
11663 | #undef X | |
11664 | #undef S2 | |
11665 | #undef S3 | |
11666 | #undef S4 | |
11667 | ||
5287ad62 JB |
11668 | /* Bit masks used in type checking given instructions. |
11669 | 'N_EQK' means the type must be the same as (or based on in some way) the key | |
11670 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is | |
11671 | set, various other bits can be set as well in order to modify the meaning of | |
11672 | the type constraint. */ | |
11673 | ||
11674 | enum neon_type_mask | |
11675 | { | |
8e79c3df CM |
11676 | N_S8 = 0x0000001, |
11677 | N_S16 = 0x0000002, | |
11678 | N_S32 = 0x0000004, | |
11679 | N_S64 = 0x0000008, | |
11680 | N_U8 = 0x0000010, | |
11681 | N_U16 = 0x0000020, | |
11682 | N_U32 = 0x0000040, | |
11683 | N_U64 = 0x0000080, | |
11684 | N_I8 = 0x0000100, | |
11685 | N_I16 = 0x0000200, | |
11686 | N_I32 = 0x0000400, | |
11687 | N_I64 = 0x0000800, | |
11688 | N_8 = 0x0001000, | |
11689 | N_16 = 0x0002000, | |
11690 | N_32 = 0x0004000, | |
11691 | N_64 = 0x0008000, | |
11692 | N_P8 = 0x0010000, | |
11693 | N_P16 = 0x0020000, | |
11694 | N_F16 = 0x0040000, | |
11695 | N_F32 = 0x0080000, | |
11696 | N_F64 = 0x0100000, | |
c921be7d NC |
11697 | N_KEY = 0x1000000, /* Key element (main type specifier). */ |
11698 | N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ | |
8e79c3df | 11699 | N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ |
c921be7d NC |
11700 | N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ |
11701 | N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ | |
11702 | N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ | |
11703 | N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ | |
11704 | N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ | |
11705 | N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ | |
11706 | N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ | |
5287ad62 | 11707 | N_UTYP = 0, |
037e8744 | 11708 | N_MAX_NONSPECIAL = N_F64 |
5287ad62 JB |
11709 | }; |
11710 | ||
dcbf9037 JB |
11711 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
11712 | ||
5287ad62 JB |
11713 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
11714 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
11715 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) | |
11716 | #define N_SUF_32 (N_SU_32 | N_F32) | |
11717 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) | |
11718 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) | |
11719 | ||
11720 | /* Pass this as the first type argument to neon_check_type to ignore types | |
11721 | altogether. */ | |
11722 | #define N_IGNORE_TYPE (N_KEY | N_EQK) | |
11723 | ||
037e8744 JB |
11724 | /* Select a "shape" for the current instruction (describing register types or |
11725 | sizes) from a list of alternatives. Return NS_NULL if the current instruction | |
11726 | doesn't fit. For non-polymorphic shapes, checking is usually done as a | |
11727 | function of operand parsing, so this function doesn't need to be called. | |
11728 | Shapes should be listed in order of decreasing length. */ | |
5287ad62 JB |
11729 | |
11730 | static enum neon_shape | |
037e8744 | 11731 | neon_select_shape (enum neon_shape shape, ...) |
5287ad62 | 11732 | { |
037e8744 JB |
11733 | va_list ap; |
11734 | enum neon_shape first_shape = shape; | |
5287ad62 JB |
11735 | |
11736 | /* Fix missing optional operands. FIXME: we don't know at this point how | |
11737 | many arguments we should have, so this makes the assumption that we have | |
11738 | > 1. This is true of all current Neon opcodes, I think, but may not be | |
11739 | true in the future. */ | |
11740 | if (!inst.operands[1].present) | |
11741 | inst.operands[1] = inst.operands[0]; | |
11742 | ||
037e8744 | 11743 | va_start (ap, shape); |
5f4273c7 | 11744 | |
21d799b5 | 11745 | for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int)) |
037e8744 JB |
11746 | { |
11747 | unsigned j; | |
11748 | int matches = 1; | |
11749 | ||
11750 | for (j = 0; j < neon_shape_tab[shape].els; j++) | |
11751 | { | |
11752 | if (!inst.operands[j].present) | |
11753 | { | |
11754 | matches = 0; | |
11755 | break; | |
11756 | } | |
11757 | ||
11758 | switch (neon_shape_tab[shape].el[j]) | |
11759 | { | |
11760 | case SE_F: | |
11761 | if (!(inst.operands[j].isreg | |
11762 | && inst.operands[j].isvec | |
11763 | && inst.operands[j].issingle | |
11764 | && !inst.operands[j].isquad)) | |
11765 | matches = 0; | |
11766 | break; | |
11767 | ||
11768 | case SE_D: | |
11769 | if (!(inst.operands[j].isreg | |
11770 | && inst.operands[j].isvec | |
11771 | && !inst.operands[j].isquad | |
11772 | && !inst.operands[j].issingle)) | |
11773 | matches = 0; | |
11774 | break; | |
11775 | ||
11776 | case SE_R: | |
11777 | if (!(inst.operands[j].isreg | |
11778 | && !inst.operands[j].isvec)) | |
11779 | matches = 0; | |
11780 | break; | |
11781 | ||
11782 | case SE_Q: | |
11783 | if (!(inst.operands[j].isreg | |
11784 | && inst.operands[j].isvec | |
11785 | && inst.operands[j].isquad | |
11786 | && !inst.operands[j].issingle)) | |
11787 | matches = 0; | |
11788 | break; | |
11789 | ||
11790 | case SE_I: | |
11791 | if (!(!inst.operands[j].isreg | |
11792 | && !inst.operands[j].isscalar)) | |
11793 | matches = 0; | |
11794 | break; | |
11795 | ||
11796 | case SE_S: | |
11797 | if (!(!inst.operands[j].isreg | |
11798 | && inst.operands[j].isscalar)) | |
11799 | matches = 0; | |
11800 | break; | |
11801 | ||
11802 | case SE_L: | |
11803 | break; | |
11804 | } | |
3fde54a2 JZ |
11805 | if (!matches) |
11806 | break; | |
037e8744 JB |
11807 | } |
11808 | if (matches) | |
5287ad62 | 11809 | break; |
037e8744 | 11810 | } |
5f4273c7 | 11811 | |
037e8744 | 11812 | va_end (ap); |
5287ad62 | 11813 | |
037e8744 JB |
11814 | if (shape == NS_NULL && first_shape != NS_NULL) |
11815 | first_error (_("invalid instruction shape")); | |
5287ad62 | 11816 | |
037e8744 JB |
11817 | return shape; |
11818 | } | |
5287ad62 | 11819 | |
037e8744 JB |
11820 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
11821 | means the Q bit should be set). */ | |
11822 | ||
11823 | static int | |
11824 | neon_quad (enum neon_shape shape) | |
11825 | { | |
11826 | return neon_shape_class[shape] == SC_QUAD; | |
5287ad62 | 11827 | } |
037e8744 | 11828 | |
5287ad62 JB |
11829 | static void |
11830 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, | |
11831 | unsigned *g_size) | |
11832 | { | |
11833 | /* Allow modification to be made to types which are constrained to be | |
11834 | based on the key element, based on bits set alongside N_EQK. */ | |
11835 | if ((typebits & N_EQK) != 0) | |
11836 | { | |
11837 | if ((typebits & N_HLF) != 0) | |
11838 | *g_size /= 2; | |
11839 | else if ((typebits & N_DBL) != 0) | |
11840 | *g_size *= 2; | |
11841 | if ((typebits & N_SGN) != 0) | |
11842 | *g_type = NT_signed; | |
11843 | else if ((typebits & N_UNS) != 0) | |
11844 | *g_type = NT_unsigned; | |
11845 | else if ((typebits & N_INT) != 0) | |
11846 | *g_type = NT_integer; | |
11847 | else if ((typebits & N_FLT) != 0) | |
11848 | *g_type = NT_float; | |
dcbf9037 JB |
11849 | else if ((typebits & N_SIZ) != 0) |
11850 | *g_type = NT_untyped; | |
5287ad62 JB |
11851 | } |
11852 | } | |
5f4273c7 | 11853 | |
5287ad62 JB |
11854 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" |
11855 | operand type, i.e. the single type specified in a Neon instruction when it | |
11856 | is the only one given. */ | |
11857 | ||
11858 | static struct neon_type_el | |
11859 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) | |
11860 | { | |
11861 | struct neon_type_el dest = *key; | |
5f4273c7 | 11862 | |
9c2799c2 | 11863 | gas_assert ((thisarg & N_EQK) != 0); |
5f4273c7 | 11864 | |
5287ad62 JB |
11865 | neon_modify_type_size (thisarg, &dest.type, &dest.size); |
11866 | ||
11867 | return dest; | |
11868 | } | |
11869 | ||
11870 | /* Convert Neon type and size into compact bitmask representation. */ | |
11871 | ||
11872 | static enum neon_type_mask | |
11873 | type_chk_of_el_type (enum neon_el_type type, unsigned size) | |
11874 | { | |
11875 | switch (type) | |
11876 | { | |
11877 | case NT_untyped: | |
11878 | switch (size) | |
11879 | { | |
11880 | case 8: return N_8; | |
11881 | case 16: return N_16; | |
11882 | case 32: return N_32; | |
11883 | case 64: return N_64; | |
11884 | default: ; | |
11885 | } | |
11886 | break; | |
11887 | ||
11888 | case NT_integer: | |
11889 | switch (size) | |
11890 | { | |
11891 | case 8: return N_I8; | |
11892 | case 16: return N_I16; | |
11893 | case 32: return N_I32; | |
11894 | case 64: return N_I64; | |
11895 | default: ; | |
11896 | } | |
11897 | break; | |
11898 | ||
11899 | case NT_float: | |
037e8744 JB |
11900 | switch (size) |
11901 | { | |
8e79c3df | 11902 | case 16: return N_F16; |
037e8744 JB |
11903 | case 32: return N_F32; |
11904 | case 64: return N_F64; | |
11905 | default: ; | |
11906 | } | |
5287ad62 JB |
11907 | break; |
11908 | ||
11909 | case NT_poly: | |
11910 | switch (size) | |
11911 | { | |
11912 | case 8: return N_P8; | |
11913 | case 16: return N_P16; | |
11914 | default: ; | |
11915 | } | |
11916 | break; | |
11917 | ||
11918 | case NT_signed: | |
11919 | switch (size) | |
11920 | { | |
11921 | case 8: return N_S8; | |
11922 | case 16: return N_S16; | |
11923 | case 32: return N_S32; | |
11924 | case 64: return N_S64; | |
11925 | default: ; | |
11926 | } | |
11927 | break; | |
11928 | ||
11929 | case NT_unsigned: | |
11930 | switch (size) | |
11931 | { | |
11932 | case 8: return N_U8; | |
11933 | case 16: return N_U16; | |
11934 | case 32: return N_U32; | |
11935 | case 64: return N_U64; | |
11936 | default: ; | |
11937 | } | |
11938 | break; | |
11939 | ||
11940 | default: ; | |
11941 | } | |
5f4273c7 | 11942 | |
5287ad62 JB |
11943 | return N_UTYP; |
11944 | } | |
11945 | ||
11946 | /* Convert compact Neon bitmask type representation to a type and size. Only | |
11947 | handles the case where a single bit is set in the mask. */ | |
11948 | ||
dcbf9037 | 11949 | static int |
5287ad62 JB |
11950 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
11951 | enum neon_type_mask mask) | |
11952 | { | |
dcbf9037 JB |
11953 | if ((mask & N_EQK) != 0) |
11954 | return FAIL; | |
11955 | ||
5287ad62 JB |
11956 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
11957 | *size = 8; | |
dcbf9037 | 11958 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) |
5287ad62 | 11959 | *size = 16; |
dcbf9037 | 11960 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
5287ad62 | 11961 | *size = 32; |
037e8744 | 11962 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) |
5287ad62 | 11963 | *size = 64; |
dcbf9037 JB |
11964 | else |
11965 | return FAIL; | |
11966 | ||
5287ad62 JB |
11967 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
11968 | *type = NT_signed; | |
dcbf9037 | 11969 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
5287ad62 | 11970 | *type = NT_unsigned; |
dcbf9037 | 11971 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
5287ad62 | 11972 | *type = NT_integer; |
dcbf9037 | 11973 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
5287ad62 | 11974 | *type = NT_untyped; |
dcbf9037 | 11975 | else if ((mask & (N_P8 | N_P16)) != 0) |
5287ad62 | 11976 | *type = NT_poly; |
037e8744 | 11977 | else if ((mask & (N_F32 | N_F64)) != 0) |
5287ad62 | 11978 | *type = NT_float; |
dcbf9037 JB |
11979 | else |
11980 | return FAIL; | |
5f4273c7 | 11981 | |
dcbf9037 | 11982 | return SUCCESS; |
5287ad62 JB |
11983 | } |
11984 | ||
11985 | /* Modify a bitmask of allowed types. This is only needed for type | |
11986 | relaxation. */ | |
11987 | ||
11988 | static unsigned | |
11989 | modify_types_allowed (unsigned allowed, unsigned mods) | |
11990 | { | |
11991 | unsigned size; | |
11992 | enum neon_el_type type; | |
11993 | unsigned destmask; | |
11994 | int i; | |
5f4273c7 | 11995 | |
5287ad62 | 11996 | destmask = 0; |
5f4273c7 | 11997 | |
5287ad62 JB |
11998 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) |
11999 | { | |
21d799b5 NC |
12000 | if (el_type_of_type_chk (&type, &size, |
12001 | (enum neon_type_mask) (allowed & i)) == SUCCESS) | |
dcbf9037 JB |
12002 | { |
12003 | neon_modify_type_size (mods, &type, &size); | |
12004 | destmask |= type_chk_of_el_type (type, size); | |
12005 | } | |
5287ad62 | 12006 | } |
5f4273c7 | 12007 | |
5287ad62 JB |
12008 | return destmask; |
12009 | } | |
12010 | ||
12011 | /* Check type and return type classification. | |
12012 | The manual states (paraphrase): If one datatype is given, it indicates the | |
12013 | type given in: | |
12014 | - the second operand, if there is one | |
12015 | - the operand, if there is no second operand | |
12016 | - the result, if there are no operands. | |
12017 | This isn't quite good enough though, so we use a concept of a "key" datatype | |
12018 | which is set on a per-instruction basis, which is the one which matters when | |
12019 | only one data type is written. | |
12020 | Note: this function has side-effects (e.g. filling in missing operands). All | |
037e8744 | 12021 | Neon instructions should call it before performing bit encoding. */ |
5287ad62 JB |
12022 | |
12023 | static struct neon_type_el | |
12024 | neon_check_type (unsigned els, enum neon_shape ns, ...) | |
12025 | { | |
12026 | va_list ap; | |
12027 | unsigned i, pass, key_el = 0; | |
12028 | unsigned types[NEON_MAX_TYPE_ELS]; | |
12029 | enum neon_el_type k_type = NT_invtype; | |
12030 | unsigned k_size = -1u; | |
12031 | struct neon_type_el badtype = {NT_invtype, -1}; | |
12032 | unsigned key_allowed = 0; | |
12033 | ||
12034 | /* Optional registers in Neon instructions are always (not) in operand 1. | |
12035 | Fill in the missing operand here, if it was omitted. */ | |
12036 | if (els > 1 && !inst.operands[1].present) | |
12037 | inst.operands[1] = inst.operands[0]; | |
12038 | ||
12039 | /* Suck up all the varargs. */ | |
12040 | va_start (ap, ns); | |
12041 | for (i = 0; i < els; i++) | |
12042 | { | |
12043 | unsigned thisarg = va_arg (ap, unsigned); | |
12044 | if (thisarg == N_IGNORE_TYPE) | |
12045 | { | |
12046 | va_end (ap); | |
12047 | return badtype; | |
12048 | } | |
12049 | types[i] = thisarg; | |
12050 | if ((thisarg & N_KEY) != 0) | |
12051 | key_el = i; | |
12052 | } | |
12053 | va_end (ap); | |
12054 | ||
dcbf9037 JB |
12055 | if (inst.vectype.elems > 0) |
12056 | for (i = 0; i < els; i++) | |
12057 | if (inst.operands[i].vectype.type != NT_invtype) | |
12058 | { | |
12059 | first_error (_("types specified in both the mnemonic and operands")); | |
12060 | return badtype; | |
12061 | } | |
12062 | ||
5287ad62 JB |
12063 | /* Duplicate inst.vectype elements here as necessary. |
12064 | FIXME: No idea if this is exactly the same as the ARM assembler, | |
12065 | particularly when an insn takes one register and one non-register | |
12066 | operand. */ | |
12067 | if (inst.vectype.elems == 1 && els > 1) | |
12068 | { | |
12069 | unsigned j; | |
12070 | inst.vectype.elems = els; | |
12071 | inst.vectype.el[key_el] = inst.vectype.el[0]; | |
12072 | for (j = 0; j < els; j++) | |
dcbf9037 JB |
12073 | if (j != key_el) |
12074 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
12075 | types[j]); | |
12076 | } | |
12077 | else if (inst.vectype.elems == 0 && els > 0) | |
12078 | { | |
12079 | unsigned j; | |
12080 | /* No types were given after the mnemonic, so look for types specified | |
12081 | after each operand. We allow some flexibility here; as long as the | |
12082 | "key" operand has a type, we can infer the others. */ | |
12083 | for (j = 0; j < els; j++) | |
12084 | if (inst.operands[j].vectype.type != NT_invtype) | |
12085 | inst.vectype.el[j] = inst.operands[j].vectype; | |
12086 | ||
12087 | if (inst.operands[key_el].vectype.type != NT_invtype) | |
5287ad62 | 12088 | { |
dcbf9037 JB |
12089 | for (j = 0; j < els; j++) |
12090 | if (inst.operands[j].vectype.type == NT_invtype) | |
12091 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
12092 | types[j]); | |
12093 | } | |
12094 | else | |
12095 | { | |
12096 | first_error (_("operand types can't be inferred")); | |
12097 | return badtype; | |
5287ad62 JB |
12098 | } |
12099 | } | |
12100 | else if (inst.vectype.elems != els) | |
12101 | { | |
dcbf9037 | 12102 | first_error (_("type specifier has the wrong number of parts")); |
5287ad62 JB |
12103 | return badtype; |
12104 | } | |
12105 | ||
12106 | for (pass = 0; pass < 2; pass++) | |
12107 | { | |
12108 | for (i = 0; i < els; i++) | |
12109 | { | |
12110 | unsigned thisarg = types[i]; | |
12111 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) | |
12112 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; | |
12113 | enum neon_el_type g_type = inst.vectype.el[i].type; | |
12114 | unsigned g_size = inst.vectype.el[i].size; | |
12115 | ||
12116 | /* Decay more-specific signed & unsigned types to sign-insensitive | |
12117 | integer types if sign-specific variants are unavailable. */ | |
12118 | if ((g_type == NT_signed || g_type == NT_unsigned) | |
12119 | && (types_allowed & N_SU_ALL) == 0) | |
12120 | g_type = NT_integer; | |
12121 | ||
12122 | /* If only untyped args are allowed, decay any more specific types to | |
12123 | them. Some instructions only care about signs for some element | |
12124 | sizes, so handle that properly. */ | |
12125 | if ((g_size == 8 && (types_allowed & N_8) != 0) | |
12126 | || (g_size == 16 && (types_allowed & N_16) != 0) | |
12127 | || (g_size == 32 && (types_allowed & N_32) != 0) | |
12128 | || (g_size == 64 && (types_allowed & N_64) != 0)) | |
12129 | g_type = NT_untyped; | |
12130 | ||
12131 | if (pass == 0) | |
12132 | { | |
12133 | if ((thisarg & N_KEY) != 0) | |
12134 | { | |
12135 | k_type = g_type; | |
12136 | k_size = g_size; | |
12137 | key_allowed = thisarg & ~N_KEY; | |
12138 | } | |
12139 | } | |
12140 | else | |
12141 | { | |
037e8744 JB |
12142 | if ((thisarg & N_VFP) != 0) |
12143 | { | |
99b253c5 NC |
12144 | enum neon_shape_el regshape; |
12145 | unsigned regwidth, match; | |
12146 | ||
12147 | /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */ | |
12148 | if (ns == NS_NULL) | |
12149 | { | |
12150 | first_error (_("invalid instruction shape")); | |
12151 | return badtype; | |
12152 | } | |
12153 | regshape = neon_shape_tab[ns].el[i]; | |
12154 | regwidth = neon_shape_el_size[regshape]; | |
037e8744 JB |
12155 | |
12156 | /* In VFP mode, operands must match register widths. If we | |
12157 | have a key operand, use its width, else use the width of | |
12158 | the current operand. */ | |
12159 | if (k_size != -1u) | |
12160 | match = k_size; | |
12161 | else | |
12162 | match = g_size; | |
12163 | ||
12164 | if (regwidth != match) | |
12165 | { | |
12166 | first_error (_("operand size must match register width")); | |
12167 | return badtype; | |
12168 | } | |
12169 | } | |
5f4273c7 | 12170 | |
5287ad62 JB |
12171 | if ((thisarg & N_EQK) == 0) |
12172 | { | |
12173 | unsigned given_type = type_chk_of_el_type (g_type, g_size); | |
12174 | ||
12175 | if ((given_type & types_allowed) == 0) | |
12176 | { | |
dcbf9037 | 12177 | first_error (_("bad type in Neon instruction")); |
5287ad62 JB |
12178 | return badtype; |
12179 | } | |
12180 | } | |
12181 | else | |
12182 | { | |
12183 | enum neon_el_type mod_k_type = k_type; | |
12184 | unsigned mod_k_size = k_size; | |
12185 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); | |
12186 | if (g_type != mod_k_type || g_size != mod_k_size) | |
12187 | { | |
dcbf9037 | 12188 | first_error (_("inconsistent types in Neon instruction")); |
5287ad62 JB |
12189 | return badtype; |
12190 | } | |
12191 | } | |
12192 | } | |
12193 | } | |
12194 | } | |
12195 | ||
12196 | return inst.vectype.el[key_el]; | |
12197 | } | |
12198 | ||
037e8744 | 12199 | /* Neon-style VFP instruction forwarding. */ |
5287ad62 | 12200 | |
037e8744 JB |
12201 | /* Thumb VFP instructions have 0xE in the condition field. */ |
12202 | ||
12203 | static void | |
12204 | do_vfp_cond_or_thumb (void) | |
5287ad62 | 12205 | { |
88714cb8 DG |
12206 | inst.is_neon = 1; |
12207 | ||
5287ad62 | 12208 | if (thumb_mode) |
037e8744 | 12209 | inst.instruction |= 0xe0000000; |
5287ad62 | 12210 | else |
037e8744 | 12211 | inst.instruction |= inst.cond << 28; |
5287ad62 JB |
12212 | } |
12213 | ||
037e8744 JB |
12214 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
12215 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, | |
12216 | etc. It is assumed that operand parsing has already been done, and that the | |
12217 | operands are in the form expected by the given opcode (this isn't necessarily | |
12218 | the same as the form in which they were parsed, hence some massaging must | |
12219 | take place before this function is called). | |
12220 | Checks current arch version against that in the looked-up opcode. */ | |
5287ad62 | 12221 | |
037e8744 JB |
12222 | static void |
12223 | do_vfp_nsyn_opcode (const char *opname) | |
5287ad62 | 12224 | { |
037e8744 | 12225 | const struct asm_opcode *opcode; |
5f4273c7 | 12226 | |
21d799b5 | 12227 | opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname); |
5287ad62 | 12228 | |
037e8744 JB |
12229 | if (!opcode) |
12230 | abort (); | |
5287ad62 | 12231 | |
037e8744 JB |
12232 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
12233 | thumb_mode ? *opcode->tvariant : *opcode->avariant), | |
12234 | _(BAD_FPU)); | |
5287ad62 | 12235 | |
88714cb8 DG |
12236 | inst.is_neon = 1; |
12237 | ||
037e8744 JB |
12238 | if (thumb_mode) |
12239 | { | |
12240 | inst.instruction = opcode->tvalue; | |
12241 | opcode->tencode (); | |
12242 | } | |
12243 | else | |
12244 | { | |
12245 | inst.instruction = (inst.cond << 28) | opcode->avalue; | |
12246 | opcode->aencode (); | |
12247 | } | |
12248 | } | |
5287ad62 JB |
12249 | |
12250 | static void | |
037e8744 | 12251 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
5287ad62 | 12252 | { |
037e8744 JB |
12253 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
12254 | ||
12255 | if (rs == NS_FFF) | |
12256 | { | |
12257 | if (is_add) | |
12258 | do_vfp_nsyn_opcode ("fadds"); | |
12259 | else | |
12260 | do_vfp_nsyn_opcode ("fsubs"); | |
12261 | } | |
12262 | else | |
12263 | { | |
12264 | if (is_add) | |
12265 | do_vfp_nsyn_opcode ("faddd"); | |
12266 | else | |
12267 | do_vfp_nsyn_opcode ("fsubd"); | |
12268 | } | |
12269 | } | |
12270 | ||
12271 | /* Check operand types to see if this is a VFP instruction, and if so call | |
12272 | PFN (). */ | |
12273 | ||
12274 | static int | |
12275 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) | |
12276 | { | |
12277 | enum neon_shape rs; | |
12278 | struct neon_type_el et; | |
12279 | ||
12280 | switch (args) | |
12281 | { | |
12282 | case 2: | |
12283 | rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
12284 | et = neon_check_type (2, rs, | |
12285 | N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
12286 | break; | |
5f4273c7 | 12287 | |
037e8744 JB |
12288 | case 3: |
12289 | rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
12290 | et = neon_check_type (3, rs, | |
12291 | N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
12292 | break; | |
12293 | ||
12294 | default: | |
12295 | abort (); | |
12296 | } | |
12297 | ||
12298 | if (et.type != NT_invtype) | |
12299 | { | |
12300 | pfn (rs); | |
12301 | return SUCCESS; | |
12302 | } | |
037e8744 | 12303 | |
99b253c5 | 12304 | inst.error = NULL; |
037e8744 JB |
12305 | return FAIL; |
12306 | } | |
12307 | ||
12308 | static void | |
12309 | do_vfp_nsyn_mla_mls (enum neon_shape rs) | |
12310 | { | |
12311 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; | |
5f4273c7 | 12312 | |
037e8744 JB |
12313 | if (rs == NS_FFF) |
12314 | { | |
12315 | if (is_mla) | |
12316 | do_vfp_nsyn_opcode ("fmacs"); | |
12317 | else | |
1ee69515 | 12318 | do_vfp_nsyn_opcode ("fnmacs"); |
037e8744 JB |
12319 | } |
12320 | else | |
12321 | { | |
12322 | if (is_mla) | |
12323 | do_vfp_nsyn_opcode ("fmacd"); | |
12324 | else | |
1ee69515 | 12325 | do_vfp_nsyn_opcode ("fnmacd"); |
037e8744 JB |
12326 | } |
12327 | } | |
12328 | ||
62f3b8c8 PB |
12329 | static void |
12330 | do_vfp_nsyn_fma_fms (enum neon_shape rs) | |
12331 | { | |
12332 | int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma; | |
12333 | ||
12334 | if (rs == NS_FFF) | |
12335 | { | |
12336 | if (is_fma) | |
12337 | do_vfp_nsyn_opcode ("ffmas"); | |
12338 | else | |
12339 | do_vfp_nsyn_opcode ("ffnmas"); | |
12340 | } | |
12341 | else | |
12342 | { | |
12343 | if (is_fma) | |
12344 | do_vfp_nsyn_opcode ("ffmad"); | |
12345 | else | |
12346 | do_vfp_nsyn_opcode ("ffnmad"); | |
12347 | } | |
12348 | } | |
12349 | ||
037e8744 JB |
12350 | static void |
12351 | do_vfp_nsyn_mul (enum neon_shape rs) | |
12352 | { | |
12353 | if (rs == NS_FFF) | |
12354 | do_vfp_nsyn_opcode ("fmuls"); | |
12355 | else | |
12356 | do_vfp_nsyn_opcode ("fmuld"); | |
12357 | } | |
12358 | ||
12359 | static void | |
12360 | do_vfp_nsyn_abs_neg (enum neon_shape rs) | |
12361 | { | |
12362 | int is_neg = (inst.instruction & 0x80) != 0; | |
12363 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); | |
12364 | ||
12365 | if (rs == NS_FF) | |
12366 | { | |
12367 | if (is_neg) | |
12368 | do_vfp_nsyn_opcode ("fnegs"); | |
12369 | else | |
12370 | do_vfp_nsyn_opcode ("fabss"); | |
12371 | } | |
12372 | else | |
12373 | { | |
12374 | if (is_neg) | |
12375 | do_vfp_nsyn_opcode ("fnegd"); | |
12376 | else | |
12377 | do_vfp_nsyn_opcode ("fabsd"); | |
12378 | } | |
12379 | } | |
12380 | ||
12381 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision | |
12382 | insns belong to Neon, and are handled elsewhere. */ | |
12383 | ||
12384 | static void | |
12385 | do_vfp_nsyn_ldm_stm (int is_dbmode) | |
12386 | { | |
12387 | int is_ldm = (inst.instruction & (1 << 20)) != 0; | |
12388 | if (is_ldm) | |
12389 | { | |
12390 | if (is_dbmode) | |
12391 | do_vfp_nsyn_opcode ("fldmdbs"); | |
12392 | else | |
12393 | do_vfp_nsyn_opcode ("fldmias"); | |
12394 | } | |
12395 | else | |
12396 | { | |
12397 | if (is_dbmode) | |
12398 | do_vfp_nsyn_opcode ("fstmdbs"); | |
12399 | else | |
12400 | do_vfp_nsyn_opcode ("fstmias"); | |
12401 | } | |
12402 | } | |
12403 | ||
037e8744 JB |
12404 | static void |
12405 | do_vfp_nsyn_sqrt (void) | |
12406 | { | |
12407 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
12408 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12409 | |
037e8744 JB |
12410 | if (rs == NS_FF) |
12411 | do_vfp_nsyn_opcode ("fsqrts"); | |
12412 | else | |
12413 | do_vfp_nsyn_opcode ("fsqrtd"); | |
12414 | } | |
12415 | ||
12416 | static void | |
12417 | do_vfp_nsyn_div (void) | |
12418 | { | |
12419 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
12420 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
12421 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12422 | |
037e8744 JB |
12423 | if (rs == NS_FFF) |
12424 | do_vfp_nsyn_opcode ("fdivs"); | |
12425 | else | |
12426 | do_vfp_nsyn_opcode ("fdivd"); | |
12427 | } | |
12428 | ||
12429 | static void | |
12430 | do_vfp_nsyn_nmul (void) | |
12431 | { | |
12432 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
12433 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
12434 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12435 | |
037e8744 JB |
12436 | if (rs == NS_FFF) |
12437 | { | |
88714cb8 | 12438 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
12439 | do_vfp_sp_dyadic (); |
12440 | } | |
12441 | else | |
12442 | { | |
88714cb8 | 12443 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
12444 | do_vfp_dp_rd_rn_rm (); |
12445 | } | |
12446 | do_vfp_cond_or_thumb (); | |
12447 | } | |
12448 | ||
12449 | static void | |
12450 | do_vfp_nsyn_cmp (void) | |
12451 | { | |
12452 | if (inst.operands[1].isreg) | |
12453 | { | |
12454 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
12455 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12456 | |
037e8744 JB |
12457 | if (rs == NS_FF) |
12458 | { | |
88714cb8 | 12459 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
12460 | do_vfp_sp_monadic (); |
12461 | } | |
12462 | else | |
12463 | { | |
88714cb8 | 12464 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
12465 | do_vfp_dp_rd_rm (); |
12466 | } | |
12467 | } | |
12468 | else | |
12469 | { | |
12470 | enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); | |
12471 | neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); | |
12472 | ||
12473 | switch (inst.instruction & 0x0fffffff) | |
12474 | { | |
12475 | case N_MNEM_vcmp: | |
12476 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; | |
12477 | break; | |
12478 | case N_MNEM_vcmpe: | |
12479 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; | |
12480 | break; | |
12481 | default: | |
12482 | abort (); | |
12483 | } | |
5f4273c7 | 12484 | |
037e8744 JB |
12485 | if (rs == NS_FI) |
12486 | { | |
88714cb8 | 12487 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
12488 | do_vfp_sp_compare_z (); |
12489 | } | |
12490 | else | |
12491 | { | |
88714cb8 | 12492 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
12493 | do_vfp_dp_rd (); |
12494 | } | |
12495 | } | |
12496 | do_vfp_cond_or_thumb (); | |
12497 | } | |
12498 | ||
12499 | static void | |
12500 | nsyn_insert_sp (void) | |
12501 | { | |
12502 | inst.operands[1] = inst.operands[0]; | |
12503 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
fdfde340 | 12504 | inst.operands[0].reg = REG_SP; |
037e8744 JB |
12505 | inst.operands[0].isreg = 1; |
12506 | inst.operands[0].writeback = 1; | |
12507 | inst.operands[0].present = 1; | |
12508 | } | |
12509 | ||
12510 | static void | |
12511 | do_vfp_nsyn_push (void) | |
12512 | { | |
12513 | nsyn_insert_sp (); | |
12514 | if (inst.operands[1].issingle) | |
12515 | do_vfp_nsyn_opcode ("fstmdbs"); | |
12516 | else | |
12517 | do_vfp_nsyn_opcode ("fstmdbd"); | |
12518 | } | |
12519 | ||
12520 | static void | |
12521 | do_vfp_nsyn_pop (void) | |
12522 | { | |
12523 | nsyn_insert_sp (); | |
12524 | if (inst.operands[1].issingle) | |
22b5b651 | 12525 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 | 12526 | else |
22b5b651 | 12527 | do_vfp_nsyn_opcode ("fldmiad"); |
037e8744 JB |
12528 | } |
12529 | ||
12530 | /* Fix up Neon data-processing instructions, ORing in the correct bits for | |
12531 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ | |
12532 | ||
88714cb8 DG |
12533 | static void |
12534 | neon_dp_fixup (struct arm_it* insn) | |
037e8744 | 12535 | { |
88714cb8 DG |
12536 | unsigned int i = insn->instruction; |
12537 | insn->is_neon = 1; | |
12538 | ||
037e8744 JB |
12539 | if (thumb_mode) |
12540 | { | |
12541 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ | |
12542 | if (i & (1 << 24)) | |
12543 | i |= 1 << 28; | |
5f4273c7 | 12544 | |
037e8744 | 12545 | i &= ~(1 << 24); |
5f4273c7 | 12546 | |
037e8744 JB |
12547 | i |= 0xef000000; |
12548 | } | |
12549 | else | |
12550 | i |= 0xf2000000; | |
5f4273c7 | 12551 | |
88714cb8 | 12552 | insn->instruction = i; |
037e8744 JB |
12553 | } |
12554 | ||
12555 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 | |
12556 | (0, 1, 2, 3). */ | |
12557 | ||
12558 | static unsigned | |
12559 | neon_logbits (unsigned x) | |
12560 | { | |
12561 | return ffs (x) - 4; | |
12562 | } | |
12563 | ||
12564 | #define LOW4(R) ((R) & 0xf) | |
12565 | #define HI1(R) (((R) >> 4) & 1) | |
12566 | ||
12567 | /* Encode insns with bit pattern: | |
12568 | ||
12569 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
12570 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | | |
5f4273c7 | 12571 | |
037e8744 JB |
12572 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a |
12573 | different meaning for some instruction. */ | |
12574 | ||
12575 | static void | |
12576 | neon_three_same (int isquad, int ubit, int size) | |
12577 | { | |
12578 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12579 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12580 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
12581 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
12582 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
12583 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
12584 | inst.instruction |= (isquad != 0) << 6; | |
12585 | inst.instruction |= (ubit != 0) << 24; | |
12586 | if (size != -1) | |
12587 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 12588 | |
88714cb8 | 12589 | neon_dp_fixup (&inst); |
037e8744 JB |
12590 | } |
12591 | ||
12592 | /* Encode instructions of the form: | |
12593 | ||
12594 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| | |
12595 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | | |
5287ad62 JB |
12596 | |
12597 | Don't write size if SIZE == -1. */ | |
12598 | ||
12599 | static void | |
12600 | neon_two_same (int qbit, int ubit, int size) | |
12601 | { | |
12602 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12603 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12604 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
12605 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
12606 | inst.instruction |= (qbit != 0) << 6; | |
12607 | inst.instruction |= (ubit != 0) << 24; | |
12608 | ||
12609 | if (size != -1) | |
12610 | inst.instruction |= neon_logbits (size) << 18; | |
12611 | ||
88714cb8 | 12612 | neon_dp_fixup (&inst); |
5287ad62 JB |
12613 | } |
12614 | ||
12615 | /* Neon instruction encoders, in approximate order of appearance. */ | |
12616 | ||
12617 | static void | |
12618 | do_neon_dyadic_i_su (void) | |
12619 | { | |
037e8744 | 12620 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12621 | struct neon_type_el et = neon_check_type (3, rs, |
12622 | N_EQK, N_EQK, N_SU_32 | N_KEY); | |
037e8744 | 12623 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
12624 | } |
12625 | ||
12626 | static void | |
12627 | do_neon_dyadic_i64_su (void) | |
12628 | { | |
037e8744 | 12629 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12630 | struct neon_type_el et = neon_check_type (3, rs, |
12631 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
037e8744 | 12632 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
12633 | } |
12634 | ||
12635 | static void | |
12636 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, | |
12637 | unsigned immbits) | |
12638 | { | |
12639 | unsigned size = et.size >> 3; | |
12640 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12641 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12642 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
12643 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
12644 | inst.instruction |= (isquad != 0) << 6; | |
12645 | inst.instruction |= immbits << 16; | |
12646 | inst.instruction |= (size >> 3) << 7; | |
12647 | inst.instruction |= (size & 0x7) << 19; | |
12648 | if (write_ubit) | |
12649 | inst.instruction |= (uval != 0) << 24; | |
12650 | ||
88714cb8 | 12651 | neon_dp_fixup (&inst); |
5287ad62 JB |
12652 | } |
12653 | ||
12654 | static void | |
12655 | do_neon_shl_imm (void) | |
12656 | { | |
12657 | if (!inst.operands[2].isreg) | |
12658 | { | |
037e8744 | 12659 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 12660 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); |
88714cb8 | 12661 | NEON_ENCODE (IMMED, inst); |
037e8744 | 12662 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); |
5287ad62 JB |
12663 | } |
12664 | else | |
12665 | { | |
037e8744 | 12666 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12667 | struct neon_type_el et = neon_check_type (3, rs, |
12668 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
12669 | unsigned int tmp; |
12670 | ||
12671 | /* VSHL/VQSHL 3-register variants have syntax such as: | |
12672 | vshl.xx Dd, Dm, Dn | |
12673 | whereas other 3-register operations encoded by neon_three_same have | |
12674 | syntax like: | |
12675 | vadd.xx Dd, Dn, Dm | |
12676 | (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg | |
12677 | here. */ | |
12678 | tmp = inst.operands[2].reg; | |
12679 | inst.operands[2].reg = inst.operands[1].reg; | |
12680 | inst.operands[1].reg = tmp; | |
88714cb8 | 12681 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 12682 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
12683 | } |
12684 | } | |
12685 | ||
12686 | static void | |
12687 | do_neon_qshl_imm (void) | |
12688 | { | |
12689 | if (!inst.operands[2].isreg) | |
12690 | { | |
037e8744 | 12691 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 12692 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
627907b7 | 12693 | |
88714cb8 | 12694 | NEON_ENCODE (IMMED, inst); |
037e8744 | 12695 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
12696 | inst.operands[2].imm); |
12697 | } | |
12698 | else | |
12699 | { | |
037e8744 | 12700 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12701 | struct neon_type_el et = neon_check_type (3, rs, |
12702 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
12703 | unsigned int tmp; |
12704 | ||
12705 | /* See note in do_neon_shl_imm. */ | |
12706 | tmp = inst.operands[2].reg; | |
12707 | inst.operands[2].reg = inst.operands[1].reg; | |
12708 | inst.operands[1].reg = tmp; | |
88714cb8 | 12709 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 12710 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
12711 | } |
12712 | } | |
12713 | ||
627907b7 JB |
12714 | static void |
12715 | do_neon_rshl (void) | |
12716 | { | |
12717 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
12718 | struct neon_type_el et = neon_check_type (3, rs, | |
12719 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
12720 | unsigned int tmp; | |
12721 | ||
12722 | tmp = inst.operands[2].reg; | |
12723 | inst.operands[2].reg = inst.operands[1].reg; | |
12724 | inst.operands[1].reg = tmp; | |
12725 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
12726 | } | |
12727 | ||
5287ad62 JB |
12728 | static int |
12729 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) | |
12730 | { | |
036dc3f7 PB |
12731 | /* Handle .I8 pseudo-instructions. */ |
12732 | if (size == 8) | |
5287ad62 | 12733 | { |
5287ad62 JB |
12734 | /* Unfortunately, this will make everything apart from zero out-of-range. |
12735 | FIXME is this the intended semantics? There doesn't seem much point in | |
12736 | accepting .I8 if so. */ | |
12737 | immediate |= immediate << 8; | |
12738 | size = 16; | |
036dc3f7 PB |
12739 | } |
12740 | ||
12741 | if (size >= 32) | |
12742 | { | |
12743 | if (immediate == (immediate & 0x000000ff)) | |
12744 | { | |
12745 | *immbits = immediate; | |
12746 | return 0x1; | |
12747 | } | |
12748 | else if (immediate == (immediate & 0x0000ff00)) | |
12749 | { | |
12750 | *immbits = immediate >> 8; | |
12751 | return 0x3; | |
12752 | } | |
12753 | else if (immediate == (immediate & 0x00ff0000)) | |
12754 | { | |
12755 | *immbits = immediate >> 16; | |
12756 | return 0x5; | |
12757 | } | |
12758 | else if (immediate == (immediate & 0xff000000)) | |
12759 | { | |
12760 | *immbits = immediate >> 24; | |
12761 | return 0x7; | |
12762 | } | |
12763 | if ((immediate & 0xffff) != (immediate >> 16)) | |
12764 | goto bad_immediate; | |
12765 | immediate &= 0xffff; | |
5287ad62 JB |
12766 | } |
12767 | ||
12768 | if (immediate == (immediate & 0x000000ff)) | |
12769 | { | |
12770 | *immbits = immediate; | |
036dc3f7 | 12771 | return 0x9; |
5287ad62 JB |
12772 | } |
12773 | else if (immediate == (immediate & 0x0000ff00)) | |
12774 | { | |
12775 | *immbits = immediate >> 8; | |
036dc3f7 | 12776 | return 0xb; |
5287ad62 JB |
12777 | } |
12778 | ||
12779 | bad_immediate: | |
dcbf9037 | 12780 | first_error (_("immediate value out of range")); |
5287ad62 JB |
12781 | return FAIL; |
12782 | } | |
12783 | ||
12784 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits | |
12785 | A, B, C, D. */ | |
12786 | ||
12787 | static int | |
12788 | neon_bits_same_in_bytes (unsigned imm) | |
12789 | { | |
12790 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) | |
12791 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) | |
12792 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) | |
12793 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); | |
12794 | } | |
12795 | ||
12796 | /* For immediate of above form, return 0bABCD. */ | |
12797 | ||
12798 | static unsigned | |
12799 | neon_squash_bits (unsigned imm) | |
12800 | { | |
12801 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) | |
12802 | | ((imm & 0x01000000) >> 21); | |
12803 | } | |
12804 | ||
136da414 | 12805 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ |
5287ad62 JB |
12806 | |
12807 | static unsigned | |
12808 | neon_qfloat_bits (unsigned imm) | |
12809 | { | |
136da414 | 12810 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); |
5287ad62 JB |
12811 | } |
12812 | ||
12813 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into | |
12814 | the instruction. *OP is passed as the initial value of the op field, and | |
12815 | may be set to a different value depending on the constant (i.e. | |
12816 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not | |
5f4273c7 | 12817 | MVN). If the immediate looks like a repeated pattern then also |
036dc3f7 | 12818 | try smaller element sizes. */ |
5287ad62 JB |
12819 | |
12820 | static int | |
c96612cc JB |
12821 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, |
12822 | unsigned *immbits, int *op, int size, | |
12823 | enum neon_el_type type) | |
5287ad62 | 12824 | { |
c96612cc JB |
12825 | /* Only permit float immediates (including 0.0/-0.0) if the operand type is |
12826 | float. */ | |
12827 | if (type == NT_float && !float_p) | |
12828 | return FAIL; | |
12829 | ||
136da414 JB |
12830 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) |
12831 | { | |
12832 | if (size != 32 || *op == 1) | |
12833 | return FAIL; | |
12834 | *immbits = neon_qfloat_bits (immlo); | |
12835 | return 0xf; | |
12836 | } | |
036dc3f7 PB |
12837 | |
12838 | if (size == 64) | |
5287ad62 | 12839 | { |
036dc3f7 PB |
12840 | if (neon_bits_same_in_bytes (immhi) |
12841 | && neon_bits_same_in_bytes (immlo)) | |
12842 | { | |
12843 | if (*op == 1) | |
12844 | return FAIL; | |
12845 | *immbits = (neon_squash_bits (immhi) << 4) | |
12846 | | neon_squash_bits (immlo); | |
12847 | *op = 1; | |
12848 | return 0xe; | |
12849 | } | |
12850 | ||
12851 | if (immhi != immlo) | |
12852 | return FAIL; | |
5287ad62 | 12853 | } |
036dc3f7 PB |
12854 | |
12855 | if (size >= 32) | |
5287ad62 | 12856 | { |
036dc3f7 PB |
12857 | if (immlo == (immlo & 0x000000ff)) |
12858 | { | |
12859 | *immbits = immlo; | |
12860 | return 0x0; | |
12861 | } | |
12862 | else if (immlo == (immlo & 0x0000ff00)) | |
12863 | { | |
12864 | *immbits = immlo >> 8; | |
12865 | return 0x2; | |
12866 | } | |
12867 | else if (immlo == (immlo & 0x00ff0000)) | |
12868 | { | |
12869 | *immbits = immlo >> 16; | |
12870 | return 0x4; | |
12871 | } | |
12872 | else if (immlo == (immlo & 0xff000000)) | |
12873 | { | |
12874 | *immbits = immlo >> 24; | |
12875 | return 0x6; | |
12876 | } | |
12877 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) | |
12878 | { | |
12879 | *immbits = (immlo >> 8) & 0xff; | |
12880 | return 0xc; | |
12881 | } | |
12882 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) | |
12883 | { | |
12884 | *immbits = (immlo >> 16) & 0xff; | |
12885 | return 0xd; | |
12886 | } | |
12887 | ||
12888 | if ((immlo & 0xffff) != (immlo >> 16)) | |
12889 | return FAIL; | |
12890 | immlo &= 0xffff; | |
5287ad62 | 12891 | } |
036dc3f7 PB |
12892 | |
12893 | if (size >= 16) | |
5287ad62 | 12894 | { |
036dc3f7 PB |
12895 | if (immlo == (immlo & 0x000000ff)) |
12896 | { | |
12897 | *immbits = immlo; | |
12898 | return 0x8; | |
12899 | } | |
12900 | else if (immlo == (immlo & 0x0000ff00)) | |
12901 | { | |
12902 | *immbits = immlo >> 8; | |
12903 | return 0xa; | |
12904 | } | |
12905 | ||
12906 | if ((immlo & 0xff) != (immlo >> 8)) | |
12907 | return FAIL; | |
12908 | immlo &= 0xff; | |
5287ad62 | 12909 | } |
036dc3f7 PB |
12910 | |
12911 | if (immlo == (immlo & 0x000000ff)) | |
5287ad62 | 12912 | { |
036dc3f7 PB |
12913 | /* Don't allow MVN with 8-bit immediate. */ |
12914 | if (*op == 1) | |
12915 | return FAIL; | |
12916 | *immbits = immlo; | |
12917 | return 0xe; | |
5287ad62 | 12918 | } |
5287ad62 JB |
12919 | |
12920 | return FAIL; | |
12921 | } | |
12922 | ||
12923 | /* Write immediate bits [7:0] to the following locations: | |
12924 | ||
12925 | |28/24|23 19|18 16|15 4|3 0| | |
12926 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| | |
12927 | ||
12928 | This function is used by VMOV/VMVN/VORR/VBIC. */ | |
12929 | ||
12930 | static void | |
12931 | neon_write_immbits (unsigned immbits) | |
12932 | { | |
12933 | inst.instruction |= immbits & 0xf; | |
12934 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; | |
12935 | inst.instruction |= ((immbits >> 7) & 0x1) << 24; | |
12936 | } | |
12937 | ||
12938 | /* Invert low-order SIZE bits of XHI:XLO. */ | |
12939 | ||
12940 | static void | |
12941 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) | |
12942 | { | |
12943 | unsigned immlo = xlo ? *xlo : 0; | |
12944 | unsigned immhi = xhi ? *xhi : 0; | |
12945 | ||
12946 | switch (size) | |
12947 | { | |
12948 | case 8: | |
12949 | immlo = (~immlo) & 0xff; | |
12950 | break; | |
12951 | ||
12952 | case 16: | |
12953 | immlo = (~immlo) & 0xffff; | |
12954 | break; | |
12955 | ||
12956 | case 64: | |
12957 | immhi = (~immhi) & 0xffffffff; | |
12958 | /* fall through. */ | |
12959 | ||
12960 | case 32: | |
12961 | immlo = (~immlo) & 0xffffffff; | |
12962 | break; | |
12963 | ||
12964 | default: | |
12965 | abort (); | |
12966 | } | |
12967 | ||
12968 | if (xlo) | |
12969 | *xlo = immlo; | |
12970 | ||
12971 | if (xhi) | |
12972 | *xhi = immhi; | |
12973 | } | |
12974 | ||
12975 | static void | |
12976 | do_neon_logic (void) | |
12977 | { | |
12978 | if (inst.operands[2].present && inst.operands[2].isreg) | |
12979 | { | |
037e8744 | 12980 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12981 | neon_check_type (3, rs, N_IGNORE_TYPE); |
12982 | /* U bit and size field were set as part of the bitmask. */ | |
88714cb8 | 12983 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 12984 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
12985 | } |
12986 | else | |
12987 | { | |
4316f0d2 DG |
12988 | const int three_ops_form = (inst.operands[2].present |
12989 | && !inst.operands[2].isreg); | |
12990 | const int immoperand = (three_ops_form ? 2 : 1); | |
12991 | enum neon_shape rs = (three_ops_form | |
12992 | ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL) | |
12993 | : neon_select_shape (NS_DI, NS_QI, NS_NULL)); | |
037e8744 JB |
12994 | struct neon_type_el et = neon_check_type (2, rs, |
12995 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
21d799b5 | 12996 | enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff; |
5287ad62 JB |
12997 | unsigned immbits; |
12998 | int cmode; | |
5f4273c7 | 12999 | |
5287ad62 JB |
13000 | if (et.type == NT_invtype) |
13001 | return; | |
5f4273c7 | 13002 | |
4316f0d2 DG |
13003 | if (three_ops_form) |
13004 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
13005 | _("first and second operands shall be the same register")); | |
13006 | ||
88714cb8 | 13007 | NEON_ENCODE (IMMED, inst); |
5287ad62 | 13008 | |
4316f0d2 | 13009 | immbits = inst.operands[immoperand].imm; |
036dc3f7 PB |
13010 | if (et.size == 64) |
13011 | { | |
13012 | /* .i64 is a pseudo-op, so the immediate must be a repeating | |
13013 | pattern. */ | |
4316f0d2 DG |
13014 | if (immbits != (inst.operands[immoperand].regisimm ? |
13015 | inst.operands[immoperand].reg : 0)) | |
036dc3f7 PB |
13016 | { |
13017 | /* Set immbits to an invalid constant. */ | |
13018 | immbits = 0xdeadbeef; | |
13019 | } | |
13020 | } | |
13021 | ||
5287ad62 JB |
13022 | switch (opcode) |
13023 | { | |
13024 | case N_MNEM_vbic: | |
036dc3f7 | 13025 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 13026 | break; |
5f4273c7 | 13027 | |
5287ad62 | 13028 | case N_MNEM_vorr: |
036dc3f7 | 13029 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 13030 | break; |
5f4273c7 | 13031 | |
5287ad62 JB |
13032 | case N_MNEM_vand: |
13033 | /* Pseudo-instruction for VBIC. */ | |
5287ad62 JB |
13034 | neon_invert_size (&immbits, 0, et.size); |
13035 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
13036 | break; | |
5f4273c7 | 13037 | |
5287ad62 JB |
13038 | case N_MNEM_vorn: |
13039 | /* Pseudo-instruction for VORR. */ | |
5287ad62 JB |
13040 | neon_invert_size (&immbits, 0, et.size); |
13041 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
13042 | break; | |
5f4273c7 | 13043 | |
5287ad62 JB |
13044 | default: |
13045 | abort (); | |
13046 | } | |
13047 | ||
13048 | if (cmode == FAIL) | |
13049 | return; | |
13050 | ||
037e8744 | 13051 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13052 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13053 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13054 | inst.instruction |= cmode << 8; | |
13055 | neon_write_immbits (immbits); | |
5f4273c7 | 13056 | |
88714cb8 | 13057 | neon_dp_fixup (&inst); |
5287ad62 JB |
13058 | } |
13059 | } | |
13060 | ||
13061 | static void | |
13062 | do_neon_bitfield (void) | |
13063 | { | |
037e8744 | 13064 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 13065 | neon_check_type (3, rs, N_IGNORE_TYPE); |
037e8744 | 13066 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13067 | } |
13068 | ||
13069 | static void | |
dcbf9037 JB |
13070 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
13071 | unsigned destbits) | |
5287ad62 | 13072 | { |
037e8744 | 13073 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 JB |
13074 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
13075 | types | N_KEY); | |
5287ad62 JB |
13076 | if (et.type == NT_float) |
13077 | { | |
88714cb8 | 13078 | NEON_ENCODE (FLOAT, inst); |
037e8744 | 13079 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13080 | } |
13081 | else | |
13082 | { | |
88714cb8 | 13083 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13084 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); |
5287ad62 JB |
13085 | } |
13086 | } | |
13087 | ||
13088 | static void | |
13089 | do_neon_dyadic_if_su (void) | |
13090 | { | |
dcbf9037 | 13091 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
13092 | } |
13093 | ||
13094 | static void | |
13095 | do_neon_dyadic_if_su_d (void) | |
13096 | { | |
13097 | /* This version only allow D registers, but that constraint is enforced during | |
13098 | operand parsing so we don't need to do anything extra here. */ | |
dcbf9037 | 13099 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
13100 | } |
13101 | ||
5287ad62 JB |
13102 | static void |
13103 | do_neon_dyadic_if_i_d (void) | |
13104 | { | |
428e3f1f PB |
13105 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
13106 | affected if we specify unsigned args. */ | |
13107 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
5287ad62 JB |
13108 | } |
13109 | ||
037e8744 JB |
13110 | enum vfp_or_neon_is_neon_bits |
13111 | { | |
13112 | NEON_CHECK_CC = 1, | |
13113 | NEON_CHECK_ARCH = 2 | |
13114 | }; | |
13115 | ||
13116 | /* Call this function if an instruction which may have belonged to the VFP or | |
13117 | Neon instruction sets, but turned out to be a Neon instruction (due to the | |
13118 | operand types involved, etc.). We have to check and/or fix-up a couple of | |
13119 | things: | |
13120 | ||
13121 | - Make sure the user hasn't attempted to make a Neon instruction | |
13122 | conditional. | |
13123 | - Alter the value in the condition code field if necessary. | |
13124 | - Make sure that the arch supports Neon instructions. | |
13125 | ||
13126 | Which of these operations take place depends on bits from enum | |
13127 | vfp_or_neon_is_neon_bits. | |
13128 | ||
13129 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the | |
13130 | current instruction's condition is COND_ALWAYS, the condition field is | |
13131 | changed to inst.uncond_value. This is necessary because instructions shared | |
13132 | between VFP and Neon may be conditional for the VFP variants only, and the | |
13133 | unconditional Neon version must have, e.g., 0xF in the condition field. */ | |
13134 | ||
13135 | static int | |
13136 | vfp_or_neon_is_neon (unsigned check) | |
13137 | { | |
13138 | /* Conditions are always legal in Thumb mode (IT blocks). */ | |
13139 | if (!thumb_mode && (check & NEON_CHECK_CC)) | |
13140 | { | |
13141 | if (inst.cond != COND_ALWAYS) | |
13142 | { | |
13143 | first_error (_(BAD_COND)); | |
13144 | return FAIL; | |
13145 | } | |
13146 | if (inst.uncond_value != -1) | |
13147 | inst.instruction |= inst.uncond_value << 28; | |
13148 | } | |
5f4273c7 | 13149 | |
037e8744 JB |
13150 | if ((check & NEON_CHECK_ARCH) |
13151 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) | |
13152 | { | |
13153 | first_error (_(BAD_FPU)); | |
13154 | return FAIL; | |
13155 | } | |
5f4273c7 | 13156 | |
037e8744 JB |
13157 | return SUCCESS; |
13158 | } | |
13159 | ||
5287ad62 JB |
13160 | static void |
13161 | do_neon_addsub_if_i (void) | |
13162 | { | |
037e8744 JB |
13163 | if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) |
13164 | return; | |
13165 | ||
13166 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13167 | return; | |
13168 | ||
5287ad62 JB |
13169 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
13170 | affected if we specify unsigned args. */ | |
dcbf9037 | 13171 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
5287ad62 JB |
13172 | } |
13173 | ||
13174 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the | |
13175 | result to be: | |
13176 | V<op> A,B (A is operand 0, B is operand 2) | |
13177 | to mean: | |
13178 | V<op> A,B,A | |
13179 | not: | |
13180 | V<op> A,B,B | |
13181 | so handle that case specially. */ | |
13182 | ||
13183 | static void | |
13184 | neon_exchange_operands (void) | |
13185 | { | |
13186 | void *scratch = alloca (sizeof (inst.operands[0])); | |
13187 | if (inst.operands[1].present) | |
13188 | { | |
13189 | /* Swap operands[1] and operands[2]. */ | |
13190 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); | |
13191 | inst.operands[1] = inst.operands[2]; | |
13192 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); | |
13193 | } | |
13194 | else | |
13195 | { | |
13196 | inst.operands[1] = inst.operands[2]; | |
13197 | inst.operands[2] = inst.operands[0]; | |
13198 | } | |
13199 | } | |
13200 | ||
13201 | static void | |
13202 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) | |
13203 | { | |
13204 | if (inst.operands[2].isreg) | |
13205 | { | |
13206 | if (invert) | |
13207 | neon_exchange_operands (); | |
dcbf9037 | 13208 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
5287ad62 JB |
13209 | } |
13210 | else | |
13211 | { | |
037e8744 | 13212 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
dcbf9037 JB |
13213 | struct neon_type_el et = neon_check_type (2, rs, |
13214 | N_EQK | N_SIZ, immtypes | N_KEY); | |
5287ad62 | 13215 | |
88714cb8 | 13216 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
13217 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13218 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13219 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13220 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 13221 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13222 | inst.instruction |= (et.type == NT_float) << 10; |
13223 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 13224 | |
88714cb8 | 13225 | neon_dp_fixup (&inst); |
5287ad62 JB |
13226 | } |
13227 | } | |
13228 | ||
13229 | static void | |
13230 | do_neon_cmp (void) | |
13231 | { | |
13232 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); | |
13233 | } | |
13234 | ||
13235 | static void | |
13236 | do_neon_cmp_inv (void) | |
13237 | { | |
13238 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); | |
13239 | } | |
13240 | ||
13241 | static void | |
13242 | do_neon_ceq (void) | |
13243 | { | |
13244 | neon_compare (N_IF_32, N_IF_32, FALSE); | |
13245 | } | |
13246 | ||
13247 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit | |
13248 | scalars, which are encoded in 5 bits, M : Rm. | |
13249 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in | |
13250 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the | |
13251 | index in M. */ | |
13252 | ||
13253 | static unsigned | |
13254 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) | |
13255 | { | |
dcbf9037 JB |
13256 | unsigned regno = NEON_SCALAR_REG (scalar); |
13257 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
5287ad62 JB |
13258 | |
13259 | switch (elsize) | |
13260 | { | |
13261 | case 16: | |
13262 | if (regno > 7 || elno > 3) | |
13263 | goto bad_scalar; | |
13264 | return regno | (elno << 3); | |
5f4273c7 | 13265 | |
5287ad62 JB |
13266 | case 32: |
13267 | if (regno > 15 || elno > 1) | |
13268 | goto bad_scalar; | |
13269 | return regno | (elno << 4); | |
13270 | ||
13271 | default: | |
13272 | bad_scalar: | |
dcbf9037 | 13273 | first_error (_("scalar out of range for multiply instruction")); |
5287ad62 JB |
13274 | } |
13275 | ||
13276 | return 0; | |
13277 | } | |
13278 | ||
13279 | /* Encode multiply / multiply-accumulate scalar instructions. */ | |
13280 | ||
13281 | static void | |
13282 | neon_mul_mac (struct neon_type_el et, int ubit) | |
13283 | { | |
dcbf9037 JB |
13284 | unsigned scalar; |
13285 | ||
13286 | /* Give a more helpful error message if we have an invalid type. */ | |
13287 | if (et.type == NT_invtype) | |
13288 | return; | |
5f4273c7 | 13289 | |
dcbf9037 | 13290 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); |
5287ad62 JB |
13291 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13292 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13293 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
13294 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
13295 | inst.instruction |= LOW4 (scalar); | |
13296 | inst.instruction |= HI1 (scalar) << 5; | |
13297 | inst.instruction |= (et.type == NT_float) << 8; | |
13298 | inst.instruction |= neon_logbits (et.size) << 20; | |
13299 | inst.instruction |= (ubit != 0) << 24; | |
13300 | ||
88714cb8 | 13301 | neon_dp_fixup (&inst); |
5287ad62 JB |
13302 | } |
13303 | ||
13304 | static void | |
13305 | do_neon_mac_maybe_scalar (void) | |
13306 | { | |
037e8744 JB |
13307 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
13308 | return; | |
13309 | ||
13310 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13311 | return; | |
13312 | ||
5287ad62 JB |
13313 | if (inst.operands[2].isscalar) |
13314 | { | |
037e8744 | 13315 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
13316 | struct neon_type_el et = neon_check_type (3, rs, |
13317 | N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); | |
88714cb8 | 13318 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 13319 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
13320 | } |
13321 | else | |
428e3f1f PB |
13322 | { |
13323 | /* The "untyped" case can't happen. Do this to stop the "U" bit being | |
13324 | affected if we specify unsigned args. */ | |
13325 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
13326 | } | |
5287ad62 JB |
13327 | } |
13328 | ||
62f3b8c8 PB |
13329 | static void |
13330 | do_neon_fmac (void) | |
13331 | { | |
13332 | if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS) | |
13333 | return; | |
13334 | ||
13335 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13336 | return; | |
13337 | ||
13338 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
13339 | } | |
13340 | ||
5287ad62 JB |
13341 | static void |
13342 | do_neon_tst (void) | |
13343 | { | |
037e8744 | 13344 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13345 | struct neon_type_el et = neon_check_type (3, rs, |
13346 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
037e8744 | 13347 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
13348 | } |
13349 | ||
13350 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the | |
13351 | same types as the MAC equivalents. The polynomial type for this instruction | |
13352 | is encoded the same as the integer type. */ | |
13353 | ||
13354 | static void | |
13355 | do_neon_mul (void) | |
13356 | { | |
037e8744 JB |
13357 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
13358 | return; | |
13359 | ||
13360 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13361 | return; | |
13362 | ||
5287ad62 JB |
13363 | if (inst.operands[2].isscalar) |
13364 | do_neon_mac_maybe_scalar (); | |
13365 | else | |
dcbf9037 | 13366 | neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); |
5287ad62 JB |
13367 | } |
13368 | ||
13369 | static void | |
13370 | do_neon_qdmulh (void) | |
13371 | { | |
13372 | if (inst.operands[2].isscalar) | |
13373 | { | |
037e8744 | 13374 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
13375 | struct neon_type_el et = neon_check_type (3, rs, |
13376 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
88714cb8 | 13377 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 13378 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
13379 | } |
13380 | else | |
13381 | { | |
037e8744 | 13382 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13383 | struct neon_type_el et = neon_check_type (3, rs, |
13384 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
88714cb8 | 13385 | NEON_ENCODE (INTEGER, inst); |
5287ad62 | 13386 | /* The U bit (rounding) comes from bit mask. */ |
037e8744 | 13387 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
13388 | } |
13389 | } | |
13390 | ||
13391 | static void | |
13392 | do_neon_fcmp_absolute (void) | |
13393 | { | |
037e8744 | 13394 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13395 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
13396 | /* Size field comes from bit mask. */ | |
037e8744 | 13397 | neon_three_same (neon_quad (rs), 1, -1); |
5287ad62 JB |
13398 | } |
13399 | ||
13400 | static void | |
13401 | do_neon_fcmp_absolute_inv (void) | |
13402 | { | |
13403 | neon_exchange_operands (); | |
13404 | do_neon_fcmp_absolute (); | |
13405 | } | |
13406 | ||
13407 | static void | |
13408 | do_neon_step (void) | |
13409 | { | |
037e8744 | 13410 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 13411 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
037e8744 | 13412 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13413 | } |
13414 | ||
13415 | static void | |
13416 | do_neon_abs_neg (void) | |
13417 | { | |
037e8744 JB |
13418 | enum neon_shape rs; |
13419 | struct neon_type_el et; | |
5f4273c7 | 13420 | |
037e8744 JB |
13421 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) |
13422 | return; | |
13423 | ||
13424 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13425 | return; | |
13426 | ||
13427 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
13428 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); | |
5f4273c7 | 13429 | |
5287ad62 JB |
13430 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13431 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13432 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13433 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 13434 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13435 | inst.instruction |= (et.type == NT_float) << 10; |
13436 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 13437 | |
88714cb8 | 13438 | neon_dp_fixup (&inst); |
5287ad62 JB |
13439 | } |
13440 | ||
13441 | static void | |
13442 | do_neon_sli (void) | |
13443 | { | |
037e8744 | 13444 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
13445 | struct neon_type_el et = neon_check_type (2, rs, |
13446 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
13447 | int imm = inst.operands[2].imm; | |
13448 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
13449 | _("immediate out of range for insert")); | |
037e8744 | 13450 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
13451 | } |
13452 | ||
13453 | static void | |
13454 | do_neon_sri (void) | |
13455 | { | |
037e8744 | 13456 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
13457 | struct neon_type_el et = neon_check_type (2, rs, |
13458 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
13459 | int imm = inst.operands[2].imm; | |
13460 | constraint (imm < 1 || (unsigned)imm > et.size, | |
13461 | _("immediate out of range for insert")); | |
037e8744 | 13462 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
5287ad62 JB |
13463 | } |
13464 | ||
13465 | static void | |
13466 | do_neon_qshlu_imm (void) | |
13467 | { | |
037e8744 | 13468 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
13469 | struct neon_type_el et = neon_check_type (2, rs, |
13470 | N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); | |
13471 | int imm = inst.operands[2].imm; | |
13472 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
13473 | _("immediate out of range for shift")); | |
13474 | /* Only encodes the 'U present' variant of the instruction. | |
13475 | In this case, signed types have OP (bit 8) set to 0. | |
13476 | Unsigned types have OP set to 1. */ | |
13477 | inst.instruction |= (et.type == NT_unsigned) << 8; | |
13478 | /* The rest of the bits are the same as other immediate shifts. */ | |
037e8744 | 13479 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
13480 | } |
13481 | ||
13482 | static void | |
13483 | do_neon_qmovn (void) | |
13484 | { | |
13485 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
13486 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
13487 | /* Saturating move where operands can be signed or unsigned, and the | |
13488 | destination has the same signedness. */ | |
88714cb8 | 13489 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13490 | if (et.type == NT_unsigned) |
13491 | inst.instruction |= 0xc0; | |
13492 | else | |
13493 | inst.instruction |= 0x80; | |
13494 | neon_two_same (0, 1, et.size / 2); | |
13495 | } | |
13496 | ||
13497 | static void | |
13498 | do_neon_qmovun (void) | |
13499 | { | |
13500 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
13501 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
13502 | /* Saturating move with unsigned results. Operands must be signed. */ | |
88714cb8 | 13503 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13504 | neon_two_same (0, 1, et.size / 2); |
13505 | } | |
13506 | ||
13507 | static void | |
13508 | do_neon_rshift_sat_narrow (void) | |
13509 | { | |
13510 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
13511 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
13512 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
13513 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
13514 | int imm = inst.operands[2].imm; | |
13515 | /* This gets the bounds check, size encoding and immediate bits calculation | |
13516 | right. */ | |
13517 | et.size /= 2; | |
5f4273c7 | 13518 | |
5287ad62 JB |
13519 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for |
13520 | VQMOVN.I<size> <Dd>, <Qm>. */ | |
13521 | if (imm == 0) | |
13522 | { | |
13523 | inst.operands[2].present = 0; | |
13524 | inst.instruction = N_MNEM_vqmovn; | |
13525 | do_neon_qmovn (); | |
13526 | return; | |
13527 | } | |
5f4273c7 | 13528 | |
5287ad62 JB |
13529 | constraint (imm < 1 || (unsigned)imm > et.size, |
13530 | _("immediate out of range")); | |
13531 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); | |
13532 | } | |
13533 | ||
13534 | static void | |
13535 | do_neon_rshift_sat_narrow_u (void) | |
13536 | { | |
13537 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
13538 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
13539 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
13540 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
13541 | int imm = inst.operands[2].imm; | |
13542 | /* This gets the bounds check, size encoding and immediate bits calculation | |
13543 | right. */ | |
13544 | et.size /= 2; | |
13545 | ||
13546 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
13547 | VQMOVUN.I<size> <Dd>, <Qm>. */ | |
13548 | if (imm == 0) | |
13549 | { | |
13550 | inst.operands[2].present = 0; | |
13551 | inst.instruction = N_MNEM_vqmovun; | |
13552 | do_neon_qmovun (); | |
13553 | return; | |
13554 | } | |
13555 | ||
13556 | constraint (imm < 1 || (unsigned)imm > et.size, | |
13557 | _("immediate out of range")); | |
13558 | /* FIXME: The manual is kind of unclear about what value U should have in | |
13559 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it | |
13560 | must be 1. */ | |
13561 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); | |
13562 | } | |
13563 | ||
13564 | static void | |
13565 | do_neon_movn (void) | |
13566 | { | |
13567 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
13568 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
88714cb8 | 13569 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13570 | neon_two_same (0, 1, et.size / 2); |
13571 | } | |
13572 | ||
13573 | static void | |
13574 | do_neon_rshift_narrow (void) | |
13575 | { | |
13576 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
13577 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
13578 | int imm = inst.operands[2].imm; | |
13579 | /* This gets the bounds check, size encoding and immediate bits calculation | |
13580 | right. */ | |
13581 | et.size /= 2; | |
5f4273c7 | 13582 | |
5287ad62 JB |
13583 | /* If immediate is zero then we are a pseudo-instruction for |
13584 | VMOVN.I<size> <Dd>, <Qm> */ | |
13585 | if (imm == 0) | |
13586 | { | |
13587 | inst.operands[2].present = 0; | |
13588 | inst.instruction = N_MNEM_vmovn; | |
13589 | do_neon_movn (); | |
13590 | return; | |
13591 | } | |
5f4273c7 | 13592 | |
5287ad62 JB |
13593 | constraint (imm < 1 || (unsigned)imm > et.size, |
13594 | _("immediate out of range for narrowing operation")); | |
13595 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); | |
13596 | } | |
13597 | ||
13598 | static void | |
13599 | do_neon_shll (void) | |
13600 | { | |
13601 | /* FIXME: Type checking when lengthening. */ | |
13602 | struct neon_type_el et = neon_check_type (2, NS_QDI, | |
13603 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); | |
13604 | unsigned imm = inst.operands[2].imm; | |
13605 | ||
13606 | if (imm == et.size) | |
13607 | { | |
13608 | /* Maximum shift variant. */ | |
88714cb8 | 13609 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13610 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13611 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13612 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13613 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13614 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 13615 | |
88714cb8 | 13616 | neon_dp_fixup (&inst); |
5287ad62 JB |
13617 | } |
13618 | else | |
13619 | { | |
13620 | /* A more-specific type check for non-max versions. */ | |
13621 | et = neon_check_type (2, NS_QDI, | |
13622 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
88714cb8 | 13623 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
13624 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); |
13625 | } | |
13626 | } | |
13627 | ||
037e8744 | 13628 | /* Check the various types for the VCVT instruction, and return which version |
5287ad62 JB |
13629 | the current instruction is. */ |
13630 | ||
13631 | static int | |
13632 | neon_cvt_flavour (enum neon_shape rs) | |
13633 | { | |
037e8744 JB |
13634 | #define CVT_VAR(C,X,Y) \ |
13635 | et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ | |
13636 | if (et.type != NT_invtype) \ | |
13637 | { \ | |
13638 | inst.error = NULL; \ | |
13639 | return (C); \ | |
5287ad62 JB |
13640 | } |
13641 | struct neon_type_el et; | |
037e8744 JB |
13642 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
13643 | || rs == NS_FF) ? N_VFP : 0; | |
13644 | /* The instruction versions which take an immediate take one register | |
13645 | argument, which is extended to the width of the full register. Thus the | |
13646 | "source" and "destination" registers must have the same width. Hack that | |
13647 | here by making the size equal to the key (wider, in this case) operand. */ | |
13648 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; | |
5f4273c7 | 13649 | |
5287ad62 JB |
13650 | CVT_VAR (0, N_S32, N_F32); |
13651 | CVT_VAR (1, N_U32, N_F32); | |
13652 | CVT_VAR (2, N_F32, N_S32); | |
13653 | CVT_VAR (3, N_F32, N_U32); | |
8e79c3df CM |
13654 | /* Half-precision conversions. */ |
13655 | CVT_VAR (4, N_F32, N_F16); | |
13656 | CVT_VAR (5, N_F16, N_F32); | |
5f4273c7 | 13657 | |
037e8744 | 13658 | whole_reg = N_VFP; |
5f4273c7 | 13659 | |
037e8744 | 13660 | /* VFP instructions. */ |
8e79c3df CM |
13661 | CVT_VAR (6, N_F32, N_F64); |
13662 | CVT_VAR (7, N_F64, N_F32); | |
13663 | CVT_VAR (8, N_S32, N_F64 | key); | |
13664 | CVT_VAR (9, N_U32, N_F64 | key); | |
13665 | CVT_VAR (10, N_F64 | key, N_S32); | |
13666 | CVT_VAR (11, N_F64 | key, N_U32); | |
037e8744 | 13667 | /* VFP instructions with bitshift. */ |
8e79c3df CM |
13668 | CVT_VAR (12, N_F32 | key, N_S16); |
13669 | CVT_VAR (13, N_F32 | key, N_U16); | |
13670 | CVT_VAR (14, N_F64 | key, N_S16); | |
13671 | CVT_VAR (15, N_F64 | key, N_U16); | |
13672 | CVT_VAR (16, N_S16, N_F32 | key); | |
13673 | CVT_VAR (17, N_U16, N_F32 | key); | |
13674 | CVT_VAR (18, N_S16, N_F64 | key); | |
13675 | CVT_VAR (19, N_U16, N_F64 | key); | |
5f4273c7 | 13676 | |
5287ad62 JB |
13677 | return -1; |
13678 | #undef CVT_VAR | |
13679 | } | |
13680 | ||
037e8744 JB |
13681 | /* Neon-syntax VFP conversions. */ |
13682 | ||
5287ad62 | 13683 | static void |
037e8744 | 13684 | do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) |
5287ad62 | 13685 | { |
037e8744 | 13686 | const char *opname = 0; |
5f4273c7 | 13687 | |
037e8744 | 13688 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) |
5287ad62 | 13689 | { |
037e8744 JB |
13690 | /* Conversions with immediate bitshift. */ |
13691 | const char *enc[] = | |
13692 | { | |
13693 | "ftosls", | |
13694 | "ftouls", | |
13695 | "fsltos", | |
13696 | "fultos", | |
13697 | NULL, | |
13698 | NULL, | |
8e79c3df CM |
13699 | NULL, |
13700 | NULL, | |
037e8744 JB |
13701 | "ftosld", |
13702 | "ftould", | |
13703 | "fsltod", | |
13704 | "fultod", | |
13705 | "fshtos", | |
13706 | "fuhtos", | |
13707 | "fshtod", | |
13708 | "fuhtod", | |
13709 | "ftoshs", | |
13710 | "ftouhs", | |
13711 | "ftoshd", | |
13712 | "ftouhd" | |
13713 | }; | |
13714 | ||
13715 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
13716 | { | |
13717 | opname = enc[flavour]; | |
13718 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
13719 | _("operands 0 and 1 must be the same register")); | |
13720 | inst.operands[1] = inst.operands[2]; | |
13721 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); | |
13722 | } | |
5287ad62 JB |
13723 | } |
13724 | else | |
13725 | { | |
037e8744 JB |
13726 | /* Conversions without bitshift. */ |
13727 | const char *enc[] = | |
13728 | { | |
13729 | "ftosis", | |
13730 | "ftouis", | |
13731 | "fsitos", | |
13732 | "fuitos", | |
8e79c3df CM |
13733 | "NULL", |
13734 | "NULL", | |
037e8744 JB |
13735 | "fcvtsd", |
13736 | "fcvtds", | |
13737 | "ftosid", | |
13738 | "ftouid", | |
13739 | "fsitod", | |
13740 | "fuitod" | |
13741 | }; | |
13742 | ||
13743 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
13744 | opname = enc[flavour]; | |
13745 | } | |
13746 | ||
13747 | if (opname) | |
13748 | do_vfp_nsyn_opcode (opname); | |
13749 | } | |
13750 | ||
13751 | static void | |
13752 | do_vfp_nsyn_cvtz (void) | |
13753 | { | |
13754 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); | |
13755 | int flavour = neon_cvt_flavour (rs); | |
13756 | const char *enc[] = | |
13757 | { | |
13758 | "ftosizs", | |
13759 | "ftouizs", | |
13760 | NULL, | |
13761 | NULL, | |
13762 | NULL, | |
13763 | NULL, | |
8e79c3df CM |
13764 | NULL, |
13765 | NULL, | |
037e8744 JB |
13766 | "ftosizd", |
13767 | "ftouizd" | |
13768 | }; | |
13769 | ||
13770 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) | |
13771 | do_vfp_nsyn_opcode (enc[flavour]); | |
13772 | } | |
f31fef98 | 13773 | |
037e8744 | 13774 | static void |
e3e535bc | 13775 | do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED) |
037e8744 JB |
13776 | { |
13777 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, | |
8e79c3df | 13778 | NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL); |
037e8744 JB |
13779 | int flavour = neon_cvt_flavour (rs); |
13780 | ||
e3e535bc NC |
13781 | /* PR11109: Handle round-to-zero for VCVT conversions. */ |
13782 | if (round_to_zero | |
13783 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2) | |
13784 | && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9) | |
13785 | && (rs == NS_FD || rs == NS_FF)) | |
13786 | { | |
13787 | do_vfp_nsyn_cvtz (); | |
13788 | return; | |
13789 | } | |
13790 | ||
037e8744 | 13791 | /* VFP rather than Neon conversions. */ |
8e79c3df | 13792 | if (flavour >= 6) |
037e8744 JB |
13793 | { |
13794 | do_vfp_nsyn_cvt (rs, flavour); | |
13795 | return; | |
13796 | } | |
13797 | ||
13798 | switch (rs) | |
13799 | { | |
13800 | case NS_DDI: | |
13801 | case NS_QQI: | |
13802 | { | |
35997600 NC |
13803 | unsigned immbits; |
13804 | unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; | |
13805 | ||
037e8744 JB |
13806 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
13807 | return; | |
13808 | ||
13809 | /* Fixed-point conversion with #0 immediate is encoded as an | |
13810 | integer conversion. */ | |
13811 | if (inst.operands[2].present && inst.operands[2].imm == 0) | |
13812 | goto int_encode; | |
35997600 | 13813 | immbits = 32 - inst.operands[2].imm; |
88714cb8 | 13814 | NEON_ENCODE (IMMED, inst); |
037e8744 JB |
13815 | if (flavour != -1) |
13816 | inst.instruction |= enctab[flavour]; | |
13817 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13818 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13819 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13820 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13821 | inst.instruction |= neon_quad (rs) << 6; | |
13822 | inst.instruction |= 1 << 21; | |
13823 | inst.instruction |= immbits << 16; | |
13824 | ||
88714cb8 | 13825 | neon_dp_fixup (&inst); |
037e8744 JB |
13826 | } |
13827 | break; | |
13828 | ||
13829 | case NS_DD: | |
13830 | case NS_QQ: | |
13831 | int_encode: | |
13832 | { | |
13833 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; | |
13834 | ||
88714cb8 | 13835 | NEON_ENCODE (INTEGER, inst); |
037e8744 JB |
13836 | |
13837 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13838 | return; | |
13839 | ||
13840 | if (flavour != -1) | |
13841 | inst.instruction |= enctab[flavour]; | |
13842 | ||
13843 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13844 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13845 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13846 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13847 | inst.instruction |= neon_quad (rs) << 6; | |
13848 | inst.instruction |= 2 << 18; | |
13849 | ||
88714cb8 | 13850 | neon_dp_fixup (&inst); |
037e8744 JB |
13851 | } |
13852 | break; | |
13853 | ||
8e79c3df CM |
13854 | /* Half-precision conversions for Advanced SIMD -- neon. */ |
13855 | case NS_QD: | |
13856 | case NS_DQ: | |
13857 | ||
13858 | if ((rs == NS_DQ) | |
13859 | && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) | |
13860 | { | |
13861 | as_bad (_("operand size must match register width")); | |
13862 | break; | |
13863 | } | |
13864 | ||
13865 | if ((rs == NS_QD) | |
13866 | && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) | |
13867 | { | |
13868 | as_bad (_("operand size must match register width")); | |
13869 | break; | |
13870 | } | |
13871 | ||
13872 | if (rs == NS_DQ) | |
13873 | inst.instruction = 0x3b60600; | |
13874 | else | |
13875 | inst.instruction = 0x3b60700; | |
13876 | ||
13877 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13878 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13879 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13880 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
88714cb8 | 13881 | neon_dp_fixup (&inst); |
8e79c3df CM |
13882 | break; |
13883 | ||
037e8744 JB |
13884 | default: |
13885 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ | |
13886 | do_vfp_nsyn_cvt (rs, flavour); | |
5287ad62 | 13887 | } |
5287ad62 JB |
13888 | } |
13889 | ||
e3e535bc NC |
13890 | static void |
13891 | do_neon_cvtr (void) | |
13892 | { | |
13893 | do_neon_cvt_1 (FALSE); | |
13894 | } | |
13895 | ||
13896 | static void | |
13897 | do_neon_cvt (void) | |
13898 | { | |
13899 | do_neon_cvt_1 (TRUE); | |
13900 | } | |
13901 | ||
8e79c3df CM |
13902 | static void |
13903 | do_neon_cvtb (void) | |
13904 | { | |
13905 | inst.instruction = 0xeb20a40; | |
13906 | ||
13907 | /* The sizes are attached to the mnemonic. */ | |
13908 | if (inst.vectype.el[0].type != NT_invtype | |
13909 | && inst.vectype.el[0].size == 16) | |
13910 | inst.instruction |= 0x00010000; | |
13911 | ||
13912 | /* Programmer's syntax: the sizes are attached to the operands. */ | |
13913 | else if (inst.operands[0].vectype.type != NT_invtype | |
13914 | && inst.operands[0].vectype.size == 16) | |
13915 | inst.instruction |= 0x00010000; | |
13916 | ||
13917 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
13918 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
13919 | do_vfp_cond_or_thumb (); | |
13920 | } | |
13921 | ||
13922 | ||
13923 | static void | |
13924 | do_neon_cvtt (void) | |
13925 | { | |
13926 | do_neon_cvtb (); | |
13927 | inst.instruction |= 0x80; | |
13928 | } | |
13929 | ||
5287ad62 JB |
13930 | static void |
13931 | neon_move_immediate (void) | |
13932 | { | |
037e8744 JB |
13933 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
13934 | struct neon_type_el et = neon_check_type (2, rs, | |
13935 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 | 13936 | unsigned immlo, immhi = 0, immbits; |
c96612cc | 13937 | int op, cmode, float_p; |
5287ad62 | 13938 | |
037e8744 JB |
13939 | constraint (et.type == NT_invtype, |
13940 | _("operand size must be specified for immediate VMOV")); | |
13941 | ||
5287ad62 JB |
13942 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
13943 | op = (inst.instruction & (1 << 5)) != 0; | |
13944 | ||
13945 | immlo = inst.operands[1].imm; | |
13946 | if (inst.operands[1].regisimm) | |
13947 | immhi = inst.operands[1].reg; | |
13948 | ||
13949 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, | |
13950 | _("immediate has bits set outside the operand size")); | |
13951 | ||
c96612cc JB |
13952 | float_p = inst.operands[1].immisfloat; |
13953 | ||
13954 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, | |
136da414 | 13955 | et.size, et.type)) == FAIL) |
5287ad62 JB |
13956 | { |
13957 | /* Invert relevant bits only. */ | |
13958 | neon_invert_size (&immlo, &immhi, et.size); | |
13959 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable | |
13960 | with one or the other; those cases are caught by | |
13961 | neon_cmode_for_move_imm. */ | |
13962 | op = !op; | |
c96612cc JB |
13963 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, |
13964 | &op, et.size, et.type)) == FAIL) | |
5287ad62 | 13965 | { |
dcbf9037 | 13966 | first_error (_("immediate out of range")); |
5287ad62 JB |
13967 | return; |
13968 | } | |
13969 | } | |
13970 | ||
13971 | inst.instruction &= ~(1 << 5); | |
13972 | inst.instruction |= op << 5; | |
13973 | ||
13974 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13975 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
037e8744 | 13976 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13977 | inst.instruction |= cmode << 8; |
13978 | ||
13979 | neon_write_immbits (immbits); | |
13980 | } | |
13981 | ||
13982 | static void | |
13983 | do_neon_mvn (void) | |
13984 | { | |
13985 | if (inst.operands[1].isreg) | |
13986 | { | |
037e8744 | 13987 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5f4273c7 | 13988 | |
88714cb8 | 13989 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13990 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13991 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13992 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13993 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 13994 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13995 | } |
13996 | else | |
13997 | { | |
88714cb8 | 13998 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
13999 | neon_move_immediate (); |
14000 | } | |
14001 | ||
88714cb8 | 14002 | neon_dp_fixup (&inst); |
5287ad62 JB |
14003 | } |
14004 | ||
14005 | /* Encode instructions of form: | |
14006 | ||
14007 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
5f4273c7 | 14008 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ |
5287ad62 JB |
14009 | |
14010 | static void | |
14011 | neon_mixed_length (struct neon_type_el et, unsigned size) | |
14012 | { | |
14013 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14014 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14015 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14016 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14017 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14018 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14019 | inst.instruction |= (et.type == NT_unsigned) << 24; | |
14020 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 14021 | |
88714cb8 | 14022 | neon_dp_fixup (&inst); |
5287ad62 JB |
14023 | } |
14024 | ||
14025 | static void | |
14026 | do_neon_dyadic_long (void) | |
14027 | { | |
14028 | /* FIXME: Type checking for lengthening op. */ | |
14029 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14030 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
14031 | neon_mixed_length (et, et.size); | |
14032 | } | |
14033 | ||
14034 | static void | |
14035 | do_neon_abal (void) | |
14036 | { | |
14037 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14038 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
14039 | neon_mixed_length (et, et.size); | |
14040 | } | |
14041 | ||
14042 | static void | |
14043 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) | |
14044 | { | |
14045 | if (inst.operands[2].isscalar) | |
14046 | { | |
dcbf9037 JB |
14047 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
14048 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); | |
88714cb8 | 14049 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
14050 | neon_mul_mac (et, et.type == NT_unsigned); |
14051 | } | |
14052 | else | |
14053 | { | |
14054 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14055 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); | |
88714cb8 | 14056 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14057 | neon_mixed_length (et, et.size); |
14058 | } | |
14059 | } | |
14060 | ||
14061 | static void | |
14062 | do_neon_mac_maybe_scalar_long (void) | |
14063 | { | |
14064 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); | |
14065 | } | |
14066 | ||
14067 | static void | |
14068 | do_neon_dyadic_wide (void) | |
14069 | { | |
14070 | struct neon_type_el et = neon_check_type (3, NS_QQD, | |
14071 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); | |
14072 | neon_mixed_length (et, et.size); | |
14073 | } | |
14074 | ||
14075 | static void | |
14076 | do_neon_dyadic_narrow (void) | |
14077 | { | |
14078 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14079 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); | |
428e3f1f PB |
14080 | /* Operand sign is unimportant, and the U bit is part of the opcode, |
14081 | so force the operand type to integer. */ | |
14082 | et.type = NT_integer; | |
5287ad62 JB |
14083 | neon_mixed_length (et, et.size / 2); |
14084 | } | |
14085 | ||
14086 | static void | |
14087 | do_neon_mul_sat_scalar_long (void) | |
14088 | { | |
14089 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); | |
14090 | } | |
14091 | ||
14092 | static void | |
14093 | do_neon_vmull (void) | |
14094 | { | |
14095 | if (inst.operands[2].isscalar) | |
14096 | do_neon_mac_maybe_scalar_long (); | |
14097 | else | |
14098 | { | |
14099 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14100 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); | |
14101 | if (et.type == NT_poly) | |
88714cb8 | 14102 | NEON_ENCODE (POLY, inst); |
5287ad62 | 14103 | else |
88714cb8 | 14104 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14105 | /* For polynomial encoding, size field must be 0b00 and the U bit must be |
14106 | zero. Should be OK as-is. */ | |
14107 | neon_mixed_length (et, et.size); | |
14108 | } | |
14109 | } | |
14110 | ||
14111 | static void | |
14112 | do_neon_ext (void) | |
14113 | { | |
037e8744 | 14114 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
5287ad62 JB |
14115 | struct neon_type_el et = neon_check_type (3, rs, |
14116 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14117 | unsigned imm = (inst.operands[3].imm * et.size) / 8; | |
35997600 NC |
14118 | |
14119 | constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), | |
14120 | _("shift out of range")); | |
5287ad62 JB |
14121 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14122 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14123 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14124 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14125 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14126 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
037e8744 | 14127 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 | 14128 | inst.instruction |= imm << 8; |
5f4273c7 | 14129 | |
88714cb8 | 14130 | neon_dp_fixup (&inst); |
5287ad62 JB |
14131 | } |
14132 | ||
14133 | static void | |
14134 | do_neon_rev (void) | |
14135 | { | |
037e8744 | 14136 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14137 | struct neon_type_el et = neon_check_type (2, rs, |
14138 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
14139 | unsigned op = (inst.instruction >> 7) & 3; | |
14140 | /* N (width of reversed regions) is encoded as part of the bitmask. We | |
14141 | extract it here to check the elements to be reversed are smaller. | |
14142 | Otherwise we'd get a reserved instruction. */ | |
14143 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; | |
9c2799c2 | 14144 | gas_assert (elsize != 0); |
5287ad62 JB |
14145 | constraint (et.size >= elsize, |
14146 | _("elements must be smaller than reversal region")); | |
037e8744 | 14147 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14148 | } |
14149 | ||
14150 | static void | |
14151 | do_neon_dup (void) | |
14152 | { | |
14153 | if (inst.operands[1].isscalar) | |
14154 | { | |
037e8744 | 14155 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
dcbf9037 JB |
14156 | struct neon_type_el et = neon_check_type (2, rs, |
14157 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
5287ad62 | 14158 | unsigned sizebits = et.size >> 3; |
dcbf9037 | 14159 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
5287ad62 | 14160 | int logsize = neon_logbits (et.size); |
dcbf9037 | 14161 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
037e8744 JB |
14162 | |
14163 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) | |
14164 | return; | |
14165 | ||
88714cb8 | 14166 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
14167 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14168 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14169 | inst.instruction |= LOW4 (dm); | |
14170 | inst.instruction |= HI1 (dm) << 5; | |
037e8744 | 14171 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14172 | inst.instruction |= x << 17; |
14173 | inst.instruction |= sizebits << 16; | |
5f4273c7 | 14174 | |
88714cb8 | 14175 | neon_dp_fixup (&inst); |
5287ad62 JB |
14176 | } |
14177 | else | |
14178 | { | |
037e8744 JB |
14179 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
14180 | struct neon_type_el et = neon_check_type (2, rs, | |
14181 | N_8 | N_16 | N_32 | N_KEY, N_EQK); | |
5287ad62 | 14182 | /* Duplicate ARM register to lanes of vector. */ |
88714cb8 | 14183 | NEON_ENCODE (ARMREG, inst); |
5287ad62 JB |
14184 | switch (et.size) |
14185 | { | |
14186 | case 8: inst.instruction |= 0x400000; break; | |
14187 | case 16: inst.instruction |= 0x000020; break; | |
14188 | case 32: inst.instruction |= 0x000000; break; | |
14189 | default: break; | |
14190 | } | |
14191 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
14192 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; | |
14193 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; | |
037e8744 | 14194 | inst.instruction |= neon_quad (rs) << 21; |
5287ad62 JB |
14195 | /* The encoding for this instruction is identical for the ARM and Thumb |
14196 | variants, except for the condition field. */ | |
037e8744 | 14197 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
14198 | } |
14199 | } | |
14200 | ||
14201 | /* VMOV has particularly many variations. It can be one of: | |
14202 | 0. VMOV<c><q> <Qd>, <Qm> | |
14203 | 1. VMOV<c><q> <Dd>, <Dm> | |
14204 | (Register operations, which are VORR with Rm = Rn.) | |
14205 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> | |
14206 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> | |
14207 | (Immediate loads.) | |
14208 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> | |
14209 | (ARM register to scalar.) | |
14210 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> | |
14211 | (Two ARM registers to vector.) | |
14212 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> | |
14213 | (Scalar to ARM register.) | |
14214 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> | |
14215 | (Vector to two ARM registers.) | |
037e8744 JB |
14216 | 8. VMOV.F32 <Sd>, <Sm> |
14217 | 9. VMOV.F64 <Dd>, <Dm> | |
14218 | (VFP register moves.) | |
14219 | 10. VMOV.F32 <Sd>, #imm | |
14220 | 11. VMOV.F64 <Dd>, #imm | |
14221 | (VFP float immediate load.) | |
14222 | 12. VMOV <Rd>, <Sm> | |
14223 | (VFP single to ARM reg.) | |
14224 | 13. VMOV <Sd>, <Rm> | |
14225 | (ARM reg to VFP single.) | |
14226 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> | |
14227 | (Two ARM regs to two VFP singles.) | |
14228 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> | |
14229 | (Two VFP singles to two ARM regs.) | |
5f4273c7 | 14230 | |
037e8744 JB |
14231 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
14232 | and 3/11 which depend on the operand type too. | |
5f4273c7 | 14233 | |
5287ad62 | 14234 | All the encoded bits are hardcoded by this function. |
5f4273c7 | 14235 | |
b7fc2769 JB |
14236 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
14237 | Cases 5, 7 may be used with VFPv2 and above. | |
5f4273c7 | 14238 | |
5287ad62 | 14239 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
5f4273c7 | 14240 | can specify a type where it doesn't make sense to, and is ignored). */ |
5287ad62 JB |
14241 | |
14242 | static void | |
14243 | do_neon_mov (void) | |
14244 | { | |
037e8744 JB |
14245 | enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, |
14246 | NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, | |
14247 | NS_NULL); | |
14248 | struct neon_type_el et; | |
14249 | const char *ldconst = 0; | |
5287ad62 | 14250 | |
037e8744 | 14251 | switch (rs) |
5287ad62 | 14252 | { |
037e8744 JB |
14253 | case NS_DD: /* case 1/9. */ |
14254 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
14255 | /* It is not an error here if no type is given. */ | |
14256 | inst.error = NULL; | |
14257 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 14258 | { |
037e8744 JB |
14259 | do_vfp_nsyn_opcode ("fcpyd"); |
14260 | break; | |
5287ad62 | 14261 | } |
037e8744 | 14262 | /* fall through. */ |
5287ad62 | 14263 | |
037e8744 JB |
14264 | case NS_QQ: /* case 0/1. */ |
14265 | { | |
14266 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14267 | return; | |
14268 | /* The architecture manual I have doesn't explicitly state which | |
14269 | value the U bit should have for register->register moves, but | |
14270 | the equivalent VORR instruction has U = 0, so do that. */ | |
14271 | inst.instruction = 0x0200110; | |
14272 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14273 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14274 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14275 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14276 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14277 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14278 | inst.instruction |= neon_quad (rs) << 6; | |
14279 | ||
88714cb8 | 14280 | neon_dp_fixup (&inst); |
037e8744 JB |
14281 | } |
14282 | break; | |
5f4273c7 | 14283 | |
037e8744 JB |
14284 | case NS_DI: /* case 3/11. */ |
14285 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
14286 | inst.error = NULL; | |
14287 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 14288 | { |
037e8744 JB |
14289 | /* case 11 (fconstd). */ |
14290 | ldconst = "fconstd"; | |
14291 | goto encode_fconstd; | |
5287ad62 | 14292 | } |
037e8744 JB |
14293 | /* fall through. */ |
14294 | ||
14295 | case NS_QI: /* case 2/3. */ | |
14296 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14297 | return; | |
14298 | inst.instruction = 0x0800010; | |
14299 | neon_move_immediate (); | |
88714cb8 | 14300 | neon_dp_fixup (&inst); |
5287ad62 | 14301 | break; |
5f4273c7 | 14302 | |
037e8744 JB |
14303 | case NS_SR: /* case 4. */ |
14304 | { | |
14305 | unsigned bcdebits = 0; | |
91d6fa6a | 14306 | int logsize; |
037e8744 JB |
14307 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); |
14308 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); | |
14309 | ||
91d6fa6a NC |
14310 | et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK); |
14311 | logsize = neon_logbits (et.size); | |
14312 | ||
037e8744 JB |
14313 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), |
14314 | _(BAD_FPU)); | |
14315 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
14316 | && et.size != 32, _(BAD_FPU)); | |
14317 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
14318 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
14319 | ||
14320 | switch (et.size) | |
14321 | { | |
14322 | case 8: bcdebits = 0x8; break; | |
14323 | case 16: bcdebits = 0x1; break; | |
14324 | case 32: bcdebits = 0x0; break; | |
14325 | default: ; | |
14326 | } | |
14327 | ||
14328 | bcdebits |= x << logsize; | |
14329 | ||
14330 | inst.instruction = 0xe000b10; | |
14331 | do_vfp_cond_or_thumb (); | |
14332 | inst.instruction |= LOW4 (dn) << 16; | |
14333 | inst.instruction |= HI1 (dn) << 7; | |
14334 | inst.instruction |= inst.operands[1].reg << 12; | |
14335 | inst.instruction |= (bcdebits & 3) << 5; | |
14336 | inst.instruction |= (bcdebits >> 2) << 21; | |
14337 | } | |
14338 | break; | |
5f4273c7 | 14339 | |
037e8744 | 14340 | case NS_DRR: /* case 5 (fmdrr). */ |
b7fc2769 | 14341 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), |
037e8744 | 14342 | _(BAD_FPU)); |
b7fc2769 | 14343 | |
037e8744 JB |
14344 | inst.instruction = 0xc400b10; |
14345 | do_vfp_cond_or_thumb (); | |
14346 | inst.instruction |= LOW4 (inst.operands[0].reg); | |
14347 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; | |
14348 | inst.instruction |= inst.operands[1].reg << 12; | |
14349 | inst.instruction |= inst.operands[2].reg << 16; | |
14350 | break; | |
5f4273c7 | 14351 | |
037e8744 JB |
14352 | case NS_RS: /* case 6. */ |
14353 | { | |
91d6fa6a | 14354 | unsigned logsize; |
037e8744 JB |
14355 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); |
14356 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); | |
14357 | unsigned abcdebits = 0; | |
14358 | ||
91d6fa6a NC |
14359 | et = neon_check_type (2, NS_NULL, |
14360 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); | |
14361 | logsize = neon_logbits (et.size); | |
14362 | ||
037e8744 JB |
14363 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), |
14364 | _(BAD_FPU)); | |
14365 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
14366 | && et.size != 32, _(BAD_FPU)); | |
14367 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
14368 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
14369 | ||
14370 | switch (et.size) | |
14371 | { | |
14372 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; | |
14373 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; | |
14374 | case 32: abcdebits = 0x00; break; | |
14375 | default: ; | |
14376 | } | |
14377 | ||
14378 | abcdebits |= x << logsize; | |
14379 | inst.instruction = 0xe100b10; | |
14380 | do_vfp_cond_or_thumb (); | |
14381 | inst.instruction |= LOW4 (dn) << 16; | |
14382 | inst.instruction |= HI1 (dn) << 7; | |
14383 | inst.instruction |= inst.operands[0].reg << 12; | |
14384 | inst.instruction |= (abcdebits & 3) << 5; | |
14385 | inst.instruction |= (abcdebits >> 2) << 21; | |
14386 | } | |
14387 | break; | |
5f4273c7 | 14388 | |
037e8744 JB |
14389 | case NS_RRD: /* case 7 (fmrrd). */ |
14390 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), | |
14391 | _(BAD_FPU)); | |
14392 | ||
14393 | inst.instruction = 0xc500b10; | |
14394 | do_vfp_cond_or_thumb (); | |
14395 | inst.instruction |= inst.operands[0].reg << 12; | |
14396 | inst.instruction |= inst.operands[1].reg << 16; | |
14397 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14398 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14399 | break; | |
5f4273c7 | 14400 | |
037e8744 JB |
14401 | case NS_FF: /* case 8 (fcpys). */ |
14402 | do_vfp_nsyn_opcode ("fcpys"); | |
14403 | break; | |
5f4273c7 | 14404 | |
037e8744 JB |
14405 | case NS_FI: /* case 10 (fconsts). */ |
14406 | ldconst = "fconsts"; | |
14407 | encode_fconstd: | |
14408 | if (is_quarter_float (inst.operands[1].imm)) | |
5287ad62 | 14409 | { |
037e8744 JB |
14410 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); |
14411 | do_vfp_nsyn_opcode (ldconst); | |
5287ad62 JB |
14412 | } |
14413 | else | |
037e8744 JB |
14414 | first_error (_("immediate out of range")); |
14415 | break; | |
5f4273c7 | 14416 | |
037e8744 JB |
14417 | case NS_RF: /* case 12 (fmrs). */ |
14418 | do_vfp_nsyn_opcode ("fmrs"); | |
14419 | break; | |
5f4273c7 | 14420 | |
037e8744 JB |
14421 | case NS_FR: /* case 13 (fmsr). */ |
14422 | do_vfp_nsyn_opcode ("fmsr"); | |
14423 | break; | |
5f4273c7 | 14424 | |
037e8744 JB |
14425 | /* The encoders for the fmrrs and fmsrr instructions expect three operands |
14426 | (one of which is a list), but we have parsed four. Do some fiddling to | |
14427 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 | |
14428 | expect. */ | |
14429 | case NS_RRFF: /* case 14 (fmrrs). */ | |
14430 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, | |
14431 | _("VFP registers must be adjacent")); | |
14432 | inst.operands[2].imm = 2; | |
14433 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
14434 | do_vfp_nsyn_opcode ("fmrrs"); | |
14435 | break; | |
5f4273c7 | 14436 | |
037e8744 JB |
14437 | case NS_FFRR: /* case 15 (fmsrr). */ |
14438 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, | |
14439 | _("VFP registers must be adjacent")); | |
14440 | inst.operands[1] = inst.operands[2]; | |
14441 | inst.operands[2] = inst.operands[3]; | |
14442 | inst.operands[0].imm = 2; | |
14443 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
14444 | do_vfp_nsyn_opcode ("fmsrr"); | |
5287ad62 | 14445 | break; |
5f4273c7 | 14446 | |
5287ad62 JB |
14447 | default: |
14448 | abort (); | |
14449 | } | |
14450 | } | |
14451 | ||
14452 | static void | |
14453 | do_neon_rshift_round_imm (void) | |
14454 | { | |
037e8744 | 14455 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14456 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
14457 | int imm = inst.operands[2].imm; | |
14458 | ||
14459 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ | |
14460 | if (imm == 0) | |
14461 | { | |
14462 | inst.operands[2].present = 0; | |
14463 | do_neon_mov (); | |
14464 | return; | |
14465 | } | |
14466 | ||
14467 | constraint (imm < 1 || (unsigned)imm > et.size, | |
14468 | _("immediate out of range for shift")); | |
037e8744 | 14469 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
14470 | et.size - imm); |
14471 | } | |
14472 | ||
14473 | static void | |
14474 | do_neon_movl (void) | |
14475 | { | |
14476 | struct neon_type_el et = neon_check_type (2, NS_QD, | |
14477 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
14478 | unsigned sizebits = et.size >> 3; | |
14479 | inst.instruction |= sizebits << 19; | |
14480 | neon_two_same (0, et.type == NT_unsigned, -1); | |
14481 | } | |
14482 | ||
14483 | static void | |
14484 | do_neon_trn (void) | |
14485 | { | |
037e8744 | 14486 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14487 | struct neon_type_el et = neon_check_type (2, rs, |
14488 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
88714cb8 | 14489 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14490 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14491 | } |
14492 | ||
14493 | static void | |
14494 | do_neon_zip_uzp (void) | |
14495 | { | |
037e8744 | 14496 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14497 | struct neon_type_el et = neon_check_type (2, rs, |
14498 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
14499 | if (rs == NS_DD && et.size == 32) | |
14500 | { | |
14501 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ | |
14502 | inst.instruction = N_MNEM_vtrn; | |
14503 | do_neon_trn (); | |
14504 | return; | |
14505 | } | |
037e8744 | 14506 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14507 | } |
14508 | ||
14509 | static void | |
14510 | do_neon_sat_abs_neg (void) | |
14511 | { | |
037e8744 | 14512 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14513 | struct neon_type_el et = neon_check_type (2, rs, |
14514 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 14515 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14516 | } |
14517 | ||
14518 | static void | |
14519 | do_neon_pair_long (void) | |
14520 | { | |
037e8744 | 14521 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14522 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
14523 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ | |
14524 | inst.instruction |= (et.type == NT_unsigned) << 7; | |
037e8744 | 14525 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14526 | } |
14527 | ||
14528 | static void | |
14529 | do_neon_recip_est (void) | |
14530 | { | |
037e8744 | 14531 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14532 | struct neon_type_el et = neon_check_type (2, rs, |
14533 | N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); | |
14534 | inst.instruction |= (et.type == NT_float) << 8; | |
037e8744 | 14535 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14536 | } |
14537 | ||
14538 | static void | |
14539 | do_neon_cls (void) | |
14540 | { | |
037e8744 | 14541 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14542 | struct neon_type_el et = neon_check_type (2, rs, |
14543 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 14544 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14545 | } |
14546 | ||
14547 | static void | |
14548 | do_neon_clz (void) | |
14549 | { | |
037e8744 | 14550 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14551 | struct neon_type_el et = neon_check_type (2, rs, |
14552 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); | |
037e8744 | 14553 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14554 | } |
14555 | ||
14556 | static void | |
14557 | do_neon_cnt (void) | |
14558 | { | |
037e8744 | 14559 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14560 | struct neon_type_el et = neon_check_type (2, rs, |
14561 | N_EQK | N_INT, N_8 | N_KEY); | |
037e8744 | 14562 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14563 | } |
14564 | ||
14565 | static void | |
14566 | do_neon_swp (void) | |
14567 | { | |
037e8744 JB |
14568 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
14569 | neon_two_same (neon_quad (rs), 1, -1); | |
5287ad62 JB |
14570 | } |
14571 | ||
14572 | static void | |
14573 | do_neon_tbl_tbx (void) | |
14574 | { | |
14575 | unsigned listlenbits; | |
dcbf9037 | 14576 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
5f4273c7 | 14577 | |
5287ad62 JB |
14578 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) |
14579 | { | |
dcbf9037 | 14580 | first_error (_("bad list length for table lookup")); |
5287ad62 JB |
14581 | return; |
14582 | } | |
5f4273c7 | 14583 | |
5287ad62 JB |
14584 | listlenbits = inst.operands[1].imm - 1; |
14585 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14586 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14587 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14588 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14589 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14590 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14591 | inst.instruction |= listlenbits << 8; | |
5f4273c7 | 14592 | |
88714cb8 | 14593 | neon_dp_fixup (&inst); |
5287ad62 JB |
14594 | } |
14595 | ||
14596 | static void | |
14597 | do_neon_ldm_stm (void) | |
14598 | { | |
14599 | /* P, U and L bits are part of bitmask. */ | |
14600 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; | |
14601 | unsigned offsetbits = inst.operands[1].imm * 2; | |
14602 | ||
037e8744 JB |
14603 | if (inst.operands[1].issingle) |
14604 | { | |
14605 | do_vfp_nsyn_ldm_stm (is_dbmode); | |
14606 | return; | |
14607 | } | |
14608 | ||
5287ad62 JB |
14609 | constraint (is_dbmode && !inst.operands[0].writeback, |
14610 | _("writeback (!) must be used for VLDMDB and VSTMDB")); | |
14611 | ||
14612 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
14613 | _("register list must contain at least 1 and at most 16 " | |
14614 | "registers")); | |
14615 | ||
14616 | inst.instruction |= inst.operands[0].reg << 16; | |
14617 | inst.instruction |= inst.operands[0].writeback << 21; | |
14618 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
14619 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; | |
14620 | ||
14621 | inst.instruction |= offsetbits; | |
5f4273c7 | 14622 | |
037e8744 | 14623 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
14624 | } |
14625 | ||
14626 | static void | |
14627 | do_neon_ldr_str (void) | |
14628 | { | |
5287ad62 | 14629 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
5f4273c7 | 14630 | |
037e8744 JB |
14631 | if (inst.operands[0].issingle) |
14632 | { | |
cd2f129f JB |
14633 | if (is_ldr) |
14634 | do_vfp_nsyn_opcode ("flds"); | |
14635 | else | |
14636 | do_vfp_nsyn_opcode ("fsts"); | |
5287ad62 JB |
14637 | } |
14638 | else | |
5287ad62 | 14639 | { |
cd2f129f JB |
14640 | if (is_ldr) |
14641 | do_vfp_nsyn_opcode ("fldd"); | |
5287ad62 | 14642 | else |
cd2f129f | 14643 | do_vfp_nsyn_opcode ("fstd"); |
5287ad62 | 14644 | } |
5287ad62 JB |
14645 | } |
14646 | ||
14647 | /* "interleave" version also handles non-interleaving register VLD1/VST1 | |
14648 | instructions. */ | |
14649 | ||
14650 | static void | |
14651 | do_neon_ld_st_interleave (void) | |
14652 | { | |
037e8744 | 14653 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
5287ad62 JB |
14654 | N_8 | N_16 | N_32 | N_64); |
14655 | unsigned alignbits = 0; | |
14656 | unsigned idx; | |
14657 | /* The bits in this table go: | |
14658 | 0: register stride of one (0) or two (1) | |
14659 | 1,2: register list length, minus one (1, 2, 3, 4). | |
14660 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). | |
14661 | We use -1 for invalid entries. */ | |
14662 | const int typetable[] = | |
14663 | { | |
14664 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ | |
14665 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ | |
14666 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ | |
14667 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ | |
14668 | }; | |
14669 | int typebits; | |
14670 | ||
dcbf9037 JB |
14671 | if (et.type == NT_invtype) |
14672 | return; | |
14673 | ||
5287ad62 JB |
14674 | if (inst.operands[1].immisalign) |
14675 | switch (inst.operands[1].imm >> 8) | |
14676 | { | |
14677 | case 64: alignbits = 1; break; | |
14678 | case 128: | |
e23c0ad8 JZ |
14679 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2 |
14680 | && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) | |
5287ad62 JB |
14681 | goto bad_alignment; |
14682 | alignbits = 2; | |
14683 | break; | |
14684 | case 256: | |
e23c0ad8 | 14685 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
5287ad62 JB |
14686 | goto bad_alignment; |
14687 | alignbits = 3; | |
14688 | break; | |
14689 | default: | |
14690 | bad_alignment: | |
dcbf9037 | 14691 | first_error (_("bad alignment")); |
5287ad62 JB |
14692 | return; |
14693 | } | |
14694 | ||
14695 | inst.instruction |= alignbits << 4; | |
14696 | inst.instruction |= neon_logbits (et.size) << 6; | |
14697 | ||
14698 | /* Bits [4:6] of the immediate in a list specifier encode register stride | |
14699 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of | |
14700 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look | |
14701 | up the right value for "type" in a table based on this value and the given | |
14702 | list style, then stick it back. */ | |
14703 | idx = ((inst.operands[0].imm >> 4) & 7) | |
14704 | | (((inst.instruction >> 8) & 3) << 3); | |
14705 | ||
14706 | typebits = typetable[idx]; | |
5f4273c7 | 14707 | |
5287ad62 JB |
14708 | constraint (typebits == -1, _("bad list type for instruction")); |
14709 | ||
14710 | inst.instruction &= ~0xf00; | |
14711 | inst.instruction |= typebits << 8; | |
14712 | } | |
14713 | ||
14714 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. | |
14715 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 | |
14716 | otherwise. The variable arguments are a list of pairs of legal (size, align) | |
14717 | values, terminated with -1. */ | |
14718 | ||
14719 | static int | |
14720 | neon_alignment_bit (int size, int align, int *do_align, ...) | |
14721 | { | |
14722 | va_list ap; | |
14723 | int result = FAIL, thissize, thisalign; | |
5f4273c7 | 14724 | |
5287ad62 JB |
14725 | if (!inst.operands[1].immisalign) |
14726 | { | |
14727 | *do_align = 0; | |
14728 | return SUCCESS; | |
14729 | } | |
5f4273c7 | 14730 | |
5287ad62 JB |
14731 | va_start (ap, do_align); |
14732 | ||
14733 | do | |
14734 | { | |
14735 | thissize = va_arg (ap, int); | |
14736 | if (thissize == -1) | |
14737 | break; | |
14738 | thisalign = va_arg (ap, int); | |
14739 | ||
14740 | if (size == thissize && align == thisalign) | |
14741 | result = SUCCESS; | |
14742 | } | |
14743 | while (result != SUCCESS); | |
14744 | ||
14745 | va_end (ap); | |
14746 | ||
14747 | if (result == SUCCESS) | |
14748 | *do_align = 1; | |
14749 | else | |
dcbf9037 | 14750 | first_error (_("unsupported alignment for instruction")); |
5f4273c7 | 14751 | |
5287ad62 JB |
14752 | return result; |
14753 | } | |
14754 | ||
14755 | static void | |
14756 | do_neon_ld_st_lane (void) | |
14757 | { | |
037e8744 | 14758 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
14759 | int align_good, do_align = 0; |
14760 | int logsize = neon_logbits (et.size); | |
14761 | int align = inst.operands[1].imm >> 8; | |
14762 | int n = (inst.instruction >> 8) & 3; | |
14763 | int max_el = 64 / et.size; | |
5f4273c7 | 14764 | |
dcbf9037 JB |
14765 | if (et.type == NT_invtype) |
14766 | return; | |
5f4273c7 | 14767 | |
5287ad62 JB |
14768 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
14769 | _("bad list length")); | |
14770 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, | |
14771 | _("scalar index out of range")); | |
14772 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 | |
14773 | && et.size == 8, | |
14774 | _("stride of 2 unavailable when element size is 8")); | |
5f4273c7 | 14775 | |
5287ad62 JB |
14776 | switch (n) |
14777 | { | |
14778 | case 0: /* VLD1 / VST1. */ | |
14779 | align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, | |
14780 | 32, 32, -1); | |
14781 | if (align_good == FAIL) | |
14782 | return; | |
14783 | if (do_align) | |
14784 | { | |
14785 | unsigned alignbits = 0; | |
14786 | switch (et.size) | |
14787 | { | |
14788 | case 16: alignbits = 0x1; break; | |
14789 | case 32: alignbits = 0x3; break; | |
14790 | default: ; | |
14791 | } | |
14792 | inst.instruction |= alignbits << 4; | |
14793 | } | |
14794 | break; | |
14795 | ||
14796 | case 1: /* VLD2 / VST2. */ | |
14797 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, | |
14798 | 32, 64, -1); | |
14799 | if (align_good == FAIL) | |
14800 | return; | |
14801 | if (do_align) | |
14802 | inst.instruction |= 1 << 4; | |
14803 | break; | |
14804 | ||
14805 | case 2: /* VLD3 / VST3. */ | |
14806 | constraint (inst.operands[1].immisalign, | |
14807 | _("can't use alignment with this instruction")); | |
14808 | break; | |
14809 | ||
14810 | case 3: /* VLD4 / VST4. */ | |
14811 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
14812 | 16, 64, 32, 64, 32, 128, -1); | |
14813 | if (align_good == FAIL) | |
14814 | return; | |
14815 | if (do_align) | |
14816 | { | |
14817 | unsigned alignbits = 0; | |
14818 | switch (et.size) | |
14819 | { | |
14820 | case 8: alignbits = 0x1; break; | |
14821 | case 16: alignbits = 0x1; break; | |
14822 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; | |
14823 | default: ; | |
14824 | } | |
14825 | inst.instruction |= alignbits << 4; | |
14826 | } | |
14827 | break; | |
14828 | ||
14829 | default: ; | |
14830 | } | |
14831 | ||
14832 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ | |
14833 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
14834 | inst.instruction |= 1 << (4 + logsize); | |
5f4273c7 | 14835 | |
5287ad62 JB |
14836 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); |
14837 | inst.instruction |= logsize << 10; | |
14838 | } | |
14839 | ||
14840 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ | |
14841 | ||
14842 | static void | |
14843 | do_neon_ld_dup (void) | |
14844 | { | |
037e8744 | 14845 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
14846 | int align_good, do_align = 0; |
14847 | ||
dcbf9037 JB |
14848 | if (et.type == NT_invtype) |
14849 | return; | |
14850 | ||
5287ad62 JB |
14851 | switch ((inst.instruction >> 8) & 3) |
14852 | { | |
14853 | case 0: /* VLD1. */ | |
9c2799c2 | 14854 | gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); |
5287ad62 JB |
14855 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, |
14856 | &do_align, 16, 16, 32, 32, -1); | |
14857 | if (align_good == FAIL) | |
14858 | return; | |
14859 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) | |
14860 | { | |
14861 | case 1: break; | |
14862 | case 2: inst.instruction |= 1 << 5; break; | |
dcbf9037 | 14863 | default: first_error (_("bad list length")); return; |
5287ad62 JB |
14864 | } |
14865 | inst.instruction |= neon_logbits (et.size) << 6; | |
14866 | break; | |
14867 | ||
14868 | case 1: /* VLD2. */ | |
14869 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
14870 | &do_align, 8, 16, 16, 32, 32, 64, -1); | |
14871 | if (align_good == FAIL) | |
14872 | return; | |
14873 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, | |
14874 | _("bad list length")); | |
14875 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
14876 | inst.instruction |= 1 << 5; | |
14877 | inst.instruction |= neon_logbits (et.size) << 6; | |
14878 | break; | |
14879 | ||
14880 | case 2: /* VLD3. */ | |
14881 | constraint (inst.operands[1].immisalign, | |
14882 | _("can't use alignment with this instruction")); | |
14883 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, | |
14884 | _("bad list length")); | |
14885 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
14886 | inst.instruction |= 1 << 5; | |
14887 | inst.instruction |= neon_logbits (et.size) << 6; | |
14888 | break; | |
14889 | ||
14890 | case 3: /* VLD4. */ | |
14891 | { | |
14892 | int align = inst.operands[1].imm >> 8; | |
14893 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
14894 | 16, 64, 32, 64, 32, 128, -1); | |
14895 | if (align_good == FAIL) | |
14896 | return; | |
14897 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, | |
14898 | _("bad list length")); | |
14899 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
14900 | inst.instruction |= 1 << 5; | |
14901 | if (et.size == 32 && align == 128) | |
14902 | inst.instruction |= 0x3 << 6; | |
14903 | else | |
14904 | inst.instruction |= neon_logbits (et.size) << 6; | |
14905 | } | |
14906 | break; | |
14907 | ||
14908 | default: ; | |
14909 | } | |
14910 | ||
14911 | inst.instruction |= do_align << 4; | |
14912 | } | |
14913 | ||
14914 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those | |
14915 | apart from bits [11:4]. */ | |
14916 | ||
14917 | static void | |
14918 | do_neon_ldx_stx (void) | |
14919 | { | |
b1a769ed DG |
14920 | if (inst.operands[1].isreg) |
14921 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
14922 | ||
5287ad62 JB |
14923 | switch (NEON_LANE (inst.operands[0].imm)) |
14924 | { | |
14925 | case NEON_INTERLEAVE_LANES: | |
88714cb8 | 14926 | NEON_ENCODE (INTERLV, inst); |
5287ad62 JB |
14927 | do_neon_ld_st_interleave (); |
14928 | break; | |
5f4273c7 | 14929 | |
5287ad62 | 14930 | case NEON_ALL_LANES: |
88714cb8 | 14931 | NEON_ENCODE (DUP, inst); |
5287ad62 JB |
14932 | do_neon_ld_dup (); |
14933 | break; | |
5f4273c7 | 14934 | |
5287ad62 | 14935 | default: |
88714cb8 | 14936 | NEON_ENCODE (LANE, inst); |
5287ad62 JB |
14937 | do_neon_ld_st_lane (); |
14938 | } | |
14939 | ||
14940 | /* L bit comes from bit mask. */ | |
14941 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14942 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14943 | inst.instruction |= inst.operands[1].reg << 16; | |
5f4273c7 | 14944 | |
5287ad62 JB |
14945 | if (inst.operands[1].postind) |
14946 | { | |
14947 | int postreg = inst.operands[1].imm & 0xf; | |
14948 | constraint (!inst.operands[1].immisreg, | |
14949 | _("post-index must be a register")); | |
14950 | constraint (postreg == 0xd || postreg == 0xf, | |
14951 | _("bad register for post-index")); | |
14952 | inst.instruction |= postreg; | |
14953 | } | |
14954 | else if (inst.operands[1].writeback) | |
14955 | { | |
14956 | inst.instruction |= 0xd; | |
14957 | } | |
14958 | else | |
5f4273c7 NC |
14959 | inst.instruction |= 0xf; |
14960 | ||
5287ad62 JB |
14961 | if (thumb_mode) |
14962 | inst.instruction |= 0xf9000000; | |
14963 | else | |
14964 | inst.instruction |= 0xf4000000; | |
14965 | } | |
5287ad62 JB |
14966 | \f |
14967 | /* Overall per-instruction processing. */ | |
14968 | ||
14969 | /* We need to be able to fix up arbitrary expressions in some statements. | |
14970 | This is so that we can handle symbols that are an arbitrary distance from | |
14971 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
14972 | which returns part of an address in a form which will be valid for | |
14973 | a data instruction. We do this by pushing the expression into a symbol | |
14974 | in the expr_section, and creating a fix for that. */ | |
14975 | ||
14976 | static void | |
14977 | fix_new_arm (fragS * frag, | |
14978 | int where, | |
14979 | short int size, | |
14980 | expressionS * exp, | |
14981 | int pc_rel, | |
14982 | int reloc) | |
14983 | { | |
14984 | fixS * new_fix; | |
14985 | ||
14986 | switch (exp->X_op) | |
14987 | { | |
14988 | case O_constant: | |
14989 | case O_symbol: | |
14990 | case O_add: | |
14991 | case O_subtract: | |
21d799b5 NC |
14992 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, |
14993 | (enum bfd_reloc_code_real) reloc); | |
5287ad62 JB |
14994 | break; |
14995 | ||
14996 | default: | |
21d799b5 NC |
14997 | new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0, |
14998 | pc_rel, (enum bfd_reloc_code_real) reloc); | |
5287ad62 JB |
14999 | break; |
15000 | } | |
15001 | ||
15002 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
15003 | instruction. */ | |
15004 | new_fix->tc_fix_data = thumb_mode; | |
15005 | } | |
15006 | ||
15007 | /* Create a frg for an instruction requiring relaxation. */ | |
15008 | static void | |
15009 | output_relax_insn (void) | |
15010 | { | |
15011 | char * to; | |
15012 | symbolS *sym; | |
0110f2b8 PB |
15013 | int offset; |
15014 | ||
6e1cb1a6 PB |
15015 | /* The size of the instruction is unknown, so tie the debug info to the |
15016 | start of the instruction. */ | |
15017 | dwarf2_emit_insn (0); | |
6e1cb1a6 | 15018 | |
0110f2b8 PB |
15019 | switch (inst.reloc.exp.X_op) |
15020 | { | |
15021 | case O_symbol: | |
15022 | sym = inst.reloc.exp.X_add_symbol; | |
15023 | offset = inst.reloc.exp.X_add_number; | |
15024 | break; | |
15025 | case O_constant: | |
15026 | sym = NULL; | |
15027 | offset = inst.reloc.exp.X_add_number; | |
15028 | break; | |
15029 | default: | |
15030 | sym = make_expr_symbol (&inst.reloc.exp); | |
15031 | offset = 0; | |
15032 | break; | |
15033 | } | |
15034 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
15035 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
15036 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
15037 | } |
15038 | ||
15039 | /* Write a 32-bit thumb instruction to buf. */ | |
15040 | static void | |
15041 | put_thumb32_insn (char * buf, unsigned long insn) | |
15042 | { | |
15043 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
15044 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
15045 | } | |
15046 | ||
b99bd4ef | 15047 | static void |
c19d1205 | 15048 | output_inst (const char * str) |
b99bd4ef | 15049 | { |
c19d1205 | 15050 | char * to = NULL; |
b99bd4ef | 15051 | |
c19d1205 | 15052 | if (inst.error) |
b99bd4ef | 15053 | { |
c19d1205 | 15054 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
15055 | return; |
15056 | } | |
5f4273c7 NC |
15057 | if (inst.relax) |
15058 | { | |
15059 | output_relax_insn (); | |
0110f2b8 | 15060 | return; |
5f4273c7 | 15061 | } |
c19d1205 ZW |
15062 | if (inst.size == 0) |
15063 | return; | |
b99bd4ef | 15064 | |
c19d1205 | 15065 | to = frag_more (inst.size); |
8dc2430f NC |
15066 | /* PR 9814: Record the thumb mode into the current frag so that we know |
15067 | what type of NOP padding to use, if necessary. We override any previous | |
15068 | setting so that if the mode has changed then the NOPS that we use will | |
15069 | match the encoding of the last instruction in the frag. */ | |
cd000bff | 15070 | frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
c19d1205 ZW |
15071 | |
15072 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 15073 | { |
9c2799c2 | 15074 | gas_assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 15075 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 15076 | } |
c19d1205 | 15077 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 15078 | { |
9c2799c2 | 15079 | gas_assert (inst.size == (2 * INSN_SIZE)); |
c19d1205 ZW |
15080 | md_number_to_chars (to, inst.instruction, INSN_SIZE); |
15081 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 15082 | } |
c19d1205 ZW |
15083 | else |
15084 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 15085 | |
c19d1205 ZW |
15086 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
15087 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
15088 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
15089 | inst.reloc.type); | |
b99bd4ef | 15090 | |
c19d1205 | 15091 | dwarf2_emit_insn (inst.size); |
c19d1205 | 15092 | } |
b99bd4ef | 15093 | |
e07e6e58 NC |
15094 | static char * |
15095 | output_it_inst (int cond, int mask, char * to) | |
15096 | { | |
15097 | unsigned long instruction = 0xbf00; | |
15098 | ||
15099 | mask &= 0xf; | |
15100 | instruction |= mask; | |
15101 | instruction |= cond << 4; | |
15102 | ||
15103 | if (to == NULL) | |
15104 | { | |
15105 | to = frag_more (2); | |
15106 | #ifdef OBJ_ELF | |
15107 | dwarf2_emit_insn (2); | |
15108 | #endif | |
15109 | } | |
15110 | ||
15111 | md_number_to_chars (to, instruction, 2); | |
15112 | ||
15113 | return to; | |
15114 | } | |
15115 | ||
c19d1205 ZW |
15116 | /* Tag values used in struct asm_opcode's tag field. */ |
15117 | enum opcode_tag | |
15118 | { | |
15119 | OT_unconditional, /* Instruction cannot be conditionalized. | |
15120 | The ARM condition field is still 0xE. */ | |
15121 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
15122 | and carries 0xF in its ARM condition field. */ | |
15123 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
037e8744 JB |
15124 | OT_csuffixF, /* Some forms of the instruction take a conditional |
15125 | suffix, others place 0xF where the condition field | |
15126 | would be. */ | |
c19d1205 ZW |
15127 | OT_cinfix3, /* Instruction takes a conditional infix, |
15128 | beginning at character index 3. (In | |
15129 | unified mode, it becomes a suffix.) */ | |
088fa78e KH |
15130 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
15131 | tsts, cmps, cmns, and teqs. */ | |
e3cb604e PB |
15132 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
15133 | character index 3, even in unified mode. Used for | |
15134 | legacy instructions where suffix and infix forms | |
15135 | may be ambiguous. */ | |
c19d1205 | 15136 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 15137 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
15138 | OT_odd_infix_unc, /* This is the unconditional variant of an |
15139 | instruction that takes a conditional infix | |
15140 | at an unusual position. In unified mode, | |
15141 | this variant will accept a suffix. */ | |
15142 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
15143 | are the conditional variants of instructions that | |
15144 | take conditional infixes in unusual positions. | |
15145 | The infix appears at character index | |
15146 | (tag - OT_odd_infix_0). These are not accepted | |
15147 | in unified mode. */ | |
15148 | }; | |
b99bd4ef | 15149 | |
c19d1205 ZW |
15150 | /* Subroutine of md_assemble, responsible for looking up the primary |
15151 | opcode from the mnemonic the user wrote. STR points to the | |
15152 | beginning of the mnemonic. | |
15153 | ||
15154 | This is not simply a hash table lookup, because of conditional | |
15155 | variants. Most instructions have conditional variants, which are | |
15156 | expressed with a _conditional affix_ to the mnemonic. If we were | |
15157 | to encode each conditional variant as a literal string in the opcode | |
15158 | table, it would have approximately 20,000 entries. | |
15159 | ||
15160 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
15161 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
15162 | instructions take the affix as an infix, notably the s-variants of | |
15163 | the arithmetic instructions. Of those instructions, all but six | |
15164 | have the infix appear after the third character of the mnemonic. | |
15165 | ||
15166 | Accordingly, the algorithm for looking up primary opcodes given | |
15167 | an identifier is: | |
15168 | ||
15169 | 1. Look up the identifier in the opcode table. | |
15170 | If we find a match, go to step U. | |
15171 | ||
15172 | 2. Look up the last two characters of the identifier in the | |
15173 | conditions table. If we find a match, look up the first N-2 | |
15174 | characters of the identifier in the opcode table. If we | |
15175 | find a match, go to step CE. | |
15176 | ||
15177 | 3. Look up the fourth and fifth characters of the identifier in | |
15178 | the conditions table. If we find a match, extract those | |
15179 | characters from the identifier, and look up the remaining | |
15180 | characters in the opcode table. If we find a match, go | |
15181 | to step CM. | |
15182 | ||
15183 | 4. Fail. | |
15184 | ||
15185 | U. Examine the tag field of the opcode structure, in case this is | |
15186 | one of the six instructions with its conditional infix in an | |
15187 | unusual place. If it is, the tag tells us where to find the | |
15188 | infix; look it up in the conditions table and set inst.cond | |
15189 | accordingly. Otherwise, this is an unconditional instruction. | |
15190 | Again set inst.cond accordingly. Return the opcode structure. | |
15191 | ||
15192 | CE. Examine the tag field to make sure this is an instruction that | |
15193 | should receive a conditional suffix. If it is not, fail. | |
15194 | Otherwise, set inst.cond from the suffix we already looked up, | |
15195 | and return the opcode structure. | |
15196 | ||
15197 | CM. Examine the tag field to make sure this is an instruction that | |
15198 | should receive a conditional infix after the third character. | |
15199 | If it is not, fail. Otherwise, undo the edits to the current | |
15200 | line of input and proceed as for case CE. */ | |
15201 | ||
15202 | static const struct asm_opcode * | |
15203 | opcode_lookup (char **str) | |
15204 | { | |
15205 | char *end, *base; | |
15206 | char *affix; | |
15207 | const struct asm_opcode *opcode; | |
15208 | const struct asm_cond *cond; | |
e3cb604e | 15209 | char save[2]; |
c19d1205 ZW |
15210 | |
15211 | /* Scan up to the end of the mnemonic, which must end in white space, | |
721a8186 | 15212 | '.' (in unified mode, or for Neon/VFP instructions), or end of string. */ |
c19d1205 | 15213 | for (base = end = *str; *end != '\0'; end++) |
721a8186 | 15214 | if (*end == ' ' || *end == '.') |
c19d1205 | 15215 | break; |
b99bd4ef | 15216 | |
c19d1205 | 15217 | if (end == base) |
c921be7d | 15218 | return NULL; |
b99bd4ef | 15219 | |
5287ad62 | 15220 | /* Handle a possible width suffix and/or Neon type suffix. */ |
c19d1205 | 15221 | if (end[0] == '.') |
b99bd4ef | 15222 | { |
5287ad62 | 15223 | int offset = 2; |
5f4273c7 | 15224 | |
267d2029 JB |
15225 | /* The .w and .n suffixes are only valid if the unified syntax is in |
15226 | use. */ | |
15227 | if (unified_syntax && end[1] == 'w') | |
c19d1205 | 15228 | inst.size_req = 4; |
267d2029 | 15229 | else if (unified_syntax && end[1] == 'n') |
c19d1205 ZW |
15230 | inst.size_req = 2; |
15231 | else | |
5287ad62 JB |
15232 | offset = 0; |
15233 | ||
15234 | inst.vectype.elems = 0; | |
15235 | ||
15236 | *str = end + offset; | |
b99bd4ef | 15237 | |
5f4273c7 | 15238 | if (end[offset] == '.') |
5287ad62 | 15239 | { |
267d2029 JB |
15240 | /* See if we have a Neon type suffix (possible in either unified or |
15241 | non-unified ARM syntax mode). */ | |
dcbf9037 | 15242 | if (parse_neon_type (&inst.vectype, str) == FAIL) |
c921be7d | 15243 | return NULL; |
5287ad62 JB |
15244 | } |
15245 | else if (end[offset] != '\0' && end[offset] != ' ') | |
c921be7d | 15246 | return NULL; |
b99bd4ef | 15247 | } |
c19d1205 ZW |
15248 | else |
15249 | *str = end; | |
b99bd4ef | 15250 | |
c19d1205 | 15251 | /* Look for unaffixed or special-case affixed mnemonic. */ |
21d799b5 NC |
15252 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
15253 | end - base); | |
c19d1205 | 15254 | if (opcode) |
b99bd4ef | 15255 | { |
c19d1205 ZW |
15256 | /* step U */ |
15257 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 15258 | { |
c19d1205 ZW |
15259 | inst.cond = COND_ALWAYS; |
15260 | return opcode; | |
b99bd4ef | 15261 | } |
b99bd4ef | 15262 | |
278df34e | 15263 | if (warn_on_deprecated && unified_syntax) |
c19d1205 ZW |
15264 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
15265 | affix = base + (opcode->tag - OT_odd_infix_0); | |
21d799b5 | 15266 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
9c2799c2 | 15267 | gas_assert (cond); |
b99bd4ef | 15268 | |
c19d1205 ZW |
15269 | inst.cond = cond->value; |
15270 | return opcode; | |
15271 | } | |
b99bd4ef | 15272 | |
c19d1205 ZW |
15273 | /* Cannot have a conditional suffix on a mnemonic of less than two |
15274 | characters. */ | |
15275 | if (end - base < 3) | |
c921be7d | 15276 | return NULL; |
b99bd4ef | 15277 | |
c19d1205 ZW |
15278 | /* Look for suffixed mnemonic. */ |
15279 | affix = end - 2; | |
21d799b5 NC |
15280 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
15281 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, | |
15282 | affix - base); | |
c19d1205 ZW |
15283 | if (opcode && cond) |
15284 | { | |
15285 | /* step CE */ | |
15286 | switch (opcode->tag) | |
15287 | { | |
e3cb604e PB |
15288 | case OT_cinfix3_legacy: |
15289 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
15290 | break; | |
15291 | ||
c19d1205 | 15292 | case OT_cinfix3: |
088fa78e | 15293 | case OT_cinfix3_deprecated: |
c19d1205 ZW |
15294 | case OT_odd_infix_unc: |
15295 | if (!unified_syntax) | |
e3cb604e | 15296 | return 0; |
c19d1205 ZW |
15297 | /* else fall through */ |
15298 | ||
15299 | case OT_csuffix: | |
037e8744 | 15300 | case OT_csuffixF: |
c19d1205 ZW |
15301 | case OT_csuf_or_in3: |
15302 | inst.cond = cond->value; | |
15303 | return opcode; | |
15304 | ||
15305 | case OT_unconditional: | |
15306 | case OT_unconditionalF: | |
dfa9f0d5 | 15307 | if (thumb_mode) |
c921be7d | 15308 | inst.cond = cond->value; |
dfa9f0d5 PB |
15309 | else |
15310 | { | |
c921be7d | 15311 | /* Delayed diagnostic. */ |
dfa9f0d5 PB |
15312 | inst.error = BAD_COND; |
15313 | inst.cond = COND_ALWAYS; | |
15314 | } | |
c19d1205 | 15315 | return opcode; |
b99bd4ef | 15316 | |
c19d1205 | 15317 | default: |
c921be7d | 15318 | return NULL; |
c19d1205 ZW |
15319 | } |
15320 | } | |
b99bd4ef | 15321 | |
c19d1205 ZW |
15322 | /* Cannot have a usual-position infix on a mnemonic of less than |
15323 | six characters (five would be a suffix). */ | |
15324 | if (end - base < 6) | |
c921be7d | 15325 | return NULL; |
b99bd4ef | 15326 | |
c19d1205 ZW |
15327 | /* Look for infixed mnemonic in the usual position. */ |
15328 | affix = base + 3; | |
21d799b5 | 15329 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
e3cb604e | 15330 | if (!cond) |
c921be7d | 15331 | return NULL; |
e3cb604e PB |
15332 | |
15333 | memcpy (save, affix, 2); | |
15334 | memmove (affix, affix + 2, (end - affix) - 2); | |
21d799b5 NC |
15335 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
15336 | (end - base) - 2); | |
e3cb604e PB |
15337 | memmove (affix + 2, affix, (end - affix) - 2); |
15338 | memcpy (affix, save, 2); | |
15339 | ||
088fa78e KH |
15340 | if (opcode |
15341 | && (opcode->tag == OT_cinfix3 | |
15342 | || opcode->tag == OT_cinfix3_deprecated | |
15343 | || opcode->tag == OT_csuf_or_in3 | |
15344 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 15345 | { |
c921be7d | 15346 | /* Step CM. */ |
278df34e | 15347 | if (warn_on_deprecated && unified_syntax |
088fa78e KH |
15348 | && (opcode->tag == OT_cinfix3 |
15349 | || opcode->tag == OT_cinfix3_deprecated)) | |
c19d1205 ZW |
15350 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
15351 | ||
15352 | inst.cond = cond->value; | |
15353 | return opcode; | |
b99bd4ef NC |
15354 | } |
15355 | ||
c921be7d | 15356 | return NULL; |
b99bd4ef NC |
15357 | } |
15358 | ||
e07e6e58 NC |
15359 | /* This function generates an initial IT instruction, leaving its block |
15360 | virtually open for the new instructions. Eventually, | |
15361 | the mask will be updated by now_it_add_mask () each time | |
15362 | a new instruction needs to be included in the IT block. | |
15363 | Finally, the block is closed with close_automatic_it_block (). | |
15364 | The block closure can be requested either from md_assemble (), | |
15365 | a tencode (), or due to a label hook. */ | |
15366 | ||
15367 | static void | |
15368 | new_automatic_it_block (int cond) | |
15369 | { | |
15370 | now_it.state = AUTOMATIC_IT_BLOCK; | |
15371 | now_it.mask = 0x18; | |
15372 | now_it.cc = cond; | |
15373 | now_it.block_length = 1; | |
cd000bff | 15374 | mapping_state (MAP_THUMB); |
e07e6e58 NC |
15375 | now_it.insn = output_it_inst (cond, now_it.mask, NULL); |
15376 | } | |
15377 | ||
15378 | /* Close an automatic IT block. | |
15379 | See comments in new_automatic_it_block (). */ | |
15380 | ||
15381 | static void | |
15382 | close_automatic_it_block (void) | |
15383 | { | |
15384 | now_it.mask = 0x10; | |
15385 | now_it.block_length = 0; | |
15386 | } | |
15387 | ||
15388 | /* Update the mask of the current automatically-generated IT | |
15389 | instruction. See comments in new_automatic_it_block (). */ | |
15390 | ||
15391 | static void | |
15392 | now_it_add_mask (int cond) | |
15393 | { | |
15394 | #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) | |
15395 | #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ | |
15396 | | ((bitvalue) << (nbit))) | |
e07e6e58 | 15397 | const int resulting_bit = (cond & 1); |
c921be7d | 15398 | |
e07e6e58 NC |
15399 | now_it.mask &= 0xf; |
15400 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
15401 | resulting_bit, | |
15402 | (5 - now_it.block_length)); | |
15403 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
15404 | 1, | |
15405 | ((5 - now_it.block_length) - 1) ); | |
15406 | output_it_inst (now_it.cc, now_it.mask, now_it.insn); | |
15407 | ||
15408 | #undef CLEAR_BIT | |
15409 | #undef SET_BIT_VALUE | |
e07e6e58 NC |
15410 | } |
15411 | ||
15412 | /* The IT blocks handling machinery is accessed through the these functions: | |
15413 | it_fsm_pre_encode () from md_assemble () | |
15414 | set_it_insn_type () optional, from the tencode functions | |
15415 | set_it_insn_type_last () ditto | |
15416 | in_it_block () ditto | |
15417 | it_fsm_post_encode () from md_assemble () | |
15418 | force_automatic_it_block_close () from label habdling functions | |
15419 | ||
15420 | Rationale: | |
15421 | 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), | |
15422 | initializing the IT insn type with a generic initial value depending | |
15423 | on the inst.condition. | |
15424 | 2) During the tencode function, two things may happen: | |
15425 | a) The tencode function overrides the IT insn type by | |
15426 | calling either set_it_insn_type (type) or set_it_insn_type_last (). | |
15427 | b) The tencode function queries the IT block state by | |
15428 | calling in_it_block () (i.e. to determine narrow/not narrow mode). | |
15429 | ||
15430 | Both set_it_insn_type and in_it_block run the internal FSM state | |
15431 | handling function (handle_it_state), because: a) setting the IT insn | |
15432 | type may incur in an invalid state (exiting the function), | |
15433 | and b) querying the state requires the FSM to be updated. | |
15434 | Specifically we want to avoid creating an IT block for conditional | |
15435 | branches, so it_fsm_pre_encode is actually a guess and we can't | |
15436 | determine whether an IT block is required until the tencode () routine | |
15437 | has decided what type of instruction this actually it. | |
15438 | Because of this, if set_it_insn_type and in_it_block have to be used, | |
15439 | set_it_insn_type has to be called first. | |
15440 | ||
15441 | set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that | |
15442 | determines the insn IT type depending on the inst.cond code. | |
15443 | When a tencode () routine encodes an instruction that can be | |
15444 | either outside an IT block, or, in the case of being inside, has to be | |
15445 | the last one, set_it_insn_type_last () will determine the proper | |
15446 | IT instruction type based on the inst.cond code. Otherwise, | |
15447 | set_it_insn_type can be called for overriding that logic or | |
15448 | for covering other cases. | |
15449 | ||
15450 | Calling handle_it_state () may not transition the IT block state to | |
15451 | OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be | |
15452 | still queried. Instead, if the FSM determines that the state should | |
15453 | be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed | |
15454 | after the tencode () function: that's what it_fsm_post_encode () does. | |
15455 | ||
15456 | Since in_it_block () calls the state handling function to get an | |
15457 | updated state, an error may occur (due to invalid insns combination). | |
15458 | In that case, inst.error is set. | |
15459 | Therefore, inst.error has to be checked after the execution of | |
15460 | the tencode () routine. | |
15461 | ||
15462 | 3) Back in md_assemble(), it_fsm_post_encode () is called to commit | |
15463 | any pending state change (if any) that didn't take place in | |
15464 | handle_it_state () as explained above. */ | |
15465 | ||
15466 | static void | |
15467 | it_fsm_pre_encode (void) | |
15468 | { | |
15469 | if (inst.cond != COND_ALWAYS) | |
15470 | inst.it_insn_type = INSIDE_IT_INSN; | |
15471 | else | |
15472 | inst.it_insn_type = OUTSIDE_IT_INSN; | |
15473 | ||
15474 | now_it.state_handled = 0; | |
15475 | } | |
15476 | ||
15477 | /* IT state FSM handling function. */ | |
15478 | ||
15479 | static int | |
15480 | handle_it_state (void) | |
15481 | { | |
15482 | now_it.state_handled = 1; | |
15483 | ||
15484 | switch (now_it.state) | |
15485 | { | |
15486 | case OUTSIDE_IT_BLOCK: | |
15487 | switch (inst.it_insn_type) | |
15488 | { | |
15489 | case OUTSIDE_IT_INSN: | |
15490 | break; | |
15491 | ||
15492 | case INSIDE_IT_INSN: | |
15493 | case INSIDE_IT_LAST_INSN: | |
15494 | if (thumb_mode == 0) | |
15495 | { | |
c921be7d | 15496 | if (unified_syntax |
e07e6e58 NC |
15497 | && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) |
15498 | as_tsktsk (_("Warning: conditional outside an IT block"\ | |
15499 | " for Thumb.")); | |
15500 | } | |
15501 | else | |
15502 | { | |
15503 | if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) | |
15504 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)) | |
15505 | { | |
15506 | /* Automatically generate the IT instruction. */ | |
15507 | new_automatic_it_block (inst.cond); | |
15508 | if (inst.it_insn_type == INSIDE_IT_LAST_INSN) | |
15509 | close_automatic_it_block (); | |
15510 | } | |
15511 | else | |
15512 | { | |
15513 | inst.error = BAD_OUT_IT; | |
15514 | return FAIL; | |
15515 | } | |
15516 | } | |
15517 | break; | |
15518 | ||
15519 | case IF_INSIDE_IT_LAST_INSN: | |
15520 | case NEUTRAL_IT_INSN: | |
15521 | break; | |
15522 | ||
15523 | case IT_INSN: | |
15524 | now_it.state = MANUAL_IT_BLOCK; | |
15525 | now_it.block_length = 0; | |
15526 | break; | |
15527 | } | |
15528 | break; | |
15529 | ||
15530 | case AUTOMATIC_IT_BLOCK: | |
15531 | /* Three things may happen now: | |
15532 | a) We should increment current it block size; | |
15533 | b) We should close current it block (closing insn or 4 insns); | |
15534 | c) We should close current it block and start a new one (due | |
15535 | to incompatible conditions or | |
15536 | 4 insns-length block reached). */ | |
15537 | ||
15538 | switch (inst.it_insn_type) | |
15539 | { | |
15540 | case OUTSIDE_IT_INSN: | |
15541 | /* The closure of the block shall happen immediatelly, | |
15542 | so any in_it_block () call reports the block as closed. */ | |
15543 | force_automatic_it_block_close (); | |
15544 | break; | |
15545 | ||
15546 | case INSIDE_IT_INSN: | |
15547 | case INSIDE_IT_LAST_INSN: | |
15548 | case IF_INSIDE_IT_LAST_INSN: | |
15549 | now_it.block_length++; | |
15550 | ||
15551 | if (now_it.block_length > 4 | |
15552 | || !now_it_compatible (inst.cond)) | |
15553 | { | |
15554 | force_automatic_it_block_close (); | |
15555 | if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN) | |
15556 | new_automatic_it_block (inst.cond); | |
15557 | } | |
15558 | else | |
15559 | { | |
15560 | now_it_add_mask (inst.cond); | |
15561 | } | |
15562 | ||
15563 | if (now_it.state == AUTOMATIC_IT_BLOCK | |
15564 | && (inst.it_insn_type == INSIDE_IT_LAST_INSN | |
15565 | || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN)) | |
15566 | close_automatic_it_block (); | |
15567 | break; | |
15568 | ||
15569 | case NEUTRAL_IT_INSN: | |
15570 | now_it.block_length++; | |
15571 | ||
15572 | if (now_it.block_length > 4) | |
15573 | force_automatic_it_block_close (); | |
15574 | else | |
15575 | now_it_add_mask (now_it.cc & 1); | |
15576 | break; | |
15577 | ||
15578 | case IT_INSN: | |
15579 | close_automatic_it_block (); | |
15580 | now_it.state = MANUAL_IT_BLOCK; | |
15581 | break; | |
15582 | } | |
15583 | break; | |
15584 | ||
15585 | case MANUAL_IT_BLOCK: | |
15586 | { | |
15587 | /* Check conditional suffixes. */ | |
15588 | const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1; | |
15589 | int is_last; | |
15590 | now_it.mask <<= 1; | |
15591 | now_it.mask &= 0x1f; | |
15592 | is_last = (now_it.mask == 0x10); | |
15593 | ||
15594 | switch (inst.it_insn_type) | |
15595 | { | |
15596 | case OUTSIDE_IT_INSN: | |
15597 | inst.error = BAD_NOT_IT; | |
15598 | return FAIL; | |
15599 | ||
15600 | case INSIDE_IT_INSN: | |
15601 | if (cond != inst.cond) | |
15602 | { | |
15603 | inst.error = BAD_IT_COND; | |
15604 | return FAIL; | |
15605 | } | |
15606 | break; | |
15607 | ||
15608 | case INSIDE_IT_LAST_INSN: | |
15609 | case IF_INSIDE_IT_LAST_INSN: | |
15610 | if (cond != inst.cond) | |
15611 | { | |
15612 | inst.error = BAD_IT_COND; | |
15613 | return FAIL; | |
15614 | } | |
15615 | if (!is_last) | |
15616 | { | |
15617 | inst.error = BAD_BRANCH; | |
15618 | return FAIL; | |
15619 | } | |
15620 | break; | |
15621 | ||
15622 | case NEUTRAL_IT_INSN: | |
15623 | /* The BKPT instruction is unconditional even in an IT block. */ | |
15624 | break; | |
15625 | ||
15626 | case IT_INSN: | |
15627 | inst.error = BAD_IT_IT; | |
15628 | return FAIL; | |
15629 | } | |
15630 | } | |
15631 | break; | |
15632 | } | |
15633 | ||
15634 | return SUCCESS; | |
15635 | } | |
15636 | ||
15637 | static void | |
15638 | it_fsm_post_encode (void) | |
15639 | { | |
15640 | int is_last; | |
15641 | ||
15642 | if (!now_it.state_handled) | |
15643 | handle_it_state (); | |
15644 | ||
15645 | is_last = (now_it.mask == 0x10); | |
15646 | if (is_last) | |
15647 | { | |
15648 | now_it.state = OUTSIDE_IT_BLOCK; | |
15649 | now_it.mask = 0; | |
15650 | } | |
15651 | } | |
15652 | ||
15653 | static void | |
15654 | force_automatic_it_block_close (void) | |
15655 | { | |
15656 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
15657 | { | |
15658 | close_automatic_it_block (); | |
15659 | now_it.state = OUTSIDE_IT_BLOCK; | |
15660 | now_it.mask = 0; | |
15661 | } | |
15662 | } | |
15663 | ||
15664 | static int | |
15665 | in_it_block (void) | |
15666 | { | |
15667 | if (!now_it.state_handled) | |
15668 | handle_it_state (); | |
15669 | ||
15670 | return now_it.state != OUTSIDE_IT_BLOCK; | |
15671 | } | |
15672 | ||
c19d1205 ZW |
15673 | void |
15674 | md_assemble (char *str) | |
b99bd4ef | 15675 | { |
c19d1205 ZW |
15676 | char *p = str; |
15677 | const struct asm_opcode * opcode; | |
b99bd4ef | 15678 | |
c19d1205 ZW |
15679 | /* Align the previous label if needed. */ |
15680 | if (last_label_seen != NULL) | |
b99bd4ef | 15681 | { |
c19d1205 ZW |
15682 | symbol_set_frag (last_label_seen, frag_now); |
15683 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
15684 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
15685 | } |
15686 | ||
c19d1205 ZW |
15687 | memset (&inst, '\0', sizeof (inst)); |
15688 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 15689 | |
c19d1205 ZW |
15690 | opcode = opcode_lookup (&p); |
15691 | if (!opcode) | |
b99bd4ef | 15692 | { |
c19d1205 | 15693 | /* It wasn't an instruction, but it might be a register alias of |
dcbf9037 | 15694 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
c921be7d NC |
15695 | if (! create_register_alias (str, p) |
15696 | && ! create_neon_reg_alias (str, p)) | |
c19d1205 | 15697 | as_bad (_("bad instruction `%s'"), str); |
b99bd4ef | 15698 | |
b99bd4ef NC |
15699 | return; |
15700 | } | |
15701 | ||
278df34e | 15702 | if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) |
088fa78e KH |
15703 | as_warn (_("s suffix on comparison instruction is deprecated")); |
15704 | ||
037e8744 JB |
15705 | /* The value which unconditional instructions should have in place of the |
15706 | condition field. */ | |
15707 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; | |
15708 | ||
c19d1205 | 15709 | if (thumb_mode) |
b99bd4ef | 15710 | { |
e74cfd16 | 15711 | arm_feature_set variant; |
8f06b2d8 PB |
15712 | |
15713 | variant = cpu_variant; | |
15714 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
15715 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
15716 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 15717 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
15718 | if (!opcode->tvariant |
15719 | || (thumb_mode == 1 | |
15720 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 15721 | { |
bf3eeda7 | 15722 | as_bad (_("selected processor does not support Thumb mode `%s'"), str); |
b99bd4ef NC |
15723 | return; |
15724 | } | |
c19d1205 ZW |
15725 | if (inst.cond != COND_ALWAYS && !unified_syntax |
15726 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 15727 | { |
c19d1205 | 15728 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
15729 | return; |
15730 | } | |
15731 | ||
752d5da4 | 15732 | if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)) |
076d447c | 15733 | { |
7e806470 | 15734 | if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23 |
752d5da4 NC |
15735 | && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr) |
15736 | || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier))) | |
15737 | { | |
15738 | /* Two things are addressed here. | |
15739 | 1) Implicit require narrow instructions on Thumb-1. | |
15740 | This avoids relaxation accidentally introducing Thumb-2 | |
15741 | instructions. | |
15742 | 2) Reject wide instructions in non Thumb-2 cores. */ | |
15743 | if (inst.size_req == 0) | |
15744 | inst.size_req = 2; | |
15745 | else if (inst.size_req == 4) | |
15746 | { | |
bf3eeda7 | 15747 | as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str); |
752d5da4 NC |
15748 | return; |
15749 | } | |
15750 | } | |
076d447c PB |
15751 | } |
15752 | ||
c19d1205 ZW |
15753 | inst.instruction = opcode->tvalue; |
15754 | ||
5be8be5d | 15755 | if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE)) |
e07e6e58 NC |
15756 | { |
15757 | /* Prepare the it_insn_type for those encodings that don't set | |
15758 | it. */ | |
15759 | it_fsm_pre_encode (); | |
c19d1205 | 15760 | |
e07e6e58 NC |
15761 | opcode->tencode (); |
15762 | ||
15763 | it_fsm_post_encode (); | |
15764 | } | |
e27ec89e | 15765 | |
0110f2b8 | 15766 | if (!(inst.error || inst.relax)) |
b99bd4ef | 15767 | { |
9c2799c2 | 15768 | gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
c19d1205 ZW |
15769 | inst.size = (inst.instruction > 0xffff ? 4 : 2); |
15770 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 15771 | { |
c19d1205 | 15772 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
15773 | return; |
15774 | } | |
15775 | } | |
076d447c PB |
15776 | |
15777 | /* Something has gone badly wrong if we try to relax a fixed size | |
15778 | instruction. */ | |
9c2799c2 | 15779 | gas_assert (inst.size_req == 0 || !inst.relax); |
076d447c | 15780 | |
e74cfd16 PB |
15781 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
15782 | *opcode->tvariant); | |
ee065d83 | 15783 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
708587a4 | 15784 | set those bits when Thumb-2 32-bit instructions are seen. ie. |
7e806470 | 15785 | anything other than bl/blx and v6-M instructions. |
ee065d83 | 15786 | This is overly pessimistic for relaxable instructions. */ |
7e806470 PB |
15787 | if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) |
15788 | || inst.relax) | |
e07e6e58 NC |
15789 | && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) |
15790 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))) | |
e74cfd16 PB |
15791 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
15792 | arm_ext_v6t2); | |
cd000bff | 15793 | |
88714cb8 DG |
15794 | check_neon_suffixes; |
15795 | ||
cd000bff | 15796 | if (!inst.error) |
c877a2f2 NC |
15797 | { |
15798 | mapping_state (MAP_THUMB); | |
15799 | } | |
c19d1205 | 15800 | } |
3e9e4fcf | 15801 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 | 15802 | { |
845b51d6 PB |
15803 | bfd_boolean is_bx; |
15804 | ||
15805 | /* bx is allowed on v5 cores, and sometimes on v4 cores. */ | |
15806 | is_bx = (opcode->aencode == do_bx); | |
15807 | ||
c19d1205 | 15808 | /* Check that this instruction is supported for this CPU. */ |
845b51d6 PB |
15809 | if (!(is_bx && fix_v4bx) |
15810 | && !(opcode->avariant && | |
15811 | ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) | |
b99bd4ef | 15812 | { |
bf3eeda7 | 15813 | as_bad (_("selected processor does not support ARM mode `%s'"), str); |
c19d1205 | 15814 | return; |
b99bd4ef | 15815 | } |
c19d1205 | 15816 | if (inst.size_req) |
b99bd4ef | 15817 | { |
c19d1205 ZW |
15818 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
15819 | return; | |
b99bd4ef NC |
15820 | } |
15821 | ||
c19d1205 ZW |
15822 | inst.instruction = opcode->avalue; |
15823 | if (opcode->tag == OT_unconditionalF) | |
15824 | inst.instruction |= 0xF << 28; | |
15825 | else | |
15826 | inst.instruction |= inst.cond << 28; | |
15827 | inst.size = INSN_SIZE; | |
5be8be5d | 15828 | if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE)) |
e07e6e58 NC |
15829 | { |
15830 | it_fsm_pre_encode (); | |
15831 | opcode->aencode (); | |
15832 | it_fsm_post_encode (); | |
15833 | } | |
ee065d83 PB |
15834 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
15835 | on a hypothetical non-thumb v5 core. */ | |
845b51d6 | 15836 | if (is_bx) |
e74cfd16 | 15837 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); |
ee065d83 | 15838 | else |
e74cfd16 PB |
15839 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
15840 | *opcode->avariant); | |
88714cb8 DG |
15841 | |
15842 | check_neon_suffixes; | |
15843 | ||
cd000bff | 15844 | if (!inst.error) |
c877a2f2 NC |
15845 | { |
15846 | mapping_state (MAP_ARM); | |
15847 | } | |
b99bd4ef | 15848 | } |
3e9e4fcf JB |
15849 | else |
15850 | { | |
15851 | as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " | |
15852 | "-- `%s'"), str); | |
15853 | return; | |
15854 | } | |
c19d1205 ZW |
15855 | output_inst (str); |
15856 | } | |
b99bd4ef | 15857 | |
e07e6e58 NC |
15858 | static void |
15859 | check_it_blocks_finished (void) | |
15860 | { | |
15861 | #ifdef OBJ_ELF | |
15862 | asection *sect; | |
15863 | ||
15864 | for (sect = stdoutput->sections; sect != NULL; sect = sect->next) | |
15865 | if (seg_info (sect)->tc_segment_info_data.current_it.state | |
15866 | == MANUAL_IT_BLOCK) | |
15867 | { | |
15868 | as_warn (_("section '%s' finished with an open IT block."), | |
15869 | sect->name); | |
15870 | } | |
15871 | #else | |
15872 | if (now_it.state == MANUAL_IT_BLOCK) | |
15873 | as_warn (_("file finished with an open IT block.")); | |
15874 | #endif | |
15875 | } | |
15876 | ||
c19d1205 ZW |
15877 | /* Various frobbings of labels and their addresses. */ |
15878 | ||
15879 | void | |
15880 | arm_start_line_hook (void) | |
15881 | { | |
15882 | last_label_seen = NULL; | |
b99bd4ef NC |
15883 | } |
15884 | ||
c19d1205 ZW |
15885 | void |
15886 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 15887 | { |
c19d1205 | 15888 | last_label_seen = sym; |
b99bd4ef | 15889 | |
c19d1205 | 15890 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 15891 | |
c19d1205 ZW |
15892 | #if defined OBJ_COFF || defined OBJ_ELF |
15893 | ARM_SET_INTERWORK (sym, support_interwork); | |
15894 | #endif | |
b99bd4ef | 15895 | |
e07e6e58 NC |
15896 | force_automatic_it_block_close (); |
15897 | ||
5f4273c7 | 15898 | /* Note - do not allow local symbols (.Lxxx) to be labelled |
c19d1205 ZW |
15899 | as Thumb functions. This is because these labels, whilst |
15900 | they exist inside Thumb code, are not the entry points for | |
15901 | possible ARM->Thumb calls. Also, these labels can be used | |
15902 | as part of a computed goto or switch statement. eg gcc | |
15903 | can generate code that looks like this: | |
b99bd4ef | 15904 | |
c19d1205 ZW |
15905 | ldr r2, [pc, .Laaa] |
15906 | lsl r3, r3, #2 | |
15907 | ldr r2, [r3, r2] | |
15908 | mov pc, r2 | |
b99bd4ef | 15909 | |
c19d1205 ZW |
15910 | .Lbbb: .word .Lxxx |
15911 | .Lccc: .word .Lyyy | |
15912 | ..etc... | |
15913 | .Laaa: .word Lbbb | |
b99bd4ef | 15914 | |
c19d1205 ZW |
15915 | The first instruction loads the address of the jump table. |
15916 | The second instruction converts a table index into a byte offset. | |
15917 | The third instruction gets the jump address out of the table. | |
15918 | The fourth instruction performs the jump. | |
b99bd4ef | 15919 | |
c19d1205 ZW |
15920 | If the address stored at .Laaa is that of a symbol which has the |
15921 | Thumb_Func bit set, then the linker will arrange for this address | |
15922 | to have the bottom bit set, which in turn would mean that the | |
15923 | address computation performed by the third instruction would end | |
15924 | up with the bottom bit set. Since the ARM is capable of unaligned | |
15925 | word loads, the instruction would then load the incorrect address | |
15926 | out of the jump table, and chaos would ensue. */ | |
15927 | if (label_is_thumb_function_name | |
15928 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
15929 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 15930 | { |
c19d1205 ZW |
15931 | /* When the address of a Thumb function is taken the bottom |
15932 | bit of that address should be set. This will allow | |
15933 | interworking between Arm and Thumb functions to work | |
15934 | correctly. */ | |
b99bd4ef | 15935 | |
c19d1205 | 15936 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 15937 | |
c19d1205 | 15938 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 15939 | } |
07a53e5c | 15940 | |
07a53e5c | 15941 | dwarf2_emit_label (sym); |
b99bd4ef NC |
15942 | } |
15943 | ||
c921be7d | 15944 | bfd_boolean |
c19d1205 | 15945 | arm_data_in_code (void) |
b99bd4ef | 15946 | { |
c19d1205 | 15947 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 15948 | { |
c19d1205 ZW |
15949 | *input_line_pointer = '/'; |
15950 | input_line_pointer += 5; | |
15951 | *input_line_pointer = 0; | |
c921be7d | 15952 | return TRUE; |
b99bd4ef NC |
15953 | } |
15954 | ||
c921be7d | 15955 | return FALSE; |
b99bd4ef NC |
15956 | } |
15957 | ||
c19d1205 ZW |
15958 | char * |
15959 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 15960 | { |
c19d1205 | 15961 | int len; |
b99bd4ef | 15962 | |
c19d1205 ZW |
15963 | if (thumb_mode && (len = strlen (name)) > 5 |
15964 | && streq (name + len - 5, "/data")) | |
15965 | *(name + len - 5) = 0; | |
b99bd4ef | 15966 | |
c19d1205 | 15967 | return name; |
b99bd4ef | 15968 | } |
c19d1205 ZW |
15969 | \f |
15970 | /* Table of all register names defined by default. The user can | |
15971 | define additional names with .req. Note that all register names | |
15972 | should appear in both upper and lowercase variants. Some registers | |
15973 | also have mixed-case names. */ | |
b99bd4ef | 15974 | |
dcbf9037 | 15975 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
c19d1205 | 15976 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
5287ad62 | 15977 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
c19d1205 ZW |
15978 | #define REGSET(p,t) \ |
15979 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
15980 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
15981 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
15982 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
5287ad62 JB |
15983 | #define REGSETH(p,t) \ |
15984 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
15985 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
15986 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
15987 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) | |
15988 | #define REGSET2(p,t) \ | |
15989 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ | |
15990 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ | |
15991 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ | |
15992 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) | |
7ed4c4c5 | 15993 | |
c19d1205 | 15994 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 15995 | { |
c19d1205 ZW |
15996 | /* ARM integer registers. */ |
15997 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 15998 | |
c19d1205 ZW |
15999 | /* ATPCS synonyms. */ |
16000 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
16001 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
16002 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 16003 | |
c19d1205 ZW |
16004 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
16005 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
16006 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 16007 | |
c19d1205 ZW |
16008 | /* Well-known aliases. */ |
16009 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
16010 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
16011 | ||
16012 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
16013 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
16014 | ||
16015 | /* Coprocessor numbers. */ | |
16016 | REGSET(p, CP), REGSET(P, CP), | |
16017 | ||
16018 | /* Coprocessor register numbers. The "cr" variants are for backward | |
16019 | compatibility. */ | |
16020 | REGSET(c, CN), REGSET(C, CN), | |
16021 | REGSET(cr, CN), REGSET(CR, CN), | |
16022 | ||
16023 | /* FPA registers. */ | |
16024 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
16025 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
16026 | ||
16027 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
16028 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
16029 | ||
16030 | /* VFP SP registers. */ | |
5287ad62 JB |
16031 | REGSET(s,VFS), REGSET(S,VFS), |
16032 | REGSETH(s,VFS), REGSETH(S,VFS), | |
c19d1205 ZW |
16033 | |
16034 | /* VFP DP Registers. */ | |
5287ad62 JB |
16035 | REGSET(d,VFD), REGSET(D,VFD), |
16036 | /* Extra Neon DP registers. */ | |
16037 | REGSETH(d,VFD), REGSETH(D,VFD), | |
16038 | ||
16039 | /* Neon QP registers. */ | |
16040 | REGSET2(q,NQ), REGSET2(Q,NQ), | |
c19d1205 ZW |
16041 | |
16042 | /* VFP control registers. */ | |
16043 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
16044 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
cd2cf30b PB |
16045 | REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), |
16046 | REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), | |
16047 | REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), | |
16048 | REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), | |
c19d1205 ZW |
16049 | |
16050 | /* Maverick DSP coprocessor registers. */ | |
16051 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
16052 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
16053 | ||
16054 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
16055 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
16056 | REGDEF(dspsc,0,DSPSC), | |
16057 | ||
16058 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
16059 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
16060 | REGDEF(DSPSC,0,DSPSC), | |
16061 | ||
16062 | /* iWMMXt data registers - p0, c0-15. */ | |
16063 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
16064 | ||
16065 | /* iWMMXt control registers - p1, c0-3. */ | |
16066 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
16067 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
16068 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
16069 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
16070 | ||
16071 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
16072 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
16073 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
16074 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
16075 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
16076 | ||
16077 | /* XScale accumulator registers. */ | |
16078 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
16079 | }; | |
16080 | #undef REGDEF | |
16081 | #undef REGNUM | |
16082 | #undef REGSET | |
7ed4c4c5 | 16083 | |
c19d1205 ZW |
16084 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
16085 | within psr_required_here. */ | |
16086 | static const struct asm_psr psrs[] = | |
16087 | { | |
16088 | /* Backward compatibility notation. Note that "all" is no longer | |
16089 | truly all possible PSR bits. */ | |
16090 | {"all", PSR_c | PSR_f}, | |
16091 | {"flg", PSR_f}, | |
16092 | {"ctl", PSR_c}, | |
16093 | ||
16094 | /* Individual flags. */ | |
16095 | {"f", PSR_f}, | |
16096 | {"c", PSR_c}, | |
16097 | {"x", PSR_x}, | |
16098 | {"s", PSR_s}, | |
16099 | /* Combinations of flags. */ | |
16100 | {"fs", PSR_f | PSR_s}, | |
16101 | {"fx", PSR_f | PSR_x}, | |
16102 | {"fc", PSR_f | PSR_c}, | |
16103 | {"sf", PSR_s | PSR_f}, | |
16104 | {"sx", PSR_s | PSR_x}, | |
16105 | {"sc", PSR_s | PSR_c}, | |
16106 | {"xf", PSR_x | PSR_f}, | |
16107 | {"xs", PSR_x | PSR_s}, | |
16108 | {"xc", PSR_x | PSR_c}, | |
16109 | {"cf", PSR_c | PSR_f}, | |
16110 | {"cs", PSR_c | PSR_s}, | |
16111 | {"cx", PSR_c | PSR_x}, | |
16112 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
16113 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
16114 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
16115 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
16116 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
16117 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
16118 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
16119 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
16120 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
16121 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
16122 | {"scf", PSR_s | PSR_c | PSR_f}, | |
16123 | {"scx", PSR_s | PSR_c | PSR_x}, | |
16124 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
16125 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
16126 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
16127 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
16128 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
16129 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
16130 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
16131 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
16132 | {"csf", PSR_c | PSR_s | PSR_f}, | |
16133 | {"csx", PSR_c | PSR_s | PSR_x}, | |
16134 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
16135 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
16136 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
16137 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
16138 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
16139 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
16140 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
16141 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
16142 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
16143 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
16144 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
16145 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
16146 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
16147 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
16148 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
16149 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
16150 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
16151 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
16152 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
16153 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
16154 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
16155 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
16156 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
16157 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
16158 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
16159 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
16160 | }; | |
16161 | ||
62b3e311 PB |
16162 | /* Table of V7M psr names. */ |
16163 | static const struct asm_psr v7m_psrs[] = | |
16164 | { | |
2b744c99 PB |
16165 | {"apsr", 0 }, {"APSR", 0 }, |
16166 | {"iapsr", 1 }, {"IAPSR", 1 }, | |
16167 | {"eapsr", 2 }, {"EAPSR", 2 }, | |
16168 | {"psr", 3 }, {"PSR", 3 }, | |
16169 | {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, | |
16170 | {"ipsr", 5 }, {"IPSR", 5 }, | |
16171 | {"epsr", 6 }, {"EPSR", 6 }, | |
16172 | {"iepsr", 7 }, {"IEPSR", 7 }, | |
16173 | {"msp", 8 }, {"MSP", 8 }, | |
16174 | {"psp", 9 }, {"PSP", 9 }, | |
16175 | {"primask", 16}, {"PRIMASK", 16}, | |
16176 | {"basepri", 17}, {"BASEPRI", 17}, | |
16177 | {"basepri_max", 18}, {"BASEPRI_MAX", 18}, | |
16178 | {"faultmask", 19}, {"FAULTMASK", 19}, | |
16179 | {"control", 20}, {"CONTROL", 20} | |
62b3e311 PB |
16180 | }; |
16181 | ||
c19d1205 ZW |
16182 | /* Table of all shift-in-operand names. */ |
16183 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 16184 | { |
c19d1205 ZW |
16185 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
16186 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
16187 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
16188 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
16189 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
16190 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
16191 | }; | |
b99bd4ef | 16192 | |
c19d1205 ZW |
16193 | /* Table of all explicit relocation names. */ |
16194 | #ifdef OBJ_ELF | |
16195 | static struct reloc_entry reloc_names[] = | |
16196 | { | |
16197 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
16198 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
16199 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
16200 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
16201 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
16202 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
16203 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
16204 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
16205 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
16206 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
b43420e6 NC |
16207 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}, |
16208 | { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL} | |
c19d1205 ZW |
16209 | }; |
16210 | #endif | |
b99bd4ef | 16211 | |
c19d1205 ZW |
16212 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
16213 | static const struct asm_cond conds[] = | |
16214 | { | |
16215 | {"eq", 0x0}, | |
16216 | {"ne", 0x1}, | |
16217 | {"cs", 0x2}, {"hs", 0x2}, | |
16218 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
16219 | {"mi", 0x4}, | |
16220 | {"pl", 0x5}, | |
16221 | {"vs", 0x6}, | |
16222 | {"vc", 0x7}, | |
16223 | {"hi", 0x8}, | |
16224 | {"ls", 0x9}, | |
16225 | {"ge", 0xa}, | |
16226 | {"lt", 0xb}, | |
16227 | {"gt", 0xc}, | |
16228 | {"le", 0xd}, | |
16229 | {"al", 0xe} | |
16230 | }; | |
bfae80f2 | 16231 | |
62b3e311 PB |
16232 | static struct asm_barrier_opt barrier_opt_names[] = |
16233 | { | |
16234 | { "sy", 0xf }, | |
16235 | { "un", 0x7 }, | |
16236 | { "st", 0xe }, | |
16237 | { "unst", 0x6 } | |
16238 | }; | |
16239 | ||
c19d1205 ZW |
16240 | /* Table of ARM-format instructions. */ |
16241 | ||
16242 | /* Macros for gluing together operand strings. N.B. In all cases | |
16243 | other than OPS0, the trailing OP_stop comes from default | |
16244 | zero-initialization of the unspecified elements of the array. */ | |
16245 | #define OPS0() { OP_stop, } | |
16246 | #define OPS1(a) { OP_##a, } | |
16247 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
16248 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
16249 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
16250 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
16251 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
16252 | ||
5be8be5d DG |
16253 | /* These macros are similar to the OPSn, but do not prepend the OP_ prefix. |
16254 | This is useful when mixing operands for ARM and THUMB, i.e. using the | |
16255 | MIX_ARM_THUMB_OPERANDS macro. | |
16256 | In order to use these macros, prefix the number of operands with _ | |
16257 | e.g. _3. */ | |
16258 | #define OPS_1(a) { a, } | |
16259 | #define OPS_2(a,b) { a,b, } | |
16260 | #define OPS_3(a,b,c) { a,b,c, } | |
16261 | #define OPS_4(a,b,c,d) { a,b,c,d, } | |
16262 | #define OPS_5(a,b,c,d,e) { a,b,c,d,e, } | |
16263 | #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, } | |
16264 | ||
c19d1205 ZW |
16265 | /* These macros abstract out the exact format of the mnemonic table and |
16266 | save some repeated characters. */ | |
16267 | ||
16268 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
16269 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16270 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 16271 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16272 | |
16273 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
16274 | a T_MNEM_xyz enumerator. */ | |
16275 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
e07e6e58 | 16276 | TxCE (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 16277 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 16278 | TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
16279 | |
16280 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
16281 | infix after the third character. */ | |
16282 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16283 | { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 16284 | THUMB_VARIANT, do_##ae, do_##te } |
088fa78e | 16285 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 16286 | { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ |
088fa78e | 16287 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 16288 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 16289 | TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) |
088fa78e | 16290 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 16291 | TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 16292 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 16293 | TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
088fa78e | 16294 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 16295 | TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
16296 | |
16297 | /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to | |
16298 | appear in the condition table. */ | |
16299 | #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16300 | { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ |
1887dd22 | 16301 | 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16302 | |
16303 | #define TxCM(m1, m2, op, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
16304 | TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \ |
16305 | TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \ | |
16306 | TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \ | |
16307 | TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \ | |
16308 | TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \ | |
16309 | TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \ | |
16310 | TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \ | |
16311 | TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \ | |
16312 | TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \ | |
16313 | TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \ | |
16314 | TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \ | |
16315 | TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \ | |
16316 | TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \ | |
16317 | TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \ | |
16318 | TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \ | |
16319 | TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \ | |
16320 | TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \ | |
16321 | TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \ | |
16322 | TxCM_ (m1, al, m2, op, top, nops, ops, ae, te) | |
c19d1205 ZW |
16323 | |
16324 | #define TCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
16325 | TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te) |
16326 | #define tCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
21d799b5 | 16327 | TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
16328 | |
16329 | /* Mnemonic that cannot be conditionalized. The ARM condition-code | |
dfa9f0d5 PB |
16330 | field is still 0xE. Many of the Thumb variants can be executed |
16331 | conditionally, so this is checked separately. */ | |
c19d1205 | 16332 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 16333 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 16334 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16335 | |
16336 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM | |
16337 | condition code field. */ | |
16338 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16339 | { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 16340 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16341 | |
16342 | /* ARM-only variants of all the above. */ | |
6a86118a | 16343 | #define CE(mnem, op, nops, ops, ae) \ |
21d799b5 | 16344 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
6a86118a NC |
16345 | |
16346 | #define C3(mnem, op, nops, ops, ae) \ | |
16347 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
16348 | ||
e3cb604e PB |
16349 | /* Legacy mnemonics that always have conditional infix after the third |
16350 | character. */ | |
16351 | #define CL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16352 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
16353 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
16354 | ||
8f06b2d8 PB |
16355 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
16356 | #define cCE(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16357 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 16358 | |
e3cb604e PB |
16359 | /* Legacy coprocessor instructions where conditional infix and conditional |
16360 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
16361 | not just the potentially ambiguous ones. */ | |
16362 | #define cCL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16363 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
16364 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
16365 | ||
16366 | /* Coprocessor, takes either a suffix or a position-3 infix | |
16367 | (for an FPA corner case). */ | |
16368 | #define C3E(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16369 | { mnem, OPS##nops ops, OT_csuf_or_in3, \ |
e3cb604e | 16370 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 16371 | |
6a86118a | 16372 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
21d799b5 NC |
16373 | { m1 #m2 m3, OPS##nops ops, \ |
16374 | sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ | |
6a86118a NC |
16375 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
16376 | ||
16377 | #define CM(m1, m2, op, nops, ops, ae) \ | |
e07e6e58 NC |
16378 | xCM_ (m1, , m2, op, nops, ops, ae), \ |
16379 | xCM_ (m1, eq, m2, op, nops, ops, ae), \ | |
16380 | xCM_ (m1, ne, m2, op, nops, ops, ae), \ | |
16381 | xCM_ (m1, cs, m2, op, nops, ops, ae), \ | |
16382 | xCM_ (m1, hs, m2, op, nops, ops, ae), \ | |
16383 | xCM_ (m1, cc, m2, op, nops, ops, ae), \ | |
16384 | xCM_ (m1, ul, m2, op, nops, ops, ae), \ | |
16385 | xCM_ (m1, lo, m2, op, nops, ops, ae), \ | |
16386 | xCM_ (m1, mi, m2, op, nops, ops, ae), \ | |
16387 | xCM_ (m1, pl, m2, op, nops, ops, ae), \ | |
16388 | xCM_ (m1, vs, m2, op, nops, ops, ae), \ | |
16389 | xCM_ (m1, vc, m2, op, nops, ops, ae), \ | |
16390 | xCM_ (m1, hi, m2, op, nops, ops, ae), \ | |
16391 | xCM_ (m1, ls, m2, op, nops, ops, ae), \ | |
16392 | xCM_ (m1, ge, m2, op, nops, ops, ae), \ | |
16393 | xCM_ (m1, lt, m2, op, nops, ops, ae), \ | |
16394 | xCM_ (m1, gt, m2, op, nops, ops, ae), \ | |
16395 | xCM_ (m1, le, m2, op, nops, ops, ae), \ | |
16396 | xCM_ (m1, al, m2, op, nops, ops, ae) | |
6a86118a NC |
16397 | |
16398 | #define UE(mnem, op, nops, ops, ae) \ | |
16399 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
16400 | ||
16401 | #define UF(mnem, op, nops, ops, ae) \ | |
16402 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
16403 | ||
5287ad62 JB |
16404 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
16405 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we | |
16406 | use the same encoding function for each. */ | |
16407 | #define NUF(mnem, op, nops, ops, enc) \ | |
16408 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
16409 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } | |
16410 | ||
16411 | /* Neon data processing, version which indirects through neon_enc_tab for | |
16412 | the various overloaded versions of opcodes. */ | |
16413 | #define nUF(mnem, op, nops, ops, enc) \ | |
21d799b5 | 16414 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
16415 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
16416 | ||
16417 | /* Neon insn with conditional suffix for the ARM version, non-overloaded | |
16418 | version. */ | |
037e8744 JB |
16419 | #define NCE_tag(mnem, op, nops, ops, enc, tag) \ |
16420 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ | |
5287ad62 JB |
16421 | THUMB_VARIANT, do_##enc, do_##enc } |
16422 | ||
037e8744 | 16423 | #define NCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 16424 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
16425 | |
16426 | #define NCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 16427 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 16428 | |
5287ad62 | 16429 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
037e8744 | 16430 | #define nCE_tag(mnem, op, nops, ops, enc, tag) \ |
21d799b5 | 16431 | { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
16432 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
16433 | ||
037e8744 | 16434 | #define nCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 16435 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
16436 | |
16437 | #define nCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 16438 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 16439 | |
c19d1205 ZW |
16440 | #define do_0 0 |
16441 | ||
c19d1205 | 16442 | static const struct asm_opcode insns[] = |
bfae80f2 | 16443 | { |
e74cfd16 PB |
16444 | #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ |
16445 | #define THUMB_VARIANT &arm_ext_v4t | |
21d799b5 NC |
16446 | tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c), |
16447 | tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
16448 | tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
16449 | tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
16450 | tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
16451 | tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
16452 | tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub), | |
16453 | tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub), | |
16454 | tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
16455 | tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
16456 | tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
16457 | tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
16458 | tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
16459 | tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
16460 | tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3), | |
16461 | tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3), | |
c19d1205 ZW |
16462 | |
16463 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
16464 | for setting PSR flag bits. They are obsolete in V6 and do not | |
16465 | have Thumb equivalents. */ | |
21d799b5 NC |
16466 | tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), |
16467 | tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), | |
16468 | CL("tstp", 110f000, 2, (RR, SH), cmp), | |
16469 | tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
16470 | tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
16471 | CL("cmpp", 150f000, 2, (RR, SH), cmp), | |
16472 | tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
16473 | tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
16474 | CL("cmnp", 170f000, 2, (RR, SH), cmp), | |
16475 | ||
16476 | tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp), | |
16477 | tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp), | |
16478 | tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst), | |
16479 | tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst), | |
16480 | ||
16481 | tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
5be8be5d DG |
16482 | tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), |
16483 | tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR, | |
16484 | OP_RRnpc), | |
16485 | OP_ADDRGLDR),ldst, t_ldst), | |
16486 | tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), | |
21d799b5 NC |
16487 | |
16488 | tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16489 | tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16490 | tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16491 | tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16492 | tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16493 | tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16494 | ||
16495 | TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), | |
16496 | TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), | |
16497 | tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), | |
16498 | TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), | |
bfae80f2 | 16499 | |
c19d1205 | 16500 | /* Pseudo ops. */ |
21d799b5 | 16501 | tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac | 16502 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
21d799b5 | 16503 | tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop), |
c19d1205 ZW |
16504 | |
16505 | /* Thumb-compatibility pseudo ops. */ | |
21d799b5 NC |
16506 | tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift), |
16507 | tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift), | |
16508 | tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift), | |
16509 | tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
16510 | tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift), | |
16511 | tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift), | |
16512 | tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift), | |
16513 | tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift), | |
16514 | tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg), | |
16515 | tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg), | |
16516 | tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop), | |
16517 | tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop), | |
c19d1205 | 16518 | |
16a4cf17 | 16519 | /* These may simplify to neg. */ |
21d799b5 NC |
16520 | TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
16521 | TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
16a4cf17 | 16522 | |
c921be7d NC |
16523 | #undef THUMB_VARIANT |
16524 | #define THUMB_VARIANT & arm_ext_v6 | |
16525 | ||
21d799b5 | 16526 | TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
16527 | |
16528 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
c921be7d NC |
16529 | #undef THUMB_VARIANT |
16530 | #define THUMB_VARIANT & arm_ext_v6t2 | |
16531 | ||
21d799b5 NC |
16532 | TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
16533 | TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
16534 | CL("teqp", 130f000, 2, (RR, SH), cmp), | |
c19d1205 | 16535 | |
5be8be5d DG |
16536 | TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
16537 | TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
16538 | TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt), | |
16539 | TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
c19d1205 | 16540 | |
21d799b5 NC |
16541 | TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
16542 | TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 16543 | |
21d799b5 NC |
16544 | TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
16545 | TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
16546 | |
16547 | /* V1 instructions with no Thumb analogue at all. */ | |
21d799b5 | 16548 | CE("rsc", 0e00000, 3, (RR, oRR, SH), arit), |
c19d1205 ZW |
16549 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), |
16550 | ||
16551 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
16552 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
16553 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
16554 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
16555 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
16556 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
16557 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
16558 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
16559 | ||
c921be7d NC |
16560 | #undef ARM_VARIANT |
16561 | #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ | |
16562 | #undef THUMB_VARIANT | |
16563 | #define THUMB_VARIANT & arm_ext_v4t | |
16564 | ||
21d799b5 NC |
16565 | tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
16566 | tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
c19d1205 | 16567 | |
c921be7d NC |
16568 | #undef THUMB_VARIANT |
16569 | #define THUMB_VARIANT & arm_ext_v6t2 | |
16570 | ||
21d799b5 | 16571 | TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
c19d1205 ZW |
16572 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), |
16573 | ||
16574 | /* Generic coprocessor instructions. */ | |
21d799b5 NC |
16575 | TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
16576 | TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16577 | TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16578 | TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16579 | TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16580 | TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
16581 | TCE("mrc", e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 16582 | |
c921be7d NC |
16583 | #undef ARM_VARIANT |
16584 | #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ | |
16585 | ||
21d799b5 | 16586 | CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
c19d1205 ZW |
16587 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
16588 | ||
c921be7d NC |
16589 | #undef ARM_VARIANT |
16590 | #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ | |
16591 | #undef THUMB_VARIANT | |
16592 | #define THUMB_VARIANT & arm_ext_msr | |
16593 | ||
21d799b5 NC |
16594 | TCE("mrs", 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs), |
16595 | TCE("msr", 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr), | |
c19d1205 | 16596 | |
c921be7d NC |
16597 | #undef ARM_VARIANT |
16598 | #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ | |
16599 | #undef THUMB_VARIANT | |
16600 | #define THUMB_VARIANT & arm_ext_v6t2 | |
16601 | ||
21d799b5 NC |
16602 | TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
16603 | CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
16604 | TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
16605 | CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
16606 | TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
16607 | CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
16608 | TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
16609 | CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
c19d1205 | 16610 | |
c921be7d NC |
16611 | #undef ARM_VARIANT |
16612 | #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ | |
16613 | #undef THUMB_VARIANT | |
16614 | #define THUMB_VARIANT & arm_ext_v4t | |
16615 | ||
5be8be5d DG |
16616 | tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
16617 | tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
16618 | tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
16619 | tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
16620 | tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
16621 | tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
c19d1205 | 16622 | |
c921be7d NC |
16623 | #undef ARM_VARIANT |
16624 | #define ARM_VARIANT & arm_ext_v4t_5 | |
16625 | ||
c19d1205 ZW |
16626 | /* ARM Architecture 4T. */ |
16627 | /* Note: bx (and blx) are required on V5, even if the processor does | |
16628 | not support Thumb. */ | |
21d799b5 | 16629 | TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx), |
c19d1205 | 16630 | |
c921be7d NC |
16631 | #undef ARM_VARIANT |
16632 | #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ | |
16633 | #undef THUMB_VARIANT | |
16634 | #define THUMB_VARIANT & arm_ext_v5t | |
16635 | ||
c19d1205 ZW |
16636 | /* Note: blx has 2 variants; the .value coded here is for |
16637 | BLX(2). Only this variant has conditional execution. */ | |
21d799b5 NC |
16638 | TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx), |
16639 | TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
c19d1205 | 16640 | |
c921be7d NC |
16641 | #undef THUMB_VARIANT |
16642 | #define THUMB_VARIANT & arm_ext_v6t2 | |
16643 | ||
21d799b5 NC |
16644 | TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
16645 | TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16646 | TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16647 | TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16648 | TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16649 | TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
16650 | TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
16651 | TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 16652 | |
c921be7d NC |
16653 | #undef ARM_VARIANT |
16654 | #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ | |
9e3c6df6 PB |
16655 | #undef THUMB_VARIANT |
16656 | #define THUMB_VARIANT &arm_ext_v5exp | |
c921be7d | 16657 | |
21d799b5 NC |
16658 | TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
16659 | TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
16660 | TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
16661 | TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 16662 | |
21d799b5 NC |
16663 | TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
16664 | TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 16665 | |
21d799b5 NC |
16666 | TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
16667 | TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
16668 | TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
16669 | TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
c19d1205 | 16670 | |
21d799b5 NC |
16671 | TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
16672 | TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16673 | TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16674 | TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 16675 | |
21d799b5 NC |
16676 | TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
16677 | TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 16678 | |
03ee1b7f NC |
16679 | TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
16680 | TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
16681 | TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
16682 | TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
c19d1205 | 16683 | |
c921be7d NC |
16684 | #undef ARM_VARIANT |
16685 | #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ | |
9e3c6df6 PB |
16686 | #undef THUMB_VARIANT |
16687 | #define THUMB_VARIANT &arm_ext_v6t2 | |
c921be7d | 16688 | |
21d799b5 | 16689 | TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld), |
5be8be5d DG |
16690 | TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS), |
16691 | ldrd, t_ldstd), | |
16692 | TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp, | |
16693 | ADDRGLDRS), ldrd, t_ldstd), | |
c19d1205 | 16694 | |
21d799b5 NC |
16695 | TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
16696 | TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
c19d1205 | 16697 | |
c921be7d NC |
16698 | #undef ARM_VARIANT |
16699 | #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ | |
16700 | ||
21d799b5 | 16701 | TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
c19d1205 | 16702 | |
c921be7d NC |
16703 | #undef ARM_VARIANT |
16704 | #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ | |
16705 | #undef THUMB_VARIANT | |
16706 | #define THUMB_VARIANT & arm_ext_v6 | |
16707 | ||
21d799b5 NC |
16708 | TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
16709 | TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
16710 | tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
16711 | tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
16712 | tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
16713 | tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16714 | tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16715 | tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16716 | tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16717 | TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), | |
c19d1205 | 16718 | |
c921be7d NC |
16719 | #undef THUMB_VARIANT |
16720 | #define THUMB_VARIANT & arm_ext_v6t2 | |
16721 | ||
5be8be5d DG |
16722 | TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), |
16723 | TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
16724 | strex, t_strex), | |
21d799b5 NC |
16725 | TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
16726 | TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 | 16727 | |
21d799b5 NC |
16728 | TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), |
16729 | TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
62b3e311 | 16730 | |
9e3c6df6 | 16731 | /* ARM V6 not included in V7M. */ |
c921be7d NC |
16732 | #undef THUMB_VARIANT |
16733 | #define THUMB_VARIANT & arm_ext_v6_notm | |
9e3c6df6 PB |
16734 | TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
16735 | UF(rfeib, 9900a00, 1, (RRw), rfe), | |
16736 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
16737 | TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
16738 | TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
16739 | UF(rfefa, 9900a00, 1, (RRw), rfe), | |
16740 | UF(rfeea, 8100a00, 1, (RRw), rfe), | |
16741 | TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
16742 | TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), | |
16743 | UF(srsib, 9c00500, 2, (oRRw, I31w), srs), | |
16744 | UF(srsda, 8400500, 2, (oRRw, I31w), srs), | |
16745 | TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), | |
c921be7d | 16746 | |
9e3c6df6 PB |
16747 | /* ARM V6 not included in V7M (eg. integer SIMD). */ |
16748 | #undef THUMB_VARIANT | |
16749 | #define THUMB_VARIANT & arm_ext_v6_dsp | |
21d799b5 NC |
16750 | TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
16751 | TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), | |
16752 | TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
16753 | TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16754 | TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16755 | TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16756 | /* Old name for QASX. */ |
21d799b5 NC |
16757 | TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16758 | TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16759 | /* Old name for QSAX. */ |
21d799b5 NC |
16760 | TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16761 | TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16762 | TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16763 | TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16764 | TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16765 | TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16766 | /* Old name for SASX. */ |
21d799b5 NC |
16767 | TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16768 | TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16769 | TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16770 | TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16771 | /* Old name for SHASX. */ |
21d799b5 NC |
16772 | TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16773 | TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16774 | /* Old name for SHSAX. */ |
21d799b5 NC |
16775 | TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16776 | TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16777 | TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16778 | TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16779 | /* Old name for SSAX. */ |
21d799b5 NC |
16780 | TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16781 | TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16782 | TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16783 | TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16784 | TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16785 | TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16786 | /* Old name for UASX. */ |
21d799b5 NC |
16787 | TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16788 | TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16789 | TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16790 | TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16791 | /* Old name for UHASX. */ |
21d799b5 NC |
16792 | TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16793 | TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16794 | /* Old name for UHSAX. */ |
21d799b5 NC |
16795 | TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16796 | TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16797 | TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16798 | TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16799 | TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16800 | TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16801 | /* Old name for UQASX. */ |
21d799b5 NC |
16802 | TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16803 | TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16804 | /* Old name for UQSAX. */ |
21d799b5 NC |
16805 | TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16806 | TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16807 | TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16808 | TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16809 | TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16810 | /* Old name for USAX. */ |
21d799b5 NC |
16811 | TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16812 | TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
21d799b5 NC |
16813 | TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
16814 | TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16815 | TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16816 | TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16817 | TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16818 | TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16819 | TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16820 | TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16821 | TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16822 | TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16823 | TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16824 | TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
16825 | TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
16826 | TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16827 | TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16828 | TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
16829 | TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
16830 | TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16831 | TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16832 | TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16833 | TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16834 | TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16835 | TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16836 | TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16837 | TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16838 | TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16839 | TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
21d799b5 NC |
16840 | TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
16841 | TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
16842 | TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16843 | TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16844 | TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
c19d1205 | 16845 | |
c921be7d NC |
16846 | #undef ARM_VARIANT |
16847 | #define ARM_VARIANT & arm_ext_v6k | |
16848 | #undef THUMB_VARIANT | |
16849 | #define THUMB_VARIANT & arm_ext_v6k | |
16850 | ||
21d799b5 NC |
16851 | tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), |
16852 | tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), | |
16853 | tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint), | |
16854 | tCE("sev", 320f004, _sev, 0, (), noargs, t_hint), | |
c19d1205 | 16855 | |
c921be7d NC |
16856 | #undef THUMB_VARIANT |
16857 | #define THUMB_VARIANT & arm_ext_v6_notm | |
5be8be5d DG |
16858 | TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb), |
16859 | ldrexd, t_ldrexd), | |
16860 | TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp, | |
16861 | RRnpcb), strexd, t_strexd), | |
ebdca51a | 16862 | |
c921be7d NC |
16863 | #undef THUMB_VARIANT |
16864 | #define THUMB_VARIANT & arm_ext_v6t2 | |
5be8be5d DG |
16865 | TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), |
16866 | rd_rn, rd_rn), | |
16867 | TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), | |
16868 | rd_rn, rd_rn), | |
16869 | TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
16870 | strex, rm_rd_rn), | |
16871 | TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
16872 | strex, rm_rd_rn), | |
21d799b5 | 16873 | TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
c19d1205 | 16874 | |
c921be7d NC |
16875 | #undef ARM_VARIANT |
16876 | #define ARM_VARIANT & arm_ext_v6z | |
16877 | ||
21d799b5 | 16878 | TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 | 16879 | |
c921be7d NC |
16880 | #undef ARM_VARIANT |
16881 | #define ARM_VARIANT & arm_ext_v6t2 | |
16882 | ||
21d799b5 NC |
16883 | TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
16884 | TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
16885 | TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
16886 | TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
c19d1205 | 16887 | |
21d799b5 NC |
16888 | TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
16889 | TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), | |
16890 | TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), | |
16891 | TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), | |
c19d1205 | 16892 | |
5be8be5d DG |
16893 | TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
16894 | TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
16895 | TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
16896 | TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
c19d1205 | 16897 | |
bf3eeda7 NS |
16898 | /* Thumb-only instructions. */ |
16899 | #undef ARM_VARIANT | |
16900 | #define ARM_VARIANT NULL | |
16901 | TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz), | |
16902 | TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz), | |
c921be7d NC |
16903 | |
16904 | /* ARM does not really have an IT instruction, so always allow it. | |
16905 | The opcode is copied from Thumb in order to allow warnings in | |
16906 | -mimplicit-it=[never | arm] modes. */ | |
16907 | #undef ARM_VARIANT | |
16908 | #define ARM_VARIANT & arm_ext_v1 | |
16909 | ||
21d799b5 NC |
16910 | TUE("it", bf08, bf08, 1, (COND), it, t_it), |
16911 | TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), | |
16912 | TUE("ite", bf04, bf04, 1, (COND), it, t_it), | |
16913 | TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it), | |
16914 | TUE("itet", bf06, bf06, 1, (COND), it, t_it), | |
16915 | TUE("itte", bf0a, bf0a, 1, (COND), it, t_it), | |
16916 | TUE("itee", bf02, bf02, 1, (COND), it, t_it), | |
16917 | TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it), | |
16918 | TUE("itett", bf07, bf07, 1, (COND), it, t_it), | |
16919 | TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it), | |
16920 | TUE("iteet", bf03, bf03, 1, (COND), it, t_it), | |
16921 | TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it), | |
16922 | TUE("itete", bf05, bf05, 1, (COND), it, t_it), | |
16923 | TUE("ittee", bf09, bf09, 1, (COND), it, t_it), | |
16924 | TUE("iteee", bf01, bf01, 1, (COND), it, t_it), | |
1c444d06 | 16925 | /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ |
21d799b5 NC |
16926 | TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), |
16927 | TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), | |
c19d1205 | 16928 | |
92e90b6e | 16929 | /* Thumb2 only instructions. */ |
c921be7d NC |
16930 | #undef ARM_VARIANT |
16931 | #define ARM_VARIANT NULL | |
92e90b6e | 16932 | |
21d799b5 NC |
16933 | TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
16934 | TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
16935 | TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), | |
16936 | TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), | |
16937 | TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb), | |
16938 | TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb), | |
92e90b6e | 16939 | |
62b3e311 | 16940 | /* Thumb-2 hardware division instructions (R and M profiles only). */ |
c921be7d NC |
16941 | #undef THUMB_VARIANT |
16942 | #define THUMB_VARIANT & arm_ext_div | |
16943 | ||
21d799b5 NC |
16944 | TCE("sdiv", 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div), |
16945 | TCE("udiv", 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div), | |
62b3e311 | 16946 | |
7e806470 | 16947 | /* ARM V6M/V7 instructions. */ |
c921be7d NC |
16948 | #undef ARM_VARIANT |
16949 | #define ARM_VARIANT & arm_ext_barrier | |
16950 | #undef THUMB_VARIANT | |
16951 | #define THUMB_VARIANT & arm_ext_barrier | |
16952 | ||
21d799b5 NC |
16953 | TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier), |
16954 | TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier), | |
16955 | TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier), | |
7e806470 | 16956 | |
62b3e311 | 16957 | /* ARM V7 instructions. */ |
c921be7d NC |
16958 | #undef ARM_VARIANT |
16959 | #define ARM_VARIANT & arm_ext_v7 | |
16960 | #undef THUMB_VARIANT | |
16961 | #define THUMB_VARIANT & arm_ext_v7 | |
16962 | ||
21d799b5 NC |
16963 | TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld), |
16964 | TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
62b3e311 | 16965 | |
c921be7d NC |
16966 | #undef ARM_VARIANT |
16967 | #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ | |
16968 | ||
21d799b5 NC |
16969 | cCE("wfs", e200110, 1, (RR), rd), |
16970 | cCE("rfs", e300110, 1, (RR), rd), | |
16971 | cCE("wfc", e400110, 1, (RR), rd), | |
16972 | cCE("rfc", e500110, 1, (RR), rd), | |
16973 | ||
16974 | cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
16975 | cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
16976 | cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
16977 | cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
16978 | ||
16979 | cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
16980 | cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
16981 | cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
16982 | cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
16983 | ||
16984 | cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm), | |
16985 | cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm), | |
16986 | cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm), | |
16987 | cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm), | |
16988 | cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm), | |
16989 | cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm), | |
16990 | cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm), | |
16991 | cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm), | |
16992 | cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm), | |
16993 | cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm), | |
16994 | cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm), | |
16995 | cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm), | |
16996 | ||
16997 | cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm), | |
16998 | cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm), | |
16999 | cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm), | |
17000 | cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm), | |
17001 | cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm), | |
17002 | cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm), | |
17003 | cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm), | |
17004 | cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm), | |
17005 | cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm), | |
17006 | cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm), | |
17007 | cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm), | |
17008 | cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm), | |
17009 | ||
17010 | cCL("abss", e208100, 2, (RF, RF_IF), rd_rm), | |
17011 | cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm), | |
17012 | cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm), | |
17013 | cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm), | |
17014 | cCL("absd", e208180, 2, (RF, RF_IF), rd_rm), | |
17015 | cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm), | |
17016 | cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm), | |
17017 | cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm), | |
17018 | cCL("abse", e288100, 2, (RF, RF_IF), rd_rm), | |
17019 | cCL("absep", e288120, 2, (RF, RF_IF), rd_rm), | |
17020 | cCL("absem", e288140, 2, (RF, RF_IF), rd_rm), | |
17021 | cCL("absez", e288160, 2, (RF, RF_IF), rd_rm), | |
17022 | ||
17023 | cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm), | |
17024 | cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm), | |
17025 | cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm), | |
17026 | cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm), | |
17027 | cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm), | |
17028 | cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm), | |
17029 | cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm), | |
17030 | cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm), | |
17031 | cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm), | |
17032 | cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm), | |
17033 | cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm), | |
17034 | cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm), | |
17035 | ||
17036 | cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm), | |
17037 | cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm), | |
17038 | cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm), | |
17039 | cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm), | |
17040 | cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm), | |
17041 | cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm), | |
17042 | cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm), | |
17043 | cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm), | |
17044 | cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm), | |
17045 | cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm), | |
17046 | cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm), | |
17047 | cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm), | |
17048 | ||
17049 | cCL("logs", e508100, 2, (RF, RF_IF), rd_rm), | |
17050 | cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm), | |
17051 | cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm), | |
17052 | cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm), | |
17053 | cCL("logd", e508180, 2, (RF, RF_IF), rd_rm), | |
17054 | cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm), | |
17055 | cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm), | |
17056 | cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm), | |
17057 | cCL("loge", e588100, 2, (RF, RF_IF), rd_rm), | |
17058 | cCL("logep", e588120, 2, (RF, RF_IF), rd_rm), | |
17059 | cCL("logem", e588140, 2, (RF, RF_IF), rd_rm), | |
17060 | cCL("logez", e588160, 2, (RF, RF_IF), rd_rm), | |
17061 | ||
17062 | cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm), | |
17063 | cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm), | |
17064 | cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm), | |
17065 | cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm), | |
17066 | cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm), | |
17067 | cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm), | |
17068 | cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm), | |
17069 | cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm), | |
17070 | cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm), | |
17071 | cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm), | |
17072 | cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm), | |
17073 | cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm), | |
17074 | ||
17075 | cCL("exps", e708100, 2, (RF, RF_IF), rd_rm), | |
17076 | cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm), | |
17077 | cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm), | |
17078 | cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm), | |
17079 | cCL("expd", e708180, 2, (RF, RF_IF), rd_rm), | |
17080 | cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm), | |
17081 | cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm), | |
17082 | cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm), | |
17083 | cCL("expe", e788100, 2, (RF, RF_IF), rd_rm), | |
17084 | cCL("expep", e788120, 2, (RF, RF_IF), rd_rm), | |
17085 | cCL("expem", e788140, 2, (RF, RF_IF), rd_rm), | |
17086 | cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm), | |
17087 | ||
17088 | cCL("sins", e808100, 2, (RF, RF_IF), rd_rm), | |
17089 | cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm), | |
17090 | cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm), | |
17091 | cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm), | |
17092 | cCL("sind", e808180, 2, (RF, RF_IF), rd_rm), | |
17093 | cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm), | |
17094 | cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm), | |
17095 | cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm), | |
17096 | cCL("sine", e888100, 2, (RF, RF_IF), rd_rm), | |
17097 | cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm), | |
17098 | cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm), | |
17099 | cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm), | |
17100 | ||
17101 | cCL("coss", e908100, 2, (RF, RF_IF), rd_rm), | |
17102 | cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm), | |
17103 | cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm), | |
17104 | cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm), | |
17105 | cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm), | |
17106 | cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm), | |
17107 | cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm), | |
17108 | cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm), | |
17109 | cCL("cose", e988100, 2, (RF, RF_IF), rd_rm), | |
17110 | cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm), | |
17111 | cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm), | |
17112 | cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm), | |
17113 | ||
17114 | cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm), | |
17115 | cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm), | |
17116 | cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm), | |
17117 | cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm), | |
17118 | cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm), | |
17119 | cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm), | |
17120 | cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm), | |
17121 | cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm), | |
17122 | cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm), | |
17123 | cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm), | |
17124 | cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm), | |
17125 | cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm), | |
17126 | ||
17127 | cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm), | |
17128 | cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm), | |
17129 | cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm), | |
17130 | cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm), | |
17131 | cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm), | |
17132 | cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm), | |
17133 | cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm), | |
17134 | cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm), | |
17135 | cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm), | |
17136 | cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm), | |
17137 | cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm), | |
17138 | cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm), | |
17139 | ||
17140 | cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm), | |
17141 | cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm), | |
17142 | cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm), | |
17143 | cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm), | |
17144 | cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm), | |
17145 | cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm), | |
17146 | cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm), | |
17147 | cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm), | |
17148 | cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm), | |
17149 | cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm), | |
17150 | cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm), | |
17151 | cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm), | |
17152 | ||
17153 | cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm), | |
17154 | cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm), | |
17155 | cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm), | |
17156 | cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm), | |
17157 | cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm), | |
17158 | cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm), | |
17159 | cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm), | |
17160 | cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm), | |
17161 | cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm), | |
17162 | cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm), | |
17163 | cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm), | |
17164 | cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm), | |
17165 | ||
17166 | cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm), | |
17167 | cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm), | |
17168 | cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm), | |
17169 | cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm), | |
17170 | cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm), | |
17171 | cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm), | |
17172 | cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm), | |
17173 | cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm), | |
17174 | cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm), | |
17175 | cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm), | |
17176 | cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm), | |
17177 | cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm), | |
17178 | ||
17179 | cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm), | |
17180 | cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm), | |
17181 | cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm), | |
17182 | cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm), | |
17183 | cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm), | |
17184 | cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm), | |
17185 | cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm), | |
17186 | cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm), | |
17187 | cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm), | |
17188 | cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm), | |
17189 | cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm), | |
17190 | cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm), | |
17191 | ||
17192 | cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17193 | cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17194 | cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17195 | cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17196 | cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17197 | cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17198 | cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17199 | cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17200 | cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17201 | cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17202 | cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17203 | cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17204 | ||
17205 | cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17206 | cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17207 | cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17208 | cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17209 | cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17210 | cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17211 | cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17212 | cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17213 | cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17214 | cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17215 | cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17216 | cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17217 | ||
17218 | cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17219 | cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17220 | cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17221 | cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17222 | cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17223 | cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17224 | cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17225 | cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17226 | cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17227 | cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17228 | cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17229 | cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17230 | ||
17231 | cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17232 | cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17233 | cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17234 | cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17235 | cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17236 | cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17237 | cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17238 | cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17239 | cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17240 | cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17241 | cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17242 | cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17243 | ||
17244 | cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17245 | cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17246 | cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17247 | cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17248 | cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17249 | cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17250 | cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17251 | cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17252 | cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17253 | cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17254 | cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17255 | cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17256 | ||
17257 | cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17258 | cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17259 | cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17260 | cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17261 | cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17262 | cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17263 | cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17264 | cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17265 | cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17266 | cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17267 | cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17268 | cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17269 | ||
17270 | cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17271 | cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17272 | cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17273 | cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17274 | cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17275 | cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17276 | cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17277 | cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17278 | cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17279 | cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17280 | cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17281 | cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17282 | ||
17283 | cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17284 | cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17285 | cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17286 | cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17287 | cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17288 | cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17289 | cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17290 | cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17291 | cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17292 | cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17293 | cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17294 | cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17295 | ||
17296 | cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17297 | cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17298 | cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17299 | cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17300 | cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17301 | cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17302 | cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17303 | cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17304 | cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17305 | cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17306 | cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17307 | cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17308 | ||
17309 | cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17310 | cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17311 | cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17312 | cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17313 | cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17314 | cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17315 | cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17316 | cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17317 | cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17318 | cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17319 | cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17320 | cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17321 | ||
17322 | cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17323 | cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17324 | cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17325 | cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17326 | cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17327 | cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17328 | cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17329 | cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17330 | cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17331 | cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17332 | cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17333 | cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17334 | ||
17335 | cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17336 | cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17337 | cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17338 | cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17339 | cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17340 | cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17341 | cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17342 | cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17343 | cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17344 | cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17345 | cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17346 | cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17347 | ||
17348 | cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17349 | cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17350 | cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17351 | cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17352 | cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17353 | cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17354 | cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17355 | cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17356 | cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17357 | cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17358 | cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17359 | cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17360 | ||
17361 | cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp), | |
17362 | C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp), | |
17363 | cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp), | |
17364 | C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp), | |
17365 | ||
17366 | cCL("flts", e000110, 2, (RF, RR), rn_rd), | |
17367 | cCL("fltsp", e000130, 2, (RF, RR), rn_rd), | |
17368 | cCL("fltsm", e000150, 2, (RF, RR), rn_rd), | |
17369 | cCL("fltsz", e000170, 2, (RF, RR), rn_rd), | |
17370 | cCL("fltd", e000190, 2, (RF, RR), rn_rd), | |
17371 | cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd), | |
17372 | cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd), | |
17373 | cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd), | |
17374 | cCL("flte", e080110, 2, (RF, RR), rn_rd), | |
17375 | cCL("fltep", e080130, 2, (RF, RR), rn_rd), | |
17376 | cCL("fltem", e080150, 2, (RF, RR), rn_rd), | |
17377 | cCL("fltez", e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 17378 | |
c19d1205 ZW |
17379 | /* The implementation of the FIX instruction is broken on some |
17380 | assemblers, in that it accepts a precision specifier as well as a | |
17381 | rounding specifier, despite the fact that this is meaningless. | |
17382 | To be more compatible, we accept it as well, though of course it | |
17383 | does not set any bits. */ | |
21d799b5 NC |
17384 | cCE("fix", e100110, 2, (RR, RF), rd_rm), |
17385 | cCL("fixp", e100130, 2, (RR, RF), rd_rm), | |
17386 | cCL("fixm", e100150, 2, (RR, RF), rd_rm), | |
17387 | cCL("fixz", e100170, 2, (RR, RF), rd_rm), | |
17388 | cCL("fixsp", e100130, 2, (RR, RF), rd_rm), | |
17389 | cCL("fixsm", e100150, 2, (RR, RF), rd_rm), | |
17390 | cCL("fixsz", e100170, 2, (RR, RF), rd_rm), | |
17391 | cCL("fixdp", e100130, 2, (RR, RF), rd_rm), | |
17392 | cCL("fixdm", e100150, 2, (RR, RF), rd_rm), | |
17393 | cCL("fixdz", e100170, 2, (RR, RF), rd_rm), | |
17394 | cCL("fixep", e100130, 2, (RR, RF), rd_rm), | |
17395 | cCL("fixem", e100150, 2, (RR, RF), rd_rm), | |
17396 | cCL("fixez", e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 17397 | |
c19d1205 | 17398 | /* Instructions that were new with the real FPA, call them V2. */ |
c921be7d NC |
17399 | #undef ARM_VARIANT |
17400 | #define ARM_VARIANT & fpu_fpa_ext_v2 | |
17401 | ||
21d799b5 NC |
17402 | cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
17403 | cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
17404 | cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
17405 | cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
17406 | cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
17407 | cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 | 17408 | |
c921be7d NC |
17409 | #undef ARM_VARIANT |
17410 | #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ | |
17411 | ||
c19d1205 | 17412 | /* Moves and type conversions. */ |
21d799b5 NC |
17413 | cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
17414 | cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
17415 | cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
17416 | cCE("fmstat", ef1fa10, 0, (), noargs), | |
f7c21dc7 NC |
17417 | cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs), |
17418 | cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr), | |
21d799b5 NC |
17419 | cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), |
17420 | cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
17421 | cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
17422 | cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
17423 | cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
17424 | cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
17425 | cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn), | |
17426 | cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
17427 | |
17428 | /* Memory operations. */ | |
21d799b5 NC |
17429 | cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
17430 | cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), | |
17431 | cCE("fldmias", c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
17432 | cCE("fldmfds", c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
17433 | cCE("fldmdbs", d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
17434 | cCE("fldmeas", d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
17435 | cCE("fldmiax", c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
17436 | cCE("fldmfdx", c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
17437 | cCE("fldmdbx", d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
17438 | cCE("fldmeax", d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
17439 | cCE("fstmias", c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
17440 | cCE("fstmeas", c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
17441 | cCE("fstmdbs", d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
17442 | cCE("fstmfds", d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
17443 | cCE("fstmiax", c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
17444 | cCE("fstmeax", c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
17445 | cCE("fstmdbx", d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
17446 | cCE("fstmfdx", d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 17447 | |
c19d1205 | 17448 | /* Monadic operations. */ |
21d799b5 NC |
17449 | cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
17450 | cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
17451 | cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
17452 | |
17453 | /* Dyadic operations. */ | |
21d799b5 NC |
17454 | cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
17455 | cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17456 | cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17457 | cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17458 | cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17459 | cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17460 | cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17461 | cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17462 | cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 17463 | |
c19d1205 | 17464 | /* Comparisons. */ |
21d799b5 NC |
17465 | cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
17466 | cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z), | |
17467 | cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
17468 | cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 17469 | |
62f3b8c8 PB |
17470 | /* Double precision load/store are still present on single precision |
17471 | implementations. */ | |
17472 | cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
17473 | cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
17474 | cCE("fldmiad", c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
17475 | cCE("fldmfdd", c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
17476 | cCE("fldmdbd", d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
17477 | cCE("fldmead", d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
17478 | cCE("fstmiad", c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
17479 | cCE("fstmead", c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
17480 | cCE("fstmdbd", d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
17481 | cCE("fstmfdd", d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
17482 | ||
c921be7d NC |
17483 | #undef ARM_VARIANT |
17484 | #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ | |
17485 | ||
c19d1205 | 17486 | /* Moves and type conversions. */ |
21d799b5 NC |
17487 | cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
17488 | cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
17489 | cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
17490 | cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
17491 | cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
17492 | cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
17493 | cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
17494 | cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
17495 | cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
17496 | cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
17497 | cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
17498 | cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
17499 | cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 | 17500 | |
c19d1205 | 17501 | /* Monadic operations. */ |
21d799b5 NC |
17502 | cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
17503 | cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), | |
17504 | cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
c19d1205 ZW |
17505 | |
17506 | /* Dyadic operations. */ | |
21d799b5 NC |
17507 | cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
17508 | cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17509 | cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17510 | cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17511 | cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17512 | cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17513 | cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17514 | cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17515 | cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
b99bd4ef | 17516 | |
c19d1205 | 17517 | /* Comparisons. */ |
21d799b5 NC |
17518 | cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
17519 | cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd), | |
17520 | cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
17521 | cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd), | |
c19d1205 | 17522 | |
c921be7d NC |
17523 | #undef ARM_VARIANT |
17524 | #define ARM_VARIANT & fpu_vfp_ext_v2 | |
17525 | ||
21d799b5 NC |
17526 | cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
17527 | cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
17528 | cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), | |
17529 | cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), | |
5287ad62 | 17530 | |
037e8744 JB |
17531 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
17532 | Individual encoder functions perform additional architecture checks. */ | |
c921be7d NC |
17533 | #undef ARM_VARIANT |
17534 | #define ARM_VARIANT & fpu_vfp_ext_v1xd | |
17535 | #undef THUMB_VARIANT | |
17536 | #define THUMB_VARIANT & fpu_vfp_ext_v1xd | |
17537 | ||
037e8744 JB |
17538 | /* These mnemonics are unique to VFP. */ |
17539 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), | |
17540 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), | |
21d799b5 NC |
17541 | nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
17542 | nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
17543 | nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
17544 | nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
17545 | nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
037e8744 JB |
17546 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), |
17547 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), | |
17548 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), | |
17549 | ||
17550 | /* Mnemonics shared by Neon and VFP. */ | |
21d799b5 NC |
17551 | nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), |
17552 | nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
17553 | nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
037e8744 | 17554 | |
21d799b5 NC |
17555 | nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), |
17556 | nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), | |
037e8744 JB |
17557 | |
17558 | NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
17559 | NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
17560 | ||
17561 | NCE(vldm, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
17562 | NCE(vldmia, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
17563 | NCE(vldmdb, d100b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
17564 | NCE(vstm, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
17565 | NCE(vstmia, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
17566 | NCE(vstmdb, d000b00, 2, (RRw, VRSDLST), neon_ldm_stm), | |
4962c51a MS |
17567 | NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), |
17568 | NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), | |
037e8744 | 17569 | |
e3e535bc NC |
17570 | nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt), |
17571 | nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr), | |
21d799b5 NC |
17572 | nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb), |
17573 | nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt), | |
f31fef98 | 17574 | |
037e8744 JB |
17575 | |
17576 | /* NOTE: All VMOV encoding is special-cased! */ | |
17577 | NCE(vmov, 0, 1, (VMOV), neon_mov), | |
17578 | NCE(vmovq, 0, 1, (VMOV), neon_mov), | |
17579 | ||
c921be7d NC |
17580 | #undef THUMB_VARIANT |
17581 | #define THUMB_VARIANT & fpu_neon_ext_v1 | |
17582 | #undef ARM_VARIANT | |
17583 | #define ARM_VARIANT & fpu_neon_ext_v1 | |
17584 | ||
5287ad62 JB |
17585 | /* Data processing with three registers of the same length. */ |
17586 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ | |
17587 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), | |
17588 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), | |
17589 | NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
17590 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
17591 | NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
17592 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
17593 | NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
17594 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
17595 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ | |
17596 | NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
17597 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
17598 | NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
17599 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
627907b7 JB |
17600 | NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), |
17601 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
17602 | NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), | |
17603 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
5287ad62 JB |
17604 | /* If not immediate, fall back to neon_dyadic_i64_su. |
17605 | shl_imm should accept I8 I16 I32 I64, | |
17606 | qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ | |
21d799b5 NC |
17607 | nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), |
17608 | nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), | |
17609 | nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), | |
17610 | nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), | |
5287ad62 | 17611 | /* Logic ops, types optional & ignored. */ |
4316f0d2 DG |
17612 | nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), |
17613 | nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
17614 | nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
17615 | nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
17616 | nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
17617 | nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
17618 | nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
17619 | nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
17620 | nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), | |
17621 | nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic), | |
5287ad62 JB |
17622 | /* Bitfield ops, untyped. */ |
17623 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
17624 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
17625 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
17626 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
17627 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
17628 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
17629 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ | |
21d799b5 NC |
17630 | nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), |
17631 | nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
17632 | nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
17633 | nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
17634 | nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
17635 | nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
5287ad62 JB |
17636 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall |
17637 | back to neon_dyadic_if_su. */ | |
21d799b5 NC |
17638 | nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), |
17639 | nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
17640 | nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
17641 | nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
17642 | nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
17643 | nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
17644 | nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
17645 | nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
428e3f1f | 17646 | /* Comparison. Type I8 I16 I32 F32. */ |
21d799b5 NC |
17647 | nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), |
17648 | nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), | |
5287ad62 | 17649 | /* As above, D registers only. */ |
21d799b5 NC |
17650 | nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), |
17651 | nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
5287ad62 | 17652 | /* Int and float variants, signedness unimportant. */ |
21d799b5 NC |
17653 | nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
17654 | nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), | |
17655 | nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), | |
5287ad62 | 17656 | /* Add/sub take types I8 I16 I32 I64 F32. */ |
21d799b5 NC |
17657 | nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
17658 | nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), | |
5287ad62 JB |
17659 | /* vtst takes sizes 8, 16, 32. */ |
17660 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), | |
17661 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), | |
17662 | /* VMUL takes I8 I16 I32 F32 P8. */ | |
21d799b5 | 17663 | nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
5287ad62 | 17664 | /* VQD{R}MULH takes S16 S32. */ |
21d799b5 NC |
17665 | nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), |
17666 | nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
17667 | nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
17668 | nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
5287ad62 JB |
17669 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), |
17670 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
17671 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
17672 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
92559b5b PB |
17673 | NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
17674 | NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
17675 | NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
17676 | NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
5287ad62 JB |
17677 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
17678 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
17679 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
17680 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
17681 | ||
17682 | /* Two address, int/float. Types S8 S16 S32 F32. */ | |
5287ad62 | 17683 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
5287ad62 JB |
17684 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
17685 | ||
17686 | /* Data processing with two registers and a shift amount. */ | |
17687 | /* Right shifts, and variants with rounding. | |
17688 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ | |
17689 | NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
17690 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
17691 | NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
17692 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
17693 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
17694 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
17695 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
17696 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
17697 | /* Shift and insert. Sizes accepted 8 16 32 64. */ | |
17698 | NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), | |
17699 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), | |
17700 | NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), | |
17701 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), | |
17702 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ | |
17703 | NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), | |
17704 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), | |
17705 | /* Right shift immediate, saturating & narrowing, with rounding variants. | |
17706 | Types accepted S16 S32 S64 U16 U32 U64. */ | |
17707 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
17708 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
17709 | /* As above, unsigned. Types accepted S16 S32 S64. */ | |
17710 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
17711 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
17712 | /* Right shift narrowing. Types accepted I16 I32 I64. */ | |
17713 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
17714 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
17715 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ | |
21d799b5 | 17716 | nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll), |
5287ad62 | 17717 | /* CVT with optional immediate for fixed-point variant. */ |
21d799b5 | 17718 | nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
b7fc2769 | 17719 | |
4316f0d2 DG |
17720 | nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn), |
17721 | nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn), | |
5287ad62 JB |
17722 | |
17723 | /* Data processing, three registers of different lengths. */ | |
17724 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ | |
17725 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), | |
17726 | NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), | |
17727 | NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), | |
17728 | NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), | |
17729 | /* If not scalar, fall back to neon_dyadic_long. | |
17730 | Vector types as above, scalar types S16 S32 U16 U32. */ | |
21d799b5 NC |
17731 | nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), |
17732 | nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
5287ad62 JB |
17733 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ |
17734 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
17735 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
17736 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ | |
17737 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
17738 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
17739 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
17740 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
17741 | /* Saturating doubling multiplies. Types S16 S32. */ | |
21d799b5 NC |
17742 | nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
17743 | nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
17744 | nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
5287ad62 JB |
17745 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types |
17746 | S16 S32 U16 U32. */ | |
21d799b5 | 17747 | nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), |
5287ad62 JB |
17748 | |
17749 | /* Extract. Size 8. */ | |
3b8d421e PB |
17750 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), |
17751 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), | |
5287ad62 JB |
17752 | |
17753 | /* Two registers, miscellaneous. */ | |
17754 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ | |
17755 | NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), | |
17756 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), | |
17757 | NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), | |
17758 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), | |
17759 | NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), | |
17760 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), | |
17761 | /* Vector replicate. Sizes 8 16 32. */ | |
21d799b5 NC |
17762 | nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup), |
17763 | nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup), | |
5287ad62 JB |
17764 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ |
17765 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), | |
17766 | /* VMOVN. Types I16 I32 I64. */ | |
21d799b5 | 17767 | nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn), |
5287ad62 | 17768 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ |
21d799b5 | 17769 | nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn), |
5287ad62 | 17770 | /* VQMOVUN. Types S16 S32 S64. */ |
21d799b5 | 17771 | nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun), |
5287ad62 JB |
17772 | /* VZIP / VUZP. Sizes 8 16 32. */ |
17773 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
17774 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), | |
17775 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
17776 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), | |
17777 | /* VQABS / VQNEG. Types S8 S16 S32. */ | |
17778 | NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
17779 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
17780 | NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
17781 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
17782 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ | |
17783 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), | |
17784 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), | |
17785 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), | |
17786 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), | |
17787 | /* Reciprocal estimates. Types U32 F32. */ | |
17788 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), | |
17789 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), | |
17790 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), | |
17791 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), | |
17792 | /* VCLS. Types S8 S16 S32. */ | |
17793 | NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), | |
17794 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), | |
17795 | /* VCLZ. Types I8 I16 I32. */ | |
17796 | NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), | |
17797 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), | |
17798 | /* VCNT. Size 8. */ | |
17799 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), | |
17800 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), | |
17801 | /* Two address, untyped. */ | |
17802 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), | |
17803 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), | |
17804 | /* VTRN. Sizes 8 16 32. */ | |
21d799b5 NC |
17805 | nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn), |
17806 | nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn), | |
5287ad62 JB |
17807 | |
17808 | /* Table lookup. Size 8. */ | |
17809 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
17810 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
17811 | ||
c921be7d NC |
17812 | #undef THUMB_VARIANT |
17813 | #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext | |
17814 | #undef ARM_VARIANT | |
17815 | #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext | |
17816 | ||
5287ad62 | 17817 | /* Neon element/structure load/store. */ |
21d799b5 NC |
17818 | nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), |
17819 | nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17820 | nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17821 | nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17822 | nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17823 | nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17824 | nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17825 | nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
5287ad62 | 17826 | |
c921be7d | 17827 | #undef THUMB_VARIANT |
62f3b8c8 PB |
17828 | #define THUMB_VARIANT &fpu_vfp_ext_v3xd |
17829 | #undef ARM_VARIANT | |
17830 | #define ARM_VARIANT &fpu_vfp_ext_v3xd | |
17831 | cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const), | |
17832 | cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
17833 | cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
17834 | cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
17835 | cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
17836 | cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
17837 | cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
17838 | cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
17839 | cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
17840 | ||
17841 | #undef THUMB_VARIANT | |
c921be7d NC |
17842 | #define THUMB_VARIANT & fpu_vfp_ext_v3 |
17843 | #undef ARM_VARIANT | |
17844 | #define ARM_VARIANT & fpu_vfp_ext_v3 | |
17845 | ||
21d799b5 | 17846 | cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const), |
21d799b5 | 17847 | cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 17848 | cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 17849 | cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 17850 | cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 17851 | cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 17852 | cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 17853 | cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 17854 | cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
c19d1205 | 17855 | |
62f3b8c8 PB |
17856 | #undef ARM_VARIANT |
17857 | #define ARM_VARIANT &fpu_vfp_ext_fma | |
17858 | #undef THUMB_VARIANT | |
17859 | #define THUMB_VARIANT &fpu_vfp_ext_fma | |
17860 | /* Mnemonics shared by Neon and VFP. These are included in the | |
17861 | VFP FMA variant; NEON and VFP FMA always includes the NEON | |
17862 | FMA instructions. */ | |
17863 | nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
17864 | nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
17865 | /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas; | |
17866 | the v form should always be used. */ | |
17867 | cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17868 | cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17869 | cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17870 | cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17871 | nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
17872 | nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
17873 | ||
5287ad62 | 17874 | #undef THUMB_VARIANT |
c921be7d NC |
17875 | #undef ARM_VARIANT |
17876 | #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ | |
17877 | ||
21d799b5 NC |
17878 | cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
17879 | cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
17880 | cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
17881 | cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
17882 | cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
17883 | cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
17884 | cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
17885 | cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 | 17886 | |
c921be7d NC |
17887 | #undef ARM_VARIANT |
17888 | #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ | |
17889 | ||
21d799b5 NC |
17890 | cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc), |
17891 | cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc), | |
17892 | cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc), | |
17893 | cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd), | |
17894 | cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd), | |
17895 | cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd), | |
17896 | cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc), | |
17897 | cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc), | |
17898 | cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc), | |
17899 | cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17900 | cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17901 | cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17902 | cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17903 | cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17904 | cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17905 | cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
17906 | cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
17907 | cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
17908 | cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd), | |
17909 | cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
17910 | cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17911 | cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17912 | cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17913 | cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17914 | cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17915 | cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17916 | cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn), | |
17917 | cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn), | |
17918 | cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn), | |
17919 | cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn), | |
17920 | cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
17921 | cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc), | |
17922 | cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc), | |
17923 | cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc), | |
17924 | cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn), | |
17925 | cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn), | |
17926 | cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn), | |
17927 | cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17928 | cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17929 | cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17930 | cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17931 | cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17932 | cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17933 | cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17934 | cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17935 | cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17936 | cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
17937 | cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17938 | cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17939 | cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17940 | cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17941 | cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17942 | cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17943 | cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17944 | cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17945 | cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17946 | cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17947 | cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17948 | cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17949 | cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17950 | cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17951 | cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17952 | cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17953 | cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17954 | cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17955 | cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17956 | cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
17957 | cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
17958 | cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
17959 | cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
17960 | cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17961 | cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17962 | cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17963 | cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17964 | cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17965 | cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17966 | cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17967 | cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17968 | cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17969 | cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17970 | cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17971 | cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17972 | cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17973 | cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17974 | cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17975 | cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17976 | cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17977 | cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17978 | cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
17979 | cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17980 | cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17981 | cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17982 | cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17983 | cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17984 | cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17985 | cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17986 | cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17987 | cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17988 | cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17989 | cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17990 | cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
17991 | cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
17992 | cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
17993 | cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
17994 | cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
17995 | cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
17996 | cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17997 | cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17998 | cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17999 | cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18000 | cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
18001 | cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18002 | cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18003 | cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18004 | cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18005 | cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18006 | cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18007 | cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18008 | cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18009 | cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18010 | cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18011 | cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18012 | cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18013 | cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18014 | cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18015 | cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18016 | cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18017 | cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18018 | cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18019 | cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18020 | cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18021 | cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
18022 | cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
18023 | cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18024 | cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18025 | cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18026 | cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18027 | cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18028 | cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18029 | cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18030 | cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18031 | cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18032 | cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn), | |
18033 | cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn), | |
18034 | cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn), | |
18035 | cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn), | |
18036 | cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn), | |
18037 | cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn), | |
18038 | cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18039 | cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18040 | cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18041 | cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn), | |
18042 | cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn), | |
18043 | cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn), | |
18044 | cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn), | |
18045 | cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn), | |
18046 | cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn), | |
18047 | cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18048 | cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18049 | cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18050 | cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18051 | cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 | 18052 | |
c921be7d NC |
18053 | #undef ARM_VARIANT |
18054 | #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ | |
18055 | ||
21d799b5 NC |
18056 | cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc), |
18057 | cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc), | |
18058 | cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc), | |
18059 | cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn), | |
18060 | cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn), | |
18061 | cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn), | |
18062 | cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18063 | cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18064 | cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18065 | cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18066 | cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18067 | cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18068 | cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18069 | cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18070 | cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18071 | cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18072 | cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18073 | cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18074 | cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18075 | cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18076 | cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), | |
18077 | cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18078 | cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18079 | cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18080 | cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18081 | cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18082 | cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18083 | cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18084 | cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18085 | cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18086 | cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18087 | cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18088 | cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18089 | cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18090 | cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18091 | cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18092 | cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18093 | cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18094 | cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18095 | cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18096 | cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18097 | cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18098 | cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18099 | cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18100 | cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18101 | cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18102 | cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18103 | cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18104 | cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18105 | cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18106 | cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18107 | cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18108 | cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18109 | cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18110 | cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18111 | cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18112 | cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
2d447fca | 18113 | |
c921be7d NC |
18114 | #undef ARM_VARIANT |
18115 | #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ | |
18116 | ||
21d799b5 NC |
18117 | cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
18118 | cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
18119 | cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
18120 | cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
18121 | cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), | |
18122 | cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
18123 | cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
18124 | cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
18125 | cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd), | |
18126 | cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn), | |
18127 | cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd), | |
18128 | cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn), | |
18129 | cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd), | |
18130 | cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn), | |
18131 | cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd), | |
18132 | cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn), | |
18133 | cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd), | |
18134 | cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn), | |
18135 | cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn), | |
18136 | cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn), | |
18137 | cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn), | |
18138 | cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn), | |
18139 | cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn), | |
18140 | cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn), | |
18141 | cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn), | |
18142 | cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn), | |
18143 | cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn), | |
18144 | cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn), | |
18145 | cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc), | |
18146 | cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd), | |
18147 | cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn), | |
18148 | cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn), | |
18149 | cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn), | |
18150 | cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn), | |
18151 | cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn), | |
18152 | cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn), | |
18153 | cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn), | |
18154 | cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn), | |
18155 | cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn), | |
18156 | cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn), | |
18157 | cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn), | |
18158 | cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn), | |
18159 | cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple), | |
18160 | cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
18161 | cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift), | |
18162 | cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
18163 | cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
18164 | cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
18165 | cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
18166 | cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
18167 | cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn), | |
18168 | cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn), | |
18169 | cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn), | |
18170 | cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn), | |
18171 | cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18172 | cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18173 | cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18174 | cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18175 | cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18176 | cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18177 | cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn), | |
18178 | cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn), | |
18179 | cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn), | |
18180 | cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn), | |
18181 | cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18182 | cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18183 | cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18184 | cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18185 | cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18186 | cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18187 | cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18188 | cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18189 | cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
18190 | cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
18191 | cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
18192 | cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
18193 | }; |
18194 | #undef ARM_VARIANT | |
18195 | #undef THUMB_VARIANT | |
18196 | #undef TCE | |
18197 | #undef TCM | |
18198 | #undef TUE | |
18199 | #undef TUF | |
18200 | #undef TCC | |
8f06b2d8 | 18201 | #undef cCE |
e3cb604e PB |
18202 | #undef cCL |
18203 | #undef C3E | |
c19d1205 ZW |
18204 | #undef CE |
18205 | #undef CM | |
18206 | #undef UE | |
18207 | #undef UF | |
18208 | #undef UT | |
5287ad62 JB |
18209 | #undef NUF |
18210 | #undef nUF | |
18211 | #undef NCE | |
18212 | #undef nCE | |
c19d1205 ZW |
18213 | #undef OPS0 |
18214 | #undef OPS1 | |
18215 | #undef OPS2 | |
18216 | #undef OPS3 | |
18217 | #undef OPS4 | |
18218 | #undef OPS5 | |
18219 | #undef OPS6 | |
18220 | #undef do_0 | |
18221 | \f | |
18222 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 18223 | |
c19d1205 ZW |
18224 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
18225 | for use in the a.out file, and stores them in the array pointed to by buf. | |
18226 | This knows about the endian-ness of the target machine and does | |
18227 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
18228 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
18229 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 18230 | |
c19d1205 ZW |
18231 | void |
18232 | md_number_to_chars (char * buf, valueT val, int n) | |
18233 | { | |
18234 | if (target_big_endian) | |
18235 | number_to_chars_bigendian (buf, val, n); | |
18236 | else | |
18237 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
18238 | } |
18239 | ||
c19d1205 ZW |
18240 | static valueT |
18241 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 18242 | { |
c19d1205 ZW |
18243 | valueT result = 0; |
18244 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 18245 | |
c19d1205 | 18246 | if (target_big_endian) |
b99bd4ef | 18247 | { |
c19d1205 ZW |
18248 | while (n--) |
18249 | { | |
18250 | result <<= 8; | |
18251 | result |= (*where++ & 255); | |
18252 | } | |
b99bd4ef | 18253 | } |
c19d1205 | 18254 | else |
b99bd4ef | 18255 | { |
c19d1205 ZW |
18256 | while (n--) |
18257 | { | |
18258 | result <<= 8; | |
18259 | result |= (where[n] & 255); | |
18260 | } | |
bfae80f2 | 18261 | } |
b99bd4ef | 18262 | |
c19d1205 | 18263 | return result; |
bfae80f2 | 18264 | } |
b99bd4ef | 18265 | |
c19d1205 | 18266 | /* MD interface: Sections. */ |
b99bd4ef | 18267 | |
0110f2b8 PB |
18268 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
18269 | 2 bytes. */ | |
18270 | ||
c19d1205 | 18271 | int |
0110f2b8 | 18272 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
18273 | segT segtype ATTRIBUTE_UNUSED) |
18274 | { | |
0110f2b8 PB |
18275 | fragp->fr_var = 2; |
18276 | return 2; | |
18277 | } | |
18278 | ||
18279 | /* Convert a machine dependent frag. */ | |
18280 | ||
18281 | void | |
18282 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
18283 | { | |
18284 | unsigned long insn; | |
18285 | unsigned long old_op; | |
18286 | char *buf; | |
18287 | expressionS exp; | |
18288 | fixS *fixp; | |
18289 | int reloc_type; | |
18290 | int pc_rel; | |
18291 | int opcode; | |
18292 | ||
18293 | buf = fragp->fr_literal + fragp->fr_fix; | |
18294 | ||
18295 | old_op = bfd_get_16(abfd, buf); | |
5f4273c7 NC |
18296 | if (fragp->fr_symbol) |
18297 | { | |
0110f2b8 PB |
18298 | exp.X_op = O_symbol; |
18299 | exp.X_add_symbol = fragp->fr_symbol; | |
5f4273c7 NC |
18300 | } |
18301 | else | |
18302 | { | |
0110f2b8 | 18303 | exp.X_op = O_constant; |
5f4273c7 | 18304 | } |
0110f2b8 PB |
18305 | exp.X_add_number = fragp->fr_offset; |
18306 | opcode = fragp->fr_subtype; | |
18307 | switch (opcode) | |
18308 | { | |
18309 | case T_MNEM_ldr_pc: | |
18310 | case T_MNEM_ldr_pc2: | |
18311 | case T_MNEM_ldr_sp: | |
18312 | case T_MNEM_str_sp: | |
18313 | case T_MNEM_ldr: | |
18314 | case T_MNEM_ldrb: | |
18315 | case T_MNEM_ldrh: | |
18316 | case T_MNEM_str: | |
18317 | case T_MNEM_strb: | |
18318 | case T_MNEM_strh: | |
18319 | if (fragp->fr_var == 4) | |
18320 | { | |
5f4273c7 | 18321 | insn = THUMB_OP32 (opcode); |
0110f2b8 PB |
18322 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) |
18323 | { | |
18324 | insn |= (old_op & 0x700) << 4; | |
18325 | } | |
18326 | else | |
18327 | { | |
18328 | insn |= (old_op & 7) << 12; | |
18329 | insn |= (old_op & 0x38) << 13; | |
18330 | } | |
18331 | insn |= 0x00000c00; | |
18332 | put_thumb32_insn (buf, insn); | |
18333 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
18334 | } | |
18335 | else | |
18336 | { | |
18337 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
18338 | } | |
18339 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
18340 | break; | |
18341 | case T_MNEM_adr: | |
18342 | if (fragp->fr_var == 4) | |
18343 | { | |
18344 | insn = THUMB_OP32 (opcode); | |
18345 | insn |= (old_op & 0xf0) << 4; | |
18346 | put_thumb32_insn (buf, insn); | |
18347 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
18348 | } | |
18349 | else | |
18350 | { | |
18351 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
18352 | exp.X_add_number -= 4; | |
18353 | } | |
18354 | pc_rel = 1; | |
18355 | break; | |
18356 | case T_MNEM_mov: | |
18357 | case T_MNEM_movs: | |
18358 | case T_MNEM_cmp: | |
18359 | case T_MNEM_cmn: | |
18360 | if (fragp->fr_var == 4) | |
18361 | { | |
18362 | int r0off = (opcode == T_MNEM_mov | |
18363 | || opcode == T_MNEM_movs) ? 0 : 8; | |
18364 | insn = THUMB_OP32 (opcode); | |
18365 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
18366 | insn |= (old_op & 0x700) << r0off; | |
18367 | put_thumb32_insn (buf, insn); | |
18368 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
18369 | } | |
18370 | else | |
18371 | { | |
18372 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
18373 | } | |
18374 | pc_rel = 0; | |
18375 | break; | |
18376 | case T_MNEM_b: | |
18377 | if (fragp->fr_var == 4) | |
18378 | { | |
18379 | insn = THUMB_OP32(opcode); | |
18380 | put_thumb32_insn (buf, insn); | |
18381 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
18382 | } | |
18383 | else | |
18384 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
18385 | pc_rel = 1; | |
18386 | break; | |
18387 | case T_MNEM_bcond: | |
18388 | if (fragp->fr_var == 4) | |
18389 | { | |
18390 | insn = THUMB_OP32(opcode); | |
18391 | insn |= (old_op & 0xf00) << 14; | |
18392 | put_thumb32_insn (buf, insn); | |
18393 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
18394 | } | |
18395 | else | |
18396 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
18397 | pc_rel = 1; | |
18398 | break; | |
18399 | case T_MNEM_add_sp: | |
18400 | case T_MNEM_add_pc: | |
18401 | case T_MNEM_inc_sp: | |
18402 | case T_MNEM_dec_sp: | |
18403 | if (fragp->fr_var == 4) | |
18404 | { | |
18405 | /* ??? Choose between add and addw. */ | |
18406 | insn = THUMB_OP32 (opcode); | |
18407 | insn |= (old_op & 0xf0) << 4; | |
18408 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
18409 | if (opcode == T_MNEM_add_pc) |
18410 | reloc_type = BFD_RELOC_ARM_T32_IMM12; | |
18411 | else | |
18412 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
0110f2b8 PB |
18413 | } |
18414 | else | |
18415 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
18416 | pc_rel = 0; | |
18417 | break; | |
18418 | ||
18419 | case T_MNEM_addi: | |
18420 | case T_MNEM_addis: | |
18421 | case T_MNEM_subi: | |
18422 | case T_MNEM_subis: | |
18423 | if (fragp->fr_var == 4) | |
18424 | { | |
18425 | insn = THUMB_OP32 (opcode); | |
18426 | insn |= (old_op & 0xf0) << 4; | |
18427 | insn |= (old_op & 0xf) << 16; | |
18428 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
18429 | if (insn & (1 << 20)) |
18430 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
18431 | else | |
18432 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
0110f2b8 PB |
18433 | } |
18434 | else | |
18435 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
18436 | pc_rel = 0; | |
18437 | break; | |
18438 | default: | |
5f4273c7 | 18439 | abort (); |
0110f2b8 PB |
18440 | } |
18441 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
21d799b5 | 18442 | (enum bfd_reloc_code_real) reloc_type); |
0110f2b8 PB |
18443 | fixp->fx_file = fragp->fr_file; |
18444 | fixp->fx_line = fragp->fr_line; | |
18445 | fragp->fr_fix += fragp->fr_var; | |
18446 | } | |
18447 | ||
18448 | /* Return the size of a relaxable immediate operand instruction. | |
18449 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
18450 | static int | |
18451 | relax_immediate (fragS *fragp, int size, int shift) | |
18452 | { | |
18453 | offsetT offset; | |
18454 | offsetT mask; | |
18455 | offsetT low; | |
18456 | ||
18457 | /* ??? Should be able to do better than this. */ | |
18458 | if (fragp->fr_symbol) | |
18459 | return 4; | |
18460 | ||
18461 | low = (1 << shift) - 1; | |
18462 | mask = (1 << (shift + size)) - (1 << shift); | |
18463 | offset = fragp->fr_offset; | |
18464 | /* Force misaligned offsets to 32-bit variant. */ | |
18465 | if (offset & low) | |
5e77afaa | 18466 | return 4; |
0110f2b8 PB |
18467 | if (offset & ~mask) |
18468 | return 4; | |
18469 | return 2; | |
18470 | } | |
18471 | ||
5e77afaa PB |
18472 | /* Get the address of a symbol during relaxation. */ |
18473 | static addressT | |
5f4273c7 | 18474 | relaxed_symbol_addr (fragS *fragp, long stretch) |
5e77afaa PB |
18475 | { |
18476 | fragS *sym_frag; | |
18477 | addressT addr; | |
18478 | symbolS *sym; | |
18479 | ||
18480 | sym = fragp->fr_symbol; | |
18481 | sym_frag = symbol_get_frag (sym); | |
18482 | know (S_GET_SEGMENT (sym) != absolute_section | |
18483 | || sym_frag == &zero_address_frag); | |
18484 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
18485 | ||
18486 | /* If frag has yet to be reached on this pass, assume it will | |
18487 | move by STRETCH just as we did. If this is not so, it will | |
18488 | be because some frag between grows, and that will force | |
18489 | another pass. */ | |
18490 | ||
18491 | if (stretch != 0 | |
18492 | && sym_frag->relax_marker != fragp->relax_marker) | |
4396b686 PB |
18493 | { |
18494 | fragS *f; | |
18495 | ||
18496 | /* Adjust stretch for any alignment frag. Note that if have | |
18497 | been expanding the earlier code, the symbol may be | |
18498 | defined in what appears to be an earlier frag. FIXME: | |
18499 | This doesn't handle the fr_subtype field, which specifies | |
18500 | a maximum number of bytes to skip when doing an | |
18501 | alignment. */ | |
18502 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
18503 | { | |
18504 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
18505 | { | |
18506 | if (stretch < 0) | |
18507 | stretch = - ((- stretch) | |
18508 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
18509 | else | |
18510 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
18511 | if (stretch == 0) | |
18512 | break; | |
18513 | } | |
18514 | } | |
18515 | if (f != NULL) | |
18516 | addr += stretch; | |
18517 | } | |
5e77afaa PB |
18518 | |
18519 | return addr; | |
18520 | } | |
18521 | ||
0110f2b8 PB |
18522 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative |
18523 | load. */ | |
18524 | static int | |
5e77afaa | 18525 | relax_adr (fragS *fragp, asection *sec, long stretch) |
0110f2b8 PB |
18526 | { |
18527 | addressT addr; | |
18528 | offsetT val; | |
18529 | ||
18530 | /* Assume worst case for symbols not known to be in the same section. */ | |
974da60d NC |
18531 | if (fragp->fr_symbol == NULL |
18532 | || !S_IS_DEFINED (fragp->fr_symbol) | |
77db8e2e NC |
18533 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
18534 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
18535 | return 4; |
18536 | ||
5f4273c7 | 18537 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
18538 | addr = fragp->fr_address + fragp->fr_fix; |
18539 | addr = (addr + 4) & ~3; | |
5e77afaa | 18540 | /* Force misaligned targets to 32-bit variant. */ |
0110f2b8 | 18541 | if (val & 3) |
5e77afaa | 18542 | return 4; |
0110f2b8 PB |
18543 | val -= addr; |
18544 | if (val < 0 || val > 1020) | |
18545 | return 4; | |
18546 | return 2; | |
18547 | } | |
18548 | ||
18549 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
18550 | static int | |
18551 | relax_addsub (fragS *fragp, asection *sec) | |
18552 | { | |
18553 | char *buf; | |
18554 | int op; | |
18555 | ||
18556 | buf = fragp->fr_literal + fragp->fr_fix; | |
18557 | op = bfd_get_16(sec->owner, buf); | |
18558 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
18559 | return relax_immediate (fragp, 8, 0); | |
18560 | else | |
18561 | return relax_immediate (fragp, 3, 0); | |
18562 | } | |
18563 | ||
18564 | ||
18565 | /* Return the size of a relaxable branch instruction. BITS is the | |
18566 | size of the offset field in the narrow instruction. */ | |
18567 | ||
18568 | static int | |
5e77afaa | 18569 | relax_branch (fragS *fragp, asection *sec, int bits, long stretch) |
0110f2b8 PB |
18570 | { |
18571 | addressT addr; | |
18572 | offsetT val; | |
18573 | offsetT limit; | |
18574 | ||
18575 | /* Assume worst case for symbols not known to be in the same section. */ | |
5f4273c7 | 18576 | if (!S_IS_DEFINED (fragp->fr_symbol) |
77db8e2e NC |
18577 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
18578 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
18579 | return 4; |
18580 | ||
267bf995 RR |
18581 | #ifdef OBJ_ELF |
18582 | if (S_IS_DEFINED (fragp->fr_symbol) | |
18583 | && ARM_IS_FUNC (fragp->fr_symbol)) | |
18584 | return 4; | |
18585 | #endif | |
18586 | ||
5f4273c7 | 18587 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
18588 | addr = fragp->fr_address + fragp->fr_fix + 4; |
18589 | val -= addr; | |
18590 | ||
18591 | /* Offset is a signed value *2 */ | |
18592 | limit = 1 << bits; | |
18593 | if (val >= limit || val < -limit) | |
18594 | return 4; | |
18595 | return 2; | |
18596 | } | |
18597 | ||
18598 | ||
18599 | /* Relax a machine dependent frag. This returns the amount by which | |
18600 | the current size of the frag should change. */ | |
18601 | ||
18602 | int | |
5e77afaa | 18603 | arm_relax_frag (asection *sec, fragS *fragp, long stretch) |
0110f2b8 PB |
18604 | { |
18605 | int oldsize; | |
18606 | int newsize; | |
18607 | ||
18608 | oldsize = fragp->fr_var; | |
18609 | switch (fragp->fr_subtype) | |
18610 | { | |
18611 | case T_MNEM_ldr_pc2: | |
5f4273c7 | 18612 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
18613 | break; |
18614 | case T_MNEM_ldr_pc: | |
18615 | case T_MNEM_ldr_sp: | |
18616 | case T_MNEM_str_sp: | |
5f4273c7 | 18617 | newsize = relax_immediate (fragp, 8, 2); |
0110f2b8 PB |
18618 | break; |
18619 | case T_MNEM_ldr: | |
18620 | case T_MNEM_str: | |
5f4273c7 | 18621 | newsize = relax_immediate (fragp, 5, 2); |
0110f2b8 PB |
18622 | break; |
18623 | case T_MNEM_ldrh: | |
18624 | case T_MNEM_strh: | |
5f4273c7 | 18625 | newsize = relax_immediate (fragp, 5, 1); |
0110f2b8 PB |
18626 | break; |
18627 | case T_MNEM_ldrb: | |
18628 | case T_MNEM_strb: | |
5f4273c7 | 18629 | newsize = relax_immediate (fragp, 5, 0); |
0110f2b8 PB |
18630 | break; |
18631 | case T_MNEM_adr: | |
5f4273c7 | 18632 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
18633 | break; |
18634 | case T_MNEM_mov: | |
18635 | case T_MNEM_movs: | |
18636 | case T_MNEM_cmp: | |
18637 | case T_MNEM_cmn: | |
5f4273c7 | 18638 | newsize = relax_immediate (fragp, 8, 0); |
0110f2b8 PB |
18639 | break; |
18640 | case T_MNEM_b: | |
5f4273c7 | 18641 | newsize = relax_branch (fragp, sec, 11, stretch); |
0110f2b8 PB |
18642 | break; |
18643 | case T_MNEM_bcond: | |
5f4273c7 | 18644 | newsize = relax_branch (fragp, sec, 8, stretch); |
0110f2b8 PB |
18645 | break; |
18646 | case T_MNEM_add_sp: | |
18647 | case T_MNEM_add_pc: | |
18648 | newsize = relax_immediate (fragp, 8, 2); | |
18649 | break; | |
18650 | case T_MNEM_inc_sp: | |
18651 | case T_MNEM_dec_sp: | |
18652 | newsize = relax_immediate (fragp, 7, 2); | |
18653 | break; | |
18654 | case T_MNEM_addi: | |
18655 | case T_MNEM_addis: | |
18656 | case T_MNEM_subi: | |
18657 | case T_MNEM_subis: | |
18658 | newsize = relax_addsub (fragp, sec); | |
18659 | break; | |
18660 | default: | |
5f4273c7 | 18661 | abort (); |
0110f2b8 | 18662 | } |
5e77afaa PB |
18663 | |
18664 | fragp->fr_var = newsize; | |
18665 | /* Freeze wide instructions that are at or before the same location as | |
18666 | in the previous pass. This avoids infinite loops. | |
5f4273c7 NC |
18667 | Don't freeze them unconditionally because targets may be artificially |
18668 | misaligned by the expansion of preceding frags. */ | |
5e77afaa | 18669 | if (stretch <= 0 && newsize > 2) |
0110f2b8 | 18670 | { |
0110f2b8 | 18671 | md_convert_frag (sec->owner, sec, fragp); |
5f4273c7 | 18672 | frag_wane (fragp); |
0110f2b8 | 18673 | } |
5e77afaa | 18674 | |
0110f2b8 | 18675 | return newsize - oldsize; |
c19d1205 | 18676 | } |
b99bd4ef | 18677 | |
c19d1205 | 18678 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 18679 | |
c19d1205 ZW |
18680 | valueT |
18681 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
18682 | valueT size) | |
18683 | { | |
f0927246 NC |
18684 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
18685 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
18686 | { | |
18687 | /* For a.out, force the section size to be aligned. If we don't do | |
18688 | this, BFD will align it for us, but it will not write out the | |
18689 | final bytes of the section. This may be a bug in BFD, but it is | |
18690 | easier to fix it here since that is how the other a.out targets | |
18691 | work. */ | |
18692 | int align; | |
18693 | ||
18694 | align = bfd_get_section_alignment (stdoutput, segment); | |
18695 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
18696 | } | |
c19d1205 | 18697 | #endif |
f0927246 NC |
18698 | |
18699 | return size; | |
bfae80f2 | 18700 | } |
b99bd4ef | 18701 | |
c19d1205 ZW |
18702 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
18703 | of an rs_align_code fragment. */ | |
18704 | ||
18705 | void | |
18706 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 18707 | { |
e7495e45 NS |
18708 | static char const arm_noop[2][2][4] = |
18709 | { | |
18710 | { /* ARMv1 */ | |
18711 | {0x00, 0x00, 0xa0, 0xe1}, /* LE */ | |
18712 | {0xe1, 0xa0, 0x00, 0x00}, /* BE */ | |
18713 | }, | |
18714 | { /* ARMv6k */ | |
18715 | {0x00, 0xf0, 0x20, 0xe3}, /* LE */ | |
18716 | {0xe3, 0x20, 0xf0, 0x00}, /* BE */ | |
18717 | }, | |
18718 | }; | |
18719 | static char const thumb_noop[2][2][2] = | |
18720 | { | |
18721 | { /* Thumb-1 */ | |
18722 | {0xc0, 0x46}, /* LE */ | |
18723 | {0x46, 0xc0}, /* BE */ | |
18724 | }, | |
18725 | { /* Thumb-2 */ | |
18726 | {0x00, 0xbf}, /* LE */ | |
18727 | {0xbf, 0x00} /* BE */ | |
18728 | } | |
18729 | }; | |
18730 | static char const wide_thumb_noop[2][4] = | |
18731 | { /* Wide Thumb-2 */ | |
18732 | {0xaf, 0xf3, 0x00, 0x80}, /* LE */ | |
18733 | {0xf3, 0xaf, 0x80, 0x00}, /* BE */ | |
18734 | }; | |
c921be7d | 18735 | |
e7495e45 | 18736 | unsigned bytes, fix, noop_size; |
c19d1205 ZW |
18737 | char * p; |
18738 | const char * noop; | |
e7495e45 | 18739 | const char *narrow_noop = NULL; |
cd000bff DJ |
18740 | #ifdef OBJ_ELF |
18741 | enum mstate state; | |
18742 | #endif | |
bfae80f2 | 18743 | |
c19d1205 | 18744 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
18745 | return; |
18746 | ||
c19d1205 ZW |
18747 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
18748 | p = fragP->fr_literal + fragP->fr_fix; | |
18749 | fix = 0; | |
bfae80f2 | 18750 | |
c19d1205 ZW |
18751 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
18752 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 18753 | |
cd000bff | 18754 | gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); |
8dc2430f | 18755 | |
cd000bff | 18756 | if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) |
a737bd4d | 18757 | { |
e7495e45 NS |
18758 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
18759 | { | |
18760 | narrow_noop = thumb_noop[1][target_big_endian]; | |
18761 | noop = wide_thumb_noop[target_big_endian]; | |
18762 | } | |
c19d1205 | 18763 | else |
e7495e45 NS |
18764 | noop = thumb_noop[0][target_big_endian]; |
18765 | noop_size = 2; | |
cd000bff DJ |
18766 | #ifdef OBJ_ELF |
18767 | state = MAP_THUMB; | |
18768 | #endif | |
7ed4c4c5 NC |
18769 | } |
18770 | else | |
18771 | { | |
e7495e45 NS |
18772 | noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0] |
18773 | [target_big_endian]; | |
18774 | noop_size = 4; | |
cd000bff DJ |
18775 | #ifdef OBJ_ELF |
18776 | state = MAP_ARM; | |
18777 | #endif | |
7ed4c4c5 | 18778 | } |
c921be7d | 18779 | |
e7495e45 | 18780 | fragP->fr_var = noop_size; |
c921be7d | 18781 | |
c19d1205 | 18782 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 18783 | { |
c19d1205 | 18784 | fix = bytes & (noop_size - 1); |
cd000bff DJ |
18785 | #ifdef OBJ_ELF |
18786 | insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); | |
18787 | #endif | |
c19d1205 ZW |
18788 | memset (p, 0, fix); |
18789 | p += fix; | |
18790 | bytes -= fix; | |
a737bd4d | 18791 | } |
a737bd4d | 18792 | |
e7495e45 NS |
18793 | if (narrow_noop) |
18794 | { | |
18795 | if (bytes & noop_size) | |
18796 | { | |
18797 | /* Insert a narrow noop. */ | |
18798 | memcpy (p, narrow_noop, noop_size); | |
18799 | p += noop_size; | |
18800 | bytes -= noop_size; | |
18801 | fix += noop_size; | |
18802 | } | |
18803 | ||
18804 | /* Use wide noops for the remainder */ | |
18805 | noop_size = 4; | |
18806 | } | |
18807 | ||
c19d1205 | 18808 | while (bytes >= noop_size) |
a737bd4d | 18809 | { |
c19d1205 ZW |
18810 | memcpy (p, noop, noop_size); |
18811 | p += noop_size; | |
18812 | bytes -= noop_size; | |
18813 | fix += noop_size; | |
a737bd4d NC |
18814 | } |
18815 | ||
c19d1205 | 18816 | fragP->fr_fix += fix; |
a737bd4d NC |
18817 | } |
18818 | ||
c19d1205 ZW |
18819 | /* Called from md_do_align. Used to create an alignment |
18820 | frag in a code section. */ | |
18821 | ||
18822 | void | |
18823 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 18824 | { |
c19d1205 | 18825 | char * p; |
7ed4c4c5 | 18826 | |
c19d1205 | 18827 | /* We assume that there will never be a requirement |
6ec8e702 | 18828 | to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ |
c19d1205 | 18829 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) |
6ec8e702 NC |
18830 | { |
18831 | char err_msg[128]; | |
18832 | ||
18833 | sprintf (err_msg, | |
18834 | _("alignments greater than %d bytes not supported in .text sections."), | |
18835 | MAX_MEM_FOR_RS_ALIGN_CODE + 1); | |
20203fb9 | 18836 | as_fatal ("%s", err_msg); |
6ec8e702 | 18837 | } |
bfae80f2 | 18838 | |
c19d1205 ZW |
18839 | p = frag_var (rs_align_code, |
18840 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
18841 | 1, | |
18842 | (relax_substateT) max, | |
18843 | (symbolS *) NULL, | |
18844 | (offsetT) n, | |
18845 | (char *) NULL); | |
18846 | *p = 0; | |
18847 | } | |
bfae80f2 | 18848 | |
8dc2430f NC |
18849 | /* Perform target specific initialisation of a frag. |
18850 | Note - despite the name this initialisation is not done when the frag | |
18851 | is created, but only when its type is assigned. A frag can be created | |
18852 | and used a long time before its type is set, so beware of assuming that | |
18853 | this initialisationis performed first. */ | |
bfae80f2 | 18854 | |
cd000bff DJ |
18855 | #ifndef OBJ_ELF |
18856 | void | |
18857 | arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) | |
18858 | { | |
18859 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
2e98972e | 18860 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
cd000bff DJ |
18861 | } |
18862 | ||
18863 | #else /* OBJ_ELF is defined. */ | |
c19d1205 | 18864 | void |
cd000bff | 18865 | arm_init_frag (fragS * fragP, int max_chars) |
c19d1205 | 18866 | { |
8dc2430f NC |
18867 | /* If the current ARM vs THUMB mode has not already |
18868 | been recorded into this frag then do so now. */ | |
cd000bff DJ |
18869 | if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) |
18870 | { | |
18871 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; | |
18872 | ||
18873 | /* Record a mapping symbol for alignment frags. We will delete this | |
18874 | later if the alignment ends up empty. */ | |
18875 | switch (fragP->fr_type) | |
18876 | { | |
18877 | case rs_align: | |
18878 | case rs_align_test: | |
18879 | case rs_fill: | |
18880 | mapping_state_2 (MAP_DATA, max_chars); | |
18881 | break; | |
18882 | case rs_align_code: | |
18883 | mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); | |
18884 | break; | |
18885 | default: | |
18886 | break; | |
18887 | } | |
18888 | } | |
bfae80f2 RE |
18889 | } |
18890 | ||
c19d1205 ZW |
18891 | /* When we change sections we need to issue a new mapping symbol. */ |
18892 | ||
18893 | void | |
18894 | arm_elf_change_section (void) | |
bfae80f2 | 18895 | { |
c19d1205 ZW |
18896 | /* Link an unlinked unwind index table section to the .text section. */ |
18897 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
18898 | && elf_linked_to_section (now_seg) == NULL) | |
18899 | elf_linked_to_section (now_seg) = text_section; | |
bfae80f2 RE |
18900 | } |
18901 | ||
c19d1205 ZW |
18902 | int |
18903 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 18904 | { |
c19d1205 ZW |
18905 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
18906 | return SHT_ARM_EXIDX; | |
e45d0630 | 18907 | |
c19d1205 ZW |
18908 | return -1; |
18909 | } | |
18910 | \f | |
18911 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 18912 | |
c19d1205 | 18913 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 18914 | |
5f4273c7 | 18915 | /* Generate any deferred unwind frame offset. */ |
e45d0630 | 18916 | |
bfae80f2 | 18917 | static void |
c19d1205 | 18918 | flush_pending_unwind (void) |
bfae80f2 | 18919 | { |
c19d1205 | 18920 | offsetT offset; |
bfae80f2 | 18921 | |
c19d1205 ZW |
18922 | offset = unwind.pending_offset; |
18923 | unwind.pending_offset = 0; | |
18924 | if (offset != 0) | |
18925 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
18926 | } |
18927 | ||
c19d1205 ZW |
18928 | /* Add an opcode to this list for this function. Two-byte opcodes should |
18929 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
18930 | order. */ | |
18931 | ||
bfae80f2 | 18932 | static void |
c19d1205 | 18933 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 18934 | { |
c19d1205 ZW |
18935 | /* Add any deferred stack adjustment. */ |
18936 | if (unwind.pending_offset) | |
18937 | flush_pending_unwind (); | |
bfae80f2 | 18938 | |
c19d1205 | 18939 | unwind.sp_restored = 0; |
bfae80f2 | 18940 | |
c19d1205 | 18941 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 18942 | { |
c19d1205 ZW |
18943 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
18944 | if (unwind.opcodes) | |
21d799b5 NC |
18945 | unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes, |
18946 | unwind.opcode_alloc); | |
c19d1205 | 18947 | else |
21d799b5 | 18948 | unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc); |
bfae80f2 | 18949 | } |
c19d1205 | 18950 | while (length > 0) |
bfae80f2 | 18951 | { |
c19d1205 ZW |
18952 | length--; |
18953 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
18954 | op >>= 8; | |
18955 | unwind.opcode_count++; | |
bfae80f2 | 18956 | } |
bfae80f2 RE |
18957 | } |
18958 | ||
c19d1205 ZW |
18959 | /* Add unwind opcodes to adjust the stack pointer. */ |
18960 | ||
bfae80f2 | 18961 | static void |
c19d1205 | 18962 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 18963 | { |
c19d1205 | 18964 | valueT op; |
bfae80f2 | 18965 | |
c19d1205 | 18966 | if (offset > 0x200) |
bfae80f2 | 18967 | { |
c19d1205 ZW |
18968 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
18969 | char bytes[5]; | |
18970 | int n; | |
18971 | valueT o; | |
bfae80f2 | 18972 | |
c19d1205 ZW |
18973 | /* Long form: 0xb2, uleb128. */ |
18974 | /* This might not fit in a word so add the individual bytes, | |
18975 | remembering the list is built in reverse order. */ | |
18976 | o = (valueT) ((offset - 0x204) >> 2); | |
18977 | if (o == 0) | |
18978 | add_unwind_opcode (0, 1); | |
bfae80f2 | 18979 | |
c19d1205 ZW |
18980 | /* Calculate the uleb128 encoding of the offset. */ |
18981 | n = 0; | |
18982 | while (o) | |
18983 | { | |
18984 | bytes[n] = o & 0x7f; | |
18985 | o >>= 7; | |
18986 | if (o) | |
18987 | bytes[n] |= 0x80; | |
18988 | n++; | |
18989 | } | |
18990 | /* Add the insn. */ | |
18991 | for (; n; n--) | |
18992 | add_unwind_opcode (bytes[n - 1], 1); | |
18993 | add_unwind_opcode (0xb2, 1); | |
18994 | } | |
18995 | else if (offset > 0x100) | |
bfae80f2 | 18996 | { |
c19d1205 ZW |
18997 | /* Two short opcodes. */ |
18998 | add_unwind_opcode (0x3f, 1); | |
18999 | op = (offset - 0x104) >> 2; | |
19000 | add_unwind_opcode (op, 1); | |
bfae80f2 | 19001 | } |
c19d1205 ZW |
19002 | else if (offset > 0) |
19003 | { | |
19004 | /* Short opcode. */ | |
19005 | op = (offset - 4) >> 2; | |
19006 | add_unwind_opcode (op, 1); | |
19007 | } | |
19008 | else if (offset < 0) | |
bfae80f2 | 19009 | { |
c19d1205 ZW |
19010 | offset = -offset; |
19011 | while (offset > 0x100) | |
bfae80f2 | 19012 | { |
c19d1205 ZW |
19013 | add_unwind_opcode (0x7f, 1); |
19014 | offset -= 0x100; | |
bfae80f2 | 19015 | } |
c19d1205 ZW |
19016 | op = ((offset - 4) >> 2) | 0x40; |
19017 | add_unwind_opcode (op, 1); | |
bfae80f2 | 19018 | } |
bfae80f2 RE |
19019 | } |
19020 | ||
c19d1205 ZW |
19021 | /* Finish the list of unwind opcodes for this function. */ |
19022 | static void | |
19023 | finish_unwind_opcodes (void) | |
bfae80f2 | 19024 | { |
c19d1205 | 19025 | valueT op; |
bfae80f2 | 19026 | |
c19d1205 | 19027 | if (unwind.fp_used) |
bfae80f2 | 19028 | { |
708587a4 | 19029 | /* Adjust sp as necessary. */ |
c19d1205 ZW |
19030 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
19031 | flush_pending_unwind (); | |
bfae80f2 | 19032 | |
c19d1205 ZW |
19033 | /* After restoring sp from the frame pointer. */ |
19034 | op = 0x90 | unwind.fp_reg; | |
19035 | add_unwind_opcode (op, 1); | |
19036 | } | |
19037 | else | |
19038 | flush_pending_unwind (); | |
bfae80f2 RE |
19039 | } |
19040 | ||
bfae80f2 | 19041 | |
c19d1205 ZW |
19042 | /* Start an exception table entry. If idx is nonzero this is an index table |
19043 | entry. */ | |
bfae80f2 RE |
19044 | |
19045 | static void | |
c19d1205 | 19046 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 19047 | { |
c19d1205 ZW |
19048 | const char * text_name; |
19049 | const char * prefix; | |
19050 | const char * prefix_once; | |
19051 | const char * group_name; | |
19052 | size_t prefix_len; | |
19053 | size_t text_len; | |
19054 | char * sec_name; | |
19055 | size_t sec_name_len; | |
19056 | int type; | |
19057 | int flags; | |
19058 | int linkonce; | |
bfae80f2 | 19059 | |
c19d1205 | 19060 | if (idx) |
bfae80f2 | 19061 | { |
c19d1205 ZW |
19062 | prefix = ELF_STRING_ARM_unwind; |
19063 | prefix_once = ELF_STRING_ARM_unwind_once; | |
19064 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 19065 | } |
c19d1205 | 19066 | else |
bfae80f2 | 19067 | { |
c19d1205 ZW |
19068 | prefix = ELF_STRING_ARM_unwind_info; |
19069 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
19070 | type = SHT_PROGBITS; | |
bfae80f2 RE |
19071 | } |
19072 | ||
c19d1205 ZW |
19073 | text_name = segment_name (text_seg); |
19074 | if (streq (text_name, ".text")) | |
19075 | text_name = ""; | |
19076 | ||
19077 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
19078 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 19079 | { |
c19d1205 ZW |
19080 | prefix = prefix_once; |
19081 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
19082 | } |
19083 | ||
c19d1205 ZW |
19084 | prefix_len = strlen (prefix); |
19085 | text_len = strlen (text_name); | |
19086 | sec_name_len = prefix_len + text_len; | |
21d799b5 | 19087 | sec_name = (char *) xmalloc (sec_name_len + 1); |
c19d1205 ZW |
19088 | memcpy (sec_name, prefix, prefix_len); |
19089 | memcpy (sec_name + prefix_len, text_name, text_len); | |
19090 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 19091 | |
c19d1205 ZW |
19092 | flags = SHF_ALLOC; |
19093 | linkonce = 0; | |
19094 | group_name = 0; | |
bfae80f2 | 19095 | |
c19d1205 ZW |
19096 | /* Handle COMDAT group. */ |
19097 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 19098 | { |
c19d1205 ZW |
19099 | group_name = elf_group_name (text_seg); |
19100 | if (group_name == NULL) | |
19101 | { | |
bd3ba5d1 | 19102 | as_bad (_("Group section `%s' has no group signature"), |
c19d1205 ZW |
19103 | segment_name (text_seg)); |
19104 | ignore_rest_of_line (); | |
19105 | return; | |
19106 | } | |
19107 | flags |= SHF_GROUP; | |
19108 | linkonce = 1; | |
bfae80f2 RE |
19109 | } |
19110 | ||
c19d1205 | 19111 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 19112 | |
5f4273c7 | 19113 | /* Set the section link for index tables. */ |
c19d1205 ZW |
19114 | if (idx) |
19115 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
19116 | } |
19117 | ||
bfae80f2 | 19118 | |
c19d1205 ZW |
19119 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
19120 | personality routine data. Returns zero, or the index table value for | |
19121 | and inline entry. */ | |
19122 | ||
19123 | static valueT | |
19124 | create_unwind_entry (int have_data) | |
bfae80f2 | 19125 | { |
c19d1205 ZW |
19126 | int size; |
19127 | addressT where; | |
19128 | char *ptr; | |
19129 | /* The current word of data. */ | |
19130 | valueT data; | |
19131 | /* The number of bytes left in this word. */ | |
19132 | int n; | |
bfae80f2 | 19133 | |
c19d1205 | 19134 | finish_unwind_opcodes (); |
bfae80f2 | 19135 | |
c19d1205 ZW |
19136 | /* Remember the current text section. */ |
19137 | unwind.saved_seg = now_seg; | |
19138 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 19139 | |
c19d1205 | 19140 | start_unwind_section (now_seg, 0); |
bfae80f2 | 19141 | |
c19d1205 | 19142 | if (unwind.personality_routine == NULL) |
bfae80f2 | 19143 | { |
c19d1205 ZW |
19144 | if (unwind.personality_index == -2) |
19145 | { | |
19146 | if (have_data) | |
5f4273c7 | 19147 | as_bad (_("handlerdata in cantunwind frame")); |
c19d1205 ZW |
19148 | return 1; /* EXIDX_CANTUNWIND. */ |
19149 | } | |
bfae80f2 | 19150 | |
c19d1205 ZW |
19151 | /* Use a default personality routine if none is specified. */ |
19152 | if (unwind.personality_index == -1) | |
19153 | { | |
19154 | if (unwind.opcode_count > 3) | |
19155 | unwind.personality_index = 1; | |
19156 | else | |
19157 | unwind.personality_index = 0; | |
19158 | } | |
bfae80f2 | 19159 | |
c19d1205 ZW |
19160 | /* Space for the personality routine entry. */ |
19161 | if (unwind.personality_index == 0) | |
19162 | { | |
19163 | if (unwind.opcode_count > 3) | |
19164 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 19165 | |
c19d1205 ZW |
19166 | if (!have_data) |
19167 | { | |
19168 | /* All the data is inline in the index table. */ | |
19169 | data = 0x80; | |
19170 | n = 3; | |
19171 | while (unwind.opcode_count > 0) | |
19172 | { | |
19173 | unwind.opcode_count--; | |
19174 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
19175 | n--; | |
19176 | } | |
bfae80f2 | 19177 | |
c19d1205 ZW |
19178 | /* Pad with "finish" opcodes. */ |
19179 | while (n--) | |
19180 | data = (data << 8) | 0xb0; | |
bfae80f2 | 19181 | |
c19d1205 ZW |
19182 | return data; |
19183 | } | |
19184 | size = 0; | |
19185 | } | |
19186 | else | |
19187 | /* We get two opcodes "free" in the first word. */ | |
19188 | size = unwind.opcode_count - 2; | |
19189 | } | |
19190 | else | |
19191 | /* An extra byte is required for the opcode count. */ | |
19192 | size = unwind.opcode_count + 1; | |
bfae80f2 | 19193 | |
c19d1205 ZW |
19194 | size = (size + 3) >> 2; |
19195 | if (size > 0xff) | |
19196 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 19197 | |
c19d1205 ZW |
19198 | frag_align (2, 0, 0); |
19199 | record_alignment (now_seg, 2); | |
19200 | unwind.table_entry = expr_build_dot (); | |
19201 | ||
19202 | /* Allocate the table entry. */ | |
19203 | ptr = frag_more ((size << 2) + 4); | |
19204 | where = frag_now_fix () - ((size << 2) + 4); | |
bfae80f2 | 19205 | |
c19d1205 | 19206 | switch (unwind.personality_index) |
bfae80f2 | 19207 | { |
c19d1205 ZW |
19208 | case -1: |
19209 | /* ??? Should this be a PLT generating relocation? */ | |
19210 | /* Custom personality routine. */ | |
19211 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
19212 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 19213 | |
c19d1205 ZW |
19214 | where += 4; |
19215 | ptr += 4; | |
bfae80f2 | 19216 | |
c19d1205 ZW |
19217 | /* Set the first byte to the number of additional words. */ |
19218 | data = size - 1; | |
19219 | n = 3; | |
19220 | break; | |
bfae80f2 | 19221 | |
c19d1205 ZW |
19222 | /* ABI defined personality routines. */ |
19223 | case 0: | |
19224 | /* Three opcodes bytes are packed into the first word. */ | |
19225 | data = 0x80; | |
19226 | n = 3; | |
19227 | break; | |
bfae80f2 | 19228 | |
c19d1205 ZW |
19229 | case 1: |
19230 | case 2: | |
19231 | /* The size and first two opcode bytes go in the first word. */ | |
19232 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
19233 | n = 2; | |
19234 | break; | |
bfae80f2 | 19235 | |
c19d1205 ZW |
19236 | default: |
19237 | /* Should never happen. */ | |
19238 | abort (); | |
19239 | } | |
bfae80f2 | 19240 | |
c19d1205 ZW |
19241 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
19242 | time. */ | |
19243 | while (unwind.opcode_count > 0) | |
19244 | { | |
19245 | if (n == 0) | |
19246 | { | |
19247 | md_number_to_chars (ptr, data, 4); | |
19248 | ptr += 4; | |
19249 | n = 4; | |
19250 | data = 0; | |
19251 | } | |
19252 | unwind.opcode_count--; | |
19253 | n--; | |
19254 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
19255 | } | |
19256 | ||
19257 | /* Finish off the last word. */ | |
19258 | if (n < 4) | |
19259 | { | |
19260 | /* Pad with "finish" opcodes. */ | |
19261 | while (n--) | |
19262 | data = (data << 8) | 0xb0; | |
19263 | ||
19264 | md_number_to_chars (ptr, data, 4); | |
19265 | } | |
19266 | ||
19267 | if (!have_data) | |
19268 | { | |
19269 | /* Add an empty descriptor if there is no user-specified data. */ | |
19270 | ptr = frag_more (4); | |
19271 | md_number_to_chars (ptr, 0, 4); | |
19272 | } | |
19273 | ||
19274 | return 0; | |
bfae80f2 RE |
19275 | } |
19276 | ||
f0927246 NC |
19277 | |
19278 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
19279 | ||
19280 | void | |
19281 | tc_arm_frame_initial_instructions (void) | |
19282 | { | |
19283 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
19284 | } | |
19285 | #endif /* OBJ_ELF */ | |
19286 | ||
c19d1205 ZW |
19287 | /* Convert REGNAME to a DWARF-2 register number. */ |
19288 | ||
19289 | int | |
1df69f4f | 19290 | tc_arm_regname_to_dw2regnum (char *regname) |
bfae80f2 | 19291 | { |
1df69f4f | 19292 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
c19d1205 ZW |
19293 | |
19294 | if (reg == FAIL) | |
19295 | return -1; | |
19296 | ||
19297 | return reg; | |
bfae80f2 RE |
19298 | } |
19299 | ||
f0927246 | 19300 | #ifdef TE_PE |
c19d1205 | 19301 | void |
f0927246 | 19302 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
bfae80f2 | 19303 | { |
91d6fa6a | 19304 | expressionS exp; |
bfae80f2 | 19305 | |
91d6fa6a NC |
19306 | exp.X_op = O_secrel; |
19307 | exp.X_add_symbol = symbol; | |
19308 | exp.X_add_number = 0; | |
19309 | emit_expr (&exp, size); | |
f0927246 NC |
19310 | } |
19311 | #endif | |
bfae80f2 | 19312 | |
c19d1205 | 19313 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 19314 | |
2fc8bdac ZW |
19315 | /* Return the address within the segment that a PC-relative fixup is |
19316 | relative to. For ARM, PC-relative fixups applied to instructions | |
19317 | are generally relative to the location of the fixup plus 8 bytes. | |
19318 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
19319 | require special handling. */ | |
bfae80f2 | 19320 | |
c19d1205 | 19321 | long |
2fc8bdac | 19322 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 19323 | { |
2fc8bdac ZW |
19324 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
19325 | ||
19326 | /* If this is pc-relative and we are going to emit a relocation | |
19327 | then we just want to put out any pipeline compensation that the linker | |
53baae48 NC |
19328 | will need. Otherwise we want to use the calculated base. |
19329 | For WinCE we skip the bias for externals as well, since this | |
19330 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ | |
5f4273c7 | 19331 | if (fixP->fx_pcrel |
2fc8bdac | 19332 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) |
53baae48 NC |
19333 | || (arm_force_relocation (fixP) |
19334 | #ifdef TE_WINCE | |
19335 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
19336 | #endif | |
19337 | ))) | |
2fc8bdac | 19338 | base = 0; |
bfae80f2 | 19339 | |
267bf995 | 19340 | |
c19d1205 | 19341 | switch (fixP->fx_r_type) |
bfae80f2 | 19342 | { |
2fc8bdac ZW |
19343 | /* PC relative addressing on the Thumb is slightly odd as the |
19344 | bottom two bits of the PC are forced to zero for the | |
19345 | calculation. This happens *after* application of the | |
19346 | pipeline offset. However, Thumb adrl already adjusts for | |
19347 | this, so we need not do it again. */ | |
c19d1205 | 19348 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 19349 | return base & ~3; |
c19d1205 ZW |
19350 | |
19351 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
19352 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 19353 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 19354 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 19355 | return (base + 4) & ~3; |
c19d1205 | 19356 | |
2fc8bdac ZW |
19357 | /* Thumb branches are simply offset by +4. */ |
19358 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
19359 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
19360 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
19361 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
2fc8bdac | 19362 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac | 19363 | return base + 4; |
bfae80f2 | 19364 | |
267bf995 | 19365 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
486499d0 CL |
19366 | if (fixP->fx_addsy |
19367 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19368 | && (!S_IS_EXTERNAL (fixP->fx_addsy)) | |
267bf995 RR |
19369 | && ARM_IS_FUNC (fixP->fx_addsy) |
19370 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19371 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
19372 | return base + 4; | |
19373 | ||
00adf2d4 JB |
19374 | /* BLX is like branches above, but forces the low two bits of PC to |
19375 | zero. */ | |
486499d0 CL |
19376 | case BFD_RELOC_THUMB_PCREL_BLX: |
19377 | if (fixP->fx_addsy | |
19378 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19379 | && (!S_IS_EXTERNAL (fixP->fx_addsy)) | |
267bf995 RR |
19380 | && THUMB_IS_FUNC (fixP->fx_addsy) |
19381 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19382 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
00adf2d4 JB |
19383 | return (base + 4) & ~3; |
19384 | ||
2fc8bdac ZW |
19385 | /* ARM mode branches are offset by +8. However, the Windows CE |
19386 | loader expects the relocation not to take this into account. */ | |
267bf995 | 19387 | case BFD_RELOC_ARM_PCREL_BLX: |
486499d0 CL |
19388 | if (fixP->fx_addsy |
19389 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19390 | && (!S_IS_EXTERNAL (fixP->fx_addsy)) | |
267bf995 RR |
19391 | && ARM_IS_FUNC (fixP->fx_addsy) |
19392 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19393 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 19394 | return base + 8; |
267bf995 | 19395 | |
486499d0 CL |
19396 | case BFD_RELOC_ARM_PCREL_CALL: |
19397 | if (fixP->fx_addsy | |
19398 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19399 | && (!S_IS_EXTERNAL (fixP->fx_addsy)) | |
267bf995 RR |
19400 | && THUMB_IS_FUNC (fixP->fx_addsy) |
19401 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19402 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 19403 | return base + 8; |
267bf995 | 19404 | |
2fc8bdac | 19405 | case BFD_RELOC_ARM_PCREL_BRANCH: |
39b41c9c | 19406 | case BFD_RELOC_ARM_PCREL_JUMP: |
2fc8bdac | 19407 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 19408 | #ifdef TE_WINCE |
5f4273c7 | 19409 | /* When handling fixups immediately, because we have already |
53baae48 NC |
19410 | discovered the value of a symbol, or the address of the frag involved |
19411 | we must account for the offset by +8, as the OS loader will never see the reloc. | |
19412 | see fixup_segment() in write.c | |
19413 | The S_IS_EXTERNAL test handles the case of global symbols. | |
19414 | Those need the calculated base, not just the pipe compensation the linker will need. */ | |
19415 | if (fixP->fx_pcrel | |
19416 | && fixP->fx_addsy != NULL | |
19417 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19418 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) | |
19419 | return base + 8; | |
2fc8bdac | 19420 | return base; |
c19d1205 | 19421 | #else |
2fc8bdac | 19422 | return base + 8; |
c19d1205 | 19423 | #endif |
2fc8bdac | 19424 | |
267bf995 | 19425 | |
2fc8bdac ZW |
19426 | /* ARM mode loads relative to PC are also offset by +8. Unlike |
19427 | branches, the Windows CE loader *does* expect the relocation | |
19428 | to take this into account. */ | |
19429 | case BFD_RELOC_ARM_OFFSET_IMM: | |
19430 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
19431 | case BFD_RELOC_ARM_HWLITERAL: | |
19432 | case BFD_RELOC_ARM_LITERAL: | |
19433 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
19434 | return base + 8; | |
19435 | ||
19436 | ||
19437 | /* Other PC-relative relocations are un-offset. */ | |
19438 | default: | |
19439 | return base; | |
19440 | } | |
bfae80f2 RE |
19441 | } |
19442 | ||
c19d1205 ZW |
19443 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. |
19444 | Otherwise we have no need to default values of symbols. */ | |
19445 | ||
19446 | symbolS * | |
19447 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
bfae80f2 | 19448 | { |
c19d1205 ZW |
19449 | #ifdef OBJ_ELF |
19450 | if (name[0] == '_' && name[1] == 'G' | |
19451 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
19452 | { | |
19453 | if (!GOT_symbol) | |
19454 | { | |
19455 | if (symbol_find (name)) | |
bd3ba5d1 | 19456 | as_bad (_("GOT already in the symbol table")); |
bfae80f2 | 19457 | |
c19d1205 ZW |
19458 | GOT_symbol = symbol_new (name, undefined_section, |
19459 | (valueT) 0, & zero_address_frag); | |
19460 | } | |
bfae80f2 | 19461 | |
c19d1205 | 19462 | return GOT_symbol; |
bfae80f2 | 19463 | } |
c19d1205 | 19464 | #endif |
bfae80f2 | 19465 | |
c921be7d | 19466 | return NULL; |
bfae80f2 RE |
19467 | } |
19468 | ||
55cf6793 | 19469 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
19470 | computed as two separate immediate values, added together. We |
19471 | already know that this value cannot be computed by just one ARM | |
19472 | instruction. */ | |
19473 | ||
19474 | static unsigned int | |
19475 | validate_immediate_twopart (unsigned int val, | |
19476 | unsigned int * highpart) | |
bfae80f2 | 19477 | { |
c19d1205 ZW |
19478 | unsigned int a; |
19479 | unsigned int i; | |
bfae80f2 | 19480 | |
c19d1205 ZW |
19481 | for (i = 0; i < 32; i += 2) |
19482 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
19483 | { | |
19484 | if (a & 0xff00) | |
19485 | { | |
19486 | if (a & ~ 0xffff) | |
19487 | continue; | |
19488 | * highpart = (a >> 8) | ((i + 24) << 7); | |
19489 | } | |
19490 | else if (a & 0xff0000) | |
19491 | { | |
19492 | if (a & 0xff000000) | |
19493 | continue; | |
19494 | * highpart = (a >> 16) | ((i + 16) << 7); | |
19495 | } | |
19496 | else | |
19497 | { | |
9c2799c2 | 19498 | gas_assert (a & 0xff000000); |
c19d1205 ZW |
19499 | * highpart = (a >> 24) | ((i + 8) << 7); |
19500 | } | |
bfae80f2 | 19501 | |
c19d1205 ZW |
19502 | return (a & 0xff) | (i << 7); |
19503 | } | |
bfae80f2 | 19504 | |
c19d1205 | 19505 | return FAIL; |
bfae80f2 RE |
19506 | } |
19507 | ||
c19d1205 ZW |
19508 | static int |
19509 | validate_offset_imm (unsigned int val, int hwse) | |
19510 | { | |
19511 | if ((hwse && val > 255) || val > 4095) | |
19512 | return FAIL; | |
19513 | return val; | |
19514 | } | |
bfae80f2 | 19515 | |
55cf6793 | 19516 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
19517 | negative immediate constant by altering the instruction. A bit of |
19518 | a hack really. | |
19519 | MOV <-> MVN | |
19520 | AND <-> BIC | |
19521 | ADC <-> SBC | |
19522 | by inverting the second operand, and | |
19523 | ADD <-> SUB | |
19524 | CMP <-> CMN | |
19525 | by negating the second operand. */ | |
bfae80f2 | 19526 | |
c19d1205 ZW |
19527 | static int |
19528 | negate_data_op (unsigned long * instruction, | |
19529 | unsigned long value) | |
bfae80f2 | 19530 | { |
c19d1205 ZW |
19531 | int op, new_inst; |
19532 | unsigned long negated, inverted; | |
bfae80f2 | 19533 | |
c19d1205 ZW |
19534 | negated = encode_arm_immediate (-value); |
19535 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 19536 | |
c19d1205 ZW |
19537 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
19538 | switch (op) | |
bfae80f2 | 19539 | { |
c19d1205 ZW |
19540 | /* First negates. */ |
19541 | case OPCODE_SUB: /* ADD <-> SUB */ | |
19542 | new_inst = OPCODE_ADD; | |
19543 | value = negated; | |
19544 | break; | |
bfae80f2 | 19545 | |
c19d1205 ZW |
19546 | case OPCODE_ADD: |
19547 | new_inst = OPCODE_SUB; | |
19548 | value = negated; | |
19549 | break; | |
bfae80f2 | 19550 | |
c19d1205 ZW |
19551 | case OPCODE_CMP: /* CMP <-> CMN */ |
19552 | new_inst = OPCODE_CMN; | |
19553 | value = negated; | |
19554 | break; | |
bfae80f2 | 19555 | |
c19d1205 ZW |
19556 | case OPCODE_CMN: |
19557 | new_inst = OPCODE_CMP; | |
19558 | value = negated; | |
19559 | break; | |
bfae80f2 | 19560 | |
c19d1205 ZW |
19561 | /* Now Inverted ops. */ |
19562 | case OPCODE_MOV: /* MOV <-> MVN */ | |
19563 | new_inst = OPCODE_MVN; | |
19564 | value = inverted; | |
19565 | break; | |
bfae80f2 | 19566 | |
c19d1205 ZW |
19567 | case OPCODE_MVN: |
19568 | new_inst = OPCODE_MOV; | |
19569 | value = inverted; | |
19570 | break; | |
bfae80f2 | 19571 | |
c19d1205 ZW |
19572 | case OPCODE_AND: /* AND <-> BIC */ |
19573 | new_inst = OPCODE_BIC; | |
19574 | value = inverted; | |
19575 | break; | |
bfae80f2 | 19576 | |
c19d1205 ZW |
19577 | case OPCODE_BIC: |
19578 | new_inst = OPCODE_AND; | |
19579 | value = inverted; | |
19580 | break; | |
bfae80f2 | 19581 | |
c19d1205 ZW |
19582 | case OPCODE_ADC: /* ADC <-> SBC */ |
19583 | new_inst = OPCODE_SBC; | |
19584 | value = inverted; | |
19585 | break; | |
bfae80f2 | 19586 | |
c19d1205 ZW |
19587 | case OPCODE_SBC: |
19588 | new_inst = OPCODE_ADC; | |
19589 | value = inverted; | |
19590 | break; | |
bfae80f2 | 19591 | |
c19d1205 ZW |
19592 | /* We cannot do anything. */ |
19593 | default: | |
19594 | return FAIL; | |
b99bd4ef NC |
19595 | } |
19596 | ||
c19d1205 ZW |
19597 | if (value == (unsigned) FAIL) |
19598 | return FAIL; | |
19599 | ||
19600 | *instruction &= OPCODE_MASK; | |
19601 | *instruction |= new_inst << DATA_OP_SHIFT; | |
19602 | return value; | |
b99bd4ef NC |
19603 | } |
19604 | ||
ef8d22e6 PB |
19605 | /* Like negate_data_op, but for Thumb-2. */ |
19606 | ||
19607 | static unsigned int | |
16dd5e42 | 19608 | thumb32_negate_data_op (offsetT *instruction, unsigned int value) |
ef8d22e6 PB |
19609 | { |
19610 | int op, new_inst; | |
19611 | int rd; | |
16dd5e42 | 19612 | unsigned int negated, inverted; |
ef8d22e6 PB |
19613 | |
19614 | negated = encode_thumb32_immediate (-value); | |
19615 | inverted = encode_thumb32_immediate (~value); | |
19616 | ||
19617 | rd = (*instruction >> 8) & 0xf; | |
19618 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
19619 | switch (op) | |
19620 | { | |
19621 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
19622 | case T2_OPCODE_SUB: | |
19623 | new_inst = T2_OPCODE_ADD; | |
19624 | value = negated; | |
19625 | break; | |
19626 | ||
19627 | case T2_OPCODE_ADD: | |
19628 | new_inst = T2_OPCODE_SUB; | |
19629 | value = negated; | |
19630 | break; | |
19631 | ||
19632 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
19633 | case T2_OPCODE_ORR: | |
19634 | new_inst = T2_OPCODE_ORN; | |
19635 | value = inverted; | |
19636 | break; | |
19637 | ||
19638 | case T2_OPCODE_ORN: | |
19639 | new_inst = T2_OPCODE_ORR; | |
19640 | value = inverted; | |
19641 | break; | |
19642 | ||
19643 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
19644 | case T2_OPCODE_AND: | |
19645 | new_inst = T2_OPCODE_BIC; | |
19646 | if (rd == 15) | |
19647 | value = FAIL; | |
19648 | else | |
19649 | value = inverted; | |
19650 | break; | |
19651 | ||
19652 | case T2_OPCODE_BIC: | |
19653 | new_inst = T2_OPCODE_AND; | |
19654 | value = inverted; | |
19655 | break; | |
19656 | ||
19657 | /* ADC <-> SBC */ | |
19658 | case T2_OPCODE_ADC: | |
19659 | new_inst = T2_OPCODE_SBC; | |
19660 | value = inverted; | |
19661 | break; | |
19662 | ||
19663 | case T2_OPCODE_SBC: | |
19664 | new_inst = T2_OPCODE_ADC; | |
19665 | value = inverted; | |
19666 | break; | |
19667 | ||
19668 | /* We cannot do anything. */ | |
19669 | default: | |
19670 | return FAIL; | |
19671 | } | |
19672 | ||
16dd5e42 | 19673 | if (value == (unsigned int)FAIL) |
ef8d22e6 PB |
19674 | return FAIL; |
19675 | ||
19676 | *instruction &= T2_OPCODE_MASK; | |
19677 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
19678 | return value; | |
19679 | } | |
19680 | ||
8f06b2d8 PB |
19681 | /* Read a 32-bit thumb instruction from buf. */ |
19682 | static unsigned long | |
19683 | get_thumb32_insn (char * buf) | |
19684 | { | |
19685 | unsigned long insn; | |
19686 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
19687 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
19688 | ||
19689 | return insn; | |
19690 | } | |
19691 | ||
a8bc6c78 PB |
19692 | |
19693 | /* We usually want to set the low bit on the address of thumb function | |
19694 | symbols. In particular .word foo - . should have the low bit set. | |
19695 | Generic code tries to fold the difference of two symbols to | |
19696 | a constant. Prevent this and force a relocation when the first symbols | |
19697 | is a thumb function. */ | |
c921be7d NC |
19698 | |
19699 | bfd_boolean | |
a8bc6c78 PB |
19700 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) |
19701 | { | |
19702 | if (op == O_subtract | |
19703 | && l->X_op == O_symbol | |
19704 | && r->X_op == O_symbol | |
19705 | && THUMB_IS_FUNC (l->X_add_symbol)) | |
19706 | { | |
19707 | l->X_op = O_subtract; | |
19708 | l->X_op_symbol = r->X_add_symbol; | |
19709 | l->X_add_number -= r->X_add_number; | |
c921be7d | 19710 | return TRUE; |
a8bc6c78 | 19711 | } |
c921be7d | 19712 | |
a8bc6c78 | 19713 | /* Process as normal. */ |
c921be7d | 19714 | return FALSE; |
a8bc6c78 PB |
19715 | } |
19716 | ||
4a42ebbc RR |
19717 | /* Encode Thumb2 unconditional branches and calls. The encoding |
19718 | for the 2 are identical for the immediate values. */ | |
19719 | ||
19720 | static void | |
19721 | encode_thumb2_b_bl_offset (char * buf, offsetT value) | |
19722 | { | |
19723 | #define T2I1I2MASK ((1 << 13) | (1 << 11)) | |
19724 | offsetT newval; | |
19725 | offsetT newval2; | |
19726 | addressT S, I1, I2, lo, hi; | |
19727 | ||
19728 | S = (value >> 24) & 0x01; | |
19729 | I1 = (value >> 23) & 0x01; | |
19730 | I2 = (value >> 22) & 0x01; | |
19731 | hi = (value >> 12) & 0x3ff; | |
19732 | lo = (value >> 1) & 0x7ff; | |
19733 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
19734 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
19735 | newval |= (S << 10) | hi; | |
19736 | newval2 &= ~T2I1I2MASK; | |
19737 | newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK; | |
19738 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
19739 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
19740 | } | |
19741 | ||
c19d1205 | 19742 | void |
55cf6793 | 19743 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
19744 | valueT * valP, |
19745 | segT seg) | |
19746 | { | |
19747 | offsetT value = * valP; | |
19748 | offsetT newval; | |
19749 | unsigned int newimm; | |
19750 | unsigned long temp; | |
19751 | int sign; | |
19752 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 19753 | |
9c2799c2 | 19754 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 19755 | |
c19d1205 | 19756 | /* Note whether this will delete the relocation. */ |
4962c51a | 19757 | |
c19d1205 ZW |
19758 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
19759 | fixP->fx_done = 1; | |
b99bd4ef | 19760 | |
adbaf948 | 19761 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
5f4273c7 | 19762 | consistency with the behaviour on 32-bit hosts. Remember value |
adbaf948 ZW |
19763 | for emit_reloc. */ |
19764 | value &= 0xffffffff; | |
19765 | value ^= 0x80000000; | |
5f4273c7 | 19766 | value -= 0x80000000; |
adbaf948 ZW |
19767 | |
19768 | *valP = value; | |
c19d1205 | 19769 | fixP->fx_addnumber = value; |
b99bd4ef | 19770 | |
adbaf948 ZW |
19771 | /* Same treatment for fixP->fx_offset. */ |
19772 | fixP->fx_offset &= 0xffffffff; | |
19773 | fixP->fx_offset ^= 0x80000000; | |
19774 | fixP->fx_offset -= 0x80000000; | |
19775 | ||
c19d1205 | 19776 | switch (fixP->fx_r_type) |
b99bd4ef | 19777 | { |
c19d1205 ZW |
19778 | case BFD_RELOC_NONE: |
19779 | /* This will need to go in the object file. */ | |
19780 | fixP->fx_done = 0; | |
19781 | break; | |
b99bd4ef | 19782 | |
c19d1205 ZW |
19783 | case BFD_RELOC_ARM_IMMEDIATE: |
19784 | /* We claim that this fixup has been processed here, | |
19785 | even if in fact we generate an error because we do | |
19786 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
19787 | fixP->fx_done = 1; | |
b99bd4ef | 19788 | |
77db8e2e | 19789 | if (fixP->fx_addsy) |
b99bd4ef | 19790 | { |
77db8e2e | 19791 | const char *msg = 0; |
b99bd4ef | 19792 | |
77db8e2e NC |
19793 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
19794 | msg = _("undefined symbol %s used as an immediate value"); | |
19795 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
19796 | msg = _("symbol %s is in a different section"); | |
19797 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
19798 | msg = _("symbol %s is weak and may be overridden later"); | |
19799 | ||
19800 | if (msg) | |
19801 | { | |
19802 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19803 | msg, S_GET_NAME (fixP->fx_addsy)); | |
19804 | break; | |
19805 | } | |
42e5fcbf AS |
19806 | } |
19807 | ||
c19d1205 ZW |
19808 | newimm = encode_arm_immediate (value); |
19809 | temp = md_chars_to_number (buf, INSN_SIZE); | |
19810 | ||
19811 | /* If the instruction will fail, see if we can fix things up by | |
19812 | changing the opcode. */ | |
19813 | if (newimm == (unsigned int) FAIL | |
19814 | && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) | |
b99bd4ef | 19815 | { |
c19d1205 ZW |
19816 | as_bad_where (fixP->fx_file, fixP->fx_line, |
19817 | _("invalid constant (%lx) after fixup"), | |
19818 | (unsigned long) value); | |
19819 | break; | |
b99bd4ef | 19820 | } |
b99bd4ef | 19821 | |
c19d1205 ZW |
19822 | newimm |= (temp & 0xfffff000); |
19823 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
19824 | break; | |
b99bd4ef | 19825 | |
c19d1205 ZW |
19826 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
19827 | { | |
19828 | unsigned int highpart = 0; | |
19829 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 19830 | |
77db8e2e | 19831 | if (fixP->fx_addsy) |
42e5fcbf | 19832 | { |
77db8e2e | 19833 | const char *msg = 0; |
42e5fcbf | 19834 | |
77db8e2e NC |
19835 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
19836 | msg = _("undefined symbol %s used as an immediate value"); | |
19837 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
19838 | msg = _("symbol %s is in a different section"); | |
19839 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
19840 | msg = _("symbol %s is weak and may be overridden later"); | |
42e5fcbf | 19841 | |
77db8e2e NC |
19842 | if (msg) |
19843 | { | |
19844 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19845 | msg, S_GET_NAME (fixP->fx_addsy)); | |
19846 | break; | |
19847 | } | |
19848 | } | |
19849 | ||
c19d1205 ZW |
19850 | newimm = encode_arm_immediate (value); |
19851 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 19852 | |
c19d1205 ZW |
19853 | /* If the instruction will fail, see if we can fix things up by |
19854 | changing the opcode. */ | |
19855 | if (newimm == (unsigned int) FAIL | |
19856 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
19857 | { | |
19858 | /* No ? OK - try using two ADD instructions to generate | |
19859 | the value. */ | |
19860 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 19861 | |
c19d1205 ZW |
19862 | /* Yes - then make sure that the second instruction is |
19863 | also an add. */ | |
19864 | if (newimm != (unsigned int) FAIL) | |
19865 | newinsn = temp; | |
19866 | /* Still No ? Try using a negated value. */ | |
19867 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
19868 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
19869 | /* Otherwise - give up. */ | |
19870 | else | |
19871 | { | |
19872 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19873 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
19874 | (long) value); | |
19875 | break; | |
19876 | } | |
b99bd4ef | 19877 | |
c19d1205 ZW |
19878 | /* Replace the first operand in the 2nd instruction (which |
19879 | is the PC) with the destination register. We have | |
19880 | already added in the PC in the first instruction and we | |
19881 | do not want to do it again. */ | |
19882 | newinsn &= ~ 0xf0000; | |
19883 | newinsn |= ((newinsn & 0x0f000) << 4); | |
19884 | } | |
b99bd4ef | 19885 | |
c19d1205 ZW |
19886 | newimm |= (temp & 0xfffff000); |
19887 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 19888 | |
c19d1205 ZW |
19889 | highpart |= (newinsn & 0xfffff000); |
19890 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
19891 | } | |
19892 | break; | |
b99bd4ef | 19893 | |
c19d1205 | 19894 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
19895 | if (!fixP->fx_done && seg->use_rela_p) |
19896 | value = 0; | |
19897 | ||
c19d1205 ZW |
19898 | case BFD_RELOC_ARM_LITERAL: |
19899 | sign = value >= 0; | |
b99bd4ef | 19900 | |
c19d1205 ZW |
19901 | if (value < 0) |
19902 | value = - value; | |
b99bd4ef | 19903 | |
c19d1205 | 19904 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 19905 | { |
c19d1205 ZW |
19906 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
19907 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19908 | _("invalid literal constant: pool needs to be closer")); | |
19909 | else | |
19910 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19911 | _("bad immediate value for offset (%ld)"), | |
19912 | (long) value); | |
19913 | break; | |
f03698e6 RE |
19914 | } |
19915 | ||
c19d1205 ZW |
19916 | newval = md_chars_to_number (buf, INSN_SIZE); |
19917 | newval &= 0xff7ff000; | |
19918 | newval |= value | (sign ? INDEX_UP : 0); | |
19919 | md_number_to_chars (buf, newval, INSN_SIZE); | |
19920 | break; | |
b99bd4ef | 19921 | |
c19d1205 ZW |
19922 | case BFD_RELOC_ARM_OFFSET_IMM8: |
19923 | case BFD_RELOC_ARM_HWLITERAL: | |
19924 | sign = value >= 0; | |
b99bd4ef | 19925 | |
c19d1205 ZW |
19926 | if (value < 0) |
19927 | value = - value; | |
b99bd4ef | 19928 | |
c19d1205 | 19929 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 19930 | { |
c19d1205 ZW |
19931 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
19932 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19933 | _("invalid literal constant: pool needs to be closer")); | |
19934 | else | |
f9d4405b | 19935 | as_bad (_("bad immediate value for 8-bit offset (%ld)"), |
c19d1205 ZW |
19936 | (long) value); |
19937 | break; | |
b99bd4ef NC |
19938 | } |
19939 | ||
c19d1205 ZW |
19940 | newval = md_chars_to_number (buf, INSN_SIZE); |
19941 | newval &= 0xff7ff0f0; | |
19942 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
19943 | md_number_to_chars (buf, newval, INSN_SIZE); | |
19944 | break; | |
b99bd4ef | 19945 | |
c19d1205 ZW |
19946 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
19947 | if (value < 0 || value > 1020 || value % 4 != 0) | |
19948 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19949 | _("bad immediate value for offset (%ld)"), (long) value); | |
19950 | value /= 4; | |
b99bd4ef | 19951 | |
c19d1205 | 19952 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
19953 | newval |= value; |
19954 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
19955 | break; | |
b99bd4ef | 19956 | |
c19d1205 ZW |
19957 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
19958 | /* This is a complicated relocation used for all varieties of Thumb32 | |
19959 | load/store instruction with immediate offset: | |
19960 | ||
19961 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
19962 | *4, optional writeback(W) | |
19963 | (doubleword load/store) | |
19964 | ||
19965 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
19966 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
19967 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
19968 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
19969 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
19970 | ||
19971 | Uppercase letters indicate bits that are already encoded at | |
19972 | this point. Lowercase letters are our problem. For the | |
19973 | second block of instructions, the secondary opcode nybble | |
19974 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
19975 | a PC-relative operation. */ | |
19976 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
19977 | newval <<= 16; | |
19978 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 19979 | |
c19d1205 | 19980 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 19981 | { |
c19d1205 ZW |
19982 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
19983 | if (value >= 0) | |
19984 | newval |= (1 << 23); | |
19985 | else | |
19986 | value = -value; | |
19987 | if (value % 4 != 0) | |
19988 | { | |
19989 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19990 | _("offset not a multiple of 4")); | |
19991 | break; | |
19992 | } | |
19993 | value /= 4; | |
216d22bc | 19994 | if (value > 0xff) |
c19d1205 ZW |
19995 | { |
19996 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19997 | _("offset out of range")); | |
19998 | break; | |
19999 | } | |
20000 | newval &= ~0xff; | |
b99bd4ef | 20001 | } |
c19d1205 | 20002 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 20003 | { |
c19d1205 ZW |
20004 | /* PC-relative, 12-bit offset. */ |
20005 | if (value >= 0) | |
20006 | newval |= (1 << 23); | |
20007 | else | |
20008 | value = -value; | |
216d22bc | 20009 | if (value > 0xfff) |
c19d1205 ZW |
20010 | { |
20011 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20012 | _("offset out of range")); | |
20013 | break; | |
20014 | } | |
20015 | newval &= ~0xfff; | |
b99bd4ef | 20016 | } |
c19d1205 | 20017 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 20018 | { |
c19d1205 ZW |
20019 | /* Writeback: 8-bit, +/- offset. */ |
20020 | if (value >= 0) | |
20021 | newval |= (1 << 9); | |
20022 | else | |
20023 | value = -value; | |
216d22bc | 20024 | if (value > 0xff) |
c19d1205 ZW |
20025 | { |
20026 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20027 | _("offset out of range")); | |
20028 | break; | |
20029 | } | |
20030 | newval &= ~0xff; | |
b99bd4ef | 20031 | } |
c19d1205 | 20032 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 20033 | { |
c19d1205 | 20034 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 20035 | if (value < 0 || value > 0xff) |
b99bd4ef | 20036 | { |
c19d1205 ZW |
20037 | as_bad_where (fixP->fx_file, fixP->fx_line, |
20038 | _("offset out of range")); | |
20039 | break; | |
b99bd4ef | 20040 | } |
c19d1205 ZW |
20041 | newval &= ~0xff; |
20042 | newval |= value; | |
b99bd4ef NC |
20043 | } |
20044 | else | |
b99bd4ef | 20045 | { |
c19d1205 ZW |
20046 | /* Positive 12-bit or negative 8-bit offset. */ |
20047 | int limit; | |
20048 | if (value >= 0) | |
b99bd4ef | 20049 | { |
c19d1205 ZW |
20050 | newval |= (1 << 23); |
20051 | limit = 0xfff; | |
20052 | } | |
20053 | else | |
20054 | { | |
20055 | value = -value; | |
20056 | limit = 0xff; | |
20057 | } | |
20058 | if (value > limit) | |
20059 | { | |
20060 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20061 | _("offset out of range")); | |
20062 | break; | |
b99bd4ef | 20063 | } |
c19d1205 | 20064 | newval &= ~limit; |
b99bd4ef | 20065 | } |
b99bd4ef | 20066 | |
c19d1205 ZW |
20067 | newval |= value; |
20068 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
20069 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
20070 | break; | |
404ff6b5 | 20071 | |
c19d1205 ZW |
20072 | case BFD_RELOC_ARM_SHIFT_IMM: |
20073 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20074 | if (((unsigned long) value) > 32 | |
20075 | || (value == 32 | |
20076 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
20077 | { | |
20078 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20079 | _("shift expression is too large")); | |
20080 | break; | |
20081 | } | |
404ff6b5 | 20082 | |
c19d1205 ZW |
20083 | if (value == 0) |
20084 | /* Shifts of zero must be done as lsl. */ | |
20085 | newval &= ~0x60; | |
20086 | else if (value == 32) | |
20087 | value = 0; | |
20088 | newval &= 0xfffff07f; | |
20089 | newval |= (value & 0x1f) << 7; | |
20090 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20091 | break; | |
404ff6b5 | 20092 | |
c19d1205 | 20093 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
16805f35 | 20094 | case BFD_RELOC_ARM_T32_ADD_IMM: |
92e90b6e | 20095 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 20096 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
20097 | /* We claim that this fixup has been processed here, |
20098 | even if in fact we generate an error because we do | |
20099 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
20100 | fixP->fx_done = 1; | |
404ff6b5 | 20101 | |
c19d1205 ZW |
20102 | if (fixP->fx_addsy |
20103 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
20104 | { | |
20105 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20106 | _("undefined symbol %s used as an immediate value"), | |
20107 | S_GET_NAME (fixP->fx_addsy)); | |
20108 | break; | |
20109 | } | |
404ff6b5 | 20110 | |
c19d1205 ZW |
20111 | newval = md_chars_to_number (buf, THUMB_SIZE); |
20112 | newval <<= 16; | |
20113 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 20114 | |
16805f35 PB |
20115 | newimm = FAIL; |
20116 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE | |
20117 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
ef8d22e6 PB |
20118 | { |
20119 | newimm = encode_thumb32_immediate (value); | |
20120 | if (newimm == (unsigned int) FAIL) | |
20121 | newimm = thumb32_negate_data_op (&newval, value); | |
20122 | } | |
16805f35 PB |
20123 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE |
20124 | && newimm == (unsigned int) FAIL) | |
92e90b6e | 20125 | { |
16805f35 PB |
20126 | /* Turn add/sum into addw/subw. */ |
20127 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
20128 | newval = (newval & 0xfeffffff) | 0x02000000; | |
20129 | ||
e9f89963 PB |
20130 | /* 12 bit immediate for addw/subw. */ |
20131 | if (value < 0) | |
20132 | { | |
20133 | value = -value; | |
20134 | newval ^= 0x00a00000; | |
20135 | } | |
92e90b6e PB |
20136 | if (value > 0xfff) |
20137 | newimm = (unsigned int) FAIL; | |
20138 | else | |
20139 | newimm = value; | |
20140 | } | |
cc8a6dd0 | 20141 | |
c19d1205 | 20142 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 20143 | { |
c19d1205 ZW |
20144 | as_bad_where (fixP->fx_file, fixP->fx_line, |
20145 | _("invalid constant (%lx) after fixup"), | |
20146 | (unsigned long) value); | |
20147 | break; | |
3631a3c8 NC |
20148 | } |
20149 | ||
c19d1205 ZW |
20150 | newval |= (newimm & 0x800) << 15; |
20151 | newval |= (newimm & 0x700) << 4; | |
20152 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 20153 | |
c19d1205 ZW |
20154 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
20155 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
20156 | break; | |
a737bd4d | 20157 | |
3eb17e6b | 20158 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
20159 | if (((unsigned long) value) > 0xffff) |
20160 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 20161 | _("invalid smc expression")); |
2fc8bdac | 20162 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
20163 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
20164 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20165 | break; | |
a737bd4d | 20166 | |
c19d1205 | 20167 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 20168 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
20169 | { |
20170 | if (((unsigned long) value) > 0xff) | |
20171 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20172 | _("invalid swi expression")); | |
2fc8bdac | 20173 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
20174 | newval |= value; |
20175 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20176 | } | |
20177 | else | |
20178 | { | |
20179 | if (((unsigned long) value) > 0x00ffffff) | |
20180 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20181 | _("invalid swi expression")); | |
2fc8bdac | 20182 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
20183 | newval |= value; |
20184 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20185 | } | |
20186 | break; | |
a737bd4d | 20187 | |
c19d1205 ZW |
20188 | case BFD_RELOC_ARM_MULTI: |
20189 | if (((unsigned long) value) > 0xffff) | |
20190 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20191 | _("invalid expression in load/store multiple")); | |
20192 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
20193 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20194 | break; | |
a737bd4d | 20195 | |
c19d1205 | 20196 | #ifdef OBJ_ELF |
39b41c9c | 20197 | case BFD_RELOC_ARM_PCREL_CALL: |
267bf995 RR |
20198 | |
20199 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
20200 | && fixP->fx_addsy | |
20201 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20202 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20203 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
20204 | /* Flip the bl to blx. This is a simple flip | |
20205 | bit here because we generate PCREL_CALL for | |
20206 | unconditional bls. */ | |
20207 | { | |
20208 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20209 | newval = newval | 0x10000000; | |
20210 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20211 | temp = 1; | |
20212 | fixP->fx_done = 1; | |
20213 | } | |
39b41c9c PB |
20214 | else |
20215 | temp = 3; | |
20216 | goto arm_branch_common; | |
20217 | ||
20218 | case BFD_RELOC_ARM_PCREL_JUMP: | |
267bf995 RR |
20219 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
20220 | && fixP->fx_addsy | |
20221 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20222 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20223 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
20224 | { | |
20225 | /* This would map to a bl<cond>, b<cond>, | |
20226 | b<always> to a Thumb function. We | |
20227 | need to force a relocation for this particular | |
20228 | case. */ | |
20229 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20230 | fixP->fx_done = 0; | |
20231 | } | |
20232 | ||
2fc8bdac | 20233 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 20234 | #endif |
39b41c9c PB |
20235 | case BFD_RELOC_ARM_PCREL_BRANCH: |
20236 | temp = 3; | |
20237 | goto arm_branch_common; | |
a737bd4d | 20238 | |
39b41c9c | 20239 | case BFD_RELOC_ARM_PCREL_BLX: |
267bf995 | 20240 | |
39b41c9c | 20241 | temp = 1; |
267bf995 RR |
20242 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
20243 | && fixP->fx_addsy | |
20244 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20245 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20246 | && ARM_IS_FUNC (fixP->fx_addsy)) | |
20247 | { | |
20248 | /* Flip the blx to a bl and warn. */ | |
20249 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
20250 | newval = 0xeb000000; | |
20251 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
20252 | _("blx to '%s' an ARM ISA state function changed to bl"), | |
20253 | name); | |
20254 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20255 | temp = 3; | |
20256 | fixP->fx_done = 1; | |
20257 | } | |
20258 | ||
20259 | #ifdef OBJ_ELF | |
20260 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
20261 | fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; | |
20262 | #endif | |
20263 | ||
39b41c9c | 20264 | arm_branch_common: |
c19d1205 | 20265 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
20266 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
20267 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
20268 | also be be clear. */ | |
20269 | if (value & temp) | |
c19d1205 | 20270 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
20271 | _("misaligned branch destination")); |
20272 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
20273 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
20274 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20275 | _("branch out of range")); | |
a737bd4d | 20276 | |
2fc8bdac | 20277 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 20278 | { |
2fc8bdac ZW |
20279 | newval = md_chars_to_number (buf, INSN_SIZE); |
20280 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
20281 | /* Set the H bit on BLX instructions. */ |
20282 | if (temp == 1) | |
20283 | { | |
20284 | if (value & 2) | |
20285 | newval |= 0x01000000; | |
20286 | else | |
20287 | newval &= ~0x01000000; | |
20288 | } | |
2fc8bdac | 20289 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 20290 | } |
c19d1205 | 20291 | break; |
a737bd4d | 20292 | |
25fe350b MS |
20293 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ |
20294 | /* CBZ can only branch forward. */ | |
a737bd4d | 20295 | |
738755b0 MS |
20296 | /* Attempts to use CBZ to branch to the next instruction |
20297 | (which, strictly speaking, are prohibited) will be turned into | |
20298 | no-ops. | |
20299 | ||
20300 | FIXME: It may be better to remove the instruction completely and | |
20301 | perform relaxation. */ | |
20302 | if (value == -2) | |
2fc8bdac ZW |
20303 | { |
20304 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
738755b0 | 20305 | newval = 0xbf00; /* NOP encoding T1 */ |
2fc8bdac ZW |
20306 | md_number_to_chars (buf, newval, THUMB_SIZE); |
20307 | } | |
738755b0 MS |
20308 | else |
20309 | { | |
20310 | if (value & ~0x7e) | |
20311 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20312 | _("branch out of range")); | |
20313 | ||
20314 | if (fixP->fx_done || !seg->use_rela_p) | |
20315 | { | |
20316 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20317 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); | |
20318 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20319 | } | |
20320 | } | |
c19d1205 | 20321 | break; |
a737bd4d | 20322 | |
c19d1205 | 20323 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac ZW |
20324 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
20325 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20326 | _("branch out of range")); | |
a737bd4d | 20327 | |
2fc8bdac ZW |
20328 | if (fixP->fx_done || !seg->use_rela_p) |
20329 | { | |
20330 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20331 | newval |= (value & 0x1ff) >> 1; | |
20332 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20333 | } | |
c19d1205 | 20334 | break; |
a737bd4d | 20335 | |
c19d1205 | 20336 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac ZW |
20337 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
20338 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20339 | _("branch out of range")); | |
a737bd4d | 20340 | |
2fc8bdac ZW |
20341 | if (fixP->fx_done || !seg->use_rela_p) |
20342 | { | |
20343 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20344 | newval |= (value & 0xfff) >> 1; | |
20345 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20346 | } | |
c19d1205 | 20347 | break; |
a737bd4d | 20348 | |
c19d1205 | 20349 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
267bf995 RR |
20350 | if (fixP->fx_addsy |
20351 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20352 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20353 | && S_IS_DEFINED (fixP->fx_addsy) | |
20354 | && ARM_IS_FUNC (fixP->fx_addsy) | |
20355 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20356 | { | |
20357 | /* Force a relocation for a branch 20 bits wide. */ | |
20358 | fixP->fx_done = 0; | |
20359 | } | |
2fc8bdac ZW |
20360 | if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) |
20361 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20362 | _("conditional branch out of range")); | |
404ff6b5 | 20363 | |
2fc8bdac ZW |
20364 | if (fixP->fx_done || !seg->use_rela_p) |
20365 | { | |
20366 | offsetT newval2; | |
20367 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 20368 | |
2fc8bdac ZW |
20369 | S = (value & 0x00100000) >> 20; |
20370 | J2 = (value & 0x00080000) >> 19; | |
20371 | J1 = (value & 0x00040000) >> 18; | |
20372 | hi = (value & 0x0003f000) >> 12; | |
20373 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 20374 | |
2fc8bdac ZW |
20375 | newval = md_chars_to_number (buf, THUMB_SIZE); |
20376 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20377 | newval |= (S << 10) | hi; | |
20378 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
20379 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20380 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
20381 | } | |
c19d1205 | 20382 | break; |
6c43fab6 | 20383 | |
c19d1205 | 20384 | case BFD_RELOC_THUMB_PCREL_BLX: |
267bf995 RR |
20385 | |
20386 | /* If there is a blx from a thumb state function to | |
20387 | another thumb function flip this to a bl and warn | |
20388 | about it. */ | |
20389 | ||
20390 | if (fixP->fx_addsy | |
20391 | && S_IS_DEFINED (fixP->fx_addsy) | |
20392 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20393 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20394 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
20395 | { | |
20396 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
20397 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
20398 | _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), | |
20399 | name); | |
20400 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20401 | newval = newval | 0x1000; | |
20402 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
20403 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
20404 | fixP->fx_done = 1; | |
20405 | } | |
20406 | ||
20407 | ||
20408 | goto thumb_bl_common; | |
20409 | ||
c19d1205 | 20410 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
267bf995 RR |
20411 | |
20412 | /* A bl from Thumb state ISA to an internal ARM state function | |
20413 | is converted to a blx. */ | |
20414 | if (fixP->fx_addsy | |
20415 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20416 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20417 | && S_IS_DEFINED (fixP->fx_addsy) | |
20418 | && ARM_IS_FUNC (fixP->fx_addsy) | |
20419 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20420 | { | |
20421 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20422 | newval = newval & ~0x1000; | |
20423 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
20424 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; | |
20425 | fixP->fx_done = 1; | |
20426 | } | |
20427 | ||
20428 | thumb_bl_common: | |
20429 | ||
20430 | #ifdef OBJ_ELF | |
20431 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 && | |
20432 | fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
20433 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
20434 | #endif | |
20435 | ||
2fc8bdac ZW |
20436 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
20437 | /* For a BLX instruction, make sure that the relocation is rounded up | |
20438 | to a word boundary. This follows the semantics of the instruction | |
20439 | which specifies that bit 1 of the target address will come from bit | |
20440 | 1 of the base address. */ | |
20441 | value = (value + 1) & ~ 1; | |
404ff6b5 | 20442 | |
2fc8bdac | 20443 | |
4a42ebbc RR |
20444 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
20445 | { | |
20446 | if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))) | |
20447 | { | |
20448 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20449 | _("branch out of range")); | |
20450 | } | |
20451 | else if ((value & ~0x1ffffff) | |
20452 | && ((value & ~0x1ffffff) != ~0x1ffffff)) | |
20453 | { | |
20454 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20455 | _("Thumb2 branch out of range")); | |
20456 | } | |
c19d1205 | 20457 | } |
4a42ebbc RR |
20458 | |
20459 | if (fixP->fx_done || !seg->use_rela_p) | |
20460 | encode_thumb2_b_bl_offset (buf, value); | |
20461 | ||
c19d1205 | 20462 | break; |
404ff6b5 | 20463 | |
c19d1205 | 20464 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac ZW |
20465 | if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) |
20466 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20467 | _("branch out of range")); | |
6c43fab6 | 20468 | |
2fc8bdac | 20469 | if (fixP->fx_done || !seg->use_rela_p) |
4a42ebbc | 20470 | encode_thumb2_b_bl_offset (buf, value); |
6c43fab6 | 20471 | |
2fc8bdac | 20472 | break; |
a737bd4d | 20473 | |
2fc8bdac ZW |
20474 | case BFD_RELOC_8: |
20475 | if (fixP->fx_done || !seg->use_rela_p) | |
20476 | md_number_to_chars (buf, value, 1); | |
c19d1205 | 20477 | break; |
a737bd4d | 20478 | |
c19d1205 | 20479 | case BFD_RELOC_16: |
2fc8bdac | 20480 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 20481 | md_number_to_chars (buf, value, 2); |
c19d1205 | 20482 | break; |
a737bd4d | 20483 | |
c19d1205 ZW |
20484 | #ifdef OBJ_ELF |
20485 | case BFD_RELOC_ARM_TLS_GD32: | |
20486 | case BFD_RELOC_ARM_TLS_LE32: | |
20487 | case BFD_RELOC_ARM_TLS_IE32: | |
20488 | case BFD_RELOC_ARM_TLS_LDM32: | |
20489 | case BFD_RELOC_ARM_TLS_LDO32: | |
20490 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
20491 | /* fall through */ | |
6c43fab6 | 20492 | |
c19d1205 ZW |
20493 | case BFD_RELOC_ARM_GOT32: |
20494 | case BFD_RELOC_ARM_GOTOFF: | |
2fc8bdac ZW |
20495 | if (fixP->fx_done || !seg->use_rela_p) |
20496 | md_number_to_chars (buf, 0, 4); | |
c19d1205 | 20497 | break; |
b43420e6 NC |
20498 | |
20499 | case BFD_RELOC_ARM_GOT_PREL: | |
20500 | if (fixP->fx_done || !seg->use_rela_p) | |
20501 | md_number_to_chars (buf, value, 4); | |
20502 | break; | |
20503 | ||
9a6f4e97 NS |
20504 | case BFD_RELOC_ARM_TARGET2: |
20505 | /* TARGET2 is not partial-inplace, so we need to write the | |
20506 | addend here for REL targets, because it won't be written out | |
20507 | during reloc processing later. */ | |
20508 | if (fixP->fx_done || !seg->use_rela_p) | |
20509 | md_number_to_chars (buf, fixP->fx_offset, 4); | |
20510 | break; | |
c19d1205 | 20511 | #endif |
6c43fab6 | 20512 | |
c19d1205 ZW |
20513 | case BFD_RELOC_RVA: |
20514 | case BFD_RELOC_32: | |
20515 | case BFD_RELOC_ARM_TARGET1: | |
20516 | case BFD_RELOC_ARM_ROSEGREL32: | |
20517 | case BFD_RELOC_ARM_SBREL32: | |
20518 | case BFD_RELOC_32_PCREL: | |
f0927246 NC |
20519 | #ifdef TE_PE |
20520 | case BFD_RELOC_32_SECREL: | |
20521 | #endif | |
2fc8bdac | 20522 | if (fixP->fx_done || !seg->use_rela_p) |
53baae48 NC |
20523 | #ifdef TE_WINCE |
20524 | /* For WinCE we only do this for pcrel fixups. */ | |
20525 | if (fixP->fx_done || fixP->fx_pcrel) | |
20526 | #endif | |
20527 | md_number_to_chars (buf, value, 4); | |
c19d1205 | 20528 | break; |
6c43fab6 | 20529 | |
c19d1205 ZW |
20530 | #ifdef OBJ_ELF |
20531 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 20532 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
20533 | { |
20534 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
20535 | if ((value ^ (value >> 1)) & 0x40000000) | |
20536 | { | |
20537 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20538 | _("rel31 relocation overflow")); | |
20539 | } | |
20540 | newval |= value & 0x7fffffff; | |
20541 | md_number_to_chars (buf, newval, 4); | |
20542 | } | |
20543 | break; | |
c19d1205 | 20544 | #endif |
a737bd4d | 20545 | |
c19d1205 | 20546 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 20547 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
20548 | if (value < -1023 || value > 1023 || (value & 3)) |
20549 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20550 | _("co-processor offset out of range")); | |
20551 | cp_off_common: | |
20552 | sign = value >= 0; | |
20553 | if (value < 0) | |
20554 | value = -value; | |
8f06b2d8 PB |
20555 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
20556 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
20557 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20558 | else | |
20559 | newval = get_thumb32_insn (buf); | |
20560 | newval &= 0xff7fff00; | |
c19d1205 | 20561 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); |
8f06b2d8 PB |
20562 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
20563 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
20564 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20565 | else | |
20566 | put_thumb32_insn (buf, newval); | |
c19d1205 | 20567 | break; |
a737bd4d | 20568 | |
c19d1205 | 20569 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 20570 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
20571 | if (value < -255 || value > 255) |
20572 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20573 | _("co-processor offset out of range")); | |
df7849c5 | 20574 | value *= 4; |
c19d1205 | 20575 | goto cp_off_common; |
6c43fab6 | 20576 | |
c19d1205 ZW |
20577 | case BFD_RELOC_ARM_THUMB_OFFSET: |
20578 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20579 | /* Exactly what ranges, and where the offset is inserted depends | |
20580 | on the type of instruction, we can establish this from the | |
20581 | top 4 bits. */ | |
20582 | switch (newval >> 12) | |
20583 | { | |
20584 | case 4: /* PC load. */ | |
20585 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
20586 | forced to zero for these loads; md_pcrel_from has already | |
20587 | compensated for this. */ | |
20588 | if (value & 3) | |
20589 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20590 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
20591 | (((unsigned long) fixP->fx_frag->fr_address |
20592 | + (unsigned long) fixP->fx_where) & ~3) | |
20593 | + (unsigned long) value); | |
a737bd4d | 20594 | |
c19d1205 ZW |
20595 | if (value & ~0x3fc) |
20596 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20597 | _("invalid offset, value too big (0x%08lX)"), | |
20598 | (long) value); | |
a737bd4d | 20599 | |
c19d1205 ZW |
20600 | newval |= value >> 2; |
20601 | break; | |
a737bd4d | 20602 | |
c19d1205 ZW |
20603 | case 9: /* SP load/store. */ |
20604 | if (value & ~0x3fc) | |
20605 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20606 | _("invalid offset, value too big (0x%08lX)"), | |
20607 | (long) value); | |
20608 | newval |= value >> 2; | |
20609 | break; | |
6c43fab6 | 20610 | |
c19d1205 ZW |
20611 | case 6: /* Word load/store. */ |
20612 | if (value & ~0x7c) | |
20613 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20614 | _("invalid offset, value too big (0x%08lX)"), | |
20615 | (long) value); | |
20616 | newval |= value << 4; /* 6 - 2. */ | |
20617 | break; | |
a737bd4d | 20618 | |
c19d1205 ZW |
20619 | case 7: /* Byte load/store. */ |
20620 | if (value & ~0x1f) | |
20621 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20622 | _("invalid offset, value too big (0x%08lX)"), | |
20623 | (long) value); | |
20624 | newval |= value << 6; | |
20625 | break; | |
a737bd4d | 20626 | |
c19d1205 ZW |
20627 | case 8: /* Halfword load/store. */ |
20628 | if (value & ~0x3e) | |
20629 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20630 | _("invalid offset, value too big (0x%08lX)"), | |
20631 | (long) value); | |
20632 | newval |= value << 5; /* 6 - 1. */ | |
20633 | break; | |
a737bd4d | 20634 | |
c19d1205 ZW |
20635 | default: |
20636 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20637 | "Unable to process relocation for thumb opcode: %lx", | |
20638 | (unsigned long) newval); | |
20639 | break; | |
20640 | } | |
20641 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20642 | break; | |
a737bd4d | 20643 | |
c19d1205 ZW |
20644 | case BFD_RELOC_ARM_THUMB_ADD: |
20645 | /* This is a complicated relocation, since we use it for all of | |
20646 | the following immediate relocations: | |
a737bd4d | 20647 | |
c19d1205 ZW |
20648 | 3bit ADD/SUB |
20649 | 8bit ADD/SUB | |
20650 | 9bit ADD/SUB SP word-aligned | |
20651 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 20652 | |
c19d1205 ZW |
20653 | The type of instruction being processed is encoded in the |
20654 | instruction field: | |
a737bd4d | 20655 | |
c19d1205 ZW |
20656 | 0x8000 SUB |
20657 | 0x00F0 Rd | |
20658 | 0x000F Rs | |
20659 | */ | |
20660 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20661 | { | |
20662 | int rd = (newval >> 4) & 0xf; | |
20663 | int rs = newval & 0xf; | |
20664 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 20665 | |
c19d1205 ZW |
20666 | /* Check for HI regs, only very restricted cases allowed: |
20667 | Adjusting SP, and using PC or SP to get an address. */ | |
20668 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
20669 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
20670 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20671 | _("invalid Hi register with immediate")); | |
a737bd4d | 20672 | |
c19d1205 ZW |
20673 | /* If value is negative, choose the opposite instruction. */ |
20674 | if (value < 0) | |
20675 | { | |
20676 | value = -value; | |
20677 | subtract = !subtract; | |
20678 | if (value < 0) | |
20679 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20680 | _("immediate value out of range")); | |
20681 | } | |
a737bd4d | 20682 | |
c19d1205 ZW |
20683 | if (rd == REG_SP) |
20684 | { | |
20685 | if (value & ~0x1fc) | |
20686 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20687 | _("invalid immediate for stack address calculation")); | |
20688 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
20689 | newval |= value >> 2; | |
20690 | } | |
20691 | else if (rs == REG_PC || rs == REG_SP) | |
20692 | { | |
20693 | if (subtract || value & ~0x3fc) | |
20694 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20695 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
20696 | (unsigned long) value); | |
20697 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
20698 | newval |= rd << 8; | |
20699 | newval |= value >> 2; | |
20700 | } | |
20701 | else if (rs == rd) | |
20702 | { | |
20703 | if (value & ~0xff) | |
20704 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20705 | _("immediate value out of range")); | |
20706 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
20707 | newval |= (rd << 8) | value; | |
20708 | } | |
20709 | else | |
20710 | { | |
20711 | if (value & ~0x7) | |
20712 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20713 | _("immediate value out of range")); | |
20714 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
20715 | newval |= rd | (rs << 3) | (value << 6); | |
20716 | } | |
20717 | } | |
20718 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20719 | break; | |
a737bd4d | 20720 | |
c19d1205 ZW |
20721 | case BFD_RELOC_ARM_THUMB_IMM: |
20722 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20723 | if (value < 0 || value > 255) | |
20724 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4e6e072b | 20725 | _("invalid immediate: %ld is out of range"), |
c19d1205 ZW |
20726 | (long) value); |
20727 | newval |= value; | |
20728 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20729 | break; | |
a737bd4d | 20730 | |
c19d1205 ZW |
20731 | case BFD_RELOC_ARM_THUMB_SHIFT: |
20732 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
20733 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
20734 | temp = newval & 0xf800; | |
20735 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
20736 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20737 | _("invalid shift value: %ld"), (long) value); | |
20738 | /* Shifts of zero must be encoded as LSL. */ | |
20739 | if (value == 0) | |
20740 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
20741 | /* Shifts of 32 are encoded as zero. */ | |
20742 | else if (value == 32) | |
20743 | value = 0; | |
20744 | newval |= value << 6; | |
20745 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20746 | break; | |
a737bd4d | 20747 | |
c19d1205 ZW |
20748 | case BFD_RELOC_VTABLE_INHERIT: |
20749 | case BFD_RELOC_VTABLE_ENTRY: | |
20750 | fixP->fx_done = 0; | |
20751 | return; | |
6c43fab6 | 20752 | |
b6895b4f PB |
20753 | case BFD_RELOC_ARM_MOVW: |
20754 | case BFD_RELOC_ARM_MOVT: | |
20755 | case BFD_RELOC_ARM_THUMB_MOVW: | |
20756 | case BFD_RELOC_ARM_THUMB_MOVT: | |
20757 | if (fixP->fx_done || !seg->use_rela_p) | |
20758 | { | |
20759 | /* REL format relocations are limited to a 16-bit addend. */ | |
20760 | if (!fixP->fx_done) | |
20761 | { | |
39623e12 | 20762 | if (value < -0x8000 || value > 0x7fff) |
b6895b4f | 20763 | as_bad_where (fixP->fx_file, fixP->fx_line, |
ff5075ca | 20764 | _("offset out of range")); |
b6895b4f PB |
20765 | } |
20766 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
20767 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
20768 | { | |
20769 | value >>= 16; | |
20770 | } | |
20771 | ||
20772 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
20773 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
20774 | { | |
20775 | newval = get_thumb32_insn (buf); | |
20776 | newval &= 0xfbf08f00; | |
20777 | newval |= (value & 0xf000) << 4; | |
20778 | newval |= (value & 0x0800) << 15; | |
20779 | newval |= (value & 0x0700) << 4; | |
20780 | newval |= (value & 0x00ff); | |
20781 | put_thumb32_insn (buf, newval); | |
20782 | } | |
20783 | else | |
20784 | { | |
20785 | newval = md_chars_to_number (buf, 4); | |
20786 | newval &= 0xfff0f000; | |
20787 | newval |= value & 0x0fff; | |
20788 | newval |= (value & 0xf000) << 4; | |
20789 | md_number_to_chars (buf, newval, 4); | |
20790 | } | |
20791 | } | |
20792 | return; | |
20793 | ||
4962c51a MS |
20794 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
20795 | case BFD_RELOC_ARM_ALU_PC_G0: | |
20796 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
20797 | case BFD_RELOC_ARM_ALU_PC_G1: | |
20798 | case BFD_RELOC_ARM_ALU_PC_G2: | |
20799 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
20800 | case BFD_RELOC_ARM_ALU_SB_G0: | |
20801 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
20802 | case BFD_RELOC_ARM_ALU_SB_G1: | |
20803 | case BFD_RELOC_ARM_ALU_SB_G2: | |
9c2799c2 | 20804 | gas_assert (!fixP->fx_done); |
4962c51a MS |
20805 | if (!seg->use_rela_p) |
20806 | { | |
20807 | bfd_vma insn; | |
20808 | bfd_vma encoded_addend; | |
20809 | bfd_vma addend_abs = abs (value); | |
20810 | ||
20811 | /* Check that the absolute value of the addend can be | |
20812 | expressed as an 8-bit constant plus a rotation. */ | |
20813 | encoded_addend = encode_arm_immediate (addend_abs); | |
20814 | if (encoded_addend == (unsigned int) FAIL) | |
20815 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20816 | _("the offset 0x%08lX is not representable"), | |
495bde8e | 20817 | (unsigned long) addend_abs); |
4962c51a MS |
20818 | |
20819 | /* Extract the instruction. */ | |
20820 | insn = md_chars_to_number (buf, INSN_SIZE); | |
20821 | ||
20822 | /* If the addend is positive, use an ADD instruction. | |
20823 | Otherwise use a SUB. Take care not to destroy the S bit. */ | |
20824 | insn &= 0xff1fffff; | |
20825 | if (value < 0) | |
20826 | insn |= 1 << 22; | |
20827 | else | |
20828 | insn |= 1 << 23; | |
20829 | ||
20830 | /* Place the encoded addend into the first 12 bits of the | |
20831 | instruction. */ | |
20832 | insn &= 0xfffff000; | |
20833 | insn |= encoded_addend; | |
5f4273c7 NC |
20834 | |
20835 | /* Update the instruction. */ | |
4962c51a MS |
20836 | md_number_to_chars (buf, insn, INSN_SIZE); |
20837 | } | |
20838 | break; | |
20839 | ||
20840 | case BFD_RELOC_ARM_LDR_PC_G0: | |
20841 | case BFD_RELOC_ARM_LDR_PC_G1: | |
20842 | case BFD_RELOC_ARM_LDR_PC_G2: | |
20843 | case BFD_RELOC_ARM_LDR_SB_G0: | |
20844 | case BFD_RELOC_ARM_LDR_SB_G1: | |
20845 | case BFD_RELOC_ARM_LDR_SB_G2: | |
9c2799c2 | 20846 | gas_assert (!fixP->fx_done); |
4962c51a MS |
20847 | if (!seg->use_rela_p) |
20848 | { | |
20849 | bfd_vma insn; | |
20850 | bfd_vma addend_abs = abs (value); | |
20851 | ||
20852 | /* Check that the absolute value of the addend can be | |
20853 | encoded in 12 bits. */ | |
20854 | if (addend_abs >= 0x1000) | |
20855 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20856 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), | |
495bde8e | 20857 | (unsigned long) addend_abs); |
4962c51a MS |
20858 | |
20859 | /* Extract the instruction. */ | |
20860 | insn = md_chars_to_number (buf, INSN_SIZE); | |
20861 | ||
20862 | /* If the addend is negative, clear bit 23 of the instruction. | |
20863 | Otherwise set it. */ | |
20864 | if (value < 0) | |
20865 | insn &= ~(1 << 23); | |
20866 | else | |
20867 | insn |= 1 << 23; | |
20868 | ||
20869 | /* Place the absolute value of the addend into the first 12 bits | |
20870 | of the instruction. */ | |
20871 | insn &= 0xfffff000; | |
20872 | insn |= addend_abs; | |
5f4273c7 NC |
20873 | |
20874 | /* Update the instruction. */ | |
4962c51a MS |
20875 | md_number_to_chars (buf, insn, INSN_SIZE); |
20876 | } | |
20877 | break; | |
20878 | ||
20879 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
20880 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
20881 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
20882 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
20883 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
20884 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
9c2799c2 | 20885 | gas_assert (!fixP->fx_done); |
4962c51a MS |
20886 | if (!seg->use_rela_p) |
20887 | { | |
20888 | bfd_vma insn; | |
20889 | bfd_vma addend_abs = abs (value); | |
20890 | ||
20891 | /* Check that the absolute value of the addend can be | |
20892 | encoded in 8 bits. */ | |
20893 | if (addend_abs >= 0x100) | |
20894 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20895 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), | |
495bde8e | 20896 | (unsigned long) addend_abs); |
4962c51a MS |
20897 | |
20898 | /* Extract the instruction. */ | |
20899 | insn = md_chars_to_number (buf, INSN_SIZE); | |
20900 | ||
20901 | /* If the addend is negative, clear bit 23 of the instruction. | |
20902 | Otherwise set it. */ | |
20903 | if (value < 0) | |
20904 | insn &= ~(1 << 23); | |
20905 | else | |
20906 | insn |= 1 << 23; | |
20907 | ||
20908 | /* Place the first four bits of the absolute value of the addend | |
20909 | into the first 4 bits of the instruction, and the remaining | |
20910 | four into bits 8 .. 11. */ | |
20911 | insn &= 0xfffff0f0; | |
20912 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); | |
5f4273c7 NC |
20913 | |
20914 | /* Update the instruction. */ | |
4962c51a MS |
20915 | md_number_to_chars (buf, insn, INSN_SIZE); |
20916 | } | |
20917 | break; | |
20918 | ||
20919 | case BFD_RELOC_ARM_LDC_PC_G0: | |
20920 | case BFD_RELOC_ARM_LDC_PC_G1: | |
20921 | case BFD_RELOC_ARM_LDC_PC_G2: | |
20922 | case BFD_RELOC_ARM_LDC_SB_G0: | |
20923 | case BFD_RELOC_ARM_LDC_SB_G1: | |
20924 | case BFD_RELOC_ARM_LDC_SB_G2: | |
9c2799c2 | 20925 | gas_assert (!fixP->fx_done); |
4962c51a MS |
20926 | if (!seg->use_rela_p) |
20927 | { | |
20928 | bfd_vma insn; | |
20929 | bfd_vma addend_abs = abs (value); | |
20930 | ||
20931 | /* Check that the absolute value of the addend is a multiple of | |
20932 | four and, when divided by four, fits in 8 bits. */ | |
20933 | if (addend_abs & 0x3) | |
20934 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20935 | _("bad offset 0x%08lX (must be word-aligned)"), | |
495bde8e | 20936 | (unsigned long) addend_abs); |
4962c51a MS |
20937 | |
20938 | if ((addend_abs >> 2) > 0xff) | |
20939 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20940 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), | |
495bde8e | 20941 | (unsigned long) addend_abs); |
4962c51a MS |
20942 | |
20943 | /* Extract the instruction. */ | |
20944 | insn = md_chars_to_number (buf, INSN_SIZE); | |
20945 | ||
20946 | /* If the addend is negative, clear bit 23 of the instruction. | |
20947 | Otherwise set it. */ | |
20948 | if (value < 0) | |
20949 | insn &= ~(1 << 23); | |
20950 | else | |
20951 | insn |= 1 << 23; | |
20952 | ||
20953 | /* Place the addend (divided by four) into the first eight | |
20954 | bits of the instruction. */ | |
20955 | insn &= 0xfffffff0; | |
20956 | insn |= addend_abs >> 2; | |
5f4273c7 NC |
20957 | |
20958 | /* Update the instruction. */ | |
4962c51a MS |
20959 | md_number_to_chars (buf, insn, INSN_SIZE); |
20960 | } | |
20961 | break; | |
20962 | ||
845b51d6 PB |
20963 | case BFD_RELOC_ARM_V4BX: |
20964 | /* This will need to go in the object file. */ | |
20965 | fixP->fx_done = 0; | |
20966 | break; | |
20967 | ||
c19d1205 ZW |
20968 | case BFD_RELOC_UNUSED: |
20969 | default: | |
20970 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20971 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
20972 | } | |
6c43fab6 RE |
20973 | } |
20974 | ||
c19d1205 ZW |
20975 | /* Translate internal representation of relocation info to BFD target |
20976 | format. */ | |
a737bd4d | 20977 | |
c19d1205 | 20978 | arelent * |
00a97672 | 20979 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 20980 | { |
c19d1205 ZW |
20981 | arelent * reloc; |
20982 | bfd_reloc_code_real_type code; | |
a737bd4d | 20983 | |
21d799b5 | 20984 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
a737bd4d | 20985 | |
21d799b5 | 20986 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
c19d1205 ZW |
20987 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
20988 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 20989 | |
2fc8bdac | 20990 | if (fixp->fx_pcrel) |
00a97672 RS |
20991 | { |
20992 | if (section->use_rela_p) | |
20993 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
20994 | else | |
20995 | fixp->fx_offset = reloc->address; | |
20996 | } | |
c19d1205 | 20997 | reloc->addend = fixp->fx_offset; |
a737bd4d | 20998 | |
c19d1205 | 20999 | switch (fixp->fx_r_type) |
a737bd4d | 21000 | { |
c19d1205 ZW |
21001 | case BFD_RELOC_8: |
21002 | if (fixp->fx_pcrel) | |
21003 | { | |
21004 | code = BFD_RELOC_8_PCREL; | |
21005 | break; | |
21006 | } | |
a737bd4d | 21007 | |
c19d1205 ZW |
21008 | case BFD_RELOC_16: |
21009 | if (fixp->fx_pcrel) | |
21010 | { | |
21011 | code = BFD_RELOC_16_PCREL; | |
21012 | break; | |
21013 | } | |
6c43fab6 | 21014 | |
c19d1205 ZW |
21015 | case BFD_RELOC_32: |
21016 | if (fixp->fx_pcrel) | |
21017 | { | |
21018 | code = BFD_RELOC_32_PCREL; | |
21019 | break; | |
21020 | } | |
a737bd4d | 21021 | |
b6895b4f PB |
21022 | case BFD_RELOC_ARM_MOVW: |
21023 | if (fixp->fx_pcrel) | |
21024 | { | |
21025 | code = BFD_RELOC_ARM_MOVW_PCREL; | |
21026 | break; | |
21027 | } | |
21028 | ||
21029 | case BFD_RELOC_ARM_MOVT: | |
21030 | if (fixp->fx_pcrel) | |
21031 | { | |
21032 | code = BFD_RELOC_ARM_MOVT_PCREL; | |
21033 | break; | |
21034 | } | |
21035 | ||
21036 | case BFD_RELOC_ARM_THUMB_MOVW: | |
21037 | if (fixp->fx_pcrel) | |
21038 | { | |
21039 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; | |
21040 | break; | |
21041 | } | |
21042 | ||
21043 | case BFD_RELOC_ARM_THUMB_MOVT: | |
21044 | if (fixp->fx_pcrel) | |
21045 | { | |
21046 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; | |
21047 | break; | |
21048 | } | |
21049 | ||
c19d1205 ZW |
21050 | case BFD_RELOC_NONE: |
21051 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
21052 | case BFD_RELOC_ARM_PCREL_BLX: | |
21053 | case BFD_RELOC_RVA: | |
21054 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
21055 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
21056 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
21057 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
21058 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
21059 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
c19d1205 ZW |
21060 | case BFD_RELOC_VTABLE_ENTRY: |
21061 | case BFD_RELOC_VTABLE_INHERIT: | |
f0927246 NC |
21062 | #ifdef TE_PE |
21063 | case BFD_RELOC_32_SECREL: | |
21064 | #endif | |
c19d1205 ZW |
21065 | code = fixp->fx_r_type; |
21066 | break; | |
a737bd4d | 21067 | |
00adf2d4 JB |
21068 | case BFD_RELOC_THUMB_PCREL_BLX: |
21069 | #ifdef OBJ_ELF | |
21070 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
21071 | code = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
21072 | else | |
21073 | #endif | |
21074 | code = BFD_RELOC_THUMB_PCREL_BLX; | |
21075 | break; | |
21076 | ||
c19d1205 ZW |
21077 | case BFD_RELOC_ARM_LITERAL: |
21078 | case BFD_RELOC_ARM_HWLITERAL: | |
21079 | /* If this is called then the a literal has | |
21080 | been referenced across a section boundary. */ | |
21081 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21082 | _("literal referenced across section boundary")); | |
21083 | return NULL; | |
a737bd4d | 21084 | |
c19d1205 ZW |
21085 | #ifdef OBJ_ELF |
21086 | case BFD_RELOC_ARM_GOT32: | |
21087 | case BFD_RELOC_ARM_GOTOFF: | |
b43420e6 | 21088 | case BFD_RELOC_ARM_GOT_PREL: |
c19d1205 ZW |
21089 | case BFD_RELOC_ARM_PLT32: |
21090 | case BFD_RELOC_ARM_TARGET1: | |
21091 | case BFD_RELOC_ARM_ROSEGREL32: | |
21092 | case BFD_RELOC_ARM_SBREL32: | |
21093 | case BFD_RELOC_ARM_PREL31: | |
21094 | case BFD_RELOC_ARM_TARGET2: | |
21095 | case BFD_RELOC_ARM_TLS_LE32: | |
21096 | case BFD_RELOC_ARM_TLS_LDO32: | |
39b41c9c PB |
21097 | case BFD_RELOC_ARM_PCREL_CALL: |
21098 | case BFD_RELOC_ARM_PCREL_JUMP: | |
4962c51a MS |
21099 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
21100 | case BFD_RELOC_ARM_ALU_PC_G0: | |
21101 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
21102 | case BFD_RELOC_ARM_ALU_PC_G1: | |
21103 | case BFD_RELOC_ARM_ALU_PC_G2: | |
21104 | case BFD_RELOC_ARM_LDR_PC_G0: | |
21105 | case BFD_RELOC_ARM_LDR_PC_G1: | |
21106 | case BFD_RELOC_ARM_LDR_PC_G2: | |
21107 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
21108 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
21109 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
21110 | case BFD_RELOC_ARM_LDC_PC_G0: | |
21111 | case BFD_RELOC_ARM_LDC_PC_G1: | |
21112 | case BFD_RELOC_ARM_LDC_PC_G2: | |
21113 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
21114 | case BFD_RELOC_ARM_ALU_SB_G0: | |
21115 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
21116 | case BFD_RELOC_ARM_ALU_SB_G1: | |
21117 | case BFD_RELOC_ARM_ALU_SB_G2: | |
21118 | case BFD_RELOC_ARM_LDR_SB_G0: | |
21119 | case BFD_RELOC_ARM_LDR_SB_G1: | |
21120 | case BFD_RELOC_ARM_LDR_SB_G2: | |
21121 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
21122 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
21123 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
21124 | case BFD_RELOC_ARM_LDC_SB_G0: | |
21125 | case BFD_RELOC_ARM_LDC_SB_G1: | |
21126 | case BFD_RELOC_ARM_LDC_SB_G2: | |
845b51d6 | 21127 | case BFD_RELOC_ARM_V4BX: |
c19d1205 ZW |
21128 | code = fixp->fx_r_type; |
21129 | break; | |
a737bd4d | 21130 | |
c19d1205 ZW |
21131 | case BFD_RELOC_ARM_TLS_GD32: |
21132 | case BFD_RELOC_ARM_TLS_IE32: | |
21133 | case BFD_RELOC_ARM_TLS_LDM32: | |
21134 | /* BFD will include the symbol's address in the addend. | |
21135 | But we don't want that, so subtract it out again here. */ | |
21136 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
21137 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
21138 | code = fixp->fx_r_type; | |
21139 | break; | |
21140 | #endif | |
a737bd4d | 21141 | |
c19d1205 ZW |
21142 | case BFD_RELOC_ARM_IMMEDIATE: |
21143 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21144 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
21145 | return NULL; | |
a737bd4d | 21146 | |
c19d1205 ZW |
21147 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
21148 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21149 | _("ADRL used for a symbol not defined in the same file")); | |
21150 | return NULL; | |
a737bd4d | 21151 | |
c19d1205 | 21152 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
21153 | if (section->use_rela_p) |
21154 | { | |
21155 | code = fixp->fx_r_type; | |
21156 | break; | |
21157 | } | |
21158 | ||
c19d1205 ZW |
21159 | if (fixp->fx_addsy != NULL |
21160 | && !S_IS_DEFINED (fixp->fx_addsy) | |
21161 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 21162 | { |
c19d1205 ZW |
21163 | as_bad_where (fixp->fx_file, fixp->fx_line, |
21164 | _("undefined local label `%s'"), | |
21165 | S_GET_NAME (fixp->fx_addsy)); | |
21166 | return NULL; | |
a737bd4d NC |
21167 | } |
21168 | ||
c19d1205 ZW |
21169 | as_bad_where (fixp->fx_file, fixp->fx_line, |
21170 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
21171 | return NULL; | |
a737bd4d | 21172 | |
c19d1205 ZW |
21173 | default: |
21174 | { | |
21175 | char * type; | |
6c43fab6 | 21176 | |
c19d1205 ZW |
21177 | switch (fixp->fx_r_type) |
21178 | { | |
21179 | case BFD_RELOC_NONE: type = "NONE"; break; | |
21180 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
21181 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 21182 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
21183 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
21184 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
21185 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
8f06b2d8 | 21186 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
21187 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
21188 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
21189 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
21190 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
21191 | default: type = _("<unknown>"); break; | |
21192 | } | |
21193 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21194 | _("cannot represent %s relocation in this object file format"), | |
21195 | type); | |
21196 | return NULL; | |
21197 | } | |
a737bd4d | 21198 | } |
6c43fab6 | 21199 | |
c19d1205 ZW |
21200 | #ifdef OBJ_ELF |
21201 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
21202 | && GOT_symbol | |
21203 | && fixp->fx_addsy == GOT_symbol) | |
21204 | { | |
21205 | code = BFD_RELOC_ARM_GOTPC; | |
21206 | reloc->addend = fixp->fx_offset = reloc->address; | |
21207 | } | |
21208 | #endif | |
6c43fab6 | 21209 | |
c19d1205 | 21210 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 21211 | |
c19d1205 ZW |
21212 | if (reloc->howto == NULL) |
21213 | { | |
21214 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21215 | _("cannot represent %s relocation in this object file format"), | |
21216 | bfd_get_reloc_code_name (code)); | |
21217 | return NULL; | |
21218 | } | |
6c43fab6 | 21219 | |
c19d1205 ZW |
21220 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
21221 | vtable entry to be used in the relocation's section offset. */ | |
21222 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
21223 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 21224 | |
c19d1205 | 21225 | return reloc; |
6c43fab6 RE |
21226 | } |
21227 | ||
c19d1205 | 21228 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 21229 | |
c19d1205 ZW |
21230 | void |
21231 | cons_fix_new_arm (fragS * frag, | |
21232 | int where, | |
21233 | int size, | |
21234 | expressionS * exp) | |
6c43fab6 | 21235 | { |
c19d1205 ZW |
21236 | bfd_reloc_code_real_type type; |
21237 | int pcrel = 0; | |
6c43fab6 | 21238 | |
c19d1205 ZW |
21239 | /* Pick a reloc. |
21240 | FIXME: @@ Should look at CPU word size. */ | |
21241 | switch (size) | |
21242 | { | |
21243 | case 1: | |
21244 | type = BFD_RELOC_8; | |
21245 | break; | |
21246 | case 2: | |
21247 | type = BFD_RELOC_16; | |
21248 | break; | |
21249 | case 4: | |
21250 | default: | |
21251 | type = BFD_RELOC_32; | |
21252 | break; | |
21253 | case 8: | |
21254 | type = BFD_RELOC_64; | |
21255 | break; | |
21256 | } | |
6c43fab6 | 21257 | |
f0927246 NC |
21258 | #ifdef TE_PE |
21259 | if (exp->X_op == O_secrel) | |
21260 | { | |
21261 | exp->X_op = O_symbol; | |
21262 | type = BFD_RELOC_32_SECREL; | |
21263 | } | |
21264 | #endif | |
21265 | ||
c19d1205 ZW |
21266 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); |
21267 | } | |
6c43fab6 | 21268 | |
4343666d | 21269 | #if defined (OBJ_COFF) |
c19d1205 ZW |
21270 | void |
21271 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 21272 | { |
c19d1205 ZW |
21273 | /* If the destination of the branch is a defined symbol which does not have |
21274 | the THUMB_FUNC attribute, then we must be calling a function which has | |
21275 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
21276 | function and change the branch to refer to that function instead. */ | |
21277 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
21278 | && fixP->fx_addsy != NULL | |
21279 | && S_IS_DEFINED (fixP->fx_addsy) | |
21280 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 21281 | { |
c19d1205 | 21282 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 21283 | } |
c19d1205 ZW |
21284 | } |
21285 | #endif | |
6c43fab6 | 21286 | |
267bf995 | 21287 | |
c19d1205 ZW |
21288 | int |
21289 | arm_force_relocation (struct fix * fixp) | |
21290 | { | |
21291 | #if defined (OBJ_COFF) && defined (TE_PE) | |
21292 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
21293 | return 1; | |
21294 | #endif | |
6c43fab6 | 21295 | |
267bf995 RR |
21296 | /* In case we have a call or a branch to a function in ARM ISA mode from |
21297 | a thumb function or vice-versa force the relocation. These relocations | |
21298 | are cleared off for some cores that might have blx and simple transformations | |
21299 | are possible. */ | |
21300 | ||
21301 | #ifdef OBJ_ELF | |
21302 | switch (fixp->fx_r_type) | |
21303 | { | |
21304 | case BFD_RELOC_ARM_PCREL_JUMP: | |
21305 | case BFD_RELOC_ARM_PCREL_CALL: | |
21306 | case BFD_RELOC_THUMB_PCREL_BLX: | |
21307 | if (THUMB_IS_FUNC (fixp->fx_addsy)) | |
21308 | return 1; | |
21309 | break; | |
21310 | ||
21311 | case BFD_RELOC_ARM_PCREL_BLX: | |
21312 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
21313 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
21314 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
21315 | if (ARM_IS_FUNC (fixp->fx_addsy)) | |
21316 | return 1; | |
21317 | break; | |
21318 | ||
21319 | default: | |
21320 | break; | |
21321 | } | |
21322 | #endif | |
21323 | ||
c19d1205 ZW |
21324 | /* Resolve these relocations even if the symbol is extern or weak. */ |
21325 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE | |
21326 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
0110f2b8 | 21327 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
16805f35 | 21328 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
0110f2b8 PB |
21329 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
21330 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
21331 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12) | |
c19d1205 | 21332 | return 0; |
a737bd4d | 21333 | |
4962c51a MS |
21334 | /* Always leave these relocations for the linker. */ |
21335 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
21336 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
21337 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
21338 | return 1; | |
21339 | ||
f0291e4c PB |
21340 | /* Always generate relocations against function symbols. */ |
21341 | if (fixp->fx_r_type == BFD_RELOC_32 | |
21342 | && fixp->fx_addsy | |
21343 | && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) | |
21344 | return 1; | |
21345 | ||
c19d1205 | 21346 | return generic_force_reloc (fixp); |
404ff6b5 AH |
21347 | } |
21348 | ||
0ffdc86c | 21349 | #if defined (OBJ_ELF) || defined (OBJ_COFF) |
e28387c3 PB |
21350 | /* Relocations against function names must be left unadjusted, |
21351 | so that the linker can use this information to generate interworking | |
21352 | stubs. The MIPS version of this function | |
c19d1205 ZW |
21353 | also prevents relocations that are mips-16 specific, but I do not |
21354 | know why it does this. | |
404ff6b5 | 21355 | |
c19d1205 ZW |
21356 | FIXME: |
21357 | There is one other problem that ought to be addressed here, but | |
21358 | which currently is not: Taking the address of a label (rather | |
21359 | than a function) and then later jumping to that address. Such | |
21360 | addresses also ought to have their bottom bit set (assuming that | |
21361 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 21362 | |
c19d1205 ZW |
21363 | bfd_boolean |
21364 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 21365 | { |
c19d1205 ZW |
21366 | if (fixP->fx_addsy == NULL) |
21367 | return 1; | |
404ff6b5 | 21368 | |
e28387c3 PB |
21369 | /* Preserve relocations against symbols with function type. */ |
21370 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) | |
c921be7d | 21371 | return FALSE; |
e28387c3 | 21372 | |
c19d1205 ZW |
21373 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
21374 | && fixP->fx_subsy == NULL) | |
c921be7d | 21375 | return FALSE; |
a737bd4d | 21376 | |
c19d1205 ZW |
21377 | /* We need the symbol name for the VTABLE entries. */ |
21378 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
21379 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c921be7d | 21380 | return FALSE; |
404ff6b5 | 21381 | |
c19d1205 ZW |
21382 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
21383 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
21384 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
21385 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
21386 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
21387 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
21388 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
21389 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
21390 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
21391 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) | |
c921be7d | 21392 | return FALSE; |
a737bd4d | 21393 | |
4962c51a MS |
21394 | /* Similarly for group relocations. */ |
21395 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
21396 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
21397 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
c921be7d | 21398 | return FALSE; |
4962c51a | 21399 | |
79947c54 CD |
21400 | /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ |
21401 | if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW | |
21402 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
21403 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL | |
21404 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL | |
21405 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
21406 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT | |
21407 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL | |
21408 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) | |
c921be7d | 21409 | return FALSE; |
79947c54 | 21410 | |
c921be7d | 21411 | return TRUE; |
a737bd4d | 21412 | } |
0ffdc86c NC |
21413 | #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ |
21414 | ||
21415 | #ifdef OBJ_ELF | |
404ff6b5 | 21416 | |
c19d1205 ZW |
21417 | const char * |
21418 | elf32_arm_target_format (void) | |
404ff6b5 | 21419 | { |
c19d1205 ZW |
21420 | #ifdef TE_SYMBIAN |
21421 | return (target_big_endian | |
21422 | ? "elf32-bigarm-symbian" | |
21423 | : "elf32-littlearm-symbian"); | |
21424 | #elif defined (TE_VXWORKS) | |
21425 | return (target_big_endian | |
21426 | ? "elf32-bigarm-vxworks" | |
21427 | : "elf32-littlearm-vxworks"); | |
21428 | #else | |
21429 | if (target_big_endian) | |
21430 | return "elf32-bigarm"; | |
21431 | else | |
21432 | return "elf32-littlearm"; | |
21433 | #endif | |
404ff6b5 AH |
21434 | } |
21435 | ||
c19d1205 ZW |
21436 | void |
21437 | armelf_frob_symbol (symbolS * symp, | |
21438 | int * puntp) | |
404ff6b5 | 21439 | { |
c19d1205 ZW |
21440 | elf_frob_symbol (symp, puntp); |
21441 | } | |
21442 | #endif | |
404ff6b5 | 21443 | |
c19d1205 | 21444 | /* MD interface: Finalization. */ |
a737bd4d | 21445 | |
c19d1205 ZW |
21446 | void |
21447 | arm_cleanup (void) | |
21448 | { | |
21449 | literal_pool * pool; | |
a737bd4d | 21450 | |
e07e6e58 NC |
21451 | /* Ensure that all the IT blocks are properly closed. */ |
21452 | check_it_blocks_finished (); | |
21453 | ||
c19d1205 ZW |
21454 | for (pool = list_of_pools; pool; pool = pool->next) |
21455 | { | |
5f4273c7 | 21456 | /* Put it at the end of the relevant section. */ |
c19d1205 ZW |
21457 | subseg_set (pool->section, pool->sub_section); |
21458 | #ifdef OBJ_ELF | |
21459 | arm_elf_change_section (); | |
21460 | #endif | |
21461 | s_ltorg (0); | |
21462 | } | |
404ff6b5 AH |
21463 | } |
21464 | ||
cd000bff DJ |
21465 | #ifdef OBJ_ELF |
21466 | /* Remove any excess mapping symbols generated for alignment frags in | |
21467 | SEC. We may have created a mapping symbol before a zero byte | |
21468 | alignment; remove it if there's a mapping symbol after the | |
21469 | alignment. */ | |
21470 | static void | |
21471 | check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, | |
21472 | void *dummy ATTRIBUTE_UNUSED) | |
21473 | { | |
21474 | segment_info_type *seginfo = seg_info (sec); | |
21475 | fragS *fragp; | |
21476 | ||
21477 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
21478 | return; | |
21479 | ||
21480 | for (fragp = seginfo->frchainP->frch_root; | |
21481 | fragp != NULL; | |
21482 | fragp = fragp->fr_next) | |
21483 | { | |
21484 | symbolS *sym = fragp->tc_frag_data.last_map; | |
21485 | fragS *next = fragp->fr_next; | |
21486 | ||
21487 | /* Variable-sized frags have been converted to fixed size by | |
21488 | this point. But if this was variable-sized to start with, | |
21489 | there will be a fixed-size frag after it. So don't handle | |
21490 | next == NULL. */ | |
21491 | if (sym == NULL || next == NULL) | |
21492 | continue; | |
21493 | ||
21494 | if (S_GET_VALUE (sym) < next->fr_address) | |
21495 | /* Not at the end of this frag. */ | |
21496 | continue; | |
21497 | know (S_GET_VALUE (sym) == next->fr_address); | |
21498 | ||
21499 | do | |
21500 | { | |
21501 | if (next->tc_frag_data.first_map != NULL) | |
21502 | { | |
21503 | /* Next frag starts with a mapping symbol. Discard this | |
21504 | one. */ | |
21505 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
21506 | break; | |
21507 | } | |
21508 | ||
21509 | if (next->fr_next == NULL) | |
21510 | { | |
21511 | /* This mapping symbol is at the end of the section. Discard | |
21512 | it. */ | |
21513 | know (next->fr_fix == 0 && next->fr_var == 0); | |
21514 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
21515 | break; | |
21516 | } | |
21517 | ||
21518 | /* As long as we have empty frags without any mapping symbols, | |
21519 | keep looking. */ | |
21520 | /* If the next frag is non-empty and does not start with a | |
21521 | mapping symbol, then this mapping symbol is required. */ | |
21522 | if (next->fr_address != next->fr_next->fr_address) | |
21523 | break; | |
21524 | ||
21525 | next = next->fr_next; | |
21526 | } | |
21527 | while (next != NULL); | |
21528 | } | |
21529 | } | |
21530 | #endif | |
21531 | ||
c19d1205 ZW |
21532 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
21533 | ARM ones. */ | |
404ff6b5 | 21534 | |
c19d1205 ZW |
21535 | void |
21536 | arm_adjust_symtab (void) | |
404ff6b5 | 21537 | { |
c19d1205 ZW |
21538 | #ifdef OBJ_COFF |
21539 | symbolS * sym; | |
404ff6b5 | 21540 | |
c19d1205 ZW |
21541 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
21542 | { | |
21543 | if (ARM_IS_THUMB (sym)) | |
21544 | { | |
21545 | if (THUMB_IS_FUNC (sym)) | |
21546 | { | |
21547 | /* Mark the symbol as a Thumb function. */ | |
21548 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
21549 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
21550 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 21551 | |
c19d1205 ZW |
21552 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
21553 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
21554 | else | |
21555 | as_bad (_("%s: unexpected function type: %d"), | |
21556 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
21557 | } | |
21558 | else switch (S_GET_STORAGE_CLASS (sym)) | |
21559 | { | |
21560 | case C_EXT: | |
21561 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
21562 | break; | |
21563 | case C_STAT: | |
21564 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
21565 | break; | |
21566 | case C_LABEL: | |
21567 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
21568 | break; | |
21569 | default: | |
21570 | /* Do nothing. */ | |
21571 | break; | |
21572 | } | |
21573 | } | |
a737bd4d | 21574 | |
c19d1205 ZW |
21575 | if (ARM_IS_INTERWORK (sym)) |
21576 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 21577 | } |
c19d1205 ZW |
21578 | #endif |
21579 | #ifdef OBJ_ELF | |
21580 | symbolS * sym; | |
21581 | char bind; | |
404ff6b5 | 21582 | |
c19d1205 | 21583 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 21584 | { |
c19d1205 ZW |
21585 | if (ARM_IS_THUMB (sym)) |
21586 | { | |
21587 | elf_symbol_type * elf_sym; | |
404ff6b5 | 21588 | |
c19d1205 ZW |
21589 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
21590 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 21591 | |
b0796911 PB |
21592 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
21593 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) | |
c19d1205 ZW |
21594 | { |
21595 | /* If it's a .thumb_func, declare it as so, | |
21596 | otherwise tag label as .code 16. */ | |
21597 | if (THUMB_IS_FUNC (sym)) | |
21598 | elf_sym->internal_elf_sym.st_info = | |
21599 | ELF_ST_INFO (bind, STT_ARM_TFUNC); | |
3ba67470 | 21600 | else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
c19d1205 ZW |
21601 | elf_sym->internal_elf_sym.st_info = |
21602 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
21603 | } | |
21604 | } | |
21605 | } | |
cd000bff DJ |
21606 | |
21607 | /* Remove any overlapping mapping symbols generated by alignment frags. */ | |
21608 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); | |
c19d1205 | 21609 | #endif |
404ff6b5 AH |
21610 | } |
21611 | ||
c19d1205 | 21612 | /* MD interface: Initialization. */ |
404ff6b5 | 21613 | |
a737bd4d | 21614 | static void |
c19d1205 | 21615 | set_constant_flonums (void) |
a737bd4d | 21616 | { |
c19d1205 | 21617 | int i; |
404ff6b5 | 21618 | |
c19d1205 ZW |
21619 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
21620 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
21621 | abort (); | |
a737bd4d | 21622 | } |
404ff6b5 | 21623 | |
3e9e4fcf JB |
21624 | /* Auto-select Thumb mode if it's the only available instruction set for the |
21625 | given architecture. */ | |
21626 | ||
21627 | static void | |
21628 | autoselect_thumb_from_cpu_variant (void) | |
21629 | { | |
21630 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) | |
21631 | opcode_select (16); | |
21632 | } | |
21633 | ||
c19d1205 ZW |
21634 | void |
21635 | md_begin (void) | |
a737bd4d | 21636 | { |
c19d1205 ZW |
21637 | unsigned mach; |
21638 | unsigned int i; | |
404ff6b5 | 21639 | |
c19d1205 ZW |
21640 | if ( (arm_ops_hsh = hash_new ()) == NULL |
21641 | || (arm_cond_hsh = hash_new ()) == NULL | |
21642 | || (arm_shift_hsh = hash_new ()) == NULL | |
21643 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 21644 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 21645 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
21646 | || (arm_reloc_hsh = hash_new ()) == NULL |
21647 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
21648 | as_fatal (_("virtual memory exhausted")); |
21649 | ||
21650 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
d3ce72d0 | 21651 | hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); |
c19d1205 | 21652 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) |
d3ce72d0 | 21653 | hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); |
c19d1205 | 21654 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) |
5a49b8ac | 21655 | hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); |
c19d1205 | 21656 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 21657 | hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); |
62b3e311 | 21658 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 NC |
21659 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, |
21660 | (void *) (v7m_psrs + i)); | |
c19d1205 | 21661 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
5a49b8ac | 21662 | hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); |
62b3e311 PB |
21663 | for (i = 0; |
21664 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
21665 | i++) | |
d3ce72d0 | 21666 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, |
5a49b8ac | 21667 | (void *) (barrier_opt_names + i)); |
c19d1205 ZW |
21668 | #ifdef OBJ_ELF |
21669 | for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) | |
5a49b8ac | 21670 | hash_insert (arm_reloc_hsh, reloc_names[i].name, (void *) (reloc_names + i)); |
c19d1205 ZW |
21671 | #endif |
21672 | ||
21673 | set_constant_flonums (); | |
404ff6b5 | 21674 | |
c19d1205 ZW |
21675 | /* Set the cpu variant based on the command-line options. We prefer |
21676 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
21677 | -mfpu= over any other way of setting the floating point unit. | |
21678 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 21679 | if (legacy_cpu) |
404ff6b5 | 21680 | { |
e74cfd16 | 21681 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
21682 | as_bad (_("use of old and new-style options to set CPU type")); |
21683 | ||
21684 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 21685 | } |
e74cfd16 | 21686 | else if (!mcpu_cpu_opt) |
c19d1205 | 21687 | mcpu_cpu_opt = march_cpu_opt; |
404ff6b5 | 21688 | |
e74cfd16 | 21689 | if (legacy_fpu) |
c19d1205 | 21690 | { |
e74cfd16 | 21691 | if (mfpu_opt) |
c19d1205 | 21692 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f RE |
21693 | |
21694 | mfpu_opt = legacy_fpu; | |
21695 | } | |
e74cfd16 | 21696 | else if (!mfpu_opt) |
03b1477f | 21697 | { |
45eb4c1b NS |
21698 | #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ |
21699 | || defined (TE_NetBSD) || defined (TE_VXWORKS)) | |
39c2da32 RE |
21700 | /* Some environments specify a default FPU. If they don't, infer it |
21701 | from the processor. */ | |
e74cfd16 | 21702 | if (mcpu_fpu_opt) |
03b1477f RE |
21703 | mfpu_opt = mcpu_fpu_opt; |
21704 | else | |
21705 | mfpu_opt = march_fpu_opt; | |
39c2da32 | 21706 | #else |
e74cfd16 | 21707 | mfpu_opt = &fpu_default; |
39c2da32 | 21708 | #endif |
03b1477f RE |
21709 | } |
21710 | ||
e74cfd16 | 21711 | if (!mfpu_opt) |
03b1477f | 21712 | { |
493cb6ef | 21713 | if (mcpu_cpu_opt != NULL) |
e74cfd16 | 21714 | mfpu_opt = &fpu_default; |
493cb6ef | 21715 | else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) |
e74cfd16 | 21716 | mfpu_opt = &fpu_arch_vfp_v2; |
03b1477f | 21717 | else |
e74cfd16 | 21718 | mfpu_opt = &fpu_arch_fpa; |
03b1477f RE |
21719 | } |
21720 | ||
ee065d83 | 21721 | #ifdef CPU_DEFAULT |
e74cfd16 | 21722 | if (!mcpu_cpu_opt) |
ee065d83 | 21723 | { |
e74cfd16 PB |
21724 | mcpu_cpu_opt = &cpu_default; |
21725 | selected_cpu = cpu_default; | |
ee065d83 | 21726 | } |
e74cfd16 PB |
21727 | #else |
21728 | if (mcpu_cpu_opt) | |
21729 | selected_cpu = *mcpu_cpu_opt; | |
ee065d83 | 21730 | else |
e74cfd16 | 21731 | mcpu_cpu_opt = &arm_arch_any; |
ee065d83 | 21732 | #endif |
03b1477f | 21733 | |
e74cfd16 | 21734 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
03b1477f | 21735 | |
3e9e4fcf JB |
21736 | autoselect_thumb_from_cpu_variant (); |
21737 | ||
e74cfd16 | 21738 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 21739 | |
f17c130b | 21740 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 21741 | { |
7cc69913 NC |
21742 | unsigned int flags = 0; |
21743 | ||
21744 | #if defined OBJ_ELF | |
21745 | flags = meabi_flags; | |
d507cf36 PB |
21746 | |
21747 | switch (meabi_flags) | |
33a392fb | 21748 | { |
d507cf36 | 21749 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 21750 | #endif |
d507cf36 PB |
21751 | /* Set the flags in the private structure. */ |
21752 | if (uses_apcs_26) flags |= F_APCS26; | |
21753 | if (support_interwork) flags |= F_INTERWORK; | |
21754 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 21755 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 21756 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
21757 | flags |= F_SOFT_FLOAT; |
21758 | ||
d507cf36 PB |
21759 | switch (mfloat_abi_opt) |
21760 | { | |
21761 | case ARM_FLOAT_ABI_SOFT: | |
21762 | case ARM_FLOAT_ABI_SOFTFP: | |
21763 | flags |= F_SOFT_FLOAT; | |
21764 | break; | |
33a392fb | 21765 | |
d507cf36 PB |
21766 | case ARM_FLOAT_ABI_HARD: |
21767 | if (flags & F_SOFT_FLOAT) | |
21768 | as_bad (_("hard-float conflicts with specified fpu")); | |
21769 | break; | |
21770 | } | |
03b1477f | 21771 | |
e74cfd16 PB |
21772 | /* Using pure-endian doubles (even if soft-float). */ |
21773 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 21774 | flags |= F_VFP_FLOAT; |
f17c130b | 21775 | |
fde78edd | 21776 | #if defined OBJ_ELF |
e74cfd16 | 21777 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 21778 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
21779 | break; |
21780 | ||
8cb51566 | 21781 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 21782 | case EF_ARM_EABI_VER5: |
c19d1205 | 21783 | /* No additional flags to set. */ |
d507cf36 PB |
21784 | break; |
21785 | ||
21786 | default: | |
21787 | abort (); | |
21788 | } | |
7cc69913 | 21789 | #endif |
b99bd4ef NC |
21790 | bfd_set_private_flags (stdoutput, flags); |
21791 | ||
21792 | /* We have run out flags in the COFF header to encode the | |
21793 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 21794 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
21795 | if (atpcs) |
21796 | { | |
21797 | asection * sec; | |
21798 | ||
21799 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
21800 | ||
21801 | if (sec != NULL) | |
21802 | { | |
21803 | bfd_set_section_flags | |
21804 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
21805 | bfd_set_section_size (stdoutput, sec, 0); | |
21806 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
21807 | } | |
21808 | } | |
7cc69913 | 21809 | } |
f17c130b | 21810 | #endif |
b99bd4ef NC |
21811 | |
21812 | /* Record the CPU type as well. */ | |
2d447fca JM |
21813 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) |
21814 | mach = bfd_mach_arm_iWMMXt2; | |
21815 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) | |
e16bb312 | 21816 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 21817 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 21818 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 21819 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 21820 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 21821 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 21822 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 21823 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 21824 | { |
e74cfd16 | 21825 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
21826 | mach = bfd_mach_arm_5T; |
21827 | else | |
21828 | mach = bfd_mach_arm_5; | |
21829 | } | |
e74cfd16 | 21830 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 21831 | { |
e74cfd16 | 21832 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
21833 | mach = bfd_mach_arm_4T; |
21834 | else | |
21835 | mach = bfd_mach_arm_4; | |
21836 | } | |
e74cfd16 | 21837 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 21838 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
21839 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
21840 | mach = bfd_mach_arm_3; | |
21841 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
21842 | mach = bfd_mach_arm_2a; | |
21843 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
21844 | mach = bfd_mach_arm_2; | |
21845 | else | |
21846 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
21847 | |
21848 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
21849 | } | |
21850 | ||
c19d1205 | 21851 | /* Command line processing. */ |
b99bd4ef | 21852 | |
c19d1205 ZW |
21853 | /* md_parse_option |
21854 | Invocation line includes a switch not recognized by the base assembler. | |
21855 | See if it's a processor-specific option. | |
b99bd4ef | 21856 | |
c19d1205 ZW |
21857 | This routine is somewhat complicated by the need for backwards |
21858 | compatibility (since older releases of gcc can't be changed). | |
21859 | The new options try to make the interface as compatible as | |
21860 | possible with GCC. | |
b99bd4ef | 21861 | |
c19d1205 | 21862 | New options (supported) are: |
b99bd4ef | 21863 | |
c19d1205 ZW |
21864 | -mcpu=<cpu name> Assemble for selected processor |
21865 | -march=<architecture name> Assemble for selected architecture | |
21866 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
21867 | -EB/-mbig-endian Big-endian | |
21868 | -EL/-mlittle-endian Little-endian | |
21869 | -k Generate PIC code | |
21870 | -mthumb Start in Thumb mode | |
21871 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 21872 | |
278df34e | 21873 | -m[no-]warn-deprecated Warn about deprecated features |
267bf995 | 21874 | |
c19d1205 | 21875 | For now we will also provide support for: |
b99bd4ef | 21876 | |
c19d1205 ZW |
21877 | -mapcs-32 32-bit Program counter |
21878 | -mapcs-26 26-bit Program counter | |
21879 | -macps-float Floats passed in FP registers | |
21880 | -mapcs-reentrant Reentrant code | |
21881 | -matpcs | |
21882 | (sometime these will probably be replaced with -mapcs=<list of options> | |
21883 | and -matpcs=<list of options>) | |
b99bd4ef | 21884 | |
c19d1205 ZW |
21885 | The remaining options are only supported for back-wards compatibility. |
21886 | Cpu variants, the arm part is optional: | |
21887 | -m[arm]1 Currently not supported. | |
21888 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
21889 | -m[arm]3 Arm 3 processor | |
21890 | -m[arm]6[xx], Arm 6 processors | |
21891 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
21892 | -m[arm]8[10] Arm 8 processors | |
21893 | -m[arm]9[20][tdmi] Arm 9 processors | |
21894 | -mstrongarm[110[0]] StrongARM processors | |
21895 | -mxscale XScale processors | |
21896 | -m[arm]v[2345[t[e]]] Arm architectures | |
21897 | -mall All (except the ARM1) | |
21898 | FP variants: | |
21899 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
21900 | -mfpe-old (No float load/store multiples) | |
21901 | -mvfpxd VFP Single precision | |
21902 | -mvfp All VFP | |
21903 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 21904 | |
c19d1205 ZW |
21905 | The following CPU names are recognized: |
21906 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
21907 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
21908 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
21909 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
21910 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
21911 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
21912 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 21913 | |
c19d1205 | 21914 | */ |
b99bd4ef | 21915 | |
c19d1205 | 21916 | const char * md_shortopts = "m:k"; |
b99bd4ef | 21917 | |
c19d1205 ZW |
21918 | #ifdef ARM_BI_ENDIAN |
21919 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
21920 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 21921 | #else |
c19d1205 ZW |
21922 | #if TARGET_BYTES_BIG_ENDIAN |
21923 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 21924 | #else |
c19d1205 ZW |
21925 | #define OPTION_EL (OPTION_MD_BASE + 1) |
21926 | #endif | |
b99bd4ef | 21927 | #endif |
845b51d6 | 21928 | #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) |
b99bd4ef | 21929 | |
c19d1205 | 21930 | struct option md_longopts[] = |
b99bd4ef | 21931 | { |
c19d1205 ZW |
21932 | #ifdef OPTION_EB |
21933 | {"EB", no_argument, NULL, OPTION_EB}, | |
21934 | #endif | |
21935 | #ifdef OPTION_EL | |
21936 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 21937 | #endif |
845b51d6 | 21938 | {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, |
c19d1205 ZW |
21939 | {NULL, no_argument, NULL, 0} |
21940 | }; | |
b99bd4ef | 21941 | |
c19d1205 | 21942 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 21943 | |
c19d1205 | 21944 | struct arm_option_table |
b99bd4ef | 21945 | { |
c19d1205 ZW |
21946 | char *option; /* Option name to match. */ |
21947 | char *help; /* Help information. */ | |
21948 | int *var; /* Variable to change. */ | |
21949 | int value; /* What to change it to. */ | |
21950 | char *deprecated; /* If non-null, print this message. */ | |
21951 | }; | |
b99bd4ef | 21952 | |
c19d1205 ZW |
21953 | struct arm_option_table arm_opts[] = |
21954 | { | |
21955 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
21956 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
21957 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
21958 | &support_interwork, 1, NULL}, | |
21959 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
21960 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
21961 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
21962 | 1, NULL}, | |
21963 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
21964 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
21965 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
21966 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
21967 | NULL}, | |
b99bd4ef | 21968 | |
c19d1205 ZW |
21969 | /* These are recognized by the assembler, but have no affect on code. */ |
21970 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
21971 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
278df34e NS |
21972 | |
21973 | {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, | |
21974 | {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), | |
21975 | &warn_on_deprecated, 0, NULL}, | |
e74cfd16 PB |
21976 | {NULL, NULL, NULL, 0, NULL} |
21977 | }; | |
21978 | ||
21979 | struct arm_legacy_option_table | |
21980 | { | |
21981 | char *option; /* Option name to match. */ | |
21982 | const arm_feature_set **var; /* Variable to change. */ | |
21983 | const arm_feature_set value; /* What to change it to. */ | |
21984 | char *deprecated; /* If non-null, print this message. */ | |
21985 | }; | |
b99bd4ef | 21986 | |
e74cfd16 PB |
21987 | const struct arm_legacy_option_table arm_legacy_opts[] = |
21988 | { | |
c19d1205 ZW |
21989 | /* DON'T add any new processors to this list -- we want the whole list |
21990 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
21991 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
21992 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
21993 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
21994 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
21995 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
21996 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
21997 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
21998 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
21999 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
22000 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
22001 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
22002 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
22003 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
22004 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
22005 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
22006 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
22007 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
22008 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
22009 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
22010 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
22011 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
22012 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
22013 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
22014 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
22015 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
22016 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
22017 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
22018 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
22019 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
22020 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
22021 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
22022 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
22023 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
22024 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
22025 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
22026 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
22027 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
22028 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
22029 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
22030 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
22031 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
22032 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
22033 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
22034 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
22035 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
22036 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
22037 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22038 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22039 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22040 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22041 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
22042 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
22043 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
22044 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
22045 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
22046 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
22047 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
22048 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
22049 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
22050 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
22051 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
22052 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
22053 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
22054 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
22055 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
22056 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
22057 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
22058 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
22059 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
22060 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 22061 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 22062 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 22063 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 22064 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 22065 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
22066 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
22067 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
22068 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 22069 | |
c19d1205 | 22070 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
22071 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
22072 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
22073 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
22074 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
22075 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
22076 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
22077 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
22078 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
22079 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
22080 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
22081 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
22082 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
22083 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
22084 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
22085 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
22086 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
22087 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
22088 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 22089 | |
c19d1205 | 22090 | /* Floating point variants -- don't add any more to this list either. */ |
e74cfd16 PB |
22091 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
22092 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
22093 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
22094 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 22095 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 22096 | |
e74cfd16 | 22097 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 22098 | }; |
7ed4c4c5 | 22099 | |
c19d1205 | 22100 | struct arm_cpu_option_table |
7ed4c4c5 | 22101 | { |
c19d1205 | 22102 | char *name; |
e74cfd16 | 22103 | const arm_feature_set value; |
c19d1205 ZW |
22104 | /* For some CPUs we assume an FPU unless the user explicitly sets |
22105 | -mfpu=... */ | |
e74cfd16 | 22106 | const arm_feature_set default_fpu; |
ee065d83 PB |
22107 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
22108 | case. */ | |
22109 | const char *canonical_name; | |
c19d1205 | 22110 | }; |
7ed4c4c5 | 22111 | |
c19d1205 ZW |
22112 | /* This list should, at a minimum, contain all the cpu names |
22113 | recognized by GCC. */ | |
e74cfd16 | 22114 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 22115 | { |
ee065d83 PB |
22116 | {"all", ARM_ANY, FPU_ARCH_FPA, NULL}, |
22117 | {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL}, | |
22118 | {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL}, | |
22119 | {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
22120 | {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
22121 | {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22122 | {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22123 | {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22124 | {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22125 | {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22126 | {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22127 | {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
22128 | {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22129 | {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
22130 | {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22131 | {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
22132 | {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22133 | {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22134 | {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22135 | {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22136 | {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22137 | {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22138 | {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22139 | {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22140 | {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22141 | {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22142 | {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22143 | {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22144 | {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22145 | {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22146 | {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22147 | {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22148 | {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22149 | {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22150 | {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22151 | {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22152 | {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22153 | {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22154 | {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22155 | {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"}, | |
22156 | {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22157 | {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22158 | {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22159 | {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
7fac0536 NC |
22160 | {"fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, |
22161 | {"fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
c19d1205 ZW |
22162 | /* For V5 or later processors we default to using VFP; but the user |
22163 | should really set the FPU type explicitly. */ | |
ee065d83 PB |
22164 | {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, |
22165 | {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22166 | {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
22167 | {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
22168 | {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
22169 | {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
22170 | {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"}, | |
22171 | {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22172 | {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
22173 | {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"}, | |
22174 | {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22175 | {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22176 | {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
22177 | {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
22178 | {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22179 | {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"}, | |
22180 | {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
22181 | {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22182 | {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22183 | {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"}, | |
22184 | {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
7fac0536 NC |
22185 | {"fa626te", ARM_ARCH_V5TE, FPU_NONE, NULL}, |
22186 | {"fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
ee065d83 PB |
22187 | {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"}, |
22188 | {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL}, | |
22189 | {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"}, | |
22190 | {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL}, | |
22191 | {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL}, | |
22192 | {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL}, | |
22193 | {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL}, | |
22194 | {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL}, | |
22195 | {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL}, | |
22196 | {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL}, | |
b38f9f31 | 22197 | {"cortex-a5", ARM_ARCH_V7A, FPU_NONE, NULL}, |
e07e6e58 | 22198 | {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE (0, FPU_VFP_V3 |
5287ad62 | 22199 | | FPU_NEON_EXT_V1), |
15290f0a | 22200 | NULL}, |
e07e6e58 | 22201 | {"cortex-a9", ARM_ARCH_V7A, ARM_FEATURE (0, FPU_VFP_V3 |
15290f0a | 22202 | | FPU_NEON_EXT_V1), |
5287ad62 | 22203 | NULL}, |
62b3e311 | 22204 | {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL}, |
307c948d | 22205 | {"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16, NULL}, |
26b6f191 | 22206 | {"cortex-m4", ARM_ARCH_V7EM, FPU_NONE, NULL}, |
62b3e311 | 22207 | {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL}, |
7e806470 | 22208 | {"cortex-m1", ARM_ARCH_V6M, FPU_NONE, NULL}, |
5b19eaba | 22209 | {"cortex-m0", ARM_ARCH_V6M, FPU_NONE, NULL}, |
c19d1205 | 22210 | /* ??? XSCALE is really an architecture. */ |
ee065d83 | 22211 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, |
c19d1205 | 22212 | /* ??? iwmmxt is not a processor. */ |
ee065d83 | 22213 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL}, |
2d447fca | 22214 | {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL}, |
ee065d83 | 22215 | {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, |
c19d1205 | 22216 | /* Maverick */ |
e07e6e58 | 22217 | {"ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"}, |
e74cfd16 | 22218 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL} |
c19d1205 | 22219 | }; |
7ed4c4c5 | 22220 | |
c19d1205 | 22221 | struct arm_arch_option_table |
7ed4c4c5 | 22222 | { |
c19d1205 | 22223 | char *name; |
e74cfd16 PB |
22224 | const arm_feature_set value; |
22225 | const arm_feature_set default_fpu; | |
c19d1205 | 22226 | }; |
7ed4c4c5 | 22227 | |
c19d1205 ZW |
22228 | /* This list should, at a minimum, contain all the architecture names |
22229 | recognized by GCC. */ | |
e74cfd16 | 22230 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 ZW |
22231 | { |
22232 | {"all", ARM_ANY, FPU_ARCH_FPA}, | |
22233 | {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, | |
22234 | {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, | |
22235 | {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
22236 | {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
22237 | {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
22238 | {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, | |
22239 | {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
22240 | {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, | |
22241 | {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
22242 | {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, | |
22243 | {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, | |
22244 | {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, | |
22245 | {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, | |
22246 | {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, | |
22247 | {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, | |
22248 | {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, | |
22249 | {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
22250 | {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
22251 | {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, | |
22252 | {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, | |
22253 | {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, | |
22254 | {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, | |
22255 | {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, | |
22256 | {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, | |
22257 | {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, | |
7e806470 | 22258 | {"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP}, |
62b3e311 | 22259 | {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP}, |
c450d570 PB |
22260 | /* The official spelling of the ARMv7 profile variants is the dashed form. |
22261 | Accept the non-dashed form for compatibility with old toolchains. */ | |
62b3e311 PB |
22262 | {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP}, |
22263 | {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP}, | |
22264 | {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP}, | |
c450d570 PB |
22265 | {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP}, |
22266 | {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP}, | |
22267 | {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP}, | |
9e3c6df6 | 22268 | {"armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP}, |
c19d1205 ZW |
22269 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, |
22270 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, | |
2d447fca | 22271 | {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP}, |
e74cfd16 | 22272 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} |
c19d1205 | 22273 | }; |
7ed4c4c5 | 22274 | |
c19d1205 | 22275 | /* ISA extensions in the co-processor space. */ |
e74cfd16 | 22276 | struct arm_option_cpu_value_table |
c19d1205 ZW |
22277 | { |
22278 | char *name; | |
e74cfd16 | 22279 | const arm_feature_set value; |
c19d1205 | 22280 | }; |
7ed4c4c5 | 22281 | |
e74cfd16 | 22282 | static const struct arm_option_cpu_value_table arm_extensions[] = |
c19d1205 | 22283 | { |
e74cfd16 PB |
22284 | {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)}, |
22285 | {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)}, | |
22286 | {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)}, | |
2d447fca | 22287 | {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2)}, |
e74cfd16 | 22288 | {NULL, ARM_ARCH_NONE} |
c19d1205 | 22289 | }; |
7ed4c4c5 | 22290 | |
c19d1205 ZW |
22291 | /* This list should, at a minimum, contain all the fpu names |
22292 | recognized by GCC. */ | |
e74cfd16 | 22293 | static const struct arm_option_cpu_value_table arm_fpus[] = |
c19d1205 ZW |
22294 | { |
22295 | {"softfpa", FPU_NONE}, | |
22296 | {"fpe", FPU_ARCH_FPE}, | |
22297 | {"fpe2", FPU_ARCH_FPE}, | |
22298 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
22299 | {"fpa", FPU_ARCH_FPA}, | |
22300 | {"fpa10", FPU_ARCH_FPA}, | |
22301 | {"fpa11", FPU_ARCH_FPA}, | |
22302 | {"arm7500fe", FPU_ARCH_FPA}, | |
22303 | {"softvfp", FPU_ARCH_VFP}, | |
22304 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
22305 | {"vfp", FPU_ARCH_VFP_V2}, | |
22306 | {"vfp9", FPU_ARCH_VFP_V2}, | |
b1cc4aeb | 22307 | {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */ |
c19d1205 ZW |
22308 | {"vfp10", FPU_ARCH_VFP_V2}, |
22309 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
22310 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
b1cc4aeb PB |
22311 | {"vfpv2", FPU_ARCH_VFP_V2}, |
22312 | {"vfpv3", FPU_ARCH_VFP_V3}, | |
62f3b8c8 | 22313 | {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16}, |
b1cc4aeb | 22314 | {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, |
62f3b8c8 PB |
22315 | {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16}, |
22316 | {"vfpv3xd", FPU_ARCH_VFP_V3xD}, | |
22317 | {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16}, | |
c19d1205 ZW |
22318 | {"arm1020t", FPU_ARCH_VFP_V1}, |
22319 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
22320 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
22321 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
22322 | {"maverick", FPU_ARCH_MAVERICK}, | |
5287ad62 | 22323 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
8e79c3df | 22324 | {"neon-fp16", FPU_ARCH_NEON_FP16}, |
62f3b8c8 PB |
22325 | {"vfpv4", FPU_ARCH_VFP_V4}, |
22326 | {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, | |
ada65aa3 | 22327 | {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, |
62f3b8c8 | 22328 | {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, |
e74cfd16 PB |
22329 | {NULL, ARM_ARCH_NONE} |
22330 | }; | |
22331 | ||
22332 | struct arm_option_value_table | |
22333 | { | |
22334 | char *name; | |
22335 | long value; | |
c19d1205 | 22336 | }; |
7ed4c4c5 | 22337 | |
e74cfd16 | 22338 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
22339 | { |
22340 | {"hard", ARM_FLOAT_ABI_HARD}, | |
22341 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
22342 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 22343 | {NULL, 0} |
c19d1205 | 22344 | }; |
7ed4c4c5 | 22345 | |
c19d1205 | 22346 | #ifdef OBJ_ELF |
3a4a14e9 | 22347 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 22348 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
22349 | { |
22350 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
22351 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 22352 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 22353 | {NULL, 0} |
c19d1205 ZW |
22354 | }; |
22355 | #endif | |
7ed4c4c5 | 22356 | |
c19d1205 ZW |
22357 | struct arm_long_option_table |
22358 | { | |
22359 | char * option; /* Substring to match. */ | |
22360 | char * help; /* Help information. */ | |
22361 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
22362 | char * deprecated; /* If non-null, print this message. */ | |
22363 | }; | |
7ed4c4c5 | 22364 | |
c921be7d | 22365 | static bfd_boolean |
e74cfd16 | 22366 | arm_parse_extension (char * str, const arm_feature_set **opt_p) |
7ed4c4c5 | 22367 | { |
21d799b5 NC |
22368 | arm_feature_set *ext_set = (arm_feature_set *) |
22369 | xmalloc (sizeof (arm_feature_set)); | |
e74cfd16 PB |
22370 | |
22371 | /* Copy the feature set, so that we can modify it. */ | |
22372 | *ext_set = **opt_p; | |
22373 | *opt_p = ext_set; | |
22374 | ||
c19d1205 | 22375 | while (str != NULL && *str != 0) |
7ed4c4c5 | 22376 | { |
e74cfd16 | 22377 | const struct arm_option_cpu_value_table * opt; |
c19d1205 ZW |
22378 | char * ext; |
22379 | int optlen; | |
7ed4c4c5 | 22380 | |
c19d1205 ZW |
22381 | if (*str != '+') |
22382 | { | |
22383 | as_bad (_("invalid architectural extension")); | |
c921be7d | 22384 | return FALSE; |
c19d1205 | 22385 | } |
7ed4c4c5 | 22386 | |
c19d1205 ZW |
22387 | str++; |
22388 | ext = strchr (str, '+'); | |
7ed4c4c5 | 22389 | |
c19d1205 ZW |
22390 | if (ext != NULL) |
22391 | optlen = ext - str; | |
22392 | else | |
22393 | optlen = strlen (str); | |
7ed4c4c5 | 22394 | |
c19d1205 ZW |
22395 | if (optlen == 0) |
22396 | { | |
22397 | as_bad (_("missing architectural extension")); | |
c921be7d | 22398 | return FALSE; |
c19d1205 | 22399 | } |
7ed4c4c5 | 22400 | |
c19d1205 ZW |
22401 | for (opt = arm_extensions; opt->name != NULL; opt++) |
22402 | if (strncmp (opt->name, str, optlen) == 0) | |
22403 | { | |
e74cfd16 | 22404 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); |
c19d1205 ZW |
22405 | break; |
22406 | } | |
7ed4c4c5 | 22407 | |
c19d1205 ZW |
22408 | if (opt->name == NULL) |
22409 | { | |
5f4273c7 | 22410 | as_bad (_("unknown architectural extension `%s'"), str); |
c921be7d | 22411 | return FALSE; |
c19d1205 | 22412 | } |
7ed4c4c5 | 22413 | |
c19d1205 ZW |
22414 | str = ext; |
22415 | }; | |
7ed4c4c5 | 22416 | |
c921be7d | 22417 | return TRUE; |
c19d1205 | 22418 | } |
7ed4c4c5 | 22419 | |
c921be7d | 22420 | static bfd_boolean |
c19d1205 | 22421 | arm_parse_cpu (char * str) |
7ed4c4c5 | 22422 | { |
e74cfd16 | 22423 | const struct arm_cpu_option_table * opt; |
c19d1205 ZW |
22424 | char * ext = strchr (str, '+'); |
22425 | int optlen; | |
7ed4c4c5 | 22426 | |
c19d1205 ZW |
22427 | if (ext != NULL) |
22428 | optlen = ext - str; | |
7ed4c4c5 | 22429 | else |
c19d1205 | 22430 | optlen = strlen (str); |
7ed4c4c5 | 22431 | |
c19d1205 | 22432 | if (optlen == 0) |
7ed4c4c5 | 22433 | { |
c19d1205 | 22434 | as_bad (_("missing cpu name `%s'"), str); |
c921be7d | 22435 | return FALSE; |
7ed4c4c5 NC |
22436 | } |
22437 | ||
c19d1205 ZW |
22438 | for (opt = arm_cpus; opt->name != NULL; opt++) |
22439 | if (strncmp (opt->name, str, optlen) == 0) | |
22440 | { | |
e74cfd16 PB |
22441 | mcpu_cpu_opt = &opt->value; |
22442 | mcpu_fpu_opt = &opt->default_fpu; | |
ee065d83 | 22443 | if (opt->canonical_name) |
5f4273c7 | 22444 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
22445 | else |
22446 | { | |
22447 | int i; | |
c921be7d | 22448 | |
ee065d83 PB |
22449 | for (i = 0; i < optlen; i++) |
22450 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
22451 | selected_cpu_name[i] = 0; | |
22452 | } | |
7ed4c4c5 | 22453 | |
c19d1205 ZW |
22454 | if (ext != NULL) |
22455 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 22456 | |
c921be7d | 22457 | return TRUE; |
c19d1205 | 22458 | } |
7ed4c4c5 | 22459 | |
c19d1205 | 22460 | as_bad (_("unknown cpu `%s'"), str); |
c921be7d | 22461 | return FALSE; |
7ed4c4c5 NC |
22462 | } |
22463 | ||
c921be7d | 22464 | static bfd_boolean |
c19d1205 | 22465 | arm_parse_arch (char * str) |
7ed4c4c5 | 22466 | { |
e74cfd16 | 22467 | const struct arm_arch_option_table *opt; |
c19d1205 ZW |
22468 | char *ext = strchr (str, '+'); |
22469 | int optlen; | |
7ed4c4c5 | 22470 | |
c19d1205 ZW |
22471 | if (ext != NULL) |
22472 | optlen = ext - str; | |
7ed4c4c5 | 22473 | else |
c19d1205 | 22474 | optlen = strlen (str); |
7ed4c4c5 | 22475 | |
c19d1205 | 22476 | if (optlen == 0) |
7ed4c4c5 | 22477 | { |
c19d1205 | 22478 | as_bad (_("missing architecture name `%s'"), str); |
c921be7d | 22479 | return FALSE; |
7ed4c4c5 NC |
22480 | } |
22481 | ||
c19d1205 ZW |
22482 | for (opt = arm_archs; opt->name != NULL; opt++) |
22483 | if (streq (opt->name, str)) | |
22484 | { | |
e74cfd16 PB |
22485 | march_cpu_opt = &opt->value; |
22486 | march_fpu_opt = &opt->default_fpu; | |
5f4273c7 | 22487 | strcpy (selected_cpu_name, opt->name); |
7ed4c4c5 | 22488 | |
c19d1205 ZW |
22489 | if (ext != NULL) |
22490 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 22491 | |
c921be7d | 22492 | return TRUE; |
c19d1205 ZW |
22493 | } |
22494 | ||
22495 | as_bad (_("unknown architecture `%s'\n"), str); | |
c921be7d | 22496 | return FALSE; |
7ed4c4c5 | 22497 | } |
eb043451 | 22498 | |
c921be7d | 22499 | static bfd_boolean |
c19d1205 ZW |
22500 | arm_parse_fpu (char * str) |
22501 | { | |
e74cfd16 | 22502 | const struct arm_option_cpu_value_table * opt; |
b99bd4ef | 22503 | |
c19d1205 ZW |
22504 | for (opt = arm_fpus; opt->name != NULL; opt++) |
22505 | if (streq (opt->name, str)) | |
22506 | { | |
e74cfd16 | 22507 | mfpu_opt = &opt->value; |
c921be7d | 22508 | return TRUE; |
c19d1205 | 22509 | } |
b99bd4ef | 22510 | |
c19d1205 | 22511 | as_bad (_("unknown floating point format `%s'\n"), str); |
c921be7d | 22512 | return FALSE; |
c19d1205 ZW |
22513 | } |
22514 | ||
c921be7d | 22515 | static bfd_boolean |
c19d1205 | 22516 | arm_parse_float_abi (char * str) |
b99bd4ef | 22517 | { |
e74cfd16 | 22518 | const struct arm_option_value_table * opt; |
b99bd4ef | 22519 | |
c19d1205 ZW |
22520 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
22521 | if (streq (opt->name, str)) | |
22522 | { | |
22523 | mfloat_abi_opt = opt->value; | |
c921be7d | 22524 | return TRUE; |
c19d1205 | 22525 | } |
cc8a6dd0 | 22526 | |
c19d1205 | 22527 | as_bad (_("unknown floating point abi `%s'\n"), str); |
c921be7d | 22528 | return FALSE; |
c19d1205 | 22529 | } |
b99bd4ef | 22530 | |
c19d1205 | 22531 | #ifdef OBJ_ELF |
c921be7d | 22532 | static bfd_boolean |
c19d1205 ZW |
22533 | arm_parse_eabi (char * str) |
22534 | { | |
e74cfd16 | 22535 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 22536 | |
c19d1205 ZW |
22537 | for (opt = arm_eabis; opt->name != NULL; opt++) |
22538 | if (streq (opt->name, str)) | |
22539 | { | |
22540 | meabi_flags = opt->value; | |
c921be7d | 22541 | return TRUE; |
c19d1205 ZW |
22542 | } |
22543 | as_bad (_("unknown EABI `%s'\n"), str); | |
c921be7d | 22544 | return FALSE; |
c19d1205 ZW |
22545 | } |
22546 | #endif | |
cc8a6dd0 | 22547 | |
c921be7d | 22548 | static bfd_boolean |
e07e6e58 NC |
22549 | arm_parse_it_mode (char * str) |
22550 | { | |
c921be7d | 22551 | bfd_boolean ret = TRUE; |
e07e6e58 NC |
22552 | |
22553 | if (streq ("arm", str)) | |
22554 | implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
22555 | else if (streq ("thumb", str)) | |
22556 | implicit_it_mode = IMPLICIT_IT_MODE_THUMB; | |
22557 | else if (streq ("always", str)) | |
22558 | implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; | |
22559 | else if (streq ("never", str)) | |
22560 | implicit_it_mode = IMPLICIT_IT_MODE_NEVER; | |
22561 | else | |
22562 | { | |
22563 | as_bad (_("unknown implicit IT mode `%s', should be "\ | |
22564 | "arm, thumb, always, or never."), str); | |
c921be7d | 22565 | ret = FALSE; |
e07e6e58 NC |
22566 | } |
22567 | ||
22568 | return ret; | |
22569 | } | |
22570 | ||
c19d1205 ZW |
22571 | struct arm_long_option_table arm_long_opts[] = |
22572 | { | |
22573 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
22574 | arm_parse_cpu, NULL}, | |
22575 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
22576 | arm_parse_arch, NULL}, | |
22577 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
22578 | arm_parse_fpu, NULL}, | |
22579 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
22580 | arm_parse_float_abi, NULL}, | |
22581 | #ifdef OBJ_ELF | |
7fac0536 | 22582 | {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), |
c19d1205 ZW |
22583 | arm_parse_eabi, NULL}, |
22584 | #endif | |
e07e6e58 NC |
22585 | {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), |
22586 | arm_parse_it_mode, NULL}, | |
c19d1205 ZW |
22587 | {NULL, NULL, 0, NULL} |
22588 | }; | |
cc8a6dd0 | 22589 | |
c19d1205 ZW |
22590 | int |
22591 | md_parse_option (int c, char * arg) | |
22592 | { | |
22593 | struct arm_option_table *opt; | |
e74cfd16 | 22594 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 22595 | struct arm_long_option_table *lopt; |
b99bd4ef | 22596 | |
c19d1205 | 22597 | switch (c) |
b99bd4ef | 22598 | { |
c19d1205 ZW |
22599 | #ifdef OPTION_EB |
22600 | case OPTION_EB: | |
22601 | target_big_endian = 1; | |
22602 | break; | |
22603 | #endif | |
cc8a6dd0 | 22604 | |
c19d1205 ZW |
22605 | #ifdef OPTION_EL |
22606 | case OPTION_EL: | |
22607 | target_big_endian = 0; | |
22608 | break; | |
22609 | #endif | |
b99bd4ef | 22610 | |
845b51d6 PB |
22611 | case OPTION_FIX_V4BX: |
22612 | fix_v4bx = TRUE; | |
22613 | break; | |
22614 | ||
c19d1205 ZW |
22615 | case 'a': |
22616 | /* Listing option. Just ignore these, we don't support additional | |
22617 | ones. */ | |
22618 | return 0; | |
b99bd4ef | 22619 | |
c19d1205 ZW |
22620 | default: |
22621 | for (opt = arm_opts; opt->option != NULL; opt++) | |
22622 | { | |
22623 | if (c == opt->option[0] | |
22624 | && ((arg == NULL && opt->option[1] == 0) | |
22625 | || streq (arg, opt->option + 1))) | |
22626 | { | |
c19d1205 | 22627 | /* If the option is deprecated, tell the user. */ |
278df34e | 22628 | if (warn_on_deprecated && opt->deprecated != NULL) |
c19d1205 ZW |
22629 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
22630 | arg ? arg : "", _(opt->deprecated)); | |
b99bd4ef | 22631 | |
c19d1205 ZW |
22632 | if (opt->var != NULL) |
22633 | *opt->var = opt->value; | |
cc8a6dd0 | 22634 | |
c19d1205 ZW |
22635 | return 1; |
22636 | } | |
22637 | } | |
b99bd4ef | 22638 | |
e74cfd16 PB |
22639 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
22640 | { | |
22641 | if (c == fopt->option[0] | |
22642 | && ((arg == NULL && fopt->option[1] == 0) | |
22643 | || streq (arg, fopt->option + 1))) | |
22644 | { | |
e74cfd16 | 22645 | /* If the option is deprecated, tell the user. */ |
278df34e | 22646 | if (warn_on_deprecated && fopt->deprecated != NULL) |
e74cfd16 PB |
22647 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
22648 | arg ? arg : "", _(fopt->deprecated)); | |
e74cfd16 PB |
22649 | |
22650 | if (fopt->var != NULL) | |
22651 | *fopt->var = &fopt->value; | |
22652 | ||
22653 | return 1; | |
22654 | } | |
22655 | } | |
22656 | ||
c19d1205 ZW |
22657 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
22658 | { | |
22659 | /* These options are expected to have an argument. */ | |
22660 | if (c == lopt->option[0] | |
22661 | && arg != NULL | |
22662 | && strncmp (arg, lopt->option + 1, | |
22663 | strlen (lopt->option + 1)) == 0) | |
22664 | { | |
c19d1205 | 22665 | /* If the option is deprecated, tell the user. */ |
278df34e | 22666 | if (warn_on_deprecated && lopt->deprecated != NULL) |
c19d1205 ZW |
22667 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, |
22668 | _(lopt->deprecated)); | |
b99bd4ef | 22669 | |
c19d1205 ZW |
22670 | /* Call the sup-option parser. */ |
22671 | return lopt->func (arg + strlen (lopt->option) - 1); | |
22672 | } | |
22673 | } | |
a737bd4d | 22674 | |
c19d1205 ZW |
22675 | return 0; |
22676 | } | |
a394c00f | 22677 | |
c19d1205 ZW |
22678 | return 1; |
22679 | } | |
a394c00f | 22680 | |
c19d1205 ZW |
22681 | void |
22682 | md_show_usage (FILE * fp) | |
a394c00f | 22683 | { |
c19d1205 ZW |
22684 | struct arm_option_table *opt; |
22685 | struct arm_long_option_table *lopt; | |
a394c00f | 22686 | |
c19d1205 | 22687 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 22688 | |
c19d1205 ZW |
22689 | for (opt = arm_opts; opt->option != NULL; opt++) |
22690 | if (opt->help != NULL) | |
22691 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 22692 | |
c19d1205 ZW |
22693 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
22694 | if (lopt->help != NULL) | |
22695 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 22696 | |
c19d1205 ZW |
22697 | #ifdef OPTION_EB |
22698 | fprintf (fp, _("\ | |
22699 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
22700 | #endif |
22701 | ||
c19d1205 ZW |
22702 | #ifdef OPTION_EL |
22703 | fprintf (fp, _("\ | |
22704 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 22705 | #endif |
845b51d6 PB |
22706 | |
22707 | fprintf (fp, _("\ | |
22708 | --fix-v4bx Allow BX in ARMv4 code\n")); | |
c19d1205 | 22709 | } |
ee065d83 PB |
22710 | |
22711 | ||
22712 | #ifdef OBJ_ELF | |
62b3e311 PB |
22713 | typedef struct |
22714 | { | |
22715 | int val; | |
22716 | arm_feature_set flags; | |
22717 | } cpu_arch_ver_table; | |
22718 | ||
22719 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted | |
22720 | least features first. */ | |
22721 | static const cpu_arch_ver_table cpu_arch_ver[] = | |
22722 | { | |
22723 | {1, ARM_ARCH_V4}, | |
22724 | {2, ARM_ARCH_V4T}, | |
22725 | {3, ARM_ARCH_V5}, | |
ee3c0378 | 22726 | {3, ARM_ARCH_V5T}, |
62b3e311 PB |
22727 | {4, ARM_ARCH_V5TE}, |
22728 | {5, ARM_ARCH_V5TEJ}, | |
22729 | {6, ARM_ARCH_V6}, | |
22730 | {7, ARM_ARCH_V6Z}, | |
7e806470 | 22731 | {9, ARM_ARCH_V6K}, |
91e22acd | 22732 | {11, ARM_ARCH_V6M}, |
7e806470 | 22733 | {8, ARM_ARCH_V6T2}, |
62b3e311 PB |
22734 | {10, ARM_ARCH_V7A}, |
22735 | {10, ARM_ARCH_V7R}, | |
22736 | {10, ARM_ARCH_V7M}, | |
22737 | {0, ARM_ARCH_NONE} | |
22738 | }; | |
22739 | ||
ee3c0378 AS |
22740 | /* Set an attribute if it has not already been set by the user. */ |
22741 | static void | |
22742 | aeabi_set_attribute_int (int tag, int value) | |
22743 | { | |
22744 | if (tag < 1 | |
22745 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
22746 | || !attributes_set_explicitly[tag]) | |
22747 | bfd_elf_add_proc_attr_int (stdoutput, tag, value); | |
22748 | } | |
22749 | ||
22750 | static void | |
22751 | aeabi_set_attribute_string (int tag, const char *value) | |
22752 | { | |
22753 | if (tag < 1 | |
22754 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
22755 | || !attributes_set_explicitly[tag]) | |
22756 | bfd_elf_add_proc_attr_string (stdoutput, tag, value); | |
22757 | } | |
22758 | ||
ee065d83 PB |
22759 | /* Set the public EABI object attributes. */ |
22760 | static void | |
22761 | aeabi_set_public_attributes (void) | |
22762 | { | |
22763 | int arch; | |
e74cfd16 | 22764 | arm_feature_set flags; |
62b3e311 PB |
22765 | arm_feature_set tmp; |
22766 | const cpu_arch_ver_table *p; | |
ee065d83 PB |
22767 | |
22768 | /* Choose the architecture based on the capabilities of the requested cpu | |
22769 | (if any) and/or the instructions actually used. */ | |
e74cfd16 PB |
22770 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); |
22771 | ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); | |
22772 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); | |
7a1d4c38 PB |
22773 | /*Allow the user to override the reported architecture. */ |
22774 | if (object_arch) | |
22775 | { | |
22776 | ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); | |
22777 | ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); | |
22778 | } | |
22779 | ||
62b3e311 PB |
22780 | tmp = flags; |
22781 | arch = 0; | |
22782 | for (p = cpu_arch_ver; p->val; p++) | |
22783 | { | |
22784 | if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) | |
22785 | { | |
22786 | arch = p->val; | |
22787 | ARM_CLEAR_FEATURE (tmp, tmp, p->flags); | |
22788 | } | |
22789 | } | |
ee065d83 | 22790 | |
9e3c6df6 PB |
22791 | /* The table lookup above finds the last architecture to contribute |
22792 | a new feature. Unfortunately, Tag13 is a subset of the union of | |
22793 | v6T2 and v7-M, so it is never seen as contributing a new feature. | |
22794 | We can not search for the last entry which is entirely used, | |
22795 | because if no CPU is specified we build up only those flags | |
22796 | actually used. Perhaps we should separate out the specified | |
22797 | and implicit cases. Avoid taking this path for -march=all by | |
22798 | checking for contradictory v7-A / v7-M features. */ | |
22799 | if (arch == 10 | |
22800 | && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a) | |
22801 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m) | |
22802 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp)) | |
22803 | arch = 13; | |
22804 | ||
ee065d83 PB |
22805 | /* Tag_CPU_name. */ |
22806 | if (selected_cpu_name[0]) | |
22807 | { | |
91d6fa6a | 22808 | char *q; |
ee065d83 | 22809 | |
91d6fa6a NC |
22810 | q = selected_cpu_name; |
22811 | if (strncmp (q, "armv", 4) == 0) | |
ee065d83 PB |
22812 | { |
22813 | int i; | |
5f4273c7 | 22814 | |
91d6fa6a NC |
22815 | q += 4; |
22816 | for (i = 0; q[i]; i++) | |
22817 | q[i] = TOUPPER (q[i]); | |
ee065d83 | 22818 | } |
91d6fa6a | 22819 | aeabi_set_attribute_string (Tag_CPU_name, q); |
ee065d83 | 22820 | } |
62f3b8c8 | 22821 | |
ee065d83 | 22822 | /* Tag_CPU_arch. */ |
ee3c0378 | 22823 | aeabi_set_attribute_int (Tag_CPU_arch, arch); |
62f3b8c8 | 22824 | |
62b3e311 PB |
22825 | /* Tag_CPU_arch_profile. */ |
22826 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) | |
ee3c0378 | 22827 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A'); |
62b3e311 | 22828 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) |
ee3c0378 | 22829 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R'); |
7e806470 | 22830 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m)) |
ee3c0378 | 22831 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M'); |
62f3b8c8 | 22832 | |
ee065d83 | 22833 | /* Tag_ARM_ISA_use. */ |
ee3c0378 AS |
22834 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) |
22835 | || arch == 0) | |
22836 | aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); | |
62f3b8c8 | 22837 | |
ee065d83 | 22838 | /* Tag_THUMB_ISA_use. */ |
ee3c0378 AS |
22839 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) |
22840 | || arch == 0) | |
22841 | aeabi_set_attribute_int (Tag_THUMB_ISA_use, | |
22842 | ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1); | |
62f3b8c8 | 22843 | |
ee065d83 | 22844 | /* Tag_VFP_arch. */ |
62f3b8c8 PB |
22845 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) |
22846 | aeabi_set_attribute_int (Tag_VFP_arch, | |
22847 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
22848 | ? 5 : 6); | |
22849 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) | |
ee3c0378 | 22850 | aeabi_set_attribute_int (Tag_VFP_arch, 3); |
ada65aa3 | 22851 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) |
ee3c0378 AS |
22852 | aeabi_set_attribute_int (Tag_VFP_arch, 4); |
22853 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) | |
22854 | aeabi_set_attribute_int (Tag_VFP_arch, 2); | |
22855 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) | |
22856 | || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) | |
22857 | aeabi_set_attribute_int (Tag_VFP_arch, 1); | |
62f3b8c8 | 22858 | |
4547cb56 NC |
22859 | /* Tag_ABI_HardFP_use. */ |
22860 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd) | |
22861 | && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)) | |
22862 | aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1); | |
22863 | ||
ee065d83 | 22864 | /* Tag_WMMX_arch. */ |
ee3c0378 AS |
22865 | if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) |
22866 | aeabi_set_attribute_int (Tag_WMMX_arch, 2); | |
22867 | else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) | |
22868 | aeabi_set_attribute_int (Tag_WMMX_arch, 1); | |
62f3b8c8 | 22869 | |
ee3c0378 | 22870 | /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ |
8e79c3df | 22871 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) |
62f3b8c8 PB |
22872 | aeabi_set_attribute_int |
22873 | (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma) | |
22874 | ? 2 : 1)); | |
22875 | ||
ee3c0378 | 22876 | /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ |
62f3b8c8 | 22877 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16)) |
ee3c0378 | 22878 | aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); |
4547cb56 NC |
22879 | |
22880 | /* Tag_DIV_use. */ | |
22881 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div)) | |
22882 | aeabi_set_attribute_int (Tag_DIV_use, 0); | |
22883 | /* Fill this in when gas supports v7a sdiv/udiv. | |
22884 | else if (... v7a with div extension used ...) | |
22885 | aeabi_set_attribute_int (Tag_DIV_use, 2); */ | |
22886 | else | |
22887 | aeabi_set_attribute_int (Tag_DIV_use, 1); | |
ee065d83 PB |
22888 | } |
22889 | ||
104d59d1 | 22890 | /* Add the default contents for the .ARM.attributes section. */ |
ee065d83 PB |
22891 | void |
22892 | arm_md_end (void) | |
22893 | { | |
ee065d83 PB |
22894 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
22895 | return; | |
22896 | ||
22897 | aeabi_set_public_attributes (); | |
ee065d83 | 22898 | } |
8463be01 | 22899 | #endif /* OBJ_ELF */ |
ee065d83 PB |
22900 | |
22901 | ||
22902 | /* Parse a .cpu directive. */ | |
22903 | ||
22904 | static void | |
22905 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
22906 | { | |
e74cfd16 | 22907 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
22908 | char *name; |
22909 | char saved_char; | |
22910 | ||
22911 | name = input_line_pointer; | |
5f4273c7 | 22912 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
22913 | input_line_pointer++; |
22914 | saved_char = *input_line_pointer; | |
22915 | *input_line_pointer = 0; | |
22916 | ||
22917 | /* Skip the first "all" entry. */ | |
22918 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
22919 | if (streq (opt->name, name)) | |
22920 | { | |
e74cfd16 PB |
22921 | mcpu_cpu_opt = &opt->value; |
22922 | selected_cpu = opt->value; | |
ee065d83 | 22923 | if (opt->canonical_name) |
5f4273c7 | 22924 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
22925 | else |
22926 | { | |
22927 | int i; | |
22928 | for (i = 0; opt->name[i]; i++) | |
22929 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
22930 | selected_cpu_name[i] = 0; | |
22931 | } | |
e74cfd16 | 22932 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
22933 | *input_line_pointer = saved_char; |
22934 | demand_empty_rest_of_line (); | |
22935 | return; | |
22936 | } | |
22937 | as_bad (_("unknown cpu `%s'"), name); | |
22938 | *input_line_pointer = saved_char; | |
22939 | ignore_rest_of_line (); | |
22940 | } | |
22941 | ||
22942 | ||
22943 | /* Parse a .arch directive. */ | |
22944 | ||
22945 | static void | |
22946 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
22947 | { | |
e74cfd16 | 22948 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
22949 | char saved_char; |
22950 | char *name; | |
22951 | ||
22952 | name = input_line_pointer; | |
5f4273c7 | 22953 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
22954 | input_line_pointer++; |
22955 | saved_char = *input_line_pointer; | |
22956 | *input_line_pointer = 0; | |
22957 | ||
22958 | /* Skip the first "all" entry. */ | |
22959 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
22960 | if (streq (opt->name, name)) | |
22961 | { | |
e74cfd16 PB |
22962 | mcpu_cpu_opt = &opt->value; |
22963 | selected_cpu = opt->value; | |
5f4273c7 | 22964 | strcpy (selected_cpu_name, opt->name); |
e74cfd16 | 22965 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
22966 | *input_line_pointer = saved_char; |
22967 | demand_empty_rest_of_line (); | |
22968 | return; | |
22969 | } | |
22970 | ||
22971 | as_bad (_("unknown architecture `%s'\n"), name); | |
22972 | *input_line_pointer = saved_char; | |
22973 | ignore_rest_of_line (); | |
22974 | } | |
22975 | ||
22976 | ||
7a1d4c38 PB |
22977 | /* Parse a .object_arch directive. */ |
22978 | ||
22979 | static void | |
22980 | s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) | |
22981 | { | |
22982 | const struct arm_arch_option_table *opt; | |
22983 | char saved_char; | |
22984 | char *name; | |
22985 | ||
22986 | name = input_line_pointer; | |
5f4273c7 | 22987 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
7a1d4c38 PB |
22988 | input_line_pointer++; |
22989 | saved_char = *input_line_pointer; | |
22990 | *input_line_pointer = 0; | |
22991 | ||
22992 | /* Skip the first "all" entry. */ | |
22993 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
22994 | if (streq (opt->name, name)) | |
22995 | { | |
22996 | object_arch = &opt->value; | |
22997 | *input_line_pointer = saved_char; | |
22998 | demand_empty_rest_of_line (); | |
22999 | return; | |
23000 | } | |
23001 | ||
23002 | as_bad (_("unknown architecture `%s'\n"), name); | |
23003 | *input_line_pointer = saved_char; | |
23004 | ignore_rest_of_line (); | |
23005 | } | |
23006 | ||
ee065d83 PB |
23007 | /* Parse a .fpu directive. */ |
23008 | ||
23009 | static void | |
23010 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
23011 | { | |
e74cfd16 | 23012 | const struct arm_option_cpu_value_table *opt; |
ee065d83 PB |
23013 | char saved_char; |
23014 | char *name; | |
23015 | ||
23016 | name = input_line_pointer; | |
5f4273c7 | 23017 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
23018 | input_line_pointer++; |
23019 | saved_char = *input_line_pointer; | |
23020 | *input_line_pointer = 0; | |
5f4273c7 | 23021 | |
ee065d83 PB |
23022 | for (opt = arm_fpus; opt->name != NULL; opt++) |
23023 | if (streq (opt->name, name)) | |
23024 | { | |
e74cfd16 PB |
23025 | mfpu_opt = &opt->value; |
23026 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
ee065d83 PB |
23027 | *input_line_pointer = saved_char; |
23028 | demand_empty_rest_of_line (); | |
23029 | return; | |
23030 | } | |
23031 | ||
23032 | as_bad (_("unknown floating point format `%s'\n"), name); | |
23033 | *input_line_pointer = saved_char; | |
23034 | ignore_rest_of_line (); | |
23035 | } | |
ee065d83 | 23036 | |
794ba86a | 23037 | /* Copy symbol information. */ |
f31fef98 | 23038 | |
794ba86a DJ |
23039 | void |
23040 | arm_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
23041 | { | |
23042 | ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); | |
23043 | } | |
e04befd0 | 23044 | |
f31fef98 | 23045 | #ifdef OBJ_ELF |
e04befd0 AS |
23046 | /* Given a symbolic attribute NAME, return the proper integer value. |
23047 | Returns -1 if the attribute is not known. */ | |
f31fef98 | 23048 | |
e04befd0 AS |
23049 | int |
23050 | arm_convert_symbolic_attribute (const char *name) | |
23051 | { | |
f31fef98 NC |
23052 | static const struct |
23053 | { | |
23054 | const char * name; | |
23055 | const int tag; | |
23056 | } | |
23057 | attribute_table[] = | |
23058 | { | |
23059 | /* When you modify this table you should | |
23060 | also modify the list in doc/c-arm.texi. */ | |
e04befd0 | 23061 | #define T(tag) {#tag, tag} |
f31fef98 NC |
23062 | T (Tag_CPU_raw_name), |
23063 | T (Tag_CPU_name), | |
23064 | T (Tag_CPU_arch), | |
23065 | T (Tag_CPU_arch_profile), | |
23066 | T (Tag_ARM_ISA_use), | |
23067 | T (Tag_THUMB_ISA_use), | |
75375b3e | 23068 | T (Tag_FP_arch), |
f31fef98 NC |
23069 | T (Tag_VFP_arch), |
23070 | T (Tag_WMMX_arch), | |
23071 | T (Tag_Advanced_SIMD_arch), | |
23072 | T (Tag_PCS_config), | |
23073 | T (Tag_ABI_PCS_R9_use), | |
23074 | T (Tag_ABI_PCS_RW_data), | |
23075 | T (Tag_ABI_PCS_RO_data), | |
23076 | T (Tag_ABI_PCS_GOT_use), | |
23077 | T (Tag_ABI_PCS_wchar_t), | |
23078 | T (Tag_ABI_FP_rounding), | |
23079 | T (Tag_ABI_FP_denormal), | |
23080 | T (Tag_ABI_FP_exceptions), | |
23081 | T (Tag_ABI_FP_user_exceptions), | |
23082 | T (Tag_ABI_FP_number_model), | |
75375b3e | 23083 | T (Tag_ABI_align_needed), |
f31fef98 | 23084 | T (Tag_ABI_align8_needed), |
75375b3e | 23085 | T (Tag_ABI_align_preserved), |
f31fef98 NC |
23086 | T (Tag_ABI_align8_preserved), |
23087 | T (Tag_ABI_enum_size), | |
23088 | T (Tag_ABI_HardFP_use), | |
23089 | T (Tag_ABI_VFP_args), | |
23090 | T (Tag_ABI_WMMX_args), | |
23091 | T (Tag_ABI_optimization_goals), | |
23092 | T (Tag_ABI_FP_optimization_goals), | |
23093 | T (Tag_compatibility), | |
23094 | T (Tag_CPU_unaligned_access), | |
75375b3e | 23095 | T (Tag_FP_HP_extension), |
f31fef98 NC |
23096 | T (Tag_VFP_HP_extension), |
23097 | T (Tag_ABI_FP_16bit_format), | |
cd21e546 MGD |
23098 | T (Tag_MPextension_use), |
23099 | T (Tag_DIV_use), | |
f31fef98 NC |
23100 | T (Tag_nodefaults), |
23101 | T (Tag_also_compatible_with), | |
23102 | T (Tag_conformance), | |
23103 | T (Tag_T2EE_use), | |
23104 | T (Tag_Virtualization_use), | |
cd21e546 | 23105 | /* We deliberately do not include Tag_MPextension_use_legacy. */ |
e04befd0 | 23106 | #undef T |
f31fef98 | 23107 | }; |
e04befd0 AS |
23108 | unsigned int i; |
23109 | ||
23110 | if (name == NULL) | |
23111 | return -1; | |
23112 | ||
f31fef98 | 23113 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
c921be7d | 23114 | if (streq (name, attribute_table[i].name)) |
e04befd0 AS |
23115 | return attribute_table[i].tag; |
23116 | ||
23117 | return -1; | |
23118 | } | |
267bf995 RR |
23119 | |
23120 | ||
23121 | /* Apply sym value for relocations only in the case that | |
23122 | they are for local symbols and you have the respective | |
23123 | architectural feature for blx and simple switches. */ | |
23124 | int | |
23125 | arm_apply_sym_value (struct fix * fixP) | |
23126 | { | |
23127 | if (fixP->fx_addsy | |
23128 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
23129 | && !S_IS_EXTERNAL (fixP->fx_addsy)) | |
23130 | { | |
23131 | switch (fixP->fx_r_type) | |
23132 | { | |
23133 | case BFD_RELOC_ARM_PCREL_BLX: | |
23134 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
23135 | if (ARM_IS_FUNC (fixP->fx_addsy)) | |
23136 | return 1; | |
23137 | break; | |
23138 | ||
23139 | case BFD_RELOC_ARM_PCREL_CALL: | |
23140 | case BFD_RELOC_THUMB_PCREL_BLX: | |
23141 | if (THUMB_IS_FUNC (fixP->fx_addsy)) | |
23142 | return 1; | |
23143 | break; | |
23144 | ||
23145 | default: | |
23146 | break; | |
23147 | } | |
23148 | ||
23149 | } | |
23150 | return 0; | |
23151 | } | |
f31fef98 | 23152 | #endif /* OBJ_ELF */ |