Commit | Line | Data |
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b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
4b95cf5c | 2 | Copyright (C) 1994-2014 Free Software Foundation, Inc. |
b99bd4ef NC |
3 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) |
4 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 5 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
6 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
7 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
8 | |
9 | This file is part of GAS, the GNU Assembler. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 13 | the Free Software Foundation; either version 3, or (at your option) |
b99bd4ef NC |
14 | any later version. |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
19 | GNU General Public License for more details. |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
b99bd4ef | 25 | |
42a68e18 | 26 | #include "as.h" |
5287ad62 | 27 | #include <limits.h> |
037e8744 | 28 | #include <stdarg.h> |
c19d1205 | 29 | #define NO_RELOC 0 |
3882b010 | 30 | #include "safe-ctype.h" |
b99bd4ef NC |
31 | #include "subsegs.h" |
32 | #include "obstack.h" | |
3da1d841 | 33 | #include "libiberty.h" |
f263249b RE |
34 | #include "opcode/arm.h" |
35 | ||
b99bd4ef NC |
36 | #ifdef OBJ_ELF |
37 | #include "elf/arm.h" | |
a394c00f | 38 | #include "dw2gencfi.h" |
b99bd4ef NC |
39 | #endif |
40 | ||
f0927246 NC |
41 | #include "dwarf2dbg.h" |
42 | ||
7ed4c4c5 NC |
43 | #ifdef OBJ_ELF |
44 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
45 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
46 | ||
47 | /* This structure holds the unwinding state. */ | |
48 | ||
49 | static struct | |
50 | { | |
c19d1205 ZW |
51 | symbolS * proc_start; |
52 | symbolS * table_entry; | |
53 | symbolS * personality_routine; | |
54 | int personality_index; | |
7ed4c4c5 | 55 | /* The segment containing the function. */ |
c19d1205 ZW |
56 | segT saved_seg; |
57 | subsegT saved_subseg; | |
7ed4c4c5 NC |
58 | /* Opcodes generated from this function. */ |
59 | unsigned char * opcodes; | |
c19d1205 ZW |
60 | int opcode_count; |
61 | int opcode_alloc; | |
7ed4c4c5 | 62 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 63 | offsetT frame_size; |
7ed4c4c5 NC |
64 | /* We don't add stack adjustment opcodes immediately so that we can merge |
65 | multiple adjustments. We can also omit the final adjustment | |
66 | when using a frame pointer. */ | |
c19d1205 | 67 | offsetT pending_offset; |
7ed4c4c5 | 68 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
69 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
70 | offsetT fp_offset; | |
71 | int fp_reg; | |
7ed4c4c5 | 72 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 73 | unsigned fp_used:1; |
7ed4c4c5 | 74 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 75 | unsigned sp_restored:1; |
7ed4c4c5 NC |
76 | } unwind; |
77 | ||
8b1ad454 NC |
78 | #endif /* OBJ_ELF */ |
79 | ||
4962c51a MS |
80 | /* Results from operand parsing worker functions. */ |
81 | ||
82 | typedef enum | |
83 | { | |
84 | PARSE_OPERAND_SUCCESS, | |
85 | PARSE_OPERAND_FAIL, | |
86 | PARSE_OPERAND_FAIL_NO_BACKTRACK | |
87 | } parse_operand_result; | |
88 | ||
33a392fb PB |
89 | enum arm_float_abi |
90 | { | |
91 | ARM_FLOAT_ABI_HARD, | |
92 | ARM_FLOAT_ABI_SOFTFP, | |
93 | ARM_FLOAT_ABI_SOFT | |
94 | }; | |
95 | ||
c19d1205 | 96 | /* Types of processor to assemble for. */ |
b99bd4ef | 97 | #ifndef CPU_DEFAULT |
8a59fff3 | 98 | /* The code that was here used to select a default CPU depending on compiler |
fa94de6b | 99 | pre-defines which were only present when doing native builds, thus |
8a59fff3 MGD |
100 | changing gas' default behaviour depending upon the build host. |
101 | ||
102 | If you have a target that requires a default CPU option then the you | |
103 | should define CPU_DEFAULT here. */ | |
b99bd4ef NC |
104 | #endif |
105 | ||
106 | #ifndef FPU_DEFAULT | |
c820d418 MM |
107 | # ifdef TE_LINUX |
108 | # define FPU_DEFAULT FPU_ARCH_FPA | |
109 | # elif defined (TE_NetBSD) | |
110 | # ifdef OBJ_ELF | |
111 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
112 | # else | |
113 | /* Legacy a.out format. */ | |
114 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
115 | # endif | |
4e7fd91e PB |
116 | # elif defined (TE_VXWORKS) |
117 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
118 | # else |
119 | /* For backwards compatibility, default to FPA. */ | |
120 | # define FPU_DEFAULT FPU_ARCH_FPA | |
121 | # endif | |
122 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 123 | |
c19d1205 | 124 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 125 | |
e74cfd16 PB |
126 | static arm_feature_set cpu_variant; |
127 | static arm_feature_set arm_arch_used; | |
128 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 129 | |
b99bd4ef | 130 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
131 | static int uses_apcs_26 = FALSE; |
132 | static int atpcs = FALSE; | |
b34976b6 AM |
133 | static int support_interwork = FALSE; |
134 | static int uses_apcs_float = FALSE; | |
c19d1205 | 135 | static int pic_code = FALSE; |
845b51d6 | 136 | static int fix_v4bx = FALSE; |
278df34e NS |
137 | /* Warn on using deprecated features. */ |
138 | static int warn_on_deprecated = TRUE; | |
139 | ||
2e6976a8 DG |
140 | /* Understand CodeComposer Studio assembly syntax. */ |
141 | bfd_boolean codecomposer_syntax = FALSE; | |
03b1477f RE |
142 | |
143 | /* Variables that we set while parsing command-line options. Once all | |
144 | options have been read we re-process these values to set the real | |
145 | assembly flags. */ | |
e74cfd16 PB |
146 | static const arm_feature_set *legacy_cpu = NULL; |
147 | static const arm_feature_set *legacy_fpu = NULL; | |
148 | ||
149 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
150 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
151 | static const arm_feature_set *march_cpu_opt = NULL; | |
152 | static const arm_feature_set *march_fpu_opt = NULL; | |
153 | static const arm_feature_set *mfpu_opt = NULL; | |
7a1d4c38 | 154 | static const arm_feature_set *object_arch = NULL; |
e74cfd16 PB |
155 | |
156 | /* Constants for known architecture features. */ | |
157 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
158 | static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; | |
159 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; | |
5287ad62 JB |
160 | static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; |
161 | static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; | |
e74cfd16 PB |
162 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
163 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
164 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; | |
165 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; | |
166 | ||
167 | #ifdef CPU_DEFAULT | |
168 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
169 | #endif | |
170 | ||
171 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); | |
172 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); | |
173 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); | |
174 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); | |
175 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); | |
176 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); | |
177 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); | |
178 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); | |
179 | static const arm_feature_set arm_ext_v4t_5 = | |
180 | ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); | |
181 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); | |
182 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); | |
183 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); | |
184 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); | |
185 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); | |
186 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); | |
e74cfd16 | 187 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); |
b2a5fbdc | 188 | static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0); |
62b3e311 | 189 | static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); |
9e3c6df6 | 190 | static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0); |
7e806470 PB |
191 | static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0); |
192 | static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0); | |
62b3e311 PB |
193 | static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); |
194 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); | |
195 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); | |
196 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); | |
9e3c6df6 | 197 | static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); |
bca38921 | 198 | static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0); |
7e806470 | 199 | static const arm_feature_set arm_ext_m = |
b2a5fbdc | 200 | ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0); |
60e5ef9f | 201 | static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0); |
f4c65163 | 202 | static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0); |
b2a5fbdc | 203 | static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0); |
eea54501 | 204 | static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0); |
90ec0d68 | 205 | static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0); |
e74cfd16 PB |
206 | |
207 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
208 | static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); | |
209 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; | |
210 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
251665fc | 211 | static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY; |
e74cfd16 | 212 | |
2d447fca JM |
213 | static const arm_feature_set arm_cext_iwmmxt2 = |
214 | ARM_FEATURE (0, ARM_CEXT_IWMMXT2); | |
e74cfd16 PB |
215 | static const arm_feature_set arm_cext_iwmmxt = |
216 | ARM_FEATURE (0, ARM_CEXT_IWMMXT); | |
217 | static const arm_feature_set arm_cext_xscale = | |
218 | ARM_FEATURE (0, ARM_CEXT_XSCALE); | |
219 | static const arm_feature_set arm_cext_maverick = | |
220 | ARM_FEATURE (0, ARM_CEXT_MAVERICK); | |
221 | static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); | |
222 | static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); | |
223 | static const arm_feature_set fpu_vfp_ext_v1xd = | |
224 | ARM_FEATURE (0, FPU_VFP_EXT_V1xD); | |
225 | static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); | |
226 | static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); | |
62f3b8c8 | 227 | static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD); |
5287ad62 | 228 | static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); |
b1cc4aeb PB |
229 | static const arm_feature_set fpu_vfp_ext_d32 = |
230 | ARM_FEATURE (0, FPU_VFP_EXT_D32); | |
5287ad62 JB |
231 | static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); |
232 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = | |
233 | ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); | |
62f3b8c8 PB |
234 | static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16); |
235 | static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA); | |
236 | static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA); | |
bca38921 MGD |
237 | static const arm_feature_set fpu_vfp_ext_armv8 = |
238 | ARM_FEATURE (0, FPU_VFP_EXT_ARMV8); | |
239 | static const arm_feature_set fpu_neon_ext_armv8 = | |
240 | ARM_FEATURE (0, FPU_NEON_EXT_ARMV8); | |
241 | static const arm_feature_set fpu_crypto_ext_armv8 = | |
242 | ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8); | |
dd5181d5 KT |
243 | static const arm_feature_set crc_ext_armv8 = |
244 | ARM_FEATURE (0, CRC_EXT_ARMV8); | |
e74cfd16 | 245 | |
33a392fb | 246 | static int mfloat_abi_opt = -1; |
e74cfd16 PB |
247 | /* Record user cpu selection for object attributes. */ |
248 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; | |
ee065d83 PB |
249 | /* Must be long enough to hold any of the names in arm_cpus. */ |
250 | static char selected_cpu_name[16]; | |
8d67f500 | 251 | |
aacf0b33 KT |
252 | extern FLONUM_TYPE generic_floating_point_number; |
253 | ||
8d67f500 NC |
254 | /* Return if no cpu was selected on command-line. */ |
255 | static bfd_boolean | |
256 | no_cpu_selected (void) | |
257 | { | |
258 | return selected_cpu.core == arm_arch_none.core | |
259 | && selected_cpu.coproc == arm_arch_none.coproc; | |
260 | } | |
261 | ||
7cc69913 | 262 | #ifdef OBJ_ELF |
deeaaff8 DJ |
263 | # ifdef EABI_DEFAULT |
264 | static int meabi_flags = EABI_DEFAULT; | |
265 | # else | |
d507cf36 | 266 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 267 | # endif |
e1da3f5b | 268 | |
ee3c0378 AS |
269 | static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; |
270 | ||
e1da3f5b | 271 | bfd_boolean |
5f4273c7 | 272 | arm_is_eabi (void) |
e1da3f5b PB |
273 | { |
274 | return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); | |
275 | } | |
7cc69913 | 276 | #endif |
b99bd4ef | 277 | |
b99bd4ef | 278 | #ifdef OBJ_ELF |
c19d1205 | 279 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
280 | symbolS * GOT_symbol; |
281 | #endif | |
282 | ||
b99bd4ef NC |
283 | /* 0: assemble for ARM, |
284 | 1: assemble for Thumb, | |
285 | 2: assemble for Thumb even though target CPU does not support thumb | |
286 | instructions. */ | |
287 | static int thumb_mode = 0; | |
8dc2430f NC |
288 | /* A value distinct from the possible values for thumb_mode that we |
289 | can use to record whether thumb_mode has been copied into the | |
290 | tc_frag_data field of a frag. */ | |
291 | #define MODE_RECORDED (1 << 4) | |
b99bd4ef | 292 | |
e07e6e58 NC |
293 | /* Specifies the intrinsic IT insn behavior mode. */ |
294 | enum implicit_it_mode | |
295 | { | |
296 | IMPLICIT_IT_MODE_NEVER = 0x00, | |
297 | IMPLICIT_IT_MODE_ARM = 0x01, | |
298 | IMPLICIT_IT_MODE_THUMB = 0x02, | |
299 | IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) | |
300 | }; | |
301 | static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
302 | ||
c19d1205 ZW |
303 | /* If unified_syntax is true, we are processing the new unified |
304 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
305 | ||
306 | - Immediate operands do not require a # prefix. | |
307 | - Conditional affixes always appear at the end of the | |
308 | instruction. (For backward compatibility, those instructions | |
309 | that formerly had them in the middle, continue to accept them | |
310 | there.) | |
311 | - The IT instruction may appear, and if it does is validated | |
312 | against subsequent conditional affixes. It does not generate | |
313 | machine code. | |
314 | ||
315 | Important differences from the old Thumb mode: | |
316 | ||
317 | - Immediate operands do not require a # prefix. | |
318 | - Most of the V6T2 instructions are only available in unified mode. | |
319 | - The .N and .W suffixes are recognized and honored (it is an error | |
320 | if they cannot be honored). | |
321 | - All instructions set the flags if and only if they have an 's' affix. | |
322 | - Conditional affixes may be used. They are validated against | |
323 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
324 | conditional affix except in the scope of an IT instruction. */ | |
325 | ||
326 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef | 327 | |
bacebabc RM |
328 | /* An immediate operand can start with #, and ld*, st*, pld operands |
329 | can contain [ and ]. We need to tell APP not to elide whitespace | |
477330fc RM |
330 | before a [, which can appear as the first operand for pld. |
331 | Likewise, a { can appear as the first operand for push, pop, vld*, etc. */ | |
332 | const char arm_symbol_chars[] = "#[]{}"; | |
bacebabc | 333 | |
5287ad62 JB |
334 | enum neon_el_type |
335 | { | |
dcbf9037 | 336 | NT_invtype, |
5287ad62 JB |
337 | NT_untyped, |
338 | NT_integer, | |
339 | NT_float, | |
340 | NT_poly, | |
341 | NT_signed, | |
dcbf9037 | 342 | NT_unsigned |
5287ad62 JB |
343 | }; |
344 | ||
345 | struct neon_type_el | |
346 | { | |
347 | enum neon_el_type type; | |
348 | unsigned size; | |
349 | }; | |
350 | ||
351 | #define NEON_MAX_TYPE_ELS 4 | |
352 | ||
353 | struct neon_type | |
354 | { | |
355 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; | |
356 | unsigned elems; | |
357 | }; | |
358 | ||
e07e6e58 NC |
359 | enum it_instruction_type |
360 | { | |
361 | OUTSIDE_IT_INSN, | |
362 | INSIDE_IT_INSN, | |
363 | INSIDE_IT_LAST_INSN, | |
364 | IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; | |
477330fc | 365 | if inside, should be the last one. */ |
e07e6e58 | 366 | NEUTRAL_IT_INSN, /* This could be either inside or outside, |
477330fc | 367 | i.e. BKPT and NOP. */ |
e07e6e58 NC |
368 | IT_INSN /* The IT insn has been parsed. */ |
369 | }; | |
370 | ||
ad6cec43 MGD |
371 | /* The maximum number of operands we need. */ |
372 | #define ARM_IT_MAX_OPERANDS 6 | |
373 | ||
b99bd4ef NC |
374 | struct arm_it |
375 | { | |
c19d1205 | 376 | const char * error; |
b99bd4ef | 377 | unsigned long instruction; |
c19d1205 ZW |
378 | int size; |
379 | int size_req; | |
380 | int cond; | |
037e8744 JB |
381 | /* "uncond_value" is set to the value in place of the conditional field in |
382 | unconditional versions of the instruction, or -1 if nothing is | |
383 | appropriate. */ | |
384 | int uncond_value; | |
5287ad62 | 385 | struct neon_type vectype; |
88714cb8 DG |
386 | /* This does not indicate an actual NEON instruction, only that |
387 | the mnemonic accepts neon-style type suffixes. */ | |
388 | int is_neon; | |
0110f2b8 PB |
389 | /* Set to the opcode if the instruction needs relaxation. |
390 | Zero if the instruction is not relaxed. */ | |
391 | unsigned long relax; | |
b99bd4ef NC |
392 | struct |
393 | { | |
394 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
395 | expressionS exp; |
396 | int pc_rel; | |
b99bd4ef | 397 | } reloc; |
b99bd4ef | 398 | |
e07e6e58 NC |
399 | enum it_instruction_type it_insn_type; |
400 | ||
c19d1205 ZW |
401 | struct |
402 | { | |
403 | unsigned reg; | |
ca3f61f7 | 404 | signed int imm; |
dcbf9037 | 405 | struct neon_type_el vectype; |
ca3f61f7 NC |
406 | unsigned present : 1; /* Operand present. */ |
407 | unsigned isreg : 1; /* Operand was a register. */ | |
408 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
5287ad62 JB |
409 | unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ |
410 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ | |
c96612cc | 411 | unsigned immisfloat : 1; /* Immediate was parsed as a float. */ |
5287ad62 JB |
412 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV |
413 | instructions. This allows us to disambiguate ARM <-> vector insns. */ | |
414 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ | |
037e8744 | 415 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
5287ad62 | 416 | unsigned isquad : 1; /* Operand is Neon quad-precision register. */ |
037e8744 | 417 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
ca3f61f7 NC |
418 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
419 | unsigned writeback : 1; /* Operand has trailing ! */ | |
420 | unsigned preind : 1; /* Preindexed address. */ | |
421 | unsigned postind : 1; /* Postindexed address. */ | |
422 | unsigned negative : 1; /* Index register was negated. */ | |
423 | unsigned shifted : 1; /* Shift applied to operation. */ | |
424 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
ad6cec43 | 425 | } operands[ARM_IT_MAX_OPERANDS]; |
b99bd4ef NC |
426 | }; |
427 | ||
c19d1205 | 428 | static struct arm_it inst; |
b99bd4ef NC |
429 | |
430 | #define NUM_FLOAT_VALS 8 | |
431 | ||
05d2d07e | 432 | const char * fp_const[] = |
b99bd4ef NC |
433 | { |
434 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
435 | }; | |
436 | ||
c19d1205 | 437 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
438 | #define MAX_LITTLENUMS 6 |
439 | ||
440 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
441 | ||
442 | #define FAIL (-1) | |
443 | #define SUCCESS (0) | |
444 | ||
445 | #define SUFF_S 1 | |
446 | #define SUFF_D 2 | |
447 | #define SUFF_E 3 | |
448 | #define SUFF_P 4 | |
449 | ||
c19d1205 ZW |
450 | #define CP_T_X 0x00008000 |
451 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 452 | |
c19d1205 ZW |
453 | #define CONDS_BIT 0x00100000 |
454 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
455 | |
456 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
457 | ||
458 | struct asm_cond | |
459 | { | |
d3ce72d0 | 460 | const char * template_name; |
c921be7d | 461 | unsigned long value; |
b99bd4ef NC |
462 | }; |
463 | ||
c19d1205 | 464 | #define COND_ALWAYS 0xE |
b99bd4ef | 465 | |
b99bd4ef NC |
466 | struct asm_psr |
467 | { | |
d3ce72d0 | 468 | const char * template_name; |
c921be7d | 469 | unsigned long field; |
b99bd4ef NC |
470 | }; |
471 | ||
62b3e311 PB |
472 | struct asm_barrier_opt |
473 | { | |
e797f7e0 MGD |
474 | const char * template_name; |
475 | unsigned long value; | |
476 | const arm_feature_set arch; | |
62b3e311 PB |
477 | }; |
478 | ||
2d2255b5 | 479 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
480 | #define SPSR_BIT (1 << 22) |
481 | ||
c19d1205 ZW |
482 | /* The individual PSR flag bits. */ |
483 | #define PSR_c (1 << 16) | |
484 | #define PSR_x (1 << 17) | |
485 | #define PSR_s (1 << 18) | |
486 | #define PSR_f (1 << 19) | |
b99bd4ef | 487 | |
c19d1205 | 488 | struct reloc_entry |
bfae80f2 | 489 | { |
c921be7d NC |
490 | char * name; |
491 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
492 | }; |
493 | ||
5287ad62 | 494 | enum vfp_reg_pos |
bfae80f2 | 495 | { |
5287ad62 JB |
496 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
497 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn | |
bfae80f2 RE |
498 | }; |
499 | ||
500 | enum vfp_ldstm_type | |
501 | { | |
502 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
503 | }; | |
504 | ||
dcbf9037 JB |
505 | /* Bits for DEFINED field in neon_typed_alias. */ |
506 | #define NTA_HASTYPE 1 | |
507 | #define NTA_HASINDEX 2 | |
508 | ||
509 | struct neon_typed_alias | |
510 | { | |
c921be7d NC |
511 | unsigned char defined; |
512 | unsigned char index; | |
513 | struct neon_type_el eltype; | |
dcbf9037 JB |
514 | }; |
515 | ||
c19d1205 ZW |
516 | /* ARM register categories. This includes coprocessor numbers and various |
517 | architecture extensions' registers. */ | |
518 | enum arm_reg_type | |
bfae80f2 | 519 | { |
c19d1205 ZW |
520 | REG_TYPE_RN, |
521 | REG_TYPE_CP, | |
522 | REG_TYPE_CN, | |
523 | REG_TYPE_FN, | |
524 | REG_TYPE_VFS, | |
525 | REG_TYPE_VFD, | |
5287ad62 | 526 | REG_TYPE_NQ, |
037e8744 | 527 | REG_TYPE_VFSD, |
5287ad62 | 528 | REG_TYPE_NDQ, |
037e8744 | 529 | REG_TYPE_NSDQ, |
c19d1205 ZW |
530 | REG_TYPE_VFC, |
531 | REG_TYPE_MVF, | |
532 | REG_TYPE_MVD, | |
533 | REG_TYPE_MVFX, | |
534 | REG_TYPE_MVDX, | |
535 | REG_TYPE_MVAX, | |
536 | REG_TYPE_DSPSC, | |
537 | REG_TYPE_MMXWR, | |
538 | REG_TYPE_MMXWC, | |
539 | REG_TYPE_MMXWCG, | |
540 | REG_TYPE_XSCALE, | |
90ec0d68 | 541 | REG_TYPE_RNB |
bfae80f2 RE |
542 | }; |
543 | ||
dcbf9037 JB |
544 | /* Structure for a hash table entry for a register. |
545 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra | |
546 | information which states whether a vector type or index is specified (for a | |
547 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ | |
6c43fab6 RE |
548 | struct reg_entry |
549 | { | |
c921be7d | 550 | const char * name; |
90ec0d68 | 551 | unsigned int number; |
c921be7d NC |
552 | unsigned char type; |
553 | unsigned char builtin; | |
554 | struct neon_typed_alias * neon; | |
6c43fab6 RE |
555 | }; |
556 | ||
c19d1205 | 557 | /* Diagnostics used when we don't get a register of the expected type. */ |
c921be7d | 558 | const char * const reg_expected_msgs[] = |
c19d1205 ZW |
559 | { |
560 | N_("ARM register expected"), | |
561 | N_("bad or missing co-processor number"), | |
562 | N_("co-processor register expected"), | |
563 | N_("FPA register expected"), | |
564 | N_("VFP single precision register expected"), | |
5287ad62 JB |
565 | N_("VFP/Neon double precision register expected"), |
566 | N_("Neon quad precision register expected"), | |
037e8744 | 567 | N_("VFP single or double precision register expected"), |
5287ad62 | 568 | N_("Neon double or quad precision register expected"), |
037e8744 | 569 | N_("VFP single, double or Neon quad precision register expected"), |
c19d1205 ZW |
570 | N_("VFP system register expected"), |
571 | N_("Maverick MVF register expected"), | |
572 | N_("Maverick MVD register expected"), | |
573 | N_("Maverick MVFX register expected"), | |
574 | N_("Maverick MVDX register expected"), | |
575 | N_("Maverick MVAX register expected"), | |
576 | N_("Maverick DSPSC register expected"), | |
577 | N_("iWMMXt data register expected"), | |
578 | N_("iWMMXt control register expected"), | |
579 | N_("iWMMXt scalar register expected"), | |
580 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
581 | }; |
582 | ||
c19d1205 | 583 | /* Some well known registers that we refer to directly elsewhere. */ |
bd340a04 | 584 | #define REG_R12 12 |
c19d1205 ZW |
585 | #define REG_SP 13 |
586 | #define REG_LR 14 | |
587 | #define REG_PC 15 | |
404ff6b5 | 588 | |
b99bd4ef NC |
589 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
590 | take 2: */ | |
c19d1205 | 591 | #define INSN_SIZE 4 |
b99bd4ef NC |
592 | |
593 | struct asm_opcode | |
594 | { | |
595 | /* Basic string to match. */ | |
d3ce72d0 | 596 | const char * template_name; |
c19d1205 ZW |
597 | |
598 | /* Parameters to instruction. */ | |
5be8be5d | 599 | unsigned int operands[8]; |
c19d1205 ZW |
600 | |
601 | /* Conditional tag - see opcode_lookup. */ | |
602 | unsigned int tag : 4; | |
b99bd4ef NC |
603 | |
604 | /* Basic instruction code. */ | |
c19d1205 | 605 | unsigned int avalue : 28; |
b99bd4ef | 606 | |
c19d1205 ZW |
607 | /* Thumb-format instruction code. */ |
608 | unsigned int tvalue; | |
b99bd4ef | 609 | |
90e4755a | 610 | /* Which architecture variant provides this instruction. */ |
c921be7d NC |
611 | const arm_feature_set * avariant; |
612 | const arm_feature_set * tvariant; | |
c19d1205 ZW |
613 | |
614 | /* Function to call to encode instruction in ARM format. */ | |
615 | void (* aencode) (void); | |
b99bd4ef | 616 | |
c19d1205 ZW |
617 | /* Function to call to encode instruction in Thumb format. */ |
618 | void (* tencode) (void); | |
b99bd4ef NC |
619 | }; |
620 | ||
a737bd4d NC |
621 | /* Defines for various bits that we will want to toggle. */ |
622 | #define INST_IMMEDIATE 0x02000000 | |
623 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 624 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
625 | #define SHIFT_BY_REG 0x00000010 |
626 | #define PRE_INDEX 0x01000000 | |
627 | #define INDEX_UP 0x00800000 | |
628 | #define WRITE_BACK 0x00200000 | |
629 | #define LDM_TYPE_2_OR_3 0x00400000 | |
a028a6f5 | 630 | #define CPSI_MMOD 0x00020000 |
90e4755a | 631 | |
a737bd4d NC |
632 | #define LITERAL_MASK 0xf000f000 |
633 | #define OPCODE_MASK 0xfe1fffff | |
634 | #define V4_STR_BIT 0x00000020 | |
8335d6aa | 635 | #define VLDR_VMOV_SAME 0x0040f000 |
90e4755a | 636 | |
efd81785 PB |
637 | #define T2_SUBS_PC_LR 0xf3de8f00 |
638 | ||
a737bd4d | 639 | #define DATA_OP_SHIFT 21 |
90e4755a | 640 | |
ef8d22e6 PB |
641 | #define T2_OPCODE_MASK 0xfe1fffff |
642 | #define T2_DATA_OP_SHIFT 21 | |
643 | ||
6530b175 NC |
644 | #define A_COND_MASK 0xf0000000 |
645 | #define A_PUSH_POP_OP_MASK 0x0fff0000 | |
646 | ||
647 | /* Opcodes for pushing/poping registers to/from the stack. */ | |
648 | #define A1_OPCODE_PUSH 0x092d0000 | |
649 | #define A2_OPCODE_PUSH 0x052d0004 | |
650 | #define A2_OPCODE_POP 0x049d0004 | |
651 | ||
a737bd4d NC |
652 | /* Codes to distinguish the arithmetic instructions. */ |
653 | #define OPCODE_AND 0 | |
654 | #define OPCODE_EOR 1 | |
655 | #define OPCODE_SUB 2 | |
656 | #define OPCODE_RSB 3 | |
657 | #define OPCODE_ADD 4 | |
658 | #define OPCODE_ADC 5 | |
659 | #define OPCODE_SBC 6 | |
660 | #define OPCODE_RSC 7 | |
661 | #define OPCODE_TST 8 | |
662 | #define OPCODE_TEQ 9 | |
663 | #define OPCODE_CMP 10 | |
664 | #define OPCODE_CMN 11 | |
665 | #define OPCODE_ORR 12 | |
666 | #define OPCODE_MOV 13 | |
667 | #define OPCODE_BIC 14 | |
668 | #define OPCODE_MVN 15 | |
90e4755a | 669 | |
ef8d22e6 PB |
670 | #define T2_OPCODE_AND 0 |
671 | #define T2_OPCODE_BIC 1 | |
672 | #define T2_OPCODE_ORR 2 | |
673 | #define T2_OPCODE_ORN 3 | |
674 | #define T2_OPCODE_EOR 4 | |
675 | #define T2_OPCODE_ADD 8 | |
676 | #define T2_OPCODE_ADC 10 | |
677 | #define T2_OPCODE_SBC 11 | |
678 | #define T2_OPCODE_SUB 13 | |
679 | #define T2_OPCODE_RSB 14 | |
680 | ||
a737bd4d NC |
681 | #define T_OPCODE_MUL 0x4340 |
682 | #define T_OPCODE_TST 0x4200 | |
683 | #define T_OPCODE_CMN 0x42c0 | |
684 | #define T_OPCODE_NEG 0x4240 | |
685 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 686 | |
a737bd4d NC |
687 | #define T_OPCODE_ADD_R3 0x1800 |
688 | #define T_OPCODE_SUB_R3 0x1a00 | |
689 | #define T_OPCODE_ADD_HI 0x4400 | |
690 | #define T_OPCODE_ADD_ST 0xb000 | |
691 | #define T_OPCODE_SUB_ST 0xb080 | |
692 | #define T_OPCODE_ADD_SP 0xa800 | |
693 | #define T_OPCODE_ADD_PC 0xa000 | |
694 | #define T_OPCODE_ADD_I8 0x3000 | |
695 | #define T_OPCODE_SUB_I8 0x3800 | |
696 | #define T_OPCODE_ADD_I3 0x1c00 | |
697 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 698 | |
a737bd4d NC |
699 | #define T_OPCODE_ASR_R 0x4100 |
700 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
701 | #define T_OPCODE_LSR_R 0x40c0 |
702 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
703 | #define T_OPCODE_ASR_I 0x1000 |
704 | #define T_OPCODE_LSL_I 0x0000 | |
705 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 706 | |
a737bd4d NC |
707 | #define T_OPCODE_MOV_I8 0x2000 |
708 | #define T_OPCODE_CMP_I8 0x2800 | |
709 | #define T_OPCODE_CMP_LR 0x4280 | |
710 | #define T_OPCODE_MOV_HR 0x4600 | |
711 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 712 | |
a737bd4d NC |
713 | #define T_OPCODE_LDR_PC 0x4800 |
714 | #define T_OPCODE_LDR_SP 0x9800 | |
715 | #define T_OPCODE_STR_SP 0x9000 | |
716 | #define T_OPCODE_LDR_IW 0x6800 | |
717 | #define T_OPCODE_STR_IW 0x6000 | |
718 | #define T_OPCODE_LDR_IH 0x8800 | |
719 | #define T_OPCODE_STR_IH 0x8000 | |
720 | #define T_OPCODE_LDR_IB 0x7800 | |
721 | #define T_OPCODE_STR_IB 0x7000 | |
722 | #define T_OPCODE_LDR_RW 0x5800 | |
723 | #define T_OPCODE_STR_RW 0x5000 | |
724 | #define T_OPCODE_LDR_RH 0x5a00 | |
725 | #define T_OPCODE_STR_RH 0x5200 | |
726 | #define T_OPCODE_LDR_RB 0x5c00 | |
727 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 728 | |
a737bd4d NC |
729 | #define T_OPCODE_PUSH 0xb400 |
730 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 731 | |
2fc8bdac | 732 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 733 | |
a737bd4d | 734 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 735 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 736 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 737 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 ZW |
738 | |
739 | #define BAD_ARGS _("bad arguments to instruction") | |
fdfde340 | 740 | #define BAD_SP _("r13 not allowed here") |
c19d1205 ZW |
741 | #define BAD_PC _("r15 not allowed here") |
742 | #define BAD_COND _("instruction cannot be conditional") | |
743 | #define BAD_OVERLAP _("registers may not be the same") | |
744 | #define BAD_HIREG _("lo register required") | |
745 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
01cfc07f | 746 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); |
dfa9f0d5 PB |
747 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
748 | #define BAD_NOT_IT _("instruction not allowed in IT block") | |
037e8744 | 749 | #define BAD_FPU _("selected FPU does not support instruction") |
e07e6e58 NC |
750 | #define BAD_OUT_IT _("thumb conditional instruction should be in IT block") |
751 | #define BAD_IT_COND _("incorrect condition in IT block") | |
752 | #define BAD_IT_IT _("IT falling in the range of a previous IT block") | |
921e5f0a | 753 | #define MISSING_FNSTART _("missing .fnstart before unwinding directive") |
5be8be5d DG |
754 | #define BAD_PC_ADDRESSING \ |
755 | _("cannot use register index with PC-relative addressing") | |
756 | #define BAD_PC_WRITEBACK \ | |
757 | _("cannot use writeback with PC-relative addressing") | |
08f10d51 | 758 | #define BAD_RANGE _("branch out of range") |
dd5181d5 | 759 | #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour") |
c19d1205 | 760 | |
c921be7d NC |
761 | static struct hash_control * arm_ops_hsh; |
762 | static struct hash_control * arm_cond_hsh; | |
763 | static struct hash_control * arm_shift_hsh; | |
764 | static struct hash_control * arm_psr_hsh; | |
765 | static struct hash_control * arm_v7m_psr_hsh; | |
766 | static struct hash_control * arm_reg_hsh; | |
767 | static struct hash_control * arm_reloc_hsh; | |
768 | static struct hash_control * arm_barrier_opt_hsh; | |
b99bd4ef | 769 | |
b99bd4ef NC |
770 | /* Stuff needed to resolve the label ambiguity |
771 | As: | |
772 | ... | |
773 | label: <insn> | |
774 | may differ from: | |
775 | ... | |
776 | label: | |
5f4273c7 | 777 | <insn> */ |
b99bd4ef NC |
778 | |
779 | symbolS * last_label_seen; | |
b34976b6 | 780 | static int label_is_thumb_function_name = FALSE; |
e07e6e58 | 781 | |
3d0c9500 NC |
782 | /* Literal pool structure. Held on a per-section |
783 | and per-sub-section basis. */ | |
a737bd4d | 784 | |
c19d1205 | 785 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 786 | typedef struct literal_pool |
b99bd4ef | 787 | { |
c921be7d NC |
788 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
789 | unsigned int next_free_entry; | |
790 | unsigned int id; | |
791 | symbolS * symbol; | |
792 | segT section; | |
793 | subsegT sub_section; | |
a8040cf2 NC |
794 | #ifdef OBJ_ELF |
795 | struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE]; | |
796 | #endif | |
c921be7d | 797 | struct literal_pool * next; |
8335d6aa | 798 | unsigned int alignment; |
3d0c9500 | 799 | } literal_pool; |
b99bd4ef | 800 | |
3d0c9500 NC |
801 | /* Pointer to a linked list of literal pools. */ |
802 | literal_pool * list_of_pools = NULL; | |
e27ec89e | 803 | |
2e6976a8 DG |
804 | typedef enum asmfunc_states |
805 | { | |
806 | OUTSIDE_ASMFUNC, | |
807 | WAITING_ASMFUNC_NAME, | |
808 | WAITING_ENDASMFUNC | |
809 | } asmfunc_states; | |
810 | ||
811 | static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC; | |
812 | ||
e07e6e58 NC |
813 | #ifdef OBJ_ELF |
814 | # define now_it seg_info (now_seg)->tc_segment_info_data.current_it | |
815 | #else | |
816 | static struct current_it now_it; | |
817 | #endif | |
818 | ||
819 | static inline int | |
820 | now_it_compatible (int cond) | |
821 | { | |
822 | return (cond & ~1) == (now_it.cc & ~1); | |
823 | } | |
824 | ||
825 | static inline int | |
826 | conditional_insn (void) | |
827 | { | |
828 | return inst.cond != COND_ALWAYS; | |
829 | } | |
830 | ||
831 | static int in_it_block (void); | |
832 | ||
833 | static int handle_it_state (void); | |
834 | ||
835 | static void force_automatic_it_block_close (void); | |
836 | ||
c921be7d NC |
837 | static void it_fsm_post_encode (void); |
838 | ||
e07e6e58 NC |
839 | #define set_it_insn_type(type) \ |
840 | do \ | |
841 | { \ | |
842 | inst.it_insn_type = type; \ | |
843 | if (handle_it_state () == FAIL) \ | |
477330fc | 844 | return; \ |
e07e6e58 NC |
845 | } \ |
846 | while (0) | |
847 | ||
c921be7d NC |
848 | #define set_it_insn_type_nonvoid(type, failret) \ |
849 | do \ | |
850 | { \ | |
851 | inst.it_insn_type = type; \ | |
852 | if (handle_it_state () == FAIL) \ | |
477330fc | 853 | return failret; \ |
c921be7d NC |
854 | } \ |
855 | while(0) | |
856 | ||
e07e6e58 NC |
857 | #define set_it_insn_type_last() \ |
858 | do \ | |
859 | { \ | |
860 | if (inst.cond == COND_ALWAYS) \ | |
477330fc | 861 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \ |
e07e6e58 | 862 | else \ |
477330fc | 863 | set_it_insn_type (INSIDE_IT_LAST_INSN); \ |
e07e6e58 NC |
864 | } \ |
865 | while (0) | |
866 | ||
c19d1205 | 867 | /* Pure syntax. */ |
b99bd4ef | 868 | |
c19d1205 ZW |
869 | /* This array holds the chars that always start a comment. If the |
870 | pre-processor is disabled, these aren't very useful. */ | |
2e6976a8 | 871 | char arm_comment_chars[] = "@"; |
3d0c9500 | 872 | |
c19d1205 ZW |
873 | /* This array holds the chars that only start a comment at the beginning of |
874 | a line. If the line seems to have the form '# 123 filename' | |
875 | .line and .file directives will appear in the pre-processed output. */ | |
876 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
877 | first line of the input file. This is because the compiler outputs | |
878 | #NO_APP at the beginning of its output. */ | |
879 | /* Also note that comments like this one will always work. */ | |
880 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 881 | |
2e6976a8 | 882 | char arm_line_separator_chars[] = ";"; |
b99bd4ef | 883 | |
c19d1205 ZW |
884 | /* Chars that can be used to separate mant |
885 | from exp in floating point numbers. */ | |
886 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 887 | |
c19d1205 ZW |
888 | /* Chars that mean this number is a floating point constant. */ |
889 | /* As in 0f12.456 */ | |
890 | /* or 0d1.2345e12 */ | |
b99bd4ef | 891 | |
c19d1205 | 892 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 893 | |
c19d1205 ZW |
894 | /* Prefix characters that indicate the start of an immediate |
895 | value. */ | |
896 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 897 | |
c19d1205 ZW |
898 | /* Separator character handling. */ |
899 | ||
900 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
901 | ||
902 | static inline int | |
903 | skip_past_char (char ** str, char c) | |
904 | { | |
8ab8155f NC |
905 | /* PR gas/14987: Allow for whitespace before the expected character. */ |
906 | skip_whitespace (*str); | |
427d0db6 | 907 | |
c19d1205 ZW |
908 | if (**str == c) |
909 | { | |
910 | (*str)++; | |
911 | return SUCCESS; | |
3d0c9500 | 912 | } |
c19d1205 ZW |
913 | else |
914 | return FAIL; | |
915 | } | |
c921be7d | 916 | |
c19d1205 | 917 | #define skip_past_comma(str) skip_past_char (str, ',') |
3d0c9500 | 918 | |
c19d1205 ZW |
919 | /* Arithmetic expressions (possibly involving symbols). */ |
920 | ||
921 | /* Return TRUE if anything in the expression is a bignum. */ | |
922 | ||
923 | static int | |
924 | walk_no_bignums (symbolS * sp) | |
925 | { | |
926 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
927 | return 1; | |
928 | ||
929 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 930 | { |
c19d1205 ZW |
931 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
932 | || (symbol_get_value_expression (sp)->X_op_symbol | |
933 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
934 | } |
935 | ||
c19d1205 | 936 | return 0; |
3d0c9500 NC |
937 | } |
938 | ||
c19d1205 ZW |
939 | static int in_my_get_expression = 0; |
940 | ||
941 | /* Third argument to my_get_expression. */ | |
942 | #define GE_NO_PREFIX 0 | |
943 | #define GE_IMM_PREFIX 1 | |
944 | #define GE_OPT_PREFIX 2 | |
5287ad62 JB |
945 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
946 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ | |
947 | #define GE_OPT_PREFIX_BIG 3 | |
a737bd4d | 948 | |
b99bd4ef | 949 | static int |
c19d1205 | 950 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 951 | { |
c19d1205 ZW |
952 | char * save_in; |
953 | segT seg; | |
b99bd4ef | 954 | |
c19d1205 ZW |
955 | /* In unified syntax, all prefixes are optional. */ |
956 | if (unified_syntax) | |
5287ad62 | 957 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
477330fc | 958 | : GE_OPT_PREFIX; |
b99bd4ef | 959 | |
c19d1205 | 960 | switch (prefix_mode) |
b99bd4ef | 961 | { |
c19d1205 ZW |
962 | case GE_NO_PREFIX: break; |
963 | case GE_IMM_PREFIX: | |
964 | if (!is_immediate_prefix (**str)) | |
965 | { | |
966 | inst.error = _("immediate expression requires a # prefix"); | |
967 | return FAIL; | |
968 | } | |
969 | (*str)++; | |
970 | break; | |
971 | case GE_OPT_PREFIX: | |
5287ad62 | 972 | case GE_OPT_PREFIX_BIG: |
c19d1205 ZW |
973 | if (is_immediate_prefix (**str)) |
974 | (*str)++; | |
975 | break; | |
976 | default: abort (); | |
977 | } | |
b99bd4ef | 978 | |
c19d1205 | 979 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 980 | |
c19d1205 ZW |
981 | save_in = input_line_pointer; |
982 | input_line_pointer = *str; | |
983 | in_my_get_expression = 1; | |
984 | seg = expression (ep); | |
985 | in_my_get_expression = 0; | |
986 | ||
f86adc07 | 987 | if (ep->X_op == O_illegal || ep->X_op == O_absent) |
b99bd4ef | 988 | { |
f86adc07 | 989 | /* We found a bad or missing expression in md_operand(). */ |
c19d1205 ZW |
990 | *str = input_line_pointer; |
991 | input_line_pointer = save_in; | |
992 | if (inst.error == NULL) | |
f86adc07 NS |
993 | inst.error = (ep->X_op == O_absent |
994 | ? _("missing expression") :_("bad expression")); | |
c19d1205 ZW |
995 | return 1; |
996 | } | |
b99bd4ef | 997 | |
c19d1205 ZW |
998 | #ifdef OBJ_AOUT |
999 | if (seg != absolute_section | |
1000 | && seg != text_section | |
1001 | && seg != data_section | |
1002 | && seg != bss_section | |
1003 | && seg != undefined_section) | |
1004 | { | |
1005 | inst.error = _("bad segment"); | |
1006 | *str = input_line_pointer; | |
1007 | input_line_pointer = save_in; | |
1008 | return 1; | |
b99bd4ef | 1009 | } |
87975d2a AM |
1010 | #else |
1011 | (void) seg; | |
c19d1205 | 1012 | #endif |
b99bd4ef | 1013 | |
c19d1205 ZW |
1014 | /* Get rid of any bignums now, so that we don't generate an error for which |
1015 | we can't establish a line number later on. Big numbers are never valid | |
1016 | in instructions, which is where this routine is always called. */ | |
5287ad62 JB |
1017 | if (prefix_mode != GE_OPT_PREFIX_BIG |
1018 | && (ep->X_op == O_big | |
477330fc | 1019 | || (ep->X_add_symbol |
5287ad62 | 1020 | && (walk_no_bignums (ep->X_add_symbol) |
477330fc | 1021 | || (ep->X_op_symbol |
5287ad62 | 1022 | && walk_no_bignums (ep->X_op_symbol)))))) |
c19d1205 ZW |
1023 | { |
1024 | inst.error = _("invalid constant"); | |
1025 | *str = input_line_pointer; | |
1026 | input_line_pointer = save_in; | |
1027 | return 1; | |
1028 | } | |
b99bd4ef | 1029 | |
c19d1205 ZW |
1030 | *str = input_line_pointer; |
1031 | input_line_pointer = save_in; | |
1032 | return 0; | |
b99bd4ef NC |
1033 | } |
1034 | ||
c19d1205 ZW |
1035 | /* Turn a string in input_line_pointer into a floating point constant |
1036 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
1037 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
1038 | returned, or NULL on OK. | |
b99bd4ef | 1039 | |
c19d1205 ZW |
1040 | Note that fp constants aren't represent in the normal way on the ARM. |
1041 | In big endian mode, things are as expected. However, in little endian | |
1042 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
1043 | within the words. For example, (double) 1.1 in big endian mode is | |
1044 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
1045 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 1046 | |
c19d1205 | 1047 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 1048 | |
c19d1205 ZW |
1049 | char * |
1050 | md_atof (int type, char * litP, int * sizeP) | |
1051 | { | |
1052 | int prec; | |
1053 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
1054 | char *t; | |
1055 | int i; | |
b99bd4ef | 1056 | |
c19d1205 ZW |
1057 | switch (type) |
1058 | { | |
1059 | case 'f': | |
1060 | case 'F': | |
1061 | case 's': | |
1062 | case 'S': | |
1063 | prec = 2; | |
1064 | break; | |
b99bd4ef | 1065 | |
c19d1205 ZW |
1066 | case 'd': |
1067 | case 'D': | |
1068 | case 'r': | |
1069 | case 'R': | |
1070 | prec = 4; | |
1071 | break; | |
b99bd4ef | 1072 | |
c19d1205 ZW |
1073 | case 'x': |
1074 | case 'X': | |
499ac353 | 1075 | prec = 5; |
c19d1205 | 1076 | break; |
b99bd4ef | 1077 | |
c19d1205 ZW |
1078 | case 'p': |
1079 | case 'P': | |
499ac353 | 1080 | prec = 5; |
c19d1205 | 1081 | break; |
a737bd4d | 1082 | |
c19d1205 ZW |
1083 | default: |
1084 | *sizeP = 0; | |
499ac353 | 1085 | return _("Unrecognized or unsupported floating point constant"); |
c19d1205 | 1086 | } |
b99bd4ef | 1087 | |
c19d1205 ZW |
1088 | t = atof_ieee (input_line_pointer, type, words); |
1089 | if (t) | |
1090 | input_line_pointer = t; | |
499ac353 | 1091 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
b99bd4ef | 1092 | |
c19d1205 ZW |
1093 | if (target_big_endian) |
1094 | { | |
1095 | for (i = 0; i < prec; i++) | |
1096 | { | |
499ac353 NC |
1097 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1098 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1099 | } |
1100 | } | |
1101 | else | |
1102 | { | |
e74cfd16 | 1103 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
1104 | for (i = prec - 1; i >= 0; i--) |
1105 | { | |
499ac353 NC |
1106 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1107 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1108 | } |
1109 | else | |
1110 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
1111 | For an 8 byte float the order is 1 0 3 2. */ | |
1112 | for (i = 0; i < prec; i += 2) | |
1113 | { | |
499ac353 NC |
1114 | md_number_to_chars (litP, (valueT) words[i + 1], |
1115 | sizeof (LITTLENUM_TYPE)); | |
1116 | md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), | |
1117 | (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1118 | litP += 2 * sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1119 | } |
1120 | } | |
b99bd4ef | 1121 | |
499ac353 | 1122 | return NULL; |
c19d1205 | 1123 | } |
b99bd4ef | 1124 | |
c19d1205 ZW |
1125 | /* We handle all bad expressions here, so that we can report the faulty |
1126 | instruction in the error message. */ | |
1127 | void | |
91d6fa6a | 1128 | md_operand (expressionS * exp) |
c19d1205 ZW |
1129 | { |
1130 | if (in_my_get_expression) | |
91d6fa6a | 1131 | exp->X_op = O_illegal; |
b99bd4ef NC |
1132 | } |
1133 | ||
c19d1205 | 1134 | /* Immediate values. */ |
b99bd4ef | 1135 | |
c19d1205 ZW |
1136 | /* Generic immediate-value read function for use in directives. |
1137 | Accepts anything that 'expression' can fold to a constant. | |
1138 | *val receives the number. */ | |
1139 | #ifdef OBJ_ELF | |
1140 | static int | |
1141 | immediate_for_directive (int *val) | |
b99bd4ef | 1142 | { |
c19d1205 ZW |
1143 | expressionS exp; |
1144 | exp.X_op = O_illegal; | |
b99bd4ef | 1145 | |
c19d1205 ZW |
1146 | if (is_immediate_prefix (*input_line_pointer)) |
1147 | { | |
1148 | input_line_pointer++; | |
1149 | expression (&exp); | |
1150 | } | |
b99bd4ef | 1151 | |
c19d1205 ZW |
1152 | if (exp.X_op != O_constant) |
1153 | { | |
1154 | as_bad (_("expected #constant")); | |
1155 | ignore_rest_of_line (); | |
1156 | return FAIL; | |
1157 | } | |
1158 | *val = exp.X_add_number; | |
1159 | return SUCCESS; | |
b99bd4ef | 1160 | } |
c19d1205 | 1161 | #endif |
b99bd4ef | 1162 | |
c19d1205 | 1163 | /* Register parsing. */ |
b99bd4ef | 1164 | |
c19d1205 ZW |
1165 | /* Generic register parser. CCP points to what should be the |
1166 | beginning of a register name. If it is indeed a valid register | |
1167 | name, advance CCP over it and return the reg_entry structure; | |
1168 | otherwise return NULL. Does not issue diagnostics. */ | |
1169 | ||
1170 | static struct reg_entry * | |
1171 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 1172 | { |
c19d1205 ZW |
1173 | char *start = *ccp; |
1174 | char *p; | |
1175 | struct reg_entry *reg; | |
b99bd4ef | 1176 | |
477330fc RM |
1177 | skip_whitespace (start); |
1178 | ||
c19d1205 ZW |
1179 | #ifdef REGISTER_PREFIX |
1180 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 1181 | return NULL; |
c19d1205 ZW |
1182 | start++; |
1183 | #endif | |
1184 | #ifdef OPTIONAL_REGISTER_PREFIX | |
1185 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
1186 | start++; | |
1187 | #endif | |
b99bd4ef | 1188 | |
c19d1205 ZW |
1189 | p = start; |
1190 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
1191 | return NULL; | |
b99bd4ef | 1192 | |
c19d1205 ZW |
1193 | do |
1194 | p++; | |
1195 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
1196 | ||
1197 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
1198 | ||
1199 | if (!reg) | |
1200 | return NULL; | |
1201 | ||
1202 | *ccp = p; | |
1203 | return reg; | |
b99bd4ef NC |
1204 | } |
1205 | ||
1206 | static int | |
dcbf9037 | 1207 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
477330fc | 1208 | enum arm_reg_type type) |
b99bd4ef | 1209 | { |
c19d1205 ZW |
1210 | /* Alternative syntaxes are accepted for a few register classes. */ |
1211 | switch (type) | |
1212 | { | |
1213 | case REG_TYPE_MVF: | |
1214 | case REG_TYPE_MVD: | |
1215 | case REG_TYPE_MVFX: | |
1216 | case REG_TYPE_MVDX: | |
1217 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 1218 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
1219 | return reg->number; |
1220 | break; | |
69b97547 | 1221 | |
c19d1205 ZW |
1222 | case REG_TYPE_CP: |
1223 | /* For backward compatibility, a bare number is valid here. */ | |
1224 | { | |
1225 | unsigned long processor = strtoul (start, ccp, 10); | |
1226 | if (*ccp != start && processor <= 15) | |
1227 | return processor; | |
1228 | } | |
6057a28f | 1229 | |
c19d1205 ZW |
1230 | case REG_TYPE_MMXWC: |
1231 | /* WC includes WCG. ??? I'm not sure this is true for all | |
1232 | instructions that take WC registers. */ | |
79134647 | 1233 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 1234 | return reg->number; |
6057a28f | 1235 | break; |
c19d1205 | 1236 | |
6057a28f | 1237 | default: |
c19d1205 | 1238 | break; |
6057a28f NC |
1239 | } |
1240 | ||
dcbf9037 JB |
1241 | return FAIL; |
1242 | } | |
1243 | ||
1244 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the | |
1245 | return value is the register number or FAIL. */ | |
1246 | ||
1247 | static int | |
1248 | arm_reg_parse (char **ccp, enum arm_reg_type type) | |
1249 | { | |
1250 | char *start = *ccp; | |
1251 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
1252 | int ret; | |
1253 | ||
1254 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1255 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) | |
1256 | return FAIL; | |
1257 | ||
1258 | if (reg && reg->type == type) | |
1259 | return reg->number; | |
1260 | ||
1261 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) | |
1262 | return ret; | |
1263 | ||
c19d1205 ZW |
1264 | *ccp = start; |
1265 | return FAIL; | |
1266 | } | |
69b97547 | 1267 | |
dcbf9037 JB |
1268 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
1269 | character. Does no verification at this stage that the type fits the opcode | |
1270 | properly. E.g., | |
1271 | ||
1272 | .i32.i32.s16 | |
1273 | .s32.f32 | |
1274 | .u16 | |
1275 | ||
1276 | Can all be legally parsed by this function. | |
1277 | ||
1278 | Fills in neon_type struct pointer with parsed information, and updates STR | |
1279 | to point after the parsed type specifier. Returns SUCCESS if this was a legal | |
1280 | type, FAIL if not. */ | |
1281 | ||
1282 | static int | |
1283 | parse_neon_type (struct neon_type *type, char **str) | |
1284 | { | |
1285 | char *ptr = *str; | |
1286 | ||
1287 | if (type) | |
1288 | type->elems = 0; | |
1289 | ||
1290 | while (type->elems < NEON_MAX_TYPE_ELS) | |
1291 | { | |
1292 | enum neon_el_type thistype = NT_untyped; | |
1293 | unsigned thissize = -1u; | |
1294 | ||
1295 | if (*ptr != '.') | |
1296 | break; | |
1297 | ||
1298 | ptr++; | |
1299 | ||
1300 | /* Just a size without an explicit type. */ | |
1301 | if (ISDIGIT (*ptr)) | |
1302 | goto parsesize; | |
1303 | ||
1304 | switch (TOLOWER (*ptr)) | |
1305 | { | |
1306 | case 'i': thistype = NT_integer; break; | |
1307 | case 'f': thistype = NT_float; break; | |
1308 | case 'p': thistype = NT_poly; break; | |
1309 | case 's': thistype = NT_signed; break; | |
1310 | case 'u': thistype = NT_unsigned; break; | |
477330fc RM |
1311 | case 'd': |
1312 | thistype = NT_float; | |
1313 | thissize = 64; | |
1314 | ptr++; | |
1315 | goto done; | |
dcbf9037 JB |
1316 | default: |
1317 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); | |
1318 | return FAIL; | |
1319 | } | |
1320 | ||
1321 | ptr++; | |
1322 | ||
1323 | /* .f is an abbreviation for .f32. */ | |
1324 | if (thistype == NT_float && !ISDIGIT (*ptr)) | |
1325 | thissize = 32; | |
1326 | else | |
1327 | { | |
1328 | parsesize: | |
1329 | thissize = strtoul (ptr, &ptr, 10); | |
1330 | ||
1331 | if (thissize != 8 && thissize != 16 && thissize != 32 | |
477330fc RM |
1332 | && thissize != 64) |
1333 | { | |
1334 | as_bad (_("bad size %d in type specifier"), thissize); | |
dcbf9037 JB |
1335 | return FAIL; |
1336 | } | |
1337 | } | |
1338 | ||
037e8744 | 1339 | done: |
dcbf9037 | 1340 | if (type) |
477330fc RM |
1341 | { |
1342 | type->el[type->elems].type = thistype; | |
dcbf9037 JB |
1343 | type->el[type->elems].size = thissize; |
1344 | type->elems++; | |
1345 | } | |
1346 | } | |
1347 | ||
1348 | /* Empty/missing type is not a successful parse. */ | |
1349 | if (type->elems == 0) | |
1350 | return FAIL; | |
1351 | ||
1352 | *str = ptr; | |
1353 | ||
1354 | return SUCCESS; | |
1355 | } | |
1356 | ||
1357 | /* Errors may be set multiple times during parsing or bit encoding | |
1358 | (particularly in the Neon bits), but usually the earliest error which is set | |
1359 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
1360 | errors by calling this function. */ | |
1361 | ||
1362 | static void | |
1363 | first_error (const char *err) | |
1364 | { | |
1365 | if (!inst.error) | |
1366 | inst.error = err; | |
1367 | } | |
1368 | ||
1369 | /* Parse a single type, e.g. ".s32", leading period included. */ | |
1370 | static int | |
1371 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) | |
1372 | { | |
1373 | char *str = *ccp; | |
1374 | struct neon_type optype; | |
1375 | ||
1376 | if (*str == '.') | |
1377 | { | |
1378 | if (parse_neon_type (&optype, &str) == SUCCESS) | |
477330fc RM |
1379 | { |
1380 | if (optype.elems == 1) | |
1381 | *vectype = optype.el[0]; | |
1382 | else | |
1383 | { | |
1384 | first_error (_("only one type should be specified for operand")); | |
1385 | return FAIL; | |
1386 | } | |
1387 | } | |
dcbf9037 | 1388 | else |
477330fc RM |
1389 | { |
1390 | first_error (_("vector type expected")); | |
1391 | return FAIL; | |
1392 | } | |
dcbf9037 JB |
1393 | } |
1394 | else | |
1395 | return FAIL; | |
5f4273c7 | 1396 | |
dcbf9037 | 1397 | *ccp = str; |
5f4273c7 | 1398 | |
dcbf9037 JB |
1399 | return SUCCESS; |
1400 | } | |
1401 | ||
1402 | /* Special meanings for indices (which have a range of 0-7), which will fit into | |
1403 | a 4-bit integer. */ | |
1404 | ||
1405 | #define NEON_ALL_LANES 15 | |
1406 | #define NEON_INTERLEAVE_LANES 14 | |
1407 | ||
1408 | /* Parse either a register or a scalar, with an optional type. Return the | |
1409 | register number, and optionally fill in the actual type of the register | |
1410 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and | |
1411 | type/index information in *TYPEINFO. */ | |
1412 | ||
1413 | static int | |
1414 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, | |
477330fc RM |
1415 | enum arm_reg_type *rtype, |
1416 | struct neon_typed_alias *typeinfo) | |
dcbf9037 JB |
1417 | { |
1418 | char *str = *ccp; | |
1419 | struct reg_entry *reg = arm_reg_parse_multi (&str); | |
1420 | struct neon_typed_alias atype; | |
1421 | struct neon_type_el parsetype; | |
1422 | ||
1423 | atype.defined = 0; | |
1424 | atype.index = -1; | |
1425 | atype.eltype.type = NT_invtype; | |
1426 | atype.eltype.size = -1; | |
1427 | ||
1428 | /* Try alternate syntax for some types of register. Note these are mutually | |
1429 | exclusive with the Neon syntax extensions. */ | |
1430 | if (reg == NULL) | |
1431 | { | |
1432 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); | |
1433 | if (altreg != FAIL) | |
477330fc | 1434 | *ccp = str; |
dcbf9037 | 1435 | if (typeinfo) |
477330fc | 1436 | *typeinfo = atype; |
dcbf9037 JB |
1437 | return altreg; |
1438 | } | |
1439 | ||
037e8744 JB |
1440 | /* Undo polymorphism when a set of register types may be accepted. */ |
1441 | if ((type == REG_TYPE_NDQ | |
1442 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) | |
1443 | || (type == REG_TYPE_VFSD | |
477330fc | 1444 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) |
037e8744 | 1445 | || (type == REG_TYPE_NSDQ |
477330fc RM |
1446 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD |
1447 | || reg->type == REG_TYPE_NQ)) | |
f512f76f NC |
1448 | || (type == REG_TYPE_MMXWC |
1449 | && (reg->type == REG_TYPE_MMXWCG))) | |
21d799b5 | 1450 | type = (enum arm_reg_type) reg->type; |
dcbf9037 JB |
1451 | |
1452 | if (type != reg->type) | |
1453 | return FAIL; | |
1454 | ||
1455 | if (reg->neon) | |
1456 | atype = *reg->neon; | |
5f4273c7 | 1457 | |
dcbf9037 JB |
1458 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) |
1459 | { | |
1460 | if ((atype.defined & NTA_HASTYPE) != 0) | |
477330fc RM |
1461 | { |
1462 | first_error (_("can't redefine type for operand")); | |
1463 | return FAIL; | |
1464 | } | |
dcbf9037 JB |
1465 | atype.defined |= NTA_HASTYPE; |
1466 | atype.eltype = parsetype; | |
1467 | } | |
5f4273c7 | 1468 | |
dcbf9037 JB |
1469 | if (skip_past_char (&str, '[') == SUCCESS) |
1470 | { | |
1471 | if (type != REG_TYPE_VFD) | |
477330fc RM |
1472 | { |
1473 | first_error (_("only D registers may be indexed")); | |
1474 | return FAIL; | |
1475 | } | |
5f4273c7 | 1476 | |
dcbf9037 | 1477 | if ((atype.defined & NTA_HASINDEX) != 0) |
477330fc RM |
1478 | { |
1479 | first_error (_("can't change index for operand")); | |
1480 | return FAIL; | |
1481 | } | |
dcbf9037 JB |
1482 | |
1483 | atype.defined |= NTA_HASINDEX; | |
1484 | ||
1485 | if (skip_past_char (&str, ']') == SUCCESS) | |
477330fc | 1486 | atype.index = NEON_ALL_LANES; |
dcbf9037 | 1487 | else |
477330fc RM |
1488 | { |
1489 | expressionS exp; | |
dcbf9037 | 1490 | |
477330fc | 1491 | my_get_expression (&exp, &str, GE_NO_PREFIX); |
dcbf9037 | 1492 | |
477330fc RM |
1493 | if (exp.X_op != O_constant) |
1494 | { | |
1495 | first_error (_("constant expression required")); | |
1496 | return FAIL; | |
1497 | } | |
dcbf9037 | 1498 | |
477330fc RM |
1499 | if (skip_past_char (&str, ']') == FAIL) |
1500 | return FAIL; | |
dcbf9037 | 1501 | |
477330fc RM |
1502 | atype.index = exp.X_add_number; |
1503 | } | |
dcbf9037 | 1504 | } |
5f4273c7 | 1505 | |
dcbf9037 JB |
1506 | if (typeinfo) |
1507 | *typeinfo = atype; | |
5f4273c7 | 1508 | |
dcbf9037 JB |
1509 | if (rtype) |
1510 | *rtype = type; | |
5f4273c7 | 1511 | |
dcbf9037 | 1512 | *ccp = str; |
5f4273c7 | 1513 | |
dcbf9037 JB |
1514 | return reg->number; |
1515 | } | |
1516 | ||
1517 | /* Like arm_reg_parse, but allow allow the following extra features: | |
1518 | - If RTYPE is non-zero, return the (possibly restricted) type of the | |
1519 | register (e.g. Neon double or quad reg when either has been requested). | |
1520 | - If this is a Neon vector type with additional type information, fill | |
1521 | in the struct pointed to by VECTYPE (if non-NULL). | |
5f4273c7 | 1522 | This function will fault on encountering a scalar. */ |
dcbf9037 JB |
1523 | |
1524 | static int | |
1525 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, | |
477330fc | 1526 | enum arm_reg_type *rtype, struct neon_type_el *vectype) |
dcbf9037 JB |
1527 | { |
1528 | struct neon_typed_alias atype; | |
1529 | char *str = *ccp; | |
1530 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); | |
1531 | ||
1532 | if (reg == FAIL) | |
1533 | return FAIL; | |
1534 | ||
0855e32b NS |
1535 | /* Do not allow regname(... to parse as a register. */ |
1536 | if (*str == '(') | |
1537 | return FAIL; | |
1538 | ||
dcbf9037 JB |
1539 | /* Do not allow a scalar (reg+index) to parse as a register. */ |
1540 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1541 | { | |
1542 | first_error (_("register operand expected, but got scalar")); | |
1543 | return FAIL; | |
1544 | } | |
1545 | ||
1546 | if (vectype) | |
1547 | *vectype = atype.eltype; | |
1548 | ||
1549 | *ccp = str; | |
1550 | ||
1551 | return reg; | |
1552 | } | |
1553 | ||
1554 | #define NEON_SCALAR_REG(X) ((X) >> 4) | |
1555 | #define NEON_SCALAR_INDEX(X) ((X) & 15) | |
1556 | ||
5287ad62 JB |
1557 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
1558 | have enough information to be able to do a good job bounds-checking. So, we | |
1559 | just do easy checks here, and do further checks later. */ | |
1560 | ||
1561 | static int | |
dcbf9037 | 1562 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type) |
5287ad62 | 1563 | { |
dcbf9037 | 1564 | int reg; |
5287ad62 | 1565 | char *str = *ccp; |
dcbf9037 | 1566 | struct neon_typed_alias atype; |
5f4273c7 | 1567 | |
dcbf9037 | 1568 | reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); |
5f4273c7 | 1569 | |
dcbf9037 | 1570 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
5287ad62 | 1571 | return FAIL; |
5f4273c7 | 1572 | |
dcbf9037 | 1573 | if (atype.index == NEON_ALL_LANES) |
5287ad62 | 1574 | { |
dcbf9037 | 1575 | first_error (_("scalar must have an index")); |
5287ad62 JB |
1576 | return FAIL; |
1577 | } | |
dcbf9037 | 1578 | else if (atype.index >= 64 / elsize) |
5287ad62 | 1579 | { |
dcbf9037 | 1580 | first_error (_("scalar index out of range")); |
5287ad62 JB |
1581 | return FAIL; |
1582 | } | |
5f4273c7 | 1583 | |
dcbf9037 JB |
1584 | if (type) |
1585 | *type = atype.eltype; | |
5f4273c7 | 1586 | |
5287ad62 | 1587 | *ccp = str; |
5f4273c7 | 1588 | |
dcbf9037 | 1589 | return reg * 16 + atype.index; |
5287ad62 JB |
1590 | } |
1591 | ||
c19d1205 | 1592 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
e07e6e58 | 1593 | |
c19d1205 ZW |
1594 | static long |
1595 | parse_reg_list (char ** strp) | |
1596 | { | |
1597 | char * str = * strp; | |
1598 | long range = 0; | |
1599 | int another_range; | |
a737bd4d | 1600 | |
c19d1205 ZW |
1601 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
1602 | do | |
6057a28f | 1603 | { |
477330fc RM |
1604 | skip_whitespace (str); |
1605 | ||
c19d1205 | 1606 | another_range = 0; |
a737bd4d | 1607 | |
c19d1205 ZW |
1608 | if (*str == '{') |
1609 | { | |
1610 | int in_range = 0; | |
1611 | int cur_reg = -1; | |
a737bd4d | 1612 | |
c19d1205 ZW |
1613 | str++; |
1614 | do | |
1615 | { | |
1616 | int reg; | |
6057a28f | 1617 | |
dcbf9037 | 1618 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
c19d1205 | 1619 | { |
dcbf9037 | 1620 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 ZW |
1621 | return FAIL; |
1622 | } | |
a737bd4d | 1623 | |
c19d1205 ZW |
1624 | if (in_range) |
1625 | { | |
1626 | int i; | |
a737bd4d | 1627 | |
c19d1205 ZW |
1628 | if (reg <= cur_reg) |
1629 | { | |
dcbf9037 | 1630 | first_error (_("bad range in register list")); |
c19d1205 ZW |
1631 | return FAIL; |
1632 | } | |
40a18ebd | 1633 | |
c19d1205 ZW |
1634 | for (i = cur_reg + 1; i < reg; i++) |
1635 | { | |
1636 | if (range & (1 << i)) | |
1637 | as_tsktsk | |
1638 | (_("Warning: duplicated register (r%d) in register list"), | |
1639 | i); | |
1640 | else | |
1641 | range |= 1 << i; | |
1642 | } | |
1643 | in_range = 0; | |
1644 | } | |
a737bd4d | 1645 | |
c19d1205 ZW |
1646 | if (range & (1 << reg)) |
1647 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1648 | reg); | |
1649 | else if (reg <= cur_reg) | |
1650 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1651 | |
c19d1205 ZW |
1652 | range |= 1 << reg; |
1653 | cur_reg = reg; | |
1654 | } | |
1655 | while (skip_past_comma (&str) != FAIL | |
1656 | || (in_range = 1, *str++ == '-')); | |
1657 | str--; | |
a737bd4d | 1658 | |
d996d970 | 1659 | if (skip_past_char (&str, '}') == FAIL) |
c19d1205 | 1660 | { |
dcbf9037 | 1661 | first_error (_("missing `}'")); |
c19d1205 ZW |
1662 | return FAIL; |
1663 | } | |
1664 | } | |
1665 | else | |
1666 | { | |
91d6fa6a | 1667 | expressionS exp; |
40a18ebd | 1668 | |
91d6fa6a | 1669 | if (my_get_expression (&exp, &str, GE_NO_PREFIX)) |
c19d1205 | 1670 | return FAIL; |
40a18ebd | 1671 | |
91d6fa6a | 1672 | if (exp.X_op == O_constant) |
c19d1205 | 1673 | { |
91d6fa6a NC |
1674 | if (exp.X_add_number |
1675 | != (exp.X_add_number & 0x0000ffff)) | |
c19d1205 ZW |
1676 | { |
1677 | inst.error = _("invalid register mask"); | |
1678 | return FAIL; | |
1679 | } | |
a737bd4d | 1680 | |
91d6fa6a | 1681 | if ((range & exp.X_add_number) != 0) |
c19d1205 | 1682 | { |
91d6fa6a | 1683 | int regno = range & exp.X_add_number; |
a737bd4d | 1684 | |
c19d1205 ZW |
1685 | regno &= -regno; |
1686 | regno = (1 << regno) - 1; | |
1687 | as_tsktsk | |
1688 | (_("Warning: duplicated register (r%d) in register list"), | |
1689 | regno); | |
1690 | } | |
a737bd4d | 1691 | |
91d6fa6a | 1692 | range |= exp.X_add_number; |
c19d1205 ZW |
1693 | } |
1694 | else | |
1695 | { | |
1696 | if (inst.reloc.type != 0) | |
1697 | { | |
1698 | inst.error = _("expression too complex"); | |
1699 | return FAIL; | |
1700 | } | |
a737bd4d | 1701 | |
91d6fa6a | 1702 | memcpy (&inst.reloc.exp, &exp, sizeof (expressionS)); |
c19d1205 ZW |
1703 | inst.reloc.type = BFD_RELOC_ARM_MULTI; |
1704 | inst.reloc.pc_rel = 0; | |
1705 | } | |
1706 | } | |
a737bd4d | 1707 | |
c19d1205 ZW |
1708 | if (*str == '|' || *str == '+') |
1709 | { | |
1710 | str++; | |
1711 | another_range = 1; | |
1712 | } | |
a737bd4d | 1713 | } |
c19d1205 | 1714 | while (another_range); |
a737bd4d | 1715 | |
c19d1205 ZW |
1716 | *strp = str; |
1717 | return range; | |
a737bd4d NC |
1718 | } |
1719 | ||
5287ad62 JB |
1720 | /* Types of registers in a list. */ |
1721 | ||
1722 | enum reg_list_els | |
1723 | { | |
1724 | REGLIST_VFP_S, | |
1725 | REGLIST_VFP_D, | |
1726 | REGLIST_NEON_D | |
1727 | }; | |
1728 | ||
c19d1205 ZW |
1729 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1730 | Otherwise return the number of registers, and set PBASE to the first | |
5287ad62 JB |
1731 | register. Parses registers of type ETYPE. |
1732 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: | |
1733 | - Q registers can be used to specify pairs of D registers | |
1734 | - { } can be omitted from around a singleton register list | |
477330fc RM |
1735 | FIXME: This is not implemented, as it would require backtracking in |
1736 | some cases, e.g.: | |
1737 | vtbl.8 d3,d4,d5 | |
1738 | This could be done (the meaning isn't really ambiguous), but doesn't | |
1739 | fit in well with the current parsing framework. | |
dcbf9037 JB |
1740 | - 32 D registers may be used (also true for VFPv3). |
1741 | FIXME: Types are ignored in these register lists, which is probably a | |
1742 | bug. */ | |
6057a28f | 1743 | |
c19d1205 | 1744 | static int |
037e8744 | 1745 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) |
6057a28f | 1746 | { |
037e8744 | 1747 | char *str = *ccp; |
c19d1205 ZW |
1748 | int base_reg; |
1749 | int new_base; | |
21d799b5 | 1750 | enum arm_reg_type regtype = (enum arm_reg_type) 0; |
5287ad62 | 1751 | int max_regs = 0; |
c19d1205 ZW |
1752 | int count = 0; |
1753 | int warned = 0; | |
1754 | unsigned long mask = 0; | |
a737bd4d | 1755 | int i; |
6057a28f | 1756 | |
477330fc | 1757 | if (skip_past_char (&str, '{') == FAIL) |
5287ad62 JB |
1758 | { |
1759 | inst.error = _("expecting {"); | |
1760 | return FAIL; | |
1761 | } | |
6057a28f | 1762 | |
5287ad62 | 1763 | switch (etype) |
c19d1205 | 1764 | { |
5287ad62 | 1765 | case REGLIST_VFP_S: |
c19d1205 ZW |
1766 | regtype = REG_TYPE_VFS; |
1767 | max_regs = 32; | |
5287ad62 | 1768 | break; |
5f4273c7 | 1769 | |
5287ad62 JB |
1770 | case REGLIST_VFP_D: |
1771 | regtype = REG_TYPE_VFD; | |
b7fc2769 | 1772 | break; |
5f4273c7 | 1773 | |
b7fc2769 JB |
1774 | case REGLIST_NEON_D: |
1775 | regtype = REG_TYPE_NDQ; | |
1776 | break; | |
1777 | } | |
1778 | ||
1779 | if (etype != REGLIST_VFP_S) | |
1780 | { | |
b1cc4aeb PB |
1781 | /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ |
1782 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) | |
477330fc RM |
1783 | { |
1784 | max_regs = 32; | |
1785 | if (thumb_mode) | |
1786 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
1787 | fpu_vfp_ext_d32); | |
1788 | else | |
1789 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
1790 | fpu_vfp_ext_d32); | |
1791 | } | |
5287ad62 | 1792 | else |
477330fc | 1793 | max_regs = 16; |
c19d1205 | 1794 | } |
6057a28f | 1795 | |
c19d1205 | 1796 | base_reg = max_regs; |
a737bd4d | 1797 | |
c19d1205 ZW |
1798 | do |
1799 | { | |
5287ad62 | 1800 | int setmask = 1, addregs = 1; |
dcbf9037 | 1801 | |
037e8744 | 1802 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
dcbf9037 | 1803 | |
c19d1205 | 1804 | if (new_base == FAIL) |
a737bd4d | 1805 | { |
dcbf9037 | 1806 | first_error (_(reg_expected_msgs[regtype])); |
c19d1205 ZW |
1807 | return FAIL; |
1808 | } | |
5f4273c7 | 1809 | |
b7fc2769 | 1810 | if (new_base >= max_regs) |
477330fc RM |
1811 | { |
1812 | first_error (_("register out of range in list")); | |
1813 | return FAIL; | |
1814 | } | |
5f4273c7 | 1815 | |
5287ad62 JB |
1816 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
1817 | if (regtype == REG_TYPE_NQ) | |
477330fc RM |
1818 | { |
1819 | setmask = 3; | |
1820 | addregs = 2; | |
1821 | } | |
5287ad62 | 1822 | |
c19d1205 ZW |
1823 | if (new_base < base_reg) |
1824 | base_reg = new_base; | |
a737bd4d | 1825 | |
5287ad62 | 1826 | if (mask & (setmask << new_base)) |
c19d1205 | 1827 | { |
dcbf9037 | 1828 | first_error (_("invalid register list")); |
c19d1205 | 1829 | return FAIL; |
a737bd4d | 1830 | } |
a737bd4d | 1831 | |
c19d1205 ZW |
1832 | if ((mask >> new_base) != 0 && ! warned) |
1833 | { | |
1834 | as_tsktsk (_("register list not in ascending order")); | |
1835 | warned = 1; | |
1836 | } | |
0bbf2aa4 | 1837 | |
5287ad62 JB |
1838 | mask |= setmask << new_base; |
1839 | count += addregs; | |
0bbf2aa4 | 1840 | |
037e8744 | 1841 | if (*str == '-') /* We have the start of a range expression */ |
c19d1205 ZW |
1842 | { |
1843 | int high_range; | |
0bbf2aa4 | 1844 | |
037e8744 | 1845 | str++; |
0bbf2aa4 | 1846 | |
037e8744 | 1847 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
477330fc | 1848 | == FAIL) |
c19d1205 ZW |
1849 | { |
1850 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1851 | return FAIL; | |
1852 | } | |
0bbf2aa4 | 1853 | |
477330fc RM |
1854 | if (high_range >= max_regs) |
1855 | { | |
1856 | first_error (_("register out of range in list")); | |
1857 | return FAIL; | |
1858 | } | |
b7fc2769 | 1859 | |
477330fc RM |
1860 | if (regtype == REG_TYPE_NQ) |
1861 | high_range = high_range + 1; | |
5287ad62 | 1862 | |
c19d1205 ZW |
1863 | if (high_range <= new_base) |
1864 | { | |
1865 | inst.error = _("register range not in ascending order"); | |
1866 | return FAIL; | |
1867 | } | |
0bbf2aa4 | 1868 | |
5287ad62 | 1869 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
0bbf2aa4 | 1870 | { |
5287ad62 | 1871 | if (mask & (setmask << new_base)) |
0bbf2aa4 | 1872 | { |
c19d1205 ZW |
1873 | inst.error = _("invalid register list"); |
1874 | return FAIL; | |
0bbf2aa4 | 1875 | } |
c19d1205 | 1876 | |
5287ad62 JB |
1877 | mask |= setmask << new_base; |
1878 | count += addregs; | |
0bbf2aa4 | 1879 | } |
0bbf2aa4 | 1880 | } |
0bbf2aa4 | 1881 | } |
037e8744 | 1882 | while (skip_past_comma (&str) != FAIL); |
0bbf2aa4 | 1883 | |
037e8744 | 1884 | str++; |
0bbf2aa4 | 1885 | |
c19d1205 ZW |
1886 | /* Sanity check -- should have raised a parse error above. */ |
1887 | if (count == 0 || count > max_regs) | |
1888 | abort (); | |
1889 | ||
1890 | *pbase = base_reg; | |
1891 | ||
1892 | /* Final test -- the registers must be consecutive. */ | |
1893 | mask >>= base_reg; | |
1894 | for (i = 0; i < count; i++) | |
1895 | { | |
1896 | if ((mask & (1u << i)) == 0) | |
1897 | { | |
1898 | inst.error = _("non-contiguous register range"); | |
1899 | return FAIL; | |
1900 | } | |
1901 | } | |
1902 | ||
037e8744 JB |
1903 | *ccp = str; |
1904 | ||
c19d1205 | 1905 | return count; |
b99bd4ef NC |
1906 | } |
1907 | ||
dcbf9037 JB |
1908 | /* True if two alias types are the same. */ |
1909 | ||
c921be7d | 1910 | static bfd_boolean |
dcbf9037 JB |
1911 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) |
1912 | { | |
1913 | if (!a && !b) | |
c921be7d | 1914 | return TRUE; |
5f4273c7 | 1915 | |
dcbf9037 | 1916 | if (!a || !b) |
c921be7d | 1917 | return FALSE; |
dcbf9037 JB |
1918 | |
1919 | if (a->defined != b->defined) | |
c921be7d | 1920 | return FALSE; |
5f4273c7 | 1921 | |
dcbf9037 JB |
1922 | if ((a->defined & NTA_HASTYPE) != 0 |
1923 | && (a->eltype.type != b->eltype.type | |
477330fc | 1924 | || a->eltype.size != b->eltype.size)) |
c921be7d | 1925 | return FALSE; |
dcbf9037 JB |
1926 | |
1927 | if ((a->defined & NTA_HASINDEX) != 0 | |
1928 | && (a->index != b->index)) | |
c921be7d | 1929 | return FALSE; |
5f4273c7 | 1930 | |
c921be7d | 1931 | return TRUE; |
dcbf9037 JB |
1932 | } |
1933 | ||
5287ad62 JB |
1934 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
1935 | The base register is put in *PBASE. | |
dcbf9037 | 1936 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
5287ad62 JB |
1937 | the return value. |
1938 | The register stride (minus one) is put in bit 4 of the return value. | |
dcbf9037 JB |
1939 | Bits [6:5] encode the list length (minus one). |
1940 | The type of the list elements is put in *ELTYPE, if non-NULL. */ | |
5287ad62 | 1941 | |
5287ad62 | 1942 | #define NEON_LANE(X) ((X) & 0xf) |
dcbf9037 | 1943 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
5287ad62 JB |
1944 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
1945 | ||
1946 | static int | |
dcbf9037 | 1947 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
477330fc | 1948 | struct neon_type_el *eltype) |
5287ad62 JB |
1949 | { |
1950 | char *ptr = *str; | |
1951 | int base_reg = -1; | |
1952 | int reg_incr = -1; | |
1953 | int count = 0; | |
1954 | int lane = -1; | |
1955 | int leading_brace = 0; | |
1956 | enum arm_reg_type rtype = REG_TYPE_NDQ; | |
20203fb9 NC |
1957 | const char *const incr_error = _("register stride must be 1 or 2"); |
1958 | const char *const type_error = _("mismatched element/structure types in list"); | |
dcbf9037 | 1959 | struct neon_typed_alias firsttype; |
5f4273c7 | 1960 | |
5287ad62 JB |
1961 | if (skip_past_char (&ptr, '{') == SUCCESS) |
1962 | leading_brace = 1; | |
5f4273c7 | 1963 | |
5287ad62 JB |
1964 | do |
1965 | { | |
dcbf9037 JB |
1966 | struct neon_typed_alias atype; |
1967 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); | |
1968 | ||
5287ad62 | 1969 | if (getreg == FAIL) |
477330fc RM |
1970 | { |
1971 | first_error (_(reg_expected_msgs[rtype])); | |
1972 | return FAIL; | |
1973 | } | |
5f4273c7 | 1974 | |
5287ad62 | 1975 | if (base_reg == -1) |
477330fc RM |
1976 | { |
1977 | base_reg = getreg; | |
1978 | if (rtype == REG_TYPE_NQ) | |
1979 | { | |
1980 | reg_incr = 1; | |
1981 | } | |
1982 | firsttype = atype; | |
1983 | } | |
5287ad62 | 1984 | else if (reg_incr == -1) |
477330fc RM |
1985 | { |
1986 | reg_incr = getreg - base_reg; | |
1987 | if (reg_incr < 1 || reg_incr > 2) | |
1988 | { | |
1989 | first_error (_(incr_error)); | |
1990 | return FAIL; | |
1991 | } | |
1992 | } | |
5287ad62 | 1993 | else if (getreg != base_reg + reg_incr * count) |
477330fc RM |
1994 | { |
1995 | first_error (_(incr_error)); | |
1996 | return FAIL; | |
1997 | } | |
dcbf9037 | 1998 | |
c921be7d | 1999 | if (! neon_alias_types_same (&atype, &firsttype)) |
477330fc RM |
2000 | { |
2001 | first_error (_(type_error)); | |
2002 | return FAIL; | |
2003 | } | |
5f4273c7 | 2004 | |
5287ad62 | 2005 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list |
477330fc | 2006 | modes. */ |
5287ad62 | 2007 | if (ptr[0] == '-') |
477330fc RM |
2008 | { |
2009 | struct neon_typed_alias htype; | |
2010 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; | |
2011 | if (lane == -1) | |
2012 | lane = NEON_INTERLEAVE_LANES; | |
2013 | else if (lane != NEON_INTERLEAVE_LANES) | |
2014 | { | |
2015 | first_error (_(type_error)); | |
2016 | return FAIL; | |
2017 | } | |
2018 | if (reg_incr == -1) | |
2019 | reg_incr = 1; | |
2020 | else if (reg_incr != 1) | |
2021 | { | |
2022 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); | |
2023 | return FAIL; | |
2024 | } | |
2025 | ptr++; | |
2026 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); | |
2027 | if (hireg == FAIL) | |
2028 | { | |
2029 | first_error (_(reg_expected_msgs[rtype])); | |
2030 | return FAIL; | |
2031 | } | |
2032 | if (! neon_alias_types_same (&htype, &firsttype)) | |
2033 | { | |
2034 | first_error (_(type_error)); | |
2035 | return FAIL; | |
2036 | } | |
2037 | count += hireg + dregs - getreg; | |
2038 | continue; | |
2039 | } | |
5f4273c7 | 2040 | |
5287ad62 JB |
2041 | /* If we're using Q registers, we can't use [] or [n] syntax. */ |
2042 | if (rtype == REG_TYPE_NQ) | |
477330fc RM |
2043 | { |
2044 | count += 2; | |
2045 | continue; | |
2046 | } | |
5f4273c7 | 2047 | |
dcbf9037 | 2048 | if ((atype.defined & NTA_HASINDEX) != 0) |
477330fc RM |
2049 | { |
2050 | if (lane == -1) | |
2051 | lane = atype.index; | |
2052 | else if (lane != atype.index) | |
2053 | { | |
2054 | first_error (_(type_error)); | |
2055 | return FAIL; | |
2056 | } | |
2057 | } | |
5287ad62 | 2058 | else if (lane == -1) |
477330fc | 2059 | lane = NEON_INTERLEAVE_LANES; |
5287ad62 | 2060 | else if (lane != NEON_INTERLEAVE_LANES) |
477330fc RM |
2061 | { |
2062 | first_error (_(type_error)); | |
2063 | return FAIL; | |
2064 | } | |
5287ad62 JB |
2065 | count++; |
2066 | } | |
2067 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); | |
5f4273c7 | 2068 | |
5287ad62 JB |
2069 | /* No lane set by [x]. We must be interleaving structures. */ |
2070 | if (lane == -1) | |
2071 | lane = NEON_INTERLEAVE_LANES; | |
5f4273c7 | 2072 | |
5287ad62 JB |
2073 | /* Sanity check. */ |
2074 | if (lane == -1 || base_reg == -1 || count < 1 || count > 4 | |
2075 | || (count > 1 && reg_incr == -1)) | |
2076 | { | |
dcbf9037 | 2077 | first_error (_("error parsing element/structure list")); |
5287ad62 JB |
2078 | return FAIL; |
2079 | } | |
2080 | ||
2081 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) | |
2082 | { | |
dcbf9037 | 2083 | first_error (_("expected }")); |
5287ad62 JB |
2084 | return FAIL; |
2085 | } | |
5f4273c7 | 2086 | |
5287ad62 JB |
2087 | if (reg_incr == -1) |
2088 | reg_incr = 1; | |
2089 | ||
dcbf9037 JB |
2090 | if (eltype) |
2091 | *eltype = firsttype.eltype; | |
2092 | ||
5287ad62 JB |
2093 | *pbase = base_reg; |
2094 | *str = ptr; | |
5f4273c7 | 2095 | |
5287ad62 JB |
2096 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); |
2097 | } | |
2098 | ||
c19d1205 ZW |
2099 | /* Parse an explicit relocation suffix on an expression. This is |
2100 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
2101 | arm_reloc_hsh contains no entries, so this function can only | |
2102 | succeed if there is no () after the word. Returns -1 on error, | |
2103 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
3da1d841 | 2104 | |
c19d1205 ZW |
2105 | static int |
2106 | parse_reloc (char **str) | |
b99bd4ef | 2107 | { |
c19d1205 ZW |
2108 | struct reloc_entry *r; |
2109 | char *p, *q; | |
b99bd4ef | 2110 | |
c19d1205 ZW |
2111 | if (**str != '(') |
2112 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 2113 | |
c19d1205 ZW |
2114 | p = *str + 1; |
2115 | q = p; | |
2116 | ||
2117 | while (*q && *q != ')' && *q != ',') | |
2118 | q++; | |
2119 | if (*q != ')') | |
2120 | return -1; | |
2121 | ||
21d799b5 NC |
2122 | if ((r = (struct reloc_entry *) |
2123 | hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
c19d1205 ZW |
2124 | return -1; |
2125 | ||
2126 | *str = q + 1; | |
2127 | return r->reloc; | |
b99bd4ef NC |
2128 | } |
2129 | ||
c19d1205 ZW |
2130 | /* Directives: register aliases. */ |
2131 | ||
dcbf9037 | 2132 | static struct reg_entry * |
90ec0d68 | 2133 | insert_reg_alias (char *str, unsigned number, int type) |
b99bd4ef | 2134 | { |
d3ce72d0 | 2135 | struct reg_entry *new_reg; |
c19d1205 | 2136 | const char *name; |
b99bd4ef | 2137 | |
d3ce72d0 | 2138 | if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) |
c19d1205 | 2139 | { |
d3ce72d0 | 2140 | if (new_reg->builtin) |
c19d1205 | 2141 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); |
b99bd4ef | 2142 | |
c19d1205 ZW |
2143 | /* Only warn about a redefinition if it's not defined as the |
2144 | same register. */ | |
d3ce72d0 | 2145 | else if (new_reg->number != number || new_reg->type != type) |
c19d1205 | 2146 | as_warn (_("ignoring redefinition of register alias '%s'"), str); |
69b97547 | 2147 | |
d929913e | 2148 | return NULL; |
c19d1205 | 2149 | } |
b99bd4ef | 2150 | |
c19d1205 | 2151 | name = xstrdup (str); |
d3ce72d0 | 2152 | new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry)); |
b99bd4ef | 2153 | |
d3ce72d0 NC |
2154 | new_reg->name = name; |
2155 | new_reg->number = number; | |
2156 | new_reg->type = type; | |
2157 | new_reg->builtin = FALSE; | |
2158 | new_reg->neon = NULL; | |
b99bd4ef | 2159 | |
d3ce72d0 | 2160 | if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) |
c19d1205 | 2161 | abort (); |
5f4273c7 | 2162 | |
d3ce72d0 | 2163 | return new_reg; |
dcbf9037 JB |
2164 | } |
2165 | ||
2166 | static void | |
2167 | insert_neon_reg_alias (char *str, int number, int type, | |
477330fc | 2168 | struct neon_typed_alias *atype) |
dcbf9037 JB |
2169 | { |
2170 | struct reg_entry *reg = insert_reg_alias (str, number, type); | |
5f4273c7 | 2171 | |
dcbf9037 JB |
2172 | if (!reg) |
2173 | { | |
2174 | first_error (_("attempt to redefine typed alias")); | |
2175 | return; | |
2176 | } | |
5f4273c7 | 2177 | |
dcbf9037 JB |
2178 | if (atype) |
2179 | { | |
21d799b5 | 2180 | reg->neon = (struct neon_typed_alias *) |
477330fc | 2181 | xmalloc (sizeof (struct neon_typed_alias)); |
dcbf9037 JB |
2182 | *reg->neon = *atype; |
2183 | } | |
c19d1205 | 2184 | } |
b99bd4ef | 2185 | |
c19d1205 | 2186 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 2187 | |
c19d1205 | 2188 | new_register_name .req existing_register_name |
b99bd4ef | 2189 | |
c19d1205 | 2190 | If we find one, or if it looks sufficiently like one that we want to |
d929913e | 2191 | handle any error here, return TRUE. Otherwise return FALSE. */ |
b99bd4ef | 2192 | |
d929913e | 2193 | static bfd_boolean |
c19d1205 ZW |
2194 | create_register_alias (char * newname, char *p) |
2195 | { | |
2196 | struct reg_entry *old; | |
2197 | char *oldname, *nbuf; | |
2198 | size_t nlen; | |
b99bd4ef | 2199 | |
c19d1205 ZW |
2200 | /* The input scrubber ensures that whitespace after the mnemonic is |
2201 | collapsed to single spaces. */ | |
2202 | oldname = p; | |
2203 | if (strncmp (oldname, " .req ", 6) != 0) | |
d929913e | 2204 | return FALSE; |
b99bd4ef | 2205 | |
c19d1205 ZW |
2206 | oldname += 6; |
2207 | if (*oldname == '\0') | |
d929913e | 2208 | return FALSE; |
b99bd4ef | 2209 | |
21d799b5 | 2210 | old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname); |
c19d1205 | 2211 | if (!old) |
b99bd4ef | 2212 | { |
c19d1205 | 2213 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
d929913e | 2214 | return TRUE; |
b99bd4ef NC |
2215 | } |
2216 | ||
c19d1205 ZW |
2217 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2218 | the desired alias name, and p points to its end. If not, then | |
2219 | the desired alias name is in the global original_case_string. */ | |
2220 | #ifdef TC_CASE_SENSITIVE | |
2221 | nlen = p - newname; | |
2222 | #else | |
2223 | newname = original_case_string; | |
2224 | nlen = strlen (newname); | |
2225 | #endif | |
b99bd4ef | 2226 | |
21d799b5 | 2227 | nbuf = (char *) alloca (nlen + 1); |
c19d1205 ZW |
2228 | memcpy (nbuf, newname, nlen); |
2229 | nbuf[nlen] = '\0'; | |
b99bd4ef | 2230 | |
c19d1205 ZW |
2231 | /* Create aliases under the new name as stated; an all-lowercase |
2232 | version of the new name; and an all-uppercase version of the new | |
2233 | name. */ | |
d929913e NC |
2234 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) |
2235 | { | |
2236 | for (p = nbuf; *p; p++) | |
2237 | *p = TOUPPER (*p); | |
c19d1205 | 2238 | |
d929913e NC |
2239 | if (strncmp (nbuf, newname, nlen)) |
2240 | { | |
2241 | /* If this attempt to create an additional alias fails, do not bother | |
2242 | trying to create the all-lower case alias. We will fail and issue | |
2243 | a second, duplicate error message. This situation arises when the | |
2244 | programmer does something like: | |
2245 | foo .req r0 | |
2246 | Foo .req r1 | |
2247 | The second .req creates the "Foo" alias but then fails to create | |
5f4273c7 | 2248 | the artificial FOO alias because it has already been created by the |
d929913e NC |
2249 | first .req. */ |
2250 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
2251 | return TRUE; | |
2252 | } | |
c19d1205 | 2253 | |
d929913e NC |
2254 | for (p = nbuf; *p; p++) |
2255 | *p = TOLOWER (*p); | |
c19d1205 | 2256 | |
d929913e NC |
2257 | if (strncmp (nbuf, newname, nlen)) |
2258 | insert_reg_alias (nbuf, old->number, old->type); | |
2259 | } | |
c19d1205 | 2260 | |
d929913e | 2261 | return TRUE; |
b99bd4ef NC |
2262 | } |
2263 | ||
dcbf9037 JB |
2264 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
2265 | X .dn d5.s32[1] | |
2266 | Y .qn 6.s16 | |
2267 | Z .dn d7 | |
2268 | T .dn Z[0] | |
2269 | These typed registers can be used instead of the types specified after the | |
2270 | Neon mnemonic, so long as all operands given have types. Types can also be | |
2271 | specified directly, e.g.: | |
5f4273c7 | 2272 | vadd d0.s32, d1.s32, d2.s32 */ |
dcbf9037 | 2273 | |
c921be7d | 2274 | static bfd_boolean |
dcbf9037 JB |
2275 | create_neon_reg_alias (char *newname, char *p) |
2276 | { | |
2277 | enum arm_reg_type basetype; | |
2278 | struct reg_entry *basereg; | |
2279 | struct reg_entry mybasereg; | |
2280 | struct neon_type ntype; | |
2281 | struct neon_typed_alias typeinfo; | |
12d6b0b7 | 2282 | char *namebuf, *nameend ATTRIBUTE_UNUSED; |
dcbf9037 | 2283 | int namelen; |
5f4273c7 | 2284 | |
dcbf9037 JB |
2285 | typeinfo.defined = 0; |
2286 | typeinfo.eltype.type = NT_invtype; | |
2287 | typeinfo.eltype.size = -1; | |
2288 | typeinfo.index = -1; | |
5f4273c7 | 2289 | |
dcbf9037 | 2290 | nameend = p; |
5f4273c7 | 2291 | |
dcbf9037 JB |
2292 | if (strncmp (p, " .dn ", 5) == 0) |
2293 | basetype = REG_TYPE_VFD; | |
2294 | else if (strncmp (p, " .qn ", 5) == 0) | |
2295 | basetype = REG_TYPE_NQ; | |
2296 | else | |
c921be7d | 2297 | return FALSE; |
5f4273c7 | 2298 | |
dcbf9037 | 2299 | p += 5; |
5f4273c7 | 2300 | |
dcbf9037 | 2301 | if (*p == '\0') |
c921be7d | 2302 | return FALSE; |
5f4273c7 | 2303 | |
dcbf9037 JB |
2304 | basereg = arm_reg_parse_multi (&p); |
2305 | ||
2306 | if (basereg && basereg->type != basetype) | |
2307 | { | |
2308 | as_bad (_("bad type for register")); | |
c921be7d | 2309 | return FALSE; |
dcbf9037 JB |
2310 | } |
2311 | ||
2312 | if (basereg == NULL) | |
2313 | { | |
2314 | expressionS exp; | |
2315 | /* Try parsing as an integer. */ | |
2316 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2317 | if (exp.X_op != O_constant) | |
477330fc RM |
2318 | { |
2319 | as_bad (_("expression must be constant")); | |
2320 | return FALSE; | |
2321 | } | |
dcbf9037 JB |
2322 | basereg = &mybasereg; |
2323 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 | |
477330fc | 2324 | : exp.X_add_number; |
dcbf9037 JB |
2325 | basereg->neon = 0; |
2326 | } | |
2327 | ||
2328 | if (basereg->neon) | |
2329 | typeinfo = *basereg->neon; | |
2330 | ||
2331 | if (parse_neon_type (&ntype, &p) == SUCCESS) | |
2332 | { | |
2333 | /* We got a type. */ | |
2334 | if (typeinfo.defined & NTA_HASTYPE) | |
477330fc RM |
2335 | { |
2336 | as_bad (_("can't redefine the type of a register alias")); | |
2337 | return FALSE; | |
2338 | } | |
5f4273c7 | 2339 | |
dcbf9037 JB |
2340 | typeinfo.defined |= NTA_HASTYPE; |
2341 | if (ntype.elems != 1) | |
477330fc RM |
2342 | { |
2343 | as_bad (_("you must specify a single type only")); | |
2344 | return FALSE; | |
2345 | } | |
dcbf9037 JB |
2346 | typeinfo.eltype = ntype.el[0]; |
2347 | } | |
5f4273c7 | 2348 | |
dcbf9037 JB |
2349 | if (skip_past_char (&p, '[') == SUCCESS) |
2350 | { | |
2351 | expressionS exp; | |
2352 | /* We got a scalar index. */ | |
5f4273c7 | 2353 | |
dcbf9037 | 2354 | if (typeinfo.defined & NTA_HASINDEX) |
477330fc RM |
2355 | { |
2356 | as_bad (_("can't redefine the index of a scalar alias")); | |
2357 | return FALSE; | |
2358 | } | |
5f4273c7 | 2359 | |
dcbf9037 | 2360 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
5f4273c7 | 2361 | |
dcbf9037 | 2362 | if (exp.X_op != O_constant) |
477330fc RM |
2363 | { |
2364 | as_bad (_("scalar index must be constant")); | |
2365 | return FALSE; | |
2366 | } | |
5f4273c7 | 2367 | |
dcbf9037 JB |
2368 | typeinfo.defined |= NTA_HASINDEX; |
2369 | typeinfo.index = exp.X_add_number; | |
5f4273c7 | 2370 | |
dcbf9037 | 2371 | if (skip_past_char (&p, ']') == FAIL) |
477330fc RM |
2372 | { |
2373 | as_bad (_("expecting ]")); | |
2374 | return FALSE; | |
2375 | } | |
dcbf9037 JB |
2376 | } |
2377 | ||
15735687 NS |
2378 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2379 | the desired alias name, and p points to its end. If not, then | |
2380 | the desired alias name is in the global original_case_string. */ | |
2381 | #ifdef TC_CASE_SENSITIVE | |
dcbf9037 | 2382 | namelen = nameend - newname; |
15735687 NS |
2383 | #else |
2384 | newname = original_case_string; | |
2385 | namelen = strlen (newname); | |
2386 | #endif | |
2387 | ||
21d799b5 | 2388 | namebuf = (char *) alloca (namelen + 1); |
dcbf9037 JB |
2389 | strncpy (namebuf, newname, namelen); |
2390 | namebuf[namelen] = '\0'; | |
5f4273c7 | 2391 | |
dcbf9037 | 2392 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
477330fc | 2393 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2394 | |
dcbf9037 JB |
2395 | /* Insert name in all uppercase. */ |
2396 | for (p = namebuf; *p; p++) | |
2397 | *p = TOUPPER (*p); | |
5f4273c7 | 2398 | |
dcbf9037 JB |
2399 | if (strncmp (namebuf, newname, namelen)) |
2400 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
477330fc | 2401 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2402 | |
dcbf9037 JB |
2403 | /* Insert name in all lowercase. */ |
2404 | for (p = namebuf; *p; p++) | |
2405 | *p = TOLOWER (*p); | |
5f4273c7 | 2406 | |
dcbf9037 JB |
2407 | if (strncmp (namebuf, newname, namelen)) |
2408 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
477330fc | 2409 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2410 | |
c921be7d | 2411 | return TRUE; |
dcbf9037 JB |
2412 | } |
2413 | ||
c19d1205 ZW |
2414 | /* Should never be called, as .req goes between the alias and the |
2415 | register name, not at the beginning of the line. */ | |
c921be7d | 2416 | |
b99bd4ef | 2417 | static void |
c19d1205 | 2418 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2419 | { |
c19d1205 ZW |
2420 | as_bad (_("invalid syntax for .req directive")); |
2421 | } | |
b99bd4ef | 2422 | |
dcbf9037 JB |
2423 | static void |
2424 | s_dn (int a ATTRIBUTE_UNUSED) | |
2425 | { | |
2426 | as_bad (_("invalid syntax for .dn directive")); | |
2427 | } | |
2428 | ||
2429 | static void | |
2430 | s_qn (int a ATTRIBUTE_UNUSED) | |
2431 | { | |
2432 | as_bad (_("invalid syntax for .qn directive")); | |
2433 | } | |
2434 | ||
c19d1205 ZW |
2435 | /* The .unreq directive deletes an alias which was previously defined |
2436 | by .req. For example: | |
b99bd4ef | 2437 | |
c19d1205 ZW |
2438 | my_alias .req r11 |
2439 | .unreq my_alias */ | |
b99bd4ef NC |
2440 | |
2441 | static void | |
c19d1205 | 2442 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2443 | { |
c19d1205 ZW |
2444 | char * name; |
2445 | char saved_char; | |
b99bd4ef | 2446 | |
c19d1205 ZW |
2447 | name = input_line_pointer; |
2448 | ||
2449 | while (*input_line_pointer != 0 | |
2450 | && *input_line_pointer != ' ' | |
2451 | && *input_line_pointer != '\n') | |
2452 | ++input_line_pointer; | |
2453 | ||
2454 | saved_char = *input_line_pointer; | |
2455 | *input_line_pointer = 0; | |
2456 | ||
2457 | if (!*name) | |
2458 | as_bad (_("invalid syntax for .unreq directive")); | |
2459 | else | |
2460 | { | |
21d799b5 | 2461 | struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh, |
477330fc | 2462 | name); |
c19d1205 ZW |
2463 | |
2464 | if (!reg) | |
2465 | as_bad (_("unknown register alias '%s'"), name); | |
2466 | else if (reg->builtin) | |
a1727c1a | 2467 | as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"), |
c19d1205 ZW |
2468 | name); |
2469 | else | |
2470 | { | |
d929913e NC |
2471 | char * p; |
2472 | char * nbuf; | |
2473 | ||
db0bc284 | 2474 | hash_delete (arm_reg_hsh, name, FALSE); |
c19d1205 | 2475 | free ((char *) reg->name); |
477330fc RM |
2476 | if (reg->neon) |
2477 | free (reg->neon); | |
c19d1205 | 2478 | free (reg); |
d929913e NC |
2479 | |
2480 | /* Also locate the all upper case and all lower case versions. | |
2481 | Do not complain if we cannot find one or the other as it | |
2482 | was probably deleted above. */ | |
5f4273c7 | 2483 | |
d929913e NC |
2484 | nbuf = strdup (name); |
2485 | for (p = nbuf; *p; p++) | |
2486 | *p = TOUPPER (*p); | |
21d799b5 | 2487 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2488 | if (reg) |
2489 | { | |
db0bc284 | 2490 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2491 | free ((char *) reg->name); |
2492 | if (reg->neon) | |
2493 | free (reg->neon); | |
2494 | free (reg); | |
2495 | } | |
2496 | ||
2497 | for (p = nbuf; *p; p++) | |
2498 | *p = TOLOWER (*p); | |
21d799b5 | 2499 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2500 | if (reg) |
2501 | { | |
db0bc284 | 2502 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2503 | free ((char *) reg->name); |
2504 | if (reg->neon) | |
2505 | free (reg->neon); | |
2506 | free (reg); | |
2507 | } | |
2508 | ||
2509 | free (nbuf); | |
c19d1205 ZW |
2510 | } |
2511 | } | |
b99bd4ef | 2512 | |
c19d1205 | 2513 | *input_line_pointer = saved_char; |
b99bd4ef NC |
2514 | demand_empty_rest_of_line (); |
2515 | } | |
2516 | ||
c19d1205 ZW |
2517 | /* Directives: Instruction set selection. */ |
2518 | ||
2519 | #ifdef OBJ_ELF | |
2520 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
2521 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
2522 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
2523 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
2524 | ||
cd000bff DJ |
2525 | /* Create a new mapping symbol for the transition to STATE. */ |
2526 | ||
2527 | static void | |
2528 | make_mapping_symbol (enum mstate state, valueT value, fragS *frag) | |
b99bd4ef | 2529 | { |
a737bd4d | 2530 | symbolS * symbolP; |
c19d1205 ZW |
2531 | const char * symname; |
2532 | int type; | |
b99bd4ef | 2533 | |
c19d1205 | 2534 | switch (state) |
b99bd4ef | 2535 | { |
c19d1205 ZW |
2536 | case MAP_DATA: |
2537 | symname = "$d"; | |
2538 | type = BSF_NO_FLAGS; | |
2539 | break; | |
2540 | case MAP_ARM: | |
2541 | symname = "$a"; | |
2542 | type = BSF_NO_FLAGS; | |
2543 | break; | |
2544 | case MAP_THUMB: | |
2545 | symname = "$t"; | |
2546 | type = BSF_NO_FLAGS; | |
2547 | break; | |
c19d1205 ZW |
2548 | default: |
2549 | abort (); | |
2550 | } | |
2551 | ||
cd000bff | 2552 | symbolP = symbol_new (symname, now_seg, value, frag); |
c19d1205 ZW |
2553 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; |
2554 | ||
2555 | switch (state) | |
2556 | { | |
2557 | case MAP_ARM: | |
2558 | THUMB_SET_FUNC (symbolP, 0); | |
2559 | ARM_SET_THUMB (symbolP, 0); | |
2560 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2561 | break; | |
2562 | ||
2563 | case MAP_THUMB: | |
2564 | THUMB_SET_FUNC (symbolP, 1); | |
2565 | ARM_SET_THUMB (symbolP, 1); | |
2566 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2567 | break; | |
2568 | ||
2569 | case MAP_DATA: | |
2570 | default: | |
cd000bff DJ |
2571 | break; |
2572 | } | |
2573 | ||
2574 | /* Save the mapping symbols for future reference. Also check that | |
2575 | we do not place two mapping symbols at the same offset within a | |
2576 | frag. We'll handle overlap between frags in | |
2de7820f JZ |
2577 | check_mapping_symbols. |
2578 | ||
2579 | If .fill or other data filling directive generates zero sized data, | |
2580 | the mapping symbol for the following code will have the same value | |
2581 | as the one generated for the data filling directive. In this case, | |
2582 | we replace the old symbol with the new one at the same address. */ | |
cd000bff DJ |
2583 | if (value == 0) |
2584 | { | |
2de7820f JZ |
2585 | if (frag->tc_frag_data.first_map != NULL) |
2586 | { | |
2587 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); | |
2588 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP); | |
2589 | } | |
cd000bff DJ |
2590 | frag->tc_frag_data.first_map = symbolP; |
2591 | } | |
2592 | if (frag->tc_frag_data.last_map != NULL) | |
0f020cef JZ |
2593 | { |
2594 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP)); | |
0f020cef JZ |
2595 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) |
2596 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP); | |
2597 | } | |
cd000bff DJ |
2598 | frag->tc_frag_data.last_map = symbolP; |
2599 | } | |
2600 | ||
2601 | /* We must sometimes convert a region marked as code to data during | |
2602 | code alignment, if an odd number of bytes have to be padded. The | |
2603 | code mapping symbol is pushed to an aligned address. */ | |
2604 | ||
2605 | static void | |
2606 | insert_data_mapping_symbol (enum mstate state, | |
2607 | valueT value, fragS *frag, offsetT bytes) | |
2608 | { | |
2609 | /* If there was already a mapping symbol, remove it. */ | |
2610 | if (frag->tc_frag_data.last_map != NULL | |
2611 | && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) | |
2612 | { | |
2613 | symbolS *symp = frag->tc_frag_data.last_map; | |
2614 | ||
2615 | if (value == 0) | |
2616 | { | |
2617 | know (frag->tc_frag_data.first_map == symp); | |
2618 | frag->tc_frag_data.first_map = NULL; | |
2619 | } | |
2620 | frag->tc_frag_data.last_map = NULL; | |
2621 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
c19d1205 | 2622 | } |
cd000bff DJ |
2623 | |
2624 | make_mapping_symbol (MAP_DATA, value, frag); | |
2625 | make_mapping_symbol (state, value + bytes, frag); | |
2626 | } | |
2627 | ||
2628 | static void mapping_state_2 (enum mstate state, int max_chars); | |
2629 | ||
2630 | /* Set the mapping state to STATE. Only call this when about to | |
2631 | emit some STATE bytes to the file. */ | |
2632 | ||
2633 | void | |
2634 | mapping_state (enum mstate state) | |
2635 | { | |
940b5ce0 DJ |
2636 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2637 | ||
cd000bff DJ |
2638 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
2639 | ||
2640 | if (mapstate == state) | |
2641 | /* The mapping symbol has already been emitted. | |
2642 | There is nothing else to do. */ | |
2643 | return; | |
49c62a33 NC |
2644 | |
2645 | if (state == MAP_ARM || state == MAP_THUMB) | |
2646 | /* PR gas/12931 | |
2647 | All ARM instructions require 4-byte alignment. | |
2648 | (Almost) all Thumb instructions require 2-byte alignment. | |
2649 | ||
2650 | When emitting instructions into any section, mark the section | |
2651 | appropriately. | |
2652 | ||
2653 | Some Thumb instructions are alignment-sensitive modulo 4 bytes, | |
2654 | but themselves require 2-byte alignment; this applies to some | |
2655 | PC- relative forms. However, these cases will invovle implicit | |
2656 | literal pool generation or an explicit .align >=2, both of | |
2657 | which will cause the section to me marked with sufficient | |
2658 | alignment. Thus, we don't handle those cases here. */ | |
2659 | record_alignment (now_seg, state == MAP_ARM ? 2 : 1); | |
2660 | ||
2661 | if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) | |
cd000bff DJ |
2662 | /* This case will be evaluated later in the next else. */ |
2663 | return; | |
2664 | else if (TRANSITION (MAP_UNDEFINED, MAP_ARM) | |
477330fc | 2665 | || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) |
cd000bff DJ |
2666 | { |
2667 | /* Only add the symbol if the offset is > 0: | |
477330fc RM |
2668 | if we're at the first frag, check it's size > 0; |
2669 | if we're not at the first frag, then for sure | |
2670 | the offset is > 0. */ | |
cd000bff DJ |
2671 | struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; |
2672 | const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); | |
2673 | ||
2674 | if (add_symbol) | |
477330fc | 2675 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); |
cd000bff DJ |
2676 | } |
2677 | ||
2678 | mapping_state_2 (state, 0); | |
2679 | #undef TRANSITION | |
2680 | } | |
2681 | ||
2682 | /* Same as mapping_state, but MAX_CHARS bytes have already been | |
2683 | allocated. Put the mapping symbol that far back. */ | |
2684 | ||
2685 | static void | |
2686 | mapping_state_2 (enum mstate state, int max_chars) | |
2687 | { | |
940b5ce0 DJ |
2688 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2689 | ||
2690 | if (!SEG_NORMAL (now_seg)) | |
2691 | return; | |
2692 | ||
cd000bff DJ |
2693 | if (mapstate == state) |
2694 | /* The mapping symbol has already been emitted. | |
2695 | There is nothing else to do. */ | |
2696 | return; | |
2697 | ||
cd000bff DJ |
2698 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; |
2699 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); | |
c19d1205 ZW |
2700 | } |
2701 | #else | |
d3106081 NS |
2702 | #define mapping_state(x) ((void)0) |
2703 | #define mapping_state_2(x, y) ((void)0) | |
c19d1205 ZW |
2704 | #endif |
2705 | ||
2706 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
2707 | ||
4343666d | 2708 | #ifdef OBJ_COFF |
c19d1205 ZW |
2709 | static symbolS * |
2710 | find_real_start (symbolS * symbolP) | |
2711 | { | |
2712 | char * real_start; | |
2713 | const char * name = S_GET_NAME (symbolP); | |
2714 | symbolS * new_target; | |
2715 | ||
2716 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
2717 | #define STUB_NAME ".real_start_of" | |
2718 | ||
2719 | if (name == NULL) | |
2720 | abort (); | |
2721 | ||
37f6032b ZW |
2722 | /* The compiler may generate BL instructions to local labels because |
2723 | it needs to perform a branch to a far away location. These labels | |
2724 | do not have a corresponding ".real_start_of" label. We check | |
2725 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
2726 | the ".real_start_of" convention for nonlocal branches. */ | |
2727 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
2728 | return symbolP; |
2729 | ||
37f6032b | 2730 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
2731 | new_target = symbol_find (real_start); |
2732 | ||
2733 | if (new_target == NULL) | |
2734 | { | |
bd3ba5d1 | 2735 | as_warn (_("Failed to find real start of function: %s\n"), name); |
c19d1205 ZW |
2736 | new_target = symbolP; |
2737 | } | |
2738 | ||
c19d1205 ZW |
2739 | return new_target; |
2740 | } | |
4343666d | 2741 | #endif |
c19d1205 ZW |
2742 | |
2743 | static void | |
2744 | opcode_select (int width) | |
2745 | { | |
2746 | switch (width) | |
2747 | { | |
2748 | case 16: | |
2749 | if (! thumb_mode) | |
2750 | { | |
e74cfd16 | 2751 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
2752 | as_bad (_("selected processor does not support THUMB opcodes")); |
2753 | ||
2754 | thumb_mode = 1; | |
2755 | /* No need to force the alignment, since we will have been | |
2756 | coming from ARM mode, which is word-aligned. */ | |
2757 | record_alignment (now_seg, 1); | |
2758 | } | |
c19d1205 ZW |
2759 | break; |
2760 | ||
2761 | case 32: | |
2762 | if (thumb_mode) | |
2763 | { | |
e74cfd16 | 2764 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
2765 | as_bad (_("selected processor does not support ARM opcodes")); |
2766 | ||
2767 | thumb_mode = 0; | |
2768 | ||
2769 | if (!need_pass_2) | |
2770 | frag_align (2, 0, 0); | |
2771 | ||
2772 | record_alignment (now_seg, 1); | |
2773 | } | |
c19d1205 ZW |
2774 | break; |
2775 | ||
2776 | default: | |
2777 | as_bad (_("invalid instruction size selected (%d)"), width); | |
2778 | } | |
2779 | } | |
2780 | ||
2781 | static void | |
2782 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
2783 | { | |
2784 | opcode_select (32); | |
2785 | demand_empty_rest_of_line (); | |
2786 | } | |
2787 | ||
2788 | static void | |
2789 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
2790 | { | |
2791 | opcode_select (16); | |
2792 | demand_empty_rest_of_line (); | |
2793 | } | |
2794 | ||
2795 | static void | |
2796 | s_code (int unused ATTRIBUTE_UNUSED) | |
2797 | { | |
2798 | int temp; | |
2799 | ||
2800 | temp = get_absolute_expression (); | |
2801 | switch (temp) | |
2802 | { | |
2803 | case 16: | |
2804 | case 32: | |
2805 | opcode_select (temp); | |
2806 | break; | |
2807 | ||
2808 | default: | |
2809 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
2810 | } | |
2811 | } | |
2812 | ||
2813 | static void | |
2814 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
2815 | { | |
2816 | /* If we are not already in thumb mode go into it, EVEN if | |
2817 | the target processor does not support thumb instructions. | |
2818 | This is used by gcc/config/arm/lib1funcs.asm for example | |
2819 | to compile interworking support functions even if the | |
2820 | target processor should not support interworking. */ | |
2821 | if (! thumb_mode) | |
2822 | { | |
2823 | thumb_mode = 2; | |
2824 | record_alignment (now_seg, 1); | |
2825 | } | |
2826 | ||
2827 | demand_empty_rest_of_line (); | |
2828 | } | |
2829 | ||
2830 | static void | |
2831 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
2832 | { | |
2833 | s_thumb (0); | |
2834 | ||
2835 | /* The following label is the name/address of the start of a Thumb function. | |
2836 | We need to know this for the interworking support. */ | |
2837 | label_is_thumb_function_name = TRUE; | |
2838 | } | |
2839 | ||
2840 | /* Perform a .set directive, but also mark the alias as | |
2841 | being a thumb function. */ | |
2842 | ||
2843 | static void | |
2844 | s_thumb_set (int equiv) | |
2845 | { | |
2846 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
2847 | We cannot just call that code as we need to get at the symbol that | |
2848 | is created. */ | |
2849 | char * name; | |
2850 | char delim; | |
2851 | char * end_name; | |
2852 | symbolS * symbolP; | |
2853 | ||
2854 | /* Especial apologies for the random logic: | |
2855 | This just grew, and could be parsed much more simply! | |
2856 | Dean - in haste. */ | |
2857 | name = input_line_pointer; | |
2858 | delim = get_symbol_end (); | |
2859 | end_name = input_line_pointer; | |
2860 | *end_name = delim; | |
2861 | ||
2862 | if (*input_line_pointer != ',') | |
2863 | { | |
2864 | *end_name = 0; | |
2865 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
2866 | *end_name = delim; |
2867 | ignore_rest_of_line (); | |
2868 | return; | |
2869 | } | |
2870 | ||
2871 | input_line_pointer++; | |
2872 | *end_name = 0; | |
2873 | ||
2874 | if (name[0] == '.' && name[1] == '\0') | |
2875 | { | |
2876 | /* XXX - this should not happen to .thumb_set. */ | |
2877 | abort (); | |
2878 | } | |
2879 | ||
2880 | if ((symbolP = symbol_find (name)) == NULL | |
2881 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
2882 | { | |
2883 | #ifndef NO_LISTING | |
2884 | /* When doing symbol listings, play games with dummy fragments living | |
2885 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 2886 | for this symbol. */ |
b99bd4ef NC |
2887 | if (listing & LISTING_SYMBOLS) |
2888 | { | |
2889 | extern struct list_info_struct * listing_tail; | |
21d799b5 | 2890 | fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS)); |
b99bd4ef NC |
2891 | |
2892 | memset (dummy_frag, 0, sizeof (fragS)); | |
2893 | dummy_frag->fr_type = rs_fill; | |
2894 | dummy_frag->line = listing_tail; | |
2895 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
2896 | dummy_frag->fr_symbol = symbolP; | |
2897 | } | |
2898 | else | |
2899 | #endif | |
2900 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
2901 | ||
2902 | #ifdef OBJ_COFF | |
2903 | /* "set" symbols are local unless otherwise specified. */ | |
2904 | SF_SET_LOCAL (symbolP); | |
2905 | #endif /* OBJ_COFF */ | |
2906 | } /* Make a new symbol. */ | |
2907 | ||
2908 | symbol_table_insert (symbolP); | |
2909 | ||
2910 | * end_name = delim; | |
2911 | ||
2912 | if (equiv | |
2913 | && S_IS_DEFINED (symbolP) | |
2914 | && S_GET_SEGMENT (symbolP) != reg_section) | |
2915 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
2916 | ||
2917 | pseudo_set (symbolP); | |
2918 | ||
2919 | demand_empty_rest_of_line (); | |
2920 | ||
c19d1205 | 2921 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
2922 | |
2923 | THUMB_SET_FUNC (symbolP, 1); | |
2924 | ARM_SET_THUMB (symbolP, 1); | |
2925 | #if defined OBJ_ELF || defined OBJ_COFF | |
2926 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2927 | #endif | |
2928 | } | |
2929 | ||
c19d1205 | 2930 | /* Directives: Mode selection. */ |
b99bd4ef | 2931 | |
c19d1205 ZW |
2932 | /* .syntax [unified|divided] - choose the new unified syntax |
2933 | (same for Arm and Thumb encoding, modulo slight differences in what | |
2934 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 2935 | static void |
c19d1205 | 2936 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2937 | { |
c19d1205 ZW |
2938 | char *name, delim; |
2939 | ||
2940 | name = input_line_pointer; | |
2941 | delim = get_symbol_end (); | |
2942 | ||
2943 | if (!strcasecmp (name, "unified")) | |
2944 | unified_syntax = TRUE; | |
2945 | else if (!strcasecmp (name, "divided")) | |
2946 | unified_syntax = FALSE; | |
2947 | else | |
2948 | { | |
2949 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
2950 | return; | |
2951 | } | |
2952 | *input_line_pointer = delim; | |
b99bd4ef NC |
2953 | demand_empty_rest_of_line (); |
2954 | } | |
2955 | ||
c19d1205 ZW |
2956 | /* Directives: sectioning and alignment. */ |
2957 | ||
2958 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
2959 | ||
b99bd4ef | 2960 | static void |
c19d1205 | 2961 | s_align (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2962 | { |
a737bd4d | 2963 | int temp; |
dce323d1 | 2964 | bfd_boolean fill_p; |
c19d1205 ZW |
2965 | long temp_fill; |
2966 | long max_alignment = 15; | |
b99bd4ef NC |
2967 | |
2968 | temp = get_absolute_expression (); | |
c19d1205 ZW |
2969 | if (temp > max_alignment) |
2970 | as_bad (_("alignment too large: %d assumed"), temp = max_alignment); | |
2971 | else if (temp < 0) | |
b99bd4ef | 2972 | { |
c19d1205 ZW |
2973 | as_bad (_("alignment negative. 0 assumed.")); |
2974 | temp = 0; | |
2975 | } | |
b99bd4ef | 2976 | |
c19d1205 ZW |
2977 | if (*input_line_pointer == ',') |
2978 | { | |
2979 | input_line_pointer++; | |
2980 | temp_fill = get_absolute_expression (); | |
dce323d1 | 2981 | fill_p = TRUE; |
b99bd4ef | 2982 | } |
c19d1205 | 2983 | else |
dce323d1 PB |
2984 | { |
2985 | fill_p = FALSE; | |
2986 | temp_fill = 0; | |
2987 | } | |
b99bd4ef | 2988 | |
c19d1205 ZW |
2989 | if (!temp) |
2990 | temp = 2; | |
b99bd4ef | 2991 | |
c19d1205 ZW |
2992 | /* Only make a frag if we HAVE to. */ |
2993 | if (temp && !need_pass_2) | |
dce323d1 PB |
2994 | { |
2995 | if (!fill_p && subseg_text_p (now_seg)) | |
2996 | frag_align_code (temp, 0); | |
2997 | else | |
2998 | frag_align (temp, (int) temp_fill, 0); | |
2999 | } | |
c19d1205 ZW |
3000 | demand_empty_rest_of_line (); |
3001 | ||
3002 | record_alignment (now_seg, temp); | |
b99bd4ef NC |
3003 | } |
3004 | ||
c19d1205 ZW |
3005 | static void |
3006 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 3007 | { |
c19d1205 ZW |
3008 | /* We don't support putting frags in the BSS segment, we fake it by |
3009 | marking in_bss, then looking at s_skip for clues. */ | |
3010 | subseg_set (bss_section, 0); | |
3011 | demand_empty_rest_of_line (); | |
cd000bff DJ |
3012 | |
3013 | #ifdef md_elf_section_change_hook | |
3014 | md_elf_section_change_hook (); | |
3015 | #endif | |
c19d1205 | 3016 | } |
b99bd4ef | 3017 | |
c19d1205 ZW |
3018 | static void |
3019 | s_even (int ignore ATTRIBUTE_UNUSED) | |
3020 | { | |
3021 | /* Never make frag if expect extra pass. */ | |
3022 | if (!need_pass_2) | |
3023 | frag_align (1, 0, 0); | |
b99bd4ef | 3024 | |
c19d1205 | 3025 | record_alignment (now_seg, 1); |
b99bd4ef | 3026 | |
c19d1205 | 3027 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3028 | } |
3029 | ||
2e6976a8 DG |
3030 | /* Directives: CodeComposer Studio. */ |
3031 | ||
3032 | /* .ref (for CodeComposer Studio syntax only). */ | |
3033 | static void | |
3034 | s_ccs_ref (int unused ATTRIBUTE_UNUSED) | |
3035 | { | |
3036 | if (codecomposer_syntax) | |
3037 | ignore_rest_of_line (); | |
3038 | else | |
3039 | as_bad (_(".ref pseudo-op only available with -mccs flag.")); | |
3040 | } | |
3041 | ||
3042 | /* If name is not NULL, then it is used for marking the beginning of a | |
3043 | function, wherease if it is NULL then it means the function end. */ | |
3044 | static void | |
3045 | asmfunc_debug (const char * name) | |
3046 | { | |
3047 | static const char * last_name = NULL; | |
3048 | ||
3049 | if (name != NULL) | |
3050 | { | |
3051 | gas_assert (last_name == NULL); | |
3052 | last_name = name; | |
3053 | ||
3054 | if (debug_type == DEBUG_STABS) | |
3055 | stabs_generate_asm_func (name, name); | |
3056 | } | |
3057 | else | |
3058 | { | |
3059 | gas_assert (last_name != NULL); | |
3060 | ||
3061 | if (debug_type == DEBUG_STABS) | |
3062 | stabs_generate_asm_endfunc (last_name, last_name); | |
3063 | ||
3064 | last_name = NULL; | |
3065 | } | |
3066 | } | |
3067 | ||
3068 | static void | |
3069 | s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED) | |
3070 | { | |
3071 | if (codecomposer_syntax) | |
3072 | { | |
3073 | switch (asmfunc_state) | |
3074 | { | |
3075 | case OUTSIDE_ASMFUNC: | |
3076 | asmfunc_state = WAITING_ASMFUNC_NAME; | |
3077 | break; | |
3078 | ||
3079 | case WAITING_ASMFUNC_NAME: | |
3080 | as_bad (_(".asmfunc repeated.")); | |
3081 | break; | |
3082 | ||
3083 | case WAITING_ENDASMFUNC: | |
3084 | as_bad (_(".asmfunc without function.")); | |
3085 | break; | |
3086 | } | |
3087 | demand_empty_rest_of_line (); | |
3088 | } | |
3089 | else | |
3090 | as_bad (_(".asmfunc pseudo-op only available with -mccs flag.")); | |
3091 | } | |
3092 | ||
3093 | static void | |
3094 | s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED) | |
3095 | { | |
3096 | if (codecomposer_syntax) | |
3097 | { | |
3098 | switch (asmfunc_state) | |
3099 | { | |
3100 | case OUTSIDE_ASMFUNC: | |
3101 | as_bad (_(".endasmfunc without a .asmfunc.")); | |
3102 | break; | |
3103 | ||
3104 | case WAITING_ASMFUNC_NAME: | |
3105 | as_bad (_(".endasmfunc without function.")); | |
3106 | break; | |
3107 | ||
3108 | case WAITING_ENDASMFUNC: | |
3109 | asmfunc_state = OUTSIDE_ASMFUNC; | |
3110 | asmfunc_debug (NULL); | |
3111 | break; | |
3112 | } | |
3113 | demand_empty_rest_of_line (); | |
3114 | } | |
3115 | else | |
3116 | as_bad (_(".endasmfunc pseudo-op only available with -mccs flag.")); | |
3117 | } | |
3118 | ||
3119 | static void | |
3120 | s_ccs_def (int name) | |
3121 | { | |
3122 | if (codecomposer_syntax) | |
3123 | s_globl (name); | |
3124 | else | |
3125 | as_bad (_(".def pseudo-op only available with -mccs flag.")); | |
3126 | } | |
3127 | ||
c19d1205 | 3128 | /* Directives: Literal pools. */ |
a737bd4d | 3129 | |
c19d1205 ZW |
3130 | static literal_pool * |
3131 | find_literal_pool (void) | |
a737bd4d | 3132 | { |
c19d1205 | 3133 | literal_pool * pool; |
a737bd4d | 3134 | |
c19d1205 | 3135 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 3136 | { |
c19d1205 ZW |
3137 | if (pool->section == now_seg |
3138 | && pool->sub_section == now_subseg) | |
3139 | break; | |
a737bd4d NC |
3140 | } |
3141 | ||
c19d1205 | 3142 | return pool; |
a737bd4d NC |
3143 | } |
3144 | ||
c19d1205 ZW |
3145 | static literal_pool * |
3146 | find_or_make_literal_pool (void) | |
a737bd4d | 3147 | { |
c19d1205 ZW |
3148 | /* Next literal pool ID number. */ |
3149 | static unsigned int latest_pool_num = 1; | |
3150 | literal_pool * pool; | |
a737bd4d | 3151 | |
c19d1205 | 3152 | pool = find_literal_pool (); |
a737bd4d | 3153 | |
c19d1205 | 3154 | if (pool == NULL) |
a737bd4d | 3155 | { |
c19d1205 | 3156 | /* Create a new pool. */ |
21d799b5 | 3157 | pool = (literal_pool *) xmalloc (sizeof (* pool)); |
c19d1205 ZW |
3158 | if (! pool) |
3159 | return NULL; | |
a737bd4d | 3160 | |
c19d1205 ZW |
3161 | pool->next_free_entry = 0; |
3162 | pool->section = now_seg; | |
3163 | pool->sub_section = now_subseg; | |
3164 | pool->next = list_of_pools; | |
3165 | pool->symbol = NULL; | |
8335d6aa | 3166 | pool->alignment = 2; |
c19d1205 ZW |
3167 | |
3168 | /* Add it to the list. */ | |
3169 | list_of_pools = pool; | |
a737bd4d | 3170 | } |
a737bd4d | 3171 | |
c19d1205 ZW |
3172 | /* New pools, and emptied pools, will have a NULL symbol. */ |
3173 | if (pool->symbol == NULL) | |
a737bd4d | 3174 | { |
c19d1205 ZW |
3175 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
3176 | (valueT) 0, &zero_address_frag); | |
3177 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
3178 | } |
3179 | ||
c19d1205 ZW |
3180 | /* Done. */ |
3181 | return pool; | |
a737bd4d NC |
3182 | } |
3183 | ||
c19d1205 | 3184 | /* Add the literal in the global 'inst' |
5f4273c7 | 3185 | structure to the relevant literal pool. */ |
b99bd4ef NC |
3186 | |
3187 | static int | |
8335d6aa | 3188 | add_to_lit_pool (unsigned int nbytes) |
b99bd4ef | 3189 | { |
8335d6aa JW |
3190 | #define PADDING_SLOT 0x1 |
3191 | #define LIT_ENTRY_SIZE_MASK 0xFF | |
c19d1205 | 3192 | literal_pool * pool; |
8335d6aa JW |
3193 | unsigned int entry, pool_size = 0; |
3194 | bfd_boolean padding_slot_p = FALSE; | |
e56c722b | 3195 | unsigned imm1 = 0; |
8335d6aa JW |
3196 | unsigned imm2 = 0; |
3197 | ||
3198 | if (nbytes == 8) | |
3199 | { | |
3200 | imm1 = inst.operands[1].imm; | |
3201 | imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg | |
3202 | : inst.reloc.exp.X_unsigned ? 0 | |
2569ceb0 | 3203 | : ((bfd_int64_t) inst.operands[1].imm) >> 32); |
8335d6aa JW |
3204 | if (target_big_endian) |
3205 | { | |
3206 | imm1 = imm2; | |
3207 | imm2 = inst.operands[1].imm; | |
3208 | } | |
3209 | } | |
b99bd4ef | 3210 | |
c19d1205 ZW |
3211 | pool = find_or_make_literal_pool (); |
3212 | ||
3213 | /* Check if this literal value is already in the pool. */ | |
3214 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 3215 | { |
8335d6aa JW |
3216 | if (nbytes == 4) |
3217 | { | |
3218 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3219 | && (inst.reloc.exp.X_op == O_constant) | |
3220 | && (pool->literals[entry].X_add_number | |
3221 | == inst.reloc.exp.X_add_number) | |
3222 | && (pool->literals[entry].X_md == nbytes) | |
3223 | && (pool->literals[entry].X_unsigned | |
3224 | == inst.reloc.exp.X_unsigned)) | |
3225 | break; | |
3226 | ||
3227 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3228 | && (inst.reloc.exp.X_op == O_symbol) | |
3229 | && (pool->literals[entry].X_add_number | |
3230 | == inst.reloc.exp.X_add_number) | |
3231 | && (pool->literals[entry].X_add_symbol | |
3232 | == inst.reloc.exp.X_add_symbol) | |
3233 | && (pool->literals[entry].X_op_symbol | |
3234 | == inst.reloc.exp.X_op_symbol) | |
3235 | && (pool->literals[entry].X_md == nbytes)) | |
3236 | break; | |
3237 | } | |
3238 | else if ((nbytes == 8) | |
3239 | && !(pool_size & 0x7) | |
3240 | && ((entry + 1) != pool->next_free_entry) | |
3241 | && (pool->literals[entry].X_op == O_constant) | |
19f2f6a9 | 3242 | && (pool->literals[entry].X_add_number == (offsetT) imm1) |
8335d6aa JW |
3243 | && (pool->literals[entry].X_unsigned |
3244 | == inst.reloc.exp.X_unsigned) | |
3245 | && (pool->literals[entry + 1].X_op == O_constant) | |
19f2f6a9 | 3246 | && (pool->literals[entry + 1].X_add_number == (offsetT) imm2) |
8335d6aa JW |
3247 | && (pool->literals[entry + 1].X_unsigned |
3248 | == inst.reloc.exp.X_unsigned)) | |
c19d1205 ZW |
3249 | break; |
3250 | ||
8335d6aa JW |
3251 | padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT); |
3252 | if (padding_slot_p && (nbytes == 4)) | |
c19d1205 | 3253 | break; |
8335d6aa JW |
3254 | |
3255 | pool_size += 4; | |
b99bd4ef NC |
3256 | } |
3257 | ||
c19d1205 ZW |
3258 | /* Do we need to create a new entry? */ |
3259 | if (entry == pool->next_free_entry) | |
3260 | { | |
3261 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
3262 | { | |
3263 | inst.error = _("literal pool overflow"); | |
3264 | return FAIL; | |
3265 | } | |
3266 | ||
8335d6aa JW |
3267 | if (nbytes == 8) |
3268 | { | |
3269 | /* For 8-byte entries, we align to an 8-byte boundary, | |
3270 | and split it into two 4-byte entries, because on 32-bit | |
3271 | host, 8-byte constants are treated as big num, thus | |
3272 | saved in "generic_bignum" which will be overwritten | |
3273 | by later assignments. | |
3274 | ||
3275 | We also need to make sure there is enough space for | |
3276 | the split. | |
3277 | ||
3278 | We also check to make sure the literal operand is a | |
3279 | constant number. */ | |
19f2f6a9 JW |
3280 | if (!(inst.reloc.exp.X_op == O_constant |
3281 | || inst.reloc.exp.X_op == O_big)) | |
8335d6aa JW |
3282 | { |
3283 | inst.error = _("invalid type for literal pool"); | |
3284 | return FAIL; | |
3285 | } | |
3286 | else if (pool_size & 0x7) | |
3287 | { | |
3288 | if ((entry + 2) >= MAX_LITERAL_POOL_SIZE) | |
3289 | { | |
3290 | inst.error = _("literal pool overflow"); | |
3291 | return FAIL; | |
3292 | } | |
3293 | ||
3294 | pool->literals[entry] = inst.reloc.exp; | |
3295 | pool->literals[entry].X_add_number = 0; | |
3296 | pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4; | |
3297 | pool->next_free_entry += 1; | |
3298 | pool_size += 4; | |
3299 | } | |
3300 | else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE) | |
3301 | { | |
3302 | inst.error = _("literal pool overflow"); | |
3303 | return FAIL; | |
3304 | } | |
3305 | ||
3306 | pool->literals[entry] = inst.reloc.exp; | |
3307 | pool->literals[entry].X_op = O_constant; | |
3308 | pool->literals[entry].X_add_number = imm1; | |
3309 | pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned; | |
3310 | pool->literals[entry++].X_md = 4; | |
3311 | pool->literals[entry] = inst.reloc.exp; | |
3312 | pool->literals[entry].X_op = O_constant; | |
3313 | pool->literals[entry].X_add_number = imm2; | |
3314 | pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned; | |
3315 | pool->literals[entry].X_md = 4; | |
3316 | pool->alignment = 3; | |
3317 | pool->next_free_entry += 1; | |
3318 | } | |
3319 | else | |
3320 | { | |
3321 | pool->literals[entry] = inst.reloc.exp; | |
3322 | pool->literals[entry].X_md = 4; | |
3323 | } | |
3324 | ||
a8040cf2 NC |
3325 | #ifdef OBJ_ELF |
3326 | /* PR ld/12974: Record the location of the first source line to reference | |
3327 | this entry in the literal pool. If it turns out during linking that the | |
3328 | symbol does not exist we will be able to give an accurate line number for | |
3329 | the (first use of the) missing reference. */ | |
3330 | if (debug_type == DEBUG_DWARF2) | |
3331 | dwarf2_where (pool->locs + entry); | |
3332 | #endif | |
c19d1205 ZW |
3333 | pool->next_free_entry += 1; |
3334 | } | |
8335d6aa JW |
3335 | else if (padding_slot_p) |
3336 | { | |
3337 | pool->literals[entry] = inst.reloc.exp; | |
3338 | pool->literals[entry].X_md = nbytes; | |
3339 | } | |
b99bd4ef | 3340 | |
c19d1205 | 3341 | inst.reloc.exp.X_op = O_symbol; |
8335d6aa | 3342 | inst.reloc.exp.X_add_number = pool_size; |
c19d1205 | 3343 | inst.reloc.exp.X_add_symbol = pool->symbol; |
b99bd4ef | 3344 | |
c19d1205 | 3345 | return SUCCESS; |
b99bd4ef NC |
3346 | } |
3347 | ||
2e6976a8 DG |
3348 | bfd_boolean |
3349 | tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED, const char * rest) | |
3350 | { | |
3351 | bfd_boolean ret = TRUE; | |
3352 | ||
3353 | if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME) | |
3354 | { | |
3355 | const char *label = rest; | |
3356 | ||
3357 | while (!is_end_of_line[(int) label[-1]]) | |
3358 | --label; | |
3359 | ||
3360 | if (*label == '.') | |
3361 | { | |
3362 | as_bad (_("Invalid label '%s'"), label); | |
3363 | ret = FALSE; | |
3364 | } | |
3365 | ||
3366 | asmfunc_debug (label); | |
3367 | ||
3368 | asmfunc_state = WAITING_ENDASMFUNC; | |
3369 | } | |
3370 | ||
3371 | return ret; | |
3372 | } | |
3373 | ||
c19d1205 ZW |
3374 | /* Can't use symbol_new here, so have to create a symbol and then at |
3375 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 3376 | |
c19d1205 ZW |
3377 | static void |
3378 | symbol_locate (symbolS * symbolP, | |
3379 | const char * name, /* It is copied, the caller can modify. */ | |
3380 | segT segment, /* Segment identifier (SEG_<something>). */ | |
3381 | valueT valu, /* Symbol value. */ | |
3382 | fragS * frag) /* Associated fragment. */ | |
3383 | { | |
e57e6ddc | 3384 | size_t name_length; |
c19d1205 | 3385 | char * preserved_copy_of_name; |
e16bb312 | 3386 | |
c19d1205 ZW |
3387 | name_length = strlen (name) + 1; /* +1 for \0. */ |
3388 | obstack_grow (¬es, name, name_length); | |
21d799b5 | 3389 | preserved_copy_of_name = (char *) obstack_finish (¬es); |
e16bb312 | 3390 | |
c19d1205 ZW |
3391 | #ifdef tc_canonicalize_symbol_name |
3392 | preserved_copy_of_name = | |
3393 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
3394 | #endif | |
b99bd4ef | 3395 | |
c19d1205 | 3396 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 3397 | |
c19d1205 ZW |
3398 | S_SET_SEGMENT (symbolP, segment); |
3399 | S_SET_VALUE (symbolP, valu); | |
3400 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 3401 | |
c19d1205 | 3402 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 3403 | |
c19d1205 ZW |
3404 | /* Link to end of symbol chain. */ |
3405 | { | |
3406 | extern int symbol_table_frozen; | |
b99bd4ef | 3407 | |
c19d1205 ZW |
3408 | if (symbol_table_frozen) |
3409 | abort (); | |
3410 | } | |
b99bd4ef | 3411 | |
c19d1205 | 3412 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 3413 | |
c19d1205 | 3414 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 3415 | |
c19d1205 ZW |
3416 | #ifdef tc_symbol_new_hook |
3417 | tc_symbol_new_hook (symbolP); | |
3418 | #endif | |
3419 | ||
3420 | #ifdef DEBUG_SYMS | |
3421 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
3422 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
3423 | } |
3424 | ||
c19d1205 ZW |
3425 | static void |
3426 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 3427 | { |
c19d1205 ZW |
3428 | unsigned int entry; |
3429 | literal_pool * pool; | |
3430 | char sym_name[20]; | |
b99bd4ef | 3431 | |
c19d1205 ZW |
3432 | pool = find_literal_pool (); |
3433 | if (pool == NULL | |
3434 | || pool->symbol == NULL | |
3435 | || pool->next_free_entry == 0) | |
3436 | return; | |
b99bd4ef | 3437 | |
c19d1205 ZW |
3438 | /* Align pool as you have word accesses. |
3439 | Only make a frag if we have to. */ | |
3440 | if (!need_pass_2) | |
8335d6aa | 3441 | frag_align (pool->alignment, 0, 0); |
b99bd4ef | 3442 | |
c19d1205 | 3443 | record_alignment (now_seg, 2); |
b99bd4ef | 3444 | |
aaca88ef | 3445 | #ifdef OBJ_ELF |
47fc6e36 WN |
3446 | seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA; |
3447 | make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now); | |
aaca88ef | 3448 | #endif |
c19d1205 | 3449 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 3450 | |
c19d1205 ZW |
3451 | symbol_locate (pool->symbol, sym_name, now_seg, |
3452 | (valueT) frag_now_fix (), frag_now); | |
3453 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 3454 | |
c19d1205 | 3455 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 3456 | |
c19d1205 ZW |
3457 | #if defined OBJ_COFF || defined OBJ_ELF |
3458 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
3459 | #endif | |
6c43fab6 | 3460 | |
c19d1205 | 3461 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
a8040cf2 NC |
3462 | { |
3463 | #ifdef OBJ_ELF | |
3464 | if (debug_type == DEBUG_DWARF2) | |
3465 | dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry); | |
3466 | #endif | |
3467 | /* First output the expression in the instruction to the pool. */ | |
8335d6aa JW |
3468 | emit_expr (&(pool->literals[entry]), |
3469 | pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK); | |
a8040cf2 | 3470 | } |
b99bd4ef | 3471 | |
c19d1205 ZW |
3472 | /* Mark the pool as empty. */ |
3473 | pool->next_free_entry = 0; | |
3474 | pool->symbol = NULL; | |
b99bd4ef NC |
3475 | } |
3476 | ||
c19d1205 ZW |
3477 | #ifdef OBJ_ELF |
3478 | /* Forward declarations for functions below, in the MD interface | |
3479 | section. */ | |
3480 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
3481 | static valueT create_unwind_entry (int); | |
3482 | static void start_unwind_section (const segT, int); | |
3483 | static void add_unwind_opcode (valueT, int); | |
3484 | static void flush_pending_unwind (void); | |
b99bd4ef | 3485 | |
c19d1205 | 3486 | /* Directives: Data. */ |
b99bd4ef | 3487 | |
c19d1205 ZW |
3488 | static void |
3489 | s_arm_elf_cons (int nbytes) | |
3490 | { | |
3491 | expressionS exp; | |
b99bd4ef | 3492 | |
c19d1205 ZW |
3493 | #ifdef md_flush_pending_output |
3494 | md_flush_pending_output (); | |
3495 | #endif | |
b99bd4ef | 3496 | |
c19d1205 | 3497 | if (is_it_end_of_statement ()) |
b99bd4ef | 3498 | { |
c19d1205 ZW |
3499 | demand_empty_rest_of_line (); |
3500 | return; | |
b99bd4ef NC |
3501 | } |
3502 | ||
c19d1205 ZW |
3503 | #ifdef md_cons_align |
3504 | md_cons_align (nbytes); | |
3505 | #endif | |
b99bd4ef | 3506 | |
c19d1205 ZW |
3507 | mapping_state (MAP_DATA); |
3508 | do | |
b99bd4ef | 3509 | { |
c19d1205 ZW |
3510 | int reloc; |
3511 | char *base = input_line_pointer; | |
b99bd4ef | 3512 | |
c19d1205 | 3513 | expression (& exp); |
b99bd4ef | 3514 | |
c19d1205 ZW |
3515 | if (exp.X_op != O_symbol) |
3516 | emit_expr (&exp, (unsigned int) nbytes); | |
3517 | else | |
3518 | { | |
3519 | char *before_reloc = input_line_pointer; | |
3520 | reloc = parse_reloc (&input_line_pointer); | |
3521 | if (reloc == -1) | |
3522 | { | |
3523 | as_bad (_("unrecognized relocation suffix")); | |
3524 | ignore_rest_of_line (); | |
3525 | return; | |
3526 | } | |
3527 | else if (reloc == BFD_RELOC_UNUSED) | |
3528 | emit_expr (&exp, (unsigned int) nbytes); | |
3529 | else | |
3530 | { | |
21d799b5 | 3531 | reloc_howto_type *howto = (reloc_howto_type *) |
477330fc RM |
3532 | bfd_reloc_type_lookup (stdoutput, |
3533 | (bfd_reloc_code_real_type) reloc); | |
c19d1205 | 3534 | int size = bfd_get_reloc_size (howto); |
b99bd4ef | 3535 | |
2fc8bdac ZW |
3536 | if (reloc == BFD_RELOC_ARM_PLT32) |
3537 | { | |
3538 | as_bad (_("(plt) is only valid on branch targets")); | |
3539 | reloc = BFD_RELOC_UNUSED; | |
3540 | size = 0; | |
3541 | } | |
3542 | ||
c19d1205 | 3543 | if (size > nbytes) |
2fc8bdac | 3544 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
3545 | howto->name, nbytes); |
3546 | else | |
3547 | { | |
3548 | /* We've parsed an expression stopping at O_symbol. | |
3549 | But there may be more expression left now that we | |
3550 | have parsed the relocation marker. Parse it again. | |
3551 | XXX Surely there is a cleaner way to do this. */ | |
3552 | char *p = input_line_pointer; | |
3553 | int offset; | |
21d799b5 | 3554 | char *save_buf = (char *) alloca (input_line_pointer - base); |
c19d1205 ZW |
3555 | memcpy (save_buf, base, input_line_pointer - base); |
3556 | memmove (base + (input_line_pointer - before_reloc), | |
3557 | base, before_reloc - base); | |
3558 | ||
3559 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
3560 | expression (&exp); | |
3561 | memcpy (base, save_buf, p - base); | |
3562 | ||
3563 | offset = nbytes - size; | |
4b1a927e AM |
3564 | p = frag_more (nbytes); |
3565 | memset (p, 0, nbytes); | |
c19d1205 | 3566 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, |
21d799b5 | 3567 | size, &exp, 0, (enum bfd_reloc_code_real) reloc); |
c19d1205 ZW |
3568 | } |
3569 | } | |
3570 | } | |
b99bd4ef | 3571 | } |
c19d1205 | 3572 | while (*input_line_pointer++ == ','); |
b99bd4ef | 3573 | |
c19d1205 ZW |
3574 | /* Put terminator back into stream. */ |
3575 | input_line_pointer --; | |
3576 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
3577 | } |
3578 | ||
c921be7d NC |
3579 | /* Emit an expression containing a 32-bit thumb instruction. |
3580 | Implementation based on put_thumb32_insn. */ | |
3581 | ||
3582 | static void | |
3583 | emit_thumb32_expr (expressionS * exp) | |
3584 | { | |
3585 | expressionS exp_high = *exp; | |
3586 | ||
3587 | exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; | |
3588 | emit_expr (& exp_high, (unsigned int) THUMB_SIZE); | |
3589 | exp->X_add_number &= 0xffff; | |
3590 | emit_expr (exp, (unsigned int) THUMB_SIZE); | |
3591 | } | |
3592 | ||
3593 | /* Guess the instruction size based on the opcode. */ | |
3594 | ||
3595 | static int | |
3596 | thumb_insn_size (int opcode) | |
3597 | { | |
3598 | if ((unsigned int) opcode < 0xe800u) | |
3599 | return 2; | |
3600 | else if ((unsigned int) opcode >= 0xe8000000u) | |
3601 | return 4; | |
3602 | else | |
3603 | return 0; | |
3604 | } | |
3605 | ||
3606 | static bfd_boolean | |
3607 | emit_insn (expressionS *exp, int nbytes) | |
3608 | { | |
3609 | int size = 0; | |
3610 | ||
3611 | if (exp->X_op == O_constant) | |
3612 | { | |
3613 | size = nbytes; | |
3614 | ||
3615 | if (size == 0) | |
3616 | size = thumb_insn_size (exp->X_add_number); | |
3617 | ||
3618 | if (size != 0) | |
3619 | { | |
3620 | if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) | |
3621 | { | |
3622 | as_bad (_(".inst.n operand too big. "\ | |
3623 | "Use .inst.w instead")); | |
3624 | size = 0; | |
3625 | } | |
3626 | else | |
3627 | { | |
3628 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
3629 | set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0); | |
3630 | else | |
3631 | set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); | |
3632 | ||
3633 | if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) | |
3634 | emit_thumb32_expr (exp); | |
3635 | else | |
3636 | emit_expr (exp, (unsigned int) size); | |
3637 | ||
3638 | it_fsm_post_encode (); | |
3639 | } | |
3640 | } | |
3641 | else | |
3642 | as_bad (_("cannot determine Thumb instruction size. " \ | |
3643 | "Use .inst.n/.inst.w instead")); | |
3644 | } | |
3645 | else | |
3646 | as_bad (_("constant expression required")); | |
3647 | ||
3648 | return (size != 0); | |
3649 | } | |
3650 | ||
3651 | /* Like s_arm_elf_cons but do not use md_cons_align and | |
3652 | set the mapping state to MAP_ARM/MAP_THUMB. */ | |
3653 | ||
3654 | static void | |
3655 | s_arm_elf_inst (int nbytes) | |
3656 | { | |
3657 | if (is_it_end_of_statement ()) | |
3658 | { | |
3659 | demand_empty_rest_of_line (); | |
3660 | return; | |
3661 | } | |
3662 | ||
3663 | /* Calling mapping_state () here will not change ARM/THUMB, | |
3664 | but will ensure not to be in DATA state. */ | |
3665 | ||
3666 | if (thumb_mode) | |
3667 | mapping_state (MAP_THUMB); | |
3668 | else | |
3669 | { | |
3670 | if (nbytes != 0) | |
3671 | { | |
3672 | as_bad (_("width suffixes are invalid in ARM mode")); | |
3673 | ignore_rest_of_line (); | |
3674 | return; | |
3675 | } | |
3676 | ||
3677 | nbytes = 4; | |
3678 | ||
3679 | mapping_state (MAP_ARM); | |
3680 | } | |
3681 | ||
3682 | do | |
3683 | { | |
3684 | expressionS exp; | |
3685 | ||
3686 | expression (& exp); | |
3687 | ||
3688 | if (! emit_insn (& exp, nbytes)) | |
3689 | { | |
3690 | ignore_rest_of_line (); | |
3691 | return; | |
3692 | } | |
3693 | } | |
3694 | while (*input_line_pointer++ == ','); | |
3695 | ||
3696 | /* Put terminator back into stream. */ | |
3697 | input_line_pointer --; | |
3698 | demand_empty_rest_of_line (); | |
3699 | } | |
b99bd4ef | 3700 | |
c19d1205 | 3701 | /* Parse a .rel31 directive. */ |
b99bd4ef | 3702 | |
c19d1205 ZW |
3703 | static void |
3704 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
3705 | { | |
3706 | expressionS exp; | |
3707 | char *p; | |
3708 | valueT highbit; | |
b99bd4ef | 3709 | |
c19d1205 ZW |
3710 | highbit = 0; |
3711 | if (*input_line_pointer == '1') | |
3712 | highbit = 0x80000000; | |
3713 | else if (*input_line_pointer != '0') | |
3714 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 3715 | |
c19d1205 ZW |
3716 | input_line_pointer++; |
3717 | if (*input_line_pointer != ',') | |
3718 | as_bad (_("missing comma")); | |
3719 | input_line_pointer++; | |
b99bd4ef | 3720 | |
c19d1205 ZW |
3721 | #ifdef md_flush_pending_output |
3722 | md_flush_pending_output (); | |
3723 | #endif | |
b99bd4ef | 3724 | |
c19d1205 ZW |
3725 | #ifdef md_cons_align |
3726 | md_cons_align (4); | |
3727 | #endif | |
b99bd4ef | 3728 | |
c19d1205 | 3729 | mapping_state (MAP_DATA); |
b99bd4ef | 3730 | |
c19d1205 | 3731 | expression (&exp); |
b99bd4ef | 3732 | |
c19d1205 ZW |
3733 | p = frag_more (4); |
3734 | md_number_to_chars (p, highbit, 4); | |
3735 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
3736 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 3737 | |
c19d1205 | 3738 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3739 | } |
3740 | ||
c19d1205 | 3741 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 3742 | |
c19d1205 | 3743 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 3744 | |
c19d1205 ZW |
3745 | static void |
3746 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
3747 | { | |
3748 | demand_empty_rest_of_line (); | |
921e5f0a PB |
3749 | if (unwind.proc_start) |
3750 | { | |
c921be7d | 3751 | as_bad (_("duplicate .fnstart directive")); |
921e5f0a PB |
3752 | return; |
3753 | } | |
3754 | ||
c19d1205 ZW |
3755 | /* Mark the start of the function. */ |
3756 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 3757 | |
c19d1205 ZW |
3758 | /* Reset the rest of the unwind info. */ |
3759 | unwind.opcode_count = 0; | |
3760 | unwind.table_entry = NULL; | |
3761 | unwind.personality_routine = NULL; | |
3762 | unwind.personality_index = -1; | |
3763 | unwind.frame_size = 0; | |
3764 | unwind.fp_offset = 0; | |
fdfde340 | 3765 | unwind.fp_reg = REG_SP; |
c19d1205 ZW |
3766 | unwind.fp_used = 0; |
3767 | unwind.sp_restored = 0; | |
3768 | } | |
b99bd4ef | 3769 | |
b99bd4ef | 3770 | |
c19d1205 ZW |
3771 | /* Parse a handlerdata directive. Creates the exception handling table entry |
3772 | for the function. */ | |
b99bd4ef | 3773 | |
c19d1205 ZW |
3774 | static void |
3775 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
3776 | { | |
3777 | demand_empty_rest_of_line (); | |
921e5f0a | 3778 | if (!unwind.proc_start) |
c921be7d | 3779 | as_bad (MISSING_FNSTART); |
921e5f0a | 3780 | |
c19d1205 | 3781 | if (unwind.table_entry) |
6decc662 | 3782 | as_bad (_("duplicate .handlerdata directive")); |
f02232aa | 3783 | |
c19d1205 ZW |
3784 | create_unwind_entry (1); |
3785 | } | |
a737bd4d | 3786 | |
c19d1205 | 3787 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 3788 | |
c19d1205 ZW |
3789 | static void |
3790 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
3791 | { | |
3792 | long where; | |
3793 | char *ptr; | |
3794 | valueT val; | |
940b5ce0 | 3795 | unsigned int marked_pr_dependency; |
f02232aa | 3796 | |
c19d1205 | 3797 | demand_empty_rest_of_line (); |
f02232aa | 3798 | |
921e5f0a PB |
3799 | if (!unwind.proc_start) |
3800 | { | |
c921be7d | 3801 | as_bad (_(".fnend directive without .fnstart")); |
921e5f0a PB |
3802 | return; |
3803 | } | |
3804 | ||
c19d1205 ZW |
3805 | /* Add eh table entry. */ |
3806 | if (unwind.table_entry == NULL) | |
3807 | val = create_unwind_entry (0); | |
3808 | else | |
3809 | val = 0; | |
f02232aa | 3810 | |
c19d1205 ZW |
3811 | /* Add index table entry. This is two words. */ |
3812 | start_unwind_section (unwind.saved_seg, 1); | |
3813 | frag_align (2, 0, 0); | |
3814 | record_alignment (now_seg, 2); | |
b99bd4ef | 3815 | |
c19d1205 | 3816 | ptr = frag_more (8); |
5011093d | 3817 | memset (ptr, 0, 8); |
c19d1205 | 3818 | where = frag_now_fix () - 8; |
f02232aa | 3819 | |
c19d1205 ZW |
3820 | /* Self relative offset of the function start. */ |
3821 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
3822 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3823 | |
c19d1205 ZW |
3824 | /* Indicate dependency on EHABI-defined personality routines to the |
3825 | linker, if it hasn't been done already. */ | |
940b5ce0 DJ |
3826 | marked_pr_dependency |
3827 | = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; | |
c19d1205 ZW |
3828 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 |
3829 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
3830 | { | |
5f4273c7 NC |
3831 | static const char *const name[] = |
3832 | { | |
3833 | "__aeabi_unwind_cpp_pr0", | |
3834 | "__aeabi_unwind_cpp_pr1", | |
3835 | "__aeabi_unwind_cpp_pr2" | |
3836 | }; | |
c19d1205 ZW |
3837 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); |
3838 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
c19d1205 | 3839 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency |
940b5ce0 | 3840 | |= 1 << unwind.personality_index; |
c19d1205 | 3841 | } |
f02232aa | 3842 | |
c19d1205 ZW |
3843 | if (val) |
3844 | /* Inline exception table entry. */ | |
3845 | md_number_to_chars (ptr + 4, val, 4); | |
3846 | else | |
3847 | /* Self relative offset of the table entry. */ | |
3848 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
3849 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3850 | |
c19d1205 ZW |
3851 | /* Restore the original section. */ |
3852 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
921e5f0a PB |
3853 | |
3854 | unwind.proc_start = NULL; | |
c19d1205 | 3855 | } |
f02232aa | 3856 | |
f02232aa | 3857 | |
c19d1205 | 3858 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 3859 | |
c19d1205 ZW |
3860 | static void |
3861 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
3862 | { | |
3863 | demand_empty_rest_of_line (); | |
921e5f0a | 3864 | if (!unwind.proc_start) |
c921be7d | 3865 | as_bad (MISSING_FNSTART); |
921e5f0a | 3866 | |
c19d1205 ZW |
3867 | if (unwind.personality_routine || unwind.personality_index != -1) |
3868 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 3869 | |
c19d1205 ZW |
3870 | unwind.personality_index = -2; |
3871 | } | |
b99bd4ef | 3872 | |
b99bd4ef | 3873 | |
c19d1205 | 3874 | /* Parse a personalityindex directive. */ |
b99bd4ef | 3875 | |
c19d1205 ZW |
3876 | static void |
3877 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
3878 | { | |
3879 | expressionS exp; | |
b99bd4ef | 3880 | |
921e5f0a | 3881 | if (!unwind.proc_start) |
c921be7d | 3882 | as_bad (MISSING_FNSTART); |
921e5f0a | 3883 | |
c19d1205 ZW |
3884 | if (unwind.personality_routine || unwind.personality_index != -1) |
3885 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 3886 | |
c19d1205 | 3887 | expression (&exp); |
b99bd4ef | 3888 | |
c19d1205 ZW |
3889 | if (exp.X_op != O_constant |
3890 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 3891 | { |
c19d1205 ZW |
3892 | as_bad (_("bad personality routine number")); |
3893 | ignore_rest_of_line (); | |
3894 | return; | |
b99bd4ef NC |
3895 | } |
3896 | ||
c19d1205 | 3897 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 3898 | |
c19d1205 ZW |
3899 | demand_empty_rest_of_line (); |
3900 | } | |
e16bb312 | 3901 | |
e16bb312 | 3902 | |
c19d1205 | 3903 | /* Parse a personality directive. */ |
e16bb312 | 3904 | |
c19d1205 ZW |
3905 | static void |
3906 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
3907 | { | |
3908 | char *name, *p, c; | |
a737bd4d | 3909 | |
921e5f0a | 3910 | if (!unwind.proc_start) |
c921be7d | 3911 | as_bad (MISSING_FNSTART); |
921e5f0a | 3912 | |
c19d1205 ZW |
3913 | if (unwind.personality_routine || unwind.personality_index != -1) |
3914 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 3915 | |
c19d1205 ZW |
3916 | name = input_line_pointer; |
3917 | c = get_symbol_end (); | |
3918 | p = input_line_pointer; | |
3919 | unwind.personality_routine = symbol_find_or_make (name); | |
3920 | *p = c; | |
3921 | demand_empty_rest_of_line (); | |
3922 | } | |
e16bb312 | 3923 | |
e16bb312 | 3924 | |
c19d1205 | 3925 | /* Parse a directive saving core registers. */ |
e16bb312 | 3926 | |
c19d1205 ZW |
3927 | static void |
3928 | s_arm_unwind_save_core (void) | |
e16bb312 | 3929 | { |
c19d1205 ZW |
3930 | valueT op; |
3931 | long range; | |
3932 | int n; | |
e16bb312 | 3933 | |
c19d1205 ZW |
3934 | range = parse_reg_list (&input_line_pointer); |
3935 | if (range == FAIL) | |
e16bb312 | 3936 | { |
c19d1205 ZW |
3937 | as_bad (_("expected register list")); |
3938 | ignore_rest_of_line (); | |
3939 | return; | |
3940 | } | |
e16bb312 | 3941 | |
c19d1205 | 3942 | demand_empty_rest_of_line (); |
e16bb312 | 3943 | |
c19d1205 ZW |
3944 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
3945 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
3946 | ip because it is clobbered by calls. */ | |
3947 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
3948 | && (range & 0x3000) == 0x1000) | |
3949 | { | |
3950 | unwind.opcode_count--; | |
3951 | unwind.sp_restored = 0; | |
3952 | range = (range | 0x2000) & ~0x1000; | |
3953 | unwind.pending_offset = 0; | |
3954 | } | |
e16bb312 | 3955 | |
01ae4198 DJ |
3956 | /* Pop r4-r15. */ |
3957 | if (range & 0xfff0) | |
c19d1205 | 3958 | { |
01ae4198 DJ |
3959 | /* See if we can use the short opcodes. These pop a block of up to 8 |
3960 | registers starting with r4, plus maybe r14. */ | |
3961 | for (n = 0; n < 8; n++) | |
3962 | { | |
3963 | /* Break at the first non-saved register. */ | |
3964 | if ((range & (1 << (n + 4))) == 0) | |
3965 | break; | |
3966 | } | |
3967 | /* See if there are any other bits set. */ | |
3968 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
3969 | { | |
3970 | /* Use the long form. */ | |
3971 | op = 0x8000 | ((range >> 4) & 0xfff); | |
3972 | add_unwind_opcode (op, 2); | |
3973 | } | |
0dd132b6 | 3974 | else |
01ae4198 DJ |
3975 | { |
3976 | /* Use the short form. */ | |
3977 | if (range & 0x4000) | |
3978 | op = 0xa8; /* Pop r14. */ | |
3979 | else | |
3980 | op = 0xa0; /* Do not pop r14. */ | |
3981 | op |= (n - 1); | |
3982 | add_unwind_opcode (op, 1); | |
3983 | } | |
c19d1205 | 3984 | } |
0dd132b6 | 3985 | |
c19d1205 ZW |
3986 | /* Pop r0-r3. */ |
3987 | if (range & 0xf) | |
3988 | { | |
3989 | op = 0xb100 | (range & 0xf); | |
3990 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
3991 | } |
3992 | ||
c19d1205 ZW |
3993 | /* Record the number of bytes pushed. */ |
3994 | for (n = 0; n < 16; n++) | |
3995 | { | |
3996 | if (range & (1 << n)) | |
3997 | unwind.frame_size += 4; | |
3998 | } | |
0dd132b6 NC |
3999 | } |
4000 | ||
c19d1205 ZW |
4001 | |
4002 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
4003 | |
4004 | static void | |
c19d1205 | 4005 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 4006 | { |
c19d1205 ZW |
4007 | expressionS exp; |
4008 | int num_regs; | |
4009 | valueT op; | |
b99bd4ef | 4010 | |
c19d1205 ZW |
4011 | /* Get Number of registers to transfer. */ |
4012 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4013 | expression (&exp); | |
4014 | else | |
4015 | exp.X_op = O_illegal; | |
b99bd4ef | 4016 | |
c19d1205 | 4017 | if (exp.X_op != O_constant) |
b99bd4ef | 4018 | { |
c19d1205 ZW |
4019 | as_bad (_("expected , <constant>")); |
4020 | ignore_rest_of_line (); | |
b99bd4ef NC |
4021 | return; |
4022 | } | |
4023 | ||
c19d1205 ZW |
4024 | num_regs = exp.X_add_number; |
4025 | ||
4026 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 4027 | { |
c19d1205 ZW |
4028 | as_bad (_("number of registers must be in the range [1:4]")); |
4029 | ignore_rest_of_line (); | |
b99bd4ef NC |
4030 | return; |
4031 | } | |
4032 | ||
c19d1205 | 4033 | demand_empty_rest_of_line (); |
b99bd4ef | 4034 | |
c19d1205 ZW |
4035 | if (reg == 4) |
4036 | { | |
4037 | /* Short form. */ | |
4038 | op = 0xb4 | (num_regs - 1); | |
4039 | add_unwind_opcode (op, 1); | |
4040 | } | |
b99bd4ef NC |
4041 | else |
4042 | { | |
c19d1205 ZW |
4043 | /* Long form. */ |
4044 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
4045 | add_unwind_opcode (op, 2); | |
b99bd4ef | 4046 | } |
c19d1205 | 4047 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
4048 | } |
4049 | ||
c19d1205 | 4050 | |
fa073d69 MS |
4051 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
4052 | ||
4053 | static void | |
4054 | s_arm_unwind_save_vfp_armv6 (void) | |
4055 | { | |
4056 | int count; | |
4057 | unsigned int start; | |
4058 | valueT op; | |
4059 | int num_vfpv3_regs = 0; | |
4060 | int num_regs_below_16; | |
4061 | ||
4062 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); | |
4063 | if (count == FAIL) | |
4064 | { | |
4065 | as_bad (_("expected register list")); | |
4066 | ignore_rest_of_line (); | |
4067 | return; | |
4068 | } | |
4069 | ||
4070 | demand_empty_rest_of_line (); | |
4071 | ||
4072 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather | |
4073 | than FSTMX/FLDMX-style ones). */ | |
4074 | ||
4075 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ | |
4076 | if (start >= 16) | |
4077 | num_vfpv3_regs = count; | |
4078 | else if (start + count > 16) | |
4079 | num_vfpv3_regs = start + count - 16; | |
4080 | ||
4081 | if (num_vfpv3_regs > 0) | |
4082 | { | |
4083 | int start_offset = start > 16 ? start - 16 : 0; | |
4084 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); | |
4085 | add_unwind_opcode (op, 2); | |
4086 | } | |
4087 | ||
4088 | /* Generate opcode for registers numbered in the range 0 .. 15. */ | |
4089 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; | |
9c2799c2 | 4090 | gas_assert (num_regs_below_16 + num_vfpv3_regs == count); |
fa073d69 MS |
4091 | if (num_regs_below_16 > 0) |
4092 | { | |
4093 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); | |
4094 | add_unwind_opcode (op, 2); | |
4095 | } | |
4096 | ||
4097 | unwind.frame_size += count * 8; | |
4098 | } | |
4099 | ||
4100 | ||
4101 | /* Parse a directive saving VFP registers for pre-ARMv6. */ | |
b99bd4ef NC |
4102 | |
4103 | static void | |
c19d1205 | 4104 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 4105 | { |
c19d1205 | 4106 | int count; |
ca3f61f7 | 4107 | unsigned int reg; |
c19d1205 | 4108 | valueT op; |
b99bd4ef | 4109 | |
5287ad62 | 4110 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); |
c19d1205 | 4111 | if (count == FAIL) |
b99bd4ef | 4112 | { |
c19d1205 ZW |
4113 | as_bad (_("expected register list")); |
4114 | ignore_rest_of_line (); | |
b99bd4ef NC |
4115 | return; |
4116 | } | |
4117 | ||
c19d1205 | 4118 | demand_empty_rest_of_line (); |
b99bd4ef | 4119 | |
c19d1205 | 4120 | if (reg == 8) |
b99bd4ef | 4121 | { |
c19d1205 ZW |
4122 | /* Short form. */ |
4123 | op = 0xb8 | (count - 1); | |
4124 | add_unwind_opcode (op, 1); | |
b99bd4ef | 4125 | } |
c19d1205 | 4126 | else |
b99bd4ef | 4127 | { |
c19d1205 ZW |
4128 | /* Long form. */ |
4129 | op = 0xb300 | (reg << 4) | (count - 1); | |
4130 | add_unwind_opcode (op, 2); | |
b99bd4ef | 4131 | } |
c19d1205 ZW |
4132 | unwind.frame_size += count * 8 + 4; |
4133 | } | |
b99bd4ef | 4134 | |
b99bd4ef | 4135 | |
c19d1205 ZW |
4136 | /* Parse a directive saving iWMMXt data registers. */ |
4137 | ||
4138 | static void | |
4139 | s_arm_unwind_save_mmxwr (void) | |
4140 | { | |
4141 | int reg; | |
4142 | int hi_reg; | |
4143 | int i; | |
4144 | unsigned mask = 0; | |
4145 | valueT op; | |
b99bd4ef | 4146 | |
c19d1205 ZW |
4147 | if (*input_line_pointer == '{') |
4148 | input_line_pointer++; | |
b99bd4ef | 4149 | |
c19d1205 | 4150 | do |
b99bd4ef | 4151 | { |
dcbf9037 | 4152 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 4153 | |
c19d1205 | 4154 | if (reg == FAIL) |
b99bd4ef | 4155 | { |
9b7132d3 | 4156 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 | 4157 | goto error; |
b99bd4ef NC |
4158 | } |
4159 | ||
c19d1205 ZW |
4160 | if (mask >> reg) |
4161 | as_tsktsk (_("register list not in ascending order")); | |
4162 | mask |= 1 << reg; | |
b99bd4ef | 4163 | |
c19d1205 ZW |
4164 | if (*input_line_pointer == '-') |
4165 | { | |
4166 | input_line_pointer++; | |
dcbf9037 | 4167 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
c19d1205 ZW |
4168 | if (hi_reg == FAIL) |
4169 | { | |
9b7132d3 | 4170 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 ZW |
4171 | goto error; |
4172 | } | |
4173 | else if (reg >= hi_reg) | |
4174 | { | |
4175 | as_bad (_("bad register range")); | |
4176 | goto error; | |
4177 | } | |
4178 | for (; reg < hi_reg; reg++) | |
4179 | mask |= 1 << reg; | |
4180 | } | |
4181 | } | |
4182 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 4183 | |
d996d970 | 4184 | skip_past_char (&input_line_pointer, '}'); |
b99bd4ef | 4185 | |
c19d1205 | 4186 | demand_empty_rest_of_line (); |
b99bd4ef | 4187 | |
708587a4 | 4188 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4189 | the list. */ |
4190 | flush_pending_unwind (); | |
b99bd4ef | 4191 | |
c19d1205 | 4192 | for (i = 0; i < 16; i++) |
b99bd4ef | 4193 | { |
c19d1205 ZW |
4194 | if (mask & (1 << i)) |
4195 | unwind.frame_size += 8; | |
b99bd4ef NC |
4196 | } |
4197 | ||
c19d1205 ZW |
4198 | /* Attempt to combine with a previous opcode. We do this because gcc |
4199 | likes to output separate unwind directives for a single block of | |
4200 | registers. */ | |
4201 | if (unwind.opcode_count > 0) | |
b99bd4ef | 4202 | { |
c19d1205 ZW |
4203 | i = unwind.opcodes[unwind.opcode_count - 1]; |
4204 | if ((i & 0xf8) == 0xc0) | |
4205 | { | |
4206 | i &= 7; | |
4207 | /* Only merge if the blocks are contiguous. */ | |
4208 | if (i < 6) | |
4209 | { | |
4210 | if ((mask & 0xfe00) == (1 << 9)) | |
4211 | { | |
4212 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
4213 | unwind.opcode_count--; | |
4214 | } | |
4215 | } | |
4216 | else if (i == 6 && unwind.opcode_count >= 2) | |
4217 | { | |
4218 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
4219 | reg = i >> 4; | |
4220 | i &= 0xf; | |
b99bd4ef | 4221 | |
c19d1205 ZW |
4222 | op = 0xffff << (reg - 1); |
4223 | if (reg > 0 | |
87a1fd79 | 4224 | && ((mask & op) == (1u << (reg - 1)))) |
c19d1205 ZW |
4225 | { |
4226 | op = (1 << (reg + i + 1)) - 1; | |
4227 | op &= ~((1 << reg) - 1); | |
4228 | mask |= op; | |
4229 | unwind.opcode_count -= 2; | |
4230 | } | |
4231 | } | |
4232 | } | |
b99bd4ef NC |
4233 | } |
4234 | ||
c19d1205 ZW |
4235 | hi_reg = 15; |
4236 | /* We want to generate opcodes in the order the registers have been | |
4237 | saved, ie. descending order. */ | |
4238 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 4239 | { |
c19d1205 ZW |
4240 | /* Save registers in blocks. */ |
4241 | if (reg < 0 | |
4242 | || !(mask & (1 << reg))) | |
4243 | { | |
4244 | /* We found an unsaved reg. Generate opcodes to save the | |
5f4273c7 | 4245 | preceding block. */ |
c19d1205 ZW |
4246 | if (reg != hi_reg) |
4247 | { | |
4248 | if (reg == 9) | |
4249 | { | |
4250 | /* Short form. */ | |
4251 | op = 0xc0 | (hi_reg - 10); | |
4252 | add_unwind_opcode (op, 1); | |
4253 | } | |
4254 | else | |
4255 | { | |
4256 | /* Long form. */ | |
4257 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
4258 | add_unwind_opcode (op, 2); | |
4259 | } | |
4260 | } | |
4261 | hi_reg = reg - 1; | |
4262 | } | |
b99bd4ef NC |
4263 | } |
4264 | ||
c19d1205 ZW |
4265 | return; |
4266 | error: | |
4267 | ignore_rest_of_line (); | |
b99bd4ef NC |
4268 | } |
4269 | ||
4270 | static void | |
c19d1205 | 4271 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 4272 | { |
c19d1205 ZW |
4273 | int reg; |
4274 | int hi_reg; | |
4275 | unsigned mask = 0; | |
4276 | valueT op; | |
b99bd4ef | 4277 | |
c19d1205 ZW |
4278 | if (*input_line_pointer == '{') |
4279 | input_line_pointer++; | |
b99bd4ef | 4280 | |
477330fc RM |
4281 | skip_whitespace (input_line_pointer); |
4282 | ||
c19d1205 | 4283 | do |
b99bd4ef | 4284 | { |
dcbf9037 | 4285 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 4286 | |
c19d1205 ZW |
4287 | if (reg == FAIL) |
4288 | { | |
9b7132d3 | 4289 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4290 | goto error; |
4291 | } | |
b99bd4ef | 4292 | |
c19d1205 ZW |
4293 | reg -= 8; |
4294 | if (mask >> reg) | |
4295 | as_tsktsk (_("register list not in ascending order")); | |
4296 | mask |= 1 << reg; | |
b99bd4ef | 4297 | |
c19d1205 ZW |
4298 | if (*input_line_pointer == '-') |
4299 | { | |
4300 | input_line_pointer++; | |
dcbf9037 | 4301 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
c19d1205 ZW |
4302 | if (hi_reg == FAIL) |
4303 | { | |
9b7132d3 | 4304 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4305 | goto error; |
4306 | } | |
4307 | else if (reg >= hi_reg) | |
4308 | { | |
4309 | as_bad (_("bad register range")); | |
4310 | goto error; | |
4311 | } | |
4312 | for (; reg < hi_reg; reg++) | |
4313 | mask |= 1 << reg; | |
4314 | } | |
b99bd4ef | 4315 | } |
c19d1205 | 4316 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 4317 | |
d996d970 | 4318 | skip_past_char (&input_line_pointer, '}'); |
b99bd4ef | 4319 | |
c19d1205 ZW |
4320 | demand_empty_rest_of_line (); |
4321 | ||
708587a4 | 4322 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4323 | the list. */ |
4324 | flush_pending_unwind (); | |
b99bd4ef | 4325 | |
c19d1205 | 4326 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 4327 | { |
c19d1205 ZW |
4328 | if (mask & (1 << reg)) |
4329 | unwind.frame_size += 4; | |
b99bd4ef | 4330 | } |
c19d1205 ZW |
4331 | op = 0xc700 | mask; |
4332 | add_unwind_opcode (op, 2); | |
4333 | return; | |
4334 | error: | |
4335 | ignore_rest_of_line (); | |
b99bd4ef NC |
4336 | } |
4337 | ||
c19d1205 | 4338 | |
fa073d69 MS |
4339 | /* Parse an unwind_save directive. |
4340 | If the argument is non-zero, this is a .vsave directive. */ | |
c19d1205 | 4341 | |
b99bd4ef | 4342 | static void |
fa073d69 | 4343 | s_arm_unwind_save (int arch_v6) |
b99bd4ef | 4344 | { |
c19d1205 ZW |
4345 | char *peek; |
4346 | struct reg_entry *reg; | |
4347 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 4348 | |
921e5f0a | 4349 | if (!unwind.proc_start) |
c921be7d | 4350 | as_bad (MISSING_FNSTART); |
921e5f0a | 4351 | |
c19d1205 ZW |
4352 | /* Figure out what sort of save we have. */ |
4353 | peek = input_line_pointer; | |
b99bd4ef | 4354 | |
c19d1205 | 4355 | if (*peek == '{') |
b99bd4ef | 4356 | { |
c19d1205 ZW |
4357 | had_brace = TRUE; |
4358 | peek++; | |
b99bd4ef NC |
4359 | } |
4360 | ||
c19d1205 | 4361 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 4362 | |
c19d1205 | 4363 | if (!reg) |
b99bd4ef | 4364 | { |
c19d1205 ZW |
4365 | as_bad (_("register expected")); |
4366 | ignore_rest_of_line (); | |
b99bd4ef NC |
4367 | return; |
4368 | } | |
4369 | ||
c19d1205 | 4370 | switch (reg->type) |
b99bd4ef | 4371 | { |
c19d1205 ZW |
4372 | case REG_TYPE_FN: |
4373 | if (had_brace) | |
4374 | { | |
4375 | as_bad (_("FPA .unwind_save does not take a register list")); | |
4376 | ignore_rest_of_line (); | |
4377 | return; | |
4378 | } | |
93ac2687 | 4379 | input_line_pointer = peek; |
c19d1205 | 4380 | s_arm_unwind_save_fpa (reg->number); |
b99bd4ef | 4381 | return; |
c19d1205 | 4382 | |
1f5afe1c NC |
4383 | case REG_TYPE_RN: |
4384 | s_arm_unwind_save_core (); | |
4385 | return; | |
4386 | ||
fa073d69 MS |
4387 | case REG_TYPE_VFD: |
4388 | if (arch_v6) | |
477330fc | 4389 | s_arm_unwind_save_vfp_armv6 (); |
fa073d69 | 4390 | else |
477330fc | 4391 | s_arm_unwind_save_vfp (); |
fa073d69 | 4392 | return; |
1f5afe1c NC |
4393 | |
4394 | case REG_TYPE_MMXWR: | |
4395 | s_arm_unwind_save_mmxwr (); | |
4396 | return; | |
4397 | ||
4398 | case REG_TYPE_MMXWCG: | |
4399 | s_arm_unwind_save_mmxwcg (); | |
4400 | return; | |
c19d1205 ZW |
4401 | |
4402 | default: | |
4403 | as_bad (_(".unwind_save does not support this kind of register")); | |
4404 | ignore_rest_of_line (); | |
b99bd4ef | 4405 | } |
c19d1205 | 4406 | } |
b99bd4ef | 4407 | |
b99bd4ef | 4408 | |
c19d1205 ZW |
4409 | /* Parse an unwind_movsp directive. */ |
4410 | ||
4411 | static void | |
4412 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
4413 | { | |
4414 | int reg; | |
4415 | valueT op; | |
4fa3602b | 4416 | int offset; |
c19d1205 | 4417 | |
921e5f0a | 4418 | if (!unwind.proc_start) |
c921be7d | 4419 | as_bad (MISSING_FNSTART); |
921e5f0a | 4420 | |
dcbf9037 | 4421 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 | 4422 | if (reg == FAIL) |
b99bd4ef | 4423 | { |
9b7132d3 | 4424 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 | 4425 | ignore_rest_of_line (); |
b99bd4ef NC |
4426 | return; |
4427 | } | |
4fa3602b PB |
4428 | |
4429 | /* Optional constant. */ | |
4430 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4431 | { | |
4432 | if (immediate_for_directive (&offset) == FAIL) | |
4433 | return; | |
4434 | } | |
4435 | else | |
4436 | offset = 0; | |
4437 | ||
c19d1205 | 4438 | demand_empty_rest_of_line (); |
b99bd4ef | 4439 | |
c19d1205 | 4440 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 4441 | { |
c19d1205 | 4442 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
4443 | return; |
4444 | } | |
4445 | ||
c19d1205 ZW |
4446 | if (unwind.fp_reg != REG_SP) |
4447 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 4448 | |
c19d1205 ZW |
4449 | /* Generate opcode to restore the value. */ |
4450 | op = 0x90 | reg; | |
4451 | add_unwind_opcode (op, 1); | |
4452 | ||
4453 | /* Record the information for later. */ | |
4454 | unwind.fp_reg = reg; | |
4fa3602b | 4455 | unwind.fp_offset = unwind.frame_size - offset; |
c19d1205 | 4456 | unwind.sp_restored = 1; |
b05fe5cf ZW |
4457 | } |
4458 | ||
c19d1205 ZW |
4459 | /* Parse an unwind_pad directive. */ |
4460 | ||
b05fe5cf | 4461 | static void |
c19d1205 | 4462 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 4463 | { |
c19d1205 | 4464 | int offset; |
b05fe5cf | 4465 | |
921e5f0a | 4466 | if (!unwind.proc_start) |
c921be7d | 4467 | as_bad (MISSING_FNSTART); |
921e5f0a | 4468 | |
c19d1205 ZW |
4469 | if (immediate_for_directive (&offset) == FAIL) |
4470 | return; | |
b99bd4ef | 4471 | |
c19d1205 ZW |
4472 | if (offset & 3) |
4473 | { | |
4474 | as_bad (_("stack increment must be multiple of 4")); | |
4475 | ignore_rest_of_line (); | |
4476 | return; | |
4477 | } | |
b99bd4ef | 4478 | |
c19d1205 ZW |
4479 | /* Don't generate any opcodes, just record the details for later. */ |
4480 | unwind.frame_size += offset; | |
4481 | unwind.pending_offset += offset; | |
4482 | ||
4483 | demand_empty_rest_of_line (); | |
4484 | } | |
4485 | ||
4486 | /* Parse an unwind_setfp directive. */ | |
4487 | ||
4488 | static void | |
4489 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 4490 | { |
c19d1205 ZW |
4491 | int sp_reg; |
4492 | int fp_reg; | |
4493 | int offset; | |
4494 | ||
921e5f0a | 4495 | if (!unwind.proc_start) |
c921be7d | 4496 | as_bad (MISSING_FNSTART); |
921e5f0a | 4497 | |
dcbf9037 | 4498 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 ZW |
4499 | if (skip_past_comma (&input_line_pointer) == FAIL) |
4500 | sp_reg = FAIL; | |
4501 | else | |
dcbf9037 | 4502 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
b99bd4ef | 4503 | |
c19d1205 ZW |
4504 | if (fp_reg == FAIL || sp_reg == FAIL) |
4505 | { | |
4506 | as_bad (_("expected <reg>, <reg>")); | |
4507 | ignore_rest_of_line (); | |
4508 | return; | |
4509 | } | |
b99bd4ef | 4510 | |
c19d1205 ZW |
4511 | /* Optional constant. */ |
4512 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4513 | { | |
4514 | if (immediate_for_directive (&offset) == FAIL) | |
4515 | return; | |
4516 | } | |
4517 | else | |
4518 | offset = 0; | |
a737bd4d | 4519 | |
c19d1205 | 4520 | demand_empty_rest_of_line (); |
a737bd4d | 4521 | |
fdfde340 | 4522 | if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) |
a737bd4d | 4523 | { |
c19d1205 ZW |
4524 | as_bad (_("register must be either sp or set by a previous" |
4525 | "unwind_movsp directive")); | |
4526 | return; | |
a737bd4d NC |
4527 | } |
4528 | ||
c19d1205 ZW |
4529 | /* Don't generate any opcodes, just record the information for later. */ |
4530 | unwind.fp_reg = fp_reg; | |
4531 | unwind.fp_used = 1; | |
fdfde340 | 4532 | if (sp_reg == REG_SP) |
c19d1205 ZW |
4533 | unwind.fp_offset = unwind.frame_size - offset; |
4534 | else | |
4535 | unwind.fp_offset -= offset; | |
a737bd4d NC |
4536 | } |
4537 | ||
c19d1205 ZW |
4538 | /* Parse an unwind_raw directive. */ |
4539 | ||
4540 | static void | |
4541 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 4542 | { |
c19d1205 | 4543 | expressionS exp; |
708587a4 | 4544 | /* This is an arbitrary limit. */ |
c19d1205 ZW |
4545 | unsigned char op[16]; |
4546 | int count; | |
a737bd4d | 4547 | |
921e5f0a | 4548 | if (!unwind.proc_start) |
c921be7d | 4549 | as_bad (MISSING_FNSTART); |
921e5f0a | 4550 | |
c19d1205 ZW |
4551 | expression (&exp); |
4552 | if (exp.X_op == O_constant | |
4553 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 4554 | { |
c19d1205 ZW |
4555 | unwind.frame_size += exp.X_add_number; |
4556 | expression (&exp); | |
4557 | } | |
4558 | else | |
4559 | exp.X_op = O_illegal; | |
a737bd4d | 4560 | |
c19d1205 ZW |
4561 | if (exp.X_op != O_constant) |
4562 | { | |
4563 | as_bad (_("expected <offset>, <opcode>")); | |
4564 | ignore_rest_of_line (); | |
4565 | return; | |
4566 | } | |
a737bd4d | 4567 | |
c19d1205 | 4568 | count = 0; |
a737bd4d | 4569 | |
c19d1205 ZW |
4570 | /* Parse the opcode. */ |
4571 | for (;;) | |
4572 | { | |
4573 | if (count >= 16) | |
4574 | { | |
4575 | as_bad (_("unwind opcode too long")); | |
4576 | ignore_rest_of_line (); | |
a737bd4d | 4577 | } |
c19d1205 | 4578 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 4579 | { |
c19d1205 ZW |
4580 | as_bad (_("invalid unwind opcode")); |
4581 | ignore_rest_of_line (); | |
4582 | return; | |
a737bd4d | 4583 | } |
c19d1205 | 4584 | op[count++] = exp.X_add_number; |
a737bd4d | 4585 | |
c19d1205 ZW |
4586 | /* Parse the next byte. */ |
4587 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
4588 | break; | |
a737bd4d | 4589 | |
c19d1205 ZW |
4590 | expression (&exp); |
4591 | } | |
b99bd4ef | 4592 | |
c19d1205 ZW |
4593 | /* Add the opcode bytes in reverse order. */ |
4594 | while (count--) | |
4595 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 4596 | |
c19d1205 | 4597 | demand_empty_rest_of_line (); |
b99bd4ef | 4598 | } |
ee065d83 PB |
4599 | |
4600 | ||
4601 | /* Parse a .eabi_attribute directive. */ | |
4602 | ||
4603 | static void | |
4604 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
4605 | { | |
0420f52b | 4606 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC); |
ee3c0378 AS |
4607 | |
4608 | if (tag < NUM_KNOWN_OBJ_ATTRIBUTES) | |
4609 | attributes_set_explicitly[tag] = 1; | |
ee065d83 PB |
4610 | } |
4611 | ||
0855e32b NS |
4612 | /* Emit a tls fix for the symbol. */ |
4613 | ||
4614 | static void | |
4615 | s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED) | |
4616 | { | |
4617 | char *p; | |
4618 | expressionS exp; | |
4619 | #ifdef md_flush_pending_output | |
4620 | md_flush_pending_output (); | |
4621 | #endif | |
4622 | ||
4623 | #ifdef md_cons_align | |
4624 | md_cons_align (4); | |
4625 | #endif | |
4626 | ||
4627 | /* Since we're just labelling the code, there's no need to define a | |
4628 | mapping symbol. */ | |
4629 | expression (&exp); | |
4630 | p = obstack_next_free (&frchain_now->frch_obstack); | |
4631 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0, | |
4632 | thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
4633 | : BFD_RELOC_ARM_TLS_DESCSEQ); | |
4634 | } | |
cdf9ccec | 4635 | #endif /* OBJ_ELF */ |
0855e32b | 4636 | |
ee065d83 | 4637 | static void s_arm_arch (int); |
7a1d4c38 | 4638 | static void s_arm_object_arch (int); |
ee065d83 PB |
4639 | static void s_arm_cpu (int); |
4640 | static void s_arm_fpu (int); | |
69133863 | 4641 | static void s_arm_arch_extension (int); |
b99bd4ef | 4642 | |
f0927246 NC |
4643 | #ifdef TE_PE |
4644 | ||
4645 | static void | |
5f4273c7 | 4646 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
f0927246 NC |
4647 | { |
4648 | expressionS exp; | |
4649 | ||
4650 | do | |
4651 | { | |
4652 | expression (&exp); | |
4653 | if (exp.X_op == O_symbol) | |
4654 | exp.X_op = O_secrel; | |
4655 | ||
4656 | emit_expr (&exp, 4); | |
4657 | } | |
4658 | while (*input_line_pointer++ == ','); | |
4659 | ||
4660 | input_line_pointer--; | |
4661 | demand_empty_rest_of_line (); | |
4662 | } | |
4663 | #endif /* TE_PE */ | |
4664 | ||
c19d1205 ZW |
4665 | /* This table describes all the machine specific pseudo-ops the assembler |
4666 | has to support. The fields are: | |
4667 | pseudo-op name without dot | |
4668 | function to call to execute this pseudo-op | |
4669 | Integer arg to pass to the function. */ | |
b99bd4ef | 4670 | |
c19d1205 | 4671 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 4672 | { |
c19d1205 ZW |
4673 | /* Never called because '.req' does not start a line. */ |
4674 | { "req", s_req, 0 }, | |
dcbf9037 JB |
4675 | /* Following two are likewise never called. */ |
4676 | { "dn", s_dn, 0 }, | |
4677 | { "qn", s_qn, 0 }, | |
c19d1205 ZW |
4678 | { "unreq", s_unreq, 0 }, |
4679 | { "bss", s_bss, 0 }, | |
4680 | { "align", s_align, 0 }, | |
4681 | { "arm", s_arm, 0 }, | |
4682 | { "thumb", s_thumb, 0 }, | |
4683 | { "code", s_code, 0 }, | |
4684 | { "force_thumb", s_force_thumb, 0 }, | |
4685 | { "thumb_func", s_thumb_func, 0 }, | |
4686 | { "thumb_set", s_thumb_set, 0 }, | |
4687 | { "even", s_even, 0 }, | |
4688 | { "ltorg", s_ltorg, 0 }, | |
4689 | { "pool", s_ltorg, 0 }, | |
4690 | { "syntax", s_syntax, 0 }, | |
8463be01 PB |
4691 | { "cpu", s_arm_cpu, 0 }, |
4692 | { "arch", s_arm_arch, 0 }, | |
7a1d4c38 | 4693 | { "object_arch", s_arm_object_arch, 0 }, |
8463be01 | 4694 | { "fpu", s_arm_fpu, 0 }, |
69133863 | 4695 | { "arch_extension", s_arm_arch_extension, 0 }, |
c19d1205 | 4696 | #ifdef OBJ_ELF |
c921be7d NC |
4697 | { "word", s_arm_elf_cons, 4 }, |
4698 | { "long", s_arm_elf_cons, 4 }, | |
4699 | { "inst.n", s_arm_elf_inst, 2 }, | |
4700 | { "inst.w", s_arm_elf_inst, 4 }, | |
4701 | { "inst", s_arm_elf_inst, 0 }, | |
4702 | { "rel31", s_arm_rel31, 0 }, | |
c19d1205 ZW |
4703 | { "fnstart", s_arm_unwind_fnstart, 0 }, |
4704 | { "fnend", s_arm_unwind_fnend, 0 }, | |
4705 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
4706 | { "personality", s_arm_unwind_personality, 0 }, | |
4707 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
4708 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
4709 | { "save", s_arm_unwind_save, 0 }, | |
fa073d69 | 4710 | { "vsave", s_arm_unwind_save, 1 }, |
c19d1205 ZW |
4711 | { "movsp", s_arm_unwind_movsp, 0 }, |
4712 | { "pad", s_arm_unwind_pad, 0 }, | |
4713 | { "setfp", s_arm_unwind_setfp, 0 }, | |
4714 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 | 4715 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
0855e32b | 4716 | { "tlsdescseq", s_arm_tls_descseq, 0 }, |
c19d1205 ZW |
4717 | #else |
4718 | { "word", cons, 4}, | |
f0927246 NC |
4719 | |
4720 | /* These are used for dwarf. */ | |
4721 | {"2byte", cons, 2}, | |
4722 | {"4byte", cons, 4}, | |
4723 | {"8byte", cons, 8}, | |
4724 | /* These are used for dwarf2. */ | |
4725 | { "file", (void (*) (int)) dwarf2_directive_file, 0 }, | |
4726 | { "loc", dwarf2_directive_loc, 0 }, | |
4727 | { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, | |
c19d1205 ZW |
4728 | #endif |
4729 | { "extend", float_cons, 'x' }, | |
4730 | { "ldouble", float_cons, 'x' }, | |
4731 | { "packed", float_cons, 'p' }, | |
f0927246 NC |
4732 | #ifdef TE_PE |
4733 | {"secrel32", pe_directive_secrel, 0}, | |
4734 | #endif | |
2e6976a8 DG |
4735 | |
4736 | /* These are for compatibility with CodeComposer Studio. */ | |
4737 | {"ref", s_ccs_ref, 0}, | |
4738 | {"def", s_ccs_def, 0}, | |
4739 | {"asmfunc", s_ccs_asmfunc, 0}, | |
4740 | {"endasmfunc", s_ccs_endasmfunc, 0}, | |
4741 | ||
c19d1205 ZW |
4742 | { 0, 0, 0 } |
4743 | }; | |
4744 | \f | |
4745 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 4746 | |
c19d1205 ZW |
4747 | /* Generic immediate-value read function for use in insn parsing. |
4748 | STR points to the beginning of the immediate (the leading #); | |
4749 | VAL receives the value; if the value is outside [MIN, MAX] | |
4750 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
4751 | optional. */ | |
b99bd4ef | 4752 | |
c19d1205 ZW |
4753 | static int |
4754 | parse_immediate (char **str, int *val, int min, int max, | |
4755 | bfd_boolean prefix_opt) | |
4756 | { | |
4757 | expressionS exp; | |
4758 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
4759 | if (exp.X_op != O_constant) | |
b99bd4ef | 4760 | { |
c19d1205 ZW |
4761 | inst.error = _("constant expression required"); |
4762 | return FAIL; | |
4763 | } | |
b99bd4ef | 4764 | |
c19d1205 ZW |
4765 | if (exp.X_add_number < min || exp.X_add_number > max) |
4766 | { | |
4767 | inst.error = _("immediate value out of range"); | |
4768 | return FAIL; | |
4769 | } | |
b99bd4ef | 4770 | |
c19d1205 ZW |
4771 | *val = exp.X_add_number; |
4772 | return SUCCESS; | |
4773 | } | |
b99bd4ef | 4774 | |
5287ad62 | 4775 | /* Less-generic immediate-value read function with the possibility of loading a |
036dc3f7 | 4776 | big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate |
5287ad62 JB |
4777 | instructions. Puts the result directly in inst.operands[i]. */ |
4778 | ||
4779 | static int | |
8335d6aa JW |
4780 | parse_big_immediate (char **str, int i, expressionS *in_exp, |
4781 | bfd_boolean allow_symbol_p) | |
5287ad62 JB |
4782 | { |
4783 | expressionS exp; | |
8335d6aa | 4784 | expressionS *exp_p = in_exp ? in_exp : &exp; |
5287ad62 JB |
4785 | char *ptr = *str; |
4786 | ||
8335d6aa | 4787 | my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG); |
5287ad62 | 4788 | |
8335d6aa | 4789 | if (exp_p->X_op == O_constant) |
036dc3f7 | 4790 | { |
8335d6aa | 4791 | inst.operands[i].imm = exp_p->X_add_number & 0xffffffff; |
036dc3f7 PB |
4792 | /* If we're on a 64-bit host, then a 64-bit number can be returned using |
4793 | O_constant. We have to be careful not to break compilation for | |
4794 | 32-bit X_add_number, though. */ | |
8335d6aa | 4795 | if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0) |
036dc3f7 | 4796 | { |
8335d6aa JW |
4797 | /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */ |
4798 | inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16) | |
4799 | & 0xffffffff); | |
036dc3f7 PB |
4800 | inst.operands[i].regisimm = 1; |
4801 | } | |
4802 | } | |
8335d6aa JW |
4803 | else if (exp_p->X_op == O_big |
4804 | && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32) | |
5287ad62 JB |
4805 | { |
4806 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; | |
95b75c01 | 4807 | |
5287ad62 | 4808 | /* Bignums have their least significant bits in |
477330fc RM |
4809 | generic_bignum[0]. Make sure we put 32 bits in imm and |
4810 | 32 bits in reg, in a (hopefully) portable way. */ | |
9c2799c2 | 4811 | gas_assert (parts != 0); |
95b75c01 NC |
4812 | |
4813 | /* Make sure that the number is not too big. | |
4814 | PR 11972: Bignums can now be sign-extended to the | |
4815 | size of a .octa so check that the out of range bits | |
4816 | are all zero or all one. */ | |
8335d6aa | 4817 | if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64) |
95b75c01 NC |
4818 | { |
4819 | LITTLENUM_TYPE m = -1; | |
4820 | ||
4821 | if (generic_bignum[parts * 2] != 0 | |
4822 | && generic_bignum[parts * 2] != m) | |
4823 | return FAIL; | |
4824 | ||
8335d6aa | 4825 | for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++) |
95b75c01 NC |
4826 | if (generic_bignum[j] != generic_bignum[j-1]) |
4827 | return FAIL; | |
4828 | } | |
4829 | ||
5287ad62 JB |
4830 | inst.operands[i].imm = 0; |
4831 | for (j = 0; j < parts; j++, idx++) | |
477330fc RM |
4832 | inst.operands[i].imm |= generic_bignum[idx] |
4833 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
5287ad62 JB |
4834 | inst.operands[i].reg = 0; |
4835 | for (j = 0; j < parts; j++, idx++) | |
477330fc RM |
4836 | inst.operands[i].reg |= generic_bignum[idx] |
4837 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
5287ad62 JB |
4838 | inst.operands[i].regisimm = 1; |
4839 | } | |
8335d6aa | 4840 | else if (!(exp_p->X_op == O_symbol && allow_symbol_p)) |
5287ad62 | 4841 | return FAIL; |
5f4273c7 | 4842 | |
5287ad62 JB |
4843 | *str = ptr; |
4844 | ||
4845 | return SUCCESS; | |
4846 | } | |
4847 | ||
c19d1205 ZW |
4848 | /* Returns the pseudo-register number of an FPA immediate constant, |
4849 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 4850 | |
c19d1205 ZW |
4851 | static int |
4852 | parse_fpa_immediate (char ** str) | |
4853 | { | |
4854 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4855 | char * save_in; | |
4856 | expressionS exp; | |
4857 | int i; | |
4858 | int j; | |
b99bd4ef | 4859 | |
c19d1205 ZW |
4860 | /* First try and match exact strings, this is to guarantee |
4861 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 4862 | |
c19d1205 ZW |
4863 | for (i = 0; fp_const[i]; i++) |
4864 | { | |
4865 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 4866 | { |
c19d1205 | 4867 | char *start = *str; |
b99bd4ef | 4868 | |
c19d1205 ZW |
4869 | *str += strlen (fp_const[i]); |
4870 | if (is_end_of_line[(unsigned char) **str]) | |
4871 | return i + 8; | |
4872 | *str = start; | |
4873 | } | |
4874 | } | |
b99bd4ef | 4875 | |
c19d1205 ZW |
4876 | /* Just because we didn't get a match doesn't mean that the constant |
4877 | isn't valid, just that it is in a format that we don't | |
4878 | automatically recognize. Try parsing it with the standard | |
4879 | expression routines. */ | |
b99bd4ef | 4880 | |
c19d1205 | 4881 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 4882 | |
c19d1205 ZW |
4883 | /* Look for a raw floating point number. */ |
4884 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
4885 | && is_end_of_line[(unsigned char) *save_in]) | |
4886 | { | |
4887 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4888 | { | |
4889 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 4890 | { |
c19d1205 ZW |
4891 | if (words[j] != fp_values[i][j]) |
4892 | break; | |
b99bd4ef NC |
4893 | } |
4894 | ||
c19d1205 | 4895 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 4896 | { |
c19d1205 ZW |
4897 | *str = save_in; |
4898 | return i + 8; | |
b99bd4ef NC |
4899 | } |
4900 | } | |
4901 | } | |
b99bd4ef | 4902 | |
c19d1205 ZW |
4903 | /* Try and parse a more complex expression, this will probably fail |
4904 | unless the code uses a floating point prefix (eg "0f"). */ | |
4905 | save_in = input_line_pointer; | |
4906 | input_line_pointer = *str; | |
4907 | if (expression (&exp) == absolute_section | |
4908 | && exp.X_op == O_big | |
4909 | && exp.X_add_number < 0) | |
4910 | { | |
4911 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
4912 | Ditto for 15. */ | |
4913 | if (gen_to_words (words, 5, (long) 15) == 0) | |
4914 | { | |
4915 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4916 | { | |
4917 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
4918 | { | |
4919 | if (words[j] != fp_values[i][j]) | |
4920 | break; | |
4921 | } | |
b99bd4ef | 4922 | |
c19d1205 ZW |
4923 | if (j == MAX_LITTLENUMS) |
4924 | { | |
4925 | *str = input_line_pointer; | |
4926 | input_line_pointer = save_in; | |
4927 | return i + 8; | |
4928 | } | |
4929 | } | |
4930 | } | |
b99bd4ef NC |
4931 | } |
4932 | ||
c19d1205 ZW |
4933 | *str = input_line_pointer; |
4934 | input_line_pointer = save_in; | |
4935 | inst.error = _("invalid FPA immediate expression"); | |
4936 | return FAIL; | |
b99bd4ef NC |
4937 | } |
4938 | ||
136da414 JB |
4939 | /* Returns 1 if a number has "quarter-precision" float format |
4940 | 0baBbbbbbc defgh000 00000000 00000000. */ | |
4941 | ||
4942 | static int | |
4943 | is_quarter_float (unsigned imm) | |
4944 | { | |
4945 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; | |
4946 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; | |
4947 | } | |
4948 | ||
aacf0b33 KT |
4949 | |
4950 | /* Detect the presence of a floating point or integer zero constant, | |
4951 | i.e. #0.0 or #0. */ | |
4952 | ||
4953 | static bfd_boolean | |
4954 | parse_ifimm_zero (char **in) | |
4955 | { | |
4956 | int error_code; | |
4957 | ||
4958 | if (!is_immediate_prefix (**in)) | |
4959 | return FALSE; | |
4960 | ||
4961 | ++*in; | |
4962 | error_code = atof_generic (in, ".", EXP_CHARS, | |
4963 | &generic_floating_point_number); | |
4964 | ||
4965 | if (!error_code | |
4966 | && generic_floating_point_number.sign == '+' | |
4967 | && (generic_floating_point_number.low | |
4968 | > generic_floating_point_number.leader)) | |
4969 | return TRUE; | |
4970 | ||
4971 | return FALSE; | |
4972 | } | |
4973 | ||
136da414 JB |
4974 | /* Parse an 8-bit "quarter-precision" floating point number of the form: |
4975 | 0baBbbbbbc defgh000 00000000 00000000. | |
c96612cc JB |
4976 | The zero and minus-zero cases need special handling, since they can't be |
4977 | encoded in the "quarter-precision" float format, but can nonetheless be | |
4978 | loaded as integer constants. */ | |
136da414 JB |
4979 | |
4980 | static unsigned | |
4981 | parse_qfloat_immediate (char **ccp, int *immed) | |
4982 | { | |
4983 | char *str = *ccp; | |
c96612cc | 4984 | char *fpnum; |
136da414 | 4985 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
c96612cc | 4986 | int found_fpchar = 0; |
5f4273c7 | 4987 | |
136da414 | 4988 | skip_past_char (&str, '#'); |
5f4273c7 | 4989 | |
c96612cc JB |
4990 | /* We must not accidentally parse an integer as a floating-point number. Make |
4991 | sure that the value we parse is not an integer by checking for special | |
4992 | characters '.' or 'e'. | |
4993 | FIXME: This is a horrible hack, but doing better is tricky because type | |
4994 | information isn't in a very usable state at parse time. */ | |
4995 | fpnum = str; | |
4996 | skip_whitespace (fpnum); | |
4997 | ||
4998 | if (strncmp (fpnum, "0x", 2) == 0) | |
4999 | return FAIL; | |
5000 | else | |
5001 | { | |
5002 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) | |
477330fc RM |
5003 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') |
5004 | { | |
5005 | found_fpchar = 1; | |
5006 | break; | |
5007 | } | |
c96612cc JB |
5008 | |
5009 | if (!found_fpchar) | |
477330fc | 5010 | return FAIL; |
c96612cc | 5011 | } |
5f4273c7 | 5012 | |
136da414 JB |
5013 | if ((str = atof_ieee (str, 's', words)) != NULL) |
5014 | { | |
5015 | unsigned fpword = 0; | |
5016 | int i; | |
5f4273c7 | 5017 | |
136da414 JB |
5018 | /* Our FP word must be 32 bits (single-precision FP). */ |
5019 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
477330fc RM |
5020 | { |
5021 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
5022 | fpword |= words[i]; | |
5023 | } | |
5f4273c7 | 5024 | |
c96612cc | 5025 | if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) |
477330fc | 5026 | *immed = fpword; |
136da414 | 5027 | else |
477330fc | 5028 | return FAIL; |
136da414 JB |
5029 | |
5030 | *ccp = str; | |
5f4273c7 | 5031 | |
136da414 JB |
5032 | return SUCCESS; |
5033 | } | |
5f4273c7 | 5034 | |
136da414 JB |
5035 | return FAIL; |
5036 | } | |
5037 | ||
c19d1205 ZW |
5038 | /* Shift operands. */ |
5039 | enum shift_kind | |
b99bd4ef | 5040 | { |
c19d1205 ZW |
5041 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
5042 | }; | |
b99bd4ef | 5043 | |
c19d1205 ZW |
5044 | struct asm_shift_name |
5045 | { | |
5046 | const char *name; | |
5047 | enum shift_kind kind; | |
5048 | }; | |
b99bd4ef | 5049 | |
c19d1205 ZW |
5050 | /* Third argument to parse_shift. */ |
5051 | enum parse_shift_mode | |
5052 | { | |
5053 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
5054 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
5055 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
5056 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
5057 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
5058 | }; | |
b99bd4ef | 5059 | |
c19d1205 ZW |
5060 | /* Parse a <shift> specifier on an ARM data processing instruction. |
5061 | This has three forms: | |
b99bd4ef | 5062 | |
c19d1205 ZW |
5063 | (LSL|LSR|ASL|ASR|ROR) Rs |
5064 | (LSL|LSR|ASL|ASR|ROR) #imm | |
5065 | RRX | |
b99bd4ef | 5066 | |
c19d1205 ZW |
5067 | Note that ASL is assimilated to LSL in the instruction encoding, and |
5068 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 5069 | |
c19d1205 ZW |
5070 | static int |
5071 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 5072 | { |
c19d1205 ZW |
5073 | const struct asm_shift_name *shift_name; |
5074 | enum shift_kind shift; | |
5075 | char *s = *str; | |
5076 | char *p = s; | |
5077 | int reg; | |
b99bd4ef | 5078 | |
c19d1205 ZW |
5079 | for (p = *str; ISALPHA (*p); p++) |
5080 | ; | |
b99bd4ef | 5081 | |
c19d1205 | 5082 | if (p == *str) |
b99bd4ef | 5083 | { |
c19d1205 ZW |
5084 | inst.error = _("shift expression expected"); |
5085 | return FAIL; | |
b99bd4ef NC |
5086 | } |
5087 | ||
21d799b5 | 5088 | shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str, |
477330fc | 5089 | p - *str); |
c19d1205 ZW |
5090 | |
5091 | if (shift_name == NULL) | |
b99bd4ef | 5092 | { |
c19d1205 ZW |
5093 | inst.error = _("shift expression expected"); |
5094 | return FAIL; | |
b99bd4ef NC |
5095 | } |
5096 | ||
c19d1205 | 5097 | shift = shift_name->kind; |
b99bd4ef | 5098 | |
c19d1205 ZW |
5099 | switch (mode) |
5100 | { | |
5101 | case NO_SHIFT_RESTRICT: | |
5102 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 5103 | |
c19d1205 ZW |
5104 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
5105 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
5106 | { | |
5107 | inst.error = _("'LSL' or 'ASR' required"); | |
5108 | return FAIL; | |
5109 | } | |
5110 | break; | |
b99bd4ef | 5111 | |
c19d1205 ZW |
5112 | case SHIFT_LSL_IMMEDIATE: |
5113 | if (shift != SHIFT_LSL) | |
5114 | { | |
5115 | inst.error = _("'LSL' required"); | |
5116 | return FAIL; | |
5117 | } | |
5118 | break; | |
b99bd4ef | 5119 | |
c19d1205 ZW |
5120 | case SHIFT_ASR_IMMEDIATE: |
5121 | if (shift != SHIFT_ASR) | |
5122 | { | |
5123 | inst.error = _("'ASR' required"); | |
5124 | return FAIL; | |
5125 | } | |
5126 | break; | |
b99bd4ef | 5127 | |
c19d1205 ZW |
5128 | default: abort (); |
5129 | } | |
b99bd4ef | 5130 | |
c19d1205 ZW |
5131 | if (shift != SHIFT_RRX) |
5132 | { | |
5133 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
5134 | skip_whitespace (p); | |
b99bd4ef | 5135 | |
c19d1205 | 5136 | if (mode == NO_SHIFT_RESTRICT |
dcbf9037 | 5137 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
5138 | { |
5139 | inst.operands[i].imm = reg; | |
5140 | inst.operands[i].immisreg = 1; | |
5141 | } | |
5142 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
5143 | return FAIL; | |
5144 | } | |
5145 | inst.operands[i].shift_kind = shift; | |
5146 | inst.operands[i].shifted = 1; | |
5147 | *str = p; | |
5148 | return SUCCESS; | |
b99bd4ef NC |
5149 | } |
5150 | ||
c19d1205 | 5151 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 5152 | |
c19d1205 ZW |
5153 | #<immediate> |
5154 | #<immediate>, <rotate> | |
5155 | <Rm> | |
5156 | <Rm>, <shift> | |
b99bd4ef | 5157 | |
c19d1205 ZW |
5158 | where <shift> is defined by parse_shift above, and <rotate> is a |
5159 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 5160 | is deferred to md_apply_fix. */ |
b99bd4ef | 5161 | |
c19d1205 ZW |
5162 | static int |
5163 | parse_shifter_operand (char **str, int i) | |
5164 | { | |
5165 | int value; | |
91d6fa6a | 5166 | expressionS exp; |
b99bd4ef | 5167 | |
dcbf9037 | 5168 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
5169 | { |
5170 | inst.operands[i].reg = value; | |
5171 | inst.operands[i].isreg = 1; | |
b99bd4ef | 5172 | |
c19d1205 ZW |
5173 | /* parse_shift will override this if appropriate */ |
5174 | inst.reloc.exp.X_op = O_constant; | |
5175 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 5176 | |
c19d1205 ZW |
5177 | if (skip_past_comma (str) == FAIL) |
5178 | return SUCCESS; | |
b99bd4ef | 5179 | |
c19d1205 ZW |
5180 | /* Shift operation on register. */ |
5181 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
5182 | } |
5183 | ||
c19d1205 ZW |
5184 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
5185 | return FAIL; | |
b99bd4ef | 5186 | |
c19d1205 | 5187 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 5188 | { |
c19d1205 | 5189 | /* #x, y -- ie explicit rotation by Y. */ |
91d6fa6a | 5190 | if (my_get_expression (&exp, str, GE_NO_PREFIX)) |
c19d1205 | 5191 | return FAIL; |
b99bd4ef | 5192 | |
91d6fa6a | 5193 | if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
c19d1205 ZW |
5194 | { |
5195 | inst.error = _("constant expression expected"); | |
5196 | return FAIL; | |
5197 | } | |
b99bd4ef | 5198 | |
91d6fa6a | 5199 | value = exp.X_add_number; |
c19d1205 ZW |
5200 | if (value < 0 || value > 30 || value % 2 != 0) |
5201 | { | |
5202 | inst.error = _("invalid rotation"); | |
5203 | return FAIL; | |
5204 | } | |
5205 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
5206 | { | |
5207 | inst.error = _("invalid constant"); | |
5208 | return FAIL; | |
5209 | } | |
09d92015 | 5210 | |
a415b1cd JB |
5211 | /* Encode as specified. */ |
5212 | inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7; | |
5213 | return SUCCESS; | |
09d92015 MM |
5214 | } |
5215 | ||
c19d1205 ZW |
5216 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
5217 | inst.reloc.pc_rel = 0; | |
5218 | return SUCCESS; | |
09d92015 MM |
5219 | } |
5220 | ||
4962c51a MS |
5221 | /* Group relocation information. Each entry in the table contains the |
5222 | textual name of the relocation as may appear in assembler source | |
5223 | and must end with a colon. | |
5224 | Along with this textual name are the relocation codes to be used if | |
5225 | the corresponding instruction is an ALU instruction (ADD or SUB only), | |
5226 | an LDR, an LDRS, or an LDC. */ | |
5227 | ||
5228 | struct group_reloc_table_entry | |
5229 | { | |
5230 | const char *name; | |
5231 | int alu_code; | |
5232 | int ldr_code; | |
5233 | int ldrs_code; | |
5234 | int ldc_code; | |
5235 | }; | |
5236 | ||
5237 | typedef enum | |
5238 | { | |
5239 | /* Varieties of non-ALU group relocation. */ | |
5240 | ||
5241 | GROUP_LDR, | |
5242 | GROUP_LDRS, | |
5243 | GROUP_LDC | |
5244 | } group_reloc_type; | |
5245 | ||
5246 | static struct group_reloc_table_entry group_reloc_table[] = | |
5247 | { /* Program counter relative: */ | |
5248 | { "pc_g0_nc", | |
5249 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ | |
5250 | 0, /* LDR */ | |
5251 | 0, /* LDRS */ | |
5252 | 0 }, /* LDC */ | |
5253 | { "pc_g0", | |
5254 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ | |
5255 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ | |
5256 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ | |
5257 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ | |
5258 | { "pc_g1_nc", | |
5259 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ | |
5260 | 0, /* LDR */ | |
5261 | 0, /* LDRS */ | |
5262 | 0 }, /* LDC */ | |
5263 | { "pc_g1", | |
5264 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ | |
5265 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ | |
5266 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ | |
5267 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ | |
5268 | { "pc_g2", | |
5269 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ | |
5270 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ | |
5271 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ | |
5272 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ | |
5273 | /* Section base relative */ | |
5274 | { "sb_g0_nc", | |
5275 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ | |
5276 | 0, /* LDR */ | |
5277 | 0, /* LDRS */ | |
5278 | 0 }, /* LDC */ | |
5279 | { "sb_g0", | |
5280 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ | |
5281 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ | |
5282 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ | |
5283 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ | |
5284 | { "sb_g1_nc", | |
5285 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ | |
5286 | 0, /* LDR */ | |
5287 | 0, /* LDRS */ | |
5288 | 0 }, /* LDC */ | |
5289 | { "sb_g1", | |
5290 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ | |
5291 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ | |
5292 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ | |
5293 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ | |
5294 | { "sb_g2", | |
5295 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ | |
5296 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ | |
5297 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ | |
5298 | BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ | |
5299 | ||
5300 | /* Given the address of a pointer pointing to the textual name of a group | |
5301 | relocation as may appear in assembler source, attempt to find its details | |
5302 | in group_reloc_table. The pointer will be updated to the character after | |
5303 | the trailing colon. On failure, FAIL will be returned; SUCCESS | |
5304 | otherwise. On success, *entry will be updated to point at the relevant | |
5305 | group_reloc_table entry. */ | |
5306 | ||
5307 | static int | |
5308 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) | |
5309 | { | |
5310 | unsigned int i; | |
5311 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) | |
5312 | { | |
5313 | int length = strlen (group_reloc_table[i].name); | |
5314 | ||
5f4273c7 NC |
5315 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 |
5316 | && (*str)[length] == ':') | |
477330fc RM |
5317 | { |
5318 | *out = &group_reloc_table[i]; | |
5319 | *str += (length + 1); | |
5320 | return SUCCESS; | |
5321 | } | |
4962c51a MS |
5322 | } |
5323 | ||
5324 | return FAIL; | |
5325 | } | |
5326 | ||
5327 | /* Parse a <shifter_operand> for an ARM data processing instruction | |
5328 | (as for parse_shifter_operand) where group relocations are allowed: | |
5329 | ||
5330 | #<immediate> | |
5331 | #<immediate>, <rotate> | |
5332 | #:<group_reloc>:<expression> | |
5333 | <Rm> | |
5334 | <Rm>, <shift> | |
5335 | ||
5336 | where <group_reloc> is one of the strings defined in group_reloc_table. | |
5337 | The hashes are optional. | |
5338 | ||
5339 | Everything else is as for parse_shifter_operand. */ | |
5340 | ||
5341 | static parse_operand_result | |
5342 | parse_shifter_operand_group_reloc (char **str, int i) | |
5343 | { | |
5344 | /* Determine if we have the sequence of characters #: or just : | |
5345 | coming next. If we do, then we check for a group relocation. | |
5346 | If we don't, punt the whole lot to parse_shifter_operand. */ | |
5347 | ||
5348 | if (((*str)[0] == '#' && (*str)[1] == ':') | |
5349 | || (*str)[0] == ':') | |
5350 | { | |
5351 | struct group_reloc_table_entry *entry; | |
5352 | ||
5353 | if ((*str)[0] == '#') | |
477330fc | 5354 | (*str) += 2; |
4962c51a | 5355 | else |
477330fc | 5356 | (*str)++; |
4962c51a MS |
5357 | |
5358 | /* Try to parse a group relocation. Anything else is an error. */ | |
5359 | if (find_group_reloc_table_entry (str, &entry) == FAIL) | |
477330fc RM |
5360 | { |
5361 | inst.error = _("unknown group relocation"); | |
5362 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5363 | } | |
4962c51a MS |
5364 | |
5365 | /* We now have the group relocation table entry corresponding to | |
477330fc | 5366 | the name in the assembler source. Next, we parse the expression. */ |
4962c51a | 5367 | if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) |
477330fc | 5368 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; |
4962c51a MS |
5369 | |
5370 | /* Record the relocation type (always the ALU variant here). */ | |
21d799b5 | 5371 | inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code; |
9c2799c2 | 5372 | gas_assert (inst.reloc.type != 0); |
4962c51a MS |
5373 | |
5374 | return PARSE_OPERAND_SUCCESS; | |
5375 | } | |
5376 | else | |
5377 | return parse_shifter_operand (str, i) == SUCCESS | |
477330fc | 5378 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; |
4962c51a MS |
5379 | |
5380 | /* Never reached. */ | |
5381 | } | |
5382 | ||
8e560766 MGD |
5383 | /* Parse a Neon alignment expression. Information is written to |
5384 | inst.operands[i]. We assume the initial ':' has been skipped. | |
fa94de6b | 5385 | |
8e560766 MGD |
5386 | align .imm = align << 8, .immisalign=1, .preind=0 */ |
5387 | static parse_operand_result | |
5388 | parse_neon_alignment (char **str, int i) | |
5389 | { | |
5390 | char *p = *str; | |
5391 | expressionS exp; | |
5392 | ||
5393 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
5394 | ||
5395 | if (exp.X_op != O_constant) | |
5396 | { | |
5397 | inst.error = _("alignment must be constant"); | |
5398 | return PARSE_OPERAND_FAIL; | |
5399 | } | |
5400 | ||
5401 | inst.operands[i].imm = exp.X_add_number << 8; | |
5402 | inst.operands[i].immisalign = 1; | |
5403 | /* Alignments are not pre-indexes. */ | |
5404 | inst.operands[i].preind = 0; | |
5405 | ||
5406 | *str = p; | |
5407 | return PARSE_OPERAND_SUCCESS; | |
5408 | } | |
5409 | ||
c19d1205 ZW |
5410 | /* Parse all forms of an ARM address expression. Information is written |
5411 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 5412 | |
c19d1205 | 5413 | Preindexed addressing (.preind=1): |
09d92015 | 5414 | |
c19d1205 ZW |
5415 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
5416 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5417 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5418 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5419 | |
c19d1205 | 5420 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 5421 | |
c19d1205 | 5422 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 5423 | |
c19d1205 ZW |
5424 | [Rn], #offset .reg=Rn .reloc.exp=offset |
5425 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5426 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5427 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5428 | |
c19d1205 | 5429 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 5430 | |
c19d1205 | 5431 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 5432 | |
c19d1205 | 5433 | Other: |
09d92015 | 5434 | |
c19d1205 ZW |
5435 | [Rn]{!} shorthand for [Rn,#0]{!} |
5436 | =immediate .isreg=0 .reloc.exp=immediate | |
5437 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 5438 | |
c19d1205 ZW |
5439 | It is the caller's responsibility to check for addressing modes not |
5440 | supported by the instruction, and to set inst.reloc.type. */ | |
5441 | ||
4962c51a MS |
5442 | static parse_operand_result |
5443 | parse_address_main (char **str, int i, int group_relocations, | |
477330fc | 5444 | group_reloc_type group_type) |
09d92015 | 5445 | { |
c19d1205 ZW |
5446 | char *p = *str; |
5447 | int reg; | |
09d92015 | 5448 | |
c19d1205 | 5449 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 5450 | { |
c19d1205 ZW |
5451 | if (skip_past_char (&p, '=') == FAIL) |
5452 | { | |
974da60d | 5453 | /* Bare address - translate to PC-relative offset. */ |
c19d1205 ZW |
5454 | inst.reloc.pc_rel = 1; |
5455 | inst.operands[i].reg = REG_PC; | |
5456 | inst.operands[i].isreg = 1; | |
5457 | inst.operands[i].preind = 1; | |
09d92015 | 5458 | |
8335d6aa JW |
5459 | if (my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX_BIG)) |
5460 | return PARSE_OPERAND_FAIL; | |
5461 | } | |
5462 | else if (parse_big_immediate (&p, i, &inst.reloc.exp, | |
5463 | /*allow_symbol_p=*/TRUE)) | |
4962c51a | 5464 | return PARSE_OPERAND_FAIL; |
09d92015 | 5465 | |
c19d1205 | 5466 | *str = p; |
4962c51a | 5467 | return PARSE_OPERAND_SUCCESS; |
09d92015 MM |
5468 | } |
5469 | ||
8ab8155f NC |
5470 | /* PR gas/14887: Allow for whitespace after the opening bracket. */ |
5471 | skip_whitespace (p); | |
5472 | ||
dcbf9037 | 5473 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 5474 | { |
c19d1205 | 5475 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
4962c51a | 5476 | return PARSE_OPERAND_FAIL; |
09d92015 | 5477 | } |
c19d1205 ZW |
5478 | inst.operands[i].reg = reg; |
5479 | inst.operands[i].isreg = 1; | |
09d92015 | 5480 | |
c19d1205 | 5481 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5482 | { |
c19d1205 | 5483 | inst.operands[i].preind = 1; |
09d92015 | 5484 | |
c19d1205 ZW |
5485 | if (*p == '+') p++; |
5486 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
5487 | ||
dcbf9037 | 5488 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
09d92015 | 5489 | { |
c19d1205 ZW |
5490 | inst.operands[i].imm = reg; |
5491 | inst.operands[i].immisreg = 1; | |
5492 | ||
5493 | if (skip_past_comma (&p) == SUCCESS) | |
5494 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5495 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5496 | } |
5287ad62 | 5497 | else if (skip_past_char (&p, ':') == SUCCESS) |
8e560766 MGD |
5498 | { |
5499 | /* FIXME: '@' should be used here, but it's filtered out by generic | |
5500 | code before we get to see it here. This may be subject to | |
5501 | change. */ | |
5502 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 5503 | |
8e560766 MGD |
5504 | if (result != PARSE_OPERAND_SUCCESS) |
5505 | return result; | |
5506 | } | |
c19d1205 ZW |
5507 | else |
5508 | { | |
5509 | if (inst.operands[i].negative) | |
5510 | { | |
5511 | inst.operands[i].negative = 0; | |
5512 | p--; | |
5513 | } | |
4962c51a | 5514 | |
5f4273c7 NC |
5515 | if (group_relocations |
5516 | && ((*p == '#' && *(p + 1) == ':') || *p == ':')) | |
4962c51a MS |
5517 | { |
5518 | struct group_reloc_table_entry *entry; | |
5519 | ||
477330fc RM |
5520 | /* Skip over the #: or : sequence. */ |
5521 | if (*p == '#') | |
5522 | p += 2; | |
5523 | else | |
5524 | p++; | |
4962c51a MS |
5525 | |
5526 | /* Try to parse a group relocation. Anything else is an | |
477330fc | 5527 | error. */ |
4962c51a MS |
5528 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) |
5529 | { | |
5530 | inst.error = _("unknown group relocation"); | |
5531 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5532 | } | |
5533 | ||
5534 | /* We now have the group relocation table entry corresponding to | |
5535 | the name in the assembler source. Next, we parse the | |
477330fc | 5536 | expression. */ |
4962c51a MS |
5537 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
5538 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5539 | ||
5540 | /* Record the relocation type. */ | |
477330fc RM |
5541 | switch (group_type) |
5542 | { | |
5543 | case GROUP_LDR: | |
5544 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code; | |
5545 | break; | |
4962c51a | 5546 | |
477330fc RM |
5547 | case GROUP_LDRS: |
5548 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code; | |
5549 | break; | |
4962c51a | 5550 | |
477330fc RM |
5551 | case GROUP_LDC: |
5552 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code; | |
5553 | break; | |
4962c51a | 5554 | |
477330fc RM |
5555 | default: |
5556 | gas_assert (0); | |
5557 | } | |
4962c51a | 5558 | |
477330fc | 5559 | if (inst.reloc.type == 0) |
4962c51a MS |
5560 | { |
5561 | inst.error = _("this group relocation is not allowed on this instruction"); | |
5562 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5563 | } | |
477330fc RM |
5564 | } |
5565 | else | |
26d97720 NS |
5566 | { |
5567 | char *q = p; | |
5568 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
5569 | return PARSE_OPERAND_FAIL; | |
5570 | /* If the offset is 0, find out if it's a +0 or -0. */ | |
5571 | if (inst.reloc.exp.X_op == O_constant | |
5572 | && inst.reloc.exp.X_add_number == 0) | |
5573 | { | |
5574 | skip_whitespace (q); | |
5575 | if (*q == '#') | |
5576 | { | |
5577 | q++; | |
5578 | skip_whitespace (q); | |
5579 | } | |
5580 | if (*q == '-') | |
5581 | inst.operands[i].negative = 1; | |
5582 | } | |
5583 | } | |
09d92015 MM |
5584 | } |
5585 | } | |
8e560766 MGD |
5586 | else if (skip_past_char (&p, ':') == SUCCESS) |
5587 | { | |
5588 | /* FIXME: '@' should be used here, but it's filtered out by generic code | |
5589 | before we get to see it here. This may be subject to change. */ | |
5590 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 5591 | |
8e560766 MGD |
5592 | if (result != PARSE_OPERAND_SUCCESS) |
5593 | return result; | |
5594 | } | |
09d92015 | 5595 | |
c19d1205 | 5596 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 5597 | { |
c19d1205 | 5598 | inst.error = _("']' expected"); |
4962c51a | 5599 | return PARSE_OPERAND_FAIL; |
09d92015 MM |
5600 | } |
5601 | ||
c19d1205 ZW |
5602 | if (skip_past_char (&p, '!') == SUCCESS) |
5603 | inst.operands[i].writeback = 1; | |
09d92015 | 5604 | |
c19d1205 | 5605 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5606 | { |
c19d1205 ZW |
5607 | if (skip_past_char (&p, '{') == SUCCESS) |
5608 | { | |
5609 | /* [Rn], {expr} - unindexed, with option */ | |
5610 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 5611 | 0, 255, TRUE) == FAIL) |
4962c51a | 5612 | return PARSE_OPERAND_FAIL; |
09d92015 | 5613 | |
c19d1205 ZW |
5614 | if (skip_past_char (&p, '}') == FAIL) |
5615 | { | |
5616 | inst.error = _("'}' expected at end of 'option' field"); | |
4962c51a | 5617 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5618 | } |
5619 | if (inst.operands[i].preind) | |
5620 | { | |
5621 | inst.error = _("cannot combine index with option"); | |
4962c51a | 5622 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5623 | } |
5624 | *str = p; | |
4962c51a | 5625 | return PARSE_OPERAND_SUCCESS; |
09d92015 | 5626 | } |
c19d1205 ZW |
5627 | else |
5628 | { | |
5629 | inst.operands[i].postind = 1; | |
5630 | inst.operands[i].writeback = 1; | |
09d92015 | 5631 | |
c19d1205 ZW |
5632 | if (inst.operands[i].preind) |
5633 | { | |
5634 | inst.error = _("cannot combine pre- and post-indexing"); | |
4962c51a | 5635 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5636 | } |
09d92015 | 5637 | |
c19d1205 ZW |
5638 | if (*p == '+') p++; |
5639 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 5640 | |
dcbf9037 | 5641 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 | 5642 | { |
477330fc RM |
5643 | /* We might be using the immediate for alignment already. If we |
5644 | are, OR the register number into the low-order bits. */ | |
5645 | if (inst.operands[i].immisalign) | |
5646 | inst.operands[i].imm |= reg; | |
5647 | else | |
5648 | inst.operands[i].imm = reg; | |
c19d1205 | 5649 | inst.operands[i].immisreg = 1; |
a737bd4d | 5650 | |
c19d1205 ZW |
5651 | if (skip_past_comma (&p) == SUCCESS) |
5652 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5653 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5654 | } |
5655 | else | |
5656 | { | |
26d97720 | 5657 | char *q = p; |
c19d1205 ZW |
5658 | if (inst.operands[i].negative) |
5659 | { | |
5660 | inst.operands[i].negative = 0; | |
5661 | p--; | |
5662 | } | |
5663 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4962c51a | 5664 | return PARSE_OPERAND_FAIL; |
26d97720 NS |
5665 | /* If the offset is 0, find out if it's a +0 or -0. */ |
5666 | if (inst.reloc.exp.X_op == O_constant | |
5667 | && inst.reloc.exp.X_add_number == 0) | |
5668 | { | |
5669 | skip_whitespace (q); | |
5670 | if (*q == '#') | |
5671 | { | |
5672 | q++; | |
5673 | skip_whitespace (q); | |
5674 | } | |
5675 | if (*q == '-') | |
5676 | inst.operands[i].negative = 1; | |
5677 | } | |
c19d1205 ZW |
5678 | } |
5679 | } | |
a737bd4d NC |
5680 | } |
5681 | ||
c19d1205 ZW |
5682 | /* If at this point neither .preind nor .postind is set, we have a |
5683 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
5684 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
5685 | { | |
5686 | inst.operands[i].preind = 1; | |
5687 | inst.reloc.exp.X_op = O_constant; | |
5688 | inst.reloc.exp.X_add_number = 0; | |
5689 | } | |
5690 | *str = p; | |
4962c51a MS |
5691 | return PARSE_OPERAND_SUCCESS; |
5692 | } | |
5693 | ||
5694 | static int | |
5695 | parse_address (char **str, int i) | |
5696 | { | |
21d799b5 | 5697 | return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS |
477330fc | 5698 | ? SUCCESS : FAIL; |
4962c51a MS |
5699 | } |
5700 | ||
5701 | static parse_operand_result | |
5702 | parse_address_group_reloc (char **str, int i, group_reloc_type type) | |
5703 | { | |
5704 | return parse_address_main (str, i, 1, type); | |
a737bd4d NC |
5705 | } |
5706 | ||
b6895b4f PB |
5707 | /* Parse an operand for a MOVW or MOVT instruction. */ |
5708 | static int | |
5709 | parse_half (char **str) | |
5710 | { | |
5711 | char * p; | |
5f4273c7 | 5712 | |
b6895b4f PB |
5713 | p = *str; |
5714 | skip_past_char (&p, '#'); | |
5f4273c7 | 5715 | if (strncasecmp (p, ":lower16:", 9) == 0) |
b6895b4f PB |
5716 | inst.reloc.type = BFD_RELOC_ARM_MOVW; |
5717 | else if (strncasecmp (p, ":upper16:", 9) == 0) | |
5718 | inst.reloc.type = BFD_RELOC_ARM_MOVT; | |
5719 | ||
5720 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
5721 | { | |
5722 | p += 9; | |
5f4273c7 | 5723 | skip_whitespace (p); |
b6895b4f PB |
5724 | } |
5725 | ||
5726 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5727 | return FAIL; | |
5728 | ||
5729 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
5730 | { | |
5731 | if (inst.reloc.exp.X_op != O_constant) | |
5732 | { | |
5733 | inst.error = _("constant expression expected"); | |
5734 | return FAIL; | |
5735 | } | |
5736 | if (inst.reloc.exp.X_add_number < 0 | |
5737 | || inst.reloc.exp.X_add_number > 0xffff) | |
5738 | { | |
5739 | inst.error = _("immediate value out of range"); | |
5740 | return FAIL; | |
5741 | } | |
5742 | } | |
5743 | *str = p; | |
5744 | return SUCCESS; | |
5745 | } | |
5746 | ||
c19d1205 | 5747 | /* Miscellaneous. */ |
a737bd4d | 5748 | |
c19d1205 ZW |
5749 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
5750 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
5751 | static int | |
d2cd1205 | 5752 | parse_psr (char **str, bfd_boolean lhs) |
09d92015 | 5753 | { |
c19d1205 ZW |
5754 | char *p; |
5755 | unsigned long psr_field; | |
62b3e311 PB |
5756 | const struct asm_psr *psr; |
5757 | char *start; | |
d2cd1205 | 5758 | bfd_boolean is_apsr = FALSE; |
ac7f631b | 5759 | bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m); |
09d92015 | 5760 | |
a4482bb6 NC |
5761 | /* PR gas/12698: If the user has specified -march=all then m_profile will |
5762 | be TRUE, but we want to ignore it in this case as we are building for any | |
5763 | CPU type, including non-m variants. */ | |
5764 | if (selected_cpu.core == arm_arch_any.core) | |
5765 | m_profile = FALSE; | |
5766 | ||
c19d1205 ZW |
5767 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
5768 | feature for ease of use and backwards compatibility. */ | |
5769 | p = *str; | |
62b3e311 | 5770 | if (strncasecmp (p, "SPSR", 4) == 0) |
d2cd1205 JB |
5771 | { |
5772 | if (m_profile) | |
5773 | goto unsupported_psr; | |
fa94de6b | 5774 | |
d2cd1205 JB |
5775 | psr_field = SPSR_BIT; |
5776 | } | |
5777 | else if (strncasecmp (p, "CPSR", 4) == 0) | |
5778 | { | |
5779 | if (m_profile) | |
5780 | goto unsupported_psr; | |
5781 | ||
5782 | psr_field = 0; | |
5783 | } | |
5784 | else if (strncasecmp (p, "APSR", 4) == 0) | |
5785 | { | |
5786 | /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A | |
5787 | and ARMv7-R architecture CPUs. */ | |
5788 | is_apsr = TRUE; | |
5789 | psr_field = 0; | |
5790 | } | |
5791 | else if (m_profile) | |
62b3e311 PB |
5792 | { |
5793 | start = p; | |
5794 | do | |
5795 | p++; | |
5796 | while (ISALNUM (*p) || *p == '_'); | |
5797 | ||
d2cd1205 JB |
5798 | if (strncasecmp (start, "iapsr", 5) == 0 |
5799 | || strncasecmp (start, "eapsr", 5) == 0 | |
5800 | || strncasecmp (start, "xpsr", 4) == 0 | |
5801 | || strncasecmp (start, "psr", 3) == 0) | |
5802 | p = start + strcspn (start, "rR") + 1; | |
5803 | ||
21d799b5 | 5804 | psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start, |
477330fc | 5805 | p - start); |
d2cd1205 | 5806 | |
62b3e311 PB |
5807 | if (!psr) |
5808 | return FAIL; | |
09d92015 | 5809 | |
d2cd1205 JB |
5810 | /* If APSR is being written, a bitfield may be specified. Note that |
5811 | APSR itself is handled above. */ | |
5812 | if (psr->field <= 3) | |
5813 | { | |
5814 | psr_field = psr->field; | |
5815 | is_apsr = TRUE; | |
5816 | goto check_suffix; | |
5817 | } | |
5818 | ||
62b3e311 | 5819 | *str = p; |
d2cd1205 JB |
5820 | /* M-profile MSR instructions have the mask field set to "10", except |
5821 | *PSR variants which modify APSR, which may use a different mask (and | |
5822 | have been handled already). Do that by setting the PSR_f field | |
5823 | here. */ | |
5824 | return psr->field | (lhs ? PSR_f : 0); | |
62b3e311 | 5825 | } |
d2cd1205 JB |
5826 | else |
5827 | goto unsupported_psr; | |
09d92015 | 5828 | |
62b3e311 | 5829 | p += 4; |
d2cd1205 | 5830 | check_suffix: |
c19d1205 ZW |
5831 | if (*p == '_') |
5832 | { | |
5833 | /* A suffix follows. */ | |
c19d1205 ZW |
5834 | p++; |
5835 | start = p; | |
a737bd4d | 5836 | |
c19d1205 ZW |
5837 | do |
5838 | p++; | |
5839 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 5840 | |
d2cd1205 JB |
5841 | if (is_apsr) |
5842 | { | |
5843 | /* APSR uses a notation for bits, rather than fields. */ | |
5844 | unsigned int nzcvq_bits = 0; | |
5845 | unsigned int g_bit = 0; | |
5846 | char *bit; | |
fa94de6b | 5847 | |
d2cd1205 JB |
5848 | for (bit = start; bit != p; bit++) |
5849 | { | |
5850 | switch (TOLOWER (*bit)) | |
477330fc | 5851 | { |
d2cd1205 JB |
5852 | case 'n': |
5853 | nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01; | |
5854 | break; | |
5855 | ||
5856 | case 'z': | |
5857 | nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02; | |
5858 | break; | |
5859 | ||
5860 | case 'c': | |
5861 | nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04; | |
5862 | break; | |
5863 | ||
5864 | case 'v': | |
5865 | nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08; | |
5866 | break; | |
fa94de6b | 5867 | |
d2cd1205 JB |
5868 | case 'q': |
5869 | nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10; | |
5870 | break; | |
fa94de6b | 5871 | |
d2cd1205 JB |
5872 | case 'g': |
5873 | g_bit |= (g_bit & 0x1) ? 0x2 : 0x1; | |
5874 | break; | |
fa94de6b | 5875 | |
d2cd1205 JB |
5876 | default: |
5877 | inst.error = _("unexpected bit specified after APSR"); | |
5878 | return FAIL; | |
5879 | } | |
5880 | } | |
fa94de6b | 5881 | |
d2cd1205 JB |
5882 | if (nzcvq_bits == 0x1f) |
5883 | psr_field |= PSR_f; | |
fa94de6b | 5884 | |
d2cd1205 JB |
5885 | if (g_bit == 0x1) |
5886 | { | |
5887 | if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)) | |
477330fc | 5888 | { |
d2cd1205 JB |
5889 | inst.error = _("selected processor does not " |
5890 | "support DSP extension"); | |
5891 | return FAIL; | |
5892 | } | |
5893 | ||
5894 | psr_field |= PSR_s; | |
5895 | } | |
fa94de6b | 5896 | |
d2cd1205 JB |
5897 | if ((nzcvq_bits & 0x20) != 0 |
5898 | || (nzcvq_bits != 0x1f && nzcvq_bits != 0) | |
5899 | || (g_bit & 0x2) != 0) | |
5900 | { | |
5901 | inst.error = _("bad bitmask specified after APSR"); | |
5902 | return FAIL; | |
5903 | } | |
5904 | } | |
5905 | else | |
477330fc | 5906 | { |
d2cd1205 | 5907 | psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start, |
477330fc | 5908 | p - start); |
d2cd1205 | 5909 | if (!psr) |
477330fc | 5910 | goto error; |
a737bd4d | 5911 | |
d2cd1205 JB |
5912 | psr_field |= psr->field; |
5913 | } | |
a737bd4d | 5914 | } |
c19d1205 | 5915 | else |
a737bd4d | 5916 | { |
c19d1205 ZW |
5917 | if (ISALNUM (*p)) |
5918 | goto error; /* Garbage after "[CS]PSR". */ | |
5919 | ||
d2cd1205 | 5920 | /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This |
477330fc | 5921 | is deprecated, but allow it anyway. */ |
d2cd1205 JB |
5922 | if (is_apsr && lhs) |
5923 | { | |
5924 | psr_field |= PSR_f; | |
5925 | as_tsktsk (_("writing to APSR without specifying a bitmask is " | |
5926 | "deprecated")); | |
5927 | } | |
5928 | else if (!m_profile) | |
5929 | /* These bits are never right for M-profile devices: don't set them | |
5930 | (only code paths which read/write APSR reach here). */ | |
5931 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 5932 | } |
c19d1205 ZW |
5933 | *str = p; |
5934 | return psr_field; | |
a737bd4d | 5935 | |
d2cd1205 JB |
5936 | unsupported_psr: |
5937 | inst.error = _("selected processor does not support requested special " | |
5938 | "purpose register"); | |
5939 | return FAIL; | |
5940 | ||
c19d1205 ZW |
5941 | error: |
5942 | inst.error = _("flag for {c}psr instruction expected"); | |
5943 | return FAIL; | |
a737bd4d NC |
5944 | } |
5945 | ||
c19d1205 ZW |
5946 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
5947 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 5948 | |
c19d1205 ZW |
5949 | static int |
5950 | parse_cps_flags (char **str) | |
a737bd4d | 5951 | { |
c19d1205 ZW |
5952 | int val = 0; |
5953 | int saw_a_flag = 0; | |
5954 | char *s = *str; | |
a737bd4d | 5955 | |
c19d1205 ZW |
5956 | for (;;) |
5957 | switch (*s++) | |
5958 | { | |
5959 | case '\0': case ',': | |
5960 | goto done; | |
a737bd4d | 5961 | |
c19d1205 ZW |
5962 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
5963 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
5964 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 5965 | |
c19d1205 ZW |
5966 | default: |
5967 | inst.error = _("unrecognized CPS flag"); | |
5968 | return FAIL; | |
5969 | } | |
a737bd4d | 5970 | |
c19d1205 ZW |
5971 | done: |
5972 | if (saw_a_flag == 0) | |
a737bd4d | 5973 | { |
c19d1205 ZW |
5974 | inst.error = _("missing CPS flags"); |
5975 | return FAIL; | |
a737bd4d | 5976 | } |
a737bd4d | 5977 | |
c19d1205 ZW |
5978 | *str = s - 1; |
5979 | return val; | |
a737bd4d NC |
5980 | } |
5981 | ||
c19d1205 ZW |
5982 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
5983 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
5984 | |
5985 | static int | |
c19d1205 | 5986 | parse_endian_specifier (char **str) |
a737bd4d | 5987 | { |
c19d1205 ZW |
5988 | int little_endian; |
5989 | char *s = *str; | |
a737bd4d | 5990 | |
c19d1205 ZW |
5991 | if (strncasecmp (s, "BE", 2)) |
5992 | little_endian = 0; | |
5993 | else if (strncasecmp (s, "LE", 2)) | |
5994 | little_endian = 1; | |
5995 | else | |
a737bd4d | 5996 | { |
c19d1205 | 5997 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5998 | return FAIL; |
5999 | } | |
6000 | ||
c19d1205 | 6001 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 6002 | { |
c19d1205 | 6003 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
6004 | return FAIL; |
6005 | } | |
6006 | ||
c19d1205 ZW |
6007 | *str = s + 2; |
6008 | return little_endian; | |
6009 | } | |
a737bd4d | 6010 | |
c19d1205 ZW |
6011 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
6012 | value suitable for poking into the rotate field of an sxt or sxta | |
6013 | instruction, or FAIL on error. */ | |
6014 | ||
6015 | static int | |
6016 | parse_ror (char **str) | |
6017 | { | |
6018 | int rot; | |
6019 | char *s = *str; | |
6020 | ||
6021 | if (strncasecmp (s, "ROR", 3) == 0) | |
6022 | s += 3; | |
6023 | else | |
a737bd4d | 6024 | { |
c19d1205 | 6025 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
6026 | return FAIL; |
6027 | } | |
c19d1205 ZW |
6028 | |
6029 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
6030 | return FAIL; | |
6031 | ||
6032 | switch (rot) | |
a737bd4d | 6033 | { |
c19d1205 ZW |
6034 | case 0: *str = s; return 0x0; |
6035 | case 8: *str = s; return 0x1; | |
6036 | case 16: *str = s; return 0x2; | |
6037 | case 24: *str = s; return 0x3; | |
6038 | ||
6039 | default: | |
6040 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
6041 | return FAIL; |
6042 | } | |
c19d1205 | 6043 | } |
a737bd4d | 6044 | |
c19d1205 ZW |
6045 | /* Parse a conditional code (from conds[] below). The value returned is in the |
6046 | range 0 .. 14, or FAIL. */ | |
6047 | static int | |
6048 | parse_cond (char **str) | |
6049 | { | |
c462b453 | 6050 | char *q; |
c19d1205 | 6051 | const struct asm_cond *c; |
c462b453 PB |
6052 | int n; |
6053 | /* Condition codes are always 2 characters, so matching up to | |
6054 | 3 characters is sufficient. */ | |
6055 | char cond[3]; | |
a737bd4d | 6056 | |
c462b453 PB |
6057 | q = *str; |
6058 | n = 0; | |
6059 | while (ISALPHA (*q) && n < 3) | |
6060 | { | |
e07e6e58 | 6061 | cond[n] = TOLOWER (*q); |
c462b453 PB |
6062 | q++; |
6063 | n++; | |
6064 | } | |
a737bd4d | 6065 | |
21d799b5 | 6066 | c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n); |
c19d1205 | 6067 | if (!c) |
a737bd4d | 6068 | { |
c19d1205 | 6069 | inst.error = _("condition required"); |
a737bd4d NC |
6070 | return FAIL; |
6071 | } | |
6072 | ||
c19d1205 ZW |
6073 | *str = q; |
6074 | return c->value; | |
6075 | } | |
6076 | ||
e797f7e0 MGD |
6077 | /* If the given feature available in the selected CPU, mark it as used. |
6078 | Returns TRUE iff feature is available. */ | |
6079 | static bfd_boolean | |
6080 | mark_feature_used (const arm_feature_set *feature) | |
6081 | { | |
6082 | /* Ensure the option is valid on the current architecture. */ | |
6083 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) | |
6084 | return FALSE; | |
6085 | ||
6086 | /* Add the appropriate architecture feature for the barrier option used. | |
6087 | */ | |
6088 | if (thumb_mode) | |
6089 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature); | |
6090 | else | |
6091 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature); | |
6092 | ||
6093 | return TRUE; | |
6094 | } | |
6095 | ||
62b3e311 PB |
6096 | /* Parse an option for a barrier instruction. Returns the encoding for the |
6097 | option, or FAIL. */ | |
6098 | static int | |
6099 | parse_barrier (char **str) | |
6100 | { | |
6101 | char *p, *q; | |
6102 | const struct asm_barrier_opt *o; | |
6103 | ||
6104 | p = q = *str; | |
6105 | while (ISALPHA (*q)) | |
6106 | q++; | |
6107 | ||
21d799b5 | 6108 | o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p, |
477330fc | 6109 | q - p); |
62b3e311 PB |
6110 | if (!o) |
6111 | return FAIL; | |
6112 | ||
e797f7e0 MGD |
6113 | if (!mark_feature_used (&o->arch)) |
6114 | return FAIL; | |
6115 | ||
62b3e311 PB |
6116 | *str = q; |
6117 | return o->value; | |
6118 | } | |
6119 | ||
92e90b6e PB |
6120 | /* Parse the operands of a table branch instruction. Similar to a memory |
6121 | operand. */ | |
6122 | static int | |
6123 | parse_tb (char **str) | |
6124 | { | |
6125 | char * p = *str; | |
6126 | int reg; | |
6127 | ||
6128 | if (skip_past_char (&p, '[') == FAIL) | |
ab1eb5fe PB |
6129 | { |
6130 | inst.error = _("'[' expected"); | |
6131 | return FAIL; | |
6132 | } | |
92e90b6e | 6133 | |
dcbf9037 | 6134 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
6135 | { |
6136 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
6137 | return FAIL; | |
6138 | } | |
6139 | inst.operands[0].reg = reg; | |
6140 | ||
6141 | if (skip_past_comma (&p) == FAIL) | |
ab1eb5fe PB |
6142 | { |
6143 | inst.error = _("',' expected"); | |
6144 | return FAIL; | |
6145 | } | |
5f4273c7 | 6146 | |
dcbf9037 | 6147 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
6148 | { |
6149 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
6150 | return FAIL; | |
6151 | } | |
6152 | inst.operands[0].imm = reg; | |
6153 | ||
6154 | if (skip_past_comma (&p) == SUCCESS) | |
6155 | { | |
6156 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
6157 | return FAIL; | |
6158 | if (inst.reloc.exp.X_add_number != 1) | |
6159 | { | |
6160 | inst.error = _("invalid shift"); | |
6161 | return FAIL; | |
6162 | } | |
6163 | inst.operands[0].shifted = 1; | |
6164 | } | |
6165 | ||
6166 | if (skip_past_char (&p, ']') == FAIL) | |
6167 | { | |
6168 | inst.error = _("']' expected"); | |
6169 | return FAIL; | |
6170 | } | |
6171 | *str = p; | |
6172 | return SUCCESS; | |
6173 | } | |
6174 | ||
5287ad62 JB |
6175 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
6176 | information on the types the operands can take and how they are encoded. | |
037e8744 JB |
6177 | Up to four operands may be read; this function handles setting the |
6178 | ".present" field for each read operand itself. | |
5287ad62 JB |
6179 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
6180 | else returns FAIL. */ | |
6181 | ||
6182 | static int | |
6183 | parse_neon_mov (char **str, int *which_operand) | |
6184 | { | |
6185 | int i = *which_operand, val; | |
6186 | enum arm_reg_type rtype; | |
6187 | char *ptr = *str; | |
dcbf9037 | 6188 | struct neon_type_el optype; |
5f4273c7 | 6189 | |
dcbf9037 | 6190 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
6191 | { |
6192 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ | |
6193 | inst.operands[i].reg = val; | |
6194 | inst.operands[i].isscalar = 1; | |
dcbf9037 | 6195 | inst.operands[i].vectype = optype; |
5287ad62 JB |
6196 | inst.operands[i++].present = 1; |
6197 | ||
6198 | if (skip_past_comma (&ptr) == FAIL) | |
477330fc | 6199 | goto wanted_comma; |
5f4273c7 | 6200 | |
dcbf9037 | 6201 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
477330fc | 6202 | goto wanted_arm; |
5f4273c7 | 6203 | |
5287ad62 JB |
6204 | inst.operands[i].reg = val; |
6205 | inst.operands[i].isreg = 1; | |
6206 | inst.operands[i].present = 1; | |
6207 | } | |
037e8744 | 6208 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
477330fc | 6209 | != FAIL) |
5287ad62 JB |
6210 | { |
6211 | /* Cases 0, 1, 2, 3, 5 (D only). */ | |
6212 | if (skip_past_comma (&ptr) == FAIL) | |
477330fc | 6213 | goto wanted_comma; |
5f4273c7 | 6214 | |
5287ad62 JB |
6215 | inst.operands[i].reg = val; |
6216 | inst.operands[i].isreg = 1; | |
6217 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
6218 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
6219 | inst.operands[i].isvec = 1; | |
dcbf9037 | 6220 | inst.operands[i].vectype = optype; |
5287ad62 JB |
6221 | inst.operands[i++].present = 1; |
6222 | ||
dcbf9037 | 6223 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
477330fc RM |
6224 | { |
6225 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. | |
6226 | Case 13: VMOV <Sd>, <Rm> */ | |
6227 | inst.operands[i].reg = val; | |
6228 | inst.operands[i].isreg = 1; | |
6229 | inst.operands[i].present = 1; | |
6230 | ||
6231 | if (rtype == REG_TYPE_NQ) | |
6232 | { | |
6233 | first_error (_("can't use Neon quad register here")); | |
6234 | return FAIL; | |
6235 | } | |
6236 | else if (rtype != REG_TYPE_VFS) | |
6237 | { | |
6238 | i++; | |
6239 | if (skip_past_comma (&ptr) == FAIL) | |
6240 | goto wanted_comma; | |
6241 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6242 | goto wanted_arm; | |
6243 | inst.operands[i].reg = val; | |
6244 | inst.operands[i].isreg = 1; | |
6245 | inst.operands[i].present = 1; | |
6246 | } | |
6247 | } | |
037e8744 | 6248 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, |
477330fc RM |
6249 | &optype)) != FAIL) |
6250 | { | |
6251 | /* Case 0: VMOV<c><q> <Qd>, <Qm> | |
6252 | Case 1: VMOV<c><q> <Dd>, <Dm> | |
6253 | Case 8: VMOV.F32 <Sd>, <Sm> | |
6254 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ | |
6255 | ||
6256 | inst.operands[i].reg = val; | |
6257 | inst.operands[i].isreg = 1; | |
6258 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
6259 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
6260 | inst.operands[i].isvec = 1; | |
6261 | inst.operands[i].vectype = optype; | |
6262 | inst.operands[i].present = 1; | |
6263 | ||
6264 | if (skip_past_comma (&ptr) == SUCCESS) | |
6265 | { | |
6266 | /* Case 15. */ | |
6267 | i++; | |
6268 | ||
6269 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6270 | goto wanted_arm; | |
6271 | ||
6272 | inst.operands[i].reg = val; | |
6273 | inst.operands[i].isreg = 1; | |
6274 | inst.operands[i++].present = 1; | |
6275 | ||
6276 | if (skip_past_comma (&ptr) == FAIL) | |
6277 | goto wanted_comma; | |
6278 | ||
6279 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6280 | goto wanted_arm; | |
6281 | ||
6282 | inst.operands[i].reg = val; | |
6283 | inst.operands[i].isreg = 1; | |
6284 | inst.operands[i].present = 1; | |
6285 | } | |
6286 | } | |
4641781c | 6287 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
477330fc RM |
6288 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> |
6289 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> | |
6290 | Case 10: VMOV.F32 <Sd>, #<imm> | |
6291 | Case 11: VMOV.F64 <Dd>, #<imm> */ | |
6292 | inst.operands[i].immisfloat = 1; | |
8335d6aa JW |
6293 | else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE) |
6294 | == SUCCESS) | |
477330fc RM |
6295 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> |
6296 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ | |
6297 | ; | |
5287ad62 | 6298 | else |
477330fc RM |
6299 | { |
6300 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); | |
6301 | return FAIL; | |
6302 | } | |
5287ad62 | 6303 | } |
dcbf9037 | 6304 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
6305 | { |
6306 | /* Cases 6, 7. */ | |
6307 | inst.operands[i].reg = val; | |
6308 | inst.operands[i].isreg = 1; | |
6309 | inst.operands[i++].present = 1; | |
5f4273c7 | 6310 | |
5287ad62 | 6311 | if (skip_past_comma (&ptr) == FAIL) |
477330fc | 6312 | goto wanted_comma; |
5f4273c7 | 6313 | |
dcbf9037 | 6314 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
477330fc RM |
6315 | { |
6316 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ | |
6317 | inst.operands[i].reg = val; | |
6318 | inst.operands[i].isscalar = 1; | |
6319 | inst.operands[i].present = 1; | |
6320 | inst.operands[i].vectype = optype; | |
6321 | } | |
dcbf9037 | 6322 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
477330fc RM |
6323 | { |
6324 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ | |
6325 | inst.operands[i].reg = val; | |
6326 | inst.operands[i].isreg = 1; | |
6327 | inst.operands[i++].present = 1; | |
6328 | ||
6329 | if (skip_past_comma (&ptr) == FAIL) | |
6330 | goto wanted_comma; | |
6331 | ||
6332 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) | |
6333 | == FAIL) | |
6334 | { | |
6335 | first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); | |
6336 | return FAIL; | |
6337 | } | |
6338 | ||
6339 | inst.operands[i].reg = val; | |
6340 | inst.operands[i].isreg = 1; | |
6341 | inst.operands[i].isvec = 1; | |
6342 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
6343 | inst.operands[i].vectype = optype; | |
6344 | inst.operands[i].present = 1; | |
6345 | ||
6346 | if (rtype == REG_TYPE_VFS) | |
6347 | { | |
6348 | /* Case 14. */ | |
6349 | i++; | |
6350 | if (skip_past_comma (&ptr) == FAIL) | |
6351 | goto wanted_comma; | |
6352 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, | |
6353 | &optype)) == FAIL) | |
6354 | { | |
6355 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); | |
6356 | return FAIL; | |
6357 | } | |
6358 | inst.operands[i].reg = val; | |
6359 | inst.operands[i].isreg = 1; | |
6360 | inst.operands[i].isvec = 1; | |
6361 | inst.operands[i].issingle = 1; | |
6362 | inst.operands[i].vectype = optype; | |
6363 | inst.operands[i].present = 1; | |
6364 | } | |
6365 | } | |
037e8744 | 6366 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) |
477330fc RM |
6367 | != FAIL) |
6368 | { | |
6369 | /* Case 13. */ | |
6370 | inst.operands[i].reg = val; | |
6371 | inst.operands[i].isreg = 1; | |
6372 | inst.operands[i].isvec = 1; | |
6373 | inst.operands[i].issingle = 1; | |
6374 | inst.operands[i].vectype = optype; | |
6375 | inst.operands[i].present = 1; | |
6376 | } | |
5287ad62 JB |
6377 | } |
6378 | else | |
6379 | { | |
dcbf9037 | 6380 | first_error (_("parse error")); |
5287ad62 JB |
6381 | return FAIL; |
6382 | } | |
6383 | ||
6384 | /* Successfully parsed the operands. Update args. */ | |
6385 | *which_operand = i; | |
6386 | *str = ptr; | |
6387 | return SUCCESS; | |
6388 | ||
5f4273c7 | 6389 | wanted_comma: |
dcbf9037 | 6390 | first_error (_("expected comma")); |
5287ad62 | 6391 | return FAIL; |
5f4273c7 NC |
6392 | |
6393 | wanted_arm: | |
dcbf9037 | 6394 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
5287ad62 | 6395 | return FAIL; |
5287ad62 JB |
6396 | } |
6397 | ||
5be8be5d DG |
6398 | /* Use this macro when the operand constraints are different |
6399 | for ARM and THUMB (e.g. ldrd). */ | |
6400 | #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \ | |
6401 | ((arm_operand) | ((thumb_operand) << 16)) | |
6402 | ||
c19d1205 ZW |
6403 | /* Matcher codes for parse_operands. */ |
6404 | enum operand_parse_code | |
6405 | { | |
6406 | OP_stop, /* end of line */ | |
6407 | ||
6408 | OP_RR, /* ARM register */ | |
6409 | OP_RRnpc, /* ARM register, not r15 */ | |
5be8be5d | 6410 | OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */ |
c19d1205 | 6411 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ |
fa94de6b | 6412 | OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback, |
55881a11 | 6413 | optional trailing ! */ |
c19d1205 ZW |
6414 | OP_RRw, /* ARM register, not r15, optional trailing ! */ |
6415 | OP_RCP, /* Coprocessor number */ | |
6416 | OP_RCN, /* Coprocessor register */ | |
6417 | OP_RF, /* FPA register */ | |
6418 | OP_RVS, /* VFP single precision register */ | |
5287ad62 JB |
6419 | OP_RVD, /* VFP double precision register (0..15) */ |
6420 | OP_RND, /* Neon double precision register (0..31) */ | |
6421 | OP_RNQ, /* Neon quad precision register */ | |
037e8744 | 6422 | OP_RVSD, /* VFP single or double precision register */ |
5287ad62 | 6423 | OP_RNDQ, /* Neon double or quad precision register */ |
037e8744 | 6424 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
5287ad62 | 6425 | OP_RNSC, /* Neon scalar D[X] */ |
c19d1205 ZW |
6426 | OP_RVC, /* VFP control register */ |
6427 | OP_RMF, /* Maverick F register */ | |
6428 | OP_RMD, /* Maverick D register */ | |
6429 | OP_RMFX, /* Maverick FX register */ | |
6430 | OP_RMDX, /* Maverick DX register */ | |
6431 | OP_RMAX, /* Maverick AX register */ | |
6432 | OP_RMDS, /* Maverick DSPSC register */ | |
6433 | OP_RIWR, /* iWMMXt wR register */ | |
6434 | OP_RIWC, /* iWMMXt wC register */ | |
6435 | OP_RIWG, /* iWMMXt wCG register */ | |
6436 | OP_RXA, /* XScale accumulator register */ | |
6437 | ||
6438 | OP_REGLST, /* ARM register list */ | |
6439 | OP_VRSLST, /* VFP single-precision register list */ | |
6440 | OP_VRDLST, /* VFP double-precision register list */ | |
037e8744 | 6441 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
5287ad62 JB |
6442 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
6443 | OP_NSTRLST, /* Neon element/structure list */ | |
6444 | ||
5287ad62 | 6445 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ |
037e8744 | 6446 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
aacf0b33 | 6447 | OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */ |
5287ad62 | 6448 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
037e8744 | 6449 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
5287ad62 JB |
6450 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
6451 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ | |
6452 | OP_VMOV, /* Neon VMOV operands. */ | |
4316f0d2 | 6453 | OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ |
5287ad62 | 6454 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ |
2d447fca | 6455 | OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ |
5287ad62 JB |
6456 | |
6457 | OP_I0, /* immediate zero */ | |
c19d1205 ZW |
6458 | OP_I7, /* immediate value 0 .. 7 */ |
6459 | OP_I15, /* 0 .. 15 */ | |
6460 | OP_I16, /* 1 .. 16 */ | |
5287ad62 | 6461 | OP_I16z, /* 0 .. 16 */ |
c19d1205 ZW |
6462 | OP_I31, /* 0 .. 31 */ |
6463 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
6464 | OP_I32, /* 1 .. 32 */ | |
5287ad62 JB |
6465 | OP_I32z, /* 0 .. 32 */ |
6466 | OP_I63, /* 0 .. 63 */ | |
c19d1205 | 6467 | OP_I63s, /* -64 .. 63 */ |
5287ad62 JB |
6468 | OP_I64, /* 1 .. 64 */ |
6469 | OP_I64z, /* 0 .. 64 */ | |
c19d1205 | 6470 | OP_I255, /* 0 .. 255 */ |
c19d1205 ZW |
6471 | |
6472 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
6473 | OP_I7b, /* 0 .. 7 */ | |
6474 | OP_I15b, /* 0 .. 15 */ | |
6475 | OP_I31b, /* 0 .. 31 */ | |
6476 | ||
6477 | OP_SH, /* shifter operand */ | |
4962c51a | 6478 | OP_SHG, /* shifter operand with possible group relocation */ |
c19d1205 | 6479 | OP_ADDR, /* Memory address expression (any mode) */ |
4962c51a MS |
6480 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
6481 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ | |
6482 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ | |
c19d1205 ZW |
6483 | OP_EXP, /* arbitrary expression */ |
6484 | OP_EXPi, /* same, with optional immediate prefix */ | |
6485 | OP_EXPr, /* same, with optional relocation suffix */ | |
b6895b4f | 6486 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
c19d1205 ZW |
6487 | |
6488 | OP_CPSF, /* CPS flags */ | |
6489 | OP_ENDI, /* Endianness specifier */ | |
d2cd1205 JB |
6490 | OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */ |
6491 | OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */ | |
c19d1205 | 6492 | OP_COND, /* conditional code */ |
92e90b6e | 6493 | OP_TB, /* Table branch. */ |
c19d1205 | 6494 | |
037e8744 JB |
6495 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ |
6496 | ||
c19d1205 ZW |
6497 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
6498 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
6499 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
6500 | OP_RF_IF, /* FPA register or immediate */ | |
6501 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
41adaa5c | 6502 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
c19d1205 ZW |
6503 | |
6504 | /* Optional operands. */ | |
6505 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
6506 | OP_oI31b, /* 0 .. 31 */ | |
5287ad62 | 6507 | OP_oI32b, /* 1 .. 32 */ |
5f1af56b | 6508 | OP_oI32z, /* 0 .. 32 */ |
c19d1205 ZW |
6509 | OP_oIffffb, /* 0 .. 65535 */ |
6510 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
6511 | ||
6512 | OP_oRR, /* ARM register */ | |
6513 | OP_oRRnpc, /* ARM register, not the PC */ | |
5be8be5d | 6514 | OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ |
b6702015 | 6515 | OP_oRRw, /* ARM register, not r15, optional trailing ! */ |
5287ad62 JB |
6516 | OP_oRND, /* Optional Neon double precision register */ |
6517 | OP_oRNQ, /* Optional Neon quad precision register */ | |
6518 | OP_oRNDQ, /* Optional Neon double or quad precision register */ | |
037e8744 | 6519 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
c19d1205 ZW |
6520 | OP_oSHll, /* LSL immediate */ |
6521 | OP_oSHar, /* ASR immediate */ | |
6522 | OP_oSHllar, /* LSL or ASR immediate */ | |
6523 | OP_oROR, /* ROR 0/8/16/24 */ | |
52e7f43d | 6524 | OP_oBARRIER_I15, /* Option argument for a barrier instruction. */ |
c19d1205 | 6525 | |
5be8be5d DG |
6526 | /* Some pre-defined mixed (ARM/THUMB) operands. */ |
6527 | OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp), | |
6528 | OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp), | |
6529 | OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp), | |
6530 | ||
c19d1205 ZW |
6531 | OP_FIRST_OPTIONAL = OP_oI7b |
6532 | }; | |
a737bd4d | 6533 | |
c19d1205 ZW |
6534 | /* Generic instruction operand parser. This does no encoding and no |
6535 | semantic validation; it merely squirrels values away in the inst | |
6536 | structure. Returns SUCCESS or FAIL depending on whether the | |
6537 | specified grammar matched. */ | |
6538 | static int | |
5be8be5d | 6539 | parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) |
c19d1205 | 6540 | { |
5be8be5d | 6541 | unsigned const int *upat = pattern; |
c19d1205 ZW |
6542 | char *backtrack_pos = 0; |
6543 | const char *backtrack_error = 0; | |
99aad254 | 6544 | int i, val = 0, backtrack_index = 0; |
5287ad62 | 6545 | enum arm_reg_type rtype; |
4962c51a | 6546 | parse_operand_result result; |
5be8be5d | 6547 | unsigned int op_parse_code; |
c19d1205 | 6548 | |
e07e6e58 NC |
6549 | #define po_char_or_fail(chr) \ |
6550 | do \ | |
6551 | { \ | |
6552 | if (skip_past_char (&str, chr) == FAIL) \ | |
477330fc | 6553 | goto bad_args; \ |
e07e6e58 NC |
6554 | } \ |
6555 | while (0) | |
c19d1205 | 6556 | |
e07e6e58 NC |
6557 | #define po_reg_or_fail(regtype) \ |
6558 | do \ | |
dcbf9037 | 6559 | { \ |
e07e6e58 | 6560 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
477330fc | 6561 | & inst.operands[i].vectype); \ |
e07e6e58 | 6562 | if (val == FAIL) \ |
477330fc RM |
6563 | { \ |
6564 | first_error (_(reg_expected_msgs[regtype])); \ | |
6565 | goto failure; \ | |
6566 | } \ | |
e07e6e58 NC |
6567 | inst.operands[i].reg = val; \ |
6568 | inst.operands[i].isreg = 1; \ | |
6569 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6570 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6571 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
477330fc RM |
6572 | || rtype == REG_TYPE_VFD \ |
6573 | || rtype == REG_TYPE_NQ); \ | |
dcbf9037 | 6574 | } \ |
e07e6e58 NC |
6575 | while (0) |
6576 | ||
6577 | #define po_reg_or_goto(regtype, label) \ | |
6578 | do \ | |
6579 | { \ | |
6580 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ | |
6581 | & inst.operands[i].vectype); \ | |
6582 | if (val == FAIL) \ | |
6583 | goto label; \ | |
dcbf9037 | 6584 | \ |
e07e6e58 NC |
6585 | inst.operands[i].reg = val; \ |
6586 | inst.operands[i].isreg = 1; \ | |
6587 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6588 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6589 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
477330fc | 6590 | || rtype == REG_TYPE_VFD \ |
e07e6e58 NC |
6591 | || rtype == REG_TYPE_NQ); \ |
6592 | } \ | |
6593 | while (0) | |
6594 | ||
6595 | #define po_imm_or_fail(min, max, popt) \ | |
6596 | do \ | |
6597 | { \ | |
6598 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
6599 | goto failure; \ | |
6600 | inst.operands[i].imm = val; \ | |
6601 | } \ | |
6602 | while (0) | |
6603 | ||
6604 | #define po_scalar_or_goto(elsz, label) \ | |
6605 | do \ | |
6606 | { \ | |
6607 | val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \ | |
6608 | if (val == FAIL) \ | |
6609 | goto label; \ | |
6610 | inst.operands[i].reg = val; \ | |
6611 | inst.operands[i].isscalar = 1; \ | |
6612 | } \ | |
6613 | while (0) | |
6614 | ||
6615 | #define po_misc_or_fail(expr) \ | |
6616 | do \ | |
6617 | { \ | |
6618 | if (expr) \ | |
6619 | goto failure; \ | |
6620 | } \ | |
6621 | while (0) | |
6622 | ||
6623 | #define po_misc_or_fail_no_backtrack(expr) \ | |
6624 | do \ | |
6625 | { \ | |
6626 | result = expr; \ | |
6627 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ | |
6628 | backtrack_pos = 0; \ | |
6629 | if (result != PARSE_OPERAND_SUCCESS) \ | |
6630 | goto failure; \ | |
6631 | } \ | |
6632 | while (0) | |
4962c51a | 6633 | |
52e7f43d RE |
6634 | #define po_barrier_or_imm(str) \ |
6635 | do \ | |
6636 | { \ | |
6637 | val = parse_barrier (&str); \ | |
ccb84d65 JB |
6638 | if (val == FAIL && ! ISALPHA (*str)) \ |
6639 | goto immediate; \ | |
6640 | if (val == FAIL \ | |
6641 | /* ISB can only take SY as an option. */ \ | |
6642 | || ((inst.instruction & 0xf0) == 0x60 \ | |
6643 | && val != 0xf)) \ | |
52e7f43d | 6644 | { \ |
ccb84d65 JB |
6645 | inst.error = _("invalid barrier type"); \ |
6646 | backtrack_pos = 0; \ | |
6647 | goto failure; \ | |
52e7f43d RE |
6648 | } \ |
6649 | } \ | |
6650 | while (0) | |
6651 | ||
c19d1205 ZW |
6652 | skip_whitespace (str); |
6653 | ||
6654 | for (i = 0; upat[i] != OP_stop; i++) | |
6655 | { | |
5be8be5d DG |
6656 | op_parse_code = upat[i]; |
6657 | if (op_parse_code >= 1<<16) | |
6658 | op_parse_code = thumb ? (op_parse_code >> 16) | |
6659 | : (op_parse_code & ((1<<16)-1)); | |
6660 | ||
6661 | if (op_parse_code >= OP_FIRST_OPTIONAL) | |
c19d1205 ZW |
6662 | { |
6663 | /* Remember where we are in case we need to backtrack. */ | |
9c2799c2 | 6664 | gas_assert (!backtrack_pos); |
c19d1205 ZW |
6665 | backtrack_pos = str; |
6666 | backtrack_error = inst.error; | |
6667 | backtrack_index = i; | |
6668 | } | |
6669 | ||
b6702015 | 6670 | if (i > 0 && (i > 1 || inst.operands[0].present)) |
c19d1205 ZW |
6671 | po_char_or_fail (','); |
6672 | ||
5be8be5d | 6673 | switch (op_parse_code) |
c19d1205 ZW |
6674 | { |
6675 | /* Registers */ | |
6676 | case OP_oRRnpc: | |
5be8be5d | 6677 | case OP_oRRnpcsp: |
c19d1205 | 6678 | case OP_RRnpc: |
5be8be5d | 6679 | case OP_RRnpcsp: |
c19d1205 ZW |
6680 | case OP_oRR: |
6681 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
6682 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
6683 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
6684 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
6685 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
6686 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
477330fc | 6687 | case OP_oRND: |
5287ad62 | 6688 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; |
cd2cf30b PB |
6689 | case OP_RVC: |
6690 | po_reg_or_goto (REG_TYPE_VFC, coproc_reg); | |
6691 | break; | |
6692 | /* Also accept generic coprocessor regs for unknown registers. */ | |
6693 | coproc_reg: | |
6694 | po_reg_or_fail (REG_TYPE_CN); | |
6695 | break; | |
c19d1205 ZW |
6696 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; |
6697 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
6698 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
6699 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
6700 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
6701 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
6702 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
6703 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
6704 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
6705 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
477330fc | 6706 | case OP_oRNQ: |
5287ad62 | 6707 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; |
477330fc | 6708 | case OP_oRNDQ: |
5287ad62 | 6709 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; |
477330fc RM |
6710 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
6711 | case OP_oRNSDQ: | |
6712 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; | |
6713 | ||
6714 | /* Neon scalar. Using an element size of 8 means that some invalid | |
6715 | scalars are accepted here, so deal with those in later code. */ | |
6716 | case OP_RNSC: po_scalar_or_goto (8, failure); break; | |
6717 | ||
6718 | case OP_RNDQ_I0: | |
6719 | { | |
6720 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); | |
6721 | break; | |
6722 | try_imm0: | |
6723 | po_imm_or_fail (0, 0, TRUE); | |
6724 | } | |
6725 | break; | |
6726 | ||
6727 | case OP_RVSD_I0: | |
6728 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); | |
6729 | break; | |
6730 | ||
aacf0b33 KT |
6731 | case OP_RSVD_FI0: |
6732 | { | |
6733 | po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0); | |
6734 | break; | |
6735 | try_ifimm0: | |
6736 | if (parse_ifimm_zero (&str)) | |
6737 | inst.operands[i].imm = 0; | |
6738 | else | |
6739 | { | |
6740 | inst.error | |
6741 | = _("only floating point zero is allowed as immediate value"); | |
6742 | goto failure; | |
6743 | } | |
6744 | } | |
6745 | break; | |
6746 | ||
477330fc RM |
6747 | case OP_RR_RNSC: |
6748 | { | |
6749 | po_scalar_or_goto (8, try_rr); | |
6750 | break; | |
6751 | try_rr: | |
6752 | po_reg_or_fail (REG_TYPE_RN); | |
6753 | } | |
6754 | break; | |
6755 | ||
6756 | case OP_RNSDQ_RNSC: | |
6757 | { | |
6758 | po_scalar_or_goto (8, try_nsdq); | |
6759 | break; | |
6760 | try_nsdq: | |
6761 | po_reg_or_fail (REG_TYPE_NSDQ); | |
6762 | } | |
6763 | break; | |
6764 | ||
6765 | case OP_RNDQ_RNSC: | |
6766 | { | |
6767 | po_scalar_or_goto (8, try_ndq); | |
6768 | break; | |
6769 | try_ndq: | |
6770 | po_reg_or_fail (REG_TYPE_NDQ); | |
6771 | } | |
6772 | break; | |
6773 | ||
6774 | case OP_RND_RNSC: | |
6775 | { | |
6776 | po_scalar_or_goto (8, try_vfd); | |
6777 | break; | |
6778 | try_vfd: | |
6779 | po_reg_or_fail (REG_TYPE_VFD); | |
6780 | } | |
6781 | break; | |
6782 | ||
6783 | case OP_VMOV: | |
6784 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're | |
6785 | not careful then bad things might happen. */ | |
6786 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); | |
6787 | break; | |
6788 | ||
6789 | case OP_RNDQ_Ibig: | |
6790 | { | |
6791 | po_reg_or_goto (REG_TYPE_NDQ, try_immbig); | |
6792 | break; | |
6793 | try_immbig: | |
6794 | /* There's a possibility of getting a 64-bit immediate here, so | |
6795 | we need special handling. */ | |
8335d6aa JW |
6796 | if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE) |
6797 | == FAIL) | |
477330fc RM |
6798 | { |
6799 | inst.error = _("immediate value is out of range"); | |
6800 | goto failure; | |
6801 | } | |
6802 | } | |
6803 | break; | |
6804 | ||
6805 | case OP_RNDQ_I63b: | |
6806 | { | |
6807 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); | |
6808 | break; | |
6809 | try_shimm: | |
6810 | po_imm_or_fail (0, 63, TRUE); | |
6811 | } | |
6812 | break; | |
c19d1205 ZW |
6813 | |
6814 | case OP_RRnpcb: | |
6815 | po_char_or_fail ('['); | |
6816 | po_reg_or_fail (REG_TYPE_RN); | |
6817 | po_char_or_fail (']'); | |
6818 | break; | |
a737bd4d | 6819 | |
55881a11 | 6820 | case OP_RRnpctw: |
c19d1205 | 6821 | case OP_RRw: |
b6702015 | 6822 | case OP_oRRw: |
c19d1205 ZW |
6823 | po_reg_or_fail (REG_TYPE_RN); |
6824 | if (skip_past_char (&str, '!') == SUCCESS) | |
6825 | inst.operands[i].writeback = 1; | |
6826 | break; | |
6827 | ||
6828 | /* Immediates */ | |
6829 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
6830 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
6831 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
477330fc | 6832 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
c19d1205 ZW |
6833 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
6834 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
477330fc | 6835 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
c19d1205 | 6836 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
477330fc RM |
6837 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
6838 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; | |
6839 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; | |
c19d1205 | 6840 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
c19d1205 ZW |
6841 | |
6842 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
6843 | case OP_oI7b: | |
6844 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
6845 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
6846 | case OP_oI31b: | |
6847 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
477330fc RM |
6848 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
6849 | case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break; | |
c19d1205 ZW |
6850 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
6851 | ||
6852 | /* Immediate variants */ | |
6853 | case OP_oI255c: | |
6854 | po_char_or_fail ('{'); | |
6855 | po_imm_or_fail (0, 255, TRUE); | |
6856 | po_char_or_fail ('}'); | |
6857 | break; | |
6858 | ||
6859 | case OP_I31w: | |
6860 | /* The expression parser chokes on a trailing !, so we have | |
6861 | to find it first and zap it. */ | |
6862 | { | |
6863 | char *s = str; | |
6864 | while (*s && *s != ',') | |
6865 | s++; | |
6866 | if (s[-1] == '!') | |
6867 | { | |
6868 | s[-1] = '\0'; | |
6869 | inst.operands[i].writeback = 1; | |
6870 | } | |
6871 | po_imm_or_fail (0, 31, TRUE); | |
6872 | if (str == s - 1) | |
6873 | str = s; | |
6874 | } | |
6875 | break; | |
6876 | ||
6877 | /* Expressions */ | |
6878 | case OP_EXPi: EXPi: | |
6879 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6880 | GE_OPT_PREFIX)); | |
6881 | break; | |
6882 | ||
6883 | case OP_EXP: | |
6884 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6885 | GE_NO_PREFIX)); | |
6886 | break; | |
6887 | ||
6888 | case OP_EXPr: EXPr: | |
6889 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6890 | GE_NO_PREFIX)); | |
6891 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 6892 | { |
c19d1205 ZW |
6893 | val = parse_reloc (&str); |
6894 | if (val == -1) | |
6895 | { | |
6896 | inst.error = _("unrecognized relocation suffix"); | |
6897 | goto failure; | |
6898 | } | |
6899 | else if (val != BFD_RELOC_UNUSED) | |
6900 | { | |
6901 | inst.operands[i].imm = val; | |
6902 | inst.operands[i].hasreloc = 1; | |
6903 | } | |
a737bd4d | 6904 | } |
c19d1205 | 6905 | break; |
a737bd4d | 6906 | |
b6895b4f PB |
6907 | /* Operand for MOVW or MOVT. */ |
6908 | case OP_HALF: | |
6909 | po_misc_or_fail (parse_half (&str)); | |
6910 | break; | |
6911 | ||
e07e6e58 | 6912 | /* Register or expression. */ |
c19d1205 ZW |
6913 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; |
6914 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 6915 | |
e07e6e58 | 6916 | /* Register or immediate. */ |
c19d1205 ZW |
6917 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; |
6918 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 6919 | |
c19d1205 ZW |
6920 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
6921 | IF: | |
6922 | if (!is_immediate_prefix (*str)) | |
6923 | goto bad_args; | |
6924 | str++; | |
6925 | val = parse_fpa_immediate (&str); | |
6926 | if (val == FAIL) | |
6927 | goto failure; | |
6928 | /* FPA immediates are encoded as registers 8-15. | |
6929 | parse_fpa_immediate has already applied the offset. */ | |
6930 | inst.operands[i].reg = val; | |
6931 | inst.operands[i].isreg = 1; | |
6932 | break; | |
09d92015 | 6933 | |
2d447fca JM |
6934 | case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; |
6935 | I32z: po_imm_or_fail (0, 32, FALSE); break; | |
6936 | ||
e07e6e58 | 6937 | /* Two kinds of register. */ |
c19d1205 ZW |
6938 | case OP_RIWR_RIWC: |
6939 | { | |
6940 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
97f87066 JM |
6941 | if (!rege |
6942 | || (rege->type != REG_TYPE_MMXWR | |
6943 | && rege->type != REG_TYPE_MMXWC | |
6944 | && rege->type != REG_TYPE_MMXWCG)) | |
c19d1205 ZW |
6945 | { |
6946 | inst.error = _("iWMMXt data or control register expected"); | |
6947 | goto failure; | |
6948 | } | |
6949 | inst.operands[i].reg = rege->number; | |
6950 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
6951 | } | |
6952 | break; | |
09d92015 | 6953 | |
41adaa5c JM |
6954 | case OP_RIWC_RIWG: |
6955 | { | |
6956 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
6957 | if (!rege | |
6958 | || (rege->type != REG_TYPE_MMXWC | |
6959 | && rege->type != REG_TYPE_MMXWCG)) | |
6960 | { | |
6961 | inst.error = _("iWMMXt control register expected"); | |
6962 | goto failure; | |
6963 | } | |
6964 | inst.operands[i].reg = rege->number; | |
6965 | inst.operands[i].isreg = 1; | |
6966 | } | |
6967 | break; | |
6968 | ||
c19d1205 ZW |
6969 | /* Misc */ |
6970 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
6971 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
6972 | case OP_oROR: val = parse_ror (&str); break; | |
c19d1205 | 6973 | case OP_COND: val = parse_cond (&str); break; |
52e7f43d RE |
6974 | case OP_oBARRIER_I15: |
6975 | po_barrier_or_imm (str); break; | |
6976 | immediate: | |
6977 | if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL) | |
477330fc | 6978 | goto failure; |
52e7f43d | 6979 | break; |
c19d1205 | 6980 | |
fa94de6b | 6981 | case OP_wPSR: |
d2cd1205 | 6982 | case OP_rPSR: |
90ec0d68 MGD |
6983 | po_reg_or_goto (REG_TYPE_RNB, try_psr); |
6984 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt)) | |
6985 | { | |
6986 | inst.error = _("Banked registers are not available with this " | |
6987 | "architecture."); | |
6988 | goto failure; | |
6989 | } | |
6990 | break; | |
d2cd1205 JB |
6991 | try_psr: |
6992 | val = parse_psr (&str, op_parse_code == OP_wPSR); | |
6993 | break; | |
037e8744 | 6994 | |
477330fc RM |
6995 | case OP_APSR_RR: |
6996 | po_reg_or_goto (REG_TYPE_RN, try_apsr); | |
6997 | break; | |
6998 | try_apsr: | |
6999 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS | |
7000 | instruction). */ | |
7001 | if (strncasecmp (str, "APSR_", 5) == 0) | |
7002 | { | |
7003 | unsigned found = 0; | |
7004 | str += 5; | |
7005 | while (found < 15) | |
7006 | switch (*str++) | |
7007 | { | |
7008 | case 'c': found = (found & 1) ? 16 : found | 1; break; | |
7009 | case 'n': found = (found & 2) ? 16 : found | 2; break; | |
7010 | case 'z': found = (found & 4) ? 16 : found | 4; break; | |
7011 | case 'v': found = (found & 8) ? 16 : found | 8; break; | |
7012 | default: found = 16; | |
7013 | } | |
7014 | if (found != 15) | |
7015 | goto failure; | |
7016 | inst.operands[i].isvec = 1; | |
f7c21dc7 NC |
7017 | /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */ |
7018 | inst.operands[i].reg = REG_PC; | |
477330fc RM |
7019 | } |
7020 | else | |
7021 | goto failure; | |
7022 | break; | |
037e8744 | 7023 | |
92e90b6e PB |
7024 | case OP_TB: |
7025 | po_misc_or_fail (parse_tb (&str)); | |
7026 | break; | |
7027 | ||
e07e6e58 | 7028 | /* Register lists. */ |
c19d1205 ZW |
7029 | case OP_REGLST: |
7030 | val = parse_reg_list (&str); | |
7031 | if (*str == '^') | |
7032 | { | |
7033 | inst.operands[1].writeback = 1; | |
7034 | str++; | |
7035 | } | |
7036 | break; | |
09d92015 | 7037 | |
c19d1205 | 7038 | case OP_VRSLST: |
5287ad62 | 7039 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); |
c19d1205 | 7040 | break; |
09d92015 | 7041 | |
c19d1205 | 7042 | case OP_VRDLST: |
5287ad62 | 7043 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); |
c19d1205 | 7044 | break; |
a737bd4d | 7045 | |
477330fc RM |
7046 | case OP_VRSDLST: |
7047 | /* Allow Q registers too. */ | |
7048 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7049 | REGLIST_NEON_D); | |
7050 | if (val == FAIL) | |
7051 | { | |
7052 | inst.error = NULL; | |
7053 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7054 | REGLIST_VFP_S); | |
7055 | inst.operands[i].issingle = 1; | |
7056 | } | |
7057 | break; | |
7058 | ||
7059 | case OP_NRDLST: | |
7060 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7061 | REGLIST_NEON_D); | |
7062 | break; | |
5287ad62 JB |
7063 | |
7064 | case OP_NSTRLST: | |
477330fc RM |
7065 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
7066 | &inst.operands[i].vectype); | |
7067 | break; | |
5287ad62 | 7068 | |
c19d1205 ZW |
7069 | /* Addressing modes */ |
7070 | case OP_ADDR: | |
7071 | po_misc_or_fail (parse_address (&str, i)); | |
7072 | break; | |
09d92015 | 7073 | |
4962c51a MS |
7074 | case OP_ADDRGLDR: |
7075 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7076 | parse_address_group_reloc (&str, i, GROUP_LDR)); |
4962c51a MS |
7077 | break; |
7078 | ||
7079 | case OP_ADDRGLDRS: | |
7080 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7081 | parse_address_group_reloc (&str, i, GROUP_LDRS)); |
4962c51a MS |
7082 | break; |
7083 | ||
7084 | case OP_ADDRGLDC: | |
7085 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7086 | parse_address_group_reloc (&str, i, GROUP_LDC)); |
4962c51a MS |
7087 | break; |
7088 | ||
c19d1205 ZW |
7089 | case OP_SH: |
7090 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
7091 | break; | |
09d92015 | 7092 | |
4962c51a MS |
7093 | case OP_SHG: |
7094 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7095 | parse_shifter_operand_group_reloc (&str, i)); |
4962c51a MS |
7096 | break; |
7097 | ||
c19d1205 ZW |
7098 | case OP_oSHll: |
7099 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
7100 | break; | |
09d92015 | 7101 | |
c19d1205 ZW |
7102 | case OP_oSHar: |
7103 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
7104 | break; | |
09d92015 | 7105 | |
c19d1205 ZW |
7106 | case OP_oSHllar: |
7107 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
7108 | break; | |
09d92015 | 7109 | |
c19d1205 | 7110 | default: |
5be8be5d | 7111 | as_fatal (_("unhandled operand code %d"), op_parse_code); |
c19d1205 | 7112 | } |
09d92015 | 7113 | |
c19d1205 ZW |
7114 | /* Various value-based sanity checks and shared operations. We |
7115 | do not signal immediate failures for the register constraints; | |
7116 | this allows a syntax error to take precedence. */ | |
5be8be5d | 7117 | switch (op_parse_code) |
c19d1205 ZW |
7118 | { |
7119 | case OP_oRRnpc: | |
7120 | case OP_RRnpc: | |
7121 | case OP_RRnpcb: | |
7122 | case OP_RRw: | |
b6702015 | 7123 | case OP_oRRw: |
c19d1205 ZW |
7124 | case OP_RRnpc_I0: |
7125 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
7126 | inst.error = BAD_PC; | |
7127 | break; | |
09d92015 | 7128 | |
5be8be5d DG |
7129 | case OP_oRRnpcsp: |
7130 | case OP_RRnpcsp: | |
7131 | if (inst.operands[i].isreg) | |
7132 | { | |
7133 | if (inst.operands[i].reg == REG_PC) | |
7134 | inst.error = BAD_PC; | |
7135 | else if (inst.operands[i].reg == REG_SP) | |
7136 | inst.error = BAD_SP; | |
7137 | } | |
7138 | break; | |
7139 | ||
55881a11 | 7140 | case OP_RRnpctw: |
fa94de6b RM |
7141 | if (inst.operands[i].isreg |
7142 | && inst.operands[i].reg == REG_PC | |
55881a11 MGD |
7143 | && (inst.operands[i].writeback || thumb)) |
7144 | inst.error = BAD_PC; | |
7145 | break; | |
7146 | ||
c19d1205 ZW |
7147 | case OP_CPSF: |
7148 | case OP_ENDI: | |
7149 | case OP_oROR: | |
d2cd1205 JB |
7150 | case OP_wPSR: |
7151 | case OP_rPSR: | |
c19d1205 | 7152 | case OP_COND: |
52e7f43d | 7153 | case OP_oBARRIER_I15: |
c19d1205 ZW |
7154 | case OP_REGLST: |
7155 | case OP_VRSLST: | |
7156 | case OP_VRDLST: | |
477330fc RM |
7157 | case OP_VRSDLST: |
7158 | case OP_NRDLST: | |
7159 | case OP_NSTRLST: | |
c19d1205 ZW |
7160 | if (val == FAIL) |
7161 | goto failure; | |
7162 | inst.operands[i].imm = val; | |
7163 | break; | |
a737bd4d | 7164 | |
c19d1205 ZW |
7165 | default: |
7166 | break; | |
7167 | } | |
09d92015 | 7168 | |
c19d1205 ZW |
7169 | /* If we get here, this operand was successfully parsed. */ |
7170 | inst.operands[i].present = 1; | |
7171 | continue; | |
09d92015 | 7172 | |
c19d1205 | 7173 | bad_args: |
09d92015 | 7174 | inst.error = BAD_ARGS; |
c19d1205 ZW |
7175 | |
7176 | failure: | |
7177 | if (!backtrack_pos) | |
d252fdde PB |
7178 | { |
7179 | /* The parse routine should already have set inst.error, but set a | |
5f4273c7 | 7180 | default here just in case. */ |
d252fdde PB |
7181 | if (!inst.error) |
7182 | inst.error = _("syntax error"); | |
7183 | return FAIL; | |
7184 | } | |
c19d1205 ZW |
7185 | |
7186 | /* Do not backtrack over a trailing optional argument that | |
7187 | absorbed some text. We will only fail again, with the | |
7188 | 'garbage following instruction' error message, which is | |
7189 | probably less helpful than the current one. */ | |
7190 | if (backtrack_index == i && backtrack_pos != str | |
7191 | && upat[i+1] == OP_stop) | |
d252fdde PB |
7192 | { |
7193 | if (!inst.error) | |
7194 | inst.error = _("syntax error"); | |
7195 | return FAIL; | |
7196 | } | |
c19d1205 ZW |
7197 | |
7198 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
7199 | str = backtrack_pos; | |
7200 | inst.error = backtrack_error; | |
7201 | inst.operands[backtrack_index].present = 0; | |
7202 | i = backtrack_index; | |
7203 | backtrack_pos = 0; | |
09d92015 | 7204 | } |
09d92015 | 7205 | |
c19d1205 ZW |
7206 | /* Check that we have parsed all the arguments. */ |
7207 | if (*str != '\0' && !inst.error) | |
7208 | inst.error = _("garbage following instruction"); | |
09d92015 | 7209 | |
c19d1205 | 7210 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
7211 | } |
7212 | ||
c19d1205 ZW |
7213 | #undef po_char_or_fail |
7214 | #undef po_reg_or_fail | |
7215 | #undef po_reg_or_goto | |
7216 | #undef po_imm_or_fail | |
5287ad62 | 7217 | #undef po_scalar_or_fail |
52e7f43d | 7218 | #undef po_barrier_or_imm |
e07e6e58 | 7219 | |
c19d1205 | 7220 | /* Shorthand macro for instruction encoding functions issuing errors. */ |
e07e6e58 NC |
7221 | #define constraint(expr, err) \ |
7222 | do \ | |
c19d1205 | 7223 | { \ |
e07e6e58 NC |
7224 | if (expr) \ |
7225 | { \ | |
7226 | inst.error = err; \ | |
7227 | return; \ | |
7228 | } \ | |
c19d1205 | 7229 | } \ |
e07e6e58 | 7230 | while (0) |
c19d1205 | 7231 | |
fdfde340 JM |
7232 | /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 |
7233 | instructions are unpredictable if these registers are used. This | |
7234 | is the BadReg predicate in ARM's Thumb-2 documentation. */ | |
7235 | #define reject_bad_reg(reg) \ | |
7236 | do \ | |
7237 | if (reg == REG_SP || reg == REG_PC) \ | |
7238 | { \ | |
7239 | inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \ | |
7240 | return; \ | |
7241 | } \ | |
7242 | while (0) | |
7243 | ||
94206790 MM |
7244 | /* If REG is R13 (the stack pointer), warn that its use is |
7245 | deprecated. */ | |
7246 | #define warn_deprecated_sp(reg) \ | |
7247 | do \ | |
7248 | if (warn_on_deprecated && reg == REG_SP) \ | |
7249 | as_warn (_("use of r13 is deprecated")); \ | |
7250 | while (0) | |
7251 | ||
c19d1205 ZW |
7252 | /* Functions for operand encoding. ARM, then Thumb. */ |
7253 | ||
d840c081 | 7254 | #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31)) |
c19d1205 ZW |
7255 | |
7256 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
7257 | return the encoded form. Otherwise, return FAIL. */ | |
7258 | ||
7259 | static unsigned int | |
7260 | encode_arm_immediate (unsigned int val) | |
09d92015 | 7261 | { |
c19d1205 ZW |
7262 | unsigned int a, i; |
7263 | ||
7264 | for (i = 0; i < 32; i += 2) | |
7265 | if ((a = rotate_left (val, i)) <= 0xff) | |
7266 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
7267 | ||
7268 | return FAIL; | |
09d92015 MM |
7269 | } |
7270 | ||
c19d1205 ZW |
7271 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
7272 | return the encoded form. Otherwise, return FAIL. */ | |
7273 | static unsigned int | |
7274 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 7275 | { |
c19d1205 | 7276 | unsigned int a, i; |
09d92015 | 7277 | |
9c3c69f2 | 7278 | if (val <= 0xff) |
c19d1205 | 7279 | return val; |
a737bd4d | 7280 | |
9c3c69f2 | 7281 | for (i = 1; i <= 24; i++) |
09d92015 | 7282 | { |
9c3c69f2 PB |
7283 | a = val >> i; |
7284 | if ((val & ~(0xff << i)) == 0) | |
7285 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 7286 | } |
a737bd4d | 7287 | |
c19d1205 ZW |
7288 | a = val & 0xff; |
7289 | if (val == ((a << 16) | a)) | |
7290 | return 0x100 | a; | |
7291 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
7292 | return 0x300 | a; | |
09d92015 | 7293 | |
c19d1205 ZW |
7294 | a = val & 0xff00; |
7295 | if (val == ((a << 16) | a)) | |
7296 | return 0x200 | (a >> 8); | |
a737bd4d | 7297 | |
c19d1205 | 7298 | return FAIL; |
09d92015 | 7299 | } |
5287ad62 | 7300 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
09d92015 MM |
7301 | |
7302 | static void | |
5287ad62 JB |
7303 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
7304 | { | |
7305 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) | |
7306 | && reg > 15) | |
7307 | { | |
b1cc4aeb | 7308 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
477330fc RM |
7309 | { |
7310 | if (thumb_mode) | |
7311 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
7312 | fpu_vfp_ext_d32); | |
7313 | else | |
7314 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
7315 | fpu_vfp_ext_d32); | |
7316 | } | |
5287ad62 | 7317 | else |
477330fc RM |
7318 | { |
7319 | first_error (_("D register out of range for selected VFP version")); | |
7320 | return; | |
7321 | } | |
5287ad62 JB |
7322 | } |
7323 | ||
c19d1205 | 7324 | switch (pos) |
09d92015 | 7325 | { |
c19d1205 ZW |
7326 | case VFP_REG_Sd: |
7327 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
7328 | break; | |
7329 | ||
7330 | case VFP_REG_Sn: | |
7331 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
7332 | break; | |
7333 | ||
7334 | case VFP_REG_Sm: | |
7335 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
7336 | break; | |
7337 | ||
5287ad62 JB |
7338 | case VFP_REG_Dd: |
7339 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); | |
7340 | break; | |
5f4273c7 | 7341 | |
5287ad62 JB |
7342 | case VFP_REG_Dn: |
7343 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); | |
7344 | break; | |
5f4273c7 | 7345 | |
5287ad62 JB |
7346 | case VFP_REG_Dm: |
7347 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); | |
7348 | break; | |
7349 | ||
c19d1205 ZW |
7350 | default: |
7351 | abort (); | |
09d92015 | 7352 | } |
09d92015 MM |
7353 | } |
7354 | ||
c19d1205 | 7355 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 7356 | if any, is handled by md_apply_fix. */ |
09d92015 | 7357 | static void |
c19d1205 | 7358 | encode_arm_shift (int i) |
09d92015 | 7359 | { |
c19d1205 ZW |
7360 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
7361 | inst.instruction |= SHIFT_ROR << 5; | |
7362 | else | |
09d92015 | 7363 | { |
c19d1205 ZW |
7364 | inst.instruction |= inst.operands[i].shift_kind << 5; |
7365 | if (inst.operands[i].immisreg) | |
7366 | { | |
7367 | inst.instruction |= SHIFT_BY_REG; | |
7368 | inst.instruction |= inst.operands[i].imm << 8; | |
7369 | } | |
7370 | else | |
7371 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 7372 | } |
c19d1205 | 7373 | } |
09d92015 | 7374 | |
c19d1205 ZW |
7375 | static void |
7376 | encode_arm_shifter_operand (int i) | |
7377 | { | |
7378 | if (inst.operands[i].isreg) | |
09d92015 | 7379 | { |
c19d1205 ZW |
7380 | inst.instruction |= inst.operands[i].reg; |
7381 | encode_arm_shift (i); | |
09d92015 | 7382 | } |
c19d1205 | 7383 | else |
a415b1cd JB |
7384 | { |
7385 | inst.instruction |= INST_IMMEDIATE; | |
7386 | if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE) | |
7387 | inst.instruction |= inst.operands[i].imm; | |
7388 | } | |
09d92015 MM |
7389 | } |
7390 | ||
c19d1205 | 7391 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 7392 | static void |
c19d1205 | 7393 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 7394 | { |
2b2f5df9 NC |
7395 | /* PR 14260: |
7396 | Generate an error if the operand is not a register. */ | |
7397 | constraint (!inst.operands[i].isreg, | |
7398 | _("Instruction does not support =N addresses")); | |
7399 | ||
c19d1205 | 7400 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 7401 | |
c19d1205 | 7402 | if (inst.operands[i].preind) |
09d92015 | 7403 | { |
c19d1205 ZW |
7404 | if (is_t) |
7405 | { | |
7406 | inst.error = _("instruction does not accept preindexed addressing"); | |
7407 | return; | |
7408 | } | |
7409 | inst.instruction |= PRE_INDEX; | |
7410 | if (inst.operands[i].writeback) | |
7411 | inst.instruction |= WRITE_BACK; | |
09d92015 | 7412 | |
c19d1205 ZW |
7413 | } |
7414 | else if (inst.operands[i].postind) | |
7415 | { | |
9c2799c2 | 7416 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
7417 | if (is_t) |
7418 | inst.instruction |= WRITE_BACK; | |
7419 | } | |
7420 | else /* unindexed - only for coprocessor */ | |
09d92015 | 7421 | { |
c19d1205 | 7422 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
7423 | return; |
7424 | } | |
7425 | ||
c19d1205 ZW |
7426 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
7427 | && (((inst.instruction & 0x000f0000) >> 16) | |
7428 | == ((inst.instruction & 0x0000f000) >> 12))) | |
7429 | as_warn ((inst.instruction & LOAD_BIT) | |
7430 | ? _("destination register same as write-back base") | |
7431 | : _("source register same as write-back base")); | |
09d92015 MM |
7432 | } |
7433 | ||
c19d1205 ZW |
7434 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7435 | ARM-format mode 2 load or store instruction. If is_t is true, | |
7436 | reject forms that cannot be used with a T instruction (i.e. not | |
7437 | post-indexed). */ | |
a737bd4d | 7438 | static void |
c19d1205 | 7439 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 7440 | { |
5be8be5d DG |
7441 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
7442 | ||
c19d1205 | 7443 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7444 | |
c19d1205 | 7445 | if (inst.operands[i].immisreg) |
09d92015 | 7446 | { |
5be8be5d DG |
7447 | constraint ((inst.operands[i].imm == REG_PC |
7448 | || (is_pc && inst.operands[i].writeback)), | |
7449 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
7450 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
7451 | inst.instruction |= inst.operands[i].imm; | |
7452 | if (!inst.operands[i].negative) | |
7453 | inst.instruction |= INDEX_UP; | |
7454 | if (inst.operands[i].shifted) | |
7455 | { | |
7456 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
7457 | inst.instruction |= SHIFT_ROR << 5; | |
7458 | else | |
7459 | { | |
7460 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
7461 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
7462 | } | |
7463 | } | |
09d92015 | 7464 | } |
c19d1205 | 7465 | else /* immediate offset in inst.reloc */ |
09d92015 | 7466 | { |
5be8be5d DG |
7467 | if (is_pc && !inst.reloc.pc_rel) |
7468 | { | |
7469 | const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0); | |
23a10334 JZ |
7470 | |
7471 | /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt | |
7472 | cannot use PC in addressing. | |
7473 | PC cannot be used in writeback addressing, either. */ | |
7474 | constraint ((is_t || inst.operands[i].writeback), | |
5be8be5d | 7475 | BAD_PC_ADDRESSING); |
23a10334 | 7476 | |
dc5ec521 | 7477 | /* Use of PC in str is deprecated for ARMv7. */ |
23a10334 JZ |
7478 | if (warn_on_deprecated |
7479 | && !is_load | |
7480 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
7481 | as_warn (_("use of PC in this instruction is deprecated")); | |
5be8be5d DG |
7482 | } |
7483 | ||
c19d1205 | 7484 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
26d97720 NS |
7485 | { |
7486 | /* Prefer + for zero encoded value. */ | |
7487 | if (!inst.operands[i].negative) | |
7488 | inst.instruction |= INDEX_UP; | |
7489 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
7490 | } | |
09d92015 | 7491 | } |
09d92015 MM |
7492 | } |
7493 | ||
c19d1205 ZW |
7494 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7495 | ARM-format mode 3 load or store instruction. Reject forms that | |
7496 | cannot be used with such instructions. If is_t is true, reject | |
7497 | forms that cannot be used with a T instruction (i.e. not | |
7498 | post-indexed). */ | |
7499 | static void | |
7500 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 7501 | { |
c19d1205 | 7502 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 7503 | { |
c19d1205 ZW |
7504 | inst.error = _("instruction does not accept scaled register index"); |
7505 | return; | |
09d92015 | 7506 | } |
a737bd4d | 7507 | |
c19d1205 | 7508 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7509 | |
c19d1205 ZW |
7510 | if (inst.operands[i].immisreg) |
7511 | { | |
5be8be5d | 7512 | constraint ((inst.operands[i].imm == REG_PC |
eb9f3f00 | 7513 | || (is_t && inst.operands[i].reg == REG_PC)), |
5be8be5d | 7514 | BAD_PC_ADDRESSING); |
eb9f3f00 JB |
7515 | constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback, |
7516 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
7517 | inst.instruction |= inst.operands[i].imm; |
7518 | if (!inst.operands[i].negative) | |
7519 | inst.instruction |= INDEX_UP; | |
7520 | } | |
7521 | else /* immediate offset in inst.reloc */ | |
7522 | { | |
5be8be5d DG |
7523 | constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel |
7524 | && inst.operands[i].writeback), | |
7525 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
7526 | inst.instruction |= HWOFFSET_IMM; |
7527 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
26d97720 NS |
7528 | { |
7529 | /* Prefer + for zero encoded value. */ | |
7530 | if (!inst.operands[i].negative) | |
7531 | inst.instruction |= INDEX_UP; | |
7532 | ||
7533 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
7534 | } | |
c19d1205 | 7535 | } |
a737bd4d NC |
7536 | } |
7537 | ||
8335d6aa JW |
7538 | /* Write immediate bits [7:0] to the following locations: |
7539 | ||
7540 | |28/24|23 19|18 16|15 4|3 0| | |
7541 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| | |
7542 | ||
7543 | This function is used by VMOV/VMVN/VORR/VBIC. */ | |
7544 | ||
7545 | static void | |
7546 | neon_write_immbits (unsigned immbits) | |
7547 | { | |
7548 | inst.instruction |= immbits & 0xf; | |
7549 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; | |
7550 | inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24); | |
7551 | } | |
7552 | ||
7553 | /* Invert low-order SIZE bits of XHI:XLO. */ | |
7554 | ||
7555 | static void | |
7556 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) | |
7557 | { | |
7558 | unsigned immlo = xlo ? *xlo : 0; | |
7559 | unsigned immhi = xhi ? *xhi : 0; | |
7560 | ||
7561 | switch (size) | |
7562 | { | |
7563 | case 8: | |
7564 | immlo = (~immlo) & 0xff; | |
7565 | break; | |
7566 | ||
7567 | case 16: | |
7568 | immlo = (~immlo) & 0xffff; | |
7569 | break; | |
7570 | ||
7571 | case 64: | |
7572 | immhi = (~immhi) & 0xffffffff; | |
7573 | /* fall through. */ | |
7574 | ||
7575 | case 32: | |
7576 | immlo = (~immlo) & 0xffffffff; | |
7577 | break; | |
7578 | ||
7579 | default: | |
7580 | abort (); | |
7581 | } | |
7582 | ||
7583 | if (xlo) | |
7584 | *xlo = immlo; | |
7585 | ||
7586 | if (xhi) | |
7587 | *xhi = immhi; | |
7588 | } | |
7589 | ||
7590 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits | |
7591 | A, B, C, D. */ | |
09d92015 | 7592 | |
c19d1205 | 7593 | static int |
8335d6aa | 7594 | neon_bits_same_in_bytes (unsigned imm) |
09d92015 | 7595 | { |
8335d6aa JW |
7596 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) |
7597 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) | |
7598 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) | |
7599 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); | |
7600 | } | |
a737bd4d | 7601 | |
8335d6aa | 7602 | /* For immediate of above form, return 0bABCD. */ |
09d92015 | 7603 | |
8335d6aa JW |
7604 | static unsigned |
7605 | neon_squash_bits (unsigned imm) | |
7606 | { | |
7607 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) | |
7608 | | ((imm & 0x01000000) >> 21); | |
7609 | } | |
7610 | ||
7611 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ | |
7612 | ||
7613 | static unsigned | |
7614 | neon_qfloat_bits (unsigned imm) | |
7615 | { | |
7616 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); | |
7617 | } | |
7618 | ||
7619 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into | |
7620 | the instruction. *OP is passed as the initial value of the op field, and | |
7621 | may be set to a different value depending on the constant (i.e. | |
7622 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not | |
7623 | MVN). If the immediate looks like a repeated pattern then also | |
7624 | try smaller element sizes. */ | |
7625 | ||
7626 | static int | |
7627 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, | |
7628 | unsigned *immbits, int *op, int size, | |
7629 | enum neon_el_type type) | |
7630 | { | |
7631 | /* Only permit float immediates (including 0.0/-0.0) if the operand type is | |
7632 | float. */ | |
7633 | if (type == NT_float && !float_p) | |
7634 | return FAIL; | |
7635 | ||
7636 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) | |
09d92015 | 7637 | { |
8335d6aa JW |
7638 | if (size != 32 || *op == 1) |
7639 | return FAIL; | |
7640 | *immbits = neon_qfloat_bits (immlo); | |
7641 | return 0xf; | |
7642 | } | |
7643 | ||
7644 | if (size == 64) | |
7645 | { | |
7646 | if (neon_bits_same_in_bytes (immhi) | |
7647 | && neon_bits_same_in_bytes (immlo)) | |
c19d1205 | 7648 | { |
8335d6aa JW |
7649 | if (*op == 1) |
7650 | return FAIL; | |
7651 | *immbits = (neon_squash_bits (immhi) << 4) | |
7652 | | neon_squash_bits (immlo); | |
7653 | *op = 1; | |
7654 | return 0xe; | |
c19d1205 | 7655 | } |
a737bd4d | 7656 | |
8335d6aa JW |
7657 | if (immhi != immlo) |
7658 | return FAIL; | |
7659 | } | |
a737bd4d | 7660 | |
8335d6aa | 7661 | if (size >= 32) |
09d92015 | 7662 | { |
8335d6aa | 7663 | if (immlo == (immlo & 0x000000ff)) |
c19d1205 | 7664 | { |
8335d6aa JW |
7665 | *immbits = immlo; |
7666 | return 0x0; | |
c19d1205 | 7667 | } |
8335d6aa | 7668 | else if (immlo == (immlo & 0x0000ff00)) |
c19d1205 | 7669 | { |
8335d6aa JW |
7670 | *immbits = immlo >> 8; |
7671 | return 0x2; | |
c19d1205 | 7672 | } |
8335d6aa JW |
7673 | else if (immlo == (immlo & 0x00ff0000)) |
7674 | { | |
7675 | *immbits = immlo >> 16; | |
7676 | return 0x4; | |
7677 | } | |
7678 | else if (immlo == (immlo & 0xff000000)) | |
7679 | { | |
7680 | *immbits = immlo >> 24; | |
7681 | return 0x6; | |
7682 | } | |
7683 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) | |
7684 | { | |
7685 | *immbits = (immlo >> 8) & 0xff; | |
7686 | return 0xc; | |
7687 | } | |
7688 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) | |
7689 | { | |
7690 | *immbits = (immlo >> 16) & 0xff; | |
7691 | return 0xd; | |
7692 | } | |
7693 | ||
7694 | if ((immlo & 0xffff) != (immlo >> 16)) | |
7695 | return FAIL; | |
7696 | immlo &= 0xffff; | |
09d92015 | 7697 | } |
a737bd4d | 7698 | |
8335d6aa | 7699 | if (size >= 16) |
4962c51a | 7700 | { |
8335d6aa JW |
7701 | if (immlo == (immlo & 0x000000ff)) |
7702 | { | |
7703 | *immbits = immlo; | |
7704 | return 0x8; | |
7705 | } | |
7706 | else if (immlo == (immlo & 0x0000ff00)) | |
7707 | { | |
7708 | *immbits = immlo >> 8; | |
7709 | return 0xa; | |
7710 | } | |
7711 | ||
7712 | if ((immlo & 0xff) != (immlo >> 8)) | |
7713 | return FAIL; | |
7714 | immlo &= 0xff; | |
4962c51a MS |
7715 | } |
7716 | ||
8335d6aa JW |
7717 | if (immlo == (immlo & 0x000000ff)) |
7718 | { | |
7719 | /* Don't allow MVN with 8-bit immediate. */ | |
7720 | if (*op == 1) | |
7721 | return FAIL; | |
7722 | *immbits = immlo; | |
7723 | return 0xe; | |
7724 | } | |
26d97720 | 7725 | |
8335d6aa | 7726 | return FAIL; |
c19d1205 | 7727 | } |
a737bd4d | 7728 | |
8335d6aa JW |
7729 | enum lit_type |
7730 | { | |
7731 | CONST_THUMB, | |
7732 | CONST_ARM, | |
7733 | CONST_VEC | |
7734 | }; | |
7735 | ||
c19d1205 ZW |
7736 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
7737 | Determine whether it can be performed with a move instruction; if | |
7738 | it can, convert inst.instruction to that move instruction and | |
c921be7d NC |
7739 | return TRUE; if it can't, convert inst.instruction to a literal-pool |
7740 | load and return FALSE. If this is not a valid thing to do in the | |
7741 | current context, set inst.error and return TRUE. | |
a737bd4d | 7742 | |
c19d1205 ZW |
7743 | inst.operands[i] describes the destination register. */ |
7744 | ||
c921be7d | 7745 | static bfd_boolean |
8335d6aa | 7746 | move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3) |
c19d1205 | 7747 | { |
53365c0d | 7748 | unsigned long tbit; |
8335d6aa JW |
7749 | bfd_boolean thumb_p = (t == CONST_THUMB); |
7750 | bfd_boolean arm_p = (t == CONST_ARM); | |
7751 | bfd_boolean vec64_p = (t == CONST_VEC) && !inst.operands[i].issingle; | |
53365c0d PB |
7752 | |
7753 | if (thumb_p) | |
7754 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
7755 | else | |
7756 | tbit = LOAD_BIT; | |
7757 | ||
7758 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 7759 | { |
c19d1205 | 7760 | inst.error = _("invalid pseudo operation"); |
c921be7d | 7761 | return TRUE; |
09d92015 | 7762 | } |
8335d6aa JW |
7763 | if (inst.reloc.exp.X_op != O_constant |
7764 | && inst.reloc.exp.X_op != O_symbol | |
7765 | && inst.reloc.exp.X_op != O_big) | |
09d92015 MM |
7766 | { |
7767 | inst.error = _("constant expression expected"); | |
c921be7d | 7768 | return TRUE; |
09d92015 | 7769 | } |
8335d6aa JW |
7770 | if ((inst.reloc.exp.X_op == O_constant |
7771 | || inst.reloc.exp.X_op == O_big) | |
7772 | && !inst.operands[i].issingle) | |
7773 | { | |
7774 | if (thumb_p && inst.reloc.exp.X_op == O_constant) | |
7775 | { | |
7776 | if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) | |
7777 | { | |
7778 | /* This can be done with a mov(1) instruction. */ | |
7779 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
7780 | inst.instruction |= inst.reloc.exp.X_add_number; | |
7781 | return TRUE; | |
7782 | } | |
7783 | } | |
7784 | else if (arm_p && inst.reloc.exp.X_op == O_constant) | |
7785 | { | |
7786 | int value = encode_arm_immediate (inst.reloc.exp.X_add_number); | |
7787 | if (value != FAIL) | |
7788 | { | |
7789 | /* This can be done with a mov instruction. */ | |
7790 | inst.instruction &= LITERAL_MASK; | |
7791 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
7792 | inst.instruction |= value & 0xfff; | |
7793 | return TRUE; | |
7794 | } | |
7795 | ||
7796 | value = encode_arm_immediate (~inst.reloc.exp.X_add_number); | |
7797 | if (value != FAIL) | |
7798 | { | |
7799 | /* This can be done with a mvn instruction. */ | |
7800 | inst.instruction &= LITERAL_MASK; | |
7801 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
7802 | inst.instruction |= value & 0xfff; | |
7803 | return TRUE; | |
7804 | } | |
7805 | } | |
7806 | else if (vec64_p) | |
7807 | { | |
7808 | int op = 0; | |
7809 | unsigned immbits = 0; | |
7810 | unsigned immlo = inst.operands[1].imm; | |
7811 | unsigned immhi = inst.operands[1].regisimm | |
7812 | ? inst.operands[1].reg | |
7813 | : inst.reloc.exp.X_unsigned | |
7814 | ? 0 | |
2569ceb0 | 7815 | : ((bfd_int64_t)((int) immlo)) >> 32; |
8335d6aa JW |
7816 | int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, |
7817 | &op, 64, NT_invtype); | |
7818 | ||
7819 | if (cmode == FAIL) | |
7820 | { | |
7821 | neon_invert_size (&immlo, &immhi, 64); | |
7822 | op = !op; | |
7823 | cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, | |
7824 | &op, 64, NT_invtype); | |
7825 | } | |
7826 | if (cmode != FAIL) | |
7827 | { | |
7828 | inst.instruction = (inst.instruction & VLDR_VMOV_SAME) | |
7829 | | (1 << 23) | |
7830 | | (cmode << 8) | |
7831 | | (op << 5) | |
7832 | | (1 << 4); | |
7833 | /* Fill other bits in vmov encoding for both thumb and arm. */ | |
7834 | if (thumb_mode) | |
7835 | inst.instruction |= (0x7 << 29) | (0xF << 24); | |
7836 | else | |
7837 | inst.instruction |= (0xF << 28) | (0x1 << 25); | |
7838 | neon_write_immbits (immbits); | |
7839 | return TRUE; | |
7840 | } | |
7841 | } | |
7842 | } | |
7843 | ||
7844 | if (add_to_lit_pool ((!inst.operands[i].isvec | |
7845 | || inst.operands[i].issingle) ? 4 : 8) == FAIL) | |
7846 | return TRUE; | |
7847 | ||
7848 | inst.operands[1].reg = REG_PC; | |
7849 | inst.operands[1].isreg = 1; | |
7850 | inst.operands[1].preind = 1; | |
7851 | inst.reloc.pc_rel = 1; | |
7852 | inst.reloc.type = (thumb_p | |
7853 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
7854 | : (mode_3 | |
7855 | ? BFD_RELOC_ARM_HWLITERAL | |
7856 | : BFD_RELOC_ARM_LITERAL)); | |
7857 | return FALSE; | |
7858 | } | |
7859 | ||
7860 | /* inst.operands[i] was set up by parse_address. Encode it into an | |
7861 | ARM-format instruction. Reject all forms which cannot be encoded | |
7862 | into a coprocessor load/store instruction. If wb_ok is false, | |
7863 | reject use of writeback; if unind_ok is false, reject use of | |
7864 | unindexed addressing. If reloc_override is not 0, use it instead | |
7865 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one | |
7866 | (in which case it is preserved). */ | |
7867 | ||
7868 | static int | |
7869 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
7870 | { | |
7871 | if (!inst.operands[i].isreg) | |
7872 | { | |
7873 | gas_assert (inst.operands[0].isvec); | |
7874 | if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE)) | |
7875 | return SUCCESS; | |
7876 | } | |
7877 | ||
7878 | inst.instruction |= inst.operands[i].reg << 16; | |
7879 | ||
7880 | gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); | |
7881 | ||
7882 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ | |
7883 | { | |
7884 | gas_assert (!inst.operands[i].writeback); | |
7885 | if (!unind_ok) | |
7886 | { | |
7887 | inst.error = _("instruction does not support unindexed addressing"); | |
7888 | return FAIL; | |
7889 | } | |
7890 | inst.instruction |= inst.operands[i].imm; | |
7891 | inst.instruction |= INDEX_UP; | |
7892 | return SUCCESS; | |
7893 | } | |
7894 | ||
7895 | if (inst.operands[i].preind) | |
7896 | inst.instruction |= PRE_INDEX; | |
7897 | ||
7898 | if (inst.operands[i].writeback) | |
09d92015 | 7899 | { |
8335d6aa | 7900 | if (inst.operands[i].reg == REG_PC) |
c19d1205 | 7901 | { |
8335d6aa JW |
7902 | inst.error = _("pc may not be used with write-back"); |
7903 | return FAIL; | |
c19d1205 | 7904 | } |
8335d6aa | 7905 | if (!wb_ok) |
c19d1205 | 7906 | { |
8335d6aa JW |
7907 | inst.error = _("instruction does not support writeback"); |
7908 | return FAIL; | |
c19d1205 | 7909 | } |
8335d6aa | 7910 | inst.instruction |= WRITE_BACK; |
09d92015 MM |
7911 | } |
7912 | ||
8335d6aa JW |
7913 | if (reloc_override) |
7914 | inst.reloc.type = (bfd_reloc_code_real_type) reloc_override; | |
7915 | else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC | |
7916 | || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) | |
7917 | && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) | |
c19d1205 | 7918 | { |
8335d6aa JW |
7919 | if (thumb_mode) |
7920 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
7921 | else | |
7922 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
c19d1205 | 7923 | } |
8335d6aa JW |
7924 | |
7925 | /* Prefer + for zero encoded value. */ | |
7926 | if (!inst.operands[i].negative) | |
7927 | inst.instruction |= INDEX_UP; | |
7928 | ||
7929 | return SUCCESS; | |
09d92015 MM |
7930 | } |
7931 | ||
5f4273c7 | 7932 | /* Functions for instruction encoding, sorted by sub-architecture. |
c19d1205 ZW |
7933 | First some generics; their names are taken from the conventional |
7934 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 7935 | |
a737bd4d | 7936 | static void |
c19d1205 | 7937 | do_noargs (void) |
09d92015 | 7938 | { |
c19d1205 | 7939 | } |
a737bd4d | 7940 | |
c19d1205 ZW |
7941 | static void |
7942 | do_rd (void) | |
7943 | { | |
7944 | inst.instruction |= inst.operands[0].reg << 12; | |
7945 | } | |
a737bd4d | 7946 | |
c19d1205 ZW |
7947 | static void |
7948 | do_rd_rm (void) | |
7949 | { | |
7950 | inst.instruction |= inst.operands[0].reg << 12; | |
7951 | inst.instruction |= inst.operands[1].reg; | |
7952 | } | |
09d92015 | 7953 | |
9eb6c0f1 MGD |
7954 | static void |
7955 | do_rm_rn (void) | |
7956 | { | |
7957 | inst.instruction |= inst.operands[0].reg; | |
7958 | inst.instruction |= inst.operands[1].reg << 16; | |
7959 | } | |
7960 | ||
c19d1205 ZW |
7961 | static void |
7962 | do_rd_rn (void) | |
7963 | { | |
7964 | inst.instruction |= inst.operands[0].reg << 12; | |
7965 | inst.instruction |= inst.operands[1].reg << 16; | |
7966 | } | |
a737bd4d | 7967 | |
c19d1205 ZW |
7968 | static void |
7969 | do_rn_rd (void) | |
7970 | { | |
7971 | inst.instruction |= inst.operands[0].reg << 16; | |
7972 | inst.instruction |= inst.operands[1].reg << 12; | |
7973 | } | |
09d92015 | 7974 | |
59d09be6 MGD |
7975 | static bfd_boolean |
7976 | check_obsolete (const arm_feature_set *feature, const char *msg) | |
7977 | { | |
7978 | if (ARM_CPU_IS_ANY (cpu_variant)) | |
7979 | { | |
7980 | as_warn ("%s", msg); | |
7981 | return TRUE; | |
7982 | } | |
7983 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) | |
7984 | { | |
7985 | as_bad ("%s", msg); | |
7986 | return TRUE; | |
7987 | } | |
7988 | ||
7989 | return FALSE; | |
7990 | } | |
7991 | ||
c19d1205 ZW |
7992 | static void |
7993 | do_rd_rm_rn (void) | |
7994 | { | |
9a64e435 | 7995 | unsigned Rn = inst.operands[2].reg; |
708587a4 | 7996 | /* Enforce restrictions on SWP instruction. */ |
9a64e435 | 7997 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
56adecf4 DG |
7998 | { |
7999 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
8000 | _("Rn must not overlap other operands")); | |
8001 | ||
59d09be6 MGD |
8002 | /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7. |
8003 | */ | |
8004 | if (!check_obsolete (&arm_ext_v8, | |
8005 | _("swp{b} use is obsoleted for ARMv8 and later")) | |
8006 | && warn_on_deprecated | |
8007 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6)) | |
8008 | as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7")); | |
56adecf4 | 8009 | } |
59d09be6 | 8010 | |
c19d1205 ZW |
8011 | inst.instruction |= inst.operands[0].reg << 12; |
8012 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 8013 | inst.instruction |= Rn << 16; |
c19d1205 | 8014 | } |
09d92015 | 8015 | |
c19d1205 ZW |
8016 | static void |
8017 | do_rd_rn_rm (void) | |
8018 | { | |
8019 | inst.instruction |= inst.operands[0].reg << 12; | |
8020 | inst.instruction |= inst.operands[1].reg << 16; | |
8021 | inst.instruction |= inst.operands[2].reg; | |
8022 | } | |
a737bd4d | 8023 | |
c19d1205 ZW |
8024 | static void |
8025 | do_rm_rd_rn (void) | |
8026 | { | |
5be8be5d DG |
8027 | constraint ((inst.operands[2].reg == REG_PC), BAD_PC); |
8028 | constraint (((inst.reloc.exp.X_op != O_constant | |
8029 | && inst.reloc.exp.X_op != O_illegal) | |
8030 | || inst.reloc.exp.X_add_number != 0), | |
8031 | BAD_ADDR_MODE); | |
c19d1205 ZW |
8032 | inst.instruction |= inst.operands[0].reg; |
8033 | inst.instruction |= inst.operands[1].reg << 12; | |
8034 | inst.instruction |= inst.operands[2].reg << 16; | |
8035 | } | |
09d92015 | 8036 | |
c19d1205 ZW |
8037 | static void |
8038 | do_imm0 (void) | |
8039 | { | |
8040 | inst.instruction |= inst.operands[0].imm; | |
8041 | } | |
09d92015 | 8042 | |
c19d1205 ZW |
8043 | static void |
8044 | do_rd_cpaddr (void) | |
8045 | { | |
8046 | inst.instruction |= inst.operands[0].reg << 12; | |
8047 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 8048 | } |
a737bd4d | 8049 | |
c19d1205 ZW |
8050 | /* ARM instructions, in alphabetical order by function name (except |
8051 | that wrapper functions appear immediately after the function they | |
8052 | wrap). */ | |
09d92015 | 8053 | |
c19d1205 ZW |
8054 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
8055 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
8056 | |
8057 | static void | |
c19d1205 | 8058 | do_adr (void) |
09d92015 | 8059 | { |
c19d1205 | 8060 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 8061 | |
c19d1205 ZW |
8062 | /* Frag hacking will turn this into a sub instruction if the offset turns |
8063 | out to be negative. */ | |
8064 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 8065 | inst.reloc.pc_rel = 1; |
2fc8bdac | 8066 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 8067 | } |
b99bd4ef | 8068 | |
c19d1205 ZW |
8069 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
8070 | into a relative address of the form: | |
8071 | add rd, pc, #low(label-.-8)" | |
8072 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 8073 | |
c19d1205 ZW |
8074 | static void |
8075 | do_adrl (void) | |
8076 | { | |
8077 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 8078 | |
c19d1205 ZW |
8079 | /* Frag hacking will turn this into a sub instruction if the offset turns |
8080 | out to be negative. */ | |
8081 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
8082 | inst.reloc.pc_rel = 1; |
8083 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 8084 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
8085 | } |
8086 | ||
b99bd4ef | 8087 | static void |
c19d1205 | 8088 | do_arit (void) |
b99bd4ef | 8089 | { |
c19d1205 ZW |
8090 | if (!inst.operands[1].present) |
8091 | inst.operands[1].reg = inst.operands[0].reg; | |
8092 | inst.instruction |= inst.operands[0].reg << 12; | |
8093 | inst.instruction |= inst.operands[1].reg << 16; | |
8094 | encode_arm_shifter_operand (2); | |
8095 | } | |
b99bd4ef | 8096 | |
62b3e311 PB |
8097 | static void |
8098 | do_barrier (void) | |
8099 | { | |
8100 | if (inst.operands[0].present) | |
ccb84d65 | 8101 | inst.instruction |= inst.operands[0].imm; |
62b3e311 PB |
8102 | else |
8103 | inst.instruction |= 0xf; | |
8104 | } | |
8105 | ||
c19d1205 ZW |
8106 | static void |
8107 | do_bfc (void) | |
8108 | { | |
8109 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
8110 | constraint (msb > 32, _("bit-field extends past end of register")); | |
8111 | /* The instruction encoding stores the LSB and MSB, | |
8112 | not the LSB and width. */ | |
8113 | inst.instruction |= inst.operands[0].reg << 12; | |
8114 | inst.instruction |= inst.operands[1].imm << 7; | |
8115 | inst.instruction |= (msb - 1) << 16; | |
8116 | } | |
b99bd4ef | 8117 | |
c19d1205 ZW |
8118 | static void |
8119 | do_bfi (void) | |
8120 | { | |
8121 | unsigned int msb; | |
b99bd4ef | 8122 | |
c19d1205 ZW |
8123 | /* #0 in second position is alternative syntax for bfc, which is |
8124 | the same instruction but with REG_PC in the Rm field. */ | |
8125 | if (!inst.operands[1].isreg) | |
8126 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 8127 | |
c19d1205 ZW |
8128 | msb = inst.operands[2].imm + inst.operands[3].imm; |
8129 | constraint (msb > 32, _("bit-field extends past end of register")); | |
8130 | /* The instruction encoding stores the LSB and MSB, | |
8131 | not the LSB and width. */ | |
8132 | inst.instruction |= inst.operands[0].reg << 12; | |
8133 | inst.instruction |= inst.operands[1].reg; | |
8134 | inst.instruction |= inst.operands[2].imm << 7; | |
8135 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
8136 | } |
8137 | ||
b99bd4ef | 8138 | static void |
c19d1205 | 8139 | do_bfx (void) |
b99bd4ef | 8140 | { |
c19d1205 ZW |
8141 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
8142 | _("bit-field extends past end of register")); | |
8143 | inst.instruction |= inst.operands[0].reg << 12; | |
8144 | inst.instruction |= inst.operands[1].reg; | |
8145 | inst.instruction |= inst.operands[2].imm << 7; | |
8146 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
8147 | } | |
09d92015 | 8148 | |
c19d1205 ZW |
8149 | /* ARM V5 breakpoint instruction (argument parse) |
8150 | BKPT <16 bit unsigned immediate> | |
8151 | Instruction is not conditional. | |
8152 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
8153 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 8154 | |
c19d1205 ZW |
8155 | static void |
8156 | do_bkpt (void) | |
8157 | { | |
8158 | /* Top 12 of 16 bits to bits 19:8. */ | |
8159 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 8160 | |
c19d1205 ZW |
8161 | /* Bottom 4 of 16 bits to bits 3:0. */ |
8162 | inst.instruction |= inst.operands[0].imm & 0xf; | |
8163 | } | |
09d92015 | 8164 | |
c19d1205 ZW |
8165 | static void |
8166 | encode_branch (int default_reloc) | |
8167 | { | |
8168 | if (inst.operands[0].hasreloc) | |
8169 | { | |
0855e32b NS |
8170 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32 |
8171 | && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL, | |
8172 | _("the only valid suffixes here are '(plt)' and '(tlscall)'")); | |
8173 | inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32 | |
8174 | ? BFD_RELOC_ARM_PLT32 | |
8175 | : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL; | |
c19d1205 | 8176 | } |
b99bd4ef | 8177 | else |
9ae92b05 | 8178 | inst.reloc.type = (bfd_reloc_code_real_type) default_reloc; |
2fc8bdac | 8179 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
8180 | } |
8181 | ||
b99bd4ef | 8182 | static void |
c19d1205 | 8183 | do_branch (void) |
b99bd4ef | 8184 | { |
39b41c9c PB |
8185 | #ifdef OBJ_ELF |
8186 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
8187 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
8188 | else | |
8189 | #endif | |
8190 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
8191 | } | |
8192 | ||
8193 | static void | |
8194 | do_bl (void) | |
8195 | { | |
8196 | #ifdef OBJ_ELF | |
8197 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
8198 | { | |
8199 | if (inst.cond == COND_ALWAYS) | |
8200 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
8201 | else | |
8202 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
8203 | } | |
8204 | else | |
8205 | #endif | |
8206 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 8207 | } |
b99bd4ef | 8208 | |
c19d1205 ZW |
8209 | /* ARM V5 branch-link-exchange instruction (argument parse) |
8210 | BLX <target_addr> ie BLX(1) | |
8211 | BLX{<condition>} <Rm> ie BLX(2) | |
8212 | Unfortunately, there are two different opcodes for this mnemonic. | |
8213 | So, the insns[].value is not used, and the code here zaps values | |
8214 | into inst.instruction. | |
8215 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 8216 | |
c19d1205 ZW |
8217 | static void |
8218 | do_blx (void) | |
8219 | { | |
8220 | if (inst.operands[0].isreg) | |
b99bd4ef | 8221 | { |
c19d1205 ZW |
8222 | /* Arg is a register; the opcode provided by insns[] is correct. |
8223 | It is not illegal to do "blx pc", just useless. */ | |
8224 | if (inst.operands[0].reg == REG_PC) | |
8225 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 8226 | |
c19d1205 ZW |
8227 | inst.instruction |= inst.operands[0].reg; |
8228 | } | |
8229 | else | |
b99bd4ef | 8230 | { |
c19d1205 | 8231 | /* Arg is an address; this instruction cannot be executed |
267bf995 RR |
8232 | conditionally, and the opcode must be adjusted. |
8233 | We retain the BFD_RELOC_ARM_PCREL_BLX till the very end | |
8234 | where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ | |
c19d1205 | 8235 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
2fc8bdac | 8236 | inst.instruction = 0xfa000000; |
267bf995 | 8237 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 8238 | } |
c19d1205 ZW |
8239 | } |
8240 | ||
8241 | static void | |
8242 | do_bx (void) | |
8243 | { | |
845b51d6 PB |
8244 | bfd_boolean want_reloc; |
8245 | ||
c19d1205 ZW |
8246 | if (inst.operands[0].reg == REG_PC) |
8247 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 8248 | |
c19d1205 | 8249 | inst.instruction |= inst.operands[0].reg; |
845b51d6 PB |
8250 | /* Output R_ARM_V4BX relocations if is an EABI object that looks like |
8251 | it is for ARMv4t or earlier. */ | |
8252 | want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); | |
8253 | if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5)) | |
8254 | want_reloc = TRUE; | |
8255 | ||
5ad34203 | 8256 | #ifdef OBJ_ELF |
845b51d6 | 8257 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
5ad34203 | 8258 | #endif |
584206db | 8259 | want_reloc = FALSE; |
845b51d6 PB |
8260 | |
8261 | if (want_reloc) | |
8262 | inst.reloc.type = BFD_RELOC_ARM_V4BX; | |
09d92015 MM |
8263 | } |
8264 | ||
c19d1205 ZW |
8265 | |
8266 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
8267 | |
8268 | static void | |
c19d1205 | 8269 | do_bxj (void) |
a737bd4d | 8270 | { |
c19d1205 ZW |
8271 | if (inst.operands[0].reg == REG_PC) |
8272 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
8273 | ||
8274 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
8275 | } |
8276 | ||
c19d1205 ZW |
8277 | /* Co-processor data operation: |
8278 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
8279 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
8280 | static void | |
8281 | do_cdp (void) | |
8282 | { | |
8283 | inst.instruction |= inst.operands[0].reg << 8; | |
8284 | inst.instruction |= inst.operands[1].imm << 20; | |
8285 | inst.instruction |= inst.operands[2].reg << 12; | |
8286 | inst.instruction |= inst.operands[3].reg << 16; | |
8287 | inst.instruction |= inst.operands[4].reg; | |
8288 | inst.instruction |= inst.operands[5].imm << 5; | |
8289 | } | |
a737bd4d NC |
8290 | |
8291 | static void | |
c19d1205 | 8292 | do_cmp (void) |
a737bd4d | 8293 | { |
c19d1205 ZW |
8294 | inst.instruction |= inst.operands[0].reg << 16; |
8295 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
8296 | } |
8297 | ||
c19d1205 ZW |
8298 | /* Transfer between coprocessor and ARM registers. |
8299 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
8300 | MRC2 | |
8301 | MCR{cond} | |
8302 | MCR2 | |
8303 | ||
8304 | No special properties. */ | |
09d92015 | 8305 | |
dcbd0d71 MGD |
8306 | struct deprecated_coproc_regs_s |
8307 | { | |
8308 | unsigned cp; | |
8309 | int opc1; | |
8310 | unsigned crn; | |
8311 | unsigned crm; | |
8312 | int opc2; | |
8313 | arm_feature_set deprecated; | |
8314 | arm_feature_set obsoleted; | |
8315 | const char *dep_msg; | |
8316 | const char *obs_msg; | |
8317 | }; | |
8318 | ||
8319 | #define DEPR_ACCESS_V8 \ | |
8320 | N_("This coprocessor register access is deprecated in ARMv8") | |
8321 | ||
8322 | /* Table of all deprecated coprocessor registers. */ | |
8323 | static struct deprecated_coproc_regs_s deprecated_coproc_regs[] = | |
8324 | { | |
8325 | {15, 0, 7, 10, 5, /* CP15DMB. */ | |
8326 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
8327 | DEPR_ACCESS_V8, NULL}, | |
8328 | {15, 0, 7, 10, 4, /* CP15DSB. */ | |
8329 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
8330 | DEPR_ACCESS_V8, NULL}, | |
8331 | {15, 0, 7, 5, 4, /* CP15ISB. */ | |
8332 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
8333 | DEPR_ACCESS_V8, NULL}, | |
8334 | {14, 6, 1, 0, 0, /* TEEHBR. */ | |
8335 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
8336 | DEPR_ACCESS_V8, NULL}, | |
8337 | {14, 6, 0, 0, 0, /* TEECR. */ | |
8338 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
8339 | DEPR_ACCESS_V8, NULL}, | |
8340 | }; | |
8341 | ||
8342 | #undef DEPR_ACCESS_V8 | |
8343 | ||
8344 | static const size_t deprecated_coproc_reg_count = | |
8345 | sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]); | |
8346 | ||
09d92015 | 8347 | static void |
c19d1205 | 8348 | do_co_reg (void) |
09d92015 | 8349 | { |
fdfde340 | 8350 | unsigned Rd; |
dcbd0d71 | 8351 | size_t i; |
fdfde340 JM |
8352 | |
8353 | Rd = inst.operands[2].reg; | |
8354 | if (thumb_mode) | |
8355 | { | |
8356 | if (inst.instruction == 0xee000010 | |
8357 | || inst.instruction == 0xfe000010) | |
8358 | /* MCR, MCR2 */ | |
8359 | reject_bad_reg (Rd); | |
8360 | else | |
8361 | /* MRC, MRC2 */ | |
8362 | constraint (Rd == REG_SP, BAD_SP); | |
8363 | } | |
8364 | else | |
8365 | { | |
8366 | /* MCR */ | |
8367 | if (inst.instruction == 0xe000010) | |
8368 | constraint (Rd == REG_PC, BAD_PC); | |
8369 | } | |
8370 | ||
dcbd0d71 MGD |
8371 | for (i = 0; i < deprecated_coproc_reg_count; ++i) |
8372 | { | |
8373 | const struct deprecated_coproc_regs_s *r = | |
8374 | deprecated_coproc_regs + i; | |
8375 | ||
8376 | if (inst.operands[0].reg == r->cp | |
8377 | && inst.operands[1].imm == r->opc1 | |
8378 | && inst.operands[3].reg == r->crn | |
8379 | && inst.operands[4].reg == r->crm | |
8380 | && inst.operands[5].imm == r->opc2) | |
8381 | { | |
b10bf8c5 | 8382 | if (! ARM_CPU_IS_ANY (cpu_variant) |
477330fc | 8383 | && warn_on_deprecated |
dcbd0d71 MGD |
8384 | && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated)) |
8385 | as_warn ("%s", r->dep_msg); | |
8386 | } | |
8387 | } | |
fdfde340 | 8388 | |
c19d1205 ZW |
8389 | inst.instruction |= inst.operands[0].reg << 8; |
8390 | inst.instruction |= inst.operands[1].imm << 21; | |
fdfde340 | 8391 | inst.instruction |= Rd << 12; |
c19d1205 ZW |
8392 | inst.instruction |= inst.operands[3].reg << 16; |
8393 | inst.instruction |= inst.operands[4].reg; | |
8394 | inst.instruction |= inst.operands[5].imm << 5; | |
8395 | } | |
09d92015 | 8396 | |
c19d1205 ZW |
8397 | /* Transfer between coprocessor register and pair of ARM registers. |
8398 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
8399 | MCRR2 | |
8400 | MRRC{cond} | |
8401 | MRRC2 | |
b99bd4ef | 8402 | |
c19d1205 | 8403 | Two XScale instructions are special cases of these: |
09d92015 | 8404 | |
c19d1205 ZW |
8405 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
8406 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 8407 | |
5f4273c7 | 8408 | Result unpredictable if Rd or Rn is R15. */ |
a737bd4d | 8409 | |
c19d1205 ZW |
8410 | static void |
8411 | do_co_reg2c (void) | |
8412 | { | |
fdfde340 JM |
8413 | unsigned Rd, Rn; |
8414 | ||
8415 | Rd = inst.operands[2].reg; | |
8416 | Rn = inst.operands[3].reg; | |
8417 | ||
8418 | if (thumb_mode) | |
8419 | { | |
8420 | reject_bad_reg (Rd); | |
8421 | reject_bad_reg (Rn); | |
8422 | } | |
8423 | else | |
8424 | { | |
8425 | constraint (Rd == REG_PC, BAD_PC); | |
8426 | constraint (Rn == REG_PC, BAD_PC); | |
8427 | } | |
8428 | ||
c19d1205 ZW |
8429 | inst.instruction |= inst.operands[0].reg << 8; |
8430 | inst.instruction |= inst.operands[1].imm << 4; | |
fdfde340 JM |
8431 | inst.instruction |= Rd << 12; |
8432 | inst.instruction |= Rn << 16; | |
c19d1205 | 8433 | inst.instruction |= inst.operands[4].reg; |
b99bd4ef NC |
8434 | } |
8435 | ||
c19d1205 ZW |
8436 | static void |
8437 | do_cpsi (void) | |
8438 | { | |
8439 | inst.instruction |= inst.operands[0].imm << 6; | |
a028a6f5 PB |
8440 | if (inst.operands[1].present) |
8441 | { | |
8442 | inst.instruction |= CPSI_MMOD; | |
8443 | inst.instruction |= inst.operands[1].imm; | |
8444 | } | |
c19d1205 | 8445 | } |
b99bd4ef | 8446 | |
62b3e311 PB |
8447 | static void |
8448 | do_dbg (void) | |
8449 | { | |
8450 | inst.instruction |= inst.operands[0].imm; | |
8451 | } | |
8452 | ||
eea54501 MGD |
8453 | static void |
8454 | do_div (void) | |
8455 | { | |
8456 | unsigned Rd, Rn, Rm; | |
8457 | ||
8458 | Rd = inst.operands[0].reg; | |
8459 | Rn = (inst.operands[1].present | |
8460 | ? inst.operands[1].reg : Rd); | |
8461 | Rm = inst.operands[2].reg; | |
8462 | ||
8463 | constraint ((Rd == REG_PC), BAD_PC); | |
8464 | constraint ((Rn == REG_PC), BAD_PC); | |
8465 | constraint ((Rm == REG_PC), BAD_PC); | |
8466 | ||
8467 | inst.instruction |= Rd << 16; | |
8468 | inst.instruction |= Rn << 0; | |
8469 | inst.instruction |= Rm << 8; | |
8470 | } | |
8471 | ||
b99bd4ef | 8472 | static void |
c19d1205 | 8473 | do_it (void) |
b99bd4ef | 8474 | { |
c19d1205 | 8475 | /* There is no IT instruction in ARM mode. We |
e07e6e58 NC |
8476 | process it to do the validation as if in |
8477 | thumb mode, just in case the code gets | |
8478 | assembled for thumb using the unified syntax. */ | |
8479 | ||
c19d1205 | 8480 | inst.size = 0; |
e07e6e58 NC |
8481 | if (unified_syntax) |
8482 | { | |
8483 | set_it_insn_type (IT_INSN); | |
8484 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
8485 | now_it.cc = inst.operands[0].imm; | |
8486 | } | |
09d92015 | 8487 | } |
b99bd4ef | 8488 | |
6530b175 NC |
8489 | /* If there is only one register in the register list, |
8490 | then return its register number. Otherwise return -1. */ | |
8491 | static int | |
8492 | only_one_reg_in_list (int range) | |
8493 | { | |
8494 | int i = ffs (range) - 1; | |
8495 | return (i > 15 || range != (1 << i)) ? -1 : i; | |
8496 | } | |
8497 | ||
09d92015 | 8498 | static void |
6530b175 | 8499 | encode_ldmstm(int from_push_pop_mnem) |
ea6ef066 | 8500 | { |
c19d1205 ZW |
8501 | int base_reg = inst.operands[0].reg; |
8502 | int range = inst.operands[1].imm; | |
6530b175 | 8503 | int one_reg; |
ea6ef066 | 8504 | |
c19d1205 ZW |
8505 | inst.instruction |= base_reg << 16; |
8506 | inst.instruction |= range; | |
ea6ef066 | 8507 | |
c19d1205 ZW |
8508 | if (inst.operands[1].writeback) |
8509 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 8510 | |
c19d1205 | 8511 | if (inst.operands[0].writeback) |
ea6ef066 | 8512 | { |
c19d1205 ZW |
8513 | inst.instruction |= WRITE_BACK; |
8514 | /* Check for unpredictable uses of writeback. */ | |
8515 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 8516 | { |
c19d1205 ZW |
8517 | /* Not allowed in LDM type 2. */ |
8518 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
8519 | && ((range & (1 << REG_PC)) == 0)) | |
8520 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
8521 | /* Only allowed if base reg not in list for other types. */ | |
8522 | else if (range & (1 << base_reg)) | |
8523 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
8524 | } | |
8525 | else /* STM. */ | |
8526 | { | |
8527 | /* Not allowed for type 2. */ | |
8528 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
8529 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
8530 | /* Only allowed if base reg not in list, or first in list. */ | |
8531 | else if ((range & (1 << base_reg)) | |
8532 | && (range & ((1 << base_reg) - 1))) | |
8533 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 8534 | } |
ea6ef066 | 8535 | } |
6530b175 NC |
8536 | |
8537 | /* If PUSH/POP has only one register, then use the A2 encoding. */ | |
8538 | one_reg = only_one_reg_in_list (range); | |
8539 | if (from_push_pop_mnem && one_reg >= 0) | |
8540 | { | |
8541 | int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH; | |
8542 | ||
8543 | inst.instruction &= A_COND_MASK; | |
8544 | inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP; | |
8545 | inst.instruction |= one_reg << 12; | |
8546 | } | |
8547 | } | |
8548 | ||
8549 | static void | |
8550 | do_ldmstm (void) | |
8551 | { | |
8552 | encode_ldmstm (/*from_push_pop_mnem=*/FALSE); | |
a737bd4d NC |
8553 | } |
8554 | ||
c19d1205 ZW |
8555 | /* ARMv5TE load-consecutive (argument parse) |
8556 | Mode is like LDRH. | |
8557 | ||
8558 | LDRccD R, mode | |
8559 | STRccD R, mode. */ | |
8560 | ||
a737bd4d | 8561 | static void |
c19d1205 | 8562 | do_ldrd (void) |
a737bd4d | 8563 | { |
c19d1205 | 8564 | constraint (inst.operands[0].reg % 2 != 0, |
c56791bb | 8565 | _("first transfer register must be even")); |
c19d1205 ZW |
8566 | constraint (inst.operands[1].present |
8567 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
c56791bb | 8568 | _("can only transfer two consecutive registers")); |
c19d1205 ZW |
8569 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); |
8570 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 8571 | |
c19d1205 ZW |
8572 | if (!inst.operands[1].present) |
8573 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
5f4273c7 | 8574 | |
c56791bb RE |
8575 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
8576 | register and the first register written; we have to diagnose | |
8577 | overlap between the base and the second register written here. */ | |
ea6ef066 | 8578 | |
c56791bb RE |
8579 | if (inst.operands[2].reg == inst.operands[1].reg |
8580 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
8581 | as_warn (_("base register written back, and overlaps " | |
8582 | "second transfer register")); | |
b05fe5cf | 8583 | |
c56791bb RE |
8584 | if (!(inst.instruction & V4_STR_BIT)) |
8585 | { | |
c19d1205 | 8586 | /* For an index-register load, the index register must not overlap the |
c56791bb RE |
8587 | destination (even if not write-back). */ |
8588 | if (inst.operands[2].immisreg | |
8589 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg | |
8590 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
8591 | as_warn (_("index register overlaps transfer register")); | |
b05fe5cf | 8592 | } |
c19d1205 ZW |
8593 | inst.instruction |= inst.operands[0].reg << 12; |
8594 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
8595 | } |
8596 | ||
8597 | static void | |
c19d1205 | 8598 | do_ldrex (void) |
b05fe5cf | 8599 | { |
c19d1205 ZW |
8600 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
8601 | || inst.operands[1].postind || inst.operands[1].writeback | |
8602 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
8603 | || inst.operands[1].negative |
8604 | /* This can arise if the programmer has written | |
8605 | strex rN, rM, foo | |
8606 | or if they have mistakenly used a register name as the last | |
8607 | operand, eg: | |
8608 | strex rN, rM, rX | |
8609 | It is very difficult to distinguish between these two cases | |
8610 | because "rX" might actually be a label. ie the register | |
8611 | name has been occluded by a symbol of the same name. So we | |
8612 | just generate a general 'bad addressing mode' type error | |
8613 | message and leave it up to the programmer to discover the | |
8614 | true cause and fix their mistake. */ | |
8615 | || (inst.operands[1].reg == REG_PC), | |
8616 | BAD_ADDR_MODE); | |
b05fe5cf | 8617 | |
c19d1205 ZW |
8618 | constraint (inst.reloc.exp.X_op != O_constant |
8619 | || inst.reloc.exp.X_add_number != 0, | |
8620 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 8621 | |
5be8be5d DG |
8622 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
8623 | ||
c19d1205 ZW |
8624 | inst.instruction |= inst.operands[0].reg << 12; |
8625 | inst.instruction |= inst.operands[1].reg << 16; | |
8626 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
8627 | } |
8628 | ||
8629 | static void | |
c19d1205 | 8630 | do_ldrexd (void) |
b05fe5cf | 8631 | { |
c19d1205 ZW |
8632 | constraint (inst.operands[0].reg % 2 != 0, |
8633 | _("even register required")); | |
8634 | constraint (inst.operands[1].present | |
8635 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
8636 | _("can only load two consecutive registers")); | |
8637 | /* If op 1 were present and equal to PC, this function wouldn't | |
8638 | have been called in the first place. */ | |
8639 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 8640 | |
c19d1205 ZW |
8641 | inst.instruction |= inst.operands[0].reg << 12; |
8642 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
8643 | } |
8644 | ||
1be5fd2e NC |
8645 | /* In both ARM and thumb state 'ldr pc, #imm' with an immediate |
8646 | which is not a multiple of four is UNPREDICTABLE. */ | |
8647 | static void | |
8648 | check_ldr_r15_aligned (void) | |
8649 | { | |
8650 | constraint (!(inst.operands[1].immisreg) | |
8651 | && (inst.operands[0].reg == REG_PC | |
8652 | && inst.operands[1].reg == REG_PC | |
8653 | && (inst.reloc.exp.X_add_number & 0x3)), | |
8654 | _("ldr to register 15 must be 4-byte alligned")); | |
8655 | } | |
8656 | ||
b05fe5cf | 8657 | static void |
c19d1205 | 8658 | do_ldst (void) |
b05fe5cf | 8659 | { |
c19d1205 ZW |
8660 | inst.instruction |= inst.operands[0].reg << 12; |
8661 | if (!inst.operands[1].isreg) | |
8335d6aa | 8662 | if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE)) |
b05fe5cf | 8663 | return; |
c19d1205 | 8664 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
1be5fd2e | 8665 | check_ldr_r15_aligned (); |
b05fe5cf ZW |
8666 | } |
8667 | ||
8668 | static void | |
c19d1205 | 8669 | do_ldstt (void) |
b05fe5cf | 8670 | { |
c19d1205 ZW |
8671 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
8672 | reject [Rn,...]. */ | |
8673 | if (inst.operands[1].preind) | |
b05fe5cf | 8674 | { |
bd3ba5d1 NC |
8675 | constraint (inst.reloc.exp.X_op != O_constant |
8676 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 8677 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 8678 | |
c19d1205 ZW |
8679 | inst.operands[1].preind = 0; |
8680 | inst.operands[1].postind = 1; | |
8681 | inst.operands[1].writeback = 1; | |
b05fe5cf | 8682 | } |
c19d1205 ZW |
8683 | inst.instruction |= inst.operands[0].reg << 12; |
8684 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
8685 | } | |
b05fe5cf | 8686 | |
c19d1205 | 8687 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 8688 | |
c19d1205 ZW |
8689 | static void |
8690 | do_ldstv4 (void) | |
8691 | { | |
ff4a8d2b | 8692 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
8693 | inst.instruction |= inst.operands[0].reg << 12; |
8694 | if (!inst.operands[1].isreg) | |
8335d6aa | 8695 | if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE)) |
b05fe5cf | 8696 | return; |
c19d1205 | 8697 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
8698 | } |
8699 | ||
8700 | static void | |
c19d1205 | 8701 | do_ldsttv4 (void) |
b05fe5cf | 8702 | { |
c19d1205 ZW |
8703 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
8704 | reject [Rn,...]. */ | |
8705 | if (inst.operands[1].preind) | |
b05fe5cf | 8706 | { |
bd3ba5d1 NC |
8707 | constraint (inst.reloc.exp.X_op != O_constant |
8708 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 8709 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 8710 | |
c19d1205 ZW |
8711 | inst.operands[1].preind = 0; |
8712 | inst.operands[1].postind = 1; | |
8713 | inst.operands[1].writeback = 1; | |
b05fe5cf | 8714 | } |
c19d1205 ZW |
8715 | inst.instruction |= inst.operands[0].reg << 12; |
8716 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
8717 | } | |
b05fe5cf | 8718 | |
c19d1205 ZW |
8719 | /* Co-processor register load/store. |
8720 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
8721 | static void | |
8722 | do_lstc (void) | |
8723 | { | |
8724 | inst.instruction |= inst.operands[0].reg << 8; | |
8725 | inst.instruction |= inst.operands[1].reg << 12; | |
8726 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
8727 | } |
8728 | ||
b05fe5cf | 8729 | static void |
c19d1205 | 8730 | do_mlas (void) |
b05fe5cf | 8731 | { |
8fb9d7b9 | 8732 | /* This restriction does not apply to mls (nor to mla in v6 or later). */ |
c19d1205 | 8733 | if (inst.operands[0].reg == inst.operands[1].reg |
8fb9d7b9 | 8734 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) |
c19d1205 | 8735 | && !(inst.instruction & 0x00400000)) |
8fb9d7b9 | 8736 | as_tsktsk (_("Rd and Rm should be different in mla")); |
b05fe5cf | 8737 | |
c19d1205 ZW |
8738 | inst.instruction |= inst.operands[0].reg << 16; |
8739 | inst.instruction |= inst.operands[1].reg; | |
8740 | inst.instruction |= inst.operands[2].reg << 8; | |
8741 | inst.instruction |= inst.operands[3].reg << 12; | |
c19d1205 | 8742 | } |
b05fe5cf | 8743 | |
c19d1205 ZW |
8744 | static void |
8745 | do_mov (void) | |
8746 | { | |
8747 | inst.instruction |= inst.operands[0].reg << 12; | |
8748 | encode_arm_shifter_operand (1); | |
8749 | } | |
b05fe5cf | 8750 | |
c19d1205 ZW |
8751 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
8752 | static void | |
8753 | do_mov16 (void) | |
8754 | { | |
b6895b4f PB |
8755 | bfd_vma imm; |
8756 | bfd_boolean top; | |
8757 | ||
8758 | top = (inst.instruction & 0x00400000) != 0; | |
8759 | constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, | |
8760 | _(":lower16: not allowed this instruction")); | |
8761 | constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, | |
8762 | _(":upper16: not allowed instruction")); | |
c19d1205 | 8763 | inst.instruction |= inst.operands[0].reg << 12; |
b6895b4f PB |
8764 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
8765 | { | |
8766 | imm = inst.reloc.exp.X_add_number; | |
8767 | /* The value is in two pieces: 0:11, 16:19. */ | |
8768 | inst.instruction |= (imm & 0x00000fff); | |
8769 | inst.instruction |= (imm & 0x0000f000) << 4; | |
8770 | } | |
b05fe5cf | 8771 | } |
b99bd4ef | 8772 | |
037e8744 JB |
8773 | static void do_vfp_nsyn_opcode (const char *); |
8774 | ||
8775 | static int | |
8776 | do_vfp_nsyn_mrs (void) | |
8777 | { | |
8778 | if (inst.operands[0].isvec) | |
8779 | { | |
8780 | if (inst.operands[1].reg != 1) | |
477330fc | 8781 | first_error (_("operand 1 must be FPSCR")); |
037e8744 JB |
8782 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); |
8783 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); | |
8784 | do_vfp_nsyn_opcode ("fmstat"); | |
8785 | } | |
8786 | else if (inst.operands[1].isvec) | |
8787 | do_vfp_nsyn_opcode ("fmrx"); | |
8788 | else | |
8789 | return FAIL; | |
5f4273c7 | 8790 | |
037e8744 JB |
8791 | return SUCCESS; |
8792 | } | |
8793 | ||
8794 | static int | |
8795 | do_vfp_nsyn_msr (void) | |
8796 | { | |
8797 | if (inst.operands[0].isvec) | |
8798 | do_vfp_nsyn_opcode ("fmxr"); | |
8799 | else | |
8800 | return FAIL; | |
8801 | ||
8802 | return SUCCESS; | |
8803 | } | |
8804 | ||
f7c21dc7 NC |
8805 | static void |
8806 | do_vmrs (void) | |
8807 | { | |
8808 | unsigned Rt = inst.operands[0].reg; | |
fa94de6b | 8809 | |
16d02dc9 | 8810 | if (thumb_mode && Rt == REG_SP) |
f7c21dc7 NC |
8811 | { |
8812 | inst.error = BAD_SP; | |
8813 | return; | |
8814 | } | |
8815 | ||
8816 | /* APSR_ sets isvec. All other refs to PC are illegal. */ | |
16d02dc9 | 8817 | if (!inst.operands[0].isvec && Rt == REG_PC) |
f7c21dc7 NC |
8818 | { |
8819 | inst.error = BAD_PC; | |
8820 | return; | |
8821 | } | |
8822 | ||
16d02dc9 JB |
8823 | /* If we get through parsing the register name, we just insert the number |
8824 | generated into the instruction without further validation. */ | |
8825 | inst.instruction |= (inst.operands[1].reg << 16); | |
f7c21dc7 NC |
8826 | inst.instruction |= (Rt << 12); |
8827 | } | |
8828 | ||
8829 | static void | |
8830 | do_vmsr (void) | |
8831 | { | |
8832 | unsigned Rt = inst.operands[1].reg; | |
fa94de6b | 8833 | |
f7c21dc7 NC |
8834 | if (thumb_mode) |
8835 | reject_bad_reg (Rt); | |
8836 | else if (Rt == REG_PC) | |
8837 | { | |
8838 | inst.error = BAD_PC; | |
8839 | return; | |
8840 | } | |
8841 | ||
16d02dc9 JB |
8842 | /* If we get through parsing the register name, we just insert the number |
8843 | generated into the instruction without further validation. */ | |
8844 | inst.instruction |= (inst.operands[0].reg << 16); | |
f7c21dc7 NC |
8845 | inst.instruction |= (Rt << 12); |
8846 | } | |
8847 | ||
b99bd4ef | 8848 | static void |
c19d1205 | 8849 | do_mrs (void) |
b99bd4ef | 8850 | { |
90ec0d68 MGD |
8851 | unsigned br; |
8852 | ||
037e8744 JB |
8853 | if (do_vfp_nsyn_mrs () == SUCCESS) |
8854 | return; | |
8855 | ||
ff4a8d2b | 8856 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 | 8857 | inst.instruction |= inst.operands[0].reg << 12; |
90ec0d68 MGD |
8858 | |
8859 | if (inst.operands[1].isreg) | |
8860 | { | |
8861 | br = inst.operands[1].reg; | |
8862 | if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000)) | |
8863 | as_bad (_("bad register for mrs")); | |
8864 | } | |
8865 | else | |
8866 | { | |
8867 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ | |
8868 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
8869 | != (PSR_c|PSR_f), | |
d2cd1205 | 8870 | _("'APSR', 'CPSR' or 'SPSR' expected")); |
90ec0d68 MGD |
8871 | br = (15<<16) | (inst.operands[1].imm & SPSR_BIT); |
8872 | } | |
8873 | ||
8874 | inst.instruction |= br; | |
c19d1205 | 8875 | } |
b99bd4ef | 8876 | |
c19d1205 ZW |
8877 | /* Two possible forms: |
8878 | "{C|S}PSR_<field>, Rm", | |
8879 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 8880 | |
c19d1205 ZW |
8881 | static void |
8882 | do_msr (void) | |
8883 | { | |
037e8744 JB |
8884 | if (do_vfp_nsyn_msr () == SUCCESS) |
8885 | return; | |
8886 | ||
c19d1205 ZW |
8887 | inst.instruction |= inst.operands[0].imm; |
8888 | if (inst.operands[1].isreg) | |
8889 | inst.instruction |= inst.operands[1].reg; | |
8890 | else | |
b99bd4ef | 8891 | { |
c19d1205 ZW |
8892 | inst.instruction |= INST_IMMEDIATE; |
8893 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
8894 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 8895 | } |
b99bd4ef NC |
8896 | } |
8897 | ||
c19d1205 ZW |
8898 | static void |
8899 | do_mul (void) | |
a737bd4d | 8900 | { |
ff4a8d2b NC |
8901 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
8902 | ||
c19d1205 ZW |
8903 | if (!inst.operands[2].present) |
8904 | inst.operands[2].reg = inst.operands[0].reg; | |
8905 | inst.instruction |= inst.operands[0].reg << 16; | |
8906 | inst.instruction |= inst.operands[1].reg; | |
8907 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 8908 | |
8fb9d7b9 MS |
8909 | if (inst.operands[0].reg == inst.operands[1].reg |
8910 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
8911 | as_tsktsk (_("Rd and Rm should be different in mul")); | |
a737bd4d NC |
8912 | } |
8913 | ||
c19d1205 ZW |
8914 | /* Long Multiply Parser |
8915 | UMULL RdLo, RdHi, Rm, Rs | |
8916 | SMULL RdLo, RdHi, Rm, Rs | |
8917 | UMLAL RdLo, RdHi, Rm, Rs | |
8918 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
8919 | |
8920 | static void | |
c19d1205 | 8921 | do_mull (void) |
b99bd4ef | 8922 | { |
c19d1205 ZW |
8923 | inst.instruction |= inst.operands[0].reg << 12; |
8924 | inst.instruction |= inst.operands[1].reg << 16; | |
8925 | inst.instruction |= inst.operands[2].reg; | |
8926 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 8927 | |
682b27ad PB |
8928 | /* rdhi and rdlo must be different. */ |
8929 | if (inst.operands[0].reg == inst.operands[1].reg) | |
8930 | as_tsktsk (_("rdhi and rdlo must be different")); | |
8931 | ||
8932 | /* rdhi, rdlo and rm must all be different before armv6. */ | |
8933 | if ((inst.operands[0].reg == inst.operands[2].reg | |
c19d1205 | 8934 | || inst.operands[1].reg == inst.operands[2].reg) |
682b27ad | 8935 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
c19d1205 ZW |
8936 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); |
8937 | } | |
b99bd4ef | 8938 | |
c19d1205 ZW |
8939 | static void |
8940 | do_nop (void) | |
8941 | { | |
e7495e45 NS |
8942 | if (inst.operands[0].present |
8943 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) | |
c19d1205 ZW |
8944 | { |
8945 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
8946 | inst.instruction &= 0xf0000000; | |
e7495e45 NS |
8947 | inst.instruction |= 0x0320f000; |
8948 | if (inst.operands[0].present) | |
8949 | inst.instruction |= inst.operands[0].imm; | |
c19d1205 | 8950 | } |
b99bd4ef NC |
8951 | } |
8952 | ||
c19d1205 ZW |
8953 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
8954 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
8955 | Condition defaults to COND_ALWAYS. | |
8956 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
8957 | |
8958 | static void | |
c19d1205 | 8959 | do_pkhbt (void) |
b99bd4ef | 8960 | { |
c19d1205 ZW |
8961 | inst.instruction |= inst.operands[0].reg << 12; |
8962 | inst.instruction |= inst.operands[1].reg << 16; | |
8963 | inst.instruction |= inst.operands[2].reg; | |
8964 | if (inst.operands[3].present) | |
8965 | encode_arm_shift (3); | |
8966 | } | |
b99bd4ef | 8967 | |
c19d1205 | 8968 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 8969 | |
c19d1205 ZW |
8970 | static void |
8971 | do_pkhtb (void) | |
8972 | { | |
8973 | if (!inst.operands[3].present) | |
b99bd4ef | 8974 | { |
c19d1205 ZW |
8975 | /* If the shift specifier is omitted, turn the instruction |
8976 | into pkhbt rd, rm, rn. */ | |
8977 | inst.instruction &= 0xfff00010; | |
8978 | inst.instruction |= inst.operands[0].reg << 12; | |
8979 | inst.instruction |= inst.operands[1].reg; | |
8980 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
8981 | } |
8982 | else | |
8983 | { | |
c19d1205 ZW |
8984 | inst.instruction |= inst.operands[0].reg << 12; |
8985 | inst.instruction |= inst.operands[1].reg << 16; | |
8986 | inst.instruction |= inst.operands[2].reg; | |
8987 | encode_arm_shift (3); | |
b99bd4ef NC |
8988 | } |
8989 | } | |
8990 | ||
c19d1205 | 8991 | /* ARMv5TE: Preload-Cache |
60e5ef9f | 8992 | MP Extensions: Preload for write |
c19d1205 | 8993 | |
60e5ef9f | 8994 | PLD(W) <addr_mode> |
c19d1205 ZW |
8995 | |
8996 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
8997 | |
8998 | static void | |
c19d1205 | 8999 | do_pld (void) |
b99bd4ef | 9000 | { |
c19d1205 ZW |
9001 | constraint (!inst.operands[0].isreg, |
9002 | _("'[' expected after PLD mnemonic")); | |
9003 | constraint (inst.operands[0].postind, | |
9004 | _("post-indexed expression used in preload instruction")); | |
9005 | constraint (inst.operands[0].writeback, | |
9006 | _("writeback used in preload instruction")); | |
9007 | constraint (!inst.operands[0].preind, | |
9008 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
9009 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
9010 | } | |
b99bd4ef | 9011 | |
62b3e311 PB |
9012 | /* ARMv7: PLI <addr_mode> */ |
9013 | static void | |
9014 | do_pli (void) | |
9015 | { | |
9016 | constraint (!inst.operands[0].isreg, | |
9017 | _("'[' expected after PLI mnemonic")); | |
9018 | constraint (inst.operands[0].postind, | |
9019 | _("post-indexed expression used in preload instruction")); | |
9020 | constraint (inst.operands[0].writeback, | |
9021 | _("writeback used in preload instruction")); | |
9022 | constraint (!inst.operands[0].preind, | |
9023 | _("unindexed addressing used in preload instruction")); | |
9024 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
9025 | inst.instruction &= ~PRE_INDEX; | |
9026 | } | |
9027 | ||
c19d1205 ZW |
9028 | static void |
9029 | do_push_pop (void) | |
9030 | { | |
9031 | inst.operands[1] = inst.operands[0]; | |
9032 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
9033 | inst.operands[0].isreg = 1; | |
9034 | inst.operands[0].writeback = 1; | |
9035 | inst.operands[0].reg = REG_SP; | |
6530b175 | 9036 | encode_ldmstm (/*from_push_pop_mnem=*/TRUE); |
c19d1205 | 9037 | } |
b99bd4ef | 9038 | |
c19d1205 ZW |
9039 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
9040 | word at the specified address and the following word | |
9041 | respectively. | |
9042 | Unconditionally executed. | |
9043 | Error if Rn is R15. */ | |
b99bd4ef | 9044 | |
c19d1205 ZW |
9045 | static void |
9046 | do_rfe (void) | |
9047 | { | |
9048 | inst.instruction |= inst.operands[0].reg << 16; | |
9049 | if (inst.operands[0].writeback) | |
9050 | inst.instruction |= WRITE_BACK; | |
9051 | } | |
b99bd4ef | 9052 | |
c19d1205 | 9053 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 9054 | |
c19d1205 ZW |
9055 | static void |
9056 | do_ssat (void) | |
9057 | { | |
9058 | inst.instruction |= inst.operands[0].reg << 12; | |
9059 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
9060 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 9061 | |
c19d1205 ZW |
9062 | if (inst.operands[3].present) |
9063 | encode_arm_shift (3); | |
b99bd4ef NC |
9064 | } |
9065 | ||
c19d1205 | 9066 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
9067 | |
9068 | static void | |
c19d1205 | 9069 | do_usat (void) |
b99bd4ef | 9070 | { |
c19d1205 ZW |
9071 | inst.instruction |= inst.operands[0].reg << 12; |
9072 | inst.instruction |= inst.operands[1].imm << 16; | |
9073 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 9074 | |
c19d1205 ZW |
9075 | if (inst.operands[3].present) |
9076 | encode_arm_shift (3); | |
b99bd4ef NC |
9077 | } |
9078 | ||
c19d1205 | 9079 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
9080 | |
9081 | static void | |
c19d1205 | 9082 | do_ssat16 (void) |
09d92015 | 9083 | { |
c19d1205 ZW |
9084 | inst.instruction |= inst.operands[0].reg << 12; |
9085 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
9086 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
9087 | } |
9088 | ||
c19d1205 ZW |
9089 | static void |
9090 | do_usat16 (void) | |
a737bd4d | 9091 | { |
c19d1205 ZW |
9092 | inst.instruction |= inst.operands[0].reg << 12; |
9093 | inst.instruction |= inst.operands[1].imm << 16; | |
9094 | inst.instruction |= inst.operands[2].reg; | |
9095 | } | |
a737bd4d | 9096 | |
c19d1205 ZW |
9097 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
9098 | preserving the other bits. | |
a737bd4d | 9099 | |
c19d1205 ZW |
9100 | setend <endian_specifier>, where <endian_specifier> is either |
9101 | BE or LE. */ | |
a737bd4d | 9102 | |
c19d1205 ZW |
9103 | static void |
9104 | do_setend (void) | |
9105 | { | |
12e37cbc MGD |
9106 | if (warn_on_deprecated |
9107 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
9108 | as_warn (_("setend use is deprecated for ARMv8")); | |
9109 | ||
c19d1205 ZW |
9110 | if (inst.operands[0].imm) |
9111 | inst.instruction |= 0x200; | |
a737bd4d NC |
9112 | } |
9113 | ||
9114 | static void | |
c19d1205 | 9115 | do_shift (void) |
a737bd4d | 9116 | { |
c19d1205 ZW |
9117 | unsigned int Rm = (inst.operands[1].present |
9118 | ? inst.operands[1].reg | |
9119 | : inst.operands[0].reg); | |
a737bd4d | 9120 | |
c19d1205 ZW |
9121 | inst.instruction |= inst.operands[0].reg << 12; |
9122 | inst.instruction |= Rm; | |
9123 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 9124 | { |
c19d1205 ZW |
9125 | inst.instruction |= inst.operands[2].reg << 8; |
9126 | inst.instruction |= SHIFT_BY_REG; | |
94342ec3 NC |
9127 | /* PR 12854: Error on extraneous shifts. */ |
9128 | constraint (inst.operands[2].shifted, | |
9129 | _("extraneous shift as part of operand to shift insn")); | |
a737bd4d NC |
9130 | } |
9131 | else | |
c19d1205 | 9132 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
9133 | } |
9134 | ||
09d92015 | 9135 | static void |
3eb17e6b | 9136 | do_smc (void) |
09d92015 | 9137 | { |
3eb17e6b | 9138 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 9139 | inst.reloc.pc_rel = 0; |
09d92015 MM |
9140 | } |
9141 | ||
90ec0d68 MGD |
9142 | static void |
9143 | do_hvc (void) | |
9144 | { | |
9145 | inst.reloc.type = BFD_RELOC_ARM_HVC; | |
9146 | inst.reloc.pc_rel = 0; | |
9147 | } | |
9148 | ||
09d92015 | 9149 | static void |
c19d1205 | 9150 | do_swi (void) |
09d92015 | 9151 | { |
c19d1205 ZW |
9152 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
9153 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
9154 | } |
9155 | ||
c19d1205 ZW |
9156 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
9157 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
9158 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
9159 | Error if any register is R15. */ | |
e16bb312 | 9160 | |
c19d1205 ZW |
9161 | static void |
9162 | do_smla (void) | |
e16bb312 | 9163 | { |
c19d1205 ZW |
9164 | inst.instruction |= inst.operands[0].reg << 16; |
9165 | inst.instruction |= inst.operands[1].reg; | |
9166 | inst.instruction |= inst.operands[2].reg << 8; | |
9167 | inst.instruction |= inst.operands[3].reg << 12; | |
9168 | } | |
a737bd4d | 9169 | |
c19d1205 ZW |
9170 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
9171 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
9172 | Error if any register is R15. | |
9173 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 9174 | |
c19d1205 ZW |
9175 | static void |
9176 | do_smlal (void) | |
9177 | { | |
9178 | inst.instruction |= inst.operands[0].reg << 12; | |
9179 | inst.instruction |= inst.operands[1].reg << 16; | |
9180 | inst.instruction |= inst.operands[2].reg; | |
9181 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 9182 | |
c19d1205 ZW |
9183 | if (inst.operands[0].reg == inst.operands[1].reg) |
9184 | as_tsktsk (_("rdhi and rdlo must be different")); | |
9185 | } | |
a737bd4d | 9186 | |
c19d1205 ZW |
9187 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
9188 | SMULxy{cond} Rd,Rm,Rs | |
9189 | Error if any register is R15. */ | |
a737bd4d | 9190 | |
c19d1205 ZW |
9191 | static void |
9192 | do_smul (void) | |
9193 | { | |
9194 | inst.instruction |= inst.operands[0].reg << 16; | |
9195 | inst.instruction |= inst.operands[1].reg; | |
9196 | inst.instruction |= inst.operands[2].reg << 8; | |
9197 | } | |
a737bd4d | 9198 | |
b6702015 PB |
9199 | /* ARM V6 srs (argument parse). The variable fields in the encoding are |
9200 | the same for both ARM and Thumb-2. */ | |
a737bd4d | 9201 | |
c19d1205 ZW |
9202 | static void |
9203 | do_srs (void) | |
9204 | { | |
b6702015 PB |
9205 | int reg; |
9206 | ||
9207 | if (inst.operands[0].present) | |
9208 | { | |
9209 | reg = inst.operands[0].reg; | |
fdfde340 | 9210 | constraint (reg != REG_SP, _("SRS base register must be r13")); |
b6702015 PB |
9211 | } |
9212 | else | |
fdfde340 | 9213 | reg = REG_SP; |
b6702015 PB |
9214 | |
9215 | inst.instruction |= reg << 16; | |
9216 | inst.instruction |= inst.operands[1].imm; | |
9217 | if (inst.operands[0].writeback || inst.operands[1].writeback) | |
c19d1205 ZW |
9218 | inst.instruction |= WRITE_BACK; |
9219 | } | |
a737bd4d | 9220 | |
c19d1205 | 9221 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 9222 | |
c19d1205 ZW |
9223 | static void |
9224 | do_strex (void) | |
9225 | { | |
9226 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
9227 | || inst.operands[2].postind || inst.operands[2].writeback | |
9228 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
9229 | || inst.operands[2].negative |
9230 | /* See comment in do_ldrex(). */ | |
9231 | || (inst.operands[2].reg == REG_PC), | |
9232 | BAD_ADDR_MODE); | |
a737bd4d | 9233 | |
c19d1205 ZW |
9234 | constraint (inst.operands[0].reg == inst.operands[1].reg |
9235 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 9236 | |
c19d1205 ZW |
9237 | constraint (inst.reloc.exp.X_op != O_constant |
9238 | || inst.reloc.exp.X_add_number != 0, | |
9239 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 9240 | |
c19d1205 ZW |
9241 | inst.instruction |= inst.operands[0].reg << 12; |
9242 | inst.instruction |= inst.operands[1].reg; | |
9243 | inst.instruction |= inst.operands[2].reg << 16; | |
9244 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
9245 | } |
9246 | ||
877807f8 NC |
9247 | static void |
9248 | do_t_strexbh (void) | |
9249 | { | |
9250 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
9251 | || inst.operands[2].postind || inst.operands[2].writeback | |
9252 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
9253 | || inst.operands[2].negative, | |
9254 | BAD_ADDR_MODE); | |
9255 | ||
9256 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
9257 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
9258 | ||
9259 | do_rm_rd_rn (); | |
9260 | } | |
9261 | ||
e16bb312 | 9262 | static void |
c19d1205 | 9263 | do_strexd (void) |
e16bb312 | 9264 | { |
c19d1205 ZW |
9265 | constraint (inst.operands[1].reg % 2 != 0, |
9266 | _("even register required")); | |
9267 | constraint (inst.operands[2].present | |
9268 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
9269 | _("can only store two consecutive registers")); | |
9270 | /* If op 2 were present and equal to PC, this function wouldn't | |
9271 | have been called in the first place. */ | |
9272 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 9273 | |
c19d1205 ZW |
9274 | constraint (inst.operands[0].reg == inst.operands[1].reg |
9275 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
9276 | || inst.operands[0].reg == inst.operands[3].reg, | |
9277 | BAD_OVERLAP); | |
e16bb312 | 9278 | |
c19d1205 ZW |
9279 | inst.instruction |= inst.operands[0].reg << 12; |
9280 | inst.instruction |= inst.operands[1].reg; | |
9281 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
9282 | } |
9283 | ||
9eb6c0f1 MGD |
9284 | /* ARM V8 STRL. */ |
9285 | static void | |
4b8c8c02 | 9286 | do_stlex (void) |
9eb6c0f1 MGD |
9287 | { |
9288 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
9289 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
9290 | ||
9291 | do_rd_rm_rn (); | |
9292 | } | |
9293 | ||
9294 | static void | |
4b8c8c02 | 9295 | do_t_stlex (void) |
9eb6c0f1 MGD |
9296 | { |
9297 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
9298 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
9299 | ||
9300 | do_rm_rd_rn (); | |
9301 | } | |
9302 | ||
c19d1205 ZW |
9303 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
9304 | extends it to 32-bits, and adds the result to a value in another | |
9305 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
9306 | before extracting the 16-bit value. | |
9307 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
9308 | Condition defaults to COND_ALWAYS. | |
9309 | Error if any register uses R15. */ | |
9310 | ||
e16bb312 | 9311 | static void |
c19d1205 | 9312 | do_sxtah (void) |
e16bb312 | 9313 | { |
c19d1205 ZW |
9314 | inst.instruction |= inst.operands[0].reg << 12; |
9315 | inst.instruction |= inst.operands[1].reg << 16; | |
9316 | inst.instruction |= inst.operands[2].reg; | |
9317 | inst.instruction |= inst.operands[3].imm << 10; | |
9318 | } | |
e16bb312 | 9319 | |
c19d1205 | 9320 | /* ARM V6 SXTH. |
e16bb312 | 9321 | |
c19d1205 ZW |
9322 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
9323 | Condition defaults to COND_ALWAYS. | |
9324 | Error if any register uses R15. */ | |
e16bb312 NC |
9325 | |
9326 | static void | |
c19d1205 | 9327 | do_sxth (void) |
e16bb312 | 9328 | { |
c19d1205 ZW |
9329 | inst.instruction |= inst.operands[0].reg << 12; |
9330 | inst.instruction |= inst.operands[1].reg; | |
9331 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 9332 | } |
c19d1205 ZW |
9333 | \f |
9334 | /* VFP instructions. In a logical order: SP variant first, monad | |
9335 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
9336 | |
9337 | static void | |
c19d1205 | 9338 | do_vfp_sp_monadic (void) |
e16bb312 | 9339 | { |
5287ad62 JB |
9340 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
9341 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
9342 | } |
9343 | ||
9344 | static void | |
c19d1205 | 9345 | do_vfp_sp_dyadic (void) |
e16bb312 | 9346 | { |
5287ad62 JB |
9347 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
9348 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
9349 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
9350 | } |
9351 | ||
9352 | static void | |
c19d1205 | 9353 | do_vfp_sp_compare_z (void) |
e16bb312 | 9354 | { |
5287ad62 | 9355 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
9356 | } |
9357 | ||
9358 | static void | |
c19d1205 | 9359 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 9360 | { |
5287ad62 JB |
9361 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
9362 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
9363 | } |
9364 | ||
9365 | static void | |
c19d1205 | 9366 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 9367 | { |
5287ad62 JB |
9368 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
9369 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
e16bb312 NC |
9370 | } |
9371 | ||
9372 | static void | |
c19d1205 | 9373 | do_vfp_reg_from_sp (void) |
e16bb312 | 9374 | { |
c19d1205 | 9375 | inst.instruction |= inst.operands[0].reg << 12; |
5287ad62 | 9376 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
e16bb312 NC |
9377 | } |
9378 | ||
9379 | static void | |
c19d1205 | 9380 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 9381 | { |
c19d1205 ZW |
9382 | constraint (inst.operands[2].imm != 2, |
9383 | _("only two consecutive VFP SP registers allowed here")); | |
9384 | inst.instruction |= inst.operands[0].reg << 12; | |
9385 | inst.instruction |= inst.operands[1].reg << 16; | |
5287ad62 | 9386 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
e16bb312 NC |
9387 | } |
9388 | ||
9389 | static void | |
c19d1205 | 9390 | do_vfp_sp_from_reg (void) |
e16bb312 | 9391 | { |
5287ad62 | 9392 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
c19d1205 | 9393 | inst.instruction |= inst.operands[1].reg << 12; |
e16bb312 NC |
9394 | } |
9395 | ||
9396 | static void | |
c19d1205 | 9397 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 9398 | { |
c19d1205 ZW |
9399 | constraint (inst.operands[0].imm != 2, |
9400 | _("only two consecutive VFP SP registers allowed here")); | |
5287ad62 | 9401 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
c19d1205 ZW |
9402 | inst.instruction |= inst.operands[1].reg << 12; |
9403 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
9404 | } |
9405 | ||
9406 | static void | |
c19d1205 | 9407 | do_vfp_sp_ldst (void) |
e16bb312 | 9408 | { |
5287ad62 | 9409 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
c19d1205 | 9410 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
9411 | } |
9412 | ||
9413 | static void | |
c19d1205 | 9414 | do_vfp_dp_ldst (void) |
e16bb312 | 9415 | { |
5287ad62 | 9416 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
c19d1205 | 9417 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
9418 | } |
9419 | ||
c19d1205 | 9420 | |
e16bb312 | 9421 | static void |
c19d1205 | 9422 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 9423 | { |
c19d1205 ZW |
9424 | if (inst.operands[0].writeback) |
9425 | inst.instruction |= WRITE_BACK; | |
9426 | else | |
9427 | constraint (ldstm_type != VFP_LDSTMIA, | |
9428 | _("this addressing mode requires base-register writeback")); | |
9429 | inst.instruction |= inst.operands[0].reg << 16; | |
5287ad62 | 9430 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
c19d1205 | 9431 | inst.instruction |= inst.operands[1].imm; |
e16bb312 NC |
9432 | } |
9433 | ||
9434 | static void | |
c19d1205 | 9435 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 9436 | { |
c19d1205 | 9437 | int count; |
e16bb312 | 9438 | |
c19d1205 ZW |
9439 | if (inst.operands[0].writeback) |
9440 | inst.instruction |= WRITE_BACK; | |
9441 | else | |
9442 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
9443 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 9444 | |
c19d1205 | 9445 | inst.instruction |= inst.operands[0].reg << 16; |
5287ad62 | 9446 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
e16bb312 | 9447 | |
c19d1205 ZW |
9448 | count = inst.operands[1].imm << 1; |
9449 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
9450 | count += 1; | |
e16bb312 | 9451 | |
c19d1205 | 9452 | inst.instruction |= count; |
e16bb312 NC |
9453 | } |
9454 | ||
9455 | static void | |
c19d1205 | 9456 | do_vfp_sp_ldstmia (void) |
e16bb312 | 9457 | { |
c19d1205 | 9458 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
9459 | } |
9460 | ||
9461 | static void | |
c19d1205 | 9462 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 9463 | { |
c19d1205 | 9464 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
9465 | } |
9466 | ||
9467 | static void | |
c19d1205 | 9468 | do_vfp_dp_ldstmia (void) |
e16bb312 | 9469 | { |
c19d1205 | 9470 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
9471 | } |
9472 | ||
9473 | static void | |
c19d1205 | 9474 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 9475 | { |
c19d1205 | 9476 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
9477 | } |
9478 | ||
9479 | static void | |
c19d1205 | 9480 | do_vfp_xp_ldstmia (void) |
e16bb312 | 9481 | { |
c19d1205 ZW |
9482 | vfp_dp_ldstm (VFP_LDSTMIAX); |
9483 | } | |
e16bb312 | 9484 | |
c19d1205 ZW |
9485 | static void |
9486 | do_vfp_xp_ldstmdb (void) | |
9487 | { | |
9488 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 9489 | } |
5287ad62 JB |
9490 | |
9491 | static void | |
9492 | do_vfp_dp_rd_rm (void) | |
9493 | { | |
9494 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9495 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
9496 | } | |
9497 | ||
9498 | static void | |
9499 | do_vfp_dp_rn_rd (void) | |
9500 | { | |
9501 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); | |
9502 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
9503 | } | |
9504 | ||
9505 | static void | |
9506 | do_vfp_dp_rd_rn (void) | |
9507 | { | |
9508 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9509 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
9510 | } | |
9511 | ||
9512 | static void | |
9513 | do_vfp_dp_rd_rn_rm (void) | |
9514 | { | |
9515 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9516 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
9517 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); | |
9518 | } | |
9519 | ||
9520 | static void | |
9521 | do_vfp_dp_rd (void) | |
9522 | { | |
9523 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9524 | } | |
9525 | ||
9526 | static void | |
9527 | do_vfp_dp_rm_rd_rn (void) | |
9528 | { | |
9529 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); | |
9530 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
9531 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); | |
9532 | } | |
9533 | ||
9534 | /* VFPv3 instructions. */ | |
9535 | static void | |
9536 | do_vfp_sp_const (void) | |
9537 | { | |
9538 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
00249aaa PB |
9539 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
9540 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
9541 | } |
9542 | ||
9543 | static void | |
9544 | do_vfp_dp_const (void) | |
9545 | { | |
9546 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
00249aaa PB |
9547 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
9548 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
9549 | } |
9550 | ||
9551 | static void | |
9552 | vfp_conv (int srcsize) | |
9553 | { | |
5f1af56b MGD |
9554 | int immbits = srcsize - inst.operands[1].imm; |
9555 | ||
fa94de6b RM |
9556 | if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize)) |
9557 | { | |
5f1af56b | 9558 | /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16. |
477330fc | 9559 | i.e. immbits must be in range 0 - 16. */ |
5f1af56b MGD |
9560 | inst.error = _("immediate value out of range, expected range [0, 16]"); |
9561 | return; | |
9562 | } | |
fa94de6b | 9563 | else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize)) |
5f1af56b MGD |
9564 | { |
9565 | /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32. | |
477330fc | 9566 | i.e. immbits must be in range 0 - 31. */ |
5f1af56b MGD |
9567 | inst.error = _("immediate value out of range, expected range [1, 32]"); |
9568 | return; | |
9569 | } | |
9570 | ||
5287ad62 JB |
9571 | inst.instruction |= (immbits & 1) << 5; |
9572 | inst.instruction |= (immbits >> 1); | |
9573 | } | |
9574 | ||
9575 | static void | |
9576 | do_vfp_sp_conv_16 (void) | |
9577 | { | |
9578 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
9579 | vfp_conv (16); | |
9580 | } | |
9581 | ||
9582 | static void | |
9583 | do_vfp_dp_conv_16 (void) | |
9584 | { | |
9585 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9586 | vfp_conv (16); | |
9587 | } | |
9588 | ||
9589 | static void | |
9590 | do_vfp_sp_conv_32 (void) | |
9591 | { | |
9592 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
9593 | vfp_conv (32); | |
9594 | } | |
9595 | ||
9596 | static void | |
9597 | do_vfp_dp_conv_32 (void) | |
9598 | { | |
9599 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9600 | vfp_conv (32); | |
9601 | } | |
c19d1205 ZW |
9602 | \f |
9603 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 9604 | |
c19d1205 ZW |
9605 | static void |
9606 | do_fpa_cmp (void) | |
9607 | { | |
9608 | inst.instruction |= inst.operands[0].reg << 16; | |
9609 | inst.instruction |= inst.operands[1].reg; | |
9610 | } | |
b99bd4ef NC |
9611 | |
9612 | static void | |
c19d1205 | 9613 | do_fpa_ldmstm (void) |
b99bd4ef | 9614 | { |
c19d1205 ZW |
9615 | inst.instruction |= inst.operands[0].reg << 12; |
9616 | switch (inst.operands[1].imm) | |
9617 | { | |
9618 | case 1: inst.instruction |= CP_T_X; break; | |
9619 | case 2: inst.instruction |= CP_T_Y; break; | |
9620 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
9621 | case 4: break; | |
9622 | default: abort (); | |
9623 | } | |
b99bd4ef | 9624 | |
c19d1205 ZW |
9625 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
9626 | { | |
9627 | /* The instruction specified "ea" or "fd", so we can only accept | |
9628 | [Rn]{!}. The instruction does not really support stacking or | |
9629 | unstacking, so we have to emulate these by setting appropriate | |
9630 | bits and offsets. */ | |
9631 | constraint (inst.reloc.exp.X_op != O_constant | |
9632 | || inst.reloc.exp.X_add_number != 0, | |
9633 | _("this instruction does not support indexing")); | |
b99bd4ef | 9634 | |
c19d1205 ZW |
9635 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
9636 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 9637 | |
c19d1205 ZW |
9638 | if (!(inst.instruction & INDEX_UP)) |
9639 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 9640 | |
c19d1205 ZW |
9641 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
9642 | { | |
9643 | inst.operands[2].preind = 0; | |
9644 | inst.operands[2].postind = 1; | |
9645 | } | |
9646 | } | |
b99bd4ef | 9647 | |
c19d1205 | 9648 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 9649 | } |
c19d1205 ZW |
9650 | \f |
9651 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 9652 | |
c19d1205 ZW |
9653 | static void |
9654 | do_iwmmxt_tandorc (void) | |
9655 | { | |
9656 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
9657 | } | |
b99bd4ef | 9658 | |
c19d1205 ZW |
9659 | static void |
9660 | do_iwmmxt_textrc (void) | |
9661 | { | |
9662 | inst.instruction |= inst.operands[0].reg << 12; | |
9663 | inst.instruction |= inst.operands[1].imm; | |
9664 | } | |
b99bd4ef NC |
9665 | |
9666 | static void | |
c19d1205 | 9667 | do_iwmmxt_textrm (void) |
b99bd4ef | 9668 | { |
c19d1205 ZW |
9669 | inst.instruction |= inst.operands[0].reg << 12; |
9670 | inst.instruction |= inst.operands[1].reg << 16; | |
9671 | inst.instruction |= inst.operands[2].imm; | |
9672 | } | |
b99bd4ef | 9673 | |
c19d1205 ZW |
9674 | static void |
9675 | do_iwmmxt_tinsr (void) | |
9676 | { | |
9677 | inst.instruction |= inst.operands[0].reg << 16; | |
9678 | inst.instruction |= inst.operands[1].reg << 12; | |
9679 | inst.instruction |= inst.operands[2].imm; | |
9680 | } | |
b99bd4ef | 9681 | |
c19d1205 ZW |
9682 | static void |
9683 | do_iwmmxt_tmia (void) | |
9684 | { | |
9685 | inst.instruction |= inst.operands[0].reg << 5; | |
9686 | inst.instruction |= inst.operands[1].reg; | |
9687 | inst.instruction |= inst.operands[2].reg << 12; | |
9688 | } | |
b99bd4ef | 9689 | |
c19d1205 ZW |
9690 | static void |
9691 | do_iwmmxt_waligni (void) | |
9692 | { | |
9693 | inst.instruction |= inst.operands[0].reg << 12; | |
9694 | inst.instruction |= inst.operands[1].reg << 16; | |
9695 | inst.instruction |= inst.operands[2].reg; | |
9696 | inst.instruction |= inst.operands[3].imm << 20; | |
9697 | } | |
b99bd4ef | 9698 | |
2d447fca JM |
9699 | static void |
9700 | do_iwmmxt_wmerge (void) | |
9701 | { | |
9702 | inst.instruction |= inst.operands[0].reg << 12; | |
9703 | inst.instruction |= inst.operands[1].reg << 16; | |
9704 | inst.instruction |= inst.operands[2].reg; | |
9705 | inst.instruction |= inst.operands[3].imm << 21; | |
9706 | } | |
9707 | ||
c19d1205 ZW |
9708 | static void |
9709 | do_iwmmxt_wmov (void) | |
9710 | { | |
9711 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
9712 | inst.instruction |= inst.operands[0].reg << 12; | |
9713 | inst.instruction |= inst.operands[1].reg << 16; | |
9714 | inst.instruction |= inst.operands[1].reg; | |
9715 | } | |
b99bd4ef | 9716 | |
c19d1205 ZW |
9717 | static void |
9718 | do_iwmmxt_wldstbh (void) | |
9719 | { | |
8f06b2d8 | 9720 | int reloc; |
c19d1205 | 9721 | inst.instruction |= inst.operands[0].reg << 12; |
8f06b2d8 PB |
9722 | if (thumb_mode) |
9723 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
9724 | else | |
9725 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
9726 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
9727 | } |
9728 | ||
c19d1205 ZW |
9729 | static void |
9730 | do_iwmmxt_wldstw (void) | |
9731 | { | |
9732 | /* RIWR_RIWC clears .isreg for a control register. */ | |
9733 | if (!inst.operands[0].isreg) | |
9734 | { | |
9735 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
9736 | inst.instruction |= 0xf0000000; | |
9737 | } | |
b99bd4ef | 9738 | |
c19d1205 ZW |
9739 | inst.instruction |= inst.operands[0].reg << 12; |
9740 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
9741 | } | |
b99bd4ef NC |
9742 | |
9743 | static void | |
c19d1205 | 9744 | do_iwmmxt_wldstd (void) |
b99bd4ef | 9745 | { |
c19d1205 | 9746 | inst.instruction |= inst.operands[0].reg << 12; |
2d447fca JM |
9747 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) |
9748 | && inst.operands[1].immisreg) | |
9749 | { | |
9750 | inst.instruction &= ~0x1a000ff; | |
9751 | inst.instruction |= (0xf << 28); | |
9752 | if (inst.operands[1].preind) | |
9753 | inst.instruction |= PRE_INDEX; | |
9754 | if (!inst.operands[1].negative) | |
9755 | inst.instruction |= INDEX_UP; | |
9756 | if (inst.operands[1].writeback) | |
9757 | inst.instruction |= WRITE_BACK; | |
9758 | inst.instruction |= inst.operands[1].reg << 16; | |
9759 | inst.instruction |= inst.reloc.exp.X_add_number << 4; | |
9760 | inst.instruction |= inst.operands[1].imm; | |
9761 | } | |
9762 | else | |
9763 | encode_arm_cp_address (1, TRUE, FALSE, 0); | |
c19d1205 | 9764 | } |
b99bd4ef | 9765 | |
c19d1205 ZW |
9766 | static void |
9767 | do_iwmmxt_wshufh (void) | |
9768 | { | |
9769 | inst.instruction |= inst.operands[0].reg << 12; | |
9770 | inst.instruction |= inst.operands[1].reg << 16; | |
9771 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
9772 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
9773 | } | |
b99bd4ef | 9774 | |
c19d1205 ZW |
9775 | static void |
9776 | do_iwmmxt_wzero (void) | |
9777 | { | |
9778 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
9779 | inst.instruction |= inst.operands[0].reg; | |
9780 | inst.instruction |= inst.operands[0].reg << 12; | |
9781 | inst.instruction |= inst.operands[0].reg << 16; | |
9782 | } | |
2d447fca JM |
9783 | |
9784 | static void | |
9785 | do_iwmmxt_wrwrwr_or_imm5 (void) | |
9786 | { | |
9787 | if (inst.operands[2].isreg) | |
9788 | do_rd_rn_rm (); | |
9789 | else { | |
9790 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), | |
9791 | _("immediate operand requires iWMMXt2")); | |
9792 | do_rd_rn (); | |
9793 | if (inst.operands[2].imm == 0) | |
9794 | { | |
9795 | switch ((inst.instruction >> 20) & 0xf) | |
9796 | { | |
9797 | case 4: | |
9798 | case 5: | |
9799 | case 6: | |
5f4273c7 | 9800 | case 7: |
2d447fca JM |
9801 | /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ |
9802 | inst.operands[2].imm = 16; | |
9803 | inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); | |
9804 | break; | |
9805 | case 8: | |
9806 | case 9: | |
9807 | case 10: | |
9808 | case 11: | |
9809 | /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ | |
9810 | inst.operands[2].imm = 32; | |
9811 | inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); | |
9812 | break; | |
9813 | case 12: | |
9814 | case 13: | |
9815 | case 14: | |
9816 | case 15: | |
9817 | { | |
9818 | /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ | |
9819 | unsigned long wrn; | |
9820 | wrn = (inst.instruction >> 16) & 0xf; | |
9821 | inst.instruction &= 0xff0fff0f; | |
9822 | inst.instruction |= wrn; | |
9823 | /* Bail out here; the instruction is now assembled. */ | |
9824 | return; | |
9825 | } | |
9826 | } | |
9827 | } | |
9828 | /* Map 32 -> 0, etc. */ | |
9829 | inst.operands[2].imm &= 0x1f; | |
9830 | inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); | |
9831 | } | |
9832 | } | |
c19d1205 ZW |
9833 | \f |
9834 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
9835 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 9836 | |
c19d1205 | 9837 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 9838 | |
c19d1205 ZW |
9839 | static void |
9840 | do_mav_triple (void) | |
9841 | { | |
9842 | inst.instruction |= inst.operands[0].reg << 16; | |
9843 | inst.instruction |= inst.operands[1].reg; | |
9844 | inst.instruction |= inst.operands[2].reg << 12; | |
9845 | } | |
b99bd4ef | 9846 | |
c19d1205 ZW |
9847 | /* Insns like "foo W,X,Y,Z". |
9848 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 9849 | |
c19d1205 ZW |
9850 | static void |
9851 | do_mav_quad (void) | |
9852 | { | |
9853 | inst.instruction |= inst.operands[0].reg << 5; | |
9854 | inst.instruction |= inst.operands[1].reg << 12; | |
9855 | inst.instruction |= inst.operands[2].reg << 16; | |
9856 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
9857 | } |
9858 | ||
c19d1205 ZW |
9859 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
9860 | static void | |
9861 | do_mav_dspsc (void) | |
a737bd4d | 9862 | { |
c19d1205 ZW |
9863 | inst.instruction |= inst.operands[1].reg << 12; |
9864 | } | |
a737bd4d | 9865 | |
c19d1205 ZW |
9866 | /* Maverick shift immediate instructions. |
9867 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
9868 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 9869 | |
c19d1205 ZW |
9870 | static void |
9871 | do_mav_shift (void) | |
9872 | { | |
9873 | int imm = inst.operands[2].imm; | |
a737bd4d | 9874 | |
c19d1205 ZW |
9875 | inst.instruction |= inst.operands[0].reg << 12; |
9876 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 9877 | |
c19d1205 ZW |
9878 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
9879 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
9880 | Bit 4 should be 0. */ | |
9881 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 9882 | |
c19d1205 ZW |
9883 | inst.instruction |= imm; |
9884 | } | |
9885 | \f | |
9886 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 9887 | |
c19d1205 ZW |
9888 | /* Xscale multiply-accumulate (argument parse) |
9889 | MIAcc acc0,Rm,Rs | |
9890 | MIAPHcc acc0,Rm,Rs | |
9891 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 9892 | |
c19d1205 ZW |
9893 | static void |
9894 | do_xsc_mia (void) | |
9895 | { | |
9896 | inst.instruction |= inst.operands[1].reg; | |
9897 | inst.instruction |= inst.operands[2].reg << 12; | |
9898 | } | |
a737bd4d | 9899 | |
c19d1205 | 9900 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 9901 | |
c19d1205 | 9902 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 9903 | |
c19d1205 ZW |
9904 | static void |
9905 | do_xsc_mar (void) | |
9906 | { | |
9907 | inst.instruction |= inst.operands[1].reg << 12; | |
9908 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
9909 | } |
9910 | ||
c19d1205 | 9911 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 9912 | |
c19d1205 | 9913 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
9914 | |
9915 | static void | |
c19d1205 | 9916 | do_xsc_mra (void) |
b99bd4ef | 9917 | { |
c19d1205 ZW |
9918 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
9919 | inst.instruction |= inst.operands[0].reg << 12; | |
9920 | inst.instruction |= inst.operands[1].reg << 16; | |
9921 | } | |
9922 | \f | |
9923 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 9924 | |
c19d1205 ZW |
9925 | /* inst.operands[i] is a shifted-register operand; encode |
9926 | it into inst.instruction in the format used by Thumb32. */ | |
9927 | ||
9928 | static void | |
9929 | encode_thumb32_shifted_operand (int i) | |
9930 | { | |
9931 | unsigned int value = inst.reloc.exp.X_add_number; | |
9932 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 9933 | |
9c3c69f2 PB |
9934 | constraint (inst.operands[i].immisreg, |
9935 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
9936 | inst.instruction |= inst.operands[i].reg; |
9937 | if (shift == SHIFT_RRX) | |
9938 | inst.instruction |= SHIFT_ROR << 4; | |
9939 | else | |
b99bd4ef | 9940 | { |
c19d1205 ZW |
9941 | constraint (inst.reloc.exp.X_op != O_constant, |
9942 | _("expression too complex")); | |
9943 | ||
9944 | constraint (value > 32 | |
9945 | || (value == 32 && (shift == SHIFT_LSL | |
9946 | || shift == SHIFT_ROR)), | |
9947 | _("shift expression is too large")); | |
9948 | ||
9949 | if (value == 0) | |
9950 | shift = SHIFT_LSL; | |
9951 | else if (value == 32) | |
9952 | value = 0; | |
9953 | ||
9954 | inst.instruction |= shift << 4; | |
9955 | inst.instruction |= (value & 0x1c) << 10; | |
9956 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 9957 | } |
c19d1205 | 9958 | } |
b99bd4ef | 9959 | |
b99bd4ef | 9960 | |
c19d1205 ZW |
9961 | /* inst.operands[i] was set up by parse_address. Encode it into a |
9962 | Thumb32 format load or store instruction. Reject forms that cannot | |
9963 | be used with such instructions. If is_t is true, reject forms that | |
9964 | cannot be used with a T instruction; if is_d is true, reject forms | |
5be8be5d DG |
9965 | that cannot be used with a D instruction. If it is a store insn, |
9966 | reject PC in Rn. */ | |
b99bd4ef | 9967 | |
c19d1205 ZW |
9968 | static void |
9969 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
9970 | { | |
5be8be5d | 9971 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
c19d1205 ZW |
9972 | |
9973 | constraint (!inst.operands[i].isreg, | |
53365c0d | 9974 | _("Instruction does not support =N addresses")); |
b99bd4ef | 9975 | |
c19d1205 ZW |
9976 | inst.instruction |= inst.operands[i].reg << 16; |
9977 | if (inst.operands[i].immisreg) | |
b99bd4ef | 9978 | { |
5be8be5d | 9979 | constraint (is_pc, BAD_PC_ADDRESSING); |
c19d1205 ZW |
9980 | constraint (is_t || is_d, _("cannot use register index with this instruction")); |
9981 | constraint (inst.operands[i].negative, | |
9982 | _("Thumb does not support negative register indexing")); | |
9983 | constraint (inst.operands[i].postind, | |
9984 | _("Thumb does not support register post-indexing")); | |
9985 | constraint (inst.operands[i].writeback, | |
9986 | _("Thumb does not support register indexing with writeback")); | |
9987 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
9988 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 9989 | |
f40d1643 | 9990 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 9991 | if (inst.operands[i].shifted) |
b99bd4ef | 9992 | { |
c19d1205 ZW |
9993 | constraint (inst.reloc.exp.X_op != O_constant, |
9994 | _("expression too complex")); | |
9c3c69f2 PB |
9995 | constraint (inst.reloc.exp.X_add_number < 0 |
9996 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 9997 | _("shift out of range")); |
9c3c69f2 | 9998 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
9999 | } |
10000 | inst.reloc.type = BFD_RELOC_UNUSED; | |
10001 | } | |
10002 | else if (inst.operands[i].preind) | |
10003 | { | |
5be8be5d | 10004 | constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); |
f40d1643 | 10005 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 | 10006 | _("cannot use writeback with this instruction")); |
4755303e WN |
10007 | constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0), |
10008 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
10009 | |
10010 | if (is_d) | |
10011 | { | |
10012 | inst.instruction |= 0x01000000; | |
10013 | if (inst.operands[i].writeback) | |
10014 | inst.instruction |= 0x00200000; | |
b99bd4ef | 10015 | } |
c19d1205 | 10016 | else |
b99bd4ef | 10017 | { |
c19d1205 ZW |
10018 | inst.instruction |= 0x00000c00; |
10019 | if (inst.operands[i].writeback) | |
10020 | inst.instruction |= 0x00000100; | |
b99bd4ef | 10021 | } |
c19d1205 | 10022 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 10023 | } |
c19d1205 | 10024 | else if (inst.operands[i].postind) |
b99bd4ef | 10025 | { |
9c2799c2 | 10026 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
10027 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); |
10028 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
10029 | ||
10030 | if (is_d) | |
10031 | inst.instruction |= 0x00200000; | |
10032 | else | |
10033 | inst.instruction |= 0x00000900; | |
10034 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
10035 | } | |
10036 | else /* unindexed - only for coprocessor */ | |
10037 | inst.error = _("instruction does not accept unindexed addressing"); | |
10038 | } | |
10039 | ||
10040 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
10041 | encodings (the latter only in post-V6T2 cores). The index is the | |
10042 | value used in the insns table below. When there is more than one | |
10043 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
10044 | holds variant (1). |
10045 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 | 10046 | #define T16_32_TAB \ |
21d799b5 NC |
10047 | X(_adc, 4140, eb400000), \ |
10048 | X(_adcs, 4140, eb500000), \ | |
10049 | X(_add, 1c00, eb000000), \ | |
10050 | X(_adds, 1c00, eb100000), \ | |
10051 | X(_addi, 0000, f1000000), \ | |
10052 | X(_addis, 0000, f1100000), \ | |
10053 | X(_add_pc,000f, f20f0000), \ | |
10054 | X(_add_sp,000d, f10d0000), \ | |
10055 | X(_adr, 000f, f20f0000), \ | |
10056 | X(_and, 4000, ea000000), \ | |
10057 | X(_ands, 4000, ea100000), \ | |
10058 | X(_asr, 1000, fa40f000), \ | |
10059 | X(_asrs, 1000, fa50f000), \ | |
10060 | X(_b, e000, f000b000), \ | |
10061 | X(_bcond, d000, f0008000), \ | |
10062 | X(_bic, 4380, ea200000), \ | |
10063 | X(_bics, 4380, ea300000), \ | |
10064 | X(_cmn, 42c0, eb100f00), \ | |
10065 | X(_cmp, 2800, ebb00f00), \ | |
10066 | X(_cpsie, b660, f3af8400), \ | |
10067 | X(_cpsid, b670, f3af8600), \ | |
10068 | X(_cpy, 4600, ea4f0000), \ | |
10069 | X(_dec_sp,80dd, f1ad0d00), \ | |
10070 | X(_eor, 4040, ea800000), \ | |
10071 | X(_eors, 4040, ea900000), \ | |
10072 | X(_inc_sp,00dd, f10d0d00), \ | |
10073 | X(_ldmia, c800, e8900000), \ | |
10074 | X(_ldr, 6800, f8500000), \ | |
10075 | X(_ldrb, 7800, f8100000), \ | |
10076 | X(_ldrh, 8800, f8300000), \ | |
10077 | X(_ldrsb, 5600, f9100000), \ | |
10078 | X(_ldrsh, 5e00, f9300000), \ | |
10079 | X(_ldr_pc,4800, f85f0000), \ | |
10080 | X(_ldr_pc2,4800, f85f0000), \ | |
10081 | X(_ldr_sp,9800, f85d0000), \ | |
10082 | X(_lsl, 0000, fa00f000), \ | |
10083 | X(_lsls, 0000, fa10f000), \ | |
10084 | X(_lsr, 0800, fa20f000), \ | |
10085 | X(_lsrs, 0800, fa30f000), \ | |
10086 | X(_mov, 2000, ea4f0000), \ | |
10087 | X(_movs, 2000, ea5f0000), \ | |
10088 | X(_mul, 4340, fb00f000), \ | |
10089 | X(_muls, 4340, ffffffff), /* no 32b muls */ \ | |
10090 | X(_mvn, 43c0, ea6f0000), \ | |
10091 | X(_mvns, 43c0, ea7f0000), \ | |
10092 | X(_neg, 4240, f1c00000), /* rsb #0 */ \ | |
10093 | X(_negs, 4240, f1d00000), /* rsbs #0 */ \ | |
10094 | X(_orr, 4300, ea400000), \ | |
10095 | X(_orrs, 4300, ea500000), \ | |
10096 | X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \ | |
10097 | X(_push, b400, e92d0000), /* stmdb sp!,... */ \ | |
10098 | X(_rev, ba00, fa90f080), \ | |
10099 | X(_rev16, ba40, fa90f090), \ | |
10100 | X(_revsh, bac0, fa90f0b0), \ | |
10101 | X(_ror, 41c0, fa60f000), \ | |
10102 | X(_rors, 41c0, fa70f000), \ | |
10103 | X(_sbc, 4180, eb600000), \ | |
10104 | X(_sbcs, 4180, eb700000), \ | |
10105 | X(_stmia, c000, e8800000), \ | |
10106 | X(_str, 6000, f8400000), \ | |
10107 | X(_strb, 7000, f8000000), \ | |
10108 | X(_strh, 8000, f8200000), \ | |
10109 | X(_str_sp,9000, f84d0000), \ | |
10110 | X(_sub, 1e00, eba00000), \ | |
10111 | X(_subs, 1e00, ebb00000), \ | |
10112 | X(_subi, 8000, f1a00000), \ | |
10113 | X(_subis, 8000, f1b00000), \ | |
10114 | X(_sxtb, b240, fa4ff080), \ | |
10115 | X(_sxth, b200, fa0ff080), \ | |
10116 | X(_tst, 4200, ea100f00), \ | |
10117 | X(_uxtb, b2c0, fa5ff080), \ | |
10118 | X(_uxth, b280, fa1ff080), \ | |
10119 | X(_nop, bf00, f3af8000), \ | |
10120 | X(_yield, bf10, f3af8001), \ | |
10121 | X(_wfe, bf20, f3af8002), \ | |
10122 | X(_wfi, bf30, f3af8003), \ | |
53c4b28b | 10123 | X(_sev, bf40, f3af8004), \ |
74db7efb NC |
10124 | X(_sevl, bf50, f3af8005), \ |
10125 | X(_udf, de00, f7f0a000) | |
c19d1205 ZW |
10126 | |
10127 | /* To catch errors in encoding functions, the codes are all offset by | |
10128 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
10129 | as 16-bit instructions. */ | |
21d799b5 | 10130 | #define X(a,b,c) T_MNEM##a |
c19d1205 ZW |
10131 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; |
10132 | #undef X | |
10133 | ||
10134 | #define X(a,b,c) 0x##b | |
10135 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
10136 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
10137 | #undef X | |
10138 | ||
10139 | #define X(a,b,c) 0x##c | |
10140 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
c921be7d NC |
10141 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) |
10142 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
c19d1205 ZW |
10143 | #undef X |
10144 | #undef T16_32_TAB | |
10145 | ||
10146 | /* Thumb instruction encoders, in alphabetical order. */ | |
10147 | ||
92e90b6e | 10148 | /* ADDW or SUBW. */ |
c921be7d | 10149 | |
92e90b6e PB |
10150 | static void |
10151 | do_t_add_sub_w (void) | |
10152 | { | |
10153 | int Rd, Rn; | |
10154 | ||
10155 | Rd = inst.operands[0].reg; | |
10156 | Rn = inst.operands[1].reg; | |
10157 | ||
539d4391 NC |
10158 | /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this |
10159 | is the SP-{plus,minus}-immediate form of the instruction. */ | |
10160 | if (Rn == REG_SP) | |
10161 | constraint (Rd == REG_PC, BAD_PC); | |
10162 | else | |
10163 | reject_bad_reg (Rd); | |
fdfde340 | 10164 | |
92e90b6e PB |
10165 | inst.instruction |= (Rn << 16) | (Rd << 8); |
10166 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
10167 | } | |
10168 | ||
c19d1205 ZW |
10169 | /* Parse an add or subtract instruction. We get here with inst.instruction |
10170 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
10171 | ||
10172 | static void | |
10173 | do_t_add_sub (void) | |
10174 | { | |
10175 | int Rd, Rs, Rn; | |
10176 | ||
10177 | Rd = inst.operands[0].reg; | |
10178 | Rs = (inst.operands[1].present | |
10179 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
10180 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
10181 | ||
e07e6e58 NC |
10182 | if (Rd == REG_PC) |
10183 | set_it_insn_type_last (); | |
10184 | ||
c19d1205 ZW |
10185 | if (unified_syntax) |
10186 | { | |
0110f2b8 PB |
10187 | bfd_boolean flags; |
10188 | bfd_boolean narrow; | |
10189 | int opcode; | |
10190 | ||
10191 | flags = (inst.instruction == T_MNEM_adds | |
10192 | || inst.instruction == T_MNEM_subs); | |
10193 | if (flags) | |
e07e6e58 | 10194 | narrow = !in_it_block (); |
0110f2b8 | 10195 | else |
e07e6e58 | 10196 | narrow = in_it_block (); |
c19d1205 | 10197 | if (!inst.operands[2].isreg) |
b99bd4ef | 10198 | { |
16805f35 PB |
10199 | int add; |
10200 | ||
fdfde340 JM |
10201 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); |
10202 | ||
16805f35 PB |
10203 | add = (inst.instruction == T_MNEM_add |
10204 | || inst.instruction == T_MNEM_adds); | |
0110f2b8 PB |
10205 | opcode = 0; |
10206 | if (inst.size_req != 4) | |
10207 | { | |
0110f2b8 | 10208 | /* Attempt to use a narrow opcode, with relaxation if |
477330fc | 10209 | appropriate. */ |
0110f2b8 PB |
10210 | if (Rd == REG_SP && Rs == REG_SP && !flags) |
10211 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
10212 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
10213 | opcode = T_MNEM_add_sp; | |
10214 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
10215 | opcode = T_MNEM_add_pc; | |
10216 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
10217 | { | |
10218 | if (flags) | |
10219 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
10220 | else | |
10221 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
10222 | } | |
10223 | if (opcode) | |
10224 | { | |
10225 | inst.instruction = THUMB_OP16(opcode); | |
10226 | inst.instruction |= (Rd << 4) | Rs; | |
10227 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
10228 | if (inst.size_req != 2) | |
10229 | inst.relax = opcode; | |
10230 | } | |
10231 | else | |
10232 | constraint (inst.size_req == 2, BAD_HIREG); | |
10233 | } | |
10234 | if (inst.size_req == 4 | |
10235 | || (inst.size_req != 2 && !opcode)) | |
10236 | { | |
efd81785 PB |
10237 | if (Rd == REG_PC) |
10238 | { | |
fdfde340 | 10239 | constraint (add, BAD_PC); |
efd81785 PB |
10240 | constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, |
10241 | _("only SUBS PC, LR, #const allowed")); | |
10242 | constraint (inst.reloc.exp.X_op != O_constant, | |
10243 | _("expression too complex")); | |
10244 | constraint (inst.reloc.exp.X_add_number < 0 | |
10245 | || inst.reloc.exp.X_add_number > 0xff, | |
10246 | _("immediate value out of range")); | |
10247 | inst.instruction = T2_SUBS_PC_LR | |
10248 | | inst.reloc.exp.X_add_number; | |
10249 | inst.reloc.type = BFD_RELOC_UNUSED; | |
10250 | return; | |
10251 | } | |
10252 | else if (Rs == REG_PC) | |
16805f35 PB |
10253 | { |
10254 | /* Always use addw/subw. */ | |
10255 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; | |
10256 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
10257 | } | |
10258 | else | |
10259 | { | |
10260 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10261 | inst.instruction = (inst.instruction & 0xe1ffffff) | |
10262 | | 0x10000000; | |
10263 | if (flags) | |
10264 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10265 | else | |
10266 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; | |
10267 | } | |
dc4503c6 PB |
10268 | inst.instruction |= Rd << 8; |
10269 | inst.instruction |= Rs << 16; | |
0110f2b8 | 10270 | } |
b99bd4ef | 10271 | } |
c19d1205 ZW |
10272 | else |
10273 | { | |
5f4cb198 NC |
10274 | unsigned int value = inst.reloc.exp.X_add_number; |
10275 | unsigned int shift = inst.operands[2].shift_kind; | |
10276 | ||
c19d1205 ZW |
10277 | Rn = inst.operands[2].reg; |
10278 | /* See if we can do this with a 16-bit instruction. */ | |
10279 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
10280 | { | |
e27ec89e PB |
10281 | if (Rd > 7 || Rs > 7 || Rn > 7) |
10282 | narrow = FALSE; | |
10283 | ||
10284 | if (narrow) | |
c19d1205 | 10285 | { |
e27ec89e PB |
10286 | inst.instruction = ((inst.instruction == T_MNEM_adds |
10287 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
10288 | ? T_OPCODE_ADD_R3 |
10289 | : T_OPCODE_SUB_R3); | |
10290 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
10291 | return; | |
10292 | } | |
b99bd4ef | 10293 | |
7e806470 | 10294 | if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) |
c19d1205 | 10295 | { |
7e806470 PB |
10296 | /* Thumb-1 cores (except v6-M) require at least one high |
10297 | register in a narrow non flag setting add. */ | |
10298 | if (Rd > 7 || Rn > 7 | |
10299 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) | |
10300 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) | |
c19d1205 | 10301 | { |
7e806470 PB |
10302 | if (Rd == Rn) |
10303 | { | |
10304 | Rn = Rs; | |
10305 | Rs = Rd; | |
10306 | } | |
c19d1205 ZW |
10307 | inst.instruction = T_OPCODE_ADD_HI; |
10308 | inst.instruction |= (Rd & 8) << 4; | |
10309 | inst.instruction |= (Rd & 7); | |
10310 | inst.instruction |= Rn << 3; | |
10311 | return; | |
10312 | } | |
c19d1205 ZW |
10313 | } |
10314 | } | |
c921be7d | 10315 | |
fdfde340 JM |
10316 | constraint (Rd == REG_PC, BAD_PC); |
10317 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
10318 | constraint (Rs == REG_PC, BAD_PC); | |
10319 | reject_bad_reg (Rn); | |
10320 | ||
c19d1205 ZW |
10321 | /* If we get here, it can't be done in 16 bits. */ |
10322 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
10323 | _("shift must be constant")); | |
10324 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10325 | inst.instruction |= Rd << 8; | |
10326 | inst.instruction |= Rs << 16; | |
5f4cb198 NC |
10327 | constraint (Rd == REG_SP && Rs == REG_SP && value > 3, |
10328 | _("shift value over 3 not allowed in thumb mode")); | |
10329 | constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL, | |
10330 | _("only LSL shift allowed in thumb mode")); | |
c19d1205 ZW |
10331 | encode_thumb32_shifted_operand (2); |
10332 | } | |
10333 | } | |
10334 | else | |
10335 | { | |
10336 | constraint (inst.instruction == T_MNEM_adds | |
10337 | || inst.instruction == T_MNEM_subs, | |
10338 | BAD_THUMB32); | |
b99bd4ef | 10339 | |
c19d1205 | 10340 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 10341 | { |
c19d1205 ZW |
10342 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
10343 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
10344 | BAD_HIREG); | |
10345 | ||
10346 | inst.instruction = (inst.instruction == T_MNEM_add | |
10347 | ? 0x0000 : 0x8000); | |
10348 | inst.instruction |= (Rd << 4) | Rs; | |
10349 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
10350 | return; |
10351 | } | |
10352 | ||
c19d1205 ZW |
10353 | Rn = inst.operands[2].reg; |
10354 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 10355 | |
c19d1205 ZW |
10356 | /* We now have Rd, Rs, and Rn set to registers. */ |
10357 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 10358 | { |
c19d1205 ZW |
10359 | /* Can't do this for SUB. */ |
10360 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
10361 | inst.instruction = T_OPCODE_ADD_HI; | |
10362 | inst.instruction |= (Rd & 8) << 4; | |
10363 | inst.instruction |= (Rd & 7); | |
10364 | if (Rs == Rd) | |
10365 | inst.instruction |= Rn << 3; | |
10366 | else if (Rn == Rd) | |
10367 | inst.instruction |= Rs << 3; | |
10368 | else | |
10369 | constraint (1, _("dest must overlap one source register")); | |
10370 | } | |
10371 | else | |
10372 | { | |
10373 | inst.instruction = (inst.instruction == T_MNEM_add | |
10374 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
10375 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 10376 | } |
b99bd4ef | 10377 | } |
b99bd4ef NC |
10378 | } |
10379 | ||
c19d1205 ZW |
10380 | static void |
10381 | do_t_adr (void) | |
10382 | { | |
fdfde340 JM |
10383 | unsigned Rd; |
10384 | ||
10385 | Rd = inst.operands[0].reg; | |
10386 | reject_bad_reg (Rd); | |
10387 | ||
10388 | if (unified_syntax && inst.size_req == 0 && Rd <= 7) | |
0110f2b8 PB |
10389 | { |
10390 | /* Defer to section relaxation. */ | |
10391 | inst.relax = inst.instruction; | |
10392 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 | 10393 | inst.instruction |= Rd << 4; |
0110f2b8 PB |
10394 | } |
10395 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 10396 | { |
0110f2b8 | 10397 | /* Generate a 32-bit opcode. */ |
e9f89963 | 10398 | inst.instruction = THUMB_OP32 (inst.instruction); |
fdfde340 | 10399 | inst.instruction |= Rd << 8; |
e9f89963 PB |
10400 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; |
10401 | inst.reloc.pc_rel = 1; | |
10402 | } | |
10403 | else | |
10404 | { | |
0110f2b8 | 10405 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
10406 | inst.instruction = THUMB_OP16 (inst.instruction); |
10407 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
10408 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
10409 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 10410 | |
fdfde340 | 10411 | inst.instruction |= Rd << 4; |
e9f89963 | 10412 | } |
c19d1205 | 10413 | } |
b99bd4ef | 10414 | |
c19d1205 ZW |
10415 | /* Arithmetic instructions for which there is just one 16-bit |
10416 | instruction encoding, and it allows only two low registers. | |
10417 | For maximal compatibility with ARM syntax, we allow three register | |
10418 | operands even when Thumb-32 instructions are not available, as long | |
10419 | as the first two are identical. For instance, both "sbc r0,r1" and | |
10420 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 10421 | static void |
c19d1205 | 10422 | do_t_arit3 (void) |
b99bd4ef | 10423 | { |
c19d1205 | 10424 | int Rd, Rs, Rn; |
b99bd4ef | 10425 | |
c19d1205 ZW |
10426 | Rd = inst.operands[0].reg; |
10427 | Rs = (inst.operands[1].present | |
10428 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
10429 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
10430 | Rn = inst.operands[2].reg; | |
b99bd4ef | 10431 | |
fdfde340 JM |
10432 | reject_bad_reg (Rd); |
10433 | reject_bad_reg (Rs); | |
10434 | if (inst.operands[2].isreg) | |
10435 | reject_bad_reg (Rn); | |
10436 | ||
c19d1205 | 10437 | if (unified_syntax) |
b99bd4ef | 10438 | { |
c19d1205 ZW |
10439 | if (!inst.operands[2].isreg) |
10440 | { | |
10441 | /* For an immediate, we always generate a 32-bit opcode; | |
10442 | section relaxation will shrink it later if possible. */ | |
10443 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10444 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
10445 | inst.instruction |= Rd << 8; | |
10446 | inst.instruction |= Rs << 16; | |
10447 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10448 | } | |
10449 | else | |
10450 | { | |
e27ec89e PB |
10451 | bfd_boolean narrow; |
10452 | ||
c19d1205 | 10453 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 10454 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 10455 | narrow = !in_it_block (); |
e27ec89e | 10456 | else |
e07e6e58 | 10457 | narrow = in_it_block (); |
e27ec89e PB |
10458 | |
10459 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
10460 | narrow = FALSE; | |
10461 | if (inst.operands[2].shifted) | |
10462 | narrow = FALSE; | |
10463 | if (inst.size_req == 4) | |
10464 | narrow = FALSE; | |
10465 | ||
10466 | if (narrow | |
c19d1205 ZW |
10467 | && Rd == Rs) |
10468 | { | |
10469 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10470 | inst.instruction |= Rd; | |
10471 | inst.instruction |= Rn << 3; | |
10472 | return; | |
10473 | } | |
b99bd4ef | 10474 | |
c19d1205 ZW |
10475 | /* If we get here, it can't be done in 16 bits. */ |
10476 | constraint (inst.operands[2].shifted | |
10477 | && inst.operands[2].immisreg, | |
10478 | _("shift must be constant")); | |
10479 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10480 | inst.instruction |= Rd << 8; | |
10481 | inst.instruction |= Rs << 16; | |
10482 | encode_thumb32_shifted_operand (2); | |
10483 | } | |
a737bd4d | 10484 | } |
c19d1205 | 10485 | else |
b99bd4ef | 10486 | { |
c19d1205 ZW |
10487 | /* On its face this is a lie - the instruction does set the |
10488 | flags. However, the only supported mnemonic in this mode | |
10489 | says it doesn't. */ | |
10490 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 10491 | |
c19d1205 ZW |
10492 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
10493 | _("unshifted register required")); | |
10494 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
10495 | constraint (Rd != Rs, | |
10496 | _("dest and source1 must be the same register")); | |
a737bd4d | 10497 | |
c19d1205 ZW |
10498 | inst.instruction = THUMB_OP16 (inst.instruction); |
10499 | inst.instruction |= Rd; | |
10500 | inst.instruction |= Rn << 3; | |
b99bd4ef | 10501 | } |
a737bd4d | 10502 | } |
b99bd4ef | 10503 | |
c19d1205 ZW |
10504 | /* Similarly, but for instructions where the arithmetic operation is |
10505 | commutative, so we can allow either of them to be different from | |
10506 | the destination operand in a 16-bit instruction. For instance, all | |
10507 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
10508 | accepted. */ | |
10509 | static void | |
10510 | do_t_arit3c (void) | |
a737bd4d | 10511 | { |
c19d1205 | 10512 | int Rd, Rs, Rn; |
b99bd4ef | 10513 | |
c19d1205 ZW |
10514 | Rd = inst.operands[0].reg; |
10515 | Rs = (inst.operands[1].present | |
10516 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
10517 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
10518 | Rn = inst.operands[2].reg; | |
c921be7d | 10519 | |
fdfde340 JM |
10520 | reject_bad_reg (Rd); |
10521 | reject_bad_reg (Rs); | |
10522 | if (inst.operands[2].isreg) | |
10523 | reject_bad_reg (Rn); | |
a737bd4d | 10524 | |
c19d1205 | 10525 | if (unified_syntax) |
a737bd4d | 10526 | { |
c19d1205 | 10527 | if (!inst.operands[2].isreg) |
b99bd4ef | 10528 | { |
c19d1205 ZW |
10529 | /* For an immediate, we always generate a 32-bit opcode; |
10530 | section relaxation will shrink it later if possible. */ | |
10531 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10532 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
10533 | inst.instruction |= Rd << 8; | |
10534 | inst.instruction |= Rs << 16; | |
10535 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 10536 | } |
c19d1205 | 10537 | else |
a737bd4d | 10538 | { |
e27ec89e PB |
10539 | bfd_boolean narrow; |
10540 | ||
c19d1205 | 10541 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 10542 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 10543 | narrow = !in_it_block (); |
e27ec89e | 10544 | else |
e07e6e58 | 10545 | narrow = in_it_block (); |
e27ec89e PB |
10546 | |
10547 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
10548 | narrow = FALSE; | |
10549 | if (inst.operands[2].shifted) | |
10550 | narrow = FALSE; | |
10551 | if (inst.size_req == 4) | |
10552 | narrow = FALSE; | |
10553 | ||
10554 | if (narrow) | |
a737bd4d | 10555 | { |
c19d1205 | 10556 | if (Rd == Rs) |
a737bd4d | 10557 | { |
c19d1205 ZW |
10558 | inst.instruction = THUMB_OP16 (inst.instruction); |
10559 | inst.instruction |= Rd; | |
10560 | inst.instruction |= Rn << 3; | |
10561 | return; | |
a737bd4d | 10562 | } |
c19d1205 | 10563 | if (Rd == Rn) |
a737bd4d | 10564 | { |
c19d1205 ZW |
10565 | inst.instruction = THUMB_OP16 (inst.instruction); |
10566 | inst.instruction |= Rd; | |
10567 | inst.instruction |= Rs << 3; | |
10568 | return; | |
a737bd4d NC |
10569 | } |
10570 | } | |
c19d1205 ZW |
10571 | |
10572 | /* If we get here, it can't be done in 16 bits. */ | |
10573 | constraint (inst.operands[2].shifted | |
10574 | && inst.operands[2].immisreg, | |
10575 | _("shift must be constant")); | |
10576 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10577 | inst.instruction |= Rd << 8; | |
10578 | inst.instruction |= Rs << 16; | |
10579 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 10580 | } |
b99bd4ef | 10581 | } |
c19d1205 ZW |
10582 | else |
10583 | { | |
10584 | /* On its face this is a lie - the instruction does set the | |
10585 | flags. However, the only supported mnemonic in this mode | |
10586 | says it doesn't. */ | |
10587 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 10588 | |
c19d1205 ZW |
10589 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
10590 | _("unshifted register required")); | |
10591 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
10592 | ||
10593 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10594 | inst.instruction |= Rd; | |
10595 | ||
10596 | if (Rd == Rs) | |
10597 | inst.instruction |= Rn << 3; | |
10598 | else if (Rd == Rn) | |
10599 | inst.instruction |= Rs << 3; | |
10600 | else | |
10601 | constraint (1, _("dest must overlap one source register")); | |
10602 | } | |
a737bd4d NC |
10603 | } |
10604 | ||
c19d1205 ZW |
10605 | static void |
10606 | do_t_bfc (void) | |
a737bd4d | 10607 | { |
fdfde340 | 10608 | unsigned Rd; |
c19d1205 ZW |
10609 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
10610 | constraint (msb > 32, _("bit-field extends past end of register")); | |
10611 | /* The instruction encoding stores the LSB and MSB, | |
10612 | not the LSB and width. */ | |
fdfde340 JM |
10613 | Rd = inst.operands[0].reg; |
10614 | reject_bad_reg (Rd); | |
10615 | inst.instruction |= Rd << 8; | |
c19d1205 ZW |
10616 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; |
10617 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
10618 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
10619 | } |
10620 | ||
c19d1205 ZW |
10621 | static void |
10622 | do_t_bfi (void) | |
b99bd4ef | 10623 | { |
fdfde340 | 10624 | int Rd, Rn; |
c19d1205 | 10625 | unsigned int msb; |
b99bd4ef | 10626 | |
fdfde340 JM |
10627 | Rd = inst.operands[0].reg; |
10628 | reject_bad_reg (Rd); | |
10629 | ||
c19d1205 ZW |
10630 | /* #0 in second position is alternative syntax for bfc, which is |
10631 | the same instruction but with REG_PC in the Rm field. */ | |
10632 | if (!inst.operands[1].isreg) | |
fdfde340 JM |
10633 | Rn = REG_PC; |
10634 | else | |
10635 | { | |
10636 | Rn = inst.operands[1].reg; | |
10637 | reject_bad_reg (Rn); | |
10638 | } | |
b99bd4ef | 10639 | |
c19d1205 ZW |
10640 | msb = inst.operands[2].imm + inst.operands[3].imm; |
10641 | constraint (msb > 32, _("bit-field extends past end of register")); | |
10642 | /* The instruction encoding stores the LSB and MSB, | |
10643 | not the LSB and width. */ | |
fdfde340 JM |
10644 | inst.instruction |= Rd << 8; |
10645 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
10646 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
10647 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
10648 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
10649 | } |
10650 | ||
c19d1205 ZW |
10651 | static void |
10652 | do_t_bfx (void) | |
b99bd4ef | 10653 | { |
fdfde340 JM |
10654 | unsigned Rd, Rn; |
10655 | ||
10656 | Rd = inst.operands[0].reg; | |
10657 | Rn = inst.operands[1].reg; | |
10658 | ||
10659 | reject_bad_reg (Rd); | |
10660 | reject_bad_reg (Rn); | |
10661 | ||
c19d1205 ZW |
10662 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
10663 | _("bit-field extends past end of register")); | |
fdfde340 JM |
10664 | inst.instruction |= Rd << 8; |
10665 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
10666 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
10667 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
10668 | inst.instruction |= inst.operands[3].imm - 1; | |
10669 | } | |
b99bd4ef | 10670 | |
c19d1205 ZW |
10671 | /* ARM V5 Thumb BLX (argument parse) |
10672 | BLX <target_addr> which is BLX(1) | |
10673 | BLX <Rm> which is BLX(2) | |
10674 | Unfortunately, there are two different opcodes for this mnemonic. | |
10675 | So, the insns[].value is not used, and the code here zaps values | |
10676 | into inst.instruction. | |
b99bd4ef | 10677 | |
c19d1205 ZW |
10678 | ??? How to take advantage of the additional two bits of displacement |
10679 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 10680 | |
c19d1205 ZW |
10681 | static void |
10682 | do_t_blx (void) | |
10683 | { | |
e07e6e58 NC |
10684 | set_it_insn_type_last (); |
10685 | ||
c19d1205 | 10686 | if (inst.operands[0].isreg) |
fdfde340 JM |
10687 | { |
10688 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); | |
10689 | /* We have a register, so this is BLX(2). */ | |
10690 | inst.instruction |= inst.operands[0].reg << 3; | |
10691 | } | |
b99bd4ef NC |
10692 | else |
10693 | { | |
c19d1205 | 10694 | /* No register. This must be BLX(1). */ |
2fc8bdac | 10695 | inst.instruction = 0xf000e800; |
0855e32b | 10696 | encode_branch (BFD_RELOC_THUMB_PCREL_BLX); |
b99bd4ef NC |
10697 | } |
10698 | } | |
10699 | ||
c19d1205 ZW |
10700 | static void |
10701 | do_t_branch (void) | |
b99bd4ef | 10702 | { |
0110f2b8 | 10703 | int opcode; |
dfa9f0d5 | 10704 | int cond; |
9ae92b05 | 10705 | int reloc; |
dfa9f0d5 | 10706 | |
e07e6e58 NC |
10707 | cond = inst.cond; |
10708 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); | |
10709 | ||
10710 | if (in_it_block ()) | |
dfa9f0d5 PB |
10711 | { |
10712 | /* Conditional branches inside IT blocks are encoded as unconditional | |
477330fc | 10713 | branches. */ |
dfa9f0d5 | 10714 | cond = COND_ALWAYS; |
dfa9f0d5 PB |
10715 | } |
10716 | else | |
10717 | cond = inst.cond; | |
10718 | ||
10719 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
10720 | opcode = T_MNEM_bcond; |
10721 | else | |
10722 | opcode = inst.instruction; | |
10723 | ||
12d6b0b7 RS |
10724 | if (unified_syntax |
10725 | && (inst.size_req == 4 | |
10960bfb PB |
10726 | || (inst.size_req != 2 |
10727 | && (inst.operands[0].hasreloc | |
10728 | || inst.reloc.exp.X_op == O_constant)))) | |
c19d1205 | 10729 | { |
0110f2b8 | 10730 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 10731 | if (cond == COND_ALWAYS) |
9ae92b05 | 10732 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
10733 | else |
10734 | { | |
9c2799c2 | 10735 | gas_assert (cond != 0xF); |
dfa9f0d5 | 10736 | inst.instruction |= cond << 22; |
9ae92b05 | 10737 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH20; |
c19d1205 ZW |
10738 | } |
10739 | } | |
b99bd4ef NC |
10740 | else |
10741 | { | |
0110f2b8 | 10742 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 10743 | if (cond == COND_ALWAYS) |
9ae92b05 | 10744 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH12; |
c19d1205 | 10745 | else |
b99bd4ef | 10746 | { |
dfa9f0d5 | 10747 | inst.instruction |= cond << 8; |
9ae92b05 | 10748 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 10749 | } |
0110f2b8 PB |
10750 | /* Allow section relaxation. */ |
10751 | if (unified_syntax && inst.size_req != 2) | |
10752 | inst.relax = opcode; | |
b99bd4ef | 10753 | } |
9ae92b05 | 10754 | inst.reloc.type = reloc; |
c19d1205 | 10755 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
10756 | } |
10757 | ||
8884b720 | 10758 | /* Actually do the work for Thumb state bkpt and hlt. The only difference |
bacebabc | 10759 | between the two is the maximum immediate allowed - which is passed in |
8884b720 | 10760 | RANGE. */ |
b99bd4ef | 10761 | static void |
8884b720 | 10762 | do_t_bkpt_hlt1 (int range) |
b99bd4ef | 10763 | { |
dfa9f0d5 PB |
10764 | constraint (inst.cond != COND_ALWAYS, |
10765 | _("instruction is always unconditional")); | |
c19d1205 | 10766 | if (inst.operands[0].present) |
b99bd4ef | 10767 | { |
8884b720 | 10768 | constraint (inst.operands[0].imm > range, |
c19d1205 ZW |
10769 | _("immediate value out of range")); |
10770 | inst.instruction |= inst.operands[0].imm; | |
b99bd4ef | 10771 | } |
8884b720 MGD |
10772 | |
10773 | set_it_insn_type (NEUTRAL_IT_INSN); | |
10774 | } | |
10775 | ||
10776 | static void | |
10777 | do_t_hlt (void) | |
10778 | { | |
10779 | do_t_bkpt_hlt1 (63); | |
10780 | } | |
10781 | ||
10782 | static void | |
10783 | do_t_bkpt (void) | |
10784 | { | |
10785 | do_t_bkpt_hlt1 (255); | |
b99bd4ef NC |
10786 | } |
10787 | ||
10788 | static void | |
c19d1205 | 10789 | do_t_branch23 (void) |
b99bd4ef | 10790 | { |
e07e6e58 | 10791 | set_it_insn_type_last (); |
0855e32b | 10792 | encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23); |
fa94de6b | 10793 | |
0855e32b NS |
10794 | /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in |
10795 | this file. We used to simply ignore the PLT reloc type here -- | |
10796 | the branch encoding is now needed to deal with TLSCALL relocs. | |
10797 | So if we see a PLT reloc now, put it back to how it used to be to | |
10798 | keep the preexisting behaviour. */ | |
10799 | if (inst.reloc.type == BFD_RELOC_ARM_PLT32) | |
10800 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
90e4755a | 10801 | |
4343666d | 10802 | #if defined(OBJ_COFF) |
c19d1205 ZW |
10803 | /* If the destination of the branch is a defined symbol which does not have |
10804 | the THUMB_FUNC attribute, then we must be calling a function which has | |
10805 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
10806 | function and change the branch to refer to that function instead. */ | |
10807 | if ( inst.reloc.exp.X_op == O_symbol | |
10808 | && inst.reloc.exp.X_add_symbol != NULL | |
10809 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
10810 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
10811 | inst.reloc.exp.X_add_symbol = | |
10812 | find_real_start (inst.reloc.exp.X_add_symbol); | |
4343666d | 10813 | #endif |
90e4755a RE |
10814 | } |
10815 | ||
10816 | static void | |
c19d1205 | 10817 | do_t_bx (void) |
90e4755a | 10818 | { |
e07e6e58 | 10819 | set_it_insn_type_last (); |
c19d1205 ZW |
10820 | inst.instruction |= inst.operands[0].reg << 3; |
10821 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
10822 | should cause the alignment to be checked once it is known. This is | |
10823 | because BX PC only works if the instruction is word aligned. */ | |
10824 | } | |
90e4755a | 10825 | |
c19d1205 ZW |
10826 | static void |
10827 | do_t_bxj (void) | |
10828 | { | |
fdfde340 | 10829 | int Rm; |
90e4755a | 10830 | |
e07e6e58 | 10831 | set_it_insn_type_last (); |
fdfde340 JM |
10832 | Rm = inst.operands[0].reg; |
10833 | reject_bad_reg (Rm); | |
10834 | inst.instruction |= Rm << 16; | |
90e4755a RE |
10835 | } |
10836 | ||
10837 | static void | |
c19d1205 | 10838 | do_t_clz (void) |
90e4755a | 10839 | { |
fdfde340 JM |
10840 | unsigned Rd; |
10841 | unsigned Rm; | |
10842 | ||
10843 | Rd = inst.operands[0].reg; | |
10844 | Rm = inst.operands[1].reg; | |
10845 | ||
10846 | reject_bad_reg (Rd); | |
10847 | reject_bad_reg (Rm); | |
10848 | ||
10849 | inst.instruction |= Rd << 8; | |
10850 | inst.instruction |= Rm << 16; | |
10851 | inst.instruction |= Rm; | |
c19d1205 | 10852 | } |
90e4755a | 10853 | |
dfa9f0d5 PB |
10854 | static void |
10855 | do_t_cps (void) | |
10856 | { | |
e07e6e58 | 10857 | set_it_insn_type (OUTSIDE_IT_INSN); |
dfa9f0d5 PB |
10858 | inst.instruction |= inst.operands[0].imm; |
10859 | } | |
10860 | ||
c19d1205 ZW |
10861 | static void |
10862 | do_t_cpsi (void) | |
10863 | { | |
e07e6e58 | 10864 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 | 10865 | if (unified_syntax |
62b3e311 PB |
10866 | && (inst.operands[1].present || inst.size_req == 4) |
10867 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 10868 | { |
c19d1205 ZW |
10869 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
10870 | inst.instruction = 0xf3af8000; | |
10871 | inst.instruction |= imod << 9; | |
10872 | inst.instruction |= inst.operands[0].imm << 5; | |
10873 | if (inst.operands[1].present) | |
10874 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 10875 | } |
c19d1205 | 10876 | else |
90e4755a | 10877 | { |
62b3e311 PB |
10878 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
10879 | && (inst.operands[0].imm & 4), | |
10880 | _("selected processor does not support 'A' form " | |
10881 | "of this instruction")); | |
10882 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
10883 | _("Thumb does not support the 2-argument " |
10884 | "form of this instruction")); | |
10885 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 10886 | } |
90e4755a RE |
10887 | } |
10888 | ||
c19d1205 ZW |
10889 | /* THUMB CPY instruction (argument parse). */ |
10890 | ||
90e4755a | 10891 | static void |
c19d1205 | 10892 | do_t_cpy (void) |
90e4755a | 10893 | { |
c19d1205 | 10894 | if (inst.size_req == 4) |
90e4755a | 10895 | { |
c19d1205 ZW |
10896 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
10897 | inst.instruction |= inst.operands[0].reg << 8; | |
10898 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 10899 | } |
c19d1205 | 10900 | else |
90e4755a | 10901 | { |
c19d1205 ZW |
10902 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
10903 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
10904 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 10905 | } |
90e4755a RE |
10906 | } |
10907 | ||
90e4755a | 10908 | static void |
25fe350b | 10909 | do_t_cbz (void) |
90e4755a | 10910 | { |
e07e6e58 | 10911 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
10912 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
10913 | inst.instruction |= inst.operands[0].reg; | |
10914 | inst.reloc.pc_rel = 1; | |
10915 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
10916 | } | |
90e4755a | 10917 | |
62b3e311 PB |
10918 | static void |
10919 | do_t_dbg (void) | |
10920 | { | |
10921 | inst.instruction |= inst.operands[0].imm; | |
10922 | } | |
10923 | ||
10924 | static void | |
10925 | do_t_div (void) | |
10926 | { | |
fdfde340 JM |
10927 | unsigned Rd, Rn, Rm; |
10928 | ||
10929 | Rd = inst.operands[0].reg; | |
10930 | Rn = (inst.operands[1].present | |
10931 | ? inst.operands[1].reg : Rd); | |
10932 | Rm = inst.operands[2].reg; | |
10933 | ||
10934 | reject_bad_reg (Rd); | |
10935 | reject_bad_reg (Rn); | |
10936 | reject_bad_reg (Rm); | |
10937 | ||
10938 | inst.instruction |= Rd << 8; | |
10939 | inst.instruction |= Rn << 16; | |
10940 | inst.instruction |= Rm; | |
62b3e311 PB |
10941 | } |
10942 | ||
c19d1205 ZW |
10943 | static void |
10944 | do_t_hint (void) | |
10945 | { | |
10946 | if (unified_syntax && inst.size_req == 4) | |
10947 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10948 | else | |
10949 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10950 | } | |
90e4755a | 10951 | |
c19d1205 ZW |
10952 | static void |
10953 | do_t_it (void) | |
10954 | { | |
10955 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 10956 | |
e07e6e58 NC |
10957 | set_it_insn_type (IT_INSN); |
10958 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
10959 | now_it.cc = cond; | |
5a01bb1d | 10960 | now_it.warn_deprecated = FALSE; |
e27ec89e PB |
10961 | |
10962 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 10963 | if ((cond & 0x1) == 0x0) |
90e4755a | 10964 | { |
c19d1205 | 10965 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 10966 | |
c19d1205 | 10967 | if ((mask & 0x7) == 0) |
5a01bb1d MGD |
10968 | { |
10969 | /* No conversion needed. */ | |
10970 | now_it.block_length = 1; | |
10971 | } | |
c19d1205 | 10972 | else if ((mask & 0x3) == 0) |
5a01bb1d MGD |
10973 | { |
10974 | mask ^= 0x8; | |
10975 | now_it.block_length = 2; | |
10976 | } | |
e27ec89e | 10977 | else if ((mask & 0x1) == 0) |
5a01bb1d MGD |
10978 | { |
10979 | mask ^= 0xC; | |
10980 | now_it.block_length = 3; | |
10981 | } | |
c19d1205 | 10982 | else |
5a01bb1d MGD |
10983 | { |
10984 | mask ^= 0xE; | |
10985 | now_it.block_length = 4; | |
10986 | } | |
90e4755a | 10987 | |
e27ec89e PB |
10988 | inst.instruction &= 0xfff0; |
10989 | inst.instruction |= mask; | |
c19d1205 | 10990 | } |
90e4755a | 10991 | |
c19d1205 ZW |
10992 | inst.instruction |= cond << 4; |
10993 | } | |
90e4755a | 10994 | |
3c707909 PB |
10995 | /* Helper function used for both push/pop and ldm/stm. */ |
10996 | static void | |
10997 | encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) | |
10998 | { | |
10999 | bfd_boolean load; | |
11000 | ||
11001 | load = (inst.instruction & (1 << 20)) != 0; | |
11002 | ||
11003 | if (mask & (1 << 13)) | |
11004 | inst.error = _("SP not allowed in register list"); | |
1e5b0379 NC |
11005 | |
11006 | if ((mask & (1 << base)) != 0 | |
11007 | && writeback) | |
11008 | inst.error = _("having the base register in the register list when " | |
11009 | "using write back is UNPREDICTABLE"); | |
11010 | ||
3c707909 PB |
11011 | if (load) |
11012 | { | |
e07e6e58 | 11013 | if (mask & (1 << 15)) |
477330fc RM |
11014 | { |
11015 | if (mask & (1 << 14)) | |
11016 | inst.error = _("LR and PC should not both be in register list"); | |
11017 | else | |
11018 | set_it_insn_type_last (); | |
11019 | } | |
3c707909 PB |
11020 | } |
11021 | else | |
11022 | { | |
11023 | if (mask & (1 << 15)) | |
11024 | inst.error = _("PC not allowed in register list"); | |
3c707909 PB |
11025 | } |
11026 | ||
11027 | if ((mask & (mask - 1)) == 0) | |
11028 | { | |
11029 | /* Single register transfers implemented as str/ldr. */ | |
11030 | if (writeback) | |
11031 | { | |
11032 | if (inst.instruction & (1 << 23)) | |
11033 | inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ | |
11034 | else | |
11035 | inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ | |
11036 | } | |
11037 | else | |
11038 | { | |
11039 | if (inst.instruction & (1 << 23)) | |
11040 | inst.instruction = 0x00800000; /* ia -> [base] */ | |
11041 | else | |
11042 | inst.instruction = 0x00000c04; /* db -> [base, #-4] */ | |
11043 | } | |
11044 | ||
11045 | inst.instruction |= 0xf8400000; | |
11046 | if (load) | |
11047 | inst.instruction |= 0x00100000; | |
11048 | ||
5f4273c7 | 11049 | mask = ffs (mask) - 1; |
3c707909 PB |
11050 | mask <<= 12; |
11051 | } | |
11052 | else if (writeback) | |
11053 | inst.instruction |= WRITE_BACK; | |
11054 | ||
11055 | inst.instruction |= mask; | |
11056 | inst.instruction |= base << 16; | |
11057 | } | |
11058 | ||
c19d1205 ZW |
11059 | static void |
11060 | do_t_ldmstm (void) | |
11061 | { | |
11062 | /* This really doesn't seem worth it. */ | |
11063 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
11064 | _("expression too complex")); | |
11065 | constraint (inst.operands[1].writeback, | |
11066 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 11067 | |
c19d1205 ZW |
11068 | if (unified_syntax) |
11069 | { | |
3c707909 PB |
11070 | bfd_boolean narrow; |
11071 | unsigned mask; | |
11072 | ||
11073 | narrow = FALSE; | |
c19d1205 ZW |
11074 | /* See if we can use a 16-bit instruction. */ |
11075 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
11076 | && inst.size_req != 4 | |
3c707909 | 11077 | && !(inst.operands[1].imm & ~0xff)) |
90e4755a | 11078 | { |
3c707909 | 11079 | mask = 1 << inst.operands[0].reg; |
90e4755a | 11080 | |
eab4f823 | 11081 | if (inst.operands[0].reg <= 7) |
90e4755a | 11082 | { |
3c707909 | 11083 | if (inst.instruction == T_MNEM_stmia |
eab4f823 MGD |
11084 | ? inst.operands[0].writeback |
11085 | : (inst.operands[0].writeback | |
11086 | == !(inst.operands[1].imm & mask))) | |
477330fc | 11087 | { |
eab4f823 MGD |
11088 | if (inst.instruction == T_MNEM_stmia |
11089 | && (inst.operands[1].imm & mask) | |
11090 | && (inst.operands[1].imm & (mask - 1))) | |
11091 | as_warn (_("value stored for r%d is UNKNOWN"), | |
11092 | inst.operands[0].reg); | |
3c707909 | 11093 | |
eab4f823 MGD |
11094 | inst.instruction = THUMB_OP16 (inst.instruction); |
11095 | inst.instruction |= inst.operands[0].reg << 8; | |
11096 | inst.instruction |= inst.operands[1].imm; | |
11097 | narrow = TRUE; | |
11098 | } | |
11099 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
11100 | { | |
11101 | /* This means 1 register in reg list one of 3 situations: | |
11102 | 1. Instruction is stmia, but without writeback. | |
11103 | 2. lmdia without writeback, but with Rn not in | |
477330fc | 11104 | reglist. |
eab4f823 MGD |
11105 | 3. ldmia with writeback, but with Rn in reglist. |
11106 | Case 3 is UNPREDICTABLE behaviour, so we handle | |
11107 | case 1 and 2 which can be converted into a 16-bit | |
11108 | str or ldr. The SP cases are handled below. */ | |
11109 | unsigned long opcode; | |
11110 | /* First, record an error for Case 3. */ | |
11111 | if (inst.operands[1].imm & mask | |
11112 | && inst.operands[0].writeback) | |
fa94de6b | 11113 | inst.error = |
eab4f823 MGD |
11114 | _("having the base register in the register list when " |
11115 | "using write back is UNPREDICTABLE"); | |
fa94de6b RM |
11116 | |
11117 | opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str | |
eab4f823 MGD |
11118 | : T_MNEM_ldr); |
11119 | inst.instruction = THUMB_OP16 (opcode); | |
11120 | inst.instruction |= inst.operands[0].reg << 3; | |
11121 | inst.instruction |= (ffs (inst.operands[1].imm)-1); | |
11122 | narrow = TRUE; | |
11123 | } | |
90e4755a | 11124 | } |
eab4f823 | 11125 | else if (inst.operands[0] .reg == REG_SP) |
90e4755a | 11126 | { |
eab4f823 MGD |
11127 | if (inst.operands[0].writeback) |
11128 | { | |
fa94de6b | 11129 | inst.instruction = |
eab4f823 | 11130 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
477330fc | 11131 | ? T_MNEM_push : T_MNEM_pop); |
eab4f823 | 11132 | inst.instruction |= inst.operands[1].imm; |
477330fc | 11133 | narrow = TRUE; |
eab4f823 MGD |
11134 | } |
11135 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
11136 | { | |
fa94de6b | 11137 | inst.instruction = |
eab4f823 | 11138 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
477330fc | 11139 | ? T_MNEM_str_sp : T_MNEM_ldr_sp); |
eab4f823 | 11140 | inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8); |
477330fc | 11141 | narrow = TRUE; |
eab4f823 | 11142 | } |
90e4755a | 11143 | } |
3c707909 PB |
11144 | } |
11145 | ||
11146 | if (!narrow) | |
11147 | { | |
c19d1205 ZW |
11148 | if (inst.instruction < 0xffff) |
11149 | inst.instruction = THUMB_OP32 (inst.instruction); | |
3c707909 | 11150 | |
5f4273c7 NC |
11151 | encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm, |
11152 | inst.operands[0].writeback); | |
90e4755a RE |
11153 | } |
11154 | } | |
c19d1205 | 11155 | else |
90e4755a | 11156 | { |
c19d1205 ZW |
11157 | constraint (inst.operands[0].reg > 7 |
11158 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
1198ca51 PB |
11159 | constraint (inst.instruction != T_MNEM_ldmia |
11160 | && inst.instruction != T_MNEM_stmia, | |
11161 | _("Thumb-2 instruction only valid in unified syntax")); | |
c19d1205 | 11162 | if (inst.instruction == T_MNEM_stmia) |
f03698e6 | 11163 | { |
c19d1205 ZW |
11164 | if (!inst.operands[0].writeback) |
11165 | as_warn (_("this instruction will write back the base register")); | |
11166 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
11167 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
1e5b0379 | 11168 | as_warn (_("value stored for r%d is UNKNOWN"), |
c19d1205 | 11169 | inst.operands[0].reg); |
f03698e6 | 11170 | } |
c19d1205 | 11171 | else |
90e4755a | 11172 | { |
c19d1205 ZW |
11173 | if (!inst.operands[0].writeback |
11174 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
11175 | as_warn (_("this instruction will write back the base register")); | |
11176 | else if (inst.operands[0].writeback | |
11177 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
11178 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
11179 | } |
11180 | ||
c19d1205 ZW |
11181 | inst.instruction = THUMB_OP16 (inst.instruction); |
11182 | inst.instruction |= inst.operands[0].reg << 8; | |
11183 | inst.instruction |= inst.operands[1].imm; | |
11184 | } | |
11185 | } | |
e28cd48c | 11186 | |
c19d1205 ZW |
11187 | static void |
11188 | do_t_ldrex (void) | |
11189 | { | |
11190 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
11191 | || inst.operands[1].postind || inst.operands[1].writeback | |
11192 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
11193 | || inst.operands[1].negative, | |
01cfc07f | 11194 | BAD_ADDR_MODE); |
e28cd48c | 11195 | |
5be8be5d DG |
11196 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
11197 | ||
c19d1205 ZW |
11198 | inst.instruction |= inst.operands[0].reg << 12; |
11199 | inst.instruction |= inst.operands[1].reg << 16; | |
11200 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
11201 | } | |
e28cd48c | 11202 | |
c19d1205 ZW |
11203 | static void |
11204 | do_t_ldrexd (void) | |
11205 | { | |
11206 | if (!inst.operands[1].present) | |
1cac9012 | 11207 | { |
c19d1205 ZW |
11208 | constraint (inst.operands[0].reg == REG_LR, |
11209 | _("r14 not allowed as first register " | |
11210 | "when second register is omitted")); | |
11211 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 11212 | } |
c19d1205 ZW |
11213 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
11214 | BAD_OVERLAP); | |
b99bd4ef | 11215 | |
c19d1205 ZW |
11216 | inst.instruction |= inst.operands[0].reg << 12; |
11217 | inst.instruction |= inst.operands[1].reg << 8; | |
11218 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
11219 | } |
11220 | ||
11221 | static void | |
c19d1205 | 11222 | do_t_ldst (void) |
b99bd4ef | 11223 | { |
0110f2b8 PB |
11224 | unsigned long opcode; |
11225 | int Rn; | |
11226 | ||
e07e6e58 NC |
11227 | if (inst.operands[0].isreg |
11228 | && !inst.operands[0].preind | |
11229 | && inst.operands[0].reg == REG_PC) | |
11230 | set_it_insn_type_last (); | |
11231 | ||
0110f2b8 | 11232 | opcode = inst.instruction; |
c19d1205 | 11233 | if (unified_syntax) |
b99bd4ef | 11234 | { |
53365c0d PB |
11235 | if (!inst.operands[1].isreg) |
11236 | { | |
11237 | if (opcode <= 0xffff) | |
11238 | inst.instruction = THUMB_OP32 (opcode); | |
8335d6aa | 11239 | if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) |
53365c0d PB |
11240 | return; |
11241 | } | |
0110f2b8 PB |
11242 | if (inst.operands[1].isreg |
11243 | && !inst.operands[1].writeback | |
c19d1205 ZW |
11244 | && !inst.operands[1].shifted && !inst.operands[1].postind |
11245 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
11246 | && opcode <= 0xffff |
11247 | && inst.size_req != 4) | |
c19d1205 | 11248 | { |
0110f2b8 PB |
11249 | /* Insn may have a 16-bit form. */ |
11250 | Rn = inst.operands[1].reg; | |
11251 | if (inst.operands[1].immisreg) | |
11252 | { | |
11253 | inst.instruction = THUMB_OP16 (opcode); | |
5f4273c7 | 11254 | /* [Rn, Rik] */ |
0110f2b8 PB |
11255 | if (Rn <= 7 && inst.operands[1].imm <= 7) |
11256 | goto op16; | |
5be8be5d DG |
11257 | else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str) |
11258 | reject_bad_reg (inst.operands[1].imm); | |
0110f2b8 PB |
11259 | } |
11260 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
11261 | && opcode != T_MNEM_ldrsb) | |
11262 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
11263 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
11264 | { | |
11265 | /* [Rn, #const] */ | |
11266 | if (Rn > 7) | |
11267 | { | |
11268 | if (Rn == REG_PC) | |
11269 | { | |
11270 | if (inst.reloc.pc_rel) | |
11271 | opcode = T_MNEM_ldr_pc2; | |
11272 | else | |
11273 | opcode = T_MNEM_ldr_pc; | |
11274 | } | |
11275 | else | |
11276 | { | |
11277 | if (opcode == T_MNEM_ldr) | |
11278 | opcode = T_MNEM_ldr_sp; | |
11279 | else | |
11280 | opcode = T_MNEM_str_sp; | |
11281 | } | |
11282 | inst.instruction = inst.operands[0].reg << 8; | |
11283 | } | |
11284 | else | |
11285 | { | |
11286 | inst.instruction = inst.operands[0].reg; | |
11287 | inst.instruction |= inst.operands[1].reg << 3; | |
11288 | } | |
11289 | inst.instruction |= THUMB_OP16 (opcode); | |
11290 | if (inst.size_req == 2) | |
11291 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
11292 | else | |
11293 | inst.relax = opcode; | |
11294 | return; | |
11295 | } | |
c19d1205 | 11296 | } |
0110f2b8 | 11297 | /* Definitely a 32-bit variant. */ |
5be8be5d | 11298 | |
8d67f500 NC |
11299 | /* Warning for Erratum 752419. */ |
11300 | if (opcode == T_MNEM_ldr | |
11301 | && inst.operands[0].reg == REG_SP | |
11302 | && inst.operands[1].writeback == 1 | |
11303 | && !inst.operands[1].immisreg) | |
11304 | { | |
11305 | if (no_cpu_selected () | |
11306 | || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7) | |
477330fc RM |
11307 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a) |
11308 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r))) | |
8d67f500 NC |
11309 | as_warn (_("This instruction may be unpredictable " |
11310 | "if executed on M-profile cores " | |
11311 | "with interrupts enabled.")); | |
11312 | } | |
11313 | ||
5be8be5d | 11314 | /* Do some validations regarding addressing modes. */ |
1be5fd2e | 11315 | if (inst.operands[1].immisreg) |
5be8be5d DG |
11316 | reject_bad_reg (inst.operands[1].imm); |
11317 | ||
1be5fd2e NC |
11318 | constraint (inst.operands[1].writeback == 1 |
11319 | && inst.operands[0].reg == inst.operands[1].reg, | |
11320 | BAD_OVERLAP); | |
11321 | ||
0110f2b8 | 11322 | inst.instruction = THUMB_OP32 (opcode); |
c19d1205 ZW |
11323 | inst.instruction |= inst.operands[0].reg << 12; |
11324 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
1be5fd2e | 11325 | check_ldr_r15_aligned (); |
b99bd4ef NC |
11326 | return; |
11327 | } | |
11328 | ||
c19d1205 ZW |
11329 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
11330 | ||
11331 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 11332 | { |
c19d1205 ZW |
11333 | /* Only [Rn,Rm] is acceptable. */ |
11334 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
11335 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
11336 | || inst.operands[1].postind || inst.operands[1].shifted | |
11337 | || inst.operands[1].negative, | |
11338 | _("Thumb does not support this addressing mode")); | |
11339 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11340 | goto op16; | |
b99bd4ef | 11341 | } |
5f4273c7 | 11342 | |
c19d1205 ZW |
11343 | inst.instruction = THUMB_OP16 (inst.instruction); |
11344 | if (!inst.operands[1].isreg) | |
8335d6aa | 11345 | if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) |
c19d1205 | 11346 | return; |
b99bd4ef | 11347 | |
c19d1205 ZW |
11348 | constraint (!inst.operands[1].preind |
11349 | || inst.operands[1].shifted | |
11350 | || inst.operands[1].writeback, | |
11351 | _("Thumb does not support this addressing mode")); | |
11352 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 11353 | { |
c19d1205 ZW |
11354 | constraint (inst.instruction & 0x0600, |
11355 | _("byte or halfword not valid for base register")); | |
11356 | constraint (inst.operands[1].reg == REG_PC | |
11357 | && !(inst.instruction & THUMB_LOAD_BIT), | |
11358 | _("r15 based store not allowed")); | |
11359 | constraint (inst.operands[1].immisreg, | |
11360 | _("invalid base register for register offset")); | |
b99bd4ef | 11361 | |
c19d1205 ZW |
11362 | if (inst.operands[1].reg == REG_PC) |
11363 | inst.instruction = T_OPCODE_LDR_PC; | |
11364 | else if (inst.instruction & THUMB_LOAD_BIT) | |
11365 | inst.instruction = T_OPCODE_LDR_SP; | |
11366 | else | |
11367 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 11368 | |
c19d1205 ZW |
11369 | inst.instruction |= inst.operands[0].reg << 8; |
11370 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
11371 | return; | |
11372 | } | |
90e4755a | 11373 | |
c19d1205 ZW |
11374 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
11375 | if (!inst.operands[1].immisreg) | |
11376 | { | |
11377 | /* Immediate offset. */ | |
11378 | inst.instruction |= inst.operands[0].reg; | |
11379 | inst.instruction |= inst.operands[1].reg << 3; | |
11380 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
11381 | return; | |
11382 | } | |
90e4755a | 11383 | |
c19d1205 ZW |
11384 | /* Register offset. */ |
11385 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
11386 | constraint (inst.operands[1].negative, | |
11387 | _("Thumb does not support this addressing mode")); | |
90e4755a | 11388 | |
c19d1205 ZW |
11389 | op16: |
11390 | switch (inst.instruction) | |
11391 | { | |
11392 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
11393 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
11394 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
11395 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
11396 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
11397 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
11398 | case 0x5600 /* ldrsb */: | |
11399 | case 0x5e00 /* ldrsh */: break; | |
11400 | default: abort (); | |
11401 | } | |
90e4755a | 11402 | |
c19d1205 ZW |
11403 | inst.instruction |= inst.operands[0].reg; |
11404 | inst.instruction |= inst.operands[1].reg << 3; | |
11405 | inst.instruction |= inst.operands[1].imm << 6; | |
11406 | } | |
90e4755a | 11407 | |
c19d1205 ZW |
11408 | static void |
11409 | do_t_ldstd (void) | |
11410 | { | |
11411 | if (!inst.operands[1].present) | |
b99bd4ef | 11412 | { |
c19d1205 ZW |
11413 | inst.operands[1].reg = inst.operands[0].reg + 1; |
11414 | constraint (inst.operands[0].reg == REG_LR, | |
11415 | _("r14 not allowed here")); | |
bd340a04 | 11416 | constraint (inst.operands[0].reg == REG_R12, |
477330fc | 11417 | _("r12 not allowed here")); |
b99bd4ef | 11418 | } |
bd340a04 MGD |
11419 | |
11420 | if (inst.operands[2].writeback | |
11421 | && (inst.operands[0].reg == inst.operands[2].reg | |
11422 | || inst.operands[1].reg == inst.operands[2].reg)) | |
11423 | as_warn (_("base register written back, and overlaps " | |
477330fc | 11424 | "one of transfer registers")); |
bd340a04 | 11425 | |
c19d1205 ZW |
11426 | inst.instruction |= inst.operands[0].reg << 12; |
11427 | inst.instruction |= inst.operands[1].reg << 8; | |
11428 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
b99bd4ef NC |
11429 | } |
11430 | ||
c19d1205 ZW |
11431 | static void |
11432 | do_t_ldstt (void) | |
11433 | { | |
11434 | inst.instruction |= inst.operands[0].reg << 12; | |
11435 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
11436 | } | |
a737bd4d | 11437 | |
b99bd4ef | 11438 | static void |
c19d1205 | 11439 | do_t_mla (void) |
b99bd4ef | 11440 | { |
fdfde340 | 11441 | unsigned Rd, Rn, Rm, Ra; |
c921be7d | 11442 | |
fdfde340 JM |
11443 | Rd = inst.operands[0].reg; |
11444 | Rn = inst.operands[1].reg; | |
11445 | Rm = inst.operands[2].reg; | |
11446 | Ra = inst.operands[3].reg; | |
11447 | ||
11448 | reject_bad_reg (Rd); | |
11449 | reject_bad_reg (Rn); | |
11450 | reject_bad_reg (Rm); | |
11451 | reject_bad_reg (Ra); | |
11452 | ||
11453 | inst.instruction |= Rd << 8; | |
11454 | inst.instruction |= Rn << 16; | |
11455 | inst.instruction |= Rm; | |
11456 | inst.instruction |= Ra << 12; | |
c19d1205 | 11457 | } |
b99bd4ef | 11458 | |
c19d1205 ZW |
11459 | static void |
11460 | do_t_mlal (void) | |
11461 | { | |
fdfde340 JM |
11462 | unsigned RdLo, RdHi, Rn, Rm; |
11463 | ||
11464 | RdLo = inst.operands[0].reg; | |
11465 | RdHi = inst.operands[1].reg; | |
11466 | Rn = inst.operands[2].reg; | |
11467 | Rm = inst.operands[3].reg; | |
11468 | ||
11469 | reject_bad_reg (RdLo); | |
11470 | reject_bad_reg (RdHi); | |
11471 | reject_bad_reg (Rn); | |
11472 | reject_bad_reg (Rm); | |
11473 | ||
11474 | inst.instruction |= RdLo << 12; | |
11475 | inst.instruction |= RdHi << 8; | |
11476 | inst.instruction |= Rn << 16; | |
11477 | inst.instruction |= Rm; | |
c19d1205 | 11478 | } |
b99bd4ef | 11479 | |
c19d1205 ZW |
11480 | static void |
11481 | do_t_mov_cmp (void) | |
11482 | { | |
fdfde340 JM |
11483 | unsigned Rn, Rm; |
11484 | ||
11485 | Rn = inst.operands[0].reg; | |
11486 | Rm = inst.operands[1].reg; | |
11487 | ||
e07e6e58 NC |
11488 | if (Rn == REG_PC) |
11489 | set_it_insn_type_last (); | |
11490 | ||
c19d1205 | 11491 | if (unified_syntax) |
b99bd4ef | 11492 | { |
c19d1205 ZW |
11493 | int r0off = (inst.instruction == T_MNEM_mov |
11494 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 11495 | unsigned long opcode; |
3d388997 PB |
11496 | bfd_boolean narrow; |
11497 | bfd_boolean low_regs; | |
11498 | ||
fdfde340 | 11499 | low_regs = (Rn <= 7 && Rm <= 7); |
0110f2b8 | 11500 | opcode = inst.instruction; |
e07e6e58 | 11501 | if (in_it_block ()) |
0110f2b8 | 11502 | narrow = opcode != T_MNEM_movs; |
3d388997 | 11503 | else |
0110f2b8 | 11504 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
11505 | if (inst.size_req == 4 |
11506 | || inst.operands[1].shifted) | |
11507 | narrow = FALSE; | |
11508 | ||
efd81785 PB |
11509 | /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ |
11510 | if (opcode == T_MNEM_movs && inst.operands[1].isreg | |
11511 | && !inst.operands[1].shifted | |
fdfde340 JM |
11512 | && Rn == REG_PC |
11513 | && Rm == REG_LR) | |
efd81785 PB |
11514 | { |
11515 | inst.instruction = T2_SUBS_PC_LR; | |
11516 | return; | |
11517 | } | |
11518 | ||
fdfde340 JM |
11519 | if (opcode == T_MNEM_cmp) |
11520 | { | |
11521 | constraint (Rn == REG_PC, BAD_PC); | |
94206790 MM |
11522 | if (narrow) |
11523 | { | |
11524 | /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, | |
11525 | but valid. */ | |
11526 | warn_deprecated_sp (Rm); | |
11527 | /* R15 was documented as a valid choice for Rm in ARMv6, | |
11528 | but as UNPREDICTABLE in ARMv7. ARM's proprietary | |
11529 | tools reject R15, so we do too. */ | |
11530 | constraint (Rm == REG_PC, BAD_PC); | |
11531 | } | |
11532 | else | |
11533 | reject_bad_reg (Rm); | |
fdfde340 JM |
11534 | } |
11535 | else if (opcode == T_MNEM_mov | |
11536 | || opcode == T_MNEM_movs) | |
11537 | { | |
11538 | if (inst.operands[1].isreg) | |
11539 | { | |
11540 | if (opcode == T_MNEM_movs) | |
11541 | { | |
11542 | reject_bad_reg (Rn); | |
11543 | reject_bad_reg (Rm); | |
11544 | } | |
76fa04a4 MGD |
11545 | else if (narrow) |
11546 | { | |
11547 | /* This is mov.n. */ | |
11548 | if ((Rn == REG_SP || Rn == REG_PC) | |
11549 | && (Rm == REG_SP || Rm == REG_PC)) | |
11550 | { | |
11551 | as_warn (_("Use of r%u as a source register is " | |
11552 | "deprecated when r%u is the destination " | |
11553 | "register."), Rm, Rn); | |
11554 | } | |
11555 | } | |
11556 | else | |
11557 | { | |
11558 | /* This is mov.w. */ | |
11559 | constraint (Rn == REG_PC, BAD_PC); | |
11560 | constraint (Rm == REG_PC, BAD_PC); | |
11561 | constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); | |
11562 | } | |
fdfde340 JM |
11563 | } |
11564 | else | |
11565 | reject_bad_reg (Rn); | |
11566 | } | |
11567 | ||
c19d1205 ZW |
11568 | if (!inst.operands[1].isreg) |
11569 | { | |
0110f2b8 | 11570 | /* Immediate operand. */ |
e07e6e58 | 11571 | if (!in_it_block () && opcode == T_MNEM_mov) |
0110f2b8 PB |
11572 | narrow = 0; |
11573 | if (low_regs && narrow) | |
11574 | { | |
11575 | inst.instruction = THUMB_OP16 (opcode); | |
fdfde340 | 11576 | inst.instruction |= Rn << 8; |
0110f2b8 PB |
11577 | if (inst.size_req == 2) |
11578 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
11579 | else | |
11580 | inst.relax = opcode; | |
11581 | } | |
11582 | else | |
11583 | { | |
11584 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11585 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 11586 | inst.instruction |= Rn << r0off; |
0110f2b8 PB |
11587 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
11588 | } | |
c19d1205 | 11589 | } |
728ca7c9 PB |
11590 | else if (inst.operands[1].shifted && inst.operands[1].immisreg |
11591 | && (inst.instruction == T_MNEM_mov | |
11592 | || inst.instruction == T_MNEM_movs)) | |
11593 | { | |
11594 | /* Register shifts are encoded as separate shift instructions. */ | |
11595 | bfd_boolean flags = (inst.instruction == T_MNEM_movs); | |
11596 | ||
e07e6e58 | 11597 | if (in_it_block ()) |
728ca7c9 PB |
11598 | narrow = !flags; |
11599 | else | |
11600 | narrow = flags; | |
11601 | ||
11602 | if (inst.size_req == 4) | |
11603 | narrow = FALSE; | |
11604 | ||
11605 | if (!low_regs || inst.operands[1].imm > 7) | |
11606 | narrow = FALSE; | |
11607 | ||
fdfde340 | 11608 | if (Rn != Rm) |
728ca7c9 PB |
11609 | narrow = FALSE; |
11610 | ||
11611 | switch (inst.operands[1].shift_kind) | |
11612 | { | |
11613 | case SHIFT_LSL: | |
11614 | opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); | |
11615 | break; | |
11616 | case SHIFT_ASR: | |
11617 | opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); | |
11618 | break; | |
11619 | case SHIFT_LSR: | |
11620 | opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); | |
11621 | break; | |
11622 | case SHIFT_ROR: | |
11623 | opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); | |
11624 | break; | |
11625 | default: | |
5f4273c7 | 11626 | abort (); |
728ca7c9 PB |
11627 | } |
11628 | ||
11629 | inst.instruction = opcode; | |
11630 | if (narrow) | |
11631 | { | |
fdfde340 | 11632 | inst.instruction |= Rn; |
728ca7c9 PB |
11633 | inst.instruction |= inst.operands[1].imm << 3; |
11634 | } | |
11635 | else | |
11636 | { | |
11637 | if (flags) | |
11638 | inst.instruction |= CONDS_BIT; | |
11639 | ||
fdfde340 JM |
11640 | inst.instruction |= Rn << 8; |
11641 | inst.instruction |= Rm << 16; | |
728ca7c9 PB |
11642 | inst.instruction |= inst.operands[1].imm; |
11643 | } | |
11644 | } | |
3d388997 | 11645 | else if (!narrow) |
c19d1205 | 11646 | { |
728ca7c9 PB |
11647 | /* Some mov with immediate shift have narrow variants. |
11648 | Register shifts are handled above. */ | |
11649 | if (low_regs && inst.operands[1].shifted | |
11650 | && (inst.instruction == T_MNEM_mov | |
11651 | || inst.instruction == T_MNEM_movs)) | |
11652 | { | |
e07e6e58 | 11653 | if (in_it_block ()) |
728ca7c9 PB |
11654 | narrow = (inst.instruction == T_MNEM_mov); |
11655 | else | |
11656 | narrow = (inst.instruction == T_MNEM_movs); | |
11657 | } | |
11658 | ||
11659 | if (narrow) | |
11660 | { | |
11661 | switch (inst.operands[1].shift_kind) | |
11662 | { | |
11663 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
11664 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
11665 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
11666 | default: narrow = FALSE; break; | |
11667 | } | |
11668 | } | |
11669 | ||
11670 | if (narrow) | |
11671 | { | |
fdfde340 JM |
11672 | inst.instruction |= Rn; |
11673 | inst.instruction |= Rm << 3; | |
728ca7c9 PB |
11674 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
11675 | } | |
11676 | else | |
11677 | { | |
11678 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 11679 | inst.instruction |= Rn << r0off; |
728ca7c9 PB |
11680 | encode_thumb32_shifted_operand (1); |
11681 | } | |
c19d1205 ZW |
11682 | } |
11683 | else | |
11684 | switch (inst.instruction) | |
11685 | { | |
11686 | case T_MNEM_mov: | |
837b3435 | 11687 | /* In v4t or v5t a move of two lowregs produces unpredictable |
c6400f8a MGD |
11688 | results. Don't allow this. */ |
11689 | if (low_regs) | |
11690 | { | |
11691 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6), | |
11692 | "MOV Rd, Rs with two low registers is not " | |
11693 | "permitted on this architecture"); | |
fa94de6b | 11694 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
c6400f8a MGD |
11695 | arm_ext_v6); |
11696 | } | |
11697 | ||
c19d1205 | 11698 | inst.instruction = T_OPCODE_MOV_HR; |
fdfde340 JM |
11699 | inst.instruction |= (Rn & 0x8) << 4; |
11700 | inst.instruction |= (Rn & 0x7); | |
11701 | inst.instruction |= Rm << 3; | |
c19d1205 | 11702 | break; |
b99bd4ef | 11703 | |
c19d1205 ZW |
11704 | case T_MNEM_movs: |
11705 | /* We know we have low registers at this point. | |
941a8a52 MGD |
11706 | Generate LSLS Rd, Rs, #0. */ |
11707 | inst.instruction = T_OPCODE_LSL_I; | |
fdfde340 JM |
11708 | inst.instruction |= Rn; |
11709 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11710 | break; |
11711 | ||
11712 | case T_MNEM_cmp: | |
3d388997 | 11713 | if (low_regs) |
c19d1205 ZW |
11714 | { |
11715 | inst.instruction = T_OPCODE_CMP_LR; | |
fdfde340 JM |
11716 | inst.instruction |= Rn; |
11717 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11718 | } |
11719 | else | |
11720 | { | |
11721 | inst.instruction = T_OPCODE_CMP_HR; | |
fdfde340 JM |
11722 | inst.instruction |= (Rn & 0x8) << 4; |
11723 | inst.instruction |= (Rn & 0x7); | |
11724 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11725 | } |
11726 | break; | |
11727 | } | |
b99bd4ef NC |
11728 | return; |
11729 | } | |
11730 | ||
c19d1205 | 11731 | inst.instruction = THUMB_OP16 (inst.instruction); |
539d4391 NC |
11732 | |
11733 | /* PR 10443: Do not silently ignore shifted operands. */ | |
11734 | constraint (inst.operands[1].shifted, | |
11735 | _("shifts in CMP/MOV instructions are only supported in unified syntax")); | |
11736 | ||
c19d1205 | 11737 | if (inst.operands[1].isreg) |
b99bd4ef | 11738 | { |
fdfde340 | 11739 | if (Rn < 8 && Rm < 8) |
b99bd4ef | 11740 | { |
c19d1205 ZW |
11741 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
11742 | since a MOV instruction produces unpredictable results. */ | |
11743 | if (inst.instruction == T_OPCODE_MOV_I8) | |
11744 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 11745 | else |
c19d1205 | 11746 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 11747 | |
fdfde340 JM |
11748 | inst.instruction |= Rn; |
11749 | inst.instruction |= Rm << 3; | |
b99bd4ef NC |
11750 | } |
11751 | else | |
11752 | { | |
c19d1205 ZW |
11753 | if (inst.instruction == T_OPCODE_MOV_I8) |
11754 | inst.instruction = T_OPCODE_MOV_HR; | |
11755 | else | |
11756 | inst.instruction = T_OPCODE_CMP_HR; | |
11757 | do_t_cpy (); | |
b99bd4ef NC |
11758 | } |
11759 | } | |
c19d1205 | 11760 | else |
b99bd4ef | 11761 | { |
fdfde340 | 11762 | constraint (Rn > 7, |
c19d1205 | 11763 | _("only lo regs allowed with immediate")); |
fdfde340 | 11764 | inst.instruction |= Rn << 8; |
c19d1205 ZW |
11765 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; |
11766 | } | |
11767 | } | |
b99bd4ef | 11768 | |
c19d1205 ZW |
11769 | static void |
11770 | do_t_mov16 (void) | |
11771 | { | |
fdfde340 | 11772 | unsigned Rd; |
b6895b4f PB |
11773 | bfd_vma imm; |
11774 | bfd_boolean top; | |
11775 | ||
11776 | top = (inst.instruction & 0x00800000) != 0; | |
11777 | if (inst.reloc.type == BFD_RELOC_ARM_MOVW) | |
11778 | { | |
11779 | constraint (top, _(":lower16: not allowed this instruction")); | |
11780 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; | |
11781 | } | |
11782 | else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) | |
11783 | { | |
11784 | constraint (!top, _(":upper16: not allowed this instruction")); | |
11785 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; | |
11786 | } | |
11787 | ||
fdfde340 JM |
11788 | Rd = inst.operands[0].reg; |
11789 | reject_bad_reg (Rd); | |
11790 | ||
11791 | inst.instruction |= Rd << 8; | |
b6895b4f PB |
11792 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
11793 | { | |
11794 | imm = inst.reloc.exp.X_add_number; | |
11795 | inst.instruction |= (imm & 0xf000) << 4; | |
11796 | inst.instruction |= (imm & 0x0800) << 15; | |
11797 | inst.instruction |= (imm & 0x0700) << 4; | |
11798 | inst.instruction |= (imm & 0x00ff); | |
11799 | } | |
c19d1205 | 11800 | } |
b99bd4ef | 11801 | |
c19d1205 ZW |
11802 | static void |
11803 | do_t_mvn_tst (void) | |
11804 | { | |
fdfde340 | 11805 | unsigned Rn, Rm; |
c921be7d | 11806 | |
fdfde340 JM |
11807 | Rn = inst.operands[0].reg; |
11808 | Rm = inst.operands[1].reg; | |
11809 | ||
11810 | if (inst.instruction == T_MNEM_cmp | |
11811 | || inst.instruction == T_MNEM_cmn) | |
11812 | constraint (Rn == REG_PC, BAD_PC); | |
11813 | else | |
11814 | reject_bad_reg (Rn); | |
11815 | reject_bad_reg (Rm); | |
11816 | ||
c19d1205 ZW |
11817 | if (unified_syntax) |
11818 | { | |
11819 | int r0off = (inst.instruction == T_MNEM_mvn | |
11820 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
11821 | bfd_boolean narrow; |
11822 | ||
11823 | if (inst.size_req == 4 | |
11824 | || inst.instruction > 0xffff | |
11825 | || inst.operands[1].shifted | |
fdfde340 | 11826 | || Rn > 7 || Rm > 7) |
3d388997 | 11827 | narrow = FALSE; |
fe8b4cc3 KT |
11828 | else if (inst.instruction == T_MNEM_cmn |
11829 | || inst.instruction == T_MNEM_tst) | |
3d388997 PB |
11830 | narrow = TRUE; |
11831 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11832 | narrow = !in_it_block (); |
3d388997 | 11833 | else |
e07e6e58 | 11834 | narrow = in_it_block (); |
3d388997 | 11835 | |
c19d1205 | 11836 | if (!inst.operands[1].isreg) |
b99bd4ef | 11837 | { |
c19d1205 ZW |
11838 | /* For an immediate, we always generate a 32-bit opcode; |
11839 | section relaxation will shrink it later if possible. */ | |
11840 | if (inst.instruction < 0xffff) | |
11841 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11842 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 11843 | inst.instruction |= Rn << r0off; |
c19d1205 | 11844 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 11845 | } |
c19d1205 | 11846 | else |
b99bd4ef | 11847 | { |
c19d1205 | 11848 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 11849 | if (narrow) |
b99bd4ef | 11850 | { |
c19d1205 | 11851 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
11852 | inst.instruction |= Rn; |
11853 | inst.instruction |= Rm << 3; | |
b99bd4ef | 11854 | } |
c19d1205 | 11855 | else |
b99bd4ef | 11856 | { |
c19d1205 ZW |
11857 | constraint (inst.operands[1].shifted |
11858 | && inst.operands[1].immisreg, | |
11859 | _("shift must be constant")); | |
11860 | if (inst.instruction < 0xffff) | |
11861 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 11862 | inst.instruction |= Rn << r0off; |
c19d1205 | 11863 | encode_thumb32_shifted_operand (1); |
b99bd4ef | 11864 | } |
b99bd4ef NC |
11865 | } |
11866 | } | |
11867 | else | |
11868 | { | |
c19d1205 ZW |
11869 | constraint (inst.instruction > 0xffff |
11870 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
11871 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
11872 | _("unshifted register required")); | |
fdfde340 | 11873 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 11874 | BAD_HIREG); |
b99bd4ef | 11875 | |
c19d1205 | 11876 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
11877 | inst.instruction |= Rn; |
11878 | inst.instruction |= Rm << 3; | |
b99bd4ef | 11879 | } |
b99bd4ef NC |
11880 | } |
11881 | ||
b05fe5cf | 11882 | static void |
c19d1205 | 11883 | do_t_mrs (void) |
b05fe5cf | 11884 | { |
fdfde340 | 11885 | unsigned Rd; |
037e8744 JB |
11886 | |
11887 | if (do_vfp_nsyn_mrs () == SUCCESS) | |
11888 | return; | |
11889 | ||
90ec0d68 MGD |
11890 | Rd = inst.operands[0].reg; |
11891 | reject_bad_reg (Rd); | |
11892 | inst.instruction |= Rd << 8; | |
11893 | ||
11894 | if (inst.operands[1].isreg) | |
62b3e311 | 11895 | { |
90ec0d68 MGD |
11896 | unsigned br = inst.operands[1].reg; |
11897 | if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000)) | |
11898 | as_bad (_("bad register for mrs")); | |
11899 | ||
11900 | inst.instruction |= br & (0xf << 16); | |
11901 | inst.instruction |= (br & 0x300) >> 4; | |
11902 | inst.instruction |= (br & SPSR_BIT) >> 2; | |
62b3e311 PB |
11903 | } |
11904 | else | |
11905 | { | |
90ec0d68 | 11906 | int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
5f4273c7 | 11907 | |
d2cd1205 | 11908 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
1a43faaf NC |
11909 | { |
11910 | /* PR gas/12698: The constraint is only applied for m_profile. | |
11911 | If the user has specified -march=all, we want to ignore it as | |
11912 | we are building for any CPU type, including non-m variants. */ | |
11913 | bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core; | |
11914 | constraint ((flags != 0) && m_profile, _("selected processor does " | |
11915 | "not support requested special purpose register")); | |
11916 | } | |
90ec0d68 | 11917 | else |
d2cd1205 JB |
11918 | /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile |
11919 | devices). */ | |
11920 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
11921 | _("'APSR', 'CPSR' or 'SPSR' expected")); | |
fdfde340 | 11922 | |
90ec0d68 MGD |
11923 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
11924 | inst.instruction |= inst.operands[1].imm & 0xff; | |
11925 | inst.instruction |= 0xf0000; | |
11926 | } | |
c19d1205 | 11927 | } |
b05fe5cf | 11928 | |
c19d1205 ZW |
11929 | static void |
11930 | do_t_msr (void) | |
11931 | { | |
62b3e311 | 11932 | int flags; |
fdfde340 | 11933 | unsigned Rn; |
62b3e311 | 11934 | |
037e8744 JB |
11935 | if (do_vfp_nsyn_msr () == SUCCESS) |
11936 | return; | |
11937 | ||
c19d1205 ZW |
11938 | constraint (!inst.operands[1].isreg, |
11939 | _("Thumb encoding does not support an immediate here")); | |
90ec0d68 MGD |
11940 | |
11941 | if (inst.operands[0].isreg) | |
11942 | flags = (int)(inst.operands[0].reg); | |
11943 | else | |
11944 | flags = inst.operands[0].imm; | |
11945 | ||
d2cd1205 | 11946 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
62b3e311 | 11947 | { |
d2cd1205 JB |
11948 | int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
11949 | ||
1a43faaf | 11950 | /* PR gas/12698: The constraint is only applied for m_profile. |
477330fc RM |
11951 | If the user has specified -march=all, we want to ignore it as |
11952 | we are building for any CPU type, including non-m variants. */ | |
1a43faaf NC |
11953 | bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core; |
11954 | constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
477330fc RM |
11955 | && (bits & ~(PSR_s | PSR_f)) != 0) |
11956 | || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
11957 | && bits != PSR_f)) && m_profile, | |
11958 | _("selected processor does not support requested special " | |
11959 | "purpose register")); | |
62b3e311 PB |
11960 | } |
11961 | else | |
d2cd1205 JB |
11962 | constraint ((flags & 0xff) != 0, _("selected processor does not support " |
11963 | "requested special purpose register")); | |
c921be7d | 11964 | |
fdfde340 JM |
11965 | Rn = inst.operands[1].reg; |
11966 | reject_bad_reg (Rn); | |
11967 | ||
62b3e311 | 11968 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
90ec0d68 MGD |
11969 | inst.instruction |= (flags & 0xf0000) >> 8; |
11970 | inst.instruction |= (flags & 0x300) >> 4; | |
62b3e311 | 11971 | inst.instruction |= (flags & 0xff); |
fdfde340 | 11972 | inst.instruction |= Rn << 16; |
c19d1205 | 11973 | } |
b05fe5cf | 11974 | |
c19d1205 ZW |
11975 | static void |
11976 | do_t_mul (void) | |
11977 | { | |
17828f45 | 11978 | bfd_boolean narrow; |
fdfde340 | 11979 | unsigned Rd, Rn, Rm; |
17828f45 | 11980 | |
c19d1205 ZW |
11981 | if (!inst.operands[2].present) |
11982 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 11983 | |
fdfde340 JM |
11984 | Rd = inst.operands[0].reg; |
11985 | Rn = inst.operands[1].reg; | |
11986 | Rm = inst.operands[2].reg; | |
11987 | ||
17828f45 | 11988 | if (unified_syntax) |
b05fe5cf | 11989 | { |
17828f45 | 11990 | if (inst.size_req == 4 |
fdfde340 JM |
11991 | || (Rd != Rn |
11992 | && Rd != Rm) | |
11993 | || Rn > 7 | |
11994 | || Rm > 7) | |
17828f45 JM |
11995 | narrow = FALSE; |
11996 | else if (inst.instruction == T_MNEM_muls) | |
e07e6e58 | 11997 | narrow = !in_it_block (); |
17828f45 | 11998 | else |
e07e6e58 | 11999 | narrow = in_it_block (); |
b05fe5cf | 12000 | } |
c19d1205 | 12001 | else |
b05fe5cf | 12002 | { |
17828f45 | 12003 | constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); |
fdfde340 | 12004 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 12005 | BAD_HIREG); |
17828f45 JM |
12006 | narrow = TRUE; |
12007 | } | |
b05fe5cf | 12008 | |
17828f45 JM |
12009 | if (narrow) |
12010 | { | |
12011 | /* 16-bit MULS/Conditional MUL. */ | |
c19d1205 | 12012 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 | 12013 | inst.instruction |= Rd; |
b05fe5cf | 12014 | |
fdfde340 JM |
12015 | if (Rd == Rn) |
12016 | inst.instruction |= Rm << 3; | |
12017 | else if (Rd == Rm) | |
12018 | inst.instruction |= Rn << 3; | |
c19d1205 ZW |
12019 | else |
12020 | constraint (1, _("dest must overlap one source register")); | |
12021 | } | |
17828f45 JM |
12022 | else |
12023 | { | |
e07e6e58 NC |
12024 | constraint (inst.instruction != T_MNEM_mul, |
12025 | _("Thumb-2 MUL must not set flags")); | |
17828f45 JM |
12026 | /* 32-bit MUL. */ |
12027 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
12028 | inst.instruction |= Rd << 8; |
12029 | inst.instruction |= Rn << 16; | |
12030 | inst.instruction |= Rm << 0; | |
12031 | ||
12032 | reject_bad_reg (Rd); | |
12033 | reject_bad_reg (Rn); | |
12034 | reject_bad_reg (Rm); | |
17828f45 | 12035 | } |
c19d1205 | 12036 | } |
b05fe5cf | 12037 | |
c19d1205 ZW |
12038 | static void |
12039 | do_t_mull (void) | |
12040 | { | |
fdfde340 | 12041 | unsigned RdLo, RdHi, Rn, Rm; |
b05fe5cf | 12042 | |
fdfde340 JM |
12043 | RdLo = inst.operands[0].reg; |
12044 | RdHi = inst.operands[1].reg; | |
12045 | Rn = inst.operands[2].reg; | |
12046 | Rm = inst.operands[3].reg; | |
12047 | ||
12048 | reject_bad_reg (RdLo); | |
12049 | reject_bad_reg (RdHi); | |
12050 | reject_bad_reg (Rn); | |
12051 | reject_bad_reg (Rm); | |
12052 | ||
12053 | inst.instruction |= RdLo << 12; | |
12054 | inst.instruction |= RdHi << 8; | |
12055 | inst.instruction |= Rn << 16; | |
12056 | inst.instruction |= Rm; | |
12057 | ||
12058 | if (RdLo == RdHi) | |
c19d1205 ZW |
12059 | as_tsktsk (_("rdhi and rdlo must be different")); |
12060 | } | |
b05fe5cf | 12061 | |
c19d1205 ZW |
12062 | static void |
12063 | do_t_nop (void) | |
12064 | { | |
e07e6e58 NC |
12065 | set_it_insn_type (NEUTRAL_IT_INSN); |
12066 | ||
c19d1205 ZW |
12067 | if (unified_syntax) |
12068 | { | |
12069 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 12070 | { |
c19d1205 ZW |
12071 | inst.instruction = THUMB_OP32 (inst.instruction); |
12072 | inst.instruction |= inst.operands[0].imm; | |
12073 | } | |
12074 | else | |
12075 | { | |
bc2d1808 NC |
12076 | /* PR9722: Check for Thumb2 availability before |
12077 | generating a thumb2 nop instruction. */ | |
afa62d5e | 12078 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
bc2d1808 NC |
12079 | { |
12080 | inst.instruction = THUMB_OP16 (inst.instruction); | |
12081 | inst.instruction |= inst.operands[0].imm << 4; | |
12082 | } | |
12083 | else | |
12084 | inst.instruction = 0x46c0; | |
c19d1205 ZW |
12085 | } |
12086 | } | |
12087 | else | |
12088 | { | |
12089 | constraint (inst.operands[0].present, | |
12090 | _("Thumb does not support NOP with hints")); | |
12091 | inst.instruction = 0x46c0; | |
12092 | } | |
12093 | } | |
b05fe5cf | 12094 | |
c19d1205 ZW |
12095 | static void |
12096 | do_t_neg (void) | |
12097 | { | |
12098 | if (unified_syntax) | |
12099 | { | |
3d388997 PB |
12100 | bfd_boolean narrow; |
12101 | ||
12102 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 12103 | narrow = !in_it_block (); |
3d388997 | 12104 | else |
e07e6e58 | 12105 | narrow = in_it_block (); |
3d388997 PB |
12106 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
12107 | narrow = FALSE; | |
12108 | if (inst.size_req == 4) | |
12109 | narrow = FALSE; | |
12110 | ||
12111 | if (!narrow) | |
c19d1205 ZW |
12112 | { |
12113 | inst.instruction = THUMB_OP32 (inst.instruction); | |
12114 | inst.instruction |= inst.operands[0].reg << 8; | |
12115 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
12116 | } |
12117 | else | |
12118 | { | |
c19d1205 ZW |
12119 | inst.instruction = THUMB_OP16 (inst.instruction); |
12120 | inst.instruction |= inst.operands[0].reg; | |
12121 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
12122 | } |
12123 | } | |
12124 | else | |
12125 | { | |
c19d1205 ZW |
12126 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
12127 | BAD_HIREG); | |
12128 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
12129 | ||
12130 | inst.instruction = THUMB_OP16 (inst.instruction); | |
12131 | inst.instruction |= inst.operands[0].reg; | |
12132 | inst.instruction |= inst.operands[1].reg << 3; | |
12133 | } | |
12134 | } | |
12135 | ||
1c444d06 JM |
12136 | static void |
12137 | do_t_orn (void) | |
12138 | { | |
12139 | unsigned Rd, Rn; | |
12140 | ||
12141 | Rd = inst.operands[0].reg; | |
12142 | Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; | |
12143 | ||
fdfde340 JM |
12144 | reject_bad_reg (Rd); |
12145 | /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ | |
12146 | reject_bad_reg (Rn); | |
12147 | ||
1c444d06 JM |
12148 | inst.instruction |= Rd << 8; |
12149 | inst.instruction |= Rn << 16; | |
12150 | ||
12151 | if (!inst.operands[2].isreg) | |
12152 | { | |
12153 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
12154 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
12155 | } | |
12156 | else | |
12157 | { | |
12158 | unsigned Rm; | |
12159 | ||
12160 | Rm = inst.operands[2].reg; | |
fdfde340 | 12161 | reject_bad_reg (Rm); |
1c444d06 JM |
12162 | |
12163 | constraint (inst.operands[2].shifted | |
12164 | && inst.operands[2].immisreg, | |
12165 | _("shift must be constant")); | |
12166 | encode_thumb32_shifted_operand (2); | |
12167 | } | |
12168 | } | |
12169 | ||
c19d1205 ZW |
12170 | static void |
12171 | do_t_pkhbt (void) | |
12172 | { | |
fdfde340 JM |
12173 | unsigned Rd, Rn, Rm; |
12174 | ||
12175 | Rd = inst.operands[0].reg; | |
12176 | Rn = inst.operands[1].reg; | |
12177 | Rm = inst.operands[2].reg; | |
12178 | ||
12179 | reject_bad_reg (Rd); | |
12180 | reject_bad_reg (Rn); | |
12181 | reject_bad_reg (Rm); | |
12182 | ||
12183 | inst.instruction |= Rd << 8; | |
12184 | inst.instruction |= Rn << 16; | |
12185 | inst.instruction |= Rm; | |
c19d1205 ZW |
12186 | if (inst.operands[3].present) |
12187 | { | |
12188 | unsigned int val = inst.reloc.exp.X_add_number; | |
12189 | constraint (inst.reloc.exp.X_op != O_constant, | |
12190 | _("expression too complex")); | |
12191 | inst.instruction |= (val & 0x1c) << 10; | |
12192 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 12193 | } |
c19d1205 | 12194 | } |
b05fe5cf | 12195 | |
c19d1205 ZW |
12196 | static void |
12197 | do_t_pkhtb (void) | |
12198 | { | |
12199 | if (!inst.operands[3].present) | |
1ef52f49 NC |
12200 | { |
12201 | unsigned Rtmp; | |
12202 | ||
12203 | inst.instruction &= ~0x00000020; | |
12204 | ||
12205 | /* PR 10168. Swap the Rm and Rn registers. */ | |
12206 | Rtmp = inst.operands[1].reg; | |
12207 | inst.operands[1].reg = inst.operands[2].reg; | |
12208 | inst.operands[2].reg = Rtmp; | |
12209 | } | |
c19d1205 | 12210 | do_t_pkhbt (); |
b05fe5cf ZW |
12211 | } |
12212 | ||
c19d1205 ZW |
12213 | static void |
12214 | do_t_pld (void) | |
12215 | { | |
fdfde340 JM |
12216 | if (inst.operands[0].immisreg) |
12217 | reject_bad_reg (inst.operands[0].imm); | |
12218 | ||
c19d1205 ZW |
12219 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); |
12220 | } | |
b05fe5cf | 12221 | |
c19d1205 ZW |
12222 | static void |
12223 | do_t_push_pop (void) | |
b99bd4ef | 12224 | { |
e9f89963 | 12225 | unsigned mask; |
5f4273c7 | 12226 | |
c19d1205 ZW |
12227 | constraint (inst.operands[0].writeback, |
12228 | _("push/pop do not support {reglist}^")); | |
12229 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
12230 | _("expression too complex")); | |
b99bd4ef | 12231 | |
e9f89963 | 12232 | mask = inst.operands[0].imm; |
d3bfe16e | 12233 | if (inst.size_req != 4 && (mask & ~0xff) == 0) |
3c707909 | 12234 | inst.instruction = THUMB_OP16 (inst.instruction) | mask; |
d3bfe16e JB |
12235 | else if (inst.size_req != 4 |
12236 | && (mask & ~0xff) == (1 << (inst.instruction == T_MNEM_push | |
12237 | ? REG_LR : REG_PC))) | |
b99bd4ef | 12238 | { |
c19d1205 ZW |
12239 | inst.instruction = THUMB_OP16 (inst.instruction); |
12240 | inst.instruction |= THUMB_PP_PC_LR; | |
3c707909 | 12241 | inst.instruction |= mask & 0xff; |
c19d1205 ZW |
12242 | } |
12243 | else if (unified_syntax) | |
12244 | { | |
3c707909 | 12245 | inst.instruction = THUMB_OP32 (inst.instruction); |
5f4273c7 | 12246 | encode_thumb2_ldmstm (13, mask, TRUE); |
c19d1205 ZW |
12247 | } |
12248 | else | |
12249 | { | |
12250 | inst.error = _("invalid register list to push/pop instruction"); | |
12251 | return; | |
12252 | } | |
c19d1205 | 12253 | } |
b99bd4ef | 12254 | |
c19d1205 ZW |
12255 | static void |
12256 | do_t_rbit (void) | |
12257 | { | |
fdfde340 JM |
12258 | unsigned Rd, Rm; |
12259 | ||
12260 | Rd = inst.operands[0].reg; | |
12261 | Rm = inst.operands[1].reg; | |
12262 | ||
12263 | reject_bad_reg (Rd); | |
12264 | reject_bad_reg (Rm); | |
12265 | ||
12266 | inst.instruction |= Rd << 8; | |
12267 | inst.instruction |= Rm << 16; | |
12268 | inst.instruction |= Rm; | |
c19d1205 | 12269 | } |
b99bd4ef | 12270 | |
c19d1205 ZW |
12271 | static void |
12272 | do_t_rev (void) | |
12273 | { | |
fdfde340 JM |
12274 | unsigned Rd, Rm; |
12275 | ||
12276 | Rd = inst.operands[0].reg; | |
12277 | Rm = inst.operands[1].reg; | |
12278 | ||
12279 | reject_bad_reg (Rd); | |
12280 | reject_bad_reg (Rm); | |
12281 | ||
12282 | if (Rd <= 7 && Rm <= 7 | |
c19d1205 ZW |
12283 | && inst.size_req != 4) |
12284 | { | |
12285 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 JM |
12286 | inst.instruction |= Rd; |
12287 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
12288 | } |
12289 | else if (unified_syntax) | |
12290 | { | |
12291 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
12292 | inst.instruction |= Rd << 8; |
12293 | inst.instruction |= Rm << 16; | |
12294 | inst.instruction |= Rm; | |
c19d1205 ZW |
12295 | } |
12296 | else | |
12297 | inst.error = BAD_HIREG; | |
12298 | } | |
b99bd4ef | 12299 | |
1c444d06 JM |
12300 | static void |
12301 | do_t_rrx (void) | |
12302 | { | |
12303 | unsigned Rd, Rm; | |
12304 | ||
12305 | Rd = inst.operands[0].reg; | |
12306 | Rm = inst.operands[1].reg; | |
12307 | ||
fdfde340 JM |
12308 | reject_bad_reg (Rd); |
12309 | reject_bad_reg (Rm); | |
c921be7d | 12310 | |
1c444d06 JM |
12311 | inst.instruction |= Rd << 8; |
12312 | inst.instruction |= Rm; | |
12313 | } | |
12314 | ||
c19d1205 ZW |
12315 | static void |
12316 | do_t_rsb (void) | |
12317 | { | |
fdfde340 | 12318 | unsigned Rd, Rs; |
b99bd4ef | 12319 | |
c19d1205 ZW |
12320 | Rd = inst.operands[0].reg; |
12321 | Rs = (inst.operands[1].present | |
12322 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
12323 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 12324 | |
fdfde340 JM |
12325 | reject_bad_reg (Rd); |
12326 | reject_bad_reg (Rs); | |
12327 | if (inst.operands[2].isreg) | |
12328 | reject_bad_reg (inst.operands[2].reg); | |
12329 | ||
c19d1205 ZW |
12330 | inst.instruction |= Rd << 8; |
12331 | inst.instruction |= Rs << 16; | |
12332 | if (!inst.operands[2].isreg) | |
12333 | { | |
026d3abb PB |
12334 | bfd_boolean narrow; |
12335 | ||
12336 | if ((inst.instruction & 0x00100000) != 0) | |
e07e6e58 | 12337 | narrow = !in_it_block (); |
026d3abb | 12338 | else |
e07e6e58 | 12339 | narrow = in_it_block (); |
026d3abb PB |
12340 | |
12341 | if (Rd > 7 || Rs > 7) | |
12342 | narrow = FALSE; | |
12343 | ||
12344 | if (inst.size_req == 4 || !unified_syntax) | |
12345 | narrow = FALSE; | |
12346 | ||
12347 | if (inst.reloc.exp.X_op != O_constant | |
12348 | || inst.reloc.exp.X_add_number != 0) | |
12349 | narrow = FALSE; | |
12350 | ||
12351 | /* Turn rsb #0 into 16-bit neg. We should probably do this via | |
477330fc | 12352 | relaxation, but it doesn't seem worth the hassle. */ |
026d3abb PB |
12353 | if (narrow) |
12354 | { | |
12355 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12356 | inst.instruction = THUMB_OP16 (T_MNEM_negs); | |
12357 | inst.instruction |= Rs << 3; | |
12358 | inst.instruction |= Rd; | |
12359 | } | |
12360 | else | |
12361 | { | |
12362 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
12363 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
12364 | } | |
c19d1205 ZW |
12365 | } |
12366 | else | |
12367 | encode_thumb32_shifted_operand (2); | |
12368 | } | |
b99bd4ef | 12369 | |
c19d1205 ZW |
12370 | static void |
12371 | do_t_setend (void) | |
12372 | { | |
12e37cbc MGD |
12373 | if (warn_on_deprecated |
12374 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
12375 | as_warn (_("setend use is deprecated for ARMv8")); | |
12376 | ||
e07e6e58 | 12377 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
12378 | if (inst.operands[0].imm) |
12379 | inst.instruction |= 0x8; | |
12380 | } | |
b99bd4ef | 12381 | |
c19d1205 ZW |
12382 | static void |
12383 | do_t_shift (void) | |
12384 | { | |
12385 | if (!inst.operands[1].present) | |
12386 | inst.operands[1].reg = inst.operands[0].reg; | |
12387 | ||
12388 | if (unified_syntax) | |
12389 | { | |
3d388997 PB |
12390 | bfd_boolean narrow; |
12391 | int shift_kind; | |
12392 | ||
12393 | switch (inst.instruction) | |
12394 | { | |
12395 | case T_MNEM_asr: | |
12396 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
12397 | case T_MNEM_lsl: | |
12398 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
12399 | case T_MNEM_lsr: | |
12400 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
12401 | case T_MNEM_ror: | |
12402 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
12403 | default: abort (); | |
12404 | } | |
12405 | ||
12406 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 12407 | narrow = !in_it_block (); |
3d388997 | 12408 | else |
e07e6e58 | 12409 | narrow = in_it_block (); |
3d388997 PB |
12410 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
12411 | narrow = FALSE; | |
12412 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
12413 | narrow = FALSE; | |
12414 | if (inst.operands[2].isreg | |
12415 | && (inst.operands[1].reg != inst.operands[0].reg | |
12416 | || inst.operands[2].reg > 7)) | |
12417 | narrow = FALSE; | |
12418 | if (inst.size_req == 4) | |
12419 | narrow = FALSE; | |
12420 | ||
fdfde340 JM |
12421 | reject_bad_reg (inst.operands[0].reg); |
12422 | reject_bad_reg (inst.operands[1].reg); | |
c921be7d | 12423 | |
3d388997 | 12424 | if (!narrow) |
c19d1205 ZW |
12425 | { |
12426 | if (inst.operands[2].isreg) | |
b99bd4ef | 12427 | { |
fdfde340 | 12428 | reject_bad_reg (inst.operands[2].reg); |
c19d1205 ZW |
12429 | inst.instruction = THUMB_OP32 (inst.instruction); |
12430 | inst.instruction |= inst.operands[0].reg << 8; | |
12431 | inst.instruction |= inst.operands[1].reg << 16; | |
12432 | inst.instruction |= inst.operands[2].reg; | |
94342ec3 NC |
12433 | |
12434 | /* PR 12854: Error on extraneous shifts. */ | |
12435 | constraint (inst.operands[2].shifted, | |
12436 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
12437 | } |
12438 | else | |
12439 | { | |
12440 | inst.operands[1].shifted = 1; | |
3d388997 | 12441 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
12442 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
12443 | ? T_MNEM_movs : T_MNEM_mov); | |
12444 | inst.instruction |= inst.operands[0].reg << 8; | |
12445 | encode_thumb32_shifted_operand (1); | |
12446 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
12447 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
12448 | } |
12449 | } | |
12450 | else | |
12451 | { | |
c19d1205 | 12452 | if (inst.operands[2].isreg) |
b99bd4ef | 12453 | { |
3d388997 | 12454 | switch (shift_kind) |
b99bd4ef | 12455 | { |
3d388997 PB |
12456 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
12457 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
12458 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
12459 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 12460 | default: abort (); |
b99bd4ef | 12461 | } |
5f4273c7 | 12462 | |
c19d1205 ZW |
12463 | inst.instruction |= inst.operands[0].reg; |
12464 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
12465 | |
12466 | /* PR 12854: Error on extraneous shifts. */ | |
12467 | constraint (inst.operands[2].shifted, | |
12468 | _("extraneous shift as part of operand to shift insn")); | |
b99bd4ef NC |
12469 | } |
12470 | else | |
12471 | { | |
3d388997 | 12472 | switch (shift_kind) |
b99bd4ef | 12473 | { |
3d388997 PB |
12474 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
12475 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
12476 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 12477 | default: abort (); |
b99bd4ef | 12478 | } |
c19d1205 ZW |
12479 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
12480 | inst.instruction |= inst.operands[0].reg; | |
12481 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
12482 | } |
12483 | } | |
c19d1205 ZW |
12484 | } |
12485 | else | |
12486 | { | |
12487 | constraint (inst.operands[0].reg > 7 | |
12488 | || inst.operands[1].reg > 7, BAD_HIREG); | |
12489 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 12490 | |
c19d1205 ZW |
12491 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
12492 | { | |
12493 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
12494 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
12495 | _("source1 and dest must be same register")); | |
b99bd4ef | 12496 | |
c19d1205 ZW |
12497 | switch (inst.instruction) |
12498 | { | |
12499 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
12500 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
12501 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
12502 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
12503 | default: abort (); | |
12504 | } | |
5f4273c7 | 12505 | |
c19d1205 ZW |
12506 | inst.instruction |= inst.operands[0].reg; |
12507 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
12508 | |
12509 | /* PR 12854: Error on extraneous shifts. */ | |
12510 | constraint (inst.operands[2].shifted, | |
12511 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
12512 | } |
12513 | else | |
b99bd4ef | 12514 | { |
c19d1205 ZW |
12515 | switch (inst.instruction) |
12516 | { | |
12517 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
12518 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
12519 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
12520 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
12521 | default: abort (); | |
12522 | } | |
12523 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
12524 | inst.instruction |= inst.operands[0].reg; | |
12525 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
12526 | } |
12527 | } | |
b99bd4ef NC |
12528 | } |
12529 | ||
12530 | static void | |
c19d1205 | 12531 | do_t_simd (void) |
b99bd4ef | 12532 | { |
fdfde340 JM |
12533 | unsigned Rd, Rn, Rm; |
12534 | ||
12535 | Rd = inst.operands[0].reg; | |
12536 | Rn = inst.operands[1].reg; | |
12537 | Rm = inst.operands[2].reg; | |
12538 | ||
12539 | reject_bad_reg (Rd); | |
12540 | reject_bad_reg (Rn); | |
12541 | reject_bad_reg (Rm); | |
12542 | ||
12543 | inst.instruction |= Rd << 8; | |
12544 | inst.instruction |= Rn << 16; | |
12545 | inst.instruction |= Rm; | |
c19d1205 | 12546 | } |
b99bd4ef | 12547 | |
03ee1b7f NC |
12548 | static void |
12549 | do_t_simd2 (void) | |
12550 | { | |
12551 | unsigned Rd, Rn, Rm; | |
12552 | ||
12553 | Rd = inst.operands[0].reg; | |
12554 | Rm = inst.operands[1].reg; | |
12555 | Rn = inst.operands[2].reg; | |
12556 | ||
12557 | reject_bad_reg (Rd); | |
12558 | reject_bad_reg (Rn); | |
12559 | reject_bad_reg (Rm); | |
12560 | ||
12561 | inst.instruction |= Rd << 8; | |
12562 | inst.instruction |= Rn << 16; | |
12563 | inst.instruction |= Rm; | |
12564 | } | |
12565 | ||
c19d1205 | 12566 | static void |
3eb17e6b | 12567 | do_t_smc (void) |
c19d1205 ZW |
12568 | { |
12569 | unsigned int value = inst.reloc.exp.X_add_number; | |
f4c65163 MGD |
12570 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a), |
12571 | _("SMC is not permitted on this architecture")); | |
c19d1205 ZW |
12572 | constraint (inst.reloc.exp.X_op != O_constant, |
12573 | _("expression too complex")); | |
12574 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12575 | inst.instruction |= (value & 0xf000) >> 12; | |
12576 | inst.instruction |= (value & 0x0ff0); | |
12577 | inst.instruction |= (value & 0x000f) << 16; | |
24382199 NC |
12578 | /* PR gas/15623: SMC instructions must be last in an IT block. */ |
12579 | set_it_insn_type_last (); | |
c19d1205 | 12580 | } |
b99bd4ef | 12581 | |
90ec0d68 MGD |
12582 | static void |
12583 | do_t_hvc (void) | |
12584 | { | |
12585 | unsigned int value = inst.reloc.exp.X_add_number; | |
12586 | ||
12587 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12588 | inst.instruction |= (value & 0x0fff); | |
12589 | inst.instruction |= (value & 0xf000) << 4; | |
12590 | } | |
12591 | ||
c19d1205 | 12592 | static void |
3a21c15a | 12593 | do_t_ssat_usat (int bias) |
c19d1205 | 12594 | { |
fdfde340 JM |
12595 | unsigned Rd, Rn; |
12596 | ||
12597 | Rd = inst.operands[0].reg; | |
12598 | Rn = inst.operands[2].reg; | |
12599 | ||
12600 | reject_bad_reg (Rd); | |
12601 | reject_bad_reg (Rn); | |
12602 | ||
12603 | inst.instruction |= Rd << 8; | |
3a21c15a | 12604 | inst.instruction |= inst.operands[1].imm - bias; |
fdfde340 | 12605 | inst.instruction |= Rn << 16; |
b99bd4ef | 12606 | |
c19d1205 | 12607 | if (inst.operands[3].present) |
b99bd4ef | 12608 | { |
3a21c15a NC |
12609 | offsetT shift_amount = inst.reloc.exp.X_add_number; |
12610 | ||
12611 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12612 | ||
c19d1205 ZW |
12613 | constraint (inst.reloc.exp.X_op != O_constant, |
12614 | _("expression too complex")); | |
b99bd4ef | 12615 | |
3a21c15a | 12616 | if (shift_amount != 0) |
6189168b | 12617 | { |
3a21c15a NC |
12618 | constraint (shift_amount > 31, |
12619 | _("shift expression is too large")); | |
12620 | ||
c19d1205 | 12621 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
3a21c15a NC |
12622 | inst.instruction |= 0x00200000; /* sh bit. */ |
12623 | ||
12624 | inst.instruction |= (shift_amount & 0x1c) << 10; | |
12625 | inst.instruction |= (shift_amount & 0x03) << 6; | |
6189168b NC |
12626 | } |
12627 | } | |
b99bd4ef | 12628 | } |
c921be7d | 12629 | |
3a21c15a NC |
12630 | static void |
12631 | do_t_ssat (void) | |
12632 | { | |
12633 | do_t_ssat_usat (1); | |
12634 | } | |
b99bd4ef | 12635 | |
0dd132b6 | 12636 | static void |
c19d1205 | 12637 | do_t_ssat16 (void) |
0dd132b6 | 12638 | { |
fdfde340 JM |
12639 | unsigned Rd, Rn; |
12640 | ||
12641 | Rd = inst.operands[0].reg; | |
12642 | Rn = inst.operands[2].reg; | |
12643 | ||
12644 | reject_bad_reg (Rd); | |
12645 | reject_bad_reg (Rn); | |
12646 | ||
12647 | inst.instruction |= Rd << 8; | |
c19d1205 | 12648 | inst.instruction |= inst.operands[1].imm - 1; |
fdfde340 | 12649 | inst.instruction |= Rn << 16; |
c19d1205 | 12650 | } |
0dd132b6 | 12651 | |
c19d1205 ZW |
12652 | static void |
12653 | do_t_strex (void) | |
12654 | { | |
12655 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
12656 | || inst.operands[2].postind || inst.operands[2].writeback | |
12657 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
12658 | || inst.operands[2].negative, | |
01cfc07f | 12659 | BAD_ADDR_MODE); |
0dd132b6 | 12660 | |
5be8be5d DG |
12661 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
12662 | ||
c19d1205 ZW |
12663 | inst.instruction |= inst.operands[0].reg << 8; |
12664 | inst.instruction |= inst.operands[1].reg << 12; | |
12665 | inst.instruction |= inst.operands[2].reg << 16; | |
12666 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
12667 | } |
12668 | ||
b99bd4ef | 12669 | static void |
c19d1205 | 12670 | do_t_strexd (void) |
b99bd4ef | 12671 | { |
c19d1205 ZW |
12672 | if (!inst.operands[2].present) |
12673 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 12674 | |
c19d1205 ZW |
12675 | constraint (inst.operands[0].reg == inst.operands[1].reg |
12676 | || inst.operands[0].reg == inst.operands[2].reg | |
f8a8e9d6 | 12677 | || inst.operands[0].reg == inst.operands[3].reg, |
c19d1205 | 12678 | BAD_OVERLAP); |
b99bd4ef | 12679 | |
c19d1205 ZW |
12680 | inst.instruction |= inst.operands[0].reg; |
12681 | inst.instruction |= inst.operands[1].reg << 12; | |
12682 | inst.instruction |= inst.operands[2].reg << 8; | |
12683 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
12684 | } |
12685 | ||
12686 | static void | |
c19d1205 | 12687 | do_t_sxtah (void) |
b99bd4ef | 12688 | { |
fdfde340 JM |
12689 | unsigned Rd, Rn, Rm; |
12690 | ||
12691 | Rd = inst.operands[0].reg; | |
12692 | Rn = inst.operands[1].reg; | |
12693 | Rm = inst.operands[2].reg; | |
12694 | ||
12695 | reject_bad_reg (Rd); | |
12696 | reject_bad_reg (Rn); | |
12697 | reject_bad_reg (Rm); | |
12698 | ||
12699 | inst.instruction |= Rd << 8; | |
12700 | inst.instruction |= Rn << 16; | |
12701 | inst.instruction |= Rm; | |
c19d1205 ZW |
12702 | inst.instruction |= inst.operands[3].imm << 4; |
12703 | } | |
b99bd4ef | 12704 | |
c19d1205 ZW |
12705 | static void |
12706 | do_t_sxth (void) | |
12707 | { | |
fdfde340 JM |
12708 | unsigned Rd, Rm; |
12709 | ||
12710 | Rd = inst.operands[0].reg; | |
12711 | Rm = inst.operands[1].reg; | |
12712 | ||
12713 | reject_bad_reg (Rd); | |
12714 | reject_bad_reg (Rm); | |
c921be7d NC |
12715 | |
12716 | if (inst.instruction <= 0xffff | |
12717 | && inst.size_req != 4 | |
fdfde340 | 12718 | && Rd <= 7 && Rm <= 7 |
c19d1205 | 12719 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) |
b99bd4ef | 12720 | { |
c19d1205 | 12721 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
12722 | inst.instruction |= Rd; |
12723 | inst.instruction |= Rm << 3; | |
b99bd4ef | 12724 | } |
c19d1205 | 12725 | else if (unified_syntax) |
b99bd4ef | 12726 | { |
c19d1205 ZW |
12727 | if (inst.instruction <= 0xffff) |
12728 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
12729 | inst.instruction |= Rd << 8; |
12730 | inst.instruction |= Rm; | |
c19d1205 | 12731 | inst.instruction |= inst.operands[2].imm << 4; |
b99bd4ef | 12732 | } |
c19d1205 | 12733 | else |
b99bd4ef | 12734 | { |
c19d1205 ZW |
12735 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
12736 | _("Thumb encoding does not support rotation")); | |
12737 | constraint (1, BAD_HIREG); | |
b99bd4ef | 12738 | } |
c19d1205 | 12739 | } |
b99bd4ef | 12740 | |
c19d1205 ZW |
12741 | static void |
12742 | do_t_swi (void) | |
12743 | { | |
b2a5fbdc MGD |
12744 | /* We have to do the following check manually as ARM_EXT_OS only applies |
12745 | to ARM_EXT_V6M. */ | |
12746 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m)) | |
12747 | { | |
ac7f631b NC |
12748 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os) |
12749 | /* This only applies to the v6m howver, not later architectures. */ | |
12750 | && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)) | |
b2a5fbdc MGD |
12751 | as_bad (_("SVC is not permitted on this architecture")); |
12752 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os); | |
12753 | } | |
12754 | ||
c19d1205 ZW |
12755 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
12756 | } | |
b99bd4ef | 12757 | |
92e90b6e PB |
12758 | static void |
12759 | do_t_tb (void) | |
12760 | { | |
fdfde340 | 12761 | unsigned Rn, Rm; |
92e90b6e PB |
12762 | int half; |
12763 | ||
12764 | half = (inst.instruction & 0x10) != 0; | |
e07e6e58 | 12765 | set_it_insn_type_last (); |
dfa9f0d5 PB |
12766 | constraint (inst.operands[0].immisreg, |
12767 | _("instruction requires register index")); | |
fdfde340 JM |
12768 | |
12769 | Rn = inst.operands[0].reg; | |
12770 | Rm = inst.operands[0].imm; | |
c921be7d | 12771 | |
fdfde340 JM |
12772 | constraint (Rn == REG_SP, BAD_SP); |
12773 | reject_bad_reg (Rm); | |
12774 | ||
92e90b6e PB |
12775 | constraint (!half && inst.operands[0].shifted, |
12776 | _("instruction does not allow shifted index")); | |
fdfde340 | 12777 | inst.instruction |= (Rn << 16) | Rm; |
92e90b6e PB |
12778 | } |
12779 | ||
74db7efb NC |
12780 | static void |
12781 | do_t_udf (void) | |
12782 | { | |
12783 | if (!inst.operands[0].present) | |
12784 | inst.operands[0].imm = 0; | |
12785 | ||
12786 | if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4) | |
12787 | { | |
12788 | constraint (inst.size_req == 2, | |
12789 | _("immediate value out of range")); | |
12790 | inst.instruction = THUMB_OP32 (inst.instruction); | |
12791 | inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4; | |
12792 | inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0; | |
12793 | } | |
12794 | else | |
12795 | { | |
12796 | inst.instruction = THUMB_OP16 (inst.instruction); | |
12797 | inst.instruction |= inst.operands[0].imm; | |
12798 | } | |
12799 | ||
12800 | set_it_insn_type (NEUTRAL_IT_INSN); | |
12801 | } | |
12802 | ||
12803 | ||
c19d1205 ZW |
12804 | static void |
12805 | do_t_usat (void) | |
12806 | { | |
3a21c15a | 12807 | do_t_ssat_usat (0); |
b99bd4ef NC |
12808 | } |
12809 | ||
12810 | static void | |
c19d1205 | 12811 | do_t_usat16 (void) |
b99bd4ef | 12812 | { |
fdfde340 JM |
12813 | unsigned Rd, Rn; |
12814 | ||
12815 | Rd = inst.operands[0].reg; | |
12816 | Rn = inst.operands[2].reg; | |
12817 | ||
12818 | reject_bad_reg (Rd); | |
12819 | reject_bad_reg (Rn); | |
12820 | ||
12821 | inst.instruction |= Rd << 8; | |
c19d1205 | 12822 | inst.instruction |= inst.operands[1].imm; |
fdfde340 | 12823 | inst.instruction |= Rn << 16; |
b99bd4ef | 12824 | } |
c19d1205 | 12825 | |
5287ad62 | 12826 | /* Neon instruction encoder helpers. */ |
5f4273c7 | 12827 | |
5287ad62 | 12828 | /* Encodings for the different types for various Neon opcodes. */ |
b99bd4ef | 12829 | |
5287ad62 JB |
12830 | /* An "invalid" code for the following tables. */ |
12831 | #define N_INV -1u | |
12832 | ||
12833 | struct neon_tab_entry | |
b99bd4ef | 12834 | { |
5287ad62 JB |
12835 | unsigned integer; |
12836 | unsigned float_or_poly; | |
12837 | unsigned scalar_or_imm; | |
12838 | }; | |
5f4273c7 | 12839 | |
5287ad62 JB |
12840 | /* Map overloaded Neon opcodes to their respective encodings. */ |
12841 | #define NEON_ENC_TAB \ | |
12842 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ | |
12843 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ | |
12844 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ | |
12845 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ | |
12846 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ | |
12847 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ | |
12848 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ | |
12849 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ | |
12850 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ | |
12851 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ | |
12852 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ | |
12853 | /* Register variants of the following two instructions are encoded as | |
e07e6e58 | 12854 | vcge / vcgt with the operands reversed. */ \ |
92559b5b PB |
12855 | X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ |
12856 | X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ | |
62f3b8c8 PB |
12857 | X(vfma, N_INV, 0x0000c10, N_INV), \ |
12858 | X(vfms, N_INV, 0x0200c10, N_INV), \ | |
5287ad62 JB |
12859 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ |
12860 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ | |
12861 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ | |
12862 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ | |
12863 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ | |
12864 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ | |
12865 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ | |
12866 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ | |
12867 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ | |
12868 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ | |
12869 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ | |
12870 | X(vshl, 0x0000400, N_INV, 0x0800510), \ | |
12871 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ | |
12872 | X(vand, 0x0000110, N_INV, 0x0800030), \ | |
12873 | X(vbic, 0x0100110, N_INV, 0x0800030), \ | |
12874 | X(veor, 0x1000110, N_INV, N_INV), \ | |
12875 | X(vorn, 0x0300110, N_INV, 0x0800010), \ | |
12876 | X(vorr, 0x0200110, N_INV, 0x0800010), \ | |
12877 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ | |
12878 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ | |
12879 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ | |
12880 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ | |
12881 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ | |
12882 | X(vst1, 0x0000000, 0x0800000, N_INV), \ | |
12883 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ | |
12884 | X(vst2, 0x0000100, 0x0800100, N_INV), \ | |
12885 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ | |
12886 | X(vst3, 0x0000200, 0x0800200, N_INV), \ | |
12887 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ | |
12888 | X(vst4, 0x0000300, 0x0800300, N_INV), \ | |
12889 | X(vmovn, 0x1b20200, N_INV, N_INV), \ | |
12890 | X(vtrn, 0x1b20080, N_INV, N_INV), \ | |
12891 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ | |
037e8744 JB |
12892 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
12893 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ | |
e6655fda PB |
12894 | X(vnmla, 0xe100a40, 0xe100b40, N_INV), \ |
12895 | X(vnmls, 0xe100a00, 0xe100b00, N_INV), \ | |
62f3b8c8 PB |
12896 | X(vfnma, 0xe900a40, 0xe900b40, N_INV), \ |
12897 | X(vfnms, 0xe900a00, 0xe900b00, N_INV), \ | |
037e8744 JB |
12898 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ |
12899 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ | |
12900 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ | |
33399f07 MGD |
12901 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \ |
12902 | X(vseleq, 0xe000a00, N_INV, N_INV), \ | |
12903 | X(vselvs, 0xe100a00, N_INV, N_INV), \ | |
12904 | X(vselge, 0xe200a00, N_INV, N_INV), \ | |
73924fbc MGD |
12905 | X(vselgt, 0xe300a00, N_INV, N_INV), \ |
12906 | X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \ | |
7e8e6784 | 12907 | X(vminnm, 0xe800a40, 0x3200f10, N_INV), \ |
30bdf752 MGD |
12908 | X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \ |
12909 | X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \ | |
91ff7894 | 12910 | X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \ |
48adcd8e | 12911 | X(aes, 0x3b00300, N_INV, N_INV), \ |
3c9017d2 MGD |
12912 | X(sha3op, 0x2000c00, N_INV, N_INV), \ |
12913 | X(sha1h, 0x3b902c0, N_INV, N_INV), \ | |
12914 | X(sha2op, 0x3ba0380, N_INV, N_INV) | |
5287ad62 JB |
12915 | |
12916 | enum neon_opc | |
12917 | { | |
12918 | #define X(OPC,I,F,S) N_MNEM_##OPC | |
12919 | NEON_ENC_TAB | |
12920 | #undef X | |
12921 | }; | |
b99bd4ef | 12922 | |
5287ad62 JB |
12923 | static const struct neon_tab_entry neon_enc_tab[] = |
12924 | { | |
12925 | #define X(OPC,I,F,S) { (I), (F), (S) } | |
12926 | NEON_ENC_TAB | |
12927 | #undef X | |
12928 | }; | |
b99bd4ef | 12929 | |
88714cb8 DG |
12930 | /* Do not use these macros; instead, use NEON_ENCODE defined below. */ |
12931 | #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
12932 | #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
12933 | #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
12934 | #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
12935 | #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
12936 | #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
12937 | #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
12938 | #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
12939 | #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
12940 | #define NEON_ENC_SINGLE_(X) \ | |
037e8744 | 12941 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) |
88714cb8 | 12942 | #define NEON_ENC_DOUBLE_(X) \ |
037e8744 | 12943 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) |
33399f07 MGD |
12944 | #define NEON_ENC_FPV8_(X) \ |
12945 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000)) | |
5287ad62 | 12946 | |
88714cb8 DG |
12947 | #define NEON_ENCODE(type, inst) \ |
12948 | do \ | |
12949 | { \ | |
12950 | inst.instruction = NEON_ENC_##type##_ (inst.instruction); \ | |
12951 | inst.is_neon = 1; \ | |
12952 | } \ | |
12953 | while (0) | |
12954 | ||
12955 | #define check_neon_suffixes \ | |
12956 | do \ | |
12957 | { \ | |
12958 | if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \ | |
12959 | { \ | |
12960 | as_bad (_("invalid neon suffix for non neon instruction")); \ | |
12961 | return; \ | |
12962 | } \ | |
12963 | } \ | |
12964 | while (0) | |
12965 | ||
037e8744 JB |
12966 | /* Define shapes for instruction operands. The following mnemonic characters |
12967 | are used in this table: | |
5287ad62 | 12968 | |
037e8744 | 12969 | F - VFP S<n> register |
5287ad62 JB |
12970 | D - Neon D<n> register |
12971 | Q - Neon Q<n> register | |
12972 | I - Immediate | |
12973 | S - Scalar | |
12974 | R - ARM register | |
12975 | L - D<n> register list | |
5f4273c7 | 12976 | |
037e8744 JB |
12977 | This table is used to generate various data: |
12978 | - enumerations of the form NS_DDR to be used as arguments to | |
12979 | neon_select_shape. | |
12980 | - a table classifying shapes into single, double, quad, mixed. | |
5f4273c7 | 12981 | - a table used to drive neon_select_shape. */ |
b99bd4ef | 12982 | |
037e8744 JB |
12983 | #define NEON_SHAPE_DEF \ |
12984 | X(3, (D, D, D), DOUBLE), \ | |
12985 | X(3, (Q, Q, Q), QUAD), \ | |
12986 | X(3, (D, D, I), DOUBLE), \ | |
12987 | X(3, (Q, Q, I), QUAD), \ | |
12988 | X(3, (D, D, S), DOUBLE), \ | |
12989 | X(3, (Q, Q, S), QUAD), \ | |
12990 | X(2, (D, D), DOUBLE), \ | |
12991 | X(2, (Q, Q), QUAD), \ | |
12992 | X(2, (D, S), DOUBLE), \ | |
12993 | X(2, (Q, S), QUAD), \ | |
12994 | X(2, (D, R), DOUBLE), \ | |
12995 | X(2, (Q, R), QUAD), \ | |
12996 | X(2, (D, I), DOUBLE), \ | |
12997 | X(2, (Q, I), QUAD), \ | |
12998 | X(3, (D, L, D), DOUBLE), \ | |
12999 | X(2, (D, Q), MIXED), \ | |
13000 | X(2, (Q, D), MIXED), \ | |
13001 | X(3, (D, Q, I), MIXED), \ | |
13002 | X(3, (Q, D, I), MIXED), \ | |
13003 | X(3, (Q, D, D), MIXED), \ | |
13004 | X(3, (D, Q, Q), MIXED), \ | |
13005 | X(3, (Q, Q, D), MIXED), \ | |
13006 | X(3, (Q, D, S), MIXED), \ | |
13007 | X(3, (D, Q, S), MIXED), \ | |
13008 | X(4, (D, D, D, I), DOUBLE), \ | |
13009 | X(4, (Q, Q, Q, I), QUAD), \ | |
13010 | X(2, (F, F), SINGLE), \ | |
13011 | X(3, (F, F, F), SINGLE), \ | |
13012 | X(2, (F, I), SINGLE), \ | |
13013 | X(2, (F, D), MIXED), \ | |
13014 | X(2, (D, F), MIXED), \ | |
13015 | X(3, (F, F, I), MIXED), \ | |
13016 | X(4, (R, R, F, F), SINGLE), \ | |
13017 | X(4, (F, F, R, R), SINGLE), \ | |
13018 | X(3, (D, R, R), DOUBLE), \ | |
13019 | X(3, (R, R, D), DOUBLE), \ | |
13020 | X(2, (S, R), SINGLE), \ | |
13021 | X(2, (R, S), SINGLE), \ | |
13022 | X(2, (F, R), SINGLE), \ | |
13023 | X(2, (R, F), SINGLE) | |
13024 | ||
13025 | #define S2(A,B) NS_##A##B | |
13026 | #define S3(A,B,C) NS_##A##B##C | |
13027 | #define S4(A,B,C,D) NS_##A##B##C##D | |
13028 | ||
13029 | #define X(N, L, C) S##N L | |
13030 | ||
5287ad62 JB |
13031 | enum neon_shape |
13032 | { | |
037e8744 JB |
13033 | NEON_SHAPE_DEF, |
13034 | NS_NULL | |
5287ad62 | 13035 | }; |
b99bd4ef | 13036 | |
037e8744 JB |
13037 | #undef X |
13038 | #undef S2 | |
13039 | #undef S3 | |
13040 | #undef S4 | |
13041 | ||
13042 | enum neon_shape_class | |
13043 | { | |
13044 | SC_SINGLE, | |
13045 | SC_DOUBLE, | |
13046 | SC_QUAD, | |
13047 | SC_MIXED | |
13048 | }; | |
13049 | ||
13050 | #define X(N, L, C) SC_##C | |
13051 | ||
13052 | static enum neon_shape_class neon_shape_class[] = | |
13053 | { | |
13054 | NEON_SHAPE_DEF | |
13055 | }; | |
13056 | ||
13057 | #undef X | |
13058 | ||
13059 | enum neon_shape_el | |
13060 | { | |
13061 | SE_F, | |
13062 | SE_D, | |
13063 | SE_Q, | |
13064 | SE_I, | |
13065 | SE_S, | |
13066 | SE_R, | |
13067 | SE_L | |
13068 | }; | |
13069 | ||
13070 | /* Register widths of above. */ | |
13071 | static unsigned neon_shape_el_size[] = | |
13072 | { | |
13073 | 32, | |
13074 | 64, | |
13075 | 128, | |
13076 | 0, | |
13077 | 32, | |
13078 | 32, | |
13079 | 0 | |
13080 | }; | |
13081 | ||
13082 | struct neon_shape_info | |
13083 | { | |
13084 | unsigned els; | |
13085 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; | |
13086 | }; | |
13087 | ||
13088 | #define S2(A,B) { SE_##A, SE_##B } | |
13089 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } | |
13090 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } | |
13091 | ||
13092 | #define X(N, L, C) { N, S##N L } | |
13093 | ||
13094 | static struct neon_shape_info neon_shape_tab[] = | |
13095 | { | |
13096 | NEON_SHAPE_DEF | |
13097 | }; | |
13098 | ||
13099 | #undef X | |
13100 | #undef S2 | |
13101 | #undef S3 | |
13102 | #undef S4 | |
13103 | ||
5287ad62 JB |
13104 | /* Bit masks used in type checking given instructions. |
13105 | 'N_EQK' means the type must be the same as (or based on in some way) the key | |
13106 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is | |
13107 | set, various other bits can be set as well in order to modify the meaning of | |
13108 | the type constraint. */ | |
13109 | ||
13110 | enum neon_type_mask | |
13111 | { | |
8e79c3df CM |
13112 | N_S8 = 0x0000001, |
13113 | N_S16 = 0x0000002, | |
13114 | N_S32 = 0x0000004, | |
13115 | N_S64 = 0x0000008, | |
13116 | N_U8 = 0x0000010, | |
13117 | N_U16 = 0x0000020, | |
13118 | N_U32 = 0x0000040, | |
13119 | N_U64 = 0x0000080, | |
13120 | N_I8 = 0x0000100, | |
13121 | N_I16 = 0x0000200, | |
13122 | N_I32 = 0x0000400, | |
13123 | N_I64 = 0x0000800, | |
13124 | N_8 = 0x0001000, | |
13125 | N_16 = 0x0002000, | |
13126 | N_32 = 0x0004000, | |
13127 | N_64 = 0x0008000, | |
13128 | N_P8 = 0x0010000, | |
13129 | N_P16 = 0x0020000, | |
13130 | N_F16 = 0x0040000, | |
13131 | N_F32 = 0x0080000, | |
13132 | N_F64 = 0x0100000, | |
4f51b4bd | 13133 | N_P64 = 0x0200000, |
c921be7d NC |
13134 | N_KEY = 0x1000000, /* Key element (main type specifier). */ |
13135 | N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ | |
8e79c3df | 13136 | N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ |
91ff7894 | 13137 | N_UNT = 0x8000000, /* Must be explicitly untyped. */ |
c921be7d NC |
13138 | N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ |
13139 | N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ | |
13140 | N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ | |
13141 | N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ | |
13142 | N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ | |
13143 | N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ | |
13144 | N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ | |
5287ad62 | 13145 | N_UTYP = 0, |
4f51b4bd | 13146 | N_MAX_NONSPECIAL = N_P64 |
5287ad62 JB |
13147 | }; |
13148 | ||
dcbf9037 JB |
13149 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
13150 | ||
5287ad62 JB |
13151 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
13152 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
13153 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) | |
13154 | #define N_SUF_32 (N_SU_32 | N_F32) | |
13155 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) | |
13156 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) | |
13157 | ||
13158 | /* Pass this as the first type argument to neon_check_type to ignore types | |
13159 | altogether. */ | |
13160 | #define N_IGNORE_TYPE (N_KEY | N_EQK) | |
13161 | ||
037e8744 JB |
13162 | /* Select a "shape" for the current instruction (describing register types or |
13163 | sizes) from a list of alternatives. Return NS_NULL if the current instruction | |
13164 | doesn't fit. For non-polymorphic shapes, checking is usually done as a | |
13165 | function of operand parsing, so this function doesn't need to be called. | |
13166 | Shapes should be listed in order of decreasing length. */ | |
5287ad62 JB |
13167 | |
13168 | static enum neon_shape | |
037e8744 | 13169 | neon_select_shape (enum neon_shape shape, ...) |
5287ad62 | 13170 | { |
037e8744 JB |
13171 | va_list ap; |
13172 | enum neon_shape first_shape = shape; | |
5287ad62 JB |
13173 | |
13174 | /* Fix missing optional operands. FIXME: we don't know at this point how | |
13175 | many arguments we should have, so this makes the assumption that we have | |
13176 | > 1. This is true of all current Neon opcodes, I think, but may not be | |
13177 | true in the future. */ | |
13178 | if (!inst.operands[1].present) | |
13179 | inst.operands[1] = inst.operands[0]; | |
13180 | ||
037e8744 | 13181 | va_start (ap, shape); |
5f4273c7 | 13182 | |
21d799b5 | 13183 | for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int)) |
037e8744 JB |
13184 | { |
13185 | unsigned j; | |
13186 | int matches = 1; | |
13187 | ||
13188 | for (j = 0; j < neon_shape_tab[shape].els; j++) | |
477330fc RM |
13189 | { |
13190 | if (!inst.operands[j].present) | |
13191 | { | |
13192 | matches = 0; | |
13193 | break; | |
13194 | } | |
13195 | ||
13196 | switch (neon_shape_tab[shape].el[j]) | |
13197 | { | |
13198 | case SE_F: | |
13199 | if (!(inst.operands[j].isreg | |
13200 | && inst.operands[j].isvec | |
13201 | && inst.operands[j].issingle | |
13202 | && !inst.operands[j].isquad)) | |
13203 | matches = 0; | |
13204 | break; | |
13205 | ||
13206 | case SE_D: | |
13207 | if (!(inst.operands[j].isreg | |
13208 | && inst.operands[j].isvec | |
13209 | && !inst.operands[j].isquad | |
13210 | && !inst.operands[j].issingle)) | |
13211 | matches = 0; | |
13212 | break; | |
13213 | ||
13214 | case SE_R: | |
13215 | if (!(inst.operands[j].isreg | |
13216 | && !inst.operands[j].isvec)) | |
13217 | matches = 0; | |
13218 | break; | |
13219 | ||
13220 | case SE_Q: | |
13221 | if (!(inst.operands[j].isreg | |
13222 | && inst.operands[j].isvec | |
13223 | && inst.operands[j].isquad | |
13224 | && !inst.operands[j].issingle)) | |
13225 | matches = 0; | |
13226 | break; | |
13227 | ||
13228 | case SE_I: | |
13229 | if (!(!inst.operands[j].isreg | |
13230 | && !inst.operands[j].isscalar)) | |
13231 | matches = 0; | |
13232 | break; | |
13233 | ||
13234 | case SE_S: | |
13235 | if (!(!inst.operands[j].isreg | |
13236 | && inst.operands[j].isscalar)) | |
13237 | matches = 0; | |
13238 | break; | |
13239 | ||
13240 | case SE_L: | |
13241 | break; | |
13242 | } | |
3fde54a2 JZ |
13243 | if (!matches) |
13244 | break; | |
477330fc | 13245 | } |
ad6cec43 MGD |
13246 | if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present)) |
13247 | /* We've matched all the entries in the shape table, and we don't | |
13248 | have any left over operands which have not been matched. */ | |
477330fc | 13249 | break; |
037e8744 | 13250 | } |
5f4273c7 | 13251 | |
037e8744 | 13252 | va_end (ap); |
5287ad62 | 13253 | |
037e8744 JB |
13254 | if (shape == NS_NULL && first_shape != NS_NULL) |
13255 | first_error (_("invalid instruction shape")); | |
5287ad62 | 13256 | |
037e8744 JB |
13257 | return shape; |
13258 | } | |
5287ad62 | 13259 | |
037e8744 JB |
13260 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
13261 | means the Q bit should be set). */ | |
13262 | ||
13263 | static int | |
13264 | neon_quad (enum neon_shape shape) | |
13265 | { | |
13266 | return neon_shape_class[shape] == SC_QUAD; | |
5287ad62 | 13267 | } |
037e8744 | 13268 | |
5287ad62 JB |
13269 | static void |
13270 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, | |
477330fc | 13271 | unsigned *g_size) |
5287ad62 JB |
13272 | { |
13273 | /* Allow modification to be made to types which are constrained to be | |
13274 | based on the key element, based on bits set alongside N_EQK. */ | |
13275 | if ((typebits & N_EQK) != 0) | |
13276 | { | |
13277 | if ((typebits & N_HLF) != 0) | |
13278 | *g_size /= 2; | |
13279 | else if ((typebits & N_DBL) != 0) | |
13280 | *g_size *= 2; | |
13281 | if ((typebits & N_SGN) != 0) | |
13282 | *g_type = NT_signed; | |
13283 | else if ((typebits & N_UNS) != 0) | |
477330fc | 13284 | *g_type = NT_unsigned; |
5287ad62 | 13285 | else if ((typebits & N_INT) != 0) |
477330fc | 13286 | *g_type = NT_integer; |
5287ad62 | 13287 | else if ((typebits & N_FLT) != 0) |
477330fc | 13288 | *g_type = NT_float; |
dcbf9037 | 13289 | else if ((typebits & N_SIZ) != 0) |
477330fc | 13290 | *g_type = NT_untyped; |
5287ad62 JB |
13291 | } |
13292 | } | |
5f4273c7 | 13293 | |
5287ad62 JB |
13294 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" |
13295 | operand type, i.e. the single type specified in a Neon instruction when it | |
13296 | is the only one given. */ | |
13297 | ||
13298 | static struct neon_type_el | |
13299 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) | |
13300 | { | |
13301 | struct neon_type_el dest = *key; | |
5f4273c7 | 13302 | |
9c2799c2 | 13303 | gas_assert ((thisarg & N_EQK) != 0); |
5f4273c7 | 13304 | |
5287ad62 JB |
13305 | neon_modify_type_size (thisarg, &dest.type, &dest.size); |
13306 | ||
13307 | return dest; | |
13308 | } | |
13309 | ||
13310 | /* Convert Neon type and size into compact bitmask representation. */ | |
13311 | ||
13312 | static enum neon_type_mask | |
13313 | type_chk_of_el_type (enum neon_el_type type, unsigned size) | |
13314 | { | |
13315 | switch (type) | |
13316 | { | |
13317 | case NT_untyped: | |
13318 | switch (size) | |
477330fc RM |
13319 | { |
13320 | case 8: return N_8; | |
13321 | case 16: return N_16; | |
13322 | case 32: return N_32; | |
13323 | case 64: return N_64; | |
13324 | default: ; | |
13325 | } | |
5287ad62 JB |
13326 | break; |
13327 | ||
13328 | case NT_integer: | |
13329 | switch (size) | |
477330fc RM |
13330 | { |
13331 | case 8: return N_I8; | |
13332 | case 16: return N_I16; | |
13333 | case 32: return N_I32; | |
13334 | case 64: return N_I64; | |
13335 | default: ; | |
13336 | } | |
5287ad62 JB |
13337 | break; |
13338 | ||
13339 | case NT_float: | |
037e8744 | 13340 | switch (size) |
477330fc | 13341 | { |
8e79c3df | 13342 | case 16: return N_F16; |
477330fc RM |
13343 | case 32: return N_F32; |
13344 | case 64: return N_F64; | |
13345 | default: ; | |
13346 | } | |
5287ad62 JB |
13347 | break; |
13348 | ||
13349 | case NT_poly: | |
13350 | switch (size) | |
477330fc RM |
13351 | { |
13352 | case 8: return N_P8; | |
13353 | case 16: return N_P16; | |
4f51b4bd | 13354 | case 64: return N_P64; |
477330fc RM |
13355 | default: ; |
13356 | } | |
5287ad62 JB |
13357 | break; |
13358 | ||
13359 | case NT_signed: | |
13360 | switch (size) | |
477330fc RM |
13361 | { |
13362 | case 8: return N_S8; | |
13363 | case 16: return N_S16; | |
13364 | case 32: return N_S32; | |
13365 | case 64: return N_S64; | |
13366 | default: ; | |
13367 | } | |
5287ad62 JB |
13368 | break; |
13369 | ||
13370 | case NT_unsigned: | |
13371 | switch (size) | |
477330fc RM |
13372 | { |
13373 | case 8: return N_U8; | |
13374 | case 16: return N_U16; | |
13375 | case 32: return N_U32; | |
13376 | case 64: return N_U64; | |
13377 | default: ; | |
13378 | } | |
5287ad62 JB |
13379 | break; |
13380 | ||
13381 | default: ; | |
13382 | } | |
5f4273c7 | 13383 | |
5287ad62 JB |
13384 | return N_UTYP; |
13385 | } | |
13386 | ||
13387 | /* Convert compact Neon bitmask type representation to a type and size. Only | |
13388 | handles the case where a single bit is set in the mask. */ | |
13389 | ||
dcbf9037 | 13390 | static int |
5287ad62 | 13391 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
477330fc | 13392 | enum neon_type_mask mask) |
5287ad62 | 13393 | { |
dcbf9037 JB |
13394 | if ((mask & N_EQK) != 0) |
13395 | return FAIL; | |
13396 | ||
5287ad62 JB |
13397 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
13398 | *size = 8; | |
c70a8987 | 13399 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0) |
5287ad62 | 13400 | *size = 16; |
dcbf9037 | 13401 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
5287ad62 | 13402 | *size = 32; |
4f51b4bd | 13403 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0) |
5287ad62 | 13404 | *size = 64; |
dcbf9037 JB |
13405 | else |
13406 | return FAIL; | |
13407 | ||
5287ad62 JB |
13408 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
13409 | *type = NT_signed; | |
dcbf9037 | 13410 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
5287ad62 | 13411 | *type = NT_unsigned; |
dcbf9037 | 13412 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
5287ad62 | 13413 | *type = NT_integer; |
dcbf9037 | 13414 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
5287ad62 | 13415 | *type = NT_untyped; |
4f51b4bd | 13416 | else if ((mask & (N_P8 | N_P16 | N_P64)) != 0) |
5287ad62 | 13417 | *type = NT_poly; |
c70a8987 | 13418 | else if ((mask & (N_F16 | N_F32 | N_F64)) != 0) |
5287ad62 | 13419 | *type = NT_float; |
dcbf9037 JB |
13420 | else |
13421 | return FAIL; | |
5f4273c7 | 13422 | |
dcbf9037 | 13423 | return SUCCESS; |
5287ad62 JB |
13424 | } |
13425 | ||
13426 | /* Modify a bitmask of allowed types. This is only needed for type | |
13427 | relaxation. */ | |
13428 | ||
13429 | static unsigned | |
13430 | modify_types_allowed (unsigned allowed, unsigned mods) | |
13431 | { | |
13432 | unsigned size; | |
13433 | enum neon_el_type type; | |
13434 | unsigned destmask; | |
13435 | int i; | |
5f4273c7 | 13436 | |
5287ad62 | 13437 | destmask = 0; |
5f4273c7 | 13438 | |
5287ad62 JB |
13439 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) |
13440 | { | |
21d799b5 | 13441 | if (el_type_of_type_chk (&type, &size, |
477330fc RM |
13442 | (enum neon_type_mask) (allowed & i)) == SUCCESS) |
13443 | { | |
13444 | neon_modify_type_size (mods, &type, &size); | |
13445 | destmask |= type_chk_of_el_type (type, size); | |
13446 | } | |
5287ad62 | 13447 | } |
5f4273c7 | 13448 | |
5287ad62 JB |
13449 | return destmask; |
13450 | } | |
13451 | ||
13452 | /* Check type and return type classification. | |
13453 | The manual states (paraphrase): If one datatype is given, it indicates the | |
13454 | type given in: | |
13455 | - the second operand, if there is one | |
13456 | - the operand, if there is no second operand | |
13457 | - the result, if there are no operands. | |
13458 | This isn't quite good enough though, so we use a concept of a "key" datatype | |
13459 | which is set on a per-instruction basis, which is the one which matters when | |
13460 | only one data type is written. | |
13461 | Note: this function has side-effects (e.g. filling in missing operands). All | |
037e8744 | 13462 | Neon instructions should call it before performing bit encoding. */ |
5287ad62 JB |
13463 | |
13464 | static struct neon_type_el | |
13465 | neon_check_type (unsigned els, enum neon_shape ns, ...) | |
13466 | { | |
13467 | va_list ap; | |
13468 | unsigned i, pass, key_el = 0; | |
13469 | unsigned types[NEON_MAX_TYPE_ELS]; | |
13470 | enum neon_el_type k_type = NT_invtype; | |
13471 | unsigned k_size = -1u; | |
13472 | struct neon_type_el badtype = {NT_invtype, -1}; | |
13473 | unsigned key_allowed = 0; | |
13474 | ||
13475 | /* Optional registers in Neon instructions are always (not) in operand 1. | |
13476 | Fill in the missing operand here, if it was omitted. */ | |
13477 | if (els > 1 && !inst.operands[1].present) | |
13478 | inst.operands[1] = inst.operands[0]; | |
13479 | ||
13480 | /* Suck up all the varargs. */ | |
13481 | va_start (ap, ns); | |
13482 | for (i = 0; i < els; i++) | |
13483 | { | |
13484 | unsigned thisarg = va_arg (ap, unsigned); | |
13485 | if (thisarg == N_IGNORE_TYPE) | |
477330fc RM |
13486 | { |
13487 | va_end (ap); | |
13488 | return badtype; | |
13489 | } | |
5287ad62 JB |
13490 | types[i] = thisarg; |
13491 | if ((thisarg & N_KEY) != 0) | |
477330fc | 13492 | key_el = i; |
5287ad62 JB |
13493 | } |
13494 | va_end (ap); | |
13495 | ||
dcbf9037 JB |
13496 | if (inst.vectype.elems > 0) |
13497 | for (i = 0; i < els; i++) | |
13498 | if (inst.operands[i].vectype.type != NT_invtype) | |
477330fc RM |
13499 | { |
13500 | first_error (_("types specified in both the mnemonic and operands")); | |
13501 | return badtype; | |
13502 | } | |
dcbf9037 | 13503 | |
5287ad62 JB |
13504 | /* Duplicate inst.vectype elements here as necessary. |
13505 | FIXME: No idea if this is exactly the same as the ARM assembler, | |
13506 | particularly when an insn takes one register and one non-register | |
13507 | operand. */ | |
13508 | if (inst.vectype.elems == 1 && els > 1) | |
13509 | { | |
13510 | unsigned j; | |
13511 | inst.vectype.elems = els; | |
13512 | inst.vectype.el[key_el] = inst.vectype.el[0]; | |
13513 | for (j = 0; j < els; j++) | |
477330fc RM |
13514 | if (j != key_el) |
13515 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
13516 | types[j]); | |
dcbf9037 JB |
13517 | } |
13518 | else if (inst.vectype.elems == 0 && els > 0) | |
13519 | { | |
13520 | unsigned j; | |
13521 | /* No types were given after the mnemonic, so look for types specified | |
477330fc RM |
13522 | after each operand. We allow some flexibility here; as long as the |
13523 | "key" operand has a type, we can infer the others. */ | |
dcbf9037 | 13524 | for (j = 0; j < els; j++) |
477330fc RM |
13525 | if (inst.operands[j].vectype.type != NT_invtype) |
13526 | inst.vectype.el[j] = inst.operands[j].vectype; | |
dcbf9037 JB |
13527 | |
13528 | if (inst.operands[key_el].vectype.type != NT_invtype) | |
477330fc RM |
13529 | { |
13530 | for (j = 0; j < els; j++) | |
13531 | if (inst.operands[j].vectype.type == NT_invtype) | |
13532 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
13533 | types[j]); | |
13534 | } | |
dcbf9037 | 13535 | else |
477330fc RM |
13536 | { |
13537 | first_error (_("operand types can't be inferred")); | |
13538 | return badtype; | |
13539 | } | |
5287ad62 JB |
13540 | } |
13541 | else if (inst.vectype.elems != els) | |
13542 | { | |
dcbf9037 | 13543 | first_error (_("type specifier has the wrong number of parts")); |
5287ad62 JB |
13544 | return badtype; |
13545 | } | |
13546 | ||
13547 | for (pass = 0; pass < 2; pass++) | |
13548 | { | |
13549 | for (i = 0; i < els; i++) | |
477330fc RM |
13550 | { |
13551 | unsigned thisarg = types[i]; | |
13552 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) | |
13553 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; | |
13554 | enum neon_el_type g_type = inst.vectype.el[i].type; | |
13555 | unsigned g_size = inst.vectype.el[i].size; | |
13556 | ||
13557 | /* Decay more-specific signed & unsigned types to sign-insensitive | |
5287ad62 | 13558 | integer types if sign-specific variants are unavailable. */ |
477330fc | 13559 | if ((g_type == NT_signed || g_type == NT_unsigned) |
5287ad62 JB |
13560 | && (types_allowed & N_SU_ALL) == 0) |
13561 | g_type = NT_integer; | |
13562 | ||
477330fc | 13563 | /* If only untyped args are allowed, decay any more specific types to |
5287ad62 JB |
13564 | them. Some instructions only care about signs for some element |
13565 | sizes, so handle that properly. */ | |
477330fc | 13566 | if (((types_allowed & N_UNT) == 0) |
91ff7894 MGD |
13567 | && ((g_size == 8 && (types_allowed & N_8) != 0) |
13568 | || (g_size == 16 && (types_allowed & N_16) != 0) | |
13569 | || (g_size == 32 && (types_allowed & N_32) != 0) | |
13570 | || (g_size == 64 && (types_allowed & N_64) != 0))) | |
5287ad62 JB |
13571 | g_type = NT_untyped; |
13572 | ||
477330fc RM |
13573 | if (pass == 0) |
13574 | { | |
13575 | if ((thisarg & N_KEY) != 0) | |
13576 | { | |
13577 | k_type = g_type; | |
13578 | k_size = g_size; | |
13579 | key_allowed = thisarg & ~N_KEY; | |
13580 | } | |
13581 | } | |
13582 | else | |
13583 | { | |
13584 | if ((thisarg & N_VFP) != 0) | |
13585 | { | |
13586 | enum neon_shape_el regshape; | |
13587 | unsigned regwidth, match; | |
99b253c5 NC |
13588 | |
13589 | /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */ | |
13590 | if (ns == NS_NULL) | |
13591 | { | |
13592 | first_error (_("invalid instruction shape")); | |
13593 | return badtype; | |
13594 | } | |
477330fc RM |
13595 | regshape = neon_shape_tab[ns].el[i]; |
13596 | regwidth = neon_shape_el_size[regshape]; | |
13597 | ||
13598 | /* In VFP mode, operands must match register widths. If we | |
13599 | have a key operand, use its width, else use the width of | |
13600 | the current operand. */ | |
13601 | if (k_size != -1u) | |
13602 | match = k_size; | |
13603 | else | |
13604 | match = g_size; | |
13605 | ||
13606 | if (regwidth != match) | |
13607 | { | |
13608 | first_error (_("operand size must match register width")); | |
13609 | return badtype; | |
13610 | } | |
13611 | } | |
13612 | ||
13613 | if ((thisarg & N_EQK) == 0) | |
13614 | { | |
13615 | unsigned given_type = type_chk_of_el_type (g_type, g_size); | |
13616 | ||
13617 | if ((given_type & types_allowed) == 0) | |
13618 | { | |
13619 | first_error (_("bad type in Neon instruction")); | |
13620 | return badtype; | |
13621 | } | |
13622 | } | |
13623 | else | |
13624 | { | |
13625 | enum neon_el_type mod_k_type = k_type; | |
13626 | unsigned mod_k_size = k_size; | |
13627 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); | |
13628 | if (g_type != mod_k_type || g_size != mod_k_size) | |
13629 | { | |
13630 | first_error (_("inconsistent types in Neon instruction")); | |
13631 | return badtype; | |
13632 | } | |
13633 | } | |
13634 | } | |
13635 | } | |
5287ad62 JB |
13636 | } |
13637 | ||
13638 | return inst.vectype.el[key_el]; | |
13639 | } | |
13640 | ||
037e8744 | 13641 | /* Neon-style VFP instruction forwarding. */ |
5287ad62 | 13642 | |
037e8744 JB |
13643 | /* Thumb VFP instructions have 0xE in the condition field. */ |
13644 | ||
13645 | static void | |
13646 | do_vfp_cond_or_thumb (void) | |
5287ad62 | 13647 | { |
88714cb8 DG |
13648 | inst.is_neon = 1; |
13649 | ||
5287ad62 | 13650 | if (thumb_mode) |
037e8744 | 13651 | inst.instruction |= 0xe0000000; |
5287ad62 | 13652 | else |
037e8744 | 13653 | inst.instruction |= inst.cond << 28; |
5287ad62 JB |
13654 | } |
13655 | ||
037e8744 JB |
13656 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
13657 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, | |
13658 | etc. It is assumed that operand parsing has already been done, and that the | |
13659 | operands are in the form expected by the given opcode (this isn't necessarily | |
13660 | the same as the form in which they were parsed, hence some massaging must | |
13661 | take place before this function is called). | |
13662 | Checks current arch version against that in the looked-up opcode. */ | |
5287ad62 | 13663 | |
037e8744 JB |
13664 | static void |
13665 | do_vfp_nsyn_opcode (const char *opname) | |
5287ad62 | 13666 | { |
037e8744 | 13667 | const struct asm_opcode *opcode; |
5f4273c7 | 13668 | |
21d799b5 | 13669 | opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname); |
5287ad62 | 13670 | |
037e8744 JB |
13671 | if (!opcode) |
13672 | abort (); | |
5287ad62 | 13673 | |
037e8744 | 13674 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
477330fc RM |
13675 | thumb_mode ? *opcode->tvariant : *opcode->avariant), |
13676 | _(BAD_FPU)); | |
5287ad62 | 13677 | |
88714cb8 DG |
13678 | inst.is_neon = 1; |
13679 | ||
037e8744 JB |
13680 | if (thumb_mode) |
13681 | { | |
13682 | inst.instruction = opcode->tvalue; | |
13683 | opcode->tencode (); | |
13684 | } | |
13685 | else | |
13686 | { | |
13687 | inst.instruction = (inst.cond << 28) | opcode->avalue; | |
13688 | opcode->aencode (); | |
13689 | } | |
13690 | } | |
5287ad62 JB |
13691 | |
13692 | static void | |
037e8744 | 13693 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
5287ad62 | 13694 | { |
037e8744 JB |
13695 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
13696 | ||
13697 | if (rs == NS_FFF) | |
13698 | { | |
13699 | if (is_add) | |
477330fc | 13700 | do_vfp_nsyn_opcode ("fadds"); |
037e8744 | 13701 | else |
477330fc | 13702 | do_vfp_nsyn_opcode ("fsubs"); |
037e8744 JB |
13703 | } |
13704 | else | |
13705 | { | |
13706 | if (is_add) | |
477330fc | 13707 | do_vfp_nsyn_opcode ("faddd"); |
037e8744 | 13708 | else |
477330fc | 13709 | do_vfp_nsyn_opcode ("fsubd"); |
037e8744 JB |
13710 | } |
13711 | } | |
13712 | ||
13713 | /* Check operand types to see if this is a VFP instruction, and if so call | |
13714 | PFN (). */ | |
13715 | ||
13716 | static int | |
13717 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) | |
13718 | { | |
13719 | enum neon_shape rs; | |
13720 | struct neon_type_el et; | |
13721 | ||
13722 | switch (args) | |
13723 | { | |
13724 | case 2: | |
13725 | rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
13726 | et = neon_check_type (2, rs, | |
477330fc | 13727 | N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); |
037e8744 | 13728 | break; |
5f4273c7 | 13729 | |
037e8744 JB |
13730 | case 3: |
13731 | rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
13732 | et = neon_check_type (3, rs, | |
477330fc | 13733 | N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); |
037e8744 JB |
13734 | break; |
13735 | ||
13736 | default: | |
13737 | abort (); | |
13738 | } | |
13739 | ||
13740 | if (et.type != NT_invtype) | |
13741 | { | |
13742 | pfn (rs); | |
13743 | return SUCCESS; | |
13744 | } | |
037e8744 | 13745 | |
99b253c5 | 13746 | inst.error = NULL; |
037e8744 JB |
13747 | return FAIL; |
13748 | } | |
13749 | ||
13750 | static void | |
13751 | do_vfp_nsyn_mla_mls (enum neon_shape rs) | |
13752 | { | |
13753 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; | |
5f4273c7 | 13754 | |
037e8744 JB |
13755 | if (rs == NS_FFF) |
13756 | { | |
13757 | if (is_mla) | |
477330fc | 13758 | do_vfp_nsyn_opcode ("fmacs"); |
037e8744 | 13759 | else |
477330fc | 13760 | do_vfp_nsyn_opcode ("fnmacs"); |
037e8744 JB |
13761 | } |
13762 | else | |
13763 | { | |
13764 | if (is_mla) | |
477330fc | 13765 | do_vfp_nsyn_opcode ("fmacd"); |
037e8744 | 13766 | else |
477330fc | 13767 | do_vfp_nsyn_opcode ("fnmacd"); |
037e8744 JB |
13768 | } |
13769 | } | |
13770 | ||
62f3b8c8 PB |
13771 | static void |
13772 | do_vfp_nsyn_fma_fms (enum neon_shape rs) | |
13773 | { | |
13774 | int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma; | |
13775 | ||
13776 | if (rs == NS_FFF) | |
13777 | { | |
13778 | if (is_fma) | |
477330fc | 13779 | do_vfp_nsyn_opcode ("ffmas"); |
62f3b8c8 | 13780 | else |
477330fc | 13781 | do_vfp_nsyn_opcode ("ffnmas"); |
62f3b8c8 PB |
13782 | } |
13783 | else | |
13784 | { | |
13785 | if (is_fma) | |
477330fc | 13786 | do_vfp_nsyn_opcode ("ffmad"); |
62f3b8c8 | 13787 | else |
477330fc | 13788 | do_vfp_nsyn_opcode ("ffnmad"); |
62f3b8c8 PB |
13789 | } |
13790 | } | |
13791 | ||
037e8744 JB |
13792 | static void |
13793 | do_vfp_nsyn_mul (enum neon_shape rs) | |
13794 | { | |
13795 | if (rs == NS_FFF) | |
13796 | do_vfp_nsyn_opcode ("fmuls"); | |
13797 | else | |
13798 | do_vfp_nsyn_opcode ("fmuld"); | |
13799 | } | |
13800 | ||
13801 | static void | |
13802 | do_vfp_nsyn_abs_neg (enum neon_shape rs) | |
13803 | { | |
13804 | int is_neg = (inst.instruction & 0x80) != 0; | |
13805 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); | |
13806 | ||
13807 | if (rs == NS_FF) | |
13808 | { | |
13809 | if (is_neg) | |
477330fc | 13810 | do_vfp_nsyn_opcode ("fnegs"); |
037e8744 | 13811 | else |
477330fc | 13812 | do_vfp_nsyn_opcode ("fabss"); |
037e8744 JB |
13813 | } |
13814 | else | |
13815 | { | |
13816 | if (is_neg) | |
477330fc | 13817 | do_vfp_nsyn_opcode ("fnegd"); |
037e8744 | 13818 | else |
477330fc | 13819 | do_vfp_nsyn_opcode ("fabsd"); |
037e8744 JB |
13820 | } |
13821 | } | |
13822 | ||
13823 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision | |
13824 | insns belong to Neon, and are handled elsewhere. */ | |
13825 | ||
13826 | static void | |
13827 | do_vfp_nsyn_ldm_stm (int is_dbmode) | |
13828 | { | |
13829 | int is_ldm = (inst.instruction & (1 << 20)) != 0; | |
13830 | if (is_ldm) | |
13831 | { | |
13832 | if (is_dbmode) | |
477330fc | 13833 | do_vfp_nsyn_opcode ("fldmdbs"); |
037e8744 | 13834 | else |
477330fc | 13835 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 JB |
13836 | } |
13837 | else | |
13838 | { | |
13839 | if (is_dbmode) | |
477330fc | 13840 | do_vfp_nsyn_opcode ("fstmdbs"); |
037e8744 | 13841 | else |
477330fc | 13842 | do_vfp_nsyn_opcode ("fstmias"); |
037e8744 JB |
13843 | } |
13844 | } | |
13845 | ||
037e8744 JB |
13846 | static void |
13847 | do_vfp_nsyn_sqrt (void) | |
13848 | { | |
13849 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
13850 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13851 | |
037e8744 JB |
13852 | if (rs == NS_FF) |
13853 | do_vfp_nsyn_opcode ("fsqrts"); | |
13854 | else | |
13855 | do_vfp_nsyn_opcode ("fsqrtd"); | |
13856 | } | |
13857 | ||
13858 | static void | |
13859 | do_vfp_nsyn_div (void) | |
13860 | { | |
13861 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
13862 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
13863 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13864 | |
037e8744 JB |
13865 | if (rs == NS_FFF) |
13866 | do_vfp_nsyn_opcode ("fdivs"); | |
13867 | else | |
13868 | do_vfp_nsyn_opcode ("fdivd"); | |
13869 | } | |
13870 | ||
13871 | static void | |
13872 | do_vfp_nsyn_nmul (void) | |
13873 | { | |
13874 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
13875 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
13876 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13877 | |
037e8744 JB |
13878 | if (rs == NS_FFF) |
13879 | { | |
88714cb8 | 13880 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
13881 | do_vfp_sp_dyadic (); |
13882 | } | |
13883 | else | |
13884 | { | |
88714cb8 | 13885 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
13886 | do_vfp_dp_rd_rn_rm (); |
13887 | } | |
13888 | do_vfp_cond_or_thumb (); | |
13889 | } | |
13890 | ||
13891 | static void | |
13892 | do_vfp_nsyn_cmp (void) | |
13893 | { | |
13894 | if (inst.operands[1].isreg) | |
13895 | { | |
13896 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
13897 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13898 | |
037e8744 | 13899 | if (rs == NS_FF) |
477330fc RM |
13900 | { |
13901 | NEON_ENCODE (SINGLE, inst); | |
13902 | do_vfp_sp_monadic (); | |
13903 | } | |
037e8744 | 13904 | else |
477330fc RM |
13905 | { |
13906 | NEON_ENCODE (DOUBLE, inst); | |
13907 | do_vfp_dp_rd_rm (); | |
13908 | } | |
037e8744 JB |
13909 | } |
13910 | else | |
13911 | { | |
13912 | enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); | |
13913 | neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); | |
13914 | ||
13915 | switch (inst.instruction & 0x0fffffff) | |
477330fc RM |
13916 | { |
13917 | case N_MNEM_vcmp: | |
13918 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; | |
13919 | break; | |
13920 | case N_MNEM_vcmpe: | |
13921 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; | |
13922 | break; | |
13923 | default: | |
13924 | abort (); | |
13925 | } | |
5f4273c7 | 13926 | |
037e8744 | 13927 | if (rs == NS_FI) |
477330fc RM |
13928 | { |
13929 | NEON_ENCODE (SINGLE, inst); | |
13930 | do_vfp_sp_compare_z (); | |
13931 | } | |
037e8744 | 13932 | else |
477330fc RM |
13933 | { |
13934 | NEON_ENCODE (DOUBLE, inst); | |
13935 | do_vfp_dp_rd (); | |
13936 | } | |
037e8744 JB |
13937 | } |
13938 | do_vfp_cond_or_thumb (); | |
13939 | } | |
13940 | ||
13941 | static void | |
13942 | nsyn_insert_sp (void) | |
13943 | { | |
13944 | inst.operands[1] = inst.operands[0]; | |
13945 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
fdfde340 | 13946 | inst.operands[0].reg = REG_SP; |
037e8744 JB |
13947 | inst.operands[0].isreg = 1; |
13948 | inst.operands[0].writeback = 1; | |
13949 | inst.operands[0].present = 1; | |
13950 | } | |
13951 | ||
13952 | static void | |
13953 | do_vfp_nsyn_push (void) | |
13954 | { | |
13955 | nsyn_insert_sp (); | |
13956 | if (inst.operands[1].issingle) | |
13957 | do_vfp_nsyn_opcode ("fstmdbs"); | |
13958 | else | |
13959 | do_vfp_nsyn_opcode ("fstmdbd"); | |
13960 | } | |
13961 | ||
13962 | static void | |
13963 | do_vfp_nsyn_pop (void) | |
13964 | { | |
13965 | nsyn_insert_sp (); | |
13966 | if (inst.operands[1].issingle) | |
22b5b651 | 13967 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 | 13968 | else |
22b5b651 | 13969 | do_vfp_nsyn_opcode ("fldmiad"); |
037e8744 JB |
13970 | } |
13971 | ||
13972 | /* Fix up Neon data-processing instructions, ORing in the correct bits for | |
13973 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ | |
13974 | ||
88714cb8 DG |
13975 | static void |
13976 | neon_dp_fixup (struct arm_it* insn) | |
037e8744 | 13977 | { |
88714cb8 DG |
13978 | unsigned int i = insn->instruction; |
13979 | insn->is_neon = 1; | |
13980 | ||
037e8744 JB |
13981 | if (thumb_mode) |
13982 | { | |
13983 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ | |
13984 | if (i & (1 << 24)) | |
477330fc | 13985 | i |= 1 << 28; |
5f4273c7 | 13986 | |
037e8744 | 13987 | i &= ~(1 << 24); |
5f4273c7 | 13988 | |
037e8744 JB |
13989 | i |= 0xef000000; |
13990 | } | |
13991 | else | |
13992 | i |= 0xf2000000; | |
5f4273c7 | 13993 | |
88714cb8 | 13994 | insn->instruction = i; |
037e8744 JB |
13995 | } |
13996 | ||
13997 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 | |
13998 | (0, 1, 2, 3). */ | |
13999 | ||
14000 | static unsigned | |
14001 | neon_logbits (unsigned x) | |
14002 | { | |
14003 | return ffs (x) - 4; | |
14004 | } | |
14005 | ||
14006 | #define LOW4(R) ((R) & 0xf) | |
14007 | #define HI1(R) (((R) >> 4) & 1) | |
14008 | ||
14009 | /* Encode insns with bit pattern: | |
14010 | ||
14011 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
14012 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | | |
5f4273c7 | 14013 | |
037e8744 JB |
14014 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a |
14015 | different meaning for some instruction. */ | |
14016 | ||
14017 | static void | |
14018 | neon_three_same (int isquad, int ubit, int size) | |
14019 | { | |
14020 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14021 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14022 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14023 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14024 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14025 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14026 | inst.instruction |= (isquad != 0) << 6; | |
14027 | inst.instruction |= (ubit != 0) << 24; | |
14028 | if (size != -1) | |
14029 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 14030 | |
88714cb8 | 14031 | neon_dp_fixup (&inst); |
037e8744 JB |
14032 | } |
14033 | ||
14034 | /* Encode instructions of the form: | |
14035 | ||
14036 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| | |
14037 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | | |
5287ad62 JB |
14038 | |
14039 | Don't write size if SIZE == -1. */ | |
14040 | ||
14041 | static void | |
14042 | neon_two_same (int qbit, int ubit, int size) | |
14043 | { | |
14044 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14045 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14046 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14047 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14048 | inst.instruction |= (qbit != 0) << 6; | |
14049 | inst.instruction |= (ubit != 0) << 24; | |
14050 | ||
14051 | if (size != -1) | |
14052 | inst.instruction |= neon_logbits (size) << 18; | |
14053 | ||
88714cb8 | 14054 | neon_dp_fixup (&inst); |
5287ad62 JB |
14055 | } |
14056 | ||
14057 | /* Neon instruction encoders, in approximate order of appearance. */ | |
14058 | ||
14059 | static void | |
14060 | do_neon_dyadic_i_su (void) | |
14061 | { | |
037e8744 | 14062 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14063 | struct neon_type_el et = neon_check_type (3, rs, |
14064 | N_EQK, N_EQK, N_SU_32 | N_KEY); | |
037e8744 | 14065 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14066 | } |
14067 | ||
14068 | static void | |
14069 | do_neon_dyadic_i64_su (void) | |
14070 | { | |
037e8744 | 14071 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14072 | struct neon_type_el et = neon_check_type (3, rs, |
14073 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
037e8744 | 14074 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14075 | } |
14076 | ||
14077 | static void | |
14078 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, | |
477330fc | 14079 | unsigned immbits) |
5287ad62 JB |
14080 | { |
14081 | unsigned size = et.size >> 3; | |
14082 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14083 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14084 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14085 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14086 | inst.instruction |= (isquad != 0) << 6; | |
14087 | inst.instruction |= immbits << 16; | |
14088 | inst.instruction |= (size >> 3) << 7; | |
14089 | inst.instruction |= (size & 0x7) << 19; | |
14090 | if (write_ubit) | |
14091 | inst.instruction |= (uval != 0) << 24; | |
14092 | ||
88714cb8 | 14093 | neon_dp_fixup (&inst); |
5287ad62 JB |
14094 | } |
14095 | ||
14096 | static void | |
14097 | do_neon_shl_imm (void) | |
14098 | { | |
14099 | if (!inst.operands[2].isreg) | |
14100 | { | |
037e8744 | 14101 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 14102 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); |
88714cb8 | 14103 | NEON_ENCODE (IMMED, inst); |
037e8744 | 14104 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); |
5287ad62 JB |
14105 | } |
14106 | else | |
14107 | { | |
037e8744 | 14108 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14109 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14110 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); |
627907b7 JB |
14111 | unsigned int tmp; |
14112 | ||
14113 | /* VSHL/VQSHL 3-register variants have syntax such as: | |
477330fc RM |
14114 | vshl.xx Dd, Dm, Dn |
14115 | whereas other 3-register operations encoded by neon_three_same have | |
14116 | syntax like: | |
14117 | vadd.xx Dd, Dn, Dm | |
14118 | (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg | |
14119 | here. */ | |
627907b7 JB |
14120 | tmp = inst.operands[2].reg; |
14121 | inst.operands[2].reg = inst.operands[1].reg; | |
14122 | inst.operands[1].reg = tmp; | |
88714cb8 | 14123 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14124 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14125 | } |
14126 | } | |
14127 | ||
14128 | static void | |
14129 | do_neon_qshl_imm (void) | |
14130 | { | |
14131 | if (!inst.operands[2].isreg) | |
14132 | { | |
037e8744 | 14133 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 14134 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
627907b7 | 14135 | |
88714cb8 | 14136 | NEON_ENCODE (IMMED, inst); |
037e8744 | 14137 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
477330fc | 14138 | inst.operands[2].imm); |
5287ad62 JB |
14139 | } |
14140 | else | |
14141 | { | |
037e8744 | 14142 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14143 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14144 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); |
627907b7 JB |
14145 | unsigned int tmp; |
14146 | ||
14147 | /* See note in do_neon_shl_imm. */ | |
14148 | tmp = inst.operands[2].reg; | |
14149 | inst.operands[2].reg = inst.operands[1].reg; | |
14150 | inst.operands[1].reg = tmp; | |
88714cb8 | 14151 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14152 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14153 | } |
14154 | } | |
14155 | ||
627907b7 JB |
14156 | static void |
14157 | do_neon_rshl (void) | |
14158 | { | |
14159 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
14160 | struct neon_type_el et = neon_check_type (3, rs, | |
14161 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
14162 | unsigned int tmp; | |
14163 | ||
14164 | tmp = inst.operands[2].reg; | |
14165 | inst.operands[2].reg = inst.operands[1].reg; | |
14166 | inst.operands[1].reg = tmp; | |
14167 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
14168 | } | |
14169 | ||
5287ad62 JB |
14170 | static int |
14171 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) | |
14172 | { | |
036dc3f7 PB |
14173 | /* Handle .I8 pseudo-instructions. */ |
14174 | if (size == 8) | |
5287ad62 | 14175 | { |
5287ad62 | 14176 | /* Unfortunately, this will make everything apart from zero out-of-range. |
477330fc RM |
14177 | FIXME is this the intended semantics? There doesn't seem much point in |
14178 | accepting .I8 if so. */ | |
5287ad62 JB |
14179 | immediate |= immediate << 8; |
14180 | size = 16; | |
036dc3f7 PB |
14181 | } |
14182 | ||
14183 | if (size >= 32) | |
14184 | { | |
14185 | if (immediate == (immediate & 0x000000ff)) | |
14186 | { | |
14187 | *immbits = immediate; | |
14188 | return 0x1; | |
14189 | } | |
14190 | else if (immediate == (immediate & 0x0000ff00)) | |
14191 | { | |
14192 | *immbits = immediate >> 8; | |
14193 | return 0x3; | |
14194 | } | |
14195 | else if (immediate == (immediate & 0x00ff0000)) | |
14196 | { | |
14197 | *immbits = immediate >> 16; | |
14198 | return 0x5; | |
14199 | } | |
14200 | else if (immediate == (immediate & 0xff000000)) | |
14201 | { | |
14202 | *immbits = immediate >> 24; | |
14203 | return 0x7; | |
14204 | } | |
14205 | if ((immediate & 0xffff) != (immediate >> 16)) | |
14206 | goto bad_immediate; | |
14207 | immediate &= 0xffff; | |
5287ad62 JB |
14208 | } |
14209 | ||
14210 | if (immediate == (immediate & 0x000000ff)) | |
14211 | { | |
14212 | *immbits = immediate; | |
036dc3f7 | 14213 | return 0x9; |
5287ad62 JB |
14214 | } |
14215 | else if (immediate == (immediate & 0x0000ff00)) | |
14216 | { | |
14217 | *immbits = immediate >> 8; | |
036dc3f7 | 14218 | return 0xb; |
5287ad62 JB |
14219 | } |
14220 | ||
14221 | bad_immediate: | |
dcbf9037 | 14222 | first_error (_("immediate value out of range")); |
5287ad62 JB |
14223 | return FAIL; |
14224 | } | |
14225 | ||
5287ad62 JB |
14226 | static void |
14227 | do_neon_logic (void) | |
14228 | { | |
14229 | if (inst.operands[2].present && inst.operands[2].isreg) | |
14230 | { | |
037e8744 | 14231 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14232 | neon_check_type (3, rs, N_IGNORE_TYPE); |
14233 | /* U bit and size field were set as part of the bitmask. */ | |
88714cb8 | 14234 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14235 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14236 | } |
14237 | else | |
14238 | { | |
4316f0d2 DG |
14239 | const int three_ops_form = (inst.operands[2].present |
14240 | && !inst.operands[2].isreg); | |
14241 | const int immoperand = (three_ops_form ? 2 : 1); | |
14242 | enum neon_shape rs = (three_ops_form | |
14243 | ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL) | |
14244 | : neon_select_shape (NS_DI, NS_QI, NS_NULL)); | |
037e8744 | 14245 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 14246 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); |
21d799b5 | 14247 | enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff; |
5287ad62 JB |
14248 | unsigned immbits; |
14249 | int cmode; | |
5f4273c7 | 14250 | |
5287ad62 | 14251 | if (et.type == NT_invtype) |
477330fc | 14252 | return; |
5f4273c7 | 14253 | |
4316f0d2 DG |
14254 | if (three_ops_form) |
14255 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
14256 | _("first and second operands shall be the same register")); | |
14257 | ||
88714cb8 | 14258 | NEON_ENCODE (IMMED, inst); |
5287ad62 | 14259 | |
4316f0d2 | 14260 | immbits = inst.operands[immoperand].imm; |
036dc3f7 PB |
14261 | if (et.size == 64) |
14262 | { | |
14263 | /* .i64 is a pseudo-op, so the immediate must be a repeating | |
14264 | pattern. */ | |
4316f0d2 DG |
14265 | if (immbits != (inst.operands[immoperand].regisimm ? |
14266 | inst.operands[immoperand].reg : 0)) | |
036dc3f7 PB |
14267 | { |
14268 | /* Set immbits to an invalid constant. */ | |
14269 | immbits = 0xdeadbeef; | |
14270 | } | |
14271 | } | |
14272 | ||
5287ad62 | 14273 | switch (opcode) |
477330fc RM |
14274 | { |
14275 | case N_MNEM_vbic: | |
14276 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14277 | break; | |
14278 | ||
14279 | case N_MNEM_vorr: | |
14280 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14281 | break; | |
14282 | ||
14283 | case N_MNEM_vand: | |
14284 | /* Pseudo-instruction for VBIC. */ | |
14285 | neon_invert_size (&immbits, 0, et.size); | |
14286 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14287 | break; | |
14288 | ||
14289 | case N_MNEM_vorn: | |
14290 | /* Pseudo-instruction for VORR. */ | |
14291 | neon_invert_size (&immbits, 0, et.size); | |
14292 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14293 | break; | |
14294 | ||
14295 | default: | |
14296 | abort (); | |
14297 | } | |
5287ad62 JB |
14298 | |
14299 | if (cmode == FAIL) | |
477330fc | 14300 | return; |
5287ad62 | 14301 | |
037e8744 | 14302 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14303 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14304 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14305 | inst.instruction |= cmode << 8; | |
14306 | neon_write_immbits (immbits); | |
5f4273c7 | 14307 | |
88714cb8 | 14308 | neon_dp_fixup (&inst); |
5287ad62 JB |
14309 | } |
14310 | } | |
14311 | ||
14312 | static void | |
14313 | do_neon_bitfield (void) | |
14314 | { | |
037e8744 | 14315 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 14316 | neon_check_type (3, rs, N_IGNORE_TYPE); |
037e8744 | 14317 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14318 | } |
14319 | ||
14320 | static void | |
dcbf9037 | 14321 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
477330fc | 14322 | unsigned destbits) |
5287ad62 | 14323 | { |
037e8744 | 14324 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 14325 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
477330fc | 14326 | types | N_KEY); |
5287ad62 JB |
14327 | if (et.type == NT_float) |
14328 | { | |
88714cb8 | 14329 | NEON_ENCODE (FLOAT, inst); |
037e8744 | 14330 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14331 | } |
14332 | else | |
14333 | { | |
88714cb8 | 14334 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14335 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); |
5287ad62 JB |
14336 | } |
14337 | } | |
14338 | ||
14339 | static void | |
14340 | do_neon_dyadic_if_su (void) | |
14341 | { | |
dcbf9037 | 14342 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
14343 | } |
14344 | ||
14345 | static void | |
14346 | do_neon_dyadic_if_su_d (void) | |
14347 | { | |
14348 | /* This version only allow D registers, but that constraint is enforced during | |
14349 | operand parsing so we don't need to do anything extra here. */ | |
dcbf9037 | 14350 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
14351 | } |
14352 | ||
5287ad62 JB |
14353 | static void |
14354 | do_neon_dyadic_if_i_d (void) | |
14355 | { | |
428e3f1f PB |
14356 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
14357 | affected if we specify unsigned args. */ | |
14358 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
5287ad62 JB |
14359 | } |
14360 | ||
037e8744 JB |
14361 | enum vfp_or_neon_is_neon_bits |
14362 | { | |
14363 | NEON_CHECK_CC = 1, | |
73924fbc MGD |
14364 | NEON_CHECK_ARCH = 2, |
14365 | NEON_CHECK_ARCH8 = 4 | |
037e8744 JB |
14366 | }; |
14367 | ||
14368 | /* Call this function if an instruction which may have belonged to the VFP or | |
14369 | Neon instruction sets, but turned out to be a Neon instruction (due to the | |
14370 | operand types involved, etc.). We have to check and/or fix-up a couple of | |
14371 | things: | |
14372 | ||
14373 | - Make sure the user hasn't attempted to make a Neon instruction | |
14374 | conditional. | |
14375 | - Alter the value in the condition code field if necessary. | |
14376 | - Make sure that the arch supports Neon instructions. | |
14377 | ||
14378 | Which of these operations take place depends on bits from enum | |
14379 | vfp_or_neon_is_neon_bits. | |
14380 | ||
14381 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the | |
14382 | current instruction's condition is COND_ALWAYS, the condition field is | |
14383 | changed to inst.uncond_value. This is necessary because instructions shared | |
14384 | between VFP and Neon may be conditional for the VFP variants only, and the | |
14385 | unconditional Neon version must have, e.g., 0xF in the condition field. */ | |
14386 | ||
14387 | static int | |
14388 | vfp_or_neon_is_neon (unsigned check) | |
14389 | { | |
14390 | /* Conditions are always legal in Thumb mode (IT blocks). */ | |
14391 | if (!thumb_mode && (check & NEON_CHECK_CC)) | |
14392 | { | |
14393 | if (inst.cond != COND_ALWAYS) | |
477330fc RM |
14394 | { |
14395 | first_error (_(BAD_COND)); | |
14396 | return FAIL; | |
14397 | } | |
037e8744 | 14398 | if (inst.uncond_value != -1) |
477330fc | 14399 | inst.instruction |= inst.uncond_value << 28; |
037e8744 | 14400 | } |
5f4273c7 | 14401 | |
037e8744 | 14402 | if ((check & NEON_CHECK_ARCH) |
73924fbc MGD |
14403 | && !mark_feature_used (&fpu_neon_ext_v1)) |
14404 | { | |
14405 | first_error (_(BAD_FPU)); | |
14406 | return FAIL; | |
14407 | } | |
14408 | ||
14409 | if ((check & NEON_CHECK_ARCH8) | |
14410 | && !mark_feature_used (&fpu_neon_ext_armv8)) | |
037e8744 JB |
14411 | { |
14412 | first_error (_(BAD_FPU)); | |
14413 | return FAIL; | |
14414 | } | |
5f4273c7 | 14415 | |
037e8744 JB |
14416 | return SUCCESS; |
14417 | } | |
14418 | ||
5287ad62 JB |
14419 | static void |
14420 | do_neon_addsub_if_i (void) | |
14421 | { | |
037e8744 JB |
14422 | if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) |
14423 | return; | |
14424 | ||
14425 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14426 | return; | |
14427 | ||
5287ad62 JB |
14428 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
14429 | affected if we specify unsigned args. */ | |
dcbf9037 | 14430 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
5287ad62 JB |
14431 | } |
14432 | ||
14433 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the | |
14434 | result to be: | |
14435 | V<op> A,B (A is operand 0, B is operand 2) | |
14436 | to mean: | |
14437 | V<op> A,B,A | |
14438 | not: | |
14439 | V<op> A,B,B | |
14440 | so handle that case specially. */ | |
14441 | ||
14442 | static void | |
14443 | neon_exchange_operands (void) | |
14444 | { | |
14445 | void *scratch = alloca (sizeof (inst.operands[0])); | |
14446 | if (inst.operands[1].present) | |
14447 | { | |
14448 | /* Swap operands[1] and operands[2]. */ | |
14449 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); | |
14450 | inst.operands[1] = inst.operands[2]; | |
14451 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); | |
14452 | } | |
14453 | else | |
14454 | { | |
14455 | inst.operands[1] = inst.operands[2]; | |
14456 | inst.operands[2] = inst.operands[0]; | |
14457 | } | |
14458 | } | |
14459 | ||
14460 | static void | |
14461 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) | |
14462 | { | |
14463 | if (inst.operands[2].isreg) | |
14464 | { | |
14465 | if (invert) | |
477330fc | 14466 | neon_exchange_operands (); |
dcbf9037 | 14467 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
5287ad62 JB |
14468 | } |
14469 | else | |
14470 | { | |
037e8744 | 14471 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
dcbf9037 | 14472 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 14473 | N_EQK | N_SIZ, immtypes | N_KEY); |
5287ad62 | 14474 | |
88714cb8 | 14475 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14476 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14477 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14478 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14479 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14480 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14481 | inst.instruction |= (et.type == NT_float) << 10; |
14482 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14483 | |
88714cb8 | 14484 | neon_dp_fixup (&inst); |
5287ad62 JB |
14485 | } |
14486 | } | |
14487 | ||
14488 | static void | |
14489 | do_neon_cmp (void) | |
14490 | { | |
14491 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); | |
14492 | } | |
14493 | ||
14494 | static void | |
14495 | do_neon_cmp_inv (void) | |
14496 | { | |
14497 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); | |
14498 | } | |
14499 | ||
14500 | static void | |
14501 | do_neon_ceq (void) | |
14502 | { | |
14503 | neon_compare (N_IF_32, N_IF_32, FALSE); | |
14504 | } | |
14505 | ||
14506 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit | |
14507 | scalars, which are encoded in 5 bits, M : Rm. | |
14508 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in | |
14509 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the | |
14510 | index in M. */ | |
14511 | ||
14512 | static unsigned | |
14513 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) | |
14514 | { | |
dcbf9037 JB |
14515 | unsigned regno = NEON_SCALAR_REG (scalar); |
14516 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
5287ad62 JB |
14517 | |
14518 | switch (elsize) | |
14519 | { | |
14520 | case 16: | |
14521 | if (regno > 7 || elno > 3) | |
477330fc | 14522 | goto bad_scalar; |
5287ad62 | 14523 | return regno | (elno << 3); |
5f4273c7 | 14524 | |
5287ad62 JB |
14525 | case 32: |
14526 | if (regno > 15 || elno > 1) | |
477330fc | 14527 | goto bad_scalar; |
5287ad62 JB |
14528 | return regno | (elno << 4); |
14529 | ||
14530 | default: | |
14531 | bad_scalar: | |
dcbf9037 | 14532 | first_error (_("scalar out of range for multiply instruction")); |
5287ad62 JB |
14533 | } |
14534 | ||
14535 | return 0; | |
14536 | } | |
14537 | ||
14538 | /* Encode multiply / multiply-accumulate scalar instructions. */ | |
14539 | ||
14540 | static void | |
14541 | neon_mul_mac (struct neon_type_el et, int ubit) | |
14542 | { | |
dcbf9037 JB |
14543 | unsigned scalar; |
14544 | ||
14545 | /* Give a more helpful error message if we have an invalid type. */ | |
14546 | if (et.type == NT_invtype) | |
14547 | return; | |
5f4273c7 | 14548 | |
dcbf9037 | 14549 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); |
5287ad62 JB |
14550 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14551 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14552 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14553 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14554 | inst.instruction |= LOW4 (scalar); | |
14555 | inst.instruction |= HI1 (scalar) << 5; | |
14556 | inst.instruction |= (et.type == NT_float) << 8; | |
14557 | inst.instruction |= neon_logbits (et.size) << 20; | |
14558 | inst.instruction |= (ubit != 0) << 24; | |
14559 | ||
88714cb8 | 14560 | neon_dp_fixup (&inst); |
5287ad62 JB |
14561 | } |
14562 | ||
14563 | static void | |
14564 | do_neon_mac_maybe_scalar (void) | |
14565 | { | |
037e8744 JB |
14566 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
14567 | return; | |
14568 | ||
14569 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14570 | return; | |
14571 | ||
5287ad62 JB |
14572 | if (inst.operands[2].isscalar) |
14573 | { | |
037e8744 | 14574 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 | 14575 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14576 | N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); |
88714cb8 | 14577 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 14578 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
14579 | } |
14580 | else | |
428e3f1f PB |
14581 | { |
14582 | /* The "untyped" case can't happen. Do this to stop the "U" bit being | |
14583 | affected if we specify unsigned args. */ | |
14584 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
14585 | } | |
5287ad62 JB |
14586 | } |
14587 | ||
62f3b8c8 PB |
14588 | static void |
14589 | do_neon_fmac (void) | |
14590 | { | |
14591 | if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS) | |
14592 | return; | |
14593 | ||
14594 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14595 | return; | |
14596 | ||
14597 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
14598 | } | |
14599 | ||
5287ad62 JB |
14600 | static void |
14601 | do_neon_tst (void) | |
14602 | { | |
037e8744 | 14603 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14604 | struct neon_type_el et = neon_check_type (3, rs, |
14605 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
037e8744 | 14606 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
14607 | } |
14608 | ||
14609 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the | |
14610 | same types as the MAC equivalents. The polynomial type for this instruction | |
14611 | is encoded the same as the integer type. */ | |
14612 | ||
14613 | static void | |
14614 | do_neon_mul (void) | |
14615 | { | |
037e8744 JB |
14616 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
14617 | return; | |
14618 | ||
14619 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14620 | return; | |
14621 | ||
5287ad62 JB |
14622 | if (inst.operands[2].isscalar) |
14623 | do_neon_mac_maybe_scalar (); | |
14624 | else | |
dcbf9037 | 14625 | neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); |
5287ad62 JB |
14626 | } |
14627 | ||
14628 | static void | |
14629 | do_neon_qdmulh (void) | |
14630 | { | |
14631 | if (inst.operands[2].isscalar) | |
14632 | { | |
037e8744 | 14633 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 | 14634 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14635 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); |
88714cb8 | 14636 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 14637 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
14638 | } |
14639 | else | |
14640 | { | |
037e8744 | 14641 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14642 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14643 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); |
88714cb8 | 14644 | NEON_ENCODE (INTEGER, inst); |
5287ad62 | 14645 | /* The U bit (rounding) comes from bit mask. */ |
037e8744 | 14646 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
14647 | } |
14648 | } | |
14649 | ||
14650 | static void | |
14651 | do_neon_fcmp_absolute (void) | |
14652 | { | |
037e8744 | 14653 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14654 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
14655 | /* Size field comes from bit mask. */ | |
037e8744 | 14656 | neon_three_same (neon_quad (rs), 1, -1); |
5287ad62 JB |
14657 | } |
14658 | ||
14659 | static void | |
14660 | do_neon_fcmp_absolute_inv (void) | |
14661 | { | |
14662 | neon_exchange_operands (); | |
14663 | do_neon_fcmp_absolute (); | |
14664 | } | |
14665 | ||
14666 | static void | |
14667 | do_neon_step (void) | |
14668 | { | |
037e8744 | 14669 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14670 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
037e8744 | 14671 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14672 | } |
14673 | ||
14674 | static void | |
14675 | do_neon_abs_neg (void) | |
14676 | { | |
037e8744 JB |
14677 | enum neon_shape rs; |
14678 | struct neon_type_el et; | |
5f4273c7 | 14679 | |
037e8744 JB |
14680 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) |
14681 | return; | |
14682 | ||
14683 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14684 | return; | |
14685 | ||
14686 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
14687 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); | |
5f4273c7 | 14688 | |
5287ad62 JB |
14689 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14690 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14691 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14692 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14693 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14694 | inst.instruction |= (et.type == NT_float) << 10; |
14695 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14696 | |
88714cb8 | 14697 | neon_dp_fixup (&inst); |
5287ad62 JB |
14698 | } |
14699 | ||
14700 | static void | |
14701 | do_neon_sli (void) | |
14702 | { | |
037e8744 | 14703 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14704 | struct neon_type_el et = neon_check_type (2, rs, |
14705 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14706 | int imm = inst.operands[2].imm; | |
14707 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
477330fc | 14708 | _("immediate out of range for insert")); |
037e8744 | 14709 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14710 | } |
14711 | ||
14712 | static void | |
14713 | do_neon_sri (void) | |
14714 | { | |
037e8744 | 14715 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14716 | struct neon_type_el et = neon_check_type (2, rs, |
14717 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14718 | int imm = inst.operands[2].imm; | |
14719 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 14720 | _("immediate out of range for insert")); |
037e8744 | 14721 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
5287ad62 JB |
14722 | } |
14723 | ||
14724 | static void | |
14725 | do_neon_qshlu_imm (void) | |
14726 | { | |
037e8744 | 14727 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14728 | struct neon_type_el et = neon_check_type (2, rs, |
14729 | N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); | |
14730 | int imm = inst.operands[2].imm; | |
14731 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
477330fc | 14732 | _("immediate out of range for shift")); |
5287ad62 JB |
14733 | /* Only encodes the 'U present' variant of the instruction. |
14734 | In this case, signed types have OP (bit 8) set to 0. | |
14735 | Unsigned types have OP set to 1. */ | |
14736 | inst.instruction |= (et.type == NT_unsigned) << 8; | |
14737 | /* The rest of the bits are the same as other immediate shifts. */ | |
037e8744 | 14738 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14739 | } |
14740 | ||
14741 | static void | |
14742 | do_neon_qmovn (void) | |
14743 | { | |
14744 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14745 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
14746 | /* Saturating move where operands can be signed or unsigned, and the | |
14747 | destination has the same signedness. */ | |
88714cb8 | 14748 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14749 | if (et.type == NT_unsigned) |
14750 | inst.instruction |= 0xc0; | |
14751 | else | |
14752 | inst.instruction |= 0x80; | |
14753 | neon_two_same (0, 1, et.size / 2); | |
14754 | } | |
14755 | ||
14756 | static void | |
14757 | do_neon_qmovun (void) | |
14758 | { | |
14759 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14760 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
14761 | /* Saturating move with unsigned results. Operands must be signed. */ | |
88714cb8 | 14762 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14763 | neon_two_same (0, 1, et.size / 2); |
14764 | } | |
14765 | ||
14766 | static void | |
14767 | do_neon_rshift_sat_narrow (void) | |
14768 | { | |
14769 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
14770 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
14771 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14772 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
14773 | int imm = inst.operands[2].imm; | |
14774 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14775 | right. */ | |
14776 | et.size /= 2; | |
5f4273c7 | 14777 | |
5287ad62 JB |
14778 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for |
14779 | VQMOVN.I<size> <Dd>, <Qm>. */ | |
14780 | if (imm == 0) | |
14781 | { | |
14782 | inst.operands[2].present = 0; | |
14783 | inst.instruction = N_MNEM_vqmovn; | |
14784 | do_neon_qmovn (); | |
14785 | return; | |
14786 | } | |
5f4273c7 | 14787 | |
5287ad62 | 14788 | constraint (imm < 1 || (unsigned)imm > et.size, |
477330fc | 14789 | _("immediate out of range")); |
5287ad62 JB |
14790 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); |
14791 | } | |
14792 | ||
14793 | static void | |
14794 | do_neon_rshift_sat_narrow_u (void) | |
14795 | { | |
14796 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
14797 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
14798 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14799 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
14800 | int imm = inst.operands[2].imm; | |
14801 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14802 | right. */ | |
14803 | et.size /= 2; | |
14804 | ||
14805 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
14806 | VQMOVUN.I<size> <Dd>, <Qm>. */ | |
14807 | if (imm == 0) | |
14808 | { | |
14809 | inst.operands[2].present = 0; | |
14810 | inst.instruction = N_MNEM_vqmovun; | |
14811 | do_neon_qmovun (); | |
14812 | return; | |
14813 | } | |
14814 | ||
14815 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 14816 | _("immediate out of range")); |
5287ad62 JB |
14817 | /* FIXME: The manual is kind of unclear about what value U should have in |
14818 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it | |
14819 | must be 1. */ | |
14820 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); | |
14821 | } | |
14822 | ||
14823 | static void | |
14824 | do_neon_movn (void) | |
14825 | { | |
14826 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14827 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
88714cb8 | 14828 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14829 | neon_two_same (0, 1, et.size / 2); |
14830 | } | |
14831 | ||
14832 | static void | |
14833 | do_neon_rshift_narrow (void) | |
14834 | { | |
14835 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14836 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
14837 | int imm = inst.operands[2].imm; | |
14838 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14839 | right. */ | |
14840 | et.size /= 2; | |
5f4273c7 | 14841 | |
5287ad62 JB |
14842 | /* If immediate is zero then we are a pseudo-instruction for |
14843 | VMOVN.I<size> <Dd>, <Qm> */ | |
14844 | if (imm == 0) | |
14845 | { | |
14846 | inst.operands[2].present = 0; | |
14847 | inst.instruction = N_MNEM_vmovn; | |
14848 | do_neon_movn (); | |
14849 | return; | |
14850 | } | |
5f4273c7 | 14851 | |
5287ad62 | 14852 | constraint (imm < 1 || (unsigned)imm > et.size, |
477330fc | 14853 | _("immediate out of range for narrowing operation")); |
5287ad62 JB |
14854 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); |
14855 | } | |
14856 | ||
14857 | static void | |
14858 | do_neon_shll (void) | |
14859 | { | |
14860 | /* FIXME: Type checking when lengthening. */ | |
14861 | struct neon_type_el et = neon_check_type (2, NS_QDI, | |
14862 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); | |
14863 | unsigned imm = inst.operands[2].imm; | |
14864 | ||
14865 | if (imm == et.size) | |
14866 | { | |
14867 | /* Maximum shift variant. */ | |
88714cb8 | 14868 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14869 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14870 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14871 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14872 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14873 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14874 | |
88714cb8 | 14875 | neon_dp_fixup (&inst); |
5287ad62 JB |
14876 | } |
14877 | else | |
14878 | { | |
14879 | /* A more-specific type check for non-max versions. */ | |
14880 | et = neon_check_type (2, NS_QDI, | |
477330fc | 14881 | N_EQK | N_DBL, N_SU_32 | N_KEY); |
88714cb8 | 14882 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14883 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); |
14884 | } | |
14885 | } | |
14886 | ||
037e8744 | 14887 | /* Check the various types for the VCVT instruction, and return which version |
5287ad62 JB |
14888 | the current instruction is. */ |
14889 | ||
6b9a8b67 MGD |
14890 | #define CVT_FLAVOUR_VAR \ |
14891 | CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \ | |
14892 | CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \ | |
14893 | CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \ | |
14894 | CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \ | |
14895 | /* Half-precision conversions. */ \ | |
14896 | CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \ | |
14897 | CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \ | |
14898 | /* VFP instructions. */ \ | |
14899 | CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \ | |
14900 | CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \ | |
14901 | CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \ | |
14902 | CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \ | |
14903 | CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \ | |
14904 | CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \ | |
14905 | /* VFP instructions with bitshift. */ \ | |
14906 | CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \ | |
14907 | CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \ | |
14908 | CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \ | |
14909 | CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \ | |
14910 | CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \ | |
14911 | CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \ | |
14912 | CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \ | |
14913 | CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL) | |
14914 | ||
14915 | #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \ | |
14916 | neon_cvt_flavour_##C, | |
14917 | ||
14918 | /* The different types of conversions we can do. */ | |
14919 | enum neon_cvt_flavour | |
14920 | { | |
14921 | CVT_FLAVOUR_VAR | |
14922 | neon_cvt_flavour_invalid, | |
14923 | neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64 | |
14924 | }; | |
14925 | ||
14926 | #undef CVT_VAR | |
14927 | ||
14928 | static enum neon_cvt_flavour | |
14929 | get_neon_cvt_flavour (enum neon_shape rs) | |
5287ad62 | 14930 | { |
6b9a8b67 MGD |
14931 | #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \ |
14932 | et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \ | |
14933 | if (et.type != NT_invtype) \ | |
14934 | { \ | |
14935 | inst.error = NULL; \ | |
14936 | return (neon_cvt_flavour_##C); \ | |
5287ad62 | 14937 | } |
6b9a8b67 | 14938 | |
5287ad62 | 14939 | struct neon_type_el et; |
037e8744 | 14940 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
477330fc | 14941 | || rs == NS_FF) ? N_VFP : 0; |
037e8744 JB |
14942 | /* The instruction versions which take an immediate take one register |
14943 | argument, which is extended to the width of the full register. Thus the | |
14944 | "source" and "destination" registers must have the same width. Hack that | |
14945 | here by making the size equal to the key (wider, in this case) operand. */ | |
14946 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; | |
5f4273c7 | 14947 | |
6b9a8b67 MGD |
14948 | CVT_FLAVOUR_VAR; |
14949 | ||
14950 | return neon_cvt_flavour_invalid; | |
5287ad62 JB |
14951 | #undef CVT_VAR |
14952 | } | |
14953 | ||
7e8e6784 MGD |
14954 | enum neon_cvt_mode |
14955 | { | |
14956 | neon_cvt_mode_a, | |
14957 | neon_cvt_mode_n, | |
14958 | neon_cvt_mode_p, | |
14959 | neon_cvt_mode_m, | |
14960 | neon_cvt_mode_z, | |
30bdf752 MGD |
14961 | neon_cvt_mode_x, |
14962 | neon_cvt_mode_r | |
7e8e6784 MGD |
14963 | }; |
14964 | ||
037e8744 JB |
14965 | /* Neon-syntax VFP conversions. */ |
14966 | ||
5287ad62 | 14967 | static void |
6b9a8b67 | 14968 | do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour) |
5287ad62 | 14969 | { |
037e8744 | 14970 | const char *opname = 0; |
5f4273c7 | 14971 | |
037e8744 | 14972 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) |
5287ad62 | 14973 | { |
037e8744 JB |
14974 | /* Conversions with immediate bitshift. */ |
14975 | const char *enc[] = | |
477330fc | 14976 | { |
6b9a8b67 MGD |
14977 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN, |
14978 | CVT_FLAVOUR_VAR | |
14979 | NULL | |
14980 | #undef CVT_VAR | |
477330fc | 14981 | }; |
037e8744 | 14982 | |
6b9a8b67 | 14983 | if (flavour < (int) ARRAY_SIZE (enc)) |
477330fc RM |
14984 | { |
14985 | opname = enc[flavour]; | |
14986 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
14987 | _("operands 0 and 1 must be the same register")); | |
14988 | inst.operands[1] = inst.operands[2]; | |
14989 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); | |
14990 | } | |
5287ad62 JB |
14991 | } |
14992 | else | |
14993 | { | |
037e8744 JB |
14994 | /* Conversions without bitshift. */ |
14995 | const char *enc[] = | |
477330fc | 14996 | { |
6b9a8b67 MGD |
14997 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN, |
14998 | CVT_FLAVOUR_VAR | |
14999 | NULL | |
15000 | #undef CVT_VAR | |
477330fc | 15001 | }; |
037e8744 | 15002 | |
6b9a8b67 | 15003 | if (flavour < (int) ARRAY_SIZE (enc)) |
477330fc | 15004 | opname = enc[flavour]; |
037e8744 JB |
15005 | } |
15006 | ||
15007 | if (opname) | |
15008 | do_vfp_nsyn_opcode (opname); | |
15009 | } | |
15010 | ||
15011 | static void | |
15012 | do_vfp_nsyn_cvtz (void) | |
15013 | { | |
15014 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); | |
6b9a8b67 | 15015 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); |
037e8744 JB |
15016 | const char *enc[] = |
15017 | { | |
6b9a8b67 MGD |
15018 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN, |
15019 | CVT_FLAVOUR_VAR | |
15020 | NULL | |
15021 | #undef CVT_VAR | |
037e8744 JB |
15022 | }; |
15023 | ||
6b9a8b67 | 15024 | if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) |
037e8744 JB |
15025 | do_vfp_nsyn_opcode (enc[flavour]); |
15026 | } | |
f31fef98 | 15027 | |
037e8744 | 15028 | static void |
bacebabc | 15029 | do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour, |
7e8e6784 MGD |
15030 | enum neon_cvt_mode mode) |
15031 | { | |
15032 | int sz, op; | |
15033 | int rm; | |
15034 | ||
15035 | set_it_insn_type (OUTSIDE_IT_INSN); | |
15036 | ||
15037 | switch (flavour) | |
15038 | { | |
15039 | case neon_cvt_flavour_s32_f64: | |
15040 | sz = 1; | |
827f64ff | 15041 | op = 1; |
7e8e6784 MGD |
15042 | break; |
15043 | case neon_cvt_flavour_s32_f32: | |
15044 | sz = 0; | |
15045 | op = 1; | |
15046 | break; | |
15047 | case neon_cvt_flavour_u32_f64: | |
15048 | sz = 1; | |
15049 | op = 0; | |
15050 | break; | |
15051 | case neon_cvt_flavour_u32_f32: | |
15052 | sz = 0; | |
15053 | op = 0; | |
15054 | break; | |
15055 | default: | |
15056 | first_error (_("invalid instruction shape")); | |
15057 | return; | |
15058 | } | |
15059 | ||
15060 | switch (mode) | |
15061 | { | |
15062 | case neon_cvt_mode_a: rm = 0; break; | |
15063 | case neon_cvt_mode_n: rm = 1; break; | |
15064 | case neon_cvt_mode_p: rm = 2; break; | |
15065 | case neon_cvt_mode_m: rm = 3; break; | |
15066 | default: first_error (_("invalid rounding mode")); return; | |
15067 | } | |
15068 | ||
15069 | NEON_ENCODE (FPV8, inst); | |
15070 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
15071 | encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm); | |
15072 | inst.instruction |= sz << 8; | |
15073 | inst.instruction |= op << 7; | |
15074 | inst.instruction |= rm << 16; | |
15075 | inst.instruction |= 0xf0000000; | |
15076 | inst.is_neon = TRUE; | |
15077 | } | |
15078 | ||
15079 | static void | |
15080 | do_neon_cvt_1 (enum neon_cvt_mode mode) | |
037e8744 JB |
15081 | { |
15082 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, | |
8e79c3df | 15083 | NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL); |
6b9a8b67 | 15084 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); |
037e8744 | 15085 | |
e3e535bc | 15086 | /* PR11109: Handle round-to-zero for VCVT conversions. */ |
7e8e6784 | 15087 | if (mode == neon_cvt_mode_z |
e3e535bc | 15088 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2) |
bacebabc RM |
15089 | && (flavour == neon_cvt_flavour_s32_f32 |
15090 | || flavour == neon_cvt_flavour_u32_f32 | |
15091 | || flavour == neon_cvt_flavour_s32_f64 | |
6b9a8b67 | 15092 | || flavour == neon_cvt_flavour_u32_f64) |
e3e535bc NC |
15093 | && (rs == NS_FD || rs == NS_FF)) |
15094 | { | |
15095 | do_vfp_nsyn_cvtz (); | |
15096 | return; | |
15097 | } | |
15098 | ||
037e8744 | 15099 | /* VFP rather than Neon conversions. */ |
6b9a8b67 | 15100 | if (flavour >= neon_cvt_flavour_first_fp) |
037e8744 | 15101 | { |
7e8e6784 MGD |
15102 | if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z) |
15103 | do_vfp_nsyn_cvt (rs, flavour); | |
15104 | else | |
15105 | do_vfp_nsyn_cvt_fpv8 (flavour, mode); | |
15106 | ||
037e8744 JB |
15107 | return; |
15108 | } | |
15109 | ||
15110 | switch (rs) | |
15111 | { | |
15112 | case NS_DDI: | |
15113 | case NS_QQI: | |
15114 | { | |
477330fc RM |
15115 | unsigned immbits; |
15116 | unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; | |
35997600 | 15117 | |
477330fc RM |
15118 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
15119 | return; | |
037e8744 | 15120 | |
477330fc RM |
15121 | /* Fixed-point conversion with #0 immediate is encoded as an |
15122 | integer conversion. */ | |
15123 | if (inst.operands[2].present && inst.operands[2].imm == 0) | |
15124 | goto int_encode; | |
35997600 | 15125 | immbits = 32 - inst.operands[2].imm; |
477330fc RM |
15126 | NEON_ENCODE (IMMED, inst); |
15127 | if (flavour != neon_cvt_flavour_invalid) | |
15128 | inst.instruction |= enctab[flavour]; | |
15129 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15130 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15131 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15132 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15133 | inst.instruction |= neon_quad (rs) << 6; | |
15134 | inst.instruction |= 1 << 21; | |
15135 | inst.instruction |= immbits << 16; | |
15136 | ||
15137 | neon_dp_fixup (&inst); | |
037e8744 JB |
15138 | } |
15139 | break; | |
15140 | ||
15141 | case NS_DD: | |
15142 | case NS_QQ: | |
7e8e6784 MGD |
15143 | if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z) |
15144 | { | |
15145 | NEON_ENCODE (FLOAT, inst); | |
15146 | set_it_insn_type (OUTSIDE_IT_INSN); | |
15147 | ||
15148 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) | |
15149 | return; | |
15150 | ||
15151 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15152 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15153 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15154 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15155 | inst.instruction |= neon_quad (rs) << 6; | |
15156 | inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7; | |
15157 | inst.instruction |= mode << 8; | |
15158 | if (thumb_mode) | |
15159 | inst.instruction |= 0xfc000000; | |
15160 | else | |
15161 | inst.instruction |= 0xf0000000; | |
15162 | } | |
15163 | else | |
15164 | { | |
037e8744 | 15165 | int_encode: |
7e8e6784 MGD |
15166 | { |
15167 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; | |
037e8744 | 15168 | |
7e8e6784 | 15169 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 15170 | |
7e8e6784 MGD |
15171 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
15172 | return; | |
037e8744 | 15173 | |
7e8e6784 MGD |
15174 | if (flavour != neon_cvt_flavour_invalid) |
15175 | inst.instruction |= enctab[flavour]; | |
037e8744 | 15176 | |
7e8e6784 MGD |
15177 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15178 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15179 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15180 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15181 | inst.instruction |= neon_quad (rs) << 6; | |
15182 | inst.instruction |= 2 << 18; | |
037e8744 | 15183 | |
7e8e6784 MGD |
15184 | neon_dp_fixup (&inst); |
15185 | } | |
15186 | } | |
15187 | break; | |
037e8744 | 15188 | |
8e79c3df CM |
15189 | /* Half-precision conversions for Advanced SIMD -- neon. */ |
15190 | case NS_QD: | |
15191 | case NS_DQ: | |
15192 | ||
15193 | if ((rs == NS_DQ) | |
15194 | && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) | |
15195 | { | |
15196 | as_bad (_("operand size must match register width")); | |
15197 | break; | |
15198 | } | |
15199 | ||
15200 | if ((rs == NS_QD) | |
15201 | && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) | |
15202 | { | |
15203 | as_bad (_("operand size must match register width")); | |
15204 | break; | |
15205 | } | |
15206 | ||
15207 | if (rs == NS_DQ) | |
477330fc | 15208 | inst.instruction = 0x3b60600; |
8e79c3df CM |
15209 | else |
15210 | inst.instruction = 0x3b60700; | |
15211 | ||
15212 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15213 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15214 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15215 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
88714cb8 | 15216 | neon_dp_fixup (&inst); |
8e79c3df CM |
15217 | break; |
15218 | ||
037e8744 JB |
15219 | default: |
15220 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ | |
7e8e6784 MGD |
15221 | if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z) |
15222 | do_vfp_nsyn_cvt (rs, flavour); | |
15223 | else | |
15224 | do_vfp_nsyn_cvt_fpv8 (flavour, mode); | |
5287ad62 | 15225 | } |
5287ad62 JB |
15226 | } |
15227 | ||
e3e535bc NC |
15228 | static void |
15229 | do_neon_cvtr (void) | |
15230 | { | |
7e8e6784 | 15231 | do_neon_cvt_1 (neon_cvt_mode_x); |
e3e535bc NC |
15232 | } |
15233 | ||
15234 | static void | |
15235 | do_neon_cvt (void) | |
15236 | { | |
7e8e6784 MGD |
15237 | do_neon_cvt_1 (neon_cvt_mode_z); |
15238 | } | |
15239 | ||
15240 | static void | |
15241 | do_neon_cvta (void) | |
15242 | { | |
15243 | do_neon_cvt_1 (neon_cvt_mode_a); | |
15244 | } | |
15245 | ||
15246 | static void | |
15247 | do_neon_cvtn (void) | |
15248 | { | |
15249 | do_neon_cvt_1 (neon_cvt_mode_n); | |
15250 | } | |
15251 | ||
15252 | static void | |
15253 | do_neon_cvtp (void) | |
15254 | { | |
15255 | do_neon_cvt_1 (neon_cvt_mode_p); | |
15256 | } | |
15257 | ||
15258 | static void | |
15259 | do_neon_cvtm (void) | |
15260 | { | |
15261 | do_neon_cvt_1 (neon_cvt_mode_m); | |
e3e535bc NC |
15262 | } |
15263 | ||
8e79c3df | 15264 | static void |
c70a8987 | 15265 | do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double) |
8e79c3df | 15266 | { |
c70a8987 MGD |
15267 | if (is_double) |
15268 | mark_feature_used (&fpu_vfp_ext_armv8); | |
8e79c3df | 15269 | |
c70a8987 MGD |
15270 | encode_arm_vfp_reg (inst.operands[0].reg, |
15271 | (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd); | |
15272 | encode_arm_vfp_reg (inst.operands[1].reg, | |
15273 | (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm); | |
15274 | inst.instruction |= to ? 0x10000 : 0; | |
15275 | inst.instruction |= t ? 0x80 : 0; | |
15276 | inst.instruction |= is_double ? 0x100 : 0; | |
15277 | do_vfp_cond_or_thumb (); | |
15278 | } | |
8e79c3df | 15279 | |
c70a8987 MGD |
15280 | static void |
15281 | do_neon_cvttb_1 (bfd_boolean t) | |
15282 | { | |
15283 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL); | |
8e79c3df | 15284 | |
c70a8987 MGD |
15285 | if (rs == NS_NULL) |
15286 | return; | |
15287 | else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype) | |
15288 | { | |
15289 | inst.error = NULL; | |
15290 | do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE); | |
15291 | } | |
15292 | else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype) | |
15293 | { | |
15294 | inst.error = NULL; | |
15295 | do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE); | |
15296 | } | |
15297 | else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype) | |
15298 | { | |
15299 | inst.error = NULL; | |
15300 | do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE); | |
15301 | } | |
15302 | else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype) | |
15303 | { | |
15304 | inst.error = NULL; | |
15305 | do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE); | |
15306 | } | |
15307 | else | |
15308 | return; | |
15309 | } | |
15310 | ||
15311 | static void | |
15312 | do_neon_cvtb (void) | |
15313 | { | |
15314 | do_neon_cvttb_1 (FALSE); | |
8e79c3df CM |
15315 | } |
15316 | ||
15317 | ||
15318 | static void | |
15319 | do_neon_cvtt (void) | |
15320 | { | |
c70a8987 | 15321 | do_neon_cvttb_1 (TRUE); |
8e79c3df CM |
15322 | } |
15323 | ||
5287ad62 JB |
15324 | static void |
15325 | neon_move_immediate (void) | |
15326 | { | |
037e8744 JB |
15327 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
15328 | struct neon_type_el et = neon_check_type (2, rs, | |
15329 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 | 15330 | unsigned immlo, immhi = 0, immbits; |
c96612cc | 15331 | int op, cmode, float_p; |
5287ad62 | 15332 | |
037e8744 | 15333 | constraint (et.type == NT_invtype, |
477330fc | 15334 | _("operand size must be specified for immediate VMOV")); |
037e8744 | 15335 | |
5287ad62 JB |
15336 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
15337 | op = (inst.instruction & (1 << 5)) != 0; | |
15338 | ||
15339 | immlo = inst.operands[1].imm; | |
15340 | if (inst.operands[1].regisimm) | |
15341 | immhi = inst.operands[1].reg; | |
15342 | ||
15343 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, | |
477330fc | 15344 | _("immediate has bits set outside the operand size")); |
5287ad62 | 15345 | |
c96612cc JB |
15346 | float_p = inst.operands[1].immisfloat; |
15347 | ||
15348 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, | |
477330fc | 15349 | et.size, et.type)) == FAIL) |
5287ad62 JB |
15350 | { |
15351 | /* Invert relevant bits only. */ | |
15352 | neon_invert_size (&immlo, &immhi, et.size); | |
15353 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable | |
477330fc RM |
15354 | with one or the other; those cases are caught by |
15355 | neon_cmode_for_move_imm. */ | |
5287ad62 | 15356 | op = !op; |
c96612cc JB |
15357 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, |
15358 | &op, et.size, et.type)) == FAIL) | |
477330fc RM |
15359 | { |
15360 | first_error (_("immediate out of range")); | |
15361 | return; | |
15362 | } | |
5287ad62 JB |
15363 | } |
15364 | ||
15365 | inst.instruction &= ~(1 << 5); | |
15366 | inst.instruction |= op << 5; | |
15367 | ||
15368 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15369 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
037e8744 | 15370 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
15371 | inst.instruction |= cmode << 8; |
15372 | ||
15373 | neon_write_immbits (immbits); | |
15374 | } | |
15375 | ||
15376 | static void | |
15377 | do_neon_mvn (void) | |
15378 | { | |
15379 | if (inst.operands[1].isreg) | |
15380 | { | |
037e8744 | 15381 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5f4273c7 | 15382 | |
88714cb8 | 15383 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
15384 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15385 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15386 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15387 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 15388 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
15389 | } |
15390 | else | |
15391 | { | |
88714cb8 | 15392 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
15393 | neon_move_immediate (); |
15394 | } | |
15395 | ||
88714cb8 | 15396 | neon_dp_fixup (&inst); |
5287ad62 JB |
15397 | } |
15398 | ||
15399 | /* Encode instructions of form: | |
15400 | ||
15401 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
5f4273c7 | 15402 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ |
5287ad62 JB |
15403 | |
15404 | static void | |
15405 | neon_mixed_length (struct neon_type_el et, unsigned size) | |
15406 | { | |
15407 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15408 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15409 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15410 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15411 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15412 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15413 | inst.instruction |= (et.type == NT_unsigned) << 24; | |
15414 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 15415 | |
88714cb8 | 15416 | neon_dp_fixup (&inst); |
5287ad62 JB |
15417 | } |
15418 | ||
15419 | static void | |
15420 | do_neon_dyadic_long (void) | |
15421 | { | |
15422 | /* FIXME: Type checking for lengthening op. */ | |
15423 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
15424 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
15425 | neon_mixed_length (et, et.size); | |
15426 | } | |
15427 | ||
15428 | static void | |
15429 | do_neon_abal (void) | |
15430 | { | |
15431 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
15432 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
15433 | neon_mixed_length (et, et.size); | |
15434 | } | |
15435 | ||
15436 | static void | |
15437 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) | |
15438 | { | |
15439 | if (inst.operands[2].isscalar) | |
15440 | { | |
dcbf9037 | 15441 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
477330fc | 15442 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); |
88714cb8 | 15443 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
15444 | neon_mul_mac (et, et.type == NT_unsigned); |
15445 | } | |
15446 | else | |
15447 | { | |
15448 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
477330fc | 15449 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); |
88714cb8 | 15450 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
15451 | neon_mixed_length (et, et.size); |
15452 | } | |
15453 | } | |
15454 | ||
15455 | static void | |
15456 | do_neon_mac_maybe_scalar_long (void) | |
15457 | { | |
15458 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); | |
15459 | } | |
15460 | ||
15461 | static void | |
15462 | do_neon_dyadic_wide (void) | |
15463 | { | |
15464 | struct neon_type_el et = neon_check_type (3, NS_QQD, | |
15465 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); | |
15466 | neon_mixed_length (et, et.size); | |
15467 | } | |
15468 | ||
15469 | static void | |
15470 | do_neon_dyadic_narrow (void) | |
15471 | { | |
15472 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
15473 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); | |
428e3f1f PB |
15474 | /* Operand sign is unimportant, and the U bit is part of the opcode, |
15475 | so force the operand type to integer. */ | |
15476 | et.type = NT_integer; | |
5287ad62 JB |
15477 | neon_mixed_length (et, et.size / 2); |
15478 | } | |
15479 | ||
15480 | static void | |
15481 | do_neon_mul_sat_scalar_long (void) | |
15482 | { | |
15483 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); | |
15484 | } | |
15485 | ||
15486 | static void | |
15487 | do_neon_vmull (void) | |
15488 | { | |
15489 | if (inst.operands[2].isscalar) | |
15490 | do_neon_mac_maybe_scalar_long (); | |
15491 | else | |
15492 | { | |
15493 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
477330fc | 15494 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY); |
4f51b4bd | 15495 | |
5287ad62 | 15496 | if (et.type == NT_poly) |
477330fc | 15497 | NEON_ENCODE (POLY, inst); |
5287ad62 | 15498 | else |
477330fc | 15499 | NEON_ENCODE (INTEGER, inst); |
4f51b4bd MGD |
15500 | |
15501 | /* For polynomial encoding the U bit must be zero, and the size must | |
15502 | be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non | |
15503 | obviously, as 0b10). */ | |
15504 | if (et.size == 64) | |
15505 | { | |
15506 | /* Check we're on the correct architecture. */ | |
15507 | if (!mark_feature_used (&fpu_crypto_ext_armv8)) | |
15508 | inst.error = | |
15509 | _("Instruction form not available on this architecture."); | |
15510 | ||
15511 | et.size = 32; | |
15512 | } | |
15513 | ||
5287ad62 JB |
15514 | neon_mixed_length (et, et.size); |
15515 | } | |
15516 | } | |
15517 | ||
15518 | static void | |
15519 | do_neon_ext (void) | |
15520 | { | |
037e8744 | 15521 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
5287ad62 JB |
15522 | struct neon_type_el et = neon_check_type (3, rs, |
15523 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
15524 | unsigned imm = (inst.operands[3].imm * et.size) / 8; | |
35997600 NC |
15525 | |
15526 | constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), | |
15527 | _("shift out of range")); | |
5287ad62 JB |
15528 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15529 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15530 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15531 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15532 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15533 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
037e8744 | 15534 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 | 15535 | inst.instruction |= imm << 8; |
5f4273c7 | 15536 | |
88714cb8 | 15537 | neon_dp_fixup (&inst); |
5287ad62 JB |
15538 | } |
15539 | ||
15540 | static void | |
15541 | do_neon_rev (void) | |
15542 | { | |
037e8744 | 15543 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15544 | struct neon_type_el et = neon_check_type (2, rs, |
15545 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
15546 | unsigned op = (inst.instruction >> 7) & 3; | |
15547 | /* N (width of reversed regions) is encoded as part of the bitmask. We | |
15548 | extract it here to check the elements to be reversed are smaller. | |
15549 | Otherwise we'd get a reserved instruction. */ | |
15550 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; | |
9c2799c2 | 15551 | gas_assert (elsize != 0); |
5287ad62 | 15552 | constraint (et.size >= elsize, |
477330fc | 15553 | _("elements must be smaller than reversal region")); |
037e8744 | 15554 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15555 | } |
15556 | ||
15557 | static void | |
15558 | do_neon_dup (void) | |
15559 | { | |
15560 | if (inst.operands[1].isscalar) | |
15561 | { | |
037e8744 | 15562 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
dcbf9037 | 15563 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 15564 | N_EQK, N_8 | N_16 | N_32 | N_KEY); |
5287ad62 | 15565 | unsigned sizebits = et.size >> 3; |
dcbf9037 | 15566 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
5287ad62 | 15567 | int logsize = neon_logbits (et.size); |
dcbf9037 | 15568 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
037e8744 JB |
15569 | |
15570 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) | |
477330fc | 15571 | return; |
037e8744 | 15572 | |
88714cb8 | 15573 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
15574 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15575 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15576 | inst.instruction |= LOW4 (dm); | |
15577 | inst.instruction |= HI1 (dm) << 5; | |
037e8744 | 15578 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
15579 | inst.instruction |= x << 17; |
15580 | inst.instruction |= sizebits << 16; | |
5f4273c7 | 15581 | |
88714cb8 | 15582 | neon_dp_fixup (&inst); |
5287ad62 JB |
15583 | } |
15584 | else | |
15585 | { | |
037e8744 JB |
15586 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
15587 | struct neon_type_el et = neon_check_type (2, rs, | |
477330fc | 15588 | N_8 | N_16 | N_32 | N_KEY, N_EQK); |
5287ad62 | 15589 | /* Duplicate ARM register to lanes of vector. */ |
88714cb8 | 15590 | NEON_ENCODE (ARMREG, inst); |
5287ad62 | 15591 | switch (et.size) |
477330fc RM |
15592 | { |
15593 | case 8: inst.instruction |= 0x400000; break; | |
15594 | case 16: inst.instruction |= 0x000020; break; | |
15595 | case 32: inst.instruction |= 0x000000; break; | |
15596 | default: break; | |
15597 | } | |
5287ad62 JB |
15598 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; |
15599 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; | |
15600 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; | |
037e8744 | 15601 | inst.instruction |= neon_quad (rs) << 21; |
5287ad62 | 15602 | /* The encoding for this instruction is identical for the ARM and Thumb |
477330fc | 15603 | variants, except for the condition field. */ |
037e8744 | 15604 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
15605 | } |
15606 | } | |
15607 | ||
15608 | /* VMOV has particularly many variations. It can be one of: | |
15609 | 0. VMOV<c><q> <Qd>, <Qm> | |
15610 | 1. VMOV<c><q> <Dd>, <Dm> | |
15611 | (Register operations, which are VORR with Rm = Rn.) | |
15612 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> | |
15613 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> | |
15614 | (Immediate loads.) | |
15615 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> | |
15616 | (ARM register to scalar.) | |
15617 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> | |
15618 | (Two ARM registers to vector.) | |
15619 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> | |
15620 | (Scalar to ARM register.) | |
15621 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> | |
15622 | (Vector to two ARM registers.) | |
037e8744 JB |
15623 | 8. VMOV.F32 <Sd>, <Sm> |
15624 | 9. VMOV.F64 <Dd>, <Dm> | |
15625 | (VFP register moves.) | |
15626 | 10. VMOV.F32 <Sd>, #imm | |
15627 | 11. VMOV.F64 <Dd>, #imm | |
15628 | (VFP float immediate load.) | |
15629 | 12. VMOV <Rd>, <Sm> | |
15630 | (VFP single to ARM reg.) | |
15631 | 13. VMOV <Sd>, <Rm> | |
15632 | (ARM reg to VFP single.) | |
15633 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> | |
15634 | (Two ARM regs to two VFP singles.) | |
15635 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> | |
15636 | (Two VFP singles to two ARM regs.) | |
5f4273c7 | 15637 | |
037e8744 JB |
15638 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
15639 | and 3/11 which depend on the operand type too. | |
5f4273c7 | 15640 | |
5287ad62 | 15641 | All the encoded bits are hardcoded by this function. |
5f4273c7 | 15642 | |
b7fc2769 JB |
15643 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
15644 | Cases 5, 7 may be used with VFPv2 and above. | |
5f4273c7 | 15645 | |
5287ad62 | 15646 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
5f4273c7 | 15647 | can specify a type where it doesn't make sense to, and is ignored). */ |
5287ad62 JB |
15648 | |
15649 | static void | |
15650 | do_neon_mov (void) | |
15651 | { | |
037e8744 JB |
15652 | enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, |
15653 | NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, | |
15654 | NS_NULL); | |
15655 | struct neon_type_el et; | |
15656 | const char *ldconst = 0; | |
5287ad62 | 15657 | |
037e8744 | 15658 | switch (rs) |
5287ad62 | 15659 | { |
037e8744 JB |
15660 | case NS_DD: /* case 1/9. */ |
15661 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
15662 | /* It is not an error here if no type is given. */ | |
15663 | inst.error = NULL; | |
15664 | if (et.type == NT_float && et.size == 64) | |
477330fc RM |
15665 | { |
15666 | do_vfp_nsyn_opcode ("fcpyd"); | |
15667 | break; | |
15668 | } | |
037e8744 | 15669 | /* fall through. */ |
5287ad62 | 15670 | |
037e8744 JB |
15671 | case NS_QQ: /* case 0/1. */ |
15672 | { | |
477330fc RM |
15673 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
15674 | return; | |
15675 | /* The architecture manual I have doesn't explicitly state which | |
15676 | value the U bit should have for register->register moves, but | |
15677 | the equivalent VORR instruction has U = 0, so do that. */ | |
15678 | inst.instruction = 0x0200110; | |
15679 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15680 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15681 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15682 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15683 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15684 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15685 | inst.instruction |= neon_quad (rs) << 6; | |
15686 | ||
15687 | neon_dp_fixup (&inst); | |
037e8744 JB |
15688 | } |
15689 | break; | |
5f4273c7 | 15690 | |
037e8744 JB |
15691 | case NS_DI: /* case 3/11. */ |
15692 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
15693 | inst.error = NULL; | |
15694 | if (et.type == NT_float && et.size == 64) | |
477330fc RM |
15695 | { |
15696 | /* case 11 (fconstd). */ | |
15697 | ldconst = "fconstd"; | |
15698 | goto encode_fconstd; | |
15699 | } | |
037e8744 JB |
15700 | /* fall through. */ |
15701 | ||
15702 | case NS_QI: /* case 2/3. */ | |
15703 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
477330fc | 15704 | return; |
037e8744 JB |
15705 | inst.instruction = 0x0800010; |
15706 | neon_move_immediate (); | |
88714cb8 | 15707 | neon_dp_fixup (&inst); |
5287ad62 | 15708 | break; |
5f4273c7 | 15709 | |
037e8744 JB |
15710 | case NS_SR: /* case 4. */ |
15711 | { | |
477330fc RM |
15712 | unsigned bcdebits = 0; |
15713 | int logsize; | |
15714 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); | |
15715 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); | |
037e8744 | 15716 | |
05ac0ffb JB |
15717 | /* .<size> is optional here, defaulting to .32. */ |
15718 | if (inst.vectype.elems == 0 | |
15719 | && inst.operands[0].vectype.type == NT_invtype | |
15720 | && inst.operands[1].vectype.type == NT_invtype) | |
15721 | { | |
15722 | inst.vectype.el[0].type = NT_untyped; | |
15723 | inst.vectype.el[0].size = 32; | |
15724 | inst.vectype.elems = 1; | |
15725 | } | |
15726 | ||
477330fc RM |
15727 | et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK); |
15728 | logsize = neon_logbits (et.size); | |
15729 | ||
15730 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), | |
15731 | _(BAD_FPU)); | |
15732 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
15733 | && et.size != 32, _(BAD_FPU)); | |
15734 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
15735 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
15736 | ||
15737 | switch (et.size) | |
15738 | { | |
15739 | case 8: bcdebits = 0x8; break; | |
15740 | case 16: bcdebits = 0x1; break; | |
15741 | case 32: bcdebits = 0x0; break; | |
15742 | default: ; | |
15743 | } | |
15744 | ||
15745 | bcdebits |= x << logsize; | |
15746 | ||
15747 | inst.instruction = 0xe000b10; | |
15748 | do_vfp_cond_or_thumb (); | |
15749 | inst.instruction |= LOW4 (dn) << 16; | |
15750 | inst.instruction |= HI1 (dn) << 7; | |
15751 | inst.instruction |= inst.operands[1].reg << 12; | |
15752 | inst.instruction |= (bcdebits & 3) << 5; | |
15753 | inst.instruction |= (bcdebits >> 2) << 21; | |
037e8744 JB |
15754 | } |
15755 | break; | |
5f4273c7 | 15756 | |
037e8744 | 15757 | case NS_DRR: /* case 5 (fmdrr). */ |
b7fc2769 | 15758 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), |
477330fc | 15759 | _(BAD_FPU)); |
b7fc2769 | 15760 | |
037e8744 JB |
15761 | inst.instruction = 0xc400b10; |
15762 | do_vfp_cond_or_thumb (); | |
15763 | inst.instruction |= LOW4 (inst.operands[0].reg); | |
15764 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; | |
15765 | inst.instruction |= inst.operands[1].reg << 12; | |
15766 | inst.instruction |= inst.operands[2].reg << 16; | |
15767 | break; | |
5f4273c7 | 15768 | |
037e8744 JB |
15769 | case NS_RS: /* case 6. */ |
15770 | { | |
477330fc RM |
15771 | unsigned logsize; |
15772 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); | |
15773 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); | |
15774 | unsigned abcdebits = 0; | |
037e8744 | 15775 | |
05ac0ffb JB |
15776 | /* .<dt> is optional here, defaulting to .32. */ |
15777 | if (inst.vectype.elems == 0 | |
15778 | && inst.operands[0].vectype.type == NT_invtype | |
15779 | && inst.operands[1].vectype.type == NT_invtype) | |
15780 | { | |
15781 | inst.vectype.el[0].type = NT_untyped; | |
15782 | inst.vectype.el[0].size = 32; | |
15783 | inst.vectype.elems = 1; | |
15784 | } | |
15785 | ||
91d6fa6a NC |
15786 | et = neon_check_type (2, NS_NULL, |
15787 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); | |
477330fc RM |
15788 | logsize = neon_logbits (et.size); |
15789 | ||
15790 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), | |
15791 | _(BAD_FPU)); | |
15792 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
15793 | && et.size != 32, _(BAD_FPU)); | |
15794 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
15795 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
15796 | ||
15797 | switch (et.size) | |
15798 | { | |
15799 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; | |
15800 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; | |
15801 | case 32: abcdebits = 0x00; break; | |
15802 | default: ; | |
15803 | } | |
15804 | ||
15805 | abcdebits |= x << logsize; | |
15806 | inst.instruction = 0xe100b10; | |
15807 | do_vfp_cond_or_thumb (); | |
15808 | inst.instruction |= LOW4 (dn) << 16; | |
15809 | inst.instruction |= HI1 (dn) << 7; | |
15810 | inst.instruction |= inst.operands[0].reg << 12; | |
15811 | inst.instruction |= (abcdebits & 3) << 5; | |
15812 | inst.instruction |= (abcdebits >> 2) << 21; | |
037e8744 JB |
15813 | } |
15814 | break; | |
5f4273c7 | 15815 | |
037e8744 JB |
15816 | case NS_RRD: /* case 7 (fmrrd). */ |
15817 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), | |
477330fc | 15818 | _(BAD_FPU)); |
037e8744 JB |
15819 | |
15820 | inst.instruction = 0xc500b10; | |
15821 | do_vfp_cond_or_thumb (); | |
15822 | inst.instruction |= inst.operands[0].reg << 12; | |
15823 | inst.instruction |= inst.operands[1].reg << 16; | |
15824 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15825 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15826 | break; | |
5f4273c7 | 15827 | |
037e8744 JB |
15828 | case NS_FF: /* case 8 (fcpys). */ |
15829 | do_vfp_nsyn_opcode ("fcpys"); | |
15830 | break; | |
5f4273c7 | 15831 | |
037e8744 JB |
15832 | case NS_FI: /* case 10 (fconsts). */ |
15833 | ldconst = "fconsts"; | |
15834 | encode_fconstd: | |
15835 | if (is_quarter_float (inst.operands[1].imm)) | |
477330fc RM |
15836 | { |
15837 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); | |
15838 | do_vfp_nsyn_opcode (ldconst); | |
15839 | } | |
5287ad62 | 15840 | else |
477330fc | 15841 | first_error (_("immediate out of range")); |
037e8744 | 15842 | break; |
5f4273c7 | 15843 | |
037e8744 JB |
15844 | case NS_RF: /* case 12 (fmrs). */ |
15845 | do_vfp_nsyn_opcode ("fmrs"); | |
15846 | break; | |
5f4273c7 | 15847 | |
037e8744 JB |
15848 | case NS_FR: /* case 13 (fmsr). */ |
15849 | do_vfp_nsyn_opcode ("fmsr"); | |
15850 | break; | |
5f4273c7 | 15851 | |
037e8744 JB |
15852 | /* The encoders for the fmrrs and fmsrr instructions expect three operands |
15853 | (one of which is a list), but we have parsed four. Do some fiddling to | |
15854 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 | |
15855 | expect. */ | |
15856 | case NS_RRFF: /* case 14 (fmrrs). */ | |
15857 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, | |
477330fc | 15858 | _("VFP registers must be adjacent")); |
037e8744 JB |
15859 | inst.operands[2].imm = 2; |
15860 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
15861 | do_vfp_nsyn_opcode ("fmrrs"); | |
15862 | break; | |
5f4273c7 | 15863 | |
037e8744 JB |
15864 | case NS_FFRR: /* case 15 (fmsrr). */ |
15865 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, | |
477330fc | 15866 | _("VFP registers must be adjacent")); |
037e8744 JB |
15867 | inst.operands[1] = inst.operands[2]; |
15868 | inst.operands[2] = inst.operands[3]; | |
15869 | inst.operands[0].imm = 2; | |
15870 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
15871 | do_vfp_nsyn_opcode ("fmsrr"); | |
5287ad62 | 15872 | break; |
5f4273c7 | 15873 | |
4c261dff NC |
15874 | case NS_NULL: |
15875 | /* neon_select_shape has determined that the instruction | |
15876 | shape is wrong and has already set the error message. */ | |
15877 | break; | |
15878 | ||
5287ad62 JB |
15879 | default: |
15880 | abort (); | |
15881 | } | |
15882 | } | |
15883 | ||
15884 | static void | |
15885 | do_neon_rshift_round_imm (void) | |
15886 | { | |
037e8744 | 15887 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
15888 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
15889 | int imm = inst.operands[2].imm; | |
15890 | ||
15891 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ | |
15892 | if (imm == 0) | |
15893 | { | |
15894 | inst.operands[2].present = 0; | |
15895 | do_neon_mov (); | |
15896 | return; | |
15897 | } | |
15898 | ||
15899 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 15900 | _("immediate out of range for shift")); |
037e8744 | 15901 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
477330fc | 15902 | et.size - imm); |
5287ad62 JB |
15903 | } |
15904 | ||
15905 | static void | |
15906 | do_neon_movl (void) | |
15907 | { | |
15908 | struct neon_type_el et = neon_check_type (2, NS_QD, | |
15909 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
15910 | unsigned sizebits = et.size >> 3; | |
15911 | inst.instruction |= sizebits << 19; | |
15912 | neon_two_same (0, et.type == NT_unsigned, -1); | |
15913 | } | |
15914 | ||
15915 | static void | |
15916 | do_neon_trn (void) | |
15917 | { | |
037e8744 | 15918 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15919 | struct neon_type_el et = neon_check_type (2, rs, |
15920 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
88714cb8 | 15921 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 15922 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15923 | } |
15924 | ||
15925 | static void | |
15926 | do_neon_zip_uzp (void) | |
15927 | { | |
037e8744 | 15928 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15929 | struct neon_type_el et = neon_check_type (2, rs, |
15930 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
15931 | if (rs == NS_DD && et.size == 32) | |
15932 | { | |
15933 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ | |
15934 | inst.instruction = N_MNEM_vtrn; | |
15935 | do_neon_trn (); | |
15936 | return; | |
15937 | } | |
037e8744 | 15938 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15939 | } |
15940 | ||
15941 | static void | |
15942 | do_neon_sat_abs_neg (void) | |
15943 | { | |
037e8744 | 15944 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15945 | struct neon_type_el et = neon_check_type (2, rs, |
15946 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 15947 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15948 | } |
15949 | ||
15950 | static void | |
15951 | do_neon_pair_long (void) | |
15952 | { | |
037e8744 | 15953 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15954 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
15955 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ | |
15956 | inst.instruction |= (et.type == NT_unsigned) << 7; | |
037e8744 | 15957 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15958 | } |
15959 | ||
15960 | static void | |
15961 | do_neon_recip_est (void) | |
15962 | { | |
037e8744 | 15963 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15964 | struct neon_type_el et = neon_check_type (2, rs, |
15965 | N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); | |
15966 | inst.instruction |= (et.type == NT_float) << 8; | |
037e8744 | 15967 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15968 | } |
15969 | ||
15970 | static void | |
15971 | do_neon_cls (void) | |
15972 | { | |
037e8744 | 15973 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15974 | struct neon_type_el et = neon_check_type (2, rs, |
15975 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 15976 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15977 | } |
15978 | ||
15979 | static void | |
15980 | do_neon_clz (void) | |
15981 | { | |
037e8744 | 15982 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15983 | struct neon_type_el et = neon_check_type (2, rs, |
15984 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); | |
037e8744 | 15985 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15986 | } |
15987 | ||
15988 | static void | |
15989 | do_neon_cnt (void) | |
15990 | { | |
037e8744 | 15991 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15992 | struct neon_type_el et = neon_check_type (2, rs, |
15993 | N_EQK | N_INT, N_8 | N_KEY); | |
037e8744 | 15994 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15995 | } |
15996 | ||
15997 | static void | |
15998 | do_neon_swp (void) | |
15999 | { | |
037e8744 JB |
16000 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
16001 | neon_two_same (neon_quad (rs), 1, -1); | |
5287ad62 JB |
16002 | } |
16003 | ||
16004 | static void | |
16005 | do_neon_tbl_tbx (void) | |
16006 | { | |
16007 | unsigned listlenbits; | |
dcbf9037 | 16008 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
5f4273c7 | 16009 | |
5287ad62 JB |
16010 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) |
16011 | { | |
dcbf9037 | 16012 | first_error (_("bad list length for table lookup")); |
5287ad62 JB |
16013 | return; |
16014 | } | |
5f4273c7 | 16015 | |
5287ad62 JB |
16016 | listlenbits = inst.operands[1].imm - 1; |
16017 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16018 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16019 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16020 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16021 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16022 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16023 | inst.instruction |= listlenbits << 8; | |
5f4273c7 | 16024 | |
88714cb8 | 16025 | neon_dp_fixup (&inst); |
5287ad62 JB |
16026 | } |
16027 | ||
16028 | static void | |
16029 | do_neon_ldm_stm (void) | |
16030 | { | |
16031 | /* P, U and L bits are part of bitmask. */ | |
16032 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; | |
16033 | unsigned offsetbits = inst.operands[1].imm * 2; | |
16034 | ||
037e8744 JB |
16035 | if (inst.operands[1].issingle) |
16036 | { | |
16037 | do_vfp_nsyn_ldm_stm (is_dbmode); | |
16038 | return; | |
16039 | } | |
16040 | ||
5287ad62 | 16041 | constraint (is_dbmode && !inst.operands[0].writeback, |
477330fc | 16042 | _("writeback (!) must be used for VLDMDB and VSTMDB")); |
5287ad62 JB |
16043 | |
16044 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
477330fc RM |
16045 | _("register list must contain at least 1 and at most 16 " |
16046 | "registers")); | |
5287ad62 JB |
16047 | |
16048 | inst.instruction |= inst.operands[0].reg << 16; | |
16049 | inst.instruction |= inst.operands[0].writeback << 21; | |
16050 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
16051 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; | |
16052 | ||
16053 | inst.instruction |= offsetbits; | |
5f4273c7 | 16054 | |
037e8744 | 16055 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
16056 | } |
16057 | ||
16058 | static void | |
16059 | do_neon_ldr_str (void) | |
16060 | { | |
5287ad62 | 16061 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
5f4273c7 | 16062 | |
6844b2c2 MGD |
16063 | /* Use of PC in vstr in ARM mode is deprecated in ARMv7. |
16064 | And is UNPREDICTABLE in thumb mode. */ | |
fa94de6b | 16065 | if (!is_ldr |
6844b2c2 | 16066 | && inst.operands[1].reg == REG_PC |
ba86b375 | 16067 | && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode)) |
6844b2c2 | 16068 | { |
94dcf8bf | 16069 | if (thumb_mode) |
6844b2c2 | 16070 | inst.error = _("Use of PC here is UNPREDICTABLE"); |
94dcf8bf JB |
16071 | else if (warn_on_deprecated) |
16072 | as_warn (_("Use of PC here is deprecated")); | |
6844b2c2 MGD |
16073 | } |
16074 | ||
037e8744 JB |
16075 | if (inst.operands[0].issingle) |
16076 | { | |
cd2f129f | 16077 | if (is_ldr) |
477330fc | 16078 | do_vfp_nsyn_opcode ("flds"); |
cd2f129f | 16079 | else |
477330fc | 16080 | do_vfp_nsyn_opcode ("fsts"); |
5287ad62 JB |
16081 | } |
16082 | else | |
5287ad62 | 16083 | { |
cd2f129f | 16084 | if (is_ldr) |
477330fc | 16085 | do_vfp_nsyn_opcode ("fldd"); |
5287ad62 | 16086 | else |
477330fc | 16087 | do_vfp_nsyn_opcode ("fstd"); |
5287ad62 | 16088 | } |
5287ad62 JB |
16089 | } |
16090 | ||
16091 | /* "interleave" version also handles non-interleaving register VLD1/VST1 | |
16092 | instructions. */ | |
16093 | ||
16094 | static void | |
16095 | do_neon_ld_st_interleave (void) | |
16096 | { | |
037e8744 | 16097 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
477330fc | 16098 | N_8 | N_16 | N_32 | N_64); |
5287ad62 JB |
16099 | unsigned alignbits = 0; |
16100 | unsigned idx; | |
16101 | /* The bits in this table go: | |
16102 | 0: register stride of one (0) or two (1) | |
16103 | 1,2: register list length, minus one (1, 2, 3, 4). | |
16104 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). | |
16105 | We use -1 for invalid entries. */ | |
16106 | const int typetable[] = | |
16107 | { | |
16108 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ | |
16109 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ | |
16110 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ | |
16111 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ | |
16112 | }; | |
16113 | int typebits; | |
16114 | ||
dcbf9037 JB |
16115 | if (et.type == NT_invtype) |
16116 | return; | |
16117 | ||
5287ad62 JB |
16118 | if (inst.operands[1].immisalign) |
16119 | switch (inst.operands[1].imm >> 8) | |
16120 | { | |
16121 | case 64: alignbits = 1; break; | |
16122 | case 128: | |
477330fc | 16123 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2 |
e23c0ad8 | 16124 | && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
477330fc RM |
16125 | goto bad_alignment; |
16126 | alignbits = 2; | |
16127 | break; | |
5287ad62 | 16128 | case 256: |
477330fc RM |
16129 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
16130 | goto bad_alignment; | |
16131 | alignbits = 3; | |
16132 | break; | |
5287ad62 JB |
16133 | default: |
16134 | bad_alignment: | |
477330fc RM |
16135 | first_error (_("bad alignment")); |
16136 | return; | |
5287ad62 JB |
16137 | } |
16138 | ||
16139 | inst.instruction |= alignbits << 4; | |
16140 | inst.instruction |= neon_logbits (et.size) << 6; | |
16141 | ||
16142 | /* Bits [4:6] of the immediate in a list specifier encode register stride | |
16143 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of | |
16144 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look | |
16145 | up the right value for "type" in a table based on this value and the given | |
16146 | list style, then stick it back. */ | |
16147 | idx = ((inst.operands[0].imm >> 4) & 7) | |
477330fc | 16148 | | (((inst.instruction >> 8) & 3) << 3); |
5287ad62 JB |
16149 | |
16150 | typebits = typetable[idx]; | |
5f4273c7 | 16151 | |
5287ad62 | 16152 | constraint (typebits == -1, _("bad list type for instruction")); |
1d50d57c WN |
16153 | constraint (((inst.instruction >> 8) & 3) && et.size == 64, |
16154 | _("bad element type for instruction")); | |
5287ad62 JB |
16155 | |
16156 | inst.instruction &= ~0xf00; | |
16157 | inst.instruction |= typebits << 8; | |
16158 | } | |
16159 | ||
16160 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. | |
16161 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 | |
16162 | otherwise. The variable arguments are a list of pairs of legal (size, align) | |
16163 | values, terminated with -1. */ | |
16164 | ||
16165 | static int | |
16166 | neon_alignment_bit (int size, int align, int *do_align, ...) | |
16167 | { | |
16168 | va_list ap; | |
16169 | int result = FAIL, thissize, thisalign; | |
5f4273c7 | 16170 | |
5287ad62 JB |
16171 | if (!inst.operands[1].immisalign) |
16172 | { | |
16173 | *do_align = 0; | |
16174 | return SUCCESS; | |
16175 | } | |
5f4273c7 | 16176 | |
5287ad62 JB |
16177 | va_start (ap, do_align); |
16178 | ||
16179 | do | |
16180 | { | |
16181 | thissize = va_arg (ap, int); | |
16182 | if (thissize == -1) | |
477330fc | 16183 | break; |
5287ad62 JB |
16184 | thisalign = va_arg (ap, int); |
16185 | ||
16186 | if (size == thissize && align == thisalign) | |
477330fc | 16187 | result = SUCCESS; |
5287ad62 JB |
16188 | } |
16189 | while (result != SUCCESS); | |
16190 | ||
16191 | va_end (ap); | |
16192 | ||
16193 | if (result == SUCCESS) | |
16194 | *do_align = 1; | |
16195 | else | |
dcbf9037 | 16196 | first_error (_("unsupported alignment for instruction")); |
5f4273c7 | 16197 | |
5287ad62 JB |
16198 | return result; |
16199 | } | |
16200 | ||
16201 | static void | |
16202 | do_neon_ld_st_lane (void) | |
16203 | { | |
037e8744 | 16204 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
16205 | int align_good, do_align = 0; |
16206 | int logsize = neon_logbits (et.size); | |
16207 | int align = inst.operands[1].imm >> 8; | |
16208 | int n = (inst.instruction >> 8) & 3; | |
16209 | int max_el = 64 / et.size; | |
5f4273c7 | 16210 | |
dcbf9037 JB |
16211 | if (et.type == NT_invtype) |
16212 | return; | |
5f4273c7 | 16213 | |
5287ad62 | 16214 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
477330fc | 16215 | _("bad list length")); |
5287ad62 | 16216 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, |
477330fc | 16217 | _("scalar index out of range")); |
5287ad62 | 16218 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 |
477330fc RM |
16219 | && et.size == 8, |
16220 | _("stride of 2 unavailable when element size is 8")); | |
5f4273c7 | 16221 | |
5287ad62 JB |
16222 | switch (n) |
16223 | { | |
16224 | case 0: /* VLD1 / VST1. */ | |
16225 | align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, | |
477330fc | 16226 | 32, 32, -1); |
5287ad62 | 16227 | if (align_good == FAIL) |
477330fc | 16228 | return; |
5287ad62 | 16229 | if (do_align) |
477330fc RM |
16230 | { |
16231 | unsigned alignbits = 0; | |
16232 | switch (et.size) | |
16233 | { | |
16234 | case 16: alignbits = 0x1; break; | |
16235 | case 32: alignbits = 0x3; break; | |
16236 | default: ; | |
16237 | } | |
16238 | inst.instruction |= alignbits << 4; | |
16239 | } | |
5287ad62 JB |
16240 | break; |
16241 | ||
16242 | case 1: /* VLD2 / VST2. */ | |
16243 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, | |
477330fc | 16244 | 32, 64, -1); |
5287ad62 | 16245 | if (align_good == FAIL) |
477330fc | 16246 | return; |
5287ad62 | 16247 | if (do_align) |
477330fc | 16248 | inst.instruction |= 1 << 4; |
5287ad62 JB |
16249 | break; |
16250 | ||
16251 | case 2: /* VLD3 / VST3. */ | |
16252 | constraint (inst.operands[1].immisalign, | |
477330fc | 16253 | _("can't use alignment with this instruction")); |
5287ad62 JB |
16254 | break; |
16255 | ||
16256 | case 3: /* VLD4 / VST4. */ | |
16257 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
477330fc | 16258 | 16, 64, 32, 64, 32, 128, -1); |
5287ad62 | 16259 | if (align_good == FAIL) |
477330fc | 16260 | return; |
5287ad62 | 16261 | if (do_align) |
477330fc RM |
16262 | { |
16263 | unsigned alignbits = 0; | |
16264 | switch (et.size) | |
16265 | { | |
16266 | case 8: alignbits = 0x1; break; | |
16267 | case 16: alignbits = 0x1; break; | |
16268 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; | |
16269 | default: ; | |
16270 | } | |
16271 | inst.instruction |= alignbits << 4; | |
16272 | } | |
5287ad62 JB |
16273 | break; |
16274 | ||
16275 | default: ; | |
16276 | } | |
16277 | ||
16278 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ | |
16279 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
16280 | inst.instruction |= 1 << (4 + logsize); | |
5f4273c7 | 16281 | |
5287ad62 JB |
16282 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); |
16283 | inst.instruction |= logsize << 10; | |
16284 | } | |
16285 | ||
16286 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ | |
16287 | ||
16288 | static void | |
16289 | do_neon_ld_dup (void) | |
16290 | { | |
037e8744 | 16291 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
16292 | int align_good, do_align = 0; |
16293 | ||
dcbf9037 JB |
16294 | if (et.type == NT_invtype) |
16295 | return; | |
16296 | ||
5287ad62 JB |
16297 | switch ((inst.instruction >> 8) & 3) |
16298 | { | |
16299 | case 0: /* VLD1. */ | |
9c2799c2 | 16300 | gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); |
5287ad62 | 16301 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, |
477330fc | 16302 | &do_align, 16, 16, 32, 32, -1); |
5287ad62 | 16303 | if (align_good == FAIL) |
477330fc | 16304 | return; |
5287ad62 | 16305 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) |
477330fc RM |
16306 | { |
16307 | case 1: break; | |
16308 | case 2: inst.instruction |= 1 << 5; break; | |
16309 | default: first_error (_("bad list length")); return; | |
16310 | } | |
5287ad62 JB |
16311 | inst.instruction |= neon_logbits (et.size) << 6; |
16312 | break; | |
16313 | ||
16314 | case 1: /* VLD2. */ | |
16315 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
477330fc | 16316 | &do_align, 8, 16, 16, 32, 32, 64, -1); |
5287ad62 | 16317 | if (align_good == FAIL) |
477330fc | 16318 | return; |
5287ad62 | 16319 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, |
477330fc | 16320 | _("bad list length")); |
5287ad62 | 16321 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
477330fc | 16322 | inst.instruction |= 1 << 5; |
5287ad62 JB |
16323 | inst.instruction |= neon_logbits (et.size) << 6; |
16324 | break; | |
16325 | ||
16326 | case 2: /* VLD3. */ | |
16327 | constraint (inst.operands[1].immisalign, | |
477330fc | 16328 | _("can't use alignment with this instruction")); |
5287ad62 | 16329 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, |
477330fc | 16330 | _("bad list length")); |
5287ad62 | 16331 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
477330fc | 16332 | inst.instruction |= 1 << 5; |
5287ad62 JB |
16333 | inst.instruction |= neon_logbits (et.size) << 6; |
16334 | break; | |
16335 | ||
16336 | case 3: /* VLD4. */ | |
16337 | { | |
477330fc RM |
16338 | int align = inst.operands[1].imm >> 8; |
16339 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
16340 | 16, 64, 32, 64, 32, 128, -1); | |
16341 | if (align_good == FAIL) | |
16342 | return; | |
16343 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, | |
16344 | _("bad list length")); | |
16345 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
16346 | inst.instruction |= 1 << 5; | |
16347 | if (et.size == 32 && align == 128) | |
16348 | inst.instruction |= 0x3 << 6; | |
16349 | else | |
16350 | inst.instruction |= neon_logbits (et.size) << 6; | |
5287ad62 JB |
16351 | } |
16352 | break; | |
16353 | ||
16354 | default: ; | |
16355 | } | |
16356 | ||
16357 | inst.instruction |= do_align << 4; | |
16358 | } | |
16359 | ||
16360 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those | |
16361 | apart from bits [11:4]. */ | |
16362 | ||
16363 | static void | |
16364 | do_neon_ldx_stx (void) | |
16365 | { | |
b1a769ed DG |
16366 | if (inst.operands[1].isreg) |
16367 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
16368 | ||
5287ad62 JB |
16369 | switch (NEON_LANE (inst.operands[0].imm)) |
16370 | { | |
16371 | case NEON_INTERLEAVE_LANES: | |
88714cb8 | 16372 | NEON_ENCODE (INTERLV, inst); |
5287ad62 JB |
16373 | do_neon_ld_st_interleave (); |
16374 | break; | |
5f4273c7 | 16375 | |
5287ad62 | 16376 | case NEON_ALL_LANES: |
88714cb8 | 16377 | NEON_ENCODE (DUP, inst); |
2d51fb74 JB |
16378 | if (inst.instruction == N_INV) |
16379 | { | |
16380 | first_error ("only loads support such operands"); | |
16381 | break; | |
16382 | } | |
5287ad62 JB |
16383 | do_neon_ld_dup (); |
16384 | break; | |
5f4273c7 | 16385 | |
5287ad62 | 16386 | default: |
88714cb8 | 16387 | NEON_ENCODE (LANE, inst); |
5287ad62 JB |
16388 | do_neon_ld_st_lane (); |
16389 | } | |
16390 | ||
16391 | /* L bit comes from bit mask. */ | |
16392 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16393 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16394 | inst.instruction |= inst.operands[1].reg << 16; | |
5f4273c7 | 16395 | |
5287ad62 JB |
16396 | if (inst.operands[1].postind) |
16397 | { | |
16398 | int postreg = inst.operands[1].imm & 0xf; | |
16399 | constraint (!inst.operands[1].immisreg, | |
477330fc | 16400 | _("post-index must be a register")); |
5287ad62 | 16401 | constraint (postreg == 0xd || postreg == 0xf, |
477330fc | 16402 | _("bad register for post-index")); |
5287ad62 JB |
16403 | inst.instruction |= postreg; |
16404 | } | |
4f2374c7 | 16405 | else |
5287ad62 | 16406 | { |
4f2374c7 WN |
16407 | constraint (inst.operands[1].immisreg, BAD_ADDR_MODE); |
16408 | constraint (inst.reloc.exp.X_op != O_constant | |
16409 | || inst.reloc.exp.X_add_number != 0, | |
16410 | BAD_ADDR_MODE); | |
16411 | ||
16412 | if (inst.operands[1].writeback) | |
16413 | { | |
16414 | inst.instruction |= 0xd; | |
16415 | } | |
16416 | else | |
16417 | inst.instruction |= 0xf; | |
5287ad62 | 16418 | } |
5f4273c7 | 16419 | |
5287ad62 JB |
16420 | if (thumb_mode) |
16421 | inst.instruction |= 0xf9000000; | |
16422 | else | |
16423 | inst.instruction |= 0xf4000000; | |
16424 | } | |
33399f07 MGD |
16425 | |
16426 | /* FP v8. */ | |
16427 | static void | |
16428 | do_vfp_nsyn_fpv8 (enum neon_shape rs) | |
16429 | { | |
16430 | NEON_ENCODE (FPV8, inst); | |
16431 | ||
16432 | if (rs == NS_FFF) | |
16433 | do_vfp_sp_dyadic (); | |
16434 | else | |
16435 | do_vfp_dp_rd_rn_rm (); | |
16436 | ||
16437 | if (rs == NS_DDD) | |
16438 | inst.instruction |= 0x100; | |
16439 | ||
16440 | inst.instruction |= 0xf0000000; | |
16441 | } | |
16442 | ||
16443 | static void | |
16444 | do_vsel (void) | |
16445 | { | |
16446 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16447 | ||
16448 | if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS) | |
16449 | first_error (_("invalid instruction shape")); | |
16450 | } | |
16451 | ||
73924fbc MGD |
16452 | static void |
16453 | do_vmaxnm (void) | |
16454 | { | |
16455 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16456 | ||
16457 | if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS) | |
16458 | return; | |
16459 | ||
16460 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) | |
16461 | return; | |
16462 | ||
16463 | neon_dyadic_misc (NT_untyped, N_F32, 0); | |
16464 | } | |
16465 | ||
30bdf752 MGD |
16466 | static void |
16467 | do_vrint_1 (enum neon_cvt_mode mode) | |
16468 | { | |
16469 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL); | |
16470 | struct neon_type_el et; | |
16471 | ||
16472 | if (rs == NS_NULL) | |
16473 | return; | |
16474 | ||
16475 | et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
16476 | if (et.type != NT_invtype) | |
16477 | { | |
16478 | /* VFP encodings. */ | |
16479 | if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n | |
16480 | || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m) | |
16481 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16482 | ||
16483 | NEON_ENCODE (FPV8, inst); | |
16484 | if (rs == NS_FF) | |
16485 | do_vfp_sp_monadic (); | |
16486 | else | |
16487 | do_vfp_dp_rd_rm (); | |
16488 | ||
16489 | switch (mode) | |
16490 | { | |
16491 | case neon_cvt_mode_r: inst.instruction |= 0x00000000; break; | |
16492 | case neon_cvt_mode_z: inst.instruction |= 0x00000080; break; | |
16493 | case neon_cvt_mode_x: inst.instruction |= 0x00010000; break; | |
16494 | case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break; | |
16495 | case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break; | |
16496 | case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break; | |
16497 | case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break; | |
16498 | default: abort (); | |
16499 | } | |
16500 | ||
16501 | inst.instruction |= (rs == NS_DD) << 8; | |
16502 | do_vfp_cond_or_thumb (); | |
16503 | } | |
16504 | else | |
16505 | { | |
16506 | /* Neon encodings (or something broken...). */ | |
16507 | inst.error = NULL; | |
16508 | et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY); | |
16509 | ||
16510 | if (et.type == NT_invtype) | |
16511 | return; | |
16512 | ||
16513 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16514 | NEON_ENCODE (FLOAT, inst); | |
16515 | ||
16516 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) | |
16517 | return; | |
16518 | ||
16519 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16520 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16521 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16522 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16523 | inst.instruction |= neon_quad (rs) << 6; | |
16524 | switch (mode) | |
16525 | { | |
16526 | case neon_cvt_mode_z: inst.instruction |= 3 << 7; break; | |
16527 | case neon_cvt_mode_x: inst.instruction |= 1 << 7; break; | |
16528 | case neon_cvt_mode_a: inst.instruction |= 2 << 7; break; | |
16529 | case neon_cvt_mode_n: inst.instruction |= 0 << 7; break; | |
16530 | case neon_cvt_mode_p: inst.instruction |= 7 << 7; break; | |
16531 | case neon_cvt_mode_m: inst.instruction |= 5 << 7; break; | |
16532 | case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break; | |
16533 | default: abort (); | |
16534 | } | |
16535 | ||
16536 | if (thumb_mode) | |
16537 | inst.instruction |= 0xfc000000; | |
16538 | else | |
16539 | inst.instruction |= 0xf0000000; | |
16540 | } | |
16541 | } | |
16542 | ||
16543 | static void | |
16544 | do_vrintx (void) | |
16545 | { | |
16546 | do_vrint_1 (neon_cvt_mode_x); | |
16547 | } | |
16548 | ||
16549 | static void | |
16550 | do_vrintz (void) | |
16551 | { | |
16552 | do_vrint_1 (neon_cvt_mode_z); | |
16553 | } | |
16554 | ||
16555 | static void | |
16556 | do_vrintr (void) | |
16557 | { | |
16558 | do_vrint_1 (neon_cvt_mode_r); | |
16559 | } | |
16560 | ||
16561 | static void | |
16562 | do_vrinta (void) | |
16563 | { | |
16564 | do_vrint_1 (neon_cvt_mode_a); | |
16565 | } | |
16566 | ||
16567 | static void | |
16568 | do_vrintn (void) | |
16569 | { | |
16570 | do_vrint_1 (neon_cvt_mode_n); | |
16571 | } | |
16572 | ||
16573 | static void | |
16574 | do_vrintp (void) | |
16575 | { | |
16576 | do_vrint_1 (neon_cvt_mode_p); | |
16577 | } | |
16578 | ||
16579 | static void | |
16580 | do_vrintm (void) | |
16581 | { | |
16582 | do_vrint_1 (neon_cvt_mode_m); | |
16583 | } | |
16584 | ||
91ff7894 MGD |
16585 | /* Crypto v1 instructions. */ |
16586 | static void | |
16587 | do_crypto_2op_1 (unsigned elttype, int op) | |
16588 | { | |
16589 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16590 | ||
16591 | if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type | |
16592 | == NT_invtype) | |
16593 | return; | |
16594 | ||
16595 | inst.error = NULL; | |
16596 | ||
16597 | NEON_ENCODE (INTEGER, inst); | |
16598 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16599 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16600 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16601 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16602 | if (op != -1) | |
16603 | inst.instruction |= op << 6; | |
16604 | ||
16605 | if (thumb_mode) | |
16606 | inst.instruction |= 0xfc000000; | |
16607 | else | |
16608 | inst.instruction |= 0xf0000000; | |
16609 | } | |
16610 | ||
48adcd8e MGD |
16611 | static void |
16612 | do_crypto_3op_1 (int u, int op) | |
16613 | { | |
16614 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16615 | ||
16616 | if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT, | |
16617 | N_32 | N_UNT | N_KEY).type == NT_invtype) | |
16618 | return; | |
16619 | ||
16620 | inst.error = NULL; | |
16621 | ||
16622 | NEON_ENCODE (INTEGER, inst); | |
16623 | neon_three_same (1, u, 8 << op); | |
16624 | } | |
16625 | ||
91ff7894 MGD |
16626 | static void |
16627 | do_aese (void) | |
16628 | { | |
16629 | do_crypto_2op_1 (N_8, 0); | |
16630 | } | |
16631 | ||
16632 | static void | |
16633 | do_aesd (void) | |
16634 | { | |
16635 | do_crypto_2op_1 (N_8, 1); | |
16636 | } | |
16637 | ||
16638 | static void | |
16639 | do_aesmc (void) | |
16640 | { | |
16641 | do_crypto_2op_1 (N_8, 2); | |
16642 | } | |
16643 | ||
16644 | static void | |
16645 | do_aesimc (void) | |
16646 | { | |
16647 | do_crypto_2op_1 (N_8, 3); | |
16648 | } | |
16649 | ||
48adcd8e MGD |
16650 | static void |
16651 | do_sha1c (void) | |
16652 | { | |
16653 | do_crypto_3op_1 (0, 0); | |
16654 | } | |
16655 | ||
16656 | static void | |
16657 | do_sha1p (void) | |
16658 | { | |
16659 | do_crypto_3op_1 (0, 1); | |
16660 | } | |
16661 | ||
16662 | static void | |
16663 | do_sha1m (void) | |
16664 | { | |
16665 | do_crypto_3op_1 (0, 2); | |
16666 | } | |
16667 | ||
16668 | static void | |
16669 | do_sha1su0 (void) | |
16670 | { | |
16671 | do_crypto_3op_1 (0, 3); | |
16672 | } | |
91ff7894 | 16673 | |
48adcd8e MGD |
16674 | static void |
16675 | do_sha256h (void) | |
16676 | { | |
16677 | do_crypto_3op_1 (1, 0); | |
16678 | } | |
16679 | ||
16680 | static void | |
16681 | do_sha256h2 (void) | |
16682 | { | |
16683 | do_crypto_3op_1 (1, 1); | |
16684 | } | |
16685 | ||
16686 | static void | |
16687 | do_sha256su1 (void) | |
16688 | { | |
16689 | do_crypto_3op_1 (1, 2); | |
16690 | } | |
3c9017d2 MGD |
16691 | |
16692 | static void | |
16693 | do_sha1h (void) | |
16694 | { | |
16695 | do_crypto_2op_1 (N_32, -1); | |
16696 | } | |
16697 | ||
16698 | static void | |
16699 | do_sha1su1 (void) | |
16700 | { | |
16701 | do_crypto_2op_1 (N_32, 0); | |
16702 | } | |
16703 | ||
16704 | static void | |
16705 | do_sha256su0 (void) | |
16706 | { | |
16707 | do_crypto_2op_1 (N_32, 1); | |
16708 | } | |
dd5181d5 KT |
16709 | |
16710 | static void | |
16711 | do_crc32_1 (unsigned int poly, unsigned int sz) | |
16712 | { | |
16713 | unsigned int Rd = inst.operands[0].reg; | |
16714 | unsigned int Rn = inst.operands[1].reg; | |
16715 | unsigned int Rm = inst.operands[2].reg; | |
16716 | ||
16717 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16718 | inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12); | |
16719 | inst.instruction |= LOW4 (Rn) << 16; | |
16720 | inst.instruction |= LOW4 (Rm); | |
16721 | inst.instruction |= sz << (thumb_mode ? 4 : 21); | |
16722 | inst.instruction |= poly << (thumb_mode ? 20 : 9); | |
16723 | ||
16724 | if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC) | |
16725 | as_warn (UNPRED_REG ("r15")); | |
16726 | if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP)) | |
16727 | as_warn (UNPRED_REG ("r13")); | |
16728 | } | |
16729 | ||
16730 | static void | |
16731 | do_crc32b (void) | |
16732 | { | |
16733 | do_crc32_1 (0, 0); | |
16734 | } | |
16735 | ||
16736 | static void | |
16737 | do_crc32h (void) | |
16738 | { | |
16739 | do_crc32_1 (0, 1); | |
16740 | } | |
16741 | ||
16742 | static void | |
16743 | do_crc32w (void) | |
16744 | { | |
16745 | do_crc32_1 (0, 2); | |
16746 | } | |
16747 | ||
16748 | static void | |
16749 | do_crc32cb (void) | |
16750 | { | |
16751 | do_crc32_1 (1, 0); | |
16752 | } | |
16753 | ||
16754 | static void | |
16755 | do_crc32ch (void) | |
16756 | { | |
16757 | do_crc32_1 (1, 1); | |
16758 | } | |
16759 | ||
16760 | static void | |
16761 | do_crc32cw (void) | |
16762 | { | |
16763 | do_crc32_1 (1, 2); | |
16764 | } | |
16765 | ||
5287ad62 JB |
16766 | \f |
16767 | /* Overall per-instruction processing. */ | |
16768 | ||
16769 | /* We need to be able to fix up arbitrary expressions in some statements. | |
16770 | This is so that we can handle symbols that are an arbitrary distance from | |
16771 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
16772 | which returns part of an address in a form which will be valid for | |
16773 | a data instruction. We do this by pushing the expression into a symbol | |
16774 | in the expr_section, and creating a fix for that. */ | |
16775 | ||
16776 | static void | |
16777 | fix_new_arm (fragS * frag, | |
16778 | int where, | |
16779 | short int size, | |
16780 | expressionS * exp, | |
16781 | int pc_rel, | |
16782 | int reloc) | |
16783 | { | |
16784 | fixS * new_fix; | |
16785 | ||
16786 | switch (exp->X_op) | |
16787 | { | |
16788 | case O_constant: | |
6e7ce2cd PB |
16789 | if (pc_rel) |
16790 | { | |
16791 | /* Create an absolute valued symbol, so we have something to | |
477330fc RM |
16792 | refer to in the object file. Unfortunately for us, gas's |
16793 | generic expression parsing will already have folded out | |
16794 | any use of .set foo/.type foo %function that may have | |
16795 | been used to set type information of the target location, | |
16796 | that's being specified symbolically. We have to presume | |
16797 | the user knows what they are doing. */ | |
6e7ce2cd PB |
16798 | char name[16 + 8]; |
16799 | symbolS *symbol; | |
16800 | ||
16801 | sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number); | |
16802 | ||
16803 | symbol = symbol_find_or_make (name); | |
16804 | S_SET_SEGMENT (symbol, absolute_section); | |
16805 | symbol_set_frag (symbol, &zero_address_frag); | |
16806 | S_SET_VALUE (symbol, exp->X_add_number); | |
16807 | exp->X_op = O_symbol; | |
16808 | exp->X_add_symbol = symbol; | |
16809 | exp->X_add_number = 0; | |
16810 | } | |
16811 | /* FALLTHROUGH */ | |
5287ad62 JB |
16812 | case O_symbol: |
16813 | case O_add: | |
16814 | case O_subtract: | |
21d799b5 | 16815 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, |
477330fc | 16816 | (enum bfd_reloc_code_real) reloc); |
5287ad62 JB |
16817 | break; |
16818 | ||
16819 | default: | |
21d799b5 | 16820 | new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0, |
477330fc | 16821 | pc_rel, (enum bfd_reloc_code_real) reloc); |
5287ad62 JB |
16822 | break; |
16823 | } | |
16824 | ||
16825 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
16826 | instruction. */ | |
16827 | new_fix->tc_fix_data = thumb_mode; | |
16828 | } | |
16829 | ||
16830 | /* Create a frg for an instruction requiring relaxation. */ | |
16831 | static void | |
16832 | output_relax_insn (void) | |
16833 | { | |
16834 | char * to; | |
16835 | symbolS *sym; | |
0110f2b8 PB |
16836 | int offset; |
16837 | ||
6e1cb1a6 PB |
16838 | /* The size of the instruction is unknown, so tie the debug info to the |
16839 | start of the instruction. */ | |
16840 | dwarf2_emit_insn (0); | |
6e1cb1a6 | 16841 | |
0110f2b8 PB |
16842 | switch (inst.reloc.exp.X_op) |
16843 | { | |
16844 | case O_symbol: | |
16845 | sym = inst.reloc.exp.X_add_symbol; | |
16846 | offset = inst.reloc.exp.X_add_number; | |
16847 | break; | |
16848 | case O_constant: | |
16849 | sym = NULL; | |
16850 | offset = inst.reloc.exp.X_add_number; | |
16851 | break; | |
16852 | default: | |
16853 | sym = make_expr_symbol (&inst.reloc.exp); | |
16854 | offset = 0; | |
16855 | break; | |
16856 | } | |
16857 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
16858 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
16859 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
16860 | } |
16861 | ||
16862 | /* Write a 32-bit thumb instruction to buf. */ | |
16863 | static void | |
16864 | put_thumb32_insn (char * buf, unsigned long insn) | |
16865 | { | |
16866 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
16867 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
16868 | } | |
16869 | ||
b99bd4ef | 16870 | static void |
c19d1205 | 16871 | output_inst (const char * str) |
b99bd4ef | 16872 | { |
c19d1205 | 16873 | char * to = NULL; |
b99bd4ef | 16874 | |
c19d1205 | 16875 | if (inst.error) |
b99bd4ef | 16876 | { |
c19d1205 | 16877 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
16878 | return; |
16879 | } | |
5f4273c7 NC |
16880 | if (inst.relax) |
16881 | { | |
16882 | output_relax_insn (); | |
0110f2b8 | 16883 | return; |
5f4273c7 | 16884 | } |
c19d1205 ZW |
16885 | if (inst.size == 0) |
16886 | return; | |
b99bd4ef | 16887 | |
c19d1205 | 16888 | to = frag_more (inst.size); |
8dc2430f NC |
16889 | /* PR 9814: Record the thumb mode into the current frag so that we know |
16890 | what type of NOP padding to use, if necessary. We override any previous | |
16891 | setting so that if the mode has changed then the NOPS that we use will | |
16892 | match the encoding of the last instruction in the frag. */ | |
cd000bff | 16893 | frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
c19d1205 ZW |
16894 | |
16895 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 16896 | { |
9c2799c2 | 16897 | gas_assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 16898 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 16899 | } |
c19d1205 | 16900 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 16901 | { |
9c2799c2 | 16902 | gas_assert (inst.size == (2 * INSN_SIZE)); |
c19d1205 ZW |
16903 | md_number_to_chars (to, inst.instruction, INSN_SIZE); |
16904 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 16905 | } |
c19d1205 ZW |
16906 | else |
16907 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 16908 | |
c19d1205 ZW |
16909 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
16910 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
16911 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
16912 | inst.reloc.type); | |
b99bd4ef | 16913 | |
c19d1205 | 16914 | dwarf2_emit_insn (inst.size); |
c19d1205 | 16915 | } |
b99bd4ef | 16916 | |
e07e6e58 NC |
16917 | static char * |
16918 | output_it_inst (int cond, int mask, char * to) | |
16919 | { | |
16920 | unsigned long instruction = 0xbf00; | |
16921 | ||
16922 | mask &= 0xf; | |
16923 | instruction |= mask; | |
16924 | instruction |= cond << 4; | |
16925 | ||
16926 | if (to == NULL) | |
16927 | { | |
16928 | to = frag_more (2); | |
16929 | #ifdef OBJ_ELF | |
16930 | dwarf2_emit_insn (2); | |
16931 | #endif | |
16932 | } | |
16933 | ||
16934 | md_number_to_chars (to, instruction, 2); | |
16935 | ||
16936 | return to; | |
16937 | } | |
16938 | ||
c19d1205 ZW |
16939 | /* Tag values used in struct asm_opcode's tag field. */ |
16940 | enum opcode_tag | |
16941 | { | |
16942 | OT_unconditional, /* Instruction cannot be conditionalized. | |
16943 | The ARM condition field is still 0xE. */ | |
16944 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
16945 | and carries 0xF in its ARM condition field. */ | |
16946 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
037e8744 | 16947 | OT_csuffixF, /* Some forms of the instruction take a conditional |
477330fc RM |
16948 | suffix, others place 0xF where the condition field |
16949 | would be. */ | |
c19d1205 ZW |
16950 | OT_cinfix3, /* Instruction takes a conditional infix, |
16951 | beginning at character index 3. (In | |
16952 | unified mode, it becomes a suffix.) */ | |
088fa78e KH |
16953 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
16954 | tsts, cmps, cmns, and teqs. */ | |
e3cb604e PB |
16955 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
16956 | character index 3, even in unified mode. Used for | |
16957 | legacy instructions where suffix and infix forms | |
16958 | may be ambiguous. */ | |
c19d1205 | 16959 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 16960 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
16961 | OT_odd_infix_unc, /* This is the unconditional variant of an |
16962 | instruction that takes a conditional infix | |
16963 | at an unusual position. In unified mode, | |
16964 | this variant will accept a suffix. */ | |
16965 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
16966 | are the conditional variants of instructions that | |
16967 | take conditional infixes in unusual positions. | |
16968 | The infix appears at character index | |
16969 | (tag - OT_odd_infix_0). These are not accepted | |
16970 | in unified mode. */ | |
16971 | }; | |
b99bd4ef | 16972 | |
c19d1205 ZW |
16973 | /* Subroutine of md_assemble, responsible for looking up the primary |
16974 | opcode from the mnemonic the user wrote. STR points to the | |
16975 | beginning of the mnemonic. | |
16976 | ||
16977 | This is not simply a hash table lookup, because of conditional | |
16978 | variants. Most instructions have conditional variants, which are | |
16979 | expressed with a _conditional affix_ to the mnemonic. If we were | |
16980 | to encode each conditional variant as a literal string in the opcode | |
16981 | table, it would have approximately 20,000 entries. | |
16982 | ||
16983 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
16984 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
16985 | instructions take the affix as an infix, notably the s-variants of | |
16986 | the arithmetic instructions. Of those instructions, all but six | |
16987 | have the infix appear after the third character of the mnemonic. | |
16988 | ||
16989 | Accordingly, the algorithm for looking up primary opcodes given | |
16990 | an identifier is: | |
16991 | ||
16992 | 1. Look up the identifier in the opcode table. | |
16993 | If we find a match, go to step U. | |
16994 | ||
16995 | 2. Look up the last two characters of the identifier in the | |
16996 | conditions table. If we find a match, look up the first N-2 | |
16997 | characters of the identifier in the opcode table. If we | |
16998 | find a match, go to step CE. | |
16999 | ||
17000 | 3. Look up the fourth and fifth characters of the identifier in | |
17001 | the conditions table. If we find a match, extract those | |
17002 | characters from the identifier, and look up the remaining | |
17003 | characters in the opcode table. If we find a match, go | |
17004 | to step CM. | |
17005 | ||
17006 | 4. Fail. | |
17007 | ||
17008 | U. Examine the tag field of the opcode structure, in case this is | |
17009 | one of the six instructions with its conditional infix in an | |
17010 | unusual place. If it is, the tag tells us where to find the | |
17011 | infix; look it up in the conditions table and set inst.cond | |
17012 | accordingly. Otherwise, this is an unconditional instruction. | |
17013 | Again set inst.cond accordingly. Return the opcode structure. | |
17014 | ||
17015 | CE. Examine the tag field to make sure this is an instruction that | |
17016 | should receive a conditional suffix. If it is not, fail. | |
17017 | Otherwise, set inst.cond from the suffix we already looked up, | |
17018 | and return the opcode structure. | |
17019 | ||
17020 | CM. Examine the tag field to make sure this is an instruction that | |
17021 | should receive a conditional infix after the third character. | |
17022 | If it is not, fail. Otherwise, undo the edits to the current | |
17023 | line of input and proceed as for case CE. */ | |
17024 | ||
17025 | static const struct asm_opcode * | |
17026 | opcode_lookup (char **str) | |
17027 | { | |
17028 | char *end, *base; | |
17029 | char *affix; | |
17030 | const struct asm_opcode *opcode; | |
17031 | const struct asm_cond *cond; | |
e3cb604e | 17032 | char save[2]; |
c19d1205 ZW |
17033 | |
17034 | /* Scan up to the end of the mnemonic, which must end in white space, | |
721a8186 | 17035 | '.' (in unified mode, or for Neon/VFP instructions), or end of string. */ |
c19d1205 | 17036 | for (base = end = *str; *end != '\0'; end++) |
721a8186 | 17037 | if (*end == ' ' || *end == '.') |
c19d1205 | 17038 | break; |
b99bd4ef | 17039 | |
c19d1205 | 17040 | if (end == base) |
c921be7d | 17041 | return NULL; |
b99bd4ef | 17042 | |
5287ad62 | 17043 | /* Handle a possible width suffix and/or Neon type suffix. */ |
c19d1205 | 17044 | if (end[0] == '.') |
b99bd4ef | 17045 | { |
5287ad62 | 17046 | int offset = 2; |
5f4273c7 | 17047 | |
267d2029 | 17048 | /* The .w and .n suffixes are only valid if the unified syntax is in |
477330fc | 17049 | use. */ |
267d2029 | 17050 | if (unified_syntax && end[1] == 'w') |
c19d1205 | 17051 | inst.size_req = 4; |
267d2029 | 17052 | else if (unified_syntax && end[1] == 'n') |
c19d1205 ZW |
17053 | inst.size_req = 2; |
17054 | else | |
477330fc | 17055 | offset = 0; |
5287ad62 JB |
17056 | |
17057 | inst.vectype.elems = 0; | |
17058 | ||
17059 | *str = end + offset; | |
b99bd4ef | 17060 | |
5f4273c7 | 17061 | if (end[offset] == '.') |
5287ad62 | 17062 | { |
267d2029 | 17063 | /* See if we have a Neon type suffix (possible in either unified or |
477330fc RM |
17064 | non-unified ARM syntax mode). */ |
17065 | if (parse_neon_type (&inst.vectype, str) == FAIL) | |
c921be7d | 17066 | return NULL; |
477330fc | 17067 | } |
5287ad62 | 17068 | else if (end[offset] != '\0' && end[offset] != ' ') |
477330fc | 17069 | return NULL; |
b99bd4ef | 17070 | } |
c19d1205 ZW |
17071 | else |
17072 | *str = end; | |
b99bd4ef | 17073 | |
c19d1205 | 17074 | /* Look for unaffixed or special-case affixed mnemonic. */ |
21d799b5 | 17075 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
477330fc | 17076 | end - base); |
c19d1205 | 17077 | if (opcode) |
b99bd4ef | 17078 | { |
c19d1205 ZW |
17079 | /* step U */ |
17080 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 17081 | { |
c19d1205 ZW |
17082 | inst.cond = COND_ALWAYS; |
17083 | return opcode; | |
b99bd4ef | 17084 | } |
b99bd4ef | 17085 | |
278df34e | 17086 | if (warn_on_deprecated && unified_syntax) |
c19d1205 ZW |
17087 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
17088 | affix = base + (opcode->tag - OT_odd_infix_0); | |
21d799b5 | 17089 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
9c2799c2 | 17090 | gas_assert (cond); |
b99bd4ef | 17091 | |
c19d1205 ZW |
17092 | inst.cond = cond->value; |
17093 | return opcode; | |
17094 | } | |
b99bd4ef | 17095 | |
c19d1205 ZW |
17096 | /* Cannot have a conditional suffix on a mnemonic of less than two |
17097 | characters. */ | |
17098 | if (end - base < 3) | |
c921be7d | 17099 | return NULL; |
b99bd4ef | 17100 | |
c19d1205 ZW |
17101 | /* Look for suffixed mnemonic. */ |
17102 | affix = end - 2; | |
21d799b5 NC |
17103 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
17104 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, | |
477330fc | 17105 | affix - base); |
c19d1205 ZW |
17106 | if (opcode && cond) |
17107 | { | |
17108 | /* step CE */ | |
17109 | switch (opcode->tag) | |
17110 | { | |
e3cb604e PB |
17111 | case OT_cinfix3_legacy: |
17112 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
17113 | break; | |
17114 | ||
c19d1205 | 17115 | case OT_cinfix3: |
088fa78e | 17116 | case OT_cinfix3_deprecated: |
c19d1205 ZW |
17117 | case OT_odd_infix_unc: |
17118 | if (!unified_syntax) | |
e3cb604e | 17119 | return 0; |
c19d1205 ZW |
17120 | /* else fall through */ |
17121 | ||
17122 | case OT_csuffix: | |
477330fc | 17123 | case OT_csuffixF: |
c19d1205 ZW |
17124 | case OT_csuf_or_in3: |
17125 | inst.cond = cond->value; | |
17126 | return opcode; | |
17127 | ||
17128 | case OT_unconditional: | |
17129 | case OT_unconditionalF: | |
dfa9f0d5 | 17130 | if (thumb_mode) |
c921be7d | 17131 | inst.cond = cond->value; |
dfa9f0d5 PB |
17132 | else |
17133 | { | |
c921be7d | 17134 | /* Delayed diagnostic. */ |
dfa9f0d5 PB |
17135 | inst.error = BAD_COND; |
17136 | inst.cond = COND_ALWAYS; | |
17137 | } | |
c19d1205 | 17138 | return opcode; |
b99bd4ef | 17139 | |
c19d1205 | 17140 | default: |
c921be7d | 17141 | return NULL; |
c19d1205 ZW |
17142 | } |
17143 | } | |
b99bd4ef | 17144 | |
c19d1205 ZW |
17145 | /* Cannot have a usual-position infix on a mnemonic of less than |
17146 | six characters (five would be a suffix). */ | |
17147 | if (end - base < 6) | |
c921be7d | 17148 | return NULL; |
b99bd4ef | 17149 | |
c19d1205 ZW |
17150 | /* Look for infixed mnemonic in the usual position. */ |
17151 | affix = base + 3; | |
21d799b5 | 17152 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
e3cb604e | 17153 | if (!cond) |
c921be7d | 17154 | return NULL; |
e3cb604e PB |
17155 | |
17156 | memcpy (save, affix, 2); | |
17157 | memmove (affix, affix + 2, (end - affix) - 2); | |
21d799b5 | 17158 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
477330fc | 17159 | (end - base) - 2); |
e3cb604e PB |
17160 | memmove (affix + 2, affix, (end - affix) - 2); |
17161 | memcpy (affix, save, 2); | |
17162 | ||
088fa78e KH |
17163 | if (opcode |
17164 | && (opcode->tag == OT_cinfix3 | |
17165 | || opcode->tag == OT_cinfix3_deprecated | |
17166 | || opcode->tag == OT_csuf_or_in3 | |
17167 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 17168 | { |
c921be7d | 17169 | /* Step CM. */ |
278df34e | 17170 | if (warn_on_deprecated && unified_syntax |
088fa78e KH |
17171 | && (opcode->tag == OT_cinfix3 |
17172 | || opcode->tag == OT_cinfix3_deprecated)) | |
c19d1205 ZW |
17173 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
17174 | ||
17175 | inst.cond = cond->value; | |
17176 | return opcode; | |
b99bd4ef NC |
17177 | } |
17178 | ||
c921be7d | 17179 | return NULL; |
b99bd4ef NC |
17180 | } |
17181 | ||
e07e6e58 NC |
17182 | /* This function generates an initial IT instruction, leaving its block |
17183 | virtually open for the new instructions. Eventually, | |
17184 | the mask will be updated by now_it_add_mask () each time | |
17185 | a new instruction needs to be included in the IT block. | |
17186 | Finally, the block is closed with close_automatic_it_block (). | |
17187 | The block closure can be requested either from md_assemble (), | |
17188 | a tencode (), or due to a label hook. */ | |
17189 | ||
17190 | static void | |
17191 | new_automatic_it_block (int cond) | |
17192 | { | |
17193 | now_it.state = AUTOMATIC_IT_BLOCK; | |
17194 | now_it.mask = 0x18; | |
17195 | now_it.cc = cond; | |
17196 | now_it.block_length = 1; | |
cd000bff | 17197 | mapping_state (MAP_THUMB); |
e07e6e58 | 17198 | now_it.insn = output_it_inst (cond, now_it.mask, NULL); |
5a01bb1d MGD |
17199 | now_it.warn_deprecated = FALSE; |
17200 | now_it.insn_cond = TRUE; | |
e07e6e58 NC |
17201 | } |
17202 | ||
17203 | /* Close an automatic IT block. | |
17204 | See comments in new_automatic_it_block (). */ | |
17205 | ||
17206 | static void | |
17207 | close_automatic_it_block (void) | |
17208 | { | |
17209 | now_it.mask = 0x10; | |
17210 | now_it.block_length = 0; | |
17211 | } | |
17212 | ||
17213 | /* Update the mask of the current automatically-generated IT | |
17214 | instruction. See comments in new_automatic_it_block (). */ | |
17215 | ||
17216 | static void | |
17217 | now_it_add_mask (int cond) | |
17218 | { | |
17219 | #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) | |
17220 | #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ | |
477330fc | 17221 | | ((bitvalue) << (nbit))) |
e07e6e58 | 17222 | const int resulting_bit = (cond & 1); |
c921be7d | 17223 | |
e07e6e58 NC |
17224 | now_it.mask &= 0xf; |
17225 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
477330fc RM |
17226 | resulting_bit, |
17227 | (5 - now_it.block_length)); | |
e07e6e58 | 17228 | now_it.mask = SET_BIT_VALUE (now_it.mask, |
477330fc RM |
17229 | 1, |
17230 | ((5 - now_it.block_length) - 1) ); | |
e07e6e58 NC |
17231 | output_it_inst (now_it.cc, now_it.mask, now_it.insn); |
17232 | ||
17233 | #undef CLEAR_BIT | |
17234 | #undef SET_BIT_VALUE | |
e07e6e58 NC |
17235 | } |
17236 | ||
17237 | /* The IT blocks handling machinery is accessed through the these functions: | |
17238 | it_fsm_pre_encode () from md_assemble () | |
17239 | set_it_insn_type () optional, from the tencode functions | |
17240 | set_it_insn_type_last () ditto | |
17241 | in_it_block () ditto | |
17242 | it_fsm_post_encode () from md_assemble () | |
17243 | force_automatic_it_block_close () from label habdling functions | |
17244 | ||
17245 | Rationale: | |
17246 | 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), | |
477330fc RM |
17247 | initializing the IT insn type with a generic initial value depending |
17248 | on the inst.condition. | |
e07e6e58 | 17249 | 2) During the tencode function, two things may happen: |
477330fc RM |
17250 | a) The tencode function overrides the IT insn type by |
17251 | calling either set_it_insn_type (type) or set_it_insn_type_last (). | |
17252 | b) The tencode function queries the IT block state by | |
17253 | calling in_it_block () (i.e. to determine narrow/not narrow mode). | |
17254 | ||
17255 | Both set_it_insn_type and in_it_block run the internal FSM state | |
17256 | handling function (handle_it_state), because: a) setting the IT insn | |
17257 | type may incur in an invalid state (exiting the function), | |
17258 | and b) querying the state requires the FSM to be updated. | |
17259 | Specifically we want to avoid creating an IT block for conditional | |
17260 | branches, so it_fsm_pre_encode is actually a guess and we can't | |
17261 | determine whether an IT block is required until the tencode () routine | |
17262 | has decided what type of instruction this actually it. | |
17263 | Because of this, if set_it_insn_type and in_it_block have to be used, | |
17264 | set_it_insn_type has to be called first. | |
17265 | ||
17266 | set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that | |
17267 | determines the insn IT type depending on the inst.cond code. | |
17268 | When a tencode () routine encodes an instruction that can be | |
17269 | either outside an IT block, or, in the case of being inside, has to be | |
17270 | the last one, set_it_insn_type_last () will determine the proper | |
17271 | IT instruction type based on the inst.cond code. Otherwise, | |
17272 | set_it_insn_type can be called for overriding that logic or | |
17273 | for covering other cases. | |
17274 | ||
17275 | Calling handle_it_state () may not transition the IT block state to | |
17276 | OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be | |
17277 | still queried. Instead, if the FSM determines that the state should | |
17278 | be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed | |
17279 | after the tencode () function: that's what it_fsm_post_encode () does. | |
17280 | ||
17281 | Since in_it_block () calls the state handling function to get an | |
17282 | updated state, an error may occur (due to invalid insns combination). | |
17283 | In that case, inst.error is set. | |
17284 | Therefore, inst.error has to be checked after the execution of | |
17285 | the tencode () routine. | |
e07e6e58 NC |
17286 | |
17287 | 3) Back in md_assemble(), it_fsm_post_encode () is called to commit | |
477330fc RM |
17288 | any pending state change (if any) that didn't take place in |
17289 | handle_it_state () as explained above. */ | |
e07e6e58 NC |
17290 | |
17291 | static void | |
17292 | it_fsm_pre_encode (void) | |
17293 | { | |
17294 | if (inst.cond != COND_ALWAYS) | |
17295 | inst.it_insn_type = INSIDE_IT_INSN; | |
17296 | else | |
17297 | inst.it_insn_type = OUTSIDE_IT_INSN; | |
17298 | ||
17299 | now_it.state_handled = 0; | |
17300 | } | |
17301 | ||
17302 | /* IT state FSM handling function. */ | |
17303 | ||
17304 | static int | |
17305 | handle_it_state (void) | |
17306 | { | |
17307 | now_it.state_handled = 1; | |
5a01bb1d | 17308 | now_it.insn_cond = FALSE; |
e07e6e58 NC |
17309 | |
17310 | switch (now_it.state) | |
17311 | { | |
17312 | case OUTSIDE_IT_BLOCK: | |
17313 | switch (inst.it_insn_type) | |
17314 | { | |
17315 | case OUTSIDE_IT_INSN: | |
17316 | break; | |
17317 | ||
17318 | case INSIDE_IT_INSN: | |
17319 | case INSIDE_IT_LAST_INSN: | |
17320 | if (thumb_mode == 0) | |
17321 | { | |
c921be7d | 17322 | if (unified_syntax |
e07e6e58 NC |
17323 | && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) |
17324 | as_tsktsk (_("Warning: conditional outside an IT block"\ | |
17325 | " for Thumb.")); | |
17326 | } | |
17327 | else | |
17328 | { | |
17329 | if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) | |
17330 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)) | |
17331 | { | |
17332 | /* Automatically generate the IT instruction. */ | |
17333 | new_automatic_it_block (inst.cond); | |
17334 | if (inst.it_insn_type == INSIDE_IT_LAST_INSN) | |
17335 | close_automatic_it_block (); | |
17336 | } | |
17337 | else | |
17338 | { | |
17339 | inst.error = BAD_OUT_IT; | |
17340 | return FAIL; | |
17341 | } | |
17342 | } | |
17343 | break; | |
17344 | ||
17345 | case IF_INSIDE_IT_LAST_INSN: | |
17346 | case NEUTRAL_IT_INSN: | |
17347 | break; | |
17348 | ||
17349 | case IT_INSN: | |
17350 | now_it.state = MANUAL_IT_BLOCK; | |
17351 | now_it.block_length = 0; | |
17352 | break; | |
17353 | } | |
17354 | break; | |
17355 | ||
17356 | case AUTOMATIC_IT_BLOCK: | |
17357 | /* Three things may happen now: | |
17358 | a) We should increment current it block size; | |
17359 | b) We should close current it block (closing insn or 4 insns); | |
17360 | c) We should close current it block and start a new one (due | |
17361 | to incompatible conditions or | |
17362 | 4 insns-length block reached). */ | |
17363 | ||
17364 | switch (inst.it_insn_type) | |
17365 | { | |
17366 | case OUTSIDE_IT_INSN: | |
17367 | /* The closure of the block shall happen immediatelly, | |
17368 | so any in_it_block () call reports the block as closed. */ | |
17369 | force_automatic_it_block_close (); | |
17370 | break; | |
17371 | ||
17372 | case INSIDE_IT_INSN: | |
17373 | case INSIDE_IT_LAST_INSN: | |
17374 | case IF_INSIDE_IT_LAST_INSN: | |
17375 | now_it.block_length++; | |
17376 | ||
17377 | if (now_it.block_length > 4 | |
17378 | || !now_it_compatible (inst.cond)) | |
17379 | { | |
17380 | force_automatic_it_block_close (); | |
17381 | if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN) | |
17382 | new_automatic_it_block (inst.cond); | |
17383 | } | |
17384 | else | |
17385 | { | |
5a01bb1d | 17386 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
17387 | now_it_add_mask (inst.cond); |
17388 | } | |
17389 | ||
17390 | if (now_it.state == AUTOMATIC_IT_BLOCK | |
17391 | && (inst.it_insn_type == INSIDE_IT_LAST_INSN | |
17392 | || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN)) | |
17393 | close_automatic_it_block (); | |
17394 | break; | |
17395 | ||
17396 | case NEUTRAL_IT_INSN: | |
17397 | now_it.block_length++; | |
5a01bb1d | 17398 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
17399 | |
17400 | if (now_it.block_length > 4) | |
17401 | force_automatic_it_block_close (); | |
17402 | else | |
17403 | now_it_add_mask (now_it.cc & 1); | |
17404 | break; | |
17405 | ||
17406 | case IT_INSN: | |
17407 | close_automatic_it_block (); | |
17408 | now_it.state = MANUAL_IT_BLOCK; | |
17409 | break; | |
17410 | } | |
17411 | break; | |
17412 | ||
17413 | case MANUAL_IT_BLOCK: | |
17414 | { | |
17415 | /* Check conditional suffixes. */ | |
17416 | const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1; | |
17417 | int is_last; | |
17418 | now_it.mask <<= 1; | |
17419 | now_it.mask &= 0x1f; | |
17420 | is_last = (now_it.mask == 0x10); | |
5a01bb1d | 17421 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
17422 | |
17423 | switch (inst.it_insn_type) | |
17424 | { | |
17425 | case OUTSIDE_IT_INSN: | |
17426 | inst.error = BAD_NOT_IT; | |
17427 | return FAIL; | |
17428 | ||
17429 | case INSIDE_IT_INSN: | |
17430 | if (cond != inst.cond) | |
17431 | { | |
17432 | inst.error = BAD_IT_COND; | |
17433 | return FAIL; | |
17434 | } | |
17435 | break; | |
17436 | ||
17437 | case INSIDE_IT_LAST_INSN: | |
17438 | case IF_INSIDE_IT_LAST_INSN: | |
17439 | if (cond != inst.cond) | |
17440 | { | |
17441 | inst.error = BAD_IT_COND; | |
17442 | return FAIL; | |
17443 | } | |
17444 | if (!is_last) | |
17445 | { | |
17446 | inst.error = BAD_BRANCH; | |
17447 | return FAIL; | |
17448 | } | |
17449 | break; | |
17450 | ||
17451 | case NEUTRAL_IT_INSN: | |
17452 | /* The BKPT instruction is unconditional even in an IT block. */ | |
17453 | break; | |
17454 | ||
17455 | case IT_INSN: | |
17456 | inst.error = BAD_IT_IT; | |
17457 | return FAIL; | |
17458 | } | |
17459 | } | |
17460 | break; | |
17461 | } | |
17462 | ||
17463 | return SUCCESS; | |
17464 | } | |
17465 | ||
5a01bb1d MGD |
17466 | struct depr_insn_mask |
17467 | { | |
17468 | unsigned long pattern; | |
17469 | unsigned long mask; | |
17470 | const char* description; | |
17471 | }; | |
17472 | ||
17473 | /* List of 16-bit instruction patterns deprecated in an IT block in | |
17474 | ARMv8. */ | |
17475 | static const struct depr_insn_mask depr_it_insns[] = { | |
17476 | { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") }, | |
17477 | { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") }, | |
17478 | { 0xa000, 0xb800, N_("ADR") }, | |
17479 | { 0x4800, 0xf800, N_("Literal loads") }, | |
17480 | { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") }, | |
17481 | { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") }, | |
c8de034b JW |
17482 | /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue' |
17483 | field in asm_opcode. 'tvalue' is used at the stage this check happen. */ | |
17484 | { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") }, | |
5a01bb1d MGD |
17485 | { 0, 0, NULL } |
17486 | }; | |
17487 | ||
e07e6e58 NC |
17488 | static void |
17489 | it_fsm_post_encode (void) | |
17490 | { | |
17491 | int is_last; | |
17492 | ||
17493 | if (!now_it.state_handled) | |
17494 | handle_it_state (); | |
17495 | ||
5a01bb1d MGD |
17496 | if (now_it.insn_cond |
17497 | && !now_it.warn_deprecated | |
17498 | && warn_on_deprecated | |
17499 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
17500 | { | |
17501 | if (inst.instruction >= 0x10000) | |
17502 | { | |
0a8897c7 | 17503 | as_warn (_("IT blocks containing 32-bit Thumb instructions are " |
5a01bb1d MGD |
17504 | "deprecated in ARMv8")); |
17505 | now_it.warn_deprecated = TRUE; | |
17506 | } | |
17507 | else | |
17508 | { | |
17509 | const struct depr_insn_mask *p = depr_it_insns; | |
17510 | ||
17511 | while (p->mask != 0) | |
17512 | { | |
17513 | if ((inst.instruction & p->mask) == p->pattern) | |
17514 | { | |
0a8897c7 | 17515 | as_warn (_("IT blocks containing 16-bit Thumb instructions " |
5a01bb1d MGD |
17516 | "of the following class are deprecated in ARMv8: " |
17517 | "%s"), p->description); | |
17518 | now_it.warn_deprecated = TRUE; | |
17519 | break; | |
17520 | } | |
17521 | ||
17522 | ++p; | |
17523 | } | |
17524 | } | |
17525 | ||
17526 | if (now_it.block_length > 1) | |
17527 | { | |
0a8897c7 KT |
17528 | as_warn (_("IT blocks containing more than one conditional " |
17529 | "instruction are deprecated in ARMv8")); | |
5a01bb1d MGD |
17530 | now_it.warn_deprecated = TRUE; |
17531 | } | |
17532 | } | |
17533 | ||
e07e6e58 NC |
17534 | is_last = (now_it.mask == 0x10); |
17535 | if (is_last) | |
17536 | { | |
17537 | now_it.state = OUTSIDE_IT_BLOCK; | |
17538 | now_it.mask = 0; | |
17539 | } | |
17540 | } | |
17541 | ||
17542 | static void | |
17543 | force_automatic_it_block_close (void) | |
17544 | { | |
17545 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
17546 | { | |
17547 | close_automatic_it_block (); | |
17548 | now_it.state = OUTSIDE_IT_BLOCK; | |
17549 | now_it.mask = 0; | |
17550 | } | |
17551 | } | |
17552 | ||
17553 | static int | |
17554 | in_it_block (void) | |
17555 | { | |
17556 | if (!now_it.state_handled) | |
17557 | handle_it_state (); | |
17558 | ||
17559 | return now_it.state != OUTSIDE_IT_BLOCK; | |
17560 | } | |
17561 | ||
c19d1205 ZW |
17562 | void |
17563 | md_assemble (char *str) | |
b99bd4ef | 17564 | { |
c19d1205 ZW |
17565 | char *p = str; |
17566 | const struct asm_opcode * opcode; | |
b99bd4ef | 17567 | |
c19d1205 ZW |
17568 | /* Align the previous label if needed. */ |
17569 | if (last_label_seen != NULL) | |
b99bd4ef | 17570 | { |
c19d1205 ZW |
17571 | symbol_set_frag (last_label_seen, frag_now); |
17572 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
17573 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
17574 | } |
17575 | ||
c19d1205 ZW |
17576 | memset (&inst, '\0', sizeof (inst)); |
17577 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 17578 | |
c19d1205 ZW |
17579 | opcode = opcode_lookup (&p); |
17580 | if (!opcode) | |
b99bd4ef | 17581 | { |
c19d1205 | 17582 | /* It wasn't an instruction, but it might be a register alias of |
dcbf9037 | 17583 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
c921be7d | 17584 | if (! create_register_alias (str, p) |
477330fc | 17585 | && ! create_neon_reg_alias (str, p)) |
c19d1205 | 17586 | as_bad (_("bad instruction `%s'"), str); |
b99bd4ef | 17587 | |
b99bd4ef NC |
17588 | return; |
17589 | } | |
17590 | ||
278df34e | 17591 | if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) |
088fa78e KH |
17592 | as_warn (_("s suffix on comparison instruction is deprecated")); |
17593 | ||
037e8744 JB |
17594 | /* The value which unconditional instructions should have in place of the |
17595 | condition field. */ | |
17596 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; | |
17597 | ||
c19d1205 | 17598 | if (thumb_mode) |
b99bd4ef | 17599 | { |
e74cfd16 | 17600 | arm_feature_set variant; |
8f06b2d8 PB |
17601 | |
17602 | variant = cpu_variant; | |
17603 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
17604 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
17605 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 17606 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
17607 | if (!opcode->tvariant |
17608 | || (thumb_mode == 1 | |
17609 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 17610 | { |
bf3eeda7 | 17611 | as_bad (_("selected processor does not support Thumb mode `%s'"), str); |
b99bd4ef NC |
17612 | return; |
17613 | } | |
c19d1205 ZW |
17614 | if (inst.cond != COND_ALWAYS && !unified_syntax |
17615 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 17616 | { |
c19d1205 | 17617 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
17618 | return; |
17619 | } | |
17620 | ||
752d5da4 | 17621 | if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)) |
076d447c | 17622 | { |
7e806470 | 17623 | if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23 |
752d5da4 NC |
17624 | && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr) |
17625 | || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier))) | |
17626 | { | |
17627 | /* Two things are addressed here. | |
17628 | 1) Implicit require narrow instructions on Thumb-1. | |
17629 | This avoids relaxation accidentally introducing Thumb-2 | |
17630 | instructions. | |
17631 | 2) Reject wide instructions in non Thumb-2 cores. */ | |
17632 | if (inst.size_req == 0) | |
17633 | inst.size_req = 2; | |
17634 | else if (inst.size_req == 4) | |
17635 | { | |
bf3eeda7 | 17636 | as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str); |
752d5da4 NC |
17637 | return; |
17638 | } | |
17639 | } | |
076d447c PB |
17640 | } |
17641 | ||
c19d1205 ZW |
17642 | inst.instruction = opcode->tvalue; |
17643 | ||
5be8be5d | 17644 | if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE)) |
477330fc RM |
17645 | { |
17646 | /* Prepare the it_insn_type for those encodings that don't set | |
17647 | it. */ | |
17648 | it_fsm_pre_encode (); | |
c19d1205 | 17649 | |
477330fc | 17650 | opcode->tencode (); |
e07e6e58 | 17651 | |
477330fc RM |
17652 | it_fsm_post_encode (); |
17653 | } | |
e27ec89e | 17654 | |
0110f2b8 | 17655 | if (!(inst.error || inst.relax)) |
b99bd4ef | 17656 | { |
9c2799c2 | 17657 | gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
c19d1205 ZW |
17658 | inst.size = (inst.instruction > 0xffff ? 4 : 2); |
17659 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 17660 | { |
c19d1205 | 17661 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
17662 | return; |
17663 | } | |
17664 | } | |
076d447c PB |
17665 | |
17666 | /* Something has gone badly wrong if we try to relax a fixed size | |
477330fc | 17667 | instruction. */ |
9c2799c2 | 17668 | gas_assert (inst.size_req == 0 || !inst.relax); |
076d447c | 17669 | |
e74cfd16 PB |
17670 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
17671 | *opcode->tvariant); | |
ee065d83 | 17672 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
708587a4 | 17673 | set those bits when Thumb-2 32-bit instructions are seen. ie. |
7e806470 | 17674 | anything other than bl/blx and v6-M instructions. |
ee065d83 | 17675 | This is overly pessimistic for relaxable instructions. */ |
7e806470 PB |
17676 | if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) |
17677 | || inst.relax) | |
e07e6e58 NC |
17678 | && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) |
17679 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))) | |
e74cfd16 PB |
17680 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
17681 | arm_ext_v6t2); | |
cd000bff | 17682 | |
88714cb8 DG |
17683 | check_neon_suffixes; |
17684 | ||
cd000bff | 17685 | if (!inst.error) |
c877a2f2 NC |
17686 | { |
17687 | mapping_state (MAP_THUMB); | |
17688 | } | |
c19d1205 | 17689 | } |
3e9e4fcf | 17690 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 | 17691 | { |
845b51d6 PB |
17692 | bfd_boolean is_bx; |
17693 | ||
17694 | /* bx is allowed on v5 cores, and sometimes on v4 cores. */ | |
17695 | is_bx = (opcode->aencode == do_bx); | |
17696 | ||
c19d1205 | 17697 | /* Check that this instruction is supported for this CPU. */ |
845b51d6 PB |
17698 | if (!(is_bx && fix_v4bx) |
17699 | && !(opcode->avariant && | |
17700 | ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) | |
b99bd4ef | 17701 | { |
bf3eeda7 | 17702 | as_bad (_("selected processor does not support ARM mode `%s'"), str); |
c19d1205 | 17703 | return; |
b99bd4ef | 17704 | } |
c19d1205 | 17705 | if (inst.size_req) |
b99bd4ef | 17706 | { |
c19d1205 ZW |
17707 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
17708 | return; | |
b99bd4ef NC |
17709 | } |
17710 | ||
c19d1205 ZW |
17711 | inst.instruction = opcode->avalue; |
17712 | if (opcode->tag == OT_unconditionalF) | |
17713 | inst.instruction |= 0xF << 28; | |
17714 | else | |
17715 | inst.instruction |= inst.cond << 28; | |
17716 | inst.size = INSN_SIZE; | |
5be8be5d | 17717 | if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE)) |
477330fc RM |
17718 | { |
17719 | it_fsm_pre_encode (); | |
17720 | opcode->aencode (); | |
17721 | it_fsm_post_encode (); | |
17722 | } | |
ee065d83 | 17723 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
477330fc | 17724 | on a hypothetical non-thumb v5 core. */ |
845b51d6 | 17725 | if (is_bx) |
e74cfd16 | 17726 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); |
ee065d83 | 17727 | else |
e74cfd16 PB |
17728 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
17729 | *opcode->avariant); | |
88714cb8 DG |
17730 | |
17731 | check_neon_suffixes; | |
17732 | ||
cd000bff | 17733 | if (!inst.error) |
c877a2f2 NC |
17734 | { |
17735 | mapping_state (MAP_ARM); | |
17736 | } | |
b99bd4ef | 17737 | } |
3e9e4fcf JB |
17738 | else |
17739 | { | |
17740 | as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " | |
17741 | "-- `%s'"), str); | |
17742 | return; | |
17743 | } | |
c19d1205 ZW |
17744 | output_inst (str); |
17745 | } | |
b99bd4ef | 17746 | |
e07e6e58 NC |
17747 | static void |
17748 | check_it_blocks_finished (void) | |
17749 | { | |
17750 | #ifdef OBJ_ELF | |
17751 | asection *sect; | |
17752 | ||
17753 | for (sect = stdoutput->sections; sect != NULL; sect = sect->next) | |
17754 | if (seg_info (sect)->tc_segment_info_data.current_it.state | |
17755 | == MANUAL_IT_BLOCK) | |
17756 | { | |
17757 | as_warn (_("section '%s' finished with an open IT block."), | |
17758 | sect->name); | |
17759 | } | |
17760 | #else | |
17761 | if (now_it.state == MANUAL_IT_BLOCK) | |
17762 | as_warn (_("file finished with an open IT block.")); | |
17763 | #endif | |
17764 | } | |
17765 | ||
c19d1205 ZW |
17766 | /* Various frobbings of labels and their addresses. */ |
17767 | ||
17768 | void | |
17769 | arm_start_line_hook (void) | |
17770 | { | |
17771 | last_label_seen = NULL; | |
b99bd4ef NC |
17772 | } |
17773 | ||
c19d1205 ZW |
17774 | void |
17775 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 17776 | { |
c19d1205 | 17777 | last_label_seen = sym; |
b99bd4ef | 17778 | |
c19d1205 | 17779 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 17780 | |
c19d1205 ZW |
17781 | #if defined OBJ_COFF || defined OBJ_ELF |
17782 | ARM_SET_INTERWORK (sym, support_interwork); | |
17783 | #endif | |
b99bd4ef | 17784 | |
e07e6e58 NC |
17785 | force_automatic_it_block_close (); |
17786 | ||
5f4273c7 | 17787 | /* Note - do not allow local symbols (.Lxxx) to be labelled |
c19d1205 ZW |
17788 | as Thumb functions. This is because these labels, whilst |
17789 | they exist inside Thumb code, are not the entry points for | |
17790 | possible ARM->Thumb calls. Also, these labels can be used | |
17791 | as part of a computed goto or switch statement. eg gcc | |
17792 | can generate code that looks like this: | |
b99bd4ef | 17793 | |
c19d1205 ZW |
17794 | ldr r2, [pc, .Laaa] |
17795 | lsl r3, r3, #2 | |
17796 | ldr r2, [r3, r2] | |
17797 | mov pc, r2 | |
b99bd4ef | 17798 | |
c19d1205 ZW |
17799 | .Lbbb: .word .Lxxx |
17800 | .Lccc: .word .Lyyy | |
17801 | ..etc... | |
17802 | .Laaa: .word Lbbb | |
b99bd4ef | 17803 | |
c19d1205 ZW |
17804 | The first instruction loads the address of the jump table. |
17805 | The second instruction converts a table index into a byte offset. | |
17806 | The third instruction gets the jump address out of the table. | |
17807 | The fourth instruction performs the jump. | |
b99bd4ef | 17808 | |
c19d1205 ZW |
17809 | If the address stored at .Laaa is that of a symbol which has the |
17810 | Thumb_Func bit set, then the linker will arrange for this address | |
17811 | to have the bottom bit set, which in turn would mean that the | |
17812 | address computation performed by the third instruction would end | |
17813 | up with the bottom bit set. Since the ARM is capable of unaligned | |
17814 | word loads, the instruction would then load the incorrect address | |
17815 | out of the jump table, and chaos would ensue. */ | |
17816 | if (label_is_thumb_function_name | |
17817 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
17818 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 17819 | { |
c19d1205 ZW |
17820 | /* When the address of a Thumb function is taken the bottom |
17821 | bit of that address should be set. This will allow | |
17822 | interworking between Arm and Thumb functions to work | |
17823 | correctly. */ | |
b99bd4ef | 17824 | |
c19d1205 | 17825 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 17826 | |
c19d1205 | 17827 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 17828 | } |
07a53e5c | 17829 | |
07a53e5c | 17830 | dwarf2_emit_label (sym); |
b99bd4ef NC |
17831 | } |
17832 | ||
c921be7d | 17833 | bfd_boolean |
c19d1205 | 17834 | arm_data_in_code (void) |
b99bd4ef | 17835 | { |
c19d1205 | 17836 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 17837 | { |
c19d1205 ZW |
17838 | *input_line_pointer = '/'; |
17839 | input_line_pointer += 5; | |
17840 | *input_line_pointer = 0; | |
c921be7d | 17841 | return TRUE; |
b99bd4ef NC |
17842 | } |
17843 | ||
c921be7d | 17844 | return FALSE; |
b99bd4ef NC |
17845 | } |
17846 | ||
c19d1205 ZW |
17847 | char * |
17848 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 17849 | { |
c19d1205 | 17850 | int len; |
b99bd4ef | 17851 | |
c19d1205 ZW |
17852 | if (thumb_mode && (len = strlen (name)) > 5 |
17853 | && streq (name + len - 5, "/data")) | |
17854 | *(name + len - 5) = 0; | |
b99bd4ef | 17855 | |
c19d1205 | 17856 | return name; |
b99bd4ef | 17857 | } |
c19d1205 ZW |
17858 | \f |
17859 | /* Table of all register names defined by default. The user can | |
17860 | define additional names with .req. Note that all register names | |
17861 | should appear in both upper and lowercase variants. Some registers | |
17862 | also have mixed-case names. */ | |
b99bd4ef | 17863 | |
dcbf9037 | 17864 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
c19d1205 | 17865 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
5287ad62 | 17866 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
c19d1205 ZW |
17867 | #define REGSET(p,t) \ |
17868 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
17869 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
17870 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
17871 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
5287ad62 JB |
17872 | #define REGSETH(p,t) \ |
17873 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
17874 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
17875 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
17876 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) | |
17877 | #define REGSET2(p,t) \ | |
17878 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ | |
17879 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ | |
17880 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ | |
17881 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) | |
90ec0d68 MGD |
17882 | #define SPLRBANK(base,bank,t) \ |
17883 | REGDEF(lr_##bank, 768|((base+0)<<16), t), \ | |
17884 | REGDEF(sp_##bank, 768|((base+1)<<16), t), \ | |
17885 | REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \ | |
17886 | REGDEF(LR_##bank, 768|((base+0)<<16), t), \ | |
17887 | REGDEF(SP_##bank, 768|((base+1)<<16), t), \ | |
17888 | REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t) | |
7ed4c4c5 | 17889 | |
c19d1205 | 17890 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 17891 | { |
c19d1205 ZW |
17892 | /* ARM integer registers. */ |
17893 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 17894 | |
c19d1205 ZW |
17895 | /* ATPCS synonyms. */ |
17896 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
17897 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
17898 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 17899 | |
c19d1205 ZW |
17900 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
17901 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
17902 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 17903 | |
c19d1205 ZW |
17904 | /* Well-known aliases. */ |
17905 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
17906 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
17907 | ||
17908 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
17909 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
17910 | ||
17911 | /* Coprocessor numbers. */ | |
17912 | REGSET(p, CP), REGSET(P, CP), | |
17913 | ||
17914 | /* Coprocessor register numbers. The "cr" variants are for backward | |
17915 | compatibility. */ | |
17916 | REGSET(c, CN), REGSET(C, CN), | |
17917 | REGSET(cr, CN), REGSET(CR, CN), | |
17918 | ||
90ec0d68 MGD |
17919 | /* ARM banked registers. */ |
17920 | REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB), | |
17921 | REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB), | |
17922 | REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB), | |
17923 | REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB), | |
17924 | REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB), | |
17925 | REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB), | |
17926 | REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB), | |
17927 | ||
17928 | REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB), | |
17929 | REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB), | |
17930 | REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB), | |
17931 | REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB), | |
17932 | REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB), | |
1472d06f | 17933 | REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB), |
90ec0d68 MGD |
17934 | REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB), |
17935 | REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB), | |
17936 | ||
17937 | SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB), | |
17938 | SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB), | |
17939 | SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB), | |
17940 | SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB), | |
17941 | SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB), | |
17942 | REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB), | |
17943 | REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB), | |
fa94de6b | 17944 | REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB), |
90ec0d68 MGD |
17945 | REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB), |
17946 | ||
c19d1205 ZW |
17947 | /* FPA registers. */ |
17948 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
17949 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
17950 | ||
17951 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
17952 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
17953 | ||
17954 | /* VFP SP registers. */ | |
5287ad62 JB |
17955 | REGSET(s,VFS), REGSET(S,VFS), |
17956 | REGSETH(s,VFS), REGSETH(S,VFS), | |
c19d1205 ZW |
17957 | |
17958 | /* VFP DP Registers. */ | |
5287ad62 JB |
17959 | REGSET(d,VFD), REGSET(D,VFD), |
17960 | /* Extra Neon DP registers. */ | |
17961 | REGSETH(d,VFD), REGSETH(D,VFD), | |
17962 | ||
17963 | /* Neon QP registers. */ | |
17964 | REGSET2(q,NQ), REGSET2(Q,NQ), | |
c19d1205 ZW |
17965 | |
17966 | /* VFP control registers. */ | |
17967 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
17968 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
cd2cf30b PB |
17969 | REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), |
17970 | REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), | |
17971 | REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), | |
17972 | REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), | |
c19d1205 ZW |
17973 | |
17974 | /* Maverick DSP coprocessor registers. */ | |
17975 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
17976 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
17977 | ||
17978 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
17979 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
17980 | REGDEF(dspsc,0,DSPSC), | |
17981 | ||
17982 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
17983 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
17984 | REGDEF(DSPSC,0,DSPSC), | |
17985 | ||
17986 | /* iWMMXt data registers - p0, c0-15. */ | |
17987 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
17988 | ||
17989 | /* iWMMXt control registers - p1, c0-3. */ | |
17990 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
17991 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
17992 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
17993 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
17994 | ||
17995 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
17996 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
17997 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
17998 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
17999 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
18000 | ||
18001 | /* XScale accumulator registers. */ | |
18002 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
18003 | }; | |
18004 | #undef REGDEF | |
18005 | #undef REGNUM | |
18006 | #undef REGSET | |
7ed4c4c5 | 18007 | |
c19d1205 ZW |
18008 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
18009 | within psr_required_here. */ | |
18010 | static const struct asm_psr psrs[] = | |
18011 | { | |
18012 | /* Backward compatibility notation. Note that "all" is no longer | |
18013 | truly all possible PSR bits. */ | |
18014 | {"all", PSR_c | PSR_f}, | |
18015 | {"flg", PSR_f}, | |
18016 | {"ctl", PSR_c}, | |
18017 | ||
18018 | /* Individual flags. */ | |
18019 | {"f", PSR_f}, | |
18020 | {"c", PSR_c}, | |
18021 | {"x", PSR_x}, | |
18022 | {"s", PSR_s}, | |
59b42a0d | 18023 | |
c19d1205 ZW |
18024 | /* Combinations of flags. */ |
18025 | {"fs", PSR_f | PSR_s}, | |
18026 | {"fx", PSR_f | PSR_x}, | |
18027 | {"fc", PSR_f | PSR_c}, | |
18028 | {"sf", PSR_s | PSR_f}, | |
18029 | {"sx", PSR_s | PSR_x}, | |
18030 | {"sc", PSR_s | PSR_c}, | |
18031 | {"xf", PSR_x | PSR_f}, | |
18032 | {"xs", PSR_x | PSR_s}, | |
18033 | {"xc", PSR_x | PSR_c}, | |
18034 | {"cf", PSR_c | PSR_f}, | |
18035 | {"cs", PSR_c | PSR_s}, | |
18036 | {"cx", PSR_c | PSR_x}, | |
18037 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
18038 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
18039 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
18040 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
18041 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
18042 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
18043 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
18044 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
18045 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
18046 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
18047 | {"scf", PSR_s | PSR_c | PSR_f}, | |
18048 | {"scx", PSR_s | PSR_c | PSR_x}, | |
18049 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
18050 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
18051 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
18052 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
18053 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
18054 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
18055 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
18056 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
18057 | {"csf", PSR_c | PSR_s | PSR_f}, | |
18058 | {"csx", PSR_c | PSR_s | PSR_x}, | |
18059 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
18060 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
18061 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
18062 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
18063 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
18064 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
18065 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
18066 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
18067 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
18068 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
18069 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
18070 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
18071 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
18072 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
18073 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
18074 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
18075 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
18076 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
18077 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
18078 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
18079 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
18080 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
18081 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
18082 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
18083 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
18084 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
18085 | }; | |
18086 | ||
62b3e311 PB |
18087 | /* Table of V7M psr names. */ |
18088 | static const struct asm_psr v7m_psrs[] = | |
18089 | { | |
2b744c99 PB |
18090 | {"apsr", 0 }, {"APSR", 0 }, |
18091 | {"iapsr", 1 }, {"IAPSR", 1 }, | |
18092 | {"eapsr", 2 }, {"EAPSR", 2 }, | |
18093 | {"psr", 3 }, {"PSR", 3 }, | |
18094 | {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, | |
18095 | {"ipsr", 5 }, {"IPSR", 5 }, | |
18096 | {"epsr", 6 }, {"EPSR", 6 }, | |
18097 | {"iepsr", 7 }, {"IEPSR", 7 }, | |
18098 | {"msp", 8 }, {"MSP", 8 }, | |
18099 | {"psp", 9 }, {"PSP", 9 }, | |
18100 | {"primask", 16}, {"PRIMASK", 16}, | |
18101 | {"basepri", 17}, {"BASEPRI", 17}, | |
00bbc0bd NC |
18102 | {"basepri_max", 18}, {"BASEPRI_MAX", 18}, |
18103 | {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */ | |
2b744c99 PB |
18104 | {"faultmask", 19}, {"FAULTMASK", 19}, |
18105 | {"control", 20}, {"CONTROL", 20} | |
62b3e311 PB |
18106 | }; |
18107 | ||
c19d1205 ZW |
18108 | /* Table of all shift-in-operand names. */ |
18109 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 18110 | { |
c19d1205 ZW |
18111 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
18112 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
18113 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
18114 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
18115 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
18116 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
18117 | }; | |
b99bd4ef | 18118 | |
c19d1205 ZW |
18119 | /* Table of all explicit relocation names. */ |
18120 | #ifdef OBJ_ELF | |
18121 | static struct reloc_entry reloc_names[] = | |
18122 | { | |
18123 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
18124 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
18125 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
18126 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
18127 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
18128 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
18129 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
18130 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
18131 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
18132 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
b43420e6 | 18133 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}, |
0855e32b NS |
18134 | { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL}, |
18135 | { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC}, | |
477330fc | 18136 | { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC}, |
0855e32b | 18137 | { "tlscall", BFD_RELOC_ARM_TLS_CALL}, |
477330fc | 18138 | { "TLSCALL", BFD_RELOC_ARM_TLS_CALL}, |
0855e32b | 18139 | { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ}, |
477330fc | 18140 | { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ} |
c19d1205 ZW |
18141 | }; |
18142 | #endif | |
b99bd4ef | 18143 | |
c19d1205 ZW |
18144 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
18145 | static const struct asm_cond conds[] = | |
18146 | { | |
18147 | {"eq", 0x0}, | |
18148 | {"ne", 0x1}, | |
18149 | {"cs", 0x2}, {"hs", 0x2}, | |
18150 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
18151 | {"mi", 0x4}, | |
18152 | {"pl", 0x5}, | |
18153 | {"vs", 0x6}, | |
18154 | {"vc", 0x7}, | |
18155 | {"hi", 0x8}, | |
18156 | {"ls", 0x9}, | |
18157 | {"ge", 0xa}, | |
18158 | {"lt", 0xb}, | |
18159 | {"gt", 0xc}, | |
18160 | {"le", 0xd}, | |
18161 | {"al", 0xe} | |
18162 | }; | |
bfae80f2 | 18163 | |
e797f7e0 MGD |
18164 | #define UL_BARRIER(L,U,CODE,FEAT) \ |
18165 | { L, CODE, ARM_FEATURE (FEAT, 0) }, \ | |
18166 | { U, CODE, ARM_FEATURE (FEAT, 0) } | |
18167 | ||
62b3e311 PB |
18168 | static struct asm_barrier_opt barrier_opt_names[] = |
18169 | { | |
e797f7e0 MGD |
18170 | UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER), |
18171 | UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER), | |
18172 | UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8), | |
18173 | UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER), | |
18174 | UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER), | |
18175 | UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER), | |
18176 | UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER), | |
18177 | UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8), | |
18178 | UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER), | |
18179 | UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER), | |
18180 | UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER), | |
18181 | UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER), | |
18182 | UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8), | |
18183 | UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER), | |
18184 | UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER), | |
18185 | UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8) | |
62b3e311 PB |
18186 | }; |
18187 | ||
e797f7e0 MGD |
18188 | #undef UL_BARRIER |
18189 | ||
c19d1205 ZW |
18190 | /* Table of ARM-format instructions. */ |
18191 | ||
18192 | /* Macros for gluing together operand strings. N.B. In all cases | |
18193 | other than OPS0, the trailing OP_stop comes from default | |
18194 | zero-initialization of the unspecified elements of the array. */ | |
18195 | #define OPS0() { OP_stop, } | |
18196 | #define OPS1(a) { OP_##a, } | |
18197 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
18198 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
18199 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
18200 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
18201 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
18202 | ||
5be8be5d DG |
18203 | /* These macros are similar to the OPSn, but do not prepend the OP_ prefix. |
18204 | This is useful when mixing operands for ARM and THUMB, i.e. using the | |
18205 | MIX_ARM_THUMB_OPERANDS macro. | |
18206 | In order to use these macros, prefix the number of operands with _ | |
18207 | e.g. _3. */ | |
18208 | #define OPS_1(a) { a, } | |
18209 | #define OPS_2(a,b) { a,b, } | |
18210 | #define OPS_3(a,b,c) { a,b,c, } | |
18211 | #define OPS_4(a,b,c,d) { a,b,c,d, } | |
18212 | #define OPS_5(a,b,c,d,e) { a,b,c,d,e, } | |
18213 | #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, } | |
18214 | ||
c19d1205 ZW |
18215 | /* These macros abstract out the exact format of the mnemonic table and |
18216 | save some repeated characters. */ | |
18217 | ||
18218 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
18219 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 18220 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 18221 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
18222 | |
18223 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
18224 | a T_MNEM_xyz enumerator. */ | |
18225 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
e07e6e58 | 18226 | TxCE (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 18227 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 18228 | TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
18229 | |
18230 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
18231 | infix after the third character. */ | |
18232 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 18233 | { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 18234 | THUMB_VARIANT, do_##ae, do_##te } |
088fa78e | 18235 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 18236 | { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ |
088fa78e | 18237 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 18238 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 18239 | TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) |
088fa78e | 18240 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 18241 | TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 18242 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 18243 | TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
088fa78e | 18244 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 18245 | TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 | 18246 | |
c19d1205 | 18247 | /* Mnemonic that cannot be conditionalized. The ARM condition-code |
dfa9f0d5 PB |
18248 | field is still 0xE. Many of the Thumb variants can be executed |
18249 | conditionally, so this is checked separately. */ | |
c19d1205 | 18250 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 18251 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 18252 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 18253 | |
dd5181d5 KT |
18254 | /* Same as TUE but the encoding function for ARM and Thumb modes is the same. |
18255 | Used by mnemonics that have very minimal differences in the encoding for | |
18256 | ARM and Thumb variants and can be handled in a common function. */ | |
18257 | #define TUEc(mnem, op, top, nops, ops, en) \ | |
18258 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ | |
18259 | THUMB_VARIANT, do_##en, do_##en } | |
18260 | ||
c19d1205 ZW |
18261 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM |
18262 | condition code field. */ | |
18263 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 18264 | { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 18265 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
18266 | |
18267 | /* ARM-only variants of all the above. */ | |
6a86118a | 18268 | #define CE(mnem, op, nops, ops, ae) \ |
21d799b5 | 18269 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
6a86118a NC |
18270 | |
18271 | #define C3(mnem, op, nops, ops, ae) \ | |
18272 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
18273 | ||
e3cb604e PB |
18274 | /* Legacy mnemonics that always have conditional infix after the third |
18275 | character. */ | |
18276 | #define CL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 18277 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
18278 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
18279 | ||
8f06b2d8 PB |
18280 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
18281 | #define cCE(mnem, op, nops, ops, ae) \ | |
21d799b5 | 18282 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 18283 | |
e3cb604e PB |
18284 | /* Legacy coprocessor instructions where conditional infix and conditional |
18285 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
18286 | not just the potentially ambiguous ones. */ | |
18287 | #define cCL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 18288 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
18289 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
18290 | ||
18291 | /* Coprocessor, takes either a suffix or a position-3 infix | |
18292 | (for an FPA corner case). */ | |
18293 | #define C3E(mnem, op, nops, ops, ae) \ | |
21d799b5 | 18294 | { mnem, OPS##nops ops, OT_csuf_or_in3, \ |
e3cb604e | 18295 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 18296 | |
6a86118a | 18297 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
21d799b5 NC |
18298 | { m1 #m2 m3, OPS##nops ops, \ |
18299 | sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ | |
6a86118a NC |
18300 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
18301 | ||
18302 | #define CM(m1, m2, op, nops, ops, ae) \ | |
e07e6e58 NC |
18303 | xCM_ (m1, , m2, op, nops, ops, ae), \ |
18304 | xCM_ (m1, eq, m2, op, nops, ops, ae), \ | |
18305 | xCM_ (m1, ne, m2, op, nops, ops, ae), \ | |
18306 | xCM_ (m1, cs, m2, op, nops, ops, ae), \ | |
18307 | xCM_ (m1, hs, m2, op, nops, ops, ae), \ | |
18308 | xCM_ (m1, cc, m2, op, nops, ops, ae), \ | |
18309 | xCM_ (m1, ul, m2, op, nops, ops, ae), \ | |
18310 | xCM_ (m1, lo, m2, op, nops, ops, ae), \ | |
18311 | xCM_ (m1, mi, m2, op, nops, ops, ae), \ | |
18312 | xCM_ (m1, pl, m2, op, nops, ops, ae), \ | |
18313 | xCM_ (m1, vs, m2, op, nops, ops, ae), \ | |
18314 | xCM_ (m1, vc, m2, op, nops, ops, ae), \ | |
18315 | xCM_ (m1, hi, m2, op, nops, ops, ae), \ | |
18316 | xCM_ (m1, ls, m2, op, nops, ops, ae), \ | |
18317 | xCM_ (m1, ge, m2, op, nops, ops, ae), \ | |
18318 | xCM_ (m1, lt, m2, op, nops, ops, ae), \ | |
18319 | xCM_ (m1, gt, m2, op, nops, ops, ae), \ | |
18320 | xCM_ (m1, le, m2, op, nops, ops, ae), \ | |
18321 | xCM_ (m1, al, m2, op, nops, ops, ae) | |
6a86118a NC |
18322 | |
18323 | #define UE(mnem, op, nops, ops, ae) \ | |
18324 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
18325 | ||
18326 | #define UF(mnem, op, nops, ops, ae) \ | |
18327 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
18328 | ||
5287ad62 JB |
18329 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
18330 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we | |
18331 | use the same encoding function for each. */ | |
18332 | #define NUF(mnem, op, nops, ops, enc) \ | |
18333 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
18334 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } | |
18335 | ||
18336 | /* Neon data processing, version which indirects through neon_enc_tab for | |
18337 | the various overloaded versions of opcodes. */ | |
18338 | #define nUF(mnem, op, nops, ops, enc) \ | |
21d799b5 | 18339 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
18340 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
18341 | ||
18342 | /* Neon insn with conditional suffix for the ARM version, non-overloaded | |
18343 | version. */ | |
037e8744 JB |
18344 | #define NCE_tag(mnem, op, nops, ops, enc, tag) \ |
18345 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ | |
5287ad62 JB |
18346 | THUMB_VARIANT, do_##enc, do_##enc } |
18347 | ||
037e8744 | 18348 | #define NCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 18349 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
18350 | |
18351 | #define NCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 18352 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 18353 | |
5287ad62 | 18354 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
037e8744 | 18355 | #define nCE_tag(mnem, op, nops, ops, enc, tag) \ |
21d799b5 | 18356 | { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
18357 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
18358 | ||
037e8744 | 18359 | #define nCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 18360 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
18361 | |
18362 | #define nCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 18363 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 18364 | |
c19d1205 ZW |
18365 | #define do_0 0 |
18366 | ||
c19d1205 | 18367 | static const struct asm_opcode insns[] = |
bfae80f2 | 18368 | { |
74db7efb NC |
18369 | #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */ |
18370 | #define THUMB_VARIANT & arm_ext_v4t | |
21d799b5 NC |
18371 | tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c), |
18372 | tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
18373 | tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
18374 | tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
18375 | tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
18376 | tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
18377 | tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub), | |
18378 | tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub), | |
18379 | tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
18380 | tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
18381 | tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
18382 | tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
18383 | tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
18384 | tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
18385 | tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3), | |
18386 | tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3), | |
c19d1205 ZW |
18387 | |
18388 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
18389 | for setting PSR flag bits. They are obsolete in V6 and do not | |
18390 | have Thumb equivalents. */ | |
21d799b5 NC |
18391 | tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), |
18392 | tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), | |
18393 | CL("tstp", 110f000, 2, (RR, SH), cmp), | |
18394 | tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
18395 | tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
18396 | CL("cmpp", 150f000, 2, (RR, SH), cmp), | |
18397 | tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
18398 | tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
18399 | CL("cmnp", 170f000, 2, (RR, SH), cmp), | |
18400 | ||
18401 | tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp), | |
18402 | tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp), | |
18403 | tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst), | |
18404 | tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst), | |
18405 | ||
18406 | tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
5be8be5d DG |
18407 | tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), |
18408 | tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR, | |
18409 | OP_RRnpc), | |
18410 | OP_ADDRGLDR),ldst, t_ldst), | |
18411 | tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), | |
21d799b5 NC |
18412 | |
18413 | tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18414 | tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18415 | tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18416 | tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18417 | tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18418 | tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18419 | ||
18420 | TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), | |
18421 | TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), | |
18422 | tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), | |
18423 | TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), | |
bfae80f2 | 18424 | |
c19d1205 | 18425 | /* Pseudo ops. */ |
21d799b5 | 18426 | tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac | 18427 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
21d799b5 | 18428 | tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop), |
74db7efb | 18429 | tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf), |
c19d1205 ZW |
18430 | |
18431 | /* Thumb-compatibility pseudo ops. */ | |
21d799b5 NC |
18432 | tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift), |
18433 | tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift), | |
18434 | tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift), | |
18435 | tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
18436 | tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift), | |
18437 | tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift), | |
18438 | tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift), | |
18439 | tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift), | |
18440 | tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg), | |
18441 | tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg), | |
18442 | tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop), | |
18443 | tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop), | |
c19d1205 | 18444 | |
16a4cf17 | 18445 | /* These may simplify to neg. */ |
21d799b5 NC |
18446 | TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
18447 | TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
16a4cf17 | 18448 | |
c921be7d NC |
18449 | #undef THUMB_VARIANT |
18450 | #define THUMB_VARIANT & arm_ext_v6 | |
18451 | ||
21d799b5 | 18452 | TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
18453 | |
18454 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
c921be7d NC |
18455 | #undef THUMB_VARIANT |
18456 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18457 | ||
21d799b5 NC |
18458 | TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
18459 | TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
18460 | CL("teqp", 130f000, 2, (RR, SH), cmp), | |
c19d1205 | 18461 | |
5be8be5d DG |
18462 | TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
18463 | TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
18464 | TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt), | |
18465 | TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
c19d1205 | 18466 | |
21d799b5 NC |
18467 | TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
18468 | TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 18469 | |
21d799b5 NC |
18470 | TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
18471 | TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
18472 | |
18473 | /* V1 instructions with no Thumb analogue at all. */ | |
21d799b5 | 18474 | CE("rsc", 0e00000, 3, (RR, oRR, SH), arit), |
c19d1205 ZW |
18475 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), |
18476 | ||
18477 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
18478 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
18479 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
18480 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
18481 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
18482 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
18483 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
18484 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
18485 | ||
c921be7d NC |
18486 | #undef ARM_VARIANT |
18487 | #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ | |
18488 | #undef THUMB_VARIANT | |
18489 | #define THUMB_VARIANT & arm_ext_v4t | |
18490 | ||
21d799b5 NC |
18491 | tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
18492 | tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
c19d1205 | 18493 | |
c921be7d NC |
18494 | #undef THUMB_VARIANT |
18495 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18496 | ||
21d799b5 | 18497 | TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
c19d1205 ZW |
18498 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), |
18499 | ||
18500 | /* Generic coprocessor instructions. */ | |
21d799b5 NC |
18501 | TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
18502 | TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18503 | TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18504 | TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18505 | TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18506 | TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
db472d6f | 18507 | TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), |
c19d1205 | 18508 | |
c921be7d NC |
18509 | #undef ARM_VARIANT |
18510 | #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ | |
18511 | ||
21d799b5 | 18512 | CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
c19d1205 ZW |
18513 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
18514 | ||
c921be7d NC |
18515 | #undef ARM_VARIANT |
18516 | #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ | |
18517 | #undef THUMB_VARIANT | |
18518 | #define THUMB_VARIANT & arm_ext_msr | |
18519 | ||
d2cd1205 JB |
18520 | TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs), |
18521 | TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr), | |
c19d1205 | 18522 | |
c921be7d NC |
18523 | #undef ARM_VARIANT |
18524 | #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ | |
18525 | #undef THUMB_VARIANT | |
18526 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18527 | ||
21d799b5 NC |
18528 | TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
18529 | CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
18530 | TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
18531 | CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
18532 | TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
18533 | CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
18534 | TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
18535 | CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
c19d1205 | 18536 | |
c921be7d NC |
18537 | #undef ARM_VARIANT |
18538 | #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ | |
18539 | #undef THUMB_VARIANT | |
18540 | #define THUMB_VARIANT & arm_ext_v4t | |
18541 | ||
5be8be5d DG |
18542 | tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
18543 | tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
18544 | tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
18545 | tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
56c0a61f RE |
18546 | tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
18547 | tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
c19d1205 | 18548 | |
c921be7d NC |
18549 | #undef ARM_VARIANT |
18550 | #define ARM_VARIANT & arm_ext_v4t_5 | |
18551 | ||
c19d1205 ZW |
18552 | /* ARM Architecture 4T. */ |
18553 | /* Note: bx (and blx) are required on V5, even if the processor does | |
18554 | not support Thumb. */ | |
21d799b5 | 18555 | TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx), |
c19d1205 | 18556 | |
c921be7d NC |
18557 | #undef ARM_VARIANT |
18558 | #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ | |
18559 | #undef THUMB_VARIANT | |
18560 | #define THUMB_VARIANT & arm_ext_v5t | |
18561 | ||
c19d1205 ZW |
18562 | /* Note: blx has 2 variants; the .value coded here is for |
18563 | BLX(2). Only this variant has conditional execution. */ | |
21d799b5 NC |
18564 | TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx), |
18565 | TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
c19d1205 | 18566 | |
c921be7d NC |
18567 | #undef THUMB_VARIANT |
18568 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18569 | ||
21d799b5 NC |
18570 | TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
18571 | TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18572 | TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18573 | TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18574 | TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18575 | TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
18576 | TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
18577 | TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 18578 | |
c921be7d | 18579 | #undef ARM_VARIANT |
74db7efb NC |
18580 | #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ |
18581 | #undef THUMB_VARIANT | |
18582 | #define THUMB_VARIANT & arm_ext_v5exp | |
c921be7d | 18583 | |
21d799b5 NC |
18584 | TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
18585 | TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
18586 | TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
18587 | TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 18588 | |
21d799b5 NC |
18589 | TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
18590 | TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 18591 | |
21d799b5 NC |
18592 | TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
18593 | TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
18594 | TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
18595 | TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
c19d1205 | 18596 | |
21d799b5 NC |
18597 | TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
18598 | TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18599 | TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18600 | TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 18601 | |
21d799b5 NC |
18602 | TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
18603 | TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 18604 | |
03ee1b7f NC |
18605 | TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
18606 | TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
18607 | TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
18608 | TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
c19d1205 | 18609 | |
c921be7d | 18610 | #undef ARM_VARIANT |
74db7efb NC |
18611 | #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ |
18612 | #undef THUMB_VARIANT | |
18613 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 18614 | |
21d799b5 | 18615 | TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld), |
5be8be5d DG |
18616 | TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS), |
18617 | ldrd, t_ldstd), | |
18618 | TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp, | |
18619 | ADDRGLDRS), ldrd, t_ldstd), | |
c19d1205 | 18620 | |
21d799b5 NC |
18621 | TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
18622 | TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
c19d1205 | 18623 | |
c921be7d NC |
18624 | #undef ARM_VARIANT |
18625 | #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ | |
18626 | ||
21d799b5 | 18627 | TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
c19d1205 | 18628 | |
c921be7d NC |
18629 | #undef ARM_VARIANT |
18630 | #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ | |
18631 | #undef THUMB_VARIANT | |
18632 | #define THUMB_VARIANT & arm_ext_v6 | |
18633 | ||
21d799b5 NC |
18634 | TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
18635 | TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
18636 | tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
18637 | tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
18638 | tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
18639 | tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18640 | tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18641 | tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18642 | tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18643 | TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), | |
c19d1205 | 18644 | |
c921be7d NC |
18645 | #undef THUMB_VARIANT |
18646 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18647 | ||
5be8be5d DG |
18648 | TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), |
18649 | TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
18650 | strex, t_strex), | |
21d799b5 NC |
18651 | TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
18652 | TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 | 18653 | |
21d799b5 NC |
18654 | TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), |
18655 | TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
62b3e311 | 18656 | |
9e3c6df6 | 18657 | /* ARM V6 not included in V7M. */ |
c921be7d NC |
18658 | #undef THUMB_VARIANT |
18659 | #define THUMB_VARIANT & arm_ext_v6_notm | |
9e3c6df6 | 18660 | TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
d709e4e6 | 18661 | TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
9e3c6df6 PB |
18662 | UF(rfeib, 9900a00, 1, (RRw), rfe), |
18663 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
18664 | TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
18665 | TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
d709e4e6 RE |
18666 | UF(rfefa, 8100a00, 1, (RRw), rfe), |
18667 | TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
18668 | UF(rfeed, 9900a00, 1, (RRw), rfe), | |
9e3c6df6 | 18669 | TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
d709e4e6 RE |
18670 | TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
18671 | TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), | |
9e3c6df6 | 18672 | UF(srsib, 9c00500, 2, (oRRw, I31w), srs), |
d709e4e6 | 18673 | UF(srsfa, 9c00500, 2, (oRRw, I31w), srs), |
9e3c6df6 | 18674 | UF(srsda, 8400500, 2, (oRRw, I31w), srs), |
d709e4e6 | 18675 | UF(srsed, 8400500, 2, (oRRw, I31w), srs), |
9e3c6df6 | 18676 | TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), |
d709e4e6 | 18677 | TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), |
c921be7d | 18678 | |
9e3c6df6 PB |
18679 | /* ARM V6 not included in V7M (eg. integer SIMD). */ |
18680 | #undef THUMB_VARIANT | |
18681 | #define THUMB_VARIANT & arm_ext_v6_dsp | |
21d799b5 NC |
18682 | TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
18683 | TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), | |
18684 | TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
18685 | TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18686 | TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18687 | TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18688 | /* Old name for QASX. */ |
74db7efb | 18689 | TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 | 18690 | TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18691 | /* Old name for QSAX. */ |
74db7efb | 18692 | TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18693 | TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18694 | TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18695 | TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18696 | TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18697 | TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18698 | /* Old name for SASX. */ |
74db7efb | 18699 | TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18700 | TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18701 | TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 18702 | TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18703 | /* Old name for SHASX. */ |
21d799b5 | 18704 | TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
74db7efb | 18705 | TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18706 | /* Old name for SHSAX. */ |
21d799b5 NC |
18707 | TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18708 | TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18709 | TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18710 | TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18711 | /* Old name for SSAX. */ |
74db7efb | 18712 | TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18713 | TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18714 | TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18715 | TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18716 | TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18717 | TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18718 | /* Old name for UASX. */ |
74db7efb | 18719 | TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18720 | TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18721 | TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 18722 | TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18723 | /* Old name for UHASX. */ |
21d799b5 NC |
18724 | TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18725 | TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18726 | /* Old name for UHSAX. */ |
21d799b5 NC |
18727 | TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18728 | TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18729 | TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18730 | TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18731 | TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 18732 | TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18733 | /* Old name for UQASX. */ |
21d799b5 NC |
18734 | TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18735 | TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18736 | /* Old name for UQSAX. */ |
21d799b5 NC |
18737 | TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18738 | TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18739 | TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18740 | TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18741 | TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18742 | /* Old name for USAX. */ |
74db7efb | 18743 | TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 | 18744 | TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18745 | TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
18746 | TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
18747 | TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
18748 | TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18749 | TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
18750 | TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
18751 | TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
18752 | TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18753 | TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18754 | TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18755 | TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18756 | TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
18757 | TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
18758 | TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18759 | TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18760 | TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
18761 | TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
18762 | TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18763 | TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18764 | TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18765 | TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18766 | TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18767 | TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18768 | TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18769 | TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18770 | TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18771 | TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
21d799b5 NC |
18772 | TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
18773 | TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
18774 | TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18775 | TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18776 | TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
c19d1205 | 18777 | |
c921be7d NC |
18778 | #undef ARM_VARIANT |
18779 | #define ARM_VARIANT & arm_ext_v6k | |
18780 | #undef THUMB_VARIANT | |
18781 | #define THUMB_VARIANT & arm_ext_v6k | |
18782 | ||
21d799b5 NC |
18783 | tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), |
18784 | tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), | |
18785 | tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint), | |
18786 | tCE("sev", 320f004, _sev, 0, (), noargs, t_hint), | |
c19d1205 | 18787 | |
c921be7d NC |
18788 | #undef THUMB_VARIANT |
18789 | #define THUMB_VARIANT & arm_ext_v6_notm | |
5be8be5d DG |
18790 | TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb), |
18791 | ldrexd, t_ldrexd), | |
18792 | TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp, | |
18793 | RRnpcb), strexd, t_strexd), | |
ebdca51a | 18794 | |
c921be7d NC |
18795 | #undef THUMB_VARIANT |
18796 | #define THUMB_VARIANT & arm_ext_v6t2 | |
5be8be5d DG |
18797 | TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), |
18798 | rd_rn, rd_rn), | |
18799 | TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), | |
18800 | rd_rn, rd_rn), | |
18801 | TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
877807f8 | 18802 | strex, t_strexbh), |
5be8be5d | 18803 | TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), |
877807f8 | 18804 | strex, t_strexbh), |
21d799b5 | 18805 | TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
c19d1205 | 18806 | |
c921be7d | 18807 | #undef ARM_VARIANT |
f4c65163 | 18808 | #define ARM_VARIANT & arm_ext_sec |
74db7efb | 18809 | #undef THUMB_VARIANT |
f4c65163 | 18810 | #define THUMB_VARIANT & arm_ext_sec |
c921be7d | 18811 | |
21d799b5 | 18812 | TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 | 18813 | |
90ec0d68 MGD |
18814 | #undef ARM_VARIANT |
18815 | #define ARM_VARIANT & arm_ext_virt | |
18816 | #undef THUMB_VARIANT | |
18817 | #define THUMB_VARIANT & arm_ext_virt | |
18818 | ||
18819 | TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc), | |
18820 | TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs), | |
18821 | ||
c921be7d | 18822 | #undef ARM_VARIANT |
74db7efb | 18823 | #define ARM_VARIANT & arm_ext_v6t2 |
f4c65163 MGD |
18824 | #undef THUMB_VARIANT |
18825 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 18826 | |
21d799b5 NC |
18827 | TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
18828 | TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
18829 | TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
18830 | TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
c19d1205 | 18831 | |
21d799b5 NC |
18832 | TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
18833 | TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), | |
18834 | TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), | |
18835 | TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), | |
c19d1205 | 18836 | |
5be8be5d DG |
18837 | TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
18838 | TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
18839 | TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
18840 | TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
c19d1205 | 18841 | |
bf3eeda7 | 18842 | /* Thumb-only instructions. */ |
74db7efb | 18843 | #undef ARM_VARIANT |
bf3eeda7 NS |
18844 | #define ARM_VARIANT NULL |
18845 | TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz), | |
18846 | TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz), | |
c921be7d NC |
18847 | |
18848 | /* ARM does not really have an IT instruction, so always allow it. | |
18849 | The opcode is copied from Thumb in order to allow warnings in | |
18850 | -mimplicit-it=[never | arm] modes. */ | |
18851 | #undef ARM_VARIANT | |
18852 | #define ARM_VARIANT & arm_ext_v1 | |
18853 | ||
21d799b5 NC |
18854 | TUE("it", bf08, bf08, 1, (COND), it, t_it), |
18855 | TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), | |
18856 | TUE("ite", bf04, bf04, 1, (COND), it, t_it), | |
18857 | TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it), | |
18858 | TUE("itet", bf06, bf06, 1, (COND), it, t_it), | |
18859 | TUE("itte", bf0a, bf0a, 1, (COND), it, t_it), | |
18860 | TUE("itee", bf02, bf02, 1, (COND), it, t_it), | |
18861 | TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it), | |
18862 | TUE("itett", bf07, bf07, 1, (COND), it, t_it), | |
18863 | TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it), | |
18864 | TUE("iteet", bf03, bf03, 1, (COND), it, t_it), | |
18865 | TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it), | |
18866 | TUE("itete", bf05, bf05, 1, (COND), it, t_it), | |
18867 | TUE("ittee", bf09, bf09, 1, (COND), it, t_it), | |
18868 | TUE("iteee", bf01, bf01, 1, (COND), it, t_it), | |
1c444d06 | 18869 | /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ |
21d799b5 NC |
18870 | TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), |
18871 | TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), | |
c19d1205 | 18872 | |
92e90b6e | 18873 | /* Thumb2 only instructions. */ |
c921be7d NC |
18874 | #undef ARM_VARIANT |
18875 | #define ARM_VARIANT NULL | |
92e90b6e | 18876 | |
21d799b5 NC |
18877 | TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
18878 | TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
18879 | TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), | |
18880 | TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), | |
18881 | TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb), | |
18882 | TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb), | |
92e90b6e | 18883 | |
eea54501 MGD |
18884 | /* Hardware division instructions. */ |
18885 | #undef ARM_VARIANT | |
18886 | #define ARM_VARIANT & arm_ext_adiv | |
c921be7d NC |
18887 | #undef THUMB_VARIANT |
18888 | #define THUMB_VARIANT & arm_ext_div | |
18889 | ||
eea54501 MGD |
18890 | TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div), |
18891 | TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div), | |
62b3e311 | 18892 | |
7e806470 | 18893 | /* ARM V6M/V7 instructions. */ |
c921be7d NC |
18894 | #undef ARM_VARIANT |
18895 | #define ARM_VARIANT & arm_ext_barrier | |
18896 | #undef THUMB_VARIANT | |
18897 | #define THUMB_VARIANT & arm_ext_barrier | |
18898 | ||
ccb84d65 JB |
18899 | TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier), |
18900 | TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier), | |
18901 | TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier), | |
7e806470 | 18902 | |
62b3e311 | 18903 | /* ARM V7 instructions. */ |
c921be7d NC |
18904 | #undef ARM_VARIANT |
18905 | #define ARM_VARIANT & arm_ext_v7 | |
18906 | #undef THUMB_VARIANT | |
18907 | #define THUMB_VARIANT & arm_ext_v7 | |
18908 | ||
21d799b5 NC |
18909 | TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld), |
18910 | TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
62b3e311 | 18911 | |
74db7efb | 18912 | #undef ARM_VARIANT |
60e5ef9f | 18913 | #define ARM_VARIANT & arm_ext_mp |
74db7efb | 18914 | #undef THUMB_VARIANT |
60e5ef9f MGD |
18915 | #define THUMB_VARIANT & arm_ext_mp |
18916 | ||
18917 | TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld), | |
18918 | ||
53c4b28b MGD |
18919 | /* AArchv8 instructions. */ |
18920 | #undef ARM_VARIANT | |
18921 | #define ARM_VARIANT & arm_ext_v8 | |
18922 | #undef THUMB_VARIANT | |
18923 | #define THUMB_VARIANT & arm_ext_v8 | |
18924 | ||
18925 | tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint), | |
8884b720 | 18926 | TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt), |
4b8c8c02 RE |
18927 | TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
18928 | TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb), | |
9eb6c0f1 | 18929 | ldrexd, t_ldrexd), |
4b8c8c02 RE |
18930 | TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn), |
18931 | TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
18932 | TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb), | |
18933 | stlex, t_stlex), | |
18934 | TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), | |
9eb6c0f1 | 18935 | strexd, t_strexd), |
4b8c8c02 RE |
18936 | TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb), |
18937 | stlex, t_stlex), | |
18938 | TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb), | |
18939 | stlex, t_stlex), | |
18940 | TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
18941 | TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
18942 | TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
18943 | TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
18944 | TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
18945 | TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
53c4b28b | 18946 | |
8884b720 | 18947 | /* ARMv8 T32 only. */ |
74db7efb | 18948 | #undef ARM_VARIANT |
b79f7053 MGD |
18949 | #define ARM_VARIANT NULL |
18950 | TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs), | |
18951 | TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs), | |
18952 | TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs), | |
18953 | ||
33399f07 MGD |
18954 | /* FP for ARMv8. */ |
18955 | #undef ARM_VARIANT | |
74db7efb | 18956 | #define ARM_VARIANT & fpu_vfp_ext_armv8 |
33399f07 MGD |
18957 | #undef THUMB_VARIANT |
18958 | #define THUMB_VARIANT & fpu_vfp_ext_armv8 | |
18959 | ||
18960 | nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel), | |
18961 | nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel), | |
18962 | nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel), | |
18963 | nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel), | |
73924fbc MGD |
18964 | nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm), |
18965 | nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm), | |
7e8e6784 MGD |
18966 | nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta), |
18967 | nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn), | |
18968 | nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp), | |
18969 | nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm), | |
30bdf752 MGD |
18970 | nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr), |
18971 | nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz), | |
18972 | nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx), | |
18973 | nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta), | |
18974 | nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn), | |
18975 | nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp), | |
18976 | nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm), | |
33399f07 | 18977 | |
91ff7894 MGD |
18978 | /* Crypto v1 extensions. */ |
18979 | #undef ARM_VARIANT | |
18980 | #define ARM_VARIANT & fpu_crypto_ext_armv8 | |
18981 | #undef THUMB_VARIANT | |
18982 | #define THUMB_VARIANT & fpu_crypto_ext_armv8 | |
18983 | ||
18984 | nUF(aese, _aes, 2, (RNQ, RNQ), aese), | |
18985 | nUF(aesd, _aes, 2, (RNQ, RNQ), aesd), | |
18986 | nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc), | |
18987 | nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc), | |
48adcd8e MGD |
18988 | nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c), |
18989 | nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p), | |
18990 | nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m), | |
18991 | nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0), | |
18992 | nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h), | |
18993 | nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2), | |
18994 | nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1), | |
3c9017d2 MGD |
18995 | nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h), |
18996 | nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1), | |
18997 | nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0), | |
91ff7894 | 18998 | |
dd5181d5 | 18999 | #undef ARM_VARIANT |
74db7efb | 19000 | #define ARM_VARIANT & crc_ext_armv8 |
dd5181d5 KT |
19001 | #undef THUMB_VARIANT |
19002 | #define THUMB_VARIANT & crc_ext_armv8 | |
19003 | TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b), | |
19004 | TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h), | |
19005 | TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w), | |
19006 | TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb), | |
19007 | TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch), | |
19008 | TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw), | |
19009 | ||
c921be7d NC |
19010 | #undef ARM_VARIANT |
19011 | #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ | |
53c4b28b MGD |
19012 | #undef THUMB_VARIANT |
19013 | #define THUMB_VARIANT NULL | |
c921be7d | 19014 | |
21d799b5 NC |
19015 | cCE("wfs", e200110, 1, (RR), rd), |
19016 | cCE("rfs", e300110, 1, (RR), rd), | |
19017 | cCE("wfc", e400110, 1, (RR), rd), | |
19018 | cCE("rfc", e500110, 1, (RR), rd), | |
19019 | ||
19020 | cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19021 | cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19022 | cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19023 | cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19024 | ||
19025 | cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19026 | cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19027 | cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19028 | cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19029 | ||
19030 | cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm), | |
19031 | cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm), | |
19032 | cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm), | |
19033 | cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm), | |
19034 | cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm), | |
19035 | cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm), | |
19036 | cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm), | |
19037 | cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm), | |
19038 | cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm), | |
19039 | cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm), | |
19040 | cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm), | |
19041 | cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm), | |
19042 | ||
19043 | cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm), | |
19044 | cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm), | |
19045 | cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm), | |
19046 | cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm), | |
19047 | cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm), | |
19048 | cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm), | |
19049 | cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm), | |
19050 | cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm), | |
19051 | cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm), | |
19052 | cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm), | |
19053 | cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm), | |
19054 | cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm), | |
19055 | ||
19056 | cCL("abss", e208100, 2, (RF, RF_IF), rd_rm), | |
19057 | cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm), | |
19058 | cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm), | |
19059 | cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm), | |
19060 | cCL("absd", e208180, 2, (RF, RF_IF), rd_rm), | |
19061 | cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm), | |
19062 | cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm), | |
19063 | cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm), | |
19064 | cCL("abse", e288100, 2, (RF, RF_IF), rd_rm), | |
19065 | cCL("absep", e288120, 2, (RF, RF_IF), rd_rm), | |
19066 | cCL("absem", e288140, 2, (RF, RF_IF), rd_rm), | |
19067 | cCL("absez", e288160, 2, (RF, RF_IF), rd_rm), | |
19068 | ||
19069 | cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm), | |
19070 | cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm), | |
19071 | cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm), | |
19072 | cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm), | |
19073 | cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm), | |
19074 | cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm), | |
19075 | cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm), | |
19076 | cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm), | |
19077 | cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm), | |
19078 | cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm), | |
19079 | cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm), | |
19080 | cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm), | |
19081 | ||
19082 | cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm), | |
19083 | cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm), | |
19084 | cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm), | |
19085 | cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm), | |
19086 | cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm), | |
19087 | cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm), | |
19088 | cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm), | |
19089 | cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm), | |
19090 | cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm), | |
19091 | cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm), | |
19092 | cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm), | |
19093 | cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm), | |
19094 | ||
19095 | cCL("logs", e508100, 2, (RF, RF_IF), rd_rm), | |
19096 | cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm), | |
19097 | cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm), | |
19098 | cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm), | |
19099 | cCL("logd", e508180, 2, (RF, RF_IF), rd_rm), | |
19100 | cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm), | |
19101 | cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm), | |
19102 | cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm), | |
19103 | cCL("loge", e588100, 2, (RF, RF_IF), rd_rm), | |
19104 | cCL("logep", e588120, 2, (RF, RF_IF), rd_rm), | |
19105 | cCL("logem", e588140, 2, (RF, RF_IF), rd_rm), | |
19106 | cCL("logez", e588160, 2, (RF, RF_IF), rd_rm), | |
19107 | ||
19108 | cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm), | |
19109 | cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm), | |
19110 | cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm), | |
19111 | cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm), | |
19112 | cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm), | |
19113 | cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm), | |
19114 | cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm), | |
19115 | cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm), | |
19116 | cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm), | |
19117 | cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm), | |
19118 | cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm), | |
19119 | cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm), | |
19120 | ||
19121 | cCL("exps", e708100, 2, (RF, RF_IF), rd_rm), | |
19122 | cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm), | |
19123 | cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm), | |
19124 | cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm), | |
19125 | cCL("expd", e708180, 2, (RF, RF_IF), rd_rm), | |
19126 | cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm), | |
19127 | cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm), | |
19128 | cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm), | |
19129 | cCL("expe", e788100, 2, (RF, RF_IF), rd_rm), | |
19130 | cCL("expep", e788120, 2, (RF, RF_IF), rd_rm), | |
19131 | cCL("expem", e788140, 2, (RF, RF_IF), rd_rm), | |
19132 | cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm), | |
19133 | ||
19134 | cCL("sins", e808100, 2, (RF, RF_IF), rd_rm), | |
19135 | cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm), | |
19136 | cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm), | |
19137 | cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm), | |
19138 | cCL("sind", e808180, 2, (RF, RF_IF), rd_rm), | |
19139 | cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm), | |
19140 | cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm), | |
19141 | cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm), | |
19142 | cCL("sine", e888100, 2, (RF, RF_IF), rd_rm), | |
19143 | cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm), | |
19144 | cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm), | |
19145 | cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm), | |
19146 | ||
19147 | cCL("coss", e908100, 2, (RF, RF_IF), rd_rm), | |
19148 | cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm), | |
19149 | cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm), | |
19150 | cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm), | |
19151 | cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm), | |
19152 | cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm), | |
19153 | cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm), | |
19154 | cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm), | |
19155 | cCL("cose", e988100, 2, (RF, RF_IF), rd_rm), | |
19156 | cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm), | |
19157 | cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm), | |
19158 | cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm), | |
19159 | ||
19160 | cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm), | |
19161 | cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm), | |
19162 | cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm), | |
19163 | cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm), | |
19164 | cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm), | |
19165 | cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm), | |
19166 | cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm), | |
19167 | cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm), | |
19168 | cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm), | |
19169 | cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm), | |
19170 | cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm), | |
19171 | cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm), | |
19172 | ||
19173 | cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm), | |
19174 | cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm), | |
19175 | cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm), | |
19176 | cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm), | |
19177 | cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm), | |
19178 | cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm), | |
19179 | cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm), | |
19180 | cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm), | |
19181 | cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm), | |
19182 | cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm), | |
19183 | cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm), | |
19184 | cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm), | |
19185 | ||
19186 | cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm), | |
19187 | cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm), | |
19188 | cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm), | |
19189 | cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm), | |
19190 | cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm), | |
19191 | cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm), | |
19192 | cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm), | |
19193 | cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm), | |
19194 | cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm), | |
19195 | cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm), | |
19196 | cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm), | |
19197 | cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm), | |
19198 | ||
19199 | cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm), | |
19200 | cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm), | |
19201 | cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm), | |
19202 | cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm), | |
19203 | cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm), | |
19204 | cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm), | |
19205 | cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm), | |
19206 | cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm), | |
19207 | cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm), | |
19208 | cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm), | |
19209 | cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm), | |
19210 | cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm), | |
19211 | ||
19212 | cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm), | |
19213 | cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm), | |
19214 | cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm), | |
19215 | cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm), | |
19216 | cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm), | |
19217 | cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm), | |
19218 | cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm), | |
19219 | cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm), | |
19220 | cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm), | |
19221 | cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm), | |
19222 | cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm), | |
19223 | cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm), | |
19224 | ||
19225 | cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm), | |
19226 | cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm), | |
19227 | cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm), | |
19228 | cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm), | |
19229 | cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm), | |
19230 | cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm), | |
19231 | cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm), | |
19232 | cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm), | |
19233 | cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm), | |
19234 | cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm), | |
19235 | cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm), | |
19236 | cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm), | |
19237 | ||
19238 | cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19239 | cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19240 | cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19241 | cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19242 | cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19243 | cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19244 | cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19245 | cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19246 | cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19247 | cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19248 | cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19249 | cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19250 | ||
19251 | cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19252 | cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19253 | cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19254 | cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19255 | cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19256 | cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19257 | cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19258 | cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19259 | cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19260 | cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19261 | cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19262 | cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19263 | ||
19264 | cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19265 | cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19266 | cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19267 | cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19268 | cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19269 | cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19270 | cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19271 | cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19272 | cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19273 | cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19274 | cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19275 | cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19276 | ||
19277 | cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19278 | cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19279 | cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19280 | cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19281 | cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19282 | cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19283 | cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19284 | cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19285 | cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19286 | cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19287 | cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19288 | cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19289 | ||
19290 | cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19291 | cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19292 | cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19293 | cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19294 | cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19295 | cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19296 | cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19297 | cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19298 | cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19299 | cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19300 | cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19301 | cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19302 | ||
19303 | cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19304 | cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19305 | cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19306 | cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19307 | cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19308 | cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19309 | cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19310 | cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19311 | cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19312 | cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19313 | cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19314 | cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19315 | ||
19316 | cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19317 | cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19318 | cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19319 | cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19320 | cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19321 | cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19322 | cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19323 | cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19324 | cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19325 | cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19326 | cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19327 | cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19328 | ||
19329 | cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19330 | cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19331 | cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19332 | cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19333 | cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19334 | cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19335 | cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19336 | cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19337 | cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19338 | cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19339 | cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19340 | cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19341 | ||
19342 | cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19343 | cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19344 | cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19345 | cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19346 | cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19347 | cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19348 | cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19349 | cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19350 | cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19351 | cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19352 | cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19353 | cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19354 | ||
19355 | cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19356 | cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19357 | cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19358 | cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19359 | cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19360 | cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19361 | cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19362 | cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19363 | cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19364 | cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19365 | cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19366 | cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19367 | ||
19368 | cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19369 | cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19370 | cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19371 | cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19372 | cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19373 | cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19374 | cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19375 | cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19376 | cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19377 | cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19378 | cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19379 | cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19380 | ||
19381 | cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19382 | cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19383 | cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19384 | cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19385 | cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19386 | cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19387 | cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19388 | cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19389 | cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19390 | cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19391 | cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19392 | cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19393 | ||
19394 | cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19395 | cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19396 | cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19397 | cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19398 | cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19399 | cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19400 | cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19401 | cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19402 | cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19403 | cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19404 | cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19405 | cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19406 | ||
19407 | cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp), | |
19408 | C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp), | |
19409 | cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp), | |
19410 | C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp), | |
19411 | ||
19412 | cCL("flts", e000110, 2, (RF, RR), rn_rd), | |
19413 | cCL("fltsp", e000130, 2, (RF, RR), rn_rd), | |
19414 | cCL("fltsm", e000150, 2, (RF, RR), rn_rd), | |
19415 | cCL("fltsz", e000170, 2, (RF, RR), rn_rd), | |
19416 | cCL("fltd", e000190, 2, (RF, RR), rn_rd), | |
19417 | cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd), | |
19418 | cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd), | |
19419 | cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd), | |
19420 | cCL("flte", e080110, 2, (RF, RR), rn_rd), | |
19421 | cCL("fltep", e080130, 2, (RF, RR), rn_rd), | |
19422 | cCL("fltem", e080150, 2, (RF, RR), rn_rd), | |
19423 | cCL("fltez", e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 19424 | |
c19d1205 ZW |
19425 | /* The implementation of the FIX instruction is broken on some |
19426 | assemblers, in that it accepts a precision specifier as well as a | |
19427 | rounding specifier, despite the fact that this is meaningless. | |
19428 | To be more compatible, we accept it as well, though of course it | |
19429 | does not set any bits. */ | |
21d799b5 NC |
19430 | cCE("fix", e100110, 2, (RR, RF), rd_rm), |
19431 | cCL("fixp", e100130, 2, (RR, RF), rd_rm), | |
19432 | cCL("fixm", e100150, 2, (RR, RF), rd_rm), | |
19433 | cCL("fixz", e100170, 2, (RR, RF), rd_rm), | |
19434 | cCL("fixsp", e100130, 2, (RR, RF), rd_rm), | |
19435 | cCL("fixsm", e100150, 2, (RR, RF), rd_rm), | |
19436 | cCL("fixsz", e100170, 2, (RR, RF), rd_rm), | |
19437 | cCL("fixdp", e100130, 2, (RR, RF), rd_rm), | |
19438 | cCL("fixdm", e100150, 2, (RR, RF), rd_rm), | |
19439 | cCL("fixdz", e100170, 2, (RR, RF), rd_rm), | |
19440 | cCL("fixep", e100130, 2, (RR, RF), rd_rm), | |
19441 | cCL("fixem", e100150, 2, (RR, RF), rd_rm), | |
19442 | cCL("fixez", e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 19443 | |
c19d1205 | 19444 | /* Instructions that were new with the real FPA, call them V2. */ |
c921be7d NC |
19445 | #undef ARM_VARIANT |
19446 | #define ARM_VARIANT & fpu_fpa_ext_v2 | |
19447 | ||
21d799b5 NC |
19448 | cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
19449 | cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
19450 | cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
19451 | cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
19452 | cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
19453 | cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 | 19454 | |
c921be7d NC |
19455 | #undef ARM_VARIANT |
19456 | #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ | |
19457 | ||
c19d1205 | 19458 | /* Moves and type conversions. */ |
21d799b5 NC |
19459 | cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
19460 | cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
19461 | cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
19462 | cCE("fmstat", ef1fa10, 0, (), noargs), | |
7465e07a NC |
19463 | cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs), |
19464 | cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr), | |
21d799b5 NC |
19465 | cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), |
19466 | cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
19467 | cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
19468 | cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
19469 | cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
19470 | cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
19471 | cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn), | |
19472 | cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
19473 | |
19474 | /* Memory operations. */ | |
21d799b5 NC |
19475 | cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
19476 | cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), | |
55881a11 MGD |
19477 | cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
19478 | cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
19479 | cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
19480 | cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
19481 | cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
19482 | cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
19483 | cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
19484 | cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
19485 | cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
19486 | cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
19487 | cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
19488 | cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
19489 | cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
19490 | cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
19491 | cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
19492 | cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 19493 | |
c19d1205 | 19494 | /* Monadic operations. */ |
21d799b5 NC |
19495 | cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
19496 | cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
19497 | cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
19498 | |
19499 | /* Dyadic operations. */ | |
21d799b5 NC |
19500 | cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
19501 | cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19502 | cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19503 | cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19504 | cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19505 | cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19506 | cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19507 | cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19508 | cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 19509 | |
c19d1205 | 19510 | /* Comparisons. */ |
21d799b5 NC |
19511 | cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
19512 | cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z), | |
19513 | cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
19514 | cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 19515 | |
62f3b8c8 PB |
19516 | /* Double precision load/store are still present on single precision |
19517 | implementations. */ | |
19518 | cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
19519 | cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
55881a11 MGD |
19520 | cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
19521 | cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
19522 | cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
19523 | cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
19524 | cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
19525 | cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
19526 | cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
19527 | cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
62f3b8c8 | 19528 | |
c921be7d NC |
19529 | #undef ARM_VARIANT |
19530 | #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ | |
19531 | ||
c19d1205 | 19532 | /* Moves and type conversions. */ |
21d799b5 NC |
19533 | cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
19534 | cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
19535 | cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
19536 | cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
19537 | cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
19538 | cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
19539 | cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
19540 | cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
19541 | cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
19542 | cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
19543 | cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
19544 | cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
19545 | cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 | 19546 | |
c19d1205 | 19547 | /* Monadic operations. */ |
21d799b5 NC |
19548 | cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
19549 | cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), | |
19550 | cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
c19d1205 ZW |
19551 | |
19552 | /* Dyadic operations. */ | |
21d799b5 NC |
19553 | cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
19554 | cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19555 | cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19556 | cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19557 | cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19558 | cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19559 | cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19560 | cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19561 | cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
b99bd4ef | 19562 | |
c19d1205 | 19563 | /* Comparisons. */ |
21d799b5 NC |
19564 | cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
19565 | cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd), | |
19566 | cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
19567 | cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd), | |
c19d1205 | 19568 | |
c921be7d NC |
19569 | #undef ARM_VARIANT |
19570 | #define ARM_VARIANT & fpu_vfp_ext_v2 | |
19571 | ||
21d799b5 NC |
19572 | cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
19573 | cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
19574 | cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), | |
19575 | cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), | |
5287ad62 | 19576 | |
037e8744 JB |
19577 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
19578 | Individual encoder functions perform additional architecture checks. */ | |
c921be7d NC |
19579 | #undef ARM_VARIANT |
19580 | #define ARM_VARIANT & fpu_vfp_ext_v1xd | |
19581 | #undef THUMB_VARIANT | |
19582 | #define THUMB_VARIANT & fpu_vfp_ext_v1xd | |
19583 | ||
037e8744 JB |
19584 | /* These mnemonics are unique to VFP. */ |
19585 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), | |
19586 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), | |
21d799b5 NC |
19587 | nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
19588 | nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
19589 | nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
aacf0b33 KT |
19590 | nCE(vcmp, _vcmp, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp), |
19591 | nCE(vcmpe, _vcmpe, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp), | |
037e8744 JB |
19592 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), |
19593 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), | |
19594 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), | |
19595 | ||
19596 | /* Mnemonics shared by Neon and VFP. */ | |
21d799b5 NC |
19597 | nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), |
19598 | nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
19599 | nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
037e8744 | 19600 | |
21d799b5 NC |
19601 | nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), |
19602 | nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), | |
037e8744 JB |
19603 | |
19604 | NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
19605 | NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
19606 | ||
55881a11 MGD |
19607 | NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
19608 | NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
19609 | NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
19610 | NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
19611 | NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
19612 | NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
4962c51a MS |
19613 | NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), |
19614 | NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), | |
037e8744 | 19615 | |
5f1af56b | 19616 | nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt), |
e3e535bc | 19617 | nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr), |
c70a8987 MGD |
19618 | NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb), |
19619 | NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt), | |
f31fef98 | 19620 | |
037e8744 JB |
19621 | |
19622 | /* NOTE: All VMOV encoding is special-cased! */ | |
19623 | NCE(vmov, 0, 1, (VMOV), neon_mov), | |
19624 | NCE(vmovq, 0, 1, (VMOV), neon_mov), | |
19625 | ||
c921be7d NC |
19626 | #undef THUMB_VARIANT |
19627 | #define THUMB_VARIANT & fpu_neon_ext_v1 | |
19628 | #undef ARM_VARIANT | |
19629 | #define ARM_VARIANT & fpu_neon_ext_v1 | |
19630 | ||
5287ad62 JB |
19631 | /* Data processing with three registers of the same length. */ |
19632 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ | |
19633 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), | |
19634 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), | |
19635 | NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
19636 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
19637 | NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
19638 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
19639 | NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
19640 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
19641 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ | |
19642 | NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
19643 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
19644 | NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
19645 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
627907b7 JB |
19646 | NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), |
19647 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
19648 | NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), | |
19649 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
5287ad62 JB |
19650 | /* If not immediate, fall back to neon_dyadic_i64_su. |
19651 | shl_imm should accept I8 I16 I32 I64, | |
19652 | qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ | |
21d799b5 NC |
19653 | nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), |
19654 | nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), | |
19655 | nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), | |
19656 | nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), | |
5287ad62 | 19657 | /* Logic ops, types optional & ignored. */ |
4316f0d2 DG |
19658 | nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), |
19659 | nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
19660 | nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
19661 | nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
19662 | nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
19663 | nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
19664 | nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
19665 | nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
19666 | nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), | |
19667 | nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic), | |
5287ad62 JB |
19668 | /* Bitfield ops, untyped. */ |
19669 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
19670 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
19671 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
19672 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
19673 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
19674 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
19675 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ | |
21d799b5 NC |
19676 | nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), |
19677 | nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
19678 | nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
19679 | nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
19680 | nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
19681 | nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
5287ad62 JB |
19682 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall |
19683 | back to neon_dyadic_if_su. */ | |
21d799b5 NC |
19684 | nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), |
19685 | nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
19686 | nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
19687 | nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
19688 | nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
19689 | nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
19690 | nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
19691 | nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
428e3f1f | 19692 | /* Comparison. Type I8 I16 I32 F32. */ |
21d799b5 NC |
19693 | nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), |
19694 | nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), | |
5287ad62 | 19695 | /* As above, D registers only. */ |
21d799b5 NC |
19696 | nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), |
19697 | nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
5287ad62 | 19698 | /* Int and float variants, signedness unimportant. */ |
21d799b5 NC |
19699 | nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
19700 | nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), | |
19701 | nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), | |
5287ad62 | 19702 | /* Add/sub take types I8 I16 I32 I64 F32. */ |
21d799b5 NC |
19703 | nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
19704 | nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), | |
5287ad62 JB |
19705 | /* vtst takes sizes 8, 16, 32. */ |
19706 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), | |
19707 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), | |
19708 | /* VMUL takes I8 I16 I32 F32 P8. */ | |
21d799b5 | 19709 | nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
5287ad62 | 19710 | /* VQD{R}MULH takes S16 S32. */ |
21d799b5 NC |
19711 | nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), |
19712 | nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
19713 | nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
19714 | nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
5287ad62 JB |
19715 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), |
19716 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
19717 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
19718 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
92559b5b PB |
19719 | NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
19720 | NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
19721 | NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
19722 | NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
5287ad62 JB |
19723 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
19724 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
19725 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
19726 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
19727 | ||
19728 | /* Two address, int/float. Types S8 S16 S32 F32. */ | |
5287ad62 | 19729 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
5287ad62 JB |
19730 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
19731 | ||
19732 | /* Data processing with two registers and a shift amount. */ | |
19733 | /* Right shifts, and variants with rounding. | |
19734 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ | |
19735 | NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
19736 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
19737 | NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
19738 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
19739 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
19740 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
19741 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
19742 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
19743 | /* Shift and insert. Sizes accepted 8 16 32 64. */ | |
19744 | NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), | |
19745 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), | |
19746 | NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), | |
19747 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), | |
19748 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ | |
19749 | NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), | |
19750 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), | |
19751 | /* Right shift immediate, saturating & narrowing, with rounding variants. | |
19752 | Types accepted S16 S32 S64 U16 U32 U64. */ | |
19753 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
19754 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
19755 | /* As above, unsigned. Types accepted S16 S32 S64. */ | |
19756 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
19757 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
19758 | /* Right shift narrowing. Types accepted I16 I32 I64. */ | |
19759 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
19760 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
19761 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ | |
21d799b5 | 19762 | nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll), |
5287ad62 | 19763 | /* CVT with optional immediate for fixed-point variant. */ |
21d799b5 | 19764 | nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
b7fc2769 | 19765 | |
4316f0d2 DG |
19766 | nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn), |
19767 | nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn), | |
5287ad62 JB |
19768 | |
19769 | /* Data processing, three registers of different lengths. */ | |
19770 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ | |
19771 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), | |
19772 | NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), | |
19773 | NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), | |
19774 | NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), | |
19775 | /* If not scalar, fall back to neon_dyadic_long. | |
19776 | Vector types as above, scalar types S16 S32 U16 U32. */ | |
21d799b5 NC |
19777 | nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), |
19778 | nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
5287ad62 JB |
19779 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ |
19780 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
19781 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
19782 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ | |
19783 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
19784 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
19785 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
19786 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
19787 | /* Saturating doubling multiplies. Types S16 S32. */ | |
21d799b5 NC |
19788 | nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
19789 | nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
19790 | nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
5287ad62 JB |
19791 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types |
19792 | S16 S32 U16 U32. */ | |
21d799b5 | 19793 | nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), |
5287ad62 JB |
19794 | |
19795 | /* Extract. Size 8. */ | |
3b8d421e PB |
19796 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), |
19797 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), | |
5287ad62 JB |
19798 | |
19799 | /* Two registers, miscellaneous. */ | |
19800 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ | |
19801 | NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), | |
19802 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), | |
19803 | NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), | |
19804 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), | |
19805 | NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), | |
19806 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), | |
19807 | /* Vector replicate. Sizes 8 16 32. */ | |
21d799b5 NC |
19808 | nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup), |
19809 | nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup), | |
5287ad62 JB |
19810 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ |
19811 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), | |
19812 | /* VMOVN. Types I16 I32 I64. */ | |
21d799b5 | 19813 | nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn), |
5287ad62 | 19814 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ |
21d799b5 | 19815 | nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn), |
5287ad62 | 19816 | /* VQMOVUN. Types S16 S32 S64. */ |
21d799b5 | 19817 | nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun), |
5287ad62 JB |
19818 | /* VZIP / VUZP. Sizes 8 16 32. */ |
19819 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
19820 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), | |
19821 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
19822 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), | |
19823 | /* VQABS / VQNEG. Types S8 S16 S32. */ | |
19824 | NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
19825 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
19826 | NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
19827 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
19828 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ | |
19829 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), | |
19830 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), | |
19831 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), | |
19832 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), | |
19833 | /* Reciprocal estimates. Types U32 F32. */ | |
19834 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), | |
19835 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), | |
19836 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), | |
19837 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), | |
19838 | /* VCLS. Types S8 S16 S32. */ | |
19839 | NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), | |
19840 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), | |
19841 | /* VCLZ. Types I8 I16 I32. */ | |
19842 | NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), | |
19843 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), | |
19844 | /* VCNT. Size 8. */ | |
19845 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), | |
19846 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), | |
19847 | /* Two address, untyped. */ | |
19848 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), | |
19849 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), | |
19850 | /* VTRN. Sizes 8 16 32. */ | |
21d799b5 NC |
19851 | nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn), |
19852 | nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn), | |
5287ad62 JB |
19853 | |
19854 | /* Table lookup. Size 8. */ | |
19855 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
19856 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
19857 | ||
c921be7d NC |
19858 | #undef THUMB_VARIANT |
19859 | #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext | |
19860 | #undef ARM_VARIANT | |
19861 | #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext | |
19862 | ||
5287ad62 | 19863 | /* Neon element/structure load/store. */ |
21d799b5 NC |
19864 | nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), |
19865 | nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
19866 | nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
19867 | nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
19868 | nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
19869 | nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
19870 | nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
19871 | nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
5287ad62 | 19872 | |
c921be7d | 19873 | #undef THUMB_VARIANT |
74db7efb NC |
19874 | #define THUMB_VARIANT & fpu_vfp_ext_v3xd |
19875 | #undef ARM_VARIANT | |
19876 | #define ARM_VARIANT & fpu_vfp_ext_v3xd | |
62f3b8c8 PB |
19877 | cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const), |
19878 | cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
19879 | cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
19880 | cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
19881 | cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
19882 | cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
19883 | cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
19884 | cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
19885 | cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
19886 | ||
74db7efb | 19887 | #undef THUMB_VARIANT |
c921be7d NC |
19888 | #define THUMB_VARIANT & fpu_vfp_ext_v3 |
19889 | #undef ARM_VARIANT | |
19890 | #define ARM_VARIANT & fpu_vfp_ext_v3 | |
19891 | ||
21d799b5 | 19892 | cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const), |
21d799b5 | 19893 | cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 19894 | cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 19895 | cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 19896 | cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 19897 | cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 19898 | cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 19899 | cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 19900 | cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
c19d1205 | 19901 | |
74db7efb NC |
19902 | #undef ARM_VARIANT |
19903 | #define ARM_VARIANT & fpu_vfp_ext_fma | |
19904 | #undef THUMB_VARIANT | |
19905 | #define THUMB_VARIANT & fpu_vfp_ext_fma | |
62f3b8c8 PB |
19906 | /* Mnemonics shared by Neon and VFP. These are included in the |
19907 | VFP FMA variant; NEON and VFP FMA always includes the NEON | |
19908 | FMA instructions. */ | |
19909 | nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
19910 | nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
19911 | /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas; | |
19912 | the v form should always be used. */ | |
19913 | cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19914 | cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19915 | cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19916 | cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19917 | nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
19918 | nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
19919 | ||
5287ad62 | 19920 | #undef THUMB_VARIANT |
c921be7d NC |
19921 | #undef ARM_VARIANT |
19922 | #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ | |
19923 | ||
21d799b5 NC |
19924 | cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
19925 | cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
19926 | cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
19927 | cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
19928 | cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
19929 | cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
19930 | cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
19931 | cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 | 19932 | |
c921be7d NC |
19933 | #undef ARM_VARIANT |
19934 | #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ | |
19935 | ||
21d799b5 NC |
19936 | cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc), |
19937 | cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc), | |
19938 | cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc), | |
19939 | cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd), | |
19940 | cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd), | |
19941 | cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd), | |
19942 | cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc), | |
19943 | cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc), | |
19944 | cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc), | |
74db7efb NC |
19945 | cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), |
19946 | cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
19947 | cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
19948 | cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
19949 | cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
19950 | cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
21d799b5 NC |
19951 | cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), |
19952 | cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
19953 | cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
19954 | cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd), | |
19955 | cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
19956 | cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
19957 | cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
19958 | cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
19959 | cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
19960 | cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
19961 | cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
74db7efb NC |
19962 | cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn), |
19963 | cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn), | |
19964 | cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn), | |
21d799b5 NC |
19965 | cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn), |
19966 | cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
19967 | cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc), | |
19968 | cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc), | |
19969 | cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc), | |
19970 | cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn), | |
19971 | cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn), | |
19972 | cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn), | |
19973 | cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19974 | cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19975 | cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19976 | cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19977 | cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19978 | cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19979 | cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19980 | cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19981 | cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19982 | cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
74db7efb NC |
19983 | cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
19984 | cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19985 | cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19986 | cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
19987 | cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
19988 | cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19989 | cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19990 | cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19991 | cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19992 | cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19993 | cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19994 | cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19995 | cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
74db7efb NC |
19996 | cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
19997 | cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19998 | cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19999 | cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20000 | cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20001 | cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
20002 | cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), |
20003 | cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
20004 | cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
20005 | cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
20006 | cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20007 | cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20008 | cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20009 | cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20010 | cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20011 | cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20012 | cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20013 | cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20014 | cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20015 | cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20016 | cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20017 | cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20018 | cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20019 | cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20020 | cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20021 | cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20022 | cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20023 | cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20024 | cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
20025 | cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20026 | cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20027 | cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20028 | cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20029 | cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
74db7efb NC |
20030 | cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
20031 | cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20032 | cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20033 | cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20034 | cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20035 | cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
20036 | cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
20037 | cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20038 | cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20039 | cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20040 | cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20041 | cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20042 | cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20043 | cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20044 | cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20045 | cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20046 | cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
20047 | cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20048 | cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20049 | cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20050 | cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20051 | cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20052 | cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20053 | cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20054 | cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20055 | cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20056 | cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20057 | cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20058 | cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20059 | cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20060 | cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20061 | cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20062 | cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20063 | cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20064 | cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20065 | cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
20066 | cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
20067 | cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
20068 | cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
20069 | cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20070 | cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20071 | cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20072 | cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20073 | cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20074 | cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20075 | cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20076 | cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20077 | cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20078 | cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn), | |
20079 | cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn), | |
20080 | cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn), | |
20081 | cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn), | |
20082 | cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn), | |
20083 | cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn), | |
20084 | cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20085 | cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20086 | cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20087 | cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn), | |
20088 | cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn), | |
20089 | cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn), | |
20090 | cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn), | |
20091 | cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn), | |
20092 | cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn), | |
20093 | cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20094 | cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20095 | cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20096 | cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20097 | cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 | 20098 | |
c921be7d NC |
20099 | #undef ARM_VARIANT |
20100 | #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ | |
20101 | ||
21d799b5 NC |
20102 | cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc), |
20103 | cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc), | |
20104 | cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc), | |
20105 | cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn), | |
20106 | cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn), | |
20107 | cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn), | |
20108 | cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20109 | cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20110 | cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20111 | cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20112 | cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20113 | cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20114 | cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20115 | cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20116 | cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20117 | cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20118 | cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20119 | cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20120 | cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20121 | cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20122 | cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), | |
20123 | cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20124 | cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20125 | cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20126 | cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20127 | cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20128 | cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20129 | cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20130 | cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20131 | cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20132 | cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20133 | cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20134 | cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20135 | cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20136 | cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20137 | cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20138 | cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20139 | cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20140 | cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20141 | cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20142 | cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20143 | cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20144 | cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20145 | cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20146 | cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20147 | cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20148 | cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20149 | cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20150 | cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20151 | cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20152 | cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20153 | cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20154 | cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20155 | cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20156 | cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20157 | cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20158 | cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
2d447fca | 20159 | |
c921be7d NC |
20160 | #undef ARM_VARIANT |
20161 | #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ | |
20162 | ||
21d799b5 NC |
20163 | cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
20164 | cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
20165 | cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
20166 | cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
20167 | cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), | |
20168 | cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
20169 | cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
20170 | cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
20171 | cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd), | |
20172 | cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn), | |
20173 | cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd), | |
20174 | cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn), | |
20175 | cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd), | |
20176 | cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn), | |
74db7efb NC |
20177 | cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd), |
20178 | cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn), | |
20179 | cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd), | |
20180 | cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn), | |
20181 | cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn), | |
20182 | cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn), | |
20183 | cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn), | |
20184 | cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn), | |
20185 | cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn), | |
20186 | cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn), | |
21d799b5 NC |
20187 | cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn), |
20188 | cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn), | |
20189 | cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn), | |
20190 | cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn), | |
74db7efb NC |
20191 | cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc), |
20192 | cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd), | |
21d799b5 NC |
20193 | cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn), |
20194 | cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn), | |
20195 | cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn), | |
20196 | cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn), | |
74db7efb NC |
20197 | cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn), |
20198 | cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn), | |
20199 | cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn), | |
20200 | cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn), | |
20201 | cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn), | |
20202 | cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn), | |
21d799b5 NC |
20203 | cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn), |
20204 | cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn), | |
74db7efb NC |
20205 | cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple), |
20206 | cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
21d799b5 NC |
20207 | cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift), |
20208 | cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
20209 | cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
20210 | cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
20211 | cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
20212 | cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
20213 | cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn), | |
20214 | cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn), | |
20215 | cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn), | |
20216 | cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn), | |
20217 | cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
20218 | cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
20219 | cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
20220 | cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
20221 | cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
20222 | cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
20223 | cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn), | |
20224 | cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn), | |
20225 | cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn), | |
20226 | cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn), | |
20227 | cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
20228 | cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
20229 | cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
20230 | cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
20231 | cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
20232 | cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
20233 | cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
20234 | cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
74db7efb NC |
20235 | cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), |
20236 | cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
21d799b5 NC |
20237 | cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), |
20238 | cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
20239 | }; |
20240 | #undef ARM_VARIANT | |
20241 | #undef THUMB_VARIANT | |
20242 | #undef TCE | |
c19d1205 ZW |
20243 | #undef TUE |
20244 | #undef TUF | |
20245 | #undef TCC | |
8f06b2d8 | 20246 | #undef cCE |
e3cb604e PB |
20247 | #undef cCL |
20248 | #undef C3E | |
c19d1205 ZW |
20249 | #undef CE |
20250 | #undef CM | |
20251 | #undef UE | |
20252 | #undef UF | |
20253 | #undef UT | |
5287ad62 JB |
20254 | #undef NUF |
20255 | #undef nUF | |
20256 | #undef NCE | |
20257 | #undef nCE | |
c19d1205 ZW |
20258 | #undef OPS0 |
20259 | #undef OPS1 | |
20260 | #undef OPS2 | |
20261 | #undef OPS3 | |
20262 | #undef OPS4 | |
20263 | #undef OPS5 | |
20264 | #undef OPS6 | |
20265 | #undef do_0 | |
20266 | \f | |
20267 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 20268 | |
c19d1205 ZW |
20269 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
20270 | for use in the a.out file, and stores them in the array pointed to by buf. | |
20271 | This knows about the endian-ness of the target machine and does | |
20272 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
20273 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
20274 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 20275 | |
c19d1205 ZW |
20276 | void |
20277 | md_number_to_chars (char * buf, valueT val, int n) | |
20278 | { | |
20279 | if (target_big_endian) | |
20280 | number_to_chars_bigendian (buf, val, n); | |
20281 | else | |
20282 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
20283 | } |
20284 | ||
c19d1205 ZW |
20285 | static valueT |
20286 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 20287 | { |
c19d1205 ZW |
20288 | valueT result = 0; |
20289 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 20290 | |
c19d1205 | 20291 | if (target_big_endian) |
b99bd4ef | 20292 | { |
c19d1205 ZW |
20293 | while (n--) |
20294 | { | |
20295 | result <<= 8; | |
20296 | result |= (*where++ & 255); | |
20297 | } | |
b99bd4ef | 20298 | } |
c19d1205 | 20299 | else |
b99bd4ef | 20300 | { |
c19d1205 ZW |
20301 | while (n--) |
20302 | { | |
20303 | result <<= 8; | |
20304 | result |= (where[n] & 255); | |
20305 | } | |
bfae80f2 | 20306 | } |
b99bd4ef | 20307 | |
c19d1205 | 20308 | return result; |
bfae80f2 | 20309 | } |
b99bd4ef | 20310 | |
c19d1205 | 20311 | /* MD interface: Sections. */ |
b99bd4ef | 20312 | |
fa94de6b RM |
20313 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
20314 | that an rs_machine_dependent frag may reach. */ | |
20315 | ||
20316 | unsigned int | |
20317 | arm_frag_max_var (fragS *fragp) | |
20318 | { | |
20319 | /* We only use rs_machine_dependent for variable-size Thumb instructions, | |
20320 | which are either THUMB_SIZE (2) or INSN_SIZE (4). | |
20321 | ||
20322 | Note that we generate relaxable instructions even for cases that don't | |
20323 | really need it, like an immediate that's a trivial constant. So we're | |
20324 | overestimating the instruction size for some of those cases. Rather | |
20325 | than putting more intelligence here, it would probably be better to | |
20326 | avoid generating a relaxation frag in the first place when it can be | |
20327 | determined up front that a short instruction will suffice. */ | |
20328 | ||
20329 | gas_assert (fragp->fr_type == rs_machine_dependent); | |
20330 | return INSN_SIZE; | |
20331 | } | |
20332 | ||
0110f2b8 PB |
20333 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
20334 | 2 bytes. */ | |
20335 | ||
c19d1205 | 20336 | int |
0110f2b8 | 20337 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
20338 | segT segtype ATTRIBUTE_UNUSED) |
20339 | { | |
0110f2b8 PB |
20340 | fragp->fr_var = 2; |
20341 | return 2; | |
20342 | } | |
20343 | ||
20344 | /* Convert a machine dependent frag. */ | |
20345 | ||
20346 | void | |
20347 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
20348 | { | |
20349 | unsigned long insn; | |
20350 | unsigned long old_op; | |
20351 | char *buf; | |
20352 | expressionS exp; | |
20353 | fixS *fixp; | |
20354 | int reloc_type; | |
20355 | int pc_rel; | |
20356 | int opcode; | |
20357 | ||
20358 | buf = fragp->fr_literal + fragp->fr_fix; | |
20359 | ||
20360 | old_op = bfd_get_16(abfd, buf); | |
5f4273c7 NC |
20361 | if (fragp->fr_symbol) |
20362 | { | |
0110f2b8 PB |
20363 | exp.X_op = O_symbol; |
20364 | exp.X_add_symbol = fragp->fr_symbol; | |
5f4273c7 NC |
20365 | } |
20366 | else | |
20367 | { | |
0110f2b8 | 20368 | exp.X_op = O_constant; |
5f4273c7 | 20369 | } |
0110f2b8 PB |
20370 | exp.X_add_number = fragp->fr_offset; |
20371 | opcode = fragp->fr_subtype; | |
20372 | switch (opcode) | |
20373 | { | |
20374 | case T_MNEM_ldr_pc: | |
20375 | case T_MNEM_ldr_pc2: | |
20376 | case T_MNEM_ldr_sp: | |
20377 | case T_MNEM_str_sp: | |
20378 | case T_MNEM_ldr: | |
20379 | case T_MNEM_ldrb: | |
20380 | case T_MNEM_ldrh: | |
20381 | case T_MNEM_str: | |
20382 | case T_MNEM_strb: | |
20383 | case T_MNEM_strh: | |
20384 | if (fragp->fr_var == 4) | |
20385 | { | |
5f4273c7 | 20386 | insn = THUMB_OP32 (opcode); |
0110f2b8 PB |
20387 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) |
20388 | { | |
20389 | insn |= (old_op & 0x700) << 4; | |
20390 | } | |
20391 | else | |
20392 | { | |
20393 | insn |= (old_op & 7) << 12; | |
20394 | insn |= (old_op & 0x38) << 13; | |
20395 | } | |
20396 | insn |= 0x00000c00; | |
20397 | put_thumb32_insn (buf, insn); | |
20398 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
20399 | } | |
20400 | else | |
20401 | { | |
20402 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
20403 | } | |
20404 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
20405 | break; | |
20406 | case T_MNEM_adr: | |
20407 | if (fragp->fr_var == 4) | |
20408 | { | |
20409 | insn = THUMB_OP32 (opcode); | |
20410 | insn |= (old_op & 0xf0) << 4; | |
20411 | put_thumb32_insn (buf, insn); | |
20412 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
20413 | } | |
20414 | else | |
20415 | { | |
20416 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
20417 | exp.X_add_number -= 4; | |
20418 | } | |
20419 | pc_rel = 1; | |
20420 | break; | |
20421 | case T_MNEM_mov: | |
20422 | case T_MNEM_movs: | |
20423 | case T_MNEM_cmp: | |
20424 | case T_MNEM_cmn: | |
20425 | if (fragp->fr_var == 4) | |
20426 | { | |
20427 | int r0off = (opcode == T_MNEM_mov | |
20428 | || opcode == T_MNEM_movs) ? 0 : 8; | |
20429 | insn = THUMB_OP32 (opcode); | |
20430 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
20431 | insn |= (old_op & 0x700) << r0off; | |
20432 | put_thumb32_insn (buf, insn); | |
20433 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
20434 | } | |
20435 | else | |
20436 | { | |
20437 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
20438 | } | |
20439 | pc_rel = 0; | |
20440 | break; | |
20441 | case T_MNEM_b: | |
20442 | if (fragp->fr_var == 4) | |
20443 | { | |
20444 | insn = THUMB_OP32(opcode); | |
20445 | put_thumb32_insn (buf, insn); | |
20446 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
20447 | } | |
20448 | else | |
20449 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
20450 | pc_rel = 1; | |
20451 | break; | |
20452 | case T_MNEM_bcond: | |
20453 | if (fragp->fr_var == 4) | |
20454 | { | |
20455 | insn = THUMB_OP32(opcode); | |
20456 | insn |= (old_op & 0xf00) << 14; | |
20457 | put_thumb32_insn (buf, insn); | |
20458 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
20459 | } | |
20460 | else | |
20461 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
20462 | pc_rel = 1; | |
20463 | break; | |
20464 | case T_MNEM_add_sp: | |
20465 | case T_MNEM_add_pc: | |
20466 | case T_MNEM_inc_sp: | |
20467 | case T_MNEM_dec_sp: | |
20468 | if (fragp->fr_var == 4) | |
20469 | { | |
20470 | /* ??? Choose between add and addw. */ | |
20471 | insn = THUMB_OP32 (opcode); | |
20472 | insn |= (old_op & 0xf0) << 4; | |
20473 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
20474 | if (opcode == T_MNEM_add_pc) |
20475 | reloc_type = BFD_RELOC_ARM_T32_IMM12; | |
20476 | else | |
20477 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
0110f2b8 PB |
20478 | } |
20479 | else | |
20480 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
20481 | pc_rel = 0; | |
20482 | break; | |
20483 | ||
20484 | case T_MNEM_addi: | |
20485 | case T_MNEM_addis: | |
20486 | case T_MNEM_subi: | |
20487 | case T_MNEM_subis: | |
20488 | if (fragp->fr_var == 4) | |
20489 | { | |
20490 | insn = THUMB_OP32 (opcode); | |
20491 | insn |= (old_op & 0xf0) << 4; | |
20492 | insn |= (old_op & 0xf) << 16; | |
20493 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
20494 | if (insn & (1 << 20)) |
20495 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
20496 | else | |
20497 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
0110f2b8 PB |
20498 | } |
20499 | else | |
20500 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
20501 | pc_rel = 0; | |
20502 | break; | |
20503 | default: | |
5f4273c7 | 20504 | abort (); |
0110f2b8 PB |
20505 | } |
20506 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
21d799b5 | 20507 | (enum bfd_reloc_code_real) reloc_type); |
0110f2b8 PB |
20508 | fixp->fx_file = fragp->fr_file; |
20509 | fixp->fx_line = fragp->fr_line; | |
20510 | fragp->fr_fix += fragp->fr_var; | |
20511 | } | |
20512 | ||
20513 | /* Return the size of a relaxable immediate operand instruction. | |
20514 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
20515 | static int | |
20516 | relax_immediate (fragS *fragp, int size, int shift) | |
20517 | { | |
20518 | offsetT offset; | |
20519 | offsetT mask; | |
20520 | offsetT low; | |
20521 | ||
20522 | /* ??? Should be able to do better than this. */ | |
20523 | if (fragp->fr_symbol) | |
20524 | return 4; | |
20525 | ||
20526 | low = (1 << shift) - 1; | |
20527 | mask = (1 << (shift + size)) - (1 << shift); | |
20528 | offset = fragp->fr_offset; | |
20529 | /* Force misaligned offsets to 32-bit variant. */ | |
20530 | if (offset & low) | |
5e77afaa | 20531 | return 4; |
0110f2b8 PB |
20532 | if (offset & ~mask) |
20533 | return 4; | |
20534 | return 2; | |
20535 | } | |
20536 | ||
5e77afaa PB |
20537 | /* Get the address of a symbol during relaxation. */ |
20538 | static addressT | |
5f4273c7 | 20539 | relaxed_symbol_addr (fragS *fragp, long stretch) |
5e77afaa PB |
20540 | { |
20541 | fragS *sym_frag; | |
20542 | addressT addr; | |
20543 | symbolS *sym; | |
20544 | ||
20545 | sym = fragp->fr_symbol; | |
20546 | sym_frag = symbol_get_frag (sym); | |
20547 | know (S_GET_SEGMENT (sym) != absolute_section | |
20548 | || sym_frag == &zero_address_frag); | |
20549 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
20550 | ||
20551 | /* If frag has yet to be reached on this pass, assume it will | |
20552 | move by STRETCH just as we did. If this is not so, it will | |
20553 | be because some frag between grows, and that will force | |
20554 | another pass. */ | |
20555 | ||
20556 | if (stretch != 0 | |
20557 | && sym_frag->relax_marker != fragp->relax_marker) | |
4396b686 PB |
20558 | { |
20559 | fragS *f; | |
20560 | ||
20561 | /* Adjust stretch for any alignment frag. Note that if have | |
20562 | been expanding the earlier code, the symbol may be | |
20563 | defined in what appears to be an earlier frag. FIXME: | |
20564 | This doesn't handle the fr_subtype field, which specifies | |
20565 | a maximum number of bytes to skip when doing an | |
20566 | alignment. */ | |
20567 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
20568 | { | |
20569 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
20570 | { | |
20571 | if (stretch < 0) | |
20572 | stretch = - ((- stretch) | |
20573 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
20574 | else | |
20575 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
20576 | if (stretch == 0) | |
20577 | break; | |
20578 | } | |
20579 | } | |
20580 | if (f != NULL) | |
20581 | addr += stretch; | |
20582 | } | |
5e77afaa PB |
20583 | |
20584 | return addr; | |
20585 | } | |
20586 | ||
0110f2b8 PB |
20587 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative |
20588 | load. */ | |
20589 | static int | |
5e77afaa | 20590 | relax_adr (fragS *fragp, asection *sec, long stretch) |
0110f2b8 PB |
20591 | { |
20592 | addressT addr; | |
20593 | offsetT val; | |
20594 | ||
20595 | /* Assume worst case for symbols not known to be in the same section. */ | |
974da60d NC |
20596 | if (fragp->fr_symbol == NULL |
20597 | || !S_IS_DEFINED (fragp->fr_symbol) | |
77db8e2e NC |
20598 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
20599 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
20600 | return 4; |
20601 | ||
5f4273c7 | 20602 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
20603 | addr = fragp->fr_address + fragp->fr_fix; |
20604 | addr = (addr + 4) & ~3; | |
5e77afaa | 20605 | /* Force misaligned targets to 32-bit variant. */ |
0110f2b8 | 20606 | if (val & 3) |
5e77afaa | 20607 | return 4; |
0110f2b8 PB |
20608 | val -= addr; |
20609 | if (val < 0 || val > 1020) | |
20610 | return 4; | |
20611 | return 2; | |
20612 | } | |
20613 | ||
20614 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
20615 | static int | |
20616 | relax_addsub (fragS *fragp, asection *sec) | |
20617 | { | |
20618 | char *buf; | |
20619 | int op; | |
20620 | ||
20621 | buf = fragp->fr_literal + fragp->fr_fix; | |
20622 | op = bfd_get_16(sec->owner, buf); | |
20623 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
20624 | return relax_immediate (fragp, 8, 0); | |
20625 | else | |
20626 | return relax_immediate (fragp, 3, 0); | |
20627 | } | |
20628 | ||
e83a675f RE |
20629 | /* Return TRUE iff the definition of symbol S could be pre-empted |
20630 | (overridden) at link or load time. */ | |
20631 | static bfd_boolean | |
20632 | symbol_preemptible (symbolS *s) | |
20633 | { | |
20634 | /* Weak symbols can always be pre-empted. */ | |
20635 | if (S_IS_WEAK (s)) | |
20636 | return TRUE; | |
20637 | ||
20638 | /* Non-global symbols cannot be pre-empted. */ | |
20639 | if (! S_IS_EXTERNAL (s)) | |
20640 | return FALSE; | |
20641 | ||
20642 | #ifdef OBJ_ELF | |
20643 | /* In ELF, a global symbol can be marked protected, or private. In that | |
20644 | case it can't be pre-empted (other definitions in the same link unit | |
20645 | would violate the ODR). */ | |
20646 | if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT) | |
20647 | return FALSE; | |
20648 | #endif | |
20649 | ||
20650 | /* Other global symbols might be pre-empted. */ | |
20651 | return TRUE; | |
20652 | } | |
0110f2b8 PB |
20653 | |
20654 | /* Return the size of a relaxable branch instruction. BITS is the | |
20655 | size of the offset field in the narrow instruction. */ | |
20656 | ||
20657 | static int | |
5e77afaa | 20658 | relax_branch (fragS *fragp, asection *sec, int bits, long stretch) |
0110f2b8 PB |
20659 | { |
20660 | addressT addr; | |
20661 | offsetT val; | |
20662 | offsetT limit; | |
20663 | ||
20664 | /* Assume worst case for symbols not known to be in the same section. */ | |
5f4273c7 | 20665 | if (!S_IS_DEFINED (fragp->fr_symbol) |
77db8e2e NC |
20666 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
20667 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
20668 | return 4; |
20669 | ||
267bf995 | 20670 | #ifdef OBJ_ELF |
e83a675f | 20671 | /* A branch to a function in ARM state will require interworking. */ |
267bf995 RR |
20672 | if (S_IS_DEFINED (fragp->fr_symbol) |
20673 | && ARM_IS_FUNC (fragp->fr_symbol)) | |
20674 | return 4; | |
e83a675f | 20675 | #endif |
0d9b4b55 | 20676 | |
e83a675f | 20677 | if (symbol_preemptible (fragp->fr_symbol)) |
0d9b4b55 | 20678 | return 4; |
267bf995 | 20679 | |
5f4273c7 | 20680 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
20681 | addr = fragp->fr_address + fragp->fr_fix + 4; |
20682 | val -= addr; | |
20683 | ||
20684 | /* Offset is a signed value *2 */ | |
20685 | limit = 1 << bits; | |
20686 | if (val >= limit || val < -limit) | |
20687 | return 4; | |
20688 | return 2; | |
20689 | } | |
20690 | ||
20691 | ||
20692 | /* Relax a machine dependent frag. This returns the amount by which | |
20693 | the current size of the frag should change. */ | |
20694 | ||
20695 | int | |
5e77afaa | 20696 | arm_relax_frag (asection *sec, fragS *fragp, long stretch) |
0110f2b8 PB |
20697 | { |
20698 | int oldsize; | |
20699 | int newsize; | |
20700 | ||
20701 | oldsize = fragp->fr_var; | |
20702 | switch (fragp->fr_subtype) | |
20703 | { | |
20704 | case T_MNEM_ldr_pc2: | |
5f4273c7 | 20705 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
20706 | break; |
20707 | case T_MNEM_ldr_pc: | |
20708 | case T_MNEM_ldr_sp: | |
20709 | case T_MNEM_str_sp: | |
5f4273c7 | 20710 | newsize = relax_immediate (fragp, 8, 2); |
0110f2b8 PB |
20711 | break; |
20712 | case T_MNEM_ldr: | |
20713 | case T_MNEM_str: | |
5f4273c7 | 20714 | newsize = relax_immediate (fragp, 5, 2); |
0110f2b8 PB |
20715 | break; |
20716 | case T_MNEM_ldrh: | |
20717 | case T_MNEM_strh: | |
5f4273c7 | 20718 | newsize = relax_immediate (fragp, 5, 1); |
0110f2b8 PB |
20719 | break; |
20720 | case T_MNEM_ldrb: | |
20721 | case T_MNEM_strb: | |
5f4273c7 | 20722 | newsize = relax_immediate (fragp, 5, 0); |
0110f2b8 PB |
20723 | break; |
20724 | case T_MNEM_adr: | |
5f4273c7 | 20725 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
20726 | break; |
20727 | case T_MNEM_mov: | |
20728 | case T_MNEM_movs: | |
20729 | case T_MNEM_cmp: | |
20730 | case T_MNEM_cmn: | |
5f4273c7 | 20731 | newsize = relax_immediate (fragp, 8, 0); |
0110f2b8 PB |
20732 | break; |
20733 | case T_MNEM_b: | |
5f4273c7 | 20734 | newsize = relax_branch (fragp, sec, 11, stretch); |
0110f2b8 PB |
20735 | break; |
20736 | case T_MNEM_bcond: | |
5f4273c7 | 20737 | newsize = relax_branch (fragp, sec, 8, stretch); |
0110f2b8 PB |
20738 | break; |
20739 | case T_MNEM_add_sp: | |
20740 | case T_MNEM_add_pc: | |
20741 | newsize = relax_immediate (fragp, 8, 2); | |
20742 | break; | |
20743 | case T_MNEM_inc_sp: | |
20744 | case T_MNEM_dec_sp: | |
20745 | newsize = relax_immediate (fragp, 7, 2); | |
20746 | break; | |
20747 | case T_MNEM_addi: | |
20748 | case T_MNEM_addis: | |
20749 | case T_MNEM_subi: | |
20750 | case T_MNEM_subis: | |
20751 | newsize = relax_addsub (fragp, sec); | |
20752 | break; | |
20753 | default: | |
5f4273c7 | 20754 | abort (); |
0110f2b8 | 20755 | } |
5e77afaa PB |
20756 | |
20757 | fragp->fr_var = newsize; | |
20758 | /* Freeze wide instructions that are at or before the same location as | |
20759 | in the previous pass. This avoids infinite loops. | |
5f4273c7 NC |
20760 | Don't freeze them unconditionally because targets may be artificially |
20761 | misaligned by the expansion of preceding frags. */ | |
5e77afaa | 20762 | if (stretch <= 0 && newsize > 2) |
0110f2b8 | 20763 | { |
0110f2b8 | 20764 | md_convert_frag (sec->owner, sec, fragp); |
5f4273c7 | 20765 | frag_wane (fragp); |
0110f2b8 | 20766 | } |
5e77afaa | 20767 | |
0110f2b8 | 20768 | return newsize - oldsize; |
c19d1205 | 20769 | } |
b99bd4ef | 20770 | |
c19d1205 | 20771 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 20772 | |
c19d1205 ZW |
20773 | valueT |
20774 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
20775 | valueT size) | |
20776 | { | |
f0927246 NC |
20777 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
20778 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
20779 | { | |
20780 | /* For a.out, force the section size to be aligned. If we don't do | |
20781 | this, BFD will align it for us, but it will not write out the | |
20782 | final bytes of the section. This may be a bug in BFD, but it is | |
20783 | easier to fix it here since that is how the other a.out targets | |
20784 | work. */ | |
20785 | int align; | |
20786 | ||
20787 | align = bfd_get_section_alignment (stdoutput, segment); | |
20788 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
20789 | } | |
c19d1205 | 20790 | #endif |
f0927246 NC |
20791 | |
20792 | return size; | |
bfae80f2 | 20793 | } |
b99bd4ef | 20794 | |
c19d1205 ZW |
20795 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
20796 | of an rs_align_code fragment. */ | |
20797 | ||
20798 | void | |
20799 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 20800 | { |
e7495e45 NS |
20801 | static char const arm_noop[2][2][4] = |
20802 | { | |
20803 | { /* ARMv1 */ | |
20804 | {0x00, 0x00, 0xa0, 0xe1}, /* LE */ | |
20805 | {0xe1, 0xa0, 0x00, 0x00}, /* BE */ | |
20806 | }, | |
20807 | { /* ARMv6k */ | |
20808 | {0x00, 0xf0, 0x20, 0xe3}, /* LE */ | |
20809 | {0xe3, 0x20, 0xf0, 0x00}, /* BE */ | |
20810 | }, | |
20811 | }; | |
20812 | static char const thumb_noop[2][2][2] = | |
20813 | { | |
20814 | { /* Thumb-1 */ | |
20815 | {0xc0, 0x46}, /* LE */ | |
20816 | {0x46, 0xc0}, /* BE */ | |
20817 | }, | |
20818 | { /* Thumb-2 */ | |
20819 | {0x00, 0xbf}, /* LE */ | |
20820 | {0xbf, 0x00} /* BE */ | |
20821 | } | |
20822 | }; | |
20823 | static char const wide_thumb_noop[2][4] = | |
20824 | { /* Wide Thumb-2 */ | |
20825 | {0xaf, 0xf3, 0x00, 0x80}, /* LE */ | |
20826 | {0xf3, 0xaf, 0x80, 0x00}, /* BE */ | |
20827 | }; | |
c921be7d | 20828 | |
e7495e45 | 20829 | unsigned bytes, fix, noop_size; |
c19d1205 ZW |
20830 | char * p; |
20831 | const char * noop; | |
e7495e45 | 20832 | const char *narrow_noop = NULL; |
cd000bff DJ |
20833 | #ifdef OBJ_ELF |
20834 | enum mstate state; | |
20835 | #endif | |
bfae80f2 | 20836 | |
c19d1205 | 20837 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
20838 | return; |
20839 | ||
c19d1205 ZW |
20840 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
20841 | p = fragP->fr_literal + fragP->fr_fix; | |
20842 | fix = 0; | |
bfae80f2 | 20843 | |
c19d1205 ZW |
20844 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
20845 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 20846 | |
cd000bff | 20847 | gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); |
8dc2430f | 20848 | |
cd000bff | 20849 | if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) |
a737bd4d | 20850 | { |
7f78eb34 JW |
20851 | if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0] |
20852 | ? selected_cpu : arm_arch_none, arm_ext_v6t2)) | |
e7495e45 NS |
20853 | { |
20854 | narrow_noop = thumb_noop[1][target_big_endian]; | |
20855 | noop = wide_thumb_noop[target_big_endian]; | |
20856 | } | |
c19d1205 | 20857 | else |
e7495e45 NS |
20858 | noop = thumb_noop[0][target_big_endian]; |
20859 | noop_size = 2; | |
cd000bff DJ |
20860 | #ifdef OBJ_ELF |
20861 | state = MAP_THUMB; | |
20862 | #endif | |
7ed4c4c5 NC |
20863 | } |
20864 | else | |
20865 | { | |
7f78eb34 JW |
20866 | noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0] |
20867 | ? selected_cpu : arm_arch_none, | |
20868 | arm_ext_v6k) != 0] | |
e7495e45 NS |
20869 | [target_big_endian]; |
20870 | noop_size = 4; | |
cd000bff DJ |
20871 | #ifdef OBJ_ELF |
20872 | state = MAP_ARM; | |
20873 | #endif | |
7ed4c4c5 | 20874 | } |
c921be7d | 20875 | |
e7495e45 | 20876 | fragP->fr_var = noop_size; |
c921be7d | 20877 | |
c19d1205 | 20878 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 20879 | { |
c19d1205 | 20880 | fix = bytes & (noop_size - 1); |
cd000bff DJ |
20881 | #ifdef OBJ_ELF |
20882 | insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); | |
20883 | #endif | |
c19d1205 ZW |
20884 | memset (p, 0, fix); |
20885 | p += fix; | |
20886 | bytes -= fix; | |
a737bd4d | 20887 | } |
a737bd4d | 20888 | |
e7495e45 NS |
20889 | if (narrow_noop) |
20890 | { | |
20891 | if (bytes & noop_size) | |
20892 | { | |
20893 | /* Insert a narrow noop. */ | |
20894 | memcpy (p, narrow_noop, noop_size); | |
20895 | p += noop_size; | |
20896 | bytes -= noop_size; | |
20897 | fix += noop_size; | |
20898 | } | |
20899 | ||
20900 | /* Use wide noops for the remainder */ | |
20901 | noop_size = 4; | |
20902 | } | |
20903 | ||
c19d1205 | 20904 | while (bytes >= noop_size) |
a737bd4d | 20905 | { |
c19d1205 ZW |
20906 | memcpy (p, noop, noop_size); |
20907 | p += noop_size; | |
20908 | bytes -= noop_size; | |
20909 | fix += noop_size; | |
a737bd4d NC |
20910 | } |
20911 | ||
c19d1205 | 20912 | fragP->fr_fix += fix; |
a737bd4d NC |
20913 | } |
20914 | ||
c19d1205 ZW |
20915 | /* Called from md_do_align. Used to create an alignment |
20916 | frag in a code section. */ | |
20917 | ||
20918 | void | |
20919 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 20920 | { |
c19d1205 | 20921 | char * p; |
7ed4c4c5 | 20922 | |
c19d1205 | 20923 | /* We assume that there will never be a requirement |
6ec8e702 | 20924 | to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ |
c19d1205 | 20925 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) |
6ec8e702 NC |
20926 | { |
20927 | char err_msg[128]; | |
20928 | ||
fa94de6b | 20929 | sprintf (err_msg, |
477330fc RM |
20930 | _("alignments greater than %d bytes not supported in .text sections."), |
20931 | MAX_MEM_FOR_RS_ALIGN_CODE + 1); | |
20203fb9 | 20932 | as_fatal ("%s", err_msg); |
6ec8e702 | 20933 | } |
bfae80f2 | 20934 | |
c19d1205 ZW |
20935 | p = frag_var (rs_align_code, |
20936 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
20937 | 1, | |
20938 | (relax_substateT) max, | |
20939 | (symbolS *) NULL, | |
20940 | (offsetT) n, | |
20941 | (char *) NULL); | |
20942 | *p = 0; | |
20943 | } | |
bfae80f2 | 20944 | |
8dc2430f NC |
20945 | /* Perform target specific initialisation of a frag. |
20946 | Note - despite the name this initialisation is not done when the frag | |
20947 | is created, but only when its type is assigned. A frag can be created | |
20948 | and used a long time before its type is set, so beware of assuming that | |
20949 | this initialisationis performed first. */ | |
bfae80f2 | 20950 | |
cd000bff DJ |
20951 | #ifndef OBJ_ELF |
20952 | void | |
20953 | arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) | |
20954 | { | |
20955 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
2e98972e | 20956 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
cd000bff DJ |
20957 | } |
20958 | ||
20959 | #else /* OBJ_ELF is defined. */ | |
c19d1205 | 20960 | void |
cd000bff | 20961 | arm_init_frag (fragS * fragP, int max_chars) |
c19d1205 | 20962 | { |
8dc2430f NC |
20963 | /* If the current ARM vs THUMB mode has not already |
20964 | been recorded into this frag then do so now. */ | |
cd000bff DJ |
20965 | if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) |
20966 | { | |
20967 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; | |
20968 | ||
20969 | /* Record a mapping symbol for alignment frags. We will delete this | |
20970 | later if the alignment ends up empty. */ | |
20971 | switch (fragP->fr_type) | |
20972 | { | |
20973 | case rs_align: | |
20974 | case rs_align_test: | |
20975 | case rs_fill: | |
20976 | mapping_state_2 (MAP_DATA, max_chars); | |
20977 | break; | |
20978 | case rs_align_code: | |
20979 | mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); | |
20980 | break; | |
20981 | default: | |
20982 | break; | |
20983 | } | |
20984 | } | |
bfae80f2 RE |
20985 | } |
20986 | ||
c19d1205 ZW |
20987 | /* When we change sections we need to issue a new mapping symbol. */ |
20988 | ||
20989 | void | |
20990 | arm_elf_change_section (void) | |
bfae80f2 | 20991 | { |
c19d1205 ZW |
20992 | /* Link an unlinked unwind index table section to the .text section. */ |
20993 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
20994 | && elf_linked_to_section (now_seg) == NULL) | |
20995 | elf_linked_to_section (now_seg) = text_section; | |
bfae80f2 RE |
20996 | } |
20997 | ||
c19d1205 ZW |
20998 | int |
20999 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 21000 | { |
c19d1205 ZW |
21001 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
21002 | return SHT_ARM_EXIDX; | |
e45d0630 | 21003 | |
c19d1205 ZW |
21004 | return -1; |
21005 | } | |
21006 | \f | |
21007 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 21008 | |
c19d1205 | 21009 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 21010 | |
5f4273c7 | 21011 | /* Generate any deferred unwind frame offset. */ |
e45d0630 | 21012 | |
bfae80f2 | 21013 | static void |
c19d1205 | 21014 | flush_pending_unwind (void) |
bfae80f2 | 21015 | { |
c19d1205 | 21016 | offsetT offset; |
bfae80f2 | 21017 | |
c19d1205 ZW |
21018 | offset = unwind.pending_offset; |
21019 | unwind.pending_offset = 0; | |
21020 | if (offset != 0) | |
21021 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
21022 | } |
21023 | ||
c19d1205 ZW |
21024 | /* Add an opcode to this list for this function. Two-byte opcodes should |
21025 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
21026 | order. */ | |
21027 | ||
bfae80f2 | 21028 | static void |
c19d1205 | 21029 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 21030 | { |
c19d1205 ZW |
21031 | /* Add any deferred stack adjustment. */ |
21032 | if (unwind.pending_offset) | |
21033 | flush_pending_unwind (); | |
bfae80f2 | 21034 | |
c19d1205 | 21035 | unwind.sp_restored = 0; |
bfae80f2 | 21036 | |
c19d1205 | 21037 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 21038 | { |
c19d1205 ZW |
21039 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
21040 | if (unwind.opcodes) | |
21d799b5 | 21041 | unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes, |
477330fc | 21042 | unwind.opcode_alloc); |
c19d1205 | 21043 | else |
21d799b5 | 21044 | unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc); |
bfae80f2 | 21045 | } |
c19d1205 | 21046 | while (length > 0) |
bfae80f2 | 21047 | { |
c19d1205 ZW |
21048 | length--; |
21049 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
21050 | op >>= 8; | |
21051 | unwind.opcode_count++; | |
bfae80f2 | 21052 | } |
bfae80f2 RE |
21053 | } |
21054 | ||
c19d1205 ZW |
21055 | /* Add unwind opcodes to adjust the stack pointer. */ |
21056 | ||
bfae80f2 | 21057 | static void |
c19d1205 | 21058 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 21059 | { |
c19d1205 | 21060 | valueT op; |
bfae80f2 | 21061 | |
c19d1205 | 21062 | if (offset > 0x200) |
bfae80f2 | 21063 | { |
c19d1205 ZW |
21064 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
21065 | char bytes[5]; | |
21066 | int n; | |
21067 | valueT o; | |
bfae80f2 | 21068 | |
c19d1205 ZW |
21069 | /* Long form: 0xb2, uleb128. */ |
21070 | /* This might not fit in a word so add the individual bytes, | |
21071 | remembering the list is built in reverse order. */ | |
21072 | o = (valueT) ((offset - 0x204) >> 2); | |
21073 | if (o == 0) | |
21074 | add_unwind_opcode (0, 1); | |
bfae80f2 | 21075 | |
c19d1205 ZW |
21076 | /* Calculate the uleb128 encoding of the offset. */ |
21077 | n = 0; | |
21078 | while (o) | |
21079 | { | |
21080 | bytes[n] = o & 0x7f; | |
21081 | o >>= 7; | |
21082 | if (o) | |
21083 | bytes[n] |= 0x80; | |
21084 | n++; | |
21085 | } | |
21086 | /* Add the insn. */ | |
21087 | for (; n; n--) | |
21088 | add_unwind_opcode (bytes[n - 1], 1); | |
21089 | add_unwind_opcode (0xb2, 1); | |
21090 | } | |
21091 | else if (offset > 0x100) | |
bfae80f2 | 21092 | { |
c19d1205 ZW |
21093 | /* Two short opcodes. */ |
21094 | add_unwind_opcode (0x3f, 1); | |
21095 | op = (offset - 0x104) >> 2; | |
21096 | add_unwind_opcode (op, 1); | |
bfae80f2 | 21097 | } |
c19d1205 ZW |
21098 | else if (offset > 0) |
21099 | { | |
21100 | /* Short opcode. */ | |
21101 | op = (offset - 4) >> 2; | |
21102 | add_unwind_opcode (op, 1); | |
21103 | } | |
21104 | else if (offset < 0) | |
bfae80f2 | 21105 | { |
c19d1205 ZW |
21106 | offset = -offset; |
21107 | while (offset > 0x100) | |
bfae80f2 | 21108 | { |
c19d1205 ZW |
21109 | add_unwind_opcode (0x7f, 1); |
21110 | offset -= 0x100; | |
bfae80f2 | 21111 | } |
c19d1205 ZW |
21112 | op = ((offset - 4) >> 2) | 0x40; |
21113 | add_unwind_opcode (op, 1); | |
bfae80f2 | 21114 | } |
bfae80f2 RE |
21115 | } |
21116 | ||
c19d1205 ZW |
21117 | /* Finish the list of unwind opcodes for this function. */ |
21118 | static void | |
21119 | finish_unwind_opcodes (void) | |
bfae80f2 | 21120 | { |
c19d1205 | 21121 | valueT op; |
bfae80f2 | 21122 | |
c19d1205 | 21123 | if (unwind.fp_used) |
bfae80f2 | 21124 | { |
708587a4 | 21125 | /* Adjust sp as necessary. */ |
c19d1205 ZW |
21126 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
21127 | flush_pending_unwind (); | |
bfae80f2 | 21128 | |
c19d1205 ZW |
21129 | /* After restoring sp from the frame pointer. */ |
21130 | op = 0x90 | unwind.fp_reg; | |
21131 | add_unwind_opcode (op, 1); | |
21132 | } | |
21133 | else | |
21134 | flush_pending_unwind (); | |
bfae80f2 RE |
21135 | } |
21136 | ||
bfae80f2 | 21137 | |
c19d1205 ZW |
21138 | /* Start an exception table entry. If idx is nonzero this is an index table |
21139 | entry. */ | |
bfae80f2 RE |
21140 | |
21141 | static void | |
c19d1205 | 21142 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 21143 | { |
c19d1205 ZW |
21144 | const char * text_name; |
21145 | const char * prefix; | |
21146 | const char * prefix_once; | |
21147 | const char * group_name; | |
21148 | size_t prefix_len; | |
21149 | size_t text_len; | |
21150 | char * sec_name; | |
21151 | size_t sec_name_len; | |
21152 | int type; | |
21153 | int flags; | |
21154 | int linkonce; | |
bfae80f2 | 21155 | |
c19d1205 | 21156 | if (idx) |
bfae80f2 | 21157 | { |
c19d1205 ZW |
21158 | prefix = ELF_STRING_ARM_unwind; |
21159 | prefix_once = ELF_STRING_ARM_unwind_once; | |
21160 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 21161 | } |
c19d1205 | 21162 | else |
bfae80f2 | 21163 | { |
c19d1205 ZW |
21164 | prefix = ELF_STRING_ARM_unwind_info; |
21165 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
21166 | type = SHT_PROGBITS; | |
bfae80f2 RE |
21167 | } |
21168 | ||
c19d1205 ZW |
21169 | text_name = segment_name (text_seg); |
21170 | if (streq (text_name, ".text")) | |
21171 | text_name = ""; | |
21172 | ||
21173 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
21174 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 21175 | { |
c19d1205 ZW |
21176 | prefix = prefix_once; |
21177 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
21178 | } |
21179 | ||
c19d1205 ZW |
21180 | prefix_len = strlen (prefix); |
21181 | text_len = strlen (text_name); | |
21182 | sec_name_len = prefix_len + text_len; | |
21d799b5 | 21183 | sec_name = (char *) xmalloc (sec_name_len + 1); |
c19d1205 ZW |
21184 | memcpy (sec_name, prefix, prefix_len); |
21185 | memcpy (sec_name + prefix_len, text_name, text_len); | |
21186 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 21187 | |
c19d1205 ZW |
21188 | flags = SHF_ALLOC; |
21189 | linkonce = 0; | |
21190 | group_name = 0; | |
bfae80f2 | 21191 | |
c19d1205 ZW |
21192 | /* Handle COMDAT group. */ |
21193 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 21194 | { |
c19d1205 ZW |
21195 | group_name = elf_group_name (text_seg); |
21196 | if (group_name == NULL) | |
21197 | { | |
bd3ba5d1 | 21198 | as_bad (_("Group section `%s' has no group signature"), |
c19d1205 ZW |
21199 | segment_name (text_seg)); |
21200 | ignore_rest_of_line (); | |
21201 | return; | |
21202 | } | |
21203 | flags |= SHF_GROUP; | |
21204 | linkonce = 1; | |
bfae80f2 RE |
21205 | } |
21206 | ||
c19d1205 | 21207 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 21208 | |
5f4273c7 | 21209 | /* Set the section link for index tables. */ |
c19d1205 ZW |
21210 | if (idx) |
21211 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
21212 | } |
21213 | ||
bfae80f2 | 21214 | |
c19d1205 ZW |
21215 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
21216 | personality routine data. Returns zero, or the index table value for | |
cad0da33 | 21217 | an inline entry. */ |
c19d1205 ZW |
21218 | |
21219 | static valueT | |
21220 | create_unwind_entry (int have_data) | |
bfae80f2 | 21221 | { |
c19d1205 ZW |
21222 | int size; |
21223 | addressT where; | |
21224 | char *ptr; | |
21225 | /* The current word of data. */ | |
21226 | valueT data; | |
21227 | /* The number of bytes left in this word. */ | |
21228 | int n; | |
bfae80f2 | 21229 | |
c19d1205 | 21230 | finish_unwind_opcodes (); |
bfae80f2 | 21231 | |
c19d1205 ZW |
21232 | /* Remember the current text section. */ |
21233 | unwind.saved_seg = now_seg; | |
21234 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 21235 | |
c19d1205 | 21236 | start_unwind_section (now_seg, 0); |
bfae80f2 | 21237 | |
c19d1205 | 21238 | if (unwind.personality_routine == NULL) |
bfae80f2 | 21239 | { |
c19d1205 ZW |
21240 | if (unwind.personality_index == -2) |
21241 | { | |
21242 | if (have_data) | |
5f4273c7 | 21243 | as_bad (_("handlerdata in cantunwind frame")); |
c19d1205 ZW |
21244 | return 1; /* EXIDX_CANTUNWIND. */ |
21245 | } | |
bfae80f2 | 21246 | |
c19d1205 ZW |
21247 | /* Use a default personality routine if none is specified. */ |
21248 | if (unwind.personality_index == -1) | |
21249 | { | |
21250 | if (unwind.opcode_count > 3) | |
21251 | unwind.personality_index = 1; | |
21252 | else | |
21253 | unwind.personality_index = 0; | |
21254 | } | |
bfae80f2 | 21255 | |
c19d1205 ZW |
21256 | /* Space for the personality routine entry. */ |
21257 | if (unwind.personality_index == 0) | |
21258 | { | |
21259 | if (unwind.opcode_count > 3) | |
21260 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 21261 | |
c19d1205 ZW |
21262 | if (!have_data) |
21263 | { | |
21264 | /* All the data is inline in the index table. */ | |
21265 | data = 0x80; | |
21266 | n = 3; | |
21267 | while (unwind.opcode_count > 0) | |
21268 | { | |
21269 | unwind.opcode_count--; | |
21270 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
21271 | n--; | |
21272 | } | |
bfae80f2 | 21273 | |
c19d1205 ZW |
21274 | /* Pad with "finish" opcodes. */ |
21275 | while (n--) | |
21276 | data = (data << 8) | 0xb0; | |
bfae80f2 | 21277 | |
c19d1205 ZW |
21278 | return data; |
21279 | } | |
21280 | size = 0; | |
21281 | } | |
21282 | else | |
21283 | /* We get two opcodes "free" in the first word. */ | |
21284 | size = unwind.opcode_count - 2; | |
21285 | } | |
21286 | else | |
5011093d | 21287 | { |
cad0da33 NC |
21288 | /* PR 16765: Missing or misplaced unwind directives can trigger this. */ |
21289 | if (unwind.personality_index != -1) | |
21290 | { | |
21291 | as_bad (_("attempt to recreate an unwind entry")); | |
21292 | return 1; | |
21293 | } | |
5011093d NC |
21294 | |
21295 | /* An extra byte is required for the opcode count. */ | |
21296 | size = unwind.opcode_count + 1; | |
21297 | } | |
bfae80f2 | 21298 | |
c19d1205 ZW |
21299 | size = (size + 3) >> 2; |
21300 | if (size > 0xff) | |
21301 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 21302 | |
c19d1205 ZW |
21303 | frag_align (2, 0, 0); |
21304 | record_alignment (now_seg, 2); | |
21305 | unwind.table_entry = expr_build_dot (); | |
21306 | ||
21307 | /* Allocate the table entry. */ | |
21308 | ptr = frag_more ((size << 2) + 4); | |
74929e7b NC |
21309 | /* PR 13449: Zero the table entries in case some of them are not used. */ |
21310 | memset (ptr, 0, (size << 2) + 4); | |
c19d1205 | 21311 | where = frag_now_fix () - ((size << 2) + 4); |
bfae80f2 | 21312 | |
c19d1205 | 21313 | switch (unwind.personality_index) |
bfae80f2 | 21314 | { |
c19d1205 ZW |
21315 | case -1: |
21316 | /* ??? Should this be a PLT generating relocation? */ | |
21317 | /* Custom personality routine. */ | |
21318 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
21319 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 21320 | |
c19d1205 ZW |
21321 | where += 4; |
21322 | ptr += 4; | |
bfae80f2 | 21323 | |
c19d1205 | 21324 | /* Set the first byte to the number of additional words. */ |
5011093d | 21325 | data = size > 0 ? size - 1 : 0; |
c19d1205 ZW |
21326 | n = 3; |
21327 | break; | |
bfae80f2 | 21328 | |
c19d1205 ZW |
21329 | /* ABI defined personality routines. */ |
21330 | case 0: | |
21331 | /* Three opcodes bytes are packed into the first word. */ | |
21332 | data = 0x80; | |
21333 | n = 3; | |
21334 | break; | |
bfae80f2 | 21335 | |
c19d1205 ZW |
21336 | case 1: |
21337 | case 2: | |
21338 | /* The size and first two opcode bytes go in the first word. */ | |
21339 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
21340 | n = 2; | |
21341 | break; | |
bfae80f2 | 21342 | |
c19d1205 ZW |
21343 | default: |
21344 | /* Should never happen. */ | |
21345 | abort (); | |
21346 | } | |
bfae80f2 | 21347 | |
c19d1205 ZW |
21348 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
21349 | time. */ | |
21350 | while (unwind.opcode_count > 0) | |
21351 | { | |
21352 | if (n == 0) | |
21353 | { | |
21354 | md_number_to_chars (ptr, data, 4); | |
21355 | ptr += 4; | |
21356 | n = 4; | |
21357 | data = 0; | |
21358 | } | |
21359 | unwind.opcode_count--; | |
21360 | n--; | |
21361 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
21362 | } | |
21363 | ||
21364 | /* Finish off the last word. */ | |
21365 | if (n < 4) | |
21366 | { | |
21367 | /* Pad with "finish" opcodes. */ | |
21368 | while (n--) | |
21369 | data = (data << 8) | 0xb0; | |
21370 | ||
21371 | md_number_to_chars (ptr, data, 4); | |
21372 | } | |
21373 | ||
21374 | if (!have_data) | |
21375 | { | |
21376 | /* Add an empty descriptor if there is no user-specified data. */ | |
21377 | ptr = frag_more (4); | |
21378 | md_number_to_chars (ptr, 0, 4); | |
21379 | } | |
21380 | ||
21381 | return 0; | |
bfae80f2 RE |
21382 | } |
21383 | ||
f0927246 NC |
21384 | |
21385 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
21386 | ||
21387 | void | |
21388 | tc_arm_frame_initial_instructions (void) | |
21389 | { | |
21390 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
21391 | } | |
21392 | #endif /* OBJ_ELF */ | |
21393 | ||
c19d1205 ZW |
21394 | /* Convert REGNAME to a DWARF-2 register number. */ |
21395 | ||
21396 | int | |
1df69f4f | 21397 | tc_arm_regname_to_dw2regnum (char *regname) |
bfae80f2 | 21398 | { |
1df69f4f | 21399 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
1f5afe1c NC |
21400 | if (reg != FAIL) |
21401 | return reg; | |
c19d1205 | 21402 | |
1f5afe1c NC |
21403 | /* PR 16694: Allow VFP registers as well. */ |
21404 | reg = arm_reg_parse (®name, REG_TYPE_VFS); | |
21405 | if (reg != FAIL) | |
21406 | return 64 + reg; | |
c19d1205 | 21407 | |
1f5afe1c NC |
21408 | reg = arm_reg_parse (®name, REG_TYPE_VFD); |
21409 | if (reg != FAIL) | |
21410 | return reg + 256; | |
21411 | ||
21412 | return -1; | |
bfae80f2 RE |
21413 | } |
21414 | ||
f0927246 | 21415 | #ifdef TE_PE |
c19d1205 | 21416 | void |
f0927246 | 21417 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
bfae80f2 | 21418 | { |
91d6fa6a | 21419 | expressionS exp; |
bfae80f2 | 21420 | |
91d6fa6a NC |
21421 | exp.X_op = O_secrel; |
21422 | exp.X_add_symbol = symbol; | |
21423 | exp.X_add_number = 0; | |
21424 | emit_expr (&exp, size); | |
f0927246 NC |
21425 | } |
21426 | #endif | |
bfae80f2 | 21427 | |
c19d1205 | 21428 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 21429 | |
2fc8bdac ZW |
21430 | /* Return the address within the segment that a PC-relative fixup is |
21431 | relative to. For ARM, PC-relative fixups applied to instructions | |
21432 | are generally relative to the location of the fixup plus 8 bytes. | |
21433 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
21434 | require special handling. */ | |
bfae80f2 | 21435 | |
c19d1205 | 21436 | long |
2fc8bdac | 21437 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 21438 | { |
2fc8bdac ZW |
21439 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
21440 | ||
21441 | /* If this is pc-relative and we are going to emit a relocation | |
21442 | then we just want to put out any pipeline compensation that the linker | |
53baae48 NC |
21443 | will need. Otherwise we want to use the calculated base. |
21444 | For WinCE we skip the bias for externals as well, since this | |
21445 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ | |
5f4273c7 | 21446 | if (fixP->fx_pcrel |
2fc8bdac | 21447 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) |
53baae48 NC |
21448 | || (arm_force_relocation (fixP) |
21449 | #ifdef TE_WINCE | |
21450 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
21451 | #endif | |
21452 | ))) | |
2fc8bdac | 21453 | base = 0; |
bfae80f2 | 21454 | |
267bf995 | 21455 | |
c19d1205 | 21456 | switch (fixP->fx_r_type) |
bfae80f2 | 21457 | { |
2fc8bdac ZW |
21458 | /* PC relative addressing on the Thumb is slightly odd as the |
21459 | bottom two bits of the PC are forced to zero for the | |
21460 | calculation. This happens *after* application of the | |
21461 | pipeline offset. However, Thumb adrl already adjusts for | |
21462 | this, so we need not do it again. */ | |
c19d1205 | 21463 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 21464 | return base & ~3; |
c19d1205 ZW |
21465 | |
21466 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
21467 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 21468 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 21469 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 21470 | return (base + 4) & ~3; |
c19d1205 | 21471 | |
2fc8bdac ZW |
21472 | /* Thumb branches are simply offset by +4. */ |
21473 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
21474 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
21475 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
21476 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
2fc8bdac | 21477 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac | 21478 | return base + 4; |
bfae80f2 | 21479 | |
267bf995 | 21480 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
486499d0 CL |
21481 | if (fixP->fx_addsy |
21482 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21483 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 | 21484 | && ARM_IS_FUNC (fixP->fx_addsy) |
477330fc RM |
21485 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) |
21486 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
267bf995 RR |
21487 | return base + 4; |
21488 | ||
00adf2d4 JB |
21489 | /* BLX is like branches above, but forces the low two bits of PC to |
21490 | zero. */ | |
486499d0 CL |
21491 | case BFD_RELOC_THUMB_PCREL_BLX: |
21492 | if (fixP->fx_addsy | |
21493 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21494 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
21495 | && THUMB_IS_FUNC (fixP->fx_addsy) |
21496 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21497 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
00adf2d4 JB |
21498 | return (base + 4) & ~3; |
21499 | ||
2fc8bdac ZW |
21500 | /* ARM mode branches are offset by +8. However, the Windows CE |
21501 | loader expects the relocation not to take this into account. */ | |
267bf995 | 21502 | case BFD_RELOC_ARM_PCREL_BLX: |
486499d0 CL |
21503 | if (fixP->fx_addsy |
21504 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21505 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
21506 | && ARM_IS_FUNC (fixP->fx_addsy) |
21507 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21508 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 21509 | return base + 8; |
267bf995 | 21510 | |
486499d0 CL |
21511 | case BFD_RELOC_ARM_PCREL_CALL: |
21512 | if (fixP->fx_addsy | |
21513 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21514 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
21515 | && THUMB_IS_FUNC (fixP->fx_addsy) |
21516 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21517 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 21518 | return base + 8; |
267bf995 | 21519 | |
2fc8bdac | 21520 | case BFD_RELOC_ARM_PCREL_BRANCH: |
39b41c9c | 21521 | case BFD_RELOC_ARM_PCREL_JUMP: |
2fc8bdac | 21522 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 21523 | #ifdef TE_WINCE |
5f4273c7 | 21524 | /* When handling fixups immediately, because we have already |
477330fc | 21525 | discovered the value of a symbol, or the address of the frag involved |
53baae48 | 21526 | we must account for the offset by +8, as the OS loader will never see the reloc. |
477330fc RM |
21527 | see fixup_segment() in write.c |
21528 | The S_IS_EXTERNAL test handles the case of global symbols. | |
21529 | Those need the calculated base, not just the pipe compensation the linker will need. */ | |
53baae48 NC |
21530 | if (fixP->fx_pcrel |
21531 | && fixP->fx_addsy != NULL | |
21532 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
21533 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) | |
21534 | return base + 8; | |
2fc8bdac | 21535 | return base; |
c19d1205 | 21536 | #else |
2fc8bdac | 21537 | return base + 8; |
c19d1205 | 21538 | #endif |
2fc8bdac | 21539 | |
267bf995 | 21540 | |
2fc8bdac ZW |
21541 | /* ARM mode loads relative to PC are also offset by +8. Unlike |
21542 | branches, the Windows CE loader *does* expect the relocation | |
21543 | to take this into account. */ | |
21544 | case BFD_RELOC_ARM_OFFSET_IMM: | |
21545 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
21546 | case BFD_RELOC_ARM_HWLITERAL: | |
21547 | case BFD_RELOC_ARM_LITERAL: | |
21548 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
21549 | return base + 8; | |
21550 | ||
21551 | ||
21552 | /* Other PC-relative relocations are un-offset. */ | |
21553 | default: | |
21554 | return base; | |
21555 | } | |
bfae80f2 RE |
21556 | } |
21557 | ||
c19d1205 ZW |
21558 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. |
21559 | Otherwise we have no need to default values of symbols. */ | |
21560 | ||
21561 | symbolS * | |
21562 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
bfae80f2 | 21563 | { |
c19d1205 ZW |
21564 | #ifdef OBJ_ELF |
21565 | if (name[0] == '_' && name[1] == 'G' | |
21566 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
21567 | { | |
21568 | if (!GOT_symbol) | |
21569 | { | |
21570 | if (symbol_find (name)) | |
bd3ba5d1 | 21571 | as_bad (_("GOT already in the symbol table")); |
bfae80f2 | 21572 | |
c19d1205 ZW |
21573 | GOT_symbol = symbol_new (name, undefined_section, |
21574 | (valueT) 0, & zero_address_frag); | |
21575 | } | |
bfae80f2 | 21576 | |
c19d1205 | 21577 | return GOT_symbol; |
bfae80f2 | 21578 | } |
c19d1205 | 21579 | #endif |
bfae80f2 | 21580 | |
c921be7d | 21581 | return NULL; |
bfae80f2 RE |
21582 | } |
21583 | ||
55cf6793 | 21584 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
21585 | computed as two separate immediate values, added together. We |
21586 | already know that this value cannot be computed by just one ARM | |
21587 | instruction. */ | |
21588 | ||
21589 | static unsigned int | |
21590 | validate_immediate_twopart (unsigned int val, | |
21591 | unsigned int * highpart) | |
bfae80f2 | 21592 | { |
c19d1205 ZW |
21593 | unsigned int a; |
21594 | unsigned int i; | |
bfae80f2 | 21595 | |
c19d1205 ZW |
21596 | for (i = 0; i < 32; i += 2) |
21597 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
21598 | { | |
21599 | if (a & 0xff00) | |
21600 | { | |
21601 | if (a & ~ 0xffff) | |
21602 | continue; | |
21603 | * highpart = (a >> 8) | ((i + 24) << 7); | |
21604 | } | |
21605 | else if (a & 0xff0000) | |
21606 | { | |
21607 | if (a & 0xff000000) | |
21608 | continue; | |
21609 | * highpart = (a >> 16) | ((i + 16) << 7); | |
21610 | } | |
21611 | else | |
21612 | { | |
9c2799c2 | 21613 | gas_assert (a & 0xff000000); |
c19d1205 ZW |
21614 | * highpart = (a >> 24) | ((i + 8) << 7); |
21615 | } | |
bfae80f2 | 21616 | |
c19d1205 ZW |
21617 | return (a & 0xff) | (i << 7); |
21618 | } | |
bfae80f2 | 21619 | |
c19d1205 | 21620 | return FAIL; |
bfae80f2 RE |
21621 | } |
21622 | ||
c19d1205 ZW |
21623 | static int |
21624 | validate_offset_imm (unsigned int val, int hwse) | |
21625 | { | |
21626 | if ((hwse && val > 255) || val > 4095) | |
21627 | return FAIL; | |
21628 | return val; | |
21629 | } | |
bfae80f2 | 21630 | |
55cf6793 | 21631 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
21632 | negative immediate constant by altering the instruction. A bit of |
21633 | a hack really. | |
21634 | MOV <-> MVN | |
21635 | AND <-> BIC | |
21636 | ADC <-> SBC | |
21637 | by inverting the second operand, and | |
21638 | ADD <-> SUB | |
21639 | CMP <-> CMN | |
21640 | by negating the second operand. */ | |
bfae80f2 | 21641 | |
c19d1205 ZW |
21642 | static int |
21643 | negate_data_op (unsigned long * instruction, | |
21644 | unsigned long value) | |
bfae80f2 | 21645 | { |
c19d1205 ZW |
21646 | int op, new_inst; |
21647 | unsigned long negated, inverted; | |
bfae80f2 | 21648 | |
c19d1205 ZW |
21649 | negated = encode_arm_immediate (-value); |
21650 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 21651 | |
c19d1205 ZW |
21652 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
21653 | switch (op) | |
bfae80f2 | 21654 | { |
c19d1205 ZW |
21655 | /* First negates. */ |
21656 | case OPCODE_SUB: /* ADD <-> SUB */ | |
21657 | new_inst = OPCODE_ADD; | |
21658 | value = negated; | |
21659 | break; | |
bfae80f2 | 21660 | |
c19d1205 ZW |
21661 | case OPCODE_ADD: |
21662 | new_inst = OPCODE_SUB; | |
21663 | value = negated; | |
21664 | break; | |
bfae80f2 | 21665 | |
c19d1205 ZW |
21666 | case OPCODE_CMP: /* CMP <-> CMN */ |
21667 | new_inst = OPCODE_CMN; | |
21668 | value = negated; | |
21669 | break; | |
bfae80f2 | 21670 | |
c19d1205 ZW |
21671 | case OPCODE_CMN: |
21672 | new_inst = OPCODE_CMP; | |
21673 | value = negated; | |
21674 | break; | |
bfae80f2 | 21675 | |
c19d1205 ZW |
21676 | /* Now Inverted ops. */ |
21677 | case OPCODE_MOV: /* MOV <-> MVN */ | |
21678 | new_inst = OPCODE_MVN; | |
21679 | value = inverted; | |
21680 | break; | |
bfae80f2 | 21681 | |
c19d1205 ZW |
21682 | case OPCODE_MVN: |
21683 | new_inst = OPCODE_MOV; | |
21684 | value = inverted; | |
21685 | break; | |
bfae80f2 | 21686 | |
c19d1205 ZW |
21687 | case OPCODE_AND: /* AND <-> BIC */ |
21688 | new_inst = OPCODE_BIC; | |
21689 | value = inverted; | |
21690 | break; | |
bfae80f2 | 21691 | |
c19d1205 ZW |
21692 | case OPCODE_BIC: |
21693 | new_inst = OPCODE_AND; | |
21694 | value = inverted; | |
21695 | break; | |
bfae80f2 | 21696 | |
c19d1205 ZW |
21697 | case OPCODE_ADC: /* ADC <-> SBC */ |
21698 | new_inst = OPCODE_SBC; | |
21699 | value = inverted; | |
21700 | break; | |
bfae80f2 | 21701 | |
c19d1205 ZW |
21702 | case OPCODE_SBC: |
21703 | new_inst = OPCODE_ADC; | |
21704 | value = inverted; | |
21705 | break; | |
bfae80f2 | 21706 | |
c19d1205 ZW |
21707 | /* We cannot do anything. */ |
21708 | default: | |
21709 | return FAIL; | |
b99bd4ef NC |
21710 | } |
21711 | ||
c19d1205 ZW |
21712 | if (value == (unsigned) FAIL) |
21713 | return FAIL; | |
21714 | ||
21715 | *instruction &= OPCODE_MASK; | |
21716 | *instruction |= new_inst << DATA_OP_SHIFT; | |
21717 | return value; | |
b99bd4ef NC |
21718 | } |
21719 | ||
ef8d22e6 PB |
21720 | /* Like negate_data_op, but for Thumb-2. */ |
21721 | ||
21722 | static unsigned int | |
16dd5e42 | 21723 | thumb32_negate_data_op (offsetT *instruction, unsigned int value) |
ef8d22e6 PB |
21724 | { |
21725 | int op, new_inst; | |
21726 | int rd; | |
16dd5e42 | 21727 | unsigned int negated, inverted; |
ef8d22e6 PB |
21728 | |
21729 | negated = encode_thumb32_immediate (-value); | |
21730 | inverted = encode_thumb32_immediate (~value); | |
21731 | ||
21732 | rd = (*instruction >> 8) & 0xf; | |
21733 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
21734 | switch (op) | |
21735 | { | |
21736 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
21737 | case T2_OPCODE_SUB: | |
21738 | new_inst = T2_OPCODE_ADD; | |
21739 | value = negated; | |
21740 | break; | |
21741 | ||
21742 | case T2_OPCODE_ADD: | |
21743 | new_inst = T2_OPCODE_SUB; | |
21744 | value = negated; | |
21745 | break; | |
21746 | ||
21747 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
21748 | case T2_OPCODE_ORR: | |
21749 | new_inst = T2_OPCODE_ORN; | |
21750 | value = inverted; | |
21751 | break; | |
21752 | ||
21753 | case T2_OPCODE_ORN: | |
21754 | new_inst = T2_OPCODE_ORR; | |
21755 | value = inverted; | |
21756 | break; | |
21757 | ||
21758 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
21759 | case T2_OPCODE_AND: | |
21760 | new_inst = T2_OPCODE_BIC; | |
21761 | if (rd == 15) | |
21762 | value = FAIL; | |
21763 | else | |
21764 | value = inverted; | |
21765 | break; | |
21766 | ||
21767 | case T2_OPCODE_BIC: | |
21768 | new_inst = T2_OPCODE_AND; | |
21769 | value = inverted; | |
21770 | break; | |
21771 | ||
21772 | /* ADC <-> SBC */ | |
21773 | case T2_OPCODE_ADC: | |
21774 | new_inst = T2_OPCODE_SBC; | |
21775 | value = inverted; | |
21776 | break; | |
21777 | ||
21778 | case T2_OPCODE_SBC: | |
21779 | new_inst = T2_OPCODE_ADC; | |
21780 | value = inverted; | |
21781 | break; | |
21782 | ||
21783 | /* We cannot do anything. */ | |
21784 | default: | |
21785 | return FAIL; | |
21786 | } | |
21787 | ||
16dd5e42 | 21788 | if (value == (unsigned int)FAIL) |
ef8d22e6 PB |
21789 | return FAIL; |
21790 | ||
21791 | *instruction &= T2_OPCODE_MASK; | |
21792 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
21793 | return value; | |
21794 | } | |
21795 | ||
8f06b2d8 PB |
21796 | /* Read a 32-bit thumb instruction from buf. */ |
21797 | static unsigned long | |
21798 | get_thumb32_insn (char * buf) | |
21799 | { | |
21800 | unsigned long insn; | |
21801 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
21802 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
21803 | ||
21804 | return insn; | |
21805 | } | |
21806 | ||
a8bc6c78 PB |
21807 | |
21808 | /* We usually want to set the low bit on the address of thumb function | |
21809 | symbols. In particular .word foo - . should have the low bit set. | |
21810 | Generic code tries to fold the difference of two symbols to | |
21811 | a constant. Prevent this and force a relocation when the first symbols | |
21812 | is a thumb function. */ | |
c921be7d NC |
21813 | |
21814 | bfd_boolean | |
a8bc6c78 PB |
21815 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) |
21816 | { | |
21817 | if (op == O_subtract | |
21818 | && l->X_op == O_symbol | |
21819 | && r->X_op == O_symbol | |
21820 | && THUMB_IS_FUNC (l->X_add_symbol)) | |
21821 | { | |
21822 | l->X_op = O_subtract; | |
21823 | l->X_op_symbol = r->X_add_symbol; | |
21824 | l->X_add_number -= r->X_add_number; | |
c921be7d | 21825 | return TRUE; |
a8bc6c78 | 21826 | } |
c921be7d | 21827 | |
a8bc6c78 | 21828 | /* Process as normal. */ |
c921be7d | 21829 | return FALSE; |
a8bc6c78 PB |
21830 | } |
21831 | ||
4a42ebbc RR |
21832 | /* Encode Thumb2 unconditional branches and calls. The encoding |
21833 | for the 2 are identical for the immediate values. */ | |
21834 | ||
21835 | static void | |
21836 | encode_thumb2_b_bl_offset (char * buf, offsetT value) | |
21837 | { | |
21838 | #define T2I1I2MASK ((1 << 13) | (1 << 11)) | |
21839 | offsetT newval; | |
21840 | offsetT newval2; | |
21841 | addressT S, I1, I2, lo, hi; | |
21842 | ||
21843 | S = (value >> 24) & 0x01; | |
21844 | I1 = (value >> 23) & 0x01; | |
21845 | I2 = (value >> 22) & 0x01; | |
21846 | hi = (value >> 12) & 0x3ff; | |
fa94de6b | 21847 | lo = (value >> 1) & 0x7ff; |
4a42ebbc RR |
21848 | newval = md_chars_to_number (buf, THUMB_SIZE); |
21849 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
21850 | newval |= (S << 10) | hi; | |
21851 | newval2 &= ~T2I1I2MASK; | |
21852 | newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK; | |
21853 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21854 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
21855 | } | |
21856 | ||
c19d1205 | 21857 | void |
55cf6793 | 21858 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
21859 | valueT * valP, |
21860 | segT seg) | |
21861 | { | |
21862 | offsetT value = * valP; | |
21863 | offsetT newval; | |
21864 | unsigned int newimm; | |
21865 | unsigned long temp; | |
21866 | int sign; | |
21867 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 21868 | |
9c2799c2 | 21869 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 21870 | |
c19d1205 | 21871 | /* Note whether this will delete the relocation. */ |
4962c51a | 21872 | |
c19d1205 ZW |
21873 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
21874 | fixP->fx_done = 1; | |
b99bd4ef | 21875 | |
adbaf948 | 21876 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
5f4273c7 | 21877 | consistency with the behaviour on 32-bit hosts. Remember value |
adbaf948 ZW |
21878 | for emit_reloc. */ |
21879 | value &= 0xffffffff; | |
21880 | value ^= 0x80000000; | |
5f4273c7 | 21881 | value -= 0x80000000; |
adbaf948 ZW |
21882 | |
21883 | *valP = value; | |
c19d1205 | 21884 | fixP->fx_addnumber = value; |
b99bd4ef | 21885 | |
adbaf948 ZW |
21886 | /* Same treatment for fixP->fx_offset. */ |
21887 | fixP->fx_offset &= 0xffffffff; | |
21888 | fixP->fx_offset ^= 0x80000000; | |
21889 | fixP->fx_offset -= 0x80000000; | |
21890 | ||
c19d1205 | 21891 | switch (fixP->fx_r_type) |
b99bd4ef | 21892 | { |
c19d1205 ZW |
21893 | case BFD_RELOC_NONE: |
21894 | /* This will need to go in the object file. */ | |
21895 | fixP->fx_done = 0; | |
21896 | break; | |
b99bd4ef | 21897 | |
c19d1205 ZW |
21898 | case BFD_RELOC_ARM_IMMEDIATE: |
21899 | /* We claim that this fixup has been processed here, | |
21900 | even if in fact we generate an error because we do | |
21901 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
21902 | fixP->fx_done = 1; | |
b99bd4ef | 21903 | |
77db8e2e | 21904 | if (fixP->fx_addsy) |
b99bd4ef | 21905 | { |
77db8e2e | 21906 | const char *msg = 0; |
b99bd4ef | 21907 | |
77db8e2e NC |
21908 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
21909 | msg = _("undefined symbol %s used as an immediate value"); | |
21910 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
21911 | msg = _("symbol %s is in a different section"); | |
21912 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
21913 | msg = _("symbol %s is weak and may be overridden later"); | |
21914 | ||
21915 | if (msg) | |
21916 | { | |
21917 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21918 | msg, S_GET_NAME (fixP->fx_addsy)); | |
21919 | break; | |
21920 | } | |
42e5fcbf AS |
21921 | } |
21922 | ||
c19d1205 ZW |
21923 | temp = md_chars_to_number (buf, INSN_SIZE); |
21924 | ||
5e73442d SL |
21925 | /* If the offset is negative, we should use encoding A2 for ADR. */ |
21926 | if ((temp & 0xfff0000) == 0x28f0000 && value < 0) | |
21927 | newimm = negate_data_op (&temp, value); | |
21928 | else | |
21929 | { | |
21930 | newimm = encode_arm_immediate (value); | |
21931 | ||
21932 | /* If the instruction will fail, see if we can fix things up by | |
21933 | changing the opcode. */ | |
21934 | if (newimm == (unsigned int) FAIL) | |
21935 | newimm = negate_data_op (&temp, value); | |
21936 | } | |
21937 | ||
21938 | if (newimm == (unsigned int) FAIL) | |
b99bd4ef | 21939 | { |
c19d1205 ZW |
21940 | as_bad_where (fixP->fx_file, fixP->fx_line, |
21941 | _("invalid constant (%lx) after fixup"), | |
21942 | (unsigned long) value); | |
21943 | break; | |
b99bd4ef | 21944 | } |
b99bd4ef | 21945 | |
c19d1205 ZW |
21946 | newimm |= (temp & 0xfffff000); |
21947 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
21948 | break; | |
b99bd4ef | 21949 | |
c19d1205 ZW |
21950 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
21951 | { | |
21952 | unsigned int highpart = 0; | |
21953 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 21954 | |
77db8e2e | 21955 | if (fixP->fx_addsy) |
42e5fcbf | 21956 | { |
77db8e2e | 21957 | const char *msg = 0; |
42e5fcbf | 21958 | |
77db8e2e NC |
21959 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
21960 | msg = _("undefined symbol %s used as an immediate value"); | |
21961 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
21962 | msg = _("symbol %s is in a different section"); | |
21963 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
21964 | msg = _("symbol %s is weak and may be overridden later"); | |
42e5fcbf | 21965 | |
77db8e2e NC |
21966 | if (msg) |
21967 | { | |
21968 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21969 | msg, S_GET_NAME (fixP->fx_addsy)); | |
21970 | break; | |
21971 | } | |
21972 | } | |
fa94de6b | 21973 | |
c19d1205 ZW |
21974 | newimm = encode_arm_immediate (value); |
21975 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 21976 | |
c19d1205 ZW |
21977 | /* If the instruction will fail, see if we can fix things up by |
21978 | changing the opcode. */ | |
21979 | if (newimm == (unsigned int) FAIL | |
21980 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
21981 | { | |
21982 | /* No ? OK - try using two ADD instructions to generate | |
21983 | the value. */ | |
21984 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 21985 | |
c19d1205 ZW |
21986 | /* Yes - then make sure that the second instruction is |
21987 | also an add. */ | |
21988 | if (newimm != (unsigned int) FAIL) | |
21989 | newinsn = temp; | |
21990 | /* Still No ? Try using a negated value. */ | |
21991 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
21992 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
21993 | /* Otherwise - give up. */ | |
21994 | else | |
21995 | { | |
21996 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21997 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
21998 | (long) value); | |
21999 | break; | |
22000 | } | |
b99bd4ef | 22001 | |
c19d1205 ZW |
22002 | /* Replace the first operand in the 2nd instruction (which |
22003 | is the PC) with the destination register. We have | |
22004 | already added in the PC in the first instruction and we | |
22005 | do not want to do it again. */ | |
22006 | newinsn &= ~ 0xf0000; | |
22007 | newinsn |= ((newinsn & 0x0f000) << 4); | |
22008 | } | |
b99bd4ef | 22009 | |
c19d1205 ZW |
22010 | newimm |= (temp & 0xfffff000); |
22011 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 22012 | |
c19d1205 ZW |
22013 | highpart |= (newinsn & 0xfffff000); |
22014 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
22015 | } | |
22016 | break; | |
b99bd4ef | 22017 | |
c19d1205 | 22018 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
22019 | if (!fixP->fx_done && seg->use_rela_p) |
22020 | value = 0; | |
22021 | ||
c19d1205 | 22022 | case BFD_RELOC_ARM_LITERAL: |
26d97720 | 22023 | sign = value > 0; |
b99bd4ef | 22024 | |
c19d1205 ZW |
22025 | if (value < 0) |
22026 | value = - value; | |
b99bd4ef | 22027 | |
c19d1205 | 22028 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 22029 | { |
c19d1205 ZW |
22030 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
22031 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22032 | _("invalid literal constant: pool needs to be closer")); | |
22033 | else | |
22034 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22035 | _("bad immediate value for offset (%ld)"), | |
22036 | (long) value); | |
22037 | break; | |
f03698e6 RE |
22038 | } |
22039 | ||
c19d1205 | 22040 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
22041 | if (value == 0) |
22042 | newval &= 0xfffff000; | |
22043 | else | |
22044 | { | |
22045 | newval &= 0xff7ff000; | |
22046 | newval |= value | (sign ? INDEX_UP : 0); | |
22047 | } | |
c19d1205 ZW |
22048 | md_number_to_chars (buf, newval, INSN_SIZE); |
22049 | break; | |
b99bd4ef | 22050 | |
c19d1205 ZW |
22051 | case BFD_RELOC_ARM_OFFSET_IMM8: |
22052 | case BFD_RELOC_ARM_HWLITERAL: | |
26d97720 | 22053 | sign = value > 0; |
b99bd4ef | 22054 | |
c19d1205 ZW |
22055 | if (value < 0) |
22056 | value = - value; | |
b99bd4ef | 22057 | |
c19d1205 | 22058 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 22059 | { |
c19d1205 ZW |
22060 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
22061 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22062 | _("invalid literal constant: pool needs to be closer")); | |
22063 | else | |
427d0db6 RM |
22064 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22065 | _("bad immediate value for 8-bit offset (%ld)"), | |
22066 | (long) value); | |
c19d1205 | 22067 | break; |
b99bd4ef NC |
22068 | } |
22069 | ||
c19d1205 | 22070 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
22071 | if (value == 0) |
22072 | newval &= 0xfffff0f0; | |
22073 | else | |
22074 | { | |
22075 | newval &= 0xff7ff0f0; | |
22076 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
22077 | } | |
c19d1205 ZW |
22078 | md_number_to_chars (buf, newval, INSN_SIZE); |
22079 | break; | |
b99bd4ef | 22080 | |
c19d1205 ZW |
22081 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
22082 | if (value < 0 || value > 1020 || value % 4 != 0) | |
22083 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22084 | _("bad immediate value for offset (%ld)"), (long) value); | |
22085 | value /= 4; | |
b99bd4ef | 22086 | |
c19d1205 | 22087 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
22088 | newval |= value; |
22089 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
22090 | break; | |
b99bd4ef | 22091 | |
c19d1205 ZW |
22092 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
22093 | /* This is a complicated relocation used for all varieties of Thumb32 | |
22094 | load/store instruction with immediate offset: | |
22095 | ||
22096 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
477330fc | 22097 | *4, optional writeback(W) |
c19d1205 ZW |
22098 | (doubleword load/store) |
22099 | ||
22100 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
22101 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
22102 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
22103 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
22104 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
22105 | ||
22106 | Uppercase letters indicate bits that are already encoded at | |
22107 | this point. Lowercase letters are our problem. For the | |
22108 | second block of instructions, the secondary opcode nybble | |
22109 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
22110 | a PC-relative operation. */ | |
22111 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22112 | newval <<= 16; | |
22113 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 22114 | |
c19d1205 | 22115 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 22116 | { |
c19d1205 ZW |
22117 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
22118 | if (value >= 0) | |
22119 | newval |= (1 << 23); | |
22120 | else | |
22121 | value = -value; | |
22122 | if (value % 4 != 0) | |
22123 | { | |
22124 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22125 | _("offset not a multiple of 4")); | |
22126 | break; | |
22127 | } | |
22128 | value /= 4; | |
216d22bc | 22129 | if (value > 0xff) |
c19d1205 ZW |
22130 | { |
22131 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22132 | _("offset out of range")); | |
22133 | break; | |
22134 | } | |
22135 | newval &= ~0xff; | |
b99bd4ef | 22136 | } |
c19d1205 | 22137 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 22138 | { |
c19d1205 ZW |
22139 | /* PC-relative, 12-bit offset. */ |
22140 | if (value >= 0) | |
22141 | newval |= (1 << 23); | |
22142 | else | |
22143 | value = -value; | |
216d22bc | 22144 | if (value > 0xfff) |
c19d1205 ZW |
22145 | { |
22146 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22147 | _("offset out of range")); | |
22148 | break; | |
22149 | } | |
22150 | newval &= ~0xfff; | |
b99bd4ef | 22151 | } |
c19d1205 | 22152 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 22153 | { |
c19d1205 ZW |
22154 | /* Writeback: 8-bit, +/- offset. */ |
22155 | if (value >= 0) | |
22156 | newval |= (1 << 9); | |
22157 | else | |
22158 | value = -value; | |
216d22bc | 22159 | if (value > 0xff) |
c19d1205 ZW |
22160 | { |
22161 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22162 | _("offset out of range")); | |
22163 | break; | |
22164 | } | |
22165 | newval &= ~0xff; | |
b99bd4ef | 22166 | } |
c19d1205 | 22167 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 22168 | { |
c19d1205 | 22169 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 22170 | if (value < 0 || value > 0xff) |
b99bd4ef | 22171 | { |
c19d1205 ZW |
22172 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22173 | _("offset out of range")); | |
22174 | break; | |
b99bd4ef | 22175 | } |
c19d1205 ZW |
22176 | newval &= ~0xff; |
22177 | newval |= value; | |
b99bd4ef NC |
22178 | } |
22179 | else | |
b99bd4ef | 22180 | { |
c19d1205 ZW |
22181 | /* Positive 12-bit or negative 8-bit offset. */ |
22182 | int limit; | |
22183 | if (value >= 0) | |
b99bd4ef | 22184 | { |
c19d1205 ZW |
22185 | newval |= (1 << 23); |
22186 | limit = 0xfff; | |
22187 | } | |
22188 | else | |
22189 | { | |
22190 | value = -value; | |
22191 | limit = 0xff; | |
22192 | } | |
22193 | if (value > limit) | |
22194 | { | |
22195 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22196 | _("offset out of range")); | |
22197 | break; | |
b99bd4ef | 22198 | } |
c19d1205 | 22199 | newval &= ~limit; |
b99bd4ef | 22200 | } |
b99bd4ef | 22201 | |
c19d1205 ZW |
22202 | newval |= value; |
22203 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
22204 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
22205 | break; | |
404ff6b5 | 22206 | |
c19d1205 ZW |
22207 | case BFD_RELOC_ARM_SHIFT_IMM: |
22208 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22209 | if (((unsigned long) value) > 32 | |
22210 | || (value == 32 | |
22211 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
22212 | { | |
22213 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22214 | _("shift expression is too large")); | |
22215 | break; | |
22216 | } | |
404ff6b5 | 22217 | |
c19d1205 ZW |
22218 | if (value == 0) |
22219 | /* Shifts of zero must be done as lsl. */ | |
22220 | newval &= ~0x60; | |
22221 | else if (value == 32) | |
22222 | value = 0; | |
22223 | newval &= 0xfffff07f; | |
22224 | newval |= (value & 0x1f) << 7; | |
22225 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22226 | break; | |
404ff6b5 | 22227 | |
c19d1205 | 22228 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
16805f35 | 22229 | case BFD_RELOC_ARM_T32_ADD_IMM: |
92e90b6e | 22230 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 22231 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
22232 | /* We claim that this fixup has been processed here, |
22233 | even if in fact we generate an error because we do | |
22234 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
22235 | fixP->fx_done = 1; | |
404ff6b5 | 22236 | |
c19d1205 ZW |
22237 | if (fixP->fx_addsy |
22238 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
22239 | { | |
22240 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22241 | _("undefined symbol %s used as an immediate value"), | |
22242 | S_GET_NAME (fixP->fx_addsy)); | |
22243 | break; | |
22244 | } | |
404ff6b5 | 22245 | |
c19d1205 ZW |
22246 | newval = md_chars_to_number (buf, THUMB_SIZE); |
22247 | newval <<= 16; | |
22248 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 22249 | |
16805f35 PB |
22250 | newimm = FAIL; |
22251 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE | |
22252 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
ef8d22e6 PB |
22253 | { |
22254 | newimm = encode_thumb32_immediate (value); | |
22255 | if (newimm == (unsigned int) FAIL) | |
22256 | newimm = thumb32_negate_data_op (&newval, value); | |
22257 | } | |
16805f35 PB |
22258 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE |
22259 | && newimm == (unsigned int) FAIL) | |
92e90b6e | 22260 | { |
16805f35 PB |
22261 | /* Turn add/sum into addw/subw. */ |
22262 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
22263 | newval = (newval & 0xfeffffff) | 0x02000000; | |
40f246e3 NC |
22264 | /* No flat 12-bit imm encoding for addsw/subsw. */ |
22265 | if ((newval & 0x00100000) == 0) | |
e9f89963 | 22266 | { |
40f246e3 NC |
22267 | /* 12 bit immediate for addw/subw. */ |
22268 | if (value < 0) | |
22269 | { | |
22270 | value = -value; | |
22271 | newval ^= 0x00a00000; | |
22272 | } | |
22273 | if (value > 0xfff) | |
22274 | newimm = (unsigned int) FAIL; | |
22275 | else | |
22276 | newimm = value; | |
e9f89963 | 22277 | } |
92e90b6e | 22278 | } |
cc8a6dd0 | 22279 | |
c19d1205 | 22280 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 22281 | { |
c19d1205 ZW |
22282 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22283 | _("invalid constant (%lx) after fixup"), | |
22284 | (unsigned long) value); | |
22285 | break; | |
3631a3c8 NC |
22286 | } |
22287 | ||
c19d1205 ZW |
22288 | newval |= (newimm & 0x800) << 15; |
22289 | newval |= (newimm & 0x700) << 4; | |
22290 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 22291 | |
c19d1205 ZW |
22292 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
22293 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
22294 | break; | |
a737bd4d | 22295 | |
3eb17e6b | 22296 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
22297 | if (((unsigned long) value) > 0xffff) |
22298 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 22299 | _("invalid smc expression")); |
2fc8bdac | 22300 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
22301 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
22302 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22303 | break; | |
a737bd4d | 22304 | |
90ec0d68 MGD |
22305 | case BFD_RELOC_ARM_HVC: |
22306 | if (((unsigned long) value) > 0xffff) | |
22307 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22308 | _("invalid hvc expression")); | |
22309 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22310 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); | |
22311 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22312 | break; | |
22313 | ||
c19d1205 | 22314 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 22315 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
22316 | { |
22317 | if (((unsigned long) value) > 0xff) | |
22318 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22319 | _("invalid swi expression")); | |
2fc8bdac | 22320 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
22321 | newval |= value; |
22322 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22323 | } | |
22324 | else | |
22325 | { | |
22326 | if (((unsigned long) value) > 0x00ffffff) | |
22327 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22328 | _("invalid swi expression")); | |
2fc8bdac | 22329 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
22330 | newval |= value; |
22331 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22332 | } | |
22333 | break; | |
a737bd4d | 22334 | |
c19d1205 ZW |
22335 | case BFD_RELOC_ARM_MULTI: |
22336 | if (((unsigned long) value) > 0xffff) | |
22337 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22338 | _("invalid expression in load/store multiple")); | |
22339 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
22340 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22341 | break; | |
a737bd4d | 22342 | |
c19d1205 | 22343 | #ifdef OBJ_ELF |
39b41c9c | 22344 | case BFD_RELOC_ARM_PCREL_CALL: |
267bf995 RR |
22345 | |
22346 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
22347 | && fixP->fx_addsy | |
34e77a92 | 22348 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22349 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
22350 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
22351 | /* Flip the bl to blx. This is a simple flip | |
22352 | bit here because we generate PCREL_CALL for | |
22353 | unconditional bls. */ | |
22354 | { | |
22355 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22356 | newval = newval | 0x10000000; | |
22357 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22358 | temp = 1; | |
22359 | fixP->fx_done = 1; | |
22360 | } | |
39b41c9c PB |
22361 | else |
22362 | temp = 3; | |
22363 | goto arm_branch_common; | |
22364 | ||
22365 | case BFD_RELOC_ARM_PCREL_JUMP: | |
267bf995 RR |
22366 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
22367 | && fixP->fx_addsy | |
34e77a92 | 22368 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22369 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
22370 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
22371 | { | |
22372 | /* This would map to a bl<cond>, b<cond>, | |
22373 | b<always> to a Thumb function. We | |
22374 | need to force a relocation for this particular | |
22375 | case. */ | |
22376 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22377 | fixP->fx_done = 0; | |
22378 | } | |
22379 | ||
2fc8bdac | 22380 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 22381 | #endif |
39b41c9c PB |
22382 | case BFD_RELOC_ARM_PCREL_BRANCH: |
22383 | temp = 3; | |
22384 | goto arm_branch_common; | |
a737bd4d | 22385 | |
39b41c9c | 22386 | case BFD_RELOC_ARM_PCREL_BLX: |
267bf995 | 22387 | |
39b41c9c | 22388 | temp = 1; |
267bf995 RR |
22389 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
22390 | && fixP->fx_addsy | |
34e77a92 | 22391 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22392 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
22393 | && ARM_IS_FUNC (fixP->fx_addsy)) | |
22394 | { | |
22395 | /* Flip the blx to a bl and warn. */ | |
22396 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
22397 | newval = 0xeb000000; | |
22398 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
22399 | _("blx to '%s' an ARM ISA state function changed to bl"), | |
22400 | name); | |
22401 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22402 | temp = 3; | |
22403 | fixP->fx_done = 1; | |
22404 | } | |
22405 | ||
22406 | #ifdef OBJ_ELF | |
22407 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
477330fc | 22408 | fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; |
267bf995 RR |
22409 | #endif |
22410 | ||
39b41c9c | 22411 | arm_branch_common: |
c19d1205 | 22412 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
22413 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
22414 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
22415 | also be be clear. */ | |
22416 | if (value & temp) | |
c19d1205 | 22417 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
22418 | _("misaligned branch destination")); |
22419 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
22420 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
08f10d51 | 22421 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 22422 | |
2fc8bdac | 22423 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 22424 | { |
2fc8bdac ZW |
22425 | newval = md_chars_to_number (buf, INSN_SIZE); |
22426 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
22427 | /* Set the H bit on BLX instructions. */ |
22428 | if (temp == 1) | |
22429 | { | |
22430 | if (value & 2) | |
22431 | newval |= 0x01000000; | |
22432 | else | |
22433 | newval &= ~0x01000000; | |
22434 | } | |
2fc8bdac | 22435 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 22436 | } |
c19d1205 | 22437 | break; |
a737bd4d | 22438 | |
25fe350b MS |
22439 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ |
22440 | /* CBZ can only branch forward. */ | |
a737bd4d | 22441 | |
738755b0 | 22442 | /* Attempts to use CBZ to branch to the next instruction |
477330fc RM |
22443 | (which, strictly speaking, are prohibited) will be turned into |
22444 | no-ops. | |
738755b0 MS |
22445 | |
22446 | FIXME: It may be better to remove the instruction completely and | |
22447 | perform relaxation. */ | |
22448 | if (value == -2) | |
2fc8bdac ZW |
22449 | { |
22450 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
738755b0 | 22451 | newval = 0xbf00; /* NOP encoding T1 */ |
2fc8bdac ZW |
22452 | md_number_to_chars (buf, newval, THUMB_SIZE); |
22453 | } | |
738755b0 MS |
22454 | else |
22455 | { | |
22456 | if (value & ~0x7e) | |
08f10d51 | 22457 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
738755b0 | 22458 | |
477330fc | 22459 | if (fixP->fx_done || !seg->use_rela_p) |
738755b0 MS |
22460 | { |
22461 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22462 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); | |
22463 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22464 | } | |
22465 | } | |
c19d1205 | 22466 | break; |
a737bd4d | 22467 | |
c19d1205 | 22468 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac | 22469 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
08f10d51 | 22470 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 22471 | |
2fc8bdac ZW |
22472 | if (fixP->fx_done || !seg->use_rela_p) |
22473 | { | |
22474 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22475 | newval |= (value & 0x1ff) >> 1; | |
22476 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22477 | } | |
c19d1205 | 22478 | break; |
a737bd4d | 22479 | |
c19d1205 | 22480 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac | 22481 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
08f10d51 | 22482 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 22483 | |
2fc8bdac ZW |
22484 | if (fixP->fx_done || !seg->use_rela_p) |
22485 | { | |
22486 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22487 | newval |= (value & 0xfff) >> 1; | |
22488 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22489 | } | |
c19d1205 | 22490 | break; |
a737bd4d | 22491 | |
c19d1205 | 22492 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
267bf995 RR |
22493 | if (fixP->fx_addsy |
22494 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 22495 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22496 | && ARM_IS_FUNC (fixP->fx_addsy) |
22497 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
22498 | { | |
22499 | /* Force a relocation for a branch 20 bits wide. */ | |
22500 | fixP->fx_done = 0; | |
22501 | } | |
08f10d51 | 22502 | if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff)) |
2fc8bdac ZW |
22503 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22504 | _("conditional branch out of range")); | |
404ff6b5 | 22505 | |
2fc8bdac ZW |
22506 | if (fixP->fx_done || !seg->use_rela_p) |
22507 | { | |
22508 | offsetT newval2; | |
22509 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 22510 | |
2fc8bdac ZW |
22511 | S = (value & 0x00100000) >> 20; |
22512 | J2 = (value & 0x00080000) >> 19; | |
22513 | J1 = (value & 0x00040000) >> 18; | |
22514 | hi = (value & 0x0003f000) >> 12; | |
22515 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 22516 | |
2fc8bdac ZW |
22517 | newval = md_chars_to_number (buf, THUMB_SIZE); |
22518 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
22519 | newval |= (S << 10) | hi; | |
22520 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
22521 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22522 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
22523 | } | |
c19d1205 | 22524 | break; |
6c43fab6 | 22525 | |
c19d1205 | 22526 | case BFD_RELOC_THUMB_PCREL_BLX: |
267bf995 RR |
22527 | /* If there is a blx from a thumb state function to |
22528 | another thumb function flip this to a bl and warn | |
22529 | about it. */ | |
22530 | ||
22531 | if (fixP->fx_addsy | |
34e77a92 | 22532 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22533 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
22534 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
22535 | { | |
22536 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
22537 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
22538 | _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), | |
22539 | name); | |
22540 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
22541 | newval = newval | 0x1000; | |
22542 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
22543 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
22544 | fixP->fx_done = 1; | |
22545 | } | |
22546 | ||
22547 | ||
22548 | goto thumb_bl_common; | |
22549 | ||
c19d1205 | 22550 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
267bf995 RR |
22551 | /* A bl from Thumb state ISA to an internal ARM state function |
22552 | is converted to a blx. */ | |
22553 | if (fixP->fx_addsy | |
22554 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 22555 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22556 | && ARM_IS_FUNC (fixP->fx_addsy) |
22557 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
22558 | { | |
22559 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
22560 | newval = newval & ~0x1000; | |
22561 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
22562 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; | |
22563 | fixP->fx_done = 1; | |
22564 | } | |
22565 | ||
22566 | thumb_bl_common: | |
22567 | ||
2fc8bdac ZW |
22568 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
22569 | /* For a BLX instruction, make sure that the relocation is rounded up | |
22570 | to a word boundary. This follows the semantics of the instruction | |
22571 | which specifies that bit 1 of the target address will come from bit | |
22572 | 1 of the base address. */ | |
d406f3e4 JB |
22573 | value = (value + 3) & ~ 3; |
22574 | ||
22575 | #ifdef OBJ_ELF | |
22576 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 | |
22577 | && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
22578 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
22579 | #endif | |
404ff6b5 | 22580 | |
2b2f5df9 NC |
22581 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
22582 | { | |
22583 | if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))) | |
22584 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); | |
22585 | else if ((value & ~0x1ffffff) | |
22586 | && ((value & ~0x1ffffff) != ~0x1ffffff)) | |
22587 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22588 | _("Thumb2 branch out of range")); | |
22589 | } | |
4a42ebbc RR |
22590 | |
22591 | if (fixP->fx_done || !seg->use_rela_p) | |
22592 | encode_thumb2_b_bl_offset (buf, value); | |
22593 | ||
c19d1205 | 22594 | break; |
404ff6b5 | 22595 | |
c19d1205 | 22596 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
08f10d51 NC |
22597 | if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff)) |
22598 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); | |
6c43fab6 | 22599 | |
2fc8bdac | 22600 | if (fixP->fx_done || !seg->use_rela_p) |
4a42ebbc | 22601 | encode_thumb2_b_bl_offset (buf, value); |
6c43fab6 | 22602 | |
2fc8bdac | 22603 | break; |
a737bd4d | 22604 | |
2fc8bdac ZW |
22605 | case BFD_RELOC_8: |
22606 | if (fixP->fx_done || !seg->use_rela_p) | |
4b1a927e | 22607 | *buf = value; |
c19d1205 | 22608 | break; |
a737bd4d | 22609 | |
c19d1205 | 22610 | case BFD_RELOC_16: |
2fc8bdac | 22611 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 22612 | md_number_to_chars (buf, value, 2); |
c19d1205 | 22613 | break; |
a737bd4d | 22614 | |
c19d1205 | 22615 | #ifdef OBJ_ELF |
0855e32b NS |
22616 | case BFD_RELOC_ARM_TLS_CALL: |
22617 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
22618 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
22619 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
0855e32b | 22620 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 ZW |
22621 | case BFD_RELOC_ARM_TLS_GD32: |
22622 | case BFD_RELOC_ARM_TLS_LE32: | |
22623 | case BFD_RELOC_ARM_TLS_IE32: | |
22624 | case BFD_RELOC_ARM_TLS_LDM32: | |
22625 | case BFD_RELOC_ARM_TLS_LDO32: | |
22626 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
4b1a927e | 22627 | break; |
6c43fab6 | 22628 | |
c19d1205 ZW |
22629 | case BFD_RELOC_ARM_GOT32: |
22630 | case BFD_RELOC_ARM_GOTOFF: | |
c19d1205 | 22631 | break; |
b43420e6 NC |
22632 | |
22633 | case BFD_RELOC_ARM_GOT_PREL: | |
22634 | if (fixP->fx_done || !seg->use_rela_p) | |
477330fc | 22635 | md_number_to_chars (buf, value, 4); |
b43420e6 NC |
22636 | break; |
22637 | ||
9a6f4e97 NS |
22638 | case BFD_RELOC_ARM_TARGET2: |
22639 | /* TARGET2 is not partial-inplace, so we need to write the | |
477330fc RM |
22640 | addend here for REL targets, because it won't be written out |
22641 | during reloc processing later. */ | |
9a6f4e97 NS |
22642 | if (fixP->fx_done || !seg->use_rela_p) |
22643 | md_number_to_chars (buf, fixP->fx_offset, 4); | |
22644 | break; | |
c19d1205 | 22645 | #endif |
6c43fab6 | 22646 | |
c19d1205 ZW |
22647 | case BFD_RELOC_RVA: |
22648 | case BFD_RELOC_32: | |
22649 | case BFD_RELOC_ARM_TARGET1: | |
22650 | case BFD_RELOC_ARM_ROSEGREL32: | |
22651 | case BFD_RELOC_ARM_SBREL32: | |
22652 | case BFD_RELOC_32_PCREL: | |
f0927246 NC |
22653 | #ifdef TE_PE |
22654 | case BFD_RELOC_32_SECREL: | |
22655 | #endif | |
2fc8bdac | 22656 | if (fixP->fx_done || !seg->use_rela_p) |
53baae48 NC |
22657 | #ifdef TE_WINCE |
22658 | /* For WinCE we only do this for pcrel fixups. */ | |
22659 | if (fixP->fx_done || fixP->fx_pcrel) | |
22660 | #endif | |
22661 | md_number_to_chars (buf, value, 4); | |
c19d1205 | 22662 | break; |
6c43fab6 | 22663 | |
c19d1205 ZW |
22664 | #ifdef OBJ_ELF |
22665 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 22666 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
22667 | { |
22668 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
22669 | if ((value ^ (value >> 1)) & 0x40000000) | |
22670 | { | |
22671 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22672 | _("rel31 relocation overflow")); | |
22673 | } | |
22674 | newval |= value & 0x7fffffff; | |
22675 | md_number_to_chars (buf, newval, 4); | |
22676 | } | |
22677 | break; | |
c19d1205 | 22678 | #endif |
a737bd4d | 22679 | |
c19d1205 | 22680 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 22681 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
22682 | if (value < -1023 || value > 1023 || (value & 3)) |
22683 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22684 | _("co-processor offset out of range")); | |
22685 | cp_off_common: | |
26d97720 | 22686 | sign = value > 0; |
c19d1205 ZW |
22687 | if (value < 0) |
22688 | value = -value; | |
8f06b2d8 PB |
22689 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
22690 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
22691 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22692 | else | |
22693 | newval = get_thumb32_insn (buf); | |
26d97720 NS |
22694 | if (value == 0) |
22695 | newval &= 0xffffff00; | |
22696 | else | |
22697 | { | |
22698 | newval &= 0xff7fff00; | |
22699 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); | |
22700 | } | |
8f06b2d8 PB |
22701 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
22702 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
22703 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22704 | else | |
22705 | put_thumb32_insn (buf, newval); | |
c19d1205 | 22706 | break; |
a737bd4d | 22707 | |
c19d1205 | 22708 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 22709 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
22710 | if (value < -255 || value > 255) |
22711 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22712 | _("co-processor offset out of range")); | |
df7849c5 | 22713 | value *= 4; |
c19d1205 | 22714 | goto cp_off_common; |
6c43fab6 | 22715 | |
c19d1205 ZW |
22716 | case BFD_RELOC_ARM_THUMB_OFFSET: |
22717 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22718 | /* Exactly what ranges, and where the offset is inserted depends | |
22719 | on the type of instruction, we can establish this from the | |
22720 | top 4 bits. */ | |
22721 | switch (newval >> 12) | |
22722 | { | |
22723 | case 4: /* PC load. */ | |
22724 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
22725 | forced to zero for these loads; md_pcrel_from has already | |
22726 | compensated for this. */ | |
22727 | if (value & 3) | |
22728 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22729 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
22730 | (((unsigned long) fixP->fx_frag->fr_address |
22731 | + (unsigned long) fixP->fx_where) & ~3) | |
22732 | + (unsigned long) value); | |
a737bd4d | 22733 | |
c19d1205 ZW |
22734 | if (value & ~0x3fc) |
22735 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22736 | _("invalid offset, value too big (0x%08lX)"), | |
22737 | (long) value); | |
a737bd4d | 22738 | |
c19d1205 ZW |
22739 | newval |= value >> 2; |
22740 | break; | |
a737bd4d | 22741 | |
c19d1205 ZW |
22742 | case 9: /* SP load/store. */ |
22743 | if (value & ~0x3fc) | |
22744 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22745 | _("invalid offset, value too big (0x%08lX)"), | |
22746 | (long) value); | |
22747 | newval |= value >> 2; | |
22748 | break; | |
6c43fab6 | 22749 | |
c19d1205 ZW |
22750 | case 6: /* Word load/store. */ |
22751 | if (value & ~0x7c) | |
22752 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22753 | _("invalid offset, value too big (0x%08lX)"), | |
22754 | (long) value); | |
22755 | newval |= value << 4; /* 6 - 2. */ | |
22756 | break; | |
a737bd4d | 22757 | |
c19d1205 ZW |
22758 | case 7: /* Byte load/store. */ |
22759 | if (value & ~0x1f) | |
22760 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22761 | _("invalid offset, value too big (0x%08lX)"), | |
22762 | (long) value); | |
22763 | newval |= value << 6; | |
22764 | break; | |
a737bd4d | 22765 | |
c19d1205 ZW |
22766 | case 8: /* Halfword load/store. */ |
22767 | if (value & ~0x3e) | |
22768 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22769 | _("invalid offset, value too big (0x%08lX)"), | |
22770 | (long) value); | |
22771 | newval |= value << 5; /* 6 - 1. */ | |
22772 | break; | |
a737bd4d | 22773 | |
c19d1205 ZW |
22774 | default: |
22775 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22776 | "Unable to process relocation for thumb opcode: %lx", | |
22777 | (unsigned long) newval); | |
22778 | break; | |
22779 | } | |
22780 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22781 | break; | |
a737bd4d | 22782 | |
c19d1205 ZW |
22783 | case BFD_RELOC_ARM_THUMB_ADD: |
22784 | /* This is a complicated relocation, since we use it for all of | |
22785 | the following immediate relocations: | |
a737bd4d | 22786 | |
c19d1205 ZW |
22787 | 3bit ADD/SUB |
22788 | 8bit ADD/SUB | |
22789 | 9bit ADD/SUB SP word-aligned | |
22790 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 22791 | |
c19d1205 ZW |
22792 | The type of instruction being processed is encoded in the |
22793 | instruction field: | |
a737bd4d | 22794 | |
c19d1205 ZW |
22795 | 0x8000 SUB |
22796 | 0x00F0 Rd | |
22797 | 0x000F Rs | |
22798 | */ | |
22799 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22800 | { | |
22801 | int rd = (newval >> 4) & 0xf; | |
22802 | int rs = newval & 0xf; | |
22803 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 22804 | |
c19d1205 ZW |
22805 | /* Check for HI regs, only very restricted cases allowed: |
22806 | Adjusting SP, and using PC or SP to get an address. */ | |
22807 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
22808 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
22809 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22810 | _("invalid Hi register with immediate")); | |
a737bd4d | 22811 | |
c19d1205 ZW |
22812 | /* If value is negative, choose the opposite instruction. */ |
22813 | if (value < 0) | |
22814 | { | |
22815 | value = -value; | |
22816 | subtract = !subtract; | |
22817 | if (value < 0) | |
22818 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22819 | _("immediate value out of range")); | |
22820 | } | |
a737bd4d | 22821 | |
c19d1205 ZW |
22822 | if (rd == REG_SP) |
22823 | { | |
22824 | if (value & ~0x1fc) | |
22825 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22826 | _("invalid immediate for stack address calculation")); | |
22827 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
22828 | newval |= value >> 2; | |
22829 | } | |
22830 | else if (rs == REG_PC || rs == REG_SP) | |
22831 | { | |
22832 | if (subtract || value & ~0x3fc) | |
22833 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22834 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
22835 | (unsigned long) value); | |
22836 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
22837 | newval |= rd << 8; | |
22838 | newval |= value >> 2; | |
22839 | } | |
22840 | else if (rs == rd) | |
22841 | { | |
22842 | if (value & ~0xff) | |
22843 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22844 | _("immediate value out of range")); | |
22845 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
22846 | newval |= (rd << 8) | value; | |
22847 | } | |
22848 | else | |
22849 | { | |
22850 | if (value & ~0x7) | |
22851 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22852 | _("immediate value out of range")); | |
22853 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
22854 | newval |= rd | (rs << 3) | (value << 6); | |
22855 | } | |
22856 | } | |
22857 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22858 | break; | |
a737bd4d | 22859 | |
c19d1205 ZW |
22860 | case BFD_RELOC_ARM_THUMB_IMM: |
22861 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22862 | if (value < 0 || value > 255) | |
22863 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4e6e072b | 22864 | _("invalid immediate: %ld is out of range"), |
c19d1205 ZW |
22865 | (long) value); |
22866 | newval |= value; | |
22867 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22868 | break; | |
a737bd4d | 22869 | |
c19d1205 ZW |
22870 | case BFD_RELOC_ARM_THUMB_SHIFT: |
22871 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
22872 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
22873 | temp = newval & 0xf800; | |
22874 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
22875 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22876 | _("invalid shift value: %ld"), (long) value); | |
22877 | /* Shifts of zero must be encoded as LSL. */ | |
22878 | if (value == 0) | |
22879 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
22880 | /* Shifts of 32 are encoded as zero. */ | |
22881 | else if (value == 32) | |
22882 | value = 0; | |
22883 | newval |= value << 6; | |
22884 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22885 | break; | |
a737bd4d | 22886 | |
c19d1205 ZW |
22887 | case BFD_RELOC_VTABLE_INHERIT: |
22888 | case BFD_RELOC_VTABLE_ENTRY: | |
22889 | fixP->fx_done = 0; | |
22890 | return; | |
6c43fab6 | 22891 | |
b6895b4f PB |
22892 | case BFD_RELOC_ARM_MOVW: |
22893 | case BFD_RELOC_ARM_MOVT: | |
22894 | case BFD_RELOC_ARM_THUMB_MOVW: | |
22895 | case BFD_RELOC_ARM_THUMB_MOVT: | |
22896 | if (fixP->fx_done || !seg->use_rela_p) | |
22897 | { | |
22898 | /* REL format relocations are limited to a 16-bit addend. */ | |
22899 | if (!fixP->fx_done) | |
22900 | { | |
39623e12 | 22901 | if (value < -0x8000 || value > 0x7fff) |
b6895b4f | 22902 | as_bad_where (fixP->fx_file, fixP->fx_line, |
ff5075ca | 22903 | _("offset out of range")); |
b6895b4f PB |
22904 | } |
22905 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
22906 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
22907 | { | |
22908 | value >>= 16; | |
22909 | } | |
22910 | ||
22911 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
22912 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
22913 | { | |
22914 | newval = get_thumb32_insn (buf); | |
22915 | newval &= 0xfbf08f00; | |
22916 | newval |= (value & 0xf000) << 4; | |
22917 | newval |= (value & 0x0800) << 15; | |
22918 | newval |= (value & 0x0700) << 4; | |
22919 | newval |= (value & 0x00ff); | |
22920 | put_thumb32_insn (buf, newval); | |
22921 | } | |
22922 | else | |
22923 | { | |
22924 | newval = md_chars_to_number (buf, 4); | |
22925 | newval &= 0xfff0f000; | |
22926 | newval |= value & 0x0fff; | |
22927 | newval |= (value & 0xf000) << 4; | |
22928 | md_number_to_chars (buf, newval, 4); | |
22929 | } | |
22930 | } | |
22931 | return; | |
22932 | ||
4962c51a MS |
22933 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
22934 | case BFD_RELOC_ARM_ALU_PC_G0: | |
22935 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
22936 | case BFD_RELOC_ARM_ALU_PC_G1: | |
22937 | case BFD_RELOC_ARM_ALU_PC_G2: | |
22938 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
22939 | case BFD_RELOC_ARM_ALU_SB_G0: | |
22940 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
22941 | case BFD_RELOC_ARM_ALU_SB_G1: | |
22942 | case BFD_RELOC_ARM_ALU_SB_G2: | |
9c2799c2 | 22943 | gas_assert (!fixP->fx_done); |
4962c51a MS |
22944 | if (!seg->use_rela_p) |
22945 | { | |
477330fc RM |
22946 | bfd_vma insn; |
22947 | bfd_vma encoded_addend; | |
22948 | bfd_vma addend_abs = abs (value); | |
22949 | ||
22950 | /* Check that the absolute value of the addend can be | |
22951 | expressed as an 8-bit constant plus a rotation. */ | |
22952 | encoded_addend = encode_arm_immediate (addend_abs); | |
22953 | if (encoded_addend == (unsigned int) FAIL) | |
4962c51a | 22954 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
22955 | _("the offset 0x%08lX is not representable"), |
22956 | (unsigned long) addend_abs); | |
22957 | ||
22958 | /* Extract the instruction. */ | |
22959 | insn = md_chars_to_number (buf, INSN_SIZE); | |
22960 | ||
22961 | /* If the addend is positive, use an ADD instruction. | |
22962 | Otherwise use a SUB. Take care not to destroy the S bit. */ | |
22963 | insn &= 0xff1fffff; | |
22964 | if (value < 0) | |
22965 | insn |= 1 << 22; | |
22966 | else | |
22967 | insn |= 1 << 23; | |
22968 | ||
22969 | /* Place the encoded addend into the first 12 bits of the | |
22970 | instruction. */ | |
22971 | insn &= 0xfffff000; | |
22972 | insn |= encoded_addend; | |
22973 | ||
22974 | /* Update the instruction. */ | |
22975 | md_number_to_chars (buf, insn, INSN_SIZE); | |
4962c51a MS |
22976 | } |
22977 | break; | |
22978 | ||
22979 | case BFD_RELOC_ARM_LDR_PC_G0: | |
22980 | case BFD_RELOC_ARM_LDR_PC_G1: | |
22981 | case BFD_RELOC_ARM_LDR_PC_G2: | |
22982 | case BFD_RELOC_ARM_LDR_SB_G0: | |
22983 | case BFD_RELOC_ARM_LDR_SB_G1: | |
22984 | case BFD_RELOC_ARM_LDR_SB_G2: | |
9c2799c2 | 22985 | gas_assert (!fixP->fx_done); |
4962c51a | 22986 | if (!seg->use_rela_p) |
477330fc RM |
22987 | { |
22988 | bfd_vma insn; | |
22989 | bfd_vma addend_abs = abs (value); | |
4962c51a | 22990 | |
477330fc RM |
22991 | /* Check that the absolute value of the addend can be |
22992 | encoded in 12 bits. */ | |
22993 | if (addend_abs >= 0x1000) | |
4962c51a | 22994 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
22995 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), |
22996 | (unsigned long) addend_abs); | |
22997 | ||
22998 | /* Extract the instruction. */ | |
22999 | insn = md_chars_to_number (buf, INSN_SIZE); | |
23000 | ||
23001 | /* If the addend is negative, clear bit 23 of the instruction. | |
23002 | Otherwise set it. */ | |
23003 | if (value < 0) | |
23004 | insn &= ~(1 << 23); | |
23005 | else | |
23006 | insn |= 1 << 23; | |
23007 | ||
23008 | /* Place the absolute value of the addend into the first 12 bits | |
23009 | of the instruction. */ | |
23010 | insn &= 0xfffff000; | |
23011 | insn |= addend_abs; | |
23012 | ||
23013 | /* Update the instruction. */ | |
23014 | md_number_to_chars (buf, insn, INSN_SIZE); | |
23015 | } | |
4962c51a MS |
23016 | break; |
23017 | ||
23018 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
23019 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
23020 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
23021 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
23022 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
23023 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
9c2799c2 | 23024 | gas_assert (!fixP->fx_done); |
4962c51a | 23025 | if (!seg->use_rela_p) |
477330fc RM |
23026 | { |
23027 | bfd_vma insn; | |
23028 | bfd_vma addend_abs = abs (value); | |
4962c51a | 23029 | |
477330fc RM |
23030 | /* Check that the absolute value of the addend can be |
23031 | encoded in 8 bits. */ | |
23032 | if (addend_abs >= 0x100) | |
4962c51a | 23033 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23034 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), |
23035 | (unsigned long) addend_abs); | |
23036 | ||
23037 | /* Extract the instruction. */ | |
23038 | insn = md_chars_to_number (buf, INSN_SIZE); | |
23039 | ||
23040 | /* If the addend is negative, clear bit 23 of the instruction. | |
23041 | Otherwise set it. */ | |
23042 | if (value < 0) | |
23043 | insn &= ~(1 << 23); | |
23044 | else | |
23045 | insn |= 1 << 23; | |
23046 | ||
23047 | /* Place the first four bits of the absolute value of the addend | |
23048 | into the first 4 bits of the instruction, and the remaining | |
23049 | four into bits 8 .. 11. */ | |
23050 | insn &= 0xfffff0f0; | |
23051 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); | |
23052 | ||
23053 | /* Update the instruction. */ | |
23054 | md_number_to_chars (buf, insn, INSN_SIZE); | |
23055 | } | |
4962c51a MS |
23056 | break; |
23057 | ||
23058 | case BFD_RELOC_ARM_LDC_PC_G0: | |
23059 | case BFD_RELOC_ARM_LDC_PC_G1: | |
23060 | case BFD_RELOC_ARM_LDC_PC_G2: | |
23061 | case BFD_RELOC_ARM_LDC_SB_G0: | |
23062 | case BFD_RELOC_ARM_LDC_SB_G1: | |
23063 | case BFD_RELOC_ARM_LDC_SB_G2: | |
9c2799c2 | 23064 | gas_assert (!fixP->fx_done); |
4962c51a | 23065 | if (!seg->use_rela_p) |
477330fc RM |
23066 | { |
23067 | bfd_vma insn; | |
23068 | bfd_vma addend_abs = abs (value); | |
4962c51a | 23069 | |
477330fc RM |
23070 | /* Check that the absolute value of the addend is a multiple of |
23071 | four and, when divided by four, fits in 8 bits. */ | |
23072 | if (addend_abs & 0x3) | |
4962c51a | 23073 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23074 | _("bad offset 0x%08lX (must be word-aligned)"), |
23075 | (unsigned long) addend_abs); | |
4962c51a | 23076 | |
477330fc | 23077 | if ((addend_abs >> 2) > 0xff) |
4962c51a | 23078 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23079 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), |
23080 | (unsigned long) addend_abs); | |
23081 | ||
23082 | /* Extract the instruction. */ | |
23083 | insn = md_chars_to_number (buf, INSN_SIZE); | |
23084 | ||
23085 | /* If the addend is negative, clear bit 23 of the instruction. | |
23086 | Otherwise set it. */ | |
23087 | if (value < 0) | |
23088 | insn &= ~(1 << 23); | |
23089 | else | |
23090 | insn |= 1 << 23; | |
23091 | ||
23092 | /* Place the addend (divided by four) into the first eight | |
23093 | bits of the instruction. */ | |
23094 | insn &= 0xfffffff0; | |
23095 | insn |= addend_abs >> 2; | |
23096 | ||
23097 | /* Update the instruction. */ | |
23098 | md_number_to_chars (buf, insn, INSN_SIZE); | |
23099 | } | |
4962c51a MS |
23100 | break; |
23101 | ||
845b51d6 PB |
23102 | case BFD_RELOC_ARM_V4BX: |
23103 | /* This will need to go in the object file. */ | |
23104 | fixP->fx_done = 0; | |
23105 | break; | |
23106 | ||
c19d1205 ZW |
23107 | case BFD_RELOC_UNUSED: |
23108 | default: | |
23109 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23110 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
23111 | } | |
6c43fab6 RE |
23112 | } |
23113 | ||
c19d1205 ZW |
23114 | /* Translate internal representation of relocation info to BFD target |
23115 | format. */ | |
a737bd4d | 23116 | |
c19d1205 | 23117 | arelent * |
00a97672 | 23118 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 23119 | { |
c19d1205 ZW |
23120 | arelent * reloc; |
23121 | bfd_reloc_code_real_type code; | |
a737bd4d | 23122 | |
21d799b5 | 23123 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
a737bd4d | 23124 | |
21d799b5 | 23125 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
c19d1205 ZW |
23126 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
23127 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 23128 | |
2fc8bdac | 23129 | if (fixp->fx_pcrel) |
00a97672 RS |
23130 | { |
23131 | if (section->use_rela_p) | |
23132 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
23133 | else | |
23134 | fixp->fx_offset = reloc->address; | |
23135 | } | |
c19d1205 | 23136 | reloc->addend = fixp->fx_offset; |
a737bd4d | 23137 | |
c19d1205 | 23138 | switch (fixp->fx_r_type) |
a737bd4d | 23139 | { |
c19d1205 ZW |
23140 | case BFD_RELOC_8: |
23141 | if (fixp->fx_pcrel) | |
23142 | { | |
23143 | code = BFD_RELOC_8_PCREL; | |
23144 | break; | |
23145 | } | |
a737bd4d | 23146 | |
c19d1205 ZW |
23147 | case BFD_RELOC_16: |
23148 | if (fixp->fx_pcrel) | |
23149 | { | |
23150 | code = BFD_RELOC_16_PCREL; | |
23151 | break; | |
23152 | } | |
6c43fab6 | 23153 | |
c19d1205 ZW |
23154 | case BFD_RELOC_32: |
23155 | if (fixp->fx_pcrel) | |
23156 | { | |
23157 | code = BFD_RELOC_32_PCREL; | |
23158 | break; | |
23159 | } | |
a737bd4d | 23160 | |
b6895b4f PB |
23161 | case BFD_RELOC_ARM_MOVW: |
23162 | if (fixp->fx_pcrel) | |
23163 | { | |
23164 | code = BFD_RELOC_ARM_MOVW_PCREL; | |
23165 | break; | |
23166 | } | |
23167 | ||
23168 | case BFD_RELOC_ARM_MOVT: | |
23169 | if (fixp->fx_pcrel) | |
23170 | { | |
23171 | code = BFD_RELOC_ARM_MOVT_PCREL; | |
23172 | break; | |
23173 | } | |
23174 | ||
23175 | case BFD_RELOC_ARM_THUMB_MOVW: | |
23176 | if (fixp->fx_pcrel) | |
23177 | { | |
23178 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; | |
23179 | break; | |
23180 | } | |
23181 | ||
23182 | case BFD_RELOC_ARM_THUMB_MOVT: | |
23183 | if (fixp->fx_pcrel) | |
23184 | { | |
23185 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; | |
23186 | break; | |
23187 | } | |
23188 | ||
c19d1205 ZW |
23189 | case BFD_RELOC_NONE: |
23190 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
23191 | case BFD_RELOC_ARM_PCREL_BLX: | |
23192 | case BFD_RELOC_RVA: | |
23193 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
23194 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
23195 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
23196 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
23197 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
23198 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
c19d1205 ZW |
23199 | case BFD_RELOC_VTABLE_ENTRY: |
23200 | case BFD_RELOC_VTABLE_INHERIT: | |
f0927246 NC |
23201 | #ifdef TE_PE |
23202 | case BFD_RELOC_32_SECREL: | |
23203 | #endif | |
c19d1205 ZW |
23204 | code = fixp->fx_r_type; |
23205 | break; | |
a737bd4d | 23206 | |
00adf2d4 JB |
23207 | case BFD_RELOC_THUMB_PCREL_BLX: |
23208 | #ifdef OBJ_ELF | |
23209 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
23210 | code = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
23211 | else | |
23212 | #endif | |
23213 | code = BFD_RELOC_THUMB_PCREL_BLX; | |
23214 | break; | |
23215 | ||
c19d1205 ZW |
23216 | case BFD_RELOC_ARM_LITERAL: |
23217 | case BFD_RELOC_ARM_HWLITERAL: | |
23218 | /* If this is called then the a literal has | |
23219 | been referenced across a section boundary. */ | |
23220 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23221 | _("literal referenced across section boundary")); | |
23222 | return NULL; | |
a737bd4d | 23223 | |
c19d1205 | 23224 | #ifdef OBJ_ELF |
0855e32b NS |
23225 | case BFD_RELOC_ARM_TLS_CALL: |
23226 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
23227 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
23228 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
c19d1205 ZW |
23229 | case BFD_RELOC_ARM_GOT32: |
23230 | case BFD_RELOC_ARM_GOTOFF: | |
b43420e6 | 23231 | case BFD_RELOC_ARM_GOT_PREL: |
c19d1205 ZW |
23232 | case BFD_RELOC_ARM_PLT32: |
23233 | case BFD_RELOC_ARM_TARGET1: | |
23234 | case BFD_RELOC_ARM_ROSEGREL32: | |
23235 | case BFD_RELOC_ARM_SBREL32: | |
23236 | case BFD_RELOC_ARM_PREL31: | |
23237 | case BFD_RELOC_ARM_TARGET2: | |
23238 | case BFD_RELOC_ARM_TLS_LE32: | |
23239 | case BFD_RELOC_ARM_TLS_LDO32: | |
39b41c9c PB |
23240 | case BFD_RELOC_ARM_PCREL_CALL: |
23241 | case BFD_RELOC_ARM_PCREL_JUMP: | |
4962c51a MS |
23242 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
23243 | case BFD_RELOC_ARM_ALU_PC_G0: | |
23244 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
23245 | case BFD_RELOC_ARM_ALU_PC_G1: | |
23246 | case BFD_RELOC_ARM_ALU_PC_G2: | |
23247 | case BFD_RELOC_ARM_LDR_PC_G0: | |
23248 | case BFD_RELOC_ARM_LDR_PC_G1: | |
23249 | case BFD_RELOC_ARM_LDR_PC_G2: | |
23250 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
23251 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
23252 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
23253 | case BFD_RELOC_ARM_LDC_PC_G0: | |
23254 | case BFD_RELOC_ARM_LDC_PC_G1: | |
23255 | case BFD_RELOC_ARM_LDC_PC_G2: | |
23256 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
23257 | case BFD_RELOC_ARM_ALU_SB_G0: | |
23258 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
23259 | case BFD_RELOC_ARM_ALU_SB_G1: | |
23260 | case BFD_RELOC_ARM_ALU_SB_G2: | |
23261 | case BFD_RELOC_ARM_LDR_SB_G0: | |
23262 | case BFD_RELOC_ARM_LDR_SB_G1: | |
23263 | case BFD_RELOC_ARM_LDR_SB_G2: | |
23264 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
23265 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
23266 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
23267 | case BFD_RELOC_ARM_LDC_SB_G0: | |
23268 | case BFD_RELOC_ARM_LDC_SB_G1: | |
23269 | case BFD_RELOC_ARM_LDC_SB_G2: | |
845b51d6 | 23270 | case BFD_RELOC_ARM_V4BX: |
c19d1205 ZW |
23271 | code = fixp->fx_r_type; |
23272 | break; | |
a737bd4d | 23273 | |
0855e32b | 23274 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 ZW |
23275 | case BFD_RELOC_ARM_TLS_GD32: |
23276 | case BFD_RELOC_ARM_TLS_IE32: | |
23277 | case BFD_RELOC_ARM_TLS_LDM32: | |
23278 | /* BFD will include the symbol's address in the addend. | |
23279 | But we don't want that, so subtract it out again here. */ | |
23280 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
23281 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
23282 | code = fixp->fx_r_type; | |
23283 | break; | |
23284 | #endif | |
a737bd4d | 23285 | |
c19d1205 ZW |
23286 | case BFD_RELOC_ARM_IMMEDIATE: |
23287 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23288 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
23289 | return NULL; | |
a737bd4d | 23290 | |
c19d1205 ZW |
23291 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
23292 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23293 | _("ADRL used for a symbol not defined in the same file")); | |
23294 | return NULL; | |
a737bd4d | 23295 | |
c19d1205 | 23296 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
23297 | if (section->use_rela_p) |
23298 | { | |
23299 | code = fixp->fx_r_type; | |
23300 | break; | |
23301 | } | |
23302 | ||
c19d1205 ZW |
23303 | if (fixp->fx_addsy != NULL |
23304 | && !S_IS_DEFINED (fixp->fx_addsy) | |
23305 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 23306 | { |
c19d1205 ZW |
23307 | as_bad_where (fixp->fx_file, fixp->fx_line, |
23308 | _("undefined local label `%s'"), | |
23309 | S_GET_NAME (fixp->fx_addsy)); | |
23310 | return NULL; | |
a737bd4d NC |
23311 | } |
23312 | ||
c19d1205 ZW |
23313 | as_bad_where (fixp->fx_file, fixp->fx_line, |
23314 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
23315 | return NULL; | |
a737bd4d | 23316 | |
c19d1205 ZW |
23317 | default: |
23318 | { | |
23319 | char * type; | |
6c43fab6 | 23320 | |
c19d1205 ZW |
23321 | switch (fixp->fx_r_type) |
23322 | { | |
23323 | case BFD_RELOC_NONE: type = "NONE"; break; | |
23324 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
23325 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 23326 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
23327 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
23328 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
23329 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
db187cb9 | 23330 | case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break; |
8f06b2d8 | 23331 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
23332 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
23333 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
23334 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
23335 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
23336 | default: type = _("<unknown>"); break; | |
23337 | } | |
23338 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23339 | _("cannot represent %s relocation in this object file format"), | |
23340 | type); | |
23341 | return NULL; | |
23342 | } | |
a737bd4d | 23343 | } |
6c43fab6 | 23344 | |
c19d1205 ZW |
23345 | #ifdef OBJ_ELF |
23346 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
23347 | && GOT_symbol | |
23348 | && fixp->fx_addsy == GOT_symbol) | |
23349 | { | |
23350 | code = BFD_RELOC_ARM_GOTPC; | |
23351 | reloc->addend = fixp->fx_offset = reloc->address; | |
23352 | } | |
23353 | #endif | |
6c43fab6 | 23354 | |
c19d1205 | 23355 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 23356 | |
c19d1205 ZW |
23357 | if (reloc->howto == NULL) |
23358 | { | |
23359 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23360 | _("cannot represent %s relocation in this object file format"), | |
23361 | bfd_get_reloc_code_name (code)); | |
23362 | return NULL; | |
23363 | } | |
6c43fab6 | 23364 | |
c19d1205 ZW |
23365 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
23366 | vtable entry to be used in the relocation's section offset. */ | |
23367 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
23368 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 23369 | |
c19d1205 | 23370 | return reloc; |
6c43fab6 RE |
23371 | } |
23372 | ||
c19d1205 | 23373 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 23374 | |
c19d1205 ZW |
23375 | void |
23376 | cons_fix_new_arm (fragS * frag, | |
23377 | int where, | |
23378 | int size, | |
62ebcb5c AM |
23379 | expressionS * exp, |
23380 | bfd_reloc_code_real_type reloc) | |
6c43fab6 | 23381 | { |
c19d1205 | 23382 | int pcrel = 0; |
6c43fab6 | 23383 | |
c19d1205 ZW |
23384 | /* Pick a reloc. |
23385 | FIXME: @@ Should look at CPU word size. */ | |
23386 | switch (size) | |
23387 | { | |
23388 | case 1: | |
62ebcb5c | 23389 | reloc = BFD_RELOC_8; |
c19d1205 ZW |
23390 | break; |
23391 | case 2: | |
62ebcb5c | 23392 | reloc = BFD_RELOC_16; |
c19d1205 ZW |
23393 | break; |
23394 | case 4: | |
23395 | default: | |
62ebcb5c | 23396 | reloc = BFD_RELOC_32; |
c19d1205 ZW |
23397 | break; |
23398 | case 8: | |
62ebcb5c | 23399 | reloc = BFD_RELOC_64; |
c19d1205 ZW |
23400 | break; |
23401 | } | |
6c43fab6 | 23402 | |
f0927246 NC |
23403 | #ifdef TE_PE |
23404 | if (exp->X_op == O_secrel) | |
23405 | { | |
23406 | exp->X_op = O_symbol; | |
62ebcb5c | 23407 | reloc = BFD_RELOC_32_SECREL; |
f0927246 NC |
23408 | } |
23409 | #endif | |
23410 | ||
62ebcb5c | 23411 | fix_new_exp (frag, where, size, exp, pcrel, reloc); |
c19d1205 | 23412 | } |
6c43fab6 | 23413 | |
4343666d | 23414 | #if defined (OBJ_COFF) |
c19d1205 ZW |
23415 | void |
23416 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 23417 | { |
c19d1205 ZW |
23418 | /* If the destination of the branch is a defined symbol which does not have |
23419 | the THUMB_FUNC attribute, then we must be calling a function which has | |
23420 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
23421 | function and change the branch to refer to that function instead. */ | |
23422 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
23423 | && fixP->fx_addsy != NULL | |
23424 | && S_IS_DEFINED (fixP->fx_addsy) | |
23425 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 23426 | { |
c19d1205 | 23427 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 23428 | } |
c19d1205 ZW |
23429 | } |
23430 | #endif | |
6c43fab6 | 23431 | |
267bf995 | 23432 | |
c19d1205 ZW |
23433 | int |
23434 | arm_force_relocation (struct fix * fixp) | |
23435 | { | |
23436 | #if defined (OBJ_COFF) && defined (TE_PE) | |
23437 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
23438 | return 1; | |
23439 | #endif | |
6c43fab6 | 23440 | |
267bf995 RR |
23441 | /* In case we have a call or a branch to a function in ARM ISA mode from |
23442 | a thumb function or vice-versa force the relocation. These relocations | |
23443 | are cleared off for some cores that might have blx and simple transformations | |
23444 | are possible. */ | |
23445 | ||
23446 | #ifdef OBJ_ELF | |
23447 | switch (fixp->fx_r_type) | |
23448 | { | |
23449 | case BFD_RELOC_ARM_PCREL_JUMP: | |
23450 | case BFD_RELOC_ARM_PCREL_CALL: | |
23451 | case BFD_RELOC_THUMB_PCREL_BLX: | |
23452 | if (THUMB_IS_FUNC (fixp->fx_addsy)) | |
23453 | return 1; | |
23454 | break; | |
23455 | ||
23456 | case BFD_RELOC_ARM_PCREL_BLX: | |
23457 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
23458 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
23459 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
23460 | if (ARM_IS_FUNC (fixp->fx_addsy)) | |
23461 | return 1; | |
23462 | break; | |
23463 | ||
23464 | default: | |
23465 | break; | |
23466 | } | |
23467 | #endif | |
23468 | ||
b5884301 PB |
23469 | /* Resolve these relocations even if the symbol is extern or weak. |
23470 | Technically this is probably wrong due to symbol preemption. | |
23471 | In practice these relocations do not have enough range to be useful | |
23472 | at dynamic link time, and some code (e.g. in the Linux kernel) | |
23473 | expects these references to be resolved. */ | |
c19d1205 ZW |
23474 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE |
23475 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
b5884301 | 23476 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8 |
0110f2b8 | 23477 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
b5884301 PB |
23478 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
23479 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2 | |
23480 | || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET | |
16805f35 | 23481 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
0110f2b8 PB |
23482 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
23483 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
b5884301 PB |
23484 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM |
23485 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12 | |
23486 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM | |
23487 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2) | |
c19d1205 | 23488 | return 0; |
a737bd4d | 23489 | |
4962c51a MS |
23490 | /* Always leave these relocations for the linker. */ |
23491 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
23492 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
23493 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
23494 | return 1; | |
23495 | ||
f0291e4c PB |
23496 | /* Always generate relocations against function symbols. */ |
23497 | if (fixp->fx_r_type == BFD_RELOC_32 | |
23498 | && fixp->fx_addsy | |
23499 | && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) | |
23500 | return 1; | |
23501 | ||
c19d1205 | 23502 | return generic_force_reloc (fixp); |
404ff6b5 AH |
23503 | } |
23504 | ||
0ffdc86c | 23505 | #if defined (OBJ_ELF) || defined (OBJ_COFF) |
e28387c3 PB |
23506 | /* Relocations against function names must be left unadjusted, |
23507 | so that the linker can use this information to generate interworking | |
23508 | stubs. The MIPS version of this function | |
c19d1205 ZW |
23509 | also prevents relocations that are mips-16 specific, but I do not |
23510 | know why it does this. | |
404ff6b5 | 23511 | |
c19d1205 ZW |
23512 | FIXME: |
23513 | There is one other problem that ought to be addressed here, but | |
23514 | which currently is not: Taking the address of a label (rather | |
23515 | than a function) and then later jumping to that address. Such | |
23516 | addresses also ought to have their bottom bit set (assuming that | |
23517 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 23518 | |
c19d1205 ZW |
23519 | bfd_boolean |
23520 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 23521 | { |
c19d1205 ZW |
23522 | if (fixP->fx_addsy == NULL) |
23523 | return 1; | |
404ff6b5 | 23524 | |
e28387c3 PB |
23525 | /* Preserve relocations against symbols with function type. */ |
23526 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) | |
c921be7d | 23527 | return FALSE; |
e28387c3 | 23528 | |
c19d1205 ZW |
23529 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
23530 | && fixP->fx_subsy == NULL) | |
c921be7d | 23531 | return FALSE; |
a737bd4d | 23532 | |
c19d1205 ZW |
23533 | /* We need the symbol name for the VTABLE entries. */ |
23534 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
23535 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c921be7d | 23536 | return FALSE; |
404ff6b5 | 23537 | |
c19d1205 ZW |
23538 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
23539 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
23540 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
23541 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
23542 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
23543 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
23544 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
23545 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
23546 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
0855e32b NS |
23547 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC |
23548 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL | |
23549 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL | |
23550 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ | |
23551 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
c19d1205 | 23552 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) |
c921be7d | 23553 | return FALSE; |
a737bd4d | 23554 | |
4962c51a MS |
23555 | /* Similarly for group relocations. */ |
23556 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
23557 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
23558 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
c921be7d | 23559 | return FALSE; |
4962c51a | 23560 | |
79947c54 CD |
23561 | /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ |
23562 | if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW | |
23563 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
23564 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL | |
23565 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL | |
23566 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
23567 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT | |
23568 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL | |
23569 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) | |
c921be7d | 23570 | return FALSE; |
79947c54 | 23571 | |
c921be7d | 23572 | return TRUE; |
a737bd4d | 23573 | } |
0ffdc86c NC |
23574 | #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ |
23575 | ||
23576 | #ifdef OBJ_ELF | |
404ff6b5 | 23577 | |
c19d1205 ZW |
23578 | const char * |
23579 | elf32_arm_target_format (void) | |
404ff6b5 | 23580 | { |
c19d1205 ZW |
23581 | #ifdef TE_SYMBIAN |
23582 | return (target_big_endian | |
23583 | ? "elf32-bigarm-symbian" | |
23584 | : "elf32-littlearm-symbian"); | |
23585 | #elif defined (TE_VXWORKS) | |
23586 | return (target_big_endian | |
23587 | ? "elf32-bigarm-vxworks" | |
23588 | : "elf32-littlearm-vxworks"); | |
b38cadfb NC |
23589 | #elif defined (TE_NACL) |
23590 | return (target_big_endian | |
23591 | ? "elf32-bigarm-nacl" | |
23592 | : "elf32-littlearm-nacl"); | |
c19d1205 ZW |
23593 | #else |
23594 | if (target_big_endian) | |
23595 | return "elf32-bigarm"; | |
23596 | else | |
23597 | return "elf32-littlearm"; | |
23598 | #endif | |
404ff6b5 AH |
23599 | } |
23600 | ||
c19d1205 ZW |
23601 | void |
23602 | armelf_frob_symbol (symbolS * symp, | |
23603 | int * puntp) | |
404ff6b5 | 23604 | { |
c19d1205 ZW |
23605 | elf_frob_symbol (symp, puntp); |
23606 | } | |
23607 | #endif | |
404ff6b5 | 23608 | |
c19d1205 | 23609 | /* MD interface: Finalization. */ |
a737bd4d | 23610 | |
c19d1205 ZW |
23611 | void |
23612 | arm_cleanup (void) | |
23613 | { | |
23614 | literal_pool * pool; | |
a737bd4d | 23615 | |
e07e6e58 NC |
23616 | /* Ensure that all the IT blocks are properly closed. */ |
23617 | check_it_blocks_finished (); | |
23618 | ||
c19d1205 ZW |
23619 | for (pool = list_of_pools; pool; pool = pool->next) |
23620 | { | |
5f4273c7 | 23621 | /* Put it at the end of the relevant section. */ |
c19d1205 ZW |
23622 | subseg_set (pool->section, pool->sub_section); |
23623 | #ifdef OBJ_ELF | |
23624 | arm_elf_change_section (); | |
23625 | #endif | |
23626 | s_ltorg (0); | |
23627 | } | |
404ff6b5 AH |
23628 | } |
23629 | ||
cd000bff DJ |
23630 | #ifdef OBJ_ELF |
23631 | /* Remove any excess mapping symbols generated for alignment frags in | |
23632 | SEC. We may have created a mapping symbol before a zero byte | |
23633 | alignment; remove it if there's a mapping symbol after the | |
23634 | alignment. */ | |
23635 | static void | |
23636 | check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, | |
23637 | void *dummy ATTRIBUTE_UNUSED) | |
23638 | { | |
23639 | segment_info_type *seginfo = seg_info (sec); | |
23640 | fragS *fragp; | |
23641 | ||
23642 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
23643 | return; | |
23644 | ||
23645 | for (fragp = seginfo->frchainP->frch_root; | |
23646 | fragp != NULL; | |
23647 | fragp = fragp->fr_next) | |
23648 | { | |
23649 | symbolS *sym = fragp->tc_frag_data.last_map; | |
23650 | fragS *next = fragp->fr_next; | |
23651 | ||
23652 | /* Variable-sized frags have been converted to fixed size by | |
23653 | this point. But if this was variable-sized to start with, | |
23654 | there will be a fixed-size frag after it. So don't handle | |
23655 | next == NULL. */ | |
23656 | if (sym == NULL || next == NULL) | |
23657 | continue; | |
23658 | ||
23659 | if (S_GET_VALUE (sym) < next->fr_address) | |
23660 | /* Not at the end of this frag. */ | |
23661 | continue; | |
23662 | know (S_GET_VALUE (sym) == next->fr_address); | |
23663 | ||
23664 | do | |
23665 | { | |
23666 | if (next->tc_frag_data.first_map != NULL) | |
23667 | { | |
23668 | /* Next frag starts with a mapping symbol. Discard this | |
23669 | one. */ | |
23670 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
23671 | break; | |
23672 | } | |
23673 | ||
23674 | if (next->fr_next == NULL) | |
23675 | { | |
23676 | /* This mapping symbol is at the end of the section. Discard | |
23677 | it. */ | |
23678 | know (next->fr_fix == 0 && next->fr_var == 0); | |
23679 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
23680 | break; | |
23681 | } | |
23682 | ||
23683 | /* As long as we have empty frags without any mapping symbols, | |
23684 | keep looking. */ | |
23685 | /* If the next frag is non-empty and does not start with a | |
23686 | mapping symbol, then this mapping symbol is required. */ | |
23687 | if (next->fr_address != next->fr_next->fr_address) | |
23688 | break; | |
23689 | ||
23690 | next = next->fr_next; | |
23691 | } | |
23692 | while (next != NULL); | |
23693 | } | |
23694 | } | |
23695 | #endif | |
23696 | ||
c19d1205 ZW |
23697 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
23698 | ARM ones. */ | |
404ff6b5 | 23699 | |
c19d1205 ZW |
23700 | void |
23701 | arm_adjust_symtab (void) | |
404ff6b5 | 23702 | { |
c19d1205 ZW |
23703 | #ifdef OBJ_COFF |
23704 | symbolS * sym; | |
404ff6b5 | 23705 | |
c19d1205 ZW |
23706 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
23707 | { | |
23708 | if (ARM_IS_THUMB (sym)) | |
23709 | { | |
23710 | if (THUMB_IS_FUNC (sym)) | |
23711 | { | |
23712 | /* Mark the symbol as a Thumb function. */ | |
23713 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
23714 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
23715 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 23716 | |
c19d1205 ZW |
23717 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
23718 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
23719 | else | |
23720 | as_bad (_("%s: unexpected function type: %d"), | |
23721 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
23722 | } | |
23723 | else switch (S_GET_STORAGE_CLASS (sym)) | |
23724 | { | |
23725 | case C_EXT: | |
23726 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
23727 | break; | |
23728 | case C_STAT: | |
23729 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
23730 | break; | |
23731 | case C_LABEL: | |
23732 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
23733 | break; | |
23734 | default: | |
23735 | /* Do nothing. */ | |
23736 | break; | |
23737 | } | |
23738 | } | |
a737bd4d | 23739 | |
c19d1205 ZW |
23740 | if (ARM_IS_INTERWORK (sym)) |
23741 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 23742 | } |
c19d1205 ZW |
23743 | #endif |
23744 | #ifdef OBJ_ELF | |
23745 | symbolS * sym; | |
23746 | char bind; | |
404ff6b5 | 23747 | |
c19d1205 | 23748 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 23749 | { |
c19d1205 ZW |
23750 | if (ARM_IS_THUMB (sym)) |
23751 | { | |
23752 | elf_symbol_type * elf_sym; | |
404ff6b5 | 23753 | |
c19d1205 ZW |
23754 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
23755 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 23756 | |
b0796911 PB |
23757 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
23758 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) | |
c19d1205 ZW |
23759 | { |
23760 | /* If it's a .thumb_func, declare it as so, | |
23761 | otherwise tag label as .code 16. */ | |
23762 | if (THUMB_IS_FUNC (sym)) | |
35fc36a8 RS |
23763 | elf_sym->internal_elf_sym.st_target_internal |
23764 | = ST_BRANCH_TO_THUMB; | |
3ba67470 | 23765 | else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
c19d1205 ZW |
23766 | elf_sym->internal_elf_sym.st_info = |
23767 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
23768 | } | |
23769 | } | |
23770 | } | |
cd000bff DJ |
23771 | |
23772 | /* Remove any overlapping mapping symbols generated by alignment frags. */ | |
23773 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); | |
709001e9 MM |
23774 | /* Now do generic ELF adjustments. */ |
23775 | elf_adjust_symtab (); | |
c19d1205 | 23776 | #endif |
404ff6b5 AH |
23777 | } |
23778 | ||
c19d1205 | 23779 | /* MD interface: Initialization. */ |
404ff6b5 | 23780 | |
a737bd4d | 23781 | static void |
c19d1205 | 23782 | set_constant_flonums (void) |
a737bd4d | 23783 | { |
c19d1205 | 23784 | int i; |
404ff6b5 | 23785 | |
c19d1205 ZW |
23786 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
23787 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
23788 | abort (); | |
a737bd4d | 23789 | } |
404ff6b5 | 23790 | |
3e9e4fcf JB |
23791 | /* Auto-select Thumb mode if it's the only available instruction set for the |
23792 | given architecture. */ | |
23793 | ||
23794 | static void | |
23795 | autoselect_thumb_from_cpu_variant (void) | |
23796 | { | |
23797 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) | |
23798 | opcode_select (16); | |
23799 | } | |
23800 | ||
c19d1205 ZW |
23801 | void |
23802 | md_begin (void) | |
a737bd4d | 23803 | { |
c19d1205 ZW |
23804 | unsigned mach; |
23805 | unsigned int i; | |
404ff6b5 | 23806 | |
c19d1205 ZW |
23807 | if ( (arm_ops_hsh = hash_new ()) == NULL |
23808 | || (arm_cond_hsh = hash_new ()) == NULL | |
23809 | || (arm_shift_hsh = hash_new ()) == NULL | |
23810 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 23811 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 23812 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
23813 | || (arm_reloc_hsh = hash_new ()) == NULL |
23814 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
23815 | as_fatal (_("virtual memory exhausted")); |
23816 | ||
23817 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
d3ce72d0 | 23818 | hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); |
c19d1205 | 23819 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) |
d3ce72d0 | 23820 | hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); |
c19d1205 | 23821 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) |
5a49b8ac | 23822 | hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); |
c19d1205 | 23823 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 23824 | hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); |
62b3e311 | 23825 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 23826 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, |
477330fc | 23827 | (void *) (v7m_psrs + i)); |
c19d1205 | 23828 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
5a49b8ac | 23829 | hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); |
62b3e311 PB |
23830 | for (i = 0; |
23831 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
23832 | i++) | |
d3ce72d0 | 23833 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, |
5a49b8ac | 23834 | (void *) (barrier_opt_names + i)); |
c19d1205 | 23835 | #ifdef OBJ_ELF |
3da1d841 NC |
23836 | for (i = 0; i < ARRAY_SIZE (reloc_names); i++) |
23837 | { | |
23838 | struct reloc_entry * entry = reloc_names + i; | |
23839 | ||
23840 | if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32) | |
23841 | /* This makes encode_branch() use the EABI versions of this relocation. */ | |
23842 | entry->reloc = BFD_RELOC_UNUSED; | |
23843 | ||
23844 | hash_insert (arm_reloc_hsh, entry->name, (void *) entry); | |
23845 | } | |
c19d1205 ZW |
23846 | #endif |
23847 | ||
23848 | set_constant_flonums (); | |
404ff6b5 | 23849 | |
c19d1205 ZW |
23850 | /* Set the cpu variant based on the command-line options. We prefer |
23851 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
23852 | -mfpu= over any other way of setting the floating point unit. | |
23853 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 23854 | if (legacy_cpu) |
404ff6b5 | 23855 | { |
e74cfd16 | 23856 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
23857 | as_bad (_("use of old and new-style options to set CPU type")); |
23858 | ||
23859 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 23860 | } |
e74cfd16 | 23861 | else if (!mcpu_cpu_opt) |
c19d1205 | 23862 | mcpu_cpu_opt = march_cpu_opt; |
404ff6b5 | 23863 | |
e74cfd16 | 23864 | if (legacy_fpu) |
c19d1205 | 23865 | { |
e74cfd16 | 23866 | if (mfpu_opt) |
c19d1205 | 23867 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f RE |
23868 | |
23869 | mfpu_opt = legacy_fpu; | |
23870 | } | |
e74cfd16 | 23871 | else if (!mfpu_opt) |
03b1477f | 23872 | { |
45eb4c1b NS |
23873 | #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ |
23874 | || defined (TE_NetBSD) || defined (TE_VXWORKS)) | |
39c2da32 RE |
23875 | /* Some environments specify a default FPU. If they don't, infer it |
23876 | from the processor. */ | |
e74cfd16 | 23877 | if (mcpu_fpu_opt) |
03b1477f RE |
23878 | mfpu_opt = mcpu_fpu_opt; |
23879 | else | |
23880 | mfpu_opt = march_fpu_opt; | |
39c2da32 | 23881 | #else |
e74cfd16 | 23882 | mfpu_opt = &fpu_default; |
39c2da32 | 23883 | #endif |
03b1477f RE |
23884 | } |
23885 | ||
e74cfd16 | 23886 | if (!mfpu_opt) |
03b1477f | 23887 | { |
493cb6ef | 23888 | if (mcpu_cpu_opt != NULL) |
e74cfd16 | 23889 | mfpu_opt = &fpu_default; |
493cb6ef | 23890 | else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) |
e74cfd16 | 23891 | mfpu_opt = &fpu_arch_vfp_v2; |
03b1477f | 23892 | else |
e74cfd16 | 23893 | mfpu_opt = &fpu_arch_fpa; |
03b1477f RE |
23894 | } |
23895 | ||
ee065d83 | 23896 | #ifdef CPU_DEFAULT |
e74cfd16 | 23897 | if (!mcpu_cpu_opt) |
ee065d83 | 23898 | { |
e74cfd16 PB |
23899 | mcpu_cpu_opt = &cpu_default; |
23900 | selected_cpu = cpu_default; | |
ee065d83 | 23901 | } |
e74cfd16 PB |
23902 | #else |
23903 | if (mcpu_cpu_opt) | |
23904 | selected_cpu = *mcpu_cpu_opt; | |
ee065d83 | 23905 | else |
e74cfd16 | 23906 | mcpu_cpu_opt = &arm_arch_any; |
ee065d83 | 23907 | #endif |
03b1477f | 23908 | |
e74cfd16 | 23909 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
03b1477f | 23910 | |
3e9e4fcf JB |
23911 | autoselect_thumb_from_cpu_variant (); |
23912 | ||
e74cfd16 | 23913 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 23914 | |
f17c130b | 23915 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 23916 | { |
7cc69913 NC |
23917 | unsigned int flags = 0; |
23918 | ||
23919 | #if defined OBJ_ELF | |
23920 | flags = meabi_flags; | |
d507cf36 PB |
23921 | |
23922 | switch (meabi_flags) | |
33a392fb | 23923 | { |
d507cf36 | 23924 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 23925 | #endif |
d507cf36 PB |
23926 | /* Set the flags in the private structure. */ |
23927 | if (uses_apcs_26) flags |= F_APCS26; | |
23928 | if (support_interwork) flags |= F_INTERWORK; | |
23929 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 23930 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 23931 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
23932 | flags |= F_SOFT_FLOAT; |
23933 | ||
d507cf36 PB |
23934 | switch (mfloat_abi_opt) |
23935 | { | |
23936 | case ARM_FLOAT_ABI_SOFT: | |
23937 | case ARM_FLOAT_ABI_SOFTFP: | |
23938 | flags |= F_SOFT_FLOAT; | |
23939 | break; | |
33a392fb | 23940 | |
d507cf36 PB |
23941 | case ARM_FLOAT_ABI_HARD: |
23942 | if (flags & F_SOFT_FLOAT) | |
23943 | as_bad (_("hard-float conflicts with specified fpu")); | |
23944 | break; | |
23945 | } | |
03b1477f | 23946 | |
e74cfd16 PB |
23947 | /* Using pure-endian doubles (even if soft-float). */ |
23948 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 23949 | flags |= F_VFP_FLOAT; |
f17c130b | 23950 | |
fde78edd | 23951 | #if defined OBJ_ELF |
e74cfd16 | 23952 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 23953 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
23954 | break; |
23955 | ||
8cb51566 | 23956 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 23957 | case EF_ARM_EABI_VER5: |
c19d1205 | 23958 | /* No additional flags to set. */ |
d507cf36 PB |
23959 | break; |
23960 | ||
23961 | default: | |
23962 | abort (); | |
23963 | } | |
7cc69913 | 23964 | #endif |
b99bd4ef NC |
23965 | bfd_set_private_flags (stdoutput, flags); |
23966 | ||
23967 | /* We have run out flags in the COFF header to encode the | |
23968 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 23969 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
23970 | if (atpcs) |
23971 | { | |
23972 | asection * sec; | |
23973 | ||
23974 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
23975 | ||
23976 | if (sec != NULL) | |
23977 | { | |
23978 | bfd_set_section_flags | |
23979 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
23980 | bfd_set_section_size (stdoutput, sec, 0); | |
23981 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
23982 | } | |
23983 | } | |
7cc69913 | 23984 | } |
f17c130b | 23985 | #endif |
b99bd4ef NC |
23986 | |
23987 | /* Record the CPU type as well. */ | |
2d447fca JM |
23988 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) |
23989 | mach = bfd_mach_arm_iWMMXt2; | |
23990 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) | |
e16bb312 | 23991 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 23992 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 23993 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 23994 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 23995 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 23996 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 23997 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 23998 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 23999 | { |
e74cfd16 | 24000 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
24001 | mach = bfd_mach_arm_5T; |
24002 | else | |
24003 | mach = bfd_mach_arm_5; | |
24004 | } | |
e74cfd16 | 24005 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 24006 | { |
e74cfd16 | 24007 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
24008 | mach = bfd_mach_arm_4T; |
24009 | else | |
24010 | mach = bfd_mach_arm_4; | |
24011 | } | |
e74cfd16 | 24012 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 24013 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
24014 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
24015 | mach = bfd_mach_arm_3; | |
24016 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
24017 | mach = bfd_mach_arm_2a; | |
24018 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
24019 | mach = bfd_mach_arm_2; | |
24020 | else | |
24021 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
24022 | |
24023 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
24024 | } | |
24025 | ||
c19d1205 | 24026 | /* Command line processing. */ |
b99bd4ef | 24027 | |
c19d1205 ZW |
24028 | /* md_parse_option |
24029 | Invocation line includes a switch not recognized by the base assembler. | |
24030 | See if it's a processor-specific option. | |
b99bd4ef | 24031 | |
c19d1205 ZW |
24032 | This routine is somewhat complicated by the need for backwards |
24033 | compatibility (since older releases of gcc can't be changed). | |
24034 | The new options try to make the interface as compatible as | |
24035 | possible with GCC. | |
b99bd4ef | 24036 | |
c19d1205 | 24037 | New options (supported) are: |
b99bd4ef | 24038 | |
c19d1205 ZW |
24039 | -mcpu=<cpu name> Assemble for selected processor |
24040 | -march=<architecture name> Assemble for selected architecture | |
24041 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
24042 | -EB/-mbig-endian Big-endian | |
24043 | -EL/-mlittle-endian Little-endian | |
24044 | -k Generate PIC code | |
24045 | -mthumb Start in Thumb mode | |
24046 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 24047 | |
278df34e | 24048 | -m[no-]warn-deprecated Warn about deprecated features |
267bf995 | 24049 | |
c19d1205 | 24050 | For now we will also provide support for: |
b99bd4ef | 24051 | |
c19d1205 ZW |
24052 | -mapcs-32 32-bit Program counter |
24053 | -mapcs-26 26-bit Program counter | |
24054 | -macps-float Floats passed in FP registers | |
24055 | -mapcs-reentrant Reentrant code | |
24056 | -matpcs | |
24057 | (sometime these will probably be replaced with -mapcs=<list of options> | |
24058 | and -matpcs=<list of options>) | |
b99bd4ef | 24059 | |
c19d1205 ZW |
24060 | The remaining options are only supported for back-wards compatibility. |
24061 | Cpu variants, the arm part is optional: | |
24062 | -m[arm]1 Currently not supported. | |
24063 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
24064 | -m[arm]3 Arm 3 processor | |
24065 | -m[arm]6[xx], Arm 6 processors | |
24066 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
24067 | -m[arm]8[10] Arm 8 processors | |
24068 | -m[arm]9[20][tdmi] Arm 9 processors | |
24069 | -mstrongarm[110[0]] StrongARM processors | |
24070 | -mxscale XScale processors | |
24071 | -m[arm]v[2345[t[e]]] Arm architectures | |
24072 | -mall All (except the ARM1) | |
24073 | FP variants: | |
24074 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
24075 | -mfpe-old (No float load/store multiples) | |
24076 | -mvfpxd VFP Single precision | |
24077 | -mvfp All VFP | |
24078 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 24079 | |
c19d1205 ZW |
24080 | The following CPU names are recognized: |
24081 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
24082 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
24083 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
24084 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
24085 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
24086 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
24087 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 24088 | |
c19d1205 | 24089 | */ |
b99bd4ef | 24090 | |
c19d1205 | 24091 | const char * md_shortopts = "m:k"; |
b99bd4ef | 24092 | |
c19d1205 ZW |
24093 | #ifdef ARM_BI_ENDIAN |
24094 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
24095 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 24096 | #else |
c19d1205 ZW |
24097 | #if TARGET_BYTES_BIG_ENDIAN |
24098 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 24099 | #else |
c19d1205 ZW |
24100 | #define OPTION_EL (OPTION_MD_BASE + 1) |
24101 | #endif | |
b99bd4ef | 24102 | #endif |
845b51d6 | 24103 | #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) |
b99bd4ef | 24104 | |
c19d1205 | 24105 | struct option md_longopts[] = |
b99bd4ef | 24106 | { |
c19d1205 ZW |
24107 | #ifdef OPTION_EB |
24108 | {"EB", no_argument, NULL, OPTION_EB}, | |
24109 | #endif | |
24110 | #ifdef OPTION_EL | |
24111 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 24112 | #endif |
845b51d6 | 24113 | {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, |
c19d1205 ZW |
24114 | {NULL, no_argument, NULL, 0} |
24115 | }; | |
b99bd4ef | 24116 | |
c19d1205 | 24117 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 24118 | |
c19d1205 | 24119 | struct arm_option_table |
b99bd4ef | 24120 | { |
c19d1205 ZW |
24121 | char *option; /* Option name to match. */ |
24122 | char *help; /* Help information. */ | |
24123 | int *var; /* Variable to change. */ | |
24124 | int value; /* What to change it to. */ | |
24125 | char *deprecated; /* If non-null, print this message. */ | |
24126 | }; | |
b99bd4ef | 24127 | |
c19d1205 ZW |
24128 | struct arm_option_table arm_opts[] = |
24129 | { | |
24130 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
24131 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
24132 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
24133 | &support_interwork, 1, NULL}, | |
24134 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
24135 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
24136 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
24137 | 1, NULL}, | |
24138 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
24139 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
24140 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
24141 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
24142 | NULL}, | |
b99bd4ef | 24143 | |
c19d1205 ZW |
24144 | /* These are recognized by the assembler, but have no affect on code. */ |
24145 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
24146 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
278df34e NS |
24147 | |
24148 | {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, | |
24149 | {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), | |
24150 | &warn_on_deprecated, 0, NULL}, | |
e74cfd16 PB |
24151 | {NULL, NULL, NULL, 0, NULL} |
24152 | }; | |
24153 | ||
24154 | struct arm_legacy_option_table | |
24155 | { | |
24156 | char *option; /* Option name to match. */ | |
24157 | const arm_feature_set **var; /* Variable to change. */ | |
24158 | const arm_feature_set value; /* What to change it to. */ | |
24159 | char *deprecated; /* If non-null, print this message. */ | |
24160 | }; | |
b99bd4ef | 24161 | |
e74cfd16 PB |
24162 | const struct arm_legacy_option_table arm_legacy_opts[] = |
24163 | { | |
c19d1205 ZW |
24164 | /* DON'T add any new processors to this list -- we want the whole list |
24165 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
24166 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
24167 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
24168 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
24169 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
24170 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
24171 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
24172 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
24173 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
24174 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
24175 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
24176 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
24177 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
24178 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
24179 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
24180 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
24181 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
24182 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
24183 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
24184 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
24185 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
24186 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
24187 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
24188 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
24189 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
24190 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
24191 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
24192 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
24193 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
24194 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
24195 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
24196 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
24197 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
24198 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
24199 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
24200 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
24201 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
24202 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
24203 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
24204 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
24205 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
24206 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
24207 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
24208 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
24209 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
24210 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
24211 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
24212 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
24213 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
24214 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
24215 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
24216 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
24217 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
24218 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
24219 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
24220 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
24221 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
24222 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
24223 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
24224 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
24225 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
24226 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
24227 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
24228 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
24229 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
24230 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
24231 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
24232 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
24233 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
24234 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
24235 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 24236 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 24237 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 24238 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 24239 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 24240 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
24241 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
24242 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
24243 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 24244 | |
c19d1205 | 24245 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
24246 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
24247 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
24248 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
24249 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
24250 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
24251 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
24252 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
24253 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
24254 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
24255 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
24256 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
24257 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
24258 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
24259 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
24260 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
24261 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
24262 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
24263 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 24264 | |
c19d1205 | 24265 | /* Floating point variants -- don't add any more to this list either. */ |
e74cfd16 PB |
24266 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
24267 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
24268 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
24269 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 24270 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 24271 | |
e74cfd16 | 24272 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 24273 | }; |
7ed4c4c5 | 24274 | |
c19d1205 | 24275 | struct arm_cpu_option_table |
7ed4c4c5 | 24276 | { |
c19d1205 | 24277 | char *name; |
f3bad469 | 24278 | size_t name_len; |
e74cfd16 | 24279 | const arm_feature_set value; |
c19d1205 ZW |
24280 | /* For some CPUs we assume an FPU unless the user explicitly sets |
24281 | -mfpu=... */ | |
e74cfd16 | 24282 | const arm_feature_set default_fpu; |
ee065d83 PB |
24283 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
24284 | case. */ | |
24285 | const char *canonical_name; | |
c19d1205 | 24286 | }; |
7ed4c4c5 | 24287 | |
c19d1205 ZW |
24288 | /* This list should, at a minimum, contain all the cpu names |
24289 | recognized by GCC. */ | |
f3bad469 | 24290 | #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN } |
e74cfd16 | 24291 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 24292 | { |
f3bad469 MGD |
24293 | ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL), |
24294 | ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL), | |
24295 | ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL), | |
24296 | ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL), | |
24297 | ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL), | |
24298 | ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24299 | ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24300 | ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24301 | ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24302 | ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24303 | ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24304 | ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
24305 | ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24306 | ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
24307 | ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24308 | ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
24309 | ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24310 | ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24311 | ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24312 | ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24313 | ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24314 | ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24315 | ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24316 | ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24317 | ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24318 | ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24319 | ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24320 | ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24321 | ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24322 | ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24323 | ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24324 | ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24325 | ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24326 | ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24327 | ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24328 | ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24329 | ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24330 | ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24331 | ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24332 | ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"), | |
24333 | ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24334 | ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24335 | ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24336 | ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24337 | ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24338 | ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
c19d1205 ZW |
24339 | /* For V5 or later processors we default to using VFP; but the user |
24340 | should really set the FPU type explicitly. */ | |
f3bad469 MGD |
24341 | ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), |
24342 | ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24343 | ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"), | |
24344 | ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"), | |
24345 | ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL), | |
24346 | ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), | |
24347 | ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"), | |
24348 | ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24349 | ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), | |
24350 | ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"), | |
24351 | ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24352 | ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24353 | ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
24354 | ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
24355 | ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24356 | ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"), | |
24357 | ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
24358 | ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24359 | ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24360 | ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, | |
24361 | "ARM1026EJ-S"), | |
24362 | ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL), | |
24363 | ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24364 | ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24365 | ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24366 | ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24367 | ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24368 | ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"), | |
24369 | ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL), | |
24370 | ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, | |
24371 | "ARM1136JF-S"), | |
24372 | ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL), | |
24373 | ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"), | |
24374 | ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"), | |
24375 | ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL), | |
24376 | ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL), | |
24377 | ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL), | |
24378 | ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL), | |
24379 | ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC, | |
24380 | FPU_NONE, "Cortex-A5"), | |
c9fb6e58 | 24381 | ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, |
f3bad469 MGD |
24382 | "Cortex-A7"), |
24383 | ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC, | |
24384 | ARM_FEATURE (0, FPU_VFP_V3 | |
477330fc | 24385 | | FPU_NEON_EXT_V1), |
f3bad469 MGD |
24386 | "Cortex-A8"), |
24387 | ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC, | |
24388 | ARM_FEATURE (0, FPU_VFP_V3 | |
477330fc | 24389 | | FPU_NEON_EXT_V1), |
f3bad469 | 24390 | "Cortex-A9"), |
c9fb6e58 | 24391 | ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, |
63a4bc21 | 24392 | "Cortex-A12"), |
c9fb6e58 | 24393 | ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, |
f3bad469 | 24394 | "Cortex-A15"), |
d7adf960 KT |
24395 | ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, |
24396 | "Cortex-A17"), | |
92eb40d9 | 24397 | ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
477330fc | 24398 | "Cortex-A53"), |
92eb40d9 | 24399 | ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
477330fc | 24400 | "Cortex-A57"), |
f3bad469 MGD |
24401 | ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"), |
24402 | ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16, | |
24403 | "Cortex-R4F"), | |
24404 | ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV, | |
24405 | FPU_NONE, "Cortex-R5"), | |
70a8bc5b | 24406 | ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV, |
24407 | FPU_ARCH_VFP_V3D16, | |
24408 | "Cortex-R7"), | |
f3bad469 MGD |
24409 | ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"), |
24410 | ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"), | |
24411 | ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"), | |
24412 | ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"), | |
ce32bd10 | 24413 | ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"), |
c19d1205 | 24414 | /* ??? XSCALE is really an architecture. */ |
f3bad469 | 24415 | ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), |
c19d1205 | 24416 | /* ??? iwmmxt is not a processor. */ |
f3bad469 MGD |
24417 | ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL), |
24418 | ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL), | |
24419 | ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), | |
c19d1205 | 24420 | /* Maverick */ |
f3bad469 | 24421 | ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), |
da4339ed NC |
24422 | FPU_ARCH_MAVERICK, "ARM920T"), |
24423 | /* Marvell processors. */ | |
4a81b02a | 24424 | ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, 0), |
477330fc | 24425 | FPU_ARCH_VFP_V3D16, NULL), |
da4339ed | 24426 | |
f3bad469 | 24427 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL } |
c19d1205 | 24428 | }; |
f3bad469 | 24429 | #undef ARM_CPU_OPT |
7ed4c4c5 | 24430 | |
c19d1205 | 24431 | struct arm_arch_option_table |
7ed4c4c5 | 24432 | { |
c19d1205 | 24433 | char *name; |
f3bad469 | 24434 | size_t name_len; |
e74cfd16 PB |
24435 | const arm_feature_set value; |
24436 | const arm_feature_set default_fpu; | |
c19d1205 | 24437 | }; |
7ed4c4c5 | 24438 | |
c19d1205 ZW |
24439 | /* This list should, at a minimum, contain all the architecture names |
24440 | recognized by GCC. */ | |
f3bad469 | 24441 | #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF } |
e74cfd16 | 24442 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 | 24443 | { |
f3bad469 MGD |
24444 | ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA), |
24445 | ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA), | |
24446 | ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA), | |
24447 | ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
24448 | ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
24449 | ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA), | |
24450 | ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA), | |
24451 | ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA), | |
24452 | ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA), | |
24453 | ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA), | |
24454 | ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA), | |
24455 | ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP), | |
24456 | ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP), | |
24457 | ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP), | |
24458 | ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP), | |
24459 | ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP), | |
24460 | ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP), | |
24461 | ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP), | |
24462 | ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP), | |
24463 | ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP), | |
24464 | ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP), | |
24465 | ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP), | |
24466 | ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP), | |
24467 | ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP), | |
24468 | ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP), | |
24469 | ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP), | |
24470 | ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP), | |
24471 | ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP), | |
24472 | ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP), | |
c450d570 PB |
24473 | /* The official spelling of the ARMv7 profile variants is the dashed form. |
24474 | Accept the non-dashed form for compatibility with old toolchains. */ | |
f3bad469 | 24475 | ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP), |
c9fb6e58 | 24476 | ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP), |
f3bad469 MGD |
24477 | ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP), |
24478 | ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP), | |
24479 | ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP), | |
24480 | ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP), | |
24481 | ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP), | |
24482 | ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP), | |
bca38921 | 24483 | ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP), |
f3bad469 MGD |
24484 | ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP), |
24485 | ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP), | |
24486 | ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP), | |
24487 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
c19d1205 | 24488 | }; |
f3bad469 | 24489 | #undef ARM_ARCH_OPT |
7ed4c4c5 | 24490 | |
69133863 MGD |
24491 | /* ISA extensions in the co-processor and main instruction set space. */ |
24492 | struct arm_option_extension_value_table | |
c19d1205 ZW |
24493 | { |
24494 | char *name; | |
f3bad469 | 24495 | size_t name_len; |
e74cfd16 | 24496 | const arm_feature_set value; |
69133863 | 24497 | const arm_feature_set allowed_archs; |
c19d1205 | 24498 | }; |
7ed4c4c5 | 24499 | |
69133863 MGD |
24500 | /* The following table must be in alphabetical order with a NULL last entry. |
24501 | */ | |
f3bad469 | 24502 | #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA } |
69133863 | 24503 | static const struct arm_option_extension_value_table arm_extensions[] = |
c19d1205 | 24504 | { |
dd5181d5 | 24505 | ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE (ARM_EXT_V8, 0)), |
bca38921 MGD |
24506 | ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
24507 | ARM_FEATURE (ARM_EXT_V8, 0)), | |
24508 | ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, | |
24509 | ARM_FEATURE (ARM_EXT_V8, 0)), | |
f3bad469 MGD |
24510 | ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0), |
24511 | ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)), | |
24512 | ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY), | |
24513 | ARM_EXT_OPT ("iwmmxt2", | |
24514 | ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY), | |
24515 | ARM_EXT_OPT ("maverick", | |
477330fc | 24516 | ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY), |
f3bad469 MGD |
24517 | ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0), |
24518 | ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)), | |
bca38921 MGD |
24519 | ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8, |
24520 | ARM_FEATURE (ARM_EXT_V8, 0)), | |
f3bad469 MGD |
24521 | ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0), |
24522 | ARM_FEATURE (ARM_EXT_V6M, 0)), | |
24523 | ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0), | |
24524 | ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)), | |
24525 | ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV | |
24526 | | ARM_EXT_DIV, 0), | |
24527 | ARM_FEATURE (ARM_EXT_V7A, 0)), | |
24528 | ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY), | |
24529 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
69133863 | 24530 | }; |
f3bad469 | 24531 | #undef ARM_EXT_OPT |
69133863 MGD |
24532 | |
24533 | /* ISA floating-point and Advanced SIMD extensions. */ | |
24534 | struct arm_option_fpu_value_table | |
24535 | { | |
24536 | char *name; | |
24537 | const arm_feature_set value; | |
c19d1205 | 24538 | }; |
7ed4c4c5 | 24539 | |
c19d1205 ZW |
24540 | /* This list should, at a minimum, contain all the fpu names |
24541 | recognized by GCC. */ | |
69133863 | 24542 | static const struct arm_option_fpu_value_table arm_fpus[] = |
c19d1205 ZW |
24543 | { |
24544 | {"softfpa", FPU_NONE}, | |
24545 | {"fpe", FPU_ARCH_FPE}, | |
24546 | {"fpe2", FPU_ARCH_FPE}, | |
24547 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
24548 | {"fpa", FPU_ARCH_FPA}, | |
24549 | {"fpa10", FPU_ARCH_FPA}, | |
24550 | {"fpa11", FPU_ARCH_FPA}, | |
24551 | {"arm7500fe", FPU_ARCH_FPA}, | |
24552 | {"softvfp", FPU_ARCH_VFP}, | |
24553 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
24554 | {"vfp", FPU_ARCH_VFP_V2}, | |
24555 | {"vfp9", FPU_ARCH_VFP_V2}, | |
b1cc4aeb | 24556 | {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */ |
c19d1205 ZW |
24557 | {"vfp10", FPU_ARCH_VFP_V2}, |
24558 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
24559 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
b1cc4aeb PB |
24560 | {"vfpv2", FPU_ARCH_VFP_V2}, |
24561 | {"vfpv3", FPU_ARCH_VFP_V3}, | |
62f3b8c8 | 24562 | {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16}, |
b1cc4aeb | 24563 | {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, |
62f3b8c8 PB |
24564 | {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16}, |
24565 | {"vfpv3xd", FPU_ARCH_VFP_V3xD}, | |
24566 | {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16}, | |
c19d1205 ZW |
24567 | {"arm1020t", FPU_ARCH_VFP_V1}, |
24568 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
24569 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
24570 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
24571 | {"maverick", FPU_ARCH_MAVERICK}, | |
5287ad62 | 24572 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
8e79c3df | 24573 | {"neon-fp16", FPU_ARCH_NEON_FP16}, |
62f3b8c8 PB |
24574 | {"vfpv4", FPU_ARCH_VFP_V4}, |
24575 | {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, | |
ada65aa3 | 24576 | {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, |
62f3b8c8 | 24577 | {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, |
bca38921 MGD |
24578 | {"fp-armv8", FPU_ARCH_VFP_ARMV8}, |
24579 | {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8}, | |
24580 | {"crypto-neon-fp-armv8", | |
24581 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8}, | |
e74cfd16 PB |
24582 | {NULL, ARM_ARCH_NONE} |
24583 | }; | |
24584 | ||
24585 | struct arm_option_value_table | |
24586 | { | |
24587 | char *name; | |
24588 | long value; | |
c19d1205 | 24589 | }; |
7ed4c4c5 | 24590 | |
e74cfd16 | 24591 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
24592 | { |
24593 | {"hard", ARM_FLOAT_ABI_HARD}, | |
24594 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
24595 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 24596 | {NULL, 0} |
c19d1205 | 24597 | }; |
7ed4c4c5 | 24598 | |
c19d1205 | 24599 | #ifdef OBJ_ELF |
3a4a14e9 | 24600 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 24601 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
24602 | { |
24603 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
24604 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 24605 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 24606 | {NULL, 0} |
c19d1205 ZW |
24607 | }; |
24608 | #endif | |
7ed4c4c5 | 24609 | |
c19d1205 ZW |
24610 | struct arm_long_option_table |
24611 | { | |
24612 | char * option; /* Substring to match. */ | |
24613 | char * help; /* Help information. */ | |
24614 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
24615 | char * deprecated; /* If non-null, print this message. */ | |
24616 | }; | |
7ed4c4c5 | 24617 | |
c921be7d | 24618 | static bfd_boolean |
f3bad469 | 24619 | arm_parse_extension (char *str, const arm_feature_set **opt_p) |
7ed4c4c5 | 24620 | { |
21d799b5 NC |
24621 | arm_feature_set *ext_set = (arm_feature_set *) |
24622 | xmalloc (sizeof (arm_feature_set)); | |
e74cfd16 | 24623 | |
69133863 | 24624 | /* We insist on extensions being specified in alphabetical order, and with |
fa94de6b RM |
24625 | extensions being added before being removed. We achieve this by having |
24626 | the global ARM_EXTENSIONS table in alphabetical order, and using the | |
69133863 | 24627 | ADDING_VALUE variable to indicate whether we are adding an extension (1) |
fa94de6b | 24628 | or removing it (0) and only allowing it to change in the order |
69133863 MGD |
24629 | -1 -> 1 -> 0. */ |
24630 | const struct arm_option_extension_value_table * opt = NULL; | |
24631 | int adding_value = -1; | |
24632 | ||
e74cfd16 PB |
24633 | /* Copy the feature set, so that we can modify it. */ |
24634 | *ext_set = **opt_p; | |
24635 | *opt_p = ext_set; | |
24636 | ||
c19d1205 | 24637 | while (str != NULL && *str != 0) |
7ed4c4c5 | 24638 | { |
f3bad469 MGD |
24639 | char *ext; |
24640 | size_t len; | |
7ed4c4c5 | 24641 | |
c19d1205 ZW |
24642 | if (*str != '+') |
24643 | { | |
24644 | as_bad (_("invalid architectural extension")); | |
c921be7d | 24645 | return FALSE; |
c19d1205 | 24646 | } |
7ed4c4c5 | 24647 | |
c19d1205 ZW |
24648 | str++; |
24649 | ext = strchr (str, '+'); | |
7ed4c4c5 | 24650 | |
c19d1205 | 24651 | if (ext != NULL) |
f3bad469 | 24652 | len = ext - str; |
c19d1205 | 24653 | else |
f3bad469 | 24654 | len = strlen (str); |
7ed4c4c5 | 24655 | |
f3bad469 | 24656 | if (len >= 2 && strncmp (str, "no", 2) == 0) |
69133863 MGD |
24657 | { |
24658 | if (adding_value != 0) | |
24659 | { | |
24660 | adding_value = 0; | |
24661 | opt = arm_extensions; | |
24662 | } | |
24663 | ||
f3bad469 | 24664 | len -= 2; |
69133863 MGD |
24665 | str += 2; |
24666 | } | |
f3bad469 | 24667 | else if (len > 0) |
69133863 MGD |
24668 | { |
24669 | if (adding_value == -1) | |
24670 | { | |
24671 | adding_value = 1; | |
24672 | opt = arm_extensions; | |
24673 | } | |
24674 | else if (adding_value != 1) | |
24675 | { | |
24676 | as_bad (_("must specify extensions to add before specifying " | |
24677 | "those to remove")); | |
24678 | return FALSE; | |
24679 | } | |
24680 | } | |
24681 | ||
f3bad469 | 24682 | if (len == 0) |
c19d1205 ZW |
24683 | { |
24684 | as_bad (_("missing architectural extension")); | |
c921be7d | 24685 | return FALSE; |
c19d1205 | 24686 | } |
7ed4c4c5 | 24687 | |
69133863 MGD |
24688 | gas_assert (adding_value != -1); |
24689 | gas_assert (opt != NULL); | |
24690 | ||
24691 | /* Scan over the options table trying to find an exact match. */ | |
24692 | for (; opt->name != NULL; opt++) | |
f3bad469 | 24693 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 24694 | { |
69133863 MGD |
24695 | /* Check we can apply the extension to this architecture. */ |
24696 | if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs)) | |
24697 | { | |
24698 | as_bad (_("extension does not apply to the base architecture")); | |
24699 | return FALSE; | |
24700 | } | |
24701 | ||
24702 | /* Add or remove the extension. */ | |
24703 | if (adding_value) | |
24704 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); | |
24705 | else | |
24706 | ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value); | |
24707 | ||
c19d1205 ZW |
24708 | break; |
24709 | } | |
7ed4c4c5 | 24710 | |
c19d1205 ZW |
24711 | if (opt->name == NULL) |
24712 | { | |
69133863 MGD |
24713 | /* Did we fail to find an extension because it wasn't specified in |
24714 | alphabetical order, or because it does not exist? */ | |
24715 | ||
24716 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
f3bad469 | 24717 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
69133863 MGD |
24718 | break; |
24719 | ||
24720 | if (opt->name == NULL) | |
24721 | as_bad (_("unknown architectural extension `%s'"), str); | |
24722 | else | |
24723 | as_bad (_("architectural extensions must be specified in " | |
24724 | "alphabetical order")); | |
24725 | ||
c921be7d | 24726 | return FALSE; |
c19d1205 | 24727 | } |
69133863 MGD |
24728 | else |
24729 | { | |
24730 | /* We should skip the extension we've just matched the next time | |
24731 | round. */ | |
24732 | opt++; | |
24733 | } | |
7ed4c4c5 | 24734 | |
c19d1205 ZW |
24735 | str = ext; |
24736 | }; | |
7ed4c4c5 | 24737 | |
c921be7d | 24738 | return TRUE; |
c19d1205 | 24739 | } |
7ed4c4c5 | 24740 | |
c921be7d | 24741 | static bfd_boolean |
f3bad469 | 24742 | arm_parse_cpu (char *str) |
7ed4c4c5 | 24743 | { |
f3bad469 MGD |
24744 | const struct arm_cpu_option_table *opt; |
24745 | char *ext = strchr (str, '+'); | |
24746 | size_t len; | |
7ed4c4c5 | 24747 | |
c19d1205 | 24748 | if (ext != NULL) |
f3bad469 | 24749 | len = ext - str; |
7ed4c4c5 | 24750 | else |
f3bad469 | 24751 | len = strlen (str); |
7ed4c4c5 | 24752 | |
f3bad469 | 24753 | if (len == 0) |
7ed4c4c5 | 24754 | { |
c19d1205 | 24755 | as_bad (_("missing cpu name `%s'"), str); |
c921be7d | 24756 | return FALSE; |
7ed4c4c5 NC |
24757 | } |
24758 | ||
c19d1205 | 24759 | for (opt = arm_cpus; opt->name != NULL; opt++) |
f3bad469 | 24760 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 24761 | { |
e74cfd16 PB |
24762 | mcpu_cpu_opt = &opt->value; |
24763 | mcpu_fpu_opt = &opt->default_fpu; | |
ee065d83 | 24764 | if (opt->canonical_name) |
5f4273c7 | 24765 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
24766 | else |
24767 | { | |
f3bad469 | 24768 | size_t i; |
c921be7d | 24769 | |
f3bad469 | 24770 | for (i = 0; i < len; i++) |
ee065d83 PB |
24771 | selected_cpu_name[i] = TOUPPER (opt->name[i]); |
24772 | selected_cpu_name[i] = 0; | |
24773 | } | |
7ed4c4c5 | 24774 | |
c19d1205 ZW |
24775 | if (ext != NULL) |
24776 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 24777 | |
c921be7d | 24778 | return TRUE; |
c19d1205 | 24779 | } |
7ed4c4c5 | 24780 | |
c19d1205 | 24781 | as_bad (_("unknown cpu `%s'"), str); |
c921be7d | 24782 | return FALSE; |
7ed4c4c5 NC |
24783 | } |
24784 | ||
c921be7d | 24785 | static bfd_boolean |
f3bad469 | 24786 | arm_parse_arch (char *str) |
7ed4c4c5 | 24787 | { |
e74cfd16 | 24788 | const struct arm_arch_option_table *opt; |
c19d1205 | 24789 | char *ext = strchr (str, '+'); |
f3bad469 | 24790 | size_t len; |
7ed4c4c5 | 24791 | |
c19d1205 | 24792 | if (ext != NULL) |
f3bad469 | 24793 | len = ext - str; |
7ed4c4c5 | 24794 | else |
f3bad469 | 24795 | len = strlen (str); |
7ed4c4c5 | 24796 | |
f3bad469 | 24797 | if (len == 0) |
7ed4c4c5 | 24798 | { |
c19d1205 | 24799 | as_bad (_("missing architecture name `%s'"), str); |
c921be7d | 24800 | return FALSE; |
7ed4c4c5 NC |
24801 | } |
24802 | ||
c19d1205 | 24803 | for (opt = arm_archs; opt->name != NULL; opt++) |
f3bad469 | 24804 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 24805 | { |
e74cfd16 PB |
24806 | march_cpu_opt = &opt->value; |
24807 | march_fpu_opt = &opt->default_fpu; | |
5f4273c7 | 24808 | strcpy (selected_cpu_name, opt->name); |
7ed4c4c5 | 24809 | |
c19d1205 ZW |
24810 | if (ext != NULL) |
24811 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 24812 | |
c921be7d | 24813 | return TRUE; |
c19d1205 ZW |
24814 | } |
24815 | ||
24816 | as_bad (_("unknown architecture `%s'\n"), str); | |
c921be7d | 24817 | return FALSE; |
7ed4c4c5 | 24818 | } |
eb043451 | 24819 | |
c921be7d | 24820 | static bfd_boolean |
c19d1205 ZW |
24821 | arm_parse_fpu (char * str) |
24822 | { | |
69133863 | 24823 | const struct arm_option_fpu_value_table * opt; |
b99bd4ef | 24824 | |
c19d1205 ZW |
24825 | for (opt = arm_fpus; opt->name != NULL; opt++) |
24826 | if (streq (opt->name, str)) | |
24827 | { | |
e74cfd16 | 24828 | mfpu_opt = &opt->value; |
c921be7d | 24829 | return TRUE; |
c19d1205 | 24830 | } |
b99bd4ef | 24831 | |
c19d1205 | 24832 | as_bad (_("unknown floating point format `%s'\n"), str); |
c921be7d | 24833 | return FALSE; |
c19d1205 ZW |
24834 | } |
24835 | ||
c921be7d | 24836 | static bfd_boolean |
c19d1205 | 24837 | arm_parse_float_abi (char * str) |
b99bd4ef | 24838 | { |
e74cfd16 | 24839 | const struct arm_option_value_table * opt; |
b99bd4ef | 24840 | |
c19d1205 ZW |
24841 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
24842 | if (streq (opt->name, str)) | |
24843 | { | |
24844 | mfloat_abi_opt = opt->value; | |
c921be7d | 24845 | return TRUE; |
c19d1205 | 24846 | } |
cc8a6dd0 | 24847 | |
c19d1205 | 24848 | as_bad (_("unknown floating point abi `%s'\n"), str); |
c921be7d | 24849 | return FALSE; |
c19d1205 | 24850 | } |
b99bd4ef | 24851 | |
c19d1205 | 24852 | #ifdef OBJ_ELF |
c921be7d | 24853 | static bfd_boolean |
c19d1205 ZW |
24854 | arm_parse_eabi (char * str) |
24855 | { | |
e74cfd16 | 24856 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 24857 | |
c19d1205 ZW |
24858 | for (opt = arm_eabis; opt->name != NULL; opt++) |
24859 | if (streq (opt->name, str)) | |
24860 | { | |
24861 | meabi_flags = opt->value; | |
c921be7d | 24862 | return TRUE; |
c19d1205 ZW |
24863 | } |
24864 | as_bad (_("unknown EABI `%s'\n"), str); | |
c921be7d | 24865 | return FALSE; |
c19d1205 ZW |
24866 | } |
24867 | #endif | |
cc8a6dd0 | 24868 | |
c921be7d | 24869 | static bfd_boolean |
e07e6e58 NC |
24870 | arm_parse_it_mode (char * str) |
24871 | { | |
c921be7d | 24872 | bfd_boolean ret = TRUE; |
e07e6e58 NC |
24873 | |
24874 | if (streq ("arm", str)) | |
24875 | implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
24876 | else if (streq ("thumb", str)) | |
24877 | implicit_it_mode = IMPLICIT_IT_MODE_THUMB; | |
24878 | else if (streq ("always", str)) | |
24879 | implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; | |
24880 | else if (streq ("never", str)) | |
24881 | implicit_it_mode = IMPLICIT_IT_MODE_NEVER; | |
24882 | else | |
24883 | { | |
24884 | as_bad (_("unknown implicit IT mode `%s', should be "\ | |
477330fc | 24885 | "arm, thumb, always, or never."), str); |
c921be7d | 24886 | ret = FALSE; |
e07e6e58 NC |
24887 | } |
24888 | ||
24889 | return ret; | |
24890 | } | |
24891 | ||
2e6976a8 DG |
24892 | static bfd_boolean |
24893 | arm_ccs_mode (char * unused ATTRIBUTE_UNUSED) | |
24894 | { | |
24895 | codecomposer_syntax = TRUE; | |
24896 | arm_comment_chars[0] = ';'; | |
24897 | arm_line_separator_chars[0] = 0; | |
24898 | return TRUE; | |
24899 | } | |
24900 | ||
c19d1205 ZW |
24901 | struct arm_long_option_table arm_long_opts[] = |
24902 | { | |
24903 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
24904 | arm_parse_cpu, NULL}, | |
24905 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
24906 | arm_parse_arch, NULL}, | |
24907 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
24908 | arm_parse_fpu, NULL}, | |
24909 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
24910 | arm_parse_float_abi, NULL}, | |
24911 | #ifdef OBJ_ELF | |
7fac0536 | 24912 | {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), |
c19d1205 ZW |
24913 | arm_parse_eabi, NULL}, |
24914 | #endif | |
e07e6e58 NC |
24915 | {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), |
24916 | arm_parse_it_mode, NULL}, | |
2e6976a8 DG |
24917 | {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"), |
24918 | arm_ccs_mode, NULL}, | |
c19d1205 ZW |
24919 | {NULL, NULL, 0, NULL} |
24920 | }; | |
cc8a6dd0 | 24921 | |
c19d1205 ZW |
24922 | int |
24923 | md_parse_option (int c, char * arg) | |
24924 | { | |
24925 | struct arm_option_table *opt; | |
e74cfd16 | 24926 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 24927 | struct arm_long_option_table *lopt; |
b99bd4ef | 24928 | |
c19d1205 | 24929 | switch (c) |
b99bd4ef | 24930 | { |
c19d1205 ZW |
24931 | #ifdef OPTION_EB |
24932 | case OPTION_EB: | |
24933 | target_big_endian = 1; | |
24934 | break; | |
24935 | #endif | |
cc8a6dd0 | 24936 | |
c19d1205 ZW |
24937 | #ifdef OPTION_EL |
24938 | case OPTION_EL: | |
24939 | target_big_endian = 0; | |
24940 | break; | |
24941 | #endif | |
b99bd4ef | 24942 | |
845b51d6 PB |
24943 | case OPTION_FIX_V4BX: |
24944 | fix_v4bx = TRUE; | |
24945 | break; | |
24946 | ||
c19d1205 ZW |
24947 | case 'a': |
24948 | /* Listing option. Just ignore these, we don't support additional | |
24949 | ones. */ | |
24950 | return 0; | |
b99bd4ef | 24951 | |
c19d1205 ZW |
24952 | default: |
24953 | for (opt = arm_opts; opt->option != NULL; opt++) | |
24954 | { | |
24955 | if (c == opt->option[0] | |
24956 | && ((arg == NULL && opt->option[1] == 0) | |
24957 | || streq (arg, opt->option + 1))) | |
24958 | { | |
c19d1205 | 24959 | /* If the option is deprecated, tell the user. */ |
278df34e | 24960 | if (warn_on_deprecated && opt->deprecated != NULL) |
c19d1205 ZW |
24961 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
24962 | arg ? arg : "", _(opt->deprecated)); | |
b99bd4ef | 24963 | |
c19d1205 ZW |
24964 | if (opt->var != NULL) |
24965 | *opt->var = opt->value; | |
cc8a6dd0 | 24966 | |
c19d1205 ZW |
24967 | return 1; |
24968 | } | |
24969 | } | |
b99bd4ef | 24970 | |
e74cfd16 PB |
24971 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
24972 | { | |
24973 | if (c == fopt->option[0] | |
24974 | && ((arg == NULL && fopt->option[1] == 0) | |
24975 | || streq (arg, fopt->option + 1))) | |
24976 | { | |
e74cfd16 | 24977 | /* If the option is deprecated, tell the user. */ |
278df34e | 24978 | if (warn_on_deprecated && fopt->deprecated != NULL) |
e74cfd16 PB |
24979 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
24980 | arg ? arg : "", _(fopt->deprecated)); | |
e74cfd16 PB |
24981 | |
24982 | if (fopt->var != NULL) | |
24983 | *fopt->var = &fopt->value; | |
24984 | ||
24985 | return 1; | |
24986 | } | |
24987 | } | |
24988 | ||
c19d1205 ZW |
24989 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
24990 | { | |
24991 | /* These options are expected to have an argument. */ | |
24992 | if (c == lopt->option[0] | |
24993 | && arg != NULL | |
24994 | && strncmp (arg, lopt->option + 1, | |
24995 | strlen (lopt->option + 1)) == 0) | |
24996 | { | |
c19d1205 | 24997 | /* If the option is deprecated, tell the user. */ |
278df34e | 24998 | if (warn_on_deprecated && lopt->deprecated != NULL) |
c19d1205 ZW |
24999 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, |
25000 | _(lopt->deprecated)); | |
b99bd4ef | 25001 | |
c19d1205 ZW |
25002 | /* Call the sup-option parser. */ |
25003 | return lopt->func (arg + strlen (lopt->option) - 1); | |
25004 | } | |
25005 | } | |
a737bd4d | 25006 | |
c19d1205 ZW |
25007 | return 0; |
25008 | } | |
a394c00f | 25009 | |
c19d1205 ZW |
25010 | return 1; |
25011 | } | |
a394c00f | 25012 | |
c19d1205 ZW |
25013 | void |
25014 | md_show_usage (FILE * fp) | |
a394c00f | 25015 | { |
c19d1205 ZW |
25016 | struct arm_option_table *opt; |
25017 | struct arm_long_option_table *lopt; | |
a394c00f | 25018 | |
c19d1205 | 25019 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 25020 | |
c19d1205 ZW |
25021 | for (opt = arm_opts; opt->option != NULL; opt++) |
25022 | if (opt->help != NULL) | |
25023 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 25024 | |
c19d1205 ZW |
25025 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
25026 | if (lopt->help != NULL) | |
25027 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 25028 | |
c19d1205 ZW |
25029 | #ifdef OPTION_EB |
25030 | fprintf (fp, _("\ | |
25031 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
25032 | #endif |
25033 | ||
c19d1205 ZW |
25034 | #ifdef OPTION_EL |
25035 | fprintf (fp, _("\ | |
25036 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 25037 | #endif |
845b51d6 PB |
25038 | |
25039 | fprintf (fp, _("\ | |
25040 | --fix-v4bx Allow BX in ARMv4 code\n")); | |
c19d1205 | 25041 | } |
ee065d83 PB |
25042 | |
25043 | ||
25044 | #ifdef OBJ_ELF | |
62b3e311 PB |
25045 | typedef struct |
25046 | { | |
25047 | int val; | |
25048 | arm_feature_set flags; | |
25049 | } cpu_arch_ver_table; | |
25050 | ||
25051 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted | |
25052 | least features first. */ | |
25053 | static const cpu_arch_ver_table cpu_arch_ver[] = | |
25054 | { | |
25055 | {1, ARM_ARCH_V4}, | |
25056 | {2, ARM_ARCH_V4T}, | |
25057 | {3, ARM_ARCH_V5}, | |
ee3c0378 | 25058 | {3, ARM_ARCH_V5T}, |
62b3e311 PB |
25059 | {4, ARM_ARCH_V5TE}, |
25060 | {5, ARM_ARCH_V5TEJ}, | |
25061 | {6, ARM_ARCH_V6}, | |
7e806470 | 25062 | {9, ARM_ARCH_V6K}, |
f4c65163 | 25063 | {7, ARM_ARCH_V6Z}, |
91e22acd | 25064 | {11, ARM_ARCH_V6M}, |
b2a5fbdc | 25065 | {12, ARM_ARCH_V6SM}, |
7e806470 | 25066 | {8, ARM_ARCH_V6T2}, |
c9fb6e58 | 25067 | {10, ARM_ARCH_V7VE}, |
62b3e311 PB |
25068 | {10, ARM_ARCH_V7R}, |
25069 | {10, ARM_ARCH_V7M}, | |
bca38921 | 25070 | {14, ARM_ARCH_V8A}, |
62b3e311 PB |
25071 | {0, ARM_ARCH_NONE} |
25072 | }; | |
25073 | ||
ee3c0378 AS |
25074 | /* Set an attribute if it has not already been set by the user. */ |
25075 | static void | |
25076 | aeabi_set_attribute_int (int tag, int value) | |
25077 | { | |
25078 | if (tag < 1 | |
25079 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
25080 | || !attributes_set_explicitly[tag]) | |
25081 | bfd_elf_add_proc_attr_int (stdoutput, tag, value); | |
25082 | } | |
25083 | ||
25084 | static void | |
25085 | aeabi_set_attribute_string (int tag, const char *value) | |
25086 | { | |
25087 | if (tag < 1 | |
25088 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
25089 | || !attributes_set_explicitly[tag]) | |
25090 | bfd_elf_add_proc_attr_string (stdoutput, tag, value); | |
25091 | } | |
25092 | ||
ee065d83 PB |
25093 | /* Set the public EABI object attributes. */ |
25094 | static void | |
25095 | aeabi_set_public_attributes (void) | |
25096 | { | |
25097 | int arch; | |
69239280 | 25098 | char profile; |
90ec0d68 | 25099 | int virt_sec = 0; |
bca38921 | 25100 | int fp16_optional = 0; |
e74cfd16 | 25101 | arm_feature_set flags; |
62b3e311 PB |
25102 | arm_feature_set tmp; |
25103 | const cpu_arch_ver_table *p; | |
ee065d83 PB |
25104 | |
25105 | /* Choose the architecture based on the capabilities of the requested cpu | |
25106 | (if any) and/or the instructions actually used. */ | |
e74cfd16 PB |
25107 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); |
25108 | ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); | |
25109 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); | |
ddd7f988 RE |
25110 | |
25111 | if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)) | |
25112 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1); | |
25113 | ||
25114 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any)) | |
25115 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t); | |
25116 | ||
7f78eb34 JW |
25117 | selected_cpu = flags; |
25118 | ||
ddd7f988 | 25119 | /* Allow the user to override the reported architecture. */ |
7a1d4c38 PB |
25120 | if (object_arch) |
25121 | { | |
25122 | ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); | |
25123 | ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); | |
25124 | } | |
25125 | ||
251665fc MGD |
25126 | /* We need to make sure that the attributes do not identify us as v6S-M |
25127 | when the only v6S-M feature in use is the Operating System Extensions. */ | |
25128 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os)) | |
25129 | if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only)) | |
477330fc | 25130 | ARM_CLEAR_FEATURE (flags, flags, arm_ext_os); |
251665fc | 25131 | |
62b3e311 PB |
25132 | tmp = flags; |
25133 | arch = 0; | |
25134 | for (p = cpu_arch_ver; p->val; p++) | |
25135 | { | |
25136 | if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) | |
25137 | { | |
25138 | arch = p->val; | |
25139 | ARM_CLEAR_FEATURE (tmp, tmp, p->flags); | |
25140 | } | |
25141 | } | |
ee065d83 | 25142 | |
9e3c6df6 PB |
25143 | /* The table lookup above finds the last architecture to contribute |
25144 | a new feature. Unfortunately, Tag13 is a subset of the union of | |
25145 | v6T2 and v7-M, so it is never seen as contributing a new feature. | |
25146 | We can not search for the last entry which is entirely used, | |
25147 | because if no CPU is specified we build up only those flags | |
25148 | actually used. Perhaps we should separate out the specified | |
25149 | and implicit cases. Avoid taking this path for -march=all by | |
25150 | checking for contradictory v7-A / v7-M features. */ | |
25151 | if (arch == 10 | |
25152 | && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a) | |
25153 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m) | |
25154 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp)) | |
25155 | arch = 13; | |
25156 | ||
ee065d83 PB |
25157 | /* Tag_CPU_name. */ |
25158 | if (selected_cpu_name[0]) | |
25159 | { | |
91d6fa6a | 25160 | char *q; |
ee065d83 | 25161 | |
91d6fa6a NC |
25162 | q = selected_cpu_name; |
25163 | if (strncmp (q, "armv", 4) == 0) | |
ee065d83 PB |
25164 | { |
25165 | int i; | |
5f4273c7 | 25166 | |
91d6fa6a NC |
25167 | q += 4; |
25168 | for (i = 0; q[i]; i++) | |
25169 | q[i] = TOUPPER (q[i]); | |
ee065d83 | 25170 | } |
91d6fa6a | 25171 | aeabi_set_attribute_string (Tag_CPU_name, q); |
ee065d83 | 25172 | } |
62f3b8c8 | 25173 | |
ee065d83 | 25174 | /* Tag_CPU_arch. */ |
ee3c0378 | 25175 | aeabi_set_attribute_int (Tag_CPU_arch, arch); |
62f3b8c8 | 25176 | |
62b3e311 PB |
25177 | /* Tag_CPU_arch_profile. */ |
25178 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) | |
69239280 | 25179 | profile = 'A'; |
62b3e311 | 25180 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) |
69239280 | 25181 | profile = 'R'; |
7e806470 | 25182 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m)) |
69239280 MGD |
25183 | profile = 'M'; |
25184 | else | |
25185 | profile = '\0'; | |
25186 | ||
25187 | if (profile != '\0') | |
25188 | aeabi_set_attribute_int (Tag_CPU_arch_profile, profile); | |
62f3b8c8 | 25189 | |
ee065d83 | 25190 | /* Tag_ARM_ISA_use. */ |
ee3c0378 AS |
25191 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) |
25192 | || arch == 0) | |
25193 | aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); | |
62f3b8c8 | 25194 | |
ee065d83 | 25195 | /* Tag_THUMB_ISA_use. */ |
ee3c0378 AS |
25196 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) |
25197 | || arch == 0) | |
25198 | aeabi_set_attribute_int (Tag_THUMB_ISA_use, | |
25199 | ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1); | |
62f3b8c8 | 25200 | |
ee065d83 | 25201 | /* Tag_VFP_arch. */ |
bca38921 MGD |
25202 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8)) |
25203 | aeabi_set_attribute_int (Tag_VFP_arch, 7); | |
25204 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) | |
62f3b8c8 PB |
25205 | aeabi_set_attribute_int (Tag_VFP_arch, |
25206 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
25207 | ? 5 : 6); | |
25208 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) | |
bca38921 MGD |
25209 | { |
25210 | fp16_optional = 1; | |
25211 | aeabi_set_attribute_int (Tag_VFP_arch, 3); | |
25212 | } | |
ada65aa3 | 25213 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) |
bca38921 MGD |
25214 | { |
25215 | aeabi_set_attribute_int (Tag_VFP_arch, 4); | |
25216 | fp16_optional = 1; | |
25217 | } | |
ee3c0378 AS |
25218 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) |
25219 | aeabi_set_attribute_int (Tag_VFP_arch, 2); | |
25220 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) | |
477330fc | 25221 | || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) |
ee3c0378 | 25222 | aeabi_set_attribute_int (Tag_VFP_arch, 1); |
62f3b8c8 | 25223 | |
4547cb56 NC |
25224 | /* Tag_ABI_HardFP_use. */ |
25225 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd) | |
25226 | && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)) | |
25227 | aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1); | |
25228 | ||
ee065d83 | 25229 | /* Tag_WMMX_arch. */ |
ee3c0378 AS |
25230 | if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) |
25231 | aeabi_set_attribute_int (Tag_WMMX_arch, 2); | |
25232 | else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) | |
25233 | aeabi_set_attribute_int (Tag_WMMX_arch, 1); | |
62f3b8c8 | 25234 | |
ee3c0378 | 25235 | /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ |
bca38921 MGD |
25236 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8)) |
25237 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3); | |
25238 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) | |
25239 | { | |
25240 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)) | |
25241 | { | |
25242 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2); | |
25243 | } | |
25244 | else | |
25245 | { | |
25246 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1); | |
25247 | fp16_optional = 1; | |
25248 | } | |
25249 | } | |
fa94de6b | 25250 | |
ee3c0378 | 25251 | /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ |
bca38921 | 25252 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional) |
ee3c0378 | 25253 | aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); |
4547cb56 | 25254 | |
69239280 MGD |
25255 | /* Tag_DIV_use. |
25256 | ||
25257 | We set Tag_DIV_use to two when integer divide instructions have been used | |
25258 | in ARM state, or when Thumb integer divide instructions have been used, | |
25259 | but we have no architecture profile set, nor have we any ARM instructions. | |
25260 | ||
bca38921 MGD |
25261 | For ARMv8 we set the tag to 0 as integer divide is implied by the base |
25262 | architecture. | |
25263 | ||
69239280 | 25264 | For new architectures we will have to check these tests. */ |
bca38921 MGD |
25265 | gas_assert (arch <= TAG_CPU_ARCH_V8); |
25266 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)) | |
25267 | aeabi_set_attribute_int (Tag_DIV_use, 0); | |
25268 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv) | |
25269 | || (profile == '\0' | |
25270 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_div) | |
25271 | && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))) | |
eea54501 | 25272 | aeabi_set_attribute_int (Tag_DIV_use, 2); |
60e5ef9f MGD |
25273 | |
25274 | /* Tag_MP_extension_use. */ | |
25275 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp)) | |
25276 | aeabi_set_attribute_int (Tag_MPextension_use, 1); | |
f4c65163 MGD |
25277 | |
25278 | /* Tag Virtualization_use. */ | |
25279 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec)) | |
90ec0d68 MGD |
25280 | virt_sec |= 1; |
25281 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt)) | |
25282 | virt_sec |= 2; | |
25283 | if (virt_sec != 0) | |
25284 | aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec); | |
ee065d83 PB |
25285 | } |
25286 | ||
104d59d1 | 25287 | /* Add the default contents for the .ARM.attributes section. */ |
ee065d83 PB |
25288 | void |
25289 | arm_md_end (void) | |
25290 | { | |
ee065d83 PB |
25291 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
25292 | return; | |
25293 | ||
25294 | aeabi_set_public_attributes (); | |
ee065d83 | 25295 | } |
8463be01 | 25296 | #endif /* OBJ_ELF */ |
ee065d83 PB |
25297 | |
25298 | ||
25299 | /* Parse a .cpu directive. */ | |
25300 | ||
25301 | static void | |
25302 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
25303 | { | |
e74cfd16 | 25304 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
25305 | char *name; |
25306 | char saved_char; | |
25307 | ||
25308 | name = input_line_pointer; | |
5f4273c7 | 25309 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
25310 | input_line_pointer++; |
25311 | saved_char = *input_line_pointer; | |
25312 | *input_line_pointer = 0; | |
25313 | ||
25314 | /* Skip the first "all" entry. */ | |
25315 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
25316 | if (streq (opt->name, name)) | |
25317 | { | |
e74cfd16 PB |
25318 | mcpu_cpu_opt = &opt->value; |
25319 | selected_cpu = opt->value; | |
ee065d83 | 25320 | if (opt->canonical_name) |
5f4273c7 | 25321 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
25322 | else |
25323 | { | |
25324 | int i; | |
25325 | for (i = 0; opt->name[i]; i++) | |
25326 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
f3bad469 | 25327 | |
ee065d83 PB |
25328 | selected_cpu_name[i] = 0; |
25329 | } | |
e74cfd16 | 25330 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
25331 | *input_line_pointer = saved_char; |
25332 | demand_empty_rest_of_line (); | |
25333 | return; | |
25334 | } | |
25335 | as_bad (_("unknown cpu `%s'"), name); | |
25336 | *input_line_pointer = saved_char; | |
25337 | ignore_rest_of_line (); | |
25338 | } | |
25339 | ||
25340 | ||
25341 | /* Parse a .arch directive. */ | |
25342 | ||
25343 | static void | |
25344 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
25345 | { | |
e74cfd16 | 25346 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
25347 | char saved_char; |
25348 | char *name; | |
25349 | ||
25350 | name = input_line_pointer; | |
5f4273c7 | 25351 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
25352 | input_line_pointer++; |
25353 | saved_char = *input_line_pointer; | |
25354 | *input_line_pointer = 0; | |
25355 | ||
25356 | /* Skip the first "all" entry. */ | |
25357 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
25358 | if (streq (opt->name, name)) | |
25359 | { | |
e74cfd16 PB |
25360 | mcpu_cpu_opt = &opt->value; |
25361 | selected_cpu = opt->value; | |
5f4273c7 | 25362 | strcpy (selected_cpu_name, opt->name); |
e74cfd16 | 25363 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
25364 | *input_line_pointer = saved_char; |
25365 | demand_empty_rest_of_line (); | |
25366 | return; | |
25367 | } | |
25368 | ||
25369 | as_bad (_("unknown architecture `%s'\n"), name); | |
25370 | *input_line_pointer = saved_char; | |
25371 | ignore_rest_of_line (); | |
25372 | } | |
25373 | ||
25374 | ||
7a1d4c38 PB |
25375 | /* Parse a .object_arch directive. */ |
25376 | ||
25377 | static void | |
25378 | s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) | |
25379 | { | |
25380 | const struct arm_arch_option_table *opt; | |
25381 | char saved_char; | |
25382 | char *name; | |
25383 | ||
25384 | name = input_line_pointer; | |
5f4273c7 | 25385 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
7a1d4c38 PB |
25386 | input_line_pointer++; |
25387 | saved_char = *input_line_pointer; | |
25388 | *input_line_pointer = 0; | |
25389 | ||
25390 | /* Skip the first "all" entry. */ | |
25391 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
25392 | if (streq (opt->name, name)) | |
25393 | { | |
25394 | object_arch = &opt->value; | |
25395 | *input_line_pointer = saved_char; | |
25396 | demand_empty_rest_of_line (); | |
25397 | return; | |
25398 | } | |
25399 | ||
25400 | as_bad (_("unknown architecture `%s'\n"), name); | |
25401 | *input_line_pointer = saved_char; | |
25402 | ignore_rest_of_line (); | |
25403 | } | |
25404 | ||
69133863 MGD |
25405 | /* Parse a .arch_extension directive. */ |
25406 | ||
25407 | static void | |
25408 | s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) | |
25409 | { | |
25410 | const struct arm_option_extension_value_table *opt; | |
25411 | char saved_char; | |
25412 | char *name; | |
25413 | int adding_value = 1; | |
25414 | ||
25415 | name = input_line_pointer; | |
25416 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
25417 | input_line_pointer++; | |
25418 | saved_char = *input_line_pointer; | |
25419 | *input_line_pointer = 0; | |
25420 | ||
25421 | if (strlen (name) >= 2 | |
25422 | && strncmp (name, "no", 2) == 0) | |
25423 | { | |
25424 | adding_value = 0; | |
25425 | name += 2; | |
25426 | } | |
25427 | ||
25428 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
25429 | if (streq (opt->name, name)) | |
25430 | { | |
25431 | if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs)) | |
25432 | { | |
25433 | as_bad (_("architectural extension `%s' is not allowed for the " | |
25434 | "current base architecture"), name); | |
25435 | break; | |
25436 | } | |
25437 | ||
25438 | if (adding_value) | |
25439 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value); | |
25440 | else | |
25441 | ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value); | |
25442 | ||
25443 | mcpu_cpu_opt = &selected_cpu; | |
25444 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
25445 | *input_line_pointer = saved_char; | |
25446 | demand_empty_rest_of_line (); | |
25447 | return; | |
25448 | } | |
25449 | ||
25450 | if (opt->name == NULL) | |
e673710a | 25451 | as_bad (_("unknown architecture extension `%s'\n"), name); |
69133863 MGD |
25452 | |
25453 | *input_line_pointer = saved_char; | |
25454 | ignore_rest_of_line (); | |
25455 | } | |
25456 | ||
ee065d83 PB |
25457 | /* Parse a .fpu directive. */ |
25458 | ||
25459 | static void | |
25460 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
25461 | { | |
69133863 | 25462 | const struct arm_option_fpu_value_table *opt; |
ee065d83 PB |
25463 | char saved_char; |
25464 | char *name; | |
25465 | ||
25466 | name = input_line_pointer; | |
5f4273c7 | 25467 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
25468 | input_line_pointer++; |
25469 | saved_char = *input_line_pointer; | |
25470 | *input_line_pointer = 0; | |
5f4273c7 | 25471 | |
ee065d83 PB |
25472 | for (opt = arm_fpus; opt->name != NULL; opt++) |
25473 | if (streq (opt->name, name)) | |
25474 | { | |
e74cfd16 PB |
25475 | mfpu_opt = &opt->value; |
25476 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
ee065d83 PB |
25477 | *input_line_pointer = saved_char; |
25478 | demand_empty_rest_of_line (); | |
25479 | return; | |
25480 | } | |
25481 | ||
25482 | as_bad (_("unknown floating point format `%s'\n"), name); | |
25483 | *input_line_pointer = saved_char; | |
25484 | ignore_rest_of_line (); | |
25485 | } | |
ee065d83 | 25486 | |
794ba86a | 25487 | /* Copy symbol information. */ |
f31fef98 | 25488 | |
794ba86a DJ |
25489 | void |
25490 | arm_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
25491 | { | |
25492 | ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); | |
25493 | } | |
e04befd0 | 25494 | |
f31fef98 | 25495 | #ifdef OBJ_ELF |
e04befd0 AS |
25496 | /* Given a symbolic attribute NAME, return the proper integer value. |
25497 | Returns -1 if the attribute is not known. */ | |
f31fef98 | 25498 | |
e04befd0 AS |
25499 | int |
25500 | arm_convert_symbolic_attribute (const char *name) | |
25501 | { | |
f31fef98 NC |
25502 | static const struct |
25503 | { | |
25504 | const char * name; | |
25505 | const int tag; | |
25506 | } | |
25507 | attribute_table[] = | |
25508 | { | |
25509 | /* When you modify this table you should | |
25510 | also modify the list in doc/c-arm.texi. */ | |
e04befd0 | 25511 | #define T(tag) {#tag, tag} |
f31fef98 NC |
25512 | T (Tag_CPU_raw_name), |
25513 | T (Tag_CPU_name), | |
25514 | T (Tag_CPU_arch), | |
25515 | T (Tag_CPU_arch_profile), | |
25516 | T (Tag_ARM_ISA_use), | |
25517 | T (Tag_THUMB_ISA_use), | |
75375b3e | 25518 | T (Tag_FP_arch), |
f31fef98 NC |
25519 | T (Tag_VFP_arch), |
25520 | T (Tag_WMMX_arch), | |
25521 | T (Tag_Advanced_SIMD_arch), | |
25522 | T (Tag_PCS_config), | |
25523 | T (Tag_ABI_PCS_R9_use), | |
25524 | T (Tag_ABI_PCS_RW_data), | |
25525 | T (Tag_ABI_PCS_RO_data), | |
25526 | T (Tag_ABI_PCS_GOT_use), | |
25527 | T (Tag_ABI_PCS_wchar_t), | |
25528 | T (Tag_ABI_FP_rounding), | |
25529 | T (Tag_ABI_FP_denormal), | |
25530 | T (Tag_ABI_FP_exceptions), | |
25531 | T (Tag_ABI_FP_user_exceptions), | |
25532 | T (Tag_ABI_FP_number_model), | |
75375b3e | 25533 | T (Tag_ABI_align_needed), |
f31fef98 | 25534 | T (Tag_ABI_align8_needed), |
75375b3e | 25535 | T (Tag_ABI_align_preserved), |
f31fef98 NC |
25536 | T (Tag_ABI_align8_preserved), |
25537 | T (Tag_ABI_enum_size), | |
25538 | T (Tag_ABI_HardFP_use), | |
25539 | T (Tag_ABI_VFP_args), | |
25540 | T (Tag_ABI_WMMX_args), | |
25541 | T (Tag_ABI_optimization_goals), | |
25542 | T (Tag_ABI_FP_optimization_goals), | |
25543 | T (Tag_compatibility), | |
25544 | T (Tag_CPU_unaligned_access), | |
75375b3e | 25545 | T (Tag_FP_HP_extension), |
f31fef98 NC |
25546 | T (Tag_VFP_HP_extension), |
25547 | T (Tag_ABI_FP_16bit_format), | |
cd21e546 MGD |
25548 | T (Tag_MPextension_use), |
25549 | T (Tag_DIV_use), | |
f31fef98 NC |
25550 | T (Tag_nodefaults), |
25551 | T (Tag_also_compatible_with), | |
25552 | T (Tag_conformance), | |
25553 | T (Tag_T2EE_use), | |
25554 | T (Tag_Virtualization_use), | |
cd21e546 | 25555 | /* We deliberately do not include Tag_MPextension_use_legacy. */ |
e04befd0 | 25556 | #undef T |
f31fef98 | 25557 | }; |
e04befd0 AS |
25558 | unsigned int i; |
25559 | ||
25560 | if (name == NULL) | |
25561 | return -1; | |
25562 | ||
f31fef98 | 25563 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
c921be7d | 25564 | if (streq (name, attribute_table[i].name)) |
e04befd0 AS |
25565 | return attribute_table[i].tag; |
25566 | ||
25567 | return -1; | |
25568 | } | |
267bf995 RR |
25569 | |
25570 | ||
25571 | /* Apply sym value for relocations only in the case that | |
25572 | they are for local symbols and you have the respective | |
25573 | architectural feature for blx and simple switches. */ | |
25574 | int | |
25575 | arm_apply_sym_value (struct fix * fixP) | |
25576 | { | |
25577 | if (fixP->fx_addsy | |
25578 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
34e77a92 | 25579 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
267bf995 RR |
25580 | { |
25581 | switch (fixP->fx_r_type) | |
25582 | { | |
25583 | case BFD_RELOC_ARM_PCREL_BLX: | |
25584 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
25585 | if (ARM_IS_FUNC (fixP->fx_addsy)) | |
25586 | return 1; | |
25587 | break; | |
25588 | ||
25589 | case BFD_RELOC_ARM_PCREL_CALL: | |
25590 | case BFD_RELOC_THUMB_PCREL_BLX: | |
25591 | if (THUMB_IS_FUNC (fixP->fx_addsy)) | |
25592 | return 1; | |
25593 | break; | |
25594 | ||
25595 | default: | |
25596 | break; | |
25597 | } | |
25598 | ||
25599 | } | |
25600 | return 0; | |
25601 | } | |
f31fef98 | 25602 | #endif /* OBJ_ELF */ |