Commit | Line | Data |
---|---|---|
b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
f17c130b | 2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
b43420e6 | 3 | 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
b99bd4ef NC |
4 | Free Software Foundation, Inc. |
5 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) | |
6 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 7 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
8 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
9 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
10 | |
11 | This file is part of GAS, the GNU Assembler. | |
12 | ||
13 | GAS is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 15 | the Free Software Foundation; either version 3, or (at your option) |
b99bd4ef NC |
16 | any later version. |
17 | ||
18 | GAS is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
21 | GNU General Public License for more details. |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
25 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
26 | 02110-1301, USA. */ | |
b99bd4ef | 27 | |
42a68e18 | 28 | #include "as.h" |
5287ad62 | 29 | #include <limits.h> |
037e8744 | 30 | #include <stdarg.h> |
c19d1205 | 31 | #define NO_RELOC 0 |
3882b010 | 32 | #include "safe-ctype.h" |
b99bd4ef NC |
33 | #include "subsegs.h" |
34 | #include "obstack.h" | |
b99bd4ef | 35 | |
f263249b RE |
36 | #include "opcode/arm.h" |
37 | ||
b99bd4ef NC |
38 | #ifdef OBJ_ELF |
39 | #include "elf/arm.h" | |
a394c00f | 40 | #include "dw2gencfi.h" |
b99bd4ef NC |
41 | #endif |
42 | ||
f0927246 NC |
43 | #include "dwarf2dbg.h" |
44 | ||
7ed4c4c5 NC |
45 | #ifdef OBJ_ELF |
46 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
47 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
48 | ||
49 | /* This structure holds the unwinding state. */ | |
50 | ||
51 | static struct | |
52 | { | |
c19d1205 ZW |
53 | symbolS * proc_start; |
54 | symbolS * table_entry; | |
55 | symbolS * personality_routine; | |
56 | int personality_index; | |
7ed4c4c5 | 57 | /* The segment containing the function. */ |
c19d1205 ZW |
58 | segT saved_seg; |
59 | subsegT saved_subseg; | |
7ed4c4c5 NC |
60 | /* Opcodes generated from this function. */ |
61 | unsigned char * opcodes; | |
c19d1205 ZW |
62 | int opcode_count; |
63 | int opcode_alloc; | |
7ed4c4c5 | 64 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 65 | offsetT frame_size; |
7ed4c4c5 NC |
66 | /* We don't add stack adjustment opcodes immediately so that we can merge |
67 | multiple adjustments. We can also omit the final adjustment | |
68 | when using a frame pointer. */ | |
c19d1205 | 69 | offsetT pending_offset; |
7ed4c4c5 | 70 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
71 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
72 | offsetT fp_offset; | |
73 | int fp_reg; | |
7ed4c4c5 | 74 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 75 | unsigned fp_used:1; |
7ed4c4c5 | 76 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 77 | unsigned sp_restored:1; |
7ed4c4c5 NC |
78 | } unwind; |
79 | ||
8b1ad454 NC |
80 | #endif /* OBJ_ELF */ |
81 | ||
4962c51a MS |
82 | /* Results from operand parsing worker functions. */ |
83 | ||
84 | typedef enum | |
85 | { | |
86 | PARSE_OPERAND_SUCCESS, | |
87 | PARSE_OPERAND_FAIL, | |
88 | PARSE_OPERAND_FAIL_NO_BACKTRACK | |
89 | } parse_operand_result; | |
90 | ||
33a392fb PB |
91 | enum arm_float_abi |
92 | { | |
93 | ARM_FLOAT_ABI_HARD, | |
94 | ARM_FLOAT_ABI_SOFTFP, | |
95 | ARM_FLOAT_ABI_SOFT | |
96 | }; | |
97 | ||
c19d1205 | 98 | /* Types of processor to assemble for. */ |
b99bd4ef | 99 | #ifndef CPU_DEFAULT |
8a59fff3 MGD |
100 | /* The code that was here used to select a default CPU depending on compiler |
101 | pre-defines which were only present when doing native builds, thus | |
102 | changing gas' default behaviour depending upon the build host. | |
103 | ||
104 | If you have a target that requires a default CPU option then the you | |
105 | should define CPU_DEFAULT here. */ | |
b99bd4ef NC |
106 | #endif |
107 | ||
108 | #ifndef FPU_DEFAULT | |
c820d418 MM |
109 | # ifdef TE_LINUX |
110 | # define FPU_DEFAULT FPU_ARCH_FPA | |
111 | # elif defined (TE_NetBSD) | |
112 | # ifdef OBJ_ELF | |
113 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
114 | # else | |
115 | /* Legacy a.out format. */ | |
116 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
117 | # endif | |
4e7fd91e PB |
118 | # elif defined (TE_VXWORKS) |
119 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
120 | # else |
121 | /* For backwards compatibility, default to FPA. */ | |
122 | # define FPU_DEFAULT FPU_ARCH_FPA | |
123 | # endif | |
124 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 125 | |
c19d1205 | 126 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 127 | |
e74cfd16 PB |
128 | static arm_feature_set cpu_variant; |
129 | static arm_feature_set arm_arch_used; | |
130 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 131 | |
b99bd4ef | 132 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
133 | static int uses_apcs_26 = FALSE; |
134 | static int atpcs = FALSE; | |
b34976b6 AM |
135 | static int support_interwork = FALSE; |
136 | static int uses_apcs_float = FALSE; | |
c19d1205 | 137 | static int pic_code = FALSE; |
845b51d6 | 138 | static int fix_v4bx = FALSE; |
278df34e NS |
139 | /* Warn on using deprecated features. */ |
140 | static int warn_on_deprecated = TRUE; | |
141 | ||
03b1477f RE |
142 | |
143 | /* Variables that we set while parsing command-line options. Once all | |
144 | options have been read we re-process these values to set the real | |
145 | assembly flags. */ | |
e74cfd16 PB |
146 | static const arm_feature_set *legacy_cpu = NULL; |
147 | static const arm_feature_set *legacy_fpu = NULL; | |
148 | ||
149 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
150 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
151 | static const arm_feature_set *march_cpu_opt = NULL; | |
152 | static const arm_feature_set *march_fpu_opt = NULL; | |
153 | static const arm_feature_set *mfpu_opt = NULL; | |
7a1d4c38 | 154 | static const arm_feature_set *object_arch = NULL; |
e74cfd16 PB |
155 | |
156 | /* Constants for known architecture features. */ | |
157 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
158 | static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; | |
159 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; | |
5287ad62 JB |
160 | static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; |
161 | static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; | |
e74cfd16 PB |
162 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
163 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
164 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; | |
165 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; | |
166 | ||
167 | #ifdef CPU_DEFAULT | |
168 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
169 | #endif | |
170 | ||
171 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); | |
172 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); | |
173 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); | |
174 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); | |
175 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); | |
176 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); | |
177 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); | |
178 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); | |
179 | static const arm_feature_set arm_ext_v4t_5 = | |
180 | ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); | |
181 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); | |
182 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); | |
183 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); | |
184 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); | |
185 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); | |
186 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); | |
187 | static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0); | |
188 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); | |
62b3e311 | 189 | static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); |
9e3c6df6 | 190 | static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0); |
7e806470 PB |
191 | static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0); |
192 | static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0); | |
62b3e311 PB |
193 | static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); |
194 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); | |
195 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); | |
196 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); | |
9e3c6df6 | 197 | static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); |
7e806470 PB |
198 | static const arm_feature_set arm_ext_m = |
199 | ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_V7M, 0); | |
e74cfd16 PB |
200 | |
201 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
202 | static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); | |
203 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; | |
204 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
205 | ||
2d447fca JM |
206 | static const arm_feature_set arm_cext_iwmmxt2 = |
207 | ARM_FEATURE (0, ARM_CEXT_IWMMXT2); | |
e74cfd16 PB |
208 | static const arm_feature_set arm_cext_iwmmxt = |
209 | ARM_FEATURE (0, ARM_CEXT_IWMMXT); | |
210 | static const arm_feature_set arm_cext_xscale = | |
211 | ARM_FEATURE (0, ARM_CEXT_XSCALE); | |
212 | static const arm_feature_set arm_cext_maverick = | |
213 | ARM_FEATURE (0, ARM_CEXT_MAVERICK); | |
214 | static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); | |
215 | static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); | |
216 | static const arm_feature_set fpu_vfp_ext_v1xd = | |
217 | ARM_FEATURE (0, FPU_VFP_EXT_V1xD); | |
218 | static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); | |
219 | static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); | |
62f3b8c8 | 220 | static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD); |
5287ad62 | 221 | static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); |
b1cc4aeb PB |
222 | static const arm_feature_set fpu_vfp_ext_d32 = |
223 | ARM_FEATURE (0, FPU_VFP_EXT_D32); | |
5287ad62 JB |
224 | static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); |
225 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = | |
226 | ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); | |
62f3b8c8 PB |
227 | static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16); |
228 | static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA); | |
229 | static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA); | |
e74cfd16 | 230 | |
33a392fb | 231 | static int mfloat_abi_opt = -1; |
e74cfd16 PB |
232 | /* Record user cpu selection for object attributes. */ |
233 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; | |
ee065d83 PB |
234 | /* Must be long enough to hold any of the names in arm_cpus. */ |
235 | static char selected_cpu_name[16]; | |
7cc69913 | 236 | #ifdef OBJ_ELF |
deeaaff8 DJ |
237 | # ifdef EABI_DEFAULT |
238 | static int meabi_flags = EABI_DEFAULT; | |
239 | # else | |
d507cf36 | 240 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 241 | # endif |
e1da3f5b | 242 | |
ee3c0378 AS |
243 | static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; |
244 | ||
e1da3f5b | 245 | bfd_boolean |
5f4273c7 | 246 | arm_is_eabi (void) |
e1da3f5b PB |
247 | { |
248 | return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); | |
249 | } | |
7cc69913 | 250 | #endif |
b99bd4ef | 251 | |
b99bd4ef | 252 | #ifdef OBJ_ELF |
c19d1205 | 253 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
254 | symbolS * GOT_symbol; |
255 | #endif | |
256 | ||
b99bd4ef NC |
257 | /* 0: assemble for ARM, |
258 | 1: assemble for Thumb, | |
259 | 2: assemble for Thumb even though target CPU does not support thumb | |
260 | instructions. */ | |
261 | static int thumb_mode = 0; | |
8dc2430f NC |
262 | /* A value distinct from the possible values for thumb_mode that we |
263 | can use to record whether thumb_mode has been copied into the | |
264 | tc_frag_data field of a frag. */ | |
265 | #define MODE_RECORDED (1 << 4) | |
b99bd4ef | 266 | |
e07e6e58 NC |
267 | /* Specifies the intrinsic IT insn behavior mode. */ |
268 | enum implicit_it_mode | |
269 | { | |
270 | IMPLICIT_IT_MODE_NEVER = 0x00, | |
271 | IMPLICIT_IT_MODE_ARM = 0x01, | |
272 | IMPLICIT_IT_MODE_THUMB = 0x02, | |
273 | IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) | |
274 | }; | |
275 | static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
276 | ||
c19d1205 ZW |
277 | /* If unified_syntax is true, we are processing the new unified |
278 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
279 | ||
280 | - Immediate operands do not require a # prefix. | |
281 | - Conditional affixes always appear at the end of the | |
282 | instruction. (For backward compatibility, those instructions | |
283 | that formerly had them in the middle, continue to accept them | |
284 | there.) | |
285 | - The IT instruction may appear, and if it does is validated | |
286 | against subsequent conditional affixes. It does not generate | |
287 | machine code. | |
288 | ||
289 | Important differences from the old Thumb mode: | |
290 | ||
291 | - Immediate operands do not require a # prefix. | |
292 | - Most of the V6T2 instructions are only available in unified mode. | |
293 | - The .N and .W suffixes are recognized and honored (it is an error | |
294 | if they cannot be honored). | |
295 | - All instructions set the flags if and only if they have an 's' affix. | |
296 | - Conditional affixes may be used. They are validated against | |
297 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
298 | conditional affix except in the scope of an IT instruction. */ | |
299 | ||
300 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef | 301 | |
5287ad62 JB |
302 | enum neon_el_type |
303 | { | |
dcbf9037 | 304 | NT_invtype, |
5287ad62 JB |
305 | NT_untyped, |
306 | NT_integer, | |
307 | NT_float, | |
308 | NT_poly, | |
309 | NT_signed, | |
dcbf9037 | 310 | NT_unsigned |
5287ad62 JB |
311 | }; |
312 | ||
313 | struct neon_type_el | |
314 | { | |
315 | enum neon_el_type type; | |
316 | unsigned size; | |
317 | }; | |
318 | ||
319 | #define NEON_MAX_TYPE_ELS 4 | |
320 | ||
321 | struct neon_type | |
322 | { | |
323 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; | |
324 | unsigned elems; | |
325 | }; | |
326 | ||
e07e6e58 NC |
327 | enum it_instruction_type |
328 | { | |
329 | OUTSIDE_IT_INSN, | |
330 | INSIDE_IT_INSN, | |
331 | INSIDE_IT_LAST_INSN, | |
332 | IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; | |
333 | if inside, should be the last one. */ | |
334 | NEUTRAL_IT_INSN, /* This could be either inside or outside, | |
335 | i.e. BKPT and NOP. */ | |
336 | IT_INSN /* The IT insn has been parsed. */ | |
337 | }; | |
338 | ||
b99bd4ef NC |
339 | struct arm_it |
340 | { | |
c19d1205 | 341 | const char * error; |
b99bd4ef | 342 | unsigned long instruction; |
c19d1205 ZW |
343 | int size; |
344 | int size_req; | |
345 | int cond; | |
037e8744 JB |
346 | /* "uncond_value" is set to the value in place of the conditional field in |
347 | unconditional versions of the instruction, or -1 if nothing is | |
348 | appropriate. */ | |
349 | int uncond_value; | |
5287ad62 | 350 | struct neon_type vectype; |
88714cb8 DG |
351 | /* This does not indicate an actual NEON instruction, only that |
352 | the mnemonic accepts neon-style type suffixes. */ | |
353 | int is_neon; | |
0110f2b8 PB |
354 | /* Set to the opcode if the instruction needs relaxation. |
355 | Zero if the instruction is not relaxed. */ | |
356 | unsigned long relax; | |
b99bd4ef NC |
357 | struct |
358 | { | |
359 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
360 | expressionS exp; |
361 | int pc_rel; | |
b99bd4ef | 362 | } reloc; |
b99bd4ef | 363 | |
e07e6e58 NC |
364 | enum it_instruction_type it_insn_type; |
365 | ||
c19d1205 ZW |
366 | struct |
367 | { | |
368 | unsigned reg; | |
ca3f61f7 | 369 | signed int imm; |
dcbf9037 | 370 | struct neon_type_el vectype; |
ca3f61f7 NC |
371 | unsigned present : 1; /* Operand present. */ |
372 | unsigned isreg : 1; /* Operand was a register. */ | |
373 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
5287ad62 JB |
374 | unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ |
375 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ | |
c96612cc | 376 | unsigned immisfloat : 1; /* Immediate was parsed as a float. */ |
5287ad62 JB |
377 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV |
378 | instructions. This allows us to disambiguate ARM <-> vector insns. */ | |
379 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ | |
037e8744 | 380 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
5287ad62 | 381 | unsigned isquad : 1; /* Operand is Neon quad-precision register. */ |
037e8744 | 382 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
ca3f61f7 NC |
383 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
384 | unsigned writeback : 1; /* Operand has trailing ! */ | |
385 | unsigned preind : 1; /* Preindexed address. */ | |
386 | unsigned postind : 1; /* Postindexed address. */ | |
387 | unsigned negative : 1; /* Index register was negated. */ | |
388 | unsigned shifted : 1; /* Shift applied to operation. */ | |
389 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
c19d1205 | 390 | } operands[6]; |
b99bd4ef NC |
391 | }; |
392 | ||
c19d1205 | 393 | static struct arm_it inst; |
b99bd4ef NC |
394 | |
395 | #define NUM_FLOAT_VALS 8 | |
396 | ||
05d2d07e | 397 | const char * fp_const[] = |
b99bd4ef NC |
398 | { |
399 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
400 | }; | |
401 | ||
c19d1205 | 402 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
403 | #define MAX_LITTLENUMS 6 |
404 | ||
405 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
406 | ||
407 | #define FAIL (-1) | |
408 | #define SUCCESS (0) | |
409 | ||
410 | #define SUFF_S 1 | |
411 | #define SUFF_D 2 | |
412 | #define SUFF_E 3 | |
413 | #define SUFF_P 4 | |
414 | ||
c19d1205 ZW |
415 | #define CP_T_X 0x00008000 |
416 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 417 | |
c19d1205 ZW |
418 | #define CONDS_BIT 0x00100000 |
419 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
420 | |
421 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
422 | ||
423 | struct asm_cond | |
424 | { | |
d3ce72d0 | 425 | const char * template_name; |
c921be7d | 426 | unsigned long value; |
b99bd4ef NC |
427 | }; |
428 | ||
c19d1205 | 429 | #define COND_ALWAYS 0xE |
b99bd4ef | 430 | |
b99bd4ef NC |
431 | struct asm_psr |
432 | { | |
d3ce72d0 | 433 | const char * template_name; |
c921be7d | 434 | unsigned long field; |
b99bd4ef NC |
435 | }; |
436 | ||
62b3e311 PB |
437 | struct asm_barrier_opt |
438 | { | |
d3ce72d0 | 439 | const char * template_name; |
c921be7d | 440 | unsigned long value; |
62b3e311 PB |
441 | }; |
442 | ||
2d2255b5 | 443 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
444 | #define SPSR_BIT (1 << 22) |
445 | ||
c19d1205 ZW |
446 | /* The individual PSR flag bits. */ |
447 | #define PSR_c (1 << 16) | |
448 | #define PSR_x (1 << 17) | |
449 | #define PSR_s (1 << 18) | |
450 | #define PSR_f (1 << 19) | |
b99bd4ef | 451 | |
c19d1205 | 452 | struct reloc_entry |
bfae80f2 | 453 | { |
c921be7d NC |
454 | char * name; |
455 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
456 | }; |
457 | ||
5287ad62 | 458 | enum vfp_reg_pos |
bfae80f2 | 459 | { |
5287ad62 JB |
460 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
461 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn | |
bfae80f2 RE |
462 | }; |
463 | ||
464 | enum vfp_ldstm_type | |
465 | { | |
466 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
467 | }; | |
468 | ||
dcbf9037 JB |
469 | /* Bits for DEFINED field in neon_typed_alias. */ |
470 | #define NTA_HASTYPE 1 | |
471 | #define NTA_HASINDEX 2 | |
472 | ||
473 | struct neon_typed_alias | |
474 | { | |
c921be7d NC |
475 | unsigned char defined; |
476 | unsigned char index; | |
477 | struct neon_type_el eltype; | |
dcbf9037 JB |
478 | }; |
479 | ||
c19d1205 ZW |
480 | /* ARM register categories. This includes coprocessor numbers and various |
481 | architecture extensions' registers. */ | |
482 | enum arm_reg_type | |
bfae80f2 | 483 | { |
c19d1205 ZW |
484 | REG_TYPE_RN, |
485 | REG_TYPE_CP, | |
486 | REG_TYPE_CN, | |
487 | REG_TYPE_FN, | |
488 | REG_TYPE_VFS, | |
489 | REG_TYPE_VFD, | |
5287ad62 | 490 | REG_TYPE_NQ, |
037e8744 | 491 | REG_TYPE_VFSD, |
5287ad62 | 492 | REG_TYPE_NDQ, |
037e8744 | 493 | REG_TYPE_NSDQ, |
c19d1205 ZW |
494 | REG_TYPE_VFC, |
495 | REG_TYPE_MVF, | |
496 | REG_TYPE_MVD, | |
497 | REG_TYPE_MVFX, | |
498 | REG_TYPE_MVDX, | |
499 | REG_TYPE_MVAX, | |
500 | REG_TYPE_DSPSC, | |
501 | REG_TYPE_MMXWR, | |
502 | REG_TYPE_MMXWC, | |
503 | REG_TYPE_MMXWCG, | |
504 | REG_TYPE_XSCALE, | |
bfae80f2 RE |
505 | }; |
506 | ||
dcbf9037 JB |
507 | /* Structure for a hash table entry for a register. |
508 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra | |
509 | information which states whether a vector type or index is specified (for a | |
510 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ | |
6c43fab6 RE |
511 | struct reg_entry |
512 | { | |
c921be7d NC |
513 | const char * name; |
514 | unsigned char number; | |
515 | unsigned char type; | |
516 | unsigned char builtin; | |
517 | struct neon_typed_alias * neon; | |
6c43fab6 RE |
518 | }; |
519 | ||
c19d1205 | 520 | /* Diagnostics used when we don't get a register of the expected type. */ |
c921be7d | 521 | const char * const reg_expected_msgs[] = |
c19d1205 ZW |
522 | { |
523 | N_("ARM register expected"), | |
524 | N_("bad or missing co-processor number"), | |
525 | N_("co-processor register expected"), | |
526 | N_("FPA register expected"), | |
527 | N_("VFP single precision register expected"), | |
5287ad62 JB |
528 | N_("VFP/Neon double precision register expected"), |
529 | N_("Neon quad precision register expected"), | |
037e8744 | 530 | N_("VFP single or double precision register expected"), |
5287ad62 | 531 | N_("Neon double or quad precision register expected"), |
037e8744 | 532 | N_("VFP single, double or Neon quad precision register expected"), |
c19d1205 ZW |
533 | N_("VFP system register expected"), |
534 | N_("Maverick MVF register expected"), | |
535 | N_("Maverick MVD register expected"), | |
536 | N_("Maverick MVFX register expected"), | |
537 | N_("Maverick MVDX register expected"), | |
538 | N_("Maverick MVAX register expected"), | |
539 | N_("Maverick DSPSC register expected"), | |
540 | N_("iWMMXt data register expected"), | |
541 | N_("iWMMXt control register expected"), | |
542 | N_("iWMMXt scalar register expected"), | |
543 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
544 | }; |
545 | ||
c19d1205 ZW |
546 | /* Some well known registers that we refer to directly elsewhere. */ |
547 | #define REG_SP 13 | |
548 | #define REG_LR 14 | |
549 | #define REG_PC 15 | |
404ff6b5 | 550 | |
b99bd4ef NC |
551 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
552 | take 2: */ | |
c19d1205 | 553 | #define INSN_SIZE 4 |
b99bd4ef NC |
554 | |
555 | struct asm_opcode | |
556 | { | |
557 | /* Basic string to match. */ | |
d3ce72d0 | 558 | const char * template_name; |
c19d1205 ZW |
559 | |
560 | /* Parameters to instruction. */ | |
5be8be5d | 561 | unsigned int operands[8]; |
c19d1205 ZW |
562 | |
563 | /* Conditional tag - see opcode_lookup. */ | |
564 | unsigned int tag : 4; | |
b99bd4ef NC |
565 | |
566 | /* Basic instruction code. */ | |
c19d1205 | 567 | unsigned int avalue : 28; |
b99bd4ef | 568 | |
c19d1205 ZW |
569 | /* Thumb-format instruction code. */ |
570 | unsigned int tvalue; | |
b99bd4ef | 571 | |
90e4755a | 572 | /* Which architecture variant provides this instruction. */ |
c921be7d NC |
573 | const arm_feature_set * avariant; |
574 | const arm_feature_set * tvariant; | |
c19d1205 ZW |
575 | |
576 | /* Function to call to encode instruction in ARM format. */ | |
577 | void (* aencode) (void); | |
b99bd4ef | 578 | |
c19d1205 ZW |
579 | /* Function to call to encode instruction in Thumb format. */ |
580 | void (* tencode) (void); | |
b99bd4ef NC |
581 | }; |
582 | ||
a737bd4d NC |
583 | /* Defines for various bits that we will want to toggle. */ |
584 | #define INST_IMMEDIATE 0x02000000 | |
585 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 586 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
587 | #define SHIFT_BY_REG 0x00000010 |
588 | #define PRE_INDEX 0x01000000 | |
589 | #define INDEX_UP 0x00800000 | |
590 | #define WRITE_BACK 0x00200000 | |
591 | #define LDM_TYPE_2_OR_3 0x00400000 | |
a028a6f5 | 592 | #define CPSI_MMOD 0x00020000 |
90e4755a | 593 | |
a737bd4d NC |
594 | #define LITERAL_MASK 0xf000f000 |
595 | #define OPCODE_MASK 0xfe1fffff | |
596 | #define V4_STR_BIT 0x00000020 | |
90e4755a | 597 | |
efd81785 PB |
598 | #define T2_SUBS_PC_LR 0xf3de8f00 |
599 | ||
a737bd4d | 600 | #define DATA_OP_SHIFT 21 |
90e4755a | 601 | |
ef8d22e6 PB |
602 | #define T2_OPCODE_MASK 0xfe1fffff |
603 | #define T2_DATA_OP_SHIFT 21 | |
604 | ||
a737bd4d NC |
605 | /* Codes to distinguish the arithmetic instructions. */ |
606 | #define OPCODE_AND 0 | |
607 | #define OPCODE_EOR 1 | |
608 | #define OPCODE_SUB 2 | |
609 | #define OPCODE_RSB 3 | |
610 | #define OPCODE_ADD 4 | |
611 | #define OPCODE_ADC 5 | |
612 | #define OPCODE_SBC 6 | |
613 | #define OPCODE_RSC 7 | |
614 | #define OPCODE_TST 8 | |
615 | #define OPCODE_TEQ 9 | |
616 | #define OPCODE_CMP 10 | |
617 | #define OPCODE_CMN 11 | |
618 | #define OPCODE_ORR 12 | |
619 | #define OPCODE_MOV 13 | |
620 | #define OPCODE_BIC 14 | |
621 | #define OPCODE_MVN 15 | |
90e4755a | 622 | |
ef8d22e6 PB |
623 | #define T2_OPCODE_AND 0 |
624 | #define T2_OPCODE_BIC 1 | |
625 | #define T2_OPCODE_ORR 2 | |
626 | #define T2_OPCODE_ORN 3 | |
627 | #define T2_OPCODE_EOR 4 | |
628 | #define T2_OPCODE_ADD 8 | |
629 | #define T2_OPCODE_ADC 10 | |
630 | #define T2_OPCODE_SBC 11 | |
631 | #define T2_OPCODE_SUB 13 | |
632 | #define T2_OPCODE_RSB 14 | |
633 | ||
a737bd4d NC |
634 | #define T_OPCODE_MUL 0x4340 |
635 | #define T_OPCODE_TST 0x4200 | |
636 | #define T_OPCODE_CMN 0x42c0 | |
637 | #define T_OPCODE_NEG 0x4240 | |
638 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 639 | |
a737bd4d NC |
640 | #define T_OPCODE_ADD_R3 0x1800 |
641 | #define T_OPCODE_SUB_R3 0x1a00 | |
642 | #define T_OPCODE_ADD_HI 0x4400 | |
643 | #define T_OPCODE_ADD_ST 0xb000 | |
644 | #define T_OPCODE_SUB_ST 0xb080 | |
645 | #define T_OPCODE_ADD_SP 0xa800 | |
646 | #define T_OPCODE_ADD_PC 0xa000 | |
647 | #define T_OPCODE_ADD_I8 0x3000 | |
648 | #define T_OPCODE_SUB_I8 0x3800 | |
649 | #define T_OPCODE_ADD_I3 0x1c00 | |
650 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 651 | |
a737bd4d NC |
652 | #define T_OPCODE_ASR_R 0x4100 |
653 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
654 | #define T_OPCODE_LSR_R 0x40c0 |
655 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
656 | #define T_OPCODE_ASR_I 0x1000 |
657 | #define T_OPCODE_LSL_I 0x0000 | |
658 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 659 | |
a737bd4d NC |
660 | #define T_OPCODE_MOV_I8 0x2000 |
661 | #define T_OPCODE_CMP_I8 0x2800 | |
662 | #define T_OPCODE_CMP_LR 0x4280 | |
663 | #define T_OPCODE_MOV_HR 0x4600 | |
664 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 665 | |
a737bd4d NC |
666 | #define T_OPCODE_LDR_PC 0x4800 |
667 | #define T_OPCODE_LDR_SP 0x9800 | |
668 | #define T_OPCODE_STR_SP 0x9000 | |
669 | #define T_OPCODE_LDR_IW 0x6800 | |
670 | #define T_OPCODE_STR_IW 0x6000 | |
671 | #define T_OPCODE_LDR_IH 0x8800 | |
672 | #define T_OPCODE_STR_IH 0x8000 | |
673 | #define T_OPCODE_LDR_IB 0x7800 | |
674 | #define T_OPCODE_STR_IB 0x7000 | |
675 | #define T_OPCODE_LDR_RW 0x5800 | |
676 | #define T_OPCODE_STR_RW 0x5000 | |
677 | #define T_OPCODE_LDR_RH 0x5a00 | |
678 | #define T_OPCODE_STR_RH 0x5200 | |
679 | #define T_OPCODE_LDR_RB 0x5c00 | |
680 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 681 | |
a737bd4d NC |
682 | #define T_OPCODE_PUSH 0xb400 |
683 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 684 | |
2fc8bdac | 685 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 686 | |
a737bd4d | 687 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 688 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 689 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 690 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 ZW |
691 | |
692 | #define BAD_ARGS _("bad arguments to instruction") | |
fdfde340 | 693 | #define BAD_SP _("r13 not allowed here") |
c19d1205 ZW |
694 | #define BAD_PC _("r15 not allowed here") |
695 | #define BAD_COND _("instruction cannot be conditional") | |
696 | #define BAD_OVERLAP _("registers may not be the same") | |
697 | #define BAD_HIREG _("lo register required") | |
698 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
01cfc07f | 699 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); |
dfa9f0d5 PB |
700 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
701 | #define BAD_NOT_IT _("instruction not allowed in IT block") | |
037e8744 | 702 | #define BAD_FPU _("selected FPU does not support instruction") |
e07e6e58 NC |
703 | #define BAD_OUT_IT _("thumb conditional instruction should be in IT block") |
704 | #define BAD_IT_COND _("incorrect condition in IT block") | |
705 | #define BAD_IT_IT _("IT falling in the range of a previous IT block") | |
921e5f0a | 706 | #define MISSING_FNSTART _("missing .fnstart before unwinding directive") |
5be8be5d DG |
707 | #define BAD_PC_ADDRESSING \ |
708 | _("cannot use register index with PC-relative addressing") | |
709 | #define BAD_PC_WRITEBACK \ | |
710 | _("cannot use writeback with PC-relative addressing") | |
c19d1205 | 711 | |
c921be7d NC |
712 | static struct hash_control * arm_ops_hsh; |
713 | static struct hash_control * arm_cond_hsh; | |
714 | static struct hash_control * arm_shift_hsh; | |
715 | static struct hash_control * arm_psr_hsh; | |
716 | static struct hash_control * arm_v7m_psr_hsh; | |
717 | static struct hash_control * arm_reg_hsh; | |
718 | static struct hash_control * arm_reloc_hsh; | |
719 | static struct hash_control * arm_barrier_opt_hsh; | |
b99bd4ef | 720 | |
b99bd4ef NC |
721 | /* Stuff needed to resolve the label ambiguity |
722 | As: | |
723 | ... | |
724 | label: <insn> | |
725 | may differ from: | |
726 | ... | |
727 | label: | |
5f4273c7 | 728 | <insn> */ |
b99bd4ef NC |
729 | |
730 | symbolS * last_label_seen; | |
b34976b6 | 731 | static int label_is_thumb_function_name = FALSE; |
e07e6e58 | 732 | |
3d0c9500 NC |
733 | /* Literal pool structure. Held on a per-section |
734 | and per-sub-section basis. */ | |
a737bd4d | 735 | |
c19d1205 | 736 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 737 | typedef struct literal_pool |
b99bd4ef | 738 | { |
c921be7d NC |
739 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
740 | unsigned int next_free_entry; | |
741 | unsigned int id; | |
742 | symbolS * symbol; | |
743 | segT section; | |
744 | subsegT sub_section; | |
745 | struct literal_pool * next; | |
3d0c9500 | 746 | } literal_pool; |
b99bd4ef | 747 | |
3d0c9500 NC |
748 | /* Pointer to a linked list of literal pools. */ |
749 | literal_pool * list_of_pools = NULL; | |
e27ec89e | 750 | |
e07e6e58 NC |
751 | #ifdef OBJ_ELF |
752 | # define now_it seg_info (now_seg)->tc_segment_info_data.current_it | |
753 | #else | |
754 | static struct current_it now_it; | |
755 | #endif | |
756 | ||
757 | static inline int | |
758 | now_it_compatible (int cond) | |
759 | { | |
760 | return (cond & ~1) == (now_it.cc & ~1); | |
761 | } | |
762 | ||
763 | static inline int | |
764 | conditional_insn (void) | |
765 | { | |
766 | return inst.cond != COND_ALWAYS; | |
767 | } | |
768 | ||
769 | static int in_it_block (void); | |
770 | ||
771 | static int handle_it_state (void); | |
772 | ||
773 | static void force_automatic_it_block_close (void); | |
774 | ||
c921be7d NC |
775 | static void it_fsm_post_encode (void); |
776 | ||
e07e6e58 NC |
777 | #define set_it_insn_type(type) \ |
778 | do \ | |
779 | { \ | |
780 | inst.it_insn_type = type; \ | |
781 | if (handle_it_state () == FAIL) \ | |
782 | return; \ | |
783 | } \ | |
784 | while (0) | |
785 | ||
c921be7d NC |
786 | #define set_it_insn_type_nonvoid(type, failret) \ |
787 | do \ | |
788 | { \ | |
789 | inst.it_insn_type = type; \ | |
790 | if (handle_it_state () == FAIL) \ | |
791 | return failret; \ | |
792 | } \ | |
793 | while(0) | |
794 | ||
e07e6e58 NC |
795 | #define set_it_insn_type_last() \ |
796 | do \ | |
797 | { \ | |
798 | if (inst.cond == COND_ALWAYS) \ | |
799 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \ | |
800 | else \ | |
801 | set_it_insn_type (INSIDE_IT_LAST_INSN); \ | |
802 | } \ | |
803 | while (0) | |
804 | ||
c19d1205 | 805 | /* Pure syntax. */ |
b99bd4ef | 806 | |
c19d1205 ZW |
807 | /* This array holds the chars that always start a comment. If the |
808 | pre-processor is disabled, these aren't very useful. */ | |
809 | const char comment_chars[] = "@"; | |
3d0c9500 | 810 | |
c19d1205 ZW |
811 | /* This array holds the chars that only start a comment at the beginning of |
812 | a line. If the line seems to have the form '# 123 filename' | |
813 | .line and .file directives will appear in the pre-processed output. */ | |
814 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
815 | first line of the input file. This is because the compiler outputs | |
816 | #NO_APP at the beginning of its output. */ | |
817 | /* Also note that comments like this one will always work. */ | |
818 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 819 | |
c19d1205 | 820 | const char line_separator_chars[] = ";"; |
b99bd4ef | 821 | |
c19d1205 ZW |
822 | /* Chars that can be used to separate mant |
823 | from exp in floating point numbers. */ | |
824 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 825 | |
c19d1205 ZW |
826 | /* Chars that mean this number is a floating point constant. */ |
827 | /* As in 0f12.456 */ | |
828 | /* or 0d1.2345e12 */ | |
b99bd4ef | 829 | |
c19d1205 | 830 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 831 | |
c19d1205 ZW |
832 | /* Prefix characters that indicate the start of an immediate |
833 | value. */ | |
834 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 835 | |
c19d1205 ZW |
836 | /* Separator character handling. */ |
837 | ||
838 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
839 | ||
840 | static inline int | |
841 | skip_past_char (char ** str, char c) | |
842 | { | |
843 | if (**str == c) | |
844 | { | |
845 | (*str)++; | |
846 | return SUCCESS; | |
3d0c9500 | 847 | } |
c19d1205 ZW |
848 | else |
849 | return FAIL; | |
850 | } | |
c921be7d | 851 | |
c19d1205 | 852 | #define skip_past_comma(str) skip_past_char (str, ',') |
3d0c9500 | 853 | |
c19d1205 ZW |
854 | /* Arithmetic expressions (possibly involving symbols). */ |
855 | ||
856 | /* Return TRUE if anything in the expression is a bignum. */ | |
857 | ||
858 | static int | |
859 | walk_no_bignums (symbolS * sp) | |
860 | { | |
861 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
862 | return 1; | |
863 | ||
864 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 865 | { |
c19d1205 ZW |
866 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
867 | || (symbol_get_value_expression (sp)->X_op_symbol | |
868 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
869 | } |
870 | ||
c19d1205 | 871 | return 0; |
3d0c9500 NC |
872 | } |
873 | ||
c19d1205 ZW |
874 | static int in_my_get_expression = 0; |
875 | ||
876 | /* Third argument to my_get_expression. */ | |
877 | #define GE_NO_PREFIX 0 | |
878 | #define GE_IMM_PREFIX 1 | |
879 | #define GE_OPT_PREFIX 2 | |
5287ad62 JB |
880 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
881 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ | |
882 | #define GE_OPT_PREFIX_BIG 3 | |
a737bd4d | 883 | |
b99bd4ef | 884 | static int |
c19d1205 | 885 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 886 | { |
c19d1205 ZW |
887 | char * save_in; |
888 | segT seg; | |
b99bd4ef | 889 | |
c19d1205 ZW |
890 | /* In unified syntax, all prefixes are optional. */ |
891 | if (unified_syntax) | |
5287ad62 JB |
892 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
893 | : GE_OPT_PREFIX; | |
b99bd4ef | 894 | |
c19d1205 | 895 | switch (prefix_mode) |
b99bd4ef | 896 | { |
c19d1205 ZW |
897 | case GE_NO_PREFIX: break; |
898 | case GE_IMM_PREFIX: | |
899 | if (!is_immediate_prefix (**str)) | |
900 | { | |
901 | inst.error = _("immediate expression requires a # prefix"); | |
902 | return FAIL; | |
903 | } | |
904 | (*str)++; | |
905 | break; | |
906 | case GE_OPT_PREFIX: | |
5287ad62 | 907 | case GE_OPT_PREFIX_BIG: |
c19d1205 ZW |
908 | if (is_immediate_prefix (**str)) |
909 | (*str)++; | |
910 | break; | |
911 | default: abort (); | |
912 | } | |
b99bd4ef | 913 | |
c19d1205 | 914 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 915 | |
c19d1205 ZW |
916 | save_in = input_line_pointer; |
917 | input_line_pointer = *str; | |
918 | in_my_get_expression = 1; | |
919 | seg = expression (ep); | |
920 | in_my_get_expression = 0; | |
921 | ||
f86adc07 | 922 | if (ep->X_op == O_illegal || ep->X_op == O_absent) |
b99bd4ef | 923 | { |
f86adc07 | 924 | /* We found a bad or missing expression in md_operand(). */ |
c19d1205 ZW |
925 | *str = input_line_pointer; |
926 | input_line_pointer = save_in; | |
927 | if (inst.error == NULL) | |
f86adc07 NS |
928 | inst.error = (ep->X_op == O_absent |
929 | ? _("missing expression") :_("bad expression")); | |
c19d1205 ZW |
930 | return 1; |
931 | } | |
b99bd4ef | 932 | |
c19d1205 ZW |
933 | #ifdef OBJ_AOUT |
934 | if (seg != absolute_section | |
935 | && seg != text_section | |
936 | && seg != data_section | |
937 | && seg != bss_section | |
938 | && seg != undefined_section) | |
939 | { | |
940 | inst.error = _("bad segment"); | |
941 | *str = input_line_pointer; | |
942 | input_line_pointer = save_in; | |
943 | return 1; | |
b99bd4ef | 944 | } |
87975d2a AM |
945 | #else |
946 | (void) seg; | |
c19d1205 | 947 | #endif |
b99bd4ef | 948 | |
c19d1205 ZW |
949 | /* Get rid of any bignums now, so that we don't generate an error for which |
950 | we can't establish a line number later on. Big numbers are never valid | |
951 | in instructions, which is where this routine is always called. */ | |
5287ad62 JB |
952 | if (prefix_mode != GE_OPT_PREFIX_BIG |
953 | && (ep->X_op == O_big | |
954 | || (ep->X_add_symbol | |
955 | && (walk_no_bignums (ep->X_add_symbol) | |
956 | || (ep->X_op_symbol | |
957 | && walk_no_bignums (ep->X_op_symbol)))))) | |
c19d1205 ZW |
958 | { |
959 | inst.error = _("invalid constant"); | |
960 | *str = input_line_pointer; | |
961 | input_line_pointer = save_in; | |
962 | return 1; | |
963 | } | |
b99bd4ef | 964 | |
c19d1205 ZW |
965 | *str = input_line_pointer; |
966 | input_line_pointer = save_in; | |
967 | return 0; | |
b99bd4ef NC |
968 | } |
969 | ||
c19d1205 ZW |
970 | /* Turn a string in input_line_pointer into a floating point constant |
971 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
972 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
973 | returned, or NULL on OK. | |
b99bd4ef | 974 | |
c19d1205 ZW |
975 | Note that fp constants aren't represent in the normal way on the ARM. |
976 | In big endian mode, things are as expected. However, in little endian | |
977 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
978 | within the words. For example, (double) 1.1 in big endian mode is | |
979 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
980 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 981 | |
c19d1205 | 982 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 983 | |
c19d1205 ZW |
984 | char * |
985 | md_atof (int type, char * litP, int * sizeP) | |
986 | { | |
987 | int prec; | |
988 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
989 | char *t; | |
990 | int i; | |
b99bd4ef | 991 | |
c19d1205 ZW |
992 | switch (type) |
993 | { | |
994 | case 'f': | |
995 | case 'F': | |
996 | case 's': | |
997 | case 'S': | |
998 | prec = 2; | |
999 | break; | |
b99bd4ef | 1000 | |
c19d1205 ZW |
1001 | case 'd': |
1002 | case 'D': | |
1003 | case 'r': | |
1004 | case 'R': | |
1005 | prec = 4; | |
1006 | break; | |
b99bd4ef | 1007 | |
c19d1205 ZW |
1008 | case 'x': |
1009 | case 'X': | |
499ac353 | 1010 | prec = 5; |
c19d1205 | 1011 | break; |
b99bd4ef | 1012 | |
c19d1205 ZW |
1013 | case 'p': |
1014 | case 'P': | |
499ac353 | 1015 | prec = 5; |
c19d1205 | 1016 | break; |
a737bd4d | 1017 | |
c19d1205 ZW |
1018 | default: |
1019 | *sizeP = 0; | |
499ac353 | 1020 | return _("Unrecognized or unsupported floating point constant"); |
c19d1205 | 1021 | } |
b99bd4ef | 1022 | |
c19d1205 ZW |
1023 | t = atof_ieee (input_line_pointer, type, words); |
1024 | if (t) | |
1025 | input_line_pointer = t; | |
499ac353 | 1026 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
b99bd4ef | 1027 | |
c19d1205 ZW |
1028 | if (target_big_endian) |
1029 | { | |
1030 | for (i = 0; i < prec; i++) | |
1031 | { | |
499ac353 NC |
1032 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1033 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1034 | } |
1035 | } | |
1036 | else | |
1037 | { | |
e74cfd16 | 1038 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
1039 | for (i = prec - 1; i >= 0; i--) |
1040 | { | |
499ac353 NC |
1041 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1042 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1043 | } |
1044 | else | |
1045 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
1046 | For an 8 byte float the order is 1 0 3 2. */ | |
1047 | for (i = 0; i < prec; i += 2) | |
1048 | { | |
499ac353 NC |
1049 | md_number_to_chars (litP, (valueT) words[i + 1], |
1050 | sizeof (LITTLENUM_TYPE)); | |
1051 | md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), | |
1052 | (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1053 | litP += 2 * sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1054 | } |
1055 | } | |
b99bd4ef | 1056 | |
499ac353 | 1057 | return NULL; |
c19d1205 | 1058 | } |
b99bd4ef | 1059 | |
c19d1205 ZW |
1060 | /* We handle all bad expressions here, so that we can report the faulty |
1061 | instruction in the error message. */ | |
1062 | void | |
91d6fa6a | 1063 | md_operand (expressionS * exp) |
c19d1205 ZW |
1064 | { |
1065 | if (in_my_get_expression) | |
91d6fa6a | 1066 | exp->X_op = O_illegal; |
b99bd4ef NC |
1067 | } |
1068 | ||
c19d1205 | 1069 | /* Immediate values. */ |
b99bd4ef | 1070 | |
c19d1205 ZW |
1071 | /* Generic immediate-value read function for use in directives. |
1072 | Accepts anything that 'expression' can fold to a constant. | |
1073 | *val receives the number. */ | |
1074 | #ifdef OBJ_ELF | |
1075 | static int | |
1076 | immediate_for_directive (int *val) | |
b99bd4ef | 1077 | { |
c19d1205 ZW |
1078 | expressionS exp; |
1079 | exp.X_op = O_illegal; | |
b99bd4ef | 1080 | |
c19d1205 ZW |
1081 | if (is_immediate_prefix (*input_line_pointer)) |
1082 | { | |
1083 | input_line_pointer++; | |
1084 | expression (&exp); | |
1085 | } | |
b99bd4ef | 1086 | |
c19d1205 ZW |
1087 | if (exp.X_op != O_constant) |
1088 | { | |
1089 | as_bad (_("expected #constant")); | |
1090 | ignore_rest_of_line (); | |
1091 | return FAIL; | |
1092 | } | |
1093 | *val = exp.X_add_number; | |
1094 | return SUCCESS; | |
b99bd4ef | 1095 | } |
c19d1205 | 1096 | #endif |
b99bd4ef | 1097 | |
c19d1205 | 1098 | /* Register parsing. */ |
b99bd4ef | 1099 | |
c19d1205 ZW |
1100 | /* Generic register parser. CCP points to what should be the |
1101 | beginning of a register name. If it is indeed a valid register | |
1102 | name, advance CCP over it and return the reg_entry structure; | |
1103 | otherwise return NULL. Does not issue diagnostics. */ | |
1104 | ||
1105 | static struct reg_entry * | |
1106 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 1107 | { |
c19d1205 ZW |
1108 | char *start = *ccp; |
1109 | char *p; | |
1110 | struct reg_entry *reg; | |
b99bd4ef | 1111 | |
c19d1205 ZW |
1112 | #ifdef REGISTER_PREFIX |
1113 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 1114 | return NULL; |
c19d1205 ZW |
1115 | start++; |
1116 | #endif | |
1117 | #ifdef OPTIONAL_REGISTER_PREFIX | |
1118 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
1119 | start++; | |
1120 | #endif | |
b99bd4ef | 1121 | |
c19d1205 ZW |
1122 | p = start; |
1123 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
1124 | return NULL; | |
b99bd4ef | 1125 | |
c19d1205 ZW |
1126 | do |
1127 | p++; | |
1128 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
1129 | ||
1130 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
1131 | ||
1132 | if (!reg) | |
1133 | return NULL; | |
1134 | ||
1135 | *ccp = p; | |
1136 | return reg; | |
b99bd4ef NC |
1137 | } |
1138 | ||
1139 | static int | |
dcbf9037 JB |
1140 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
1141 | enum arm_reg_type type) | |
b99bd4ef | 1142 | { |
c19d1205 ZW |
1143 | /* Alternative syntaxes are accepted for a few register classes. */ |
1144 | switch (type) | |
1145 | { | |
1146 | case REG_TYPE_MVF: | |
1147 | case REG_TYPE_MVD: | |
1148 | case REG_TYPE_MVFX: | |
1149 | case REG_TYPE_MVDX: | |
1150 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 1151 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
1152 | return reg->number; |
1153 | break; | |
69b97547 | 1154 | |
c19d1205 ZW |
1155 | case REG_TYPE_CP: |
1156 | /* For backward compatibility, a bare number is valid here. */ | |
1157 | { | |
1158 | unsigned long processor = strtoul (start, ccp, 10); | |
1159 | if (*ccp != start && processor <= 15) | |
1160 | return processor; | |
1161 | } | |
6057a28f | 1162 | |
c19d1205 ZW |
1163 | case REG_TYPE_MMXWC: |
1164 | /* WC includes WCG. ??? I'm not sure this is true for all | |
1165 | instructions that take WC registers. */ | |
79134647 | 1166 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 1167 | return reg->number; |
6057a28f | 1168 | break; |
c19d1205 | 1169 | |
6057a28f | 1170 | default: |
c19d1205 | 1171 | break; |
6057a28f NC |
1172 | } |
1173 | ||
dcbf9037 JB |
1174 | return FAIL; |
1175 | } | |
1176 | ||
1177 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the | |
1178 | return value is the register number or FAIL. */ | |
1179 | ||
1180 | static int | |
1181 | arm_reg_parse (char **ccp, enum arm_reg_type type) | |
1182 | { | |
1183 | char *start = *ccp; | |
1184 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
1185 | int ret; | |
1186 | ||
1187 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1188 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) | |
1189 | return FAIL; | |
1190 | ||
1191 | if (reg && reg->type == type) | |
1192 | return reg->number; | |
1193 | ||
1194 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) | |
1195 | return ret; | |
1196 | ||
c19d1205 ZW |
1197 | *ccp = start; |
1198 | return FAIL; | |
1199 | } | |
69b97547 | 1200 | |
dcbf9037 JB |
1201 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
1202 | character. Does no verification at this stage that the type fits the opcode | |
1203 | properly. E.g., | |
1204 | ||
1205 | .i32.i32.s16 | |
1206 | .s32.f32 | |
1207 | .u16 | |
1208 | ||
1209 | Can all be legally parsed by this function. | |
1210 | ||
1211 | Fills in neon_type struct pointer with parsed information, and updates STR | |
1212 | to point after the parsed type specifier. Returns SUCCESS if this was a legal | |
1213 | type, FAIL if not. */ | |
1214 | ||
1215 | static int | |
1216 | parse_neon_type (struct neon_type *type, char **str) | |
1217 | { | |
1218 | char *ptr = *str; | |
1219 | ||
1220 | if (type) | |
1221 | type->elems = 0; | |
1222 | ||
1223 | while (type->elems < NEON_MAX_TYPE_ELS) | |
1224 | { | |
1225 | enum neon_el_type thistype = NT_untyped; | |
1226 | unsigned thissize = -1u; | |
1227 | ||
1228 | if (*ptr != '.') | |
1229 | break; | |
1230 | ||
1231 | ptr++; | |
1232 | ||
1233 | /* Just a size without an explicit type. */ | |
1234 | if (ISDIGIT (*ptr)) | |
1235 | goto parsesize; | |
1236 | ||
1237 | switch (TOLOWER (*ptr)) | |
1238 | { | |
1239 | case 'i': thistype = NT_integer; break; | |
1240 | case 'f': thistype = NT_float; break; | |
1241 | case 'p': thistype = NT_poly; break; | |
1242 | case 's': thistype = NT_signed; break; | |
1243 | case 'u': thistype = NT_unsigned; break; | |
037e8744 JB |
1244 | case 'd': |
1245 | thistype = NT_float; | |
1246 | thissize = 64; | |
1247 | ptr++; | |
1248 | goto done; | |
dcbf9037 JB |
1249 | default: |
1250 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); | |
1251 | return FAIL; | |
1252 | } | |
1253 | ||
1254 | ptr++; | |
1255 | ||
1256 | /* .f is an abbreviation for .f32. */ | |
1257 | if (thistype == NT_float && !ISDIGIT (*ptr)) | |
1258 | thissize = 32; | |
1259 | else | |
1260 | { | |
1261 | parsesize: | |
1262 | thissize = strtoul (ptr, &ptr, 10); | |
1263 | ||
1264 | if (thissize != 8 && thissize != 16 && thissize != 32 | |
1265 | && thissize != 64) | |
1266 | { | |
1267 | as_bad (_("bad size %d in type specifier"), thissize); | |
1268 | return FAIL; | |
1269 | } | |
1270 | } | |
1271 | ||
037e8744 | 1272 | done: |
dcbf9037 JB |
1273 | if (type) |
1274 | { | |
1275 | type->el[type->elems].type = thistype; | |
1276 | type->el[type->elems].size = thissize; | |
1277 | type->elems++; | |
1278 | } | |
1279 | } | |
1280 | ||
1281 | /* Empty/missing type is not a successful parse. */ | |
1282 | if (type->elems == 0) | |
1283 | return FAIL; | |
1284 | ||
1285 | *str = ptr; | |
1286 | ||
1287 | return SUCCESS; | |
1288 | } | |
1289 | ||
1290 | /* Errors may be set multiple times during parsing or bit encoding | |
1291 | (particularly in the Neon bits), but usually the earliest error which is set | |
1292 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
1293 | errors by calling this function. */ | |
1294 | ||
1295 | static void | |
1296 | first_error (const char *err) | |
1297 | { | |
1298 | if (!inst.error) | |
1299 | inst.error = err; | |
1300 | } | |
1301 | ||
1302 | /* Parse a single type, e.g. ".s32", leading period included. */ | |
1303 | static int | |
1304 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) | |
1305 | { | |
1306 | char *str = *ccp; | |
1307 | struct neon_type optype; | |
1308 | ||
1309 | if (*str == '.') | |
1310 | { | |
1311 | if (parse_neon_type (&optype, &str) == SUCCESS) | |
1312 | { | |
1313 | if (optype.elems == 1) | |
1314 | *vectype = optype.el[0]; | |
1315 | else | |
1316 | { | |
1317 | first_error (_("only one type should be specified for operand")); | |
1318 | return FAIL; | |
1319 | } | |
1320 | } | |
1321 | else | |
1322 | { | |
1323 | first_error (_("vector type expected")); | |
1324 | return FAIL; | |
1325 | } | |
1326 | } | |
1327 | else | |
1328 | return FAIL; | |
5f4273c7 | 1329 | |
dcbf9037 | 1330 | *ccp = str; |
5f4273c7 | 1331 | |
dcbf9037 JB |
1332 | return SUCCESS; |
1333 | } | |
1334 | ||
1335 | /* Special meanings for indices (which have a range of 0-7), which will fit into | |
1336 | a 4-bit integer. */ | |
1337 | ||
1338 | #define NEON_ALL_LANES 15 | |
1339 | #define NEON_INTERLEAVE_LANES 14 | |
1340 | ||
1341 | /* Parse either a register or a scalar, with an optional type. Return the | |
1342 | register number, and optionally fill in the actual type of the register | |
1343 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and | |
1344 | type/index information in *TYPEINFO. */ | |
1345 | ||
1346 | static int | |
1347 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, | |
1348 | enum arm_reg_type *rtype, | |
1349 | struct neon_typed_alias *typeinfo) | |
1350 | { | |
1351 | char *str = *ccp; | |
1352 | struct reg_entry *reg = arm_reg_parse_multi (&str); | |
1353 | struct neon_typed_alias atype; | |
1354 | struct neon_type_el parsetype; | |
1355 | ||
1356 | atype.defined = 0; | |
1357 | atype.index = -1; | |
1358 | atype.eltype.type = NT_invtype; | |
1359 | atype.eltype.size = -1; | |
1360 | ||
1361 | /* Try alternate syntax for some types of register. Note these are mutually | |
1362 | exclusive with the Neon syntax extensions. */ | |
1363 | if (reg == NULL) | |
1364 | { | |
1365 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); | |
1366 | if (altreg != FAIL) | |
1367 | *ccp = str; | |
1368 | if (typeinfo) | |
1369 | *typeinfo = atype; | |
1370 | return altreg; | |
1371 | } | |
1372 | ||
037e8744 JB |
1373 | /* Undo polymorphism when a set of register types may be accepted. */ |
1374 | if ((type == REG_TYPE_NDQ | |
1375 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) | |
1376 | || (type == REG_TYPE_VFSD | |
1377 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) | |
1378 | || (type == REG_TYPE_NSDQ | |
1379 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD | |
f512f76f NC |
1380 | || reg->type == REG_TYPE_NQ)) |
1381 | || (type == REG_TYPE_MMXWC | |
1382 | && (reg->type == REG_TYPE_MMXWCG))) | |
21d799b5 | 1383 | type = (enum arm_reg_type) reg->type; |
dcbf9037 JB |
1384 | |
1385 | if (type != reg->type) | |
1386 | return FAIL; | |
1387 | ||
1388 | if (reg->neon) | |
1389 | atype = *reg->neon; | |
5f4273c7 | 1390 | |
dcbf9037 JB |
1391 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) |
1392 | { | |
1393 | if ((atype.defined & NTA_HASTYPE) != 0) | |
1394 | { | |
1395 | first_error (_("can't redefine type for operand")); | |
1396 | return FAIL; | |
1397 | } | |
1398 | atype.defined |= NTA_HASTYPE; | |
1399 | atype.eltype = parsetype; | |
1400 | } | |
5f4273c7 | 1401 | |
dcbf9037 JB |
1402 | if (skip_past_char (&str, '[') == SUCCESS) |
1403 | { | |
1404 | if (type != REG_TYPE_VFD) | |
1405 | { | |
1406 | first_error (_("only D registers may be indexed")); | |
1407 | return FAIL; | |
1408 | } | |
5f4273c7 | 1409 | |
dcbf9037 JB |
1410 | if ((atype.defined & NTA_HASINDEX) != 0) |
1411 | { | |
1412 | first_error (_("can't change index for operand")); | |
1413 | return FAIL; | |
1414 | } | |
1415 | ||
1416 | atype.defined |= NTA_HASINDEX; | |
1417 | ||
1418 | if (skip_past_char (&str, ']') == SUCCESS) | |
1419 | atype.index = NEON_ALL_LANES; | |
1420 | else | |
1421 | { | |
1422 | expressionS exp; | |
1423 | ||
1424 | my_get_expression (&exp, &str, GE_NO_PREFIX); | |
1425 | ||
1426 | if (exp.X_op != O_constant) | |
1427 | { | |
1428 | first_error (_("constant expression required")); | |
1429 | return FAIL; | |
1430 | } | |
1431 | ||
1432 | if (skip_past_char (&str, ']') == FAIL) | |
1433 | return FAIL; | |
1434 | ||
1435 | atype.index = exp.X_add_number; | |
1436 | } | |
1437 | } | |
5f4273c7 | 1438 | |
dcbf9037 JB |
1439 | if (typeinfo) |
1440 | *typeinfo = atype; | |
5f4273c7 | 1441 | |
dcbf9037 JB |
1442 | if (rtype) |
1443 | *rtype = type; | |
5f4273c7 | 1444 | |
dcbf9037 | 1445 | *ccp = str; |
5f4273c7 | 1446 | |
dcbf9037 JB |
1447 | return reg->number; |
1448 | } | |
1449 | ||
1450 | /* Like arm_reg_parse, but allow allow the following extra features: | |
1451 | - If RTYPE is non-zero, return the (possibly restricted) type of the | |
1452 | register (e.g. Neon double or quad reg when either has been requested). | |
1453 | - If this is a Neon vector type with additional type information, fill | |
1454 | in the struct pointed to by VECTYPE (if non-NULL). | |
5f4273c7 | 1455 | This function will fault on encountering a scalar. */ |
dcbf9037 JB |
1456 | |
1457 | static int | |
1458 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, | |
1459 | enum arm_reg_type *rtype, struct neon_type_el *vectype) | |
1460 | { | |
1461 | struct neon_typed_alias atype; | |
1462 | char *str = *ccp; | |
1463 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); | |
1464 | ||
1465 | if (reg == FAIL) | |
1466 | return FAIL; | |
1467 | ||
1468 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1469 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1470 | { | |
1471 | first_error (_("register operand expected, but got scalar")); | |
1472 | return FAIL; | |
1473 | } | |
1474 | ||
1475 | if (vectype) | |
1476 | *vectype = atype.eltype; | |
1477 | ||
1478 | *ccp = str; | |
1479 | ||
1480 | return reg; | |
1481 | } | |
1482 | ||
1483 | #define NEON_SCALAR_REG(X) ((X) >> 4) | |
1484 | #define NEON_SCALAR_INDEX(X) ((X) & 15) | |
1485 | ||
5287ad62 JB |
1486 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
1487 | have enough information to be able to do a good job bounds-checking. So, we | |
1488 | just do easy checks here, and do further checks later. */ | |
1489 | ||
1490 | static int | |
dcbf9037 | 1491 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type) |
5287ad62 | 1492 | { |
dcbf9037 | 1493 | int reg; |
5287ad62 | 1494 | char *str = *ccp; |
dcbf9037 | 1495 | struct neon_typed_alias atype; |
5f4273c7 | 1496 | |
dcbf9037 | 1497 | reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); |
5f4273c7 | 1498 | |
dcbf9037 | 1499 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
5287ad62 | 1500 | return FAIL; |
5f4273c7 | 1501 | |
dcbf9037 | 1502 | if (atype.index == NEON_ALL_LANES) |
5287ad62 | 1503 | { |
dcbf9037 | 1504 | first_error (_("scalar must have an index")); |
5287ad62 JB |
1505 | return FAIL; |
1506 | } | |
dcbf9037 | 1507 | else if (atype.index >= 64 / elsize) |
5287ad62 | 1508 | { |
dcbf9037 | 1509 | first_error (_("scalar index out of range")); |
5287ad62 JB |
1510 | return FAIL; |
1511 | } | |
5f4273c7 | 1512 | |
dcbf9037 JB |
1513 | if (type) |
1514 | *type = atype.eltype; | |
5f4273c7 | 1515 | |
5287ad62 | 1516 | *ccp = str; |
5f4273c7 | 1517 | |
dcbf9037 | 1518 | return reg * 16 + atype.index; |
5287ad62 JB |
1519 | } |
1520 | ||
c19d1205 | 1521 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
e07e6e58 | 1522 | |
c19d1205 ZW |
1523 | static long |
1524 | parse_reg_list (char ** strp) | |
1525 | { | |
1526 | char * str = * strp; | |
1527 | long range = 0; | |
1528 | int another_range; | |
a737bd4d | 1529 | |
c19d1205 ZW |
1530 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
1531 | do | |
6057a28f | 1532 | { |
c19d1205 | 1533 | another_range = 0; |
a737bd4d | 1534 | |
c19d1205 ZW |
1535 | if (*str == '{') |
1536 | { | |
1537 | int in_range = 0; | |
1538 | int cur_reg = -1; | |
a737bd4d | 1539 | |
c19d1205 ZW |
1540 | str++; |
1541 | do | |
1542 | { | |
1543 | int reg; | |
6057a28f | 1544 | |
dcbf9037 | 1545 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
c19d1205 | 1546 | { |
dcbf9037 | 1547 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 ZW |
1548 | return FAIL; |
1549 | } | |
a737bd4d | 1550 | |
c19d1205 ZW |
1551 | if (in_range) |
1552 | { | |
1553 | int i; | |
a737bd4d | 1554 | |
c19d1205 ZW |
1555 | if (reg <= cur_reg) |
1556 | { | |
dcbf9037 | 1557 | first_error (_("bad range in register list")); |
c19d1205 ZW |
1558 | return FAIL; |
1559 | } | |
40a18ebd | 1560 | |
c19d1205 ZW |
1561 | for (i = cur_reg + 1; i < reg; i++) |
1562 | { | |
1563 | if (range & (1 << i)) | |
1564 | as_tsktsk | |
1565 | (_("Warning: duplicated register (r%d) in register list"), | |
1566 | i); | |
1567 | else | |
1568 | range |= 1 << i; | |
1569 | } | |
1570 | in_range = 0; | |
1571 | } | |
a737bd4d | 1572 | |
c19d1205 ZW |
1573 | if (range & (1 << reg)) |
1574 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1575 | reg); | |
1576 | else if (reg <= cur_reg) | |
1577 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1578 | |
c19d1205 ZW |
1579 | range |= 1 << reg; |
1580 | cur_reg = reg; | |
1581 | } | |
1582 | while (skip_past_comma (&str) != FAIL | |
1583 | || (in_range = 1, *str++ == '-')); | |
1584 | str--; | |
a737bd4d | 1585 | |
c19d1205 ZW |
1586 | if (*str++ != '}') |
1587 | { | |
dcbf9037 | 1588 | first_error (_("missing `}'")); |
c19d1205 ZW |
1589 | return FAIL; |
1590 | } | |
1591 | } | |
1592 | else | |
1593 | { | |
91d6fa6a | 1594 | expressionS exp; |
40a18ebd | 1595 | |
91d6fa6a | 1596 | if (my_get_expression (&exp, &str, GE_NO_PREFIX)) |
c19d1205 | 1597 | return FAIL; |
40a18ebd | 1598 | |
91d6fa6a | 1599 | if (exp.X_op == O_constant) |
c19d1205 | 1600 | { |
91d6fa6a NC |
1601 | if (exp.X_add_number |
1602 | != (exp.X_add_number & 0x0000ffff)) | |
c19d1205 ZW |
1603 | { |
1604 | inst.error = _("invalid register mask"); | |
1605 | return FAIL; | |
1606 | } | |
a737bd4d | 1607 | |
91d6fa6a | 1608 | if ((range & exp.X_add_number) != 0) |
c19d1205 | 1609 | { |
91d6fa6a | 1610 | int regno = range & exp.X_add_number; |
a737bd4d | 1611 | |
c19d1205 ZW |
1612 | regno &= -regno; |
1613 | regno = (1 << regno) - 1; | |
1614 | as_tsktsk | |
1615 | (_("Warning: duplicated register (r%d) in register list"), | |
1616 | regno); | |
1617 | } | |
a737bd4d | 1618 | |
91d6fa6a | 1619 | range |= exp.X_add_number; |
c19d1205 ZW |
1620 | } |
1621 | else | |
1622 | { | |
1623 | if (inst.reloc.type != 0) | |
1624 | { | |
1625 | inst.error = _("expression too complex"); | |
1626 | return FAIL; | |
1627 | } | |
a737bd4d | 1628 | |
91d6fa6a | 1629 | memcpy (&inst.reloc.exp, &exp, sizeof (expressionS)); |
c19d1205 ZW |
1630 | inst.reloc.type = BFD_RELOC_ARM_MULTI; |
1631 | inst.reloc.pc_rel = 0; | |
1632 | } | |
1633 | } | |
a737bd4d | 1634 | |
c19d1205 ZW |
1635 | if (*str == '|' || *str == '+') |
1636 | { | |
1637 | str++; | |
1638 | another_range = 1; | |
1639 | } | |
a737bd4d | 1640 | } |
c19d1205 | 1641 | while (another_range); |
a737bd4d | 1642 | |
c19d1205 ZW |
1643 | *strp = str; |
1644 | return range; | |
a737bd4d NC |
1645 | } |
1646 | ||
5287ad62 JB |
1647 | /* Types of registers in a list. */ |
1648 | ||
1649 | enum reg_list_els | |
1650 | { | |
1651 | REGLIST_VFP_S, | |
1652 | REGLIST_VFP_D, | |
1653 | REGLIST_NEON_D | |
1654 | }; | |
1655 | ||
c19d1205 ZW |
1656 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1657 | Otherwise return the number of registers, and set PBASE to the first | |
5287ad62 JB |
1658 | register. Parses registers of type ETYPE. |
1659 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: | |
1660 | - Q registers can be used to specify pairs of D registers | |
1661 | - { } can be omitted from around a singleton register list | |
1662 | FIXME: This is not implemented, as it would require backtracking in | |
1663 | some cases, e.g.: | |
1664 | vtbl.8 d3,d4,d5 | |
1665 | This could be done (the meaning isn't really ambiguous), but doesn't | |
1666 | fit in well with the current parsing framework. | |
dcbf9037 JB |
1667 | - 32 D registers may be used (also true for VFPv3). |
1668 | FIXME: Types are ignored in these register lists, which is probably a | |
1669 | bug. */ | |
6057a28f | 1670 | |
c19d1205 | 1671 | static int |
037e8744 | 1672 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) |
6057a28f | 1673 | { |
037e8744 | 1674 | char *str = *ccp; |
c19d1205 ZW |
1675 | int base_reg; |
1676 | int new_base; | |
21d799b5 | 1677 | enum arm_reg_type regtype = (enum arm_reg_type) 0; |
5287ad62 | 1678 | int max_regs = 0; |
c19d1205 ZW |
1679 | int count = 0; |
1680 | int warned = 0; | |
1681 | unsigned long mask = 0; | |
a737bd4d | 1682 | int i; |
6057a28f | 1683 | |
037e8744 | 1684 | if (*str != '{') |
5287ad62 JB |
1685 | { |
1686 | inst.error = _("expecting {"); | |
1687 | return FAIL; | |
1688 | } | |
6057a28f | 1689 | |
037e8744 | 1690 | str++; |
6057a28f | 1691 | |
5287ad62 | 1692 | switch (etype) |
c19d1205 | 1693 | { |
5287ad62 | 1694 | case REGLIST_VFP_S: |
c19d1205 ZW |
1695 | regtype = REG_TYPE_VFS; |
1696 | max_regs = 32; | |
5287ad62 | 1697 | break; |
5f4273c7 | 1698 | |
5287ad62 JB |
1699 | case REGLIST_VFP_D: |
1700 | regtype = REG_TYPE_VFD; | |
b7fc2769 | 1701 | break; |
5f4273c7 | 1702 | |
b7fc2769 JB |
1703 | case REGLIST_NEON_D: |
1704 | regtype = REG_TYPE_NDQ; | |
1705 | break; | |
1706 | } | |
1707 | ||
1708 | if (etype != REGLIST_VFP_S) | |
1709 | { | |
b1cc4aeb PB |
1710 | /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ |
1711 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) | |
5287ad62 JB |
1712 | { |
1713 | max_regs = 32; | |
1714 | if (thumb_mode) | |
1715 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 1716 | fpu_vfp_ext_d32); |
5287ad62 JB |
1717 | else |
1718 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 1719 | fpu_vfp_ext_d32); |
5287ad62 JB |
1720 | } |
1721 | else | |
1722 | max_regs = 16; | |
c19d1205 | 1723 | } |
6057a28f | 1724 | |
c19d1205 | 1725 | base_reg = max_regs; |
a737bd4d | 1726 | |
c19d1205 ZW |
1727 | do |
1728 | { | |
5287ad62 | 1729 | int setmask = 1, addregs = 1; |
dcbf9037 | 1730 | |
037e8744 | 1731 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
dcbf9037 | 1732 | |
c19d1205 | 1733 | if (new_base == FAIL) |
a737bd4d | 1734 | { |
dcbf9037 | 1735 | first_error (_(reg_expected_msgs[regtype])); |
c19d1205 ZW |
1736 | return FAIL; |
1737 | } | |
5f4273c7 | 1738 | |
b7fc2769 JB |
1739 | if (new_base >= max_regs) |
1740 | { | |
1741 | first_error (_("register out of range in list")); | |
1742 | return FAIL; | |
1743 | } | |
5f4273c7 | 1744 | |
5287ad62 JB |
1745 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
1746 | if (regtype == REG_TYPE_NQ) | |
1747 | { | |
1748 | setmask = 3; | |
1749 | addregs = 2; | |
1750 | } | |
1751 | ||
c19d1205 ZW |
1752 | if (new_base < base_reg) |
1753 | base_reg = new_base; | |
a737bd4d | 1754 | |
5287ad62 | 1755 | if (mask & (setmask << new_base)) |
c19d1205 | 1756 | { |
dcbf9037 | 1757 | first_error (_("invalid register list")); |
c19d1205 | 1758 | return FAIL; |
a737bd4d | 1759 | } |
a737bd4d | 1760 | |
c19d1205 ZW |
1761 | if ((mask >> new_base) != 0 && ! warned) |
1762 | { | |
1763 | as_tsktsk (_("register list not in ascending order")); | |
1764 | warned = 1; | |
1765 | } | |
0bbf2aa4 | 1766 | |
5287ad62 JB |
1767 | mask |= setmask << new_base; |
1768 | count += addregs; | |
0bbf2aa4 | 1769 | |
037e8744 | 1770 | if (*str == '-') /* We have the start of a range expression */ |
c19d1205 ZW |
1771 | { |
1772 | int high_range; | |
0bbf2aa4 | 1773 | |
037e8744 | 1774 | str++; |
0bbf2aa4 | 1775 | |
037e8744 | 1776 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
dcbf9037 | 1777 | == FAIL) |
c19d1205 ZW |
1778 | { |
1779 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1780 | return FAIL; | |
1781 | } | |
0bbf2aa4 | 1782 | |
b7fc2769 JB |
1783 | if (high_range >= max_regs) |
1784 | { | |
1785 | first_error (_("register out of range in list")); | |
1786 | return FAIL; | |
1787 | } | |
1788 | ||
5287ad62 JB |
1789 | if (regtype == REG_TYPE_NQ) |
1790 | high_range = high_range + 1; | |
1791 | ||
c19d1205 ZW |
1792 | if (high_range <= new_base) |
1793 | { | |
1794 | inst.error = _("register range not in ascending order"); | |
1795 | return FAIL; | |
1796 | } | |
0bbf2aa4 | 1797 | |
5287ad62 | 1798 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
0bbf2aa4 | 1799 | { |
5287ad62 | 1800 | if (mask & (setmask << new_base)) |
0bbf2aa4 | 1801 | { |
c19d1205 ZW |
1802 | inst.error = _("invalid register list"); |
1803 | return FAIL; | |
0bbf2aa4 | 1804 | } |
c19d1205 | 1805 | |
5287ad62 JB |
1806 | mask |= setmask << new_base; |
1807 | count += addregs; | |
0bbf2aa4 | 1808 | } |
0bbf2aa4 | 1809 | } |
0bbf2aa4 | 1810 | } |
037e8744 | 1811 | while (skip_past_comma (&str) != FAIL); |
0bbf2aa4 | 1812 | |
037e8744 | 1813 | str++; |
0bbf2aa4 | 1814 | |
c19d1205 ZW |
1815 | /* Sanity check -- should have raised a parse error above. */ |
1816 | if (count == 0 || count > max_regs) | |
1817 | abort (); | |
1818 | ||
1819 | *pbase = base_reg; | |
1820 | ||
1821 | /* Final test -- the registers must be consecutive. */ | |
1822 | mask >>= base_reg; | |
1823 | for (i = 0; i < count; i++) | |
1824 | { | |
1825 | if ((mask & (1u << i)) == 0) | |
1826 | { | |
1827 | inst.error = _("non-contiguous register range"); | |
1828 | return FAIL; | |
1829 | } | |
1830 | } | |
1831 | ||
037e8744 JB |
1832 | *ccp = str; |
1833 | ||
c19d1205 | 1834 | return count; |
b99bd4ef NC |
1835 | } |
1836 | ||
dcbf9037 JB |
1837 | /* True if two alias types are the same. */ |
1838 | ||
c921be7d | 1839 | static bfd_boolean |
dcbf9037 JB |
1840 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) |
1841 | { | |
1842 | if (!a && !b) | |
c921be7d | 1843 | return TRUE; |
5f4273c7 | 1844 | |
dcbf9037 | 1845 | if (!a || !b) |
c921be7d | 1846 | return FALSE; |
dcbf9037 JB |
1847 | |
1848 | if (a->defined != b->defined) | |
c921be7d | 1849 | return FALSE; |
5f4273c7 | 1850 | |
dcbf9037 JB |
1851 | if ((a->defined & NTA_HASTYPE) != 0 |
1852 | && (a->eltype.type != b->eltype.type | |
1853 | || a->eltype.size != b->eltype.size)) | |
c921be7d | 1854 | return FALSE; |
dcbf9037 JB |
1855 | |
1856 | if ((a->defined & NTA_HASINDEX) != 0 | |
1857 | && (a->index != b->index)) | |
c921be7d | 1858 | return FALSE; |
5f4273c7 | 1859 | |
c921be7d | 1860 | return TRUE; |
dcbf9037 JB |
1861 | } |
1862 | ||
5287ad62 JB |
1863 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
1864 | The base register is put in *PBASE. | |
dcbf9037 | 1865 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
5287ad62 JB |
1866 | the return value. |
1867 | The register stride (minus one) is put in bit 4 of the return value. | |
dcbf9037 JB |
1868 | Bits [6:5] encode the list length (minus one). |
1869 | The type of the list elements is put in *ELTYPE, if non-NULL. */ | |
5287ad62 | 1870 | |
5287ad62 | 1871 | #define NEON_LANE(X) ((X) & 0xf) |
dcbf9037 | 1872 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
5287ad62 JB |
1873 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
1874 | ||
1875 | static int | |
dcbf9037 JB |
1876 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
1877 | struct neon_type_el *eltype) | |
5287ad62 JB |
1878 | { |
1879 | char *ptr = *str; | |
1880 | int base_reg = -1; | |
1881 | int reg_incr = -1; | |
1882 | int count = 0; | |
1883 | int lane = -1; | |
1884 | int leading_brace = 0; | |
1885 | enum arm_reg_type rtype = REG_TYPE_NDQ; | |
20203fb9 NC |
1886 | const char *const incr_error = _("register stride must be 1 or 2"); |
1887 | const char *const type_error = _("mismatched element/structure types in list"); | |
dcbf9037 | 1888 | struct neon_typed_alias firsttype; |
5f4273c7 | 1889 | |
5287ad62 JB |
1890 | if (skip_past_char (&ptr, '{') == SUCCESS) |
1891 | leading_brace = 1; | |
5f4273c7 | 1892 | |
5287ad62 JB |
1893 | do |
1894 | { | |
dcbf9037 JB |
1895 | struct neon_typed_alias atype; |
1896 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); | |
1897 | ||
5287ad62 JB |
1898 | if (getreg == FAIL) |
1899 | { | |
dcbf9037 | 1900 | first_error (_(reg_expected_msgs[rtype])); |
5287ad62 JB |
1901 | return FAIL; |
1902 | } | |
5f4273c7 | 1903 | |
5287ad62 JB |
1904 | if (base_reg == -1) |
1905 | { | |
1906 | base_reg = getreg; | |
1907 | if (rtype == REG_TYPE_NQ) | |
1908 | { | |
1909 | reg_incr = 1; | |
5287ad62 | 1910 | } |
dcbf9037 | 1911 | firsttype = atype; |
5287ad62 JB |
1912 | } |
1913 | else if (reg_incr == -1) | |
1914 | { | |
1915 | reg_incr = getreg - base_reg; | |
1916 | if (reg_incr < 1 || reg_incr > 2) | |
1917 | { | |
dcbf9037 | 1918 | first_error (_(incr_error)); |
5287ad62 JB |
1919 | return FAIL; |
1920 | } | |
1921 | } | |
1922 | else if (getreg != base_reg + reg_incr * count) | |
1923 | { | |
dcbf9037 JB |
1924 | first_error (_(incr_error)); |
1925 | return FAIL; | |
1926 | } | |
1927 | ||
c921be7d | 1928 | if (! neon_alias_types_same (&atype, &firsttype)) |
dcbf9037 JB |
1929 | { |
1930 | first_error (_(type_error)); | |
5287ad62 JB |
1931 | return FAIL; |
1932 | } | |
5f4273c7 | 1933 | |
5287ad62 JB |
1934 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list |
1935 | modes. */ | |
1936 | if (ptr[0] == '-') | |
1937 | { | |
dcbf9037 | 1938 | struct neon_typed_alias htype; |
5287ad62 JB |
1939 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; |
1940 | if (lane == -1) | |
1941 | lane = NEON_INTERLEAVE_LANES; | |
1942 | else if (lane != NEON_INTERLEAVE_LANES) | |
1943 | { | |
dcbf9037 | 1944 | first_error (_(type_error)); |
5287ad62 JB |
1945 | return FAIL; |
1946 | } | |
1947 | if (reg_incr == -1) | |
1948 | reg_incr = 1; | |
1949 | else if (reg_incr != 1) | |
1950 | { | |
dcbf9037 | 1951 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); |
5287ad62 JB |
1952 | return FAIL; |
1953 | } | |
1954 | ptr++; | |
dcbf9037 | 1955 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); |
5287ad62 JB |
1956 | if (hireg == FAIL) |
1957 | { | |
dcbf9037 JB |
1958 | first_error (_(reg_expected_msgs[rtype])); |
1959 | return FAIL; | |
1960 | } | |
c921be7d | 1961 | if (! neon_alias_types_same (&htype, &firsttype)) |
dcbf9037 JB |
1962 | { |
1963 | first_error (_(type_error)); | |
5287ad62 JB |
1964 | return FAIL; |
1965 | } | |
1966 | count += hireg + dregs - getreg; | |
1967 | continue; | |
1968 | } | |
5f4273c7 | 1969 | |
5287ad62 JB |
1970 | /* If we're using Q registers, we can't use [] or [n] syntax. */ |
1971 | if (rtype == REG_TYPE_NQ) | |
1972 | { | |
1973 | count += 2; | |
1974 | continue; | |
1975 | } | |
5f4273c7 | 1976 | |
dcbf9037 | 1977 | if ((atype.defined & NTA_HASINDEX) != 0) |
5287ad62 | 1978 | { |
dcbf9037 JB |
1979 | if (lane == -1) |
1980 | lane = atype.index; | |
1981 | else if (lane != atype.index) | |
5287ad62 | 1982 | { |
dcbf9037 JB |
1983 | first_error (_(type_error)); |
1984 | return FAIL; | |
5287ad62 JB |
1985 | } |
1986 | } | |
1987 | else if (lane == -1) | |
1988 | lane = NEON_INTERLEAVE_LANES; | |
1989 | else if (lane != NEON_INTERLEAVE_LANES) | |
1990 | { | |
dcbf9037 | 1991 | first_error (_(type_error)); |
5287ad62 JB |
1992 | return FAIL; |
1993 | } | |
1994 | count++; | |
1995 | } | |
1996 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); | |
5f4273c7 | 1997 | |
5287ad62 JB |
1998 | /* No lane set by [x]. We must be interleaving structures. */ |
1999 | if (lane == -1) | |
2000 | lane = NEON_INTERLEAVE_LANES; | |
5f4273c7 | 2001 | |
5287ad62 JB |
2002 | /* Sanity check. */ |
2003 | if (lane == -1 || base_reg == -1 || count < 1 || count > 4 | |
2004 | || (count > 1 && reg_incr == -1)) | |
2005 | { | |
dcbf9037 | 2006 | first_error (_("error parsing element/structure list")); |
5287ad62 JB |
2007 | return FAIL; |
2008 | } | |
2009 | ||
2010 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) | |
2011 | { | |
dcbf9037 | 2012 | first_error (_("expected }")); |
5287ad62 JB |
2013 | return FAIL; |
2014 | } | |
5f4273c7 | 2015 | |
5287ad62 JB |
2016 | if (reg_incr == -1) |
2017 | reg_incr = 1; | |
2018 | ||
dcbf9037 JB |
2019 | if (eltype) |
2020 | *eltype = firsttype.eltype; | |
2021 | ||
5287ad62 JB |
2022 | *pbase = base_reg; |
2023 | *str = ptr; | |
5f4273c7 | 2024 | |
5287ad62 JB |
2025 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); |
2026 | } | |
2027 | ||
c19d1205 ZW |
2028 | /* Parse an explicit relocation suffix on an expression. This is |
2029 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
2030 | arm_reloc_hsh contains no entries, so this function can only | |
2031 | succeed if there is no () after the word. Returns -1 on error, | |
2032 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
2033 | static int | |
2034 | parse_reloc (char **str) | |
b99bd4ef | 2035 | { |
c19d1205 ZW |
2036 | struct reloc_entry *r; |
2037 | char *p, *q; | |
b99bd4ef | 2038 | |
c19d1205 ZW |
2039 | if (**str != '(') |
2040 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 2041 | |
c19d1205 ZW |
2042 | p = *str + 1; |
2043 | q = p; | |
2044 | ||
2045 | while (*q && *q != ')' && *q != ',') | |
2046 | q++; | |
2047 | if (*q != ')') | |
2048 | return -1; | |
2049 | ||
21d799b5 NC |
2050 | if ((r = (struct reloc_entry *) |
2051 | hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
c19d1205 ZW |
2052 | return -1; |
2053 | ||
2054 | *str = q + 1; | |
2055 | return r->reloc; | |
b99bd4ef NC |
2056 | } |
2057 | ||
c19d1205 ZW |
2058 | /* Directives: register aliases. */ |
2059 | ||
dcbf9037 | 2060 | static struct reg_entry * |
c19d1205 | 2061 | insert_reg_alias (char *str, int number, int type) |
b99bd4ef | 2062 | { |
d3ce72d0 | 2063 | struct reg_entry *new_reg; |
c19d1205 | 2064 | const char *name; |
b99bd4ef | 2065 | |
d3ce72d0 | 2066 | if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) |
c19d1205 | 2067 | { |
d3ce72d0 | 2068 | if (new_reg->builtin) |
c19d1205 | 2069 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); |
b99bd4ef | 2070 | |
c19d1205 ZW |
2071 | /* Only warn about a redefinition if it's not defined as the |
2072 | same register. */ | |
d3ce72d0 | 2073 | else if (new_reg->number != number || new_reg->type != type) |
c19d1205 | 2074 | as_warn (_("ignoring redefinition of register alias '%s'"), str); |
69b97547 | 2075 | |
d929913e | 2076 | return NULL; |
c19d1205 | 2077 | } |
b99bd4ef | 2078 | |
c19d1205 | 2079 | name = xstrdup (str); |
d3ce72d0 | 2080 | new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry)); |
b99bd4ef | 2081 | |
d3ce72d0 NC |
2082 | new_reg->name = name; |
2083 | new_reg->number = number; | |
2084 | new_reg->type = type; | |
2085 | new_reg->builtin = FALSE; | |
2086 | new_reg->neon = NULL; | |
b99bd4ef | 2087 | |
d3ce72d0 | 2088 | if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) |
c19d1205 | 2089 | abort (); |
5f4273c7 | 2090 | |
d3ce72d0 | 2091 | return new_reg; |
dcbf9037 JB |
2092 | } |
2093 | ||
2094 | static void | |
2095 | insert_neon_reg_alias (char *str, int number, int type, | |
2096 | struct neon_typed_alias *atype) | |
2097 | { | |
2098 | struct reg_entry *reg = insert_reg_alias (str, number, type); | |
5f4273c7 | 2099 | |
dcbf9037 JB |
2100 | if (!reg) |
2101 | { | |
2102 | first_error (_("attempt to redefine typed alias")); | |
2103 | return; | |
2104 | } | |
5f4273c7 | 2105 | |
dcbf9037 JB |
2106 | if (atype) |
2107 | { | |
21d799b5 NC |
2108 | reg->neon = (struct neon_typed_alias *) |
2109 | xmalloc (sizeof (struct neon_typed_alias)); | |
dcbf9037 JB |
2110 | *reg->neon = *atype; |
2111 | } | |
c19d1205 | 2112 | } |
b99bd4ef | 2113 | |
c19d1205 | 2114 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 2115 | |
c19d1205 | 2116 | new_register_name .req existing_register_name |
b99bd4ef | 2117 | |
c19d1205 | 2118 | If we find one, or if it looks sufficiently like one that we want to |
d929913e | 2119 | handle any error here, return TRUE. Otherwise return FALSE. */ |
b99bd4ef | 2120 | |
d929913e | 2121 | static bfd_boolean |
c19d1205 ZW |
2122 | create_register_alias (char * newname, char *p) |
2123 | { | |
2124 | struct reg_entry *old; | |
2125 | char *oldname, *nbuf; | |
2126 | size_t nlen; | |
b99bd4ef | 2127 | |
c19d1205 ZW |
2128 | /* The input scrubber ensures that whitespace after the mnemonic is |
2129 | collapsed to single spaces. */ | |
2130 | oldname = p; | |
2131 | if (strncmp (oldname, " .req ", 6) != 0) | |
d929913e | 2132 | return FALSE; |
b99bd4ef | 2133 | |
c19d1205 ZW |
2134 | oldname += 6; |
2135 | if (*oldname == '\0') | |
d929913e | 2136 | return FALSE; |
b99bd4ef | 2137 | |
21d799b5 | 2138 | old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname); |
c19d1205 | 2139 | if (!old) |
b99bd4ef | 2140 | { |
c19d1205 | 2141 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
d929913e | 2142 | return TRUE; |
b99bd4ef NC |
2143 | } |
2144 | ||
c19d1205 ZW |
2145 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2146 | the desired alias name, and p points to its end. If not, then | |
2147 | the desired alias name is in the global original_case_string. */ | |
2148 | #ifdef TC_CASE_SENSITIVE | |
2149 | nlen = p - newname; | |
2150 | #else | |
2151 | newname = original_case_string; | |
2152 | nlen = strlen (newname); | |
2153 | #endif | |
b99bd4ef | 2154 | |
21d799b5 | 2155 | nbuf = (char *) alloca (nlen + 1); |
c19d1205 ZW |
2156 | memcpy (nbuf, newname, nlen); |
2157 | nbuf[nlen] = '\0'; | |
b99bd4ef | 2158 | |
c19d1205 ZW |
2159 | /* Create aliases under the new name as stated; an all-lowercase |
2160 | version of the new name; and an all-uppercase version of the new | |
2161 | name. */ | |
d929913e NC |
2162 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) |
2163 | { | |
2164 | for (p = nbuf; *p; p++) | |
2165 | *p = TOUPPER (*p); | |
c19d1205 | 2166 | |
d929913e NC |
2167 | if (strncmp (nbuf, newname, nlen)) |
2168 | { | |
2169 | /* If this attempt to create an additional alias fails, do not bother | |
2170 | trying to create the all-lower case alias. We will fail and issue | |
2171 | a second, duplicate error message. This situation arises when the | |
2172 | programmer does something like: | |
2173 | foo .req r0 | |
2174 | Foo .req r1 | |
2175 | The second .req creates the "Foo" alias but then fails to create | |
5f4273c7 | 2176 | the artificial FOO alias because it has already been created by the |
d929913e NC |
2177 | first .req. */ |
2178 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
2179 | return TRUE; | |
2180 | } | |
c19d1205 | 2181 | |
d929913e NC |
2182 | for (p = nbuf; *p; p++) |
2183 | *p = TOLOWER (*p); | |
c19d1205 | 2184 | |
d929913e NC |
2185 | if (strncmp (nbuf, newname, nlen)) |
2186 | insert_reg_alias (nbuf, old->number, old->type); | |
2187 | } | |
c19d1205 | 2188 | |
d929913e | 2189 | return TRUE; |
b99bd4ef NC |
2190 | } |
2191 | ||
dcbf9037 JB |
2192 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
2193 | X .dn d5.s32[1] | |
2194 | Y .qn 6.s16 | |
2195 | Z .dn d7 | |
2196 | T .dn Z[0] | |
2197 | These typed registers can be used instead of the types specified after the | |
2198 | Neon mnemonic, so long as all operands given have types. Types can also be | |
2199 | specified directly, e.g.: | |
5f4273c7 | 2200 | vadd d0.s32, d1.s32, d2.s32 */ |
dcbf9037 | 2201 | |
c921be7d | 2202 | static bfd_boolean |
dcbf9037 JB |
2203 | create_neon_reg_alias (char *newname, char *p) |
2204 | { | |
2205 | enum arm_reg_type basetype; | |
2206 | struct reg_entry *basereg; | |
2207 | struct reg_entry mybasereg; | |
2208 | struct neon_type ntype; | |
2209 | struct neon_typed_alias typeinfo; | |
2210 | char *namebuf, *nameend; | |
2211 | int namelen; | |
5f4273c7 | 2212 | |
dcbf9037 JB |
2213 | typeinfo.defined = 0; |
2214 | typeinfo.eltype.type = NT_invtype; | |
2215 | typeinfo.eltype.size = -1; | |
2216 | typeinfo.index = -1; | |
5f4273c7 | 2217 | |
dcbf9037 | 2218 | nameend = p; |
5f4273c7 | 2219 | |
dcbf9037 JB |
2220 | if (strncmp (p, " .dn ", 5) == 0) |
2221 | basetype = REG_TYPE_VFD; | |
2222 | else if (strncmp (p, " .qn ", 5) == 0) | |
2223 | basetype = REG_TYPE_NQ; | |
2224 | else | |
c921be7d | 2225 | return FALSE; |
5f4273c7 | 2226 | |
dcbf9037 | 2227 | p += 5; |
5f4273c7 | 2228 | |
dcbf9037 | 2229 | if (*p == '\0') |
c921be7d | 2230 | return FALSE; |
5f4273c7 | 2231 | |
dcbf9037 JB |
2232 | basereg = arm_reg_parse_multi (&p); |
2233 | ||
2234 | if (basereg && basereg->type != basetype) | |
2235 | { | |
2236 | as_bad (_("bad type for register")); | |
c921be7d | 2237 | return FALSE; |
dcbf9037 JB |
2238 | } |
2239 | ||
2240 | if (basereg == NULL) | |
2241 | { | |
2242 | expressionS exp; | |
2243 | /* Try parsing as an integer. */ | |
2244 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2245 | if (exp.X_op != O_constant) | |
2246 | { | |
2247 | as_bad (_("expression must be constant")); | |
c921be7d | 2248 | return FALSE; |
dcbf9037 JB |
2249 | } |
2250 | basereg = &mybasereg; | |
2251 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 | |
2252 | : exp.X_add_number; | |
2253 | basereg->neon = 0; | |
2254 | } | |
2255 | ||
2256 | if (basereg->neon) | |
2257 | typeinfo = *basereg->neon; | |
2258 | ||
2259 | if (parse_neon_type (&ntype, &p) == SUCCESS) | |
2260 | { | |
2261 | /* We got a type. */ | |
2262 | if (typeinfo.defined & NTA_HASTYPE) | |
2263 | { | |
2264 | as_bad (_("can't redefine the type of a register alias")); | |
c921be7d | 2265 | return FALSE; |
dcbf9037 | 2266 | } |
5f4273c7 | 2267 | |
dcbf9037 JB |
2268 | typeinfo.defined |= NTA_HASTYPE; |
2269 | if (ntype.elems != 1) | |
2270 | { | |
2271 | as_bad (_("you must specify a single type only")); | |
c921be7d | 2272 | return FALSE; |
dcbf9037 JB |
2273 | } |
2274 | typeinfo.eltype = ntype.el[0]; | |
2275 | } | |
5f4273c7 | 2276 | |
dcbf9037 JB |
2277 | if (skip_past_char (&p, '[') == SUCCESS) |
2278 | { | |
2279 | expressionS exp; | |
2280 | /* We got a scalar index. */ | |
5f4273c7 | 2281 | |
dcbf9037 JB |
2282 | if (typeinfo.defined & NTA_HASINDEX) |
2283 | { | |
2284 | as_bad (_("can't redefine the index of a scalar alias")); | |
c921be7d | 2285 | return FALSE; |
dcbf9037 | 2286 | } |
5f4273c7 | 2287 | |
dcbf9037 | 2288 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
5f4273c7 | 2289 | |
dcbf9037 JB |
2290 | if (exp.X_op != O_constant) |
2291 | { | |
2292 | as_bad (_("scalar index must be constant")); | |
c921be7d | 2293 | return FALSE; |
dcbf9037 | 2294 | } |
5f4273c7 | 2295 | |
dcbf9037 JB |
2296 | typeinfo.defined |= NTA_HASINDEX; |
2297 | typeinfo.index = exp.X_add_number; | |
5f4273c7 | 2298 | |
dcbf9037 JB |
2299 | if (skip_past_char (&p, ']') == FAIL) |
2300 | { | |
2301 | as_bad (_("expecting ]")); | |
c921be7d | 2302 | return FALSE; |
dcbf9037 JB |
2303 | } |
2304 | } | |
2305 | ||
2306 | namelen = nameend - newname; | |
21d799b5 | 2307 | namebuf = (char *) alloca (namelen + 1); |
dcbf9037 JB |
2308 | strncpy (namebuf, newname, namelen); |
2309 | namebuf[namelen] = '\0'; | |
5f4273c7 | 2310 | |
dcbf9037 JB |
2311 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
2312 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2313 | |
dcbf9037 JB |
2314 | /* Insert name in all uppercase. */ |
2315 | for (p = namebuf; *p; p++) | |
2316 | *p = TOUPPER (*p); | |
5f4273c7 | 2317 | |
dcbf9037 JB |
2318 | if (strncmp (namebuf, newname, namelen)) |
2319 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2320 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2321 | |
dcbf9037 JB |
2322 | /* Insert name in all lowercase. */ |
2323 | for (p = namebuf; *p; p++) | |
2324 | *p = TOLOWER (*p); | |
5f4273c7 | 2325 | |
dcbf9037 JB |
2326 | if (strncmp (namebuf, newname, namelen)) |
2327 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2328 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2329 | |
c921be7d | 2330 | return TRUE; |
dcbf9037 JB |
2331 | } |
2332 | ||
c19d1205 ZW |
2333 | /* Should never be called, as .req goes between the alias and the |
2334 | register name, not at the beginning of the line. */ | |
c921be7d | 2335 | |
b99bd4ef | 2336 | static void |
c19d1205 | 2337 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2338 | { |
c19d1205 ZW |
2339 | as_bad (_("invalid syntax for .req directive")); |
2340 | } | |
b99bd4ef | 2341 | |
dcbf9037 JB |
2342 | static void |
2343 | s_dn (int a ATTRIBUTE_UNUSED) | |
2344 | { | |
2345 | as_bad (_("invalid syntax for .dn directive")); | |
2346 | } | |
2347 | ||
2348 | static void | |
2349 | s_qn (int a ATTRIBUTE_UNUSED) | |
2350 | { | |
2351 | as_bad (_("invalid syntax for .qn directive")); | |
2352 | } | |
2353 | ||
c19d1205 ZW |
2354 | /* The .unreq directive deletes an alias which was previously defined |
2355 | by .req. For example: | |
b99bd4ef | 2356 | |
c19d1205 ZW |
2357 | my_alias .req r11 |
2358 | .unreq my_alias */ | |
b99bd4ef NC |
2359 | |
2360 | static void | |
c19d1205 | 2361 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2362 | { |
c19d1205 ZW |
2363 | char * name; |
2364 | char saved_char; | |
b99bd4ef | 2365 | |
c19d1205 ZW |
2366 | name = input_line_pointer; |
2367 | ||
2368 | while (*input_line_pointer != 0 | |
2369 | && *input_line_pointer != ' ' | |
2370 | && *input_line_pointer != '\n') | |
2371 | ++input_line_pointer; | |
2372 | ||
2373 | saved_char = *input_line_pointer; | |
2374 | *input_line_pointer = 0; | |
2375 | ||
2376 | if (!*name) | |
2377 | as_bad (_("invalid syntax for .unreq directive")); | |
2378 | else | |
2379 | { | |
21d799b5 NC |
2380 | struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh, |
2381 | name); | |
c19d1205 ZW |
2382 | |
2383 | if (!reg) | |
2384 | as_bad (_("unknown register alias '%s'"), name); | |
2385 | else if (reg->builtin) | |
2386 | as_warn (_("ignoring attempt to undefine built-in register '%s'"), | |
2387 | name); | |
2388 | else | |
2389 | { | |
d929913e NC |
2390 | char * p; |
2391 | char * nbuf; | |
2392 | ||
db0bc284 | 2393 | hash_delete (arm_reg_hsh, name, FALSE); |
c19d1205 | 2394 | free ((char *) reg->name); |
dcbf9037 JB |
2395 | if (reg->neon) |
2396 | free (reg->neon); | |
c19d1205 | 2397 | free (reg); |
d929913e NC |
2398 | |
2399 | /* Also locate the all upper case and all lower case versions. | |
2400 | Do not complain if we cannot find one or the other as it | |
2401 | was probably deleted above. */ | |
5f4273c7 | 2402 | |
d929913e NC |
2403 | nbuf = strdup (name); |
2404 | for (p = nbuf; *p; p++) | |
2405 | *p = TOUPPER (*p); | |
21d799b5 | 2406 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2407 | if (reg) |
2408 | { | |
db0bc284 | 2409 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2410 | free ((char *) reg->name); |
2411 | if (reg->neon) | |
2412 | free (reg->neon); | |
2413 | free (reg); | |
2414 | } | |
2415 | ||
2416 | for (p = nbuf; *p; p++) | |
2417 | *p = TOLOWER (*p); | |
21d799b5 | 2418 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2419 | if (reg) |
2420 | { | |
db0bc284 | 2421 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2422 | free ((char *) reg->name); |
2423 | if (reg->neon) | |
2424 | free (reg->neon); | |
2425 | free (reg); | |
2426 | } | |
2427 | ||
2428 | free (nbuf); | |
c19d1205 ZW |
2429 | } |
2430 | } | |
b99bd4ef | 2431 | |
c19d1205 | 2432 | *input_line_pointer = saved_char; |
b99bd4ef NC |
2433 | demand_empty_rest_of_line (); |
2434 | } | |
2435 | ||
c19d1205 ZW |
2436 | /* Directives: Instruction set selection. */ |
2437 | ||
2438 | #ifdef OBJ_ELF | |
2439 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
2440 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
2441 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
2442 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
2443 | ||
cd000bff DJ |
2444 | /* Create a new mapping symbol for the transition to STATE. */ |
2445 | ||
2446 | static void | |
2447 | make_mapping_symbol (enum mstate state, valueT value, fragS *frag) | |
b99bd4ef | 2448 | { |
a737bd4d | 2449 | symbolS * symbolP; |
c19d1205 ZW |
2450 | const char * symname; |
2451 | int type; | |
b99bd4ef | 2452 | |
c19d1205 | 2453 | switch (state) |
b99bd4ef | 2454 | { |
c19d1205 ZW |
2455 | case MAP_DATA: |
2456 | symname = "$d"; | |
2457 | type = BSF_NO_FLAGS; | |
2458 | break; | |
2459 | case MAP_ARM: | |
2460 | symname = "$a"; | |
2461 | type = BSF_NO_FLAGS; | |
2462 | break; | |
2463 | case MAP_THUMB: | |
2464 | symname = "$t"; | |
2465 | type = BSF_NO_FLAGS; | |
2466 | break; | |
c19d1205 ZW |
2467 | default: |
2468 | abort (); | |
2469 | } | |
2470 | ||
cd000bff | 2471 | symbolP = symbol_new (symname, now_seg, value, frag); |
c19d1205 ZW |
2472 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; |
2473 | ||
2474 | switch (state) | |
2475 | { | |
2476 | case MAP_ARM: | |
2477 | THUMB_SET_FUNC (symbolP, 0); | |
2478 | ARM_SET_THUMB (symbolP, 0); | |
2479 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2480 | break; | |
2481 | ||
2482 | case MAP_THUMB: | |
2483 | THUMB_SET_FUNC (symbolP, 1); | |
2484 | ARM_SET_THUMB (symbolP, 1); | |
2485 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2486 | break; | |
2487 | ||
2488 | case MAP_DATA: | |
2489 | default: | |
cd000bff DJ |
2490 | break; |
2491 | } | |
2492 | ||
2493 | /* Save the mapping symbols for future reference. Also check that | |
2494 | we do not place two mapping symbols at the same offset within a | |
2495 | frag. We'll handle overlap between frags in | |
2de7820f JZ |
2496 | check_mapping_symbols. |
2497 | ||
2498 | If .fill or other data filling directive generates zero sized data, | |
2499 | the mapping symbol for the following code will have the same value | |
2500 | as the one generated for the data filling directive. In this case, | |
2501 | we replace the old symbol with the new one at the same address. */ | |
cd000bff DJ |
2502 | if (value == 0) |
2503 | { | |
2de7820f JZ |
2504 | if (frag->tc_frag_data.first_map != NULL) |
2505 | { | |
2506 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); | |
2507 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP); | |
2508 | } | |
cd000bff DJ |
2509 | frag->tc_frag_data.first_map = symbolP; |
2510 | } | |
2511 | if (frag->tc_frag_data.last_map != NULL) | |
0f020cef JZ |
2512 | { |
2513 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP)); | |
0f020cef JZ |
2514 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) |
2515 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP); | |
2516 | } | |
cd000bff DJ |
2517 | frag->tc_frag_data.last_map = symbolP; |
2518 | } | |
2519 | ||
2520 | /* We must sometimes convert a region marked as code to data during | |
2521 | code alignment, if an odd number of bytes have to be padded. The | |
2522 | code mapping symbol is pushed to an aligned address. */ | |
2523 | ||
2524 | static void | |
2525 | insert_data_mapping_symbol (enum mstate state, | |
2526 | valueT value, fragS *frag, offsetT bytes) | |
2527 | { | |
2528 | /* If there was already a mapping symbol, remove it. */ | |
2529 | if (frag->tc_frag_data.last_map != NULL | |
2530 | && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) | |
2531 | { | |
2532 | symbolS *symp = frag->tc_frag_data.last_map; | |
2533 | ||
2534 | if (value == 0) | |
2535 | { | |
2536 | know (frag->tc_frag_data.first_map == symp); | |
2537 | frag->tc_frag_data.first_map = NULL; | |
2538 | } | |
2539 | frag->tc_frag_data.last_map = NULL; | |
2540 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
c19d1205 | 2541 | } |
cd000bff DJ |
2542 | |
2543 | make_mapping_symbol (MAP_DATA, value, frag); | |
2544 | make_mapping_symbol (state, value + bytes, frag); | |
2545 | } | |
2546 | ||
2547 | static void mapping_state_2 (enum mstate state, int max_chars); | |
2548 | ||
2549 | /* Set the mapping state to STATE. Only call this when about to | |
2550 | emit some STATE bytes to the file. */ | |
2551 | ||
2552 | void | |
2553 | mapping_state (enum mstate state) | |
2554 | { | |
940b5ce0 DJ |
2555 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2556 | ||
cd000bff DJ |
2557 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
2558 | ||
2559 | if (mapstate == state) | |
2560 | /* The mapping symbol has already been emitted. | |
2561 | There is nothing else to do. */ | |
2562 | return; | |
2563 | else if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) | |
2564 | /* This case will be evaluated later in the next else. */ | |
2565 | return; | |
2566 | else if (TRANSITION (MAP_UNDEFINED, MAP_ARM) | |
2567 | || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) | |
2568 | { | |
2569 | /* Only add the symbol if the offset is > 0: | |
2570 | if we're at the first frag, check it's size > 0; | |
2571 | if we're not at the first frag, then for sure | |
2572 | the offset is > 0. */ | |
2573 | struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; | |
2574 | const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); | |
2575 | ||
2576 | if (add_symbol) | |
2577 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); | |
2578 | } | |
2579 | ||
2580 | mapping_state_2 (state, 0); | |
2581 | #undef TRANSITION | |
2582 | } | |
2583 | ||
2584 | /* Same as mapping_state, but MAX_CHARS bytes have already been | |
2585 | allocated. Put the mapping symbol that far back. */ | |
2586 | ||
2587 | static void | |
2588 | mapping_state_2 (enum mstate state, int max_chars) | |
2589 | { | |
940b5ce0 DJ |
2590 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2591 | ||
2592 | if (!SEG_NORMAL (now_seg)) | |
2593 | return; | |
2594 | ||
cd000bff DJ |
2595 | if (mapstate == state) |
2596 | /* The mapping symbol has already been emitted. | |
2597 | There is nothing else to do. */ | |
2598 | return; | |
2599 | ||
cd000bff DJ |
2600 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; |
2601 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); | |
c19d1205 ZW |
2602 | } |
2603 | #else | |
d3106081 NS |
2604 | #define mapping_state(x) ((void)0) |
2605 | #define mapping_state_2(x, y) ((void)0) | |
c19d1205 ZW |
2606 | #endif |
2607 | ||
2608 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
2609 | ||
4343666d | 2610 | #ifdef OBJ_COFF |
c19d1205 ZW |
2611 | static symbolS * |
2612 | find_real_start (symbolS * symbolP) | |
2613 | { | |
2614 | char * real_start; | |
2615 | const char * name = S_GET_NAME (symbolP); | |
2616 | symbolS * new_target; | |
2617 | ||
2618 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
2619 | #define STUB_NAME ".real_start_of" | |
2620 | ||
2621 | if (name == NULL) | |
2622 | abort (); | |
2623 | ||
37f6032b ZW |
2624 | /* The compiler may generate BL instructions to local labels because |
2625 | it needs to perform a branch to a far away location. These labels | |
2626 | do not have a corresponding ".real_start_of" label. We check | |
2627 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
2628 | the ".real_start_of" convention for nonlocal branches. */ | |
2629 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
2630 | return symbolP; |
2631 | ||
37f6032b | 2632 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
2633 | new_target = symbol_find (real_start); |
2634 | ||
2635 | if (new_target == NULL) | |
2636 | { | |
bd3ba5d1 | 2637 | as_warn (_("Failed to find real start of function: %s\n"), name); |
c19d1205 ZW |
2638 | new_target = symbolP; |
2639 | } | |
2640 | ||
c19d1205 ZW |
2641 | return new_target; |
2642 | } | |
4343666d | 2643 | #endif |
c19d1205 ZW |
2644 | |
2645 | static void | |
2646 | opcode_select (int width) | |
2647 | { | |
2648 | switch (width) | |
2649 | { | |
2650 | case 16: | |
2651 | if (! thumb_mode) | |
2652 | { | |
e74cfd16 | 2653 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
2654 | as_bad (_("selected processor does not support THUMB opcodes")); |
2655 | ||
2656 | thumb_mode = 1; | |
2657 | /* No need to force the alignment, since we will have been | |
2658 | coming from ARM mode, which is word-aligned. */ | |
2659 | record_alignment (now_seg, 1); | |
2660 | } | |
c19d1205 ZW |
2661 | break; |
2662 | ||
2663 | case 32: | |
2664 | if (thumb_mode) | |
2665 | { | |
e74cfd16 | 2666 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
2667 | as_bad (_("selected processor does not support ARM opcodes")); |
2668 | ||
2669 | thumb_mode = 0; | |
2670 | ||
2671 | if (!need_pass_2) | |
2672 | frag_align (2, 0, 0); | |
2673 | ||
2674 | record_alignment (now_seg, 1); | |
2675 | } | |
c19d1205 ZW |
2676 | break; |
2677 | ||
2678 | default: | |
2679 | as_bad (_("invalid instruction size selected (%d)"), width); | |
2680 | } | |
2681 | } | |
2682 | ||
2683 | static void | |
2684 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
2685 | { | |
2686 | opcode_select (32); | |
2687 | demand_empty_rest_of_line (); | |
2688 | } | |
2689 | ||
2690 | static void | |
2691 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
2692 | { | |
2693 | opcode_select (16); | |
2694 | demand_empty_rest_of_line (); | |
2695 | } | |
2696 | ||
2697 | static void | |
2698 | s_code (int unused ATTRIBUTE_UNUSED) | |
2699 | { | |
2700 | int temp; | |
2701 | ||
2702 | temp = get_absolute_expression (); | |
2703 | switch (temp) | |
2704 | { | |
2705 | case 16: | |
2706 | case 32: | |
2707 | opcode_select (temp); | |
2708 | break; | |
2709 | ||
2710 | default: | |
2711 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
2712 | } | |
2713 | } | |
2714 | ||
2715 | static void | |
2716 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
2717 | { | |
2718 | /* If we are not already in thumb mode go into it, EVEN if | |
2719 | the target processor does not support thumb instructions. | |
2720 | This is used by gcc/config/arm/lib1funcs.asm for example | |
2721 | to compile interworking support functions even if the | |
2722 | target processor should not support interworking. */ | |
2723 | if (! thumb_mode) | |
2724 | { | |
2725 | thumb_mode = 2; | |
2726 | record_alignment (now_seg, 1); | |
2727 | } | |
2728 | ||
2729 | demand_empty_rest_of_line (); | |
2730 | } | |
2731 | ||
2732 | static void | |
2733 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
2734 | { | |
2735 | s_thumb (0); | |
2736 | ||
2737 | /* The following label is the name/address of the start of a Thumb function. | |
2738 | We need to know this for the interworking support. */ | |
2739 | label_is_thumb_function_name = TRUE; | |
2740 | } | |
2741 | ||
2742 | /* Perform a .set directive, but also mark the alias as | |
2743 | being a thumb function. */ | |
2744 | ||
2745 | static void | |
2746 | s_thumb_set (int equiv) | |
2747 | { | |
2748 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
2749 | We cannot just call that code as we need to get at the symbol that | |
2750 | is created. */ | |
2751 | char * name; | |
2752 | char delim; | |
2753 | char * end_name; | |
2754 | symbolS * symbolP; | |
2755 | ||
2756 | /* Especial apologies for the random logic: | |
2757 | This just grew, and could be parsed much more simply! | |
2758 | Dean - in haste. */ | |
2759 | name = input_line_pointer; | |
2760 | delim = get_symbol_end (); | |
2761 | end_name = input_line_pointer; | |
2762 | *end_name = delim; | |
2763 | ||
2764 | if (*input_line_pointer != ',') | |
2765 | { | |
2766 | *end_name = 0; | |
2767 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
2768 | *end_name = delim; |
2769 | ignore_rest_of_line (); | |
2770 | return; | |
2771 | } | |
2772 | ||
2773 | input_line_pointer++; | |
2774 | *end_name = 0; | |
2775 | ||
2776 | if (name[0] == '.' && name[1] == '\0') | |
2777 | { | |
2778 | /* XXX - this should not happen to .thumb_set. */ | |
2779 | abort (); | |
2780 | } | |
2781 | ||
2782 | if ((symbolP = symbol_find (name)) == NULL | |
2783 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
2784 | { | |
2785 | #ifndef NO_LISTING | |
2786 | /* When doing symbol listings, play games with dummy fragments living | |
2787 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 2788 | for this symbol. */ |
b99bd4ef NC |
2789 | if (listing & LISTING_SYMBOLS) |
2790 | { | |
2791 | extern struct list_info_struct * listing_tail; | |
21d799b5 | 2792 | fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS)); |
b99bd4ef NC |
2793 | |
2794 | memset (dummy_frag, 0, sizeof (fragS)); | |
2795 | dummy_frag->fr_type = rs_fill; | |
2796 | dummy_frag->line = listing_tail; | |
2797 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
2798 | dummy_frag->fr_symbol = symbolP; | |
2799 | } | |
2800 | else | |
2801 | #endif | |
2802 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
2803 | ||
2804 | #ifdef OBJ_COFF | |
2805 | /* "set" symbols are local unless otherwise specified. */ | |
2806 | SF_SET_LOCAL (symbolP); | |
2807 | #endif /* OBJ_COFF */ | |
2808 | } /* Make a new symbol. */ | |
2809 | ||
2810 | symbol_table_insert (symbolP); | |
2811 | ||
2812 | * end_name = delim; | |
2813 | ||
2814 | if (equiv | |
2815 | && S_IS_DEFINED (symbolP) | |
2816 | && S_GET_SEGMENT (symbolP) != reg_section) | |
2817 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
2818 | ||
2819 | pseudo_set (symbolP); | |
2820 | ||
2821 | demand_empty_rest_of_line (); | |
2822 | ||
c19d1205 | 2823 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
2824 | |
2825 | THUMB_SET_FUNC (symbolP, 1); | |
2826 | ARM_SET_THUMB (symbolP, 1); | |
2827 | #if defined OBJ_ELF || defined OBJ_COFF | |
2828 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2829 | #endif | |
2830 | } | |
2831 | ||
c19d1205 | 2832 | /* Directives: Mode selection. */ |
b99bd4ef | 2833 | |
c19d1205 ZW |
2834 | /* .syntax [unified|divided] - choose the new unified syntax |
2835 | (same for Arm and Thumb encoding, modulo slight differences in what | |
2836 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 2837 | static void |
c19d1205 | 2838 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2839 | { |
c19d1205 ZW |
2840 | char *name, delim; |
2841 | ||
2842 | name = input_line_pointer; | |
2843 | delim = get_symbol_end (); | |
2844 | ||
2845 | if (!strcasecmp (name, "unified")) | |
2846 | unified_syntax = TRUE; | |
2847 | else if (!strcasecmp (name, "divided")) | |
2848 | unified_syntax = FALSE; | |
2849 | else | |
2850 | { | |
2851 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
2852 | return; | |
2853 | } | |
2854 | *input_line_pointer = delim; | |
b99bd4ef NC |
2855 | demand_empty_rest_of_line (); |
2856 | } | |
2857 | ||
c19d1205 ZW |
2858 | /* Directives: sectioning and alignment. */ |
2859 | ||
2860 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
2861 | ||
b99bd4ef | 2862 | static void |
c19d1205 | 2863 | s_align (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2864 | { |
a737bd4d | 2865 | int temp; |
dce323d1 | 2866 | bfd_boolean fill_p; |
c19d1205 ZW |
2867 | long temp_fill; |
2868 | long max_alignment = 15; | |
b99bd4ef NC |
2869 | |
2870 | temp = get_absolute_expression (); | |
c19d1205 ZW |
2871 | if (temp > max_alignment) |
2872 | as_bad (_("alignment too large: %d assumed"), temp = max_alignment); | |
2873 | else if (temp < 0) | |
b99bd4ef | 2874 | { |
c19d1205 ZW |
2875 | as_bad (_("alignment negative. 0 assumed.")); |
2876 | temp = 0; | |
2877 | } | |
b99bd4ef | 2878 | |
c19d1205 ZW |
2879 | if (*input_line_pointer == ',') |
2880 | { | |
2881 | input_line_pointer++; | |
2882 | temp_fill = get_absolute_expression (); | |
dce323d1 | 2883 | fill_p = TRUE; |
b99bd4ef | 2884 | } |
c19d1205 | 2885 | else |
dce323d1 PB |
2886 | { |
2887 | fill_p = FALSE; | |
2888 | temp_fill = 0; | |
2889 | } | |
b99bd4ef | 2890 | |
c19d1205 ZW |
2891 | if (!temp) |
2892 | temp = 2; | |
b99bd4ef | 2893 | |
c19d1205 ZW |
2894 | /* Only make a frag if we HAVE to. */ |
2895 | if (temp && !need_pass_2) | |
dce323d1 PB |
2896 | { |
2897 | if (!fill_p && subseg_text_p (now_seg)) | |
2898 | frag_align_code (temp, 0); | |
2899 | else | |
2900 | frag_align (temp, (int) temp_fill, 0); | |
2901 | } | |
c19d1205 ZW |
2902 | demand_empty_rest_of_line (); |
2903 | ||
2904 | record_alignment (now_seg, temp); | |
b99bd4ef NC |
2905 | } |
2906 | ||
c19d1205 ZW |
2907 | static void |
2908 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 2909 | { |
c19d1205 ZW |
2910 | /* We don't support putting frags in the BSS segment, we fake it by |
2911 | marking in_bss, then looking at s_skip for clues. */ | |
2912 | subseg_set (bss_section, 0); | |
2913 | demand_empty_rest_of_line (); | |
cd000bff DJ |
2914 | |
2915 | #ifdef md_elf_section_change_hook | |
2916 | md_elf_section_change_hook (); | |
2917 | #endif | |
c19d1205 | 2918 | } |
b99bd4ef | 2919 | |
c19d1205 ZW |
2920 | static void |
2921 | s_even (int ignore ATTRIBUTE_UNUSED) | |
2922 | { | |
2923 | /* Never make frag if expect extra pass. */ | |
2924 | if (!need_pass_2) | |
2925 | frag_align (1, 0, 0); | |
b99bd4ef | 2926 | |
c19d1205 | 2927 | record_alignment (now_seg, 1); |
b99bd4ef | 2928 | |
c19d1205 | 2929 | demand_empty_rest_of_line (); |
b99bd4ef NC |
2930 | } |
2931 | ||
c19d1205 | 2932 | /* Directives: Literal pools. */ |
a737bd4d | 2933 | |
c19d1205 ZW |
2934 | static literal_pool * |
2935 | find_literal_pool (void) | |
a737bd4d | 2936 | { |
c19d1205 | 2937 | literal_pool * pool; |
a737bd4d | 2938 | |
c19d1205 | 2939 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 2940 | { |
c19d1205 ZW |
2941 | if (pool->section == now_seg |
2942 | && pool->sub_section == now_subseg) | |
2943 | break; | |
a737bd4d NC |
2944 | } |
2945 | ||
c19d1205 | 2946 | return pool; |
a737bd4d NC |
2947 | } |
2948 | ||
c19d1205 ZW |
2949 | static literal_pool * |
2950 | find_or_make_literal_pool (void) | |
a737bd4d | 2951 | { |
c19d1205 ZW |
2952 | /* Next literal pool ID number. */ |
2953 | static unsigned int latest_pool_num = 1; | |
2954 | literal_pool * pool; | |
a737bd4d | 2955 | |
c19d1205 | 2956 | pool = find_literal_pool (); |
a737bd4d | 2957 | |
c19d1205 | 2958 | if (pool == NULL) |
a737bd4d | 2959 | { |
c19d1205 | 2960 | /* Create a new pool. */ |
21d799b5 | 2961 | pool = (literal_pool *) xmalloc (sizeof (* pool)); |
c19d1205 ZW |
2962 | if (! pool) |
2963 | return NULL; | |
a737bd4d | 2964 | |
c19d1205 ZW |
2965 | pool->next_free_entry = 0; |
2966 | pool->section = now_seg; | |
2967 | pool->sub_section = now_subseg; | |
2968 | pool->next = list_of_pools; | |
2969 | pool->symbol = NULL; | |
2970 | ||
2971 | /* Add it to the list. */ | |
2972 | list_of_pools = pool; | |
a737bd4d | 2973 | } |
a737bd4d | 2974 | |
c19d1205 ZW |
2975 | /* New pools, and emptied pools, will have a NULL symbol. */ |
2976 | if (pool->symbol == NULL) | |
a737bd4d | 2977 | { |
c19d1205 ZW |
2978 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
2979 | (valueT) 0, &zero_address_frag); | |
2980 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
2981 | } |
2982 | ||
c19d1205 ZW |
2983 | /* Done. */ |
2984 | return pool; | |
a737bd4d NC |
2985 | } |
2986 | ||
c19d1205 | 2987 | /* Add the literal in the global 'inst' |
5f4273c7 | 2988 | structure to the relevant literal pool. */ |
b99bd4ef NC |
2989 | |
2990 | static int | |
c19d1205 | 2991 | add_to_lit_pool (void) |
b99bd4ef | 2992 | { |
c19d1205 ZW |
2993 | literal_pool * pool; |
2994 | unsigned int entry; | |
b99bd4ef | 2995 | |
c19d1205 ZW |
2996 | pool = find_or_make_literal_pool (); |
2997 | ||
2998 | /* Check if this literal value is already in the pool. */ | |
2999 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 3000 | { |
c19d1205 ZW |
3001 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) |
3002 | && (inst.reloc.exp.X_op == O_constant) | |
3003 | && (pool->literals[entry].X_add_number | |
3004 | == inst.reloc.exp.X_add_number) | |
3005 | && (pool->literals[entry].X_unsigned | |
3006 | == inst.reloc.exp.X_unsigned)) | |
3007 | break; | |
3008 | ||
3009 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3010 | && (inst.reloc.exp.X_op == O_symbol) | |
3011 | && (pool->literals[entry].X_add_number | |
3012 | == inst.reloc.exp.X_add_number) | |
3013 | && (pool->literals[entry].X_add_symbol | |
3014 | == inst.reloc.exp.X_add_symbol) | |
3015 | && (pool->literals[entry].X_op_symbol | |
3016 | == inst.reloc.exp.X_op_symbol)) | |
3017 | break; | |
b99bd4ef NC |
3018 | } |
3019 | ||
c19d1205 ZW |
3020 | /* Do we need to create a new entry? */ |
3021 | if (entry == pool->next_free_entry) | |
3022 | { | |
3023 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
3024 | { | |
3025 | inst.error = _("literal pool overflow"); | |
3026 | return FAIL; | |
3027 | } | |
3028 | ||
3029 | pool->literals[entry] = inst.reloc.exp; | |
3030 | pool->next_free_entry += 1; | |
3031 | } | |
b99bd4ef | 3032 | |
c19d1205 ZW |
3033 | inst.reloc.exp.X_op = O_symbol; |
3034 | inst.reloc.exp.X_add_number = ((int) entry) * 4; | |
3035 | inst.reloc.exp.X_add_symbol = pool->symbol; | |
b99bd4ef | 3036 | |
c19d1205 | 3037 | return SUCCESS; |
b99bd4ef NC |
3038 | } |
3039 | ||
c19d1205 ZW |
3040 | /* Can't use symbol_new here, so have to create a symbol and then at |
3041 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 3042 | |
c19d1205 ZW |
3043 | static void |
3044 | symbol_locate (symbolS * symbolP, | |
3045 | const char * name, /* It is copied, the caller can modify. */ | |
3046 | segT segment, /* Segment identifier (SEG_<something>). */ | |
3047 | valueT valu, /* Symbol value. */ | |
3048 | fragS * frag) /* Associated fragment. */ | |
3049 | { | |
3050 | unsigned int name_length; | |
3051 | char * preserved_copy_of_name; | |
e16bb312 | 3052 | |
c19d1205 ZW |
3053 | name_length = strlen (name) + 1; /* +1 for \0. */ |
3054 | obstack_grow (¬es, name, name_length); | |
21d799b5 | 3055 | preserved_copy_of_name = (char *) obstack_finish (¬es); |
e16bb312 | 3056 | |
c19d1205 ZW |
3057 | #ifdef tc_canonicalize_symbol_name |
3058 | preserved_copy_of_name = | |
3059 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
3060 | #endif | |
b99bd4ef | 3061 | |
c19d1205 | 3062 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 3063 | |
c19d1205 ZW |
3064 | S_SET_SEGMENT (symbolP, segment); |
3065 | S_SET_VALUE (symbolP, valu); | |
3066 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 3067 | |
c19d1205 | 3068 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 3069 | |
c19d1205 ZW |
3070 | /* Link to end of symbol chain. */ |
3071 | { | |
3072 | extern int symbol_table_frozen; | |
b99bd4ef | 3073 | |
c19d1205 ZW |
3074 | if (symbol_table_frozen) |
3075 | abort (); | |
3076 | } | |
b99bd4ef | 3077 | |
c19d1205 | 3078 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 3079 | |
c19d1205 | 3080 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 3081 | |
c19d1205 ZW |
3082 | #ifdef tc_symbol_new_hook |
3083 | tc_symbol_new_hook (symbolP); | |
3084 | #endif | |
3085 | ||
3086 | #ifdef DEBUG_SYMS | |
3087 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
3088 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
3089 | } |
3090 | ||
b99bd4ef | 3091 | |
c19d1205 ZW |
3092 | static void |
3093 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 3094 | { |
c19d1205 ZW |
3095 | unsigned int entry; |
3096 | literal_pool * pool; | |
3097 | char sym_name[20]; | |
b99bd4ef | 3098 | |
c19d1205 ZW |
3099 | pool = find_literal_pool (); |
3100 | if (pool == NULL | |
3101 | || pool->symbol == NULL | |
3102 | || pool->next_free_entry == 0) | |
3103 | return; | |
b99bd4ef | 3104 | |
c19d1205 | 3105 | mapping_state (MAP_DATA); |
b99bd4ef | 3106 | |
c19d1205 ZW |
3107 | /* Align pool as you have word accesses. |
3108 | Only make a frag if we have to. */ | |
3109 | if (!need_pass_2) | |
3110 | frag_align (2, 0, 0); | |
b99bd4ef | 3111 | |
c19d1205 | 3112 | record_alignment (now_seg, 2); |
b99bd4ef | 3113 | |
c19d1205 | 3114 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 3115 | |
c19d1205 ZW |
3116 | symbol_locate (pool->symbol, sym_name, now_seg, |
3117 | (valueT) frag_now_fix (), frag_now); | |
3118 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 3119 | |
c19d1205 | 3120 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 3121 | |
c19d1205 ZW |
3122 | #if defined OBJ_COFF || defined OBJ_ELF |
3123 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
3124 | #endif | |
6c43fab6 | 3125 | |
c19d1205 ZW |
3126 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
3127 | /* First output the expression in the instruction to the pool. */ | |
3128 | emit_expr (&(pool->literals[entry]), 4); /* .word */ | |
b99bd4ef | 3129 | |
c19d1205 ZW |
3130 | /* Mark the pool as empty. */ |
3131 | pool->next_free_entry = 0; | |
3132 | pool->symbol = NULL; | |
b99bd4ef NC |
3133 | } |
3134 | ||
c19d1205 ZW |
3135 | #ifdef OBJ_ELF |
3136 | /* Forward declarations for functions below, in the MD interface | |
3137 | section. */ | |
3138 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
3139 | static valueT create_unwind_entry (int); | |
3140 | static void start_unwind_section (const segT, int); | |
3141 | static void add_unwind_opcode (valueT, int); | |
3142 | static void flush_pending_unwind (void); | |
b99bd4ef | 3143 | |
c19d1205 | 3144 | /* Directives: Data. */ |
b99bd4ef | 3145 | |
c19d1205 ZW |
3146 | static void |
3147 | s_arm_elf_cons (int nbytes) | |
3148 | { | |
3149 | expressionS exp; | |
b99bd4ef | 3150 | |
c19d1205 ZW |
3151 | #ifdef md_flush_pending_output |
3152 | md_flush_pending_output (); | |
3153 | #endif | |
b99bd4ef | 3154 | |
c19d1205 | 3155 | if (is_it_end_of_statement ()) |
b99bd4ef | 3156 | { |
c19d1205 ZW |
3157 | demand_empty_rest_of_line (); |
3158 | return; | |
b99bd4ef NC |
3159 | } |
3160 | ||
c19d1205 ZW |
3161 | #ifdef md_cons_align |
3162 | md_cons_align (nbytes); | |
3163 | #endif | |
b99bd4ef | 3164 | |
c19d1205 ZW |
3165 | mapping_state (MAP_DATA); |
3166 | do | |
b99bd4ef | 3167 | { |
c19d1205 ZW |
3168 | int reloc; |
3169 | char *base = input_line_pointer; | |
b99bd4ef | 3170 | |
c19d1205 | 3171 | expression (& exp); |
b99bd4ef | 3172 | |
c19d1205 ZW |
3173 | if (exp.X_op != O_symbol) |
3174 | emit_expr (&exp, (unsigned int) nbytes); | |
3175 | else | |
3176 | { | |
3177 | char *before_reloc = input_line_pointer; | |
3178 | reloc = parse_reloc (&input_line_pointer); | |
3179 | if (reloc == -1) | |
3180 | { | |
3181 | as_bad (_("unrecognized relocation suffix")); | |
3182 | ignore_rest_of_line (); | |
3183 | return; | |
3184 | } | |
3185 | else if (reloc == BFD_RELOC_UNUSED) | |
3186 | emit_expr (&exp, (unsigned int) nbytes); | |
3187 | else | |
3188 | { | |
21d799b5 NC |
3189 | reloc_howto_type *howto = (reloc_howto_type *) |
3190 | bfd_reloc_type_lookup (stdoutput, | |
3191 | (bfd_reloc_code_real_type) reloc); | |
c19d1205 | 3192 | int size = bfd_get_reloc_size (howto); |
b99bd4ef | 3193 | |
2fc8bdac ZW |
3194 | if (reloc == BFD_RELOC_ARM_PLT32) |
3195 | { | |
3196 | as_bad (_("(plt) is only valid on branch targets")); | |
3197 | reloc = BFD_RELOC_UNUSED; | |
3198 | size = 0; | |
3199 | } | |
3200 | ||
c19d1205 | 3201 | if (size > nbytes) |
2fc8bdac | 3202 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
3203 | howto->name, nbytes); |
3204 | else | |
3205 | { | |
3206 | /* We've parsed an expression stopping at O_symbol. | |
3207 | But there may be more expression left now that we | |
3208 | have parsed the relocation marker. Parse it again. | |
3209 | XXX Surely there is a cleaner way to do this. */ | |
3210 | char *p = input_line_pointer; | |
3211 | int offset; | |
21d799b5 | 3212 | char *save_buf = (char *) alloca (input_line_pointer - base); |
c19d1205 ZW |
3213 | memcpy (save_buf, base, input_line_pointer - base); |
3214 | memmove (base + (input_line_pointer - before_reloc), | |
3215 | base, before_reloc - base); | |
3216 | ||
3217 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
3218 | expression (&exp); | |
3219 | memcpy (base, save_buf, p - base); | |
3220 | ||
3221 | offset = nbytes - size; | |
3222 | p = frag_more ((int) nbytes); | |
3223 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, | |
21d799b5 | 3224 | size, &exp, 0, (enum bfd_reloc_code_real) reloc); |
c19d1205 ZW |
3225 | } |
3226 | } | |
3227 | } | |
b99bd4ef | 3228 | } |
c19d1205 | 3229 | while (*input_line_pointer++ == ','); |
b99bd4ef | 3230 | |
c19d1205 ZW |
3231 | /* Put terminator back into stream. */ |
3232 | input_line_pointer --; | |
3233 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
3234 | } |
3235 | ||
c921be7d NC |
3236 | /* Emit an expression containing a 32-bit thumb instruction. |
3237 | Implementation based on put_thumb32_insn. */ | |
3238 | ||
3239 | static void | |
3240 | emit_thumb32_expr (expressionS * exp) | |
3241 | { | |
3242 | expressionS exp_high = *exp; | |
3243 | ||
3244 | exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; | |
3245 | emit_expr (& exp_high, (unsigned int) THUMB_SIZE); | |
3246 | exp->X_add_number &= 0xffff; | |
3247 | emit_expr (exp, (unsigned int) THUMB_SIZE); | |
3248 | } | |
3249 | ||
3250 | /* Guess the instruction size based on the opcode. */ | |
3251 | ||
3252 | static int | |
3253 | thumb_insn_size (int opcode) | |
3254 | { | |
3255 | if ((unsigned int) opcode < 0xe800u) | |
3256 | return 2; | |
3257 | else if ((unsigned int) opcode >= 0xe8000000u) | |
3258 | return 4; | |
3259 | else | |
3260 | return 0; | |
3261 | } | |
3262 | ||
3263 | static bfd_boolean | |
3264 | emit_insn (expressionS *exp, int nbytes) | |
3265 | { | |
3266 | int size = 0; | |
3267 | ||
3268 | if (exp->X_op == O_constant) | |
3269 | { | |
3270 | size = nbytes; | |
3271 | ||
3272 | if (size == 0) | |
3273 | size = thumb_insn_size (exp->X_add_number); | |
3274 | ||
3275 | if (size != 0) | |
3276 | { | |
3277 | if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) | |
3278 | { | |
3279 | as_bad (_(".inst.n operand too big. "\ | |
3280 | "Use .inst.w instead")); | |
3281 | size = 0; | |
3282 | } | |
3283 | else | |
3284 | { | |
3285 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
3286 | set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0); | |
3287 | else | |
3288 | set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); | |
3289 | ||
3290 | if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) | |
3291 | emit_thumb32_expr (exp); | |
3292 | else | |
3293 | emit_expr (exp, (unsigned int) size); | |
3294 | ||
3295 | it_fsm_post_encode (); | |
3296 | } | |
3297 | } | |
3298 | else | |
3299 | as_bad (_("cannot determine Thumb instruction size. " \ | |
3300 | "Use .inst.n/.inst.w instead")); | |
3301 | } | |
3302 | else | |
3303 | as_bad (_("constant expression required")); | |
3304 | ||
3305 | return (size != 0); | |
3306 | } | |
3307 | ||
3308 | /* Like s_arm_elf_cons but do not use md_cons_align and | |
3309 | set the mapping state to MAP_ARM/MAP_THUMB. */ | |
3310 | ||
3311 | static void | |
3312 | s_arm_elf_inst (int nbytes) | |
3313 | { | |
3314 | if (is_it_end_of_statement ()) | |
3315 | { | |
3316 | demand_empty_rest_of_line (); | |
3317 | return; | |
3318 | } | |
3319 | ||
3320 | /* Calling mapping_state () here will not change ARM/THUMB, | |
3321 | but will ensure not to be in DATA state. */ | |
3322 | ||
3323 | if (thumb_mode) | |
3324 | mapping_state (MAP_THUMB); | |
3325 | else | |
3326 | { | |
3327 | if (nbytes != 0) | |
3328 | { | |
3329 | as_bad (_("width suffixes are invalid in ARM mode")); | |
3330 | ignore_rest_of_line (); | |
3331 | return; | |
3332 | } | |
3333 | ||
3334 | nbytes = 4; | |
3335 | ||
3336 | mapping_state (MAP_ARM); | |
3337 | } | |
3338 | ||
3339 | do | |
3340 | { | |
3341 | expressionS exp; | |
3342 | ||
3343 | expression (& exp); | |
3344 | ||
3345 | if (! emit_insn (& exp, nbytes)) | |
3346 | { | |
3347 | ignore_rest_of_line (); | |
3348 | return; | |
3349 | } | |
3350 | } | |
3351 | while (*input_line_pointer++ == ','); | |
3352 | ||
3353 | /* Put terminator back into stream. */ | |
3354 | input_line_pointer --; | |
3355 | demand_empty_rest_of_line (); | |
3356 | } | |
b99bd4ef | 3357 | |
c19d1205 | 3358 | /* Parse a .rel31 directive. */ |
b99bd4ef | 3359 | |
c19d1205 ZW |
3360 | static void |
3361 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
3362 | { | |
3363 | expressionS exp; | |
3364 | char *p; | |
3365 | valueT highbit; | |
b99bd4ef | 3366 | |
c19d1205 ZW |
3367 | highbit = 0; |
3368 | if (*input_line_pointer == '1') | |
3369 | highbit = 0x80000000; | |
3370 | else if (*input_line_pointer != '0') | |
3371 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 3372 | |
c19d1205 ZW |
3373 | input_line_pointer++; |
3374 | if (*input_line_pointer != ',') | |
3375 | as_bad (_("missing comma")); | |
3376 | input_line_pointer++; | |
b99bd4ef | 3377 | |
c19d1205 ZW |
3378 | #ifdef md_flush_pending_output |
3379 | md_flush_pending_output (); | |
3380 | #endif | |
b99bd4ef | 3381 | |
c19d1205 ZW |
3382 | #ifdef md_cons_align |
3383 | md_cons_align (4); | |
3384 | #endif | |
b99bd4ef | 3385 | |
c19d1205 | 3386 | mapping_state (MAP_DATA); |
b99bd4ef | 3387 | |
c19d1205 | 3388 | expression (&exp); |
b99bd4ef | 3389 | |
c19d1205 ZW |
3390 | p = frag_more (4); |
3391 | md_number_to_chars (p, highbit, 4); | |
3392 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
3393 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 3394 | |
c19d1205 | 3395 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3396 | } |
3397 | ||
c19d1205 | 3398 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 3399 | |
c19d1205 | 3400 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 3401 | |
c19d1205 ZW |
3402 | static void |
3403 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
3404 | { | |
3405 | demand_empty_rest_of_line (); | |
921e5f0a PB |
3406 | if (unwind.proc_start) |
3407 | { | |
c921be7d | 3408 | as_bad (_("duplicate .fnstart directive")); |
921e5f0a PB |
3409 | return; |
3410 | } | |
3411 | ||
c19d1205 ZW |
3412 | /* Mark the start of the function. */ |
3413 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 3414 | |
c19d1205 ZW |
3415 | /* Reset the rest of the unwind info. */ |
3416 | unwind.opcode_count = 0; | |
3417 | unwind.table_entry = NULL; | |
3418 | unwind.personality_routine = NULL; | |
3419 | unwind.personality_index = -1; | |
3420 | unwind.frame_size = 0; | |
3421 | unwind.fp_offset = 0; | |
fdfde340 | 3422 | unwind.fp_reg = REG_SP; |
c19d1205 ZW |
3423 | unwind.fp_used = 0; |
3424 | unwind.sp_restored = 0; | |
3425 | } | |
b99bd4ef | 3426 | |
b99bd4ef | 3427 | |
c19d1205 ZW |
3428 | /* Parse a handlerdata directive. Creates the exception handling table entry |
3429 | for the function. */ | |
b99bd4ef | 3430 | |
c19d1205 ZW |
3431 | static void |
3432 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
3433 | { | |
3434 | demand_empty_rest_of_line (); | |
921e5f0a | 3435 | if (!unwind.proc_start) |
c921be7d | 3436 | as_bad (MISSING_FNSTART); |
921e5f0a | 3437 | |
c19d1205 | 3438 | if (unwind.table_entry) |
6decc662 | 3439 | as_bad (_("duplicate .handlerdata directive")); |
f02232aa | 3440 | |
c19d1205 ZW |
3441 | create_unwind_entry (1); |
3442 | } | |
a737bd4d | 3443 | |
c19d1205 | 3444 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 3445 | |
c19d1205 ZW |
3446 | static void |
3447 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
3448 | { | |
3449 | long where; | |
3450 | char *ptr; | |
3451 | valueT val; | |
940b5ce0 | 3452 | unsigned int marked_pr_dependency; |
f02232aa | 3453 | |
c19d1205 | 3454 | demand_empty_rest_of_line (); |
f02232aa | 3455 | |
921e5f0a PB |
3456 | if (!unwind.proc_start) |
3457 | { | |
c921be7d | 3458 | as_bad (_(".fnend directive without .fnstart")); |
921e5f0a PB |
3459 | return; |
3460 | } | |
3461 | ||
c19d1205 ZW |
3462 | /* Add eh table entry. */ |
3463 | if (unwind.table_entry == NULL) | |
3464 | val = create_unwind_entry (0); | |
3465 | else | |
3466 | val = 0; | |
f02232aa | 3467 | |
c19d1205 ZW |
3468 | /* Add index table entry. This is two words. */ |
3469 | start_unwind_section (unwind.saved_seg, 1); | |
3470 | frag_align (2, 0, 0); | |
3471 | record_alignment (now_seg, 2); | |
b99bd4ef | 3472 | |
c19d1205 ZW |
3473 | ptr = frag_more (8); |
3474 | where = frag_now_fix () - 8; | |
f02232aa | 3475 | |
c19d1205 ZW |
3476 | /* Self relative offset of the function start. */ |
3477 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
3478 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3479 | |
c19d1205 ZW |
3480 | /* Indicate dependency on EHABI-defined personality routines to the |
3481 | linker, if it hasn't been done already. */ | |
940b5ce0 DJ |
3482 | marked_pr_dependency |
3483 | = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; | |
c19d1205 ZW |
3484 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 |
3485 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
3486 | { | |
5f4273c7 NC |
3487 | static const char *const name[] = |
3488 | { | |
3489 | "__aeabi_unwind_cpp_pr0", | |
3490 | "__aeabi_unwind_cpp_pr1", | |
3491 | "__aeabi_unwind_cpp_pr2" | |
3492 | }; | |
c19d1205 ZW |
3493 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); |
3494 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
c19d1205 | 3495 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency |
940b5ce0 | 3496 | |= 1 << unwind.personality_index; |
c19d1205 | 3497 | } |
f02232aa | 3498 | |
c19d1205 ZW |
3499 | if (val) |
3500 | /* Inline exception table entry. */ | |
3501 | md_number_to_chars (ptr + 4, val, 4); | |
3502 | else | |
3503 | /* Self relative offset of the table entry. */ | |
3504 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
3505 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3506 | |
c19d1205 ZW |
3507 | /* Restore the original section. */ |
3508 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
921e5f0a PB |
3509 | |
3510 | unwind.proc_start = NULL; | |
c19d1205 | 3511 | } |
f02232aa | 3512 | |
f02232aa | 3513 | |
c19d1205 | 3514 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 3515 | |
c19d1205 ZW |
3516 | static void |
3517 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
3518 | { | |
3519 | demand_empty_rest_of_line (); | |
921e5f0a | 3520 | if (!unwind.proc_start) |
c921be7d | 3521 | as_bad (MISSING_FNSTART); |
921e5f0a | 3522 | |
c19d1205 ZW |
3523 | if (unwind.personality_routine || unwind.personality_index != -1) |
3524 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 3525 | |
c19d1205 ZW |
3526 | unwind.personality_index = -2; |
3527 | } | |
b99bd4ef | 3528 | |
b99bd4ef | 3529 | |
c19d1205 | 3530 | /* Parse a personalityindex directive. */ |
b99bd4ef | 3531 | |
c19d1205 ZW |
3532 | static void |
3533 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
3534 | { | |
3535 | expressionS exp; | |
b99bd4ef | 3536 | |
921e5f0a | 3537 | if (!unwind.proc_start) |
c921be7d | 3538 | as_bad (MISSING_FNSTART); |
921e5f0a | 3539 | |
c19d1205 ZW |
3540 | if (unwind.personality_routine || unwind.personality_index != -1) |
3541 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 3542 | |
c19d1205 | 3543 | expression (&exp); |
b99bd4ef | 3544 | |
c19d1205 ZW |
3545 | if (exp.X_op != O_constant |
3546 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 3547 | { |
c19d1205 ZW |
3548 | as_bad (_("bad personality routine number")); |
3549 | ignore_rest_of_line (); | |
3550 | return; | |
b99bd4ef NC |
3551 | } |
3552 | ||
c19d1205 | 3553 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 3554 | |
c19d1205 ZW |
3555 | demand_empty_rest_of_line (); |
3556 | } | |
e16bb312 | 3557 | |
e16bb312 | 3558 | |
c19d1205 | 3559 | /* Parse a personality directive. */ |
e16bb312 | 3560 | |
c19d1205 ZW |
3561 | static void |
3562 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
3563 | { | |
3564 | char *name, *p, c; | |
a737bd4d | 3565 | |
921e5f0a | 3566 | if (!unwind.proc_start) |
c921be7d | 3567 | as_bad (MISSING_FNSTART); |
921e5f0a | 3568 | |
c19d1205 ZW |
3569 | if (unwind.personality_routine || unwind.personality_index != -1) |
3570 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 3571 | |
c19d1205 ZW |
3572 | name = input_line_pointer; |
3573 | c = get_symbol_end (); | |
3574 | p = input_line_pointer; | |
3575 | unwind.personality_routine = symbol_find_or_make (name); | |
3576 | *p = c; | |
3577 | demand_empty_rest_of_line (); | |
3578 | } | |
e16bb312 | 3579 | |
e16bb312 | 3580 | |
c19d1205 | 3581 | /* Parse a directive saving core registers. */ |
e16bb312 | 3582 | |
c19d1205 ZW |
3583 | static void |
3584 | s_arm_unwind_save_core (void) | |
e16bb312 | 3585 | { |
c19d1205 ZW |
3586 | valueT op; |
3587 | long range; | |
3588 | int n; | |
e16bb312 | 3589 | |
c19d1205 ZW |
3590 | range = parse_reg_list (&input_line_pointer); |
3591 | if (range == FAIL) | |
e16bb312 | 3592 | { |
c19d1205 ZW |
3593 | as_bad (_("expected register list")); |
3594 | ignore_rest_of_line (); | |
3595 | return; | |
3596 | } | |
e16bb312 | 3597 | |
c19d1205 | 3598 | demand_empty_rest_of_line (); |
e16bb312 | 3599 | |
c19d1205 ZW |
3600 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
3601 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
3602 | ip because it is clobbered by calls. */ | |
3603 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
3604 | && (range & 0x3000) == 0x1000) | |
3605 | { | |
3606 | unwind.opcode_count--; | |
3607 | unwind.sp_restored = 0; | |
3608 | range = (range | 0x2000) & ~0x1000; | |
3609 | unwind.pending_offset = 0; | |
3610 | } | |
e16bb312 | 3611 | |
01ae4198 DJ |
3612 | /* Pop r4-r15. */ |
3613 | if (range & 0xfff0) | |
c19d1205 | 3614 | { |
01ae4198 DJ |
3615 | /* See if we can use the short opcodes. These pop a block of up to 8 |
3616 | registers starting with r4, plus maybe r14. */ | |
3617 | for (n = 0; n < 8; n++) | |
3618 | { | |
3619 | /* Break at the first non-saved register. */ | |
3620 | if ((range & (1 << (n + 4))) == 0) | |
3621 | break; | |
3622 | } | |
3623 | /* See if there are any other bits set. */ | |
3624 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
3625 | { | |
3626 | /* Use the long form. */ | |
3627 | op = 0x8000 | ((range >> 4) & 0xfff); | |
3628 | add_unwind_opcode (op, 2); | |
3629 | } | |
0dd132b6 | 3630 | else |
01ae4198 DJ |
3631 | { |
3632 | /* Use the short form. */ | |
3633 | if (range & 0x4000) | |
3634 | op = 0xa8; /* Pop r14. */ | |
3635 | else | |
3636 | op = 0xa0; /* Do not pop r14. */ | |
3637 | op |= (n - 1); | |
3638 | add_unwind_opcode (op, 1); | |
3639 | } | |
c19d1205 | 3640 | } |
0dd132b6 | 3641 | |
c19d1205 ZW |
3642 | /* Pop r0-r3. */ |
3643 | if (range & 0xf) | |
3644 | { | |
3645 | op = 0xb100 | (range & 0xf); | |
3646 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
3647 | } |
3648 | ||
c19d1205 ZW |
3649 | /* Record the number of bytes pushed. */ |
3650 | for (n = 0; n < 16; n++) | |
3651 | { | |
3652 | if (range & (1 << n)) | |
3653 | unwind.frame_size += 4; | |
3654 | } | |
0dd132b6 NC |
3655 | } |
3656 | ||
c19d1205 ZW |
3657 | |
3658 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
3659 | |
3660 | static void | |
c19d1205 | 3661 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 3662 | { |
c19d1205 ZW |
3663 | expressionS exp; |
3664 | int num_regs; | |
3665 | valueT op; | |
b99bd4ef | 3666 | |
c19d1205 ZW |
3667 | /* Get Number of registers to transfer. */ |
3668 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
3669 | expression (&exp); | |
3670 | else | |
3671 | exp.X_op = O_illegal; | |
b99bd4ef | 3672 | |
c19d1205 | 3673 | if (exp.X_op != O_constant) |
b99bd4ef | 3674 | { |
c19d1205 ZW |
3675 | as_bad (_("expected , <constant>")); |
3676 | ignore_rest_of_line (); | |
b99bd4ef NC |
3677 | return; |
3678 | } | |
3679 | ||
c19d1205 ZW |
3680 | num_regs = exp.X_add_number; |
3681 | ||
3682 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 3683 | { |
c19d1205 ZW |
3684 | as_bad (_("number of registers must be in the range [1:4]")); |
3685 | ignore_rest_of_line (); | |
b99bd4ef NC |
3686 | return; |
3687 | } | |
3688 | ||
c19d1205 | 3689 | demand_empty_rest_of_line (); |
b99bd4ef | 3690 | |
c19d1205 ZW |
3691 | if (reg == 4) |
3692 | { | |
3693 | /* Short form. */ | |
3694 | op = 0xb4 | (num_regs - 1); | |
3695 | add_unwind_opcode (op, 1); | |
3696 | } | |
b99bd4ef NC |
3697 | else |
3698 | { | |
c19d1205 ZW |
3699 | /* Long form. */ |
3700 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
3701 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3702 | } |
c19d1205 | 3703 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
3704 | } |
3705 | ||
c19d1205 | 3706 | |
fa073d69 MS |
3707 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
3708 | ||
3709 | static void | |
3710 | s_arm_unwind_save_vfp_armv6 (void) | |
3711 | { | |
3712 | int count; | |
3713 | unsigned int start; | |
3714 | valueT op; | |
3715 | int num_vfpv3_regs = 0; | |
3716 | int num_regs_below_16; | |
3717 | ||
3718 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); | |
3719 | if (count == FAIL) | |
3720 | { | |
3721 | as_bad (_("expected register list")); | |
3722 | ignore_rest_of_line (); | |
3723 | return; | |
3724 | } | |
3725 | ||
3726 | demand_empty_rest_of_line (); | |
3727 | ||
3728 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather | |
3729 | than FSTMX/FLDMX-style ones). */ | |
3730 | ||
3731 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ | |
3732 | if (start >= 16) | |
3733 | num_vfpv3_regs = count; | |
3734 | else if (start + count > 16) | |
3735 | num_vfpv3_regs = start + count - 16; | |
3736 | ||
3737 | if (num_vfpv3_regs > 0) | |
3738 | { | |
3739 | int start_offset = start > 16 ? start - 16 : 0; | |
3740 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); | |
3741 | add_unwind_opcode (op, 2); | |
3742 | } | |
3743 | ||
3744 | /* Generate opcode for registers numbered in the range 0 .. 15. */ | |
3745 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; | |
9c2799c2 | 3746 | gas_assert (num_regs_below_16 + num_vfpv3_regs == count); |
fa073d69 MS |
3747 | if (num_regs_below_16 > 0) |
3748 | { | |
3749 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); | |
3750 | add_unwind_opcode (op, 2); | |
3751 | } | |
3752 | ||
3753 | unwind.frame_size += count * 8; | |
3754 | } | |
3755 | ||
3756 | ||
3757 | /* Parse a directive saving VFP registers for pre-ARMv6. */ | |
b99bd4ef NC |
3758 | |
3759 | static void | |
c19d1205 | 3760 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 3761 | { |
c19d1205 | 3762 | int count; |
ca3f61f7 | 3763 | unsigned int reg; |
c19d1205 | 3764 | valueT op; |
b99bd4ef | 3765 | |
5287ad62 | 3766 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); |
c19d1205 | 3767 | if (count == FAIL) |
b99bd4ef | 3768 | { |
c19d1205 ZW |
3769 | as_bad (_("expected register list")); |
3770 | ignore_rest_of_line (); | |
b99bd4ef NC |
3771 | return; |
3772 | } | |
3773 | ||
c19d1205 | 3774 | demand_empty_rest_of_line (); |
b99bd4ef | 3775 | |
c19d1205 | 3776 | if (reg == 8) |
b99bd4ef | 3777 | { |
c19d1205 ZW |
3778 | /* Short form. */ |
3779 | op = 0xb8 | (count - 1); | |
3780 | add_unwind_opcode (op, 1); | |
b99bd4ef | 3781 | } |
c19d1205 | 3782 | else |
b99bd4ef | 3783 | { |
c19d1205 ZW |
3784 | /* Long form. */ |
3785 | op = 0xb300 | (reg << 4) | (count - 1); | |
3786 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3787 | } |
c19d1205 ZW |
3788 | unwind.frame_size += count * 8 + 4; |
3789 | } | |
b99bd4ef | 3790 | |
b99bd4ef | 3791 | |
c19d1205 ZW |
3792 | /* Parse a directive saving iWMMXt data registers. */ |
3793 | ||
3794 | static void | |
3795 | s_arm_unwind_save_mmxwr (void) | |
3796 | { | |
3797 | int reg; | |
3798 | int hi_reg; | |
3799 | int i; | |
3800 | unsigned mask = 0; | |
3801 | valueT op; | |
b99bd4ef | 3802 | |
c19d1205 ZW |
3803 | if (*input_line_pointer == '{') |
3804 | input_line_pointer++; | |
b99bd4ef | 3805 | |
c19d1205 | 3806 | do |
b99bd4ef | 3807 | { |
dcbf9037 | 3808 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 3809 | |
c19d1205 | 3810 | if (reg == FAIL) |
b99bd4ef | 3811 | { |
9b7132d3 | 3812 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 | 3813 | goto error; |
b99bd4ef NC |
3814 | } |
3815 | ||
c19d1205 ZW |
3816 | if (mask >> reg) |
3817 | as_tsktsk (_("register list not in ascending order")); | |
3818 | mask |= 1 << reg; | |
b99bd4ef | 3819 | |
c19d1205 ZW |
3820 | if (*input_line_pointer == '-') |
3821 | { | |
3822 | input_line_pointer++; | |
dcbf9037 | 3823 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
c19d1205 ZW |
3824 | if (hi_reg == FAIL) |
3825 | { | |
9b7132d3 | 3826 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 ZW |
3827 | goto error; |
3828 | } | |
3829 | else if (reg >= hi_reg) | |
3830 | { | |
3831 | as_bad (_("bad register range")); | |
3832 | goto error; | |
3833 | } | |
3834 | for (; reg < hi_reg; reg++) | |
3835 | mask |= 1 << reg; | |
3836 | } | |
3837 | } | |
3838 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 3839 | |
c19d1205 ZW |
3840 | if (*input_line_pointer == '}') |
3841 | input_line_pointer++; | |
b99bd4ef | 3842 | |
c19d1205 | 3843 | demand_empty_rest_of_line (); |
b99bd4ef | 3844 | |
708587a4 | 3845 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
3846 | the list. */ |
3847 | flush_pending_unwind (); | |
b99bd4ef | 3848 | |
c19d1205 | 3849 | for (i = 0; i < 16; i++) |
b99bd4ef | 3850 | { |
c19d1205 ZW |
3851 | if (mask & (1 << i)) |
3852 | unwind.frame_size += 8; | |
b99bd4ef NC |
3853 | } |
3854 | ||
c19d1205 ZW |
3855 | /* Attempt to combine with a previous opcode. We do this because gcc |
3856 | likes to output separate unwind directives for a single block of | |
3857 | registers. */ | |
3858 | if (unwind.opcode_count > 0) | |
b99bd4ef | 3859 | { |
c19d1205 ZW |
3860 | i = unwind.opcodes[unwind.opcode_count - 1]; |
3861 | if ((i & 0xf8) == 0xc0) | |
3862 | { | |
3863 | i &= 7; | |
3864 | /* Only merge if the blocks are contiguous. */ | |
3865 | if (i < 6) | |
3866 | { | |
3867 | if ((mask & 0xfe00) == (1 << 9)) | |
3868 | { | |
3869 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
3870 | unwind.opcode_count--; | |
3871 | } | |
3872 | } | |
3873 | else if (i == 6 && unwind.opcode_count >= 2) | |
3874 | { | |
3875 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
3876 | reg = i >> 4; | |
3877 | i &= 0xf; | |
b99bd4ef | 3878 | |
c19d1205 ZW |
3879 | op = 0xffff << (reg - 1); |
3880 | if (reg > 0 | |
87a1fd79 | 3881 | && ((mask & op) == (1u << (reg - 1)))) |
c19d1205 ZW |
3882 | { |
3883 | op = (1 << (reg + i + 1)) - 1; | |
3884 | op &= ~((1 << reg) - 1); | |
3885 | mask |= op; | |
3886 | unwind.opcode_count -= 2; | |
3887 | } | |
3888 | } | |
3889 | } | |
b99bd4ef NC |
3890 | } |
3891 | ||
c19d1205 ZW |
3892 | hi_reg = 15; |
3893 | /* We want to generate opcodes in the order the registers have been | |
3894 | saved, ie. descending order. */ | |
3895 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 3896 | { |
c19d1205 ZW |
3897 | /* Save registers in blocks. */ |
3898 | if (reg < 0 | |
3899 | || !(mask & (1 << reg))) | |
3900 | { | |
3901 | /* We found an unsaved reg. Generate opcodes to save the | |
5f4273c7 | 3902 | preceding block. */ |
c19d1205 ZW |
3903 | if (reg != hi_reg) |
3904 | { | |
3905 | if (reg == 9) | |
3906 | { | |
3907 | /* Short form. */ | |
3908 | op = 0xc0 | (hi_reg - 10); | |
3909 | add_unwind_opcode (op, 1); | |
3910 | } | |
3911 | else | |
3912 | { | |
3913 | /* Long form. */ | |
3914 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
3915 | add_unwind_opcode (op, 2); | |
3916 | } | |
3917 | } | |
3918 | hi_reg = reg - 1; | |
3919 | } | |
b99bd4ef NC |
3920 | } |
3921 | ||
c19d1205 ZW |
3922 | return; |
3923 | error: | |
3924 | ignore_rest_of_line (); | |
b99bd4ef NC |
3925 | } |
3926 | ||
3927 | static void | |
c19d1205 | 3928 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 3929 | { |
c19d1205 ZW |
3930 | int reg; |
3931 | int hi_reg; | |
3932 | unsigned mask = 0; | |
3933 | valueT op; | |
b99bd4ef | 3934 | |
c19d1205 ZW |
3935 | if (*input_line_pointer == '{') |
3936 | input_line_pointer++; | |
b99bd4ef | 3937 | |
c19d1205 | 3938 | do |
b99bd4ef | 3939 | { |
dcbf9037 | 3940 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 3941 | |
c19d1205 ZW |
3942 | if (reg == FAIL) |
3943 | { | |
9b7132d3 | 3944 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
3945 | goto error; |
3946 | } | |
b99bd4ef | 3947 | |
c19d1205 ZW |
3948 | reg -= 8; |
3949 | if (mask >> reg) | |
3950 | as_tsktsk (_("register list not in ascending order")); | |
3951 | mask |= 1 << reg; | |
b99bd4ef | 3952 | |
c19d1205 ZW |
3953 | if (*input_line_pointer == '-') |
3954 | { | |
3955 | input_line_pointer++; | |
dcbf9037 | 3956 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
c19d1205 ZW |
3957 | if (hi_reg == FAIL) |
3958 | { | |
9b7132d3 | 3959 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
3960 | goto error; |
3961 | } | |
3962 | else if (reg >= hi_reg) | |
3963 | { | |
3964 | as_bad (_("bad register range")); | |
3965 | goto error; | |
3966 | } | |
3967 | for (; reg < hi_reg; reg++) | |
3968 | mask |= 1 << reg; | |
3969 | } | |
b99bd4ef | 3970 | } |
c19d1205 | 3971 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 3972 | |
c19d1205 ZW |
3973 | if (*input_line_pointer == '}') |
3974 | input_line_pointer++; | |
b99bd4ef | 3975 | |
c19d1205 ZW |
3976 | demand_empty_rest_of_line (); |
3977 | ||
708587a4 | 3978 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
3979 | the list. */ |
3980 | flush_pending_unwind (); | |
b99bd4ef | 3981 | |
c19d1205 | 3982 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 3983 | { |
c19d1205 ZW |
3984 | if (mask & (1 << reg)) |
3985 | unwind.frame_size += 4; | |
b99bd4ef | 3986 | } |
c19d1205 ZW |
3987 | op = 0xc700 | mask; |
3988 | add_unwind_opcode (op, 2); | |
3989 | return; | |
3990 | error: | |
3991 | ignore_rest_of_line (); | |
b99bd4ef NC |
3992 | } |
3993 | ||
c19d1205 | 3994 | |
fa073d69 MS |
3995 | /* Parse an unwind_save directive. |
3996 | If the argument is non-zero, this is a .vsave directive. */ | |
c19d1205 | 3997 | |
b99bd4ef | 3998 | static void |
fa073d69 | 3999 | s_arm_unwind_save (int arch_v6) |
b99bd4ef | 4000 | { |
c19d1205 ZW |
4001 | char *peek; |
4002 | struct reg_entry *reg; | |
4003 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 4004 | |
921e5f0a | 4005 | if (!unwind.proc_start) |
c921be7d | 4006 | as_bad (MISSING_FNSTART); |
921e5f0a | 4007 | |
c19d1205 ZW |
4008 | /* Figure out what sort of save we have. */ |
4009 | peek = input_line_pointer; | |
b99bd4ef | 4010 | |
c19d1205 | 4011 | if (*peek == '{') |
b99bd4ef | 4012 | { |
c19d1205 ZW |
4013 | had_brace = TRUE; |
4014 | peek++; | |
b99bd4ef NC |
4015 | } |
4016 | ||
c19d1205 | 4017 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 4018 | |
c19d1205 | 4019 | if (!reg) |
b99bd4ef | 4020 | { |
c19d1205 ZW |
4021 | as_bad (_("register expected")); |
4022 | ignore_rest_of_line (); | |
b99bd4ef NC |
4023 | return; |
4024 | } | |
4025 | ||
c19d1205 | 4026 | switch (reg->type) |
b99bd4ef | 4027 | { |
c19d1205 ZW |
4028 | case REG_TYPE_FN: |
4029 | if (had_brace) | |
4030 | { | |
4031 | as_bad (_("FPA .unwind_save does not take a register list")); | |
4032 | ignore_rest_of_line (); | |
4033 | return; | |
4034 | } | |
93ac2687 | 4035 | input_line_pointer = peek; |
c19d1205 | 4036 | s_arm_unwind_save_fpa (reg->number); |
b99bd4ef | 4037 | return; |
c19d1205 ZW |
4038 | |
4039 | case REG_TYPE_RN: s_arm_unwind_save_core (); return; | |
fa073d69 MS |
4040 | case REG_TYPE_VFD: |
4041 | if (arch_v6) | |
4042 | s_arm_unwind_save_vfp_armv6 (); | |
4043 | else | |
4044 | s_arm_unwind_save_vfp (); | |
4045 | return; | |
c19d1205 ZW |
4046 | case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; |
4047 | case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; | |
4048 | ||
4049 | default: | |
4050 | as_bad (_(".unwind_save does not support this kind of register")); | |
4051 | ignore_rest_of_line (); | |
b99bd4ef | 4052 | } |
c19d1205 | 4053 | } |
b99bd4ef | 4054 | |
b99bd4ef | 4055 | |
c19d1205 ZW |
4056 | /* Parse an unwind_movsp directive. */ |
4057 | ||
4058 | static void | |
4059 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
4060 | { | |
4061 | int reg; | |
4062 | valueT op; | |
4fa3602b | 4063 | int offset; |
c19d1205 | 4064 | |
921e5f0a | 4065 | if (!unwind.proc_start) |
c921be7d | 4066 | as_bad (MISSING_FNSTART); |
921e5f0a | 4067 | |
dcbf9037 | 4068 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 | 4069 | if (reg == FAIL) |
b99bd4ef | 4070 | { |
9b7132d3 | 4071 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 | 4072 | ignore_rest_of_line (); |
b99bd4ef NC |
4073 | return; |
4074 | } | |
4fa3602b PB |
4075 | |
4076 | /* Optional constant. */ | |
4077 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4078 | { | |
4079 | if (immediate_for_directive (&offset) == FAIL) | |
4080 | return; | |
4081 | } | |
4082 | else | |
4083 | offset = 0; | |
4084 | ||
c19d1205 | 4085 | demand_empty_rest_of_line (); |
b99bd4ef | 4086 | |
c19d1205 | 4087 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 4088 | { |
c19d1205 | 4089 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
4090 | return; |
4091 | } | |
4092 | ||
c19d1205 ZW |
4093 | if (unwind.fp_reg != REG_SP) |
4094 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 4095 | |
c19d1205 ZW |
4096 | /* Generate opcode to restore the value. */ |
4097 | op = 0x90 | reg; | |
4098 | add_unwind_opcode (op, 1); | |
4099 | ||
4100 | /* Record the information for later. */ | |
4101 | unwind.fp_reg = reg; | |
4fa3602b | 4102 | unwind.fp_offset = unwind.frame_size - offset; |
c19d1205 | 4103 | unwind.sp_restored = 1; |
b05fe5cf ZW |
4104 | } |
4105 | ||
c19d1205 ZW |
4106 | /* Parse an unwind_pad directive. */ |
4107 | ||
b05fe5cf | 4108 | static void |
c19d1205 | 4109 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 4110 | { |
c19d1205 | 4111 | int offset; |
b05fe5cf | 4112 | |
921e5f0a | 4113 | if (!unwind.proc_start) |
c921be7d | 4114 | as_bad (MISSING_FNSTART); |
921e5f0a | 4115 | |
c19d1205 ZW |
4116 | if (immediate_for_directive (&offset) == FAIL) |
4117 | return; | |
b99bd4ef | 4118 | |
c19d1205 ZW |
4119 | if (offset & 3) |
4120 | { | |
4121 | as_bad (_("stack increment must be multiple of 4")); | |
4122 | ignore_rest_of_line (); | |
4123 | return; | |
4124 | } | |
b99bd4ef | 4125 | |
c19d1205 ZW |
4126 | /* Don't generate any opcodes, just record the details for later. */ |
4127 | unwind.frame_size += offset; | |
4128 | unwind.pending_offset += offset; | |
4129 | ||
4130 | demand_empty_rest_of_line (); | |
4131 | } | |
4132 | ||
4133 | /* Parse an unwind_setfp directive. */ | |
4134 | ||
4135 | static void | |
4136 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 4137 | { |
c19d1205 ZW |
4138 | int sp_reg; |
4139 | int fp_reg; | |
4140 | int offset; | |
4141 | ||
921e5f0a | 4142 | if (!unwind.proc_start) |
c921be7d | 4143 | as_bad (MISSING_FNSTART); |
921e5f0a | 4144 | |
dcbf9037 | 4145 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 ZW |
4146 | if (skip_past_comma (&input_line_pointer) == FAIL) |
4147 | sp_reg = FAIL; | |
4148 | else | |
dcbf9037 | 4149 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
b99bd4ef | 4150 | |
c19d1205 ZW |
4151 | if (fp_reg == FAIL || sp_reg == FAIL) |
4152 | { | |
4153 | as_bad (_("expected <reg>, <reg>")); | |
4154 | ignore_rest_of_line (); | |
4155 | return; | |
4156 | } | |
b99bd4ef | 4157 | |
c19d1205 ZW |
4158 | /* Optional constant. */ |
4159 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4160 | { | |
4161 | if (immediate_for_directive (&offset) == FAIL) | |
4162 | return; | |
4163 | } | |
4164 | else | |
4165 | offset = 0; | |
a737bd4d | 4166 | |
c19d1205 | 4167 | demand_empty_rest_of_line (); |
a737bd4d | 4168 | |
fdfde340 | 4169 | if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) |
a737bd4d | 4170 | { |
c19d1205 ZW |
4171 | as_bad (_("register must be either sp or set by a previous" |
4172 | "unwind_movsp directive")); | |
4173 | return; | |
a737bd4d NC |
4174 | } |
4175 | ||
c19d1205 ZW |
4176 | /* Don't generate any opcodes, just record the information for later. */ |
4177 | unwind.fp_reg = fp_reg; | |
4178 | unwind.fp_used = 1; | |
fdfde340 | 4179 | if (sp_reg == REG_SP) |
c19d1205 ZW |
4180 | unwind.fp_offset = unwind.frame_size - offset; |
4181 | else | |
4182 | unwind.fp_offset -= offset; | |
a737bd4d NC |
4183 | } |
4184 | ||
c19d1205 ZW |
4185 | /* Parse an unwind_raw directive. */ |
4186 | ||
4187 | static void | |
4188 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 4189 | { |
c19d1205 | 4190 | expressionS exp; |
708587a4 | 4191 | /* This is an arbitrary limit. */ |
c19d1205 ZW |
4192 | unsigned char op[16]; |
4193 | int count; | |
a737bd4d | 4194 | |
921e5f0a | 4195 | if (!unwind.proc_start) |
c921be7d | 4196 | as_bad (MISSING_FNSTART); |
921e5f0a | 4197 | |
c19d1205 ZW |
4198 | expression (&exp); |
4199 | if (exp.X_op == O_constant | |
4200 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 4201 | { |
c19d1205 ZW |
4202 | unwind.frame_size += exp.X_add_number; |
4203 | expression (&exp); | |
4204 | } | |
4205 | else | |
4206 | exp.X_op = O_illegal; | |
a737bd4d | 4207 | |
c19d1205 ZW |
4208 | if (exp.X_op != O_constant) |
4209 | { | |
4210 | as_bad (_("expected <offset>, <opcode>")); | |
4211 | ignore_rest_of_line (); | |
4212 | return; | |
4213 | } | |
a737bd4d | 4214 | |
c19d1205 | 4215 | count = 0; |
a737bd4d | 4216 | |
c19d1205 ZW |
4217 | /* Parse the opcode. */ |
4218 | for (;;) | |
4219 | { | |
4220 | if (count >= 16) | |
4221 | { | |
4222 | as_bad (_("unwind opcode too long")); | |
4223 | ignore_rest_of_line (); | |
a737bd4d | 4224 | } |
c19d1205 | 4225 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 4226 | { |
c19d1205 ZW |
4227 | as_bad (_("invalid unwind opcode")); |
4228 | ignore_rest_of_line (); | |
4229 | return; | |
a737bd4d | 4230 | } |
c19d1205 | 4231 | op[count++] = exp.X_add_number; |
a737bd4d | 4232 | |
c19d1205 ZW |
4233 | /* Parse the next byte. */ |
4234 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
4235 | break; | |
a737bd4d | 4236 | |
c19d1205 ZW |
4237 | expression (&exp); |
4238 | } | |
b99bd4ef | 4239 | |
c19d1205 ZW |
4240 | /* Add the opcode bytes in reverse order. */ |
4241 | while (count--) | |
4242 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 4243 | |
c19d1205 | 4244 | demand_empty_rest_of_line (); |
b99bd4ef | 4245 | } |
ee065d83 PB |
4246 | |
4247 | ||
4248 | /* Parse a .eabi_attribute directive. */ | |
4249 | ||
4250 | static void | |
4251 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
4252 | { | |
ee3c0378 AS |
4253 | int tag = s_vendor_attribute (OBJ_ATTR_PROC); |
4254 | ||
4255 | if (tag < NUM_KNOWN_OBJ_ATTRIBUTES) | |
4256 | attributes_set_explicitly[tag] = 1; | |
ee065d83 | 4257 | } |
8463be01 | 4258 | #endif /* OBJ_ELF */ |
ee065d83 PB |
4259 | |
4260 | static void s_arm_arch (int); | |
7a1d4c38 | 4261 | static void s_arm_object_arch (int); |
ee065d83 PB |
4262 | static void s_arm_cpu (int); |
4263 | static void s_arm_fpu (int); | |
b99bd4ef | 4264 | |
f0927246 NC |
4265 | #ifdef TE_PE |
4266 | ||
4267 | static void | |
5f4273c7 | 4268 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
f0927246 NC |
4269 | { |
4270 | expressionS exp; | |
4271 | ||
4272 | do | |
4273 | { | |
4274 | expression (&exp); | |
4275 | if (exp.X_op == O_symbol) | |
4276 | exp.X_op = O_secrel; | |
4277 | ||
4278 | emit_expr (&exp, 4); | |
4279 | } | |
4280 | while (*input_line_pointer++ == ','); | |
4281 | ||
4282 | input_line_pointer--; | |
4283 | demand_empty_rest_of_line (); | |
4284 | } | |
4285 | #endif /* TE_PE */ | |
4286 | ||
c19d1205 ZW |
4287 | /* This table describes all the machine specific pseudo-ops the assembler |
4288 | has to support. The fields are: | |
4289 | pseudo-op name without dot | |
4290 | function to call to execute this pseudo-op | |
4291 | Integer arg to pass to the function. */ | |
b99bd4ef | 4292 | |
c19d1205 | 4293 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 4294 | { |
c19d1205 ZW |
4295 | /* Never called because '.req' does not start a line. */ |
4296 | { "req", s_req, 0 }, | |
dcbf9037 JB |
4297 | /* Following two are likewise never called. */ |
4298 | { "dn", s_dn, 0 }, | |
4299 | { "qn", s_qn, 0 }, | |
c19d1205 ZW |
4300 | { "unreq", s_unreq, 0 }, |
4301 | { "bss", s_bss, 0 }, | |
4302 | { "align", s_align, 0 }, | |
4303 | { "arm", s_arm, 0 }, | |
4304 | { "thumb", s_thumb, 0 }, | |
4305 | { "code", s_code, 0 }, | |
4306 | { "force_thumb", s_force_thumb, 0 }, | |
4307 | { "thumb_func", s_thumb_func, 0 }, | |
4308 | { "thumb_set", s_thumb_set, 0 }, | |
4309 | { "even", s_even, 0 }, | |
4310 | { "ltorg", s_ltorg, 0 }, | |
4311 | { "pool", s_ltorg, 0 }, | |
4312 | { "syntax", s_syntax, 0 }, | |
8463be01 PB |
4313 | { "cpu", s_arm_cpu, 0 }, |
4314 | { "arch", s_arm_arch, 0 }, | |
7a1d4c38 | 4315 | { "object_arch", s_arm_object_arch, 0 }, |
8463be01 | 4316 | { "fpu", s_arm_fpu, 0 }, |
c19d1205 | 4317 | #ifdef OBJ_ELF |
c921be7d NC |
4318 | { "word", s_arm_elf_cons, 4 }, |
4319 | { "long", s_arm_elf_cons, 4 }, | |
4320 | { "inst.n", s_arm_elf_inst, 2 }, | |
4321 | { "inst.w", s_arm_elf_inst, 4 }, | |
4322 | { "inst", s_arm_elf_inst, 0 }, | |
4323 | { "rel31", s_arm_rel31, 0 }, | |
c19d1205 ZW |
4324 | { "fnstart", s_arm_unwind_fnstart, 0 }, |
4325 | { "fnend", s_arm_unwind_fnend, 0 }, | |
4326 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
4327 | { "personality", s_arm_unwind_personality, 0 }, | |
4328 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
4329 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
4330 | { "save", s_arm_unwind_save, 0 }, | |
fa073d69 | 4331 | { "vsave", s_arm_unwind_save, 1 }, |
c19d1205 ZW |
4332 | { "movsp", s_arm_unwind_movsp, 0 }, |
4333 | { "pad", s_arm_unwind_pad, 0 }, | |
4334 | { "setfp", s_arm_unwind_setfp, 0 }, | |
4335 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 | 4336 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
c19d1205 ZW |
4337 | #else |
4338 | { "word", cons, 4}, | |
f0927246 NC |
4339 | |
4340 | /* These are used for dwarf. */ | |
4341 | {"2byte", cons, 2}, | |
4342 | {"4byte", cons, 4}, | |
4343 | {"8byte", cons, 8}, | |
4344 | /* These are used for dwarf2. */ | |
4345 | { "file", (void (*) (int)) dwarf2_directive_file, 0 }, | |
4346 | { "loc", dwarf2_directive_loc, 0 }, | |
4347 | { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, | |
c19d1205 ZW |
4348 | #endif |
4349 | { "extend", float_cons, 'x' }, | |
4350 | { "ldouble", float_cons, 'x' }, | |
4351 | { "packed", float_cons, 'p' }, | |
f0927246 NC |
4352 | #ifdef TE_PE |
4353 | {"secrel32", pe_directive_secrel, 0}, | |
4354 | #endif | |
c19d1205 ZW |
4355 | { 0, 0, 0 } |
4356 | }; | |
4357 | \f | |
4358 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 4359 | |
c19d1205 ZW |
4360 | /* Generic immediate-value read function for use in insn parsing. |
4361 | STR points to the beginning of the immediate (the leading #); | |
4362 | VAL receives the value; if the value is outside [MIN, MAX] | |
4363 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
4364 | optional. */ | |
b99bd4ef | 4365 | |
c19d1205 ZW |
4366 | static int |
4367 | parse_immediate (char **str, int *val, int min, int max, | |
4368 | bfd_boolean prefix_opt) | |
4369 | { | |
4370 | expressionS exp; | |
4371 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
4372 | if (exp.X_op != O_constant) | |
b99bd4ef | 4373 | { |
c19d1205 ZW |
4374 | inst.error = _("constant expression required"); |
4375 | return FAIL; | |
4376 | } | |
b99bd4ef | 4377 | |
c19d1205 ZW |
4378 | if (exp.X_add_number < min || exp.X_add_number > max) |
4379 | { | |
4380 | inst.error = _("immediate value out of range"); | |
4381 | return FAIL; | |
4382 | } | |
b99bd4ef | 4383 | |
c19d1205 ZW |
4384 | *val = exp.X_add_number; |
4385 | return SUCCESS; | |
4386 | } | |
b99bd4ef | 4387 | |
5287ad62 | 4388 | /* Less-generic immediate-value read function with the possibility of loading a |
036dc3f7 | 4389 | big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate |
5287ad62 JB |
4390 | instructions. Puts the result directly in inst.operands[i]. */ |
4391 | ||
4392 | static int | |
4393 | parse_big_immediate (char **str, int i) | |
4394 | { | |
4395 | expressionS exp; | |
4396 | char *ptr = *str; | |
4397 | ||
4398 | my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); | |
4399 | ||
4400 | if (exp.X_op == O_constant) | |
036dc3f7 PB |
4401 | { |
4402 | inst.operands[i].imm = exp.X_add_number & 0xffffffff; | |
4403 | /* If we're on a 64-bit host, then a 64-bit number can be returned using | |
4404 | O_constant. We have to be careful not to break compilation for | |
4405 | 32-bit X_add_number, though. */ | |
4406 | if ((exp.X_add_number & ~0xffffffffl) != 0) | |
4407 | { | |
4408 | /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ | |
4409 | inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; | |
4410 | inst.operands[i].regisimm = 1; | |
4411 | } | |
4412 | } | |
5287ad62 JB |
4413 | else if (exp.X_op == O_big |
4414 | && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32 | |
4415 | && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64) | |
4416 | { | |
4417 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; | |
4418 | /* Bignums have their least significant bits in | |
4419 | generic_bignum[0]. Make sure we put 32 bits in imm and | |
4420 | 32 bits in reg, in a (hopefully) portable way. */ | |
9c2799c2 | 4421 | gas_assert (parts != 0); |
5287ad62 JB |
4422 | inst.operands[i].imm = 0; |
4423 | for (j = 0; j < parts; j++, idx++) | |
4424 | inst.operands[i].imm |= generic_bignum[idx] | |
4425 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4426 | inst.operands[i].reg = 0; | |
4427 | for (j = 0; j < parts; j++, idx++) | |
4428 | inst.operands[i].reg |= generic_bignum[idx] | |
4429 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4430 | inst.operands[i].regisimm = 1; | |
4431 | } | |
4432 | else | |
4433 | return FAIL; | |
5f4273c7 | 4434 | |
5287ad62 JB |
4435 | *str = ptr; |
4436 | ||
4437 | return SUCCESS; | |
4438 | } | |
4439 | ||
c19d1205 ZW |
4440 | /* Returns the pseudo-register number of an FPA immediate constant, |
4441 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 4442 | |
c19d1205 ZW |
4443 | static int |
4444 | parse_fpa_immediate (char ** str) | |
4445 | { | |
4446 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4447 | char * save_in; | |
4448 | expressionS exp; | |
4449 | int i; | |
4450 | int j; | |
b99bd4ef | 4451 | |
c19d1205 ZW |
4452 | /* First try and match exact strings, this is to guarantee |
4453 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 4454 | |
c19d1205 ZW |
4455 | for (i = 0; fp_const[i]; i++) |
4456 | { | |
4457 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 4458 | { |
c19d1205 | 4459 | char *start = *str; |
b99bd4ef | 4460 | |
c19d1205 ZW |
4461 | *str += strlen (fp_const[i]); |
4462 | if (is_end_of_line[(unsigned char) **str]) | |
4463 | return i + 8; | |
4464 | *str = start; | |
4465 | } | |
4466 | } | |
b99bd4ef | 4467 | |
c19d1205 ZW |
4468 | /* Just because we didn't get a match doesn't mean that the constant |
4469 | isn't valid, just that it is in a format that we don't | |
4470 | automatically recognize. Try parsing it with the standard | |
4471 | expression routines. */ | |
b99bd4ef | 4472 | |
c19d1205 | 4473 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 4474 | |
c19d1205 ZW |
4475 | /* Look for a raw floating point number. */ |
4476 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
4477 | && is_end_of_line[(unsigned char) *save_in]) | |
4478 | { | |
4479 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4480 | { | |
4481 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 4482 | { |
c19d1205 ZW |
4483 | if (words[j] != fp_values[i][j]) |
4484 | break; | |
b99bd4ef NC |
4485 | } |
4486 | ||
c19d1205 | 4487 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 4488 | { |
c19d1205 ZW |
4489 | *str = save_in; |
4490 | return i + 8; | |
b99bd4ef NC |
4491 | } |
4492 | } | |
4493 | } | |
b99bd4ef | 4494 | |
c19d1205 ZW |
4495 | /* Try and parse a more complex expression, this will probably fail |
4496 | unless the code uses a floating point prefix (eg "0f"). */ | |
4497 | save_in = input_line_pointer; | |
4498 | input_line_pointer = *str; | |
4499 | if (expression (&exp) == absolute_section | |
4500 | && exp.X_op == O_big | |
4501 | && exp.X_add_number < 0) | |
4502 | { | |
4503 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
4504 | Ditto for 15. */ | |
4505 | if (gen_to_words (words, 5, (long) 15) == 0) | |
4506 | { | |
4507 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4508 | { | |
4509 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
4510 | { | |
4511 | if (words[j] != fp_values[i][j]) | |
4512 | break; | |
4513 | } | |
b99bd4ef | 4514 | |
c19d1205 ZW |
4515 | if (j == MAX_LITTLENUMS) |
4516 | { | |
4517 | *str = input_line_pointer; | |
4518 | input_line_pointer = save_in; | |
4519 | return i + 8; | |
4520 | } | |
4521 | } | |
4522 | } | |
b99bd4ef NC |
4523 | } |
4524 | ||
c19d1205 ZW |
4525 | *str = input_line_pointer; |
4526 | input_line_pointer = save_in; | |
4527 | inst.error = _("invalid FPA immediate expression"); | |
4528 | return FAIL; | |
b99bd4ef NC |
4529 | } |
4530 | ||
136da414 JB |
4531 | /* Returns 1 if a number has "quarter-precision" float format |
4532 | 0baBbbbbbc defgh000 00000000 00000000. */ | |
4533 | ||
4534 | static int | |
4535 | is_quarter_float (unsigned imm) | |
4536 | { | |
4537 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; | |
4538 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; | |
4539 | } | |
4540 | ||
4541 | /* Parse an 8-bit "quarter-precision" floating point number of the form: | |
4542 | 0baBbbbbbc defgh000 00000000 00000000. | |
c96612cc JB |
4543 | The zero and minus-zero cases need special handling, since they can't be |
4544 | encoded in the "quarter-precision" float format, but can nonetheless be | |
4545 | loaded as integer constants. */ | |
136da414 JB |
4546 | |
4547 | static unsigned | |
4548 | parse_qfloat_immediate (char **ccp, int *immed) | |
4549 | { | |
4550 | char *str = *ccp; | |
c96612cc | 4551 | char *fpnum; |
136da414 | 4552 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
c96612cc | 4553 | int found_fpchar = 0; |
5f4273c7 | 4554 | |
136da414 | 4555 | skip_past_char (&str, '#'); |
5f4273c7 | 4556 | |
c96612cc JB |
4557 | /* We must not accidentally parse an integer as a floating-point number. Make |
4558 | sure that the value we parse is not an integer by checking for special | |
4559 | characters '.' or 'e'. | |
4560 | FIXME: This is a horrible hack, but doing better is tricky because type | |
4561 | information isn't in a very usable state at parse time. */ | |
4562 | fpnum = str; | |
4563 | skip_whitespace (fpnum); | |
4564 | ||
4565 | if (strncmp (fpnum, "0x", 2) == 0) | |
4566 | return FAIL; | |
4567 | else | |
4568 | { | |
4569 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) | |
4570 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') | |
4571 | { | |
4572 | found_fpchar = 1; | |
4573 | break; | |
4574 | } | |
4575 | ||
4576 | if (!found_fpchar) | |
4577 | return FAIL; | |
4578 | } | |
5f4273c7 | 4579 | |
136da414 JB |
4580 | if ((str = atof_ieee (str, 's', words)) != NULL) |
4581 | { | |
4582 | unsigned fpword = 0; | |
4583 | int i; | |
5f4273c7 | 4584 | |
136da414 JB |
4585 | /* Our FP word must be 32 bits (single-precision FP). */ |
4586 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
4587 | { | |
4588 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
4589 | fpword |= words[i]; | |
4590 | } | |
5f4273c7 | 4591 | |
c96612cc | 4592 | if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) |
136da414 JB |
4593 | *immed = fpword; |
4594 | else | |
4595 | return FAIL; | |
4596 | ||
4597 | *ccp = str; | |
5f4273c7 | 4598 | |
136da414 JB |
4599 | return SUCCESS; |
4600 | } | |
5f4273c7 | 4601 | |
136da414 JB |
4602 | return FAIL; |
4603 | } | |
4604 | ||
c19d1205 ZW |
4605 | /* Shift operands. */ |
4606 | enum shift_kind | |
b99bd4ef | 4607 | { |
c19d1205 ZW |
4608 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
4609 | }; | |
b99bd4ef | 4610 | |
c19d1205 ZW |
4611 | struct asm_shift_name |
4612 | { | |
4613 | const char *name; | |
4614 | enum shift_kind kind; | |
4615 | }; | |
b99bd4ef | 4616 | |
c19d1205 ZW |
4617 | /* Third argument to parse_shift. */ |
4618 | enum parse_shift_mode | |
4619 | { | |
4620 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
4621 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
4622 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
4623 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
4624 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
4625 | }; | |
b99bd4ef | 4626 | |
c19d1205 ZW |
4627 | /* Parse a <shift> specifier on an ARM data processing instruction. |
4628 | This has three forms: | |
b99bd4ef | 4629 | |
c19d1205 ZW |
4630 | (LSL|LSR|ASL|ASR|ROR) Rs |
4631 | (LSL|LSR|ASL|ASR|ROR) #imm | |
4632 | RRX | |
b99bd4ef | 4633 | |
c19d1205 ZW |
4634 | Note that ASL is assimilated to LSL in the instruction encoding, and |
4635 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 4636 | |
c19d1205 ZW |
4637 | static int |
4638 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 4639 | { |
c19d1205 ZW |
4640 | const struct asm_shift_name *shift_name; |
4641 | enum shift_kind shift; | |
4642 | char *s = *str; | |
4643 | char *p = s; | |
4644 | int reg; | |
b99bd4ef | 4645 | |
c19d1205 ZW |
4646 | for (p = *str; ISALPHA (*p); p++) |
4647 | ; | |
b99bd4ef | 4648 | |
c19d1205 | 4649 | if (p == *str) |
b99bd4ef | 4650 | { |
c19d1205 ZW |
4651 | inst.error = _("shift expression expected"); |
4652 | return FAIL; | |
b99bd4ef NC |
4653 | } |
4654 | ||
21d799b5 NC |
4655 | shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str, |
4656 | p - *str); | |
c19d1205 ZW |
4657 | |
4658 | if (shift_name == NULL) | |
b99bd4ef | 4659 | { |
c19d1205 ZW |
4660 | inst.error = _("shift expression expected"); |
4661 | return FAIL; | |
b99bd4ef NC |
4662 | } |
4663 | ||
c19d1205 | 4664 | shift = shift_name->kind; |
b99bd4ef | 4665 | |
c19d1205 ZW |
4666 | switch (mode) |
4667 | { | |
4668 | case NO_SHIFT_RESTRICT: | |
4669 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 4670 | |
c19d1205 ZW |
4671 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
4672 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
4673 | { | |
4674 | inst.error = _("'LSL' or 'ASR' required"); | |
4675 | return FAIL; | |
4676 | } | |
4677 | break; | |
b99bd4ef | 4678 | |
c19d1205 ZW |
4679 | case SHIFT_LSL_IMMEDIATE: |
4680 | if (shift != SHIFT_LSL) | |
4681 | { | |
4682 | inst.error = _("'LSL' required"); | |
4683 | return FAIL; | |
4684 | } | |
4685 | break; | |
b99bd4ef | 4686 | |
c19d1205 ZW |
4687 | case SHIFT_ASR_IMMEDIATE: |
4688 | if (shift != SHIFT_ASR) | |
4689 | { | |
4690 | inst.error = _("'ASR' required"); | |
4691 | return FAIL; | |
4692 | } | |
4693 | break; | |
b99bd4ef | 4694 | |
c19d1205 ZW |
4695 | default: abort (); |
4696 | } | |
b99bd4ef | 4697 | |
c19d1205 ZW |
4698 | if (shift != SHIFT_RRX) |
4699 | { | |
4700 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
4701 | skip_whitespace (p); | |
b99bd4ef | 4702 | |
c19d1205 | 4703 | if (mode == NO_SHIFT_RESTRICT |
dcbf9037 | 4704 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4705 | { |
4706 | inst.operands[i].imm = reg; | |
4707 | inst.operands[i].immisreg = 1; | |
4708 | } | |
4709 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4710 | return FAIL; | |
4711 | } | |
4712 | inst.operands[i].shift_kind = shift; | |
4713 | inst.operands[i].shifted = 1; | |
4714 | *str = p; | |
4715 | return SUCCESS; | |
b99bd4ef NC |
4716 | } |
4717 | ||
c19d1205 | 4718 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 4719 | |
c19d1205 ZW |
4720 | #<immediate> |
4721 | #<immediate>, <rotate> | |
4722 | <Rm> | |
4723 | <Rm>, <shift> | |
b99bd4ef | 4724 | |
c19d1205 ZW |
4725 | where <shift> is defined by parse_shift above, and <rotate> is a |
4726 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 4727 | is deferred to md_apply_fix. */ |
b99bd4ef | 4728 | |
c19d1205 ZW |
4729 | static int |
4730 | parse_shifter_operand (char **str, int i) | |
4731 | { | |
4732 | int value; | |
91d6fa6a | 4733 | expressionS exp; |
b99bd4ef | 4734 | |
dcbf9037 | 4735 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4736 | { |
4737 | inst.operands[i].reg = value; | |
4738 | inst.operands[i].isreg = 1; | |
b99bd4ef | 4739 | |
c19d1205 ZW |
4740 | /* parse_shift will override this if appropriate */ |
4741 | inst.reloc.exp.X_op = O_constant; | |
4742 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 4743 | |
c19d1205 ZW |
4744 | if (skip_past_comma (str) == FAIL) |
4745 | return SUCCESS; | |
b99bd4ef | 4746 | |
c19d1205 ZW |
4747 | /* Shift operation on register. */ |
4748 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
4749 | } |
4750 | ||
c19d1205 ZW |
4751 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
4752 | return FAIL; | |
b99bd4ef | 4753 | |
c19d1205 | 4754 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 4755 | { |
c19d1205 | 4756 | /* #x, y -- ie explicit rotation by Y. */ |
91d6fa6a | 4757 | if (my_get_expression (&exp, str, GE_NO_PREFIX)) |
c19d1205 | 4758 | return FAIL; |
b99bd4ef | 4759 | |
91d6fa6a | 4760 | if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
c19d1205 ZW |
4761 | { |
4762 | inst.error = _("constant expression expected"); | |
4763 | return FAIL; | |
4764 | } | |
b99bd4ef | 4765 | |
91d6fa6a | 4766 | value = exp.X_add_number; |
c19d1205 ZW |
4767 | if (value < 0 || value > 30 || value % 2 != 0) |
4768 | { | |
4769 | inst.error = _("invalid rotation"); | |
4770 | return FAIL; | |
4771 | } | |
4772 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
4773 | { | |
4774 | inst.error = _("invalid constant"); | |
4775 | return FAIL; | |
4776 | } | |
09d92015 | 4777 | |
55cf6793 | 4778 | /* Convert to decoded value. md_apply_fix will put it back. */ |
c19d1205 ZW |
4779 | inst.reloc.exp.X_add_number |
4780 | = (((inst.reloc.exp.X_add_number << (32 - value)) | |
4781 | | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); | |
09d92015 MM |
4782 | } |
4783 | ||
c19d1205 ZW |
4784 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
4785 | inst.reloc.pc_rel = 0; | |
4786 | return SUCCESS; | |
09d92015 MM |
4787 | } |
4788 | ||
4962c51a MS |
4789 | /* Group relocation information. Each entry in the table contains the |
4790 | textual name of the relocation as may appear in assembler source | |
4791 | and must end with a colon. | |
4792 | Along with this textual name are the relocation codes to be used if | |
4793 | the corresponding instruction is an ALU instruction (ADD or SUB only), | |
4794 | an LDR, an LDRS, or an LDC. */ | |
4795 | ||
4796 | struct group_reloc_table_entry | |
4797 | { | |
4798 | const char *name; | |
4799 | int alu_code; | |
4800 | int ldr_code; | |
4801 | int ldrs_code; | |
4802 | int ldc_code; | |
4803 | }; | |
4804 | ||
4805 | typedef enum | |
4806 | { | |
4807 | /* Varieties of non-ALU group relocation. */ | |
4808 | ||
4809 | GROUP_LDR, | |
4810 | GROUP_LDRS, | |
4811 | GROUP_LDC | |
4812 | } group_reloc_type; | |
4813 | ||
4814 | static struct group_reloc_table_entry group_reloc_table[] = | |
4815 | { /* Program counter relative: */ | |
4816 | { "pc_g0_nc", | |
4817 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ | |
4818 | 0, /* LDR */ | |
4819 | 0, /* LDRS */ | |
4820 | 0 }, /* LDC */ | |
4821 | { "pc_g0", | |
4822 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ | |
4823 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ | |
4824 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ | |
4825 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ | |
4826 | { "pc_g1_nc", | |
4827 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ | |
4828 | 0, /* LDR */ | |
4829 | 0, /* LDRS */ | |
4830 | 0 }, /* LDC */ | |
4831 | { "pc_g1", | |
4832 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ | |
4833 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ | |
4834 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ | |
4835 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ | |
4836 | { "pc_g2", | |
4837 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ | |
4838 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ | |
4839 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ | |
4840 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ | |
4841 | /* Section base relative */ | |
4842 | { "sb_g0_nc", | |
4843 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ | |
4844 | 0, /* LDR */ | |
4845 | 0, /* LDRS */ | |
4846 | 0 }, /* LDC */ | |
4847 | { "sb_g0", | |
4848 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ | |
4849 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ | |
4850 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ | |
4851 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ | |
4852 | { "sb_g1_nc", | |
4853 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ | |
4854 | 0, /* LDR */ | |
4855 | 0, /* LDRS */ | |
4856 | 0 }, /* LDC */ | |
4857 | { "sb_g1", | |
4858 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ | |
4859 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ | |
4860 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ | |
4861 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ | |
4862 | { "sb_g2", | |
4863 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ | |
4864 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ | |
4865 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ | |
4866 | BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ | |
4867 | ||
4868 | /* Given the address of a pointer pointing to the textual name of a group | |
4869 | relocation as may appear in assembler source, attempt to find its details | |
4870 | in group_reloc_table. The pointer will be updated to the character after | |
4871 | the trailing colon. On failure, FAIL will be returned; SUCCESS | |
4872 | otherwise. On success, *entry will be updated to point at the relevant | |
4873 | group_reloc_table entry. */ | |
4874 | ||
4875 | static int | |
4876 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) | |
4877 | { | |
4878 | unsigned int i; | |
4879 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) | |
4880 | { | |
4881 | int length = strlen (group_reloc_table[i].name); | |
4882 | ||
5f4273c7 NC |
4883 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 |
4884 | && (*str)[length] == ':') | |
4962c51a MS |
4885 | { |
4886 | *out = &group_reloc_table[i]; | |
4887 | *str += (length + 1); | |
4888 | return SUCCESS; | |
4889 | } | |
4890 | } | |
4891 | ||
4892 | return FAIL; | |
4893 | } | |
4894 | ||
4895 | /* Parse a <shifter_operand> for an ARM data processing instruction | |
4896 | (as for parse_shifter_operand) where group relocations are allowed: | |
4897 | ||
4898 | #<immediate> | |
4899 | #<immediate>, <rotate> | |
4900 | #:<group_reloc>:<expression> | |
4901 | <Rm> | |
4902 | <Rm>, <shift> | |
4903 | ||
4904 | where <group_reloc> is one of the strings defined in group_reloc_table. | |
4905 | The hashes are optional. | |
4906 | ||
4907 | Everything else is as for parse_shifter_operand. */ | |
4908 | ||
4909 | static parse_operand_result | |
4910 | parse_shifter_operand_group_reloc (char **str, int i) | |
4911 | { | |
4912 | /* Determine if we have the sequence of characters #: or just : | |
4913 | coming next. If we do, then we check for a group relocation. | |
4914 | If we don't, punt the whole lot to parse_shifter_operand. */ | |
4915 | ||
4916 | if (((*str)[0] == '#' && (*str)[1] == ':') | |
4917 | || (*str)[0] == ':') | |
4918 | { | |
4919 | struct group_reloc_table_entry *entry; | |
4920 | ||
4921 | if ((*str)[0] == '#') | |
4922 | (*str) += 2; | |
4923 | else | |
4924 | (*str)++; | |
4925 | ||
4926 | /* Try to parse a group relocation. Anything else is an error. */ | |
4927 | if (find_group_reloc_table_entry (str, &entry) == FAIL) | |
4928 | { | |
4929 | inst.error = _("unknown group relocation"); | |
4930 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
4931 | } | |
4932 | ||
4933 | /* We now have the group relocation table entry corresponding to | |
4934 | the name in the assembler source. Next, we parse the expression. */ | |
4935 | if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) | |
4936 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
4937 | ||
4938 | /* Record the relocation type (always the ALU variant here). */ | |
21d799b5 | 4939 | inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code; |
9c2799c2 | 4940 | gas_assert (inst.reloc.type != 0); |
4962c51a MS |
4941 | |
4942 | return PARSE_OPERAND_SUCCESS; | |
4943 | } | |
4944 | else | |
4945 | return parse_shifter_operand (str, i) == SUCCESS | |
4946 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; | |
4947 | ||
4948 | /* Never reached. */ | |
4949 | } | |
4950 | ||
8e560766 MGD |
4951 | /* Parse a Neon alignment expression. Information is written to |
4952 | inst.operands[i]. We assume the initial ':' has been skipped. | |
4953 | ||
4954 | align .imm = align << 8, .immisalign=1, .preind=0 */ | |
4955 | static parse_operand_result | |
4956 | parse_neon_alignment (char **str, int i) | |
4957 | { | |
4958 | char *p = *str; | |
4959 | expressionS exp; | |
4960 | ||
4961 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
4962 | ||
4963 | if (exp.X_op != O_constant) | |
4964 | { | |
4965 | inst.error = _("alignment must be constant"); | |
4966 | return PARSE_OPERAND_FAIL; | |
4967 | } | |
4968 | ||
4969 | inst.operands[i].imm = exp.X_add_number << 8; | |
4970 | inst.operands[i].immisalign = 1; | |
4971 | /* Alignments are not pre-indexes. */ | |
4972 | inst.operands[i].preind = 0; | |
4973 | ||
4974 | *str = p; | |
4975 | return PARSE_OPERAND_SUCCESS; | |
4976 | } | |
4977 | ||
c19d1205 ZW |
4978 | /* Parse all forms of an ARM address expression. Information is written |
4979 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 4980 | |
c19d1205 | 4981 | Preindexed addressing (.preind=1): |
09d92015 | 4982 | |
c19d1205 ZW |
4983 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
4984 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
4985 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
4986 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 4987 | |
c19d1205 | 4988 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 4989 | |
c19d1205 | 4990 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 4991 | |
c19d1205 ZW |
4992 | [Rn], #offset .reg=Rn .reloc.exp=offset |
4993 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
4994 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
4995 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 4996 | |
c19d1205 | 4997 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 4998 | |
c19d1205 | 4999 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 5000 | |
c19d1205 | 5001 | Other: |
09d92015 | 5002 | |
c19d1205 ZW |
5003 | [Rn]{!} shorthand for [Rn,#0]{!} |
5004 | =immediate .isreg=0 .reloc.exp=immediate | |
5005 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 5006 | |
c19d1205 ZW |
5007 | It is the caller's responsibility to check for addressing modes not |
5008 | supported by the instruction, and to set inst.reloc.type. */ | |
5009 | ||
4962c51a MS |
5010 | static parse_operand_result |
5011 | parse_address_main (char **str, int i, int group_relocations, | |
5012 | group_reloc_type group_type) | |
09d92015 | 5013 | { |
c19d1205 ZW |
5014 | char *p = *str; |
5015 | int reg; | |
09d92015 | 5016 | |
c19d1205 | 5017 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 5018 | { |
c19d1205 ZW |
5019 | if (skip_past_char (&p, '=') == FAIL) |
5020 | { | |
974da60d | 5021 | /* Bare address - translate to PC-relative offset. */ |
c19d1205 ZW |
5022 | inst.reloc.pc_rel = 1; |
5023 | inst.operands[i].reg = REG_PC; | |
5024 | inst.operands[i].isreg = 1; | |
5025 | inst.operands[i].preind = 1; | |
5026 | } | |
974da60d | 5027 | /* Otherwise a load-constant pseudo op, no special treatment needed here. */ |
09d92015 | 5028 | |
c19d1205 | 5029 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
4962c51a | 5030 | return PARSE_OPERAND_FAIL; |
09d92015 | 5031 | |
c19d1205 | 5032 | *str = p; |
4962c51a | 5033 | return PARSE_OPERAND_SUCCESS; |
09d92015 MM |
5034 | } |
5035 | ||
dcbf9037 | 5036 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 5037 | { |
c19d1205 | 5038 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
4962c51a | 5039 | return PARSE_OPERAND_FAIL; |
09d92015 | 5040 | } |
c19d1205 ZW |
5041 | inst.operands[i].reg = reg; |
5042 | inst.operands[i].isreg = 1; | |
09d92015 | 5043 | |
c19d1205 | 5044 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5045 | { |
c19d1205 | 5046 | inst.operands[i].preind = 1; |
09d92015 | 5047 | |
c19d1205 ZW |
5048 | if (*p == '+') p++; |
5049 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
5050 | ||
dcbf9037 | 5051 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
09d92015 | 5052 | { |
c19d1205 ZW |
5053 | inst.operands[i].imm = reg; |
5054 | inst.operands[i].immisreg = 1; | |
5055 | ||
5056 | if (skip_past_comma (&p) == SUCCESS) | |
5057 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5058 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5059 | } |
5287ad62 | 5060 | else if (skip_past_char (&p, ':') == SUCCESS) |
8e560766 MGD |
5061 | { |
5062 | /* FIXME: '@' should be used here, but it's filtered out by generic | |
5063 | code before we get to see it here. This may be subject to | |
5064 | change. */ | |
5065 | parse_operand_result result = parse_neon_alignment (&p, i); | |
5066 | ||
5067 | if (result != PARSE_OPERAND_SUCCESS) | |
5068 | return result; | |
5069 | } | |
c19d1205 ZW |
5070 | else |
5071 | { | |
5072 | if (inst.operands[i].negative) | |
5073 | { | |
5074 | inst.operands[i].negative = 0; | |
5075 | p--; | |
5076 | } | |
4962c51a | 5077 | |
5f4273c7 NC |
5078 | if (group_relocations |
5079 | && ((*p == '#' && *(p + 1) == ':') || *p == ':')) | |
4962c51a MS |
5080 | { |
5081 | struct group_reloc_table_entry *entry; | |
5082 | ||
5083 | /* Skip over the #: or : sequence. */ | |
5084 | if (*p == '#') | |
5085 | p += 2; | |
5086 | else | |
5087 | p++; | |
5088 | ||
5089 | /* Try to parse a group relocation. Anything else is an | |
5090 | error. */ | |
5091 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) | |
5092 | { | |
5093 | inst.error = _("unknown group relocation"); | |
5094 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5095 | } | |
5096 | ||
5097 | /* We now have the group relocation table entry corresponding to | |
5098 | the name in the assembler source. Next, we parse the | |
5099 | expression. */ | |
5100 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5101 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5102 | ||
5103 | /* Record the relocation type. */ | |
5104 | switch (group_type) | |
5105 | { | |
5106 | case GROUP_LDR: | |
21d799b5 | 5107 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code; |
4962c51a MS |
5108 | break; |
5109 | ||
5110 | case GROUP_LDRS: | |
21d799b5 | 5111 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code; |
4962c51a MS |
5112 | break; |
5113 | ||
5114 | case GROUP_LDC: | |
21d799b5 | 5115 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code; |
4962c51a MS |
5116 | break; |
5117 | ||
5118 | default: | |
9c2799c2 | 5119 | gas_assert (0); |
4962c51a MS |
5120 | } |
5121 | ||
5122 | if (inst.reloc.type == 0) | |
5123 | { | |
5124 | inst.error = _("this group relocation is not allowed on this instruction"); | |
5125 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5126 | } | |
5127 | } | |
5128 | else | |
5129 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
5130 | return PARSE_OPERAND_FAIL; | |
09d92015 MM |
5131 | } |
5132 | } | |
8e560766 MGD |
5133 | else if (skip_past_char (&p, ':') == SUCCESS) |
5134 | { | |
5135 | /* FIXME: '@' should be used here, but it's filtered out by generic code | |
5136 | before we get to see it here. This may be subject to change. */ | |
5137 | parse_operand_result result = parse_neon_alignment (&p, i); | |
5138 | ||
5139 | if (result != PARSE_OPERAND_SUCCESS) | |
5140 | return result; | |
5141 | } | |
09d92015 | 5142 | |
c19d1205 | 5143 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 5144 | { |
c19d1205 | 5145 | inst.error = _("']' expected"); |
4962c51a | 5146 | return PARSE_OPERAND_FAIL; |
09d92015 MM |
5147 | } |
5148 | ||
c19d1205 ZW |
5149 | if (skip_past_char (&p, '!') == SUCCESS) |
5150 | inst.operands[i].writeback = 1; | |
09d92015 | 5151 | |
c19d1205 | 5152 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5153 | { |
c19d1205 ZW |
5154 | if (skip_past_char (&p, '{') == SUCCESS) |
5155 | { | |
5156 | /* [Rn], {expr} - unindexed, with option */ | |
5157 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 5158 | 0, 255, TRUE) == FAIL) |
4962c51a | 5159 | return PARSE_OPERAND_FAIL; |
09d92015 | 5160 | |
c19d1205 ZW |
5161 | if (skip_past_char (&p, '}') == FAIL) |
5162 | { | |
5163 | inst.error = _("'}' expected at end of 'option' field"); | |
4962c51a | 5164 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5165 | } |
5166 | if (inst.operands[i].preind) | |
5167 | { | |
5168 | inst.error = _("cannot combine index with option"); | |
4962c51a | 5169 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5170 | } |
5171 | *str = p; | |
4962c51a | 5172 | return PARSE_OPERAND_SUCCESS; |
09d92015 | 5173 | } |
c19d1205 ZW |
5174 | else |
5175 | { | |
5176 | inst.operands[i].postind = 1; | |
5177 | inst.operands[i].writeback = 1; | |
09d92015 | 5178 | |
c19d1205 ZW |
5179 | if (inst.operands[i].preind) |
5180 | { | |
5181 | inst.error = _("cannot combine pre- and post-indexing"); | |
4962c51a | 5182 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5183 | } |
09d92015 | 5184 | |
c19d1205 ZW |
5185 | if (*p == '+') p++; |
5186 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 5187 | |
dcbf9037 | 5188 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 | 5189 | { |
5287ad62 JB |
5190 | /* We might be using the immediate for alignment already. If we |
5191 | are, OR the register number into the low-order bits. */ | |
5192 | if (inst.operands[i].immisalign) | |
5193 | inst.operands[i].imm |= reg; | |
5194 | else | |
5195 | inst.operands[i].imm = reg; | |
c19d1205 | 5196 | inst.operands[i].immisreg = 1; |
a737bd4d | 5197 | |
c19d1205 ZW |
5198 | if (skip_past_comma (&p) == SUCCESS) |
5199 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5200 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5201 | } |
5202 | else | |
5203 | { | |
5204 | if (inst.operands[i].negative) | |
5205 | { | |
5206 | inst.operands[i].negative = 0; | |
5207 | p--; | |
5208 | } | |
5209 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4962c51a | 5210 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5211 | } |
5212 | } | |
a737bd4d NC |
5213 | } |
5214 | ||
c19d1205 ZW |
5215 | /* If at this point neither .preind nor .postind is set, we have a |
5216 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
5217 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
5218 | { | |
5219 | inst.operands[i].preind = 1; | |
5220 | inst.reloc.exp.X_op = O_constant; | |
5221 | inst.reloc.exp.X_add_number = 0; | |
5222 | } | |
5223 | *str = p; | |
4962c51a MS |
5224 | return PARSE_OPERAND_SUCCESS; |
5225 | } | |
5226 | ||
5227 | static int | |
5228 | parse_address (char **str, int i) | |
5229 | { | |
21d799b5 | 5230 | return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS |
4962c51a MS |
5231 | ? SUCCESS : FAIL; |
5232 | } | |
5233 | ||
5234 | static parse_operand_result | |
5235 | parse_address_group_reloc (char **str, int i, group_reloc_type type) | |
5236 | { | |
5237 | return parse_address_main (str, i, 1, type); | |
a737bd4d NC |
5238 | } |
5239 | ||
b6895b4f PB |
5240 | /* Parse an operand for a MOVW or MOVT instruction. */ |
5241 | static int | |
5242 | parse_half (char **str) | |
5243 | { | |
5244 | char * p; | |
5f4273c7 | 5245 | |
b6895b4f PB |
5246 | p = *str; |
5247 | skip_past_char (&p, '#'); | |
5f4273c7 | 5248 | if (strncasecmp (p, ":lower16:", 9) == 0) |
b6895b4f PB |
5249 | inst.reloc.type = BFD_RELOC_ARM_MOVW; |
5250 | else if (strncasecmp (p, ":upper16:", 9) == 0) | |
5251 | inst.reloc.type = BFD_RELOC_ARM_MOVT; | |
5252 | ||
5253 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
5254 | { | |
5255 | p += 9; | |
5f4273c7 | 5256 | skip_whitespace (p); |
b6895b4f PB |
5257 | } |
5258 | ||
5259 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5260 | return FAIL; | |
5261 | ||
5262 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
5263 | { | |
5264 | if (inst.reloc.exp.X_op != O_constant) | |
5265 | { | |
5266 | inst.error = _("constant expression expected"); | |
5267 | return FAIL; | |
5268 | } | |
5269 | if (inst.reloc.exp.X_add_number < 0 | |
5270 | || inst.reloc.exp.X_add_number > 0xffff) | |
5271 | { | |
5272 | inst.error = _("immediate value out of range"); | |
5273 | return FAIL; | |
5274 | } | |
5275 | } | |
5276 | *str = p; | |
5277 | return SUCCESS; | |
5278 | } | |
5279 | ||
c19d1205 | 5280 | /* Miscellaneous. */ |
a737bd4d | 5281 | |
c19d1205 ZW |
5282 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
5283 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
5284 | static int | |
5285 | parse_psr (char **str) | |
09d92015 | 5286 | { |
c19d1205 ZW |
5287 | char *p; |
5288 | unsigned long psr_field; | |
62b3e311 PB |
5289 | const struct asm_psr *psr; |
5290 | char *start; | |
09d92015 | 5291 | |
c19d1205 ZW |
5292 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
5293 | feature for ease of use and backwards compatibility. */ | |
5294 | p = *str; | |
62b3e311 | 5295 | if (strncasecmp (p, "SPSR", 4) == 0) |
c19d1205 | 5296 | psr_field = SPSR_BIT; |
62b3e311 | 5297 | else if (strncasecmp (p, "CPSR", 4) == 0) |
c19d1205 ZW |
5298 | psr_field = 0; |
5299 | else | |
62b3e311 PB |
5300 | { |
5301 | start = p; | |
5302 | do | |
5303 | p++; | |
5304 | while (ISALNUM (*p) || *p == '_'); | |
5305 | ||
21d799b5 NC |
5306 | psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start, |
5307 | p - start); | |
62b3e311 PB |
5308 | if (!psr) |
5309 | return FAIL; | |
09d92015 | 5310 | |
62b3e311 PB |
5311 | *str = p; |
5312 | return psr->field; | |
5313 | } | |
09d92015 | 5314 | |
62b3e311 | 5315 | p += 4; |
c19d1205 ZW |
5316 | if (*p == '_') |
5317 | { | |
5318 | /* A suffix follows. */ | |
c19d1205 ZW |
5319 | p++; |
5320 | start = p; | |
a737bd4d | 5321 | |
c19d1205 ZW |
5322 | do |
5323 | p++; | |
5324 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 5325 | |
21d799b5 NC |
5326 | psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start, |
5327 | p - start); | |
c19d1205 ZW |
5328 | if (!psr) |
5329 | goto error; | |
a737bd4d | 5330 | |
c19d1205 | 5331 | psr_field |= psr->field; |
a737bd4d | 5332 | } |
c19d1205 | 5333 | else |
a737bd4d | 5334 | { |
c19d1205 ZW |
5335 | if (ISALNUM (*p)) |
5336 | goto error; /* Garbage after "[CS]PSR". */ | |
5337 | ||
5338 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 5339 | } |
c19d1205 ZW |
5340 | *str = p; |
5341 | return psr_field; | |
a737bd4d | 5342 | |
c19d1205 ZW |
5343 | error: |
5344 | inst.error = _("flag for {c}psr instruction expected"); | |
5345 | return FAIL; | |
a737bd4d NC |
5346 | } |
5347 | ||
c19d1205 ZW |
5348 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
5349 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 5350 | |
c19d1205 ZW |
5351 | static int |
5352 | parse_cps_flags (char **str) | |
a737bd4d | 5353 | { |
c19d1205 ZW |
5354 | int val = 0; |
5355 | int saw_a_flag = 0; | |
5356 | char *s = *str; | |
a737bd4d | 5357 | |
c19d1205 ZW |
5358 | for (;;) |
5359 | switch (*s++) | |
5360 | { | |
5361 | case '\0': case ',': | |
5362 | goto done; | |
a737bd4d | 5363 | |
c19d1205 ZW |
5364 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
5365 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
5366 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 5367 | |
c19d1205 ZW |
5368 | default: |
5369 | inst.error = _("unrecognized CPS flag"); | |
5370 | return FAIL; | |
5371 | } | |
a737bd4d | 5372 | |
c19d1205 ZW |
5373 | done: |
5374 | if (saw_a_flag == 0) | |
a737bd4d | 5375 | { |
c19d1205 ZW |
5376 | inst.error = _("missing CPS flags"); |
5377 | return FAIL; | |
a737bd4d | 5378 | } |
a737bd4d | 5379 | |
c19d1205 ZW |
5380 | *str = s - 1; |
5381 | return val; | |
a737bd4d NC |
5382 | } |
5383 | ||
c19d1205 ZW |
5384 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
5385 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
5386 | |
5387 | static int | |
c19d1205 | 5388 | parse_endian_specifier (char **str) |
a737bd4d | 5389 | { |
c19d1205 ZW |
5390 | int little_endian; |
5391 | char *s = *str; | |
a737bd4d | 5392 | |
c19d1205 ZW |
5393 | if (strncasecmp (s, "BE", 2)) |
5394 | little_endian = 0; | |
5395 | else if (strncasecmp (s, "LE", 2)) | |
5396 | little_endian = 1; | |
5397 | else | |
a737bd4d | 5398 | { |
c19d1205 | 5399 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5400 | return FAIL; |
5401 | } | |
5402 | ||
c19d1205 | 5403 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 5404 | { |
c19d1205 | 5405 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5406 | return FAIL; |
5407 | } | |
5408 | ||
c19d1205 ZW |
5409 | *str = s + 2; |
5410 | return little_endian; | |
5411 | } | |
a737bd4d | 5412 | |
c19d1205 ZW |
5413 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
5414 | value suitable for poking into the rotate field of an sxt or sxta | |
5415 | instruction, or FAIL on error. */ | |
5416 | ||
5417 | static int | |
5418 | parse_ror (char **str) | |
5419 | { | |
5420 | int rot; | |
5421 | char *s = *str; | |
5422 | ||
5423 | if (strncasecmp (s, "ROR", 3) == 0) | |
5424 | s += 3; | |
5425 | else | |
a737bd4d | 5426 | { |
c19d1205 | 5427 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
5428 | return FAIL; |
5429 | } | |
c19d1205 ZW |
5430 | |
5431 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
5432 | return FAIL; | |
5433 | ||
5434 | switch (rot) | |
a737bd4d | 5435 | { |
c19d1205 ZW |
5436 | case 0: *str = s; return 0x0; |
5437 | case 8: *str = s; return 0x1; | |
5438 | case 16: *str = s; return 0x2; | |
5439 | case 24: *str = s; return 0x3; | |
5440 | ||
5441 | default: | |
5442 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
5443 | return FAIL; |
5444 | } | |
c19d1205 | 5445 | } |
a737bd4d | 5446 | |
c19d1205 ZW |
5447 | /* Parse a conditional code (from conds[] below). The value returned is in the |
5448 | range 0 .. 14, or FAIL. */ | |
5449 | static int | |
5450 | parse_cond (char **str) | |
5451 | { | |
c462b453 | 5452 | char *q; |
c19d1205 | 5453 | const struct asm_cond *c; |
c462b453 PB |
5454 | int n; |
5455 | /* Condition codes are always 2 characters, so matching up to | |
5456 | 3 characters is sufficient. */ | |
5457 | char cond[3]; | |
a737bd4d | 5458 | |
c462b453 PB |
5459 | q = *str; |
5460 | n = 0; | |
5461 | while (ISALPHA (*q) && n < 3) | |
5462 | { | |
e07e6e58 | 5463 | cond[n] = TOLOWER (*q); |
c462b453 PB |
5464 | q++; |
5465 | n++; | |
5466 | } | |
a737bd4d | 5467 | |
21d799b5 | 5468 | c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n); |
c19d1205 | 5469 | if (!c) |
a737bd4d | 5470 | { |
c19d1205 | 5471 | inst.error = _("condition required"); |
a737bd4d NC |
5472 | return FAIL; |
5473 | } | |
5474 | ||
c19d1205 ZW |
5475 | *str = q; |
5476 | return c->value; | |
5477 | } | |
5478 | ||
62b3e311 PB |
5479 | /* Parse an option for a barrier instruction. Returns the encoding for the |
5480 | option, or FAIL. */ | |
5481 | static int | |
5482 | parse_barrier (char **str) | |
5483 | { | |
5484 | char *p, *q; | |
5485 | const struct asm_barrier_opt *o; | |
5486 | ||
5487 | p = q = *str; | |
5488 | while (ISALPHA (*q)) | |
5489 | q++; | |
5490 | ||
21d799b5 NC |
5491 | o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p, |
5492 | q - p); | |
62b3e311 PB |
5493 | if (!o) |
5494 | return FAIL; | |
5495 | ||
5496 | *str = q; | |
5497 | return o->value; | |
5498 | } | |
5499 | ||
92e90b6e PB |
5500 | /* Parse the operands of a table branch instruction. Similar to a memory |
5501 | operand. */ | |
5502 | static int | |
5503 | parse_tb (char **str) | |
5504 | { | |
5505 | char * p = *str; | |
5506 | int reg; | |
5507 | ||
5508 | if (skip_past_char (&p, '[') == FAIL) | |
ab1eb5fe PB |
5509 | { |
5510 | inst.error = _("'[' expected"); | |
5511 | return FAIL; | |
5512 | } | |
92e90b6e | 5513 | |
dcbf9037 | 5514 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5515 | { |
5516 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5517 | return FAIL; | |
5518 | } | |
5519 | inst.operands[0].reg = reg; | |
5520 | ||
5521 | if (skip_past_comma (&p) == FAIL) | |
ab1eb5fe PB |
5522 | { |
5523 | inst.error = _("',' expected"); | |
5524 | return FAIL; | |
5525 | } | |
5f4273c7 | 5526 | |
dcbf9037 | 5527 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5528 | { |
5529 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5530 | return FAIL; | |
5531 | } | |
5532 | inst.operands[0].imm = reg; | |
5533 | ||
5534 | if (skip_past_comma (&p) == SUCCESS) | |
5535 | { | |
5536 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
5537 | return FAIL; | |
5538 | if (inst.reloc.exp.X_add_number != 1) | |
5539 | { | |
5540 | inst.error = _("invalid shift"); | |
5541 | return FAIL; | |
5542 | } | |
5543 | inst.operands[0].shifted = 1; | |
5544 | } | |
5545 | ||
5546 | if (skip_past_char (&p, ']') == FAIL) | |
5547 | { | |
5548 | inst.error = _("']' expected"); | |
5549 | return FAIL; | |
5550 | } | |
5551 | *str = p; | |
5552 | return SUCCESS; | |
5553 | } | |
5554 | ||
5287ad62 JB |
5555 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
5556 | information on the types the operands can take and how they are encoded. | |
037e8744 JB |
5557 | Up to four operands may be read; this function handles setting the |
5558 | ".present" field for each read operand itself. | |
5287ad62 JB |
5559 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
5560 | else returns FAIL. */ | |
5561 | ||
5562 | static int | |
5563 | parse_neon_mov (char **str, int *which_operand) | |
5564 | { | |
5565 | int i = *which_operand, val; | |
5566 | enum arm_reg_type rtype; | |
5567 | char *ptr = *str; | |
dcbf9037 | 5568 | struct neon_type_el optype; |
5f4273c7 | 5569 | |
dcbf9037 | 5570 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5571 | { |
5572 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ | |
5573 | inst.operands[i].reg = val; | |
5574 | inst.operands[i].isscalar = 1; | |
dcbf9037 | 5575 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5576 | inst.operands[i++].present = 1; |
5577 | ||
5578 | if (skip_past_comma (&ptr) == FAIL) | |
5579 | goto wanted_comma; | |
5f4273c7 | 5580 | |
dcbf9037 | 5581 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5287ad62 | 5582 | goto wanted_arm; |
5f4273c7 | 5583 | |
5287ad62 JB |
5584 | inst.operands[i].reg = val; |
5585 | inst.operands[i].isreg = 1; | |
5586 | inst.operands[i].present = 1; | |
5587 | } | |
037e8744 | 5588 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
dcbf9037 | 5589 | != FAIL) |
5287ad62 JB |
5590 | { |
5591 | /* Cases 0, 1, 2, 3, 5 (D only). */ | |
5592 | if (skip_past_comma (&ptr) == FAIL) | |
5593 | goto wanted_comma; | |
5f4273c7 | 5594 | |
5287ad62 JB |
5595 | inst.operands[i].reg = val; |
5596 | inst.operands[i].isreg = 1; | |
5597 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5598 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5599 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5600 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5601 | inst.operands[i++].present = 1; |
5602 | ||
dcbf9037 | 5603 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 | 5604 | { |
037e8744 JB |
5605 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. |
5606 | Case 13: VMOV <Sd>, <Rm> */ | |
5287ad62 JB |
5607 | inst.operands[i].reg = val; |
5608 | inst.operands[i].isreg = 1; | |
037e8744 | 5609 | inst.operands[i].present = 1; |
5287ad62 JB |
5610 | |
5611 | if (rtype == REG_TYPE_NQ) | |
5612 | { | |
dcbf9037 | 5613 | first_error (_("can't use Neon quad register here")); |
5287ad62 JB |
5614 | return FAIL; |
5615 | } | |
037e8744 JB |
5616 | else if (rtype != REG_TYPE_VFS) |
5617 | { | |
5618 | i++; | |
5619 | if (skip_past_comma (&ptr) == FAIL) | |
5620 | goto wanted_comma; | |
5621 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5622 | goto wanted_arm; | |
5623 | inst.operands[i].reg = val; | |
5624 | inst.operands[i].isreg = 1; | |
5625 | inst.operands[i].present = 1; | |
5626 | } | |
5287ad62 | 5627 | } |
037e8744 JB |
5628 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, |
5629 | &optype)) != FAIL) | |
5287ad62 JB |
5630 | { |
5631 | /* Case 0: VMOV<c><q> <Qd>, <Qm> | |
037e8744 JB |
5632 | Case 1: VMOV<c><q> <Dd>, <Dm> |
5633 | Case 8: VMOV.F32 <Sd>, <Sm> | |
5634 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ | |
5287ad62 JB |
5635 | |
5636 | inst.operands[i].reg = val; | |
5637 | inst.operands[i].isreg = 1; | |
5638 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5639 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5640 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5641 | inst.operands[i].vectype = optype; |
5287ad62 | 5642 | inst.operands[i].present = 1; |
5f4273c7 | 5643 | |
037e8744 JB |
5644 | if (skip_past_comma (&ptr) == SUCCESS) |
5645 | { | |
5646 | /* Case 15. */ | |
5647 | i++; | |
5648 | ||
5649 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5650 | goto wanted_arm; | |
5651 | ||
5652 | inst.operands[i].reg = val; | |
5653 | inst.operands[i].isreg = 1; | |
5654 | inst.operands[i++].present = 1; | |
5f4273c7 | 5655 | |
037e8744 JB |
5656 | if (skip_past_comma (&ptr) == FAIL) |
5657 | goto wanted_comma; | |
5f4273c7 | 5658 | |
037e8744 JB |
5659 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5660 | goto wanted_arm; | |
5f4273c7 | 5661 | |
037e8744 JB |
5662 | inst.operands[i].reg = val; |
5663 | inst.operands[i].isreg = 1; | |
5664 | inst.operands[i++].present = 1; | |
5665 | } | |
5287ad62 | 5666 | } |
4641781c PB |
5667 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
5668 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> | |
5669 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> | |
5670 | Case 10: VMOV.F32 <Sd>, #<imm> | |
5671 | Case 11: VMOV.F64 <Dd>, #<imm> */ | |
5672 | inst.operands[i].immisfloat = 1; | |
5673 | else if (parse_big_immediate (&ptr, i) == SUCCESS) | |
5674 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> | |
5675 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ | |
5676 | ; | |
5287ad62 JB |
5677 | else |
5678 | { | |
dcbf9037 | 5679 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); |
5287ad62 JB |
5680 | return FAIL; |
5681 | } | |
5682 | } | |
dcbf9037 | 5683 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5684 | { |
5685 | /* Cases 6, 7. */ | |
5686 | inst.operands[i].reg = val; | |
5687 | inst.operands[i].isreg = 1; | |
5688 | inst.operands[i++].present = 1; | |
5f4273c7 | 5689 | |
5287ad62 JB |
5690 | if (skip_past_comma (&ptr) == FAIL) |
5691 | goto wanted_comma; | |
5f4273c7 | 5692 | |
dcbf9037 | 5693 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5694 | { |
5695 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ | |
5696 | inst.operands[i].reg = val; | |
5697 | inst.operands[i].isscalar = 1; | |
5698 | inst.operands[i].present = 1; | |
dcbf9037 | 5699 | inst.operands[i].vectype = optype; |
5287ad62 | 5700 | } |
dcbf9037 | 5701 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5702 | { |
5703 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ | |
5704 | inst.operands[i].reg = val; | |
5705 | inst.operands[i].isreg = 1; | |
5706 | inst.operands[i++].present = 1; | |
5f4273c7 | 5707 | |
5287ad62 JB |
5708 | if (skip_past_comma (&ptr) == FAIL) |
5709 | goto wanted_comma; | |
5f4273c7 | 5710 | |
037e8744 | 5711 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) |
dcbf9037 | 5712 | == FAIL) |
5287ad62 | 5713 | { |
037e8744 | 5714 | first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); |
5287ad62 JB |
5715 | return FAIL; |
5716 | } | |
5717 | ||
5718 | inst.operands[i].reg = val; | |
5719 | inst.operands[i].isreg = 1; | |
037e8744 JB |
5720 | inst.operands[i].isvec = 1; |
5721 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
dcbf9037 | 5722 | inst.operands[i].vectype = optype; |
5287ad62 | 5723 | inst.operands[i].present = 1; |
5f4273c7 | 5724 | |
037e8744 JB |
5725 | if (rtype == REG_TYPE_VFS) |
5726 | { | |
5727 | /* Case 14. */ | |
5728 | i++; | |
5729 | if (skip_past_comma (&ptr) == FAIL) | |
5730 | goto wanted_comma; | |
5731 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, | |
5732 | &optype)) == FAIL) | |
5733 | { | |
5734 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); | |
5735 | return FAIL; | |
5736 | } | |
5737 | inst.operands[i].reg = val; | |
5738 | inst.operands[i].isreg = 1; | |
5739 | inst.operands[i].isvec = 1; | |
5740 | inst.operands[i].issingle = 1; | |
5741 | inst.operands[i].vectype = optype; | |
5742 | inst.operands[i].present = 1; | |
5743 | } | |
5744 | } | |
5745 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) | |
5746 | != FAIL) | |
5747 | { | |
5748 | /* Case 13. */ | |
5749 | inst.operands[i].reg = val; | |
5750 | inst.operands[i].isreg = 1; | |
5751 | inst.operands[i].isvec = 1; | |
5752 | inst.operands[i].issingle = 1; | |
5753 | inst.operands[i].vectype = optype; | |
5754 | inst.operands[i++].present = 1; | |
5287ad62 JB |
5755 | } |
5756 | } | |
5757 | else | |
5758 | { | |
dcbf9037 | 5759 | first_error (_("parse error")); |
5287ad62 JB |
5760 | return FAIL; |
5761 | } | |
5762 | ||
5763 | /* Successfully parsed the operands. Update args. */ | |
5764 | *which_operand = i; | |
5765 | *str = ptr; | |
5766 | return SUCCESS; | |
5767 | ||
5f4273c7 | 5768 | wanted_comma: |
dcbf9037 | 5769 | first_error (_("expected comma")); |
5287ad62 | 5770 | return FAIL; |
5f4273c7 NC |
5771 | |
5772 | wanted_arm: | |
dcbf9037 | 5773 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
5287ad62 | 5774 | return FAIL; |
5287ad62 JB |
5775 | } |
5776 | ||
5be8be5d DG |
5777 | /* Use this macro when the operand constraints are different |
5778 | for ARM and THUMB (e.g. ldrd). */ | |
5779 | #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \ | |
5780 | ((arm_operand) | ((thumb_operand) << 16)) | |
5781 | ||
c19d1205 ZW |
5782 | /* Matcher codes for parse_operands. */ |
5783 | enum operand_parse_code | |
5784 | { | |
5785 | OP_stop, /* end of line */ | |
5786 | ||
5787 | OP_RR, /* ARM register */ | |
5788 | OP_RRnpc, /* ARM register, not r15 */ | |
5be8be5d | 5789 | OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */ |
c19d1205 | 5790 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ |
55881a11 MGD |
5791 | OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback, |
5792 | optional trailing ! */ | |
c19d1205 ZW |
5793 | OP_RRw, /* ARM register, not r15, optional trailing ! */ |
5794 | OP_RCP, /* Coprocessor number */ | |
5795 | OP_RCN, /* Coprocessor register */ | |
5796 | OP_RF, /* FPA register */ | |
5797 | OP_RVS, /* VFP single precision register */ | |
5287ad62 JB |
5798 | OP_RVD, /* VFP double precision register (0..15) */ |
5799 | OP_RND, /* Neon double precision register (0..31) */ | |
5800 | OP_RNQ, /* Neon quad precision register */ | |
037e8744 | 5801 | OP_RVSD, /* VFP single or double precision register */ |
5287ad62 | 5802 | OP_RNDQ, /* Neon double or quad precision register */ |
037e8744 | 5803 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
5287ad62 | 5804 | OP_RNSC, /* Neon scalar D[X] */ |
c19d1205 ZW |
5805 | OP_RVC, /* VFP control register */ |
5806 | OP_RMF, /* Maverick F register */ | |
5807 | OP_RMD, /* Maverick D register */ | |
5808 | OP_RMFX, /* Maverick FX register */ | |
5809 | OP_RMDX, /* Maverick DX register */ | |
5810 | OP_RMAX, /* Maverick AX register */ | |
5811 | OP_RMDS, /* Maverick DSPSC register */ | |
5812 | OP_RIWR, /* iWMMXt wR register */ | |
5813 | OP_RIWC, /* iWMMXt wC register */ | |
5814 | OP_RIWG, /* iWMMXt wCG register */ | |
5815 | OP_RXA, /* XScale accumulator register */ | |
5816 | ||
5817 | OP_REGLST, /* ARM register list */ | |
5818 | OP_VRSLST, /* VFP single-precision register list */ | |
5819 | OP_VRDLST, /* VFP double-precision register list */ | |
037e8744 | 5820 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
5287ad62 JB |
5821 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
5822 | OP_NSTRLST, /* Neon element/structure list */ | |
5823 | ||
5287ad62 | 5824 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ |
037e8744 | 5825 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
5287ad62 | 5826 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
037e8744 | 5827 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
5287ad62 JB |
5828 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
5829 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ | |
5830 | OP_VMOV, /* Neon VMOV operands. */ | |
4316f0d2 | 5831 | OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ |
5287ad62 | 5832 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ |
2d447fca | 5833 | OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ |
5287ad62 JB |
5834 | |
5835 | OP_I0, /* immediate zero */ | |
c19d1205 ZW |
5836 | OP_I7, /* immediate value 0 .. 7 */ |
5837 | OP_I15, /* 0 .. 15 */ | |
5838 | OP_I16, /* 1 .. 16 */ | |
5287ad62 | 5839 | OP_I16z, /* 0 .. 16 */ |
c19d1205 ZW |
5840 | OP_I31, /* 0 .. 31 */ |
5841 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
5842 | OP_I32, /* 1 .. 32 */ | |
5287ad62 JB |
5843 | OP_I32z, /* 0 .. 32 */ |
5844 | OP_I63, /* 0 .. 63 */ | |
c19d1205 | 5845 | OP_I63s, /* -64 .. 63 */ |
5287ad62 JB |
5846 | OP_I64, /* 1 .. 64 */ |
5847 | OP_I64z, /* 0 .. 64 */ | |
c19d1205 | 5848 | OP_I255, /* 0 .. 255 */ |
c19d1205 ZW |
5849 | |
5850 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
5851 | OP_I7b, /* 0 .. 7 */ | |
5852 | OP_I15b, /* 0 .. 15 */ | |
5853 | OP_I31b, /* 0 .. 31 */ | |
5854 | ||
5855 | OP_SH, /* shifter operand */ | |
4962c51a | 5856 | OP_SHG, /* shifter operand with possible group relocation */ |
c19d1205 | 5857 | OP_ADDR, /* Memory address expression (any mode) */ |
4962c51a MS |
5858 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
5859 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ | |
5860 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ | |
c19d1205 ZW |
5861 | OP_EXP, /* arbitrary expression */ |
5862 | OP_EXPi, /* same, with optional immediate prefix */ | |
5863 | OP_EXPr, /* same, with optional relocation suffix */ | |
b6895b4f | 5864 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
c19d1205 ZW |
5865 | |
5866 | OP_CPSF, /* CPS flags */ | |
5867 | OP_ENDI, /* Endianness specifier */ | |
5868 | OP_PSR, /* CPSR/SPSR mask for msr */ | |
5869 | OP_COND, /* conditional code */ | |
92e90b6e | 5870 | OP_TB, /* Table branch. */ |
c19d1205 | 5871 | |
037e8744 JB |
5872 | OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */ |
5873 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ | |
5874 | ||
c19d1205 ZW |
5875 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
5876 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
5877 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
5878 | OP_RF_IF, /* FPA register or immediate */ | |
5879 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
41adaa5c | 5880 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
c19d1205 ZW |
5881 | |
5882 | /* Optional operands. */ | |
5883 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
5884 | OP_oI31b, /* 0 .. 31 */ | |
5287ad62 | 5885 | OP_oI32b, /* 1 .. 32 */ |
c19d1205 ZW |
5886 | OP_oIffffb, /* 0 .. 65535 */ |
5887 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
5888 | ||
5889 | OP_oRR, /* ARM register */ | |
5890 | OP_oRRnpc, /* ARM register, not the PC */ | |
5be8be5d | 5891 | OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ |
b6702015 | 5892 | OP_oRRw, /* ARM register, not r15, optional trailing ! */ |
5287ad62 JB |
5893 | OP_oRND, /* Optional Neon double precision register */ |
5894 | OP_oRNQ, /* Optional Neon quad precision register */ | |
5895 | OP_oRNDQ, /* Optional Neon double or quad precision register */ | |
037e8744 | 5896 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
c19d1205 ZW |
5897 | OP_oSHll, /* LSL immediate */ |
5898 | OP_oSHar, /* ASR immediate */ | |
5899 | OP_oSHllar, /* LSL or ASR immediate */ | |
5900 | OP_oROR, /* ROR 0/8/16/24 */ | |
62b3e311 | 5901 | OP_oBARRIER, /* Option argument for a barrier instruction. */ |
c19d1205 | 5902 | |
5be8be5d DG |
5903 | /* Some pre-defined mixed (ARM/THUMB) operands. */ |
5904 | OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp), | |
5905 | OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp), | |
5906 | OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp), | |
5907 | ||
c19d1205 ZW |
5908 | OP_FIRST_OPTIONAL = OP_oI7b |
5909 | }; | |
a737bd4d | 5910 | |
c19d1205 ZW |
5911 | /* Generic instruction operand parser. This does no encoding and no |
5912 | semantic validation; it merely squirrels values away in the inst | |
5913 | structure. Returns SUCCESS or FAIL depending on whether the | |
5914 | specified grammar matched. */ | |
5915 | static int | |
5be8be5d | 5916 | parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) |
c19d1205 | 5917 | { |
5be8be5d | 5918 | unsigned const int *upat = pattern; |
c19d1205 ZW |
5919 | char *backtrack_pos = 0; |
5920 | const char *backtrack_error = 0; | |
5921 | int i, val, backtrack_index = 0; | |
5287ad62 | 5922 | enum arm_reg_type rtype; |
4962c51a | 5923 | parse_operand_result result; |
5be8be5d | 5924 | unsigned int op_parse_code; |
c19d1205 | 5925 | |
e07e6e58 NC |
5926 | #define po_char_or_fail(chr) \ |
5927 | do \ | |
5928 | { \ | |
5929 | if (skip_past_char (&str, chr) == FAIL) \ | |
5930 | goto bad_args; \ | |
5931 | } \ | |
5932 | while (0) | |
c19d1205 | 5933 | |
e07e6e58 NC |
5934 | #define po_reg_or_fail(regtype) \ |
5935 | do \ | |
dcbf9037 | 5936 | { \ |
e07e6e58 NC |
5937 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
5938 | & inst.operands[i].vectype); \ | |
5939 | if (val == FAIL) \ | |
5940 | { \ | |
5941 | first_error (_(reg_expected_msgs[regtype])); \ | |
5942 | goto failure; \ | |
5943 | } \ | |
5944 | inst.operands[i].reg = val; \ | |
5945 | inst.operands[i].isreg = 1; \ | |
5946 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
5947 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
5948 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
5949 | || rtype == REG_TYPE_VFD \ | |
5950 | || rtype == REG_TYPE_NQ); \ | |
dcbf9037 | 5951 | } \ |
e07e6e58 NC |
5952 | while (0) |
5953 | ||
5954 | #define po_reg_or_goto(regtype, label) \ | |
5955 | do \ | |
5956 | { \ | |
5957 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ | |
5958 | & inst.operands[i].vectype); \ | |
5959 | if (val == FAIL) \ | |
5960 | goto label; \ | |
dcbf9037 | 5961 | \ |
e07e6e58 NC |
5962 | inst.operands[i].reg = val; \ |
5963 | inst.operands[i].isreg = 1; \ | |
5964 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
5965 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
5966 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
5967 | || rtype == REG_TYPE_VFD \ | |
5968 | || rtype == REG_TYPE_NQ); \ | |
5969 | } \ | |
5970 | while (0) | |
5971 | ||
5972 | #define po_imm_or_fail(min, max, popt) \ | |
5973 | do \ | |
5974 | { \ | |
5975 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
5976 | goto failure; \ | |
5977 | inst.operands[i].imm = val; \ | |
5978 | } \ | |
5979 | while (0) | |
5980 | ||
5981 | #define po_scalar_or_goto(elsz, label) \ | |
5982 | do \ | |
5983 | { \ | |
5984 | val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \ | |
5985 | if (val == FAIL) \ | |
5986 | goto label; \ | |
5987 | inst.operands[i].reg = val; \ | |
5988 | inst.operands[i].isscalar = 1; \ | |
5989 | } \ | |
5990 | while (0) | |
5991 | ||
5992 | #define po_misc_or_fail(expr) \ | |
5993 | do \ | |
5994 | { \ | |
5995 | if (expr) \ | |
5996 | goto failure; \ | |
5997 | } \ | |
5998 | while (0) | |
5999 | ||
6000 | #define po_misc_or_fail_no_backtrack(expr) \ | |
6001 | do \ | |
6002 | { \ | |
6003 | result = expr; \ | |
6004 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ | |
6005 | backtrack_pos = 0; \ | |
6006 | if (result != PARSE_OPERAND_SUCCESS) \ | |
6007 | goto failure; \ | |
6008 | } \ | |
6009 | while (0) | |
4962c51a | 6010 | |
c19d1205 ZW |
6011 | skip_whitespace (str); |
6012 | ||
6013 | for (i = 0; upat[i] != OP_stop; i++) | |
6014 | { | |
5be8be5d DG |
6015 | op_parse_code = upat[i]; |
6016 | if (op_parse_code >= 1<<16) | |
6017 | op_parse_code = thumb ? (op_parse_code >> 16) | |
6018 | : (op_parse_code & ((1<<16)-1)); | |
6019 | ||
6020 | if (op_parse_code >= OP_FIRST_OPTIONAL) | |
c19d1205 ZW |
6021 | { |
6022 | /* Remember where we are in case we need to backtrack. */ | |
9c2799c2 | 6023 | gas_assert (!backtrack_pos); |
c19d1205 ZW |
6024 | backtrack_pos = str; |
6025 | backtrack_error = inst.error; | |
6026 | backtrack_index = i; | |
6027 | } | |
6028 | ||
b6702015 | 6029 | if (i > 0 && (i > 1 || inst.operands[0].present)) |
c19d1205 ZW |
6030 | po_char_or_fail (','); |
6031 | ||
5be8be5d | 6032 | switch (op_parse_code) |
c19d1205 ZW |
6033 | { |
6034 | /* Registers */ | |
6035 | case OP_oRRnpc: | |
5be8be5d | 6036 | case OP_oRRnpcsp: |
c19d1205 | 6037 | case OP_RRnpc: |
5be8be5d | 6038 | case OP_RRnpcsp: |
c19d1205 ZW |
6039 | case OP_oRR: |
6040 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
6041 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
6042 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
6043 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
6044 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
6045 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
5287ad62 JB |
6046 | case OP_oRND: |
6047 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; | |
cd2cf30b PB |
6048 | case OP_RVC: |
6049 | po_reg_or_goto (REG_TYPE_VFC, coproc_reg); | |
6050 | break; | |
6051 | /* Also accept generic coprocessor regs for unknown registers. */ | |
6052 | coproc_reg: | |
6053 | po_reg_or_fail (REG_TYPE_CN); | |
6054 | break; | |
c19d1205 ZW |
6055 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; |
6056 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
6057 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
6058 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
6059 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
6060 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
6061 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
6062 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
6063 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
6064 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
5287ad62 JB |
6065 | case OP_oRNQ: |
6066 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; | |
6067 | case OP_oRNDQ: | |
6068 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; | |
037e8744 JB |
6069 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
6070 | case OP_oRNSDQ: | |
6071 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; | |
5287ad62 JB |
6072 | |
6073 | /* Neon scalar. Using an element size of 8 means that some invalid | |
6074 | scalars are accepted here, so deal with those in later code. */ | |
6075 | case OP_RNSC: po_scalar_or_goto (8, failure); break; | |
6076 | ||
5287ad62 JB |
6077 | case OP_RNDQ_I0: |
6078 | { | |
6079 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); | |
6080 | break; | |
6081 | try_imm0: | |
6082 | po_imm_or_fail (0, 0, TRUE); | |
6083 | } | |
6084 | break; | |
6085 | ||
037e8744 JB |
6086 | case OP_RVSD_I0: |
6087 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); | |
6088 | break; | |
6089 | ||
5287ad62 JB |
6090 | case OP_RR_RNSC: |
6091 | { | |
6092 | po_scalar_or_goto (8, try_rr); | |
6093 | break; | |
6094 | try_rr: | |
6095 | po_reg_or_fail (REG_TYPE_RN); | |
6096 | } | |
6097 | break; | |
6098 | ||
037e8744 JB |
6099 | case OP_RNSDQ_RNSC: |
6100 | { | |
6101 | po_scalar_or_goto (8, try_nsdq); | |
6102 | break; | |
6103 | try_nsdq: | |
6104 | po_reg_or_fail (REG_TYPE_NSDQ); | |
6105 | } | |
6106 | break; | |
6107 | ||
5287ad62 JB |
6108 | case OP_RNDQ_RNSC: |
6109 | { | |
6110 | po_scalar_or_goto (8, try_ndq); | |
6111 | break; | |
6112 | try_ndq: | |
6113 | po_reg_or_fail (REG_TYPE_NDQ); | |
6114 | } | |
6115 | break; | |
6116 | ||
6117 | case OP_RND_RNSC: | |
6118 | { | |
6119 | po_scalar_or_goto (8, try_vfd); | |
6120 | break; | |
6121 | try_vfd: | |
6122 | po_reg_or_fail (REG_TYPE_VFD); | |
6123 | } | |
6124 | break; | |
6125 | ||
6126 | case OP_VMOV: | |
6127 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're | |
6128 | not careful then bad things might happen. */ | |
6129 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); | |
6130 | break; | |
6131 | ||
4316f0d2 | 6132 | case OP_RNDQ_Ibig: |
5287ad62 | 6133 | { |
4316f0d2 | 6134 | po_reg_or_goto (REG_TYPE_NDQ, try_immbig); |
5287ad62 | 6135 | break; |
4316f0d2 | 6136 | try_immbig: |
5287ad62 JB |
6137 | /* There's a possibility of getting a 64-bit immediate here, so |
6138 | we need special handling. */ | |
6139 | if (parse_big_immediate (&str, i) == FAIL) | |
6140 | { | |
6141 | inst.error = _("immediate value is out of range"); | |
6142 | goto failure; | |
6143 | } | |
6144 | } | |
6145 | break; | |
6146 | ||
6147 | case OP_RNDQ_I63b: | |
6148 | { | |
6149 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); | |
6150 | break; | |
6151 | try_shimm: | |
6152 | po_imm_or_fail (0, 63, TRUE); | |
6153 | } | |
6154 | break; | |
c19d1205 ZW |
6155 | |
6156 | case OP_RRnpcb: | |
6157 | po_char_or_fail ('['); | |
6158 | po_reg_or_fail (REG_TYPE_RN); | |
6159 | po_char_or_fail (']'); | |
6160 | break; | |
a737bd4d | 6161 | |
55881a11 | 6162 | case OP_RRnpctw: |
c19d1205 | 6163 | case OP_RRw: |
b6702015 | 6164 | case OP_oRRw: |
c19d1205 ZW |
6165 | po_reg_or_fail (REG_TYPE_RN); |
6166 | if (skip_past_char (&str, '!') == SUCCESS) | |
6167 | inst.operands[i].writeback = 1; | |
6168 | break; | |
6169 | ||
6170 | /* Immediates */ | |
6171 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
6172 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
6173 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
5287ad62 | 6174 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
c19d1205 ZW |
6175 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
6176 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
5287ad62 | 6177 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
c19d1205 | 6178 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
5287ad62 JB |
6179 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
6180 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; | |
6181 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; | |
c19d1205 | 6182 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
c19d1205 ZW |
6183 | |
6184 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
6185 | case OP_oI7b: | |
6186 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
6187 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
6188 | case OP_oI31b: | |
6189 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
5287ad62 | 6190 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
c19d1205 ZW |
6191 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
6192 | ||
6193 | /* Immediate variants */ | |
6194 | case OP_oI255c: | |
6195 | po_char_or_fail ('{'); | |
6196 | po_imm_or_fail (0, 255, TRUE); | |
6197 | po_char_or_fail ('}'); | |
6198 | break; | |
6199 | ||
6200 | case OP_I31w: | |
6201 | /* The expression parser chokes on a trailing !, so we have | |
6202 | to find it first and zap it. */ | |
6203 | { | |
6204 | char *s = str; | |
6205 | while (*s && *s != ',') | |
6206 | s++; | |
6207 | if (s[-1] == '!') | |
6208 | { | |
6209 | s[-1] = '\0'; | |
6210 | inst.operands[i].writeback = 1; | |
6211 | } | |
6212 | po_imm_or_fail (0, 31, TRUE); | |
6213 | if (str == s - 1) | |
6214 | str = s; | |
6215 | } | |
6216 | break; | |
6217 | ||
6218 | /* Expressions */ | |
6219 | case OP_EXPi: EXPi: | |
6220 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6221 | GE_OPT_PREFIX)); | |
6222 | break; | |
6223 | ||
6224 | case OP_EXP: | |
6225 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6226 | GE_NO_PREFIX)); | |
6227 | break; | |
6228 | ||
6229 | case OP_EXPr: EXPr: | |
6230 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6231 | GE_NO_PREFIX)); | |
6232 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 6233 | { |
c19d1205 ZW |
6234 | val = parse_reloc (&str); |
6235 | if (val == -1) | |
6236 | { | |
6237 | inst.error = _("unrecognized relocation suffix"); | |
6238 | goto failure; | |
6239 | } | |
6240 | else if (val != BFD_RELOC_UNUSED) | |
6241 | { | |
6242 | inst.operands[i].imm = val; | |
6243 | inst.operands[i].hasreloc = 1; | |
6244 | } | |
a737bd4d | 6245 | } |
c19d1205 | 6246 | break; |
a737bd4d | 6247 | |
b6895b4f PB |
6248 | /* Operand for MOVW or MOVT. */ |
6249 | case OP_HALF: | |
6250 | po_misc_or_fail (parse_half (&str)); | |
6251 | break; | |
6252 | ||
e07e6e58 | 6253 | /* Register or expression. */ |
c19d1205 ZW |
6254 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; |
6255 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 6256 | |
e07e6e58 | 6257 | /* Register or immediate. */ |
c19d1205 ZW |
6258 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; |
6259 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 6260 | |
c19d1205 ZW |
6261 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
6262 | IF: | |
6263 | if (!is_immediate_prefix (*str)) | |
6264 | goto bad_args; | |
6265 | str++; | |
6266 | val = parse_fpa_immediate (&str); | |
6267 | if (val == FAIL) | |
6268 | goto failure; | |
6269 | /* FPA immediates are encoded as registers 8-15. | |
6270 | parse_fpa_immediate has already applied the offset. */ | |
6271 | inst.operands[i].reg = val; | |
6272 | inst.operands[i].isreg = 1; | |
6273 | break; | |
09d92015 | 6274 | |
2d447fca JM |
6275 | case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; |
6276 | I32z: po_imm_or_fail (0, 32, FALSE); break; | |
6277 | ||
e07e6e58 | 6278 | /* Two kinds of register. */ |
c19d1205 ZW |
6279 | case OP_RIWR_RIWC: |
6280 | { | |
6281 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
97f87066 JM |
6282 | if (!rege |
6283 | || (rege->type != REG_TYPE_MMXWR | |
6284 | && rege->type != REG_TYPE_MMXWC | |
6285 | && rege->type != REG_TYPE_MMXWCG)) | |
c19d1205 ZW |
6286 | { |
6287 | inst.error = _("iWMMXt data or control register expected"); | |
6288 | goto failure; | |
6289 | } | |
6290 | inst.operands[i].reg = rege->number; | |
6291 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
6292 | } | |
6293 | break; | |
09d92015 | 6294 | |
41adaa5c JM |
6295 | case OP_RIWC_RIWG: |
6296 | { | |
6297 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
6298 | if (!rege | |
6299 | || (rege->type != REG_TYPE_MMXWC | |
6300 | && rege->type != REG_TYPE_MMXWCG)) | |
6301 | { | |
6302 | inst.error = _("iWMMXt control register expected"); | |
6303 | goto failure; | |
6304 | } | |
6305 | inst.operands[i].reg = rege->number; | |
6306 | inst.operands[i].isreg = 1; | |
6307 | } | |
6308 | break; | |
6309 | ||
c19d1205 ZW |
6310 | /* Misc */ |
6311 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
6312 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
6313 | case OP_oROR: val = parse_ror (&str); break; | |
6314 | case OP_PSR: val = parse_psr (&str); break; | |
6315 | case OP_COND: val = parse_cond (&str); break; | |
62b3e311 | 6316 | case OP_oBARRIER:val = parse_barrier (&str); break; |
c19d1205 | 6317 | |
037e8744 JB |
6318 | case OP_RVC_PSR: |
6319 | po_reg_or_goto (REG_TYPE_VFC, try_psr); | |
6320 | inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */ | |
6321 | break; | |
6322 | try_psr: | |
6323 | val = parse_psr (&str); | |
6324 | break; | |
6325 | ||
6326 | case OP_APSR_RR: | |
6327 | po_reg_or_goto (REG_TYPE_RN, try_apsr); | |
6328 | break; | |
6329 | try_apsr: | |
6330 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS | |
6331 | instruction). */ | |
6332 | if (strncasecmp (str, "APSR_", 5) == 0) | |
6333 | { | |
6334 | unsigned found = 0; | |
6335 | str += 5; | |
6336 | while (found < 15) | |
6337 | switch (*str++) | |
6338 | { | |
6339 | case 'c': found = (found & 1) ? 16 : found | 1; break; | |
6340 | case 'n': found = (found & 2) ? 16 : found | 2; break; | |
6341 | case 'z': found = (found & 4) ? 16 : found | 4; break; | |
6342 | case 'v': found = (found & 8) ? 16 : found | 8; break; | |
6343 | default: found = 16; | |
6344 | } | |
6345 | if (found != 15) | |
6346 | goto failure; | |
6347 | inst.operands[i].isvec = 1; | |
f7c21dc7 NC |
6348 | /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */ |
6349 | inst.operands[i].reg = REG_PC; | |
037e8744 JB |
6350 | } |
6351 | else | |
6352 | goto failure; | |
6353 | break; | |
6354 | ||
92e90b6e PB |
6355 | case OP_TB: |
6356 | po_misc_or_fail (parse_tb (&str)); | |
6357 | break; | |
6358 | ||
e07e6e58 | 6359 | /* Register lists. */ |
c19d1205 ZW |
6360 | case OP_REGLST: |
6361 | val = parse_reg_list (&str); | |
6362 | if (*str == '^') | |
6363 | { | |
6364 | inst.operands[1].writeback = 1; | |
6365 | str++; | |
6366 | } | |
6367 | break; | |
09d92015 | 6368 | |
c19d1205 | 6369 | case OP_VRSLST: |
5287ad62 | 6370 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); |
c19d1205 | 6371 | break; |
09d92015 | 6372 | |
c19d1205 | 6373 | case OP_VRDLST: |
5287ad62 | 6374 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); |
c19d1205 | 6375 | break; |
a737bd4d | 6376 | |
037e8744 JB |
6377 | case OP_VRSDLST: |
6378 | /* Allow Q registers too. */ | |
6379 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6380 | REGLIST_NEON_D); | |
6381 | if (val == FAIL) | |
6382 | { | |
6383 | inst.error = NULL; | |
6384 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6385 | REGLIST_VFP_S); | |
6386 | inst.operands[i].issingle = 1; | |
6387 | } | |
6388 | break; | |
6389 | ||
5287ad62 JB |
6390 | case OP_NRDLST: |
6391 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6392 | REGLIST_NEON_D); | |
6393 | break; | |
6394 | ||
6395 | case OP_NSTRLST: | |
dcbf9037 JB |
6396 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
6397 | &inst.operands[i].vectype); | |
5287ad62 JB |
6398 | break; |
6399 | ||
c19d1205 ZW |
6400 | /* Addressing modes */ |
6401 | case OP_ADDR: | |
6402 | po_misc_or_fail (parse_address (&str, i)); | |
6403 | break; | |
09d92015 | 6404 | |
4962c51a MS |
6405 | case OP_ADDRGLDR: |
6406 | po_misc_or_fail_no_backtrack ( | |
6407 | parse_address_group_reloc (&str, i, GROUP_LDR)); | |
6408 | break; | |
6409 | ||
6410 | case OP_ADDRGLDRS: | |
6411 | po_misc_or_fail_no_backtrack ( | |
6412 | parse_address_group_reloc (&str, i, GROUP_LDRS)); | |
6413 | break; | |
6414 | ||
6415 | case OP_ADDRGLDC: | |
6416 | po_misc_or_fail_no_backtrack ( | |
6417 | parse_address_group_reloc (&str, i, GROUP_LDC)); | |
6418 | break; | |
6419 | ||
c19d1205 ZW |
6420 | case OP_SH: |
6421 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
6422 | break; | |
09d92015 | 6423 | |
4962c51a MS |
6424 | case OP_SHG: |
6425 | po_misc_or_fail_no_backtrack ( | |
6426 | parse_shifter_operand_group_reloc (&str, i)); | |
6427 | break; | |
6428 | ||
c19d1205 ZW |
6429 | case OP_oSHll: |
6430 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
6431 | break; | |
09d92015 | 6432 | |
c19d1205 ZW |
6433 | case OP_oSHar: |
6434 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
6435 | break; | |
09d92015 | 6436 | |
c19d1205 ZW |
6437 | case OP_oSHllar: |
6438 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
6439 | break; | |
09d92015 | 6440 | |
c19d1205 | 6441 | default: |
5be8be5d | 6442 | as_fatal (_("unhandled operand code %d"), op_parse_code); |
c19d1205 | 6443 | } |
09d92015 | 6444 | |
c19d1205 ZW |
6445 | /* Various value-based sanity checks and shared operations. We |
6446 | do not signal immediate failures for the register constraints; | |
6447 | this allows a syntax error to take precedence. */ | |
5be8be5d | 6448 | switch (op_parse_code) |
c19d1205 ZW |
6449 | { |
6450 | case OP_oRRnpc: | |
6451 | case OP_RRnpc: | |
6452 | case OP_RRnpcb: | |
6453 | case OP_RRw: | |
b6702015 | 6454 | case OP_oRRw: |
c19d1205 ZW |
6455 | case OP_RRnpc_I0: |
6456 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
6457 | inst.error = BAD_PC; | |
6458 | break; | |
09d92015 | 6459 | |
5be8be5d DG |
6460 | case OP_oRRnpcsp: |
6461 | case OP_RRnpcsp: | |
6462 | if (inst.operands[i].isreg) | |
6463 | { | |
6464 | if (inst.operands[i].reg == REG_PC) | |
6465 | inst.error = BAD_PC; | |
6466 | else if (inst.operands[i].reg == REG_SP) | |
6467 | inst.error = BAD_SP; | |
6468 | } | |
6469 | break; | |
6470 | ||
55881a11 MGD |
6471 | case OP_RRnpctw: |
6472 | if (inst.operands[i].isreg | |
6473 | && inst.operands[i].reg == REG_PC | |
6474 | && (inst.operands[i].writeback || thumb)) | |
6475 | inst.error = BAD_PC; | |
6476 | break; | |
6477 | ||
c19d1205 ZW |
6478 | case OP_CPSF: |
6479 | case OP_ENDI: | |
6480 | case OP_oROR: | |
6481 | case OP_PSR: | |
037e8744 | 6482 | case OP_RVC_PSR: |
c19d1205 | 6483 | case OP_COND: |
62b3e311 | 6484 | case OP_oBARRIER: |
c19d1205 ZW |
6485 | case OP_REGLST: |
6486 | case OP_VRSLST: | |
6487 | case OP_VRDLST: | |
037e8744 | 6488 | case OP_VRSDLST: |
5287ad62 JB |
6489 | case OP_NRDLST: |
6490 | case OP_NSTRLST: | |
c19d1205 ZW |
6491 | if (val == FAIL) |
6492 | goto failure; | |
6493 | inst.operands[i].imm = val; | |
6494 | break; | |
a737bd4d | 6495 | |
c19d1205 ZW |
6496 | default: |
6497 | break; | |
6498 | } | |
09d92015 | 6499 | |
c19d1205 ZW |
6500 | /* If we get here, this operand was successfully parsed. */ |
6501 | inst.operands[i].present = 1; | |
6502 | continue; | |
09d92015 | 6503 | |
c19d1205 | 6504 | bad_args: |
09d92015 | 6505 | inst.error = BAD_ARGS; |
c19d1205 ZW |
6506 | |
6507 | failure: | |
6508 | if (!backtrack_pos) | |
d252fdde PB |
6509 | { |
6510 | /* The parse routine should already have set inst.error, but set a | |
5f4273c7 | 6511 | default here just in case. */ |
d252fdde PB |
6512 | if (!inst.error) |
6513 | inst.error = _("syntax error"); | |
6514 | return FAIL; | |
6515 | } | |
c19d1205 ZW |
6516 | |
6517 | /* Do not backtrack over a trailing optional argument that | |
6518 | absorbed some text. We will only fail again, with the | |
6519 | 'garbage following instruction' error message, which is | |
6520 | probably less helpful than the current one. */ | |
6521 | if (backtrack_index == i && backtrack_pos != str | |
6522 | && upat[i+1] == OP_stop) | |
d252fdde PB |
6523 | { |
6524 | if (!inst.error) | |
6525 | inst.error = _("syntax error"); | |
6526 | return FAIL; | |
6527 | } | |
c19d1205 ZW |
6528 | |
6529 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
6530 | str = backtrack_pos; | |
6531 | inst.error = backtrack_error; | |
6532 | inst.operands[backtrack_index].present = 0; | |
6533 | i = backtrack_index; | |
6534 | backtrack_pos = 0; | |
09d92015 | 6535 | } |
09d92015 | 6536 | |
c19d1205 ZW |
6537 | /* Check that we have parsed all the arguments. */ |
6538 | if (*str != '\0' && !inst.error) | |
6539 | inst.error = _("garbage following instruction"); | |
09d92015 | 6540 | |
c19d1205 | 6541 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
6542 | } |
6543 | ||
c19d1205 ZW |
6544 | #undef po_char_or_fail |
6545 | #undef po_reg_or_fail | |
6546 | #undef po_reg_or_goto | |
6547 | #undef po_imm_or_fail | |
5287ad62 | 6548 | #undef po_scalar_or_fail |
e07e6e58 | 6549 | |
c19d1205 | 6550 | /* Shorthand macro for instruction encoding functions issuing errors. */ |
e07e6e58 NC |
6551 | #define constraint(expr, err) \ |
6552 | do \ | |
c19d1205 | 6553 | { \ |
e07e6e58 NC |
6554 | if (expr) \ |
6555 | { \ | |
6556 | inst.error = err; \ | |
6557 | return; \ | |
6558 | } \ | |
c19d1205 | 6559 | } \ |
e07e6e58 | 6560 | while (0) |
c19d1205 | 6561 | |
fdfde340 JM |
6562 | /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 |
6563 | instructions are unpredictable if these registers are used. This | |
6564 | is the BadReg predicate in ARM's Thumb-2 documentation. */ | |
6565 | #define reject_bad_reg(reg) \ | |
6566 | do \ | |
6567 | if (reg == REG_SP || reg == REG_PC) \ | |
6568 | { \ | |
6569 | inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \ | |
6570 | return; \ | |
6571 | } \ | |
6572 | while (0) | |
6573 | ||
94206790 MM |
6574 | /* If REG is R13 (the stack pointer), warn that its use is |
6575 | deprecated. */ | |
6576 | #define warn_deprecated_sp(reg) \ | |
6577 | do \ | |
6578 | if (warn_on_deprecated && reg == REG_SP) \ | |
6579 | as_warn (_("use of r13 is deprecated")); \ | |
6580 | while (0) | |
6581 | ||
c19d1205 ZW |
6582 | /* Functions for operand encoding. ARM, then Thumb. */ |
6583 | ||
6584 | #define rotate_left(v, n) (v << n | v >> (32 - n)) | |
6585 | ||
6586 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
6587 | return the encoded form. Otherwise, return FAIL. */ | |
6588 | ||
6589 | static unsigned int | |
6590 | encode_arm_immediate (unsigned int val) | |
09d92015 | 6591 | { |
c19d1205 ZW |
6592 | unsigned int a, i; |
6593 | ||
6594 | for (i = 0; i < 32; i += 2) | |
6595 | if ((a = rotate_left (val, i)) <= 0xff) | |
6596 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
6597 | ||
6598 | return FAIL; | |
09d92015 MM |
6599 | } |
6600 | ||
c19d1205 ZW |
6601 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
6602 | return the encoded form. Otherwise, return FAIL. */ | |
6603 | static unsigned int | |
6604 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 6605 | { |
c19d1205 | 6606 | unsigned int a, i; |
09d92015 | 6607 | |
9c3c69f2 | 6608 | if (val <= 0xff) |
c19d1205 | 6609 | return val; |
a737bd4d | 6610 | |
9c3c69f2 | 6611 | for (i = 1; i <= 24; i++) |
09d92015 | 6612 | { |
9c3c69f2 PB |
6613 | a = val >> i; |
6614 | if ((val & ~(0xff << i)) == 0) | |
6615 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 6616 | } |
a737bd4d | 6617 | |
c19d1205 ZW |
6618 | a = val & 0xff; |
6619 | if (val == ((a << 16) | a)) | |
6620 | return 0x100 | a; | |
6621 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
6622 | return 0x300 | a; | |
09d92015 | 6623 | |
c19d1205 ZW |
6624 | a = val & 0xff00; |
6625 | if (val == ((a << 16) | a)) | |
6626 | return 0x200 | (a >> 8); | |
a737bd4d | 6627 | |
c19d1205 | 6628 | return FAIL; |
09d92015 | 6629 | } |
5287ad62 | 6630 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
09d92015 MM |
6631 | |
6632 | static void | |
5287ad62 JB |
6633 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
6634 | { | |
6635 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) | |
6636 | && reg > 15) | |
6637 | { | |
b1cc4aeb | 6638 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
5287ad62 JB |
6639 | { |
6640 | if (thumb_mode) | |
6641 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 6642 | fpu_vfp_ext_d32); |
5287ad62 JB |
6643 | else |
6644 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 6645 | fpu_vfp_ext_d32); |
5287ad62 JB |
6646 | } |
6647 | else | |
6648 | { | |
dcbf9037 | 6649 | first_error (_("D register out of range for selected VFP version")); |
5287ad62 JB |
6650 | return; |
6651 | } | |
6652 | } | |
6653 | ||
c19d1205 | 6654 | switch (pos) |
09d92015 | 6655 | { |
c19d1205 ZW |
6656 | case VFP_REG_Sd: |
6657 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
6658 | break; | |
6659 | ||
6660 | case VFP_REG_Sn: | |
6661 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
6662 | break; | |
6663 | ||
6664 | case VFP_REG_Sm: | |
6665 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
6666 | break; | |
6667 | ||
5287ad62 JB |
6668 | case VFP_REG_Dd: |
6669 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); | |
6670 | break; | |
5f4273c7 | 6671 | |
5287ad62 JB |
6672 | case VFP_REG_Dn: |
6673 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); | |
6674 | break; | |
5f4273c7 | 6675 | |
5287ad62 JB |
6676 | case VFP_REG_Dm: |
6677 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); | |
6678 | break; | |
6679 | ||
c19d1205 ZW |
6680 | default: |
6681 | abort (); | |
09d92015 | 6682 | } |
09d92015 MM |
6683 | } |
6684 | ||
c19d1205 | 6685 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 6686 | if any, is handled by md_apply_fix. */ |
09d92015 | 6687 | static void |
c19d1205 | 6688 | encode_arm_shift (int i) |
09d92015 | 6689 | { |
c19d1205 ZW |
6690 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
6691 | inst.instruction |= SHIFT_ROR << 5; | |
6692 | else | |
09d92015 | 6693 | { |
c19d1205 ZW |
6694 | inst.instruction |= inst.operands[i].shift_kind << 5; |
6695 | if (inst.operands[i].immisreg) | |
6696 | { | |
6697 | inst.instruction |= SHIFT_BY_REG; | |
6698 | inst.instruction |= inst.operands[i].imm << 8; | |
6699 | } | |
6700 | else | |
6701 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 6702 | } |
c19d1205 | 6703 | } |
09d92015 | 6704 | |
c19d1205 ZW |
6705 | static void |
6706 | encode_arm_shifter_operand (int i) | |
6707 | { | |
6708 | if (inst.operands[i].isreg) | |
09d92015 | 6709 | { |
c19d1205 ZW |
6710 | inst.instruction |= inst.operands[i].reg; |
6711 | encode_arm_shift (i); | |
09d92015 | 6712 | } |
c19d1205 ZW |
6713 | else |
6714 | inst.instruction |= INST_IMMEDIATE; | |
09d92015 MM |
6715 | } |
6716 | ||
c19d1205 | 6717 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 6718 | static void |
c19d1205 | 6719 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 6720 | { |
9c2799c2 | 6721 | gas_assert (inst.operands[i].isreg); |
c19d1205 | 6722 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 6723 | |
c19d1205 | 6724 | if (inst.operands[i].preind) |
09d92015 | 6725 | { |
c19d1205 ZW |
6726 | if (is_t) |
6727 | { | |
6728 | inst.error = _("instruction does not accept preindexed addressing"); | |
6729 | return; | |
6730 | } | |
6731 | inst.instruction |= PRE_INDEX; | |
6732 | if (inst.operands[i].writeback) | |
6733 | inst.instruction |= WRITE_BACK; | |
09d92015 | 6734 | |
c19d1205 ZW |
6735 | } |
6736 | else if (inst.operands[i].postind) | |
6737 | { | |
9c2799c2 | 6738 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
6739 | if (is_t) |
6740 | inst.instruction |= WRITE_BACK; | |
6741 | } | |
6742 | else /* unindexed - only for coprocessor */ | |
09d92015 | 6743 | { |
c19d1205 | 6744 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
6745 | return; |
6746 | } | |
6747 | ||
c19d1205 ZW |
6748 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
6749 | && (((inst.instruction & 0x000f0000) >> 16) | |
6750 | == ((inst.instruction & 0x0000f000) >> 12))) | |
6751 | as_warn ((inst.instruction & LOAD_BIT) | |
6752 | ? _("destination register same as write-back base") | |
6753 | : _("source register same as write-back base")); | |
09d92015 MM |
6754 | } |
6755 | ||
c19d1205 ZW |
6756 | /* inst.operands[i] was set up by parse_address. Encode it into an |
6757 | ARM-format mode 2 load or store instruction. If is_t is true, | |
6758 | reject forms that cannot be used with a T instruction (i.e. not | |
6759 | post-indexed). */ | |
a737bd4d | 6760 | static void |
c19d1205 | 6761 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 6762 | { |
5be8be5d DG |
6763 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
6764 | ||
c19d1205 | 6765 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 6766 | |
c19d1205 | 6767 | if (inst.operands[i].immisreg) |
09d92015 | 6768 | { |
5be8be5d DG |
6769 | constraint ((inst.operands[i].imm == REG_PC |
6770 | || (is_pc && inst.operands[i].writeback)), | |
6771 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
6772 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
6773 | inst.instruction |= inst.operands[i].imm; | |
6774 | if (!inst.operands[i].negative) | |
6775 | inst.instruction |= INDEX_UP; | |
6776 | if (inst.operands[i].shifted) | |
6777 | { | |
6778 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
6779 | inst.instruction |= SHIFT_ROR << 5; | |
6780 | else | |
6781 | { | |
6782 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
6783 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
6784 | } | |
6785 | } | |
09d92015 | 6786 | } |
c19d1205 | 6787 | else /* immediate offset in inst.reloc */ |
09d92015 | 6788 | { |
5be8be5d DG |
6789 | if (is_pc && !inst.reloc.pc_rel) |
6790 | { | |
6791 | const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0); | |
6792 | /* BAD_PC_ADDRESSING Condition = | |
6793 | is_load => is_t | |
6794 | which becomes !is_load || is_t. */ | |
6795 | constraint ((!is_load || is_t), | |
6796 | BAD_PC_ADDRESSING); | |
6797 | } | |
6798 | ||
c19d1205 ZW |
6799 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
6800 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
09d92015 | 6801 | } |
09d92015 MM |
6802 | } |
6803 | ||
c19d1205 ZW |
6804 | /* inst.operands[i] was set up by parse_address. Encode it into an |
6805 | ARM-format mode 3 load or store instruction. Reject forms that | |
6806 | cannot be used with such instructions. If is_t is true, reject | |
6807 | forms that cannot be used with a T instruction (i.e. not | |
6808 | post-indexed). */ | |
6809 | static void | |
6810 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 6811 | { |
c19d1205 | 6812 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 6813 | { |
c19d1205 ZW |
6814 | inst.error = _("instruction does not accept scaled register index"); |
6815 | return; | |
09d92015 | 6816 | } |
a737bd4d | 6817 | |
c19d1205 | 6818 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 6819 | |
c19d1205 ZW |
6820 | if (inst.operands[i].immisreg) |
6821 | { | |
5be8be5d DG |
6822 | constraint ((inst.operands[i].imm == REG_PC |
6823 | || inst.operands[i].reg == REG_PC), | |
6824 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
6825 | inst.instruction |= inst.operands[i].imm; |
6826 | if (!inst.operands[i].negative) | |
6827 | inst.instruction |= INDEX_UP; | |
6828 | } | |
6829 | else /* immediate offset in inst.reloc */ | |
6830 | { | |
5be8be5d DG |
6831 | constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel |
6832 | && inst.operands[i].writeback), | |
6833 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
6834 | inst.instruction |= HWOFFSET_IMM; |
6835 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
6836 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
c19d1205 | 6837 | } |
a737bd4d NC |
6838 | } |
6839 | ||
c19d1205 ZW |
6840 | /* inst.operands[i] was set up by parse_address. Encode it into an |
6841 | ARM-format instruction. Reject all forms which cannot be encoded | |
6842 | into a coprocessor load/store instruction. If wb_ok is false, | |
6843 | reject use of writeback; if unind_ok is false, reject use of | |
6844 | unindexed addressing. If reloc_override is not 0, use it instead | |
4962c51a MS |
6845 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one |
6846 | (in which case it is preserved). */ | |
09d92015 | 6847 | |
c19d1205 ZW |
6848 | static int |
6849 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
09d92015 | 6850 | { |
c19d1205 | 6851 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 6852 | |
9c2799c2 | 6853 | gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); |
09d92015 | 6854 | |
c19d1205 | 6855 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ |
09d92015 | 6856 | { |
9c2799c2 | 6857 | gas_assert (!inst.operands[i].writeback); |
c19d1205 ZW |
6858 | if (!unind_ok) |
6859 | { | |
6860 | inst.error = _("instruction does not support unindexed addressing"); | |
6861 | return FAIL; | |
6862 | } | |
6863 | inst.instruction |= inst.operands[i].imm; | |
6864 | inst.instruction |= INDEX_UP; | |
6865 | return SUCCESS; | |
09d92015 | 6866 | } |
a737bd4d | 6867 | |
c19d1205 ZW |
6868 | if (inst.operands[i].preind) |
6869 | inst.instruction |= PRE_INDEX; | |
a737bd4d | 6870 | |
c19d1205 | 6871 | if (inst.operands[i].writeback) |
09d92015 | 6872 | { |
c19d1205 ZW |
6873 | if (inst.operands[i].reg == REG_PC) |
6874 | { | |
6875 | inst.error = _("pc may not be used with write-back"); | |
6876 | return FAIL; | |
6877 | } | |
6878 | if (!wb_ok) | |
6879 | { | |
6880 | inst.error = _("instruction does not support writeback"); | |
6881 | return FAIL; | |
6882 | } | |
6883 | inst.instruction |= WRITE_BACK; | |
09d92015 | 6884 | } |
a737bd4d | 6885 | |
c19d1205 | 6886 | if (reloc_override) |
21d799b5 | 6887 | inst.reloc.type = (bfd_reloc_code_real_type) reloc_override; |
4962c51a MS |
6888 | else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC |
6889 | || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) | |
6890 | && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) | |
6891 | { | |
6892 | if (thumb_mode) | |
6893 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
6894 | else | |
6895 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
6896 | } | |
6897 | ||
c19d1205 ZW |
6898 | return SUCCESS; |
6899 | } | |
a737bd4d | 6900 | |
c19d1205 ZW |
6901 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
6902 | Determine whether it can be performed with a move instruction; if | |
6903 | it can, convert inst.instruction to that move instruction and | |
c921be7d NC |
6904 | return TRUE; if it can't, convert inst.instruction to a literal-pool |
6905 | load and return FALSE. If this is not a valid thing to do in the | |
6906 | current context, set inst.error and return TRUE. | |
a737bd4d | 6907 | |
c19d1205 ZW |
6908 | inst.operands[i] describes the destination register. */ |
6909 | ||
c921be7d | 6910 | static bfd_boolean |
c19d1205 ZW |
6911 | move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) |
6912 | { | |
53365c0d PB |
6913 | unsigned long tbit; |
6914 | ||
6915 | if (thumb_p) | |
6916 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
6917 | else | |
6918 | tbit = LOAD_BIT; | |
6919 | ||
6920 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 6921 | { |
c19d1205 | 6922 | inst.error = _("invalid pseudo operation"); |
c921be7d | 6923 | return TRUE; |
09d92015 | 6924 | } |
c19d1205 | 6925 | if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) |
09d92015 MM |
6926 | { |
6927 | inst.error = _("constant expression expected"); | |
c921be7d | 6928 | return TRUE; |
09d92015 | 6929 | } |
c19d1205 | 6930 | if (inst.reloc.exp.X_op == O_constant) |
09d92015 | 6931 | { |
c19d1205 ZW |
6932 | if (thumb_p) |
6933 | { | |
53365c0d | 6934 | if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) |
c19d1205 ZW |
6935 | { |
6936 | /* This can be done with a mov(1) instruction. */ | |
6937 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
6938 | inst.instruction |= inst.reloc.exp.X_add_number; | |
c921be7d | 6939 | return TRUE; |
c19d1205 ZW |
6940 | } |
6941 | } | |
6942 | else | |
6943 | { | |
6944 | int value = encode_arm_immediate (inst.reloc.exp.X_add_number); | |
6945 | if (value != FAIL) | |
6946 | { | |
6947 | /* This can be done with a mov instruction. */ | |
6948 | inst.instruction &= LITERAL_MASK; | |
6949 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
6950 | inst.instruction |= value & 0xfff; | |
c921be7d | 6951 | return TRUE; |
c19d1205 | 6952 | } |
09d92015 | 6953 | |
c19d1205 ZW |
6954 | value = encode_arm_immediate (~inst.reloc.exp.X_add_number); |
6955 | if (value != FAIL) | |
6956 | { | |
6957 | /* This can be done with a mvn instruction. */ | |
6958 | inst.instruction &= LITERAL_MASK; | |
6959 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
6960 | inst.instruction |= value & 0xfff; | |
c921be7d | 6961 | return TRUE; |
c19d1205 ZW |
6962 | } |
6963 | } | |
09d92015 MM |
6964 | } |
6965 | ||
c19d1205 ZW |
6966 | if (add_to_lit_pool () == FAIL) |
6967 | { | |
6968 | inst.error = _("literal pool insertion failed"); | |
c921be7d | 6969 | return TRUE; |
c19d1205 ZW |
6970 | } |
6971 | inst.operands[1].reg = REG_PC; | |
6972 | inst.operands[1].isreg = 1; | |
6973 | inst.operands[1].preind = 1; | |
6974 | inst.reloc.pc_rel = 1; | |
6975 | inst.reloc.type = (thumb_p | |
6976 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
6977 | : (mode_3 | |
6978 | ? BFD_RELOC_ARM_HWLITERAL | |
6979 | : BFD_RELOC_ARM_LITERAL)); | |
c921be7d | 6980 | return FALSE; |
09d92015 MM |
6981 | } |
6982 | ||
5f4273c7 | 6983 | /* Functions for instruction encoding, sorted by sub-architecture. |
c19d1205 ZW |
6984 | First some generics; their names are taken from the conventional |
6985 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 6986 | |
a737bd4d | 6987 | static void |
c19d1205 | 6988 | do_noargs (void) |
09d92015 | 6989 | { |
c19d1205 | 6990 | } |
a737bd4d | 6991 | |
c19d1205 ZW |
6992 | static void |
6993 | do_rd (void) | |
6994 | { | |
6995 | inst.instruction |= inst.operands[0].reg << 12; | |
6996 | } | |
a737bd4d | 6997 | |
c19d1205 ZW |
6998 | static void |
6999 | do_rd_rm (void) | |
7000 | { | |
7001 | inst.instruction |= inst.operands[0].reg << 12; | |
7002 | inst.instruction |= inst.operands[1].reg; | |
7003 | } | |
09d92015 | 7004 | |
c19d1205 ZW |
7005 | static void |
7006 | do_rd_rn (void) | |
7007 | { | |
7008 | inst.instruction |= inst.operands[0].reg << 12; | |
7009 | inst.instruction |= inst.operands[1].reg << 16; | |
7010 | } | |
a737bd4d | 7011 | |
c19d1205 ZW |
7012 | static void |
7013 | do_rn_rd (void) | |
7014 | { | |
7015 | inst.instruction |= inst.operands[0].reg << 16; | |
7016 | inst.instruction |= inst.operands[1].reg << 12; | |
7017 | } | |
09d92015 | 7018 | |
c19d1205 ZW |
7019 | static void |
7020 | do_rd_rm_rn (void) | |
7021 | { | |
9a64e435 | 7022 | unsigned Rn = inst.operands[2].reg; |
708587a4 | 7023 | /* Enforce restrictions on SWP instruction. */ |
9a64e435 | 7024 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
56adecf4 DG |
7025 | { |
7026 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
7027 | _("Rn must not overlap other operands")); | |
7028 | ||
7029 | /* SWP{b} is deprecated for ARMv6* and ARMv7. */ | |
7030 | if (warn_on_deprecated | |
7031 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
7032 | as_warn (_("swp{b} use is deprecated for this architecture")); | |
7033 | ||
7034 | } | |
c19d1205 ZW |
7035 | inst.instruction |= inst.operands[0].reg << 12; |
7036 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 7037 | inst.instruction |= Rn << 16; |
c19d1205 | 7038 | } |
09d92015 | 7039 | |
c19d1205 ZW |
7040 | static void |
7041 | do_rd_rn_rm (void) | |
7042 | { | |
7043 | inst.instruction |= inst.operands[0].reg << 12; | |
7044 | inst.instruction |= inst.operands[1].reg << 16; | |
7045 | inst.instruction |= inst.operands[2].reg; | |
7046 | } | |
a737bd4d | 7047 | |
c19d1205 ZW |
7048 | static void |
7049 | do_rm_rd_rn (void) | |
7050 | { | |
5be8be5d DG |
7051 | constraint ((inst.operands[2].reg == REG_PC), BAD_PC); |
7052 | constraint (((inst.reloc.exp.X_op != O_constant | |
7053 | && inst.reloc.exp.X_op != O_illegal) | |
7054 | || inst.reloc.exp.X_add_number != 0), | |
7055 | BAD_ADDR_MODE); | |
c19d1205 ZW |
7056 | inst.instruction |= inst.operands[0].reg; |
7057 | inst.instruction |= inst.operands[1].reg << 12; | |
7058 | inst.instruction |= inst.operands[2].reg << 16; | |
7059 | } | |
09d92015 | 7060 | |
c19d1205 ZW |
7061 | static void |
7062 | do_imm0 (void) | |
7063 | { | |
7064 | inst.instruction |= inst.operands[0].imm; | |
7065 | } | |
09d92015 | 7066 | |
c19d1205 ZW |
7067 | static void |
7068 | do_rd_cpaddr (void) | |
7069 | { | |
7070 | inst.instruction |= inst.operands[0].reg << 12; | |
7071 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 7072 | } |
a737bd4d | 7073 | |
c19d1205 ZW |
7074 | /* ARM instructions, in alphabetical order by function name (except |
7075 | that wrapper functions appear immediately after the function they | |
7076 | wrap). */ | |
09d92015 | 7077 | |
c19d1205 ZW |
7078 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
7079 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
7080 | |
7081 | static void | |
c19d1205 | 7082 | do_adr (void) |
09d92015 | 7083 | { |
c19d1205 | 7084 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 7085 | |
c19d1205 ZW |
7086 | /* Frag hacking will turn this into a sub instruction if the offset turns |
7087 | out to be negative. */ | |
7088 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 7089 | inst.reloc.pc_rel = 1; |
2fc8bdac | 7090 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 7091 | } |
b99bd4ef | 7092 | |
c19d1205 ZW |
7093 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
7094 | into a relative address of the form: | |
7095 | add rd, pc, #low(label-.-8)" | |
7096 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 7097 | |
c19d1205 ZW |
7098 | static void |
7099 | do_adrl (void) | |
7100 | { | |
7101 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 7102 | |
c19d1205 ZW |
7103 | /* Frag hacking will turn this into a sub instruction if the offset turns |
7104 | out to be negative. */ | |
7105 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
7106 | inst.reloc.pc_rel = 1; |
7107 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 7108 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
7109 | } |
7110 | ||
b99bd4ef | 7111 | static void |
c19d1205 | 7112 | do_arit (void) |
b99bd4ef | 7113 | { |
c19d1205 ZW |
7114 | if (!inst.operands[1].present) |
7115 | inst.operands[1].reg = inst.operands[0].reg; | |
7116 | inst.instruction |= inst.operands[0].reg << 12; | |
7117 | inst.instruction |= inst.operands[1].reg << 16; | |
7118 | encode_arm_shifter_operand (2); | |
7119 | } | |
b99bd4ef | 7120 | |
62b3e311 PB |
7121 | static void |
7122 | do_barrier (void) | |
7123 | { | |
7124 | if (inst.operands[0].present) | |
7125 | { | |
7126 | constraint ((inst.instruction & 0xf0) != 0x40 | |
7127 | && inst.operands[0].imm != 0xf, | |
bd3ba5d1 | 7128 | _("bad barrier type")); |
62b3e311 PB |
7129 | inst.instruction |= inst.operands[0].imm; |
7130 | } | |
7131 | else | |
7132 | inst.instruction |= 0xf; | |
7133 | } | |
7134 | ||
c19d1205 ZW |
7135 | static void |
7136 | do_bfc (void) | |
7137 | { | |
7138 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
7139 | constraint (msb > 32, _("bit-field extends past end of register")); | |
7140 | /* The instruction encoding stores the LSB and MSB, | |
7141 | not the LSB and width. */ | |
7142 | inst.instruction |= inst.operands[0].reg << 12; | |
7143 | inst.instruction |= inst.operands[1].imm << 7; | |
7144 | inst.instruction |= (msb - 1) << 16; | |
7145 | } | |
b99bd4ef | 7146 | |
c19d1205 ZW |
7147 | static void |
7148 | do_bfi (void) | |
7149 | { | |
7150 | unsigned int msb; | |
b99bd4ef | 7151 | |
c19d1205 ZW |
7152 | /* #0 in second position is alternative syntax for bfc, which is |
7153 | the same instruction but with REG_PC in the Rm field. */ | |
7154 | if (!inst.operands[1].isreg) | |
7155 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 7156 | |
c19d1205 ZW |
7157 | msb = inst.operands[2].imm + inst.operands[3].imm; |
7158 | constraint (msb > 32, _("bit-field extends past end of register")); | |
7159 | /* The instruction encoding stores the LSB and MSB, | |
7160 | not the LSB and width. */ | |
7161 | inst.instruction |= inst.operands[0].reg << 12; | |
7162 | inst.instruction |= inst.operands[1].reg; | |
7163 | inst.instruction |= inst.operands[2].imm << 7; | |
7164 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
7165 | } |
7166 | ||
b99bd4ef | 7167 | static void |
c19d1205 | 7168 | do_bfx (void) |
b99bd4ef | 7169 | { |
c19d1205 ZW |
7170 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
7171 | _("bit-field extends past end of register")); | |
7172 | inst.instruction |= inst.operands[0].reg << 12; | |
7173 | inst.instruction |= inst.operands[1].reg; | |
7174 | inst.instruction |= inst.operands[2].imm << 7; | |
7175 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
7176 | } | |
09d92015 | 7177 | |
c19d1205 ZW |
7178 | /* ARM V5 breakpoint instruction (argument parse) |
7179 | BKPT <16 bit unsigned immediate> | |
7180 | Instruction is not conditional. | |
7181 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
7182 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 7183 | |
c19d1205 ZW |
7184 | static void |
7185 | do_bkpt (void) | |
7186 | { | |
7187 | /* Top 12 of 16 bits to bits 19:8. */ | |
7188 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 7189 | |
c19d1205 ZW |
7190 | /* Bottom 4 of 16 bits to bits 3:0. */ |
7191 | inst.instruction |= inst.operands[0].imm & 0xf; | |
7192 | } | |
09d92015 | 7193 | |
c19d1205 ZW |
7194 | static void |
7195 | encode_branch (int default_reloc) | |
7196 | { | |
7197 | if (inst.operands[0].hasreloc) | |
7198 | { | |
7199 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, | |
7200 | _("the only suffix valid here is '(plt)'")); | |
267bf995 | 7201 | inst.reloc.type = BFD_RELOC_ARM_PLT32; |
c19d1205 | 7202 | } |
b99bd4ef | 7203 | else |
c19d1205 | 7204 | { |
21d799b5 | 7205 | inst.reloc.type = (bfd_reloc_code_real_type) default_reloc; |
c19d1205 | 7206 | } |
2fc8bdac | 7207 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
7208 | } |
7209 | ||
b99bd4ef | 7210 | static void |
c19d1205 | 7211 | do_branch (void) |
b99bd4ef | 7212 | { |
39b41c9c PB |
7213 | #ifdef OBJ_ELF |
7214 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
7215 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
7216 | else | |
7217 | #endif | |
7218 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
7219 | } | |
7220 | ||
7221 | static void | |
7222 | do_bl (void) | |
7223 | { | |
7224 | #ifdef OBJ_ELF | |
7225 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
7226 | { | |
7227 | if (inst.cond == COND_ALWAYS) | |
7228 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
7229 | else | |
7230 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
7231 | } | |
7232 | else | |
7233 | #endif | |
7234 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 7235 | } |
b99bd4ef | 7236 | |
c19d1205 ZW |
7237 | /* ARM V5 branch-link-exchange instruction (argument parse) |
7238 | BLX <target_addr> ie BLX(1) | |
7239 | BLX{<condition>} <Rm> ie BLX(2) | |
7240 | Unfortunately, there are two different opcodes for this mnemonic. | |
7241 | So, the insns[].value is not used, and the code here zaps values | |
7242 | into inst.instruction. | |
7243 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 7244 | |
c19d1205 ZW |
7245 | static void |
7246 | do_blx (void) | |
7247 | { | |
7248 | if (inst.operands[0].isreg) | |
b99bd4ef | 7249 | { |
c19d1205 ZW |
7250 | /* Arg is a register; the opcode provided by insns[] is correct. |
7251 | It is not illegal to do "blx pc", just useless. */ | |
7252 | if (inst.operands[0].reg == REG_PC) | |
7253 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 7254 | |
c19d1205 ZW |
7255 | inst.instruction |= inst.operands[0].reg; |
7256 | } | |
7257 | else | |
b99bd4ef | 7258 | { |
c19d1205 | 7259 | /* Arg is an address; this instruction cannot be executed |
267bf995 RR |
7260 | conditionally, and the opcode must be adjusted. |
7261 | We retain the BFD_RELOC_ARM_PCREL_BLX till the very end | |
7262 | where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ | |
c19d1205 | 7263 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
2fc8bdac | 7264 | inst.instruction = 0xfa000000; |
267bf995 | 7265 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 7266 | } |
c19d1205 ZW |
7267 | } |
7268 | ||
7269 | static void | |
7270 | do_bx (void) | |
7271 | { | |
845b51d6 PB |
7272 | bfd_boolean want_reloc; |
7273 | ||
c19d1205 ZW |
7274 | if (inst.operands[0].reg == REG_PC) |
7275 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 7276 | |
c19d1205 | 7277 | inst.instruction |= inst.operands[0].reg; |
845b51d6 PB |
7278 | /* Output R_ARM_V4BX relocations if is an EABI object that looks like |
7279 | it is for ARMv4t or earlier. */ | |
7280 | want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); | |
7281 | if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5)) | |
7282 | want_reloc = TRUE; | |
7283 | ||
5ad34203 | 7284 | #ifdef OBJ_ELF |
845b51d6 | 7285 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
5ad34203 | 7286 | #endif |
584206db | 7287 | want_reloc = FALSE; |
845b51d6 PB |
7288 | |
7289 | if (want_reloc) | |
7290 | inst.reloc.type = BFD_RELOC_ARM_V4BX; | |
09d92015 MM |
7291 | } |
7292 | ||
c19d1205 ZW |
7293 | |
7294 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
7295 | |
7296 | static void | |
c19d1205 | 7297 | do_bxj (void) |
a737bd4d | 7298 | { |
c19d1205 ZW |
7299 | if (inst.operands[0].reg == REG_PC) |
7300 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
7301 | ||
7302 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
7303 | } |
7304 | ||
c19d1205 ZW |
7305 | /* Co-processor data operation: |
7306 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
7307 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
7308 | static void | |
7309 | do_cdp (void) | |
7310 | { | |
7311 | inst.instruction |= inst.operands[0].reg << 8; | |
7312 | inst.instruction |= inst.operands[1].imm << 20; | |
7313 | inst.instruction |= inst.operands[2].reg << 12; | |
7314 | inst.instruction |= inst.operands[3].reg << 16; | |
7315 | inst.instruction |= inst.operands[4].reg; | |
7316 | inst.instruction |= inst.operands[5].imm << 5; | |
7317 | } | |
a737bd4d NC |
7318 | |
7319 | static void | |
c19d1205 | 7320 | do_cmp (void) |
a737bd4d | 7321 | { |
c19d1205 ZW |
7322 | inst.instruction |= inst.operands[0].reg << 16; |
7323 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
7324 | } |
7325 | ||
c19d1205 ZW |
7326 | /* Transfer between coprocessor and ARM registers. |
7327 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
7328 | MRC2 | |
7329 | MCR{cond} | |
7330 | MCR2 | |
7331 | ||
7332 | No special properties. */ | |
09d92015 MM |
7333 | |
7334 | static void | |
c19d1205 | 7335 | do_co_reg (void) |
09d92015 | 7336 | { |
fdfde340 JM |
7337 | unsigned Rd; |
7338 | ||
7339 | Rd = inst.operands[2].reg; | |
7340 | if (thumb_mode) | |
7341 | { | |
7342 | if (inst.instruction == 0xee000010 | |
7343 | || inst.instruction == 0xfe000010) | |
7344 | /* MCR, MCR2 */ | |
7345 | reject_bad_reg (Rd); | |
7346 | else | |
7347 | /* MRC, MRC2 */ | |
7348 | constraint (Rd == REG_SP, BAD_SP); | |
7349 | } | |
7350 | else | |
7351 | { | |
7352 | /* MCR */ | |
7353 | if (inst.instruction == 0xe000010) | |
7354 | constraint (Rd == REG_PC, BAD_PC); | |
7355 | } | |
7356 | ||
7357 | ||
c19d1205 ZW |
7358 | inst.instruction |= inst.operands[0].reg << 8; |
7359 | inst.instruction |= inst.operands[1].imm << 21; | |
fdfde340 | 7360 | inst.instruction |= Rd << 12; |
c19d1205 ZW |
7361 | inst.instruction |= inst.operands[3].reg << 16; |
7362 | inst.instruction |= inst.operands[4].reg; | |
7363 | inst.instruction |= inst.operands[5].imm << 5; | |
7364 | } | |
09d92015 | 7365 | |
c19d1205 ZW |
7366 | /* Transfer between coprocessor register and pair of ARM registers. |
7367 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
7368 | MCRR2 | |
7369 | MRRC{cond} | |
7370 | MRRC2 | |
b99bd4ef | 7371 | |
c19d1205 | 7372 | Two XScale instructions are special cases of these: |
09d92015 | 7373 | |
c19d1205 ZW |
7374 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
7375 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 7376 | |
5f4273c7 | 7377 | Result unpredictable if Rd or Rn is R15. */ |
a737bd4d | 7378 | |
c19d1205 ZW |
7379 | static void |
7380 | do_co_reg2c (void) | |
7381 | { | |
fdfde340 JM |
7382 | unsigned Rd, Rn; |
7383 | ||
7384 | Rd = inst.operands[2].reg; | |
7385 | Rn = inst.operands[3].reg; | |
7386 | ||
7387 | if (thumb_mode) | |
7388 | { | |
7389 | reject_bad_reg (Rd); | |
7390 | reject_bad_reg (Rn); | |
7391 | } | |
7392 | else | |
7393 | { | |
7394 | constraint (Rd == REG_PC, BAD_PC); | |
7395 | constraint (Rn == REG_PC, BAD_PC); | |
7396 | } | |
7397 | ||
c19d1205 ZW |
7398 | inst.instruction |= inst.operands[0].reg << 8; |
7399 | inst.instruction |= inst.operands[1].imm << 4; | |
fdfde340 JM |
7400 | inst.instruction |= Rd << 12; |
7401 | inst.instruction |= Rn << 16; | |
c19d1205 | 7402 | inst.instruction |= inst.operands[4].reg; |
b99bd4ef NC |
7403 | } |
7404 | ||
c19d1205 ZW |
7405 | static void |
7406 | do_cpsi (void) | |
7407 | { | |
7408 | inst.instruction |= inst.operands[0].imm << 6; | |
a028a6f5 PB |
7409 | if (inst.operands[1].present) |
7410 | { | |
7411 | inst.instruction |= CPSI_MMOD; | |
7412 | inst.instruction |= inst.operands[1].imm; | |
7413 | } | |
c19d1205 | 7414 | } |
b99bd4ef | 7415 | |
62b3e311 PB |
7416 | static void |
7417 | do_dbg (void) | |
7418 | { | |
7419 | inst.instruction |= inst.operands[0].imm; | |
7420 | } | |
7421 | ||
b99bd4ef | 7422 | static void |
c19d1205 | 7423 | do_it (void) |
b99bd4ef | 7424 | { |
c19d1205 | 7425 | /* There is no IT instruction in ARM mode. We |
e07e6e58 NC |
7426 | process it to do the validation as if in |
7427 | thumb mode, just in case the code gets | |
7428 | assembled for thumb using the unified syntax. */ | |
7429 | ||
c19d1205 | 7430 | inst.size = 0; |
e07e6e58 NC |
7431 | if (unified_syntax) |
7432 | { | |
7433 | set_it_insn_type (IT_INSN); | |
7434 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
7435 | now_it.cc = inst.operands[0].imm; | |
7436 | } | |
09d92015 | 7437 | } |
b99bd4ef | 7438 | |
09d92015 | 7439 | static void |
c19d1205 | 7440 | do_ldmstm (void) |
ea6ef066 | 7441 | { |
c19d1205 ZW |
7442 | int base_reg = inst.operands[0].reg; |
7443 | int range = inst.operands[1].imm; | |
ea6ef066 | 7444 | |
c19d1205 ZW |
7445 | inst.instruction |= base_reg << 16; |
7446 | inst.instruction |= range; | |
ea6ef066 | 7447 | |
c19d1205 ZW |
7448 | if (inst.operands[1].writeback) |
7449 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 7450 | |
c19d1205 | 7451 | if (inst.operands[0].writeback) |
ea6ef066 | 7452 | { |
c19d1205 ZW |
7453 | inst.instruction |= WRITE_BACK; |
7454 | /* Check for unpredictable uses of writeback. */ | |
7455 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 7456 | { |
c19d1205 ZW |
7457 | /* Not allowed in LDM type 2. */ |
7458 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
7459 | && ((range & (1 << REG_PC)) == 0)) | |
7460 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7461 | /* Only allowed if base reg not in list for other types. */ | |
7462 | else if (range & (1 << base_reg)) | |
7463 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
7464 | } | |
7465 | else /* STM. */ | |
7466 | { | |
7467 | /* Not allowed for type 2. */ | |
7468 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
7469 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7470 | /* Only allowed if base reg not in list, or first in list. */ | |
7471 | else if ((range & (1 << base_reg)) | |
7472 | && (range & ((1 << base_reg) - 1))) | |
7473 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 7474 | } |
ea6ef066 | 7475 | } |
a737bd4d NC |
7476 | } |
7477 | ||
c19d1205 ZW |
7478 | /* ARMv5TE load-consecutive (argument parse) |
7479 | Mode is like LDRH. | |
7480 | ||
7481 | LDRccD R, mode | |
7482 | STRccD R, mode. */ | |
7483 | ||
a737bd4d | 7484 | static void |
c19d1205 | 7485 | do_ldrd (void) |
a737bd4d | 7486 | { |
c19d1205 ZW |
7487 | constraint (inst.operands[0].reg % 2 != 0, |
7488 | _("first destination register must be even")); | |
7489 | constraint (inst.operands[1].present | |
7490 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
7491 | _("can only load two consecutive registers")); | |
7492 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
7493 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 7494 | |
c19d1205 ZW |
7495 | if (!inst.operands[1].present) |
7496 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
5f4273c7 | 7497 | |
c19d1205 | 7498 | if (inst.instruction & LOAD_BIT) |
a737bd4d | 7499 | { |
c19d1205 ZW |
7500 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
7501 | register and the first register written; we have to diagnose | |
7502 | overlap between the base and the second register written here. */ | |
ea6ef066 | 7503 | |
c19d1205 ZW |
7504 | if (inst.operands[2].reg == inst.operands[1].reg |
7505 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
7506 | as_warn (_("base register written back, and overlaps " | |
7507 | "second destination register")); | |
b05fe5cf | 7508 | |
c19d1205 ZW |
7509 | /* For an index-register load, the index register must not overlap the |
7510 | destination (even if not write-back). */ | |
7511 | else if (inst.operands[2].immisreg | |
ca3f61f7 NC |
7512 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg |
7513 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
c19d1205 | 7514 | as_warn (_("index register overlaps destination register")); |
b05fe5cf | 7515 | } |
c19d1205 ZW |
7516 | |
7517 | inst.instruction |= inst.operands[0].reg << 12; | |
7518 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
7519 | } |
7520 | ||
7521 | static void | |
c19d1205 | 7522 | do_ldrex (void) |
b05fe5cf | 7523 | { |
c19d1205 ZW |
7524 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
7525 | || inst.operands[1].postind || inst.operands[1].writeback | |
7526 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
7527 | || inst.operands[1].negative |
7528 | /* This can arise if the programmer has written | |
7529 | strex rN, rM, foo | |
7530 | or if they have mistakenly used a register name as the last | |
7531 | operand, eg: | |
7532 | strex rN, rM, rX | |
7533 | It is very difficult to distinguish between these two cases | |
7534 | because "rX" might actually be a label. ie the register | |
7535 | name has been occluded by a symbol of the same name. So we | |
7536 | just generate a general 'bad addressing mode' type error | |
7537 | message and leave it up to the programmer to discover the | |
7538 | true cause and fix their mistake. */ | |
7539 | || (inst.operands[1].reg == REG_PC), | |
7540 | BAD_ADDR_MODE); | |
b05fe5cf | 7541 | |
c19d1205 ZW |
7542 | constraint (inst.reloc.exp.X_op != O_constant |
7543 | || inst.reloc.exp.X_add_number != 0, | |
7544 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 7545 | |
5be8be5d DG |
7546 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
7547 | ||
c19d1205 ZW |
7548 | inst.instruction |= inst.operands[0].reg << 12; |
7549 | inst.instruction |= inst.operands[1].reg << 16; | |
7550 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
7551 | } |
7552 | ||
7553 | static void | |
c19d1205 | 7554 | do_ldrexd (void) |
b05fe5cf | 7555 | { |
c19d1205 ZW |
7556 | constraint (inst.operands[0].reg % 2 != 0, |
7557 | _("even register required")); | |
7558 | constraint (inst.operands[1].present | |
7559 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
7560 | _("can only load two consecutive registers")); | |
7561 | /* If op 1 were present and equal to PC, this function wouldn't | |
7562 | have been called in the first place. */ | |
7563 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 7564 | |
c19d1205 ZW |
7565 | inst.instruction |= inst.operands[0].reg << 12; |
7566 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
7567 | } |
7568 | ||
7569 | static void | |
c19d1205 | 7570 | do_ldst (void) |
b05fe5cf | 7571 | { |
c19d1205 ZW |
7572 | inst.instruction |= inst.operands[0].reg << 12; |
7573 | if (!inst.operands[1].isreg) | |
7574 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) | |
b05fe5cf | 7575 | return; |
c19d1205 | 7576 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
7577 | } |
7578 | ||
7579 | static void | |
c19d1205 | 7580 | do_ldstt (void) |
b05fe5cf | 7581 | { |
c19d1205 ZW |
7582 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
7583 | reject [Rn,...]. */ | |
7584 | if (inst.operands[1].preind) | |
b05fe5cf | 7585 | { |
bd3ba5d1 NC |
7586 | constraint (inst.reloc.exp.X_op != O_constant |
7587 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 7588 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 7589 | |
c19d1205 ZW |
7590 | inst.operands[1].preind = 0; |
7591 | inst.operands[1].postind = 1; | |
7592 | inst.operands[1].writeback = 1; | |
b05fe5cf | 7593 | } |
c19d1205 ZW |
7594 | inst.instruction |= inst.operands[0].reg << 12; |
7595 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
7596 | } | |
b05fe5cf | 7597 | |
c19d1205 | 7598 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 7599 | |
c19d1205 ZW |
7600 | static void |
7601 | do_ldstv4 (void) | |
7602 | { | |
ff4a8d2b | 7603 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
7604 | inst.instruction |= inst.operands[0].reg << 12; |
7605 | if (!inst.operands[1].isreg) | |
7606 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) | |
b05fe5cf | 7607 | return; |
c19d1205 | 7608 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
7609 | } |
7610 | ||
7611 | static void | |
c19d1205 | 7612 | do_ldsttv4 (void) |
b05fe5cf | 7613 | { |
c19d1205 ZW |
7614 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
7615 | reject [Rn,...]. */ | |
7616 | if (inst.operands[1].preind) | |
b05fe5cf | 7617 | { |
bd3ba5d1 NC |
7618 | constraint (inst.reloc.exp.X_op != O_constant |
7619 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 7620 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 7621 | |
c19d1205 ZW |
7622 | inst.operands[1].preind = 0; |
7623 | inst.operands[1].postind = 1; | |
7624 | inst.operands[1].writeback = 1; | |
b05fe5cf | 7625 | } |
c19d1205 ZW |
7626 | inst.instruction |= inst.operands[0].reg << 12; |
7627 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
7628 | } | |
b05fe5cf | 7629 | |
c19d1205 ZW |
7630 | /* Co-processor register load/store. |
7631 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
7632 | static void | |
7633 | do_lstc (void) | |
7634 | { | |
7635 | inst.instruction |= inst.operands[0].reg << 8; | |
7636 | inst.instruction |= inst.operands[1].reg << 12; | |
7637 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
7638 | } |
7639 | ||
b05fe5cf | 7640 | static void |
c19d1205 | 7641 | do_mlas (void) |
b05fe5cf | 7642 | { |
8fb9d7b9 | 7643 | /* This restriction does not apply to mls (nor to mla in v6 or later). */ |
c19d1205 | 7644 | if (inst.operands[0].reg == inst.operands[1].reg |
8fb9d7b9 | 7645 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) |
c19d1205 | 7646 | && !(inst.instruction & 0x00400000)) |
8fb9d7b9 | 7647 | as_tsktsk (_("Rd and Rm should be different in mla")); |
b05fe5cf | 7648 | |
c19d1205 ZW |
7649 | inst.instruction |= inst.operands[0].reg << 16; |
7650 | inst.instruction |= inst.operands[1].reg; | |
7651 | inst.instruction |= inst.operands[2].reg << 8; | |
7652 | inst.instruction |= inst.operands[3].reg << 12; | |
c19d1205 | 7653 | } |
b05fe5cf | 7654 | |
c19d1205 ZW |
7655 | static void |
7656 | do_mov (void) | |
7657 | { | |
7658 | inst.instruction |= inst.operands[0].reg << 12; | |
7659 | encode_arm_shifter_operand (1); | |
7660 | } | |
b05fe5cf | 7661 | |
c19d1205 ZW |
7662 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
7663 | static void | |
7664 | do_mov16 (void) | |
7665 | { | |
b6895b4f PB |
7666 | bfd_vma imm; |
7667 | bfd_boolean top; | |
7668 | ||
7669 | top = (inst.instruction & 0x00400000) != 0; | |
7670 | constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, | |
7671 | _(":lower16: not allowed this instruction")); | |
7672 | constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, | |
7673 | _(":upper16: not allowed instruction")); | |
c19d1205 | 7674 | inst.instruction |= inst.operands[0].reg << 12; |
b6895b4f PB |
7675 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
7676 | { | |
7677 | imm = inst.reloc.exp.X_add_number; | |
7678 | /* The value is in two pieces: 0:11, 16:19. */ | |
7679 | inst.instruction |= (imm & 0x00000fff); | |
7680 | inst.instruction |= (imm & 0x0000f000) << 4; | |
7681 | } | |
b05fe5cf | 7682 | } |
b99bd4ef | 7683 | |
037e8744 JB |
7684 | static void do_vfp_nsyn_opcode (const char *); |
7685 | ||
7686 | static int | |
7687 | do_vfp_nsyn_mrs (void) | |
7688 | { | |
7689 | if (inst.operands[0].isvec) | |
7690 | { | |
7691 | if (inst.operands[1].reg != 1) | |
7692 | first_error (_("operand 1 must be FPSCR")); | |
7693 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
7694 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); | |
7695 | do_vfp_nsyn_opcode ("fmstat"); | |
7696 | } | |
7697 | else if (inst.operands[1].isvec) | |
7698 | do_vfp_nsyn_opcode ("fmrx"); | |
7699 | else | |
7700 | return FAIL; | |
5f4273c7 | 7701 | |
037e8744 JB |
7702 | return SUCCESS; |
7703 | } | |
7704 | ||
7705 | static int | |
7706 | do_vfp_nsyn_msr (void) | |
7707 | { | |
7708 | if (inst.operands[0].isvec) | |
7709 | do_vfp_nsyn_opcode ("fmxr"); | |
7710 | else | |
7711 | return FAIL; | |
7712 | ||
7713 | return SUCCESS; | |
7714 | } | |
7715 | ||
f7c21dc7 NC |
7716 | static void |
7717 | do_vmrs (void) | |
7718 | { | |
7719 | unsigned Rt = inst.operands[0].reg; | |
7720 | ||
7721 | if (thumb_mode && inst.operands[0].reg == REG_SP) | |
7722 | { | |
7723 | inst.error = BAD_SP; | |
7724 | return; | |
7725 | } | |
7726 | ||
7727 | /* APSR_ sets isvec. All other refs to PC are illegal. */ | |
7728 | if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC) | |
7729 | { | |
7730 | inst.error = BAD_PC; | |
7731 | return; | |
7732 | } | |
7733 | ||
7734 | if (inst.operands[1].reg != 1) | |
7735 | first_error (_("operand 1 must be FPSCR")); | |
7736 | ||
7737 | inst.instruction |= (Rt << 12); | |
7738 | } | |
7739 | ||
7740 | static void | |
7741 | do_vmsr (void) | |
7742 | { | |
7743 | unsigned Rt = inst.operands[1].reg; | |
7744 | ||
7745 | if (thumb_mode) | |
7746 | reject_bad_reg (Rt); | |
7747 | else if (Rt == REG_PC) | |
7748 | { | |
7749 | inst.error = BAD_PC; | |
7750 | return; | |
7751 | } | |
7752 | ||
7753 | if (inst.operands[0].reg != 1) | |
7754 | first_error (_("operand 0 must be FPSCR")); | |
7755 | ||
7756 | inst.instruction |= (Rt << 12); | |
7757 | } | |
7758 | ||
b99bd4ef | 7759 | static void |
c19d1205 | 7760 | do_mrs (void) |
b99bd4ef | 7761 | { |
037e8744 JB |
7762 | if (do_vfp_nsyn_mrs () == SUCCESS) |
7763 | return; | |
7764 | ||
c19d1205 ZW |
7765 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ |
7766 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
7767 | != (PSR_c|PSR_f), | |
7768 | _("'CPSR' or 'SPSR' expected")); | |
ff4a8d2b | 7769 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
7770 | inst.instruction |= inst.operands[0].reg << 12; |
7771 | inst.instruction |= (inst.operands[1].imm & SPSR_BIT); | |
7772 | } | |
b99bd4ef | 7773 | |
c19d1205 ZW |
7774 | /* Two possible forms: |
7775 | "{C|S}PSR_<field>, Rm", | |
7776 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 7777 | |
c19d1205 ZW |
7778 | static void |
7779 | do_msr (void) | |
7780 | { | |
037e8744 JB |
7781 | if (do_vfp_nsyn_msr () == SUCCESS) |
7782 | return; | |
7783 | ||
c19d1205 ZW |
7784 | inst.instruction |= inst.operands[0].imm; |
7785 | if (inst.operands[1].isreg) | |
7786 | inst.instruction |= inst.operands[1].reg; | |
7787 | else | |
b99bd4ef | 7788 | { |
c19d1205 ZW |
7789 | inst.instruction |= INST_IMMEDIATE; |
7790 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
7791 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 7792 | } |
b99bd4ef NC |
7793 | } |
7794 | ||
c19d1205 ZW |
7795 | static void |
7796 | do_mul (void) | |
a737bd4d | 7797 | { |
ff4a8d2b NC |
7798 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
7799 | ||
c19d1205 ZW |
7800 | if (!inst.operands[2].present) |
7801 | inst.operands[2].reg = inst.operands[0].reg; | |
7802 | inst.instruction |= inst.operands[0].reg << 16; | |
7803 | inst.instruction |= inst.operands[1].reg; | |
7804 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 7805 | |
8fb9d7b9 MS |
7806 | if (inst.operands[0].reg == inst.operands[1].reg |
7807 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
7808 | as_tsktsk (_("Rd and Rm should be different in mul")); | |
a737bd4d NC |
7809 | } |
7810 | ||
c19d1205 ZW |
7811 | /* Long Multiply Parser |
7812 | UMULL RdLo, RdHi, Rm, Rs | |
7813 | SMULL RdLo, RdHi, Rm, Rs | |
7814 | UMLAL RdLo, RdHi, Rm, Rs | |
7815 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
7816 | |
7817 | static void | |
c19d1205 | 7818 | do_mull (void) |
b99bd4ef | 7819 | { |
c19d1205 ZW |
7820 | inst.instruction |= inst.operands[0].reg << 12; |
7821 | inst.instruction |= inst.operands[1].reg << 16; | |
7822 | inst.instruction |= inst.operands[2].reg; | |
7823 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 7824 | |
682b27ad PB |
7825 | /* rdhi and rdlo must be different. */ |
7826 | if (inst.operands[0].reg == inst.operands[1].reg) | |
7827 | as_tsktsk (_("rdhi and rdlo must be different")); | |
7828 | ||
7829 | /* rdhi, rdlo and rm must all be different before armv6. */ | |
7830 | if ((inst.operands[0].reg == inst.operands[2].reg | |
c19d1205 | 7831 | || inst.operands[1].reg == inst.operands[2].reg) |
682b27ad | 7832 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
c19d1205 ZW |
7833 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); |
7834 | } | |
b99bd4ef | 7835 | |
c19d1205 ZW |
7836 | static void |
7837 | do_nop (void) | |
7838 | { | |
e7495e45 NS |
7839 | if (inst.operands[0].present |
7840 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) | |
c19d1205 ZW |
7841 | { |
7842 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
7843 | inst.instruction &= 0xf0000000; | |
e7495e45 NS |
7844 | inst.instruction |= 0x0320f000; |
7845 | if (inst.operands[0].present) | |
7846 | inst.instruction |= inst.operands[0].imm; | |
c19d1205 | 7847 | } |
b99bd4ef NC |
7848 | } |
7849 | ||
c19d1205 ZW |
7850 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
7851 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
7852 | Condition defaults to COND_ALWAYS. | |
7853 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
7854 | |
7855 | static void | |
c19d1205 | 7856 | do_pkhbt (void) |
b99bd4ef | 7857 | { |
c19d1205 ZW |
7858 | inst.instruction |= inst.operands[0].reg << 12; |
7859 | inst.instruction |= inst.operands[1].reg << 16; | |
7860 | inst.instruction |= inst.operands[2].reg; | |
7861 | if (inst.operands[3].present) | |
7862 | encode_arm_shift (3); | |
7863 | } | |
b99bd4ef | 7864 | |
c19d1205 | 7865 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 7866 | |
c19d1205 ZW |
7867 | static void |
7868 | do_pkhtb (void) | |
7869 | { | |
7870 | if (!inst.operands[3].present) | |
b99bd4ef | 7871 | { |
c19d1205 ZW |
7872 | /* If the shift specifier is omitted, turn the instruction |
7873 | into pkhbt rd, rm, rn. */ | |
7874 | inst.instruction &= 0xfff00010; | |
7875 | inst.instruction |= inst.operands[0].reg << 12; | |
7876 | inst.instruction |= inst.operands[1].reg; | |
7877 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
7878 | } |
7879 | else | |
7880 | { | |
c19d1205 ZW |
7881 | inst.instruction |= inst.operands[0].reg << 12; |
7882 | inst.instruction |= inst.operands[1].reg << 16; | |
7883 | inst.instruction |= inst.operands[2].reg; | |
7884 | encode_arm_shift (3); | |
b99bd4ef NC |
7885 | } |
7886 | } | |
7887 | ||
c19d1205 ZW |
7888 | /* ARMv5TE: Preload-Cache |
7889 | ||
7890 | PLD <addr_mode> | |
7891 | ||
7892 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
7893 | |
7894 | static void | |
c19d1205 | 7895 | do_pld (void) |
b99bd4ef | 7896 | { |
c19d1205 ZW |
7897 | constraint (!inst.operands[0].isreg, |
7898 | _("'[' expected after PLD mnemonic")); | |
7899 | constraint (inst.operands[0].postind, | |
7900 | _("post-indexed expression used in preload instruction")); | |
7901 | constraint (inst.operands[0].writeback, | |
7902 | _("writeback used in preload instruction")); | |
7903 | constraint (!inst.operands[0].preind, | |
7904 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
7905 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
7906 | } | |
b99bd4ef | 7907 | |
62b3e311 PB |
7908 | /* ARMv7: PLI <addr_mode> */ |
7909 | static void | |
7910 | do_pli (void) | |
7911 | { | |
7912 | constraint (!inst.operands[0].isreg, | |
7913 | _("'[' expected after PLI mnemonic")); | |
7914 | constraint (inst.operands[0].postind, | |
7915 | _("post-indexed expression used in preload instruction")); | |
7916 | constraint (inst.operands[0].writeback, | |
7917 | _("writeback used in preload instruction")); | |
7918 | constraint (!inst.operands[0].preind, | |
7919 | _("unindexed addressing used in preload instruction")); | |
7920 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
7921 | inst.instruction &= ~PRE_INDEX; | |
7922 | } | |
7923 | ||
c19d1205 ZW |
7924 | static void |
7925 | do_push_pop (void) | |
7926 | { | |
7927 | inst.operands[1] = inst.operands[0]; | |
7928 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
7929 | inst.operands[0].isreg = 1; | |
7930 | inst.operands[0].writeback = 1; | |
7931 | inst.operands[0].reg = REG_SP; | |
7932 | do_ldmstm (); | |
7933 | } | |
b99bd4ef | 7934 | |
c19d1205 ZW |
7935 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
7936 | word at the specified address and the following word | |
7937 | respectively. | |
7938 | Unconditionally executed. | |
7939 | Error if Rn is R15. */ | |
b99bd4ef | 7940 | |
c19d1205 ZW |
7941 | static void |
7942 | do_rfe (void) | |
7943 | { | |
7944 | inst.instruction |= inst.operands[0].reg << 16; | |
7945 | if (inst.operands[0].writeback) | |
7946 | inst.instruction |= WRITE_BACK; | |
7947 | } | |
b99bd4ef | 7948 | |
c19d1205 | 7949 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 7950 | |
c19d1205 ZW |
7951 | static void |
7952 | do_ssat (void) | |
7953 | { | |
7954 | inst.instruction |= inst.operands[0].reg << 12; | |
7955 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
7956 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 7957 | |
c19d1205 ZW |
7958 | if (inst.operands[3].present) |
7959 | encode_arm_shift (3); | |
b99bd4ef NC |
7960 | } |
7961 | ||
c19d1205 | 7962 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
7963 | |
7964 | static void | |
c19d1205 | 7965 | do_usat (void) |
b99bd4ef | 7966 | { |
c19d1205 ZW |
7967 | inst.instruction |= inst.operands[0].reg << 12; |
7968 | inst.instruction |= inst.operands[1].imm << 16; | |
7969 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 7970 | |
c19d1205 ZW |
7971 | if (inst.operands[3].present) |
7972 | encode_arm_shift (3); | |
b99bd4ef NC |
7973 | } |
7974 | ||
c19d1205 | 7975 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
7976 | |
7977 | static void | |
c19d1205 | 7978 | do_ssat16 (void) |
09d92015 | 7979 | { |
c19d1205 ZW |
7980 | inst.instruction |= inst.operands[0].reg << 12; |
7981 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
7982 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
7983 | } |
7984 | ||
c19d1205 ZW |
7985 | static void |
7986 | do_usat16 (void) | |
a737bd4d | 7987 | { |
c19d1205 ZW |
7988 | inst.instruction |= inst.operands[0].reg << 12; |
7989 | inst.instruction |= inst.operands[1].imm << 16; | |
7990 | inst.instruction |= inst.operands[2].reg; | |
7991 | } | |
a737bd4d | 7992 | |
c19d1205 ZW |
7993 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
7994 | preserving the other bits. | |
a737bd4d | 7995 | |
c19d1205 ZW |
7996 | setend <endian_specifier>, where <endian_specifier> is either |
7997 | BE or LE. */ | |
a737bd4d | 7998 | |
c19d1205 ZW |
7999 | static void |
8000 | do_setend (void) | |
8001 | { | |
8002 | if (inst.operands[0].imm) | |
8003 | inst.instruction |= 0x200; | |
a737bd4d NC |
8004 | } |
8005 | ||
8006 | static void | |
c19d1205 | 8007 | do_shift (void) |
a737bd4d | 8008 | { |
c19d1205 ZW |
8009 | unsigned int Rm = (inst.operands[1].present |
8010 | ? inst.operands[1].reg | |
8011 | : inst.operands[0].reg); | |
a737bd4d | 8012 | |
c19d1205 ZW |
8013 | inst.instruction |= inst.operands[0].reg << 12; |
8014 | inst.instruction |= Rm; | |
8015 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 8016 | { |
c19d1205 ZW |
8017 | inst.instruction |= inst.operands[2].reg << 8; |
8018 | inst.instruction |= SHIFT_BY_REG; | |
a737bd4d NC |
8019 | } |
8020 | else | |
c19d1205 | 8021 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
8022 | } |
8023 | ||
09d92015 | 8024 | static void |
3eb17e6b | 8025 | do_smc (void) |
09d92015 | 8026 | { |
3eb17e6b | 8027 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 8028 | inst.reloc.pc_rel = 0; |
09d92015 MM |
8029 | } |
8030 | ||
09d92015 | 8031 | static void |
c19d1205 | 8032 | do_swi (void) |
09d92015 | 8033 | { |
c19d1205 ZW |
8034 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
8035 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
8036 | } |
8037 | ||
c19d1205 ZW |
8038 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
8039 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
8040 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
8041 | Error if any register is R15. */ | |
e16bb312 | 8042 | |
c19d1205 ZW |
8043 | static void |
8044 | do_smla (void) | |
e16bb312 | 8045 | { |
c19d1205 ZW |
8046 | inst.instruction |= inst.operands[0].reg << 16; |
8047 | inst.instruction |= inst.operands[1].reg; | |
8048 | inst.instruction |= inst.operands[2].reg << 8; | |
8049 | inst.instruction |= inst.operands[3].reg << 12; | |
8050 | } | |
a737bd4d | 8051 | |
c19d1205 ZW |
8052 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
8053 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
8054 | Error if any register is R15. | |
8055 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 8056 | |
c19d1205 ZW |
8057 | static void |
8058 | do_smlal (void) | |
8059 | { | |
8060 | inst.instruction |= inst.operands[0].reg << 12; | |
8061 | inst.instruction |= inst.operands[1].reg << 16; | |
8062 | inst.instruction |= inst.operands[2].reg; | |
8063 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 8064 | |
c19d1205 ZW |
8065 | if (inst.operands[0].reg == inst.operands[1].reg) |
8066 | as_tsktsk (_("rdhi and rdlo must be different")); | |
8067 | } | |
a737bd4d | 8068 | |
c19d1205 ZW |
8069 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
8070 | SMULxy{cond} Rd,Rm,Rs | |
8071 | Error if any register is R15. */ | |
a737bd4d | 8072 | |
c19d1205 ZW |
8073 | static void |
8074 | do_smul (void) | |
8075 | { | |
8076 | inst.instruction |= inst.operands[0].reg << 16; | |
8077 | inst.instruction |= inst.operands[1].reg; | |
8078 | inst.instruction |= inst.operands[2].reg << 8; | |
8079 | } | |
a737bd4d | 8080 | |
b6702015 PB |
8081 | /* ARM V6 srs (argument parse). The variable fields in the encoding are |
8082 | the same for both ARM and Thumb-2. */ | |
a737bd4d | 8083 | |
c19d1205 ZW |
8084 | static void |
8085 | do_srs (void) | |
8086 | { | |
b6702015 PB |
8087 | int reg; |
8088 | ||
8089 | if (inst.operands[0].present) | |
8090 | { | |
8091 | reg = inst.operands[0].reg; | |
fdfde340 | 8092 | constraint (reg != REG_SP, _("SRS base register must be r13")); |
b6702015 PB |
8093 | } |
8094 | else | |
fdfde340 | 8095 | reg = REG_SP; |
b6702015 PB |
8096 | |
8097 | inst.instruction |= reg << 16; | |
8098 | inst.instruction |= inst.operands[1].imm; | |
8099 | if (inst.operands[0].writeback || inst.operands[1].writeback) | |
c19d1205 ZW |
8100 | inst.instruction |= WRITE_BACK; |
8101 | } | |
a737bd4d | 8102 | |
c19d1205 | 8103 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 8104 | |
c19d1205 ZW |
8105 | static void |
8106 | do_strex (void) | |
8107 | { | |
8108 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
8109 | || inst.operands[2].postind || inst.operands[2].writeback | |
8110 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
8111 | || inst.operands[2].negative |
8112 | /* See comment in do_ldrex(). */ | |
8113 | || (inst.operands[2].reg == REG_PC), | |
8114 | BAD_ADDR_MODE); | |
a737bd4d | 8115 | |
c19d1205 ZW |
8116 | constraint (inst.operands[0].reg == inst.operands[1].reg |
8117 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 8118 | |
c19d1205 ZW |
8119 | constraint (inst.reloc.exp.X_op != O_constant |
8120 | || inst.reloc.exp.X_add_number != 0, | |
8121 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 8122 | |
c19d1205 ZW |
8123 | inst.instruction |= inst.operands[0].reg << 12; |
8124 | inst.instruction |= inst.operands[1].reg; | |
8125 | inst.instruction |= inst.operands[2].reg << 16; | |
8126 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
8127 | } |
8128 | ||
8129 | static void | |
c19d1205 | 8130 | do_strexd (void) |
e16bb312 | 8131 | { |
c19d1205 ZW |
8132 | constraint (inst.operands[1].reg % 2 != 0, |
8133 | _("even register required")); | |
8134 | constraint (inst.operands[2].present | |
8135 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
8136 | _("can only store two consecutive registers")); | |
8137 | /* If op 2 were present and equal to PC, this function wouldn't | |
8138 | have been called in the first place. */ | |
8139 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 8140 | |
c19d1205 ZW |
8141 | constraint (inst.operands[0].reg == inst.operands[1].reg |
8142 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
8143 | || inst.operands[0].reg == inst.operands[3].reg, | |
8144 | BAD_OVERLAP); | |
e16bb312 | 8145 | |
c19d1205 ZW |
8146 | inst.instruction |= inst.operands[0].reg << 12; |
8147 | inst.instruction |= inst.operands[1].reg; | |
8148 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
8149 | } |
8150 | ||
c19d1205 ZW |
8151 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
8152 | extends it to 32-bits, and adds the result to a value in another | |
8153 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
8154 | before extracting the 16-bit value. | |
8155 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
8156 | Condition defaults to COND_ALWAYS. | |
8157 | Error if any register uses R15. */ | |
8158 | ||
e16bb312 | 8159 | static void |
c19d1205 | 8160 | do_sxtah (void) |
e16bb312 | 8161 | { |
c19d1205 ZW |
8162 | inst.instruction |= inst.operands[0].reg << 12; |
8163 | inst.instruction |= inst.operands[1].reg << 16; | |
8164 | inst.instruction |= inst.operands[2].reg; | |
8165 | inst.instruction |= inst.operands[3].imm << 10; | |
8166 | } | |
e16bb312 | 8167 | |
c19d1205 | 8168 | /* ARM V6 SXTH. |
e16bb312 | 8169 | |
c19d1205 ZW |
8170 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
8171 | Condition defaults to COND_ALWAYS. | |
8172 | Error if any register uses R15. */ | |
e16bb312 NC |
8173 | |
8174 | static void | |
c19d1205 | 8175 | do_sxth (void) |
e16bb312 | 8176 | { |
c19d1205 ZW |
8177 | inst.instruction |= inst.operands[0].reg << 12; |
8178 | inst.instruction |= inst.operands[1].reg; | |
8179 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 8180 | } |
c19d1205 ZW |
8181 | \f |
8182 | /* VFP instructions. In a logical order: SP variant first, monad | |
8183 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
8184 | |
8185 | static void | |
c19d1205 | 8186 | do_vfp_sp_monadic (void) |
e16bb312 | 8187 | { |
5287ad62 JB |
8188 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8189 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
8190 | } |
8191 | ||
8192 | static void | |
c19d1205 | 8193 | do_vfp_sp_dyadic (void) |
e16bb312 | 8194 | { |
5287ad62 JB |
8195 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8196 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
8197 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
8198 | } |
8199 | ||
8200 | static void | |
c19d1205 | 8201 | do_vfp_sp_compare_z (void) |
e16bb312 | 8202 | { |
5287ad62 | 8203 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
8204 | } |
8205 | ||
8206 | static void | |
c19d1205 | 8207 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 8208 | { |
5287ad62 JB |
8209 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
8210 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
8211 | } |
8212 | ||
8213 | static void | |
c19d1205 | 8214 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 8215 | { |
5287ad62 JB |
8216 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8217 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
e16bb312 NC |
8218 | } |
8219 | ||
8220 | static void | |
c19d1205 | 8221 | do_vfp_reg_from_sp (void) |
e16bb312 | 8222 | { |
c19d1205 | 8223 | inst.instruction |= inst.operands[0].reg << 12; |
5287ad62 | 8224 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
e16bb312 NC |
8225 | } |
8226 | ||
8227 | static void | |
c19d1205 | 8228 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 8229 | { |
c19d1205 ZW |
8230 | constraint (inst.operands[2].imm != 2, |
8231 | _("only two consecutive VFP SP registers allowed here")); | |
8232 | inst.instruction |= inst.operands[0].reg << 12; | |
8233 | inst.instruction |= inst.operands[1].reg << 16; | |
5287ad62 | 8234 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
e16bb312 NC |
8235 | } |
8236 | ||
8237 | static void | |
c19d1205 | 8238 | do_vfp_sp_from_reg (void) |
e16bb312 | 8239 | { |
5287ad62 | 8240 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
c19d1205 | 8241 | inst.instruction |= inst.operands[1].reg << 12; |
e16bb312 NC |
8242 | } |
8243 | ||
8244 | static void | |
c19d1205 | 8245 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 8246 | { |
c19d1205 ZW |
8247 | constraint (inst.operands[0].imm != 2, |
8248 | _("only two consecutive VFP SP registers allowed here")); | |
5287ad62 | 8249 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
c19d1205 ZW |
8250 | inst.instruction |= inst.operands[1].reg << 12; |
8251 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
8252 | } |
8253 | ||
8254 | static void | |
c19d1205 | 8255 | do_vfp_sp_ldst (void) |
e16bb312 | 8256 | { |
5287ad62 | 8257 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
c19d1205 | 8258 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
8259 | } |
8260 | ||
8261 | static void | |
c19d1205 | 8262 | do_vfp_dp_ldst (void) |
e16bb312 | 8263 | { |
5287ad62 | 8264 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
c19d1205 | 8265 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
8266 | } |
8267 | ||
c19d1205 | 8268 | |
e16bb312 | 8269 | static void |
c19d1205 | 8270 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 8271 | { |
c19d1205 ZW |
8272 | if (inst.operands[0].writeback) |
8273 | inst.instruction |= WRITE_BACK; | |
8274 | else | |
8275 | constraint (ldstm_type != VFP_LDSTMIA, | |
8276 | _("this addressing mode requires base-register writeback")); | |
8277 | inst.instruction |= inst.operands[0].reg << 16; | |
5287ad62 | 8278 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
c19d1205 | 8279 | inst.instruction |= inst.operands[1].imm; |
e16bb312 NC |
8280 | } |
8281 | ||
8282 | static void | |
c19d1205 | 8283 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 8284 | { |
c19d1205 | 8285 | int count; |
e16bb312 | 8286 | |
c19d1205 ZW |
8287 | if (inst.operands[0].writeback) |
8288 | inst.instruction |= WRITE_BACK; | |
8289 | else | |
8290 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
8291 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 8292 | |
c19d1205 | 8293 | inst.instruction |= inst.operands[0].reg << 16; |
5287ad62 | 8294 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
e16bb312 | 8295 | |
c19d1205 ZW |
8296 | count = inst.operands[1].imm << 1; |
8297 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
8298 | count += 1; | |
e16bb312 | 8299 | |
c19d1205 | 8300 | inst.instruction |= count; |
e16bb312 NC |
8301 | } |
8302 | ||
8303 | static void | |
c19d1205 | 8304 | do_vfp_sp_ldstmia (void) |
e16bb312 | 8305 | { |
c19d1205 | 8306 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
8307 | } |
8308 | ||
8309 | static void | |
c19d1205 | 8310 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 8311 | { |
c19d1205 | 8312 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
8313 | } |
8314 | ||
8315 | static void | |
c19d1205 | 8316 | do_vfp_dp_ldstmia (void) |
e16bb312 | 8317 | { |
c19d1205 | 8318 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
8319 | } |
8320 | ||
8321 | static void | |
c19d1205 | 8322 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 8323 | { |
c19d1205 | 8324 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
8325 | } |
8326 | ||
8327 | static void | |
c19d1205 | 8328 | do_vfp_xp_ldstmia (void) |
e16bb312 | 8329 | { |
c19d1205 ZW |
8330 | vfp_dp_ldstm (VFP_LDSTMIAX); |
8331 | } | |
e16bb312 | 8332 | |
c19d1205 ZW |
8333 | static void |
8334 | do_vfp_xp_ldstmdb (void) | |
8335 | { | |
8336 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 8337 | } |
5287ad62 JB |
8338 | |
8339 | static void | |
8340 | do_vfp_dp_rd_rm (void) | |
8341 | { | |
8342 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8343 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
8344 | } | |
8345 | ||
8346 | static void | |
8347 | do_vfp_dp_rn_rd (void) | |
8348 | { | |
8349 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); | |
8350 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
8351 | } | |
8352 | ||
8353 | static void | |
8354 | do_vfp_dp_rd_rn (void) | |
8355 | { | |
8356 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8357 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
8358 | } | |
8359 | ||
8360 | static void | |
8361 | do_vfp_dp_rd_rn_rm (void) | |
8362 | { | |
8363 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8364 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
8365 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); | |
8366 | } | |
8367 | ||
8368 | static void | |
8369 | do_vfp_dp_rd (void) | |
8370 | { | |
8371 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8372 | } | |
8373 | ||
8374 | static void | |
8375 | do_vfp_dp_rm_rd_rn (void) | |
8376 | { | |
8377 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); | |
8378 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
8379 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); | |
8380 | } | |
8381 | ||
8382 | /* VFPv3 instructions. */ | |
8383 | static void | |
8384 | do_vfp_sp_const (void) | |
8385 | { | |
8386 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
00249aaa PB |
8387 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
8388 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
8389 | } |
8390 | ||
8391 | static void | |
8392 | do_vfp_dp_const (void) | |
8393 | { | |
8394 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
00249aaa PB |
8395 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
8396 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
8397 | } |
8398 | ||
8399 | static void | |
8400 | vfp_conv (int srcsize) | |
8401 | { | |
8402 | unsigned immbits = srcsize - inst.operands[1].imm; | |
8403 | inst.instruction |= (immbits & 1) << 5; | |
8404 | inst.instruction |= (immbits >> 1); | |
8405 | } | |
8406 | ||
8407 | static void | |
8408 | do_vfp_sp_conv_16 (void) | |
8409 | { | |
8410 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
8411 | vfp_conv (16); | |
8412 | } | |
8413 | ||
8414 | static void | |
8415 | do_vfp_dp_conv_16 (void) | |
8416 | { | |
8417 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8418 | vfp_conv (16); | |
8419 | } | |
8420 | ||
8421 | static void | |
8422 | do_vfp_sp_conv_32 (void) | |
8423 | { | |
8424 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
8425 | vfp_conv (32); | |
8426 | } | |
8427 | ||
8428 | static void | |
8429 | do_vfp_dp_conv_32 (void) | |
8430 | { | |
8431 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8432 | vfp_conv (32); | |
8433 | } | |
c19d1205 ZW |
8434 | \f |
8435 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 8436 | |
c19d1205 ZW |
8437 | static void |
8438 | do_fpa_cmp (void) | |
8439 | { | |
8440 | inst.instruction |= inst.operands[0].reg << 16; | |
8441 | inst.instruction |= inst.operands[1].reg; | |
8442 | } | |
b99bd4ef NC |
8443 | |
8444 | static void | |
c19d1205 | 8445 | do_fpa_ldmstm (void) |
b99bd4ef | 8446 | { |
c19d1205 ZW |
8447 | inst.instruction |= inst.operands[0].reg << 12; |
8448 | switch (inst.operands[1].imm) | |
8449 | { | |
8450 | case 1: inst.instruction |= CP_T_X; break; | |
8451 | case 2: inst.instruction |= CP_T_Y; break; | |
8452 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
8453 | case 4: break; | |
8454 | default: abort (); | |
8455 | } | |
b99bd4ef | 8456 | |
c19d1205 ZW |
8457 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
8458 | { | |
8459 | /* The instruction specified "ea" or "fd", so we can only accept | |
8460 | [Rn]{!}. The instruction does not really support stacking or | |
8461 | unstacking, so we have to emulate these by setting appropriate | |
8462 | bits and offsets. */ | |
8463 | constraint (inst.reloc.exp.X_op != O_constant | |
8464 | || inst.reloc.exp.X_add_number != 0, | |
8465 | _("this instruction does not support indexing")); | |
b99bd4ef | 8466 | |
c19d1205 ZW |
8467 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
8468 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 8469 | |
c19d1205 ZW |
8470 | if (!(inst.instruction & INDEX_UP)) |
8471 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 8472 | |
c19d1205 ZW |
8473 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
8474 | { | |
8475 | inst.operands[2].preind = 0; | |
8476 | inst.operands[2].postind = 1; | |
8477 | } | |
8478 | } | |
b99bd4ef | 8479 | |
c19d1205 | 8480 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 8481 | } |
c19d1205 ZW |
8482 | \f |
8483 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 8484 | |
c19d1205 ZW |
8485 | static void |
8486 | do_iwmmxt_tandorc (void) | |
8487 | { | |
8488 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
8489 | } | |
b99bd4ef | 8490 | |
c19d1205 ZW |
8491 | static void |
8492 | do_iwmmxt_textrc (void) | |
8493 | { | |
8494 | inst.instruction |= inst.operands[0].reg << 12; | |
8495 | inst.instruction |= inst.operands[1].imm; | |
8496 | } | |
b99bd4ef NC |
8497 | |
8498 | static void | |
c19d1205 | 8499 | do_iwmmxt_textrm (void) |
b99bd4ef | 8500 | { |
c19d1205 ZW |
8501 | inst.instruction |= inst.operands[0].reg << 12; |
8502 | inst.instruction |= inst.operands[1].reg << 16; | |
8503 | inst.instruction |= inst.operands[2].imm; | |
8504 | } | |
b99bd4ef | 8505 | |
c19d1205 ZW |
8506 | static void |
8507 | do_iwmmxt_tinsr (void) | |
8508 | { | |
8509 | inst.instruction |= inst.operands[0].reg << 16; | |
8510 | inst.instruction |= inst.operands[1].reg << 12; | |
8511 | inst.instruction |= inst.operands[2].imm; | |
8512 | } | |
b99bd4ef | 8513 | |
c19d1205 ZW |
8514 | static void |
8515 | do_iwmmxt_tmia (void) | |
8516 | { | |
8517 | inst.instruction |= inst.operands[0].reg << 5; | |
8518 | inst.instruction |= inst.operands[1].reg; | |
8519 | inst.instruction |= inst.operands[2].reg << 12; | |
8520 | } | |
b99bd4ef | 8521 | |
c19d1205 ZW |
8522 | static void |
8523 | do_iwmmxt_waligni (void) | |
8524 | { | |
8525 | inst.instruction |= inst.operands[0].reg << 12; | |
8526 | inst.instruction |= inst.operands[1].reg << 16; | |
8527 | inst.instruction |= inst.operands[2].reg; | |
8528 | inst.instruction |= inst.operands[3].imm << 20; | |
8529 | } | |
b99bd4ef | 8530 | |
2d447fca JM |
8531 | static void |
8532 | do_iwmmxt_wmerge (void) | |
8533 | { | |
8534 | inst.instruction |= inst.operands[0].reg << 12; | |
8535 | inst.instruction |= inst.operands[1].reg << 16; | |
8536 | inst.instruction |= inst.operands[2].reg; | |
8537 | inst.instruction |= inst.operands[3].imm << 21; | |
8538 | } | |
8539 | ||
c19d1205 ZW |
8540 | static void |
8541 | do_iwmmxt_wmov (void) | |
8542 | { | |
8543 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
8544 | inst.instruction |= inst.operands[0].reg << 12; | |
8545 | inst.instruction |= inst.operands[1].reg << 16; | |
8546 | inst.instruction |= inst.operands[1].reg; | |
8547 | } | |
b99bd4ef | 8548 | |
c19d1205 ZW |
8549 | static void |
8550 | do_iwmmxt_wldstbh (void) | |
8551 | { | |
8f06b2d8 | 8552 | int reloc; |
c19d1205 | 8553 | inst.instruction |= inst.operands[0].reg << 12; |
8f06b2d8 PB |
8554 | if (thumb_mode) |
8555 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
8556 | else | |
8557 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
8558 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
8559 | } |
8560 | ||
c19d1205 ZW |
8561 | static void |
8562 | do_iwmmxt_wldstw (void) | |
8563 | { | |
8564 | /* RIWR_RIWC clears .isreg for a control register. */ | |
8565 | if (!inst.operands[0].isreg) | |
8566 | { | |
8567 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
8568 | inst.instruction |= 0xf0000000; | |
8569 | } | |
b99bd4ef | 8570 | |
c19d1205 ZW |
8571 | inst.instruction |= inst.operands[0].reg << 12; |
8572 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
8573 | } | |
b99bd4ef NC |
8574 | |
8575 | static void | |
c19d1205 | 8576 | do_iwmmxt_wldstd (void) |
b99bd4ef | 8577 | { |
c19d1205 | 8578 | inst.instruction |= inst.operands[0].reg << 12; |
2d447fca JM |
8579 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) |
8580 | && inst.operands[1].immisreg) | |
8581 | { | |
8582 | inst.instruction &= ~0x1a000ff; | |
8583 | inst.instruction |= (0xf << 28); | |
8584 | if (inst.operands[1].preind) | |
8585 | inst.instruction |= PRE_INDEX; | |
8586 | if (!inst.operands[1].negative) | |
8587 | inst.instruction |= INDEX_UP; | |
8588 | if (inst.operands[1].writeback) | |
8589 | inst.instruction |= WRITE_BACK; | |
8590 | inst.instruction |= inst.operands[1].reg << 16; | |
8591 | inst.instruction |= inst.reloc.exp.X_add_number << 4; | |
8592 | inst.instruction |= inst.operands[1].imm; | |
8593 | } | |
8594 | else | |
8595 | encode_arm_cp_address (1, TRUE, FALSE, 0); | |
c19d1205 | 8596 | } |
b99bd4ef | 8597 | |
c19d1205 ZW |
8598 | static void |
8599 | do_iwmmxt_wshufh (void) | |
8600 | { | |
8601 | inst.instruction |= inst.operands[0].reg << 12; | |
8602 | inst.instruction |= inst.operands[1].reg << 16; | |
8603 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
8604 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
8605 | } | |
b99bd4ef | 8606 | |
c19d1205 ZW |
8607 | static void |
8608 | do_iwmmxt_wzero (void) | |
8609 | { | |
8610 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
8611 | inst.instruction |= inst.operands[0].reg; | |
8612 | inst.instruction |= inst.operands[0].reg << 12; | |
8613 | inst.instruction |= inst.operands[0].reg << 16; | |
8614 | } | |
2d447fca JM |
8615 | |
8616 | static void | |
8617 | do_iwmmxt_wrwrwr_or_imm5 (void) | |
8618 | { | |
8619 | if (inst.operands[2].isreg) | |
8620 | do_rd_rn_rm (); | |
8621 | else { | |
8622 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), | |
8623 | _("immediate operand requires iWMMXt2")); | |
8624 | do_rd_rn (); | |
8625 | if (inst.operands[2].imm == 0) | |
8626 | { | |
8627 | switch ((inst.instruction >> 20) & 0xf) | |
8628 | { | |
8629 | case 4: | |
8630 | case 5: | |
8631 | case 6: | |
5f4273c7 | 8632 | case 7: |
2d447fca JM |
8633 | /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ |
8634 | inst.operands[2].imm = 16; | |
8635 | inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); | |
8636 | break; | |
8637 | case 8: | |
8638 | case 9: | |
8639 | case 10: | |
8640 | case 11: | |
8641 | /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ | |
8642 | inst.operands[2].imm = 32; | |
8643 | inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); | |
8644 | break; | |
8645 | case 12: | |
8646 | case 13: | |
8647 | case 14: | |
8648 | case 15: | |
8649 | { | |
8650 | /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ | |
8651 | unsigned long wrn; | |
8652 | wrn = (inst.instruction >> 16) & 0xf; | |
8653 | inst.instruction &= 0xff0fff0f; | |
8654 | inst.instruction |= wrn; | |
8655 | /* Bail out here; the instruction is now assembled. */ | |
8656 | return; | |
8657 | } | |
8658 | } | |
8659 | } | |
8660 | /* Map 32 -> 0, etc. */ | |
8661 | inst.operands[2].imm &= 0x1f; | |
8662 | inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); | |
8663 | } | |
8664 | } | |
c19d1205 ZW |
8665 | \f |
8666 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
8667 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 8668 | |
c19d1205 | 8669 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 8670 | |
c19d1205 ZW |
8671 | static void |
8672 | do_mav_triple (void) | |
8673 | { | |
8674 | inst.instruction |= inst.operands[0].reg << 16; | |
8675 | inst.instruction |= inst.operands[1].reg; | |
8676 | inst.instruction |= inst.operands[2].reg << 12; | |
8677 | } | |
b99bd4ef | 8678 | |
c19d1205 ZW |
8679 | /* Insns like "foo W,X,Y,Z". |
8680 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 8681 | |
c19d1205 ZW |
8682 | static void |
8683 | do_mav_quad (void) | |
8684 | { | |
8685 | inst.instruction |= inst.operands[0].reg << 5; | |
8686 | inst.instruction |= inst.operands[1].reg << 12; | |
8687 | inst.instruction |= inst.operands[2].reg << 16; | |
8688 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
8689 | } |
8690 | ||
c19d1205 ZW |
8691 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
8692 | static void | |
8693 | do_mav_dspsc (void) | |
a737bd4d | 8694 | { |
c19d1205 ZW |
8695 | inst.instruction |= inst.operands[1].reg << 12; |
8696 | } | |
a737bd4d | 8697 | |
c19d1205 ZW |
8698 | /* Maverick shift immediate instructions. |
8699 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
8700 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 8701 | |
c19d1205 ZW |
8702 | static void |
8703 | do_mav_shift (void) | |
8704 | { | |
8705 | int imm = inst.operands[2].imm; | |
a737bd4d | 8706 | |
c19d1205 ZW |
8707 | inst.instruction |= inst.operands[0].reg << 12; |
8708 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 8709 | |
c19d1205 ZW |
8710 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
8711 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
8712 | Bit 4 should be 0. */ | |
8713 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 8714 | |
c19d1205 ZW |
8715 | inst.instruction |= imm; |
8716 | } | |
8717 | \f | |
8718 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 8719 | |
c19d1205 ZW |
8720 | /* Xscale multiply-accumulate (argument parse) |
8721 | MIAcc acc0,Rm,Rs | |
8722 | MIAPHcc acc0,Rm,Rs | |
8723 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 8724 | |
c19d1205 ZW |
8725 | static void |
8726 | do_xsc_mia (void) | |
8727 | { | |
8728 | inst.instruction |= inst.operands[1].reg; | |
8729 | inst.instruction |= inst.operands[2].reg << 12; | |
8730 | } | |
a737bd4d | 8731 | |
c19d1205 | 8732 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 8733 | |
c19d1205 | 8734 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 8735 | |
c19d1205 ZW |
8736 | static void |
8737 | do_xsc_mar (void) | |
8738 | { | |
8739 | inst.instruction |= inst.operands[1].reg << 12; | |
8740 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
8741 | } |
8742 | ||
c19d1205 | 8743 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 8744 | |
c19d1205 | 8745 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
8746 | |
8747 | static void | |
c19d1205 | 8748 | do_xsc_mra (void) |
b99bd4ef | 8749 | { |
c19d1205 ZW |
8750 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
8751 | inst.instruction |= inst.operands[0].reg << 12; | |
8752 | inst.instruction |= inst.operands[1].reg << 16; | |
8753 | } | |
8754 | \f | |
8755 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 8756 | |
c19d1205 ZW |
8757 | /* inst.operands[i] is a shifted-register operand; encode |
8758 | it into inst.instruction in the format used by Thumb32. */ | |
8759 | ||
8760 | static void | |
8761 | encode_thumb32_shifted_operand (int i) | |
8762 | { | |
8763 | unsigned int value = inst.reloc.exp.X_add_number; | |
8764 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 8765 | |
9c3c69f2 PB |
8766 | constraint (inst.operands[i].immisreg, |
8767 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
8768 | inst.instruction |= inst.operands[i].reg; |
8769 | if (shift == SHIFT_RRX) | |
8770 | inst.instruction |= SHIFT_ROR << 4; | |
8771 | else | |
b99bd4ef | 8772 | { |
c19d1205 ZW |
8773 | constraint (inst.reloc.exp.X_op != O_constant, |
8774 | _("expression too complex")); | |
8775 | ||
8776 | constraint (value > 32 | |
8777 | || (value == 32 && (shift == SHIFT_LSL | |
8778 | || shift == SHIFT_ROR)), | |
8779 | _("shift expression is too large")); | |
8780 | ||
8781 | if (value == 0) | |
8782 | shift = SHIFT_LSL; | |
8783 | else if (value == 32) | |
8784 | value = 0; | |
8785 | ||
8786 | inst.instruction |= shift << 4; | |
8787 | inst.instruction |= (value & 0x1c) << 10; | |
8788 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 8789 | } |
c19d1205 | 8790 | } |
b99bd4ef | 8791 | |
b99bd4ef | 8792 | |
c19d1205 ZW |
8793 | /* inst.operands[i] was set up by parse_address. Encode it into a |
8794 | Thumb32 format load or store instruction. Reject forms that cannot | |
8795 | be used with such instructions. If is_t is true, reject forms that | |
8796 | cannot be used with a T instruction; if is_d is true, reject forms | |
5be8be5d DG |
8797 | that cannot be used with a D instruction. If it is a store insn, |
8798 | reject PC in Rn. */ | |
b99bd4ef | 8799 | |
c19d1205 ZW |
8800 | static void |
8801 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
8802 | { | |
5be8be5d | 8803 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
c19d1205 ZW |
8804 | |
8805 | constraint (!inst.operands[i].isreg, | |
53365c0d | 8806 | _("Instruction does not support =N addresses")); |
b99bd4ef | 8807 | |
c19d1205 ZW |
8808 | inst.instruction |= inst.operands[i].reg << 16; |
8809 | if (inst.operands[i].immisreg) | |
b99bd4ef | 8810 | { |
5be8be5d | 8811 | constraint (is_pc, BAD_PC_ADDRESSING); |
c19d1205 ZW |
8812 | constraint (is_t || is_d, _("cannot use register index with this instruction")); |
8813 | constraint (inst.operands[i].negative, | |
8814 | _("Thumb does not support negative register indexing")); | |
8815 | constraint (inst.operands[i].postind, | |
8816 | _("Thumb does not support register post-indexing")); | |
8817 | constraint (inst.operands[i].writeback, | |
8818 | _("Thumb does not support register indexing with writeback")); | |
8819 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
8820 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 8821 | |
f40d1643 | 8822 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 8823 | if (inst.operands[i].shifted) |
b99bd4ef | 8824 | { |
c19d1205 ZW |
8825 | constraint (inst.reloc.exp.X_op != O_constant, |
8826 | _("expression too complex")); | |
9c3c69f2 PB |
8827 | constraint (inst.reloc.exp.X_add_number < 0 |
8828 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 8829 | _("shift out of range")); |
9c3c69f2 | 8830 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
8831 | } |
8832 | inst.reloc.type = BFD_RELOC_UNUSED; | |
8833 | } | |
8834 | else if (inst.operands[i].preind) | |
8835 | { | |
5be8be5d | 8836 | constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); |
f40d1643 | 8837 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 | 8838 | _("cannot use writeback with this instruction")); |
5be8be5d DG |
8839 | constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0) |
8840 | && !inst.reloc.pc_rel, BAD_PC_ADDRESSING); | |
c19d1205 ZW |
8841 | |
8842 | if (is_d) | |
8843 | { | |
8844 | inst.instruction |= 0x01000000; | |
8845 | if (inst.operands[i].writeback) | |
8846 | inst.instruction |= 0x00200000; | |
b99bd4ef | 8847 | } |
c19d1205 | 8848 | else |
b99bd4ef | 8849 | { |
c19d1205 ZW |
8850 | inst.instruction |= 0x00000c00; |
8851 | if (inst.operands[i].writeback) | |
8852 | inst.instruction |= 0x00000100; | |
b99bd4ef | 8853 | } |
c19d1205 | 8854 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 8855 | } |
c19d1205 | 8856 | else if (inst.operands[i].postind) |
b99bd4ef | 8857 | { |
9c2799c2 | 8858 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
8859 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); |
8860 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
8861 | ||
8862 | if (is_d) | |
8863 | inst.instruction |= 0x00200000; | |
8864 | else | |
8865 | inst.instruction |= 0x00000900; | |
8866 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
8867 | } | |
8868 | else /* unindexed - only for coprocessor */ | |
8869 | inst.error = _("instruction does not accept unindexed addressing"); | |
8870 | } | |
8871 | ||
8872 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
8873 | encodings (the latter only in post-V6T2 cores). The index is the | |
8874 | value used in the insns table below. When there is more than one | |
8875 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
8876 | holds variant (1). |
8877 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 | 8878 | #define T16_32_TAB \ |
21d799b5 NC |
8879 | X(_adc, 4140, eb400000), \ |
8880 | X(_adcs, 4140, eb500000), \ | |
8881 | X(_add, 1c00, eb000000), \ | |
8882 | X(_adds, 1c00, eb100000), \ | |
8883 | X(_addi, 0000, f1000000), \ | |
8884 | X(_addis, 0000, f1100000), \ | |
8885 | X(_add_pc,000f, f20f0000), \ | |
8886 | X(_add_sp,000d, f10d0000), \ | |
8887 | X(_adr, 000f, f20f0000), \ | |
8888 | X(_and, 4000, ea000000), \ | |
8889 | X(_ands, 4000, ea100000), \ | |
8890 | X(_asr, 1000, fa40f000), \ | |
8891 | X(_asrs, 1000, fa50f000), \ | |
8892 | X(_b, e000, f000b000), \ | |
8893 | X(_bcond, d000, f0008000), \ | |
8894 | X(_bic, 4380, ea200000), \ | |
8895 | X(_bics, 4380, ea300000), \ | |
8896 | X(_cmn, 42c0, eb100f00), \ | |
8897 | X(_cmp, 2800, ebb00f00), \ | |
8898 | X(_cpsie, b660, f3af8400), \ | |
8899 | X(_cpsid, b670, f3af8600), \ | |
8900 | X(_cpy, 4600, ea4f0000), \ | |
8901 | X(_dec_sp,80dd, f1ad0d00), \ | |
8902 | X(_eor, 4040, ea800000), \ | |
8903 | X(_eors, 4040, ea900000), \ | |
8904 | X(_inc_sp,00dd, f10d0d00), \ | |
8905 | X(_ldmia, c800, e8900000), \ | |
8906 | X(_ldr, 6800, f8500000), \ | |
8907 | X(_ldrb, 7800, f8100000), \ | |
8908 | X(_ldrh, 8800, f8300000), \ | |
8909 | X(_ldrsb, 5600, f9100000), \ | |
8910 | X(_ldrsh, 5e00, f9300000), \ | |
8911 | X(_ldr_pc,4800, f85f0000), \ | |
8912 | X(_ldr_pc2,4800, f85f0000), \ | |
8913 | X(_ldr_sp,9800, f85d0000), \ | |
8914 | X(_lsl, 0000, fa00f000), \ | |
8915 | X(_lsls, 0000, fa10f000), \ | |
8916 | X(_lsr, 0800, fa20f000), \ | |
8917 | X(_lsrs, 0800, fa30f000), \ | |
8918 | X(_mov, 2000, ea4f0000), \ | |
8919 | X(_movs, 2000, ea5f0000), \ | |
8920 | X(_mul, 4340, fb00f000), \ | |
8921 | X(_muls, 4340, ffffffff), /* no 32b muls */ \ | |
8922 | X(_mvn, 43c0, ea6f0000), \ | |
8923 | X(_mvns, 43c0, ea7f0000), \ | |
8924 | X(_neg, 4240, f1c00000), /* rsb #0 */ \ | |
8925 | X(_negs, 4240, f1d00000), /* rsbs #0 */ \ | |
8926 | X(_orr, 4300, ea400000), \ | |
8927 | X(_orrs, 4300, ea500000), \ | |
8928 | X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \ | |
8929 | X(_push, b400, e92d0000), /* stmdb sp!,... */ \ | |
8930 | X(_rev, ba00, fa90f080), \ | |
8931 | X(_rev16, ba40, fa90f090), \ | |
8932 | X(_revsh, bac0, fa90f0b0), \ | |
8933 | X(_ror, 41c0, fa60f000), \ | |
8934 | X(_rors, 41c0, fa70f000), \ | |
8935 | X(_sbc, 4180, eb600000), \ | |
8936 | X(_sbcs, 4180, eb700000), \ | |
8937 | X(_stmia, c000, e8800000), \ | |
8938 | X(_str, 6000, f8400000), \ | |
8939 | X(_strb, 7000, f8000000), \ | |
8940 | X(_strh, 8000, f8200000), \ | |
8941 | X(_str_sp,9000, f84d0000), \ | |
8942 | X(_sub, 1e00, eba00000), \ | |
8943 | X(_subs, 1e00, ebb00000), \ | |
8944 | X(_subi, 8000, f1a00000), \ | |
8945 | X(_subis, 8000, f1b00000), \ | |
8946 | X(_sxtb, b240, fa4ff080), \ | |
8947 | X(_sxth, b200, fa0ff080), \ | |
8948 | X(_tst, 4200, ea100f00), \ | |
8949 | X(_uxtb, b2c0, fa5ff080), \ | |
8950 | X(_uxth, b280, fa1ff080), \ | |
8951 | X(_nop, bf00, f3af8000), \ | |
8952 | X(_yield, bf10, f3af8001), \ | |
8953 | X(_wfe, bf20, f3af8002), \ | |
8954 | X(_wfi, bf30, f3af8003), \ | |
8955 | X(_sev, bf40, f3af8004), | |
c19d1205 ZW |
8956 | |
8957 | /* To catch errors in encoding functions, the codes are all offset by | |
8958 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
8959 | as 16-bit instructions. */ | |
21d799b5 | 8960 | #define X(a,b,c) T_MNEM##a |
c19d1205 ZW |
8961 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; |
8962 | #undef X | |
8963 | ||
8964 | #define X(a,b,c) 0x##b | |
8965 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
8966 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
8967 | #undef X | |
8968 | ||
8969 | #define X(a,b,c) 0x##c | |
8970 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
c921be7d NC |
8971 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) |
8972 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
c19d1205 ZW |
8973 | #undef X |
8974 | #undef T16_32_TAB | |
8975 | ||
8976 | /* Thumb instruction encoders, in alphabetical order. */ | |
8977 | ||
92e90b6e | 8978 | /* ADDW or SUBW. */ |
c921be7d | 8979 | |
92e90b6e PB |
8980 | static void |
8981 | do_t_add_sub_w (void) | |
8982 | { | |
8983 | int Rd, Rn; | |
8984 | ||
8985 | Rd = inst.operands[0].reg; | |
8986 | Rn = inst.operands[1].reg; | |
8987 | ||
539d4391 NC |
8988 | /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this |
8989 | is the SP-{plus,minus}-immediate form of the instruction. */ | |
8990 | if (Rn == REG_SP) | |
8991 | constraint (Rd == REG_PC, BAD_PC); | |
8992 | else | |
8993 | reject_bad_reg (Rd); | |
fdfde340 | 8994 | |
92e90b6e PB |
8995 | inst.instruction |= (Rn << 16) | (Rd << 8); |
8996 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
8997 | } | |
8998 | ||
c19d1205 ZW |
8999 | /* Parse an add or subtract instruction. We get here with inst.instruction |
9000 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
9001 | ||
9002 | static void | |
9003 | do_t_add_sub (void) | |
9004 | { | |
9005 | int Rd, Rs, Rn; | |
9006 | ||
9007 | Rd = inst.operands[0].reg; | |
9008 | Rs = (inst.operands[1].present | |
9009 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9010 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9011 | ||
e07e6e58 NC |
9012 | if (Rd == REG_PC) |
9013 | set_it_insn_type_last (); | |
9014 | ||
c19d1205 ZW |
9015 | if (unified_syntax) |
9016 | { | |
0110f2b8 PB |
9017 | bfd_boolean flags; |
9018 | bfd_boolean narrow; | |
9019 | int opcode; | |
9020 | ||
9021 | flags = (inst.instruction == T_MNEM_adds | |
9022 | || inst.instruction == T_MNEM_subs); | |
9023 | if (flags) | |
e07e6e58 | 9024 | narrow = !in_it_block (); |
0110f2b8 | 9025 | else |
e07e6e58 | 9026 | narrow = in_it_block (); |
c19d1205 | 9027 | if (!inst.operands[2].isreg) |
b99bd4ef | 9028 | { |
16805f35 PB |
9029 | int add; |
9030 | ||
fdfde340 JM |
9031 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); |
9032 | ||
16805f35 PB |
9033 | add = (inst.instruction == T_MNEM_add |
9034 | || inst.instruction == T_MNEM_adds); | |
0110f2b8 PB |
9035 | opcode = 0; |
9036 | if (inst.size_req != 4) | |
9037 | { | |
0110f2b8 PB |
9038 | /* Attempt to use a narrow opcode, with relaxation if |
9039 | appropriate. */ | |
9040 | if (Rd == REG_SP && Rs == REG_SP && !flags) | |
9041 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
9042 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
9043 | opcode = T_MNEM_add_sp; | |
9044 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
9045 | opcode = T_MNEM_add_pc; | |
9046 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
9047 | { | |
9048 | if (flags) | |
9049 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
9050 | else | |
9051 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
9052 | } | |
9053 | if (opcode) | |
9054 | { | |
9055 | inst.instruction = THUMB_OP16(opcode); | |
9056 | inst.instruction |= (Rd << 4) | Rs; | |
9057 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
9058 | if (inst.size_req != 2) | |
9059 | inst.relax = opcode; | |
9060 | } | |
9061 | else | |
9062 | constraint (inst.size_req == 2, BAD_HIREG); | |
9063 | } | |
9064 | if (inst.size_req == 4 | |
9065 | || (inst.size_req != 2 && !opcode)) | |
9066 | { | |
efd81785 PB |
9067 | if (Rd == REG_PC) |
9068 | { | |
fdfde340 | 9069 | constraint (add, BAD_PC); |
efd81785 PB |
9070 | constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, |
9071 | _("only SUBS PC, LR, #const allowed")); | |
9072 | constraint (inst.reloc.exp.X_op != O_constant, | |
9073 | _("expression too complex")); | |
9074 | constraint (inst.reloc.exp.X_add_number < 0 | |
9075 | || inst.reloc.exp.X_add_number > 0xff, | |
9076 | _("immediate value out of range")); | |
9077 | inst.instruction = T2_SUBS_PC_LR | |
9078 | | inst.reloc.exp.X_add_number; | |
9079 | inst.reloc.type = BFD_RELOC_UNUSED; | |
9080 | return; | |
9081 | } | |
9082 | else if (Rs == REG_PC) | |
16805f35 PB |
9083 | { |
9084 | /* Always use addw/subw. */ | |
9085 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; | |
9086 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
9087 | } | |
9088 | else | |
9089 | { | |
9090 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9091 | inst.instruction = (inst.instruction & 0xe1ffffff) | |
9092 | | 0x10000000; | |
9093 | if (flags) | |
9094 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9095 | else | |
9096 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; | |
9097 | } | |
dc4503c6 PB |
9098 | inst.instruction |= Rd << 8; |
9099 | inst.instruction |= Rs << 16; | |
0110f2b8 | 9100 | } |
b99bd4ef | 9101 | } |
c19d1205 ZW |
9102 | else |
9103 | { | |
9104 | Rn = inst.operands[2].reg; | |
9105 | /* See if we can do this with a 16-bit instruction. */ | |
9106 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
9107 | { | |
e27ec89e PB |
9108 | if (Rd > 7 || Rs > 7 || Rn > 7) |
9109 | narrow = FALSE; | |
9110 | ||
9111 | if (narrow) | |
c19d1205 | 9112 | { |
e27ec89e PB |
9113 | inst.instruction = ((inst.instruction == T_MNEM_adds |
9114 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
9115 | ? T_OPCODE_ADD_R3 |
9116 | : T_OPCODE_SUB_R3); | |
9117 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
9118 | return; | |
9119 | } | |
b99bd4ef | 9120 | |
7e806470 | 9121 | if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) |
c19d1205 | 9122 | { |
7e806470 PB |
9123 | /* Thumb-1 cores (except v6-M) require at least one high |
9124 | register in a narrow non flag setting add. */ | |
9125 | if (Rd > 7 || Rn > 7 | |
9126 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) | |
9127 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) | |
c19d1205 | 9128 | { |
7e806470 PB |
9129 | if (Rd == Rn) |
9130 | { | |
9131 | Rn = Rs; | |
9132 | Rs = Rd; | |
9133 | } | |
c19d1205 ZW |
9134 | inst.instruction = T_OPCODE_ADD_HI; |
9135 | inst.instruction |= (Rd & 8) << 4; | |
9136 | inst.instruction |= (Rd & 7); | |
9137 | inst.instruction |= Rn << 3; | |
9138 | return; | |
9139 | } | |
c19d1205 ZW |
9140 | } |
9141 | } | |
c921be7d | 9142 | |
fdfde340 JM |
9143 | constraint (Rd == REG_PC, BAD_PC); |
9144 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
9145 | constraint (Rs == REG_PC, BAD_PC); | |
9146 | reject_bad_reg (Rn); | |
9147 | ||
c19d1205 ZW |
9148 | /* If we get here, it can't be done in 16 bits. */ |
9149 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
9150 | _("shift must be constant")); | |
9151 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9152 | inst.instruction |= Rd << 8; | |
9153 | inst.instruction |= Rs << 16; | |
9154 | encode_thumb32_shifted_operand (2); | |
9155 | } | |
9156 | } | |
9157 | else | |
9158 | { | |
9159 | constraint (inst.instruction == T_MNEM_adds | |
9160 | || inst.instruction == T_MNEM_subs, | |
9161 | BAD_THUMB32); | |
b99bd4ef | 9162 | |
c19d1205 | 9163 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 9164 | { |
c19d1205 ZW |
9165 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
9166 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
9167 | BAD_HIREG); | |
9168 | ||
9169 | inst.instruction = (inst.instruction == T_MNEM_add | |
9170 | ? 0x0000 : 0x8000); | |
9171 | inst.instruction |= (Rd << 4) | Rs; | |
9172 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
9173 | return; |
9174 | } | |
9175 | ||
c19d1205 ZW |
9176 | Rn = inst.operands[2].reg; |
9177 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 9178 | |
c19d1205 ZW |
9179 | /* We now have Rd, Rs, and Rn set to registers. */ |
9180 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 9181 | { |
c19d1205 ZW |
9182 | /* Can't do this for SUB. */ |
9183 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
9184 | inst.instruction = T_OPCODE_ADD_HI; | |
9185 | inst.instruction |= (Rd & 8) << 4; | |
9186 | inst.instruction |= (Rd & 7); | |
9187 | if (Rs == Rd) | |
9188 | inst.instruction |= Rn << 3; | |
9189 | else if (Rn == Rd) | |
9190 | inst.instruction |= Rs << 3; | |
9191 | else | |
9192 | constraint (1, _("dest must overlap one source register")); | |
9193 | } | |
9194 | else | |
9195 | { | |
9196 | inst.instruction = (inst.instruction == T_MNEM_add | |
9197 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
9198 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 9199 | } |
b99bd4ef | 9200 | } |
b99bd4ef NC |
9201 | } |
9202 | ||
c19d1205 ZW |
9203 | static void |
9204 | do_t_adr (void) | |
9205 | { | |
fdfde340 JM |
9206 | unsigned Rd; |
9207 | ||
9208 | Rd = inst.operands[0].reg; | |
9209 | reject_bad_reg (Rd); | |
9210 | ||
9211 | if (unified_syntax && inst.size_req == 0 && Rd <= 7) | |
0110f2b8 PB |
9212 | { |
9213 | /* Defer to section relaxation. */ | |
9214 | inst.relax = inst.instruction; | |
9215 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 | 9216 | inst.instruction |= Rd << 4; |
0110f2b8 PB |
9217 | } |
9218 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 9219 | { |
0110f2b8 | 9220 | /* Generate a 32-bit opcode. */ |
e9f89963 | 9221 | inst.instruction = THUMB_OP32 (inst.instruction); |
fdfde340 | 9222 | inst.instruction |= Rd << 8; |
e9f89963 PB |
9223 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; |
9224 | inst.reloc.pc_rel = 1; | |
9225 | } | |
9226 | else | |
9227 | { | |
0110f2b8 | 9228 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
9229 | inst.instruction = THUMB_OP16 (inst.instruction); |
9230 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
9231 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
9232 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 9233 | |
fdfde340 | 9234 | inst.instruction |= Rd << 4; |
e9f89963 | 9235 | } |
c19d1205 | 9236 | } |
b99bd4ef | 9237 | |
c19d1205 ZW |
9238 | /* Arithmetic instructions for which there is just one 16-bit |
9239 | instruction encoding, and it allows only two low registers. | |
9240 | For maximal compatibility with ARM syntax, we allow three register | |
9241 | operands even when Thumb-32 instructions are not available, as long | |
9242 | as the first two are identical. For instance, both "sbc r0,r1" and | |
9243 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 9244 | static void |
c19d1205 | 9245 | do_t_arit3 (void) |
b99bd4ef | 9246 | { |
c19d1205 | 9247 | int Rd, Rs, Rn; |
b99bd4ef | 9248 | |
c19d1205 ZW |
9249 | Rd = inst.operands[0].reg; |
9250 | Rs = (inst.operands[1].present | |
9251 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9252 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9253 | Rn = inst.operands[2].reg; | |
b99bd4ef | 9254 | |
fdfde340 JM |
9255 | reject_bad_reg (Rd); |
9256 | reject_bad_reg (Rs); | |
9257 | if (inst.operands[2].isreg) | |
9258 | reject_bad_reg (Rn); | |
9259 | ||
c19d1205 | 9260 | if (unified_syntax) |
b99bd4ef | 9261 | { |
c19d1205 ZW |
9262 | if (!inst.operands[2].isreg) |
9263 | { | |
9264 | /* For an immediate, we always generate a 32-bit opcode; | |
9265 | section relaxation will shrink it later if possible. */ | |
9266 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9267 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9268 | inst.instruction |= Rd << 8; | |
9269 | inst.instruction |= Rs << 16; | |
9270 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9271 | } | |
9272 | else | |
9273 | { | |
e27ec89e PB |
9274 | bfd_boolean narrow; |
9275 | ||
c19d1205 | 9276 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 9277 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 9278 | narrow = !in_it_block (); |
e27ec89e | 9279 | else |
e07e6e58 | 9280 | narrow = in_it_block (); |
e27ec89e PB |
9281 | |
9282 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
9283 | narrow = FALSE; | |
9284 | if (inst.operands[2].shifted) | |
9285 | narrow = FALSE; | |
9286 | if (inst.size_req == 4) | |
9287 | narrow = FALSE; | |
9288 | ||
9289 | if (narrow | |
c19d1205 ZW |
9290 | && Rd == Rs) |
9291 | { | |
9292 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9293 | inst.instruction |= Rd; | |
9294 | inst.instruction |= Rn << 3; | |
9295 | return; | |
9296 | } | |
b99bd4ef | 9297 | |
c19d1205 ZW |
9298 | /* If we get here, it can't be done in 16 bits. */ |
9299 | constraint (inst.operands[2].shifted | |
9300 | && inst.operands[2].immisreg, | |
9301 | _("shift must be constant")); | |
9302 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9303 | inst.instruction |= Rd << 8; | |
9304 | inst.instruction |= Rs << 16; | |
9305 | encode_thumb32_shifted_operand (2); | |
9306 | } | |
a737bd4d | 9307 | } |
c19d1205 | 9308 | else |
b99bd4ef | 9309 | { |
c19d1205 ZW |
9310 | /* On its face this is a lie - the instruction does set the |
9311 | flags. However, the only supported mnemonic in this mode | |
9312 | says it doesn't. */ | |
9313 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 9314 | |
c19d1205 ZW |
9315 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
9316 | _("unshifted register required")); | |
9317 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
9318 | constraint (Rd != Rs, | |
9319 | _("dest and source1 must be the same register")); | |
a737bd4d | 9320 | |
c19d1205 ZW |
9321 | inst.instruction = THUMB_OP16 (inst.instruction); |
9322 | inst.instruction |= Rd; | |
9323 | inst.instruction |= Rn << 3; | |
b99bd4ef | 9324 | } |
a737bd4d | 9325 | } |
b99bd4ef | 9326 | |
c19d1205 ZW |
9327 | /* Similarly, but for instructions where the arithmetic operation is |
9328 | commutative, so we can allow either of them to be different from | |
9329 | the destination operand in a 16-bit instruction. For instance, all | |
9330 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
9331 | accepted. */ | |
9332 | static void | |
9333 | do_t_arit3c (void) | |
a737bd4d | 9334 | { |
c19d1205 | 9335 | int Rd, Rs, Rn; |
b99bd4ef | 9336 | |
c19d1205 ZW |
9337 | Rd = inst.operands[0].reg; |
9338 | Rs = (inst.operands[1].present | |
9339 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9340 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9341 | Rn = inst.operands[2].reg; | |
c921be7d | 9342 | |
fdfde340 JM |
9343 | reject_bad_reg (Rd); |
9344 | reject_bad_reg (Rs); | |
9345 | if (inst.operands[2].isreg) | |
9346 | reject_bad_reg (Rn); | |
a737bd4d | 9347 | |
c19d1205 | 9348 | if (unified_syntax) |
a737bd4d | 9349 | { |
c19d1205 | 9350 | if (!inst.operands[2].isreg) |
b99bd4ef | 9351 | { |
c19d1205 ZW |
9352 | /* For an immediate, we always generate a 32-bit opcode; |
9353 | section relaxation will shrink it later if possible. */ | |
9354 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9355 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9356 | inst.instruction |= Rd << 8; | |
9357 | inst.instruction |= Rs << 16; | |
9358 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 9359 | } |
c19d1205 | 9360 | else |
a737bd4d | 9361 | { |
e27ec89e PB |
9362 | bfd_boolean narrow; |
9363 | ||
c19d1205 | 9364 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 9365 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 9366 | narrow = !in_it_block (); |
e27ec89e | 9367 | else |
e07e6e58 | 9368 | narrow = in_it_block (); |
e27ec89e PB |
9369 | |
9370 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
9371 | narrow = FALSE; | |
9372 | if (inst.operands[2].shifted) | |
9373 | narrow = FALSE; | |
9374 | if (inst.size_req == 4) | |
9375 | narrow = FALSE; | |
9376 | ||
9377 | if (narrow) | |
a737bd4d | 9378 | { |
c19d1205 | 9379 | if (Rd == Rs) |
a737bd4d | 9380 | { |
c19d1205 ZW |
9381 | inst.instruction = THUMB_OP16 (inst.instruction); |
9382 | inst.instruction |= Rd; | |
9383 | inst.instruction |= Rn << 3; | |
9384 | return; | |
a737bd4d | 9385 | } |
c19d1205 | 9386 | if (Rd == Rn) |
a737bd4d | 9387 | { |
c19d1205 ZW |
9388 | inst.instruction = THUMB_OP16 (inst.instruction); |
9389 | inst.instruction |= Rd; | |
9390 | inst.instruction |= Rs << 3; | |
9391 | return; | |
a737bd4d NC |
9392 | } |
9393 | } | |
c19d1205 ZW |
9394 | |
9395 | /* If we get here, it can't be done in 16 bits. */ | |
9396 | constraint (inst.operands[2].shifted | |
9397 | && inst.operands[2].immisreg, | |
9398 | _("shift must be constant")); | |
9399 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9400 | inst.instruction |= Rd << 8; | |
9401 | inst.instruction |= Rs << 16; | |
9402 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 9403 | } |
b99bd4ef | 9404 | } |
c19d1205 ZW |
9405 | else |
9406 | { | |
9407 | /* On its face this is a lie - the instruction does set the | |
9408 | flags. However, the only supported mnemonic in this mode | |
9409 | says it doesn't. */ | |
9410 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 9411 | |
c19d1205 ZW |
9412 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
9413 | _("unshifted register required")); | |
9414 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
9415 | ||
9416 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9417 | inst.instruction |= Rd; | |
9418 | ||
9419 | if (Rd == Rs) | |
9420 | inst.instruction |= Rn << 3; | |
9421 | else if (Rd == Rn) | |
9422 | inst.instruction |= Rs << 3; | |
9423 | else | |
9424 | constraint (1, _("dest must overlap one source register")); | |
9425 | } | |
a737bd4d NC |
9426 | } |
9427 | ||
62b3e311 PB |
9428 | static void |
9429 | do_t_barrier (void) | |
9430 | { | |
9431 | if (inst.operands[0].present) | |
9432 | { | |
9433 | constraint ((inst.instruction & 0xf0) != 0x40 | |
9434 | && inst.operands[0].imm != 0xf, | |
bd3ba5d1 | 9435 | _("bad barrier type")); |
62b3e311 PB |
9436 | inst.instruction |= inst.operands[0].imm; |
9437 | } | |
9438 | else | |
9439 | inst.instruction |= 0xf; | |
9440 | } | |
9441 | ||
c19d1205 ZW |
9442 | static void |
9443 | do_t_bfc (void) | |
a737bd4d | 9444 | { |
fdfde340 | 9445 | unsigned Rd; |
c19d1205 ZW |
9446 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
9447 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9448 | /* The instruction encoding stores the LSB and MSB, | |
9449 | not the LSB and width. */ | |
fdfde340 JM |
9450 | Rd = inst.operands[0].reg; |
9451 | reject_bad_reg (Rd); | |
9452 | inst.instruction |= Rd << 8; | |
c19d1205 ZW |
9453 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; |
9454 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
9455 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
9456 | } |
9457 | ||
c19d1205 ZW |
9458 | static void |
9459 | do_t_bfi (void) | |
b99bd4ef | 9460 | { |
fdfde340 | 9461 | int Rd, Rn; |
c19d1205 | 9462 | unsigned int msb; |
b99bd4ef | 9463 | |
fdfde340 JM |
9464 | Rd = inst.operands[0].reg; |
9465 | reject_bad_reg (Rd); | |
9466 | ||
c19d1205 ZW |
9467 | /* #0 in second position is alternative syntax for bfc, which is |
9468 | the same instruction but with REG_PC in the Rm field. */ | |
9469 | if (!inst.operands[1].isreg) | |
fdfde340 JM |
9470 | Rn = REG_PC; |
9471 | else | |
9472 | { | |
9473 | Rn = inst.operands[1].reg; | |
9474 | reject_bad_reg (Rn); | |
9475 | } | |
b99bd4ef | 9476 | |
c19d1205 ZW |
9477 | msb = inst.operands[2].imm + inst.operands[3].imm; |
9478 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9479 | /* The instruction encoding stores the LSB and MSB, | |
9480 | not the LSB and width. */ | |
fdfde340 JM |
9481 | inst.instruction |= Rd << 8; |
9482 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
9483 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
9484 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
9485 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
9486 | } |
9487 | ||
c19d1205 ZW |
9488 | static void |
9489 | do_t_bfx (void) | |
b99bd4ef | 9490 | { |
fdfde340 JM |
9491 | unsigned Rd, Rn; |
9492 | ||
9493 | Rd = inst.operands[0].reg; | |
9494 | Rn = inst.operands[1].reg; | |
9495 | ||
9496 | reject_bad_reg (Rd); | |
9497 | reject_bad_reg (Rn); | |
9498 | ||
c19d1205 ZW |
9499 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
9500 | _("bit-field extends past end of register")); | |
fdfde340 JM |
9501 | inst.instruction |= Rd << 8; |
9502 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
9503 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
9504 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
9505 | inst.instruction |= inst.operands[3].imm - 1; | |
9506 | } | |
b99bd4ef | 9507 | |
c19d1205 ZW |
9508 | /* ARM V5 Thumb BLX (argument parse) |
9509 | BLX <target_addr> which is BLX(1) | |
9510 | BLX <Rm> which is BLX(2) | |
9511 | Unfortunately, there are two different opcodes for this mnemonic. | |
9512 | So, the insns[].value is not used, and the code here zaps values | |
9513 | into inst.instruction. | |
b99bd4ef | 9514 | |
c19d1205 ZW |
9515 | ??? How to take advantage of the additional two bits of displacement |
9516 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 9517 | |
c19d1205 ZW |
9518 | static void |
9519 | do_t_blx (void) | |
9520 | { | |
e07e6e58 NC |
9521 | set_it_insn_type_last (); |
9522 | ||
c19d1205 | 9523 | if (inst.operands[0].isreg) |
fdfde340 JM |
9524 | { |
9525 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); | |
9526 | /* We have a register, so this is BLX(2). */ | |
9527 | inst.instruction |= inst.operands[0].reg << 3; | |
9528 | } | |
b99bd4ef NC |
9529 | else |
9530 | { | |
c19d1205 | 9531 | /* No register. This must be BLX(1). */ |
2fc8bdac | 9532 | inst.instruction = 0xf000e800; |
00adf2d4 | 9533 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; |
c19d1205 | 9534 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
9535 | } |
9536 | } | |
9537 | ||
c19d1205 ZW |
9538 | static void |
9539 | do_t_branch (void) | |
b99bd4ef | 9540 | { |
0110f2b8 | 9541 | int opcode; |
dfa9f0d5 PB |
9542 | int cond; |
9543 | ||
e07e6e58 NC |
9544 | cond = inst.cond; |
9545 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); | |
9546 | ||
9547 | if (in_it_block ()) | |
dfa9f0d5 PB |
9548 | { |
9549 | /* Conditional branches inside IT blocks are encoded as unconditional | |
9550 | branches. */ | |
9551 | cond = COND_ALWAYS; | |
dfa9f0d5 PB |
9552 | } |
9553 | else | |
9554 | cond = inst.cond; | |
9555 | ||
9556 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
9557 | opcode = T_MNEM_bcond; |
9558 | else | |
9559 | opcode = inst.instruction; | |
9560 | ||
9561 | if (unified_syntax && inst.size_req == 4) | |
c19d1205 | 9562 | { |
0110f2b8 | 9563 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 9564 | if (cond == COND_ALWAYS) |
0110f2b8 | 9565 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
9566 | else |
9567 | { | |
9c2799c2 | 9568 | gas_assert (cond != 0xF); |
dfa9f0d5 | 9569 | inst.instruction |= cond << 22; |
c19d1205 ZW |
9570 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20; |
9571 | } | |
9572 | } | |
b99bd4ef NC |
9573 | else |
9574 | { | |
0110f2b8 | 9575 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 9576 | if (cond == COND_ALWAYS) |
c19d1205 ZW |
9577 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; |
9578 | else | |
b99bd4ef | 9579 | { |
dfa9f0d5 | 9580 | inst.instruction |= cond << 8; |
c19d1205 | 9581 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 9582 | } |
0110f2b8 PB |
9583 | /* Allow section relaxation. */ |
9584 | if (unified_syntax && inst.size_req != 2) | |
9585 | inst.relax = opcode; | |
b99bd4ef | 9586 | } |
c19d1205 ZW |
9587 | |
9588 | inst.reloc.pc_rel = 1; | |
b99bd4ef NC |
9589 | } |
9590 | ||
9591 | static void | |
c19d1205 | 9592 | do_t_bkpt (void) |
b99bd4ef | 9593 | { |
dfa9f0d5 PB |
9594 | constraint (inst.cond != COND_ALWAYS, |
9595 | _("instruction is always unconditional")); | |
c19d1205 | 9596 | if (inst.operands[0].present) |
b99bd4ef | 9597 | { |
c19d1205 ZW |
9598 | constraint (inst.operands[0].imm > 255, |
9599 | _("immediate value out of range")); | |
9600 | inst.instruction |= inst.operands[0].imm; | |
e07e6e58 | 9601 | set_it_insn_type (NEUTRAL_IT_INSN); |
b99bd4ef | 9602 | } |
b99bd4ef NC |
9603 | } |
9604 | ||
9605 | static void | |
c19d1205 | 9606 | do_t_branch23 (void) |
b99bd4ef | 9607 | { |
e07e6e58 | 9608 | set_it_insn_type_last (); |
c19d1205 | 9609 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; |
90e4755a RE |
9610 | inst.reloc.pc_rel = 1; |
9611 | ||
4343666d | 9612 | #if defined(OBJ_COFF) |
c19d1205 ZW |
9613 | /* If the destination of the branch is a defined symbol which does not have |
9614 | the THUMB_FUNC attribute, then we must be calling a function which has | |
9615 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
9616 | function and change the branch to refer to that function instead. */ | |
9617 | if ( inst.reloc.exp.X_op == O_symbol | |
9618 | && inst.reloc.exp.X_add_symbol != NULL | |
9619 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
9620 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
9621 | inst.reloc.exp.X_add_symbol = | |
9622 | find_real_start (inst.reloc.exp.X_add_symbol); | |
4343666d | 9623 | #endif |
90e4755a RE |
9624 | } |
9625 | ||
9626 | static void | |
c19d1205 | 9627 | do_t_bx (void) |
90e4755a | 9628 | { |
e07e6e58 | 9629 | set_it_insn_type_last (); |
c19d1205 ZW |
9630 | inst.instruction |= inst.operands[0].reg << 3; |
9631 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
9632 | should cause the alignment to be checked once it is known. This is | |
9633 | because BX PC only works if the instruction is word aligned. */ | |
9634 | } | |
90e4755a | 9635 | |
c19d1205 ZW |
9636 | static void |
9637 | do_t_bxj (void) | |
9638 | { | |
fdfde340 | 9639 | int Rm; |
90e4755a | 9640 | |
e07e6e58 | 9641 | set_it_insn_type_last (); |
fdfde340 JM |
9642 | Rm = inst.operands[0].reg; |
9643 | reject_bad_reg (Rm); | |
9644 | inst.instruction |= Rm << 16; | |
90e4755a RE |
9645 | } |
9646 | ||
9647 | static void | |
c19d1205 | 9648 | do_t_clz (void) |
90e4755a | 9649 | { |
fdfde340 JM |
9650 | unsigned Rd; |
9651 | unsigned Rm; | |
9652 | ||
9653 | Rd = inst.operands[0].reg; | |
9654 | Rm = inst.operands[1].reg; | |
9655 | ||
9656 | reject_bad_reg (Rd); | |
9657 | reject_bad_reg (Rm); | |
9658 | ||
9659 | inst.instruction |= Rd << 8; | |
9660 | inst.instruction |= Rm << 16; | |
9661 | inst.instruction |= Rm; | |
c19d1205 | 9662 | } |
90e4755a | 9663 | |
dfa9f0d5 PB |
9664 | static void |
9665 | do_t_cps (void) | |
9666 | { | |
e07e6e58 | 9667 | set_it_insn_type (OUTSIDE_IT_INSN); |
dfa9f0d5 PB |
9668 | inst.instruction |= inst.operands[0].imm; |
9669 | } | |
9670 | ||
c19d1205 ZW |
9671 | static void |
9672 | do_t_cpsi (void) | |
9673 | { | |
e07e6e58 | 9674 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 | 9675 | if (unified_syntax |
62b3e311 PB |
9676 | && (inst.operands[1].present || inst.size_req == 4) |
9677 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 9678 | { |
c19d1205 ZW |
9679 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
9680 | inst.instruction = 0xf3af8000; | |
9681 | inst.instruction |= imod << 9; | |
9682 | inst.instruction |= inst.operands[0].imm << 5; | |
9683 | if (inst.operands[1].present) | |
9684 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 9685 | } |
c19d1205 | 9686 | else |
90e4755a | 9687 | { |
62b3e311 PB |
9688 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
9689 | && (inst.operands[0].imm & 4), | |
9690 | _("selected processor does not support 'A' form " | |
9691 | "of this instruction")); | |
9692 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
9693 | _("Thumb does not support the 2-argument " |
9694 | "form of this instruction")); | |
9695 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 9696 | } |
90e4755a RE |
9697 | } |
9698 | ||
c19d1205 ZW |
9699 | /* THUMB CPY instruction (argument parse). */ |
9700 | ||
90e4755a | 9701 | static void |
c19d1205 | 9702 | do_t_cpy (void) |
90e4755a | 9703 | { |
c19d1205 | 9704 | if (inst.size_req == 4) |
90e4755a | 9705 | { |
c19d1205 ZW |
9706 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
9707 | inst.instruction |= inst.operands[0].reg << 8; | |
9708 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 9709 | } |
c19d1205 | 9710 | else |
90e4755a | 9711 | { |
c19d1205 ZW |
9712 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
9713 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
9714 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 9715 | } |
90e4755a RE |
9716 | } |
9717 | ||
90e4755a | 9718 | static void |
25fe350b | 9719 | do_t_cbz (void) |
90e4755a | 9720 | { |
e07e6e58 | 9721 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
9722 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
9723 | inst.instruction |= inst.operands[0].reg; | |
9724 | inst.reloc.pc_rel = 1; | |
9725 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
9726 | } | |
90e4755a | 9727 | |
62b3e311 PB |
9728 | static void |
9729 | do_t_dbg (void) | |
9730 | { | |
9731 | inst.instruction |= inst.operands[0].imm; | |
9732 | } | |
9733 | ||
9734 | static void | |
9735 | do_t_div (void) | |
9736 | { | |
fdfde340 JM |
9737 | unsigned Rd, Rn, Rm; |
9738 | ||
9739 | Rd = inst.operands[0].reg; | |
9740 | Rn = (inst.operands[1].present | |
9741 | ? inst.operands[1].reg : Rd); | |
9742 | Rm = inst.operands[2].reg; | |
9743 | ||
9744 | reject_bad_reg (Rd); | |
9745 | reject_bad_reg (Rn); | |
9746 | reject_bad_reg (Rm); | |
9747 | ||
9748 | inst.instruction |= Rd << 8; | |
9749 | inst.instruction |= Rn << 16; | |
9750 | inst.instruction |= Rm; | |
62b3e311 PB |
9751 | } |
9752 | ||
c19d1205 ZW |
9753 | static void |
9754 | do_t_hint (void) | |
9755 | { | |
9756 | if (unified_syntax && inst.size_req == 4) | |
9757 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9758 | else | |
9759 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9760 | } | |
90e4755a | 9761 | |
c19d1205 ZW |
9762 | static void |
9763 | do_t_it (void) | |
9764 | { | |
9765 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 9766 | |
e07e6e58 NC |
9767 | set_it_insn_type (IT_INSN); |
9768 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
9769 | now_it.cc = cond; | |
e27ec89e PB |
9770 | |
9771 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 9772 | if ((cond & 0x1) == 0x0) |
90e4755a | 9773 | { |
c19d1205 | 9774 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 9775 | |
c19d1205 ZW |
9776 | if ((mask & 0x7) == 0) |
9777 | /* no conversion needed */; | |
9778 | else if ((mask & 0x3) == 0) | |
e27ec89e PB |
9779 | mask ^= 0x8; |
9780 | else if ((mask & 0x1) == 0) | |
9781 | mask ^= 0xC; | |
c19d1205 | 9782 | else |
e27ec89e | 9783 | mask ^= 0xE; |
90e4755a | 9784 | |
e27ec89e PB |
9785 | inst.instruction &= 0xfff0; |
9786 | inst.instruction |= mask; | |
c19d1205 | 9787 | } |
90e4755a | 9788 | |
c19d1205 ZW |
9789 | inst.instruction |= cond << 4; |
9790 | } | |
90e4755a | 9791 | |
3c707909 PB |
9792 | /* Helper function used for both push/pop and ldm/stm. */ |
9793 | static void | |
9794 | encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) | |
9795 | { | |
9796 | bfd_boolean load; | |
9797 | ||
9798 | load = (inst.instruction & (1 << 20)) != 0; | |
9799 | ||
9800 | if (mask & (1 << 13)) | |
9801 | inst.error = _("SP not allowed in register list"); | |
1e5b0379 NC |
9802 | |
9803 | if ((mask & (1 << base)) != 0 | |
9804 | && writeback) | |
9805 | inst.error = _("having the base register in the register list when " | |
9806 | "using write back is UNPREDICTABLE"); | |
9807 | ||
3c707909 PB |
9808 | if (load) |
9809 | { | |
e07e6e58 NC |
9810 | if (mask & (1 << 15)) |
9811 | { | |
9812 | if (mask & (1 << 14)) | |
9813 | inst.error = _("LR and PC should not both be in register list"); | |
9814 | else | |
9815 | set_it_insn_type_last (); | |
9816 | } | |
3c707909 PB |
9817 | } |
9818 | else | |
9819 | { | |
9820 | if (mask & (1 << 15)) | |
9821 | inst.error = _("PC not allowed in register list"); | |
3c707909 PB |
9822 | } |
9823 | ||
9824 | if ((mask & (mask - 1)) == 0) | |
9825 | { | |
9826 | /* Single register transfers implemented as str/ldr. */ | |
9827 | if (writeback) | |
9828 | { | |
9829 | if (inst.instruction & (1 << 23)) | |
9830 | inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ | |
9831 | else | |
9832 | inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ | |
9833 | } | |
9834 | else | |
9835 | { | |
9836 | if (inst.instruction & (1 << 23)) | |
9837 | inst.instruction = 0x00800000; /* ia -> [base] */ | |
9838 | else | |
9839 | inst.instruction = 0x00000c04; /* db -> [base, #-4] */ | |
9840 | } | |
9841 | ||
9842 | inst.instruction |= 0xf8400000; | |
9843 | if (load) | |
9844 | inst.instruction |= 0x00100000; | |
9845 | ||
5f4273c7 | 9846 | mask = ffs (mask) - 1; |
3c707909 PB |
9847 | mask <<= 12; |
9848 | } | |
9849 | else if (writeback) | |
9850 | inst.instruction |= WRITE_BACK; | |
9851 | ||
9852 | inst.instruction |= mask; | |
9853 | inst.instruction |= base << 16; | |
9854 | } | |
9855 | ||
c19d1205 ZW |
9856 | static void |
9857 | do_t_ldmstm (void) | |
9858 | { | |
9859 | /* This really doesn't seem worth it. */ | |
9860 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
9861 | _("expression too complex")); | |
9862 | constraint (inst.operands[1].writeback, | |
9863 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 9864 | |
c19d1205 ZW |
9865 | if (unified_syntax) |
9866 | { | |
3c707909 PB |
9867 | bfd_boolean narrow; |
9868 | unsigned mask; | |
9869 | ||
9870 | narrow = FALSE; | |
c19d1205 ZW |
9871 | /* See if we can use a 16-bit instruction. */ |
9872 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
9873 | && inst.size_req != 4 | |
3c707909 | 9874 | && !(inst.operands[1].imm & ~0xff)) |
90e4755a | 9875 | { |
3c707909 | 9876 | mask = 1 << inst.operands[0].reg; |
90e4755a | 9877 | |
3c707909 PB |
9878 | if (inst.operands[0].reg <= 7 |
9879 | && (inst.instruction == T_MNEM_stmia | |
9880 | ? inst.operands[0].writeback | |
9881 | : (inst.operands[0].writeback | |
9882 | == !(inst.operands[1].imm & mask)))) | |
90e4755a | 9883 | { |
3c707909 PB |
9884 | if (inst.instruction == T_MNEM_stmia |
9885 | && (inst.operands[1].imm & mask) | |
9886 | && (inst.operands[1].imm & (mask - 1))) | |
1e5b0379 | 9887 | as_warn (_("value stored for r%d is UNKNOWN"), |
c19d1205 | 9888 | inst.operands[0].reg); |
3c707909 PB |
9889 | |
9890 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9891 | inst.instruction |= inst.operands[0].reg << 8; | |
9892 | inst.instruction |= inst.operands[1].imm; | |
9893 | narrow = TRUE; | |
90e4755a | 9894 | } |
3c707909 PB |
9895 | else if (inst.operands[0] .reg == REG_SP |
9896 | && inst.operands[0].writeback) | |
90e4755a | 9897 | { |
3c707909 PB |
9898 | inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia |
9899 | ? T_MNEM_push : T_MNEM_pop); | |
9900 | inst.instruction |= inst.operands[1].imm; | |
9901 | narrow = TRUE; | |
90e4755a | 9902 | } |
3c707909 PB |
9903 | } |
9904 | ||
9905 | if (!narrow) | |
9906 | { | |
c19d1205 ZW |
9907 | if (inst.instruction < 0xffff) |
9908 | inst.instruction = THUMB_OP32 (inst.instruction); | |
3c707909 | 9909 | |
5f4273c7 NC |
9910 | encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm, |
9911 | inst.operands[0].writeback); | |
90e4755a RE |
9912 | } |
9913 | } | |
c19d1205 | 9914 | else |
90e4755a | 9915 | { |
c19d1205 ZW |
9916 | constraint (inst.operands[0].reg > 7 |
9917 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
1198ca51 PB |
9918 | constraint (inst.instruction != T_MNEM_ldmia |
9919 | && inst.instruction != T_MNEM_stmia, | |
9920 | _("Thumb-2 instruction only valid in unified syntax")); | |
c19d1205 | 9921 | if (inst.instruction == T_MNEM_stmia) |
f03698e6 | 9922 | { |
c19d1205 ZW |
9923 | if (!inst.operands[0].writeback) |
9924 | as_warn (_("this instruction will write back the base register")); | |
9925 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
9926 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
1e5b0379 | 9927 | as_warn (_("value stored for r%d is UNKNOWN"), |
c19d1205 | 9928 | inst.operands[0].reg); |
f03698e6 | 9929 | } |
c19d1205 | 9930 | else |
90e4755a | 9931 | { |
c19d1205 ZW |
9932 | if (!inst.operands[0].writeback |
9933 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
9934 | as_warn (_("this instruction will write back the base register")); | |
9935 | else if (inst.operands[0].writeback | |
9936 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
9937 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
9938 | } |
9939 | ||
c19d1205 ZW |
9940 | inst.instruction = THUMB_OP16 (inst.instruction); |
9941 | inst.instruction |= inst.operands[0].reg << 8; | |
9942 | inst.instruction |= inst.operands[1].imm; | |
9943 | } | |
9944 | } | |
e28cd48c | 9945 | |
c19d1205 ZW |
9946 | static void |
9947 | do_t_ldrex (void) | |
9948 | { | |
9949 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
9950 | || inst.operands[1].postind || inst.operands[1].writeback | |
9951 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
9952 | || inst.operands[1].negative, | |
01cfc07f | 9953 | BAD_ADDR_MODE); |
e28cd48c | 9954 | |
5be8be5d DG |
9955 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
9956 | ||
c19d1205 ZW |
9957 | inst.instruction |= inst.operands[0].reg << 12; |
9958 | inst.instruction |= inst.operands[1].reg << 16; | |
9959 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
9960 | } | |
e28cd48c | 9961 | |
c19d1205 ZW |
9962 | static void |
9963 | do_t_ldrexd (void) | |
9964 | { | |
9965 | if (!inst.operands[1].present) | |
1cac9012 | 9966 | { |
c19d1205 ZW |
9967 | constraint (inst.operands[0].reg == REG_LR, |
9968 | _("r14 not allowed as first register " | |
9969 | "when second register is omitted")); | |
9970 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 9971 | } |
c19d1205 ZW |
9972 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
9973 | BAD_OVERLAP); | |
b99bd4ef | 9974 | |
c19d1205 ZW |
9975 | inst.instruction |= inst.operands[0].reg << 12; |
9976 | inst.instruction |= inst.operands[1].reg << 8; | |
9977 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
9978 | } |
9979 | ||
9980 | static void | |
c19d1205 | 9981 | do_t_ldst (void) |
b99bd4ef | 9982 | { |
0110f2b8 PB |
9983 | unsigned long opcode; |
9984 | int Rn; | |
9985 | ||
e07e6e58 NC |
9986 | if (inst.operands[0].isreg |
9987 | && !inst.operands[0].preind | |
9988 | && inst.operands[0].reg == REG_PC) | |
9989 | set_it_insn_type_last (); | |
9990 | ||
0110f2b8 | 9991 | opcode = inst.instruction; |
c19d1205 | 9992 | if (unified_syntax) |
b99bd4ef | 9993 | { |
53365c0d PB |
9994 | if (!inst.operands[1].isreg) |
9995 | { | |
9996 | if (opcode <= 0xffff) | |
9997 | inst.instruction = THUMB_OP32 (opcode); | |
9998 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
9999 | return; | |
10000 | } | |
0110f2b8 PB |
10001 | if (inst.operands[1].isreg |
10002 | && !inst.operands[1].writeback | |
c19d1205 ZW |
10003 | && !inst.operands[1].shifted && !inst.operands[1].postind |
10004 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
10005 | && opcode <= 0xffff |
10006 | && inst.size_req != 4) | |
c19d1205 | 10007 | { |
0110f2b8 PB |
10008 | /* Insn may have a 16-bit form. */ |
10009 | Rn = inst.operands[1].reg; | |
10010 | if (inst.operands[1].immisreg) | |
10011 | { | |
10012 | inst.instruction = THUMB_OP16 (opcode); | |
5f4273c7 | 10013 | /* [Rn, Rik] */ |
0110f2b8 PB |
10014 | if (Rn <= 7 && inst.operands[1].imm <= 7) |
10015 | goto op16; | |
5be8be5d DG |
10016 | else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str) |
10017 | reject_bad_reg (inst.operands[1].imm); | |
0110f2b8 PB |
10018 | } |
10019 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
10020 | && opcode != T_MNEM_ldrsb) | |
10021 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
10022 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
10023 | { | |
10024 | /* [Rn, #const] */ | |
10025 | if (Rn > 7) | |
10026 | { | |
10027 | if (Rn == REG_PC) | |
10028 | { | |
10029 | if (inst.reloc.pc_rel) | |
10030 | opcode = T_MNEM_ldr_pc2; | |
10031 | else | |
10032 | opcode = T_MNEM_ldr_pc; | |
10033 | } | |
10034 | else | |
10035 | { | |
10036 | if (opcode == T_MNEM_ldr) | |
10037 | opcode = T_MNEM_ldr_sp; | |
10038 | else | |
10039 | opcode = T_MNEM_str_sp; | |
10040 | } | |
10041 | inst.instruction = inst.operands[0].reg << 8; | |
10042 | } | |
10043 | else | |
10044 | { | |
10045 | inst.instruction = inst.operands[0].reg; | |
10046 | inst.instruction |= inst.operands[1].reg << 3; | |
10047 | } | |
10048 | inst.instruction |= THUMB_OP16 (opcode); | |
10049 | if (inst.size_req == 2) | |
10050 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10051 | else | |
10052 | inst.relax = opcode; | |
10053 | return; | |
10054 | } | |
c19d1205 | 10055 | } |
0110f2b8 | 10056 | /* Definitely a 32-bit variant. */ |
5be8be5d DG |
10057 | |
10058 | /* Do some validations regarding addressing modes. */ | |
10059 | if (inst.operands[1].immisreg && opcode != T_MNEM_ldr | |
10060 | && opcode != T_MNEM_str) | |
10061 | reject_bad_reg (inst.operands[1].imm); | |
10062 | ||
0110f2b8 | 10063 | inst.instruction = THUMB_OP32 (opcode); |
c19d1205 ZW |
10064 | inst.instruction |= inst.operands[0].reg << 12; |
10065 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
b99bd4ef NC |
10066 | return; |
10067 | } | |
10068 | ||
c19d1205 ZW |
10069 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
10070 | ||
10071 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 10072 | { |
c19d1205 ZW |
10073 | /* Only [Rn,Rm] is acceptable. */ |
10074 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
10075 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
10076 | || inst.operands[1].postind || inst.operands[1].shifted | |
10077 | || inst.operands[1].negative, | |
10078 | _("Thumb does not support this addressing mode")); | |
10079 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10080 | goto op16; | |
b99bd4ef | 10081 | } |
5f4273c7 | 10082 | |
c19d1205 ZW |
10083 | inst.instruction = THUMB_OP16 (inst.instruction); |
10084 | if (!inst.operands[1].isreg) | |
10085 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
10086 | return; | |
b99bd4ef | 10087 | |
c19d1205 ZW |
10088 | constraint (!inst.operands[1].preind |
10089 | || inst.operands[1].shifted | |
10090 | || inst.operands[1].writeback, | |
10091 | _("Thumb does not support this addressing mode")); | |
10092 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 10093 | { |
c19d1205 ZW |
10094 | constraint (inst.instruction & 0x0600, |
10095 | _("byte or halfword not valid for base register")); | |
10096 | constraint (inst.operands[1].reg == REG_PC | |
10097 | && !(inst.instruction & THUMB_LOAD_BIT), | |
10098 | _("r15 based store not allowed")); | |
10099 | constraint (inst.operands[1].immisreg, | |
10100 | _("invalid base register for register offset")); | |
b99bd4ef | 10101 | |
c19d1205 ZW |
10102 | if (inst.operands[1].reg == REG_PC) |
10103 | inst.instruction = T_OPCODE_LDR_PC; | |
10104 | else if (inst.instruction & THUMB_LOAD_BIT) | |
10105 | inst.instruction = T_OPCODE_LDR_SP; | |
10106 | else | |
10107 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 10108 | |
c19d1205 ZW |
10109 | inst.instruction |= inst.operands[0].reg << 8; |
10110 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10111 | return; | |
10112 | } | |
90e4755a | 10113 | |
c19d1205 ZW |
10114 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
10115 | if (!inst.operands[1].immisreg) | |
10116 | { | |
10117 | /* Immediate offset. */ | |
10118 | inst.instruction |= inst.operands[0].reg; | |
10119 | inst.instruction |= inst.operands[1].reg << 3; | |
10120 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10121 | return; | |
10122 | } | |
90e4755a | 10123 | |
c19d1205 ZW |
10124 | /* Register offset. */ |
10125 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
10126 | constraint (inst.operands[1].negative, | |
10127 | _("Thumb does not support this addressing mode")); | |
90e4755a | 10128 | |
c19d1205 ZW |
10129 | op16: |
10130 | switch (inst.instruction) | |
10131 | { | |
10132 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
10133 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
10134 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
10135 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
10136 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
10137 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
10138 | case 0x5600 /* ldrsb */: | |
10139 | case 0x5e00 /* ldrsh */: break; | |
10140 | default: abort (); | |
10141 | } | |
90e4755a | 10142 | |
c19d1205 ZW |
10143 | inst.instruction |= inst.operands[0].reg; |
10144 | inst.instruction |= inst.operands[1].reg << 3; | |
10145 | inst.instruction |= inst.operands[1].imm << 6; | |
10146 | } | |
90e4755a | 10147 | |
c19d1205 ZW |
10148 | static void |
10149 | do_t_ldstd (void) | |
10150 | { | |
10151 | if (!inst.operands[1].present) | |
b99bd4ef | 10152 | { |
c19d1205 ZW |
10153 | inst.operands[1].reg = inst.operands[0].reg + 1; |
10154 | constraint (inst.operands[0].reg == REG_LR, | |
10155 | _("r14 not allowed here")); | |
b99bd4ef | 10156 | } |
c19d1205 ZW |
10157 | inst.instruction |= inst.operands[0].reg << 12; |
10158 | inst.instruction |= inst.operands[1].reg << 8; | |
10159 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
b99bd4ef NC |
10160 | } |
10161 | ||
c19d1205 ZW |
10162 | static void |
10163 | do_t_ldstt (void) | |
10164 | { | |
10165 | inst.instruction |= inst.operands[0].reg << 12; | |
10166 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
10167 | } | |
a737bd4d | 10168 | |
b99bd4ef | 10169 | static void |
c19d1205 | 10170 | do_t_mla (void) |
b99bd4ef | 10171 | { |
fdfde340 | 10172 | unsigned Rd, Rn, Rm, Ra; |
c921be7d | 10173 | |
fdfde340 JM |
10174 | Rd = inst.operands[0].reg; |
10175 | Rn = inst.operands[1].reg; | |
10176 | Rm = inst.operands[2].reg; | |
10177 | Ra = inst.operands[3].reg; | |
10178 | ||
10179 | reject_bad_reg (Rd); | |
10180 | reject_bad_reg (Rn); | |
10181 | reject_bad_reg (Rm); | |
10182 | reject_bad_reg (Ra); | |
10183 | ||
10184 | inst.instruction |= Rd << 8; | |
10185 | inst.instruction |= Rn << 16; | |
10186 | inst.instruction |= Rm; | |
10187 | inst.instruction |= Ra << 12; | |
c19d1205 | 10188 | } |
b99bd4ef | 10189 | |
c19d1205 ZW |
10190 | static void |
10191 | do_t_mlal (void) | |
10192 | { | |
fdfde340 JM |
10193 | unsigned RdLo, RdHi, Rn, Rm; |
10194 | ||
10195 | RdLo = inst.operands[0].reg; | |
10196 | RdHi = inst.operands[1].reg; | |
10197 | Rn = inst.operands[2].reg; | |
10198 | Rm = inst.operands[3].reg; | |
10199 | ||
10200 | reject_bad_reg (RdLo); | |
10201 | reject_bad_reg (RdHi); | |
10202 | reject_bad_reg (Rn); | |
10203 | reject_bad_reg (Rm); | |
10204 | ||
10205 | inst.instruction |= RdLo << 12; | |
10206 | inst.instruction |= RdHi << 8; | |
10207 | inst.instruction |= Rn << 16; | |
10208 | inst.instruction |= Rm; | |
c19d1205 | 10209 | } |
b99bd4ef | 10210 | |
c19d1205 ZW |
10211 | static void |
10212 | do_t_mov_cmp (void) | |
10213 | { | |
fdfde340 JM |
10214 | unsigned Rn, Rm; |
10215 | ||
10216 | Rn = inst.operands[0].reg; | |
10217 | Rm = inst.operands[1].reg; | |
10218 | ||
e07e6e58 NC |
10219 | if (Rn == REG_PC) |
10220 | set_it_insn_type_last (); | |
10221 | ||
c19d1205 | 10222 | if (unified_syntax) |
b99bd4ef | 10223 | { |
c19d1205 ZW |
10224 | int r0off = (inst.instruction == T_MNEM_mov |
10225 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 10226 | unsigned long opcode; |
3d388997 PB |
10227 | bfd_boolean narrow; |
10228 | bfd_boolean low_regs; | |
10229 | ||
fdfde340 | 10230 | low_regs = (Rn <= 7 && Rm <= 7); |
0110f2b8 | 10231 | opcode = inst.instruction; |
e07e6e58 | 10232 | if (in_it_block ()) |
0110f2b8 | 10233 | narrow = opcode != T_MNEM_movs; |
3d388997 | 10234 | else |
0110f2b8 | 10235 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
10236 | if (inst.size_req == 4 |
10237 | || inst.operands[1].shifted) | |
10238 | narrow = FALSE; | |
10239 | ||
efd81785 PB |
10240 | /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ |
10241 | if (opcode == T_MNEM_movs && inst.operands[1].isreg | |
10242 | && !inst.operands[1].shifted | |
fdfde340 JM |
10243 | && Rn == REG_PC |
10244 | && Rm == REG_LR) | |
efd81785 PB |
10245 | { |
10246 | inst.instruction = T2_SUBS_PC_LR; | |
10247 | return; | |
10248 | } | |
10249 | ||
fdfde340 JM |
10250 | if (opcode == T_MNEM_cmp) |
10251 | { | |
10252 | constraint (Rn == REG_PC, BAD_PC); | |
94206790 MM |
10253 | if (narrow) |
10254 | { | |
10255 | /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, | |
10256 | but valid. */ | |
10257 | warn_deprecated_sp (Rm); | |
10258 | /* R15 was documented as a valid choice for Rm in ARMv6, | |
10259 | but as UNPREDICTABLE in ARMv7. ARM's proprietary | |
10260 | tools reject R15, so we do too. */ | |
10261 | constraint (Rm == REG_PC, BAD_PC); | |
10262 | } | |
10263 | else | |
10264 | reject_bad_reg (Rm); | |
fdfde340 JM |
10265 | } |
10266 | else if (opcode == T_MNEM_mov | |
10267 | || opcode == T_MNEM_movs) | |
10268 | { | |
10269 | if (inst.operands[1].isreg) | |
10270 | { | |
10271 | if (opcode == T_MNEM_movs) | |
10272 | { | |
10273 | reject_bad_reg (Rn); | |
10274 | reject_bad_reg (Rm); | |
10275 | } | |
76fa04a4 MGD |
10276 | else if (narrow) |
10277 | { | |
10278 | /* This is mov.n. */ | |
10279 | if ((Rn == REG_SP || Rn == REG_PC) | |
10280 | && (Rm == REG_SP || Rm == REG_PC)) | |
10281 | { | |
10282 | as_warn (_("Use of r%u as a source register is " | |
10283 | "deprecated when r%u is the destination " | |
10284 | "register."), Rm, Rn); | |
10285 | } | |
10286 | } | |
10287 | else | |
10288 | { | |
10289 | /* This is mov.w. */ | |
10290 | constraint (Rn == REG_PC, BAD_PC); | |
10291 | constraint (Rm == REG_PC, BAD_PC); | |
10292 | constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); | |
10293 | } | |
fdfde340 JM |
10294 | } |
10295 | else | |
10296 | reject_bad_reg (Rn); | |
10297 | } | |
10298 | ||
c19d1205 ZW |
10299 | if (!inst.operands[1].isreg) |
10300 | { | |
0110f2b8 | 10301 | /* Immediate operand. */ |
e07e6e58 | 10302 | if (!in_it_block () && opcode == T_MNEM_mov) |
0110f2b8 PB |
10303 | narrow = 0; |
10304 | if (low_regs && narrow) | |
10305 | { | |
10306 | inst.instruction = THUMB_OP16 (opcode); | |
fdfde340 | 10307 | inst.instruction |= Rn << 8; |
0110f2b8 PB |
10308 | if (inst.size_req == 2) |
10309 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
10310 | else | |
10311 | inst.relax = opcode; | |
10312 | } | |
10313 | else | |
10314 | { | |
10315 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10316 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 10317 | inst.instruction |= Rn << r0off; |
0110f2b8 PB |
10318 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
10319 | } | |
c19d1205 | 10320 | } |
728ca7c9 PB |
10321 | else if (inst.operands[1].shifted && inst.operands[1].immisreg |
10322 | && (inst.instruction == T_MNEM_mov | |
10323 | || inst.instruction == T_MNEM_movs)) | |
10324 | { | |
10325 | /* Register shifts are encoded as separate shift instructions. */ | |
10326 | bfd_boolean flags = (inst.instruction == T_MNEM_movs); | |
10327 | ||
e07e6e58 | 10328 | if (in_it_block ()) |
728ca7c9 PB |
10329 | narrow = !flags; |
10330 | else | |
10331 | narrow = flags; | |
10332 | ||
10333 | if (inst.size_req == 4) | |
10334 | narrow = FALSE; | |
10335 | ||
10336 | if (!low_regs || inst.operands[1].imm > 7) | |
10337 | narrow = FALSE; | |
10338 | ||
fdfde340 | 10339 | if (Rn != Rm) |
728ca7c9 PB |
10340 | narrow = FALSE; |
10341 | ||
10342 | switch (inst.operands[1].shift_kind) | |
10343 | { | |
10344 | case SHIFT_LSL: | |
10345 | opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); | |
10346 | break; | |
10347 | case SHIFT_ASR: | |
10348 | opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); | |
10349 | break; | |
10350 | case SHIFT_LSR: | |
10351 | opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); | |
10352 | break; | |
10353 | case SHIFT_ROR: | |
10354 | opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); | |
10355 | break; | |
10356 | default: | |
5f4273c7 | 10357 | abort (); |
728ca7c9 PB |
10358 | } |
10359 | ||
10360 | inst.instruction = opcode; | |
10361 | if (narrow) | |
10362 | { | |
fdfde340 | 10363 | inst.instruction |= Rn; |
728ca7c9 PB |
10364 | inst.instruction |= inst.operands[1].imm << 3; |
10365 | } | |
10366 | else | |
10367 | { | |
10368 | if (flags) | |
10369 | inst.instruction |= CONDS_BIT; | |
10370 | ||
fdfde340 JM |
10371 | inst.instruction |= Rn << 8; |
10372 | inst.instruction |= Rm << 16; | |
728ca7c9 PB |
10373 | inst.instruction |= inst.operands[1].imm; |
10374 | } | |
10375 | } | |
3d388997 | 10376 | else if (!narrow) |
c19d1205 | 10377 | { |
728ca7c9 PB |
10378 | /* Some mov with immediate shift have narrow variants. |
10379 | Register shifts are handled above. */ | |
10380 | if (low_regs && inst.operands[1].shifted | |
10381 | && (inst.instruction == T_MNEM_mov | |
10382 | || inst.instruction == T_MNEM_movs)) | |
10383 | { | |
e07e6e58 | 10384 | if (in_it_block ()) |
728ca7c9 PB |
10385 | narrow = (inst.instruction == T_MNEM_mov); |
10386 | else | |
10387 | narrow = (inst.instruction == T_MNEM_movs); | |
10388 | } | |
10389 | ||
10390 | if (narrow) | |
10391 | { | |
10392 | switch (inst.operands[1].shift_kind) | |
10393 | { | |
10394 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
10395 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
10396 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
10397 | default: narrow = FALSE; break; | |
10398 | } | |
10399 | } | |
10400 | ||
10401 | if (narrow) | |
10402 | { | |
fdfde340 JM |
10403 | inst.instruction |= Rn; |
10404 | inst.instruction |= Rm << 3; | |
728ca7c9 PB |
10405 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
10406 | } | |
10407 | else | |
10408 | { | |
10409 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 10410 | inst.instruction |= Rn << r0off; |
728ca7c9 PB |
10411 | encode_thumb32_shifted_operand (1); |
10412 | } | |
c19d1205 ZW |
10413 | } |
10414 | else | |
10415 | switch (inst.instruction) | |
10416 | { | |
10417 | case T_MNEM_mov: | |
10418 | inst.instruction = T_OPCODE_MOV_HR; | |
fdfde340 JM |
10419 | inst.instruction |= (Rn & 0x8) << 4; |
10420 | inst.instruction |= (Rn & 0x7); | |
10421 | inst.instruction |= Rm << 3; | |
c19d1205 | 10422 | break; |
b99bd4ef | 10423 | |
c19d1205 ZW |
10424 | case T_MNEM_movs: |
10425 | /* We know we have low registers at this point. | |
941a8a52 MGD |
10426 | Generate LSLS Rd, Rs, #0. */ |
10427 | inst.instruction = T_OPCODE_LSL_I; | |
fdfde340 JM |
10428 | inst.instruction |= Rn; |
10429 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10430 | break; |
10431 | ||
10432 | case T_MNEM_cmp: | |
3d388997 | 10433 | if (low_regs) |
c19d1205 ZW |
10434 | { |
10435 | inst.instruction = T_OPCODE_CMP_LR; | |
fdfde340 JM |
10436 | inst.instruction |= Rn; |
10437 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10438 | } |
10439 | else | |
10440 | { | |
10441 | inst.instruction = T_OPCODE_CMP_HR; | |
fdfde340 JM |
10442 | inst.instruction |= (Rn & 0x8) << 4; |
10443 | inst.instruction |= (Rn & 0x7); | |
10444 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10445 | } |
10446 | break; | |
10447 | } | |
b99bd4ef NC |
10448 | return; |
10449 | } | |
10450 | ||
c19d1205 | 10451 | inst.instruction = THUMB_OP16 (inst.instruction); |
539d4391 NC |
10452 | |
10453 | /* PR 10443: Do not silently ignore shifted operands. */ | |
10454 | constraint (inst.operands[1].shifted, | |
10455 | _("shifts in CMP/MOV instructions are only supported in unified syntax")); | |
10456 | ||
c19d1205 | 10457 | if (inst.operands[1].isreg) |
b99bd4ef | 10458 | { |
fdfde340 | 10459 | if (Rn < 8 && Rm < 8) |
b99bd4ef | 10460 | { |
c19d1205 ZW |
10461 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
10462 | since a MOV instruction produces unpredictable results. */ | |
10463 | if (inst.instruction == T_OPCODE_MOV_I8) | |
10464 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 10465 | else |
c19d1205 | 10466 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 10467 | |
fdfde340 JM |
10468 | inst.instruction |= Rn; |
10469 | inst.instruction |= Rm << 3; | |
b99bd4ef NC |
10470 | } |
10471 | else | |
10472 | { | |
c19d1205 ZW |
10473 | if (inst.instruction == T_OPCODE_MOV_I8) |
10474 | inst.instruction = T_OPCODE_MOV_HR; | |
10475 | else | |
10476 | inst.instruction = T_OPCODE_CMP_HR; | |
10477 | do_t_cpy (); | |
b99bd4ef NC |
10478 | } |
10479 | } | |
c19d1205 | 10480 | else |
b99bd4ef | 10481 | { |
fdfde340 | 10482 | constraint (Rn > 7, |
c19d1205 | 10483 | _("only lo regs allowed with immediate")); |
fdfde340 | 10484 | inst.instruction |= Rn << 8; |
c19d1205 ZW |
10485 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; |
10486 | } | |
10487 | } | |
b99bd4ef | 10488 | |
c19d1205 ZW |
10489 | static void |
10490 | do_t_mov16 (void) | |
10491 | { | |
fdfde340 | 10492 | unsigned Rd; |
b6895b4f PB |
10493 | bfd_vma imm; |
10494 | bfd_boolean top; | |
10495 | ||
10496 | top = (inst.instruction & 0x00800000) != 0; | |
10497 | if (inst.reloc.type == BFD_RELOC_ARM_MOVW) | |
10498 | { | |
10499 | constraint (top, _(":lower16: not allowed this instruction")); | |
10500 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; | |
10501 | } | |
10502 | else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) | |
10503 | { | |
10504 | constraint (!top, _(":upper16: not allowed this instruction")); | |
10505 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; | |
10506 | } | |
10507 | ||
fdfde340 JM |
10508 | Rd = inst.operands[0].reg; |
10509 | reject_bad_reg (Rd); | |
10510 | ||
10511 | inst.instruction |= Rd << 8; | |
b6895b4f PB |
10512 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
10513 | { | |
10514 | imm = inst.reloc.exp.X_add_number; | |
10515 | inst.instruction |= (imm & 0xf000) << 4; | |
10516 | inst.instruction |= (imm & 0x0800) << 15; | |
10517 | inst.instruction |= (imm & 0x0700) << 4; | |
10518 | inst.instruction |= (imm & 0x00ff); | |
10519 | } | |
c19d1205 | 10520 | } |
b99bd4ef | 10521 | |
c19d1205 ZW |
10522 | static void |
10523 | do_t_mvn_tst (void) | |
10524 | { | |
fdfde340 | 10525 | unsigned Rn, Rm; |
c921be7d | 10526 | |
fdfde340 JM |
10527 | Rn = inst.operands[0].reg; |
10528 | Rm = inst.operands[1].reg; | |
10529 | ||
10530 | if (inst.instruction == T_MNEM_cmp | |
10531 | || inst.instruction == T_MNEM_cmn) | |
10532 | constraint (Rn == REG_PC, BAD_PC); | |
10533 | else | |
10534 | reject_bad_reg (Rn); | |
10535 | reject_bad_reg (Rm); | |
10536 | ||
c19d1205 ZW |
10537 | if (unified_syntax) |
10538 | { | |
10539 | int r0off = (inst.instruction == T_MNEM_mvn | |
10540 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
10541 | bfd_boolean narrow; |
10542 | ||
10543 | if (inst.size_req == 4 | |
10544 | || inst.instruction > 0xffff | |
10545 | || inst.operands[1].shifted | |
fdfde340 | 10546 | || Rn > 7 || Rm > 7) |
3d388997 PB |
10547 | narrow = FALSE; |
10548 | else if (inst.instruction == T_MNEM_cmn) | |
10549 | narrow = TRUE; | |
10550 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 10551 | narrow = !in_it_block (); |
3d388997 | 10552 | else |
e07e6e58 | 10553 | narrow = in_it_block (); |
3d388997 | 10554 | |
c19d1205 | 10555 | if (!inst.operands[1].isreg) |
b99bd4ef | 10556 | { |
c19d1205 ZW |
10557 | /* For an immediate, we always generate a 32-bit opcode; |
10558 | section relaxation will shrink it later if possible. */ | |
10559 | if (inst.instruction < 0xffff) | |
10560 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10561 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 10562 | inst.instruction |= Rn << r0off; |
c19d1205 | 10563 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 10564 | } |
c19d1205 | 10565 | else |
b99bd4ef | 10566 | { |
c19d1205 | 10567 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 10568 | if (narrow) |
b99bd4ef | 10569 | { |
c19d1205 | 10570 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
10571 | inst.instruction |= Rn; |
10572 | inst.instruction |= Rm << 3; | |
b99bd4ef | 10573 | } |
c19d1205 | 10574 | else |
b99bd4ef | 10575 | { |
c19d1205 ZW |
10576 | constraint (inst.operands[1].shifted |
10577 | && inst.operands[1].immisreg, | |
10578 | _("shift must be constant")); | |
10579 | if (inst.instruction < 0xffff) | |
10580 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 10581 | inst.instruction |= Rn << r0off; |
c19d1205 | 10582 | encode_thumb32_shifted_operand (1); |
b99bd4ef | 10583 | } |
b99bd4ef NC |
10584 | } |
10585 | } | |
10586 | else | |
10587 | { | |
c19d1205 ZW |
10588 | constraint (inst.instruction > 0xffff |
10589 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
10590 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
10591 | _("unshifted register required")); | |
fdfde340 | 10592 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 10593 | BAD_HIREG); |
b99bd4ef | 10594 | |
c19d1205 | 10595 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
10596 | inst.instruction |= Rn; |
10597 | inst.instruction |= Rm << 3; | |
b99bd4ef | 10598 | } |
b99bd4ef NC |
10599 | } |
10600 | ||
b05fe5cf | 10601 | static void |
c19d1205 | 10602 | do_t_mrs (void) |
b05fe5cf | 10603 | { |
fdfde340 | 10604 | unsigned Rd; |
62b3e311 | 10605 | int flags; |
037e8744 JB |
10606 | |
10607 | if (do_vfp_nsyn_mrs () == SUCCESS) | |
10608 | return; | |
10609 | ||
62b3e311 PB |
10610 | flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
10611 | if (flags == 0) | |
10612 | { | |
7e806470 | 10613 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m), |
62b3e311 PB |
10614 | _("selected processor does not support " |
10615 | "requested special purpose register")); | |
10616 | } | |
10617 | else | |
10618 | { | |
10619 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), | |
10620 | _("selected processor does not support " | |
44bf2362 | 10621 | "requested special purpose register")); |
62b3e311 PB |
10622 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ |
10623 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
10624 | _("'CPSR' or 'SPSR' expected")); | |
10625 | } | |
5f4273c7 | 10626 | |
fdfde340 JM |
10627 | Rd = inst.operands[0].reg; |
10628 | reject_bad_reg (Rd); | |
10629 | ||
10630 | inst.instruction |= Rd << 8; | |
62b3e311 PB |
10631 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
10632 | inst.instruction |= inst.operands[1].imm & 0xff; | |
c19d1205 | 10633 | } |
b05fe5cf | 10634 | |
c19d1205 ZW |
10635 | static void |
10636 | do_t_msr (void) | |
10637 | { | |
62b3e311 | 10638 | int flags; |
fdfde340 | 10639 | unsigned Rn; |
62b3e311 | 10640 | |
037e8744 JB |
10641 | if (do_vfp_nsyn_msr () == SUCCESS) |
10642 | return; | |
10643 | ||
c19d1205 ZW |
10644 | constraint (!inst.operands[1].isreg, |
10645 | _("Thumb encoding does not support an immediate here")); | |
62b3e311 PB |
10646 | flags = inst.operands[0].imm; |
10647 | if (flags & ~0xff) | |
10648 | { | |
10649 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), | |
10650 | _("selected processor does not support " | |
10651 | "requested special purpose register")); | |
10652 | } | |
10653 | else | |
10654 | { | |
7e806470 | 10655 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m), |
62b3e311 PB |
10656 | _("selected processor does not support " |
10657 | "requested special purpose register")); | |
10658 | flags |= PSR_f; | |
10659 | } | |
c921be7d | 10660 | |
fdfde340 JM |
10661 | Rn = inst.operands[1].reg; |
10662 | reject_bad_reg (Rn); | |
10663 | ||
62b3e311 PB |
10664 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
10665 | inst.instruction |= (flags & ~SPSR_BIT) >> 8; | |
10666 | inst.instruction |= (flags & 0xff); | |
fdfde340 | 10667 | inst.instruction |= Rn << 16; |
c19d1205 | 10668 | } |
b05fe5cf | 10669 | |
c19d1205 ZW |
10670 | static void |
10671 | do_t_mul (void) | |
10672 | { | |
17828f45 | 10673 | bfd_boolean narrow; |
fdfde340 | 10674 | unsigned Rd, Rn, Rm; |
17828f45 | 10675 | |
c19d1205 ZW |
10676 | if (!inst.operands[2].present) |
10677 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 10678 | |
fdfde340 JM |
10679 | Rd = inst.operands[0].reg; |
10680 | Rn = inst.operands[1].reg; | |
10681 | Rm = inst.operands[2].reg; | |
10682 | ||
17828f45 | 10683 | if (unified_syntax) |
b05fe5cf | 10684 | { |
17828f45 | 10685 | if (inst.size_req == 4 |
fdfde340 JM |
10686 | || (Rd != Rn |
10687 | && Rd != Rm) | |
10688 | || Rn > 7 | |
10689 | || Rm > 7) | |
17828f45 JM |
10690 | narrow = FALSE; |
10691 | else if (inst.instruction == T_MNEM_muls) | |
e07e6e58 | 10692 | narrow = !in_it_block (); |
17828f45 | 10693 | else |
e07e6e58 | 10694 | narrow = in_it_block (); |
b05fe5cf | 10695 | } |
c19d1205 | 10696 | else |
b05fe5cf | 10697 | { |
17828f45 | 10698 | constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); |
fdfde340 | 10699 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 10700 | BAD_HIREG); |
17828f45 JM |
10701 | narrow = TRUE; |
10702 | } | |
b05fe5cf | 10703 | |
17828f45 JM |
10704 | if (narrow) |
10705 | { | |
10706 | /* 16-bit MULS/Conditional MUL. */ | |
c19d1205 | 10707 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 | 10708 | inst.instruction |= Rd; |
b05fe5cf | 10709 | |
fdfde340 JM |
10710 | if (Rd == Rn) |
10711 | inst.instruction |= Rm << 3; | |
10712 | else if (Rd == Rm) | |
10713 | inst.instruction |= Rn << 3; | |
c19d1205 ZW |
10714 | else |
10715 | constraint (1, _("dest must overlap one source register")); | |
10716 | } | |
17828f45 JM |
10717 | else |
10718 | { | |
e07e6e58 NC |
10719 | constraint (inst.instruction != T_MNEM_mul, |
10720 | _("Thumb-2 MUL must not set flags")); | |
17828f45 JM |
10721 | /* 32-bit MUL. */ |
10722 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
10723 | inst.instruction |= Rd << 8; |
10724 | inst.instruction |= Rn << 16; | |
10725 | inst.instruction |= Rm << 0; | |
10726 | ||
10727 | reject_bad_reg (Rd); | |
10728 | reject_bad_reg (Rn); | |
10729 | reject_bad_reg (Rm); | |
17828f45 | 10730 | } |
c19d1205 | 10731 | } |
b05fe5cf | 10732 | |
c19d1205 ZW |
10733 | static void |
10734 | do_t_mull (void) | |
10735 | { | |
fdfde340 | 10736 | unsigned RdLo, RdHi, Rn, Rm; |
b05fe5cf | 10737 | |
fdfde340 JM |
10738 | RdLo = inst.operands[0].reg; |
10739 | RdHi = inst.operands[1].reg; | |
10740 | Rn = inst.operands[2].reg; | |
10741 | Rm = inst.operands[3].reg; | |
10742 | ||
10743 | reject_bad_reg (RdLo); | |
10744 | reject_bad_reg (RdHi); | |
10745 | reject_bad_reg (Rn); | |
10746 | reject_bad_reg (Rm); | |
10747 | ||
10748 | inst.instruction |= RdLo << 12; | |
10749 | inst.instruction |= RdHi << 8; | |
10750 | inst.instruction |= Rn << 16; | |
10751 | inst.instruction |= Rm; | |
10752 | ||
10753 | if (RdLo == RdHi) | |
c19d1205 ZW |
10754 | as_tsktsk (_("rdhi and rdlo must be different")); |
10755 | } | |
b05fe5cf | 10756 | |
c19d1205 ZW |
10757 | static void |
10758 | do_t_nop (void) | |
10759 | { | |
e07e6e58 NC |
10760 | set_it_insn_type (NEUTRAL_IT_INSN); |
10761 | ||
c19d1205 ZW |
10762 | if (unified_syntax) |
10763 | { | |
10764 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 10765 | { |
c19d1205 ZW |
10766 | inst.instruction = THUMB_OP32 (inst.instruction); |
10767 | inst.instruction |= inst.operands[0].imm; | |
10768 | } | |
10769 | else | |
10770 | { | |
bc2d1808 NC |
10771 | /* PR9722: Check for Thumb2 availability before |
10772 | generating a thumb2 nop instruction. */ | |
afa62d5e | 10773 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
bc2d1808 NC |
10774 | { |
10775 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10776 | inst.instruction |= inst.operands[0].imm << 4; | |
10777 | } | |
10778 | else | |
10779 | inst.instruction = 0x46c0; | |
c19d1205 ZW |
10780 | } |
10781 | } | |
10782 | else | |
10783 | { | |
10784 | constraint (inst.operands[0].present, | |
10785 | _("Thumb does not support NOP with hints")); | |
10786 | inst.instruction = 0x46c0; | |
10787 | } | |
10788 | } | |
b05fe5cf | 10789 | |
c19d1205 ZW |
10790 | static void |
10791 | do_t_neg (void) | |
10792 | { | |
10793 | if (unified_syntax) | |
10794 | { | |
3d388997 PB |
10795 | bfd_boolean narrow; |
10796 | ||
10797 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 10798 | narrow = !in_it_block (); |
3d388997 | 10799 | else |
e07e6e58 | 10800 | narrow = in_it_block (); |
3d388997 PB |
10801 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
10802 | narrow = FALSE; | |
10803 | if (inst.size_req == 4) | |
10804 | narrow = FALSE; | |
10805 | ||
10806 | if (!narrow) | |
c19d1205 ZW |
10807 | { |
10808 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10809 | inst.instruction |= inst.operands[0].reg << 8; | |
10810 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
10811 | } |
10812 | else | |
10813 | { | |
c19d1205 ZW |
10814 | inst.instruction = THUMB_OP16 (inst.instruction); |
10815 | inst.instruction |= inst.operands[0].reg; | |
10816 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
10817 | } |
10818 | } | |
10819 | else | |
10820 | { | |
c19d1205 ZW |
10821 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
10822 | BAD_HIREG); | |
10823 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
10824 | ||
10825 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10826 | inst.instruction |= inst.operands[0].reg; | |
10827 | inst.instruction |= inst.operands[1].reg << 3; | |
10828 | } | |
10829 | } | |
10830 | ||
1c444d06 JM |
10831 | static void |
10832 | do_t_orn (void) | |
10833 | { | |
10834 | unsigned Rd, Rn; | |
10835 | ||
10836 | Rd = inst.operands[0].reg; | |
10837 | Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; | |
10838 | ||
fdfde340 JM |
10839 | reject_bad_reg (Rd); |
10840 | /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ | |
10841 | reject_bad_reg (Rn); | |
10842 | ||
1c444d06 JM |
10843 | inst.instruction |= Rd << 8; |
10844 | inst.instruction |= Rn << 16; | |
10845 | ||
10846 | if (!inst.operands[2].isreg) | |
10847 | { | |
10848 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
10849 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10850 | } | |
10851 | else | |
10852 | { | |
10853 | unsigned Rm; | |
10854 | ||
10855 | Rm = inst.operands[2].reg; | |
fdfde340 | 10856 | reject_bad_reg (Rm); |
1c444d06 JM |
10857 | |
10858 | constraint (inst.operands[2].shifted | |
10859 | && inst.operands[2].immisreg, | |
10860 | _("shift must be constant")); | |
10861 | encode_thumb32_shifted_operand (2); | |
10862 | } | |
10863 | } | |
10864 | ||
c19d1205 ZW |
10865 | static void |
10866 | do_t_pkhbt (void) | |
10867 | { | |
fdfde340 JM |
10868 | unsigned Rd, Rn, Rm; |
10869 | ||
10870 | Rd = inst.operands[0].reg; | |
10871 | Rn = inst.operands[1].reg; | |
10872 | Rm = inst.operands[2].reg; | |
10873 | ||
10874 | reject_bad_reg (Rd); | |
10875 | reject_bad_reg (Rn); | |
10876 | reject_bad_reg (Rm); | |
10877 | ||
10878 | inst.instruction |= Rd << 8; | |
10879 | inst.instruction |= Rn << 16; | |
10880 | inst.instruction |= Rm; | |
c19d1205 ZW |
10881 | if (inst.operands[3].present) |
10882 | { | |
10883 | unsigned int val = inst.reloc.exp.X_add_number; | |
10884 | constraint (inst.reloc.exp.X_op != O_constant, | |
10885 | _("expression too complex")); | |
10886 | inst.instruction |= (val & 0x1c) << 10; | |
10887 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 10888 | } |
c19d1205 | 10889 | } |
b05fe5cf | 10890 | |
c19d1205 ZW |
10891 | static void |
10892 | do_t_pkhtb (void) | |
10893 | { | |
10894 | if (!inst.operands[3].present) | |
1ef52f49 NC |
10895 | { |
10896 | unsigned Rtmp; | |
10897 | ||
10898 | inst.instruction &= ~0x00000020; | |
10899 | ||
10900 | /* PR 10168. Swap the Rm and Rn registers. */ | |
10901 | Rtmp = inst.operands[1].reg; | |
10902 | inst.operands[1].reg = inst.operands[2].reg; | |
10903 | inst.operands[2].reg = Rtmp; | |
10904 | } | |
c19d1205 | 10905 | do_t_pkhbt (); |
b05fe5cf ZW |
10906 | } |
10907 | ||
c19d1205 ZW |
10908 | static void |
10909 | do_t_pld (void) | |
10910 | { | |
fdfde340 JM |
10911 | if (inst.operands[0].immisreg) |
10912 | reject_bad_reg (inst.operands[0].imm); | |
10913 | ||
c19d1205 ZW |
10914 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); |
10915 | } | |
b05fe5cf | 10916 | |
c19d1205 ZW |
10917 | static void |
10918 | do_t_push_pop (void) | |
b99bd4ef | 10919 | { |
e9f89963 | 10920 | unsigned mask; |
5f4273c7 | 10921 | |
c19d1205 ZW |
10922 | constraint (inst.operands[0].writeback, |
10923 | _("push/pop do not support {reglist}^")); | |
10924 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
10925 | _("expression too complex")); | |
b99bd4ef | 10926 | |
e9f89963 PB |
10927 | mask = inst.operands[0].imm; |
10928 | if ((mask & ~0xff) == 0) | |
3c707909 | 10929 | inst.instruction = THUMB_OP16 (inst.instruction) | mask; |
c19d1205 | 10930 | else if ((inst.instruction == T_MNEM_push |
e9f89963 | 10931 | && (mask & ~0xff) == 1 << REG_LR) |
c19d1205 | 10932 | || (inst.instruction == T_MNEM_pop |
e9f89963 | 10933 | && (mask & ~0xff) == 1 << REG_PC)) |
b99bd4ef | 10934 | { |
c19d1205 ZW |
10935 | inst.instruction = THUMB_OP16 (inst.instruction); |
10936 | inst.instruction |= THUMB_PP_PC_LR; | |
3c707909 | 10937 | inst.instruction |= mask & 0xff; |
c19d1205 ZW |
10938 | } |
10939 | else if (unified_syntax) | |
10940 | { | |
3c707909 | 10941 | inst.instruction = THUMB_OP32 (inst.instruction); |
5f4273c7 | 10942 | encode_thumb2_ldmstm (13, mask, TRUE); |
c19d1205 ZW |
10943 | } |
10944 | else | |
10945 | { | |
10946 | inst.error = _("invalid register list to push/pop instruction"); | |
10947 | return; | |
10948 | } | |
c19d1205 | 10949 | } |
b99bd4ef | 10950 | |
c19d1205 ZW |
10951 | static void |
10952 | do_t_rbit (void) | |
10953 | { | |
fdfde340 JM |
10954 | unsigned Rd, Rm; |
10955 | ||
10956 | Rd = inst.operands[0].reg; | |
10957 | Rm = inst.operands[1].reg; | |
10958 | ||
10959 | reject_bad_reg (Rd); | |
10960 | reject_bad_reg (Rm); | |
10961 | ||
10962 | inst.instruction |= Rd << 8; | |
10963 | inst.instruction |= Rm << 16; | |
10964 | inst.instruction |= Rm; | |
c19d1205 | 10965 | } |
b99bd4ef | 10966 | |
c19d1205 ZW |
10967 | static void |
10968 | do_t_rev (void) | |
10969 | { | |
fdfde340 JM |
10970 | unsigned Rd, Rm; |
10971 | ||
10972 | Rd = inst.operands[0].reg; | |
10973 | Rm = inst.operands[1].reg; | |
10974 | ||
10975 | reject_bad_reg (Rd); | |
10976 | reject_bad_reg (Rm); | |
10977 | ||
10978 | if (Rd <= 7 && Rm <= 7 | |
c19d1205 ZW |
10979 | && inst.size_req != 4) |
10980 | { | |
10981 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 JM |
10982 | inst.instruction |= Rd; |
10983 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10984 | } |
10985 | else if (unified_syntax) | |
10986 | { | |
10987 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
10988 | inst.instruction |= Rd << 8; |
10989 | inst.instruction |= Rm << 16; | |
10990 | inst.instruction |= Rm; | |
c19d1205 ZW |
10991 | } |
10992 | else | |
10993 | inst.error = BAD_HIREG; | |
10994 | } | |
b99bd4ef | 10995 | |
1c444d06 JM |
10996 | static void |
10997 | do_t_rrx (void) | |
10998 | { | |
10999 | unsigned Rd, Rm; | |
11000 | ||
11001 | Rd = inst.operands[0].reg; | |
11002 | Rm = inst.operands[1].reg; | |
11003 | ||
fdfde340 JM |
11004 | reject_bad_reg (Rd); |
11005 | reject_bad_reg (Rm); | |
c921be7d | 11006 | |
1c444d06 JM |
11007 | inst.instruction |= Rd << 8; |
11008 | inst.instruction |= Rm; | |
11009 | } | |
11010 | ||
c19d1205 ZW |
11011 | static void |
11012 | do_t_rsb (void) | |
11013 | { | |
fdfde340 | 11014 | unsigned Rd, Rs; |
b99bd4ef | 11015 | |
c19d1205 ZW |
11016 | Rd = inst.operands[0].reg; |
11017 | Rs = (inst.operands[1].present | |
11018 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
11019 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 11020 | |
fdfde340 JM |
11021 | reject_bad_reg (Rd); |
11022 | reject_bad_reg (Rs); | |
11023 | if (inst.operands[2].isreg) | |
11024 | reject_bad_reg (inst.operands[2].reg); | |
11025 | ||
c19d1205 ZW |
11026 | inst.instruction |= Rd << 8; |
11027 | inst.instruction |= Rs << 16; | |
11028 | if (!inst.operands[2].isreg) | |
11029 | { | |
026d3abb PB |
11030 | bfd_boolean narrow; |
11031 | ||
11032 | if ((inst.instruction & 0x00100000) != 0) | |
e07e6e58 | 11033 | narrow = !in_it_block (); |
026d3abb | 11034 | else |
e07e6e58 | 11035 | narrow = in_it_block (); |
026d3abb PB |
11036 | |
11037 | if (Rd > 7 || Rs > 7) | |
11038 | narrow = FALSE; | |
11039 | ||
11040 | if (inst.size_req == 4 || !unified_syntax) | |
11041 | narrow = FALSE; | |
11042 | ||
11043 | if (inst.reloc.exp.X_op != O_constant | |
11044 | || inst.reloc.exp.X_add_number != 0) | |
11045 | narrow = FALSE; | |
11046 | ||
11047 | /* Turn rsb #0 into 16-bit neg. We should probably do this via | |
11048 | relaxation, but it doesn't seem worth the hassle. */ | |
11049 | if (narrow) | |
11050 | { | |
11051 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11052 | inst.instruction = THUMB_OP16 (T_MNEM_negs); | |
11053 | inst.instruction |= Rs << 3; | |
11054 | inst.instruction |= Rd; | |
11055 | } | |
11056 | else | |
11057 | { | |
11058 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
11059 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
11060 | } | |
c19d1205 ZW |
11061 | } |
11062 | else | |
11063 | encode_thumb32_shifted_operand (2); | |
11064 | } | |
b99bd4ef | 11065 | |
c19d1205 ZW |
11066 | static void |
11067 | do_t_setend (void) | |
11068 | { | |
e07e6e58 | 11069 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
11070 | if (inst.operands[0].imm) |
11071 | inst.instruction |= 0x8; | |
11072 | } | |
b99bd4ef | 11073 | |
c19d1205 ZW |
11074 | static void |
11075 | do_t_shift (void) | |
11076 | { | |
11077 | if (!inst.operands[1].present) | |
11078 | inst.operands[1].reg = inst.operands[0].reg; | |
11079 | ||
11080 | if (unified_syntax) | |
11081 | { | |
3d388997 PB |
11082 | bfd_boolean narrow; |
11083 | int shift_kind; | |
11084 | ||
11085 | switch (inst.instruction) | |
11086 | { | |
11087 | case T_MNEM_asr: | |
11088 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
11089 | case T_MNEM_lsl: | |
11090 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
11091 | case T_MNEM_lsr: | |
11092 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
11093 | case T_MNEM_ror: | |
11094 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
11095 | default: abort (); | |
11096 | } | |
11097 | ||
11098 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11099 | narrow = !in_it_block (); |
3d388997 | 11100 | else |
e07e6e58 | 11101 | narrow = in_it_block (); |
3d388997 PB |
11102 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
11103 | narrow = FALSE; | |
11104 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
11105 | narrow = FALSE; | |
11106 | if (inst.operands[2].isreg | |
11107 | && (inst.operands[1].reg != inst.operands[0].reg | |
11108 | || inst.operands[2].reg > 7)) | |
11109 | narrow = FALSE; | |
11110 | if (inst.size_req == 4) | |
11111 | narrow = FALSE; | |
11112 | ||
fdfde340 JM |
11113 | reject_bad_reg (inst.operands[0].reg); |
11114 | reject_bad_reg (inst.operands[1].reg); | |
c921be7d | 11115 | |
3d388997 | 11116 | if (!narrow) |
c19d1205 ZW |
11117 | { |
11118 | if (inst.operands[2].isreg) | |
b99bd4ef | 11119 | { |
fdfde340 | 11120 | reject_bad_reg (inst.operands[2].reg); |
c19d1205 ZW |
11121 | inst.instruction = THUMB_OP32 (inst.instruction); |
11122 | inst.instruction |= inst.operands[0].reg << 8; | |
11123 | inst.instruction |= inst.operands[1].reg << 16; | |
11124 | inst.instruction |= inst.operands[2].reg; | |
11125 | } | |
11126 | else | |
11127 | { | |
11128 | inst.operands[1].shifted = 1; | |
3d388997 | 11129 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
11130 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
11131 | ? T_MNEM_movs : T_MNEM_mov); | |
11132 | inst.instruction |= inst.operands[0].reg << 8; | |
11133 | encode_thumb32_shifted_operand (1); | |
11134 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
11135 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
11136 | } |
11137 | } | |
11138 | else | |
11139 | { | |
c19d1205 | 11140 | if (inst.operands[2].isreg) |
b99bd4ef | 11141 | { |
3d388997 | 11142 | switch (shift_kind) |
b99bd4ef | 11143 | { |
3d388997 PB |
11144 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
11145 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
11146 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
11147 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 11148 | default: abort (); |
b99bd4ef | 11149 | } |
5f4273c7 | 11150 | |
c19d1205 ZW |
11151 | inst.instruction |= inst.operands[0].reg; |
11152 | inst.instruction |= inst.operands[2].reg << 3; | |
b99bd4ef NC |
11153 | } |
11154 | else | |
11155 | { | |
3d388997 | 11156 | switch (shift_kind) |
b99bd4ef | 11157 | { |
3d388997 PB |
11158 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
11159 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
11160 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 11161 | default: abort (); |
b99bd4ef | 11162 | } |
c19d1205 ZW |
11163 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
11164 | inst.instruction |= inst.operands[0].reg; | |
11165 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
11166 | } |
11167 | } | |
c19d1205 ZW |
11168 | } |
11169 | else | |
11170 | { | |
11171 | constraint (inst.operands[0].reg > 7 | |
11172 | || inst.operands[1].reg > 7, BAD_HIREG); | |
11173 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 11174 | |
c19d1205 ZW |
11175 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
11176 | { | |
11177 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
11178 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
11179 | _("source1 and dest must be same register")); | |
b99bd4ef | 11180 | |
c19d1205 ZW |
11181 | switch (inst.instruction) |
11182 | { | |
11183 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
11184 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
11185 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
11186 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
11187 | default: abort (); | |
11188 | } | |
5f4273c7 | 11189 | |
c19d1205 ZW |
11190 | inst.instruction |= inst.operands[0].reg; |
11191 | inst.instruction |= inst.operands[2].reg << 3; | |
11192 | } | |
11193 | else | |
b99bd4ef | 11194 | { |
c19d1205 ZW |
11195 | switch (inst.instruction) |
11196 | { | |
11197 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
11198 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
11199 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
11200 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
11201 | default: abort (); | |
11202 | } | |
11203 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
11204 | inst.instruction |= inst.operands[0].reg; | |
11205 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
11206 | } |
11207 | } | |
b99bd4ef NC |
11208 | } |
11209 | ||
11210 | static void | |
c19d1205 | 11211 | do_t_simd (void) |
b99bd4ef | 11212 | { |
fdfde340 JM |
11213 | unsigned Rd, Rn, Rm; |
11214 | ||
11215 | Rd = inst.operands[0].reg; | |
11216 | Rn = inst.operands[1].reg; | |
11217 | Rm = inst.operands[2].reg; | |
11218 | ||
11219 | reject_bad_reg (Rd); | |
11220 | reject_bad_reg (Rn); | |
11221 | reject_bad_reg (Rm); | |
11222 | ||
11223 | inst.instruction |= Rd << 8; | |
11224 | inst.instruction |= Rn << 16; | |
11225 | inst.instruction |= Rm; | |
c19d1205 | 11226 | } |
b99bd4ef | 11227 | |
03ee1b7f NC |
11228 | static void |
11229 | do_t_simd2 (void) | |
11230 | { | |
11231 | unsigned Rd, Rn, Rm; | |
11232 | ||
11233 | Rd = inst.operands[0].reg; | |
11234 | Rm = inst.operands[1].reg; | |
11235 | Rn = inst.operands[2].reg; | |
11236 | ||
11237 | reject_bad_reg (Rd); | |
11238 | reject_bad_reg (Rn); | |
11239 | reject_bad_reg (Rm); | |
11240 | ||
11241 | inst.instruction |= Rd << 8; | |
11242 | inst.instruction |= Rn << 16; | |
11243 | inst.instruction |= Rm; | |
11244 | } | |
11245 | ||
c19d1205 | 11246 | static void |
3eb17e6b | 11247 | do_t_smc (void) |
c19d1205 ZW |
11248 | { |
11249 | unsigned int value = inst.reloc.exp.X_add_number; | |
11250 | constraint (inst.reloc.exp.X_op != O_constant, | |
11251 | _("expression too complex")); | |
11252 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11253 | inst.instruction |= (value & 0xf000) >> 12; | |
11254 | inst.instruction |= (value & 0x0ff0); | |
11255 | inst.instruction |= (value & 0x000f) << 16; | |
11256 | } | |
b99bd4ef | 11257 | |
c19d1205 | 11258 | static void |
3a21c15a | 11259 | do_t_ssat_usat (int bias) |
c19d1205 | 11260 | { |
fdfde340 JM |
11261 | unsigned Rd, Rn; |
11262 | ||
11263 | Rd = inst.operands[0].reg; | |
11264 | Rn = inst.operands[2].reg; | |
11265 | ||
11266 | reject_bad_reg (Rd); | |
11267 | reject_bad_reg (Rn); | |
11268 | ||
11269 | inst.instruction |= Rd << 8; | |
3a21c15a | 11270 | inst.instruction |= inst.operands[1].imm - bias; |
fdfde340 | 11271 | inst.instruction |= Rn << 16; |
b99bd4ef | 11272 | |
c19d1205 | 11273 | if (inst.operands[3].present) |
b99bd4ef | 11274 | { |
3a21c15a NC |
11275 | offsetT shift_amount = inst.reloc.exp.X_add_number; |
11276 | ||
11277 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11278 | ||
c19d1205 ZW |
11279 | constraint (inst.reloc.exp.X_op != O_constant, |
11280 | _("expression too complex")); | |
b99bd4ef | 11281 | |
3a21c15a | 11282 | if (shift_amount != 0) |
6189168b | 11283 | { |
3a21c15a NC |
11284 | constraint (shift_amount > 31, |
11285 | _("shift expression is too large")); | |
11286 | ||
c19d1205 | 11287 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
3a21c15a NC |
11288 | inst.instruction |= 0x00200000; /* sh bit. */ |
11289 | ||
11290 | inst.instruction |= (shift_amount & 0x1c) << 10; | |
11291 | inst.instruction |= (shift_amount & 0x03) << 6; | |
6189168b NC |
11292 | } |
11293 | } | |
b99bd4ef | 11294 | } |
c921be7d | 11295 | |
3a21c15a NC |
11296 | static void |
11297 | do_t_ssat (void) | |
11298 | { | |
11299 | do_t_ssat_usat (1); | |
11300 | } | |
b99bd4ef | 11301 | |
0dd132b6 | 11302 | static void |
c19d1205 | 11303 | do_t_ssat16 (void) |
0dd132b6 | 11304 | { |
fdfde340 JM |
11305 | unsigned Rd, Rn; |
11306 | ||
11307 | Rd = inst.operands[0].reg; | |
11308 | Rn = inst.operands[2].reg; | |
11309 | ||
11310 | reject_bad_reg (Rd); | |
11311 | reject_bad_reg (Rn); | |
11312 | ||
11313 | inst.instruction |= Rd << 8; | |
c19d1205 | 11314 | inst.instruction |= inst.operands[1].imm - 1; |
fdfde340 | 11315 | inst.instruction |= Rn << 16; |
c19d1205 | 11316 | } |
0dd132b6 | 11317 | |
c19d1205 ZW |
11318 | static void |
11319 | do_t_strex (void) | |
11320 | { | |
11321 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
11322 | || inst.operands[2].postind || inst.operands[2].writeback | |
11323 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
11324 | || inst.operands[2].negative, | |
01cfc07f | 11325 | BAD_ADDR_MODE); |
0dd132b6 | 11326 | |
5be8be5d DG |
11327 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
11328 | ||
c19d1205 ZW |
11329 | inst.instruction |= inst.operands[0].reg << 8; |
11330 | inst.instruction |= inst.operands[1].reg << 12; | |
11331 | inst.instruction |= inst.operands[2].reg << 16; | |
11332 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
11333 | } |
11334 | ||
b99bd4ef | 11335 | static void |
c19d1205 | 11336 | do_t_strexd (void) |
b99bd4ef | 11337 | { |
c19d1205 ZW |
11338 | if (!inst.operands[2].present) |
11339 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 11340 | |
c19d1205 ZW |
11341 | constraint (inst.operands[0].reg == inst.operands[1].reg |
11342 | || inst.operands[0].reg == inst.operands[2].reg | |
f8a8e9d6 | 11343 | || inst.operands[0].reg == inst.operands[3].reg, |
c19d1205 | 11344 | BAD_OVERLAP); |
b99bd4ef | 11345 | |
c19d1205 ZW |
11346 | inst.instruction |= inst.operands[0].reg; |
11347 | inst.instruction |= inst.operands[1].reg << 12; | |
11348 | inst.instruction |= inst.operands[2].reg << 8; | |
11349 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
11350 | } |
11351 | ||
11352 | static void | |
c19d1205 | 11353 | do_t_sxtah (void) |
b99bd4ef | 11354 | { |
fdfde340 JM |
11355 | unsigned Rd, Rn, Rm; |
11356 | ||
11357 | Rd = inst.operands[0].reg; | |
11358 | Rn = inst.operands[1].reg; | |
11359 | Rm = inst.operands[2].reg; | |
11360 | ||
11361 | reject_bad_reg (Rd); | |
11362 | reject_bad_reg (Rn); | |
11363 | reject_bad_reg (Rm); | |
11364 | ||
11365 | inst.instruction |= Rd << 8; | |
11366 | inst.instruction |= Rn << 16; | |
11367 | inst.instruction |= Rm; | |
c19d1205 ZW |
11368 | inst.instruction |= inst.operands[3].imm << 4; |
11369 | } | |
b99bd4ef | 11370 | |
c19d1205 ZW |
11371 | static void |
11372 | do_t_sxth (void) | |
11373 | { | |
fdfde340 JM |
11374 | unsigned Rd, Rm; |
11375 | ||
11376 | Rd = inst.operands[0].reg; | |
11377 | Rm = inst.operands[1].reg; | |
11378 | ||
11379 | reject_bad_reg (Rd); | |
11380 | reject_bad_reg (Rm); | |
c921be7d NC |
11381 | |
11382 | if (inst.instruction <= 0xffff | |
11383 | && inst.size_req != 4 | |
fdfde340 | 11384 | && Rd <= 7 && Rm <= 7 |
c19d1205 | 11385 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) |
b99bd4ef | 11386 | { |
c19d1205 | 11387 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
11388 | inst.instruction |= Rd; |
11389 | inst.instruction |= Rm << 3; | |
b99bd4ef | 11390 | } |
c19d1205 | 11391 | else if (unified_syntax) |
b99bd4ef | 11392 | { |
c19d1205 ZW |
11393 | if (inst.instruction <= 0xffff) |
11394 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
11395 | inst.instruction |= Rd << 8; |
11396 | inst.instruction |= Rm; | |
c19d1205 | 11397 | inst.instruction |= inst.operands[2].imm << 4; |
b99bd4ef | 11398 | } |
c19d1205 | 11399 | else |
b99bd4ef | 11400 | { |
c19d1205 ZW |
11401 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
11402 | _("Thumb encoding does not support rotation")); | |
11403 | constraint (1, BAD_HIREG); | |
b99bd4ef | 11404 | } |
c19d1205 | 11405 | } |
b99bd4ef | 11406 | |
c19d1205 ZW |
11407 | static void |
11408 | do_t_swi (void) | |
11409 | { | |
11410 | inst.reloc.type = BFD_RELOC_ARM_SWI; | |
11411 | } | |
b99bd4ef | 11412 | |
92e90b6e PB |
11413 | static void |
11414 | do_t_tb (void) | |
11415 | { | |
fdfde340 | 11416 | unsigned Rn, Rm; |
92e90b6e PB |
11417 | int half; |
11418 | ||
11419 | half = (inst.instruction & 0x10) != 0; | |
e07e6e58 | 11420 | set_it_insn_type_last (); |
dfa9f0d5 PB |
11421 | constraint (inst.operands[0].immisreg, |
11422 | _("instruction requires register index")); | |
fdfde340 JM |
11423 | |
11424 | Rn = inst.operands[0].reg; | |
11425 | Rm = inst.operands[0].imm; | |
c921be7d | 11426 | |
fdfde340 JM |
11427 | constraint (Rn == REG_SP, BAD_SP); |
11428 | reject_bad_reg (Rm); | |
11429 | ||
92e90b6e PB |
11430 | constraint (!half && inst.operands[0].shifted, |
11431 | _("instruction does not allow shifted index")); | |
fdfde340 | 11432 | inst.instruction |= (Rn << 16) | Rm; |
92e90b6e PB |
11433 | } |
11434 | ||
c19d1205 ZW |
11435 | static void |
11436 | do_t_usat (void) | |
11437 | { | |
3a21c15a | 11438 | do_t_ssat_usat (0); |
b99bd4ef NC |
11439 | } |
11440 | ||
11441 | static void | |
c19d1205 | 11442 | do_t_usat16 (void) |
b99bd4ef | 11443 | { |
fdfde340 JM |
11444 | unsigned Rd, Rn; |
11445 | ||
11446 | Rd = inst.operands[0].reg; | |
11447 | Rn = inst.operands[2].reg; | |
11448 | ||
11449 | reject_bad_reg (Rd); | |
11450 | reject_bad_reg (Rn); | |
11451 | ||
11452 | inst.instruction |= Rd << 8; | |
c19d1205 | 11453 | inst.instruction |= inst.operands[1].imm; |
fdfde340 | 11454 | inst.instruction |= Rn << 16; |
b99bd4ef | 11455 | } |
c19d1205 | 11456 | |
5287ad62 | 11457 | /* Neon instruction encoder helpers. */ |
5f4273c7 | 11458 | |
5287ad62 | 11459 | /* Encodings for the different types for various Neon opcodes. */ |
b99bd4ef | 11460 | |
5287ad62 JB |
11461 | /* An "invalid" code for the following tables. */ |
11462 | #define N_INV -1u | |
11463 | ||
11464 | struct neon_tab_entry | |
b99bd4ef | 11465 | { |
5287ad62 JB |
11466 | unsigned integer; |
11467 | unsigned float_or_poly; | |
11468 | unsigned scalar_or_imm; | |
11469 | }; | |
5f4273c7 | 11470 | |
5287ad62 JB |
11471 | /* Map overloaded Neon opcodes to their respective encodings. */ |
11472 | #define NEON_ENC_TAB \ | |
11473 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ | |
11474 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ | |
11475 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ | |
11476 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ | |
11477 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ | |
11478 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ | |
11479 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ | |
11480 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ | |
11481 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ | |
11482 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ | |
11483 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ | |
11484 | /* Register variants of the following two instructions are encoded as | |
e07e6e58 | 11485 | vcge / vcgt with the operands reversed. */ \ |
92559b5b PB |
11486 | X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ |
11487 | X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ | |
62f3b8c8 PB |
11488 | X(vfma, N_INV, 0x0000c10, N_INV), \ |
11489 | X(vfms, N_INV, 0x0200c10, N_INV), \ | |
5287ad62 JB |
11490 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ |
11491 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ | |
11492 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ | |
11493 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ | |
11494 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ | |
11495 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ | |
11496 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ | |
11497 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ | |
11498 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ | |
11499 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ | |
11500 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ | |
11501 | X(vshl, 0x0000400, N_INV, 0x0800510), \ | |
11502 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ | |
11503 | X(vand, 0x0000110, N_INV, 0x0800030), \ | |
11504 | X(vbic, 0x0100110, N_INV, 0x0800030), \ | |
11505 | X(veor, 0x1000110, N_INV, N_INV), \ | |
11506 | X(vorn, 0x0300110, N_INV, 0x0800010), \ | |
11507 | X(vorr, 0x0200110, N_INV, 0x0800010), \ | |
11508 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ | |
11509 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ | |
11510 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ | |
11511 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ | |
11512 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ | |
11513 | X(vst1, 0x0000000, 0x0800000, N_INV), \ | |
11514 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ | |
11515 | X(vst2, 0x0000100, 0x0800100, N_INV), \ | |
11516 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ | |
11517 | X(vst3, 0x0000200, 0x0800200, N_INV), \ | |
11518 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ | |
11519 | X(vst4, 0x0000300, 0x0800300, N_INV), \ | |
11520 | X(vmovn, 0x1b20200, N_INV, N_INV), \ | |
11521 | X(vtrn, 0x1b20080, N_INV, N_INV), \ | |
11522 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ | |
037e8744 JB |
11523 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
11524 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ | |
e6655fda PB |
11525 | X(vnmla, 0xe100a40, 0xe100b40, N_INV), \ |
11526 | X(vnmls, 0xe100a00, 0xe100b00, N_INV), \ | |
62f3b8c8 PB |
11527 | X(vfnma, 0xe900a40, 0xe900b40, N_INV), \ |
11528 | X(vfnms, 0xe900a00, 0xe900b00, N_INV), \ | |
037e8744 JB |
11529 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ |
11530 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ | |
11531 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ | |
11532 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) | |
5287ad62 JB |
11533 | |
11534 | enum neon_opc | |
11535 | { | |
11536 | #define X(OPC,I,F,S) N_MNEM_##OPC | |
11537 | NEON_ENC_TAB | |
11538 | #undef X | |
11539 | }; | |
b99bd4ef | 11540 | |
5287ad62 JB |
11541 | static const struct neon_tab_entry neon_enc_tab[] = |
11542 | { | |
11543 | #define X(OPC,I,F,S) { (I), (F), (S) } | |
11544 | NEON_ENC_TAB | |
11545 | #undef X | |
11546 | }; | |
b99bd4ef | 11547 | |
88714cb8 DG |
11548 | /* Do not use these macros; instead, use NEON_ENCODE defined below. */ |
11549 | #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
11550 | #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
11551 | #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11552 | #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11553 | #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
11554 | #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
11555 | #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
11556 | #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11557 | #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
11558 | #define NEON_ENC_SINGLE_(X) \ | |
037e8744 | 11559 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) |
88714cb8 | 11560 | #define NEON_ENC_DOUBLE_(X) \ |
037e8744 | 11561 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) |
5287ad62 | 11562 | |
88714cb8 DG |
11563 | #define NEON_ENCODE(type, inst) \ |
11564 | do \ | |
11565 | { \ | |
11566 | inst.instruction = NEON_ENC_##type##_ (inst.instruction); \ | |
11567 | inst.is_neon = 1; \ | |
11568 | } \ | |
11569 | while (0) | |
11570 | ||
11571 | #define check_neon_suffixes \ | |
11572 | do \ | |
11573 | { \ | |
11574 | if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \ | |
11575 | { \ | |
11576 | as_bad (_("invalid neon suffix for non neon instruction")); \ | |
11577 | return; \ | |
11578 | } \ | |
11579 | } \ | |
11580 | while (0) | |
11581 | ||
037e8744 JB |
11582 | /* Define shapes for instruction operands. The following mnemonic characters |
11583 | are used in this table: | |
5287ad62 | 11584 | |
037e8744 | 11585 | F - VFP S<n> register |
5287ad62 JB |
11586 | D - Neon D<n> register |
11587 | Q - Neon Q<n> register | |
11588 | I - Immediate | |
11589 | S - Scalar | |
11590 | R - ARM register | |
11591 | L - D<n> register list | |
5f4273c7 | 11592 | |
037e8744 JB |
11593 | This table is used to generate various data: |
11594 | - enumerations of the form NS_DDR to be used as arguments to | |
11595 | neon_select_shape. | |
11596 | - a table classifying shapes into single, double, quad, mixed. | |
5f4273c7 | 11597 | - a table used to drive neon_select_shape. */ |
b99bd4ef | 11598 | |
037e8744 JB |
11599 | #define NEON_SHAPE_DEF \ |
11600 | X(3, (D, D, D), DOUBLE), \ | |
11601 | X(3, (Q, Q, Q), QUAD), \ | |
11602 | X(3, (D, D, I), DOUBLE), \ | |
11603 | X(3, (Q, Q, I), QUAD), \ | |
11604 | X(3, (D, D, S), DOUBLE), \ | |
11605 | X(3, (Q, Q, S), QUAD), \ | |
11606 | X(2, (D, D), DOUBLE), \ | |
11607 | X(2, (Q, Q), QUAD), \ | |
11608 | X(2, (D, S), DOUBLE), \ | |
11609 | X(2, (Q, S), QUAD), \ | |
11610 | X(2, (D, R), DOUBLE), \ | |
11611 | X(2, (Q, R), QUAD), \ | |
11612 | X(2, (D, I), DOUBLE), \ | |
11613 | X(2, (Q, I), QUAD), \ | |
11614 | X(3, (D, L, D), DOUBLE), \ | |
11615 | X(2, (D, Q), MIXED), \ | |
11616 | X(2, (Q, D), MIXED), \ | |
11617 | X(3, (D, Q, I), MIXED), \ | |
11618 | X(3, (Q, D, I), MIXED), \ | |
11619 | X(3, (Q, D, D), MIXED), \ | |
11620 | X(3, (D, Q, Q), MIXED), \ | |
11621 | X(3, (Q, Q, D), MIXED), \ | |
11622 | X(3, (Q, D, S), MIXED), \ | |
11623 | X(3, (D, Q, S), MIXED), \ | |
11624 | X(4, (D, D, D, I), DOUBLE), \ | |
11625 | X(4, (Q, Q, Q, I), QUAD), \ | |
11626 | X(2, (F, F), SINGLE), \ | |
11627 | X(3, (F, F, F), SINGLE), \ | |
11628 | X(2, (F, I), SINGLE), \ | |
11629 | X(2, (F, D), MIXED), \ | |
11630 | X(2, (D, F), MIXED), \ | |
11631 | X(3, (F, F, I), MIXED), \ | |
11632 | X(4, (R, R, F, F), SINGLE), \ | |
11633 | X(4, (F, F, R, R), SINGLE), \ | |
11634 | X(3, (D, R, R), DOUBLE), \ | |
11635 | X(3, (R, R, D), DOUBLE), \ | |
11636 | X(2, (S, R), SINGLE), \ | |
11637 | X(2, (R, S), SINGLE), \ | |
11638 | X(2, (F, R), SINGLE), \ | |
11639 | X(2, (R, F), SINGLE) | |
11640 | ||
11641 | #define S2(A,B) NS_##A##B | |
11642 | #define S3(A,B,C) NS_##A##B##C | |
11643 | #define S4(A,B,C,D) NS_##A##B##C##D | |
11644 | ||
11645 | #define X(N, L, C) S##N L | |
11646 | ||
5287ad62 JB |
11647 | enum neon_shape |
11648 | { | |
037e8744 JB |
11649 | NEON_SHAPE_DEF, |
11650 | NS_NULL | |
5287ad62 | 11651 | }; |
b99bd4ef | 11652 | |
037e8744 JB |
11653 | #undef X |
11654 | #undef S2 | |
11655 | #undef S3 | |
11656 | #undef S4 | |
11657 | ||
11658 | enum neon_shape_class | |
11659 | { | |
11660 | SC_SINGLE, | |
11661 | SC_DOUBLE, | |
11662 | SC_QUAD, | |
11663 | SC_MIXED | |
11664 | }; | |
11665 | ||
11666 | #define X(N, L, C) SC_##C | |
11667 | ||
11668 | static enum neon_shape_class neon_shape_class[] = | |
11669 | { | |
11670 | NEON_SHAPE_DEF | |
11671 | }; | |
11672 | ||
11673 | #undef X | |
11674 | ||
11675 | enum neon_shape_el | |
11676 | { | |
11677 | SE_F, | |
11678 | SE_D, | |
11679 | SE_Q, | |
11680 | SE_I, | |
11681 | SE_S, | |
11682 | SE_R, | |
11683 | SE_L | |
11684 | }; | |
11685 | ||
11686 | /* Register widths of above. */ | |
11687 | static unsigned neon_shape_el_size[] = | |
11688 | { | |
11689 | 32, | |
11690 | 64, | |
11691 | 128, | |
11692 | 0, | |
11693 | 32, | |
11694 | 32, | |
11695 | 0 | |
11696 | }; | |
11697 | ||
11698 | struct neon_shape_info | |
11699 | { | |
11700 | unsigned els; | |
11701 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; | |
11702 | }; | |
11703 | ||
11704 | #define S2(A,B) { SE_##A, SE_##B } | |
11705 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } | |
11706 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } | |
11707 | ||
11708 | #define X(N, L, C) { N, S##N L } | |
11709 | ||
11710 | static struct neon_shape_info neon_shape_tab[] = | |
11711 | { | |
11712 | NEON_SHAPE_DEF | |
11713 | }; | |
11714 | ||
11715 | #undef X | |
11716 | #undef S2 | |
11717 | #undef S3 | |
11718 | #undef S4 | |
11719 | ||
5287ad62 JB |
11720 | /* Bit masks used in type checking given instructions. |
11721 | 'N_EQK' means the type must be the same as (or based on in some way) the key | |
11722 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is | |
11723 | set, various other bits can be set as well in order to modify the meaning of | |
11724 | the type constraint. */ | |
11725 | ||
11726 | enum neon_type_mask | |
11727 | { | |
8e79c3df CM |
11728 | N_S8 = 0x0000001, |
11729 | N_S16 = 0x0000002, | |
11730 | N_S32 = 0x0000004, | |
11731 | N_S64 = 0x0000008, | |
11732 | N_U8 = 0x0000010, | |
11733 | N_U16 = 0x0000020, | |
11734 | N_U32 = 0x0000040, | |
11735 | N_U64 = 0x0000080, | |
11736 | N_I8 = 0x0000100, | |
11737 | N_I16 = 0x0000200, | |
11738 | N_I32 = 0x0000400, | |
11739 | N_I64 = 0x0000800, | |
11740 | N_8 = 0x0001000, | |
11741 | N_16 = 0x0002000, | |
11742 | N_32 = 0x0004000, | |
11743 | N_64 = 0x0008000, | |
11744 | N_P8 = 0x0010000, | |
11745 | N_P16 = 0x0020000, | |
11746 | N_F16 = 0x0040000, | |
11747 | N_F32 = 0x0080000, | |
11748 | N_F64 = 0x0100000, | |
c921be7d NC |
11749 | N_KEY = 0x1000000, /* Key element (main type specifier). */ |
11750 | N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ | |
8e79c3df | 11751 | N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ |
c921be7d NC |
11752 | N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ |
11753 | N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ | |
11754 | N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ | |
11755 | N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ | |
11756 | N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ | |
11757 | N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ | |
11758 | N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ | |
5287ad62 | 11759 | N_UTYP = 0, |
037e8744 | 11760 | N_MAX_NONSPECIAL = N_F64 |
5287ad62 JB |
11761 | }; |
11762 | ||
dcbf9037 JB |
11763 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
11764 | ||
5287ad62 JB |
11765 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
11766 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
11767 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) | |
11768 | #define N_SUF_32 (N_SU_32 | N_F32) | |
11769 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) | |
11770 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) | |
11771 | ||
11772 | /* Pass this as the first type argument to neon_check_type to ignore types | |
11773 | altogether. */ | |
11774 | #define N_IGNORE_TYPE (N_KEY | N_EQK) | |
11775 | ||
037e8744 JB |
11776 | /* Select a "shape" for the current instruction (describing register types or |
11777 | sizes) from a list of alternatives. Return NS_NULL if the current instruction | |
11778 | doesn't fit. For non-polymorphic shapes, checking is usually done as a | |
11779 | function of operand parsing, so this function doesn't need to be called. | |
11780 | Shapes should be listed in order of decreasing length. */ | |
5287ad62 JB |
11781 | |
11782 | static enum neon_shape | |
037e8744 | 11783 | neon_select_shape (enum neon_shape shape, ...) |
5287ad62 | 11784 | { |
037e8744 JB |
11785 | va_list ap; |
11786 | enum neon_shape first_shape = shape; | |
5287ad62 JB |
11787 | |
11788 | /* Fix missing optional operands. FIXME: we don't know at this point how | |
11789 | many arguments we should have, so this makes the assumption that we have | |
11790 | > 1. This is true of all current Neon opcodes, I think, but may not be | |
11791 | true in the future. */ | |
11792 | if (!inst.operands[1].present) | |
11793 | inst.operands[1] = inst.operands[0]; | |
11794 | ||
037e8744 | 11795 | va_start (ap, shape); |
5f4273c7 | 11796 | |
21d799b5 | 11797 | for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int)) |
037e8744 JB |
11798 | { |
11799 | unsigned j; | |
11800 | int matches = 1; | |
11801 | ||
11802 | for (j = 0; j < neon_shape_tab[shape].els; j++) | |
11803 | { | |
11804 | if (!inst.operands[j].present) | |
11805 | { | |
11806 | matches = 0; | |
11807 | break; | |
11808 | } | |
11809 | ||
11810 | switch (neon_shape_tab[shape].el[j]) | |
11811 | { | |
11812 | case SE_F: | |
11813 | if (!(inst.operands[j].isreg | |
11814 | && inst.operands[j].isvec | |
11815 | && inst.operands[j].issingle | |
11816 | && !inst.operands[j].isquad)) | |
11817 | matches = 0; | |
11818 | break; | |
11819 | ||
11820 | case SE_D: | |
11821 | if (!(inst.operands[j].isreg | |
11822 | && inst.operands[j].isvec | |
11823 | && !inst.operands[j].isquad | |
11824 | && !inst.operands[j].issingle)) | |
11825 | matches = 0; | |
11826 | break; | |
11827 | ||
11828 | case SE_R: | |
11829 | if (!(inst.operands[j].isreg | |
11830 | && !inst.operands[j].isvec)) | |
11831 | matches = 0; | |
11832 | break; | |
11833 | ||
11834 | case SE_Q: | |
11835 | if (!(inst.operands[j].isreg | |
11836 | && inst.operands[j].isvec | |
11837 | && inst.operands[j].isquad | |
11838 | && !inst.operands[j].issingle)) | |
11839 | matches = 0; | |
11840 | break; | |
11841 | ||
11842 | case SE_I: | |
11843 | if (!(!inst.operands[j].isreg | |
11844 | && !inst.operands[j].isscalar)) | |
11845 | matches = 0; | |
11846 | break; | |
11847 | ||
11848 | case SE_S: | |
11849 | if (!(!inst.operands[j].isreg | |
11850 | && inst.operands[j].isscalar)) | |
11851 | matches = 0; | |
11852 | break; | |
11853 | ||
11854 | case SE_L: | |
11855 | break; | |
11856 | } | |
3fde54a2 JZ |
11857 | if (!matches) |
11858 | break; | |
037e8744 JB |
11859 | } |
11860 | if (matches) | |
5287ad62 | 11861 | break; |
037e8744 | 11862 | } |
5f4273c7 | 11863 | |
037e8744 | 11864 | va_end (ap); |
5287ad62 | 11865 | |
037e8744 JB |
11866 | if (shape == NS_NULL && first_shape != NS_NULL) |
11867 | first_error (_("invalid instruction shape")); | |
5287ad62 | 11868 | |
037e8744 JB |
11869 | return shape; |
11870 | } | |
5287ad62 | 11871 | |
037e8744 JB |
11872 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
11873 | means the Q bit should be set). */ | |
11874 | ||
11875 | static int | |
11876 | neon_quad (enum neon_shape shape) | |
11877 | { | |
11878 | return neon_shape_class[shape] == SC_QUAD; | |
5287ad62 | 11879 | } |
037e8744 | 11880 | |
5287ad62 JB |
11881 | static void |
11882 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, | |
11883 | unsigned *g_size) | |
11884 | { | |
11885 | /* Allow modification to be made to types which are constrained to be | |
11886 | based on the key element, based on bits set alongside N_EQK. */ | |
11887 | if ((typebits & N_EQK) != 0) | |
11888 | { | |
11889 | if ((typebits & N_HLF) != 0) | |
11890 | *g_size /= 2; | |
11891 | else if ((typebits & N_DBL) != 0) | |
11892 | *g_size *= 2; | |
11893 | if ((typebits & N_SGN) != 0) | |
11894 | *g_type = NT_signed; | |
11895 | else if ((typebits & N_UNS) != 0) | |
11896 | *g_type = NT_unsigned; | |
11897 | else if ((typebits & N_INT) != 0) | |
11898 | *g_type = NT_integer; | |
11899 | else if ((typebits & N_FLT) != 0) | |
11900 | *g_type = NT_float; | |
dcbf9037 JB |
11901 | else if ((typebits & N_SIZ) != 0) |
11902 | *g_type = NT_untyped; | |
5287ad62 JB |
11903 | } |
11904 | } | |
5f4273c7 | 11905 | |
5287ad62 JB |
11906 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" |
11907 | operand type, i.e. the single type specified in a Neon instruction when it | |
11908 | is the only one given. */ | |
11909 | ||
11910 | static struct neon_type_el | |
11911 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) | |
11912 | { | |
11913 | struct neon_type_el dest = *key; | |
5f4273c7 | 11914 | |
9c2799c2 | 11915 | gas_assert ((thisarg & N_EQK) != 0); |
5f4273c7 | 11916 | |
5287ad62 JB |
11917 | neon_modify_type_size (thisarg, &dest.type, &dest.size); |
11918 | ||
11919 | return dest; | |
11920 | } | |
11921 | ||
11922 | /* Convert Neon type and size into compact bitmask representation. */ | |
11923 | ||
11924 | static enum neon_type_mask | |
11925 | type_chk_of_el_type (enum neon_el_type type, unsigned size) | |
11926 | { | |
11927 | switch (type) | |
11928 | { | |
11929 | case NT_untyped: | |
11930 | switch (size) | |
11931 | { | |
11932 | case 8: return N_8; | |
11933 | case 16: return N_16; | |
11934 | case 32: return N_32; | |
11935 | case 64: return N_64; | |
11936 | default: ; | |
11937 | } | |
11938 | break; | |
11939 | ||
11940 | case NT_integer: | |
11941 | switch (size) | |
11942 | { | |
11943 | case 8: return N_I8; | |
11944 | case 16: return N_I16; | |
11945 | case 32: return N_I32; | |
11946 | case 64: return N_I64; | |
11947 | default: ; | |
11948 | } | |
11949 | break; | |
11950 | ||
11951 | case NT_float: | |
037e8744 JB |
11952 | switch (size) |
11953 | { | |
8e79c3df | 11954 | case 16: return N_F16; |
037e8744 JB |
11955 | case 32: return N_F32; |
11956 | case 64: return N_F64; | |
11957 | default: ; | |
11958 | } | |
5287ad62 JB |
11959 | break; |
11960 | ||
11961 | case NT_poly: | |
11962 | switch (size) | |
11963 | { | |
11964 | case 8: return N_P8; | |
11965 | case 16: return N_P16; | |
11966 | default: ; | |
11967 | } | |
11968 | break; | |
11969 | ||
11970 | case NT_signed: | |
11971 | switch (size) | |
11972 | { | |
11973 | case 8: return N_S8; | |
11974 | case 16: return N_S16; | |
11975 | case 32: return N_S32; | |
11976 | case 64: return N_S64; | |
11977 | default: ; | |
11978 | } | |
11979 | break; | |
11980 | ||
11981 | case NT_unsigned: | |
11982 | switch (size) | |
11983 | { | |
11984 | case 8: return N_U8; | |
11985 | case 16: return N_U16; | |
11986 | case 32: return N_U32; | |
11987 | case 64: return N_U64; | |
11988 | default: ; | |
11989 | } | |
11990 | break; | |
11991 | ||
11992 | default: ; | |
11993 | } | |
5f4273c7 | 11994 | |
5287ad62 JB |
11995 | return N_UTYP; |
11996 | } | |
11997 | ||
11998 | /* Convert compact Neon bitmask type representation to a type and size. Only | |
11999 | handles the case where a single bit is set in the mask. */ | |
12000 | ||
dcbf9037 | 12001 | static int |
5287ad62 JB |
12002 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
12003 | enum neon_type_mask mask) | |
12004 | { | |
dcbf9037 JB |
12005 | if ((mask & N_EQK) != 0) |
12006 | return FAIL; | |
12007 | ||
5287ad62 JB |
12008 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
12009 | *size = 8; | |
dcbf9037 | 12010 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) |
5287ad62 | 12011 | *size = 16; |
dcbf9037 | 12012 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
5287ad62 | 12013 | *size = 32; |
037e8744 | 12014 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) |
5287ad62 | 12015 | *size = 64; |
dcbf9037 JB |
12016 | else |
12017 | return FAIL; | |
12018 | ||
5287ad62 JB |
12019 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
12020 | *type = NT_signed; | |
dcbf9037 | 12021 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
5287ad62 | 12022 | *type = NT_unsigned; |
dcbf9037 | 12023 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
5287ad62 | 12024 | *type = NT_integer; |
dcbf9037 | 12025 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
5287ad62 | 12026 | *type = NT_untyped; |
dcbf9037 | 12027 | else if ((mask & (N_P8 | N_P16)) != 0) |
5287ad62 | 12028 | *type = NT_poly; |
037e8744 | 12029 | else if ((mask & (N_F32 | N_F64)) != 0) |
5287ad62 | 12030 | *type = NT_float; |
dcbf9037 JB |
12031 | else |
12032 | return FAIL; | |
5f4273c7 | 12033 | |
dcbf9037 | 12034 | return SUCCESS; |
5287ad62 JB |
12035 | } |
12036 | ||
12037 | /* Modify a bitmask of allowed types. This is only needed for type | |
12038 | relaxation. */ | |
12039 | ||
12040 | static unsigned | |
12041 | modify_types_allowed (unsigned allowed, unsigned mods) | |
12042 | { | |
12043 | unsigned size; | |
12044 | enum neon_el_type type; | |
12045 | unsigned destmask; | |
12046 | int i; | |
5f4273c7 | 12047 | |
5287ad62 | 12048 | destmask = 0; |
5f4273c7 | 12049 | |
5287ad62 JB |
12050 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) |
12051 | { | |
21d799b5 NC |
12052 | if (el_type_of_type_chk (&type, &size, |
12053 | (enum neon_type_mask) (allowed & i)) == SUCCESS) | |
dcbf9037 JB |
12054 | { |
12055 | neon_modify_type_size (mods, &type, &size); | |
12056 | destmask |= type_chk_of_el_type (type, size); | |
12057 | } | |
5287ad62 | 12058 | } |
5f4273c7 | 12059 | |
5287ad62 JB |
12060 | return destmask; |
12061 | } | |
12062 | ||
12063 | /* Check type and return type classification. | |
12064 | The manual states (paraphrase): If one datatype is given, it indicates the | |
12065 | type given in: | |
12066 | - the second operand, if there is one | |
12067 | - the operand, if there is no second operand | |
12068 | - the result, if there are no operands. | |
12069 | This isn't quite good enough though, so we use a concept of a "key" datatype | |
12070 | which is set on a per-instruction basis, which is the one which matters when | |
12071 | only one data type is written. | |
12072 | Note: this function has side-effects (e.g. filling in missing operands). All | |
037e8744 | 12073 | Neon instructions should call it before performing bit encoding. */ |
5287ad62 JB |
12074 | |
12075 | static struct neon_type_el | |
12076 | neon_check_type (unsigned els, enum neon_shape ns, ...) | |
12077 | { | |
12078 | va_list ap; | |
12079 | unsigned i, pass, key_el = 0; | |
12080 | unsigned types[NEON_MAX_TYPE_ELS]; | |
12081 | enum neon_el_type k_type = NT_invtype; | |
12082 | unsigned k_size = -1u; | |
12083 | struct neon_type_el badtype = {NT_invtype, -1}; | |
12084 | unsigned key_allowed = 0; | |
12085 | ||
12086 | /* Optional registers in Neon instructions are always (not) in operand 1. | |
12087 | Fill in the missing operand here, if it was omitted. */ | |
12088 | if (els > 1 && !inst.operands[1].present) | |
12089 | inst.operands[1] = inst.operands[0]; | |
12090 | ||
12091 | /* Suck up all the varargs. */ | |
12092 | va_start (ap, ns); | |
12093 | for (i = 0; i < els; i++) | |
12094 | { | |
12095 | unsigned thisarg = va_arg (ap, unsigned); | |
12096 | if (thisarg == N_IGNORE_TYPE) | |
12097 | { | |
12098 | va_end (ap); | |
12099 | return badtype; | |
12100 | } | |
12101 | types[i] = thisarg; | |
12102 | if ((thisarg & N_KEY) != 0) | |
12103 | key_el = i; | |
12104 | } | |
12105 | va_end (ap); | |
12106 | ||
dcbf9037 JB |
12107 | if (inst.vectype.elems > 0) |
12108 | for (i = 0; i < els; i++) | |
12109 | if (inst.operands[i].vectype.type != NT_invtype) | |
12110 | { | |
12111 | first_error (_("types specified in both the mnemonic and operands")); | |
12112 | return badtype; | |
12113 | } | |
12114 | ||
5287ad62 JB |
12115 | /* Duplicate inst.vectype elements here as necessary. |
12116 | FIXME: No idea if this is exactly the same as the ARM assembler, | |
12117 | particularly when an insn takes one register and one non-register | |
12118 | operand. */ | |
12119 | if (inst.vectype.elems == 1 && els > 1) | |
12120 | { | |
12121 | unsigned j; | |
12122 | inst.vectype.elems = els; | |
12123 | inst.vectype.el[key_el] = inst.vectype.el[0]; | |
12124 | for (j = 0; j < els; j++) | |
dcbf9037 JB |
12125 | if (j != key_el) |
12126 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
12127 | types[j]); | |
12128 | } | |
12129 | else if (inst.vectype.elems == 0 && els > 0) | |
12130 | { | |
12131 | unsigned j; | |
12132 | /* No types were given after the mnemonic, so look for types specified | |
12133 | after each operand. We allow some flexibility here; as long as the | |
12134 | "key" operand has a type, we can infer the others. */ | |
12135 | for (j = 0; j < els; j++) | |
12136 | if (inst.operands[j].vectype.type != NT_invtype) | |
12137 | inst.vectype.el[j] = inst.operands[j].vectype; | |
12138 | ||
12139 | if (inst.operands[key_el].vectype.type != NT_invtype) | |
5287ad62 | 12140 | { |
dcbf9037 JB |
12141 | for (j = 0; j < els; j++) |
12142 | if (inst.operands[j].vectype.type == NT_invtype) | |
12143 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
12144 | types[j]); | |
12145 | } | |
12146 | else | |
12147 | { | |
12148 | first_error (_("operand types can't be inferred")); | |
12149 | return badtype; | |
5287ad62 JB |
12150 | } |
12151 | } | |
12152 | else if (inst.vectype.elems != els) | |
12153 | { | |
dcbf9037 | 12154 | first_error (_("type specifier has the wrong number of parts")); |
5287ad62 JB |
12155 | return badtype; |
12156 | } | |
12157 | ||
12158 | for (pass = 0; pass < 2; pass++) | |
12159 | { | |
12160 | for (i = 0; i < els; i++) | |
12161 | { | |
12162 | unsigned thisarg = types[i]; | |
12163 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) | |
12164 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; | |
12165 | enum neon_el_type g_type = inst.vectype.el[i].type; | |
12166 | unsigned g_size = inst.vectype.el[i].size; | |
12167 | ||
12168 | /* Decay more-specific signed & unsigned types to sign-insensitive | |
12169 | integer types if sign-specific variants are unavailable. */ | |
12170 | if ((g_type == NT_signed || g_type == NT_unsigned) | |
12171 | && (types_allowed & N_SU_ALL) == 0) | |
12172 | g_type = NT_integer; | |
12173 | ||
12174 | /* If only untyped args are allowed, decay any more specific types to | |
12175 | them. Some instructions only care about signs for some element | |
12176 | sizes, so handle that properly. */ | |
12177 | if ((g_size == 8 && (types_allowed & N_8) != 0) | |
12178 | || (g_size == 16 && (types_allowed & N_16) != 0) | |
12179 | || (g_size == 32 && (types_allowed & N_32) != 0) | |
12180 | || (g_size == 64 && (types_allowed & N_64) != 0)) | |
12181 | g_type = NT_untyped; | |
12182 | ||
12183 | if (pass == 0) | |
12184 | { | |
12185 | if ((thisarg & N_KEY) != 0) | |
12186 | { | |
12187 | k_type = g_type; | |
12188 | k_size = g_size; | |
12189 | key_allowed = thisarg & ~N_KEY; | |
12190 | } | |
12191 | } | |
12192 | else | |
12193 | { | |
037e8744 JB |
12194 | if ((thisarg & N_VFP) != 0) |
12195 | { | |
99b253c5 NC |
12196 | enum neon_shape_el regshape; |
12197 | unsigned regwidth, match; | |
12198 | ||
12199 | /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */ | |
12200 | if (ns == NS_NULL) | |
12201 | { | |
12202 | first_error (_("invalid instruction shape")); | |
12203 | return badtype; | |
12204 | } | |
12205 | regshape = neon_shape_tab[ns].el[i]; | |
12206 | regwidth = neon_shape_el_size[regshape]; | |
037e8744 JB |
12207 | |
12208 | /* In VFP mode, operands must match register widths. If we | |
12209 | have a key operand, use its width, else use the width of | |
12210 | the current operand. */ | |
12211 | if (k_size != -1u) | |
12212 | match = k_size; | |
12213 | else | |
12214 | match = g_size; | |
12215 | ||
12216 | if (regwidth != match) | |
12217 | { | |
12218 | first_error (_("operand size must match register width")); | |
12219 | return badtype; | |
12220 | } | |
12221 | } | |
5f4273c7 | 12222 | |
5287ad62 JB |
12223 | if ((thisarg & N_EQK) == 0) |
12224 | { | |
12225 | unsigned given_type = type_chk_of_el_type (g_type, g_size); | |
12226 | ||
12227 | if ((given_type & types_allowed) == 0) | |
12228 | { | |
dcbf9037 | 12229 | first_error (_("bad type in Neon instruction")); |
5287ad62 JB |
12230 | return badtype; |
12231 | } | |
12232 | } | |
12233 | else | |
12234 | { | |
12235 | enum neon_el_type mod_k_type = k_type; | |
12236 | unsigned mod_k_size = k_size; | |
12237 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); | |
12238 | if (g_type != mod_k_type || g_size != mod_k_size) | |
12239 | { | |
dcbf9037 | 12240 | first_error (_("inconsistent types in Neon instruction")); |
5287ad62 JB |
12241 | return badtype; |
12242 | } | |
12243 | } | |
12244 | } | |
12245 | } | |
12246 | } | |
12247 | ||
12248 | return inst.vectype.el[key_el]; | |
12249 | } | |
12250 | ||
037e8744 | 12251 | /* Neon-style VFP instruction forwarding. */ |
5287ad62 | 12252 | |
037e8744 JB |
12253 | /* Thumb VFP instructions have 0xE in the condition field. */ |
12254 | ||
12255 | static void | |
12256 | do_vfp_cond_or_thumb (void) | |
5287ad62 | 12257 | { |
88714cb8 DG |
12258 | inst.is_neon = 1; |
12259 | ||
5287ad62 | 12260 | if (thumb_mode) |
037e8744 | 12261 | inst.instruction |= 0xe0000000; |
5287ad62 | 12262 | else |
037e8744 | 12263 | inst.instruction |= inst.cond << 28; |
5287ad62 JB |
12264 | } |
12265 | ||
037e8744 JB |
12266 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
12267 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, | |
12268 | etc. It is assumed that operand parsing has already been done, and that the | |
12269 | operands are in the form expected by the given opcode (this isn't necessarily | |
12270 | the same as the form in which they were parsed, hence some massaging must | |
12271 | take place before this function is called). | |
12272 | Checks current arch version against that in the looked-up opcode. */ | |
5287ad62 | 12273 | |
037e8744 JB |
12274 | static void |
12275 | do_vfp_nsyn_opcode (const char *opname) | |
5287ad62 | 12276 | { |
037e8744 | 12277 | const struct asm_opcode *opcode; |
5f4273c7 | 12278 | |
21d799b5 | 12279 | opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname); |
5287ad62 | 12280 | |
037e8744 JB |
12281 | if (!opcode) |
12282 | abort (); | |
5287ad62 | 12283 | |
037e8744 JB |
12284 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
12285 | thumb_mode ? *opcode->tvariant : *opcode->avariant), | |
12286 | _(BAD_FPU)); | |
5287ad62 | 12287 | |
88714cb8 DG |
12288 | inst.is_neon = 1; |
12289 | ||
037e8744 JB |
12290 | if (thumb_mode) |
12291 | { | |
12292 | inst.instruction = opcode->tvalue; | |
12293 | opcode->tencode (); | |
12294 | } | |
12295 | else | |
12296 | { | |
12297 | inst.instruction = (inst.cond << 28) | opcode->avalue; | |
12298 | opcode->aencode (); | |
12299 | } | |
12300 | } | |
5287ad62 JB |
12301 | |
12302 | static void | |
037e8744 | 12303 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
5287ad62 | 12304 | { |
037e8744 JB |
12305 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
12306 | ||
12307 | if (rs == NS_FFF) | |
12308 | { | |
12309 | if (is_add) | |
12310 | do_vfp_nsyn_opcode ("fadds"); | |
12311 | else | |
12312 | do_vfp_nsyn_opcode ("fsubs"); | |
12313 | } | |
12314 | else | |
12315 | { | |
12316 | if (is_add) | |
12317 | do_vfp_nsyn_opcode ("faddd"); | |
12318 | else | |
12319 | do_vfp_nsyn_opcode ("fsubd"); | |
12320 | } | |
12321 | } | |
12322 | ||
12323 | /* Check operand types to see if this is a VFP instruction, and if so call | |
12324 | PFN (). */ | |
12325 | ||
12326 | static int | |
12327 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) | |
12328 | { | |
12329 | enum neon_shape rs; | |
12330 | struct neon_type_el et; | |
12331 | ||
12332 | switch (args) | |
12333 | { | |
12334 | case 2: | |
12335 | rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
12336 | et = neon_check_type (2, rs, | |
12337 | N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
12338 | break; | |
5f4273c7 | 12339 | |
037e8744 JB |
12340 | case 3: |
12341 | rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
12342 | et = neon_check_type (3, rs, | |
12343 | N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
12344 | break; | |
12345 | ||
12346 | default: | |
12347 | abort (); | |
12348 | } | |
12349 | ||
12350 | if (et.type != NT_invtype) | |
12351 | { | |
12352 | pfn (rs); | |
12353 | return SUCCESS; | |
12354 | } | |
037e8744 | 12355 | |
99b253c5 | 12356 | inst.error = NULL; |
037e8744 JB |
12357 | return FAIL; |
12358 | } | |
12359 | ||
12360 | static void | |
12361 | do_vfp_nsyn_mla_mls (enum neon_shape rs) | |
12362 | { | |
12363 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; | |
5f4273c7 | 12364 | |
037e8744 JB |
12365 | if (rs == NS_FFF) |
12366 | { | |
12367 | if (is_mla) | |
12368 | do_vfp_nsyn_opcode ("fmacs"); | |
12369 | else | |
1ee69515 | 12370 | do_vfp_nsyn_opcode ("fnmacs"); |
037e8744 JB |
12371 | } |
12372 | else | |
12373 | { | |
12374 | if (is_mla) | |
12375 | do_vfp_nsyn_opcode ("fmacd"); | |
12376 | else | |
1ee69515 | 12377 | do_vfp_nsyn_opcode ("fnmacd"); |
037e8744 JB |
12378 | } |
12379 | } | |
12380 | ||
62f3b8c8 PB |
12381 | static void |
12382 | do_vfp_nsyn_fma_fms (enum neon_shape rs) | |
12383 | { | |
12384 | int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma; | |
12385 | ||
12386 | if (rs == NS_FFF) | |
12387 | { | |
12388 | if (is_fma) | |
12389 | do_vfp_nsyn_opcode ("ffmas"); | |
12390 | else | |
12391 | do_vfp_nsyn_opcode ("ffnmas"); | |
12392 | } | |
12393 | else | |
12394 | { | |
12395 | if (is_fma) | |
12396 | do_vfp_nsyn_opcode ("ffmad"); | |
12397 | else | |
12398 | do_vfp_nsyn_opcode ("ffnmad"); | |
12399 | } | |
12400 | } | |
12401 | ||
037e8744 JB |
12402 | static void |
12403 | do_vfp_nsyn_mul (enum neon_shape rs) | |
12404 | { | |
12405 | if (rs == NS_FFF) | |
12406 | do_vfp_nsyn_opcode ("fmuls"); | |
12407 | else | |
12408 | do_vfp_nsyn_opcode ("fmuld"); | |
12409 | } | |
12410 | ||
12411 | static void | |
12412 | do_vfp_nsyn_abs_neg (enum neon_shape rs) | |
12413 | { | |
12414 | int is_neg = (inst.instruction & 0x80) != 0; | |
12415 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); | |
12416 | ||
12417 | if (rs == NS_FF) | |
12418 | { | |
12419 | if (is_neg) | |
12420 | do_vfp_nsyn_opcode ("fnegs"); | |
12421 | else | |
12422 | do_vfp_nsyn_opcode ("fabss"); | |
12423 | } | |
12424 | else | |
12425 | { | |
12426 | if (is_neg) | |
12427 | do_vfp_nsyn_opcode ("fnegd"); | |
12428 | else | |
12429 | do_vfp_nsyn_opcode ("fabsd"); | |
12430 | } | |
12431 | } | |
12432 | ||
12433 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision | |
12434 | insns belong to Neon, and are handled elsewhere. */ | |
12435 | ||
12436 | static void | |
12437 | do_vfp_nsyn_ldm_stm (int is_dbmode) | |
12438 | { | |
12439 | int is_ldm = (inst.instruction & (1 << 20)) != 0; | |
12440 | if (is_ldm) | |
12441 | { | |
12442 | if (is_dbmode) | |
12443 | do_vfp_nsyn_opcode ("fldmdbs"); | |
12444 | else | |
12445 | do_vfp_nsyn_opcode ("fldmias"); | |
12446 | } | |
12447 | else | |
12448 | { | |
12449 | if (is_dbmode) | |
12450 | do_vfp_nsyn_opcode ("fstmdbs"); | |
12451 | else | |
12452 | do_vfp_nsyn_opcode ("fstmias"); | |
12453 | } | |
12454 | } | |
12455 | ||
037e8744 JB |
12456 | static void |
12457 | do_vfp_nsyn_sqrt (void) | |
12458 | { | |
12459 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
12460 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12461 | |
037e8744 JB |
12462 | if (rs == NS_FF) |
12463 | do_vfp_nsyn_opcode ("fsqrts"); | |
12464 | else | |
12465 | do_vfp_nsyn_opcode ("fsqrtd"); | |
12466 | } | |
12467 | ||
12468 | static void | |
12469 | do_vfp_nsyn_div (void) | |
12470 | { | |
12471 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
12472 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
12473 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12474 | |
037e8744 JB |
12475 | if (rs == NS_FFF) |
12476 | do_vfp_nsyn_opcode ("fdivs"); | |
12477 | else | |
12478 | do_vfp_nsyn_opcode ("fdivd"); | |
12479 | } | |
12480 | ||
12481 | static void | |
12482 | do_vfp_nsyn_nmul (void) | |
12483 | { | |
12484 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
12485 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
12486 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12487 | |
037e8744 JB |
12488 | if (rs == NS_FFF) |
12489 | { | |
88714cb8 | 12490 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
12491 | do_vfp_sp_dyadic (); |
12492 | } | |
12493 | else | |
12494 | { | |
88714cb8 | 12495 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
12496 | do_vfp_dp_rd_rn_rm (); |
12497 | } | |
12498 | do_vfp_cond_or_thumb (); | |
12499 | } | |
12500 | ||
12501 | static void | |
12502 | do_vfp_nsyn_cmp (void) | |
12503 | { | |
12504 | if (inst.operands[1].isreg) | |
12505 | { | |
12506 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
12507 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12508 | |
037e8744 JB |
12509 | if (rs == NS_FF) |
12510 | { | |
88714cb8 | 12511 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
12512 | do_vfp_sp_monadic (); |
12513 | } | |
12514 | else | |
12515 | { | |
88714cb8 | 12516 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
12517 | do_vfp_dp_rd_rm (); |
12518 | } | |
12519 | } | |
12520 | else | |
12521 | { | |
12522 | enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); | |
12523 | neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); | |
12524 | ||
12525 | switch (inst.instruction & 0x0fffffff) | |
12526 | { | |
12527 | case N_MNEM_vcmp: | |
12528 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; | |
12529 | break; | |
12530 | case N_MNEM_vcmpe: | |
12531 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; | |
12532 | break; | |
12533 | default: | |
12534 | abort (); | |
12535 | } | |
5f4273c7 | 12536 | |
037e8744 JB |
12537 | if (rs == NS_FI) |
12538 | { | |
88714cb8 | 12539 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
12540 | do_vfp_sp_compare_z (); |
12541 | } | |
12542 | else | |
12543 | { | |
88714cb8 | 12544 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
12545 | do_vfp_dp_rd (); |
12546 | } | |
12547 | } | |
12548 | do_vfp_cond_or_thumb (); | |
12549 | } | |
12550 | ||
12551 | static void | |
12552 | nsyn_insert_sp (void) | |
12553 | { | |
12554 | inst.operands[1] = inst.operands[0]; | |
12555 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
fdfde340 | 12556 | inst.operands[0].reg = REG_SP; |
037e8744 JB |
12557 | inst.operands[0].isreg = 1; |
12558 | inst.operands[0].writeback = 1; | |
12559 | inst.operands[0].present = 1; | |
12560 | } | |
12561 | ||
12562 | static void | |
12563 | do_vfp_nsyn_push (void) | |
12564 | { | |
12565 | nsyn_insert_sp (); | |
12566 | if (inst.operands[1].issingle) | |
12567 | do_vfp_nsyn_opcode ("fstmdbs"); | |
12568 | else | |
12569 | do_vfp_nsyn_opcode ("fstmdbd"); | |
12570 | } | |
12571 | ||
12572 | static void | |
12573 | do_vfp_nsyn_pop (void) | |
12574 | { | |
12575 | nsyn_insert_sp (); | |
12576 | if (inst.operands[1].issingle) | |
22b5b651 | 12577 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 | 12578 | else |
22b5b651 | 12579 | do_vfp_nsyn_opcode ("fldmiad"); |
037e8744 JB |
12580 | } |
12581 | ||
12582 | /* Fix up Neon data-processing instructions, ORing in the correct bits for | |
12583 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ | |
12584 | ||
88714cb8 DG |
12585 | static void |
12586 | neon_dp_fixup (struct arm_it* insn) | |
037e8744 | 12587 | { |
88714cb8 DG |
12588 | unsigned int i = insn->instruction; |
12589 | insn->is_neon = 1; | |
12590 | ||
037e8744 JB |
12591 | if (thumb_mode) |
12592 | { | |
12593 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ | |
12594 | if (i & (1 << 24)) | |
12595 | i |= 1 << 28; | |
5f4273c7 | 12596 | |
037e8744 | 12597 | i &= ~(1 << 24); |
5f4273c7 | 12598 | |
037e8744 JB |
12599 | i |= 0xef000000; |
12600 | } | |
12601 | else | |
12602 | i |= 0xf2000000; | |
5f4273c7 | 12603 | |
88714cb8 | 12604 | insn->instruction = i; |
037e8744 JB |
12605 | } |
12606 | ||
12607 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 | |
12608 | (0, 1, 2, 3). */ | |
12609 | ||
12610 | static unsigned | |
12611 | neon_logbits (unsigned x) | |
12612 | { | |
12613 | return ffs (x) - 4; | |
12614 | } | |
12615 | ||
12616 | #define LOW4(R) ((R) & 0xf) | |
12617 | #define HI1(R) (((R) >> 4) & 1) | |
12618 | ||
12619 | /* Encode insns with bit pattern: | |
12620 | ||
12621 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
12622 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | | |
5f4273c7 | 12623 | |
037e8744 JB |
12624 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a |
12625 | different meaning for some instruction. */ | |
12626 | ||
12627 | static void | |
12628 | neon_three_same (int isquad, int ubit, int size) | |
12629 | { | |
12630 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12631 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12632 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
12633 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
12634 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
12635 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
12636 | inst.instruction |= (isquad != 0) << 6; | |
12637 | inst.instruction |= (ubit != 0) << 24; | |
12638 | if (size != -1) | |
12639 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 12640 | |
88714cb8 | 12641 | neon_dp_fixup (&inst); |
037e8744 JB |
12642 | } |
12643 | ||
12644 | /* Encode instructions of the form: | |
12645 | ||
12646 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| | |
12647 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | | |
5287ad62 JB |
12648 | |
12649 | Don't write size if SIZE == -1. */ | |
12650 | ||
12651 | static void | |
12652 | neon_two_same (int qbit, int ubit, int size) | |
12653 | { | |
12654 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12655 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12656 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
12657 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
12658 | inst.instruction |= (qbit != 0) << 6; | |
12659 | inst.instruction |= (ubit != 0) << 24; | |
12660 | ||
12661 | if (size != -1) | |
12662 | inst.instruction |= neon_logbits (size) << 18; | |
12663 | ||
88714cb8 | 12664 | neon_dp_fixup (&inst); |
5287ad62 JB |
12665 | } |
12666 | ||
12667 | /* Neon instruction encoders, in approximate order of appearance. */ | |
12668 | ||
12669 | static void | |
12670 | do_neon_dyadic_i_su (void) | |
12671 | { | |
037e8744 | 12672 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12673 | struct neon_type_el et = neon_check_type (3, rs, |
12674 | N_EQK, N_EQK, N_SU_32 | N_KEY); | |
037e8744 | 12675 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
12676 | } |
12677 | ||
12678 | static void | |
12679 | do_neon_dyadic_i64_su (void) | |
12680 | { | |
037e8744 | 12681 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12682 | struct neon_type_el et = neon_check_type (3, rs, |
12683 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
037e8744 | 12684 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
12685 | } |
12686 | ||
12687 | static void | |
12688 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, | |
12689 | unsigned immbits) | |
12690 | { | |
12691 | unsigned size = et.size >> 3; | |
12692 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12693 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12694 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
12695 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
12696 | inst.instruction |= (isquad != 0) << 6; | |
12697 | inst.instruction |= immbits << 16; | |
12698 | inst.instruction |= (size >> 3) << 7; | |
12699 | inst.instruction |= (size & 0x7) << 19; | |
12700 | if (write_ubit) | |
12701 | inst.instruction |= (uval != 0) << 24; | |
12702 | ||
88714cb8 | 12703 | neon_dp_fixup (&inst); |
5287ad62 JB |
12704 | } |
12705 | ||
12706 | static void | |
12707 | do_neon_shl_imm (void) | |
12708 | { | |
12709 | if (!inst.operands[2].isreg) | |
12710 | { | |
037e8744 | 12711 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 12712 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); |
88714cb8 | 12713 | NEON_ENCODE (IMMED, inst); |
037e8744 | 12714 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); |
5287ad62 JB |
12715 | } |
12716 | else | |
12717 | { | |
037e8744 | 12718 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12719 | struct neon_type_el et = neon_check_type (3, rs, |
12720 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
12721 | unsigned int tmp; |
12722 | ||
12723 | /* VSHL/VQSHL 3-register variants have syntax such as: | |
12724 | vshl.xx Dd, Dm, Dn | |
12725 | whereas other 3-register operations encoded by neon_three_same have | |
12726 | syntax like: | |
12727 | vadd.xx Dd, Dn, Dm | |
12728 | (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg | |
12729 | here. */ | |
12730 | tmp = inst.operands[2].reg; | |
12731 | inst.operands[2].reg = inst.operands[1].reg; | |
12732 | inst.operands[1].reg = tmp; | |
88714cb8 | 12733 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 12734 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
12735 | } |
12736 | } | |
12737 | ||
12738 | static void | |
12739 | do_neon_qshl_imm (void) | |
12740 | { | |
12741 | if (!inst.operands[2].isreg) | |
12742 | { | |
037e8744 | 12743 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 12744 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
627907b7 | 12745 | |
88714cb8 | 12746 | NEON_ENCODE (IMMED, inst); |
037e8744 | 12747 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
12748 | inst.operands[2].imm); |
12749 | } | |
12750 | else | |
12751 | { | |
037e8744 | 12752 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
12753 | struct neon_type_el et = neon_check_type (3, rs, |
12754 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
12755 | unsigned int tmp; |
12756 | ||
12757 | /* See note in do_neon_shl_imm. */ | |
12758 | tmp = inst.operands[2].reg; | |
12759 | inst.operands[2].reg = inst.operands[1].reg; | |
12760 | inst.operands[1].reg = tmp; | |
88714cb8 | 12761 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 12762 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
12763 | } |
12764 | } | |
12765 | ||
627907b7 JB |
12766 | static void |
12767 | do_neon_rshl (void) | |
12768 | { | |
12769 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
12770 | struct neon_type_el et = neon_check_type (3, rs, | |
12771 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
12772 | unsigned int tmp; | |
12773 | ||
12774 | tmp = inst.operands[2].reg; | |
12775 | inst.operands[2].reg = inst.operands[1].reg; | |
12776 | inst.operands[1].reg = tmp; | |
12777 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
12778 | } | |
12779 | ||
5287ad62 JB |
12780 | static int |
12781 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) | |
12782 | { | |
036dc3f7 PB |
12783 | /* Handle .I8 pseudo-instructions. */ |
12784 | if (size == 8) | |
5287ad62 | 12785 | { |
5287ad62 JB |
12786 | /* Unfortunately, this will make everything apart from zero out-of-range. |
12787 | FIXME is this the intended semantics? There doesn't seem much point in | |
12788 | accepting .I8 if so. */ | |
12789 | immediate |= immediate << 8; | |
12790 | size = 16; | |
036dc3f7 PB |
12791 | } |
12792 | ||
12793 | if (size >= 32) | |
12794 | { | |
12795 | if (immediate == (immediate & 0x000000ff)) | |
12796 | { | |
12797 | *immbits = immediate; | |
12798 | return 0x1; | |
12799 | } | |
12800 | else if (immediate == (immediate & 0x0000ff00)) | |
12801 | { | |
12802 | *immbits = immediate >> 8; | |
12803 | return 0x3; | |
12804 | } | |
12805 | else if (immediate == (immediate & 0x00ff0000)) | |
12806 | { | |
12807 | *immbits = immediate >> 16; | |
12808 | return 0x5; | |
12809 | } | |
12810 | else if (immediate == (immediate & 0xff000000)) | |
12811 | { | |
12812 | *immbits = immediate >> 24; | |
12813 | return 0x7; | |
12814 | } | |
12815 | if ((immediate & 0xffff) != (immediate >> 16)) | |
12816 | goto bad_immediate; | |
12817 | immediate &= 0xffff; | |
5287ad62 JB |
12818 | } |
12819 | ||
12820 | if (immediate == (immediate & 0x000000ff)) | |
12821 | { | |
12822 | *immbits = immediate; | |
036dc3f7 | 12823 | return 0x9; |
5287ad62 JB |
12824 | } |
12825 | else if (immediate == (immediate & 0x0000ff00)) | |
12826 | { | |
12827 | *immbits = immediate >> 8; | |
036dc3f7 | 12828 | return 0xb; |
5287ad62 JB |
12829 | } |
12830 | ||
12831 | bad_immediate: | |
dcbf9037 | 12832 | first_error (_("immediate value out of range")); |
5287ad62 JB |
12833 | return FAIL; |
12834 | } | |
12835 | ||
12836 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits | |
12837 | A, B, C, D. */ | |
12838 | ||
12839 | static int | |
12840 | neon_bits_same_in_bytes (unsigned imm) | |
12841 | { | |
12842 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) | |
12843 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) | |
12844 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) | |
12845 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); | |
12846 | } | |
12847 | ||
12848 | /* For immediate of above form, return 0bABCD. */ | |
12849 | ||
12850 | static unsigned | |
12851 | neon_squash_bits (unsigned imm) | |
12852 | { | |
12853 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) | |
12854 | | ((imm & 0x01000000) >> 21); | |
12855 | } | |
12856 | ||
136da414 | 12857 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ |
5287ad62 JB |
12858 | |
12859 | static unsigned | |
12860 | neon_qfloat_bits (unsigned imm) | |
12861 | { | |
136da414 | 12862 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); |
5287ad62 JB |
12863 | } |
12864 | ||
12865 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into | |
12866 | the instruction. *OP is passed as the initial value of the op field, and | |
12867 | may be set to a different value depending on the constant (i.e. | |
12868 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not | |
5f4273c7 | 12869 | MVN). If the immediate looks like a repeated pattern then also |
036dc3f7 | 12870 | try smaller element sizes. */ |
5287ad62 JB |
12871 | |
12872 | static int | |
c96612cc JB |
12873 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, |
12874 | unsigned *immbits, int *op, int size, | |
12875 | enum neon_el_type type) | |
5287ad62 | 12876 | { |
c96612cc JB |
12877 | /* Only permit float immediates (including 0.0/-0.0) if the operand type is |
12878 | float. */ | |
12879 | if (type == NT_float && !float_p) | |
12880 | return FAIL; | |
12881 | ||
136da414 JB |
12882 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) |
12883 | { | |
12884 | if (size != 32 || *op == 1) | |
12885 | return FAIL; | |
12886 | *immbits = neon_qfloat_bits (immlo); | |
12887 | return 0xf; | |
12888 | } | |
036dc3f7 PB |
12889 | |
12890 | if (size == 64) | |
5287ad62 | 12891 | { |
036dc3f7 PB |
12892 | if (neon_bits_same_in_bytes (immhi) |
12893 | && neon_bits_same_in_bytes (immlo)) | |
12894 | { | |
12895 | if (*op == 1) | |
12896 | return FAIL; | |
12897 | *immbits = (neon_squash_bits (immhi) << 4) | |
12898 | | neon_squash_bits (immlo); | |
12899 | *op = 1; | |
12900 | return 0xe; | |
12901 | } | |
12902 | ||
12903 | if (immhi != immlo) | |
12904 | return FAIL; | |
5287ad62 | 12905 | } |
036dc3f7 PB |
12906 | |
12907 | if (size >= 32) | |
5287ad62 | 12908 | { |
036dc3f7 PB |
12909 | if (immlo == (immlo & 0x000000ff)) |
12910 | { | |
12911 | *immbits = immlo; | |
12912 | return 0x0; | |
12913 | } | |
12914 | else if (immlo == (immlo & 0x0000ff00)) | |
12915 | { | |
12916 | *immbits = immlo >> 8; | |
12917 | return 0x2; | |
12918 | } | |
12919 | else if (immlo == (immlo & 0x00ff0000)) | |
12920 | { | |
12921 | *immbits = immlo >> 16; | |
12922 | return 0x4; | |
12923 | } | |
12924 | else if (immlo == (immlo & 0xff000000)) | |
12925 | { | |
12926 | *immbits = immlo >> 24; | |
12927 | return 0x6; | |
12928 | } | |
12929 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) | |
12930 | { | |
12931 | *immbits = (immlo >> 8) & 0xff; | |
12932 | return 0xc; | |
12933 | } | |
12934 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) | |
12935 | { | |
12936 | *immbits = (immlo >> 16) & 0xff; | |
12937 | return 0xd; | |
12938 | } | |
12939 | ||
12940 | if ((immlo & 0xffff) != (immlo >> 16)) | |
12941 | return FAIL; | |
12942 | immlo &= 0xffff; | |
5287ad62 | 12943 | } |
036dc3f7 PB |
12944 | |
12945 | if (size >= 16) | |
5287ad62 | 12946 | { |
036dc3f7 PB |
12947 | if (immlo == (immlo & 0x000000ff)) |
12948 | { | |
12949 | *immbits = immlo; | |
12950 | return 0x8; | |
12951 | } | |
12952 | else if (immlo == (immlo & 0x0000ff00)) | |
12953 | { | |
12954 | *immbits = immlo >> 8; | |
12955 | return 0xa; | |
12956 | } | |
12957 | ||
12958 | if ((immlo & 0xff) != (immlo >> 8)) | |
12959 | return FAIL; | |
12960 | immlo &= 0xff; | |
5287ad62 | 12961 | } |
036dc3f7 PB |
12962 | |
12963 | if (immlo == (immlo & 0x000000ff)) | |
5287ad62 | 12964 | { |
036dc3f7 PB |
12965 | /* Don't allow MVN with 8-bit immediate. */ |
12966 | if (*op == 1) | |
12967 | return FAIL; | |
12968 | *immbits = immlo; | |
12969 | return 0xe; | |
5287ad62 | 12970 | } |
5287ad62 JB |
12971 | |
12972 | return FAIL; | |
12973 | } | |
12974 | ||
12975 | /* Write immediate bits [7:0] to the following locations: | |
12976 | ||
12977 | |28/24|23 19|18 16|15 4|3 0| | |
12978 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| | |
12979 | ||
12980 | This function is used by VMOV/VMVN/VORR/VBIC. */ | |
12981 | ||
12982 | static void | |
12983 | neon_write_immbits (unsigned immbits) | |
12984 | { | |
12985 | inst.instruction |= immbits & 0xf; | |
12986 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; | |
12987 | inst.instruction |= ((immbits >> 7) & 0x1) << 24; | |
12988 | } | |
12989 | ||
12990 | /* Invert low-order SIZE bits of XHI:XLO. */ | |
12991 | ||
12992 | static void | |
12993 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) | |
12994 | { | |
12995 | unsigned immlo = xlo ? *xlo : 0; | |
12996 | unsigned immhi = xhi ? *xhi : 0; | |
12997 | ||
12998 | switch (size) | |
12999 | { | |
13000 | case 8: | |
13001 | immlo = (~immlo) & 0xff; | |
13002 | break; | |
13003 | ||
13004 | case 16: | |
13005 | immlo = (~immlo) & 0xffff; | |
13006 | break; | |
13007 | ||
13008 | case 64: | |
13009 | immhi = (~immhi) & 0xffffffff; | |
13010 | /* fall through. */ | |
13011 | ||
13012 | case 32: | |
13013 | immlo = (~immlo) & 0xffffffff; | |
13014 | break; | |
13015 | ||
13016 | default: | |
13017 | abort (); | |
13018 | } | |
13019 | ||
13020 | if (xlo) | |
13021 | *xlo = immlo; | |
13022 | ||
13023 | if (xhi) | |
13024 | *xhi = immhi; | |
13025 | } | |
13026 | ||
13027 | static void | |
13028 | do_neon_logic (void) | |
13029 | { | |
13030 | if (inst.operands[2].present && inst.operands[2].isreg) | |
13031 | { | |
037e8744 | 13032 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13033 | neon_check_type (3, rs, N_IGNORE_TYPE); |
13034 | /* U bit and size field were set as part of the bitmask. */ | |
88714cb8 | 13035 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13036 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13037 | } |
13038 | else | |
13039 | { | |
4316f0d2 DG |
13040 | const int three_ops_form = (inst.operands[2].present |
13041 | && !inst.operands[2].isreg); | |
13042 | const int immoperand = (three_ops_form ? 2 : 1); | |
13043 | enum neon_shape rs = (three_ops_form | |
13044 | ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL) | |
13045 | : neon_select_shape (NS_DI, NS_QI, NS_NULL)); | |
037e8744 JB |
13046 | struct neon_type_el et = neon_check_type (2, rs, |
13047 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
21d799b5 | 13048 | enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff; |
5287ad62 JB |
13049 | unsigned immbits; |
13050 | int cmode; | |
5f4273c7 | 13051 | |
5287ad62 JB |
13052 | if (et.type == NT_invtype) |
13053 | return; | |
5f4273c7 | 13054 | |
4316f0d2 DG |
13055 | if (three_ops_form) |
13056 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
13057 | _("first and second operands shall be the same register")); | |
13058 | ||
88714cb8 | 13059 | NEON_ENCODE (IMMED, inst); |
5287ad62 | 13060 | |
4316f0d2 | 13061 | immbits = inst.operands[immoperand].imm; |
036dc3f7 PB |
13062 | if (et.size == 64) |
13063 | { | |
13064 | /* .i64 is a pseudo-op, so the immediate must be a repeating | |
13065 | pattern. */ | |
4316f0d2 DG |
13066 | if (immbits != (inst.operands[immoperand].regisimm ? |
13067 | inst.operands[immoperand].reg : 0)) | |
036dc3f7 PB |
13068 | { |
13069 | /* Set immbits to an invalid constant. */ | |
13070 | immbits = 0xdeadbeef; | |
13071 | } | |
13072 | } | |
13073 | ||
5287ad62 JB |
13074 | switch (opcode) |
13075 | { | |
13076 | case N_MNEM_vbic: | |
036dc3f7 | 13077 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 13078 | break; |
5f4273c7 | 13079 | |
5287ad62 | 13080 | case N_MNEM_vorr: |
036dc3f7 | 13081 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 13082 | break; |
5f4273c7 | 13083 | |
5287ad62 JB |
13084 | case N_MNEM_vand: |
13085 | /* Pseudo-instruction for VBIC. */ | |
5287ad62 JB |
13086 | neon_invert_size (&immbits, 0, et.size); |
13087 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
13088 | break; | |
5f4273c7 | 13089 | |
5287ad62 JB |
13090 | case N_MNEM_vorn: |
13091 | /* Pseudo-instruction for VORR. */ | |
5287ad62 JB |
13092 | neon_invert_size (&immbits, 0, et.size); |
13093 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
13094 | break; | |
5f4273c7 | 13095 | |
5287ad62 JB |
13096 | default: |
13097 | abort (); | |
13098 | } | |
13099 | ||
13100 | if (cmode == FAIL) | |
13101 | return; | |
13102 | ||
037e8744 | 13103 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13104 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13105 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13106 | inst.instruction |= cmode << 8; | |
13107 | neon_write_immbits (immbits); | |
5f4273c7 | 13108 | |
88714cb8 | 13109 | neon_dp_fixup (&inst); |
5287ad62 JB |
13110 | } |
13111 | } | |
13112 | ||
13113 | static void | |
13114 | do_neon_bitfield (void) | |
13115 | { | |
037e8744 | 13116 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 13117 | neon_check_type (3, rs, N_IGNORE_TYPE); |
037e8744 | 13118 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13119 | } |
13120 | ||
13121 | static void | |
dcbf9037 JB |
13122 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
13123 | unsigned destbits) | |
5287ad62 | 13124 | { |
037e8744 | 13125 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 JB |
13126 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
13127 | types | N_KEY); | |
5287ad62 JB |
13128 | if (et.type == NT_float) |
13129 | { | |
88714cb8 | 13130 | NEON_ENCODE (FLOAT, inst); |
037e8744 | 13131 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13132 | } |
13133 | else | |
13134 | { | |
88714cb8 | 13135 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13136 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); |
5287ad62 JB |
13137 | } |
13138 | } | |
13139 | ||
13140 | static void | |
13141 | do_neon_dyadic_if_su (void) | |
13142 | { | |
dcbf9037 | 13143 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
13144 | } |
13145 | ||
13146 | static void | |
13147 | do_neon_dyadic_if_su_d (void) | |
13148 | { | |
13149 | /* This version only allow D registers, but that constraint is enforced during | |
13150 | operand parsing so we don't need to do anything extra here. */ | |
dcbf9037 | 13151 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
13152 | } |
13153 | ||
5287ad62 JB |
13154 | static void |
13155 | do_neon_dyadic_if_i_d (void) | |
13156 | { | |
428e3f1f PB |
13157 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
13158 | affected if we specify unsigned args. */ | |
13159 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
5287ad62 JB |
13160 | } |
13161 | ||
037e8744 JB |
13162 | enum vfp_or_neon_is_neon_bits |
13163 | { | |
13164 | NEON_CHECK_CC = 1, | |
13165 | NEON_CHECK_ARCH = 2 | |
13166 | }; | |
13167 | ||
13168 | /* Call this function if an instruction which may have belonged to the VFP or | |
13169 | Neon instruction sets, but turned out to be a Neon instruction (due to the | |
13170 | operand types involved, etc.). We have to check and/or fix-up a couple of | |
13171 | things: | |
13172 | ||
13173 | - Make sure the user hasn't attempted to make a Neon instruction | |
13174 | conditional. | |
13175 | - Alter the value in the condition code field if necessary. | |
13176 | - Make sure that the arch supports Neon instructions. | |
13177 | ||
13178 | Which of these operations take place depends on bits from enum | |
13179 | vfp_or_neon_is_neon_bits. | |
13180 | ||
13181 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the | |
13182 | current instruction's condition is COND_ALWAYS, the condition field is | |
13183 | changed to inst.uncond_value. This is necessary because instructions shared | |
13184 | between VFP and Neon may be conditional for the VFP variants only, and the | |
13185 | unconditional Neon version must have, e.g., 0xF in the condition field. */ | |
13186 | ||
13187 | static int | |
13188 | vfp_or_neon_is_neon (unsigned check) | |
13189 | { | |
13190 | /* Conditions are always legal in Thumb mode (IT blocks). */ | |
13191 | if (!thumb_mode && (check & NEON_CHECK_CC)) | |
13192 | { | |
13193 | if (inst.cond != COND_ALWAYS) | |
13194 | { | |
13195 | first_error (_(BAD_COND)); | |
13196 | return FAIL; | |
13197 | } | |
13198 | if (inst.uncond_value != -1) | |
13199 | inst.instruction |= inst.uncond_value << 28; | |
13200 | } | |
5f4273c7 | 13201 | |
037e8744 JB |
13202 | if ((check & NEON_CHECK_ARCH) |
13203 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) | |
13204 | { | |
13205 | first_error (_(BAD_FPU)); | |
13206 | return FAIL; | |
13207 | } | |
5f4273c7 | 13208 | |
037e8744 JB |
13209 | return SUCCESS; |
13210 | } | |
13211 | ||
5287ad62 JB |
13212 | static void |
13213 | do_neon_addsub_if_i (void) | |
13214 | { | |
037e8744 JB |
13215 | if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) |
13216 | return; | |
13217 | ||
13218 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13219 | return; | |
13220 | ||
5287ad62 JB |
13221 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
13222 | affected if we specify unsigned args. */ | |
dcbf9037 | 13223 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
5287ad62 JB |
13224 | } |
13225 | ||
13226 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the | |
13227 | result to be: | |
13228 | V<op> A,B (A is operand 0, B is operand 2) | |
13229 | to mean: | |
13230 | V<op> A,B,A | |
13231 | not: | |
13232 | V<op> A,B,B | |
13233 | so handle that case specially. */ | |
13234 | ||
13235 | static void | |
13236 | neon_exchange_operands (void) | |
13237 | { | |
13238 | void *scratch = alloca (sizeof (inst.operands[0])); | |
13239 | if (inst.operands[1].present) | |
13240 | { | |
13241 | /* Swap operands[1] and operands[2]. */ | |
13242 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); | |
13243 | inst.operands[1] = inst.operands[2]; | |
13244 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); | |
13245 | } | |
13246 | else | |
13247 | { | |
13248 | inst.operands[1] = inst.operands[2]; | |
13249 | inst.operands[2] = inst.operands[0]; | |
13250 | } | |
13251 | } | |
13252 | ||
13253 | static void | |
13254 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) | |
13255 | { | |
13256 | if (inst.operands[2].isreg) | |
13257 | { | |
13258 | if (invert) | |
13259 | neon_exchange_operands (); | |
dcbf9037 | 13260 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
5287ad62 JB |
13261 | } |
13262 | else | |
13263 | { | |
037e8744 | 13264 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
dcbf9037 JB |
13265 | struct neon_type_el et = neon_check_type (2, rs, |
13266 | N_EQK | N_SIZ, immtypes | N_KEY); | |
5287ad62 | 13267 | |
88714cb8 | 13268 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
13269 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13270 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13271 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13272 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 13273 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13274 | inst.instruction |= (et.type == NT_float) << 10; |
13275 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 13276 | |
88714cb8 | 13277 | neon_dp_fixup (&inst); |
5287ad62 JB |
13278 | } |
13279 | } | |
13280 | ||
13281 | static void | |
13282 | do_neon_cmp (void) | |
13283 | { | |
13284 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); | |
13285 | } | |
13286 | ||
13287 | static void | |
13288 | do_neon_cmp_inv (void) | |
13289 | { | |
13290 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); | |
13291 | } | |
13292 | ||
13293 | static void | |
13294 | do_neon_ceq (void) | |
13295 | { | |
13296 | neon_compare (N_IF_32, N_IF_32, FALSE); | |
13297 | } | |
13298 | ||
13299 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit | |
13300 | scalars, which are encoded in 5 bits, M : Rm. | |
13301 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in | |
13302 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the | |
13303 | index in M. */ | |
13304 | ||
13305 | static unsigned | |
13306 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) | |
13307 | { | |
dcbf9037 JB |
13308 | unsigned regno = NEON_SCALAR_REG (scalar); |
13309 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
5287ad62 JB |
13310 | |
13311 | switch (elsize) | |
13312 | { | |
13313 | case 16: | |
13314 | if (regno > 7 || elno > 3) | |
13315 | goto bad_scalar; | |
13316 | return regno | (elno << 3); | |
5f4273c7 | 13317 | |
5287ad62 JB |
13318 | case 32: |
13319 | if (regno > 15 || elno > 1) | |
13320 | goto bad_scalar; | |
13321 | return regno | (elno << 4); | |
13322 | ||
13323 | default: | |
13324 | bad_scalar: | |
dcbf9037 | 13325 | first_error (_("scalar out of range for multiply instruction")); |
5287ad62 JB |
13326 | } |
13327 | ||
13328 | return 0; | |
13329 | } | |
13330 | ||
13331 | /* Encode multiply / multiply-accumulate scalar instructions. */ | |
13332 | ||
13333 | static void | |
13334 | neon_mul_mac (struct neon_type_el et, int ubit) | |
13335 | { | |
dcbf9037 JB |
13336 | unsigned scalar; |
13337 | ||
13338 | /* Give a more helpful error message if we have an invalid type. */ | |
13339 | if (et.type == NT_invtype) | |
13340 | return; | |
5f4273c7 | 13341 | |
dcbf9037 | 13342 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); |
5287ad62 JB |
13343 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13344 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13345 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
13346 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
13347 | inst.instruction |= LOW4 (scalar); | |
13348 | inst.instruction |= HI1 (scalar) << 5; | |
13349 | inst.instruction |= (et.type == NT_float) << 8; | |
13350 | inst.instruction |= neon_logbits (et.size) << 20; | |
13351 | inst.instruction |= (ubit != 0) << 24; | |
13352 | ||
88714cb8 | 13353 | neon_dp_fixup (&inst); |
5287ad62 JB |
13354 | } |
13355 | ||
13356 | static void | |
13357 | do_neon_mac_maybe_scalar (void) | |
13358 | { | |
037e8744 JB |
13359 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
13360 | return; | |
13361 | ||
13362 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13363 | return; | |
13364 | ||
5287ad62 JB |
13365 | if (inst.operands[2].isscalar) |
13366 | { | |
037e8744 | 13367 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
13368 | struct neon_type_el et = neon_check_type (3, rs, |
13369 | N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); | |
88714cb8 | 13370 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 13371 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
13372 | } |
13373 | else | |
428e3f1f PB |
13374 | { |
13375 | /* The "untyped" case can't happen. Do this to stop the "U" bit being | |
13376 | affected if we specify unsigned args. */ | |
13377 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
13378 | } | |
5287ad62 JB |
13379 | } |
13380 | ||
62f3b8c8 PB |
13381 | static void |
13382 | do_neon_fmac (void) | |
13383 | { | |
13384 | if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS) | |
13385 | return; | |
13386 | ||
13387 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13388 | return; | |
13389 | ||
13390 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
13391 | } | |
13392 | ||
5287ad62 JB |
13393 | static void |
13394 | do_neon_tst (void) | |
13395 | { | |
037e8744 | 13396 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13397 | struct neon_type_el et = neon_check_type (3, rs, |
13398 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
037e8744 | 13399 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
13400 | } |
13401 | ||
13402 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the | |
13403 | same types as the MAC equivalents. The polynomial type for this instruction | |
13404 | is encoded the same as the integer type. */ | |
13405 | ||
13406 | static void | |
13407 | do_neon_mul (void) | |
13408 | { | |
037e8744 JB |
13409 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
13410 | return; | |
13411 | ||
13412 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13413 | return; | |
13414 | ||
5287ad62 JB |
13415 | if (inst.operands[2].isscalar) |
13416 | do_neon_mac_maybe_scalar (); | |
13417 | else | |
dcbf9037 | 13418 | neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); |
5287ad62 JB |
13419 | } |
13420 | ||
13421 | static void | |
13422 | do_neon_qdmulh (void) | |
13423 | { | |
13424 | if (inst.operands[2].isscalar) | |
13425 | { | |
037e8744 | 13426 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
13427 | struct neon_type_el et = neon_check_type (3, rs, |
13428 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
88714cb8 | 13429 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 13430 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
13431 | } |
13432 | else | |
13433 | { | |
037e8744 | 13434 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13435 | struct neon_type_el et = neon_check_type (3, rs, |
13436 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
88714cb8 | 13437 | NEON_ENCODE (INTEGER, inst); |
5287ad62 | 13438 | /* The U bit (rounding) comes from bit mask. */ |
037e8744 | 13439 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
13440 | } |
13441 | } | |
13442 | ||
13443 | static void | |
13444 | do_neon_fcmp_absolute (void) | |
13445 | { | |
037e8744 | 13446 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13447 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
13448 | /* Size field comes from bit mask. */ | |
037e8744 | 13449 | neon_three_same (neon_quad (rs), 1, -1); |
5287ad62 JB |
13450 | } |
13451 | ||
13452 | static void | |
13453 | do_neon_fcmp_absolute_inv (void) | |
13454 | { | |
13455 | neon_exchange_operands (); | |
13456 | do_neon_fcmp_absolute (); | |
13457 | } | |
13458 | ||
13459 | static void | |
13460 | do_neon_step (void) | |
13461 | { | |
037e8744 | 13462 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 13463 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
037e8744 | 13464 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13465 | } |
13466 | ||
13467 | static void | |
13468 | do_neon_abs_neg (void) | |
13469 | { | |
037e8744 JB |
13470 | enum neon_shape rs; |
13471 | struct neon_type_el et; | |
5f4273c7 | 13472 | |
037e8744 JB |
13473 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) |
13474 | return; | |
13475 | ||
13476 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13477 | return; | |
13478 | ||
13479 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
13480 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); | |
5f4273c7 | 13481 | |
5287ad62 JB |
13482 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13483 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13484 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13485 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 13486 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13487 | inst.instruction |= (et.type == NT_float) << 10; |
13488 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 13489 | |
88714cb8 | 13490 | neon_dp_fixup (&inst); |
5287ad62 JB |
13491 | } |
13492 | ||
13493 | static void | |
13494 | do_neon_sli (void) | |
13495 | { | |
037e8744 | 13496 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
13497 | struct neon_type_el et = neon_check_type (2, rs, |
13498 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
13499 | int imm = inst.operands[2].imm; | |
13500 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
13501 | _("immediate out of range for insert")); | |
037e8744 | 13502 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
13503 | } |
13504 | ||
13505 | static void | |
13506 | do_neon_sri (void) | |
13507 | { | |
037e8744 | 13508 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
13509 | struct neon_type_el et = neon_check_type (2, rs, |
13510 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
13511 | int imm = inst.operands[2].imm; | |
13512 | constraint (imm < 1 || (unsigned)imm > et.size, | |
13513 | _("immediate out of range for insert")); | |
037e8744 | 13514 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
5287ad62 JB |
13515 | } |
13516 | ||
13517 | static void | |
13518 | do_neon_qshlu_imm (void) | |
13519 | { | |
037e8744 | 13520 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
13521 | struct neon_type_el et = neon_check_type (2, rs, |
13522 | N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); | |
13523 | int imm = inst.operands[2].imm; | |
13524 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
13525 | _("immediate out of range for shift")); | |
13526 | /* Only encodes the 'U present' variant of the instruction. | |
13527 | In this case, signed types have OP (bit 8) set to 0. | |
13528 | Unsigned types have OP set to 1. */ | |
13529 | inst.instruction |= (et.type == NT_unsigned) << 8; | |
13530 | /* The rest of the bits are the same as other immediate shifts. */ | |
037e8744 | 13531 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
13532 | } |
13533 | ||
13534 | static void | |
13535 | do_neon_qmovn (void) | |
13536 | { | |
13537 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
13538 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
13539 | /* Saturating move where operands can be signed or unsigned, and the | |
13540 | destination has the same signedness. */ | |
88714cb8 | 13541 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13542 | if (et.type == NT_unsigned) |
13543 | inst.instruction |= 0xc0; | |
13544 | else | |
13545 | inst.instruction |= 0x80; | |
13546 | neon_two_same (0, 1, et.size / 2); | |
13547 | } | |
13548 | ||
13549 | static void | |
13550 | do_neon_qmovun (void) | |
13551 | { | |
13552 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
13553 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
13554 | /* Saturating move with unsigned results. Operands must be signed. */ | |
88714cb8 | 13555 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13556 | neon_two_same (0, 1, et.size / 2); |
13557 | } | |
13558 | ||
13559 | static void | |
13560 | do_neon_rshift_sat_narrow (void) | |
13561 | { | |
13562 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
13563 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
13564 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
13565 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
13566 | int imm = inst.operands[2].imm; | |
13567 | /* This gets the bounds check, size encoding and immediate bits calculation | |
13568 | right. */ | |
13569 | et.size /= 2; | |
5f4273c7 | 13570 | |
5287ad62 JB |
13571 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for |
13572 | VQMOVN.I<size> <Dd>, <Qm>. */ | |
13573 | if (imm == 0) | |
13574 | { | |
13575 | inst.operands[2].present = 0; | |
13576 | inst.instruction = N_MNEM_vqmovn; | |
13577 | do_neon_qmovn (); | |
13578 | return; | |
13579 | } | |
5f4273c7 | 13580 | |
5287ad62 JB |
13581 | constraint (imm < 1 || (unsigned)imm > et.size, |
13582 | _("immediate out of range")); | |
13583 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); | |
13584 | } | |
13585 | ||
13586 | static void | |
13587 | do_neon_rshift_sat_narrow_u (void) | |
13588 | { | |
13589 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
13590 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
13591 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
13592 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
13593 | int imm = inst.operands[2].imm; | |
13594 | /* This gets the bounds check, size encoding and immediate bits calculation | |
13595 | right. */ | |
13596 | et.size /= 2; | |
13597 | ||
13598 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
13599 | VQMOVUN.I<size> <Dd>, <Qm>. */ | |
13600 | if (imm == 0) | |
13601 | { | |
13602 | inst.operands[2].present = 0; | |
13603 | inst.instruction = N_MNEM_vqmovun; | |
13604 | do_neon_qmovun (); | |
13605 | return; | |
13606 | } | |
13607 | ||
13608 | constraint (imm < 1 || (unsigned)imm > et.size, | |
13609 | _("immediate out of range")); | |
13610 | /* FIXME: The manual is kind of unclear about what value U should have in | |
13611 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it | |
13612 | must be 1. */ | |
13613 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); | |
13614 | } | |
13615 | ||
13616 | static void | |
13617 | do_neon_movn (void) | |
13618 | { | |
13619 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
13620 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
88714cb8 | 13621 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13622 | neon_two_same (0, 1, et.size / 2); |
13623 | } | |
13624 | ||
13625 | static void | |
13626 | do_neon_rshift_narrow (void) | |
13627 | { | |
13628 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
13629 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
13630 | int imm = inst.operands[2].imm; | |
13631 | /* This gets the bounds check, size encoding and immediate bits calculation | |
13632 | right. */ | |
13633 | et.size /= 2; | |
5f4273c7 | 13634 | |
5287ad62 JB |
13635 | /* If immediate is zero then we are a pseudo-instruction for |
13636 | VMOVN.I<size> <Dd>, <Qm> */ | |
13637 | if (imm == 0) | |
13638 | { | |
13639 | inst.operands[2].present = 0; | |
13640 | inst.instruction = N_MNEM_vmovn; | |
13641 | do_neon_movn (); | |
13642 | return; | |
13643 | } | |
5f4273c7 | 13644 | |
5287ad62 JB |
13645 | constraint (imm < 1 || (unsigned)imm > et.size, |
13646 | _("immediate out of range for narrowing operation")); | |
13647 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); | |
13648 | } | |
13649 | ||
13650 | static void | |
13651 | do_neon_shll (void) | |
13652 | { | |
13653 | /* FIXME: Type checking when lengthening. */ | |
13654 | struct neon_type_el et = neon_check_type (2, NS_QDI, | |
13655 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); | |
13656 | unsigned imm = inst.operands[2].imm; | |
13657 | ||
13658 | if (imm == et.size) | |
13659 | { | |
13660 | /* Maximum shift variant. */ | |
88714cb8 | 13661 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13662 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13663 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13664 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13665 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13666 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 13667 | |
88714cb8 | 13668 | neon_dp_fixup (&inst); |
5287ad62 JB |
13669 | } |
13670 | else | |
13671 | { | |
13672 | /* A more-specific type check for non-max versions. */ | |
13673 | et = neon_check_type (2, NS_QDI, | |
13674 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
88714cb8 | 13675 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
13676 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); |
13677 | } | |
13678 | } | |
13679 | ||
037e8744 | 13680 | /* Check the various types for the VCVT instruction, and return which version |
5287ad62 JB |
13681 | the current instruction is. */ |
13682 | ||
13683 | static int | |
13684 | neon_cvt_flavour (enum neon_shape rs) | |
13685 | { | |
037e8744 JB |
13686 | #define CVT_VAR(C,X,Y) \ |
13687 | et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ | |
13688 | if (et.type != NT_invtype) \ | |
13689 | { \ | |
13690 | inst.error = NULL; \ | |
13691 | return (C); \ | |
5287ad62 JB |
13692 | } |
13693 | struct neon_type_el et; | |
037e8744 JB |
13694 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
13695 | || rs == NS_FF) ? N_VFP : 0; | |
13696 | /* The instruction versions which take an immediate take one register | |
13697 | argument, which is extended to the width of the full register. Thus the | |
13698 | "source" and "destination" registers must have the same width. Hack that | |
13699 | here by making the size equal to the key (wider, in this case) operand. */ | |
13700 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; | |
5f4273c7 | 13701 | |
5287ad62 JB |
13702 | CVT_VAR (0, N_S32, N_F32); |
13703 | CVT_VAR (1, N_U32, N_F32); | |
13704 | CVT_VAR (2, N_F32, N_S32); | |
13705 | CVT_VAR (3, N_F32, N_U32); | |
8e79c3df CM |
13706 | /* Half-precision conversions. */ |
13707 | CVT_VAR (4, N_F32, N_F16); | |
13708 | CVT_VAR (5, N_F16, N_F32); | |
5f4273c7 | 13709 | |
037e8744 | 13710 | whole_reg = N_VFP; |
5f4273c7 | 13711 | |
037e8744 | 13712 | /* VFP instructions. */ |
8e79c3df CM |
13713 | CVT_VAR (6, N_F32, N_F64); |
13714 | CVT_VAR (7, N_F64, N_F32); | |
13715 | CVT_VAR (8, N_S32, N_F64 | key); | |
13716 | CVT_VAR (9, N_U32, N_F64 | key); | |
13717 | CVT_VAR (10, N_F64 | key, N_S32); | |
13718 | CVT_VAR (11, N_F64 | key, N_U32); | |
037e8744 | 13719 | /* VFP instructions with bitshift. */ |
8e79c3df CM |
13720 | CVT_VAR (12, N_F32 | key, N_S16); |
13721 | CVT_VAR (13, N_F32 | key, N_U16); | |
13722 | CVT_VAR (14, N_F64 | key, N_S16); | |
13723 | CVT_VAR (15, N_F64 | key, N_U16); | |
13724 | CVT_VAR (16, N_S16, N_F32 | key); | |
13725 | CVT_VAR (17, N_U16, N_F32 | key); | |
13726 | CVT_VAR (18, N_S16, N_F64 | key); | |
13727 | CVT_VAR (19, N_U16, N_F64 | key); | |
5f4273c7 | 13728 | |
5287ad62 JB |
13729 | return -1; |
13730 | #undef CVT_VAR | |
13731 | } | |
13732 | ||
037e8744 JB |
13733 | /* Neon-syntax VFP conversions. */ |
13734 | ||
5287ad62 | 13735 | static void |
037e8744 | 13736 | do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) |
5287ad62 | 13737 | { |
037e8744 | 13738 | const char *opname = 0; |
5f4273c7 | 13739 | |
037e8744 | 13740 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) |
5287ad62 | 13741 | { |
037e8744 JB |
13742 | /* Conversions with immediate bitshift. */ |
13743 | const char *enc[] = | |
13744 | { | |
13745 | "ftosls", | |
13746 | "ftouls", | |
13747 | "fsltos", | |
13748 | "fultos", | |
13749 | NULL, | |
13750 | NULL, | |
8e79c3df CM |
13751 | NULL, |
13752 | NULL, | |
037e8744 JB |
13753 | "ftosld", |
13754 | "ftould", | |
13755 | "fsltod", | |
13756 | "fultod", | |
13757 | "fshtos", | |
13758 | "fuhtos", | |
13759 | "fshtod", | |
13760 | "fuhtod", | |
13761 | "ftoshs", | |
13762 | "ftouhs", | |
13763 | "ftoshd", | |
13764 | "ftouhd" | |
13765 | }; | |
13766 | ||
13767 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
13768 | { | |
13769 | opname = enc[flavour]; | |
13770 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
13771 | _("operands 0 and 1 must be the same register")); | |
13772 | inst.operands[1] = inst.operands[2]; | |
13773 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); | |
13774 | } | |
5287ad62 JB |
13775 | } |
13776 | else | |
13777 | { | |
037e8744 JB |
13778 | /* Conversions without bitshift. */ |
13779 | const char *enc[] = | |
13780 | { | |
13781 | "ftosis", | |
13782 | "ftouis", | |
13783 | "fsitos", | |
13784 | "fuitos", | |
8e79c3df CM |
13785 | "NULL", |
13786 | "NULL", | |
037e8744 JB |
13787 | "fcvtsd", |
13788 | "fcvtds", | |
13789 | "ftosid", | |
13790 | "ftouid", | |
13791 | "fsitod", | |
13792 | "fuitod" | |
13793 | }; | |
13794 | ||
13795 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
13796 | opname = enc[flavour]; | |
13797 | } | |
13798 | ||
13799 | if (opname) | |
13800 | do_vfp_nsyn_opcode (opname); | |
13801 | } | |
13802 | ||
13803 | static void | |
13804 | do_vfp_nsyn_cvtz (void) | |
13805 | { | |
13806 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); | |
13807 | int flavour = neon_cvt_flavour (rs); | |
13808 | const char *enc[] = | |
13809 | { | |
13810 | "ftosizs", | |
13811 | "ftouizs", | |
13812 | NULL, | |
13813 | NULL, | |
13814 | NULL, | |
13815 | NULL, | |
8e79c3df CM |
13816 | NULL, |
13817 | NULL, | |
037e8744 JB |
13818 | "ftosizd", |
13819 | "ftouizd" | |
13820 | }; | |
13821 | ||
13822 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) | |
13823 | do_vfp_nsyn_opcode (enc[flavour]); | |
13824 | } | |
f31fef98 | 13825 | |
037e8744 | 13826 | static void |
e3e535bc | 13827 | do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED) |
037e8744 JB |
13828 | { |
13829 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, | |
8e79c3df | 13830 | NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL); |
037e8744 JB |
13831 | int flavour = neon_cvt_flavour (rs); |
13832 | ||
e3e535bc NC |
13833 | /* PR11109: Handle round-to-zero for VCVT conversions. */ |
13834 | if (round_to_zero | |
13835 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2) | |
13836 | && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9) | |
13837 | && (rs == NS_FD || rs == NS_FF)) | |
13838 | { | |
13839 | do_vfp_nsyn_cvtz (); | |
13840 | return; | |
13841 | } | |
13842 | ||
037e8744 | 13843 | /* VFP rather than Neon conversions. */ |
8e79c3df | 13844 | if (flavour >= 6) |
037e8744 JB |
13845 | { |
13846 | do_vfp_nsyn_cvt (rs, flavour); | |
13847 | return; | |
13848 | } | |
13849 | ||
13850 | switch (rs) | |
13851 | { | |
13852 | case NS_DDI: | |
13853 | case NS_QQI: | |
13854 | { | |
35997600 NC |
13855 | unsigned immbits; |
13856 | unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; | |
13857 | ||
037e8744 JB |
13858 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
13859 | return; | |
13860 | ||
13861 | /* Fixed-point conversion with #0 immediate is encoded as an | |
13862 | integer conversion. */ | |
13863 | if (inst.operands[2].present && inst.operands[2].imm == 0) | |
13864 | goto int_encode; | |
35997600 | 13865 | immbits = 32 - inst.operands[2].imm; |
88714cb8 | 13866 | NEON_ENCODE (IMMED, inst); |
037e8744 JB |
13867 | if (flavour != -1) |
13868 | inst.instruction |= enctab[flavour]; | |
13869 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13870 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13871 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13872 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13873 | inst.instruction |= neon_quad (rs) << 6; | |
13874 | inst.instruction |= 1 << 21; | |
13875 | inst.instruction |= immbits << 16; | |
13876 | ||
88714cb8 | 13877 | neon_dp_fixup (&inst); |
037e8744 JB |
13878 | } |
13879 | break; | |
13880 | ||
13881 | case NS_DD: | |
13882 | case NS_QQ: | |
13883 | int_encode: | |
13884 | { | |
13885 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; | |
13886 | ||
88714cb8 | 13887 | NEON_ENCODE (INTEGER, inst); |
037e8744 JB |
13888 | |
13889 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13890 | return; | |
13891 | ||
13892 | if (flavour != -1) | |
13893 | inst.instruction |= enctab[flavour]; | |
13894 | ||
13895 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13896 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13897 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13898 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13899 | inst.instruction |= neon_quad (rs) << 6; | |
13900 | inst.instruction |= 2 << 18; | |
13901 | ||
88714cb8 | 13902 | neon_dp_fixup (&inst); |
037e8744 JB |
13903 | } |
13904 | break; | |
13905 | ||
8e79c3df CM |
13906 | /* Half-precision conversions for Advanced SIMD -- neon. */ |
13907 | case NS_QD: | |
13908 | case NS_DQ: | |
13909 | ||
13910 | if ((rs == NS_DQ) | |
13911 | && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) | |
13912 | { | |
13913 | as_bad (_("operand size must match register width")); | |
13914 | break; | |
13915 | } | |
13916 | ||
13917 | if ((rs == NS_QD) | |
13918 | && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) | |
13919 | { | |
13920 | as_bad (_("operand size must match register width")); | |
13921 | break; | |
13922 | } | |
13923 | ||
13924 | if (rs == NS_DQ) | |
13925 | inst.instruction = 0x3b60600; | |
13926 | else | |
13927 | inst.instruction = 0x3b60700; | |
13928 | ||
13929 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13930 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13931 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13932 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
88714cb8 | 13933 | neon_dp_fixup (&inst); |
8e79c3df CM |
13934 | break; |
13935 | ||
037e8744 JB |
13936 | default: |
13937 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ | |
13938 | do_vfp_nsyn_cvt (rs, flavour); | |
5287ad62 | 13939 | } |
5287ad62 JB |
13940 | } |
13941 | ||
e3e535bc NC |
13942 | static void |
13943 | do_neon_cvtr (void) | |
13944 | { | |
13945 | do_neon_cvt_1 (FALSE); | |
13946 | } | |
13947 | ||
13948 | static void | |
13949 | do_neon_cvt (void) | |
13950 | { | |
13951 | do_neon_cvt_1 (TRUE); | |
13952 | } | |
13953 | ||
8e79c3df CM |
13954 | static void |
13955 | do_neon_cvtb (void) | |
13956 | { | |
13957 | inst.instruction = 0xeb20a40; | |
13958 | ||
13959 | /* The sizes are attached to the mnemonic. */ | |
13960 | if (inst.vectype.el[0].type != NT_invtype | |
13961 | && inst.vectype.el[0].size == 16) | |
13962 | inst.instruction |= 0x00010000; | |
13963 | ||
13964 | /* Programmer's syntax: the sizes are attached to the operands. */ | |
13965 | else if (inst.operands[0].vectype.type != NT_invtype | |
13966 | && inst.operands[0].vectype.size == 16) | |
13967 | inst.instruction |= 0x00010000; | |
13968 | ||
13969 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
13970 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
13971 | do_vfp_cond_or_thumb (); | |
13972 | } | |
13973 | ||
13974 | ||
13975 | static void | |
13976 | do_neon_cvtt (void) | |
13977 | { | |
13978 | do_neon_cvtb (); | |
13979 | inst.instruction |= 0x80; | |
13980 | } | |
13981 | ||
5287ad62 JB |
13982 | static void |
13983 | neon_move_immediate (void) | |
13984 | { | |
037e8744 JB |
13985 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
13986 | struct neon_type_el et = neon_check_type (2, rs, | |
13987 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 | 13988 | unsigned immlo, immhi = 0, immbits; |
c96612cc | 13989 | int op, cmode, float_p; |
5287ad62 | 13990 | |
037e8744 JB |
13991 | constraint (et.type == NT_invtype, |
13992 | _("operand size must be specified for immediate VMOV")); | |
13993 | ||
5287ad62 JB |
13994 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
13995 | op = (inst.instruction & (1 << 5)) != 0; | |
13996 | ||
13997 | immlo = inst.operands[1].imm; | |
13998 | if (inst.operands[1].regisimm) | |
13999 | immhi = inst.operands[1].reg; | |
14000 | ||
14001 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, | |
14002 | _("immediate has bits set outside the operand size")); | |
14003 | ||
c96612cc JB |
14004 | float_p = inst.operands[1].immisfloat; |
14005 | ||
14006 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, | |
136da414 | 14007 | et.size, et.type)) == FAIL) |
5287ad62 JB |
14008 | { |
14009 | /* Invert relevant bits only. */ | |
14010 | neon_invert_size (&immlo, &immhi, et.size); | |
14011 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable | |
14012 | with one or the other; those cases are caught by | |
14013 | neon_cmode_for_move_imm. */ | |
14014 | op = !op; | |
c96612cc JB |
14015 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, |
14016 | &op, et.size, et.type)) == FAIL) | |
5287ad62 | 14017 | { |
dcbf9037 | 14018 | first_error (_("immediate out of range")); |
5287ad62 JB |
14019 | return; |
14020 | } | |
14021 | } | |
14022 | ||
14023 | inst.instruction &= ~(1 << 5); | |
14024 | inst.instruction |= op << 5; | |
14025 | ||
14026 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14027 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
037e8744 | 14028 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14029 | inst.instruction |= cmode << 8; |
14030 | ||
14031 | neon_write_immbits (immbits); | |
14032 | } | |
14033 | ||
14034 | static void | |
14035 | do_neon_mvn (void) | |
14036 | { | |
14037 | if (inst.operands[1].isreg) | |
14038 | { | |
037e8744 | 14039 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5f4273c7 | 14040 | |
88714cb8 | 14041 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14042 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14043 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14044 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14045 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14046 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14047 | } |
14048 | else | |
14049 | { | |
88714cb8 | 14050 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14051 | neon_move_immediate (); |
14052 | } | |
14053 | ||
88714cb8 | 14054 | neon_dp_fixup (&inst); |
5287ad62 JB |
14055 | } |
14056 | ||
14057 | /* Encode instructions of form: | |
14058 | ||
14059 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
5f4273c7 | 14060 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ |
5287ad62 JB |
14061 | |
14062 | static void | |
14063 | neon_mixed_length (struct neon_type_el et, unsigned size) | |
14064 | { | |
14065 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14066 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14067 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14068 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14069 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14070 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14071 | inst.instruction |= (et.type == NT_unsigned) << 24; | |
14072 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 14073 | |
88714cb8 | 14074 | neon_dp_fixup (&inst); |
5287ad62 JB |
14075 | } |
14076 | ||
14077 | static void | |
14078 | do_neon_dyadic_long (void) | |
14079 | { | |
14080 | /* FIXME: Type checking for lengthening op. */ | |
14081 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14082 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
14083 | neon_mixed_length (et, et.size); | |
14084 | } | |
14085 | ||
14086 | static void | |
14087 | do_neon_abal (void) | |
14088 | { | |
14089 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14090 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
14091 | neon_mixed_length (et, et.size); | |
14092 | } | |
14093 | ||
14094 | static void | |
14095 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) | |
14096 | { | |
14097 | if (inst.operands[2].isscalar) | |
14098 | { | |
dcbf9037 JB |
14099 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
14100 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); | |
88714cb8 | 14101 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
14102 | neon_mul_mac (et, et.type == NT_unsigned); |
14103 | } | |
14104 | else | |
14105 | { | |
14106 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14107 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); | |
88714cb8 | 14108 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14109 | neon_mixed_length (et, et.size); |
14110 | } | |
14111 | } | |
14112 | ||
14113 | static void | |
14114 | do_neon_mac_maybe_scalar_long (void) | |
14115 | { | |
14116 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); | |
14117 | } | |
14118 | ||
14119 | static void | |
14120 | do_neon_dyadic_wide (void) | |
14121 | { | |
14122 | struct neon_type_el et = neon_check_type (3, NS_QQD, | |
14123 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); | |
14124 | neon_mixed_length (et, et.size); | |
14125 | } | |
14126 | ||
14127 | static void | |
14128 | do_neon_dyadic_narrow (void) | |
14129 | { | |
14130 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14131 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); | |
428e3f1f PB |
14132 | /* Operand sign is unimportant, and the U bit is part of the opcode, |
14133 | so force the operand type to integer. */ | |
14134 | et.type = NT_integer; | |
5287ad62 JB |
14135 | neon_mixed_length (et, et.size / 2); |
14136 | } | |
14137 | ||
14138 | static void | |
14139 | do_neon_mul_sat_scalar_long (void) | |
14140 | { | |
14141 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); | |
14142 | } | |
14143 | ||
14144 | static void | |
14145 | do_neon_vmull (void) | |
14146 | { | |
14147 | if (inst.operands[2].isscalar) | |
14148 | do_neon_mac_maybe_scalar_long (); | |
14149 | else | |
14150 | { | |
14151 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14152 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); | |
14153 | if (et.type == NT_poly) | |
88714cb8 | 14154 | NEON_ENCODE (POLY, inst); |
5287ad62 | 14155 | else |
88714cb8 | 14156 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14157 | /* For polynomial encoding, size field must be 0b00 and the U bit must be |
14158 | zero. Should be OK as-is. */ | |
14159 | neon_mixed_length (et, et.size); | |
14160 | } | |
14161 | } | |
14162 | ||
14163 | static void | |
14164 | do_neon_ext (void) | |
14165 | { | |
037e8744 | 14166 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
5287ad62 JB |
14167 | struct neon_type_el et = neon_check_type (3, rs, |
14168 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14169 | unsigned imm = (inst.operands[3].imm * et.size) / 8; | |
35997600 NC |
14170 | |
14171 | constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), | |
14172 | _("shift out of range")); | |
5287ad62 JB |
14173 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14174 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14175 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14176 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14177 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14178 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
037e8744 | 14179 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 | 14180 | inst.instruction |= imm << 8; |
5f4273c7 | 14181 | |
88714cb8 | 14182 | neon_dp_fixup (&inst); |
5287ad62 JB |
14183 | } |
14184 | ||
14185 | static void | |
14186 | do_neon_rev (void) | |
14187 | { | |
037e8744 | 14188 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14189 | struct neon_type_el et = neon_check_type (2, rs, |
14190 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
14191 | unsigned op = (inst.instruction >> 7) & 3; | |
14192 | /* N (width of reversed regions) is encoded as part of the bitmask. We | |
14193 | extract it here to check the elements to be reversed are smaller. | |
14194 | Otherwise we'd get a reserved instruction. */ | |
14195 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; | |
9c2799c2 | 14196 | gas_assert (elsize != 0); |
5287ad62 JB |
14197 | constraint (et.size >= elsize, |
14198 | _("elements must be smaller than reversal region")); | |
037e8744 | 14199 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14200 | } |
14201 | ||
14202 | static void | |
14203 | do_neon_dup (void) | |
14204 | { | |
14205 | if (inst.operands[1].isscalar) | |
14206 | { | |
037e8744 | 14207 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
dcbf9037 JB |
14208 | struct neon_type_el et = neon_check_type (2, rs, |
14209 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
5287ad62 | 14210 | unsigned sizebits = et.size >> 3; |
dcbf9037 | 14211 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
5287ad62 | 14212 | int logsize = neon_logbits (et.size); |
dcbf9037 | 14213 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
037e8744 JB |
14214 | |
14215 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) | |
14216 | return; | |
14217 | ||
88714cb8 | 14218 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
14219 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14220 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14221 | inst.instruction |= LOW4 (dm); | |
14222 | inst.instruction |= HI1 (dm) << 5; | |
037e8744 | 14223 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14224 | inst.instruction |= x << 17; |
14225 | inst.instruction |= sizebits << 16; | |
5f4273c7 | 14226 | |
88714cb8 | 14227 | neon_dp_fixup (&inst); |
5287ad62 JB |
14228 | } |
14229 | else | |
14230 | { | |
037e8744 JB |
14231 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
14232 | struct neon_type_el et = neon_check_type (2, rs, | |
14233 | N_8 | N_16 | N_32 | N_KEY, N_EQK); | |
5287ad62 | 14234 | /* Duplicate ARM register to lanes of vector. */ |
88714cb8 | 14235 | NEON_ENCODE (ARMREG, inst); |
5287ad62 JB |
14236 | switch (et.size) |
14237 | { | |
14238 | case 8: inst.instruction |= 0x400000; break; | |
14239 | case 16: inst.instruction |= 0x000020; break; | |
14240 | case 32: inst.instruction |= 0x000000; break; | |
14241 | default: break; | |
14242 | } | |
14243 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
14244 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; | |
14245 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; | |
037e8744 | 14246 | inst.instruction |= neon_quad (rs) << 21; |
5287ad62 JB |
14247 | /* The encoding for this instruction is identical for the ARM and Thumb |
14248 | variants, except for the condition field. */ | |
037e8744 | 14249 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
14250 | } |
14251 | } | |
14252 | ||
14253 | /* VMOV has particularly many variations. It can be one of: | |
14254 | 0. VMOV<c><q> <Qd>, <Qm> | |
14255 | 1. VMOV<c><q> <Dd>, <Dm> | |
14256 | (Register operations, which are VORR with Rm = Rn.) | |
14257 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> | |
14258 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> | |
14259 | (Immediate loads.) | |
14260 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> | |
14261 | (ARM register to scalar.) | |
14262 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> | |
14263 | (Two ARM registers to vector.) | |
14264 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> | |
14265 | (Scalar to ARM register.) | |
14266 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> | |
14267 | (Vector to two ARM registers.) | |
037e8744 JB |
14268 | 8. VMOV.F32 <Sd>, <Sm> |
14269 | 9. VMOV.F64 <Dd>, <Dm> | |
14270 | (VFP register moves.) | |
14271 | 10. VMOV.F32 <Sd>, #imm | |
14272 | 11. VMOV.F64 <Dd>, #imm | |
14273 | (VFP float immediate load.) | |
14274 | 12. VMOV <Rd>, <Sm> | |
14275 | (VFP single to ARM reg.) | |
14276 | 13. VMOV <Sd>, <Rm> | |
14277 | (ARM reg to VFP single.) | |
14278 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> | |
14279 | (Two ARM regs to two VFP singles.) | |
14280 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> | |
14281 | (Two VFP singles to two ARM regs.) | |
5f4273c7 | 14282 | |
037e8744 JB |
14283 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
14284 | and 3/11 which depend on the operand type too. | |
5f4273c7 | 14285 | |
5287ad62 | 14286 | All the encoded bits are hardcoded by this function. |
5f4273c7 | 14287 | |
b7fc2769 JB |
14288 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
14289 | Cases 5, 7 may be used with VFPv2 and above. | |
5f4273c7 | 14290 | |
5287ad62 | 14291 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
5f4273c7 | 14292 | can specify a type where it doesn't make sense to, and is ignored). */ |
5287ad62 JB |
14293 | |
14294 | static void | |
14295 | do_neon_mov (void) | |
14296 | { | |
037e8744 JB |
14297 | enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, |
14298 | NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, | |
14299 | NS_NULL); | |
14300 | struct neon_type_el et; | |
14301 | const char *ldconst = 0; | |
5287ad62 | 14302 | |
037e8744 | 14303 | switch (rs) |
5287ad62 | 14304 | { |
037e8744 JB |
14305 | case NS_DD: /* case 1/9. */ |
14306 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
14307 | /* It is not an error here if no type is given. */ | |
14308 | inst.error = NULL; | |
14309 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 14310 | { |
037e8744 JB |
14311 | do_vfp_nsyn_opcode ("fcpyd"); |
14312 | break; | |
5287ad62 | 14313 | } |
037e8744 | 14314 | /* fall through. */ |
5287ad62 | 14315 | |
037e8744 JB |
14316 | case NS_QQ: /* case 0/1. */ |
14317 | { | |
14318 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14319 | return; | |
14320 | /* The architecture manual I have doesn't explicitly state which | |
14321 | value the U bit should have for register->register moves, but | |
14322 | the equivalent VORR instruction has U = 0, so do that. */ | |
14323 | inst.instruction = 0x0200110; | |
14324 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14325 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14326 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14327 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14328 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14329 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14330 | inst.instruction |= neon_quad (rs) << 6; | |
14331 | ||
88714cb8 | 14332 | neon_dp_fixup (&inst); |
037e8744 JB |
14333 | } |
14334 | break; | |
5f4273c7 | 14335 | |
037e8744 JB |
14336 | case NS_DI: /* case 3/11. */ |
14337 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
14338 | inst.error = NULL; | |
14339 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 14340 | { |
037e8744 JB |
14341 | /* case 11 (fconstd). */ |
14342 | ldconst = "fconstd"; | |
14343 | goto encode_fconstd; | |
5287ad62 | 14344 | } |
037e8744 JB |
14345 | /* fall through. */ |
14346 | ||
14347 | case NS_QI: /* case 2/3. */ | |
14348 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14349 | return; | |
14350 | inst.instruction = 0x0800010; | |
14351 | neon_move_immediate (); | |
88714cb8 | 14352 | neon_dp_fixup (&inst); |
5287ad62 | 14353 | break; |
5f4273c7 | 14354 | |
037e8744 JB |
14355 | case NS_SR: /* case 4. */ |
14356 | { | |
14357 | unsigned bcdebits = 0; | |
91d6fa6a | 14358 | int logsize; |
037e8744 JB |
14359 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); |
14360 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); | |
14361 | ||
91d6fa6a NC |
14362 | et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK); |
14363 | logsize = neon_logbits (et.size); | |
14364 | ||
037e8744 JB |
14365 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), |
14366 | _(BAD_FPU)); | |
14367 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
14368 | && et.size != 32, _(BAD_FPU)); | |
14369 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
14370 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
14371 | ||
14372 | switch (et.size) | |
14373 | { | |
14374 | case 8: bcdebits = 0x8; break; | |
14375 | case 16: bcdebits = 0x1; break; | |
14376 | case 32: bcdebits = 0x0; break; | |
14377 | default: ; | |
14378 | } | |
14379 | ||
14380 | bcdebits |= x << logsize; | |
14381 | ||
14382 | inst.instruction = 0xe000b10; | |
14383 | do_vfp_cond_or_thumb (); | |
14384 | inst.instruction |= LOW4 (dn) << 16; | |
14385 | inst.instruction |= HI1 (dn) << 7; | |
14386 | inst.instruction |= inst.operands[1].reg << 12; | |
14387 | inst.instruction |= (bcdebits & 3) << 5; | |
14388 | inst.instruction |= (bcdebits >> 2) << 21; | |
14389 | } | |
14390 | break; | |
5f4273c7 | 14391 | |
037e8744 | 14392 | case NS_DRR: /* case 5 (fmdrr). */ |
b7fc2769 | 14393 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), |
037e8744 | 14394 | _(BAD_FPU)); |
b7fc2769 | 14395 | |
037e8744 JB |
14396 | inst.instruction = 0xc400b10; |
14397 | do_vfp_cond_or_thumb (); | |
14398 | inst.instruction |= LOW4 (inst.operands[0].reg); | |
14399 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; | |
14400 | inst.instruction |= inst.operands[1].reg << 12; | |
14401 | inst.instruction |= inst.operands[2].reg << 16; | |
14402 | break; | |
5f4273c7 | 14403 | |
037e8744 JB |
14404 | case NS_RS: /* case 6. */ |
14405 | { | |
91d6fa6a | 14406 | unsigned logsize; |
037e8744 JB |
14407 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); |
14408 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); | |
14409 | unsigned abcdebits = 0; | |
14410 | ||
91d6fa6a NC |
14411 | et = neon_check_type (2, NS_NULL, |
14412 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); | |
14413 | logsize = neon_logbits (et.size); | |
14414 | ||
037e8744 JB |
14415 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), |
14416 | _(BAD_FPU)); | |
14417 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
14418 | && et.size != 32, _(BAD_FPU)); | |
14419 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
14420 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
14421 | ||
14422 | switch (et.size) | |
14423 | { | |
14424 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; | |
14425 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; | |
14426 | case 32: abcdebits = 0x00; break; | |
14427 | default: ; | |
14428 | } | |
14429 | ||
14430 | abcdebits |= x << logsize; | |
14431 | inst.instruction = 0xe100b10; | |
14432 | do_vfp_cond_or_thumb (); | |
14433 | inst.instruction |= LOW4 (dn) << 16; | |
14434 | inst.instruction |= HI1 (dn) << 7; | |
14435 | inst.instruction |= inst.operands[0].reg << 12; | |
14436 | inst.instruction |= (abcdebits & 3) << 5; | |
14437 | inst.instruction |= (abcdebits >> 2) << 21; | |
14438 | } | |
14439 | break; | |
5f4273c7 | 14440 | |
037e8744 JB |
14441 | case NS_RRD: /* case 7 (fmrrd). */ |
14442 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), | |
14443 | _(BAD_FPU)); | |
14444 | ||
14445 | inst.instruction = 0xc500b10; | |
14446 | do_vfp_cond_or_thumb (); | |
14447 | inst.instruction |= inst.operands[0].reg << 12; | |
14448 | inst.instruction |= inst.operands[1].reg << 16; | |
14449 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14450 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14451 | break; | |
5f4273c7 | 14452 | |
037e8744 JB |
14453 | case NS_FF: /* case 8 (fcpys). */ |
14454 | do_vfp_nsyn_opcode ("fcpys"); | |
14455 | break; | |
5f4273c7 | 14456 | |
037e8744 JB |
14457 | case NS_FI: /* case 10 (fconsts). */ |
14458 | ldconst = "fconsts"; | |
14459 | encode_fconstd: | |
14460 | if (is_quarter_float (inst.operands[1].imm)) | |
5287ad62 | 14461 | { |
037e8744 JB |
14462 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); |
14463 | do_vfp_nsyn_opcode (ldconst); | |
5287ad62 JB |
14464 | } |
14465 | else | |
037e8744 JB |
14466 | first_error (_("immediate out of range")); |
14467 | break; | |
5f4273c7 | 14468 | |
037e8744 JB |
14469 | case NS_RF: /* case 12 (fmrs). */ |
14470 | do_vfp_nsyn_opcode ("fmrs"); | |
14471 | break; | |
5f4273c7 | 14472 | |
037e8744 JB |
14473 | case NS_FR: /* case 13 (fmsr). */ |
14474 | do_vfp_nsyn_opcode ("fmsr"); | |
14475 | break; | |
5f4273c7 | 14476 | |
037e8744 JB |
14477 | /* The encoders for the fmrrs and fmsrr instructions expect three operands |
14478 | (one of which is a list), but we have parsed four. Do some fiddling to | |
14479 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 | |
14480 | expect. */ | |
14481 | case NS_RRFF: /* case 14 (fmrrs). */ | |
14482 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, | |
14483 | _("VFP registers must be adjacent")); | |
14484 | inst.operands[2].imm = 2; | |
14485 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
14486 | do_vfp_nsyn_opcode ("fmrrs"); | |
14487 | break; | |
5f4273c7 | 14488 | |
037e8744 JB |
14489 | case NS_FFRR: /* case 15 (fmsrr). */ |
14490 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, | |
14491 | _("VFP registers must be adjacent")); | |
14492 | inst.operands[1] = inst.operands[2]; | |
14493 | inst.operands[2] = inst.operands[3]; | |
14494 | inst.operands[0].imm = 2; | |
14495 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
14496 | do_vfp_nsyn_opcode ("fmsrr"); | |
5287ad62 | 14497 | break; |
5f4273c7 | 14498 | |
5287ad62 JB |
14499 | default: |
14500 | abort (); | |
14501 | } | |
14502 | } | |
14503 | ||
14504 | static void | |
14505 | do_neon_rshift_round_imm (void) | |
14506 | { | |
037e8744 | 14507 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14508 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
14509 | int imm = inst.operands[2].imm; | |
14510 | ||
14511 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ | |
14512 | if (imm == 0) | |
14513 | { | |
14514 | inst.operands[2].present = 0; | |
14515 | do_neon_mov (); | |
14516 | return; | |
14517 | } | |
14518 | ||
14519 | constraint (imm < 1 || (unsigned)imm > et.size, | |
14520 | _("immediate out of range for shift")); | |
037e8744 | 14521 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
14522 | et.size - imm); |
14523 | } | |
14524 | ||
14525 | static void | |
14526 | do_neon_movl (void) | |
14527 | { | |
14528 | struct neon_type_el et = neon_check_type (2, NS_QD, | |
14529 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
14530 | unsigned sizebits = et.size >> 3; | |
14531 | inst.instruction |= sizebits << 19; | |
14532 | neon_two_same (0, et.type == NT_unsigned, -1); | |
14533 | } | |
14534 | ||
14535 | static void | |
14536 | do_neon_trn (void) | |
14537 | { | |
037e8744 | 14538 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14539 | struct neon_type_el et = neon_check_type (2, rs, |
14540 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
88714cb8 | 14541 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14542 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14543 | } |
14544 | ||
14545 | static void | |
14546 | do_neon_zip_uzp (void) | |
14547 | { | |
037e8744 | 14548 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14549 | struct neon_type_el et = neon_check_type (2, rs, |
14550 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
14551 | if (rs == NS_DD && et.size == 32) | |
14552 | { | |
14553 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ | |
14554 | inst.instruction = N_MNEM_vtrn; | |
14555 | do_neon_trn (); | |
14556 | return; | |
14557 | } | |
037e8744 | 14558 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14559 | } |
14560 | ||
14561 | static void | |
14562 | do_neon_sat_abs_neg (void) | |
14563 | { | |
037e8744 | 14564 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14565 | struct neon_type_el et = neon_check_type (2, rs, |
14566 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 14567 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14568 | } |
14569 | ||
14570 | static void | |
14571 | do_neon_pair_long (void) | |
14572 | { | |
037e8744 | 14573 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14574 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
14575 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ | |
14576 | inst.instruction |= (et.type == NT_unsigned) << 7; | |
037e8744 | 14577 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14578 | } |
14579 | ||
14580 | static void | |
14581 | do_neon_recip_est (void) | |
14582 | { | |
037e8744 | 14583 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14584 | struct neon_type_el et = neon_check_type (2, rs, |
14585 | N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); | |
14586 | inst.instruction |= (et.type == NT_float) << 8; | |
037e8744 | 14587 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14588 | } |
14589 | ||
14590 | static void | |
14591 | do_neon_cls (void) | |
14592 | { | |
037e8744 | 14593 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14594 | struct neon_type_el et = neon_check_type (2, rs, |
14595 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 14596 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14597 | } |
14598 | ||
14599 | static void | |
14600 | do_neon_clz (void) | |
14601 | { | |
037e8744 | 14602 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14603 | struct neon_type_el et = neon_check_type (2, rs, |
14604 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); | |
037e8744 | 14605 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14606 | } |
14607 | ||
14608 | static void | |
14609 | do_neon_cnt (void) | |
14610 | { | |
037e8744 | 14611 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14612 | struct neon_type_el et = neon_check_type (2, rs, |
14613 | N_EQK | N_INT, N_8 | N_KEY); | |
037e8744 | 14614 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14615 | } |
14616 | ||
14617 | static void | |
14618 | do_neon_swp (void) | |
14619 | { | |
037e8744 JB |
14620 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
14621 | neon_two_same (neon_quad (rs), 1, -1); | |
5287ad62 JB |
14622 | } |
14623 | ||
14624 | static void | |
14625 | do_neon_tbl_tbx (void) | |
14626 | { | |
14627 | unsigned listlenbits; | |
dcbf9037 | 14628 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
5f4273c7 | 14629 | |
5287ad62 JB |
14630 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) |
14631 | { | |
dcbf9037 | 14632 | first_error (_("bad list length for table lookup")); |
5287ad62 JB |
14633 | return; |
14634 | } | |
5f4273c7 | 14635 | |
5287ad62 JB |
14636 | listlenbits = inst.operands[1].imm - 1; |
14637 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14638 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14639 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14640 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14641 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14642 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14643 | inst.instruction |= listlenbits << 8; | |
5f4273c7 | 14644 | |
88714cb8 | 14645 | neon_dp_fixup (&inst); |
5287ad62 JB |
14646 | } |
14647 | ||
14648 | static void | |
14649 | do_neon_ldm_stm (void) | |
14650 | { | |
14651 | /* P, U and L bits are part of bitmask. */ | |
14652 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; | |
14653 | unsigned offsetbits = inst.operands[1].imm * 2; | |
14654 | ||
037e8744 JB |
14655 | if (inst.operands[1].issingle) |
14656 | { | |
14657 | do_vfp_nsyn_ldm_stm (is_dbmode); | |
14658 | return; | |
14659 | } | |
14660 | ||
5287ad62 JB |
14661 | constraint (is_dbmode && !inst.operands[0].writeback, |
14662 | _("writeback (!) must be used for VLDMDB and VSTMDB")); | |
14663 | ||
14664 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
14665 | _("register list must contain at least 1 and at most 16 " | |
14666 | "registers")); | |
14667 | ||
14668 | inst.instruction |= inst.operands[0].reg << 16; | |
14669 | inst.instruction |= inst.operands[0].writeback << 21; | |
14670 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
14671 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; | |
14672 | ||
14673 | inst.instruction |= offsetbits; | |
5f4273c7 | 14674 | |
037e8744 | 14675 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
14676 | } |
14677 | ||
14678 | static void | |
14679 | do_neon_ldr_str (void) | |
14680 | { | |
5287ad62 | 14681 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
5f4273c7 | 14682 | |
037e8744 JB |
14683 | if (inst.operands[0].issingle) |
14684 | { | |
cd2f129f JB |
14685 | if (is_ldr) |
14686 | do_vfp_nsyn_opcode ("flds"); | |
14687 | else | |
14688 | do_vfp_nsyn_opcode ("fsts"); | |
5287ad62 JB |
14689 | } |
14690 | else | |
5287ad62 | 14691 | { |
cd2f129f JB |
14692 | if (is_ldr) |
14693 | do_vfp_nsyn_opcode ("fldd"); | |
5287ad62 | 14694 | else |
cd2f129f | 14695 | do_vfp_nsyn_opcode ("fstd"); |
5287ad62 | 14696 | } |
5287ad62 JB |
14697 | } |
14698 | ||
14699 | /* "interleave" version also handles non-interleaving register VLD1/VST1 | |
14700 | instructions. */ | |
14701 | ||
14702 | static void | |
14703 | do_neon_ld_st_interleave (void) | |
14704 | { | |
037e8744 | 14705 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
5287ad62 JB |
14706 | N_8 | N_16 | N_32 | N_64); |
14707 | unsigned alignbits = 0; | |
14708 | unsigned idx; | |
14709 | /* The bits in this table go: | |
14710 | 0: register stride of one (0) or two (1) | |
14711 | 1,2: register list length, minus one (1, 2, 3, 4). | |
14712 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). | |
14713 | We use -1 for invalid entries. */ | |
14714 | const int typetable[] = | |
14715 | { | |
14716 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ | |
14717 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ | |
14718 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ | |
14719 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ | |
14720 | }; | |
14721 | int typebits; | |
14722 | ||
dcbf9037 JB |
14723 | if (et.type == NT_invtype) |
14724 | return; | |
14725 | ||
5287ad62 JB |
14726 | if (inst.operands[1].immisalign) |
14727 | switch (inst.operands[1].imm >> 8) | |
14728 | { | |
14729 | case 64: alignbits = 1; break; | |
14730 | case 128: | |
e23c0ad8 JZ |
14731 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2 |
14732 | && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) | |
5287ad62 JB |
14733 | goto bad_alignment; |
14734 | alignbits = 2; | |
14735 | break; | |
14736 | case 256: | |
e23c0ad8 | 14737 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
5287ad62 JB |
14738 | goto bad_alignment; |
14739 | alignbits = 3; | |
14740 | break; | |
14741 | default: | |
14742 | bad_alignment: | |
dcbf9037 | 14743 | first_error (_("bad alignment")); |
5287ad62 JB |
14744 | return; |
14745 | } | |
14746 | ||
14747 | inst.instruction |= alignbits << 4; | |
14748 | inst.instruction |= neon_logbits (et.size) << 6; | |
14749 | ||
14750 | /* Bits [4:6] of the immediate in a list specifier encode register stride | |
14751 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of | |
14752 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look | |
14753 | up the right value for "type" in a table based on this value and the given | |
14754 | list style, then stick it back. */ | |
14755 | idx = ((inst.operands[0].imm >> 4) & 7) | |
14756 | | (((inst.instruction >> 8) & 3) << 3); | |
14757 | ||
14758 | typebits = typetable[idx]; | |
5f4273c7 | 14759 | |
5287ad62 JB |
14760 | constraint (typebits == -1, _("bad list type for instruction")); |
14761 | ||
14762 | inst.instruction &= ~0xf00; | |
14763 | inst.instruction |= typebits << 8; | |
14764 | } | |
14765 | ||
14766 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. | |
14767 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 | |
14768 | otherwise. The variable arguments are a list of pairs of legal (size, align) | |
14769 | values, terminated with -1. */ | |
14770 | ||
14771 | static int | |
14772 | neon_alignment_bit (int size, int align, int *do_align, ...) | |
14773 | { | |
14774 | va_list ap; | |
14775 | int result = FAIL, thissize, thisalign; | |
5f4273c7 | 14776 | |
5287ad62 JB |
14777 | if (!inst.operands[1].immisalign) |
14778 | { | |
14779 | *do_align = 0; | |
14780 | return SUCCESS; | |
14781 | } | |
5f4273c7 | 14782 | |
5287ad62 JB |
14783 | va_start (ap, do_align); |
14784 | ||
14785 | do | |
14786 | { | |
14787 | thissize = va_arg (ap, int); | |
14788 | if (thissize == -1) | |
14789 | break; | |
14790 | thisalign = va_arg (ap, int); | |
14791 | ||
14792 | if (size == thissize && align == thisalign) | |
14793 | result = SUCCESS; | |
14794 | } | |
14795 | while (result != SUCCESS); | |
14796 | ||
14797 | va_end (ap); | |
14798 | ||
14799 | if (result == SUCCESS) | |
14800 | *do_align = 1; | |
14801 | else | |
dcbf9037 | 14802 | first_error (_("unsupported alignment for instruction")); |
5f4273c7 | 14803 | |
5287ad62 JB |
14804 | return result; |
14805 | } | |
14806 | ||
14807 | static void | |
14808 | do_neon_ld_st_lane (void) | |
14809 | { | |
037e8744 | 14810 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
14811 | int align_good, do_align = 0; |
14812 | int logsize = neon_logbits (et.size); | |
14813 | int align = inst.operands[1].imm >> 8; | |
14814 | int n = (inst.instruction >> 8) & 3; | |
14815 | int max_el = 64 / et.size; | |
5f4273c7 | 14816 | |
dcbf9037 JB |
14817 | if (et.type == NT_invtype) |
14818 | return; | |
5f4273c7 | 14819 | |
5287ad62 JB |
14820 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
14821 | _("bad list length")); | |
14822 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, | |
14823 | _("scalar index out of range")); | |
14824 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 | |
14825 | && et.size == 8, | |
14826 | _("stride of 2 unavailable when element size is 8")); | |
5f4273c7 | 14827 | |
5287ad62 JB |
14828 | switch (n) |
14829 | { | |
14830 | case 0: /* VLD1 / VST1. */ | |
14831 | align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, | |
14832 | 32, 32, -1); | |
14833 | if (align_good == FAIL) | |
14834 | return; | |
14835 | if (do_align) | |
14836 | { | |
14837 | unsigned alignbits = 0; | |
14838 | switch (et.size) | |
14839 | { | |
14840 | case 16: alignbits = 0x1; break; | |
14841 | case 32: alignbits = 0x3; break; | |
14842 | default: ; | |
14843 | } | |
14844 | inst.instruction |= alignbits << 4; | |
14845 | } | |
14846 | break; | |
14847 | ||
14848 | case 1: /* VLD2 / VST2. */ | |
14849 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, | |
14850 | 32, 64, -1); | |
14851 | if (align_good == FAIL) | |
14852 | return; | |
14853 | if (do_align) | |
14854 | inst.instruction |= 1 << 4; | |
14855 | break; | |
14856 | ||
14857 | case 2: /* VLD3 / VST3. */ | |
14858 | constraint (inst.operands[1].immisalign, | |
14859 | _("can't use alignment with this instruction")); | |
14860 | break; | |
14861 | ||
14862 | case 3: /* VLD4 / VST4. */ | |
14863 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
14864 | 16, 64, 32, 64, 32, 128, -1); | |
14865 | if (align_good == FAIL) | |
14866 | return; | |
14867 | if (do_align) | |
14868 | { | |
14869 | unsigned alignbits = 0; | |
14870 | switch (et.size) | |
14871 | { | |
14872 | case 8: alignbits = 0x1; break; | |
14873 | case 16: alignbits = 0x1; break; | |
14874 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; | |
14875 | default: ; | |
14876 | } | |
14877 | inst.instruction |= alignbits << 4; | |
14878 | } | |
14879 | break; | |
14880 | ||
14881 | default: ; | |
14882 | } | |
14883 | ||
14884 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ | |
14885 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
14886 | inst.instruction |= 1 << (4 + logsize); | |
5f4273c7 | 14887 | |
5287ad62 JB |
14888 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); |
14889 | inst.instruction |= logsize << 10; | |
14890 | } | |
14891 | ||
14892 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ | |
14893 | ||
14894 | static void | |
14895 | do_neon_ld_dup (void) | |
14896 | { | |
037e8744 | 14897 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
14898 | int align_good, do_align = 0; |
14899 | ||
dcbf9037 JB |
14900 | if (et.type == NT_invtype) |
14901 | return; | |
14902 | ||
5287ad62 JB |
14903 | switch ((inst.instruction >> 8) & 3) |
14904 | { | |
14905 | case 0: /* VLD1. */ | |
9c2799c2 | 14906 | gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); |
5287ad62 JB |
14907 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, |
14908 | &do_align, 16, 16, 32, 32, -1); | |
14909 | if (align_good == FAIL) | |
14910 | return; | |
14911 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) | |
14912 | { | |
14913 | case 1: break; | |
14914 | case 2: inst.instruction |= 1 << 5; break; | |
dcbf9037 | 14915 | default: first_error (_("bad list length")); return; |
5287ad62 JB |
14916 | } |
14917 | inst.instruction |= neon_logbits (et.size) << 6; | |
14918 | break; | |
14919 | ||
14920 | case 1: /* VLD2. */ | |
14921 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
14922 | &do_align, 8, 16, 16, 32, 32, 64, -1); | |
14923 | if (align_good == FAIL) | |
14924 | return; | |
14925 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, | |
14926 | _("bad list length")); | |
14927 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
14928 | inst.instruction |= 1 << 5; | |
14929 | inst.instruction |= neon_logbits (et.size) << 6; | |
14930 | break; | |
14931 | ||
14932 | case 2: /* VLD3. */ | |
14933 | constraint (inst.operands[1].immisalign, | |
14934 | _("can't use alignment with this instruction")); | |
14935 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, | |
14936 | _("bad list length")); | |
14937 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
14938 | inst.instruction |= 1 << 5; | |
14939 | inst.instruction |= neon_logbits (et.size) << 6; | |
14940 | break; | |
14941 | ||
14942 | case 3: /* VLD4. */ | |
14943 | { | |
14944 | int align = inst.operands[1].imm >> 8; | |
14945 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
14946 | 16, 64, 32, 64, 32, 128, -1); | |
14947 | if (align_good == FAIL) | |
14948 | return; | |
14949 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, | |
14950 | _("bad list length")); | |
14951 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
14952 | inst.instruction |= 1 << 5; | |
14953 | if (et.size == 32 && align == 128) | |
14954 | inst.instruction |= 0x3 << 6; | |
14955 | else | |
14956 | inst.instruction |= neon_logbits (et.size) << 6; | |
14957 | } | |
14958 | break; | |
14959 | ||
14960 | default: ; | |
14961 | } | |
14962 | ||
14963 | inst.instruction |= do_align << 4; | |
14964 | } | |
14965 | ||
14966 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those | |
14967 | apart from bits [11:4]. */ | |
14968 | ||
14969 | static void | |
14970 | do_neon_ldx_stx (void) | |
14971 | { | |
b1a769ed DG |
14972 | if (inst.operands[1].isreg) |
14973 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
14974 | ||
5287ad62 JB |
14975 | switch (NEON_LANE (inst.operands[0].imm)) |
14976 | { | |
14977 | case NEON_INTERLEAVE_LANES: | |
88714cb8 | 14978 | NEON_ENCODE (INTERLV, inst); |
5287ad62 JB |
14979 | do_neon_ld_st_interleave (); |
14980 | break; | |
5f4273c7 | 14981 | |
5287ad62 | 14982 | case NEON_ALL_LANES: |
88714cb8 | 14983 | NEON_ENCODE (DUP, inst); |
5287ad62 JB |
14984 | do_neon_ld_dup (); |
14985 | break; | |
5f4273c7 | 14986 | |
5287ad62 | 14987 | default: |
88714cb8 | 14988 | NEON_ENCODE (LANE, inst); |
5287ad62 JB |
14989 | do_neon_ld_st_lane (); |
14990 | } | |
14991 | ||
14992 | /* L bit comes from bit mask. */ | |
14993 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14994 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14995 | inst.instruction |= inst.operands[1].reg << 16; | |
5f4273c7 | 14996 | |
5287ad62 JB |
14997 | if (inst.operands[1].postind) |
14998 | { | |
14999 | int postreg = inst.operands[1].imm & 0xf; | |
15000 | constraint (!inst.operands[1].immisreg, | |
15001 | _("post-index must be a register")); | |
15002 | constraint (postreg == 0xd || postreg == 0xf, | |
15003 | _("bad register for post-index")); | |
15004 | inst.instruction |= postreg; | |
15005 | } | |
15006 | else if (inst.operands[1].writeback) | |
15007 | { | |
15008 | inst.instruction |= 0xd; | |
15009 | } | |
15010 | else | |
5f4273c7 NC |
15011 | inst.instruction |= 0xf; |
15012 | ||
5287ad62 JB |
15013 | if (thumb_mode) |
15014 | inst.instruction |= 0xf9000000; | |
15015 | else | |
15016 | inst.instruction |= 0xf4000000; | |
15017 | } | |
5287ad62 JB |
15018 | \f |
15019 | /* Overall per-instruction processing. */ | |
15020 | ||
15021 | /* We need to be able to fix up arbitrary expressions in some statements. | |
15022 | This is so that we can handle symbols that are an arbitrary distance from | |
15023 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
15024 | which returns part of an address in a form which will be valid for | |
15025 | a data instruction. We do this by pushing the expression into a symbol | |
15026 | in the expr_section, and creating a fix for that. */ | |
15027 | ||
15028 | static void | |
15029 | fix_new_arm (fragS * frag, | |
15030 | int where, | |
15031 | short int size, | |
15032 | expressionS * exp, | |
15033 | int pc_rel, | |
15034 | int reloc) | |
15035 | { | |
15036 | fixS * new_fix; | |
15037 | ||
15038 | switch (exp->X_op) | |
15039 | { | |
15040 | case O_constant: | |
15041 | case O_symbol: | |
15042 | case O_add: | |
15043 | case O_subtract: | |
21d799b5 NC |
15044 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, |
15045 | (enum bfd_reloc_code_real) reloc); | |
5287ad62 JB |
15046 | break; |
15047 | ||
15048 | default: | |
21d799b5 NC |
15049 | new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0, |
15050 | pc_rel, (enum bfd_reloc_code_real) reloc); | |
5287ad62 JB |
15051 | break; |
15052 | } | |
15053 | ||
15054 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
15055 | instruction. */ | |
15056 | new_fix->tc_fix_data = thumb_mode; | |
15057 | } | |
15058 | ||
15059 | /* Create a frg for an instruction requiring relaxation. */ | |
15060 | static void | |
15061 | output_relax_insn (void) | |
15062 | { | |
15063 | char * to; | |
15064 | symbolS *sym; | |
0110f2b8 PB |
15065 | int offset; |
15066 | ||
6e1cb1a6 PB |
15067 | /* The size of the instruction is unknown, so tie the debug info to the |
15068 | start of the instruction. */ | |
15069 | dwarf2_emit_insn (0); | |
6e1cb1a6 | 15070 | |
0110f2b8 PB |
15071 | switch (inst.reloc.exp.X_op) |
15072 | { | |
15073 | case O_symbol: | |
15074 | sym = inst.reloc.exp.X_add_symbol; | |
15075 | offset = inst.reloc.exp.X_add_number; | |
15076 | break; | |
15077 | case O_constant: | |
15078 | sym = NULL; | |
15079 | offset = inst.reloc.exp.X_add_number; | |
15080 | break; | |
15081 | default: | |
15082 | sym = make_expr_symbol (&inst.reloc.exp); | |
15083 | offset = 0; | |
15084 | break; | |
15085 | } | |
15086 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
15087 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
15088 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
15089 | } |
15090 | ||
15091 | /* Write a 32-bit thumb instruction to buf. */ | |
15092 | static void | |
15093 | put_thumb32_insn (char * buf, unsigned long insn) | |
15094 | { | |
15095 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
15096 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
15097 | } | |
15098 | ||
b99bd4ef | 15099 | static void |
c19d1205 | 15100 | output_inst (const char * str) |
b99bd4ef | 15101 | { |
c19d1205 | 15102 | char * to = NULL; |
b99bd4ef | 15103 | |
c19d1205 | 15104 | if (inst.error) |
b99bd4ef | 15105 | { |
c19d1205 | 15106 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
15107 | return; |
15108 | } | |
5f4273c7 NC |
15109 | if (inst.relax) |
15110 | { | |
15111 | output_relax_insn (); | |
0110f2b8 | 15112 | return; |
5f4273c7 | 15113 | } |
c19d1205 ZW |
15114 | if (inst.size == 0) |
15115 | return; | |
b99bd4ef | 15116 | |
c19d1205 | 15117 | to = frag_more (inst.size); |
8dc2430f NC |
15118 | /* PR 9814: Record the thumb mode into the current frag so that we know |
15119 | what type of NOP padding to use, if necessary. We override any previous | |
15120 | setting so that if the mode has changed then the NOPS that we use will | |
15121 | match the encoding of the last instruction in the frag. */ | |
cd000bff | 15122 | frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
c19d1205 ZW |
15123 | |
15124 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 15125 | { |
9c2799c2 | 15126 | gas_assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 15127 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 15128 | } |
c19d1205 | 15129 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 15130 | { |
9c2799c2 | 15131 | gas_assert (inst.size == (2 * INSN_SIZE)); |
c19d1205 ZW |
15132 | md_number_to_chars (to, inst.instruction, INSN_SIZE); |
15133 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 15134 | } |
c19d1205 ZW |
15135 | else |
15136 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 15137 | |
c19d1205 ZW |
15138 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
15139 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
15140 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
15141 | inst.reloc.type); | |
b99bd4ef | 15142 | |
c19d1205 | 15143 | dwarf2_emit_insn (inst.size); |
c19d1205 | 15144 | } |
b99bd4ef | 15145 | |
e07e6e58 NC |
15146 | static char * |
15147 | output_it_inst (int cond, int mask, char * to) | |
15148 | { | |
15149 | unsigned long instruction = 0xbf00; | |
15150 | ||
15151 | mask &= 0xf; | |
15152 | instruction |= mask; | |
15153 | instruction |= cond << 4; | |
15154 | ||
15155 | if (to == NULL) | |
15156 | { | |
15157 | to = frag_more (2); | |
15158 | #ifdef OBJ_ELF | |
15159 | dwarf2_emit_insn (2); | |
15160 | #endif | |
15161 | } | |
15162 | ||
15163 | md_number_to_chars (to, instruction, 2); | |
15164 | ||
15165 | return to; | |
15166 | } | |
15167 | ||
c19d1205 ZW |
15168 | /* Tag values used in struct asm_opcode's tag field. */ |
15169 | enum opcode_tag | |
15170 | { | |
15171 | OT_unconditional, /* Instruction cannot be conditionalized. | |
15172 | The ARM condition field is still 0xE. */ | |
15173 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
15174 | and carries 0xF in its ARM condition field. */ | |
15175 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
037e8744 JB |
15176 | OT_csuffixF, /* Some forms of the instruction take a conditional |
15177 | suffix, others place 0xF where the condition field | |
15178 | would be. */ | |
c19d1205 ZW |
15179 | OT_cinfix3, /* Instruction takes a conditional infix, |
15180 | beginning at character index 3. (In | |
15181 | unified mode, it becomes a suffix.) */ | |
088fa78e KH |
15182 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
15183 | tsts, cmps, cmns, and teqs. */ | |
e3cb604e PB |
15184 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
15185 | character index 3, even in unified mode. Used for | |
15186 | legacy instructions where suffix and infix forms | |
15187 | may be ambiguous. */ | |
c19d1205 | 15188 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 15189 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
15190 | OT_odd_infix_unc, /* This is the unconditional variant of an |
15191 | instruction that takes a conditional infix | |
15192 | at an unusual position. In unified mode, | |
15193 | this variant will accept a suffix. */ | |
15194 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
15195 | are the conditional variants of instructions that | |
15196 | take conditional infixes in unusual positions. | |
15197 | The infix appears at character index | |
15198 | (tag - OT_odd_infix_0). These are not accepted | |
15199 | in unified mode. */ | |
15200 | }; | |
b99bd4ef | 15201 | |
c19d1205 ZW |
15202 | /* Subroutine of md_assemble, responsible for looking up the primary |
15203 | opcode from the mnemonic the user wrote. STR points to the | |
15204 | beginning of the mnemonic. | |
15205 | ||
15206 | This is not simply a hash table lookup, because of conditional | |
15207 | variants. Most instructions have conditional variants, which are | |
15208 | expressed with a _conditional affix_ to the mnemonic. If we were | |
15209 | to encode each conditional variant as a literal string in the opcode | |
15210 | table, it would have approximately 20,000 entries. | |
15211 | ||
15212 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
15213 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
15214 | instructions take the affix as an infix, notably the s-variants of | |
15215 | the arithmetic instructions. Of those instructions, all but six | |
15216 | have the infix appear after the third character of the mnemonic. | |
15217 | ||
15218 | Accordingly, the algorithm for looking up primary opcodes given | |
15219 | an identifier is: | |
15220 | ||
15221 | 1. Look up the identifier in the opcode table. | |
15222 | If we find a match, go to step U. | |
15223 | ||
15224 | 2. Look up the last two characters of the identifier in the | |
15225 | conditions table. If we find a match, look up the first N-2 | |
15226 | characters of the identifier in the opcode table. If we | |
15227 | find a match, go to step CE. | |
15228 | ||
15229 | 3. Look up the fourth and fifth characters of the identifier in | |
15230 | the conditions table. If we find a match, extract those | |
15231 | characters from the identifier, and look up the remaining | |
15232 | characters in the opcode table. If we find a match, go | |
15233 | to step CM. | |
15234 | ||
15235 | 4. Fail. | |
15236 | ||
15237 | U. Examine the tag field of the opcode structure, in case this is | |
15238 | one of the six instructions with its conditional infix in an | |
15239 | unusual place. If it is, the tag tells us where to find the | |
15240 | infix; look it up in the conditions table and set inst.cond | |
15241 | accordingly. Otherwise, this is an unconditional instruction. | |
15242 | Again set inst.cond accordingly. Return the opcode structure. | |
15243 | ||
15244 | CE. Examine the tag field to make sure this is an instruction that | |
15245 | should receive a conditional suffix. If it is not, fail. | |
15246 | Otherwise, set inst.cond from the suffix we already looked up, | |
15247 | and return the opcode structure. | |
15248 | ||
15249 | CM. Examine the tag field to make sure this is an instruction that | |
15250 | should receive a conditional infix after the third character. | |
15251 | If it is not, fail. Otherwise, undo the edits to the current | |
15252 | line of input and proceed as for case CE. */ | |
15253 | ||
15254 | static const struct asm_opcode * | |
15255 | opcode_lookup (char **str) | |
15256 | { | |
15257 | char *end, *base; | |
15258 | char *affix; | |
15259 | const struct asm_opcode *opcode; | |
15260 | const struct asm_cond *cond; | |
e3cb604e | 15261 | char save[2]; |
c19d1205 ZW |
15262 | |
15263 | /* Scan up to the end of the mnemonic, which must end in white space, | |
721a8186 | 15264 | '.' (in unified mode, or for Neon/VFP instructions), or end of string. */ |
c19d1205 | 15265 | for (base = end = *str; *end != '\0'; end++) |
721a8186 | 15266 | if (*end == ' ' || *end == '.') |
c19d1205 | 15267 | break; |
b99bd4ef | 15268 | |
c19d1205 | 15269 | if (end == base) |
c921be7d | 15270 | return NULL; |
b99bd4ef | 15271 | |
5287ad62 | 15272 | /* Handle a possible width suffix and/or Neon type suffix. */ |
c19d1205 | 15273 | if (end[0] == '.') |
b99bd4ef | 15274 | { |
5287ad62 | 15275 | int offset = 2; |
5f4273c7 | 15276 | |
267d2029 JB |
15277 | /* The .w and .n suffixes are only valid if the unified syntax is in |
15278 | use. */ | |
15279 | if (unified_syntax && end[1] == 'w') | |
c19d1205 | 15280 | inst.size_req = 4; |
267d2029 | 15281 | else if (unified_syntax && end[1] == 'n') |
c19d1205 ZW |
15282 | inst.size_req = 2; |
15283 | else | |
5287ad62 JB |
15284 | offset = 0; |
15285 | ||
15286 | inst.vectype.elems = 0; | |
15287 | ||
15288 | *str = end + offset; | |
b99bd4ef | 15289 | |
5f4273c7 | 15290 | if (end[offset] == '.') |
5287ad62 | 15291 | { |
267d2029 JB |
15292 | /* See if we have a Neon type suffix (possible in either unified or |
15293 | non-unified ARM syntax mode). */ | |
dcbf9037 | 15294 | if (parse_neon_type (&inst.vectype, str) == FAIL) |
c921be7d | 15295 | return NULL; |
5287ad62 JB |
15296 | } |
15297 | else if (end[offset] != '\0' && end[offset] != ' ') | |
c921be7d | 15298 | return NULL; |
b99bd4ef | 15299 | } |
c19d1205 ZW |
15300 | else |
15301 | *str = end; | |
b99bd4ef | 15302 | |
c19d1205 | 15303 | /* Look for unaffixed or special-case affixed mnemonic. */ |
21d799b5 NC |
15304 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
15305 | end - base); | |
c19d1205 | 15306 | if (opcode) |
b99bd4ef | 15307 | { |
c19d1205 ZW |
15308 | /* step U */ |
15309 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 15310 | { |
c19d1205 ZW |
15311 | inst.cond = COND_ALWAYS; |
15312 | return opcode; | |
b99bd4ef | 15313 | } |
b99bd4ef | 15314 | |
278df34e | 15315 | if (warn_on_deprecated && unified_syntax) |
c19d1205 ZW |
15316 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
15317 | affix = base + (opcode->tag - OT_odd_infix_0); | |
21d799b5 | 15318 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
9c2799c2 | 15319 | gas_assert (cond); |
b99bd4ef | 15320 | |
c19d1205 ZW |
15321 | inst.cond = cond->value; |
15322 | return opcode; | |
15323 | } | |
b99bd4ef | 15324 | |
c19d1205 ZW |
15325 | /* Cannot have a conditional suffix on a mnemonic of less than two |
15326 | characters. */ | |
15327 | if (end - base < 3) | |
c921be7d | 15328 | return NULL; |
b99bd4ef | 15329 | |
c19d1205 ZW |
15330 | /* Look for suffixed mnemonic. */ |
15331 | affix = end - 2; | |
21d799b5 NC |
15332 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
15333 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, | |
15334 | affix - base); | |
c19d1205 ZW |
15335 | if (opcode && cond) |
15336 | { | |
15337 | /* step CE */ | |
15338 | switch (opcode->tag) | |
15339 | { | |
e3cb604e PB |
15340 | case OT_cinfix3_legacy: |
15341 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
15342 | break; | |
15343 | ||
c19d1205 | 15344 | case OT_cinfix3: |
088fa78e | 15345 | case OT_cinfix3_deprecated: |
c19d1205 ZW |
15346 | case OT_odd_infix_unc: |
15347 | if (!unified_syntax) | |
e3cb604e | 15348 | return 0; |
c19d1205 ZW |
15349 | /* else fall through */ |
15350 | ||
15351 | case OT_csuffix: | |
037e8744 | 15352 | case OT_csuffixF: |
c19d1205 ZW |
15353 | case OT_csuf_or_in3: |
15354 | inst.cond = cond->value; | |
15355 | return opcode; | |
15356 | ||
15357 | case OT_unconditional: | |
15358 | case OT_unconditionalF: | |
dfa9f0d5 | 15359 | if (thumb_mode) |
c921be7d | 15360 | inst.cond = cond->value; |
dfa9f0d5 PB |
15361 | else |
15362 | { | |
c921be7d | 15363 | /* Delayed diagnostic. */ |
dfa9f0d5 PB |
15364 | inst.error = BAD_COND; |
15365 | inst.cond = COND_ALWAYS; | |
15366 | } | |
c19d1205 | 15367 | return opcode; |
b99bd4ef | 15368 | |
c19d1205 | 15369 | default: |
c921be7d | 15370 | return NULL; |
c19d1205 ZW |
15371 | } |
15372 | } | |
b99bd4ef | 15373 | |
c19d1205 ZW |
15374 | /* Cannot have a usual-position infix on a mnemonic of less than |
15375 | six characters (five would be a suffix). */ | |
15376 | if (end - base < 6) | |
c921be7d | 15377 | return NULL; |
b99bd4ef | 15378 | |
c19d1205 ZW |
15379 | /* Look for infixed mnemonic in the usual position. */ |
15380 | affix = base + 3; | |
21d799b5 | 15381 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
e3cb604e | 15382 | if (!cond) |
c921be7d | 15383 | return NULL; |
e3cb604e PB |
15384 | |
15385 | memcpy (save, affix, 2); | |
15386 | memmove (affix, affix + 2, (end - affix) - 2); | |
21d799b5 NC |
15387 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
15388 | (end - base) - 2); | |
e3cb604e PB |
15389 | memmove (affix + 2, affix, (end - affix) - 2); |
15390 | memcpy (affix, save, 2); | |
15391 | ||
088fa78e KH |
15392 | if (opcode |
15393 | && (opcode->tag == OT_cinfix3 | |
15394 | || opcode->tag == OT_cinfix3_deprecated | |
15395 | || opcode->tag == OT_csuf_or_in3 | |
15396 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 15397 | { |
c921be7d | 15398 | /* Step CM. */ |
278df34e | 15399 | if (warn_on_deprecated && unified_syntax |
088fa78e KH |
15400 | && (opcode->tag == OT_cinfix3 |
15401 | || opcode->tag == OT_cinfix3_deprecated)) | |
c19d1205 ZW |
15402 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
15403 | ||
15404 | inst.cond = cond->value; | |
15405 | return opcode; | |
b99bd4ef NC |
15406 | } |
15407 | ||
c921be7d | 15408 | return NULL; |
b99bd4ef NC |
15409 | } |
15410 | ||
e07e6e58 NC |
15411 | /* This function generates an initial IT instruction, leaving its block |
15412 | virtually open for the new instructions. Eventually, | |
15413 | the mask will be updated by now_it_add_mask () each time | |
15414 | a new instruction needs to be included in the IT block. | |
15415 | Finally, the block is closed with close_automatic_it_block (). | |
15416 | The block closure can be requested either from md_assemble (), | |
15417 | a tencode (), or due to a label hook. */ | |
15418 | ||
15419 | static void | |
15420 | new_automatic_it_block (int cond) | |
15421 | { | |
15422 | now_it.state = AUTOMATIC_IT_BLOCK; | |
15423 | now_it.mask = 0x18; | |
15424 | now_it.cc = cond; | |
15425 | now_it.block_length = 1; | |
cd000bff | 15426 | mapping_state (MAP_THUMB); |
e07e6e58 NC |
15427 | now_it.insn = output_it_inst (cond, now_it.mask, NULL); |
15428 | } | |
15429 | ||
15430 | /* Close an automatic IT block. | |
15431 | See comments in new_automatic_it_block (). */ | |
15432 | ||
15433 | static void | |
15434 | close_automatic_it_block (void) | |
15435 | { | |
15436 | now_it.mask = 0x10; | |
15437 | now_it.block_length = 0; | |
15438 | } | |
15439 | ||
15440 | /* Update the mask of the current automatically-generated IT | |
15441 | instruction. See comments in new_automatic_it_block (). */ | |
15442 | ||
15443 | static void | |
15444 | now_it_add_mask (int cond) | |
15445 | { | |
15446 | #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) | |
15447 | #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ | |
15448 | | ((bitvalue) << (nbit))) | |
e07e6e58 | 15449 | const int resulting_bit = (cond & 1); |
c921be7d | 15450 | |
e07e6e58 NC |
15451 | now_it.mask &= 0xf; |
15452 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
15453 | resulting_bit, | |
15454 | (5 - now_it.block_length)); | |
15455 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
15456 | 1, | |
15457 | ((5 - now_it.block_length) - 1) ); | |
15458 | output_it_inst (now_it.cc, now_it.mask, now_it.insn); | |
15459 | ||
15460 | #undef CLEAR_BIT | |
15461 | #undef SET_BIT_VALUE | |
e07e6e58 NC |
15462 | } |
15463 | ||
15464 | /* The IT blocks handling machinery is accessed through the these functions: | |
15465 | it_fsm_pre_encode () from md_assemble () | |
15466 | set_it_insn_type () optional, from the tencode functions | |
15467 | set_it_insn_type_last () ditto | |
15468 | in_it_block () ditto | |
15469 | it_fsm_post_encode () from md_assemble () | |
15470 | force_automatic_it_block_close () from label habdling functions | |
15471 | ||
15472 | Rationale: | |
15473 | 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), | |
15474 | initializing the IT insn type with a generic initial value depending | |
15475 | on the inst.condition. | |
15476 | 2) During the tencode function, two things may happen: | |
15477 | a) The tencode function overrides the IT insn type by | |
15478 | calling either set_it_insn_type (type) or set_it_insn_type_last (). | |
15479 | b) The tencode function queries the IT block state by | |
15480 | calling in_it_block () (i.e. to determine narrow/not narrow mode). | |
15481 | ||
15482 | Both set_it_insn_type and in_it_block run the internal FSM state | |
15483 | handling function (handle_it_state), because: a) setting the IT insn | |
15484 | type may incur in an invalid state (exiting the function), | |
15485 | and b) querying the state requires the FSM to be updated. | |
15486 | Specifically we want to avoid creating an IT block for conditional | |
15487 | branches, so it_fsm_pre_encode is actually a guess and we can't | |
15488 | determine whether an IT block is required until the tencode () routine | |
15489 | has decided what type of instruction this actually it. | |
15490 | Because of this, if set_it_insn_type and in_it_block have to be used, | |
15491 | set_it_insn_type has to be called first. | |
15492 | ||
15493 | set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that | |
15494 | determines the insn IT type depending on the inst.cond code. | |
15495 | When a tencode () routine encodes an instruction that can be | |
15496 | either outside an IT block, or, in the case of being inside, has to be | |
15497 | the last one, set_it_insn_type_last () will determine the proper | |
15498 | IT instruction type based on the inst.cond code. Otherwise, | |
15499 | set_it_insn_type can be called for overriding that logic or | |
15500 | for covering other cases. | |
15501 | ||
15502 | Calling handle_it_state () may not transition the IT block state to | |
15503 | OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be | |
15504 | still queried. Instead, if the FSM determines that the state should | |
15505 | be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed | |
15506 | after the tencode () function: that's what it_fsm_post_encode () does. | |
15507 | ||
15508 | Since in_it_block () calls the state handling function to get an | |
15509 | updated state, an error may occur (due to invalid insns combination). | |
15510 | In that case, inst.error is set. | |
15511 | Therefore, inst.error has to be checked after the execution of | |
15512 | the tencode () routine. | |
15513 | ||
15514 | 3) Back in md_assemble(), it_fsm_post_encode () is called to commit | |
15515 | any pending state change (if any) that didn't take place in | |
15516 | handle_it_state () as explained above. */ | |
15517 | ||
15518 | static void | |
15519 | it_fsm_pre_encode (void) | |
15520 | { | |
15521 | if (inst.cond != COND_ALWAYS) | |
15522 | inst.it_insn_type = INSIDE_IT_INSN; | |
15523 | else | |
15524 | inst.it_insn_type = OUTSIDE_IT_INSN; | |
15525 | ||
15526 | now_it.state_handled = 0; | |
15527 | } | |
15528 | ||
15529 | /* IT state FSM handling function. */ | |
15530 | ||
15531 | static int | |
15532 | handle_it_state (void) | |
15533 | { | |
15534 | now_it.state_handled = 1; | |
15535 | ||
15536 | switch (now_it.state) | |
15537 | { | |
15538 | case OUTSIDE_IT_BLOCK: | |
15539 | switch (inst.it_insn_type) | |
15540 | { | |
15541 | case OUTSIDE_IT_INSN: | |
15542 | break; | |
15543 | ||
15544 | case INSIDE_IT_INSN: | |
15545 | case INSIDE_IT_LAST_INSN: | |
15546 | if (thumb_mode == 0) | |
15547 | { | |
c921be7d | 15548 | if (unified_syntax |
e07e6e58 NC |
15549 | && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) |
15550 | as_tsktsk (_("Warning: conditional outside an IT block"\ | |
15551 | " for Thumb.")); | |
15552 | } | |
15553 | else | |
15554 | { | |
15555 | if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) | |
15556 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)) | |
15557 | { | |
15558 | /* Automatically generate the IT instruction. */ | |
15559 | new_automatic_it_block (inst.cond); | |
15560 | if (inst.it_insn_type == INSIDE_IT_LAST_INSN) | |
15561 | close_automatic_it_block (); | |
15562 | } | |
15563 | else | |
15564 | { | |
15565 | inst.error = BAD_OUT_IT; | |
15566 | return FAIL; | |
15567 | } | |
15568 | } | |
15569 | break; | |
15570 | ||
15571 | case IF_INSIDE_IT_LAST_INSN: | |
15572 | case NEUTRAL_IT_INSN: | |
15573 | break; | |
15574 | ||
15575 | case IT_INSN: | |
15576 | now_it.state = MANUAL_IT_BLOCK; | |
15577 | now_it.block_length = 0; | |
15578 | break; | |
15579 | } | |
15580 | break; | |
15581 | ||
15582 | case AUTOMATIC_IT_BLOCK: | |
15583 | /* Three things may happen now: | |
15584 | a) We should increment current it block size; | |
15585 | b) We should close current it block (closing insn or 4 insns); | |
15586 | c) We should close current it block and start a new one (due | |
15587 | to incompatible conditions or | |
15588 | 4 insns-length block reached). */ | |
15589 | ||
15590 | switch (inst.it_insn_type) | |
15591 | { | |
15592 | case OUTSIDE_IT_INSN: | |
15593 | /* The closure of the block shall happen immediatelly, | |
15594 | so any in_it_block () call reports the block as closed. */ | |
15595 | force_automatic_it_block_close (); | |
15596 | break; | |
15597 | ||
15598 | case INSIDE_IT_INSN: | |
15599 | case INSIDE_IT_LAST_INSN: | |
15600 | case IF_INSIDE_IT_LAST_INSN: | |
15601 | now_it.block_length++; | |
15602 | ||
15603 | if (now_it.block_length > 4 | |
15604 | || !now_it_compatible (inst.cond)) | |
15605 | { | |
15606 | force_automatic_it_block_close (); | |
15607 | if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN) | |
15608 | new_automatic_it_block (inst.cond); | |
15609 | } | |
15610 | else | |
15611 | { | |
15612 | now_it_add_mask (inst.cond); | |
15613 | } | |
15614 | ||
15615 | if (now_it.state == AUTOMATIC_IT_BLOCK | |
15616 | && (inst.it_insn_type == INSIDE_IT_LAST_INSN | |
15617 | || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN)) | |
15618 | close_automatic_it_block (); | |
15619 | break; | |
15620 | ||
15621 | case NEUTRAL_IT_INSN: | |
15622 | now_it.block_length++; | |
15623 | ||
15624 | if (now_it.block_length > 4) | |
15625 | force_automatic_it_block_close (); | |
15626 | else | |
15627 | now_it_add_mask (now_it.cc & 1); | |
15628 | break; | |
15629 | ||
15630 | case IT_INSN: | |
15631 | close_automatic_it_block (); | |
15632 | now_it.state = MANUAL_IT_BLOCK; | |
15633 | break; | |
15634 | } | |
15635 | break; | |
15636 | ||
15637 | case MANUAL_IT_BLOCK: | |
15638 | { | |
15639 | /* Check conditional suffixes. */ | |
15640 | const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1; | |
15641 | int is_last; | |
15642 | now_it.mask <<= 1; | |
15643 | now_it.mask &= 0x1f; | |
15644 | is_last = (now_it.mask == 0x10); | |
15645 | ||
15646 | switch (inst.it_insn_type) | |
15647 | { | |
15648 | case OUTSIDE_IT_INSN: | |
15649 | inst.error = BAD_NOT_IT; | |
15650 | return FAIL; | |
15651 | ||
15652 | case INSIDE_IT_INSN: | |
15653 | if (cond != inst.cond) | |
15654 | { | |
15655 | inst.error = BAD_IT_COND; | |
15656 | return FAIL; | |
15657 | } | |
15658 | break; | |
15659 | ||
15660 | case INSIDE_IT_LAST_INSN: | |
15661 | case IF_INSIDE_IT_LAST_INSN: | |
15662 | if (cond != inst.cond) | |
15663 | { | |
15664 | inst.error = BAD_IT_COND; | |
15665 | return FAIL; | |
15666 | } | |
15667 | if (!is_last) | |
15668 | { | |
15669 | inst.error = BAD_BRANCH; | |
15670 | return FAIL; | |
15671 | } | |
15672 | break; | |
15673 | ||
15674 | case NEUTRAL_IT_INSN: | |
15675 | /* The BKPT instruction is unconditional even in an IT block. */ | |
15676 | break; | |
15677 | ||
15678 | case IT_INSN: | |
15679 | inst.error = BAD_IT_IT; | |
15680 | return FAIL; | |
15681 | } | |
15682 | } | |
15683 | break; | |
15684 | } | |
15685 | ||
15686 | return SUCCESS; | |
15687 | } | |
15688 | ||
15689 | static void | |
15690 | it_fsm_post_encode (void) | |
15691 | { | |
15692 | int is_last; | |
15693 | ||
15694 | if (!now_it.state_handled) | |
15695 | handle_it_state (); | |
15696 | ||
15697 | is_last = (now_it.mask == 0x10); | |
15698 | if (is_last) | |
15699 | { | |
15700 | now_it.state = OUTSIDE_IT_BLOCK; | |
15701 | now_it.mask = 0; | |
15702 | } | |
15703 | } | |
15704 | ||
15705 | static void | |
15706 | force_automatic_it_block_close (void) | |
15707 | { | |
15708 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
15709 | { | |
15710 | close_automatic_it_block (); | |
15711 | now_it.state = OUTSIDE_IT_BLOCK; | |
15712 | now_it.mask = 0; | |
15713 | } | |
15714 | } | |
15715 | ||
15716 | static int | |
15717 | in_it_block (void) | |
15718 | { | |
15719 | if (!now_it.state_handled) | |
15720 | handle_it_state (); | |
15721 | ||
15722 | return now_it.state != OUTSIDE_IT_BLOCK; | |
15723 | } | |
15724 | ||
c19d1205 ZW |
15725 | void |
15726 | md_assemble (char *str) | |
b99bd4ef | 15727 | { |
c19d1205 ZW |
15728 | char *p = str; |
15729 | const struct asm_opcode * opcode; | |
b99bd4ef | 15730 | |
c19d1205 ZW |
15731 | /* Align the previous label if needed. */ |
15732 | if (last_label_seen != NULL) | |
b99bd4ef | 15733 | { |
c19d1205 ZW |
15734 | symbol_set_frag (last_label_seen, frag_now); |
15735 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
15736 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
15737 | } |
15738 | ||
c19d1205 ZW |
15739 | memset (&inst, '\0', sizeof (inst)); |
15740 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 15741 | |
c19d1205 ZW |
15742 | opcode = opcode_lookup (&p); |
15743 | if (!opcode) | |
b99bd4ef | 15744 | { |
c19d1205 | 15745 | /* It wasn't an instruction, but it might be a register alias of |
dcbf9037 | 15746 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
c921be7d NC |
15747 | if (! create_register_alias (str, p) |
15748 | && ! create_neon_reg_alias (str, p)) | |
c19d1205 | 15749 | as_bad (_("bad instruction `%s'"), str); |
b99bd4ef | 15750 | |
b99bd4ef NC |
15751 | return; |
15752 | } | |
15753 | ||
278df34e | 15754 | if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) |
088fa78e KH |
15755 | as_warn (_("s suffix on comparison instruction is deprecated")); |
15756 | ||
037e8744 JB |
15757 | /* The value which unconditional instructions should have in place of the |
15758 | condition field. */ | |
15759 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; | |
15760 | ||
c19d1205 | 15761 | if (thumb_mode) |
b99bd4ef | 15762 | { |
e74cfd16 | 15763 | arm_feature_set variant; |
8f06b2d8 PB |
15764 | |
15765 | variant = cpu_variant; | |
15766 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
15767 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
15768 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 15769 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
15770 | if (!opcode->tvariant |
15771 | || (thumb_mode == 1 | |
15772 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 15773 | { |
bf3eeda7 | 15774 | as_bad (_("selected processor does not support Thumb mode `%s'"), str); |
b99bd4ef NC |
15775 | return; |
15776 | } | |
c19d1205 ZW |
15777 | if (inst.cond != COND_ALWAYS && !unified_syntax |
15778 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 15779 | { |
c19d1205 | 15780 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
15781 | return; |
15782 | } | |
15783 | ||
752d5da4 | 15784 | if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)) |
076d447c | 15785 | { |
7e806470 | 15786 | if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23 |
752d5da4 NC |
15787 | && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr) |
15788 | || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier))) | |
15789 | { | |
15790 | /* Two things are addressed here. | |
15791 | 1) Implicit require narrow instructions on Thumb-1. | |
15792 | This avoids relaxation accidentally introducing Thumb-2 | |
15793 | instructions. | |
15794 | 2) Reject wide instructions in non Thumb-2 cores. */ | |
15795 | if (inst.size_req == 0) | |
15796 | inst.size_req = 2; | |
15797 | else if (inst.size_req == 4) | |
15798 | { | |
bf3eeda7 | 15799 | as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str); |
752d5da4 NC |
15800 | return; |
15801 | } | |
15802 | } | |
076d447c PB |
15803 | } |
15804 | ||
c19d1205 ZW |
15805 | inst.instruction = opcode->tvalue; |
15806 | ||
5be8be5d | 15807 | if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE)) |
e07e6e58 NC |
15808 | { |
15809 | /* Prepare the it_insn_type for those encodings that don't set | |
15810 | it. */ | |
15811 | it_fsm_pre_encode (); | |
c19d1205 | 15812 | |
e07e6e58 NC |
15813 | opcode->tencode (); |
15814 | ||
15815 | it_fsm_post_encode (); | |
15816 | } | |
e27ec89e | 15817 | |
0110f2b8 | 15818 | if (!(inst.error || inst.relax)) |
b99bd4ef | 15819 | { |
9c2799c2 | 15820 | gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
c19d1205 ZW |
15821 | inst.size = (inst.instruction > 0xffff ? 4 : 2); |
15822 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 15823 | { |
c19d1205 | 15824 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
15825 | return; |
15826 | } | |
15827 | } | |
076d447c PB |
15828 | |
15829 | /* Something has gone badly wrong if we try to relax a fixed size | |
15830 | instruction. */ | |
9c2799c2 | 15831 | gas_assert (inst.size_req == 0 || !inst.relax); |
076d447c | 15832 | |
e74cfd16 PB |
15833 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
15834 | *opcode->tvariant); | |
ee065d83 | 15835 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
708587a4 | 15836 | set those bits when Thumb-2 32-bit instructions are seen. ie. |
7e806470 | 15837 | anything other than bl/blx and v6-M instructions. |
ee065d83 | 15838 | This is overly pessimistic for relaxable instructions. */ |
7e806470 PB |
15839 | if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) |
15840 | || inst.relax) | |
e07e6e58 NC |
15841 | && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) |
15842 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))) | |
e74cfd16 PB |
15843 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
15844 | arm_ext_v6t2); | |
cd000bff | 15845 | |
88714cb8 DG |
15846 | check_neon_suffixes; |
15847 | ||
cd000bff | 15848 | if (!inst.error) |
c877a2f2 NC |
15849 | { |
15850 | mapping_state (MAP_THUMB); | |
15851 | } | |
c19d1205 | 15852 | } |
3e9e4fcf | 15853 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 | 15854 | { |
845b51d6 PB |
15855 | bfd_boolean is_bx; |
15856 | ||
15857 | /* bx is allowed on v5 cores, and sometimes on v4 cores. */ | |
15858 | is_bx = (opcode->aencode == do_bx); | |
15859 | ||
c19d1205 | 15860 | /* Check that this instruction is supported for this CPU. */ |
845b51d6 PB |
15861 | if (!(is_bx && fix_v4bx) |
15862 | && !(opcode->avariant && | |
15863 | ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) | |
b99bd4ef | 15864 | { |
bf3eeda7 | 15865 | as_bad (_("selected processor does not support ARM mode `%s'"), str); |
c19d1205 | 15866 | return; |
b99bd4ef | 15867 | } |
c19d1205 | 15868 | if (inst.size_req) |
b99bd4ef | 15869 | { |
c19d1205 ZW |
15870 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
15871 | return; | |
b99bd4ef NC |
15872 | } |
15873 | ||
c19d1205 ZW |
15874 | inst.instruction = opcode->avalue; |
15875 | if (opcode->tag == OT_unconditionalF) | |
15876 | inst.instruction |= 0xF << 28; | |
15877 | else | |
15878 | inst.instruction |= inst.cond << 28; | |
15879 | inst.size = INSN_SIZE; | |
5be8be5d | 15880 | if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE)) |
e07e6e58 NC |
15881 | { |
15882 | it_fsm_pre_encode (); | |
15883 | opcode->aencode (); | |
15884 | it_fsm_post_encode (); | |
15885 | } | |
ee065d83 PB |
15886 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
15887 | on a hypothetical non-thumb v5 core. */ | |
845b51d6 | 15888 | if (is_bx) |
e74cfd16 | 15889 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); |
ee065d83 | 15890 | else |
e74cfd16 PB |
15891 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
15892 | *opcode->avariant); | |
88714cb8 DG |
15893 | |
15894 | check_neon_suffixes; | |
15895 | ||
cd000bff | 15896 | if (!inst.error) |
c877a2f2 NC |
15897 | { |
15898 | mapping_state (MAP_ARM); | |
15899 | } | |
b99bd4ef | 15900 | } |
3e9e4fcf JB |
15901 | else |
15902 | { | |
15903 | as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " | |
15904 | "-- `%s'"), str); | |
15905 | return; | |
15906 | } | |
c19d1205 ZW |
15907 | output_inst (str); |
15908 | } | |
b99bd4ef | 15909 | |
e07e6e58 NC |
15910 | static void |
15911 | check_it_blocks_finished (void) | |
15912 | { | |
15913 | #ifdef OBJ_ELF | |
15914 | asection *sect; | |
15915 | ||
15916 | for (sect = stdoutput->sections; sect != NULL; sect = sect->next) | |
15917 | if (seg_info (sect)->tc_segment_info_data.current_it.state | |
15918 | == MANUAL_IT_BLOCK) | |
15919 | { | |
15920 | as_warn (_("section '%s' finished with an open IT block."), | |
15921 | sect->name); | |
15922 | } | |
15923 | #else | |
15924 | if (now_it.state == MANUAL_IT_BLOCK) | |
15925 | as_warn (_("file finished with an open IT block.")); | |
15926 | #endif | |
15927 | } | |
15928 | ||
c19d1205 ZW |
15929 | /* Various frobbings of labels and their addresses. */ |
15930 | ||
15931 | void | |
15932 | arm_start_line_hook (void) | |
15933 | { | |
15934 | last_label_seen = NULL; | |
b99bd4ef NC |
15935 | } |
15936 | ||
c19d1205 ZW |
15937 | void |
15938 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 15939 | { |
c19d1205 | 15940 | last_label_seen = sym; |
b99bd4ef | 15941 | |
c19d1205 | 15942 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 15943 | |
c19d1205 ZW |
15944 | #if defined OBJ_COFF || defined OBJ_ELF |
15945 | ARM_SET_INTERWORK (sym, support_interwork); | |
15946 | #endif | |
b99bd4ef | 15947 | |
e07e6e58 NC |
15948 | force_automatic_it_block_close (); |
15949 | ||
5f4273c7 | 15950 | /* Note - do not allow local symbols (.Lxxx) to be labelled |
c19d1205 ZW |
15951 | as Thumb functions. This is because these labels, whilst |
15952 | they exist inside Thumb code, are not the entry points for | |
15953 | possible ARM->Thumb calls. Also, these labels can be used | |
15954 | as part of a computed goto or switch statement. eg gcc | |
15955 | can generate code that looks like this: | |
b99bd4ef | 15956 | |
c19d1205 ZW |
15957 | ldr r2, [pc, .Laaa] |
15958 | lsl r3, r3, #2 | |
15959 | ldr r2, [r3, r2] | |
15960 | mov pc, r2 | |
b99bd4ef | 15961 | |
c19d1205 ZW |
15962 | .Lbbb: .word .Lxxx |
15963 | .Lccc: .word .Lyyy | |
15964 | ..etc... | |
15965 | .Laaa: .word Lbbb | |
b99bd4ef | 15966 | |
c19d1205 ZW |
15967 | The first instruction loads the address of the jump table. |
15968 | The second instruction converts a table index into a byte offset. | |
15969 | The third instruction gets the jump address out of the table. | |
15970 | The fourth instruction performs the jump. | |
b99bd4ef | 15971 | |
c19d1205 ZW |
15972 | If the address stored at .Laaa is that of a symbol which has the |
15973 | Thumb_Func bit set, then the linker will arrange for this address | |
15974 | to have the bottom bit set, which in turn would mean that the | |
15975 | address computation performed by the third instruction would end | |
15976 | up with the bottom bit set. Since the ARM is capable of unaligned | |
15977 | word loads, the instruction would then load the incorrect address | |
15978 | out of the jump table, and chaos would ensue. */ | |
15979 | if (label_is_thumb_function_name | |
15980 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
15981 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 15982 | { |
c19d1205 ZW |
15983 | /* When the address of a Thumb function is taken the bottom |
15984 | bit of that address should be set. This will allow | |
15985 | interworking between Arm and Thumb functions to work | |
15986 | correctly. */ | |
b99bd4ef | 15987 | |
c19d1205 | 15988 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 15989 | |
c19d1205 | 15990 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 15991 | } |
07a53e5c | 15992 | |
07a53e5c | 15993 | dwarf2_emit_label (sym); |
b99bd4ef NC |
15994 | } |
15995 | ||
c921be7d | 15996 | bfd_boolean |
c19d1205 | 15997 | arm_data_in_code (void) |
b99bd4ef | 15998 | { |
c19d1205 | 15999 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 16000 | { |
c19d1205 ZW |
16001 | *input_line_pointer = '/'; |
16002 | input_line_pointer += 5; | |
16003 | *input_line_pointer = 0; | |
c921be7d | 16004 | return TRUE; |
b99bd4ef NC |
16005 | } |
16006 | ||
c921be7d | 16007 | return FALSE; |
b99bd4ef NC |
16008 | } |
16009 | ||
c19d1205 ZW |
16010 | char * |
16011 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 16012 | { |
c19d1205 | 16013 | int len; |
b99bd4ef | 16014 | |
c19d1205 ZW |
16015 | if (thumb_mode && (len = strlen (name)) > 5 |
16016 | && streq (name + len - 5, "/data")) | |
16017 | *(name + len - 5) = 0; | |
b99bd4ef | 16018 | |
c19d1205 | 16019 | return name; |
b99bd4ef | 16020 | } |
c19d1205 ZW |
16021 | \f |
16022 | /* Table of all register names defined by default. The user can | |
16023 | define additional names with .req. Note that all register names | |
16024 | should appear in both upper and lowercase variants. Some registers | |
16025 | also have mixed-case names. */ | |
b99bd4ef | 16026 | |
dcbf9037 | 16027 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
c19d1205 | 16028 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
5287ad62 | 16029 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
c19d1205 ZW |
16030 | #define REGSET(p,t) \ |
16031 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
16032 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
16033 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
16034 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
5287ad62 JB |
16035 | #define REGSETH(p,t) \ |
16036 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
16037 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
16038 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
16039 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) | |
16040 | #define REGSET2(p,t) \ | |
16041 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ | |
16042 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ | |
16043 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ | |
16044 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) | |
7ed4c4c5 | 16045 | |
c19d1205 | 16046 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 16047 | { |
c19d1205 ZW |
16048 | /* ARM integer registers. */ |
16049 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 16050 | |
c19d1205 ZW |
16051 | /* ATPCS synonyms. */ |
16052 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
16053 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
16054 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 16055 | |
c19d1205 ZW |
16056 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
16057 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
16058 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 16059 | |
c19d1205 ZW |
16060 | /* Well-known aliases. */ |
16061 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
16062 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
16063 | ||
16064 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
16065 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
16066 | ||
16067 | /* Coprocessor numbers. */ | |
16068 | REGSET(p, CP), REGSET(P, CP), | |
16069 | ||
16070 | /* Coprocessor register numbers. The "cr" variants are for backward | |
16071 | compatibility. */ | |
16072 | REGSET(c, CN), REGSET(C, CN), | |
16073 | REGSET(cr, CN), REGSET(CR, CN), | |
16074 | ||
16075 | /* FPA registers. */ | |
16076 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
16077 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
16078 | ||
16079 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
16080 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
16081 | ||
16082 | /* VFP SP registers. */ | |
5287ad62 JB |
16083 | REGSET(s,VFS), REGSET(S,VFS), |
16084 | REGSETH(s,VFS), REGSETH(S,VFS), | |
c19d1205 ZW |
16085 | |
16086 | /* VFP DP Registers. */ | |
5287ad62 JB |
16087 | REGSET(d,VFD), REGSET(D,VFD), |
16088 | /* Extra Neon DP registers. */ | |
16089 | REGSETH(d,VFD), REGSETH(D,VFD), | |
16090 | ||
16091 | /* Neon QP registers. */ | |
16092 | REGSET2(q,NQ), REGSET2(Q,NQ), | |
c19d1205 ZW |
16093 | |
16094 | /* VFP control registers. */ | |
16095 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
16096 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
cd2cf30b PB |
16097 | REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), |
16098 | REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), | |
16099 | REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), | |
16100 | REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), | |
c19d1205 ZW |
16101 | |
16102 | /* Maverick DSP coprocessor registers. */ | |
16103 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
16104 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
16105 | ||
16106 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
16107 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
16108 | REGDEF(dspsc,0,DSPSC), | |
16109 | ||
16110 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
16111 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
16112 | REGDEF(DSPSC,0,DSPSC), | |
16113 | ||
16114 | /* iWMMXt data registers - p0, c0-15. */ | |
16115 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
16116 | ||
16117 | /* iWMMXt control registers - p1, c0-3. */ | |
16118 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
16119 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
16120 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
16121 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
16122 | ||
16123 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
16124 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
16125 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
16126 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
16127 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
16128 | ||
16129 | /* XScale accumulator registers. */ | |
16130 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
16131 | }; | |
16132 | #undef REGDEF | |
16133 | #undef REGNUM | |
16134 | #undef REGSET | |
7ed4c4c5 | 16135 | |
c19d1205 ZW |
16136 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
16137 | within psr_required_here. */ | |
16138 | static const struct asm_psr psrs[] = | |
16139 | { | |
16140 | /* Backward compatibility notation. Note that "all" is no longer | |
16141 | truly all possible PSR bits. */ | |
16142 | {"all", PSR_c | PSR_f}, | |
16143 | {"flg", PSR_f}, | |
16144 | {"ctl", PSR_c}, | |
16145 | ||
16146 | /* Individual flags. */ | |
16147 | {"f", PSR_f}, | |
16148 | {"c", PSR_c}, | |
16149 | {"x", PSR_x}, | |
16150 | {"s", PSR_s}, | |
16151 | /* Combinations of flags. */ | |
16152 | {"fs", PSR_f | PSR_s}, | |
16153 | {"fx", PSR_f | PSR_x}, | |
16154 | {"fc", PSR_f | PSR_c}, | |
16155 | {"sf", PSR_s | PSR_f}, | |
16156 | {"sx", PSR_s | PSR_x}, | |
16157 | {"sc", PSR_s | PSR_c}, | |
16158 | {"xf", PSR_x | PSR_f}, | |
16159 | {"xs", PSR_x | PSR_s}, | |
16160 | {"xc", PSR_x | PSR_c}, | |
16161 | {"cf", PSR_c | PSR_f}, | |
16162 | {"cs", PSR_c | PSR_s}, | |
16163 | {"cx", PSR_c | PSR_x}, | |
16164 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
16165 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
16166 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
16167 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
16168 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
16169 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
16170 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
16171 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
16172 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
16173 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
16174 | {"scf", PSR_s | PSR_c | PSR_f}, | |
16175 | {"scx", PSR_s | PSR_c | PSR_x}, | |
16176 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
16177 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
16178 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
16179 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
16180 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
16181 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
16182 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
16183 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
16184 | {"csf", PSR_c | PSR_s | PSR_f}, | |
16185 | {"csx", PSR_c | PSR_s | PSR_x}, | |
16186 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
16187 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
16188 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
16189 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
16190 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
16191 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
16192 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
16193 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
16194 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
16195 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
16196 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
16197 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
16198 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
16199 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
16200 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
16201 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
16202 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
16203 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
16204 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
16205 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
16206 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
16207 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
16208 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
16209 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
16210 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
16211 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
16212 | }; | |
16213 | ||
62b3e311 PB |
16214 | /* Table of V7M psr names. */ |
16215 | static const struct asm_psr v7m_psrs[] = | |
16216 | { | |
2b744c99 PB |
16217 | {"apsr", 0 }, {"APSR", 0 }, |
16218 | {"iapsr", 1 }, {"IAPSR", 1 }, | |
16219 | {"eapsr", 2 }, {"EAPSR", 2 }, | |
16220 | {"psr", 3 }, {"PSR", 3 }, | |
16221 | {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, | |
16222 | {"ipsr", 5 }, {"IPSR", 5 }, | |
16223 | {"epsr", 6 }, {"EPSR", 6 }, | |
16224 | {"iepsr", 7 }, {"IEPSR", 7 }, | |
16225 | {"msp", 8 }, {"MSP", 8 }, | |
16226 | {"psp", 9 }, {"PSP", 9 }, | |
16227 | {"primask", 16}, {"PRIMASK", 16}, | |
16228 | {"basepri", 17}, {"BASEPRI", 17}, | |
16229 | {"basepri_max", 18}, {"BASEPRI_MAX", 18}, | |
16230 | {"faultmask", 19}, {"FAULTMASK", 19}, | |
16231 | {"control", 20}, {"CONTROL", 20} | |
62b3e311 PB |
16232 | }; |
16233 | ||
c19d1205 ZW |
16234 | /* Table of all shift-in-operand names. */ |
16235 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 16236 | { |
c19d1205 ZW |
16237 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
16238 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
16239 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
16240 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
16241 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
16242 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
16243 | }; | |
b99bd4ef | 16244 | |
c19d1205 ZW |
16245 | /* Table of all explicit relocation names. */ |
16246 | #ifdef OBJ_ELF | |
16247 | static struct reloc_entry reloc_names[] = | |
16248 | { | |
16249 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
16250 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
16251 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
16252 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
16253 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
16254 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
16255 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
16256 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
16257 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
16258 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
b43420e6 NC |
16259 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}, |
16260 | { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL} | |
c19d1205 ZW |
16261 | }; |
16262 | #endif | |
b99bd4ef | 16263 | |
c19d1205 ZW |
16264 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
16265 | static const struct asm_cond conds[] = | |
16266 | { | |
16267 | {"eq", 0x0}, | |
16268 | {"ne", 0x1}, | |
16269 | {"cs", 0x2}, {"hs", 0x2}, | |
16270 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
16271 | {"mi", 0x4}, | |
16272 | {"pl", 0x5}, | |
16273 | {"vs", 0x6}, | |
16274 | {"vc", 0x7}, | |
16275 | {"hi", 0x8}, | |
16276 | {"ls", 0x9}, | |
16277 | {"ge", 0xa}, | |
16278 | {"lt", 0xb}, | |
16279 | {"gt", 0xc}, | |
16280 | {"le", 0xd}, | |
16281 | {"al", 0xe} | |
16282 | }; | |
bfae80f2 | 16283 | |
62b3e311 PB |
16284 | static struct asm_barrier_opt barrier_opt_names[] = |
16285 | { | |
16286 | { "sy", 0xf }, | |
16287 | { "un", 0x7 }, | |
16288 | { "st", 0xe }, | |
16289 | { "unst", 0x6 } | |
16290 | }; | |
16291 | ||
c19d1205 ZW |
16292 | /* Table of ARM-format instructions. */ |
16293 | ||
16294 | /* Macros for gluing together operand strings. N.B. In all cases | |
16295 | other than OPS0, the trailing OP_stop comes from default | |
16296 | zero-initialization of the unspecified elements of the array. */ | |
16297 | #define OPS0() { OP_stop, } | |
16298 | #define OPS1(a) { OP_##a, } | |
16299 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
16300 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
16301 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
16302 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
16303 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
16304 | ||
5be8be5d DG |
16305 | /* These macros are similar to the OPSn, but do not prepend the OP_ prefix. |
16306 | This is useful when mixing operands for ARM and THUMB, i.e. using the | |
16307 | MIX_ARM_THUMB_OPERANDS macro. | |
16308 | In order to use these macros, prefix the number of operands with _ | |
16309 | e.g. _3. */ | |
16310 | #define OPS_1(a) { a, } | |
16311 | #define OPS_2(a,b) { a,b, } | |
16312 | #define OPS_3(a,b,c) { a,b,c, } | |
16313 | #define OPS_4(a,b,c,d) { a,b,c,d, } | |
16314 | #define OPS_5(a,b,c,d,e) { a,b,c,d,e, } | |
16315 | #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, } | |
16316 | ||
c19d1205 ZW |
16317 | /* These macros abstract out the exact format of the mnemonic table and |
16318 | save some repeated characters. */ | |
16319 | ||
16320 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
16321 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16322 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 16323 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16324 | |
16325 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
16326 | a T_MNEM_xyz enumerator. */ | |
16327 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
e07e6e58 | 16328 | TxCE (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 16329 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 16330 | TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
16331 | |
16332 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
16333 | infix after the third character. */ | |
16334 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16335 | { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 16336 | THUMB_VARIANT, do_##ae, do_##te } |
088fa78e | 16337 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 16338 | { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ |
088fa78e | 16339 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 16340 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 16341 | TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) |
088fa78e | 16342 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 16343 | TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 16344 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 16345 | TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
088fa78e | 16346 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 16347 | TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
16348 | |
16349 | /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to | |
16350 | appear in the condition table. */ | |
16351 | #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16352 | { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ |
1887dd22 | 16353 | 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16354 | |
16355 | #define TxCM(m1, m2, op, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
16356 | TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \ |
16357 | TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \ | |
16358 | TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \ | |
16359 | TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \ | |
16360 | TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \ | |
16361 | TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \ | |
16362 | TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \ | |
16363 | TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \ | |
16364 | TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \ | |
16365 | TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \ | |
16366 | TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \ | |
16367 | TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \ | |
16368 | TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \ | |
16369 | TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \ | |
16370 | TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \ | |
16371 | TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \ | |
16372 | TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \ | |
16373 | TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \ | |
16374 | TxCM_ (m1, al, m2, op, top, nops, ops, ae, te) | |
c19d1205 ZW |
16375 | |
16376 | #define TCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
16377 | TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te) |
16378 | #define tCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
21d799b5 | 16379 | TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
16380 | |
16381 | /* Mnemonic that cannot be conditionalized. The ARM condition-code | |
dfa9f0d5 PB |
16382 | field is still 0xE. Many of the Thumb variants can be executed |
16383 | conditionally, so this is checked separately. */ | |
c19d1205 | 16384 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 16385 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 16386 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16387 | |
16388 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM | |
16389 | condition code field. */ | |
16390 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16391 | { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 16392 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16393 | |
16394 | /* ARM-only variants of all the above. */ | |
6a86118a | 16395 | #define CE(mnem, op, nops, ops, ae) \ |
21d799b5 | 16396 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
6a86118a NC |
16397 | |
16398 | #define C3(mnem, op, nops, ops, ae) \ | |
16399 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
16400 | ||
e3cb604e PB |
16401 | /* Legacy mnemonics that always have conditional infix after the third |
16402 | character. */ | |
16403 | #define CL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16404 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
16405 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
16406 | ||
8f06b2d8 PB |
16407 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
16408 | #define cCE(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16409 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 16410 | |
e3cb604e PB |
16411 | /* Legacy coprocessor instructions where conditional infix and conditional |
16412 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
16413 | not just the potentially ambiguous ones. */ | |
16414 | #define cCL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16415 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
16416 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
16417 | ||
16418 | /* Coprocessor, takes either a suffix or a position-3 infix | |
16419 | (for an FPA corner case). */ | |
16420 | #define C3E(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16421 | { mnem, OPS##nops ops, OT_csuf_or_in3, \ |
e3cb604e | 16422 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 16423 | |
6a86118a | 16424 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
21d799b5 NC |
16425 | { m1 #m2 m3, OPS##nops ops, \ |
16426 | sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ | |
6a86118a NC |
16427 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
16428 | ||
16429 | #define CM(m1, m2, op, nops, ops, ae) \ | |
e07e6e58 NC |
16430 | xCM_ (m1, , m2, op, nops, ops, ae), \ |
16431 | xCM_ (m1, eq, m2, op, nops, ops, ae), \ | |
16432 | xCM_ (m1, ne, m2, op, nops, ops, ae), \ | |
16433 | xCM_ (m1, cs, m2, op, nops, ops, ae), \ | |
16434 | xCM_ (m1, hs, m2, op, nops, ops, ae), \ | |
16435 | xCM_ (m1, cc, m2, op, nops, ops, ae), \ | |
16436 | xCM_ (m1, ul, m2, op, nops, ops, ae), \ | |
16437 | xCM_ (m1, lo, m2, op, nops, ops, ae), \ | |
16438 | xCM_ (m1, mi, m2, op, nops, ops, ae), \ | |
16439 | xCM_ (m1, pl, m2, op, nops, ops, ae), \ | |
16440 | xCM_ (m1, vs, m2, op, nops, ops, ae), \ | |
16441 | xCM_ (m1, vc, m2, op, nops, ops, ae), \ | |
16442 | xCM_ (m1, hi, m2, op, nops, ops, ae), \ | |
16443 | xCM_ (m1, ls, m2, op, nops, ops, ae), \ | |
16444 | xCM_ (m1, ge, m2, op, nops, ops, ae), \ | |
16445 | xCM_ (m1, lt, m2, op, nops, ops, ae), \ | |
16446 | xCM_ (m1, gt, m2, op, nops, ops, ae), \ | |
16447 | xCM_ (m1, le, m2, op, nops, ops, ae), \ | |
16448 | xCM_ (m1, al, m2, op, nops, ops, ae) | |
6a86118a NC |
16449 | |
16450 | #define UE(mnem, op, nops, ops, ae) \ | |
16451 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
16452 | ||
16453 | #define UF(mnem, op, nops, ops, ae) \ | |
16454 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
16455 | ||
5287ad62 JB |
16456 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
16457 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we | |
16458 | use the same encoding function for each. */ | |
16459 | #define NUF(mnem, op, nops, ops, enc) \ | |
16460 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
16461 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } | |
16462 | ||
16463 | /* Neon data processing, version which indirects through neon_enc_tab for | |
16464 | the various overloaded versions of opcodes. */ | |
16465 | #define nUF(mnem, op, nops, ops, enc) \ | |
21d799b5 | 16466 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
16467 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
16468 | ||
16469 | /* Neon insn with conditional suffix for the ARM version, non-overloaded | |
16470 | version. */ | |
037e8744 JB |
16471 | #define NCE_tag(mnem, op, nops, ops, enc, tag) \ |
16472 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ | |
5287ad62 JB |
16473 | THUMB_VARIANT, do_##enc, do_##enc } |
16474 | ||
037e8744 | 16475 | #define NCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 16476 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
16477 | |
16478 | #define NCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 16479 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 16480 | |
5287ad62 | 16481 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
037e8744 | 16482 | #define nCE_tag(mnem, op, nops, ops, enc, tag) \ |
21d799b5 | 16483 | { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
16484 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
16485 | ||
037e8744 | 16486 | #define nCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 16487 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
16488 | |
16489 | #define nCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 16490 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 16491 | |
c19d1205 ZW |
16492 | #define do_0 0 |
16493 | ||
c19d1205 | 16494 | static const struct asm_opcode insns[] = |
bfae80f2 | 16495 | { |
e74cfd16 PB |
16496 | #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ |
16497 | #define THUMB_VARIANT &arm_ext_v4t | |
21d799b5 NC |
16498 | tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c), |
16499 | tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
16500 | tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
16501 | tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
16502 | tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
16503 | tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
16504 | tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub), | |
16505 | tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub), | |
16506 | tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
16507 | tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
16508 | tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
16509 | tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
16510 | tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
16511 | tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
16512 | tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3), | |
16513 | tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3), | |
c19d1205 ZW |
16514 | |
16515 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
16516 | for setting PSR flag bits. They are obsolete in V6 and do not | |
16517 | have Thumb equivalents. */ | |
21d799b5 NC |
16518 | tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), |
16519 | tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), | |
16520 | CL("tstp", 110f000, 2, (RR, SH), cmp), | |
16521 | tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
16522 | tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
16523 | CL("cmpp", 150f000, 2, (RR, SH), cmp), | |
16524 | tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
16525 | tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
16526 | CL("cmnp", 170f000, 2, (RR, SH), cmp), | |
16527 | ||
16528 | tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp), | |
16529 | tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp), | |
16530 | tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst), | |
16531 | tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst), | |
16532 | ||
16533 | tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
5be8be5d DG |
16534 | tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), |
16535 | tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR, | |
16536 | OP_RRnpc), | |
16537 | OP_ADDRGLDR),ldst, t_ldst), | |
16538 | tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), | |
21d799b5 NC |
16539 | |
16540 | tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16541 | tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16542 | tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16543 | tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16544 | tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16545 | tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16546 | ||
16547 | TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), | |
16548 | TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), | |
16549 | tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), | |
16550 | TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), | |
bfae80f2 | 16551 | |
c19d1205 | 16552 | /* Pseudo ops. */ |
21d799b5 | 16553 | tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac | 16554 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
21d799b5 | 16555 | tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop), |
c19d1205 ZW |
16556 | |
16557 | /* Thumb-compatibility pseudo ops. */ | |
21d799b5 NC |
16558 | tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift), |
16559 | tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift), | |
16560 | tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift), | |
16561 | tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
16562 | tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift), | |
16563 | tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift), | |
16564 | tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift), | |
16565 | tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift), | |
16566 | tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg), | |
16567 | tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg), | |
16568 | tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop), | |
16569 | tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop), | |
c19d1205 | 16570 | |
16a4cf17 | 16571 | /* These may simplify to neg. */ |
21d799b5 NC |
16572 | TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
16573 | TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
16a4cf17 | 16574 | |
c921be7d NC |
16575 | #undef THUMB_VARIANT |
16576 | #define THUMB_VARIANT & arm_ext_v6 | |
16577 | ||
21d799b5 | 16578 | TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
16579 | |
16580 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
c921be7d NC |
16581 | #undef THUMB_VARIANT |
16582 | #define THUMB_VARIANT & arm_ext_v6t2 | |
16583 | ||
21d799b5 NC |
16584 | TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
16585 | TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
16586 | CL("teqp", 130f000, 2, (RR, SH), cmp), | |
c19d1205 | 16587 | |
5be8be5d DG |
16588 | TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
16589 | TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
16590 | TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt), | |
16591 | TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
c19d1205 | 16592 | |
21d799b5 NC |
16593 | TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
16594 | TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 16595 | |
21d799b5 NC |
16596 | TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
16597 | TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
16598 | |
16599 | /* V1 instructions with no Thumb analogue at all. */ | |
21d799b5 | 16600 | CE("rsc", 0e00000, 3, (RR, oRR, SH), arit), |
c19d1205 ZW |
16601 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), |
16602 | ||
16603 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
16604 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
16605 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
16606 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
16607 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
16608 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
16609 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
16610 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
16611 | ||
c921be7d NC |
16612 | #undef ARM_VARIANT |
16613 | #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ | |
16614 | #undef THUMB_VARIANT | |
16615 | #define THUMB_VARIANT & arm_ext_v4t | |
16616 | ||
21d799b5 NC |
16617 | tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
16618 | tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
c19d1205 | 16619 | |
c921be7d NC |
16620 | #undef THUMB_VARIANT |
16621 | #define THUMB_VARIANT & arm_ext_v6t2 | |
16622 | ||
21d799b5 | 16623 | TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
c19d1205 ZW |
16624 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), |
16625 | ||
16626 | /* Generic coprocessor instructions. */ | |
21d799b5 NC |
16627 | TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
16628 | TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16629 | TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16630 | TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16631 | TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16632 | TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
16633 | TCE("mrc", e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 16634 | |
c921be7d NC |
16635 | #undef ARM_VARIANT |
16636 | #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ | |
16637 | ||
21d799b5 | 16638 | CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
c19d1205 ZW |
16639 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
16640 | ||
c921be7d NC |
16641 | #undef ARM_VARIANT |
16642 | #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ | |
16643 | #undef THUMB_VARIANT | |
16644 | #define THUMB_VARIANT & arm_ext_msr | |
16645 | ||
21d799b5 NC |
16646 | TCE("mrs", 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs), |
16647 | TCE("msr", 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr), | |
c19d1205 | 16648 | |
c921be7d NC |
16649 | #undef ARM_VARIANT |
16650 | #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ | |
16651 | #undef THUMB_VARIANT | |
16652 | #define THUMB_VARIANT & arm_ext_v6t2 | |
16653 | ||
21d799b5 NC |
16654 | TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
16655 | CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
16656 | TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
16657 | CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
16658 | TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
16659 | CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
16660 | TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
16661 | CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
c19d1205 | 16662 | |
c921be7d NC |
16663 | #undef ARM_VARIANT |
16664 | #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ | |
16665 | #undef THUMB_VARIANT | |
16666 | #define THUMB_VARIANT & arm_ext_v4t | |
16667 | ||
5be8be5d DG |
16668 | tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
16669 | tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
16670 | tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
16671 | tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
16672 | tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
16673 | tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
c19d1205 | 16674 | |
c921be7d NC |
16675 | #undef ARM_VARIANT |
16676 | #define ARM_VARIANT & arm_ext_v4t_5 | |
16677 | ||
c19d1205 ZW |
16678 | /* ARM Architecture 4T. */ |
16679 | /* Note: bx (and blx) are required on V5, even if the processor does | |
16680 | not support Thumb. */ | |
21d799b5 | 16681 | TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx), |
c19d1205 | 16682 | |
c921be7d NC |
16683 | #undef ARM_VARIANT |
16684 | #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ | |
16685 | #undef THUMB_VARIANT | |
16686 | #define THUMB_VARIANT & arm_ext_v5t | |
16687 | ||
c19d1205 ZW |
16688 | /* Note: blx has 2 variants; the .value coded here is for |
16689 | BLX(2). Only this variant has conditional execution. */ | |
21d799b5 NC |
16690 | TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx), |
16691 | TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
c19d1205 | 16692 | |
c921be7d NC |
16693 | #undef THUMB_VARIANT |
16694 | #define THUMB_VARIANT & arm_ext_v6t2 | |
16695 | ||
21d799b5 NC |
16696 | TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
16697 | TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16698 | TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16699 | TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16700 | TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
16701 | TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
16702 | TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
16703 | TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 16704 | |
c921be7d NC |
16705 | #undef ARM_VARIANT |
16706 | #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ | |
9e3c6df6 PB |
16707 | #undef THUMB_VARIANT |
16708 | #define THUMB_VARIANT &arm_ext_v5exp | |
c921be7d | 16709 | |
21d799b5 NC |
16710 | TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
16711 | TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
16712 | TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
16713 | TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 16714 | |
21d799b5 NC |
16715 | TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
16716 | TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 16717 | |
21d799b5 NC |
16718 | TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
16719 | TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
16720 | TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
16721 | TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
c19d1205 | 16722 | |
21d799b5 NC |
16723 | TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
16724 | TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16725 | TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16726 | TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 16727 | |
21d799b5 NC |
16728 | TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
16729 | TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 16730 | |
03ee1b7f NC |
16731 | TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
16732 | TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
16733 | TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
16734 | TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
c19d1205 | 16735 | |
c921be7d NC |
16736 | #undef ARM_VARIANT |
16737 | #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ | |
9e3c6df6 PB |
16738 | #undef THUMB_VARIANT |
16739 | #define THUMB_VARIANT &arm_ext_v6t2 | |
c921be7d | 16740 | |
21d799b5 | 16741 | TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld), |
5be8be5d DG |
16742 | TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS), |
16743 | ldrd, t_ldstd), | |
16744 | TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp, | |
16745 | ADDRGLDRS), ldrd, t_ldstd), | |
c19d1205 | 16746 | |
21d799b5 NC |
16747 | TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
16748 | TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
c19d1205 | 16749 | |
c921be7d NC |
16750 | #undef ARM_VARIANT |
16751 | #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ | |
16752 | ||
21d799b5 | 16753 | TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
c19d1205 | 16754 | |
c921be7d NC |
16755 | #undef ARM_VARIANT |
16756 | #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ | |
16757 | #undef THUMB_VARIANT | |
16758 | #define THUMB_VARIANT & arm_ext_v6 | |
16759 | ||
21d799b5 NC |
16760 | TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
16761 | TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
16762 | tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
16763 | tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
16764 | tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
16765 | tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16766 | tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16767 | tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16768 | tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16769 | TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), | |
c19d1205 | 16770 | |
c921be7d NC |
16771 | #undef THUMB_VARIANT |
16772 | #define THUMB_VARIANT & arm_ext_v6t2 | |
16773 | ||
5be8be5d DG |
16774 | TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), |
16775 | TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
16776 | strex, t_strex), | |
21d799b5 NC |
16777 | TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
16778 | TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 | 16779 | |
21d799b5 NC |
16780 | TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), |
16781 | TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
62b3e311 | 16782 | |
9e3c6df6 | 16783 | /* ARM V6 not included in V7M. */ |
c921be7d NC |
16784 | #undef THUMB_VARIANT |
16785 | #define THUMB_VARIANT & arm_ext_v6_notm | |
9e3c6df6 PB |
16786 | TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
16787 | UF(rfeib, 9900a00, 1, (RRw), rfe), | |
16788 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
16789 | TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
16790 | TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
16791 | UF(rfefa, 9900a00, 1, (RRw), rfe), | |
16792 | UF(rfeea, 8100a00, 1, (RRw), rfe), | |
16793 | TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
16794 | TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), | |
16795 | UF(srsib, 9c00500, 2, (oRRw, I31w), srs), | |
16796 | UF(srsda, 8400500, 2, (oRRw, I31w), srs), | |
16797 | TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), | |
c921be7d | 16798 | |
9e3c6df6 PB |
16799 | /* ARM V6 not included in V7M (eg. integer SIMD). */ |
16800 | #undef THUMB_VARIANT | |
16801 | #define THUMB_VARIANT & arm_ext_v6_dsp | |
21d799b5 NC |
16802 | TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
16803 | TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), | |
16804 | TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
16805 | TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16806 | TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16807 | TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16808 | /* Old name for QASX. */ |
21d799b5 NC |
16809 | TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16810 | TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16811 | /* Old name for QSAX. */ |
21d799b5 NC |
16812 | TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16813 | TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16814 | TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16815 | TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16816 | TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16817 | TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16818 | /* Old name for SASX. */ |
21d799b5 NC |
16819 | TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16820 | TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16821 | TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16822 | TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16823 | /* Old name for SHASX. */ |
21d799b5 NC |
16824 | TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16825 | TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16826 | /* Old name for SHSAX. */ |
21d799b5 NC |
16827 | TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16828 | TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16829 | TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16830 | TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16831 | /* Old name for SSAX. */ |
21d799b5 NC |
16832 | TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16833 | TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16834 | TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16835 | TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16836 | TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16837 | TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16838 | /* Old name for UASX. */ |
21d799b5 NC |
16839 | TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16840 | TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16841 | TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16842 | TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16843 | /* Old name for UHASX. */ |
21d799b5 NC |
16844 | TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16845 | TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16846 | /* Old name for UHSAX. */ |
21d799b5 NC |
16847 | TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16848 | TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16849 | TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16850 | TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16851 | TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16852 | TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16853 | /* Old name for UQASX. */ |
21d799b5 NC |
16854 | TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16855 | TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16856 | /* Old name for UQSAX. */ |
21d799b5 NC |
16857 | TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16858 | TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16859 | TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16860 | TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16861 | TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 16862 | /* Old name for USAX. */ |
21d799b5 NC |
16863 | TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
16864 | TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
21d799b5 NC |
16865 | TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
16866 | TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16867 | TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16868 | TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16869 | TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16870 | TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16871 | TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
16872 | TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
16873 | TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
16874 | TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16875 | TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16876 | TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
16877 | TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
16878 | TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16879 | TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16880 | TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
16881 | TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
16882 | TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16883 | TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16884 | TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16885 | TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16886 | TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16887 | TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16888 | TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16889 | TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16890 | TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16891 | TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
21d799b5 NC |
16892 | TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
16893 | TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
16894 | TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
16895 | TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
16896 | TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
c19d1205 | 16897 | |
c921be7d NC |
16898 | #undef ARM_VARIANT |
16899 | #define ARM_VARIANT & arm_ext_v6k | |
16900 | #undef THUMB_VARIANT | |
16901 | #define THUMB_VARIANT & arm_ext_v6k | |
16902 | ||
21d799b5 NC |
16903 | tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), |
16904 | tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), | |
16905 | tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint), | |
16906 | tCE("sev", 320f004, _sev, 0, (), noargs, t_hint), | |
c19d1205 | 16907 | |
c921be7d NC |
16908 | #undef THUMB_VARIANT |
16909 | #define THUMB_VARIANT & arm_ext_v6_notm | |
5be8be5d DG |
16910 | TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb), |
16911 | ldrexd, t_ldrexd), | |
16912 | TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp, | |
16913 | RRnpcb), strexd, t_strexd), | |
ebdca51a | 16914 | |
c921be7d NC |
16915 | #undef THUMB_VARIANT |
16916 | #define THUMB_VARIANT & arm_ext_v6t2 | |
5be8be5d DG |
16917 | TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), |
16918 | rd_rn, rd_rn), | |
16919 | TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), | |
16920 | rd_rn, rd_rn), | |
16921 | TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
16922 | strex, rm_rd_rn), | |
16923 | TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
16924 | strex, rm_rd_rn), | |
21d799b5 | 16925 | TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
c19d1205 | 16926 | |
c921be7d NC |
16927 | #undef ARM_VARIANT |
16928 | #define ARM_VARIANT & arm_ext_v6z | |
16929 | ||
21d799b5 | 16930 | TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 | 16931 | |
c921be7d NC |
16932 | #undef ARM_VARIANT |
16933 | #define ARM_VARIANT & arm_ext_v6t2 | |
16934 | ||
21d799b5 NC |
16935 | TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
16936 | TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
16937 | TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
16938 | TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
c19d1205 | 16939 | |
21d799b5 NC |
16940 | TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
16941 | TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), | |
16942 | TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), | |
16943 | TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), | |
c19d1205 | 16944 | |
5be8be5d DG |
16945 | TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
16946 | TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
16947 | TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
16948 | TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
c19d1205 | 16949 | |
bf3eeda7 NS |
16950 | /* Thumb-only instructions. */ |
16951 | #undef ARM_VARIANT | |
16952 | #define ARM_VARIANT NULL | |
16953 | TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz), | |
16954 | TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz), | |
c921be7d NC |
16955 | |
16956 | /* ARM does not really have an IT instruction, so always allow it. | |
16957 | The opcode is copied from Thumb in order to allow warnings in | |
16958 | -mimplicit-it=[never | arm] modes. */ | |
16959 | #undef ARM_VARIANT | |
16960 | #define ARM_VARIANT & arm_ext_v1 | |
16961 | ||
21d799b5 NC |
16962 | TUE("it", bf08, bf08, 1, (COND), it, t_it), |
16963 | TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), | |
16964 | TUE("ite", bf04, bf04, 1, (COND), it, t_it), | |
16965 | TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it), | |
16966 | TUE("itet", bf06, bf06, 1, (COND), it, t_it), | |
16967 | TUE("itte", bf0a, bf0a, 1, (COND), it, t_it), | |
16968 | TUE("itee", bf02, bf02, 1, (COND), it, t_it), | |
16969 | TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it), | |
16970 | TUE("itett", bf07, bf07, 1, (COND), it, t_it), | |
16971 | TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it), | |
16972 | TUE("iteet", bf03, bf03, 1, (COND), it, t_it), | |
16973 | TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it), | |
16974 | TUE("itete", bf05, bf05, 1, (COND), it, t_it), | |
16975 | TUE("ittee", bf09, bf09, 1, (COND), it, t_it), | |
16976 | TUE("iteee", bf01, bf01, 1, (COND), it, t_it), | |
1c444d06 | 16977 | /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ |
21d799b5 NC |
16978 | TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), |
16979 | TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), | |
c19d1205 | 16980 | |
92e90b6e | 16981 | /* Thumb2 only instructions. */ |
c921be7d NC |
16982 | #undef ARM_VARIANT |
16983 | #define ARM_VARIANT NULL | |
92e90b6e | 16984 | |
21d799b5 NC |
16985 | TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
16986 | TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
16987 | TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), | |
16988 | TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), | |
16989 | TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb), | |
16990 | TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb), | |
92e90b6e | 16991 | |
62b3e311 | 16992 | /* Thumb-2 hardware division instructions (R and M profiles only). */ |
c921be7d NC |
16993 | #undef THUMB_VARIANT |
16994 | #define THUMB_VARIANT & arm_ext_div | |
16995 | ||
21d799b5 NC |
16996 | TCE("sdiv", 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div), |
16997 | TCE("udiv", 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div), | |
62b3e311 | 16998 | |
7e806470 | 16999 | /* ARM V6M/V7 instructions. */ |
c921be7d NC |
17000 | #undef ARM_VARIANT |
17001 | #define ARM_VARIANT & arm_ext_barrier | |
17002 | #undef THUMB_VARIANT | |
17003 | #define THUMB_VARIANT & arm_ext_barrier | |
17004 | ||
21d799b5 NC |
17005 | TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier), |
17006 | TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier), | |
17007 | TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier), | |
7e806470 | 17008 | |
62b3e311 | 17009 | /* ARM V7 instructions. */ |
c921be7d NC |
17010 | #undef ARM_VARIANT |
17011 | #define ARM_VARIANT & arm_ext_v7 | |
17012 | #undef THUMB_VARIANT | |
17013 | #define THUMB_VARIANT & arm_ext_v7 | |
17014 | ||
21d799b5 NC |
17015 | TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld), |
17016 | TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
62b3e311 | 17017 | |
c921be7d NC |
17018 | #undef ARM_VARIANT |
17019 | #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ | |
17020 | ||
21d799b5 NC |
17021 | cCE("wfs", e200110, 1, (RR), rd), |
17022 | cCE("rfs", e300110, 1, (RR), rd), | |
17023 | cCE("wfc", e400110, 1, (RR), rd), | |
17024 | cCE("rfc", e500110, 1, (RR), rd), | |
17025 | ||
17026 | cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17027 | cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17028 | cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17029 | cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17030 | ||
17031 | cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17032 | cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17033 | cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17034 | cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17035 | ||
17036 | cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm), | |
17037 | cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm), | |
17038 | cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm), | |
17039 | cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm), | |
17040 | cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm), | |
17041 | cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm), | |
17042 | cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm), | |
17043 | cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm), | |
17044 | cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm), | |
17045 | cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm), | |
17046 | cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm), | |
17047 | cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm), | |
17048 | ||
17049 | cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm), | |
17050 | cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm), | |
17051 | cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm), | |
17052 | cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm), | |
17053 | cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm), | |
17054 | cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm), | |
17055 | cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm), | |
17056 | cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm), | |
17057 | cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm), | |
17058 | cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm), | |
17059 | cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm), | |
17060 | cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm), | |
17061 | ||
17062 | cCL("abss", e208100, 2, (RF, RF_IF), rd_rm), | |
17063 | cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm), | |
17064 | cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm), | |
17065 | cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm), | |
17066 | cCL("absd", e208180, 2, (RF, RF_IF), rd_rm), | |
17067 | cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm), | |
17068 | cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm), | |
17069 | cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm), | |
17070 | cCL("abse", e288100, 2, (RF, RF_IF), rd_rm), | |
17071 | cCL("absep", e288120, 2, (RF, RF_IF), rd_rm), | |
17072 | cCL("absem", e288140, 2, (RF, RF_IF), rd_rm), | |
17073 | cCL("absez", e288160, 2, (RF, RF_IF), rd_rm), | |
17074 | ||
17075 | cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm), | |
17076 | cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm), | |
17077 | cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm), | |
17078 | cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm), | |
17079 | cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm), | |
17080 | cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm), | |
17081 | cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm), | |
17082 | cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm), | |
17083 | cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm), | |
17084 | cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm), | |
17085 | cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm), | |
17086 | cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm), | |
17087 | ||
17088 | cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm), | |
17089 | cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm), | |
17090 | cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm), | |
17091 | cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm), | |
17092 | cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm), | |
17093 | cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm), | |
17094 | cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm), | |
17095 | cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm), | |
17096 | cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm), | |
17097 | cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm), | |
17098 | cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm), | |
17099 | cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm), | |
17100 | ||
17101 | cCL("logs", e508100, 2, (RF, RF_IF), rd_rm), | |
17102 | cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm), | |
17103 | cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm), | |
17104 | cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm), | |
17105 | cCL("logd", e508180, 2, (RF, RF_IF), rd_rm), | |
17106 | cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm), | |
17107 | cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm), | |
17108 | cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm), | |
17109 | cCL("loge", e588100, 2, (RF, RF_IF), rd_rm), | |
17110 | cCL("logep", e588120, 2, (RF, RF_IF), rd_rm), | |
17111 | cCL("logem", e588140, 2, (RF, RF_IF), rd_rm), | |
17112 | cCL("logez", e588160, 2, (RF, RF_IF), rd_rm), | |
17113 | ||
17114 | cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm), | |
17115 | cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm), | |
17116 | cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm), | |
17117 | cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm), | |
17118 | cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm), | |
17119 | cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm), | |
17120 | cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm), | |
17121 | cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm), | |
17122 | cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm), | |
17123 | cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm), | |
17124 | cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm), | |
17125 | cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm), | |
17126 | ||
17127 | cCL("exps", e708100, 2, (RF, RF_IF), rd_rm), | |
17128 | cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm), | |
17129 | cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm), | |
17130 | cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm), | |
17131 | cCL("expd", e708180, 2, (RF, RF_IF), rd_rm), | |
17132 | cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm), | |
17133 | cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm), | |
17134 | cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm), | |
17135 | cCL("expe", e788100, 2, (RF, RF_IF), rd_rm), | |
17136 | cCL("expep", e788120, 2, (RF, RF_IF), rd_rm), | |
17137 | cCL("expem", e788140, 2, (RF, RF_IF), rd_rm), | |
17138 | cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm), | |
17139 | ||
17140 | cCL("sins", e808100, 2, (RF, RF_IF), rd_rm), | |
17141 | cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm), | |
17142 | cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm), | |
17143 | cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm), | |
17144 | cCL("sind", e808180, 2, (RF, RF_IF), rd_rm), | |
17145 | cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm), | |
17146 | cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm), | |
17147 | cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm), | |
17148 | cCL("sine", e888100, 2, (RF, RF_IF), rd_rm), | |
17149 | cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm), | |
17150 | cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm), | |
17151 | cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm), | |
17152 | ||
17153 | cCL("coss", e908100, 2, (RF, RF_IF), rd_rm), | |
17154 | cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm), | |
17155 | cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm), | |
17156 | cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm), | |
17157 | cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm), | |
17158 | cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm), | |
17159 | cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm), | |
17160 | cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm), | |
17161 | cCL("cose", e988100, 2, (RF, RF_IF), rd_rm), | |
17162 | cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm), | |
17163 | cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm), | |
17164 | cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm), | |
17165 | ||
17166 | cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm), | |
17167 | cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm), | |
17168 | cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm), | |
17169 | cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm), | |
17170 | cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm), | |
17171 | cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm), | |
17172 | cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm), | |
17173 | cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm), | |
17174 | cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm), | |
17175 | cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm), | |
17176 | cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm), | |
17177 | cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm), | |
17178 | ||
17179 | cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm), | |
17180 | cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm), | |
17181 | cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm), | |
17182 | cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm), | |
17183 | cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm), | |
17184 | cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm), | |
17185 | cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm), | |
17186 | cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm), | |
17187 | cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm), | |
17188 | cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm), | |
17189 | cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm), | |
17190 | cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm), | |
17191 | ||
17192 | cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm), | |
17193 | cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm), | |
17194 | cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm), | |
17195 | cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm), | |
17196 | cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm), | |
17197 | cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm), | |
17198 | cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm), | |
17199 | cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm), | |
17200 | cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm), | |
17201 | cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm), | |
17202 | cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm), | |
17203 | cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm), | |
17204 | ||
17205 | cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm), | |
17206 | cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm), | |
17207 | cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm), | |
17208 | cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm), | |
17209 | cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm), | |
17210 | cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm), | |
17211 | cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm), | |
17212 | cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm), | |
17213 | cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm), | |
17214 | cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm), | |
17215 | cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm), | |
17216 | cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm), | |
17217 | ||
17218 | cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm), | |
17219 | cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm), | |
17220 | cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm), | |
17221 | cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm), | |
17222 | cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm), | |
17223 | cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm), | |
17224 | cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm), | |
17225 | cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm), | |
17226 | cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm), | |
17227 | cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm), | |
17228 | cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm), | |
17229 | cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm), | |
17230 | ||
17231 | cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm), | |
17232 | cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm), | |
17233 | cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm), | |
17234 | cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm), | |
17235 | cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm), | |
17236 | cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm), | |
17237 | cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm), | |
17238 | cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm), | |
17239 | cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm), | |
17240 | cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm), | |
17241 | cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm), | |
17242 | cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm), | |
17243 | ||
17244 | cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17245 | cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17246 | cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17247 | cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17248 | cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17249 | cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17250 | cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17251 | cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17252 | cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17253 | cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17254 | cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17255 | cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17256 | ||
17257 | cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17258 | cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17259 | cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17260 | cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17261 | cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17262 | cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17263 | cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17264 | cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17265 | cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17266 | cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17267 | cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17268 | cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17269 | ||
17270 | cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17271 | cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17272 | cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17273 | cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17274 | cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17275 | cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17276 | cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17277 | cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17278 | cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17279 | cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17280 | cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17281 | cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17282 | ||
17283 | cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17284 | cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17285 | cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17286 | cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17287 | cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17288 | cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17289 | cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17290 | cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17291 | cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17292 | cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17293 | cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17294 | cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17295 | ||
17296 | cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17297 | cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17298 | cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17299 | cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17300 | cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17301 | cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17302 | cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17303 | cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17304 | cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17305 | cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17306 | cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17307 | cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17308 | ||
17309 | cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17310 | cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17311 | cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17312 | cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17313 | cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17314 | cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17315 | cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17316 | cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17317 | cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17318 | cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17319 | cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17320 | cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17321 | ||
17322 | cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17323 | cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17324 | cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17325 | cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17326 | cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17327 | cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17328 | cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17329 | cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17330 | cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17331 | cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17332 | cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17333 | cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17334 | ||
17335 | cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17336 | cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17337 | cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17338 | cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17339 | cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17340 | cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17341 | cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17342 | cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17343 | cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17344 | cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17345 | cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17346 | cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17347 | ||
17348 | cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17349 | cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17350 | cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17351 | cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17352 | cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17353 | cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17354 | cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17355 | cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17356 | cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17357 | cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17358 | cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17359 | cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17360 | ||
17361 | cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17362 | cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17363 | cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17364 | cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17365 | cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17366 | cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17367 | cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17368 | cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17369 | cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17370 | cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17371 | cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17372 | cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17373 | ||
17374 | cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17375 | cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17376 | cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17377 | cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17378 | cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17379 | cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17380 | cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17381 | cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17382 | cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17383 | cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17384 | cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17385 | cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17386 | ||
17387 | cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17388 | cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17389 | cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17390 | cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17391 | cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17392 | cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17393 | cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17394 | cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17395 | cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17396 | cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17397 | cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17398 | cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17399 | ||
17400 | cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17401 | cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17402 | cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17403 | cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17404 | cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17405 | cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17406 | cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17407 | cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17408 | cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17409 | cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17410 | cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17411 | cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17412 | ||
17413 | cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp), | |
17414 | C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp), | |
17415 | cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp), | |
17416 | C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp), | |
17417 | ||
17418 | cCL("flts", e000110, 2, (RF, RR), rn_rd), | |
17419 | cCL("fltsp", e000130, 2, (RF, RR), rn_rd), | |
17420 | cCL("fltsm", e000150, 2, (RF, RR), rn_rd), | |
17421 | cCL("fltsz", e000170, 2, (RF, RR), rn_rd), | |
17422 | cCL("fltd", e000190, 2, (RF, RR), rn_rd), | |
17423 | cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd), | |
17424 | cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd), | |
17425 | cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd), | |
17426 | cCL("flte", e080110, 2, (RF, RR), rn_rd), | |
17427 | cCL("fltep", e080130, 2, (RF, RR), rn_rd), | |
17428 | cCL("fltem", e080150, 2, (RF, RR), rn_rd), | |
17429 | cCL("fltez", e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 17430 | |
c19d1205 ZW |
17431 | /* The implementation of the FIX instruction is broken on some |
17432 | assemblers, in that it accepts a precision specifier as well as a | |
17433 | rounding specifier, despite the fact that this is meaningless. | |
17434 | To be more compatible, we accept it as well, though of course it | |
17435 | does not set any bits. */ | |
21d799b5 NC |
17436 | cCE("fix", e100110, 2, (RR, RF), rd_rm), |
17437 | cCL("fixp", e100130, 2, (RR, RF), rd_rm), | |
17438 | cCL("fixm", e100150, 2, (RR, RF), rd_rm), | |
17439 | cCL("fixz", e100170, 2, (RR, RF), rd_rm), | |
17440 | cCL("fixsp", e100130, 2, (RR, RF), rd_rm), | |
17441 | cCL("fixsm", e100150, 2, (RR, RF), rd_rm), | |
17442 | cCL("fixsz", e100170, 2, (RR, RF), rd_rm), | |
17443 | cCL("fixdp", e100130, 2, (RR, RF), rd_rm), | |
17444 | cCL("fixdm", e100150, 2, (RR, RF), rd_rm), | |
17445 | cCL("fixdz", e100170, 2, (RR, RF), rd_rm), | |
17446 | cCL("fixep", e100130, 2, (RR, RF), rd_rm), | |
17447 | cCL("fixem", e100150, 2, (RR, RF), rd_rm), | |
17448 | cCL("fixez", e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 17449 | |
c19d1205 | 17450 | /* Instructions that were new with the real FPA, call them V2. */ |
c921be7d NC |
17451 | #undef ARM_VARIANT |
17452 | #define ARM_VARIANT & fpu_fpa_ext_v2 | |
17453 | ||
21d799b5 NC |
17454 | cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
17455 | cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
17456 | cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
17457 | cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
17458 | cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
17459 | cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 | 17460 | |
c921be7d NC |
17461 | #undef ARM_VARIANT |
17462 | #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ | |
17463 | ||
c19d1205 | 17464 | /* Moves and type conversions. */ |
21d799b5 NC |
17465 | cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
17466 | cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
17467 | cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
17468 | cCE("fmstat", ef1fa10, 0, (), noargs), | |
f7c21dc7 NC |
17469 | cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs), |
17470 | cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr), | |
21d799b5 NC |
17471 | cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), |
17472 | cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
17473 | cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
17474 | cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
17475 | cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
17476 | cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
17477 | cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn), | |
17478 | cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
17479 | |
17480 | /* Memory operations. */ | |
21d799b5 NC |
17481 | cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
17482 | cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), | |
55881a11 MGD |
17483 | cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
17484 | cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
17485 | cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
17486 | cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
17487 | cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
17488 | cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
17489 | cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
17490 | cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
17491 | cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
17492 | cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
17493 | cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
17494 | cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
17495 | cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
17496 | cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
17497 | cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
17498 | cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 17499 | |
c19d1205 | 17500 | /* Monadic operations. */ |
21d799b5 NC |
17501 | cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
17502 | cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
17503 | cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
17504 | |
17505 | /* Dyadic operations. */ | |
21d799b5 NC |
17506 | cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
17507 | cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17508 | cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17509 | cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17510 | cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17511 | cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17512 | cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17513 | cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17514 | cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 17515 | |
c19d1205 | 17516 | /* Comparisons. */ |
21d799b5 NC |
17517 | cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
17518 | cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z), | |
17519 | cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
17520 | cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 17521 | |
62f3b8c8 PB |
17522 | /* Double precision load/store are still present on single precision |
17523 | implementations. */ | |
17524 | cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
17525 | cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
55881a11 MGD |
17526 | cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
17527 | cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
17528 | cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
17529 | cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
17530 | cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
17531 | cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
17532 | cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
17533 | cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
62f3b8c8 | 17534 | |
c921be7d NC |
17535 | #undef ARM_VARIANT |
17536 | #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ | |
17537 | ||
c19d1205 | 17538 | /* Moves and type conversions. */ |
21d799b5 NC |
17539 | cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
17540 | cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
17541 | cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
17542 | cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
17543 | cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
17544 | cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
17545 | cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
17546 | cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
17547 | cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
17548 | cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
17549 | cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
17550 | cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
17551 | cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 | 17552 | |
c19d1205 | 17553 | /* Monadic operations. */ |
21d799b5 NC |
17554 | cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
17555 | cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), | |
17556 | cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
c19d1205 ZW |
17557 | |
17558 | /* Dyadic operations. */ | |
21d799b5 NC |
17559 | cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
17560 | cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17561 | cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17562 | cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17563 | cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17564 | cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17565 | cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17566 | cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17567 | cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
b99bd4ef | 17568 | |
c19d1205 | 17569 | /* Comparisons. */ |
21d799b5 NC |
17570 | cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
17571 | cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd), | |
17572 | cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
17573 | cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd), | |
c19d1205 | 17574 | |
c921be7d NC |
17575 | #undef ARM_VARIANT |
17576 | #define ARM_VARIANT & fpu_vfp_ext_v2 | |
17577 | ||
21d799b5 NC |
17578 | cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
17579 | cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
17580 | cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), | |
17581 | cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), | |
5287ad62 | 17582 | |
037e8744 JB |
17583 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
17584 | Individual encoder functions perform additional architecture checks. */ | |
c921be7d NC |
17585 | #undef ARM_VARIANT |
17586 | #define ARM_VARIANT & fpu_vfp_ext_v1xd | |
17587 | #undef THUMB_VARIANT | |
17588 | #define THUMB_VARIANT & fpu_vfp_ext_v1xd | |
17589 | ||
037e8744 JB |
17590 | /* These mnemonics are unique to VFP. */ |
17591 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), | |
17592 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), | |
21d799b5 NC |
17593 | nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
17594 | nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
17595 | nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
17596 | nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
17597 | nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
037e8744 JB |
17598 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), |
17599 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), | |
17600 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), | |
17601 | ||
17602 | /* Mnemonics shared by Neon and VFP. */ | |
21d799b5 NC |
17603 | nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), |
17604 | nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
17605 | nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
037e8744 | 17606 | |
21d799b5 NC |
17607 | nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), |
17608 | nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), | |
037e8744 JB |
17609 | |
17610 | NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
17611 | NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
17612 | ||
55881a11 MGD |
17613 | NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
17614 | NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
17615 | NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
17616 | NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
17617 | NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
17618 | NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
4962c51a MS |
17619 | NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), |
17620 | NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), | |
037e8744 | 17621 | |
e3e535bc NC |
17622 | nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt), |
17623 | nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr), | |
21d799b5 NC |
17624 | nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb), |
17625 | nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt), | |
f31fef98 | 17626 | |
037e8744 JB |
17627 | |
17628 | /* NOTE: All VMOV encoding is special-cased! */ | |
17629 | NCE(vmov, 0, 1, (VMOV), neon_mov), | |
17630 | NCE(vmovq, 0, 1, (VMOV), neon_mov), | |
17631 | ||
c921be7d NC |
17632 | #undef THUMB_VARIANT |
17633 | #define THUMB_VARIANT & fpu_neon_ext_v1 | |
17634 | #undef ARM_VARIANT | |
17635 | #define ARM_VARIANT & fpu_neon_ext_v1 | |
17636 | ||
5287ad62 JB |
17637 | /* Data processing with three registers of the same length. */ |
17638 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ | |
17639 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), | |
17640 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), | |
17641 | NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
17642 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
17643 | NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
17644 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
17645 | NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
17646 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
17647 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ | |
17648 | NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
17649 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
17650 | NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
17651 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
627907b7 JB |
17652 | NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), |
17653 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
17654 | NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), | |
17655 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
5287ad62 JB |
17656 | /* If not immediate, fall back to neon_dyadic_i64_su. |
17657 | shl_imm should accept I8 I16 I32 I64, | |
17658 | qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ | |
21d799b5 NC |
17659 | nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), |
17660 | nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), | |
17661 | nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), | |
17662 | nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), | |
5287ad62 | 17663 | /* Logic ops, types optional & ignored. */ |
4316f0d2 DG |
17664 | nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), |
17665 | nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
17666 | nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
17667 | nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
17668 | nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
17669 | nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
17670 | nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
17671 | nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
17672 | nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), | |
17673 | nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic), | |
5287ad62 JB |
17674 | /* Bitfield ops, untyped. */ |
17675 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
17676 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
17677 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
17678 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
17679 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
17680 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
17681 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ | |
21d799b5 NC |
17682 | nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), |
17683 | nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
17684 | nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
17685 | nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
17686 | nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
17687 | nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
5287ad62 JB |
17688 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall |
17689 | back to neon_dyadic_if_su. */ | |
21d799b5 NC |
17690 | nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), |
17691 | nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
17692 | nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
17693 | nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
17694 | nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
17695 | nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
17696 | nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
17697 | nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
428e3f1f | 17698 | /* Comparison. Type I8 I16 I32 F32. */ |
21d799b5 NC |
17699 | nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), |
17700 | nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), | |
5287ad62 | 17701 | /* As above, D registers only. */ |
21d799b5 NC |
17702 | nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), |
17703 | nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
5287ad62 | 17704 | /* Int and float variants, signedness unimportant. */ |
21d799b5 NC |
17705 | nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
17706 | nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), | |
17707 | nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), | |
5287ad62 | 17708 | /* Add/sub take types I8 I16 I32 I64 F32. */ |
21d799b5 NC |
17709 | nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
17710 | nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), | |
5287ad62 JB |
17711 | /* vtst takes sizes 8, 16, 32. */ |
17712 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), | |
17713 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), | |
17714 | /* VMUL takes I8 I16 I32 F32 P8. */ | |
21d799b5 | 17715 | nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
5287ad62 | 17716 | /* VQD{R}MULH takes S16 S32. */ |
21d799b5 NC |
17717 | nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), |
17718 | nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
17719 | nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
17720 | nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
5287ad62 JB |
17721 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), |
17722 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
17723 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
17724 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
92559b5b PB |
17725 | NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
17726 | NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
17727 | NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
17728 | NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
5287ad62 JB |
17729 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
17730 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
17731 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
17732 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
17733 | ||
17734 | /* Two address, int/float. Types S8 S16 S32 F32. */ | |
5287ad62 | 17735 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
5287ad62 JB |
17736 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
17737 | ||
17738 | /* Data processing with two registers and a shift amount. */ | |
17739 | /* Right shifts, and variants with rounding. | |
17740 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ | |
17741 | NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
17742 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
17743 | NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
17744 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
17745 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
17746 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
17747 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
17748 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
17749 | /* Shift and insert. Sizes accepted 8 16 32 64. */ | |
17750 | NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), | |
17751 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), | |
17752 | NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), | |
17753 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), | |
17754 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ | |
17755 | NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), | |
17756 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), | |
17757 | /* Right shift immediate, saturating & narrowing, with rounding variants. | |
17758 | Types accepted S16 S32 S64 U16 U32 U64. */ | |
17759 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
17760 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
17761 | /* As above, unsigned. Types accepted S16 S32 S64. */ | |
17762 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
17763 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
17764 | /* Right shift narrowing. Types accepted I16 I32 I64. */ | |
17765 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
17766 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
17767 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ | |
21d799b5 | 17768 | nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll), |
5287ad62 | 17769 | /* CVT with optional immediate for fixed-point variant. */ |
21d799b5 | 17770 | nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
b7fc2769 | 17771 | |
4316f0d2 DG |
17772 | nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn), |
17773 | nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn), | |
5287ad62 JB |
17774 | |
17775 | /* Data processing, three registers of different lengths. */ | |
17776 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ | |
17777 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), | |
17778 | NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), | |
17779 | NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), | |
17780 | NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), | |
17781 | /* If not scalar, fall back to neon_dyadic_long. | |
17782 | Vector types as above, scalar types S16 S32 U16 U32. */ | |
21d799b5 NC |
17783 | nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), |
17784 | nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
5287ad62 JB |
17785 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ |
17786 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
17787 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
17788 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ | |
17789 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
17790 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
17791 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
17792 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
17793 | /* Saturating doubling multiplies. Types S16 S32. */ | |
21d799b5 NC |
17794 | nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
17795 | nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
17796 | nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
5287ad62 JB |
17797 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types |
17798 | S16 S32 U16 U32. */ | |
21d799b5 | 17799 | nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), |
5287ad62 JB |
17800 | |
17801 | /* Extract. Size 8. */ | |
3b8d421e PB |
17802 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), |
17803 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), | |
5287ad62 JB |
17804 | |
17805 | /* Two registers, miscellaneous. */ | |
17806 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ | |
17807 | NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), | |
17808 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), | |
17809 | NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), | |
17810 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), | |
17811 | NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), | |
17812 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), | |
17813 | /* Vector replicate. Sizes 8 16 32. */ | |
21d799b5 NC |
17814 | nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup), |
17815 | nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup), | |
5287ad62 JB |
17816 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ |
17817 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), | |
17818 | /* VMOVN. Types I16 I32 I64. */ | |
21d799b5 | 17819 | nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn), |
5287ad62 | 17820 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ |
21d799b5 | 17821 | nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn), |
5287ad62 | 17822 | /* VQMOVUN. Types S16 S32 S64. */ |
21d799b5 | 17823 | nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun), |
5287ad62 JB |
17824 | /* VZIP / VUZP. Sizes 8 16 32. */ |
17825 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
17826 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), | |
17827 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
17828 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), | |
17829 | /* VQABS / VQNEG. Types S8 S16 S32. */ | |
17830 | NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
17831 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
17832 | NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
17833 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
17834 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ | |
17835 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), | |
17836 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), | |
17837 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), | |
17838 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), | |
17839 | /* Reciprocal estimates. Types U32 F32. */ | |
17840 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), | |
17841 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), | |
17842 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), | |
17843 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), | |
17844 | /* VCLS. Types S8 S16 S32. */ | |
17845 | NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), | |
17846 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), | |
17847 | /* VCLZ. Types I8 I16 I32. */ | |
17848 | NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), | |
17849 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), | |
17850 | /* VCNT. Size 8. */ | |
17851 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), | |
17852 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), | |
17853 | /* Two address, untyped. */ | |
17854 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), | |
17855 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), | |
17856 | /* VTRN. Sizes 8 16 32. */ | |
21d799b5 NC |
17857 | nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn), |
17858 | nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn), | |
5287ad62 JB |
17859 | |
17860 | /* Table lookup. Size 8. */ | |
17861 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
17862 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
17863 | ||
c921be7d NC |
17864 | #undef THUMB_VARIANT |
17865 | #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext | |
17866 | #undef ARM_VARIANT | |
17867 | #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext | |
17868 | ||
5287ad62 | 17869 | /* Neon element/structure load/store. */ |
21d799b5 NC |
17870 | nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), |
17871 | nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17872 | nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17873 | nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17874 | nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17875 | nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17876 | nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
17877 | nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
5287ad62 | 17878 | |
c921be7d | 17879 | #undef THUMB_VARIANT |
62f3b8c8 PB |
17880 | #define THUMB_VARIANT &fpu_vfp_ext_v3xd |
17881 | #undef ARM_VARIANT | |
17882 | #define ARM_VARIANT &fpu_vfp_ext_v3xd | |
17883 | cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const), | |
17884 | cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
17885 | cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
17886 | cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
17887 | cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
17888 | cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
17889 | cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
17890 | cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
17891 | cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
17892 | ||
17893 | #undef THUMB_VARIANT | |
c921be7d NC |
17894 | #define THUMB_VARIANT & fpu_vfp_ext_v3 |
17895 | #undef ARM_VARIANT | |
17896 | #define ARM_VARIANT & fpu_vfp_ext_v3 | |
17897 | ||
21d799b5 | 17898 | cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const), |
21d799b5 | 17899 | cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 17900 | cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 17901 | cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 17902 | cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 17903 | cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 17904 | cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 17905 | cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 17906 | cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
c19d1205 | 17907 | |
62f3b8c8 PB |
17908 | #undef ARM_VARIANT |
17909 | #define ARM_VARIANT &fpu_vfp_ext_fma | |
17910 | #undef THUMB_VARIANT | |
17911 | #define THUMB_VARIANT &fpu_vfp_ext_fma | |
17912 | /* Mnemonics shared by Neon and VFP. These are included in the | |
17913 | VFP FMA variant; NEON and VFP FMA always includes the NEON | |
17914 | FMA instructions. */ | |
17915 | nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
17916 | nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
17917 | /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas; | |
17918 | the v form should always be used. */ | |
17919 | cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17920 | cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17921 | cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17922 | cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
17923 | nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
17924 | nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
17925 | ||
5287ad62 | 17926 | #undef THUMB_VARIANT |
c921be7d NC |
17927 | #undef ARM_VARIANT |
17928 | #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ | |
17929 | ||
21d799b5 NC |
17930 | cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
17931 | cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
17932 | cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
17933 | cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
17934 | cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
17935 | cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
17936 | cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
17937 | cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 | 17938 | |
c921be7d NC |
17939 | #undef ARM_VARIANT |
17940 | #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ | |
17941 | ||
21d799b5 NC |
17942 | cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc), |
17943 | cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc), | |
17944 | cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc), | |
17945 | cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd), | |
17946 | cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd), | |
17947 | cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd), | |
17948 | cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc), | |
17949 | cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc), | |
17950 | cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc), | |
17951 | cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17952 | cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17953 | cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17954 | cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17955 | cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17956 | cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
17957 | cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
17958 | cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
17959 | cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
17960 | cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd), | |
17961 | cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
17962 | cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17963 | cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17964 | cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17965 | cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17966 | cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17967 | cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
17968 | cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn), | |
17969 | cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn), | |
17970 | cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn), | |
17971 | cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn), | |
17972 | cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
17973 | cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc), | |
17974 | cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc), | |
17975 | cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc), | |
17976 | cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn), | |
17977 | cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn), | |
17978 | cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn), | |
17979 | cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17980 | cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17981 | cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17982 | cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17983 | cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17984 | cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17985 | cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17986 | cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17987 | cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17988 | cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
17989 | cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17990 | cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17991 | cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17992 | cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17993 | cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17994 | cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17995 | cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17996 | cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17997 | cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17998 | cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
17999 | cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18000 | cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18001 | cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18002 | cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18003 | cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18004 | cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18005 | cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18006 | cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18007 | cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18008 | cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18009 | cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18010 | cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
18011 | cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
18012 | cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18013 | cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18014 | cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18015 | cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18016 | cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18017 | cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18018 | cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18019 | cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18020 | cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18021 | cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18022 | cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18023 | cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18024 | cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18025 | cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18026 | cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18027 | cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18028 | cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18029 | cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18030 | cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
18031 | cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18032 | cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18033 | cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18034 | cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18035 | cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18036 | cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18037 | cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18038 | cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18039 | cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18040 | cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18041 | cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18042 | cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18043 | cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18044 | cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18045 | cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18046 | cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18047 | cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18048 | cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18049 | cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18050 | cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18051 | cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18052 | cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
18053 | cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18054 | cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18055 | cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18056 | cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18057 | cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18058 | cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18059 | cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18060 | cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18061 | cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18062 | cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18063 | cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18064 | cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18065 | cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18066 | cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18067 | cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18068 | cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18069 | cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18070 | cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18071 | cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18072 | cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18073 | cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
18074 | cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
18075 | cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18076 | cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18077 | cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18078 | cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18079 | cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18080 | cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18081 | cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18082 | cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18083 | cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18084 | cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn), | |
18085 | cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn), | |
18086 | cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn), | |
18087 | cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn), | |
18088 | cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn), | |
18089 | cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn), | |
18090 | cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18091 | cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18092 | cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18093 | cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn), | |
18094 | cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn), | |
18095 | cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn), | |
18096 | cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn), | |
18097 | cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn), | |
18098 | cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn), | |
18099 | cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18100 | cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18101 | cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18102 | cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18103 | cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 | 18104 | |
c921be7d NC |
18105 | #undef ARM_VARIANT |
18106 | #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ | |
18107 | ||
21d799b5 NC |
18108 | cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc), |
18109 | cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc), | |
18110 | cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc), | |
18111 | cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn), | |
18112 | cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn), | |
18113 | cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn), | |
18114 | cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18115 | cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18116 | cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18117 | cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18118 | cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18119 | cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18120 | cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18121 | cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18122 | cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18123 | cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18124 | cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18125 | cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18126 | cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18127 | cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18128 | cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), | |
18129 | cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18130 | cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18131 | cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18132 | cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18133 | cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18134 | cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18135 | cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18136 | cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18137 | cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18138 | cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18139 | cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18140 | cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18141 | cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18142 | cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18143 | cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18144 | cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18145 | cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18146 | cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18147 | cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18148 | cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18149 | cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18150 | cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18151 | cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18152 | cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18153 | cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18154 | cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18155 | cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18156 | cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18157 | cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18158 | cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18159 | cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18160 | cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18161 | cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18162 | cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18163 | cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18164 | cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
2d447fca | 18165 | |
c921be7d NC |
18166 | #undef ARM_VARIANT |
18167 | #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ | |
18168 | ||
21d799b5 NC |
18169 | cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
18170 | cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
18171 | cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
18172 | cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
18173 | cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), | |
18174 | cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
18175 | cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
18176 | cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
18177 | cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd), | |
18178 | cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn), | |
18179 | cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd), | |
18180 | cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn), | |
18181 | cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd), | |
18182 | cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn), | |
18183 | cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd), | |
18184 | cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn), | |
18185 | cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd), | |
18186 | cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn), | |
18187 | cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn), | |
18188 | cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn), | |
18189 | cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn), | |
18190 | cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn), | |
18191 | cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn), | |
18192 | cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn), | |
18193 | cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn), | |
18194 | cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn), | |
18195 | cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn), | |
18196 | cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn), | |
18197 | cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc), | |
18198 | cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd), | |
18199 | cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn), | |
18200 | cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn), | |
18201 | cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn), | |
18202 | cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn), | |
18203 | cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn), | |
18204 | cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn), | |
18205 | cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn), | |
18206 | cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn), | |
18207 | cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn), | |
18208 | cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn), | |
18209 | cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn), | |
18210 | cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn), | |
18211 | cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple), | |
18212 | cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
18213 | cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift), | |
18214 | cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
18215 | cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
18216 | cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
18217 | cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
18218 | cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
18219 | cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn), | |
18220 | cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn), | |
18221 | cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn), | |
18222 | cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn), | |
18223 | cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18224 | cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18225 | cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18226 | cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18227 | cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18228 | cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18229 | cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn), | |
18230 | cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn), | |
18231 | cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn), | |
18232 | cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn), | |
18233 | cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18234 | cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18235 | cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18236 | cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18237 | cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18238 | cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18239 | cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18240 | cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18241 | cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
18242 | cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
18243 | cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
18244 | cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
18245 | }; |
18246 | #undef ARM_VARIANT | |
18247 | #undef THUMB_VARIANT | |
18248 | #undef TCE | |
18249 | #undef TCM | |
18250 | #undef TUE | |
18251 | #undef TUF | |
18252 | #undef TCC | |
8f06b2d8 | 18253 | #undef cCE |
e3cb604e PB |
18254 | #undef cCL |
18255 | #undef C3E | |
c19d1205 ZW |
18256 | #undef CE |
18257 | #undef CM | |
18258 | #undef UE | |
18259 | #undef UF | |
18260 | #undef UT | |
5287ad62 JB |
18261 | #undef NUF |
18262 | #undef nUF | |
18263 | #undef NCE | |
18264 | #undef nCE | |
c19d1205 ZW |
18265 | #undef OPS0 |
18266 | #undef OPS1 | |
18267 | #undef OPS2 | |
18268 | #undef OPS3 | |
18269 | #undef OPS4 | |
18270 | #undef OPS5 | |
18271 | #undef OPS6 | |
18272 | #undef do_0 | |
18273 | \f | |
18274 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 18275 | |
c19d1205 ZW |
18276 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
18277 | for use in the a.out file, and stores them in the array pointed to by buf. | |
18278 | This knows about the endian-ness of the target machine and does | |
18279 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
18280 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
18281 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 18282 | |
c19d1205 ZW |
18283 | void |
18284 | md_number_to_chars (char * buf, valueT val, int n) | |
18285 | { | |
18286 | if (target_big_endian) | |
18287 | number_to_chars_bigendian (buf, val, n); | |
18288 | else | |
18289 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
18290 | } |
18291 | ||
c19d1205 ZW |
18292 | static valueT |
18293 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 18294 | { |
c19d1205 ZW |
18295 | valueT result = 0; |
18296 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 18297 | |
c19d1205 | 18298 | if (target_big_endian) |
b99bd4ef | 18299 | { |
c19d1205 ZW |
18300 | while (n--) |
18301 | { | |
18302 | result <<= 8; | |
18303 | result |= (*where++ & 255); | |
18304 | } | |
b99bd4ef | 18305 | } |
c19d1205 | 18306 | else |
b99bd4ef | 18307 | { |
c19d1205 ZW |
18308 | while (n--) |
18309 | { | |
18310 | result <<= 8; | |
18311 | result |= (where[n] & 255); | |
18312 | } | |
bfae80f2 | 18313 | } |
b99bd4ef | 18314 | |
c19d1205 | 18315 | return result; |
bfae80f2 | 18316 | } |
b99bd4ef | 18317 | |
c19d1205 | 18318 | /* MD interface: Sections. */ |
b99bd4ef | 18319 | |
0110f2b8 PB |
18320 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
18321 | 2 bytes. */ | |
18322 | ||
c19d1205 | 18323 | int |
0110f2b8 | 18324 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
18325 | segT segtype ATTRIBUTE_UNUSED) |
18326 | { | |
0110f2b8 PB |
18327 | fragp->fr_var = 2; |
18328 | return 2; | |
18329 | } | |
18330 | ||
18331 | /* Convert a machine dependent frag. */ | |
18332 | ||
18333 | void | |
18334 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
18335 | { | |
18336 | unsigned long insn; | |
18337 | unsigned long old_op; | |
18338 | char *buf; | |
18339 | expressionS exp; | |
18340 | fixS *fixp; | |
18341 | int reloc_type; | |
18342 | int pc_rel; | |
18343 | int opcode; | |
18344 | ||
18345 | buf = fragp->fr_literal + fragp->fr_fix; | |
18346 | ||
18347 | old_op = bfd_get_16(abfd, buf); | |
5f4273c7 NC |
18348 | if (fragp->fr_symbol) |
18349 | { | |
0110f2b8 PB |
18350 | exp.X_op = O_symbol; |
18351 | exp.X_add_symbol = fragp->fr_symbol; | |
5f4273c7 NC |
18352 | } |
18353 | else | |
18354 | { | |
0110f2b8 | 18355 | exp.X_op = O_constant; |
5f4273c7 | 18356 | } |
0110f2b8 PB |
18357 | exp.X_add_number = fragp->fr_offset; |
18358 | opcode = fragp->fr_subtype; | |
18359 | switch (opcode) | |
18360 | { | |
18361 | case T_MNEM_ldr_pc: | |
18362 | case T_MNEM_ldr_pc2: | |
18363 | case T_MNEM_ldr_sp: | |
18364 | case T_MNEM_str_sp: | |
18365 | case T_MNEM_ldr: | |
18366 | case T_MNEM_ldrb: | |
18367 | case T_MNEM_ldrh: | |
18368 | case T_MNEM_str: | |
18369 | case T_MNEM_strb: | |
18370 | case T_MNEM_strh: | |
18371 | if (fragp->fr_var == 4) | |
18372 | { | |
5f4273c7 | 18373 | insn = THUMB_OP32 (opcode); |
0110f2b8 PB |
18374 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) |
18375 | { | |
18376 | insn |= (old_op & 0x700) << 4; | |
18377 | } | |
18378 | else | |
18379 | { | |
18380 | insn |= (old_op & 7) << 12; | |
18381 | insn |= (old_op & 0x38) << 13; | |
18382 | } | |
18383 | insn |= 0x00000c00; | |
18384 | put_thumb32_insn (buf, insn); | |
18385 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
18386 | } | |
18387 | else | |
18388 | { | |
18389 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
18390 | } | |
18391 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
18392 | break; | |
18393 | case T_MNEM_adr: | |
18394 | if (fragp->fr_var == 4) | |
18395 | { | |
18396 | insn = THUMB_OP32 (opcode); | |
18397 | insn |= (old_op & 0xf0) << 4; | |
18398 | put_thumb32_insn (buf, insn); | |
18399 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
18400 | } | |
18401 | else | |
18402 | { | |
18403 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
18404 | exp.X_add_number -= 4; | |
18405 | } | |
18406 | pc_rel = 1; | |
18407 | break; | |
18408 | case T_MNEM_mov: | |
18409 | case T_MNEM_movs: | |
18410 | case T_MNEM_cmp: | |
18411 | case T_MNEM_cmn: | |
18412 | if (fragp->fr_var == 4) | |
18413 | { | |
18414 | int r0off = (opcode == T_MNEM_mov | |
18415 | || opcode == T_MNEM_movs) ? 0 : 8; | |
18416 | insn = THUMB_OP32 (opcode); | |
18417 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
18418 | insn |= (old_op & 0x700) << r0off; | |
18419 | put_thumb32_insn (buf, insn); | |
18420 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
18421 | } | |
18422 | else | |
18423 | { | |
18424 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
18425 | } | |
18426 | pc_rel = 0; | |
18427 | break; | |
18428 | case T_MNEM_b: | |
18429 | if (fragp->fr_var == 4) | |
18430 | { | |
18431 | insn = THUMB_OP32(opcode); | |
18432 | put_thumb32_insn (buf, insn); | |
18433 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
18434 | } | |
18435 | else | |
18436 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
18437 | pc_rel = 1; | |
18438 | break; | |
18439 | case T_MNEM_bcond: | |
18440 | if (fragp->fr_var == 4) | |
18441 | { | |
18442 | insn = THUMB_OP32(opcode); | |
18443 | insn |= (old_op & 0xf00) << 14; | |
18444 | put_thumb32_insn (buf, insn); | |
18445 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
18446 | } | |
18447 | else | |
18448 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
18449 | pc_rel = 1; | |
18450 | break; | |
18451 | case T_MNEM_add_sp: | |
18452 | case T_MNEM_add_pc: | |
18453 | case T_MNEM_inc_sp: | |
18454 | case T_MNEM_dec_sp: | |
18455 | if (fragp->fr_var == 4) | |
18456 | { | |
18457 | /* ??? Choose between add and addw. */ | |
18458 | insn = THUMB_OP32 (opcode); | |
18459 | insn |= (old_op & 0xf0) << 4; | |
18460 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
18461 | if (opcode == T_MNEM_add_pc) |
18462 | reloc_type = BFD_RELOC_ARM_T32_IMM12; | |
18463 | else | |
18464 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
0110f2b8 PB |
18465 | } |
18466 | else | |
18467 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
18468 | pc_rel = 0; | |
18469 | break; | |
18470 | ||
18471 | case T_MNEM_addi: | |
18472 | case T_MNEM_addis: | |
18473 | case T_MNEM_subi: | |
18474 | case T_MNEM_subis: | |
18475 | if (fragp->fr_var == 4) | |
18476 | { | |
18477 | insn = THUMB_OP32 (opcode); | |
18478 | insn |= (old_op & 0xf0) << 4; | |
18479 | insn |= (old_op & 0xf) << 16; | |
18480 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
18481 | if (insn & (1 << 20)) |
18482 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
18483 | else | |
18484 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
0110f2b8 PB |
18485 | } |
18486 | else | |
18487 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
18488 | pc_rel = 0; | |
18489 | break; | |
18490 | default: | |
5f4273c7 | 18491 | abort (); |
0110f2b8 PB |
18492 | } |
18493 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
21d799b5 | 18494 | (enum bfd_reloc_code_real) reloc_type); |
0110f2b8 PB |
18495 | fixp->fx_file = fragp->fr_file; |
18496 | fixp->fx_line = fragp->fr_line; | |
18497 | fragp->fr_fix += fragp->fr_var; | |
18498 | } | |
18499 | ||
18500 | /* Return the size of a relaxable immediate operand instruction. | |
18501 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
18502 | static int | |
18503 | relax_immediate (fragS *fragp, int size, int shift) | |
18504 | { | |
18505 | offsetT offset; | |
18506 | offsetT mask; | |
18507 | offsetT low; | |
18508 | ||
18509 | /* ??? Should be able to do better than this. */ | |
18510 | if (fragp->fr_symbol) | |
18511 | return 4; | |
18512 | ||
18513 | low = (1 << shift) - 1; | |
18514 | mask = (1 << (shift + size)) - (1 << shift); | |
18515 | offset = fragp->fr_offset; | |
18516 | /* Force misaligned offsets to 32-bit variant. */ | |
18517 | if (offset & low) | |
5e77afaa | 18518 | return 4; |
0110f2b8 PB |
18519 | if (offset & ~mask) |
18520 | return 4; | |
18521 | return 2; | |
18522 | } | |
18523 | ||
5e77afaa PB |
18524 | /* Get the address of a symbol during relaxation. */ |
18525 | static addressT | |
5f4273c7 | 18526 | relaxed_symbol_addr (fragS *fragp, long stretch) |
5e77afaa PB |
18527 | { |
18528 | fragS *sym_frag; | |
18529 | addressT addr; | |
18530 | symbolS *sym; | |
18531 | ||
18532 | sym = fragp->fr_symbol; | |
18533 | sym_frag = symbol_get_frag (sym); | |
18534 | know (S_GET_SEGMENT (sym) != absolute_section | |
18535 | || sym_frag == &zero_address_frag); | |
18536 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
18537 | ||
18538 | /* If frag has yet to be reached on this pass, assume it will | |
18539 | move by STRETCH just as we did. If this is not so, it will | |
18540 | be because some frag between grows, and that will force | |
18541 | another pass. */ | |
18542 | ||
18543 | if (stretch != 0 | |
18544 | && sym_frag->relax_marker != fragp->relax_marker) | |
4396b686 PB |
18545 | { |
18546 | fragS *f; | |
18547 | ||
18548 | /* Adjust stretch for any alignment frag. Note that if have | |
18549 | been expanding the earlier code, the symbol may be | |
18550 | defined in what appears to be an earlier frag. FIXME: | |
18551 | This doesn't handle the fr_subtype field, which specifies | |
18552 | a maximum number of bytes to skip when doing an | |
18553 | alignment. */ | |
18554 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
18555 | { | |
18556 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
18557 | { | |
18558 | if (stretch < 0) | |
18559 | stretch = - ((- stretch) | |
18560 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
18561 | else | |
18562 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
18563 | if (stretch == 0) | |
18564 | break; | |
18565 | } | |
18566 | } | |
18567 | if (f != NULL) | |
18568 | addr += stretch; | |
18569 | } | |
5e77afaa PB |
18570 | |
18571 | return addr; | |
18572 | } | |
18573 | ||
0110f2b8 PB |
18574 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative |
18575 | load. */ | |
18576 | static int | |
5e77afaa | 18577 | relax_adr (fragS *fragp, asection *sec, long stretch) |
0110f2b8 PB |
18578 | { |
18579 | addressT addr; | |
18580 | offsetT val; | |
18581 | ||
18582 | /* Assume worst case for symbols not known to be in the same section. */ | |
974da60d NC |
18583 | if (fragp->fr_symbol == NULL |
18584 | || !S_IS_DEFINED (fragp->fr_symbol) | |
77db8e2e NC |
18585 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
18586 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
18587 | return 4; |
18588 | ||
5f4273c7 | 18589 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
18590 | addr = fragp->fr_address + fragp->fr_fix; |
18591 | addr = (addr + 4) & ~3; | |
5e77afaa | 18592 | /* Force misaligned targets to 32-bit variant. */ |
0110f2b8 | 18593 | if (val & 3) |
5e77afaa | 18594 | return 4; |
0110f2b8 PB |
18595 | val -= addr; |
18596 | if (val < 0 || val > 1020) | |
18597 | return 4; | |
18598 | return 2; | |
18599 | } | |
18600 | ||
18601 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
18602 | static int | |
18603 | relax_addsub (fragS *fragp, asection *sec) | |
18604 | { | |
18605 | char *buf; | |
18606 | int op; | |
18607 | ||
18608 | buf = fragp->fr_literal + fragp->fr_fix; | |
18609 | op = bfd_get_16(sec->owner, buf); | |
18610 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
18611 | return relax_immediate (fragp, 8, 0); | |
18612 | else | |
18613 | return relax_immediate (fragp, 3, 0); | |
18614 | } | |
18615 | ||
18616 | ||
18617 | /* Return the size of a relaxable branch instruction. BITS is the | |
18618 | size of the offset field in the narrow instruction. */ | |
18619 | ||
18620 | static int | |
5e77afaa | 18621 | relax_branch (fragS *fragp, asection *sec, int bits, long stretch) |
0110f2b8 PB |
18622 | { |
18623 | addressT addr; | |
18624 | offsetT val; | |
18625 | offsetT limit; | |
18626 | ||
18627 | /* Assume worst case for symbols not known to be in the same section. */ | |
5f4273c7 | 18628 | if (!S_IS_DEFINED (fragp->fr_symbol) |
77db8e2e NC |
18629 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
18630 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
18631 | return 4; |
18632 | ||
267bf995 RR |
18633 | #ifdef OBJ_ELF |
18634 | if (S_IS_DEFINED (fragp->fr_symbol) | |
18635 | && ARM_IS_FUNC (fragp->fr_symbol)) | |
18636 | return 4; | |
18637 | #endif | |
18638 | ||
5f4273c7 | 18639 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
18640 | addr = fragp->fr_address + fragp->fr_fix + 4; |
18641 | val -= addr; | |
18642 | ||
18643 | /* Offset is a signed value *2 */ | |
18644 | limit = 1 << bits; | |
18645 | if (val >= limit || val < -limit) | |
18646 | return 4; | |
18647 | return 2; | |
18648 | } | |
18649 | ||
18650 | ||
18651 | /* Relax a machine dependent frag. This returns the amount by which | |
18652 | the current size of the frag should change. */ | |
18653 | ||
18654 | int | |
5e77afaa | 18655 | arm_relax_frag (asection *sec, fragS *fragp, long stretch) |
0110f2b8 PB |
18656 | { |
18657 | int oldsize; | |
18658 | int newsize; | |
18659 | ||
18660 | oldsize = fragp->fr_var; | |
18661 | switch (fragp->fr_subtype) | |
18662 | { | |
18663 | case T_MNEM_ldr_pc2: | |
5f4273c7 | 18664 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
18665 | break; |
18666 | case T_MNEM_ldr_pc: | |
18667 | case T_MNEM_ldr_sp: | |
18668 | case T_MNEM_str_sp: | |
5f4273c7 | 18669 | newsize = relax_immediate (fragp, 8, 2); |
0110f2b8 PB |
18670 | break; |
18671 | case T_MNEM_ldr: | |
18672 | case T_MNEM_str: | |
5f4273c7 | 18673 | newsize = relax_immediate (fragp, 5, 2); |
0110f2b8 PB |
18674 | break; |
18675 | case T_MNEM_ldrh: | |
18676 | case T_MNEM_strh: | |
5f4273c7 | 18677 | newsize = relax_immediate (fragp, 5, 1); |
0110f2b8 PB |
18678 | break; |
18679 | case T_MNEM_ldrb: | |
18680 | case T_MNEM_strb: | |
5f4273c7 | 18681 | newsize = relax_immediate (fragp, 5, 0); |
0110f2b8 PB |
18682 | break; |
18683 | case T_MNEM_adr: | |
5f4273c7 | 18684 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
18685 | break; |
18686 | case T_MNEM_mov: | |
18687 | case T_MNEM_movs: | |
18688 | case T_MNEM_cmp: | |
18689 | case T_MNEM_cmn: | |
5f4273c7 | 18690 | newsize = relax_immediate (fragp, 8, 0); |
0110f2b8 PB |
18691 | break; |
18692 | case T_MNEM_b: | |
5f4273c7 | 18693 | newsize = relax_branch (fragp, sec, 11, stretch); |
0110f2b8 PB |
18694 | break; |
18695 | case T_MNEM_bcond: | |
5f4273c7 | 18696 | newsize = relax_branch (fragp, sec, 8, stretch); |
0110f2b8 PB |
18697 | break; |
18698 | case T_MNEM_add_sp: | |
18699 | case T_MNEM_add_pc: | |
18700 | newsize = relax_immediate (fragp, 8, 2); | |
18701 | break; | |
18702 | case T_MNEM_inc_sp: | |
18703 | case T_MNEM_dec_sp: | |
18704 | newsize = relax_immediate (fragp, 7, 2); | |
18705 | break; | |
18706 | case T_MNEM_addi: | |
18707 | case T_MNEM_addis: | |
18708 | case T_MNEM_subi: | |
18709 | case T_MNEM_subis: | |
18710 | newsize = relax_addsub (fragp, sec); | |
18711 | break; | |
18712 | default: | |
5f4273c7 | 18713 | abort (); |
0110f2b8 | 18714 | } |
5e77afaa PB |
18715 | |
18716 | fragp->fr_var = newsize; | |
18717 | /* Freeze wide instructions that are at or before the same location as | |
18718 | in the previous pass. This avoids infinite loops. | |
5f4273c7 NC |
18719 | Don't freeze them unconditionally because targets may be artificially |
18720 | misaligned by the expansion of preceding frags. */ | |
5e77afaa | 18721 | if (stretch <= 0 && newsize > 2) |
0110f2b8 | 18722 | { |
0110f2b8 | 18723 | md_convert_frag (sec->owner, sec, fragp); |
5f4273c7 | 18724 | frag_wane (fragp); |
0110f2b8 | 18725 | } |
5e77afaa | 18726 | |
0110f2b8 | 18727 | return newsize - oldsize; |
c19d1205 | 18728 | } |
b99bd4ef | 18729 | |
c19d1205 | 18730 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 18731 | |
c19d1205 ZW |
18732 | valueT |
18733 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
18734 | valueT size) | |
18735 | { | |
f0927246 NC |
18736 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
18737 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
18738 | { | |
18739 | /* For a.out, force the section size to be aligned. If we don't do | |
18740 | this, BFD will align it for us, but it will not write out the | |
18741 | final bytes of the section. This may be a bug in BFD, but it is | |
18742 | easier to fix it here since that is how the other a.out targets | |
18743 | work. */ | |
18744 | int align; | |
18745 | ||
18746 | align = bfd_get_section_alignment (stdoutput, segment); | |
18747 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
18748 | } | |
c19d1205 | 18749 | #endif |
f0927246 NC |
18750 | |
18751 | return size; | |
bfae80f2 | 18752 | } |
b99bd4ef | 18753 | |
c19d1205 ZW |
18754 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
18755 | of an rs_align_code fragment. */ | |
18756 | ||
18757 | void | |
18758 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 18759 | { |
e7495e45 NS |
18760 | static char const arm_noop[2][2][4] = |
18761 | { | |
18762 | { /* ARMv1 */ | |
18763 | {0x00, 0x00, 0xa0, 0xe1}, /* LE */ | |
18764 | {0xe1, 0xa0, 0x00, 0x00}, /* BE */ | |
18765 | }, | |
18766 | { /* ARMv6k */ | |
18767 | {0x00, 0xf0, 0x20, 0xe3}, /* LE */ | |
18768 | {0xe3, 0x20, 0xf0, 0x00}, /* BE */ | |
18769 | }, | |
18770 | }; | |
18771 | static char const thumb_noop[2][2][2] = | |
18772 | { | |
18773 | { /* Thumb-1 */ | |
18774 | {0xc0, 0x46}, /* LE */ | |
18775 | {0x46, 0xc0}, /* BE */ | |
18776 | }, | |
18777 | { /* Thumb-2 */ | |
18778 | {0x00, 0xbf}, /* LE */ | |
18779 | {0xbf, 0x00} /* BE */ | |
18780 | } | |
18781 | }; | |
18782 | static char const wide_thumb_noop[2][4] = | |
18783 | { /* Wide Thumb-2 */ | |
18784 | {0xaf, 0xf3, 0x00, 0x80}, /* LE */ | |
18785 | {0xf3, 0xaf, 0x80, 0x00}, /* BE */ | |
18786 | }; | |
c921be7d | 18787 | |
e7495e45 | 18788 | unsigned bytes, fix, noop_size; |
c19d1205 ZW |
18789 | char * p; |
18790 | const char * noop; | |
e7495e45 | 18791 | const char *narrow_noop = NULL; |
cd000bff DJ |
18792 | #ifdef OBJ_ELF |
18793 | enum mstate state; | |
18794 | #endif | |
bfae80f2 | 18795 | |
c19d1205 | 18796 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
18797 | return; |
18798 | ||
c19d1205 ZW |
18799 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
18800 | p = fragP->fr_literal + fragP->fr_fix; | |
18801 | fix = 0; | |
bfae80f2 | 18802 | |
c19d1205 ZW |
18803 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
18804 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 18805 | |
cd000bff | 18806 | gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); |
8dc2430f | 18807 | |
cd000bff | 18808 | if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) |
a737bd4d | 18809 | { |
e7495e45 NS |
18810 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
18811 | { | |
18812 | narrow_noop = thumb_noop[1][target_big_endian]; | |
18813 | noop = wide_thumb_noop[target_big_endian]; | |
18814 | } | |
c19d1205 | 18815 | else |
e7495e45 NS |
18816 | noop = thumb_noop[0][target_big_endian]; |
18817 | noop_size = 2; | |
cd000bff DJ |
18818 | #ifdef OBJ_ELF |
18819 | state = MAP_THUMB; | |
18820 | #endif | |
7ed4c4c5 NC |
18821 | } |
18822 | else | |
18823 | { | |
e7495e45 NS |
18824 | noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0] |
18825 | [target_big_endian]; | |
18826 | noop_size = 4; | |
cd000bff DJ |
18827 | #ifdef OBJ_ELF |
18828 | state = MAP_ARM; | |
18829 | #endif | |
7ed4c4c5 | 18830 | } |
c921be7d | 18831 | |
e7495e45 | 18832 | fragP->fr_var = noop_size; |
c921be7d | 18833 | |
c19d1205 | 18834 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 18835 | { |
c19d1205 | 18836 | fix = bytes & (noop_size - 1); |
cd000bff DJ |
18837 | #ifdef OBJ_ELF |
18838 | insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); | |
18839 | #endif | |
c19d1205 ZW |
18840 | memset (p, 0, fix); |
18841 | p += fix; | |
18842 | bytes -= fix; | |
a737bd4d | 18843 | } |
a737bd4d | 18844 | |
e7495e45 NS |
18845 | if (narrow_noop) |
18846 | { | |
18847 | if (bytes & noop_size) | |
18848 | { | |
18849 | /* Insert a narrow noop. */ | |
18850 | memcpy (p, narrow_noop, noop_size); | |
18851 | p += noop_size; | |
18852 | bytes -= noop_size; | |
18853 | fix += noop_size; | |
18854 | } | |
18855 | ||
18856 | /* Use wide noops for the remainder */ | |
18857 | noop_size = 4; | |
18858 | } | |
18859 | ||
c19d1205 | 18860 | while (bytes >= noop_size) |
a737bd4d | 18861 | { |
c19d1205 ZW |
18862 | memcpy (p, noop, noop_size); |
18863 | p += noop_size; | |
18864 | bytes -= noop_size; | |
18865 | fix += noop_size; | |
a737bd4d NC |
18866 | } |
18867 | ||
c19d1205 | 18868 | fragP->fr_fix += fix; |
a737bd4d NC |
18869 | } |
18870 | ||
c19d1205 ZW |
18871 | /* Called from md_do_align. Used to create an alignment |
18872 | frag in a code section. */ | |
18873 | ||
18874 | void | |
18875 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 18876 | { |
c19d1205 | 18877 | char * p; |
7ed4c4c5 | 18878 | |
c19d1205 | 18879 | /* We assume that there will never be a requirement |
6ec8e702 | 18880 | to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ |
c19d1205 | 18881 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) |
6ec8e702 NC |
18882 | { |
18883 | char err_msg[128]; | |
18884 | ||
18885 | sprintf (err_msg, | |
18886 | _("alignments greater than %d bytes not supported in .text sections."), | |
18887 | MAX_MEM_FOR_RS_ALIGN_CODE + 1); | |
20203fb9 | 18888 | as_fatal ("%s", err_msg); |
6ec8e702 | 18889 | } |
bfae80f2 | 18890 | |
c19d1205 ZW |
18891 | p = frag_var (rs_align_code, |
18892 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
18893 | 1, | |
18894 | (relax_substateT) max, | |
18895 | (symbolS *) NULL, | |
18896 | (offsetT) n, | |
18897 | (char *) NULL); | |
18898 | *p = 0; | |
18899 | } | |
bfae80f2 | 18900 | |
8dc2430f NC |
18901 | /* Perform target specific initialisation of a frag. |
18902 | Note - despite the name this initialisation is not done when the frag | |
18903 | is created, but only when its type is assigned. A frag can be created | |
18904 | and used a long time before its type is set, so beware of assuming that | |
18905 | this initialisationis performed first. */ | |
bfae80f2 | 18906 | |
cd000bff DJ |
18907 | #ifndef OBJ_ELF |
18908 | void | |
18909 | arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) | |
18910 | { | |
18911 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
2e98972e | 18912 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
cd000bff DJ |
18913 | } |
18914 | ||
18915 | #else /* OBJ_ELF is defined. */ | |
c19d1205 | 18916 | void |
cd000bff | 18917 | arm_init_frag (fragS * fragP, int max_chars) |
c19d1205 | 18918 | { |
8dc2430f NC |
18919 | /* If the current ARM vs THUMB mode has not already |
18920 | been recorded into this frag then do so now. */ | |
cd000bff DJ |
18921 | if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) |
18922 | { | |
18923 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; | |
18924 | ||
18925 | /* Record a mapping symbol for alignment frags. We will delete this | |
18926 | later if the alignment ends up empty. */ | |
18927 | switch (fragP->fr_type) | |
18928 | { | |
18929 | case rs_align: | |
18930 | case rs_align_test: | |
18931 | case rs_fill: | |
18932 | mapping_state_2 (MAP_DATA, max_chars); | |
18933 | break; | |
18934 | case rs_align_code: | |
18935 | mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); | |
18936 | break; | |
18937 | default: | |
18938 | break; | |
18939 | } | |
18940 | } | |
bfae80f2 RE |
18941 | } |
18942 | ||
c19d1205 ZW |
18943 | /* When we change sections we need to issue a new mapping symbol. */ |
18944 | ||
18945 | void | |
18946 | arm_elf_change_section (void) | |
bfae80f2 | 18947 | { |
c19d1205 ZW |
18948 | /* Link an unlinked unwind index table section to the .text section. */ |
18949 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
18950 | && elf_linked_to_section (now_seg) == NULL) | |
18951 | elf_linked_to_section (now_seg) = text_section; | |
bfae80f2 RE |
18952 | } |
18953 | ||
c19d1205 ZW |
18954 | int |
18955 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 18956 | { |
c19d1205 ZW |
18957 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
18958 | return SHT_ARM_EXIDX; | |
e45d0630 | 18959 | |
c19d1205 ZW |
18960 | return -1; |
18961 | } | |
18962 | \f | |
18963 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 18964 | |
c19d1205 | 18965 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 18966 | |
5f4273c7 | 18967 | /* Generate any deferred unwind frame offset. */ |
e45d0630 | 18968 | |
bfae80f2 | 18969 | static void |
c19d1205 | 18970 | flush_pending_unwind (void) |
bfae80f2 | 18971 | { |
c19d1205 | 18972 | offsetT offset; |
bfae80f2 | 18973 | |
c19d1205 ZW |
18974 | offset = unwind.pending_offset; |
18975 | unwind.pending_offset = 0; | |
18976 | if (offset != 0) | |
18977 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
18978 | } |
18979 | ||
c19d1205 ZW |
18980 | /* Add an opcode to this list for this function. Two-byte opcodes should |
18981 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
18982 | order. */ | |
18983 | ||
bfae80f2 | 18984 | static void |
c19d1205 | 18985 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 18986 | { |
c19d1205 ZW |
18987 | /* Add any deferred stack adjustment. */ |
18988 | if (unwind.pending_offset) | |
18989 | flush_pending_unwind (); | |
bfae80f2 | 18990 | |
c19d1205 | 18991 | unwind.sp_restored = 0; |
bfae80f2 | 18992 | |
c19d1205 | 18993 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 18994 | { |
c19d1205 ZW |
18995 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
18996 | if (unwind.opcodes) | |
21d799b5 NC |
18997 | unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes, |
18998 | unwind.opcode_alloc); | |
c19d1205 | 18999 | else |
21d799b5 | 19000 | unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc); |
bfae80f2 | 19001 | } |
c19d1205 | 19002 | while (length > 0) |
bfae80f2 | 19003 | { |
c19d1205 ZW |
19004 | length--; |
19005 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
19006 | op >>= 8; | |
19007 | unwind.opcode_count++; | |
bfae80f2 | 19008 | } |
bfae80f2 RE |
19009 | } |
19010 | ||
c19d1205 ZW |
19011 | /* Add unwind opcodes to adjust the stack pointer. */ |
19012 | ||
bfae80f2 | 19013 | static void |
c19d1205 | 19014 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 19015 | { |
c19d1205 | 19016 | valueT op; |
bfae80f2 | 19017 | |
c19d1205 | 19018 | if (offset > 0x200) |
bfae80f2 | 19019 | { |
c19d1205 ZW |
19020 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
19021 | char bytes[5]; | |
19022 | int n; | |
19023 | valueT o; | |
bfae80f2 | 19024 | |
c19d1205 ZW |
19025 | /* Long form: 0xb2, uleb128. */ |
19026 | /* This might not fit in a word so add the individual bytes, | |
19027 | remembering the list is built in reverse order. */ | |
19028 | o = (valueT) ((offset - 0x204) >> 2); | |
19029 | if (o == 0) | |
19030 | add_unwind_opcode (0, 1); | |
bfae80f2 | 19031 | |
c19d1205 ZW |
19032 | /* Calculate the uleb128 encoding of the offset. */ |
19033 | n = 0; | |
19034 | while (o) | |
19035 | { | |
19036 | bytes[n] = o & 0x7f; | |
19037 | o >>= 7; | |
19038 | if (o) | |
19039 | bytes[n] |= 0x80; | |
19040 | n++; | |
19041 | } | |
19042 | /* Add the insn. */ | |
19043 | for (; n; n--) | |
19044 | add_unwind_opcode (bytes[n - 1], 1); | |
19045 | add_unwind_opcode (0xb2, 1); | |
19046 | } | |
19047 | else if (offset > 0x100) | |
bfae80f2 | 19048 | { |
c19d1205 ZW |
19049 | /* Two short opcodes. */ |
19050 | add_unwind_opcode (0x3f, 1); | |
19051 | op = (offset - 0x104) >> 2; | |
19052 | add_unwind_opcode (op, 1); | |
bfae80f2 | 19053 | } |
c19d1205 ZW |
19054 | else if (offset > 0) |
19055 | { | |
19056 | /* Short opcode. */ | |
19057 | op = (offset - 4) >> 2; | |
19058 | add_unwind_opcode (op, 1); | |
19059 | } | |
19060 | else if (offset < 0) | |
bfae80f2 | 19061 | { |
c19d1205 ZW |
19062 | offset = -offset; |
19063 | while (offset > 0x100) | |
bfae80f2 | 19064 | { |
c19d1205 ZW |
19065 | add_unwind_opcode (0x7f, 1); |
19066 | offset -= 0x100; | |
bfae80f2 | 19067 | } |
c19d1205 ZW |
19068 | op = ((offset - 4) >> 2) | 0x40; |
19069 | add_unwind_opcode (op, 1); | |
bfae80f2 | 19070 | } |
bfae80f2 RE |
19071 | } |
19072 | ||
c19d1205 ZW |
19073 | /* Finish the list of unwind opcodes for this function. */ |
19074 | static void | |
19075 | finish_unwind_opcodes (void) | |
bfae80f2 | 19076 | { |
c19d1205 | 19077 | valueT op; |
bfae80f2 | 19078 | |
c19d1205 | 19079 | if (unwind.fp_used) |
bfae80f2 | 19080 | { |
708587a4 | 19081 | /* Adjust sp as necessary. */ |
c19d1205 ZW |
19082 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
19083 | flush_pending_unwind (); | |
bfae80f2 | 19084 | |
c19d1205 ZW |
19085 | /* After restoring sp from the frame pointer. */ |
19086 | op = 0x90 | unwind.fp_reg; | |
19087 | add_unwind_opcode (op, 1); | |
19088 | } | |
19089 | else | |
19090 | flush_pending_unwind (); | |
bfae80f2 RE |
19091 | } |
19092 | ||
bfae80f2 | 19093 | |
c19d1205 ZW |
19094 | /* Start an exception table entry. If idx is nonzero this is an index table |
19095 | entry. */ | |
bfae80f2 RE |
19096 | |
19097 | static void | |
c19d1205 | 19098 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 19099 | { |
c19d1205 ZW |
19100 | const char * text_name; |
19101 | const char * prefix; | |
19102 | const char * prefix_once; | |
19103 | const char * group_name; | |
19104 | size_t prefix_len; | |
19105 | size_t text_len; | |
19106 | char * sec_name; | |
19107 | size_t sec_name_len; | |
19108 | int type; | |
19109 | int flags; | |
19110 | int linkonce; | |
bfae80f2 | 19111 | |
c19d1205 | 19112 | if (idx) |
bfae80f2 | 19113 | { |
c19d1205 ZW |
19114 | prefix = ELF_STRING_ARM_unwind; |
19115 | prefix_once = ELF_STRING_ARM_unwind_once; | |
19116 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 19117 | } |
c19d1205 | 19118 | else |
bfae80f2 | 19119 | { |
c19d1205 ZW |
19120 | prefix = ELF_STRING_ARM_unwind_info; |
19121 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
19122 | type = SHT_PROGBITS; | |
bfae80f2 RE |
19123 | } |
19124 | ||
c19d1205 ZW |
19125 | text_name = segment_name (text_seg); |
19126 | if (streq (text_name, ".text")) | |
19127 | text_name = ""; | |
19128 | ||
19129 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
19130 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 19131 | { |
c19d1205 ZW |
19132 | prefix = prefix_once; |
19133 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
19134 | } |
19135 | ||
c19d1205 ZW |
19136 | prefix_len = strlen (prefix); |
19137 | text_len = strlen (text_name); | |
19138 | sec_name_len = prefix_len + text_len; | |
21d799b5 | 19139 | sec_name = (char *) xmalloc (sec_name_len + 1); |
c19d1205 ZW |
19140 | memcpy (sec_name, prefix, prefix_len); |
19141 | memcpy (sec_name + prefix_len, text_name, text_len); | |
19142 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 19143 | |
c19d1205 ZW |
19144 | flags = SHF_ALLOC; |
19145 | linkonce = 0; | |
19146 | group_name = 0; | |
bfae80f2 | 19147 | |
c19d1205 ZW |
19148 | /* Handle COMDAT group. */ |
19149 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 19150 | { |
c19d1205 ZW |
19151 | group_name = elf_group_name (text_seg); |
19152 | if (group_name == NULL) | |
19153 | { | |
bd3ba5d1 | 19154 | as_bad (_("Group section `%s' has no group signature"), |
c19d1205 ZW |
19155 | segment_name (text_seg)); |
19156 | ignore_rest_of_line (); | |
19157 | return; | |
19158 | } | |
19159 | flags |= SHF_GROUP; | |
19160 | linkonce = 1; | |
bfae80f2 RE |
19161 | } |
19162 | ||
c19d1205 | 19163 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 19164 | |
5f4273c7 | 19165 | /* Set the section link for index tables. */ |
c19d1205 ZW |
19166 | if (idx) |
19167 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
19168 | } |
19169 | ||
bfae80f2 | 19170 | |
c19d1205 ZW |
19171 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
19172 | personality routine data. Returns zero, or the index table value for | |
19173 | and inline entry. */ | |
19174 | ||
19175 | static valueT | |
19176 | create_unwind_entry (int have_data) | |
bfae80f2 | 19177 | { |
c19d1205 ZW |
19178 | int size; |
19179 | addressT where; | |
19180 | char *ptr; | |
19181 | /* The current word of data. */ | |
19182 | valueT data; | |
19183 | /* The number of bytes left in this word. */ | |
19184 | int n; | |
bfae80f2 | 19185 | |
c19d1205 | 19186 | finish_unwind_opcodes (); |
bfae80f2 | 19187 | |
c19d1205 ZW |
19188 | /* Remember the current text section. */ |
19189 | unwind.saved_seg = now_seg; | |
19190 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 19191 | |
c19d1205 | 19192 | start_unwind_section (now_seg, 0); |
bfae80f2 | 19193 | |
c19d1205 | 19194 | if (unwind.personality_routine == NULL) |
bfae80f2 | 19195 | { |
c19d1205 ZW |
19196 | if (unwind.personality_index == -2) |
19197 | { | |
19198 | if (have_data) | |
5f4273c7 | 19199 | as_bad (_("handlerdata in cantunwind frame")); |
c19d1205 ZW |
19200 | return 1; /* EXIDX_CANTUNWIND. */ |
19201 | } | |
bfae80f2 | 19202 | |
c19d1205 ZW |
19203 | /* Use a default personality routine if none is specified. */ |
19204 | if (unwind.personality_index == -1) | |
19205 | { | |
19206 | if (unwind.opcode_count > 3) | |
19207 | unwind.personality_index = 1; | |
19208 | else | |
19209 | unwind.personality_index = 0; | |
19210 | } | |
bfae80f2 | 19211 | |
c19d1205 ZW |
19212 | /* Space for the personality routine entry. */ |
19213 | if (unwind.personality_index == 0) | |
19214 | { | |
19215 | if (unwind.opcode_count > 3) | |
19216 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 19217 | |
c19d1205 ZW |
19218 | if (!have_data) |
19219 | { | |
19220 | /* All the data is inline in the index table. */ | |
19221 | data = 0x80; | |
19222 | n = 3; | |
19223 | while (unwind.opcode_count > 0) | |
19224 | { | |
19225 | unwind.opcode_count--; | |
19226 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
19227 | n--; | |
19228 | } | |
bfae80f2 | 19229 | |
c19d1205 ZW |
19230 | /* Pad with "finish" opcodes. */ |
19231 | while (n--) | |
19232 | data = (data << 8) | 0xb0; | |
bfae80f2 | 19233 | |
c19d1205 ZW |
19234 | return data; |
19235 | } | |
19236 | size = 0; | |
19237 | } | |
19238 | else | |
19239 | /* We get two opcodes "free" in the first word. */ | |
19240 | size = unwind.opcode_count - 2; | |
19241 | } | |
19242 | else | |
19243 | /* An extra byte is required for the opcode count. */ | |
19244 | size = unwind.opcode_count + 1; | |
bfae80f2 | 19245 | |
c19d1205 ZW |
19246 | size = (size + 3) >> 2; |
19247 | if (size > 0xff) | |
19248 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 19249 | |
c19d1205 ZW |
19250 | frag_align (2, 0, 0); |
19251 | record_alignment (now_seg, 2); | |
19252 | unwind.table_entry = expr_build_dot (); | |
19253 | ||
19254 | /* Allocate the table entry. */ | |
19255 | ptr = frag_more ((size << 2) + 4); | |
19256 | where = frag_now_fix () - ((size << 2) + 4); | |
bfae80f2 | 19257 | |
c19d1205 | 19258 | switch (unwind.personality_index) |
bfae80f2 | 19259 | { |
c19d1205 ZW |
19260 | case -1: |
19261 | /* ??? Should this be a PLT generating relocation? */ | |
19262 | /* Custom personality routine. */ | |
19263 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
19264 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 19265 | |
c19d1205 ZW |
19266 | where += 4; |
19267 | ptr += 4; | |
bfae80f2 | 19268 | |
c19d1205 ZW |
19269 | /* Set the first byte to the number of additional words. */ |
19270 | data = size - 1; | |
19271 | n = 3; | |
19272 | break; | |
bfae80f2 | 19273 | |
c19d1205 ZW |
19274 | /* ABI defined personality routines. */ |
19275 | case 0: | |
19276 | /* Three opcodes bytes are packed into the first word. */ | |
19277 | data = 0x80; | |
19278 | n = 3; | |
19279 | break; | |
bfae80f2 | 19280 | |
c19d1205 ZW |
19281 | case 1: |
19282 | case 2: | |
19283 | /* The size and first two opcode bytes go in the first word. */ | |
19284 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
19285 | n = 2; | |
19286 | break; | |
bfae80f2 | 19287 | |
c19d1205 ZW |
19288 | default: |
19289 | /* Should never happen. */ | |
19290 | abort (); | |
19291 | } | |
bfae80f2 | 19292 | |
c19d1205 ZW |
19293 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
19294 | time. */ | |
19295 | while (unwind.opcode_count > 0) | |
19296 | { | |
19297 | if (n == 0) | |
19298 | { | |
19299 | md_number_to_chars (ptr, data, 4); | |
19300 | ptr += 4; | |
19301 | n = 4; | |
19302 | data = 0; | |
19303 | } | |
19304 | unwind.opcode_count--; | |
19305 | n--; | |
19306 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
19307 | } | |
19308 | ||
19309 | /* Finish off the last word. */ | |
19310 | if (n < 4) | |
19311 | { | |
19312 | /* Pad with "finish" opcodes. */ | |
19313 | while (n--) | |
19314 | data = (data << 8) | 0xb0; | |
19315 | ||
19316 | md_number_to_chars (ptr, data, 4); | |
19317 | } | |
19318 | ||
19319 | if (!have_data) | |
19320 | { | |
19321 | /* Add an empty descriptor if there is no user-specified data. */ | |
19322 | ptr = frag_more (4); | |
19323 | md_number_to_chars (ptr, 0, 4); | |
19324 | } | |
19325 | ||
19326 | return 0; | |
bfae80f2 RE |
19327 | } |
19328 | ||
f0927246 NC |
19329 | |
19330 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
19331 | ||
19332 | void | |
19333 | tc_arm_frame_initial_instructions (void) | |
19334 | { | |
19335 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
19336 | } | |
19337 | #endif /* OBJ_ELF */ | |
19338 | ||
c19d1205 ZW |
19339 | /* Convert REGNAME to a DWARF-2 register number. */ |
19340 | ||
19341 | int | |
1df69f4f | 19342 | tc_arm_regname_to_dw2regnum (char *regname) |
bfae80f2 | 19343 | { |
1df69f4f | 19344 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
c19d1205 ZW |
19345 | |
19346 | if (reg == FAIL) | |
19347 | return -1; | |
19348 | ||
19349 | return reg; | |
bfae80f2 RE |
19350 | } |
19351 | ||
f0927246 | 19352 | #ifdef TE_PE |
c19d1205 | 19353 | void |
f0927246 | 19354 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
bfae80f2 | 19355 | { |
91d6fa6a | 19356 | expressionS exp; |
bfae80f2 | 19357 | |
91d6fa6a NC |
19358 | exp.X_op = O_secrel; |
19359 | exp.X_add_symbol = symbol; | |
19360 | exp.X_add_number = 0; | |
19361 | emit_expr (&exp, size); | |
f0927246 NC |
19362 | } |
19363 | #endif | |
bfae80f2 | 19364 | |
c19d1205 | 19365 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 19366 | |
2fc8bdac ZW |
19367 | /* Return the address within the segment that a PC-relative fixup is |
19368 | relative to. For ARM, PC-relative fixups applied to instructions | |
19369 | are generally relative to the location of the fixup plus 8 bytes. | |
19370 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
19371 | require special handling. */ | |
bfae80f2 | 19372 | |
c19d1205 | 19373 | long |
2fc8bdac | 19374 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 19375 | { |
2fc8bdac ZW |
19376 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
19377 | ||
19378 | /* If this is pc-relative and we are going to emit a relocation | |
19379 | then we just want to put out any pipeline compensation that the linker | |
53baae48 NC |
19380 | will need. Otherwise we want to use the calculated base. |
19381 | For WinCE we skip the bias for externals as well, since this | |
19382 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ | |
5f4273c7 | 19383 | if (fixP->fx_pcrel |
2fc8bdac | 19384 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) |
53baae48 NC |
19385 | || (arm_force_relocation (fixP) |
19386 | #ifdef TE_WINCE | |
19387 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
19388 | #endif | |
19389 | ))) | |
2fc8bdac | 19390 | base = 0; |
bfae80f2 | 19391 | |
267bf995 | 19392 | |
c19d1205 | 19393 | switch (fixP->fx_r_type) |
bfae80f2 | 19394 | { |
2fc8bdac ZW |
19395 | /* PC relative addressing on the Thumb is slightly odd as the |
19396 | bottom two bits of the PC are forced to zero for the | |
19397 | calculation. This happens *after* application of the | |
19398 | pipeline offset. However, Thumb adrl already adjusts for | |
19399 | this, so we need not do it again. */ | |
c19d1205 | 19400 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 19401 | return base & ~3; |
c19d1205 ZW |
19402 | |
19403 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
19404 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 19405 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 19406 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 19407 | return (base + 4) & ~3; |
c19d1205 | 19408 | |
2fc8bdac ZW |
19409 | /* Thumb branches are simply offset by +4. */ |
19410 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
19411 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
19412 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
19413 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
2fc8bdac | 19414 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac | 19415 | return base + 4; |
bfae80f2 | 19416 | |
267bf995 | 19417 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
486499d0 CL |
19418 | if (fixP->fx_addsy |
19419 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19420 | && (!S_IS_EXTERNAL (fixP->fx_addsy)) | |
267bf995 RR |
19421 | && ARM_IS_FUNC (fixP->fx_addsy) |
19422 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19423 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
19424 | return base + 4; | |
19425 | ||
00adf2d4 JB |
19426 | /* BLX is like branches above, but forces the low two bits of PC to |
19427 | zero. */ | |
486499d0 CL |
19428 | case BFD_RELOC_THUMB_PCREL_BLX: |
19429 | if (fixP->fx_addsy | |
19430 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19431 | && (!S_IS_EXTERNAL (fixP->fx_addsy)) | |
267bf995 RR |
19432 | && THUMB_IS_FUNC (fixP->fx_addsy) |
19433 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19434 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
00adf2d4 JB |
19435 | return (base + 4) & ~3; |
19436 | ||
2fc8bdac ZW |
19437 | /* ARM mode branches are offset by +8. However, the Windows CE |
19438 | loader expects the relocation not to take this into account. */ | |
267bf995 | 19439 | case BFD_RELOC_ARM_PCREL_BLX: |
486499d0 CL |
19440 | if (fixP->fx_addsy |
19441 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19442 | && (!S_IS_EXTERNAL (fixP->fx_addsy)) | |
267bf995 RR |
19443 | && ARM_IS_FUNC (fixP->fx_addsy) |
19444 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19445 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 19446 | return base + 8; |
267bf995 | 19447 | |
486499d0 CL |
19448 | case BFD_RELOC_ARM_PCREL_CALL: |
19449 | if (fixP->fx_addsy | |
19450 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19451 | && (!S_IS_EXTERNAL (fixP->fx_addsy)) | |
267bf995 RR |
19452 | && THUMB_IS_FUNC (fixP->fx_addsy) |
19453 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19454 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 19455 | return base + 8; |
267bf995 | 19456 | |
2fc8bdac | 19457 | case BFD_RELOC_ARM_PCREL_BRANCH: |
39b41c9c | 19458 | case BFD_RELOC_ARM_PCREL_JUMP: |
2fc8bdac | 19459 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 19460 | #ifdef TE_WINCE |
5f4273c7 | 19461 | /* When handling fixups immediately, because we have already |
53baae48 NC |
19462 | discovered the value of a symbol, or the address of the frag involved |
19463 | we must account for the offset by +8, as the OS loader will never see the reloc. | |
19464 | see fixup_segment() in write.c | |
19465 | The S_IS_EXTERNAL test handles the case of global symbols. | |
19466 | Those need the calculated base, not just the pipe compensation the linker will need. */ | |
19467 | if (fixP->fx_pcrel | |
19468 | && fixP->fx_addsy != NULL | |
19469 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19470 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) | |
19471 | return base + 8; | |
2fc8bdac | 19472 | return base; |
c19d1205 | 19473 | #else |
2fc8bdac | 19474 | return base + 8; |
c19d1205 | 19475 | #endif |
2fc8bdac | 19476 | |
267bf995 | 19477 | |
2fc8bdac ZW |
19478 | /* ARM mode loads relative to PC are also offset by +8. Unlike |
19479 | branches, the Windows CE loader *does* expect the relocation | |
19480 | to take this into account. */ | |
19481 | case BFD_RELOC_ARM_OFFSET_IMM: | |
19482 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
19483 | case BFD_RELOC_ARM_HWLITERAL: | |
19484 | case BFD_RELOC_ARM_LITERAL: | |
19485 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
19486 | return base + 8; | |
19487 | ||
19488 | ||
19489 | /* Other PC-relative relocations are un-offset. */ | |
19490 | default: | |
19491 | return base; | |
19492 | } | |
bfae80f2 RE |
19493 | } |
19494 | ||
c19d1205 ZW |
19495 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. |
19496 | Otherwise we have no need to default values of symbols. */ | |
19497 | ||
19498 | symbolS * | |
19499 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
bfae80f2 | 19500 | { |
c19d1205 ZW |
19501 | #ifdef OBJ_ELF |
19502 | if (name[0] == '_' && name[1] == 'G' | |
19503 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
19504 | { | |
19505 | if (!GOT_symbol) | |
19506 | { | |
19507 | if (symbol_find (name)) | |
bd3ba5d1 | 19508 | as_bad (_("GOT already in the symbol table")); |
bfae80f2 | 19509 | |
c19d1205 ZW |
19510 | GOT_symbol = symbol_new (name, undefined_section, |
19511 | (valueT) 0, & zero_address_frag); | |
19512 | } | |
bfae80f2 | 19513 | |
c19d1205 | 19514 | return GOT_symbol; |
bfae80f2 | 19515 | } |
c19d1205 | 19516 | #endif |
bfae80f2 | 19517 | |
c921be7d | 19518 | return NULL; |
bfae80f2 RE |
19519 | } |
19520 | ||
55cf6793 | 19521 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
19522 | computed as two separate immediate values, added together. We |
19523 | already know that this value cannot be computed by just one ARM | |
19524 | instruction. */ | |
19525 | ||
19526 | static unsigned int | |
19527 | validate_immediate_twopart (unsigned int val, | |
19528 | unsigned int * highpart) | |
bfae80f2 | 19529 | { |
c19d1205 ZW |
19530 | unsigned int a; |
19531 | unsigned int i; | |
bfae80f2 | 19532 | |
c19d1205 ZW |
19533 | for (i = 0; i < 32; i += 2) |
19534 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
19535 | { | |
19536 | if (a & 0xff00) | |
19537 | { | |
19538 | if (a & ~ 0xffff) | |
19539 | continue; | |
19540 | * highpart = (a >> 8) | ((i + 24) << 7); | |
19541 | } | |
19542 | else if (a & 0xff0000) | |
19543 | { | |
19544 | if (a & 0xff000000) | |
19545 | continue; | |
19546 | * highpart = (a >> 16) | ((i + 16) << 7); | |
19547 | } | |
19548 | else | |
19549 | { | |
9c2799c2 | 19550 | gas_assert (a & 0xff000000); |
c19d1205 ZW |
19551 | * highpart = (a >> 24) | ((i + 8) << 7); |
19552 | } | |
bfae80f2 | 19553 | |
c19d1205 ZW |
19554 | return (a & 0xff) | (i << 7); |
19555 | } | |
bfae80f2 | 19556 | |
c19d1205 | 19557 | return FAIL; |
bfae80f2 RE |
19558 | } |
19559 | ||
c19d1205 ZW |
19560 | static int |
19561 | validate_offset_imm (unsigned int val, int hwse) | |
19562 | { | |
19563 | if ((hwse && val > 255) || val > 4095) | |
19564 | return FAIL; | |
19565 | return val; | |
19566 | } | |
bfae80f2 | 19567 | |
55cf6793 | 19568 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
19569 | negative immediate constant by altering the instruction. A bit of |
19570 | a hack really. | |
19571 | MOV <-> MVN | |
19572 | AND <-> BIC | |
19573 | ADC <-> SBC | |
19574 | by inverting the second operand, and | |
19575 | ADD <-> SUB | |
19576 | CMP <-> CMN | |
19577 | by negating the second operand. */ | |
bfae80f2 | 19578 | |
c19d1205 ZW |
19579 | static int |
19580 | negate_data_op (unsigned long * instruction, | |
19581 | unsigned long value) | |
bfae80f2 | 19582 | { |
c19d1205 ZW |
19583 | int op, new_inst; |
19584 | unsigned long negated, inverted; | |
bfae80f2 | 19585 | |
c19d1205 ZW |
19586 | negated = encode_arm_immediate (-value); |
19587 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 19588 | |
c19d1205 ZW |
19589 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
19590 | switch (op) | |
bfae80f2 | 19591 | { |
c19d1205 ZW |
19592 | /* First negates. */ |
19593 | case OPCODE_SUB: /* ADD <-> SUB */ | |
19594 | new_inst = OPCODE_ADD; | |
19595 | value = negated; | |
19596 | break; | |
bfae80f2 | 19597 | |
c19d1205 ZW |
19598 | case OPCODE_ADD: |
19599 | new_inst = OPCODE_SUB; | |
19600 | value = negated; | |
19601 | break; | |
bfae80f2 | 19602 | |
c19d1205 ZW |
19603 | case OPCODE_CMP: /* CMP <-> CMN */ |
19604 | new_inst = OPCODE_CMN; | |
19605 | value = negated; | |
19606 | break; | |
bfae80f2 | 19607 | |
c19d1205 ZW |
19608 | case OPCODE_CMN: |
19609 | new_inst = OPCODE_CMP; | |
19610 | value = negated; | |
19611 | break; | |
bfae80f2 | 19612 | |
c19d1205 ZW |
19613 | /* Now Inverted ops. */ |
19614 | case OPCODE_MOV: /* MOV <-> MVN */ | |
19615 | new_inst = OPCODE_MVN; | |
19616 | value = inverted; | |
19617 | break; | |
bfae80f2 | 19618 | |
c19d1205 ZW |
19619 | case OPCODE_MVN: |
19620 | new_inst = OPCODE_MOV; | |
19621 | value = inverted; | |
19622 | break; | |
bfae80f2 | 19623 | |
c19d1205 ZW |
19624 | case OPCODE_AND: /* AND <-> BIC */ |
19625 | new_inst = OPCODE_BIC; | |
19626 | value = inverted; | |
19627 | break; | |
bfae80f2 | 19628 | |
c19d1205 ZW |
19629 | case OPCODE_BIC: |
19630 | new_inst = OPCODE_AND; | |
19631 | value = inverted; | |
19632 | break; | |
bfae80f2 | 19633 | |
c19d1205 ZW |
19634 | case OPCODE_ADC: /* ADC <-> SBC */ |
19635 | new_inst = OPCODE_SBC; | |
19636 | value = inverted; | |
19637 | break; | |
bfae80f2 | 19638 | |
c19d1205 ZW |
19639 | case OPCODE_SBC: |
19640 | new_inst = OPCODE_ADC; | |
19641 | value = inverted; | |
19642 | break; | |
bfae80f2 | 19643 | |
c19d1205 ZW |
19644 | /* We cannot do anything. */ |
19645 | default: | |
19646 | return FAIL; | |
b99bd4ef NC |
19647 | } |
19648 | ||
c19d1205 ZW |
19649 | if (value == (unsigned) FAIL) |
19650 | return FAIL; | |
19651 | ||
19652 | *instruction &= OPCODE_MASK; | |
19653 | *instruction |= new_inst << DATA_OP_SHIFT; | |
19654 | return value; | |
b99bd4ef NC |
19655 | } |
19656 | ||
ef8d22e6 PB |
19657 | /* Like negate_data_op, but for Thumb-2. */ |
19658 | ||
19659 | static unsigned int | |
16dd5e42 | 19660 | thumb32_negate_data_op (offsetT *instruction, unsigned int value) |
ef8d22e6 PB |
19661 | { |
19662 | int op, new_inst; | |
19663 | int rd; | |
16dd5e42 | 19664 | unsigned int negated, inverted; |
ef8d22e6 PB |
19665 | |
19666 | negated = encode_thumb32_immediate (-value); | |
19667 | inverted = encode_thumb32_immediate (~value); | |
19668 | ||
19669 | rd = (*instruction >> 8) & 0xf; | |
19670 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
19671 | switch (op) | |
19672 | { | |
19673 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
19674 | case T2_OPCODE_SUB: | |
19675 | new_inst = T2_OPCODE_ADD; | |
19676 | value = negated; | |
19677 | break; | |
19678 | ||
19679 | case T2_OPCODE_ADD: | |
19680 | new_inst = T2_OPCODE_SUB; | |
19681 | value = negated; | |
19682 | break; | |
19683 | ||
19684 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
19685 | case T2_OPCODE_ORR: | |
19686 | new_inst = T2_OPCODE_ORN; | |
19687 | value = inverted; | |
19688 | break; | |
19689 | ||
19690 | case T2_OPCODE_ORN: | |
19691 | new_inst = T2_OPCODE_ORR; | |
19692 | value = inverted; | |
19693 | break; | |
19694 | ||
19695 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
19696 | case T2_OPCODE_AND: | |
19697 | new_inst = T2_OPCODE_BIC; | |
19698 | if (rd == 15) | |
19699 | value = FAIL; | |
19700 | else | |
19701 | value = inverted; | |
19702 | break; | |
19703 | ||
19704 | case T2_OPCODE_BIC: | |
19705 | new_inst = T2_OPCODE_AND; | |
19706 | value = inverted; | |
19707 | break; | |
19708 | ||
19709 | /* ADC <-> SBC */ | |
19710 | case T2_OPCODE_ADC: | |
19711 | new_inst = T2_OPCODE_SBC; | |
19712 | value = inverted; | |
19713 | break; | |
19714 | ||
19715 | case T2_OPCODE_SBC: | |
19716 | new_inst = T2_OPCODE_ADC; | |
19717 | value = inverted; | |
19718 | break; | |
19719 | ||
19720 | /* We cannot do anything. */ | |
19721 | default: | |
19722 | return FAIL; | |
19723 | } | |
19724 | ||
16dd5e42 | 19725 | if (value == (unsigned int)FAIL) |
ef8d22e6 PB |
19726 | return FAIL; |
19727 | ||
19728 | *instruction &= T2_OPCODE_MASK; | |
19729 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
19730 | return value; | |
19731 | } | |
19732 | ||
8f06b2d8 PB |
19733 | /* Read a 32-bit thumb instruction from buf. */ |
19734 | static unsigned long | |
19735 | get_thumb32_insn (char * buf) | |
19736 | { | |
19737 | unsigned long insn; | |
19738 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
19739 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
19740 | ||
19741 | return insn; | |
19742 | } | |
19743 | ||
a8bc6c78 PB |
19744 | |
19745 | /* We usually want to set the low bit on the address of thumb function | |
19746 | symbols. In particular .word foo - . should have the low bit set. | |
19747 | Generic code tries to fold the difference of two symbols to | |
19748 | a constant. Prevent this and force a relocation when the first symbols | |
19749 | is a thumb function. */ | |
c921be7d NC |
19750 | |
19751 | bfd_boolean | |
a8bc6c78 PB |
19752 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) |
19753 | { | |
19754 | if (op == O_subtract | |
19755 | && l->X_op == O_symbol | |
19756 | && r->X_op == O_symbol | |
19757 | && THUMB_IS_FUNC (l->X_add_symbol)) | |
19758 | { | |
19759 | l->X_op = O_subtract; | |
19760 | l->X_op_symbol = r->X_add_symbol; | |
19761 | l->X_add_number -= r->X_add_number; | |
c921be7d | 19762 | return TRUE; |
a8bc6c78 | 19763 | } |
c921be7d | 19764 | |
a8bc6c78 | 19765 | /* Process as normal. */ |
c921be7d | 19766 | return FALSE; |
a8bc6c78 PB |
19767 | } |
19768 | ||
4a42ebbc RR |
19769 | /* Encode Thumb2 unconditional branches and calls. The encoding |
19770 | for the 2 are identical for the immediate values. */ | |
19771 | ||
19772 | static void | |
19773 | encode_thumb2_b_bl_offset (char * buf, offsetT value) | |
19774 | { | |
19775 | #define T2I1I2MASK ((1 << 13) | (1 << 11)) | |
19776 | offsetT newval; | |
19777 | offsetT newval2; | |
19778 | addressT S, I1, I2, lo, hi; | |
19779 | ||
19780 | S = (value >> 24) & 0x01; | |
19781 | I1 = (value >> 23) & 0x01; | |
19782 | I2 = (value >> 22) & 0x01; | |
19783 | hi = (value >> 12) & 0x3ff; | |
19784 | lo = (value >> 1) & 0x7ff; | |
19785 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
19786 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
19787 | newval |= (S << 10) | hi; | |
19788 | newval2 &= ~T2I1I2MASK; | |
19789 | newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK; | |
19790 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
19791 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
19792 | } | |
19793 | ||
c19d1205 | 19794 | void |
55cf6793 | 19795 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
19796 | valueT * valP, |
19797 | segT seg) | |
19798 | { | |
19799 | offsetT value = * valP; | |
19800 | offsetT newval; | |
19801 | unsigned int newimm; | |
19802 | unsigned long temp; | |
19803 | int sign; | |
19804 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 19805 | |
9c2799c2 | 19806 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 19807 | |
c19d1205 | 19808 | /* Note whether this will delete the relocation. */ |
4962c51a | 19809 | |
c19d1205 ZW |
19810 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
19811 | fixP->fx_done = 1; | |
b99bd4ef | 19812 | |
adbaf948 | 19813 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
5f4273c7 | 19814 | consistency with the behaviour on 32-bit hosts. Remember value |
adbaf948 ZW |
19815 | for emit_reloc. */ |
19816 | value &= 0xffffffff; | |
19817 | value ^= 0x80000000; | |
5f4273c7 | 19818 | value -= 0x80000000; |
adbaf948 ZW |
19819 | |
19820 | *valP = value; | |
c19d1205 | 19821 | fixP->fx_addnumber = value; |
b99bd4ef | 19822 | |
adbaf948 ZW |
19823 | /* Same treatment for fixP->fx_offset. */ |
19824 | fixP->fx_offset &= 0xffffffff; | |
19825 | fixP->fx_offset ^= 0x80000000; | |
19826 | fixP->fx_offset -= 0x80000000; | |
19827 | ||
c19d1205 | 19828 | switch (fixP->fx_r_type) |
b99bd4ef | 19829 | { |
c19d1205 ZW |
19830 | case BFD_RELOC_NONE: |
19831 | /* This will need to go in the object file. */ | |
19832 | fixP->fx_done = 0; | |
19833 | break; | |
b99bd4ef | 19834 | |
c19d1205 ZW |
19835 | case BFD_RELOC_ARM_IMMEDIATE: |
19836 | /* We claim that this fixup has been processed here, | |
19837 | even if in fact we generate an error because we do | |
19838 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
19839 | fixP->fx_done = 1; | |
b99bd4ef | 19840 | |
77db8e2e | 19841 | if (fixP->fx_addsy) |
b99bd4ef | 19842 | { |
77db8e2e | 19843 | const char *msg = 0; |
b99bd4ef | 19844 | |
77db8e2e NC |
19845 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
19846 | msg = _("undefined symbol %s used as an immediate value"); | |
19847 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
19848 | msg = _("symbol %s is in a different section"); | |
19849 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
19850 | msg = _("symbol %s is weak and may be overridden later"); | |
19851 | ||
19852 | if (msg) | |
19853 | { | |
19854 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19855 | msg, S_GET_NAME (fixP->fx_addsy)); | |
19856 | break; | |
19857 | } | |
42e5fcbf AS |
19858 | } |
19859 | ||
c19d1205 ZW |
19860 | newimm = encode_arm_immediate (value); |
19861 | temp = md_chars_to_number (buf, INSN_SIZE); | |
19862 | ||
19863 | /* If the instruction will fail, see if we can fix things up by | |
19864 | changing the opcode. */ | |
19865 | if (newimm == (unsigned int) FAIL | |
19866 | && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) | |
b99bd4ef | 19867 | { |
c19d1205 ZW |
19868 | as_bad_where (fixP->fx_file, fixP->fx_line, |
19869 | _("invalid constant (%lx) after fixup"), | |
19870 | (unsigned long) value); | |
19871 | break; | |
b99bd4ef | 19872 | } |
b99bd4ef | 19873 | |
c19d1205 ZW |
19874 | newimm |= (temp & 0xfffff000); |
19875 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
19876 | break; | |
b99bd4ef | 19877 | |
c19d1205 ZW |
19878 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
19879 | { | |
19880 | unsigned int highpart = 0; | |
19881 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 19882 | |
77db8e2e | 19883 | if (fixP->fx_addsy) |
42e5fcbf | 19884 | { |
77db8e2e | 19885 | const char *msg = 0; |
42e5fcbf | 19886 | |
77db8e2e NC |
19887 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
19888 | msg = _("undefined symbol %s used as an immediate value"); | |
19889 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
19890 | msg = _("symbol %s is in a different section"); | |
19891 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
19892 | msg = _("symbol %s is weak and may be overridden later"); | |
42e5fcbf | 19893 | |
77db8e2e NC |
19894 | if (msg) |
19895 | { | |
19896 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19897 | msg, S_GET_NAME (fixP->fx_addsy)); | |
19898 | break; | |
19899 | } | |
19900 | } | |
19901 | ||
c19d1205 ZW |
19902 | newimm = encode_arm_immediate (value); |
19903 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 19904 | |
c19d1205 ZW |
19905 | /* If the instruction will fail, see if we can fix things up by |
19906 | changing the opcode. */ | |
19907 | if (newimm == (unsigned int) FAIL | |
19908 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
19909 | { | |
19910 | /* No ? OK - try using two ADD instructions to generate | |
19911 | the value. */ | |
19912 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 19913 | |
c19d1205 ZW |
19914 | /* Yes - then make sure that the second instruction is |
19915 | also an add. */ | |
19916 | if (newimm != (unsigned int) FAIL) | |
19917 | newinsn = temp; | |
19918 | /* Still No ? Try using a negated value. */ | |
19919 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
19920 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
19921 | /* Otherwise - give up. */ | |
19922 | else | |
19923 | { | |
19924 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19925 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
19926 | (long) value); | |
19927 | break; | |
19928 | } | |
b99bd4ef | 19929 | |
c19d1205 ZW |
19930 | /* Replace the first operand in the 2nd instruction (which |
19931 | is the PC) with the destination register. We have | |
19932 | already added in the PC in the first instruction and we | |
19933 | do not want to do it again. */ | |
19934 | newinsn &= ~ 0xf0000; | |
19935 | newinsn |= ((newinsn & 0x0f000) << 4); | |
19936 | } | |
b99bd4ef | 19937 | |
c19d1205 ZW |
19938 | newimm |= (temp & 0xfffff000); |
19939 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 19940 | |
c19d1205 ZW |
19941 | highpart |= (newinsn & 0xfffff000); |
19942 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
19943 | } | |
19944 | break; | |
b99bd4ef | 19945 | |
c19d1205 | 19946 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
19947 | if (!fixP->fx_done && seg->use_rela_p) |
19948 | value = 0; | |
19949 | ||
c19d1205 ZW |
19950 | case BFD_RELOC_ARM_LITERAL: |
19951 | sign = value >= 0; | |
b99bd4ef | 19952 | |
c19d1205 ZW |
19953 | if (value < 0) |
19954 | value = - value; | |
b99bd4ef | 19955 | |
c19d1205 | 19956 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 19957 | { |
c19d1205 ZW |
19958 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
19959 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19960 | _("invalid literal constant: pool needs to be closer")); | |
19961 | else | |
19962 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19963 | _("bad immediate value for offset (%ld)"), | |
19964 | (long) value); | |
19965 | break; | |
f03698e6 RE |
19966 | } |
19967 | ||
c19d1205 ZW |
19968 | newval = md_chars_to_number (buf, INSN_SIZE); |
19969 | newval &= 0xff7ff000; | |
19970 | newval |= value | (sign ? INDEX_UP : 0); | |
19971 | md_number_to_chars (buf, newval, INSN_SIZE); | |
19972 | break; | |
b99bd4ef | 19973 | |
c19d1205 ZW |
19974 | case BFD_RELOC_ARM_OFFSET_IMM8: |
19975 | case BFD_RELOC_ARM_HWLITERAL: | |
19976 | sign = value >= 0; | |
b99bd4ef | 19977 | |
c19d1205 ZW |
19978 | if (value < 0) |
19979 | value = - value; | |
b99bd4ef | 19980 | |
c19d1205 | 19981 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 19982 | { |
c19d1205 ZW |
19983 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
19984 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
19985 | _("invalid literal constant: pool needs to be closer")); | |
19986 | else | |
f9d4405b | 19987 | as_bad (_("bad immediate value for 8-bit offset (%ld)"), |
c19d1205 ZW |
19988 | (long) value); |
19989 | break; | |
b99bd4ef NC |
19990 | } |
19991 | ||
c19d1205 ZW |
19992 | newval = md_chars_to_number (buf, INSN_SIZE); |
19993 | newval &= 0xff7ff0f0; | |
19994 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
19995 | md_number_to_chars (buf, newval, INSN_SIZE); | |
19996 | break; | |
b99bd4ef | 19997 | |
c19d1205 ZW |
19998 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
19999 | if (value < 0 || value > 1020 || value % 4 != 0) | |
20000 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20001 | _("bad immediate value for offset (%ld)"), (long) value); | |
20002 | value /= 4; | |
b99bd4ef | 20003 | |
c19d1205 | 20004 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
20005 | newval |= value; |
20006 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
20007 | break; | |
b99bd4ef | 20008 | |
c19d1205 ZW |
20009 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
20010 | /* This is a complicated relocation used for all varieties of Thumb32 | |
20011 | load/store instruction with immediate offset: | |
20012 | ||
20013 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
20014 | *4, optional writeback(W) | |
20015 | (doubleword load/store) | |
20016 | ||
20017 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
20018 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
20019 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
20020 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
20021 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
20022 | ||
20023 | Uppercase letters indicate bits that are already encoded at | |
20024 | this point. Lowercase letters are our problem. For the | |
20025 | second block of instructions, the secondary opcode nybble | |
20026 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
20027 | a PC-relative operation. */ | |
20028 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20029 | newval <<= 16; | |
20030 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 20031 | |
c19d1205 | 20032 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 20033 | { |
c19d1205 ZW |
20034 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
20035 | if (value >= 0) | |
20036 | newval |= (1 << 23); | |
20037 | else | |
20038 | value = -value; | |
20039 | if (value % 4 != 0) | |
20040 | { | |
20041 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20042 | _("offset not a multiple of 4")); | |
20043 | break; | |
20044 | } | |
20045 | value /= 4; | |
216d22bc | 20046 | if (value > 0xff) |
c19d1205 ZW |
20047 | { |
20048 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20049 | _("offset out of range")); | |
20050 | break; | |
20051 | } | |
20052 | newval &= ~0xff; | |
b99bd4ef | 20053 | } |
c19d1205 | 20054 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 20055 | { |
c19d1205 ZW |
20056 | /* PC-relative, 12-bit offset. */ |
20057 | if (value >= 0) | |
20058 | newval |= (1 << 23); | |
20059 | else | |
20060 | value = -value; | |
216d22bc | 20061 | if (value > 0xfff) |
c19d1205 ZW |
20062 | { |
20063 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20064 | _("offset out of range")); | |
20065 | break; | |
20066 | } | |
20067 | newval &= ~0xfff; | |
b99bd4ef | 20068 | } |
c19d1205 | 20069 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 20070 | { |
c19d1205 ZW |
20071 | /* Writeback: 8-bit, +/- offset. */ |
20072 | if (value >= 0) | |
20073 | newval |= (1 << 9); | |
20074 | else | |
20075 | value = -value; | |
216d22bc | 20076 | if (value > 0xff) |
c19d1205 ZW |
20077 | { |
20078 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20079 | _("offset out of range")); | |
20080 | break; | |
20081 | } | |
20082 | newval &= ~0xff; | |
b99bd4ef | 20083 | } |
c19d1205 | 20084 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 20085 | { |
c19d1205 | 20086 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 20087 | if (value < 0 || value > 0xff) |
b99bd4ef | 20088 | { |
c19d1205 ZW |
20089 | as_bad_where (fixP->fx_file, fixP->fx_line, |
20090 | _("offset out of range")); | |
20091 | break; | |
b99bd4ef | 20092 | } |
c19d1205 ZW |
20093 | newval &= ~0xff; |
20094 | newval |= value; | |
b99bd4ef NC |
20095 | } |
20096 | else | |
b99bd4ef | 20097 | { |
c19d1205 ZW |
20098 | /* Positive 12-bit or negative 8-bit offset. */ |
20099 | int limit; | |
20100 | if (value >= 0) | |
b99bd4ef | 20101 | { |
c19d1205 ZW |
20102 | newval |= (1 << 23); |
20103 | limit = 0xfff; | |
20104 | } | |
20105 | else | |
20106 | { | |
20107 | value = -value; | |
20108 | limit = 0xff; | |
20109 | } | |
20110 | if (value > limit) | |
20111 | { | |
20112 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20113 | _("offset out of range")); | |
20114 | break; | |
b99bd4ef | 20115 | } |
c19d1205 | 20116 | newval &= ~limit; |
b99bd4ef | 20117 | } |
b99bd4ef | 20118 | |
c19d1205 ZW |
20119 | newval |= value; |
20120 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
20121 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
20122 | break; | |
404ff6b5 | 20123 | |
c19d1205 ZW |
20124 | case BFD_RELOC_ARM_SHIFT_IMM: |
20125 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20126 | if (((unsigned long) value) > 32 | |
20127 | || (value == 32 | |
20128 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
20129 | { | |
20130 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20131 | _("shift expression is too large")); | |
20132 | break; | |
20133 | } | |
404ff6b5 | 20134 | |
c19d1205 ZW |
20135 | if (value == 0) |
20136 | /* Shifts of zero must be done as lsl. */ | |
20137 | newval &= ~0x60; | |
20138 | else if (value == 32) | |
20139 | value = 0; | |
20140 | newval &= 0xfffff07f; | |
20141 | newval |= (value & 0x1f) << 7; | |
20142 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20143 | break; | |
404ff6b5 | 20144 | |
c19d1205 | 20145 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
16805f35 | 20146 | case BFD_RELOC_ARM_T32_ADD_IMM: |
92e90b6e | 20147 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 20148 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
20149 | /* We claim that this fixup has been processed here, |
20150 | even if in fact we generate an error because we do | |
20151 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
20152 | fixP->fx_done = 1; | |
404ff6b5 | 20153 | |
c19d1205 ZW |
20154 | if (fixP->fx_addsy |
20155 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
20156 | { | |
20157 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20158 | _("undefined symbol %s used as an immediate value"), | |
20159 | S_GET_NAME (fixP->fx_addsy)); | |
20160 | break; | |
20161 | } | |
404ff6b5 | 20162 | |
c19d1205 ZW |
20163 | newval = md_chars_to_number (buf, THUMB_SIZE); |
20164 | newval <<= 16; | |
20165 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 20166 | |
16805f35 PB |
20167 | newimm = FAIL; |
20168 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE | |
20169 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
ef8d22e6 PB |
20170 | { |
20171 | newimm = encode_thumb32_immediate (value); | |
20172 | if (newimm == (unsigned int) FAIL) | |
20173 | newimm = thumb32_negate_data_op (&newval, value); | |
20174 | } | |
16805f35 PB |
20175 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE |
20176 | && newimm == (unsigned int) FAIL) | |
92e90b6e | 20177 | { |
16805f35 PB |
20178 | /* Turn add/sum into addw/subw. */ |
20179 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
20180 | newval = (newval & 0xfeffffff) | 0x02000000; | |
20181 | ||
e9f89963 PB |
20182 | /* 12 bit immediate for addw/subw. */ |
20183 | if (value < 0) | |
20184 | { | |
20185 | value = -value; | |
20186 | newval ^= 0x00a00000; | |
20187 | } | |
92e90b6e PB |
20188 | if (value > 0xfff) |
20189 | newimm = (unsigned int) FAIL; | |
20190 | else | |
20191 | newimm = value; | |
20192 | } | |
cc8a6dd0 | 20193 | |
c19d1205 | 20194 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 20195 | { |
c19d1205 ZW |
20196 | as_bad_where (fixP->fx_file, fixP->fx_line, |
20197 | _("invalid constant (%lx) after fixup"), | |
20198 | (unsigned long) value); | |
20199 | break; | |
3631a3c8 NC |
20200 | } |
20201 | ||
c19d1205 ZW |
20202 | newval |= (newimm & 0x800) << 15; |
20203 | newval |= (newimm & 0x700) << 4; | |
20204 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 20205 | |
c19d1205 ZW |
20206 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
20207 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
20208 | break; | |
a737bd4d | 20209 | |
3eb17e6b | 20210 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
20211 | if (((unsigned long) value) > 0xffff) |
20212 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 20213 | _("invalid smc expression")); |
2fc8bdac | 20214 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
20215 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
20216 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20217 | break; | |
a737bd4d | 20218 | |
c19d1205 | 20219 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 20220 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
20221 | { |
20222 | if (((unsigned long) value) > 0xff) | |
20223 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20224 | _("invalid swi expression")); | |
2fc8bdac | 20225 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
20226 | newval |= value; |
20227 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20228 | } | |
20229 | else | |
20230 | { | |
20231 | if (((unsigned long) value) > 0x00ffffff) | |
20232 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20233 | _("invalid swi expression")); | |
2fc8bdac | 20234 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
20235 | newval |= value; |
20236 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20237 | } | |
20238 | break; | |
a737bd4d | 20239 | |
c19d1205 ZW |
20240 | case BFD_RELOC_ARM_MULTI: |
20241 | if (((unsigned long) value) > 0xffff) | |
20242 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20243 | _("invalid expression in load/store multiple")); | |
20244 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
20245 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20246 | break; | |
a737bd4d | 20247 | |
c19d1205 | 20248 | #ifdef OBJ_ELF |
39b41c9c | 20249 | case BFD_RELOC_ARM_PCREL_CALL: |
267bf995 RR |
20250 | |
20251 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
20252 | && fixP->fx_addsy | |
20253 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20254 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20255 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
20256 | /* Flip the bl to blx. This is a simple flip | |
20257 | bit here because we generate PCREL_CALL for | |
20258 | unconditional bls. */ | |
20259 | { | |
20260 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20261 | newval = newval | 0x10000000; | |
20262 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20263 | temp = 1; | |
20264 | fixP->fx_done = 1; | |
20265 | } | |
39b41c9c PB |
20266 | else |
20267 | temp = 3; | |
20268 | goto arm_branch_common; | |
20269 | ||
20270 | case BFD_RELOC_ARM_PCREL_JUMP: | |
267bf995 RR |
20271 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
20272 | && fixP->fx_addsy | |
20273 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20274 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20275 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
20276 | { | |
20277 | /* This would map to a bl<cond>, b<cond>, | |
20278 | b<always> to a Thumb function. We | |
20279 | need to force a relocation for this particular | |
20280 | case. */ | |
20281 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20282 | fixP->fx_done = 0; | |
20283 | } | |
20284 | ||
2fc8bdac | 20285 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 20286 | #endif |
39b41c9c PB |
20287 | case BFD_RELOC_ARM_PCREL_BRANCH: |
20288 | temp = 3; | |
20289 | goto arm_branch_common; | |
a737bd4d | 20290 | |
39b41c9c | 20291 | case BFD_RELOC_ARM_PCREL_BLX: |
267bf995 | 20292 | |
39b41c9c | 20293 | temp = 1; |
267bf995 RR |
20294 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
20295 | && fixP->fx_addsy | |
20296 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20297 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20298 | && ARM_IS_FUNC (fixP->fx_addsy)) | |
20299 | { | |
20300 | /* Flip the blx to a bl and warn. */ | |
20301 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
20302 | newval = 0xeb000000; | |
20303 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
20304 | _("blx to '%s' an ARM ISA state function changed to bl"), | |
20305 | name); | |
20306 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20307 | temp = 3; | |
20308 | fixP->fx_done = 1; | |
20309 | } | |
20310 | ||
20311 | #ifdef OBJ_ELF | |
20312 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
20313 | fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; | |
20314 | #endif | |
20315 | ||
39b41c9c | 20316 | arm_branch_common: |
c19d1205 | 20317 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
20318 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
20319 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
20320 | also be be clear. */ | |
20321 | if (value & temp) | |
c19d1205 | 20322 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
20323 | _("misaligned branch destination")); |
20324 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
20325 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
20326 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20327 | _("branch out of range")); | |
a737bd4d | 20328 | |
2fc8bdac | 20329 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 20330 | { |
2fc8bdac ZW |
20331 | newval = md_chars_to_number (buf, INSN_SIZE); |
20332 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
20333 | /* Set the H bit on BLX instructions. */ |
20334 | if (temp == 1) | |
20335 | { | |
20336 | if (value & 2) | |
20337 | newval |= 0x01000000; | |
20338 | else | |
20339 | newval &= ~0x01000000; | |
20340 | } | |
2fc8bdac | 20341 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 20342 | } |
c19d1205 | 20343 | break; |
a737bd4d | 20344 | |
25fe350b MS |
20345 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ |
20346 | /* CBZ can only branch forward. */ | |
a737bd4d | 20347 | |
738755b0 MS |
20348 | /* Attempts to use CBZ to branch to the next instruction |
20349 | (which, strictly speaking, are prohibited) will be turned into | |
20350 | no-ops. | |
20351 | ||
20352 | FIXME: It may be better to remove the instruction completely and | |
20353 | perform relaxation. */ | |
20354 | if (value == -2) | |
2fc8bdac ZW |
20355 | { |
20356 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
738755b0 | 20357 | newval = 0xbf00; /* NOP encoding T1 */ |
2fc8bdac ZW |
20358 | md_number_to_chars (buf, newval, THUMB_SIZE); |
20359 | } | |
738755b0 MS |
20360 | else |
20361 | { | |
20362 | if (value & ~0x7e) | |
20363 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20364 | _("branch out of range")); | |
20365 | ||
20366 | if (fixP->fx_done || !seg->use_rela_p) | |
20367 | { | |
20368 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20369 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); | |
20370 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20371 | } | |
20372 | } | |
c19d1205 | 20373 | break; |
a737bd4d | 20374 | |
c19d1205 | 20375 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac ZW |
20376 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
20377 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20378 | _("branch out of range")); | |
a737bd4d | 20379 | |
2fc8bdac ZW |
20380 | if (fixP->fx_done || !seg->use_rela_p) |
20381 | { | |
20382 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20383 | newval |= (value & 0x1ff) >> 1; | |
20384 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20385 | } | |
c19d1205 | 20386 | break; |
a737bd4d | 20387 | |
c19d1205 | 20388 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac ZW |
20389 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
20390 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20391 | _("branch out of range")); | |
a737bd4d | 20392 | |
2fc8bdac ZW |
20393 | if (fixP->fx_done || !seg->use_rela_p) |
20394 | { | |
20395 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20396 | newval |= (value & 0xfff) >> 1; | |
20397 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20398 | } | |
c19d1205 | 20399 | break; |
a737bd4d | 20400 | |
c19d1205 | 20401 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
267bf995 RR |
20402 | if (fixP->fx_addsy |
20403 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20404 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20405 | && S_IS_DEFINED (fixP->fx_addsy) | |
20406 | && ARM_IS_FUNC (fixP->fx_addsy) | |
20407 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20408 | { | |
20409 | /* Force a relocation for a branch 20 bits wide. */ | |
20410 | fixP->fx_done = 0; | |
20411 | } | |
2fc8bdac ZW |
20412 | if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) |
20413 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20414 | _("conditional branch out of range")); | |
404ff6b5 | 20415 | |
2fc8bdac ZW |
20416 | if (fixP->fx_done || !seg->use_rela_p) |
20417 | { | |
20418 | offsetT newval2; | |
20419 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 20420 | |
2fc8bdac ZW |
20421 | S = (value & 0x00100000) >> 20; |
20422 | J2 = (value & 0x00080000) >> 19; | |
20423 | J1 = (value & 0x00040000) >> 18; | |
20424 | hi = (value & 0x0003f000) >> 12; | |
20425 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 20426 | |
2fc8bdac ZW |
20427 | newval = md_chars_to_number (buf, THUMB_SIZE); |
20428 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20429 | newval |= (S << 10) | hi; | |
20430 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
20431 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20432 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
20433 | } | |
c19d1205 | 20434 | break; |
6c43fab6 | 20435 | |
c19d1205 | 20436 | case BFD_RELOC_THUMB_PCREL_BLX: |
267bf995 RR |
20437 | |
20438 | /* If there is a blx from a thumb state function to | |
20439 | another thumb function flip this to a bl and warn | |
20440 | about it. */ | |
20441 | ||
20442 | if (fixP->fx_addsy | |
20443 | && S_IS_DEFINED (fixP->fx_addsy) | |
20444 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20445 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20446 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
20447 | { | |
20448 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
20449 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
20450 | _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), | |
20451 | name); | |
20452 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20453 | newval = newval | 0x1000; | |
20454 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
20455 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
20456 | fixP->fx_done = 1; | |
20457 | } | |
20458 | ||
20459 | ||
20460 | goto thumb_bl_common; | |
20461 | ||
c19d1205 | 20462 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
267bf995 RR |
20463 | |
20464 | /* A bl from Thumb state ISA to an internal ARM state function | |
20465 | is converted to a blx. */ | |
20466 | if (fixP->fx_addsy | |
20467 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20468 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20469 | && S_IS_DEFINED (fixP->fx_addsy) | |
20470 | && ARM_IS_FUNC (fixP->fx_addsy) | |
20471 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20472 | { | |
20473 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20474 | newval = newval & ~0x1000; | |
20475 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
20476 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; | |
20477 | fixP->fx_done = 1; | |
20478 | } | |
20479 | ||
20480 | thumb_bl_common: | |
20481 | ||
20482 | #ifdef OBJ_ELF | |
20483 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 && | |
20484 | fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
20485 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
20486 | #endif | |
20487 | ||
2fc8bdac ZW |
20488 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
20489 | /* For a BLX instruction, make sure that the relocation is rounded up | |
20490 | to a word boundary. This follows the semantics of the instruction | |
20491 | which specifies that bit 1 of the target address will come from bit | |
20492 | 1 of the base address. */ | |
20493 | value = (value + 1) & ~ 1; | |
404ff6b5 | 20494 | |
2fc8bdac | 20495 | |
4a42ebbc RR |
20496 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
20497 | { | |
20498 | if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))) | |
20499 | { | |
20500 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20501 | _("branch out of range")); | |
20502 | } | |
20503 | else if ((value & ~0x1ffffff) | |
20504 | && ((value & ~0x1ffffff) != ~0x1ffffff)) | |
20505 | { | |
20506 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20507 | _("Thumb2 branch out of range")); | |
20508 | } | |
c19d1205 | 20509 | } |
4a42ebbc RR |
20510 | |
20511 | if (fixP->fx_done || !seg->use_rela_p) | |
20512 | encode_thumb2_b_bl_offset (buf, value); | |
20513 | ||
c19d1205 | 20514 | break; |
404ff6b5 | 20515 | |
c19d1205 | 20516 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac ZW |
20517 | if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) |
20518 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20519 | _("branch out of range")); | |
6c43fab6 | 20520 | |
2fc8bdac | 20521 | if (fixP->fx_done || !seg->use_rela_p) |
4a42ebbc | 20522 | encode_thumb2_b_bl_offset (buf, value); |
6c43fab6 | 20523 | |
2fc8bdac | 20524 | break; |
a737bd4d | 20525 | |
2fc8bdac ZW |
20526 | case BFD_RELOC_8: |
20527 | if (fixP->fx_done || !seg->use_rela_p) | |
20528 | md_number_to_chars (buf, value, 1); | |
c19d1205 | 20529 | break; |
a737bd4d | 20530 | |
c19d1205 | 20531 | case BFD_RELOC_16: |
2fc8bdac | 20532 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 20533 | md_number_to_chars (buf, value, 2); |
c19d1205 | 20534 | break; |
a737bd4d | 20535 | |
c19d1205 ZW |
20536 | #ifdef OBJ_ELF |
20537 | case BFD_RELOC_ARM_TLS_GD32: | |
20538 | case BFD_RELOC_ARM_TLS_LE32: | |
20539 | case BFD_RELOC_ARM_TLS_IE32: | |
20540 | case BFD_RELOC_ARM_TLS_LDM32: | |
20541 | case BFD_RELOC_ARM_TLS_LDO32: | |
20542 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
20543 | /* fall through */ | |
6c43fab6 | 20544 | |
c19d1205 ZW |
20545 | case BFD_RELOC_ARM_GOT32: |
20546 | case BFD_RELOC_ARM_GOTOFF: | |
2fc8bdac ZW |
20547 | if (fixP->fx_done || !seg->use_rela_p) |
20548 | md_number_to_chars (buf, 0, 4); | |
c19d1205 | 20549 | break; |
b43420e6 NC |
20550 | |
20551 | case BFD_RELOC_ARM_GOT_PREL: | |
20552 | if (fixP->fx_done || !seg->use_rela_p) | |
20553 | md_number_to_chars (buf, value, 4); | |
20554 | break; | |
20555 | ||
9a6f4e97 NS |
20556 | case BFD_RELOC_ARM_TARGET2: |
20557 | /* TARGET2 is not partial-inplace, so we need to write the | |
20558 | addend here for REL targets, because it won't be written out | |
20559 | during reloc processing later. */ | |
20560 | if (fixP->fx_done || !seg->use_rela_p) | |
20561 | md_number_to_chars (buf, fixP->fx_offset, 4); | |
20562 | break; | |
c19d1205 | 20563 | #endif |
6c43fab6 | 20564 | |
c19d1205 ZW |
20565 | case BFD_RELOC_RVA: |
20566 | case BFD_RELOC_32: | |
20567 | case BFD_RELOC_ARM_TARGET1: | |
20568 | case BFD_RELOC_ARM_ROSEGREL32: | |
20569 | case BFD_RELOC_ARM_SBREL32: | |
20570 | case BFD_RELOC_32_PCREL: | |
f0927246 NC |
20571 | #ifdef TE_PE |
20572 | case BFD_RELOC_32_SECREL: | |
20573 | #endif | |
2fc8bdac | 20574 | if (fixP->fx_done || !seg->use_rela_p) |
53baae48 NC |
20575 | #ifdef TE_WINCE |
20576 | /* For WinCE we only do this for pcrel fixups. */ | |
20577 | if (fixP->fx_done || fixP->fx_pcrel) | |
20578 | #endif | |
20579 | md_number_to_chars (buf, value, 4); | |
c19d1205 | 20580 | break; |
6c43fab6 | 20581 | |
c19d1205 ZW |
20582 | #ifdef OBJ_ELF |
20583 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 20584 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
20585 | { |
20586 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
20587 | if ((value ^ (value >> 1)) & 0x40000000) | |
20588 | { | |
20589 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20590 | _("rel31 relocation overflow")); | |
20591 | } | |
20592 | newval |= value & 0x7fffffff; | |
20593 | md_number_to_chars (buf, newval, 4); | |
20594 | } | |
20595 | break; | |
c19d1205 | 20596 | #endif |
a737bd4d | 20597 | |
c19d1205 | 20598 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 20599 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
20600 | if (value < -1023 || value > 1023 || (value & 3)) |
20601 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20602 | _("co-processor offset out of range")); | |
20603 | cp_off_common: | |
20604 | sign = value >= 0; | |
20605 | if (value < 0) | |
20606 | value = -value; | |
8f06b2d8 PB |
20607 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
20608 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
20609 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20610 | else | |
20611 | newval = get_thumb32_insn (buf); | |
20612 | newval &= 0xff7fff00; | |
c19d1205 | 20613 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); |
8f06b2d8 PB |
20614 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
20615 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
20616 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20617 | else | |
20618 | put_thumb32_insn (buf, newval); | |
c19d1205 | 20619 | break; |
a737bd4d | 20620 | |
c19d1205 | 20621 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 20622 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
20623 | if (value < -255 || value > 255) |
20624 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20625 | _("co-processor offset out of range")); | |
df7849c5 | 20626 | value *= 4; |
c19d1205 | 20627 | goto cp_off_common; |
6c43fab6 | 20628 | |
c19d1205 ZW |
20629 | case BFD_RELOC_ARM_THUMB_OFFSET: |
20630 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20631 | /* Exactly what ranges, and where the offset is inserted depends | |
20632 | on the type of instruction, we can establish this from the | |
20633 | top 4 bits. */ | |
20634 | switch (newval >> 12) | |
20635 | { | |
20636 | case 4: /* PC load. */ | |
20637 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
20638 | forced to zero for these loads; md_pcrel_from has already | |
20639 | compensated for this. */ | |
20640 | if (value & 3) | |
20641 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20642 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
20643 | (((unsigned long) fixP->fx_frag->fr_address |
20644 | + (unsigned long) fixP->fx_where) & ~3) | |
20645 | + (unsigned long) value); | |
a737bd4d | 20646 | |
c19d1205 ZW |
20647 | if (value & ~0x3fc) |
20648 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20649 | _("invalid offset, value too big (0x%08lX)"), | |
20650 | (long) value); | |
a737bd4d | 20651 | |
c19d1205 ZW |
20652 | newval |= value >> 2; |
20653 | break; | |
a737bd4d | 20654 | |
c19d1205 ZW |
20655 | case 9: /* SP load/store. */ |
20656 | if (value & ~0x3fc) | |
20657 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20658 | _("invalid offset, value too big (0x%08lX)"), | |
20659 | (long) value); | |
20660 | newval |= value >> 2; | |
20661 | break; | |
6c43fab6 | 20662 | |
c19d1205 ZW |
20663 | case 6: /* Word load/store. */ |
20664 | if (value & ~0x7c) | |
20665 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20666 | _("invalid offset, value too big (0x%08lX)"), | |
20667 | (long) value); | |
20668 | newval |= value << 4; /* 6 - 2. */ | |
20669 | break; | |
a737bd4d | 20670 | |
c19d1205 ZW |
20671 | case 7: /* Byte load/store. */ |
20672 | if (value & ~0x1f) | |
20673 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20674 | _("invalid offset, value too big (0x%08lX)"), | |
20675 | (long) value); | |
20676 | newval |= value << 6; | |
20677 | break; | |
a737bd4d | 20678 | |
c19d1205 ZW |
20679 | case 8: /* Halfword load/store. */ |
20680 | if (value & ~0x3e) | |
20681 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20682 | _("invalid offset, value too big (0x%08lX)"), | |
20683 | (long) value); | |
20684 | newval |= value << 5; /* 6 - 1. */ | |
20685 | break; | |
a737bd4d | 20686 | |
c19d1205 ZW |
20687 | default: |
20688 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20689 | "Unable to process relocation for thumb opcode: %lx", | |
20690 | (unsigned long) newval); | |
20691 | break; | |
20692 | } | |
20693 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20694 | break; | |
a737bd4d | 20695 | |
c19d1205 ZW |
20696 | case BFD_RELOC_ARM_THUMB_ADD: |
20697 | /* This is a complicated relocation, since we use it for all of | |
20698 | the following immediate relocations: | |
a737bd4d | 20699 | |
c19d1205 ZW |
20700 | 3bit ADD/SUB |
20701 | 8bit ADD/SUB | |
20702 | 9bit ADD/SUB SP word-aligned | |
20703 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 20704 | |
c19d1205 ZW |
20705 | The type of instruction being processed is encoded in the |
20706 | instruction field: | |
a737bd4d | 20707 | |
c19d1205 ZW |
20708 | 0x8000 SUB |
20709 | 0x00F0 Rd | |
20710 | 0x000F Rs | |
20711 | */ | |
20712 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20713 | { | |
20714 | int rd = (newval >> 4) & 0xf; | |
20715 | int rs = newval & 0xf; | |
20716 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 20717 | |
c19d1205 ZW |
20718 | /* Check for HI regs, only very restricted cases allowed: |
20719 | Adjusting SP, and using PC or SP to get an address. */ | |
20720 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
20721 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
20722 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20723 | _("invalid Hi register with immediate")); | |
a737bd4d | 20724 | |
c19d1205 ZW |
20725 | /* If value is negative, choose the opposite instruction. */ |
20726 | if (value < 0) | |
20727 | { | |
20728 | value = -value; | |
20729 | subtract = !subtract; | |
20730 | if (value < 0) | |
20731 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20732 | _("immediate value out of range")); | |
20733 | } | |
a737bd4d | 20734 | |
c19d1205 ZW |
20735 | if (rd == REG_SP) |
20736 | { | |
20737 | if (value & ~0x1fc) | |
20738 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20739 | _("invalid immediate for stack address calculation")); | |
20740 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
20741 | newval |= value >> 2; | |
20742 | } | |
20743 | else if (rs == REG_PC || rs == REG_SP) | |
20744 | { | |
20745 | if (subtract || value & ~0x3fc) | |
20746 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20747 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
20748 | (unsigned long) value); | |
20749 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
20750 | newval |= rd << 8; | |
20751 | newval |= value >> 2; | |
20752 | } | |
20753 | else if (rs == rd) | |
20754 | { | |
20755 | if (value & ~0xff) | |
20756 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20757 | _("immediate value out of range")); | |
20758 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
20759 | newval |= (rd << 8) | value; | |
20760 | } | |
20761 | else | |
20762 | { | |
20763 | if (value & ~0x7) | |
20764 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20765 | _("immediate value out of range")); | |
20766 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
20767 | newval |= rd | (rs << 3) | (value << 6); | |
20768 | } | |
20769 | } | |
20770 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20771 | break; | |
a737bd4d | 20772 | |
c19d1205 ZW |
20773 | case BFD_RELOC_ARM_THUMB_IMM: |
20774 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20775 | if (value < 0 || value > 255) | |
20776 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4e6e072b | 20777 | _("invalid immediate: %ld is out of range"), |
c19d1205 ZW |
20778 | (long) value); |
20779 | newval |= value; | |
20780 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20781 | break; | |
a737bd4d | 20782 | |
c19d1205 ZW |
20783 | case BFD_RELOC_ARM_THUMB_SHIFT: |
20784 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
20785 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
20786 | temp = newval & 0xf800; | |
20787 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
20788 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20789 | _("invalid shift value: %ld"), (long) value); | |
20790 | /* Shifts of zero must be encoded as LSL. */ | |
20791 | if (value == 0) | |
20792 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
20793 | /* Shifts of 32 are encoded as zero. */ | |
20794 | else if (value == 32) | |
20795 | value = 0; | |
20796 | newval |= value << 6; | |
20797 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20798 | break; | |
a737bd4d | 20799 | |
c19d1205 ZW |
20800 | case BFD_RELOC_VTABLE_INHERIT: |
20801 | case BFD_RELOC_VTABLE_ENTRY: | |
20802 | fixP->fx_done = 0; | |
20803 | return; | |
6c43fab6 | 20804 | |
b6895b4f PB |
20805 | case BFD_RELOC_ARM_MOVW: |
20806 | case BFD_RELOC_ARM_MOVT: | |
20807 | case BFD_RELOC_ARM_THUMB_MOVW: | |
20808 | case BFD_RELOC_ARM_THUMB_MOVT: | |
20809 | if (fixP->fx_done || !seg->use_rela_p) | |
20810 | { | |
20811 | /* REL format relocations are limited to a 16-bit addend. */ | |
20812 | if (!fixP->fx_done) | |
20813 | { | |
39623e12 | 20814 | if (value < -0x8000 || value > 0x7fff) |
b6895b4f | 20815 | as_bad_where (fixP->fx_file, fixP->fx_line, |
ff5075ca | 20816 | _("offset out of range")); |
b6895b4f PB |
20817 | } |
20818 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
20819 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
20820 | { | |
20821 | value >>= 16; | |
20822 | } | |
20823 | ||
20824 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
20825 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
20826 | { | |
20827 | newval = get_thumb32_insn (buf); | |
20828 | newval &= 0xfbf08f00; | |
20829 | newval |= (value & 0xf000) << 4; | |
20830 | newval |= (value & 0x0800) << 15; | |
20831 | newval |= (value & 0x0700) << 4; | |
20832 | newval |= (value & 0x00ff); | |
20833 | put_thumb32_insn (buf, newval); | |
20834 | } | |
20835 | else | |
20836 | { | |
20837 | newval = md_chars_to_number (buf, 4); | |
20838 | newval &= 0xfff0f000; | |
20839 | newval |= value & 0x0fff; | |
20840 | newval |= (value & 0xf000) << 4; | |
20841 | md_number_to_chars (buf, newval, 4); | |
20842 | } | |
20843 | } | |
20844 | return; | |
20845 | ||
4962c51a MS |
20846 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
20847 | case BFD_RELOC_ARM_ALU_PC_G0: | |
20848 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
20849 | case BFD_RELOC_ARM_ALU_PC_G1: | |
20850 | case BFD_RELOC_ARM_ALU_PC_G2: | |
20851 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
20852 | case BFD_RELOC_ARM_ALU_SB_G0: | |
20853 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
20854 | case BFD_RELOC_ARM_ALU_SB_G1: | |
20855 | case BFD_RELOC_ARM_ALU_SB_G2: | |
9c2799c2 | 20856 | gas_assert (!fixP->fx_done); |
4962c51a MS |
20857 | if (!seg->use_rela_p) |
20858 | { | |
20859 | bfd_vma insn; | |
20860 | bfd_vma encoded_addend; | |
20861 | bfd_vma addend_abs = abs (value); | |
20862 | ||
20863 | /* Check that the absolute value of the addend can be | |
20864 | expressed as an 8-bit constant plus a rotation. */ | |
20865 | encoded_addend = encode_arm_immediate (addend_abs); | |
20866 | if (encoded_addend == (unsigned int) FAIL) | |
20867 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20868 | _("the offset 0x%08lX is not representable"), | |
495bde8e | 20869 | (unsigned long) addend_abs); |
4962c51a MS |
20870 | |
20871 | /* Extract the instruction. */ | |
20872 | insn = md_chars_to_number (buf, INSN_SIZE); | |
20873 | ||
20874 | /* If the addend is positive, use an ADD instruction. | |
20875 | Otherwise use a SUB. Take care not to destroy the S bit. */ | |
20876 | insn &= 0xff1fffff; | |
20877 | if (value < 0) | |
20878 | insn |= 1 << 22; | |
20879 | else | |
20880 | insn |= 1 << 23; | |
20881 | ||
20882 | /* Place the encoded addend into the first 12 bits of the | |
20883 | instruction. */ | |
20884 | insn &= 0xfffff000; | |
20885 | insn |= encoded_addend; | |
5f4273c7 NC |
20886 | |
20887 | /* Update the instruction. */ | |
4962c51a MS |
20888 | md_number_to_chars (buf, insn, INSN_SIZE); |
20889 | } | |
20890 | break; | |
20891 | ||
20892 | case BFD_RELOC_ARM_LDR_PC_G0: | |
20893 | case BFD_RELOC_ARM_LDR_PC_G1: | |
20894 | case BFD_RELOC_ARM_LDR_PC_G2: | |
20895 | case BFD_RELOC_ARM_LDR_SB_G0: | |
20896 | case BFD_RELOC_ARM_LDR_SB_G1: | |
20897 | case BFD_RELOC_ARM_LDR_SB_G2: | |
9c2799c2 | 20898 | gas_assert (!fixP->fx_done); |
4962c51a MS |
20899 | if (!seg->use_rela_p) |
20900 | { | |
20901 | bfd_vma insn; | |
20902 | bfd_vma addend_abs = abs (value); | |
20903 | ||
20904 | /* Check that the absolute value of the addend can be | |
20905 | encoded in 12 bits. */ | |
20906 | if (addend_abs >= 0x1000) | |
20907 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20908 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), | |
495bde8e | 20909 | (unsigned long) addend_abs); |
4962c51a MS |
20910 | |
20911 | /* Extract the instruction. */ | |
20912 | insn = md_chars_to_number (buf, INSN_SIZE); | |
20913 | ||
20914 | /* If the addend is negative, clear bit 23 of the instruction. | |
20915 | Otherwise set it. */ | |
20916 | if (value < 0) | |
20917 | insn &= ~(1 << 23); | |
20918 | else | |
20919 | insn |= 1 << 23; | |
20920 | ||
20921 | /* Place the absolute value of the addend into the first 12 bits | |
20922 | of the instruction. */ | |
20923 | insn &= 0xfffff000; | |
20924 | insn |= addend_abs; | |
5f4273c7 NC |
20925 | |
20926 | /* Update the instruction. */ | |
4962c51a MS |
20927 | md_number_to_chars (buf, insn, INSN_SIZE); |
20928 | } | |
20929 | break; | |
20930 | ||
20931 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
20932 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
20933 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
20934 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
20935 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
20936 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
9c2799c2 | 20937 | gas_assert (!fixP->fx_done); |
4962c51a MS |
20938 | if (!seg->use_rela_p) |
20939 | { | |
20940 | bfd_vma insn; | |
20941 | bfd_vma addend_abs = abs (value); | |
20942 | ||
20943 | /* Check that the absolute value of the addend can be | |
20944 | encoded in 8 bits. */ | |
20945 | if (addend_abs >= 0x100) | |
20946 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20947 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), | |
495bde8e | 20948 | (unsigned long) addend_abs); |
4962c51a MS |
20949 | |
20950 | /* Extract the instruction. */ | |
20951 | insn = md_chars_to_number (buf, INSN_SIZE); | |
20952 | ||
20953 | /* If the addend is negative, clear bit 23 of the instruction. | |
20954 | Otherwise set it. */ | |
20955 | if (value < 0) | |
20956 | insn &= ~(1 << 23); | |
20957 | else | |
20958 | insn |= 1 << 23; | |
20959 | ||
20960 | /* Place the first four bits of the absolute value of the addend | |
20961 | into the first 4 bits of the instruction, and the remaining | |
20962 | four into bits 8 .. 11. */ | |
20963 | insn &= 0xfffff0f0; | |
20964 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); | |
5f4273c7 NC |
20965 | |
20966 | /* Update the instruction. */ | |
4962c51a MS |
20967 | md_number_to_chars (buf, insn, INSN_SIZE); |
20968 | } | |
20969 | break; | |
20970 | ||
20971 | case BFD_RELOC_ARM_LDC_PC_G0: | |
20972 | case BFD_RELOC_ARM_LDC_PC_G1: | |
20973 | case BFD_RELOC_ARM_LDC_PC_G2: | |
20974 | case BFD_RELOC_ARM_LDC_SB_G0: | |
20975 | case BFD_RELOC_ARM_LDC_SB_G1: | |
20976 | case BFD_RELOC_ARM_LDC_SB_G2: | |
9c2799c2 | 20977 | gas_assert (!fixP->fx_done); |
4962c51a MS |
20978 | if (!seg->use_rela_p) |
20979 | { | |
20980 | bfd_vma insn; | |
20981 | bfd_vma addend_abs = abs (value); | |
20982 | ||
20983 | /* Check that the absolute value of the addend is a multiple of | |
20984 | four and, when divided by four, fits in 8 bits. */ | |
20985 | if (addend_abs & 0x3) | |
20986 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20987 | _("bad offset 0x%08lX (must be word-aligned)"), | |
495bde8e | 20988 | (unsigned long) addend_abs); |
4962c51a MS |
20989 | |
20990 | if ((addend_abs >> 2) > 0xff) | |
20991 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20992 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), | |
495bde8e | 20993 | (unsigned long) addend_abs); |
4962c51a MS |
20994 | |
20995 | /* Extract the instruction. */ | |
20996 | insn = md_chars_to_number (buf, INSN_SIZE); | |
20997 | ||
20998 | /* If the addend is negative, clear bit 23 of the instruction. | |
20999 | Otherwise set it. */ | |
21000 | if (value < 0) | |
21001 | insn &= ~(1 << 23); | |
21002 | else | |
21003 | insn |= 1 << 23; | |
21004 | ||
21005 | /* Place the addend (divided by four) into the first eight | |
21006 | bits of the instruction. */ | |
21007 | insn &= 0xfffffff0; | |
21008 | insn |= addend_abs >> 2; | |
5f4273c7 NC |
21009 | |
21010 | /* Update the instruction. */ | |
4962c51a MS |
21011 | md_number_to_chars (buf, insn, INSN_SIZE); |
21012 | } | |
21013 | break; | |
21014 | ||
845b51d6 PB |
21015 | case BFD_RELOC_ARM_V4BX: |
21016 | /* This will need to go in the object file. */ | |
21017 | fixP->fx_done = 0; | |
21018 | break; | |
21019 | ||
c19d1205 ZW |
21020 | case BFD_RELOC_UNUSED: |
21021 | default: | |
21022 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21023 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
21024 | } | |
6c43fab6 RE |
21025 | } |
21026 | ||
c19d1205 ZW |
21027 | /* Translate internal representation of relocation info to BFD target |
21028 | format. */ | |
a737bd4d | 21029 | |
c19d1205 | 21030 | arelent * |
00a97672 | 21031 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 21032 | { |
c19d1205 ZW |
21033 | arelent * reloc; |
21034 | bfd_reloc_code_real_type code; | |
a737bd4d | 21035 | |
21d799b5 | 21036 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
a737bd4d | 21037 | |
21d799b5 | 21038 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
c19d1205 ZW |
21039 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
21040 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 21041 | |
2fc8bdac | 21042 | if (fixp->fx_pcrel) |
00a97672 RS |
21043 | { |
21044 | if (section->use_rela_p) | |
21045 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
21046 | else | |
21047 | fixp->fx_offset = reloc->address; | |
21048 | } | |
c19d1205 | 21049 | reloc->addend = fixp->fx_offset; |
a737bd4d | 21050 | |
c19d1205 | 21051 | switch (fixp->fx_r_type) |
a737bd4d | 21052 | { |
c19d1205 ZW |
21053 | case BFD_RELOC_8: |
21054 | if (fixp->fx_pcrel) | |
21055 | { | |
21056 | code = BFD_RELOC_8_PCREL; | |
21057 | break; | |
21058 | } | |
a737bd4d | 21059 | |
c19d1205 ZW |
21060 | case BFD_RELOC_16: |
21061 | if (fixp->fx_pcrel) | |
21062 | { | |
21063 | code = BFD_RELOC_16_PCREL; | |
21064 | break; | |
21065 | } | |
6c43fab6 | 21066 | |
c19d1205 ZW |
21067 | case BFD_RELOC_32: |
21068 | if (fixp->fx_pcrel) | |
21069 | { | |
21070 | code = BFD_RELOC_32_PCREL; | |
21071 | break; | |
21072 | } | |
a737bd4d | 21073 | |
b6895b4f PB |
21074 | case BFD_RELOC_ARM_MOVW: |
21075 | if (fixp->fx_pcrel) | |
21076 | { | |
21077 | code = BFD_RELOC_ARM_MOVW_PCREL; | |
21078 | break; | |
21079 | } | |
21080 | ||
21081 | case BFD_RELOC_ARM_MOVT: | |
21082 | if (fixp->fx_pcrel) | |
21083 | { | |
21084 | code = BFD_RELOC_ARM_MOVT_PCREL; | |
21085 | break; | |
21086 | } | |
21087 | ||
21088 | case BFD_RELOC_ARM_THUMB_MOVW: | |
21089 | if (fixp->fx_pcrel) | |
21090 | { | |
21091 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; | |
21092 | break; | |
21093 | } | |
21094 | ||
21095 | case BFD_RELOC_ARM_THUMB_MOVT: | |
21096 | if (fixp->fx_pcrel) | |
21097 | { | |
21098 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; | |
21099 | break; | |
21100 | } | |
21101 | ||
c19d1205 ZW |
21102 | case BFD_RELOC_NONE: |
21103 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
21104 | case BFD_RELOC_ARM_PCREL_BLX: | |
21105 | case BFD_RELOC_RVA: | |
21106 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
21107 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
21108 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
21109 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
21110 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
21111 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
c19d1205 ZW |
21112 | case BFD_RELOC_VTABLE_ENTRY: |
21113 | case BFD_RELOC_VTABLE_INHERIT: | |
f0927246 NC |
21114 | #ifdef TE_PE |
21115 | case BFD_RELOC_32_SECREL: | |
21116 | #endif | |
c19d1205 ZW |
21117 | code = fixp->fx_r_type; |
21118 | break; | |
a737bd4d | 21119 | |
00adf2d4 JB |
21120 | case BFD_RELOC_THUMB_PCREL_BLX: |
21121 | #ifdef OBJ_ELF | |
21122 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
21123 | code = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
21124 | else | |
21125 | #endif | |
21126 | code = BFD_RELOC_THUMB_PCREL_BLX; | |
21127 | break; | |
21128 | ||
c19d1205 ZW |
21129 | case BFD_RELOC_ARM_LITERAL: |
21130 | case BFD_RELOC_ARM_HWLITERAL: | |
21131 | /* If this is called then the a literal has | |
21132 | been referenced across a section boundary. */ | |
21133 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21134 | _("literal referenced across section boundary")); | |
21135 | return NULL; | |
a737bd4d | 21136 | |
c19d1205 ZW |
21137 | #ifdef OBJ_ELF |
21138 | case BFD_RELOC_ARM_GOT32: | |
21139 | case BFD_RELOC_ARM_GOTOFF: | |
b43420e6 | 21140 | case BFD_RELOC_ARM_GOT_PREL: |
c19d1205 ZW |
21141 | case BFD_RELOC_ARM_PLT32: |
21142 | case BFD_RELOC_ARM_TARGET1: | |
21143 | case BFD_RELOC_ARM_ROSEGREL32: | |
21144 | case BFD_RELOC_ARM_SBREL32: | |
21145 | case BFD_RELOC_ARM_PREL31: | |
21146 | case BFD_RELOC_ARM_TARGET2: | |
21147 | case BFD_RELOC_ARM_TLS_LE32: | |
21148 | case BFD_RELOC_ARM_TLS_LDO32: | |
39b41c9c PB |
21149 | case BFD_RELOC_ARM_PCREL_CALL: |
21150 | case BFD_RELOC_ARM_PCREL_JUMP: | |
4962c51a MS |
21151 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
21152 | case BFD_RELOC_ARM_ALU_PC_G0: | |
21153 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
21154 | case BFD_RELOC_ARM_ALU_PC_G1: | |
21155 | case BFD_RELOC_ARM_ALU_PC_G2: | |
21156 | case BFD_RELOC_ARM_LDR_PC_G0: | |
21157 | case BFD_RELOC_ARM_LDR_PC_G1: | |
21158 | case BFD_RELOC_ARM_LDR_PC_G2: | |
21159 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
21160 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
21161 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
21162 | case BFD_RELOC_ARM_LDC_PC_G0: | |
21163 | case BFD_RELOC_ARM_LDC_PC_G1: | |
21164 | case BFD_RELOC_ARM_LDC_PC_G2: | |
21165 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
21166 | case BFD_RELOC_ARM_ALU_SB_G0: | |
21167 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
21168 | case BFD_RELOC_ARM_ALU_SB_G1: | |
21169 | case BFD_RELOC_ARM_ALU_SB_G2: | |
21170 | case BFD_RELOC_ARM_LDR_SB_G0: | |
21171 | case BFD_RELOC_ARM_LDR_SB_G1: | |
21172 | case BFD_RELOC_ARM_LDR_SB_G2: | |
21173 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
21174 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
21175 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
21176 | case BFD_RELOC_ARM_LDC_SB_G0: | |
21177 | case BFD_RELOC_ARM_LDC_SB_G1: | |
21178 | case BFD_RELOC_ARM_LDC_SB_G2: | |
845b51d6 | 21179 | case BFD_RELOC_ARM_V4BX: |
c19d1205 ZW |
21180 | code = fixp->fx_r_type; |
21181 | break; | |
a737bd4d | 21182 | |
c19d1205 ZW |
21183 | case BFD_RELOC_ARM_TLS_GD32: |
21184 | case BFD_RELOC_ARM_TLS_IE32: | |
21185 | case BFD_RELOC_ARM_TLS_LDM32: | |
21186 | /* BFD will include the symbol's address in the addend. | |
21187 | But we don't want that, so subtract it out again here. */ | |
21188 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
21189 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
21190 | code = fixp->fx_r_type; | |
21191 | break; | |
21192 | #endif | |
a737bd4d | 21193 | |
c19d1205 ZW |
21194 | case BFD_RELOC_ARM_IMMEDIATE: |
21195 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21196 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
21197 | return NULL; | |
a737bd4d | 21198 | |
c19d1205 ZW |
21199 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
21200 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21201 | _("ADRL used for a symbol not defined in the same file")); | |
21202 | return NULL; | |
a737bd4d | 21203 | |
c19d1205 | 21204 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
21205 | if (section->use_rela_p) |
21206 | { | |
21207 | code = fixp->fx_r_type; | |
21208 | break; | |
21209 | } | |
21210 | ||
c19d1205 ZW |
21211 | if (fixp->fx_addsy != NULL |
21212 | && !S_IS_DEFINED (fixp->fx_addsy) | |
21213 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 21214 | { |
c19d1205 ZW |
21215 | as_bad_where (fixp->fx_file, fixp->fx_line, |
21216 | _("undefined local label `%s'"), | |
21217 | S_GET_NAME (fixp->fx_addsy)); | |
21218 | return NULL; | |
a737bd4d NC |
21219 | } |
21220 | ||
c19d1205 ZW |
21221 | as_bad_where (fixp->fx_file, fixp->fx_line, |
21222 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
21223 | return NULL; | |
a737bd4d | 21224 | |
c19d1205 ZW |
21225 | default: |
21226 | { | |
21227 | char * type; | |
6c43fab6 | 21228 | |
c19d1205 ZW |
21229 | switch (fixp->fx_r_type) |
21230 | { | |
21231 | case BFD_RELOC_NONE: type = "NONE"; break; | |
21232 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
21233 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 21234 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
21235 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
21236 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
21237 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
db187cb9 | 21238 | case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break; |
8f06b2d8 | 21239 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
21240 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
21241 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
21242 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
21243 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
21244 | default: type = _("<unknown>"); break; | |
21245 | } | |
21246 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21247 | _("cannot represent %s relocation in this object file format"), | |
21248 | type); | |
21249 | return NULL; | |
21250 | } | |
a737bd4d | 21251 | } |
6c43fab6 | 21252 | |
c19d1205 ZW |
21253 | #ifdef OBJ_ELF |
21254 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
21255 | && GOT_symbol | |
21256 | && fixp->fx_addsy == GOT_symbol) | |
21257 | { | |
21258 | code = BFD_RELOC_ARM_GOTPC; | |
21259 | reloc->addend = fixp->fx_offset = reloc->address; | |
21260 | } | |
21261 | #endif | |
6c43fab6 | 21262 | |
c19d1205 | 21263 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 21264 | |
c19d1205 ZW |
21265 | if (reloc->howto == NULL) |
21266 | { | |
21267 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21268 | _("cannot represent %s relocation in this object file format"), | |
21269 | bfd_get_reloc_code_name (code)); | |
21270 | return NULL; | |
21271 | } | |
6c43fab6 | 21272 | |
c19d1205 ZW |
21273 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
21274 | vtable entry to be used in the relocation's section offset. */ | |
21275 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
21276 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 21277 | |
c19d1205 | 21278 | return reloc; |
6c43fab6 RE |
21279 | } |
21280 | ||
c19d1205 | 21281 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 21282 | |
c19d1205 ZW |
21283 | void |
21284 | cons_fix_new_arm (fragS * frag, | |
21285 | int where, | |
21286 | int size, | |
21287 | expressionS * exp) | |
6c43fab6 | 21288 | { |
c19d1205 ZW |
21289 | bfd_reloc_code_real_type type; |
21290 | int pcrel = 0; | |
6c43fab6 | 21291 | |
c19d1205 ZW |
21292 | /* Pick a reloc. |
21293 | FIXME: @@ Should look at CPU word size. */ | |
21294 | switch (size) | |
21295 | { | |
21296 | case 1: | |
21297 | type = BFD_RELOC_8; | |
21298 | break; | |
21299 | case 2: | |
21300 | type = BFD_RELOC_16; | |
21301 | break; | |
21302 | case 4: | |
21303 | default: | |
21304 | type = BFD_RELOC_32; | |
21305 | break; | |
21306 | case 8: | |
21307 | type = BFD_RELOC_64; | |
21308 | break; | |
21309 | } | |
6c43fab6 | 21310 | |
f0927246 NC |
21311 | #ifdef TE_PE |
21312 | if (exp->X_op == O_secrel) | |
21313 | { | |
21314 | exp->X_op = O_symbol; | |
21315 | type = BFD_RELOC_32_SECREL; | |
21316 | } | |
21317 | #endif | |
21318 | ||
c19d1205 ZW |
21319 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); |
21320 | } | |
6c43fab6 | 21321 | |
4343666d | 21322 | #if defined (OBJ_COFF) |
c19d1205 ZW |
21323 | void |
21324 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 21325 | { |
c19d1205 ZW |
21326 | /* If the destination of the branch is a defined symbol which does not have |
21327 | the THUMB_FUNC attribute, then we must be calling a function which has | |
21328 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
21329 | function and change the branch to refer to that function instead. */ | |
21330 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
21331 | && fixP->fx_addsy != NULL | |
21332 | && S_IS_DEFINED (fixP->fx_addsy) | |
21333 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 21334 | { |
c19d1205 | 21335 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 21336 | } |
c19d1205 ZW |
21337 | } |
21338 | #endif | |
6c43fab6 | 21339 | |
267bf995 | 21340 | |
c19d1205 ZW |
21341 | int |
21342 | arm_force_relocation (struct fix * fixp) | |
21343 | { | |
21344 | #if defined (OBJ_COFF) && defined (TE_PE) | |
21345 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
21346 | return 1; | |
21347 | #endif | |
6c43fab6 | 21348 | |
267bf995 RR |
21349 | /* In case we have a call or a branch to a function in ARM ISA mode from |
21350 | a thumb function or vice-versa force the relocation. These relocations | |
21351 | are cleared off for some cores that might have blx and simple transformations | |
21352 | are possible. */ | |
21353 | ||
21354 | #ifdef OBJ_ELF | |
21355 | switch (fixp->fx_r_type) | |
21356 | { | |
21357 | case BFD_RELOC_ARM_PCREL_JUMP: | |
21358 | case BFD_RELOC_ARM_PCREL_CALL: | |
21359 | case BFD_RELOC_THUMB_PCREL_BLX: | |
21360 | if (THUMB_IS_FUNC (fixp->fx_addsy)) | |
21361 | return 1; | |
21362 | break; | |
21363 | ||
21364 | case BFD_RELOC_ARM_PCREL_BLX: | |
21365 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
21366 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
21367 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
21368 | if (ARM_IS_FUNC (fixp->fx_addsy)) | |
21369 | return 1; | |
21370 | break; | |
21371 | ||
21372 | default: | |
21373 | break; | |
21374 | } | |
21375 | #endif | |
21376 | ||
c19d1205 ZW |
21377 | /* Resolve these relocations even if the symbol is extern or weak. */ |
21378 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE | |
21379 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
0110f2b8 | 21380 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
16805f35 | 21381 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
0110f2b8 PB |
21382 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
21383 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
21384 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12) | |
c19d1205 | 21385 | return 0; |
a737bd4d | 21386 | |
4962c51a MS |
21387 | /* Always leave these relocations for the linker. */ |
21388 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
21389 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
21390 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
21391 | return 1; | |
21392 | ||
f0291e4c PB |
21393 | /* Always generate relocations against function symbols. */ |
21394 | if (fixp->fx_r_type == BFD_RELOC_32 | |
21395 | && fixp->fx_addsy | |
21396 | && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) | |
21397 | return 1; | |
21398 | ||
c19d1205 | 21399 | return generic_force_reloc (fixp); |
404ff6b5 AH |
21400 | } |
21401 | ||
0ffdc86c | 21402 | #if defined (OBJ_ELF) || defined (OBJ_COFF) |
e28387c3 PB |
21403 | /* Relocations against function names must be left unadjusted, |
21404 | so that the linker can use this information to generate interworking | |
21405 | stubs. The MIPS version of this function | |
c19d1205 ZW |
21406 | also prevents relocations that are mips-16 specific, but I do not |
21407 | know why it does this. | |
404ff6b5 | 21408 | |
c19d1205 ZW |
21409 | FIXME: |
21410 | There is one other problem that ought to be addressed here, but | |
21411 | which currently is not: Taking the address of a label (rather | |
21412 | than a function) and then later jumping to that address. Such | |
21413 | addresses also ought to have their bottom bit set (assuming that | |
21414 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 21415 | |
c19d1205 ZW |
21416 | bfd_boolean |
21417 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 21418 | { |
c19d1205 ZW |
21419 | if (fixP->fx_addsy == NULL) |
21420 | return 1; | |
404ff6b5 | 21421 | |
e28387c3 PB |
21422 | /* Preserve relocations against symbols with function type. */ |
21423 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) | |
c921be7d | 21424 | return FALSE; |
e28387c3 | 21425 | |
c19d1205 ZW |
21426 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
21427 | && fixP->fx_subsy == NULL) | |
c921be7d | 21428 | return FALSE; |
a737bd4d | 21429 | |
c19d1205 ZW |
21430 | /* We need the symbol name for the VTABLE entries. */ |
21431 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
21432 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c921be7d | 21433 | return FALSE; |
404ff6b5 | 21434 | |
c19d1205 ZW |
21435 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
21436 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
21437 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
21438 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
21439 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
21440 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
21441 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
21442 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
21443 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
21444 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) | |
c921be7d | 21445 | return FALSE; |
a737bd4d | 21446 | |
4962c51a MS |
21447 | /* Similarly for group relocations. */ |
21448 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
21449 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
21450 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
c921be7d | 21451 | return FALSE; |
4962c51a | 21452 | |
79947c54 CD |
21453 | /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ |
21454 | if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW | |
21455 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
21456 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL | |
21457 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL | |
21458 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
21459 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT | |
21460 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL | |
21461 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) | |
c921be7d | 21462 | return FALSE; |
79947c54 | 21463 | |
c921be7d | 21464 | return TRUE; |
a737bd4d | 21465 | } |
0ffdc86c NC |
21466 | #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ |
21467 | ||
21468 | #ifdef OBJ_ELF | |
404ff6b5 | 21469 | |
c19d1205 ZW |
21470 | const char * |
21471 | elf32_arm_target_format (void) | |
404ff6b5 | 21472 | { |
c19d1205 ZW |
21473 | #ifdef TE_SYMBIAN |
21474 | return (target_big_endian | |
21475 | ? "elf32-bigarm-symbian" | |
21476 | : "elf32-littlearm-symbian"); | |
21477 | #elif defined (TE_VXWORKS) | |
21478 | return (target_big_endian | |
21479 | ? "elf32-bigarm-vxworks" | |
21480 | : "elf32-littlearm-vxworks"); | |
21481 | #else | |
21482 | if (target_big_endian) | |
21483 | return "elf32-bigarm"; | |
21484 | else | |
21485 | return "elf32-littlearm"; | |
21486 | #endif | |
404ff6b5 AH |
21487 | } |
21488 | ||
c19d1205 ZW |
21489 | void |
21490 | armelf_frob_symbol (symbolS * symp, | |
21491 | int * puntp) | |
404ff6b5 | 21492 | { |
c19d1205 ZW |
21493 | elf_frob_symbol (symp, puntp); |
21494 | } | |
21495 | #endif | |
404ff6b5 | 21496 | |
c19d1205 | 21497 | /* MD interface: Finalization. */ |
a737bd4d | 21498 | |
c19d1205 ZW |
21499 | void |
21500 | arm_cleanup (void) | |
21501 | { | |
21502 | literal_pool * pool; | |
a737bd4d | 21503 | |
e07e6e58 NC |
21504 | /* Ensure that all the IT blocks are properly closed. */ |
21505 | check_it_blocks_finished (); | |
21506 | ||
c19d1205 ZW |
21507 | for (pool = list_of_pools; pool; pool = pool->next) |
21508 | { | |
5f4273c7 | 21509 | /* Put it at the end of the relevant section. */ |
c19d1205 ZW |
21510 | subseg_set (pool->section, pool->sub_section); |
21511 | #ifdef OBJ_ELF | |
21512 | arm_elf_change_section (); | |
21513 | #endif | |
21514 | s_ltorg (0); | |
21515 | } | |
404ff6b5 AH |
21516 | } |
21517 | ||
cd000bff DJ |
21518 | #ifdef OBJ_ELF |
21519 | /* Remove any excess mapping symbols generated for alignment frags in | |
21520 | SEC. We may have created a mapping symbol before a zero byte | |
21521 | alignment; remove it if there's a mapping symbol after the | |
21522 | alignment. */ | |
21523 | static void | |
21524 | check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, | |
21525 | void *dummy ATTRIBUTE_UNUSED) | |
21526 | { | |
21527 | segment_info_type *seginfo = seg_info (sec); | |
21528 | fragS *fragp; | |
21529 | ||
21530 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
21531 | return; | |
21532 | ||
21533 | for (fragp = seginfo->frchainP->frch_root; | |
21534 | fragp != NULL; | |
21535 | fragp = fragp->fr_next) | |
21536 | { | |
21537 | symbolS *sym = fragp->tc_frag_data.last_map; | |
21538 | fragS *next = fragp->fr_next; | |
21539 | ||
21540 | /* Variable-sized frags have been converted to fixed size by | |
21541 | this point. But if this was variable-sized to start with, | |
21542 | there will be a fixed-size frag after it. So don't handle | |
21543 | next == NULL. */ | |
21544 | if (sym == NULL || next == NULL) | |
21545 | continue; | |
21546 | ||
21547 | if (S_GET_VALUE (sym) < next->fr_address) | |
21548 | /* Not at the end of this frag. */ | |
21549 | continue; | |
21550 | know (S_GET_VALUE (sym) == next->fr_address); | |
21551 | ||
21552 | do | |
21553 | { | |
21554 | if (next->tc_frag_data.first_map != NULL) | |
21555 | { | |
21556 | /* Next frag starts with a mapping symbol. Discard this | |
21557 | one. */ | |
21558 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
21559 | break; | |
21560 | } | |
21561 | ||
21562 | if (next->fr_next == NULL) | |
21563 | { | |
21564 | /* This mapping symbol is at the end of the section. Discard | |
21565 | it. */ | |
21566 | know (next->fr_fix == 0 && next->fr_var == 0); | |
21567 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
21568 | break; | |
21569 | } | |
21570 | ||
21571 | /* As long as we have empty frags without any mapping symbols, | |
21572 | keep looking. */ | |
21573 | /* If the next frag is non-empty and does not start with a | |
21574 | mapping symbol, then this mapping symbol is required. */ | |
21575 | if (next->fr_address != next->fr_next->fr_address) | |
21576 | break; | |
21577 | ||
21578 | next = next->fr_next; | |
21579 | } | |
21580 | while (next != NULL); | |
21581 | } | |
21582 | } | |
21583 | #endif | |
21584 | ||
c19d1205 ZW |
21585 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
21586 | ARM ones. */ | |
404ff6b5 | 21587 | |
c19d1205 ZW |
21588 | void |
21589 | arm_adjust_symtab (void) | |
404ff6b5 | 21590 | { |
c19d1205 ZW |
21591 | #ifdef OBJ_COFF |
21592 | symbolS * sym; | |
404ff6b5 | 21593 | |
c19d1205 ZW |
21594 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
21595 | { | |
21596 | if (ARM_IS_THUMB (sym)) | |
21597 | { | |
21598 | if (THUMB_IS_FUNC (sym)) | |
21599 | { | |
21600 | /* Mark the symbol as a Thumb function. */ | |
21601 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
21602 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
21603 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 21604 | |
c19d1205 ZW |
21605 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
21606 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
21607 | else | |
21608 | as_bad (_("%s: unexpected function type: %d"), | |
21609 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
21610 | } | |
21611 | else switch (S_GET_STORAGE_CLASS (sym)) | |
21612 | { | |
21613 | case C_EXT: | |
21614 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
21615 | break; | |
21616 | case C_STAT: | |
21617 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
21618 | break; | |
21619 | case C_LABEL: | |
21620 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
21621 | break; | |
21622 | default: | |
21623 | /* Do nothing. */ | |
21624 | break; | |
21625 | } | |
21626 | } | |
a737bd4d | 21627 | |
c19d1205 ZW |
21628 | if (ARM_IS_INTERWORK (sym)) |
21629 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 21630 | } |
c19d1205 ZW |
21631 | #endif |
21632 | #ifdef OBJ_ELF | |
21633 | symbolS * sym; | |
21634 | char bind; | |
404ff6b5 | 21635 | |
c19d1205 | 21636 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 21637 | { |
c19d1205 ZW |
21638 | if (ARM_IS_THUMB (sym)) |
21639 | { | |
21640 | elf_symbol_type * elf_sym; | |
404ff6b5 | 21641 | |
c19d1205 ZW |
21642 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
21643 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 21644 | |
b0796911 PB |
21645 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
21646 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) | |
c19d1205 ZW |
21647 | { |
21648 | /* If it's a .thumb_func, declare it as so, | |
21649 | otherwise tag label as .code 16. */ | |
21650 | if (THUMB_IS_FUNC (sym)) | |
21651 | elf_sym->internal_elf_sym.st_info = | |
21652 | ELF_ST_INFO (bind, STT_ARM_TFUNC); | |
3ba67470 | 21653 | else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
c19d1205 ZW |
21654 | elf_sym->internal_elf_sym.st_info = |
21655 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
21656 | } | |
21657 | } | |
21658 | } | |
cd000bff DJ |
21659 | |
21660 | /* Remove any overlapping mapping symbols generated by alignment frags. */ | |
21661 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); | |
c19d1205 | 21662 | #endif |
404ff6b5 AH |
21663 | } |
21664 | ||
c19d1205 | 21665 | /* MD interface: Initialization. */ |
404ff6b5 | 21666 | |
a737bd4d | 21667 | static void |
c19d1205 | 21668 | set_constant_flonums (void) |
a737bd4d | 21669 | { |
c19d1205 | 21670 | int i; |
404ff6b5 | 21671 | |
c19d1205 ZW |
21672 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
21673 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
21674 | abort (); | |
a737bd4d | 21675 | } |
404ff6b5 | 21676 | |
3e9e4fcf JB |
21677 | /* Auto-select Thumb mode if it's the only available instruction set for the |
21678 | given architecture. */ | |
21679 | ||
21680 | static void | |
21681 | autoselect_thumb_from_cpu_variant (void) | |
21682 | { | |
21683 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) | |
21684 | opcode_select (16); | |
21685 | } | |
21686 | ||
c19d1205 ZW |
21687 | void |
21688 | md_begin (void) | |
a737bd4d | 21689 | { |
c19d1205 ZW |
21690 | unsigned mach; |
21691 | unsigned int i; | |
404ff6b5 | 21692 | |
c19d1205 ZW |
21693 | if ( (arm_ops_hsh = hash_new ()) == NULL |
21694 | || (arm_cond_hsh = hash_new ()) == NULL | |
21695 | || (arm_shift_hsh = hash_new ()) == NULL | |
21696 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 21697 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 21698 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
21699 | || (arm_reloc_hsh = hash_new ()) == NULL |
21700 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
21701 | as_fatal (_("virtual memory exhausted")); |
21702 | ||
21703 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
d3ce72d0 | 21704 | hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); |
c19d1205 | 21705 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) |
d3ce72d0 | 21706 | hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); |
c19d1205 | 21707 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) |
5a49b8ac | 21708 | hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); |
c19d1205 | 21709 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 21710 | hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); |
62b3e311 | 21711 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 NC |
21712 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, |
21713 | (void *) (v7m_psrs + i)); | |
c19d1205 | 21714 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
5a49b8ac | 21715 | hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); |
62b3e311 PB |
21716 | for (i = 0; |
21717 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
21718 | i++) | |
d3ce72d0 | 21719 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, |
5a49b8ac | 21720 | (void *) (barrier_opt_names + i)); |
c19d1205 ZW |
21721 | #ifdef OBJ_ELF |
21722 | for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) | |
5a49b8ac | 21723 | hash_insert (arm_reloc_hsh, reloc_names[i].name, (void *) (reloc_names + i)); |
c19d1205 ZW |
21724 | #endif |
21725 | ||
21726 | set_constant_flonums (); | |
404ff6b5 | 21727 | |
c19d1205 ZW |
21728 | /* Set the cpu variant based on the command-line options. We prefer |
21729 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
21730 | -mfpu= over any other way of setting the floating point unit. | |
21731 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 21732 | if (legacy_cpu) |
404ff6b5 | 21733 | { |
e74cfd16 | 21734 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
21735 | as_bad (_("use of old and new-style options to set CPU type")); |
21736 | ||
21737 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 21738 | } |
e74cfd16 | 21739 | else if (!mcpu_cpu_opt) |
c19d1205 | 21740 | mcpu_cpu_opt = march_cpu_opt; |
404ff6b5 | 21741 | |
e74cfd16 | 21742 | if (legacy_fpu) |
c19d1205 | 21743 | { |
e74cfd16 | 21744 | if (mfpu_opt) |
c19d1205 | 21745 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f RE |
21746 | |
21747 | mfpu_opt = legacy_fpu; | |
21748 | } | |
e74cfd16 | 21749 | else if (!mfpu_opt) |
03b1477f | 21750 | { |
45eb4c1b NS |
21751 | #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ |
21752 | || defined (TE_NetBSD) || defined (TE_VXWORKS)) | |
39c2da32 RE |
21753 | /* Some environments specify a default FPU. If they don't, infer it |
21754 | from the processor. */ | |
e74cfd16 | 21755 | if (mcpu_fpu_opt) |
03b1477f RE |
21756 | mfpu_opt = mcpu_fpu_opt; |
21757 | else | |
21758 | mfpu_opt = march_fpu_opt; | |
39c2da32 | 21759 | #else |
e74cfd16 | 21760 | mfpu_opt = &fpu_default; |
39c2da32 | 21761 | #endif |
03b1477f RE |
21762 | } |
21763 | ||
e74cfd16 | 21764 | if (!mfpu_opt) |
03b1477f | 21765 | { |
493cb6ef | 21766 | if (mcpu_cpu_opt != NULL) |
e74cfd16 | 21767 | mfpu_opt = &fpu_default; |
493cb6ef | 21768 | else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) |
e74cfd16 | 21769 | mfpu_opt = &fpu_arch_vfp_v2; |
03b1477f | 21770 | else |
e74cfd16 | 21771 | mfpu_opt = &fpu_arch_fpa; |
03b1477f RE |
21772 | } |
21773 | ||
ee065d83 | 21774 | #ifdef CPU_DEFAULT |
e74cfd16 | 21775 | if (!mcpu_cpu_opt) |
ee065d83 | 21776 | { |
e74cfd16 PB |
21777 | mcpu_cpu_opt = &cpu_default; |
21778 | selected_cpu = cpu_default; | |
ee065d83 | 21779 | } |
e74cfd16 PB |
21780 | #else |
21781 | if (mcpu_cpu_opt) | |
21782 | selected_cpu = *mcpu_cpu_opt; | |
ee065d83 | 21783 | else |
e74cfd16 | 21784 | mcpu_cpu_opt = &arm_arch_any; |
ee065d83 | 21785 | #endif |
03b1477f | 21786 | |
e74cfd16 | 21787 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
03b1477f | 21788 | |
3e9e4fcf JB |
21789 | autoselect_thumb_from_cpu_variant (); |
21790 | ||
e74cfd16 | 21791 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 21792 | |
f17c130b | 21793 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 21794 | { |
7cc69913 NC |
21795 | unsigned int flags = 0; |
21796 | ||
21797 | #if defined OBJ_ELF | |
21798 | flags = meabi_flags; | |
d507cf36 PB |
21799 | |
21800 | switch (meabi_flags) | |
33a392fb | 21801 | { |
d507cf36 | 21802 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 21803 | #endif |
d507cf36 PB |
21804 | /* Set the flags in the private structure. */ |
21805 | if (uses_apcs_26) flags |= F_APCS26; | |
21806 | if (support_interwork) flags |= F_INTERWORK; | |
21807 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 21808 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 21809 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
21810 | flags |= F_SOFT_FLOAT; |
21811 | ||
d507cf36 PB |
21812 | switch (mfloat_abi_opt) |
21813 | { | |
21814 | case ARM_FLOAT_ABI_SOFT: | |
21815 | case ARM_FLOAT_ABI_SOFTFP: | |
21816 | flags |= F_SOFT_FLOAT; | |
21817 | break; | |
33a392fb | 21818 | |
d507cf36 PB |
21819 | case ARM_FLOAT_ABI_HARD: |
21820 | if (flags & F_SOFT_FLOAT) | |
21821 | as_bad (_("hard-float conflicts with specified fpu")); | |
21822 | break; | |
21823 | } | |
03b1477f | 21824 | |
e74cfd16 PB |
21825 | /* Using pure-endian doubles (even if soft-float). */ |
21826 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 21827 | flags |= F_VFP_FLOAT; |
f17c130b | 21828 | |
fde78edd | 21829 | #if defined OBJ_ELF |
e74cfd16 | 21830 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 21831 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
21832 | break; |
21833 | ||
8cb51566 | 21834 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 21835 | case EF_ARM_EABI_VER5: |
c19d1205 | 21836 | /* No additional flags to set. */ |
d507cf36 PB |
21837 | break; |
21838 | ||
21839 | default: | |
21840 | abort (); | |
21841 | } | |
7cc69913 | 21842 | #endif |
b99bd4ef NC |
21843 | bfd_set_private_flags (stdoutput, flags); |
21844 | ||
21845 | /* We have run out flags in the COFF header to encode the | |
21846 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 21847 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
21848 | if (atpcs) |
21849 | { | |
21850 | asection * sec; | |
21851 | ||
21852 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
21853 | ||
21854 | if (sec != NULL) | |
21855 | { | |
21856 | bfd_set_section_flags | |
21857 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
21858 | bfd_set_section_size (stdoutput, sec, 0); | |
21859 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
21860 | } | |
21861 | } | |
7cc69913 | 21862 | } |
f17c130b | 21863 | #endif |
b99bd4ef NC |
21864 | |
21865 | /* Record the CPU type as well. */ | |
2d447fca JM |
21866 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) |
21867 | mach = bfd_mach_arm_iWMMXt2; | |
21868 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) | |
e16bb312 | 21869 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 21870 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 21871 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 21872 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 21873 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 21874 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 21875 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 21876 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 21877 | { |
e74cfd16 | 21878 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
21879 | mach = bfd_mach_arm_5T; |
21880 | else | |
21881 | mach = bfd_mach_arm_5; | |
21882 | } | |
e74cfd16 | 21883 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 21884 | { |
e74cfd16 | 21885 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
21886 | mach = bfd_mach_arm_4T; |
21887 | else | |
21888 | mach = bfd_mach_arm_4; | |
21889 | } | |
e74cfd16 | 21890 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 21891 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
21892 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
21893 | mach = bfd_mach_arm_3; | |
21894 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
21895 | mach = bfd_mach_arm_2a; | |
21896 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
21897 | mach = bfd_mach_arm_2; | |
21898 | else | |
21899 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
21900 | |
21901 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
21902 | } | |
21903 | ||
c19d1205 | 21904 | /* Command line processing. */ |
b99bd4ef | 21905 | |
c19d1205 ZW |
21906 | /* md_parse_option |
21907 | Invocation line includes a switch not recognized by the base assembler. | |
21908 | See if it's a processor-specific option. | |
b99bd4ef | 21909 | |
c19d1205 ZW |
21910 | This routine is somewhat complicated by the need for backwards |
21911 | compatibility (since older releases of gcc can't be changed). | |
21912 | The new options try to make the interface as compatible as | |
21913 | possible with GCC. | |
b99bd4ef | 21914 | |
c19d1205 | 21915 | New options (supported) are: |
b99bd4ef | 21916 | |
c19d1205 ZW |
21917 | -mcpu=<cpu name> Assemble for selected processor |
21918 | -march=<architecture name> Assemble for selected architecture | |
21919 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
21920 | -EB/-mbig-endian Big-endian | |
21921 | -EL/-mlittle-endian Little-endian | |
21922 | -k Generate PIC code | |
21923 | -mthumb Start in Thumb mode | |
21924 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 21925 | |
278df34e | 21926 | -m[no-]warn-deprecated Warn about deprecated features |
267bf995 | 21927 | |
c19d1205 | 21928 | For now we will also provide support for: |
b99bd4ef | 21929 | |
c19d1205 ZW |
21930 | -mapcs-32 32-bit Program counter |
21931 | -mapcs-26 26-bit Program counter | |
21932 | -macps-float Floats passed in FP registers | |
21933 | -mapcs-reentrant Reentrant code | |
21934 | -matpcs | |
21935 | (sometime these will probably be replaced with -mapcs=<list of options> | |
21936 | and -matpcs=<list of options>) | |
b99bd4ef | 21937 | |
c19d1205 ZW |
21938 | The remaining options are only supported for back-wards compatibility. |
21939 | Cpu variants, the arm part is optional: | |
21940 | -m[arm]1 Currently not supported. | |
21941 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
21942 | -m[arm]3 Arm 3 processor | |
21943 | -m[arm]6[xx], Arm 6 processors | |
21944 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
21945 | -m[arm]8[10] Arm 8 processors | |
21946 | -m[arm]9[20][tdmi] Arm 9 processors | |
21947 | -mstrongarm[110[0]] StrongARM processors | |
21948 | -mxscale XScale processors | |
21949 | -m[arm]v[2345[t[e]]] Arm architectures | |
21950 | -mall All (except the ARM1) | |
21951 | FP variants: | |
21952 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
21953 | -mfpe-old (No float load/store multiples) | |
21954 | -mvfpxd VFP Single precision | |
21955 | -mvfp All VFP | |
21956 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 21957 | |
c19d1205 ZW |
21958 | The following CPU names are recognized: |
21959 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
21960 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
21961 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
21962 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
21963 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
21964 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
21965 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 21966 | |
c19d1205 | 21967 | */ |
b99bd4ef | 21968 | |
c19d1205 | 21969 | const char * md_shortopts = "m:k"; |
b99bd4ef | 21970 | |
c19d1205 ZW |
21971 | #ifdef ARM_BI_ENDIAN |
21972 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
21973 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 21974 | #else |
c19d1205 ZW |
21975 | #if TARGET_BYTES_BIG_ENDIAN |
21976 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 21977 | #else |
c19d1205 ZW |
21978 | #define OPTION_EL (OPTION_MD_BASE + 1) |
21979 | #endif | |
b99bd4ef | 21980 | #endif |
845b51d6 | 21981 | #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) |
b99bd4ef | 21982 | |
c19d1205 | 21983 | struct option md_longopts[] = |
b99bd4ef | 21984 | { |
c19d1205 ZW |
21985 | #ifdef OPTION_EB |
21986 | {"EB", no_argument, NULL, OPTION_EB}, | |
21987 | #endif | |
21988 | #ifdef OPTION_EL | |
21989 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 21990 | #endif |
845b51d6 | 21991 | {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, |
c19d1205 ZW |
21992 | {NULL, no_argument, NULL, 0} |
21993 | }; | |
b99bd4ef | 21994 | |
c19d1205 | 21995 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 21996 | |
c19d1205 | 21997 | struct arm_option_table |
b99bd4ef | 21998 | { |
c19d1205 ZW |
21999 | char *option; /* Option name to match. */ |
22000 | char *help; /* Help information. */ | |
22001 | int *var; /* Variable to change. */ | |
22002 | int value; /* What to change it to. */ | |
22003 | char *deprecated; /* If non-null, print this message. */ | |
22004 | }; | |
b99bd4ef | 22005 | |
c19d1205 ZW |
22006 | struct arm_option_table arm_opts[] = |
22007 | { | |
22008 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
22009 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
22010 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
22011 | &support_interwork, 1, NULL}, | |
22012 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
22013 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
22014 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
22015 | 1, NULL}, | |
22016 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
22017 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
22018 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
22019 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
22020 | NULL}, | |
b99bd4ef | 22021 | |
c19d1205 ZW |
22022 | /* These are recognized by the assembler, but have no affect on code. */ |
22023 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
22024 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
278df34e NS |
22025 | |
22026 | {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, | |
22027 | {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), | |
22028 | &warn_on_deprecated, 0, NULL}, | |
e74cfd16 PB |
22029 | {NULL, NULL, NULL, 0, NULL} |
22030 | }; | |
22031 | ||
22032 | struct arm_legacy_option_table | |
22033 | { | |
22034 | char *option; /* Option name to match. */ | |
22035 | const arm_feature_set **var; /* Variable to change. */ | |
22036 | const arm_feature_set value; /* What to change it to. */ | |
22037 | char *deprecated; /* If non-null, print this message. */ | |
22038 | }; | |
b99bd4ef | 22039 | |
e74cfd16 PB |
22040 | const struct arm_legacy_option_table arm_legacy_opts[] = |
22041 | { | |
c19d1205 ZW |
22042 | /* DON'T add any new processors to this list -- we want the whole list |
22043 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
22044 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
22045 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
22046 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
22047 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
22048 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
22049 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
22050 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
22051 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
22052 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
22053 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
22054 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
22055 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
22056 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
22057 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
22058 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
22059 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
22060 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
22061 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
22062 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
22063 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
22064 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
22065 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
22066 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
22067 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
22068 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
22069 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
22070 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
22071 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
22072 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
22073 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
22074 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
22075 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
22076 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
22077 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
22078 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
22079 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
22080 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
22081 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
22082 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
22083 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
22084 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
22085 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
22086 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
22087 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
22088 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
22089 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
22090 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22091 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22092 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22093 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22094 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
22095 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
22096 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
22097 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
22098 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
22099 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
22100 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
22101 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
22102 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
22103 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
22104 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
22105 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
22106 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
22107 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
22108 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
22109 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
22110 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
22111 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
22112 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
22113 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 22114 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 22115 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 22116 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 22117 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 22118 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
22119 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
22120 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
22121 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 22122 | |
c19d1205 | 22123 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
22124 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
22125 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
22126 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
22127 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
22128 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
22129 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
22130 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
22131 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
22132 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
22133 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
22134 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
22135 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
22136 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
22137 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
22138 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
22139 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
22140 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
22141 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 22142 | |
c19d1205 | 22143 | /* Floating point variants -- don't add any more to this list either. */ |
e74cfd16 PB |
22144 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
22145 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
22146 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
22147 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 22148 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 22149 | |
e74cfd16 | 22150 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 22151 | }; |
7ed4c4c5 | 22152 | |
c19d1205 | 22153 | struct arm_cpu_option_table |
7ed4c4c5 | 22154 | { |
c19d1205 | 22155 | char *name; |
e74cfd16 | 22156 | const arm_feature_set value; |
c19d1205 ZW |
22157 | /* For some CPUs we assume an FPU unless the user explicitly sets |
22158 | -mfpu=... */ | |
e74cfd16 | 22159 | const arm_feature_set default_fpu; |
ee065d83 PB |
22160 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
22161 | case. */ | |
22162 | const char *canonical_name; | |
c19d1205 | 22163 | }; |
7ed4c4c5 | 22164 | |
c19d1205 ZW |
22165 | /* This list should, at a minimum, contain all the cpu names |
22166 | recognized by GCC. */ | |
e74cfd16 | 22167 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 22168 | { |
ee065d83 PB |
22169 | {"all", ARM_ANY, FPU_ARCH_FPA, NULL}, |
22170 | {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL}, | |
22171 | {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL}, | |
22172 | {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
22173 | {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
22174 | {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22175 | {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22176 | {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22177 | {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22178 | {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22179 | {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22180 | {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
22181 | {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22182 | {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
22183 | {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22184 | {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
22185 | {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22186 | {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22187 | {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22188 | {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22189 | {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22190 | {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22191 | {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22192 | {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22193 | {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22194 | {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22195 | {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22196 | {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22197 | {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22198 | {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22199 | {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22200 | {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22201 | {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22202 | {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22203 | {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22204 | {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22205 | {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22206 | {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22207 | {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22208 | {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"}, | |
22209 | {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22210 | {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22211 | {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22212 | {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
7fac0536 NC |
22213 | {"fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, |
22214 | {"fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
c19d1205 ZW |
22215 | /* For V5 or later processors we default to using VFP; but the user |
22216 | should really set the FPU type explicitly. */ | |
ee065d83 PB |
22217 | {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, |
22218 | {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22219 | {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
22220 | {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
22221 | {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
22222 | {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
22223 | {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"}, | |
22224 | {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22225 | {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
22226 | {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"}, | |
22227 | {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22228 | {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22229 | {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
22230 | {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
22231 | {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22232 | {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"}, | |
22233 | {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
22234 | {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22235 | {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22236 | {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"}, | |
22237 | {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
7fac0536 NC |
22238 | {"fa626te", ARM_ARCH_V5TE, FPU_NONE, NULL}, |
22239 | {"fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
ee065d83 PB |
22240 | {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"}, |
22241 | {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL}, | |
22242 | {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"}, | |
22243 | {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL}, | |
22244 | {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL}, | |
22245 | {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL}, | |
22246 | {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL}, | |
22247 | {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL}, | |
22248 | {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL}, | |
22249 | {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL}, | |
b38f9f31 | 22250 | {"cortex-a5", ARM_ARCH_V7A, FPU_NONE, NULL}, |
e07e6e58 | 22251 | {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE (0, FPU_VFP_V3 |
5287ad62 | 22252 | | FPU_NEON_EXT_V1), |
15290f0a | 22253 | NULL}, |
e07e6e58 | 22254 | {"cortex-a9", ARM_ARCH_V7A, ARM_FEATURE (0, FPU_VFP_V3 |
15290f0a | 22255 | | FPU_NEON_EXT_V1), |
5287ad62 | 22256 | NULL}, |
62b3e311 | 22257 | {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL}, |
307c948d | 22258 | {"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16, NULL}, |
26b6f191 | 22259 | {"cortex-m4", ARM_ARCH_V7EM, FPU_NONE, NULL}, |
62b3e311 | 22260 | {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL}, |
7e806470 | 22261 | {"cortex-m1", ARM_ARCH_V6M, FPU_NONE, NULL}, |
5b19eaba | 22262 | {"cortex-m0", ARM_ARCH_V6M, FPU_NONE, NULL}, |
c19d1205 | 22263 | /* ??? XSCALE is really an architecture. */ |
ee065d83 | 22264 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, |
c19d1205 | 22265 | /* ??? iwmmxt is not a processor. */ |
ee065d83 | 22266 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL}, |
2d447fca | 22267 | {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL}, |
ee065d83 | 22268 | {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, |
c19d1205 | 22269 | /* Maverick */ |
e07e6e58 | 22270 | {"ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"}, |
e74cfd16 | 22271 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL} |
c19d1205 | 22272 | }; |
7ed4c4c5 | 22273 | |
c19d1205 | 22274 | struct arm_arch_option_table |
7ed4c4c5 | 22275 | { |
c19d1205 | 22276 | char *name; |
e74cfd16 PB |
22277 | const arm_feature_set value; |
22278 | const arm_feature_set default_fpu; | |
c19d1205 | 22279 | }; |
7ed4c4c5 | 22280 | |
c19d1205 ZW |
22281 | /* This list should, at a minimum, contain all the architecture names |
22282 | recognized by GCC. */ | |
e74cfd16 | 22283 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 ZW |
22284 | { |
22285 | {"all", ARM_ANY, FPU_ARCH_FPA}, | |
22286 | {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, | |
22287 | {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, | |
22288 | {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
22289 | {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
22290 | {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
22291 | {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, | |
22292 | {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
22293 | {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, | |
22294 | {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
22295 | {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, | |
22296 | {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, | |
22297 | {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, | |
22298 | {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, | |
22299 | {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, | |
22300 | {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, | |
22301 | {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, | |
22302 | {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
22303 | {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
22304 | {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, | |
22305 | {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, | |
22306 | {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, | |
22307 | {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, | |
22308 | {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, | |
22309 | {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, | |
22310 | {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, | |
7e806470 | 22311 | {"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP}, |
62b3e311 | 22312 | {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP}, |
c450d570 PB |
22313 | /* The official spelling of the ARMv7 profile variants is the dashed form. |
22314 | Accept the non-dashed form for compatibility with old toolchains. */ | |
62b3e311 PB |
22315 | {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP}, |
22316 | {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP}, | |
22317 | {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP}, | |
c450d570 PB |
22318 | {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP}, |
22319 | {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP}, | |
22320 | {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP}, | |
9e3c6df6 | 22321 | {"armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP}, |
c19d1205 ZW |
22322 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, |
22323 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, | |
2d447fca | 22324 | {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP}, |
e74cfd16 | 22325 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} |
c19d1205 | 22326 | }; |
7ed4c4c5 | 22327 | |
c19d1205 | 22328 | /* ISA extensions in the co-processor space. */ |
e74cfd16 | 22329 | struct arm_option_cpu_value_table |
c19d1205 ZW |
22330 | { |
22331 | char *name; | |
e74cfd16 | 22332 | const arm_feature_set value; |
c19d1205 | 22333 | }; |
7ed4c4c5 | 22334 | |
e74cfd16 | 22335 | static const struct arm_option_cpu_value_table arm_extensions[] = |
c19d1205 | 22336 | { |
e74cfd16 PB |
22337 | {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)}, |
22338 | {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)}, | |
22339 | {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)}, | |
2d447fca | 22340 | {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2)}, |
e74cfd16 | 22341 | {NULL, ARM_ARCH_NONE} |
c19d1205 | 22342 | }; |
7ed4c4c5 | 22343 | |
c19d1205 ZW |
22344 | /* This list should, at a minimum, contain all the fpu names |
22345 | recognized by GCC. */ | |
e74cfd16 | 22346 | static const struct arm_option_cpu_value_table arm_fpus[] = |
c19d1205 ZW |
22347 | { |
22348 | {"softfpa", FPU_NONE}, | |
22349 | {"fpe", FPU_ARCH_FPE}, | |
22350 | {"fpe2", FPU_ARCH_FPE}, | |
22351 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
22352 | {"fpa", FPU_ARCH_FPA}, | |
22353 | {"fpa10", FPU_ARCH_FPA}, | |
22354 | {"fpa11", FPU_ARCH_FPA}, | |
22355 | {"arm7500fe", FPU_ARCH_FPA}, | |
22356 | {"softvfp", FPU_ARCH_VFP}, | |
22357 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
22358 | {"vfp", FPU_ARCH_VFP_V2}, | |
22359 | {"vfp9", FPU_ARCH_VFP_V2}, | |
b1cc4aeb | 22360 | {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */ |
c19d1205 ZW |
22361 | {"vfp10", FPU_ARCH_VFP_V2}, |
22362 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
22363 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
b1cc4aeb PB |
22364 | {"vfpv2", FPU_ARCH_VFP_V2}, |
22365 | {"vfpv3", FPU_ARCH_VFP_V3}, | |
62f3b8c8 | 22366 | {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16}, |
b1cc4aeb | 22367 | {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, |
62f3b8c8 PB |
22368 | {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16}, |
22369 | {"vfpv3xd", FPU_ARCH_VFP_V3xD}, | |
22370 | {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16}, | |
c19d1205 ZW |
22371 | {"arm1020t", FPU_ARCH_VFP_V1}, |
22372 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
22373 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
22374 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
22375 | {"maverick", FPU_ARCH_MAVERICK}, | |
5287ad62 | 22376 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
8e79c3df | 22377 | {"neon-fp16", FPU_ARCH_NEON_FP16}, |
62f3b8c8 PB |
22378 | {"vfpv4", FPU_ARCH_VFP_V4}, |
22379 | {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, | |
ada65aa3 | 22380 | {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, |
62f3b8c8 | 22381 | {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, |
e74cfd16 PB |
22382 | {NULL, ARM_ARCH_NONE} |
22383 | }; | |
22384 | ||
22385 | struct arm_option_value_table | |
22386 | { | |
22387 | char *name; | |
22388 | long value; | |
c19d1205 | 22389 | }; |
7ed4c4c5 | 22390 | |
e74cfd16 | 22391 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
22392 | { |
22393 | {"hard", ARM_FLOAT_ABI_HARD}, | |
22394 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
22395 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 22396 | {NULL, 0} |
c19d1205 | 22397 | }; |
7ed4c4c5 | 22398 | |
c19d1205 | 22399 | #ifdef OBJ_ELF |
3a4a14e9 | 22400 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 22401 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
22402 | { |
22403 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
22404 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 22405 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 22406 | {NULL, 0} |
c19d1205 ZW |
22407 | }; |
22408 | #endif | |
7ed4c4c5 | 22409 | |
c19d1205 ZW |
22410 | struct arm_long_option_table |
22411 | { | |
22412 | char * option; /* Substring to match. */ | |
22413 | char * help; /* Help information. */ | |
22414 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
22415 | char * deprecated; /* If non-null, print this message. */ | |
22416 | }; | |
7ed4c4c5 | 22417 | |
c921be7d | 22418 | static bfd_boolean |
e74cfd16 | 22419 | arm_parse_extension (char * str, const arm_feature_set **opt_p) |
7ed4c4c5 | 22420 | { |
21d799b5 NC |
22421 | arm_feature_set *ext_set = (arm_feature_set *) |
22422 | xmalloc (sizeof (arm_feature_set)); | |
e74cfd16 PB |
22423 | |
22424 | /* Copy the feature set, so that we can modify it. */ | |
22425 | *ext_set = **opt_p; | |
22426 | *opt_p = ext_set; | |
22427 | ||
c19d1205 | 22428 | while (str != NULL && *str != 0) |
7ed4c4c5 | 22429 | { |
e74cfd16 | 22430 | const struct arm_option_cpu_value_table * opt; |
c19d1205 ZW |
22431 | char * ext; |
22432 | int optlen; | |
7ed4c4c5 | 22433 | |
c19d1205 ZW |
22434 | if (*str != '+') |
22435 | { | |
22436 | as_bad (_("invalid architectural extension")); | |
c921be7d | 22437 | return FALSE; |
c19d1205 | 22438 | } |
7ed4c4c5 | 22439 | |
c19d1205 ZW |
22440 | str++; |
22441 | ext = strchr (str, '+'); | |
7ed4c4c5 | 22442 | |
c19d1205 ZW |
22443 | if (ext != NULL) |
22444 | optlen = ext - str; | |
22445 | else | |
22446 | optlen = strlen (str); | |
7ed4c4c5 | 22447 | |
c19d1205 ZW |
22448 | if (optlen == 0) |
22449 | { | |
22450 | as_bad (_("missing architectural extension")); | |
c921be7d | 22451 | return FALSE; |
c19d1205 | 22452 | } |
7ed4c4c5 | 22453 | |
c19d1205 ZW |
22454 | for (opt = arm_extensions; opt->name != NULL; opt++) |
22455 | if (strncmp (opt->name, str, optlen) == 0) | |
22456 | { | |
e74cfd16 | 22457 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); |
c19d1205 ZW |
22458 | break; |
22459 | } | |
7ed4c4c5 | 22460 | |
c19d1205 ZW |
22461 | if (opt->name == NULL) |
22462 | { | |
5f4273c7 | 22463 | as_bad (_("unknown architectural extension `%s'"), str); |
c921be7d | 22464 | return FALSE; |
c19d1205 | 22465 | } |
7ed4c4c5 | 22466 | |
c19d1205 ZW |
22467 | str = ext; |
22468 | }; | |
7ed4c4c5 | 22469 | |
c921be7d | 22470 | return TRUE; |
c19d1205 | 22471 | } |
7ed4c4c5 | 22472 | |
c921be7d | 22473 | static bfd_boolean |
c19d1205 | 22474 | arm_parse_cpu (char * str) |
7ed4c4c5 | 22475 | { |
e74cfd16 | 22476 | const struct arm_cpu_option_table * opt; |
c19d1205 ZW |
22477 | char * ext = strchr (str, '+'); |
22478 | int optlen; | |
7ed4c4c5 | 22479 | |
c19d1205 ZW |
22480 | if (ext != NULL) |
22481 | optlen = ext - str; | |
7ed4c4c5 | 22482 | else |
c19d1205 | 22483 | optlen = strlen (str); |
7ed4c4c5 | 22484 | |
c19d1205 | 22485 | if (optlen == 0) |
7ed4c4c5 | 22486 | { |
c19d1205 | 22487 | as_bad (_("missing cpu name `%s'"), str); |
c921be7d | 22488 | return FALSE; |
7ed4c4c5 NC |
22489 | } |
22490 | ||
c19d1205 ZW |
22491 | for (opt = arm_cpus; opt->name != NULL; opt++) |
22492 | if (strncmp (opt->name, str, optlen) == 0) | |
22493 | { | |
e74cfd16 PB |
22494 | mcpu_cpu_opt = &opt->value; |
22495 | mcpu_fpu_opt = &opt->default_fpu; | |
ee065d83 | 22496 | if (opt->canonical_name) |
5f4273c7 | 22497 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
22498 | else |
22499 | { | |
22500 | int i; | |
c921be7d | 22501 | |
ee065d83 PB |
22502 | for (i = 0; i < optlen; i++) |
22503 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
22504 | selected_cpu_name[i] = 0; | |
22505 | } | |
7ed4c4c5 | 22506 | |
c19d1205 ZW |
22507 | if (ext != NULL) |
22508 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 22509 | |
c921be7d | 22510 | return TRUE; |
c19d1205 | 22511 | } |
7ed4c4c5 | 22512 | |
c19d1205 | 22513 | as_bad (_("unknown cpu `%s'"), str); |
c921be7d | 22514 | return FALSE; |
7ed4c4c5 NC |
22515 | } |
22516 | ||
c921be7d | 22517 | static bfd_boolean |
c19d1205 | 22518 | arm_parse_arch (char * str) |
7ed4c4c5 | 22519 | { |
e74cfd16 | 22520 | const struct arm_arch_option_table *opt; |
c19d1205 ZW |
22521 | char *ext = strchr (str, '+'); |
22522 | int optlen; | |
7ed4c4c5 | 22523 | |
c19d1205 ZW |
22524 | if (ext != NULL) |
22525 | optlen = ext - str; | |
7ed4c4c5 | 22526 | else |
c19d1205 | 22527 | optlen = strlen (str); |
7ed4c4c5 | 22528 | |
c19d1205 | 22529 | if (optlen == 0) |
7ed4c4c5 | 22530 | { |
c19d1205 | 22531 | as_bad (_("missing architecture name `%s'"), str); |
c921be7d | 22532 | return FALSE; |
7ed4c4c5 NC |
22533 | } |
22534 | ||
c19d1205 ZW |
22535 | for (opt = arm_archs; opt->name != NULL; opt++) |
22536 | if (streq (opt->name, str)) | |
22537 | { | |
e74cfd16 PB |
22538 | march_cpu_opt = &opt->value; |
22539 | march_fpu_opt = &opt->default_fpu; | |
5f4273c7 | 22540 | strcpy (selected_cpu_name, opt->name); |
7ed4c4c5 | 22541 | |
c19d1205 ZW |
22542 | if (ext != NULL) |
22543 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 22544 | |
c921be7d | 22545 | return TRUE; |
c19d1205 ZW |
22546 | } |
22547 | ||
22548 | as_bad (_("unknown architecture `%s'\n"), str); | |
c921be7d | 22549 | return FALSE; |
7ed4c4c5 | 22550 | } |
eb043451 | 22551 | |
c921be7d | 22552 | static bfd_boolean |
c19d1205 ZW |
22553 | arm_parse_fpu (char * str) |
22554 | { | |
e74cfd16 | 22555 | const struct arm_option_cpu_value_table * opt; |
b99bd4ef | 22556 | |
c19d1205 ZW |
22557 | for (opt = arm_fpus; opt->name != NULL; opt++) |
22558 | if (streq (opt->name, str)) | |
22559 | { | |
e74cfd16 | 22560 | mfpu_opt = &opt->value; |
c921be7d | 22561 | return TRUE; |
c19d1205 | 22562 | } |
b99bd4ef | 22563 | |
c19d1205 | 22564 | as_bad (_("unknown floating point format `%s'\n"), str); |
c921be7d | 22565 | return FALSE; |
c19d1205 ZW |
22566 | } |
22567 | ||
c921be7d | 22568 | static bfd_boolean |
c19d1205 | 22569 | arm_parse_float_abi (char * str) |
b99bd4ef | 22570 | { |
e74cfd16 | 22571 | const struct arm_option_value_table * opt; |
b99bd4ef | 22572 | |
c19d1205 ZW |
22573 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
22574 | if (streq (opt->name, str)) | |
22575 | { | |
22576 | mfloat_abi_opt = opt->value; | |
c921be7d | 22577 | return TRUE; |
c19d1205 | 22578 | } |
cc8a6dd0 | 22579 | |
c19d1205 | 22580 | as_bad (_("unknown floating point abi `%s'\n"), str); |
c921be7d | 22581 | return FALSE; |
c19d1205 | 22582 | } |
b99bd4ef | 22583 | |
c19d1205 | 22584 | #ifdef OBJ_ELF |
c921be7d | 22585 | static bfd_boolean |
c19d1205 ZW |
22586 | arm_parse_eabi (char * str) |
22587 | { | |
e74cfd16 | 22588 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 22589 | |
c19d1205 ZW |
22590 | for (opt = arm_eabis; opt->name != NULL; opt++) |
22591 | if (streq (opt->name, str)) | |
22592 | { | |
22593 | meabi_flags = opt->value; | |
c921be7d | 22594 | return TRUE; |
c19d1205 ZW |
22595 | } |
22596 | as_bad (_("unknown EABI `%s'\n"), str); | |
c921be7d | 22597 | return FALSE; |
c19d1205 ZW |
22598 | } |
22599 | #endif | |
cc8a6dd0 | 22600 | |
c921be7d | 22601 | static bfd_boolean |
e07e6e58 NC |
22602 | arm_parse_it_mode (char * str) |
22603 | { | |
c921be7d | 22604 | bfd_boolean ret = TRUE; |
e07e6e58 NC |
22605 | |
22606 | if (streq ("arm", str)) | |
22607 | implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
22608 | else if (streq ("thumb", str)) | |
22609 | implicit_it_mode = IMPLICIT_IT_MODE_THUMB; | |
22610 | else if (streq ("always", str)) | |
22611 | implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; | |
22612 | else if (streq ("never", str)) | |
22613 | implicit_it_mode = IMPLICIT_IT_MODE_NEVER; | |
22614 | else | |
22615 | { | |
22616 | as_bad (_("unknown implicit IT mode `%s', should be "\ | |
22617 | "arm, thumb, always, or never."), str); | |
c921be7d | 22618 | ret = FALSE; |
e07e6e58 NC |
22619 | } |
22620 | ||
22621 | return ret; | |
22622 | } | |
22623 | ||
c19d1205 ZW |
22624 | struct arm_long_option_table arm_long_opts[] = |
22625 | { | |
22626 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
22627 | arm_parse_cpu, NULL}, | |
22628 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
22629 | arm_parse_arch, NULL}, | |
22630 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
22631 | arm_parse_fpu, NULL}, | |
22632 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
22633 | arm_parse_float_abi, NULL}, | |
22634 | #ifdef OBJ_ELF | |
7fac0536 | 22635 | {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), |
c19d1205 ZW |
22636 | arm_parse_eabi, NULL}, |
22637 | #endif | |
e07e6e58 NC |
22638 | {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), |
22639 | arm_parse_it_mode, NULL}, | |
c19d1205 ZW |
22640 | {NULL, NULL, 0, NULL} |
22641 | }; | |
cc8a6dd0 | 22642 | |
c19d1205 ZW |
22643 | int |
22644 | md_parse_option (int c, char * arg) | |
22645 | { | |
22646 | struct arm_option_table *opt; | |
e74cfd16 | 22647 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 22648 | struct arm_long_option_table *lopt; |
b99bd4ef | 22649 | |
c19d1205 | 22650 | switch (c) |
b99bd4ef | 22651 | { |
c19d1205 ZW |
22652 | #ifdef OPTION_EB |
22653 | case OPTION_EB: | |
22654 | target_big_endian = 1; | |
22655 | break; | |
22656 | #endif | |
cc8a6dd0 | 22657 | |
c19d1205 ZW |
22658 | #ifdef OPTION_EL |
22659 | case OPTION_EL: | |
22660 | target_big_endian = 0; | |
22661 | break; | |
22662 | #endif | |
b99bd4ef | 22663 | |
845b51d6 PB |
22664 | case OPTION_FIX_V4BX: |
22665 | fix_v4bx = TRUE; | |
22666 | break; | |
22667 | ||
c19d1205 ZW |
22668 | case 'a': |
22669 | /* Listing option. Just ignore these, we don't support additional | |
22670 | ones. */ | |
22671 | return 0; | |
b99bd4ef | 22672 | |
c19d1205 ZW |
22673 | default: |
22674 | for (opt = arm_opts; opt->option != NULL; opt++) | |
22675 | { | |
22676 | if (c == opt->option[0] | |
22677 | && ((arg == NULL && opt->option[1] == 0) | |
22678 | || streq (arg, opt->option + 1))) | |
22679 | { | |
c19d1205 | 22680 | /* If the option is deprecated, tell the user. */ |
278df34e | 22681 | if (warn_on_deprecated && opt->deprecated != NULL) |
c19d1205 ZW |
22682 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
22683 | arg ? arg : "", _(opt->deprecated)); | |
b99bd4ef | 22684 | |
c19d1205 ZW |
22685 | if (opt->var != NULL) |
22686 | *opt->var = opt->value; | |
cc8a6dd0 | 22687 | |
c19d1205 ZW |
22688 | return 1; |
22689 | } | |
22690 | } | |
b99bd4ef | 22691 | |
e74cfd16 PB |
22692 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
22693 | { | |
22694 | if (c == fopt->option[0] | |
22695 | && ((arg == NULL && fopt->option[1] == 0) | |
22696 | || streq (arg, fopt->option + 1))) | |
22697 | { | |
e74cfd16 | 22698 | /* If the option is deprecated, tell the user. */ |
278df34e | 22699 | if (warn_on_deprecated && fopt->deprecated != NULL) |
e74cfd16 PB |
22700 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
22701 | arg ? arg : "", _(fopt->deprecated)); | |
e74cfd16 PB |
22702 | |
22703 | if (fopt->var != NULL) | |
22704 | *fopt->var = &fopt->value; | |
22705 | ||
22706 | return 1; | |
22707 | } | |
22708 | } | |
22709 | ||
c19d1205 ZW |
22710 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
22711 | { | |
22712 | /* These options are expected to have an argument. */ | |
22713 | if (c == lopt->option[0] | |
22714 | && arg != NULL | |
22715 | && strncmp (arg, lopt->option + 1, | |
22716 | strlen (lopt->option + 1)) == 0) | |
22717 | { | |
c19d1205 | 22718 | /* If the option is deprecated, tell the user. */ |
278df34e | 22719 | if (warn_on_deprecated && lopt->deprecated != NULL) |
c19d1205 ZW |
22720 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, |
22721 | _(lopt->deprecated)); | |
b99bd4ef | 22722 | |
c19d1205 ZW |
22723 | /* Call the sup-option parser. */ |
22724 | return lopt->func (arg + strlen (lopt->option) - 1); | |
22725 | } | |
22726 | } | |
a737bd4d | 22727 | |
c19d1205 ZW |
22728 | return 0; |
22729 | } | |
a394c00f | 22730 | |
c19d1205 ZW |
22731 | return 1; |
22732 | } | |
a394c00f | 22733 | |
c19d1205 ZW |
22734 | void |
22735 | md_show_usage (FILE * fp) | |
a394c00f | 22736 | { |
c19d1205 ZW |
22737 | struct arm_option_table *opt; |
22738 | struct arm_long_option_table *lopt; | |
a394c00f | 22739 | |
c19d1205 | 22740 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 22741 | |
c19d1205 ZW |
22742 | for (opt = arm_opts; opt->option != NULL; opt++) |
22743 | if (opt->help != NULL) | |
22744 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 22745 | |
c19d1205 ZW |
22746 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
22747 | if (lopt->help != NULL) | |
22748 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 22749 | |
c19d1205 ZW |
22750 | #ifdef OPTION_EB |
22751 | fprintf (fp, _("\ | |
22752 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
22753 | #endif |
22754 | ||
c19d1205 ZW |
22755 | #ifdef OPTION_EL |
22756 | fprintf (fp, _("\ | |
22757 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 22758 | #endif |
845b51d6 PB |
22759 | |
22760 | fprintf (fp, _("\ | |
22761 | --fix-v4bx Allow BX in ARMv4 code\n")); | |
c19d1205 | 22762 | } |
ee065d83 PB |
22763 | |
22764 | ||
22765 | #ifdef OBJ_ELF | |
62b3e311 PB |
22766 | typedef struct |
22767 | { | |
22768 | int val; | |
22769 | arm_feature_set flags; | |
22770 | } cpu_arch_ver_table; | |
22771 | ||
22772 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted | |
22773 | least features first. */ | |
22774 | static const cpu_arch_ver_table cpu_arch_ver[] = | |
22775 | { | |
22776 | {1, ARM_ARCH_V4}, | |
22777 | {2, ARM_ARCH_V4T}, | |
22778 | {3, ARM_ARCH_V5}, | |
ee3c0378 | 22779 | {3, ARM_ARCH_V5T}, |
62b3e311 PB |
22780 | {4, ARM_ARCH_V5TE}, |
22781 | {5, ARM_ARCH_V5TEJ}, | |
22782 | {6, ARM_ARCH_V6}, | |
22783 | {7, ARM_ARCH_V6Z}, | |
7e806470 | 22784 | {9, ARM_ARCH_V6K}, |
91e22acd | 22785 | {11, ARM_ARCH_V6M}, |
7e806470 | 22786 | {8, ARM_ARCH_V6T2}, |
62b3e311 PB |
22787 | {10, ARM_ARCH_V7A}, |
22788 | {10, ARM_ARCH_V7R}, | |
22789 | {10, ARM_ARCH_V7M}, | |
22790 | {0, ARM_ARCH_NONE} | |
22791 | }; | |
22792 | ||
ee3c0378 AS |
22793 | /* Set an attribute if it has not already been set by the user. */ |
22794 | static void | |
22795 | aeabi_set_attribute_int (int tag, int value) | |
22796 | { | |
22797 | if (tag < 1 | |
22798 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
22799 | || !attributes_set_explicitly[tag]) | |
22800 | bfd_elf_add_proc_attr_int (stdoutput, tag, value); | |
22801 | } | |
22802 | ||
22803 | static void | |
22804 | aeabi_set_attribute_string (int tag, const char *value) | |
22805 | { | |
22806 | if (tag < 1 | |
22807 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
22808 | || !attributes_set_explicitly[tag]) | |
22809 | bfd_elf_add_proc_attr_string (stdoutput, tag, value); | |
22810 | } | |
22811 | ||
ee065d83 PB |
22812 | /* Set the public EABI object attributes. */ |
22813 | static void | |
22814 | aeabi_set_public_attributes (void) | |
22815 | { | |
22816 | int arch; | |
e74cfd16 | 22817 | arm_feature_set flags; |
62b3e311 PB |
22818 | arm_feature_set tmp; |
22819 | const cpu_arch_ver_table *p; | |
ee065d83 PB |
22820 | |
22821 | /* Choose the architecture based on the capabilities of the requested cpu | |
22822 | (if any) and/or the instructions actually used. */ | |
e74cfd16 PB |
22823 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); |
22824 | ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); | |
22825 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); | |
7a1d4c38 PB |
22826 | /*Allow the user to override the reported architecture. */ |
22827 | if (object_arch) | |
22828 | { | |
22829 | ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); | |
22830 | ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); | |
22831 | } | |
22832 | ||
62b3e311 PB |
22833 | tmp = flags; |
22834 | arch = 0; | |
22835 | for (p = cpu_arch_ver; p->val; p++) | |
22836 | { | |
22837 | if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) | |
22838 | { | |
22839 | arch = p->val; | |
22840 | ARM_CLEAR_FEATURE (tmp, tmp, p->flags); | |
22841 | } | |
22842 | } | |
ee065d83 | 22843 | |
9e3c6df6 PB |
22844 | /* The table lookup above finds the last architecture to contribute |
22845 | a new feature. Unfortunately, Tag13 is a subset of the union of | |
22846 | v6T2 and v7-M, so it is never seen as contributing a new feature. | |
22847 | We can not search for the last entry which is entirely used, | |
22848 | because if no CPU is specified we build up only those flags | |
22849 | actually used. Perhaps we should separate out the specified | |
22850 | and implicit cases. Avoid taking this path for -march=all by | |
22851 | checking for contradictory v7-A / v7-M features. */ | |
22852 | if (arch == 10 | |
22853 | && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a) | |
22854 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m) | |
22855 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp)) | |
22856 | arch = 13; | |
22857 | ||
ee065d83 PB |
22858 | /* Tag_CPU_name. */ |
22859 | if (selected_cpu_name[0]) | |
22860 | { | |
91d6fa6a | 22861 | char *q; |
ee065d83 | 22862 | |
91d6fa6a NC |
22863 | q = selected_cpu_name; |
22864 | if (strncmp (q, "armv", 4) == 0) | |
ee065d83 PB |
22865 | { |
22866 | int i; | |
5f4273c7 | 22867 | |
91d6fa6a NC |
22868 | q += 4; |
22869 | for (i = 0; q[i]; i++) | |
22870 | q[i] = TOUPPER (q[i]); | |
ee065d83 | 22871 | } |
91d6fa6a | 22872 | aeabi_set_attribute_string (Tag_CPU_name, q); |
ee065d83 | 22873 | } |
62f3b8c8 | 22874 | |
ee065d83 | 22875 | /* Tag_CPU_arch. */ |
ee3c0378 | 22876 | aeabi_set_attribute_int (Tag_CPU_arch, arch); |
62f3b8c8 | 22877 | |
62b3e311 PB |
22878 | /* Tag_CPU_arch_profile. */ |
22879 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) | |
ee3c0378 | 22880 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A'); |
62b3e311 | 22881 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) |
ee3c0378 | 22882 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R'); |
7e806470 | 22883 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m)) |
ee3c0378 | 22884 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M'); |
62f3b8c8 | 22885 | |
ee065d83 | 22886 | /* Tag_ARM_ISA_use. */ |
ee3c0378 AS |
22887 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) |
22888 | || arch == 0) | |
22889 | aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); | |
62f3b8c8 | 22890 | |
ee065d83 | 22891 | /* Tag_THUMB_ISA_use. */ |
ee3c0378 AS |
22892 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) |
22893 | || arch == 0) | |
22894 | aeabi_set_attribute_int (Tag_THUMB_ISA_use, | |
22895 | ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1); | |
62f3b8c8 | 22896 | |
ee065d83 | 22897 | /* Tag_VFP_arch. */ |
62f3b8c8 PB |
22898 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) |
22899 | aeabi_set_attribute_int (Tag_VFP_arch, | |
22900 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
22901 | ? 5 : 6); | |
22902 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) | |
ee3c0378 | 22903 | aeabi_set_attribute_int (Tag_VFP_arch, 3); |
ada65aa3 | 22904 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) |
ee3c0378 AS |
22905 | aeabi_set_attribute_int (Tag_VFP_arch, 4); |
22906 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) | |
22907 | aeabi_set_attribute_int (Tag_VFP_arch, 2); | |
22908 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) | |
22909 | || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) | |
22910 | aeabi_set_attribute_int (Tag_VFP_arch, 1); | |
62f3b8c8 | 22911 | |
4547cb56 NC |
22912 | /* Tag_ABI_HardFP_use. */ |
22913 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd) | |
22914 | && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)) | |
22915 | aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1); | |
22916 | ||
ee065d83 | 22917 | /* Tag_WMMX_arch. */ |
ee3c0378 AS |
22918 | if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) |
22919 | aeabi_set_attribute_int (Tag_WMMX_arch, 2); | |
22920 | else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) | |
22921 | aeabi_set_attribute_int (Tag_WMMX_arch, 1); | |
62f3b8c8 | 22922 | |
ee3c0378 | 22923 | /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ |
8e79c3df | 22924 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) |
62f3b8c8 PB |
22925 | aeabi_set_attribute_int |
22926 | (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma) | |
22927 | ? 2 : 1)); | |
22928 | ||
ee3c0378 | 22929 | /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ |
62f3b8c8 | 22930 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16)) |
ee3c0378 | 22931 | aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); |
4547cb56 NC |
22932 | |
22933 | /* Tag_DIV_use. */ | |
22934 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div)) | |
22935 | aeabi_set_attribute_int (Tag_DIV_use, 0); | |
22936 | /* Fill this in when gas supports v7a sdiv/udiv. | |
22937 | else if (... v7a with div extension used ...) | |
22938 | aeabi_set_attribute_int (Tag_DIV_use, 2); */ | |
22939 | else | |
22940 | aeabi_set_attribute_int (Tag_DIV_use, 1); | |
ee065d83 PB |
22941 | } |
22942 | ||
104d59d1 | 22943 | /* Add the default contents for the .ARM.attributes section. */ |
ee065d83 PB |
22944 | void |
22945 | arm_md_end (void) | |
22946 | { | |
ee065d83 PB |
22947 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
22948 | return; | |
22949 | ||
22950 | aeabi_set_public_attributes (); | |
ee065d83 | 22951 | } |
8463be01 | 22952 | #endif /* OBJ_ELF */ |
ee065d83 PB |
22953 | |
22954 | ||
22955 | /* Parse a .cpu directive. */ | |
22956 | ||
22957 | static void | |
22958 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
22959 | { | |
e74cfd16 | 22960 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
22961 | char *name; |
22962 | char saved_char; | |
22963 | ||
22964 | name = input_line_pointer; | |
5f4273c7 | 22965 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
22966 | input_line_pointer++; |
22967 | saved_char = *input_line_pointer; | |
22968 | *input_line_pointer = 0; | |
22969 | ||
22970 | /* Skip the first "all" entry. */ | |
22971 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
22972 | if (streq (opt->name, name)) | |
22973 | { | |
e74cfd16 PB |
22974 | mcpu_cpu_opt = &opt->value; |
22975 | selected_cpu = opt->value; | |
ee065d83 | 22976 | if (opt->canonical_name) |
5f4273c7 | 22977 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
22978 | else |
22979 | { | |
22980 | int i; | |
22981 | for (i = 0; opt->name[i]; i++) | |
22982 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
22983 | selected_cpu_name[i] = 0; | |
22984 | } | |
e74cfd16 | 22985 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
22986 | *input_line_pointer = saved_char; |
22987 | demand_empty_rest_of_line (); | |
22988 | return; | |
22989 | } | |
22990 | as_bad (_("unknown cpu `%s'"), name); | |
22991 | *input_line_pointer = saved_char; | |
22992 | ignore_rest_of_line (); | |
22993 | } | |
22994 | ||
22995 | ||
22996 | /* Parse a .arch directive. */ | |
22997 | ||
22998 | static void | |
22999 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
23000 | { | |
e74cfd16 | 23001 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
23002 | char saved_char; |
23003 | char *name; | |
23004 | ||
23005 | name = input_line_pointer; | |
5f4273c7 | 23006 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
23007 | input_line_pointer++; |
23008 | saved_char = *input_line_pointer; | |
23009 | *input_line_pointer = 0; | |
23010 | ||
23011 | /* Skip the first "all" entry. */ | |
23012 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
23013 | if (streq (opt->name, name)) | |
23014 | { | |
e74cfd16 PB |
23015 | mcpu_cpu_opt = &opt->value; |
23016 | selected_cpu = opt->value; | |
5f4273c7 | 23017 | strcpy (selected_cpu_name, opt->name); |
e74cfd16 | 23018 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
23019 | *input_line_pointer = saved_char; |
23020 | demand_empty_rest_of_line (); | |
23021 | return; | |
23022 | } | |
23023 | ||
23024 | as_bad (_("unknown architecture `%s'\n"), name); | |
23025 | *input_line_pointer = saved_char; | |
23026 | ignore_rest_of_line (); | |
23027 | } | |
23028 | ||
23029 | ||
7a1d4c38 PB |
23030 | /* Parse a .object_arch directive. */ |
23031 | ||
23032 | static void | |
23033 | s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) | |
23034 | { | |
23035 | const struct arm_arch_option_table *opt; | |
23036 | char saved_char; | |
23037 | char *name; | |
23038 | ||
23039 | name = input_line_pointer; | |
5f4273c7 | 23040 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
7a1d4c38 PB |
23041 | input_line_pointer++; |
23042 | saved_char = *input_line_pointer; | |
23043 | *input_line_pointer = 0; | |
23044 | ||
23045 | /* Skip the first "all" entry. */ | |
23046 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
23047 | if (streq (opt->name, name)) | |
23048 | { | |
23049 | object_arch = &opt->value; | |
23050 | *input_line_pointer = saved_char; | |
23051 | demand_empty_rest_of_line (); | |
23052 | return; | |
23053 | } | |
23054 | ||
23055 | as_bad (_("unknown architecture `%s'\n"), name); | |
23056 | *input_line_pointer = saved_char; | |
23057 | ignore_rest_of_line (); | |
23058 | } | |
23059 | ||
ee065d83 PB |
23060 | /* Parse a .fpu directive. */ |
23061 | ||
23062 | static void | |
23063 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
23064 | { | |
e74cfd16 | 23065 | const struct arm_option_cpu_value_table *opt; |
ee065d83 PB |
23066 | char saved_char; |
23067 | char *name; | |
23068 | ||
23069 | name = input_line_pointer; | |
5f4273c7 | 23070 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
23071 | input_line_pointer++; |
23072 | saved_char = *input_line_pointer; | |
23073 | *input_line_pointer = 0; | |
5f4273c7 | 23074 | |
ee065d83 PB |
23075 | for (opt = arm_fpus; opt->name != NULL; opt++) |
23076 | if (streq (opt->name, name)) | |
23077 | { | |
e74cfd16 PB |
23078 | mfpu_opt = &opt->value; |
23079 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
ee065d83 PB |
23080 | *input_line_pointer = saved_char; |
23081 | demand_empty_rest_of_line (); | |
23082 | return; | |
23083 | } | |
23084 | ||
23085 | as_bad (_("unknown floating point format `%s'\n"), name); | |
23086 | *input_line_pointer = saved_char; | |
23087 | ignore_rest_of_line (); | |
23088 | } | |
ee065d83 | 23089 | |
794ba86a | 23090 | /* Copy symbol information. */ |
f31fef98 | 23091 | |
794ba86a DJ |
23092 | void |
23093 | arm_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
23094 | { | |
23095 | ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); | |
23096 | } | |
e04befd0 | 23097 | |
f31fef98 | 23098 | #ifdef OBJ_ELF |
e04befd0 AS |
23099 | /* Given a symbolic attribute NAME, return the proper integer value. |
23100 | Returns -1 if the attribute is not known. */ | |
f31fef98 | 23101 | |
e04befd0 AS |
23102 | int |
23103 | arm_convert_symbolic_attribute (const char *name) | |
23104 | { | |
f31fef98 NC |
23105 | static const struct |
23106 | { | |
23107 | const char * name; | |
23108 | const int tag; | |
23109 | } | |
23110 | attribute_table[] = | |
23111 | { | |
23112 | /* When you modify this table you should | |
23113 | also modify the list in doc/c-arm.texi. */ | |
e04befd0 | 23114 | #define T(tag) {#tag, tag} |
f31fef98 NC |
23115 | T (Tag_CPU_raw_name), |
23116 | T (Tag_CPU_name), | |
23117 | T (Tag_CPU_arch), | |
23118 | T (Tag_CPU_arch_profile), | |
23119 | T (Tag_ARM_ISA_use), | |
23120 | T (Tag_THUMB_ISA_use), | |
75375b3e | 23121 | T (Tag_FP_arch), |
f31fef98 NC |
23122 | T (Tag_VFP_arch), |
23123 | T (Tag_WMMX_arch), | |
23124 | T (Tag_Advanced_SIMD_arch), | |
23125 | T (Tag_PCS_config), | |
23126 | T (Tag_ABI_PCS_R9_use), | |
23127 | T (Tag_ABI_PCS_RW_data), | |
23128 | T (Tag_ABI_PCS_RO_data), | |
23129 | T (Tag_ABI_PCS_GOT_use), | |
23130 | T (Tag_ABI_PCS_wchar_t), | |
23131 | T (Tag_ABI_FP_rounding), | |
23132 | T (Tag_ABI_FP_denormal), | |
23133 | T (Tag_ABI_FP_exceptions), | |
23134 | T (Tag_ABI_FP_user_exceptions), | |
23135 | T (Tag_ABI_FP_number_model), | |
75375b3e | 23136 | T (Tag_ABI_align_needed), |
f31fef98 | 23137 | T (Tag_ABI_align8_needed), |
75375b3e | 23138 | T (Tag_ABI_align_preserved), |
f31fef98 NC |
23139 | T (Tag_ABI_align8_preserved), |
23140 | T (Tag_ABI_enum_size), | |
23141 | T (Tag_ABI_HardFP_use), | |
23142 | T (Tag_ABI_VFP_args), | |
23143 | T (Tag_ABI_WMMX_args), | |
23144 | T (Tag_ABI_optimization_goals), | |
23145 | T (Tag_ABI_FP_optimization_goals), | |
23146 | T (Tag_compatibility), | |
23147 | T (Tag_CPU_unaligned_access), | |
75375b3e | 23148 | T (Tag_FP_HP_extension), |
f31fef98 NC |
23149 | T (Tag_VFP_HP_extension), |
23150 | T (Tag_ABI_FP_16bit_format), | |
cd21e546 MGD |
23151 | T (Tag_MPextension_use), |
23152 | T (Tag_DIV_use), | |
f31fef98 NC |
23153 | T (Tag_nodefaults), |
23154 | T (Tag_also_compatible_with), | |
23155 | T (Tag_conformance), | |
23156 | T (Tag_T2EE_use), | |
23157 | T (Tag_Virtualization_use), | |
cd21e546 | 23158 | /* We deliberately do not include Tag_MPextension_use_legacy. */ |
e04befd0 | 23159 | #undef T |
f31fef98 | 23160 | }; |
e04befd0 AS |
23161 | unsigned int i; |
23162 | ||
23163 | if (name == NULL) | |
23164 | return -1; | |
23165 | ||
f31fef98 | 23166 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
c921be7d | 23167 | if (streq (name, attribute_table[i].name)) |
e04befd0 AS |
23168 | return attribute_table[i].tag; |
23169 | ||
23170 | return -1; | |
23171 | } | |
267bf995 RR |
23172 | |
23173 | ||
23174 | /* Apply sym value for relocations only in the case that | |
23175 | they are for local symbols and you have the respective | |
23176 | architectural feature for blx and simple switches. */ | |
23177 | int | |
23178 | arm_apply_sym_value (struct fix * fixP) | |
23179 | { | |
23180 | if (fixP->fx_addsy | |
23181 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
23182 | && !S_IS_EXTERNAL (fixP->fx_addsy)) | |
23183 | { | |
23184 | switch (fixP->fx_r_type) | |
23185 | { | |
23186 | case BFD_RELOC_ARM_PCREL_BLX: | |
23187 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
23188 | if (ARM_IS_FUNC (fixP->fx_addsy)) | |
23189 | return 1; | |
23190 | break; | |
23191 | ||
23192 | case BFD_RELOC_ARM_PCREL_CALL: | |
23193 | case BFD_RELOC_THUMB_PCREL_BLX: | |
23194 | if (THUMB_IS_FUNC (fixP->fx_addsy)) | |
23195 | return 1; | |
23196 | break; | |
23197 | ||
23198 | default: | |
23199 | break; | |
23200 | } | |
23201 | ||
23202 | } | |
23203 | return 0; | |
23204 | } | |
f31fef98 | 23205 | #endif /* OBJ_ELF */ |