Commit | Line | Data |
---|---|---|
b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
f17c130b AM |
2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
3 | 2004, 2005 | |
b99bd4ef NC |
4 | Free Software Foundation, Inc. |
5 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) | |
6 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 7 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
8 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
9 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
10 | |
11 | This file is part of GAS, the GNU Assembler. | |
12 | ||
13 | GAS is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
15 | the Free Software Foundation; either version 2, or (at your option) | |
16 | any later version. | |
17 | ||
18 | GAS is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
21 | GNU General Public License for more details. |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
25 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
26 | 02110-1301, USA. */ | |
b99bd4ef | 27 | |
b99bd4ef | 28 | #include <string.h> |
c19d1205 | 29 | #define NO_RELOC 0 |
b99bd4ef | 30 | #include "as.h" |
3882b010 | 31 | #include "safe-ctype.h" |
b99bd4ef NC |
32 | |
33 | /* Need TARGET_CPU. */ | |
34 | #include "config.h" | |
35 | #include "subsegs.h" | |
36 | #include "obstack.h" | |
37 | #include "symbols.h" | |
38 | #include "listing.h" | |
39 | ||
f263249b RE |
40 | #include "opcode/arm.h" |
41 | ||
b99bd4ef NC |
42 | #ifdef OBJ_ELF |
43 | #include "elf/arm.h" | |
44 | #include "dwarf2dbg.h" | |
a394c00f | 45 | #include "dw2gencfi.h" |
b99bd4ef NC |
46 | #endif |
47 | ||
7ed4c4c5 | 48 | /* XXX Set this to 1 after the next binutils release. */ |
03b1477f RE |
49 | #define WARN_DEPRECATED 0 |
50 | ||
7ed4c4c5 NC |
51 | #ifdef OBJ_ELF |
52 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
53 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
54 | ||
55 | /* This structure holds the unwinding state. */ | |
56 | ||
57 | static struct | |
58 | { | |
c19d1205 ZW |
59 | symbolS * proc_start; |
60 | symbolS * table_entry; | |
61 | symbolS * personality_routine; | |
62 | int personality_index; | |
7ed4c4c5 | 63 | /* The segment containing the function. */ |
c19d1205 ZW |
64 | segT saved_seg; |
65 | subsegT saved_subseg; | |
7ed4c4c5 NC |
66 | /* Opcodes generated from this function. */ |
67 | unsigned char * opcodes; | |
c19d1205 ZW |
68 | int opcode_count; |
69 | int opcode_alloc; | |
7ed4c4c5 | 70 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 71 | offsetT frame_size; |
7ed4c4c5 NC |
72 | /* We don't add stack adjustment opcodes immediately so that we can merge |
73 | multiple adjustments. We can also omit the final adjustment | |
74 | when using a frame pointer. */ | |
c19d1205 | 75 | offsetT pending_offset; |
7ed4c4c5 | 76 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
77 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
78 | offsetT fp_offset; | |
79 | int fp_reg; | |
7ed4c4c5 | 80 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 81 | unsigned fp_used:1; |
7ed4c4c5 | 82 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 83 | unsigned sp_restored:1; |
7ed4c4c5 NC |
84 | } unwind; |
85 | ||
84798bd6 JB |
86 | /* Bit N indicates that an R_ARM_NONE relocation has been output for |
87 | __aeabi_unwind_cpp_prN already if set. This enables dependencies to be | |
88 | emitted only once per section, to save unnecessary bloat. */ | |
89 | static unsigned int marked_pr_dependency = 0; | |
90 | ||
7ed4c4c5 NC |
91 | #endif /* OBJ_ELF */ |
92 | ||
33a392fb PB |
93 | enum arm_float_abi |
94 | { | |
95 | ARM_FLOAT_ABI_HARD, | |
96 | ARM_FLOAT_ABI_SOFTFP, | |
97 | ARM_FLOAT_ABI_SOFT | |
98 | }; | |
99 | ||
c19d1205 | 100 | /* Types of processor to assemble for. */ |
b99bd4ef NC |
101 | #ifndef CPU_DEFAULT |
102 | #if defined __XSCALE__ | |
e74cfd16 | 103 | #define CPU_DEFAULT ARM_ARCH_XSCALE |
b99bd4ef NC |
104 | #else |
105 | #if defined __thumb__ | |
e74cfd16 | 106 | #define CPU_DEFAULT ARM_ARCH_V5T |
b99bd4ef NC |
107 | #endif |
108 | #endif | |
109 | #endif | |
110 | ||
111 | #ifndef FPU_DEFAULT | |
c820d418 MM |
112 | # ifdef TE_LINUX |
113 | # define FPU_DEFAULT FPU_ARCH_FPA | |
114 | # elif defined (TE_NetBSD) | |
115 | # ifdef OBJ_ELF | |
116 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
117 | # else | |
118 | /* Legacy a.out format. */ | |
119 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
120 | # endif | |
4e7fd91e PB |
121 | # elif defined (TE_VXWORKS) |
122 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
123 | # else |
124 | /* For backwards compatibility, default to FPA. */ | |
125 | # define FPU_DEFAULT FPU_ARCH_FPA | |
126 | # endif | |
127 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 128 | |
c19d1205 | 129 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 130 | |
e74cfd16 PB |
131 | static arm_feature_set cpu_variant; |
132 | static arm_feature_set arm_arch_used; | |
133 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 134 | |
b99bd4ef | 135 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
136 | static int uses_apcs_26 = FALSE; |
137 | static int atpcs = FALSE; | |
b34976b6 AM |
138 | static int support_interwork = FALSE; |
139 | static int uses_apcs_float = FALSE; | |
c19d1205 | 140 | static int pic_code = FALSE; |
03b1477f RE |
141 | |
142 | /* Variables that we set while parsing command-line options. Once all | |
143 | options have been read we re-process these values to set the real | |
144 | assembly flags. */ | |
e74cfd16 PB |
145 | static const arm_feature_set *legacy_cpu = NULL; |
146 | static const arm_feature_set *legacy_fpu = NULL; | |
147 | ||
148 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
149 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
150 | static const arm_feature_set *march_cpu_opt = NULL; | |
151 | static const arm_feature_set *march_fpu_opt = NULL; | |
152 | static const arm_feature_set *mfpu_opt = NULL; | |
153 | ||
154 | /* Constants for known architecture features. */ | |
155 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
156 | static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; | |
157 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; | |
158 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; | |
159 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
160 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; | |
161 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; | |
162 | ||
163 | #ifdef CPU_DEFAULT | |
164 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
165 | #endif | |
166 | ||
167 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); | |
168 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); | |
169 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); | |
170 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); | |
171 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); | |
172 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); | |
173 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); | |
174 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); | |
175 | static const arm_feature_set arm_ext_v4t_5 = | |
176 | ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); | |
177 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); | |
178 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); | |
179 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); | |
180 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); | |
181 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); | |
182 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); | |
183 | static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0); | |
184 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); | |
185 | ||
186 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
187 | static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); | |
188 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; | |
189 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
190 | ||
191 | static const arm_feature_set arm_cext_iwmmxt = | |
192 | ARM_FEATURE (0, ARM_CEXT_IWMMXT); | |
193 | static const arm_feature_set arm_cext_xscale = | |
194 | ARM_FEATURE (0, ARM_CEXT_XSCALE); | |
195 | static const arm_feature_set arm_cext_maverick = | |
196 | ARM_FEATURE (0, ARM_CEXT_MAVERICK); | |
197 | static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); | |
198 | static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); | |
199 | static const arm_feature_set fpu_vfp_ext_v1xd = | |
200 | ARM_FEATURE (0, FPU_VFP_EXT_V1xD); | |
201 | static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); | |
202 | static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); | |
203 | ||
33a392fb | 204 | static int mfloat_abi_opt = -1; |
e74cfd16 PB |
205 | /* Record user cpu selection for object attributes. */ |
206 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; | |
ee065d83 PB |
207 | /* Must be long enough to hold any of the names in arm_cpus. */ |
208 | static char selected_cpu_name[16]; | |
7cc69913 | 209 | #ifdef OBJ_ELF |
deeaaff8 DJ |
210 | # ifdef EABI_DEFAULT |
211 | static int meabi_flags = EABI_DEFAULT; | |
212 | # else | |
d507cf36 | 213 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 214 | # endif |
7cc69913 | 215 | #endif |
b99bd4ef | 216 | |
b99bd4ef | 217 | #ifdef OBJ_ELF |
c19d1205 | 218 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
219 | symbolS * GOT_symbol; |
220 | #endif | |
221 | ||
b99bd4ef NC |
222 | /* 0: assemble for ARM, |
223 | 1: assemble for Thumb, | |
224 | 2: assemble for Thumb even though target CPU does not support thumb | |
225 | instructions. */ | |
226 | static int thumb_mode = 0; | |
227 | ||
c19d1205 ZW |
228 | /* If unified_syntax is true, we are processing the new unified |
229 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
230 | ||
231 | - Immediate operands do not require a # prefix. | |
232 | - Conditional affixes always appear at the end of the | |
233 | instruction. (For backward compatibility, those instructions | |
234 | that formerly had them in the middle, continue to accept them | |
235 | there.) | |
236 | - The IT instruction may appear, and if it does is validated | |
237 | against subsequent conditional affixes. It does not generate | |
238 | machine code. | |
239 | ||
240 | Important differences from the old Thumb mode: | |
241 | ||
242 | - Immediate operands do not require a # prefix. | |
243 | - Most of the V6T2 instructions are only available in unified mode. | |
244 | - The .N and .W suffixes are recognized and honored (it is an error | |
245 | if they cannot be honored). | |
246 | - All instructions set the flags if and only if they have an 's' affix. | |
247 | - Conditional affixes may be used. They are validated against | |
248 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
249 | conditional affix except in the scope of an IT instruction. */ | |
250 | ||
251 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef NC |
252 | |
253 | struct arm_it | |
254 | { | |
c19d1205 | 255 | const char * error; |
b99bd4ef | 256 | unsigned long instruction; |
c19d1205 ZW |
257 | int size; |
258 | int size_req; | |
259 | int cond; | |
0110f2b8 PB |
260 | /* Set to the opcode if the instruction needs relaxation. |
261 | Zero if the instruction is not relaxed. */ | |
262 | unsigned long relax; | |
b99bd4ef NC |
263 | struct |
264 | { | |
265 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
266 | expressionS exp; |
267 | int pc_rel; | |
b99bd4ef | 268 | } reloc; |
b99bd4ef | 269 | |
c19d1205 ZW |
270 | struct |
271 | { | |
272 | unsigned reg; | |
ca3f61f7 NC |
273 | signed int imm; |
274 | unsigned present : 1; /* Operand present. */ | |
275 | unsigned isreg : 1; /* Operand was a register. */ | |
276 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
277 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ | |
278 | unsigned writeback : 1; /* Operand has trailing ! */ | |
279 | unsigned preind : 1; /* Preindexed address. */ | |
280 | unsigned postind : 1; /* Postindexed address. */ | |
281 | unsigned negative : 1; /* Index register was negated. */ | |
282 | unsigned shifted : 1; /* Shift applied to operation. */ | |
283 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
c19d1205 | 284 | } operands[6]; |
b99bd4ef NC |
285 | }; |
286 | ||
c19d1205 | 287 | static struct arm_it inst; |
b99bd4ef NC |
288 | |
289 | #define NUM_FLOAT_VALS 8 | |
290 | ||
05d2d07e | 291 | const char * fp_const[] = |
b99bd4ef NC |
292 | { |
293 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
294 | }; | |
295 | ||
c19d1205 | 296 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
297 | #define MAX_LITTLENUMS 6 |
298 | ||
299 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
300 | ||
301 | #define FAIL (-1) | |
302 | #define SUCCESS (0) | |
303 | ||
304 | #define SUFF_S 1 | |
305 | #define SUFF_D 2 | |
306 | #define SUFF_E 3 | |
307 | #define SUFF_P 4 | |
308 | ||
c19d1205 ZW |
309 | #define CP_T_X 0x00008000 |
310 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 311 | |
c19d1205 ZW |
312 | #define CONDS_BIT 0x00100000 |
313 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
314 | |
315 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
316 | ||
317 | struct asm_cond | |
318 | { | |
c19d1205 | 319 | const char * template; |
b99bd4ef NC |
320 | unsigned long value; |
321 | }; | |
322 | ||
c19d1205 | 323 | #define COND_ALWAYS 0xE |
b99bd4ef | 324 | |
b99bd4ef NC |
325 | struct asm_psr |
326 | { | |
b34976b6 | 327 | const char *template; |
b99bd4ef NC |
328 | unsigned long field; |
329 | }; | |
330 | ||
2d2255b5 | 331 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
332 | #define SPSR_BIT (1 << 22) |
333 | ||
c19d1205 ZW |
334 | /* The individual PSR flag bits. */ |
335 | #define PSR_c (1 << 16) | |
336 | #define PSR_x (1 << 17) | |
337 | #define PSR_s (1 << 18) | |
338 | #define PSR_f (1 << 19) | |
b99bd4ef | 339 | |
c19d1205 | 340 | struct reloc_entry |
bfae80f2 | 341 | { |
c19d1205 ZW |
342 | char *name; |
343 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
344 | }; |
345 | ||
346 | enum vfp_sp_reg_pos | |
347 | { | |
348 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn | |
349 | }; | |
350 | ||
351 | enum vfp_ldstm_type | |
352 | { | |
353 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
354 | }; | |
355 | ||
c19d1205 ZW |
356 | /* ARM register categories. This includes coprocessor numbers and various |
357 | architecture extensions' registers. */ | |
358 | enum arm_reg_type | |
bfae80f2 | 359 | { |
c19d1205 ZW |
360 | REG_TYPE_RN, |
361 | REG_TYPE_CP, | |
362 | REG_TYPE_CN, | |
363 | REG_TYPE_FN, | |
364 | REG_TYPE_VFS, | |
365 | REG_TYPE_VFD, | |
366 | REG_TYPE_VFC, | |
367 | REG_TYPE_MVF, | |
368 | REG_TYPE_MVD, | |
369 | REG_TYPE_MVFX, | |
370 | REG_TYPE_MVDX, | |
371 | REG_TYPE_MVAX, | |
372 | REG_TYPE_DSPSC, | |
373 | REG_TYPE_MMXWR, | |
374 | REG_TYPE_MMXWC, | |
375 | REG_TYPE_MMXWCG, | |
376 | REG_TYPE_XSCALE, | |
bfae80f2 RE |
377 | }; |
378 | ||
6c43fab6 RE |
379 | /* Structure for a hash table entry for a register. */ |
380 | struct reg_entry | |
381 | { | |
c19d1205 ZW |
382 | const char *name; |
383 | unsigned char number; | |
384 | unsigned char type; | |
385 | unsigned char builtin; | |
6c43fab6 RE |
386 | }; |
387 | ||
c19d1205 ZW |
388 | /* Diagnostics used when we don't get a register of the expected type. */ |
389 | const char *const reg_expected_msgs[] = | |
390 | { | |
391 | N_("ARM register expected"), | |
392 | N_("bad or missing co-processor number"), | |
393 | N_("co-processor register expected"), | |
394 | N_("FPA register expected"), | |
395 | N_("VFP single precision register expected"), | |
396 | N_("VFP double precision register expected"), | |
397 | N_("VFP system register expected"), | |
398 | N_("Maverick MVF register expected"), | |
399 | N_("Maverick MVD register expected"), | |
400 | N_("Maverick MVFX register expected"), | |
401 | N_("Maverick MVDX register expected"), | |
402 | N_("Maverick MVAX register expected"), | |
403 | N_("Maverick DSPSC register expected"), | |
404 | N_("iWMMXt data register expected"), | |
405 | N_("iWMMXt control register expected"), | |
406 | N_("iWMMXt scalar register expected"), | |
407 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
408 | }; |
409 | ||
c19d1205 ZW |
410 | /* Some well known registers that we refer to directly elsewhere. */ |
411 | #define REG_SP 13 | |
412 | #define REG_LR 14 | |
413 | #define REG_PC 15 | |
404ff6b5 | 414 | |
b99bd4ef NC |
415 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
416 | take 2: */ | |
c19d1205 | 417 | #define INSN_SIZE 4 |
b99bd4ef NC |
418 | |
419 | struct asm_opcode | |
420 | { | |
421 | /* Basic string to match. */ | |
c19d1205 ZW |
422 | const char *template; |
423 | ||
424 | /* Parameters to instruction. */ | |
425 | unsigned char operands[8]; | |
426 | ||
427 | /* Conditional tag - see opcode_lookup. */ | |
428 | unsigned int tag : 4; | |
b99bd4ef NC |
429 | |
430 | /* Basic instruction code. */ | |
c19d1205 | 431 | unsigned int avalue : 28; |
b99bd4ef | 432 | |
c19d1205 ZW |
433 | /* Thumb-format instruction code. */ |
434 | unsigned int tvalue; | |
b99bd4ef | 435 | |
90e4755a | 436 | /* Which architecture variant provides this instruction. */ |
e74cfd16 PB |
437 | const arm_feature_set *avariant; |
438 | const arm_feature_set *tvariant; | |
c19d1205 ZW |
439 | |
440 | /* Function to call to encode instruction in ARM format. */ | |
441 | void (* aencode) (void); | |
b99bd4ef | 442 | |
c19d1205 ZW |
443 | /* Function to call to encode instruction in Thumb format. */ |
444 | void (* tencode) (void); | |
b99bd4ef NC |
445 | }; |
446 | ||
a737bd4d NC |
447 | /* Defines for various bits that we will want to toggle. */ |
448 | #define INST_IMMEDIATE 0x02000000 | |
449 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 450 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
451 | #define SHIFT_BY_REG 0x00000010 |
452 | #define PRE_INDEX 0x01000000 | |
453 | #define INDEX_UP 0x00800000 | |
454 | #define WRITE_BACK 0x00200000 | |
455 | #define LDM_TYPE_2_OR_3 0x00400000 | |
90e4755a | 456 | |
a737bd4d NC |
457 | #define LITERAL_MASK 0xf000f000 |
458 | #define OPCODE_MASK 0xfe1fffff | |
459 | #define V4_STR_BIT 0x00000020 | |
90e4755a | 460 | |
a737bd4d | 461 | #define DATA_OP_SHIFT 21 |
90e4755a | 462 | |
ef8d22e6 PB |
463 | #define T2_OPCODE_MASK 0xfe1fffff |
464 | #define T2_DATA_OP_SHIFT 21 | |
465 | ||
a737bd4d NC |
466 | /* Codes to distinguish the arithmetic instructions. */ |
467 | #define OPCODE_AND 0 | |
468 | #define OPCODE_EOR 1 | |
469 | #define OPCODE_SUB 2 | |
470 | #define OPCODE_RSB 3 | |
471 | #define OPCODE_ADD 4 | |
472 | #define OPCODE_ADC 5 | |
473 | #define OPCODE_SBC 6 | |
474 | #define OPCODE_RSC 7 | |
475 | #define OPCODE_TST 8 | |
476 | #define OPCODE_TEQ 9 | |
477 | #define OPCODE_CMP 10 | |
478 | #define OPCODE_CMN 11 | |
479 | #define OPCODE_ORR 12 | |
480 | #define OPCODE_MOV 13 | |
481 | #define OPCODE_BIC 14 | |
482 | #define OPCODE_MVN 15 | |
90e4755a | 483 | |
ef8d22e6 PB |
484 | #define T2_OPCODE_AND 0 |
485 | #define T2_OPCODE_BIC 1 | |
486 | #define T2_OPCODE_ORR 2 | |
487 | #define T2_OPCODE_ORN 3 | |
488 | #define T2_OPCODE_EOR 4 | |
489 | #define T2_OPCODE_ADD 8 | |
490 | #define T2_OPCODE_ADC 10 | |
491 | #define T2_OPCODE_SBC 11 | |
492 | #define T2_OPCODE_SUB 13 | |
493 | #define T2_OPCODE_RSB 14 | |
494 | ||
a737bd4d NC |
495 | #define T_OPCODE_MUL 0x4340 |
496 | #define T_OPCODE_TST 0x4200 | |
497 | #define T_OPCODE_CMN 0x42c0 | |
498 | #define T_OPCODE_NEG 0x4240 | |
499 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 500 | |
a737bd4d NC |
501 | #define T_OPCODE_ADD_R3 0x1800 |
502 | #define T_OPCODE_SUB_R3 0x1a00 | |
503 | #define T_OPCODE_ADD_HI 0x4400 | |
504 | #define T_OPCODE_ADD_ST 0xb000 | |
505 | #define T_OPCODE_SUB_ST 0xb080 | |
506 | #define T_OPCODE_ADD_SP 0xa800 | |
507 | #define T_OPCODE_ADD_PC 0xa000 | |
508 | #define T_OPCODE_ADD_I8 0x3000 | |
509 | #define T_OPCODE_SUB_I8 0x3800 | |
510 | #define T_OPCODE_ADD_I3 0x1c00 | |
511 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 512 | |
a737bd4d NC |
513 | #define T_OPCODE_ASR_R 0x4100 |
514 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
515 | #define T_OPCODE_LSR_R 0x40c0 |
516 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
517 | #define T_OPCODE_ASR_I 0x1000 |
518 | #define T_OPCODE_LSL_I 0x0000 | |
519 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 520 | |
a737bd4d NC |
521 | #define T_OPCODE_MOV_I8 0x2000 |
522 | #define T_OPCODE_CMP_I8 0x2800 | |
523 | #define T_OPCODE_CMP_LR 0x4280 | |
524 | #define T_OPCODE_MOV_HR 0x4600 | |
525 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 526 | |
a737bd4d NC |
527 | #define T_OPCODE_LDR_PC 0x4800 |
528 | #define T_OPCODE_LDR_SP 0x9800 | |
529 | #define T_OPCODE_STR_SP 0x9000 | |
530 | #define T_OPCODE_LDR_IW 0x6800 | |
531 | #define T_OPCODE_STR_IW 0x6000 | |
532 | #define T_OPCODE_LDR_IH 0x8800 | |
533 | #define T_OPCODE_STR_IH 0x8000 | |
534 | #define T_OPCODE_LDR_IB 0x7800 | |
535 | #define T_OPCODE_STR_IB 0x7000 | |
536 | #define T_OPCODE_LDR_RW 0x5800 | |
537 | #define T_OPCODE_STR_RW 0x5000 | |
538 | #define T_OPCODE_LDR_RH 0x5a00 | |
539 | #define T_OPCODE_STR_RH 0x5200 | |
540 | #define T_OPCODE_LDR_RB 0x5c00 | |
541 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 542 | |
a737bd4d NC |
543 | #define T_OPCODE_PUSH 0xb400 |
544 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 545 | |
2fc8bdac | 546 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 547 | |
a737bd4d | 548 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 549 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 ZW |
550 | #define THUMB_LOAD_BIT 0x0800 |
551 | ||
552 | #define BAD_ARGS _("bad arguments to instruction") | |
553 | #define BAD_PC _("r15 not allowed here") | |
554 | #define BAD_COND _("instruction cannot be conditional") | |
555 | #define BAD_OVERLAP _("registers may not be the same") | |
556 | #define BAD_HIREG _("lo register required") | |
557 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
01cfc07f | 558 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); |
c19d1205 ZW |
559 | |
560 | static struct hash_control *arm_ops_hsh; | |
561 | static struct hash_control *arm_cond_hsh; | |
562 | static struct hash_control *arm_shift_hsh; | |
563 | static struct hash_control *arm_psr_hsh; | |
564 | static struct hash_control *arm_reg_hsh; | |
565 | static struct hash_control *arm_reloc_hsh; | |
b99bd4ef | 566 | |
b99bd4ef NC |
567 | /* Stuff needed to resolve the label ambiguity |
568 | As: | |
569 | ... | |
570 | label: <insn> | |
571 | may differ from: | |
572 | ... | |
573 | label: | |
c19d1205 | 574 | <insn> |
b99bd4ef NC |
575 | */ |
576 | ||
577 | symbolS * last_label_seen; | |
b34976b6 | 578 | static int label_is_thumb_function_name = FALSE; |
a737bd4d | 579 | \f |
3d0c9500 NC |
580 | /* Literal pool structure. Held on a per-section |
581 | and per-sub-section basis. */ | |
a737bd4d | 582 | |
c19d1205 | 583 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 584 | typedef struct literal_pool |
b99bd4ef | 585 | { |
c19d1205 ZW |
586 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
587 | unsigned int next_free_entry; | |
588 | unsigned int id; | |
589 | symbolS * symbol; | |
590 | segT section; | |
591 | subsegT sub_section; | |
61b5f74b | 592 | struct literal_pool * next; |
3d0c9500 | 593 | } literal_pool; |
b99bd4ef | 594 | |
3d0c9500 NC |
595 | /* Pointer to a linked list of literal pools. */ |
596 | literal_pool * list_of_pools = NULL; | |
e27ec89e PB |
597 | |
598 | /* State variables for IT block handling. */ | |
599 | static bfd_boolean current_it_mask = 0; | |
600 | static int current_cc; | |
601 | ||
c19d1205 ZW |
602 | \f |
603 | /* Pure syntax. */ | |
b99bd4ef | 604 | |
c19d1205 ZW |
605 | /* This array holds the chars that always start a comment. If the |
606 | pre-processor is disabled, these aren't very useful. */ | |
607 | const char comment_chars[] = "@"; | |
3d0c9500 | 608 | |
c19d1205 ZW |
609 | /* This array holds the chars that only start a comment at the beginning of |
610 | a line. If the line seems to have the form '# 123 filename' | |
611 | .line and .file directives will appear in the pre-processed output. */ | |
612 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
613 | first line of the input file. This is because the compiler outputs | |
614 | #NO_APP at the beginning of its output. */ | |
615 | /* Also note that comments like this one will always work. */ | |
616 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 617 | |
c19d1205 | 618 | const char line_separator_chars[] = ";"; |
b99bd4ef | 619 | |
c19d1205 ZW |
620 | /* Chars that can be used to separate mant |
621 | from exp in floating point numbers. */ | |
622 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 623 | |
c19d1205 ZW |
624 | /* Chars that mean this number is a floating point constant. */ |
625 | /* As in 0f12.456 */ | |
626 | /* or 0d1.2345e12 */ | |
b99bd4ef | 627 | |
c19d1205 | 628 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 629 | |
c19d1205 ZW |
630 | /* Prefix characters that indicate the start of an immediate |
631 | value. */ | |
632 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 633 | |
c19d1205 ZW |
634 | /* Separator character handling. */ |
635 | ||
636 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
637 | ||
638 | static inline int | |
639 | skip_past_char (char ** str, char c) | |
640 | { | |
641 | if (**str == c) | |
642 | { | |
643 | (*str)++; | |
644 | return SUCCESS; | |
3d0c9500 | 645 | } |
c19d1205 ZW |
646 | else |
647 | return FAIL; | |
648 | } | |
649 | #define skip_past_comma(str) skip_past_char (str, ',') | |
3d0c9500 | 650 | |
c19d1205 ZW |
651 | /* Arithmetic expressions (possibly involving symbols). */ |
652 | ||
653 | /* Return TRUE if anything in the expression is a bignum. */ | |
654 | ||
655 | static int | |
656 | walk_no_bignums (symbolS * sp) | |
657 | { | |
658 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
659 | return 1; | |
660 | ||
661 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 662 | { |
c19d1205 ZW |
663 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
664 | || (symbol_get_value_expression (sp)->X_op_symbol | |
665 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
666 | } |
667 | ||
c19d1205 | 668 | return 0; |
3d0c9500 NC |
669 | } |
670 | ||
c19d1205 ZW |
671 | static int in_my_get_expression = 0; |
672 | ||
673 | /* Third argument to my_get_expression. */ | |
674 | #define GE_NO_PREFIX 0 | |
675 | #define GE_IMM_PREFIX 1 | |
676 | #define GE_OPT_PREFIX 2 | |
a737bd4d | 677 | |
b99bd4ef | 678 | static int |
c19d1205 | 679 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 680 | { |
c19d1205 ZW |
681 | char * save_in; |
682 | segT seg; | |
b99bd4ef | 683 | |
c19d1205 ZW |
684 | /* In unified syntax, all prefixes are optional. */ |
685 | if (unified_syntax) | |
686 | prefix_mode = GE_OPT_PREFIX; | |
b99bd4ef | 687 | |
c19d1205 | 688 | switch (prefix_mode) |
b99bd4ef | 689 | { |
c19d1205 ZW |
690 | case GE_NO_PREFIX: break; |
691 | case GE_IMM_PREFIX: | |
692 | if (!is_immediate_prefix (**str)) | |
693 | { | |
694 | inst.error = _("immediate expression requires a # prefix"); | |
695 | return FAIL; | |
696 | } | |
697 | (*str)++; | |
698 | break; | |
699 | case GE_OPT_PREFIX: | |
700 | if (is_immediate_prefix (**str)) | |
701 | (*str)++; | |
702 | break; | |
703 | default: abort (); | |
704 | } | |
b99bd4ef | 705 | |
c19d1205 | 706 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 707 | |
c19d1205 ZW |
708 | save_in = input_line_pointer; |
709 | input_line_pointer = *str; | |
710 | in_my_get_expression = 1; | |
711 | seg = expression (ep); | |
712 | in_my_get_expression = 0; | |
713 | ||
714 | if (ep->X_op == O_illegal) | |
b99bd4ef | 715 | { |
c19d1205 ZW |
716 | /* We found a bad expression in md_operand(). */ |
717 | *str = input_line_pointer; | |
718 | input_line_pointer = save_in; | |
719 | if (inst.error == NULL) | |
720 | inst.error = _("bad expression"); | |
721 | return 1; | |
722 | } | |
b99bd4ef | 723 | |
c19d1205 ZW |
724 | #ifdef OBJ_AOUT |
725 | if (seg != absolute_section | |
726 | && seg != text_section | |
727 | && seg != data_section | |
728 | && seg != bss_section | |
729 | && seg != undefined_section) | |
730 | { | |
731 | inst.error = _("bad segment"); | |
732 | *str = input_line_pointer; | |
733 | input_line_pointer = save_in; | |
734 | return 1; | |
b99bd4ef | 735 | } |
c19d1205 | 736 | #endif |
b99bd4ef | 737 | |
c19d1205 ZW |
738 | /* Get rid of any bignums now, so that we don't generate an error for which |
739 | we can't establish a line number later on. Big numbers are never valid | |
740 | in instructions, which is where this routine is always called. */ | |
741 | if (ep->X_op == O_big | |
742 | || (ep->X_add_symbol | |
743 | && (walk_no_bignums (ep->X_add_symbol) | |
744 | || (ep->X_op_symbol | |
745 | && walk_no_bignums (ep->X_op_symbol))))) | |
746 | { | |
747 | inst.error = _("invalid constant"); | |
748 | *str = input_line_pointer; | |
749 | input_line_pointer = save_in; | |
750 | return 1; | |
751 | } | |
b99bd4ef | 752 | |
c19d1205 ZW |
753 | *str = input_line_pointer; |
754 | input_line_pointer = save_in; | |
755 | return 0; | |
b99bd4ef NC |
756 | } |
757 | ||
c19d1205 ZW |
758 | /* Turn a string in input_line_pointer into a floating point constant |
759 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
760 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
761 | returned, or NULL on OK. | |
b99bd4ef | 762 | |
c19d1205 ZW |
763 | Note that fp constants aren't represent in the normal way on the ARM. |
764 | In big endian mode, things are as expected. However, in little endian | |
765 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
766 | within the words. For example, (double) 1.1 in big endian mode is | |
767 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
768 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 769 | |
c19d1205 | 770 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 771 | |
c19d1205 ZW |
772 | char * |
773 | md_atof (int type, char * litP, int * sizeP) | |
774 | { | |
775 | int prec; | |
776 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
777 | char *t; | |
778 | int i; | |
b99bd4ef | 779 | |
c19d1205 ZW |
780 | switch (type) |
781 | { | |
782 | case 'f': | |
783 | case 'F': | |
784 | case 's': | |
785 | case 'S': | |
786 | prec = 2; | |
787 | break; | |
b99bd4ef | 788 | |
c19d1205 ZW |
789 | case 'd': |
790 | case 'D': | |
791 | case 'r': | |
792 | case 'R': | |
793 | prec = 4; | |
794 | break; | |
b99bd4ef | 795 | |
c19d1205 ZW |
796 | case 'x': |
797 | case 'X': | |
798 | prec = 6; | |
799 | break; | |
b99bd4ef | 800 | |
c19d1205 ZW |
801 | case 'p': |
802 | case 'P': | |
803 | prec = 6; | |
804 | break; | |
a737bd4d | 805 | |
c19d1205 ZW |
806 | default: |
807 | *sizeP = 0; | |
808 | return _("bad call to MD_ATOF()"); | |
809 | } | |
b99bd4ef | 810 | |
c19d1205 ZW |
811 | t = atof_ieee (input_line_pointer, type, words); |
812 | if (t) | |
813 | input_line_pointer = t; | |
814 | *sizeP = prec * 2; | |
b99bd4ef | 815 | |
c19d1205 ZW |
816 | if (target_big_endian) |
817 | { | |
818 | for (i = 0; i < prec; i++) | |
819 | { | |
820 | md_number_to_chars (litP, (valueT) words[i], 2); | |
821 | litP += 2; | |
822 | } | |
823 | } | |
824 | else | |
825 | { | |
e74cfd16 | 826 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
827 | for (i = prec - 1; i >= 0; i--) |
828 | { | |
829 | md_number_to_chars (litP, (valueT) words[i], 2); | |
830 | litP += 2; | |
831 | } | |
832 | else | |
833 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
834 | For an 8 byte float the order is 1 0 3 2. */ | |
835 | for (i = 0; i < prec; i += 2) | |
836 | { | |
837 | md_number_to_chars (litP, (valueT) words[i + 1], 2); | |
838 | md_number_to_chars (litP + 2, (valueT) words[i], 2); | |
839 | litP += 4; | |
840 | } | |
841 | } | |
b99bd4ef | 842 | |
c19d1205 ZW |
843 | return 0; |
844 | } | |
b99bd4ef | 845 | |
c19d1205 ZW |
846 | /* We handle all bad expressions here, so that we can report the faulty |
847 | instruction in the error message. */ | |
848 | void | |
849 | md_operand (expressionS * expr) | |
850 | { | |
851 | if (in_my_get_expression) | |
852 | expr->X_op = O_illegal; | |
b99bd4ef NC |
853 | } |
854 | ||
c19d1205 | 855 | /* Immediate values. */ |
b99bd4ef | 856 | |
c19d1205 ZW |
857 | /* Generic immediate-value read function for use in directives. |
858 | Accepts anything that 'expression' can fold to a constant. | |
859 | *val receives the number. */ | |
860 | #ifdef OBJ_ELF | |
861 | static int | |
862 | immediate_for_directive (int *val) | |
b99bd4ef | 863 | { |
c19d1205 ZW |
864 | expressionS exp; |
865 | exp.X_op = O_illegal; | |
b99bd4ef | 866 | |
c19d1205 ZW |
867 | if (is_immediate_prefix (*input_line_pointer)) |
868 | { | |
869 | input_line_pointer++; | |
870 | expression (&exp); | |
871 | } | |
b99bd4ef | 872 | |
c19d1205 ZW |
873 | if (exp.X_op != O_constant) |
874 | { | |
875 | as_bad (_("expected #constant")); | |
876 | ignore_rest_of_line (); | |
877 | return FAIL; | |
878 | } | |
879 | *val = exp.X_add_number; | |
880 | return SUCCESS; | |
b99bd4ef | 881 | } |
c19d1205 | 882 | #endif |
b99bd4ef | 883 | |
c19d1205 | 884 | /* Register parsing. */ |
b99bd4ef | 885 | |
c19d1205 ZW |
886 | /* Generic register parser. CCP points to what should be the |
887 | beginning of a register name. If it is indeed a valid register | |
888 | name, advance CCP over it and return the reg_entry structure; | |
889 | otherwise return NULL. Does not issue diagnostics. */ | |
890 | ||
891 | static struct reg_entry * | |
892 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 893 | { |
c19d1205 ZW |
894 | char *start = *ccp; |
895 | char *p; | |
896 | struct reg_entry *reg; | |
b99bd4ef | 897 | |
c19d1205 ZW |
898 | #ifdef REGISTER_PREFIX |
899 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 900 | return NULL; |
c19d1205 ZW |
901 | start++; |
902 | #endif | |
903 | #ifdef OPTIONAL_REGISTER_PREFIX | |
904 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
905 | start++; | |
906 | #endif | |
b99bd4ef | 907 | |
c19d1205 ZW |
908 | p = start; |
909 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
910 | return NULL; | |
b99bd4ef | 911 | |
c19d1205 ZW |
912 | do |
913 | p++; | |
914 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
915 | ||
916 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
917 | ||
918 | if (!reg) | |
919 | return NULL; | |
920 | ||
921 | *ccp = p; | |
922 | return reg; | |
b99bd4ef NC |
923 | } |
924 | ||
c19d1205 | 925 | /* As above, but the register must be of type TYPE, and the return |
01cfc07f | 926 | value is the register number or FAIL. */ |
c19d1205 | 927 | |
b99bd4ef | 928 | static int |
c19d1205 | 929 | arm_reg_parse (char **ccp, enum arm_reg_type type) |
b99bd4ef | 930 | { |
c19d1205 ZW |
931 | char *start = *ccp; |
932 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
b99bd4ef | 933 | |
c19d1205 ZW |
934 | if (reg && reg->type == type) |
935 | return reg->number; | |
6057a28f | 936 | |
c19d1205 ZW |
937 | /* Alternative syntaxes are accepted for a few register classes. */ |
938 | switch (type) | |
939 | { | |
940 | case REG_TYPE_MVF: | |
941 | case REG_TYPE_MVD: | |
942 | case REG_TYPE_MVFX: | |
943 | case REG_TYPE_MVDX: | |
944 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 945 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
946 | return reg->number; |
947 | break; | |
69b97547 | 948 | |
c19d1205 ZW |
949 | case REG_TYPE_CP: |
950 | /* For backward compatibility, a bare number is valid here. */ | |
951 | { | |
952 | unsigned long processor = strtoul (start, ccp, 10); | |
953 | if (*ccp != start && processor <= 15) | |
954 | return processor; | |
955 | } | |
6057a28f | 956 | |
c19d1205 ZW |
957 | case REG_TYPE_MMXWC: |
958 | /* WC includes WCG. ??? I'm not sure this is true for all | |
959 | instructions that take WC registers. */ | |
79134647 | 960 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 961 | return reg->number; |
6057a28f | 962 | break; |
c19d1205 | 963 | |
6057a28f | 964 | default: |
c19d1205 | 965 | break; |
6057a28f NC |
966 | } |
967 | ||
c19d1205 ZW |
968 | *ccp = start; |
969 | return FAIL; | |
970 | } | |
69b97547 | 971 | |
c19d1205 ZW |
972 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
973 | static long | |
974 | parse_reg_list (char ** strp) | |
975 | { | |
976 | char * str = * strp; | |
977 | long range = 0; | |
978 | int another_range; | |
a737bd4d | 979 | |
c19d1205 ZW |
980 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
981 | do | |
6057a28f | 982 | { |
c19d1205 | 983 | another_range = 0; |
a737bd4d | 984 | |
c19d1205 ZW |
985 | if (*str == '{') |
986 | { | |
987 | int in_range = 0; | |
988 | int cur_reg = -1; | |
a737bd4d | 989 | |
c19d1205 ZW |
990 | str++; |
991 | do | |
992 | { | |
993 | int reg; | |
6057a28f | 994 | |
c19d1205 ZW |
995 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
996 | { | |
997 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
998 | return FAIL; | |
999 | } | |
a737bd4d | 1000 | |
c19d1205 ZW |
1001 | if (in_range) |
1002 | { | |
1003 | int i; | |
a737bd4d | 1004 | |
c19d1205 ZW |
1005 | if (reg <= cur_reg) |
1006 | { | |
1007 | inst.error = _("bad range in register list"); | |
1008 | return FAIL; | |
1009 | } | |
40a18ebd | 1010 | |
c19d1205 ZW |
1011 | for (i = cur_reg + 1; i < reg; i++) |
1012 | { | |
1013 | if (range & (1 << i)) | |
1014 | as_tsktsk | |
1015 | (_("Warning: duplicated register (r%d) in register list"), | |
1016 | i); | |
1017 | else | |
1018 | range |= 1 << i; | |
1019 | } | |
1020 | in_range = 0; | |
1021 | } | |
a737bd4d | 1022 | |
c19d1205 ZW |
1023 | if (range & (1 << reg)) |
1024 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1025 | reg); | |
1026 | else if (reg <= cur_reg) | |
1027 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1028 | |
c19d1205 ZW |
1029 | range |= 1 << reg; |
1030 | cur_reg = reg; | |
1031 | } | |
1032 | while (skip_past_comma (&str) != FAIL | |
1033 | || (in_range = 1, *str++ == '-')); | |
1034 | str--; | |
a737bd4d | 1035 | |
c19d1205 ZW |
1036 | if (*str++ != '}') |
1037 | { | |
1038 | inst.error = _("missing `}'"); | |
1039 | return FAIL; | |
1040 | } | |
1041 | } | |
1042 | else | |
1043 | { | |
1044 | expressionS expr; | |
40a18ebd | 1045 | |
c19d1205 ZW |
1046 | if (my_get_expression (&expr, &str, GE_NO_PREFIX)) |
1047 | return FAIL; | |
40a18ebd | 1048 | |
c19d1205 ZW |
1049 | if (expr.X_op == O_constant) |
1050 | { | |
1051 | if (expr.X_add_number | |
1052 | != (expr.X_add_number & 0x0000ffff)) | |
1053 | { | |
1054 | inst.error = _("invalid register mask"); | |
1055 | return FAIL; | |
1056 | } | |
a737bd4d | 1057 | |
c19d1205 ZW |
1058 | if ((range & expr.X_add_number) != 0) |
1059 | { | |
1060 | int regno = range & expr.X_add_number; | |
a737bd4d | 1061 | |
c19d1205 ZW |
1062 | regno &= -regno; |
1063 | regno = (1 << regno) - 1; | |
1064 | as_tsktsk | |
1065 | (_("Warning: duplicated register (r%d) in register list"), | |
1066 | regno); | |
1067 | } | |
a737bd4d | 1068 | |
c19d1205 ZW |
1069 | range |= expr.X_add_number; |
1070 | } | |
1071 | else | |
1072 | { | |
1073 | if (inst.reloc.type != 0) | |
1074 | { | |
1075 | inst.error = _("expression too complex"); | |
1076 | return FAIL; | |
1077 | } | |
a737bd4d | 1078 | |
c19d1205 ZW |
1079 | memcpy (&inst.reloc.exp, &expr, sizeof (expressionS)); |
1080 | inst.reloc.type = BFD_RELOC_ARM_MULTI; | |
1081 | inst.reloc.pc_rel = 0; | |
1082 | } | |
1083 | } | |
a737bd4d | 1084 | |
c19d1205 ZW |
1085 | if (*str == '|' || *str == '+') |
1086 | { | |
1087 | str++; | |
1088 | another_range = 1; | |
1089 | } | |
a737bd4d | 1090 | } |
c19d1205 | 1091 | while (another_range); |
a737bd4d | 1092 | |
c19d1205 ZW |
1093 | *strp = str; |
1094 | return range; | |
a737bd4d NC |
1095 | } |
1096 | ||
c19d1205 ZW |
1097 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1098 | Otherwise return the number of registers, and set PBASE to the first | |
1099 | register. Double precision registers are matched if DP is nonzero. */ | |
6057a28f | 1100 | |
c19d1205 | 1101 | static int |
ca3f61f7 | 1102 | parse_vfp_reg_list (char **str, unsigned int *pbase, int dp) |
6057a28f | 1103 | { |
c19d1205 ZW |
1104 | int base_reg; |
1105 | int new_base; | |
1106 | int regtype; | |
1107 | int max_regs; | |
1108 | int count = 0; | |
1109 | int warned = 0; | |
1110 | unsigned long mask = 0; | |
a737bd4d | 1111 | int i; |
6057a28f | 1112 | |
c19d1205 ZW |
1113 | if (**str != '{') |
1114 | return FAIL; | |
6057a28f | 1115 | |
c19d1205 | 1116 | (*str)++; |
6057a28f | 1117 | |
c19d1205 | 1118 | if (dp) |
a737bd4d | 1119 | { |
c19d1205 ZW |
1120 | regtype = REG_TYPE_VFD; |
1121 | max_regs = 16; | |
1122 | } | |
1123 | else | |
1124 | { | |
1125 | regtype = REG_TYPE_VFS; | |
1126 | max_regs = 32; | |
1127 | } | |
6057a28f | 1128 | |
c19d1205 | 1129 | base_reg = max_regs; |
a737bd4d | 1130 | |
c19d1205 ZW |
1131 | do |
1132 | { | |
1133 | new_base = arm_reg_parse (str, regtype); | |
1134 | if (new_base == FAIL) | |
a737bd4d | 1135 | { |
c19d1205 ZW |
1136 | inst.error = gettext (reg_expected_msgs[regtype]); |
1137 | return FAIL; | |
1138 | } | |
a737bd4d | 1139 | |
c19d1205 ZW |
1140 | if (new_base < base_reg) |
1141 | base_reg = new_base; | |
a737bd4d | 1142 | |
c19d1205 ZW |
1143 | if (mask & (1 << new_base)) |
1144 | { | |
1145 | inst.error = _("invalid register list"); | |
1146 | return FAIL; | |
a737bd4d | 1147 | } |
a737bd4d | 1148 | |
c19d1205 ZW |
1149 | if ((mask >> new_base) != 0 && ! warned) |
1150 | { | |
1151 | as_tsktsk (_("register list not in ascending order")); | |
1152 | warned = 1; | |
1153 | } | |
0bbf2aa4 | 1154 | |
c19d1205 ZW |
1155 | mask |= 1 << new_base; |
1156 | count++; | |
0bbf2aa4 | 1157 | |
c19d1205 ZW |
1158 | if (**str == '-') /* We have the start of a range expression */ |
1159 | { | |
1160 | int high_range; | |
0bbf2aa4 | 1161 | |
c19d1205 | 1162 | (*str)++; |
0bbf2aa4 | 1163 | |
c19d1205 ZW |
1164 | if ((high_range = arm_reg_parse (str, regtype)) == FAIL) |
1165 | { | |
1166 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1167 | return FAIL; | |
1168 | } | |
0bbf2aa4 | 1169 | |
c19d1205 ZW |
1170 | if (high_range <= new_base) |
1171 | { | |
1172 | inst.error = _("register range not in ascending order"); | |
1173 | return FAIL; | |
1174 | } | |
0bbf2aa4 | 1175 | |
c19d1205 | 1176 | for (new_base++; new_base <= high_range; new_base++) |
0bbf2aa4 | 1177 | { |
c19d1205 | 1178 | if (mask & (1 << new_base)) |
0bbf2aa4 | 1179 | { |
c19d1205 ZW |
1180 | inst.error = _("invalid register list"); |
1181 | return FAIL; | |
0bbf2aa4 | 1182 | } |
c19d1205 ZW |
1183 | |
1184 | mask |= 1 << new_base; | |
1185 | count++; | |
0bbf2aa4 | 1186 | } |
0bbf2aa4 | 1187 | } |
0bbf2aa4 | 1188 | } |
c19d1205 | 1189 | while (skip_past_comma (str) != FAIL); |
0bbf2aa4 | 1190 | |
c19d1205 | 1191 | (*str)++; |
0bbf2aa4 | 1192 | |
c19d1205 ZW |
1193 | /* Sanity check -- should have raised a parse error above. */ |
1194 | if (count == 0 || count > max_regs) | |
1195 | abort (); | |
1196 | ||
1197 | *pbase = base_reg; | |
1198 | ||
1199 | /* Final test -- the registers must be consecutive. */ | |
1200 | mask >>= base_reg; | |
1201 | for (i = 0; i < count; i++) | |
1202 | { | |
1203 | if ((mask & (1u << i)) == 0) | |
1204 | { | |
1205 | inst.error = _("non-contiguous register range"); | |
1206 | return FAIL; | |
1207 | } | |
1208 | } | |
1209 | ||
1210 | return count; | |
b99bd4ef NC |
1211 | } |
1212 | ||
c19d1205 ZW |
1213 | /* Parse an explicit relocation suffix on an expression. This is |
1214 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
1215 | arm_reloc_hsh contains no entries, so this function can only | |
1216 | succeed if there is no () after the word. Returns -1 on error, | |
1217 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
1218 | static int | |
1219 | parse_reloc (char **str) | |
b99bd4ef | 1220 | { |
c19d1205 ZW |
1221 | struct reloc_entry *r; |
1222 | char *p, *q; | |
b99bd4ef | 1223 | |
c19d1205 ZW |
1224 | if (**str != '(') |
1225 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 1226 | |
c19d1205 ZW |
1227 | p = *str + 1; |
1228 | q = p; | |
1229 | ||
1230 | while (*q && *q != ')' && *q != ',') | |
1231 | q++; | |
1232 | if (*q != ')') | |
1233 | return -1; | |
1234 | ||
1235 | if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
1236 | return -1; | |
1237 | ||
1238 | *str = q + 1; | |
1239 | return r->reloc; | |
b99bd4ef NC |
1240 | } |
1241 | ||
c19d1205 ZW |
1242 | /* Directives: register aliases. */ |
1243 | ||
b99bd4ef | 1244 | static void |
c19d1205 | 1245 | insert_reg_alias (char *str, int number, int type) |
b99bd4ef | 1246 | { |
c19d1205 ZW |
1247 | struct reg_entry *new; |
1248 | const char *name; | |
b99bd4ef | 1249 | |
c19d1205 ZW |
1250 | if ((new = hash_find (arm_reg_hsh, str)) != 0) |
1251 | { | |
1252 | if (new->builtin) | |
1253 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); | |
b99bd4ef | 1254 | |
c19d1205 ZW |
1255 | /* Only warn about a redefinition if it's not defined as the |
1256 | same register. */ | |
1257 | else if (new->number != number || new->type != type) | |
1258 | as_warn (_("ignoring redefinition of register alias '%s'"), str); | |
69b97547 | 1259 | |
c19d1205 ZW |
1260 | return; |
1261 | } | |
b99bd4ef | 1262 | |
c19d1205 ZW |
1263 | name = xstrdup (str); |
1264 | new = xmalloc (sizeof (struct reg_entry)); | |
b99bd4ef | 1265 | |
c19d1205 ZW |
1266 | new->name = name; |
1267 | new->number = number; | |
1268 | new->type = type; | |
1269 | new->builtin = FALSE; | |
b99bd4ef | 1270 | |
c19d1205 ZW |
1271 | if (hash_insert (arm_reg_hsh, name, (PTR) new)) |
1272 | abort (); | |
1273 | } | |
b99bd4ef | 1274 | |
c19d1205 | 1275 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 1276 | |
c19d1205 | 1277 | new_register_name .req existing_register_name |
b99bd4ef | 1278 | |
c19d1205 ZW |
1279 | If we find one, or if it looks sufficiently like one that we want to |
1280 | handle any error here, return non-zero. Otherwise return zero. */ | |
b99bd4ef | 1281 | |
c19d1205 ZW |
1282 | static int |
1283 | create_register_alias (char * newname, char *p) | |
1284 | { | |
1285 | struct reg_entry *old; | |
1286 | char *oldname, *nbuf; | |
1287 | size_t nlen; | |
b99bd4ef | 1288 | |
c19d1205 ZW |
1289 | /* The input scrubber ensures that whitespace after the mnemonic is |
1290 | collapsed to single spaces. */ | |
1291 | oldname = p; | |
1292 | if (strncmp (oldname, " .req ", 6) != 0) | |
1293 | return 0; | |
b99bd4ef | 1294 | |
c19d1205 ZW |
1295 | oldname += 6; |
1296 | if (*oldname == '\0') | |
1297 | return 0; | |
b99bd4ef | 1298 | |
c19d1205 ZW |
1299 | old = hash_find (arm_reg_hsh, oldname); |
1300 | if (!old) | |
b99bd4ef | 1301 | { |
c19d1205 ZW |
1302 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
1303 | return 1; | |
b99bd4ef NC |
1304 | } |
1305 | ||
c19d1205 ZW |
1306 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
1307 | the desired alias name, and p points to its end. If not, then | |
1308 | the desired alias name is in the global original_case_string. */ | |
1309 | #ifdef TC_CASE_SENSITIVE | |
1310 | nlen = p - newname; | |
1311 | #else | |
1312 | newname = original_case_string; | |
1313 | nlen = strlen (newname); | |
1314 | #endif | |
b99bd4ef | 1315 | |
c19d1205 ZW |
1316 | nbuf = alloca (nlen + 1); |
1317 | memcpy (nbuf, newname, nlen); | |
1318 | nbuf[nlen] = '\0'; | |
b99bd4ef | 1319 | |
c19d1205 ZW |
1320 | /* Create aliases under the new name as stated; an all-lowercase |
1321 | version of the new name; and an all-uppercase version of the new | |
1322 | name. */ | |
1323 | insert_reg_alias (nbuf, old->number, old->type); | |
b99bd4ef | 1324 | |
c19d1205 ZW |
1325 | for (p = nbuf; *p; p++) |
1326 | *p = TOUPPER (*p); | |
1327 | ||
1328 | if (strncmp (nbuf, newname, nlen)) | |
1329 | insert_reg_alias (nbuf, old->number, old->type); | |
1330 | ||
1331 | for (p = nbuf; *p; p++) | |
1332 | *p = TOLOWER (*p); | |
1333 | ||
1334 | if (strncmp (nbuf, newname, nlen)) | |
1335 | insert_reg_alias (nbuf, old->number, old->type); | |
1336 | ||
1337 | return 1; | |
b99bd4ef NC |
1338 | } |
1339 | ||
c19d1205 ZW |
1340 | /* Should never be called, as .req goes between the alias and the |
1341 | register name, not at the beginning of the line. */ | |
b99bd4ef | 1342 | static void |
c19d1205 | 1343 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 1344 | { |
c19d1205 ZW |
1345 | as_bad (_("invalid syntax for .req directive")); |
1346 | } | |
b99bd4ef | 1347 | |
c19d1205 ZW |
1348 | /* The .unreq directive deletes an alias which was previously defined |
1349 | by .req. For example: | |
b99bd4ef | 1350 | |
c19d1205 ZW |
1351 | my_alias .req r11 |
1352 | .unreq my_alias */ | |
b99bd4ef NC |
1353 | |
1354 | static void | |
c19d1205 | 1355 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 1356 | { |
c19d1205 ZW |
1357 | char * name; |
1358 | char saved_char; | |
b99bd4ef | 1359 | |
c19d1205 ZW |
1360 | name = input_line_pointer; |
1361 | ||
1362 | while (*input_line_pointer != 0 | |
1363 | && *input_line_pointer != ' ' | |
1364 | && *input_line_pointer != '\n') | |
1365 | ++input_line_pointer; | |
1366 | ||
1367 | saved_char = *input_line_pointer; | |
1368 | *input_line_pointer = 0; | |
1369 | ||
1370 | if (!*name) | |
1371 | as_bad (_("invalid syntax for .unreq directive")); | |
1372 | else | |
1373 | { | |
1374 | struct reg_entry *reg = hash_find (arm_reg_hsh, name); | |
1375 | ||
1376 | if (!reg) | |
1377 | as_bad (_("unknown register alias '%s'"), name); | |
1378 | else if (reg->builtin) | |
1379 | as_warn (_("ignoring attempt to undefine built-in register '%s'"), | |
1380 | name); | |
1381 | else | |
1382 | { | |
1383 | hash_delete (arm_reg_hsh, name); | |
1384 | free ((char *) reg->name); | |
1385 | free (reg); | |
1386 | } | |
1387 | } | |
b99bd4ef | 1388 | |
c19d1205 | 1389 | *input_line_pointer = saved_char; |
b99bd4ef NC |
1390 | demand_empty_rest_of_line (); |
1391 | } | |
1392 | ||
c19d1205 ZW |
1393 | /* Directives: Instruction set selection. */ |
1394 | ||
1395 | #ifdef OBJ_ELF | |
1396 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
1397 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
1398 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
1399 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
1400 | ||
1401 | static enum mstate mapstate = MAP_UNDEFINED; | |
b99bd4ef NC |
1402 | |
1403 | static void | |
c19d1205 | 1404 | mapping_state (enum mstate state) |
b99bd4ef | 1405 | { |
a737bd4d | 1406 | symbolS * symbolP; |
c19d1205 ZW |
1407 | const char * symname; |
1408 | int type; | |
b99bd4ef | 1409 | |
c19d1205 ZW |
1410 | if (mapstate == state) |
1411 | /* The mapping symbol has already been emitted. | |
1412 | There is nothing else to do. */ | |
1413 | return; | |
b99bd4ef | 1414 | |
c19d1205 | 1415 | mapstate = state; |
b99bd4ef | 1416 | |
c19d1205 | 1417 | switch (state) |
b99bd4ef | 1418 | { |
c19d1205 ZW |
1419 | case MAP_DATA: |
1420 | symname = "$d"; | |
1421 | type = BSF_NO_FLAGS; | |
1422 | break; | |
1423 | case MAP_ARM: | |
1424 | symname = "$a"; | |
1425 | type = BSF_NO_FLAGS; | |
1426 | break; | |
1427 | case MAP_THUMB: | |
1428 | symname = "$t"; | |
1429 | type = BSF_NO_FLAGS; | |
1430 | break; | |
1431 | case MAP_UNDEFINED: | |
1432 | return; | |
1433 | default: | |
1434 | abort (); | |
1435 | } | |
1436 | ||
1437 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; | |
1438 | ||
1439 | symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now); | |
1440 | symbol_table_insert (symbolP); | |
1441 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; | |
1442 | ||
1443 | switch (state) | |
1444 | { | |
1445 | case MAP_ARM: | |
1446 | THUMB_SET_FUNC (symbolP, 0); | |
1447 | ARM_SET_THUMB (symbolP, 0); | |
1448 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
1449 | break; | |
1450 | ||
1451 | case MAP_THUMB: | |
1452 | THUMB_SET_FUNC (symbolP, 1); | |
1453 | ARM_SET_THUMB (symbolP, 1); | |
1454 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
1455 | break; | |
1456 | ||
1457 | case MAP_DATA: | |
1458 | default: | |
1459 | return; | |
1460 | } | |
1461 | } | |
1462 | #else | |
1463 | #define mapping_state(x) /* nothing */ | |
1464 | #endif | |
1465 | ||
1466 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
1467 | ||
1468 | static symbolS * | |
1469 | find_real_start (symbolS * symbolP) | |
1470 | { | |
1471 | char * real_start; | |
1472 | const char * name = S_GET_NAME (symbolP); | |
1473 | symbolS * new_target; | |
1474 | ||
1475 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
1476 | #define STUB_NAME ".real_start_of" | |
1477 | ||
1478 | if (name == NULL) | |
1479 | abort (); | |
1480 | ||
37f6032b ZW |
1481 | /* The compiler may generate BL instructions to local labels because |
1482 | it needs to perform a branch to a far away location. These labels | |
1483 | do not have a corresponding ".real_start_of" label. We check | |
1484 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
1485 | the ".real_start_of" convention for nonlocal branches. */ | |
1486 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
1487 | return symbolP; |
1488 | ||
37f6032b | 1489 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
1490 | new_target = symbol_find (real_start); |
1491 | ||
1492 | if (new_target == NULL) | |
1493 | { | |
1494 | as_warn ("Failed to find real start of function: %s\n", name); | |
1495 | new_target = symbolP; | |
1496 | } | |
1497 | ||
c19d1205 ZW |
1498 | return new_target; |
1499 | } | |
1500 | ||
1501 | static void | |
1502 | opcode_select (int width) | |
1503 | { | |
1504 | switch (width) | |
1505 | { | |
1506 | case 16: | |
1507 | if (! thumb_mode) | |
1508 | { | |
e74cfd16 | 1509 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
1510 | as_bad (_("selected processor does not support THUMB opcodes")); |
1511 | ||
1512 | thumb_mode = 1; | |
1513 | /* No need to force the alignment, since we will have been | |
1514 | coming from ARM mode, which is word-aligned. */ | |
1515 | record_alignment (now_seg, 1); | |
1516 | } | |
1517 | mapping_state (MAP_THUMB); | |
1518 | break; | |
1519 | ||
1520 | case 32: | |
1521 | if (thumb_mode) | |
1522 | { | |
e74cfd16 | 1523 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
1524 | as_bad (_("selected processor does not support ARM opcodes")); |
1525 | ||
1526 | thumb_mode = 0; | |
1527 | ||
1528 | if (!need_pass_2) | |
1529 | frag_align (2, 0, 0); | |
1530 | ||
1531 | record_alignment (now_seg, 1); | |
1532 | } | |
1533 | mapping_state (MAP_ARM); | |
1534 | break; | |
1535 | ||
1536 | default: | |
1537 | as_bad (_("invalid instruction size selected (%d)"), width); | |
1538 | } | |
1539 | } | |
1540 | ||
1541 | static void | |
1542 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
1543 | { | |
1544 | opcode_select (32); | |
1545 | demand_empty_rest_of_line (); | |
1546 | } | |
1547 | ||
1548 | static void | |
1549 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
1550 | { | |
1551 | opcode_select (16); | |
1552 | demand_empty_rest_of_line (); | |
1553 | } | |
1554 | ||
1555 | static void | |
1556 | s_code (int unused ATTRIBUTE_UNUSED) | |
1557 | { | |
1558 | int temp; | |
1559 | ||
1560 | temp = get_absolute_expression (); | |
1561 | switch (temp) | |
1562 | { | |
1563 | case 16: | |
1564 | case 32: | |
1565 | opcode_select (temp); | |
1566 | break; | |
1567 | ||
1568 | default: | |
1569 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
1570 | } | |
1571 | } | |
1572 | ||
1573 | static void | |
1574 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
1575 | { | |
1576 | /* If we are not already in thumb mode go into it, EVEN if | |
1577 | the target processor does not support thumb instructions. | |
1578 | This is used by gcc/config/arm/lib1funcs.asm for example | |
1579 | to compile interworking support functions even if the | |
1580 | target processor should not support interworking. */ | |
1581 | if (! thumb_mode) | |
1582 | { | |
1583 | thumb_mode = 2; | |
1584 | record_alignment (now_seg, 1); | |
1585 | } | |
1586 | ||
1587 | demand_empty_rest_of_line (); | |
1588 | } | |
1589 | ||
1590 | static void | |
1591 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
1592 | { | |
1593 | s_thumb (0); | |
1594 | ||
1595 | /* The following label is the name/address of the start of a Thumb function. | |
1596 | We need to know this for the interworking support. */ | |
1597 | label_is_thumb_function_name = TRUE; | |
1598 | } | |
1599 | ||
1600 | /* Perform a .set directive, but also mark the alias as | |
1601 | being a thumb function. */ | |
1602 | ||
1603 | static void | |
1604 | s_thumb_set (int equiv) | |
1605 | { | |
1606 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
1607 | We cannot just call that code as we need to get at the symbol that | |
1608 | is created. */ | |
1609 | char * name; | |
1610 | char delim; | |
1611 | char * end_name; | |
1612 | symbolS * symbolP; | |
1613 | ||
1614 | /* Especial apologies for the random logic: | |
1615 | This just grew, and could be parsed much more simply! | |
1616 | Dean - in haste. */ | |
1617 | name = input_line_pointer; | |
1618 | delim = get_symbol_end (); | |
1619 | end_name = input_line_pointer; | |
1620 | *end_name = delim; | |
1621 | ||
1622 | if (*input_line_pointer != ',') | |
1623 | { | |
1624 | *end_name = 0; | |
1625 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
1626 | *end_name = delim; |
1627 | ignore_rest_of_line (); | |
1628 | return; | |
1629 | } | |
1630 | ||
1631 | input_line_pointer++; | |
1632 | *end_name = 0; | |
1633 | ||
1634 | if (name[0] == '.' && name[1] == '\0') | |
1635 | { | |
1636 | /* XXX - this should not happen to .thumb_set. */ | |
1637 | abort (); | |
1638 | } | |
1639 | ||
1640 | if ((symbolP = symbol_find (name)) == NULL | |
1641 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
1642 | { | |
1643 | #ifndef NO_LISTING | |
1644 | /* When doing symbol listings, play games with dummy fragments living | |
1645 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 1646 | for this symbol. */ |
b99bd4ef NC |
1647 | if (listing & LISTING_SYMBOLS) |
1648 | { | |
1649 | extern struct list_info_struct * listing_tail; | |
a737bd4d | 1650 | fragS * dummy_frag = xmalloc (sizeof (fragS)); |
b99bd4ef NC |
1651 | |
1652 | memset (dummy_frag, 0, sizeof (fragS)); | |
1653 | dummy_frag->fr_type = rs_fill; | |
1654 | dummy_frag->line = listing_tail; | |
1655 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
1656 | dummy_frag->fr_symbol = symbolP; | |
1657 | } | |
1658 | else | |
1659 | #endif | |
1660 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
1661 | ||
1662 | #ifdef OBJ_COFF | |
1663 | /* "set" symbols are local unless otherwise specified. */ | |
1664 | SF_SET_LOCAL (symbolP); | |
1665 | #endif /* OBJ_COFF */ | |
1666 | } /* Make a new symbol. */ | |
1667 | ||
1668 | symbol_table_insert (symbolP); | |
1669 | ||
1670 | * end_name = delim; | |
1671 | ||
1672 | if (equiv | |
1673 | && S_IS_DEFINED (symbolP) | |
1674 | && S_GET_SEGMENT (symbolP) != reg_section) | |
1675 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
1676 | ||
1677 | pseudo_set (symbolP); | |
1678 | ||
1679 | demand_empty_rest_of_line (); | |
1680 | ||
c19d1205 | 1681 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
1682 | |
1683 | THUMB_SET_FUNC (symbolP, 1); | |
1684 | ARM_SET_THUMB (symbolP, 1); | |
1685 | #if defined OBJ_ELF || defined OBJ_COFF | |
1686 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
1687 | #endif | |
1688 | } | |
1689 | ||
c19d1205 | 1690 | /* Directives: Mode selection. */ |
b99bd4ef | 1691 | |
c19d1205 ZW |
1692 | /* .syntax [unified|divided] - choose the new unified syntax |
1693 | (same for Arm and Thumb encoding, modulo slight differences in what | |
1694 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 1695 | static void |
c19d1205 | 1696 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 1697 | { |
c19d1205 ZW |
1698 | char *name, delim; |
1699 | ||
1700 | name = input_line_pointer; | |
1701 | delim = get_symbol_end (); | |
1702 | ||
1703 | if (!strcasecmp (name, "unified")) | |
1704 | unified_syntax = TRUE; | |
1705 | else if (!strcasecmp (name, "divided")) | |
1706 | unified_syntax = FALSE; | |
1707 | else | |
1708 | { | |
1709 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
1710 | return; | |
1711 | } | |
1712 | *input_line_pointer = delim; | |
b99bd4ef NC |
1713 | demand_empty_rest_of_line (); |
1714 | } | |
1715 | ||
c19d1205 ZW |
1716 | /* Directives: sectioning and alignment. */ |
1717 | ||
1718 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
1719 | ||
b99bd4ef | 1720 | static void |
c19d1205 | 1721 | s_align (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 1722 | { |
a737bd4d | 1723 | int temp; |
c19d1205 ZW |
1724 | long temp_fill; |
1725 | long max_alignment = 15; | |
b99bd4ef NC |
1726 | |
1727 | temp = get_absolute_expression (); | |
c19d1205 ZW |
1728 | if (temp > max_alignment) |
1729 | as_bad (_("alignment too large: %d assumed"), temp = max_alignment); | |
1730 | else if (temp < 0) | |
b99bd4ef | 1731 | { |
c19d1205 ZW |
1732 | as_bad (_("alignment negative. 0 assumed.")); |
1733 | temp = 0; | |
1734 | } | |
b99bd4ef | 1735 | |
c19d1205 ZW |
1736 | if (*input_line_pointer == ',') |
1737 | { | |
1738 | input_line_pointer++; | |
1739 | temp_fill = get_absolute_expression (); | |
b99bd4ef | 1740 | } |
c19d1205 ZW |
1741 | else |
1742 | temp_fill = 0; | |
b99bd4ef | 1743 | |
c19d1205 ZW |
1744 | if (!temp) |
1745 | temp = 2; | |
b99bd4ef | 1746 | |
c19d1205 ZW |
1747 | /* Only make a frag if we HAVE to. */ |
1748 | if (temp && !need_pass_2) | |
1749 | frag_align (temp, (int) temp_fill, 0); | |
1750 | demand_empty_rest_of_line (); | |
1751 | ||
1752 | record_alignment (now_seg, temp); | |
b99bd4ef NC |
1753 | } |
1754 | ||
c19d1205 ZW |
1755 | static void |
1756 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 1757 | { |
c19d1205 ZW |
1758 | /* We don't support putting frags in the BSS segment, we fake it by |
1759 | marking in_bss, then looking at s_skip for clues. */ | |
1760 | subseg_set (bss_section, 0); | |
1761 | demand_empty_rest_of_line (); | |
1762 | mapping_state (MAP_DATA); | |
1763 | } | |
b99bd4ef | 1764 | |
c19d1205 ZW |
1765 | static void |
1766 | s_even (int ignore ATTRIBUTE_UNUSED) | |
1767 | { | |
1768 | /* Never make frag if expect extra pass. */ | |
1769 | if (!need_pass_2) | |
1770 | frag_align (1, 0, 0); | |
b99bd4ef | 1771 | |
c19d1205 | 1772 | record_alignment (now_seg, 1); |
b99bd4ef | 1773 | |
c19d1205 | 1774 | demand_empty_rest_of_line (); |
b99bd4ef NC |
1775 | } |
1776 | ||
c19d1205 | 1777 | /* Directives: Literal pools. */ |
a737bd4d | 1778 | |
c19d1205 ZW |
1779 | static literal_pool * |
1780 | find_literal_pool (void) | |
a737bd4d | 1781 | { |
c19d1205 | 1782 | literal_pool * pool; |
a737bd4d | 1783 | |
c19d1205 | 1784 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 1785 | { |
c19d1205 ZW |
1786 | if (pool->section == now_seg |
1787 | && pool->sub_section == now_subseg) | |
1788 | break; | |
a737bd4d NC |
1789 | } |
1790 | ||
c19d1205 | 1791 | return pool; |
a737bd4d NC |
1792 | } |
1793 | ||
c19d1205 ZW |
1794 | static literal_pool * |
1795 | find_or_make_literal_pool (void) | |
a737bd4d | 1796 | { |
c19d1205 ZW |
1797 | /* Next literal pool ID number. */ |
1798 | static unsigned int latest_pool_num = 1; | |
1799 | literal_pool * pool; | |
a737bd4d | 1800 | |
c19d1205 | 1801 | pool = find_literal_pool (); |
a737bd4d | 1802 | |
c19d1205 | 1803 | if (pool == NULL) |
a737bd4d | 1804 | { |
c19d1205 ZW |
1805 | /* Create a new pool. */ |
1806 | pool = xmalloc (sizeof (* pool)); | |
1807 | if (! pool) | |
1808 | return NULL; | |
a737bd4d | 1809 | |
c19d1205 ZW |
1810 | pool->next_free_entry = 0; |
1811 | pool->section = now_seg; | |
1812 | pool->sub_section = now_subseg; | |
1813 | pool->next = list_of_pools; | |
1814 | pool->symbol = NULL; | |
1815 | ||
1816 | /* Add it to the list. */ | |
1817 | list_of_pools = pool; | |
a737bd4d | 1818 | } |
a737bd4d | 1819 | |
c19d1205 ZW |
1820 | /* New pools, and emptied pools, will have a NULL symbol. */ |
1821 | if (pool->symbol == NULL) | |
a737bd4d | 1822 | { |
c19d1205 ZW |
1823 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
1824 | (valueT) 0, &zero_address_frag); | |
1825 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
1826 | } |
1827 | ||
c19d1205 ZW |
1828 | /* Done. */ |
1829 | return pool; | |
a737bd4d NC |
1830 | } |
1831 | ||
c19d1205 ZW |
1832 | /* Add the literal in the global 'inst' |
1833 | structure to the relevent literal pool. */ | |
b99bd4ef NC |
1834 | |
1835 | static int | |
c19d1205 | 1836 | add_to_lit_pool (void) |
b99bd4ef | 1837 | { |
c19d1205 ZW |
1838 | literal_pool * pool; |
1839 | unsigned int entry; | |
b99bd4ef | 1840 | |
c19d1205 ZW |
1841 | pool = find_or_make_literal_pool (); |
1842 | ||
1843 | /* Check if this literal value is already in the pool. */ | |
1844 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 1845 | { |
c19d1205 ZW |
1846 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) |
1847 | && (inst.reloc.exp.X_op == O_constant) | |
1848 | && (pool->literals[entry].X_add_number | |
1849 | == inst.reloc.exp.X_add_number) | |
1850 | && (pool->literals[entry].X_unsigned | |
1851 | == inst.reloc.exp.X_unsigned)) | |
1852 | break; | |
1853 | ||
1854 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
1855 | && (inst.reloc.exp.X_op == O_symbol) | |
1856 | && (pool->literals[entry].X_add_number | |
1857 | == inst.reloc.exp.X_add_number) | |
1858 | && (pool->literals[entry].X_add_symbol | |
1859 | == inst.reloc.exp.X_add_symbol) | |
1860 | && (pool->literals[entry].X_op_symbol | |
1861 | == inst.reloc.exp.X_op_symbol)) | |
1862 | break; | |
b99bd4ef NC |
1863 | } |
1864 | ||
c19d1205 ZW |
1865 | /* Do we need to create a new entry? */ |
1866 | if (entry == pool->next_free_entry) | |
1867 | { | |
1868 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
1869 | { | |
1870 | inst.error = _("literal pool overflow"); | |
1871 | return FAIL; | |
1872 | } | |
1873 | ||
1874 | pool->literals[entry] = inst.reloc.exp; | |
1875 | pool->next_free_entry += 1; | |
1876 | } | |
b99bd4ef | 1877 | |
c19d1205 ZW |
1878 | inst.reloc.exp.X_op = O_symbol; |
1879 | inst.reloc.exp.X_add_number = ((int) entry) * 4; | |
1880 | inst.reloc.exp.X_add_symbol = pool->symbol; | |
b99bd4ef | 1881 | |
c19d1205 | 1882 | return SUCCESS; |
b99bd4ef NC |
1883 | } |
1884 | ||
c19d1205 ZW |
1885 | /* Can't use symbol_new here, so have to create a symbol and then at |
1886 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 1887 | |
c19d1205 ZW |
1888 | static void |
1889 | symbol_locate (symbolS * symbolP, | |
1890 | const char * name, /* It is copied, the caller can modify. */ | |
1891 | segT segment, /* Segment identifier (SEG_<something>). */ | |
1892 | valueT valu, /* Symbol value. */ | |
1893 | fragS * frag) /* Associated fragment. */ | |
1894 | { | |
1895 | unsigned int name_length; | |
1896 | char * preserved_copy_of_name; | |
e16bb312 | 1897 | |
c19d1205 ZW |
1898 | name_length = strlen (name) + 1; /* +1 for \0. */ |
1899 | obstack_grow (¬es, name, name_length); | |
1900 | preserved_copy_of_name = obstack_finish (¬es); | |
e16bb312 | 1901 | |
c19d1205 ZW |
1902 | #ifdef tc_canonicalize_symbol_name |
1903 | preserved_copy_of_name = | |
1904 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
1905 | #endif | |
b99bd4ef | 1906 | |
c19d1205 | 1907 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 1908 | |
c19d1205 ZW |
1909 | S_SET_SEGMENT (symbolP, segment); |
1910 | S_SET_VALUE (symbolP, valu); | |
1911 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 1912 | |
c19d1205 | 1913 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 1914 | |
c19d1205 ZW |
1915 | /* Link to end of symbol chain. */ |
1916 | { | |
1917 | extern int symbol_table_frozen; | |
b99bd4ef | 1918 | |
c19d1205 ZW |
1919 | if (symbol_table_frozen) |
1920 | abort (); | |
1921 | } | |
b99bd4ef | 1922 | |
c19d1205 | 1923 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 1924 | |
c19d1205 | 1925 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 1926 | |
c19d1205 ZW |
1927 | #ifdef tc_symbol_new_hook |
1928 | tc_symbol_new_hook (symbolP); | |
1929 | #endif | |
1930 | ||
1931 | #ifdef DEBUG_SYMS | |
1932 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
1933 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
1934 | } |
1935 | ||
b99bd4ef | 1936 | |
c19d1205 ZW |
1937 | static void |
1938 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 1939 | { |
c19d1205 ZW |
1940 | unsigned int entry; |
1941 | literal_pool * pool; | |
1942 | char sym_name[20]; | |
b99bd4ef | 1943 | |
c19d1205 ZW |
1944 | pool = find_literal_pool (); |
1945 | if (pool == NULL | |
1946 | || pool->symbol == NULL | |
1947 | || pool->next_free_entry == 0) | |
1948 | return; | |
b99bd4ef | 1949 | |
c19d1205 | 1950 | mapping_state (MAP_DATA); |
b99bd4ef | 1951 | |
c19d1205 ZW |
1952 | /* Align pool as you have word accesses. |
1953 | Only make a frag if we have to. */ | |
1954 | if (!need_pass_2) | |
1955 | frag_align (2, 0, 0); | |
b99bd4ef | 1956 | |
c19d1205 | 1957 | record_alignment (now_seg, 2); |
b99bd4ef | 1958 | |
c19d1205 | 1959 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 1960 | |
c19d1205 ZW |
1961 | symbol_locate (pool->symbol, sym_name, now_seg, |
1962 | (valueT) frag_now_fix (), frag_now); | |
1963 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 1964 | |
c19d1205 | 1965 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 1966 | |
c19d1205 ZW |
1967 | #if defined OBJ_COFF || defined OBJ_ELF |
1968 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
1969 | #endif | |
6c43fab6 | 1970 | |
c19d1205 ZW |
1971 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
1972 | /* First output the expression in the instruction to the pool. */ | |
1973 | emit_expr (&(pool->literals[entry]), 4); /* .word */ | |
b99bd4ef | 1974 | |
c19d1205 ZW |
1975 | /* Mark the pool as empty. */ |
1976 | pool->next_free_entry = 0; | |
1977 | pool->symbol = NULL; | |
b99bd4ef NC |
1978 | } |
1979 | ||
c19d1205 ZW |
1980 | #ifdef OBJ_ELF |
1981 | /* Forward declarations for functions below, in the MD interface | |
1982 | section. */ | |
1983 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
1984 | static valueT create_unwind_entry (int); | |
1985 | static void start_unwind_section (const segT, int); | |
1986 | static void add_unwind_opcode (valueT, int); | |
1987 | static void flush_pending_unwind (void); | |
b99bd4ef | 1988 | |
c19d1205 | 1989 | /* Directives: Data. */ |
b99bd4ef | 1990 | |
c19d1205 ZW |
1991 | static void |
1992 | s_arm_elf_cons (int nbytes) | |
1993 | { | |
1994 | expressionS exp; | |
b99bd4ef | 1995 | |
c19d1205 ZW |
1996 | #ifdef md_flush_pending_output |
1997 | md_flush_pending_output (); | |
1998 | #endif | |
b99bd4ef | 1999 | |
c19d1205 | 2000 | if (is_it_end_of_statement ()) |
b99bd4ef | 2001 | { |
c19d1205 ZW |
2002 | demand_empty_rest_of_line (); |
2003 | return; | |
b99bd4ef NC |
2004 | } |
2005 | ||
c19d1205 ZW |
2006 | #ifdef md_cons_align |
2007 | md_cons_align (nbytes); | |
2008 | #endif | |
b99bd4ef | 2009 | |
c19d1205 ZW |
2010 | mapping_state (MAP_DATA); |
2011 | do | |
b99bd4ef | 2012 | { |
c19d1205 ZW |
2013 | int reloc; |
2014 | char *base = input_line_pointer; | |
b99bd4ef | 2015 | |
c19d1205 | 2016 | expression (& exp); |
b99bd4ef | 2017 | |
c19d1205 ZW |
2018 | if (exp.X_op != O_symbol) |
2019 | emit_expr (&exp, (unsigned int) nbytes); | |
2020 | else | |
2021 | { | |
2022 | char *before_reloc = input_line_pointer; | |
2023 | reloc = parse_reloc (&input_line_pointer); | |
2024 | if (reloc == -1) | |
2025 | { | |
2026 | as_bad (_("unrecognized relocation suffix")); | |
2027 | ignore_rest_of_line (); | |
2028 | return; | |
2029 | } | |
2030 | else if (reloc == BFD_RELOC_UNUSED) | |
2031 | emit_expr (&exp, (unsigned int) nbytes); | |
2032 | else | |
2033 | { | |
2034 | reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc); | |
2035 | int size = bfd_get_reloc_size (howto); | |
b99bd4ef | 2036 | |
2fc8bdac ZW |
2037 | if (reloc == BFD_RELOC_ARM_PLT32) |
2038 | { | |
2039 | as_bad (_("(plt) is only valid on branch targets")); | |
2040 | reloc = BFD_RELOC_UNUSED; | |
2041 | size = 0; | |
2042 | } | |
2043 | ||
c19d1205 | 2044 | if (size > nbytes) |
2fc8bdac | 2045 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
2046 | howto->name, nbytes); |
2047 | else | |
2048 | { | |
2049 | /* We've parsed an expression stopping at O_symbol. | |
2050 | But there may be more expression left now that we | |
2051 | have parsed the relocation marker. Parse it again. | |
2052 | XXX Surely there is a cleaner way to do this. */ | |
2053 | char *p = input_line_pointer; | |
2054 | int offset; | |
2055 | char *save_buf = alloca (input_line_pointer - base); | |
2056 | memcpy (save_buf, base, input_line_pointer - base); | |
2057 | memmove (base + (input_line_pointer - before_reloc), | |
2058 | base, before_reloc - base); | |
2059 | ||
2060 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
2061 | expression (&exp); | |
2062 | memcpy (base, save_buf, p - base); | |
2063 | ||
2064 | offset = nbytes - size; | |
2065 | p = frag_more ((int) nbytes); | |
2066 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, | |
2067 | size, &exp, 0, reloc); | |
2068 | } | |
2069 | } | |
2070 | } | |
b99bd4ef | 2071 | } |
c19d1205 | 2072 | while (*input_line_pointer++ == ','); |
b99bd4ef | 2073 | |
c19d1205 ZW |
2074 | /* Put terminator back into stream. */ |
2075 | input_line_pointer --; | |
2076 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
2077 | } |
2078 | ||
b99bd4ef | 2079 | |
c19d1205 | 2080 | /* Parse a .rel31 directive. */ |
b99bd4ef | 2081 | |
c19d1205 ZW |
2082 | static void |
2083 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
2084 | { | |
2085 | expressionS exp; | |
2086 | char *p; | |
2087 | valueT highbit; | |
b99bd4ef | 2088 | |
c19d1205 ZW |
2089 | highbit = 0; |
2090 | if (*input_line_pointer == '1') | |
2091 | highbit = 0x80000000; | |
2092 | else if (*input_line_pointer != '0') | |
2093 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 2094 | |
c19d1205 ZW |
2095 | input_line_pointer++; |
2096 | if (*input_line_pointer != ',') | |
2097 | as_bad (_("missing comma")); | |
2098 | input_line_pointer++; | |
b99bd4ef | 2099 | |
c19d1205 ZW |
2100 | #ifdef md_flush_pending_output |
2101 | md_flush_pending_output (); | |
2102 | #endif | |
b99bd4ef | 2103 | |
c19d1205 ZW |
2104 | #ifdef md_cons_align |
2105 | md_cons_align (4); | |
2106 | #endif | |
b99bd4ef | 2107 | |
c19d1205 | 2108 | mapping_state (MAP_DATA); |
b99bd4ef | 2109 | |
c19d1205 | 2110 | expression (&exp); |
b99bd4ef | 2111 | |
c19d1205 ZW |
2112 | p = frag_more (4); |
2113 | md_number_to_chars (p, highbit, 4); | |
2114 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
2115 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 2116 | |
c19d1205 | 2117 | demand_empty_rest_of_line (); |
b99bd4ef NC |
2118 | } |
2119 | ||
c19d1205 | 2120 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 2121 | |
c19d1205 | 2122 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 2123 | |
c19d1205 ZW |
2124 | static void |
2125 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
2126 | { | |
2127 | demand_empty_rest_of_line (); | |
2128 | /* Mark the start of the function. */ | |
2129 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 2130 | |
c19d1205 ZW |
2131 | /* Reset the rest of the unwind info. */ |
2132 | unwind.opcode_count = 0; | |
2133 | unwind.table_entry = NULL; | |
2134 | unwind.personality_routine = NULL; | |
2135 | unwind.personality_index = -1; | |
2136 | unwind.frame_size = 0; | |
2137 | unwind.fp_offset = 0; | |
2138 | unwind.fp_reg = 13; | |
2139 | unwind.fp_used = 0; | |
2140 | unwind.sp_restored = 0; | |
2141 | } | |
b99bd4ef | 2142 | |
b99bd4ef | 2143 | |
c19d1205 ZW |
2144 | /* Parse a handlerdata directive. Creates the exception handling table entry |
2145 | for the function. */ | |
b99bd4ef | 2146 | |
c19d1205 ZW |
2147 | static void |
2148 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
2149 | { | |
2150 | demand_empty_rest_of_line (); | |
2151 | if (unwind.table_entry) | |
2152 | as_bad (_("dupicate .handlerdata directive")); | |
f02232aa | 2153 | |
c19d1205 ZW |
2154 | create_unwind_entry (1); |
2155 | } | |
a737bd4d | 2156 | |
c19d1205 | 2157 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 2158 | |
c19d1205 ZW |
2159 | static void |
2160 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
2161 | { | |
2162 | long where; | |
2163 | char *ptr; | |
2164 | valueT val; | |
f02232aa | 2165 | |
c19d1205 | 2166 | demand_empty_rest_of_line (); |
f02232aa | 2167 | |
c19d1205 ZW |
2168 | /* Add eh table entry. */ |
2169 | if (unwind.table_entry == NULL) | |
2170 | val = create_unwind_entry (0); | |
2171 | else | |
2172 | val = 0; | |
f02232aa | 2173 | |
c19d1205 ZW |
2174 | /* Add index table entry. This is two words. */ |
2175 | start_unwind_section (unwind.saved_seg, 1); | |
2176 | frag_align (2, 0, 0); | |
2177 | record_alignment (now_seg, 2); | |
b99bd4ef | 2178 | |
c19d1205 ZW |
2179 | ptr = frag_more (8); |
2180 | where = frag_now_fix () - 8; | |
f02232aa | 2181 | |
c19d1205 ZW |
2182 | /* Self relative offset of the function start. */ |
2183 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
2184 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 2185 | |
c19d1205 ZW |
2186 | /* Indicate dependency on EHABI-defined personality routines to the |
2187 | linker, if it hasn't been done already. */ | |
2188 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 | |
2189 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
2190 | { | |
2191 | static const char *const name[] = { | |
2192 | "__aeabi_unwind_cpp_pr0", | |
2193 | "__aeabi_unwind_cpp_pr1", | |
2194 | "__aeabi_unwind_cpp_pr2" | |
2195 | }; | |
2196 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); | |
2197 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
2198 | marked_pr_dependency |= 1 << unwind.personality_index; | |
2199 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency | |
2200 | = marked_pr_dependency; | |
2201 | } | |
f02232aa | 2202 | |
c19d1205 ZW |
2203 | if (val) |
2204 | /* Inline exception table entry. */ | |
2205 | md_number_to_chars (ptr + 4, val, 4); | |
2206 | else | |
2207 | /* Self relative offset of the table entry. */ | |
2208 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
2209 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 2210 | |
c19d1205 ZW |
2211 | /* Restore the original section. */ |
2212 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
2213 | } | |
f02232aa | 2214 | |
f02232aa | 2215 | |
c19d1205 | 2216 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 2217 | |
c19d1205 ZW |
2218 | static void |
2219 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
2220 | { | |
2221 | demand_empty_rest_of_line (); | |
2222 | if (unwind.personality_routine || unwind.personality_index != -1) | |
2223 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 2224 | |
c19d1205 ZW |
2225 | unwind.personality_index = -2; |
2226 | } | |
b99bd4ef | 2227 | |
b99bd4ef | 2228 | |
c19d1205 | 2229 | /* Parse a personalityindex directive. */ |
b99bd4ef | 2230 | |
c19d1205 ZW |
2231 | static void |
2232 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
2233 | { | |
2234 | expressionS exp; | |
b99bd4ef | 2235 | |
c19d1205 ZW |
2236 | if (unwind.personality_routine || unwind.personality_index != -1) |
2237 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 2238 | |
c19d1205 | 2239 | expression (&exp); |
b99bd4ef | 2240 | |
c19d1205 ZW |
2241 | if (exp.X_op != O_constant |
2242 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 2243 | { |
c19d1205 ZW |
2244 | as_bad (_("bad personality routine number")); |
2245 | ignore_rest_of_line (); | |
2246 | return; | |
b99bd4ef NC |
2247 | } |
2248 | ||
c19d1205 | 2249 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 2250 | |
c19d1205 ZW |
2251 | demand_empty_rest_of_line (); |
2252 | } | |
e16bb312 | 2253 | |
e16bb312 | 2254 | |
c19d1205 | 2255 | /* Parse a personality directive. */ |
e16bb312 | 2256 | |
c19d1205 ZW |
2257 | static void |
2258 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
2259 | { | |
2260 | char *name, *p, c; | |
a737bd4d | 2261 | |
c19d1205 ZW |
2262 | if (unwind.personality_routine || unwind.personality_index != -1) |
2263 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 2264 | |
c19d1205 ZW |
2265 | name = input_line_pointer; |
2266 | c = get_symbol_end (); | |
2267 | p = input_line_pointer; | |
2268 | unwind.personality_routine = symbol_find_or_make (name); | |
2269 | *p = c; | |
2270 | demand_empty_rest_of_line (); | |
2271 | } | |
e16bb312 | 2272 | |
e16bb312 | 2273 | |
c19d1205 | 2274 | /* Parse a directive saving core registers. */ |
e16bb312 | 2275 | |
c19d1205 ZW |
2276 | static void |
2277 | s_arm_unwind_save_core (void) | |
e16bb312 | 2278 | { |
c19d1205 ZW |
2279 | valueT op; |
2280 | long range; | |
2281 | int n; | |
e16bb312 | 2282 | |
c19d1205 ZW |
2283 | range = parse_reg_list (&input_line_pointer); |
2284 | if (range == FAIL) | |
e16bb312 | 2285 | { |
c19d1205 ZW |
2286 | as_bad (_("expected register list")); |
2287 | ignore_rest_of_line (); | |
2288 | return; | |
2289 | } | |
e16bb312 | 2290 | |
c19d1205 | 2291 | demand_empty_rest_of_line (); |
e16bb312 | 2292 | |
c19d1205 ZW |
2293 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
2294 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
2295 | ip because it is clobbered by calls. */ | |
2296 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
2297 | && (range & 0x3000) == 0x1000) | |
2298 | { | |
2299 | unwind.opcode_count--; | |
2300 | unwind.sp_restored = 0; | |
2301 | range = (range | 0x2000) & ~0x1000; | |
2302 | unwind.pending_offset = 0; | |
2303 | } | |
e16bb312 | 2304 | |
01ae4198 DJ |
2305 | /* Pop r4-r15. */ |
2306 | if (range & 0xfff0) | |
c19d1205 | 2307 | { |
01ae4198 DJ |
2308 | /* See if we can use the short opcodes. These pop a block of up to 8 |
2309 | registers starting with r4, plus maybe r14. */ | |
2310 | for (n = 0; n < 8; n++) | |
2311 | { | |
2312 | /* Break at the first non-saved register. */ | |
2313 | if ((range & (1 << (n + 4))) == 0) | |
2314 | break; | |
2315 | } | |
2316 | /* See if there are any other bits set. */ | |
2317 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
2318 | { | |
2319 | /* Use the long form. */ | |
2320 | op = 0x8000 | ((range >> 4) & 0xfff); | |
2321 | add_unwind_opcode (op, 2); | |
2322 | } | |
0dd132b6 | 2323 | else |
01ae4198 DJ |
2324 | { |
2325 | /* Use the short form. */ | |
2326 | if (range & 0x4000) | |
2327 | op = 0xa8; /* Pop r14. */ | |
2328 | else | |
2329 | op = 0xa0; /* Do not pop r14. */ | |
2330 | op |= (n - 1); | |
2331 | add_unwind_opcode (op, 1); | |
2332 | } | |
c19d1205 | 2333 | } |
0dd132b6 | 2334 | |
c19d1205 ZW |
2335 | /* Pop r0-r3. */ |
2336 | if (range & 0xf) | |
2337 | { | |
2338 | op = 0xb100 | (range & 0xf); | |
2339 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
2340 | } |
2341 | ||
c19d1205 ZW |
2342 | /* Record the number of bytes pushed. */ |
2343 | for (n = 0; n < 16; n++) | |
2344 | { | |
2345 | if (range & (1 << n)) | |
2346 | unwind.frame_size += 4; | |
2347 | } | |
0dd132b6 NC |
2348 | } |
2349 | ||
c19d1205 ZW |
2350 | |
2351 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
2352 | |
2353 | static void | |
c19d1205 | 2354 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 2355 | { |
c19d1205 ZW |
2356 | expressionS exp; |
2357 | int num_regs; | |
2358 | valueT op; | |
b99bd4ef | 2359 | |
c19d1205 ZW |
2360 | /* Get Number of registers to transfer. */ |
2361 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
2362 | expression (&exp); | |
2363 | else | |
2364 | exp.X_op = O_illegal; | |
b99bd4ef | 2365 | |
c19d1205 | 2366 | if (exp.X_op != O_constant) |
b99bd4ef | 2367 | { |
c19d1205 ZW |
2368 | as_bad (_("expected , <constant>")); |
2369 | ignore_rest_of_line (); | |
b99bd4ef NC |
2370 | return; |
2371 | } | |
2372 | ||
c19d1205 ZW |
2373 | num_regs = exp.X_add_number; |
2374 | ||
2375 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 2376 | { |
c19d1205 ZW |
2377 | as_bad (_("number of registers must be in the range [1:4]")); |
2378 | ignore_rest_of_line (); | |
b99bd4ef NC |
2379 | return; |
2380 | } | |
2381 | ||
c19d1205 | 2382 | demand_empty_rest_of_line (); |
b99bd4ef | 2383 | |
c19d1205 ZW |
2384 | if (reg == 4) |
2385 | { | |
2386 | /* Short form. */ | |
2387 | op = 0xb4 | (num_regs - 1); | |
2388 | add_unwind_opcode (op, 1); | |
2389 | } | |
b99bd4ef NC |
2390 | else |
2391 | { | |
c19d1205 ZW |
2392 | /* Long form. */ |
2393 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
2394 | add_unwind_opcode (op, 2); | |
b99bd4ef | 2395 | } |
c19d1205 | 2396 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
2397 | } |
2398 | ||
c19d1205 ZW |
2399 | |
2400 | /* Parse a directive saving VFP registers. */ | |
b99bd4ef NC |
2401 | |
2402 | static void | |
c19d1205 | 2403 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 2404 | { |
c19d1205 | 2405 | int count; |
ca3f61f7 | 2406 | unsigned int reg; |
c19d1205 | 2407 | valueT op; |
b99bd4ef | 2408 | |
c19d1205 ZW |
2409 | count = parse_vfp_reg_list (&input_line_pointer, ®, 1); |
2410 | if (count == FAIL) | |
b99bd4ef | 2411 | { |
c19d1205 ZW |
2412 | as_bad (_("expected register list")); |
2413 | ignore_rest_of_line (); | |
b99bd4ef NC |
2414 | return; |
2415 | } | |
2416 | ||
c19d1205 | 2417 | demand_empty_rest_of_line (); |
b99bd4ef | 2418 | |
c19d1205 | 2419 | if (reg == 8) |
b99bd4ef | 2420 | { |
c19d1205 ZW |
2421 | /* Short form. */ |
2422 | op = 0xb8 | (count - 1); | |
2423 | add_unwind_opcode (op, 1); | |
b99bd4ef | 2424 | } |
c19d1205 | 2425 | else |
b99bd4ef | 2426 | { |
c19d1205 ZW |
2427 | /* Long form. */ |
2428 | op = 0xb300 | (reg << 4) | (count - 1); | |
2429 | add_unwind_opcode (op, 2); | |
b99bd4ef | 2430 | } |
c19d1205 ZW |
2431 | unwind.frame_size += count * 8 + 4; |
2432 | } | |
b99bd4ef | 2433 | |
b99bd4ef | 2434 | |
c19d1205 ZW |
2435 | /* Parse a directive saving iWMMXt data registers. */ |
2436 | ||
2437 | static void | |
2438 | s_arm_unwind_save_mmxwr (void) | |
2439 | { | |
2440 | int reg; | |
2441 | int hi_reg; | |
2442 | int i; | |
2443 | unsigned mask = 0; | |
2444 | valueT op; | |
b99bd4ef | 2445 | |
c19d1205 ZW |
2446 | if (*input_line_pointer == '{') |
2447 | input_line_pointer++; | |
b99bd4ef | 2448 | |
c19d1205 | 2449 | do |
b99bd4ef | 2450 | { |
c19d1205 | 2451 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 2452 | |
c19d1205 | 2453 | if (reg == FAIL) |
b99bd4ef | 2454 | { |
c19d1205 ZW |
2455 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); |
2456 | goto error; | |
b99bd4ef NC |
2457 | } |
2458 | ||
c19d1205 ZW |
2459 | if (mask >> reg) |
2460 | as_tsktsk (_("register list not in ascending order")); | |
2461 | mask |= 1 << reg; | |
b99bd4ef | 2462 | |
c19d1205 ZW |
2463 | if (*input_line_pointer == '-') |
2464 | { | |
2465 | input_line_pointer++; | |
2466 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); | |
2467 | if (hi_reg == FAIL) | |
2468 | { | |
2469 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); | |
2470 | goto error; | |
2471 | } | |
2472 | else if (reg >= hi_reg) | |
2473 | { | |
2474 | as_bad (_("bad register range")); | |
2475 | goto error; | |
2476 | } | |
2477 | for (; reg < hi_reg; reg++) | |
2478 | mask |= 1 << reg; | |
2479 | } | |
2480 | } | |
2481 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 2482 | |
c19d1205 ZW |
2483 | if (*input_line_pointer == '}') |
2484 | input_line_pointer++; | |
b99bd4ef | 2485 | |
c19d1205 | 2486 | demand_empty_rest_of_line (); |
b99bd4ef | 2487 | |
c19d1205 ZW |
2488 | /* Generate any deferred opcodes becuuse we're going to be looking at |
2489 | the list. */ | |
2490 | flush_pending_unwind (); | |
b99bd4ef | 2491 | |
c19d1205 | 2492 | for (i = 0; i < 16; i++) |
b99bd4ef | 2493 | { |
c19d1205 ZW |
2494 | if (mask & (1 << i)) |
2495 | unwind.frame_size += 8; | |
b99bd4ef NC |
2496 | } |
2497 | ||
c19d1205 ZW |
2498 | /* Attempt to combine with a previous opcode. We do this because gcc |
2499 | likes to output separate unwind directives for a single block of | |
2500 | registers. */ | |
2501 | if (unwind.opcode_count > 0) | |
b99bd4ef | 2502 | { |
c19d1205 ZW |
2503 | i = unwind.opcodes[unwind.opcode_count - 1]; |
2504 | if ((i & 0xf8) == 0xc0) | |
2505 | { | |
2506 | i &= 7; | |
2507 | /* Only merge if the blocks are contiguous. */ | |
2508 | if (i < 6) | |
2509 | { | |
2510 | if ((mask & 0xfe00) == (1 << 9)) | |
2511 | { | |
2512 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
2513 | unwind.opcode_count--; | |
2514 | } | |
2515 | } | |
2516 | else if (i == 6 && unwind.opcode_count >= 2) | |
2517 | { | |
2518 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
2519 | reg = i >> 4; | |
2520 | i &= 0xf; | |
b99bd4ef | 2521 | |
c19d1205 ZW |
2522 | op = 0xffff << (reg - 1); |
2523 | if (reg > 0 | |
2524 | || ((mask & op) == (1u << (reg - 1)))) | |
2525 | { | |
2526 | op = (1 << (reg + i + 1)) - 1; | |
2527 | op &= ~((1 << reg) - 1); | |
2528 | mask |= op; | |
2529 | unwind.opcode_count -= 2; | |
2530 | } | |
2531 | } | |
2532 | } | |
b99bd4ef NC |
2533 | } |
2534 | ||
c19d1205 ZW |
2535 | hi_reg = 15; |
2536 | /* We want to generate opcodes in the order the registers have been | |
2537 | saved, ie. descending order. */ | |
2538 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 2539 | { |
c19d1205 ZW |
2540 | /* Save registers in blocks. */ |
2541 | if (reg < 0 | |
2542 | || !(mask & (1 << reg))) | |
2543 | { | |
2544 | /* We found an unsaved reg. Generate opcodes to save the | |
2545 | preceeding block. */ | |
2546 | if (reg != hi_reg) | |
2547 | { | |
2548 | if (reg == 9) | |
2549 | { | |
2550 | /* Short form. */ | |
2551 | op = 0xc0 | (hi_reg - 10); | |
2552 | add_unwind_opcode (op, 1); | |
2553 | } | |
2554 | else | |
2555 | { | |
2556 | /* Long form. */ | |
2557 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
2558 | add_unwind_opcode (op, 2); | |
2559 | } | |
2560 | } | |
2561 | hi_reg = reg - 1; | |
2562 | } | |
b99bd4ef NC |
2563 | } |
2564 | ||
c19d1205 ZW |
2565 | return; |
2566 | error: | |
2567 | ignore_rest_of_line (); | |
b99bd4ef NC |
2568 | } |
2569 | ||
2570 | static void | |
c19d1205 | 2571 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 2572 | { |
c19d1205 ZW |
2573 | int reg; |
2574 | int hi_reg; | |
2575 | unsigned mask = 0; | |
2576 | valueT op; | |
b99bd4ef | 2577 | |
c19d1205 ZW |
2578 | if (*input_line_pointer == '{') |
2579 | input_line_pointer++; | |
b99bd4ef | 2580 | |
c19d1205 | 2581 | do |
b99bd4ef | 2582 | { |
c19d1205 | 2583 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 2584 | |
c19d1205 ZW |
2585 | if (reg == FAIL) |
2586 | { | |
2587 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); | |
2588 | goto error; | |
2589 | } | |
b99bd4ef | 2590 | |
c19d1205 ZW |
2591 | reg -= 8; |
2592 | if (mask >> reg) | |
2593 | as_tsktsk (_("register list not in ascending order")); | |
2594 | mask |= 1 << reg; | |
b99bd4ef | 2595 | |
c19d1205 ZW |
2596 | if (*input_line_pointer == '-') |
2597 | { | |
2598 | input_line_pointer++; | |
2599 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); | |
2600 | if (hi_reg == FAIL) | |
2601 | { | |
2602 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); | |
2603 | goto error; | |
2604 | } | |
2605 | else if (reg >= hi_reg) | |
2606 | { | |
2607 | as_bad (_("bad register range")); | |
2608 | goto error; | |
2609 | } | |
2610 | for (; reg < hi_reg; reg++) | |
2611 | mask |= 1 << reg; | |
2612 | } | |
b99bd4ef | 2613 | } |
c19d1205 | 2614 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 2615 | |
c19d1205 ZW |
2616 | if (*input_line_pointer == '}') |
2617 | input_line_pointer++; | |
b99bd4ef | 2618 | |
c19d1205 ZW |
2619 | demand_empty_rest_of_line (); |
2620 | ||
2621 | /* Generate any deferred opcodes becuuse we're going to be looking at | |
2622 | the list. */ | |
2623 | flush_pending_unwind (); | |
b99bd4ef | 2624 | |
c19d1205 | 2625 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 2626 | { |
c19d1205 ZW |
2627 | if (mask & (1 << reg)) |
2628 | unwind.frame_size += 4; | |
b99bd4ef | 2629 | } |
c19d1205 ZW |
2630 | op = 0xc700 | mask; |
2631 | add_unwind_opcode (op, 2); | |
2632 | return; | |
2633 | error: | |
2634 | ignore_rest_of_line (); | |
b99bd4ef NC |
2635 | } |
2636 | ||
c19d1205 ZW |
2637 | |
2638 | /* Parse an unwind_save directive. */ | |
2639 | ||
b99bd4ef | 2640 | static void |
c19d1205 | 2641 | s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED) |
b99bd4ef | 2642 | { |
c19d1205 ZW |
2643 | char *peek; |
2644 | struct reg_entry *reg; | |
2645 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 2646 | |
c19d1205 ZW |
2647 | /* Figure out what sort of save we have. */ |
2648 | peek = input_line_pointer; | |
b99bd4ef | 2649 | |
c19d1205 | 2650 | if (*peek == '{') |
b99bd4ef | 2651 | { |
c19d1205 ZW |
2652 | had_brace = TRUE; |
2653 | peek++; | |
b99bd4ef NC |
2654 | } |
2655 | ||
c19d1205 | 2656 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 2657 | |
c19d1205 | 2658 | if (!reg) |
b99bd4ef | 2659 | { |
c19d1205 ZW |
2660 | as_bad (_("register expected")); |
2661 | ignore_rest_of_line (); | |
b99bd4ef NC |
2662 | return; |
2663 | } | |
2664 | ||
c19d1205 | 2665 | switch (reg->type) |
b99bd4ef | 2666 | { |
c19d1205 ZW |
2667 | case REG_TYPE_FN: |
2668 | if (had_brace) | |
2669 | { | |
2670 | as_bad (_("FPA .unwind_save does not take a register list")); | |
2671 | ignore_rest_of_line (); | |
2672 | return; | |
2673 | } | |
2674 | s_arm_unwind_save_fpa (reg->number); | |
b99bd4ef | 2675 | return; |
c19d1205 ZW |
2676 | |
2677 | case REG_TYPE_RN: s_arm_unwind_save_core (); return; | |
2678 | case REG_TYPE_VFD: s_arm_unwind_save_vfp (); return; | |
2679 | case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; | |
2680 | case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; | |
2681 | ||
2682 | default: | |
2683 | as_bad (_(".unwind_save does not support this kind of register")); | |
2684 | ignore_rest_of_line (); | |
b99bd4ef | 2685 | } |
c19d1205 | 2686 | } |
b99bd4ef | 2687 | |
b99bd4ef | 2688 | |
c19d1205 ZW |
2689 | /* Parse an unwind_movsp directive. */ |
2690 | ||
2691 | static void | |
2692 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
2693 | { | |
2694 | int reg; | |
2695 | valueT op; | |
2696 | ||
2697 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); | |
2698 | if (reg == FAIL) | |
b99bd4ef | 2699 | { |
c19d1205 ZW |
2700 | as_bad (_(reg_expected_msgs[REG_TYPE_RN])); |
2701 | ignore_rest_of_line (); | |
b99bd4ef NC |
2702 | return; |
2703 | } | |
c19d1205 | 2704 | demand_empty_rest_of_line (); |
b99bd4ef | 2705 | |
c19d1205 | 2706 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 2707 | { |
c19d1205 | 2708 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
2709 | return; |
2710 | } | |
2711 | ||
c19d1205 ZW |
2712 | if (unwind.fp_reg != REG_SP) |
2713 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 2714 | |
c19d1205 ZW |
2715 | /* Generate opcode to restore the value. */ |
2716 | op = 0x90 | reg; | |
2717 | add_unwind_opcode (op, 1); | |
2718 | ||
2719 | /* Record the information for later. */ | |
2720 | unwind.fp_reg = reg; | |
2721 | unwind.fp_offset = unwind.frame_size; | |
2722 | unwind.sp_restored = 1; | |
b05fe5cf ZW |
2723 | } |
2724 | ||
c19d1205 ZW |
2725 | /* Parse an unwind_pad directive. */ |
2726 | ||
b05fe5cf | 2727 | static void |
c19d1205 | 2728 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 2729 | { |
c19d1205 | 2730 | int offset; |
b05fe5cf | 2731 | |
c19d1205 ZW |
2732 | if (immediate_for_directive (&offset) == FAIL) |
2733 | return; | |
b99bd4ef | 2734 | |
c19d1205 ZW |
2735 | if (offset & 3) |
2736 | { | |
2737 | as_bad (_("stack increment must be multiple of 4")); | |
2738 | ignore_rest_of_line (); | |
2739 | return; | |
2740 | } | |
b99bd4ef | 2741 | |
c19d1205 ZW |
2742 | /* Don't generate any opcodes, just record the details for later. */ |
2743 | unwind.frame_size += offset; | |
2744 | unwind.pending_offset += offset; | |
2745 | ||
2746 | demand_empty_rest_of_line (); | |
2747 | } | |
2748 | ||
2749 | /* Parse an unwind_setfp directive. */ | |
2750 | ||
2751 | static void | |
2752 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 2753 | { |
c19d1205 ZW |
2754 | int sp_reg; |
2755 | int fp_reg; | |
2756 | int offset; | |
2757 | ||
2758 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); | |
2759 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
2760 | sp_reg = FAIL; | |
2761 | else | |
2762 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); | |
b99bd4ef | 2763 | |
c19d1205 ZW |
2764 | if (fp_reg == FAIL || sp_reg == FAIL) |
2765 | { | |
2766 | as_bad (_("expected <reg>, <reg>")); | |
2767 | ignore_rest_of_line (); | |
2768 | return; | |
2769 | } | |
b99bd4ef | 2770 | |
c19d1205 ZW |
2771 | /* Optional constant. */ |
2772 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
2773 | { | |
2774 | if (immediate_for_directive (&offset) == FAIL) | |
2775 | return; | |
2776 | } | |
2777 | else | |
2778 | offset = 0; | |
a737bd4d | 2779 | |
c19d1205 | 2780 | demand_empty_rest_of_line (); |
a737bd4d | 2781 | |
c19d1205 | 2782 | if (sp_reg != 13 && sp_reg != unwind.fp_reg) |
a737bd4d | 2783 | { |
c19d1205 ZW |
2784 | as_bad (_("register must be either sp or set by a previous" |
2785 | "unwind_movsp directive")); | |
2786 | return; | |
a737bd4d NC |
2787 | } |
2788 | ||
c19d1205 ZW |
2789 | /* Don't generate any opcodes, just record the information for later. */ |
2790 | unwind.fp_reg = fp_reg; | |
2791 | unwind.fp_used = 1; | |
2792 | if (sp_reg == 13) | |
2793 | unwind.fp_offset = unwind.frame_size - offset; | |
2794 | else | |
2795 | unwind.fp_offset -= offset; | |
a737bd4d NC |
2796 | } |
2797 | ||
c19d1205 ZW |
2798 | /* Parse an unwind_raw directive. */ |
2799 | ||
2800 | static void | |
2801 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 2802 | { |
c19d1205 ZW |
2803 | expressionS exp; |
2804 | /* This is an arbitary limit. */ | |
2805 | unsigned char op[16]; | |
2806 | int count; | |
a737bd4d | 2807 | |
c19d1205 ZW |
2808 | expression (&exp); |
2809 | if (exp.X_op == O_constant | |
2810 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 2811 | { |
c19d1205 ZW |
2812 | unwind.frame_size += exp.X_add_number; |
2813 | expression (&exp); | |
2814 | } | |
2815 | else | |
2816 | exp.X_op = O_illegal; | |
a737bd4d | 2817 | |
c19d1205 ZW |
2818 | if (exp.X_op != O_constant) |
2819 | { | |
2820 | as_bad (_("expected <offset>, <opcode>")); | |
2821 | ignore_rest_of_line (); | |
2822 | return; | |
2823 | } | |
a737bd4d | 2824 | |
c19d1205 | 2825 | count = 0; |
a737bd4d | 2826 | |
c19d1205 ZW |
2827 | /* Parse the opcode. */ |
2828 | for (;;) | |
2829 | { | |
2830 | if (count >= 16) | |
2831 | { | |
2832 | as_bad (_("unwind opcode too long")); | |
2833 | ignore_rest_of_line (); | |
a737bd4d | 2834 | } |
c19d1205 | 2835 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 2836 | { |
c19d1205 ZW |
2837 | as_bad (_("invalid unwind opcode")); |
2838 | ignore_rest_of_line (); | |
2839 | return; | |
a737bd4d | 2840 | } |
c19d1205 | 2841 | op[count++] = exp.X_add_number; |
a737bd4d | 2842 | |
c19d1205 ZW |
2843 | /* Parse the next byte. */ |
2844 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
2845 | break; | |
a737bd4d | 2846 | |
c19d1205 ZW |
2847 | expression (&exp); |
2848 | } | |
b99bd4ef | 2849 | |
c19d1205 ZW |
2850 | /* Add the opcode bytes in reverse order. */ |
2851 | while (count--) | |
2852 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 2853 | |
c19d1205 | 2854 | demand_empty_rest_of_line (); |
b99bd4ef | 2855 | } |
ee065d83 PB |
2856 | |
2857 | ||
2858 | /* Parse a .eabi_attribute directive. */ | |
2859 | ||
2860 | static void | |
2861 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
2862 | { | |
2863 | expressionS exp; | |
2864 | bfd_boolean is_string; | |
2865 | int tag; | |
2866 | unsigned int i = 0; | |
2867 | char *s = NULL; | |
2868 | char saved_char; | |
2869 | ||
2870 | expression (& exp); | |
2871 | if (exp.X_op != O_constant) | |
2872 | goto bad; | |
2873 | ||
2874 | tag = exp.X_add_number; | |
2875 | if (tag == 4 || tag == 5 || tag == 32 || (tag > 32 && (tag & 1) != 0)) | |
2876 | is_string = 1; | |
2877 | else | |
2878 | is_string = 0; | |
2879 | ||
2880 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
2881 | goto bad; | |
2882 | if (tag == 32 || !is_string) | |
2883 | { | |
2884 | expression (& exp); | |
2885 | if (exp.X_op != O_constant) | |
2886 | { | |
2887 | as_bad (_("expected numeric constant")); | |
2888 | ignore_rest_of_line (); | |
2889 | return; | |
2890 | } | |
2891 | i = exp.X_add_number; | |
2892 | } | |
2893 | if (tag == Tag_compatibility | |
2894 | && skip_past_comma (&input_line_pointer) == FAIL) | |
2895 | { | |
2896 | as_bad (_("expected comma")); | |
2897 | ignore_rest_of_line (); | |
2898 | return; | |
2899 | } | |
2900 | if (is_string) | |
2901 | { | |
2902 | skip_whitespace(input_line_pointer); | |
2903 | if (*input_line_pointer != '"') | |
2904 | goto bad_string; | |
2905 | input_line_pointer++; | |
2906 | s = input_line_pointer; | |
2907 | while (*input_line_pointer && *input_line_pointer != '"') | |
2908 | input_line_pointer++; | |
2909 | if (*input_line_pointer != '"') | |
2910 | goto bad_string; | |
2911 | saved_char = *input_line_pointer; | |
2912 | *input_line_pointer = 0; | |
2913 | } | |
2914 | else | |
2915 | { | |
2916 | s = NULL; | |
2917 | saved_char = 0; | |
2918 | } | |
2919 | ||
2920 | if (tag == Tag_compatibility) | |
2921 | elf32_arm_add_eabi_attr_compat (stdoutput, i, s); | |
2922 | else if (is_string) | |
2923 | elf32_arm_add_eabi_attr_string (stdoutput, tag, s); | |
2924 | else | |
2925 | elf32_arm_add_eabi_attr_int (stdoutput, tag, i); | |
2926 | ||
2927 | if (s) | |
2928 | { | |
2929 | *input_line_pointer = saved_char; | |
2930 | input_line_pointer++; | |
2931 | } | |
2932 | demand_empty_rest_of_line (); | |
2933 | return; | |
2934 | bad_string: | |
2935 | as_bad (_("bad string constant")); | |
2936 | ignore_rest_of_line (); | |
2937 | return; | |
2938 | bad: | |
2939 | as_bad (_("expected <tag> , <value>")); | |
2940 | ignore_rest_of_line (); | |
2941 | } | |
2942 | ||
2943 | static void s_arm_arch (int); | |
2944 | static void s_arm_cpu (int); | |
2945 | static void s_arm_fpu (int); | |
c19d1205 | 2946 | #endif /* OBJ_ELF */ |
b99bd4ef | 2947 | |
c19d1205 ZW |
2948 | /* This table describes all the machine specific pseudo-ops the assembler |
2949 | has to support. The fields are: | |
2950 | pseudo-op name without dot | |
2951 | function to call to execute this pseudo-op | |
2952 | Integer arg to pass to the function. */ | |
b99bd4ef | 2953 | |
c19d1205 | 2954 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 2955 | { |
c19d1205 ZW |
2956 | /* Never called because '.req' does not start a line. */ |
2957 | { "req", s_req, 0 }, | |
2958 | { "unreq", s_unreq, 0 }, | |
2959 | { "bss", s_bss, 0 }, | |
2960 | { "align", s_align, 0 }, | |
2961 | { "arm", s_arm, 0 }, | |
2962 | { "thumb", s_thumb, 0 }, | |
2963 | { "code", s_code, 0 }, | |
2964 | { "force_thumb", s_force_thumb, 0 }, | |
2965 | { "thumb_func", s_thumb_func, 0 }, | |
2966 | { "thumb_set", s_thumb_set, 0 }, | |
2967 | { "even", s_even, 0 }, | |
2968 | { "ltorg", s_ltorg, 0 }, | |
2969 | { "pool", s_ltorg, 0 }, | |
2970 | { "syntax", s_syntax, 0 }, | |
2971 | #ifdef OBJ_ELF | |
2972 | { "word", s_arm_elf_cons, 4 }, | |
2973 | { "long", s_arm_elf_cons, 4 }, | |
2974 | { "rel31", s_arm_rel31, 0 }, | |
2975 | { "fnstart", s_arm_unwind_fnstart, 0 }, | |
2976 | { "fnend", s_arm_unwind_fnend, 0 }, | |
2977 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
2978 | { "personality", s_arm_unwind_personality, 0 }, | |
2979 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
2980 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
2981 | { "save", s_arm_unwind_save, 0 }, | |
2982 | { "movsp", s_arm_unwind_movsp, 0 }, | |
2983 | { "pad", s_arm_unwind_pad, 0 }, | |
2984 | { "setfp", s_arm_unwind_setfp, 0 }, | |
2985 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 PB |
2986 | { "cpu", s_arm_cpu, 0 }, |
2987 | { "arch", s_arm_arch, 0 }, | |
2988 | { "fpu", s_arm_fpu, 0 }, | |
2989 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, | |
c19d1205 ZW |
2990 | #else |
2991 | { "word", cons, 4}, | |
2992 | #endif | |
2993 | { "extend", float_cons, 'x' }, | |
2994 | { "ldouble", float_cons, 'x' }, | |
2995 | { "packed", float_cons, 'p' }, | |
2996 | { 0, 0, 0 } | |
2997 | }; | |
2998 | \f | |
2999 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 3000 | |
c19d1205 ZW |
3001 | /* Generic immediate-value read function for use in insn parsing. |
3002 | STR points to the beginning of the immediate (the leading #); | |
3003 | VAL receives the value; if the value is outside [MIN, MAX] | |
3004 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
3005 | optional. */ | |
b99bd4ef | 3006 | |
c19d1205 ZW |
3007 | static int |
3008 | parse_immediate (char **str, int *val, int min, int max, | |
3009 | bfd_boolean prefix_opt) | |
3010 | { | |
3011 | expressionS exp; | |
3012 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
3013 | if (exp.X_op != O_constant) | |
b99bd4ef | 3014 | { |
c19d1205 ZW |
3015 | inst.error = _("constant expression required"); |
3016 | return FAIL; | |
3017 | } | |
b99bd4ef | 3018 | |
c19d1205 ZW |
3019 | if (exp.X_add_number < min || exp.X_add_number > max) |
3020 | { | |
3021 | inst.error = _("immediate value out of range"); | |
3022 | return FAIL; | |
3023 | } | |
b99bd4ef | 3024 | |
c19d1205 ZW |
3025 | *val = exp.X_add_number; |
3026 | return SUCCESS; | |
3027 | } | |
b99bd4ef | 3028 | |
c19d1205 ZW |
3029 | /* Returns the pseudo-register number of an FPA immediate constant, |
3030 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 3031 | |
c19d1205 ZW |
3032 | static int |
3033 | parse_fpa_immediate (char ** str) | |
3034 | { | |
3035 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
3036 | char * save_in; | |
3037 | expressionS exp; | |
3038 | int i; | |
3039 | int j; | |
b99bd4ef | 3040 | |
c19d1205 ZW |
3041 | /* First try and match exact strings, this is to guarantee |
3042 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 3043 | |
c19d1205 ZW |
3044 | for (i = 0; fp_const[i]; i++) |
3045 | { | |
3046 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 3047 | { |
c19d1205 | 3048 | char *start = *str; |
b99bd4ef | 3049 | |
c19d1205 ZW |
3050 | *str += strlen (fp_const[i]); |
3051 | if (is_end_of_line[(unsigned char) **str]) | |
3052 | return i + 8; | |
3053 | *str = start; | |
3054 | } | |
3055 | } | |
b99bd4ef | 3056 | |
c19d1205 ZW |
3057 | /* Just because we didn't get a match doesn't mean that the constant |
3058 | isn't valid, just that it is in a format that we don't | |
3059 | automatically recognize. Try parsing it with the standard | |
3060 | expression routines. */ | |
b99bd4ef | 3061 | |
c19d1205 | 3062 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 3063 | |
c19d1205 ZW |
3064 | /* Look for a raw floating point number. */ |
3065 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
3066 | && is_end_of_line[(unsigned char) *save_in]) | |
3067 | { | |
3068 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
3069 | { | |
3070 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 3071 | { |
c19d1205 ZW |
3072 | if (words[j] != fp_values[i][j]) |
3073 | break; | |
b99bd4ef NC |
3074 | } |
3075 | ||
c19d1205 | 3076 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 3077 | { |
c19d1205 ZW |
3078 | *str = save_in; |
3079 | return i + 8; | |
b99bd4ef NC |
3080 | } |
3081 | } | |
3082 | } | |
b99bd4ef | 3083 | |
c19d1205 ZW |
3084 | /* Try and parse a more complex expression, this will probably fail |
3085 | unless the code uses a floating point prefix (eg "0f"). */ | |
3086 | save_in = input_line_pointer; | |
3087 | input_line_pointer = *str; | |
3088 | if (expression (&exp) == absolute_section | |
3089 | && exp.X_op == O_big | |
3090 | && exp.X_add_number < 0) | |
3091 | { | |
3092 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
3093 | Ditto for 15. */ | |
3094 | if (gen_to_words (words, 5, (long) 15) == 0) | |
3095 | { | |
3096 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
3097 | { | |
3098 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
3099 | { | |
3100 | if (words[j] != fp_values[i][j]) | |
3101 | break; | |
3102 | } | |
b99bd4ef | 3103 | |
c19d1205 ZW |
3104 | if (j == MAX_LITTLENUMS) |
3105 | { | |
3106 | *str = input_line_pointer; | |
3107 | input_line_pointer = save_in; | |
3108 | return i + 8; | |
3109 | } | |
3110 | } | |
3111 | } | |
b99bd4ef NC |
3112 | } |
3113 | ||
c19d1205 ZW |
3114 | *str = input_line_pointer; |
3115 | input_line_pointer = save_in; | |
3116 | inst.error = _("invalid FPA immediate expression"); | |
3117 | return FAIL; | |
b99bd4ef NC |
3118 | } |
3119 | ||
c19d1205 ZW |
3120 | /* Shift operands. */ |
3121 | enum shift_kind | |
b99bd4ef | 3122 | { |
c19d1205 ZW |
3123 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
3124 | }; | |
b99bd4ef | 3125 | |
c19d1205 ZW |
3126 | struct asm_shift_name |
3127 | { | |
3128 | const char *name; | |
3129 | enum shift_kind kind; | |
3130 | }; | |
b99bd4ef | 3131 | |
c19d1205 ZW |
3132 | /* Third argument to parse_shift. */ |
3133 | enum parse_shift_mode | |
3134 | { | |
3135 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
3136 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
3137 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
3138 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
3139 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
3140 | }; | |
b99bd4ef | 3141 | |
c19d1205 ZW |
3142 | /* Parse a <shift> specifier on an ARM data processing instruction. |
3143 | This has three forms: | |
b99bd4ef | 3144 | |
c19d1205 ZW |
3145 | (LSL|LSR|ASL|ASR|ROR) Rs |
3146 | (LSL|LSR|ASL|ASR|ROR) #imm | |
3147 | RRX | |
b99bd4ef | 3148 | |
c19d1205 ZW |
3149 | Note that ASL is assimilated to LSL in the instruction encoding, and |
3150 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 3151 | |
c19d1205 ZW |
3152 | static int |
3153 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 3154 | { |
c19d1205 ZW |
3155 | const struct asm_shift_name *shift_name; |
3156 | enum shift_kind shift; | |
3157 | char *s = *str; | |
3158 | char *p = s; | |
3159 | int reg; | |
b99bd4ef | 3160 | |
c19d1205 ZW |
3161 | for (p = *str; ISALPHA (*p); p++) |
3162 | ; | |
b99bd4ef | 3163 | |
c19d1205 | 3164 | if (p == *str) |
b99bd4ef | 3165 | { |
c19d1205 ZW |
3166 | inst.error = _("shift expression expected"); |
3167 | return FAIL; | |
b99bd4ef NC |
3168 | } |
3169 | ||
c19d1205 ZW |
3170 | shift_name = hash_find_n (arm_shift_hsh, *str, p - *str); |
3171 | ||
3172 | if (shift_name == NULL) | |
b99bd4ef | 3173 | { |
c19d1205 ZW |
3174 | inst.error = _("shift expression expected"); |
3175 | return FAIL; | |
b99bd4ef NC |
3176 | } |
3177 | ||
c19d1205 | 3178 | shift = shift_name->kind; |
b99bd4ef | 3179 | |
c19d1205 ZW |
3180 | switch (mode) |
3181 | { | |
3182 | case NO_SHIFT_RESTRICT: | |
3183 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 3184 | |
c19d1205 ZW |
3185 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
3186 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
3187 | { | |
3188 | inst.error = _("'LSL' or 'ASR' required"); | |
3189 | return FAIL; | |
3190 | } | |
3191 | break; | |
b99bd4ef | 3192 | |
c19d1205 ZW |
3193 | case SHIFT_LSL_IMMEDIATE: |
3194 | if (shift != SHIFT_LSL) | |
3195 | { | |
3196 | inst.error = _("'LSL' required"); | |
3197 | return FAIL; | |
3198 | } | |
3199 | break; | |
b99bd4ef | 3200 | |
c19d1205 ZW |
3201 | case SHIFT_ASR_IMMEDIATE: |
3202 | if (shift != SHIFT_ASR) | |
3203 | { | |
3204 | inst.error = _("'ASR' required"); | |
3205 | return FAIL; | |
3206 | } | |
3207 | break; | |
b99bd4ef | 3208 | |
c19d1205 ZW |
3209 | default: abort (); |
3210 | } | |
b99bd4ef | 3211 | |
c19d1205 ZW |
3212 | if (shift != SHIFT_RRX) |
3213 | { | |
3214 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
3215 | skip_whitespace (p); | |
b99bd4ef | 3216 | |
c19d1205 ZW |
3217 | if (mode == NO_SHIFT_RESTRICT |
3218 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) | |
3219 | { | |
3220 | inst.operands[i].imm = reg; | |
3221 | inst.operands[i].immisreg = 1; | |
3222 | } | |
3223 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
3224 | return FAIL; | |
3225 | } | |
3226 | inst.operands[i].shift_kind = shift; | |
3227 | inst.operands[i].shifted = 1; | |
3228 | *str = p; | |
3229 | return SUCCESS; | |
b99bd4ef NC |
3230 | } |
3231 | ||
c19d1205 | 3232 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 3233 | |
c19d1205 ZW |
3234 | #<immediate> |
3235 | #<immediate>, <rotate> | |
3236 | <Rm> | |
3237 | <Rm>, <shift> | |
b99bd4ef | 3238 | |
c19d1205 ZW |
3239 | where <shift> is defined by parse_shift above, and <rotate> is a |
3240 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 3241 | is deferred to md_apply_fix. */ |
b99bd4ef | 3242 | |
c19d1205 ZW |
3243 | static int |
3244 | parse_shifter_operand (char **str, int i) | |
3245 | { | |
3246 | int value; | |
3247 | expressionS expr; | |
b99bd4ef | 3248 | |
c19d1205 ZW |
3249 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
3250 | { | |
3251 | inst.operands[i].reg = value; | |
3252 | inst.operands[i].isreg = 1; | |
b99bd4ef | 3253 | |
c19d1205 ZW |
3254 | /* parse_shift will override this if appropriate */ |
3255 | inst.reloc.exp.X_op = O_constant; | |
3256 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 3257 | |
c19d1205 ZW |
3258 | if (skip_past_comma (str) == FAIL) |
3259 | return SUCCESS; | |
b99bd4ef | 3260 | |
c19d1205 ZW |
3261 | /* Shift operation on register. */ |
3262 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
3263 | } |
3264 | ||
c19d1205 ZW |
3265 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
3266 | return FAIL; | |
b99bd4ef | 3267 | |
c19d1205 | 3268 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 3269 | { |
c19d1205 ZW |
3270 | /* #x, y -- ie explicit rotation by Y. */ |
3271 | if (my_get_expression (&expr, str, GE_NO_PREFIX)) | |
3272 | return FAIL; | |
b99bd4ef | 3273 | |
c19d1205 ZW |
3274 | if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
3275 | { | |
3276 | inst.error = _("constant expression expected"); | |
3277 | return FAIL; | |
3278 | } | |
b99bd4ef | 3279 | |
c19d1205 ZW |
3280 | value = expr.X_add_number; |
3281 | if (value < 0 || value > 30 || value % 2 != 0) | |
3282 | { | |
3283 | inst.error = _("invalid rotation"); | |
3284 | return FAIL; | |
3285 | } | |
3286 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
3287 | { | |
3288 | inst.error = _("invalid constant"); | |
3289 | return FAIL; | |
3290 | } | |
09d92015 | 3291 | |
55cf6793 | 3292 | /* Convert to decoded value. md_apply_fix will put it back. */ |
c19d1205 ZW |
3293 | inst.reloc.exp.X_add_number |
3294 | = (((inst.reloc.exp.X_add_number << (32 - value)) | |
3295 | | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); | |
09d92015 MM |
3296 | } |
3297 | ||
c19d1205 ZW |
3298 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
3299 | inst.reloc.pc_rel = 0; | |
3300 | return SUCCESS; | |
09d92015 MM |
3301 | } |
3302 | ||
c19d1205 ZW |
3303 | /* Parse all forms of an ARM address expression. Information is written |
3304 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 3305 | |
c19d1205 | 3306 | Preindexed addressing (.preind=1): |
09d92015 | 3307 | |
c19d1205 ZW |
3308 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
3309 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
3310 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
3311 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 3312 | |
c19d1205 | 3313 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 3314 | |
c19d1205 | 3315 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 3316 | |
c19d1205 ZW |
3317 | [Rn], #offset .reg=Rn .reloc.exp=offset |
3318 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
3319 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
3320 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 3321 | |
c19d1205 | 3322 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 3323 | |
c19d1205 | 3324 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 3325 | |
c19d1205 | 3326 | Other: |
09d92015 | 3327 | |
c19d1205 ZW |
3328 | [Rn]{!} shorthand for [Rn,#0]{!} |
3329 | =immediate .isreg=0 .reloc.exp=immediate | |
3330 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 3331 | |
c19d1205 ZW |
3332 | It is the caller's responsibility to check for addressing modes not |
3333 | supported by the instruction, and to set inst.reloc.type. */ | |
3334 | ||
3335 | static int | |
3336 | parse_address (char **str, int i) | |
09d92015 | 3337 | { |
c19d1205 ZW |
3338 | char *p = *str; |
3339 | int reg; | |
09d92015 | 3340 | |
c19d1205 | 3341 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 3342 | { |
c19d1205 ZW |
3343 | if (skip_past_char (&p, '=') == FAIL) |
3344 | { | |
3345 | /* bare address - translate to PC-relative offset */ | |
3346 | inst.reloc.pc_rel = 1; | |
3347 | inst.operands[i].reg = REG_PC; | |
3348 | inst.operands[i].isreg = 1; | |
3349 | inst.operands[i].preind = 1; | |
3350 | } | |
3351 | /* else a load-constant pseudo op, no special treatment needed here */ | |
09d92015 | 3352 | |
c19d1205 ZW |
3353 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
3354 | return FAIL; | |
09d92015 | 3355 | |
c19d1205 ZW |
3356 | *str = p; |
3357 | return SUCCESS; | |
09d92015 MM |
3358 | } |
3359 | ||
c19d1205 | 3360 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 3361 | { |
c19d1205 ZW |
3362 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
3363 | return FAIL; | |
09d92015 | 3364 | } |
c19d1205 ZW |
3365 | inst.operands[i].reg = reg; |
3366 | inst.operands[i].isreg = 1; | |
09d92015 | 3367 | |
c19d1205 | 3368 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 3369 | { |
c19d1205 | 3370 | inst.operands[i].preind = 1; |
09d92015 | 3371 | |
c19d1205 ZW |
3372 | if (*p == '+') p++; |
3373 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
3374 | ||
3375 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) | |
09d92015 | 3376 | { |
c19d1205 ZW |
3377 | inst.operands[i].imm = reg; |
3378 | inst.operands[i].immisreg = 1; | |
3379 | ||
3380 | if (skip_past_comma (&p) == SUCCESS) | |
3381 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
3382 | return FAIL; | |
3383 | } | |
3384 | else | |
3385 | { | |
3386 | if (inst.operands[i].negative) | |
3387 | { | |
3388 | inst.operands[i].negative = 0; | |
3389 | p--; | |
3390 | } | |
3391 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
3392 | return FAIL; | |
09d92015 MM |
3393 | } |
3394 | } | |
3395 | ||
c19d1205 | 3396 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 3397 | { |
c19d1205 ZW |
3398 | inst.error = _("']' expected"); |
3399 | return FAIL; | |
09d92015 MM |
3400 | } |
3401 | ||
c19d1205 ZW |
3402 | if (skip_past_char (&p, '!') == SUCCESS) |
3403 | inst.operands[i].writeback = 1; | |
09d92015 | 3404 | |
c19d1205 | 3405 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 3406 | { |
c19d1205 ZW |
3407 | if (skip_past_char (&p, '{') == SUCCESS) |
3408 | { | |
3409 | /* [Rn], {expr} - unindexed, with option */ | |
3410 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 3411 | 0, 255, TRUE) == FAIL) |
c19d1205 | 3412 | return FAIL; |
09d92015 | 3413 | |
c19d1205 ZW |
3414 | if (skip_past_char (&p, '}') == FAIL) |
3415 | { | |
3416 | inst.error = _("'}' expected at end of 'option' field"); | |
3417 | return FAIL; | |
3418 | } | |
3419 | if (inst.operands[i].preind) | |
3420 | { | |
3421 | inst.error = _("cannot combine index with option"); | |
3422 | return FAIL; | |
3423 | } | |
3424 | *str = p; | |
3425 | return SUCCESS; | |
09d92015 | 3426 | } |
c19d1205 ZW |
3427 | else |
3428 | { | |
3429 | inst.operands[i].postind = 1; | |
3430 | inst.operands[i].writeback = 1; | |
09d92015 | 3431 | |
c19d1205 ZW |
3432 | if (inst.operands[i].preind) |
3433 | { | |
3434 | inst.error = _("cannot combine pre- and post-indexing"); | |
3435 | return FAIL; | |
3436 | } | |
09d92015 | 3437 | |
c19d1205 ZW |
3438 | if (*p == '+') p++; |
3439 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 3440 | |
c19d1205 ZW |
3441 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
3442 | { | |
3443 | inst.operands[i].imm = reg; | |
3444 | inst.operands[i].immisreg = 1; | |
a737bd4d | 3445 | |
c19d1205 ZW |
3446 | if (skip_past_comma (&p) == SUCCESS) |
3447 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
3448 | return FAIL; | |
3449 | } | |
3450 | else | |
3451 | { | |
3452 | if (inst.operands[i].negative) | |
3453 | { | |
3454 | inst.operands[i].negative = 0; | |
3455 | p--; | |
3456 | } | |
3457 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
3458 | return FAIL; | |
3459 | } | |
3460 | } | |
a737bd4d NC |
3461 | } |
3462 | ||
c19d1205 ZW |
3463 | /* If at this point neither .preind nor .postind is set, we have a |
3464 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
3465 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
3466 | { | |
3467 | inst.operands[i].preind = 1; | |
3468 | inst.reloc.exp.X_op = O_constant; | |
3469 | inst.reloc.exp.X_add_number = 0; | |
3470 | } | |
3471 | *str = p; | |
3472 | return SUCCESS; | |
a737bd4d NC |
3473 | } |
3474 | ||
c19d1205 | 3475 | /* Miscellaneous. */ |
a737bd4d | 3476 | |
c19d1205 ZW |
3477 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
3478 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
3479 | static int | |
3480 | parse_psr (char **str) | |
09d92015 | 3481 | { |
c19d1205 ZW |
3482 | char *p; |
3483 | unsigned long psr_field; | |
09d92015 | 3484 | |
c19d1205 ZW |
3485 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
3486 | feature for ease of use and backwards compatibility. */ | |
3487 | p = *str; | |
3488 | if (*p == 's' || *p == 'S') | |
3489 | psr_field = SPSR_BIT; | |
3490 | else if (*p == 'c' || *p == 'C') | |
3491 | psr_field = 0; | |
3492 | else | |
3493 | goto error; | |
09d92015 | 3494 | |
c19d1205 ZW |
3495 | p++; |
3496 | if (strncasecmp (p, "PSR", 3) != 0) | |
3497 | goto error; | |
3498 | p += 3; | |
09d92015 | 3499 | |
c19d1205 ZW |
3500 | if (*p == '_') |
3501 | { | |
3502 | /* A suffix follows. */ | |
3503 | const struct asm_psr *psr; | |
3504 | char *start; | |
a737bd4d | 3505 | |
c19d1205 ZW |
3506 | p++; |
3507 | start = p; | |
a737bd4d | 3508 | |
c19d1205 ZW |
3509 | do |
3510 | p++; | |
3511 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 3512 | |
c19d1205 ZW |
3513 | psr = hash_find_n (arm_psr_hsh, start, p - start); |
3514 | if (!psr) | |
3515 | goto error; | |
a737bd4d | 3516 | |
c19d1205 | 3517 | psr_field |= psr->field; |
a737bd4d | 3518 | } |
c19d1205 | 3519 | else |
a737bd4d | 3520 | { |
c19d1205 ZW |
3521 | if (ISALNUM (*p)) |
3522 | goto error; /* Garbage after "[CS]PSR". */ | |
3523 | ||
3524 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 3525 | } |
c19d1205 ZW |
3526 | *str = p; |
3527 | return psr_field; | |
a737bd4d | 3528 | |
c19d1205 ZW |
3529 | error: |
3530 | inst.error = _("flag for {c}psr instruction expected"); | |
3531 | return FAIL; | |
a737bd4d NC |
3532 | } |
3533 | ||
c19d1205 ZW |
3534 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
3535 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 3536 | |
c19d1205 ZW |
3537 | static int |
3538 | parse_cps_flags (char **str) | |
a737bd4d | 3539 | { |
c19d1205 ZW |
3540 | int val = 0; |
3541 | int saw_a_flag = 0; | |
3542 | char *s = *str; | |
a737bd4d | 3543 | |
c19d1205 ZW |
3544 | for (;;) |
3545 | switch (*s++) | |
3546 | { | |
3547 | case '\0': case ',': | |
3548 | goto done; | |
a737bd4d | 3549 | |
c19d1205 ZW |
3550 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
3551 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
3552 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 3553 | |
c19d1205 ZW |
3554 | default: |
3555 | inst.error = _("unrecognized CPS flag"); | |
3556 | return FAIL; | |
3557 | } | |
a737bd4d | 3558 | |
c19d1205 ZW |
3559 | done: |
3560 | if (saw_a_flag == 0) | |
a737bd4d | 3561 | { |
c19d1205 ZW |
3562 | inst.error = _("missing CPS flags"); |
3563 | return FAIL; | |
a737bd4d | 3564 | } |
a737bd4d | 3565 | |
c19d1205 ZW |
3566 | *str = s - 1; |
3567 | return val; | |
a737bd4d NC |
3568 | } |
3569 | ||
c19d1205 ZW |
3570 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
3571 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
3572 | |
3573 | static int | |
c19d1205 | 3574 | parse_endian_specifier (char **str) |
a737bd4d | 3575 | { |
c19d1205 ZW |
3576 | int little_endian; |
3577 | char *s = *str; | |
a737bd4d | 3578 | |
c19d1205 ZW |
3579 | if (strncasecmp (s, "BE", 2)) |
3580 | little_endian = 0; | |
3581 | else if (strncasecmp (s, "LE", 2)) | |
3582 | little_endian = 1; | |
3583 | else | |
a737bd4d | 3584 | { |
c19d1205 | 3585 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
3586 | return FAIL; |
3587 | } | |
3588 | ||
c19d1205 | 3589 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 3590 | { |
c19d1205 | 3591 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
3592 | return FAIL; |
3593 | } | |
3594 | ||
c19d1205 ZW |
3595 | *str = s + 2; |
3596 | return little_endian; | |
3597 | } | |
a737bd4d | 3598 | |
c19d1205 ZW |
3599 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
3600 | value suitable for poking into the rotate field of an sxt or sxta | |
3601 | instruction, or FAIL on error. */ | |
3602 | ||
3603 | static int | |
3604 | parse_ror (char **str) | |
3605 | { | |
3606 | int rot; | |
3607 | char *s = *str; | |
3608 | ||
3609 | if (strncasecmp (s, "ROR", 3) == 0) | |
3610 | s += 3; | |
3611 | else | |
a737bd4d | 3612 | { |
c19d1205 | 3613 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
3614 | return FAIL; |
3615 | } | |
c19d1205 ZW |
3616 | |
3617 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
3618 | return FAIL; | |
3619 | ||
3620 | switch (rot) | |
a737bd4d | 3621 | { |
c19d1205 ZW |
3622 | case 0: *str = s; return 0x0; |
3623 | case 8: *str = s; return 0x1; | |
3624 | case 16: *str = s; return 0x2; | |
3625 | case 24: *str = s; return 0x3; | |
3626 | ||
3627 | default: | |
3628 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
3629 | return FAIL; |
3630 | } | |
c19d1205 | 3631 | } |
a737bd4d | 3632 | |
c19d1205 ZW |
3633 | /* Parse a conditional code (from conds[] below). The value returned is in the |
3634 | range 0 .. 14, or FAIL. */ | |
3635 | static int | |
3636 | parse_cond (char **str) | |
3637 | { | |
3638 | char *p, *q; | |
3639 | const struct asm_cond *c; | |
a737bd4d | 3640 | |
c19d1205 ZW |
3641 | p = q = *str; |
3642 | while (ISALPHA (*q)) | |
3643 | q++; | |
a737bd4d | 3644 | |
c19d1205 ZW |
3645 | c = hash_find_n (arm_cond_hsh, p, q - p); |
3646 | if (!c) | |
a737bd4d | 3647 | { |
c19d1205 | 3648 | inst.error = _("condition required"); |
a737bd4d NC |
3649 | return FAIL; |
3650 | } | |
3651 | ||
c19d1205 ZW |
3652 | *str = q; |
3653 | return c->value; | |
3654 | } | |
3655 | ||
92e90b6e PB |
3656 | /* Parse the operands of a table branch instruction. Similar to a memory |
3657 | operand. */ | |
3658 | static int | |
3659 | parse_tb (char **str) | |
3660 | { | |
3661 | char * p = *str; | |
3662 | int reg; | |
3663 | ||
3664 | if (skip_past_char (&p, '[') == FAIL) | |
3665 | return FAIL; | |
3666 | ||
3667 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) | |
3668 | { | |
3669 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
3670 | return FAIL; | |
3671 | } | |
3672 | inst.operands[0].reg = reg; | |
3673 | ||
3674 | if (skip_past_comma (&p) == FAIL) | |
3675 | return FAIL; | |
3676 | ||
3677 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) | |
3678 | { | |
3679 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
3680 | return FAIL; | |
3681 | } | |
3682 | inst.operands[0].imm = reg; | |
3683 | ||
3684 | if (skip_past_comma (&p) == SUCCESS) | |
3685 | { | |
3686 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
3687 | return FAIL; | |
3688 | if (inst.reloc.exp.X_add_number != 1) | |
3689 | { | |
3690 | inst.error = _("invalid shift"); | |
3691 | return FAIL; | |
3692 | } | |
3693 | inst.operands[0].shifted = 1; | |
3694 | } | |
3695 | ||
3696 | if (skip_past_char (&p, ']') == FAIL) | |
3697 | { | |
3698 | inst.error = _("']' expected"); | |
3699 | return FAIL; | |
3700 | } | |
3701 | *str = p; | |
3702 | return SUCCESS; | |
3703 | } | |
3704 | ||
c19d1205 ZW |
3705 | /* Matcher codes for parse_operands. */ |
3706 | enum operand_parse_code | |
3707 | { | |
3708 | OP_stop, /* end of line */ | |
3709 | ||
3710 | OP_RR, /* ARM register */ | |
3711 | OP_RRnpc, /* ARM register, not r15 */ | |
3712 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ | |
3713 | OP_RRw, /* ARM register, not r15, optional trailing ! */ | |
3714 | OP_RCP, /* Coprocessor number */ | |
3715 | OP_RCN, /* Coprocessor register */ | |
3716 | OP_RF, /* FPA register */ | |
3717 | OP_RVS, /* VFP single precision register */ | |
3718 | OP_RVD, /* VFP double precision register */ | |
3719 | OP_RVC, /* VFP control register */ | |
3720 | OP_RMF, /* Maverick F register */ | |
3721 | OP_RMD, /* Maverick D register */ | |
3722 | OP_RMFX, /* Maverick FX register */ | |
3723 | OP_RMDX, /* Maverick DX register */ | |
3724 | OP_RMAX, /* Maverick AX register */ | |
3725 | OP_RMDS, /* Maverick DSPSC register */ | |
3726 | OP_RIWR, /* iWMMXt wR register */ | |
3727 | OP_RIWC, /* iWMMXt wC register */ | |
3728 | OP_RIWG, /* iWMMXt wCG register */ | |
3729 | OP_RXA, /* XScale accumulator register */ | |
3730 | ||
3731 | OP_REGLST, /* ARM register list */ | |
3732 | OP_VRSLST, /* VFP single-precision register list */ | |
3733 | OP_VRDLST, /* VFP double-precision register list */ | |
3734 | ||
3735 | OP_I7, /* immediate value 0 .. 7 */ | |
3736 | OP_I15, /* 0 .. 15 */ | |
3737 | OP_I16, /* 1 .. 16 */ | |
3738 | OP_I31, /* 0 .. 31 */ | |
3739 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
3740 | OP_I32, /* 1 .. 32 */ | |
3741 | OP_I63s, /* -64 .. 63 */ | |
3742 | OP_I255, /* 0 .. 255 */ | |
3743 | OP_Iffff, /* 0 .. 65535 */ | |
3744 | ||
3745 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
3746 | OP_I7b, /* 0 .. 7 */ | |
3747 | OP_I15b, /* 0 .. 15 */ | |
3748 | OP_I31b, /* 0 .. 31 */ | |
3749 | ||
3750 | OP_SH, /* shifter operand */ | |
3751 | OP_ADDR, /* Memory address expression (any mode) */ | |
3752 | OP_EXP, /* arbitrary expression */ | |
3753 | OP_EXPi, /* same, with optional immediate prefix */ | |
3754 | OP_EXPr, /* same, with optional relocation suffix */ | |
3755 | ||
3756 | OP_CPSF, /* CPS flags */ | |
3757 | OP_ENDI, /* Endianness specifier */ | |
3758 | OP_PSR, /* CPSR/SPSR mask for msr */ | |
3759 | OP_COND, /* conditional code */ | |
92e90b6e | 3760 | OP_TB, /* Table branch. */ |
c19d1205 ZW |
3761 | |
3762 | OP_RRnpc_I0, /* ARM register or literal 0 */ | |
3763 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
3764 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
3765 | OP_RF_IF, /* FPA register or immediate */ | |
3766 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
3767 | ||
3768 | /* Optional operands. */ | |
3769 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
3770 | OP_oI31b, /* 0 .. 31 */ | |
3771 | OP_oIffffb, /* 0 .. 65535 */ | |
3772 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
3773 | ||
3774 | OP_oRR, /* ARM register */ | |
3775 | OP_oRRnpc, /* ARM register, not the PC */ | |
3776 | OP_oSHll, /* LSL immediate */ | |
3777 | OP_oSHar, /* ASR immediate */ | |
3778 | OP_oSHllar, /* LSL or ASR immediate */ | |
3779 | OP_oROR, /* ROR 0/8/16/24 */ | |
3780 | ||
3781 | OP_FIRST_OPTIONAL = OP_oI7b | |
3782 | }; | |
a737bd4d | 3783 | |
c19d1205 ZW |
3784 | /* Generic instruction operand parser. This does no encoding and no |
3785 | semantic validation; it merely squirrels values away in the inst | |
3786 | structure. Returns SUCCESS or FAIL depending on whether the | |
3787 | specified grammar matched. */ | |
3788 | static int | |
ca3f61f7 | 3789 | parse_operands (char *str, const unsigned char *pattern) |
c19d1205 ZW |
3790 | { |
3791 | unsigned const char *upat = pattern; | |
3792 | char *backtrack_pos = 0; | |
3793 | const char *backtrack_error = 0; | |
3794 | int i, val, backtrack_index = 0; | |
3795 | ||
3796 | #define po_char_or_fail(chr) do { \ | |
3797 | if (skip_past_char (&str, chr) == FAIL) \ | |
3798 | goto bad_args; \ | |
3799 | } while (0) | |
3800 | ||
3801 | #define po_reg_or_fail(regtype) do { \ | |
3802 | val = arm_reg_parse (&str, regtype); \ | |
3803 | if (val == FAIL) \ | |
3804 | { \ | |
3805 | inst.error = _(reg_expected_msgs[regtype]); \ | |
3806 | goto failure; \ | |
3807 | } \ | |
3808 | inst.operands[i].reg = val; \ | |
3809 | inst.operands[i].isreg = 1; \ | |
3810 | } while (0) | |
3811 | ||
3812 | #define po_reg_or_goto(regtype, label) do { \ | |
3813 | val = arm_reg_parse (&str, regtype); \ | |
3814 | if (val == FAIL) \ | |
3815 | goto label; \ | |
3816 | \ | |
3817 | inst.operands[i].reg = val; \ | |
3818 | inst.operands[i].isreg = 1; \ | |
3819 | } while (0) | |
3820 | ||
3821 | #define po_imm_or_fail(min, max, popt) do { \ | |
3822 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
3823 | goto failure; \ | |
3824 | inst.operands[i].imm = val; \ | |
3825 | } while (0) | |
3826 | ||
3827 | #define po_misc_or_fail(expr) do { \ | |
3828 | if (expr) \ | |
3829 | goto failure; \ | |
3830 | } while (0) | |
3831 | ||
3832 | skip_whitespace (str); | |
3833 | ||
3834 | for (i = 0; upat[i] != OP_stop; i++) | |
3835 | { | |
3836 | if (upat[i] >= OP_FIRST_OPTIONAL) | |
3837 | { | |
3838 | /* Remember where we are in case we need to backtrack. */ | |
3839 | assert (!backtrack_pos); | |
3840 | backtrack_pos = str; | |
3841 | backtrack_error = inst.error; | |
3842 | backtrack_index = i; | |
3843 | } | |
3844 | ||
3845 | if (i > 0) | |
3846 | po_char_or_fail (','); | |
3847 | ||
3848 | switch (upat[i]) | |
3849 | { | |
3850 | /* Registers */ | |
3851 | case OP_oRRnpc: | |
3852 | case OP_RRnpc: | |
3853 | case OP_oRR: | |
3854 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
3855 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
3856 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
3857 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
3858 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
3859 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
3860 | case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break; | |
3861 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; | |
3862 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
3863 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
3864 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
3865 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
3866 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
3867 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
3868 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
3869 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
3870 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
3871 | ||
3872 | case OP_RRnpcb: | |
3873 | po_char_or_fail ('['); | |
3874 | po_reg_or_fail (REG_TYPE_RN); | |
3875 | po_char_or_fail (']'); | |
3876 | break; | |
a737bd4d | 3877 | |
c19d1205 ZW |
3878 | case OP_RRw: |
3879 | po_reg_or_fail (REG_TYPE_RN); | |
3880 | if (skip_past_char (&str, '!') == SUCCESS) | |
3881 | inst.operands[i].writeback = 1; | |
3882 | break; | |
3883 | ||
3884 | /* Immediates */ | |
3885 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
3886 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
3887 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
3888 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; | |
3889 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
3890 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; | |
3891 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; | |
3892 | case OP_Iffff: po_imm_or_fail ( 0, 0xffff, FALSE); break; | |
3893 | ||
3894 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
3895 | case OP_oI7b: | |
3896 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
3897 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
3898 | case OP_oI31b: | |
3899 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
3900 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; | |
3901 | ||
3902 | /* Immediate variants */ | |
3903 | case OP_oI255c: | |
3904 | po_char_or_fail ('{'); | |
3905 | po_imm_or_fail (0, 255, TRUE); | |
3906 | po_char_or_fail ('}'); | |
3907 | break; | |
3908 | ||
3909 | case OP_I31w: | |
3910 | /* The expression parser chokes on a trailing !, so we have | |
3911 | to find it first and zap it. */ | |
3912 | { | |
3913 | char *s = str; | |
3914 | while (*s && *s != ',') | |
3915 | s++; | |
3916 | if (s[-1] == '!') | |
3917 | { | |
3918 | s[-1] = '\0'; | |
3919 | inst.operands[i].writeback = 1; | |
3920 | } | |
3921 | po_imm_or_fail (0, 31, TRUE); | |
3922 | if (str == s - 1) | |
3923 | str = s; | |
3924 | } | |
3925 | break; | |
3926 | ||
3927 | /* Expressions */ | |
3928 | case OP_EXPi: EXPi: | |
3929 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
3930 | GE_OPT_PREFIX)); | |
3931 | break; | |
3932 | ||
3933 | case OP_EXP: | |
3934 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
3935 | GE_NO_PREFIX)); | |
3936 | break; | |
3937 | ||
3938 | case OP_EXPr: EXPr: | |
3939 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
3940 | GE_NO_PREFIX)); | |
3941 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 3942 | { |
c19d1205 ZW |
3943 | val = parse_reloc (&str); |
3944 | if (val == -1) | |
3945 | { | |
3946 | inst.error = _("unrecognized relocation suffix"); | |
3947 | goto failure; | |
3948 | } | |
3949 | else if (val != BFD_RELOC_UNUSED) | |
3950 | { | |
3951 | inst.operands[i].imm = val; | |
3952 | inst.operands[i].hasreloc = 1; | |
3953 | } | |
a737bd4d | 3954 | } |
c19d1205 | 3955 | break; |
a737bd4d | 3956 | |
c19d1205 ZW |
3957 | /* Register or expression */ |
3958 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; | |
3959 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 3960 | |
c19d1205 ZW |
3961 | /* Register or immediate */ |
3962 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; | |
3963 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 3964 | |
c19d1205 ZW |
3965 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
3966 | IF: | |
3967 | if (!is_immediate_prefix (*str)) | |
3968 | goto bad_args; | |
3969 | str++; | |
3970 | val = parse_fpa_immediate (&str); | |
3971 | if (val == FAIL) | |
3972 | goto failure; | |
3973 | /* FPA immediates are encoded as registers 8-15. | |
3974 | parse_fpa_immediate has already applied the offset. */ | |
3975 | inst.operands[i].reg = val; | |
3976 | inst.operands[i].isreg = 1; | |
3977 | break; | |
09d92015 | 3978 | |
c19d1205 ZW |
3979 | /* Two kinds of register */ |
3980 | case OP_RIWR_RIWC: | |
3981 | { | |
3982 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
3983 | if (rege->type != REG_TYPE_MMXWR | |
3984 | && rege->type != REG_TYPE_MMXWC | |
3985 | && rege->type != REG_TYPE_MMXWCG) | |
3986 | { | |
3987 | inst.error = _("iWMMXt data or control register expected"); | |
3988 | goto failure; | |
3989 | } | |
3990 | inst.operands[i].reg = rege->number; | |
3991 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
3992 | } | |
3993 | break; | |
09d92015 | 3994 | |
c19d1205 ZW |
3995 | /* Misc */ |
3996 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
3997 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
3998 | case OP_oROR: val = parse_ror (&str); break; | |
3999 | case OP_PSR: val = parse_psr (&str); break; | |
4000 | case OP_COND: val = parse_cond (&str); break; | |
4001 | ||
92e90b6e PB |
4002 | case OP_TB: |
4003 | po_misc_or_fail (parse_tb (&str)); | |
4004 | break; | |
4005 | ||
c19d1205 ZW |
4006 | /* Register lists */ |
4007 | case OP_REGLST: | |
4008 | val = parse_reg_list (&str); | |
4009 | if (*str == '^') | |
4010 | { | |
4011 | inst.operands[1].writeback = 1; | |
4012 | str++; | |
4013 | } | |
4014 | break; | |
09d92015 | 4015 | |
c19d1205 ZW |
4016 | case OP_VRSLST: |
4017 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 0); | |
4018 | break; | |
09d92015 | 4019 | |
c19d1205 ZW |
4020 | case OP_VRDLST: |
4021 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 1); | |
4022 | break; | |
a737bd4d | 4023 | |
c19d1205 ZW |
4024 | /* Addressing modes */ |
4025 | case OP_ADDR: | |
4026 | po_misc_or_fail (parse_address (&str, i)); | |
4027 | break; | |
09d92015 | 4028 | |
c19d1205 ZW |
4029 | case OP_SH: |
4030 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
4031 | break; | |
09d92015 | 4032 | |
c19d1205 ZW |
4033 | case OP_oSHll: |
4034 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
4035 | break; | |
09d92015 | 4036 | |
c19d1205 ZW |
4037 | case OP_oSHar: |
4038 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
4039 | break; | |
09d92015 | 4040 | |
c19d1205 ZW |
4041 | case OP_oSHllar: |
4042 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
4043 | break; | |
09d92015 | 4044 | |
c19d1205 ZW |
4045 | default: |
4046 | as_fatal ("unhandled operand code %d", upat[i]); | |
4047 | } | |
09d92015 | 4048 | |
c19d1205 ZW |
4049 | /* Various value-based sanity checks and shared operations. We |
4050 | do not signal immediate failures for the register constraints; | |
4051 | this allows a syntax error to take precedence. */ | |
4052 | switch (upat[i]) | |
4053 | { | |
4054 | case OP_oRRnpc: | |
4055 | case OP_RRnpc: | |
4056 | case OP_RRnpcb: | |
4057 | case OP_RRw: | |
4058 | case OP_RRnpc_I0: | |
4059 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
4060 | inst.error = BAD_PC; | |
4061 | break; | |
09d92015 | 4062 | |
c19d1205 ZW |
4063 | case OP_CPSF: |
4064 | case OP_ENDI: | |
4065 | case OP_oROR: | |
4066 | case OP_PSR: | |
4067 | case OP_COND: | |
4068 | case OP_REGLST: | |
4069 | case OP_VRSLST: | |
4070 | case OP_VRDLST: | |
4071 | if (val == FAIL) | |
4072 | goto failure; | |
4073 | inst.operands[i].imm = val; | |
4074 | break; | |
a737bd4d | 4075 | |
c19d1205 ZW |
4076 | default: |
4077 | break; | |
4078 | } | |
09d92015 | 4079 | |
c19d1205 ZW |
4080 | /* If we get here, this operand was successfully parsed. */ |
4081 | inst.operands[i].present = 1; | |
4082 | continue; | |
09d92015 | 4083 | |
c19d1205 | 4084 | bad_args: |
09d92015 | 4085 | inst.error = BAD_ARGS; |
c19d1205 ZW |
4086 | |
4087 | failure: | |
4088 | if (!backtrack_pos) | |
4089 | return FAIL; | |
4090 | ||
4091 | /* Do not backtrack over a trailing optional argument that | |
4092 | absorbed some text. We will only fail again, with the | |
4093 | 'garbage following instruction' error message, which is | |
4094 | probably less helpful than the current one. */ | |
4095 | if (backtrack_index == i && backtrack_pos != str | |
4096 | && upat[i+1] == OP_stop) | |
4097 | return FAIL; | |
4098 | ||
4099 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
4100 | str = backtrack_pos; | |
4101 | inst.error = backtrack_error; | |
4102 | inst.operands[backtrack_index].present = 0; | |
4103 | i = backtrack_index; | |
4104 | backtrack_pos = 0; | |
09d92015 | 4105 | } |
09d92015 | 4106 | |
c19d1205 ZW |
4107 | /* Check that we have parsed all the arguments. */ |
4108 | if (*str != '\0' && !inst.error) | |
4109 | inst.error = _("garbage following instruction"); | |
09d92015 | 4110 | |
c19d1205 | 4111 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
4112 | } |
4113 | ||
c19d1205 ZW |
4114 | #undef po_char_or_fail |
4115 | #undef po_reg_or_fail | |
4116 | #undef po_reg_or_goto | |
4117 | #undef po_imm_or_fail | |
4118 | \f | |
4119 | /* Shorthand macro for instruction encoding functions issuing errors. */ | |
4120 | #define constraint(expr, err) do { \ | |
4121 | if (expr) \ | |
4122 | { \ | |
4123 | inst.error = err; \ | |
4124 | return; \ | |
4125 | } \ | |
4126 | } while (0) | |
4127 | ||
4128 | /* Functions for operand encoding. ARM, then Thumb. */ | |
4129 | ||
4130 | #define rotate_left(v, n) (v << n | v >> (32 - n)) | |
4131 | ||
4132 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
4133 | return the encoded form. Otherwise, return FAIL. */ | |
4134 | ||
4135 | static unsigned int | |
4136 | encode_arm_immediate (unsigned int val) | |
09d92015 | 4137 | { |
c19d1205 ZW |
4138 | unsigned int a, i; |
4139 | ||
4140 | for (i = 0; i < 32; i += 2) | |
4141 | if ((a = rotate_left (val, i)) <= 0xff) | |
4142 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
4143 | ||
4144 | return FAIL; | |
09d92015 MM |
4145 | } |
4146 | ||
c19d1205 ZW |
4147 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
4148 | return the encoded form. Otherwise, return FAIL. */ | |
4149 | static unsigned int | |
4150 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 4151 | { |
c19d1205 | 4152 | unsigned int a, i; |
09d92015 | 4153 | |
9c3c69f2 | 4154 | if (val <= 0xff) |
c19d1205 | 4155 | return val; |
a737bd4d | 4156 | |
9c3c69f2 | 4157 | for (i = 1; i <= 24; i++) |
09d92015 | 4158 | { |
9c3c69f2 PB |
4159 | a = val >> i; |
4160 | if ((val & ~(0xff << i)) == 0) | |
4161 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 4162 | } |
a737bd4d | 4163 | |
c19d1205 ZW |
4164 | a = val & 0xff; |
4165 | if (val == ((a << 16) | a)) | |
4166 | return 0x100 | a; | |
4167 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
4168 | return 0x300 | a; | |
09d92015 | 4169 | |
c19d1205 ZW |
4170 | a = val & 0xff00; |
4171 | if (val == ((a << 16) | a)) | |
4172 | return 0x200 | (a >> 8); | |
a737bd4d | 4173 | |
c19d1205 | 4174 | return FAIL; |
09d92015 | 4175 | } |
c19d1205 | 4176 | /* Encode a VFP SP register number into inst.instruction. */ |
09d92015 MM |
4177 | |
4178 | static void | |
c19d1205 | 4179 | encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos) |
09d92015 | 4180 | { |
c19d1205 | 4181 | switch (pos) |
09d92015 | 4182 | { |
c19d1205 ZW |
4183 | case VFP_REG_Sd: |
4184 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
4185 | break; | |
4186 | ||
4187 | case VFP_REG_Sn: | |
4188 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
4189 | break; | |
4190 | ||
4191 | case VFP_REG_Sm: | |
4192 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
4193 | break; | |
4194 | ||
4195 | default: | |
4196 | abort (); | |
09d92015 | 4197 | } |
09d92015 MM |
4198 | } |
4199 | ||
c19d1205 | 4200 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 4201 | if any, is handled by md_apply_fix. */ |
09d92015 | 4202 | static void |
c19d1205 | 4203 | encode_arm_shift (int i) |
09d92015 | 4204 | { |
c19d1205 ZW |
4205 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
4206 | inst.instruction |= SHIFT_ROR << 5; | |
4207 | else | |
09d92015 | 4208 | { |
c19d1205 ZW |
4209 | inst.instruction |= inst.operands[i].shift_kind << 5; |
4210 | if (inst.operands[i].immisreg) | |
4211 | { | |
4212 | inst.instruction |= SHIFT_BY_REG; | |
4213 | inst.instruction |= inst.operands[i].imm << 8; | |
4214 | } | |
4215 | else | |
4216 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 4217 | } |
c19d1205 | 4218 | } |
09d92015 | 4219 | |
c19d1205 ZW |
4220 | static void |
4221 | encode_arm_shifter_operand (int i) | |
4222 | { | |
4223 | if (inst.operands[i].isreg) | |
09d92015 | 4224 | { |
c19d1205 ZW |
4225 | inst.instruction |= inst.operands[i].reg; |
4226 | encode_arm_shift (i); | |
09d92015 | 4227 | } |
c19d1205 ZW |
4228 | else |
4229 | inst.instruction |= INST_IMMEDIATE; | |
09d92015 MM |
4230 | } |
4231 | ||
c19d1205 | 4232 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 4233 | static void |
c19d1205 | 4234 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 4235 | { |
c19d1205 ZW |
4236 | assert (inst.operands[i].isreg); |
4237 | inst.instruction |= inst.operands[i].reg << 16; | |
a737bd4d | 4238 | |
c19d1205 | 4239 | if (inst.operands[i].preind) |
09d92015 | 4240 | { |
c19d1205 ZW |
4241 | if (is_t) |
4242 | { | |
4243 | inst.error = _("instruction does not accept preindexed addressing"); | |
4244 | return; | |
4245 | } | |
4246 | inst.instruction |= PRE_INDEX; | |
4247 | if (inst.operands[i].writeback) | |
4248 | inst.instruction |= WRITE_BACK; | |
09d92015 | 4249 | |
c19d1205 ZW |
4250 | } |
4251 | else if (inst.operands[i].postind) | |
4252 | { | |
4253 | assert (inst.operands[i].writeback); | |
4254 | if (is_t) | |
4255 | inst.instruction |= WRITE_BACK; | |
4256 | } | |
4257 | else /* unindexed - only for coprocessor */ | |
09d92015 | 4258 | { |
c19d1205 | 4259 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
4260 | return; |
4261 | } | |
4262 | ||
c19d1205 ZW |
4263 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
4264 | && (((inst.instruction & 0x000f0000) >> 16) | |
4265 | == ((inst.instruction & 0x0000f000) >> 12))) | |
4266 | as_warn ((inst.instruction & LOAD_BIT) | |
4267 | ? _("destination register same as write-back base") | |
4268 | : _("source register same as write-back base")); | |
09d92015 MM |
4269 | } |
4270 | ||
c19d1205 ZW |
4271 | /* inst.operands[i] was set up by parse_address. Encode it into an |
4272 | ARM-format mode 2 load or store instruction. If is_t is true, | |
4273 | reject forms that cannot be used with a T instruction (i.e. not | |
4274 | post-indexed). */ | |
a737bd4d | 4275 | static void |
c19d1205 | 4276 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 4277 | { |
c19d1205 | 4278 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 4279 | |
c19d1205 | 4280 | if (inst.operands[i].immisreg) |
09d92015 | 4281 | { |
c19d1205 ZW |
4282 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
4283 | inst.instruction |= inst.operands[i].imm; | |
4284 | if (!inst.operands[i].negative) | |
4285 | inst.instruction |= INDEX_UP; | |
4286 | if (inst.operands[i].shifted) | |
4287 | { | |
4288 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
4289 | inst.instruction |= SHIFT_ROR << 5; | |
4290 | else | |
4291 | { | |
4292 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
4293 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
4294 | } | |
4295 | } | |
09d92015 | 4296 | } |
c19d1205 | 4297 | else /* immediate offset in inst.reloc */ |
09d92015 | 4298 | { |
c19d1205 ZW |
4299 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
4300 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
09d92015 | 4301 | } |
09d92015 MM |
4302 | } |
4303 | ||
c19d1205 ZW |
4304 | /* inst.operands[i] was set up by parse_address. Encode it into an |
4305 | ARM-format mode 3 load or store instruction. Reject forms that | |
4306 | cannot be used with such instructions. If is_t is true, reject | |
4307 | forms that cannot be used with a T instruction (i.e. not | |
4308 | post-indexed). */ | |
4309 | static void | |
4310 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 4311 | { |
c19d1205 | 4312 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 4313 | { |
c19d1205 ZW |
4314 | inst.error = _("instruction does not accept scaled register index"); |
4315 | return; | |
09d92015 | 4316 | } |
a737bd4d | 4317 | |
c19d1205 | 4318 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 4319 | |
c19d1205 ZW |
4320 | if (inst.operands[i].immisreg) |
4321 | { | |
4322 | inst.instruction |= inst.operands[i].imm; | |
4323 | if (!inst.operands[i].negative) | |
4324 | inst.instruction |= INDEX_UP; | |
4325 | } | |
4326 | else /* immediate offset in inst.reloc */ | |
4327 | { | |
4328 | inst.instruction |= HWOFFSET_IMM; | |
4329 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
4330 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
c19d1205 | 4331 | } |
a737bd4d NC |
4332 | } |
4333 | ||
c19d1205 ZW |
4334 | /* inst.operands[i] was set up by parse_address. Encode it into an |
4335 | ARM-format instruction. Reject all forms which cannot be encoded | |
4336 | into a coprocessor load/store instruction. If wb_ok is false, | |
4337 | reject use of writeback; if unind_ok is false, reject use of | |
4338 | unindexed addressing. If reloc_override is not 0, use it instead | |
4339 | of BFD_ARM_CP_OFF_IMM. */ | |
09d92015 | 4340 | |
c19d1205 ZW |
4341 | static int |
4342 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
09d92015 | 4343 | { |
c19d1205 | 4344 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 4345 | |
c19d1205 | 4346 | assert (!(inst.operands[i].preind && inst.operands[i].postind)); |
09d92015 | 4347 | |
c19d1205 | 4348 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ |
09d92015 | 4349 | { |
c19d1205 ZW |
4350 | assert (!inst.operands[i].writeback); |
4351 | if (!unind_ok) | |
4352 | { | |
4353 | inst.error = _("instruction does not support unindexed addressing"); | |
4354 | return FAIL; | |
4355 | } | |
4356 | inst.instruction |= inst.operands[i].imm; | |
4357 | inst.instruction |= INDEX_UP; | |
4358 | return SUCCESS; | |
09d92015 | 4359 | } |
a737bd4d | 4360 | |
c19d1205 ZW |
4361 | if (inst.operands[i].preind) |
4362 | inst.instruction |= PRE_INDEX; | |
a737bd4d | 4363 | |
c19d1205 | 4364 | if (inst.operands[i].writeback) |
09d92015 | 4365 | { |
c19d1205 ZW |
4366 | if (inst.operands[i].reg == REG_PC) |
4367 | { | |
4368 | inst.error = _("pc may not be used with write-back"); | |
4369 | return FAIL; | |
4370 | } | |
4371 | if (!wb_ok) | |
4372 | { | |
4373 | inst.error = _("instruction does not support writeback"); | |
4374 | return FAIL; | |
4375 | } | |
4376 | inst.instruction |= WRITE_BACK; | |
09d92015 | 4377 | } |
a737bd4d | 4378 | |
c19d1205 ZW |
4379 | if (reloc_override) |
4380 | inst.reloc.type = reloc_override; | |
8f06b2d8 PB |
4381 | else if (thumb_mode) |
4382 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
09d92015 | 4383 | else |
c19d1205 | 4384 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; |
c19d1205 ZW |
4385 | return SUCCESS; |
4386 | } | |
a737bd4d | 4387 | |
c19d1205 ZW |
4388 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
4389 | Determine whether it can be performed with a move instruction; if | |
4390 | it can, convert inst.instruction to that move instruction and | |
4391 | return 1; if it can't, convert inst.instruction to a literal-pool | |
4392 | load and return 0. If this is not a valid thing to do in the | |
4393 | current context, set inst.error and return 1. | |
a737bd4d | 4394 | |
c19d1205 ZW |
4395 | inst.operands[i] describes the destination register. */ |
4396 | ||
4397 | static int | |
4398 | move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) | |
4399 | { | |
4400 | if ((inst.instruction & (thumb_p ? THUMB_LOAD_BIT : LOAD_BIT)) == 0) | |
09d92015 | 4401 | { |
c19d1205 ZW |
4402 | inst.error = _("invalid pseudo operation"); |
4403 | return 1; | |
09d92015 | 4404 | } |
c19d1205 | 4405 | if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) |
09d92015 MM |
4406 | { |
4407 | inst.error = _("constant expression expected"); | |
c19d1205 | 4408 | return 1; |
09d92015 | 4409 | } |
c19d1205 | 4410 | if (inst.reloc.exp.X_op == O_constant) |
09d92015 | 4411 | { |
c19d1205 ZW |
4412 | if (thumb_p) |
4413 | { | |
4414 | if ((inst.reloc.exp.X_add_number & ~0xFF) == 0) | |
4415 | { | |
4416 | /* This can be done with a mov(1) instruction. */ | |
4417 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
4418 | inst.instruction |= inst.reloc.exp.X_add_number; | |
4419 | return 1; | |
4420 | } | |
4421 | } | |
4422 | else | |
4423 | { | |
4424 | int value = encode_arm_immediate (inst.reloc.exp.X_add_number); | |
4425 | if (value != FAIL) | |
4426 | { | |
4427 | /* This can be done with a mov instruction. */ | |
4428 | inst.instruction &= LITERAL_MASK; | |
4429 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
4430 | inst.instruction |= value & 0xfff; | |
4431 | return 1; | |
4432 | } | |
09d92015 | 4433 | |
c19d1205 ZW |
4434 | value = encode_arm_immediate (~inst.reloc.exp.X_add_number); |
4435 | if (value != FAIL) | |
4436 | { | |
4437 | /* This can be done with a mvn instruction. */ | |
4438 | inst.instruction &= LITERAL_MASK; | |
4439 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
4440 | inst.instruction |= value & 0xfff; | |
4441 | return 1; | |
4442 | } | |
4443 | } | |
09d92015 MM |
4444 | } |
4445 | ||
c19d1205 ZW |
4446 | if (add_to_lit_pool () == FAIL) |
4447 | { | |
4448 | inst.error = _("literal pool insertion failed"); | |
4449 | return 1; | |
4450 | } | |
4451 | inst.operands[1].reg = REG_PC; | |
4452 | inst.operands[1].isreg = 1; | |
4453 | inst.operands[1].preind = 1; | |
4454 | inst.reloc.pc_rel = 1; | |
4455 | inst.reloc.type = (thumb_p | |
4456 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
4457 | : (mode_3 | |
4458 | ? BFD_RELOC_ARM_HWLITERAL | |
4459 | : BFD_RELOC_ARM_LITERAL)); | |
4460 | return 0; | |
09d92015 MM |
4461 | } |
4462 | ||
c19d1205 ZW |
4463 | /* Functions for instruction encoding, sorted by subarchitecture. |
4464 | First some generics; their names are taken from the conventional | |
4465 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 4466 | |
a737bd4d | 4467 | static void |
c19d1205 | 4468 | do_noargs (void) |
09d92015 | 4469 | { |
c19d1205 | 4470 | } |
a737bd4d | 4471 | |
c19d1205 ZW |
4472 | static void |
4473 | do_rd (void) | |
4474 | { | |
4475 | inst.instruction |= inst.operands[0].reg << 12; | |
4476 | } | |
a737bd4d | 4477 | |
c19d1205 ZW |
4478 | static void |
4479 | do_rd_rm (void) | |
4480 | { | |
4481 | inst.instruction |= inst.operands[0].reg << 12; | |
4482 | inst.instruction |= inst.operands[1].reg; | |
4483 | } | |
09d92015 | 4484 | |
c19d1205 ZW |
4485 | static void |
4486 | do_rd_rn (void) | |
4487 | { | |
4488 | inst.instruction |= inst.operands[0].reg << 12; | |
4489 | inst.instruction |= inst.operands[1].reg << 16; | |
4490 | } | |
a737bd4d | 4491 | |
c19d1205 ZW |
4492 | static void |
4493 | do_rn_rd (void) | |
4494 | { | |
4495 | inst.instruction |= inst.operands[0].reg << 16; | |
4496 | inst.instruction |= inst.operands[1].reg << 12; | |
4497 | } | |
09d92015 | 4498 | |
c19d1205 ZW |
4499 | static void |
4500 | do_rd_rm_rn (void) | |
4501 | { | |
9a64e435 PB |
4502 | unsigned Rn = inst.operands[2].reg; |
4503 | /* Enforce resutrictions on SWP instruction. */ | |
4504 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) | |
4505 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
4506 | _("Rn must not overlap other operands")); | |
c19d1205 ZW |
4507 | inst.instruction |= inst.operands[0].reg << 12; |
4508 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 4509 | inst.instruction |= Rn << 16; |
c19d1205 | 4510 | } |
09d92015 | 4511 | |
c19d1205 ZW |
4512 | static void |
4513 | do_rd_rn_rm (void) | |
4514 | { | |
4515 | inst.instruction |= inst.operands[0].reg << 12; | |
4516 | inst.instruction |= inst.operands[1].reg << 16; | |
4517 | inst.instruction |= inst.operands[2].reg; | |
4518 | } | |
a737bd4d | 4519 | |
c19d1205 ZW |
4520 | static void |
4521 | do_rm_rd_rn (void) | |
4522 | { | |
4523 | inst.instruction |= inst.operands[0].reg; | |
4524 | inst.instruction |= inst.operands[1].reg << 12; | |
4525 | inst.instruction |= inst.operands[2].reg << 16; | |
4526 | } | |
09d92015 | 4527 | |
c19d1205 ZW |
4528 | static void |
4529 | do_imm0 (void) | |
4530 | { | |
4531 | inst.instruction |= inst.operands[0].imm; | |
4532 | } | |
09d92015 | 4533 | |
c19d1205 ZW |
4534 | static void |
4535 | do_rd_cpaddr (void) | |
4536 | { | |
4537 | inst.instruction |= inst.operands[0].reg << 12; | |
4538 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 4539 | } |
a737bd4d | 4540 | |
c19d1205 ZW |
4541 | /* ARM instructions, in alphabetical order by function name (except |
4542 | that wrapper functions appear immediately after the function they | |
4543 | wrap). */ | |
09d92015 | 4544 | |
c19d1205 ZW |
4545 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
4546 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
4547 | |
4548 | static void | |
c19d1205 | 4549 | do_adr (void) |
09d92015 | 4550 | { |
c19d1205 | 4551 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 4552 | |
c19d1205 ZW |
4553 | /* Frag hacking will turn this into a sub instruction if the offset turns |
4554 | out to be negative. */ | |
4555 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 4556 | inst.reloc.pc_rel = 1; |
2fc8bdac | 4557 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 4558 | } |
b99bd4ef | 4559 | |
c19d1205 ZW |
4560 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
4561 | into a relative address of the form: | |
4562 | add rd, pc, #low(label-.-8)" | |
4563 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 4564 | |
c19d1205 ZW |
4565 | static void |
4566 | do_adrl (void) | |
4567 | { | |
4568 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 4569 | |
c19d1205 ZW |
4570 | /* Frag hacking will turn this into a sub instruction if the offset turns |
4571 | out to be negative. */ | |
4572 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
4573 | inst.reloc.pc_rel = 1; |
4574 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 4575 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
4576 | } |
4577 | ||
b99bd4ef | 4578 | static void |
c19d1205 | 4579 | do_arit (void) |
b99bd4ef | 4580 | { |
c19d1205 ZW |
4581 | if (!inst.operands[1].present) |
4582 | inst.operands[1].reg = inst.operands[0].reg; | |
4583 | inst.instruction |= inst.operands[0].reg << 12; | |
4584 | inst.instruction |= inst.operands[1].reg << 16; | |
4585 | encode_arm_shifter_operand (2); | |
4586 | } | |
b99bd4ef | 4587 | |
c19d1205 ZW |
4588 | static void |
4589 | do_bfc (void) | |
4590 | { | |
4591 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
4592 | constraint (msb > 32, _("bit-field extends past end of register")); | |
4593 | /* The instruction encoding stores the LSB and MSB, | |
4594 | not the LSB and width. */ | |
4595 | inst.instruction |= inst.operands[0].reg << 12; | |
4596 | inst.instruction |= inst.operands[1].imm << 7; | |
4597 | inst.instruction |= (msb - 1) << 16; | |
4598 | } | |
b99bd4ef | 4599 | |
c19d1205 ZW |
4600 | static void |
4601 | do_bfi (void) | |
4602 | { | |
4603 | unsigned int msb; | |
b99bd4ef | 4604 | |
c19d1205 ZW |
4605 | /* #0 in second position is alternative syntax for bfc, which is |
4606 | the same instruction but with REG_PC in the Rm field. */ | |
4607 | if (!inst.operands[1].isreg) | |
4608 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 4609 | |
c19d1205 ZW |
4610 | msb = inst.operands[2].imm + inst.operands[3].imm; |
4611 | constraint (msb > 32, _("bit-field extends past end of register")); | |
4612 | /* The instruction encoding stores the LSB and MSB, | |
4613 | not the LSB and width. */ | |
4614 | inst.instruction |= inst.operands[0].reg << 12; | |
4615 | inst.instruction |= inst.operands[1].reg; | |
4616 | inst.instruction |= inst.operands[2].imm << 7; | |
4617 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
4618 | } |
4619 | ||
b99bd4ef | 4620 | static void |
c19d1205 | 4621 | do_bfx (void) |
b99bd4ef | 4622 | { |
c19d1205 ZW |
4623 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
4624 | _("bit-field extends past end of register")); | |
4625 | inst.instruction |= inst.operands[0].reg << 12; | |
4626 | inst.instruction |= inst.operands[1].reg; | |
4627 | inst.instruction |= inst.operands[2].imm << 7; | |
4628 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
4629 | } | |
09d92015 | 4630 | |
c19d1205 ZW |
4631 | /* ARM V5 breakpoint instruction (argument parse) |
4632 | BKPT <16 bit unsigned immediate> | |
4633 | Instruction is not conditional. | |
4634 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
4635 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 4636 | |
c19d1205 ZW |
4637 | static void |
4638 | do_bkpt (void) | |
4639 | { | |
4640 | /* Top 12 of 16 bits to bits 19:8. */ | |
4641 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 4642 | |
c19d1205 ZW |
4643 | /* Bottom 4 of 16 bits to bits 3:0. */ |
4644 | inst.instruction |= inst.operands[0].imm & 0xf; | |
4645 | } | |
09d92015 | 4646 | |
c19d1205 ZW |
4647 | static void |
4648 | encode_branch (int default_reloc) | |
4649 | { | |
4650 | if (inst.operands[0].hasreloc) | |
4651 | { | |
4652 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, | |
4653 | _("the only suffix valid here is '(plt)'")); | |
4654 | inst.reloc.type = BFD_RELOC_ARM_PLT32; | |
c19d1205 | 4655 | } |
b99bd4ef | 4656 | else |
c19d1205 ZW |
4657 | { |
4658 | inst.reloc.type = default_reloc; | |
c19d1205 | 4659 | } |
2fc8bdac | 4660 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
4661 | } |
4662 | ||
b99bd4ef | 4663 | static void |
c19d1205 | 4664 | do_branch (void) |
b99bd4ef | 4665 | { |
39b41c9c PB |
4666 | #ifdef OBJ_ELF |
4667 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
4668 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
4669 | else | |
4670 | #endif | |
4671 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
4672 | } | |
4673 | ||
4674 | static void | |
4675 | do_bl (void) | |
4676 | { | |
4677 | #ifdef OBJ_ELF | |
4678 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
4679 | { | |
4680 | if (inst.cond == COND_ALWAYS) | |
4681 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
4682 | else | |
4683 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
4684 | } | |
4685 | else | |
4686 | #endif | |
4687 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 4688 | } |
b99bd4ef | 4689 | |
c19d1205 ZW |
4690 | /* ARM V5 branch-link-exchange instruction (argument parse) |
4691 | BLX <target_addr> ie BLX(1) | |
4692 | BLX{<condition>} <Rm> ie BLX(2) | |
4693 | Unfortunately, there are two different opcodes for this mnemonic. | |
4694 | So, the insns[].value is not used, and the code here zaps values | |
4695 | into inst.instruction. | |
4696 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 4697 | |
c19d1205 ZW |
4698 | static void |
4699 | do_blx (void) | |
4700 | { | |
4701 | if (inst.operands[0].isreg) | |
b99bd4ef | 4702 | { |
c19d1205 ZW |
4703 | /* Arg is a register; the opcode provided by insns[] is correct. |
4704 | It is not illegal to do "blx pc", just useless. */ | |
4705 | if (inst.operands[0].reg == REG_PC) | |
4706 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 4707 | |
c19d1205 ZW |
4708 | inst.instruction |= inst.operands[0].reg; |
4709 | } | |
4710 | else | |
b99bd4ef | 4711 | { |
c19d1205 ZW |
4712 | /* Arg is an address; this instruction cannot be executed |
4713 | conditionally, and the opcode must be adjusted. */ | |
4714 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
2fc8bdac | 4715 | inst.instruction = 0xfa000000; |
39b41c9c PB |
4716 | #ifdef OBJ_ELF |
4717 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
4718 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
4719 | else | |
4720 | #endif | |
4721 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); | |
b99bd4ef | 4722 | } |
c19d1205 ZW |
4723 | } |
4724 | ||
4725 | static void | |
4726 | do_bx (void) | |
4727 | { | |
4728 | if (inst.operands[0].reg == REG_PC) | |
4729 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 4730 | |
c19d1205 | 4731 | inst.instruction |= inst.operands[0].reg; |
09d92015 MM |
4732 | } |
4733 | ||
c19d1205 ZW |
4734 | |
4735 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
4736 | |
4737 | static void | |
c19d1205 | 4738 | do_bxj (void) |
a737bd4d | 4739 | { |
c19d1205 ZW |
4740 | if (inst.operands[0].reg == REG_PC) |
4741 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
4742 | ||
4743 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
4744 | } |
4745 | ||
c19d1205 ZW |
4746 | /* Co-processor data operation: |
4747 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
4748 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
4749 | static void | |
4750 | do_cdp (void) | |
4751 | { | |
4752 | inst.instruction |= inst.operands[0].reg << 8; | |
4753 | inst.instruction |= inst.operands[1].imm << 20; | |
4754 | inst.instruction |= inst.operands[2].reg << 12; | |
4755 | inst.instruction |= inst.operands[3].reg << 16; | |
4756 | inst.instruction |= inst.operands[4].reg; | |
4757 | inst.instruction |= inst.operands[5].imm << 5; | |
4758 | } | |
a737bd4d NC |
4759 | |
4760 | static void | |
c19d1205 | 4761 | do_cmp (void) |
a737bd4d | 4762 | { |
c19d1205 ZW |
4763 | inst.instruction |= inst.operands[0].reg << 16; |
4764 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
4765 | } |
4766 | ||
c19d1205 ZW |
4767 | /* Transfer between coprocessor and ARM registers. |
4768 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
4769 | MRC2 | |
4770 | MCR{cond} | |
4771 | MCR2 | |
4772 | ||
4773 | No special properties. */ | |
09d92015 MM |
4774 | |
4775 | static void | |
c19d1205 | 4776 | do_co_reg (void) |
09d92015 | 4777 | { |
c19d1205 ZW |
4778 | inst.instruction |= inst.operands[0].reg << 8; |
4779 | inst.instruction |= inst.operands[1].imm << 21; | |
4780 | inst.instruction |= inst.operands[2].reg << 12; | |
4781 | inst.instruction |= inst.operands[3].reg << 16; | |
4782 | inst.instruction |= inst.operands[4].reg; | |
4783 | inst.instruction |= inst.operands[5].imm << 5; | |
4784 | } | |
09d92015 | 4785 | |
c19d1205 ZW |
4786 | /* Transfer between coprocessor register and pair of ARM registers. |
4787 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
4788 | MCRR2 | |
4789 | MRRC{cond} | |
4790 | MRRC2 | |
b99bd4ef | 4791 | |
c19d1205 | 4792 | Two XScale instructions are special cases of these: |
09d92015 | 4793 | |
c19d1205 ZW |
4794 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
4795 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 4796 | |
c19d1205 | 4797 | Result unpredicatable if Rd or Rn is R15. */ |
a737bd4d | 4798 | |
c19d1205 ZW |
4799 | static void |
4800 | do_co_reg2c (void) | |
4801 | { | |
4802 | inst.instruction |= inst.operands[0].reg << 8; | |
4803 | inst.instruction |= inst.operands[1].imm << 4; | |
4804 | inst.instruction |= inst.operands[2].reg << 12; | |
4805 | inst.instruction |= inst.operands[3].reg << 16; | |
4806 | inst.instruction |= inst.operands[4].reg; | |
b99bd4ef NC |
4807 | } |
4808 | ||
c19d1205 ZW |
4809 | static void |
4810 | do_cpsi (void) | |
4811 | { | |
4812 | inst.instruction |= inst.operands[0].imm << 6; | |
4813 | inst.instruction |= inst.operands[1].imm; | |
4814 | } | |
b99bd4ef NC |
4815 | |
4816 | static void | |
c19d1205 | 4817 | do_it (void) |
b99bd4ef | 4818 | { |
c19d1205 ZW |
4819 | /* There is no IT instruction in ARM mode. We |
4820 | process it but do not generate code for it. */ | |
4821 | inst.size = 0; | |
09d92015 | 4822 | } |
b99bd4ef | 4823 | |
09d92015 | 4824 | static void |
c19d1205 | 4825 | do_ldmstm (void) |
ea6ef066 | 4826 | { |
c19d1205 ZW |
4827 | int base_reg = inst.operands[0].reg; |
4828 | int range = inst.operands[1].imm; | |
ea6ef066 | 4829 | |
c19d1205 ZW |
4830 | inst.instruction |= base_reg << 16; |
4831 | inst.instruction |= range; | |
ea6ef066 | 4832 | |
c19d1205 ZW |
4833 | if (inst.operands[1].writeback) |
4834 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 4835 | |
c19d1205 | 4836 | if (inst.operands[0].writeback) |
ea6ef066 | 4837 | { |
c19d1205 ZW |
4838 | inst.instruction |= WRITE_BACK; |
4839 | /* Check for unpredictable uses of writeback. */ | |
4840 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 4841 | { |
c19d1205 ZW |
4842 | /* Not allowed in LDM type 2. */ |
4843 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
4844 | && ((range & (1 << REG_PC)) == 0)) | |
4845 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
4846 | /* Only allowed if base reg not in list for other types. */ | |
4847 | else if (range & (1 << base_reg)) | |
4848 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
4849 | } | |
4850 | else /* STM. */ | |
4851 | { | |
4852 | /* Not allowed for type 2. */ | |
4853 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
4854 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
4855 | /* Only allowed if base reg not in list, or first in list. */ | |
4856 | else if ((range & (1 << base_reg)) | |
4857 | && (range & ((1 << base_reg) - 1))) | |
4858 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 4859 | } |
ea6ef066 | 4860 | } |
a737bd4d NC |
4861 | } |
4862 | ||
c19d1205 ZW |
4863 | /* ARMv5TE load-consecutive (argument parse) |
4864 | Mode is like LDRH. | |
4865 | ||
4866 | LDRccD R, mode | |
4867 | STRccD R, mode. */ | |
4868 | ||
a737bd4d | 4869 | static void |
c19d1205 | 4870 | do_ldrd (void) |
a737bd4d | 4871 | { |
c19d1205 ZW |
4872 | constraint (inst.operands[0].reg % 2 != 0, |
4873 | _("first destination register must be even")); | |
4874 | constraint (inst.operands[1].present | |
4875 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
4876 | _("can only load two consecutive registers")); | |
4877 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
4878 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 4879 | |
c19d1205 ZW |
4880 | if (!inst.operands[1].present) |
4881 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
4882 | ||
4883 | if (inst.instruction & LOAD_BIT) | |
a737bd4d | 4884 | { |
c19d1205 ZW |
4885 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
4886 | register and the first register written; we have to diagnose | |
4887 | overlap between the base and the second register written here. */ | |
ea6ef066 | 4888 | |
c19d1205 ZW |
4889 | if (inst.operands[2].reg == inst.operands[1].reg |
4890 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
4891 | as_warn (_("base register written back, and overlaps " | |
4892 | "second destination register")); | |
b05fe5cf | 4893 | |
c19d1205 ZW |
4894 | /* For an index-register load, the index register must not overlap the |
4895 | destination (even if not write-back). */ | |
4896 | else if (inst.operands[2].immisreg | |
ca3f61f7 NC |
4897 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg |
4898 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
c19d1205 | 4899 | as_warn (_("index register overlaps destination register")); |
b05fe5cf | 4900 | } |
c19d1205 ZW |
4901 | |
4902 | inst.instruction |= inst.operands[0].reg << 12; | |
4903 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
4904 | } |
4905 | ||
4906 | static void | |
c19d1205 | 4907 | do_ldrex (void) |
b05fe5cf | 4908 | { |
c19d1205 ZW |
4909 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
4910 | || inst.operands[1].postind || inst.operands[1].writeback | |
4911 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
4912 | || inst.operands[1].negative |
4913 | /* This can arise if the programmer has written | |
4914 | strex rN, rM, foo | |
4915 | or if they have mistakenly used a register name as the last | |
4916 | operand, eg: | |
4917 | strex rN, rM, rX | |
4918 | It is very difficult to distinguish between these two cases | |
4919 | because "rX" might actually be a label. ie the register | |
4920 | name has been occluded by a symbol of the same name. So we | |
4921 | just generate a general 'bad addressing mode' type error | |
4922 | message and leave it up to the programmer to discover the | |
4923 | true cause and fix their mistake. */ | |
4924 | || (inst.operands[1].reg == REG_PC), | |
4925 | BAD_ADDR_MODE); | |
b05fe5cf | 4926 | |
c19d1205 ZW |
4927 | constraint (inst.reloc.exp.X_op != O_constant |
4928 | || inst.reloc.exp.X_add_number != 0, | |
4929 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 4930 | |
c19d1205 ZW |
4931 | inst.instruction |= inst.operands[0].reg << 12; |
4932 | inst.instruction |= inst.operands[1].reg << 16; | |
4933 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
4934 | } |
4935 | ||
4936 | static void | |
c19d1205 | 4937 | do_ldrexd (void) |
b05fe5cf | 4938 | { |
c19d1205 ZW |
4939 | constraint (inst.operands[0].reg % 2 != 0, |
4940 | _("even register required")); | |
4941 | constraint (inst.operands[1].present | |
4942 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
4943 | _("can only load two consecutive registers")); | |
4944 | /* If op 1 were present and equal to PC, this function wouldn't | |
4945 | have been called in the first place. */ | |
4946 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 4947 | |
c19d1205 ZW |
4948 | inst.instruction |= inst.operands[0].reg << 12; |
4949 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
4950 | } |
4951 | ||
4952 | static void | |
c19d1205 | 4953 | do_ldst (void) |
b05fe5cf | 4954 | { |
c19d1205 ZW |
4955 | inst.instruction |= inst.operands[0].reg << 12; |
4956 | if (!inst.operands[1].isreg) | |
4957 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) | |
b05fe5cf | 4958 | return; |
c19d1205 | 4959 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
4960 | } |
4961 | ||
4962 | static void | |
c19d1205 | 4963 | do_ldstt (void) |
b05fe5cf | 4964 | { |
c19d1205 ZW |
4965 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
4966 | reject [Rn,...]. */ | |
4967 | if (inst.operands[1].preind) | |
b05fe5cf | 4968 | { |
c19d1205 ZW |
4969 | constraint (inst.reloc.exp.X_op != O_constant || |
4970 | inst.reloc.exp.X_add_number != 0, | |
4971 | _("this instruction requires a post-indexed address")); | |
b05fe5cf | 4972 | |
c19d1205 ZW |
4973 | inst.operands[1].preind = 0; |
4974 | inst.operands[1].postind = 1; | |
4975 | inst.operands[1].writeback = 1; | |
b05fe5cf | 4976 | } |
c19d1205 ZW |
4977 | inst.instruction |= inst.operands[0].reg << 12; |
4978 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
4979 | } | |
b05fe5cf | 4980 | |
c19d1205 | 4981 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 4982 | |
c19d1205 ZW |
4983 | static void |
4984 | do_ldstv4 (void) | |
4985 | { | |
4986 | inst.instruction |= inst.operands[0].reg << 12; | |
4987 | if (!inst.operands[1].isreg) | |
4988 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) | |
b05fe5cf | 4989 | return; |
c19d1205 | 4990 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
4991 | } |
4992 | ||
4993 | static void | |
c19d1205 | 4994 | do_ldsttv4 (void) |
b05fe5cf | 4995 | { |
c19d1205 ZW |
4996 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
4997 | reject [Rn,...]. */ | |
4998 | if (inst.operands[1].preind) | |
b05fe5cf | 4999 | { |
c19d1205 ZW |
5000 | constraint (inst.reloc.exp.X_op != O_constant || |
5001 | inst.reloc.exp.X_add_number != 0, | |
5002 | _("this instruction requires a post-indexed address")); | |
b05fe5cf | 5003 | |
c19d1205 ZW |
5004 | inst.operands[1].preind = 0; |
5005 | inst.operands[1].postind = 1; | |
5006 | inst.operands[1].writeback = 1; | |
b05fe5cf | 5007 | } |
c19d1205 ZW |
5008 | inst.instruction |= inst.operands[0].reg << 12; |
5009 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
5010 | } | |
b05fe5cf | 5011 | |
c19d1205 ZW |
5012 | /* Co-processor register load/store. |
5013 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
5014 | static void | |
5015 | do_lstc (void) | |
5016 | { | |
5017 | inst.instruction |= inst.operands[0].reg << 8; | |
5018 | inst.instruction |= inst.operands[1].reg << 12; | |
5019 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
5020 | } |
5021 | ||
b05fe5cf | 5022 | static void |
c19d1205 | 5023 | do_mlas (void) |
b05fe5cf | 5024 | { |
c19d1205 ZW |
5025 | /* This restriction does not apply to mls (nor to mla in v6, but |
5026 | that's hard to detect at present). */ | |
5027 | if (inst.operands[0].reg == inst.operands[1].reg | |
5028 | && !(inst.instruction & 0x00400000)) | |
5029 | as_tsktsk (_("rd and rm should be different in mla")); | |
b05fe5cf | 5030 | |
c19d1205 ZW |
5031 | inst.instruction |= inst.operands[0].reg << 16; |
5032 | inst.instruction |= inst.operands[1].reg; | |
5033 | inst.instruction |= inst.operands[2].reg << 8; | |
5034 | inst.instruction |= inst.operands[3].reg << 12; | |
b05fe5cf | 5035 | |
c19d1205 | 5036 | } |
b05fe5cf | 5037 | |
c19d1205 ZW |
5038 | static void |
5039 | do_mov (void) | |
5040 | { | |
5041 | inst.instruction |= inst.operands[0].reg << 12; | |
5042 | encode_arm_shifter_operand (1); | |
5043 | } | |
b05fe5cf | 5044 | |
c19d1205 ZW |
5045 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
5046 | static void | |
5047 | do_mov16 (void) | |
5048 | { | |
5049 | inst.instruction |= inst.operands[0].reg << 12; | |
b05fe5cf | 5050 | /* The value is in two pieces: 0:11, 16:19. */ |
c19d1205 ZW |
5051 | inst.instruction |= (inst.operands[1].imm & 0x00000fff); |
5052 | inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4; | |
b05fe5cf | 5053 | } |
b99bd4ef NC |
5054 | |
5055 | static void | |
c19d1205 | 5056 | do_mrs (void) |
b99bd4ef | 5057 | { |
c19d1205 ZW |
5058 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ |
5059 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
5060 | != (PSR_c|PSR_f), | |
5061 | _("'CPSR' or 'SPSR' expected")); | |
5062 | inst.instruction |= inst.operands[0].reg << 12; | |
5063 | inst.instruction |= (inst.operands[1].imm & SPSR_BIT); | |
5064 | } | |
b99bd4ef | 5065 | |
c19d1205 ZW |
5066 | /* Two possible forms: |
5067 | "{C|S}PSR_<field>, Rm", | |
5068 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 5069 | |
c19d1205 ZW |
5070 | static void |
5071 | do_msr (void) | |
5072 | { | |
5073 | inst.instruction |= inst.operands[0].imm; | |
5074 | if (inst.operands[1].isreg) | |
5075 | inst.instruction |= inst.operands[1].reg; | |
5076 | else | |
b99bd4ef | 5077 | { |
c19d1205 ZW |
5078 | inst.instruction |= INST_IMMEDIATE; |
5079 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
5080 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 5081 | } |
b99bd4ef NC |
5082 | } |
5083 | ||
c19d1205 ZW |
5084 | static void |
5085 | do_mul (void) | |
a737bd4d | 5086 | { |
c19d1205 ZW |
5087 | if (!inst.operands[2].present) |
5088 | inst.operands[2].reg = inst.operands[0].reg; | |
5089 | inst.instruction |= inst.operands[0].reg << 16; | |
5090 | inst.instruction |= inst.operands[1].reg; | |
5091 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 5092 | |
c19d1205 ZW |
5093 | if (inst.operands[0].reg == inst.operands[1].reg) |
5094 | as_tsktsk (_("rd and rm should be different in mul")); | |
a737bd4d NC |
5095 | } |
5096 | ||
c19d1205 ZW |
5097 | /* Long Multiply Parser |
5098 | UMULL RdLo, RdHi, Rm, Rs | |
5099 | SMULL RdLo, RdHi, Rm, Rs | |
5100 | UMLAL RdLo, RdHi, Rm, Rs | |
5101 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
5102 | |
5103 | static void | |
c19d1205 | 5104 | do_mull (void) |
b99bd4ef | 5105 | { |
c19d1205 ZW |
5106 | inst.instruction |= inst.operands[0].reg << 12; |
5107 | inst.instruction |= inst.operands[1].reg << 16; | |
5108 | inst.instruction |= inst.operands[2].reg; | |
5109 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 5110 | |
c19d1205 ZW |
5111 | /* rdhi, rdlo and rm must all be different. */ |
5112 | if (inst.operands[0].reg == inst.operands[1].reg | |
5113 | || inst.operands[0].reg == inst.operands[2].reg | |
5114 | || inst.operands[1].reg == inst.operands[2].reg) | |
5115 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); | |
5116 | } | |
b99bd4ef | 5117 | |
c19d1205 ZW |
5118 | static void |
5119 | do_nop (void) | |
5120 | { | |
5121 | if (inst.operands[0].present) | |
5122 | { | |
5123 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
5124 | inst.instruction &= 0xf0000000; | |
5125 | inst.instruction |= 0x0320f000 + inst.operands[0].imm; | |
5126 | } | |
b99bd4ef NC |
5127 | } |
5128 | ||
c19d1205 ZW |
5129 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
5130 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
5131 | Condition defaults to COND_ALWAYS. | |
5132 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
5133 | |
5134 | static void | |
c19d1205 | 5135 | do_pkhbt (void) |
b99bd4ef | 5136 | { |
c19d1205 ZW |
5137 | inst.instruction |= inst.operands[0].reg << 12; |
5138 | inst.instruction |= inst.operands[1].reg << 16; | |
5139 | inst.instruction |= inst.operands[2].reg; | |
5140 | if (inst.operands[3].present) | |
5141 | encode_arm_shift (3); | |
5142 | } | |
b99bd4ef | 5143 | |
c19d1205 | 5144 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 5145 | |
c19d1205 ZW |
5146 | static void |
5147 | do_pkhtb (void) | |
5148 | { | |
5149 | if (!inst.operands[3].present) | |
b99bd4ef | 5150 | { |
c19d1205 ZW |
5151 | /* If the shift specifier is omitted, turn the instruction |
5152 | into pkhbt rd, rm, rn. */ | |
5153 | inst.instruction &= 0xfff00010; | |
5154 | inst.instruction |= inst.operands[0].reg << 12; | |
5155 | inst.instruction |= inst.operands[1].reg; | |
5156 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
5157 | } |
5158 | else | |
5159 | { | |
c19d1205 ZW |
5160 | inst.instruction |= inst.operands[0].reg << 12; |
5161 | inst.instruction |= inst.operands[1].reg << 16; | |
5162 | inst.instruction |= inst.operands[2].reg; | |
5163 | encode_arm_shift (3); | |
b99bd4ef NC |
5164 | } |
5165 | } | |
5166 | ||
c19d1205 ZW |
5167 | /* ARMv5TE: Preload-Cache |
5168 | ||
5169 | PLD <addr_mode> | |
5170 | ||
5171 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
5172 | |
5173 | static void | |
c19d1205 | 5174 | do_pld (void) |
b99bd4ef | 5175 | { |
c19d1205 ZW |
5176 | constraint (!inst.operands[0].isreg, |
5177 | _("'[' expected after PLD mnemonic")); | |
5178 | constraint (inst.operands[0].postind, | |
5179 | _("post-indexed expression used in preload instruction")); | |
5180 | constraint (inst.operands[0].writeback, | |
5181 | _("writeback used in preload instruction")); | |
5182 | constraint (!inst.operands[0].preind, | |
5183 | _("unindexed addressing used in preload instruction")); | |
5184 | inst.instruction |= inst.operands[0].reg; | |
5185 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
5186 | } | |
b99bd4ef | 5187 | |
c19d1205 ZW |
5188 | static void |
5189 | do_push_pop (void) | |
5190 | { | |
5191 | inst.operands[1] = inst.operands[0]; | |
5192 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
5193 | inst.operands[0].isreg = 1; | |
5194 | inst.operands[0].writeback = 1; | |
5195 | inst.operands[0].reg = REG_SP; | |
5196 | do_ldmstm (); | |
5197 | } | |
b99bd4ef | 5198 | |
c19d1205 ZW |
5199 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
5200 | word at the specified address and the following word | |
5201 | respectively. | |
5202 | Unconditionally executed. | |
5203 | Error if Rn is R15. */ | |
b99bd4ef | 5204 | |
c19d1205 ZW |
5205 | static void |
5206 | do_rfe (void) | |
5207 | { | |
5208 | inst.instruction |= inst.operands[0].reg << 16; | |
5209 | if (inst.operands[0].writeback) | |
5210 | inst.instruction |= WRITE_BACK; | |
5211 | } | |
b99bd4ef | 5212 | |
c19d1205 | 5213 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 5214 | |
c19d1205 ZW |
5215 | static void |
5216 | do_ssat (void) | |
5217 | { | |
5218 | inst.instruction |= inst.operands[0].reg << 12; | |
5219 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
5220 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 5221 | |
c19d1205 ZW |
5222 | if (inst.operands[3].present) |
5223 | encode_arm_shift (3); | |
b99bd4ef NC |
5224 | } |
5225 | ||
c19d1205 | 5226 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
5227 | |
5228 | static void | |
c19d1205 | 5229 | do_usat (void) |
b99bd4ef | 5230 | { |
c19d1205 ZW |
5231 | inst.instruction |= inst.operands[0].reg << 12; |
5232 | inst.instruction |= inst.operands[1].imm << 16; | |
5233 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 5234 | |
c19d1205 ZW |
5235 | if (inst.operands[3].present) |
5236 | encode_arm_shift (3); | |
b99bd4ef NC |
5237 | } |
5238 | ||
c19d1205 | 5239 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
5240 | |
5241 | static void | |
c19d1205 | 5242 | do_ssat16 (void) |
09d92015 | 5243 | { |
c19d1205 ZW |
5244 | inst.instruction |= inst.operands[0].reg << 12; |
5245 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
5246 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
5247 | } |
5248 | ||
c19d1205 ZW |
5249 | static void |
5250 | do_usat16 (void) | |
a737bd4d | 5251 | { |
c19d1205 ZW |
5252 | inst.instruction |= inst.operands[0].reg << 12; |
5253 | inst.instruction |= inst.operands[1].imm << 16; | |
5254 | inst.instruction |= inst.operands[2].reg; | |
5255 | } | |
a737bd4d | 5256 | |
c19d1205 ZW |
5257 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
5258 | preserving the other bits. | |
a737bd4d | 5259 | |
c19d1205 ZW |
5260 | setend <endian_specifier>, where <endian_specifier> is either |
5261 | BE or LE. */ | |
a737bd4d | 5262 | |
c19d1205 ZW |
5263 | static void |
5264 | do_setend (void) | |
5265 | { | |
5266 | if (inst.operands[0].imm) | |
5267 | inst.instruction |= 0x200; | |
a737bd4d NC |
5268 | } |
5269 | ||
5270 | static void | |
c19d1205 | 5271 | do_shift (void) |
a737bd4d | 5272 | { |
c19d1205 ZW |
5273 | unsigned int Rm = (inst.operands[1].present |
5274 | ? inst.operands[1].reg | |
5275 | : inst.operands[0].reg); | |
a737bd4d | 5276 | |
c19d1205 ZW |
5277 | inst.instruction |= inst.operands[0].reg << 12; |
5278 | inst.instruction |= Rm; | |
5279 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 5280 | { |
c19d1205 ZW |
5281 | constraint (inst.operands[0].reg != Rm, |
5282 | _("source1 and dest must be same register")); | |
5283 | inst.instruction |= inst.operands[2].reg << 8; | |
5284 | inst.instruction |= SHIFT_BY_REG; | |
a737bd4d NC |
5285 | } |
5286 | else | |
c19d1205 | 5287 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
5288 | } |
5289 | ||
09d92015 | 5290 | static void |
3eb17e6b | 5291 | do_smc (void) |
09d92015 | 5292 | { |
3eb17e6b | 5293 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 5294 | inst.reloc.pc_rel = 0; |
09d92015 MM |
5295 | } |
5296 | ||
09d92015 | 5297 | static void |
c19d1205 | 5298 | do_swi (void) |
09d92015 | 5299 | { |
c19d1205 ZW |
5300 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
5301 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
5302 | } |
5303 | ||
c19d1205 ZW |
5304 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
5305 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
5306 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
5307 | Error if any register is R15. */ | |
e16bb312 | 5308 | |
c19d1205 ZW |
5309 | static void |
5310 | do_smla (void) | |
e16bb312 | 5311 | { |
c19d1205 ZW |
5312 | inst.instruction |= inst.operands[0].reg << 16; |
5313 | inst.instruction |= inst.operands[1].reg; | |
5314 | inst.instruction |= inst.operands[2].reg << 8; | |
5315 | inst.instruction |= inst.operands[3].reg << 12; | |
5316 | } | |
a737bd4d | 5317 | |
c19d1205 ZW |
5318 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
5319 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
5320 | Error if any register is R15. | |
5321 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 5322 | |
c19d1205 ZW |
5323 | static void |
5324 | do_smlal (void) | |
5325 | { | |
5326 | inst.instruction |= inst.operands[0].reg << 12; | |
5327 | inst.instruction |= inst.operands[1].reg << 16; | |
5328 | inst.instruction |= inst.operands[2].reg; | |
5329 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 5330 | |
c19d1205 ZW |
5331 | if (inst.operands[0].reg == inst.operands[1].reg) |
5332 | as_tsktsk (_("rdhi and rdlo must be different")); | |
5333 | } | |
a737bd4d | 5334 | |
c19d1205 ZW |
5335 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
5336 | SMULxy{cond} Rd,Rm,Rs | |
5337 | Error if any register is R15. */ | |
a737bd4d | 5338 | |
c19d1205 ZW |
5339 | static void |
5340 | do_smul (void) | |
5341 | { | |
5342 | inst.instruction |= inst.operands[0].reg << 16; | |
5343 | inst.instruction |= inst.operands[1].reg; | |
5344 | inst.instruction |= inst.operands[2].reg << 8; | |
5345 | } | |
a737bd4d | 5346 | |
c19d1205 | 5347 | /* ARM V6 srs (argument parse). */ |
a737bd4d | 5348 | |
c19d1205 ZW |
5349 | static void |
5350 | do_srs (void) | |
5351 | { | |
5352 | inst.instruction |= inst.operands[0].imm; | |
5353 | if (inst.operands[0].writeback) | |
5354 | inst.instruction |= WRITE_BACK; | |
5355 | } | |
a737bd4d | 5356 | |
c19d1205 | 5357 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 5358 | |
c19d1205 ZW |
5359 | static void |
5360 | do_strex (void) | |
5361 | { | |
5362 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
5363 | || inst.operands[2].postind || inst.operands[2].writeback | |
5364 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
5365 | || inst.operands[2].negative |
5366 | /* See comment in do_ldrex(). */ | |
5367 | || (inst.operands[2].reg == REG_PC), | |
5368 | BAD_ADDR_MODE); | |
a737bd4d | 5369 | |
c19d1205 ZW |
5370 | constraint (inst.operands[0].reg == inst.operands[1].reg |
5371 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 5372 | |
c19d1205 ZW |
5373 | constraint (inst.reloc.exp.X_op != O_constant |
5374 | || inst.reloc.exp.X_add_number != 0, | |
5375 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 5376 | |
c19d1205 ZW |
5377 | inst.instruction |= inst.operands[0].reg << 12; |
5378 | inst.instruction |= inst.operands[1].reg; | |
5379 | inst.instruction |= inst.operands[2].reg << 16; | |
5380 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
5381 | } |
5382 | ||
5383 | static void | |
c19d1205 | 5384 | do_strexd (void) |
e16bb312 | 5385 | { |
c19d1205 ZW |
5386 | constraint (inst.operands[1].reg % 2 != 0, |
5387 | _("even register required")); | |
5388 | constraint (inst.operands[2].present | |
5389 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
5390 | _("can only store two consecutive registers")); | |
5391 | /* If op 2 were present and equal to PC, this function wouldn't | |
5392 | have been called in the first place. */ | |
5393 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 5394 | |
c19d1205 ZW |
5395 | constraint (inst.operands[0].reg == inst.operands[1].reg |
5396 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
5397 | || inst.operands[0].reg == inst.operands[3].reg, | |
5398 | BAD_OVERLAP); | |
e16bb312 | 5399 | |
c19d1205 ZW |
5400 | inst.instruction |= inst.operands[0].reg << 12; |
5401 | inst.instruction |= inst.operands[1].reg; | |
5402 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
5403 | } |
5404 | ||
c19d1205 ZW |
5405 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
5406 | extends it to 32-bits, and adds the result to a value in another | |
5407 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
5408 | before extracting the 16-bit value. | |
5409 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
5410 | Condition defaults to COND_ALWAYS. | |
5411 | Error if any register uses R15. */ | |
5412 | ||
e16bb312 | 5413 | static void |
c19d1205 | 5414 | do_sxtah (void) |
e16bb312 | 5415 | { |
c19d1205 ZW |
5416 | inst.instruction |= inst.operands[0].reg << 12; |
5417 | inst.instruction |= inst.operands[1].reg << 16; | |
5418 | inst.instruction |= inst.operands[2].reg; | |
5419 | inst.instruction |= inst.operands[3].imm << 10; | |
5420 | } | |
e16bb312 | 5421 | |
c19d1205 | 5422 | /* ARM V6 SXTH. |
e16bb312 | 5423 | |
c19d1205 ZW |
5424 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
5425 | Condition defaults to COND_ALWAYS. | |
5426 | Error if any register uses R15. */ | |
e16bb312 NC |
5427 | |
5428 | static void | |
c19d1205 | 5429 | do_sxth (void) |
e16bb312 | 5430 | { |
c19d1205 ZW |
5431 | inst.instruction |= inst.operands[0].reg << 12; |
5432 | inst.instruction |= inst.operands[1].reg; | |
5433 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 5434 | } |
c19d1205 ZW |
5435 | \f |
5436 | /* VFP instructions. In a logical order: SP variant first, monad | |
5437 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
5438 | |
5439 | static void | |
c19d1205 | 5440 | do_vfp_sp_monadic (void) |
e16bb312 | 5441 | { |
c19d1205 ZW |
5442 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
5443 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
5444 | } |
5445 | ||
5446 | static void | |
c19d1205 | 5447 | do_vfp_sp_dyadic (void) |
e16bb312 | 5448 | { |
c19d1205 ZW |
5449 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
5450 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
5451 | encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
5452 | } |
5453 | ||
5454 | static void | |
c19d1205 | 5455 | do_vfp_sp_compare_z (void) |
e16bb312 | 5456 | { |
c19d1205 | 5457 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
5458 | } |
5459 | ||
5460 | static void | |
c19d1205 | 5461 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 5462 | { |
c19d1205 ZW |
5463 | inst.instruction |= inst.operands[0].reg << 12; |
5464 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
5465 | } |
5466 | ||
5467 | static void | |
c19d1205 | 5468 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 5469 | { |
c19d1205 ZW |
5470 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
5471 | inst.instruction |= inst.operands[1].reg; | |
e16bb312 NC |
5472 | } |
5473 | ||
5474 | static void | |
c19d1205 | 5475 | do_vfp_reg_from_sp (void) |
e16bb312 | 5476 | { |
c19d1205 ZW |
5477 | inst.instruction |= inst.operands[0].reg << 12; |
5478 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
e16bb312 NC |
5479 | } |
5480 | ||
5481 | static void | |
c19d1205 | 5482 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 5483 | { |
c19d1205 ZW |
5484 | constraint (inst.operands[2].imm != 2, |
5485 | _("only two consecutive VFP SP registers allowed here")); | |
5486 | inst.instruction |= inst.operands[0].reg << 12; | |
5487 | inst.instruction |= inst.operands[1].reg << 16; | |
5488 | encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
5489 | } |
5490 | ||
5491 | static void | |
c19d1205 | 5492 | do_vfp_sp_from_reg (void) |
e16bb312 | 5493 | { |
c19d1205 ZW |
5494 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sn); |
5495 | inst.instruction |= inst.operands[1].reg << 12; | |
e16bb312 NC |
5496 | } |
5497 | ||
5498 | static void | |
c19d1205 | 5499 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 5500 | { |
c19d1205 ZW |
5501 | constraint (inst.operands[0].imm != 2, |
5502 | _("only two consecutive VFP SP registers allowed here")); | |
5503 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sm); | |
5504 | inst.instruction |= inst.operands[1].reg << 12; | |
5505 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
5506 | } |
5507 | ||
5508 | static void | |
c19d1205 | 5509 | do_vfp_sp_ldst (void) |
e16bb312 | 5510 | { |
c19d1205 ZW |
5511 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
5512 | encode_arm_cp_address (1, FALSE, TRUE, 0); | |
e16bb312 NC |
5513 | } |
5514 | ||
5515 | static void | |
c19d1205 | 5516 | do_vfp_dp_ldst (void) |
e16bb312 | 5517 | { |
c19d1205 ZW |
5518 | inst.instruction |= inst.operands[0].reg << 12; |
5519 | encode_arm_cp_address (1, FALSE, TRUE, 0); | |
e16bb312 NC |
5520 | } |
5521 | ||
c19d1205 | 5522 | |
e16bb312 | 5523 | static void |
c19d1205 | 5524 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 5525 | { |
c19d1205 ZW |
5526 | if (inst.operands[0].writeback) |
5527 | inst.instruction |= WRITE_BACK; | |
5528 | else | |
5529 | constraint (ldstm_type != VFP_LDSTMIA, | |
5530 | _("this addressing mode requires base-register writeback")); | |
5531 | inst.instruction |= inst.operands[0].reg << 16; | |
5532 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sd); | |
5533 | inst.instruction |= inst.operands[1].imm; | |
e16bb312 NC |
5534 | } |
5535 | ||
5536 | static void | |
c19d1205 | 5537 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 5538 | { |
c19d1205 | 5539 | int count; |
e16bb312 | 5540 | |
c19d1205 ZW |
5541 | if (inst.operands[0].writeback) |
5542 | inst.instruction |= WRITE_BACK; | |
5543 | else | |
5544 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
5545 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 5546 | |
c19d1205 ZW |
5547 | inst.instruction |= inst.operands[0].reg << 16; |
5548 | inst.instruction |= inst.operands[1].reg << 12; | |
e16bb312 | 5549 | |
c19d1205 ZW |
5550 | count = inst.operands[1].imm << 1; |
5551 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
5552 | count += 1; | |
e16bb312 | 5553 | |
c19d1205 | 5554 | inst.instruction |= count; |
e16bb312 NC |
5555 | } |
5556 | ||
5557 | static void | |
c19d1205 | 5558 | do_vfp_sp_ldstmia (void) |
e16bb312 | 5559 | { |
c19d1205 | 5560 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
5561 | } |
5562 | ||
5563 | static void | |
c19d1205 | 5564 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 5565 | { |
c19d1205 | 5566 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
5567 | } |
5568 | ||
5569 | static void | |
c19d1205 | 5570 | do_vfp_dp_ldstmia (void) |
e16bb312 | 5571 | { |
c19d1205 | 5572 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
5573 | } |
5574 | ||
5575 | static void | |
c19d1205 | 5576 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 5577 | { |
c19d1205 | 5578 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
5579 | } |
5580 | ||
5581 | static void | |
c19d1205 | 5582 | do_vfp_xp_ldstmia (void) |
e16bb312 | 5583 | { |
c19d1205 ZW |
5584 | vfp_dp_ldstm (VFP_LDSTMIAX); |
5585 | } | |
e16bb312 | 5586 | |
c19d1205 ZW |
5587 | static void |
5588 | do_vfp_xp_ldstmdb (void) | |
5589 | { | |
5590 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 5591 | } |
c19d1205 ZW |
5592 | \f |
5593 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 5594 | |
c19d1205 ZW |
5595 | static void |
5596 | do_fpa_cmp (void) | |
5597 | { | |
5598 | inst.instruction |= inst.operands[0].reg << 16; | |
5599 | inst.instruction |= inst.operands[1].reg; | |
5600 | } | |
b99bd4ef NC |
5601 | |
5602 | static void | |
c19d1205 | 5603 | do_fpa_ldmstm (void) |
b99bd4ef | 5604 | { |
c19d1205 ZW |
5605 | inst.instruction |= inst.operands[0].reg << 12; |
5606 | switch (inst.operands[1].imm) | |
5607 | { | |
5608 | case 1: inst.instruction |= CP_T_X; break; | |
5609 | case 2: inst.instruction |= CP_T_Y; break; | |
5610 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
5611 | case 4: break; | |
5612 | default: abort (); | |
5613 | } | |
b99bd4ef | 5614 | |
c19d1205 ZW |
5615 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
5616 | { | |
5617 | /* The instruction specified "ea" or "fd", so we can only accept | |
5618 | [Rn]{!}. The instruction does not really support stacking or | |
5619 | unstacking, so we have to emulate these by setting appropriate | |
5620 | bits and offsets. */ | |
5621 | constraint (inst.reloc.exp.X_op != O_constant | |
5622 | || inst.reloc.exp.X_add_number != 0, | |
5623 | _("this instruction does not support indexing")); | |
b99bd4ef | 5624 | |
c19d1205 ZW |
5625 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
5626 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 5627 | |
c19d1205 ZW |
5628 | if (!(inst.instruction & INDEX_UP)) |
5629 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 5630 | |
c19d1205 ZW |
5631 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
5632 | { | |
5633 | inst.operands[2].preind = 0; | |
5634 | inst.operands[2].postind = 1; | |
5635 | } | |
5636 | } | |
b99bd4ef | 5637 | |
c19d1205 | 5638 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 5639 | } |
c19d1205 ZW |
5640 | \f |
5641 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 5642 | |
c19d1205 ZW |
5643 | static void |
5644 | do_iwmmxt_tandorc (void) | |
5645 | { | |
5646 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
5647 | } | |
b99bd4ef | 5648 | |
c19d1205 ZW |
5649 | static void |
5650 | do_iwmmxt_textrc (void) | |
5651 | { | |
5652 | inst.instruction |= inst.operands[0].reg << 12; | |
5653 | inst.instruction |= inst.operands[1].imm; | |
5654 | } | |
b99bd4ef NC |
5655 | |
5656 | static void | |
c19d1205 | 5657 | do_iwmmxt_textrm (void) |
b99bd4ef | 5658 | { |
c19d1205 ZW |
5659 | inst.instruction |= inst.operands[0].reg << 12; |
5660 | inst.instruction |= inst.operands[1].reg << 16; | |
5661 | inst.instruction |= inst.operands[2].imm; | |
5662 | } | |
b99bd4ef | 5663 | |
c19d1205 ZW |
5664 | static void |
5665 | do_iwmmxt_tinsr (void) | |
5666 | { | |
5667 | inst.instruction |= inst.operands[0].reg << 16; | |
5668 | inst.instruction |= inst.operands[1].reg << 12; | |
5669 | inst.instruction |= inst.operands[2].imm; | |
5670 | } | |
b99bd4ef | 5671 | |
c19d1205 ZW |
5672 | static void |
5673 | do_iwmmxt_tmia (void) | |
5674 | { | |
5675 | inst.instruction |= inst.operands[0].reg << 5; | |
5676 | inst.instruction |= inst.operands[1].reg; | |
5677 | inst.instruction |= inst.operands[2].reg << 12; | |
5678 | } | |
b99bd4ef | 5679 | |
c19d1205 ZW |
5680 | static void |
5681 | do_iwmmxt_waligni (void) | |
5682 | { | |
5683 | inst.instruction |= inst.operands[0].reg << 12; | |
5684 | inst.instruction |= inst.operands[1].reg << 16; | |
5685 | inst.instruction |= inst.operands[2].reg; | |
5686 | inst.instruction |= inst.operands[3].imm << 20; | |
5687 | } | |
b99bd4ef | 5688 | |
c19d1205 ZW |
5689 | static void |
5690 | do_iwmmxt_wmov (void) | |
5691 | { | |
5692 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
5693 | inst.instruction |= inst.operands[0].reg << 12; | |
5694 | inst.instruction |= inst.operands[1].reg << 16; | |
5695 | inst.instruction |= inst.operands[1].reg; | |
5696 | } | |
b99bd4ef | 5697 | |
c19d1205 ZW |
5698 | static void |
5699 | do_iwmmxt_wldstbh (void) | |
5700 | { | |
8f06b2d8 | 5701 | int reloc; |
c19d1205 ZW |
5702 | inst.instruction |= inst.operands[0].reg << 12; |
5703 | inst.reloc.exp.X_add_number *= 4; | |
8f06b2d8 PB |
5704 | if (thumb_mode) |
5705 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
5706 | else | |
5707 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
5708 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
5709 | } |
5710 | ||
c19d1205 ZW |
5711 | static void |
5712 | do_iwmmxt_wldstw (void) | |
5713 | { | |
5714 | /* RIWR_RIWC clears .isreg for a control register. */ | |
5715 | if (!inst.operands[0].isreg) | |
5716 | { | |
5717 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
5718 | inst.instruction |= 0xf0000000; | |
5719 | } | |
b99bd4ef | 5720 | |
c19d1205 ZW |
5721 | inst.instruction |= inst.operands[0].reg << 12; |
5722 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
5723 | } | |
b99bd4ef NC |
5724 | |
5725 | static void | |
c19d1205 | 5726 | do_iwmmxt_wldstd (void) |
b99bd4ef | 5727 | { |
c19d1205 | 5728 | inst.instruction |= inst.operands[0].reg << 12; |
f2184508 | 5729 | encode_arm_cp_address (1, TRUE, FALSE, 0); |
c19d1205 | 5730 | } |
b99bd4ef | 5731 | |
c19d1205 ZW |
5732 | static void |
5733 | do_iwmmxt_wshufh (void) | |
5734 | { | |
5735 | inst.instruction |= inst.operands[0].reg << 12; | |
5736 | inst.instruction |= inst.operands[1].reg << 16; | |
5737 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
5738 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
5739 | } | |
b99bd4ef | 5740 | |
c19d1205 ZW |
5741 | static void |
5742 | do_iwmmxt_wzero (void) | |
5743 | { | |
5744 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
5745 | inst.instruction |= inst.operands[0].reg; | |
5746 | inst.instruction |= inst.operands[0].reg << 12; | |
5747 | inst.instruction |= inst.operands[0].reg << 16; | |
5748 | } | |
5749 | \f | |
5750 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
5751 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 5752 | |
c19d1205 | 5753 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 5754 | |
c19d1205 ZW |
5755 | static void |
5756 | do_mav_triple (void) | |
5757 | { | |
5758 | inst.instruction |= inst.operands[0].reg << 16; | |
5759 | inst.instruction |= inst.operands[1].reg; | |
5760 | inst.instruction |= inst.operands[2].reg << 12; | |
5761 | } | |
b99bd4ef | 5762 | |
c19d1205 ZW |
5763 | /* Insns like "foo W,X,Y,Z". |
5764 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 5765 | |
c19d1205 ZW |
5766 | static void |
5767 | do_mav_quad (void) | |
5768 | { | |
5769 | inst.instruction |= inst.operands[0].reg << 5; | |
5770 | inst.instruction |= inst.operands[1].reg << 12; | |
5771 | inst.instruction |= inst.operands[2].reg << 16; | |
5772 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
5773 | } |
5774 | ||
c19d1205 ZW |
5775 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
5776 | static void | |
5777 | do_mav_dspsc (void) | |
a737bd4d | 5778 | { |
c19d1205 ZW |
5779 | inst.instruction |= inst.operands[1].reg << 12; |
5780 | } | |
a737bd4d | 5781 | |
c19d1205 ZW |
5782 | /* Maverick shift immediate instructions. |
5783 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
5784 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 5785 | |
c19d1205 ZW |
5786 | static void |
5787 | do_mav_shift (void) | |
5788 | { | |
5789 | int imm = inst.operands[2].imm; | |
a737bd4d | 5790 | |
c19d1205 ZW |
5791 | inst.instruction |= inst.operands[0].reg << 12; |
5792 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 5793 | |
c19d1205 ZW |
5794 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
5795 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
5796 | Bit 4 should be 0. */ | |
5797 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 5798 | |
c19d1205 ZW |
5799 | inst.instruction |= imm; |
5800 | } | |
5801 | \f | |
5802 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 5803 | |
c19d1205 ZW |
5804 | /* Xscale multiply-accumulate (argument parse) |
5805 | MIAcc acc0,Rm,Rs | |
5806 | MIAPHcc acc0,Rm,Rs | |
5807 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 5808 | |
c19d1205 ZW |
5809 | static void |
5810 | do_xsc_mia (void) | |
5811 | { | |
5812 | inst.instruction |= inst.operands[1].reg; | |
5813 | inst.instruction |= inst.operands[2].reg << 12; | |
5814 | } | |
a737bd4d | 5815 | |
c19d1205 | 5816 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 5817 | |
c19d1205 | 5818 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 5819 | |
c19d1205 ZW |
5820 | static void |
5821 | do_xsc_mar (void) | |
5822 | { | |
5823 | inst.instruction |= inst.operands[1].reg << 12; | |
5824 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
5825 | } |
5826 | ||
c19d1205 | 5827 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 5828 | |
c19d1205 | 5829 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
5830 | |
5831 | static void | |
c19d1205 | 5832 | do_xsc_mra (void) |
b99bd4ef | 5833 | { |
c19d1205 ZW |
5834 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
5835 | inst.instruction |= inst.operands[0].reg << 12; | |
5836 | inst.instruction |= inst.operands[1].reg << 16; | |
5837 | } | |
5838 | \f | |
5839 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 5840 | |
c19d1205 ZW |
5841 | /* inst.operands[i] is a shifted-register operand; encode |
5842 | it into inst.instruction in the format used by Thumb32. */ | |
5843 | ||
5844 | static void | |
5845 | encode_thumb32_shifted_operand (int i) | |
5846 | { | |
5847 | unsigned int value = inst.reloc.exp.X_add_number; | |
5848 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 5849 | |
9c3c69f2 PB |
5850 | constraint (inst.operands[i].immisreg, |
5851 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
5852 | inst.instruction |= inst.operands[i].reg; |
5853 | if (shift == SHIFT_RRX) | |
5854 | inst.instruction |= SHIFT_ROR << 4; | |
5855 | else | |
b99bd4ef | 5856 | { |
c19d1205 ZW |
5857 | constraint (inst.reloc.exp.X_op != O_constant, |
5858 | _("expression too complex")); | |
5859 | ||
5860 | constraint (value > 32 | |
5861 | || (value == 32 && (shift == SHIFT_LSL | |
5862 | || shift == SHIFT_ROR)), | |
5863 | _("shift expression is too large")); | |
5864 | ||
5865 | if (value == 0) | |
5866 | shift = SHIFT_LSL; | |
5867 | else if (value == 32) | |
5868 | value = 0; | |
5869 | ||
5870 | inst.instruction |= shift << 4; | |
5871 | inst.instruction |= (value & 0x1c) << 10; | |
5872 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 5873 | } |
c19d1205 | 5874 | } |
b99bd4ef | 5875 | |
b99bd4ef | 5876 | |
c19d1205 ZW |
5877 | /* inst.operands[i] was set up by parse_address. Encode it into a |
5878 | Thumb32 format load or store instruction. Reject forms that cannot | |
5879 | be used with such instructions. If is_t is true, reject forms that | |
5880 | cannot be used with a T instruction; if is_d is true, reject forms | |
5881 | that cannot be used with a D instruction. */ | |
b99bd4ef | 5882 | |
c19d1205 ZW |
5883 | static void |
5884 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
5885 | { | |
5886 | bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); | |
5887 | ||
5888 | constraint (!inst.operands[i].isreg, | |
5889 | _("Thumb does not support the ldr =N pseudo-operation")); | |
b99bd4ef | 5890 | |
c19d1205 ZW |
5891 | inst.instruction |= inst.operands[i].reg << 16; |
5892 | if (inst.operands[i].immisreg) | |
b99bd4ef | 5893 | { |
c19d1205 ZW |
5894 | constraint (is_pc, _("cannot use register index with PC-relative addressing")); |
5895 | constraint (is_t || is_d, _("cannot use register index with this instruction")); | |
5896 | constraint (inst.operands[i].negative, | |
5897 | _("Thumb does not support negative register indexing")); | |
5898 | constraint (inst.operands[i].postind, | |
5899 | _("Thumb does not support register post-indexing")); | |
5900 | constraint (inst.operands[i].writeback, | |
5901 | _("Thumb does not support register indexing with writeback")); | |
5902 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
5903 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 5904 | |
c19d1205 ZW |
5905 | inst.instruction |= inst.operands[1].imm; |
5906 | if (inst.operands[i].shifted) | |
b99bd4ef | 5907 | { |
c19d1205 ZW |
5908 | constraint (inst.reloc.exp.X_op != O_constant, |
5909 | _("expression too complex")); | |
9c3c69f2 PB |
5910 | constraint (inst.reloc.exp.X_add_number < 0 |
5911 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 5912 | _("shift out of range")); |
9c3c69f2 | 5913 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
5914 | } |
5915 | inst.reloc.type = BFD_RELOC_UNUSED; | |
5916 | } | |
5917 | else if (inst.operands[i].preind) | |
5918 | { | |
5919 | constraint (is_pc && inst.operands[i].writeback, | |
5920 | _("cannot use writeback with PC-relative addressing")); | |
5921 | constraint (is_t && inst.operands[1].writeback, | |
5922 | _("cannot use writeback with this instruction")); | |
5923 | ||
5924 | if (is_d) | |
5925 | { | |
5926 | inst.instruction |= 0x01000000; | |
5927 | if (inst.operands[i].writeback) | |
5928 | inst.instruction |= 0x00200000; | |
b99bd4ef | 5929 | } |
c19d1205 | 5930 | else |
b99bd4ef | 5931 | { |
c19d1205 ZW |
5932 | inst.instruction |= 0x00000c00; |
5933 | if (inst.operands[i].writeback) | |
5934 | inst.instruction |= 0x00000100; | |
b99bd4ef | 5935 | } |
c19d1205 | 5936 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 5937 | } |
c19d1205 | 5938 | else if (inst.operands[i].postind) |
b99bd4ef | 5939 | { |
c19d1205 ZW |
5940 | assert (inst.operands[i].writeback); |
5941 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); | |
5942 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
5943 | ||
5944 | if (is_d) | |
5945 | inst.instruction |= 0x00200000; | |
5946 | else | |
5947 | inst.instruction |= 0x00000900; | |
5948 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
5949 | } | |
5950 | else /* unindexed - only for coprocessor */ | |
5951 | inst.error = _("instruction does not accept unindexed addressing"); | |
5952 | } | |
5953 | ||
5954 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
5955 | encodings (the latter only in post-V6T2 cores). The index is the | |
5956 | value used in the insns table below. When there is more than one | |
5957 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
5958 | holds variant (1). |
5959 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 ZW |
5960 | #define T16_32_TAB \ |
5961 | X(adc, 4140, eb400000), \ | |
5962 | X(adcs, 4140, eb500000), \ | |
5963 | X(add, 1c00, eb000000), \ | |
5964 | X(adds, 1c00, eb100000), \ | |
0110f2b8 PB |
5965 | X(addi, 0000, f1000000), \ |
5966 | X(addis, 0000, f1100000), \ | |
5967 | X(add_pc,000f, f20f0000), \ | |
5968 | X(add_sp,000d, f10d0000), \ | |
e9f89963 | 5969 | X(adr, 000f, f20f0000), \ |
c19d1205 ZW |
5970 | X(and, 4000, ea000000), \ |
5971 | X(ands, 4000, ea100000), \ | |
5972 | X(asr, 1000, fa40f000), \ | |
5973 | X(asrs, 1000, fa50f000), \ | |
0110f2b8 PB |
5974 | X(b, e000, f000b000), \ |
5975 | X(bcond, d000, f0008000), \ | |
c19d1205 ZW |
5976 | X(bic, 4380, ea200000), \ |
5977 | X(bics, 4380, ea300000), \ | |
5978 | X(cmn, 42c0, eb100f00), \ | |
5979 | X(cmp, 2800, ebb00f00), \ | |
5980 | X(cpsie, b660, f3af8400), \ | |
5981 | X(cpsid, b670, f3af8600), \ | |
5982 | X(cpy, 4600, ea4f0000), \ | |
0110f2b8 | 5983 | X(dec_sp,80dd, f1bd0d00), \ |
c19d1205 ZW |
5984 | X(eor, 4040, ea800000), \ |
5985 | X(eors, 4040, ea900000), \ | |
0110f2b8 | 5986 | X(inc_sp,00dd, f10d0d00), \ |
c19d1205 ZW |
5987 | X(ldmia, c800, e8900000), \ |
5988 | X(ldr, 6800, f8500000), \ | |
5989 | X(ldrb, 7800, f8100000), \ | |
5990 | X(ldrh, 8800, f8300000), \ | |
5991 | X(ldrsb, 5600, f9100000), \ | |
5992 | X(ldrsh, 5e00, f9300000), \ | |
0110f2b8 PB |
5993 | X(ldr_pc,4800, f85f0000), \ |
5994 | X(ldr_pc2,4800, f85f0000), \ | |
5995 | X(ldr_sp,9800, f85d0000), \ | |
c19d1205 ZW |
5996 | X(lsl, 0000, fa00f000), \ |
5997 | X(lsls, 0000, fa10f000), \ | |
5998 | X(lsr, 0800, fa20f000), \ | |
5999 | X(lsrs, 0800, fa30f000), \ | |
6000 | X(mov, 2000, ea4f0000), \ | |
6001 | X(movs, 2000, ea5f0000), \ | |
6002 | X(mul, 4340, fb00f000), \ | |
6003 | X(muls, 4340, ffffffff), /* no 32b muls */ \ | |
6004 | X(mvn, 43c0, ea6f0000), \ | |
6005 | X(mvns, 43c0, ea7f0000), \ | |
6006 | X(neg, 4240, f1c00000), /* rsb #0 */ \ | |
6007 | X(negs, 4240, f1d00000), /* rsbs #0 */ \ | |
6008 | X(orr, 4300, ea400000), \ | |
6009 | X(orrs, 4300, ea500000), \ | |
e9f89963 PB |
6010 | X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \ |
6011 | X(push, b400, e92d0000), /* stmdb sp!,... */ \ | |
c19d1205 ZW |
6012 | X(rev, ba00, fa90f080), \ |
6013 | X(rev16, ba40, fa90f090), \ | |
6014 | X(revsh, bac0, fa90f0b0), \ | |
6015 | X(ror, 41c0, fa60f000), \ | |
6016 | X(rors, 41c0, fa70f000), \ | |
6017 | X(sbc, 4180, eb600000), \ | |
6018 | X(sbcs, 4180, eb700000), \ | |
6019 | X(stmia, c000, e8800000), \ | |
6020 | X(str, 6000, f8400000), \ | |
6021 | X(strb, 7000, f8000000), \ | |
6022 | X(strh, 8000, f8200000), \ | |
0110f2b8 | 6023 | X(str_sp,9000, f84d0000), \ |
c19d1205 ZW |
6024 | X(sub, 1e00, eba00000), \ |
6025 | X(subs, 1e00, ebb00000), \ | |
0110f2b8 PB |
6026 | X(subi, 8000, f1a00000), \ |
6027 | X(subis, 8000, f1b00000), \ | |
c19d1205 ZW |
6028 | X(sxtb, b240, fa4ff080), \ |
6029 | X(sxth, b200, fa0ff080), \ | |
6030 | X(tst, 4200, ea100f00), \ | |
6031 | X(uxtb, b2c0, fa5ff080), \ | |
6032 | X(uxth, b280, fa1ff080), \ | |
6033 | X(nop, bf00, f3af8000), \ | |
6034 | X(yield, bf10, f3af8001), \ | |
6035 | X(wfe, bf20, f3af8002), \ | |
6036 | X(wfi, bf30, f3af8003), \ | |
6037 | X(sev, bf40, f3af9004), /* typo, 8004? */ | |
6038 | ||
6039 | /* To catch errors in encoding functions, the codes are all offset by | |
6040 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
6041 | as 16-bit instructions. */ | |
6042 | #define X(a,b,c) T_MNEM_##a | |
6043 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; | |
6044 | #undef X | |
6045 | ||
6046 | #define X(a,b,c) 0x##b | |
6047 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
6048 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
6049 | #undef X | |
6050 | ||
6051 | #define X(a,b,c) 0x##c | |
6052 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
6053 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) | |
6054 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
6055 | #undef X | |
6056 | #undef T16_32_TAB | |
6057 | ||
6058 | /* Thumb instruction encoders, in alphabetical order. */ | |
6059 | ||
92e90b6e PB |
6060 | /* ADDW or SUBW. */ |
6061 | static void | |
6062 | do_t_add_sub_w (void) | |
6063 | { | |
6064 | int Rd, Rn; | |
6065 | ||
6066 | Rd = inst.operands[0].reg; | |
6067 | Rn = inst.operands[1].reg; | |
6068 | ||
6069 | constraint (Rd == 15, _("PC not allowed as destination")); | |
6070 | inst.instruction |= (Rn << 16) | (Rd << 8); | |
6071 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
6072 | } | |
6073 | ||
c19d1205 ZW |
6074 | /* Parse an add or subtract instruction. We get here with inst.instruction |
6075 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
6076 | ||
6077 | static void | |
6078 | do_t_add_sub (void) | |
6079 | { | |
6080 | int Rd, Rs, Rn; | |
6081 | ||
6082 | Rd = inst.operands[0].reg; | |
6083 | Rs = (inst.operands[1].present | |
6084 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
6085 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
6086 | ||
6087 | if (unified_syntax) | |
6088 | { | |
0110f2b8 PB |
6089 | bfd_boolean flags; |
6090 | bfd_boolean narrow; | |
6091 | int opcode; | |
6092 | ||
6093 | flags = (inst.instruction == T_MNEM_adds | |
6094 | || inst.instruction == T_MNEM_subs); | |
6095 | if (flags) | |
6096 | narrow = (current_it_mask == 0); | |
6097 | else | |
6098 | narrow = (current_it_mask != 0); | |
c19d1205 | 6099 | if (!inst.operands[2].isreg) |
b99bd4ef | 6100 | { |
0110f2b8 PB |
6101 | opcode = 0; |
6102 | if (inst.size_req != 4) | |
6103 | { | |
6104 | int add; | |
6105 | ||
6106 | add = (inst.instruction == T_MNEM_add | |
6107 | || inst.instruction == T_MNEM_adds); | |
6108 | /* Attempt to use a narrow opcode, with relaxation if | |
6109 | appropriate. */ | |
6110 | if (Rd == REG_SP && Rs == REG_SP && !flags) | |
6111 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
6112 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
6113 | opcode = T_MNEM_add_sp; | |
6114 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
6115 | opcode = T_MNEM_add_pc; | |
6116 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
6117 | { | |
6118 | if (flags) | |
6119 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
6120 | else | |
6121 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
6122 | } | |
6123 | if (opcode) | |
6124 | { | |
6125 | inst.instruction = THUMB_OP16(opcode); | |
6126 | inst.instruction |= (Rd << 4) | Rs; | |
6127 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
6128 | if (inst.size_req != 2) | |
6129 | inst.relax = opcode; | |
6130 | } | |
6131 | else | |
6132 | constraint (inst.size_req == 2, BAD_HIREG); | |
6133 | } | |
6134 | if (inst.size_req == 4 | |
6135 | || (inst.size_req != 2 && !opcode)) | |
6136 | { | |
6137 | /* ??? Convert large immediates to addw/subw. */ | |
6138 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6139 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
6140 | inst.instruction |= inst.operands[0].reg << 8; | |
6141 | inst.instruction |= inst.operands[1].reg << 16; | |
6142 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
6143 | } | |
b99bd4ef | 6144 | } |
c19d1205 ZW |
6145 | else |
6146 | { | |
6147 | Rn = inst.operands[2].reg; | |
6148 | /* See if we can do this with a 16-bit instruction. */ | |
6149 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
6150 | { | |
e27ec89e PB |
6151 | if (Rd > 7 || Rs > 7 || Rn > 7) |
6152 | narrow = FALSE; | |
6153 | ||
6154 | if (narrow) | |
c19d1205 | 6155 | { |
e27ec89e PB |
6156 | inst.instruction = ((inst.instruction == T_MNEM_adds |
6157 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
6158 | ? T_OPCODE_ADD_R3 |
6159 | : T_OPCODE_SUB_R3); | |
6160 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
6161 | return; | |
6162 | } | |
b99bd4ef | 6163 | |
c19d1205 ZW |
6164 | if (inst.instruction == T_MNEM_add) |
6165 | { | |
6166 | if (Rd == Rs) | |
6167 | { | |
6168 | inst.instruction = T_OPCODE_ADD_HI; | |
6169 | inst.instruction |= (Rd & 8) << 4; | |
6170 | inst.instruction |= (Rd & 7); | |
6171 | inst.instruction |= Rn << 3; | |
6172 | return; | |
6173 | } | |
6174 | /* ... because addition is commutative! */ | |
6175 | else if (Rd == Rn) | |
6176 | { | |
6177 | inst.instruction = T_OPCODE_ADD_HI; | |
6178 | inst.instruction |= (Rd & 8) << 4; | |
6179 | inst.instruction |= (Rd & 7); | |
6180 | inst.instruction |= Rs << 3; | |
6181 | return; | |
6182 | } | |
6183 | } | |
6184 | } | |
6185 | /* If we get here, it can't be done in 16 bits. */ | |
6186 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
6187 | _("shift must be constant")); | |
6188 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6189 | inst.instruction |= Rd << 8; | |
6190 | inst.instruction |= Rs << 16; | |
6191 | encode_thumb32_shifted_operand (2); | |
6192 | } | |
6193 | } | |
6194 | else | |
6195 | { | |
6196 | constraint (inst.instruction == T_MNEM_adds | |
6197 | || inst.instruction == T_MNEM_subs, | |
6198 | BAD_THUMB32); | |
b99bd4ef | 6199 | |
c19d1205 | 6200 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 6201 | { |
c19d1205 ZW |
6202 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
6203 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
6204 | BAD_HIREG); | |
6205 | ||
6206 | inst.instruction = (inst.instruction == T_MNEM_add | |
6207 | ? 0x0000 : 0x8000); | |
6208 | inst.instruction |= (Rd << 4) | Rs; | |
6209 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
6210 | return; |
6211 | } | |
6212 | ||
c19d1205 ZW |
6213 | Rn = inst.operands[2].reg; |
6214 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 6215 | |
c19d1205 ZW |
6216 | /* We now have Rd, Rs, and Rn set to registers. */ |
6217 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 6218 | { |
c19d1205 ZW |
6219 | /* Can't do this for SUB. */ |
6220 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
6221 | inst.instruction = T_OPCODE_ADD_HI; | |
6222 | inst.instruction |= (Rd & 8) << 4; | |
6223 | inst.instruction |= (Rd & 7); | |
6224 | if (Rs == Rd) | |
6225 | inst.instruction |= Rn << 3; | |
6226 | else if (Rn == Rd) | |
6227 | inst.instruction |= Rs << 3; | |
6228 | else | |
6229 | constraint (1, _("dest must overlap one source register")); | |
6230 | } | |
6231 | else | |
6232 | { | |
6233 | inst.instruction = (inst.instruction == T_MNEM_add | |
6234 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
6235 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 6236 | } |
b99bd4ef | 6237 | } |
b99bd4ef NC |
6238 | } |
6239 | ||
c19d1205 ZW |
6240 | static void |
6241 | do_t_adr (void) | |
6242 | { | |
0110f2b8 PB |
6243 | if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7) |
6244 | { | |
6245 | /* Defer to section relaxation. */ | |
6246 | inst.relax = inst.instruction; | |
6247 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6248 | inst.instruction |= inst.operands[0].reg << 4; | |
6249 | } | |
6250 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 6251 | { |
0110f2b8 | 6252 | /* Generate a 32-bit opcode. */ |
e9f89963 PB |
6253 | inst.instruction = THUMB_OP32 (inst.instruction); |
6254 | inst.instruction |= inst.operands[0].reg << 8; | |
6255 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; | |
6256 | inst.reloc.pc_rel = 1; | |
6257 | } | |
6258 | else | |
6259 | { | |
0110f2b8 | 6260 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
6261 | inst.instruction = THUMB_OP16 (inst.instruction); |
6262 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
6263 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
6264 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 6265 | |
e9f89963 PB |
6266 | inst.instruction |= inst.operands[0].reg << 4; |
6267 | } | |
c19d1205 | 6268 | } |
b99bd4ef | 6269 | |
c19d1205 ZW |
6270 | /* Arithmetic instructions for which there is just one 16-bit |
6271 | instruction encoding, and it allows only two low registers. | |
6272 | For maximal compatibility with ARM syntax, we allow three register | |
6273 | operands even when Thumb-32 instructions are not available, as long | |
6274 | as the first two are identical. For instance, both "sbc r0,r1" and | |
6275 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 6276 | static void |
c19d1205 | 6277 | do_t_arit3 (void) |
b99bd4ef | 6278 | { |
c19d1205 | 6279 | int Rd, Rs, Rn; |
b99bd4ef | 6280 | |
c19d1205 ZW |
6281 | Rd = inst.operands[0].reg; |
6282 | Rs = (inst.operands[1].present | |
6283 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
6284 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
6285 | Rn = inst.operands[2].reg; | |
b99bd4ef | 6286 | |
c19d1205 | 6287 | if (unified_syntax) |
b99bd4ef | 6288 | { |
c19d1205 ZW |
6289 | if (!inst.operands[2].isreg) |
6290 | { | |
6291 | /* For an immediate, we always generate a 32-bit opcode; | |
6292 | section relaxation will shrink it later if possible. */ | |
6293 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6294 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
6295 | inst.instruction |= Rd << 8; | |
6296 | inst.instruction |= Rs << 16; | |
6297 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
6298 | } | |
6299 | else | |
6300 | { | |
e27ec89e PB |
6301 | bfd_boolean narrow; |
6302 | ||
c19d1205 | 6303 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e PB |
6304 | if (THUMB_SETS_FLAGS (inst.instruction)) |
6305 | narrow = current_it_mask == 0; | |
6306 | else | |
6307 | narrow = current_it_mask != 0; | |
6308 | ||
6309 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
6310 | narrow = FALSE; | |
6311 | if (inst.operands[2].shifted) | |
6312 | narrow = FALSE; | |
6313 | if (inst.size_req == 4) | |
6314 | narrow = FALSE; | |
6315 | ||
6316 | if (narrow | |
c19d1205 ZW |
6317 | && Rd == Rs) |
6318 | { | |
6319 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6320 | inst.instruction |= Rd; | |
6321 | inst.instruction |= Rn << 3; | |
6322 | return; | |
6323 | } | |
b99bd4ef | 6324 | |
c19d1205 ZW |
6325 | /* If we get here, it can't be done in 16 bits. */ |
6326 | constraint (inst.operands[2].shifted | |
6327 | && inst.operands[2].immisreg, | |
6328 | _("shift must be constant")); | |
6329 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6330 | inst.instruction |= Rd << 8; | |
6331 | inst.instruction |= Rs << 16; | |
6332 | encode_thumb32_shifted_operand (2); | |
6333 | } | |
a737bd4d | 6334 | } |
c19d1205 | 6335 | else |
b99bd4ef | 6336 | { |
c19d1205 ZW |
6337 | /* On its face this is a lie - the instruction does set the |
6338 | flags. However, the only supported mnemonic in this mode | |
6339 | says it doesn't. */ | |
6340 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 6341 | |
c19d1205 ZW |
6342 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
6343 | _("unshifted register required")); | |
6344 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
6345 | constraint (Rd != Rs, | |
6346 | _("dest and source1 must be the same register")); | |
a737bd4d | 6347 | |
c19d1205 ZW |
6348 | inst.instruction = THUMB_OP16 (inst.instruction); |
6349 | inst.instruction |= Rd; | |
6350 | inst.instruction |= Rn << 3; | |
b99bd4ef | 6351 | } |
a737bd4d | 6352 | } |
b99bd4ef | 6353 | |
c19d1205 ZW |
6354 | /* Similarly, but for instructions where the arithmetic operation is |
6355 | commutative, so we can allow either of them to be different from | |
6356 | the destination operand in a 16-bit instruction. For instance, all | |
6357 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
6358 | accepted. */ | |
6359 | static void | |
6360 | do_t_arit3c (void) | |
a737bd4d | 6361 | { |
c19d1205 | 6362 | int Rd, Rs, Rn; |
b99bd4ef | 6363 | |
c19d1205 ZW |
6364 | Rd = inst.operands[0].reg; |
6365 | Rs = (inst.operands[1].present | |
6366 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
6367 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
6368 | Rn = inst.operands[2].reg; | |
a737bd4d | 6369 | |
c19d1205 | 6370 | if (unified_syntax) |
a737bd4d | 6371 | { |
c19d1205 | 6372 | if (!inst.operands[2].isreg) |
b99bd4ef | 6373 | { |
c19d1205 ZW |
6374 | /* For an immediate, we always generate a 32-bit opcode; |
6375 | section relaxation will shrink it later if possible. */ | |
6376 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6377 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
6378 | inst.instruction |= Rd << 8; | |
6379 | inst.instruction |= Rs << 16; | |
6380 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 6381 | } |
c19d1205 | 6382 | else |
a737bd4d | 6383 | { |
e27ec89e PB |
6384 | bfd_boolean narrow; |
6385 | ||
c19d1205 | 6386 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e PB |
6387 | if (THUMB_SETS_FLAGS (inst.instruction)) |
6388 | narrow = current_it_mask == 0; | |
6389 | else | |
6390 | narrow = current_it_mask != 0; | |
6391 | ||
6392 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
6393 | narrow = FALSE; | |
6394 | if (inst.operands[2].shifted) | |
6395 | narrow = FALSE; | |
6396 | if (inst.size_req == 4) | |
6397 | narrow = FALSE; | |
6398 | ||
6399 | if (narrow) | |
a737bd4d | 6400 | { |
c19d1205 | 6401 | if (Rd == Rs) |
a737bd4d | 6402 | { |
c19d1205 ZW |
6403 | inst.instruction = THUMB_OP16 (inst.instruction); |
6404 | inst.instruction |= Rd; | |
6405 | inst.instruction |= Rn << 3; | |
6406 | return; | |
a737bd4d | 6407 | } |
c19d1205 | 6408 | if (Rd == Rn) |
a737bd4d | 6409 | { |
c19d1205 ZW |
6410 | inst.instruction = THUMB_OP16 (inst.instruction); |
6411 | inst.instruction |= Rd; | |
6412 | inst.instruction |= Rs << 3; | |
6413 | return; | |
a737bd4d NC |
6414 | } |
6415 | } | |
c19d1205 ZW |
6416 | |
6417 | /* If we get here, it can't be done in 16 bits. */ | |
6418 | constraint (inst.operands[2].shifted | |
6419 | && inst.operands[2].immisreg, | |
6420 | _("shift must be constant")); | |
6421 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6422 | inst.instruction |= Rd << 8; | |
6423 | inst.instruction |= Rs << 16; | |
6424 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 6425 | } |
b99bd4ef | 6426 | } |
c19d1205 ZW |
6427 | else |
6428 | { | |
6429 | /* On its face this is a lie - the instruction does set the | |
6430 | flags. However, the only supported mnemonic in this mode | |
6431 | says it doesn't. */ | |
6432 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 6433 | |
c19d1205 ZW |
6434 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
6435 | _("unshifted register required")); | |
6436 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
6437 | ||
6438 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6439 | inst.instruction |= Rd; | |
6440 | ||
6441 | if (Rd == Rs) | |
6442 | inst.instruction |= Rn << 3; | |
6443 | else if (Rd == Rn) | |
6444 | inst.instruction |= Rs << 3; | |
6445 | else | |
6446 | constraint (1, _("dest must overlap one source register")); | |
6447 | } | |
a737bd4d NC |
6448 | } |
6449 | ||
c19d1205 ZW |
6450 | static void |
6451 | do_t_bfc (void) | |
a737bd4d | 6452 | { |
c19d1205 ZW |
6453 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
6454 | constraint (msb > 32, _("bit-field extends past end of register")); | |
6455 | /* The instruction encoding stores the LSB and MSB, | |
6456 | not the LSB and width. */ | |
6457 | inst.instruction |= inst.operands[0].reg << 8; | |
6458 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; | |
6459 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
6460 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
6461 | } |
6462 | ||
c19d1205 ZW |
6463 | static void |
6464 | do_t_bfi (void) | |
b99bd4ef | 6465 | { |
c19d1205 | 6466 | unsigned int msb; |
b99bd4ef | 6467 | |
c19d1205 ZW |
6468 | /* #0 in second position is alternative syntax for bfc, which is |
6469 | the same instruction but with REG_PC in the Rm field. */ | |
6470 | if (!inst.operands[1].isreg) | |
6471 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 6472 | |
c19d1205 ZW |
6473 | msb = inst.operands[2].imm + inst.operands[3].imm; |
6474 | constraint (msb > 32, _("bit-field extends past end of register")); | |
6475 | /* The instruction encoding stores the LSB and MSB, | |
6476 | not the LSB and width. */ | |
6477 | inst.instruction |= inst.operands[0].reg << 8; | |
6478 | inst.instruction |= inst.operands[1].reg << 16; | |
6479 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; | |
6480 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
6481 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
6482 | } |
6483 | ||
c19d1205 ZW |
6484 | static void |
6485 | do_t_bfx (void) | |
b99bd4ef | 6486 | { |
c19d1205 ZW |
6487 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
6488 | _("bit-field extends past end of register")); | |
6489 | inst.instruction |= inst.operands[0].reg << 8; | |
6490 | inst.instruction |= inst.operands[1].reg << 16; | |
6491 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; | |
6492 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
6493 | inst.instruction |= inst.operands[3].imm - 1; | |
6494 | } | |
b99bd4ef | 6495 | |
c19d1205 ZW |
6496 | /* ARM V5 Thumb BLX (argument parse) |
6497 | BLX <target_addr> which is BLX(1) | |
6498 | BLX <Rm> which is BLX(2) | |
6499 | Unfortunately, there are two different opcodes for this mnemonic. | |
6500 | So, the insns[].value is not used, and the code here zaps values | |
6501 | into inst.instruction. | |
b99bd4ef | 6502 | |
c19d1205 ZW |
6503 | ??? How to take advantage of the additional two bits of displacement |
6504 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 6505 | |
c19d1205 ZW |
6506 | static void |
6507 | do_t_blx (void) | |
6508 | { | |
6509 | if (inst.operands[0].isreg) | |
6510 | /* We have a register, so this is BLX(2). */ | |
6511 | inst.instruction |= inst.operands[0].reg << 3; | |
b99bd4ef NC |
6512 | else |
6513 | { | |
c19d1205 | 6514 | /* No register. This must be BLX(1). */ |
2fc8bdac | 6515 | inst.instruction = 0xf000e800; |
39b41c9c PB |
6516 | #ifdef OBJ_ELF |
6517 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
6518 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
6519 | else | |
6520 | #endif | |
6521 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; | |
c19d1205 | 6522 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
6523 | } |
6524 | } | |
6525 | ||
c19d1205 ZW |
6526 | static void |
6527 | do_t_branch (void) | |
b99bd4ef | 6528 | { |
0110f2b8 PB |
6529 | int opcode; |
6530 | if (inst.cond != COND_ALWAYS) | |
6531 | opcode = T_MNEM_bcond; | |
6532 | else | |
6533 | opcode = inst.instruction; | |
6534 | ||
6535 | if (unified_syntax && inst.size_req == 4) | |
c19d1205 | 6536 | { |
0110f2b8 | 6537 | inst.instruction = THUMB_OP32(opcode); |
c19d1205 | 6538 | if (inst.cond == COND_ALWAYS) |
0110f2b8 | 6539 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
6540 | else |
6541 | { | |
6542 | assert (inst.cond != 0xF); | |
0110f2b8 | 6543 | inst.instruction |= inst.cond << 22; |
c19d1205 ZW |
6544 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20; |
6545 | } | |
6546 | } | |
b99bd4ef NC |
6547 | else |
6548 | { | |
0110f2b8 | 6549 | inst.instruction = THUMB_OP16(opcode); |
c19d1205 ZW |
6550 | if (inst.cond == COND_ALWAYS) |
6551 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
6552 | else | |
b99bd4ef | 6553 | { |
0110f2b8 | 6554 | inst.instruction |= inst.cond << 8; |
c19d1205 | 6555 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 6556 | } |
0110f2b8 PB |
6557 | /* Allow section relaxation. */ |
6558 | if (unified_syntax && inst.size_req != 2) | |
6559 | inst.relax = opcode; | |
b99bd4ef | 6560 | } |
c19d1205 ZW |
6561 | |
6562 | inst.reloc.pc_rel = 1; | |
b99bd4ef NC |
6563 | } |
6564 | ||
6565 | static void | |
c19d1205 | 6566 | do_t_bkpt (void) |
b99bd4ef | 6567 | { |
c19d1205 | 6568 | if (inst.operands[0].present) |
b99bd4ef | 6569 | { |
c19d1205 ZW |
6570 | constraint (inst.operands[0].imm > 255, |
6571 | _("immediate value out of range")); | |
6572 | inst.instruction |= inst.operands[0].imm; | |
b99bd4ef | 6573 | } |
b99bd4ef NC |
6574 | } |
6575 | ||
6576 | static void | |
c19d1205 | 6577 | do_t_branch23 (void) |
b99bd4ef | 6578 | { |
c19d1205 | 6579 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; |
90e4755a RE |
6580 | inst.reloc.pc_rel = 1; |
6581 | ||
c19d1205 ZW |
6582 | /* If the destination of the branch is a defined symbol which does not have |
6583 | the THUMB_FUNC attribute, then we must be calling a function which has | |
6584 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
6585 | function and change the branch to refer to that function instead. */ | |
6586 | if ( inst.reloc.exp.X_op == O_symbol | |
6587 | && inst.reloc.exp.X_add_symbol != NULL | |
6588 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
6589 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
6590 | inst.reloc.exp.X_add_symbol = | |
6591 | find_real_start (inst.reloc.exp.X_add_symbol); | |
90e4755a RE |
6592 | } |
6593 | ||
6594 | static void | |
c19d1205 | 6595 | do_t_bx (void) |
90e4755a | 6596 | { |
c19d1205 ZW |
6597 | inst.instruction |= inst.operands[0].reg << 3; |
6598 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
6599 | should cause the alignment to be checked once it is known. This is | |
6600 | because BX PC only works if the instruction is word aligned. */ | |
6601 | } | |
90e4755a | 6602 | |
c19d1205 ZW |
6603 | static void |
6604 | do_t_bxj (void) | |
6605 | { | |
6606 | if (inst.operands[0].reg == REG_PC) | |
6607 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
90e4755a | 6608 | |
c19d1205 | 6609 | inst.instruction |= inst.operands[0].reg << 16; |
90e4755a RE |
6610 | } |
6611 | ||
6612 | static void | |
c19d1205 | 6613 | do_t_clz (void) |
90e4755a | 6614 | { |
c19d1205 ZW |
6615 | inst.instruction |= inst.operands[0].reg << 8; |
6616 | inst.instruction |= inst.operands[1].reg << 16; | |
6617 | inst.instruction |= inst.operands[1].reg; | |
6618 | } | |
90e4755a | 6619 | |
c19d1205 ZW |
6620 | static void |
6621 | do_t_cpsi (void) | |
6622 | { | |
6623 | if (unified_syntax | |
6624 | && (inst.operands[1].present || inst.size_req == 4)) | |
90e4755a | 6625 | { |
c19d1205 ZW |
6626 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
6627 | inst.instruction = 0xf3af8000; | |
6628 | inst.instruction |= imod << 9; | |
6629 | inst.instruction |= inst.operands[0].imm << 5; | |
6630 | if (inst.operands[1].present) | |
6631 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 6632 | } |
c19d1205 | 6633 | else |
90e4755a | 6634 | { |
c19d1205 ZW |
6635 | constraint (inst.operands[1].present, |
6636 | _("Thumb does not support the 2-argument " | |
6637 | "form of this instruction")); | |
6638 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 6639 | } |
90e4755a RE |
6640 | } |
6641 | ||
c19d1205 ZW |
6642 | /* THUMB CPY instruction (argument parse). */ |
6643 | ||
90e4755a | 6644 | static void |
c19d1205 | 6645 | do_t_cpy (void) |
90e4755a | 6646 | { |
c19d1205 | 6647 | if (inst.size_req == 4) |
90e4755a | 6648 | { |
c19d1205 ZW |
6649 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
6650 | inst.instruction |= inst.operands[0].reg << 8; | |
6651 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 6652 | } |
c19d1205 | 6653 | else |
90e4755a | 6654 | { |
c19d1205 ZW |
6655 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
6656 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
6657 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 6658 | } |
90e4755a RE |
6659 | } |
6660 | ||
90e4755a | 6661 | static void |
c19d1205 | 6662 | do_t_czb (void) |
90e4755a | 6663 | { |
c19d1205 ZW |
6664 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
6665 | inst.instruction |= inst.operands[0].reg; | |
6666 | inst.reloc.pc_rel = 1; | |
6667 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
6668 | } | |
90e4755a | 6669 | |
c19d1205 ZW |
6670 | static void |
6671 | do_t_hint (void) | |
6672 | { | |
6673 | if (unified_syntax && inst.size_req == 4) | |
6674 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6675 | else | |
6676 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6677 | } | |
90e4755a | 6678 | |
c19d1205 ZW |
6679 | static void |
6680 | do_t_it (void) | |
6681 | { | |
6682 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e PB |
6683 | |
6684 | current_it_mask = (inst.instruction & 0xf) | 0x10; | |
6685 | current_cc = cond; | |
6686 | ||
6687 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 6688 | if ((cond & 0x1) == 0x0) |
90e4755a | 6689 | { |
c19d1205 | 6690 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 6691 | |
c19d1205 ZW |
6692 | if ((mask & 0x7) == 0) |
6693 | /* no conversion needed */; | |
6694 | else if ((mask & 0x3) == 0) | |
e27ec89e PB |
6695 | mask ^= 0x8; |
6696 | else if ((mask & 0x1) == 0) | |
6697 | mask ^= 0xC; | |
c19d1205 | 6698 | else |
e27ec89e | 6699 | mask ^= 0xE; |
90e4755a | 6700 | |
e27ec89e PB |
6701 | inst.instruction &= 0xfff0; |
6702 | inst.instruction |= mask; | |
c19d1205 | 6703 | } |
90e4755a | 6704 | |
c19d1205 ZW |
6705 | inst.instruction |= cond << 4; |
6706 | } | |
90e4755a | 6707 | |
c19d1205 ZW |
6708 | static void |
6709 | do_t_ldmstm (void) | |
6710 | { | |
6711 | /* This really doesn't seem worth it. */ | |
6712 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
6713 | _("expression too complex")); | |
6714 | constraint (inst.operands[1].writeback, | |
6715 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 6716 | |
c19d1205 ZW |
6717 | if (unified_syntax) |
6718 | { | |
6719 | /* See if we can use a 16-bit instruction. */ | |
6720 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
6721 | && inst.size_req != 4 | |
6722 | && inst.operands[0].reg <= 7 | |
6723 | && !(inst.operands[1].imm & ~0xff) | |
6724 | && (inst.instruction == T_MNEM_stmia | |
6725 | ? inst.operands[0].writeback | |
6726 | : (inst.operands[0].writeback | |
6727 | == !(inst.operands[1].imm & (1 << inst.operands[0].reg))))) | |
90e4755a | 6728 | { |
c19d1205 ZW |
6729 | if (inst.instruction == T_MNEM_stmia |
6730 | && (inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
6731 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
6732 | as_warn (_("value stored for r%d is UNPREDICTABLE"), | |
6733 | inst.operands[0].reg); | |
90e4755a | 6734 | |
c19d1205 ZW |
6735 | inst.instruction = THUMB_OP16 (inst.instruction); |
6736 | inst.instruction |= inst.operands[0].reg << 8; | |
6737 | inst.instruction |= inst.operands[1].imm; | |
6738 | } | |
6739 | else | |
6740 | { | |
6741 | if (inst.operands[1].imm & (1 << 13)) | |
6742 | as_warn (_("SP should not be in register list")); | |
6743 | if (inst.instruction == T_MNEM_stmia) | |
90e4755a | 6744 | { |
c19d1205 ZW |
6745 | if (inst.operands[1].imm & (1 << 15)) |
6746 | as_warn (_("PC should not be in register list")); | |
6747 | if (inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
6748 | as_warn (_("value stored for r%d is UNPREDICTABLE"), | |
6749 | inst.operands[0].reg); | |
90e4755a RE |
6750 | } |
6751 | else | |
6752 | { | |
c19d1205 ZW |
6753 | if (inst.operands[1].imm & (1 << 14) |
6754 | && inst.operands[1].imm & (1 << 15)) | |
6755 | as_warn (_("LR and PC should not both be in register list")); | |
6756 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
6757 | && inst.operands[0].writeback) | |
6758 | as_warn (_("base register should not be in register list " | |
6759 | "when written back")); | |
90e4755a | 6760 | } |
c19d1205 ZW |
6761 | if (inst.instruction < 0xffff) |
6762 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6763 | inst.instruction |= inst.operands[0].reg << 16; | |
6764 | inst.instruction |= inst.operands[1].imm; | |
6765 | if (inst.operands[0].writeback) | |
6766 | inst.instruction |= WRITE_BACK; | |
90e4755a RE |
6767 | } |
6768 | } | |
c19d1205 | 6769 | else |
90e4755a | 6770 | { |
c19d1205 ZW |
6771 | constraint (inst.operands[0].reg > 7 |
6772 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
6773 | if (inst.instruction == T_MNEM_stmia) | |
f03698e6 | 6774 | { |
c19d1205 ZW |
6775 | if (!inst.operands[0].writeback) |
6776 | as_warn (_("this instruction will write back the base register")); | |
6777 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
6778 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
6779 | as_warn (_("value stored for r%d is UNPREDICTABLE"), | |
6780 | inst.operands[0].reg); | |
f03698e6 | 6781 | } |
c19d1205 | 6782 | else |
90e4755a | 6783 | { |
c19d1205 ZW |
6784 | if (!inst.operands[0].writeback |
6785 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
6786 | as_warn (_("this instruction will write back the base register")); | |
6787 | else if (inst.operands[0].writeback | |
6788 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
6789 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
6790 | } |
6791 | ||
c19d1205 ZW |
6792 | inst.instruction = THUMB_OP16 (inst.instruction); |
6793 | inst.instruction |= inst.operands[0].reg << 8; | |
6794 | inst.instruction |= inst.operands[1].imm; | |
6795 | } | |
6796 | } | |
e28cd48c | 6797 | |
c19d1205 ZW |
6798 | static void |
6799 | do_t_ldrex (void) | |
6800 | { | |
6801 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
6802 | || inst.operands[1].postind || inst.operands[1].writeback | |
6803 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
6804 | || inst.operands[1].negative, | |
01cfc07f | 6805 | BAD_ADDR_MODE); |
e28cd48c | 6806 | |
c19d1205 ZW |
6807 | inst.instruction |= inst.operands[0].reg << 12; |
6808 | inst.instruction |= inst.operands[1].reg << 16; | |
6809 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
6810 | } | |
e28cd48c | 6811 | |
c19d1205 ZW |
6812 | static void |
6813 | do_t_ldrexd (void) | |
6814 | { | |
6815 | if (!inst.operands[1].present) | |
1cac9012 | 6816 | { |
c19d1205 ZW |
6817 | constraint (inst.operands[0].reg == REG_LR, |
6818 | _("r14 not allowed as first register " | |
6819 | "when second register is omitted")); | |
6820 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 6821 | } |
c19d1205 ZW |
6822 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
6823 | BAD_OVERLAP); | |
b99bd4ef | 6824 | |
c19d1205 ZW |
6825 | inst.instruction |= inst.operands[0].reg << 12; |
6826 | inst.instruction |= inst.operands[1].reg << 8; | |
6827 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
6828 | } |
6829 | ||
6830 | static void | |
c19d1205 | 6831 | do_t_ldst (void) |
b99bd4ef | 6832 | { |
0110f2b8 PB |
6833 | unsigned long opcode; |
6834 | int Rn; | |
6835 | ||
6836 | opcode = inst.instruction; | |
c19d1205 | 6837 | if (unified_syntax) |
b99bd4ef | 6838 | { |
0110f2b8 PB |
6839 | if (inst.operands[1].isreg |
6840 | && !inst.operands[1].writeback | |
c19d1205 ZW |
6841 | && !inst.operands[1].shifted && !inst.operands[1].postind |
6842 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
6843 | && opcode <= 0xffff |
6844 | && inst.size_req != 4) | |
c19d1205 | 6845 | { |
0110f2b8 PB |
6846 | /* Insn may have a 16-bit form. */ |
6847 | Rn = inst.operands[1].reg; | |
6848 | if (inst.operands[1].immisreg) | |
6849 | { | |
6850 | inst.instruction = THUMB_OP16 (opcode); | |
6851 | /* [Rn, Ri] */ | |
6852 | if (Rn <= 7 && inst.operands[1].imm <= 7) | |
6853 | goto op16; | |
6854 | } | |
6855 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
6856 | && opcode != T_MNEM_ldrsb) | |
6857 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
6858 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
6859 | { | |
6860 | /* [Rn, #const] */ | |
6861 | if (Rn > 7) | |
6862 | { | |
6863 | if (Rn == REG_PC) | |
6864 | { | |
6865 | if (inst.reloc.pc_rel) | |
6866 | opcode = T_MNEM_ldr_pc2; | |
6867 | else | |
6868 | opcode = T_MNEM_ldr_pc; | |
6869 | } | |
6870 | else | |
6871 | { | |
6872 | if (opcode == T_MNEM_ldr) | |
6873 | opcode = T_MNEM_ldr_sp; | |
6874 | else | |
6875 | opcode = T_MNEM_str_sp; | |
6876 | } | |
6877 | inst.instruction = inst.operands[0].reg << 8; | |
6878 | } | |
6879 | else | |
6880 | { | |
6881 | inst.instruction = inst.operands[0].reg; | |
6882 | inst.instruction |= inst.operands[1].reg << 3; | |
6883 | } | |
6884 | inst.instruction |= THUMB_OP16 (opcode); | |
6885 | if (inst.size_req == 2) | |
6886 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
6887 | else | |
6888 | inst.relax = opcode; | |
6889 | return; | |
6890 | } | |
c19d1205 | 6891 | } |
0110f2b8 PB |
6892 | /* Definitely a 32-bit variant. */ |
6893 | inst.instruction = THUMB_OP32 (opcode); | |
c19d1205 ZW |
6894 | inst.instruction |= inst.operands[0].reg << 12; |
6895 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
b99bd4ef NC |
6896 | return; |
6897 | } | |
6898 | ||
c19d1205 ZW |
6899 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
6900 | ||
6901 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 6902 | { |
c19d1205 ZW |
6903 | /* Only [Rn,Rm] is acceptable. */ |
6904 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
6905 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
6906 | || inst.operands[1].postind || inst.operands[1].shifted | |
6907 | || inst.operands[1].negative, | |
6908 | _("Thumb does not support this addressing mode")); | |
6909 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6910 | goto op16; | |
b99bd4ef | 6911 | } |
c19d1205 ZW |
6912 | |
6913 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6914 | if (!inst.operands[1].isreg) | |
6915 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
6916 | return; | |
b99bd4ef | 6917 | |
c19d1205 ZW |
6918 | constraint (!inst.operands[1].preind |
6919 | || inst.operands[1].shifted | |
6920 | || inst.operands[1].writeback, | |
6921 | _("Thumb does not support this addressing mode")); | |
6922 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 6923 | { |
c19d1205 ZW |
6924 | constraint (inst.instruction & 0x0600, |
6925 | _("byte or halfword not valid for base register")); | |
6926 | constraint (inst.operands[1].reg == REG_PC | |
6927 | && !(inst.instruction & THUMB_LOAD_BIT), | |
6928 | _("r15 based store not allowed")); | |
6929 | constraint (inst.operands[1].immisreg, | |
6930 | _("invalid base register for register offset")); | |
b99bd4ef | 6931 | |
c19d1205 ZW |
6932 | if (inst.operands[1].reg == REG_PC) |
6933 | inst.instruction = T_OPCODE_LDR_PC; | |
6934 | else if (inst.instruction & THUMB_LOAD_BIT) | |
6935 | inst.instruction = T_OPCODE_LDR_SP; | |
6936 | else | |
6937 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 6938 | |
c19d1205 ZW |
6939 | inst.instruction |= inst.operands[0].reg << 8; |
6940 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
6941 | return; | |
6942 | } | |
90e4755a | 6943 | |
c19d1205 ZW |
6944 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
6945 | if (!inst.operands[1].immisreg) | |
6946 | { | |
6947 | /* Immediate offset. */ | |
6948 | inst.instruction |= inst.operands[0].reg; | |
6949 | inst.instruction |= inst.operands[1].reg << 3; | |
6950 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
6951 | return; | |
6952 | } | |
90e4755a | 6953 | |
c19d1205 ZW |
6954 | /* Register offset. */ |
6955 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
6956 | constraint (inst.operands[1].negative, | |
6957 | _("Thumb does not support this addressing mode")); | |
90e4755a | 6958 | |
c19d1205 ZW |
6959 | op16: |
6960 | switch (inst.instruction) | |
6961 | { | |
6962 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
6963 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
6964 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
6965 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
6966 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
6967 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
6968 | case 0x5600 /* ldrsb */: | |
6969 | case 0x5e00 /* ldrsh */: break; | |
6970 | default: abort (); | |
6971 | } | |
90e4755a | 6972 | |
c19d1205 ZW |
6973 | inst.instruction |= inst.operands[0].reg; |
6974 | inst.instruction |= inst.operands[1].reg << 3; | |
6975 | inst.instruction |= inst.operands[1].imm << 6; | |
6976 | } | |
90e4755a | 6977 | |
c19d1205 ZW |
6978 | static void |
6979 | do_t_ldstd (void) | |
6980 | { | |
6981 | if (!inst.operands[1].present) | |
b99bd4ef | 6982 | { |
c19d1205 ZW |
6983 | inst.operands[1].reg = inst.operands[0].reg + 1; |
6984 | constraint (inst.operands[0].reg == REG_LR, | |
6985 | _("r14 not allowed here")); | |
b99bd4ef | 6986 | } |
c19d1205 ZW |
6987 | inst.instruction |= inst.operands[0].reg << 12; |
6988 | inst.instruction |= inst.operands[1].reg << 8; | |
6989 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
6990 | ||
b99bd4ef NC |
6991 | } |
6992 | ||
c19d1205 ZW |
6993 | static void |
6994 | do_t_ldstt (void) | |
6995 | { | |
6996 | inst.instruction |= inst.operands[0].reg << 12; | |
6997 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
6998 | } | |
a737bd4d | 6999 | |
b99bd4ef | 7000 | static void |
c19d1205 | 7001 | do_t_mla (void) |
b99bd4ef | 7002 | { |
c19d1205 ZW |
7003 | inst.instruction |= inst.operands[0].reg << 8; |
7004 | inst.instruction |= inst.operands[1].reg << 16; | |
7005 | inst.instruction |= inst.operands[2].reg; | |
7006 | inst.instruction |= inst.operands[3].reg << 12; | |
7007 | } | |
b99bd4ef | 7008 | |
c19d1205 ZW |
7009 | static void |
7010 | do_t_mlal (void) | |
7011 | { | |
7012 | inst.instruction |= inst.operands[0].reg << 12; | |
7013 | inst.instruction |= inst.operands[1].reg << 8; | |
7014 | inst.instruction |= inst.operands[2].reg << 16; | |
7015 | inst.instruction |= inst.operands[3].reg; | |
7016 | } | |
b99bd4ef | 7017 | |
c19d1205 ZW |
7018 | static void |
7019 | do_t_mov_cmp (void) | |
7020 | { | |
7021 | if (unified_syntax) | |
b99bd4ef | 7022 | { |
c19d1205 ZW |
7023 | int r0off = (inst.instruction == T_MNEM_mov |
7024 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 7025 | unsigned long opcode; |
3d388997 PB |
7026 | bfd_boolean narrow; |
7027 | bfd_boolean low_regs; | |
7028 | ||
7029 | low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7); | |
0110f2b8 | 7030 | opcode = inst.instruction; |
3d388997 | 7031 | if (current_it_mask) |
0110f2b8 | 7032 | narrow = opcode != T_MNEM_movs; |
3d388997 | 7033 | else |
0110f2b8 | 7034 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
7035 | if (inst.size_req == 4 |
7036 | || inst.operands[1].shifted) | |
7037 | narrow = FALSE; | |
7038 | ||
c19d1205 ZW |
7039 | if (!inst.operands[1].isreg) |
7040 | { | |
0110f2b8 PB |
7041 | /* Immediate operand. */ |
7042 | if (current_it_mask == 0 && opcode == T_MNEM_mov) | |
7043 | narrow = 0; | |
7044 | if (low_regs && narrow) | |
7045 | { | |
7046 | inst.instruction = THUMB_OP16 (opcode); | |
7047 | inst.instruction |= inst.operands[0].reg << 8; | |
7048 | if (inst.size_req == 2) | |
7049 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
7050 | else | |
7051 | inst.relax = opcode; | |
7052 | } | |
7053 | else | |
7054 | { | |
7055 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7056 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
7057 | inst.instruction |= inst.operands[0].reg << r0off; | |
7058 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
7059 | } | |
c19d1205 | 7060 | } |
3d388997 | 7061 | else if (!narrow) |
c19d1205 ZW |
7062 | { |
7063 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7064 | inst.instruction |= inst.operands[0].reg << r0off; | |
7065 | encode_thumb32_shifted_operand (1); | |
7066 | } | |
7067 | else | |
7068 | switch (inst.instruction) | |
7069 | { | |
7070 | case T_MNEM_mov: | |
7071 | inst.instruction = T_OPCODE_MOV_HR; | |
7072 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; | |
7073 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
7074 | inst.instruction |= inst.operands[1].reg << 3; | |
7075 | break; | |
b99bd4ef | 7076 | |
c19d1205 ZW |
7077 | case T_MNEM_movs: |
7078 | /* We know we have low registers at this point. | |
7079 | Generate ADD Rd, Rs, #0. */ | |
7080 | inst.instruction = T_OPCODE_ADD_I3; | |
7081 | inst.instruction |= inst.operands[0].reg; | |
7082 | inst.instruction |= inst.operands[1].reg << 3; | |
7083 | break; | |
7084 | ||
7085 | case T_MNEM_cmp: | |
3d388997 | 7086 | if (low_regs) |
c19d1205 ZW |
7087 | { |
7088 | inst.instruction = T_OPCODE_CMP_LR; | |
7089 | inst.instruction |= inst.operands[0].reg; | |
7090 | inst.instruction |= inst.operands[1].reg << 3; | |
7091 | } | |
7092 | else | |
7093 | { | |
7094 | inst.instruction = T_OPCODE_CMP_HR; | |
7095 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; | |
7096 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
7097 | inst.instruction |= inst.operands[1].reg << 3; | |
7098 | } | |
7099 | break; | |
7100 | } | |
b99bd4ef NC |
7101 | return; |
7102 | } | |
7103 | ||
c19d1205 ZW |
7104 | inst.instruction = THUMB_OP16 (inst.instruction); |
7105 | if (inst.operands[1].isreg) | |
b99bd4ef | 7106 | { |
c19d1205 | 7107 | if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8) |
b99bd4ef | 7108 | { |
c19d1205 ZW |
7109 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
7110 | since a MOV instruction produces unpredictable results. */ | |
7111 | if (inst.instruction == T_OPCODE_MOV_I8) | |
7112 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 7113 | else |
c19d1205 | 7114 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 7115 | |
c19d1205 ZW |
7116 | inst.instruction |= inst.operands[0].reg; |
7117 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
7118 | } |
7119 | else | |
7120 | { | |
c19d1205 ZW |
7121 | if (inst.instruction == T_OPCODE_MOV_I8) |
7122 | inst.instruction = T_OPCODE_MOV_HR; | |
7123 | else | |
7124 | inst.instruction = T_OPCODE_CMP_HR; | |
7125 | do_t_cpy (); | |
b99bd4ef NC |
7126 | } |
7127 | } | |
c19d1205 | 7128 | else |
b99bd4ef | 7129 | { |
c19d1205 ZW |
7130 | constraint (inst.operands[0].reg > 7, |
7131 | _("only lo regs allowed with immediate")); | |
7132 | inst.instruction |= inst.operands[0].reg << 8; | |
7133 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
7134 | } | |
7135 | } | |
b99bd4ef | 7136 | |
c19d1205 ZW |
7137 | static void |
7138 | do_t_mov16 (void) | |
7139 | { | |
7140 | inst.instruction |= inst.operands[0].reg << 8; | |
7141 | inst.instruction |= (inst.operands[1].imm & 0xf000) << 4; | |
7142 | inst.instruction |= (inst.operands[1].imm & 0x0800) << 15; | |
7143 | inst.instruction |= (inst.operands[1].imm & 0x0700) << 4; | |
7144 | inst.instruction |= (inst.operands[1].imm & 0x00ff); | |
7145 | } | |
b99bd4ef | 7146 | |
c19d1205 ZW |
7147 | static void |
7148 | do_t_mvn_tst (void) | |
7149 | { | |
7150 | if (unified_syntax) | |
7151 | { | |
7152 | int r0off = (inst.instruction == T_MNEM_mvn | |
7153 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
7154 | bfd_boolean narrow; |
7155 | ||
7156 | if (inst.size_req == 4 | |
7157 | || inst.instruction > 0xffff | |
7158 | || inst.operands[1].shifted | |
7159 | || inst.operands[0].reg > 7 || inst.operands[1].reg > 7) | |
7160 | narrow = FALSE; | |
7161 | else if (inst.instruction == T_MNEM_cmn) | |
7162 | narrow = TRUE; | |
7163 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
7164 | narrow = (current_it_mask == 0); | |
7165 | else | |
7166 | narrow = (current_it_mask != 0); | |
7167 | ||
c19d1205 | 7168 | if (!inst.operands[1].isreg) |
b99bd4ef | 7169 | { |
c19d1205 ZW |
7170 | /* For an immediate, we always generate a 32-bit opcode; |
7171 | section relaxation will shrink it later if possible. */ | |
7172 | if (inst.instruction < 0xffff) | |
7173 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7174 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
7175 | inst.instruction |= inst.operands[0].reg << r0off; | |
7176 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 7177 | } |
c19d1205 | 7178 | else |
b99bd4ef | 7179 | { |
c19d1205 | 7180 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 7181 | if (narrow) |
b99bd4ef | 7182 | { |
c19d1205 ZW |
7183 | inst.instruction = THUMB_OP16 (inst.instruction); |
7184 | inst.instruction |= inst.operands[0].reg; | |
7185 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef | 7186 | } |
c19d1205 | 7187 | else |
b99bd4ef | 7188 | { |
c19d1205 ZW |
7189 | constraint (inst.operands[1].shifted |
7190 | && inst.operands[1].immisreg, | |
7191 | _("shift must be constant")); | |
7192 | if (inst.instruction < 0xffff) | |
7193 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7194 | inst.instruction |= inst.operands[0].reg << r0off; | |
7195 | encode_thumb32_shifted_operand (1); | |
b99bd4ef | 7196 | } |
b99bd4ef NC |
7197 | } |
7198 | } | |
7199 | else | |
7200 | { | |
c19d1205 ZW |
7201 | constraint (inst.instruction > 0xffff |
7202 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
7203 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
7204 | _("unshifted register required")); | |
7205 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, | |
7206 | BAD_HIREG); | |
b99bd4ef | 7207 | |
c19d1205 ZW |
7208 | inst.instruction = THUMB_OP16 (inst.instruction); |
7209 | inst.instruction |= inst.operands[0].reg; | |
7210 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef | 7211 | } |
b99bd4ef NC |
7212 | } |
7213 | ||
b05fe5cf | 7214 | static void |
c19d1205 | 7215 | do_t_mrs (void) |
b05fe5cf | 7216 | { |
c19d1205 ZW |
7217 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ |
7218 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
7219 | != (PSR_c|PSR_f), | |
7220 | _("'CPSR' or 'SPSR' expected")); | |
7221 | inst.instruction |= inst.operands[0].reg << 8; | |
7222 | inst.instruction |= (inst.operands[1].imm & SPSR_BIT) >> 2; | |
7223 | } | |
b05fe5cf | 7224 | |
c19d1205 ZW |
7225 | static void |
7226 | do_t_msr (void) | |
7227 | { | |
7228 | constraint (!inst.operands[1].isreg, | |
7229 | _("Thumb encoding does not support an immediate here")); | |
7230 | inst.instruction |= (inst.operands[0].imm & SPSR_BIT) >> 2; | |
7231 | inst.instruction |= (inst.operands[0].imm & ~SPSR_BIT) >> 8; | |
7232 | inst.instruction |= inst.operands[1].reg << 16; | |
7233 | } | |
b05fe5cf | 7234 | |
c19d1205 ZW |
7235 | static void |
7236 | do_t_mul (void) | |
7237 | { | |
7238 | if (!inst.operands[2].present) | |
7239 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 7240 | |
c19d1205 ZW |
7241 | /* There is no 32-bit MULS and no 16-bit MUL. */ |
7242 | if (unified_syntax && inst.instruction == T_MNEM_mul) | |
b05fe5cf | 7243 | { |
c19d1205 ZW |
7244 | inst.instruction = THUMB_OP32 (inst.instruction); |
7245 | inst.instruction |= inst.operands[0].reg << 8; | |
7246 | inst.instruction |= inst.operands[1].reg << 16; | |
7247 | inst.instruction |= inst.operands[2].reg << 0; | |
b05fe5cf | 7248 | } |
c19d1205 | 7249 | else |
b05fe5cf | 7250 | { |
c19d1205 ZW |
7251 | constraint (!unified_syntax |
7252 | && inst.instruction == T_MNEM_muls, BAD_THUMB32); | |
7253 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, | |
7254 | BAD_HIREG); | |
b05fe5cf | 7255 | |
c19d1205 ZW |
7256 | inst.instruction = THUMB_OP16 (inst.instruction); |
7257 | inst.instruction |= inst.operands[0].reg; | |
b05fe5cf | 7258 | |
c19d1205 ZW |
7259 | if (inst.operands[0].reg == inst.operands[1].reg) |
7260 | inst.instruction |= inst.operands[2].reg << 3; | |
7261 | else if (inst.operands[0].reg == inst.operands[2].reg) | |
7262 | inst.instruction |= inst.operands[1].reg << 3; | |
7263 | else | |
7264 | constraint (1, _("dest must overlap one source register")); | |
7265 | } | |
7266 | } | |
b05fe5cf | 7267 | |
c19d1205 ZW |
7268 | static void |
7269 | do_t_mull (void) | |
7270 | { | |
7271 | inst.instruction |= inst.operands[0].reg << 12; | |
7272 | inst.instruction |= inst.operands[1].reg << 8; | |
7273 | inst.instruction |= inst.operands[2].reg << 16; | |
7274 | inst.instruction |= inst.operands[3].reg; | |
b05fe5cf | 7275 | |
c19d1205 ZW |
7276 | if (inst.operands[0].reg == inst.operands[1].reg) |
7277 | as_tsktsk (_("rdhi and rdlo must be different")); | |
7278 | } | |
b05fe5cf | 7279 | |
c19d1205 ZW |
7280 | static void |
7281 | do_t_nop (void) | |
7282 | { | |
7283 | if (unified_syntax) | |
7284 | { | |
7285 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 7286 | { |
c19d1205 ZW |
7287 | inst.instruction = THUMB_OP32 (inst.instruction); |
7288 | inst.instruction |= inst.operands[0].imm; | |
7289 | } | |
7290 | else | |
7291 | { | |
7292 | inst.instruction = THUMB_OP16 (inst.instruction); | |
7293 | inst.instruction |= inst.operands[0].imm << 4; | |
7294 | } | |
7295 | } | |
7296 | else | |
7297 | { | |
7298 | constraint (inst.operands[0].present, | |
7299 | _("Thumb does not support NOP with hints")); | |
7300 | inst.instruction = 0x46c0; | |
7301 | } | |
7302 | } | |
b05fe5cf | 7303 | |
c19d1205 ZW |
7304 | static void |
7305 | do_t_neg (void) | |
7306 | { | |
7307 | if (unified_syntax) | |
7308 | { | |
3d388997 PB |
7309 | bfd_boolean narrow; |
7310 | ||
7311 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
7312 | narrow = (current_it_mask == 0); | |
7313 | else | |
7314 | narrow = (current_it_mask != 0); | |
7315 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) | |
7316 | narrow = FALSE; | |
7317 | if (inst.size_req == 4) | |
7318 | narrow = FALSE; | |
7319 | ||
7320 | if (!narrow) | |
c19d1205 ZW |
7321 | { |
7322 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7323 | inst.instruction |= inst.operands[0].reg << 8; | |
7324 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
7325 | } |
7326 | else | |
7327 | { | |
c19d1205 ZW |
7328 | inst.instruction = THUMB_OP16 (inst.instruction); |
7329 | inst.instruction |= inst.operands[0].reg; | |
7330 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
7331 | } |
7332 | } | |
7333 | else | |
7334 | { | |
c19d1205 ZW |
7335 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
7336 | BAD_HIREG); | |
7337 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
7338 | ||
7339 | inst.instruction = THUMB_OP16 (inst.instruction); | |
7340 | inst.instruction |= inst.operands[0].reg; | |
7341 | inst.instruction |= inst.operands[1].reg << 3; | |
7342 | } | |
7343 | } | |
7344 | ||
7345 | static void | |
7346 | do_t_pkhbt (void) | |
7347 | { | |
7348 | inst.instruction |= inst.operands[0].reg << 8; | |
7349 | inst.instruction |= inst.operands[1].reg << 16; | |
7350 | inst.instruction |= inst.operands[2].reg; | |
7351 | if (inst.operands[3].present) | |
7352 | { | |
7353 | unsigned int val = inst.reloc.exp.X_add_number; | |
7354 | constraint (inst.reloc.exp.X_op != O_constant, | |
7355 | _("expression too complex")); | |
7356 | inst.instruction |= (val & 0x1c) << 10; | |
7357 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 7358 | } |
c19d1205 | 7359 | } |
b05fe5cf | 7360 | |
c19d1205 ZW |
7361 | static void |
7362 | do_t_pkhtb (void) | |
7363 | { | |
7364 | if (!inst.operands[3].present) | |
7365 | inst.instruction &= ~0x00000020; | |
7366 | do_t_pkhbt (); | |
b05fe5cf ZW |
7367 | } |
7368 | ||
c19d1205 ZW |
7369 | static void |
7370 | do_t_pld (void) | |
7371 | { | |
7372 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
7373 | } | |
b05fe5cf | 7374 | |
c19d1205 ZW |
7375 | static void |
7376 | do_t_push_pop (void) | |
b99bd4ef | 7377 | { |
e9f89963 PB |
7378 | unsigned mask; |
7379 | ||
c19d1205 ZW |
7380 | constraint (inst.operands[0].writeback, |
7381 | _("push/pop do not support {reglist}^")); | |
7382 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
7383 | _("expression too complex")); | |
b99bd4ef | 7384 | |
e9f89963 PB |
7385 | mask = inst.operands[0].imm; |
7386 | if ((mask & ~0xff) == 0) | |
c19d1205 ZW |
7387 | inst.instruction = THUMB_OP16 (inst.instruction); |
7388 | else if ((inst.instruction == T_MNEM_push | |
e9f89963 | 7389 | && (mask & ~0xff) == 1 << REG_LR) |
c19d1205 | 7390 | || (inst.instruction == T_MNEM_pop |
e9f89963 | 7391 | && (mask & ~0xff) == 1 << REG_PC)) |
b99bd4ef | 7392 | { |
c19d1205 ZW |
7393 | inst.instruction = THUMB_OP16 (inst.instruction); |
7394 | inst.instruction |= THUMB_PP_PC_LR; | |
e9f89963 | 7395 | mask &= 0xff; |
c19d1205 ZW |
7396 | } |
7397 | else if (unified_syntax) | |
7398 | { | |
e9f89963 PB |
7399 | if (mask & (1 << 13)) |
7400 | inst.error = _("SP not allowed in register list"); | |
c19d1205 | 7401 | if (inst.instruction == T_MNEM_push) |
b99bd4ef | 7402 | { |
e9f89963 PB |
7403 | if (mask & (1 << 15)) |
7404 | inst.error = _("PC not allowed in register list"); | |
c19d1205 ZW |
7405 | } |
7406 | else | |
7407 | { | |
e9f89963 PB |
7408 | if (mask & (1 << 14) |
7409 | && mask & (1 << 15)) | |
7410 | inst.error = _("LR and PC should not both be in register list"); | |
c19d1205 | 7411 | } |
e9f89963 PB |
7412 | if ((mask & (mask - 1)) == 0) |
7413 | { | |
7414 | /* Single register push/pop implemented as str/ldr. */ | |
7415 | if (inst.instruction == T_MNEM_push) | |
7416 | inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */ | |
7417 | else | |
7418 | inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */ | |
7419 | mask = ffs(mask) - 1; | |
7420 | mask <<= 12; | |
7421 | } | |
7422 | else | |
7423 | inst.instruction = THUMB_OP32 (inst.instruction); | |
c19d1205 ZW |
7424 | } |
7425 | else | |
7426 | { | |
7427 | inst.error = _("invalid register list to push/pop instruction"); | |
7428 | return; | |
7429 | } | |
b99bd4ef | 7430 | |
e9f89963 | 7431 | inst.instruction |= mask; |
c19d1205 | 7432 | } |
b99bd4ef | 7433 | |
c19d1205 ZW |
7434 | static void |
7435 | do_t_rbit (void) | |
7436 | { | |
7437 | inst.instruction |= inst.operands[0].reg << 8; | |
7438 | inst.instruction |= inst.operands[1].reg << 16; | |
7439 | } | |
b99bd4ef | 7440 | |
c19d1205 ZW |
7441 | static void |
7442 | do_t_rev (void) | |
7443 | { | |
7444 | if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 | |
7445 | && inst.size_req != 4) | |
7446 | { | |
7447 | inst.instruction = THUMB_OP16 (inst.instruction); | |
7448 | inst.instruction |= inst.operands[0].reg; | |
7449 | inst.instruction |= inst.operands[1].reg << 3; | |
7450 | } | |
7451 | else if (unified_syntax) | |
7452 | { | |
7453 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7454 | inst.instruction |= inst.operands[0].reg << 8; | |
7455 | inst.instruction |= inst.operands[1].reg << 16; | |
7456 | inst.instruction |= inst.operands[1].reg; | |
7457 | } | |
7458 | else | |
7459 | inst.error = BAD_HIREG; | |
7460 | } | |
b99bd4ef | 7461 | |
c19d1205 ZW |
7462 | static void |
7463 | do_t_rsb (void) | |
7464 | { | |
7465 | int Rd, Rs; | |
b99bd4ef | 7466 | |
c19d1205 ZW |
7467 | Rd = inst.operands[0].reg; |
7468 | Rs = (inst.operands[1].present | |
7469 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
7470 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 7471 | |
c19d1205 ZW |
7472 | inst.instruction |= Rd << 8; |
7473 | inst.instruction |= Rs << 16; | |
7474 | if (!inst.operands[2].isreg) | |
7475 | { | |
7476 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
7477 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
7478 | } | |
7479 | else | |
7480 | encode_thumb32_shifted_operand (2); | |
7481 | } | |
b99bd4ef | 7482 | |
c19d1205 ZW |
7483 | static void |
7484 | do_t_setend (void) | |
7485 | { | |
7486 | if (inst.operands[0].imm) | |
7487 | inst.instruction |= 0x8; | |
7488 | } | |
b99bd4ef | 7489 | |
c19d1205 ZW |
7490 | static void |
7491 | do_t_shift (void) | |
7492 | { | |
7493 | if (!inst.operands[1].present) | |
7494 | inst.operands[1].reg = inst.operands[0].reg; | |
7495 | ||
7496 | if (unified_syntax) | |
7497 | { | |
3d388997 PB |
7498 | bfd_boolean narrow; |
7499 | int shift_kind; | |
7500 | ||
7501 | switch (inst.instruction) | |
7502 | { | |
7503 | case T_MNEM_asr: | |
7504 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
7505 | case T_MNEM_lsl: | |
7506 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
7507 | case T_MNEM_lsr: | |
7508 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
7509 | case T_MNEM_ror: | |
7510 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
7511 | default: abort (); | |
7512 | } | |
7513 | ||
7514 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
7515 | narrow = (current_it_mask == 0); | |
7516 | else | |
7517 | narrow = (current_it_mask != 0); | |
7518 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) | |
7519 | narrow = FALSE; | |
7520 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
7521 | narrow = FALSE; | |
7522 | if (inst.operands[2].isreg | |
7523 | && (inst.operands[1].reg != inst.operands[0].reg | |
7524 | || inst.operands[2].reg > 7)) | |
7525 | narrow = FALSE; | |
7526 | if (inst.size_req == 4) | |
7527 | narrow = FALSE; | |
7528 | ||
7529 | if (!narrow) | |
c19d1205 ZW |
7530 | { |
7531 | if (inst.operands[2].isreg) | |
b99bd4ef | 7532 | { |
c19d1205 ZW |
7533 | inst.instruction = THUMB_OP32 (inst.instruction); |
7534 | inst.instruction |= inst.operands[0].reg << 8; | |
7535 | inst.instruction |= inst.operands[1].reg << 16; | |
7536 | inst.instruction |= inst.operands[2].reg; | |
7537 | } | |
7538 | else | |
7539 | { | |
7540 | inst.operands[1].shifted = 1; | |
3d388997 | 7541 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
7542 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
7543 | ? T_MNEM_movs : T_MNEM_mov); | |
7544 | inst.instruction |= inst.operands[0].reg << 8; | |
7545 | encode_thumb32_shifted_operand (1); | |
7546 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
7547 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
7548 | } |
7549 | } | |
7550 | else | |
7551 | { | |
c19d1205 | 7552 | if (inst.operands[2].isreg) |
b99bd4ef | 7553 | { |
3d388997 | 7554 | switch (shift_kind) |
b99bd4ef | 7555 | { |
3d388997 PB |
7556 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
7557 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
7558 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
7559 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 7560 | default: abort (); |
b99bd4ef | 7561 | } |
c19d1205 ZW |
7562 | |
7563 | inst.instruction |= inst.operands[0].reg; | |
7564 | inst.instruction |= inst.operands[2].reg << 3; | |
b99bd4ef NC |
7565 | } |
7566 | else | |
7567 | { | |
3d388997 | 7568 | switch (shift_kind) |
b99bd4ef | 7569 | { |
3d388997 PB |
7570 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
7571 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
7572 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 7573 | default: abort (); |
b99bd4ef | 7574 | } |
c19d1205 ZW |
7575 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
7576 | inst.instruction |= inst.operands[0].reg; | |
7577 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
7578 | } |
7579 | } | |
c19d1205 ZW |
7580 | } |
7581 | else | |
7582 | { | |
7583 | constraint (inst.operands[0].reg > 7 | |
7584 | || inst.operands[1].reg > 7, BAD_HIREG); | |
7585 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 7586 | |
c19d1205 ZW |
7587 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
7588 | { | |
7589 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
7590 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
7591 | _("source1 and dest must be same register")); | |
b99bd4ef | 7592 | |
c19d1205 ZW |
7593 | switch (inst.instruction) |
7594 | { | |
7595 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
7596 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
7597 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
7598 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
7599 | default: abort (); | |
7600 | } | |
7601 | ||
7602 | inst.instruction |= inst.operands[0].reg; | |
7603 | inst.instruction |= inst.operands[2].reg << 3; | |
7604 | } | |
7605 | else | |
b99bd4ef | 7606 | { |
c19d1205 ZW |
7607 | switch (inst.instruction) |
7608 | { | |
7609 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
7610 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
7611 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
7612 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
7613 | default: abort (); | |
7614 | } | |
7615 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
7616 | inst.instruction |= inst.operands[0].reg; | |
7617 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
7618 | } |
7619 | } | |
b99bd4ef NC |
7620 | } |
7621 | ||
7622 | static void | |
c19d1205 | 7623 | do_t_simd (void) |
b99bd4ef | 7624 | { |
c19d1205 ZW |
7625 | inst.instruction |= inst.operands[0].reg << 8; |
7626 | inst.instruction |= inst.operands[1].reg << 16; | |
7627 | inst.instruction |= inst.operands[2].reg; | |
7628 | } | |
b99bd4ef | 7629 | |
c19d1205 | 7630 | static void |
3eb17e6b | 7631 | do_t_smc (void) |
c19d1205 ZW |
7632 | { |
7633 | unsigned int value = inst.reloc.exp.X_add_number; | |
7634 | constraint (inst.reloc.exp.X_op != O_constant, | |
7635 | _("expression too complex")); | |
7636 | inst.reloc.type = BFD_RELOC_UNUSED; | |
7637 | inst.instruction |= (value & 0xf000) >> 12; | |
7638 | inst.instruction |= (value & 0x0ff0); | |
7639 | inst.instruction |= (value & 0x000f) << 16; | |
7640 | } | |
b99bd4ef | 7641 | |
c19d1205 ZW |
7642 | static void |
7643 | do_t_ssat (void) | |
7644 | { | |
7645 | inst.instruction |= inst.operands[0].reg << 8; | |
7646 | inst.instruction |= inst.operands[1].imm - 1; | |
7647 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef | 7648 | |
c19d1205 | 7649 | if (inst.operands[3].present) |
b99bd4ef | 7650 | { |
c19d1205 ZW |
7651 | constraint (inst.reloc.exp.X_op != O_constant, |
7652 | _("expression too complex")); | |
b99bd4ef | 7653 | |
c19d1205 | 7654 | if (inst.reloc.exp.X_add_number != 0) |
6189168b | 7655 | { |
c19d1205 ZW |
7656 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
7657 | inst.instruction |= 0x00200000; /* sh bit */ | |
7658 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; | |
7659 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; | |
6189168b | 7660 | } |
c19d1205 | 7661 | inst.reloc.type = BFD_RELOC_UNUSED; |
6189168b | 7662 | } |
b99bd4ef NC |
7663 | } |
7664 | ||
0dd132b6 | 7665 | static void |
c19d1205 | 7666 | do_t_ssat16 (void) |
0dd132b6 | 7667 | { |
c19d1205 ZW |
7668 | inst.instruction |= inst.operands[0].reg << 8; |
7669 | inst.instruction |= inst.operands[1].imm - 1; | |
7670 | inst.instruction |= inst.operands[2].reg << 16; | |
7671 | } | |
0dd132b6 | 7672 | |
c19d1205 ZW |
7673 | static void |
7674 | do_t_strex (void) | |
7675 | { | |
7676 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
7677 | || inst.operands[2].postind || inst.operands[2].writeback | |
7678 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
7679 | || inst.operands[2].negative, | |
01cfc07f | 7680 | BAD_ADDR_MODE); |
0dd132b6 | 7681 | |
c19d1205 ZW |
7682 | inst.instruction |= inst.operands[0].reg << 8; |
7683 | inst.instruction |= inst.operands[1].reg << 12; | |
7684 | inst.instruction |= inst.operands[2].reg << 16; | |
7685 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
7686 | } |
7687 | ||
b99bd4ef | 7688 | static void |
c19d1205 | 7689 | do_t_strexd (void) |
b99bd4ef | 7690 | { |
c19d1205 ZW |
7691 | if (!inst.operands[2].present) |
7692 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 7693 | |
c19d1205 ZW |
7694 | constraint (inst.operands[0].reg == inst.operands[1].reg |
7695 | || inst.operands[0].reg == inst.operands[2].reg | |
7696 | || inst.operands[0].reg == inst.operands[3].reg | |
7697 | || inst.operands[1].reg == inst.operands[2].reg, | |
7698 | BAD_OVERLAP); | |
b99bd4ef | 7699 | |
c19d1205 ZW |
7700 | inst.instruction |= inst.operands[0].reg; |
7701 | inst.instruction |= inst.operands[1].reg << 12; | |
7702 | inst.instruction |= inst.operands[2].reg << 8; | |
7703 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
7704 | } |
7705 | ||
7706 | static void | |
c19d1205 | 7707 | do_t_sxtah (void) |
b99bd4ef | 7708 | { |
c19d1205 ZW |
7709 | inst.instruction |= inst.operands[0].reg << 8; |
7710 | inst.instruction |= inst.operands[1].reg << 16; | |
7711 | inst.instruction |= inst.operands[2].reg; | |
7712 | inst.instruction |= inst.operands[3].imm << 4; | |
7713 | } | |
b99bd4ef | 7714 | |
c19d1205 ZW |
7715 | static void |
7716 | do_t_sxth (void) | |
7717 | { | |
7718 | if (inst.instruction <= 0xffff && inst.size_req != 4 | |
7719 | && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 | |
7720 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) | |
b99bd4ef | 7721 | { |
c19d1205 ZW |
7722 | inst.instruction = THUMB_OP16 (inst.instruction); |
7723 | inst.instruction |= inst.operands[0].reg; | |
7724 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef | 7725 | } |
c19d1205 | 7726 | else if (unified_syntax) |
b99bd4ef | 7727 | { |
c19d1205 ZW |
7728 | if (inst.instruction <= 0xffff) |
7729 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7730 | inst.instruction |= inst.operands[0].reg << 8; | |
7731 | inst.instruction |= inst.operands[1].reg; | |
7732 | inst.instruction |= inst.operands[2].imm << 4; | |
b99bd4ef | 7733 | } |
c19d1205 | 7734 | else |
b99bd4ef | 7735 | { |
c19d1205 ZW |
7736 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
7737 | _("Thumb encoding does not support rotation")); | |
7738 | constraint (1, BAD_HIREG); | |
b99bd4ef | 7739 | } |
c19d1205 | 7740 | } |
b99bd4ef | 7741 | |
c19d1205 ZW |
7742 | static void |
7743 | do_t_swi (void) | |
7744 | { | |
7745 | inst.reloc.type = BFD_RELOC_ARM_SWI; | |
7746 | } | |
b99bd4ef | 7747 | |
92e90b6e PB |
7748 | static void |
7749 | do_t_tb (void) | |
7750 | { | |
7751 | int half; | |
7752 | ||
7753 | half = (inst.instruction & 0x10) != 0; | |
7754 | constraint (inst.operands[0].imm == 15, | |
7755 | _("PC is not a valid index register")); | |
7756 | constraint (!half && inst.operands[0].shifted, | |
7757 | _("instruction does not allow shifted index")); | |
7758 | constraint (half && !inst.operands[0].shifted, | |
7759 | _("instruction requires shifted index")); | |
7760 | inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm; | |
7761 | } | |
7762 | ||
c19d1205 ZW |
7763 | static void |
7764 | do_t_usat (void) | |
7765 | { | |
7766 | inst.instruction |= inst.operands[0].reg << 8; | |
7767 | inst.instruction |= inst.operands[1].imm; | |
7768 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef | 7769 | |
c19d1205 | 7770 | if (inst.operands[3].present) |
b99bd4ef | 7771 | { |
c19d1205 ZW |
7772 | constraint (inst.reloc.exp.X_op != O_constant, |
7773 | _("expression too complex")); | |
7774 | if (inst.reloc.exp.X_add_number != 0) | |
7775 | { | |
7776 | if (inst.operands[3].shift_kind == SHIFT_ASR) | |
7777 | inst.instruction |= 0x00200000; /* sh bit */ | |
b99bd4ef | 7778 | |
c19d1205 ZW |
7779 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; |
7780 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; | |
7781 | } | |
7782 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 7783 | } |
b99bd4ef NC |
7784 | } |
7785 | ||
7786 | static void | |
c19d1205 | 7787 | do_t_usat16 (void) |
b99bd4ef | 7788 | { |
c19d1205 ZW |
7789 | inst.instruction |= inst.operands[0].reg << 8; |
7790 | inst.instruction |= inst.operands[1].imm; | |
7791 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef | 7792 | } |
c19d1205 ZW |
7793 | \f |
7794 | /* Overall per-instruction processing. */ | |
7795 | ||
7796 | /* We need to be able to fix up arbitrary expressions in some statements. | |
7797 | This is so that we can handle symbols that are an arbitrary distance from | |
7798 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
7799 | which returns part of an address in a form which will be valid for | |
7800 | a data instruction. We do this by pushing the expression into a symbol | |
7801 | in the expr_section, and creating a fix for that. */ | |
b99bd4ef NC |
7802 | |
7803 | static void | |
c19d1205 ZW |
7804 | fix_new_arm (fragS * frag, |
7805 | int where, | |
7806 | short int size, | |
7807 | expressionS * exp, | |
7808 | int pc_rel, | |
7809 | int reloc) | |
b99bd4ef | 7810 | { |
c19d1205 | 7811 | fixS * new_fix; |
b99bd4ef | 7812 | |
c19d1205 | 7813 | switch (exp->X_op) |
b99bd4ef | 7814 | { |
c19d1205 ZW |
7815 | case O_constant: |
7816 | case O_symbol: | |
7817 | case O_add: | |
7818 | case O_subtract: | |
7819 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc); | |
7820 | break; | |
b99bd4ef | 7821 | |
c19d1205 ZW |
7822 | default: |
7823 | new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, | |
7824 | pc_rel, reloc); | |
7825 | break; | |
b99bd4ef NC |
7826 | } |
7827 | ||
c19d1205 ZW |
7828 | /* Mark whether the fix is to a THUMB instruction, or an ARM |
7829 | instruction. */ | |
adbaf948 | 7830 | new_fix->tc_fix_data = thumb_mode; |
b99bd4ef NC |
7831 | } |
7832 | ||
0110f2b8 PB |
7833 | /* Create a frg for an instruction requiring relaxation. */ |
7834 | static void | |
7835 | output_relax_insn (void) | |
7836 | { | |
7837 | char * to; | |
7838 | symbolS *sym; | |
7839 | int offset; | |
7840 | ||
7841 | switch (inst.reloc.exp.X_op) | |
7842 | { | |
7843 | case O_symbol: | |
7844 | sym = inst.reloc.exp.X_add_symbol; | |
7845 | offset = inst.reloc.exp.X_add_number; | |
7846 | break; | |
7847 | case O_constant: | |
7848 | sym = NULL; | |
7849 | offset = inst.reloc.exp.X_add_number; | |
7850 | break; | |
7851 | default: | |
7852 | sym = make_expr_symbol (&inst.reloc.exp); | |
7853 | offset = 0; | |
7854 | break; | |
7855 | } | |
7856 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
7857 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
7858 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
7859 | ||
7860 | #ifdef OBJ_ELF | |
7861 | dwarf2_emit_insn (INSN_SIZE); | |
7862 | #endif | |
7863 | } | |
7864 | ||
7865 | /* Write a 32-bit thumb instruction to buf. */ | |
7866 | static void | |
7867 | put_thumb32_insn (char * buf, unsigned long insn) | |
7868 | { | |
7869 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
7870 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
7871 | } | |
7872 | ||
b99bd4ef | 7873 | static void |
c19d1205 | 7874 | output_inst (const char * str) |
b99bd4ef | 7875 | { |
c19d1205 | 7876 | char * to = NULL; |
b99bd4ef | 7877 | |
c19d1205 | 7878 | if (inst.error) |
b99bd4ef | 7879 | { |
c19d1205 | 7880 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
7881 | return; |
7882 | } | |
0110f2b8 PB |
7883 | if (inst.relax) { |
7884 | output_relax_insn(); | |
7885 | return; | |
7886 | } | |
c19d1205 ZW |
7887 | if (inst.size == 0) |
7888 | return; | |
b99bd4ef | 7889 | |
c19d1205 ZW |
7890 | to = frag_more (inst.size); |
7891 | ||
7892 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 7893 | { |
c19d1205 | 7894 | assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 7895 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 7896 | } |
c19d1205 | 7897 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 7898 | { |
c19d1205 ZW |
7899 | assert (inst.size == (2 * INSN_SIZE)); |
7900 | md_number_to_chars (to, inst.instruction, INSN_SIZE); | |
7901 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 7902 | } |
c19d1205 ZW |
7903 | else |
7904 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 7905 | |
c19d1205 ZW |
7906 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
7907 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
7908 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
7909 | inst.reloc.type); | |
b99bd4ef | 7910 | |
c19d1205 ZW |
7911 | #ifdef OBJ_ELF |
7912 | dwarf2_emit_insn (inst.size); | |
7913 | #endif | |
7914 | } | |
b99bd4ef | 7915 | |
c19d1205 ZW |
7916 | /* Tag values used in struct asm_opcode's tag field. */ |
7917 | enum opcode_tag | |
7918 | { | |
7919 | OT_unconditional, /* Instruction cannot be conditionalized. | |
7920 | The ARM condition field is still 0xE. */ | |
7921 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
7922 | and carries 0xF in its ARM condition field. */ | |
7923 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
7924 | OT_cinfix3, /* Instruction takes a conditional infix, | |
7925 | beginning at character index 3. (In | |
7926 | unified mode, it becomes a suffix.) */ | |
e3cb604e PB |
7927 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
7928 | character index 3, even in unified mode. Used for | |
7929 | legacy instructions where suffix and infix forms | |
7930 | may be ambiguous. */ | |
c19d1205 | 7931 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 7932 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
7933 | OT_odd_infix_unc, /* This is the unconditional variant of an |
7934 | instruction that takes a conditional infix | |
7935 | at an unusual position. In unified mode, | |
7936 | this variant will accept a suffix. */ | |
7937 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
7938 | are the conditional variants of instructions that | |
7939 | take conditional infixes in unusual positions. | |
7940 | The infix appears at character index | |
7941 | (tag - OT_odd_infix_0). These are not accepted | |
7942 | in unified mode. */ | |
7943 | }; | |
b99bd4ef | 7944 | |
c19d1205 ZW |
7945 | /* Subroutine of md_assemble, responsible for looking up the primary |
7946 | opcode from the mnemonic the user wrote. STR points to the | |
7947 | beginning of the mnemonic. | |
7948 | ||
7949 | This is not simply a hash table lookup, because of conditional | |
7950 | variants. Most instructions have conditional variants, which are | |
7951 | expressed with a _conditional affix_ to the mnemonic. If we were | |
7952 | to encode each conditional variant as a literal string in the opcode | |
7953 | table, it would have approximately 20,000 entries. | |
7954 | ||
7955 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
7956 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
7957 | instructions take the affix as an infix, notably the s-variants of | |
7958 | the arithmetic instructions. Of those instructions, all but six | |
7959 | have the infix appear after the third character of the mnemonic. | |
7960 | ||
7961 | Accordingly, the algorithm for looking up primary opcodes given | |
7962 | an identifier is: | |
7963 | ||
7964 | 1. Look up the identifier in the opcode table. | |
7965 | If we find a match, go to step U. | |
7966 | ||
7967 | 2. Look up the last two characters of the identifier in the | |
7968 | conditions table. If we find a match, look up the first N-2 | |
7969 | characters of the identifier in the opcode table. If we | |
7970 | find a match, go to step CE. | |
7971 | ||
7972 | 3. Look up the fourth and fifth characters of the identifier in | |
7973 | the conditions table. If we find a match, extract those | |
7974 | characters from the identifier, and look up the remaining | |
7975 | characters in the opcode table. If we find a match, go | |
7976 | to step CM. | |
7977 | ||
7978 | 4. Fail. | |
7979 | ||
7980 | U. Examine the tag field of the opcode structure, in case this is | |
7981 | one of the six instructions with its conditional infix in an | |
7982 | unusual place. If it is, the tag tells us where to find the | |
7983 | infix; look it up in the conditions table and set inst.cond | |
7984 | accordingly. Otherwise, this is an unconditional instruction. | |
7985 | Again set inst.cond accordingly. Return the opcode structure. | |
7986 | ||
7987 | CE. Examine the tag field to make sure this is an instruction that | |
7988 | should receive a conditional suffix. If it is not, fail. | |
7989 | Otherwise, set inst.cond from the suffix we already looked up, | |
7990 | and return the opcode structure. | |
7991 | ||
7992 | CM. Examine the tag field to make sure this is an instruction that | |
7993 | should receive a conditional infix after the third character. | |
7994 | If it is not, fail. Otherwise, undo the edits to the current | |
7995 | line of input and proceed as for case CE. */ | |
7996 | ||
7997 | static const struct asm_opcode * | |
7998 | opcode_lookup (char **str) | |
7999 | { | |
8000 | char *end, *base; | |
8001 | char *affix; | |
8002 | const struct asm_opcode *opcode; | |
8003 | const struct asm_cond *cond; | |
e3cb604e | 8004 | char save[2]; |
c19d1205 ZW |
8005 | |
8006 | /* Scan up to the end of the mnemonic, which must end in white space, | |
8007 | '.' (in unified mode only), or end of string. */ | |
8008 | for (base = end = *str; *end != '\0'; end++) | |
8009 | if (*end == ' ' || (unified_syntax && *end == '.')) | |
8010 | break; | |
b99bd4ef | 8011 | |
c19d1205 ZW |
8012 | if (end == base) |
8013 | return 0; | |
b99bd4ef | 8014 | |
c19d1205 ZW |
8015 | /* Handle a possible width suffix. */ |
8016 | if (end[0] == '.') | |
b99bd4ef | 8017 | { |
c19d1205 ZW |
8018 | if (end[1] == 'w' && (end[2] == ' ' || end[2] == '\0')) |
8019 | inst.size_req = 4; | |
8020 | else if (end[1] == 'n' && (end[2] == ' ' || end[2] == '\0')) | |
8021 | inst.size_req = 2; | |
8022 | else | |
8023 | return 0; | |
b99bd4ef | 8024 | |
c19d1205 | 8025 | *str = end + 2; |
b99bd4ef | 8026 | } |
c19d1205 ZW |
8027 | else |
8028 | *str = end; | |
b99bd4ef | 8029 | |
c19d1205 ZW |
8030 | /* Look for unaffixed or special-case affixed mnemonic. */ |
8031 | opcode = hash_find_n (arm_ops_hsh, base, end - base); | |
8032 | if (opcode) | |
b99bd4ef | 8033 | { |
c19d1205 ZW |
8034 | /* step U */ |
8035 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 8036 | { |
c19d1205 ZW |
8037 | inst.cond = COND_ALWAYS; |
8038 | return opcode; | |
b99bd4ef | 8039 | } |
b99bd4ef | 8040 | |
c19d1205 ZW |
8041 | if (unified_syntax) |
8042 | as_warn (_("conditional infixes are deprecated in unified syntax")); | |
8043 | affix = base + (opcode->tag - OT_odd_infix_0); | |
8044 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
8045 | assert (cond); | |
b99bd4ef | 8046 | |
c19d1205 ZW |
8047 | inst.cond = cond->value; |
8048 | return opcode; | |
8049 | } | |
b99bd4ef | 8050 | |
c19d1205 ZW |
8051 | /* Cannot have a conditional suffix on a mnemonic of less than two |
8052 | characters. */ | |
8053 | if (end - base < 3) | |
8054 | return 0; | |
b99bd4ef | 8055 | |
c19d1205 ZW |
8056 | /* Look for suffixed mnemonic. */ |
8057 | affix = end - 2; | |
8058 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
8059 | opcode = hash_find_n (arm_ops_hsh, base, affix - base); | |
8060 | if (opcode && cond) | |
8061 | { | |
8062 | /* step CE */ | |
8063 | switch (opcode->tag) | |
8064 | { | |
e3cb604e PB |
8065 | case OT_cinfix3_legacy: |
8066 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
8067 | break; | |
8068 | ||
c19d1205 ZW |
8069 | case OT_cinfix3: |
8070 | case OT_odd_infix_unc: | |
8071 | if (!unified_syntax) | |
e3cb604e | 8072 | return 0; |
c19d1205 ZW |
8073 | /* else fall through */ |
8074 | ||
8075 | case OT_csuffix: | |
8076 | case OT_csuf_or_in3: | |
8077 | inst.cond = cond->value; | |
8078 | return opcode; | |
8079 | ||
8080 | case OT_unconditional: | |
8081 | case OT_unconditionalF: | |
8082 | /* delayed diagnostic */ | |
8083 | inst.error = BAD_COND; | |
8084 | inst.cond = COND_ALWAYS; | |
8085 | return opcode; | |
b99bd4ef | 8086 | |
c19d1205 ZW |
8087 | default: |
8088 | return 0; | |
8089 | } | |
8090 | } | |
b99bd4ef | 8091 | |
c19d1205 ZW |
8092 | /* Cannot have a usual-position infix on a mnemonic of less than |
8093 | six characters (five would be a suffix). */ | |
8094 | if (end - base < 6) | |
8095 | return 0; | |
b99bd4ef | 8096 | |
c19d1205 ZW |
8097 | /* Look for infixed mnemonic in the usual position. */ |
8098 | affix = base + 3; | |
8099 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
e3cb604e PB |
8100 | if (!cond) |
8101 | return 0; | |
8102 | ||
8103 | memcpy (save, affix, 2); | |
8104 | memmove (affix, affix + 2, (end - affix) - 2); | |
8105 | opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2); | |
8106 | memmove (affix + 2, affix, (end - affix) - 2); | |
8107 | memcpy (affix, save, 2); | |
8108 | ||
8109 | if (opcode && (opcode->tag == OT_cinfix3 || opcode->tag == OT_csuf_or_in3 | |
8110 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 8111 | { |
c19d1205 | 8112 | /* step CM */ |
e3cb604e | 8113 | if (unified_syntax && opcode->tag == OT_cinfix3) |
c19d1205 ZW |
8114 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
8115 | ||
8116 | inst.cond = cond->value; | |
8117 | return opcode; | |
b99bd4ef NC |
8118 | } |
8119 | ||
c19d1205 | 8120 | return 0; |
b99bd4ef NC |
8121 | } |
8122 | ||
c19d1205 ZW |
8123 | void |
8124 | md_assemble (char *str) | |
b99bd4ef | 8125 | { |
c19d1205 ZW |
8126 | char *p = str; |
8127 | const struct asm_opcode * opcode; | |
b99bd4ef | 8128 | |
c19d1205 ZW |
8129 | /* Align the previous label if needed. */ |
8130 | if (last_label_seen != NULL) | |
b99bd4ef | 8131 | { |
c19d1205 ZW |
8132 | symbol_set_frag (last_label_seen, frag_now); |
8133 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
8134 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
8135 | } |
8136 | ||
c19d1205 ZW |
8137 | memset (&inst, '\0', sizeof (inst)); |
8138 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 8139 | |
c19d1205 ZW |
8140 | opcode = opcode_lookup (&p); |
8141 | if (!opcode) | |
b99bd4ef | 8142 | { |
c19d1205 ZW |
8143 | /* It wasn't an instruction, but it might be a register alias of |
8144 | the form alias .req reg. */ | |
8145 | if (!create_register_alias (str, p)) | |
8146 | as_bad (_("bad instruction `%s'"), str); | |
b99bd4ef | 8147 | |
b99bd4ef NC |
8148 | return; |
8149 | } | |
8150 | ||
c19d1205 | 8151 | if (thumb_mode) |
b99bd4ef | 8152 | { |
e74cfd16 | 8153 | arm_feature_set variant; |
8f06b2d8 PB |
8154 | |
8155 | variant = cpu_variant; | |
8156 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
8157 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
8158 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 8159 | /* Check that this instruction is supported for this CPU. */ |
e74cfd16 PB |
8160 | if (thumb_mode == 1 |
8161 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)) | |
b99bd4ef | 8162 | { |
c19d1205 | 8163 | as_bad (_("selected processor does not support `%s'"), str); |
b99bd4ef NC |
8164 | return; |
8165 | } | |
c19d1205 ZW |
8166 | if (inst.cond != COND_ALWAYS && !unified_syntax |
8167 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 8168 | { |
c19d1205 | 8169 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
8170 | return; |
8171 | } | |
8172 | ||
e27ec89e PB |
8173 | /* Check conditional suffixes. */ |
8174 | if (current_it_mask) | |
8175 | { | |
8176 | int cond; | |
8177 | cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1; | |
8178 | if (cond != inst.cond) | |
8179 | { | |
8180 | as_bad (_("incorrect condition in IT block")); | |
8181 | return; | |
8182 | } | |
8183 | current_it_mask <<= 1; | |
8184 | current_it_mask &= 0x1f; | |
8185 | } | |
8186 | else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch) | |
8187 | { | |
8188 | as_bad (_("thumb conditional instrunction not in IT block")); | |
8189 | return; | |
8190 | } | |
8191 | ||
c19d1205 ZW |
8192 | mapping_state (MAP_THUMB); |
8193 | inst.instruction = opcode->tvalue; | |
8194 | ||
8195 | if (!parse_operands (p, opcode->operands)) | |
8196 | opcode->tencode (); | |
8197 | ||
e27ec89e PB |
8198 | /* Clear current_it_mask at the end of an IT block. */ |
8199 | if (current_it_mask == 0x10) | |
8200 | current_it_mask = 0; | |
8201 | ||
0110f2b8 | 8202 | if (!(inst.error || inst.relax)) |
b99bd4ef | 8203 | { |
c19d1205 ZW |
8204 | assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
8205 | inst.size = (inst.instruction > 0xffff ? 4 : 2); | |
8206 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 8207 | { |
c19d1205 | 8208 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
8209 | return; |
8210 | } | |
8211 | } | |
e74cfd16 PB |
8212 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
8213 | *opcode->tvariant); | |
ee065d83 | 8214 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
e74cfd16 | 8215 | set those bits when Thumb-2 32-bit instuctions are seen. ie. |
ee065d83 PB |
8216 | anything other than bl/blx. |
8217 | This is overly pessimistic for relaxable instructions. */ | |
8218 | if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) | |
8219 | || inst.relax) | |
e74cfd16 PB |
8220 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
8221 | arm_ext_v6t2); | |
c19d1205 ZW |
8222 | } |
8223 | else | |
8224 | { | |
8225 | /* Check that this instruction is supported for this CPU. */ | |
e74cfd16 | 8226 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)) |
b99bd4ef | 8227 | { |
c19d1205 ZW |
8228 | as_bad (_("selected processor does not support `%s'"), str); |
8229 | return; | |
b99bd4ef | 8230 | } |
c19d1205 | 8231 | if (inst.size_req) |
b99bd4ef | 8232 | { |
c19d1205 ZW |
8233 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
8234 | return; | |
b99bd4ef NC |
8235 | } |
8236 | ||
c19d1205 ZW |
8237 | mapping_state (MAP_ARM); |
8238 | inst.instruction = opcode->avalue; | |
8239 | if (opcode->tag == OT_unconditionalF) | |
8240 | inst.instruction |= 0xF << 28; | |
8241 | else | |
8242 | inst.instruction |= inst.cond << 28; | |
8243 | inst.size = INSN_SIZE; | |
8244 | if (!parse_operands (p, opcode->operands)) | |
8245 | opcode->aencode (); | |
ee065d83 PB |
8246 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
8247 | on a hypothetical non-thumb v5 core. */ | |
e74cfd16 PB |
8248 | if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t) |
8249 | || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5)) | |
8250 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); | |
ee065d83 | 8251 | else |
e74cfd16 PB |
8252 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
8253 | *opcode->avariant); | |
b99bd4ef | 8254 | } |
c19d1205 ZW |
8255 | output_inst (str); |
8256 | } | |
b99bd4ef | 8257 | |
c19d1205 ZW |
8258 | /* Various frobbings of labels and their addresses. */ |
8259 | ||
8260 | void | |
8261 | arm_start_line_hook (void) | |
8262 | { | |
8263 | last_label_seen = NULL; | |
b99bd4ef NC |
8264 | } |
8265 | ||
c19d1205 ZW |
8266 | void |
8267 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 8268 | { |
c19d1205 | 8269 | last_label_seen = sym; |
b99bd4ef | 8270 | |
c19d1205 | 8271 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 8272 | |
c19d1205 ZW |
8273 | #if defined OBJ_COFF || defined OBJ_ELF |
8274 | ARM_SET_INTERWORK (sym, support_interwork); | |
8275 | #endif | |
b99bd4ef | 8276 | |
c19d1205 ZW |
8277 | /* Note - do not allow local symbols (.Lxxx) to be labeled |
8278 | as Thumb functions. This is because these labels, whilst | |
8279 | they exist inside Thumb code, are not the entry points for | |
8280 | possible ARM->Thumb calls. Also, these labels can be used | |
8281 | as part of a computed goto or switch statement. eg gcc | |
8282 | can generate code that looks like this: | |
b99bd4ef | 8283 | |
c19d1205 ZW |
8284 | ldr r2, [pc, .Laaa] |
8285 | lsl r3, r3, #2 | |
8286 | ldr r2, [r3, r2] | |
8287 | mov pc, r2 | |
b99bd4ef | 8288 | |
c19d1205 ZW |
8289 | .Lbbb: .word .Lxxx |
8290 | .Lccc: .word .Lyyy | |
8291 | ..etc... | |
8292 | .Laaa: .word Lbbb | |
b99bd4ef | 8293 | |
c19d1205 ZW |
8294 | The first instruction loads the address of the jump table. |
8295 | The second instruction converts a table index into a byte offset. | |
8296 | The third instruction gets the jump address out of the table. | |
8297 | The fourth instruction performs the jump. | |
b99bd4ef | 8298 | |
c19d1205 ZW |
8299 | If the address stored at .Laaa is that of a symbol which has the |
8300 | Thumb_Func bit set, then the linker will arrange for this address | |
8301 | to have the bottom bit set, which in turn would mean that the | |
8302 | address computation performed by the third instruction would end | |
8303 | up with the bottom bit set. Since the ARM is capable of unaligned | |
8304 | word loads, the instruction would then load the incorrect address | |
8305 | out of the jump table, and chaos would ensue. */ | |
8306 | if (label_is_thumb_function_name | |
8307 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
8308 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 8309 | { |
c19d1205 ZW |
8310 | /* When the address of a Thumb function is taken the bottom |
8311 | bit of that address should be set. This will allow | |
8312 | interworking between Arm and Thumb functions to work | |
8313 | correctly. */ | |
b99bd4ef | 8314 | |
c19d1205 | 8315 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 8316 | |
c19d1205 | 8317 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 8318 | } |
07a53e5c RH |
8319 | |
8320 | #ifdef OBJ_ELF | |
8321 | dwarf2_emit_label (sym); | |
8322 | #endif | |
b99bd4ef NC |
8323 | } |
8324 | ||
c19d1205 ZW |
8325 | int |
8326 | arm_data_in_code (void) | |
b99bd4ef | 8327 | { |
c19d1205 | 8328 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 8329 | { |
c19d1205 ZW |
8330 | *input_line_pointer = '/'; |
8331 | input_line_pointer += 5; | |
8332 | *input_line_pointer = 0; | |
8333 | return 1; | |
b99bd4ef NC |
8334 | } |
8335 | ||
c19d1205 | 8336 | return 0; |
b99bd4ef NC |
8337 | } |
8338 | ||
c19d1205 ZW |
8339 | char * |
8340 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 8341 | { |
c19d1205 | 8342 | int len; |
b99bd4ef | 8343 | |
c19d1205 ZW |
8344 | if (thumb_mode && (len = strlen (name)) > 5 |
8345 | && streq (name + len - 5, "/data")) | |
8346 | *(name + len - 5) = 0; | |
b99bd4ef | 8347 | |
c19d1205 | 8348 | return name; |
b99bd4ef | 8349 | } |
c19d1205 ZW |
8350 | \f |
8351 | /* Table of all register names defined by default. The user can | |
8352 | define additional names with .req. Note that all register names | |
8353 | should appear in both upper and lowercase variants. Some registers | |
8354 | also have mixed-case names. */ | |
b99bd4ef | 8355 | |
c19d1205 ZW |
8356 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE } |
8357 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) | |
8358 | #define REGSET(p,t) \ | |
8359 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
8360 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
8361 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
8362 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
7ed4c4c5 | 8363 | |
c19d1205 | 8364 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 8365 | { |
c19d1205 ZW |
8366 | /* ARM integer registers. */ |
8367 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 8368 | |
c19d1205 ZW |
8369 | /* ATPCS synonyms. */ |
8370 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
8371 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
8372 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 8373 | |
c19d1205 ZW |
8374 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
8375 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
8376 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 8377 | |
c19d1205 ZW |
8378 | /* Well-known aliases. */ |
8379 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
8380 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
8381 | ||
8382 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
8383 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
8384 | ||
8385 | /* Coprocessor numbers. */ | |
8386 | REGSET(p, CP), REGSET(P, CP), | |
8387 | ||
8388 | /* Coprocessor register numbers. The "cr" variants are for backward | |
8389 | compatibility. */ | |
8390 | REGSET(c, CN), REGSET(C, CN), | |
8391 | REGSET(cr, CN), REGSET(CR, CN), | |
8392 | ||
8393 | /* FPA registers. */ | |
8394 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
8395 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
8396 | ||
8397 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
8398 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
8399 | ||
8400 | /* VFP SP registers. */ | |
8401 | REGSET(s,VFS), | |
8402 | REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS), | |
8403 | REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS), | |
8404 | REGNUM(s,24,VFS), REGNUM(s,25,VFS), REGNUM(s,26,VFS), REGNUM(s,27,VFS), | |
8405 | REGNUM(s,28,VFS), REGNUM(s,29,VFS), REGNUM(s,30,VFS), REGNUM(s,31,VFS), | |
8406 | ||
8407 | REGSET(S,VFS), | |
8408 | REGNUM(S,16,VFS), REGNUM(S,17,VFS), REGNUM(S,18,VFS), REGNUM(S,19,VFS), | |
8409 | REGNUM(S,20,VFS), REGNUM(S,21,VFS), REGNUM(S,22,VFS), REGNUM(S,23,VFS), | |
8410 | REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS), | |
8411 | REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS), | |
8412 | ||
8413 | /* VFP DP Registers. */ | |
8414 | REGSET(d,VFD), REGSET(D,VFS), | |
8415 | ||
8416 | /* VFP control registers. */ | |
8417 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
8418 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
8419 | ||
8420 | /* Maverick DSP coprocessor registers. */ | |
8421 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
8422 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
8423 | ||
8424 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
8425 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
8426 | REGDEF(dspsc,0,DSPSC), | |
8427 | ||
8428 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
8429 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
8430 | REGDEF(DSPSC,0,DSPSC), | |
8431 | ||
8432 | /* iWMMXt data registers - p0, c0-15. */ | |
8433 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
8434 | ||
8435 | /* iWMMXt control registers - p1, c0-3. */ | |
8436 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
8437 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
8438 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
8439 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
8440 | ||
8441 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
8442 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
8443 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
8444 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
8445 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
8446 | ||
8447 | /* XScale accumulator registers. */ | |
8448 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
8449 | }; | |
8450 | #undef REGDEF | |
8451 | #undef REGNUM | |
8452 | #undef REGSET | |
7ed4c4c5 | 8453 | |
c19d1205 ZW |
8454 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
8455 | within psr_required_here. */ | |
8456 | static const struct asm_psr psrs[] = | |
8457 | { | |
8458 | /* Backward compatibility notation. Note that "all" is no longer | |
8459 | truly all possible PSR bits. */ | |
8460 | {"all", PSR_c | PSR_f}, | |
8461 | {"flg", PSR_f}, | |
8462 | {"ctl", PSR_c}, | |
8463 | ||
8464 | /* Individual flags. */ | |
8465 | {"f", PSR_f}, | |
8466 | {"c", PSR_c}, | |
8467 | {"x", PSR_x}, | |
8468 | {"s", PSR_s}, | |
8469 | /* Combinations of flags. */ | |
8470 | {"fs", PSR_f | PSR_s}, | |
8471 | {"fx", PSR_f | PSR_x}, | |
8472 | {"fc", PSR_f | PSR_c}, | |
8473 | {"sf", PSR_s | PSR_f}, | |
8474 | {"sx", PSR_s | PSR_x}, | |
8475 | {"sc", PSR_s | PSR_c}, | |
8476 | {"xf", PSR_x | PSR_f}, | |
8477 | {"xs", PSR_x | PSR_s}, | |
8478 | {"xc", PSR_x | PSR_c}, | |
8479 | {"cf", PSR_c | PSR_f}, | |
8480 | {"cs", PSR_c | PSR_s}, | |
8481 | {"cx", PSR_c | PSR_x}, | |
8482 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
8483 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
8484 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
8485 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
8486 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
8487 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
8488 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
8489 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
8490 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
8491 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
8492 | {"scf", PSR_s | PSR_c | PSR_f}, | |
8493 | {"scx", PSR_s | PSR_c | PSR_x}, | |
8494 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
8495 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
8496 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
8497 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
8498 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
8499 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
8500 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
8501 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
8502 | {"csf", PSR_c | PSR_s | PSR_f}, | |
8503 | {"csx", PSR_c | PSR_s | PSR_x}, | |
8504 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
8505 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
8506 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
8507 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
8508 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
8509 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
8510 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
8511 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
8512 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
8513 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
8514 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
8515 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
8516 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
8517 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
8518 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
8519 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
8520 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
8521 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
8522 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
8523 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
8524 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
8525 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
8526 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
8527 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
8528 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
8529 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
8530 | }; | |
8531 | ||
8532 | /* Table of all shift-in-operand names. */ | |
8533 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 8534 | { |
c19d1205 ZW |
8535 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
8536 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
8537 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
8538 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
8539 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
8540 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
8541 | }; | |
b99bd4ef | 8542 | |
c19d1205 ZW |
8543 | /* Table of all explicit relocation names. */ |
8544 | #ifdef OBJ_ELF | |
8545 | static struct reloc_entry reloc_names[] = | |
8546 | { | |
8547 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
8548 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
8549 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
8550 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
8551 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
8552 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
8553 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
8554 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
8555 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
8556 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
8557 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32} | |
8558 | }; | |
8559 | #endif | |
b99bd4ef | 8560 | |
c19d1205 ZW |
8561 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
8562 | static const struct asm_cond conds[] = | |
8563 | { | |
8564 | {"eq", 0x0}, | |
8565 | {"ne", 0x1}, | |
8566 | {"cs", 0x2}, {"hs", 0x2}, | |
8567 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
8568 | {"mi", 0x4}, | |
8569 | {"pl", 0x5}, | |
8570 | {"vs", 0x6}, | |
8571 | {"vc", 0x7}, | |
8572 | {"hi", 0x8}, | |
8573 | {"ls", 0x9}, | |
8574 | {"ge", 0xa}, | |
8575 | {"lt", 0xb}, | |
8576 | {"gt", 0xc}, | |
8577 | {"le", 0xd}, | |
8578 | {"al", 0xe} | |
8579 | }; | |
bfae80f2 | 8580 | |
c19d1205 ZW |
8581 | /* Table of ARM-format instructions. */ |
8582 | ||
8583 | /* Macros for gluing together operand strings. N.B. In all cases | |
8584 | other than OPS0, the trailing OP_stop comes from default | |
8585 | zero-initialization of the unspecified elements of the array. */ | |
8586 | #define OPS0() { OP_stop, } | |
8587 | #define OPS1(a) { OP_##a, } | |
8588 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
8589 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
8590 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
8591 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
8592 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
8593 | ||
8594 | /* These macros abstract out the exact format of the mnemonic table and | |
8595 | save some repeated characters. */ | |
8596 | ||
8597 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
8598 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
8599 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ | |
1887dd22 | 8600 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8601 | |
8602 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
8603 | a T_MNEM_xyz enumerator. */ | |
8604 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
8605 | TxCE(mnem, aop, 0x##top, nops, ops, ae, te) | |
8606 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ | |
8607 | TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te) | |
8608 | ||
8609 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
8610 | infix after the third character. */ | |
8611 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
8612 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ | |
1887dd22 | 8613 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8614 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
8615 | TxC3(mnem, aop, 0x##top, nops, ops, ae, te) | |
8616 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ | |
8617 | TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te) | |
8618 | ||
8619 | /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to | |
8620 | appear in the condition table. */ | |
8621 | #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ | |
8622 | { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ | |
1887dd22 | 8623 | 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8624 | |
8625 | #define TxCM(m1, m2, op, top, nops, ops, ae, te) \ | |
8626 | TxCM_(m1, , m2, op, top, nops, ops, ae, te), \ | |
8627 | TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \ | |
8628 | TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \ | |
8629 | TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \ | |
8630 | TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \ | |
8631 | TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \ | |
8632 | TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \ | |
8633 | TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \ | |
8634 | TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \ | |
8635 | TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \ | |
8636 | TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \ | |
8637 | TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \ | |
8638 | TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \ | |
8639 | TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \ | |
8640 | TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \ | |
8641 | TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \ | |
8642 | TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \ | |
8643 | TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \ | |
8644 | TxCM_(m1, al, m2, op, top, nops, ops, ae, te) | |
8645 | ||
8646 | #define TCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
8647 | TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te) | |
8648 | #define tCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
8649 | TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te) | |
8650 | ||
8651 | /* Mnemonic that cannot be conditionalized. The ARM condition-code | |
8652 | field is still 0xE. */ | |
8653 | #define TUE(mnem, op, top, nops, ops, ae, te) \ | |
8654 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ | |
1887dd22 | 8655 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8656 | |
8657 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM | |
8658 | condition code field. */ | |
8659 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
8660 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ | |
1887dd22 | 8661 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8662 | |
8663 | /* ARM-only variants of all the above. */ | |
6a86118a NC |
8664 | #define CE(mnem, op, nops, ops, ae) \ |
8665 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
8666 | ||
8667 | #define C3(mnem, op, nops, ops, ae) \ | |
8668 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
8669 | ||
e3cb604e PB |
8670 | /* Legacy mnemonics that always have conditional infix after the third |
8671 | character. */ | |
8672 | #define CL(mnem, op, nops, ops, ae) \ | |
8673 | { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ | |
8674 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
8675 | ||
8f06b2d8 PB |
8676 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
8677 | #define cCE(mnem, op, nops, ops, ae) \ | |
8678 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } | |
8679 | ||
e3cb604e PB |
8680 | /* Legacy coprocessor instructions where conditional infix and conditional |
8681 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
8682 | not just the potentially ambiguous ones. */ | |
8683 | #define cCL(mnem, op, nops, ops, ae) \ | |
8684 | { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ | |
8685 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } | |
8686 | ||
8687 | /* Coprocessor, takes either a suffix or a position-3 infix | |
8688 | (for an FPA corner case). */ | |
8689 | #define C3E(mnem, op, nops, ops, ae) \ | |
8690 | { #mnem, OPS##nops ops, OT_csuf_or_in3, \ | |
8691 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } | |
8f06b2d8 | 8692 | |
6a86118a NC |
8693 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
8694 | { #m1 #m2 #m3, OPS##nops ops, \ | |
8695 | sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ | |
8696 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
8697 | ||
8698 | #define CM(m1, m2, op, nops, ops, ae) \ | |
8699 | xCM_(m1, , m2, op, nops, ops, ae), \ | |
8700 | xCM_(m1, eq, m2, op, nops, ops, ae), \ | |
8701 | xCM_(m1, ne, m2, op, nops, ops, ae), \ | |
8702 | xCM_(m1, cs, m2, op, nops, ops, ae), \ | |
8703 | xCM_(m1, hs, m2, op, nops, ops, ae), \ | |
8704 | xCM_(m1, cc, m2, op, nops, ops, ae), \ | |
8705 | xCM_(m1, ul, m2, op, nops, ops, ae), \ | |
8706 | xCM_(m1, lo, m2, op, nops, ops, ae), \ | |
8707 | xCM_(m1, mi, m2, op, nops, ops, ae), \ | |
8708 | xCM_(m1, pl, m2, op, nops, ops, ae), \ | |
8709 | xCM_(m1, vs, m2, op, nops, ops, ae), \ | |
8710 | xCM_(m1, vc, m2, op, nops, ops, ae), \ | |
8711 | xCM_(m1, hi, m2, op, nops, ops, ae), \ | |
8712 | xCM_(m1, ls, m2, op, nops, ops, ae), \ | |
8713 | xCM_(m1, ge, m2, op, nops, ops, ae), \ | |
8714 | xCM_(m1, lt, m2, op, nops, ops, ae), \ | |
8715 | xCM_(m1, gt, m2, op, nops, ops, ae), \ | |
8716 | xCM_(m1, le, m2, op, nops, ops, ae), \ | |
8717 | xCM_(m1, al, m2, op, nops, ops, ae) | |
8718 | ||
8719 | #define UE(mnem, op, nops, ops, ae) \ | |
8720 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
8721 | ||
8722 | #define UF(mnem, op, nops, ops, ae) \ | |
8723 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
8724 | ||
c19d1205 ZW |
8725 | #define do_0 0 |
8726 | ||
8727 | /* Thumb-only, unconditional. */ | |
8728 | #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te) | |
8729 | ||
c19d1205 | 8730 | static const struct asm_opcode insns[] = |
bfae80f2 | 8731 | { |
e74cfd16 PB |
8732 | #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ |
8733 | #define THUMB_VARIANT &arm_ext_v4t | |
c19d1205 ZW |
8734 | tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c), |
8735 | tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
8736 | tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
8737 | tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
8738 | tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
8739 | tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
8740 | tCE(add, 0800000, add, 3, (RR, oRR, SH), arit, t_add_sub), | |
8741 | tC3(adds, 0900000, adds, 3, (RR, oRR, SH), arit, t_add_sub), | |
8742 | tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
8743 | tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
8744 | tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
8745 | tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
8746 | tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
8747 | tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
8748 | tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3), | |
8749 | tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3), | |
8750 | ||
8751 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
8752 | for setting PSR flag bits. They are obsolete in V6 and do not | |
8753 | have Thumb equivalents. */ | |
8754 | tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), | |
8755 | tC3(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), | |
e3cb604e | 8756 | CL(tstp, 110f000, 2, (RR, SH), cmp), |
c19d1205 ZW |
8757 | tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), |
8758 | tC3(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
e3cb604e | 8759 | CL(cmpp, 150f000, 2, (RR, SH), cmp), |
c19d1205 ZW |
8760 | tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), |
8761 | tC3(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
e3cb604e | 8762 | CL(cmnp, 170f000, 2, (RR, SH), cmp), |
c19d1205 ZW |
8763 | |
8764 | tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp), | |
8765 | tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp), | |
8766 | tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst), | |
8767 | tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst), | |
8768 | ||
8769 | tCE(ldr, 4100000, ldr, 2, (RR, ADDR), ldst, t_ldst), | |
8770 | tC3(ldrb, 4500000, ldrb, 2, (RR, ADDR), ldst, t_ldst), | |
8771 | tCE(str, 4000000, str, 2, (RR, ADDR), ldst, t_ldst), | |
8772 | tC3(strb, 4400000, strb, 2, (RR, ADDR), ldst, t_ldst), | |
8773 | ||
8774 | tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
8775 | tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
8776 | tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
8777 | tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
8778 | ||
8779 | TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi), | |
0110f2b8 | 8780 | tCE(b, a000000, b, 1, (EXPr), branch, t_branch), |
39b41c9c | 8781 | TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23), |
bfae80f2 | 8782 | |
c19d1205 | 8783 | /* Pseudo ops. */ |
e9f89963 | 8784 | tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac ZW |
8785 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
8786 | tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop), | |
c19d1205 ZW |
8787 | |
8788 | /* Thumb-compatibility pseudo ops. */ | |
8789 | tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift), | |
8790 | tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift), | |
8791 | tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift), | |
8792 | tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
8793 | tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift), | |
2fc8bdac | 8794 | tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift), |
c19d1205 ZW |
8795 | tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift), |
8796 | tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift), | |
8797 | tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg), | |
8798 | tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg), | |
8799 | tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop), | |
8800 | tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop), | |
8801 | ||
8802 | #undef THUMB_VARIANT | |
e74cfd16 | 8803 | #define THUMB_VARIANT &arm_ext_v6 |
2fc8bdac | 8804 | TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
8805 | |
8806 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
8807 | #undef THUMB_VARIANT | |
e74cfd16 | 8808 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
8809 | TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
8810 | TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
8811 | TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
8812 | TC3(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
e3cb604e | 8813 | CL(teqp, 130f000, 2, (RR, SH), cmp), |
c19d1205 ZW |
8814 | |
8815 | TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt), | |
8816 | TC3(ldrbt, 4700000, f8300e00, 2, (RR, ADDR), ldstt, t_ldstt), | |
8817 | TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt), | |
8818 | TC3(strbt, 4600000, f8200e00, 2, (RR, ADDR), ldstt, t_ldstt), | |
8819 | ||
9c3c69f2 PB |
8820 | TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
8821 | TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 8822 | |
9c3c69f2 PB |
8823 | TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
8824 | TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
8825 | |
8826 | /* V1 instructions with no Thumb analogue at all. */ | |
8827 | CE(rsc, 0e00000, 3, (RR, oRR, SH), arit), | |
8828 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), | |
8829 | ||
8830 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
8831 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
8832 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
8833 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
8834 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
8835 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
8836 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
8837 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
8838 | ||
8839 | #undef ARM_VARIANT | |
e74cfd16 | 8840 | #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */ |
c19d1205 | 8841 | #undef THUMB_VARIANT |
e74cfd16 | 8842 | #define THUMB_VARIANT &arm_ext_v4t |
c19d1205 ZW |
8843 | tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
8844 | tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
8845 | ||
8846 | #undef THUMB_VARIANT | |
e74cfd16 | 8847 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
8848 | TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
8849 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), | |
8850 | ||
8851 | /* Generic coprocessor instructions. */ | |
8852 | TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
8853 | TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8854 | TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8855 | TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8856 | TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8857 | TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
8858 | TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
8859 | ||
8860 | #undef ARM_VARIANT | |
e74cfd16 | 8861 | #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */ |
c19d1205 ZW |
8862 | CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
8863 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), | |
8864 | ||
8865 | #undef ARM_VARIANT | |
e74cfd16 | 8866 | #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */ |
c19d1205 ZW |
8867 | TCE(mrs, 10f0000, f3ef8000, 2, (RR, PSR), mrs, t_mrs), |
8868 | TCE(msr, 120f000, f3808000, 2, (PSR, RR_EXi), msr, t_msr), | |
8869 | ||
8870 | #undef ARM_VARIANT | |
e74cfd16 | 8871 | #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */ |
c19d1205 ZW |
8872 | TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
8873 | CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
8874 | TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
8875 | CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
8876 | TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
8877 | CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
8878 | TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
8879 | CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
8880 | ||
8881 | #undef ARM_VARIANT | |
e74cfd16 | 8882 | #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */ |
c19d1205 | 8883 | #undef THUMB_VARIANT |
e74cfd16 | 8884 | #define THUMB_VARIANT &arm_ext_v4t |
c19d1205 ZW |
8885 | tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDR), ldstv4, t_ldst), |
8886 | tC3(strh, 00000b0, strh, 2, (RR, ADDR), ldstv4, t_ldst), | |
8887 | tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst), | |
8888 | tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst), | |
8889 | tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst), | |
8890 | tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst), | |
8891 | ||
8892 | #undef ARM_VARIANT | |
e74cfd16 | 8893 | #define ARM_VARIANT &arm_ext_v4t_5 |
c19d1205 ZW |
8894 | /* ARM Architecture 4T. */ |
8895 | /* Note: bx (and blx) are required on V5, even if the processor does | |
8896 | not support Thumb. */ | |
8897 | TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx), | |
8898 | ||
8899 | #undef ARM_VARIANT | |
e74cfd16 | 8900 | #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */ |
c19d1205 | 8901 | #undef THUMB_VARIANT |
e74cfd16 | 8902 | #define THUMB_VARIANT &arm_ext_v5t |
c19d1205 ZW |
8903 | /* Note: blx has 2 variants; the .value coded here is for |
8904 | BLX(2). Only this variant has conditional execution. */ | |
8905 | TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx), | |
8906 | TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
8907 | ||
8908 | #undef THUMB_VARIANT | |
e74cfd16 | 8909 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
8910 | TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
8911 | TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8912 | TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8913 | TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8914 | TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8915 | TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
8916 | TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
8917 | TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
8918 | ||
8919 | #undef ARM_VARIANT | |
e74cfd16 | 8920 | #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */ |
c19d1205 ZW |
8921 | TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
8922 | TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
8923 | TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
8924 | TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
8925 | ||
8926 | TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
8927 | TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
8928 | ||
8929 | TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
8930 | TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
8931 | TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
8932 | TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
8933 | ||
8934 | TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8935 | TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8936 | TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8937 | TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8938 | ||
8939 | TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8940 | TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8941 | ||
8942 | TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
8943 | TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
8944 | TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
8945 | TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
8946 | ||
8947 | #undef ARM_VARIANT | |
e74cfd16 | 8948 | #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */ |
c19d1205 ZW |
8949 | TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld), |
8950 | TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd), | |
8951 | TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd), | |
8952 | ||
8953 | TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
8954 | TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
8955 | ||
8956 | #undef ARM_VARIANT | |
e74cfd16 | 8957 | #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */ |
c19d1205 ZW |
8958 | TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
8959 | ||
8960 | #undef ARM_VARIANT | |
e74cfd16 | 8961 | #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */ |
c19d1205 | 8962 | #undef THUMB_VARIANT |
e74cfd16 | 8963 | #define THUMB_VARIANT &arm_ext_v6 |
c19d1205 ZW |
8964 | TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
8965 | TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
8966 | tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
8967 | tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
8968 | tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
8969 | tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
8970 | tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
8971 | tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
8972 | tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
8973 | TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend), | |
8974 | ||
8975 | #undef THUMB_VARIANT | |
e74cfd16 | 8976 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
8977 | TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, imm0), |
8978 | TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex), | |
8979 | TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
8980 | TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
8981 | TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), | |
8982 | TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
8983 | TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8984 | TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8985 | TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8986 | TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8987 | TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8988 | TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8989 | TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8990 | TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8991 | TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8992 | TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8993 | TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8994 | TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8995 | TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8996 | TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8997 | TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8998 | TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8999 | TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9000 | TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9001 | TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9002 | TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9003 | TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9004 | TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9005 | TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9006 | TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9007 | TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9008 | TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9009 | TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9010 | TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9011 | TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9012 | TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9013 | TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9014 | TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9015 | TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9016 | TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9017 | TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9018 | TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9019 | TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
9020 | UF(rfeib, 9900a00, 1, (RRw), rfe), | |
9021 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
9022 | TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
9023 | TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
9024 | UF(rfefa, 9900a00, 1, (RRw), rfe), | |
9025 | UF(rfeea, 8100a00, 1, (RRw), rfe), | |
9026 | TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
9027 | TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
9028 | TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
9029 | TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
9030 | TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
9031 | TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
9032 | TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
9033 | TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
9034 | TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
f1022c90 | 9035 | TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
c19d1205 ZW |
9036 | TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), |
9037 | TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
9038 | TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
9039 | TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
9040 | TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
9041 | TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
9042 | TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
9043 | TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
9044 | TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
9045 | TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
9046 | TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
9047 | TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
9048 | TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9049 | TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9050 | TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9051 | TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9052 | TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9053 | TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9054 | TUF(srsia, 8cd0500, e980c000, 1, (I31w), srs, srs), | |
9055 | UF(srsib, 9cd0500, 1, (I31w), srs), | |
9056 | UF(srsda, 84d0500, 1, (I31w), srs), | |
9057 | TUF(srsdb, 94d0500, e800c000, 1, (I31w), srs, srs), | |
9058 | TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), | |
9059 | TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), | |
9060 | TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex), | |
9061 | TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
9062 | TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9063 | TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
9064 | TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
9065 | TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
9066 | ||
9067 | #undef ARM_VARIANT | |
e74cfd16 | 9068 | #define ARM_VARIANT &arm_ext_v6k |
c19d1205 | 9069 | #undef THUMB_VARIANT |
e74cfd16 | 9070 | #define THUMB_VARIANT &arm_ext_v6k |
c19d1205 ZW |
9071 | tCE(yield, 320f001, yield, 0, (), noargs, t_hint), |
9072 | tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint), | |
9073 | tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint), | |
9074 | tCE(sev, 320f004, sev, 0, (), noargs, t_hint), | |
9075 | ||
9076 | #undef THUMB_VARIANT | |
e74cfd16 | 9077 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
9078 | TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
9079 | TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
9080 | TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd), | |
9081 | TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), | |
9082 | TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), | |
9083 | TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd), | |
9084 | TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs), | |
9085 | ||
9086 | #undef ARM_VARIANT | |
e74cfd16 | 9087 | #define ARM_VARIANT &arm_ext_v6z |
3eb17e6b | 9088 | TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 ZW |
9089 | |
9090 | #undef ARM_VARIANT | |
e74cfd16 | 9091 | #define ARM_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
9092 | TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
9093 | TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
9094 | TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
9095 | TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
9096 | ||
9097 | TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), | |
9098 | TCE(movw, 3000000, f2400000, 2, (RRnpc, Iffff), mov16, t_mov16), | |
9099 | TCE(movt, 3400000, f2c00000, 2, (RRnpc, Iffff), mov16, t_mov16), | |
9100 | TCE(rbit, 3ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), | |
9101 | ||
9102 | TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
9103 | TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
9104 | TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
9105 | TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
9106 | ||
9107 | UT(cbnz, b900, 2, (RR, EXP), t_czb), | |
9108 | UT(cbz, b100, 2, (RR, EXP), t_czb), | |
9109 | /* ARM does not really have an IT instruction. */ | |
9110 | TUE(it, 0, bf08, 1, (COND), it, t_it), | |
9111 | TUE(itt, 0, bf0c, 1, (COND), it, t_it), | |
9112 | TUE(ite, 0, bf04, 1, (COND), it, t_it), | |
9113 | TUE(ittt, 0, bf0e, 1, (COND), it, t_it), | |
9114 | TUE(itet, 0, bf06, 1, (COND), it, t_it), | |
9115 | TUE(itte, 0, bf0a, 1, (COND), it, t_it), | |
9116 | TUE(itee, 0, bf02, 1, (COND), it, t_it), | |
9117 | TUE(itttt, 0, bf0f, 1, (COND), it, t_it), | |
9118 | TUE(itett, 0, bf07, 1, (COND), it, t_it), | |
9119 | TUE(ittet, 0, bf0b, 1, (COND), it, t_it), | |
9120 | TUE(iteet, 0, bf03, 1, (COND), it, t_it), | |
9121 | TUE(ittte, 0, bf0d, 1, (COND), it, t_it), | |
9122 | TUE(itete, 0, bf05, 1, (COND), it, t_it), | |
9123 | TUE(ittee, 0, bf09, 1, (COND), it, t_it), | |
9124 | TUE(iteee, 0, bf01, 1, (COND), it, t_it), | |
9125 | ||
92e90b6e PB |
9126 | /* Thumb2 only instructions. */ |
9127 | #undef ARM_VARIANT | |
e74cfd16 | 9128 | #define ARM_VARIANT NULL |
92e90b6e PB |
9129 | |
9130 | TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
9131 | TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
9132 | TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb), | |
9133 | TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb), | |
9134 | ||
c19d1205 | 9135 | #undef ARM_VARIANT |
e74cfd16 | 9136 | #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ |
8f06b2d8 PB |
9137 | cCE(wfs, e200110, 1, (RR), rd), |
9138 | cCE(rfs, e300110, 1, (RR), rd), | |
9139 | cCE(wfc, e400110, 1, (RR), rd), | |
9140 | cCE(rfc, e500110, 1, (RR), rd), | |
9141 | ||
e3cb604e PB |
9142 | cCL(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr), |
9143 | cCL(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr), | |
9144 | cCL(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr), | |
9145 | cCL(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr), | |
9146 | ||
9147 | cCL(stfs, c000100, 2, (RF, ADDR), rd_cpaddr), | |
9148 | cCL(stfd, c008100, 2, (RF, ADDR), rd_cpaddr), | |
9149 | cCL(stfe, c400100, 2, (RF, ADDR), rd_cpaddr), | |
9150 | cCL(stfp, c408100, 2, (RF, ADDR), rd_cpaddr), | |
9151 | ||
9152 | cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm), | |
9153 | cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm), | |
9154 | cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm), | |
9155 | cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm), | |
9156 | cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm), | |
9157 | cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm), | |
9158 | cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm), | |
9159 | cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm), | |
9160 | cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm), | |
9161 | cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm), | |
9162 | cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm), | |
9163 | cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm), | |
9164 | ||
9165 | cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm), | |
9166 | cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm), | |
9167 | cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm), | |
9168 | cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm), | |
9169 | cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm), | |
9170 | cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm), | |
9171 | cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm), | |
9172 | cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm), | |
9173 | cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm), | |
9174 | cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm), | |
9175 | cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm), | |
9176 | cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm), | |
9177 | ||
9178 | cCL(abss, e208100, 2, (RF, RF_IF), rd_rm), | |
9179 | cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm), | |
9180 | cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm), | |
9181 | cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm), | |
9182 | cCL(absd, e208180, 2, (RF, RF_IF), rd_rm), | |
9183 | cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm), | |
9184 | cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm), | |
9185 | cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm), | |
9186 | cCL(abse, e288100, 2, (RF, RF_IF), rd_rm), | |
9187 | cCL(absep, e288120, 2, (RF, RF_IF), rd_rm), | |
9188 | cCL(absem, e288140, 2, (RF, RF_IF), rd_rm), | |
9189 | cCL(absez, e288160, 2, (RF, RF_IF), rd_rm), | |
9190 | ||
9191 | cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm), | |
9192 | cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm), | |
9193 | cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm), | |
9194 | cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm), | |
9195 | cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm), | |
9196 | cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm), | |
9197 | cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm), | |
9198 | cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm), | |
9199 | cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm), | |
9200 | cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm), | |
9201 | cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm), | |
9202 | cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm), | |
9203 | ||
9204 | cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm), | |
9205 | cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm), | |
9206 | cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm), | |
9207 | cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm), | |
9208 | cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm), | |
9209 | cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm), | |
9210 | cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm), | |
9211 | cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm), | |
9212 | cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm), | |
9213 | cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm), | |
9214 | cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm), | |
9215 | cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm), | |
9216 | ||
9217 | cCL(logs, e508100, 2, (RF, RF_IF), rd_rm), | |
9218 | cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm), | |
9219 | cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm), | |
9220 | cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm), | |
9221 | cCL(logd, e508180, 2, (RF, RF_IF), rd_rm), | |
9222 | cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm), | |
9223 | cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm), | |
9224 | cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm), | |
9225 | cCL(loge, e588100, 2, (RF, RF_IF), rd_rm), | |
9226 | cCL(logep, e588120, 2, (RF, RF_IF), rd_rm), | |
9227 | cCL(logem, e588140, 2, (RF, RF_IF), rd_rm), | |
9228 | cCL(logez, e588160, 2, (RF, RF_IF), rd_rm), | |
9229 | ||
9230 | cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm), | |
9231 | cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm), | |
9232 | cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm), | |
9233 | cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm), | |
9234 | cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm), | |
9235 | cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm), | |
9236 | cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm), | |
9237 | cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm), | |
9238 | cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm), | |
9239 | cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm), | |
9240 | cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm), | |
9241 | cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm), | |
9242 | ||
9243 | cCL(exps, e708100, 2, (RF, RF_IF), rd_rm), | |
9244 | cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm), | |
9245 | cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm), | |
9246 | cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm), | |
9247 | cCL(expd, e708180, 2, (RF, RF_IF), rd_rm), | |
9248 | cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm), | |
9249 | cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm), | |
9250 | cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm), | |
9251 | cCL(expe, e788100, 2, (RF, RF_IF), rd_rm), | |
9252 | cCL(expep, e788120, 2, (RF, RF_IF), rd_rm), | |
9253 | cCL(expem, e788140, 2, (RF, RF_IF), rd_rm), | |
9254 | cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm), | |
9255 | ||
9256 | cCL(sins, e808100, 2, (RF, RF_IF), rd_rm), | |
9257 | cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm), | |
9258 | cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm), | |
9259 | cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm), | |
9260 | cCL(sind, e808180, 2, (RF, RF_IF), rd_rm), | |
9261 | cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm), | |
9262 | cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm), | |
9263 | cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm), | |
9264 | cCL(sine, e888100, 2, (RF, RF_IF), rd_rm), | |
9265 | cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm), | |
9266 | cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm), | |
9267 | cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm), | |
9268 | ||
9269 | cCL(coss, e908100, 2, (RF, RF_IF), rd_rm), | |
9270 | cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm), | |
9271 | cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm), | |
9272 | cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm), | |
9273 | cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm), | |
9274 | cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm), | |
9275 | cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm), | |
9276 | cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm), | |
9277 | cCL(cose, e988100, 2, (RF, RF_IF), rd_rm), | |
9278 | cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm), | |
9279 | cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm), | |
9280 | cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm), | |
9281 | ||
9282 | cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm), | |
9283 | cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm), | |
9284 | cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm), | |
9285 | cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm), | |
9286 | cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm), | |
9287 | cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm), | |
9288 | cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm), | |
9289 | cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm), | |
9290 | cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm), | |
9291 | cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm), | |
9292 | cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm), | |
9293 | cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm), | |
9294 | ||
9295 | cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm), | |
9296 | cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm), | |
9297 | cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm), | |
9298 | cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm), | |
9299 | cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm), | |
9300 | cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm), | |
9301 | cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm), | |
9302 | cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm), | |
9303 | cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm), | |
9304 | cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm), | |
9305 | cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm), | |
9306 | cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm), | |
9307 | ||
9308 | cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm), | |
9309 | cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm), | |
9310 | cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm), | |
9311 | cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm), | |
9312 | cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm), | |
9313 | cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm), | |
9314 | cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm), | |
9315 | cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm), | |
9316 | cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm), | |
9317 | cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm), | |
9318 | cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm), | |
9319 | cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm), | |
9320 | ||
9321 | cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm), | |
9322 | cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm), | |
9323 | cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm), | |
9324 | cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm), | |
9325 | cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm), | |
9326 | cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm), | |
9327 | cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm), | |
9328 | cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm), | |
9329 | cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm), | |
9330 | cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm), | |
9331 | cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm), | |
9332 | cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm), | |
9333 | ||
9334 | cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm), | |
9335 | cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm), | |
9336 | cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm), | |
9337 | cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm), | |
9338 | cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm), | |
9339 | cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm), | |
9340 | cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm), | |
9341 | cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm), | |
9342 | cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm), | |
9343 | cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm), | |
9344 | cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm), | |
9345 | cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm), | |
9346 | ||
9347 | cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm), | |
9348 | cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm), | |
9349 | cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm), | |
9350 | cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm), | |
9351 | cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm), | |
9352 | cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm), | |
9353 | cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm), | |
9354 | cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm), | |
9355 | cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm), | |
9356 | cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm), | |
9357 | cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm), | |
9358 | cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm), | |
9359 | ||
9360 | cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9361 | cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9362 | cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9363 | cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9364 | cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9365 | cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9366 | cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9367 | cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9368 | cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9369 | cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9370 | cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9371 | cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9372 | ||
9373 | cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9374 | cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9375 | cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9376 | cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9377 | cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9378 | cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9379 | cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9380 | cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9381 | cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9382 | cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9383 | cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9384 | cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9385 | ||
9386 | cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9387 | cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9388 | cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9389 | cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9390 | cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9391 | cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9392 | cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9393 | cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9394 | cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9395 | cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9396 | cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9397 | cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9398 | ||
9399 | cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9400 | cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9401 | cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9402 | cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9403 | cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9404 | cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9405 | cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9406 | cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9407 | cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9408 | cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9409 | cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9410 | cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9411 | ||
9412 | cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9413 | cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9414 | cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9415 | cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9416 | cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9417 | cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9418 | cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9419 | cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9420 | cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9421 | cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9422 | cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9423 | cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9424 | ||
9425 | cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9426 | cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9427 | cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9428 | cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9429 | cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9430 | cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9431 | cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9432 | cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9433 | cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9434 | cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9435 | cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9436 | cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9437 | ||
9438 | cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9439 | cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9440 | cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9441 | cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9442 | cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9443 | cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9444 | cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9445 | cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9446 | cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9447 | cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9448 | cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9449 | cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9450 | ||
9451 | cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9452 | cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9453 | cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9454 | cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9455 | cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9456 | cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9457 | cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9458 | cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9459 | cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9460 | cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9461 | cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9462 | cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9463 | ||
9464 | cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9465 | cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9466 | cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9467 | cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9468 | cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9469 | cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9470 | cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9471 | cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9472 | cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9473 | cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9474 | cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9475 | cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9476 | ||
9477 | cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9478 | cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9479 | cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9480 | cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9481 | cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9482 | cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9483 | cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9484 | cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9485 | cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9486 | cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9487 | cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9488 | cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9489 | ||
9490 | cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9491 | cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9492 | cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9493 | cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9494 | cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9495 | cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9496 | cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9497 | cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9498 | cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9499 | cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9500 | cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9501 | cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9502 | ||
9503 | cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9504 | cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9505 | cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9506 | cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9507 | cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9508 | cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9509 | cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9510 | cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9511 | cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9512 | cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9513 | cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9514 | cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9515 | ||
9516 | cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9517 | cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9518 | cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9519 | cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9520 | cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9521 | cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9522 | cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9523 | cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9524 | cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9525 | cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9526 | cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9527 | cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8f06b2d8 PB |
9528 | |
9529 | cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp), | |
c19d1205 | 9530 | C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp), |
8f06b2d8 | 9531 | cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp), |
c19d1205 ZW |
9532 | C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp), |
9533 | ||
e3cb604e PB |
9534 | cCL(flts, e000110, 2, (RF, RR), rn_rd), |
9535 | cCL(fltsp, e000130, 2, (RF, RR), rn_rd), | |
9536 | cCL(fltsm, e000150, 2, (RF, RR), rn_rd), | |
9537 | cCL(fltsz, e000170, 2, (RF, RR), rn_rd), | |
9538 | cCL(fltd, e000190, 2, (RF, RR), rn_rd), | |
9539 | cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd), | |
9540 | cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd), | |
9541 | cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd), | |
9542 | cCL(flte, e080110, 2, (RF, RR), rn_rd), | |
9543 | cCL(fltep, e080130, 2, (RF, RR), rn_rd), | |
9544 | cCL(fltem, e080150, 2, (RF, RR), rn_rd), | |
9545 | cCL(fltez, e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 9546 | |
c19d1205 ZW |
9547 | /* The implementation of the FIX instruction is broken on some |
9548 | assemblers, in that it accepts a precision specifier as well as a | |
9549 | rounding specifier, despite the fact that this is meaningless. | |
9550 | To be more compatible, we accept it as well, though of course it | |
9551 | does not set any bits. */ | |
8f06b2d8 | 9552 | cCE(fix, e100110, 2, (RR, RF), rd_rm), |
e3cb604e PB |
9553 | cCL(fixp, e100130, 2, (RR, RF), rd_rm), |
9554 | cCL(fixm, e100150, 2, (RR, RF), rd_rm), | |
9555 | cCL(fixz, e100170, 2, (RR, RF), rd_rm), | |
9556 | cCL(fixsp, e100130, 2, (RR, RF), rd_rm), | |
9557 | cCL(fixsm, e100150, 2, (RR, RF), rd_rm), | |
9558 | cCL(fixsz, e100170, 2, (RR, RF), rd_rm), | |
9559 | cCL(fixdp, e100130, 2, (RR, RF), rd_rm), | |
9560 | cCL(fixdm, e100150, 2, (RR, RF), rd_rm), | |
9561 | cCL(fixdz, e100170, 2, (RR, RF), rd_rm), | |
9562 | cCL(fixep, e100130, 2, (RR, RF), rd_rm), | |
9563 | cCL(fixem, e100150, 2, (RR, RF), rd_rm), | |
9564 | cCL(fixez, e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 9565 | |
c19d1205 ZW |
9566 | /* Instructions that were new with the real FPA, call them V2. */ |
9567 | #undef ARM_VARIANT | |
e74cfd16 | 9568 | #define ARM_VARIANT &fpu_fpa_ext_v2 |
8f06b2d8 | 9569 | cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
e3cb604e PB |
9570 | cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
9571 | cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
8f06b2d8 | 9572 | cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
e3cb604e PB |
9573 | cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
9574 | cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 ZW |
9575 | |
9576 | #undef ARM_VARIANT | |
e74cfd16 | 9577 | #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ |
c19d1205 | 9578 | /* Moves and type conversions. */ |
8f06b2d8 PB |
9579 | cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
9580 | cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
9581 | cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
9582 | cCE(fmstat, ef1fa10, 0, (), noargs), | |
9583 | cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
9584 | cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
9585 | cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
9586 | cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
9587 | cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
9588 | cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
9589 | cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn), | |
9590 | cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
9591 | |
9592 | /* Memory operations. */ | |
8f06b2d8 PB |
9593 | cCE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst), |
9594 | cCE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst), | |
9595 | cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
9596 | cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
9597 | cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
9598 | cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
9599 | cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
9600 | cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
9601 | cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
9602 | cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
9603 | cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
9604 | cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
9605 | cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
9606 | cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
9607 | cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
9608 | cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
9609 | cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
9610 | cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 9611 | |
c19d1205 | 9612 | /* Monadic operations. */ |
8f06b2d8 PB |
9613 | cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
9614 | cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
9615 | cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
9616 | |
9617 | /* Dyadic operations. */ | |
8f06b2d8 PB |
9618 | cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
9619 | cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9620 | cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9621 | cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9622 | cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9623 | cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9624 | cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9625 | cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9626 | cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 9627 | |
c19d1205 | 9628 | /* Comparisons. */ |
8f06b2d8 PB |
9629 | cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
9630 | cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z), | |
9631 | cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
9632 | cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 9633 | |
c19d1205 | 9634 | #undef ARM_VARIANT |
e74cfd16 | 9635 | #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ |
c19d1205 | 9636 | /* Moves and type conversions. */ |
8f06b2d8 PB |
9637 | cCE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm), |
9638 | cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
9639 | cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
9640 | cCE(fmdhr, e200b10, 2, (RVD, RR), rn_rd), | |
9641 | cCE(fmdlr, e000b10, 2, (RVD, RR), rn_rd), | |
9642 | cCE(fmrdh, e300b10, 2, (RR, RVD), rd_rn), | |
9643 | cCE(fmrdl, e100b10, 2, (RR, RVD), rd_rn), | |
9644 | cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
9645 | cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
9646 | cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
9647 | cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
9648 | cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
9649 | cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 ZW |
9650 | |
9651 | /* Memory operations. */ | |
8f06b2d8 PB |
9652 | cCE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst), |
9653 | cCE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst), | |
9654 | cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
9655 | cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
9656 | cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
9657 | cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
9658 | cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
9659 | cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
9660 | cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
9661 | cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
b99bd4ef | 9662 | |
c19d1205 | 9663 | /* Monadic operations. */ |
8f06b2d8 PB |
9664 | cCE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm), |
9665 | cCE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm), | |
9666 | cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm), | |
c19d1205 ZW |
9667 | |
9668 | /* Dyadic operations. */ | |
8f06b2d8 PB |
9669 | cCE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm), |
9670 | cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9671 | cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9672 | cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9673 | cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9674 | cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9675 | cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9676 | cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9677 | cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm), | |
b99bd4ef | 9678 | |
c19d1205 | 9679 | /* Comparisons. */ |
8f06b2d8 PB |
9680 | cCE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm), |
9681 | cCE(fcmpzd, eb50b40, 1, (RVD), rd), | |
9682 | cCE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm), | |
9683 | cCE(fcmpezd, eb50bc0, 1, (RVD), rd), | |
c19d1205 ZW |
9684 | |
9685 | #undef ARM_VARIANT | |
e74cfd16 | 9686 | #define ARM_VARIANT &fpu_vfp_ext_v2 |
8f06b2d8 PB |
9687 | cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
9688 | cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
9689 | cCE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn), | |
9690 | cCE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm), | |
c19d1205 ZW |
9691 | |
9692 | #undef ARM_VARIANT | |
e74cfd16 | 9693 | #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */ |
8f06b2d8 PB |
9694 | cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
9695 | cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9696 | cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9697 | cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9698 | cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9699 | cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9700 | cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
9701 | cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 ZW |
9702 | |
9703 | #undef ARM_VARIANT | |
e74cfd16 | 9704 | #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */ |
8f06b2d8 PB |
9705 | cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc), |
9706 | cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc), | |
9707 | cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc), | |
9708 | cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd), | |
9709 | cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd), | |
9710 | cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd), | |
9711 | cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc), | |
9712 | cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc), | |
9713 | cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc), | |
9714 | cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9715 | cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9716 | cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9717 | cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9718 | cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9719 | cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9720 | cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
9721 | cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
9722 | cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
9723 | cCE(tmcr, e000110, 2, (RIWC, RR), rn_rd), | |
9724 | cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
9725 | cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9726 | cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9727 | cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9728 | cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9729 | cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9730 | cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9731 | cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn), | |
9732 | cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn), | |
9733 | cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn), | |
9734 | cCE(tmrc, e100110, 2, (RR, RIWC), rd_rn), | |
9735 | cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
9736 | cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc), | |
9737 | cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc), | |
9738 | cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc), | |
9739 | cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn), | |
9740 | cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn), | |
9741 | cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn), | |
9742 | cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9743 | cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9744 | cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9745 | cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9746 | cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9747 | cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9748 | cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9749 | cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9750 | cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9751 | cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
9752 | cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9753 | cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9754 | cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9755 | cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9756 | cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9757 | cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9758 | cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9759 | cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9760 | cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9761 | cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9762 | cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9763 | cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9764 | cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9765 | cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9766 | cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9767 | cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9768 | cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9769 | cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9770 | cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9771 | cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
9772 | cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
9773 | cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
9774 | cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
9775 | cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9776 | cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9777 | cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9778 | cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9779 | cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9780 | cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9781 | cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9782 | cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9783 | cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9784 | cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9785 | cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9786 | cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9787 | cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9788 | cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9789 | cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9790 | cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9791 | cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9792 | cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9793 | cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
9794 | cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9795 | cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9796 | cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9797 | cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9798 | cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9799 | cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9800 | cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9801 | cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9802 | cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9803 | cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9804 | cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9805 | cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9806 | cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9807 | cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9808 | cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9809 | cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9810 | cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9811 | cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9812 | cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9813 | cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9814 | cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9815 | cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
9816 | cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9817 | cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9818 | cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9819 | cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9820 | cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9821 | cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9822 | cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9823 | cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9824 | cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9825 | cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9826 | cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9827 | cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9828 | cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9829 | cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9830 | cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9831 | cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9832 | cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9833 | cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9834 | cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
9835 | cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
9836 | cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
9837 | cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
9838 | cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9839 | cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9840 | cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9841 | cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9842 | cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9843 | cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9844 | cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9845 | cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9846 | cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9847 | cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn), | |
9848 | cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn), | |
9849 | cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn), | |
9850 | cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn), | |
9851 | cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn), | |
9852 | cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn), | |
9853 | cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9854 | cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9855 | cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9856 | cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn), | |
9857 | cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn), | |
9858 | cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn), | |
9859 | cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn), | |
9860 | cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn), | |
9861 | cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn), | |
9862 | cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9863 | cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9864 | cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9865 | cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9866 | cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 ZW |
9867 | |
9868 | #undef ARM_VARIANT | |
e74cfd16 | 9869 | #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */ |
8f06b2d8 PB |
9870 | cCE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr), |
9871 | cCE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr), | |
9872 | cCE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr), | |
9873 | cCE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr), | |
9874 | cCE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr), | |
9875 | cCE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr), | |
9876 | cCE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr), | |
9877 | cCE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr), | |
9878 | cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd), | |
9879 | cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn), | |
9880 | cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd), | |
9881 | cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn), | |
9882 | cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd), | |
9883 | cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn), | |
9884 | cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd), | |
9885 | cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn), | |
9886 | cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd), | |
9887 | cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn), | |
9888 | cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn), | |
9889 | cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn), | |
9890 | cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn), | |
9891 | cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn), | |
9892 | cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn), | |
9893 | cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn), | |
9894 | cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn), | |
9895 | cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn), | |
9896 | cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn), | |
9897 | cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn), | |
9898 | cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc), | |
9899 | cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd), | |
9900 | cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn), | |
9901 | cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn), | |
9902 | cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn), | |
9903 | cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn), | |
9904 | cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn), | |
9905 | cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn), | |
9906 | cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn), | |
9907 | cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn), | |
9908 | cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn), | |
9909 | cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn), | |
9910 | cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn), | |
9911 | cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn), | |
9912 | cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple), | |
9913 | cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
9914 | cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift), | |
9915 | cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
9916 | cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
9917 | cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
9918 | cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
9919 | cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
9920 | cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn), | |
9921 | cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn), | |
9922 | cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn), | |
9923 | cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn), | |
9924 | cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
9925 | cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
9926 | cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
9927 | cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
9928 | cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
9929 | cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
9930 | cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn), | |
9931 | cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn), | |
9932 | cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn), | |
9933 | cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn), | |
9934 | cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
9935 | cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
9936 | cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
9937 | cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
9938 | cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
9939 | cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
9940 | cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
9941 | cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
9942 | cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
9943 | cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
9944 | cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
9945 | cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
9946 | }; |
9947 | #undef ARM_VARIANT | |
9948 | #undef THUMB_VARIANT | |
9949 | #undef TCE | |
9950 | #undef TCM | |
9951 | #undef TUE | |
9952 | #undef TUF | |
9953 | #undef TCC | |
8f06b2d8 | 9954 | #undef cCE |
e3cb604e PB |
9955 | #undef cCL |
9956 | #undef C3E | |
c19d1205 ZW |
9957 | #undef CE |
9958 | #undef CM | |
9959 | #undef UE | |
9960 | #undef UF | |
9961 | #undef UT | |
9962 | #undef OPS0 | |
9963 | #undef OPS1 | |
9964 | #undef OPS2 | |
9965 | #undef OPS3 | |
9966 | #undef OPS4 | |
9967 | #undef OPS5 | |
9968 | #undef OPS6 | |
9969 | #undef do_0 | |
9970 | \f | |
9971 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 9972 | |
c19d1205 ZW |
9973 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
9974 | for use in the a.out file, and stores them in the array pointed to by buf. | |
9975 | This knows about the endian-ness of the target machine and does | |
9976 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
9977 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
9978 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 9979 | |
c19d1205 ZW |
9980 | void |
9981 | md_number_to_chars (char * buf, valueT val, int n) | |
9982 | { | |
9983 | if (target_big_endian) | |
9984 | number_to_chars_bigendian (buf, val, n); | |
9985 | else | |
9986 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
9987 | } |
9988 | ||
c19d1205 ZW |
9989 | static valueT |
9990 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 9991 | { |
c19d1205 ZW |
9992 | valueT result = 0; |
9993 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 9994 | |
c19d1205 | 9995 | if (target_big_endian) |
b99bd4ef | 9996 | { |
c19d1205 ZW |
9997 | while (n--) |
9998 | { | |
9999 | result <<= 8; | |
10000 | result |= (*where++ & 255); | |
10001 | } | |
b99bd4ef | 10002 | } |
c19d1205 | 10003 | else |
b99bd4ef | 10004 | { |
c19d1205 ZW |
10005 | while (n--) |
10006 | { | |
10007 | result <<= 8; | |
10008 | result |= (where[n] & 255); | |
10009 | } | |
bfae80f2 | 10010 | } |
b99bd4ef | 10011 | |
c19d1205 | 10012 | return result; |
bfae80f2 | 10013 | } |
b99bd4ef | 10014 | |
c19d1205 | 10015 | /* MD interface: Sections. */ |
b99bd4ef | 10016 | |
0110f2b8 PB |
10017 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
10018 | 2 bytes. */ | |
10019 | ||
c19d1205 | 10020 | int |
0110f2b8 | 10021 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
10022 | segT segtype ATTRIBUTE_UNUSED) |
10023 | { | |
0110f2b8 PB |
10024 | fragp->fr_var = 2; |
10025 | return 2; | |
10026 | } | |
10027 | ||
10028 | /* Convert a machine dependent frag. */ | |
10029 | ||
10030 | void | |
10031 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
10032 | { | |
10033 | unsigned long insn; | |
10034 | unsigned long old_op; | |
10035 | char *buf; | |
10036 | expressionS exp; | |
10037 | fixS *fixp; | |
10038 | int reloc_type; | |
10039 | int pc_rel; | |
10040 | int opcode; | |
10041 | ||
10042 | buf = fragp->fr_literal + fragp->fr_fix; | |
10043 | ||
10044 | old_op = bfd_get_16(abfd, buf); | |
10045 | if (fragp->fr_symbol) { | |
10046 | exp.X_op = O_symbol; | |
10047 | exp.X_add_symbol = fragp->fr_symbol; | |
10048 | } else { | |
10049 | exp.X_op = O_constant; | |
10050 | } | |
10051 | exp.X_add_number = fragp->fr_offset; | |
10052 | opcode = fragp->fr_subtype; | |
10053 | switch (opcode) | |
10054 | { | |
10055 | case T_MNEM_ldr_pc: | |
10056 | case T_MNEM_ldr_pc2: | |
10057 | case T_MNEM_ldr_sp: | |
10058 | case T_MNEM_str_sp: | |
10059 | case T_MNEM_ldr: | |
10060 | case T_MNEM_ldrb: | |
10061 | case T_MNEM_ldrh: | |
10062 | case T_MNEM_str: | |
10063 | case T_MNEM_strb: | |
10064 | case T_MNEM_strh: | |
10065 | if (fragp->fr_var == 4) | |
10066 | { | |
10067 | insn = THUMB_OP32(opcode); | |
10068 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) | |
10069 | { | |
10070 | insn |= (old_op & 0x700) << 4; | |
10071 | } | |
10072 | else | |
10073 | { | |
10074 | insn |= (old_op & 7) << 12; | |
10075 | insn |= (old_op & 0x38) << 13; | |
10076 | } | |
10077 | insn |= 0x00000c00; | |
10078 | put_thumb32_insn (buf, insn); | |
10079 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
10080 | } | |
10081 | else | |
10082 | { | |
10083 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10084 | } | |
10085 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
10086 | break; | |
10087 | case T_MNEM_adr: | |
10088 | if (fragp->fr_var == 4) | |
10089 | { | |
10090 | insn = THUMB_OP32 (opcode); | |
10091 | insn |= (old_op & 0xf0) << 4; | |
10092 | put_thumb32_insn (buf, insn); | |
10093 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
10094 | } | |
10095 | else | |
10096 | { | |
10097 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
10098 | exp.X_add_number -= 4; | |
10099 | } | |
10100 | pc_rel = 1; | |
10101 | break; | |
10102 | case T_MNEM_mov: | |
10103 | case T_MNEM_movs: | |
10104 | case T_MNEM_cmp: | |
10105 | case T_MNEM_cmn: | |
10106 | if (fragp->fr_var == 4) | |
10107 | { | |
10108 | int r0off = (opcode == T_MNEM_mov | |
10109 | || opcode == T_MNEM_movs) ? 0 : 8; | |
10110 | insn = THUMB_OP32 (opcode); | |
10111 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
10112 | insn |= (old_op & 0x700) << r0off; | |
10113 | put_thumb32_insn (buf, insn); | |
10114 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10115 | } | |
10116 | else | |
10117 | { | |
10118 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
10119 | } | |
10120 | pc_rel = 0; | |
10121 | break; | |
10122 | case T_MNEM_b: | |
10123 | if (fragp->fr_var == 4) | |
10124 | { | |
10125 | insn = THUMB_OP32(opcode); | |
10126 | put_thumb32_insn (buf, insn); | |
10127 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
10128 | } | |
10129 | else | |
10130 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
10131 | pc_rel = 1; | |
10132 | break; | |
10133 | case T_MNEM_bcond: | |
10134 | if (fragp->fr_var == 4) | |
10135 | { | |
10136 | insn = THUMB_OP32(opcode); | |
10137 | insn |= (old_op & 0xf00) << 14; | |
10138 | put_thumb32_insn (buf, insn); | |
10139 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
10140 | } | |
10141 | else | |
10142 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
10143 | pc_rel = 1; | |
10144 | break; | |
10145 | case T_MNEM_add_sp: | |
10146 | case T_MNEM_add_pc: | |
10147 | case T_MNEM_inc_sp: | |
10148 | case T_MNEM_dec_sp: | |
10149 | if (fragp->fr_var == 4) | |
10150 | { | |
10151 | /* ??? Choose between add and addw. */ | |
10152 | insn = THUMB_OP32 (opcode); | |
10153 | insn |= (old_op & 0xf0) << 4; | |
10154 | put_thumb32_insn (buf, insn); | |
10155 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10156 | } | |
10157 | else | |
10158 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
10159 | pc_rel = 0; | |
10160 | break; | |
10161 | ||
10162 | case T_MNEM_addi: | |
10163 | case T_MNEM_addis: | |
10164 | case T_MNEM_subi: | |
10165 | case T_MNEM_subis: | |
10166 | if (fragp->fr_var == 4) | |
10167 | { | |
10168 | insn = THUMB_OP32 (opcode); | |
10169 | insn |= (old_op & 0xf0) << 4; | |
10170 | insn |= (old_op & 0xf) << 16; | |
10171 | put_thumb32_insn (buf, insn); | |
10172 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10173 | } | |
10174 | else | |
10175 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
10176 | pc_rel = 0; | |
10177 | break; | |
10178 | default: | |
10179 | abort(); | |
10180 | } | |
10181 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
10182 | reloc_type); | |
10183 | fixp->fx_file = fragp->fr_file; | |
10184 | fixp->fx_line = fragp->fr_line; | |
10185 | fragp->fr_fix += fragp->fr_var; | |
10186 | } | |
10187 | ||
10188 | /* Return the size of a relaxable immediate operand instruction. | |
10189 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
10190 | static int | |
10191 | relax_immediate (fragS *fragp, int size, int shift) | |
10192 | { | |
10193 | offsetT offset; | |
10194 | offsetT mask; | |
10195 | offsetT low; | |
10196 | ||
10197 | /* ??? Should be able to do better than this. */ | |
10198 | if (fragp->fr_symbol) | |
10199 | return 4; | |
10200 | ||
10201 | low = (1 << shift) - 1; | |
10202 | mask = (1 << (shift + size)) - (1 << shift); | |
10203 | offset = fragp->fr_offset; | |
10204 | /* Force misaligned offsets to 32-bit variant. */ | |
10205 | if (offset & low) | |
10206 | return -4; | |
10207 | if (offset & ~mask) | |
10208 | return 4; | |
10209 | return 2; | |
10210 | } | |
10211 | ||
10212 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative | |
10213 | load. */ | |
10214 | static int | |
10215 | relax_adr (fragS *fragp, asection *sec) | |
10216 | { | |
10217 | addressT addr; | |
10218 | offsetT val; | |
10219 | ||
10220 | /* Assume worst case for symbols not known to be in the same section. */ | |
10221 | if (!S_IS_DEFINED(fragp->fr_symbol) | |
10222 | || sec != S_GET_SEGMENT (fragp->fr_symbol)) | |
10223 | return 4; | |
10224 | ||
10225 | val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset; | |
10226 | addr = fragp->fr_address + fragp->fr_fix; | |
10227 | addr = (addr + 4) & ~3; | |
10228 | /* Fix the insn as the 4-byte version if the target address is not | |
10229 | sufficiently aligned. This is prevents an infinite loop when two | |
10230 | instructions have contradictory range/alignment requirements. */ | |
10231 | if (val & 3) | |
10232 | return -4; | |
10233 | val -= addr; | |
10234 | if (val < 0 || val > 1020) | |
10235 | return 4; | |
10236 | return 2; | |
10237 | } | |
10238 | ||
10239 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
10240 | static int | |
10241 | relax_addsub (fragS *fragp, asection *sec) | |
10242 | { | |
10243 | char *buf; | |
10244 | int op; | |
10245 | ||
10246 | buf = fragp->fr_literal + fragp->fr_fix; | |
10247 | op = bfd_get_16(sec->owner, buf); | |
10248 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
10249 | return relax_immediate (fragp, 8, 0); | |
10250 | else | |
10251 | return relax_immediate (fragp, 3, 0); | |
10252 | } | |
10253 | ||
10254 | ||
10255 | /* Return the size of a relaxable branch instruction. BITS is the | |
10256 | size of the offset field in the narrow instruction. */ | |
10257 | ||
10258 | static int | |
10259 | relax_branch (fragS *fragp, asection *sec, int bits) | |
10260 | { | |
10261 | addressT addr; | |
10262 | offsetT val; | |
10263 | offsetT limit; | |
10264 | ||
10265 | /* Assume worst case for symbols not known to be in the same section. */ | |
10266 | if (!S_IS_DEFINED(fragp->fr_symbol) | |
10267 | || sec != S_GET_SEGMENT (fragp->fr_symbol)) | |
10268 | return 4; | |
10269 | ||
10270 | val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset; | |
10271 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
10272 | val -= addr; | |
10273 | ||
10274 | /* Offset is a signed value *2 */ | |
10275 | limit = 1 << bits; | |
10276 | if (val >= limit || val < -limit) | |
10277 | return 4; | |
10278 | return 2; | |
10279 | } | |
10280 | ||
10281 | ||
10282 | /* Relax a machine dependent frag. This returns the amount by which | |
10283 | the current size of the frag should change. */ | |
10284 | ||
10285 | int | |
10286 | arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED) | |
10287 | { | |
10288 | int oldsize; | |
10289 | int newsize; | |
10290 | ||
10291 | oldsize = fragp->fr_var; | |
10292 | switch (fragp->fr_subtype) | |
10293 | { | |
10294 | case T_MNEM_ldr_pc2: | |
10295 | newsize = relax_adr(fragp, sec); | |
10296 | break; | |
10297 | case T_MNEM_ldr_pc: | |
10298 | case T_MNEM_ldr_sp: | |
10299 | case T_MNEM_str_sp: | |
10300 | newsize = relax_immediate(fragp, 8, 2); | |
10301 | break; | |
10302 | case T_MNEM_ldr: | |
10303 | case T_MNEM_str: | |
10304 | newsize = relax_immediate(fragp, 5, 2); | |
10305 | break; | |
10306 | case T_MNEM_ldrh: | |
10307 | case T_MNEM_strh: | |
10308 | newsize = relax_immediate(fragp, 5, 1); | |
10309 | break; | |
10310 | case T_MNEM_ldrb: | |
10311 | case T_MNEM_strb: | |
10312 | newsize = relax_immediate(fragp, 5, 0); | |
10313 | break; | |
10314 | case T_MNEM_adr: | |
10315 | newsize = relax_adr(fragp, sec); | |
10316 | break; | |
10317 | case T_MNEM_mov: | |
10318 | case T_MNEM_movs: | |
10319 | case T_MNEM_cmp: | |
10320 | case T_MNEM_cmn: | |
10321 | newsize = relax_immediate(fragp, 8, 0); | |
10322 | break; | |
10323 | case T_MNEM_b: | |
10324 | newsize = relax_branch(fragp, sec, 11); | |
10325 | break; | |
10326 | case T_MNEM_bcond: | |
10327 | newsize = relax_branch(fragp, sec, 8); | |
10328 | break; | |
10329 | case T_MNEM_add_sp: | |
10330 | case T_MNEM_add_pc: | |
10331 | newsize = relax_immediate (fragp, 8, 2); | |
10332 | break; | |
10333 | case T_MNEM_inc_sp: | |
10334 | case T_MNEM_dec_sp: | |
10335 | newsize = relax_immediate (fragp, 7, 2); | |
10336 | break; | |
10337 | case T_MNEM_addi: | |
10338 | case T_MNEM_addis: | |
10339 | case T_MNEM_subi: | |
10340 | case T_MNEM_subis: | |
10341 | newsize = relax_addsub (fragp, sec); | |
10342 | break; | |
10343 | default: | |
10344 | abort(); | |
10345 | } | |
10346 | if (newsize < 0) | |
10347 | { | |
10348 | fragp->fr_var = -newsize; | |
10349 | md_convert_frag (sec->owner, sec, fragp); | |
10350 | frag_wane(fragp); | |
10351 | return -(newsize + oldsize); | |
10352 | } | |
10353 | fragp->fr_var = newsize; | |
10354 | return newsize - oldsize; | |
c19d1205 | 10355 | } |
b99bd4ef | 10356 | |
c19d1205 | 10357 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 10358 | |
c19d1205 ZW |
10359 | valueT |
10360 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
10361 | valueT size) | |
10362 | { | |
10363 | #ifdef OBJ_ELF | |
10364 | return size; | |
10365 | #else | |
10366 | /* Round all sects to multiple of 4. */ | |
10367 | return (size + 3) & ~3; | |
10368 | #endif | |
bfae80f2 | 10369 | } |
b99bd4ef | 10370 | |
c19d1205 ZW |
10371 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
10372 | of an rs_align_code fragment. */ | |
10373 | ||
10374 | void | |
10375 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 10376 | { |
c19d1205 ZW |
10377 | static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 }; |
10378 | static char const thumb_noop[2] = { 0xc0, 0x46 }; | |
10379 | static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 }; | |
10380 | static char const thumb_bigend_noop[2] = { 0x46, 0xc0 }; | |
10381 | ||
10382 | int bytes, fix, noop_size; | |
10383 | char * p; | |
10384 | const char * noop; | |
bfae80f2 | 10385 | |
c19d1205 | 10386 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
10387 | return; |
10388 | ||
c19d1205 ZW |
10389 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
10390 | p = fragP->fr_literal + fragP->fr_fix; | |
10391 | fix = 0; | |
bfae80f2 | 10392 | |
c19d1205 ZW |
10393 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
10394 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 10395 | |
c19d1205 | 10396 | if (fragP->tc_frag_data) |
a737bd4d | 10397 | { |
c19d1205 ZW |
10398 | if (target_big_endian) |
10399 | noop = thumb_bigend_noop; | |
10400 | else | |
10401 | noop = thumb_noop; | |
10402 | noop_size = sizeof (thumb_noop); | |
7ed4c4c5 NC |
10403 | } |
10404 | else | |
10405 | { | |
c19d1205 ZW |
10406 | if (target_big_endian) |
10407 | noop = arm_bigend_noop; | |
10408 | else | |
10409 | noop = arm_noop; | |
10410 | noop_size = sizeof (arm_noop); | |
7ed4c4c5 | 10411 | } |
a737bd4d | 10412 | |
c19d1205 | 10413 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 10414 | { |
c19d1205 ZW |
10415 | fix = bytes & (noop_size - 1); |
10416 | memset (p, 0, fix); | |
10417 | p += fix; | |
10418 | bytes -= fix; | |
a737bd4d | 10419 | } |
a737bd4d | 10420 | |
c19d1205 | 10421 | while (bytes >= noop_size) |
a737bd4d | 10422 | { |
c19d1205 ZW |
10423 | memcpy (p, noop, noop_size); |
10424 | p += noop_size; | |
10425 | bytes -= noop_size; | |
10426 | fix += noop_size; | |
a737bd4d NC |
10427 | } |
10428 | ||
c19d1205 ZW |
10429 | fragP->fr_fix += fix; |
10430 | fragP->fr_var = noop_size; | |
a737bd4d NC |
10431 | } |
10432 | ||
c19d1205 ZW |
10433 | /* Called from md_do_align. Used to create an alignment |
10434 | frag in a code section. */ | |
10435 | ||
10436 | void | |
10437 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 10438 | { |
c19d1205 | 10439 | char * p; |
7ed4c4c5 | 10440 | |
c19d1205 ZW |
10441 | /* We assume that there will never be a requirement |
10442 | to support alignments greater than 32 bytes. */ | |
10443 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) | |
10444 | as_fatal (_("alignments greater than 32 bytes not supported in .text sections.")); | |
bfae80f2 | 10445 | |
c19d1205 ZW |
10446 | p = frag_var (rs_align_code, |
10447 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
10448 | 1, | |
10449 | (relax_substateT) max, | |
10450 | (symbolS *) NULL, | |
10451 | (offsetT) n, | |
10452 | (char *) NULL); | |
10453 | *p = 0; | |
10454 | } | |
bfae80f2 | 10455 | |
c19d1205 | 10456 | /* Perform target specific initialisation of a frag. */ |
bfae80f2 | 10457 | |
c19d1205 ZW |
10458 | void |
10459 | arm_init_frag (fragS * fragP) | |
10460 | { | |
10461 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
10462 | fragP->tc_frag_data = thumb_mode; | |
bfae80f2 RE |
10463 | } |
10464 | ||
c19d1205 ZW |
10465 | #ifdef OBJ_ELF |
10466 | /* When we change sections we need to issue a new mapping symbol. */ | |
10467 | ||
10468 | void | |
10469 | arm_elf_change_section (void) | |
bfae80f2 | 10470 | { |
c19d1205 ZW |
10471 | flagword flags; |
10472 | segment_info_type *seginfo; | |
bfae80f2 | 10473 | |
c19d1205 ZW |
10474 | /* Link an unlinked unwind index table section to the .text section. */ |
10475 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
10476 | && elf_linked_to_section (now_seg) == NULL) | |
10477 | elf_linked_to_section (now_seg) = text_section; | |
10478 | ||
10479 | if (!SEG_NORMAL (now_seg)) | |
bfae80f2 RE |
10480 | return; |
10481 | ||
c19d1205 ZW |
10482 | flags = bfd_get_section_flags (stdoutput, now_seg); |
10483 | ||
10484 | /* We can ignore sections that only contain debug info. */ | |
10485 | if ((flags & SEC_ALLOC) == 0) | |
10486 | return; | |
bfae80f2 | 10487 | |
c19d1205 ZW |
10488 | seginfo = seg_info (now_seg); |
10489 | mapstate = seginfo->tc_segment_info_data.mapstate; | |
10490 | marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency; | |
bfae80f2 RE |
10491 | } |
10492 | ||
c19d1205 ZW |
10493 | int |
10494 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 10495 | { |
c19d1205 ZW |
10496 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
10497 | return SHT_ARM_EXIDX; | |
e45d0630 | 10498 | |
c19d1205 ZW |
10499 | return -1; |
10500 | } | |
10501 | \f | |
10502 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 10503 | |
c19d1205 | 10504 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 10505 | |
c19d1205 | 10506 | /* Cenerate and deferred unwind frame offset. */ |
e45d0630 | 10507 | |
bfae80f2 | 10508 | static void |
c19d1205 | 10509 | flush_pending_unwind (void) |
bfae80f2 | 10510 | { |
c19d1205 | 10511 | offsetT offset; |
bfae80f2 | 10512 | |
c19d1205 ZW |
10513 | offset = unwind.pending_offset; |
10514 | unwind.pending_offset = 0; | |
10515 | if (offset != 0) | |
10516 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
10517 | } |
10518 | ||
c19d1205 ZW |
10519 | /* Add an opcode to this list for this function. Two-byte opcodes should |
10520 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
10521 | order. */ | |
10522 | ||
bfae80f2 | 10523 | static void |
c19d1205 | 10524 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 10525 | { |
c19d1205 ZW |
10526 | /* Add any deferred stack adjustment. */ |
10527 | if (unwind.pending_offset) | |
10528 | flush_pending_unwind (); | |
bfae80f2 | 10529 | |
c19d1205 | 10530 | unwind.sp_restored = 0; |
bfae80f2 | 10531 | |
c19d1205 | 10532 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 10533 | { |
c19d1205 ZW |
10534 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
10535 | if (unwind.opcodes) | |
10536 | unwind.opcodes = xrealloc (unwind.opcodes, | |
10537 | unwind.opcode_alloc); | |
10538 | else | |
10539 | unwind.opcodes = xmalloc (unwind.opcode_alloc); | |
bfae80f2 | 10540 | } |
c19d1205 | 10541 | while (length > 0) |
bfae80f2 | 10542 | { |
c19d1205 ZW |
10543 | length--; |
10544 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
10545 | op >>= 8; | |
10546 | unwind.opcode_count++; | |
bfae80f2 | 10547 | } |
bfae80f2 RE |
10548 | } |
10549 | ||
c19d1205 ZW |
10550 | /* Add unwind opcodes to adjust the stack pointer. */ |
10551 | ||
bfae80f2 | 10552 | static void |
c19d1205 | 10553 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 10554 | { |
c19d1205 | 10555 | valueT op; |
bfae80f2 | 10556 | |
c19d1205 | 10557 | if (offset > 0x200) |
bfae80f2 | 10558 | { |
c19d1205 ZW |
10559 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
10560 | char bytes[5]; | |
10561 | int n; | |
10562 | valueT o; | |
bfae80f2 | 10563 | |
c19d1205 ZW |
10564 | /* Long form: 0xb2, uleb128. */ |
10565 | /* This might not fit in a word so add the individual bytes, | |
10566 | remembering the list is built in reverse order. */ | |
10567 | o = (valueT) ((offset - 0x204) >> 2); | |
10568 | if (o == 0) | |
10569 | add_unwind_opcode (0, 1); | |
bfae80f2 | 10570 | |
c19d1205 ZW |
10571 | /* Calculate the uleb128 encoding of the offset. */ |
10572 | n = 0; | |
10573 | while (o) | |
10574 | { | |
10575 | bytes[n] = o & 0x7f; | |
10576 | o >>= 7; | |
10577 | if (o) | |
10578 | bytes[n] |= 0x80; | |
10579 | n++; | |
10580 | } | |
10581 | /* Add the insn. */ | |
10582 | for (; n; n--) | |
10583 | add_unwind_opcode (bytes[n - 1], 1); | |
10584 | add_unwind_opcode (0xb2, 1); | |
10585 | } | |
10586 | else if (offset > 0x100) | |
bfae80f2 | 10587 | { |
c19d1205 ZW |
10588 | /* Two short opcodes. */ |
10589 | add_unwind_opcode (0x3f, 1); | |
10590 | op = (offset - 0x104) >> 2; | |
10591 | add_unwind_opcode (op, 1); | |
bfae80f2 | 10592 | } |
c19d1205 ZW |
10593 | else if (offset > 0) |
10594 | { | |
10595 | /* Short opcode. */ | |
10596 | op = (offset - 4) >> 2; | |
10597 | add_unwind_opcode (op, 1); | |
10598 | } | |
10599 | else if (offset < 0) | |
bfae80f2 | 10600 | { |
c19d1205 ZW |
10601 | offset = -offset; |
10602 | while (offset > 0x100) | |
bfae80f2 | 10603 | { |
c19d1205 ZW |
10604 | add_unwind_opcode (0x7f, 1); |
10605 | offset -= 0x100; | |
bfae80f2 | 10606 | } |
c19d1205 ZW |
10607 | op = ((offset - 4) >> 2) | 0x40; |
10608 | add_unwind_opcode (op, 1); | |
bfae80f2 | 10609 | } |
bfae80f2 RE |
10610 | } |
10611 | ||
c19d1205 ZW |
10612 | /* Finish the list of unwind opcodes for this function. */ |
10613 | static void | |
10614 | finish_unwind_opcodes (void) | |
bfae80f2 | 10615 | { |
c19d1205 | 10616 | valueT op; |
bfae80f2 | 10617 | |
c19d1205 | 10618 | if (unwind.fp_used) |
bfae80f2 | 10619 | { |
c19d1205 ZW |
10620 | /* Adjust sp as neccessary. */ |
10621 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; | |
10622 | flush_pending_unwind (); | |
bfae80f2 | 10623 | |
c19d1205 ZW |
10624 | /* After restoring sp from the frame pointer. */ |
10625 | op = 0x90 | unwind.fp_reg; | |
10626 | add_unwind_opcode (op, 1); | |
10627 | } | |
10628 | else | |
10629 | flush_pending_unwind (); | |
bfae80f2 RE |
10630 | } |
10631 | ||
bfae80f2 | 10632 | |
c19d1205 ZW |
10633 | /* Start an exception table entry. If idx is nonzero this is an index table |
10634 | entry. */ | |
bfae80f2 RE |
10635 | |
10636 | static void | |
c19d1205 | 10637 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 10638 | { |
c19d1205 ZW |
10639 | const char * text_name; |
10640 | const char * prefix; | |
10641 | const char * prefix_once; | |
10642 | const char * group_name; | |
10643 | size_t prefix_len; | |
10644 | size_t text_len; | |
10645 | char * sec_name; | |
10646 | size_t sec_name_len; | |
10647 | int type; | |
10648 | int flags; | |
10649 | int linkonce; | |
bfae80f2 | 10650 | |
c19d1205 | 10651 | if (idx) |
bfae80f2 | 10652 | { |
c19d1205 ZW |
10653 | prefix = ELF_STRING_ARM_unwind; |
10654 | prefix_once = ELF_STRING_ARM_unwind_once; | |
10655 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 10656 | } |
c19d1205 | 10657 | else |
bfae80f2 | 10658 | { |
c19d1205 ZW |
10659 | prefix = ELF_STRING_ARM_unwind_info; |
10660 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
10661 | type = SHT_PROGBITS; | |
bfae80f2 RE |
10662 | } |
10663 | ||
c19d1205 ZW |
10664 | text_name = segment_name (text_seg); |
10665 | if (streq (text_name, ".text")) | |
10666 | text_name = ""; | |
10667 | ||
10668 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
10669 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 10670 | { |
c19d1205 ZW |
10671 | prefix = prefix_once; |
10672 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
10673 | } |
10674 | ||
c19d1205 ZW |
10675 | prefix_len = strlen (prefix); |
10676 | text_len = strlen (text_name); | |
10677 | sec_name_len = prefix_len + text_len; | |
10678 | sec_name = xmalloc (sec_name_len + 1); | |
10679 | memcpy (sec_name, prefix, prefix_len); | |
10680 | memcpy (sec_name + prefix_len, text_name, text_len); | |
10681 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 10682 | |
c19d1205 ZW |
10683 | flags = SHF_ALLOC; |
10684 | linkonce = 0; | |
10685 | group_name = 0; | |
bfae80f2 | 10686 | |
c19d1205 ZW |
10687 | /* Handle COMDAT group. */ |
10688 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 10689 | { |
c19d1205 ZW |
10690 | group_name = elf_group_name (text_seg); |
10691 | if (group_name == NULL) | |
10692 | { | |
10693 | as_bad ("Group section `%s' has no group signature", | |
10694 | segment_name (text_seg)); | |
10695 | ignore_rest_of_line (); | |
10696 | return; | |
10697 | } | |
10698 | flags |= SHF_GROUP; | |
10699 | linkonce = 1; | |
bfae80f2 RE |
10700 | } |
10701 | ||
c19d1205 | 10702 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 10703 | |
c19d1205 ZW |
10704 | /* Set the setion link for index tables. */ |
10705 | if (idx) | |
10706 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
10707 | } |
10708 | ||
bfae80f2 | 10709 | |
c19d1205 ZW |
10710 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
10711 | personality routine data. Returns zero, or the index table value for | |
10712 | and inline entry. */ | |
10713 | ||
10714 | static valueT | |
10715 | create_unwind_entry (int have_data) | |
bfae80f2 | 10716 | { |
c19d1205 ZW |
10717 | int size; |
10718 | addressT where; | |
10719 | char *ptr; | |
10720 | /* The current word of data. */ | |
10721 | valueT data; | |
10722 | /* The number of bytes left in this word. */ | |
10723 | int n; | |
bfae80f2 | 10724 | |
c19d1205 | 10725 | finish_unwind_opcodes (); |
bfae80f2 | 10726 | |
c19d1205 ZW |
10727 | /* Remember the current text section. */ |
10728 | unwind.saved_seg = now_seg; | |
10729 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 10730 | |
c19d1205 | 10731 | start_unwind_section (now_seg, 0); |
bfae80f2 | 10732 | |
c19d1205 | 10733 | if (unwind.personality_routine == NULL) |
bfae80f2 | 10734 | { |
c19d1205 ZW |
10735 | if (unwind.personality_index == -2) |
10736 | { | |
10737 | if (have_data) | |
10738 | as_bad (_("handerdata in cantunwind frame")); | |
10739 | return 1; /* EXIDX_CANTUNWIND. */ | |
10740 | } | |
bfae80f2 | 10741 | |
c19d1205 ZW |
10742 | /* Use a default personality routine if none is specified. */ |
10743 | if (unwind.personality_index == -1) | |
10744 | { | |
10745 | if (unwind.opcode_count > 3) | |
10746 | unwind.personality_index = 1; | |
10747 | else | |
10748 | unwind.personality_index = 0; | |
10749 | } | |
bfae80f2 | 10750 | |
c19d1205 ZW |
10751 | /* Space for the personality routine entry. */ |
10752 | if (unwind.personality_index == 0) | |
10753 | { | |
10754 | if (unwind.opcode_count > 3) | |
10755 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 10756 | |
c19d1205 ZW |
10757 | if (!have_data) |
10758 | { | |
10759 | /* All the data is inline in the index table. */ | |
10760 | data = 0x80; | |
10761 | n = 3; | |
10762 | while (unwind.opcode_count > 0) | |
10763 | { | |
10764 | unwind.opcode_count--; | |
10765 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
10766 | n--; | |
10767 | } | |
bfae80f2 | 10768 | |
c19d1205 ZW |
10769 | /* Pad with "finish" opcodes. */ |
10770 | while (n--) | |
10771 | data = (data << 8) | 0xb0; | |
bfae80f2 | 10772 | |
c19d1205 ZW |
10773 | return data; |
10774 | } | |
10775 | size = 0; | |
10776 | } | |
10777 | else | |
10778 | /* We get two opcodes "free" in the first word. */ | |
10779 | size = unwind.opcode_count - 2; | |
10780 | } | |
10781 | else | |
10782 | /* An extra byte is required for the opcode count. */ | |
10783 | size = unwind.opcode_count + 1; | |
bfae80f2 | 10784 | |
c19d1205 ZW |
10785 | size = (size + 3) >> 2; |
10786 | if (size > 0xff) | |
10787 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 10788 | |
c19d1205 ZW |
10789 | frag_align (2, 0, 0); |
10790 | record_alignment (now_seg, 2); | |
10791 | unwind.table_entry = expr_build_dot (); | |
10792 | ||
10793 | /* Allocate the table entry. */ | |
10794 | ptr = frag_more ((size << 2) + 4); | |
10795 | where = frag_now_fix () - ((size << 2) + 4); | |
bfae80f2 | 10796 | |
c19d1205 | 10797 | switch (unwind.personality_index) |
bfae80f2 | 10798 | { |
c19d1205 ZW |
10799 | case -1: |
10800 | /* ??? Should this be a PLT generating relocation? */ | |
10801 | /* Custom personality routine. */ | |
10802 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
10803 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 10804 | |
c19d1205 ZW |
10805 | where += 4; |
10806 | ptr += 4; | |
bfae80f2 | 10807 | |
c19d1205 ZW |
10808 | /* Set the first byte to the number of additional words. */ |
10809 | data = size - 1; | |
10810 | n = 3; | |
10811 | break; | |
bfae80f2 | 10812 | |
c19d1205 ZW |
10813 | /* ABI defined personality routines. */ |
10814 | case 0: | |
10815 | /* Three opcodes bytes are packed into the first word. */ | |
10816 | data = 0x80; | |
10817 | n = 3; | |
10818 | break; | |
bfae80f2 | 10819 | |
c19d1205 ZW |
10820 | case 1: |
10821 | case 2: | |
10822 | /* The size and first two opcode bytes go in the first word. */ | |
10823 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
10824 | n = 2; | |
10825 | break; | |
bfae80f2 | 10826 | |
c19d1205 ZW |
10827 | default: |
10828 | /* Should never happen. */ | |
10829 | abort (); | |
10830 | } | |
bfae80f2 | 10831 | |
c19d1205 ZW |
10832 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
10833 | time. */ | |
10834 | while (unwind.opcode_count > 0) | |
10835 | { | |
10836 | if (n == 0) | |
10837 | { | |
10838 | md_number_to_chars (ptr, data, 4); | |
10839 | ptr += 4; | |
10840 | n = 4; | |
10841 | data = 0; | |
10842 | } | |
10843 | unwind.opcode_count--; | |
10844 | n--; | |
10845 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
10846 | } | |
10847 | ||
10848 | /* Finish off the last word. */ | |
10849 | if (n < 4) | |
10850 | { | |
10851 | /* Pad with "finish" opcodes. */ | |
10852 | while (n--) | |
10853 | data = (data << 8) | 0xb0; | |
10854 | ||
10855 | md_number_to_chars (ptr, data, 4); | |
10856 | } | |
10857 | ||
10858 | if (!have_data) | |
10859 | { | |
10860 | /* Add an empty descriptor if there is no user-specified data. */ | |
10861 | ptr = frag_more (4); | |
10862 | md_number_to_chars (ptr, 0, 4); | |
10863 | } | |
10864 | ||
10865 | return 0; | |
bfae80f2 RE |
10866 | } |
10867 | ||
c19d1205 ZW |
10868 | /* Convert REGNAME to a DWARF-2 register number. */ |
10869 | ||
10870 | int | |
10871 | tc_arm_regname_to_dw2regnum (const char *regname) | |
bfae80f2 | 10872 | { |
c19d1205 ZW |
10873 | int reg = arm_reg_parse ((char **) ®name, REG_TYPE_RN); |
10874 | ||
10875 | if (reg == FAIL) | |
10876 | return -1; | |
10877 | ||
10878 | return reg; | |
bfae80f2 RE |
10879 | } |
10880 | ||
c19d1205 ZW |
10881 | /* Initialize the DWARF-2 unwind information for this procedure. */ |
10882 | ||
10883 | void | |
10884 | tc_arm_frame_initial_instructions (void) | |
bfae80f2 | 10885 | { |
c19d1205 | 10886 | cfi_add_CFA_def_cfa (REG_SP, 0); |
bfae80f2 | 10887 | } |
c19d1205 | 10888 | #endif /* OBJ_ELF */ |
bfae80f2 | 10889 | |
bfae80f2 | 10890 | |
c19d1205 | 10891 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 10892 | |
2fc8bdac ZW |
10893 | /* Return the address within the segment that a PC-relative fixup is |
10894 | relative to. For ARM, PC-relative fixups applied to instructions | |
10895 | are generally relative to the location of the fixup plus 8 bytes. | |
10896 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
10897 | require special handling. */ | |
bfae80f2 | 10898 | |
c19d1205 | 10899 | long |
2fc8bdac | 10900 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 10901 | { |
2fc8bdac ZW |
10902 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
10903 | ||
10904 | /* If this is pc-relative and we are going to emit a relocation | |
10905 | then we just want to put out any pipeline compensation that the linker | |
10906 | will need. Otherwise we want to use the calculated base. */ | |
10907 | if (fixP->fx_pcrel | |
10908 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
10909 | || arm_force_relocation (fixP))) | |
10910 | base = 0; | |
bfae80f2 | 10911 | |
c19d1205 | 10912 | switch (fixP->fx_r_type) |
bfae80f2 | 10913 | { |
2fc8bdac ZW |
10914 | /* PC relative addressing on the Thumb is slightly odd as the |
10915 | bottom two bits of the PC are forced to zero for the | |
10916 | calculation. This happens *after* application of the | |
10917 | pipeline offset. However, Thumb adrl already adjusts for | |
10918 | this, so we need not do it again. */ | |
c19d1205 | 10919 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 10920 | return base & ~3; |
c19d1205 ZW |
10921 | |
10922 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
10923 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 10924 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 10925 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 10926 | return (base + 4) & ~3; |
c19d1205 | 10927 | |
2fc8bdac ZW |
10928 | /* Thumb branches are simply offset by +4. */ |
10929 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
10930 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
10931 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
10932 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
10933 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
10934 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
10935 | case BFD_RELOC_THUMB_PCREL_BLX: | |
10936 | return base + 4; | |
bfae80f2 | 10937 | |
2fc8bdac ZW |
10938 | /* ARM mode branches are offset by +8. However, the Windows CE |
10939 | loader expects the relocation not to take this into account. */ | |
10940 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
39b41c9c PB |
10941 | case BFD_RELOC_ARM_PCREL_CALL: |
10942 | case BFD_RELOC_ARM_PCREL_JUMP: | |
2fc8bdac ZW |
10943 | case BFD_RELOC_ARM_PCREL_BLX: |
10944 | case BFD_RELOC_ARM_PLT32: | |
c19d1205 | 10945 | #ifdef TE_WINCE |
2fc8bdac | 10946 | return base; |
c19d1205 | 10947 | #else |
2fc8bdac | 10948 | return base + 8; |
c19d1205 | 10949 | #endif |
2fc8bdac ZW |
10950 | |
10951 | /* ARM mode loads relative to PC are also offset by +8. Unlike | |
10952 | branches, the Windows CE loader *does* expect the relocation | |
10953 | to take this into account. */ | |
10954 | case BFD_RELOC_ARM_OFFSET_IMM: | |
10955 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
10956 | case BFD_RELOC_ARM_HWLITERAL: | |
10957 | case BFD_RELOC_ARM_LITERAL: | |
10958 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
10959 | return base + 8; | |
10960 | ||
10961 | ||
10962 | /* Other PC-relative relocations are un-offset. */ | |
10963 | default: | |
10964 | return base; | |
10965 | } | |
bfae80f2 RE |
10966 | } |
10967 | ||
c19d1205 ZW |
10968 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. |
10969 | Otherwise we have no need to default values of symbols. */ | |
10970 | ||
10971 | symbolS * | |
10972 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
bfae80f2 | 10973 | { |
c19d1205 ZW |
10974 | #ifdef OBJ_ELF |
10975 | if (name[0] == '_' && name[1] == 'G' | |
10976 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
10977 | { | |
10978 | if (!GOT_symbol) | |
10979 | { | |
10980 | if (symbol_find (name)) | |
10981 | as_bad ("GOT already in the symbol table"); | |
bfae80f2 | 10982 | |
c19d1205 ZW |
10983 | GOT_symbol = symbol_new (name, undefined_section, |
10984 | (valueT) 0, & zero_address_frag); | |
10985 | } | |
bfae80f2 | 10986 | |
c19d1205 | 10987 | return GOT_symbol; |
bfae80f2 | 10988 | } |
c19d1205 | 10989 | #endif |
bfae80f2 | 10990 | |
c19d1205 | 10991 | return 0; |
bfae80f2 RE |
10992 | } |
10993 | ||
55cf6793 | 10994 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
10995 | computed as two separate immediate values, added together. We |
10996 | already know that this value cannot be computed by just one ARM | |
10997 | instruction. */ | |
10998 | ||
10999 | static unsigned int | |
11000 | validate_immediate_twopart (unsigned int val, | |
11001 | unsigned int * highpart) | |
bfae80f2 | 11002 | { |
c19d1205 ZW |
11003 | unsigned int a; |
11004 | unsigned int i; | |
bfae80f2 | 11005 | |
c19d1205 ZW |
11006 | for (i = 0; i < 32; i += 2) |
11007 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
11008 | { | |
11009 | if (a & 0xff00) | |
11010 | { | |
11011 | if (a & ~ 0xffff) | |
11012 | continue; | |
11013 | * highpart = (a >> 8) | ((i + 24) << 7); | |
11014 | } | |
11015 | else if (a & 0xff0000) | |
11016 | { | |
11017 | if (a & 0xff000000) | |
11018 | continue; | |
11019 | * highpart = (a >> 16) | ((i + 16) << 7); | |
11020 | } | |
11021 | else | |
11022 | { | |
11023 | assert (a & 0xff000000); | |
11024 | * highpart = (a >> 24) | ((i + 8) << 7); | |
11025 | } | |
bfae80f2 | 11026 | |
c19d1205 ZW |
11027 | return (a & 0xff) | (i << 7); |
11028 | } | |
bfae80f2 | 11029 | |
c19d1205 | 11030 | return FAIL; |
bfae80f2 RE |
11031 | } |
11032 | ||
c19d1205 ZW |
11033 | static int |
11034 | validate_offset_imm (unsigned int val, int hwse) | |
11035 | { | |
11036 | if ((hwse && val > 255) || val > 4095) | |
11037 | return FAIL; | |
11038 | return val; | |
11039 | } | |
bfae80f2 | 11040 | |
55cf6793 | 11041 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
11042 | negative immediate constant by altering the instruction. A bit of |
11043 | a hack really. | |
11044 | MOV <-> MVN | |
11045 | AND <-> BIC | |
11046 | ADC <-> SBC | |
11047 | by inverting the second operand, and | |
11048 | ADD <-> SUB | |
11049 | CMP <-> CMN | |
11050 | by negating the second operand. */ | |
bfae80f2 | 11051 | |
c19d1205 ZW |
11052 | static int |
11053 | negate_data_op (unsigned long * instruction, | |
11054 | unsigned long value) | |
bfae80f2 | 11055 | { |
c19d1205 ZW |
11056 | int op, new_inst; |
11057 | unsigned long negated, inverted; | |
bfae80f2 | 11058 | |
c19d1205 ZW |
11059 | negated = encode_arm_immediate (-value); |
11060 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 11061 | |
c19d1205 ZW |
11062 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
11063 | switch (op) | |
bfae80f2 | 11064 | { |
c19d1205 ZW |
11065 | /* First negates. */ |
11066 | case OPCODE_SUB: /* ADD <-> SUB */ | |
11067 | new_inst = OPCODE_ADD; | |
11068 | value = negated; | |
11069 | break; | |
bfae80f2 | 11070 | |
c19d1205 ZW |
11071 | case OPCODE_ADD: |
11072 | new_inst = OPCODE_SUB; | |
11073 | value = negated; | |
11074 | break; | |
bfae80f2 | 11075 | |
c19d1205 ZW |
11076 | case OPCODE_CMP: /* CMP <-> CMN */ |
11077 | new_inst = OPCODE_CMN; | |
11078 | value = negated; | |
11079 | break; | |
bfae80f2 | 11080 | |
c19d1205 ZW |
11081 | case OPCODE_CMN: |
11082 | new_inst = OPCODE_CMP; | |
11083 | value = negated; | |
11084 | break; | |
bfae80f2 | 11085 | |
c19d1205 ZW |
11086 | /* Now Inverted ops. */ |
11087 | case OPCODE_MOV: /* MOV <-> MVN */ | |
11088 | new_inst = OPCODE_MVN; | |
11089 | value = inverted; | |
11090 | break; | |
bfae80f2 | 11091 | |
c19d1205 ZW |
11092 | case OPCODE_MVN: |
11093 | new_inst = OPCODE_MOV; | |
11094 | value = inverted; | |
11095 | break; | |
bfae80f2 | 11096 | |
c19d1205 ZW |
11097 | case OPCODE_AND: /* AND <-> BIC */ |
11098 | new_inst = OPCODE_BIC; | |
11099 | value = inverted; | |
11100 | break; | |
bfae80f2 | 11101 | |
c19d1205 ZW |
11102 | case OPCODE_BIC: |
11103 | new_inst = OPCODE_AND; | |
11104 | value = inverted; | |
11105 | break; | |
bfae80f2 | 11106 | |
c19d1205 ZW |
11107 | case OPCODE_ADC: /* ADC <-> SBC */ |
11108 | new_inst = OPCODE_SBC; | |
11109 | value = inverted; | |
11110 | break; | |
bfae80f2 | 11111 | |
c19d1205 ZW |
11112 | case OPCODE_SBC: |
11113 | new_inst = OPCODE_ADC; | |
11114 | value = inverted; | |
11115 | break; | |
bfae80f2 | 11116 | |
c19d1205 ZW |
11117 | /* We cannot do anything. */ |
11118 | default: | |
11119 | return FAIL; | |
b99bd4ef NC |
11120 | } |
11121 | ||
c19d1205 ZW |
11122 | if (value == (unsigned) FAIL) |
11123 | return FAIL; | |
11124 | ||
11125 | *instruction &= OPCODE_MASK; | |
11126 | *instruction |= new_inst << DATA_OP_SHIFT; | |
11127 | return value; | |
b99bd4ef NC |
11128 | } |
11129 | ||
ef8d22e6 PB |
11130 | /* Like negate_data_op, but for Thumb-2. */ |
11131 | ||
11132 | static unsigned int | |
11133 | thumb32_negate_data_op (offsetT *instruction, offsetT value) | |
11134 | { | |
11135 | int op, new_inst; | |
11136 | int rd; | |
11137 | offsetT negated, inverted; | |
11138 | ||
11139 | negated = encode_thumb32_immediate (-value); | |
11140 | inverted = encode_thumb32_immediate (~value); | |
11141 | ||
11142 | rd = (*instruction >> 8) & 0xf; | |
11143 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
11144 | switch (op) | |
11145 | { | |
11146 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
11147 | case T2_OPCODE_SUB: | |
11148 | new_inst = T2_OPCODE_ADD; | |
11149 | value = negated; | |
11150 | break; | |
11151 | ||
11152 | case T2_OPCODE_ADD: | |
11153 | new_inst = T2_OPCODE_SUB; | |
11154 | value = negated; | |
11155 | break; | |
11156 | ||
11157 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
11158 | case T2_OPCODE_ORR: | |
11159 | new_inst = T2_OPCODE_ORN; | |
11160 | value = inverted; | |
11161 | break; | |
11162 | ||
11163 | case T2_OPCODE_ORN: | |
11164 | new_inst = T2_OPCODE_ORR; | |
11165 | value = inverted; | |
11166 | break; | |
11167 | ||
11168 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
11169 | case T2_OPCODE_AND: | |
11170 | new_inst = T2_OPCODE_BIC; | |
11171 | if (rd == 15) | |
11172 | value = FAIL; | |
11173 | else | |
11174 | value = inverted; | |
11175 | break; | |
11176 | ||
11177 | case T2_OPCODE_BIC: | |
11178 | new_inst = T2_OPCODE_AND; | |
11179 | value = inverted; | |
11180 | break; | |
11181 | ||
11182 | /* ADC <-> SBC */ | |
11183 | case T2_OPCODE_ADC: | |
11184 | new_inst = T2_OPCODE_SBC; | |
11185 | value = inverted; | |
11186 | break; | |
11187 | ||
11188 | case T2_OPCODE_SBC: | |
11189 | new_inst = T2_OPCODE_ADC; | |
11190 | value = inverted; | |
11191 | break; | |
11192 | ||
11193 | /* We cannot do anything. */ | |
11194 | default: | |
11195 | return FAIL; | |
11196 | } | |
11197 | ||
11198 | if (value == FAIL) | |
11199 | return FAIL; | |
11200 | ||
11201 | *instruction &= T2_OPCODE_MASK; | |
11202 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
11203 | return value; | |
11204 | } | |
11205 | ||
8f06b2d8 PB |
11206 | /* Read a 32-bit thumb instruction from buf. */ |
11207 | static unsigned long | |
11208 | get_thumb32_insn (char * buf) | |
11209 | { | |
11210 | unsigned long insn; | |
11211 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
11212 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
11213 | ||
11214 | return insn; | |
11215 | } | |
11216 | ||
c19d1205 | 11217 | void |
55cf6793 | 11218 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
11219 | valueT * valP, |
11220 | segT seg) | |
11221 | { | |
11222 | offsetT value = * valP; | |
11223 | offsetT newval; | |
11224 | unsigned int newimm; | |
11225 | unsigned long temp; | |
11226 | int sign; | |
11227 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 11228 | |
c19d1205 | 11229 | assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 11230 | |
c19d1205 ZW |
11231 | /* Note whether this will delete the relocation. */ |
11232 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
11233 | fixP->fx_done = 1; | |
b99bd4ef | 11234 | |
adbaf948 ZW |
11235 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
11236 | consistency with the behavior on 32-bit hosts. Remember value | |
11237 | for emit_reloc. */ | |
11238 | value &= 0xffffffff; | |
11239 | value ^= 0x80000000; | |
11240 | value -= 0x80000000; | |
11241 | ||
11242 | *valP = value; | |
c19d1205 | 11243 | fixP->fx_addnumber = value; |
b99bd4ef | 11244 | |
adbaf948 ZW |
11245 | /* Same treatment for fixP->fx_offset. */ |
11246 | fixP->fx_offset &= 0xffffffff; | |
11247 | fixP->fx_offset ^= 0x80000000; | |
11248 | fixP->fx_offset -= 0x80000000; | |
11249 | ||
c19d1205 | 11250 | switch (fixP->fx_r_type) |
b99bd4ef | 11251 | { |
c19d1205 ZW |
11252 | case BFD_RELOC_NONE: |
11253 | /* This will need to go in the object file. */ | |
11254 | fixP->fx_done = 0; | |
11255 | break; | |
b99bd4ef | 11256 | |
c19d1205 ZW |
11257 | case BFD_RELOC_ARM_IMMEDIATE: |
11258 | /* We claim that this fixup has been processed here, | |
11259 | even if in fact we generate an error because we do | |
11260 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
11261 | fixP->fx_done = 1; | |
b99bd4ef | 11262 | |
c19d1205 ZW |
11263 | if (fixP->fx_addsy |
11264 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
b99bd4ef | 11265 | { |
c19d1205 ZW |
11266 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11267 | _("undefined symbol %s used as an immediate value"), | |
11268 | S_GET_NAME (fixP->fx_addsy)); | |
11269 | break; | |
b99bd4ef NC |
11270 | } |
11271 | ||
c19d1205 ZW |
11272 | newimm = encode_arm_immediate (value); |
11273 | temp = md_chars_to_number (buf, INSN_SIZE); | |
11274 | ||
11275 | /* If the instruction will fail, see if we can fix things up by | |
11276 | changing the opcode. */ | |
11277 | if (newimm == (unsigned int) FAIL | |
11278 | && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) | |
b99bd4ef | 11279 | { |
c19d1205 ZW |
11280 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11281 | _("invalid constant (%lx) after fixup"), | |
11282 | (unsigned long) value); | |
11283 | break; | |
b99bd4ef | 11284 | } |
b99bd4ef | 11285 | |
c19d1205 ZW |
11286 | newimm |= (temp & 0xfffff000); |
11287 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
11288 | break; | |
b99bd4ef | 11289 | |
c19d1205 ZW |
11290 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
11291 | { | |
11292 | unsigned int highpart = 0; | |
11293 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 11294 | |
c19d1205 ZW |
11295 | newimm = encode_arm_immediate (value); |
11296 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 11297 | |
c19d1205 ZW |
11298 | /* If the instruction will fail, see if we can fix things up by |
11299 | changing the opcode. */ | |
11300 | if (newimm == (unsigned int) FAIL | |
11301 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
11302 | { | |
11303 | /* No ? OK - try using two ADD instructions to generate | |
11304 | the value. */ | |
11305 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 11306 | |
c19d1205 ZW |
11307 | /* Yes - then make sure that the second instruction is |
11308 | also an add. */ | |
11309 | if (newimm != (unsigned int) FAIL) | |
11310 | newinsn = temp; | |
11311 | /* Still No ? Try using a negated value. */ | |
11312 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
11313 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
11314 | /* Otherwise - give up. */ | |
11315 | else | |
11316 | { | |
11317 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11318 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
11319 | (long) value); | |
11320 | break; | |
11321 | } | |
b99bd4ef | 11322 | |
c19d1205 ZW |
11323 | /* Replace the first operand in the 2nd instruction (which |
11324 | is the PC) with the destination register. We have | |
11325 | already added in the PC in the first instruction and we | |
11326 | do not want to do it again. */ | |
11327 | newinsn &= ~ 0xf0000; | |
11328 | newinsn |= ((newinsn & 0x0f000) << 4); | |
11329 | } | |
b99bd4ef | 11330 | |
c19d1205 ZW |
11331 | newimm |= (temp & 0xfffff000); |
11332 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 11333 | |
c19d1205 ZW |
11334 | highpart |= (newinsn & 0xfffff000); |
11335 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
11336 | } | |
11337 | break; | |
b99bd4ef | 11338 | |
c19d1205 ZW |
11339 | case BFD_RELOC_ARM_OFFSET_IMM: |
11340 | case BFD_RELOC_ARM_LITERAL: | |
11341 | sign = value >= 0; | |
b99bd4ef | 11342 | |
c19d1205 ZW |
11343 | if (value < 0) |
11344 | value = - value; | |
b99bd4ef | 11345 | |
c19d1205 | 11346 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 11347 | { |
c19d1205 ZW |
11348 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
11349 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11350 | _("invalid literal constant: pool needs to be closer")); | |
11351 | else | |
11352 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11353 | _("bad immediate value for offset (%ld)"), | |
11354 | (long) value); | |
11355 | break; | |
f03698e6 RE |
11356 | } |
11357 | ||
c19d1205 ZW |
11358 | newval = md_chars_to_number (buf, INSN_SIZE); |
11359 | newval &= 0xff7ff000; | |
11360 | newval |= value | (sign ? INDEX_UP : 0); | |
11361 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11362 | break; | |
b99bd4ef | 11363 | |
c19d1205 ZW |
11364 | case BFD_RELOC_ARM_OFFSET_IMM8: |
11365 | case BFD_RELOC_ARM_HWLITERAL: | |
11366 | sign = value >= 0; | |
b99bd4ef | 11367 | |
c19d1205 ZW |
11368 | if (value < 0) |
11369 | value = - value; | |
b99bd4ef | 11370 | |
c19d1205 | 11371 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 11372 | { |
c19d1205 ZW |
11373 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
11374 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11375 | _("invalid literal constant: pool needs to be closer")); | |
11376 | else | |
11377 | as_bad (_("bad immediate value for half-word offset (%ld)"), | |
11378 | (long) value); | |
11379 | break; | |
b99bd4ef NC |
11380 | } |
11381 | ||
c19d1205 ZW |
11382 | newval = md_chars_to_number (buf, INSN_SIZE); |
11383 | newval &= 0xff7ff0f0; | |
11384 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
11385 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11386 | break; | |
b99bd4ef | 11387 | |
c19d1205 ZW |
11388 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
11389 | if (value < 0 || value > 1020 || value % 4 != 0) | |
11390 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11391 | _("bad immediate value for offset (%ld)"), (long) value); | |
11392 | value /= 4; | |
b99bd4ef | 11393 | |
c19d1205 | 11394 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
11395 | newval |= value; |
11396 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
11397 | break; | |
b99bd4ef | 11398 | |
c19d1205 ZW |
11399 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
11400 | /* This is a complicated relocation used for all varieties of Thumb32 | |
11401 | load/store instruction with immediate offset: | |
11402 | ||
11403 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
11404 | *4, optional writeback(W) | |
11405 | (doubleword load/store) | |
11406 | ||
11407 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
11408 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
11409 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
11410 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
11411 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
11412 | ||
11413 | Uppercase letters indicate bits that are already encoded at | |
11414 | this point. Lowercase letters are our problem. For the | |
11415 | second block of instructions, the secondary opcode nybble | |
11416 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
11417 | a PC-relative operation. */ | |
11418 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11419 | newval <<= 16; | |
11420 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 11421 | |
c19d1205 | 11422 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 11423 | { |
c19d1205 ZW |
11424 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
11425 | if (value >= 0) | |
11426 | newval |= (1 << 23); | |
11427 | else | |
11428 | value = -value; | |
11429 | if (value % 4 != 0) | |
11430 | { | |
11431 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11432 | _("offset not a multiple of 4")); | |
11433 | break; | |
11434 | } | |
11435 | value /= 4; | |
11436 | if (value >= 0xff) | |
11437 | { | |
11438 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11439 | _("offset out of range")); | |
11440 | break; | |
11441 | } | |
11442 | newval &= ~0xff; | |
b99bd4ef | 11443 | } |
c19d1205 | 11444 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 11445 | { |
c19d1205 ZW |
11446 | /* PC-relative, 12-bit offset. */ |
11447 | if (value >= 0) | |
11448 | newval |= (1 << 23); | |
11449 | else | |
11450 | value = -value; | |
11451 | if (value >= 0xfff) | |
11452 | { | |
11453 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11454 | _("offset out of range")); | |
11455 | break; | |
11456 | } | |
11457 | newval &= ~0xfff; | |
b99bd4ef | 11458 | } |
c19d1205 | 11459 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 11460 | { |
c19d1205 ZW |
11461 | /* Writeback: 8-bit, +/- offset. */ |
11462 | if (value >= 0) | |
11463 | newval |= (1 << 9); | |
11464 | else | |
11465 | value = -value; | |
11466 | if (value >= 0xff) | |
11467 | { | |
11468 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11469 | _("offset out of range")); | |
11470 | break; | |
11471 | } | |
11472 | newval &= ~0xff; | |
b99bd4ef | 11473 | } |
c19d1205 | 11474 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 11475 | { |
c19d1205 ZW |
11476 | /* T-instruction: positive 8-bit offset. */ |
11477 | if (value < 0 || value >= 0xff) | |
b99bd4ef | 11478 | { |
c19d1205 ZW |
11479 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11480 | _("offset out of range")); | |
11481 | break; | |
b99bd4ef | 11482 | } |
c19d1205 ZW |
11483 | newval &= ~0xff; |
11484 | newval |= value; | |
b99bd4ef NC |
11485 | } |
11486 | else | |
b99bd4ef | 11487 | { |
c19d1205 ZW |
11488 | /* Positive 12-bit or negative 8-bit offset. */ |
11489 | int limit; | |
11490 | if (value >= 0) | |
b99bd4ef | 11491 | { |
c19d1205 ZW |
11492 | newval |= (1 << 23); |
11493 | limit = 0xfff; | |
11494 | } | |
11495 | else | |
11496 | { | |
11497 | value = -value; | |
11498 | limit = 0xff; | |
11499 | } | |
11500 | if (value > limit) | |
11501 | { | |
11502 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11503 | _("offset out of range")); | |
11504 | break; | |
b99bd4ef | 11505 | } |
c19d1205 | 11506 | newval &= ~limit; |
b99bd4ef | 11507 | } |
b99bd4ef | 11508 | |
c19d1205 ZW |
11509 | newval |= value; |
11510 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
11511 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
11512 | break; | |
404ff6b5 | 11513 | |
c19d1205 ZW |
11514 | case BFD_RELOC_ARM_SHIFT_IMM: |
11515 | newval = md_chars_to_number (buf, INSN_SIZE); | |
11516 | if (((unsigned long) value) > 32 | |
11517 | || (value == 32 | |
11518 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
11519 | { | |
11520 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11521 | _("shift expression is too large")); | |
11522 | break; | |
11523 | } | |
404ff6b5 | 11524 | |
c19d1205 ZW |
11525 | if (value == 0) |
11526 | /* Shifts of zero must be done as lsl. */ | |
11527 | newval &= ~0x60; | |
11528 | else if (value == 32) | |
11529 | value = 0; | |
11530 | newval &= 0xfffff07f; | |
11531 | newval |= (value & 0x1f) << 7; | |
11532 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11533 | break; | |
404ff6b5 | 11534 | |
c19d1205 | 11535 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
92e90b6e | 11536 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 11537 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
11538 | /* We claim that this fixup has been processed here, |
11539 | even if in fact we generate an error because we do | |
11540 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
11541 | fixP->fx_done = 1; | |
404ff6b5 | 11542 | |
c19d1205 ZW |
11543 | if (fixP->fx_addsy |
11544 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
11545 | { | |
11546 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11547 | _("undefined symbol %s used as an immediate value"), | |
11548 | S_GET_NAME (fixP->fx_addsy)); | |
11549 | break; | |
11550 | } | |
404ff6b5 | 11551 | |
c19d1205 ZW |
11552 | newval = md_chars_to_number (buf, THUMB_SIZE); |
11553 | newval <<= 16; | |
11554 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 11555 | |
e9f89963 PB |
11556 | /* FUTURE: Implement analogue of negate_data_op for T32. */ |
11557 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE) | |
ef8d22e6 PB |
11558 | { |
11559 | newimm = encode_thumb32_immediate (value); | |
11560 | if (newimm == (unsigned int) FAIL) | |
11561 | newimm = thumb32_negate_data_op (&newval, value); | |
11562 | } | |
e9f89963 | 11563 | else |
92e90b6e | 11564 | { |
e9f89963 PB |
11565 | /* 12 bit immediate for addw/subw. */ |
11566 | if (value < 0) | |
11567 | { | |
11568 | value = -value; | |
11569 | newval ^= 0x00a00000; | |
11570 | } | |
92e90b6e PB |
11571 | if (value > 0xfff) |
11572 | newimm = (unsigned int) FAIL; | |
11573 | else | |
11574 | newimm = value; | |
11575 | } | |
cc8a6dd0 | 11576 | |
c19d1205 | 11577 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 11578 | { |
c19d1205 ZW |
11579 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11580 | _("invalid constant (%lx) after fixup"), | |
11581 | (unsigned long) value); | |
11582 | break; | |
3631a3c8 NC |
11583 | } |
11584 | ||
c19d1205 ZW |
11585 | newval |= (newimm & 0x800) << 15; |
11586 | newval |= (newimm & 0x700) << 4; | |
11587 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 11588 | |
c19d1205 ZW |
11589 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
11590 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
11591 | break; | |
a737bd4d | 11592 | |
3eb17e6b | 11593 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
11594 | if (((unsigned long) value) > 0xffff) |
11595 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 11596 | _("invalid smc expression")); |
2fc8bdac | 11597 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
11598 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
11599 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11600 | break; | |
a737bd4d | 11601 | |
c19d1205 | 11602 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 11603 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
11604 | { |
11605 | if (((unsigned long) value) > 0xff) | |
11606 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11607 | _("invalid swi expression")); | |
2fc8bdac | 11608 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
11609 | newval |= value; |
11610 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11611 | } | |
11612 | else | |
11613 | { | |
11614 | if (((unsigned long) value) > 0x00ffffff) | |
11615 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11616 | _("invalid swi expression")); | |
2fc8bdac | 11617 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
11618 | newval |= value; |
11619 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11620 | } | |
11621 | break; | |
a737bd4d | 11622 | |
c19d1205 ZW |
11623 | case BFD_RELOC_ARM_MULTI: |
11624 | if (((unsigned long) value) > 0xffff) | |
11625 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11626 | _("invalid expression in load/store multiple")); | |
11627 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
11628 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11629 | break; | |
a737bd4d | 11630 | |
c19d1205 | 11631 | #ifdef OBJ_ELF |
39b41c9c PB |
11632 | case BFD_RELOC_ARM_PCREL_CALL: |
11633 | newval = md_chars_to_number (buf, INSN_SIZE); | |
11634 | if ((newval & 0xf0000000) == 0xf0000000) | |
11635 | temp = 1; | |
11636 | else | |
11637 | temp = 3; | |
11638 | goto arm_branch_common; | |
11639 | ||
11640 | case BFD_RELOC_ARM_PCREL_JUMP: | |
2fc8bdac | 11641 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 11642 | #endif |
39b41c9c PB |
11643 | case BFD_RELOC_ARM_PCREL_BRANCH: |
11644 | temp = 3; | |
11645 | goto arm_branch_common; | |
a737bd4d | 11646 | |
39b41c9c PB |
11647 | case BFD_RELOC_ARM_PCREL_BLX: |
11648 | temp = 1; | |
11649 | arm_branch_common: | |
c19d1205 | 11650 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
11651 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
11652 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
11653 | also be be clear. */ | |
11654 | if (value & temp) | |
c19d1205 | 11655 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
11656 | _("misaligned branch destination")); |
11657 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
11658 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
11659 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11660 | _("branch out of range")); | |
a737bd4d | 11661 | |
2fc8bdac | 11662 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 11663 | { |
2fc8bdac ZW |
11664 | newval = md_chars_to_number (buf, INSN_SIZE); |
11665 | newval |= (value >> 2) & 0x00ffffff; | |
11666 | md_number_to_chars (buf, newval, INSN_SIZE); | |
c19d1205 | 11667 | } |
c19d1205 | 11668 | break; |
a737bd4d | 11669 | |
c19d1205 | 11670 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */ |
2fc8bdac ZW |
11671 | /* CZB can only branch forward. */ |
11672 | if (value & ~0x7e) | |
11673 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11674 | _("branch out of range")); | |
a737bd4d | 11675 | |
2fc8bdac ZW |
11676 | if (fixP->fx_done || !seg->use_rela_p) |
11677 | { | |
11678 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
c19d1205 | 11679 | newval |= ((value & 0x2e) << 2) | ((value & 0x40) << 3); |
2fc8bdac ZW |
11680 | md_number_to_chars (buf, newval, THUMB_SIZE); |
11681 | } | |
c19d1205 | 11682 | break; |
a737bd4d | 11683 | |
c19d1205 | 11684 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac ZW |
11685 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
11686 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11687 | _("branch out of range")); | |
a737bd4d | 11688 | |
2fc8bdac ZW |
11689 | if (fixP->fx_done || !seg->use_rela_p) |
11690 | { | |
11691 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11692 | newval |= (value & 0x1ff) >> 1; | |
11693 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11694 | } | |
c19d1205 | 11695 | break; |
a737bd4d | 11696 | |
c19d1205 | 11697 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac ZW |
11698 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
11699 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11700 | _("branch out of range")); | |
a737bd4d | 11701 | |
2fc8bdac ZW |
11702 | if (fixP->fx_done || !seg->use_rela_p) |
11703 | { | |
11704 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11705 | newval |= (value & 0xfff) >> 1; | |
11706 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11707 | } | |
c19d1205 | 11708 | break; |
a737bd4d | 11709 | |
c19d1205 | 11710 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
2fc8bdac ZW |
11711 | if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) |
11712 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11713 | _("conditional branch out of range")); | |
404ff6b5 | 11714 | |
2fc8bdac ZW |
11715 | if (fixP->fx_done || !seg->use_rela_p) |
11716 | { | |
11717 | offsetT newval2; | |
11718 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 11719 | |
2fc8bdac ZW |
11720 | S = (value & 0x00100000) >> 20; |
11721 | J2 = (value & 0x00080000) >> 19; | |
11722 | J1 = (value & 0x00040000) >> 18; | |
11723 | hi = (value & 0x0003f000) >> 12; | |
11724 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 11725 | |
2fc8bdac ZW |
11726 | newval = md_chars_to_number (buf, THUMB_SIZE); |
11727 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
11728 | newval |= (S << 10) | hi; | |
11729 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
11730 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11731 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
11732 | } | |
c19d1205 | 11733 | break; |
6c43fab6 | 11734 | |
c19d1205 ZW |
11735 | case BFD_RELOC_THUMB_PCREL_BLX: |
11736 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
2fc8bdac ZW |
11737 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
11738 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11739 | _("branch out of range")); | |
404ff6b5 | 11740 | |
2fc8bdac ZW |
11741 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
11742 | /* For a BLX instruction, make sure that the relocation is rounded up | |
11743 | to a word boundary. This follows the semantics of the instruction | |
11744 | which specifies that bit 1 of the target address will come from bit | |
11745 | 1 of the base address. */ | |
11746 | value = (value + 1) & ~ 1; | |
404ff6b5 | 11747 | |
2fc8bdac | 11748 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 11749 | { |
2fc8bdac ZW |
11750 | offsetT newval2; |
11751 | ||
11752 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11753 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
11754 | newval |= (value & 0x7fffff) >> 12; | |
11755 | newval2 |= (value & 0xfff) >> 1; | |
11756 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11757 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
c19d1205 | 11758 | } |
c19d1205 | 11759 | break; |
404ff6b5 | 11760 | |
c19d1205 | 11761 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac ZW |
11762 | if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) |
11763 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11764 | _("branch out of range")); | |
6c43fab6 | 11765 | |
2fc8bdac ZW |
11766 | if (fixP->fx_done || !seg->use_rela_p) |
11767 | { | |
11768 | offsetT newval2; | |
11769 | addressT S, I1, I2, lo, hi; | |
6c43fab6 | 11770 | |
2fc8bdac ZW |
11771 | S = (value & 0x01000000) >> 24; |
11772 | I1 = (value & 0x00800000) >> 23; | |
11773 | I2 = (value & 0x00400000) >> 22; | |
11774 | hi = (value & 0x003ff000) >> 12; | |
11775 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 11776 | |
2fc8bdac ZW |
11777 | I1 = !(I1 ^ S); |
11778 | I2 = !(I2 ^ S); | |
a737bd4d | 11779 | |
2fc8bdac ZW |
11780 | newval = md_chars_to_number (buf, THUMB_SIZE); |
11781 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
11782 | newval |= (S << 10) | hi; | |
11783 | newval2 |= (I1 << 13) | (I2 << 11) | lo; | |
11784 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11785 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
11786 | } | |
11787 | break; | |
a737bd4d | 11788 | |
2fc8bdac ZW |
11789 | case BFD_RELOC_8: |
11790 | if (fixP->fx_done || !seg->use_rela_p) | |
11791 | md_number_to_chars (buf, value, 1); | |
c19d1205 | 11792 | break; |
a737bd4d | 11793 | |
c19d1205 | 11794 | case BFD_RELOC_16: |
2fc8bdac | 11795 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 11796 | md_number_to_chars (buf, value, 2); |
c19d1205 | 11797 | break; |
a737bd4d | 11798 | |
c19d1205 ZW |
11799 | #ifdef OBJ_ELF |
11800 | case BFD_RELOC_ARM_TLS_GD32: | |
11801 | case BFD_RELOC_ARM_TLS_LE32: | |
11802 | case BFD_RELOC_ARM_TLS_IE32: | |
11803 | case BFD_RELOC_ARM_TLS_LDM32: | |
11804 | case BFD_RELOC_ARM_TLS_LDO32: | |
11805 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11806 | /* fall through */ | |
6c43fab6 | 11807 | |
c19d1205 ZW |
11808 | case BFD_RELOC_ARM_GOT32: |
11809 | case BFD_RELOC_ARM_GOTOFF: | |
11810 | case BFD_RELOC_ARM_TARGET2: | |
2fc8bdac ZW |
11811 | if (fixP->fx_done || !seg->use_rela_p) |
11812 | md_number_to_chars (buf, 0, 4); | |
c19d1205 ZW |
11813 | break; |
11814 | #endif | |
6c43fab6 | 11815 | |
c19d1205 ZW |
11816 | case BFD_RELOC_RVA: |
11817 | case BFD_RELOC_32: | |
11818 | case BFD_RELOC_ARM_TARGET1: | |
11819 | case BFD_RELOC_ARM_ROSEGREL32: | |
11820 | case BFD_RELOC_ARM_SBREL32: | |
11821 | case BFD_RELOC_32_PCREL: | |
2fc8bdac | 11822 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 11823 | md_number_to_chars (buf, value, 4); |
c19d1205 | 11824 | break; |
6c43fab6 | 11825 | |
c19d1205 ZW |
11826 | #ifdef OBJ_ELF |
11827 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 11828 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
11829 | { |
11830 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
11831 | if ((value ^ (value >> 1)) & 0x40000000) | |
11832 | { | |
11833 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11834 | _("rel31 relocation overflow")); | |
11835 | } | |
11836 | newval |= value & 0x7fffffff; | |
11837 | md_number_to_chars (buf, newval, 4); | |
11838 | } | |
11839 | break; | |
c19d1205 | 11840 | #endif |
a737bd4d | 11841 | |
c19d1205 | 11842 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 11843 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
11844 | if (value < -1023 || value > 1023 || (value & 3)) |
11845 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11846 | _("co-processor offset out of range")); | |
11847 | cp_off_common: | |
11848 | sign = value >= 0; | |
11849 | if (value < 0) | |
11850 | value = -value; | |
8f06b2d8 PB |
11851 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
11852 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
11853 | newval = md_chars_to_number (buf, INSN_SIZE); | |
11854 | else | |
11855 | newval = get_thumb32_insn (buf); | |
11856 | newval &= 0xff7fff00; | |
c19d1205 ZW |
11857 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); |
11858 | if (value == 0) | |
11859 | newval &= ~WRITE_BACK; | |
8f06b2d8 PB |
11860 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
11861 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
11862 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11863 | else | |
11864 | put_thumb32_insn (buf, newval); | |
c19d1205 | 11865 | break; |
a737bd4d | 11866 | |
c19d1205 | 11867 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 11868 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
11869 | if (value < -255 || value > 255) |
11870 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11871 | _("co-processor offset out of range")); | |
11872 | goto cp_off_common; | |
6c43fab6 | 11873 | |
c19d1205 ZW |
11874 | case BFD_RELOC_ARM_THUMB_OFFSET: |
11875 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11876 | /* Exactly what ranges, and where the offset is inserted depends | |
11877 | on the type of instruction, we can establish this from the | |
11878 | top 4 bits. */ | |
11879 | switch (newval >> 12) | |
11880 | { | |
11881 | case 4: /* PC load. */ | |
11882 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
11883 | forced to zero for these loads; md_pcrel_from has already | |
11884 | compensated for this. */ | |
11885 | if (value & 3) | |
11886 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11887 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
11888 | (((unsigned long) fixP->fx_frag->fr_address |
11889 | + (unsigned long) fixP->fx_where) & ~3) | |
11890 | + (unsigned long) value); | |
a737bd4d | 11891 | |
c19d1205 ZW |
11892 | if (value & ~0x3fc) |
11893 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11894 | _("invalid offset, value too big (0x%08lX)"), | |
11895 | (long) value); | |
a737bd4d | 11896 | |
c19d1205 ZW |
11897 | newval |= value >> 2; |
11898 | break; | |
a737bd4d | 11899 | |
c19d1205 ZW |
11900 | case 9: /* SP load/store. */ |
11901 | if (value & ~0x3fc) | |
11902 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11903 | _("invalid offset, value too big (0x%08lX)"), | |
11904 | (long) value); | |
11905 | newval |= value >> 2; | |
11906 | break; | |
6c43fab6 | 11907 | |
c19d1205 ZW |
11908 | case 6: /* Word load/store. */ |
11909 | if (value & ~0x7c) | |
11910 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11911 | _("invalid offset, value too big (0x%08lX)"), | |
11912 | (long) value); | |
11913 | newval |= value << 4; /* 6 - 2. */ | |
11914 | break; | |
a737bd4d | 11915 | |
c19d1205 ZW |
11916 | case 7: /* Byte load/store. */ |
11917 | if (value & ~0x1f) | |
11918 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11919 | _("invalid offset, value too big (0x%08lX)"), | |
11920 | (long) value); | |
11921 | newval |= value << 6; | |
11922 | break; | |
a737bd4d | 11923 | |
c19d1205 ZW |
11924 | case 8: /* Halfword load/store. */ |
11925 | if (value & ~0x3e) | |
11926 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11927 | _("invalid offset, value too big (0x%08lX)"), | |
11928 | (long) value); | |
11929 | newval |= value << 5; /* 6 - 1. */ | |
11930 | break; | |
a737bd4d | 11931 | |
c19d1205 ZW |
11932 | default: |
11933 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11934 | "Unable to process relocation for thumb opcode: %lx", | |
11935 | (unsigned long) newval); | |
11936 | break; | |
11937 | } | |
11938 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11939 | break; | |
a737bd4d | 11940 | |
c19d1205 ZW |
11941 | case BFD_RELOC_ARM_THUMB_ADD: |
11942 | /* This is a complicated relocation, since we use it for all of | |
11943 | the following immediate relocations: | |
a737bd4d | 11944 | |
c19d1205 ZW |
11945 | 3bit ADD/SUB |
11946 | 8bit ADD/SUB | |
11947 | 9bit ADD/SUB SP word-aligned | |
11948 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 11949 | |
c19d1205 ZW |
11950 | The type of instruction being processed is encoded in the |
11951 | instruction field: | |
a737bd4d | 11952 | |
c19d1205 ZW |
11953 | 0x8000 SUB |
11954 | 0x00F0 Rd | |
11955 | 0x000F Rs | |
11956 | */ | |
11957 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11958 | { | |
11959 | int rd = (newval >> 4) & 0xf; | |
11960 | int rs = newval & 0xf; | |
11961 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 11962 | |
c19d1205 ZW |
11963 | /* Check for HI regs, only very restricted cases allowed: |
11964 | Adjusting SP, and using PC or SP to get an address. */ | |
11965 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
11966 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
11967 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11968 | _("invalid Hi register with immediate")); | |
a737bd4d | 11969 | |
c19d1205 ZW |
11970 | /* If value is negative, choose the opposite instruction. */ |
11971 | if (value < 0) | |
11972 | { | |
11973 | value = -value; | |
11974 | subtract = !subtract; | |
11975 | if (value < 0) | |
11976 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11977 | _("immediate value out of range")); | |
11978 | } | |
a737bd4d | 11979 | |
c19d1205 ZW |
11980 | if (rd == REG_SP) |
11981 | { | |
11982 | if (value & ~0x1fc) | |
11983 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11984 | _("invalid immediate for stack address calculation")); | |
11985 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
11986 | newval |= value >> 2; | |
11987 | } | |
11988 | else if (rs == REG_PC || rs == REG_SP) | |
11989 | { | |
11990 | if (subtract || value & ~0x3fc) | |
11991 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11992 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
11993 | (unsigned long) value); | |
11994 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
11995 | newval |= rd << 8; | |
11996 | newval |= value >> 2; | |
11997 | } | |
11998 | else if (rs == rd) | |
11999 | { | |
12000 | if (value & ~0xff) | |
12001 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12002 | _("immediate value out of range")); | |
12003 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
12004 | newval |= (rd << 8) | value; | |
12005 | } | |
12006 | else | |
12007 | { | |
12008 | if (value & ~0x7) | |
12009 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12010 | _("immediate value out of range")); | |
12011 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
12012 | newval |= rd | (rs << 3) | (value << 6); | |
12013 | } | |
12014 | } | |
12015 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
12016 | break; | |
a737bd4d | 12017 | |
c19d1205 ZW |
12018 | case BFD_RELOC_ARM_THUMB_IMM: |
12019 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
12020 | if (value < 0 || value > 255) | |
12021 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12022 | _("invalid immediate: %ld is too large"), | |
12023 | (long) value); | |
12024 | newval |= value; | |
12025 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
12026 | break; | |
a737bd4d | 12027 | |
c19d1205 ZW |
12028 | case BFD_RELOC_ARM_THUMB_SHIFT: |
12029 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
12030 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
12031 | temp = newval & 0xf800; | |
12032 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
12033 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12034 | _("invalid shift value: %ld"), (long) value); | |
12035 | /* Shifts of zero must be encoded as LSL. */ | |
12036 | if (value == 0) | |
12037 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
12038 | /* Shifts of 32 are encoded as zero. */ | |
12039 | else if (value == 32) | |
12040 | value = 0; | |
12041 | newval |= value << 6; | |
12042 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
12043 | break; | |
a737bd4d | 12044 | |
c19d1205 ZW |
12045 | case BFD_RELOC_VTABLE_INHERIT: |
12046 | case BFD_RELOC_VTABLE_ENTRY: | |
12047 | fixP->fx_done = 0; | |
12048 | return; | |
6c43fab6 | 12049 | |
c19d1205 ZW |
12050 | case BFD_RELOC_UNUSED: |
12051 | default: | |
12052 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12053 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
12054 | } | |
6c43fab6 RE |
12055 | } |
12056 | ||
c19d1205 ZW |
12057 | /* Translate internal representation of relocation info to BFD target |
12058 | format. */ | |
a737bd4d | 12059 | |
c19d1205 ZW |
12060 | arelent * |
12061 | tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, | |
12062 | fixS * fixp) | |
a737bd4d | 12063 | { |
c19d1205 ZW |
12064 | arelent * reloc; |
12065 | bfd_reloc_code_real_type code; | |
a737bd4d | 12066 | |
c19d1205 | 12067 | reloc = xmalloc (sizeof (arelent)); |
a737bd4d | 12068 | |
c19d1205 ZW |
12069 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); |
12070 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
12071 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 12072 | |
2fc8bdac ZW |
12073 | if (fixp->fx_pcrel) |
12074 | fixp->fx_offset = reloc->address; | |
c19d1205 | 12075 | reloc->addend = fixp->fx_offset; |
a737bd4d | 12076 | |
c19d1205 | 12077 | switch (fixp->fx_r_type) |
a737bd4d | 12078 | { |
c19d1205 ZW |
12079 | case BFD_RELOC_8: |
12080 | if (fixp->fx_pcrel) | |
12081 | { | |
12082 | code = BFD_RELOC_8_PCREL; | |
12083 | break; | |
12084 | } | |
a737bd4d | 12085 | |
c19d1205 ZW |
12086 | case BFD_RELOC_16: |
12087 | if (fixp->fx_pcrel) | |
12088 | { | |
12089 | code = BFD_RELOC_16_PCREL; | |
12090 | break; | |
12091 | } | |
6c43fab6 | 12092 | |
c19d1205 ZW |
12093 | case BFD_RELOC_32: |
12094 | if (fixp->fx_pcrel) | |
12095 | { | |
12096 | code = BFD_RELOC_32_PCREL; | |
12097 | break; | |
12098 | } | |
a737bd4d | 12099 | |
c19d1205 ZW |
12100 | case BFD_RELOC_NONE: |
12101 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
12102 | case BFD_RELOC_ARM_PCREL_BLX: | |
12103 | case BFD_RELOC_RVA: | |
12104 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
12105 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
12106 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
12107 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
12108 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
12109 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
12110 | case BFD_RELOC_THUMB_PCREL_BLX: | |
12111 | case BFD_RELOC_VTABLE_ENTRY: | |
12112 | case BFD_RELOC_VTABLE_INHERIT: | |
12113 | code = fixp->fx_r_type; | |
12114 | break; | |
a737bd4d | 12115 | |
c19d1205 ZW |
12116 | case BFD_RELOC_ARM_LITERAL: |
12117 | case BFD_RELOC_ARM_HWLITERAL: | |
12118 | /* If this is called then the a literal has | |
12119 | been referenced across a section boundary. */ | |
12120 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12121 | _("literal referenced across section boundary")); | |
12122 | return NULL; | |
a737bd4d | 12123 | |
c19d1205 ZW |
12124 | #ifdef OBJ_ELF |
12125 | case BFD_RELOC_ARM_GOT32: | |
12126 | case BFD_RELOC_ARM_GOTOFF: | |
12127 | case BFD_RELOC_ARM_PLT32: | |
12128 | case BFD_RELOC_ARM_TARGET1: | |
12129 | case BFD_RELOC_ARM_ROSEGREL32: | |
12130 | case BFD_RELOC_ARM_SBREL32: | |
12131 | case BFD_RELOC_ARM_PREL31: | |
12132 | case BFD_RELOC_ARM_TARGET2: | |
12133 | case BFD_RELOC_ARM_TLS_LE32: | |
12134 | case BFD_RELOC_ARM_TLS_LDO32: | |
39b41c9c PB |
12135 | case BFD_RELOC_ARM_PCREL_CALL: |
12136 | case BFD_RELOC_ARM_PCREL_JUMP: | |
c19d1205 ZW |
12137 | code = fixp->fx_r_type; |
12138 | break; | |
a737bd4d | 12139 | |
c19d1205 ZW |
12140 | case BFD_RELOC_ARM_TLS_GD32: |
12141 | case BFD_RELOC_ARM_TLS_IE32: | |
12142 | case BFD_RELOC_ARM_TLS_LDM32: | |
12143 | /* BFD will include the symbol's address in the addend. | |
12144 | But we don't want that, so subtract it out again here. */ | |
12145 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
12146 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
12147 | code = fixp->fx_r_type; | |
12148 | break; | |
12149 | #endif | |
a737bd4d | 12150 | |
c19d1205 ZW |
12151 | case BFD_RELOC_ARM_IMMEDIATE: |
12152 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12153 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
12154 | return NULL; | |
a737bd4d | 12155 | |
c19d1205 ZW |
12156 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
12157 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12158 | _("ADRL used for a symbol not defined in the same file")); | |
12159 | return NULL; | |
a737bd4d | 12160 | |
c19d1205 ZW |
12161 | case BFD_RELOC_ARM_OFFSET_IMM: |
12162 | if (fixp->fx_addsy != NULL | |
12163 | && !S_IS_DEFINED (fixp->fx_addsy) | |
12164 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 12165 | { |
c19d1205 ZW |
12166 | as_bad_where (fixp->fx_file, fixp->fx_line, |
12167 | _("undefined local label `%s'"), | |
12168 | S_GET_NAME (fixp->fx_addsy)); | |
12169 | return NULL; | |
a737bd4d NC |
12170 | } |
12171 | ||
c19d1205 ZW |
12172 | as_bad_where (fixp->fx_file, fixp->fx_line, |
12173 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
12174 | return NULL; | |
a737bd4d | 12175 | |
c19d1205 ZW |
12176 | default: |
12177 | { | |
12178 | char * type; | |
6c43fab6 | 12179 | |
c19d1205 ZW |
12180 | switch (fixp->fx_r_type) |
12181 | { | |
12182 | case BFD_RELOC_NONE: type = "NONE"; break; | |
12183 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
12184 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 12185 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
12186 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
12187 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
12188 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
8f06b2d8 | 12189 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
12190 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
12191 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
12192 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
12193 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
12194 | default: type = _("<unknown>"); break; | |
12195 | } | |
12196 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12197 | _("cannot represent %s relocation in this object file format"), | |
12198 | type); | |
12199 | return NULL; | |
12200 | } | |
a737bd4d | 12201 | } |
6c43fab6 | 12202 | |
c19d1205 ZW |
12203 | #ifdef OBJ_ELF |
12204 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
12205 | && GOT_symbol | |
12206 | && fixp->fx_addsy == GOT_symbol) | |
12207 | { | |
12208 | code = BFD_RELOC_ARM_GOTPC; | |
12209 | reloc->addend = fixp->fx_offset = reloc->address; | |
12210 | } | |
12211 | #endif | |
6c43fab6 | 12212 | |
c19d1205 | 12213 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 12214 | |
c19d1205 ZW |
12215 | if (reloc->howto == NULL) |
12216 | { | |
12217 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12218 | _("cannot represent %s relocation in this object file format"), | |
12219 | bfd_get_reloc_code_name (code)); | |
12220 | return NULL; | |
12221 | } | |
6c43fab6 | 12222 | |
c19d1205 ZW |
12223 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
12224 | vtable entry to be used in the relocation's section offset. */ | |
12225 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12226 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 12227 | |
c19d1205 | 12228 | return reloc; |
6c43fab6 RE |
12229 | } |
12230 | ||
c19d1205 | 12231 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 12232 | |
c19d1205 ZW |
12233 | void |
12234 | cons_fix_new_arm (fragS * frag, | |
12235 | int where, | |
12236 | int size, | |
12237 | expressionS * exp) | |
6c43fab6 | 12238 | { |
c19d1205 ZW |
12239 | bfd_reloc_code_real_type type; |
12240 | int pcrel = 0; | |
6c43fab6 | 12241 | |
c19d1205 ZW |
12242 | /* Pick a reloc. |
12243 | FIXME: @@ Should look at CPU word size. */ | |
12244 | switch (size) | |
12245 | { | |
12246 | case 1: | |
12247 | type = BFD_RELOC_8; | |
12248 | break; | |
12249 | case 2: | |
12250 | type = BFD_RELOC_16; | |
12251 | break; | |
12252 | case 4: | |
12253 | default: | |
12254 | type = BFD_RELOC_32; | |
12255 | break; | |
12256 | case 8: | |
12257 | type = BFD_RELOC_64; | |
12258 | break; | |
12259 | } | |
6c43fab6 | 12260 | |
c19d1205 ZW |
12261 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); |
12262 | } | |
6c43fab6 | 12263 | |
c19d1205 ZW |
12264 | #if defined OBJ_COFF || defined OBJ_ELF |
12265 | void | |
12266 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 12267 | { |
c19d1205 ZW |
12268 | /* If the destination of the branch is a defined symbol which does not have |
12269 | the THUMB_FUNC attribute, then we must be calling a function which has | |
12270 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
12271 | function and change the branch to refer to that function instead. */ | |
12272 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
12273 | && fixP->fx_addsy != NULL | |
12274 | && S_IS_DEFINED (fixP->fx_addsy) | |
12275 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 12276 | { |
c19d1205 | 12277 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 12278 | } |
c19d1205 ZW |
12279 | } |
12280 | #endif | |
6c43fab6 | 12281 | |
c19d1205 ZW |
12282 | int |
12283 | arm_force_relocation (struct fix * fixp) | |
12284 | { | |
12285 | #if defined (OBJ_COFF) && defined (TE_PE) | |
12286 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
12287 | return 1; | |
12288 | #endif | |
6c43fab6 | 12289 | |
c19d1205 ZW |
12290 | /* Resolve these relocations even if the symbol is extern or weak. */ |
12291 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE | |
12292 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
0110f2b8 PB |
12293 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
12294 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE | |
12295 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
12296 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12) | |
c19d1205 | 12297 | return 0; |
a737bd4d | 12298 | |
c19d1205 | 12299 | return generic_force_reloc (fixp); |
404ff6b5 AH |
12300 | } |
12301 | ||
c19d1205 ZW |
12302 | #ifdef OBJ_COFF |
12303 | /* This is a little hack to help the gas/arm/adrl.s test. It prevents | |
12304 | local labels from being added to the output symbol table when they | |
12305 | are used with the ADRL pseudo op. The ADRL relocation should always | |
12306 | be resolved before the binbary is emitted, so it is safe to say that | |
12307 | it is adjustable. */ | |
404ff6b5 | 12308 | |
c19d1205 ZW |
12309 | bfd_boolean |
12310 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 12311 | { |
c19d1205 ZW |
12312 | if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE) |
12313 | return 1; | |
12314 | return 0; | |
404ff6b5 | 12315 | } |
c19d1205 | 12316 | #endif |
404ff6b5 | 12317 | |
c19d1205 ZW |
12318 | #ifdef OBJ_ELF |
12319 | /* Relocations against Thumb function names must be left unadjusted, | |
12320 | so that the linker can use this information to correctly set the | |
12321 | bottom bit of their addresses. The MIPS version of this function | |
12322 | also prevents relocations that are mips-16 specific, but I do not | |
12323 | know why it does this. | |
404ff6b5 | 12324 | |
c19d1205 ZW |
12325 | FIXME: |
12326 | There is one other problem that ought to be addressed here, but | |
12327 | which currently is not: Taking the address of a label (rather | |
12328 | than a function) and then later jumping to that address. Such | |
12329 | addresses also ought to have their bottom bit set (assuming that | |
12330 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 12331 | |
c19d1205 ZW |
12332 | bfd_boolean |
12333 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 12334 | { |
c19d1205 ZW |
12335 | if (fixP->fx_addsy == NULL) |
12336 | return 1; | |
404ff6b5 | 12337 | |
c19d1205 ZW |
12338 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
12339 | && fixP->fx_subsy == NULL) | |
12340 | return 0; | |
a737bd4d | 12341 | |
c19d1205 ZW |
12342 | /* We need the symbol name for the VTABLE entries. */ |
12343 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
12344 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12345 | return 0; | |
404ff6b5 | 12346 | |
c19d1205 ZW |
12347 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
12348 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
12349 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
12350 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
12351 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
12352 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
12353 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
12354 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
12355 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
12356 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) | |
12357 | return 0; | |
a737bd4d | 12358 | |
c19d1205 | 12359 | return 1; |
a737bd4d | 12360 | } |
404ff6b5 | 12361 | |
c19d1205 ZW |
12362 | const char * |
12363 | elf32_arm_target_format (void) | |
404ff6b5 | 12364 | { |
c19d1205 ZW |
12365 | #ifdef TE_SYMBIAN |
12366 | return (target_big_endian | |
12367 | ? "elf32-bigarm-symbian" | |
12368 | : "elf32-littlearm-symbian"); | |
12369 | #elif defined (TE_VXWORKS) | |
12370 | return (target_big_endian | |
12371 | ? "elf32-bigarm-vxworks" | |
12372 | : "elf32-littlearm-vxworks"); | |
12373 | #else | |
12374 | if (target_big_endian) | |
12375 | return "elf32-bigarm"; | |
12376 | else | |
12377 | return "elf32-littlearm"; | |
12378 | #endif | |
404ff6b5 AH |
12379 | } |
12380 | ||
c19d1205 ZW |
12381 | void |
12382 | armelf_frob_symbol (symbolS * symp, | |
12383 | int * puntp) | |
404ff6b5 | 12384 | { |
c19d1205 ZW |
12385 | elf_frob_symbol (symp, puntp); |
12386 | } | |
12387 | #endif | |
404ff6b5 | 12388 | |
c19d1205 | 12389 | /* MD interface: Finalization. */ |
a737bd4d | 12390 | |
c19d1205 ZW |
12391 | /* A good place to do this, although this was probably not intended |
12392 | for this kind of use. We need to dump the literal pool before | |
12393 | references are made to a null symbol pointer. */ | |
a737bd4d | 12394 | |
c19d1205 ZW |
12395 | void |
12396 | arm_cleanup (void) | |
12397 | { | |
12398 | literal_pool * pool; | |
a737bd4d | 12399 | |
c19d1205 ZW |
12400 | for (pool = list_of_pools; pool; pool = pool->next) |
12401 | { | |
12402 | /* Put it at the end of the relevent section. */ | |
12403 | subseg_set (pool->section, pool->sub_section); | |
12404 | #ifdef OBJ_ELF | |
12405 | arm_elf_change_section (); | |
12406 | #endif | |
12407 | s_ltorg (0); | |
12408 | } | |
404ff6b5 AH |
12409 | } |
12410 | ||
c19d1205 ZW |
12411 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
12412 | ARM ones. */ | |
404ff6b5 | 12413 | |
c19d1205 ZW |
12414 | void |
12415 | arm_adjust_symtab (void) | |
404ff6b5 | 12416 | { |
c19d1205 ZW |
12417 | #ifdef OBJ_COFF |
12418 | symbolS * sym; | |
404ff6b5 | 12419 | |
c19d1205 ZW |
12420 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
12421 | { | |
12422 | if (ARM_IS_THUMB (sym)) | |
12423 | { | |
12424 | if (THUMB_IS_FUNC (sym)) | |
12425 | { | |
12426 | /* Mark the symbol as a Thumb function. */ | |
12427 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
12428 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
12429 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 12430 | |
c19d1205 ZW |
12431 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
12432 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
12433 | else | |
12434 | as_bad (_("%s: unexpected function type: %d"), | |
12435 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
12436 | } | |
12437 | else switch (S_GET_STORAGE_CLASS (sym)) | |
12438 | { | |
12439 | case C_EXT: | |
12440 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
12441 | break; | |
12442 | case C_STAT: | |
12443 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
12444 | break; | |
12445 | case C_LABEL: | |
12446 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
12447 | break; | |
12448 | default: | |
12449 | /* Do nothing. */ | |
12450 | break; | |
12451 | } | |
12452 | } | |
a737bd4d | 12453 | |
c19d1205 ZW |
12454 | if (ARM_IS_INTERWORK (sym)) |
12455 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 12456 | } |
c19d1205 ZW |
12457 | #endif |
12458 | #ifdef OBJ_ELF | |
12459 | symbolS * sym; | |
12460 | char bind; | |
404ff6b5 | 12461 | |
c19d1205 | 12462 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 12463 | { |
c19d1205 ZW |
12464 | if (ARM_IS_THUMB (sym)) |
12465 | { | |
12466 | elf_symbol_type * elf_sym; | |
404ff6b5 | 12467 | |
c19d1205 ZW |
12468 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
12469 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 12470 | |
c19d1205 ZW |
12471 | if (! bfd_is_arm_mapping_symbol_name (elf_sym->symbol.name)) |
12472 | { | |
12473 | /* If it's a .thumb_func, declare it as so, | |
12474 | otherwise tag label as .code 16. */ | |
12475 | if (THUMB_IS_FUNC (sym)) | |
12476 | elf_sym->internal_elf_sym.st_info = | |
12477 | ELF_ST_INFO (bind, STT_ARM_TFUNC); | |
12478 | else | |
12479 | elf_sym->internal_elf_sym.st_info = | |
12480 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
12481 | } | |
12482 | } | |
12483 | } | |
12484 | #endif | |
404ff6b5 AH |
12485 | } |
12486 | ||
c19d1205 | 12487 | /* MD interface: Initialization. */ |
404ff6b5 | 12488 | |
a737bd4d | 12489 | static void |
c19d1205 | 12490 | set_constant_flonums (void) |
a737bd4d | 12491 | { |
c19d1205 | 12492 | int i; |
404ff6b5 | 12493 | |
c19d1205 ZW |
12494 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
12495 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
12496 | abort (); | |
a737bd4d | 12497 | } |
404ff6b5 | 12498 | |
c19d1205 ZW |
12499 | void |
12500 | md_begin (void) | |
a737bd4d | 12501 | { |
c19d1205 ZW |
12502 | unsigned mach; |
12503 | unsigned int i; | |
404ff6b5 | 12504 | |
c19d1205 ZW |
12505 | if ( (arm_ops_hsh = hash_new ()) == NULL |
12506 | || (arm_cond_hsh = hash_new ()) == NULL | |
12507 | || (arm_shift_hsh = hash_new ()) == NULL | |
12508 | || (arm_psr_hsh = hash_new ()) == NULL | |
12509 | || (arm_reg_hsh = hash_new ()) == NULL | |
12510 | || (arm_reloc_hsh = hash_new ()) == NULL) | |
12511 | as_fatal (_("virtual memory exhausted")); | |
12512 | ||
12513 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
12514 | hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i)); | |
12515 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) | |
12516 | hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i)); | |
12517 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) | |
12518 | hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i)); | |
12519 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) | |
12520 | hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i)); | |
12521 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) | |
12522 | hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i)); | |
12523 | #ifdef OBJ_ELF | |
12524 | for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) | |
12525 | hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i)); | |
12526 | #endif | |
12527 | ||
12528 | set_constant_flonums (); | |
404ff6b5 | 12529 | |
c19d1205 ZW |
12530 | /* Set the cpu variant based on the command-line options. We prefer |
12531 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
12532 | -mfpu= over any other way of setting the floating point unit. | |
12533 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 12534 | if (legacy_cpu) |
404ff6b5 | 12535 | { |
e74cfd16 | 12536 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
12537 | as_bad (_("use of old and new-style options to set CPU type")); |
12538 | ||
12539 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 12540 | } |
e74cfd16 | 12541 | else if (!mcpu_cpu_opt) |
c19d1205 | 12542 | mcpu_cpu_opt = march_cpu_opt; |
404ff6b5 | 12543 | |
e74cfd16 | 12544 | if (legacy_fpu) |
c19d1205 | 12545 | { |
e74cfd16 | 12546 | if (mfpu_opt) |
c19d1205 | 12547 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f RE |
12548 | |
12549 | mfpu_opt = legacy_fpu; | |
12550 | } | |
e74cfd16 | 12551 | else if (!mfpu_opt) |
03b1477f | 12552 | { |
c19d1205 | 12553 | #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS)) |
39c2da32 RE |
12554 | /* Some environments specify a default FPU. If they don't, infer it |
12555 | from the processor. */ | |
e74cfd16 | 12556 | if (mcpu_fpu_opt) |
03b1477f RE |
12557 | mfpu_opt = mcpu_fpu_opt; |
12558 | else | |
12559 | mfpu_opt = march_fpu_opt; | |
39c2da32 | 12560 | #else |
e74cfd16 | 12561 | mfpu_opt = &fpu_default; |
39c2da32 | 12562 | #endif |
03b1477f RE |
12563 | } |
12564 | ||
e74cfd16 | 12565 | if (!mfpu_opt) |
03b1477f | 12566 | { |
e74cfd16 PB |
12567 | if (!mcpu_cpu_opt) |
12568 | mfpu_opt = &fpu_default; | |
12569 | else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) | |
12570 | mfpu_opt = &fpu_arch_vfp_v2; | |
03b1477f | 12571 | else |
e74cfd16 | 12572 | mfpu_opt = &fpu_arch_fpa; |
03b1477f RE |
12573 | } |
12574 | ||
ee065d83 | 12575 | #ifdef CPU_DEFAULT |
e74cfd16 | 12576 | if (!mcpu_cpu_opt) |
ee065d83 | 12577 | { |
e74cfd16 PB |
12578 | mcpu_cpu_opt = &cpu_default; |
12579 | selected_cpu = cpu_default; | |
ee065d83 | 12580 | } |
e74cfd16 PB |
12581 | #else |
12582 | if (mcpu_cpu_opt) | |
12583 | selected_cpu = *mcpu_cpu_opt; | |
ee065d83 | 12584 | else |
e74cfd16 | 12585 | mcpu_cpu_opt = &arm_arch_any; |
ee065d83 | 12586 | #endif |
03b1477f | 12587 | |
e74cfd16 | 12588 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
03b1477f | 12589 | |
e74cfd16 | 12590 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 12591 | |
f17c130b | 12592 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 12593 | { |
7cc69913 NC |
12594 | unsigned int flags = 0; |
12595 | ||
12596 | #if defined OBJ_ELF | |
12597 | flags = meabi_flags; | |
d507cf36 PB |
12598 | |
12599 | switch (meabi_flags) | |
33a392fb | 12600 | { |
d507cf36 | 12601 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 12602 | #endif |
d507cf36 PB |
12603 | /* Set the flags in the private structure. */ |
12604 | if (uses_apcs_26) flags |= F_APCS26; | |
12605 | if (support_interwork) flags |= F_INTERWORK; | |
12606 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 12607 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 12608 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
12609 | flags |= F_SOFT_FLOAT; |
12610 | ||
d507cf36 PB |
12611 | switch (mfloat_abi_opt) |
12612 | { | |
12613 | case ARM_FLOAT_ABI_SOFT: | |
12614 | case ARM_FLOAT_ABI_SOFTFP: | |
12615 | flags |= F_SOFT_FLOAT; | |
12616 | break; | |
33a392fb | 12617 | |
d507cf36 PB |
12618 | case ARM_FLOAT_ABI_HARD: |
12619 | if (flags & F_SOFT_FLOAT) | |
12620 | as_bad (_("hard-float conflicts with specified fpu")); | |
12621 | break; | |
12622 | } | |
03b1477f | 12623 | |
e74cfd16 PB |
12624 | /* Using pure-endian doubles (even if soft-float). */ |
12625 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 12626 | flags |= F_VFP_FLOAT; |
f17c130b | 12627 | |
fde78edd | 12628 | #if defined OBJ_ELF |
e74cfd16 | 12629 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 12630 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
12631 | break; |
12632 | ||
8cb51566 | 12633 | case EF_ARM_EABI_VER4: |
c19d1205 | 12634 | /* No additional flags to set. */ |
d507cf36 PB |
12635 | break; |
12636 | ||
12637 | default: | |
12638 | abort (); | |
12639 | } | |
7cc69913 | 12640 | #endif |
b99bd4ef NC |
12641 | bfd_set_private_flags (stdoutput, flags); |
12642 | ||
12643 | /* We have run out flags in the COFF header to encode the | |
12644 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 12645 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
12646 | if (atpcs) |
12647 | { | |
12648 | asection * sec; | |
12649 | ||
12650 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
12651 | ||
12652 | if (sec != NULL) | |
12653 | { | |
12654 | bfd_set_section_flags | |
12655 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
12656 | bfd_set_section_size (stdoutput, sec, 0); | |
12657 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
12658 | } | |
12659 | } | |
7cc69913 | 12660 | } |
f17c130b | 12661 | #endif |
b99bd4ef NC |
12662 | |
12663 | /* Record the CPU type as well. */ | |
e74cfd16 | 12664 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) |
e16bb312 | 12665 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 12666 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 12667 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 12668 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 12669 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 12670 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 12671 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 12672 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 12673 | { |
e74cfd16 | 12674 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
12675 | mach = bfd_mach_arm_5T; |
12676 | else | |
12677 | mach = bfd_mach_arm_5; | |
12678 | } | |
e74cfd16 | 12679 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 12680 | { |
e74cfd16 | 12681 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
12682 | mach = bfd_mach_arm_4T; |
12683 | else | |
12684 | mach = bfd_mach_arm_4; | |
12685 | } | |
e74cfd16 | 12686 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 12687 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
12688 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
12689 | mach = bfd_mach_arm_3; | |
12690 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
12691 | mach = bfd_mach_arm_2a; | |
12692 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
12693 | mach = bfd_mach_arm_2; | |
12694 | else | |
12695 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
12696 | |
12697 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
12698 | } | |
12699 | ||
c19d1205 | 12700 | /* Command line processing. */ |
b99bd4ef | 12701 | |
c19d1205 ZW |
12702 | /* md_parse_option |
12703 | Invocation line includes a switch not recognized by the base assembler. | |
12704 | See if it's a processor-specific option. | |
b99bd4ef | 12705 | |
c19d1205 ZW |
12706 | This routine is somewhat complicated by the need for backwards |
12707 | compatibility (since older releases of gcc can't be changed). | |
12708 | The new options try to make the interface as compatible as | |
12709 | possible with GCC. | |
b99bd4ef | 12710 | |
c19d1205 | 12711 | New options (supported) are: |
b99bd4ef | 12712 | |
c19d1205 ZW |
12713 | -mcpu=<cpu name> Assemble for selected processor |
12714 | -march=<architecture name> Assemble for selected architecture | |
12715 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
12716 | -EB/-mbig-endian Big-endian | |
12717 | -EL/-mlittle-endian Little-endian | |
12718 | -k Generate PIC code | |
12719 | -mthumb Start in Thumb mode | |
12720 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 12721 | |
c19d1205 | 12722 | For now we will also provide support for: |
b99bd4ef | 12723 | |
c19d1205 ZW |
12724 | -mapcs-32 32-bit Program counter |
12725 | -mapcs-26 26-bit Program counter | |
12726 | -macps-float Floats passed in FP registers | |
12727 | -mapcs-reentrant Reentrant code | |
12728 | -matpcs | |
12729 | (sometime these will probably be replaced with -mapcs=<list of options> | |
12730 | and -matpcs=<list of options>) | |
b99bd4ef | 12731 | |
c19d1205 ZW |
12732 | The remaining options are only supported for back-wards compatibility. |
12733 | Cpu variants, the arm part is optional: | |
12734 | -m[arm]1 Currently not supported. | |
12735 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
12736 | -m[arm]3 Arm 3 processor | |
12737 | -m[arm]6[xx], Arm 6 processors | |
12738 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
12739 | -m[arm]8[10] Arm 8 processors | |
12740 | -m[arm]9[20][tdmi] Arm 9 processors | |
12741 | -mstrongarm[110[0]] StrongARM processors | |
12742 | -mxscale XScale processors | |
12743 | -m[arm]v[2345[t[e]]] Arm architectures | |
12744 | -mall All (except the ARM1) | |
12745 | FP variants: | |
12746 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
12747 | -mfpe-old (No float load/store multiples) | |
12748 | -mvfpxd VFP Single precision | |
12749 | -mvfp All VFP | |
12750 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 12751 | |
c19d1205 ZW |
12752 | The following CPU names are recognized: |
12753 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
12754 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
12755 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
12756 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
12757 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
12758 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
12759 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 12760 | |
c19d1205 | 12761 | */ |
b99bd4ef | 12762 | |
c19d1205 | 12763 | const char * md_shortopts = "m:k"; |
b99bd4ef | 12764 | |
c19d1205 ZW |
12765 | #ifdef ARM_BI_ENDIAN |
12766 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
12767 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 12768 | #else |
c19d1205 ZW |
12769 | #if TARGET_BYTES_BIG_ENDIAN |
12770 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 12771 | #else |
c19d1205 ZW |
12772 | #define OPTION_EL (OPTION_MD_BASE + 1) |
12773 | #endif | |
b99bd4ef | 12774 | #endif |
b99bd4ef | 12775 | |
c19d1205 | 12776 | struct option md_longopts[] = |
b99bd4ef | 12777 | { |
c19d1205 ZW |
12778 | #ifdef OPTION_EB |
12779 | {"EB", no_argument, NULL, OPTION_EB}, | |
12780 | #endif | |
12781 | #ifdef OPTION_EL | |
12782 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 12783 | #endif |
c19d1205 ZW |
12784 | {NULL, no_argument, NULL, 0} |
12785 | }; | |
b99bd4ef | 12786 | |
c19d1205 | 12787 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 12788 | |
c19d1205 | 12789 | struct arm_option_table |
b99bd4ef | 12790 | { |
c19d1205 ZW |
12791 | char *option; /* Option name to match. */ |
12792 | char *help; /* Help information. */ | |
12793 | int *var; /* Variable to change. */ | |
12794 | int value; /* What to change it to. */ | |
12795 | char *deprecated; /* If non-null, print this message. */ | |
12796 | }; | |
b99bd4ef | 12797 | |
c19d1205 ZW |
12798 | struct arm_option_table arm_opts[] = |
12799 | { | |
12800 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
12801 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
12802 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
12803 | &support_interwork, 1, NULL}, | |
12804 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
12805 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
12806 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
12807 | 1, NULL}, | |
12808 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
12809 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
12810 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
12811 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
12812 | NULL}, | |
b99bd4ef | 12813 | |
c19d1205 ZW |
12814 | /* These are recognized by the assembler, but have no affect on code. */ |
12815 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
12816 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
e74cfd16 PB |
12817 | {NULL, NULL, NULL, 0, NULL} |
12818 | }; | |
12819 | ||
12820 | struct arm_legacy_option_table | |
12821 | { | |
12822 | char *option; /* Option name to match. */ | |
12823 | const arm_feature_set **var; /* Variable to change. */ | |
12824 | const arm_feature_set value; /* What to change it to. */ | |
12825 | char *deprecated; /* If non-null, print this message. */ | |
12826 | }; | |
b99bd4ef | 12827 | |
e74cfd16 PB |
12828 | const struct arm_legacy_option_table arm_legacy_opts[] = |
12829 | { | |
c19d1205 ZW |
12830 | /* DON'T add any new processors to this list -- we want the whole list |
12831 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
12832 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
12833 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
12834 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
12835 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
12836 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
12837 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
12838 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
12839 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
12840 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
12841 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
12842 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
12843 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
12844 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
12845 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
12846 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
12847 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
12848 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
12849 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
12850 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
12851 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
12852 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
12853 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
12854 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
12855 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
12856 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
12857 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
12858 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
12859 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
12860 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
12861 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
12862 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
12863 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
12864 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
12865 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
12866 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
12867 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
12868 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
12869 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
12870 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
12871 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
12872 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
12873 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
12874 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
12875 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
12876 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
12877 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
12878 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
12879 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
12880 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
12881 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
12882 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
12883 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
12884 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
12885 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
12886 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
12887 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
12888 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
12889 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
12890 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
12891 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
12892 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
12893 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
12894 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
12895 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
12896 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
12897 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
12898 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
12899 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
12900 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
12901 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 12902 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 12903 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 12904 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 12905 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 12906 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
12907 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
12908 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
12909 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 12910 | |
c19d1205 | 12911 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
12912 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
12913 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
12914 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
12915 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
12916 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
12917 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
12918 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
12919 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
12920 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
12921 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
12922 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
12923 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
12924 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
12925 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
12926 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
12927 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
12928 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
12929 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 12930 | |
c19d1205 | 12931 | /* Floating point variants -- don't add any more to this list either. */ |
e74cfd16 PB |
12932 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
12933 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
12934 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
12935 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 12936 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 12937 | |
e74cfd16 | 12938 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 12939 | }; |
7ed4c4c5 | 12940 | |
c19d1205 | 12941 | struct arm_cpu_option_table |
7ed4c4c5 | 12942 | { |
c19d1205 | 12943 | char *name; |
e74cfd16 | 12944 | const arm_feature_set value; |
c19d1205 ZW |
12945 | /* For some CPUs we assume an FPU unless the user explicitly sets |
12946 | -mfpu=... */ | |
e74cfd16 | 12947 | const arm_feature_set default_fpu; |
ee065d83 PB |
12948 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
12949 | case. */ | |
12950 | const char *canonical_name; | |
c19d1205 | 12951 | }; |
7ed4c4c5 | 12952 | |
c19d1205 ZW |
12953 | /* This list should, at a minimum, contain all the cpu names |
12954 | recognized by GCC. */ | |
e74cfd16 | 12955 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 12956 | { |
ee065d83 PB |
12957 | {"all", ARM_ANY, FPU_ARCH_FPA, NULL}, |
12958 | {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL}, | |
12959 | {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL}, | |
12960 | {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
12961 | {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
12962 | {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
12963 | {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
12964 | {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
12965 | {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
12966 | {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
12967 | {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
12968 | {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
12969 | {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
12970 | {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
12971 | {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
12972 | {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
12973 | {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
12974 | {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
12975 | {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
12976 | {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
12977 | {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
12978 | {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
12979 | {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
12980 | {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
12981 | {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
12982 | {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
12983 | {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
12984 | {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
12985 | {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
12986 | {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
12987 | {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
12988 | {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
12989 | {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
12990 | {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
12991 | {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
12992 | {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
12993 | {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
12994 | {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
12995 | {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
12996 | {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"}, | |
12997 | {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
12998 | {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
12999 | {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
13000 | {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
c19d1205 ZW |
13001 | /* For V5 or later processors we default to using VFP; but the user |
13002 | should really set the FPU type explicitly. */ | |
ee065d83 PB |
13003 | {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, |
13004 | {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
13005 | {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
13006 | {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
13007 | {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
13008 | {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
13009 | {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"}, | |
13010 | {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
13011 | {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
13012 | {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"}, | |
13013 | {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
13014 | {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
13015 | {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
13016 | {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
13017 | {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
13018 | {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"}, | |
13019 | {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
13020 | {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
13021 | {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
13022 | {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"}, | |
13023 | {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
13024 | {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"}, | |
13025 | {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL}, | |
13026 | {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"}, | |
13027 | {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL}, | |
13028 | {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL}, | |
13029 | {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL}, | |
13030 | {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL}, | |
13031 | {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL}, | |
13032 | {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL}, | |
13033 | {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL}, | |
c19d1205 | 13034 | /* ??? XSCALE is really an architecture. */ |
ee065d83 | 13035 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, |
c19d1205 | 13036 | /* ??? iwmmxt is not a processor. */ |
ee065d83 PB |
13037 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL}, |
13038 | {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, | |
c19d1205 | 13039 | /* Maverick */ |
e74cfd16 PB |
13040 | {"ep9312", ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"}, |
13041 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL} | |
c19d1205 | 13042 | }; |
7ed4c4c5 | 13043 | |
c19d1205 | 13044 | struct arm_arch_option_table |
7ed4c4c5 | 13045 | { |
c19d1205 | 13046 | char *name; |
e74cfd16 PB |
13047 | const arm_feature_set value; |
13048 | const arm_feature_set default_fpu; | |
c19d1205 | 13049 | }; |
7ed4c4c5 | 13050 | |
c19d1205 ZW |
13051 | /* This list should, at a minimum, contain all the architecture names |
13052 | recognized by GCC. */ | |
e74cfd16 | 13053 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 ZW |
13054 | { |
13055 | {"all", ARM_ANY, FPU_ARCH_FPA}, | |
13056 | {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, | |
13057 | {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, | |
13058 | {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
13059 | {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
13060 | {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
13061 | {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, | |
13062 | {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
13063 | {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, | |
13064 | {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
13065 | {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, | |
13066 | {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, | |
13067 | {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, | |
13068 | {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, | |
13069 | {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, | |
13070 | {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, | |
13071 | {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, | |
13072 | {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
13073 | {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
13074 | {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, | |
13075 | {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, | |
13076 | {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, | |
13077 | {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, | |
13078 | {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, | |
13079 | {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, | |
13080 | {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, | |
13081 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, | |
13082 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, | |
e74cfd16 | 13083 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} |
c19d1205 | 13084 | }; |
7ed4c4c5 | 13085 | |
c19d1205 | 13086 | /* ISA extensions in the co-processor space. */ |
e74cfd16 | 13087 | struct arm_option_cpu_value_table |
c19d1205 ZW |
13088 | { |
13089 | char *name; | |
e74cfd16 | 13090 | const arm_feature_set value; |
c19d1205 | 13091 | }; |
7ed4c4c5 | 13092 | |
e74cfd16 | 13093 | static const struct arm_option_cpu_value_table arm_extensions[] = |
c19d1205 | 13094 | { |
e74cfd16 PB |
13095 | {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)}, |
13096 | {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)}, | |
13097 | {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)}, | |
13098 | {NULL, ARM_ARCH_NONE} | |
c19d1205 | 13099 | }; |
7ed4c4c5 | 13100 | |
c19d1205 ZW |
13101 | /* This list should, at a minimum, contain all the fpu names |
13102 | recognized by GCC. */ | |
e74cfd16 | 13103 | static const struct arm_option_cpu_value_table arm_fpus[] = |
c19d1205 ZW |
13104 | { |
13105 | {"softfpa", FPU_NONE}, | |
13106 | {"fpe", FPU_ARCH_FPE}, | |
13107 | {"fpe2", FPU_ARCH_FPE}, | |
13108 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
13109 | {"fpa", FPU_ARCH_FPA}, | |
13110 | {"fpa10", FPU_ARCH_FPA}, | |
13111 | {"fpa11", FPU_ARCH_FPA}, | |
13112 | {"arm7500fe", FPU_ARCH_FPA}, | |
13113 | {"softvfp", FPU_ARCH_VFP}, | |
13114 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
13115 | {"vfp", FPU_ARCH_VFP_V2}, | |
13116 | {"vfp9", FPU_ARCH_VFP_V2}, | |
13117 | {"vfp10", FPU_ARCH_VFP_V2}, | |
13118 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
13119 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
13120 | {"arm1020t", FPU_ARCH_VFP_V1}, | |
13121 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
13122 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
13123 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
13124 | {"maverick", FPU_ARCH_MAVERICK}, | |
e74cfd16 PB |
13125 | {NULL, ARM_ARCH_NONE} |
13126 | }; | |
13127 | ||
13128 | struct arm_option_value_table | |
13129 | { | |
13130 | char *name; | |
13131 | long value; | |
c19d1205 | 13132 | }; |
7ed4c4c5 | 13133 | |
e74cfd16 | 13134 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
13135 | { |
13136 | {"hard", ARM_FLOAT_ABI_HARD}, | |
13137 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
13138 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 13139 | {NULL, 0} |
c19d1205 | 13140 | }; |
7ed4c4c5 | 13141 | |
c19d1205 ZW |
13142 | #ifdef OBJ_ELF |
13143 | /* We only know how to output GNU and ver 4 (AAELF) formats. */ | |
e74cfd16 | 13144 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
13145 | { |
13146 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
13147 | {"4", EF_ARM_EABI_VER4}, | |
e74cfd16 | 13148 | {NULL, 0} |
c19d1205 ZW |
13149 | }; |
13150 | #endif | |
7ed4c4c5 | 13151 | |
c19d1205 ZW |
13152 | struct arm_long_option_table |
13153 | { | |
13154 | char * option; /* Substring to match. */ | |
13155 | char * help; /* Help information. */ | |
13156 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
13157 | char * deprecated; /* If non-null, print this message. */ | |
13158 | }; | |
7ed4c4c5 NC |
13159 | |
13160 | static int | |
e74cfd16 | 13161 | arm_parse_extension (char * str, const arm_feature_set **opt_p) |
7ed4c4c5 | 13162 | { |
e74cfd16 PB |
13163 | arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set)); |
13164 | ||
13165 | /* Copy the feature set, so that we can modify it. */ | |
13166 | *ext_set = **opt_p; | |
13167 | *opt_p = ext_set; | |
13168 | ||
c19d1205 | 13169 | while (str != NULL && *str != 0) |
7ed4c4c5 | 13170 | { |
e74cfd16 | 13171 | const struct arm_option_cpu_value_table * opt; |
c19d1205 ZW |
13172 | char * ext; |
13173 | int optlen; | |
7ed4c4c5 | 13174 | |
c19d1205 ZW |
13175 | if (*str != '+') |
13176 | { | |
13177 | as_bad (_("invalid architectural extension")); | |
13178 | return 0; | |
13179 | } | |
7ed4c4c5 | 13180 | |
c19d1205 ZW |
13181 | str++; |
13182 | ext = strchr (str, '+'); | |
7ed4c4c5 | 13183 | |
c19d1205 ZW |
13184 | if (ext != NULL) |
13185 | optlen = ext - str; | |
13186 | else | |
13187 | optlen = strlen (str); | |
7ed4c4c5 | 13188 | |
c19d1205 ZW |
13189 | if (optlen == 0) |
13190 | { | |
13191 | as_bad (_("missing architectural extension")); | |
13192 | return 0; | |
13193 | } | |
7ed4c4c5 | 13194 | |
c19d1205 ZW |
13195 | for (opt = arm_extensions; opt->name != NULL; opt++) |
13196 | if (strncmp (opt->name, str, optlen) == 0) | |
13197 | { | |
e74cfd16 | 13198 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); |
c19d1205 ZW |
13199 | break; |
13200 | } | |
7ed4c4c5 | 13201 | |
c19d1205 ZW |
13202 | if (opt->name == NULL) |
13203 | { | |
13204 | as_bad (_("unknown architectural extnsion `%s'"), str); | |
13205 | return 0; | |
13206 | } | |
7ed4c4c5 | 13207 | |
c19d1205 ZW |
13208 | str = ext; |
13209 | }; | |
7ed4c4c5 | 13210 | |
c19d1205 ZW |
13211 | return 1; |
13212 | } | |
7ed4c4c5 | 13213 | |
c19d1205 ZW |
13214 | static int |
13215 | arm_parse_cpu (char * str) | |
7ed4c4c5 | 13216 | { |
e74cfd16 | 13217 | const struct arm_cpu_option_table * opt; |
c19d1205 ZW |
13218 | char * ext = strchr (str, '+'); |
13219 | int optlen; | |
7ed4c4c5 | 13220 | |
c19d1205 ZW |
13221 | if (ext != NULL) |
13222 | optlen = ext - str; | |
7ed4c4c5 | 13223 | else |
c19d1205 | 13224 | optlen = strlen (str); |
7ed4c4c5 | 13225 | |
c19d1205 | 13226 | if (optlen == 0) |
7ed4c4c5 | 13227 | { |
c19d1205 ZW |
13228 | as_bad (_("missing cpu name `%s'"), str); |
13229 | return 0; | |
7ed4c4c5 NC |
13230 | } |
13231 | ||
c19d1205 ZW |
13232 | for (opt = arm_cpus; opt->name != NULL; opt++) |
13233 | if (strncmp (opt->name, str, optlen) == 0) | |
13234 | { | |
e74cfd16 PB |
13235 | mcpu_cpu_opt = &opt->value; |
13236 | mcpu_fpu_opt = &opt->default_fpu; | |
ee065d83 PB |
13237 | if (opt->canonical_name) |
13238 | strcpy(selected_cpu_name, opt->canonical_name); | |
13239 | else | |
13240 | { | |
13241 | int i; | |
13242 | for (i = 0; i < optlen; i++) | |
13243 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
13244 | selected_cpu_name[i] = 0; | |
13245 | } | |
7ed4c4c5 | 13246 | |
c19d1205 ZW |
13247 | if (ext != NULL) |
13248 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 13249 | |
c19d1205 ZW |
13250 | return 1; |
13251 | } | |
7ed4c4c5 | 13252 | |
c19d1205 ZW |
13253 | as_bad (_("unknown cpu `%s'"), str); |
13254 | return 0; | |
7ed4c4c5 NC |
13255 | } |
13256 | ||
c19d1205 ZW |
13257 | static int |
13258 | arm_parse_arch (char * str) | |
7ed4c4c5 | 13259 | { |
e74cfd16 | 13260 | const struct arm_arch_option_table *opt; |
c19d1205 ZW |
13261 | char *ext = strchr (str, '+'); |
13262 | int optlen; | |
7ed4c4c5 | 13263 | |
c19d1205 ZW |
13264 | if (ext != NULL) |
13265 | optlen = ext - str; | |
7ed4c4c5 | 13266 | else |
c19d1205 | 13267 | optlen = strlen (str); |
7ed4c4c5 | 13268 | |
c19d1205 | 13269 | if (optlen == 0) |
7ed4c4c5 | 13270 | { |
c19d1205 ZW |
13271 | as_bad (_("missing architecture name `%s'"), str); |
13272 | return 0; | |
7ed4c4c5 NC |
13273 | } |
13274 | ||
c19d1205 ZW |
13275 | for (opt = arm_archs; opt->name != NULL; opt++) |
13276 | if (streq (opt->name, str)) | |
13277 | { | |
e74cfd16 PB |
13278 | march_cpu_opt = &opt->value; |
13279 | march_fpu_opt = &opt->default_fpu; | |
ee065d83 | 13280 | strcpy(selected_cpu_name, opt->name); |
7ed4c4c5 | 13281 | |
c19d1205 ZW |
13282 | if (ext != NULL) |
13283 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 13284 | |
c19d1205 ZW |
13285 | return 1; |
13286 | } | |
13287 | ||
13288 | as_bad (_("unknown architecture `%s'\n"), str); | |
13289 | return 0; | |
7ed4c4c5 | 13290 | } |
eb043451 | 13291 | |
c19d1205 ZW |
13292 | static int |
13293 | arm_parse_fpu (char * str) | |
13294 | { | |
e74cfd16 | 13295 | const struct arm_option_cpu_value_table * opt; |
b99bd4ef | 13296 | |
c19d1205 ZW |
13297 | for (opt = arm_fpus; opt->name != NULL; opt++) |
13298 | if (streq (opt->name, str)) | |
13299 | { | |
e74cfd16 | 13300 | mfpu_opt = &opt->value; |
c19d1205 ZW |
13301 | return 1; |
13302 | } | |
b99bd4ef | 13303 | |
c19d1205 ZW |
13304 | as_bad (_("unknown floating point format `%s'\n"), str); |
13305 | return 0; | |
13306 | } | |
13307 | ||
13308 | static int | |
13309 | arm_parse_float_abi (char * str) | |
b99bd4ef | 13310 | { |
e74cfd16 | 13311 | const struct arm_option_value_table * opt; |
b99bd4ef | 13312 | |
c19d1205 ZW |
13313 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
13314 | if (streq (opt->name, str)) | |
13315 | { | |
13316 | mfloat_abi_opt = opt->value; | |
13317 | return 1; | |
13318 | } | |
cc8a6dd0 | 13319 | |
c19d1205 ZW |
13320 | as_bad (_("unknown floating point abi `%s'\n"), str); |
13321 | return 0; | |
13322 | } | |
b99bd4ef | 13323 | |
c19d1205 ZW |
13324 | #ifdef OBJ_ELF |
13325 | static int | |
13326 | arm_parse_eabi (char * str) | |
13327 | { | |
e74cfd16 | 13328 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 13329 | |
c19d1205 ZW |
13330 | for (opt = arm_eabis; opt->name != NULL; opt++) |
13331 | if (streq (opt->name, str)) | |
13332 | { | |
13333 | meabi_flags = opt->value; | |
13334 | return 1; | |
13335 | } | |
13336 | as_bad (_("unknown EABI `%s'\n"), str); | |
13337 | return 0; | |
13338 | } | |
13339 | #endif | |
cc8a6dd0 | 13340 | |
c19d1205 ZW |
13341 | struct arm_long_option_table arm_long_opts[] = |
13342 | { | |
13343 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
13344 | arm_parse_cpu, NULL}, | |
13345 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
13346 | arm_parse_arch, NULL}, | |
13347 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
13348 | arm_parse_fpu, NULL}, | |
13349 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
13350 | arm_parse_float_abi, NULL}, | |
13351 | #ifdef OBJ_ELF | |
13352 | {"meabi=", N_("<ver>\t assemble for eabi version <ver>"), | |
13353 | arm_parse_eabi, NULL}, | |
13354 | #endif | |
13355 | {NULL, NULL, 0, NULL} | |
13356 | }; | |
cc8a6dd0 | 13357 | |
c19d1205 ZW |
13358 | int |
13359 | md_parse_option (int c, char * arg) | |
13360 | { | |
13361 | struct arm_option_table *opt; | |
e74cfd16 | 13362 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 13363 | struct arm_long_option_table *lopt; |
b99bd4ef | 13364 | |
c19d1205 | 13365 | switch (c) |
b99bd4ef | 13366 | { |
c19d1205 ZW |
13367 | #ifdef OPTION_EB |
13368 | case OPTION_EB: | |
13369 | target_big_endian = 1; | |
13370 | break; | |
13371 | #endif | |
cc8a6dd0 | 13372 | |
c19d1205 ZW |
13373 | #ifdef OPTION_EL |
13374 | case OPTION_EL: | |
13375 | target_big_endian = 0; | |
13376 | break; | |
13377 | #endif | |
b99bd4ef | 13378 | |
c19d1205 ZW |
13379 | case 'a': |
13380 | /* Listing option. Just ignore these, we don't support additional | |
13381 | ones. */ | |
13382 | return 0; | |
b99bd4ef | 13383 | |
c19d1205 ZW |
13384 | default: |
13385 | for (opt = arm_opts; opt->option != NULL; opt++) | |
13386 | { | |
13387 | if (c == opt->option[0] | |
13388 | && ((arg == NULL && opt->option[1] == 0) | |
13389 | || streq (arg, opt->option + 1))) | |
13390 | { | |
13391 | #if WARN_DEPRECATED | |
13392 | /* If the option is deprecated, tell the user. */ | |
13393 | if (opt->deprecated != NULL) | |
13394 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, | |
13395 | arg ? arg : "", _(opt->deprecated)); | |
13396 | #endif | |
b99bd4ef | 13397 | |
c19d1205 ZW |
13398 | if (opt->var != NULL) |
13399 | *opt->var = opt->value; | |
cc8a6dd0 | 13400 | |
c19d1205 ZW |
13401 | return 1; |
13402 | } | |
13403 | } | |
b99bd4ef | 13404 | |
e74cfd16 PB |
13405 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
13406 | { | |
13407 | if (c == fopt->option[0] | |
13408 | && ((arg == NULL && fopt->option[1] == 0) | |
13409 | || streq (arg, fopt->option + 1))) | |
13410 | { | |
13411 | #if WARN_DEPRECATED | |
13412 | /* If the option is deprecated, tell the user. */ | |
13413 | if (fopt->deprecated != NULL) | |
13414 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, | |
13415 | arg ? arg : "", _(fopt->deprecated)); | |
13416 | #endif | |
13417 | ||
13418 | if (fopt->var != NULL) | |
13419 | *fopt->var = &fopt->value; | |
13420 | ||
13421 | return 1; | |
13422 | } | |
13423 | } | |
13424 | ||
c19d1205 ZW |
13425 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
13426 | { | |
13427 | /* These options are expected to have an argument. */ | |
13428 | if (c == lopt->option[0] | |
13429 | && arg != NULL | |
13430 | && strncmp (arg, lopt->option + 1, | |
13431 | strlen (lopt->option + 1)) == 0) | |
13432 | { | |
13433 | #if WARN_DEPRECATED | |
13434 | /* If the option is deprecated, tell the user. */ | |
13435 | if (lopt->deprecated != NULL) | |
13436 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, | |
13437 | _(lopt->deprecated)); | |
13438 | #endif | |
b99bd4ef | 13439 | |
c19d1205 ZW |
13440 | /* Call the sup-option parser. */ |
13441 | return lopt->func (arg + strlen (lopt->option) - 1); | |
13442 | } | |
13443 | } | |
a737bd4d | 13444 | |
c19d1205 ZW |
13445 | return 0; |
13446 | } | |
a394c00f | 13447 | |
c19d1205 ZW |
13448 | return 1; |
13449 | } | |
a394c00f | 13450 | |
c19d1205 ZW |
13451 | void |
13452 | md_show_usage (FILE * fp) | |
a394c00f | 13453 | { |
c19d1205 ZW |
13454 | struct arm_option_table *opt; |
13455 | struct arm_long_option_table *lopt; | |
a394c00f | 13456 | |
c19d1205 | 13457 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 13458 | |
c19d1205 ZW |
13459 | for (opt = arm_opts; opt->option != NULL; opt++) |
13460 | if (opt->help != NULL) | |
13461 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 13462 | |
c19d1205 ZW |
13463 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
13464 | if (lopt->help != NULL) | |
13465 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 13466 | |
c19d1205 ZW |
13467 | #ifdef OPTION_EB |
13468 | fprintf (fp, _("\ | |
13469 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
13470 | #endif |
13471 | ||
c19d1205 ZW |
13472 | #ifdef OPTION_EL |
13473 | fprintf (fp, _("\ | |
13474 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 13475 | #endif |
c19d1205 | 13476 | } |
ee065d83 PB |
13477 | |
13478 | ||
13479 | #ifdef OBJ_ELF | |
13480 | /* Set the public EABI object attributes. */ | |
13481 | static void | |
13482 | aeabi_set_public_attributes (void) | |
13483 | { | |
13484 | int arch; | |
e74cfd16 | 13485 | arm_feature_set flags; |
ee065d83 PB |
13486 | |
13487 | /* Choose the architecture based on the capabilities of the requested cpu | |
13488 | (if any) and/or the instructions actually used. */ | |
e74cfd16 PB |
13489 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); |
13490 | ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); | |
13491 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); | |
13492 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v6t2)) | |
ee065d83 | 13493 | arch = 8; |
e74cfd16 | 13494 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v6z)) |
ee065d83 | 13495 | arch = 7; |
e74cfd16 | 13496 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v6k)) |
ee065d83 | 13497 | arch = 9; |
e74cfd16 | 13498 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v6)) |
ee065d83 | 13499 | arch = 6; |
e74cfd16 | 13500 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v5e)) |
ee065d83 | 13501 | arch = 4; |
e74cfd16 PB |
13502 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v5) |
13503 | || ARM_CPU_HAS_FEATURE (flags, arm_ext_v5t)) | |
ee065d83 | 13504 | arch = 3; |
e74cfd16 | 13505 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)) |
ee065d83 | 13506 | arch = 2; |
e74cfd16 | 13507 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4)) |
ee065d83 PB |
13508 | arch = 1; |
13509 | else | |
13510 | arch = 0; | |
13511 | ||
13512 | /* Tag_CPU_name. */ | |
13513 | if (selected_cpu_name[0]) | |
13514 | { | |
13515 | char *p; | |
13516 | ||
13517 | p = selected_cpu_name; | |
13518 | if (strncmp(p, "armv", 4) == 0) | |
13519 | { | |
13520 | int i; | |
13521 | ||
13522 | p += 4; | |
13523 | for (i = 0; p[i]; i++) | |
13524 | p[i] = TOUPPER (p[i]); | |
13525 | } | |
13526 | elf32_arm_add_eabi_attr_string (stdoutput, 5, p); | |
13527 | } | |
13528 | /* Tag_CPU_arch. */ | |
13529 | elf32_arm_add_eabi_attr_int (stdoutput, 6, arch); | |
13530 | /* Tag_ARM_ISA_use. */ | |
e74cfd16 | 13531 | if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full)) |
ee065d83 PB |
13532 | elf32_arm_add_eabi_attr_int (stdoutput, 8, 1); |
13533 | /* Tag_THUMB_ISA_use. */ | |
e74cfd16 | 13534 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full)) |
ee065d83 | 13535 | elf32_arm_add_eabi_attr_int (stdoutput, 9, |
e74cfd16 | 13536 | ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1); |
ee065d83 | 13537 | /* Tag_VFP_arch. */ |
e74cfd16 PB |
13538 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v2) |
13539 | || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v2)) | |
ee065d83 | 13540 | elf32_arm_add_eabi_attr_int (stdoutput, 10, 2); |
e74cfd16 PB |
13541 | else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v1) |
13542 | || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v1)) | |
ee065d83 PB |
13543 | elf32_arm_add_eabi_attr_int (stdoutput, 10, 1); |
13544 | /* Tag_WMMX_arch. */ | |
e74cfd16 PB |
13545 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt) |
13546 | || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt)) | |
ee065d83 PB |
13547 | elf32_arm_add_eabi_attr_int (stdoutput, 11, 1); |
13548 | } | |
13549 | ||
13550 | /* Add the .ARM.attributes section. */ | |
13551 | void | |
13552 | arm_md_end (void) | |
13553 | { | |
13554 | segT s; | |
13555 | char *p; | |
13556 | addressT addr; | |
13557 | offsetT size; | |
13558 | ||
13559 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) | |
13560 | return; | |
13561 | ||
13562 | aeabi_set_public_attributes (); | |
13563 | size = elf32_arm_eabi_attr_size (stdoutput); | |
13564 | s = subseg_new (".ARM.attributes", 0); | |
13565 | bfd_set_section_flags (stdoutput, s, SEC_READONLY | SEC_DATA); | |
13566 | addr = frag_now_fix (); | |
13567 | p = frag_more (size); | |
13568 | elf32_arm_set_eabi_attr_contents (stdoutput, (bfd_byte *)p, size); | |
13569 | } | |
13570 | ||
13571 | ||
13572 | /* Parse a .cpu directive. */ | |
13573 | ||
13574 | static void | |
13575 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
13576 | { | |
e74cfd16 | 13577 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
13578 | char *name; |
13579 | char saved_char; | |
13580 | ||
13581 | name = input_line_pointer; | |
13582 | while (*input_line_pointer && !ISSPACE(*input_line_pointer)) | |
13583 | input_line_pointer++; | |
13584 | saved_char = *input_line_pointer; | |
13585 | *input_line_pointer = 0; | |
13586 | ||
13587 | /* Skip the first "all" entry. */ | |
13588 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
13589 | if (streq (opt->name, name)) | |
13590 | { | |
e74cfd16 PB |
13591 | mcpu_cpu_opt = &opt->value; |
13592 | selected_cpu = opt->value; | |
ee065d83 PB |
13593 | if (opt->canonical_name) |
13594 | strcpy(selected_cpu_name, opt->canonical_name); | |
13595 | else | |
13596 | { | |
13597 | int i; | |
13598 | for (i = 0; opt->name[i]; i++) | |
13599 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
13600 | selected_cpu_name[i] = 0; | |
13601 | } | |
e74cfd16 | 13602 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
13603 | *input_line_pointer = saved_char; |
13604 | demand_empty_rest_of_line (); | |
13605 | return; | |
13606 | } | |
13607 | as_bad (_("unknown cpu `%s'"), name); | |
13608 | *input_line_pointer = saved_char; | |
13609 | ignore_rest_of_line (); | |
13610 | } | |
13611 | ||
13612 | ||
13613 | /* Parse a .arch directive. */ | |
13614 | ||
13615 | static void | |
13616 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
13617 | { | |
e74cfd16 | 13618 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
13619 | char saved_char; |
13620 | char *name; | |
13621 | ||
13622 | name = input_line_pointer; | |
13623 | while (*input_line_pointer && !ISSPACE(*input_line_pointer)) | |
13624 | input_line_pointer++; | |
13625 | saved_char = *input_line_pointer; | |
13626 | *input_line_pointer = 0; | |
13627 | ||
13628 | /* Skip the first "all" entry. */ | |
13629 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
13630 | if (streq (opt->name, name)) | |
13631 | { | |
e74cfd16 PB |
13632 | mcpu_cpu_opt = &opt->value; |
13633 | selected_cpu = opt->value; | |
ee065d83 | 13634 | strcpy(selected_cpu_name, opt->name); |
e74cfd16 | 13635 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
13636 | *input_line_pointer = saved_char; |
13637 | demand_empty_rest_of_line (); | |
13638 | return; | |
13639 | } | |
13640 | ||
13641 | as_bad (_("unknown architecture `%s'\n"), name); | |
13642 | *input_line_pointer = saved_char; | |
13643 | ignore_rest_of_line (); | |
13644 | } | |
13645 | ||
13646 | ||
13647 | /* Parse a .fpu directive. */ | |
13648 | ||
13649 | static void | |
13650 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
13651 | { | |
e74cfd16 | 13652 | const struct arm_option_cpu_value_table *opt; |
ee065d83 PB |
13653 | char saved_char; |
13654 | char *name; | |
13655 | ||
13656 | name = input_line_pointer; | |
13657 | while (*input_line_pointer && !ISSPACE(*input_line_pointer)) | |
13658 | input_line_pointer++; | |
13659 | saved_char = *input_line_pointer; | |
13660 | *input_line_pointer = 0; | |
13661 | ||
13662 | for (opt = arm_fpus; opt->name != NULL; opt++) | |
13663 | if (streq (opt->name, name)) | |
13664 | { | |
e74cfd16 PB |
13665 | mfpu_opt = &opt->value; |
13666 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
ee065d83 PB |
13667 | *input_line_pointer = saved_char; |
13668 | demand_empty_rest_of_line (); | |
13669 | return; | |
13670 | } | |
13671 | ||
13672 | as_bad (_("unknown floating point format `%s'\n"), name); | |
13673 | *input_line_pointer = saved_char; | |
13674 | ignore_rest_of_line (); | |
13675 | } | |
13676 | #endif /* OBJ_ELF */ | |
13677 |