Commit | Line | Data |
---|---|---|
07c1b327 | 1 | /* tc-bfin.c -- Assembler for the ADI Blackfin. |
aa820537 | 2 | Copyright 2005, 2006, 2007, 2008, 2009 |
07c1b327 CM |
3 | Free Software Foundation, Inc. |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
07c1b327 CM |
10 | any later version. |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA | |
20 | 02110-1301, USA. */ | |
21 | ||
22 | #include "as.h" | |
23 | #include "struc-symbol.h" | |
07c1b327 CM |
24 | #include "bfin-defs.h" |
25 | #include "obstack.h" | |
26 | #include "safe-ctype.h" | |
27 | #ifdef OBJ_ELF | |
28 | #include "dwarf2dbg.h" | |
29 | #endif | |
1ac4baed BS |
30 | #include "libbfd.h" |
31 | #include "elf/common.h" | |
32 | #include "elf/bfin.h" | |
07c1b327 CM |
33 | |
34 | extern int yyparse (void); | |
35 | struct yy_buffer_state; | |
36 | typedef struct yy_buffer_state *YY_BUFFER_STATE; | |
37 | extern YY_BUFFER_STATE yy_scan_string (const char *yy_str); | |
38 | extern void yy_delete_buffer (YY_BUFFER_STATE b); | |
39 | static parse_state parse (char *line); | |
07c1b327 CM |
40 | |
41 | /* Global variables. */ | |
42 | struct bfin_insn *insn; | |
43 | int last_insn_size; | |
44 | ||
45 | extern struct obstack mempool; | |
46 | FILE *errorf; | |
47 | ||
1ac4baed BS |
48 | /* Flags to set in the elf header */ |
49 | #define DEFAULT_FLAGS 0 | |
50 | ||
fe4fa32c MF |
51 | #ifdef OBJ_FDPIC_ELF |
52 | # define DEFAULT_FDPIC EF_BFIN_FDPIC | |
53 | #else | |
54 | # define DEFAULT_FDPIC 0 | |
55 | #endif | |
56 | ||
57 | static flagword bfin_flags = DEFAULT_FLAGS | DEFAULT_FDPIC; | |
58 | static const char *bfin_pic_flag = DEFAULT_FDPIC ? "-mfdpic" : (const char *)0; | |
1ac4baed | 59 | |
1ac4baed BS |
60 | /* Blackfin specific function to handle FD-PIC pointer initializations. */ |
61 | ||
62 | static void | |
63 | bfin_pic_ptr (int nbytes) | |
64 | { | |
65 | expressionS exp; | |
66 | char *p; | |
67 | ||
68 | if (nbytes != 4) | |
69 | abort (); | |
70 | ||
71 | #ifdef md_flush_pending_output | |
72 | md_flush_pending_output (); | |
73 | #endif | |
74 | ||
75 | if (is_it_end_of_statement ()) | |
76 | { | |
77 | demand_empty_rest_of_line (); | |
78 | return; | |
79 | } | |
80 | ||
81 | #ifdef md_cons_align | |
82 | md_cons_align (nbytes); | |
83 | #endif | |
84 | ||
85 | do | |
86 | { | |
87 | bfd_reloc_code_real_type reloc_type = BFD_RELOC_BFIN_FUNCDESC; | |
88 | ||
89 | if (strncasecmp (input_line_pointer, "funcdesc(", 9) == 0) | |
90 | { | |
91 | input_line_pointer += 9; | |
92 | expression (&exp); | |
93 | if (*input_line_pointer == ')') | |
94 | input_line_pointer++; | |
95 | else | |
bd3ba5d1 | 96 | as_bad (_("missing ')'")); |
1ac4baed BS |
97 | } |
98 | else | |
99 | error ("missing funcdesc in picptr"); | |
100 | ||
101 | p = frag_more (4); | |
102 | memset (p, 0, 4); | |
103 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &exp, 0, | |
104 | reloc_type); | |
105 | } | |
106 | while (*input_line_pointer++ == ','); | |
107 | ||
108 | input_line_pointer--; /* Put terminator back into stream. */ | |
109 | demand_empty_rest_of_line (); | |
110 | } | |
111 | ||
112 | static void | |
113 | bfin_s_bss (int ignore ATTRIBUTE_UNUSED) | |
114 | { | |
115 | register int temp; | |
116 | ||
117 | temp = get_absolute_expression (); | |
118 | subseg_set (bss_section, (subsegT) temp); | |
119 | demand_empty_rest_of_line (); | |
120 | } | |
07c1b327 CM |
121 | |
122 | const pseudo_typeS md_pseudo_table[] = { | |
123 | {"align", s_align_bytes, 0}, | |
124 | {"byte2", cons, 2}, | |
125 | {"byte4", cons, 4}, | |
1ac4baed | 126 | {"picptr", bfin_pic_ptr, 4}, |
07c1b327 CM |
127 | {"code", obj_elf_section, 0}, |
128 | {"db", cons, 1}, | |
129 | {"dd", cons, 4}, | |
130 | {"dw", cons, 2}, | |
131 | {"p", s_ignore, 0}, | |
132 | {"pdata", s_ignore, 0}, | |
133 | {"var", s_ignore, 0}, | |
134 | {"bss", bfin_s_bss, 0}, | |
135 | {0, 0, 0} | |
136 | }; | |
137 | ||
07c1b327 CM |
138 | /* Characters that are used to denote comments and line separators. */ |
139 | const char comment_chars[] = ""; | |
140 | const char line_comment_chars[] = "#"; | |
141 | const char line_separator_chars[] = ";"; | |
142 | ||
143 | /* Characters that can be used to separate the mantissa from the | |
144 | exponent in floating point numbers. */ | |
145 | const char EXP_CHARS[] = "eE"; | |
146 | ||
147 | /* Characters that mean this number is a floating point constant. | |
148 | As in 0f12.456 or 0d1.2345e12. */ | |
149 | const char FLT_CHARS[] = "fFdDxX"; | |
150 | ||
6306cd85 BS |
151 | typedef enum bfin_cpu_type |
152 | { | |
153 | BFIN_CPU_UNKNOWN, | |
154 | BFIN_CPU_BF512, | |
155 | BFIN_CPU_BF514, | |
156 | BFIN_CPU_BF516, | |
157 | BFIN_CPU_BF518, | |
158 | BFIN_CPU_BF522, | |
159 | BFIN_CPU_BF523, | |
160 | BFIN_CPU_BF524, | |
161 | BFIN_CPU_BF525, | |
162 | BFIN_CPU_BF526, | |
163 | BFIN_CPU_BF527, | |
164 | BFIN_CPU_BF531, | |
165 | BFIN_CPU_BF532, | |
166 | BFIN_CPU_BF533, | |
167 | BFIN_CPU_BF534, | |
168 | BFIN_CPU_BF536, | |
169 | BFIN_CPU_BF537, | |
170 | BFIN_CPU_BF538, | |
171 | BFIN_CPU_BF539, | |
172 | BFIN_CPU_BF542, | |
173 | BFIN_CPU_BF542M, | |
174 | BFIN_CPU_BF544, | |
175 | BFIN_CPU_BF544M, | |
176 | BFIN_CPU_BF547, | |
177 | BFIN_CPU_BF547M, | |
178 | BFIN_CPU_BF548, | |
179 | BFIN_CPU_BF548M, | |
180 | BFIN_CPU_BF549, | |
181 | BFIN_CPU_BF549M, | |
182 | BFIN_CPU_BF561 | |
183 | } bfin_cpu_t; | |
184 | ||
185 | bfin_cpu_t bfin_cpu_type = BFIN_CPU_UNKNOWN; | |
186 | /* -msi-revision support. There are three special values: | |
187 | -1 -msi-revision=none. | |
188 | 0xffff -msi-revision=any. */ | |
189 | int bfin_si_revision; | |
190 | ||
191 | unsigned int bfin_anomaly_checks = 0; | |
192 | ||
193 | struct bfin_cpu | |
194 | { | |
195 | const char *name; | |
196 | bfin_cpu_t type; | |
197 | int si_revision; | |
198 | unsigned int anomaly_checks; | |
199 | }; | |
200 | ||
201 | struct bfin_cpu bfin_cpus[] = | |
202 | { | |
203 | {"bf512", BFIN_CPU_BF512, 0x0001, AC_05000074}, | |
204 | {"bf512", BFIN_CPU_BF512, 0x0000, AC_05000074}, | |
205 | ||
206 | {"bf514", BFIN_CPU_BF514, 0x0001, AC_05000074}, | |
207 | {"bf514", BFIN_CPU_BF514, 0x0000, AC_05000074}, | |
208 | ||
209 | {"bf516", BFIN_CPU_BF516, 0x0001, AC_05000074}, | |
210 | {"bf516", BFIN_CPU_BF516, 0x0000, AC_05000074}, | |
211 | ||
212 | {"bf518", BFIN_CPU_BF518, 0x0001, AC_05000074}, | |
213 | {"bf518", BFIN_CPU_BF518, 0x0000, AC_05000074}, | |
214 | ||
215 | {"bf522", BFIN_CPU_BF522, 0x0002, AC_05000074}, | |
216 | {"bf522", BFIN_CPU_BF522, 0x0001, AC_05000074}, | |
217 | {"bf522", BFIN_CPU_BF522, 0x0000, AC_05000074}, | |
218 | ||
219 | {"bf523", BFIN_CPU_BF523, 0x0002, AC_05000074}, | |
220 | {"bf523", BFIN_CPU_BF523, 0x0001, AC_05000074}, | |
221 | {"bf523", BFIN_CPU_BF523, 0x0000, AC_05000074}, | |
222 | ||
223 | {"bf524", BFIN_CPU_BF524, 0x0002, AC_05000074}, | |
224 | {"bf524", BFIN_CPU_BF524, 0x0001, AC_05000074}, | |
225 | {"bf524", BFIN_CPU_BF524, 0x0000, AC_05000074}, | |
226 | ||
227 | {"bf525", BFIN_CPU_BF525, 0x0002, AC_05000074}, | |
228 | {"bf525", BFIN_CPU_BF525, 0x0001, AC_05000074}, | |
229 | {"bf525", BFIN_CPU_BF525, 0x0000, AC_05000074}, | |
230 | ||
231 | {"bf526", BFIN_CPU_BF526, 0x0002, AC_05000074}, | |
232 | {"bf526", BFIN_CPU_BF526, 0x0001, AC_05000074}, | |
233 | {"bf526", BFIN_CPU_BF526, 0x0000, AC_05000074}, | |
234 | ||
235 | {"bf527", BFIN_CPU_BF527, 0x0002, AC_05000074}, | |
236 | {"bf527", BFIN_CPU_BF527, 0x0001, AC_05000074}, | |
237 | {"bf527", BFIN_CPU_BF527, 0x0000, AC_05000074}, | |
238 | ||
239 | {"bf531", BFIN_CPU_BF531, 0x0006, AC_05000074}, | |
240 | {"bf531", BFIN_CPU_BF531, 0x0005, AC_05000074}, | |
241 | {"bf531", BFIN_CPU_BF531, 0x0004, AC_05000074}, | |
242 | {"bf531", BFIN_CPU_BF531, 0x0003, AC_05000074}, | |
243 | ||
244 | {"bf532", BFIN_CPU_BF532, 0x0006, AC_05000074}, | |
245 | {"bf532", BFIN_CPU_BF532, 0x0005, AC_05000074}, | |
246 | {"bf532", BFIN_CPU_BF532, 0x0004, AC_05000074}, | |
247 | {"bf532", BFIN_CPU_BF532, 0x0003, AC_05000074}, | |
248 | ||
249 | {"bf533", BFIN_CPU_BF533, 0x0006, AC_05000074}, | |
250 | {"bf533", BFIN_CPU_BF533, 0x0005, AC_05000074}, | |
251 | {"bf533", BFIN_CPU_BF533, 0x0004, AC_05000074}, | |
252 | {"bf533", BFIN_CPU_BF533, 0x0003, AC_05000074}, | |
253 | ||
254 | {"bf534", BFIN_CPU_BF534, 0x0003, AC_05000074}, | |
255 | {"bf534", BFIN_CPU_BF534, 0x0002, AC_05000074}, | |
256 | {"bf534", BFIN_CPU_BF534, 0x0001, AC_05000074}, | |
257 | ||
258 | {"bf536", BFIN_CPU_BF536, 0x0003, AC_05000074}, | |
259 | {"bf536", BFIN_CPU_BF536, 0x0002, AC_05000074}, | |
260 | {"bf536", BFIN_CPU_BF536, 0x0001, AC_05000074}, | |
261 | ||
262 | {"bf537", BFIN_CPU_BF537, 0x0003, AC_05000074}, | |
263 | {"bf537", BFIN_CPU_BF537, 0x0002, AC_05000074}, | |
264 | {"bf537", BFIN_CPU_BF537, 0x0001, AC_05000074}, | |
265 | ||
266 | {"bf538", BFIN_CPU_BF538, 0x0005, AC_05000074}, | |
267 | {"bf538", BFIN_CPU_BF538, 0x0004, AC_05000074}, | |
268 | {"bf538", BFIN_CPU_BF538, 0x0003, AC_05000074}, | |
269 | {"bf538", BFIN_CPU_BF538, 0x0002, AC_05000074}, | |
270 | ||
271 | {"bf539", BFIN_CPU_BF539, 0x0005, AC_05000074}, | |
272 | {"bf539", BFIN_CPU_BF539, 0x0004, AC_05000074}, | |
273 | {"bf539", BFIN_CPU_BF539, 0x0003, AC_05000074}, | |
274 | {"bf539", BFIN_CPU_BF539, 0x0002, AC_05000074}, | |
275 | ||
276 | {"bf542m", BFIN_CPU_BF542M, 0x0003, AC_05000074}, | |
277 | ||
278 | {"bf542", BFIN_CPU_BF542, 0x0002, AC_05000074}, | |
279 | {"bf542", BFIN_CPU_BF542, 0x0001, AC_05000074}, | |
280 | {"bf542", BFIN_CPU_BF542, 0x0000, AC_05000074}, | |
281 | ||
282 | {"bf544m", BFIN_CPU_BF544M, 0x0003, AC_05000074}, | |
283 | ||
284 | {"bf544", BFIN_CPU_BF544, 0x0002, AC_05000074}, | |
285 | {"bf544", BFIN_CPU_BF544, 0x0001, AC_05000074}, | |
286 | {"bf544", BFIN_CPU_BF544, 0x0000, AC_05000074}, | |
287 | ||
288 | {"bf547m", BFIN_CPU_BF547M, 0x0003, AC_05000074}, | |
289 | ||
290 | {"bf547", BFIN_CPU_BF547, 0x0002, AC_05000074}, | |
291 | {"bf547", BFIN_CPU_BF547, 0x0001, AC_05000074}, | |
292 | {"bf547", BFIN_CPU_BF547, 0x0000, AC_05000074}, | |
293 | ||
294 | {"bf548m", BFIN_CPU_BF548M, 0x0003, AC_05000074}, | |
295 | ||
296 | {"bf548", BFIN_CPU_BF548, 0x0002, AC_05000074}, | |
297 | {"bf548", BFIN_CPU_BF548, 0x0001, AC_05000074}, | |
298 | {"bf548", BFIN_CPU_BF548, 0x0000, AC_05000074}, | |
299 | ||
300 | {"bf549m", BFIN_CPU_BF549M, 0x0003, AC_05000074}, | |
301 | ||
302 | {"bf549", BFIN_CPU_BF549, 0x0002, AC_05000074}, | |
303 | {"bf549", BFIN_CPU_BF549, 0x0001, AC_05000074}, | |
304 | {"bf549", BFIN_CPU_BF549, 0x0000, AC_05000074}, | |
305 | ||
306 | {"bf561", BFIN_CPU_BF561, 0x0005, AC_05000074}, | |
307 | {"bf561", BFIN_CPU_BF561, 0x0003, AC_05000074}, | |
308 | {"bf561", BFIN_CPU_BF561, 0x0002, AC_05000074}, | |
309 | ||
310 | {NULL, 0, 0, 0} | |
311 | }; | |
312 | ||
07c1b327 CM |
313 | /* Define bfin-specific command-line options (there are none). */ |
314 | const char *md_shortopts = ""; | |
315 | ||
1ac4baed | 316 | #define OPTION_FDPIC (OPTION_MD_BASE) |
fe4fa32c | 317 | #define OPTION_NOPIC (OPTION_MD_BASE + 1) |
6306cd85 | 318 | #define OPTION_MCPU (OPTION_MD_BASE + 2) |
1ac4baed BS |
319 | |
320 | struct option md_longopts[] = | |
321 | { | |
6306cd85 | 322 | { "mcpu", required_argument, NULL, OPTION_MCPU }, |
fe4fa32c MF |
323 | { "mfdpic", no_argument, NULL, OPTION_FDPIC }, |
324 | { "mnopic", no_argument, NULL, OPTION_NOPIC }, | |
325 | { "mno-fdpic", no_argument, NULL, OPTION_NOPIC }, | |
1ac4baed | 326 | { NULL, no_argument, NULL, 0 }, |
07c1b327 | 327 | }; |
1ac4baed | 328 | |
07c1b327 CM |
329 | size_t md_longopts_size = sizeof (md_longopts); |
330 | ||
331 | ||
332 | int | |
333 | md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED) | |
334 | { | |
1ac4baed BS |
335 | switch (c) |
336 | { | |
337 | default: | |
338 | return 0; | |
339 | ||
6306cd85 BS |
340 | case OPTION_MCPU: |
341 | { | |
342 | const char *p, *q; | |
343 | int i; | |
344 | ||
345 | i = 0; | |
346 | while ((p = bfin_cpus[i].name) != NULL) | |
347 | { | |
348 | if (strncmp (arg, p, strlen (p)) == 0) | |
349 | break; | |
350 | i++; | |
351 | } | |
352 | ||
353 | if (p == NULL) | |
354 | { | |
355 | error ("-mcpu=%s is not valid", arg); | |
356 | return 0; | |
357 | } | |
358 | ||
359 | bfin_cpu_type = bfin_cpus[i].type; | |
360 | ||
361 | q = arg + strlen (p); | |
362 | ||
363 | if (*q == '\0') | |
364 | { | |
365 | bfin_si_revision = bfin_cpus[i].si_revision; | |
366 | bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks; | |
367 | } | |
368 | else if (strcmp (q, "-none") == 0) | |
369 | bfin_si_revision = -1; | |
370 | else if (strcmp (q, "-any") == 0) | |
371 | { | |
372 | bfin_si_revision = 0xffff; | |
373 | while (bfin_cpus[i].type == bfin_cpu_type) | |
374 | { | |
375 | bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks; | |
376 | i++; | |
377 | } | |
378 | } | |
379 | else | |
380 | { | |
381 | unsigned int si_major, si_minor; | |
382 | int rev_len, n; | |
383 | ||
384 | rev_len = strlen (q); | |
385 | ||
386 | if (sscanf (q, "-%u.%u%n", &si_major, &si_minor, &n) != 2 | |
387 | || n != rev_len | |
388 | || si_major > 0xff || si_minor > 0xff) | |
389 | { | |
390 | invalid_silicon_revision: | |
391 | error ("-mcpu=%s has invalid silicon revision", arg); | |
392 | return 0; | |
393 | } | |
394 | ||
395 | bfin_si_revision = (si_major << 8) | si_minor; | |
396 | ||
397 | while (bfin_cpus[i].type == bfin_cpu_type | |
398 | && bfin_cpus[i].si_revision != bfin_si_revision) | |
399 | i++; | |
400 | ||
401 | if (bfin_cpus[i].type != bfin_cpu_type) | |
402 | goto invalid_silicon_revision; | |
403 | ||
404 | bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks; | |
405 | } | |
406 | ||
407 | break; | |
408 | } | |
409 | ||
1ac4baed BS |
410 | case OPTION_FDPIC: |
411 | bfin_flags |= EF_BFIN_FDPIC; | |
412 | bfin_pic_flag = "-mfdpic"; | |
413 | break; | |
fe4fa32c MF |
414 | |
415 | case OPTION_NOPIC: | |
416 | bfin_flags &= ~(EF_BFIN_FDPIC); | |
417 | bfin_pic_flag = 0; | |
418 | break; | |
1ac4baed BS |
419 | } |
420 | ||
421 | return 1; | |
07c1b327 CM |
422 | } |
423 | ||
424 | void | |
425 | md_show_usage (FILE * stream ATTRIBUTE_UNUSED) | |
426 | { | |
427 | fprintf (stream, _(" BFIN specific command line options:\n")); | |
428 | } | |
429 | ||
430 | /* Perform machine-specific initializations. */ | |
431 | void | |
432 | md_begin () | |
433 | { | |
1ac4baed BS |
434 | /* Set the ELF flags if desired. */ |
435 | if (bfin_flags) | |
436 | bfd_set_private_flags (stdoutput, bfin_flags); | |
437 | ||
07c1b327 CM |
438 | /* Set the default machine type. */ |
439 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_bfin, 0)) | |
bd3ba5d1 | 440 | as_warn (_("Could not set architecture and machine.")); |
07c1b327 CM |
441 | |
442 | /* Ensure that lines can begin with '(', for multiple | |
443 | register stack pops. */ | |
9f8e671b | 444 | lex_type ['('] = LEX_BEGIN_NAME; |
07c1b327 CM |
445 | |
446 | #ifdef OBJ_ELF | |
447 | record_alignment (text_section, 2); | |
448 | record_alignment (data_section, 2); | |
449 | record_alignment (bss_section, 2); | |
450 | #endif | |
451 | ||
452 | errorf = stderr; | |
453 | obstack_init (&mempool); | |
454 | ||
455 | #ifdef DEBUG | |
456 | extern int debug_codeselection; | |
457 | debug_codeselection = 1; | |
458 | #endif | |
459 | ||
460 | last_insn_size = 0; | |
461 | } | |
462 | ||
463 | /* Perform the main parsing, and assembly of the input here. Also, | |
464 | call the required routines for alignment and fixups here. | |
465 | This is called for every line that contains real assembly code. */ | |
466 | ||
467 | void | |
468 | md_assemble (char *line) | |
469 | { | |
470 | char *toP = 0; | |
471 | extern char *current_inputline; | |
472 | int size, insn_size; | |
473 | struct bfin_insn *tmp_insn; | |
474 | size_t len; | |
475 | static size_t buffer_len = 0; | |
476 | parse_state state; | |
477 | ||
478 | len = strlen (line); | |
479 | if (len + 2 > buffer_len) | |
480 | { | |
481 | if (buffer_len > 0) | |
482 | free (current_inputline); | |
483 | buffer_len = len + 40; | |
484 | current_inputline = xmalloc (buffer_len); | |
485 | } | |
486 | memcpy (current_inputline, line, len); | |
487 | current_inputline[len] = ';'; | |
488 | current_inputline[len + 1] = '\0'; | |
489 | ||
490 | state = parse (current_inputline); | |
491 | if (state == NO_INSN_GENERATED) | |
492 | return; | |
493 | ||
494 | for (insn_size = 0, tmp_insn = insn; tmp_insn; tmp_insn = tmp_insn->next) | |
495 | if (!tmp_insn->reloc || !tmp_insn->exp->symbol) | |
496 | insn_size += 2; | |
497 | ||
498 | if (insn_size) | |
499 | toP = frag_more (insn_size); | |
500 | ||
501 | last_insn_size = insn_size; | |
502 | ||
503 | #ifdef DEBUG | |
504 | printf ("INS:"); | |
505 | #endif | |
506 | while (insn) | |
507 | { | |
508 | if (insn->reloc && insn->exp->symbol) | |
509 | { | |
510 | char *prev_toP = toP - 2; | |
511 | switch (insn->reloc) | |
512 | { | |
513 | case BFD_RELOC_BFIN_24_PCREL_JUMP_L: | |
514 | case BFD_RELOC_24_PCREL: | |
515 | case BFD_RELOC_BFIN_16_LOW: | |
516 | case BFD_RELOC_BFIN_16_HIGH: | |
517 | size = 4; | |
518 | break; | |
519 | default: | |
520 | size = 2; | |
521 | } | |
522 | ||
523 | /* Following if condition checks for the arithmetic relocations. | |
524 | If the case then it doesn't required to generate the code. | |
525 | It has been assumed that, their ID will be contiguous. */ | |
526 | if ((BFD_ARELOC_BFIN_PUSH <= insn->reloc | |
527 | && BFD_ARELOC_BFIN_COMP >= insn->reloc) | |
528 | || insn->reloc == BFD_RELOC_BFIN_16_IMM) | |
529 | { | |
530 | size = 2; | |
531 | } | |
532 | if (insn->reloc == BFD_ARELOC_BFIN_CONST | |
533 | || insn->reloc == BFD_ARELOC_BFIN_PUSH) | |
534 | size = 4; | |
535 | ||
536 | fix_new (frag_now, | |
537 | (prev_toP - frag_now->fr_literal), | |
538 | size, insn->exp->symbol, insn->exp->value, | |
539 | insn->pcrel, insn->reloc); | |
540 | } | |
541 | else | |
542 | { | |
543 | md_number_to_chars (toP, insn->value, 2); | |
544 | toP += 2; | |
545 | } | |
546 | ||
547 | #ifdef DEBUG | |
548 | printf (" reloc :"); | |
549 | printf (" %02x%02x", ((unsigned char *) &insn->value)[0], | |
550 | ((unsigned char *) &insn->value)[1]); | |
551 | printf ("\n"); | |
552 | #endif | |
553 | insn = insn->next; | |
554 | } | |
555 | #ifdef OBJ_ELF | |
556 | dwarf2_emit_insn (insn_size); | |
557 | #endif | |
bd03da30 JZ |
558 | |
559 | while (*line++ != '\0') | |
560 | if (*line == '\n') | |
561 | bump_line_counters (); | |
07c1b327 CM |
562 | } |
563 | ||
564 | /* Parse one line of instructions, and generate opcode for it. | |
565 | To parse the line, YACC and LEX are used, because the instruction set | |
566 | syntax doesn't confirm to the AT&T assembly syntax. | |
567 | To call a YACC & LEX generated parser, we must provide the input via | |
568 | a FILE stream, otherwise stdin is used by default. Below the input | |
569 | to the function will be put into a temporary file, then the generated | |
570 | parser uses the temporary file for parsing. */ | |
571 | ||
572 | static parse_state | |
573 | parse (char *line) | |
574 | { | |
575 | parse_state state; | |
576 | YY_BUFFER_STATE buffstate; | |
577 | ||
578 | buffstate = yy_scan_string (line); | |
579 | ||
580 | /* our lex requires setting the start state to keyword | |
581 | every line as the first word may be a keyword. | |
582 | Fixes a bug where we could not have keywords as labels. */ | |
583 | set_start_state (); | |
584 | ||
585 | /* Call yyparse here. */ | |
586 | state = yyparse (); | |
587 | if (state == SEMANTIC_ERROR) | |
588 | { | |
bd3ba5d1 | 589 | as_bad (_("Parse failed.")); |
07c1b327 CM |
590 | insn = 0; |
591 | } | |
592 | ||
593 | yy_delete_buffer (buffstate); | |
594 | return state; | |
595 | } | |
596 | ||
597 | /* We need to handle various expressions properly. | |
598 | Such as, [SP--] = 34, concerned by md_assemble(). */ | |
599 | ||
600 | void | |
601 | md_operand (expressionS * expressionP) | |
602 | { | |
603 | if (*input_line_pointer == '[') | |
604 | { | |
605 | as_tsktsk ("We found a '['!"); | |
606 | input_line_pointer++; | |
607 | expression (expressionP); | |
608 | } | |
609 | } | |
610 | ||
611 | /* Handle undefined symbols. */ | |
612 | symbolS * | |
613 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) | |
614 | { | |
615 | return (symbolS *) 0; | |
616 | } | |
617 | ||
618 | int | |
619 | md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED, | |
620 | segT segment ATTRIBUTE_UNUSED) | |
621 | { | |
622 | return 0; | |
623 | } | |
624 | ||
625 | /* Convert from target byte order to host byte order. */ | |
626 | ||
627 | static int | |
9ba4c445 | 628 | md_chars_to_number (char *val, int n) |
07c1b327 CM |
629 | { |
630 | int retval; | |
631 | ||
632 | for (retval = 0; n--;) | |
633 | { | |
634 | retval <<= 8; | |
635 | retval |= val[n]; | |
636 | } | |
637 | return retval; | |
638 | } | |
639 | ||
640 | void | |
641 | md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED) | |
642 | { | |
643 | char *where = fixP->fx_frag->fr_literal + fixP->fx_where; | |
644 | ||
645 | long value = *valueP; | |
646 | long newval; | |
647 | ||
648 | switch (fixP->fx_r_type) | |
649 | { | |
650 | case BFD_RELOC_BFIN_GOT: | |
1ac4baed BS |
651 | case BFD_RELOC_BFIN_GOT17M4: |
652 | case BFD_RELOC_BFIN_FUNCDESC_GOT17M4: | |
07c1b327 CM |
653 | fixP->fx_no_overflow = 1; |
654 | newval = md_chars_to_number (where, 2); | |
655 | newval |= 0x0 & 0x7f; | |
656 | md_number_to_chars (where, newval, 2); | |
657 | break; | |
658 | ||
659 | case BFD_RELOC_BFIN_10_PCREL: | |
660 | if (!value) | |
661 | break; | |
662 | if (value < -1024 || value > 1022) | |
663 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
bd3ba5d1 | 664 | _("pcrel too far BFD_RELOC_BFIN_10")); |
07c1b327 CM |
665 | |
666 | /* 11 bit offset even numbered, so we remove right bit. */ | |
667 | value = value >> 1; | |
668 | newval = md_chars_to_number (where, 2); | |
669 | newval |= value & 0x03ff; | |
670 | md_number_to_chars (where, newval, 2); | |
671 | break; | |
672 | ||
673 | case BFD_RELOC_BFIN_12_PCREL_JUMP: | |
674 | case BFD_RELOC_BFIN_12_PCREL_JUMP_S: | |
675 | case BFD_RELOC_12_PCREL: | |
676 | if (!value) | |
677 | break; | |
678 | ||
679 | if (value < -4096 || value > 4094) | |
bd3ba5d1 | 680 | as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_12")); |
07c1b327 CM |
681 | /* 13 bit offset even numbered, so we remove right bit. */ |
682 | value = value >> 1; | |
683 | newval = md_chars_to_number (where, 2); | |
684 | newval |= value & 0xfff; | |
685 | md_number_to_chars (where, newval, 2); | |
686 | break; | |
687 | ||
688 | case BFD_RELOC_BFIN_16_LOW: | |
689 | case BFD_RELOC_BFIN_16_HIGH: | |
690 | fixP->fx_done = FALSE; | |
691 | break; | |
692 | ||
693 | case BFD_RELOC_BFIN_24_PCREL_JUMP_L: | |
694 | case BFD_RELOC_BFIN_24_PCREL_CALL_X: | |
695 | case BFD_RELOC_24_PCREL: | |
696 | if (!value) | |
697 | break; | |
698 | ||
699 | if (value < -16777216 || value > 16777214) | |
bd3ba5d1 | 700 | as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_24")); |
07c1b327 CM |
701 | |
702 | /* 25 bit offset even numbered, so we remove right bit. */ | |
703 | value = value >> 1; | |
704 | value++; | |
705 | ||
706 | md_number_to_chars (where - 2, value >> 16, 1); | |
707 | md_number_to_chars (where, value, 1); | |
708 | md_number_to_chars (where + 1, value >> 8, 1); | |
709 | break; | |
710 | ||
711 | case BFD_RELOC_BFIN_5_PCREL: /* LSETUP (a, b) : "a" */ | |
712 | if (!value) | |
713 | break; | |
714 | if (value < 4 || value > 30) | |
bd3ba5d1 | 715 | as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_5")); |
07c1b327 CM |
716 | value = value >> 1; |
717 | newval = md_chars_to_number (where, 1); | |
718 | newval = (newval & 0xf0) | (value & 0xf); | |
719 | md_number_to_chars (where, newval, 1); | |
720 | break; | |
721 | ||
722 | case BFD_RELOC_BFIN_11_PCREL: /* LSETUP (a, b) : "b" */ | |
723 | if (!value) | |
724 | break; | |
725 | value += 2; | |
726 | if (value < 4 || value > 2046) | |
bd3ba5d1 | 727 | as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_11_PCREL")); |
07c1b327 CM |
728 | /* 11 bit unsigned even, so we remove right bit. */ |
729 | value = value >> 1; | |
730 | newval = md_chars_to_number (where, 2); | |
731 | newval |= value & 0x03ff; | |
732 | md_number_to_chars (where, newval, 2); | |
733 | break; | |
734 | ||
735 | case BFD_RELOC_8: | |
736 | if (value < -0x80 || value >= 0x7f) | |
bd3ba5d1 | 737 | as_bad_where (fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_8")); |
07c1b327 CM |
738 | md_number_to_chars (where, value, 1); |
739 | break; | |
740 | ||
741 | case BFD_RELOC_BFIN_16_IMM: | |
742 | case BFD_RELOC_16: | |
743 | if (value < -0x8000 || value >= 0x7fff) | |
bd3ba5d1 | 744 | as_bad_where (fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_16")); |
07c1b327 CM |
745 | md_number_to_chars (where, value, 2); |
746 | break; | |
747 | ||
748 | case BFD_RELOC_32: | |
749 | md_number_to_chars (where, value, 4); | |
750 | break; | |
751 | ||
752 | case BFD_RELOC_BFIN_PLTPC: | |
753 | md_number_to_chars (where, value, 2); | |
754 | break; | |
755 | ||
1ac4baed | 756 | case BFD_RELOC_BFIN_FUNCDESC: |
07c1b327 CM |
757 | case BFD_RELOC_VTABLE_INHERIT: |
758 | case BFD_RELOC_VTABLE_ENTRY: | |
759 | fixP->fx_done = FALSE; | |
760 | break; | |
761 | ||
762 | default: | |
763 | if ((BFD_ARELOC_BFIN_PUSH > fixP->fx_r_type) || (BFD_ARELOC_BFIN_COMP < fixP->fx_r_type)) | |
764 | { | |
765 | fprintf (stderr, "Relocation %d not handled in gas." " Contact support.\n", fixP->fx_r_type); | |
766 | return; | |
767 | } | |
768 | } | |
769 | ||
770 | if (!fixP->fx_addsy) | |
771 | fixP->fx_done = TRUE; | |
772 | ||
773 | } | |
774 | ||
775 | /* Round up a section size to the appropriate boundary. */ | |
776 | valueT | |
777 | md_section_align (segment, size) | |
778 | segT segment; | |
779 | valueT size; | |
780 | { | |
781 | int boundary = bfd_get_section_alignment (stdoutput, segment); | |
782 | return ((size + (1 << boundary) - 1) & (-1 << boundary)); | |
783 | } | |
784 | ||
785 | ||
07c1b327 | 786 | char * |
499ac353 | 787 | md_atof (int type, char * litP, int * sizeP) |
07c1b327 | 788 | { |
499ac353 | 789 | return ieee_md_atof (type, litP, sizeP, FALSE); |
07c1b327 CM |
790 | } |
791 | ||
792 | ||
793 | /* If while processing a fixup, a reloc really needs to be created | |
794 | then it is done here. */ | |
795 | ||
796 | arelent * | |
797 | tc_gen_reloc (seg, fixp) | |
798 | asection *seg ATTRIBUTE_UNUSED; | |
799 | fixS *fixp; | |
800 | { | |
801 | arelent *reloc; | |
802 | ||
803 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
804 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
805 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
806 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
807 | ||
808 | reloc->addend = fixp->fx_offset; | |
809 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
810 | ||
811 | if (reloc->howto == (reloc_howto_type *) NULL) | |
812 | { | |
813 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
814 | /* xgettext:c-format. */ | |
815 | _("reloc %d not supported by object file format"), | |
816 | (int) fixp->fx_r_type); | |
817 | ||
818 | xfree (reloc); | |
819 | ||
820 | return NULL; | |
821 | } | |
822 | ||
823 | return reloc; | |
824 | } | |
825 | ||
826 | /* The location from which a PC relative jump should be calculated, | |
827 | given a PC relative reloc. */ | |
828 | ||
829 | long | |
830 | md_pcrel_from_section (fixP, sec) | |
831 | fixS *fixP; | |
832 | segT sec; | |
833 | { | |
834 | if (fixP->fx_addsy != (symbolS *) NULL | |
835 | && (!S_IS_DEFINED (fixP->fx_addsy) | |
836 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
837 | { | |
838 | /* The symbol is undefined (or is defined but not in this section). | |
839 | Let the linker figure it out. */ | |
840 | return 0; | |
841 | } | |
842 | return fixP->fx_frag->fr_address + fixP->fx_where; | |
843 | } | |
844 | ||
845 | /* Return true if the fix can be handled by GAS, false if it must | |
846 | be passed through to the linker. */ | |
847 | ||
848 | bfd_boolean | |
849 | bfin_fix_adjustable (fixS *fixP) | |
850 | { | |
851 | switch (fixP->fx_r_type) | |
852 | { | |
853 | /* Adjust_reloc_syms doesn't know about the GOT. */ | |
1ac4baed | 854 | case BFD_RELOC_BFIN_GOT: |
1ac4baed | 855 | case BFD_RELOC_BFIN_PLTPC: |
07c1b327 CM |
856 | /* We need the symbol name for the VTABLE entries. */ |
857 | case BFD_RELOC_VTABLE_INHERIT: | |
858 | case BFD_RELOC_VTABLE_ENTRY: | |
859 | return 0; | |
860 | ||
861 | default: | |
862 | return 1; | |
863 | } | |
864 | } | |
865 | ||
07c1b327 CM |
866 | /* Special extra functions that help bfin-parse.y perform its job. */ |
867 | ||
07c1b327 CM |
868 | struct obstack mempool; |
869 | ||
870 | INSTR_T | |
871 | conscode (INSTR_T head, INSTR_T tail) | |
872 | { | |
873 | if (!head) | |
874 | return tail; | |
875 | head->next = tail; | |
876 | return head; | |
877 | } | |
878 | ||
879 | INSTR_T | |
880 | conctcode (INSTR_T head, INSTR_T tail) | |
881 | { | |
882 | INSTR_T temp = (head); | |
883 | if (!head) | |
884 | return tail; | |
885 | while (temp->next) | |
886 | temp = temp->next; | |
887 | temp->next = tail; | |
888 | ||
889 | return head; | |
890 | } | |
891 | ||
892 | INSTR_T | |
893 | note_reloc (INSTR_T code, Expr_Node * symbol, int reloc, int pcrel) | |
894 | { | |
895 | /* Assert that the symbol is not an operator. */ | |
9c2799c2 | 896 | gas_assert (symbol->type == Expr_Node_Reloc); |
07c1b327 CM |
897 | |
898 | return note_reloc1 (code, symbol->value.s_value, reloc, pcrel); | |
899 | ||
900 | } | |
901 | ||
902 | INSTR_T | |
903 | note_reloc1 (INSTR_T code, const char *symbol, int reloc, int pcrel) | |
904 | { | |
905 | code->reloc = reloc; | |
906 | code->exp = mkexpr (0, symbol_find_or_make (symbol)); | |
907 | code->pcrel = pcrel; | |
908 | return code; | |
909 | } | |
910 | ||
911 | INSTR_T | |
912 | note_reloc2 (INSTR_T code, const char *symbol, int reloc, int value, int pcrel) | |
913 | { | |
914 | code->reloc = reloc; | |
915 | code->exp = mkexpr (value, symbol_find_or_make (symbol)); | |
916 | code->pcrel = pcrel; | |
917 | return code; | |
918 | } | |
919 | ||
920 | INSTR_T | |
921 | gencode (unsigned long x) | |
922 | { | |
78aff5a5 | 923 | INSTR_T cell = obstack_alloc (&mempool, sizeof (struct bfin_insn)); |
07c1b327 CM |
924 | memset (cell, 0, sizeof (struct bfin_insn)); |
925 | cell->value = (x); | |
926 | return cell; | |
927 | } | |
928 | ||
929 | int reloc; | |
930 | int ninsns; | |
931 | int count_insns; | |
932 | ||
933 | static void * | |
934 | allocate (int n) | |
935 | { | |
78aff5a5 | 936 | return obstack_alloc (&mempool, n); |
07c1b327 CM |
937 | } |
938 | ||
939 | Expr_Node * | |
940 | Expr_Node_Create (Expr_Node_Type type, | |
941 | Expr_Node_Value value, | |
942 | Expr_Node *Left_Child, | |
943 | Expr_Node *Right_Child) | |
944 | { | |
945 | ||
946 | ||
947 | Expr_Node *node = (Expr_Node *) allocate (sizeof (Expr_Node)); | |
948 | node->type = type; | |
949 | node->value = value; | |
950 | node->Left_Child = Left_Child; | |
951 | node->Right_Child = Right_Child; | |
952 | return node; | |
953 | } | |
954 | ||
955 | static const char *con = ".__constant"; | |
956 | static const char *op = ".__operator"; | |
957 | static INSTR_T Expr_Node_Gen_Reloc_R (Expr_Node * head); | |
958 | INSTR_T Expr_Node_Gen_Reloc (Expr_Node *head, int parent_reloc); | |
959 | ||
960 | INSTR_T | |
961 | Expr_Node_Gen_Reloc (Expr_Node * head, int parent_reloc) | |
962 | { | |
963 | /* Top level reloction expression generator VDSP style. | |
964 | If the relocation is just by itself, generate one item | |
965 | else generate this convoluted expression. */ | |
966 | ||
967 | INSTR_T note = NULL_CODE; | |
968 | INSTR_T note1 = NULL_CODE; | |
969 | int pcrel = 1; /* Is the parent reloc pcrelative? | |
970 | This calculation here and HOWTO should match. */ | |
971 | ||
972 | if (parent_reloc) | |
973 | { | |
974 | /* If it's 32 bit quantity then 16bit code needs to be added. */ | |
975 | int value = 0; | |
976 | ||
977 | if (head->type == Expr_Node_Constant) | |
978 | { | |
979 | /* If note1 is not null code, we have to generate a right | |
980 | aligned value for the constant. Otherwise the reloc is | |
981 | a part of the basic command and the yacc file | |
982 | generates this. */ | |
983 | value = head->value.i_value; | |
984 | } | |
985 | switch (parent_reloc) | |
986 | { | |
708587a4 | 987 | /* Some relocations will need to allocate extra words. */ |
07c1b327 CM |
988 | case BFD_RELOC_BFIN_16_IMM: |
989 | case BFD_RELOC_BFIN_16_LOW: | |
990 | case BFD_RELOC_BFIN_16_HIGH: | |
991 | note1 = conscode (gencode (value), NULL_CODE); | |
992 | pcrel = 0; | |
993 | break; | |
994 | case BFD_RELOC_BFIN_PLTPC: | |
995 | note1 = conscode (gencode (value), NULL_CODE); | |
996 | pcrel = 0; | |
997 | break; | |
998 | case BFD_RELOC_16: | |
999 | case BFD_RELOC_BFIN_GOT: | |
1ac4baed BS |
1000 | case BFD_RELOC_BFIN_GOT17M4: |
1001 | case BFD_RELOC_BFIN_FUNCDESC_GOT17M4: | |
07c1b327 CM |
1002 | note1 = conscode (gencode (value), NULL_CODE); |
1003 | pcrel = 0; | |
1004 | break; | |
1005 | case BFD_RELOC_24_PCREL: | |
1006 | case BFD_RELOC_BFIN_24_PCREL_JUMP_L: | |
1007 | case BFD_RELOC_BFIN_24_PCREL_CALL_X: | |
1008 | /* These offsets are even numbered pcrel. */ | |
1009 | note1 = conscode (gencode (value >> 1), NULL_CODE); | |
1010 | break; | |
1011 | default: | |
1012 | note1 = NULL_CODE; | |
1013 | } | |
1014 | } | |
1015 | if (head->type == Expr_Node_Constant) | |
1016 | note = note1; | |
1017 | else if (head->type == Expr_Node_Reloc) | |
1018 | { | |
1019 | note = note_reloc1 (gencode (0), head->value.s_value, parent_reloc, pcrel); | |
1020 | if (note1 != NULL_CODE) | |
1021 | note = conscode (note1, note); | |
1022 | } | |
beb6bfe8 BS |
1023 | else if (head->type == Expr_Node_Binop |
1024 | && (head->value.op_value == Expr_Op_Type_Add | |
1025 | || head->value.op_value == Expr_Op_Type_Sub) | |
1026 | && head->Left_Child->type == Expr_Node_Reloc | |
1027 | && head->Right_Child->type == Expr_Node_Constant) | |
1028 | { | |
1029 | int val = head->Right_Child->value.i_value; | |
1030 | if (head->value.op_value == Expr_Op_Type_Sub) | |
1031 | val = -val; | |
1032 | note = conscode (note_reloc2 (gencode (0), head->Left_Child->value.s_value, | |
1033 | parent_reloc, val, 0), | |
1034 | NULL_CODE); | |
1035 | if (note1 != NULL_CODE) | |
1036 | note = conscode (note1, note); | |
1037 | } | |
07c1b327 CM |
1038 | else |
1039 | { | |
1040 | /* Call the recursive function. */ | |
1041 | note = note_reloc1 (gencode (0), op, parent_reloc, pcrel); | |
1042 | if (note1 != NULL_CODE) | |
1043 | note = conscode (note1, note); | |
1044 | note = conctcode (Expr_Node_Gen_Reloc_R (head), note); | |
1045 | } | |
1046 | return note; | |
1047 | } | |
1048 | ||
1049 | static INSTR_T | |
1050 | Expr_Node_Gen_Reloc_R (Expr_Node * head) | |
1051 | { | |
1052 | ||
1053 | INSTR_T note = 0; | |
1054 | INSTR_T note1 = 0; | |
1055 | ||
1056 | switch (head->type) | |
1057 | { | |
1058 | case Expr_Node_Constant: | |
1059 | note = conscode (note_reloc2 (gencode (0), con, BFD_ARELOC_BFIN_CONST, head->value.i_value, 0), NULL_CODE); | |
1060 | break; | |
1061 | case Expr_Node_Reloc: | |
1062 | note = conscode (note_reloc (gencode (0), head, BFD_ARELOC_BFIN_PUSH, 0), NULL_CODE); | |
1063 | break; | |
1064 | case Expr_Node_Binop: | |
1065 | note1 = conctcode (Expr_Node_Gen_Reloc_R (head->Left_Child), Expr_Node_Gen_Reloc_R (head->Right_Child)); | |
1066 | switch (head->value.op_value) | |
1067 | { | |
1068 | case Expr_Op_Type_Add: | |
1069 | note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_ADD, 0), NULL_CODE)); | |
1070 | break; | |
1071 | case Expr_Op_Type_Sub: | |
1072 | note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_SUB, 0), NULL_CODE)); | |
1073 | break; | |
1074 | case Expr_Op_Type_Mult: | |
1075 | note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_MULT, 0), NULL_CODE)); | |
1076 | break; | |
1077 | case Expr_Op_Type_Div: | |
1078 | note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_DIV, 0), NULL_CODE)); | |
1079 | break; | |
1080 | case Expr_Op_Type_Mod: | |
1081 | note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_MOD, 0), NULL_CODE)); | |
1082 | break; | |
1083 | case Expr_Op_Type_Lshift: | |
1084 | note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LSHIFT, 0), NULL_CODE)); | |
1085 | break; | |
1086 | case Expr_Op_Type_Rshift: | |
1087 | note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_RSHIFT, 0), NULL_CODE)); | |
1088 | break; | |
1089 | case Expr_Op_Type_BAND: | |
1090 | note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_AND, 0), NULL_CODE)); | |
1091 | break; | |
1092 | case Expr_Op_Type_BOR: | |
1093 | note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_OR, 0), NULL_CODE)); | |
1094 | break; | |
1095 | case Expr_Op_Type_BXOR: | |
1096 | note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_XOR, 0), NULL_CODE)); | |
1097 | break; | |
1098 | case Expr_Op_Type_LAND: | |
1099 | note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LAND, 0), NULL_CODE)); | |
1100 | break; | |
1101 | case Expr_Op_Type_LOR: | |
1102 | note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LOR, 0), NULL_CODE)); | |
1103 | break; | |
1104 | default: | |
df3e8017 | 1105 | fprintf (stderr, "%s:%d:Unknown operator found for arithmetic" " relocation", __FILE__, __LINE__); |
07c1b327 CM |
1106 | |
1107 | ||
1108 | } | |
1109 | break; | |
1110 | case Expr_Node_Unop: | |
1111 | note1 = conscode (Expr_Node_Gen_Reloc_R (head->Left_Child), NULL_CODE); | |
1112 | switch (head->value.op_value) | |
1113 | { | |
1114 | case Expr_Op_Type_NEG: | |
1115 | note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_NEG, 0), NULL_CODE)); | |
1116 | break; | |
1117 | case Expr_Op_Type_COMP: | |
1118 | note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_COMP, 0), NULL_CODE)); | |
1119 | break; | |
1120 | default: | |
df3e8017 | 1121 | fprintf (stderr, "%s:%d:Unknown operator found for arithmetic" " relocation", __FILE__, __LINE__); |
07c1b327 CM |
1122 | } |
1123 | break; | |
1124 | default: | |
1125 | fprintf (stderr, "%s:%d:Unknown node expression found during " "arithmetic relocation generation", __FILE__, __LINE__); | |
1126 | } | |
1127 | return note; | |
1128 | } | |
d55cb1c5 | 1129 | \f |
07c1b327 CM |
1130 | /* Blackfin opcode generation. */ |
1131 | ||
1132 | /* These functions are called by the generated parser | |
1133 | (from bfin-parse.y), the register type classification | |
1134 | happens in bfin-lex.l. */ | |
1135 | ||
1136 | #include "bfin-aux.h" | |
1137 | #include "opcode/bfin.h" | |
1138 | ||
1139 | #define INIT(t) t c_code = init_##t | |
1140 | #define ASSIGN(x) c_code.opcode |= ((x & c_code.mask_##x)<<c_code.bits_##x) | |
1141 | #define ASSIGN_R(x) c_code.opcode |= (((x ? (x->regno & CODE_MASK) : 0) & c_code.mask_##x)<<c_code.bits_##x) | |
1142 | ||
1143 | #define HI(x) ((x >> 16) & 0xffff) | |
1144 | #define LO(x) ((x ) & 0xffff) | |
1145 | ||
1146 | #define GROUP(x) ((x->regno & CLASS_MASK) >> 4) | |
1147 | ||
1148 | #define GEN_OPCODE32() \ | |
1149 | conscode (gencode (HI (c_code.opcode)), \ | |
1150 | conscode (gencode (LO (c_code.opcode)), NULL_CODE)) | |
1151 | ||
1152 | #define GEN_OPCODE16() \ | |
1153 | conscode (gencode (c_code.opcode), NULL_CODE) | |
1154 | ||
1155 | ||
1156 | /* 32 BIT INSTRUCTIONS. */ | |
1157 | ||
1158 | ||
1159 | /* DSP32 instruction generation. */ | |
1160 | ||
1161 | INSTR_T | |
1162 | bfin_gen_dsp32mac (int op1, int MM, int mmod, int w1, int P, | |
1163 | int h01, int h11, int h00, int h10, int op0, | |
1164 | REG_T dst, REG_T src0, REG_T src1, int w0) | |
1165 | { | |
1166 | INIT (DSP32Mac); | |
1167 | ||
1168 | ASSIGN (op0); | |
1169 | ASSIGN (op1); | |
1170 | ASSIGN (MM); | |
1171 | ASSIGN (mmod); | |
1172 | ASSIGN (w0); | |
1173 | ASSIGN (w1); | |
1174 | ASSIGN (h01); | |
1175 | ASSIGN (h11); | |
1176 | ASSIGN (h00); | |
1177 | ASSIGN (h10); | |
1178 | ASSIGN (P); | |
1179 | ||
1180 | /* If we have full reg assignments, mask out LSB to encode | |
1181 | single or simultaneous even/odd register moves. */ | |
1182 | if (P) | |
1183 | { | |
1184 | dst->regno &= 0x06; | |
1185 | } | |
1186 | ||
1187 | ASSIGN_R (dst); | |
1188 | ASSIGN_R (src0); | |
1189 | ASSIGN_R (src1); | |
1190 | ||
1191 | return GEN_OPCODE32 (); | |
1192 | } | |
1193 | ||
1194 | INSTR_T | |
1195 | bfin_gen_dsp32mult (int op1, int MM, int mmod, int w1, int P, | |
1196 | int h01, int h11, int h00, int h10, int op0, | |
1197 | REG_T dst, REG_T src0, REG_T src1, int w0) | |
1198 | { | |
1199 | INIT (DSP32Mult); | |
1200 | ||
1201 | ASSIGN (op0); | |
1202 | ASSIGN (op1); | |
1203 | ASSIGN (MM); | |
1204 | ASSIGN (mmod); | |
1205 | ASSIGN (w0); | |
1206 | ASSIGN (w1); | |
1207 | ASSIGN (h01); | |
1208 | ASSIGN (h11); | |
1209 | ASSIGN (h00); | |
1210 | ASSIGN (h10); | |
1211 | ASSIGN (P); | |
1212 | ||
1213 | if (P) | |
1214 | { | |
1215 | dst->regno &= 0x06; | |
1216 | } | |
1217 | ||
1218 | ASSIGN_R (dst); | |
1219 | ASSIGN_R (src0); | |
1220 | ASSIGN_R (src1); | |
1221 | ||
1222 | return GEN_OPCODE32 (); | |
1223 | } | |
1224 | ||
1225 | INSTR_T | |
1226 | bfin_gen_dsp32alu (int HL, int aopcde, int aop, int s, int x, | |
1227 | REG_T dst0, REG_T dst1, REG_T src0, REG_T src1) | |
1228 | { | |
1229 | INIT (DSP32Alu); | |
1230 | ||
1231 | ASSIGN (HL); | |
1232 | ASSIGN (aopcde); | |
1233 | ASSIGN (aop); | |
1234 | ASSIGN (s); | |
1235 | ASSIGN (x); | |
1236 | ASSIGN_R (dst0); | |
1237 | ASSIGN_R (dst1); | |
1238 | ASSIGN_R (src0); | |
1239 | ASSIGN_R (src1); | |
1240 | ||
1241 | return GEN_OPCODE32 (); | |
1242 | } | |
1243 | ||
1244 | INSTR_T | |
1245 | bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0, | |
1246 | REG_T src1, int sop, int HLs) | |
1247 | { | |
1248 | INIT (DSP32Shift); | |
1249 | ||
1250 | ASSIGN (sopcde); | |
1251 | ASSIGN (sop); | |
1252 | ASSIGN (HLs); | |
1253 | ||
1254 | ASSIGN_R (dst0); | |
1255 | ASSIGN_R (src0); | |
1256 | ASSIGN_R (src1); | |
1257 | ||
1258 | return GEN_OPCODE32 (); | |
1259 | } | |
1260 | ||
1261 | INSTR_T | |
1262 | bfin_gen_dsp32shiftimm (int sopcde, REG_T dst0, int immag, | |
1263 | REG_T src1, int sop, int HLs) | |
1264 | { | |
1265 | INIT (DSP32ShiftImm); | |
1266 | ||
1267 | ASSIGN (sopcde); | |
1268 | ASSIGN (sop); | |
1269 | ASSIGN (HLs); | |
1270 | ||
1271 | ASSIGN_R (dst0); | |
1272 | ASSIGN (immag); | |
1273 | ASSIGN_R (src1); | |
1274 | ||
1275 | return GEN_OPCODE32 (); | |
1276 | } | |
1277 | ||
1278 | /* LOOP SETUP. */ | |
1279 | ||
1280 | INSTR_T | |
1281 | bfin_gen_loopsetup (Expr_Node * psoffset, REG_T c, int rop, | |
1282 | Expr_Node * peoffset, REG_T reg) | |
1283 | { | |
1284 | int soffset, eoffset; | |
1285 | INIT (LoopSetup); | |
1286 | ||
1287 | soffset = (EXPR_VALUE (psoffset) >> 1); | |
1288 | ASSIGN (soffset); | |
1289 | eoffset = (EXPR_VALUE (peoffset) >> 1); | |
1290 | ASSIGN (eoffset); | |
1291 | ASSIGN (rop); | |
1292 | ASSIGN_R (c); | |
1293 | ASSIGN_R (reg); | |
1294 | ||
1295 | return | |
1296 | conscode (gencode (HI (c_code.opcode)), | |
1297 | conctcode (Expr_Node_Gen_Reloc (psoffset, BFD_RELOC_BFIN_5_PCREL), | |
1298 | conctcode (gencode (LO (c_code.opcode)), Expr_Node_Gen_Reloc (peoffset, BFD_RELOC_BFIN_11_PCREL)))); | |
1299 | ||
1300 | } | |
1301 | ||
1302 | /* Call, Link. */ | |
1303 | ||
1304 | INSTR_T | |
1305 | bfin_gen_calla (Expr_Node * addr, int S) | |
1306 | { | |
1307 | int val; | |
1308 | int high_val; | |
1309 | int reloc = 0; | |
1310 | INIT (CALLa); | |
1311 | ||
1312 | switch(S){ | |
1313 | case 0 : reloc = BFD_RELOC_BFIN_24_PCREL_JUMP_L; break; | |
1314 | case 1 : reloc = BFD_RELOC_24_PCREL; break; | |
1315 | case 2 : reloc = BFD_RELOC_BFIN_PLTPC; break; | |
1316 | default : break; | |
1317 | } | |
1318 | ||
1319 | ASSIGN (S); | |
1320 | ||
1321 | val = EXPR_VALUE (addr) >> 1; | |
1322 | high_val = val >> 16; | |
1323 | ||
1324 | return conscode (gencode (HI (c_code.opcode) | (high_val & 0xff)), | |
1325 | Expr_Node_Gen_Reloc (addr, reloc)); | |
1326 | } | |
1327 | ||
1328 | INSTR_T | |
1329 | bfin_gen_linkage (int R, int framesize) | |
1330 | { | |
1331 | INIT (Linkage); | |
1332 | ||
1333 | ASSIGN (R); | |
1334 | ASSIGN (framesize); | |
1335 | ||
1336 | return GEN_OPCODE32 (); | |
1337 | } | |
1338 | ||
1339 | ||
1340 | /* Load and Store. */ | |
1341 | ||
1342 | INSTR_T | |
1343 | bfin_gen_ldimmhalf (REG_T reg, int H, int S, int Z, Expr_Node * phword, int reloc) | |
1344 | { | |
1345 | int grp, hword; | |
1346 | unsigned val = EXPR_VALUE (phword); | |
1347 | INIT (LDIMMhalf); | |
1348 | ||
1349 | ASSIGN (H); | |
1350 | ASSIGN (S); | |
1351 | ASSIGN (Z); | |
1352 | ||
1353 | ASSIGN_R (reg); | |
1354 | grp = (GROUP (reg)); | |
1355 | ASSIGN (grp); | |
1356 | if (reloc == 2) | |
1357 | { | |
1358 | return conscode (gencode (HI (c_code.opcode)), Expr_Node_Gen_Reloc (phword, BFD_RELOC_BFIN_16_IMM)); | |
1359 | } | |
1360 | else if (reloc == 1) | |
1361 | { | |
1362 | return conscode (gencode (HI (c_code.opcode)), Expr_Node_Gen_Reloc (phword, IS_H (*reg) ? BFD_RELOC_BFIN_16_HIGH : BFD_RELOC_BFIN_16_LOW)); | |
1363 | } | |
1364 | else | |
1365 | { | |
1366 | hword = val; | |
1367 | ASSIGN (hword); | |
1368 | } | |
1369 | return GEN_OPCODE32 (); | |
1370 | } | |
1371 | ||
1372 | INSTR_T | |
1373 | bfin_gen_ldstidxi (REG_T ptr, REG_T reg, int W, int sz, int Z, Expr_Node * poffset) | |
1374 | { | |
07c1b327 CM |
1375 | INIT (LDSTidxI); |
1376 | ||
1377 | if (!IS_PREG (*ptr) || (!IS_DREG (*reg) && !Z)) | |
1378 | { | |
1379 | fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n"); | |
1380 | return 0; | |
1381 | } | |
1382 | ||
1383 | ASSIGN_R (ptr); | |
1384 | ASSIGN_R (reg); | |
1385 | ASSIGN (W); | |
1386 | ASSIGN (sz); | |
07c1b327 CM |
1387 | |
1388 | ASSIGN (Z); | |
1389 | ||
1ac4baed BS |
1390 | if (poffset->type != Expr_Node_Constant) |
1391 | { | |
1392 | /* a GOT relocation such as R0 = [P5 + symbol@GOT] */ | |
1393 | /* distinguish between R0 = [P5 + symbol@GOT] and | |
1394 | P5 = [P5 + _current_shared_library_p5_offset_] | |
1395 | */ | |
1396 | if (poffset->type == Expr_Node_Reloc | |
1397 | && !strcmp (poffset->value.s_value, | |
1398 | "_current_shared_library_p5_offset_")) | |
1399 | { | |
1400 | return conscode (gencode (HI (c_code.opcode)), | |
1401 | Expr_Node_Gen_Reloc(poffset, BFD_RELOC_16)); | |
1402 | } | |
1403 | else if (poffset->type != Expr_Node_GOT_Reloc) | |
1404 | abort (); | |
1405 | ||
1406 | return conscode (gencode (HI (c_code.opcode)), | |
1407 | Expr_Node_Gen_Reloc(poffset->Left_Child, | |
1408 | poffset->value.i_value)); | |
07c1b327 | 1409 | } |
1ac4baed | 1410 | else |
07c1b327 | 1411 | { |
1ac4baed BS |
1412 | int value, offset; |
1413 | switch (sz) | |
8fc4ee9b AM |
1414 | { /* load/store access size */ |
1415 | case 0: /* 32 bit */ | |
1ac4baed BS |
1416 | value = EXPR_VALUE (poffset) >> 2; |
1417 | break; | |
8fc4ee9b | 1418 | case 1: /* 16 bit */ |
1ac4baed BS |
1419 | value = EXPR_VALUE (poffset) >> 1; |
1420 | break; | |
8fc4ee9b | 1421 | case 2: /* 8 bit */ |
1ac4baed BS |
1422 | value = EXPR_VALUE (poffset); |
1423 | break; | |
1424 | default: | |
1425 | abort (); | |
1426 | } | |
1427 | ||
1428 | offset = (value & 0xffff); | |
1429 | ASSIGN (offset); | |
1430 | return GEN_OPCODE32 (); | |
07c1b327 | 1431 | } |
07c1b327 CM |
1432 | } |
1433 | ||
1434 | ||
1435 | INSTR_T | |
1436 | bfin_gen_ldst (REG_T ptr, REG_T reg, int aop, int sz, int Z, int W) | |
1437 | { | |
1438 | INIT (LDST); | |
1439 | ||
1440 | if (!IS_PREG (*ptr) || (!IS_DREG (*reg) && !Z)) | |
1441 | { | |
1442 | fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n"); | |
1443 | return 0; | |
1444 | } | |
1445 | ||
1446 | ASSIGN_R (ptr); | |
1447 | ASSIGN_R (reg); | |
1448 | ASSIGN (aop); | |
1449 | ASSIGN (sz); | |
1450 | ASSIGN (Z); | |
1451 | ASSIGN (W); | |
1452 | ||
1453 | return GEN_OPCODE16 (); | |
1454 | } | |
1455 | ||
1456 | INSTR_T | |
1457 | bfin_gen_ldstii (REG_T ptr, REG_T reg, Expr_Node * poffset, int W, int op) | |
1458 | { | |
1459 | int offset; | |
1460 | int value = 0; | |
1461 | INIT (LDSTii); | |
1462 | ||
1463 | ||
1464 | if (!IS_PREG (*ptr)) | |
1465 | { | |
1466 | fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n"); | |
1467 | return 0; | |
1468 | } | |
1469 | ||
1470 | switch (op) | |
1471 | { | |
1472 | case 1: | |
1473 | case 2: | |
1474 | value = EXPR_VALUE (poffset) >> 1; | |
1475 | break; | |
1476 | case 0: | |
1477 | case 3: | |
1478 | value = EXPR_VALUE (poffset) >> 2; | |
1479 | break; | |
1480 | } | |
1481 | ||
1482 | ASSIGN_R (ptr); | |
1483 | ASSIGN_R (reg); | |
1484 | ||
1485 | offset = value; | |
1486 | ASSIGN (offset); | |
1487 | ASSIGN (W); | |
1488 | ASSIGN (op); | |
1489 | ||
1490 | return GEN_OPCODE16 (); | |
1491 | } | |
1492 | ||
1493 | INSTR_T | |
1494 | bfin_gen_ldstiifp (REG_T sreg, Expr_Node * poffset, int W) | |
1495 | { | |
1496 | /* Set bit 4 if it's a Preg. */ | |
1497 | int reg = (sreg->regno & CODE_MASK) | (IS_PREG (*sreg) ? 0x8 : 0x0); | |
1498 | int offset = ((~(EXPR_VALUE (poffset) >> 2)) & 0x1f) + 1; | |
1499 | INIT (LDSTiiFP); | |
1500 | ASSIGN (reg); | |
1501 | ASSIGN (offset); | |
1502 | ASSIGN (W); | |
1503 | ||
1504 | return GEN_OPCODE16 (); | |
1505 | } | |
1506 | ||
1507 | INSTR_T | |
1508 | bfin_gen_ldstpmod (REG_T ptr, REG_T reg, int aop, int W, REG_T idx) | |
1509 | { | |
1510 | INIT (LDSTpmod); | |
1511 | ||
1512 | ASSIGN_R (ptr); | |
1513 | ASSIGN_R (reg); | |
1514 | ASSIGN (aop); | |
1515 | ASSIGN (W); | |
1516 | ASSIGN_R (idx); | |
1517 | ||
1518 | return GEN_OPCODE16 (); | |
1519 | } | |
1520 | ||
1521 | INSTR_T | |
1522 | bfin_gen_dspldst (REG_T i, REG_T reg, int aop, int W, int m) | |
1523 | { | |
1524 | INIT (DspLDST); | |
1525 | ||
1526 | ASSIGN_R (i); | |
1527 | ASSIGN_R (reg); | |
1528 | ASSIGN (aop); | |
1529 | ASSIGN (W); | |
1530 | ASSIGN (m); | |
1531 | ||
1532 | return GEN_OPCODE16 (); | |
1533 | } | |
1534 | ||
1535 | INSTR_T | |
1536 | bfin_gen_logi2op (int opc, int src, int dst) | |
1537 | { | |
1538 | INIT (LOGI2op); | |
1539 | ||
1540 | ASSIGN (opc); | |
1541 | ASSIGN (src); | |
1542 | ASSIGN (dst); | |
1543 | ||
1544 | return GEN_OPCODE16 (); | |
1545 | } | |
1546 | ||
1547 | INSTR_T | |
1548 | bfin_gen_brcc (int T, int B, Expr_Node * poffset) | |
1549 | { | |
1550 | int offset; | |
1551 | INIT (BRCC); | |
1552 | ||
1553 | ASSIGN (T); | |
1554 | ASSIGN (B); | |
1555 | offset = ((EXPR_VALUE (poffset) >> 1)); | |
1556 | ASSIGN (offset); | |
1557 | return conscode (gencode (c_code.opcode), Expr_Node_Gen_Reloc (poffset, BFD_RELOC_BFIN_10_PCREL)); | |
1558 | } | |
1559 | ||
1560 | INSTR_T | |
1561 | bfin_gen_ujump (Expr_Node * poffset) | |
1562 | { | |
1563 | int offset; | |
1564 | INIT (UJump); | |
1565 | ||
1566 | offset = ((EXPR_VALUE (poffset) >> 1)); | |
1567 | ASSIGN (offset); | |
1568 | ||
1569 | return conscode (gencode (c_code.opcode), | |
1570 | Expr_Node_Gen_Reloc ( | |
1571 | poffset, BFD_RELOC_BFIN_12_PCREL_JUMP_S)); | |
1572 | } | |
1573 | ||
1574 | INSTR_T | |
1575 | bfin_gen_alu2op (REG_T dst, REG_T src, int opc) | |
1576 | { | |
1577 | INIT (ALU2op); | |
1578 | ||
1579 | ASSIGN_R (dst); | |
1580 | ASSIGN_R (src); | |
1581 | ASSIGN (opc); | |
1582 | ||
1583 | return GEN_OPCODE16 (); | |
1584 | } | |
1585 | ||
1586 | INSTR_T | |
1587 | bfin_gen_compi2opd (REG_T dst, int src, int op) | |
1588 | { | |
1589 | INIT (COMPI2opD); | |
1590 | ||
1591 | ASSIGN_R (dst); | |
1592 | ASSIGN (src); | |
1593 | ASSIGN (op); | |
1594 | ||
1595 | return GEN_OPCODE16 (); | |
1596 | } | |
1597 | ||
1598 | INSTR_T | |
1599 | bfin_gen_compi2opp (REG_T dst, int src, int op) | |
1600 | { | |
1601 | INIT (COMPI2opP); | |
1602 | ||
1603 | ASSIGN_R (dst); | |
1604 | ASSIGN (src); | |
1605 | ASSIGN (op); | |
1606 | ||
1607 | return GEN_OPCODE16 (); | |
1608 | } | |
1609 | ||
1610 | INSTR_T | |
1611 | bfin_gen_dagmodik (REG_T i, int op) | |
1612 | { | |
1613 | INIT (DagMODik); | |
1614 | ||
1615 | ASSIGN_R (i); | |
1616 | ASSIGN (op); | |
1617 | ||
1618 | return GEN_OPCODE16 (); | |
1619 | } | |
1620 | ||
1621 | INSTR_T | |
1622 | bfin_gen_dagmodim (REG_T i, REG_T m, int op, int br) | |
1623 | { | |
1624 | INIT (DagMODim); | |
1625 | ||
1626 | ASSIGN_R (i); | |
1627 | ASSIGN_R (m); | |
1628 | ASSIGN (op); | |
1629 | ASSIGN (br); | |
1630 | ||
1631 | return GEN_OPCODE16 (); | |
1632 | } | |
1633 | ||
1634 | INSTR_T | |
1635 | bfin_gen_ptr2op (REG_T dst, REG_T src, int opc) | |
1636 | { | |
1637 | INIT (PTR2op); | |
1638 | ||
1639 | ASSIGN_R (dst); | |
1640 | ASSIGN_R (src); | |
1641 | ASSIGN (opc); | |
1642 | ||
1643 | return GEN_OPCODE16 (); | |
1644 | } | |
1645 | ||
1646 | INSTR_T | |
1647 | bfin_gen_comp3op (REG_T src0, REG_T src1, REG_T dst, int opc) | |
1648 | { | |
1649 | INIT (COMP3op); | |
1650 | ||
1651 | ASSIGN_R (src0); | |
1652 | ASSIGN_R (src1); | |
1653 | ASSIGN_R (dst); | |
1654 | ASSIGN (opc); | |
1655 | ||
1656 | return GEN_OPCODE16 (); | |
1657 | } | |
1658 | ||
1659 | INSTR_T | |
1660 | bfin_gen_ccflag (REG_T x, int y, int opc, int I, int G) | |
1661 | { | |
1662 | INIT (CCflag); | |
1663 | ||
1664 | ASSIGN_R (x); | |
1665 | ASSIGN (y); | |
1666 | ASSIGN (opc); | |
1667 | ASSIGN (I); | |
1668 | ASSIGN (G); | |
1669 | ||
1670 | return GEN_OPCODE16 (); | |
1671 | } | |
1672 | ||
1673 | INSTR_T | |
1674 | bfin_gen_ccmv (REG_T src, REG_T dst, int T) | |
1675 | { | |
1676 | int s, d; | |
1677 | INIT (CCmv); | |
1678 | ||
1679 | ASSIGN_R (src); | |
1680 | ASSIGN_R (dst); | |
1681 | s = (GROUP (src)); | |
1682 | ASSIGN (s); | |
1683 | d = (GROUP (dst)); | |
1684 | ASSIGN (d); | |
1685 | ASSIGN (T); | |
1686 | ||
1687 | return GEN_OPCODE16 (); | |
1688 | } | |
1689 | ||
1690 | INSTR_T | |
1691 | bfin_gen_cc2stat (int cbit, int op, int D) | |
1692 | { | |
1693 | INIT (CC2stat); | |
1694 | ||
1695 | ASSIGN (cbit); | |
1696 | ASSIGN (op); | |
1697 | ASSIGN (D); | |
1698 | ||
1699 | return GEN_OPCODE16 (); | |
1700 | } | |
1701 | ||
1702 | INSTR_T | |
1703 | bfin_gen_regmv (REG_T src, REG_T dst) | |
1704 | { | |
1705 | int gs, gd; | |
1706 | INIT (RegMv); | |
1707 | ||
1708 | ASSIGN_R (src); | |
1709 | ASSIGN_R (dst); | |
1710 | ||
1711 | gs = (GROUP (src)); | |
1712 | ASSIGN (gs); | |
1713 | gd = (GROUP (dst)); | |
1714 | ASSIGN (gd); | |
1715 | ||
1716 | return GEN_OPCODE16 (); | |
1717 | } | |
1718 | ||
1719 | INSTR_T | |
1720 | bfin_gen_cc2dreg (int op, REG_T reg) | |
1721 | { | |
1722 | INIT (CC2dreg); | |
1723 | ||
1724 | ASSIGN (op); | |
1725 | ASSIGN_R (reg); | |
1726 | ||
1727 | return GEN_OPCODE16 (); | |
1728 | } | |
1729 | ||
1730 | INSTR_T | |
1731 | bfin_gen_progctrl (int prgfunc, int poprnd) | |
1732 | { | |
1733 | INIT (ProgCtrl); | |
1734 | ||
1735 | ASSIGN (prgfunc); | |
1736 | ASSIGN (poprnd); | |
1737 | ||
1738 | return GEN_OPCODE16 (); | |
1739 | } | |
1740 | ||
1741 | INSTR_T | |
1742 | bfin_gen_cactrl (REG_T reg, int a, int op) | |
1743 | { | |
1744 | INIT (CaCTRL); | |
1745 | ||
1746 | ASSIGN_R (reg); | |
1747 | ASSIGN (a); | |
1748 | ASSIGN (op); | |
1749 | ||
1750 | return GEN_OPCODE16 (); | |
1751 | } | |
1752 | ||
1753 | INSTR_T | |
1754 | bfin_gen_pushpopmultiple (int dr, int pr, int d, int p, int W) | |
1755 | { | |
1756 | INIT (PushPopMultiple); | |
1757 | ||
1758 | ASSIGN (dr); | |
1759 | ASSIGN (pr); | |
1760 | ASSIGN (d); | |
1761 | ASSIGN (p); | |
1762 | ASSIGN (W); | |
1763 | ||
1764 | return GEN_OPCODE16 (); | |
1765 | } | |
1766 | ||
1767 | INSTR_T | |
1768 | bfin_gen_pushpopreg (REG_T reg, int W) | |
1769 | { | |
1770 | int grp; | |
1771 | INIT (PushPopReg); | |
1772 | ||
1773 | ASSIGN_R (reg); | |
1774 | grp = (GROUP (reg)); | |
1775 | ASSIGN (grp); | |
1776 | ASSIGN (W); | |
1777 | ||
1778 | return GEN_OPCODE16 (); | |
1779 | } | |
1780 | ||
1781 | /* Pseudo Debugging Support. */ | |
1782 | ||
1783 | INSTR_T | |
1784 | bfin_gen_pseudodbg (int fn, int reg, int grp) | |
1785 | { | |
1786 | INIT (PseudoDbg); | |
1787 | ||
1788 | ASSIGN (fn); | |
1789 | ASSIGN (reg); | |
1790 | ASSIGN (grp); | |
1791 | ||
1792 | return GEN_OPCODE16 (); | |
1793 | } | |
1794 | ||
1795 | INSTR_T | |
1796 | bfin_gen_pseudodbg_assert (int dbgop, REG_T regtest, int expected) | |
1797 | { | |
1798 | INIT (PseudoDbg_Assert); | |
1799 | ||
1800 | ASSIGN (dbgop); | |
1801 | ASSIGN_R (regtest); | |
1802 | ASSIGN (expected); | |
1803 | ||
1804 | return GEN_OPCODE32 (); | |
1805 | } | |
1806 | ||
1807 | /* Multiple instruction generation. */ | |
1808 | ||
1809 | INSTR_T | |
1810 | bfin_gen_multi_instr (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2) | |
1811 | { | |
1812 | INSTR_T walk; | |
1813 | ||
1814 | /* If it's a 0, convert into MNOP. */ | |
1815 | if (dsp32) | |
1816 | { | |
1817 | walk = dsp32->next; | |
1818 | SET_MULTI_INSTRUCTION_BIT (dsp32); | |
1819 | } | |
1820 | else | |
1821 | { | |
1822 | dsp32 = gencode (0xc803); | |
1823 | walk = gencode (0x1800); | |
1824 | dsp32->next = walk; | |
1825 | } | |
1826 | ||
1827 | if (!dsp16_grp1) | |
1828 | { | |
1829 | dsp16_grp1 = gencode (0x0000); | |
1830 | } | |
1831 | ||
1832 | if (!dsp16_grp2) | |
1833 | { | |
1834 | dsp16_grp2 = gencode (0x0000); | |
1835 | } | |
1836 | ||
1837 | walk->next = dsp16_grp1; | |
1838 | dsp16_grp1->next = dsp16_grp2; | |
1839 | dsp16_grp2->next = NULL_CODE; | |
1840 | ||
1841 | return dsp32; | |
1842 | } | |
1843 | ||
1844 | INSTR_T | |
1845 | bfin_gen_loop (Expr_Node *expr, REG_T reg, int rop, REG_T preg) | |
1846 | { | |
1847 | const char *loopsym; | |
1848 | char *lbeginsym, *lendsym; | |
1849 | Expr_Node_Value lbeginval, lendval; | |
1850 | Expr_Node *lbegin, *lend; | |
1851 | ||
1852 | loopsym = expr->value.s_value; | |
e2c038d3 BS |
1853 | lbeginsym = (char *) xmalloc (strlen (loopsym) + strlen ("__BEGIN") + 5); |
1854 | lendsym = (char *) xmalloc (strlen (loopsym) + strlen ("__END") + 5); | |
07c1b327 CM |
1855 | |
1856 | lbeginsym[0] = 0; | |
1857 | lendsym[0] = 0; | |
1858 | ||
e2c038d3 | 1859 | strcat (lbeginsym, "L$L$"); |
07c1b327 CM |
1860 | strcat (lbeginsym, loopsym); |
1861 | strcat (lbeginsym, "__BEGIN"); | |
1862 | ||
e2c038d3 | 1863 | strcat (lendsym, "L$L$"); |
07c1b327 CM |
1864 | strcat (lendsym, loopsym); |
1865 | strcat (lendsym, "__END"); | |
1866 | ||
1867 | lbeginval.s_value = lbeginsym; | |
1868 | lendval.s_value = lendsym; | |
1869 | ||
1870 | lbegin = Expr_Node_Create (Expr_Node_Reloc, lbeginval, NULL, NULL); | |
1871 | lend = Expr_Node_Create (Expr_Node_Reloc, lendval, NULL, NULL); | |
b4f42c96 JZ |
1872 | |
1873 | symbol_remove (symbol_find (loopsym), &symbol_rootP, &symbol_lastP); | |
1874 | ||
07c1b327 CM |
1875 | return bfin_gen_loopsetup(lbegin, reg, rop, lend, preg); |
1876 | } | |
1877 | ||
d3a50e14 JZ |
1878 | void |
1879 | bfin_loop_beginend (Expr_Node *expr, int begin) | |
1880 | { | |
1881 | const char *loopsym; | |
1882 | char *label_name; | |
1883 | symbolS *line_label; | |
1884 | const char *suffix = begin ? "__BEGIN" : "__END"; | |
1885 | ||
1886 | loopsym = expr->value.s_value; | |
1887 | label_name = (char *) xmalloc (strlen (loopsym) + strlen (suffix) + 5); | |
1888 | ||
1889 | label_name[0] = 0; | |
1890 | ||
1891 | strcat (label_name, "L$L$"); | |
1892 | strcat (label_name, loopsym); | |
1893 | strcat (label_name, suffix); | |
1894 | ||
1895 | line_label = colon (label_name); | |
1896 | ||
1897 | /* LOOP_END follows the last instruction in the loop. | |
1898 | Adjust label address. */ | |
1899 | if (!begin) | |
1900 | ((struct local_symbol *) line_label)->lsy_value -= last_insn_size; | |
1901 | } | |
1902 | ||
07c1b327 CM |
1903 | bfd_boolean |
1904 | bfin_eol_in_insn (char *line) | |
1905 | { | |
1906 | /* Allow a new-line to appear in the middle of a multi-issue instruction. */ | |
1907 | ||
1908 | char *temp = line; | |
1909 | ||
1910 | if (*line != '\n') | |
1911 | return FALSE; | |
1912 | ||
1913 | /* A semi-colon followed by a newline is always the end of a line. */ | |
1914 | if (line[-1] == ';') | |
1915 | return FALSE; | |
1916 | ||
1917 | if (line[-1] == '|') | |
1918 | return TRUE; | |
1919 | ||
1920 | /* If the || is on the next line, there might be leading whitespace. */ | |
1921 | temp++; | |
1922 | while (*temp == ' ' || *temp == '\t') temp++; | |
1923 | ||
1924 | if (*temp == '|') | |
1925 | return TRUE; | |
1926 | ||
1927 | return FALSE; | |
1928 | } | |
1929 | ||
07c1b327 | 1930 | bfd_boolean |
5e8c8f8f | 1931 | bfin_start_label (char *s, char *ptr) |
07c1b327 | 1932 | { |
5e8c8f8f JZ |
1933 | while (s != ptr) |
1934 | { | |
1935 | if (*s == '(' || *s == '[') | |
1936 | return FALSE; | |
1937 | s++; | |
1938 | } | |
07c1b327 | 1939 | |
07c1b327 CM |
1940 | return TRUE; |
1941 | } | |
1942 | ||
1943 | int | |
1944 | bfin_force_relocation (struct fix *fixp) | |
1945 | { | |
1946 | if (fixp->fx_r_type ==BFD_RELOC_BFIN_16_LOW | |
1947 | || fixp->fx_r_type == BFD_RELOC_BFIN_16_HIGH) | |
1948 | return TRUE; | |
1949 | ||
1950 | return generic_force_reloc (fixp); | |
1951 | } | |
d55cb1c5 BS |
1952 | \f |
1953 | /* This is a stripped down version of the disassembler. The only thing it | |
1954 | does is return a mask of registers modified by an instruction. Only | |
1955 | instructions that can occur in a parallel-issue bundle are handled, and | |
1956 | only the registers that can cause a conflict are recorded. */ | |
1957 | ||
1958 | #define DREG_MASK(n) (0x101 << (n)) | |
1959 | #define DREGH_MASK(n) (0x100 << (n)) | |
1960 | #define DREGL_MASK(n) (0x001 << (n)) | |
1961 | #define IREG_MASK(n) (1 << ((n) + 16)) | |
1962 | ||
1963 | static int | |
1964 | decode_ProgCtrl_0 (int iw0) | |
1965 | { | |
1966 | if (iw0 == 0) | |
1967 | return 0; | |
1968 | abort (); | |
1969 | } | |
1970 | ||
1971 | static int | |
1972 | decode_LDSTpmod_0 (int iw0) | |
1973 | { | |
1974 | /* LDSTpmod | |
1975 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | |
1976 | | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......| | |
1977 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ | |
1978 | int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask); | |
1979 | int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask); | |
1980 | int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask); | |
1981 | int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask); | |
1982 | int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask); | |
1983 | ||
1984 | if (aop == 1 && W == 0 && idx == ptr) | |
1985 | return DREGL_MASK (reg); | |
1986 | else if (aop == 2 && W == 0 && idx == ptr) | |
1987 | return DREGH_MASK (reg); | |
1988 | else if (aop == 1 && W == 1 && idx == ptr) | |
1989 | return 0; | |
1990 | else if (aop == 2 && W == 1 && idx == ptr) | |
1991 | return 0; | |
1992 | else if (aop == 0 && W == 0) | |
1993 | return DREG_MASK (reg); | |
1994 | else if (aop == 1 && W == 0) | |
1995 | return DREGL_MASK (reg); | |
1996 | else if (aop == 2 && W == 0) | |
1997 | return DREGH_MASK (reg); | |
1998 | else if (aop == 3 && W == 0) | |
1999 | return DREG_MASK (reg); | |
2000 | else if (aop == 3 && W == 1) | |
2001 | return DREG_MASK (reg); | |
2002 | else if (aop == 0 && W == 1) | |
2003 | return 0; | |
2004 | else if (aop == 1 && W == 1) | |
2005 | return 0; | |
2006 | else if (aop == 2 && W == 1) | |
2007 | return 0; | |
2008 | else | |
2009 | return 0; | |
2010 | ||
2011 | return 2; | |
2012 | } | |
2013 | ||
2014 | static int | |
2015 | decode_dagMODim_0 (int iw0) | |
2016 | { | |
2017 | /* dagMODim | |
2018 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | |
2019 | | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....| | |
2020 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ | |
2021 | int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask); | |
2022 | int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask); | |
2023 | ||
2024 | if (op == 0 || op == 1) | |
2025 | return IREG_MASK (i); | |
2026 | else | |
2027 | return 0; | |
2028 | ||
2029 | return 2; | |
2030 | } | |
2031 | ||
2032 | static int | |
2033 | decode_dagMODik_0 (int iw0) | |
2034 | { | |
2035 | /* dagMODik | |
2036 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | |
2037 | | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....| | |
2038 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ | |
2039 | int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask); | |
2040 | return IREG_MASK (i); | |
2041 | } | |
2042 | ||
2043 | /* GOOD */ | |
2044 | static int | |
2045 | decode_dspLDST_0 (int iw0) | |
2046 | { | |
2047 | /* dspLDST | |
2048 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | |
2049 | | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......| | |
2050 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ | |
2051 | int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask); | |
2052 | int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask); | |
2053 | int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask); | |
2054 | int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask); | |
2055 | int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask); | |
2056 | ||
2057 | if (aop == 0 && W == 0 && m == 0) | |
2058 | return DREG_MASK (reg) | IREG_MASK (i); | |
2059 | else if (aop == 0 && W == 0 && m == 1) | |
2060 | return DREGL_MASK (reg) | IREG_MASK (i); | |
2061 | else if (aop == 0 && W == 0 && m == 2) | |
2062 | return DREGH_MASK (reg) | IREG_MASK (i); | |
2063 | else if (aop == 1 && W == 0 && m == 0) | |
2064 | return DREG_MASK (reg) | IREG_MASK (i); | |
2065 | else if (aop == 1 && W == 0 && m == 1) | |
2066 | return DREGL_MASK (reg) | IREG_MASK (i); | |
2067 | else if (aop == 1 && W == 0 && m == 2) | |
2068 | return DREGH_MASK (reg) | IREG_MASK (i); | |
2069 | else if (aop == 2 && W == 0 && m == 0) | |
2070 | return DREG_MASK (reg); | |
2071 | else if (aop == 2 && W == 0 && m == 1) | |
2072 | return DREGL_MASK (reg); | |
2073 | else if (aop == 2 && W == 0 && m == 2) | |
2074 | return DREGH_MASK (reg); | |
2075 | else if (aop == 0 && W == 1 && m == 0) | |
2076 | return IREG_MASK (i); | |
2077 | else if (aop == 0 && W == 1 && m == 1) | |
2078 | return IREG_MASK (i); | |
2079 | else if (aop == 0 && W == 1 && m == 2) | |
2080 | return IREG_MASK (i); | |
2081 | else if (aop == 1 && W == 1 && m == 0) | |
2082 | return IREG_MASK (i); | |
2083 | else if (aop == 1 && W == 1 && m == 1) | |
2084 | return IREG_MASK (i); | |
2085 | else if (aop == 1 && W == 1 && m == 2) | |
2086 | return IREG_MASK (i); | |
2087 | else if (aop == 2 && W == 1 && m == 0) | |
2088 | return 0; | |
2089 | else if (aop == 2 && W == 1 && m == 1) | |
2090 | return 0; | |
2091 | else if (aop == 2 && W == 1 && m == 2) | |
2092 | return 0; | |
2093 | else if (aop == 3 && W == 0) | |
2094 | return DREG_MASK (reg) | IREG_MASK (i); | |
2095 | else if (aop == 3 && W == 1) | |
2096 | return IREG_MASK (i); | |
2097 | ||
2098 | abort (); | |
2099 | } | |
2100 | ||
2101 | /* GOOD */ | |
2102 | static int | |
2103 | decode_LDST_0 (int iw0) | |
2104 | { | |
2105 | /* LDST | |
2106 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | |
2107 | | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......| | |
2108 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ | |
2109 | int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask); | |
2110 | int W = ((iw0 >> LDST_W_bits) & LDST_W_mask); | |
2111 | int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask); | |
2112 | int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask); | |
2113 | int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask); | |
2114 | ||
2115 | if (aop == 0 && sz == 0 && Z == 0 && W == 0) | |
2116 | return DREG_MASK (reg); | |
2117 | else if (aop == 0 && sz == 0 && Z == 1 && W == 0) | |
2118 | return 0; | |
2119 | else if (aop == 0 && sz == 1 && Z == 0 && W == 0) | |
2120 | return DREG_MASK (reg); | |
2121 | else if (aop == 0 && sz == 1 && Z == 1 && W == 0) | |
2122 | return DREG_MASK (reg); | |
2123 | else if (aop == 0 && sz == 2 && Z == 0 && W == 0) | |
2124 | return DREG_MASK (reg); | |
2125 | else if (aop == 0 && sz == 2 && Z == 1 && W == 0) | |
2126 | return DREG_MASK (reg); | |
2127 | else if (aop == 1 && sz == 0 && Z == 0 && W == 0) | |
2128 | return DREG_MASK (reg); | |
2129 | else if (aop == 1 && sz == 0 && Z == 1 && W == 0) | |
2130 | return 0; | |
2131 | else if (aop == 1 && sz == 1 && Z == 0 && W == 0) | |
2132 | return DREG_MASK (reg); | |
2133 | else if (aop == 1 && sz == 1 && Z == 1 && W == 0) | |
2134 | return DREG_MASK (reg); | |
2135 | else if (aop == 1 && sz == 2 && Z == 0 && W == 0) | |
2136 | return DREG_MASK (reg); | |
2137 | else if (aop == 1 && sz == 2 && Z == 1 && W == 0) | |
2138 | return DREG_MASK (reg); | |
2139 | else if (aop == 2 && sz == 0 && Z == 0 && W == 0) | |
2140 | return DREG_MASK (reg); | |
2141 | else if (aop == 2 && sz == 0 && Z == 1 && W == 0) | |
2142 | return 0; | |
2143 | else if (aop == 2 && sz == 1 && Z == 0 && W == 0) | |
2144 | return DREG_MASK (reg); | |
2145 | else if (aop == 2 && sz == 1 && Z == 1 && W == 0) | |
2146 | return DREG_MASK (reg); | |
2147 | else if (aop == 2 && sz == 2 && Z == 0 && W == 0) | |
2148 | return DREG_MASK (reg); | |
2149 | else if (aop == 2 && sz == 2 && Z == 1 && W == 0) | |
2150 | return DREG_MASK (reg); | |
2151 | else if (aop == 0 && sz == 0 && Z == 0 && W == 1) | |
2152 | return 0; | |
2153 | else if (aop == 0 && sz == 0 && Z == 1 && W == 1) | |
2154 | return 0; | |
2155 | else if (aop == 0 && sz == 1 && Z == 0 && W == 1) | |
2156 | return 0; | |
2157 | else if (aop == 0 && sz == 2 && Z == 0 && W == 1) | |
2158 | return 0; | |
2159 | else if (aop == 1 && sz == 0 && Z == 0 && W == 1) | |
2160 | return 0; | |
2161 | else if (aop == 1 && sz == 0 && Z == 1 && W == 1) | |
2162 | return 0; | |
2163 | else if (aop == 1 && sz == 1 && Z == 0 && W == 1) | |
2164 | return 0; | |
2165 | else if (aop == 1 && sz == 2 && Z == 0 && W == 1) | |
2166 | return 0; | |
2167 | else if (aop == 2 && sz == 0 && Z == 0 && W == 1) | |
2168 | return 0; | |
2169 | else if (aop == 2 && sz == 0 && Z == 1 && W == 1) | |
2170 | return 0; | |
2171 | else if (aop == 2 && sz == 1 && Z == 0 && W == 1) | |
2172 | return 0; | |
2173 | else if (aop == 2 && sz == 2 && Z == 0 && W == 1) | |
2174 | return 0; | |
2175 | ||
2176 | abort (); | |
2177 | } | |
2178 | ||
2179 | static int | |
2180 | decode_LDSTiiFP_0 (int iw0) | |
2181 | { | |
2182 | /* LDSTiiFP | |
2183 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | |
2184 | | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........| | |
2185 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ | |
2186 | int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask); | |
2187 | int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask); | |
2188 | ||
2189 | if (W == 0) | |
2190 | return reg < 8 ? DREG_MASK (reg) : 0; | |
2191 | else | |
2192 | return 0; | |
2193 | } | |
2194 | ||
2195 | static int | |
2196 | decode_LDSTii_0 (int iw0) | |
2197 | { | |
2198 | /* LDSTii | |
2199 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | |
2200 | | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......| | |
2201 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ | |
2202 | int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask); | |
2203 | int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask); | |
2204 | int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask); | |
2205 | ||
2206 | if (W == 0 && op != 3) | |
2207 | return DREG_MASK (reg); | |
2208 | else if (W == 0 && op == 3) | |
2209 | return 0; | |
2210 | else if (W == 1 && op == 0) | |
2211 | return 0; | |
2212 | else if (W == 1 && op == 1) | |
2213 | return 0; | |
2214 | else if (W == 1 && op == 3) | |
2215 | return 0; | |
2216 | ||
2217 | abort (); | |
2218 | } | |
2219 | ||
2220 | static int | |
2221 | decode_dsp32mac_0 (int iw0, int iw1) | |
2222 | { | |
2223 | int result = 0; | |
2224 | /* dsp32mac | |
2225 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | |
2226 | | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...| | |
2227 | |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..| | |
2228 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ | |
2229 | int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask); | |
2230 | int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask); | |
2231 | int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask); | |
2232 | int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask); | |
2233 | int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask); | |
2234 | int MM = ((iw1 >> DSP32Mac_MM_bits) & DSP32Mac_MM_mask); | |
2235 | int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask); | |
2236 | int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask); | |
2237 | ||
2238 | if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3) | |
2239 | return 0; | |
2240 | ||
2241 | if (op1 == 3 && MM) | |
2242 | return 0; | |
2243 | ||
2244 | if ((w1 || w0) && mmod == M_W32) | |
2245 | return 0; | |
2246 | ||
2247 | if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0) | |
2248 | return 0; | |
2249 | ||
2250 | if (w1 == 1 || op1 != 3) | |
2251 | { | |
2252 | if (w1) | |
2253 | { | |
2254 | if (P) | |
2255 | return DREG_MASK (dst + 1); | |
2256 | else | |
2257 | return DREGH_MASK (dst); | |
2258 | } | |
2259 | } | |
2260 | ||
2261 | if (w0 == 1 || op0 != 3) | |
2262 | { | |
2263 | if (w0) | |
2264 | { | |
2265 | if (P) | |
2266 | return DREG_MASK (dst); | |
2267 | else | |
2268 | return DREGL_MASK (dst); | |
2269 | } | |
2270 | } | |
2271 | ||
2272 | return result; | |
2273 | } | |
2274 | ||
2275 | static int | |
2276 | decode_dsp32mult_0 (int iw0, int iw1) | |
2277 | { | |
2278 | /* dsp32mult | |
2279 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | |
2280 | | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...| | |
2281 | |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..| | |
2282 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ | |
2283 | int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask); | |
2284 | int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask); | |
2285 | int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask); | |
2286 | int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask); | |
2287 | int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask); | |
2288 | int result = 0; | |
2289 | ||
2290 | if (w1 == 0 && w0 == 0) | |
2291 | return 0; | |
2292 | ||
2293 | if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0) | |
2294 | return 0; | |
2295 | ||
2296 | if (w1) | |
2297 | { | |
2298 | if (P) | |
2299 | return DREG_MASK (dst | 1); | |
2300 | else | |
2301 | return DREGH_MASK (dst); | |
2302 | } | |
2303 | ||
2304 | if (w0) | |
2305 | { | |
2306 | if (P) | |
2307 | return DREG_MASK (dst); | |
2308 | else | |
2309 | return DREGL_MASK (dst); | |
2310 | } | |
2311 | ||
2312 | return result; | |
2313 | } | |
2314 | ||
2315 | static int | |
2316 | decode_dsp32alu_0 (int iw0, int iw1) | |
2317 | { | |
2318 | /* dsp32alu | |
2319 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | |
2320 | | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............| | |
2321 | |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......| | |
2322 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ | |
2323 | int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask); | |
2324 | int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask); | |
2325 | int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask); | |
2326 | int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask); | |
2327 | int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask); | |
2328 | int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask); | |
2329 | int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask); | |
2330 | ||
2331 | if (aop == 0 && aopcde == 9 && s == 0) | |
2332 | return 0; | |
2333 | else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0) | |
2334 | return 0; | |
2335 | else if (aop >= x * 2 && aopcde == 5) | |
2336 | return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0); | |
2337 | else if (HL == 0 && aopcde == 2) | |
2338 | return DREGL_MASK (dst0); | |
2339 | else if (HL == 1 && aopcde == 2) | |
2340 | return DREGH_MASK (dst0); | |
2341 | else if (HL == 0 && aopcde == 3) | |
2342 | return DREGL_MASK (dst0); | |
2343 | else if (HL == 1 && aopcde == 3) | |
2344 | return DREGH_MASK (dst0); | |
2345 | ||
2346 | else if (aop == 0 && aopcde == 9 && s == 1) | |
2347 | return 0; | |
2348 | else if (aop == 1 && aopcde == 9 && s == 0) | |
2349 | return 0; | |
2350 | else if (aop == 2 && aopcde == 9 && s == 1) | |
2351 | return 0; | |
2352 | else if (aop == 3 && aopcde == 9 && s == 0) | |
2353 | return 0; | |
2354 | else if (aopcde == 8) | |
2355 | return 0; | |
2356 | else if (aop == 0 && aopcde == 11) | |
2357 | return DREG_MASK (dst0); | |
2358 | else if (aop == 1 && aopcde == 11) | |
2359 | return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0); | |
2360 | else if (aopcde == 11) | |
2361 | return 0; | |
2362 | else if (aopcde == 22) | |
2363 | return DREG_MASK (dst0); | |
2364 | ||
2365 | else if ((aop == 0 || aop == 1) && aopcde == 14) | |
2366 | return 0; | |
2367 | else if (aop == 3 && HL == 0 && aopcde == 14) | |
2368 | return 0; | |
2369 | ||
2370 | else if (aop == 3 && HL == 0 && aopcde == 15) | |
2371 | return DREG_MASK (dst0); | |
2372 | ||
2373 | else if (aop == 1 && aopcde == 16) | |
2374 | return 0; | |
2375 | ||
2376 | else if (aop == 0 && aopcde == 16) | |
2377 | return 0; | |
2378 | ||
2379 | else if (aop == 3 && HL == 0 && aopcde == 16) | |
2380 | return 0; | |
2381 | ||
2382 | else if (aop == 3 && HL == 0 && aopcde == 7) | |
2383 | return DREG_MASK (dst0); | |
2384 | else if ((aop == 0 || aop == 1 || aop == 2) && aopcde == 7) | |
2385 | return DREG_MASK (dst0); | |
2386 | ||
2387 | else if (aop == 0 && aopcde == 12) | |
2388 | return DREG_MASK (dst0); | |
2389 | else if (aop == 1 && aopcde == 12) | |
2390 | return DREG_MASK (dst0) | DREG_MASK (dst1); | |
2391 | else if (aop == 3 && aopcde == 12) | |
2392 | return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0); | |
2393 | ||
2394 | else if (aopcde == 0) | |
2395 | return DREG_MASK (dst0); | |
2396 | else if (aopcde == 1) | |
2397 | return DREG_MASK (dst0) | DREG_MASK (dst1); | |
2398 | ||
2399 | else if (aop == 0 && aopcde == 10) | |
2400 | return DREGL_MASK (dst0); | |
2401 | else if (aop == 1 && aopcde == 10) | |
2402 | return DREGL_MASK (dst0); | |
2403 | ||
2404 | else if ((aop == 1 || aop == 0) && aopcde == 4) | |
2405 | return DREG_MASK (dst0); | |
2406 | else if (aop == 2 && aopcde == 4) | |
2407 | return DREG_MASK (dst0) | DREG_MASK (dst1); | |
2408 | ||
2409 | else if (aop == 0 && aopcde == 17) | |
2410 | return DREG_MASK (dst0) | DREG_MASK (dst1); | |
2411 | else if (aop == 1 && aopcde == 17) | |
2412 | return DREG_MASK (dst0) | DREG_MASK (dst1); | |
2413 | else if (aop == 0 && aopcde == 18) | |
2414 | return 0; | |
2415 | else if (aop == 3 && aopcde == 18) | |
2416 | return 0; | |
2417 | ||
2418 | else if ((aop == 0 || aop == 1 || aop == 2) && aopcde == 6) | |
2419 | return DREG_MASK (dst0); | |
2420 | ||
2421 | else if ((aop == 0 || aop == 1) && aopcde == 20) | |
2422 | return DREG_MASK (dst0); | |
2423 | ||
2424 | else if ((aop == 0 || aop == 1) && aopcde == 21) | |
2425 | return DREG_MASK (dst0) | DREG_MASK (dst1); | |
2426 | ||
2427 | else if (aop == 0 && aopcde == 23 && HL == 1) | |
2428 | return DREG_MASK (dst0); | |
2429 | else if (aop == 0 && aopcde == 23 && HL == 0) | |
2430 | return DREG_MASK (dst0); | |
2431 | ||
2432 | else if (aop == 0 && aopcde == 24) | |
2433 | return DREG_MASK (dst0); | |
2434 | else if (aop == 1 && aopcde == 24) | |
2435 | return DREG_MASK (dst0) | DREG_MASK (dst1); | |
2436 | else if (aopcde == 13) | |
2437 | return DREG_MASK (dst0) | DREG_MASK (dst1); | |
2438 | else | |
2439 | return 0; | |
2440 | ||
2441 | return 4; | |
2442 | } | |
2443 | ||
2444 | static int | |
2445 | decode_dsp32shift_0 (int iw0, int iw1) | |
2446 | { | |
2447 | /* dsp32shift | |
2448 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | |
2449 | | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............| | |
2450 | |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......| | |
2451 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ | |
2452 | int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask); | |
2453 | int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask); | |
2454 | int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); | |
2455 | int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask); | |
2456 | int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask); | |
2457 | int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask); | |
2458 | ||
2459 | if (sop == 0 && sopcde == 0) | |
2460 | return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0); | |
2461 | else if (sop == 1 && sopcde == 0) | |
2462 | return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0); | |
2463 | else if (sop == 2 && sopcde == 0) | |
2464 | return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0); | |
2465 | else if (sop == 0 && sopcde == 3) | |
2466 | return 0; | |
2467 | else if (sop == 1 && sopcde == 3) | |
2468 | return 0; | |
2469 | else if (sop == 2 && sopcde == 3) | |
2470 | return 0; | |
2471 | else if (sop == 3 && sopcde == 3) | |
2472 | return DREG_MASK (dst0); | |
2473 | else if (sop == 0 && sopcde == 1) | |
2474 | return DREG_MASK (dst0); | |
2475 | else if (sop == 1 && sopcde == 1) | |
2476 | return DREG_MASK (dst0); | |
2477 | else if (sop == 2 && sopcde == 1) | |
2478 | return DREG_MASK (dst0); | |
2479 | else if (sopcde == 2) | |
2480 | return DREG_MASK (dst0); | |
2481 | else if (sopcde == 4) | |
2482 | return DREG_MASK (dst0); | |
2483 | else if (sop == 0 && sopcde == 5) | |
2484 | return DREGL_MASK (dst0); | |
2485 | else if (sop == 1 && sopcde == 5) | |
2486 | return DREGL_MASK (dst0); | |
2487 | else if (sop == 2 && sopcde == 5) | |
2488 | return DREGL_MASK (dst0); | |
2489 | else if (sop == 0 && sopcde == 6) | |
2490 | return DREGL_MASK (dst0); | |
2491 | else if (sop == 1 && sopcde == 6) | |
2492 | return DREGL_MASK (dst0); | |
2493 | else if (sop == 3 && sopcde == 6) | |
2494 | return DREGL_MASK (dst0); | |
2495 | else if (sop == 0 && sopcde == 7) | |
2496 | return DREGL_MASK (dst0); | |
2497 | else if (sop == 1 && sopcde == 7) | |
2498 | return DREGL_MASK (dst0); | |
2499 | else if (sop == 2 && sopcde == 7) | |
2500 | return DREGL_MASK (dst0); | |
2501 | else if (sop == 3 && sopcde == 7) | |
2502 | return DREGL_MASK (dst0); | |
2503 | else if (sop == 0 && sopcde == 8) | |
2504 | return DREG_MASK (src0) | DREG_MASK (src1); | |
2505 | #if 0 | |
2506 | { | |
2507 | OUTS (outf, "BITMUX ("); | |
2508 | OUTS (outf, dregs (src0)); | |
2509 | OUTS (outf, ", "); | |
2510 | OUTS (outf, dregs (src1)); | |
2511 | OUTS (outf, ", A0) (ASR)"); | |
2512 | } | |
2513 | #endif | |
2514 | else if (sop == 1 && sopcde == 8) | |
2515 | return DREG_MASK (src0) | DREG_MASK (src1); | |
2516 | #if 0 | |
2517 | { | |
2518 | OUTS (outf, "BITMUX ("); | |
2519 | OUTS (outf, dregs (src0)); | |
2520 | OUTS (outf, ", "); | |
2521 | OUTS (outf, dregs (src1)); | |
2522 | OUTS (outf, ", A0) (ASL)"); | |
2523 | } | |
2524 | #endif | |
2525 | else if (sopcde == 9) | |
2526 | return sop < 2 ? DREGL_MASK (dst0) : DREG_MASK (dst0); | |
2527 | else if (sopcde == 10) | |
2528 | return DREG_MASK (dst0); | |
2529 | else if (sop == 0 && sopcde == 11) | |
2530 | return DREGL_MASK (dst0); | |
2531 | else if (sop == 1 && sopcde == 11) | |
2532 | return DREGL_MASK (dst0); | |
2533 | else if (sop == 0 && sopcde == 12) | |
2534 | return 0; | |
2535 | else if (sop == 1 && sopcde == 12) | |
2536 | return DREGL_MASK (dst0); | |
2537 | else if (sop == 0 && sopcde == 13) | |
2538 | return DREG_MASK (dst0); | |
2539 | else if (sop == 1 && sopcde == 13) | |
2540 | return DREG_MASK (dst0); | |
2541 | else if (sop == 2 && sopcde == 13) | |
2542 | return DREG_MASK (dst0); | |
2543 | ||
2544 | abort (); | |
2545 | } | |
2546 | ||
2547 | static int | |
2548 | decode_dsp32shiftimm_0 (int iw0, int iw1) | |
2549 | { | |
2550 | /* dsp32shiftimm | |
2551 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | |
2552 | | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............| | |
2553 | |.sop...|.HLs...|.dst0......|.immag.................|.src1......| | |
2554 | +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ | |
2555 | int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask); | |
2556 | int bit8 = ((iw1 >> 8) & 0x1); | |
2557 | int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask); | |
2558 | int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask); | |
2559 | int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask); | |
2560 | ||
2561 | ||
2562 | if (sop == 0 && sopcde == 0) | |
2563 | return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0); | |
2564 | else if (sop == 1 && sopcde == 0 && bit8 == 0) | |
2565 | return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0); | |
2566 | else if (sop == 1 && sopcde == 0 && bit8 == 1) | |
2567 | return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0); | |
2568 | else if (sop == 2 && sopcde == 0 && bit8 == 0) | |
2569 | return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0); | |
2570 | else if (sop == 2 && sopcde == 0 && bit8 == 1) | |
2571 | return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0); | |
2572 | else if (sop == 2 && sopcde == 3 && HLs == 1) | |
2573 | return 0; | |
2574 | else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0) | |
2575 | return 0; | |
2576 | else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1) | |
2577 | return 0; | |
2578 | else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0) | |
2579 | return 0; | |
2580 | else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1) | |
2581 | return 0; | |
2582 | else if (sop == 1 && sopcde == 3 && HLs == 0) | |
2583 | return 0; | |
2584 | else if (sop == 1 && sopcde == 3 && HLs == 1) | |
2585 | return 0; | |
2586 | else if (sop == 2 && sopcde == 3 && HLs == 0) | |
2587 | return 0; | |
2588 | else if (sop == 1 && sopcde == 1 && bit8 == 0) | |
2589 | return DREG_MASK (dst0); | |
2590 | else if (sop == 1 && sopcde == 1 && bit8 == 1) | |
2591 | return DREG_MASK (dst0); | |
2592 | else if (sop == 2 && sopcde == 1 && bit8 == 1) | |
2593 | return DREG_MASK (dst0); | |
2594 | else if (sop == 2 && sopcde == 1 && bit8 == 0) | |
2595 | return DREG_MASK (dst0); | |
2596 | else if (sop == 0 && sopcde == 1) | |
2597 | return DREG_MASK (dst0); | |
2598 | else if (sop == 1 && sopcde == 2) | |
2599 | return DREG_MASK (dst0); | |
2600 | else if (sop == 2 && sopcde == 2 && bit8 == 1) | |
2601 | return DREG_MASK (dst0); | |
2602 | else if (sop == 2 && sopcde == 2 && bit8 == 0) | |
2603 | return DREG_MASK (dst0); | |
2604 | else if (sop == 3 && sopcde == 2) | |
2605 | return DREG_MASK (dst0); | |
2606 | else if (sop == 0 && sopcde == 2) | |
2607 | return DREG_MASK (dst0); | |
2608 | ||
2609 | abort (); | |
2610 | } | |
2611 | ||
2612 | int | |
2613 | insn_regmask (int iw0, int iw1) | |
2614 | { | |
2615 | if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800) | |
2616 | return 0; /* MNOP */ | |
2617 | else if ((iw0 & 0xff00) == 0x0000) | |
2618 | return decode_ProgCtrl_0 (iw0); | |
2619 | else if ((iw0 & 0xffc0) == 0x0240) | |
2620 | abort (); | |
2621 | else if ((iw0 & 0xff80) == 0x0100) | |
2622 | abort (); | |
2623 | else if ((iw0 & 0xfe00) == 0x0400) | |
2624 | abort (); | |
2625 | else if ((iw0 & 0xfe00) == 0x0600) | |
2626 | abort (); | |
2627 | else if ((iw0 & 0xf800) == 0x0800) | |
2628 | abort (); | |
2629 | else if ((iw0 & 0xffe0) == 0x0200) | |
2630 | abort (); | |
2631 | else if ((iw0 & 0xff00) == 0x0300) | |
2632 | abort (); | |
2633 | else if ((iw0 & 0xf000) == 0x1000) | |
2634 | abort (); | |
2635 | else if ((iw0 & 0xf000) == 0x2000) | |
2636 | abort (); | |
2637 | else if ((iw0 & 0xf000) == 0x3000) | |
2638 | abort (); | |
2639 | else if ((iw0 & 0xfc00) == 0x4000) | |
2640 | abort (); | |
2641 | else if ((iw0 & 0xfe00) == 0x4400) | |
2642 | abort (); | |
2643 | else if ((iw0 & 0xf800) == 0x4800) | |
2644 | abort (); | |
2645 | else if ((iw0 & 0xf000) == 0x5000) | |
2646 | abort (); | |
2647 | else if ((iw0 & 0xf800) == 0x6000) | |
2648 | abort (); | |
2649 | else if ((iw0 & 0xf800) == 0x6800) | |
2650 | abort (); | |
2651 | else if ((iw0 & 0xf000) == 0x8000) | |
2652 | return decode_LDSTpmod_0 (iw0); | |
2653 | else if ((iw0 & 0xff60) == 0x9e60) | |
2654 | return decode_dagMODim_0 (iw0); | |
2655 | else if ((iw0 & 0xfff0) == 0x9f60) | |
2656 | return decode_dagMODik_0 (iw0); | |
2657 | else if ((iw0 & 0xfc00) == 0x9c00) | |
2658 | return decode_dspLDST_0 (iw0); | |
2659 | else if ((iw0 & 0xf000) == 0x9000) | |
2660 | return decode_LDST_0 (iw0); | |
2661 | else if ((iw0 & 0xfc00) == 0xb800) | |
2662 | return decode_LDSTiiFP_0 (iw0); | |
2663 | else if ((iw0 & 0xe000) == 0xA000) | |
2664 | return decode_LDSTii_0 (iw0); | |
2665 | else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000) | |
2666 | abort (); | |
2667 | else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000) | |
2668 | abort (); | |
2669 | else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000) | |
2670 | abort (); | |
2671 | else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000) | |
2672 | abort (); | |
2673 | else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000) | |
2674 | abort (); | |
2675 | else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000) | |
2676 | return decode_dsp32mac_0 (iw0, iw1); | |
2677 | else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000) | |
2678 | return decode_dsp32mult_0 (iw0, iw1); | |
2679 | else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000) | |
2680 | return decode_dsp32alu_0 (iw0, iw1); | |
2681 | else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000) | |
2682 | return decode_dsp32shift_0 (iw0, iw1); | |
2683 | else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000) | |
2684 | return decode_dsp32shiftimm_0 (iw0, iw1); | |
2685 | else if ((iw0 & 0xff00) == 0xf800) | |
2686 | abort (); | |
2687 | else if ((iw0 & 0xFFC0) == 0xf000 && (iw1 & 0x0000) == 0x0000) | |
2688 | abort (); | |
2689 | ||
2690 | abort (); | |
2691 | } |