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3bcbcc3d HPN |
1 | /* tc-cris.c -- Assembler code for the CRIS CPU core. |
2 | Copyright (C) 2000 Free Software Foundation, Inc. | |
3 | ||
4 | Contributed by Axis Communications AB, Lund, Sweden. | |
5 | Originally written for GAS 1.38.1 by Mikael Asker. | |
6 | Updated, BFDized and GNUified by Hans-Peter Nilsson. | |
7 | ||
8 | This file is part of GAS, the GNU Assembler. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the | |
22 | Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
47926f60 | 23 | MA 02111-1307, USA. */ |
3bcbcc3d HPN |
24 | |
25 | #include <stdio.h> | |
26 | #include <ctype.h> | |
27 | #include "as.h" | |
28 | #include "subsegs.h" | |
29 | #include "opcode/cris.h" | |
30 | ||
31 | /* Conventions used here: | |
32 | Generally speaking, pointers to binutils types such as "fragS" and | |
33 | "expressionS" get parameter and variable names ending in "P", such as | |
34 | "fragP", to harmonize with the rest of the binutils code. Other | |
35 | pointers get a "p" suffix, such as "bufp". Any function or type-name | |
36 | that could clash with a current or future binutils or GAS function get | |
37 | a "cris_" prefix. */ | |
38 | ||
7b15d668 HPN |
39 | #define SYNTAX_RELAX_REG_PREFIX "no_register_prefix" |
40 | #define SYNTAX_ENFORCE_REG_PREFIX "register_prefix" | |
41 | #define SYNTAX_USER_SYM_LEADING_UNDERSCORE "leading_underscore" | |
42 | #define SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE "no_leading_underscore" | |
43 | #define REGISTER_PREFIX_CHAR '$' | |
44 | ||
3bcbcc3d HPN |
45 | /* This might be CRIS_INSN_NONE if we're assembling a prefix-insn only. |
46 | Note that some prefix-insns might be assembled as CRIS_INSN_NORMAL. */ | |
47 | enum cris_insn_kind | |
48 | { | |
49 | CRIS_INSN_NORMAL, CRIS_INSN_NONE, CRIS_INSN_BRANCH | |
50 | }; | |
51 | ||
52 | /* An instruction will have one of these prefixes. | |
53 | Although the same bit-pattern, we handle BDAP with an immediate | |
54 | expression (eventually quick or [pc+]) different from when we only have | |
55 | register expressions. */ | |
56 | enum prefix_kind | |
57 | { | |
58 | PREFIX_NONE, PREFIX_BDAP_IMM, PREFIX_BDAP, PREFIX_BIAP, PREFIX_DIP, | |
59 | PREFIX_PUSH | |
60 | }; | |
61 | ||
62 | /* The prefix for an instruction. */ | |
63 | struct cris_prefix | |
64 | { | |
47926f60 KH |
65 | enum prefix_kind kind; |
66 | int base_reg_number; | |
67 | unsigned int opcode; | |
3bcbcc3d HPN |
68 | |
69 | /* There might be an expression to be evaluated, like I in [rN+I]. */ | |
47926f60 | 70 | expressionS expr; |
3bcbcc3d HPN |
71 | |
72 | /* If there's an expression, we might need a relocation. Here's the | |
73 | type of what relocation to start relaxaton with. | |
74 | The relocation is assumed to start immediately after the prefix insn, | |
75 | so we don't provide an offset. */ | |
76 | enum bfd_reloc_code_real reloc; | |
77 | }; | |
78 | ||
47926f60 | 79 | /* The description of the instruction being assembled. */ |
3bcbcc3d HPN |
80 | struct cris_instruction |
81 | { | |
82 | /* If CRIS_INSN_NONE, then this insn is of zero length. */ | |
47926f60 | 83 | enum cris_insn_kind insn_type; |
3bcbcc3d HPN |
84 | |
85 | /* If a special register was mentioned, this is its description, else | |
47926f60 | 86 | it is NULL. */ |
3bcbcc3d HPN |
87 | const struct cris_spec_reg *spec_reg; |
88 | ||
47926f60 | 89 | unsigned int opcode; |
3bcbcc3d HPN |
90 | |
91 | /* An insn may have at most one expression; theoretically there could be | |
47926f60 KH |
92 | another in its prefix (but I don't see how that could happen). */ |
93 | expressionS expr; | |
3bcbcc3d HPN |
94 | |
95 | /* The expression might need a relocation. Here's one to start | |
96 | relaxation with. */ | |
47926f60 | 97 | enum bfd_reloc_code_real reloc; |
3bcbcc3d HPN |
98 | |
99 | /* The size in bytes of an immediate expression, or zero in | |
100 | nonapplicable. */ | |
47926f60 | 101 | int imm_oprnd_size; |
3bcbcc3d HPN |
102 | }; |
103 | ||
104 | static void cris_process_instruction PARAMS ((char *, | |
105 | struct cris_instruction *, | |
106 | struct cris_prefix *)); | |
107 | static int get_bwd_size_modifier PARAMS ((char **, int *)); | |
108 | static int get_bw_size_modifier PARAMS ((char **, int *)); | |
109 | static int get_gen_reg PARAMS ((char **, int *)); | |
110 | static int get_spec_reg PARAMS ((char **, | |
111 | const struct cris_spec_reg **)); | |
112 | static int get_autoinc_prefix_or_indir_op PARAMS ((char **, | |
113 | struct cris_prefix *, | |
114 | int *, int *, int *, | |
115 | expressionS *)); | |
116 | static int get_3op_or_dip_prefix_op PARAMS ((char **, | |
117 | struct cris_prefix *)); | |
118 | static int cris_get_expression PARAMS ((char **, expressionS *)); | |
119 | static int get_flags PARAMS ((char **, int *)); | |
120 | static void gen_bdap PARAMS ((int, expressionS *)); | |
121 | static int branch_disp PARAMS ((int)); | |
122 | static void gen_cond_branch_32 PARAMS ((char *, char *, fragS *, | |
123 | symbolS *, symbolS *, long int)); | |
124 | static void cris_number_to_imm PARAMS ((char *, long, int, fixS *)); | |
125 | static void cris_create_short_jump PARAMS ((char *, addressT, addressT, | |
126 | fragS *, symbolS *)); | |
7b15d668 HPN |
127 | static void s_syntax PARAMS ((int)); |
128 | ||
129 | /* All the .syntax functions. */ | |
130 | static void cris_force_reg_prefix PARAMS ((void)); | |
131 | static void cris_relax_reg_prefix PARAMS ((void)); | |
132 | static void cris_sym_leading_underscore PARAMS ((void)); | |
133 | static void cris_sym_no_leading_underscore PARAMS ((void)); | |
134 | ||
3bcbcc3d HPN |
135 | /* Handle to the opcode hash table. */ |
136 | static struct hash_control *op_hash = NULL; | |
137 | ||
7b15d668 HPN |
138 | /* Whether we demand that registers have a `$' prefix. Default here. */ |
139 | static boolean demand_register_prefix = false; | |
140 | ||
141 | /* Whether global user symbols have a leading underscore. Default here. */ | |
142 | static boolean symbols_have_leading_underscore = true; | |
143 | ||
3bcbcc3d HPN |
144 | const pseudo_typeS md_pseudo_table[] = |
145 | { | |
146 | {"dword", cons, 4}, | |
7b15d668 | 147 | {"syntax", s_syntax, 0}, |
3bcbcc3d HPN |
148 | {NULL, 0, 0} |
149 | }; | |
150 | ||
151 | static int warn_for_branch_expansion = 0; | |
152 | ||
153 | const char cris_comment_chars[] = ";"; | |
154 | ||
155 | /* This array holds the chars that only start a comment at the beginning of | |
156 | a line. If the line seems to have the form '# 123 filename' | |
47926f60 | 157 | .line and .file directives will appear in the pre-processed output. */ |
3bcbcc3d HPN |
158 | /* Note that input_file.c hand-checks for '#' at the beginning of the |
159 | first line of the input file. This is because the compiler outputs | |
47926f60 KH |
160 | #NO_APP at the beginning of its output. */ |
161 | /* Also note that slash-star will always start a comment. */ | |
3bcbcc3d HPN |
162 | const char line_comment_chars[] = "#"; |
163 | const char line_separator_chars[] = "@"; | |
164 | ||
165 | /* Now all floating point support is shut off. See md_atof. */ | |
166 | const char EXP_CHARS[] = ""; | |
167 | const char FLT_CHARS[] = ""; | |
168 | ||
3bcbcc3d HPN |
169 | /* For CRIS, we encode the relax_substateTs (in e.g. fr_substate) as: |
170 | 2 1 0 | |
171 | ---/ /--+-----------------+-----------------+-----------------+ | |
172 | | what state ? | how long ? | | |
173 | ---/ /--+-----------------+-----------------+-----------------+ | |
174 | ||
175 | The "how long" bits are 00 = byte, 01 = word, 10 = dword (long). | |
176 | This is a Un*x convention. | |
177 | Not all lengths are legit for a given value of (what state). | |
178 | ||
179 | Groups for CRIS address relaxing: | |
180 | ||
181 | 1. Bcc | |
182 | length: byte, word, 10-byte expansion | |
183 | ||
184 | 2. BDAP | |
47926f60 | 185 | length: byte, word, dword */ |
3bcbcc3d HPN |
186 | |
187 | #define STATE_CONDITIONAL_BRANCH (1) | |
188 | #define STATE_BASE_PLUS_DISP_PREFIX (2) | |
189 | ||
190 | #define STATE_LENGTH_MASK (3) | |
191 | #define STATE_BYTE (0) | |
192 | #define STATE_WORD (1) | |
193 | #define STATE_DWORD (2) | |
194 | /* Symbol undefined. */ | |
195 | #define STATE_UNDF (3) | |
196 | #define STATE_MAX_LENGTH (3) | |
197 | ||
3bcbcc3d HPN |
198 | /* These displacements are relative to the adress following the opcode |
199 | word of the instruction. The first letter is Byte, Word. The 2nd | |
200 | letter is Forward, Backward. */ | |
201 | ||
202 | #define BRANCH_BF ( 254) | |
203 | #define BRANCH_BB (-256) | |
47926f60 KH |
204 | #define BRANCH_WF (2 + 32767) |
205 | #define BRANCH_WB (2 + -32768) | |
3bcbcc3d HPN |
206 | |
207 | #define BDAP_BF ( 127) | |
208 | #define BDAP_BB (-128) | |
209 | #define BDAP_WF ( 32767) | |
210 | #define BDAP_WB (-32768) | |
211 | ||
212 | #define ENCODE_RELAX(what, length) (((what) << 2) + (length)) | |
213 | ||
214 | const relax_typeS md_cris_relax_table[] = | |
215 | { | |
216 | /* Error sentinel (0, 0). */ | |
217 | {1, 1, 0, 0}, | |
218 | ||
219 | /* Unused (0, 1). */ | |
220 | {1, 1, 0, 0}, | |
221 | ||
222 | /* Unused (0, 2). */ | |
223 | {1, 1, 0, 0}, | |
224 | ||
225 | /* Unused (0, 3). */ | |
226 | {1, 1, 0, 0}, | |
227 | ||
228 | /* Bcc o (1, 0). */ | |
229 | {BRANCH_BF, BRANCH_BB, 0, ENCODE_RELAX (1, 1)}, | |
230 | ||
47926f60 | 231 | /* Bcc [PC+] (1, 1). */ |
3bcbcc3d HPN |
232 | {BRANCH_WF, BRANCH_WB, 2, ENCODE_RELAX (1, 2)}, |
233 | ||
234 | /* BEXT/BWF, BA, JUMP (external), JUMP (always), Bnot_cc, JUMP (default) | |
235 | (1, 2). */ | |
236 | {0, 0, 10, 0}, | |
237 | ||
238 | /* Unused (1, 3). */ | |
239 | {1, 1, 0, 0}, | |
240 | ||
241 | /* BDAP o (2, 0). */ | |
242 | {BDAP_BF, BDAP_BB, 0, ENCODE_RELAX (2, 1)}, | |
243 | ||
244 | /* BDAP.[bw] [PC+] (2, 1). */ | |
245 | {BDAP_WF, BDAP_WB, 2, ENCODE_RELAX (2, 2)}, | |
246 | ||
247 | /* BDAP.d [PC+] (2, 2). */ | |
248 | {0, 0, 4, 0} | |
249 | }; | |
250 | ||
251 | #undef BRANCH_BF | |
252 | #undef BRANCH_BB | |
253 | #undef BRANCH_WF | |
254 | #undef BRANCH_WB | |
255 | #undef BDAP_BF | |
256 | #undef BDAP_BB | |
257 | #undef BDAP_WF | |
258 | #undef BDAP_WB | |
259 | ||
3bcbcc3d HPN |
260 | /* Target-specific multicharacter options, not const-declared at usage |
261 | in 2.9.1 and CVS of 2000-02-16. */ | |
262 | struct option md_longopts[] = | |
263 | { | |
7b15d668 HPN |
264 | #define OPTION_NO_US (OPTION_MD_BASE + 0) |
265 | {"no-underscore", no_argument, NULL, OPTION_NO_US}, | |
266 | #define OPTION_US (OPTION_MD_BASE + 1) | |
267 | {"underscore", no_argument, NULL, OPTION_US}, | |
3bcbcc3d HPN |
268 | {NULL, no_argument, NULL, 0} |
269 | }; | |
270 | ||
271 | /* Not const-declared at usage in 2.9.1. */ | |
272 | size_t md_longopts_size = sizeof (md_longopts); | |
273 | const char *md_shortopts = "hHN"; | |
274 | ||
3bcbcc3d HPN |
275 | /* At first glance, this may seems wrong and should be 4 (ba + nop); but |
276 | since a short_jump must skip a *number* of long jumps, it must also be | |
277 | a long jump. Here, we hope to make it a "ba [16bit_offs]" and a "nop" | |
278 | for the delay slot and hope that the jump table at most needs | |
279 | 32767/4=8191 long-jumps. A branch is better than a jump, since it is | |
280 | relative; we will not have a reloc to fix up somewhere. | |
281 | ||
282 | Note that we can't add relocs, because relaxation uses these fixed | |
283 | numbers, and md_create_short_jump is called after relaxation. */ | |
284 | ||
285 | const int md_short_jump_size = 6; | |
286 | const int md_long_jump_size = 6; | |
287 | ||
7b15d668 HPN |
288 | /* Report output format. Small changes in output format (like elf |
289 | variants below) can happen until all options are parsed. */ | |
47926f60 | 290 | |
3bcbcc3d HPN |
291 | const char * |
292 | cris_target_format () | |
293 | { | |
294 | switch (OUTPUT_FLAVOR) | |
295 | { | |
296 | case bfd_target_aout_flavour: | |
297 | return "a.out-cris"; | |
298 | ||
299 | case bfd_target_elf_flavour: | |
7b15d668 HPN |
300 | if (symbols_have_leading_underscore) |
301 | return "elf32-us-cris"; | |
3bcbcc3d HPN |
302 | return "elf32-cris"; |
303 | ||
304 | default: | |
305 | abort (); | |
306 | return NULL; | |
307 | } | |
308 | } | |
309 | ||
310 | /* Prepare machine-dependent frags for relaxation. | |
311 | ||
312 | Called just before relaxation starts. Any symbol that is now undefined | |
313 | will not become defined. | |
314 | ||
315 | Return the correct fr_subtype in the frag. | |
316 | ||
317 | Return the initial "guess for fr_var" to caller. The guess for fr_var | |
318 | is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix | |
319 | or fr_var contributes to our returned value. | |
320 | ||
321 | Although it may not be explicit in the frag, pretend | |
47926f60 | 322 | fr_var starts with a value. */ |
3bcbcc3d HPN |
323 | |
324 | int | |
325 | md_estimate_size_before_relax (fragP, segment_type) | |
326 | fragS *fragP; | |
327 | /* The segment is either N_DATA or N_TEXT. */ | |
47926f60 | 328 | segT segment_type; |
3bcbcc3d | 329 | { |
47926f60 | 330 | int old_fr_fix; |
3bcbcc3d HPN |
331 | |
332 | old_fr_fix = fragP->fr_fix; | |
333 | ||
334 | switch (fragP->fr_subtype) | |
335 | { | |
336 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_UNDF): | |
337 | if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type) | |
338 | { | |
339 | /* The symbol lies in the same segment - a relaxable case. */ | |
340 | fragP->fr_subtype | |
341 | = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE); | |
342 | } | |
343 | else | |
344 | { | |
345 | /* Unknown or not the same segment, so not relaxable. */ | |
346 | char *writep; | |
347 | ||
348 | /* A small branch-always (2 bytes) to the "real" branch | |
349 | instruction, plus a delay-slot nop (2 bytes), plus a | |
350 | jump (2 plus 4 bytes). See gen_cond_branch_32. */ | |
351 | fragP->fr_fix += 2 + 2 + 2 + 4; | |
352 | writep = fragP->fr_literal + old_fr_fix; | |
353 | gen_cond_branch_32 (fragP->fr_opcode, writep, fragP, | |
47926f60 | 354 | fragP->fr_symbol, (symbolS *) NULL, |
3bcbcc3d HPN |
355 | fragP->fr_offset); |
356 | frag_wane (fragP); | |
357 | } | |
358 | break; | |
359 | ||
360 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE): | |
361 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD): | |
362 | /* We *might* give a better initial guess if we peek at offsets | |
363 | now, but the caller will relax correctly and without this, so | |
364 | don't bother. */ | |
365 | break; | |
366 | ||
367 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF): | |
368 | /* Note that we can not do anything sane with relaxing | |
369 | [rX + a_known_symbol_in_text], it will have to be a 32-bit | |
370 | value. | |
371 | ||
372 | We could play tricks with managing a constant pool and make | |
373 | a_known_symbol_in_text a "bdap [pc + offset]" pointing there, but | |
374 | that's pointless, it can only be longer and slower. | |
375 | ||
376 | Off-topic: If PIC becomes *really* important, and has to be done | |
377 | in the assembler and linker only (which would be weird or | |
378 | clueless), we can so something. Imagine: | |
379 | move.x [r + 32_bit_symbol],r | |
380 | move.x [32_bit_symbol],r | |
381 | move.x 32_bit_symbol,r | |
382 | can be shortened by a word (8-bit offset) if we are close to the | |
383 | symbol or keep its length (16-bit offset) or be a word longer | |
384 | (32-bit offset). Then change the 32_bit_symbol into a "bdap [pc | |
385 | + offset]", and put the offset to the 32_bit_symbol in "offset". | |
386 | Weird, to say the least, and we still have to add support for a | |
387 | PC-relative relocation in the loader (shared libraries). But | |
388 | it's an interesting thought. */ | |
389 | ||
390 | if (S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) | |
391 | { | |
392 | /* Go for dword if not absolute or same segment. */ | |
393 | fragP->fr_subtype | |
394 | = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD); | |
395 | fragP->fr_var += 4; | |
396 | } | |
397 | else | |
398 | { | |
399 | /* Absolute expression. */ | |
400 | long int value; | |
401 | value = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
402 | ||
403 | if (value >= -128 && value <= 127) | |
404 | { | |
405 | /* Byte displacement. */ | |
406 | (fragP->fr_opcode)[0] = value; | |
407 | } | |
408 | else | |
409 | { | |
410 | /* Word or dword displacement. */ | |
411 | int pow2_of_size = 1; | |
412 | char *writep; | |
413 | ||
414 | if (value < -32768 || value > 32767) | |
415 | { | |
416 | /* Outside word range, make it a dword. */ | |
417 | pow2_of_size = 2; | |
418 | } | |
419 | ||
420 | /* Modify the byte-offset BDAP into a word or dword offset | |
421 | BDAP. Or really, a BDAP rX,8bit into a | |
07e90ad5 | 422 | BDAP.[wd] rX,[PC+] followed by a word or dword. */ |
3bcbcc3d HPN |
423 | (fragP->fr_opcode)[0] = BDAP_PC_LOW + pow2_of_size * 16; |
424 | ||
425 | /* Keep the register number in the highest four bits. */ | |
426 | (fragP->fr_opcode)[1] &= 0xF0; | |
427 | (fragP->fr_opcode)[1] |= BDAP_INCR_HIGH; | |
428 | ||
47926f60 | 429 | /* It grew by two or four bytes. */ |
3bcbcc3d HPN |
430 | fragP->fr_fix += 1 << pow2_of_size; |
431 | writep = fragP->fr_literal + old_fr_fix; | |
432 | md_number_to_chars (writep, value, 1 << pow2_of_size); | |
433 | } | |
434 | frag_wane (fragP); | |
435 | } | |
436 | break; | |
437 | ||
438 | default: | |
439 | BAD_CASE (fragP->fr_subtype); | |
440 | } | |
441 | ||
442 | return fragP->fr_var + (fragP->fr_fix - old_fr_fix); | |
443 | } | |
444 | ||
3bcbcc3d HPN |
445 | /* Perform post-processing of machine-dependent frags after relaxation. |
446 | Called after relaxation is finished. | |
447 | In: Address of frag. | |
448 | fr_type == rs_machine_dependent. | |
449 | fr_subtype is what the address relaxed to. | |
450 | ||
451 | Out: Any fixS:s and constants are set up. | |
452 | ||
453 | The caller will turn the frag into a ".space 0". */ | |
454 | ||
455 | void | |
456 | md_convert_frag (abfd, sec, fragP) | |
457 | bfd *abfd ATTRIBUTE_UNUSED; | |
458 | segT sec ATTRIBUTE_UNUSED; | |
459 | fragS *fragP; | |
460 | { | |
47926f60 | 461 | /* Pointer to first byte in variable-sized part of the frag. */ |
3bcbcc3d HPN |
462 | char *var_partp; |
463 | ||
464 | /* Pointer to first opcode byte in frag. */ | |
465 | char *opcodep; | |
466 | ||
467 | /* Used to check integrity of the relaxation. | |
468 | One of 2 = long, 1 = word, or 0 = byte. */ | |
469 | int length_code; | |
470 | ||
471 | /* Size in bytes of variable-sized part of frag. */ | |
472 | int var_part_size = 0; | |
473 | ||
474 | /* This is part of *fragP. It contains all information about addresses | |
475 | and offsets to varying parts. */ | |
476 | symbolS *symbolP; | |
477 | unsigned long var_part_offset; | |
478 | ||
479 | /* Where, in file space, is _var of *fragP? */ | |
480 | unsigned long address_of_var_part = 0; | |
481 | ||
482 | /* Where, in file space, does addr point? */ | |
483 | unsigned long target_address; | |
484 | ||
485 | know (fragP->fr_type == rs_machine_dependent); | |
486 | ||
487 | length_code = fragP->fr_subtype & STATE_LENGTH_MASK; | |
488 | know (length_code >= 0 && length_code < STATE_MAX_LENGTH); | |
489 | ||
490 | var_part_offset = fragP->fr_fix; | |
491 | var_partp = fragP->fr_literal + var_part_offset; | |
492 | opcodep = fragP->fr_opcode; | |
493 | ||
494 | symbolP = fragP->fr_symbol; | |
495 | target_address | |
496 | = (symbolP | |
497 | ? S_GET_VALUE (symbolP) + symbol_get_frag(fragP->fr_symbol)->fr_address | |
498 | : 0 ) + fragP->fr_offset; | |
499 | address_of_var_part = fragP->fr_address + var_part_offset; | |
500 | ||
501 | switch (fragP->fr_subtype) | |
47926f60 KH |
502 | { |
503 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE): | |
504 | opcodep[0] = branch_disp ((target_address - address_of_var_part)); | |
505 | var_part_size = 0; | |
506 | break; | |
3bcbcc3d | 507 | |
47926f60 KH |
508 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD): |
509 | /* We had a quick immediate branch, now turn it into a word one i.e. a | |
510 | PC autoincrement. */ | |
511 | opcodep[0] = BRANCH_PC_LOW; | |
512 | opcodep[1] &= 0xF0; | |
513 | opcodep[1] |= BRANCH_INCR_HIGH; | |
514 | md_number_to_chars (var_partp, | |
515 | (long) (target_address - (address_of_var_part + 2)), | |
516 | 2); | |
517 | var_part_size = 2; | |
518 | break; | |
519 | ||
520 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_DWORD): | |
521 | gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP, | |
522 | fragP->fr_symbol, (symbolS *) NULL, | |
523 | fragP->fr_offset); | |
524 | /* Ten bytes added: a branch, nop and a jump. */ | |
525 | var_part_size = 2 + 2 + 4 + 2; | |
526 | break; | |
3bcbcc3d | 527 | |
47926f60 KH |
528 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): |
529 | var_partp[0] = target_address - (address_of_var_part + 1); | |
530 | var_part_size = 0; | |
531 | break; | |
532 | ||
533 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): | |
534 | /* We had a BDAP 8-bit "quick immediate", now turn it into a 16-bit | |
535 | one that uses PC autoincrement. */ | |
536 | opcodep[0] = BDAP_PC_LOW + (1 << 4); | |
537 | opcodep[1] &= 0xF0; | |
538 | opcodep[1] |= BDAP_INCR_HIGH; | |
539 | md_number_to_chars (var_partp, (long) (target_address), 2); | |
540 | var_part_size = 2; | |
541 | break; | |
542 | ||
543 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): | |
544 | /* We had a BDAP 16-bit "word", change the offset to a dword. */ | |
545 | opcodep[0] = BDAP_PC_LOW + (2 << 4); | |
546 | opcodep[1] &= 0xF0; | |
547 | opcodep[1] |= BDAP_INCR_HIGH; | |
548 | if (fragP->fr_symbol == NULL) | |
549 | md_number_to_chars (var_partp, fragP->fr_offset, 4); | |
550 | else | |
551 | fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol, | |
552 | fragP->fr_offset, 0, BFD_RELOC_32); | |
553 | var_part_size = 4; | |
554 | break; | |
555 | ||
556 | default: | |
557 | BAD_CASE (fragP->fr_subtype); | |
558 | break; | |
559 | } | |
560 | ||
561 | fragP->fr_fix += var_part_size; | |
3bcbcc3d HPN |
562 | } |
563 | ||
564 | /* Generate a short jump around a secondary jump table. | |
565 | Used by md_create_long_jump. | |
566 | ||
567 | This used to be md_create_short_jump, but is now called from | |
568 | md_create_long_jump instead, when sufficient. | |
569 | since the sizes of the jumps are the same. It used to be brittle, | |
47926f60 | 570 | making possibilities for creating bad code. */ |
3bcbcc3d HPN |
571 | |
572 | static void | |
573 | cris_create_short_jump (storep, from_addr, to_addr, fragP, to_symbol) | |
574 | char *storep; | |
575 | addressT from_addr; | |
576 | addressT to_addr; | |
577 | fragS *fragP ATTRIBUTE_UNUSED; | |
578 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
579 | { | |
580 | long int distance; | |
581 | ||
582 | distance = to_addr - from_addr; | |
583 | ||
584 | if (-254 <= distance && distance <= 256) | |
585 | { | |
586 | /* Create a "short" short jump: "BA distance - 2". */ | |
47926f60 | 587 | storep[0] = branch_disp (distance - 2); |
3bcbcc3d HPN |
588 | storep[1] = BA_QUICK_HIGH; |
589 | ||
590 | /* A nop for the delay slot. */ | |
47926f60 | 591 | md_number_to_chars (storep + 2, NOP_OPCODE, 2); |
3bcbcc3d HPN |
592 | |
593 | /* The extra word should be filled with something sane too. Make it | |
594 | a nop to keep disassembly sane. */ | |
47926f60 | 595 | md_number_to_chars (storep + 4, NOP_OPCODE, 2); |
3bcbcc3d HPN |
596 | } |
597 | else | |
598 | { | |
599 | /* Make it a "long" short jump: "BA (PC+)". */ | |
600 | md_number_to_chars (storep, BA_PC_INCR_OPCODE, 2); | |
601 | ||
47926f60 | 602 | /* ".WORD distance - 4". */ |
3bcbcc3d HPN |
603 | md_number_to_chars (storep + 2, (long) (distance - 4), 2); |
604 | ||
605 | /* A nop for the delay slot. */ | |
47926f60 | 606 | md_number_to_chars (storep + 4, NOP_OPCODE, 2); |
3bcbcc3d HPN |
607 | } |
608 | } | |
609 | ||
3bcbcc3d HPN |
610 | /* Generate a long jump in a secondary jump table. |
611 | ||
612 | storep Where to store the jump instruction. | |
613 | from_addr Address of the jump instruction. | |
614 | to_addr Destination address of the jump. | |
615 | fragP Which frag the destination address operand | |
616 | lies in. | |
617 | to_symbol Destination symbol. */ | |
618 | ||
619 | void | |
620 | md_create_long_jump (storep, from_addr, to_addr, fragP, to_symbol) | |
621 | char *storep; | |
622 | addressT from_addr; | |
623 | addressT to_addr; | |
624 | fragS *fragP; | |
625 | symbolS *to_symbol; | |
626 | { | |
627 | long int distance; | |
628 | ||
629 | distance = to_addr - from_addr; | |
630 | ||
631 | if (-32763 <= distance && distance <= 32772) | |
632 | { | |
633 | /* Then make it a "short" long jump. */ | |
634 | cris_create_short_jump (storep, from_addr, to_addr, fragP, | |
635 | to_symbol); | |
636 | } | |
637 | else | |
638 | { | |
639 | /* We have a "long" long jump: "JUMP (PC+)". */ | |
640 | md_number_to_chars (storep, JUMP_PC_INCR_OPCODE, 2); | |
641 | ||
642 | /* Follow with a ".DWORD to_addr". */ | |
643 | fix_new (fragP, storep + 2 - fragP->fr_literal, 4, to_symbol, | |
644 | 0, 0, BFD_RELOC_32); | |
645 | } | |
646 | } | |
647 | ||
3bcbcc3d | 648 | /* Port-specific assembler initialization. */ |
47926f60 | 649 | |
3bcbcc3d HPN |
650 | void |
651 | md_begin () | |
652 | { | |
653 | const char *hashret = NULL; | |
654 | int i = 0; | |
655 | ||
47926f60 | 656 | /* Set up a hash table for the instructions. */ |
3bcbcc3d HPN |
657 | op_hash = hash_new (); |
658 | if (op_hash == NULL) | |
659 | as_fatal (_("Virtual memory exhausted")); | |
660 | ||
661 | while (cris_opcodes[i].name != NULL) | |
662 | { | |
663 | const char *name = cris_opcodes[i].name; | |
664 | hashret = hash_insert (op_hash, name, (PTR) &cris_opcodes[i]); | |
665 | ||
666 | if (hashret != NULL && *hashret != '\0') | |
667 | as_fatal (_("Can't hash `%s': %s\n"), cris_opcodes[i].name, | |
47926f60 | 668 | *hashret == 0 ? _("(unknown reason)") : hashret); |
3bcbcc3d HPN |
669 | do |
670 | { | |
671 | if (cris_opcodes[i].match & cris_opcodes[i].lose) | |
672 | as_fatal (_("Buggy opcode: `%s' \"%s\"\n"), cris_opcodes[i].name, | |
673 | cris_opcodes[i].args); | |
674 | ||
675 | ++i; | |
47926f60 KH |
676 | } |
677 | while (cris_opcodes[i].name != NULL | |
678 | && strcmp (cris_opcodes[i].name, name) == 0); | |
3bcbcc3d HPN |
679 | } |
680 | } | |
681 | ||
3bcbcc3d | 682 | /* Assemble a source line. */ |
47926f60 | 683 | |
3bcbcc3d HPN |
684 | void |
685 | md_assemble (str) | |
686 | char *str; | |
687 | { | |
688 | struct cris_instruction output_instruction; | |
689 | struct cris_prefix prefix; | |
690 | char *opcodep; | |
691 | char *p; | |
692 | ||
693 | know (str); | |
694 | ||
695 | /* Do the low-level grunt - assemble to bits and split up into a prefix | |
696 | and ordinary insn. */ | |
697 | cris_process_instruction (str, &output_instruction, &prefix); | |
698 | ||
699 | /* Handle any prefixes to the instruction. */ | |
700 | switch (prefix.kind) | |
701 | { | |
702 | case PREFIX_NONE: | |
703 | break; | |
704 | ||
705 | /* When the expression is unknown for a BDAP, it can need 0, 2 or 4 | |
706 | extra bytes, so we handle it separately. */ | |
707 | case PREFIX_BDAP_IMM: | |
708 | gen_bdap (prefix.base_reg_number, &prefix.expr); | |
709 | break; | |
710 | ||
711 | case PREFIX_BDAP: | |
712 | case PREFIX_BIAP: | |
713 | case PREFIX_DIP: | |
714 | opcodep = frag_more (2); | |
715 | ||
716 | /* Output the prefix opcode. */ | |
717 | md_number_to_chars (opcodep, (long) prefix.opcode, 2); | |
718 | ||
719 | /* This only happens for DIP, but is ok for the others as they have | |
720 | no reloc. */ | |
721 | if (prefix.reloc != BFD_RELOC_NONE) | |
722 | { | |
47926f60 | 723 | /* Output an absolute mode address. */ |
3bcbcc3d HPN |
724 | p = frag_more (4); |
725 | fix_new_exp (frag_now, (p - frag_now->fr_literal), 4, | |
726 | &prefix.expr, 0, prefix.reloc); | |
727 | } | |
728 | break; | |
729 | ||
730 | case PREFIX_PUSH: | |
731 | opcodep = frag_more (2); | |
732 | ||
733 | /* Output the prefix opcode. Being a "push", we add the negative | |
734 | size of the register to "sp". */ | |
735 | if (output_instruction.spec_reg != NULL) | |
736 | { | |
47926f60 | 737 | /* Special register. */ |
3bcbcc3d HPN |
738 | opcodep[0] = -output_instruction.spec_reg->reg_size; |
739 | } | |
740 | else | |
741 | { | |
47926f60 | 742 | /* General register. */ |
3bcbcc3d HPN |
743 | opcodep[0] = -4; |
744 | } | |
745 | opcodep[1] = (REG_SP << 4) + (BDAP_QUICK_OPCODE >> 8); | |
746 | break; | |
747 | ||
748 | default: | |
749 | BAD_CASE (prefix.kind); | |
750 | } | |
751 | ||
752 | /* If we only had a prefix insn, we're done. */ | |
753 | if (output_instruction.insn_type == CRIS_INSN_NONE) | |
754 | return; | |
755 | ||
756 | /* Done with the prefix. Continue with the main instruction. */ | |
757 | opcodep = frag_more (2); | |
758 | ||
759 | /* Output the instruction opcode. */ | |
47926f60 | 760 | md_number_to_chars (opcodep, (long) (output_instruction.opcode), 2); |
3bcbcc3d HPN |
761 | |
762 | /* Output the symbol-dependent instruction stuff. */ | |
763 | if (output_instruction.insn_type == CRIS_INSN_BRANCH) | |
764 | { | |
765 | segT to_seg = absolute_section; | |
766 | int is_undefined = 0; | |
767 | int length_code; | |
768 | ||
769 | if (output_instruction.expr.X_op != O_constant) | |
770 | { | |
771 | to_seg = S_GET_SEGMENT (output_instruction.expr.X_add_symbol); | |
772 | ||
773 | if (to_seg == undefined_section) | |
774 | is_undefined = 1; | |
775 | } | |
776 | ||
777 | if (output_instruction.expr.X_op == O_constant | |
778 | || to_seg == now_seg || is_undefined) | |
779 | { | |
780 | /* If is_undefined, then the expression may BECOME now_seg. */ | |
47926f60 | 781 | length_code = is_undefined ? STATE_UNDF : STATE_BYTE; |
3bcbcc3d HPN |
782 | |
783 | /* Make room for max ten bytes of variable length. */ | |
784 | frag_var (rs_machine_dependent, 10, 0, | |
785 | ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, length_code), | |
786 | output_instruction.expr.X_add_symbol, | |
787 | output_instruction.expr.X_add_number, | |
788 | opcodep); | |
789 | } | |
790 | else | |
791 | { | |
792 | /* We have: to_seg != now_seg && to_seg != undefined_section. | |
793 | This means it is a branch to a known symbol in another | |
794 | section. Code in data? Weird but valid. Emit a 32-bit | |
795 | branch. */ | |
796 | gen_cond_branch_32 (opcodep, frag_more (10), frag_now, | |
797 | output_instruction.expr.X_add_symbol, | |
47926f60 | 798 | (symbolS *) NULL, |
3bcbcc3d HPN |
799 | output_instruction.expr.X_add_number); |
800 | } | |
801 | } | |
802 | else | |
803 | { | |
804 | if (output_instruction.imm_oprnd_size > 0) | |
805 | { | |
806 | /* The intruction has an immediate operand. */ | |
807 | enum bfd_reloc_code_real reloc = 0; | |
808 | ||
809 | switch (output_instruction.imm_oprnd_size) | |
810 | { | |
811 | /* Any byte-size immediate constants are treated as | |
812 | word-size. FIXME: Thus overflow check does not work | |
813 | correctly. */ | |
814 | ||
815 | case 2: | |
816 | reloc = BFD_RELOC_16; | |
817 | break; | |
818 | ||
819 | case 4: | |
820 | reloc = BFD_RELOC_32; | |
821 | break; | |
822 | ||
823 | default: | |
824 | BAD_CASE (output_instruction.imm_oprnd_size); | |
825 | } | |
826 | ||
827 | p = frag_more (output_instruction.imm_oprnd_size); | |
828 | fix_new_exp (frag_now, (p - frag_now->fr_literal), | |
829 | output_instruction.imm_oprnd_size, | |
830 | &output_instruction.expr, 0, reloc); | |
831 | } | |
832 | else if (output_instruction.reloc != BFD_RELOC_NONE) | |
833 | { | |
834 | /* An immediate operand that has a relocation and needs to be | |
47926f60 | 835 | processed further. */ |
3bcbcc3d HPN |
836 | |
837 | /* It is important to use fix_new_exp here and everywhere else | |
838 | (and not fix_new), as fix_new_exp can handle "difference | |
839 | expressions" - where the expression contains a difference of | |
840 | two symbols in the same segment. */ | |
841 | fix_new_exp (frag_now, (opcodep - frag_now->fr_literal), 2, | |
842 | &output_instruction.expr, 0, | |
843 | output_instruction.reloc); | |
844 | } | |
845 | } | |
846 | } | |
847 | ||
3bcbcc3d | 848 | /* Low level text-to-bits assembly. */ |
47926f60 | 849 | |
3bcbcc3d HPN |
850 | static void |
851 | cris_process_instruction (insn_text, out_insnp, prefixp) | |
852 | char *insn_text; | |
47926f60 | 853 | struct cris_instruction *out_insnp; |
3bcbcc3d HPN |
854 | struct cris_prefix *prefixp; |
855 | { | |
47926f60 KH |
856 | char *s; |
857 | char modified_char = 0; | |
858 | const char *args; | |
3bcbcc3d | 859 | struct cris_opcode *instruction; |
47926f60 KH |
860 | char *operands; |
861 | int match = 0; | |
862 | int mode; | |
863 | int regno; | |
864 | int size_bits; | |
3bcbcc3d HPN |
865 | |
866 | /* Reset these fields to a harmless state in case we need to return in | |
867 | error. */ | |
868 | prefixp->kind = PREFIX_NONE; | |
869 | prefixp->reloc = BFD_RELOC_NONE; | |
870 | out_insnp->insn_type = CRIS_INSN_NORMAL; | |
871 | out_insnp->imm_oprnd_size = 0; | |
872 | ||
873 | /* Find the end of the opcode mnemonic. We assume (true in 2.9.1) | |
874 | that the caller has translated the opcode to lower-case, up to the | |
47926f60 KH |
875 | first non-letter. */ |
876 | for (operands = insn_text; islower (*operands); ++operands) | |
3bcbcc3d HPN |
877 | ; |
878 | ||
879 | /* Terminate the opcode after letters, but save the character there if | |
880 | it was of significance. */ | |
881 | switch (*operands) | |
882 | { | |
883 | case '\0': | |
884 | break; | |
885 | ||
886 | case '.': | |
47926f60 | 887 | /* Put back the modified character later. */ |
3bcbcc3d | 888 | modified_char = *operands; |
47926f60 | 889 | /* Fall through. */ |
3bcbcc3d HPN |
890 | |
891 | case ' ': | |
47926f60 KH |
892 | /* Consume the character after the mnemonic |
893 | and replace it with '\0'. */ | |
3bcbcc3d HPN |
894 | *operands++ = '\0'; |
895 | break; | |
896 | ||
897 | default: | |
898 | as_bad (_("Unknown opcode: `%s'"), insn_text); | |
899 | return; | |
900 | } | |
901 | ||
902 | /* Find the instruction. */ | |
903 | instruction = (struct cris_opcode *) hash_find (op_hash, insn_text); | |
904 | if (instruction == NULL) | |
905 | { | |
906 | as_bad (_("Unknown opcode: `%s'"), insn_text); | |
907 | return; | |
908 | } | |
909 | ||
910 | /* Put back the modified character. */ | |
911 | switch (modified_char) | |
912 | { | |
913 | case 0: | |
914 | break; | |
915 | ||
916 | default: | |
917 | *--operands = modified_char; | |
918 | } | |
919 | ||
3bcbcc3d | 920 | /* Try to match an opcode table slot. */ |
47926f60 | 921 | for (s = operands;;) |
3bcbcc3d | 922 | { |
47926f60 | 923 | int imm_expr_found; |
3bcbcc3d HPN |
924 | |
925 | /* Initialize *prefixp, perhaps after being modified for a | |
47926f60 | 926 | "near match". */ |
3bcbcc3d HPN |
927 | prefixp->kind = PREFIX_NONE; |
928 | prefixp->reloc = BFD_RELOC_NONE; | |
929 | ||
930 | /* Initialize *out_insnp. */ | |
931 | memset (out_insnp, 0, sizeof (*out_insnp)); | |
932 | out_insnp->opcode = instruction->match; | |
933 | out_insnp->reloc = BFD_RELOC_NONE; | |
934 | out_insnp->insn_type = CRIS_INSN_NORMAL; | |
935 | out_insnp->imm_oprnd_size = 0; | |
936 | ||
937 | imm_expr_found = 0; | |
938 | ||
939 | /* Build the opcode, checking as we go to make sure that the | |
940 | operands match. */ | |
47926f60 | 941 | for (args = instruction->args;; ++args) |
3bcbcc3d HPN |
942 | { |
943 | switch (*args) | |
944 | { | |
945 | case '\0': | |
946 | /* If we've come to the end of arguments, we're done. */ | |
947 | if (*s == '\0') | |
948 | match = 1; | |
949 | break; | |
950 | ||
951 | case '!': | |
952 | /* Non-matcher character for disassembly. | |
953 | Ignore it here. */ | |
954 | continue; | |
955 | ||
956 | case ',': | |
957 | case ' ': | |
958 | /* These must match exactly. */ | |
959 | if (*s++ == *args) | |
960 | continue; | |
961 | break; | |
962 | ||
963 | case 'B': | |
964 | /* This is not really an operand, but causes a "BDAP | |
47926f60 | 965 | -size,SP" prefix to be output, for PUSH instructions. */ |
3bcbcc3d HPN |
966 | prefixp->kind = PREFIX_PUSH; |
967 | continue; | |
968 | ||
969 | case 'b': | |
970 | /* This letter marks an operand that should not be matched | |
971 | in the assembler. It is a branch with 16-bit | |
972 | displacement. The assembler will create them from the | |
973 | 8-bit flavor when necessary. The assembler does not | |
974 | support the [rN+] operand, as the [r15+] that is | |
975 | generated for 16-bit displacements. */ | |
976 | break; | |
977 | ||
978 | case 'c': | |
979 | /* A 5-bit unsigned immediate in bits <4:0>. */ | |
980 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
981 | break; | |
982 | else | |
983 | { | |
984 | if (out_insnp->expr.X_op == O_constant | |
985 | && (out_insnp->expr.X_add_number < 0 | |
986 | || out_insnp->expr.X_add_number > 31)) | |
987 | as_bad (_("Immediate value not in 5 bit unsigned range: %ld"), | |
988 | out_insnp->expr.X_add_number); | |
989 | ||
990 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_5; | |
991 | continue; | |
992 | } | |
993 | ||
994 | case 'C': | |
995 | /* A 4-bit unsigned immediate in bits <3:0>. */ | |
996 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
997 | break; | |
998 | else | |
999 | { | |
1000 | if (out_insnp->expr.X_op == O_constant | |
1001 | && (out_insnp->expr.X_add_number < 0 | |
1002 | || out_insnp->expr.X_add_number > 15)) | |
1003 | as_bad (_("Immediate value not in 4 bit unsigned range: %ld"), | |
1004 | out_insnp->expr.X_add_number); | |
1005 | ||
1006 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_4; | |
1007 | continue; | |
1008 | } | |
1009 | ||
1010 | case 'D': | |
1011 | /* General register in bits <15:12> and <3:0>. */ | |
1012 | if (! get_gen_reg (&s, ®no)) | |
1013 | break; | |
1014 | else | |
1015 | { | |
1016 | out_insnp->opcode |= regno /* << 0 */; | |
1017 | out_insnp->opcode |= regno << 12; | |
1018 | continue; | |
1019 | } | |
1020 | ||
1021 | case 'f': | |
1022 | /* Flags from the condition code register. */ | |
1023 | { | |
1024 | int flags = 0; | |
1025 | ||
1026 | if (! get_flags (&s, &flags)) | |
1027 | break; | |
1028 | ||
47926f60 | 1029 | out_insnp->opcode |= ((flags & 0xf0) << 8) | (flags & 0xf); |
3bcbcc3d HPN |
1030 | continue; |
1031 | } | |
1032 | ||
1033 | case 'i': | |
1034 | /* A 6-bit signed immediate in bits <5:0>. */ | |
1035 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1036 | break; | |
1037 | else | |
1038 | { | |
1039 | if (out_insnp->expr.X_op == O_constant | |
1040 | && (out_insnp->expr.X_add_number < -32 | |
1041 | || out_insnp->expr.X_add_number > 31)) | |
1042 | as_bad (_("Immediate value not in 6 bit range: %ld"), | |
1043 | out_insnp->expr.X_add_number); | |
1044 | out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_6; | |
1045 | continue; | |
1046 | } | |
1047 | ||
1048 | case 'I': | |
1049 | /* A 6-bit unsigned immediate in bits <5:0>. */ | |
1050 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1051 | break; | |
1052 | else | |
1053 | { | |
1054 | if (out_insnp->expr.X_op == O_constant | |
1055 | && (out_insnp->expr.X_add_number < 0 | |
1056 | || out_insnp->expr.X_add_number > 63)) | |
1057 | as_bad (_("Immediate value not in 6 bit unsigned range: %ld"), | |
1058 | out_insnp->expr.X_add_number); | |
1059 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_6; | |
1060 | continue; | |
1061 | } | |
1062 | ||
1063 | case 'M': | |
1064 | /* A size modifier, B, W or D, to be put in a bit position | |
1065 | suitable for CLEAR instructions (i.e. reflecting a zero | |
1066 | register). */ | |
1067 | if (! get_bwd_size_modifier (&s, &size_bits)) | |
1068 | break; | |
1069 | else | |
1070 | { | |
1071 | switch (size_bits) | |
1072 | { | |
1073 | case 0: | |
1074 | out_insnp->opcode |= 0 << 12; | |
1075 | break; | |
1076 | ||
1077 | case 1: | |
1078 | out_insnp->opcode |= 4 << 12; | |
1079 | break; | |
1080 | ||
1081 | case 2: | |
1082 | out_insnp->opcode |= 8 << 12; | |
1083 | break; | |
1084 | } | |
1085 | continue; | |
1086 | } | |
1087 | ||
1088 | case 'm': | |
1089 | /* A size modifier, B, W or D, to be put in bits <5:4>. */ | |
1090 | if (! get_bwd_size_modifier (&s, &size_bits)) | |
1091 | break; | |
1092 | else | |
1093 | { | |
1094 | out_insnp->opcode |= size_bits << 4; | |
1095 | continue; | |
1096 | } | |
1097 | ||
1098 | case 'o': | |
1099 | /* A branch expression. */ | |
1100 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1101 | break; | |
1102 | else | |
1103 | { | |
1104 | out_insnp->insn_type = CRIS_INSN_BRANCH; | |
1105 | continue; | |
1106 | } | |
1107 | ||
1108 | case 'O': | |
1109 | /* A BDAP expression for any size, "expr,r". */ | |
1110 | if (! cris_get_expression (&s, &prefixp->expr)) | |
1111 | break; | |
1112 | else | |
1113 | { | |
1114 | if (*s != ',') | |
1115 | break; | |
1116 | ||
1117 | s++; | |
1118 | ||
1119 | if (!get_gen_reg (&s, &prefixp->base_reg_number)) | |
1120 | break; | |
1121 | ||
1122 | /* Since 'O' is used with an explicit bdap, we have no | |
47926f60 | 1123 | "real" instruction. */ |
3bcbcc3d HPN |
1124 | prefixp->kind = PREFIX_BDAP_IMM; |
1125 | out_insnp->insn_type = CRIS_INSN_NONE; | |
1126 | continue; | |
1127 | } | |
1128 | ||
1129 | case 'P': | |
1130 | /* Special register in bits <15:12>. */ | |
1131 | if (! get_spec_reg (&s, &out_insnp->spec_reg)) | |
1132 | break; | |
1133 | else | |
1134 | { | |
1135 | /* Use of some special register names come with a | |
1136 | specific warning. Note that we have no ".cpu type" | |
1137 | pseudo yet, so some of this is just unused | |
1138 | framework. */ | |
1139 | if (out_insnp->spec_reg->warning) | |
1140 | as_warn (out_insnp->spec_reg->warning); | |
1141 | else if (out_insnp->spec_reg->applicable_version | |
1142 | == cris_ver_warning) | |
1143 | /* Others have a generic warning. */ | |
1144 | as_warn (_("Unimplemented register `%s' specified"), | |
1145 | out_insnp->spec_reg->name); | |
1146 | ||
1147 | out_insnp->opcode | |
1148 | |= out_insnp->spec_reg->number << 12; | |
1149 | continue; | |
1150 | } | |
1151 | ||
1152 | case 'p': | |
1153 | /* This character is used in the disassembler to | |
1154 | recognize a prefix instruction to fold into the | |
1155 | addressing mode for the next instruction. It is | |
47926f60 | 1156 | ignored here. */ |
3bcbcc3d HPN |
1157 | continue; |
1158 | ||
1159 | case 'R': | |
1160 | /* General register in bits <15:12>. */ | |
1161 | if (! get_gen_reg (&s, ®no)) | |
1162 | break; | |
1163 | else | |
1164 | { | |
1165 | out_insnp->opcode |= regno << 12; | |
1166 | continue; | |
1167 | } | |
1168 | ||
1169 | case 'r': | |
1170 | /* General register in bits <3:0>. */ | |
1171 | if (! get_gen_reg (&s, ®no)) | |
1172 | break; | |
1173 | else | |
1174 | { | |
1175 | out_insnp->opcode |= regno /* << 0 */; | |
1176 | continue; | |
1177 | } | |
1178 | ||
1179 | case 'S': | |
1180 | /* Source operand in bit <10> and a prefix; a 3-operand | |
1181 | prefix. */ | |
1182 | if (! get_3op_or_dip_prefix_op (&s, prefixp)) | |
1183 | break; | |
1184 | else | |
1185 | continue; | |
1186 | ||
1187 | case 's': | |
1188 | /* Source operand in bits <10>, <3:0> and optionally a | |
1189 | prefix; i.e. an indirect operand or an side-effect | |
1190 | prefix. */ | |
1191 | if (! get_autoinc_prefix_or_indir_op (&s, prefixp, &mode, | |
1192 | ®no, | |
1193 | &imm_expr_found, | |
1194 | &out_insnp->expr)) | |
1195 | break; | |
1196 | else | |
1197 | { | |
1198 | if (prefixp->kind != PREFIX_NONE) | |
1199 | { | |
1200 | /* A prefix, so it has the autoincrement bit | |
1201 | set. */ | |
1202 | out_insnp->opcode |= (AUTOINCR_BIT << 8); | |
1203 | } | |
1204 | else | |
1205 | /* No prefix. The "mode" variable contains bits like | |
1206 | whether or not this is autoincrement mode. */ | |
1207 | out_insnp->opcode |= (mode << 10); | |
1208 | ||
1209 | out_insnp->opcode |= regno /* << 0 */ ; | |
1210 | continue; | |
1211 | } | |
1212 | ||
1213 | case 'x': | |
1214 | /* Rs.m in bits <15:12> and <5:4>. */ | |
1215 | if (! get_gen_reg (&s, ®no) | |
1216 | || ! get_bwd_size_modifier (&s, &size_bits)) | |
1217 | break; | |
1218 | else | |
1219 | { | |
47926f60 | 1220 | out_insnp->opcode |= (regno << 12) | (size_bits << 4); |
3bcbcc3d HPN |
1221 | continue; |
1222 | } | |
1223 | ||
1224 | case 'y': | |
1225 | /* Source operand in bits <10>, <3:0> and optionally a | |
1226 | prefix; i.e. an indirect operand or an side-effect | |
1227 | prefix. | |
1228 | ||
1229 | The difference to 's' is that this does not allow an | |
81d4177b | 1230 | "immediate" expression. */ |
3bcbcc3d HPN |
1231 | if (! get_autoinc_prefix_or_indir_op (&s, prefixp, |
1232 | &mode, ®no, | |
1233 | &imm_expr_found, | |
1234 | &out_insnp->expr) | |
1235 | || imm_expr_found) | |
1236 | break; | |
1237 | else | |
1238 | { | |
1239 | if (prefixp->kind != PREFIX_NONE) | |
1240 | { | |
1241 | /* A prefix, and those matched here always have | |
1242 | side-effects (see 's' case). */ | |
1243 | out_insnp->opcode |= (AUTOINCR_BIT << 8); | |
1244 | } | |
1245 | else | |
1246 | { | |
1247 | /* No prefix. The "mode" variable contains bits | |
1248 | like whether or not this is autoincrement | |
1249 | mode. */ | |
1250 | out_insnp->opcode |= (mode << 10); | |
1251 | } | |
1252 | ||
1253 | out_insnp->opcode |= regno /* << 0 */; | |
1254 | continue; | |
1255 | } | |
1256 | ||
1257 | case 'z': | |
1258 | /* Size modifier (B or W) in bit <4>. */ | |
1259 | if (! get_bw_size_modifier (&s, &size_bits)) | |
1260 | break; | |
1261 | else | |
1262 | { | |
1263 | out_insnp->opcode |= size_bits << 4; | |
1264 | continue; | |
1265 | } | |
1266 | ||
1267 | default: | |
1268 | BAD_CASE (*args); | |
1269 | } | |
1270 | ||
1271 | /* We get here when we fail a match above or we found a | |
1272 | complete match. Break out of this loop. */ | |
1273 | break; | |
1274 | } | |
1275 | ||
1276 | /* Was it a match or a miss? */ | |
1277 | if (match == 0) | |
1278 | { | |
1279 | /* If it's just that the args don't match, maybe the next | |
1280 | item in the table is the same opcode but with | |
1281 | matching operands. */ | |
1282 | if (instruction[1].name != NULL | |
1283 | && ! strcmp (instruction->name, instruction[1].name)) | |
1284 | { | |
1285 | /* Yep. Restart and try that one instead. */ | |
1286 | ++instruction; | |
1287 | s = operands; | |
1288 | continue; | |
1289 | } | |
1290 | else | |
1291 | { | |
1292 | /* We've come to the end of instructions with this | |
1293 | opcode, so it must be an error. */ | |
1294 | as_bad (_("Illegal operands")); | |
1295 | return; | |
1296 | } | |
1297 | } | |
1298 | else | |
1299 | { | |
1300 | /* We have a match. Check if there's anything more to do. */ | |
1301 | if (imm_expr_found) | |
1302 | { | |
1303 | /* There was an immediate mode operand, so we must check | |
1304 | that it has an appropriate size. */ | |
1305 | ||
1306 | switch (instruction->imm_oprnd_size) | |
1307 | { | |
1308 | default: | |
1309 | case SIZE_NONE: | |
1310 | /* Shouldn't happen; this one does not have immediate | |
1311 | operands with different sizes. */ | |
1312 | BAD_CASE (instruction->imm_oprnd_size); | |
1313 | break; | |
1314 | ||
1315 | case SIZE_FIX_32: | |
1316 | out_insnp->imm_oprnd_size = 4; | |
1317 | break; | |
1318 | ||
1319 | case SIZE_SPEC_REG: | |
1320 | switch (out_insnp->spec_reg->reg_size) | |
1321 | { | |
1322 | case 1: | |
1323 | if (out_insnp->expr.X_op == O_constant | |
1324 | && (out_insnp->expr.X_add_number < -128 | |
1325 | || out_insnp->expr.X_add_number > 255)) | |
1326 | as_bad (_("Immediate value not in 8 bit range: %ld"), | |
1327 | out_insnp->expr.X_add_number); | |
47926f60 | 1328 | /* Fall through. */ |
3bcbcc3d HPN |
1329 | case 2: |
1330 | /* FIXME: We need an indicator in the instruction | |
1331 | table to pass on, to indicate if we need to check | |
1332 | overflow for a signed or unsigned number. */ | |
1333 | if (out_insnp->expr.X_op == O_constant | |
1334 | && (out_insnp->expr.X_add_number < -32768 | |
1335 | || out_insnp->expr.X_add_number > 65535)) | |
1336 | as_bad (_("Immediate value not in 16 bit range: %ld"), | |
1337 | out_insnp->expr.X_add_number); | |
1338 | out_insnp->imm_oprnd_size = 2; | |
1339 | break; | |
1340 | ||
1341 | case 4: | |
1342 | out_insnp->imm_oprnd_size = 4; | |
1343 | break; | |
1344 | ||
1345 | default: | |
1346 | BAD_CASE (out_insnp->spec_reg->reg_size); | |
1347 | } | |
1348 | break; | |
1349 | ||
1350 | case SIZE_FIELD: | |
1351 | switch (size_bits) | |
1352 | { | |
1353 | case 0: | |
1354 | if (out_insnp->expr.X_op == O_constant | |
1355 | && (out_insnp->expr.X_add_number < -128 | |
1356 | || out_insnp->expr.X_add_number > 255)) | |
1357 | as_bad (_("Immediate value not in 8 bit range: %ld"), | |
1358 | out_insnp->expr.X_add_number); | |
47926f60 | 1359 | /* Fall through. */ |
3bcbcc3d HPN |
1360 | case 1: |
1361 | if (out_insnp->expr.X_op == O_constant | |
1362 | && (out_insnp->expr.X_add_number < -32768 | |
1363 | || out_insnp->expr.X_add_number > 65535)) | |
1364 | as_bad (_("Immediate value not in 16 bit range: %ld"), | |
1365 | out_insnp->expr.X_add_number); | |
1366 | out_insnp->imm_oprnd_size = 2; | |
1367 | break; | |
1368 | ||
1369 | case 2: | |
1370 | out_insnp->imm_oprnd_size = 4; | |
1371 | break; | |
1372 | ||
1373 | default: | |
1374 | BAD_CASE (out_insnp->spec_reg->reg_size); | |
1375 | } | |
1376 | } | |
1377 | } | |
1378 | } | |
1379 | break; | |
1380 | } | |
1381 | } | |
1382 | ||
3bcbcc3d HPN |
1383 | /* Get a B, W, or D size modifier from the string pointed out by *cPP, |
1384 | which must point to a '.' in front of the modifier. On successful | |
1385 | return, *cPP is advanced to the character following the size | |
1386 | modifier, and is undefined otherwise. | |
1387 | ||
1388 | cPP Pointer to pointer to string starting | |
1389 | with the size modifier. | |
1390 | ||
1391 | size_bitsp Pointer to variable to contain the size bits on | |
1392 | successful return. | |
1393 | ||
1394 | Return 1 iff a correct size modifier is found, else 0. */ | |
1395 | ||
1396 | static int | |
1397 | get_bwd_size_modifier (cPP, size_bitsp) | |
1398 | char **cPP; | |
1399 | int *size_bitsp; | |
1400 | { | |
1401 | if (**cPP != '.') | |
1402 | return 0; | |
1403 | else | |
1404 | { | |
47926f60 | 1405 | /* Consume the '.'. */ |
3bcbcc3d HPN |
1406 | (*cPP)++; |
1407 | ||
1408 | switch (**cPP) | |
1409 | { | |
1410 | case 'B': | |
1411 | case 'b': | |
1412 | *size_bitsp = 0; | |
1413 | break; | |
1414 | ||
1415 | case 'W': | |
1416 | case 'w': | |
1417 | *size_bitsp = 1; | |
1418 | break; | |
1419 | ||
1420 | case 'D': | |
1421 | case 'd': | |
1422 | *size_bitsp = 2; | |
1423 | break; | |
1424 | ||
1425 | default: | |
1426 | return 0; | |
1427 | } | |
1428 | ||
1429 | /* Consume the size letter. */ | |
1430 | (*cPP)++; | |
1431 | return 1; | |
1432 | } | |
1433 | } | |
1434 | ||
3bcbcc3d HPN |
1435 | /* Get a B or W size modifier from the string pointed out by *cPP, |
1436 | which must point to a '.' in front of the modifier. On successful | |
1437 | return, *cPP is advanced to the character following the size | |
1438 | modifier, and is undefined otherwise. | |
1439 | ||
1440 | cPP Pointer to pointer to string starting | |
1441 | with the size modifier. | |
1442 | ||
1443 | size_bitsp Pointer to variable to contain the size bits on | |
1444 | successful return. | |
1445 | ||
1446 | Return 1 iff a correct size modifier is found, else 0. */ | |
1447 | ||
1448 | static int | |
1449 | get_bw_size_modifier (cPP, size_bitsp) | |
1450 | char **cPP; | |
1451 | int *size_bitsp; | |
1452 | { | |
1453 | if (**cPP != '.') | |
1454 | return 0; | |
1455 | else | |
1456 | { | |
47926f60 | 1457 | /* Consume the '.'. */ |
3bcbcc3d HPN |
1458 | (*cPP)++; |
1459 | ||
1460 | switch (**cPP) | |
1461 | { | |
1462 | case 'B': | |
1463 | case 'b': | |
1464 | *size_bitsp = 0; | |
1465 | break; | |
1466 | ||
1467 | case 'W': | |
1468 | case 'w': | |
1469 | *size_bitsp = 1; | |
1470 | break; | |
1471 | ||
1472 | default: | |
1473 | return 0; | |
1474 | } | |
1475 | ||
1476 | /* Consume the size letter. */ | |
1477 | (*cPP)++; | |
1478 | return 1; | |
1479 | } | |
1480 | } | |
1481 | ||
07e90ad5 | 1482 | /* Get a general register from the string pointed out by *cPP. The |
3bcbcc3d HPN |
1483 | variable *cPP is advanced to the character following the general |
1484 | register name on a successful return, and has its initial position | |
1485 | otherwise. | |
1486 | ||
1487 | cPP Pointer to pointer to string, beginning with a general | |
1488 | register name. | |
1489 | ||
1490 | regnop Pointer to int containing the register number. | |
1491 | ||
1492 | Return 1 iff a correct general register designator is found, | |
1493 | else 0. */ | |
1494 | ||
1495 | static int | |
1496 | get_gen_reg (cPP, regnop) | |
1497 | char **cPP; | |
1498 | int *regnop; | |
1499 | { | |
1500 | char *oldp; | |
1501 | oldp = *cPP; | |
1502 | ||
7b15d668 HPN |
1503 | /* Handle a sometimes-mandatory dollar sign as register prefix. */ |
1504 | if (**cPP == REGISTER_PREFIX_CHAR) | |
1505 | (*cPP)++; | |
1506 | else if (demand_register_prefix) | |
1507 | return 0; | |
1508 | ||
3bcbcc3d HPN |
1509 | switch (**cPP) |
1510 | { | |
1511 | case 'P': | |
1512 | case 'p': | |
1513 | /* "P" as in "PC"? Consume the "P". */ | |
1514 | (*cPP)++; | |
1515 | ||
1516 | if ((**cPP == 'C' || **cPP == 'c') | |
1517 | && ! isalnum ((*cPP)[1])) | |
1518 | { | |
1519 | /* It's "PC": consume the "c" and we're done. */ | |
1520 | (*cPP)++; | |
1521 | *regnop = REG_PC; | |
1522 | return 1; | |
1523 | } | |
1524 | break; | |
1525 | ||
1526 | case 'R': | |
1527 | case 'r': | |
47926f60 | 1528 | /* Hopefully r[0-9] or r1[0-5]. Consume 'R' or 'r'. */ |
3bcbcc3d HPN |
1529 | (*cPP)++; |
1530 | ||
1531 | if (isdigit (**cPP)) | |
1532 | { | |
1533 | /* It's r[0-9]. Consume and check the next digit. */ | |
1534 | *regnop = **cPP - '0'; | |
1535 | (*cPP)++; | |
1536 | ||
1537 | if (! isalnum (**cPP)) | |
1538 | { | |
47926f60 | 1539 | /* No more digits, we're done. */ |
3bcbcc3d HPN |
1540 | return 1; |
1541 | } | |
1542 | else | |
1543 | { | |
1544 | /* One more digit. Consume and add. */ | |
47926f60 | 1545 | *regnop = *regnop * 10 + (**cPP - '0'); |
3bcbcc3d HPN |
1546 | |
1547 | /* We need to check for a valid register number; Rn, | |
1548 | 0 <= n <= MAX_REG. */ | |
1549 | if (*regnop <= MAX_REG) | |
1550 | { | |
1551 | /* Consume second digit. */ | |
1552 | (*cPP)++; | |
1553 | return 1; | |
1554 | } | |
1555 | } | |
1556 | } | |
1557 | break; | |
1558 | ||
1559 | case 'S': | |
1560 | case 's': | |
1561 | /* "S" as in "SP"? Consume the "S". */ | |
1562 | (*cPP)++; | |
1563 | if (**cPP == 'P' || **cPP == 'p') | |
1564 | { | |
1565 | /* It's "SP": consume the "p" and we're done. */ | |
1566 | (*cPP)++; | |
1567 | *regnop = REG_SP; | |
1568 | return 1; | |
1569 | } | |
1570 | break; | |
1571 | ||
1572 | default: | |
1573 | /* Just here to silence compilation warnings. */ | |
1574 | ; | |
1575 | } | |
1576 | ||
1577 | /* We get here if we fail. Restore the pointer. */ | |
1578 | *cPP = oldp; | |
1579 | return 0; | |
1580 | } | |
1581 | ||
3bcbcc3d HPN |
1582 | /* Get a special register from the string pointed out by *cPP. The |
1583 | variable *cPP is advanced to the character following the special | |
1584 | register name if one is found, and retains its original position | |
1585 | otherwise. | |
1586 | ||
1587 | cPP Pointer to pointer to string starting with a special register | |
1588 | name. | |
1589 | ||
1590 | sregpp Pointer to Pointer to struct spec_reg, where a pointer to the | |
1591 | register description will be stored. | |
1592 | ||
1593 | Return 1 iff a correct special register name is found. */ | |
1594 | ||
1595 | static int | |
1596 | get_spec_reg (cPP, sregpp) | |
1597 | char **cPP; | |
1598 | const struct cris_spec_reg **sregpp; | |
1599 | { | |
1600 | char *s1; | |
1601 | const char *s2; | |
7b15d668 | 1602 | char *name_begin = *cPP; |
3bcbcc3d HPN |
1603 | |
1604 | const struct cris_spec_reg *sregp; | |
1605 | ||
7b15d668 HPN |
1606 | /* Handle a sometimes-mandatory dollar sign as register prefix. */ |
1607 | if (*name_begin == REGISTER_PREFIX_CHAR) | |
1608 | name_begin++; | |
1609 | else if (demand_register_prefix) | |
1610 | return 0; | |
1611 | ||
3bcbcc3d | 1612 | /* Loop over all special registers. */ |
47926f60 | 1613 | for (sregp = cris_spec_regs; sregp->name != NULL; sregp++) |
3bcbcc3d | 1614 | { |
3bcbcc3d | 1615 | /* Start over from beginning of the supposed name. */ |
7b15d668 | 1616 | s1 = name_begin; |
3bcbcc3d HPN |
1617 | s2 = sregp->name; |
1618 | ||
1619 | while (*s2 != '\0' | |
1620 | && (isupper (*s1) ? tolower (*s1) == *s2 : *s1 == *s2)) | |
1621 | { | |
1622 | s1++; | |
1623 | s2++; | |
1624 | } | |
1625 | ||
1626 | /* For a match, we must have consumed the name in the table, and we | |
1627 | must be outside what could be part of a name. Assume here that a | |
47926f60 | 1628 | test for alphanumerics is sufficient for a name test. */ |
3bcbcc3d HPN |
1629 | if (*s2 == 0 && ! isalnum (*s1)) |
1630 | { | |
47926f60 | 1631 | /* We have a match. Update the pointer and be done. */ |
3bcbcc3d HPN |
1632 | *cPP = s1; |
1633 | *sregpp = sregp; | |
1634 | return 1; | |
1635 | } | |
1636 | } | |
1637 | ||
47926f60 | 1638 | /* If we got here, we did not find any name. */ |
3bcbcc3d HPN |
1639 | return 0; |
1640 | } | |
1641 | ||
3bcbcc3d HPN |
1642 | /* Get an unprefixed or side-effect-prefix operand from the string pointed |
1643 | out by *cPP. The pointer *cPP is advanced to the character following | |
1644 | the indirect operand if we have success, else it contains an undefined | |
1645 | value. | |
1646 | ||
1647 | cPP Pointer to pointer to string beginning with the first | |
1648 | character of the supposed operand. | |
1649 | ||
1650 | prefixp Pointer to structure containing an optional instruction | |
1651 | prefix. | |
1652 | ||
1653 | is_autoincp Pointer to int indicating the indirect or autoincrement | |
1654 | bits. | |
1655 | ||
1656 | src_regnop Pointer to int containing the source register number in | |
1657 | the instruction. | |
1658 | ||
1659 | imm_foundp Pointer to an int indicating if an immediate expression | |
1660 | is found. | |
1661 | ||
1662 | imm_exprP Pointer to a structure containing an immediate | |
1663 | expression, if success and if *imm_foundp is nonzero. | |
1664 | ||
1665 | Return 1 iff a correct indirect operand is found. */ | |
1666 | ||
1667 | static int | |
1668 | get_autoinc_prefix_or_indir_op (cPP, prefixp, is_autoincp, src_regnop, | |
1669 | imm_foundp, imm_exprP) | |
47926f60 KH |
1670 | char **cPP; |
1671 | struct cris_prefix *prefixp; | |
1672 | int *is_autoincp; | |
1673 | int *src_regnop; | |
1674 | int *imm_foundp; | |
1675 | expressionS *imm_exprP; | |
3bcbcc3d HPN |
1676 | { |
1677 | /* Assume there was no immediate mode expression. */ | |
1678 | *imm_foundp = 0; | |
1679 | ||
1680 | if (**cPP == '[') | |
1681 | { | |
1682 | /* So this operand is one of: | |
1683 | Indirect: [rN] | |
1684 | Autoincrement: [rN+] | |
1685 | Indexed with assign: [rN=rM+rO.S] | |
1686 | Offset with assign: [rN=rM+I], [rN=rM+[rO].s], [rN=rM+[rO+].s] | |
1687 | ||
1688 | Either way, consume the '['. */ | |
1689 | (*cPP)++; | |
1690 | ||
1691 | /* Get the rN register. */ | |
1692 | if (! get_gen_reg (cPP, src_regnop)) | |
1693 | /* If there was no register, then this cannot match. */ | |
1694 | return 0; | |
1695 | else | |
1696 | { | |
1697 | /* We got the register, now check the next character. */ | |
1698 | switch (**cPP) | |
1699 | { | |
1700 | case ']': | |
1701 | /* Indirect mode. We're done here. */ | |
1702 | prefixp->kind = PREFIX_NONE; | |
1703 | *is_autoincp = 0; | |
1704 | break; | |
1705 | ||
1706 | case '+': | |
1707 | /* This must be an auto-increment mode, if there's a | |
1708 | match. */ | |
1709 | prefixp->kind = PREFIX_NONE; | |
1710 | *is_autoincp = 1; | |
1711 | ||
1712 | /* We consume this character and break out to check the | |
1713 | closing ']'. */ | |
1714 | (*cPP)++; | |
1715 | break; | |
1716 | ||
1717 | case '=': | |
1718 | /* This must be indexed with assign, or offset with assign | |
1719 | to match. */ | |
1720 | (*cPP)++; | |
1721 | ||
1722 | /* Either way, the next thing must be a register. */ | |
1723 | if (! get_gen_reg (cPP, &prefixp->base_reg_number)) | |
1724 | /* No register, no match. */ | |
1725 | return 0; | |
1726 | else | |
1727 | { | |
1728 | /* We've consumed "[rN=rM", so we must be looking at | |
1729 | "+rO.s]" or "+I]", or "-I]", or "+[rO].s]" or | |
1730 | "+[rO+].s]". */ | |
1731 | if (**cPP == '+') | |
1732 | { | |
1733 | int index_reg_number; | |
1734 | (*cPP)++; | |
1735 | ||
1736 | if (**cPP == '[') | |
1737 | { | |
1738 | int size_bits; | |
1739 | /* This must be [rx=ry+[rz].s] or | |
1740 | [rx=ry+[rz+].s] or no match. We must be | |
1741 | looking at rz after consuming the '['. */ | |
1742 | (*cPP)++; | |
1743 | ||
1744 | if (!get_gen_reg (cPP, &index_reg_number)) | |
1745 | return 0; | |
1746 | ||
1747 | prefixp->kind = PREFIX_BDAP; | |
1748 | prefixp->opcode | |
1749 | = (BDAP_INDIR_OPCODE | |
1750 | + (prefixp->base_reg_number << 12) | |
1751 | + index_reg_number); | |
1752 | ||
1753 | if (**cPP == '+') | |
1754 | { | |
1755 | /* We've seen "[rx=ry+[rz+" here, so now we | |
1756 | know that there must be "].s]" left to | |
1757 | check. */ | |
1758 | (*cPP)++; | |
1759 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
1760 | } | |
1761 | ||
1762 | /* If it wasn't autoincrement, we don't need to | |
1763 | add anything. */ | |
1764 | ||
1765 | /* Check the next-to-last ']'. */ | |
1766 | if (**cPP != ']') | |
1767 | return 0; | |
1768 | ||
1769 | (*cPP)++; | |
1770 | ||
1771 | /* Check the ".s" modifier. */ | |
1772 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
1773 | return 0; | |
1774 | ||
1775 | prefixp->opcode |= size_bits << 4; | |
1776 | ||
1777 | /* Now we got [rx=ry+[rz+].s or [rx=ry+[rz].s. | |
1778 | We break out to check the final ']'. */ | |
1779 | break; | |
1780 | } | |
ab3e48dc KH |
1781 | /* It wasn't an indirection. Check if it's a |
1782 | register. */ | |
1783 | else if (get_gen_reg (cPP, &index_reg_number)) | |
47926f60 KH |
1784 | { |
1785 | int size_bits; | |
1786 | ||
1787 | /* Indexed with assign mode: "[rN+rM.S]". */ | |
1788 | prefixp->kind = PREFIX_BIAP; | |
1789 | prefixp->opcode | |
1790 | = (BIAP_OPCODE + (index_reg_number << 12) | |
1791 | + prefixp->base_reg_number /* << 0 */); | |
1792 | ||
1793 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
1794 | /* Size missing, this isn't a match. */ | |
1795 | return 0; | |
1796 | else | |
3bcbcc3d | 1797 | { |
47926f60 | 1798 | /* Size found, break out to check the |
3bcbcc3d | 1799 | final ']'. */ |
47926f60 | 1800 | prefixp->opcode |= size_bits << 4; |
3bcbcc3d HPN |
1801 | break; |
1802 | } | |
47926f60 KH |
1803 | } |
1804 | /* Not a register. Then this must be "[rN+I]". */ | |
1805 | else if (cris_get_expression (cPP, &prefixp->expr)) | |
1806 | { | |
1807 | /* We've got offset with assign mode. Fill | |
1808 | in the blanks and break out to match the | |
1809 | final ']'. */ | |
1810 | prefixp->kind = PREFIX_BDAP_IMM; | |
1811 | break; | |
1812 | } | |
1813 | else | |
1814 | /* Neither register nor expression found, so | |
1815 | this can't be a match. */ | |
1816 | return 0; | |
3bcbcc3d | 1817 | } |
47926f60 | 1818 | /* Not "[rN+" but perhaps "[rN-"? */ |
ab3e48dc | 1819 | else if (**cPP == '-') |
47926f60 KH |
1820 | { |
1821 | /* We must have an offset with assign mode. */ | |
1822 | if (! cris_get_expression (cPP, &prefixp->expr)) | |
1823 | /* No expression, no match. */ | |
1824 | return 0; | |
1825 | else | |
1826 | { | |
1827 | /* We've got offset with assign mode. Fill | |
1828 | in the blanks and break out to match the | |
1829 | final ']'. */ | |
1830 | prefixp->kind = PREFIX_BDAP_IMM; | |
1831 | break; | |
1832 | } | |
1833 | } | |
1834 | else | |
1835 | /* Neither '+' nor '-' after "[rN=rM". Lose. */ | |
1836 | return 0; | |
3bcbcc3d HPN |
1837 | } |
1838 | default: | |
1839 | /* Neither ']' nor '+' nor '=' after "[rN". Lose. */ | |
1840 | return 0; | |
1841 | } | |
1842 | } | |
1843 | ||
1844 | /* When we get here, we have a match and will just check the closing | |
1845 | ']'. We can still fail though. */ | |
1846 | if (**cPP != ']') | |
1847 | return 0; | |
1848 | else | |
1849 | { | |
1850 | /* Don't forget to consume the final ']'. | |
1851 | Then return in glory. */ | |
1852 | (*cPP)++; | |
1853 | return 1; | |
1854 | } | |
1855 | } | |
47926f60 | 1856 | /* No indirection. Perhaps a constant? */ |
ab3e48dc | 1857 | else if (cris_get_expression (cPP, imm_exprP)) |
47926f60 KH |
1858 | { |
1859 | /* Expression found, this is immediate mode. */ | |
1860 | prefixp->kind = PREFIX_NONE; | |
1861 | *is_autoincp = 1; | |
1862 | *src_regnop = REG_PC; | |
1863 | *imm_foundp = 1; | |
1864 | return 1; | |
1865 | } | |
3bcbcc3d HPN |
1866 | |
1867 | /* No luck today. */ | |
1868 | return 0; | |
1869 | } | |
1870 | ||
3bcbcc3d HPN |
1871 | /* This function gets an indirect operand in a three-address operand |
1872 | combination from the string pointed out by *cPP. The pointer *cPP is | |
1873 | advanced to the character following the indirect operand on success, or | |
1874 | has an unspecified value on failure. | |
1875 | ||
1876 | cPP Pointer to pointer to string begining | |
1877 | with the operand | |
1878 | ||
1879 | prefixp Pointer to structure containing an | |
1880 | instruction prefix | |
1881 | ||
1882 | Returns 1 iff a correct indirect operand is found. */ | |
1883 | ||
1884 | static int | |
1885 | get_3op_or_dip_prefix_op (cPP, prefixp) | |
1886 | char **cPP; | |
1887 | struct cris_prefix *prefixp; | |
1888 | { | |
ab3e48dc KH |
1889 | int reg_number; |
1890 | ||
3bcbcc3d HPN |
1891 | if (**cPP != '[') |
1892 | /* We must have a '[' or it's a clean failure. */ | |
1893 | return 0; | |
3bcbcc3d | 1894 | |
47926f60 KH |
1895 | /* Eat the first '['. */ |
1896 | (*cPP)++; | |
1897 | ||
1898 | if (**cPP == '[') | |
1899 | { | |
1900 | /* A second '[', so this must be double-indirect mode. */ | |
3bcbcc3d | 1901 | (*cPP)++; |
47926f60 KH |
1902 | prefixp->kind = PREFIX_DIP; |
1903 | prefixp->opcode = DIP_OPCODE; | |
3bcbcc3d | 1904 | |
47926f60 KH |
1905 | /* Get the register or fail entirely. */ |
1906 | if (! get_gen_reg (cPP, ®_number)) | |
1907 | return 0; | |
1908 | else | |
3bcbcc3d | 1909 | { |
47926f60 KH |
1910 | prefixp->opcode |= reg_number /* << 0 */ ; |
1911 | if (**cPP == '+') | |
1912 | { | |
1913 | /* Since we found a '+', this must be double-indirect | |
1914 | autoincrement mode. */ | |
1915 | (*cPP)++; | |
1916 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
1917 | } | |
1918 | ||
1919 | /* There's nothing particular to do, if this was a | |
1920 | double-indirect *without* autoincrement. */ | |
1921 | } | |
1922 | ||
1923 | /* Check the first ']'. The second one is checked at the end. */ | |
1924 | if (**cPP != ']') | |
1925 | return 0; | |
1926 | ||
1927 | /* Eat the first ']', so we'll be looking at a second ']'. */ | |
1928 | (*cPP)++; | |
1929 | } | |
1930 | /* No second '['. Then we should have a register here, making | |
1931 | it "[rN". */ | |
1932 | else if (get_gen_reg (cPP, &prefixp->base_reg_number)) | |
1933 | { | |
1934 | /* This must be indexed or offset mode: "[rN+I]" or | |
1935 | "[rN+rM.S]" or "[rN+[rM].S]" or "[rN+[rM+].S]". */ | |
1936 | if (**cPP == '+') | |
1937 | { | |
1938 | /* Not the first alternative, must be one of the last | |
1939 | three. */ | |
1940 | int index_reg_number; | |
1941 | ||
3bcbcc3d | 1942 | (*cPP)++; |
3bcbcc3d | 1943 | |
47926f60 | 1944 | if (**cPP == '[') |
3bcbcc3d | 1945 | { |
47926f60 KH |
1946 | /* This is "[rx+["... Expect a register next. */ |
1947 | int size_bits; | |
1948 | (*cPP)++; | |
1949 | ||
1950 | if (!get_gen_reg (cPP, &index_reg_number)) | |
1951 | return 0; | |
1952 | ||
1953 | prefixp->kind = PREFIX_BDAP; | |
1954 | prefixp->opcode | |
1955 | = (BDAP_INDIR_OPCODE | |
1956 | + (prefixp->base_reg_number << 12) | |
1957 | + index_reg_number); | |
1958 | ||
1959 | /* We've seen "[rx+[ry", so check if this is | |
1960 | autoincrement. */ | |
3bcbcc3d HPN |
1961 | if (**cPP == '+') |
1962 | { | |
47926f60 | 1963 | /* Yep, now at "[rx+[ry+". */ |
3bcbcc3d HPN |
1964 | (*cPP)++; |
1965 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
1966 | } | |
47926f60 KH |
1967 | /* If it wasn't autoincrement, we don't need to |
1968 | add anything. */ | |
3bcbcc3d | 1969 | |
47926f60 KH |
1970 | /* Check a first closing ']': "[rx+[ry]" or |
1971 | "[rx+[ry+]". */ | |
1972 | if (**cPP != ']') | |
1973 | return 0; | |
1974 | (*cPP)++; | |
3bcbcc3d | 1975 | |
47926f60 KH |
1976 | /* Now expect a size modifier ".S". */ |
1977 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
1978 | return 0; | |
3bcbcc3d | 1979 | |
47926f60 KH |
1980 | prefixp->opcode |= size_bits << 4; |
1981 | ||
1982 | /* Ok, all interesting stuff has been seen: | |
1983 | "[rx+[ry+].S" or "[rx+[ry].S". We only need to | |
1984 | expect a final ']', which we'll do in a common | |
1985 | closing session. */ | |
1986 | } | |
1987 | /* Seen "[rN+", but not a '[', so check if we have a | |
1988 | register. */ | |
1989 | else if (get_gen_reg (cPP, &index_reg_number)) | |
1990 | { | |
1991 | /* This is indexed mode: "[rN+rM.S]" or | |
1992 | "[rN+rM.S+]". */ | |
1993 | int size_bits; | |
1994 | prefixp->kind = PREFIX_BIAP; | |
1995 | prefixp->opcode | |
1996 | = (BIAP_OPCODE | |
1997 | | prefixp->base_reg_number /* << 0 */ | |
1998 | | (index_reg_number << 12)); | |
1999 | ||
07e90ad5 | 2000 | /* Consume the ".S". */ |
47926f60 KH |
2001 | if (! get_bwd_size_modifier (cPP, &size_bits)) |
2002 | /* Missing size, so fail. */ | |
2003 | return 0; | |
3bcbcc3d | 2004 | else |
47926f60 KH |
2005 | /* Size found. Add that piece and drop down to |
2006 | the common checking of the closing ']'. */ | |
2007 | prefixp->opcode |= size_bits << 4; | |
2008 | } | |
2009 | /* Seen "[rN+", but not a '[' or a register, so then | |
2010 | it must be a constant "I". */ | |
2011 | else if (cris_get_expression (cPP, &prefixp->expr)) | |
2012 | { | |
2013 | /* Expression found, so fill in the bits of offset | |
2014 | mode and drop down to check the closing ']'. */ | |
2015 | prefixp->kind = PREFIX_BDAP_IMM; | |
2016 | } | |
2017 | else | |
2018 | /* Nothing valid here: lose. */ | |
2019 | return 0; | |
2020 | } | |
2021 | /* Seen "[rN" but no '+', so check if it's a '-'. */ | |
2022 | else if (**cPP == '-') | |
2023 | { | |
2024 | /* Yep, we must have offset mode. */ | |
2025 | if (! cris_get_expression (cPP, &prefixp->expr)) | |
2026 | /* No expression, so we lose. */ | |
2027 | return 0; | |
2028 | else | |
2029 | { | |
2030 | /* Expression found to make this offset mode, so | |
2031 | fill those bits and drop down to check the | |
2032 | closing ']'. */ | |
2033 | prefixp->kind = PREFIX_BDAP_IMM; | |
2034 | } | |
2035 | } | |
2036 | else | |
2037 | { | |
2038 | /* We've seen "[rN", but not '+' or '-'; rather a ']'. | |
2039 | Hmm. Normally this is a simple indirect mode that we | |
2040 | shouldn't match, but if we expect ']', then we have a | |
2041 | zero offset, so it can be a three-address-operand, | |
2042 | like "[rN],rO,rP", thus offset mode. | |
2043 | ||
2044 | Don't eat the ']', that will be done in the closing | |
2045 | ceremony. */ | |
2046 | prefixp->expr.X_op = O_constant; | |
2047 | prefixp->expr.X_add_number = 0; | |
2048 | prefixp->expr.X_add_symbol = NULL; | |
2049 | prefixp->expr.X_op_symbol = NULL; | |
2050 | prefixp->kind = PREFIX_BDAP_IMM; | |
2051 | } | |
2052 | } | |
2053 | /* A '[', but no second '[', and no register. Check if we | |
2054 | have an expression, making this "[I]" for a double-indirect | |
2055 | prefix. */ | |
2056 | else if (cris_get_expression (cPP, &prefixp->expr)) | |
2057 | { | |
2058 | /* Expression found, the so called absolute mode for a | |
2059 | double-indirect prefix on PC. */ | |
2060 | prefixp->kind = PREFIX_DIP; | |
2061 | prefixp->opcode = DIP_OPCODE | (AUTOINCR_BIT << 8) | REG_PC; | |
2062 | prefixp->reloc = BFD_RELOC_32; | |
2063 | } | |
2064 | else | |
2065 | /* Neither '[' nor register nor expression. We lose. */ | |
2066 | return 0; | |
3bcbcc3d HPN |
2067 | |
2068 | /* We get here as a closing ceremony to a successful match. We just | |
2069 | need to check the closing ']'. */ | |
2070 | if (**cPP != ']') | |
2071 | /* Oops. Close but no air-polluter. */ | |
2072 | return 0; | |
2073 | ||
2074 | /* Don't forget to consume that ']', before returning in glory. */ | |
2075 | (*cPP)++; | |
2076 | return 1; | |
2077 | } | |
2078 | ||
3bcbcc3d HPN |
2079 | /* Get an expression from the string pointed out by *cPP. |
2080 | The pointer *cPP is advanced to the character following the expression | |
2081 | on a success, or retains its original value otherwise. | |
2082 | ||
2083 | cPP Pointer to pointer to string beginning with the expression. | |
2084 | ||
2085 | exprP Pointer to structure containing the expression. | |
2086 | ||
47926f60 | 2087 | Return 1 iff a correct expression is found. */ |
3bcbcc3d HPN |
2088 | |
2089 | static int | |
2090 | cris_get_expression (cPP, exprP) | |
47926f60 KH |
2091 | char **cPP; |
2092 | expressionS *exprP; | |
3bcbcc3d HPN |
2093 | { |
2094 | char *saved_input_line_pointer; | |
2095 | segT exp; | |
2096 | ||
2097 | /* The "expression" function expects to find an expression at the | |
2098 | global variable input_line_pointer, so we have to save it to give | |
2099 | the impression that we don't fiddle with global variables. */ | |
2100 | saved_input_line_pointer = input_line_pointer; | |
2101 | input_line_pointer = *cPP; | |
2102 | ||
2103 | exp = expression (exprP); | |
2104 | if (exprP->X_op == O_illegal || exprP->X_op == O_absent) | |
2105 | { | |
2106 | input_line_pointer = saved_input_line_pointer; | |
2107 | return 0; | |
2108 | } | |
2109 | ||
2110 | /* Everything seems to be fine, just restore the global | |
2111 | input_line_pointer and say we're successful. */ | |
2112 | *cPP = input_line_pointer; | |
2113 | input_line_pointer = saved_input_line_pointer; | |
2114 | return 1; | |
2115 | } | |
2116 | ||
3bcbcc3d HPN |
2117 | /* Get a sequence of flag characters from *spp. The pointer *cPP is |
2118 | advanced to the character following the expression. The flag | |
2119 | characters are consecutive, no commas or spaces. | |
2120 | ||
2121 | cPP Pointer to pointer to string beginning with the expression. | |
2122 | ||
2123 | flagp Pointer to int to return the flags expression. | |
2124 | ||
2125 | Return 1 iff a correct flags expression is found. */ | |
2126 | ||
2127 | static int | |
2128 | get_flags (cPP, flagsp) | |
2129 | char **cPP; | |
2130 | int *flagsp; | |
2131 | { | |
2132 | for (;;) | |
2133 | { | |
2134 | switch (**cPP) | |
2135 | { | |
2136 | case 'd': | |
2137 | case 'D': | |
2138 | case 'm': | |
2139 | case 'M': | |
2140 | *flagsp |= 0x80; | |
2141 | break; | |
2142 | ||
2143 | case 'e': | |
2144 | case 'E': | |
2145 | case 'b': | |
2146 | case 'B': | |
2147 | *flagsp |= 0x40; | |
2148 | break; | |
2149 | ||
2150 | case 'i': | |
2151 | case 'I': | |
2152 | *flagsp |= 0x20; | |
2153 | break; | |
2154 | ||
2155 | case 'x': | |
2156 | case 'X': | |
2157 | *flagsp |= 0x10; | |
2158 | break; | |
2159 | ||
2160 | case 'n': | |
2161 | case 'N': | |
2162 | *flagsp |= 0x8; | |
2163 | break; | |
2164 | ||
2165 | case 'z': | |
2166 | case 'Z': | |
2167 | *flagsp |= 0x4; | |
2168 | break; | |
2169 | ||
2170 | case 'v': | |
2171 | case 'V': | |
2172 | *flagsp |= 0x2; | |
2173 | break; | |
2174 | ||
2175 | case 'c': | |
2176 | case 'C': | |
2177 | *flagsp |= 1; | |
2178 | break; | |
2179 | ||
2180 | default: | |
2181 | /* We consider this successful if we stop at a comma or | |
47926f60 | 2182 | whitespace. Anything else, and we consider it a failure. */ |
3bcbcc3d HPN |
2183 | if (**cPP != ',' |
2184 | && **cPP != 0 | |
2185 | && ! isspace (**cPP)) | |
2186 | return 0; | |
2187 | else | |
2188 | return 1; | |
2189 | } | |
2190 | ||
2191 | /* Don't forget to consume each flag character. */ | |
2192 | (*cPP)++; | |
2193 | } | |
2194 | } | |
2195 | ||
3bcbcc3d HPN |
2196 | /* Generate code and fixes for a BDAP prefix. |
2197 | ||
2198 | base_regno Int containing the base register number. | |
2199 | ||
2200 | exprP Pointer to structure containing the offset expression. */ | |
2201 | ||
2202 | static void | |
2203 | gen_bdap (base_regno, exprP) | |
47926f60 KH |
2204 | int base_regno; |
2205 | expressionS *exprP; | |
3bcbcc3d HPN |
2206 | { |
2207 | unsigned int opcode; | |
2208 | char *opcodep; | |
2209 | ||
2210 | /* Put out the prefix opcode; assume quick immediate mode at first. */ | |
2211 | opcode = BDAP_QUICK_OPCODE | (base_regno << 12); | |
2212 | opcodep = frag_more (2); | |
2213 | md_number_to_chars (opcodep, opcode, 2); | |
2214 | ||
2215 | if (exprP->X_op == O_constant) | |
2216 | { | |
2217 | /* We have an absolute expression that we know the size of right | |
47926f60 | 2218 | now. */ |
3bcbcc3d HPN |
2219 | long int value; |
2220 | int size; | |
2221 | ||
2222 | value = exprP->X_add_number; | |
2223 | if (value < -32768 || value > 32767) | |
2224 | /* Outside range for a "word", make it a dword. */ | |
2225 | size = 2; | |
2226 | else | |
47926f60 | 2227 | /* Assume "word" size. */ |
3bcbcc3d HPN |
2228 | size = 1; |
2229 | ||
2230 | /* If this is a signed-byte value, we can fit it into the prefix | |
2231 | insn itself. */ | |
2232 | if (value >= -128 && value <= 127) | |
2233 | opcodep[0] = value; | |
2234 | else | |
2235 | { | |
2236 | /* This is a word or dword displacement, which will be put in a | |
2237 | word or dword after the prefix. */ | |
2238 | char *p; | |
2239 | ||
2240 | opcodep[0] = BDAP_PC_LOW + (size << 4); | |
2241 | opcodep[1] &= 0xF0; | |
2242 | opcodep[1] |= BDAP_INCR_HIGH; | |
2243 | p = frag_more (1 << size); | |
2244 | md_number_to_chars (p, value, 1 << size); | |
2245 | } | |
2246 | } | |
2247 | else | |
2248 | /* The expression is not defined yet but may become absolute. We make | |
2249 | it a relocation to be relaxed. */ | |
47926f60 KH |
2250 | frag_var (rs_machine_dependent, 4, 0, |
2251 | ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF), | |
2252 | exprP->X_add_symbol, exprP->X_add_number, opcodep); | |
3bcbcc3d HPN |
2253 | } |
2254 | ||
3bcbcc3d HPN |
2255 | /* Encode a branch displacement in the range -256..254 into the form used |
2256 | by CRIS conditional branch instructions. | |
2257 | ||
2258 | offset The displacement value in bytes. */ | |
2259 | ||
2260 | static int | |
2261 | branch_disp (offset) | |
2262 | int offset; | |
2263 | { | |
2264 | int disp; | |
2265 | ||
2266 | disp = offset & 0xFE; | |
2267 | ||
2268 | if (offset < 0) | |
2269 | disp |= 1; | |
2270 | ||
2271 | return disp; | |
2272 | } | |
2273 | ||
3bcbcc3d HPN |
2274 | /* Generate code and fixes for a 32-bit conditional branch instruction |
2275 | created by "extending" an existing 8-bit branch instruction. | |
2276 | ||
2277 | opcodep Pointer to the word containing the original 8-bit branch | |
2278 | instruction. | |
2279 | ||
2280 | writep Pointer to "extension area" following the first instruction | |
2281 | word. | |
2282 | ||
2283 | fragP Pointer to the frag containing the instruction. | |
2284 | ||
2285 | add_symP, Parts of the destination address expression. | |
2286 | sub_symP, | |
2287 | add_num. */ | |
2288 | ||
2289 | static void | |
2290 | gen_cond_branch_32 (opcodep, writep, fragP, add_symP, sub_symP, add_num) | |
2291 | char *opcodep; | |
2292 | char *writep; | |
2293 | fragS *fragP; | |
2294 | symbolS *add_symP; | |
2295 | symbolS *sub_symP; | |
2296 | long int add_num; | |
2297 | { | |
2298 | if (warn_for_branch_expansion) | |
2299 | { | |
2300 | /* FIXME: Find out and change to as_warn_where. Add testcase. */ | |
2301 | as_warn (_("32-bit conditional branch generated")); | |
2302 | } | |
2303 | ||
2304 | /* Here, writep points to what will be opcodep + 2. First, we change | |
2305 | the actual branch in opcodep[0] and opcodep[1], so that in the | |
2306 | final insn, it will look like: | |
2307 | opcodep+10: Bcc .-6 | |
2308 | ||
2309 | This means we don't have to worry about changing the opcode or | |
2310 | messing with te delay-slot instruction. So, we move it to last in | |
2311 | the "extended" branch, and just change the displacement. Admittedly, | |
2312 | it's not the optimal extended construct, but we should get this | |
2313 | rarely enough that it shouldn't matter. */ | |
2314 | ||
47926f60 | 2315 | writep[8] = branch_disp (-2 - 6); |
3bcbcc3d HPN |
2316 | writep[9] = opcodep[1]; |
2317 | ||
2318 | /* Then, we change the branch to an unconditional branch over the | |
2319 | extended part, to the new location of the Bcc: | |
2320 | opcodep: BA .+10 | |
2321 | opcodep+2: NOP | |
2322 | ||
2323 | Note that these two writes are to currently different locations, | |
2324 | merged later. */ | |
2325 | ||
2326 | md_number_to_chars (opcodep, BA_QUICK_OPCODE + 8, 2); | |
2327 | md_number_to_chars (writep, NOP_OPCODE, 2); | |
2328 | ||
2329 | /* Then the extended thing, the 32-bit jump insn. | |
2330 | opcodep+4: JUMP [PC+] */ | |
2331 | ||
2332 | md_number_to_chars (writep + 2, JUMP_PC_INCR_OPCODE, 2); | |
2333 | ||
2334 | /* We have to fill in the actual value too. | |
2335 | opcodep+6: .DWORD | |
2336 | This is most probably an expression, but we can cope with an absolute | |
2337 | value too. FIXME: Testcase needed. */ | |
2338 | ||
2339 | if (add_symP == NULL && sub_symP == NULL) | |
2340 | /* An absolute address. */ | |
2341 | md_number_to_chars (writep + 4, add_num, 4); | |
2342 | else | |
2343 | { | |
47926f60 | 2344 | /* Not absolute, we have to make it a frag for later evaluation. */ |
3bcbcc3d HPN |
2345 | know (sub_symP == 0); |
2346 | ||
2347 | fix_new (fragP, writep + 4 - fragP->fr_literal, 4, add_symP, | |
2348 | add_num, 0, BFD_RELOC_32); | |
2349 | } | |
2350 | } | |
2351 | ||
3bcbcc3d HPN |
2352 | /* This *could* be: |
2353 | ||
47926f60 KH |
2354 | Turn a string in input_line_pointer into a floating point constant |
2355 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
2356 | of LITTLENUMS emitted is stored in *SIZEP. | |
3bcbcc3d HPN |
2357 | |
2358 | type A character from FLTCHARS that describes what kind of | |
2359 | floating-point number is wanted. | |
2360 | ||
2361 | litp A pointer to an array that the result should be stored in. | |
2362 | ||
2363 | sizep A pointer to an integer where the size of the result is stored. | |
2364 | ||
2365 | But we don't support floating point constants in assembly code *at all*, | |
2366 | since it's suboptimal and just opens up bug opportunities. GCC emits | |
2367 | the bit patterns as hex. All we could do here is to emit what GCC | |
2368 | would have done in the first place. *Nobody* writes floating-point | |
2369 | code as assembly code, but if they do, they should be able enough to | |
2370 | find out the correct bit patterns and use them. */ | |
2371 | ||
2372 | char * | |
2373 | md_atof (type, litp, sizep) | |
2374 | char type ATTRIBUTE_UNUSED; | |
2375 | char *litp ATTRIBUTE_UNUSED; | |
47926f60 | 2376 | int *sizep ATTRIBUTE_UNUSED; |
3bcbcc3d HPN |
2377 | { |
2378 | /* FIXME: Is this function mentioned in the internals.texi manual? If | |
2379 | not, add it. */ | |
2380 | return _("Bad call to md_atof () - floating point formats are not supported"); | |
2381 | } | |
2382 | ||
3bcbcc3d HPN |
2383 | /* Turn a number as a fixS * into a series of bytes that represents the |
2384 | number on the target machine. The purpose of this procedure is the | |
2385 | same as that of md_number_to_chars but this procedure is supposed to | |
2386 | handle general bit field fixes and machine-dependent fixups. | |
2387 | ||
2388 | bufp Pointer to an array where the result should be stored. | |
2389 | ||
2390 | val The value to store. | |
2391 | ||
2392 | n The number of bytes in "val" that should be stored. | |
2393 | ||
47926f60 | 2394 | fixP The fix to be applied to the bit field starting at bufp. */ |
3bcbcc3d HPN |
2395 | |
2396 | static void | |
2397 | cris_number_to_imm (bufp, val, n, fixP) | |
2398 | char *bufp; | |
2399 | long val; | |
2400 | int n; | |
2401 | fixS *fixP; | |
2402 | { | |
2403 | segT sym_seg; | |
2404 | ||
2405 | know (n <= 4); | |
2406 | know (fixP); | |
2407 | ||
2408 | /* We put the relative "vma" for the other segment for inter-segment | |
2409 | relocations in the object data to stay binary "compatible" (with an | |
2410 | uninteresting old version) for the relocation. | |
2411 | Maybe delete some day. */ | |
2412 | if (fixP->fx_addsy | |
2413 | && (sym_seg = S_GET_SEGMENT (fixP->fx_addsy)) != now_seg) | |
2414 | val += sym_seg->vma; | |
2415 | ||
2416 | switch (fixP->fx_r_type) | |
2417 | { | |
2418 | /* Ditto here, we put the addend into the object code as | |
2419 | well as the reloc addend. Keep it that way for now, to simplify | |
2420 | regression tests on the object file contents. FIXME: Seems | |
2421 | uninteresting now that we have a test suite. */ | |
2422 | ||
2423 | case BFD_RELOC_32: | |
2424 | /* No use having warnings here, since most hosts have a 32-bit type | |
2425 | for "long" (which will probably change soon, now that I wrote | |
2426 | this). */ | |
2427 | bufp[3] = (val >> 24) & 0xFF; | |
2428 | bufp[2] = (val >> 16) & 0xFF; | |
2429 | bufp[1] = (val >> 8) & 0xFF; | |
2430 | bufp[0] = val & 0xFF; | |
2431 | break; | |
2432 | ||
2433 | /* FIXME: The 16 and 8-bit cases should have a way to check | |
2434 | whether a signed or unsigned (or any signedness) number is | |
2435 | accepted. | |
2436 | FIXME: Does the as_bad calls find the line number by themselves, | |
2437 | or should we change them into as_bad_where? */ | |
2438 | ||
2439 | case BFD_RELOC_16: | |
2440 | if (val > 0xffff || val < -32768) | |
2441 | as_bad (_("Value not in 16 bit range: %ld"), val); | |
2442 | if (! fixP->fx_addsy) | |
2443 | { | |
2444 | bufp[1] = (val >> 8) & 0xFF; | |
2445 | bufp[0] = val & 0xFF; | |
2446 | } | |
2447 | break; | |
2448 | ||
2449 | case BFD_RELOC_8: | |
2450 | if (val > 255 || val < -128) | |
2451 | as_bad (_("Value not in 8 bit range: %ld"), val); | |
2452 | if (! fixP->fx_addsy) | |
2453 | bufp[0] = val & 0xFF; | |
2454 | break; | |
2455 | ||
2456 | case BFD_RELOC_CRIS_UNSIGNED_4: | |
2457 | if (val > 15 || val < 0) | |
2458 | as_bad (_("Value not in 4 bit unsigned range: %ld"), val); | |
2459 | if (! fixP->fx_addsy) | |
2460 | bufp[0] |= val & 0x0F; | |
2461 | break; | |
2462 | ||
2463 | case BFD_RELOC_CRIS_UNSIGNED_5: | |
2464 | if (val > 31 || val < 0) | |
2465 | as_bad (_("Value not in 5 bit unsigned range: %ld"), val); | |
2466 | if (! fixP->fx_addsy) | |
2467 | bufp[0] |= val & 0x1F; | |
2468 | break; | |
2469 | ||
2470 | case BFD_RELOC_CRIS_SIGNED_6: | |
2471 | if (val > 31 || val < -32) | |
2472 | as_bad (_("Value not in 6 bit range: %ld"), val); | |
2473 | if (! fixP->fx_addsy) | |
2474 | bufp[0] |= val & 0x3F; | |
2475 | break; | |
2476 | ||
2477 | case BFD_RELOC_CRIS_UNSIGNED_6: | |
2478 | if (val > 63 || val < 0) | |
2479 | as_bad (_("Value not in 6 bit unsigned range: %ld"), val); | |
2480 | if (! fixP->fx_addsy) | |
2481 | bufp[0] |= val & 0x3F; | |
2482 | break; | |
2483 | ||
2484 | case BFD_RELOC_CRIS_BDISP8: | |
2485 | if (! fixP->fx_addsy) | |
2486 | bufp[0] = branch_disp (val); | |
2487 | break; | |
2488 | ||
2489 | case BFD_RELOC_NONE: | |
2490 | /* May actually happen automatically. For example at broken | |
2491 | words, if the word turns out not to be broken. | |
47926f60 | 2492 | FIXME: When? Which testcase? */ |
3bcbcc3d HPN |
2493 | if (! fixP->fx_addsy) |
2494 | md_number_to_chars (bufp, val, n); | |
2495 | break; | |
2496 | ||
2497 | case BFD_RELOC_VTABLE_INHERIT: | |
2498 | /* This borrowed from tc-ppc.c on a whim. */ | |
2499 | if (fixP->fx_addsy | |
2500 | && !S_IS_DEFINED (fixP->fx_addsy) | |
2501 | && !S_IS_WEAK (fixP->fx_addsy)) | |
2502 | S_SET_WEAK (fixP->fx_addsy); | |
7b15d668 HPN |
2503 | /* Fall through. */ |
2504 | ||
3bcbcc3d | 2505 | case BFD_RELOC_VTABLE_ENTRY: |
3bcbcc3d HPN |
2506 | fixP->fx_done = 0; |
2507 | break; | |
2508 | ||
2509 | default: | |
2510 | BAD_CASE (fixP->fx_r_type); | |
2511 | } | |
2512 | } | |
2513 | ||
3bcbcc3d HPN |
2514 | /* Processes machine-dependent command line options. Called once for |
2515 | each option on the command line that the machine-independent part of | |
2516 | GAS does not understand. */ | |
47926f60 | 2517 | |
3bcbcc3d HPN |
2518 | int |
2519 | md_parse_option (arg, argp) | |
2520 | int arg; | |
2521 | char *argp ATTRIBUTE_UNUSED; | |
2522 | { | |
2523 | switch (arg) | |
2524 | { | |
2525 | case 'H': | |
2526 | case 'h': | |
7b15d668 | 2527 | printf (_("Please use --help to see usage and options for this assembler.\n")); |
3bcbcc3d | 2528 | md_show_usage (stdout); |
7b15d668 | 2529 | exit (EXIT_SUCCESS); |
3bcbcc3d HPN |
2530 | |
2531 | case 'N': | |
2532 | warn_for_branch_expansion = 1; | |
2533 | return 1; | |
2534 | ||
7b15d668 HPN |
2535 | case OPTION_NO_US: |
2536 | demand_register_prefix = true; | |
2537 | ||
2538 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
2539 | as_bad (_("--no-underscore is invalid with a.out format"), arg); | |
2540 | else | |
2541 | symbols_have_leading_underscore = false; | |
2542 | return 1; | |
2543 | ||
2544 | case OPTION_US: | |
2545 | demand_register_prefix = false; | |
2546 | symbols_have_leading_underscore = true; | |
2547 | return 1; | |
2548 | ||
3bcbcc3d HPN |
2549 | default: |
2550 | return 0; | |
47926f60 | 2551 | } |
3bcbcc3d HPN |
2552 | } |
2553 | ||
2554 | /* Round up a section size to the appropriate boundary. */ | |
2555 | valueT | |
2556 | md_section_align (segment, size) | |
2557 | segT segment; | |
2558 | valueT size; | |
2559 | { | |
2560 | /* Round all sects to multiple of 4, except the bss section, which | |
2561 | we'll round to word-size. | |
2562 | ||
2563 | FIXME: Check if this really matters. All sections should be | |
2564 | rounded up, and all sections should (optionally) be assumed to be | |
2565 | dword-aligned, it's just that there is actual usage of linking to a | |
2566 | multiple of two. */ | |
2567 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
2568 | { | |
2569 | if (segment == bss_section) | |
2570 | return (size + 1) & ~1; | |
2571 | return (size + 3) & ~3; | |
2572 | } | |
2573 | else | |
2574 | { | |
2575 | /* FIXME: Is this wanted? It matches the testsuite, but that's not | |
2576 | really a valid reason. */ | |
2577 | if (segment == text_section) | |
2578 | return (size + 3) & ~3; | |
2579 | } | |
2580 | ||
2581 | return size; | |
2582 | } | |
2583 | ||
3bcbcc3d HPN |
2584 | /* Generate a machine-dependent relocation. */ |
2585 | arelent * | |
2586 | tc_gen_reloc (section, fixP) | |
2587 | asection *section ATTRIBUTE_UNUSED; | |
2588 | fixS *fixP; | |
2589 | { | |
2590 | arelent *relP; | |
2591 | bfd_reloc_code_real_type code; | |
2592 | ||
2593 | switch (fixP->fx_r_type) | |
2594 | { | |
2595 | case BFD_RELOC_32: | |
2596 | case BFD_RELOC_16: | |
2597 | case BFD_RELOC_8: | |
2598 | case BFD_RELOC_VTABLE_INHERIT: | |
2599 | case BFD_RELOC_VTABLE_ENTRY: | |
2600 | code = fixP->fx_r_type; | |
2601 | break; | |
2602 | default: | |
2603 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2604 | _("Semantics error. This type of operand can not be relocated, it must be an assembly-time constant")); | |
2605 | return 0; | |
2606 | } | |
2607 | ||
2608 | relP = (arelent *) xmalloc (sizeof (arelent)); | |
2609 | assert (relP != 0); | |
2610 | relP->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
2611 | *relP->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); | |
2612 | relP->address = fixP->fx_frag->fr_address + fixP->fx_where; | |
2613 | ||
2614 | if (fixP->fx_pcrel) | |
47926f60 | 2615 | /* FIXME: Is this correct? */ |
3bcbcc3d HPN |
2616 | relP->addend = fixP->fx_addnumber; |
2617 | else | |
47926f60 | 2618 | /* At least *this one* is correct. */ |
3bcbcc3d HPN |
2619 | relP->addend = fixP->fx_offset; |
2620 | ||
2621 | /* This is the standard place for KLUDGEs to work around bugs in | |
2622 | bfd_install_relocation (first such note in the documentation | |
2623 | appears with binutils-2.8). | |
2624 | ||
2625 | That function bfd_install_relocation does the wrong thing with | |
2626 | putting stuff into the addend of a reloc (it should stay out) for a | |
2627 | weak symbol. The really bad thing is that it adds the | |
2628 | "segment-relative offset" of the symbol into the reloc. In this | |
2629 | case, the reloc should instead be relative to the symbol with no | |
2630 | other offset than the assembly code shows; and since the symbol is | |
2631 | weak, any local definition should be ignored until link time (or | |
2632 | thereafter). | |
2633 | To wit: weaksym+42 should be weaksym+42 in the reloc, | |
2634 | not weaksym+(offset_from_segment_of_local_weaksym_definition) | |
2635 | ||
2636 | To "work around" this, we subtract the segment-relative offset of | |
2637 | "known" weak symbols. This evens out the extra offset. | |
2638 | ||
2639 | That happens for a.out but not for ELF, since for ELF, | |
2640 | bfd_install_relocation uses the "special function" field of the | |
2641 | howto, and does not execute the code that needs to be undone. */ | |
2642 | ||
2643 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour | |
2644 | && fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy) | |
2645 | && ! bfd_is_und_section (S_GET_SEGMENT (fixP->fx_addsy))) | |
47926f60 KH |
2646 | { |
2647 | relP->addend -= S_GET_VALUE (fixP->fx_addsy); | |
2648 | } | |
3bcbcc3d HPN |
2649 | |
2650 | relP->howto = bfd_reloc_type_lookup (stdoutput, code); | |
2651 | if (! relP->howto) | |
2652 | { | |
2653 | const char *name; | |
2654 | ||
2655 | name = S_GET_NAME (fixP->fx_addsy); | |
2656 | if (name == NULL) | |
2657 | name = _("<unknown>"); | |
2658 | as_fatal (_("Cannot generate relocation type for symbol %s, code %s"), | |
2659 | name, bfd_get_reloc_code_name (code)); | |
2660 | } | |
2661 | ||
2662 | return relP; | |
2663 | } | |
2664 | ||
3bcbcc3d | 2665 | /* Machine-dependent usage-output. */ |
47926f60 | 2666 | |
3bcbcc3d HPN |
2667 | void |
2668 | md_show_usage (stream) | |
2669 | FILE *stream; | |
2670 | { | |
7b15d668 HPN |
2671 | fprintf (stream, _("CRIS-specific options:\n")); |
2672 | fprintf (stream, "%s", | |
2673 | _(" -h, -H Don't execute, print this help text. Deprecated.\n")); | |
2674 | fprintf (stream, "%s", | |
2675 | _(" -N Warn when branches are expanded to jumps.\n")); | |
2676 | fprintf (stream, "%s", | |
2677 | _(" --underscore User symbols are normally prepended with underscore.\n")); | |
2678 | fprintf (stream, "%s", | |
2679 | _(" Registers will not need any prefix.\n")); | |
2680 | fprintf (stream, "%s", | |
2681 | _(" --no-underscore User symbols do not have any prefix.\n")); | |
2682 | fprintf (stream, "%s", | |
2683 | _(" Registers will require a `$'-prefix.\n")); | |
3bcbcc3d HPN |
2684 | } |
2685 | ||
3bcbcc3d | 2686 | /* Apply a fixS (fixup of an instruction or data that we didn't have |
47926f60 | 2687 | enough info to complete immediately) to the data in a frag. */ |
3bcbcc3d HPN |
2688 | |
2689 | int | |
2690 | md_apply_fix (fixP, valP) | |
2691 | fixS *fixP; | |
2692 | valueT *valP; | |
2693 | { | |
2694 | long val = *valP; | |
2695 | ||
2696 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
2697 | ||
2698 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
2699 | fixP->fx_done = 1; | |
2700 | ||
2701 | if (fixP->fx_bit_fixP || fixP->fx_im_disp != 0) | |
2702 | { | |
2703 | as_bad_where (fixP->fx_file, fixP->fx_line, _("Invalid relocation")); | |
2704 | fixP->fx_done = 1; | |
2705 | } | |
2706 | else | |
47926f60 KH |
2707 | { |
2708 | /* I took this from tc-arc.c, since we used to not support | |
2709 | fx_subsy != NULL. I'm not totally sure it's TRT. */ | |
2710 | if (fixP->fx_subsy != (symbolS *) NULL) | |
2711 | { | |
2712 | if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section) | |
2713 | val -= S_GET_VALUE (fixP->fx_subsy); | |
2714 | else | |
2715 | { | |
2716 | /* We can't actually support subtracting a symbol. */ | |
2717 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2718 | _("expression too complex")); | |
2719 | } | |
2720 | } | |
2721 | ||
2722 | cris_number_to_imm (buf, val, fixP->fx_size, fixP); | |
2723 | } | |
3bcbcc3d HPN |
2724 | |
2725 | return 1; | |
2726 | } | |
2727 | ||
3bcbcc3d HPN |
2728 | /* All relocations are relative to the location just after the fixup; |
2729 | the address of the fixup plus its size. */ | |
2730 | ||
2731 | long | |
2732 | md_pcrel_from (fixP) | |
2733 | fixS *fixP; | |
2734 | { | |
2735 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
2736 | ||
2737 | /* FIXME: We get here only at the end of assembly, when X in ".-X" is | |
2738 | still unknown. Since we don't have pc-relative relocations, this | |
2739 | is invalid. What to do if anything for a.out, is to add | |
2740 | pc-relative relocations everywhere including the elinux program | |
2741 | loader. */ | |
2742 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2743 | _("Invalid pc-relative relocation")); | |
2744 | return fixP->fx_size + addr; | |
2745 | } | |
2746 | ||
47926f60 | 2747 | /* We have no need to give defaults for symbol-values. */ |
3bcbcc3d HPN |
2748 | symbolS * |
2749 | md_undefined_symbol (name) | |
2750 | char *name ATTRIBUTE_UNUSED; | |
2751 | { | |
2752 | return 0; | |
2753 | } | |
2754 | ||
3bcbcc3d HPN |
2755 | /* Definition of TC_FORCE_RELOCATION. |
2756 | FIXME: Unsure of this. Can we omit it? Just copied from tc-i386.c | |
2757 | when doing multi-object format with ELF, since it's the only other | |
2758 | multi-object-format target with a.out and ELF. */ | |
2759 | int | |
2760 | md_cris_force_relocation (fixp) | |
2761 | struct fix *fixp; | |
2762 | { | |
2763 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
2764 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
2765 | return 1; | |
2766 | return 0; | |
2767 | } | |
2768 | ||
2769 | /* Check and emit error if broken-word handling has failed to fix up a | |
2770 | case-table. This is called from write.c, after doing everything it | |
2771 | knows about how to handle broken words. */ | |
2772 | ||
2773 | void | |
2774 | tc_cris_check_adjusted_broken_word (new_offset, brokwP) | |
2775 | offsetT new_offset; | |
2776 | struct broken_word *brokwP; | |
2777 | { | |
2778 | if (new_offset > 32767 || new_offset < -32768) | |
47926f60 | 2779 | /* We really want a genuine error, not a warning, so make it one. */ |
3bcbcc3d HPN |
2780 | as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line, |
2781 | _("Adjusted signed .word (%ld) overflows: `switch'-statement too large."), | |
2782 | (long) new_offset); | |
2783 | } | |
2784 | ||
7b15d668 HPN |
2785 | /* Make a leading REGISTER_PREFIX_CHAR mandatory for all registers. */ |
2786 | ||
2787 | static void cris_force_reg_prefix () | |
2788 | { | |
2789 | demand_register_prefix = true; | |
2790 | } | |
2791 | ||
2792 | /* Do not demand a leading REGISTER_PREFIX_CHAR for all registers. */ | |
2793 | ||
2794 | static void cris_relax_reg_prefix () | |
2795 | { | |
2796 | demand_register_prefix = false; | |
2797 | } | |
2798 | ||
2799 | /* Adjust for having a leading '_' on all user symbols. */ | |
2800 | ||
2801 | static void cris_sym_leading_underscore () | |
2802 | { | |
2803 | /* We can't really do anything more than assert that what the program | |
2804 | thinks symbol starts with agrees with the command-line options, since | |
2805 | the bfd is already created. */ | |
2806 | ||
2807 | if (symbols_have_leading_underscore == false) | |
2808 | as_bad (".syntax %s requires command-line option `--underscore'", | |
2809 | SYNTAX_USER_SYM_LEADING_UNDERSCORE); | |
2810 | } | |
2811 | ||
2812 | /* Adjust for not having any particular prefix on user symbols. */ | |
2813 | ||
2814 | static void cris_sym_no_leading_underscore () | |
2815 | { | |
2816 | if (symbols_have_leading_underscore == true) | |
2817 | as_bad (".syntax %s requires command-line option `--no-underscore'", | |
2818 | SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE); | |
2819 | } | |
2820 | ||
2821 | /* Handle the .syntax pseudo, which takes an argument that decides what | |
2822 | syntax the assembly code has. */ | |
2823 | ||
2824 | static void | |
2825 | s_syntax (ignore) | |
2826 | int ignore ATTRIBUTE_UNUSED; | |
2827 | { | |
2828 | static const struct syntaxes | |
2829 | { | |
2830 | const char *operand; | |
2831 | void (*fn) PARAMS ((void)); | |
2832 | } syntax_table[] = | |
2833 | {{SYNTAX_ENFORCE_REG_PREFIX, cris_force_reg_prefix}, | |
2834 | {SYNTAX_RELAX_REG_PREFIX, cris_relax_reg_prefix}, | |
2835 | {SYNTAX_USER_SYM_LEADING_UNDERSCORE, cris_sym_leading_underscore}, | |
2836 | {SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE, cris_sym_no_leading_underscore}}; | |
2837 | ||
2838 | const struct syntaxes *sp; | |
2839 | ||
2840 | for (sp = syntax_table; | |
2841 | sp < syntax_table + sizeof (syntax_table) / sizeof (syntax_table[0]); | |
2842 | sp++) | |
2843 | { | |
2844 | if (strncmp (input_line_pointer, sp->operand, | |
2845 | strlen (sp->operand)) == 0) | |
2846 | { | |
2847 | (sp->fn)(); | |
2848 | ||
2849 | input_line_pointer += strlen (sp->operand); | |
2850 | demand_empty_rest_of_line (); | |
2851 | return; | |
2852 | } | |
2853 | } | |
2854 | ||
2855 | as_bad (_("Unknown .syntax operand")); | |
2856 | } | |
2857 | ||
3bcbcc3d HPN |
2858 | /* |
2859 | * Local variables: | |
2860 | * eval: (c-set-style "gnu") | |
2861 | * indent-tabs-mode: t | |
2862 | * End: | |
2863 | */ |