Commit | Line | Data |
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3bcbcc3d | 1 | /* tc-cris.c -- Assembler code for the CRIS CPU core. |
ae6063d4 | 2 | Copyright 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
3bcbcc3d HPN |
3 | |
4 | Contributed by Axis Communications AB, Lund, Sweden. | |
5 | Originally written for GAS 1.38.1 by Mikael Asker. | |
08caf3f8 | 6 | Updates, BFDizing, GNUifying and ELF support by Hans-Peter Nilsson. |
3bcbcc3d HPN |
7 | |
8 | This file is part of GAS, the GNU Assembler. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the | |
22 | Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
47926f60 | 23 | MA 02111-1307, USA. */ |
3bcbcc3d HPN |
24 | |
25 | #include <stdio.h> | |
3bcbcc3d | 26 | #include "as.h" |
3882b010 | 27 | #include "safe-ctype.h" |
3bcbcc3d HPN |
28 | #include "subsegs.h" |
29 | #include "opcode/cris.h" | |
fcdc20a4 | 30 | #include "dwarf2dbg.h" |
3bcbcc3d HPN |
31 | |
32 | /* Conventions used here: | |
33 | Generally speaking, pointers to binutils types such as "fragS" and | |
34 | "expressionS" get parameter and variable names ending in "P", such as | |
35 | "fragP", to harmonize with the rest of the binutils code. Other | |
36 | pointers get a "p" suffix, such as "bufp". Any function or type-name | |
37 | that could clash with a current or future binutils or GAS function get | |
38 | a "cris_" prefix. */ | |
39 | ||
7b15d668 HPN |
40 | #define SYNTAX_RELAX_REG_PREFIX "no_register_prefix" |
41 | #define SYNTAX_ENFORCE_REG_PREFIX "register_prefix" | |
42 | #define SYNTAX_USER_SYM_LEADING_UNDERSCORE "leading_underscore" | |
43 | #define SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE "no_leading_underscore" | |
44 | #define REGISTER_PREFIX_CHAR '$' | |
45 | ||
1c971160 HPN |
46 | /* True for expressions where getting X_add_symbol and X_add_number is |
47 | enough to get the "base" and "offset"; no need to make_expr_symbol. | |
48 | It's not enough to check if X_op_symbol is NULL; that misses unary | |
49 | operations like O_uminus. */ | |
50 | #define SIMPLE_EXPR(EXP) \ | |
51 | ((EXP)->X_op == O_constant || (EXP)->X_op == O_symbol) | |
52 | ||
08caf3f8 HPN |
53 | /* Like in ":GOT", ":GOTOFF" etc. Other ports use '@', but that's in |
54 | line_separator_chars for CRIS, so we avoid it. */ | |
55 | #define PIC_SUFFIX_CHAR ':' | |
56 | ||
3bcbcc3d HPN |
57 | /* This might be CRIS_INSN_NONE if we're assembling a prefix-insn only. |
58 | Note that some prefix-insns might be assembled as CRIS_INSN_NORMAL. */ | |
59 | enum cris_insn_kind | |
60 | { | |
61 | CRIS_INSN_NORMAL, CRIS_INSN_NONE, CRIS_INSN_BRANCH | |
62 | }; | |
63 | ||
64 | /* An instruction will have one of these prefixes. | |
65 | Although the same bit-pattern, we handle BDAP with an immediate | |
66 | expression (eventually quick or [pc+]) different from when we only have | |
67 | register expressions. */ | |
68 | enum prefix_kind | |
69 | { | |
70 | PREFIX_NONE, PREFIX_BDAP_IMM, PREFIX_BDAP, PREFIX_BIAP, PREFIX_DIP, | |
71 | PREFIX_PUSH | |
72 | }; | |
73 | ||
74 | /* The prefix for an instruction. */ | |
75 | struct cris_prefix | |
76 | { | |
47926f60 KH |
77 | enum prefix_kind kind; |
78 | int base_reg_number; | |
79 | unsigned int opcode; | |
3bcbcc3d HPN |
80 | |
81 | /* There might be an expression to be evaluated, like I in [rN+I]. */ | |
47926f60 | 82 | expressionS expr; |
3bcbcc3d HPN |
83 | |
84 | /* If there's an expression, we might need a relocation. Here's the | |
85 | type of what relocation to start relaxaton with. | |
86 | The relocation is assumed to start immediately after the prefix insn, | |
87 | so we don't provide an offset. */ | |
88 | enum bfd_reloc_code_real reloc; | |
89 | }; | |
90 | ||
47926f60 | 91 | /* The description of the instruction being assembled. */ |
3bcbcc3d HPN |
92 | struct cris_instruction |
93 | { | |
94 | /* If CRIS_INSN_NONE, then this insn is of zero length. */ | |
47926f60 | 95 | enum cris_insn_kind insn_type; |
3bcbcc3d HPN |
96 | |
97 | /* If a special register was mentioned, this is its description, else | |
47926f60 | 98 | it is NULL. */ |
3bcbcc3d HPN |
99 | const struct cris_spec_reg *spec_reg; |
100 | ||
47926f60 | 101 | unsigned int opcode; |
3bcbcc3d HPN |
102 | |
103 | /* An insn may have at most one expression; theoretically there could be | |
47926f60 KH |
104 | another in its prefix (but I don't see how that could happen). */ |
105 | expressionS expr; | |
3bcbcc3d HPN |
106 | |
107 | /* The expression might need a relocation. Here's one to start | |
108 | relaxation with. */ | |
47926f60 | 109 | enum bfd_reloc_code_real reloc; |
3bcbcc3d | 110 | |
08caf3f8 | 111 | /* The size in bytes of an immediate expression, or zero if |
3bcbcc3d | 112 | nonapplicable. */ |
47926f60 | 113 | int imm_oprnd_size; |
3bcbcc3d HPN |
114 | }; |
115 | ||
116 | static void cris_process_instruction PARAMS ((char *, | |
117 | struct cris_instruction *, | |
118 | struct cris_prefix *)); | |
119 | static int get_bwd_size_modifier PARAMS ((char **, int *)); | |
120 | static int get_bw_size_modifier PARAMS ((char **, int *)); | |
121 | static int get_gen_reg PARAMS ((char **, int *)); | |
122 | static int get_spec_reg PARAMS ((char **, | |
123 | const struct cris_spec_reg **)); | |
124 | static int get_autoinc_prefix_or_indir_op PARAMS ((char **, | |
125 | struct cris_prefix *, | |
126 | int *, int *, int *, | |
127 | expressionS *)); | |
128 | static int get_3op_or_dip_prefix_op PARAMS ((char **, | |
129 | struct cris_prefix *)); | |
130 | static int cris_get_expression PARAMS ((char **, expressionS *)); | |
131 | static int get_flags PARAMS ((char **, int *)); | |
132 | static void gen_bdap PARAMS ((int, expressionS *)); | |
133 | static int branch_disp PARAMS ((int)); | |
134 | static void gen_cond_branch_32 PARAMS ((char *, char *, fragS *, | |
135 | symbolS *, symbolS *, long int)); | |
08caf3f8 | 136 | static void cris_number_to_imm PARAMS ((char *, long, int, fixS *, segT)); |
3bcbcc3d HPN |
137 | static void cris_create_short_jump PARAMS ((char *, addressT, addressT, |
138 | fragS *, symbolS *)); | |
7b15d668 | 139 | static void s_syntax PARAMS ((int)); |
fcdc20a4 HPN |
140 | static void s_cris_file PARAMS ((int)); |
141 | static void s_cris_loc PARAMS ((int)); | |
7b15d668 | 142 | |
08caf3f8 HPN |
143 | /* Get ":GOT", ":GOTOFF", ":PLT" etc. suffixes. */ |
144 | static void cris_get_pic_suffix PARAMS ((char **, | |
145 | bfd_reloc_code_real_type *, | |
146 | expressionS *)); | |
147 | static unsigned int cris_get_pic_reloc_size | |
148 | PARAMS ((bfd_reloc_code_real_type)); | |
149 | ||
7b15d668 HPN |
150 | /* All the .syntax functions. */ |
151 | static void cris_force_reg_prefix PARAMS ((void)); | |
152 | static void cris_relax_reg_prefix PARAMS ((void)); | |
153 | static void cris_sym_leading_underscore PARAMS ((void)); | |
154 | static void cris_sym_no_leading_underscore PARAMS ((void)); | |
ed67db7a | 155 | static char *cris_insn_first_word_frag PARAMS ((void)); |
7b15d668 | 156 | |
3bcbcc3d HPN |
157 | /* Handle to the opcode hash table. */ |
158 | static struct hash_control *op_hash = NULL; | |
159 | ||
399f703e HPN |
160 | /* If we target cris-axis-linux-gnu (as opposed to generic cris-axis-elf), |
161 | we default to no underscore and required register-prefixes. The | |
162 | difference is in the default values. */ | |
163 | #ifdef TE_LINUX | |
164 | #define DEFAULT_CRIS_AXIS_LINUX_GNU TRUE | |
165 | #else | |
166 | #define DEFAULT_CRIS_AXIS_LINUX_GNU FALSE | |
167 | #endif | |
168 | ||
7b15d668 | 169 | /* Whether we demand that registers have a `$' prefix. Default here. */ |
399f703e | 170 | static bfd_boolean demand_register_prefix = DEFAULT_CRIS_AXIS_LINUX_GNU; |
7b15d668 HPN |
171 | |
172 | /* Whether global user symbols have a leading underscore. Default here. */ | |
399f703e HPN |
173 | static bfd_boolean symbols_have_leading_underscore |
174 | = !DEFAULT_CRIS_AXIS_LINUX_GNU; | |
7b15d668 | 175 | |
08caf3f8 | 176 | /* Whether or not we allow PIC, and expand to PIC-friendly constructs. */ |
b34976b6 | 177 | static bfd_boolean pic = FALSE; |
08caf3f8 | 178 | |
3bcbcc3d HPN |
179 | const pseudo_typeS md_pseudo_table[] = |
180 | { | |
181 | {"dword", cons, 4}, | |
7b15d668 | 182 | {"syntax", s_syntax, 0}, |
fcdc20a4 HPN |
183 | {"file", s_cris_file, 0}, |
184 | {"loc", s_cris_loc, 0}, | |
3bcbcc3d HPN |
185 | {NULL, 0, 0} |
186 | }; | |
187 | ||
188 | static int warn_for_branch_expansion = 0; | |
189 | ||
190 | const char cris_comment_chars[] = ";"; | |
191 | ||
192 | /* This array holds the chars that only start a comment at the beginning of | |
193 | a line. If the line seems to have the form '# 123 filename' | |
47926f60 | 194 | .line and .file directives will appear in the pre-processed output. */ |
3bcbcc3d HPN |
195 | /* Note that input_file.c hand-checks for '#' at the beginning of the |
196 | first line of the input file. This is because the compiler outputs | |
47926f60 KH |
197 | #NO_APP at the beginning of its output. */ |
198 | /* Also note that slash-star will always start a comment. */ | |
3bcbcc3d HPN |
199 | const char line_comment_chars[] = "#"; |
200 | const char line_separator_chars[] = "@"; | |
201 | ||
202 | /* Now all floating point support is shut off. See md_atof. */ | |
203 | const char EXP_CHARS[] = ""; | |
204 | const char FLT_CHARS[] = ""; | |
205 | ||
3bcbcc3d HPN |
206 | /* For CRIS, we encode the relax_substateTs (in e.g. fr_substate) as: |
207 | 2 1 0 | |
208 | ---/ /--+-----------------+-----------------+-----------------+ | |
209 | | what state ? | how long ? | | |
210 | ---/ /--+-----------------+-----------------+-----------------+ | |
211 | ||
212 | The "how long" bits are 00 = byte, 01 = word, 10 = dword (long). | |
213 | This is a Un*x convention. | |
214 | Not all lengths are legit for a given value of (what state). | |
215 | ||
216 | Groups for CRIS address relaxing: | |
217 | ||
218 | 1. Bcc | |
219 | length: byte, word, 10-byte expansion | |
220 | ||
221 | 2. BDAP | |
47926f60 | 222 | length: byte, word, dword */ |
3bcbcc3d HPN |
223 | |
224 | #define STATE_CONDITIONAL_BRANCH (1) | |
225 | #define STATE_BASE_PLUS_DISP_PREFIX (2) | |
226 | ||
227 | #define STATE_LENGTH_MASK (3) | |
228 | #define STATE_BYTE (0) | |
229 | #define STATE_WORD (1) | |
230 | #define STATE_DWORD (2) | |
231 | /* Symbol undefined. */ | |
232 | #define STATE_UNDF (3) | |
233 | #define STATE_MAX_LENGTH (3) | |
234 | ||
2d2255b5 | 235 | /* These displacements are relative to the address following the opcode |
3bcbcc3d HPN |
236 | word of the instruction. The first letter is Byte, Word. The 2nd |
237 | letter is Forward, Backward. */ | |
238 | ||
239 | #define BRANCH_BF ( 254) | |
240 | #define BRANCH_BB (-256) | |
47926f60 KH |
241 | #define BRANCH_WF (2 + 32767) |
242 | #define BRANCH_WB (2 + -32768) | |
3bcbcc3d HPN |
243 | |
244 | #define BDAP_BF ( 127) | |
245 | #define BDAP_BB (-128) | |
246 | #define BDAP_WF ( 32767) | |
247 | #define BDAP_WB (-32768) | |
248 | ||
249 | #define ENCODE_RELAX(what, length) (((what) << 2) + (length)) | |
250 | ||
251 | const relax_typeS md_cris_relax_table[] = | |
252 | { | |
253 | /* Error sentinel (0, 0). */ | |
254 | {1, 1, 0, 0}, | |
255 | ||
256 | /* Unused (0, 1). */ | |
257 | {1, 1, 0, 0}, | |
258 | ||
259 | /* Unused (0, 2). */ | |
260 | {1, 1, 0, 0}, | |
261 | ||
262 | /* Unused (0, 3). */ | |
263 | {1, 1, 0, 0}, | |
264 | ||
265 | /* Bcc o (1, 0). */ | |
266 | {BRANCH_BF, BRANCH_BB, 0, ENCODE_RELAX (1, 1)}, | |
267 | ||
47926f60 | 268 | /* Bcc [PC+] (1, 1). */ |
3bcbcc3d HPN |
269 | {BRANCH_WF, BRANCH_WB, 2, ENCODE_RELAX (1, 2)}, |
270 | ||
271 | /* BEXT/BWF, BA, JUMP (external), JUMP (always), Bnot_cc, JUMP (default) | |
272 | (1, 2). */ | |
273 | {0, 0, 10, 0}, | |
274 | ||
275 | /* Unused (1, 3). */ | |
276 | {1, 1, 0, 0}, | |
277 | ||
278 | /* BDAP o (2, 0). */ | |
279 | {BDAP_BF, BDAP_BB, 0, ENCODE_RELAX (2, 1)}, | |
280 | ||
281 | /* BDAP.[bw] [PC+] (2, 1). */ | |
282 | {BDAP_WF, BDAP_WB, 2, ENCODE_RELAX (2, 2)}, | |
283 | ||
284 | /* BDAP.d [PC+] (2, 2). */ | |
285 | {0, 0, 4, 0} | |
286 | }; | |
287 | ||
288 | #undef BRANCH_BF | |
289 | #undef BRANCH_BB | |
290 | #undef BRANCH_WF | |
291 | #undef BRANCH_WB | |
292 | #undef BDAP_BF | |
293 | #undef BDAP_BB | |
294 | #undef BDAP_WF | |
295 | #undef BDAP_WB | |
296 | ||
3bcbcc3d HPN |
297 | /* Target-specific multicharacter options, not const-declared at usage |
298 | in 2.9.1 and CVS of 2000-02-16. */ | |
299 | struct option md_longopts[] = | |
300 | { | |
7b15d668 HPN |
301 | #define OPTION_NO_US (OPTION_MD_BASE + 0) |
302 | {"no-underscore", no_argument, NULL, OPTION_NO_US}, | |
303 | #define OPTION_US (OPTION_MD_BASE + 1) | |
304 | {"underscore", no_argument, NULL, OPTION_US}, | |
08caf3f8 HPN |
305 | #define OPTION_PIC (OPTION_MD_BASE + 2) |
306 | {"pic", no_argument, NULL, OPTION_PIC}, | |
3bcbcc3d HPN |
307 | {NULL, no_argument, NULL, 0} |
308 | }; | |
309 | ||
310 | /* Not const-declared at usage in 2.9.1. */ | |
311 | size_t md_longopts_size = sizeof (md_longopts); | |
312 | const char *md_shortopts = "hHN"; | |
313 | ||
3bcbcc3d HPN |
314 | /* At first glance, this may seems wrong and should be 4 (ba + nop); but |
315 | since a short_jump must skip a *number* of long jumps, it must also be | |
316 | a long jump. Here, we hope to make it a "ba [16bit_offs]" and a "nop" | |
317 | for the delay slot and hope that the jump table at most needs | |
318 | 32767/4=8191 long-jumps. A branch is better than a jump, since it is | |
319 | relative; we will not have a reloc to fix up somewhere. | |
320 | ||
321 | Note that we can't add relocs, because relaxation uses these fixed | |
322 | numbers, and md_create_short_jump is called after relaxation. */ | |
323 | ||
324 | const int md_short_jump_size = 6; | |
325 | const int md_long_jump_size = 6; | |
326 | ||
7b15d668 | 327 | /* Report output format. Small changes in output format (like elf |
08caf3f8 HPN |
328 | variants below) can happen until all options are parsed, but after |
329 | that, the output format must remain fixed. */ | |
47926f60 | 330 | |
3bcbcc3d HPN |
331 | const char * |
332 | cris_target_format () | |
333 | { | |
334 | switch (OUTPUT_FLAVOR) | |
335 | { | |
336 | case bfd_target_aout_flavour: | |
337 | return "a.out-cris"; | |
338 | ||
339 | case bfd_target_elf_flavour: | |
7b15d668 HPN |
340 | if (symbols_have_leading_underscore) |
341 | return "elf32-us-cris"; | |
3bcbcc3d HPN |
342 | return "elf32-cris"; |
343 | ||
344 | default: | |
345 | abort (); | |
346 | return NULL; | |
347 | } | |
348 | } | |
349 | ||
1c971160 HPN |
350 | /* We need a port-specific relaxation function to cope with sym2 - sym1 |
351 | relative expressions with both symbols in the same segment (but not | |
352 | necessarily in the same frag as this insn), for example: | |
353 | move.d [pc+sym2-(sym1-2)],r10 | |
354 | sym1: | |
355 | The offset can be 8, 16 or 32 bits long. */ | |
356 | ||
357 | long | |
358 | cris_relax_frag (seg, fragP, stretch) | |
359 | segT seg ATTRIBUTE_UNUSED; | |
360 | fragS *fragP; | |
361 | long stretch ATTRIBUTE_UNUSED; | |
362 | { | |
363 | long growth; | |
364 | offsetT aim = 0; | |
365 | symbolS *symbolP; | |
366 | const relax_typeS *this_type; | |
367 | const relax_typeS *start_type; | |
368 | relax_substateT next_state; | |
369 | relax_substateT this_state; | |
370 | const relax_typeS *table = TC_GENERIC_RELAX_TABLE; | |
371 | ||
372 | /* We only have to cope with frags as prepared by | |
fb2fd3e1 | 373 | md_estimate_size_before_relax. The dword cases may get here |
1c971160 HPN |
374 | because of the different reasons that they aren't relaxable. */ |
375 | switch (fragP->fr_subtype) | |
376 | { | |
377 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_DWORD): | |
378 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): | |
379 | /* When we get to these states, the frag won't grow any more. */ | |
380 | return 0; | |
381 | ||
382 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): | |
383 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): | |
384 | if (fragP->fr_symbol == NULL | |
385 | || S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) | |
386 | as_fatal (_("internal inconsistency problem in %s: fr_symbol %lx"), | |
387 | __FUNCTION__, (long) fragP->fr_symbol); | |
388 | symbolP = fragP->fr_symbol; | |
389 | if (symbol_resolved_p (symbolP)) | |
390 | as_fatal (_("internal inconsistency problem in %s: resolved symbol"), | |
391 | __FUNCTION__); | |
392 | aim = S_GET_VALUE (symbolP); | |
393 | break; | |
394 | ||
395 | default: | |
396 | as_fatal (_("internal inconsistency problem in %s: fr_subtype %d"), | |
397 | __FUNCTION__, fragP->fr_subtype); | |
398 | } | |
399 | ||
400 | /* The rest is stolen from relax_frag. There's no obvious way to | |
401 | share the code, but fortunately no requirement to keep in sync as | |
402 | long as fragP->fr_symbol does not have its segment changed. */ | |
403 | ||
404 | this_state = fragP->fr_subtype; | |
405 | start_type = this_type = table + this_state; | |
406 | ||
407 | if (aim < 0) | |
408 | { | |
409 | /* Look backwards. */ | |
410 | for (next_state = this_type->rlx_more; next_state;) | |
411 | if (aim >= this_type->rlx_backward) | |
412 | next_state = 0; | |
413 | else | |
414 | { | |
415 | /* Grow to next state. */ | |
416 | this_state = next_state; | |
417 | this_type = table + this_state; | |
418 | next_state = this_type->rlx_more; | |
419 | } | |
420 | } | |
421 | else | |
422 | { | |
423 | /* Look forwards. */ | |
424 | for (next_state = this_type->rlx_more; next_state;) | |
425 | if (aim <= this_type->rlx_forward) | |
426 | next_state = 0; | |
427 | else | |
428 | { | |
429 | /* Grow to next state. */ | |
430 | this_state = next_state; | |
431 | this_type = table + this_state; | |
432 | next_state = this_type->rlx_more; | |
433 | } | |
434 | } | |
435 | ||
436 | growth = this_type->rlx_length - start_type->rlx_length; | |
437 | if (growth != 0) | |
438 | fragP->fr_subtype = this_state; | |
439 | return growth; | |
440 | } | |
441 | ||
3bcbcc3d HPN |
442 | /* Prepare machine-dependent frags for relaxation. |
443 | ||
444 | Called just before relaxation starts. Any symbol that is now undefined | |
445 | will not become defined. | |
446 | ||
447 | Return the correct fr_subtype in the frag. | |
448 | ||
449 | Return the initial "guess for fr_var" to caller. The guess for fr_var | |
450 | is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix | |
451 | or fr_var contributes to our returned value. | |
452 | ||
453 | Although it may not be explicit in the frag, pretend | |
47926f60 | 454 | fr_var starts with a value. */ |
3bcbcc3d HPN |
455 | |
456 | int | |
457 | md_estimate_size_before_relax (fragP, segment_type) | |
458 | fragS *fragP; | |
459 | /* The segment is either N_DATA or N_TEXT. */ | |
47926f60 | 460 | segT segment_type; |
3bcbcc3d | 461 | { |
47926f60 | 462 | int old_fr_fix; |
3bcbcc3d HPN |
463 | |
464 | old_fr_fix = fragP->fr_fix; | |
465 | ||
466 | switch (fragP->fr_subtype) | |
467 | { | |
468 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_UNDF): | |
469 | if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type) | |
c335d394 HPN |
470 | /* The symbol lies in the same segment - a relaxable case. */ |
471 | fragP->fr_subtype | |
472 | = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE); | |
3bcbcc3d | 473 | else |
c335d394 HPN |
474 | /* Unknown or not the same segment, so not relaxable. */ |
475 | fragP->fr_subtype | |
476 | = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_DWORD); | |
477 | fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; | |
3bcbcc3d HPN |
478 | break; |
479 | ||
480 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF): | |
481 | /* Note that we can not do anything sane with relaxing | |
482 | [rX + a_known_symbol_in_text], it will have to be a 32-bit | |
483 | value. | |
484 | ||
485 | We could play tricks with managing a constant pool and make | |
08caf3f8 HPN |
486 | a_known_symbol_in_text a "bdap [pc + offset]" pointing there |
487 | (like the GOT for ELF shared libraries), but that's no use, it | |
488 | would in general be no shorter or faster code, only more | |
489 | complicated. */ | |
3bcbcc3d HPN |
490 | |
491 | if (S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) | |
492 | { | |
493 | /* Go for dword if not absolute or same segment. */ | |
494 | fragP->fr_subtype | |
495 | = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD); | |
c335d394 | 496 | fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; |
3bcbcc3d | 497 | } |
1c971160 HPN |
498 | else if (!symbol_resolved_p (fragP->fr_symbol)) |
499 | { | |
500 | /* The symbol will eventually be completely resolved as an | |
501 | absolute expression, but right now it depends on the result | |
502 | of relaxation and we don't know anything else about the | |
503 | value. We start relaxation with the assumption that it'll | |
504 | fit in a byte. */ | |
505 | fragP->fr_subtype | |
506 | = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE); | |
507 | fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; | |
508 | } | |
3bcbcc3d HPN |
509 | else |
510 | { | |
511 | /* Absolute expression. */ | |
512 | long int value; | |
513 | value = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
514 | ||
515 | if (value >= -128 && value <= 127) | |
516 | { | |
517 | /* Byte displacement. */ | |
518 | (fragP->fr_opcode)[0] = value; | |
519 | } | |
520 | else | |
521 | { | |
522 | /* Word or dword displacement. */ | |
523 | int pow2_of_size = 1; | |
524 | char *writep; | |
525 | ||
526 | if (value < -32768 || value > 32767) | |
527 | { | |
528 | /* Outside word range, make it a dword. */ | |
529 | pow2_of_size = 2; | |
530 | } | |
531 | ||
532 | /* Modify the byte-offset BDAP into a word or dword offset | |
533 | BDAP. Or really, a BDAP rX,8bit into a | |
07e90ad5 | 534 | BDAP.[wd] rX,[PC+] followed by a word or dword. */ |
3bcbcc3d HPN |
535 | (fragP->fr_opcode)[0] = BDAP_PC_LOW + pow2_of_size * 16; |
536 | ||
537 | /* Keep the register number in the highest four bits. */ | |
538 | (fragP->fr_opcode)[1] &= 0xF0; | |
539 | (fragP->fr_opcode)[1] |= BDAP_INCR_HIGH; | |
540 | ||
47926f60 | 541 | /* It grew by two or four bytes. */ |
3bcbcc3d HPN |
542 | fragP->fr_fix += 1 << pow2_of_size; |
543 | writep = fragP->fr_literal + old_fr_fix; | |
544 | md_number_to_chars (writep, value, 1 << pow2_of_size); | |
545 | } | |
546 | frag_wane (fragP); | |
547 | } | |
548 | break; | |
549 | ||
c335d394 HPN |
550 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE): |
551 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD): | |
552 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_DWORD): | |
553 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): | |
554 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): | |
93c2a809 AM |
555 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): |
556 | /* When relaxing a section for the second time, we don't need to | |
c335d394 HPN |
557 | do anything except making sure that fr_var is set right. */ |
558 | fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; | |
93c2a809 AM |
559 | break; |
560 | ||
3bcbcc3d HPN |
561 | default: |
562 | BAD_CASE (fragP->fr_subtype); | |
563 | } | |
564 | ||
565 | return fragP->fr_var + (fragP->fr_fix - old_fr_fix); | |
566 | } | |
567 | ||
3bcbcc3d HPN |
568 | /* Perform post-processing of machine-dependent frags after relaxation. |
569 | Called after relaxation is finished. | |
570 | In: Address of frag. | |
571 | fr_type == rs_machine_dependent. | |
572 | fr_subtype is what the address relaxed to. | |
573 | ||
574 | Out: Any fixS:s and constants are set up. | |
575 | ||
576 | The caller will turn the frag into a ".space 0". */ | |
577 | ||
578 | void | |
579 | md_convert_frag (abfd, sec, fragP) | |
580 | bfd *abfd ATTRIBUTE_UNUSED; | |
581 | segT sec ATTRIBUTE_UNUSED; | |
582 | fragS *fragP; | |
583 | { | |
47926f60 | 584 | /* Pointer to first byte in variable-sized part of the frag. */ |
3bcbcc3d HPN |
585 | char *var_partp; |
586 | ||
587 | /* Pointer to first opcode byte in frag. */ | |
588 | char *opcodep; | |
589 | ||
590 | /* Used to check integrity of the relaxation. | |
591 | One of 2 = long, 1 = word, or 0 = byte. */ | |
592 | int length_code; | |
593 | ||
594 | /* Size in bytes of variable-sized part of frag. */ | |
595 | int var_part_size = 0; | |
596 | ||
597 | /* This is part of *fragP. It contains all information about addresses | |
598 | and offsets to varying parts. */ | |
599 | symbolS *symbolP; | |
600 | unsigned long var_part_offset; | |
601 | ||
602 | /* Where, in file space, is _var of *fragP? */ | |
603 | unsigned long address_of_var_part = 0; | |
604 | ||
605 | /* Where, in file space, does addr point? */ | |
606 | unsigned long target_address; | |
607 | ||
608 | know (fragP->fr_type == rs_machine_dependent); | |
609 | ||
610 | length_code = fragP->fr_subtype & STATE_LENGTH_MASK; | |
611 | know (length_code >= 0 && length_code < STATE_MAX_LENGTH); | |
612 | ||
613 | var_part_offset = fragP->fr_fix; | |
614 | var_partp = fragP->fr_literal + var_part_offset; | |
615 | opcodep = fragP->fr_opcode; | |
616 | ||
617 | symbolP = fragP->fr_symbol; | |
ac62c346 | 618 | target_address = (symbolP ? S_GET_VALUE (symbolP) : 0) + fragP->fr_offset; |
3bcbcc3d HPN |
619 | address_of_var_part = fragP->fr_address + var_part_offset; |
620 | ||
621 | switch (fragP->fr_subtype) | |
47926f60 KH |
622 | { |
623 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE): | |
624 | opcodep[0] = branch_disp ((target_address - address_of_var_part)); | |
625 | var_part_size = 0; | |
626 | break; | |
3bcbcc3d | 627 | |
47926f60 KH |
628 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD): |
629 | /* We had a quick immediate branch, now turn it into a word one i.e. a | |
630 | PC autoincrement. */ | |
631 | opcodep[0] = BRANCH_PC_LOW; | |
632 | opcodep[1] &= 0xF0; | |
633 | opcodep[1] |= BRANCH_INCR_HIGH; | |
634 | md_number_to_chars (var_partp, | |
635 | (long) (target_address - (address_of_var_part + 2)), | |
636 | 2); | |
637 | var_part_size = 2; | |
638 | break; | |
639 | ||
640 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_DWORD): | |
641 | gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP, | |
642 | fragP->fr_symbol, (symbolS *) NULL, | |
643 | fragP->fr_offset); | |
644 | /* Ten bytes added: a branch, nop and a jump. */ | |
645 | var_part_size = 2 + 2 + 4 + 2; | |
646 | break; | |
3bcbcc3d | 647 | |
47926f60 | 648 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): |
1c971160 HPN |
649 | if (symbolP == NULL) |
650 | as_fatal (_("internal inconsistency in %s: bdapq no symbol"), | |
651 | __FUNCTION__); | |
652 | opcodep[0] = S_GET_VALUE (symbolP); | |
47926f60 KH |
653 | var_part_size = 0; |
654 | break; | |
655 | ||
656 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): | |
657 | /* We had a BDAP 8-bit "quick immediate", now turn it into a 16-bit | |
658 | one that uses PC autoincrement. */ | |
659 | opcodep[0] = BDAP_PC_LOW + (1 << 4); | |
660 | opcodep[1] &= 0xF0; | |
661 | opcodep[1] |= BDAP_INCR_HIGH; | |
1c971160 HPN |
662 | if (symbolP == NULL) |
663 | as_fatal (_("internal inconsistency in %s: bdap.w with no symbol"), | |
664 | __FUNCTION__); | |
665 | md_number_to_chars (var_partp, S_GET_VALUE (symbolP), 2); | |
47926f60 KH |
666 | var_part_size = 2; |
667 | break; | |
668 | ||
669 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): | |
670 | /* We had a BDAP 16-bit "word", change the offset to a dword. */ | |
671 | opcodep[0] = BDAP_PC_LOW + (2 << 4); | |
672 | opcodep[1] &= 0xF0; | |
673 | opcodep[1] |= BDAP_INCR_HIGH; | |
674 | if (fragP->fr_symbol == NULL) | |
675 | md_number_to_chars (var_partp, fragP->fr_offset, 4); | |
676 | else | |
677 | fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol, | |
678 | fragP->fr_offset, 0, BFD_RELOC_32); | |
679 | var_part_size = 4; | |
680 | break; | |
681 | ||
682 | default: | |
683 | BAD_CASE (fragP->fr_subtype); | |
684 | break; | |
685 | } | |
686 | ||
687 | fragP->fr_fix += var_part_size; | |
3bcbcc3d HPN |
688 | } |
689 | ||
690 | /* Generate a short jump around a secondary jump table. | |
691 | Used by md_create_long_jump. | |
692 | ||
693 | This used to be md_create_short_jump, but is now called from | |
694 | md_create_long_jump instead, when sufficient. | |
695 | since the sizes of the jumps are the same. It used to be brittle, | |
47926f60 | 696 | making possibilities for creating bad code. */ |
3bcbcc3d HPN |
697 | |
698 | static void | |
699 | cris_create_short_jump (storep, from_addr, to_addr, fragP, to_symbol) | |
700 | char *storep; | |
701 | addressT from_addr; | |
702 | addressT to_addr; | |
703 | fragS *fragP ATTRIBUTE_UNUSED; | |
704 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
705 | { | |
706 | long int distance; | |
707 | ||
708 | distance = to_addr - from_addr; | |
709 | ||
710 | if (-254 <= distance && distance <= 256) | |
711 | { | |
712 | /* Create a "short" short jump: "BA distance - 2". */ | |
47926f60 | 713 | storep[0] = branch_disp (distance - 2); |
3bcbcc3d HPN |
714 | storep[1] = BA_QUICK_HIGH; |
715 | ||
716 | /* A nop for the delay slot. */ | |
47926f60 | 717 | md_number_to_chars (storep + 2, NOP_OPCODE, 2); |
3bcbcc3d HPN |
718 | |
719 | /* The extra word should be filled with something sane too. Make it | |
720 | a nop to keep disassembly sane. */ | |
47926f60 | 721 | md_number_to_chars (storep + 4, NOP_OPCODE, 2); |
3bcbcc3d HPN |
722 | } |
723 | else | |
724 | { | |
725 | /* Make it a "long" short jump: "BA (PC+)". */ | |
726 | md_number_to_chars (storep, BA_PC_INCR_OPCODE, 2); | |
727 | ||
47926f60 | 728 | /* ".WORD distance - 4". */ |
3bcbcc3d HPN |
729 | md_number_to_chars (storep + 2, (long) (distance - 4), 2); |
730 | ||
731 | /* A nop for the delay slot. */ | |
47926f60 | 732 | md_number_to_chars (storep + 4, NOP_OPCODE, 2); |
3bcbcc3d HPN |
733 | } |
734 | } | |
735 | ||
3bcbcc3d HPN |
736 | /* Generate a long jump in a secondary jump table. |
737 | ||
738 | storep Where to store the jump instruction. | |
739 | from_addr Address of the jump instruction. | |
740 | to_addr Destination address of the jump. | |
741 | fragP Which frag the destination address operand | |
742 | lies in. | |
743 | to_symbol Destination symbol. */ | |
744 | ||
745 | void | |
746 | md_create_long_jump (storep, from_addr, to_addr, fragP, to_symbol) | |
747 | char *storep; | |
748 | addressT from_addr; | |
749 | addressT to_addr; | |
750 | fragS *fragP; | |
751 | symbolS *to_symbol; | |
752 | { | |
753 | long int distance; | |
754 | ||
755 | distance = to_addr - from_addr; | |
756 | ||
757 | if (-32763 <= distance && distance <= 32772) | |
758 | { | |
759 | /* Then make it a "short" long jump. */ | |
760 | cris_create_short_jump (storep, from_addr, to_addr, fragP, | |
761 | to_symbol); | |
762 | } | |
763 | else | |
764 | { | |
08caf3f8 HPN |
765 | /* We have a "long" long jump: "JUMP [PC+]". |
766 | Make it an "ADD [PC+],PC" if we're supposed to emit PIC code. */ | |
767 | md_number_to_chars (storep, | |
768 | pic ? ADD_PC_INCR_OPCODE : JUMP_PC_INCR_OPCODE, 2); | |
3bcbcc3d | 769 | |
08caf3f8 | 770 | /* Follow with a ".DWORD to_addr", PC-relative for PIC. */ |
3bcbcc3d | 771 | fix_new (fragP, storep + 2 - fragP->fr_literal, 4, to_symbol, |
08caf3f8 | 772 | 0, pic ? 1 : 0, pic ? BFD_RELOC_32_PCREL : BFD_RELOC_32); |
3bcbcc3d HPN |
773 | } |
774 | } | |
775 | ||
ed67db7a HPN |
776 | /* Allocate space for the first piece of an insn, and mark it as the |
777 | start of the insn for debug-format use. */ | |
778 | ||
779 | static char * | |
780 | cris_insn_first_word_frag () | |
781 | { | |
782 | char *insnp = frag_more (2); | |
783 | ||
784 | /* We need to mark the start of the insn by passing dwarf2_emit_insn | |
785 | the offset from the current fragment position. This must be done | |
786 | after the first fragment is created but before any other fragments | |
787 | (fixed or varying) are created. Note that the offset only | |
788 | corresponds to the "size" of the insn for a fixed-size, | |
789 | non-expanded insn. */ | |
790 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
791 | dwarf2_emit_insn (2); | |
792 | ||
793 | return insnp; | |
794 | } | |
795 | ||
3bcbcc3d | 796 | /* Port-specific assembler initialization. */ |
47926f60 | 797 | |
3bcbcc3d HPN |
798 | void |
799 | md_begin () | |
800 | { | |
801 | const char *hashret = NULL; | |
802 | int i = 0; | |
803 | ||
47926f60 | 804 | /* Set up a hash table for the instructions. */ |
3bcbcc3d HPN |
805 | op_hash = hash_new (); |
806 | if (op_hash == NULL) | |
807 | as_fatal (_("Virtual memory exhausted")); | |
808 | ||
809 | while (cris_opcodes[i].name != NULL) | |
810 | { | |
811 | const char *name = cris_opcodes[i].name; | |
812 | hashret = hash_insert (op_hash, name, (PTR) &cris_opcodes[i]); | |
813 | ||
814 | if (hashret != NULL && *hashret != '\0') | |
815 | as_fatal (_("Can't hash `%s': %s\n"), cris_opcodes[i].name, | |
47926f60 | 816 | *hashret == 0 ? _("(unknown reason)") : hashret); |
3bcbcc3d HPN |
817 | do |
818 | { | |
819 | if (cris_opcodes[i].match & cris_opcodes[i].lose) | |
820 | as_fatal (_("Buggy opcode: `%s' \"%s\"\n"), cris_opcodes[i].name, | |
821 | cris_opcodes[i].args); | |
822 | ||
823 | ++i; | |
47926f60 KH |
824 | } |
825 | while (cris_opcodes[i].name != NULL | |
826 | && strcmp (cris_opcodes[i].name, name) == 0); | |
3bcbcc3d HPN |
827 | } |
828 | } | |
829 | ||
3bcbcc3d | 830 | /* Assemble a source line. */ |
47926f60 | 831 | |
3bcbcc3d HPN |
832 | void |
833 | md_assemble (str) | |
834 | char *str; | |
835 | { | |
836 | struct cris_instruction output_instruction; | |
837 | struct cris_prefix prefix; | |
838 | char *opcodep; | |
839 | char *p; | |
840 | ||
841 | know (str); | |
842 | ||
843 | /* Do the low-level grunt - assemble to bits and split up into a prefix | |
844 | and ordinary insn. */ | |
845 | cris_process_instruction (str, &output_instruction, &prefix); | |
846 | ||
847 | /* Handle any prefixes to the instruction. */ | |
848 | switch (prefix.kind) | |
849 | { | |
850 | case PREFIX_NONE: | |
851 | break; | |
852 | ||
853 | /* When the expression is unknown for a BDAP, it can need 0, 2 or 4 | |
854 | extra bytes, so we handle it separately. */ | |
855 | case PREFIX_BDAP_IMM: | |
08caf3f8 HPN |
856 | /* We only do it if the relocation is unspecified, i.e. not a PIC |
857 | relocation. */ | |
858 | if (prefix.reloc == BFD_RELOC_NONE) | |
859 | { | |
860 | gen_bdap (prefix.base_reg_number, &prefix.expr); | |
861 | break; | |
862 | } | |
863 | /* Fall through. */ | |
3bcbcc3d HPN |
864 | case PREFIX_BDAP: |
865 | case PREFIX_BIAP: | |
866 | case PREFIX_DIP: | |
ed67db7a | 867 | opcodep = cris_insn_first_word_frag (); |
3bcbcc3d HPN |
868 | |
869 | /* Output the prefix opcode. */ | |
870 | md_number_to_chars (opcodep, (long) prefix.opcode, 2); | |
871 | ||
08caf3f8 HPN |
872 | /* Having a specified reloc only happens for DIP and for BDAP with |
873 | PIC operands, but it is ok to drop through here for the other | |
874 | prefixes as they can have no relocs specified. */ | |
3bcbcc3d HPN |
875 | if (prefix.reloc != BFD_RELOC_NONE) |
876 | { | |
08caf3f8 HPN |
877 | unsigned int relocsize |
878 | = (prefix.kind == PREFIX_DIP | |
879 | ? 4 : cris_get_pic_reloc_size (prefix.reloc)); | |
880 | ||
08caf3f8 HPN |
881 | p = frag_more (relocsize); |
882 | fix_new_exp (frag_now, (p - frag_now->fr_literal), relocsize, | |
3bcbcc3d HPN |
883 | &prefix.expr, 0, prefix.reloc); |
884 | } | |
885 | break; | |
886 | ||
887 | case PREFIX_PUSH: | |
ed67db7a | 888 | opcodep = cris_insn_first_word_frag (); |
3bcbcc3d HPN |
889 | |
890 | /* Output the prefix opcode. Being a "push", we add the negative | |
891 | size of the register to "sp". */ | |
892 | if (output_instruction.spec_reg != NULL) | |
893 | { | |
47926f60 | 894 | /* Special register. */ |
3bcbcc3d HPN |
895 | opcodep[0] = -output_instruction.spec_reg->reg_size; |
896 | } | |
897 | else | |
898 | { | |
47926f60 | 899 | /* General register. */ |
3bcbcc3d HPN |
900 | opcodep[0] = -4; |
901 | } | |
902 | opcodep[1] = (REG_SP << 4) + (BDAP_QUICK_OPCODE >> 8); | |
903 | break; | |
904 | ||
905 | default: | |
906 | BAD_CASE (prefix.kind); | |
907 | } | |
908 | ||
909 | /* If we only had a prefix insn, we're done. */ | |
910 | if (output_instruction.insn_type == CRIS_INSN_NONE) | |
911 | return; | |
912 | ||
913 | /* Done with the prefix. Continue with the main instruction. */ | |
ed67db7a HPN |
914 | if (prefix.kind == PREFIX_NONE) |
915 | opcodep = cris_insn_first_word_frag (); | |
916 | else | |
917 | opcodep = frag_more (2); | |
3bcbcc3d HPN |
918 | |
919 | /* Output the instruction opcode. */ | |
47926f60 | 920 | md_number_to_chars (opcodep, (long) (output_instruction.opcode), 2); |
3bcbcc3d HPN |
921 | |
922 | /* Output the symbol-dependent instruction stuff. */ | |
923 | if (output_instruction.insn_type == CRIS_INSN_BRANCH) | |
924 | { | |
925 | segT to_seg = absolute_section; | |
926 | int is_undefined = 0; | |
927 | int length_code; | |
928 | ||
929 | if (output_instruction.expr.X_op != O_constant) | |
930 | { | |
931 | to_seg = S_GET_SEGMENT (output_instruction.expr.X_add_symbol); | |
932 | ||
933 | if (to_seg == undefined_section) | |
934 | is_undefined = 1; | |
935 | } | |
936 | ||
fb2fd3e1 | 937 | if (to_seg == now_seg || is_undefined) |
3bcbcc3d | 938 | { |
08caf3f8 HPN |
939 | /* Handle complex expressions. */ |
940 | valueT addvalue | |
1c971160 HPN |
941 | = (SIMPLE_EXPR (&output_instruction.expr) |
942 | ? output_instruction.expr.X_add_number | |
943 | : 0); | |
08caf3f8 | 944 | symbolS *sym |
1c971160 HPN |
945 | = (SIMPLE_EXPR (&output_instruction.expr) |
946 | ? output_instruction.expr.X_add_symbol | |
947 | : make_expr_symbol (&output_instruction.expr)); | |
08caf3f8 | 948 | |
3bcbcc3d | 949 | /* If is_undefined, then the expression may BECOME now_seg. */ |
47926f60 | 950 | length_code = is_undefined ? STATE_UNDF : STATE_BYTE; |
3bcbcc3d HPN |
951 | |
952 | /* Make room for max ten bytes of variable length. */ | |
953 | frag_var (rs_machine_dependent, 10, 0, | |
954 | ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, length_code), | |
08caf3f8 | 955 | sym, addvalue, opcodep); |
3bcbcc3d HPN |
956 | } |
957 | else | |
958 | { | |
959 | /* We have: to_seg != now_seg && to_seg != undefined_section. | |
960 | This means it is a branch to a known symbol in another | |
fb2fd3e1 | 961 | section, perhaps an absolute address. Emit a 32-bit branch. */ |
08caf3f8 HPN |
962 | char *cond_jump = frag_more (10); |
963 | ||
08caf3f8 | 964 | gen_cond_branch_32 (opcodep, cond_jump, frag_now, |
3bcbcc3d | 965 | output_instruction.expr.X_add_symbol, |
47926f60 | 966 | (symbolS *) NULL, |
3bcbcc3d HPN |
967 | output_instruction.expr.X_add_number); |
968 | } | |
969 | } | |
970 | else | |
971 | { | |
972 | if (output_instruction.imm_oprnd_size > 0) | |
973 | { | |
2d2255b5 | 974 | /* The instruction has an immediate operand. */ |
08caf3f8 | 975 | enum bfd_reloc_code_real reloc = BFD_RELOC_NONE; |
3bcbcc3d HPN |
976 | |
977 | switch (output_instruction.imm_oprnd_size) | |
978 | { | |
979 | /* Any byte-size immediate constants are treated as | |
980 | word-size. FIXME: Thus overflow check does not work | |
981 | correctly. */ | |
982 | ||
983 | case 2: | |
08caf3f8 HPN |
984 | /* Note that size-check for the explicit reloc has already |
985 | been done when we get here. */ | |
986 | if (output_instruction.reloc != BFD_RELOC_NONE) | |
987 | reloc = output_instruction.reloc; | |
988 | else | |
989 | reloc = BFD_RELOC_16; | |
3bcbcc3d HPN |
990 | break; |
991 | ||
992 | case 4: | |
08caf3f8 HPN |
993 | /* Allow a relocation specified in the operand. */ |
994 | if (output_instruction.reloc != BFD_RELOC_NONE) | |
995 | reloc = output_instruction.reloc; | |
996 | else | |
997 | reloc = BFD_RELOC_32; | |
3bcbcc3d HPN |
998 | break; |
999 | ||
1000 | default: | |
1001 | BAD_CASE (output_instruction.imm_oprnd_size); | |
1002 | } | |
1003 | ||
1004 | p = frag_more (output_instruction.imm_oprnd_size); | |
1005 | fix_new_exp (frag_now, (p - frag_now->fr_literal), | |
1006 | output_instruction.imm_oprnd_size, | |
1007 | &output_instruction.expr, 0, reloc); | |
1008 | } | |
1009 | else if (output_instruction.reloc != BFD_RELOC_NONE) | |
1010 | { | |
1011 | /* An immediate operand that has a relocation and needs to be | |
47926f60 | 1012 | processed further. */ |
3bcbcc3d HPN |
1013 | |
1014 | /* It is important to use fix_new_exp here and everywhere else | |
1015 | (and not fix_new), as fix_new_exp can handle "difference | |
1016 | expressions" - where the expression contains a difference of | |
1017 | two symbols in the same segment. */ | |
1018 | fix_new_exp (frag_now, (opcodep - frag_now->fr_literal), 2, | |
1019 | &output_instruction.expr, 0, | |
1020 | output_instruction.reloc); | |
1021 | } | |
1022 | } | |
1023 | } | |
1024 | ||
3bcbcc3d | 1025 | /* Low level text-to-bits assembly. */ |
47926f60 | 1026 | |
3bcbcc3d HPN |
1027 | static void |
1028 | cris_process_instruction (insn_text, out_insnp, prefixp) | |
1029 | char *insn_text; | |
47926f60 | 1030 | struct cris_instruction *out_insnp; |
3bcbcc3d HPN |
1031 | struct cris_prefix *prefixp; |
1032 | { | |
47926f60 KH |
1033 | char *s; |
1034 | char modified_char = 0; | |
1035 | const char *args; | |
3bcbcc3d | 1036 | struct cris_opcode *instruction; |
47926f60 KH |
1037 | char *operands; |
1038 | int match = 0; | |
1039 | int mode; | |
1040 | int regno; | |
1041 | int size_bits; | |
3bcbcc3d HPN |
1042 | |
1043 | /* Reset these fields to a harmless state in case we need to return in | |
1044 | error. */ | |
1045 | prefixp->kind = PREFIX_NONE; | |
1046 | prefixp->reloc = BFD_RELOC_NONE; | |
1047 | out_insnp->insn_type = CRIS_INSN_NORMAL; | |
1048 | out_insnp->imm_oprnd_size = 0; | |
1049 | ||
1050 | /* Find the end of the opcode mnemonic. We assume (true in 2.9.1) | |
1051 | that the caller has translated the opcode to lower-case, up to the | |
47926f60 | 1052 | first non-letter. */ |
3882b010 | 1053 | for (operands = insn_text; ISLOWER (*operands); ++operands) |
3bcbcc3d HPN |
1054 | ; |
1055 | ||
1056 | /* Terminate the opcode after letters, but save the character there if | |
1057 | it was of significance. */ | |
1058 | switch (*operands) | |
1059 | { | |
1060 | case '\0': | |
1061 | break; | |
1062 | ||
1063 | case '.': | |
47926f60 | 1064 | /* Put back the modified character later. */ |
3bcbcc3d | 1065 | modified_char = *operands; |
47926f60 | 1066 | /* Fall through. */ |
3bcbcc3d HPN |
1067 | |
1068 | case ' ': | |
47926f60 KH |
1069 | /* Consume the character after the mnemonic |
1070 | and replace it with '\0'. */ | |
3bcbcc3d HPN |
1071 | *operands++ = '\0'; |
1072 | break; | |
1073 | ||
1074 | default: | |
1075 | as_bad (_("Unknown opcode: `%s'"), insn_text); | |
1076 | return; | |
1077 | } | |
1078 | ||
1079 | /* Find the instruction. */ | |
1080 | instruction = (struct cris_opcode *) hash_find (op_hash, insn_text); | |
1081 | if (instruction == NULL) | |
1082 | { | |
1083 | as_bad (_("Unknown opcode: `%s'"), insn_text); | |
1084 | return; | |
1085 | } | |
1086 | ||
1087 | /* Put back the modified character. */ | |
1088 | switch (modified_char) | |
1089 | { | |
1090 | case 0: | |
1091 | break; | |
1092 | ||
1093 | default: | |
1094 | *--operands = modified_char; | |
1095 | } | |
1096 | ||
3bcbcc3d | 1097 | /* Try to match an opcode table slot. */ |
47926f60 | 1098 | for (s = operands;;) |
3bcbcc3d | 1099 | { |
47926f60 | 1100 | int imm_expr_found; |
3bcbcc3d HPN |
1101 | |
1102 | /* Initialize *prefixp, perhaps after being modified for a | |
47926f60 | 1103 | "near match". */ |
3bcbcc3d HPN |
1104 | prefixp->kind = PREFIX_NONE; |
1105 | prefixp->reloc = BFD_RELOC_NONE; | |
1106 | ||
1107 | /* Initialize *out_insnp. */ | |
1108 | memset (out_insnp, 0, sizeof (*out_insnp)); | |
1109 | out_insnp->opcode = instruction->match; | |
1110 | out_insnp->reloc = BFD_RELOC_NONE; | |
1111 | out_insnp->insn_type = CRIS_INSN_NORMAL; | |
1112 | out_insnp->imm_oprnd_size = 0; | |
1113 | ||
1114 | imm_expr_found = 0; | |
1115 | ||
1116 | /* Build the opcode, checking as we go to make sure that the | |
1117 | operands match. */ | |
47926f60 | 1118 | for (args = instruction->args;; ++args) |
3bcbcc3d HPN |
1119 | { |
1120 | switch (*args) | |
1121 | { | |
1122 | case '\0': | |
1123 | /* If we've come to the end of arguments, we're done. */ | |
1124 | if (*s == '\0') | |
1125 | match = 1; | |
1126 | break; | |
1127 | ||
1128 | case '!': | |
1129 | /* Non-matcher character for disassembly. | |
1130 | Ignore it here. */ | |
1131 | continue; | |
1132 | ||
1133 | case ',': | |
1134 | case ' ': | |
1135 | /* These must match exactly. */ | |
1136 | if (*s++ == *args) | |
1137 | continue; | |
1138 | break; | |
1139 | ||
1140 | case 'B': | |
1141 | /* This is not really an operand, but causes a "BDAP | |
47926f60 | 1142 | -size,SP" prefix to be output, for PUSH instructions. */ |
3bcbcc3d HPN |
1143 | prefixp->kind = PREFIX_PUSH; |
1144 | continue; | |
1145 | ||
1146 | case 'b': | |
1147 | /* This letter marks an operand that should not be matched | |
1148 | in the assembler. It is a branch with 16-bit | |
1149 | displacement. The assembler will create them from the | |
1150 | 8-bit flavor when necessary. The assembler does not | |
1151 | support the [rN+] operand, as the [r15+] that is | |
1152 | generated for 16-bit displacements. */ | |
1153 | break; | |
1154 | ||
1155 | case 'c': | |
1156 | /* A 5-bit unsigned immediate in bits <4:0>. */ | |
1157 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1158 | break; | |
1159 | else | |
1160 | { | |
1161 | if (out_insnp->expr.X_op == O_constant | |
1162 | && (out_insnp->expr.X_add_number < 0 | |
1163 | || out_insnp->expr.X_add_number > 31)) | |
1164 | as_bad (_("Immediate value not in 5 bit unsigned range: %ld"), | |
1165 | out_insnp->expr.X_add_number); | |
1166 | ||
1167 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_5; | |
1168 | continue; | |
1169 | } | |
1170 | ||
1171 | case 'C': | |
1172 | /* A 4-bit unsigned immediate in bits <3:0>. */ | |
1173 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1174 | break; | |
1175 | else | |
1176 | { | |
1177 | if (out_insnp->expr.X_op == O_constant | |
1178 | && (out_insnp->expr.X_add_number < 0 | |
1179 | || out_insnp->expr.X_add_number > 15)) | |
1180 | as_bad (_("Immediate value not in 4 bit unsigned range: %ld"), | |
1181 | out_insnp->expr.X_add_number); | |
1182 | ||
1183 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_4; | |
1184 | continue; | |
1185 | } | |
1186 | ||
1187 | case 'D': | |
1188 | /* General register in bits <15:12> and <3:0>. */ | |
1189 | if (! get_gen_reg (&s, ®no)) | |
1190 | break; | |
1191 | else | |
1192 | { | |
1193 | out_insnp->opcode |= regno /* << 0 */; | |
1194 | out_insnp->opcode |= regno << 12; | |
1195 | continue; | |
1196 | } | |
1197 | ||
1198 | case 'f': | |
1199 | /* Flags from the condition code register. */ | |
1200 | { | |
1201 | int flags = 0; | |
1202 | ||
1203 | if (! get_flags (&s, &flags)) | |
1204 | break; | |
1205 | ||
47926f60 | 1206 | out_insnp->opcode |= ((flags & 0xf0) << 8) | (flags & 0xf); |
3bcbcc3d HPN |
1207 | continue; |
1208 | } | |
1209 | ||
1210 | case 'i': | |
1211 | /* A 6-bit signed immediate in bits <5:0>. */ | |
1212 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1213 | break; | |
1214 | else | |
1215 | { | |
1216 | if (out_insnp->expr.X_op == O_constant | |
1217 | && (out_insnp->expr.X_add_number < -32 | |
1218 | || out_insnp->expr.X_add_number > 31)) | |
1219 | as_bad (_("Immediate value not in 6 bit range: %ld"), | |
1220 | out_insnp->expr.X_add_number); | |
1221 | out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_6; | |
1222 | continue; | |
1223 | } | |
1224 | ||
1225 | case 'I': | |
1226 | /* A 6-bit unsigned immediate in bits <5:0>. */ | |
1227 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1228 | break; | |
1229 | else | |
1230 | { | |
1231 | if (out_insnp->expr.X_op == O_constant | |
1232 | && (out_insnp->expr.X_add_number < 0 | |
1233 | || out_insnp->expr.X_add_number > 63)) | |
1234 | as_bad (_("Immediate value not in 6 bit unsigned range: %ld"), | |
1235 | out_insnp->expr.X_add_number); | |
1236 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_6; | |
1237 | continue; | |
1238 | } | |
1239 | ||
1240 | case 'M': | |
1241 | /* A size modifier, B, W or D, to be put in a bit position | |
1242 | suitable for CLEAR instructions (i.e. reflecting a zero | |
1243 | register). */ | |
1244 | if (! get_bwd_size_modifier (&s, &size_bits)) | |
1245 | break; | |
1246 | else | |
1247 | { | |
1248 | switch (size_bits) | |
1249 | { | |
1250 | case 0: | |
1251 | out_insnp->opcode |= 0 << 12; | |
1252 | break; | |
1253 | ||
1254 | case 1: | |
1255 | out_insnp->opcode |= 4 << 12; | |
1256 | break; | |
1257 | ||
1258 | case 2: | |
1259 | out_insnp->opcode |= 8 << 12; | |
1260 | break; | |
1261 | } | |
1262 | continue; | |
1263 | } | |
1264 | ||
1265 | case 'm': | |
1266 | /* A size modifier, B, W or D, to be put in bits <5:4>. */ | |
1267 | if (! get_bwd_size_modifier (&s, &size_bits)) | |
1268 | break; | |
1269 | else | |
1270 | { | |
1271 | out_insnp->opcode |= size_bits << 4; | |
1272 | continue; | |
1273 | } | |
1274 | ||
1275 | case 'o': | |
1276 | /* A branch expression. */ | |
1277 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1278 | break; | |
1279 | else | |
1280 | { | |
1281 | out_insnp->insn_type = CRIS_INSN_BRANCH; | |
1282 | continue; | |
1283 | } | |
1284 | ||
1285 | case 'O': | |
1286 | /* A BDAP expression for any size, "expr,r". */ | |
1287 | if (! cris_get_expression (&s, &prefixp->expr)) | |
1288 | break; | |
1289 | else | |
1290 | { | |
1291 | if (*s != ',') | |
1292 | break; | |
1293 | ||
1294 | s++; | |
1295 | ||
1296 | if (!get_gen_reg (&s, &prefixp->base_reg_number)) | |
1297 | break; | |
1298 | ||
1299 | /* Since 'O' is used with an explicit bdap, we have no | |
47926f60 | 1300 | "real" instruction. */ |
3bcbcc3d | 1301 | prefixp->kind = PREFIX_BDAP_IMM; |
08caf3f8 HPN |
1302 | prefixp->opcode |
1303 | = BDAP_QUICK_OPCODE | (prefixp->base_reg_number << 12); | |
1304 | ||
3bcbcc3d HPN |
1305 | out_insnp->insn_type = CRIS_INSN_NONE; |
1306 | continue; | |
1307 | } | |
1308 | ||
1309 | case 'P': | |
1310 | /* Special register in bits <15:12>. */ | |
1311 | if (! get_spec_reg (&s, &out_insnp->spec_reg)) | |
1312 | break; | |
1313 | else | |
1314 | { | |
1315 | /* Use of some special register names come with a | |
1316 | specific warning. Note that we have no ".cpu type" | |
1317 | pseudo yet, so some of this is just unused | |
1318 | framework. */ | |
1319 | if (out_insnp->spec_reg->warning) | |
1320 | as_warn (out_insnp->spec_reg->warning); | |
1321 | else if (out_insnp->spec_reg->applicable_version | |
1322 | == cris_ver_warning) | |
1323 | /* Others have a generic warning. */ | |
1324 | as_warn (_("Unimplemented register `%s' specified"), | |
1325 | out_insnp->spec_reg->name); | |
1326 | ||
1327 | out_insnp->opcode | |
1328 | |= out_insnp->spec_reg->number << 12; | |
1329 | continue; | |
1330 | } | |
1331 | ||
1332 | case 'p': | |
1333 | /* This character is used in the disassembler to | |
1334 | recognize a prefix instruction to fold into the | |
1335 | addressing mode for the next instruction. It is | |
47926f60 | 1336 | ignored here. */ |
3bcbcc3d HPN |
1337 | continue; |
1338 | ||
1339 | case 'R': | |
1340 | /* General register in bits <15:12>. */ | |
1341 | if (! get_gen_reg (&s, ®no)) | |
1342 | break; | |
1343 | else | |
1344 | { | |
1345 | out_insnp->opcode |= regno << 12; | |
1346 | continue; | |
1347 | } | |
1348 | ||
1349 | case 'r': | |
1350 | /* General register in bits <3:0>. */ | |
1351 | if (! get_gen_reg (&s, ®no)) | |
1352 | break; | |
1353 | else | |
1354 | { | |
1355 | out_insnp->opcode |= regno /* << 0 */; | |
1356 | continue; | |
1357 | } | |
1358 | ||
1359 | case 'S': | |
1360 | /* Source operand in bit <10> and a prefix; a 3-operand | |
1361 | prefix. */ | |
1362 | if (! get_3op_or_dip_prefix_op (&s, prefixp)) | |
1363 | break; | |
1364 | else | |
1365 | continue; | |
1366 | ||
1367 | case 's': | |
1368 | /* Source operand in bits <10>, <3:0> and optionally a | |
1369 | prefix; i.e. an indirect operand or an side-effect | |
1370 | prefix. */ | |
1371 | if (! get_autoinc_prefix_or_indir_op (&s, prefixp, &mode, | |
1372 | ®no, | |
1373 | &imm_expr_found, | |
1374 | &out_insnp->expr)) | |
1375 | break; | |
1376 | else | |
1377 | { | |
1378 | if (prefixp->kind != PREFIX_NONE) | |
1379 | { | |
1380 | /* A prefix, so it has the autoincrement bit | |
1381 | set. */ | |
1382 | out_insnp->opcode |= (AUTOINCR_BIT << 8); | |
1383 | } | |
1384 | else | |
08caf3f8 HPN |
1385 | { |
1386 | /* No prefix. The "mode" variable contains bits like | |
1387 | whether or not this is autoincrement mode. */ | |
1388 | out_insnp->opcode |= (mode << 10); | |
1389 | ||
1390 | /* If there was a PIC reloc specifier, then it was | |
1391 | attached to the prefix. Note that we can't check | |
1392 | that the reloc size matches, since we don't have | |
1393 | all the operands yet in all cases. */ | |
1394 | if (prefixp->reloc != BFD_RELOC_NONE) | |
1395 | out_insnp->reloc = prefixp->reloc; | |
1396 | } | |
3bcbcc3d HPN |
1397 | |
1398 | out_insnp->opcode |= regno /* << 0 */ ; | |
1399 | continue; | |
1400 | } | |
1401 | ||
1402 | case 'x': | |
1403 | /* Rs.m in bits <15:12> and <5:4>. */ | |
1404 | if (! get_gen_reg (&s, ®no) | |
1405 | || ! get_bwd_size_modifier (&s, &size_bits)) | |
1406 | break; | |
1407 | else | |
1408 | { | |
47926f60 | 1409 | out_insnp->opcode |= (regno << 12) | (size_bits << 4); |
3bcbcc3d HPN |
1410 | continue; |
1411 | } | |
1412 | ||
1413 | case 'y': | |
1414 | /* Source operand in bits <10>, <3:0> and optionally a | |
1415 | prefix; i.e. an indirect operand or an side-effect | |
1416 | prefix. | |
1417 | ||
1418 | The difference to 's' is that this does not allow an | |
81d4177b | 1419 | "immediate" expression. */ |
3bcbcc3d HPN |
1420 | if (! get_autoinc_prefix_or_indir_op (&s, prefixp, |
1421 | &mode, ®no, | |
1422 | &imm_expr_found, | |
1423 | &out_insnp->expr) | |
1424 | || imm_expr_found) | |
1425 | break; | |
1426 | else | |
1427 | { | |
1428 | if (prefixp->kind != PREFIX_NONE) | |
1429 | { | |
1430 | /* A prefix, and those matched here always have | |
1431 | side-effects (see 's' case). */ | |
1432 | out_insnp->opcode |= (AUTOINCR_BIT << 8); | |
1433 | } | |
1434 | else | |
1435 | { | |
1436 | /* No prefix. The "mode" variable contains bits | |
1437 | like whether or not this is autoincrement | |
1438 | mode. */ | |
1439 | out_insnp->opcode |= (mode << 10); | |
1440 | } | |
1441 | ||
1442 | out_insnp->opcode |= regno /* << 0 */; | |
1443 | continue; | |
1444 | } | |
1445 | ||
1446 | case 'z': | |
1447 | /* Size modifier (B or W) in bit <4>. */ | |
1448 | if (! get_bw_size_modifier (&s, &size_bits)) | |
1449 | break; | |
1450 | else | |
1451 | { | |
1452 | out_insnp->opcode |= size_bits << 4; | |
1453 | continue; | |
1454 | } | |
1455 | ||
1456 | default: | |
1457 | BAD_CASE (*args); | |
1458 | } | |
1459 | ||
1460 | /* We get here when we fail a match above or we found a | |
1461 | complete match. Break out of this loop. */ | |
1462 | break; | |
1463 | } | |
1464 | ||
1465 | /* Was it a match or a miss? */ | |
1466 | if (match == 0) | |
1467 | { | |
1468 | /* If it's just that the args don't match, maybe the next | |
1469 | item in the table is the same opcode but with | |
1470 | matching operands. */ | |
1471 | if (instruction[1].name != NULL | |
1472 | && ! strcmp (instruction->name, instruction[1].name)) | |
1473 | { | |
1474 | /* Yep. Restart and try that one instead. */ | |
1475 | ++instruction; | |
1476 | s = operands; | |
1477 | continue; | |
1478 | } | |
1479 | else | |
1480 | { | |
1481 | /* We've come to the end of instructions with this | |
1482 | opcode, so it must be an error. */ | |
1483 | as_bad (_("Illegal operands")); | |
1484 | return; | |
1485 | } | |
1486 | } | |
1487 | else | |
1488 | { | |
1489 | /* We have a match. Check if there's anything more to do. */ | |
1490 | if (imm_expr_found) | |
1491 | { | |
1492 | /* There was an immediate mode operand, so we must check | |
1493 | that it has an appropriate size. */ | |
3bcbcc3d HPN |
1494 | switch (instruction->imm_oprnd_size) |
1495 | { | |
1496 | default: | |
1497 | case SIZE_NONE: | |
1498 | /* Shouldn't happen; this one does not have immediate | |
1499 | operands with different sizes. */ | |
1500 | BAD_CASE (instruction->imm_oprnd_size); | |
1501 | break; | |
1502 | ||
1503 | case SIZE_FIX_32: | |
1504 | out_insnp->imm_oprnd_size = 4; | |
1505 | break; | |
1506 | ||
1507 | case SIZE_SPEC_REG: | |
1508 | switch (out_insnp->spec_reg->reg_size) | |
1509 | { | |
1510 | case 1: | |
1511 | if (out_insnp->expr.X_op == O_constant | |
1512 | && (out_insnp->expr.X_add_number < -128 | |
1513 | || out_insnp->expr.X_add_number > 255)) | |
1514 | as_bad (_("Immediate value not in 8 bit range: %ld"), | |
1515 | out_insnp->expr.X_add_number); | |
47926f60 | 1516 | /* Fall through. */ |
3bcbcc3d HPN |
1517 | case 2: |
1518 | /* FIXME: We need an indicator in the instruction | |
1519 | table to pass on, to indicate if we need to check | |
1520 | overflow for a signed or unsigned number. */ | |
1521 | if (out_insnp->expr.X_op == O_constant | |
1522 | && (out_insnp->expr.X_add_number < -32768 | |
1523 | || out_insnp->expr.X_add_number > 65535)) | |
1524 | as_bad (_("Immediate value not in 16 bit range: %ld"), | |
1525 | out_insnp->expr.X_add_number); | |
1526 | out_insnp->imm_oprnd_size = 2; | |
1527 | break; | |
1528 | ||
1529 | case 4: | |
1530 | out_insnp->imm_oprnd_size = 4; | |
1531 | break; | |
1532 | ||
1533 | default: | |
1534 | BAD_CASE (out_insnp->spec_reg->reg_size); | |
1535 | } | |
1536 | break; | |
1537 | ||
1538 | case SIZE_FIELD: | |
1539 | switch (size_bits) | |
1540 | { | |
1541 | case 0: | |
1542 | if (out_insnp->expr.X_op == O_constant | |
1543 | && (out_insnp->expr.X_add_number < -128 | |
1544 | || out_insnp->expr.X_add_number > 255)) | |
1545 | as_bad (_("Immediate value not in 8 bit range: %ld"), | |
1546 | out_insnp->expr.X_add_number); | |
47926f60 | 1547 | /* Fall through. */ |
3bcbcc3d HPN |
1548 | case 1: |
1549 | if (out_insnp->expr.X_op == O_constant | |
1550 | && (out_insnp->expr.X_add_number < -32768 | |
1551 | || out_insnp->expr.X_add_number > 65535)) | |
1552 | as_bad (_("Immediate value not in 16 bit range: %ld"), | |
1553 | out_insnp->expr.X_add_number); | |
1554 | out_insnp->imm_oprnd_size = 2; | |
1555 | break; | |
1556 | ||
1557 | case 2: | |
1558 | out_insnp->imm_oprnd_size = 4; | |
1559 | break; | |
1560 | ||
1561 | default: | |
1562 | BAD_CASE (out_insnp->spec_reg->reg_size); | |
1563 | } | |
1564 | } | |
08caf3f8 HPN |
1565 | |
1566 | /* If there was a relocation specified for the immediate | |
1567 | expression (i.e. it had a PIC modifier) check that the | |
1568 | size of the PIC relocation matches the size specified by | |
1569 | the opcode. */ | |
1570 | if (out_insnp->reloc != BFD_RELOC_NONE | |
1571 | && (cris_get_pic_reloc_size (out_insnp->reloc) | |
1572 | != (unsigned int) out_insnp->imm_oprnd_size)) | |
1573 | as_bad (_("PIC relocation size does not match operand size")); | |
3bcbcc3d HPN |
1574 | } |
1575 | } | |
1576 | break; | |
1577 | } | |
1578 | } | |
1579 | ||
3bcbcc3d HPN |
1580 | /* Get a B, W, or D size modifier from the string pointed out by *cPP, |
1581 | which must point to a '.' in front of the modifier. On successful | |
1582 | return, *cPP is advanced to the character following the size | |
1583 | modifier, and is undefined otherwise. | |
1584 | ||
1585 | cPP Pointer to pointer to string starting | |
1586 | with the size modifier. | |
1587 | ||
1588 | size_bitsp Pointer to variable to contain the size bits on | |
1589 | successful return. | |
1590 | ||
1591 | Return 1 iff a correct size modifier is found, else 0. */ | |
1592 | ||
1593 | static int | |
1594 | get_bwd_size_modifier (cPP, size_bitsp) | |
1595 | char **cPP; | |
1596 | int *size_bitsp; | |
1597 | { | |
1598 | if (**cPP != '.') | |
1599 | return 0; | |
1600 | else | |
1601 | { | |
47926f60 | 1602 | /* Consume the '.'. */ |
3bcbcc3d HPN |
1603 | (*cPP)++; |
1604 | ||
1605 | switch (**cPP) | |
1606 | { | |
1607 | case 'B': | |
1608 | case 'b': | |
1609 | *size_bitsp = 0; | |
1610 | break; | |
1611 | ||
1612 | case 'W': | |
1613 | case 'w': | |
1614 | *size_bitsp = 1; | |
1615 | break; | |
1616 | ||
1617 | case 'D': | |
1618 | case 'd': | |
1619 | *size_bitsp = 2; | |
1620 | break; | |
1621 | ||
1622 | default: | |
1623 | return 0; | |
1624 | } | |
1625 | ||
1626 | /* Consume the size letter. */ | |
1627 | (*cPP)++; | |
1628 | return 1; | |
1629 | } | |
1630 | } | |
1631 | ||
3bcbcc3d HPN |
1632 | /* Get a B or W size modifier from the string pointed out by *cPP, |
1633 | which must point to a '.' in front of the modifier. On successful | |
1634 | return, *cPP is advanced to the character following the size | |
1635 | modifier, and is undefined otherwise. | |
1636 | ||
1637 | cPP Pointer to pointer to string starting | |
1638 | with the size modifier. | |
1639 | ||
1640 | size_bitsp Pointer to variable to contain the size bits on | |
1641 | successful return. | |
1642 | ||
1643 | Return 1 iff a correct size modifier is found, else 0. */ | |
1644 | ||
1645 | static int | |
1646 | get_bw_size_modifier (cPP, size_bitsp) | |
1647 | char **cPP; | |
1648 | int *size_bitsp; | |
1649 | { | |
1650 | if (**cPP != '.') | |
1651 | return 0; | |
1652 | else | |
1653 | { | |
47926f60 | 1654 | /* Consume the '.'. */ |
3bcbcc3d HPN |
1655 | (*cPP)++; |
1656 | ||
1657 | switch (**cPP) | |
1658 | { | |
1659 | case 'B': | |
1660 | case 'b': | |
1661 | *size_bitsp = 0; | |
1662 | break; | |
1663 | ||
1664 | case 'W': | |
1665 | case 'w': | |
1666 | *size_bitsp = 1; | |
1667 | break; | |
1668 | ||
1669 | default: | |
1670 | return 0; | |
1671 | } | |
1672 | ||
1673 | /* Consume the size letter. */ | |
1674 | (*cPP)++; | |
1675 | return 1; | |
1676 | } | |
1677 | } | |
1678 | ||
07e90ad5 | 1679 | /* Get a general register from the string pointed out by *cPP. The |
3bcbcc3d HPN |
1680 | variable *cPP is advanced to the character following the general |
1681 | register name on a successful return, and has its initial position | |
1682 | otherwise. | |
1683 | ||
1684 | cPP Pointer to pointer to string, beginning with a general | |
1685 | register name. | |
1686 | ||
1687 | regnop Pointer to int containing the register number. | |
1688 | ||
1689 | Return 1 iff a correct general register designator is found, | |
1690 | else 0. */ | |
1691 | ||
1692 | static int | |
1693 | get_gen_reg (cPP, regnop) | |
1694 | char **cPP; | |
1695 | int *regnop; | |
1696 | { | |
1697 | char *oldp; | |
1698 | oldp = *cPP; | |
1699 | ||
7b15d668 HPN |
1700 | /* Handle a sometimes-mandatory dollar sign as register prefix. */ |
1701 | if (**cPP == REGISTER_PREFIX_CHAR) | |
1702 | (*cPP)++; | |
1703 | else if (demand_register_prefix) | |
1704 | return 0; | |
1705 | ||
3bcbcc3d HPN |
1706 | switch (**cPP) |
1707 | { | |
1708 | case 'P': | |
1709 | case 'p': | |
1710 | /* "P" as in "PC"? Consume the "P". */ | |
1711 | (*cPP)++; | |
1712 | ||
1713 | if ((**cPP == 'C' || **cPP == 'c') | |
3882b010 | 1714 | && ! ISALNUM ((*cPP)[1])) |
3bcbcc3d HPN |
1715 | { |
1716 | /* It's "PC": consume the "c" and we're done. */ | |
1717 | (*cPP)++; | |
1718 | *regnop = REG_PC; | |
1719 | return 1; | |
1720 | } | |
1721 | break; | |
1722 | ||
1723 | case 'R': | |
1724 | case 'r': | |
47926f60 | 1725 | /* Hopefully r[0-9] or r1[0-5]. Consume 'R' or 'r'. */ |
3bcbcc3d HPN |
1726 | (*cPP)++; |
1727 | ||
3882b010 | 1728 | if (ISDIGIT (**cPP)) |
3bcbcc3d HPN |
1729 | { |
1730 | /* It's r[0-9]. Consume and check the next digit. */ | |
1731 | *regnop = **cPP - '0'; | |
1732 | (*cPP)++; | |
1733 | ||
3882b010 | 1734 | if (! ISALNUM (**cPP)) |
3bcbcc3d | 1735 | { |
47926f60 | 1736 | /* No more digits, we're done. */ |
3bcbcc3d HPN |
1737 | return 1; |
1738 | } | |
1739 | else | |
1740 | { | |
1741 | /* One more digit. Consume and add. */ | |
47926f60 | 1742 | *regnop = *regnop * 10 + (**cPP - '0'); |
3bcbcc3d HPN |
1743 | |
1744 | /* We need to check for a valid register number; Rn, | |
1745 | 0 <= n <= MAX_REG. */ | |
1746 | if (*regnop <= MAX_REG) | |
1747 | { | |
1748 | /* Consume second digit. */ | |
1749 | (*cPP)++; | |
1750 | return 1; | |
1751 | } | |
1752 | } | |
1753 | } | |
1754 | break; | |
1755 | ||
1756 | case 'S': | |
1757 | case 's': | |
1758 | /* "S" as in "SP"? Consume the "S". */ | |
1759 | (*cPP)++; | |
1760 | if (**cPP == 'P' || **cPP == 'p') | |
1761 | { | |
1762 | /* It's "SP": consume the "p" and we're done. */ | |
1763 | (*cPP)++; | |
1764 | *regnop = REG_SP; | |
1765 | return 1; | |
1766 | } | |
1767 | break; | |
1768 | ||
1769 | default: | |
1770 | /* Just here to silence compilation warnings. */ | |
1771 | ; | |
1772 | } | |
1773 | ||
1774 | /* We get here if we fail. Restore the pointer. */ | |
1775 | *cPP = oldp; | |
1776 | return 0; | |
1777 | } | |
1778 | ||
3bcbcc3d HPN |
1779 | /* Get a special register from the string pointed out by *cPP. The |
1780 | variable *cPP is advanced to the character following the special | |
1781 | register name if one is found, and retains its original position | |
1782 | otherwise. | |
1783 | ||
1784 | cPP Pointer to pointer to string starting with a special register | |
1785 | name. | |
1786 | ||
1787 | sregpp Pointer to Pointer to struct spec_reg, where a pointer to the | |
1788 | register description will be stored. | |
1789 | ||
1790 | Return 1 iff a correct special register name is found. */ | |
1791 | ||
1792 | static int | |
1793 | get_spec_reg (cPP, sregpp) | |
1794 | char **cPP; | |
1795 | const struct cris_spec_reg **sregpp; | |
1796 | { | |
1797 | char *s1; | |
1798 | const char *s2; | |
7b15d668 | 1799 | char *name_begin = *cPP; |
3bcbcc3d HPN |
1800 | |
1801 | const struct cris_spec_reg *sregp; | |
1802 | ||
7b15d668 HPN |
1803 | /* Handle a sometimes-mandatory dollar sign as register prefix. */ |
1804 | if (*name_begin == REGISTER_PREFIX_CHAR) | |
1805 | name_begin++; | |
1806 | else if (demand_register_prefix) | |
1807 | return 0; | |
1808 | ||
3bcbcc3d | 1809 | /* Loop over all special registers. */ |
47926f60 | 1810 | for (sregp = cris_spec_regs; sregp->name != NULL; sregp++) |
3bcbcc3d | 1811 | { |
3bcbcc3d | 1812 | /* Start over from beginning of the supposed name. */ |
7b15d668 | 1813 | s1 = name_begin; |
3bcbcc3d HPN |
1814 | s2 = sregp->name; |
1815 | ||
3882b010 | 1816 | while (*s2 != '\0' && TOLOWER (*s1) == *s2) |
3bcbcc3d HPN |
1817 | { |
1818 | s1++; | |
1819 | s2++; | |
1820 | } | |
1821 | ||
1822 | /* For a match, we must have consumed the name in the table, and we | |
1823 | must be outside what could be part of a name. Assume here that a | |
47926f60 | 1824 | test for alphanumerics is sufficient for a name test. */ |
3882b010 | 1825 | if (*s2 == 0 && ! ISALNUM (*s1)) |
3bcbcc3d | 1826 | { |
47926f60 | 1827 | /* We have a match. Update the pointer and be done. */ |
3bcbcc3d HPN |
1828 | *cPP = s1; |
1829 | *sregpp = sregp; | |
1830 | return 1; | |
1831 | } | |
1832 | } | |
1833 | ||
47926f60 | 1834 | /* If we got here, we did not find any name. */ |
3bcbcc3d HPN |
1835 | return 0; |
1836 | } | |
1837 | ||
3bcbcc3d HPN |
1838 | /* Get an unprefixed or side-effect-prefix operand from the string pointed |
1839 | out by *cPP. The pointer *cPP is advanced to the character following | |
1840 | the indirect operand if we have success, else it contains an undefined | |
1841 | value. | |
1842 | ||
1843 | cPP Pointer to pointer to string beginning with the first | |
1844 | character of the supposed operand. | |
1845 | ||
1846 | prefixp Pointer to structure containing an optional instruction | |
1847 | prefix. | |
1848 | ||
1849 | is_autoincp Pointer to int indicating the indirect or autoincrement | |
1850 | bits. | |
1851 | ||
1852 | src_regnop Pointer to int containing the source register number in | |
1853 | the instruction. | |
1854 | ||
1855 | imm_foundp Pointer to an int indicating if an immediate expression | |
1856 | is found. | |
1857 | ||
1858 | imm_exprP Pointer to a structure containing an immediate | |
1859 | expression, if success and if *imm_foundp is nonzero. | |
1860 | ||
1861 | Return 1 iff a correct indirect operand is found. */ | |
1862 | ||
1863 | static int | |
1864 | get_autoinc_prefix_or_indir_op (cPP, prefixp, is_autoincp, src_regnop, | |
1865 | imm_foundp, imm_exprP) | |
47926f60 KH |
1866 | char **cPP; |
1867 | struct cris_prefix *prefixp; | |
1868 | int *is_autoincp; | |
1869 | int *src_regnop; | |
1870 | int *imm_foundp; | |
1871 | expressionS *imm_exprP; | |
3bcbcc3d HPN |
1872 | { |
1873 | /* Assume there was no immediate mode expression. */ | |
1874 | *imm_foundp = 0; | |
1875 | ||
1876 | if (**cPP == '[') | |
1877 | { | |
1878 | /* So this operand is one of: | |
1879 | Indirect: [rN] | |
1880 | Autoincrement: [rN+] | |
1881 | Indexed with assign: [rN=rM+rO.S] | |
1882 | Offset with assign: [rN=rM+I], [rN=rM+[rO].s], [rN=rM+[rO+].s] | |
1883 | ||
1884 | Either way, consume the '['. */ | |
1885 | (*cPP)++; | |
1886 | ||
1887 | /* Get the rN register. */ | |
1888 | if (! get_gen_reg (cPP, src_regnop)) | |
1889 | /* If there was no register, then this cannot match. */ | |
1890 | return 0; | |
1891 | else | |
1892 | { | |
1893 | /* We got the register, now check the next character. */ | |
1894 | switch (**cPP) | |
1895 | { | |
1896 | case ']': | |
1897 | /* Indirect mode. We're done here. */ | |
1898 | prefixp->kind = PREFIX_NONE; | |
1899 | *is_autoincp = 0; | |
1900 | break; | |
1901 | ||
1902 | case '+': | |
1903 | /* This must be an auto-increment mode, if there's a | |
1904 | match. */ | |
1905 | prefixp->kind = PREFIX_NONE; | |
1906 | *is_autoincp = 1; | |
1907 | ||
1908 | /* We consume this character and break out to check the | |
1909 | closing ']'. */ | |
1910 | (*cPP)++; | |
1911 | break; | |
1912 | ||
1913 | case '=': | |
1914 | /* This must be indexed with assign, or offset with assign | |
1915 | to match. */ | |
1916 | (*cPP)++; | |
1917 | ||
1918 | /* Either way, the next thing must be a register. */ | |
1919 | if (! get_gen_reg (cPP, &prefixp->base_reg_number)) | |
1920 | /* No register, no match. */ | |
1921 | return 0; | |
1922 | else | |
1923 | { | |
1924 | /* We've consumed "[rN=rM", so we must be looking at | |
1925 | "+rO.s]" or "+I]", or "-I]", or "+[rO].s]" or | |
1926 | "+[rO+].s]". */ | |
1927 | if (**cPP == '+') | |
1928 | { | |
1929 | int index_reg_number; | |
1930 | (*cPP)++; | |
1931 | ||
1932 | if (**cPP == '[') | |
1933 | { | |
1934 | int size_bits; | |
1935 | /* This must be [rx=ry+[rz].s] or | |
1936 | [rx=ry+[rz+].s] or no match. We must be | |
1937 | looking at rz after consuming the '['. */ | |
1938 | (*cPP)++; | |
1939 | ||
1940 | if (!get_gen_reg (cPP, &index_reg_number)) | |
1941 | return 0; | |
1942 | ||
1943 | prefixp->kind = PREFIX_BDAP; | |
1944 | prefixp->opcode | |
1945 | = (BDAP_INDIR_OPCODE | |
1946 | + (prefixp->base_reg_number << 12) | |
1947 | + index_reg_number); | |
1948 | ||
1949 | if (**cPP == '+') | |
1950 | { | |
1951 | /* We've seen "[rx=ry+[rz+" here, so now we | |
1952 | know that there must be "].s]" left to | |
1953 | check. */ | |
1954 | (*cPP)++; | |
1955 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
1956 | } | |
1957 | ||
1958 | /* If it wasn't autoincrement, we don't need to | |
1959 | add anything. */ | |
1960 | ||
1961 | /* Check the next-to-last ']'. */ | |
1962 | if (**cPP != ']') | |
1963 | return 0; | |
1964 | ||
1965 | (*cPP)++; | |
1966 | ||
1967 | /* Check the ".s" modifier. */ | |
1968 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
1969 | return 0; | |
1970 | ||
1971 | prefixp->opcode |= size_bits << 4; | |
1972 | ||
1973 | /* Now we got [rx=ry+[rz+].s or [rx=ry+[rz].s. | |
1974 | We break out to check the final ']'. */ | |
1975 | break; | |
1976 | } | |
ab3e48dc KH |
1977 | /* It wasn't an indirection. Check if it's a |
1978 | register. */ | |
1979 | else if (get_gen_reg (cPP, &index_reg_number)) | |
47926f60 KH |
1980 | { |
1981 | int size_bits; | |
1982 | ||
1983 | /* Indexed with assign mode: "[rN+rM.S]". */ | |
1984 | prefixp->kind = PREFIX_BIAP; | |
1985 | prefixp->opcode | |
1986 | = (BIAP_OPCODE + (index_reg_number << 12) | |
1987 | + prefixp->base_reg_number /* << 0 */); | |
1988 | ||
1989 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
1990 | /* Size missing, this isn't a match. */ | |
1991 | return 0; | |
1992 | else | |
3bcbcc3d | 1993 | { |
47926f60 | 1994 | /* Size found, break out to check the |
3bcbcc3d | 1995 | final ']'. */ |
47926f60 | 1996 | prefixp->opcode |= size_bits << 4; |
3bcbcc3d HPN |
1997 | break; |
1998 | } | |
47926f60 KH |
1999 | } |
2000 | /* Not a register. Then this must be "[rN+I]". */ | |
2001 | else if (cris_get_expression (cPP, &prefixp->expr)) | |
2002 | { | |
2003 | /* We've got offset with assign mode. Fill | |
2004 | in the blanks and break out to match the | |
2005 | final ']'. */ | |
2006 | prefixp->kind = PREFIX_BDAP_IMM; | |
08caf3f8 HPN |
2007 | |
2008 | /* We tentatively put an opcode corresponding to | |
2009 | a 32-bit operand here, although it may be | |
2010 | relaxed when there's no PIC specifier for the | |
2011 | operand. */ | |
2012 | prefixp->opcode | |
2013 | = (BDAP_INDIR_OPCODE | |
2014 | | (prefixp->base_reg_number << 12) | |
2015 | | (AUTOINCR_BIT << 8) | |
2016 | | (2 << 4) | |
2017 | | REG_PC /* << 0 */); | |
2018 | ||
2019 | /* This can have a PIC suffix, specifying reloc | |
2020 | type to use. */ | |
2021 | if (pic && **cPP == PIC_SUFFIX_CHAR) | |
2022 | { | |
2023 | unsigned int relocsize; | |
2024 | ||
2025 | cris_get_pic_suffix (cPP, &prefixp->reloc, | |
2026 | &prefixp->expr); | |
2027 | ||
2028 | /* Tweak the size of the immediate operand | |
2029 | in the prefix opcode if it isn't what we | |
2030 | set. */ | |
2031 | relocsize | |
2032 | = cris_get_pic_reloc_size (prefixp->reloc); | |
2033 | if (relocsize != 4) | |
2034 | prefixp->opcode | |
2035 | = ((prefixp->opcode & ~(3 << 4)) | |
2036 | | ((relocsize >> 1) << 4)); | |
2037 | } | |
47926f60 KH |
2038 | break; |
2039 | } | |
2040 | else | |
2041 | /* Neither register nor expression found, so | |
2042 | this can't be a match. */ | |
2043 | return 0; | |
3bcbcc3d | 2044 | } |
47926f60 | 2045 | /* Not "[rN+" but perhaps "[rN-"? */ |
ab3e48dc | 2046 | else if (**cPP == '-') |
47926f60 KH |
2047 | { |
2048 | /* We must have an offset with assign mode. */ | |
2049 | if (! cris_get_expression (cPP, &prefixp->expr)) | |
2050 | /* No expression, no match. */ | |
2051 | return 0; | |
2052 | else | |
2053 | { | |
2054 | /* We've got offset with assign mode. Fill | |
2055 | in the blanks and break out to match the | |
08caf3f8 HPN |
2056 | final ']'. |
2057 | ||
2058 | Note that we don't allow a PIC suffix for an | |
2059 | operand with a minus sign. */ | |
47926f60 KH |
2060 | prefixp->kind = PREFIX_BDAP_IMM; |
2061 | break; | |
2062 | } | |
2063 | } | |
2064 | else | |
2065 | /* Neither '+' nor '-' after "[rN=rM". Lose. */ | |
2066 | return 0; | |
3bcbcc3d HPN |
2067 | } |
2068 | default: | |
2069 | /* Neither ']' nor '+' nor '=' after "[rN". Lose. */ | |
2070 | return 0; | |
2071 | } | |
2072 | } | |
2073 | ||
2074 | /* When we get here, we have a match and will just check the closing | |
2075 | ']'. We can still fail though. */ | |
2076 | if (**cPP != ']') | |
2077 | return 0; | |
2078 | else | |
2079 | { | |
2080 | /* Don't forget to consume the final ']'. | |
2081 | Then return in glory. */ | |
2082 | (*cPP)++; | |
2083 | return 1; | |
2084 | } | |
2085 | } | |
47926f60 | 2086 | /* No indirection. Perhaps a constant? */ |
ab3e48dc | 2087 | else if (cris_get_expression (cPP, imm_exprP)) |
47926f60 KH |
2088 | { |
2089 | /* Expression found, this is immediate mode. */ | |
2090 | prefixp->kind = PREFIX_NONE; | |
2091 | *is_autoincp = 1; | |
2092 | *src_regnop = REG_PC; | |
2093 | *imm_foundp = 1; | |
08caf3f8 HPN |
2094 | |
2095 | /* This can have a PIC suffix, specifying reloc type to use. The | |
2096 | caller must check that the reloc size matches the operand size. */ | |
2097 | if (pic && **cPP == PIC_SUFFIX_CHAR) | |
2098 | cris_get_pic_suffix (cPP, &prefixp->reloc, imm_exprP); | |
2099 | ||
47926f60 KH |
2100 | return 1; |
2101 | } | |
3bcbcc3d HPN |
2102 | |
2103 | /* No luck today. */ | |
2104 | return 0; | |
2105 | } | |
2106 | ||
3bcbcc3d HPN |
2107 | /* This function gets an indirect operand in a three-address operand |
2108 | combination from the string pointed out by *cPP. The pointer *cPP is | |
2109 | advanced to the character following the indirect operand on success, or | |
2110 | has an unspecified value on failure. | |
2111 | ||
2d2255b5 | 2112 | cPP Pointer to pointer to string beginning |
3bcbcc3d HPN |
2113 | with the operand |
2114 | ||
2115 | prefixp Pointer to structure containing an | |
2116 | instruction prefix | |
2117 | ||
2118 | Returns 1 iff a correct indirect operand is found. */ | |
2119 | ||
2120 | static int | |
2121 | get_3op_or_dip_prefix_op (cPP, prefixp) | |
2122 | char **cPP; | |
2123 | struct cris_prefix *prefixp; | |
2124 | { | |
ab3e48dc KH |
2125 | int reg_number; |
2126 | ||
3bcbcc3d HPN |
2127 | if (**cPP != '[') |
2128 | /* We must have a '[' or it's a clean failure. */ | |
2129 | return 0; | |
3bcbcc3d | 2130 | |
47926f60 KH |
2131 | /* Eat the first '['. */ |
2132 | (*cPP)++; | |
2133 | ||
2134 | if (**cPP == '[') | |
2135 | { | |
2136 | /* A second '[', so this must be double-indirect mode. */ | |
3bcbcc3d | 2137 | (*cPP)++; |
47926f60 KH |
2138 | prefixp->kind = PREFIX_DIP; |
2139 | prefixp->opcode = DIP_OPCODE; | |
3bcbcc3d | 2140 | |
47926f60 KH |
2141 | /* Get the register or fail entirely. */ |
2142 | if (! get_gen_reg (cPP, ®_number)) | |
2143 | return 0; | |
2144 | else | |
3bcbcc3d | 2145 | { |
47926f60 KH |
2146 | prefixp->opcode |= reg_number /* << 0 */ ; |
2147 | if (**cPP == '+') | |
2148 | { | |
2149 | /* Since we found a '+', this must be double-indirect | |
2150 | autoincrement mode. */ | |
2151 | (*cPP)++; | |
2152 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
2153 | } | |
2154 | ||
2155 | /* There's nothing particular to do, if this was a | |
2156 | double-indirect *without* autoincrement. */ | |
2157 | } | |
2158 | ||
2159 | /* Check the first ']'. The second one is checked at the end. */ | |
2160 | if (**cPP != ']') | |
2161 | return 0; | |
2162 | ||
2163 | /* Eat the first ']', so we'll be looking at a second ']'. */ | |
2164 | (*cPP)++; | |
2165 | } | |
2166 | /* No second '['. Then we should have a register here, making | |
2167 | it "[rN". */ | |
2168 | else if (get_gen_reg (cPP, &prefixp->base_reg_number)) | |
2169 | { | |
2170 | /* This must be indexed or offset mode: "[rN+I]" or | |
2171 | "[rN+rM.S]" or "[rN+[rM].S]" or "[rN+[rM+].S]". */ | |
2172 | if (**cPP == '+') | |
2173 | { | |
47926f60 KH |
2174 | int index_reg_number; |
2175 | ||
3bcbcc3d | 2176 | (*cPP)++; |
3bcbcc3d | 2177 | |
47926f60 | 2178 | if (**cPP == '[') |
3bcbcc3d | 2179 | { |
47926f60 KH |
2180 | /* This is "[rx+["... Expect a register next. */ |
2181 | int size_bits; | |
2182 | (*cPP)++; | |
2183 | ||
2184 | if (!get_gen_reg (cPP, &index_reg_number)) | |
2185 | return 0; | |
2186 | ||
2187 | prefixp->kind = PREFIX_BDAP; | |
2188 | prefixp->opcode | |
2189 | = (BDAP_INDIR_OPCODE | |
2190 | + (prefixp->base_reg_number << 12) | |
2191 | + index_reg_number); | |
2192 | ||
2193 | /* We've seen "[rx+[ry", so check if this is | |
2194 | autoincrement. */ | |
3bcbcc3d HPN |
2195 | if (**cPP == '+') |
2196 | { | |
47926f60 | 2197 | /* Yep, now at "[rx+[ry+". */ |
3bcbcc3d HPN |
2198 | (*cPP)++; |
2199 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
2200 | } | |
47926f60 KH |
2201 | /* If it wasn't autoincrement, we don't need to |
2202 | add anything. */ | |
3bcbcc3d | 2203 | |
47926f60 KH |
2204 | /* Check a first closing ']': "[rx+[ry]" or |
2205 | "[rx+[ry+]". */ | |
2206 | if (**cPP != ']') | |
2207 | return 0; | |
2208 | (*cPP)++; | |
3bcbcc3d | 2209 | |
47926f60 KH |
2210 | /* Now expect a size modifier ".S". */ |
2211 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
2212 | return 0; | |
3bcbcc3d | 2213 | |
47926f60 KH |
2214 | prefixp->opcode |= size_bits << 4; |
2215 | ||
2216 | /* Ok, all interesting stuff has been seen: | |
2217 | "[rx+[ry+].S" or "[rx+[ry].S". We only need to | |
2218 | expect a final ']', which we'll do in a common | |
2219 | closing session. */ | |
2220 | } | |
2221 | /* Seen "[rN+", but not a '[', so check if we have a | |
2222 | register. */ | |
2223 | else if (get_gen_reg (cPP, &index_reg_number)) | |
2224 | { | |
2225 | /* This is indexed mode: "[rN+rM.S]" or | |
2226 | "[rN+rM.S+]". */ | |
2227 | int size_bits; | |
2228 | prefixp->kind = PREFIX_BIAP; | |
2229 | prefixp->opcode | |
2230 | = (BIAP_OPCODE | |
2231 | | prefixp->base_reg_number /* << 0 */ | |
2232 | | (index_reg_number << 12)); | |
2233 | ||
07e90ad5 | 2234 | /* Consume the ".S". */ |
47926f60 KH |
2235 | if (! get_bwd_size_modifier (cPP, &size_bits)) |
2236 | /* Missing size, so fail. */ | |
2237 | return 0; | |
3bcbcc3d | 2238 | else |
47926f60 KH |
2239 | /* Size found. Add that piece and drop down to |
2240 | the common checking of the closing ']'. */ | |
2241 | prefixp->opcode |= size_bits << 4; | |
2242 | } | |
2243 | /* Seen "[rN+", but not a '[' or a register, so then | |
2244 | it must be a constant "I". */ | |
2245 | else if (cris_get_expression (cPP, &prefixp->expr)) | |
2246 | { | |
2247 | /* Expression found, so fill in the bits of offset | |
2248 | mode and drop down to check the closing ']'. */ | |
2249 | prefixp->kind = PREFIX_BDAP_IMM; | |
08caf3f8 HPN |
2250 | |
2251 | /* We tentatively put an opcode corresponding to a 32-bit | |
2252 | operand here, although it may be relaxed when there's no | |
2253 | PIC specifier for the operand. */ | |
2254 | prefixp->opcode | |
2255 | = (BDAP_INDIR_OPCODE | |
2256 | | (prefixp->base_reg_number << 12) | |
2257 | | (AUTOINCR_BIT << 8) | |
2258 | | (2 << 4) | |
2259 | | REG_PC /* << 0 */); | |
2260 | ||
2261 | /* This can have a PIC suffix, specifying reloc type to use. */ | |
2262 | if (pic && **cPP == PIC_SUFFIX_CHAR) | |
2263 | { | |
2264 | unsigned int relocsize; | |
2265 | ||
2266 | cris_get_pic_suffix (cPP, &prefixp->reloc, &prefixp->expr); | |
2267 | ||
2268 | /* Tweak the size of the immediate operand in the prefix | |
2269 | opcode if it isn't what we set. */ | |
2270 | relocsize = cris_get_pic_reloc_size (prefixp->reloc); | |
2271 | if (relocsize != 4) | |
2272 | prefixp->opcode | |
2273 | = ((prefixp->opcode & ~(3 << 4)) | |
2274 | | ((relocsize >> 1) << 4)); | |
2275 | } | |
47926f60 KH |
2276 | } |
2277 | else | |
2278 | /* Nothing valid here: lose. */ | |
2279 | return 0; | |
2280 | } | |
2281 | /* Seen "[rN" but no '+', so check if it's a '-'. */ | |
2282 | else if (**cPP == '-') | |
2283 | { | |
2284 | /* Yep, we must have offset mode. */ | |
2285 | if (! cris_get_expression (cPP, &prefixp->expr)) | |
2286 | /* No expression, so we lose. */ | |
2287 | return 0; | |
2288 | else | |
2289 | { | |
2290 | /* Expression found to make this offset mode, so | |
2291 | fill those bits and drop down to check the | |
08caf3f8 HPN |
2292 | closing ']'. |
2293 | ||
2294 | Note that we don't allow a PIC suffix for | |
2295 | an operand with a minus sign like this. */ | |
47926f60 KH |
2296 | prefixp->kind = PREFIX_BDAP_IMM; |
2297 | } | |
2298 | } | |
2299 | else | |
2300 | { | |
2301 | /* We've seen "[rN", but not '+' or '-'; rather a ']'. | |
2302 | Hmm. Normally this is a simple indirect mode that we | |
2303 | shouldn't match, but if we expect ']', then we have a | |
2304 | zero offset, so it can be a three-address-operand, | |
2305 | like "[rN],rO,rP", thus offset mode. | |
2306 | ||
2307 | Don't eat the ']', that will be done in the closing | |
2308 | ceremony. */ | |
2309 | prefixp->expr.X_op = O_constant; | |
2310 | prefixp->expr.X_add_number = 0; | |
2311 | prefixp->expr.X_add_symbol = NULL; | |
2312 | prefixp->expr.X_op_symbol = NULL; | |
2313 | prefixp->kind = PREFIX_BDAP_IMM; | |
2314 | } | |
2315 | } | |
2316 | /* A '[', but no second '[', and no register. Check if we | |
2317 | have an expression, making this "[I]" for a double-indirect | |
2318 | prefix. */ | |
2319 | else if (cris_get_expression (cPP, &prefixp->expr)) | |
2320 | { | |
2321 | /* Expression found, the so called absolute mode for a | |
2322 | double-indirect prefix on PC. */ | |
2323 | prefixp->kind = PREFIX_DIP; | |
2324 | prefixp->opcode = DIP_OPCODE | (AUTOINCR_BIT << 8) | REG_PC; | |
2325 | prefixp->reloc = BFD_RELOC_32; | |
2326 | } | |
2327 | else | |
2328 | /* Neither '[' nor register nor expression. We lose. */ | |
2329 | return 0; | |
3bcbcc3d HPN |
2330 | |
2331 | /* We get here as a closing ceremony to a successful match. We just | |
2332 | need to check the closing ']'. */ | |
2333 | if (**cPP != ']') | |
2334 | /* Oops. Close but no air-polluter. */ | |
2335 | return 0; | |
2336 | ||
2337 | /* Don't forget to consume that ']', before returning in glory. */ | |
2338 | (*cPP)++; | |
2339 | return 1; | |
2340 | } | |
2341 | ||
3bcbcc3d HPN |
2342 | /* Get an expression from the string pointed out by *cPP. |
2343 | The pointer *cPP is advanced to the character following the expression | |
2344 | on a success, or retains its original value otherwise. | |
2345 | ||
2346 | cPP Pointer to pointer to string beginning with the expression. | |
2347 | ||
2348 | exprP Pointer to structure containing the expression. | |
2349 | ||
47926f60 | 2350 | Return 1 iff a correct expression is found. */ |
3bcbcc3d HPN |
2351 | |
2352 | static int | |
2353 | cris_get_expression (cPP, exprP) | |
47926f60 KH |
2354 | char **cPP; |
2355 | expressionS *exprP; | |
3bcbcc3d HPN |
2356 | { |
2357 | char *saved_input_line_pointer; | |
2358 | segT exp; | |
2359 | ||
2360 | /* The "expression" function expects to find an expression at the | |
2361 | global variable input_line_pointer, so we have to save it to give | |
2362 | the impression that we don't fiddle with global variables. */ | |
2363 | saved_input_line_pointer = input_line_pointer; | |
2364 | input_line_pointer = *cPP; | |
2365 | ||
2366 | exp = expression (exprP); | |
2367 | if (exprP->X_op == O_illegal || exprP->X_op == O_absent) | |
2368 | { | |
2369 | input_line_pointer = saved_input_line_pointer; | |
2370 | return 0; | |
2371 | } | |
2372 | ||
2373 | /* Everything seems to be fine, just restore the global | |
2374 | input_line_pointer and say we're successful. */ | |
2375 | *cPP = input_line_pointer; | |
2376 | input_line_pointer = saved_input_line_pointer; | |
2377 | return 1; | |
2378 | } | |
2379 | ||
3bcbcc3d HPN |
2380 | /* Get a sequence of flag characters from *spp. The pointer *cPP is |
2381 | advanced to the character following the expression. The flag | |
2382 | characters are consecutive, no commas or spaces. | |
2383 | ||
2384 | cPP Pointer to pointer to string beginning with the expression. | |
2385 | ||
2386 | flagp Pointer to int to return the flags expression. | |
2387 | ||
2388 | Return 1 iff a correct flags expression is found. */ | |
2389 | ||
2390 | static int | |
2391 | get_flags (cPP, flagsp) | |
2392 | char **cPP; | |
2393 | int *flagsp; | |
2394 | { | |
2395 | for (;;) | |
2396 | { | |
2397 | switch (**cPP) | |
2398 | { | |
2399 | case 'd': | |
2400 | case 'D': | |
2401 | case 'm': | |
2402 | case 'M': | |
2403 | *flagsp |= 0x80; | |
2404 | break; | |
2405 | ||
2406 | case 'e': | |
2407 | case 'E': | |
2408 | case 'b': | |
2409 | case 'B': | |
2410 | *flagsp |= 0x40; | |
2411 | break; | |
2412 | ||
2413 | case 'i': | |
2414 | case 'I': | |
2415 | *flagsp |= 0x20; | |
2416 | break; | |
2417 | ||
2418 | case 'x': | |
2419 | case 'X': | |
2420 | *flagsp |= 0x10; | |
2421 | break; | |
2422 | ||
2423 | case 'n': | |
2424 | case 'N': | |
2425 | *flagsp |= 0x8; | |
2426 | break; | |
2427 | ||
2428 | case 'z': | |
2429 | case 'Z': | |
2430 | *flagsp |= 0x4; | |
2431 | break; | |
2432 | ||
2433 | case 'v': | |
2434 | case 'V': | |
2435 | *flagsp |= 0x2; | |
2436 | break; | |
2437 | ||
2438 | case 'c': | |
2439 | case 'C': | |
2440 | *flagsp |= 1; | |
2441 | break; | |
2442 | ||
2443 | default: | |
2444 | /* We consider this successful if we stop at a comma or | |
47926f60 | 2445 | whitespace. Anything else, and we consider it a failure. */ |
3bcbcc3d HPN |
2446 | if (**cPP != ',' |
2447 | && **cPP != 0 | |
3882b010 | 2448 | && ! ISSPACE (**cPP)) |
3bcbcc3d HPN |
2449 | return 0; |
2450 | else | |
2451 | return 1; | |
2452 | } | |
2453 | ||
2454 | /* Don't forget to consume each flag character. */ | |
2455 | (*cPP)++; | |
2456 | } | |
2457 | } | |
2458 | ||
3bcbcc3d HPN |
2459 | /* Generate code and fixes for a BDAP prefix. |
2460 | ||
2461 | base_regno Int containing the base register number. | |
2462 | ||
2463 | exprP Pointer to structure containing the offset expression. */ | |
2464 | ||
2465 | static void | |
2466 | gen_bdap (base_regno, exprP) | |
47926f60 KH |
2467 | int base_regno; |
2468 | expressionS *exprP; | |
3bcbcc3d HPN |
2469 | { |
2470 | unsigned int opcode; | |
2471 | char *opcodep; | |
2472 | ||
2473 | /* Put out the prefix opcode; assume quick immediate mode at first. */ | |
2474 | opcode = BDAP_QUICK_OPCODE | (base_regno << 12); | |
ed67db7a | 2475 | opcodep = cris_insn_first_word_frag (); |
3bcbcc3d HPN |
2476 | md_number_to_chars (opcodep, opcode, 2); |
2477 | ||
2478 | if (exprP->X_op == O_constant) | |
2479 | { | |
2480 | /* We have an absolute expression that we know the size of right | |
47926f60 | 2481 | now. */ |
3bcbcc3d HPN |
2482 | long int value; |
2483 | int size; | |
2484 | ||
2485 | value = exprP->X_add_number; | |
2486 | if (value < -32768 || value > 32767) | |
2487 | /* Outside range for a "word", make it a dword. */ | |
2488 | size = 2; | |
2489 | else | |
47926f60 | 2490 | /* Assume "word" size. */ |
3bcbcc3d HPN |
2491 | size = 1; |
2492 | ||
2493 | /* If this is a signed-byte value, we can fit it into the prefix | |
2494 | insn itself. */ | |
2495 | if (value >= -128 && value <= 127) | |
2496 | opcodep[0] = value; | |
2497 | else | |
2498 | { | |
2499 | /* This is a word or dword displacement, which will be put in a | |
2500 | word or dword after the prefix. */ | |
2501 | char *p; | |
2502 | ||
2503 | opcodep[0] = BDAP_PC_LOW + (size << 4); | |
2504 | opcodep[1] &= 0xF0; | |
2505 | opcodep[1] |= BDAP_INCR_HIGH; | |
2506 | p = frag_more (1 << size); | |
2507 | md_number_to_chars (p, value, 1 << size); | |
2508 | } | |
2509 | } | |
2510 | else | |
08caf3f8 HPN |
2511 | { |
2512 | /* Handle complex expressions. */ | |
2513 | valueT addvalue | |
1c971160 | 2514 | = SIMPLE_EXPR (exprP) ? exprP->X_add_number : 0; |
08caf3f8 | 2515 | symbolS *sym |
1c971160 HPN |
2516 | = (SIMPLE_EXPR (exprP) |
2517 | ? exprP->X_add_symbol : make_expr_symbol (exprP)); | |
08caf3f8 HPN |
2518 | |
2519 | /* The expression is not defined yet but may become absolute. We | |
2520 | make it a relocation to be relaxed. */ | |
2521 | frag_var (rs_machine_dependent, 4, 0, | |
2522 | ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF), | |
2523 | sym, addvalue, opcodep); | |
2524 | } | |
3bcbcc3d HPN |
2525 | } |
2526 | ||
3bcbcc3d HPN |
2527 | /* Encode a branch displacement in the range -256..254 into the form used |
2528 | by CRIS conditional branch instructions. | |
2529 | ||
2530 | offset The displacement value in bytes. */ | |
2531 | ||
2532 | static int | |
2533 | branch_disp (offset) | |
2534 | int offset; | |
2535 | { | |
2536 | int disp; | |
2537 | ||
2538 | disp = offset & 0xFE; | |
2539 | ||
2540 | if (offset < 0) | |
2541 | disp |= 1; | |
2542 | ||
2543 | return disp; | |
2544 | } | |
2545 | ||
3bcbcc3d HPN |
2546 | /* Generate code and fixes for a 32-bit conditional branch instruction |
2547 | created by "extending" an existing 8-bit branch instruction. | |
2548 | ||
2549 | opcodep Pointer to the word containing the original 8-bit branch | |
2550 | instruction. | |
2551 | ||
2552 | writep Pointer to "extension area" following the first instruction | |
2553 | word. | |
2554 | ||
2555 | fragP Pointer to the frag containing the instruction. | |
2556 | ||
2557 | add_symP, Parts of the destination address expression. | |
2558 | sub_symP, | |
2559 | add_num. */ | |
2560 | ||
2561 | static void | |
2562 | gen_cond_branch_32 (opcodep, writep, fragP, add_symP, sub_symP, add_num) | |
2563 | char *opcodep; | |
2564 | char *writep; | |
2565 | fragS *fragP; | |
2566 | symbolS *add_symP; | |
2567 | symbolS *sub_symP; | |
2568 | long int add_num; | |
2569 | { | |
2570 | if (warn_for_branch_expansion) | |
08caf3f8 HPN |
2571 | as_warn_where (fragP->fr_file, fragP->fr_line, |
2572 | _("32-bit conditional branch generated")); | |
3bcbcc3d HPN |
2573 | |
2574 | /* Here, writep points to what will be opcodep + 2. First, we change | |
2575 | the actual branch in opcodep[0] and opcodep[1], so that in the | |
2576 | final insn, it will look like: | |
2577 | opcodep+10: Bcc .-6 | |
2578 | ||
2579 | This means we don't have to worry about changing the opcode or | |
08caf3f8 | 2580 | messing with the delay-slot instruction. So, we move it to last in |
3bcbcc3d HPN |
2581 | the "extended" branch, and just change the displacement. Admittedly, |
2582 | it's not the optimal extended construct, but we should get this | |
2583 | rarely enough that it shouldn't matter. */ | |
2584 | ||
47926f60 | 2585 | writep[8] = branch_disp (-2 - 6); |
3bcbcc3d HPN |
2586 | writep[9] = opcodep[1]; |
2587 | ||
2588 | /* Then, we change the branch to an unconditional branch over the | |
2589 | extended part, to the new location of the Bcc: | |
2590 | opcodep: BA .+10 | |
2591 | opcodep+2: NOP | |
2592 | ||
2593 | Note that these two writes are to currently different locations, | |
2594 | merged later. */ | |
2595 | ||
2596 | md_number_to_chars (opcodep, BA_QUICK_OPCODE + 8, 2); | |
2597 | md_number_to_chars (writep, NOP_OPCODE, 2); | |
2598 | ||
2599 | /* Then the extended thing, the 32-bit jump insn. | |
08caf3f8 HPN |
2600 | opcodep+4: JUMP [PC+] |
2601 | or, in the PIC case, | |
2602 | opcodep+4: ADD [PC+],PC. */ | |
3bcbcc3d | 2603 | |
08caf3f8 HPN |
2604 | md_number_to_chars (writep + 2, |
2605 | pic ? ADD_PC_INCR_OPCODE : JUMP_PC_INCR_OPCODE, 2); | |
3bcbcc3d HPN |
2606 | |
2607 | /* We have to fill in the actual value too. | |
2608 | opcodep+6: .DWORD | |
2609 | This is most probably an expression, but we can cope with an absolute | |
08caf3f8 | 2610 | value too. FIXME: Testcase needed with and without pic. */ |
3bcbcc3d HPN |
2611 | |
2612 | if (add_symP == NULL && sub_symP == NULL) | |
08caf3f8 HPN |
2613 | { |
2614 | /* An absolute address. */ | |
2615 | if (pic) | |
2616 | fix_new (fragP, writep + 4 - fragP->fr_literal, 4, | |
2617 | section_symbol (absolute_section), | |
2618 | add_num, 1, BFD_RELOC_32_PCREL); | |
2619 | else | |
2620 | md_number_to_chars (writep + 4, add_num, 4); | |
2621 | } | |
3bcbcc3d HPN |
2622 | else |
2623 | { | |
08caf3f8 HPN |
2624 | if (sub_symP != NULL) |
2625 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
2626 | _("Complex expression not supported")); | |
3bcbcc3d | 2627 | |
08caf3f8 | 2628 | /* Not absolute, we have to make it a frag for later evaluation. */ |
3bcbcc3d | 2629 | fix_new (fragP, writep + 4 - fragP->fr_literal, 4, add_symP, |
08caf3f8 | 2630 | add_num, pic ? 1 : 0, pic ? BFD_RELOC_32_PCREL : BFD_RELOC_32); |
3bcbcc3d HPN |
2631 | } |
2632 | } | |
2633 | ||
08caf3f8 HPN |
2634 | /* Get the size of an immediate-reloc in bytes. Only valid for PIC |
2635 | relocs. */ | |
2636 | ||
2637 | static unsigned int | |
2638 | cris_get_pic_reloc_size (reloc) | |
2639 | bfd_reloc_code_real_type reloc; | |
2640 | { | |
2641 | return reloc == BFD_RELOC_CRIS_16_GOTPLT || reloc == BFD_RELOC_CRIS_16_GOT | |
2642 | ? 2 : 4; | |
2643 | } | |
2644 | ||
2645 | /* Store a reloc type at *RELOCP corresponding to the PIC suffix at *CPP. | |
2646 | Adjust *EXPRP with any addend found after the PIC suffix. */ | |
2647 | ||
2648 | static void | |
2649 | cris_get_pic_suffix (cPP, relocp, exprP) | |
2650 | char **cPP; | |
2651 | bfd_reloc_code_real_type *relocp; | |
2652 | expressionS *exprP; | |
2653 | { | |
2654 | char *s = *cPP; | |
2655 | unsigned int i; | |
2656 | expressionS const_expr; | |
2657 | ||
2658 | const struct pic_suffixes_struct | |
2659 | { | |
2660 | const char *const suffix; | |
2661 | unsigned int len; | |
2662 | bfd_reloc_code_real_type reloc; | |
2663 | } pic_suffixes[] = | |
2664 | { | |
2665 | #undef PICMAP | |
2666 | #define PICMAP(s, r) {s, sizeof (s) - 1, r} | |
2667 | /* Keep this in order with longest unambiguous prefix first. */ | |
2668 | PICMAP ("GOTPLT16", BFD_RELOC_CRIS_16_GOTPLT), | |
2669 | PICMAP ("GOTPLT", BFD_RELOC_CRIS_32_GOTPLT), | |
2670 | PICMAP ("PLTG", BFD_RELOC_CRIS_32_PLT_GOTREL), | |
2671 | PICMAP ("PLT", BFD_RELOC_CRIS_32_PLT_PCREL), | |
2672 | PICMAP ("GOTOFF", BFD_RELOC_CRIS_32_GOTREL), | |
2673 | PICMAP ("GOT16", BFD_RELOC_CRIS_16_GOT), | |
2674 | PICMAP ("GOT", BFD_RELOC_CRIS_32_GOT) | |
2675 | }; | |
2676 | ||
2677 | /* We've already seen the ':', so consume it. */ | |
2678 | s++; | |
2679 | ||
2680 | for (i = 0; i < sizeof (pic_suffixes)/sizeof (pic_suffixes[0]); i++) | |
2681 | { | |
2682 | if (strncmp (s, pic_suffixes[i].suffix, pic_suffixes[i].len) == 0 | |
2683 | && ! is_part_of_name (s[pic_suffixes[i].len])) | |
2684 | { | |
2685 | /* We have a match. Consume the suffix and set the relocation | |
2686 | type. */ | |
2687 | s += pic_suffixes[i].len; | |
2688 | ||
2689 | /* There can be a constant term appended. If so, we will add it | |
2690 | to *EXPRP. */ | |
2691 | if (*s == '+' || *s == '-') | |
2692 | { | |
2693 | if (! cris_get_expression (&s, &const_expr)) | |
2694 | /* There was some kind of syntax error. Bail out. */ | |
2695 | break; | |
2696 | ||
2697 | /* Allow complex expressions as the constant part. It still | |
b6ff326e | 2698 | has to be an assembly-time constant or there will be an |
08caf3f8 | 2699 | error emitting the reloc. This makes the PIC qualifiers |
d551a338 | 2700 | idempotent; foo:GOTOFF+32 == foo+32:GOTOFF. The former we |
08caf3f8 HPN |
2701 | recognize here; the latter is parsed in the incoming |
2702 | expression. */ | |
2703 | exprP->X_add_symbol = make_expr_symbol (exprP); | |
2704 | exprP->X_op = O_add; | |
2705 | exprP->X_add_number = 0; | |
2706 | exprP->X_op_symbol = make_expr_symbol (&const_expr); | |
2707 | } | |
2708 | ||
2709 | *relocp = pic_suffixes[i].reloc; | |
2710 | *cPP = s; | |
2711 | return; | |
2712 | } | |
2713 | } | |
2714 | ||
2715 | /* No match. Don't consume anything; fall back and there will be a | |
2716 | syntax error. */ | |
2717 | } | |
2718 | ||
3bcbcc3d HPN |
2719 | /* This *could* be: |
2720 | ||
47926f60 KH |
2721 | Turn a string in input_line_pointer into a floating point constant |
2722 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
2723 | of LITTLENUMS emitted is stored in *SIZEP. | |
3bcbcc3d HPN |
2724 | |
2725 | type A character from FLTCHARS that describes what kind of | |
2726 | floating-point number is wanted. | |
2727 | ||
2728 | litp A pointer to an array that the result should be stored in. | |
2729 | ||
2730 | sizep A pointer to an integer where the size of the result is stored. | |
2731 | ||
2732 | But we don't support floating point constants in assembly code *at all*, | |
2733 | since it's suboptimal and just opens up bug opportunities. GCC emits | |
2734 | the bit patterns as hex. All we could do here is to emit what GCC | |
2735 | would have done in the first place. *Nobody* writes floating-point | |
2736 | code as assembly code, but if they do, they should be able enough to | |
2737 | find out the correct bit patterns and use them. */ | |
2738 | ||
2739 | char * | |
2740 | md_atof (type, litp, sizep) | |
2741 | char type ATTRIBUTE_UNUSED; | |
2742 | char *litp ATTRIBUTE_UNUSED; | |
47926f60 | 2743 | int *sizep ATTRIBUTE_UNUSED; |
3bcbcc3d HPN |
2744 | { |
2745 | /* FIXME: Is this function mentioned in the internals.texi manual? If | |
2746 | not, add it. */ | |
2747 | return _("Bad call to md_atof () - floating point formats are not supported"); | |
2748 | } | |
2749 | ||
3bcbcc3d HPN |
2750 | /* Turn a number as a fixS * into a series of bytes that represents the |
2751 | number on the target machine. The purpose of this procedure is the | |
2752 | same as that of md_number_to_chars but this procedure is supposed to | |
2753 | handle general bit field fixes and machine-dependent fixups. | |
2754 | ||
2755 | bufp Pointer to an array where the result should be stored. | |
2756 | ||
2757 | val The value to store. | |
2758 | ||
2759 | n The number of bytes in "val" that should be stored. | |
2760 | ||
08caf3f8 HPN |
2761 | fixP The fix to be applied to the bit field starting at bufp. |
2762 | ||
2763 | seg The segment containing this number. */ | |
3bcbcc3d HPN |
2764 | |
2765 | static void | |
08caf3f8 | 2766 | cris_number_to_imm (bufp, val, n, fixP, seg) |
3bcbcc3d HPN |
2767 | char *bufp; |
2768 | long val; | |
2769 | int n; | |
2770 | fixS *fixP; | |
08caf3f8 | 2771 | segT seg; |
3bcbcc3d HPN |
2772 | { |
2773 | segT sym_seg; | |
2774 | ||
2775 | know (n <= 4); | |
2776 | know (fixP); | |
2777 | ||
2778 | /* We put the relative "vma" for the other segment for inter-segment | |
2779 | relocations in the object data to stay binary "compatible" (with an | |
2780 | uninteresting old version) for the relocation. | |
2781 | Maybe delete some day. */ | |
2782 | if (fixP->fx_addsy | |
08caf3f8 | 2783 | && (sym_seg = S_GET_SEGMENT (fixP->fx_addsy)) != seg) |
3bcbcc3d HPN |
2784 | val += sym_seg->vma; |
2785 | ||
08caf3f8 HPN |
2786 | if (fixP->fx_addsy != NULL || fixP->fx_pcrel) |
2787 | switch (fixP->fx_r_type) | |
2788 | { | |
2789 | /* These must be fully resolved when getting here. */ | |
2790 | case BFD_RELOC_32_PCREL: | |
2791 | case BFD_RELOC_16_PCREL: | |
2792 | case BFD_RELOC_8_PCREL: | |
2793 | as_bad_where (fixP->fx_frag->fr_file, fixP->fx_frag->fr_line, | |
2794 | _("PC-relative relocation must be trivially resolved")); | |
2795 | default: | |
2796 | ; | |
2797 | } | |
2798 | ||
3bcbcc3d HPN |
2799 | switch (fixP->fx_r_type) |
2800 | { | |
2801 | /* Ditto here, we put the addend into the object code as | |
2802 | well as the reloc addend. Keep it that way for now, to simplify | |
2803 | regression tests on the object file contents. FIXME: Seems | |
2804 | uninteresting now that we have a test suite. */ | |
2805 | ||
08caf3f8 HPN |
2806 | case BFD_RELOC_CRIS_16_GOT: |
2807 | case BFD_RELOC_CRIS_32_GOT: | |
2808 | case BFD_RELOC_CRIS_32_GOTREL: | |
2809 | case BFD_RELOC_CRIS_16_GOTPLT: | |
2810 | case BFD_RELOC_CRIS_32_GOTPLT: | |
2811 | case BFD_RELOC_CRIS_32_PLT_GOTREL: | |
2812 | case BFD_RELOC_CRIS_32_PLT_PCREL: | |
2813 | /* We don't want to put in any kind of non-zero bits in the data | |
2814 | being relocated for these. */ | |
2815 | break; | |
2816 | ||
3bcbcc3d | 2817 | case BFD_RELOC_32: |
08caf3f8 | 2818 | case BFD_RELOC_32_PCREL: |
3bcbcc3d HPN |
2819 | /* No use having warnings here, since most hosts have a 32-bit type |
2820 | for "long" (which will probably change soon, now that I wrote | |
2821 | this). */ | |
2822 | bufp[3] = (val >> 24) & 0xFF; | |
2823 | bufp[2] = (val >> 16) & 0xFF; | |
2824 | bufp[1] = (val >> 8) & 0xFF; | |
2825 | bufp[0] = val & 0xFF; | |
2826 | break; | |
2827 | ||
2828 | /* FIXME: The 16 and 8-bit cases should have a way to check | |
2829 | whether a signed or unsigned (or any signedness) number is | |
2830 | accepted. | |
2831 | FIXME: Does the as_bad calls find the line number by themselves, | |
2832 | or should we change them into as_bad_where? */ | |
2833 | ||
2834 | case BFD_RELOC_16: | |
08caf3f8 | 2835 | case BFD_RELOC_16_PCREL: |
3bcbcc3d HPN |
2836 | if (val > 0xffff || val < -32768) |
2837 | as_bad (_("Value not in 16 bit range: %ld"), val); | |
2838 | if (! fixP->fx_addsy) | |
2839 | { | |
2840 | bufp[1] = (val >> 8) & 0xFF; | |
2841 | bufp[0] = val & 0xFF; | |
2842 | } | |
2843 | break; | |
2844 | ||
2845 | case BFD_RELOC_8: | |
08caf3f8 | 2846 | case BFD_RELOC_8_PCREL: |
3bcbcc3d HPN |
2847 | if (val > 255 || val < -128) |
2848 | as_bad (_("Value not in 8 bit range: %ld"), val); | |
2849 | if (! fixP->fx_addsy) | |
2850 | bufp[0] = val & 0xFF; | |
2851 | break; | |
2852 | ||
2853 | case BFD_RELOC_CRIS_UNSIGNED_4: | |
2854 | if (val > 15 || val < 0) | |
2855 | as_bad (_("Value not in 4 bit unsigned range: %ld"), val); | |
2856 | if (! fixP->fx_addsy) | |
2857 | bufp[0] |= val & 0x0F; | |
2858 | break; | |
2859 | ||
2860 | case BFD_RELOC_CRIS_UNSIGNED_5: | |
2861 | if (val > 31 || val < 0) | |
2862 | as_bad (_("Value not in 5 bit unsigned range: %ld"), val); | |
2863 | if (! fixP->fx_addsy) | |
2864 | bufp[0] |= val & 0x1F; | |
2865 | break; | |
2866 | ||
2867 | case BFD_RELOC_CRIS_SIGNED_6: | |
2868 | if (val > 31 || val < -32) | |
2869 | as_bad (_("Value not in 6 bit range: %ld"), val); | |
2870 | if (! fixP->fx_addsy) | |
2871 | bufp[0] |= val & 0x3F; | |
2872 | break; | |
2873 | ||
2874 | case BFD_RELOC_CRIS_UNSIGNED_6: | |
2875 | if (val > 63 || val < 0) | |
2876 | as_bad (_("Value not in 6 bit unsigned range: %ld"), val); | |
2877 | if (! fixP->fx_addsy) | |
2878 | bufp[0] |= val & 0x3F; | |
2879 | break; | |
2880 | ||
2881 | case BFD_RELOC_CRIS_BDISP8: | |
2882 | if (! fixP->fx_addsy) | |
2883 | bufp[0] = branch_disp (val); | |
2884 | break; | |
2885 | ||
2886 | case BFD_RELOC_NONE: | |
2887 | /* May actually happen automatically. For example at broken | |
2888 | words, if the word turns out not to be broken. | |
47926f60 | 2889 | FIXME: When? Which testcase? */ |
3bcbcc3d HPN |
2890 | if (! fixP->fx_addsy) |
2891 | md_number_to_chars (bufp, val, n); | |
2892 | break; | |
2893 | ||
2894 | case BFD_RELOC_VTABLE_INHERIT: | |
2895 | /* This borrowed from tc-ppc.c on a whim. */ | |
2896 | if (fixP->fx_addsy | |
2897 | && !S_IS_DEFINED (fixP->fx_addsy) | |
2898 | && !S_IS_WEAK (fixP->fx_addsy)) | |
2899 | S_SET_WEAK (fixP->fx_addsy); | |
7b15d668 HPN |
2900 | /* Fall through. */ |
2901 | ||
3bcbcc3d | 2902 | case BFD_RELOC_VTABLE_ENTRY: |
3bcbcc3d HPN |
2903 | fixP->fx_done = 0; |
2904 | break; | |
2905 | ||
2906 | default: | |
2907 | BAD_CASE (fixP->fx_r_type); | |
2908 | } | |
2909 | } | |
2910 | ||
3bcbcc3d HPN |
2911 | /* Processes machine-dependent command line options. Called once for |
2912 | each option on the command line that the machine-independent part of | |
2913 | GAS does not understand. */ | |
47926f60 | 2914 | |
3bcbcc3d HPN |
2915 | int |
2916 | md_parse_option (arg, argp) | |
2917 | int arg; | |
2918 | char *argp ATTRIBUTE_UNUSED; | |
2919 | { | |
2920 | switch (arg) | |
2921 | { | |
2922 | case 'H': | |
2923 | case 'h': | |
7b15d668 | 2924 | printf (_("Please use --help to see usage and options for this assembler.\n")); |
3bcbcc3d | 2925 | md_show_usage (stdout); |
7b15d668 | 2926 | exit (EXIT_SUCCESS); |
3bcbcc3d HPN |
2927 | |
2928 | case 'N': | |
2929 | warn_for_branch_expansion = 1; | |
2930 | return 1; | |
2931 | ||
7b15d668 | 2932 | case OPTION_NO_US: |
b34976b6 | 2933 | demand_register_prefix = TRUE; |
7b15d668 HPN |
2934 | |
2935 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
08caf3f8 | 2936 | as_bad (_("--no-underscore is invalid with a.out format")); |
7b15d668 | 2937 | else |
b34976b6 | 2938 | symbols_have_leading_underscore = FALSE; |
7b15d668 HPN |
2939 | return 1; |
2940 | ||
2941 | case OPTION_US: | |
b34976b6 AM |
2942 | demand_register_prefix = FALSE; |
2943 | symbols_have_leading_underscore = TRUE; | |
7b15d668 HPN |
2944 | return 1; |
2945 | ||
08caf3f8 | 2946 | case OPTION_PIC: |
b34976b6 | 2947 | pic = TRUE; |
08caf3f8 HPN |
2948 | return 1; |
2949 | ||
3bcbcc3d HPN |
2950 | default: |
2951 | return 0; | |
47926f60 | 2952 | } |
3bcbcc3d HPN |
2953 | } |
2954 | ||
2955 | /* Round up a section size to the appropriate boundary. */ | |
2956 | valueT | |
2957 | md_section_align (segment, size) | |
2958 | segT segment; | |
2959 | valueT size; | |
2960 | { | |
2961 | /* Round all sects to multiple of 4, except the bss section, which | |
2962 | we'll round to word-size. | |
2963 | ||
2964 | FIXME: Check if this really matters. All sections should be | |
2965 | rounded up, and all sections should (optionally) be assumed to be | |
2966 | dword-aligned, it's just that there is actual usage of linking to a | |
2967 | multiple of two. */ | |
2968 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
2969 | { | |
2970 | if (segment == bss_section) | |
2971 | return (size + 1) & ~1; | |
2972 | return (size + 3) & ~3; | |
2973 | } | |
2974 | else | |
2975 | { | |
2976 | /* FIXME: Is this wanted? It matches the testsuite, but that's not | |
2977 | really a valid reason. */ | |
2978 | if (segment == text_section) | |
2979 | return (size + 3) & ~3; | |
2980 | } | |
2981 | ||
2982 | return size; | |
2983 | } | |
2984 | ||
3bcbcc3d HPN |
2985 | /* Generate a machine-dependent relocation. */ |
2986 | arelent * | |
2987 | tc_gen_reloc (section, fixP) | |
2988 | asection *section ATTRIBUTE_UNUSED; | |
2989 | fixS *fixP; | |
2990 | { | |
2991 | arelent *relP; | |
2992 | bfd_reloc_code_real_type code; | |
2993 | ||
2994 | switch (fixP->fx_r_type) | |
2995 | { | |
08caf3f8 HPN |
2996 | case BFD_RELOC_CRIS_16_GOT: |
2997 | case BFD_RELOC_CRIS_32_GOT: | |
2998 | case BFD_RELOC_CRIS_16_GOTPLT: | |
2999 | case BFD_RELOC_CRIS_32_GOTPLT: | |
3000 | case BFD_RELOC_CRIS_32_GOTREL: | |
3001 | case BFD_RELOC_CRIS_32_PLT_GOTREL: | |
3002 | case BFD_RELOC_CRIS_32_PLT_PCREL: | |
3bcbcc3d HPN |
3003 | case BFD_RELOC_32: |
3004 | case BFD_RELOC_16: | |
3005 | case BFD_RELOC_8: | |
3006 | case BFD_RELOC_VTABLE_INHERIT: | |
3007 | case BFD_RELOC_VTABLE_ENTRY: | |
3008 | code = fixP->fx_r_type; | |
3009 | break; | |
3010 | default: | |
3011 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3012 | _("Semantics error. This type of operand can not be relocated, it must be an assembly-time constant")); | |
3013 | return 0; | |
3014 | } | |
3015 | ||
3016 | relP = (arelent *) xmalloc (sizeof (arelent)); | |
3017 | assert (relP != 0); | |
3018 | relP->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
3019 | *relP->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); | |
3020 | relP->address = fixP->fx_frag->fr_address + fixP->fx_where; | |
3021 | ||
3022 | if (fixP->fx_pcrel) | |
a161fe53 | 3023 | relP->addend = 0; |
3bcbcc3d | 3024 | else |
3bcbcc3d HPN |
3025 | relP->addend = fixP->fx_offset; |
3026 | ||
3027 | /* This is the standard place for KLUDGEs to work around bugs in | |
3028 | bfd_install_relocation (first such note in the documentation | |
3029 | appears with binutils-2.8). | |
3030 | ||
3031 | That function bfd_install_relocation does the wrong thing with | |
3032 | putting stuff into the addend of a reloc (it should stay out) for a | |
3033 | weak symbol. The really bad thing is that it adds the | |
3034 | "segment-relative offset" of the symbol into the reloc. In this | |
3035 | case, the reloc should instead be relative to the symbol with no | |
3036 | other offset than the assembly code shows; and since the symbol is | |
3037 | weak, any local definition should be ignored until link time (or | |
3038 | thereafter). | |
3039 | To wit: weaksym+42 should be weaksym+42 in the reloc, | |
3040 | not weaksym+(offset_from_segment_of_local_weaksym_definition) | |
3041 | ||
3042 | To "work around" this, we subtract the segment-relative offset of | |
3043 | "known" weak symbols. This evens out the extra offset. | |
3044 | ||
3045 | That happens for a.out but not for ELF, since for ELF, | |
3046 | bfd_install_relocation uses the "special function" field of the | |
3047 | howto, and does not execute the code that needs to be undone. */ | |
3048 | ||
3049 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour | |
3050 | && fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy) | |
3051 | && ! bfd_is_und_section (S_GET_SEGMENT (fixP->fx_addsy))) | |
47926f60 KH |
3052 | { |
3053 | relP->addend -= S_GET_VALUE (fixP->fx_addsy); | |
3054 | } | |
3bcbcc3d HPN |
3055 | |
3056 | relP->howto = bfd_reloc_type_lookup (stdoutput, code); | |
3057 | if (! relP->howto) | |
3058 | { | |
3059 | const char *name; | |
3060 | ||
3061 | name = S_GET_NAME (fixP->fx_addsy); | |
3062 | if (name == NULL) | |
3063 | name = _("<unknown>"); | |
3064 | as_fatal (_("Cannot generate relocation type for symbol %s, code %s"), | |
3065 | name, bfd_get_reloc_code_name (code)); | |
3066 | } | |
3067 | ||
3068 | return relP; | |
3069 | } | |
3070 | ||
3bcbcc3d | 3071 | /* Machine-dependent usage-output. */ |
47926f60 | 3072 | |
3bcbcc3d HPN |
3073 | void |
3074 | md_show_usage (stream) | |
3075 | FILE *stream; | |
3076 | { | |
08caf3f8 | 3077 | /* The messages are formatted to line up with the generic options. */ |
7b15d668 HPN |
3078 | fprintf (stream, _("CRIS-specific options:\n")); |
3079 | fprintf (stream, "%s", | |
3080 | _(" -h, -H Don't execute, print this help text. Deprecated.\n")); | |
3081 | fprintf (stream, "%s", | |
3082 | _(" -N Warn when branches are expanded to jumps.\n")); | |
3083 | fprintf (stream, "%s", | |
3084 | _(" --underscore User symbols are normally prepended with underscore.\n")); | |
3085 | fprintf (stream, "%s", | |
3086 | _(" Registers will not need any prefix.\n")); | |
3087 | fprintf (stream, "%s", | |
3088 | _(" --no-underscore User symbols do not have any prefix.\n")); | |
3089 | fprintf (stream, "%s", | |
3090 | _(" Registers will require a `$'-prefix.\n")); | |
08caf3f8 HPN |
3091 | fprintf (stream, "%s", |
3092 | _(" --pic Enable generation of position-independent code.\n")); | |
3bcbcc3d HPN |
3093 | } |
3094 | ||
3bcbcc3d | 3095 | /* Apply a fixS (fixup of an instruction or data that we didn't have |
47926f60 | 3096 | enough info to complete immediately) to the data in a frag. */ |
3bcbcc3d | 3097 | |
94f592af | 3098 | void |
08caf3f8 | 3099 | md_apply_fix3 (fixP, valP, seg) |
3bcbcc3d HPN |
3100 | fixS *fixP; |
3101 | valueT *valP; | |
08caf3f8 | 3102 | segT seg; |
3bcbcc3d | 3103 | { |
451a1fc5 HPN |
3104 | /* This assignment truncates upper bits if valueT is 64 bits (as with |
3105 | --enable-64-bit-bfd), which is fine here, though we cast to avoid | |
920e4177 | 3106 | any compiler warnings. */ |
451a1fc5 | 3107 | long val = (long) *valP; |
3bcbcc3d HPN |
3108 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; |
3109 | ||
3110 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
3111 | fixP->fx_done = 1; | |
3112 | ||
3113 | if (fixP->fx_bit_fixP || fixP->fx_im_disp != 0) | |
3114 | { | |
3115 | as_bad_where (fixP->fx_file, fixP->fx_line, _("Invalid relocation")); | |
3116 | fixP->fx_done = 1; | |
3117 | } | |
3118 | else | |
47926f60 | 3119 | { |
a161fe53 | 3120 | /* We can't actually support subtracting a symbol. */ |
47926f60 | 3121 | if (fixP->fx_subsy != (symbolS *) NULL) |
a161fe53 AM |
3122 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3123 | _("expression too complex")); | |
47926f60 | 3124 | |
08caf3f8 | 3125 | cris_number_to_imm (buf, val, fixP->fx_size, fixP, seg); |
47926f60 | 3126 | } |
3bcbcc3d HPN |
3127 | } |
3128 | ||
3bcbcc3d HPN |
3129 | /* All relocations are relative to the location just after the fixup; |
3130 | the address of the fixup plus its size. */ | |
3131 | ||
3132 | long | |
3133 | md_pcrel_from (fixP) | |
3134 | fixS *fixP; | |
3135 | { | |
3136 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
3137 | ||
3138 | /* FIXME: We get here only at the end of assembly, when X in ".-X" is | |
08caf3f8 HPN |
3139 | still unknown. Since we don't have pc-relative relocations in a.out, |
3140 | this is invalid. What to do if anything for a.out, is to add | |
3bcbcc3d | 3141 | pc-relative relocations everywhere including the elinux program |
08caf3f8 HPN |
3142 | loader. For ELF, allow straight-forward PC-relative relocations, |
3143 | which are always relative to the location after the relocation. */ | |
3144 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3145 | || (fixP->fx_r_type != BFD_RELOC_8_PCREL | |
3146 | && fixP->fx_r_type != BFD_RELOC_16_PCREL | |
3147 | && fixP->fx_r_type != BFD_RELOC_32_PCREL)) | |
3148 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3149 | _("Invalid pc-relative relocation")); | |
3bcbcc3d HPN |
3150 | return fixP->fx_size + addr; |
3151 | } | |
3152 | ||
47926f60 | 3153 | /* We have no need to give defaults for symbol-values. */ |
3bcbcc3d HPN |
3154 | symbolS * |
3155 | md_undefined_symbol (name) | |
3156 | char *name ATTRIBUTE_UNUSED; | |
3157 | { | |
3158 | return 0; | |
3159 | } | |
3160 | ||
a161fe53 AM |
3161 | /* If this function returns non-zero, it prevents the relocation |
3162 | against symbol(s) in the FIXP from being replaced with relocations | |
3163 | against section symbols, and guarantees that a relocation will be | |
3164 | emitted even when the value can be resolved locally. */ | |
3bcbcc3d HPN |
3165 | int |
3166 | md_cris_force_relocation (fixp) | |
3167 | struct fix *fixp; | |
3168 | { | |
08caf3f8 HPN |
3169 | switch (fixp->fx_r_type) |
3170 | { | |
08caf3f8 HPN |
3171 | case BFD_RELOC_CRIS_16_GOT: |
3172 | case BFD_RELOC_CRIS_32_GOT: | |
3173 | case BFD_RELOC_CRIS_16_GOTPLT: | |
3174 | case BFD_RELOC_CRIS_32_GOTPLT: | |
3175 | case BFD_RELOC_CRIS_32_GOTREL: | |
3176 | case BFD_RELOC_CRIS_32_PLT_GOTREL: | |
3177 | case BFD_RELOC_CRIS_32_PLT_PCREL: | |
3178 | return 1; | |
3179 | default: | |
3180 | ; | |
3181 | } | |
3182 | ||
ae6063d4 | 3183 | return generic_force_reloc (fixp); |
3bcbcc3d HPN |
3184 | } |
3185 | ||
3186 | /* Check and emit error if broken-word handling has failed to fix up a | |
3187 | case-table. This is called from write.c, after doing everything it | |
3188 | knows about how to handle broken words. */ | |
3189 | ||
3190 | void | |
3191 | tc_cris_check_adjusted_broken_word (new_offset, brokwP) | |
3192 | offsetT new_offset; | |
3193 | struct broken_word *brokwP; | |
3194 | { | |
3195 | if (new_offset > 32767 || new_offset < -32768) | |
47926f60 | 3196 | /* We really want a genuine error, not a warning, so make it one. */ |
3bcbcc3d HPN |
3197 | as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line, |
3198 | _("Adjusted signed .word (%ld) overflows: `switch'-statement too large."), | |
3199 | (long) new_offset); | |
3200 | } | |
3201 | ||
7b15d668 HPN |
3202 | /* Make a leading REGISTER_PREFIX_CHAR mandatory for all registers. */ |
3203 | ||
3204 | static void cris_force_reg_prefix () | |
3205 | { | |
b34976b6 | 3206 | demand_register_prefix = TRUE; |
7b15d668 HPN |
3207 | } |
3208 | ||
3209 | /* Do not demand a leading REGISTER_PREFIX_CHAR for all registers. */ | |
3210 | ||
3211 | static void cris_relax_reg_prefix () | |
3212 | { | |
b34976b6 | 3213 | demand_register_prefix = FALSE; |
7b15d668 HPN |
3214 | } |
3215 | ||
3216 | /* Adjust for having a leading '_' on all user symbols. */ | |
3217 | ||
3218 | static void cris_sym_leading_underscore () | |
3219 | { | |
3220 | /* We can't really do anything more than assert that what the program | |
3221 | thinks symbol starts with agrees with the command-line options, since | |
3222 | the bfd is already created. */ | |
3223 | ||
b34976b6 | 3224 | if (!symbols_have_leading_underscore) |
ed67db7a | 3225 | as_bad (_(".syntax %s requires command-line option `--underscore'"), |
7b15d668 HPN |
3226 | SYNTAX_USER_SYM_LEADING_UNDERSCORE); |
3227 | } | |
3228 | ||
3229 | /* Adjust for not having any particular prefix on user symbols. */ | |
3230 | ||
3231 | static void cris_sym_no_leading_underscore () | |
3232 | { | |
b34976b6 | 3233 | if (symbols_have_leading_underscore) |
ed67db7a | 3234 | as_bad (_(".syntax %s requires command-line option `--no-underscore'"), |
7b15d668 HPN |
3235 | SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE); |
3236 | } | |
3237 | ||
3238 | /* Handle the .syntax pseudo, which takes an argument that decides what | |
3239 | syntax the assembly code has. */ | |
3240 | ||
3241 | static void | |
3242 | s_syntax (ignore) | |
3243 | int ignore ATTRIBUTE_UNUSED; | |
3244 | { | |
3245 | static const struct syntaxes | |
3246 | { | |
3247 | const char *operand; | |
3248 | void (*fn) PARAMS ((void)); | |
4a1805b1 | 3249 | } syntax_table[] = |
7b15d668 HPN |
3250 | {{SYNTAX_ENFORCE_REG_PREFIX, cris_force_reg_prefix}, |
3251 | {SYNTAX_RELAX_REG_PREFIX, cris_relax_reg_prefix}, | |
3252 | {SYNTAX_USER_SYM_LEADING_UNDERSCORE, cris_sym_leading_underscore}, | |
3253 | {SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE, cris_sym_no_leading_underscore}}; | |
3254 | ||
3255 | const struct syntaxes *sp; | |
3256 | ||
3257 | for (sp = syntax_table; | |
3258 | sp < syntax_table + sizeof (syntax_table) / sizeof (syntax_table[0]); | |
3259 | sp++) | |
3260 | { | |
3261 | if (strncmp (input_line_pointer, sp->operand, | |
3262 | strlen (sp->operand)) == 0) | |
3263 | { | |
bc805888 | 3264 | (sp->fn) (); |
7b15d668 HPN |
3265 | |
3266 | input_line_pointer += strlen (sp->operand); | |
3267 | demand_empty_rest_of_line (); | |
3268 | return; | |
3269 | } | |
3270 | } | |
3271 | ||
3272 | as_bad (_("Unknown .syntax operand")); | |
3273 | } | |
3274 | ||
fcdc20a4 HPN |
3275 | /* Wrapper for dwarf2_directive_file to emit error if this is seen when |
3276 | not emitting ELF. */ | |
3277 | ||
3278 | static void | |
3279 | s_cris_file (dummy) | |
3280 | int dummy; | |
3281 | { | |
3282 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
ed67db7a | 3283 | as_bad (_("Pseudodirective .file is only valid when generating ELF")); |
fcdc20a4 HPN |
3284 | else |
3285 | dwarf2_directive_file (dummy); | |
3286 | } | |
3287 | ||
3288 | /* Wrapper for dwarf2_directive_loc to emit error if this is seen when not | |
3289 | emitting ELF. */ | |
3290 | ||
3291 | static void | |
3292 | s_cris_loc (dummy) | |
3293 | int dummy; | |
3294 | { | |
3295 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
ed67db7a | 3296 | as_bad (_("Pseudodirective .loc is only valid when generating ELF")); |
fcdc20a4 HPN |
3297 | else |
3298 | dwarf2_directive_loc (dummy); | |
3299 | } | |
3300 | ||
3bcbcc3d HPN |
3301 | /* |
3302 | * Local variables: | |
3303 | * eval: (c-set-style "gnu") | |
3304 | * indent-tabs-mode: t | |
3305 | * End: | |
3306 | */ |