Commit | Line | Data |
---|---|---|
3bcbcc3d HPN |
1 | /* tc-cris.c -- Assembler code for the CRIS CPU core. |
2 | Copyright (C) 2000 Free Software Foundation, Inc. | |
3 | ||
4 | Contributed by Axis Communications AB, Lund, Sweden. | |
5 | Originally written for GAS 1.38.1 by Mikael Asker. | |
6 | Updated, BFDized and GNUified by Hans-Peter Nilsson. | |
7 | ||
8 | This file is part of GAS, the GNU Assembler. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the | |
22 | Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
47926f60 | 23 | MA 02111-1307, USA. */ |
3bcbcc3d HPN |
24 | |
25 | #include <stdio.h> | |
26 | #include <ctype.h> | |
27 | #include "as.h" | |
28 | #include "subsegs.h" | |
29 | #include "opcode/cris.h" | |
fcdc20a4 | 30 | #include "dwarf2dbg.h" |
3bcbcc3d HPN |
31 | |
32 | /* Conventions used here: | |
33 | Generally speaking, pointers to binutils types such as "fragS" and | |
34 | "expressionS" get parameter and variable names ending in "P", such as | |
35 | "fragP", to harmonize with the rest of the binutils code. Other | |
36 | pointers get a "p" suffix, such as "bufp". Any function or type-name | |
37 | that could clash with a current or future binutils or GAS function get | |
38 | a "cris_" prefix. */ | |
39 | ||
7b15d668 HPN |
40 | #define SYNTAX_RELAX_REG_PREFIX "no_register_prefix" |
41 | #define SYNTAX_ENFORCE_REG_PREFIX "register_prefix" | |
42 | #define SYNTAX_USER_SYM_LEADING_UNDERSCORE "leading_underscore" | |
43 | #define SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE "no_leading_underscore" | |
44 | #define REGISTER_PREFIX_CHAR '$' | |
45 | ||
3bcbcc3d HPN |
46 | /* This might be CRIS_INSN_NONE if we're assembling a prefix-insn only. |
47 | Note that some prefix-insns might be assembled as CRIS_INSN_NORMAL. */ | |
48 | enum cris_insn_kind | |
49 | { | |
50 | CRIS_INSN_NORMAL, CRIS_INSN_NONE, CRIS_INSN_BRANCH | |
51 | }; | |
52 | ||
53 | /* An instruction will have one of these prefixes. | |
54 | Although the same bit-pattern, we handle BDAP with an immediate | |
55 | expression (eventually quick or [pc+]) different from when we only have | |
56 | register expressions. */ | |
57 | enum prefix_kind | |
58 | { | |
59 | PREFIX_NONE, PREFIX_BDAP_IMM, PREFIX_BDAP, PREFIX_BIAP, PREFIX_DIP, | |
60 | PREFIX_PUSH | |
61 | }; | |
62 | ||
63 | /* The prefix for an instruction. */ | |
64 | struct cris_prefix | |
65 | { | |
47926f60 KH |
66 | enum prefix_kind kind; |
67 | int base_reg_number; | |
68 | unsigned int opcode; | |
3bcbcc3d HPN |
69 | |
70 | /* There might be an expression to be evaluated, like I in [rN+I]. */ | |
47926f60 | 71 | expressionS expr; |
3bcbcc3d HPN |
72 | |
73 | /* If there's an expression, we might need a relocation. Here's the | |
74 | type of what relocation to start relaxaton with. | |
75 | The relocation is assumed to start immediately after the prefix insn, | |
76 | so we don't provide an offset. */ | |
77 | enum bfd_reloc_code_real reloc; | |
78 | }; | |
79 | ||
47926f60 | 80 | /* The description of the instruction being assembled. */ |
3bcbcc3d HPN |
81 | struct cris_instruction |
82 | { | |
83 | /* If CRIS_INSN_NONE, then this insn is of zero length. */ | |
47926f60 | 84 | enum cris_insn_kind insn_type; |
3bcbcc3d HPN |
85 | |
86 | /* If a special register was mentioned, this is its description, else | |
47926f60 | 87 | it is NULL. */ |
3bcbcc3d HPN |
88 | const struct cris_spec_reg *spec_reg; |
89 | ||
47926f60 | 90 | unsigned int opcode; |
3bcbcc3d HPN |
91 | |
92 | /* An insn may have at most one expression; theoretically there could be | |
47926f60 KH |
93 | another in its prefix (but I don't see how that could happen). */ |
94 | expressionS expr; | |
3bcbcc3d HPN |
95 | |
96 | /* The expression might need a relocation. Here's one to start | |
97 | relaxation with. */ | |
47926f60 | 98 | enum bfd_reloc_code_real reloc; |
3bcbcc3d HPN |
99 | |
100 | /* The size in bytes of an immediate expression, or zero in | |
101 | nonapplicable. */ | |
47926f60 | 102 | int imm_oprnd_size; |
3bcbcc3d HPN |
103 | }; |
104 | ||
105 | static void cris_process_instruction PARAMS ((char *, | |
106 | struct cris_instruction *, | |
107 | struct cris_prefix *)); | |
108 | static int get_bwd_size_modifier PARAMS ((char **, int *)); | |
109 | static int get_bw_size_modifier PARAMS ((char **, int *)); | |
110 | static int get_gen_reg PARAMS ((char **, int *)); | |
111 | static int get_spec_reg PARAMS ((char **, | |
112 | const struct cris_spec_reg **)); | |
113 | static int get_autoinc_prefix_or_indir_op PARAMS ((char **, | |
114 | struct cris_prefix *, | |
115 | int *, int *, int *, | |
116 | expressionS *)); | |
117 | static int get_3op_or_dip_prefix_op PARAMS ((char **, | |
118 | struct cris_prefix *)); | |
119 | static int cris_get_expression PARAMS ((char **, expressionS *)); | |
120 | static int get_flags PARAMS ((char **, int *)); | |
121 | static void gen_bdap PARAMS ((int, expressionS *)); | |
122 | static int branch_disp PARAMS ((int)); | |
123 | static void gen_cond_branch_32 PARAMS ((char *, char *, fragS *, | |
124 | symbolS *, symbolS *, long int)); | |
125 | static void cris_number_to_imm PARAMS ((char *, long, int, fixS *)); | |
126 | static void cris_create_short_jump PARAMS ((char *, addressT, addressT, | |
127 | fragS *, symbolS *)); | |
7b15d668 | 128 | static void s_syntax PARAMS ((int)); |
fcdc20a4 HPN |
129 | static void s_cris_file PARAMS ((int)); |
130 | static void s_cris_loc PARAMS ((int)); | |
7b15d668 HPN |
131 | |
132 | /* All the .syntax functions. */ | |
133 | static void cris_force_reg_prefix PARAMS ((void)); | |
134 | static void cris_relax_reg_prefix PARAMS ((void)); | |
135 | static void cris_sym_leading_underscore PARAMS ((void)); | |
136 | static void cris_sym_no_leading_underscore PARAMS ((void)); | |
137 | ||
3bcbcc3d HPN |
138 | /* Handle to the opcode hash table. */ |
139 | static struct hash_control *op_hash = NULL; | |
140 | ||
7b15d668 HPN |
141 | /* Whether we demand that registers have a `$' prefix. Default here. */ |
142 | static boolean demand_register_prefix = false; | |
143 | ||
144 | /* Whether global user symbols have a leading underscore. Default here. */ | |
145 | static boolean symbols_have_leading_underscore = true; | |
146 | ||
3bcbcc3d HPN |
147 | const pseudo_typeS md_pseudo_table[] = |
148 | { | |
149 | {"dword", cons, 4}, | |
7b15d668 | 150 | {"syntax", s_syntax, 0}, |
fcdc20a4 HPN |
151 | {"file", s_cris_file, 0}, |
152 | {"loc", s_cris_loc, 0}, | |
3bcbcc3d HPN |
153 | {NULL, 0, 0} |
154 | }; | |
155 | ||
156 | static int warn_for_branch_expansion = 0; | |
157 | ||
158 | const char cris_comment_chars[] = ";"; | |
159 | ||
160 | /* This array holds the chars that only start a comment at the beginning of | |
161 | a line. If the line seems to have the form '# 123 filename' | |
47926f60 | 162 | .line and .file directives will appear in the pre-processed output. */ |
3bcbcc3d HPN |
163 | /* Note that input_file.c hand-checks for '#' at the beginning of the |
164 | first line of the input file. This is because the compiler outputs | |
47926f60 KH |
165 | #NO_APP at the beginning of its output. */ |
166 | /* Also note that slash-star will always start a comment. */ | |
3bcbcc3d HPN |
167 | const char line_comment_chars[] = "#"; |
168 | const char line_separator_chars[] = "@"; | |
169 | ||
170 | /* Now all floating point support is shut off. See md_atof. */ | |
171 | const char EXP_CHARS[] = ""; | |
172 | const char FLT_CHARS[] = ""; | |
173 | ||
3bcbcc3d HPN |
174 | /* For CRIS, we encode the relax_substateTs (in e.g. fr_substate) as: |
175 | 2 1 0 | |
176 | ---/ /--+-----------------+-----------------+-----------------+ | |
177 | | what state ? | how long ? | | |
178 | ---/ /--+-----------------+-----------------+-----------------+ | |
179 | ||
180 | The "how long" bits are 00 = byte, 01 = word, 10 = dword (long). | |
181 | This is a Un*x convention. | |
182 | Not all lengths are legit for a given value of (what state). | |
183 | ||
184 | Groups for CRIS address relaxing: | |
185 | ||
186 | 1. Bcc | |
187 | length: byte, word, 10-byte expansion | |
188 | ||
189 | 2. BDAP | |
47926f60 | 190 | length: byte, word, dword */ |
3bcbcc3d HPN |
191 | |
192 | #define STATE_CONDITIONAL_BRANCH (1) | |
193 | #define STATE_BASE_PLUS_DISP_PREFIX (2) | |
194 | ||
195 | #define STATE_LENGTH_MASK (3) | |
196 | #define STATE_BYTE (0) | |
197 | #define STATE_WORD (1) | |
198 | #define STATE_DWORD (2) | |
199 | /* Symbol undefined. */ | |
200 | #define STATE_UNDF (3) | |
201 | #define STATE_MAX_LENGTH (3) | |
202 | ||
3bcbcc3d HPN |
203 | /* These displacements are relative to the adress following the opcode |
204 | word of the instruction. The first letter is Byte, Word. The 2nd | |
205 | letter is Forward, Backward. */ | |
206 | ||
207 | #define BRANCH_BF ( 254) | |
208 | #define BRANCH_BB (-256) | |
47926f60 KH |
209 | #define BRANCH_WF (2 + 32767) |
210 | #define BRANCH_WB (2 + -32768) | |
3bcbcc3d HPN |
211 | |
212 | #define BDAP_BF ( 127) | |
213 | #define BDAP_BB (-128) | |
214 | #define BDAP_WF ( 32767) | |
215 | #define BDAP_WB (-32768) | |
216 | ||
217 | #define ENCODE_RELAX(what, length) (((what) << 2) + (length)) | |
218 | ||
219 | const relax_typeS md_cris_relax_table[] = | |
220 | { | |
221 | /* Error sentinel (0, 0). */ | |
222 | {1, 1, 0, 0}, | |
223 | ||
224 | /* Unused (0, 1). */ | |
225 | {1, 1, 0, 0}, | |
226 | ||
227 | /* Unused (0, 2). */ | |
228 | {1, 1, 0, 0}, | |
229 | ||
230 | /* Unused (0, 3). */ | |
231 | {1, 1, 0, 0}, | |
232 | ||
233 | /* Bcc o (1, 0). */ | |
234 | {BRANCH_BF, BRANCH_BB, 0, ENCODE_RELAX (1, 1)}, | |
235 | ||
47926f60 | 236 | /* Bcc [PC+] (1, 1). */ |
3bcbcc3d HPN |
237 | {BRANCH_WF, BRANCH_WB, 2, ENCODE_RELAX (1, 2)}, |
238 | ||
239 | /* BEXT/BWF, BA, JUMP (external), JUMP (always), Bnot_cc, JUMP (default) | |
240 | (1, 2). */ | |
241 | {0, 0, 10, 0}, | |
242 | ||
243 | /* Unused (1, 3). */ | |
244 | {1, 1, 0, 0}, | |
245 | ||
246 | /* BDAP o (2, 0). */ | |
247 | {BDAP_BF, BDAP_BB, 0, ENCODE_RELAX (2, 1)}, | |
248 | ||
249 | /* BDAP.[bw] [PC+] (2, 1). */ | |
250 | {BDAP_WF, BDAP_WB, 2, ENCODE_RELAX (2, 2)}, | |
251 | ||
252 | /* BDAP.d [PC+] (2, 2). */ | |
253 | {0, 0, 4, 0} | |
254 | }; | |
255 | ||
256 | #undef BRANCH_BF | |
257 | #undef BRANCH_BB | |
258 | #undef BRANCH_WF | |
259 | #undef BRANCH_WB | |
260 | #undef BDAP_BF | |
261 | #undef BDAP_BB | |
262 | #undef BDAP_WF | |
263 | #undef BDAP_WB | |
264 | ||
3bcbcc3d HPN |
265 | /* Target-specific multicharacter options, not const-declared at usage |
266 | in 2.9.1 and CVS of 2000-02-16. */ | |
267 | struct option md_longopts[] = | |
268 | { | |
7b15d668 HPN |
269 | #define OPTION_NO_US (OPTION_MD_BASE + 0) |
270 | {"no-underscore", no_argument, NULL, OPTION_NO_US}, | |
271 | #define OPTION_US (OPTION_MD_BASE + 1) | |
272 | {"underscore", no_argument, NULL, OPTION_US}, | |
3bcbcc3d HPN |
273 | {NULL, no_argument, NULL, 0} |
274 | }; | |
275 | ||
276 | /* Not const-declared at usage in 2.9.1. */ | |
277 | size_t md_longopts_size = sizeof (md_longopts); | |
278 | const char *md_shortopts = "hHN"; | |
279 | ||
3bcbcc3d HPN |
280 | /* At first glance, this may seems wrong and should be 4 (ba + nop); but |
281 | since a short_jump must skip a *number* of long jumps, it must also be | |
282 | a long jump. Here, we hope to make it a "ba [16bit_offs]" and a "nop" | |
283 | for the delay slot and hope that the jump table at most needs | |
284 | 32767/4=8191 long-jumps. A branch is better than a jump, since it is | |
285 | relative; we will not have a reloc to fix up somewhere. | |
286 | ||
287 | Note that we can't add relocs, because relaxation uses these fixed | |
288 | numbers, and md_create_short_jump is called after relaxation. */ | |
289 | ||
290 | const int md_short_jump_size = 6; | |
291 | const int md_long_jump_size = 6; | |
292 | ||
7b15d668 HPN |
293 | /* Report output format. Small changes in output format (like elf |
294 | variants below) can happen until all options are parsed. */ | |
47926f60 | 295 | |
3bcbcc3d HPN |
296 | const char * |
297 | cris_target_format () | |
298 | { | |
299 | switch (OUTPUT_FLAVOR) | |
300 | { | |
301 | case bfd_target_aout_flavour: | |
302 | return "a.out-cris"; | |
303 | ||
304 | case bfd_target_elf_flavour: | |
7b15d668 HPN |
305 | if (symbols_have_leading_underscore) |
306 | return "elf32-us-cris"; | |
3bcbcc3d HPN |
307 | return "elf32-cris"; |
308 | ||
309 | default: | |
310 | abort (); | |
311 | return NULL; | |
312 | } | |
313 | } | |
314 | ||
315 | /* Prepare machine-dependent frags for relaxation. | |
316 | ||
317 | Called just before relaxation starts. Any symbol that is now undefined | |
318 | will not become defined. | |
319 | ||
320 | Return the correct fr_subtype in the frag. | |
321 | ||
322 | Return the initial "guess for fr_var" to caller. The guess for fr_var | |
323 | is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix | |
324 | or fr_var contributes to our returned value. | |
325 | ||
326 | Although it may not be explicit in the frag, pretend | |
47926f60 | 327 | fr_var starts with a value. */ |
3bcbcc3d HPN |
328 | |
329 | int | |
330 | md_estimate_size_before_relax (fragP, segment_type) | |
331 | fragS *fragP; | |
332 | /* The segment is either N_DATA or N_TEXT. */ | |
47926f60 | 333 | segT segment_type; |
3bcbcc3d | 334 | { |
47926f60 | 335 | int old_fr_fix; |
3bcbcc3d HPN |
336 | |
337 | old_fr_fix = fragP->fr_fix; | |
338 | ||
339 | switch (fragP->fr_subtype) | |
340 | { | |
341 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_UNDF): | |
342 | if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type) | |
343 | { | |
344 | /* The symbol lies in the same segment - a relaxable case. */ | |
345 | fragP->fr_subtype | |
346 | = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE); | |
347 | } | |
348 | else | |
349 | { | |
350 | /* Unknown or not the same segment, so not relaxable. */ | |
351 | char *writep; | |
352 | ||
353 | /* A small branch-always (2 bytes) to the "real" branch | |
354 | instruction, plus a delay-slot nop (2 bytes), plus a | |
355 | jump (2 plus 4 bytes). See gen_cond_branch_32. */ | |
356 | fragP->fr_fix += 2 + 2 + 2 + 4; | |
357 | writep = fragP->fr_literal + old_fr_fix; | |
358 | gen_cond_branch_32 (fragP->fr_opcode, writep, fragP, | |
47926f60 | 359 | fragP->fr_symbol, (symbolS *) NULL, |
3bcbcc3d HPN |
360 | fragP->fr_offset); |
361 | frag_wane (fragP); | |
362 | } | |
363 | break; | |
364 | ||
365 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE): | |
366 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD): | |
367 | /* We *might* give a better initial guess if we peek at offsets | |
368 | now, but the caller will relax correctly and without this, so | |
369 | don't bother. */ | |
370 | break; | |
371 | ||
372 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF): | |
373 | /* Note that we can not do anything sane with relaxing | |
374 | [rX + a_known_symbol_in_text], it will have to be a 32-bit | |
375 | value. | |
376 | ||
377 | We could play tricks with managing a constant pool and make | |
378 | a_known_symbol_in_text a "bdap [pc + offset]" pointing there, but | |
379 | that's pointless, it can only be longer and slower. | |
380 | ||
381 | Off-topic: If PIC becomes *really* important, and has to be done | |
382 | in the assembler and linker only (which would be weird or | |
383 | clueless), we can so something. Imagine: | |
384 | move.x [r + 32_bit_symbol],r | |
385 | move.x [32_bit_symbol],r | |
386 | move.x 32_bit_symbol,r | |
387 | can be shortened by a word (8-bit offset) if we are close to the | |
388 | symbol or keep its length (16-bit offset) or be a word longer | |
389 | (32-bit offset). Then change the 32_bit_symbol into a "bdap [pc | |
390 | + offset]", and put the offset to the 32_bit_symbol in "offset". | |
391 | Weird, to say the least, and we still have to add support for a | |
392 | PC-relative relocation in the loader (shared libraries). But | |
393 | it's an interesting thought. */ | |
394 | ||
395 | if (S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) | |
396 | { | |
397 | /* Go for dword if not absolute or same segment. */ | |
398 | fragP->fr_subtype | |
399 | = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD); | |
400 | fragP->fr_var += 4; | |
401 | } | |
402 | else | |
403 | { | |
404 | /* Absolute expression. */ | |
405 | long int value; | |
406 | value = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
407 | ||
408 | if (value >= -128 && value <= 127) | |
409 | { | |
410 | /* Byte displacement. */ | |
411 | (fragP->fr_opcode)[0] = value; | |
412 | } | |
413 | else | |
414 | { | |
415 | /* Word or dword displacement. */ | |
416 | int pow2_of_size = 1; | |
417 | char *writep; | |
418 | ||
419 | if (value < -32768 || value > 32767) | |
420 | { | |
421 | /* Outside word range, make it a dword. */ | |
422 | pow2_of_size = 2; | |
423 | } | |
424 | ||
425 | /* Modify the byte-offset BDAP into a word or dword offset | |
426 | BDAP. Or really, a BDAP rX,8bit into a | |
07e90ad5 | 427 | BDAP.[wd] rX,[PC+] followed by a word or dword. */ |
3bcbcc3d HPN |
428 | (fragP->fr_opcode)[0] = BDAP_PC_LOW + pow2_of_size * 16; |
429 | ||
430 | /* Keep the register number in the highest four bits. */ | |
431 | (fragP->fr_opcode)[1] &= 0xF0; | |
432 | (fragP->fr_opcode)[1] |= BDAP_INCR_HIGH; | |
433 | ||
47926f60 | 434 | /* It grew by two or four bytes. */ |
3bcbcc3d HPN |
435 | fragP->fr_fix += 1 << pow2_of_size; |
436 | writep = fragP->fr_literal + old_fr_fix; | |
437 | md_number_to_chars (writep, value, 1 << pow2_of_size); | |
438 | } | |
439 | frag_wane (fragP); | |
440 | } | |
441 | break; | |
442 | ||
443 | default: | |
444 | BAD_CASE (fragP->fr_subtype); | |
445 | } | |
446 | ||
447 | return fragP->fr_var + (fragP->fr_fix - old_fr_fix); | |
448 | } | |
449 | ||
3bcbcc3d HPN |
450 | /* Perform post-processing of machine-dependent frags after relaxation. |
451 | Called after relaxation is finished. | |
452 | In: Address of frag. | |
453 | fr_type == rs_machine_dependent. | |
454 | fr_subtype is what the address relaxed to. | |
455 | ||
456 | Out: Any fixS:s and constants are set up. | |
457 | ||
458 | The caller will turn the frag into a ".space 0". */ | |
459 | ||
460 | void | |
461 | md_convert_frag (abfd, sec, fragP) | |
462 | bfd *abfd ATTRIBUTE_UNUSED; | |
463 | segT sec ATTRIBUTE_UNUSED; | |
464 | fragS *fragP; | |
465 | { | |
47926f60 | 466 | /* Pointer to first byte in variable-sized part of the frag. */ |
3bcbcc3d HPN |
467 | char *var_partp; |
468 | ||
469 | /* Pointer to first opcode byte in frag. */ | |
470 | char *opcodep; | |
471 | ||
472 | /* Used to check integrity of the relaxation. | |
473 | One of 2 = long, 1 = word, or 0 = byte. */ | |
474 | int length_code; | |
475 | ||
476 | /* Size in bytes of variable-sized part of frag. */ | |
477 | int var_part_size = 0; | |
478 | ||
479 | /* This is part of *fragP. It contains all information about addresses | |
480 | and offsets to varying parts. */ | |
481 | symbolS *symbolP; | |
482 | unsigned long var_part_offset; | |
483 | ||
484 | /* Where, in file space, is _var of *fragP? */ | |
485 | unsigned long address_of_var_part = 0; | |
486 | ||
487 | /* Where, in file space, does addr point? */ | |
488 | unsigned long target_address; | |
489 | ||
490 | know (fragP->fr_type == rs_machine_dependent); | |
491 | ||
492 | length_code = fragP->fr_subtype & STATE_LENGTH_MASK; | |
493 | know (length_code >= 0 && length_code < STATE_MAX_LENGTH); | |
494 | ||
495 | var_part_offset = fragP->fr_fix; | |
496 | var_partp = fragP->fr_literal + var_part_offset; | |
497 | opcodep = fragP->fr_opcode; | |
498 | ||
499 | symbolP = fragP->fr_symbol; | |
500 | target_address | |
501 | = (symbolP | |
502 | ? S_GET_VALUE (symbolP) + symbol_get_frag(fragP->fr_symbol)->fr_address | |
503 | : 0 ) + fragP->fr_offset; | |
504 | address_of_var_part = fragP->fr_address + var_part_offset; | |
505 | ||
506 | switch (fragP->fr_subtype) | |
47926f60 KH |
507 | { |
508 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE): | |
509 | opcodep[0] = branch_disp ((target_address - address_of_var_part)); | |
510 | var_part_size = 0; | |
511 | break; | |
3bcbcc3d | 512 | |
47926f60 KH |
513 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD): |
514 | /* We had a quick immediate branch, now turn it into a word one i.e. a | |
515 | PC autoincrement. */ | |
516 | opcodep[0] = BRANCH_PC_LOW; | |
517 | opcodep[1] &= 0xF0; | |
518 | opcodep[1] |= BRANCH_INCR_HIGH; | |
519 | md_number_to_chars (var_partp, | |
520 | (long) (target_address - (address_of_var_part + 2)), | |
521 | 2); | |
522 | var_part_size = 2; | |
523 | break; | |
524 | ||
525 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_DWORD): | |
526 | gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP, | |
527 | fragP->fr_symbol, (symbolS *) NULL, | |
528 | fragP->fr_offset); | |
529 | /* Ten bytes added: a branch, nop and a jump. */ | |
530 | var_part_size = 2 + 2 + 4 + 2; | |
531 | break; | |
3bcbcc3d | 532 | |
47926f60 KH |
533 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): |
534 | var_partp[0] = target_address - (address_of_var_part + 1); | |
535 | var_part_size = 0; | |
536 | break; | |
537 | ||
538 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): | |
539 | /* We had a BDAP 8-bit "quick immediate", now turn it into a 16-bit | |
540 | one that uses PC autoincrement. */ | |
541 | opcodep[0] = BDAP_PC_LOW + (1 << 4); | |
542 | opcodep[1] &= 0xF0; | |
543 | opcodep[1] |= BDAP_INCR_HIGH; | |
544 | md_number_to_chars (var_partp, (long) (target_address), 2); | |
545 | var_part_size = 2; | |
546 | break; | |
547 | ||
548 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): | |
549 | /* We had a BDAP 16-bit "word", change the offset to a dword. */ | |
550 | opcodep[0] = BDAP_PC_LOW + (2 << 4); | |
551 | opcodep[1] &= 0xF0; | |
552 | opcodep[1] |= BDAP_INCR_HIGH; | |
553 | if (fragP->fr_symbol == NULL) | |
554 | md_number_to_chars (var_partp, fragP->fr_offset, 4); | |
555 | else | |
556 | fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol, | |
557 | fragP->fr_offset, 0, BFD_RELOC_32); | |
558 | var_part_size = 4; | |
559 | break; | |
560 | ||
561 | default: | |
562 | BAD_CASE (fragP->fr_subtype); | |
563 | break; | |
564 | } | |
565 | ||
566 | fragP->fr_fix += var_part_size; | |
3bcbcc3d HPN |
567 | } |
568 | ||
569 | /* Generate a short jump around a secondary jump table. | |
570 | Used by md_create_long_jump. | |
571 | ||
572 | This used to be md_create_short_jump, but is now called from | |
573 | md_create_long_jump instead, when sufficient. | |
574 | since the sizes of the jumps are the same. It used to be brittle, | |
47926f60 | 575 | making possibilities for creating bad code. */ |
3bcbcc3d HPN |
576 | |
577 | static void | |
578 | cris_create_short_jump (storep, from_addr, to_addr, fragP, to_symbol) | |
579 | char *storep; | |
580 | addressT from_addr; | |
581 | addressT to_addr; | |
582 | fragS *fragP ATTRIBUTE_UNUSED; | |
583 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
584 | { | |
585 | long int distance; | |
586 | ||
587 | distance = to_addr - from_addr; | |
588 | ||
589 | if (-254 <= distance && distance <= 256) | |
590 | { | |
591 | /* Create a "short" short jump: "BA distance - 2". */ | |
47926f60 | 592 | storep[0] = branch_disp (distance - 2); |
3bcbcc3d HPN |
593 | storep[1] = BA_QUICK_HIGH; |
594 | ||
595 | /* A nop for the delay slot. */ | |
47926f60 | 596 | md_number_to_chars (storep + 2, NOP_OPCODE, 2); |
3bcbcc3d HPN |
597 | |
598 | /* The extra word should be filled with something sane too. Make it | |
599 | a nop to keep disassembly sane. */ | |
47926f60 | 600 | md_number_to_chars (storep + 4, NOP_OPCODE, 2); |
3bcbcc3d HPN |
601 | } |
602 | else | |
603 | { | |
604 | /* Make it a "long" short jump: "BA (PC+)". */ | |
605 | md_number_to_chars (storep, BA_PC_INCR_OPCODE, 2); | |
606 | ||
47926f60 | 607 | /* ".WORD distance - 4". */ |
3bcbcc3d HPN |
608 | md_number_to_chars (storep + 2, (long) (distance - 4), 2); |
609 | ||
610 | /* A nop for the delay slot. */ | |
47926f60 | 611 | md_number_to_chars (storep + 4, NOP_OPCODE, 2); |
3bcbcc3d HPN |
612 | } |
613 | } | |
614 | ||
3bcbcc3d HPN |
615 | /* Generate a long jump in a secondary jump table. |
616 | ||
617 | storep Where to store the jump instruction. | |
618 | from_addr Address of the jump instruction. | |
619 | to_addr Destination address of the jump. | |
620 | fragP Which frag the destination address operand | |
621 | lies in. | |
622 | to_symbol Destination symbol. */ | |
623 | ||
624 | void | |
625 | md_create_long_jump (storep, from_addr, to_addr, fragP, to_symbol) | |
626 | char *storep; | |
627 | addressT from_addr; | |
628 | addressT to_addr; | |
629 | fragS *fragP; | |
630 | symbolS *to_symbol; | |
631 | { | |
632 | long int distance; | |
633 | ||
634 | distance = to_addr - from_addr; | |
635 | ||
636 | if (-32763 <= distance && distance <= 32772) | |
637 | { | |
638 | /* Then make it a "short" long jump. */ | |
639 | cris_create_short_jump (storep, from_addr, to_addr, fragP, | |
640 | to_symbol); | |
641 | } | |
642 | else | |
643 | { | |
644 | /* We have a "long" long jump: "JUMP (PC+)". */ | |
645 | md_number_to_chars (storep, JUMP_PC_INCR_OPCODE, 2); | |
646 | ||
647 | /* Follow with a ".DWORD to_addr". */ | |
648 | fix_new (fragP, storep + 2 - fragP->fr_literal, 4, to_symbol, | |
649 | 0, 0, BFD_RELOC_32); | |
650 | } | |
651 | } | |
652 | ||
3bcbcc3d | 653 | /* Port-specific assembler initialization. */ |
47926f60 | 654 | |
3bcbcc3d HPN |
655 | void |
656 | md_begin () | |
657 | { | |
658 | const char *hashret = NULL; | |
659 | int i = 0; | |
660 | ||
47926f60 | 661 | /* Set up a hash table for the instructions. */ |
3bcbcc3d HPN |
662 | op_hash = hash_new (); |
663 | if (op_hash == NULL) | |
664 | as_fatal (_("Virtual memory exhausted")); | |
665 | ||
666 | while (cris_opcodes[i].name != NULL) | |
667 | { | |
668 | const char *name = cris_opcodes[i].name; | |
669 | hashret = hash_insert (op_hash, name, (PTR) &cris_opcodes[i]); | |
670 | ||
671 | if (hashret != NULL && *hashret != '\0') | |
672 | as_fatal (_("Can't hash `%s': %s\n"), cris_opcodes[i].name, | |
47926f60 | 673 | *hashret == 0 ? _("(unknown reason)") : hashret); |
3bcbcc3d HPN |
674 | do |
675 | { | |
676 | if (cris_opcodes[i].match & cris_opcodes[i].lose) | |
677 | as_fatal (_("Buggy opcode: `%s' \"%s\"\n"), cris_opcodes[i].name, | |
678 | cris_opcodes[i].args); | |
679 | ||
680 | ++i; | |
47926f60 KH |
681 | } |
682 | while (cris_opcodes[i].name != NULL | |
683 | && strcmp (cris_opcodes[i].name, name) == 0); | |
3bcbcc3d HPN |
684 | } |
685 | } | |
686 | ||
3bcbcc3d | 687 | /* Assemble a source line. */ |
47926f60 | 688 | |
3bcbcc3d HPN |
689 | void |
690 | md_assemble (str) | |
691 | char *str; | |
692 | { | |
693 | struct cris_instruction output_instruction; | |
694 | struct cris_prefix prefix; | |
695 | char *opcodep; | |
696 | char *p; | |
fcdc20a4 | 697 | int insn_size = 0; |
3bcbcc3d HPN |
698 | |
699 | know (str); | |
700 | ||
701 | /* Do the low-level grunt - assemble to bits and split up into a prefix | |
702 | and ordinary insn. */ | |
703 | cris_process_instruction (str, &output_instruction, &prefix); | |
704 | ||
705 | /* Handle any prefixes to the instruction. */ | |
706 | switch (prefix.kind) | |
707 | { | |
708 | case PREFIX_NONE: | |
709 | break; | |
710 | ||
711 | /* When the expression is unknown for a BDAP, it can need 0, 2 or 4 | |
712 | extra bytes, so we handle it separately. */ | |
713 | case PREFIX_BDAP_IMM: | |
714 | gen_bdap (prefix.base_reg_number, &prefix.expr); | |
715 | break; | |
716 | ||
717 | case PREFIX_BDAP: | |
718 | case PREFIX_BIAP: | |
719 | case PREFIX_DIP: | |
fcdc20a4 | 720 | insn_size += 2; |
3bcbcc3d HPN |
721 | opcodep = frag_more (2); |
722 | ||
723 | /* Output the prefix opcode. */ | |
724 | md_number_to_chars (opcodep, (long) prefix.opcode, 2); | |
725 | ||
726 | /* This only happens for DIP, but is ok for the others as they have | |
727 | no reloc. */ | |
728 | if (prefix.reloc != BFD_RELOC_NONE) | |
729 | { | |
47926f60 | 730 | /* Output an absolute mode address. */ |
fcdc20a4 | 731 | insn_size += 4; |
3bcbcc3d HPN |
732 | p = frag_more (4); |
733 | fix_new_exp (frag_now, (p - frag_now->fr_literal), 4, | |
734 | &prefix.expr, 0, prefix.reloc); | |
735 | } | |
736 | break; | |
737 | ||
738 | case PREFIX_PUSH: | |
fcdc20a4 | 739 | insn_size += 2; |
3bcbcc3d HPN |
740 | opcodep = frag_more (2); |
741 | ||
742 | /* Output the prefix opcode. Being a "push", we add the negative | |
743 | size of the register to "sp". */ | |
744 | if (output_instruction.spec_reg != NULL) | |
745 | { | |
47926f60 | 746 | /* Special register. */ |
3bcbcc3d HPN |
747 | opcodep[0] = -output_instruction.spec_reg->reg_size; |
748 | } | |
749 | else | |
750 | { | |
47926f60 | 751 | /* General register. */ |
3bcbcc3d HPN |
752 | opcodep[0] = -4; |
753 | } | |
754 | opcodep[1] = (REG_SP << 4) + (BDAP_QUICK_OPCODE >> 8); | |
755 | break; | |
756 | ||
757 | default: | |
758 | BAD_CASE (prefix.kind); | |
759 | } | |
760 | ||
761 | /* If we only had a prefix insn, we're done. */ | |
762 | if (output_instruction.insn_type == CRIS_INSN_NONE) | |
763 | return; | |
764 | ||
765 | /* Done with the prefix. Continue with the main instruction. */ | |
fcdc20a4 | 766 | insn_size += 2; |
3bcbcc3d HPN |
767 | opcodep = frag_more (2); |
768 | ||
769 | /* Output the instruction opcode. */ | |
47926f60 | 770 | md_number_to_chars (opcodep, (long) (output_instruction.opcode), 2); |
3bcbcc3d HPN |
771 | |
772 | /* Output the symbol-dependent instruction stuff. */ | |
773 | if (output_instruction.insn_type == CRIS_INSN_BRANCH) | |
774 | { | |
775 | segT to_seg = absolute_section; | |
776 | int is_undefined = 0; | |
777 | int length_code; | |
778 | ||
779 | if (output_instruction.expr.X_op != O_constant) | |
780 | { | |
781 | to_seg = S_GET_SEGMENT (output_instruction.expr.X_add_symbol); | |
782 | ||
783 | if (to_seg == undefined_section) | |
784 | is_undefined = 1; | |
785 | } | |
786 | ||
787 | if (output_instruction.expr.X_op == O_constant | |
788 | || to_seg == now_seg || is_undefined) | |
789 | { | |
790 | /* If is_undefined, then the expression may BECOME now_seg. */ | |
47926f60 | 791 | length_code = is_undefined ? STATE_UNDF : STATE_BYTE; |
3bcbcc3d HPN |
792 | |
793 | /* Make room for max ten bytes of variable length. */ | |
794 | frag_var (rs_machine_dependent, 10, 0, | |
795 | ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, length_code), | |
796 | output_instruction.expr.X_add_symbol, | |
797 | output_instruction.expr.X_add_number, | |
798 | opcodep); | |
799 | } | |
800 | else | |
801 | { | |
802 | /* We have: to_seg != now_seg && to_seg != undefined_section. | |
803 | This means it is a branch to a known symbol in another | |
804 | section. Code in data? Weird but valid. Emit a 32-bit | |
805 | branch. */ | |
fcdc20a4 | 806 | insn_size += 10; |
3bcbcc3d HPN |
807 | gen_cond_branch_32 (opcodep, frag_more (10), frag_now, |
808 | output_instruction.expr.X_add_symbol, | |
47926f60 | 809 | (symbolS *) NULL, |
3bcbcc3d HPN |
810 | output_instruction.expr.X_add_number); |
811 | } | |
812 | } | |
813 | else | |
814 | { | |
815 | if (output_instruction.imm_oprnd_size > 0) | |
816 | { | |
817 | /* The intruction has an immediate operand. */ | |
818 | enum bfd_reloc_code_real reloc = 0; | |
819 | ||
820 | switch (output_instruction.imm_oprnd_size) | |
821 | { | |
822 | /* Any byte-size immediate constants are treated as | |
823 | word-size. FIXME: Thus overflow check does not work | |
824 | correctly. */ | |
825 | ||
826 | case 2: | |
827 | reloc = BFD_RELOC_16; | |
828 | break; | |
829 | ||
830 | case 4: | |
831 | reloc = BFD_RELOC_32; | |
832 | break; | |
833 | ||
834 | default: | |
835 | BAD_CASE (output_instruction.imm_oprnd_size); | |
836 | } | |
837 | ||
fcdc20a4 | 838 | insn_size += output_instruction.imm_oprnd_size; |
3bcbcc3d HPN |
839 | p = frag_more (output_instruction.imm_oprnd_size); |
840 | fix_new_exp (frag_now, (p - frag_now->fr_literal), | |
841 | output_instruction.imm_oprnd_size, | |
842 | &output_instruction.expr, 0, reloc); | |
843 | } | |
844 | else if (output_instruction.reloc != BFD_RELOC_NONE) | |
845 | { | |
846 | /* An immediate operand that has a relocation and needs to be | |
47926f60 | 847 | processed further. */ |
3bcbcc3d HPN |
848 | |
849 | /* It is important to use fix_new_exp here and everywhere else | |
850 | (and not fix_new), as fix_new_exp can handle "difference | |
851 | expressions" - where the expression contains a difference of | |
852 | two symbols in the same segment. */ | |
853 | fix_new_exp (frag_now, (opcodep - frag_now->fr_literal), 2, | |
854 | &output_instruction.expr, 0, | |
855 | output_instruction.reloc); | |
856 | } | |
857 | } | |
fcdc20a4 HPN |
858 | |
859 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
860 | dwarf2_emit_insn (insn_size); | |
3bcbcc3d HPN |
861 | } |
862 | ||
3bcbcc3d | 863 | /* Low level text-to-bits assembly. */ |
47926f60 | 864 | |
3bcbcc3d HPN |
865 | static void |
866 | cris_process_instruction (insn_text, out_insnp, prefixp) | |
867 | char *insn_text; | |
47926f60 | 868 | struct cris_instruction *out_insnp; |
3bcbcc3d HPN |
869 | struct cris_prefix *prefixp; |
870 | { | |
47926f60 KH |
871 | char *s; |
872 | char modified_char = 0; | |
873 | const char *args; | |
3bcbcc3d | 874 | struct cris_opcode *instruction; |
47926f60 KH |
875 | char *operands; |
876 | int match = 0; | |
877 | int mode; | |
878 | int regno; | |
879 | int size_bits; | |
3bcbcc3d HPN |
880 | |
881 | /* Reset these fields to a harmless state in case we need to return in | |
882 | error. */ | |
883 | prefixp->kind = PREFIX_NONE; | |
884 | prefixp->reloc = BFD_RELOC_NONE; | |
885 | out_insnp->insn_type = CRIS_INSN_NORMAL; | |
886 | out_insnp->imm_oprnd_size = 0; | |
887 | ||
888 | /* Find the end of the opcode mnemonic. We assume (true in 2.9.1) | |
889 | that the caller has translated the opcode to lower-case, up to the | |
47926f60 KH |
890 | first non-letter. */ |
891 | for (operands = insn_text; islower (*operands); ++operands) | |
3bcbcc3d HPN |
892 | ; |
893 | ||
894 | /* Terminate the opcode after letters, but save the character there if | |
895 | it was of significance. */ | |
896 | switch (*operands) | |
897 | { | |
898 | case '\0': | |
899 | break; | |
900 | ||
901 | case '.': | |
47926f60 | 902 | /* Put back the modified character later. */ |
3bcbcc3d | 903 | modified_char = *operands; |
47926f60 | 904 | /* Fall through. */ |
3bcbcc3d HPN |
905 | |
906 | case ' ': | |
47926f60 KH |
907 | /* Consume the character after the mnemonic |
908 | and replace it with '\0'. */ | |
3bcbcc3d HPN |
909 | *operands++ = '\0'; |
910 | break; | |
911 | ||
912 | default: | |
913 | as_bad (_("Unknown opcode: `%s'"), insn_text); | |
914 | return; | |
915 | } | |
916 | ||
917 | /* Find the instruction. */ | |
918 | instruction = (struct cris_opcode *) hash_find (op_hash, insn_text); | |
919 | if (instruction == NULL) | |
920 | { | |
921 | as_bad (_("Unknown opcode: `%s'"), insn_text); | |
922 | return; | |
923 | } | |
924 | ||
925 | /* Put back the modified character. */ | |
926 | switch (modified_char) | |
927 | { | |
928 | case 0: | |
929 | break; | |
930 | ||
931 | default: | |
932 | *--operands = modified_char; | |
933 | } | |
934 | ||
3bcbcc3d | 935 | /* Try to match an opcode table slot. */ |
47926f60 | 936 | for (s = operands;;) |
3bcbcc3d | 937 | { |
47926f60 | 938 | int imm_expr_found; |
3bcbcc3d HPN |
939 | |
940 | /* Initialize *prefixp, perhaps after being modified for a | |
47926f60 | 941 | "near match". */ |
3bcbcc3d HPN |
942 | prefixp->kind = PREFIX_NONE; |
943 | prefixp->reloc = BFD_RELOC_NONE; | |
944 | ||
945 | /* Initialize *out_insnp. */ | |
946 | memset (out_insnp, 0, sizeof (*out_insnp)); | |
947 | out_insnp->opcode = instruction->match; | |
948 | out_insnp->reloc = BFD_RELOC_NONE; | |
949 | out_insnp->insn_type = CRIS_INSN_NORMAL; | |
950 | out_insnp->imm_oprnd_size = 0; | |
951 | ||
952 | imm_expr_found = 0; | |
953 | ||
954 | /* Build the opcode, checking as we go to make sure that the | |
955 | operands match. */ | |
47926f60 | 956 | for (args = instruction->args;; ++args) |
3bcbcc3d HPN |
957 | { |
958 | switch (*args) | |
959 | { | |
960 | case '\0': | |
961 | /* If we've come to the end of arguments, we're done. */ | |
962 | if (*s == '\0') | |
963 | match = 1; | |
964 | break; | |
965 | ||
966 | case '!': | |
967 | /* Non-matcher character for disassembly. | |
968 | Ignore it here. */ | |
969 | continue; | |
970 | ||
971 | case ',': | |
972 | case ' ': | |
973 | /* These must match exactly. */ | |
974 | if (*s++ == *args) | |
975 | continue; | |
976 | break; | |
977 | ||
978 | case 'B': | |
979 | /* This is not really an operand, but causes a "BDAP | |
47926f60 | 980 | -size,SP" prefix to be output, for PUSH instructions. */ |
3bcbcc3d HPN |
981 | prefixp->kind = PREFIX_PUSH; |
982 | continue; | |
983 | ||
984 | case 'b': | |
985 | /* This letter marks an operand that should not be matched | |
986 | in the assembler. It is a branch with 16-bit | |
987 | displacement. The assembler will create them from the | |
988 | 8-bit flavor when necessary. The assembler does not | |
989 | support the [rN+] operand, as the [r15+] that is | |
990 | generated for 16-bit displacements. */ | |
991 | break; | |
992 | ||
993 | case 'c': | |
994 | /* A 5-bit unsigned immediate in bits <4:0>. */ | |
995 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
996 | break; | |
997 | else | |
998 | { | |
999 | if (out_insnp->expr.X_op == O_constant | |
1000 | && (out_insnp->expr.X_add_number < 0 | |
1001 | || out_insnp->expr.X_add_number > 31)) | |
1002 | as_bad (_("Immediate value not in 5 bit unsigned range: %ld"), | |
1003 | out_insnp->expr.X_add_number); | |
1004 | ||
1005 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_5; | |
1006 | continue; | |
1007 | } | |
1008 | ||
1009 | case 'C': | |
1010 | /* A 4-bit unsigned immediate in bits <3:0>. */ | |
1011 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1012 | break; | |
1013 | else | |
1014 | { | |
1015 | if (out_insnp->expr.X_op == O_constant | |
1016 | && (out_insnp->expr.X_add_number < 0 | |
1017 | || out_insnp->expr.X_add_number > 15)) | |
1018 | as_bad (_("Immediate value not in 4 bit unsigned range: %ld"), | |
1019 | out_insnp->expr.X_add_number); | |
1020 | ||
1021 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_4; | |
1022 | continue; | |
1023 | } | |
1024 | ||
1025 | case 'D': | |
1026 | /* General register in bits <15:12> and <3:0>. */ | |
1027 | if (! get_gen_reg (&s, ®no)) | |
1028 | break; | |
1029 | else | |
1030 | { | |
1031 | out_insnp->opcode |= regno /* << 0 */; | |
1032 | out_insnp->opcode |= regno << 12; | |
1033 | continue; | |
1034 | } | |
1035 | ||
1036 | case 'f': | |
1037 | /* Flags from the condition code register. */ | |
1038 | { | |
1039 | int flags = 0; | |
1040 | ||
1041 | if (! get_flags (&s, &flags)) | |
1042 | break; | |
1043 | ||
47926f60 | 1044 | out_insnp->opcode |= ((flags & 0xf0) << 8) | (flags & 0xf); |
3bcbcc3d HPN |
1045 | continue; |
1046 | } | |
1047 | ||
1048 | case 'i': | |
1049 | /* A 6-bit signed immediate in bits <5:0>. */ | |
1050 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1051 | break; | |
1052 | else | |
1053 | { | |
1054 | if (out_insnp->expr.X_op == O_constant | |
1055 | && (out_insnp->expr.X_add_number < -32 | |
1056 | || out_insnp->expr.X_add_number > 31)) | |
1057 | as_bad (_("Immediate value not in 6 bit range: %ld"), | |
1058 | out_insnp->expr.X_add_number); | |
1059 | out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_6; | |
1060 | continue; | |
1061 | } | |
1062 | ||
1063 | case 'I': | |
1064 | /* A 6-bit unsigned immediate in bits <5:0>. */ | |
1065 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1066 | break; | |
1067 | else | |
1068 | { | |
1069 | if (out_insnp->expr.X_op == O_constant | |
1070 | && (out_insnp->expr.X_add_number < 0 | |
1071 | || out_insnp->expr.X_add_number > 63)) | |
1072 | as_bad (_("Immediate value not in 6 bit unsigned range: %ld"), | |
1073 | out_insnp->expr.X_add_number); | |
1074 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_6; | |
1075 | continue; | |
1076 | } | |
1077 | ||
1078 | case 'M': | |
1079 | /* A size modifier, B, W or D, to be put in a bit position | |
1080 | suitable for CLEAR instructions (i.e. reflecting a zero | |
1081 | register). */ | |
1082 | if (! get_bwd_size_modifier (&s, &size_bits)) | |
1083 | break; | |
1084 | else | |
1085 | { | |
1086 | switch (size_bits) | |
1087 | { | |
1088 | case 0: | |
1089 | out_insnp->opcode |= 0 << 12; | |
1090 | break; | |
1091 | ||
1092 | case 1: | |
1093 | out_insnp->opcode |= 4 << 12; | |
1094 | break; | |
1095 | ||
1096 | case 2: | |
1097 | out_insnp->opcode |= 8 << 12; | |
1098 | break; | |
1099 | } | |
1100 | continue; | |
1101 | } | |
1102 | ||
1103 | case 'm': | |
1104 | /* A size modifier, B, W or D, to be put in bits <5:4>. */ | |
1105 | if (! get_bwd_size_modifier (&s, &size_bits)) | |
1106 | break; | |
1107 | else | |
1108 | { | |
1109 | out_insnp->opcode |= size_bits << 4; | |
1110 | continue; | |
1111 | } | |
1112 | ||
1113 | case 'o': | |
1114 | /* A branch expression. */ | |
1115 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1116 | break; | |
1117 | else | |
1118 | { | |
1119 | out_insnp->insn_type = CRIS_INSN_BRANCH; | |
1120 | continue; | |
1121 | } | |
1122 | ||
1123 | case 'O': | |
1124 | /* A BDAP expression for any size, "expr,r". */ | |
1125 | if (! cris_get_expression (&s, &prefixp->expr)) | |
1126 | break; | |
1127 | else | |
1128 | { | |
1129 | if (*s != ',') | |
1130 | break; | |
1131 | ||
1132 | s++; | |
1133 | ||
1134 | if (!get_gen_reg (&s, &prefixp->base_reg_number)) | |
1135 | break; | |
1136 | ||
1137 | /* Since 'O' is used with an explicit bdap, we have no | |
47926f60 | 1138 | "real" instruction. */ |
3bcbcc3d HPN |
1139 | prefixp->kind = PREFIX_BDAP_IMM; |
1140 | out_insnp->insn_type = CRIS_INSN_NONE; | |
1141 | continue; | |
1142 | } | |
1143 | ||
1144 | case 'P': | |
1145 | /* Special register in bits <15:12>. */ | |
1146 | if (! get_spec_reg (&s, &out_insnp->spec_reg)) | |
1147 | break; | |
1148 | else | |
1149 | { | |
1150 | /* Use of some special register names come with a | |
1151 | specific warning. Note that we have no ".cpu type" | |
1152 | pseudo yet, so some of this is just unused | |
1153 | framework. */ | |
1154 | if (out_insnp->spec_reg->warning) | |
1155 | as_warn (out_insnp->spec_reg->warning); | |
1156 | else if (out_insnp->spec_reg->applicable_version | |
1157 | == cris_ver_warning) | |
1158 | /* Others have a generic warning. */ | |
1159 | as_warn (_("Unimplemented register `%s' specified"), | |
1160 | out_insnp->spec_reg->name); | |
1161 | ||
1162 | out_insnp->opcode | |
1163 | |= out_insnp->spec_reg->number << 12; | |
1164 | continue; | |
1165 | } | |
1166 | ||
1167 | case 'p': | |
1168 | /* This character is used in the disassembler to | |
1169 | recognize a prefix instruction to fold into the | |
1170 | addressing mode for the next instruction. It is | |
47926f60 | 1171 | ignored here. */ |
3bcbcc3d HPN |
1172 | continue; |
1173 | ||
1174 | case 'R': | |
1175 | /* General register in bits <15:12>. */ | |
1176 | if (! get_gen_reg (&s, ®no)) | |
1177 | break; | |
1178 | else | |
1179 | { | |
1180 | out_insnp->opcode |= regno << 12; | |
1181 | continue; | |
1182 | } | |
1183 | ||
1184 | case 'r': | |
1185 | /* General register in bits <3:0>. */ | |
1186 | if (! get_gen_reg (&s, ®no)) | |
1187 | break; | |
1188 | else | |
1189 | { | |
1190 | out_insnp->opcode |= regno /* << 0 */; | |
1191 | continue; | |
1192 | } | |
1193 | ||
1194 | case 'S': | |
1195 | /* Source operand in bit <10> and a prefix; a 3-operand | |
1196 | prefix. */ | |
1197 | if (! get_3op_or_dip_prefix_op (&s, prefixp)) | |
1198 | break; | |
1199 | else | |
1200 | continue; | |
1201 | ||
1202 | case 's': | |
1203 | /* Source operand in bits <10>, <3:0> and optionally a | |
1204 | prefix; i.e. an indirect operand or an side-effect | |
1205 | prefix. */ | |
1206 | if (! get_autoinc_prefix_or_indir_op (&s, prefixp, &mode, | |
1207 | ®no, | |
1208 | &imm_expr_found, | |
1209 | &out_insnp->expr)) | |
1210 | break; | |
1211 | else | |
1212 | { | |
1213 | if (prefixp->kind != PREFIX_NONE) | |
1214 | { | |
1215 | /* A prefix, so it has the autoincrement bit | |
1216 | set. */ | |
1217 | out_insnp->opcode |= (AUTOINCR_BIT << 8); | |
1218 | } | |
1219 | else | |
1220 | /* No prefix. The "mode" variable contains bits like | |
1221 | whether or not this is autoincrement mode. */ | |
1222 | out_insnp->opcode |= (mode << 10); | |
1223 | ||
1224 | out_insnp->opcode |= regno /* << 0 */ ; | |
1225 | continue; | |
1226 | } | |
1227 | ||
1228 | case 'x': | |
1229 | /* Rs.m in bits <15:12> and <5:4>. */ | |
1230 | if (! get_gen_reg (&s, ®no) | |
1231 | || ! get_bwd_size_modifier (&s, &size_bits)) | |
1232 | break; | |
1233 | else | |
1234 | { | |
47926f60 | 1235 | out_insnp->opcode |= (regno << 12) | (size_bits << 4); |
3bcbcc3d HPN |
1236 | continue; |
1237 | } | |
1238 | ||
1239 | case 'y': | |
1240 | /* Source operand in bits <10>, <3:0> and optionally a | |
1241 | prefix; i.e. an indirect operand or an side-effect | |
1242 | prefix. | |
1243 | ||
1244 | The difference to 's' is that this does not allow an | |
81d4177b | 1245 | "immediate" expression. */ |
3bcbcc3d HPN |
1246 | if (! get_autoinc_prefix_or_indir_op (&s, prefixp, |
1247 | &mode, ®no, | |
1248 | &imm_expr_found, | |
1249 | &out_insnp->expr) | |
1250 | || imm_expr_found) | |
1251 | break; | |
1252 | else | |
1253 | { | |
1254 | if (prefixp->kind != PREFIX_NONE) | |
1255 | { | |
1256 | /* A prefix, and those matched here always have | |
1257 | side-effects (see 's' case). */ | |
1258 | out_insnp->opcode |= (AUTOINCR_BIT << 8); | |
1259 | } | |
1260 | else | |
1261 | { | |
1262 | /* No prefix. The "mode" variable contains bits | |
1263 | like whether or not this is autoincrement | |
1264 | mode. */ | |
1265 | out_insnp->opcode |= (mode << 10); | |
1266 | } | |
1267 | ||
1268 | out_insnp->opcode |= regno /* << 0 */; | |
1269 | continue; | |
1270 | } | |
1271 | ||
1272 | case 'z': | |
1273 | /* Size modifier (B or W) in bit <4>. */ | |
1274 | if (! get_bw_size_modifier (&s, &size_bits)) | |
1275 | break; | |
1276 | else | |
1277 | { | |
1278 | out_insnp->opcode |= size_bits << 4; | |
1279 | continue; | |
1280 | } | |
1281 | ||
1282 | default: | |
1283 | BAD_CASE (*args); | |
1284 | } | |
1285 | ||
1286 | /* We get here when we fail a match above or we found a | |
1287 | complete match. Break out of this loop. */ | |
1288 | break; | |
1289 | } | |
1290 | ||
1291 | /* Was it a match or a miss? */ | |
1292 | if (match == 0) | |
1293 | { | |
1294 | /* If it's just that the args don't match, maybe the next | |
1295 | item in the table is the same opcode but with | |
1296 | matching operands. */ | |
1297 | if (instruction[1].name != NULL | |
1298 | && ! strcmp (instruction->name, instruction[1].name)) | |
1299 | { | |
1300 | /* Yep. Restart and try that one instead. */ | |
1301 | ++instruction; | |
1302 | s = operands; | |
1303 | continue; | |
1304 | } | |
1305 | else | |
1306 | { | |
1307 | /* We've come to the end of instructions with this | |
1308 | opcode, so it must be an error. */ | |
1309 | as_bad (_("Illegal operands")); | |
1310 | return; | |
1311 | } | |
1312 | } | |
1313 | else | |
1314 | { | |
1315 | /* We have a match. Check if there's anything more to do. */ | |
1316 | if (imm_expr_found) | |
1317 | { | |
1318 | /* There was an immediate mode operand, so we must check | |
1319 | that it has an appropriate size. */ | |
1320 | ||
1321 | switch (instruction->imm_oprnd_size) | |
1322 | { | |
1323 | default: | |
1324 | case SIZE_NONE: | |
1325 | /* Shouldn't happen; this one does not have immediate | |
1326 | operands with different sizes. */ | |
1327 | BAD_CASE (instruction->imm_oprnd_size); | |
1328 | break; | |
1329 | ||
1330 | case SIZE_FIX_32: | |
1331 | out_insnp->imm_oprnd_size = 4; | |
1332 | break; | |
1333 | ||
1334 | case SIZE_SPEC_REG: | |
1335 | switch (out_insnp->spec_reg->reg_size) | |
1336 | { | |
1337 | case 1: | |
1338 | if (out_insnp->expr.X_op == O_constant | |
1339 | && (out_insnp->expr.X_add_number < -128 | |
1340 | || out_insnp->expr.X_add_number > 255)) | |
1341 | as_bad (_("Immediate value not in 8 bit range: %ld"), | |
1342 | out_insnp->expr.X_add_number); | |
47926f60 | 1343 | /* Fall through. */ |
3bcbcc3d HPN |
1344 | case 2: |
1345 | /* FIXME: We need an indicator in the instruction | |
1346 | table to pass on, to indicate if we need to check | |
1347 | overflow for a signed or unsigned number. */ | |
1348 | if (out_insnp->expr.X_op == O_constant | |
1349 | && (out_insnp->expr.X_add_number < -32768 | |
1350 | || out_insnp->expr.X_add_number > 65535)) | |
1351 | as_bad (_("Immediate value not in 16 bit range: %ld"), | |
1352 | out_insnp->expr.X_add_number); | |
1353 | out_insnp->imm_oprnd_size = 2; | |
1354 | break; | |
1355 | ||
1356 | case 4: | |
1357 | out_insnp->imm_oprnd_size = 4; | |
1358 | break; | |
1359 | ||
1360 | default: | |
1361 | BAD_CASE (out_insnp->spec_reg->reg_size); | |
1362 | } | |
1363 | break; | |
1364 | ||
1365 | case SIZE_FIELD: | |
1366 | switch (size_bits) | |
1367 | { | |
1368 | case 0: | |
1369 | if (out_insnp->expr.X_op == O_constant | |
1370 | && (out_insnp->expr.X_add_number < -128 | |
1371 | || out_insnp->expr.X_add_number > 255)) | |
1372 | as_bad (_("Immediate value not in 8 bit range: %ld"), | |
1373 | out_insnp->expr.X_add_number); | |
47926f60 | 1374 | /* Fall through. */ |
3bcbcc3d HPN |
1375 | case 1: |
1376 | if (out_insnp->expr.X_op == O_constant | |
1377 | && (out_insnp->expr.X_add_number < -32768 | |
1378 | || out_insnp->expr.X_add_number > 65535)) | |
1379 | as_bad (_("Immediate value not in 16 bit range: %ld"), | |
1380 | out_insnp->expr.X_add_number); | |
1381 | out_insnp->imm_oprnd_size = 2; | |
1382 | break; | |
1383 | ||
1384 | case 2: | |
1385 | out_insnp->imm_oprnd_size = 4; | |
1386 | break; | |
1387 | ||
1388 | default: | |
1389 | BAD_CASE (out_insnp->spec_reg->reg_size); | |
1390 | } | |
1391 | } | |
1392 | } | |
1393 | } | |
1394 | break; | |
1395 | } | |
1396 | } | |
1397 | ||
3bcbcc3d HPN |
1398 | /* Get a B, W, or D size modifier from the string pointed out by *cPP, |
1399 | which must point to a '.' in front of the modifier. On successful | |
1400 | return, *cPP is advanced to the character following the size | |
1401 | modifier, and is undefined otherwise. | |
1402 | ||
1403 | cPP Pointer to pointer to string starting | |
1404 | with the size modifier. | |
1405 | ||
1406 | size_bitsp Pointer to variable to contain the size bits on | |
1407 | successful return. | |
1408 | ||
1409 | Return 1 iff a correct size modifier is found, else 0. */ | |
1410 | ||
1411 | static int | |
1412 | get_bwd_size_modifier (cPP, size_bitsp) | |
1413 | char **cPP; | |
1414 | int *size_bitsp; | |
1415 | { | |
1416 | if (**cPP != '.') | |
1417 | return 0; | |
1418 | else | |
1419 | { | |
47926f60 | 1420 | /* Consume the '.'. */ |
3bcbcc3d HPN |
1421 | (*cPP)++; |
1422 | ||
1423 | switch (**cPP) | |
1424 | { | |
1425 | case 'B': | |
1426 | case 'b': | |
1427 | *size_bitsp = 0; | |
1428 | break; | |
1429 | ||
1430 | case 'W': | |
1431 | case 'w': | |
1432 | *size_bitsp = 1; | |
1433 | break; | |
1434 | ||
1435 | case 'D': | |
1436 | case 'd': | |
1437 | *size_bitsp = 2; | |
1438 | break; | |
1439 | ||
1440 | default: | |
1441 | return 0; | |
1442 | } | |
1443 | ||
1444 | /* Consume the size letter. */ | |
1445 | (*cPP)++; | |
1446 | return 1; | |
1447 | } | |
1448 | } | |
1449 | ||
3bcbcc3d HPN |
1450 | /* Get a B or W size modifier from the string pointed out by *cPP, |
1451 | which must point to a '.' in front of the modifier. On successful | |
1452 | return, *cPP is advanced to the character following the size | |
1453 | modifier, and is undefined otherwise. | |
1454 | ||
1455 | cPP Pointer to pointer to string starting | |
1456 | with the size modifier. | |
1457 | ||
1458 | size_bitsp Pointer to variable to contain the size bits on | |
1459 | successful return. | |
1460 | ||
1461 | Return 1 iff a correct size modifier is found, else 0. */ | |
1462 | ||
1463 | static int | |
1464 | get_bw_size_modifier (cPP, size_bitsp) | |
1465 | char **cPP; | |
1466 | int *size_bitsp; | |
1467 | { | |
1468 | if (**cPP != '.') | |
1469 | return 0; | |
1470 | else | |
1471 | { | |
47926f60 | 1472 | /* Consume the '.'. */ |
3bcbcc3d HPN |
1473 | (*cPP)++; |
1474 | ||
1475 | switch (**cPP) | |
1476 | { | |
1477 | case 'B': | |
1478 | case 'b': | |
1479 | *size_bitsp = 0; | |
1480 | break; | |
1481 | ||
1482 | case 'W': | |
1483 | case 'w': | |
1484 | *size_bitsp = 1; | |
1485 | break; | |
1486 | ||
1487 | default: | |
1488 | return 0; | |
1489 | } | |
1490 | ||
1491 | /* Consume the size letter. */ | |
1492 | (*cPP)++; | |
1493 | return 1; | |
1494 | } | |
1495 | } | |
1496 | ||
07e90ad5 | 1497 | /* Get a general register from the string pointed out by *cPP. The |
3bcbcc3d HPN |
1498 | variable *cPP is advanced to the character following the general |
1499 | register name on a successful return, and has its initial position | |
1500 | otherwise. | |
1501 | ||
1502 | cPP Pointer to pointer to string, beginning with a general | |
1503 | register name. | |
1504 | ||
1505 | regnop Pointer to int containing the register number. | |
1506 | ||
1507 | Return 1 iff a correct general register designator is found, | |
1508 | else 0. */ | |
1509 | ||
1510 | static int | |
1511 | get_gen_reg (cPP, regnop) | |
1512 | char **cPP; | |
1513 | int *regnop; | |
1514 | { | |
1515 | char *oldp; | |
1516 | oldp = *cPP; | |
1517 | ||
7b15d668 HPN |
1518 | /* Handle a sometimes-mandatory dollar sign as register prefix. */ |
1519 | if (**cPP == REGISTER_PREFIX_CHAR) | |
1520 | (*cPP)++; | |
1521 | else if (demand_register_prefix) | |
1522 | return 0; | |
1523 | ||
3bcbcc3d HPN |
1524 | switch (**cPP) |
1525 | { | |
1526 | case 'P': | |
1527 | case 'p': | |
1528 | /* "P" as in "PC"? Consume the "P". */ | |
1529 | (*cPP)++; | |
1530 | ||
1531 | if ((**cPP == 'C' || **cPP == 'c') | |
1532 | && ! isalnum ((*cPP)[1])) | |
1533 | { | |
1534 | /* It's "PC": consume the "c" and we're done. */ | |
1535 | (*cPP)++; | |
1536 | *regnop = REG_PC; | |
1537 | return 1; | |
1538 | } | |
1539 | break; | |
1540 | ||
1541 | case 'R': | |
1542 | case 'r': | |
47926f60 | 1543 | /* Hopefully r[0-9] or r1[0-5]. Consume 'R' or 'r'. */ |
3bcbcc3d HPN |
1544 | (*cPP)++; |
1545 | ||
1546 | if (isdigit (**cPP)) | |
1547 | { | |
1548 | /* It's r[0-9]. Consume and check the next digit. */ | |
1549 | *regnop = **cPP - '0'; | |
1550 | (*cPP)++; | |
1551 | ||
1552 | if (! isalnum (**cPP)) | |
1553 | { | |
47926f60 | 1554 | /* No more digits, we're done. */ |
3bcbcc3d HPN |
1555 | return 1; |
1556 | } | |
1557 | else | |
1558 | { | |
1559 | /* One more digit. Consume and add. */ | |
47926f60 | 1560 | *regnop = *regnop * 10 + (**cPP - '0'); |
3bcbcc3d HPN |
1561 | |
1562 | /* We need to check for a valid register number; Rn, | |
1563 | 0 <= n <= MAX_REG. */ | |
1564 | if (*regnop <= MAX_REG) | |
1565 | { | |
1566 | /* Consume second digit. */ | |
1567 | (*cPP)++; | |
1568 | return 1; | |
1569 | } | |
1570 | } | |
1571 | } | |
1572 | break; | |
1573 | ||
1574 | case 'S': | |
1575 | case 's': | |
1576 | /* "S" as in "SP"? Consume the "S". */ | |
1577 | (*cPP)++; | |
1578 | if (**cPP == 'P' || **cPP == 'p') | |
1579 | { | |
1580 | /* It's "SP": consume the "p" and we're done. */ | |
1581 | (*cPP)++; | |
1582 | *regnop = REG_SP; | |
1583 | return 1; | |
1584 | } | |
1585 | break; | |
1586 | ||
1587 | default: | |
1588 | /* Just here to silence compilation warnings. */ | |
1589 | ; | |
1590 | } | |
1591 | ||
1592 | /* We get here if we fail. Restore the pointer. */ | |
1593 | *cPP = oldp; | |
1594 | return 0; | |
1595 | } | |
1596 | ||
3bcbcc3d HPN |
1597 | /* Get a special register from the string pointed out by *cPP. The |
1598 | variable *cPP is advanced to the character following the special | |
1599 | register name if one is found, and retains its original position | |
1600 | otherwise. | |
1601 | ||
1602 | cPP Pointer to pointer to string starting with a special register | |
1603 | name. | |
1604 | ||
1605 | sregpp Pointer to Pointer to struct spec_reg, where a pointer to the | |
1606 | register description will be stored. | |
1607 | ||
1608 | Return 1 iff a correct special register name is found. */ | |
1609 | ||
1610 | static int | |
1611 | get_spec_reg (cPP, sregpp) | |
1612 | char **cPP; | |
1613 | const struct cris_spec_reg **sregpp; | |
1614 | { | |
1615 | char *s1; | |
1616 | const char *s2; | |
7b15d668 | 1617 | char *name_begin = *cPP; |
3bcbcc3d HPN |
1618 | |
1619 | const struct cris_spec_reg *sregp; | |
1620 | ||
7b15d668 HPN |
1621 | /* Handle a sometimes-mandatory dollar sign as register prefix. */ |
1622 | if (*name_begin == REGISTER_PREFIX_CHAR) | |
1623 | name_begin++; | |
1624 | else if (demand_register_prefix) | |
1625 | return 0; | |
1626 | ||
3bcbcc3d | 1627 | /* Loop over all special registers. */ |
47926f60 | 1628 | for (sregp = cris_spec_regs; sregp->name != NULL; sregp++) |
3bcbcc3d | 1629 | { |
3bcbcc3d | 1630 | /* Start over from beginning of the supposed name. */ |
7b15d668 | 1631 | s1 = name_begin; |
3bcbcc3d HPN |
1632 | s2 = sregp->name; |
1633 | ||
1634 | while (*s2 != '\0' | |
1635 | && (isupper (*s1) ? tolower (*s1) == *s2 : *s1 == *s2)) | |
1636 | { | |
1637 | s1++; | |
1638 | s2++; | |
1639 | } | |
1640 | ||
1641 | /* For a match, we must have consumed the name in the table, and we | |
1642 | must be outside what could be part of a name. Assume here that a | |
47926f60 | 1643 | test for alphanumerics is sufficient for a name test. */ |
3bcbcc3d HPN |
1644 | if (*s2 == 0 && ! isalnum (*s1)) |
1645 | { | |
47926f60 | 1646 | /* We have a match. Update the pointer and be done. */ |
3bcbcc3d HPN |
1647 | *cPP = s1; |
1648 | *sregpp = sregp; | |
1649 | return 1; | |
1650 | } | |
1651 | } | |
1652 | ||
47926f60 | 1653 | /* If we got here, we did not find any name. */ |
3bcbcc3d HPN |
1654 | return 0; |
1655 | } | |
1656 | ||
3bcbcc3d HPN |
1657 | /* Get an unprefixed or side-effect-prefix operand from the string pointed |
1658 | out by *cPP. The pointer *cPP is advanced to the character following | |
1659 | the indirect operand if we have success, else it contains an undefined | |
1660 | value. | |
1661 | ||
1662 | cPP Pointer to pointer to string beginning with the first | |
1663 | character of the supposed operand. | |
1664 | ||
1665 | prefixp Pointer to structure containing an optional instruction | |
1666 | prefix. | |
1667 | ||
1668 | is_autoincp Pointer to int indicating the indirect or autoincrement | |
1669 | bits. | |
1670 | ||
1671 | src_regnop Pointer to int containing the source register number in | |
1672 | the instruction. | |
1673 | ||
1674 | imm_foundp Pointer to an int indicating if an immediate expression | |
1675 | is found. | |
1676 | ||
1677 | imm_exprP Pointer to a structure containing an immediate | |
1678 | expression, if success and if *imm_foundp is nonzero. | |
1679 | ||
1680 | Return 1 iff a correct indirect operand is found. */ | |
1681 | ||
1682 | static int | |
1683 | get_autoinc_prefix_or_indir_op (cPP, prefixp, is_autoincp, src_regnop, | |
1684 | imm_foundp, imm_exprP) | |
47926f60 KH |
1685 | char **cPP; |
1686 | struct cris_prefix *prefixp; | |
1687 | int *is_autoincp; | |
1688 | int *src_regnop; | |
1689 | int *imm_foundp; | |
1690 | expressionS *imm_exprP; | |
3bcbcc3d HPN |
1691 | { |
1692 | /* Assume there was no immediate mode expression. */ | |
1693 | *imm_foundp = 0; | |
1694 | ||
1695 | if (**cPP == '[') | |
1696 | { | |
1697 | /* So this operand is one of: | |
1698 | Indirect: [rN] | |
1699 | Autoincrement: [rN+] | |
1700 | Indexed with assign: [rN=rM+rO.S] | |
1701 | Offset with assign: [rN=rM+I], [rN=rM+[rO].s], [rN=rM+[rO+].s] | |
1702 | ||
1703 | Either way, consume the '['. */ | |
1704 | (*cPP)++; | |
1705 | ||
1706 | /* Get the rN register. */ | |
1707 | if (! get_gen_reg (cPP, src_regnop)) | |
1708 | /* If there was no register, then this cannot match. */ | |
1709 | return 0; | |
1710 | else | |
1711 | { | |
1712 | /* We got the register, now check the next character. */ | |
1713 | switch (**cPP) | |
1714 | { | |
1715 | case ']': | |
1716 | /* Indirect mode. We're done here. */ | |
1717 | prefixp->kind = PREFIX_NONE; | |
1718 | *is_autoincp = 0; | |
1719 | break; | |
1720 | ||
1721 | case '+': | |
1722 | /* This must be an auto-increment mode, if there's a | |
1723 | match. */ | |
1724 | prefixp->kind = PREFIX_NONE; | |
1725 | *is_autoincp = 1; | |
1726 | ||
1727 | /* We consume this character and break out to check the | |
1728 | closing ']'. */ | |
1729 | (*cPP)++; | |
1730 | break; | |
1731 | ||
1732 | case '=': | |
1733 | /* This must be indexed with assign, or offset with assign | |
1734 | to match. */ | |
1735 | (*cPP)++; | |
1736 | ||
1737 | /* Either way, the next thing must be a register. */ | |
1738 | if (! get_gen_reg (cPP, &prefixp->base_reg_number)) | |
1739 | /* No register, no match. */ | |
1740 | return 0; | |
1741 | else | |
1742 | { | |
1743 | /* We've consumed "[rN=rM", so we must be looking at | |
1744 | "+rO.s]" or "+I]", or "-I]", or "+[rO].s]" or | |
1745 | "+[rO+].s]". */ | |
1746 | if (**cPP == '+') | |
1747 | { | |
1748 | int index_reg_number; | |
1749 | (*cPP)++; | |
1750 | ||
1751 | if (**cPP == '[') | |
1752 | { | |
1753 | int size_bits; | |
1754 | /* This must be [rx=ry+[rz].s] or | |
1755 | [rx=ry+[rz+].s] or no match. We must be | |
1756 | looking at rz after consuming the '['. */ | |
1757 | (*cPP)++; | |
1758 | ||
1759 | if (!get_gen_reg (cPP, &index_reg_number)) | |
1760 | return 0; | |
1761 | ||
1762 | prefixp->kind = PREFIX_BDAP; | |
1763 | prefixp->opcode | |
1764 | = (BDAP_INDIR_OPCODE | |
1765 | + (prefixp->base_reg_number << 12) | |
1766 | + index_reg_number); | |
1767 | ||
1768 | if (**cPP == '+') | |
1769 | { | |
1770 | /* We've seen "[rx=ry+[rz+" here, so now we | |
1771 | know that there must be "].s]" left to | |
1772 | check. */ | |
1773 | (*cPP)++; | |
1774 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
1775 | } | |
1776 | ||
1777 | /* If it wasn't autoincrement, we don't need to | |
1778 | add anything. */ | |
1779 | ||
1780 | /* Check the next-to-last ']'. */ | |
1781 | if (**cPP != ']') | |
1782 | return 0; | |
1783 | ||
1784 | (*cPP)++; | |
1785 | ||
1786 | /* Check the ".s" modifier. */ | |
1787 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
1788 | return 0; | |
1789 | ||
1790 | prefixp->opcode |= size_bits << 4; | |
1791 | ||
1792 | /* Now we got [rx=ry+[rz+].s or [rx=ry+[rz].s. | |
1793 | We break out to check the final ']'. */ | |
1794 | break; | |
1795 | } | |
ab3e48dc KH |
1796 | /* It wasn't an indirection. Check if it's a |
1797 | register. */ | |
1798 | else if (get_gen_reg (cPP, &index_reg_number)) | |
47926f60 KH |
1799 | { |
1800 | int size_bits; | |
1801 | ||
1802 | /* Indexed with assign mode: "[rN+rM.S]". */ | |
1803 | prefixp->kind = PREFIX_BIAP; | |
1804 | prefixp->opcode | |
1805 | = (BIAP_OPCODE + (index_reg_number << 12) | |
1806 | + prefixp->base_reg_number /* << 0 */); | |
1807 | ||
1808 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
1809 | /* Size missing, this isn't a match. */ | |
1810 | return 0; | |
1811 | else | |
3bcbcc3d | 1812 | { |
47926f60 | 1813 | /* Size found, break out to check the |
3bcbcc3d | 1814 | final ']'. */ |
47926f60 | 1815 | prefixp->opcode |= size_bits << 4; |
3bcbcc3d HPN |
1816 | break; |
1817 | } | |
47926f60 KH |
1818 | } |
1819 | /* Not a register. Then this must be "[rN+I]". */ | |
1820 | else if (cris_get_expression (cPP, &prefixp->expr)) | |
1821 | { | |
1822 | /* We've got offset with assign mode. Fill | |
1823 | in the blanks and break out to match the | |
1824 | final ']'. */ | |
1825 | prefixp->kind = PREFIX_BDAP_IMM; | |
1826 | break; | |
1827 | } | |
1828 | else | |
1829 | /* Neither register nor expression found, so | |
1830 | this can't be a match. */ | |
1831 | return 0; | |
3bcbcc3d | 1832 | } |
47926f60 | 1833 | /* Not "[rN+" but perhaps "[rN-"? */ |
ab3e48dc | 1834 | else if (**cPP == '-') |
47926f60 KH |
1835 | { |
1836 | /* We must have an offset with assign mode. */ | |
1837 | if (! cris_get_expression (cPP, &prefixp->expr)) | |
1838 | /* No expression, no match. */ | |
1839 | return 0; | |
1840 | else | |
1841 | { | |
1842 | /* We've got offset with assign mode. Fill | |
1843 | in the blanks and break out to match the | |
1844 | final ']'. */ | |
1845 | prefixp->kind = PREFIX_BDAP_IMM; | |
1846 | break; | |
1847 | } | |
1848 | } | |
1849 | else | |
1850 | /* Neither '+' nor '-' after "[rN=rM". Lose. */ | |
1851 | return 0; | |
3bcbcc3d HPN |
1852 | } |
1853 | default: | |
1854 | /* Neither ']' nor '+' nor '=' after "[rN". Lose. */ | |
1855 | return 0; | |
1856 | } | |
1857 | } | |
1858 | ||
1859 | /* When we get here, we have a match and will just check the closing | |
1860 | ']'. We can still fail though. */ | |
1861 | if (**cPP != ']') | |
1862 | return 0; | |
1863 | else | |
1864 | { | |
1865 | /* Don't forget to consume the final ']'. | |
1866 | Then return in glory. */ | |
1867 | (*cPP)++; | |
1868 | return 1; | |
1869 | } | |
1870 | } | |
47926f60 | 1871 | /* No indirection. Perhaps a constant? */ |
ab3e48dc | 1872 | else if (cris_get_expression (cPP, imm_exprP)) |
47926f60 KH |
1873 | { |
1874 | /* Expression found, this is immediate mode. */ | |
1875 | prefixp->kind = PREFIX_NONE; | |
1876 | *is_autoincp = 1; | |
1877 | *src_regnop = REG_PC; | |
1878 | *imm_foundp = 1; | |
1879 | return 1; | |
1880 | } | |
3bcbcc3d HPN |
1881 | |
1882 | /* No luck today. */ | |
1883 | return 0; | |
1884 | } | |
1885 | ||
3bcbcc3d HPN |
1886 | /* This function gets an indirect operand in a three-address operand |
1887 | combination from the string pointed out by *cPP. The pointer *cPP is | |
1888 | advanced to the character following the indirect operand on success, or | |
1889 | has an unspecified value on failure. | |
1890 | ||
1891 | cPP Pointer to pointer to string begining | |
1892 | with the operand | |
1893 | ||
1894 | prefixp Pointer to structure containing an | |
1895 | instruction prefix | |
1896 | ||
1897 | Returns 1 iff a correct indirect operand is found. */ | |
1898 | ||
1899 | static int | |
1900 | get_3op_or_dip_prefix_op (cPP, prefixp) | |
1901 | char **cPP; | |
1902 | struct cris_prefix *prefixp; | |
1903 | { | |
ab3e48dc KH |
1904 | int reg_number; |
1905 | ||
3bcbcc3d HPN |
1906 | if (**cPP != '[') |
1907 | /* We must have a '[' or it's a clean failure. */ | |
1908 | return 0; | |
3bcbcc3d | 1909 | |
47926f60 KH |
1910 | /* Eat the first '['. */ |
1911 | (*cPP)++; | |
1912 | ||
1913 | if (**cPP == '[') | |
1914 | { | |
1915 | /* A second '[', so this must be double-indirect mode. */ | |
3bcbcc3d | 1916 | (*cPP)++; |
47926f60 KH |
1917 | prefixp->kind = PREFIX_DIP; |
1918 | prefixp->opcode = DIP_OPCODE; | |
3bcbcc3d | 1919 | |
47926f60 KH |
1920 | /* Get the register or fail entirely. */ |
1921 | if (! get_gen_reg (cPP, ®_number)) | |
1922 | return 0; | |
1923 | else | |
3bcbcc3d | 1924 | { |
47926f60 KH |
1925 | prefixp->opcode |= reg_number /* << 0 */ ; |
1926 | if (**cPP == '+') | |
1927 | { | |
1928 | /* Since we found a '+', this must be double-indirect | |
1929 | autoincrement mode. */ | |
1930 | (*cPP)++; | |
1931 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
1932 | } | |
1933 | ||
1934 | /* There's nothing particular to do, if this was a | |
1935 | double-indirect *without* autoincrement. */ | |
1936 | } | |
1937 | ||
1938 | /* Check the first ']'. The second one is checked at the end. */ | |
1939 | if (**cPP != ']') | |
1940 | return 0; | |
1941 | ||
1942 | /* Eat the first ']', so we'll be looking at a second ']'. */ | |
1943 | (*cPP)++; | |
1944 | } | |
1945 | /* No second '['. Then we should have a register here, making | |
1946 | it "[rN". */ | |
1947 | else if (get_gen_reg (cPP, &prefixp->base_reg_number)) | |
1948 | { | |
1949 | /* This must be indexed or offset mode: "[rN+I]" or | |
1950 | "[rN+rM.S]" or "[rN+[rM].S]" or "[rN+[rM+].S]". */ | |
1951 | if (**cPP == '+') | |
1952 | { | |
1953 | /* Not the first alternative, must be one of the last | |
1954 | three. */ | |
1955 | int index_reg_number; | |
1956 | ||
3bcbcc3d | 1957 | (*cPP)++; |
3bcbcc3d | 1958 | |
47926f60 | 1959 | if (**cPP == '[') |
3bcbcc3d | 1960 | { |
47926f60 KH |
1961 | /* This is "[rx+["... Expect a register next. */ |
1962 | int size_bits; | |
1963 | (*cPP)++; | |
1964 | ||
1965 | if (!get_gen_reg (cPP, &index_reg_number)) | |
1966 | return 0; | |
1967 | ||
1968 | prefixp->kind = PREFIX_BDAP; | |
1969 | prefixp->opcode | |
1970 | = (BDAP_INDIR_OPCODE | |
1971 | + (prefixp->base_reg_number << 12) | |
1972 | + index_reg_number); | |
1973 | ||
1974 | /* We've seen "[rx+[ry", so check if this is | |
1975 | autoincrement. */ | |
3bcbcc3d HPN |
1976 | if (**cPP == '+') |
1977 | { | |
47926f60 | 1978 | /* Yep, now at "[rx+[ry+". */ |
3bcbcc3d HPN |
1979 | (*cPP)++; |
1980 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
1981 | } | |
47926f60 KH |
1982 | /* If it wasn't autoincrement, we don't need to |
1983 | add anything. */ | |
3bcbcc3d | 1984 | |
47926f60 KH |
1985 | /* Check a first closing ']': "[rx+[ry]" or |
1986 | "[rx+[ry+]". */ | |
1987 | if (**cPP != ']') | |
1988 | return 0; | |
1989 | (*cPP)++; | |
3bcbcc3d | 1990 | |
47926f60 KH |
1991 | /* Now expect a size modifier ".S". */ |
1992 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
1993 | return 0; | |
3bcbcc3d | 1994 | |
47926f60 KH |
1995 | prefixp->opcode |= size_bits << 4; |
1996 | ||
1997 | /* Ok, all interesting stuff has been seen: | |
1998 | "[rx+[ry+].S" or "[rx+[ry].S". We only need to | |
1999 | expect a final ']', which we'll do in a common | |
2000 | closing session. */ | |
2001 | } | |
2002 | /* Seen "[rN+", but not a '[', so check if we have a | |
2003 | register. */ | |
2004 | else if (get_gen_reg (cPP, &index_reg_number)) | |
2005 | { | |
2006 | /* This is indexed mode: "[rN+rM.S]" or | |
2007 | "[rN+rM.S+]". */ | |
2008 | int size_bits; | |
2009 | prefixp->kind = PREFIX_BIAP; | |
2010 | prefixp->opcode | |
2011 | = (BIAP_OPCODE | |
2012 | | prefixp->base_reg_number /* << 0 */ | |
2013 | | (index_reg_number << 12)); | |
2014 | ||
07e90ad5 | 2015 | /* Consume the ".S". */ |
47926f60 KH |
2016 | if (! get_bwd_size_modifier (cPP, &size_bits)) |
2017 | /* Missing size, so fail. */ | |
2018 | return 0; | |
3bcbcc3d | 2019 | else |
47926f60 KH |
2020 | /* Size found. Add that piece and drop down to |
2021 | the common checking of the closing ']'. */ | |
2022 | prefixp->opcode |= size_bits << 4; | |
2023 | } | |
2024 | /* Seen "[rN+", but not a '[' or a register, so then | |
2025 | it must be a constant "I". */ | |
2026 | else if (cris_get_expression (cPP, &prefixp->expr)) | |
2027 | { | |
2028 | /* Expression found, so fill in the bits of offset | |
2029 | mode and drop down to check the closing ']'. */ | |
2030 | prefixp->kind = PREFIX_BDAP_IMM; | |
2031 | } | |
2032 | else | |
2033 | /* Nothing valid here: lose. */ | |
2034 | return 0; | |
2035 | } | |
2036 | /* Seen "[rN" but no '+', so check if it's a '-'. */ | |
2037 | else if (**cPP == '-') | |
2038 | { | |
2039 | /* Yep, we must have offset mode. */ | |
2040 | if (! cris_get_expression (cPP, &prefixp->expr)) | |
2041 | /* No expression, so we lose. */ | |
2042 | return 0; | |
2043 | else | |
2044 | { | |
2045 | /* Expression found to make this offset mode, so | |
2046 | fill those bits and drop down to check the | |
2047 | closing ']'. */ | |
2048 | prefixp->kind = PREFIX_BDAP_IMM; | |
2049 | } | |
2050 | } | |
2051 | else | |
2052 | { | |
2053 | /* We've seen "[rN", but not '+' or '-'; rather a ']'. | |
2054 | Hmm. Normally this is a simple indirect mode that we | |
2055 | shouldn't match, but if we expect ']', then we have a | |
2056 | zero offset, so it can be a three-address-operand, | |
2057 | like "[rN],rO,rP", thus offset mode. | |
2058 | ||
2059 | Don't eat the ']', that will be done in the closing | |
2060 | ceremony. */ | |
2061 | prefixp->expr.X_op = O_constant; | |
2062 | prefixp->expr.X_add_number = 0; | |
2063 | prefixp->expr.X_add_symbol = NULL; | |
2064 | prefixp->expr.X_op_symbol = NULL; | |
2065 | prefixp->kind = PREFIX_BDAP_IMM; | |
2066 | } | |
2067 | } | |
2068 | /* A '[', but no second '[', and no register. Check if we | |
2069 | have an expression, making this "[I]" for a double-indirect | |
2070 | prefix. */ | |
2071 | else if (cris_get_expression (cPP, &prefixp->expr)) | |
2072 | { | |
2073 | /* Expression found, the so called absolute mode for a | |
2074 | double-indirect prefix on PC. */ | |
2075 | prefixp->kind = PREFIX_DIP; | |
2076 | prefixp->opcode = DIP_OPCODE | (AUTOINCR_BIT << 8) | REG_PC; | |
2077 | prefixp->reloc = BFD_RELOC_32; | |
2078 | } | |
2079 | else | |
2080 | /* Neither '[' nor register nor expression. We lose. */ | |
2081 | return 0; | |
3bcbcc3d HPN |
2082 | |
2083 | /* We get here as a closing ceremony to a successful match. We just | |
2084 | need to check the closing ']'. */ | |
2085 | if (**cPP != ']') | |
2086 | /* Oops. Close but no air-polluter. */ | |
2087 | return 0; | |
2088 | ||
2089 | /* Don't forget to consume that ']', before returning in glory. */ | |
2090 | (*cPP)++; | |
2091 | return 1; | |
2092 | } | |
2093 | ||
3bcbcc3d HPN |
2094 | /* Get an expression from the string pointed out by *cPP. |
2095 | The pointer *cPP is advanced to the character following the expression | |
2096 | on a success, or retains its original value otherwise. | |
2097 | ||
2098 | cPP Pointer to pointer to string beginning with the expression. | |
2099 | ||
2100 | exprP Pointer to structure containing the expression. | |
2101 | ||
47926f60 | 2102 | Return 1 iff a correct expression is found. */ |
3bcbcc3d HPN |
2103 | |
2104 | static int | |
2105 | cris_get_expression (cPP, exprP) | |
47926f60 KH |
2106 | char **cPP; |
2107 | expressionS *exprP; | |
3bcbcc3d HPN |
2108 | { |
2109 | char *saved_input_line_pointer; | |
2110 | segT exp; | |
2111 | ||
2112 | /* The "expression" function expects to find an expression at the | |
2113 | global variable input_line_pointer, so we have to save it to give | |
2114 | the impression that we don't fiddle with global variables. */ | |
2115 | saved_input_line_pointer = input_line_pointer; | |
2116 | input_line_pointer = *cPP; | |
2117 | ||
2118 | exp = expression (exprP); | |
2119 | if (exprP->X_op == O_illegal || exprP->X_op == O_absent) | |
2120 | { | |
2121 | input_line_pointer = saved_input_line_pointer; | |
2122 | return 0; | |
2123 | } | |
2124 | ||
2125 | /* Everything seems to be fine, just restore the global | |
2126 | input_line_pointer and say we're successful. */ | |
2127 | *cPP = input_line_pointer; | |
2128 | input_line_pointer = saved_input_line_pointer; | |
2129 | return 1; | |
2130 | } | |
2131 | ||
3bcbcc3d HPN |
2132 | /* Get a sequence of flag characters from *spp. The pointer *cPP is |
2133 | advanced to the character following the expression. The flag | |
2134 | characters are consecutive, no commas or spaces. | |
2135 | ||
2136 | cPP Pointer to pointer to string beginning with the expression. | |
2137 | ||
2138 | flagp Pointer to int to return the flags expression. | |
2139 | ||
2140 | Return 1 iff a correct flags expression is found. */ | |
2141 | ||
2142 | static int | |
2143 | get_flags (cPP, flagsp) | |
2144 | char **cPP; | |
2145 | int *flagsp; | |
2146 | { | |
2147 | for (;;) | |
2148 | { | |
2149 | switch (**cPP) | |
2150 | { | |
2151 | case 'd': | |
2152 | case 'D': | |
2153 | case 'm': | |
2154 | case 'M': | |
2155 | *flagsp |= 0x80; | |
2156 | break; | |
2157 | ||
2158 | case 'e': | |
2159 | case 'E': | |
2160 | case 'b': | |
2161 | case 'B': | |
2162 | *flagsp |= 0x40; | |
2163 | break; | |
2164 | ||
2165 | case 'i': | |
2166 | case 'I': | |
2167 | *flagsp |= 0x20; | |
2168 | break; | |
2169 | ||
2170 | case 'x': | |
2171 | case 'X': | |
2172 | *flagsp |= 0x10; | |
2173 | break; | |
2174 | ||
2175 | case 'n': | |
2176 | case 'N': | |
2177 | *flagsp |= 0x8; | |
2178 | break; | |
2179 | ||
2180 | case 'z': | |
2181 | case 'Z': | |
2182 | *flagsp |= 0x4; | |
2183 | break; | |
2184 | ||
2185 | case 'v': | |
2186 | case 'V': | |
2187 | *flagsp |= 0x2; | |
2188 | break; | |
2189 | ||
2190 | case 'c': | |
2191 | case 'C': | |
2192 | *flagsp |= 1; | |
2193 | break; | |
2194 | ||
2195 | default: | |
2196 | /* We consider this successful if we stop at a comma or | |
47926f60 | 2197 | whitespace. Anything else, and we consider it a failure. */ |
3bcbcc3d HPN |
2198 | if (**cPP != ',' |
2199 | && **cPP != 0 | |
2200 | && ! isspace (**cPP)) | |
2201 | return 0; | |
2202 | else | |
2203 | return 1; | |
2204 | } | |
2205 | ||
2206 | /* Don't forget to consume each flag character. */ | |
2207 | (*cPP)++; | |
2208 | } | |
2209 | } | |
2210 | ||
3bcbcc3d HPN |
2211 | /* Generate code and fixes for a BDAP prefix. |
2212 | ||
2213 | base_regno Int containing the base register number. | |
2214 | ||
2215 | exprP Pointer to structure containing the offset expression. */ | |
2216 | ||
2217 | static void | |
2218 | gen_bdap (base_regno, exprP) | |
47926f60 KH |
2219 | int base_regno; |
2220 | expressionS *exprP; | |
3bcbcc3d HPN |
2221 | { |
2222 | unsigned int opcode; | |
2223 | char *opcodep; | |
2224 | ||
2225 | /* Put out the prefix opcode; assume quick immediate mode at first. */ | |
2226 | opcode = BDAP_QUICK_OPCODE | (base_regno << 12); | |
2227 | opcodep = frag_more (2); | |
2228 | md_number_to_chars (opcodep, opcode, 2); | |
2229 | ||
2230 | if (exprP->X_op == O_constant) | |
2231 | { | |
2232 | /* We have an absolute expression that we know the size of right | |
47926f60 | 2233 | now. */ |
3bcbcc3d HPN |
2234 | long int value; |
2235 | int size; | |
2236 | ||
2237 | value = exprP->X_add_number; | |
2238 | if (value < -32768 || value > 32767) | |
2239 | /* Outside range for a "word", make it a dword. */ | |
2240 | size = 2; | |
2241 | else | |
47926f60 | 2242 | /* Assume "word" size. */ |
3bcbcc3d HPN |
2243 | size = 1; |
2244 | ||
2245 | /* If this is a signed-byte value, we can fit it into the prefix | |
2246 | insn itself. */ | |
2247 | if (value >= -128 && value <= 127) | |
2248 | opcodep[0] = value; | |
2249 | else | |
2250 | { | |
2251 | /* This is a word or dword displacement, which will be put in a | |
2252 | word or dword after the prefix. */ | |
2253 | char *p; | |
2254 | ||
2255 | opcodep[0] = BDAP_PC_LOW + (size << 4); | |
2256 | opcodep[1] &= 0xF0; | |
2257 | opcodep[1] |= BDAP_INCR_HIGH; | |
2258 | p = frag_more (1 << size); | |
2259 | md_number_to_chars (p, value, 1 << size); | |
2260 | } | |
2261 | } | |
2262 | else | |
2263 | /* The expression is not defined yet but may become absolute. We make | |
2264 | it a relocation to be relaxed. */ | |
47926f60 KH |
2265 | frag_var (rs_machine_dependent, 4, 0, |
2266 | ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF), | |
2267 | exprP->X_add_symbol, exprP->X_add_number, opcodep); | |
3bcbcc3d HPN |
2268 | } |
2269 | ||
3bcbcc3d HPN |
2270 | /* Encode a branch displacement in the range -256..254 into the form used |
2271 | by CRIS conditional branch instructions. | |
2272 | ||
2273 | offset The displacement value in bytes. */ | |
2274 | ||
2275 | static int | |
2276 | branch_disp (offset) | |
2277 | int offset; | |
2278 | { | |
2279 | int disp; | |
2280 | ||
2281 | disp = offset & 0xFE; | |
2282 | ||
2283 | if (offset < 0) | |
2284 | disp |= 1; | |
2285 | ||
2286 | return disp; | |
2287 | } | |
2288 | ||
3bcbcc3d HPN |
2289 | /* Generate code and fixes for a 32-bit conditional branch instruction |
2290 | created by "extending" an existing 8-bit branch instruction. | |
2291 | ||
2292 | opcodep Pointer to the word containing the original 8-bit branch | |
2293 | instruction. | |
2294 | ||
2295 | writep Pointer to "extension area" following the first instruction | |
2296 | word. | |
2297 | ||
2298 | fragP Pointer to the frag containing the instruction. | |
2299 | ||
2300 | add_symP, Parts of the destination address expression. | |
2301 | sub_symP, | |
2302 | add_num. */ | |
2303 | ||
2304 | static void | |
2305 | gen_cond_branch_32 (opcodep, writep, fragP, add_symP, sub_symP, add_num) | |
2306 | char *opcodep; | |
2307 | char *writep; | |
2308 | fragS *fragP; | |
2309 | symbolS *add_symP; | |
2310 | symbolS *sub_symP; | |
2311 | long int add_num; | |
2312 | { | |
2313 | if (warn_for_branch_expansion) | |
2314 | { | |
2315 | /* FIXME: Find out and change to as_warn_where. Add testcase. */ | |
2316 | as_warn (_("32-bit conditional branch generated")); | |
2317 | } | |
2318 | ||
2319 | /* Here, writep points to what will be opcodep + 2. First, we change | |
2320 | the actual branch in opcodep[0] and opcodep[1], so that in the | |
2321 | final insn, it will look like: | |
2322 | opcodep+10: Bcc .-6 | |
2323 | ||
2324 | This means we don't have to worry about changing the opcode or | |
2325 | messing with te delay-slot instruction. So, we move it to last in | |
2326 | the "extended" branch, and just change the displacement. Admittedly, | |
2327 | it's not the optimal extended construct, but we should get this | |
2328 | rarely enough that it shouldn't matter. */ | |
2329 | ||
47926f60 | 2330 | writep[8] = branch_disp (-2 - 6); |
3bcbcc3d HPN |
2331 | writep[9] = opcodep[1]; |
2332 | ||
2333 | /* Then, we change the branch to an unconditional branch over the | |
2334 | extended part, to the new location of the Bcc: | |
2335 | opcodep: BA .+10 | |
2336 | opcodep+2: NOP | |
2337 | ||
2338 | Note that these two writes are to currently different locations, | |
2339 | merged later. */ | |
2340 | ||
2341 | md_number_to_chars (opcodep, BA_QUICK_OPCODE + 8, 2); | |
2342 | md_number_to_chars (writep, NOP_OPCODE, 2); | |
2343 | ||
2344 | /* Then the extended thing, the 32-bit jump insn. | |
2345 | opcodep+4: JUMP [PC+] */ | |
2346 | ||
2347 | md_number_to_chars (writep + 2, JUMP_PC_INCR_OPCODE, 2); | |
2348 | ||
2349 | /* We have to fill in the actual value too. | |
2350 | opcodep+6: .DWORD | |
2351 | This is most probably an expression, but we can cope with an absolute | |
2352 | value too. FIXME: Testcase needed. */ | |
2353 | ||
2354 | if (add_symP == NULL && sub_symP == NULL) | |
2355 | /* An absolute address. */ | |
2356 | md_number_to_chars (writep + 4, add_num, 4); | |
2357 | else | |
2358 | { | |
47926f60 | 2359 | /* Not absolute, we have to make it a frag for later evaluation. */ |
3bcbcc3d HPN |
2360 | know (sub_symP == 0); |
2361 | ||
2362 | fix_new (fragP, writep + 4 - fragP->fr_literal, 4, add_symP, | |
2363 | add_num, 0, BFD_RELOC_32); | |
2364 | } | |
2365 | } | |
2366 | ||
3bcbcc3d HPN |
2367 | /* This *could* be: |
2368 | ||
47926f60 KH |
2369 | Turn a string in input_line_pointer into a floating point constant |
2370 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
2371 | of LITTLENUMS emitted is stored in *SIZEP. | |
3bcbcc3d HPN |
2372 | |
2373 | type A character from FLTCHARS that describes what kind of | |
2374 | floating-point number is wanted. | |
2375 | ||
2376 | litp A pointer to an array that the result should be stored in. | |
2377 | ||
2378 | sizep A pointer to an integer where the size of the result is stored. | |
2379 | ||
2380 | But we don't support floating point constants in assembly code *at all*, | |
2381 | since it's suboptimal and just opens up bug opportunities. GCC emits | |
2382 | the bit patterns as hex. All we could do here is to emit what GCC | |
2383 | would have done in the first place. *Nobody* writes floating-point | |
2384 | code as assembly code, but if they do, they should be able enough to | |
2385 | find out the correct bit patterns and use them. */ | |
2386 | ||
2387 | char * | |
2388 | md_atof (type, litp, sizep) | |
2389 | char type ATTRIBUTE_UNUSED; | |
2390 | char *litp ATTRIBUTE_UNUSED; | |
47926f60 | 2391 | int *sizep ATTRIBUTE_UNUSED; |
3bcbcc3d HPN |
2392 | { |
2393 | /* FIXME: Is this function mentioned in the internals.texi manual? If | |
2394 | not, add it. */ | |
2395 | return _("Bad call to md_atof () - floating point formats are not supported"); | |
2396 | } | |
2397 | ||
3bcbcc3d HPN |
2398 | /* Turn a number as a fixS * into a series of bytes that represents the |
2399 | number on the target machine. The purpose of this procedure is the | |
2400 | same as that of md_number_to_chars but this procedure is supposed to | |
2401 | handle general bit field fixes and machine-dependent fixups. | |
2402 | ||
2403 | bufp Pointer to an array where the result should be stored. | |
2404 | ||
2405 | val The value to store. | |
2406 | ||
2407 | n The number of bytes in "val" that should be stored. | |
2408 | ||
47926f60 | 2409 | fixP The fix to be applied to the bit field starting at bufp. */ |
3bcbcc3d HPN |
2410 | |
2411 | static void | |
2412 | cris_number_to_imm (bufp, val, n, fixP) | |
2413 | char *bufp; | |
2414 | long val; | |
2415 | int n; | |
2416 | fixS *fixP; | |
2417 | { | |
2418 | segT sym_seg; | |
2419 | ||
2420 | know (n <= 4); | |
2421 | know (fixP); | |
2422 | ||
2423 | /* We put the relative "vma" for the other segment for inter-segment | |
2424 | relocations in the object data to stay binary "compatible" (with an | |
2425 | uninteresting old version) for the relocation. | |
2426 | Maybe delete some day. */ | |
2427 | if (fixP->fx_addsy | |
2428 | && (sym_seg = S_GET_SEGMENT (fixP->fx_addsy)) != now_seg) | |
2429 | val += sym_seg->vma; | |
2430 | ||
2431 | switch (fixP->fx_r_type) | |
2432 | { | |
2433 | /* Ditto here, we put the addend into the object code as | |
2434 | well as the reloc addend. Keep it that way for now, to simplify | |
2435 | regression tests on the object file contents. FIXME: Seems | |
2436 | uninteresting now that we have a test suite. */ | |
2437 | ||
2438 | case BFD_RELOC_32: | |
2439 | /* No use having warnings here, since most hosts have a 32-bit type | |
2440 | for "long" (which will probably change soon, now that I wrote | |
2441 | this). */ | |
2442 | bufp[3] = (val >> 24) & 0xFF; | |
2443 | bufp[2] = (val >> 16) & 0xFF; | |
2444 | bufp[1] = (val >> 8) & 0xFF; | |
2445 | bufp[0] = val & 0xFF; | |
2446 | break; | |
2447 | ||
2448 | /* FIXME: The 16 and 8-bit cases should have a way to check | |
2449 | whether a signed or unsigned (or any signedness) number is | |
2450 | accepted. | |
2451 | FIXME: Does the as_bad calls find the line number by themselves, | |
2452 | or should we change them into as_bad_where? */ | |
2453 | ||
2454 | case BFD_RELOC_16: | |
2455 | if (val > 0xffff || val < -32768) | |
2456 | as_bad (_("Value not in 16 bit range: %ld"), val); | |
2457 | if (! fixP->fx_addsy) | |
2458 | { | |
2459 | bufp[1] = (val >> 8) & 0xFF; | |
2460 | bufp[0] = val & 0xFF; | |
2461 | } | |
2462 | break; | |
2463 | ||
2464 | case BFD_RELOC_8: | |
2465 | if (val > 255 || val < -128) | |
2466 | as_bad (_("Value not in 8 bit range: %ld"), val); | |
2467 | if (! fixP->fx_addsy) | |
2468 | bufp[0] = val & 0xFF; | |
2469 | break; | |
2470 | ||
2471 | case BFD_RELOC_CRIS_UNSIGNED_4: | |
2472 | if (val > 15 || val < 0) | |
2473 | as_bad (_("Value not in 4 bit unsigned range: %ld"), val); | |
2474 | if (! fixP->fx_addsy) | |
2475 | bufp[0] |= val & 0x0F; | |
2476 | break; | |
2477 | ||
2478 | case BFD_RELOC_CRIS_UNSIGNED_5: | |
2479 | if (val > 31 || val < 0) | |
2480 | as_bad (_("Value not in 5 bit unsigned range: %ld"), val); | |
2481 | if (! fixP->fx_addsy) | |
2482 | bufp[0] |= val & 0x1F; | |
2483 | break; | |
2484 | ||
2485 | case BFD_RELOC_CRIS_SIGNED_6: | |
2486 | if (val > 31 || val < -32) | |
2487 | as_bad (_("Value not in 6 bit range: %ld"), val); | |
2488 | if (! fixP->fx_addsy) | |
2489 | bufp[0] |= val & 0x3F; | |
2490 | break; | |
2491 | ||
2492 | case BFD_RELOC_CRIS_UNSIGNED_6: | |
2493 | if (val > 63 || val < 0) | |
2494 | as_bad (_("Value not in 6 bit unsigned range: %ld"), val); | |
2495 | if (! fixP->fx_addsy) | |
2496 | bufp[0] |= val & 0x3F; | |
2497 | break; | |
2498 | ||
2499 | case BFD_RELOC_CRIS_BDISP8: | |
2500 | if (! fixP->fx_addsy) | |
2501 | bufp[0] = branch_disp (val); | |
2502 | break; | |
2503 | ||
2504 | case BFD_RELOC_NONE: | |
2505 | /* May actually happen automatically. For example at broken | |
2506 | words, if the word turns out not to be broken. | |
47926f60 | 2507 | FIXME: When? Which testcase? */ |
3bcbcc3d HPN |
2508 | if (! fixP->fx_addsy) |
2509 | md_number_to_chars (bufp, val, n); | |
2510 | break; | |
2511 | ||
2512 | case BFD_RELOC_VTABLE_INHERIT: | |
2513 | /* This borrowed from tc-ppc.c on a whim. */ | |
2514 | if (fixP->fx_addsy | |
2515 | && !S_IS_DEFINED (fixP->fx_addsy) | |
2516 | && !S_IS_WEAK (fixP->fx_addsy)) | |
2517 | S_SET_WEAK (fixP->fx_addsy); | |
7b15d668 HPN |
2518 | /* Fall through. */ |
2519 | ||
3bcbcc3d | 2520 | case BFD_RELOC_VTABLE_ENTRY: |
3bcbcc3d HPN |
2521 | fixP->fx_done = 0; |
2522 | break; | |
2523 | ||
2524 | default: | |
2525 | BAD_CASE (fixP->fx_r_type); | |
2526 | } | |
2527 | } | |
2528 | ||
3bcbcc3d HPN |
2529 | /* Processes machine-dependent command line options. Called once for |
2530 | each option on the command line that the machine-independent part of | |
2531 | GAS does not understand. */ | |
47926f60 | 2532 | |
3bcbcc3d HPN |
2533 | int |
2534 | md_parse_option (arg, argp) | |
2535 | int arg; | |
2536 | char *argp ATTRIBUTE_UNUSED; | |
2537 | { | |
2538 | switch (arg) | |
2539 | { | |
2540 | case 'H': | |
2541 | case 'h': | |
7b15d668 | 2542 | printf (_("Please use --help to see usage and options for this assembler.\n")); |
3bcbcc3d | 2543 | md_show_usage (stdout); |
7b15d668 | 2544 | exit (EXIT_SUCCESS); |
3bcbcc3d HPN |
2545 | |
2546 | case 'N': | |
2547 | warn_for_branch_expansion = 1; | |
2548 | return 1; | |
2549 | ||
7b15d668 HPN |
2550 | case OPTION_NO_US: |
2551 | demand_register_prefix = true; | |
2552 | ||
2553 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
2554 | as_bad (_("--no-underscore is invalid with a.out format"), arg); | |
2555 | else | |
2556 | symbols_have_leading_underscore = false; | |
2557 | return 1; | |
2558 | ||
2559 | case OPTION_US: | |
2560 | demand_register_prefix = false; | |
2561 | symbols_have_leading_underscore = true; | |
2562 | return 1; | |
2563 | ||
3bcbcc3d HPN |
2564 | default: |
2565 | return 0; | |
47926f60 | 2566 | } |
3bcbcc3d HPN |
2567 | } |
2568 | ||
2569 | /* Round up a section size to the appropriate boundary. */ | |
2570 | valueT | |
2571 | md_section_align (segment, size) | |
2572 | segT segment; | |
2573 | valueT size; | |
2574 | { | |
2575 | /* Round all sects to multiple of 4, except the bss section, which | |
2576 | we'll round to word-size. | |
2577 | ||
2578 | FIXME: Check if this really matters. All sections should be | |
2579 | rounded up, and all sections should (optionally) be assumed to be | |
2580 | dword-aligned, it's just that there is actual usage of linking to a | |
2581 | multiple of two. */ | |
2582 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
2583 | { | |
2584 | if (segment == bss_section) | |
2585 | return (size + 1) & ~1; | |
2586 | return (size + 3) & ~3; | |
2587 | } | |
2588 | else | |
2589 | { | |
2590 | /* FIXME: Is this wanted? It matches the testsuite, but that's not | |
2591 | really a valid reason. */ | |
2592 | if (segment == text_section) | |
2593 | return (size + 3) & ~3; | |
2594 | } | |
2595 | ||
2596 | return size; | |
2597 | } | |
2598 | ||
3bcbcc3d HPN |
2599 | /* Generate a machine-dependent relocation. */ |
2600 | arelent * | |
2601 | tc_gen_reloc (section, fixP) | |
2602 | asection *section ATTRIBUTE_UNUSED; | |
2603 | fixS *fixP; | |
2604 | { | |
2605 | arelent *relP; | |
2606 | bfd_reloc_code_real_type code; | |
2607 | ||
2608 | switch (fixP->fx_r_type) | |
2609 | { | |
2610 | case BFD_RELOC_32: | |
2611 | case BFD_RELOC_16: | |
2612 | case BFD_RELOC_8: | |
2613 | case BFD_RELOC_VTABLE_INHERIT: | |
2614 | case BFD_RELOC_VTABLE_ENTRY: | |
2615 | code = fixP->fx_r_type; | |
2616 | break; | |
2617 | default: | |
2618 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2619 | _("Semantics error. This type of operand can not be relocated, it must be an assembly-time constant")); | |
2620 | return 0; | |
2621 | } | |
2622 | ||
2623 | relP = (arelent *) xmalloc (sizeof (arelent)); | |
2624 | assert (relP != 0); | |
2625 | relP->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
2626 | *relP->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); | |
2627 | relP->address = fixP->fx_frag->fr_address + fixP->fx_where; | |
2628 | ||
2629 | if (fixP->fx_pcrel) | |
47926f60 | 2630 | /* FIXME: Is this correct? */ |
3bcbcc3d HPN |
2631 | relP->addend = fixP->fx_addnumber; |
2632 | else | |
47926f60 | 2633 | /* At least *this one* is correct. */ |
3bcbcc3d HPN |
2634 | relP->addend = fixP->fx_offset; |
2635 | ||
2636 | /* This is the standard place for KLUDGEs to work around bugs in | |
2637 | bfd_install_relocation (first such note in the documentation | |
2638 | appears with binutils-2.8). | |
2639 | ||
2640 | That function bfd_install_relocation does the wrong thing with | |
2641 | putting stuff into the addend of a reloc (it should stay out) for a | |
2642 | weak symbol. The really bad thing is that it adds the | |
2643 | "segment-relative offset" of the symbol into the reloc. In this | |
2644 | case, the reloc should instead be relative to the symbol with no | |
2645 | other offset than the assembly code shows; and since the symbol is | |
2646 | weak, any local definition should be ignored until link time (or | |
2647 | thereafter). | |
2648 | To wit: weaksym+42 should be weaksym+42 in the reloc, | |
2649 | not weaksym+(offset_from_segment_of_local_weaksym_definition) | |
2650 | ||
2651 | To "work around" this, we subtract the segment-relative offset of | |
2652 | "known" weak symbols. This evens out the extra offset. | |
2653 | ||
2654 | That happens for a.out but not for ELF, since for ELF, | |
2655 | bfd_install_relocation uses the "special function" field of the | |
2656 | howto, and does not execute the code that needs to be undone. */ | |
2657 | ||
2658 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour | |
2659 | && fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy) | |
2660 | && ! bfd_is_und_section (S_GET_SEGMENT (fixP->fx_addsy))) | |
47926f60 KH |
2661 | { |
2662 | relP->addend -= S_GET_VALUE (fixP->fx_addsy); | |
2663 | } | |
3bcbcc3d HPN |
2664 | |
2665 | relP->howto = bfd_reloc_type_lookup (stdoutput, code); | |
2666 | if (! relP->howto) | |
2667 | { | |
2668 | const char *name; | |
2669 | ||
2670 | name = S_GET_NAME (fixP->fx_addsy); | |
2671 | if (name == NULL) | |
2672 | name = _("<unknown>"); | |
2673 | as_fatal (_("Cannot generate relocation type for symbol %s, code %s"), | |
2674 | name, bfd_get_reloc_code_name (code)); | |
2675 | } | |
2676 | ||
2677 | return relP; | |
2678 | } | |
2679 | ||
3bcbcc3d | 2680 | /* Machine-dependent usage-output. */ |
47926f60 | 2681 | |
3bcbcc3d HPN |
2682 | void |
2683 | md_show_usage (stream) | |
2684 | FILE *stream; | |
2685 | { | |
7b15d668 HPN |
2686 | fprintf (stream, _("CRIS-specific options:\n")); |
2687 | fprintf (stream, "%s", | |
2688 | _(" -h, -H Don't execute, print this help text. Deprecated.\n")); | |
2689 | fprintf (stream, "%s", | |
2690 | _(" -N Warn when branches are expanded to jumps.\n")); | |
2691 | fprintf (stream, "%s", | |
2692 | _(" --underscore User symbols are normally prepended with underscore.\n")); | |
2693 | fprintf (stream, "%s", | |
2694 | _(" Registers will not need any prefix.\n")); | |
2695 | fprintf (stream, "%s", | |
2696 | _(" --no-underscore User symbols do not have any prefix.\n")); | |
2697 | fprintf (stream, "%s", | |
2698 | _(" Registers will require a `$'-prefix.\n")); | |
3bcbcc3d HPN |
2699 | } |
2700 | ||
3bcbcc3d | 2701 | /* Apply a fixS (fixup of an instruction or data that we didn't have |
47926f60 | 2702 | enough info to complete immediately) to the data in a frag. */ |
3bcbcc3d HPN |
2703 | |
2704 | int | |
2705 | md_apply_fix (fixP, valP) | |
2706 | fixS *fixP; | |
2707 | valueT *valP; | |
2708 | { | |
2709 | long val = *valP; | |
2710 | ||
2711 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
2712 | ||
2713 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
2714 | fixP->fx_done = 1; | |
2715 | ||
2716 | if (fixP->fx_bit_fixP || fixP->fx_im_disp != 0) | |
2717 | { | |
2718 | as_bad_where (fixP->fx_file, fixP->fx_line, _("Invalid relocation")); | |
2719 | fixP->fx_done = 1; | |
2720 | } | |
2721 | else | |
47926f60 KH |
2722 | { |
2723 | /* I took this from tc-arc.c, since we used to not support | |
2724 | fx_subsy != NULL. I'm not totally sure it's TRT. */ | |
2725 | if (fixP->fx_subsy != (symbolS *) NULL) | |
2726 | { | |
2727 | if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section) | |
2728 | val -= S_GET_VALUE (fixP->fx_subsy); | |
2729 | else | |
2730 | { | |
2731 | /* We can't actually support subtracting a symbol. */ | |
2732 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2733 | _("expression too complex")); | |
2734 | } | |
2735 | } | |
2736 | ||
2737 | cris_number_to_imm (buf, val, fixP->fx_size, fixP); | |
2738 | } | |
3bcbcc3d HPN |
2739 | |
2740 | return 1; | |
2741 | } | |
2742 | ||
3bcbcc3d HPN |
2743 | /* All relocations are relative to the location just after the fixup; |
2744 | the address of the fixup plus its size. */ | |
2745 | ||
2746 | long | |
2747 | md_pcrel_from (fixP) | |
2748 | fixS *fixP; | |
2749 | { | |
2750 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
2751 | ||
2752 | /* FIXME: We get here only at the end of assembly, when X in ".-X" is | |
2753 | still unknown. Since we don't have pc-relative relocations, this | |
2754 | is invalid. What to do if anything for a.out, is to add | |
2755 | pc-relative relocations everywhere including the elinux program | |
2756 | loader. */ | |
2757 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2758 | _("Invalid pc-relative relocation")); | |
2759 | return fixP->fx_size + addr; | |
2760 | } | |
2761 | ||
47926f60 | 2762 | /* We have no need to give defaults for symbol-values. */ |
3bcbcc3d HPN |
2763 | symbolS * |
2764 | md_undefined_symbol (name) | |
2765 | char *name ATTRIBUTE_UNUSED; | |
2766 | { | |
2767 | return 0; | |
2768 | } | |
2769 | ||
3bcbcc3d HPN |
2770 | /* Definition of TC_FORCE_RELOCATION. |
2771 | FIXME: Unsure of this. Can we omit it? Just copied from tc-i386.c | |
2772 | when doing multi-object format with ELF, since it's the only other | |
2773 | multi-object-format target with a.out and ELF. */ | |
2774 | int | |
2775 | md_cris_force_relocation (fixp) | |
2776 | struct fix *fixp; | |
2777 | { | |
2778 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
2779 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
2780 | return 1; | |
2781 | return 0; | |
2782 | } | |
2783 | ||
2784 | /* Check and emit error if broken-word handling has failed to fix up a | |
2785 | case-table. This is called from write.c, after doing everything it | |
2786 | knows about how to handle broken words. */ | |
2787 | ||
2788 | void | |
2789 | tc_cris_check_adjusted_broken_word (new_offset, brokwP) | |
2790 | offsetT new_offset; | |
2791 | struct broken_word *brokwP; | |
2792 | { | |
2793 | if (new_offset > 32767 || new_offset < -32768) | |
47926f60 | 2794 | /* We really want a genuine error, not a warning, so make it one. */ |
3bcbcc3d HPN |
2795 | as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line, |
2796 | _("Adjusted signed .word (%ld) overflows: `switch'-statement too large."), | |
2797 | (long) new_offset); | |
2798 | } | |
2799 | ||
7b15d668 HPN |
2800 | /* Make a leading REGISTER_PREFIX_CHAR mandatory for all registers. */ |
2801 | ||
2802 | static void cris_force_reg_prefix () | |
2803 | { | |
2804 | demand_register_prefix = true; | |
2805 | } | |
2806 | ||
2807 | /* Do not demand a leading REGISTER_PREFIX_CHAR for all registers. */ | |
2808 | ||
2809 | static void cris_relax_reg_prefix () | |
2810 | { | |
2811 | demand_register_prefix = false; | |
2812 | } | |
2813 | ||
2814 | /* Adjust for having a leading '_' on all user symbols. */ | |
2815 | ||
2816 | static void cris_sym_leading_underscore () | |
2817 | { | |
2818 | /* We can't really do anything more than assert that what the program | |
2819 | thinks symbol starts with agrees with the command-line options, since | |
2820 | the bfd is already created. */ | |
2821 | ||
2822 | if (symbols_have_leading_underscore == false) | |
2823 | as_bad (".syntax %s requires command-line option `--underscore'", | |
2824 | SYNTAX_USER_SYM_LEADING_UNDERSCORE); | |
2825 | } | |
2826 | ||
2827 | /* Adjust for not having any particular prefix on user symbols. */ | |
2828 | ||
2829 | static void cris_sym_no_leading_underscore () | |
2830 | { | |
2831 | if (symbols_have_leading_underscore == true) | |
2832 | as_bad (".syntax %s requires command-line option `--no-underscore'", | |
2833 | SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE); | |
2834 | } | |
2835 | ||
2836 | /* Handle the .syntax pseudo, which takes an argument that decides what | |
2837 | syntax the assembly code has. */ | |
2838 | ||
2839 | static void | |
2840 | s_syntax (ignore) | |
2841 | int ignore ATTRIBUTE_UNUSED; | |
2842 | { | |
2843 | static const struct syntaxes | |
2844 | { | |
2845 | const char *operand; | |
2846 | void (*fn) PARAMS ((void)); | |
4a1805b1 | 2847 | } syntax_table[] = |
7b15d668 HPN |
2848 | {{SYNTAX_ENFORCE_REG_PREFIX, cris_force_reg_prefix}, |
2849 | {SYNTAX_RELAX_REG_PREFIX, cris_relax_reg_prefix}, | |
2850 | {SYNTAX_USER_SYM_LEADING_UNDERSCORE, cris_sym_leading_underscore}, | |
2851 | {SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE, cris_sym_no_leading_underscore}}; | |
2852 | ||
2853 | const struct syntaxes *sp; | |
2854 | ||
2855 | for (sp = syntax_table; | |
2856 | sp < syntax_table + sizeof (syntax_table) / sizeof (syntax_table[0]); | |
2857 | sp++) | |
2858 | { | |
2859 | if (strncmp (input_line_pointer, sp->operand, | |
2860 | strlen (sp->operand)) == 0) | |
2861 | { | |
bc805888 | 2862 | (sp->fn) (); |
7b15d668 HPN |
2863 | |
2864 | input_line_pointer += strlen (sp->operand); | |
2865 | demand_empty_rest_of_line (); | |
2866 | return; | |
2867 | } | |
2868 | } | |
2869 | ||
2870 | as_bad (_("Unknown .syntax operand")); | |
2871 | } | |
2872 | ||
fcdc20a4 HPN |
2873 | /* Wrapper for dwarf2_directive_file to emit error if this is seen when |
2874 | not emitting ELF. */ | |
2875 | ||
2876 | static void | |
2877 | s_cris_file (dummy) | |
2878 | int dummy; | |
2879 | { | |
2880 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2881 | as_bad ("Pseudodirective .file is only valid when generating ELF"); | |
2882 | else | |
2883 | dwarf2_directive_file (dummy); | |
2884 | } | |
2885 | ||
2886 | /* Wrapper for dwarf2_directive_loc to emit error if this is seen when not | |
2887 | emitting ELF. */ | |
2888 | ||
2889 | static void | |
2890 | s_cris_loc (dummy) | |
2891 | int dummy; | |
2892 | { | |
2893 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2894 | as_bad ("Pseudodirective .loc is only valid when generating ELF"); | |
2895 | else | |
2896 | dwarf2_directive_loc (dummy); | |
2897 | } | |
2898 | ||
3bcbcc3d HPN |
2899 | /* |
2900 | * Local variables: | |
2901 | * eval: (c-set-style "gnu") | |
2902 | * indent-tabs-mode: t | |
2903 | * End: | |
2904 | */ |