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3bcbcc3d | 1 | /* tc-cris.c -- Assembler code for the CRIS CPU core. |
4b95cf5c | 2 | Copyright (C) 2000-2014 Free Software Foundation, Inc. |
3bcbcc3d HPN |
3 | |
4 | Contributed by Axis Communications AB, Lund, Sweden. | |
5 | Originally written for GAS 1.38.1 by Mikael Asker. | |
08caf3f8 | 6 | Updates, BFDizing, GNUifying and ELF support by Hans-Peter Nilsson. |
3bcbcc3d HPN |
7 | |
8 | This file is part of GAS, the GNU Assembler. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
3bcbcc3d HPN |
13 | any later version. |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the | |
4b4da160 NC |
22 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
23 | MA 02110-1301, USA. */ | |
3bcbcc3d | 24 | |
3bcbcc3d | 25 | #include "as.h" |
3882b010 | 26 | #include "safe-ctype.h" |
3bcbcc3d HPN |
27 | #include "subsegs.h" |
28 | #include "opcode/cris.h" | |
fcdc20a4 | 29 | #include "dwarf2dbg.h" |
3bcbcc3d HPN |
30 | |
31 | /* Conventions used here: | |
32 | Generally speaking, pointers to binutils types such as "fragS" and | |
33 | "expressionS" get parameter and variable names ending in "P", such as | |
34 | "fragP", to harmonize with the rest of the binutils code. Other | |
35 | pointers get a "p" suffix, such as "bufp". Any function or type-name | |
36 | that could clash with a current or future binutils or GAS function get | |
37 | a "cris_" prefix. */ | |
38 | ||
7b15d668 HPN |
39 | #define SYNTAX_RELAX_REG_PREFIX "no_register_prefix" |
40 | #define SYNTAX_ENFORCE_REG_PREFIX "register_prefix" | |
41 | #define SYNTAX_USER_SYM_LEADING_UNDERSCORE "leading_underscore" | |
42 | #define SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE "no_leading_underscore" | |
43 | #define REGISTER_PREFIX_CHAR '$' | |
44 | ||
1c971160 HPN |
45 | /* True for expressions where getting X_add_symbol and X_add_number is |
46 | enough to get the "base" and "offset"; no need to make_expr_symbol. | |
47 | It's not enough to check if X_op_symbol is NULL; that misses unary | |
48 | operations like O_uminus. */ | |
49 | #define SIMPLE_EXPR(EXP) \ | |
50 | ((EXP)->X_op == O_constant || (EXP)->X_op == O_symbol) | |
51 | ||
08caf3f8 HPN |
52 | /* Like in ":GOT", ":GOTOFF" etc. Other ports use '@', but that's in |
53 | line_separator_chars for CRIS, so we avoid it. */ | |
cc99daad | 54 | #define RELOC_SUFFIX_CHAR ':' |
08caf3f8 | 55 | |
3bcbcc3d HPN |
56 | /* This might be CRIS_INSN_NONE if we're assembling a prefix-insn only. |
57 | Note that some prefix-insns might be assembled as CRIS_INSN_NORMAL. */ | |
58 | enum cris_insn_kind | |
59 | { | |
1048a9ba | 60 | CRIS_INSN_NORMAL, CRIS_INSN_NONE, CRIS_INSN_BRANCH, CRIS_INSN_MUL |
3bcbcc3d HPN |
61 | }; |
62 | ||
63 | /* An instruction will have one of these prefixes. | |
64 | Although the same bit-pattern, we handle BDAP with an immediate | |
65 | expression (eventually quick or [pc+]) different from when we only have | |
66 | register expressions. */ | |
67 | enum prefix_kind | |
68 | { | |
69 | PREFIX_NONE, PREFIX_BDAP_IMM, PREFIX_BDAP, PREFIX_BIAP, PREFIX_DIP, | |
70 | PREFIX_PUSH | |
71 | }; | |
72 | ||
73 | /* The prefix for an instruction. */ | |
74 | struct cris_prefix | |
75 | { | |
47926f60 KH |
76 | enum prefix_kind kind; |
77 | int base_reg_number; | |
78 | unsigned int opcode; | |
3bcbcc3d HPN |
79 | |
80 | /* There might be an expression to be evaluated, like I in [rN+I]. */ | |
47926f60 | 81 | expressionS expr; |
3bcbcc3d HPN |
82 | |
83 | /* If there's an expression, we might need a relocation. Here's the | |
84 | type of what relocation to start relaxaton with. | |
85 | The relocation is assumed to start immediately after the prefix insn, | |
86 | so we don't provide an offset. */ | |
87 | enum bfd_reloc_code_real reloc; | |
88 | }; | |
89 | ||
47926f60 | 90 | /* The description of the instruction being assembled. */ |
3bcbcc3d HPN |
91 | struct cris_instruction |
92 | { | |
93 | /* If CRIS_INSN_NONE, then this insn is of zero length. */ | |
47926f60 | 94 | enum cris_insn_kind insn_type; |
3bcbcc3d HPN |
95 | |
96 | /* If a special register was mentioned, this is its description, else | |
47926f60 | 97 | it is NULL. */ |
3bcbcc3d HPN |
98 | const struct cris_spec_reg *spec_reg; |
99 | ||
47926f60 | 100 | unsigned int opcode; |
3bcbcc3d HPN |
101 | |
102 | /* An insn may have at most one expression; theoretically there could be | |
47926f60 KH |
103 | another in its prefix (but I don't see how that could happen). */ |
104 | expressionS expr; | |
3bcbcc3d HPN |
105 | |
106 | /* The expression might need a relocation. Here's one to start | |
107 | relaxation with. */ | |
47926f60 | 108 | enum bfd_reloc_code_real reloc; |
3bcbcc3d | 109 | |
08caf3f8 | 110 | /* The size in bytes of an immediate expression, or zero if |
3bcbcc3d | 111 | nonapplicable. */ |
47926f60 | 112 | int imm_oprnd_size; |
3bcbcc3d HPN |
113 | }; |
114 | ||
ae57792d HPN |
115 | enum cris_archs |
116 | { | |
117 | arch_cris_unknown, | |
118 | arch_crisv0, arch_crisv3, arch_crisv8, arch_crisv10, | |
119 | arch_cris_any_v0_v10, arch_crisv32, arch_cris_common_v10_v32 | |
120 | }; | |
121 | ||
695a4822 HPN |
122 | static enum cris_archs cris_arch_from_string (char **); |
123 | static int cris_insn_ver_valid_for_arch (enum cris_insn_version_usage, | |
124 | enum cris_archs); | |
125 | ||
126 | static void cris_process_instruction (char *, struct cris_instruction *, | |
127 | struct cris_prefix *); | |
128 | static int get_bwd_size_modifier (char **, int *); | |
129 | static int get_bw_size_modifier (char **, int *); | |
130 | static int get_gen_reg (char **, int *); | |
131 | static int get_spec_reg (char **, const struct cris_spec_reg **); | |
132 | static int get_sup_reg (char **, int *); | |
133 | static int get_autoinc_prefix_or_indir_op (char **, struct cris_prefix *, | |
134 | int *, int *, int *, | |
135 | expressionS *); | |
136 | static int get_3op_or_dip_prefix_op (char **, struct cris_prefix *); | |
137 | static int cris_get_expression (char **, expressionS *); | |
138 | static int get_flags (char **, int *); | |
139 | static void gen_bdap (int, expressionS *); | |
140 | static int branch_disp (int); | |
141 | static void gen_cond_branch_32 (char *, char *, fragS *, symbolS *, symbolS *, | |
142 | long int); | |
143 | static void cris_number_to_imm (char *, long, int, fixS *, segT); | |
695a4822 HPN |
144 | static void s_syntax (int); |
145 | static void s_cris_file (int); | |
146 | static void s_cris_loc (int); | |
147 | static void s_cris_arch (int); | |
d2b52762 | 148 | static void s_cris_dtpoff (int); |
7b15d668 | 149 | |
08caf3f8 | 150 | /* Get ":GOT", ":GOTOFF", ":PLT" etc. suffixes. */ |
cc99daad HPN |
151 | static void cris_get_reloc_suffix (char **, bfd_reloc_code_real_type *, |
152 | expressionS *); | |
153 | static unsigned int cris_get_specified_reloc_size (bfd_reloc_code_real_type); | |
08caf3f8 | 154 | |
7b15d668 | 155 | /* All the .syntax functions. */ |
695a4822 HPN |
156 | static void cris_force_reg_prefix (void); |
157 | static void cris_relax_reg_prefix (void); | |
158 | static void cris_sym_leading_underscore (void); | |
159 | static void cris_sym_no_leading_underscore (void); | |
160 | static char *cris_insn_first_word_frag (void); | |
7b15d668 | 161 | |
3bcbcc3d HPN |
162 | /* Handle to the opcode hash table. */ |
163 | static struct hash_control *op_hash = NULL; | |
164 | ||
399f703e HPN |
165 | /* If we target cris-axis-linux-gnu (as opposed to generic cris-axis-elf), |
166 | we default to no underscore and required register-prefixes. The | |
167 | difference is in the default values. */ | |
168 | #ifdef TE_LINUX | |
169 | #define DEFAULT_CRIS_AXIS_LINUX_GNU TRUE | |
170 | #else | |
171 | #define DEFAULT_CRIS_AXIS_LINUX_GNU FALSE | |
172 | #endif | |
173 | ||
7b15d668 | 174 | /* Whether we demand that registers have a `$' prefix. Default here. */ |
399f703e | 175 | static bfd_boolean demand_register_prefix = DEFAULT_CRIS_AXIS_LINUX_GNU; |
7b15d668 HPN |
176 | |
177 | /* Whether global user symbols have a leading underscore. Default here. */ | |
399f703e HPN |
178 | static bfd_boolean symbols_have_leading_underscore |
179 | = !DEFAULT_CRIS_AXIS_LINUX_GNU; | |
7b15d668 | 180 | |
08caf3f8 | 181 | /* Whether or not we allow PIC, and expand to PIC-friendly constructs. */ |
b34976b6 | 182 | static bfd_boolean pic = FALSE; |
08caf3f8 | 183 | |
cc99daad HPN |
184 | /* Whether or not we allow TLS suffixes. For the moment, we always do. */ |
185 | static const bfd_boolean tls = TRUE; | |
186 | ||
ae57792d HPN |
187 | /* If we're configured for "cris", default to allow all v0..v10 |
188 | instructions and register names. */ | |
189 | #ifndef DEFAULT_CRIS_ARCH | |
190 | #define DEFAULT_CRIS_ARCH cris_any_v0_v10 | |
191 | #endif | |
192 | ||
193 | /* No whitespace in the CONCAT2 parameter list. */ | |
194 | static enum cris_archs cris_arch = XCONCAT2 (arch_,DEFAULT_CRIS_ARCH); | |
195 | ||
3bcbcc3d HPN |
196 | const pseudo_typeS md_pseudo_table[] = |
197 | { | |
198 | {"dword", cons, 4}, | |
d2b52762 | 199 | {"dtpoffd", s_cris_dtpoff, 4}, |
7b15d668 | 200 | {"syntax", s_syntax, 0}, |
fcdc20a4 HPN |
201 | {"file", s_cris_file, 0}, |
202 | {"loc", s_cris_loc, 0}, | |
ae57792d | 203 | {"arch", s_cris_arch, 0}, |
3bcbcc3d HPN |
204 | {NULL, 0, 0} |
205 | }; | |
206 | ||
207 | static int warn_for_branch_expansion = 0; | |
208 | ||
1048a9ba HPN |
209 | /* Whether to emit error when a MULS/MULU could be located last on a |
210 | cache-line. */ | |
ae57792d HPN |
211 | static int err_for_dangerous_mul_placement |
212 | = (XCONCAT2 (arch_,DEFAULT_CRIS_ARCH) != arch_crisv32); | |
1048a9ba | 213 | |
3bcbcc3d HPN |
214 | const char cris_comment_chars[] = ";"; |
215 | ||
216 | /* This array holds the chars that only start a comment at the beginning of | |
217 | a line. If the line seems to have the form '# 123 filename' | |
47926f60 | 218 | .line and .file directives will appear in the pre-processed output. */ |
3bcbcc3d HPN |
219 | /* Note that input_file.c hand-checks for '#' at the beginning of the |
220 | first line of the input file. This is because the compiler outputs | |
47926f60 KH |
221 | #NO_APP at the beginning of its output. */ |
222 | /* Also note that slash-star will always start a comment. */ | |
3bcbcc3d HPN |
223 | const char line_comment_chars[] = "#"; |
224 | const char line_separator_chars[] = "@"; | |
225 | ||
226 | /* Now all floating point support is shut off. See md_atof. */ | |
227 | const char EXP_CHARS[] = ""; | |
228 | const char FLT_CHARS[] = ""; | |
229 | ||
3bcbcc3d HPN |
230 | /* For CRIS, we encode the relax_substateTs (in e.g. fr_substate) as: |
231 | 2 1 0 | |
232 | ---/ /--+-----------------+-----------------+-----------------+ | |
233 | | what state ? | how long ? | | |
234 | ---/ /--+-----------------+-----------------+-----------------+ | |
235 | ||
236 | The "how long" bits are 00 = byte, 01 = word, 10 = dword (long). | |
3bcbcc3d HPN |
237 | Not all lengths are legit for a given value of (what state). |
238 | ||
239 | Groups for CRIS address relaxing: | |
240 | ||
ae57792d | 241 | 1. Bcc (pre-V32) |
3bcbcc3d HPN |
242 | length: byte, word, 10-byte expansion |
243 | ||
244 | 2. BDAP | |
1048a9ba HPN |
245 | length: byte, word, dword |
246 | ||
247 | 3. MULS/MULU | |
248 | Not really a relaxation (no infrastructure to get delay-slots | |
249 | right), just an alignment and placement checker for the v10 | |
ae57792d HPN |
250 | multiply/cache-bug. |
251 | ||
252 | 4. Bcc (V32 and later) | |
253 | length: byte, word, 14-byte expansion | |
254 | ||
255 | 5. Bcc (V10+V32) | |
256 | length: byte, word, error | |
257 | ||
258 | 6. BA (V32) | |
259 | length: byte, word, dword | |
3bcbcc3d | 260 | |
ae57792d HPN |
261 | 7. LAPC (V32) |
262 | length: byte, dword | |
263 | */ | |
264 | ||
265 | #define STATE_COND_BRANCH (1) | |
3bcbcc3d | 266 | #define STATE_BASE_PLUS_DISP_PREFIX (2) |
1048a9ba | 267 | #define STATE_MUL (3) |
ae57792d HPN |
268 | #define STATE_COND_BRANCH_V32 (4) |
269 | #define STATE_COND_BRANCH_COMMON (5) | |
270 | #define STATE_ABS_BRANCH_V32 (6) | |
271 | #define STATE_LAPC (7) | |
d2aa3f9f | 272 | #define STATE_COND_BRANCH_PIC (8) |
3bcbcc3d HPN |
273 | |
274 | #define STATE_LENGTH_MASK (3) | |
275 | #define STATE_BYTE (0) | |
276 | #define STATE_WORD (1) | |
277 | #define STATE_DWORD (2) | |
278 | /* Symbol undefined. */ | |
279 | #define STATE_UNDF (3) | |
280 | #define STATE_MAX_LENGTH (3) | |
281 | ||
2d2255b5 | 282 | /* These displacements are relative to the address following the opcode |
3bcbcc3d HPN |
283 | word of the instruction. The first letter is Byte, Word. The 2nd |
284 | letter is Forward, Backward. */ | |
285 | ||
286 | #define BRANCH_BF ( 254) | |
287 | #define BRANCH_BB (-256) | |
ae57792d HPN |
288 | #define BRANCH_BF_V32 ( 252) |
289 | #define BRANCH_BB_V32 (-258) | |
47926f60 KH |
290 | #define BRANCH_WF (2 + 32767) |
291 | #define BRANCH_WB (2 + -32768) | |
ae57792d HPN |
292 | #define BRANCH_WF_V32 (-2 + 32767) |
293 | #define BRANCH_WB_V32 (-2 + -32768) | |
3bcbcc3d HPN |
294 | |
295 | #define BDAP_BF ( 127) | |
296 | #define BDAP_BB (-128) | |
297 | #define BDAP_WF ( 32767) | |
298 | #define BDAP_WB (-32768) | |
299 | ||
300 | #define ENCODE_RELAX(what, length) (((what) << 2) + (length)) | |
301 | ||
302 | const relax_typeS md_cris_relax_table[] = | |
303 | { | |
304 | /* Error sentinel (0, 0). */ | |
305 | {1, 1, 0, 0}, | |
306 | ||
307 | /* Unused (0, 1). */ | |
308 | {1, 1, 0, 0}, | |
309 | ||
310 | /* Unused (0, 2). */ | |
311 | {1, 1, 0, 0}, | |
312 | ||
313 | /* Unused (0, 3). */ | |
314 | {1, 1, 0, 0}, | |
315 | ||
316 | /* Bcc o (1, 0). */ | |
317 | {BRANCH_BF, BRANCH_BB, 0, ENCODE_RELAX (1, 1)}, | |
318 | ||
47926f60 | 319 | /* Bcc [PC+] (1, 1). */ |
3bcbcc3d HPN |
320 | {BRANCH_WF, BRANCH_WB, 2, ENCODE_RELAX (1, 2)}, |
321 | ||
322 | /* BEXT/BWF, BA, JUMP (external), JUMP (always), Bnot_cc, JUMP (default) | |
323 | (1, 2). */ | |
324 | {0, 0, 10, 0}, | |
325 | ||
326 | /* Unused (1, 3). */ | |
327 | {1, 1, 0, 0}, | |
328 | ||
329 | /* BDAP o (2, 0). */ | |
330 | {BDAP_BF, BDAP_BB, 0, ENCODE_RELAX (2, 1)}, | |
331 | ||
332 | /* BDAP.[bw] [PC+] (2, 1). */ | |
333 | {BDAP_WF, BDAP_WB, 2, ENCODE_RELAX (2, 2)}, | |
334 | ||
335 | /* BDAP.d [PC+] (2, 2). */ | |
1048a9ba HPN |
336 | {0, 0, 4, 0}, |
337 | ||
338 | /* Unused (2, 3). */ | |
ae57792d | 339 | {1, 1, 0, 0}, |
1048a9ba HPN |
340 | |
341 | /* MULS/MULU (3, 0). Positions (3, 1..3) are unused. */ | |
ae57792d HPN |
342 | {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, |
343 | ||
344 | /* V32: Bcc o (4, 0). */ | |
345 | {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (4, 1)}, | |
346 | ||
347 | /* V32: Bcc [PC+] (4, 1). */ | |
348 | {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (4, 2)}, | |
349 | ||
350 | /* V32: BA .+12; NOP; BA32 target; NOP; Bcc .-6 (4, 2). */ | |
351 | {0, 0, 12, 0}, | |
352 | ||
353 | /* Unused (4, 3). */ | |
354 | {1, 1, 0, 0}, | |
355 | ||
356 | /* COMMON: Bcc o (5, 0). The offsets are calculated as for v32. Code | |
357 | should contain two nop insns (or four if offset size is large or | |
358 | unknown) after every label. */ | |
359 | {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (5, 1)}, | |
360 | ||
361 | /* COMMON: Bcc [PC+] (5, 1). */ | |
362 | {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (5, 2)}, | |
363 | ||
364 | /* COMMON: FIXME: ???. Treat as error currently. */ | |
365 | {0, 0, 12, 0}, | |
366 | ||
367 | /* Unused (5, 3). */ | |
368 | {1, 1, 0, 0}, | |
369 | ||
370 | /* V32: BA o (6, 0). */ | |
371 | {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (6, 1)}, | |
372 | ||
373 | /* V32: BA.W (6, 1). */ | |
374 | {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (6, 2)}, | |
375 | ||
376 | /* V32: BA.D (6, 2). */ | |
377 | {0, 0, 4, 0}, | |
378 | ||
379 | /* Unused (6, 3). */ | |
380 | {1, 1, 0, 0}, | |
381 | ||
382 | /* LAPC: LAPCQ .+0..15*2,Rn (7, 0). */ | |
383 | {14*2, -1*2, 0, ENCODE_RELAX (7, 2)}, | |
384 | ||
385 | /* Unused (7, 1). | |
386 | While there's a shorter sequence, e.g. LAPCQ + an ADDQ or SUBQ, | |
387 | that would affect flags, so we can't do that as it wouldn't be a | |
388 | proper insn expansion of LAPCQ. This row is associated with a | |
389 | 2-byte expansion, so it's unused rather than the next. */ | |
390 | {1, 1, 0, 0}, | |
391 | ||
392 | /* LAPC: LAPC.D (7, 2). */ | |
393 | {0, 0, 4, 0}, | |
394 | ||
395 | /* Unused (7, 3). */ | |
d2aa3f9f HPN |
396 | {1, 1, 0, 0}, |
397 | ||
398 | /* PIC for pre-v32: Bcc o (8, 0). */ | |
399 | {BRANCH_BF, BRANCH_BB, 0, ENCODE_RELAX (STATE_COND_BRANCH_PIC, 1)}, | |
400 | ||
401 | /* Bcc [PC+] (8, 1). */ | |
402 | {BRANCH_WF, BRANCH_WB, 2, ENCODE_RELAX (STATE_COND_BRANCH_PIC, 2)}, | |
403 | ||
404 | /* 32-bit expansion, PIC (8, 2). */ | |
405 | {0, 0, 12, 0}, | |
406 | ||
407 | /* Unused (8, 3). */ | |
ae57792d | 408 | {1, 1, 0, 0} |
3bcbcc3d HPN |
409 | }; |
410 | ||
3bcbcc3d HPN |
411 | #undef BDAP_BF |
412 | #undef BDAP_BB | |
413 | #undef BDAP_WF | |
414 | #undef BDAP_WB | |
415 | ||
ae57792d | 416 | /* Target-specific multicharacter options, not const-declared. */ |
3bcbcc3d HPN |
417 | struct option md_longopts[] = |
418 | { | |
7b15d668 HPN |
419 | #define OPTION_NO_US (OPTION_MD_BASE + 0) |
420 | {"no-underscore", no_argument, NULL, OPTION_NO_US}, | |
421 | #define OPTION_US (OPTION_MD_BASE + 1) | |
422 | {"underscore", no_argument, NULL, OPTION_US}, | |
ae57792d | 423 | #define OPTION_PIC (OPTION_US + 1) |
08caf3f8 | 424 | {"pic", no_argument, NULL, OPTION_PIC}, |
ae57792d | 425 | #define OPTION_MULBUG_ABORT_ON (OPTION_PIC + 1) |
1048a9ba | 426 | {"mul-bug-abort", no_argument, NULL, OPTION_MULBUG_ABORT_ON}, |
ae57792d | 427 | #define OPTION_MULBUG_ABORT_OFF (OPTION_MULBUG_ABORT_ON + 1) |
1048a9ba | 428 | {"no-mul-bug-abort", no_argument, NULL, OPTION_MULBUG_ABORT_OFF}, |
ae57792d HPN |
429 | #define OPTION_ARCH (OPTION_MULBUG_ABORT_OFF + 1) |
430 | {"march", required_argument, NULL, OPTION_ARCH}, | |
3bcbcc3d HPN |
431 | {NULL, no_argument, NULL, 0} |
432 | }; | |
433 | ||
ae57792d | 434 | /* Not const-declared. */ |
3bcbcc3d HPN |
435 | size_t md_longopts_size = sizeof (md_longopts); |
436 | const char *md_shortopts = "hHN"; | |
437 | ||
3bcbcc3d HPN |
438 | /* At first glance, this may seems wrong and should be 4 (ba + nop); but |
439 | since a short_jump must skip a *number* of long jumps, it must also be | |
440 | a long jump. Here, we hope to make it a "ba [16bit_offs]" and a "nop" | |
441 | for the delay slot and hope that the jump table at most needs | |
442 | 32767/4=8191 long-jumps. A branch is better than a jump, since it is | |
443 | relative; we will not have a reloc to fix up somewhere. | |
444 | ||
445 | Note that we can't add relocs, because relaxation uses these fixed | |
446 | numbers, and md_create_short_jump is called after relaxation. */ | |
447 | ||
2b4f075a | 448 | int md_short_jump_size = 6; |
ae57792d | 449 | |
d2aa3f9f HPN |
450 | /* The v32 version has a delay-slot, hence two bytes longer. |
451 | The pre-v32 PIC version uses a prefixed insn. */ | |
ae57792d | 452 | #define cris_any_v0_v10_long_jump_size 6 |
d2aa3f9f | 453 | #define cris_any_v0_v10_long_jump_size_pic 8 |
ae57792d HPN |
454 | #define crisv32_long_jump_size 8 |
455 | ||
456 | int md_long_jump_size = XCONCAT2 (DEFAULT_CRIS_ARCH,_long_jump_size); | |
3bcbcc3d | 457 | |
7b15d668 | 458 | /* Report output format. Small changes in output format (like elf |
08caf3f8 HPN |
459 | variants below) can happen until all options are parsed, but after |
460 | that, the output format must remain fixed. */ | |
47926f60 | 461 | |
3bcbcc3d | 462 | const char * |
695a4822 | 463 | cris_target_format (void) |
3bcbcc3d HPN |
464 | { |
465 | switch (OUTPUT_FLAVOR) | |
466 | { | |
467 | case bfd_target_aout_flavour: | |
468 | return "a.out-cris"; | |
469 | ||
470 | case bfd_target_elf_flavour: | |
7b15d668 HPN |
471 | if (symbols_have_leading_underscore) |
472 | return "elf32-us-cris"; | |
3bcbcc3d HPN |
473 | return "elf32-cris"; |
474 | ||
475 | default: | |
476 | abort (); | |
477 | return NULL; | |
478 | } | |
479 | } | |
480 | ||
ae57792d HPN |
481 | /* Return a bfd_mach_cris... value corresponding to the value of |
482 | cris_arch. */ | |
483 | ||
484 | unsigned int | |
695a4822 | 485 | cris_mach (void) |
ae57792d HPN |
486 | { |
487 | unsigned int retval = 0; | |
488 | ||
489 | switch (cris_arch) | |
490 | { | |
491 | case arch_cris_common_v10_v32: | |
492 | retval = bfd_mach_cris_v10_v32; | |
493 | break; | |
494 | ||
495 | case arch_crisv32: | |
496 | retval = bfd_mach_cris_v32; | |
497 | break; | |
498 | ||
499 | case arch_crisv10: | |
500 | case arch_cris_any_v0_v10: | |
501 | retval = bfd_mach_cris_v0_v10; | |
502 | break; | |
503 | ||
504 | default: | |
505 | BAD_CASE (cris_arch); | |
506 | } | |
507 | ||
508 | return retval; | |
509 | } | |
510 | ||
1c971160 HPN |
511 | /* We need a port-specific relaxation function to cope with sym2 - sym1 |
512 | relative expressions with both symbols in the same segment (but not | |
513 | necessarily in the same frag as this insn), for example: | |
514 | move.d [pc+sym2-(sym1-2)],r10 | |
515 | sym1: | |
516 | The offset can be 8, 16 or 32 bits long. */ | |
517 | ||
518 | long | |
695a4822 HPN |
519 | cris_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS *fragP, |
520 | long stretch ATTRIBUTE_UNUSED) | |
1c971160 HPN |
521 | { |
522 | long growth; | |
523 | offsetT aim = 0; | |
524 | symbolS *symbolP; | |
525 | const relax_typeS *this_type; | |
526 | const relax_typeS *start_type; | |
527 | relax_substateT next_state; | |
528 | relax_substateT this_state; | |
529 | const relax_typeS *table = TC_GENERIC_RELAX_TABLE; | |
530 | ||
531 | /* We only have to cope with frags as prepared by | |
fb2fd3e1 | 532 | md_estimate_size_before_relax. The dword cases may get here |
1c971160 HPN |
533 | because of the different reasons that they aren't relaxable. */ |
534 | switch (fragP->fr_subtype) | |
535 | { | |
f6ce267c | 536 | case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD): |
ae57792d HPN |
537 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD): |
538 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD): | |
539 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD): | |
540 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD): | |
541 | case ENCODE_RELAX (STATE_LAPC, STATE_DWORD): | |
1c971160 HPN |
542 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): |
543 | /* When we get to these states, the frag won't grow any more. */ | |
544 | return 0; | |
545 | ||
546 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): | |
547 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): | |
548 | if (fragP->fr_symbol == NULL | |
549 | || S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) | |
550 | as_fatal (_("internal inconsistency problem in %s: fr_symbol %lx"), | |
551 | __FUNCTION__, (long) fragP->fr_symbol); | |
552 | symbolP = fragP->fr_symbol; | |
553 | if (symbol_resolved_p (symbolP)) | |
554 | as_fatal (_("internal inconsistency problem in %s: resolved symbol"), | |
555 | __FUNCTION__); | |
556 | aim = S_GET_VALUE (symbolP); | |
557 | break; | |
558 | ||
1048a9ba HPN |
559 | case ENCODE_RELAX (STATE_MUL, STATE_BYTE): |
560 | /* Nothing to do here. */ | |
561 | return 0; | |
562 | ||
1c971160 HPN |
563 | default: |
564 | as_fatal (_("internal inconsistency problem in %s: fr_subtype %d"), | |
565 | __FUNCTION__, fragP->fr_subtype); | |
566 | } | |
567 | ||
568 | /* The rest is stolen from relax_frag. There's no obvious way to | |
569 | share the code, but fortunately no requirement to keep in sync as | |
570 | long as fragP->fr_symbol does not have its segment changed. */ | |
571 | ||
572 | this_state = fragP->fr_subtype; | |
573 | start_type = this_type = table + this_state; | |
574 | ||
575 | if (aim < 0) | |
576 | { | |
577 | /* Look backwards. */ | |
578 | for (next_state = this_type->rlx_more; next_state;) | |
579 | if (aim >= this_type->rlx_backward) | |
580 | next_state = 0; | |
581 | else | |
582 | { | |
583 | /* Grow to next state. */ | |
584 | this_state = next_state; | |
585 | this_type = table + this_state; | |
586 | next_state = this_type->rlx_more; | |
587 | } | |
588 | } | |
589 | else | |
590 | { | |
591 | /* Look forwards. */ | |
592 | for (next_state = this_type->rlx_more; next_state;) | |
593 | if (aim <= this_type->rlx_forward) | |
594 | next_state = 0; | |
595 | else | |
596 | { | |
597 | /* Grow to next state. */ | |
598 | this_state = next_state; | |
599 | this_type = table + this_state; | |
600 | next_state = this_type->rlx_more; | |
601 | } | |
602 | } | |
603 | ||
604 | growth = this_type->rlx_length - start_type->rlx_length; | |
605 | if (growth != 0) | |
606 | fragP->fr_subtype = this_state; | |
607 | return growth; | |
608 | } | |
609 | ||
3bcbcc3d HPN |
610 | /* Prepare machine-dependent frags for relaxation. |
611 | ||
612 | Called just before relaxation starts. Any symbol that is now undefined | |
613 | will not become defined. | |
614 | ||
615 | Return the correct fr_subtype in the frag. | |
616 | ||
617 | Return the initial "guess for fr_var" to caller. The guess for fr_var | |
618 | is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix | |
619 | or fr_var contributes to our returned value. | |
620 | ||
621 | Although it may not be explicit in the frag, pretend | |
47926f60 | 622 | fr_var starts with a value. */ |
3bcbcc3d HPN |
623 | |
624 | int | |
695a4822 | 625 | md_estimate_size_before_relax (fragS *fragP, segT segment_type) |
3bcbcc3d | 626 | { |
47926f60 | 627 | int old_fr_fix; |
ae57792d HPN |
628 | symbolS *symbolP = fragP->fr_symbol; |
629 | ||
630 | #define HANDLE_RELAXABLE(state) \ | |
631 | case ENCODE_RELAX (state, STATE_UNDF): \ | |
632 | if (symbolP != NULL \ | |
633 | && S_GET_SEGMENT (symbolP) == segment_type \ | |
634 | && !S_IS_WEAK (symbolP)) \ | |
635 | /* The symbol lies in the same segment - a relaxable \ | |
636 | case. */ \ | |
637 | fragP->fr_subtype \ | |
638 | = ENCODE_RELAX (state, STATE_BYTE); \ | |
639 | else \ | |
640 | /* Unknown or not the same segment, so not relaxable. */ \ | |
641 | fragP->fr_subtype \ | |
642 | = ENCODE_RELAX (state, STATE_DWORD); \ | |
643 | fragP->fr_var \ | |
644 | = md_cris_relax_table[fragP->fr_subtype].rlx_length; \ | |
645 | break | |
3bcbcc3d HPN |
646 | |
647 | old_fr_fix = fragP->fr_fix; | |
648 | ||
649 | switch (fragP->fr_subtype) | |
650 | { | |
ae57792d HPN |
651 | HANDLE_RELAXABLE (STATE_COND_BRANCH); |
652 | HANDLE_RELAXABLE (STATE_COND_BRANCH_V32); | |
653 | HANDLE_RELAXABLE (STATE_COND_BRANCH_COMMON); | |
d2aa3f9f | 654 | HANDLE_RELAXABLE (STATE_COND_BRANCH_PIC); |
ae57792d HPN |
655 | HANDLE_RELAXABLE (STATE_ABS_BRANCH_V32); |
656 | ||
657 | case ENCODE_RELAX (STATE_LAPC, STATE_UNDF): | |
658 | if (symbolP != NULL | |
659 | && S_GET_SEGMENT (symbolP) == segment_type | |
660 | && !S_IS_WEAK (symbolP)) | |
661 | { | |
662 | /* The symbol lies in the same segment - a relaxable case. | |
663 | Check if we currently have an odd offset; we can't code | |
664 | that into the instruction. Relaxing presumably only cause | |
665 | multiple-of-two changes, so we should only need to adjust | |
666 | for that here. */ | |
667 | bfd_vma target_address | |
668 | = (symbolP | |
669 | ? S_GET_VALUE (symbolP) | |
670 | : 0) + fragP->fr_offset; | |
671 | bfd_vma var_part_offset = fragP->fr_fix; | |
672 | bfd_vma address_of_var_part = fragP->fr_address + var_part_offset; | |
673 | long offset = target_address - (address_of_var_part - 2); | |
674 | ||
675 | fragP->fr_subtype | |
676 | = (offset & 1) | |
677 | ? ENCODE_RELAX (STATE_LAPC, STATE_DWORD) | |
678 | : ENCODE_RELAX (STATE_LAPC, STATE_BYTE); | |
679 | } | |
3bcbcc3d | 680 | else |
c335d394 HPN |
681 | /* Unknown or not the same segment, so not relaxable. */ |
682 | fragP->fr_subtype | |
ae57792d HPN |
683 | = ENCODE_RELAX (STATE_LAPC, STATE_DWORD); |
684 | fragP->fr_var | |
685 | = md_cris_relax_table[fragP->fr_subtype].rlx_length; | |
3bcbcc3d HPN |
686 | break; |
687 | ||
688 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF): | |
689 | /* Note that we can not do anything sane with relaxing | |
690 | [rX + a_known_symbol_in_text], it will have to be a 32-bit | |
691 | value. | |
692 | ||
693 | We could play tricks with managing a constant pool and make | |
08caf3f8 HPN |
694 | a_known_symbol_in_text a "bdap [pc + offset]" pointing there |
695 | (like the GOT for ELF shared libraries), but that's no use, it | |
696 | would in general be no shorter or faster code, only more | |
697 | complicated. */ | |
3bcbcc3d | 698 | |
ae57792d | 699 | if (S_GET_SEGMENT (symbolP) != absolute_section) |
3bcbcc3d HPN |
700 | { |
701 | /* Go for dword if not absolute or same segment. */ | |
702 | fragP->fr_subtype | |
703 | = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD); | |
c335d394 | 704 | fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; |
3bcbcc3d | 705 | } |
1c971160 HPN |
706 | else if (!symbol_resolved_p (fragP->fr_symbol)) |
707 | { | |
708 | /* The symbol will eventually be completely resolved as an | |
709 | absolute expression, but right now it depends on the result | |
710 | of relaxation and we don't know anything else about the | |
711 | value. We start relaxation with the assumption that it'll | |
712 | fit in a byte. */ | |
713 | fragP->fr_subtype | |
714 | = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE); | |
715 | fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; | |
716 | } | |
3bcbcc3d HPN |
717 | else |
718 | { | |
719 | /* Absolute expression. */ | |
720 | long int value; | |
ae57792d HPN |
721 | value = (symbolP != NULL |
722 | ? S_GET_VALUE (symbolP) : 0) + fragP->fr_offset; | |
3bcbcc3d HPN |
723 | |
724 | if (value >= -128 && value <= 127) | |
725 | { | |
726 | /* Byte displacement. */ | |
727 | (fragP->fr_opcode)[0] = value; | |
728 | } | |
729 | else | |
730 | { | |
731 | /* Word or dword displacement. */ | |
732 | int pow2_of_size = 1; | |
733 | char *writep; | |
734 | ||
735 | if (value < -32768 || value > 32767) | |
736 | { | |
737 | /* Outside word range, make it a dword. */ | |
738 | pow2_of_size = 2; | |
739 | } | |
740 | ||
741 | /* Modify the byte-offset BDAP into a word or dword offset | |
742 | BDAP. Or really, a BDAP rX,8bit into a | |
07e90ad5 | 743 | BDAP.[wd] rX,[PC+] followed by a word or dword. */ |
3bcbcc3d HPN |
744 | (fragP->fr_opcode)[0] = BDAP_PC_LOW + pow2_of_size * 16; |
745 | ||
746 | /* Keep the register number in the highest four bits. */ | |
747 | (fragP->fr_opcode)[1] &= 0xF0; | |
748 | (fragP->fr_opcode)[1] |= BDAP_INCR_HIGH; | |
749 | ||
47926f60 | 750 | /* It grew by two or four bytes. */ |
3bcbcc3d HPN |
751 | fragP->fr_fix += 1 << pow2_of_size; |
752 | writep = fragP->fr_literal + old_fr_fix; | |
753 | md_number_to_chars (writep, value, 1 << pow2_of_size); | |
754 | } | |
755 | frag_wane (fragP); | |
756 | } | |
757 | break; | |
758 | ||
ae57792d HPN |
759 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_BYTE): |
760 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_WORD): | |
761 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD): | |
d2aa3f9f HPN |
762 | case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_BYTE): |
763 | case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_WORD): | |
764 | case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD): | |
ae57792d HPN |
765 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_BYTE): |
766 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_WORD): | |
767 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD): | |
768 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_BYTE): | |
769 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_WORD): | |
770 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD): | |
771 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_BYTE): | |
772 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_WORD): | |
773 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD): | |
774 | case ENCODE_RELAX (STATE_LAPC, STATE_BYTE): | |
775 | case ENCODE_RELAX (STATE_LAPC, STATE_DWORD): | |
c335d394 HPN |
776 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): |
777 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): | |
93c2a809 AM |
778 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): |
779 | /* When relaxing a section for the second time, we don't need to | |
c335d394 HPN |
780 | do anything except making sure that fr_var is set right. */ |
781 | fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; | |
93c2a809 AM |
782 | break; |
783 | ||
1048a9ba HPN |
784 | case ENCODE_RELAX (STATE_MUL, STATE_BYTE): |
785 | /* Nothing to do here. */ | |
786 | break; | |
787 | ||
3bcbcc3d HPN |
788 | default: |
789 | BAD_CASE (fragP->fr_subtype); | |
790 | } | |
791 | ||
792 | return fragP->fr_var + (fragP->fr_fix - old_fr_fix); | |
793 | } | |
794 | ||
3bcbcc3d HPN |
795 | /* Perform post-processing of machine-dependent frags after relaxation. |
796 | Called after relaxation is finished. | |
797 | In: Address of frag. | |
798 | fr_type == rs_machine_dependent. | |
799 | fr_subtype is what the address relaxed to. | |
800 | ||
801 | Out: Any fixS:s and constants are set up. | |
802 | ||
803 | The caller will turn the frag into a ".space 0". */ | |
804 | ||
805 | void | |
695a4822 HPN |
806 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
807 | fragS *fragP) | |
3bcbcc3d | 808 | { |
47926f60 | 809 | /* Pointer to first byte in variable-sized part of the frag. */ |
3bcbcc3d HPN |
810 | char *var_partp; |
811 | ||
812 | /* Pointer to first opcode byte in frag. */ | |
813 | char *opcodep; | |
814 | ||
815 | /* Used to check integrity of the relaxation. | |
816 | One of 2 = long, 1 = word, or 0 = byte. */ | |
66dbb2bb | 817 | int length_code ATTRIBUTE_UNUSED; |
3bcbcc3d HPN |
818 | |
819 | /* Size in bytes of variable-sized part of frag. */ | |
820 | int var_part_size = 0; | |
821 | ||
822 | /* This is part of *fragP. It contains all information about addresses | |
823 | and offsets to varying parts. */ | |
824 | symbolS *symbolP; | |
825 | unsigned long var_part_offset; | |
826 | ||
827 | /* Where, in file space, is _var of *fragP? */ | |
828 | unsigned long address_of_var_part = 0; | |
829 | ||
830 | /* Where, in file space, does addr point? */ | |
831 | unsigned long target_address; | |
832 | ||
833 | know (fragP->fr_type == rs_machine_dependent); | |
834 | ||
835 | length_code = fragP->fr_subtype & STATE_LENGTH_MASK; | |
836 | know (length_code >= 0 && length_code < STATE_MAX_LENGTH); | |
837 | ||
838 | var_part_offset = fragP->fr_fix; | |
839 | var_partp = fragP->fr_literal + var_part_offset; | |
840 | opcodep = fragP->fr_opcode; | |
841 | ||
842 | symbolP = fragP->fr_symbol; | |
ac62c346 | 843 | target_address = (symbolP ? S_GET_VALUE (symbolP) : 0) + fragP->fr_offset; |
3bcbcc3d HPN |
844 | address_of_var_part = fragP->fr_address + var_part_offset; |
845 | ||
846 | switch (fragP->fr_subtype) | |
47926f60 | 847 | { |
ae57792d | 848 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_BYTE): |
d2aa3f9f | 849 | case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_BYTE): |
ae57792d HPN |
850 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_BYTE): |
851 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_BYTE): | |
852 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_BYTE): | |
47926f60 KH |
853 | opcodep[0] = branch_disp ((target_address - address_of_var_part)); |
854 | var_part_size = 0; | |
855 | break; | |
3bcbcc3d | 856 | |
ae57792d | 857 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_WORD): |
d2aa3f9f | 858 | case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_WORD): |
ae57792d HPN |
859 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_WORD): |
860 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_WORD): | |
861 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_WORD): | |
47926f60 KH |
862 | /* We had a quick immediate branch, now turn it into a word one i.e. a |
863 | PC autoincrement. */ | |
864 | opcodep[0] = BRANCH_PC_LOW; | |
865 | opcodep[1] &= 0xF0; | |
866 | opcodep[1] |= BRANCH_INCR_HIGH; | |
867 | md_number_to_chars (var_partp, | |
ae57792d HPN |
868 | (long) |
869 | (target_address | |
870 | - (address_of_var_part | |
871 | + (cris_arch == arch_crisv32 | |
872 | || cris_arch == arch_cris_common_v10_v32 | |
873 | ? -2 : 2))), | |
47926f60 KH |
874 | 2); |
875 | var_part_size = 2; | |
876 | break; | |
877 | ||
ae57792d | 878 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD): |
47926f60 KH |
879 | gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP, |
880 | fragP->fr_symbol, (symbolS *) NULL, | |
881 | fragP->fr_offset); | |
882 | /* Ten bytes added: a branch, nop and a jump. */ | |
883 | var_part_size = 2 + 2 + 4 + 2; | |
884 | break; | |
3bcbcc3d | 885 | |
d2aa3f9f HPN |
886 | case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD): |
887 | gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP, | |
888 | fragP->fr_symbol, (symbolS *) NULL, | |
889 | fragP->fr_offset); | |
890 | /* Twelve bytes added: a branch, nop and a pic-branch-32. */ | |
891 | var_part_size = 2 + 2 + 4 + 2 + 2; | |
892 | break; | |
893 | ||
ae57792d HPN |
894 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD): |
895 | gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP, | |
896 | fragP->fr_symbol, (symbolS *) NULL, | |
897 | fragP->fr_offset); | |
898 | /* Twelve bytes added: a branch, nop and another branch and nop. */ | |
899 | var_part_size = 2 + 2 + 2 + 4 + 2; | |
900 | break; | |
901 | ||
902 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD): | |
903 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
904 | _("Relaxation to long branches for .arch common_v10_v32\ | |
905 | not implemented")); | |
906 | /* Pretend we have twelve bytes for sake of quelling further | |
907 | errors. */ | |
908 | var_part_size = 2 + 2 + 2 + 4 + 2; | |
909 | break; | |
910 | ||
911 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD): | |
912 | /* We had a quick immediate branch or a word immediate ba. Now | |
913 | turn it into a dword one. */ | |
914 | opcodep[0] = BA_DWORD_OPCODE & 255; | |
915 | opcodep[1] = (BA_DWORD_OPCODE >> 8) & 255; | |
916 | fix_new (fragP, var_partp - fragP->fr_literal, 4, symbolP, | |
917 | fragP->fr_offset + 6, 1, BFD_RELOC_32_PCREL); | |
918 | var_part_size = 4; | |
919 | break; | |
920 | ||
921 | case ENCODE_RELAX (STATE_LAPC, STATE_BYTE): | |
922 | { | |
923 | long offset = target_address - (address_of_var_part - 2); | |
924 | ||
925 | /* This is mostly a sanity check; useful occurrences (if there | |
926 | really are any) should have been caught in | |
927 | md_estimate_size_before_relax. We can (at least | |
928 | theoretically) stumble over invalid code with odd sizes and | |
929 | .p2aligns within the code, so emit an error if that happens. | |
930 | (The generic relaxation machinery is not fit to check this.) */ | |
931 | ||
932 | if (offset & 1) | |
933 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
934 | _("Complicated LAPC target operand is not\ | |
935 | a multiple of two. Use LAPC.D")); | |
936 | ||
937 | /* FIXME: This *is* a sanity check. Remove when done with. */ | |
938 | if (offset > 15*2 || offset < 0) | |
939 | as_fatal (_("Internal error found in md_convert_frag: offset %ld.\ | |
940 | Please report this."), | |
941 | offset); | |
942 | ||
943 | opcodep[0] |= (offset / 2) & 0xf; | |
944 | var_part_size = 0; | |
945 | } | |
946 | break; | |
947 | ||
948 | case ENCODE_RELAX (STATE_LAPC, STATE_DWORD): | |
949 | { | |
950 | md_number_to_chars (opcodep, | |
951 | LAPC_DWORD_OPCODE + (opcodep[1] & 0xf0) * 256, | |
952 | 2); | |
953 | /* Remember that the reloc is against the position *after* the | |
954 | relocated contents, so we need to adjust to the start of | |
955 | the insn. */ | |
956 | fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol, | |
957 | fragP->fr_offset + 6, 1, BFD_RELOC_32_PCREL); | |
958 | var_part_size = 4; | |
959 | } | |
960 | break; | |
961 | ||
47926f60 | 962 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): |
1c971160 HPN |
963 | if (symbolP == NULL) |
964 | as_fatal (_("internal inconsistency in %s: bdapq no symbol"), | |
965 | __FUNCTION__); | |
966 | opcodep[0] = S_GET_VALUE (symbolP); | |
47926f60 KH |
967 | var_part_size = 0; |
968 | break; | |
969 | ||
970 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): | |
971 | /* We had a BDAP 8-bit "quick immediate", now turn it into a 16-bit | |
972 | one that uses PC autoincrement. */ | |
973 | opcodep[0] = BDAP_PC_LOW + (1 << 4); | |
974 | opcodep[1] &= 0xF0; | |
975 | opcodep[1] |= BDAP_INCR_HIGH; | |
1c971160 HPN |
976 | if (symbolP == NULL) |
977 | as_fatal (_("internal inconsistency in %s: bdap.w with no symbol"), | |
978 | __FUNCTION__); | |
979 | md_number_to_chars (var_partp, S_GET_VALUE (symbolP), 2); | |
47926f60 KH |
980 | var_part_size = 2; |
981 | break; | |
982 | ||
983 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): | |
984 | /* We had a BDAP 16-bit "word", change the offset to a dword. */ | |
985 | opcodep[0] = BDAP_PC_LOW + (2 << 4); | |
986 | opcodep[1] &= 0xF0; | |
987 | opcodep[1] |= BDAP_INCR_HIGH; | |
988 | if (fragP->fr_symbol == NULL) | |
989 | md_number_to_chars (var_partp, fragP->fr_offset, 4); | |
990 | else | |
991 | fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol, | |
992 | fragP->fr_offset, 0, BFD_RELOC_32); | |
993 | var_part_size = 4; | |
994 | break; | |
995 | ||
1048a9ba | 996 | case ENCODE_RELAX (STATE_MUL, STATE_BYTE): |
708587a4 | 997 | /* This is the only time we check position and alignment of the |
1048a9ba HPN |
998 | placement-tracking frag. */ |
999 | if (sec->alignment_power < 2) | |
1000 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1001 | _("section alignment must be >= 4 bytes to check MULS/MULU safeness")); | |
1002 | else | |
1003 | { | |
1004 | /* If the address after the MULS/MULU has alignment which is | |
1005 | that of the section and may be that of a cache-size of the | |
1006 | buggy versions, then the MULS/MULU can be placed badly. */ | |
1007 | if ((address_of_var_part | |
1008 | & ((1 << sec->alignment_power) - 1) & 31) == 0) | |
1009 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1010 | _("dangerous MULS/MULU location; give it higher alignment")); | |
1011 | } | |
1012 | break; | |
1013 | ||
47926f60 KH |
1014 | default: |
1015 | BAD_CASE (fragP->fr_subtype); | |
1016 | break; | |
1017 | } | |
1018 | ||
1019 | fragP->fr_fix += var_part_size; | |
3bcbcc3d HPN |
1020 | } |
1021 | ||
1022 | /* Generate a short jump around a secondary jump table. | |
a07dbd48 | 1023 | Also called from md_create_long_jump, when sufficient. */ |
3bcbcc3d | 1024 | |
a07dbd48 HPN |
1025 | void |
1026 | md_create_short_jump (char *storep, addressT from_addr, addressT to_addr, | |
695a4822 HPN |
1027 | fragS *fragP ATTRIBUTE_UNUSED, |
1028 | symbolS *to_symbol ATTRIBUTE_UNUSED) | |
3bcbcc3d HPN |
1029 | { |
1030 | long int distance; | |
1031 | ||
ae57792d HPN |
1032 | /* See md_create_long_jump about the comment on the "+ 2". */ |
1033 | long int max_minimal_minus_distance; | |
1034 | long int max_minimal_plus_distance; | |
a07dbd48 HPN |
1035 | long int max_minus_distance; |
1036 | long int max_plus_distance; | |
ae57792d HPN |
1037 | int nop_opcode; |
1038 | ||
1039 | if (cris_arch == arch_crisv32) | |
1040 | { | |
1041 | max_minimal_minus_distance = BRANCH_BB_V32 + 2; | |
1042 | max_minimal_plus_distance = BRANCH_BF_V32 + 2; | |
a07dbd48 HPN |
1043 | max_minus_distance = BRANCH_WB_V32 + 2; |
1044 | max_plus_distance = BRANCH_WF_V32 + 2; | |
ae57792d HPN |
1045 | nop_opcode = NOP_OPCODE_V32; |
1046 | } | |
a07dbd48 HPN |
1047 | else if (cris_arch == arch_cris_common_v10_v32) |
1048 | /* Bail out for compatibility mode. (It seems it can be implemented, | |
1049 | perhaps with a 10-byte sequence: "move.d NNNN,$pc/$acr", "jump | |
1050 | $acr", "nop"; but doesn't seem worth it at the moment.) */ | |
1051 | as_fatal (_("Out-of-range .word offset handling\ | |
1052 | is not implemented for .arch common_v10_v32")); | |
ae57792d HPN |
1053 | else |
1054 | { | |
1055 | max_minimal_minus_distance = BRANCH_BB + 2; | |
1056 | max_minimal_plus_distance = BRANCH_BF + 2; | |
a07dbd48 HPN |
1057 | max_minus_distance = BRANCH_WB + 2; |
1058 | max_plus_distance = BRANCH_WF + 2; | |
ae57792d HPN |
1059 | nop_opcode = NOP_OPCODE; |
1060 | } | |
1061 | ||
3bcbcc3d HPN |
1062 | distance = to_addr - from_addr; |
1063 | ||
ae57792d HPN |
1064 | if (max_minimal_minus_distance <= distance |
1065 | && distance <= max_minimal_plus_distance) | |
3bcbcc3d HPN |
1066 | { |
1067 | /* Create a "short" short jump: "BA distance - 2". */ | |
47926f60 | 1068 | storep[0] = branch_disp (distance - 2); |
3bcbcc3d HPN |
1069 | storep[1] = BA_QUICK_HIGH; |
1070 | ||
1071 | /* A nop for the delay slot. */ | |
ae57792d | 1072 | md_number_to_chars (storep + 2, nop_opcode, 2); |
3bcbcc3d HPN |
1073 | |
1074 | /* The extra word should be filled with something sane too. Make it | |
1075 | a nop to keep disassembly sane. */ | |
ae57792d | 1076 | md_number_to_chars (storep + 4, nop_opcode, 2); |
3bcbcc3d | 1077 | } |
a07dbd48 HPN |
1078 | else if (max_minus_distance <= distance |
1079 | && distance <= max_plus_distance) | |
3bcbcc3d HPN |
1080 | { |
1081 | /* Make it a "long" short jump: "BA (PC+)". */ | |
1082 | md_number_to_chars (storep, BA_PC_INCR_OPCODE, 2); | |
1083 | ||
47926f60 | 1084 | /* ".WORD distance - 4". */ |
ae57792d HPN |
1085 | md_number_to_chars (storep + 2, |
1086 | (long) (distance - 4 | |
1087 | - (cris_arch == arch_crisv32 | |
1088 | ? -4 : 0)), | |
1089 | 2); | |
3bcbcc3d HPN |
1090 | |
1091 | /* A nop for the delay slot. */ | |
ae57792d | 1092 | md_number_to_chars (storep + 4, nop_opcode, 2); |
3bcbcc3d | 1093 | } |
a07dbd48 HPN |
1094 | else |
1095 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1096 | _(".word case-table handling failed: table too large")); | |
3bcbcc3d HPN |
1097 | } |
1098 | ||
3bcbcc3d HPN |
1099 | /* Generate a long jump in a secondary jump table. |
1100 | ||
1101 | storep Where to store the jump instruction. | |
1102 | from_addr Address of the jump instruction. | |
1103 | to_addr Destination address of the jump. | |
1104 | fragP Which frag the destination address operand | |
1105 | lies in. | |
1106 | to_symbol Destination symbol. */ | |
1107 | ||
1108 | void | |
695a4822 HPN |
1109 | md_create_long_jump (char *storep, addressT from_addr, addressT to_addr, |
1110 | fragS *fragP, symbolS *to_symbol) | |
3bcbcc3d HPN |
1111 | { |
1112 | long int distance; | |
1113 | ||
ae57792d HPN |
1114 | /* FIXME: What's that "+ 3"? It comes from the magic numbers that |
1115 | used to be here, it's just translated to the limit macros used in | |
1116 | the relax table. But why + 3? */ | |
1117 | long int max_short_minus_distance | |
1118 | = cris_arch != arch_crisv32 ? BRANCH_WB + 3 : BRANCH_WB_V32 + 3; | |
1119 | ||
1120 | long int max_short_plus_distance | |
1121 | = cris_arch != arch_crisv32 ? BRANCH_WF + 3 : BRANCH_WF_V32 + 3; | |
1122 | ||
3bcbcc3d HPN |
1123 | distance = to_addr - from_addr; |
1124 | ||
ae57792d HPN |
1125 | if (max_short_minus_distance <= distance |
1126 | && distance <= max_short_plus_distance) | |
1127 | /* Then make it a "short" long jump. */ | |
a07dbd48 | 1128 | md_create_short_jump (storep, from_addr, to_addr, fragP, |
ae57792d | 1129 | to_symbol); |
3bcbcc3d HPN |
1130 | else |
1131 | { | |
ae57792d | 1132 | /* We have a "long" long jump: "JUMP [PC+]". If CRISv32, always |
d2aa3f9f | 1133 | make it a BA. Else make it an "MOVE [PC=PC+N],P0" if we're supposed |
ae57792d | 1134 | to emit PIC code. */ |
08caf3f8 | 1135 | md_number_to_chars (storep, |
ae57792d HPN |
1136 | cris_arch == arch_crisv32 |
1137 | ? BA_DWORD_OPCODE | |
d2aa3f9f HPN |
1138 | : (pic ? MOVE_PC_INCR_OPCODE_PREFIX |
1139 | : JUMP_PC_INCR_OPCODE), | |
ae57792d | 1140 | 2); |
3bcbcc3d | 1141 | |
08caf3f8 | 1142 | /* Follow with a ".DWORD to_addr", PC-relative for PIC. */ |
3bcbcc3d | 1143 | fix_new (fragP, storep + 2 - fragP->fr_literal, 4, to_symbol, |
ae57792d HPN |
1144 | cris_arch == arch_crisv32 ? 6 : 0, |
1145 | cris_arch == arch_crisv32 || pic ? 1 : 0, | |
1146 | cris_arch == arch_crisv32 || pic | |
1147 | ? BFD_RELOC_32_PCREL : BFD_RELOC_32); | |
1148 | ||
1149 | /* Follow it with a "NOP" for CRISv32. */ | |
1150 | if (cris_arch == arch_crisv32) | |
1151 | md_number_to_chars (storep + 6, NOP_OPCODE_V32, 2); | |
d2aa3f9f HPN |
1152 | else if (pic) |
1153 | /* ...and the rest of the move-opcode for pre-v32 PIC. */ | |
1154 | md_number_to_chars (storep + 6, MOVE_PC_INCR_OPCODE_SUFFIX, 2); | |
3bcbcc3d HPN |
1155 | } |
1156 | } | |
1157 | ||
ed67db7a HPN |
1158 | /* Allocate space for the first piece of an insn, and mark it as the |
1159 | start of the insn for debug-format use. */ | |
1160 | ||
1161 | static char * | |
695a4822 | 1162 | cris_insn_first_word_frag (void) |
ed67db7a HPN |
1163 | { |
1164 | char *insnp = frag_more (2); | |
1165 | ||
1166 | /* We need to mark the start of the insn by passing dwarf2_emit_insn | |
1167 | the offset from the current fragment position. This must be done | |
1168 | after the first fragment is created but before any other fragments | |
1169 | (fixed or varying) are created. Note that the offset only | |
1170 | corresponds to the "size" of the insn for a fixed-size, | |
1171 | non-expanded insn. */ | |
1172 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1173 | dwarf2_emit_insn (2); | |
1174 | ||
1175 | return insnp; | |
1176 | } | |
1177 | ||
3bcbcc3d | 1178 | /* Port-specific assembler initialization. */ |
47926f60 | 1179 | |
3bcbcc3d | 1180 | void |
695a4822 | 1181 | md_begin (void) |
3bcbcc3d HPN |
1182 | { |
1183 | const char *hashret = NULL; | |
1184 | int i = 0; | |
1185 | ||
47926f60 | 1186 | /* Set up a hash table for the instructions. */ |
3bcbcc3d HPN |
1187 | op_hash = hash_new (); |
1188 | if (op_hash == NULL) | |
1189 | as_fatal (_("Virtual memory exhausted")); | |
1190 | ||
ae57792d HPN |
1191 | /* Enable use of ".if ..asm.arch.cris.v32" |
1192 | and ".if ..asm.arch.cris.common_v10_v32" and a few others. */ | |
1193 | symbol_table_insert (symbol_new ("..asm.arch.cris.v32", absolute_section, | |
1194 | (cris_arch == arch_crisv32), | |
1195 | &zero_address_frag)); | |
1196 | symbol_table_insert (symbol_new ("..asm.arch.cris.v10", absolute_section, | |
1197 | (cris_arch == arch_crisv10), | |
1198 | &zero_address_frag)); | |
1199 | symbol_table_insert (symbol_new ("..asm.arch.cris.common_v10_v32", | |
1200 | absolute_section, | |
1201 | (cris_arch == arch_cris_common_v10_v32), | |
1202 | &zero_address_frag)); | |
1203 | symbol_table_insert (symbol_new ("..asm.arch.cris.any_v0_v10", | |
1204 | absolute_section, | |
1205 | (cris_arch == arch_cris_any_v0_v10), | |
1206 | &zero_address_frag)); | |
1207 | ||
3bcbcc3d HPN |
1208 | while (cris_opcodes[i].name != NULL) |
1209 | { | |
1210 | const char *name = cris_opcodes[i].name; | |
ae57792d HPN |
1211 | |
1212 | if (! cris_insn_ver_valid_for_arch (cris_opcodes[i].applicable_version, | |
1213 | cris_arch)) | |
1214 | { | |
1215 | i++; | |
1216 | continue; | |
1217 | } | |
1218 | ||
695a4822 HPN |
1219 | /* Need to cast to get rid of "const". FIXME: Fix hash_insert instead. */ |
1220 | hashret = hash_insert (op_hash, name, (void *) &cris_opcodes[i]); | |
3bcbcc3d HPN |
1221 | |
1222 | if (hashret != NULL && *hashret != '\0') | |
1223 | as_fatal (_("Can't hash `%s': %s\n"), cris_opcodes[i].name, | |
47926f60 | 1224 | *hashret == 0 ? _("(unknown reason)") : hashret); |
3bcbcc3d HPN |
1225 | do |
1226 | { | |
1227 | if (cris_opcodes[i].match & cris_opcodes[i].lose) | |
1228 | as_fatal (_("Buggy opcode: `%s' \"%s\"\n"), cris_opcodes[i].name, | |
1229 | cris_opcodes[i].args); | |
1230 | ||
1231 | ++i; | |
47926f60 KH |
1232 | } |
1233 | while (cris_opcodes[i].name != NULL | |
1234 | && strcmp (cris_opcodes[i].name, name) == 0); | |
3bcbcc3d HPN |
1235 | } |
1236 | } | |
1237 | ||
3bcbcc3d | 1238 | /* Assemble a source line. */ |
47926f60 | 1239 | |
3bcbcc3d | 1240 | void |
695a4822 | 1241 | md_assemble (char *str) |
3bcbcc3d HPN |
1242 | { |
1243 | struct cris_instruction output_instruction; | |
1244 | struct cris_prefix prefix; | |
1245 | char *opcodep; | |
1246 | char *p; | |
1247 | ||
1248 | know (str); | |
1249 | ||
1250 | /* Do the low-level grunt - assemble to bits and split up into a prefix | |
1251 | and ordinary insn. */ | |
1252 | cris_process_instruction (str, &output_instruction, &prefix); | |
1253 | ||
1254 | /* Handle any prefixes to the instruction. */ | |
1255 | switch (prefix.kind) | |
1256 | { | |
1257 | case PREFIX_NONE: | |
1258 | break; | |
1259 | ||
1260 | /* When the expression is unknown for a BDAP, it can need 0, 2 or 4 | |
1261 | extra bytes, so we handle it separately. */ | |
1262 | case PREFIX_BDAP_IMM: | |
cc99daad | 1263 | /* We only do it if the relocation is unspecified, i.e. not a PIC or TLS |
08caf3f8 HPN |
1264 | relocation. */ |
1265 | if (prefix.reloc == BFD_RELOC_NONE) | |
1266 | { | |
1267 | gen_bdap (prefix.base_reg_number, &prefix.expr); | |
1268 | break; | |
1269 | } | |
1270 | /* Fall through. */ | |
3bcbcc3d HPN |
1271 | case PREFIX_BDAP: |
1272 | case PREFIX_BIAP: | |
1273 | case PREFIX_DIP: | |
ed67db7a | 1274 | opcodep = cris_insn_first_word_frag (); |
3bcbcc3d HPN |
1275 | |
1276 | /* Output the prefix opcode. */ | |
1277 | md_number_to_chars (opcodep, (long) prefix.opcode, 2); | |
1278 | ||
08caf3f8 | 1279 | /* Having a specified reloc only happens for DIP and for BDAP with |
cc99daad | 1280 | PIC or TLS operands, but it is ok to drop through here for the other |
08caf3f8 | 1281 | prefixes as they can have no relocs specified. */ |
3bcbcc3d HPN |
1282 | if (prefix.reloc != BFD_RELOC_NONE) |
1283 | { | |
08caf3f8 HPN |
1284 | unsigned int relocsize |
1285 | = (prefix.kind == PREFIX_DIP | |
cc99daad | 1286 | ? 4 : cris_get_specified_reloc_size (prefix.reloc)); |
08caf3f8 | 1287 | |
08caf3f8 HPN |
1288 | p = frag_more (relocsize); |
1289 | fix_new_exp (frag_now, (p - frag_now->fr_literal), relocsize, | |
3bcbcc3d HPN |
1290 | &prefix.expr, 0, prefix.reloc); |
1291 | } | |
1292 | break; | |
1293 | ||
1294 | case PREFIX_PUSH: | |
ed67db7a | 1295 | opcodep = cris_insn_first_word_frag (); |
3bcbcc3d HPN |
1296 | |
1297 | /* Output the prefix opcode. Being a "push", we add the negative | |
1298 | size of the register to "sp". */ | |
1299 | if (output_instruction.spec_reg != NULL) | |
1300 | { | |
47926f60 | 1301 | /* Special register. */ |
3bcbcc3d HPN |
1302 | opcodep[0] = -output_instruction.spec_reg->reg_size; |
1303 | } | |
1304 | else | |
1305 | { | |
47926f60 | 1306 | /* General register. */ |
3bcbcc3d HPN |
1307 | opcodep[0] = -4; |
1308 | } | |
1309 | opcodep[1] = (REG_SP << 4) + (BDAP_QUICK_OPCODE >> 8); | |
1310 | break; | |
1311 | ||
1312 | default: | |
1313 | BAD_CASE (prefix.kind); | |
1314 | } | |
1315 | ||
1316 | /* If we only had a prefix insn, we're done. */ | |
1317 | if (output_instruction.insn_type == CRIS_INSN_NONE) | |
1318 | return; | |
1319 | ||
1320 | /* Done with the prefix. Continue with the main instruction. */ | |
ed67db7a HPN |
1321 | if (prefix.kind == PREFIX_NONE) |
1322 | opcodep = cris_insn_first_word_frag (); | |
1323 | else | |
1324 | opcodep = frag_more (2); | |
3bcbcc3d HPN |
1325 | |
1326 | /* Output the instruction opcode. */ | |
47926f60 | 1327 | md_number_to_chars (opcodep, (long) (output_instruction.opcode), 2); |
3bcbcc3d HPN |
1328 | |
1329 | /* Output the symbol-dependent instruction stuff. */ | |
1330 | if (output_instruction.insn_type == CRIS_INSN_BRANCH) | |
1331 | { | |
1332 | segT to_seg = absolute_section; | |
1333 | int is_undefined = 0; | |
1334 | int length_code; | |
1335 | ||
1336 | if (output_instruction.expr.X_op != O_constant) | |
1337 | { | |
1338 | to_seg = S_GET_SEGMENT (output_instruction.expr.X_add_symbol); | |
1339 | ||
1340 | if (to_seg == undefined_section) | |
1341 | is_undefined = 1; | |
1342 | } | |
1343 | ||
ae57792d HPN |
1344 | if (to_seg == now_seg || is_undefined |
1345 | /* In CRISv32, there *is* a 32-bit absolute branch, so don't | |
1346 | emit the 12-byte sequence for known symbols in other | |
1347 | segments. */ | |
1348 | || (cris_arch == arch_crisv32 | |
1349 | && output_instruction.opcode == BA_QUICK_OPCODE)) | |
3bcbcc3d | 1350 | { |
08caf3f8 HPN |
1351 | /* Handle complex expressions. */ |
1352 | valueT addvalue | |
1c971160 HPN |
1353 | = (SIMPLE_EXPR (&output_instruction.expr) |
1354 | ? output_instruction.expr.X_add_number | |
1355 | : 0); | |
08caf3f8 | 1356 | symbolS *sym |
1c971160 HPN |
1357 | = (SIMPLE_EXPR (&output_instruction.expr) |
1358 | ? output_instruction.expr.X_add_symbol | |
1359 | : make_expr_symbol (&output_instruction.expr)); | |
08caf3f8 | 1360 | |
ae57792d HPN |
1361 | /* If is_undefined, the expression may still become now_seg. |
1362 | That case is handled by md_estimate_size_before_relax. */ | |
1363 | length_code = to_seg == now_seg ? STATE_BYTE : STATE_UNDF; | |
1364 | ||
d2aa3f9f HPN |
1365 | /* Make room for max twelve bytes of variable length for v32 mode |
1366 | or PIC, ten for v10 and older. */ | |
ae57792d HPN |
1367 | frag_var (rs_machine_dependent, |
1368 | (cris_arch == arch_crisv32 | |
d2aa3f9f HPN |
1369 | || cris_arch == arch_cris_common_v10_v32 |
1370 | || pic) ? 12 : 10, 0, | |
ae57792d HPN |
1371 | ENCODE_RELAX (cris_arch == arch_crisv32 |
1372 | ? (output_instruction.opcode | |
1373 | == BA_QUICK_OPCODE | |
1374 | ? STATE_ABS_BRANCH_V32 | |
1375 | : STATE_COND_BRANCH_V32) | |
1376 | : (cris_arch == arch_cris_common_v10_v32 | |
1377 | ? STATE_COND_BRANCH_COMMON | |
d2aa3f9f HPN |
1378 | : (pic ? STATE_COND_BRANCH_PIC |
1379 | : STATE_COND_BRANCH)), | |
ae57792d | 1380 | length_code), |
08caf3f8 | 1381 | sym, addvalue, opcodep); |
3bcbcc3d HPN |
1382 | } |
1383 | else | |
1384 | { | |
1385 | /* We have: to_seg != now_seg && to_seg != undefined_section. | |
1386 | This means it is a branch to a known symbol in another | |
fb2fd3e1 | 1387 | section, perhaps an absolute address. Emit a 32-bit branch. */ |
ae57792d HPN |
1388 | char *cond_jump |
1389 | = frag_more ((cris_arch == arch_crisv32 | |
d2aa3f9f HPN |
1390 | || cris_arch == arch_cris_common_v10_v32 |
1391 | || pic) | |
ae57792d | 1392 | ? 12 : 10); |
08caf3f8 | 1393 | |
08caf3f8 | 1394 | gen_cond_branch_32 (opcodep, cond_jump, frag_now, |
3bcbcc3d | 1395 | output_instruction.expr.X_add_symbol, |
47926f60 | 1396 | (symbolS *) NULL, |
3bcbcc3d HPN |
1397 | output_instruction.expr.X_add_number); |
1398 | } | |
1399 | } | |
1048a9ba HPN |
1400 | else if (output_instruction.insn_type == CRIS_INSN_MUL |
1401 | && err_for_dangerous_mul_placement) | |
1402 | /* Create a frag which which we track the location of the mul insn | |
1403 | (in the last two bytes before the mul-frag). */ | |
1404 | frag_variant (rs_machine_dependent, 0, 0, | |
1405 | ENCODE_RELAX (STATE_MUL, STATE_BYTE), | |
1406 | NULL, 0, opcodep); | |
3bcbcc3d HPN |
1407 | else |
1408 | { | |
1409 | if (output_instruction.imm_oprnd_size > 0) | |
1410 | { | |
2d2255b5 | 1411 | /* The instruction has an immediate operand. */ |
08caf3f8 | 1412 | enum bfd_reloc_code_real reloc = BFD_RELOC_NONE; |
3bcbcc3d HPN |
1413 | |
1414 | switch (output_instruction.imm_oprnd_size) | |
1415 | { | |
1416 | /* Any byte-size immediate constants are treated as | |
1417 | word-size. FIXME: Thus overflow check does not work | |
1418 | correctly. */ | |
1419 | ||
1420 | case 2: | |
08caf3f8 HPN |
1421 | /* Note that size-check for the explicit reloc has already |
1422 | been done when we get here. */ | |
1423 | if (output_instruction.reloc != BFD_RELOC_NONE) | |
1424 | reloc = output_instruction.reloc; | |
1425 | else | |
1426 | reloc = BFD_RELOC_16; | |
3bcbcc3d HPN |
1427 | break; |
1428 | ||
1429 | case 4: | |
08caf3f8 HPN |
1430 | /* Allow a relocation specified in the operand. */ |
1431 | if (output_instruction.reloc != BFD_RELOC_NONE) | |
1432 | reloc = output_instruction.reloc; | |
1433 | else | |
1434 | reloc = BFD_RELOC_32; | |
3bcbcc3d HPN |
1435 | break; |
1436 | ||
1437 | default: | |
1438 | BAD_CASE (output_instruction.imm_oprnd_size); | |
1439 | } | |
1440 | ||
1441 | p = frag_more (output_instruction.imm_oprnd_size); | |
1442 | fix_new_exp (frag_now, (p - frag_now->fr_literal), | |
1443 | output_instruction.imm_oprnd_size, | |
ae57792d HPN |
1444 | &output_instruction.expr, |
1445 | reloc == BFD_RELOC_32_PCREL | |
1446 | || reloc == BFD_RELOC_16_PCREL | |
1447 | || reloc == BFD_RELOC_8_PCREL, reloc); | |
1448 | } | |
1449 | else if (output_instruction.reloc == BFD_RELOC_CRIS_LAPCQ_OFFSET | |
1450 | && output_instruction.expr.X_md != 0) | |
1451 | { | |
1452 | /* Handle complex expressions. */ | |
1453 | valueT addvalue | |
1454 | = (output_instruction.expr.X_op_symbol != NULL | |
1455 | ? 0 : output_instruction.expr.X_add_number); | |
1456 | symbolS *sym | |
1457 | = (output_instruction.expr.X_op_symbol != NULL | |
1458 | ? make_expr_symbol (&output_instruction.expr) | |
1459 | : output_instruction.expr.X_add_symbol); | |
1460 | ||
1461 | /* This is a relaxing construct, so we need a frag_var rather | |
1462 | than the fix_new_exp call below. */ | |
1463 | frag_var (rs_machine_dependent, | |
1464 | 4, 0, | |
1465 | ENCODE_RELAX (STATE_LAPC, STATE_UNDF), | |
1466 | sym, addvalue, opcodep); | |
3bcbcc3d HPN |
1467 | } |
1468 | else if (output_instruction.reloc != BFD_RELOC_NONE) | |
1469 | { | |
1470 | /* An immediate operand that has a relocation and needs to be | |
47926f60 | 1471 | processed further. */ |
3bcbcc3d HPN |
1472 | |
1473 | /* It is important to use fix_new_exp here and everywhere else | |
1474 | (and not fix_new), as fix_new_exp can handle "difference | |
1475 | expressions" - where the expression contains a difference of | |
1476 | two symbols in the same segment. */ | |
1477 | fix_new_exp (frag_now, (opcodep - frag_now->fr_literal), 2, | |
ae57792d HPN |
1478 | &output_instruction.expr, |
1479 | output_instruction.reloc == BFD_RELOC_32_PCREL | |
1480 | || output_instruction.reloc == BFD_RELOC_16_PCREL | |
1481 | || output_instruction.reloc == BFD_RELOC_8_PCREL | |
1482 | || (output_instruction.reloc | |
1483 | == BFD_RELOC_CRIS_LAPCQ_OFFSET), | |
3bcbcc3d HPN |
1484 | output_instruction.reloc); |
1485 | } | |
1486 | } | |
1487 | } | |
1488 | ||
3bcbcc3d | 1489 | /* Low level text-to-bits assembly. */ |
47926f60 | 1490 | |
3bcbcc3d | 1491 | static void |
695a4822 HPN |
1492 | cris_process_instruction (char *insn_text, struct cris_instruction *out_insnp, |
1493 | struct cris_prefix *prefixp) | |
3bcbcc3d | 1494 | { |
47926f60 KH |
1495 | char *s; |
1496 | char modified_char = 0; | |
1497 | const char *args; | |
3bcbcc3d | 1498 | struct cris_opcode *instruction; |
47926f60 KH |
1499 | char *operands; |
1500 | int match = 0; | |
1501 | int mode; | |
1502 | int regno; | |
1503 | int size_bits; | |
3bcbcc3d HPN |
1504 | |
1505 | /* Reset these fields to a harmless state in case we need to return in | |
1506 | error. */ | |
1507 | prefixp->kind = PREFIX_NONE; | |
1508 | prefixp->reloc = BFD_RELOC_NONE; | |
ae57792d | 1509 | out_insnp->insn_type = CRIS_INSN_NONE; |
3bcbcc3d HPN |
1510 | out_insnp->imm_oprnd_size = 0; |
1511 | ||
1512 | /* Find the end of the opcode mnemonic. We assume (true in 2.9.1) | |
1513 | that the caller has translated the opcode to lower-case, up to the | |
47926f60 | 1514 | first non-letter. */ |
3882b010 | 1515 | for (operands = insn_text; ISLOWER (*operands); ++operands) |
3bcbcc3d HPN |
1516 | ; |
1517 | ||
1518 | /* Terminate the opcode after letters, but save the character there if | |
1519 | it was of significance. */ | |
1520 | switch (*operands) | |
1521 | { | |
1522 | case '\0': | |
1523 | break; | |
1524 | ||
1525 | case '.': | |
47926f60 | 1526 | /* Put back the modified character later. */ |
3bcbcc3d | 1527 | modified_char = *operands; |
47926f60 | 1528 | /* Fall through. */ |
3bcbcc3d HPN |
1529 | |
1530 | case ' ': | |
47926f60 KH |
1531 | /* Consume the character after the mnemonic |
1532 | and replace it with '\0'. */ | |
3bcbcc3d HPN |
1533 | *operands++ = '\0'; |
1534 | break; | |
1535 | ||
1536 | default: | |
1537 | as_bad (_("Unknown opcode: `%s'"), insn_text); | |
1538 | return; | |
1539 | } | |
1540 | ||
1541 | /* Find the instruction. */ | |
1542 | instruction = (struct cris_opcode *) hash_find (op_hash, insn_text); | |
1543 | if (instruction == NULL) | |
1544 | { | |
1545 | as_bad (_("Unknown opcode: `%s'"), insn_text); | |
1546 | return; | |
1547 | } | |
1548 | ||
1549 | /* Put back the modified character. */ | |
1550 | switch (modified_char) | |
1551 | { | |
1552 | case 0: | |
1553 | break; | |
1554 | ||
1555 | default: | |
1556 | *--operands = modified_char; | |
1557 | } | |
1558 | ||
3bcbcc3d | 1559 | /* Try to match an opcode table slot. */ |
47926f60 | 1560 | for (s = operands;;) |
3bcbcc3d | 1561 | { |
47926f60 | 1562 | int imm_expr_found; |
3bcbcc3d HPN |
1563 | |
1564 | /* Initialize *prefixp, perhaps after being modified for a | |
47926f60 | 1565 | "near match". */ |
3bcbcc3d HPN |
1566 | prefixp->kind = PREFIX_NONE; |
1567 | prefixp->reloc = BFD_RELOC_NONE; | |
1568 | ||
1569 | /* Initialize *out_insnp. */ | |
1570 | memset (out_insnp, 0, sizeof (*out_insnp)); | |
1571 | out_insnp->opcode = instruction->match; | |
1572 | out_insnp->reloc = BFD_RELOC_NONE; | |
1573 | out_insnp->insn_type = CRIS_INSN_NORMAL; | |
1574 | out_insnp->imm_oprnd_size = 0; | |
1575 | ||
1576 | imm_expr_found = 0; | |
1577 | ||
1578 | /* Build the opcode, checking as we go to make sure that the | |
1579 | operands match. */ | |
47926f60 | 1580 | for (args = instruction->args;; ++args) |
3bcbcc3d HPN |
1581 | { |
1582 | switch (*args) | |
1583 | { | |
1584 | case '\0': | |
1585 | /* If we've come to the end of arguments, we're done. */ | |
1586 | if (*s == '\0') | |
1587 | match = 1; | |
1588 | break; | |
1589 | ||
1590 | case '!': | |
1591 | /* Non-matcher character for disassembly. | |
1592 | Ignore it here. */ | |
1593 | continue; | |
1594 | ||
ae57792d HPN |
1595 | case '[': |
1596 | case ']': | |
3bcbcc3d HPN |
1597 | case ',': |
1598 | case ' ': | |
1599 | /* These must match exactly. */ | |
1600 | if (*s++ == *args) | |
1601 | continue; | |
1602 | break; | |
1603 | ||
ae57792d HPN |
1604 | case 'A': |
1605 | /* "ACR", case-insensitive. | |
1606 | Handle a sometimes-mandatory dollar sign as register | |
1607 | prefix. */ | |
1608 | if (*s == REGISTER_PREFIX_CHAR) | |
1609 | s++; | |
1610 | else if (demand_register_prefix) | |
1611 | break; | |
1612 | ||
1613 | if ((*s++ != 'a' && s[-1] != 'A') | |
1614 | || (*s++ != 'c' && s[-1] != 'C') | |
1615 | || (*s++ != 'r' && s[-1] != 'R')) | |
1616 | break; | |
1617 | continue; | |
1618 | ||
3bcbcc3d HPN |
1619 | case 'B': |
1620 | /* This is not really an operand, but causes a "BDAP | |
47926f60 | 1621 | -size,SP" prefix to be output, for PUSH instructions. */ |
3bcbcc3d HPN |
1622 | prefixp->kind = PREFIX_PUSH; |
1623 | continue; | |
1624 | ||
1625 | case 'b': | |
1626 | /* This letter marks an operand that should not be matched | |
1627 | in the assembler. It is a branch with 16-bit | |
1628 | displacement. The assembler will create them from the | |
1629 | 8-bit flavor when necessary. The assembler does not | |
1630 | support the [rN+] operand, as the [r15+] that is | |
1631 | generated for 16-bit displacements. */ | |
1632 | break; | |
1633 | ||
1634 | case 'c': | |
1635 | /* A 5-bit unsigned immediate in bits <4:0>. */ | |
1636 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1637 | break; | |
1638 | else | |
1639 | { | |
1640 | if (out_insnp->expr.X_op == O_constant | |
1641 | && (out_insnp->expr.X_add_number < 0 | |
1642 | || out_insnp->expr.X_add_number > 31)) | |
1643 | as_bad (_("Immediate value not in 5 bit unsigned range: %ld"), | |
1644 | out_insnp->expr.X_add_number); | |
1645 | ||
1646 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_5; | |
1647 | continue; | |
1648 | } | |
1649 | ||
1650 | case 'C': | |
1651 | /* A 4-bit unsigned immediate in bits <3:0>. */ | |
1652 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1653 | break; | |
1654 | else | |
1655 | { | |
1656 | if (out_insnp->expr.X_op == O_constant | |
1657 | && (out_insnp->expr.X_add_number < 0 | |
1658 | || out_insnp->expr.X_add_number > 15)) | |
1659 | as_bad (_("Immediate value not in 4 bit unsigned range: %ld"), | |
1660 | out_insnp->expr.X_add_number); | |
1661 | ||
1662 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_4; | |
1663 | continue; | |
1664 | } | |
1665 | ||
ae57792d HPN |
1666 | /* For 'd', check for an optional ".d" or ".D" at the |
1667 | start of the operands, followed by a space character. */ | |
1668 | case 'd': | |
1669 | if (modified_char == '.' && *s == '.') | |
1670 | { | |
1671 | if ((s[1] != 'd' && s[1] == 'D') | |
1672 | || ! ISSPACE (s[2])) | |
1673 | break; | |
1674 | s += 2; | |
1675 | continue; | |
1676 | } | |
1677 | continue; | |
1678 | ||
3bcbcc3d HPN |
1679 | case 'D': |
1680 | /* General register in bits <15:12> and <3:0>. */ | |
1681 | if (! get_gen_reg (&s, ®no)) | |
1682 | break; | |
1683 | else | |
1684 | { | |
1685 | out_insnp->opcode |= regno /* << 0 */; | |
1686 | out_insnp->opcode |= regno << 12; | |
1687 | continue; | |
1688 | } | |
1689 | ||
1690 | case 'f': | |
1691 | /* Flags from the condition code register. */ | |
1692 | { | |
1693 | int flags = 0; | |
1694 | ||
1695 | if (! get_flags (&s, &flags)) | |
1696 | break; | |
1697 | ||
47926f60 | 1698 | out_insnp->opcode |= ((flags & 0xf0) << 8) | (flags & 0xf); |
3bcbcc3d HPN |
1699 | continue; |
1700 | } | |
1701 | ||
1702 | case 'i': | |
1703 | /* A 6-bit signed immediate in bits <5:0>. */ | |
1704 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1705 | break; | |
1706 | else | |
1707 | { | |
1708 | if (out_insnp->expr.X_op == O_constant | |
1709 | && (out_insnp->expr.X_add_number < -32 | |
1710 | || out_insnp->expr.X_add_number > 31)) | |
1711 | as_bad (_("Immediate value not in 6 bit range: %ld"), | |
1712 | out_insnp->expr.X_add_number); | |
1713 | out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_6; | |
1714 | continue; | |
1715 | } | |
1716 | ||
1717 | case 'I': | |
1718 | /* A 6-bit unsigned immediate in bits <5:0>. */ | |
1719 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1720 | break; | |
1721 | else | |
1722 | { | |
1723 | if (out_insnp->expr.X_op == O_constant | |
1724 | && (out_insnp->expr.X_add_number < 0 | |
1725 | || out_insnp->expr.X_add_number > 63)) | |
1726 | as_bad (_("Immediate value not in 6 bit unsigned range: %ld"), | |
1727 | out_insnp->expr.X_add_number); | |
1728 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_6; | |
1729 | continue; | |
1730 | } | |
1731 | ||
1732 | case 'M': | |
1733 | /* A size modifier, B, W or D, to be put in a bit position | |
1734 | suitable for CLEAR instructions (i.e. reflecting a zero | |
1735 | register). */ | |
1736 | if (! get_bwd_size_modifier (&s, &size_bits)) | |
1737 | break; | |
1738 | else | |
1739 | { | |
1740 | switch (size_bits) | |
1741 | { | |
1742 | case 0: | |
1743 | out_insnp->opcode |= 0 << 12; | |
1744 | break; | |
1745 | ||
1746 | case 1: | |
1747 | out_insnp->opcode |= 4 << 12; | |
1748 | break; | |
1749 | ||
1750 | case 2: | |
1751 | out_insnp->opcode |= 8 << 12; | |
1752 | break; | |
1753 | } | |
1754 | continue; | |
1755 | } | |
1756 | ||
1757 | case 'm': | |
1758 | /* A size modifier, B, W or D, to be put in bits <5:4>. */ | |
ae57792d HPN |
1759 | if (modified_char != '.' |
1760 | || ! get_bwd_size_modifier (&s, &size_bits)) | |
3bcbcc3d HPN |
1761 | break; |
1762 | else | |
1763 | { | |
1764 | out_insnp->opcode |= size_bits << 4; | |
1765 | continue; | |
1766 | } | |
1767 | ||
1768 | case 'o': | |
1769 | /* A branch expression. */ | |
1770 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1771 | break; | |
1772 | else | |
1773 | { | |
1774 | out_insnp->insn_type = CRIS_INSN_BRANCH; | |
1775 | continue; | |
1776 | } | |
1777 | ||
ae57792d HPN |
1778 | case 'Q': |
1779 | /* A 8-bit quick BDAP expression, "expr,R". */ | |
1780 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1781 | break; | |
1782 | ||
1783 | if (*s != ',') | |
1784 | break; | |
1785 | ||
1786 | s++; | |
1787 | ||
1788 | if (!get_gen_reg (&s, ®no)) | |
1789 | break; | |
1790 | ||
1791 | out_insnp->opcode |= regno << 12; | |
1792 | out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_8; | |
1793 | continue; | |
1794 | ||
3bcbcc3d | 1795 | case 'O': |
ae57792d | 1796 | /* A BDAP expression for any size, "expr,R". */ |
3bcbcc3d HPN |
1797 | if (! cris_get_expression (&s, &prefixp->expr)) |
1798 | break; | |
1799 | else | |
1800 | { | |
1801 | if (*s != ',') | |
1802 | break; | |
1803 | ||
1804 | s++; | |
1805 | ||
1806 | if (!get_gen_reg (&s, &prefixp->base_reg_number)) | |
1807 | break; | |
1808 | ||
1809 | /* Since 'O' is used with an explicit bdap, we have no | |
47926f60 | 1810 | "real" instruction. */ |
3bcbcc3d | 1811 | prefixp->kind = PREFIX_BDAP_IMM; |
08caf3f8 HPN |
1812 | prefixp->opcode |
1813 | = BDAP_QUICK_OPCODE | (prefixp->base_reg_number << 12); | |
1814 | ||
3bcbcc3d HPN |
1815 | out_insnp->insn_type = CRIS_INSN_NONE; |
1816 | continue; | |
1817 | } | |
1818 | ||
1819 | case 'P': | |
1820 | /* Special register in bits <15:12>. */ | |
1821 | if (! get_spec_reg (&s, &out_insnp->spec_reg)) | |
1822 | break; | |
1823 | else | |
1824 | { | |
1825 | /* Use of some special register names come with a | |
1826 | specific warning. Note that we have no ".cpu type" | |
1827 | pseudo yet, so some of this is just unused | |
1828 | framework. */ | |
1829 | if (out_insnp->spec_reg->warning) | |
20203fb9 | 1830 | as_warn ("%s", out_insnp->spec_reg->warning); |
3bcbcc3d HPN |
1831 | else if (out_insnp->spec_reg->applicable_version |
1832 | == cris_ver_warning) | |
1833 | /* Others have a generic warning. */ | |
1834 | as_warn (_("Unimplemented register `%s' specified"), | |
1835 | out_insnp->spec_reg->name); | |
1836 | ||
1837 | out_insnp->opcode | |
1838 | |= out_insnp->spec_reg->number << 12; | |
1839 | continue; | |
1840 | } | |
1841 | ||
1842 | case 'p': | |
1843 | /* This character is used in the disassembler to | |
1844 | recognize a prefix instruction to fold into the | |
1845 | addressing mode for the next instruction. It is | |
47926f60 | 1846 | ignored here. */ |
3bcbcc3d HPN |
1847 | continue; |
1848 | ||
1849 | case 'R': | |
1850 | /* General register in bits <15:12>. */ | |
1851 | if (! get_gen_reg (&s, ®no)) | |
1852 | break; | |
1853 | else | |
1854 | { | |
1855 | out_insnp->opcode |= regno << 12; | |
1856 | continue; | |
1857 | } | |
1858 | ||
1859 | case 'r': | |
1860 | /* General register in bits <3:0>. */ | |
1861 | if (! get_gen_reg (&s, ®no)) | |
1862 | break; | |
1863 | else | |
1864 | { | |
1865 | out_insnp->opcode |= regno /* << 0 */; | |
1866 | continue; | |
1867 | } | |
1868 | ||
1869 | case 'S': | |
1870 | /* Source operand in bit <10> and a prefix; a 3-operand | |
1871 | prefix. */ | |
1872 | if (! get_3op_or_dip_prefix_op (&s, prefixp)) | |
1873 | break; | |
1874 | else | |
1875 | continue; | |
1876 | ||
1877 | case 's': | |
1878 | /* Source operand in bits <10>, <3:0> and optionally a | |
1879 | prefix; i.e. an indirect operand or an side-effect | |
ae57792d | 1880 | prefix (where valid). */ |
3bcbcc3d HPN |
1881 | if (! get_autoinc_prefix_or_indir_op (&s, prefixp, &mode, |
1882 | ®no, | |
1883 | &imm_expr_found, | |
1884 | &out_insnp->expr)) | |
1885 | break; | |
1886 | else | |
1887 | { | |
1888 | if (prefixp->kind != PREFIX_NONE) | |
1889 | { | |
1890 | /* A prefix, so it has the autoincrement bit | |
1891 | set. */ | |
1892 | out_insnp->opcode |= (AUTOINCR_BIT << 8); | |
1893 | } | |
1894 | else | |
08caf3f8 HPN |
1895 | { |
1896 | /* No prefix. The "mode" variable contains bits like | |
1897 | whether or not this is autoincrement mode. */ | |
1898 | out_insnp->opcode |= (mode << 10); | |
1899 | ||
cc99daad | 1900 | /* If there was a reloc specifier, then it was |
08caf3f8 HPN |
1901 | attached to the prefix. Note that we can't check |
1902 | that the reloc size matches, since we don't have | |
1903 | all the operands yet in all cases. */ | |
1904 | if (prefixp->reloc != BFD_RELOC_NONE) | |
1905 | out_insnp->reloc = prefixp->reloc; | |
1906 | } | |
3bcbcc3d HPN |
1907 | |
1908 | out_insnp->opcode |= regno /* << 0 */ ; | |
1909 | continue; | |
1910 | } | |
1911 | ||
ae57792d HPN |
1912 | case 'N': |
1913 | case 'Y': | |
cc99daad HPN |
1914 | /* Like 's', but immediate operand only. Also do not |
1915 | modify insn. There are no insns where an explicit reloc | |
ae57792d HPN |
1916 | specifier makes sense. */ |
1917 | if (cris_get_expression (&s, &out_insnp->expr)) | |
1918 | { | |
1919 | imm_expr_found = 1; | |
1920 | continue; | |
1921 | } | |
1922 | break; | |
1923 | ||
1924 | case 'n': | |
1925 | /* Like 'N', but PC-relative to the start of the insn. | |
1926 | There might be a :PLT to request a PLT entry. */ | |
1927 | if (cris_get_expression (&s, &out_insnp->expr)) | |
1928 | { | |
1929 | imm_expr_found = 1; | |
1930 | out_insnp->reloc = BFD_RELOC_32_PCREL; | |
1931 | ||
1932 | /* We have to adjust the expression, because that | |
1933 | relocation is to the location *after* the | |
1934 | relocation. So add 2 for the insn and 4 for the | |
1935 | relocation. */ | |
1936 | out_insnp->expr.X_add_number += 6; | |
1937 | ||
cc99daad HPN |
1938 | /* TLS specifiers do not make sense here. */ |
1939 | if (pic && *s == RELOC_SUFFIX_CHAR) | |
1940 | cris_get_reloc_suffix (&s, &out_insnp->reloc, | |
1941 | &out_insnp->expr); | |
ae57792d HPN |
1942 | |
1943 | continue; | |
1944 | } | |
1945 | break; | |
1946 | ||
1947 | case 'U': | |
1948 | /* Maybe 'u', maybe 'n'. Only for LAPC/LAPCQ. */ | |
1949 | if (cris_get_expression (&s, &out_insnp->expr)) | |
1950 | { | |
1951 | out_insnp->reloc = BFD_RELOC_CRIS_LAPCQ_OFFSET; | |
1952 | ||
1953 | /* Define 1 as relaxing. */ | |
1954 | out_insnp->expr.X_md = 1; | |
1955 | continue; | |
1956 | } | |
1957 | break; | |
1958 | ||
1959 | case 'u': | |
1960 | /* Four PC-relative bits in <3:0> representing <4:1>:0 of | |
1961 | an offset relative to the beginning of the current | |
1962 | insn. */ | |
1963 | if (cris_get_expression (&s, &out_insnp->expr)) | |
1964 | { | |
1965 | out_insnp->reloc = BFD_RELOC_CRIS_LAPCQ_OFFSET; | |
1966 | ||
1967 | /* Define 0 as non-relaxing. */ | |
1968 | out_insnp->expr.X_md = 0; | |
1969 | ||
1970 | /* We have to adjust the expression, because that | |
1971 | relocation is to the location *after* the | |
1972 | insn. So add 2 for the insn. */ | |
1973 | out_insnp->expr.X_add_number += 2; | |
1974 | continue; | |
1975 | } | |
1976 | break; | |
1977 | ||
3bcbcc3d HPN |
1978 | case 'x': |
1979 | /* Rs.m in bits <15:12> and <5:4>. */ | |
1980 | if (! get_gen_reg (&s, ®no) | |
1981 | || ! get_bwd_size_modifier (&s, &size_bits)) | |
1982 | break; | |
1983 | else | |
1984 | { | |
47926f60 | 1985 | out_insnp->opcode |= (regno << 12) | (size_bits << 4); |
3bcbcc3d HPN |
1986 | continue; |
1987 | } | |
1988 | ||
1989 | case 'y': | |
1990 | /* Source operand in bits <10>, <3:0> and optionally a | |
1991 | prefix; i.e. an indirect operand or an side-effect | |
1992 | prefix. | |
1993 | ||
1994 | The difference to 's' is that this does not allow an | |
81d4177b | 1995 | "immediate" expression. */ |
3bcbcc3d HPN |
1996 | if (! get_autoinc_prefix_or_indir_op (&s, prefixp, |
1997 | &mode, ®no, | |
1998 | &imm_expr_found, | |
1999 | &out_insnp->expr) | |
2000 | || imm_expr_found) | |
2001 | break; | |
2002 | else | |
2003 | { | |
2004 | if (prefixp->kind != PREFIX_NONE) | |
2005 | { | |
2006 | /* A prefix, and those matched here always have | |
2007 | side-effects (see 's' case). */ | |
2008 | out_insnp->opcode |= (AUTOINCR_BIT << 8); | |
2009 | } | |
2010 | else | |
2011 | { | |
2012 | /* No prefix. The "mode" variable contains bits | |
2013 | like whether or not this is autoincrement | |
2014 | mode. */ | |
2015 | out_insnp->opcode |= (mode << 10); | |
2016 | } | |
2017 | ||
2018 | out_insnp->opcode |= regno /* << 0 */; | |
2019 | continue; | |
2020 | } | |
2021 | ||
2022 | case 'z': | |
2023 | /* Size modifier (B or W) in bit <4>. */ | |
2024 | if (! get_bw_size_modifier (&s, &size_bits)) | |
2025 | break; | |
2026 | else | |
2027 | { | |
2028 | out_insnp->opcode |= size_bits << 4; | |
2029 | continue; | |
2030 | } | |
2031 | ||
ae57792d HPN |
2032 | case 'T': |
2033 | if (cris_arch == arch_crisv32 | |
2034 | && get_sup_reg (&s, ®no)) | |
2035 | { | |
2036 | out_insnp->opcode |= regno << 12; | |
2037 | continue; | |
2038 | } | |
2039 | break; | |
2040 | ||
3bcbcc3d HPN |
2041 | default: |
2042 | BAD_CASE (*args); | |
2043 | } | |
2044 | ||
2045 | /* We get here when we fail a match above or we found a | |
2046 | complete match. Break out of this loop. */ | |
2047 | break; | |
2048 | } | |
2049 | ||
2050 | /* Was it a match or a miss? */ | |
2051 | if (match == 0) | |
2052 | { | |
2053 | /* If it's just that the args don't match, maybe the next | |
2054 | item in the table is the same opcode but with | |
ae57792d HPN |
2055 | matching operands. First skip any invalid ones. */ |
2056 | while (instruction[1].name != NULL | |
2057 | && strcmp (instruction->name, instruction[1].name) == 0 | |
2058 | && ! cris_insn_ver_valid_for_arch (instruction[1] | |
2059 | .applicable_version, | |
2060 | cris_arch)) | |
2061 | ++instruction; | |
2062 | ||
3bcbcc3d | 2063 | if (instruction[1].name != NULL |
ae57792d HPN |
2064 | && strcmp (instruction->name, instruction[1].name) == 0 |
2065 | && cris_insn_ver_valid_for_arch (instruction[1] | |
2066 | .applicable_version, | |
2067 | cris_arch)) | |
3bcbcc3d HPN |
2068 | { |
2069 | /* Yep. Restart and try that one instead. */ | |
2070 | ++instruction; | |
2071 | s = operands; | |
2072 | continue; | |
2073 | } | |
2074 | else | |
2075 | { | |
2076 | /* We've come to the end of instructions with this | |
2077 | opcode, so it must be an error. */ | |
2078 | as_bad (_("Illegal operands")); | |
ae57792d HPN |
2079 | |
2080 | /* As discard_rest_of_line, but without continuing to the | |
2081 | next line. */ | |
2082 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2083 | input_line_pointer++; | |
3bcbcc3d HPN |
2084 | return; |
2085 | } | |
2086 | } | |
2087 | else | |
2088 | { | |
2089 | /* We have a match. Check if there's anything more to do. */ | |
2090 | if (imm_expr_found) | |
2091 | { | |
2092 | /* There was an immediate mode operand, so we must check | |
2093 | that it has an appropriate size. */ | |
3bcbcc3d HPN |
2094 | switch (instruction->imm_oprnd_size) |
2095 | { | |
2096 | default: | |
2097 | case SIZE_NONE: | |
2098 | /* Shouldn't happen; this one does not have immediate | |
2099 | operands with different sizes. */ | |
2100 | BAD_CASE (instruction->imm_oprnd_size); | |
2101 | break; | |
2102 | ||
2103 | case SIZE_FIX_32: | |
2104 | out_insnp->imm_oprnd_size = 4; | |
2105 | break; | |
2106 | ||
2107 | case SIZE_SPEC_REG: | |
ae57792d HPN |
2108 | if (cris_arch == arch_crisv32) |
2109 | /* All immediate loads of special registers are | |
2110 | 32-bit on CRISv32. */ | |
2111 | out_insnp->imm_oprnd_size = 4; | |
2112 | else | |
2113 | switch (out_insnp->spec_reg->reg_size) | |
2114 | { | |
2115 | case 1: | |
2116 | if (out_insnp->expr.X_op == O_constant | |
2117 | && (out_insnp->expr.X_add_number < -128 | |
2118 | || out_insnp->expr.X_add_number > 255)) | |
2119 | as_bad (_("Immediate value not in 8 bit range: %ld"), | |
2120 | out_insnp->expr.X_add_number); | |
2121 | /* Fall through. */ | |
2122 | case 2: | |
2123 | /* FIXME: We need an indicator in the instruction | |
2124 | table to pass on, to indicate if we need to check | |
2125 | overflow for a signed or unsigned number. */ | |
2126 | if (out_insnp->expr.X_op == O_constant | |
2127 | && (out_insnp->expr.X_add_number < -32768 | |
2128 | || out_insnp->expr.X_add_number > 65535)) | |
2129 | as_bad (_("Immediate value not in 16 bit range: %ld"), | |
2130 | out_insnp->expr.X_add_number); | |
2131 | out_insnp->imm_oprnd_size = 2; | |
2132 | break; | |
2133 | ||
2134 | case 4: | |
2135 | out_insnp->imm_oprnd_size = 4; | |
2136 | break; | |
2137 | ||
2138 | default: | |
2139 | BAD_CASE (out_insnp->spec_reg->reg_size); | |
2140 | } | |
3bcbcc3d HPN |
2141 | break; |
2142 | ||
2143 | case SIZE_FIELD: | |
ae57792d HPN |
2144 | case SIZE_FIELD_SIGNED: |
2145 | case SIZE_FIELD_UNSIGNED: | |
3bcbcc3d HPN |
2146 | switch (size_bits) |
2147 | { | |
ae57792d HPN |
2148 | /* FIXME: Find way to pass un/signedness to |
2149 | caller, and set reloc type instead, postponing | |
2150 | this check until cris_number_to_imm. That | |
2151 | necessarily corrects the reloc type for the | |
2152 | byte case, maybe requiring further changes. */ | |
3bcbcc3d | 2153 | case 0: |
ae57792d HPN |
2154 | if (out_insnp->expr.X_op == O_constant) |
2155 | { | |
2156 | if (instruction->imm_oprnd_size == SIZE_FIELD | |
2157 | && (out_insnp->expr.X_add_number < -128 | |
2158 | || out_insnp->expr.X_add_number > 255)) | |
2159 | as_bad (_("Immediate value not in 8 bit range: %ld"), | |
2160 | out_insnp->expr.X_add_number); | |
2161 | else if (instruction->imm_oprnd_size == SIZE_FIELD_SIGNED | |
2162 | && (out_insnp->expr.X_add_number < -128 | |
2163 | || out_insnp->expr.X_add_number > 127)) | |
2164 | as_bad (_("Immediate value not in 8 bit signed range: %ld"), | |
2165 | out_insnp->expr.X_add_number); | |
2166 | else if (instruction->imm_oprnd_size == SIZE_FIELD_UNSIGNED | |
2167 | && (out_insnp->expr.X_add_number < 0 | |
2168 | || out_insnp->expr.X_add_number > 255)) | |
2169 | as_bad (_("Immediate value not in 8 bit unsigned range: %ld"), | |
2170 | out_insnp->expr.X_add_number); | |
2171 | } | |
2172 | ||
47926f60 | 2173 | /* Fall through. */ |
3bcbcc3d | 2174 | case 1: |
ae57792d HPN |
2175 | if (out_insnp->expr.X_op == O_constant) |
2176 | { | |
2177 | if (instruction->imm_oprnd_size == SIZE_FIELD | |
2178 | && (out_insnp->expr.X_add_number < -32768 | |
2179 | || out_insnp->expr.X_add_number > 65535)) | |
2180 | as_bad (_("Immediate value not in 16 bit range: %ld"), | |
2181 | out_insnp->expr.X_add_number); | |
2182 | else if (instruction->imm_oprnd_size == SIZE_FIELD_SIGNED | |
2183 | && (out_insnp->expr.X_add_number < -32768 | |
2184 | || out_insnp->expr.X_add_number > 32767)) | |
2185 | as_bad (_("Immediate value not in 16 bit signed range: %ld"), | |
2186 | out_insnp->expr.X_add_number); | |
2187 | else if (instruction->imm_oprnd_size == SIZE_FIELD_UNSIGNED | |
2188 | && (out_insnp->expr.X_add_number < 0 | |
2189 | || out_insnp->expr.X_add_number > 65535)) | |
2190 | as_bad (_("Immediate value not in 16 bit unsigned range: %ld"), | |
2191 | out_insnp->expr.X_add_number); | |
2192 | } | |
3bcbcc3d HPN |
2193 | out_insnp->imm_oprnd_size = 2; |
2194 | break; | |
2195 | ||
2196 | case 2: | |
2197 | out_insnp->imm_oprnd_size = 4; | |
2198 | break; | |
2199 | ||
2200 | default: | |
2201 | BAD_CASE (out_insnp->spec_reg->reg_size); | |
2202 | } | |
2203 | } | |
08caf3f8 HPN |
2204 | |
2205 | /* If there was a relocation specified for the immediate | |
cc99daad HPN |
2206 | expression (i.e. it had a PIC or TLS modifier) check that the |
2207 | size of the relocation matches the size specified by | |
08caf3f8 HPN |
2208 | the opcode. */ |
2209 | if (out_insnp->reloc != BFD_RELOC_NONE | |
cc99daad | 2210 | && (cris_get_specified_reloc_size (out_insnp->reloc) |
08caf3f8 | 2211 | != (unsigned int) out_insnp->imm_oprnd_size)) |
cc99daad HPN |
2212 | as_bad (out_insnp->reloc == BFD_RELOC_CRIS_32_GD |
2213 | || out_insnp->reloc == BFD_RELOC_CRIS_32_TPREL | |
2214 | || out_insnp->reloc == BFD_RELOC_CRIS_16_TPREL | |
5a00ea25 | 2215 | || out_insnp->reloc == BFD_RELOC_CRIS_32_IE |
cc99daad HPN |
2216 | ? _("TLS relocation size does not match operand size") |
2217 | : _("PIC relocation size does not match operand size")); | |
3bcbcc3d | 2218 | } |
1048a9ba HPN |
2219 | else if (instruction->op == cris_muls_op |
2220 | || instruction->op == cris_mulu_op) | |
2221 | out_insnp->insn_type = CRIS_INSN_MUL; | |
3bcbcc3d HPN |
2222 | } |
2223 | break; | |
2224 | } | |
2225 | } | |
2226 | ||
3bcbcc3d HPN |
2227 | /* Get a B, W, or D size modifier from the string pointed out by *cPP, |
2228 | which must point to a '.' in front of the modifier. On successful | |
2229 | return, *cPP is advanced to the character following the size | |
2230 | modifier, and is undefined otherwise. | |
2231 | ||
2232 | cPP Pointer to pointer to string starting | |
2233 | with the size modifier. | |
2234 | ||
2235 | size_bitsp Pointer to variable to contain the size bits on | |
2236 | successful return. | |
2237 | ||
2238 | Return 1 iff a correct size modifier is found, else 0. */ | |
2239 | ||
2240 | static int | |
695a4822 | 2241 | get_bwd_size_modifier (char **cPP, int *size_bitsp) |
3bcbcc3d HPN |
2242 | { |
2243 | if (**cPP != '.') | |
2244 | return 0; | |
2245 | else | |
2246 | { | |
47926f60 | 2247 | /* Consume the '.'. */ |
3bcbcc3d HPN |
2248 | (*cPP)++; |
2249 | ||
2250 | switch (**cPP) | |
2251 | { | |
2252 | case 'B': | |
2253 | case 'b': | |
2254 | *size_bitsp = 0; | |
2255 | break; | |
2256 | ||
2257 | case 'W': | |
2258 | case 'w': | |
2259 | *size_bitsp = 1; | |
2260 | break; | |
2261 | ||
2262 | case 'D': | |
2263 | case 'd': | |
2264 | *size_bitsp = 2; | |
2265 | break; | |
2266 | ||
2267 | default: | |
2268 | return 0; | |
2269 | } | |
2270 | ||
2271 | /* Consume the size letter. */ | |
2272 | (*cPP)++; | |
2273 | return 1; | |
2274 | } | |
2275 | } | |
2276 | ||
3bcbcc3d HPN |
2277 | /* Get a B or W size modifier from the string pointed out by *cPP, |
2278 | which must point to a '.' in front of the modifier. On successful | |
2279 | return, *cPP is advanced to the character following the size | |
2280 | modifier, and is undefined otherwise. | |
2281 | ||
2282 | cPP Pointer to pointer to string starting | |
2283 | with the size modifier. | |
2284 | ||
2285 | size_bitsp Pointer to variable to contain the size bits on | |
2286 | successful return. | |
2287 | ||
2288 | Return 1 iff a correct size modifier is found, else 0. */ | |
2289 | ||
2290 | static int | |
695a4822 | 2291 | get_bw_size_modifier (char **cPP, int *size_bitsp) |
3bcbcc3d HPN |
2292 | { |
2293 | if (**cPP != '.') | |
2294 | return 0; | |
2295 | else | |
2296 | { | |
47926f60 | 2297 | /* Consume the '.'. */ |
3bcbcc3d HPN |
2298 | (*cPP)++; |
2299 | ||
2300 | switch (**cPP) | |
2301 | { | |
2302 | case 'B': | |
2303 | case 'b': | |
2304 | *size_bitsp = 0; | |
2305 | break; | |
2306 | ||
2307 | case 'W': | |
2308 | case 'w': | |
2309 | *size_bitsp = 1; | |
2310 | break; | |
2311 | ||
2312 | default: | |
2313 | return 0; | |
2314 | } | |
2315 | ||
2316 | /* Consume the size letter. */ | |
2317 | (*cPP)++; | |
2318 | return 1; | |
2319 | } | |
2320 | } | |
2321 | ||
07e90ad5 | 2322 | /* Get a general register from the string pointed out by *cPP. The |
3bcbcc3d HPN |
2323 | variable *cPP is advanced to the character following the general |
2324 | register name on a successful return, and has its initial position | |
2325 | otherwise. | |
2326 | ||
2327 | cPP Pointer to pointer to string, beginning with a general | |
2328 | register name. | |
2329 | ||
2330 | regnop Pointer to int containing the register number. | |
2331 | ||
2332 | Return 1 iff a correct general register designator is found, | |
2333 | else 0. */ | |
2334 | ||
2335 | static int | |
695a4822 | 2336 | get_gen_reg (char **cPP, int *regnop) |
3bcbcc3d HPN |
2337 | { |
2338 | char *oldp; | |
2339 | oldp = *cPP; | |
2340 | ||
7b15d668 HPN |
2341 | /* Handle a sometimes-mandatory dollar sign as register prefix. */ |
2342 | if (**cPP == REGISTER_PREFIX_CHAR) | |
2343 | (*cPP)++; | |
2344 | else if (demand_register_prefix) | |
2345 | return 0; | |
2346 | ||
3bcbcc3d HPN |
2347 | switch (**cPP) |
2348 | { | |
2349 | case 'P': | |
2350 | case 'p': | |
2351 | /* "P" as in "PC"? Consume the "P". */ | |
2352 | (*cPP)++; | |
2353 | ||
2354 | if ((**cPP == 'C' || **cPP == 'c') | |
ae57792d HPN |
2355 | && ! ISALNUM ((*cPP)[1]) |
2356 | /* Here's a little twist: For v32 and the compatibility mode, | |
2357 | we only recognize PC as a register number if there's '+]' | |
2358 | after. We don't consume that, but the presence can only be | |
2359 | valid after a register in a post-increment context, which | |
2360 | is also the only valid context for PC as a register for | |
2361 | v32. Not that it's used very often, but saying "MOVE.D | |
2362 | [PC+],R5" should remain valid. It's not supported for | |
2363 | jump-type insns or other insns with no [Rn+] mode, though. */ | |
2364 | && ((cris_arch != arch_crisv32 | |
2365 | && cris_arch != arch_cris_common_v10_v32) | |
2366 | || ((*cPP)[1] == '+' && (*cPP)[2] == ']'))) | |
3bcbcc3d HPN |
2367 | { |
2368 | /* It's "PC": consume the "c" and we're done. */ | |
2369 | (*cPP)++; | |
2370 | *regnop = REG_PC; | |
2371 | return 1; | |
2372 | } | |
2373 | break; | |
2374 | ||
ae57792d HPN |
2375 | /* Like with PC, we recognize ACR, but only if it's *not* followed |
2376 | by '+', and only for v32. */ | |
2377 | case 'A': | |
2378 | case 'a': | |
2379 | if (cris_arch != arch_crisv32 | |
2380 | || ((*cPP)[1] != 'c' && (*cPP)[1] != 'C') | |
2381 | || ((*cPP)[2] != 'r' && (*cPP)[2] != 'R') | |
2382 | || ISALNUM ((*cPP)[3]) | |
2383 | || (*cPP)[3] == '+') | |
2384 | break; | |
2385 | (*cPP) += 3; | |
2386 | *regnop = 15; | |
2387 | return 1; | |
2388 | ||
3bcbcc3d HPN |
2389 | case 'R': |
2390 | case 'r': | |
47926f60 | 2391 | /* Hopefully r[0-9] or r1[0-5]. Consume 'R' or 'r'. */ |
3bcbcc3d HPN |
2392 | (*cPP)++; |
2393 | ||
3882b010 | 2394 | if (ISDIGIT (**cPP)) |
3bcbcc3d HPN |
2395 | { |
2396 | /* It's r[0-9]. Consume and check the next digit. */ | |
2397 | *regnop = **cPP - '0'; | |
2398 | (*cPP)++; | |
2399 | ||
3882b010 | 2400 | if (! ISALNUM (**cPP)) |
3bcbcc3d | 2401 | { |
47926f60 | 2402 | /* No more digits, we're done. */ |
3bcbcc3d HPN |
2403 | return 1; |
2404 | } | |
2405 | else | |
2406 | { | |
2407 | /* One more digit. Consume and add. */ | |
47926f60 | 2408 | *regnop = *regnop * 10 + (**cPP - '0'); |
3bcbcc3d HPN |
2409 | |
2410 | /* We need to check for a valid register number; Rn, | |
2411 | 0 <= n <= MAX_REG. */ | |
2412 | if (*regnop <= MAX_REG) | |
2413 | { | |
2414 | /* Consume second digit. */ | |
2415 | (*cPP)++; | |
2416 | return 1; | |
2417 | } | |
2418 | } | |
2419 | } | |
2420 | break; | |
2421 | ||
2422 | case 'S': | |
2423 | case 's': | |
2424 | /* "S" as in "SP"? Consume the "S". */ | |
2425 | (*cPP)++; | |
2426 | if (**cPP == 'P' || **cPP == 'p') | |
2427 | { | |
2428 | /* It's "SP": consume the "p" and we're done. */ | |
2429 | (*cPP)++; | |
2430 | *regnop = REG_SP; | |
2431 | return 1; | |
2432 | } | |
2433 | break; | |
2434 | ||
2435 | default: | |
2436 | /* Just here to silence compilation warnings. */ | |
2437 | ; | |
2438 | } | |
2439 | ||
2440 | /* We get here if we fail. Restore the pointer. */ | |
2441 | *cPP = oldp; | |
2442 | return 0; | |
2443 | } | |
2444 | ||
3bcbcc3d HPN |
2445 | /* Get a special register from the string pointed out by *cPP. The |
2446 | variable *cPP is advanced to the character following the special | |
2447 | register name if one is found, and retains its original position | |
2448 | otherwise. | |
2449 | ||
2450 | cPP Pointer to pointer to string starting with a special register | |
2451 | name. | |
2452 | ||
2453 | sregpp Pointer to Pointer to struct spec_reg, where a pointer to the | |
2454 | register description will be stored. | |
2455 | ||
2456 | Return 1 iff a correct special register name is found. */ | |
2457 | ||
2458 | static int | |
695a4822 | 2459 | get_spec_reg (char **cPP, const struct cris_spec_reg **sregpp) |
3bcbcc3d HPN |
2460 | { |
2461 | char *s1; | |
2462 | const char *s2; | |
7b15d668 | 2463 | char *name_begin = *cPP; |
3bcbcc3d HPN |
2464 | |
2465 | const struct cris_spec_reg *sregp; | |
2466 | ||
7b15d668 HPN |
2467 | /* Handle a sometimes-mandatory dollar sign as register prefix. */ |
2468 | if (*name_begin == REGISTER_PREFIX_CHAR) | |
2469 | name_begin++; | |
2470 | else if (demand_register_prefix) | |
2471 | return 0; | |
2472 | ||
3bcbcc3d | 2473 | /* Loop over all special registers. */ |
47926f60 | 2474 | for (sregp = cris_spec_regs; sregp->name != NULL; sregp++) |
3bcbcc3d | 2475 | { |
3bcbcc3d | 2476 | /* Start over from beginning of the supposed name. */ |
7b15d668 | 2477 | s1 = name_begin; |
3bcbcc3d HPN |
2478 | s2 = sregp->name; |
2479 | ||
3882b010 | 2480 | while (*s2 != '\0' && TOLOWER (*s1) == *s2) |
3bcbcc3d HPN |
2481 | { |
2482 | s1++; | |
2483 | s2++; | |
2484 | } | |
2485 | ||
2486 | /* For a match, we must have consumed the name in the table, and we | |
2487 | must be outside what could be part of a name. Assume here that a | |
47926f60 | 2488 | test for alphanumerics is sufficient for a name test. */ |
ae57792d HPN |
2489 | if (*s2 == 0 && ! ISALNUM (*s1) |
2490 | && cris_insn_ver_valid_for_arch (sregp->applicable_version, | |
2491 | cris_arch)) | |
3bcbcc3d | 2492 | { |
47926f60 | 2493 | /* We have a match. Update the pointer and be done. */ |
3bcbcc3d HPN |
2494 | *cPP = s1; |
2495 | *sregpp = sregp; | |
2496 | return 1; | |
2497 | } | |
2498 | } | |
2499 | ||
47926f60 | 2500 | /* If we got here, we did not find any name. */ |
3bcbcc3d HPN |
2501 | return 0; |
2502 | } | |
2503 | ||
ae57792d HPN |
2504 | /* Get a support register from the string pointed out by *cPP. The |
2505 | variable *cPP is advanced to the character following the support- | |
2506 | register name if one is found, and retains its original position | |
2507 | otherwise. | |
2508 | ||
2509 | cPP Pointer to pointer to string starting with a support-register | |
2510 | name. | |
2511 | ||
2512 | sregpp Pointer to int containing the register number. | |
2513 | ||
2514 | Return 1 iff a correct support-register name is found. */ | |
2515 | ||
2516 | static int | |
695a4822 | 2517 | get_sup_reg (char **cPP, int *regnop) |
ae57792d HPN |
2518 | { |
2519 | char *s1; | |
2520 | const char *s2; | |
2521 | char *name_begin = *cPP; | |
2522 | ||
2523 | const struct cris_support_reg *sregp; | |
2524 | ||
2525 | /* Handle a sometimes-mandatory dollar sign as register prefix. */ | |
2526 | if (*name_begin == REGISTER_PREFIX_CHAR) | |
2527 | name_begin++; | |
2528 | else if (demand_register_prefix) | |
2529 | return 0; | |
2530 | ||
2531 | /* Loop over all support-registers. */ | |
2532 | for (sregp = cris_support_regs; sregp->name != NULL; sregp++) | |
2533 | { | |
2534 | /* Start over from beginning of the supposed name. */ | |
2535 | s1 = name_begin; | |
2536 | s2 = sregp->name; | |
2537 | ||
2538 | while (*s2 != '\0' && TOLOWER (*s1) == *s2) | |
2539 | { | |
2540 | s1++; | |
2541 | s2++; | |
2542 | } | |
2543 | ||
2544 | /* For a match, we must have consumed the name in the table, and we | |
2545 | must be outside what could be part of a name. Assume here that a | |
2546 | test for alphanumerics is sufficient for a name test. */ | |
2547 | if (*s2 == 0 && ! ISALNUM (*s1)) | |
2548 | { | |
2549 | /* We have a match. Update the pointer and be done. */ | |
2550 | *cPP = s1; | |
2551 | *regnop = sregp->number; | |
2552 | return 1; | |
2553 | } | |
2554 | } | |
2555 | ||
2556 | /* If we got here, we did not find any name. */ | |
2557 | return 0; | |
2558 | } | |
2559 | ||
3bcbcc3d HPN |
2560 | /* Get an unprefixed or side-effect-prefix operand from the string pointed |
2561 | out by *cPP. The pointer *cPP is advanced to the character following | |
2562 | the indirect operand if we have success, else it contains an undefined | |
2563 | value. | |
2564 | ||
2565 | cPP Pointer to pointer to string beginning with the first | |
2566 | character of the supposed operand. | |
2567 | ||
2568 | prefixp Pointer to structure containing an optional instruction | |
2569 | prefix. | |
2570 | ||
2571 | is_autoincp Pointer to int indicating the indirect or autoincrement | |
2572 | bits. | |
2573 | ||
2574 | src_regnop Pointer to int containing the source register number in | |
2575 | the instruction. | |
2576 | ||
2577 | imm_foundp Pointer to an int indicating if an immediate expression | |
2578 | is found. | |
2579 | ||
2580 | imm_exprP Pointer to a structure containing an immediate | |
2581 | expression, if success and if *imm_foundp is nonzero. | |
2582 | ||
2583 | Return 1 iff a correct indirect operand is found. */ | |
2584 | ||
2585 | static int | |
695a4822 HPN |
2586 | get_autoinc_prefix_or_indir_op (char **cPP, struct cris_prefix *prefixp, |
2587 | int *is_autoincp, int *src_regnop, | |
2588 | int *imm_foundp, expressionS *imm_exprP) | |
3bcbcc3d HPN |
2589 | { |
2590 | /* Assume there was no immediate mode expression. */ | |
2591 | *imm_foundp = 0; | |
2592 | ||
2593 | if (**cPP == '[') | |
2594 | { | |
2595 | /* So this operand is one of: | |
2596 | Indirect: [rN] | |
2597 | Autoincrement: [rN+] | |
2598 | Indexed with assign: [rN=rM+rO.S] | |
2599 | Offset with assign: [rN=rM+I], [rN=rM+[rO].s], [rN=rM+[rO+].s] | |
2600 | ||
2601 | Either way, consume the '['. */ | |
2602 | (*cPP)++; | |
2603 | ||
2604 | /* Get the rN register. */ | |
2605 | if (! get_gen_reg (cPP, src_regnop)) | |
2606 | /* If there was no register, then this cannot match. */ | |
2607 | return 0; | |
2608 | else | |
2609 | { | |
2610 | /* We got the register, now check the next character. */ | |
2611 | switch (**cPP) | |
2612 | { | |
2613 | case ']': | |
2614 | /* Indirect mode. We're done here. */ | |
2615 | prefixp->kind = PREFIX_NONE; | |
2616 | *is_autoincp = 0; | |
2617 | break; | |
2618 | ||
2619 | case '+': | |
2620 | /* This must be an auto-increment mode, if there's a | |
2621 | match. */ | |
2622 | prefixp->kind = PREFIX_NONE; | |
2623 | *is_autoincp = 1; | |
2624 | ||
2625 | /* We consume this character and break out to check the | |
2626 | closing ']'. */ | |
2627 | (*cPP)++; | |
2628 | break; | |
2629 | ||
2630 | case '=': | |
2631 | /* This must be indexed with assign, or offset with assign | |
ae57792d HPN |
2632 | to match. Not supported for crisv32 or in |
2633 | compatibility mode. */ | |
2634 | if (cris_arch == arch_crisv32 | |
2635 | || cris_arch == arch_cris_common_v10_v32) | |
2636 | return 0; | |
2637 | ||
3bcbcc3d HPN |
2638 | (*cPP)++; |
2639 | ||
2640 | /* Either way, the next thing must be a register. */ | |
2641 | if (! get_gen_reg (cPP, &prefixp->base_reg_number)) | |
2642 | /* No register, no match. */ | |
2643 | return 0; | |
2644 | else | |
2645 | { | |
2646 | /* We've consumed "[rN=rM", so we must be looking at | |
2647 | "+rO.s]" or "+I]", or "-I]", or "+[rO].s]" or | |
2648 | "+[rO+].s]". */ | |
2649 | if (**cPP == '+') | |
2650 | { | |
2651 | int index_reg_number; | |
2652 | (*cPP)++; | |
2653 | ||
2654 | if (**cPP == '[') | |
2655 | { | |
2656 | int size_bits; | |
2657 | /* This must be [rx=ry+[rz].s] or | |
2658 | [rx=ry+[rz+].s] or no match. We must be | |
2659 | looking at rz after consuming the '['. */ | |
2660 | (*cPP)++; | |
2661 | ||
2662 | if (!get_gen_reg (cPP, &index_reg_number)) | |
2663 | return 0; | |
2664 | ||
2665 | prefixp->kind = PREFIX_BDAP; | |
2666 | prefixp->opcode | |
2667 | = (BDAP_INDIR_OPCODE | |
2668 | + (prefixp->base_reg_number << 12) | |
2669 | + index_reg_number); | |
2670 | ||
2671 | if (**cPP == '+') | |
2672 | { | |
2673 | /* We've seen "[rx=ry+[rz+" here, so now we | |
2674 | know that there must be "].s]" left to | |
2675 | check. */ | |
2676 | (*cPP)++; | |
2677 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
2678 | } | |
2679 | ||
2680 | /* If it wasn't autoincrement, we don't need to | |
2681 | add anything. */ | |
2682 | ||
2683 | /* Check the next-to-last ']'. */ | |
2684 | if (**cPP != ']') | |
2685 | return 0; | |
2686 | ||
2687 | (*cPP)++; | |
2688 | ||
2689 | /* Check the ".s" modifier. */ | |
2690 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
2691 | return 0; | |
2692 | ||
2693 | prefixp->opcode |= size_bits << 4; | |
2694 | ||
2695 | /* Now we got [rx=ry+[rz+].s or [rx=ry+[rz].s. | |
2696 | We break out to check the final ']'. */ | |
2697 | break; | |
2698 | } | |
ab3e48dc KH |
2699 | /* It wasn't an indirection. Check if it's a |
2700 | register. */ | |
2701 | else if (get_gen_reg (cPP, &index_reg_number)) | |
47926f60 KH |
2702 | { |
2703 | int size_bits; | |
2704 | ||
2705 | /* Indexed with assign mode: "[rN+rM.S]". */ | |
2706 | prefixp->kind = PREFIX_BIAP; | |
2707 | prefixp->opcode | |
2708 | = (BIAP_OPCODE + (index_reg_number << 12) | |
2709 | + prefixp->base_reg_number /* << 0 */); | |
2710 | ||
2711 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
2712 | /* Size missing, this isn't a match. */ | |
2713 | return 0; | |
2714 | else | |
3bcbcc3d | 2715 | { |
47926f60 | 2716 | /* Size found, break out to check the |
3bcbcc3d | 2717 | final ']'. */ |
47926f60 | 2718 | prefixp->opcode |= size_bits << 4; |
3bcbcc3d HPN |
2719 | break; |
2720 | } | |
47926f60 KH |
2721 | } |
2722 | /* Not a register. Then this must be "[rN+I]". */ | |
2723 | else if (cris_get_expression (cPP, &prefixp->expr)) | |
2724 | { | |
2725 | /* We've got offset with assign mode. Fill | |
2726 | in the blanks and break out to match the | |
2727 | final ']'. */ | |
2728 | prefixp->kind = PREFIX_BDAP_IMM; | |
08caf3f8 HPN |
2729 | |
2730 | /* We tentatively put an opcode corresponding to | |
2731 | a 32-bit operand here, although it may be | |
cc99daad HPN |
2732 | relaxed when there's no relocation |
2733 | specifier for the operand. */ | |
08caf3f8 HPN |
2734 | prefixp->opcode |
2735 | = (BDAP_INDIR_OPCODE | |
2736 | | (prefixp->base_reg_number << 12) | |
2737 | | (AUTOINCR_BIT << 8) | |
2738 | | (2 << 4) | |
2739 | | REG_PC /* << 0 */); | |
2740 | ||
2741 | /* This can have a PIC suffix, specifying reloc | |
2742 | type to use. */ | |
cc99daad | 2743 | if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR) |
08caf3f8 HPN |
2744 | { |
2745 | unsigned int relocsize; | |
2746 | ||
cc99daad HPN |
2747 | cris_get_reloc_suffix (cPP, &prefixp->reloc, |
2748 | &prefixp->expr); | |
08caf3f8 HPN |
2749 | |
2750 | /* Tweak the size of the immediate operand | |
2751 | in the prefix opcode if it isn't what we | |
2752 | set. */ | |
2753 | relocsize | |
cc99daad | 2754 | = cris_get_specified_reloc_size (prefixp->reloc); |
08caf3f8 HPN |
2755 | if (relocsize != 4) |
2756 | prefixp->opcode | |
2757 | = ((prefixp->opcode & ~(3 << 4)) | |
2758 | | ((relocsize >> 1) << 4)); | |
2759 | } | |
47926f60 KH |
2760 | break; |
2761 | } | |
2762 | else | |
2763 | /* Neither register nor expression found, so | |
2764 | this can't be a match. */ | |
2765 | return 0; | |
3bcbcc3d | 2766 | } |
47926f60 | 2767 | /* Not "[rN+" but perhaps "[rN-"? */ |
ab3e48dc | 2768 | else if (**cPP == '-') |
47926f60 KH |
2769 | { |
2770 | /* We must have an offset with assign mode. */ | |
2771 | if (! cris_get_expression (cPP, &prefixp->expr)) | |
2772 | /* No expression, no match. */ | |
2773 | return 0; | |
2774 | else | |
2775 | { | |
2776 | /* We've got offset with assign mode. Fill | |
2777 | in the blanks and break out to match the | |
08caf3f8 HPN |
2778 | final ']'. |
2779 | ||
cc99daad HPN |
2780 | Note that we don't allow a relocation |
2781 | suffix for an operand with a minus | |
2782 | sign. */ | |
47926f60 KH |
2783 | prefixp->kind = PREFIX_BDAP_IMM; |
2784 | break; | |
2785 | } | |
2786 | } | |
2787 | else | |
2788 | /* Neither '+' nor '-' after "[rN=rM". Lose. */ | |
2789 | return 0; | |
3bcbcc3d HPN |
2790 | } |
2791 | default: | |
2792 | /* Neither ']' nor '+' nor '=' after "[rN". Lose. */ | |
2793 | return 0; | |
2794 | } | |
2795 | } | |
2796 | ||
2797 | /* When we get here, we have a match and will just check the closing | |
2798 | ']'. We can still fail though. */ | |
2799 | if (**cPP != ']') | |
2800 | return 0; | |
2801 | else | |
2802 | { | |
2803 | /* Don't forget to consume the final ']'. | |
2804 | Then return in glory. */ | |
2805 | (*cPP)++; | |
2806 | return 1; | |
2807 | } | |
2808 | } | |
47926f60 | 2809 | /* No indirection. Perhaps a constant? */ |
ab3e48dc | 2810 | else if (cris_get_expression (cPP, imm_exprP)) |
47926f60 KH |
2811 | { |
2812 | /* Expression found, this is immediate mode. */ | |
2813 | prefixp->kind = PREFIX_NONE; | |
2814 | *is_autoincp = 1; | |
2815 | *src_regnop = REG_PC; | |
2816 | *imm_foundp = 1; | |
08caf3f8 HPN |
2817 | |
2818 | /* This can have a PIC suffix, specifying reloc type to use. The | |
2819 | caller must check that the reloc size matches the operand size. */ | |
cc99daad HPN |
2820 | if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR) |
2821 | cris_get_reloc_suffix (cPP, &prefixp->reloc, imm_exprP); | |
08caf3f8 | 2822 | |
47926f60 KH |
2823 | return 1; |
2824 | } | |
3bcbcc3d HPN |
2825 | |
2826 | /* No luck today. */ | |
2827 | return 0; | |
2828 | } | |
2829 | ||
3bcbcc3d HPN |
2830 | /* This function gets an indirect operand in a three-address operand |
2831 | combination from the string pointed out by *cPP. The pointer *cPP is | |
2832 | advanced to the character following the indirect operand on success, or | |
2833 | has an unspecified value on failure. | |
2834 | ||
2d2255b5 | 2835 | cPP Pointer to pointer to string beginning |
3bcbcc3d HPN |
2836 | with the operand |
2837 | ||
2838 | prefixp Pointer to structure containing an | |
2839 | instruction prefix | |
2840 | ||
2841 | Returns 1 iff a correct indirect operand is found. */ | |
2842 | ||
2843 | static int | |
695a4822 | 2844 | get_3op_or_dip_prefix_op (char **cPP, struct cris_prefix *prefixp) |
3bcbcc3d | 2845 | { |
ab3e48dc KH |
2846 | int reg_number; |
2847 | ||
3bcbcc3d HPN |
2848 | if (**cPP != '[') |
2849 | /* We must have a '[' or it's a clean failure. */ | |
2850 | return 0; | |
3bcbcc3d | 2851 | |
47926f60 KH |
2852 | /* Eat the first '['. */ |
2853 | (*cPP)++; | |
2854 | ||
2855 | if (**cPP == '[') | |
2856 | { | |
2857 | /* A second '[', so this must be double-indirect mode. */ | |
3bcbcc3d | 2858 | (*cPP)++; |
47926f60 KH |
2859 | prefixp->kind = PREFIX_DIP; |
2860 | prefixp->opcode = DIP_OPCODE; | |
3bcbcc3d | 2861 | |
47926f60 KH |
2862 | /* Get the register or fail entirely. */ |
2863 | if (! get_gen_reg (cPP, ®_number)) | |
2864 | return 0; | |
2865 | else | |
3bcbcc3d | 2866 | { |
47926f60 KH |
2867 | prefixp->opcode |= reg_number /* << 0 */ ; |
2868 | if (**cPP == '+') | |
2869 | { | |
2870 | /* Since we found a '+', this must be double-indirect | |
2871 | autoincrement mode. */ | |
2872 | (*cPP)++; | |
2873 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
2874 | } | |
2875 | ||
2876 | /* There's nothing particular to do, if this was a | |
2877 | double-indirect *without* autoincrement. */ | |
2878 | } | |
2879 | ||
2880 | /* Check the first ']'. The second one is checked at the end. */ | |
2881 | if (**cPP != ']') | |
2882 | return 0; | |
2883 | ||
2884 | /* Eat the first ']', so we'll be looking at a second ']'. */ | |
2885 | (*cPP)++; | |
2886 | } | |
2887 | /* No second '['. Then we should have a register here, making | |
2888 | it "[rN". */ | |
2889 | else if (get_gen_reg (cPP, &prefixp->base_reg_number)) | |
2890 | { | |
2891 | /* This must be indexed or offset mode: "[rN+I]" or | |
2892 | "[rN+rM.S]" or "[rN+[rM].S]" or "[rN+[rM+].S]". */ | |
2893 | if (**cPP == '+') | |
2894 | { | |
47926f60 KH |
2895 | int index_reg_number; |
2896 | ||
3bcbcc3d | 2897 | (*cPP)++; |
3bcbcc3d | 2898 | |
47926f60 | 2899 | if (**cPP == '[') |
3bcbcc3d | 2900 | { |
47926f60 KH |
2901 | /* This is "[rx+["... Expect a register next. */ |
2902 | int size_bits; | |
2903 | (*cPP)++; | |
2904 | ||
2905 | if (!get_gen_reg (cPP, &index_reg_number)) | |
2906 | return 0; | |
2907 | ||
2908 | prefixp->kind = PREFIX_BDAP; | |
2909 | prefixp->opcode | |
2910 | = (BDAP_INDIR_OPCODE | |
2911 | + (prefixp->base_reg_number << 12) | |
2912 | + index_reg_number); | |
2913 | ||
2914 | /* We've seen "[rx+[ry", so check if this is | |
2915 | autoincrement. */ | |
3bcbcc3d HPN |
2916 | if (**cPP == '+') |
2917 | { | |
47926f60 | 2918 | /* Yep, now at "[rx+[ry+". */ |
3bcbcc3d HPN |
2919 | (*cPP)++; |
2920 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
2921 | } | |
47926f60 KH |
2922 | /* If it wasn't autoincrement, we don't need to |
2923 | add anything. */ | |
3bcbcc3d | 2924 | |
47926f60 KH |
2925 | /* Check a first closing ']': "[rx+[ry]" or |
2926 | "[rx+[ry+]". */ | |
2927 | if (**cPP != ']') | |
2928 | return 0; | |
2929 | (*cPP)++; | |
3bcbcc3d | 2930 | |
47926f60 KH |
2931 | /* Now expect a size modifier ".S". */ |
2932 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
2933 | return 0; | |
3bcbcc3d | 2934 | |
47926f60 KH |
2935 | prefixp->opcode |= size_bits << 4; |
2936 | ||
2937 | /* Ok, all interesting stuff has been seen: | |
2938 | "[rx+[ry+].S" or "[rx+[ry].S". We only need to | |
2939 | expect a final ']', which we'll do in a common | |
2940 | closing session. */ | |
2941 | } | |
2942 | /* Seen "[rN+", but not a '[', so check if we have a | |
2943 | register. */ | |
2944 | else if (get_gen_reg (cPP, &index_reg_number)) | |
2945 | { | |
2946 | /* This is indexed mode: "[rN+rM.S]" or | |
2947 | "[rN+rM.S+]". */ | |
2948 | int size_bits; | |
2949 | prefixp->kind = PREFIX_BIAP; | |
2950 | prefixp->opcode | |
2951 | = (BIAP_OPCODE | |
2952 | | prefixp->base_reg_number /* << 0 */ | |
2953 | | (index_reg_number << 12)); | |
2954 | ||
07e90ad5 | 2955 | /* Consume the ".S". */ |
47926f60 KH |
2956 | if (! get_bwd_size_modifier (cPP, &size_bits)) |
2957 | /* Missing size, so fail. */ | |
2958 | return 0; | |
3bcbcc3d | 2959 | else |
47926f60 KH |
2960 | /* Size found. Add that piece and drop down to |
2961 | the common checking of the closing ']'. */ | |
2962 | prefixp->opcode |= size_bits << 4; | |
2963 | } | |
2964 | /* Seen "[rN+", but not a '[' or a register, so then | |
ae57792d HPN |
2965 | it must be a constant "I". |
2966 | ||
2967 | As a quality of implementation improvement, we check for a | |
2968 | closing ']', like in an erroneous "[rN+]". If we don't, | |
2969 | the expression parser will emit a confusing "bad | |
2970 | expression" when it sees the ']', probably because it | |
2971 | doesn't like seeing no expression. */ | |
2972 | else if (**cPP != ']' && cris_get_expression (cPP, &prefixp->expr)) | |
47926f60 KH |
2973 | { |
2974 | /* Expression found, so fill in the bits of offset | |
2975 | mode and drop down to check the closing ']'. */ | |
2976 | prefixp->kind = PREFIX_BDAP_IMM; | |
08caf3f8 HPN |
2977 | |
2978 | /* We tentatively put an opcode corresponding to a 32-bit | |
2979 | operand here, although it may be relaxed when there's no | |
2980 | PIC specifier for the operand. */ | |
2981 | prefixp->opcode | |
2982 | = (BDAP_INDIR_OPCODE | |
2983 | | (prefixp->base_reg_number << 12) | |
2984 | | (AUTOINCR_BIT << 8) | |
2985 | | (2 << 4) | |
2986 | | REG_PC /* << 0 */); | |
2987 | ||
2988 | /* This can have a PIC suffix, specifying reloc type to use. */ | |
cc99daad | 2989 | if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR) |
08caf3f8 HPN |
2990 | { |
2991 | unsigned int relocsize; | |
2992 | ||
cc99daad | 2993 | cris_get_reloc_suffix (cPP, &prefixp->reloc, &prefixp->expr); |
08caf3f8 HPN |
2994 | |
2995 | /* Tweak the size of the immediate operand in the prefix | |
2996 | opcode if it isn't what we set. */ | |
cc99daad | 2997 | relocsize = cris_get_specified_reloc_size (prefixp->reloc); |
08caf3f8 HPN |
2998 | if (relocsize != 4) |
2999 | prefixp->opcode | |
3000 | = ((prefixp->opcode & ~(3 << 4)) | |
3001 | | ((relocsize >> 1) << 4)); | |
3002 | } | |
47926f60 KH |
3003 | } |
3004 | else | |
3005 | /* Nothing valid here: lose. */ | |
3006 | return 0; | |
3007 | } | |
3008 | /* Seen "[rN" but no '+', so check if it's a '-'. */ | |
3009 | else if (**cPP == '-') | |
3010 | { | |
3011 | /* Yep, we must have offset mode. */ | |
3012 | if (! cris_get_expression (cPP, &prefixp->expr)) | |
3013 | /* No expression, so we lose. */ | |
3014 | return 0; | |
3015 | else | |
3016 | { | |
3017 | /* Expression found to make this offset mode, so | |
3018 | fill those bits and drop down to check the | |
08caf3f8 HPN |
3019 | closing ']'. |
3020 | ||
3021 | Note that we don't allow a PIC suffix for | |
3022 | an operand with a minus sign like this. */ | |
47926f60 KH |
3023 | prefixp->kind = PREFIX_BDAP_IMM; |
3024 | } | |
3025 | } | |
3026 | else | |
3027 | { | |
3028 | /* We've seen "[rN", but not '+' or '-'; rather a ']'. | |
3029 | Hmm. Normally this is a simple indirect mode that we | |
3030 | shouldn't match, but if we expect ']', then we have a | |
3031 | zero offset, so it can be a three-address-operand, | |
3032 | like "[rN],rO,rP", thus offset mode. | |
3033 | ||
3034 | Don't eat the ']', that will be done in the closing | |
3035 | ceremony. */ | |
3036 | prefixp->expr.X_op = O_constant; | |
3037 | prefixp->expr.X_add_number = 0; | |
3038 | prefixp->expr.X_add_symbol = NULL; | |
3039 | prefixp->expr.X_op_symbol = NULL; | |
3040 | prefixp->kind = PREFIX_BDAP_IMM; | |
3041 | } | |
3042 | } | |
3043 | /* A '[', but no second '[', and no register. Check if we | |
3044 | have an expression, making this "[I]" for a double-indirect | |
3045 | prefix. */ | |
3046 | else if (cris_get_expression (cPP, &prefixp->expr)) | |
3047 | { | |
3048 | /* Expression found, the so called absolute mode for a | |
3049 | double-indirect prefix on PC. */ | |
3050 | prefixp->kind = PREFIX_DIP; | |
3051 | prefixp->opcode = DIP_OPCODE | (AUTOINCR_BIT << 8) | REG_PC; | |
3052 | prefixp->reloc = BFD_RELOC_32; | |
5a00ea25 HPN |
3053 | |
3054 | /* For :GD and :IE, it makes sense to have TLS specifiers here. */ | |
3055 | if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR) | |
3056 | cris_get_reloc_suffix (cPP, &prefixp->reloc, &prefixp->expr); | |
47926f60 KH |
3057 | } |
3058 | else | |
3059 | /* Neither '[' nor register nor expression. We lose. */ | |
3060 | return 0; | |
3bcbcc3d HPN |
3061 | |
3062 | /* We get here as a closing ceremony to a successful match. We just | |
3063 | need to check the closing ']'. */ | |
3064 | if (**cPP != ']') | |
3065 | /* Oops. Close but no air-polluter. */ | |
3066 | return 0; | |
3067 | ||
3068 | /* Don't forget to consume that ']', before returning in glory. */ | |
3069 | (*cPP)++; | |
3070 | return 1; | |
3071 | } | |
3072 | ||
3bcbcc3d HPN |
3073 | /* Get an expression from the string pointed out by *cPP. |
3074 | The pointer *cPP is advanced to the character following the expression | |
3075 | on a success, or retains its original value otherwise. | |
3076 | ||
3077 | cPP Pointer to pointer to string beginning with the expression. | |
3078 | ||
3079 | exprP Pointer to structure containing the expression. | |
3080 | ||
47926f60 | 3081 | Return 1 iff a correct expression is found. */ |
3bcbcc3d HPN |
3082 | |
3083 | static int | |
695a4822 | 3084 | cris_get_expression (char **cPP, expressionS *exprP) |
3bcbcc3d HPN |
3085 | { |
3086 | char *saved_input_line_pointer; | |
3bcbcc3d HPN |
3087 | |
3088 | /* The "expression" function expects to find an expression at the | |
3089 | global variable input_line_pointer, so we have to save it to give | |
3090 | the impression that we don't fiddle with global variables. */ | |
3091 | saved_input_line_pointer = input_line_pointer; | |
3092 | input_line_pointer = *cPP; | |
3093 | ||
ae57792d HPN |
3094 | /* Avoid a common error, confusing addressing modes. Beware that the |
3095 | call to expression below does not signal that error; it treats [] | |
3096 | as parentheses, unless #define NEED_INDEX_OPERATOR in which case it | |
3097 | gives them other confusing semantics rather than plain outlawing | |
3098 | them, which is what we want. */ | |
3099 | if (*input_line_pointer == '[') | |
3100 | { | |
3101 | input_line_pointer = saved_input_line_pointer; | |
3102 | return 0; | |
3103 | } | |
3104 | ||
87975d2a | 3105 | expression (exprP); |
3bcbcc3d HPN |
3106 | if (exprP->X_op == O_illegal || exprP->X_op == O_absent) |
3107 | { | |
3108 | input_line_pointer = saved_input_line_pointer; | |
3109 | return 0; | |
3110 | } | |
3111 | ||
3112 | /* Everything seems to be fine, just restore the global | |
3113 | input_line_pointer and say we're successful. */ | |
3114 | *cPP = input_line_pointer; | |
3115 | input_line_pointer = saved_input_line_pointer; | |
3116 | return 1; | |
3117 | } | |
3118 | ||
3bcbcc3d HPN |
3119 | /* Get a sequence of flag characters from *spp. The pointer *cPP is |
3120 | advanced to the character following the expression. The flag | |
3121 | characters are consecutive, no commas or spaces. | |
3122 | ||
3123 | cPP Pointer to pointer to string beginning with the expression. | |
3124 | ||
3125 | flagp Pointer to int to return the flags expression. | |
3126 | ||
3127 | Return 1 iff a correct flags expression is found. */ | |
3128 | ||
3129 | static int | |
695a4822 | 3130 | get_flags (char **cPP, int *flagsp) |
3bcbcc3d HPN |
3131 | { |
3132 | for (;;) | |
3133 | { | |
3134 | switch (**cPP) | |
3135 | { | |
3136 | case 'd': | |
3137 | case 'D': | |
ae57792d HPN |
3138 | if (! cris_insn_ver_valid_for_arch (cris_ver_v0_3, |
3139 | cris_arch)) | |
3140 | return 0; | |
3141 | *flagsp |= 0x80; | |
3142 | break; | |
3143 | ||
3bcbcc3d HPN |
3144 | case 'm': |
3145 | case 'M': | |
ae57792d HPN |
3146 | if (! cris_insn_ver_valid_for_arch (cris_ver_v8_10, |
3147 | cris_arch)) | |
3148 | return 0; | |
3bcbcc3d HPN |
3149 | *flagsp |= 0x80; |
3150 | break; | |
3151 | ||
3152 | case 'e': | |
3153 | case 'E': | |
ae57792d HPN |
3154 | if (! cris_insn_ver_valid_for_arch (cris_ver_v0_3, |
3155 | cris_arch)) | |
3156 | return 0; | |
3157 | *flagsp |= 0x40; | |
3158 | break; | |
3159 | ||
3bcbcc3d HPN |
3160 | case 'b': |
3161 | case 'B': | |
ae57792d HPN |
3162 | if (! cris_insn_ver_valid_for_arch (cris_ver_v8_10, |
3163 | cris_arch)) | |
3164 | return 0; | |
3165 | *flagsp |= 0x40; | |
3166 | break; | |
3167 | ||
3168 | case 'p': | |
3169 | case 'P': | |
3170 | if (! cris_insn_ver_valid_for_arch (cris_ver_v32p, | |
3171 | cris_arch)) | |
3172 | return 0; | |
3173 | *flagsp |= 0x80; | |
3174 | break; | |
3175 | ||
3176 | case 'u': | |
3177 | case 'U': | |
3178 | if (! cris_insn_ver_valid_for_arch (cris_ver_v32p, | |
3179 | cris_arch)) | |
3180 | return 0; | |
3bcbcc3d HPN |
3181 | *flagsp |= 0x40; |
3182 | break; | |
3183 | ||
3184 | case 'i': | |
3185 | case 'I': | |
3186 | *flagsp |= 0x20; | |
3187 | break; | |
3188 | ||
3189 | case 'x': | |
3190 | case 'X': | |
3191 | *flagsp |= 0x10; | |
3192 | break; | |
3193 | ||
3194 | case 'n': | |
3195 | case 'N': | |
3196 | *flagsp |= 0x8; | |
3197 | break; | |
3198 | ||
3199 | case 'z': | |
3200 | case 'Z': | |
3201 | *flagsp |= 0x4; | |
3202 | break; | |
3203 | ||
3204 | case 'v': | |
3205 | case 'V': | |
3206 | *flagsp |= 0x2; | |
3207 | break; | |
3208 | ||
3209 | case 'c': | |
3210 | case 'C': | |
3211 | *flagsp |= 1; | |
3212 | break; | |
3213 | ||
3214 | default: | |
3215 | /* We consider this successful if we stop at a comma or | |
47926f60 | 3216 | whitespace. Anything else, and we consider it a failure. */ |
3bcbcc3d HPN |
3217 | if (**cPP != ',' |
3218 | && **cPP != 0 | |
3882b010 | 3219 | && ! ISSPACE (**cPP)) |
3bcbcc3d HPN |
3220 | return 0; |
3221 | else | |
3222 | return 1; | |
3223 | } | |
3224 | ||
3225 | /* Don't forget to consume each flag character. */ | |
3226 | (*cPP)++; | |
3227 | } | |
3228 | } | |
3229 | ||
3bcbcc3d | 3230 | /* Generate code and fixes for a BDAP prefix. |
ae57792d HPN |
3231 | For v32, this handles ADDOQ because thankfully the opcodes are the |
3232 | same. | |
3bcbcc3d HPN |
3233 | |
3234 | base_regno Int containing the base register number. | |
3235 | ||
3236 | exprP Pointer to structure containing the offset expression. */ | |
3237 | ||
3238 | static void | |
695a4822 | 3239 | gen_bdap (int base_regno, expressionS *exprP) |
3bcbcc3d HPN |
3240 | { |
3241 | unsigned int opcode; | |
3242 | char *opcodep; | |
3243 | ||
3244 | /* Put out the prefix opcode; assume quick immediate mode at first. */ | |
3245 | opcode = BDAP_QUICK_OPCODE | (base_regno << 12); | |
ed67db7a | 3246 | opcodep = cris_insn_first_word_frag (); |
3bcbcc3d HPN |
3247 | md_number_to_chars (opcodep, opcode, 2); |
3248 | ||
3249 | if (exprP->X_op == O_constant) | |
3250 | { | |
3251 | /* We have an absolute expression that we know the size of right | |
47926f60 | 3252 | now. */ |
3bcbcc3d HPN |
3253 | long int value; |
3254 | int size; | |
3255 | ||
3256 | value = exprP->X_add_number; | |
3257 | if (value < -32768 || value > 32767) | |
3258 | /* Outside range for a "word", make it a dword. */ | |
3259 | size = 2; | |
3260 | else | |
47926f60 | 3261 | /* Assume "word" size. */ |
3bcbcc3d HPN |
3262 | size = 1; |
3263 | ||
3264 | /* If this is a signed-byte value, we can fit it into the prefix | |
3265 | insn itself. */ | |
3266 | if (value >= -128 && value <= 127) | |
3267 | opcodep[0] = value; | |
3268 | else | |
3269 | { | |
3270 | /* This is a word or dword displacement, which will be put in a | |
3271 | word or dword after the prefix. */ | |
3272 | char *p; | |
3273 | ||
3274 | opcodep[0] = BDAP_PC_LOW + (size << 4); | |
3275 | opcodep[1] &= 0xF0; | |
3276 | opcodep[1] |= BDAP_INCR_HIGH; | |
3277 | p = frag_more (1 << size); | |
3278 | md_number_to_chars (p, value, 1 << size); | |
3279 | } | |
3280 | } | |
3281 | else | |
08caf3f8 HPN |
3282 | { |
3283 | /* Handle complex expressions. */ | |
3284 | valueT addvalue | |
1c971160 | 3285 | = SIMPLE_EXPR (exprP) ? exprP->X_add_number : 0; |
08caf3f8 | 3286 | symbolS *sym |
1c971160 HPN |
3287 | = (SIMPLE_EXPR (exprP) |
3288 | ? exprP->X_add_symbol : make_expr_symbol (exprP)); | |
08caf3f8 HPN |
3289 | |
3290 | /* The expression is not defined yet but may become absolute. We | |
3291 | make it a relocation to be relaxed. */ | |
3292 | frag_var (rs_machine_dependent, 4, 0, | |
3293 | ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF), | |
3294 | sym, addvalue, opcodep); | |
3295 | } | |
3bcbcc3d HPN |
3296 | } |
3297 | ||
3bcbcc3d HPN |
3298 | /* Encode a branch displacement in the range -256..254 into the form used |
3299 | by CRIS conditional branch instructions. | |
3300 | ||
3301 | offset The displacement value in bytes. */ | |
3302 | ||
3303 | static int | |
695a4822 | 3304 | branch_disp (int offset) |
3bcbcc3d HPN |
3305 | { |
3306 | int disp; | |
3307 | ||
ae57792d HPN |
3308 | /* Adjust all short branch offsets here. */ |
3309 | if (cris_arch == arch_crisv32 || cris_arch == arch_cris_common_v10_v32) | |
3310 | offset += 2; | |
3311 | ||
3bcbcc3d HPN |
3312 | disp = offset & 0xFE; |
3313 | ||
3314 | if (offset < 0) | |
3315 | disp |= 1; | |
3316 | ||
3317 | return disp; | |
3318 | } | |
3319 | ||
3bcbcc3d HPN |
3320 | /* Generate code and fixes for a 32-bit conditional branch instruction |
3321 | created by "extending" an existing 8-bit branch instruction. | |
3322 | ||
3323 | opcodep Pointer to the word containing the original 8-bit branch | |
3324 | instruction. | |
3325 | ||
3326 | writep Pointer to "extension area" following the first instruction | |
3327 | word. | |
3328 | ||
3329 | fragP Pointer to the frag containing the instruction. | |
3330 | ||
3331 | add_symP, Parts of the destination address expression. | |
3332 | sub_symP, | |
3333 | add_num. */ | |
3334 | ||
3335 | static void | |
695a4822 HPN |
3336 | gen_cond_branch_32 (char *opcodep, char *writep, fragS *fragP, |
3337 | symbolS *add_symP, symbolS *sub_symP, long int add_num) | |
3bcbcc3d | 3338 | { |
ae57792d HPN |
3339 | int nop_opcode; |
3340 | int opc_offset; | |
3341 | int branch_offset; | |
3342 | ||
3343 | if (cris_arch == arch_crisv32) | |
3344 | { | |
3345 | nop_opcode = NOP_OPCODE_V32; | |
3346 | opc_offset = 10; | |
3347 | branch_offset = -2 - 8; | |
3348 | } | |
d2aa3f9f HPN |
3349 | else if (pic) |
3350 | { | |
3351 | nop_opcode = NOP_OPCODE; | |
3352 | opc_offset = 10; | |
3353 | branch_offset = -2 - 8; | |
3354 | } | |
ae57792d HPN |
3355 | else |
3356 | { | |
3357 | nop_opcode = NOP_OPCODE; | |
3358 | opc_offset = 8; | |
3359 | branch_offset = -2 - 6; | |
3360 | } | |
3361 | ||
3362 | /* We should never get here for compatibility mode. */ | |
3363 | if (cris_arch == arch_cris_common_v10_v32) | |
3364 | as_fatal (_("Calling gen_cond_branch_32 for .arch common_v10_v32\n")); | |
3365 | ||
3bcbcc3d | 3366 | if (warn_for_branch_expansion) |
08caf3f8 HPN |
3367 | as_warn_where (fragP->fr_file, fragP->fr_line, |
3368 | _("32-bit conditional branch generated")); | |
3bcbcc3d HPN |
3369 | |
3370 | /* Here, writep points to what will be opcodep + 2. First, we change | |
3371 | the actual branch in opcodep[0] and opcodep[1], so that in the | |
3372 | final insn, it will look like: | |
3373 | opcodep+10: Bcc .-6 | |
3374 | ||
3375 | This means we don't have to worry about changing the opcode or | |
08caf3f8 | 3376 | messing with the delay-slot instruction. So, we move it to last in |
3bcbcc3d HPN |
3377 | the "extended" branch, and just change the displacement. Admittedly, |
3378 | it's not the optimal extended construct, but we should get this | |
3379 | rarely enough that it shouldn't matter. */ | |
3380 | ||
ae57792d HPN |
3381 | writep[opc_offset] = branch_disp (branch_offset); |
3382 | writep[opc_offset + 1] = opcodep[1]; | |
3bcbcc3d HPN |
3383 | |
3384 | /* Then, we change the branch to an unconditional branch over the | |
3385 | extended part, to the new location of the Bcc: | |
3386 | opcodep: BA .+10 | |
3387 | opcodep+2: NOP | |
3388 | ||
3389 | Note that these two writes are to currently different locations, | |
3390 | merged later. */ | |
3391 | ||
ae57792d | 3392 | md_number_to_chars (opcodep, BA_QUICK_OPCODE |
d2aa3f9f HPN |
3393 | + (cris_arch == arch_crisv32 ? 12 : (pic ? 10 : 8)), |
3394 | 2); | |
ae57792d | 3395 | md_number_to_chars (writep, nop_opcode, 2); |
3bcbcc3d HPN |
3396 | |
3397 | /* Then the extended thing, the 32-bit jump insn. | |
08caf3f8 HPN |
3398 | opcodep+4: JUMP [PC+] |
3399 | or, in the PIC case, | |
d2aa3f9f | 3400 | opcodep+4: MOVE [PC=PC+N],P0. */ |
3bcbcc3d | 3401 | |
08caf3f8 | 3402 | md_number_to_chars (writep + 2, |
ae57792d HPN |
3403 | cris_arch == arch_crisv32 |
3404 | ? BA_DWORD_OPCODE | |
d2aa3f9f HPN |
3405 | : (pic ? MOVE_PC_INCR_OPCODE_PREFIX |
3406 | : JUMP_PC_INCR_OPCODE), 2); | |
3bcbcc3d HPN |
3407 | |
3408 | /* We have to fill in the actual value too. | |
3409 | opcodep+6: .DWORD | |
3410 | This is most probably an expression, but we can cope with an absolute | |
08caf3f8 | 3411 | value too. FIXME: Testcase needed with and without pic. */ |
3bcbcc3d HPN |
3412 | |
3413 | if (add_symP == NULL && sub_symP == NULL) | |
08caf3f8 HPN |
3414 | { |
3415 | /* An absolute address. */ | |
ae57792d | 3416 | if (pic || cris_arch == arch_crisv32) |
08caf3f8 HPN |
3417 | fix_new (fragP, writep + 4 - fragP->fr_literal, 4, |
3418 | section_symbol (absolute_section), | |
ae57792d HPN |
3419 | add_num |
3420 | + (cris_arch == arch_crisv32 ? 6 : 0), | |
3421 | 1, BFD_RELOC_32_PCREL); | |
08caf3f8 HPN |
3422 | else |
3423 | md_number_to_chars (writep + 4, add_num, 4); | |
3424 | } | |
3bcbcc3d HPN |
3425 | else |
3426 | { | |
08caf3f8 HPN |
3427 | if (sub_symP != NULL) |
3428 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
3429 | _("Complex expression not supported")); | |
3bcbcc3d | 3430 | |
08caf3f8 | 3431 | /* Not absolute, we have to make it a frag for later evaluation. */ |
3bcbcc3d | 3432 | fix_new (fragP, writep + 4 - fragP->fr_literal, 4, add_symP, |
ae57792d HPN |
3433 | add_num + (cris_arch == arch_crisv32 ? 6 : 0), |
3434 | pic || cris_arch == arch_crisv32 ? 1 : 0, | |
3435 | pic || cris_arch == arch_crisv32 | |
3436 | ? BFD_RELOC_32_PCREL : BFD_RELOC_32); | |
3bcbcc3d | 3437 | } |
ae57792d HPN |
3438 | |
3439 | if (cris_arch == arch_crisv32) | |
3440 | /* Follow it with a "NOP" for CRISv32. */ | |
3441 | md_number_to_chars (writep + 8, NOP_OPCODE_V32, 2); | |
d2aa3f9f HPN |
3442 | else if (pic) |
3443 | /* ...and the rest of the move-opcode for pre-v32 PIC. */ | |
3444 | md_number_to_chars (writep + 8, MOVE_PC_INCR_OPCODE_SUFFIX, 2); | |
3bcbcc3d HPN |
3445 | } |
3446 | ||
cc99daad HPN |
3447 | /* Get the size of an immediate-reloc in bytes. Only valid for |
3448 | specified relocs (TLS, PIC). */ | |
08caf3f8 HPN |
3449 | |
3450 | static unsigned int | |
cc99daad | 3451 | cris_get_specified_reloc_size (bfd_reloc_code_real_type reloc) |
08caf3f8 | 3452 | { |
cc99daad HPN |
3453 | return |
3454 | reloc == BFD_RELOC_CRIS_16_GOTPLT | |
3455 | || reloc == BFD_RELOC_CRIS_16_GOT | |
3456 | || reloc == BFD_RELOC_CRIS_16_GOT_GD | |
3457 | || reloc == BFD_RELOC_CRIS_16_DTPREL | |
3458 | || reloc == BFD_RELOC_CRIS_16_GOT_TPREL | |
3459 | || reloc == BFD_RELOC_CRIS_16_TPREL | |
08caf3f8 HPN |
3460 | ? 2 : 4; |
3461 | } | |
3462 | ||
3463 | /* Store a reloc type at *RELOCP corresponding to the PIC suffix at *CPP. | |
3464 | Adjust *EXPRP with any addend found after the PIC suffix. */ | |
3465 | ||
3466 | static void | |
cc99daad HPN |
3467 | cris_get_reloc_suffix (char **cPP, bfd_reloc_code_real_type *relocp, |
3468 | expressionS *exprP) | |
08caf3f8 HPN |
3469 | { |
3470 | char *s = *cPP; | |
3471 | unsigned int i; | |
3472 | expressionS const_expr; | |
3473 | ||
3474 | const struct pic_suffixes_struct | |
3475 | { | |
3476 | const char *const suffix; | |
3477 | unsigned int len; | |
3478 | bfd_reloc_code_real_type reloc; | |
cc99daad HPN |
3479 | bfd_boolean pic_p; |
3480 | bfd_boolean tls_p; | |
08caf3f8 HPN |
3481 | } pic_suffixes[] = |
3482 | { | |
3483 | #undef PICMAP | |
cc99daad HPN |
3484 | #define PICMAP(s, r) {s, sizeof (s) - 1, r, TRUE, FALSE} |
3485 | #define PICTLSMAP(s, r) {s, sizeof (s) - 1, r, TRUE, TRUE} | |
3486 | #define TLSMAP(s, r) {s, sizeof (s) - 1, r, FALSE, TRUE} | |
08caf3f8 HPN |
3487 | /* Keep this in order with longest unambiguous prefix first. */ |
3488 | PICMAP ("GOTPLT16", BFD_RELOC_CRIS_16_GOTPLT), | |
3489 | PICMAP ("GOTPLT", BFD_RELOC_CRIS_32_GOTPLT), | |
3490 | PICMAP ("PLTG", BFD_RELOC_CRIS_32_PLT_GOTREL), | |
3491 | PICMAP ("PLT", BFD_RELOC_CRIS_32_PLT_PCREL), | |
3492 | PICMAP ("GOTOFF", BFD_RELOC_CRIS_32_GOTREL), | |
3493 | PICMAP ("GOT16", BFD_RELOC_CRIS_16_GOT), | |
cc99daad HPN |
3494 | PICMAP ("GOT", BFD_RELOC_CRIS_32_GOT), |
3495 | PICTLSMAP ("GDGOTREL16", BFD_RELOC_CRIS_16_GOT_GD), | |
3496 | PICTLSMAP ("GDGOTREL", BFD_RELOC_CRIS_32_GOT_GD), | |
3497 | TLSMAP ("GD", BFD_RELOC_CRIS_32_GD), | |
3498 | PICTLSMAP ("DTPREL16", BFD_RELOC_CRIS_16_DTPREL), | |
3499 | PICTLSMAP ("DTPREL", BFD_RELOC_CRIS_32_DTPREL), | |
5a00ea25 | 3500 | TLSMAP ("IE", BFD_RELOC_CRIS_32_IE), |
cc99daad HPN |
3501 | PICTLSMAP ("TPOFFGOT16", BFD_RELOC_CRIS_16_GOT_TPREL), |
3502 | PICTLSMAP ("TPOFFGOT", BFD_RELOC_CRIS_32_GOT_TPREL), | |
3503 | TLSMAP ("TPOFF16", BFD_RELOC_CRIS_16_TPREL), | |
3504 | TLSMAP ("TPOFF", BFD_RELOC_CRIS_32_TPREL) | |
08caf3f8 HPN |
3505 | }; |
3506 | ||
3507 | /* We've already seen the ':', so consume it. */ | |
3508 | s++; | |
3509 | ||
3510 | for (i = 0; i < sizeof (pic_suffixes)/sizeof (pic_suffixes[0]); i++) | |
3511 | { | |
3512 | if (strncmp (s, pic_suffixes[i].suffix, pic_suffixes[i].len) == 0 | |
cc99daad HPN |
3513 | && ! is_part_of_name (s[pic_suffixes[i].len]) |
3514 | /* PIC and non-PIC relocations are exclusive. */ | |
3515 | && (pic != 0) == (pic_suffixes[i].pic_p != 0) | |
3516 | /* But TLS can be active for non-TLS relocations too. */ | |
3517 | && (pic_suffixes[i].tls_p == 0 || tls)) | |
08caf3f8 HPN |
3518 | { |
3519 | /* We have a match. Consume the suffix and set the relocation | |
3520 | type. */ | |
3521 | s += pic_suffixes[i].len; | |
3522 | ||
3523 | /* There can be a constant term appended. If so, we will add it | |
3524 | to *EXPRP. */ | |
3525 | if (*s == '+' || *s == '-') | |
3526 | { | |
3527 | if (! cris_get_expression (&s, &const_expr)) | |
3528 | /* There was some kind of syntax error. Bail out. */ | |
3529 | break; | |
3530 | ||
3531 | /* Allow complex expressions as the constant part. It still | |
b6ff326e | 3532 | has to be an assembly-time constant or there will be an |
08caf3f8 | 3533 | error emitting the reloc. This makes the PIC qualifiers |
d551a338 | 3534 | idempotent; foo:GOTOFF+32 == foo+32:GOTOFF. The former we |
08caf3f8 HPN |
3535 | recognize here; the latter is parsed in the incoming |
3536 | expression. */ | |
3537 | exprP->X_add_symbol = make_expr_symbol (exprP); | |
3538 | exprP->X_op = O_add; | |
3539 | exprP->X_add_number = 0; | |
3540 | exprP->X_op_symbol = make_expr_symbol (&const_expr); | |
3541 | } | |
3542 | ||
3543 | *relocp = pic_suffixes[i].reloc; | |
3544 | *cPP = s; | |
3545 | return; | |
3546 | } | |
3547 | } | |
3548 | ||
3549 | /* No match. Don't consume anything; fall back and there will be a | |
3550 | syntax error. */ | |
3551 | } | |
3552 | ||
ae57792d | 3553 | /* This *could* have been: |
3bcbcc3d | 3554 | |
47926f60 KH |
3555 | Turn a string in input_line_pointer into a floating point constant |
3556 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
3557 | of LITTLENUMS emitted is stored in *SIZEP. | |
3bcbcc3d HPN |
3558 | |
3559 | type A character from FLTCHARS that describes what kind of | |
3560 | floating-point number is wanted. | |
3561 | ||
3562 | litp A pointer to an array that the result should be stored in. | |
3563 | ||
3564 | sizep A pointer to an integer where the size of the result is stored. | |
3565 | ||
3566 | But we don't support floating point constants in assembly code *at all*, | |
3567 | since it's suboptimal and just opens up bug opportunities. GCC emits | |
3568 | the bit patterns as hex. All we could do here is to emit what GCC | |
3569 | would have done in the first place. *Nobody* writes floating-point | |
3570 | code as assembly code, but if they do, they should be able enough to | |
3571 | find out the correct bit patterns and use them. */ | |
3572 | ||
3573 | char * | |
695a4822 HPN |
3574 | md_atof (int type ATTRIBUTE_UNUSED, char *litp ATTRIBUTE_UNUSED, |
3575 | int *sizep ATTRIBUTE_UNUSED) | |
3bcbcc3d HPN |
3576 | { |
3577 | /* FIXME: Is this function mentioned in the internals.texi manual? If | |
3578 | not, add it. */ | |
3579 | return _("Bad call to md_atof () - floating point formats are not supported"); | |
3580 | } | |
3581 | ||
3bcbcc3d HPN |
3582 | /* Turn a number as a fixS * into a series of bytes that represents the |
3583 | number on the target machine. The purpose of this procedure is the | |
3584 | same as that of md_number_to_chars but this procedure is supposed to | |
3585 | handle general bit field fixes and machine-dependent fixups. | |
3586 | ||
3587 | bufp Pointer to an array where the result should be stored. | |
3588 | ||
3589 | val The value to store. | |
3590 | ||
3591 | n The number of bytes in "val" that should be stored. | |
3592 | ||
08caf3f8 HPN |
3593 | fixP The fix to be applied to the bit field starting at bufp. |
3594 | ||
3595 | seg The segment containing this number. */ | |
3bcbcc3d HPN |
3596 | |
3597 | static void | |
695a4822 | 3598 | cris_number_to_imm (char *bufp, long val, int n, fixS *fixP, segT seg) |
3bcbcc3d HPN |
3599 | { |
3600 | segT sym_seg; | |
3601 | ||
3602 | know (n <= 4); | |
3603 | know (fixP); | |
3604 | ||
3605 | /* We put the relative "vma" for the other segment for inter-segment | |
3606 | relocations in the object data to stay binary "compatible" (with an | |
3607 | uninteresting old version) for the relocation. | |
3608 | Maybe delete some day. */ | |
3609 | if (fixP->fx_addsy | |
08caf3f8 | 3610 | && (sym_seg = S_GET_SEGMENT (fixP->fx_addsy)) != seg) |
3bcbcc3d HPN |
3611 | val += sym_seg->vma; |
3612 | ||
08caf3f8 HPN |
3613 | if (fixP->fx_addsy != NULL || fixP->fx_pcrel) |
3614 | switch (fixP->fx_r_type) | |
3615 | { | |
3616 | /* These must be fully resolved when getting here. */ | |
08caf3f8 HPN |
3617 | case BFD_RELOC_16_PCREL: |
3618 | case BFD_RELOC_8_PCREL: | |
ae57792d | 3619 | as_bad_where (fixP->fx_file, fixP->fx_line, |
08caf3f8 HPN |
3620 | _("PC-relative relocation must be trivially resolved")); |
3621 | default: | |
3622 | ; | |
3623 | } | |
3624 | ||
bfa1b75c HPN |
3625 | /* Only use the computed value for old-arch binaries. For all |
3626 | others, where we're going to output a relocation, put 0 in the | |
3627 | code. */ | |
ae57792d HPN |
3628 | if (cris_arch != arch_cris_any_v0_v10 |
3629 | && (fixP->fx_addsy != NULL || fixP->fx_pcrel)) | |
bfa1b75c | 3630 | val = 0; |
ae57792d | 3631 | |
3bcbcc3d HPN |
3632 | switch (fixP->fx_r_type) |
3633 | { | |
3634 | /* Ditto here, we put the addend into the object code as | |
3635 | well as the reloc addend. Keep it that way for now, to simplify | |
3636 | regression tests on the object file contents. FIXME: Seems | |
3637 | uninteresting now that we have a test suite. */ | |
3638 | ||
cc99daad HPN |
3639 | case BFD_RELOC_CRIS_32_GOT_GD: |
3640 | case BFD_RELOC_CRIS_16_GOT_GD: | |
3641 | case BFD_RELOC_CRIS_32_GD: | |
5a00ea25 | 3642 | case BFD_RELOC_CRIS_32_IE: |
cc99daad HPN |
3643 | case BFD_RELOC_CRIS_32_DTPREL: |
3644 | case BFD_RELOC_CRIS_16_DTPREL: | |
3645 | case BFD_RELOC_CRIS_32_GOT_TPREL: | |
3646 | case BFD_RELOC_CRIS_16_GOT_TPREL: | |
3647 | case BFD_RELOC_CRIS_32_TPREL: | |
3648 | case BFD_RELOC_CRIS_16_TPREL: | |
f3294356 HPN |
3649 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3650 | if (IS_ELF && fixP->fx_addsy != NULL) | |
3651 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
3652 | #endif | |
3653 | /* Fall through. */ | |
3654 | ||
3655 | case BFD_RELOC_CRIS_16_GOT: | |
3656 | case BFD_RELOC_CRIS_32_GOT: | |
3657 | case BFD_RELOC_CRIS_32_GOTREL: | |
3658 | case BFD_RELOC_CRIS_16_GOTPLT: | |
3659 | case BFD_RELOC_CRIS_32_GOTPLT: | |
3660 | case BFD_RELOC_CRIS_32_PLT_GOTREL: | |
3661 | case BFD_RELOC_CRIS_32_PLT_PCREL: | |
08caf3f8 HPN |
3662 | /* We don't want to put in any kind of non-zero bits in the data |
3663 | being relocated for these. */ | |
bfa1b75c | 3664 | md_number_to_chars (bufp, 0, n); |
08caf3f8 HPN |
3665 | break; |
3666 | ||
08caf3f8 | 3667 | case BFD_RELOC_32_PCREL: |
bfa1b75c | 3668 | /* If this one isn't fully resolved, we don't want to put non-zero |
ae57792d HPN |
3669 | in the object. */ |
3670 | if (fixP->fx_addsy != NULL || fixP->fx_pcrel) | |
bfa1b75c | 3671 | val = 0; |
ae57792d HPN |
3672 | |
3673 | /* Fall through. */ | |
3674 | case BFD_RELOC_32: | |
3bcbcc3d HPN |
3675 | /* No use having warnings here, since most hosts have a 32-bit type |
3676 | for "long" (which will probably change soon, now that I wrote | |
3677 | this). */ | |
3678 | bufp[3] = (val >> 24) & 0xFF; | |
3679 | bufp[2] = (val >> 16) & 0xFF; | |
3680 | bufp[1] = (val >> 8) & 0xFF; | |
3681 | bufp[0] = val & 0xFF; | |
3682 | break; | |
3683 | ||
3684 | /* FIXME: The 16 and 8-bit cases should have a way to check | |
3685 | whether a signed or unsigned (or any signedness) number is | |
ae57792d | 3686 | accepted. */ |
3bcbcc3d HPN |
3687 | |
3688 | case BFD_RELOC_16: | |
08caf3f8 | 3689 | case BFD_RELOC_16_PCREL: |
3bcbcc3d | 3690 | if (val > 0xffff || val < -32768) |
ae57792d HPN |
3691 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3692 | _("Value not in 16 bit range: %ld"), val); | |
bfa1b75c HPN |
3693 | bufp[1] = (val >> 8) & 0xFF; |
3694 | bufp[0] = val & 0xFF; | |
ae57792d HPN |
3695 | break; |
3696 | ||
3697 | case BFD_RELOC_CRIS_SIGNED_16: | |
3698 | if (val > 32767 || val < -32768) | |
3699 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3700 | _("Value not in 16 bit signed range: %ld"), val); | |
bfa1b75c HPN |
3701 | bufp[1] = (val >> 8) & 0xFF; |
3702 | bufp[0] = val & 0xFF; | |
3bcbcc3d HPN |
3703 | break; |
3704 | ||
3705 | case BFD_RELOC_8: | |
08caf3f8 | 3706 | case BFD_RELOC_8_PCREL: |
3bcbcc3d | 3707 | if (val > 255 || val < -128) |
ae57792d | 3708 | as_bad_where (fixP->fx_file, fixP->fx_line, _("Value not in 8 bit range: %ld"), val); |
bfa1b75c | 3709 | bufp[0] = val & 0xFF; |
ae57792d HPN |
3710 | break; |
3711 | ||
3712 | case BFD_RELOC_CRIS_SIGNED_8: | |
3713 | if (val > 127 || val < -128) | |
3714 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3715 | _("Value not in 8 bit signed range: %ld"), val); | |
bfa1b75c | 3716 | bufp[0] = val & 0xFF; |
3bcbcc3d HPN |
3717 | break; |
3718 | ||
ae57792d HPN |
3719 | case BFD_RELOC_CRIS_LAPCQ_OFFSET: |
3720 | /* FIXME: Test-cases for out-of-range values. Probably also need | |
3721 | to use as_bad_where. */ | |
3bcbcc3d HPN |
3722 | case BFD_RELOC_CRIS_UNSIGNED_4: |
3723 | if (val > 15 || val < 0) | |
ae57792d HPN |
3724 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3725 | _("Value not in 4 bit unsigned range: %ld"), val); | |
bfa1b75c | 3726 | bufp[0] |= val & 0x0F; |
3bcbcc3d HPN |
3727 | break; |
3728 | ||
3729 | case BFD_RELOC_CRIS_UNSIGNED_5: | |
3730 | if (val > 31 || val < 0) | |
ae57792d HPN |
3731 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3732 | _("Value not in 5 bit unsigned range: %ld"), val); | |
bfa1b75c | 3733 | bufp[0] |= val & 0x1F; |
3bcbcc3d HPN |
3734 | break; |
3735 | ||
3736 | case BFD_RELOC_CRIS_SIGNED_6: | |
3737 | if (val > 31 || val < -32) | |
ae57792d HPN |
3738 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3739 | _("Value not in 6 bit range: %ld"), val); | |
bfa1b75c | 3740 | bufp[0] |= val & 0x3F; |
3bcbcc3d HPN |
3741 | break; |
3742 | ||
3743 | case BFD_RELOC_CRIS_UNSIGNED_6: | |
3744 | if (val > 63 || val < 0) | |
ae57792d HPN |
3745 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3746 | _("Value not in 6 bit unsigned range: %ld"), val); | |
bfa1b75c | 3747 | bufp[0] |= val & 0x3F; |
3bcbcc3d HPN |
3748 | break; |
3749 | ||
3750 | case BFD_RELOC_CRIS_BDISP8: | |
bfa1b75c | 3751 | bufp[0] = branch_disp (val); |
3bcbcc3d HPN |
3752 | break; |
3753 | ||
3754 | case BFD_RELOC_NONE: | |
3755 | /* May actually happen automatically. For example at broken | |
3756 | words, if the word turns out not to be broken. | |
47926f60 | 3757 | FIXME: When? Which testcase? */ |
3bcbcc3d HPN |
3758 | if (! fixP->fx_addsy) |
3759 | md_number_to_chars (bufp, val, n); | |
3760 | break; | |
3761 | ||
3762 | case BFD_RELOC_VTABLE_INHERIT: | |
3763 | /* This borrowed from tc-ppc.c on a whim. */ | |
3764 | if (fixP->fx_addsy | |
3765 | && !S_IS_DEFINED (fixP->fx_addsy) | |
3766 | && !S_IS_WEAK (fixP->fx_addsy)) | |
3767 | S_SET_WEAK (fixP->fx_addsy); | |
7b15d668 HPN |
3768 | /* Fall through. */ |
3769 | ||
3bcbcc3d | 3770 | case BFD_RELOC_VTABLE_ENTRY: |
3bcbcc3d HPN |
3771 | fixP->fx_done = 0; |
3772 | break; | |
3773 | ||
3774 | default: | |
3775 | BAD_CASE (fixP->fx_r_type); | |
3776 | } | |
3777 | } | |
3778 | ||
3bcbcc3d HPN |
3779 | /* Processes machine-dependent command line options. Called once for |
3780 | each option on the command line that the machine-independent part of | |
3781 | GAS does not understand. */ | |
47926f60 | 3782 | |
3bcbcc3d | 3783 | int |
695a4822 | 3784 | md_parse_option (int arg, char *argp ATTRIBUTE_UNUSED) |
3bcbcc3d HPN |
3785 | { |
3786 | switch (arg) | |
3787 | { | |
3788 | case 'H': | |
3789 | case 'h': | |
7b15d668 | 3790 | printf (_("Please use --help to see usage and options for this assembler.\n")); |
3bcbcc3d | 3791 | md_show_usage (stdout); |
7b15d668 | 3792 | exit (EXIT_SUCCESS); |
3bcbcc3d HPN |
3793 | |
3794 | case 'N': | |
3795 | warn_for_branch_expansion = 1; | |
ae57792d | 3796 | break; |
3bcbcc3d | 3797 | |
7b15d668 | 3798 | case OPTION_NO_US: |
b34976b6 | 3799 | demand_register_prefix = TRUE; |
7b15d668 HPN |
3800 | |
3801 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
08caf3f8 | 3802 | as_bad (_("--no-underscore is invalid with a.out format")); |
7b15d668 | 3803 | else |
b34976b6 | 3804 | symbols_have_leading_underscore = FALSE; |
ae57792d | 3805 | break; |
7b15d668 HPN |
3806 | |
3807 | case OPTION_US: | |
b34976b6 AM |
3808 | demand_register_prefix = FALSE; |
3809 | symbols_have_leading_underscore = TRUE; | |
ae57792d | 3810 | break; |
7b15d668 | 3811 | |
08caf3f8 | 3812 | case OPTION_PIC: |
0d7e0060 HPN |
3813 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
3814 | as_bad (_("--pic is invalid for this object format")); | |
b34976b6 | 3815 | pic = TRUE; |
d2aa3f9f HPN |
3816 | if (cris_arch != arch_crisv32) |
3817 | md_long_jump_size = cris_any_v0_v10_long_jump_size_pic; | |
3818 | else | |
3819 | md_long_jump_size = crisv32_long_jump_size; | |
ae57792d HPN |
3820 | break; |
3821 | ||
3822 | case OPTION_ARCH: | |
3823 | { | |
3824 | char *str = argp; | |
3825 | enum cris_archs argarch = cris_arch_from_string (&str); | |
3826 | ||
3827 | if (argarch == arch_cris_unknown) | |
3828 | as_bad (_("invalid <arch> in --march=<arch>: %s"), argp); | |
3829 | else | |
3830 | cris_arch = argarch; | |
3831 | ||
3832 | if (argarch == arch_crisv32) | |
3833 | { | |
3834 | err_for_dangerous_mul_placement = 0; | |
3835 | md_long_jump_size = crisv32_long_jump_size; | |
3836 | } | |
3837 | else | |
d2aa3f9f HPN |
3838 | { |
3839 | if (pic) | |
3840 | md_long_jump_size = cris_any_v0_v10_long_jump_size_pic; | |
3841 | else | |
3842 | md_long_jump_size = cris_any_v0_v10_long_jump_size; | |
3843 | } | |
ae57792d HPN |
3844 | } |
3845 | break; | |
08caf3f8 | 3846 | |
1048a9ba HPN |
3847 | case OPTION_MULBUG_ABORT_OFF: |
3848 | err_for_dangerous_mul_placement = 0; | |
ae57792d | 3849 | break; |
1048a9ba HPN |
3850 | |
3851 | case OPTION_MULBUG_ABORT_ON: | |
3852 | err_for_dangerous_mul_placement = 1; | |
ae57792d | 3853 | break; |
1048a9ba | 3854 | |
3bcbcc3d HPN |
3855 | default: |
3856 | return 0; | |
47926f60 | 3857 | } |
ae57792d HPN |
3858 | |
3859 | return 1; | |
3bcbcc3d HPN |
3860 | } |
3861 | ||
3862 | /* Round up a section size to the appropriate boundary. */ | |
3863 | valueT | |
695a4822 | 3864 | md_section_align (segT segment, valueT size) |
3bcbcc3d HPN |
3865 | { |
3866 | /* Round all sects to multiple of 4, except the bss section, which | |
3867 | we'll round to word-size. | |
3868 | ||
3869 | FIXME: Check if this really matters. All sections should be | |
3870 | rounded up, and all sections should (optionally) be assumed to be | |
3871 | dword-aligned, it's just that there is actual usage of linking to a | |
3872 | multiple of two. */ | |
3873 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
3874 | { | |
3875 | if (segment == bss_section) | |
3876 | return (size + 1) & ~1; | |
3877 | return (size + 3) & ~3; | |
3878 | } | |
3879 | else | |
3880 | { | |
3881 | /* FIXME: Is this wanted? It matches the testsuite, but that's not | |
3882 | really a valid reason. */ | |
3883 | if (segment == text_section) | |
3884 | return (size + 3) & ~3; | |
3885 | } | |
3886 | ||
3887 | return size; | |
3888 | } | |
3889 | ||
3bcbcc3d HPN |
3890 | /* Generate a machine-dependent relocation. */ |
3891 | arelent * | |
695a4822 | 3892 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP) |
3bcbcc3d HPN |
3893 | { |
3894 | arelent *relP; | |
3895 | bfd_reloc_code_real_type code; | |
3896 | ||
3897 | switch (fixP->fx_r_type) | |
3898 | { | |
ae57792d HPN |
3899 | case BFD_RELOC_CRIS_SIGNED_8: |
3900 | code = BFD_RELOC_8; | |
3901 | break; | |
3902 | ||
3903 | case BFD_RELOC_CRIS_SIGNED_16: | |
3904 | code = BFD_RELOC_16; | |
3905 | break; | |
3906 | ||
08caf3f8 HPN |
3907 | case BFD_RELOC_CRIS_16_GOT: |
3908 | case BFD_RELOC_CRIS_32_GOT: | |
3909 | case BFD_RELOC_CRIS_16_GOTPLT: | |
3910 | case BFD_RELOC_CRIS_32_GOTPLT: | |
3911 | case BFD_RELOC_CRIS_32_GOTREL: | |
3912 | case BFD_RELOC_CRIS_32_PLT_GOTREL: | |
3913 | case BFD_RELOC_CRIS_32_PLT_PCREL: | |
3bcbcc3d | 3914 | case BFD_RELOC_32: |
ae57792d | 3915 | case BFD_RELOC_32_PCREL: |
3bcbcc3d HPN |
3916 | case BFD_RELOC_16: |
3917 | case BFD_RELOC_8: | |
3918 | case BFD_RELOC_VTABLE_INHERIT: | |
3919 | case BFD_RELOC_VTABLE_ENTRY: | |
ae57792d HPN |
3920 | case BFD_RELOC_CRIS_UNSIGNED_8: |
3921 | case BFD_RELOC_CRIS_UNSIGNED_16: | |
3922 | case BFD_RELOC_CRIS_LAPCQ_OFFSET: | |
cc99daad HPN |
3923 | case BFD_RELOC_CRIS_32_GOT_GD: |
3924 | case BFD_RELOC_CRIS_16_GOT_GD: | |
3925 | case BFD_RELOC_CRIS_32_GD: | |
5a00ea25 | 3926 | case BFD_RELOC_CRIS_32_IE: |
cc99daad HPN |
3927 | case BFD_RELOC_CRIS_32_DTPREL: |
3928 | case BFD_RELOC_CRIS_16_DTPREL: | |
3929 | case BFD_RELOC_CRIS_32_GOT_TPREL: | |
3930 | case BFD_RELOC_CRIS_16_GOT_TPREL: | |
3931 | case BFD_RELOC_CRIS_32_TPREL: | |
3932 | case BFD_RELOC_CRIS_16_TPREL: | |
3bcbcc3d HPN |
3933 | code = fixP->fx_r_type; |
3934 | break; | |
3935 | default: | |
3936 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3937 | _("Semantics error. This type of operand can not be relocated, it must be an assembly-time constant")); | |
3938 | return 0; | |
3939 | } | |
3940 | ||
3941 | relP = (arelent *) xmalloc (sizeof (arelent)); | |
9c2799c2 | 3942 | gas_assert (relP != 0); |
3bcbcc3d HPN |
3943 | relP->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
3944 | *relP->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); | |
3945 | relP->address = fixP->fx_frag->fr_address + fixP->fx_where; | |
3946 | ||
ae57792d | 3947 | relP->addend = fixP->fx_offset; |
3bcbcc3d HPN |
3948 | |
3949 | /* This is the standard place for KLUDGEs to work around bugs in | |
3950 | bfd_install_relocation (first such note in the documentation | |
3951 | appears with binutils-2.8). | |
3952 | ||
3953 | That function bfd_install_relocation does the wrong thing with | |
3954 | putting stuff into the addend of a reloc (it should stay out) for a | |
3955 | weak symbol. The really bad thing is that it adds the | |
3956 | "segment-relative offset" of the symbol into the reloc. In this | |
3957 | case, the reloc should instead be relative to the symbol with no | |
3958 | other offset than the assembly code shows; and since the symbol is | |
3959 | weak, any local definition should be ignored until link time (or | |
3960 | thereafter). | |
3961 | To wit: weaksym+42 should be weaksym+42 in the reloc, | |
3962 | not weaksym+(offset_from_segment_of_local_weaksym_definition) | |
3963 | ||
3964 | To "work around" this, we subtract the segment-relative offset of | |
3965 | "known" weak symbols. This evens out the extra offset. | |
3966 | ||
3967 | That happens for a.out but not for ELF, since for ELF, | |
3968 | bfd_install_relocation uses the "special function" field of the | |
3969 | howto, and does not execute the code that needs to be undone. */ | |
3970 | ||
3971 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour | |
3972 | && fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy) | |
3973 | && ! bfd_is_und_section (S_GET_SEGMENT (fixP->fx_addsy))) | |
47926f60 KH |
3974 | { |
3975 | relP->addend -= S_GET_VALUE (fixP->fx_addsy); | |
3976 | } | |
3bcbcc3d HPN |
3977 | |
3978 | relP->howto = bfd_reloc_type_lookup (stdoutput, code); | |
3979 | if (! relP->howto) | |
3980 | { | |
3981 | const char *name; | |
3982 | ||
3983 | name = S_GET_NAME (fixP->fx_addsy); | |
3984 | if (name == NULL) | |
3985 | name = _("<unknown>"); | |
3986 | as_fatal (_("Cannot generate relocation type for symbol %s, code %s"), | |
3987 | name, bfd_get_reloc_code_name (code)); | |
3988 | } | |
3989 | ||
3990 | return relP; | |
3991 | } | |
3992 | ||
3bcbcc3d | 3993 | /* Machine-dependent usage-output. */ |
47926f60 | 3994 | |
3bcbcc3d | 3995 | void |
695a4822 | 3996 | md_show_usage (FILE *stream) |
3bcbcc3d | 3997 | { |
08caf3f8 | 3998 | /* The messages are formatted to line up with the generic options. */ |
7b15d668 HPN |
3999 | fprintf (stream, _("CRIS-specific options:\n")); |
4000 | fprintf (stream, "%s", | |
4001 | _(" -h, -H Don't execute, print this help text. Deprecated.\n")); | |
4002 | fprintf (stream, "%s", | |
4003 | _(" -N Warn when branches are expanded to jumps.\n")); | |
4004 | fprintf (stream, "%s", | |
4005 | _(" --underscore User symbols are normally prepended with underscore.\n")); | |
4006 | fprintf (stream, "%s", | |
4007 | _(" Registers will not need any prefix.\n")); | |
4008 | fprintf (stream, "%s", | |
4009 | _(" --no-underscore User symbols do not have any prefix.\n")); | |
4010 | fprintf (stream, "%s", | |
4011 | _(" Registers will require a `$'-prefix.\n")); | |
0d7e0060 | 4012 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
08caf3f8 HPN |
4013 | fprintf (stream, "%s", |
4014 | _(" --pic Enable generation of position-independent code.\n")); | |
0d7e0060 | 4015 | #endif |
ae57792d HPN |
4016 | fprintf (stream, "%s", |
4017 | _(" --march=<arch> Generate code for <arch>. Valid choices for <arch>\n\ | |
4018 | are v0_v10, v10, v32 and common_v10_v32.\n")); | |
3bcbcc3d HPN |
4019 | } |
4020 | ||
3bcbcc3d | 4021 | /* Apply a fixS (fixup of an instruction or data that we didn't have |
47926f60 | 4022 | enough info to complete immediately) to the data in a frag. */ |
3bcbcc3d | 4023 | |
94f592af | 4024 | void |
55cf6793 | 4025 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
3bcbcc3d | 4026 | { |
451a1fc5 HPN |
4027 | /* This assignment truncates upper bits if valueT is 64 bits (as with |
4028 | --enable-64-bit-bfd), which is fine here, though we cast to avoid | |
920e4177 | 4029 | any compiler warnings. */ |
451a1fc5 | 4030 | long val = (long) *valP; |
3bcbcc3d HPN |
4031 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; |
4032 | ||
4033 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
4034 | fixP->fx_done = 1; | |
4035 | ||
4036 | if (fixP->fx_bit_fixP || fixP->fx_im_disp != 0) | |
4037 | { | |
4038 | as_bad_where (fixP->fx_file, fixP->fx_line, _("Invalid relocation")); | |
4039 | fixP->fx_done = 1; | |
4040 | } | |
4041 | else | |
47926f60 | 4042 | { |
a161fe53 | 4043 | /* We can't actually support subtracting a symbol. */ |
47926f60 | 4044 | if (fixP->fx_subsy != (symbolS *) NULL) |
a161fe53 AM |
4045 | as_bad_where (fixP->fx_file, fixP->fx_line, |
4046 | _("expression too complex")); | |
47926f60 | 4047 | |
ae57792d HPN |
4048 | /* This operand-type is scaled. */ |
4049 | if (fixP->fx_r_type == BFD_RELOC_CRIS_LAPCQ_OFFSET) | |
4050 | val /= 2; | |
08caf3f8 | 4051 | cris_number_to_imm (buf, val, fixP->fx_size, fixP, seg); |
47926f60 | 4052 | } |
3bcbcc3d HPN |
4053 | } |
4054 | ||
3bcbcc3d HPN |
4055 | /* All relocations are relative to the location just after the fixup; |
4056 | the address of the fixup plus its size. */ | |
4057 | ||
4058 | long | |
695a4822 | 4059 | md_pcrel_from (fixS *fixP) |
3bcbcc3d HPN |
4060 | { |
4061 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
4062 | ||
4063 | /* FIXME: We get here only at the end of assembly, when X in ".-X" is | |
08caf3f8 HPN |
4064 | still unknown. Since we don't have pc-relative relocations in a.out, |
4065 | this is invalid. What to do if anything for a.out, is to add | |
3bcbcc3d | 4066 | pc-relative relocations everywhere including the elinux program |
08caf3f8 HPN |
4067 | loader. For ELF, allow straight-forward PC-relative relocations, |
4068 | which are always relative to the location after the relocation. */ | |
4069 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
4070 | || (fixP->fx_r_type != BFD_RELOC_8_PCREL | |
4071 | && fixP->fx_r_type != BFD_RELOC_16_PCREL | |
ae57792d HPN |
4072 | && fixP->fx_r_type != BFD_RELOC_32_PCREL |
4073 | && fixP->fx_r_type != BFD_RELOC_CRIS_LAPCQ_OFFSET)) | |
08caf3f8 HPN |
4074 | as_bad_where (fixP->fx_file, fixP->fx_line, |
4075 | _("Invalid pc-relative relocation")); | |
3bcbcc3d HPN |
4076 | return fixP->fx_size + addr; |
4077 | } | |
4078 | ||
47926f60 | 4079 | /* We have no need to give defaults for symbol-values. */ |
3bcbcc3d | 4080 | symbolS * |
695a4822 | 4081 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
3bcbcc3d HPN |
4082 | { |
4083 | return 0; | |
4084 | } | |
4085 | ||
a161fe53 AM |
4086 | /* If this function returns non-zero, it prevents the relocation |
4087 | against symbol(s) in the FIXP from being replaced with relocations | |
4088 | against section symbols, and guarantees that a relocation will be | |
4089 | emitted even when the value can be resolved locally. */ | |
3bcbcc3d | 4090 | int |
695a4822 | 4091 | md_cris_force_relocation (struct fix *fixp) |
3bcbcc3d | 4092 | { |
08caf3f8 HPN |
4093 | switch (fixp->fx_r_type) |
4094 | { | |
08caf3f8 HPN |
4095 | case BFD_RELOC_CRIS_16_GOT: |
4096 | case BFD_RELOC_CRIS_32_GOT: | |
4097 | case BFD_RELOC_CRIS_16_GOTPLT: | |
4098 | case BFD_RELOC_CRIS_32_GOTPLT: | |
4099 | case BFD_RELOC_CRIS_32_GOTREL: | |
4100 | case BFD_RELOC_CRIS_32_PLT_GOTREL: | |
4101 | case BFD_RELOC_CRIS_32_PLT_PCREL: | |
4102 | return 1; | |
4103 | default: | |
4104 | ; | |
4105 | } | |
4106 | ||
ae6063d4 | 4107 | return generic_force_reloc (fixp); |
3bcbcc3d HPN |
4108 | } |
4109 | ||
4110 | /* Check and emit error if broken-word handling has failed to fix up a | |
4111 | case-table. This is called from write.c, after doing everything it | |
4112 | knows about how to handle broken words. */ | |
4113 | ||
4114 | void | |
695a4822 | 4115 | tc_cris_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP) |
3bcbcc3d HPN |
4116 | { |
4117 | if (new_offset > 32767 || new_offset < -32768) | |
47926f60 | 4118 | /* We really want a genuine error, not a warning, so make it one. */ |
3bcbcc3d HPN |
4119 | as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line, |
4120 | _("Adjusted signed .word (%ld) overflows: `switch'-statement too large."), | |
4121 | (long) new_offset); | |
4122 | } | |
4123 | ||
7b15d668 HPN |
4124 | /* Make a leading REGISTER_PREFIX_CHAR mandatory for all registers. */ |
4125 | ||
695a4822 HPN |
4126 | static void |
4127 | cris_force_reg_prefix (void) | |
7b15d668 | 4128 | { |
b34976b6 | 4129 | demand_register_prefix = TRUE; |
7b15d668 HPN |
4130 | } |
4131 | ||
4132 | /* Do not demand a leading REGISTER_PREFIX_CHAR for all registers. */ | |
4133 | ||
695a4822 HPN |
4134 | static void |
4135 | cris_relax_reg_prefix (void) | |
7b15d668 | 4136 | { |
b34976b6 | 4137 | demand_register_prefix = FALSE; |
7b15d668 HPN |
4138 | } |
4139 | ||
4140 | /* Adjust for having a leading '_' on all user symbols. */ | |
4141 | ||
695a4822 HPN |
4142 | static void |
4143 | cris_sym_leading_underscore (void) | |
7b15d668 HPN |
4144 | { |
4145 | /* We can't really do anything more than assert that what the program | |
4146 | thinks symbol starts with agrees with the command-line options, since | |
4147 | the bfd is already created. */ | |
4148 | ||
b34976b6 | 4149 | if (!symbols_have_leading_underscore) |
ed67db7a | 4150 | as_bad (_(".syntax %s requires command-line option `--underscore'"), |
7b15d668 HPN |
4151 | SYNTAX_USER_SYM_LEADING_UNDERSCORE); |
4152 | } | |
4153 | ||
4154 | /* Adjust for not having any particular prefix on user symbols. */ | |
4155 | ||
695a4822 | 4156 | static void cris_sym_no_leading_underscore (void) |
7b15d668 | 4157 | { |
b34976b6 | 4158 | if (symbols_have_leading_underscore) |
ed67db7a | 4159 | as_bad (_(".syntax %s requires command-line option `--no-underscore'"), |
7b15d668 HPN |
4160 | SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE); |
4161 | } | |
4162 | ||
4163 | /* Handle the .syntax pseudo, which takes an argument that decides what | |
4164 | syntax the assembly code has. */ | |
4165 | ||
4166 | static void | |
695a4822 | 4167 | s_syntax (int ignore ATTRIBUTE_UNUSED) |
7b15d668 HPN |
4168 | { |
4169 | static const struct syntaxes | |
4170 | { | |
ae57792d | 4171 | const char *const operand; |
695a4822 | 4172 | void (*fn) (void); |
4a1805b1 | 4173 | } syntax_table[] = |
7b15d668 HPN |
4174 | {{SYNTAX_ENFORCE_REG_PREFIX, cris_force_reg_prefix}, |
4175 | {SYNTAX_RELAX_REG_PREFIX, cris_relax_reg_prefix}, | |
4176 | {SYNTAX_USER_SYM_LEADING_UNDERSCORE, cris_sym_leading_underscore}, | |
4177 | {SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE, cris_sym_no_leading_underscore}}; | |
4178 | ||
4179 | const struct syntaxes *sp; | |
4180 | ||
4181 | for (sp = syntax_table; | |
4182 | sp < syntax_table + sizeof (syntax_table) / sizeof (syntax_table[0]); | |
4183 | sp++) | |
4184 | { | |
4185 | if (strncmp (input_line_pointer, sp->operand, | |
4186 | strlen (sp->operand)) == 0) | |
4187 | { | |
bc805888 | 4188 | (sp->fn) (); |
7b15d668 HPN |
4189 | |
4190 | input_line_pointer += strlen (sp->operand); | |
4191 | demand_empty_rest_of_line (); | |
4192 | return; | |
4193 | } | |
4194 | } | |
4195 | ||
4196 | as_bad (_("Unknown .syntax operand")); | |
4197 | } | |
4198 | ||
fcdc20a4 HPN |
4199 | /* Wrapper for dwarf2_directive_file to emit error if this is seen when |
4200 | not emitting ELF. */ | |
4201 | ||
4202 | static void | |
695a4822 | 4203 | s_cris_file (int dummy) |
fcdc20a4 HPN |
4204 | { |
4205 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
ed67db7a | 4206 | as_bad (_("Pseudodirective .file is only valid when generating ELF")); |
fcdc20a4 HPN |
4207 | else |
4208 | dwarf2_directive_file (dummy); | |
4209 | } | |
4210 | ||
4211 | /* Wrapper for dwarf2_directive_loc to emit error if this is seen when not | |
4212 | emitting ELF. */ | |
4213 | ||
4214 | static void | |
695a4822 | 4215 | s_cris_loc (int dummy) |
fcdc20a4 HPN |
4216 | { |
4217 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
ed67db7a | 4218 | as_bad (_("Pseudodirective .loc is only valid when generating ELF")); |
fcdc20a4 HPN |
4219 | else |
4220 | dwarf2_directive_loc (dummy); | |
4221 | } | |
4222 | ||
d2b52762 HPN |
4223 | /* Worker for .dtpoffd: generate a R_CRIS_32_DTPREL reloc, as for |
4224 | expr:DTPREL but for use in debug info. */ | |
4225 | ||
4226 | static void | |
4227 | s_cris_dtpoff (int bytes) | |
4228 | { | |
4229 | expressionS ex; | |
4230 | char *p; | |
4231 | ||
4232 | if (bytes != 4) | |
4233 | as_fatal (_("internal inconsistency problem: %s called for %d bytes"), | |
4234 | __FUNCTION__, bytes); | |
4235 | ||
4236 | expression (&ex); | |
4237 | ||
4238 | p = frag_more (bytes); | |
4239 | md_number_to_chars (p, 0, bytes); | |
4240 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
4241 | BFD_RELOC_CRIS_32_DTPREL); | |
4242 | ||
4243 | demand_empty_rest_of_line (); | |
4244 | } | |
4245 | ||
4246 | ||
ae57792d HPN |
4247 | /* Translate a <arch> string (as common to --march=<arch> and .arch <arch>) |
4248 | into an enum. If the string *STR is recognized, *STR is updated to point | |
4249 | to the end of the string. If the string is not recognized, | |
4250 | arch_cris_unknown is returned. */ | |
4251 | ||
4252 | static enum cris_archs | |
695a4822 | 4253 | cris_arch_from_string (char **str) |
ae57792d HPN |
4254 | { |
4255 | static const struct cris_arch_struct | |
4256 | { | |
4257 | const char *const name; | |
4258 | enum cris_archs arch; | |
4259 | } arch_table[] = | |
4260 | /* Keep in order longest-first for choices where one is a prefix | |
4261 | of another. */ | |
4262 | {{"v0_v10", arch_cris_any_v0_v10}, | |
4263 | {"v10", arch_crisv10}, | |
4264 | {"v32", arch_crisv32}, | |
4265 | {"common_v10_v32", arch_cris_common_v10_v32}}; | |
4266 | ||
4267 | const struct cris_arch_struct *ap; | |
4268 | ||
4269 | for (ap = arch_table; | |
4270 | ap < arch_table + sizeof (arch_table) / sizeof (arch_table[0]); | |
4271 | ap++) | |
4272 | { | |
4273 | int len = strlen (ap->name); | |
4274 | ||
4275 | if (strncmp (*str, ap->name, len) == 0 | |
4276 | && (str[0][len] == 0 || ISSPACE (str[0][len]))) | |
4277 | { | |
4278 | *str += strlen (ap->name); | |
4279 | return ap->arch; | |
4280 | } | |
4281 | } | |
4282 | ||
4283 | return arch_cris_unknown; | |
4284 | } | |
4285 | ||
4286 | /* Return nonzero if architecture version ARCH matches version range in | |
4287 | IVER. */ | |
4288 | ||
4289 | static int | |
695a4822 HPN |
4290 | cris_insn_ver_valid_for_arch (enum cris_insn_version_usage iver, |
4291 | enum cris_archs arch) | |
ae57792d HPN |
4292 | { |
4293 | switch (arch) | |
4294 | { | |
4295 | case arch_cris_any_v0_v10: | |
4296 | return | |
4297 | (iver == cris_ver_version_all | |
4298 | || iver == cris_ver_warning | |
4299 | || iver == cris_ver_v0_3 | |
4300 | || iver == cris_ver_v3p | |
4301 | || iver == cris_ver_v0_10 | |
4302 | || iver == cris_ver_sim_v0_10 | |
4303 | || iver == cris_ver_v3_10 | |
4304 | || iver == cris_ver_v8 | |
4305 | || iver == cris_ver_v8p | |
4306 | || iver == cris_ver_v8_10 | |
4307 | || iver == cris_ver_v10 | |
4308 | || iver == cris_ver_v10p); | |
4309 | ||
4310 | case arch_crisv32: | |
4311 | return | |
4312 | (iver == cris_ver_version_all | |
4313 | || iver == cris_ver_v3p | |
4314 | || iver == cris_ver_v8p | |
4315 | || iver == cris_ver_v10p | |
4316 | || iver == cris_ver_v32p); | |
4317 | ||
4318 | case arch_cris_common_v10_v32: | |
4319 | return | |
4320 | (iver == cris_ver_version_all | |
4321 | || iver == cris_ver_v3p | |
4322 | || iver == cris_ver_v8p | |
4323 | || iver == cris_ver_v10p); | |
4324 | ||
4325 | case arch_crisv0: | |
4326 | return | |
4327 | (iver == cris_ver_version_all | |
4328 | || iver == cris_ver_v0_3 | |
4329 | || iver == cris_ver_v0_10 | |
4330 | || iver == cris_ver_sim_v0_10); | |
4331 | ||
4332 | case arch_crisv3: | |
4333 | return | |
4334 | (iver == cris_ver_version_all | |
4335 | || iver == cris_ver_v0_3 | |
4336 | || iver == cris_ver_v3p | |
4337 | || iver == cris_ver_v0_10 | |
4338 | || iver == cris_ver_sim_v0_10 | |
4339 | || iver == cris_ver_v3_10); | |
4340 | ||
4341 | case arch_crisv8: | |
4342 | return | |
4343 | (iver == cris_ver_version_all | |
4344 | || iver == cris_ver_v3p | |
4345 | || iver == cris_ver_v0_10 | |
4346 | || iver == cris_ver_sim_v0_10 | |
4347 | || iver == cris_ver_v3_10 | |
4348 | || iver == cris_ver_v8 | |
4349 | || iver == cris_ver_v8p | |
4350 | || iver == cris_ver_v8_10); | |
4351 | ||
4352 | case arch_crisv10: | |
4353 | return | |
4354 | (iver == cris_ver_version_all | |
4355 | || iver == cris_ver_v3p | |
4356 | || iver == cris_ver_v0_10 | |
4357 | || iver == cris_ver_sim_v0_10 | |
4358 | || iver == cris_ver_v3_10 | |
4359 | || iver == cris_ver_v8p | |
4360 | || iver == cris_ver_v8_10 | |
4361 | || iver == cris_ver_v10 | |
4362 | || iver == cris_ver_v10p); | |
4363 | ||
4364 | default: | |
4365 | BAD_CASE (arch); | |
4366 | } | |
4367 | } | |
4368 | ||
4369 | /* Assert that the .arch ARCHCHOICE1 is compatible with the specified or | |
4370 | default --march=<ARCHCHOICE2> option. */ | |
4371 | ||
4372 | static void | |
695a4822 | 4373 | s_cris_arch (int dummy ATTRIBUTE_UNUSED) |
ae57792d HPN |
4374 | { |
4375 | /* Right now we take the easy route and check for sameness. It's not | |
4376 | obvious that allowing e.g. --march=v32 and .arch common_v0_v32 | |
4377 | would be more useful than confusing, implementation-wise and | |
4378 | user-wise. */ | |
4379 | ||
4380 | char *str = input_line_pointer; | |
4381 | enum cris_archs arch = cris_arch_from_string (&str); | |
4382 | ||
4383 | if (arch == arch_cris_unknown) | |
4384 | { | |
4385 | as_bad (_("unknown operand to .arch")); | |
4386 | ||
4387 | /* For this one, str does not reflect the end of the operand, | |
4388 | since there was no matching arch. Skip it manually; skip | |
4389 | things that can be part of a word (a name). */ | |
4390 | while (is_part_of_name (*str)) | |
4391 | str++; | |
4392 | } | |
4393 | else if (arch != cris_arch) | |
4394 | as_bad (_(".arch <arch> requires a matching --march=... option")); | |
4395 | ||
4396 | input_line_pointer = str; | |
4397 | demand_empty_rest_of_line (); | |
4398 | return; | |
4399 | } | |
4400 | ||
3bcbcc3d HPN |
4401 | /* |
4402 | * Local variables: | |
4403 | * eval: (c-set-style "gnu") | |
4404 | * indent-tabs-mode: t | |
4405 | * End: | |
4406 | */ |