Commit | Line | Data |
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3bcbcc3d | 1 | /* tc-cris.c -- Assembler code for the CRIS CPU core. |
ec2655a6 | 2 | Copyright 2000, 2001, 2002, 2003, 2004, 2006, 2007 |
ebd1c875 | 3 | Free Software Foundation, Inc. |
3bcbcc3d HPN |
4 | |
5 | Contributed by Axis Communications AB, Lund, Sweden. | |
6 | Originally written for GAS 1.38.1 by Mikael Asker. | |
08caf3f8 | 7 | Updates, BFDizing, GNUifying and ELF support by Hans-Peter Nilsson. |
3bcbcc3d HPN |
8 | |
9 | This file is part of GAS, the GNU Assembler. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 13 | the Free Software Foundation; either version 3, or (at your option) |
3bcbcc3d HPN |
14 | any later version. |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the | |
4b4da160 NC |
23 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
24 | MA 02110-1301, USA. */ | |
3bcbcc3d | 25 | |
3bcbcc3d | 26 | #include "as.h" |
3882b010 | 27 | #include "safe-ctype.h" |
3bcbcc3d HPN |
28 | #include "subsegs.h" |
29 | #include "opcode/cris.h" | |
fcdc20a4 | 30 | #include "dwarf2dbg.h" |
3bcbcc3d HPN |
31 | |
32 | /* Conventions used here: | |
33 | Generally speaking, pointers to binutils types such as "fragS" and | |
34 | "expressionS" get parameter and variable names ending in "P", such as | |
35 | "fragP", to harmonize with the rest of the binutils code. Other | |
36 | pointers get a "p" suffix, such as "bufp". Any function or type-name | |
37 | that could clash with a current or future binutils or GAS function get | |
38 | a "cris_" prefix. */ | |
39 | ||
7b15d668 HPN |
40 | #define SYNTAX_RELAX_REG_PREFIX "no_register_prefix" |
41 | #define SYNTAX_ENFORCE_REG_PREFIX "register_prefix" | |
42 | #define SYNTAX_USER_SYM_LEADING_UNDERSCORE "leading_underscore" | |
43 | #define SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE "no_leading_underscore" | |
44 | #define REGISTER_PREFIX_CHAR '$' | |
45 | ||
1c971160 HPN |
46 | /* True for expressions where getting X_add_symbol and X_add_number is |
47 | enough to get the "base" and "offset"; no need to make_expr_symbol. | |
48 | It's not enough to check if X_op_symbol is NULL; that misses unary | |
49 | operations like O_uminus. */ | |
50 | #define SIMPLE_EXPR(EXP) \ | |
51 | ((EXP)->X_op == O_constant || (EXP)->X_op == O_symbol) | |
52 | ||
08caf3f8 HPN |
53 | /* Like in ":GOT", ":GOTOFF" etc. Other ports use '@', but that's in |
54 | line_separator_chars for CRIS, so we avoid it. */ | |
cc99daad | 55 | #define RELOC_SUFFIX_CHAR ':' |
08caf3f8 | 56 | |
3bcbcc3d HPN |
57 | /* This might be CRIS_INSN_NONE if we're assembling a prefix-insn only. |
58 | Note that some prefix-insns might be assembled as CRIS_INSN_NORMAL. */ | |
59 | enum cris_insn_kind | |
60 | { | |
1048a9ba | 61 | CRIS_INSN_NORMAL, CRIS_INSN_NONE, CRIS_INSN_BRANCH, CRIS_INSN_MUL |
3bcbcc3d HPN |
62 | }; |
63 | ||
64 | /* An instruction will have one of these prefixes. | |
65 | Although the same bit-pattern, we handle BDAP with an immediate | |
66 | expression (eventually quick or [pc+]) different from when we only have | |
67 | register expressions. */ | |
68 | enum prefix_kind | |
69 | { | |
70 | PREFIX_NONE, PREFIX_BDAP_IMM, PREFIX_BDAP, PREFIX_BIAP, PREFIX_DIP, | |
71 | PREFIX_PUSH | |
72 | }; | |
73 | ||
74 | /* The prefix for an instruction. */ | |
75 | struct cris_prefix | |
76 | { | |
47926f60 KH |
77 | enum prefix_kind kind; |
78 | int base_reg_number; | |
79 | unsigned int opcode; | |
3bcbcc3d HPN |
80 | |
81 | /* There might be an expression to be evaluated, like I in [rN+I]. */ | |
47926f60 | 82 | expressionS expr; |
3bcbcc3d HPN |
83 | |
84 | /* If there's an expression, we might need a relocation. Here's the | |
85 | type of what relocation to start relaxaton with. | |
86 | The relocation is assumed to start immediately after the prefix insn, | |
87 | so we don't provide an offset. */ | |
88 | enum bfd_reloc_code_real reloc; | |
89 | }; | |
90 | ||
47926f60 | 91 | /* The description of the instruction being assembled. */ |
3bcbcc3d HPN |
92 | struct cris_instruction |
93 | { | |
94 | /* If CRIS_INSN_NONE, then this insn is of zero length. */ | |
47926f60 | 95 | enum cris_insn_kind insn_type; |
3bcbcc3d HPN |
96 | |
97 | /* If a special register was mentioned, this is its description, else | |
47926f60 | 98 | it is NULL. */ |
3bcbcc3d HPN |
99 | const struct cris_spec_reg *spec_reg; |
100 | ||
47926f60 | 101 | unsigned int opcode; |
3bcbcc3d HPN |
102 | |
103 | /* An insn may have at most one expression; theoretically there could be | |
47926f60 KH |
104 | another in its prefix (but I don't see how that could happen). */ |
105 | expressionS expr; | |
3bcbcc3d HPN |
106 | |
107 | /* The expression might need a relocation. Here's one to start | |
108 | relaxation with. */ | |
47926f60 | 109 | enum bfd_reloc_code_real reloc; |
3bcbcc3d | 110 | |
08caf3f8 | 111 | /* The size in bytes of an immediate expression, or zero if |
3bcbcc3d | 112 | nonapplicable. */ |
47926f60 | 113 | int imm_oprnd_size; |
3bcbcc3d HPN |
114 | }; |
115 | ||
ae57792d HPN |
116 | enum cris_archs |
117 | { | |
118 | arch_cris_unknown, | |
119 | arch_crisv0, arch_crisv3, arch_crisv8, arch_crisv10, | |
120 | arch_cris_any_v0_v10, arch_crisv32, arch_cris_common_v10_v32 | |
121 | }; | |
122 | ||
695a4822 HPN |
123 | static enum cris_archs cris_arch_from_string (char **); |
124 | static int cris_insn_ver_valid_for_arch (enum cris_insn_version_usage, | |
125 | enum cris_archs); | |
126 | ||
127 | static void cris_process_instruction (char *, struct cris_instruction *, | |
128 | struct cris_prefix *); | |
129 | static int get_bwd_size_modifier (char **, int *); | |
130 | static int get_bw_size_modifier (char **, int *); | |
131 | static int get_gen_reg (char **, int *); | |
132 | static int get_spec_reg (char **, const struct cris_spec_reg **); | |
133 | static int get_sup_reg (char **, int *); | |
134 | static int get_autoinc_prefix_or_indir_op (char **, struct cris_prefix *, | |
135 | int *, int *, int *, | |
136 | expressionS *); | |
137 | static int get_3op_or_dip_prefix_op (char **, struct cris_prefix *); | |
138 | static int cris_get_expression (char **, expressionS *); | |
139 | static int get_flags (char **, int *); | |
140 | static void gen_bdap (int, expressionS *); | |
141 | static int branch_disp (int); | |
142 | static void gen_cond_branch_32 (char *, char *, fragS *, symbolS *, symbolS *, | |
143 | long int); | |
144 | static void cris_number_to_imm (char *, long, int, fixS *, segT); | |
145 | static void cris_create_short_jump (char *, addressT, addressT, fragS *, | |
146 | symbolS *); | |
147 | static void s_syntax (int); | |
148 | static void s_cris_file (int); | |
149 | static void s_cris_loc (int); | |
150 | static void s_cris_arch (int); | |
7b15d668 | 151 | |
08caf3f8 | 152 | /* Get ":GOT", ":GOTOFF", ":PLT" etc. suffixes. */ |
cc99daad HPN |
153 | static void cris_get_reloc_suffix (char **, bfd_reloc_code_real_type *, |
154 | expressionS *); | |
155 | static unsigned int cris_get_specified_reloc_size (bfd_reloc_code_real_type); | |
08caf3f8 | 156 | |
7b15d668 | 157 | /* All the .syntax functions. */ |
695a4822 HPN |
158 | static void cris_force_reg_prefix (void); |
159 | static void cris_relax_reg_prefix (void); | |
160 | static void cris_sym_leading_underscore (void); | |
161 | static void cris_sym_no_leading_underscore (void); | |
162 | static char *cris_insn_first_word_frag (void); | |
7b15d668 | 163 | |
3bcbcc3d HPN |
164 | /* Handle to the opcode hash table. */ |
165 | static struct hash_control *op_hash = NULL; | |
166 | ||
399f703e HPN |
167 | /* If we target cris-axis-linux-gnu (as opposed to generic cris-axis-elf), |
168 | we default to no underscore and required register-prefixes. The | |
169 | difference is in the default values. */ | |
170 | #ifdef TE_LINUX | |
171 | #define DEFAULT_CRIS_AXIS_LINUX_GNU TRUE | |
172 | #else | |
173 | #define DEFAULT_CRIS_AXIS_LINUX_GNU FALSE | |
174 | #endif | |
175 | ||
7b15d668 | 176 | /* Whether we demand that registers have a `$' prefix. Default here. */ |
399f703e | 177 | static bfd_boolean demand_register_prefix = DEFAULT_CRIS_AXIS_LINUX_GNU; |
7b15d668 HPN |
178 | |
179 | /* Whether global user symbols have a leading underscore. Default here. */ | |
399f703e HPN |
180 | static bfd_boolean symbols_have_leading_underscore |
181 | = !DEFAULT_CRIS_AXIS_LINUX_GNU; | |
7b15d668 | 182 | |
08caf3f8 | 183 | /* Whether or not we allow PIC, and expand to PIC-friendly constructs. */ |
b34976b6 | 184 | static bfd_boolean pic = FALSE; |
08caf3f8 | 185 | |
cc99daad HPN |
186 | /* Whether or not we allow TLS suffixes. For the moment, we always do. */ |
187 | static const bfd_boolean tls = TRUE; | |
188 | ||
ae57792d HPN |
189 | /* If we're configured for "cris", default to allow all v0..v10 |
190 | instructions and register names. */ | |
191 | #ifndef DEFAULT_CRIS_ARCH | |
192 | #define DEFAULT_CRIS_ARCH cris_any_v0_v10 | |
193 | #endif | |
194 | ||
195 | /* No whitespace in the CONCAT2 parameter list. */ | |
196 | static enum cris_archs cris_arch = XCONCAT2 (arch_,DEFAULT_CRIS_ARCH); | |
197 | ||
3bcbcc3d HPN |
198 | const pseudo_typeS md_pseudo_table[] = |
199 | { | |
200 | {"dword", cons, 4}, | |
7b15d668 | 201 | {"syntax", s_syntax, 0}, |
fcdc20a4 HPN |
202 | {"file", s_cris_file, 0}, |
203 | {"loc", s_cris_loc, 0}, | |
ae57792d | 204 | {"arch", s_cris_arch, 0}, |
3bcbcc3d HPN |
205 | {NULL, 0, 0} |
206 | }; | |
207 | ||
208 | static int warn_for_branch_expansion = 0; | |
209 | ||
1048a9ba HPN |
210 | /* Whether to emit error when a MULS/MULU could be located last on a |
211 | cache-line. */ | |
ae57792d HPN |
212 | static int err_for_dangerous_mul_placement |
213 | = (XCONCAT2 (arch_,DEFAULT_CRIS_ARCH) != arch_crisv32); | |
1048a9ba | 214 | |
3bcbcc3d HPN |
215 | const char cris_comment_chars[] = ";"; |
216 | ||
217 | /* This array holds the chars that only start a comment at the beginning of | |
218 | a line. If the line seems to have the form '# 123 filename' | |
47926f60 | 219 | .line and .file directives will appear in the pre-processed output. */ |
3bcbcc3d HPN |
220 | /* Note that input_file.c hand-checks for '#' at the beginning of the |
221 | first line of the input file. This is because the compiler outputs | |
47926f60 KH |
222 | #NO_APP at the beginning of its output. */ |
223 | /* Also note that slash-star will always start a comment. */ | |
3bcbcc3d HPN |
224 | const char line_comment_chars[] = "#"; |
225 | const char line_separator_chars[] = "@"; | |
226 | ||
227 | /* Now all floating point support is shut off. See md_atof. */ | |
228 | const char EXP_CHARS[] = ""; | |
229 | const char FLT_CHARS[] = ""; | |
230 | ||
3bcbcc3d HPN |
231 | /* For CRIS, we encode the relax_substateTs (in e.g. fr_substate) as: |
232 | 2 1 0 | |
233 | ---/ /--+-----------------+-----------------+-----------------+ | |
234 | | what state ? | how long ? | | |
235 | ---/ /--+-----------------+-----------------+-----------------+ | |
236 | ||
237 | The "how long" bits are 00 = byte, 01 = word, 10 = dword (long). | |
3bcbcc3d HPN |
238 | Not all lengths are legit for a given value of (what state). |
239 | ||
240 | Groups for CRIS address relaxing: | |
241 | ||
ae57792d | 242 | 1. Bcc (pre-V32) |
3bcbcc3d HPN |
243 | length: byte, word, 10-byte expansion |
244 | ||
245 | 2. BDAP | |
1048a9ba HPN |
246 | length: byte, word, dword |
247 | ||
248 | 3. MULS/MULU | |
249 | Not really a relaxation (no infrastructure to get delay-slots | |
250 | right), just an alignment and placement checker for the v10 | |
ae57792d HPN |
251 | multiply/cache-bug. |
252 | ||
253 | 4. Bcc (V32 and later) | |
254 | length: byte, word, 14-byte expansion | |
255 | ||
256 | 5. Bcc (V10+V32) | |
257 | length: byte, word, error | |
258 | ||
259 | 6. BA (V32) | |
260 | length: byte, word, dword | |
3bcbcc3d | 261 | |
ae57792d HPN |
262 | 7. LAPC (V32) |
263 | length: byte, dword | |
264 | */ | |
265 | ||
266 | #define STATE_COND_BRANCH (1) | |
3bcbcc3d | 267 | #define STATE_BASE_PLUS_DISP_PREFIX (2) |
1048a9ba | 268 | #define STATE_MUL (3) |
ae57792d HPN |
269 | #define STATE_COND_BRANCH_V32 (4) |
270 | #define STATE_COND_BRANCH_COMMON (5) | |
271 | #define STATE_ABS_BRANCH_V32 (6) | |
272 | #define STATE_LAPC (7) | |
d2aa3f9f | 273 | #define STATE_COND_BRANCH_PIC (8) |
3bcbcc3d HPN |
274 | |
275 | #define STATE_LENGTH_MASK (3) | |
276 | #define STATE_BYTE (0) | |
277 | #define STATE_WORD (1) | |
278 | #define STATE_DWORD (2) | |
279 | /* Symbol undefined. */ | |
280 | #define STATE_UNDF (3) | |
281 | #define STATE_MAX_LENGTH (3) | |
282 | ||
2d2255b5 | 283 | /* These displacements are relative to the address following the opcode |
3bcbcc3d HPN |
284 | word of the instruction. The first letter is Byte, Word. The 2nd |
285 | letter is Forward, Backward. */ | |
286 | ||
287 | #define BRANCH_BF ( 254) | |
288 | #define BRANCH_BB (-256) | |
ae57792d HPN |
289 | #define BRANCH_BF_V32 ( 252) |
290 | #define BRANCH_BB_V32 (-258) | |
47926f60 KH |
291 | #define BRANCH_WF (2 + 32767) |
292 | #define BRANCH_WB (2 + -32768) | |
ae57792d HPN |
293 | #define BRANCH_WF_V32 (-2 + 32767) |
294 | #define BRANCH_WB_V32 (-2 + -32768) | |
3bcbcc3d HPN |
295 | |
296 | #define BDAP_BF ( 127) | |
297 | #define BDAP_BB (-128) | |
298 | #define BDAP_WF ( 32767) | |
299 | #define BDAP_WB (-32768) | |
300 | ||
301 | #define ENCODE_RELAX(what, length) (((what) << 2) + (length)) | |
302 | ||
303 | const relax_typeS md_cris_relax_table[] = | |
304 | { | |
305 | /* Error sentinel (0, 0). */ | |
306 | {1, 1, 0, 0}, | |
307 | ||
308 | /* Unused (0, 1). */ | |
309 | {1, 1, 0, 0}, | |
310 | ||
311 | /* Unused (0, 2). */ | |
312 | {1, 1, 0, 0}, | |
313 | ||
314 | /* Unused (0, 3). */ | |
315 | {1, 1, 0, 0}, | |
316 | ||
317 | /* Bcc o (1, 0). */ | |
318 | {BRANCH_BF, BRANCH_BB, 0, ENCODE_RELAX (1, 1)}, | |
319 | ||
47926f60 | 320 | /* Bcc [PC+] (1, 1). */ |
3bcbcc3d HPN |
321 | {BRANCH_WF, BRANCH_WB, 2, ENCODE_RELAX (1, 2)}, |
322 | ||
323 | /* BEXT/BWF, BA, JUMP (external), JUMP (always), Bnot_cc, JUMP (default) | |
324 | (1, 2). */ | |
325 | {0, 0, 10, 0}, | |
326 | ||
327 | /* Unused (1, 3). */ | |
328 | {1, 1, 0, 0}, | |
329 | ||
330 | /* BDAP o (2, 0). */ | |
331 | {BDAP_BF, BDAP_BB, 0, ENCODE_RELAX (2, 1)}, | |
332 | ||
333 | /* BDAP.[bw] [PC+] (2, 1). */ | |
334 | {BDAP_WF, BDAP_WB, 2, ENCODE_RELAX (2, 2)}, | |
335 | ||
336 | /* BDAP.d [PC+] (2, 2). */ | |
1048a9ba HPN |
337 | {0, 0, 4, 0}, |
338 | ||
339 | /* Unused (2, 3). */ | |
ae57792d | 340 | {1, 1, 0, 0}, |
1048a9ba HPN |
341 | |
342 | /* MULS/MULU (3, 0). Positions (3, 1..3) are unused. */ | |
ae57792d HPN |
343 | {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, |
344 | ||
345 | /* V32: Bcc o (4, 0). */ | |
346 | {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (4, 1)}, | |
347 | ||
348 | /* V32: Bcc [PC+] (4, 1). */ | |
349 | {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (4, 2)}, | |
350 | ||
351 | /* V32: BA .+12; NOP; BA32 target; NOP; Bcc .-6 (4, 2). */ | |
352 | {0, 0, 12, 0}, | |
353 | ||
354 | /* Unused (4, 3). */ | |
355 | {1, 1, 0, 0}, | |
356 | ||
357 | /* COMMON: Bcc o (5, 0). The offsets are calculated as for v32. Code | |
358 | should contain two nop insns (or four if offset size is large or | |
359 | unknown) after every label. */ | |
360 | {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (5, 1)}, | |
361 | ||
362 | /* COMMON: Bcc [PC+] (5, 1). */ | |
363 | {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (5, 2)}, | |
364 | ||
365 | /* COMMON: FIXME: ???. Treat as error currently. */ | |
366 | {0, 0, 12, 0}, | |
367 | ||
368 | /* Unused (5, 3). */ | |
369 | {1, 1, 0, 0}, | |
370 | ||
371 | /* V32: BA o (6, 0). */ | |
372 | {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (6, 1)}, | |
373 | ||
374 | /* V32: BA.W (6, 1). */ | |
375 | {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (6, 2)}, | |
376 | ||
377 | /* V32: BA.D (6, 2). */ | |
378 | {0, 0, 4, 0}, | |
379 | ||
380 | /* Unused (6, 3). */ | |
381 | {1, 1, 0, 0}, | |
382 | ||
383 | /* LAPC: LAPCQ .+0..15*2,Rn (7, 0). */ | |
384 | {14*2, -1*2, 0, ENCODE_RELAX (7, 2)}, | |
385 | ||
386 | /* Unused (7, 1). | |
387 | While there's a shorter sequence, e.g. LAPCQ + an ADDQ or SUBQ, | |
388 | that would affect flags, so we can't do that as it wouldn't be a | |
389 | proper insn expansion of LAPCQ. This row is associated with a | |
390 | 2-byte expansion, so it's unused rather than the next. */ | |
391 | {1, 1, 0, 0}, | |
392 | ||
393 | /* LAPC: LAPC.D (7, 2). */ | |
394 | {0, 0, 4, 0}, | |
395 | ||
396 | /* Unused (7, 3). */ | |
d2aa3f9f HPN |
397 | {1, 1, 0, 0}, |
398 | ||
399 | /* PIC for pre-v32: Bcc o (8, 0). */ | |
400 | {BRANCH_BF, BRANCH_BB, 0, ENCODE_RELAX (STATE_COND_BRANCH_PIC, 1)}, | |
401 | ||
402 | /* Bcc [PC+] (8, 1). */ | |
403 | {BRANCH_WF, BRANCH_WB, 2, ENCODE_RELAX (STATE_COND_BRANCH_PIC, 2)}, | |
404 | ||
405 | /* 32-bit expansion, PIC (8, 2). */ | |
406 | {0, 0, 12, 0}, | |
407 | ||
408 | /* Unused (8, 3). */ | |
ae57792d | 409 | {1, 1, 0, 0} |
3bcbcc3d HPN |
410 | }; |
411 | ||
3bcbcc3d HPN |
412 | #undef BDAP_BF |
413 | #undef BDAP_BB | |
414 | #undef BDAP_WF | |
415 | #undef BDAP_WB | |
416 | ||
ae57792d | 417 | /* Target-specific multicharacter options, not const-declared. */ |
3bcbcc3d HPN |
418 | struct option md_longopts[] = |
419 | { | |
7b15d668 HPN |
420 | #define OPTION_NO_US (OPTION_MD_BASE + 0) |
421 | {"no-underscore", no_argument, NULL, OPTION_NO_US}, | |
422 | #define OPTION_US (OPTION_MD_BASE + 1) | |
423 | {"underscore", no_argument, NULL, OPTION_US}, | |
ae57792d | 424 | #define OPTION_PIC (OPTION_US + 1) |
08caf3f8 | 425 | {"pic", no_argument, NULL, OPTION_PIC}, |
ae57792d | 426 | #define OPTION_MULBUG_ABORT_ON (OPTION_PIC + 1) |
1048a9ba | 427 | {"mul-bug-abort", no_argument, NULL, OPTION_MULBUG_ABORT_ON}, |
ae57792d | 428 | #define OPTION_MULBUG_ABORT_OFF (OPTION_MULBUG_ABORT_ON + 1) |
1048a9ba | 429 | {"no-mul-bug-abort", no_argument, NULL, OPTION_MULBUG_ABORT_OFF}, |
ae57792d HPN |
430 | #define OPTION_ARCH (OPTION_MULBUG_ABORT_OFF + 1) |
431 | {"march", required_argument, NULL, OPTION_ARCH}, | |
3bcbcc3d HPN |
432 | {NULL, no_argument, NULL, 0} |
433 | }; | |
434 | ||
ae57792d | 435 | /* Not const-declared. */ |
3bcbcc3d HPN |
436 | size_t md_longopts_size = sizeof (md_longopts); |
437 | const char *md_shortopts = "hHN"; | |
438 | ||
3bcbcc3d HPN |
439 | /* At first glance, this may seems wrong and should be 4 (ba + nop); but |
440 | since a short_jump must skip a *number* of long jumps, it must also be | |
441 | a long jump. Here, we hope to make it a "ba [16bit_offs]" and a "nop" | |
442 | for the delay slot and hope that the jump table at most needs | |
443 | 32767/4=8191 long-jumps. A branch is better than a jump, since it is | |
444 | relative; we will not have a reloc to fix up somewhere. | |
445 | ||
446 | Note that we can't add relocs, because relaxation uses these fixed | |
447 | numbers, and md_create_short_jump is called after relaxation. */ | |
448 | ||
2b4f075a | 449 | int md_short_jump_size = 6; |
ae57792d | 450 | |
d2aa3f9f HPN |
451 | /* The v32 version has a delay-slot, hence two bytes longer. |
452 | The pre-v32 PIC version uses a prefixed insn. */ | |
ae57792d | 453 | #define cris_any_v0_v10_long_jump_size 6 |
d2aa3f9f | 454 | #define cris_any_v0_v10_long_jump_size_pic 8 |
ae57792d HPN |
455 | #define crisv32_long_jump_size 8 |
456 | ||
457 | int md_long_jump_size = XCONCAT2 (DEFAULT_CRIS_ARCH,_long_jump_size); | |
3bcbcc3d | 458 | |
7b15d668 | 459 | /* Report output format. Small changes in output format (like elf |
08caf3f8 HPN |
460 | variants below) can happen until all options are parsed, but after |
461 | that, the output format must remain fixed. */ | |
47926f60 | 462 | |
3bcbcc3d | 463 | const char * |
695a4822 | 464 | cris_target_format (void) |
3bcbcc3d HPN |
465 | { |
466 | switch (OUTPUT_FLAVOR) | |
467 | { | |
468 | case bfd_target_aout_flavour: | |
469 | return "a.out-cris"; | |
470 | ||
471 | case bfd_target_elf_flavour: | |
7b15d668 HPN |
472 | if (symbols_have_leading_underscore) |
473 | return "elf32-us-cris"; | |
3bcbcc3d HPN |
474 | return "elf32-cris"; |
475 | ||
476 | default: | |
477 | abort (); | |
478 | return NULL; | |
479 | } | |
480 | } | |
481 | ||
ae57792d HPN |
482 | /* Return a bfd_mach_cris... value corresponding to the value of |
483 | cris_arch. */ | |
484 | ||
485 | unsigned int | |
695a4822 | 486 | cris_mach (void) |
ae57792d HPN |
487 | { |
488 | unsigned int retval = 0; | |
489 | ||
490 | switch (cris_arch) | |
491 | { | |
492 | case arch_cris_common_v10_v32: | |
493 | retval = bfd_mach_cris_v10_v32; | |
494 | break; | |
495 | ||
496 | case arch_crisv32: | |
497 | retval = bfd_mach_cris_v32; | |
498 | break; | |
499 | ||
500 | case arch_crisv10: | |
501 | case arch_cris_any_v0_v10: | |
502 | retval = bfd_mach_cris_v0_v10; | |
503 | break; | |
504 | ||
505 | default: | |
506 | BAD_CASE (cris_arch); | |
507 | } | |
508 | ||
509 | return retval; | |
510 | } | |
511 | ||
1c971160 HPN |
512 | /* We need a port-specific relaxation function to cope with sym2 - sym1 |
513 | relative expressions with both symbols in the same segment (but not | |
514 | necessarily in the same frag as this insn), for example: | |
515 | move.d [pc+sym2-(sym1-2)],r10 | |
516 | sym1: | |
517 | The offset can be 8, 16 or 32 bits long. */ | |
518 | ||
519 | long | |
695a4822 HPN |
520 | cris_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS *fragP, |
521 | long stretch ATTRIBUTE_UNUSED) | |
1c971160 HPN |
522 | { |
523 | long growth; | |
524 | offsetT aim = 0; | |
525 | symbolS *symbolP; | |
526 | const relax_typeS *this_type; | |
527 | const relax_typeS *start_type; | |
528 | relax_substateT next_state; | |
529 | relax_substateT this_state; | |
530 | const relax_typeS *table = TC_GENERIC_RELAX_TABLE; | |
531 | ||
532 | /* We only have to cope with frags as prepared by | |
fb2fd3e1 | 533 | md_estimate_size_before_relax. The dword cases may get here |
1c971160 HPN |
534 | because of the different reasons that they aren't relaxable. */ |
535 | switch (fragP->fr_subtype) | |
536 | { | |
f6ce267c | 537 | case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD): |
ae57792d HPN |
538 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD): |
539 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD): | |
540 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD): | |
541 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD): | |
542 | case ENCODE_RELAX (STATE_LAPC, STATE_DWORD): | |
1c971160 HPN |
543 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): |
544 | /* When we get to these states, the frag won't grow any more. */ | |
545 | return 0; | |
546 | ||
547 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): | |
548 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): | |
549 | if (fragP->fr_symbol == NULL | |
550 | || S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) | |
551 | as_fatal (_("internal inconsistency problem in %s: fr_symbol %lx"), | |
552 | __FUNCTION__, (long) fragP->fr_symbol); | |
553 | symbolP = fragP->fr_symbol; | |
554 | if (symbol_resolved_p (symbolP)) | |
555 | as_fatal (_("internal inconsistency problem in %s: resolved symbol"), | |
556 | __FUNCTION__); | |
557 | aim = S_GET_VALUE (symbolP); | |
558 | break; | |
559 | ||
1048a9ba HPN |
560 | case ENCODE_RELAX (STATE_MUL, STATE_BYTE): |
561 | /* Nothing to do here. */ | |
562 | return 0; | |
563 | ||
1c971160 HPN |
564 | default: |
565 | as_fatal (_("internal inconsistency problem in %s: fr_subtype %d"), | |
566 | __FUNCTION__, fragP->fr_subtype); | |
567 | } | |
568 | ||
569 | /* The rest is stolen from relax_frag. There's no obvious way to | |
570 | share the code, but fortunately no requirement to keep in sync as | |
571 | long as fragP->fr_symbol does not have its segment changed. */ | |
572 | ||
573 | this_state = fragP->fr_subtype; | |
574 | start_type = this_type = table + this_state; | |
575 | ||
576 | if (aim < 0) | |
577 | { | |
578 | /* Look backwards. */ | |
579 | for (next_state = this_type->rlx_more; next_state;) | |
580 | if (aim >= this_type->rlx_backward) | |
581 | next_state = 0; | |
582 | else | |
583 | { | |
584 | /* Grow to next state. */ | |
585 | this_state = next_state; | |
586 | this_type = table + this_state; | |
587 | next_state = this_type->rlx_more; | |
588 | } | |
589 | } | |
590 | else | |
591 | { | |
592 | /* Look forwards. */ | |
593 | for (next_state = this_type->rlx_more; next_state;) | |
594 | if (aim <= this_type->rlx_forward) | |
595 | next_state = 0; | |
596 | else | |
597 | { | |
598 | /* Grow to next state. */ | |
599 | this_state = next_state; | |
600 | this_type = table + this_state; | |
601 | next_state = this_type->rlx_more; | |
602 | } | |
603 | } | |
604 | ||
605 | growth = this_type->rlx_length - start_type->rlx_length; | |
606 | if (growth != 0) | |
607 | fragP->fr_subtype = this_state; | |
608 | return growth; | |
609 | } | |
610 | ||
3bcbcc3d HPN |
611 | /* Prepare machine-dependent frags for relaxation. |
612 | ||
613 | Called just before relaxation starts. Any symbol that is now undefined | |
614 | will not become defined. | |
615 | ||
616 | Return the correct fr_subtype in the frag. | |
617 | ||
618 | Return the initial "guess for fr_var" to caller. The guess for fr_var | |
619 | is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix | |
620 | or fr_var contributes to our returned value. | |
621 | ||
622 | Although it may not be explicit in the frag, pretend | |
47926f60 | 623 | fr_var starts with a value. */ |
3bcbcc3d HPN |
624 | |
625 | int | |
695a4822 | 626 | md_estimate_size_before_relax (fragS *fragP, segT segment_type) |
3bcbcc3d | 627 | { |
47926f60 | 628 | int old_fr_fix; |
ae57792d HPN |
629 | symbolS *symbolP = fragP->fr_symbol; |
630 | ||
631 | #define HANDLE_RELAXABLE(state) \ | |
632 | case ENCODE_RELAX (state, STATE_UNDF): \ | |
633 | if (symbolP != NULL \ | |
634 | && S_GET_SEGMENT (symbolP) == segment_type \ | |
635 | && !S_IS_WEAK (symbolP)) \ | |
636 | /* The symbol lies in the same segment - a relaxable \ | |
637 | case. */ \ | |
638 | fragP->fr_subtype \ | |
639 | = ENCODE_RELAX (state, STATE_BYTE); \ | |
640 | else \ | |
641 | /* Unknown or not the same segment, so not relaxable. */ \ | |
642 | fragP->fr_subtype \ | |
643 | = ENCODE_RELAX (state, STATE_DWORD); \ | |
644 | fragP->fr_var \ | |
645 | = md_cris_relax_table[fragP->fr_subtype].rlx_length; \ | |
646 | break | |
3bcbcc3d HPN |
647 | |
648 | old_fr_fix = fragP->fr_fix; | |
649 | ||
650 | switch (fragP->fr_subtype) | |
651 | { | |
ae57792d HPN |
652 | HANDLE_RELAXABLE (STATE_COND_BRANCH); |
653 | HANDLE_RELAXABLE (STATE_COND_BRANCH_V32); | |
654 | HANDLE_RELAXABLE (STATE_COND_BRANCH_COMMON); | |
d2aa3f9f | 655 | HANDLE_RELAXABLE (STATE_COND_BRANCH_PIC); |
ae57792d HPN |
656 | HANDLE_RELAXABLE (STATE_ABS_BRANCH_V32); |
657 | ||
658 | case ENCODE_RELAX (STATE_LAPC, STATE_UNDF): | |
659 | if (symbolP != NULL | |
660 | && S_GET_SEGMENT (symbolP) == segment_type | |
661 | && !S_IS_WEAK (symbolP)) | |
662 | { | |
663 | /* The symbol lies in the same segment - a relaxable case. | |
664 | Check if we currently have an odd offset; we can't code | |
665 | that into the instruction. Relaxing presumably only cause | |
666 | multiple-of-two changes, so we should only need to adjust | |
667 | for that here. */ | |
668 | bfd_vma target_address | |
669 | = (symbolP | |
670 | ? S_GET_VALUE (symbolP) | |
671 | : 0) + fragP->fr_offset; | |
672 | bfd_vma var_part_offset = fragP->fr_fix; | |
673 | bfd_vma address_of_var_part = fragP->fr_address + var_part_offset; | |
674 | long offset = target_address - (address_of_var_part - 2); | |
675 | ||
676 | fragP->fr_subtype | |
677 | = (offset & 1) | |
678 | ? ENCODE_RELAX (STATE_LAPC, STATE_DWORD) | |
679 | : ENCODE_RELAX (STATE_LAPC, STATE_BYTE); | |
680 | } | |
3bcbcc3d | 681 | else |
c335d394 HPN |
682 | /* Unknown or not the same segment, so not relaxable. */ |
683 | fragP->fr_subtype | |
ae57792d HPN |
684 | = ENCODE_RELAX (STATE_LAPC, STATE_DWORD); |
685 | fragP->fr_var | |
686 | = md_cris_relax_table[fragP->fr_subtype].rlx_length; | |
3bcbcc3d HPN |
687 | break; |
688 | ||
689 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF): | |
690 | /* Note that we can not do anything sane with relaxing | |
691 | [rX + a_known_symbol_in_text], it will have to be a 32-bit | |
692 | value. | |
693 | ||
694 | We could play tricks with managing a constant pool and make | |
08caf3f8 HPN |
695 | a_known_symbol_in_text a "bdap [pc + offset]" pointing there |
696 | (like the GOT for ELF shared libraries), but that's no use, it | |
697 | would in general be no shorter or faster code, only more | |
698 | complicated. */ | |
3bcbcc3d | 699 | |
ae57792d | 700 | if (S_GET_SEGMENT (symbolP) != absolute_section) |
3bcbcc3d HPN |
701 | { |
702 | /* Go for dword if not absolute or same segment. */ | |
703 | fragP->fr_subtype | |
704 | = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD); | |
c335d394 | 705 | fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; |
3bcbcc3d | 706 | } |
1c971160 HPN |
707 | else if (!symbol_resolved_p (fragP->fr_symbol)) |
708 | { | |
709 | /* The symbol will eventually be completely resolved as an | |
710 | absolute expression, but right now it depends on the result | |
711 | of relaxation and we don't know anything else about the | |
712 | value. We start relaxation with the assumption that it'll | |
713 | fit in a byte. */ | |
714 | fragP->fr_subtype | |
715 | = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE); | |
716 | fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; | |
717 | } | |
3bcbcc3d HPN |
718 | else |
719 | { | |
720 | /* Absolute expression. */ | |
721 | long int value; | |
ae57792d HPN |
722 | value = (symbolP != NULL |
723 | ? S_GET_VALUE (symbolP) : 0) + fragP->fr_offset; | |
3bcbcc3d HPN |
724 | |
725 | if (value >= -128 && value <= 127) | |
726 | { | |
727 | /* Byte displacement. */ | |
728 | (fragP->fr_opcode)[0] = value; | |
729 | } | |
730 | else | |
731 | { | |
732 | /* Word or dword displacement. */ | |
733 | int pow2_of_size = 1; | |
734 | char *writep; | |
735 | ||
736 | if (value < -32768 || value > 32767) | |
737 | { | |
738 | /* Outside word range, make it a dword. */ | |
739 | pow2_of_size = 2; | |
740 | } | |
741 | ||
742 | /* Modify the byte-offset BDAP into a word or dword offset | |
743 | BDAP. Or really, a BDAP rX,8bit into a | |
07e90ad5 | 744 | BDAP.[wd] rX,[PC+] followed by a word or dword. */ |
3bcbcc3d HPN |
745 | (fragP->fr_opcode)[0] = BDAP_PC_LOW + pow2_of_size * 16; |
746 | ||
747 | /* Keep the register number in the highest four bits. */ | |
748 | (fragP->fr_opcode)[1] &= 0xF0; | |
749 | (fragP->fr_opcode)[1] |= BDAP_INCR_HIGH; | |
750 | ||
47926f60 | 751 | /* It grew by two or four bytes. */ |
3bcbcc3d HPN |
752 | fragP->fr_fix += 1 << pow2_of_size; |
753 | writep = fragP->fr_literal + old_fr_fix; | |
754 | md_number_to_chars (writep, value, 1 << pow2_of_size); | |
755 | } | |
756 | frag_wane (fragP); | |
757 | } | |
758 | break; | |
759 | ||
ae57792d HPN |
760 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_BYTE): |
761 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_WORD): | |
762 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD): | |
d2aa3f9f HPN |
763 | case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_BYTE): |
764 | case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_WORD): | |
765 | case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD): | |
ae57792d HPN |
766 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_BYTE): |
767 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_WORD): | |
768 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD): | |
769 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_BYTE): | |
770 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_WORD): | |
771 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD): | |
772 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_BYTE): | |
773 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_WORD): | |
774 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD): | |
775 | case ENCODE_RELAX (STATE_LAPC, STATE_BYTE): | |
776 | case ENCODE_RELAX (STATE_LAPC, STATE_DWORD): | |
c335d394 HPN |
777 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): |
778 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): | |
93c2a809 AM |
779 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): |
780 | /* When relaxing a section for the second time, we don't need to | |
c335d394 HPN |
781 | do anything except making sure that fr_var is set right. */ |
782 | fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; | |
93c2a809 AM |
783 | break; |
784 | ||
1048a9ba HPN |
785 | case ENCODE_RELAX (STATE_MUL, STATE_BYTE): |
786 | /* Nothing to do here. */ | |
787 | break; | |
788 | ||
3bcbcc3d HPN |
789 | default: |
790 | BAD_CASE (fragP->fr_subtype); | |
791 | } | |
792 | ||
793 | return fragP->fr_var + (fragP->fr_fix - old_fr_fix); | |
794 | } | |
795 | ||
3bcbcc3d HPN |
796 | /* Perform post-processing of machine-dependent frags after relaxation. |
797 | Called after relaxation is finished. | |
798 | In: Address of frag. | |
799 | fr_type == rs_machine_dependent. | |
800 | fr_subtype is what the address relaxed to. | |
801 | ||
802 | Out: Any fixS:s and constants are set up. | |
803 | ||
804 | The caller will turn the frag into a ".space 0". */ | |
805 | ||
806 | void | |
695a4822 HPN |
807 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
808 | fragS *fragP) | |
3bcbcc3d | 809 | { |
47926f60 | 810 | /* Pointer to first byte in variable-sized part of the frag. */ |
3bcbcc3d HPN |
811 | char *var_partp; |
812 | ||
813 | /* Pointer to first opcode byte in frag. */ | |
814 | char *opcodep; | |
815 | ||
816 | /* Used to check integrity of the relaxation. | |
817 | One of 2 = long, 1 = word, or 0 = byte. */ | |
818 | int length_code; | |
819 | ||
820 | /* Size in bytes of variable-sized part of frag. */ | |
821 | int var_part_size = 0; | |
822 | ||
823 | /* This is part of *fragP. It contains all information about addresses | |
824 | and offsets to varying parts. */ | |
825 | symbolS *symbolP; | |
826 | unsigned long var_part_offset; | |
827 | ||
828 | /* Where, in file space, is _var of *fragP? */ | |
829 | unsigned long address_of_var_part = 0; | |
830 | ||
831 | /* Where, in file space, does addr point? */ | |
832 | unsigned long target_address; | |
833 | ||
834 | know (fragP->fr_type == rs_machine_dependent); | |
835 | ||
836 | length_code = fragP->fr_subtype & STATE_LENGTH_MASK; | |
837 | know (length_code >= 0 && length_code < STATE_MAX_LENGTH); | |
838 | ||
839 | var_part_offset = fragP->fr_fix; | |
840 | var_partp = fragP->fr_literal + var_part_offset; | |
841 | opcodep = fragP->fr_opcode; | |
842 | ||
843 | symbolP = fragP->fr_symbol; | |
ac62c346 | 844 | target_address = (symbolP ? S_GET_VALUE (symbolP) : 0) + fragP->fr_offset; |
3bcbcc3d HPN |
845 | address_of_var_part = fragP->fr_address + var_part_offset; |
846 | ||
847 | switch (fragP->fr_subtype) | |
47926f60 | 848 | { |
ae57792d | 849 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_BYTE): |
d2aa3f9f | 850 | case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_BYTE): |
ae57792d HPN |
851 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_BYTE): |
852 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_BYTE): | |
853 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_BYTE): | |
47926f60 KH |
854 | opcodep[0] = branch_disp ((target_address - address_of_var_part)); |
855 | var_part_size = 0; | |
856 | break; | |
3bcbcc3d | 857 | |
ae57792d | 858 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_WORD): |
d2aa3f9f | 859 | case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_WORD): |
ae57792d HPN |
860 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_WORD): |
861 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_WORD): | |
862 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_WORD): | |
47926f60 KH |
863 | /* We had a quick immediate branch, now turn it into a word one i.e. a |
864 | PC autoincrement. */ | |
865 | opcodep[0] = BRANCH_PC_LOW; | |
866 | opcodep[1] &= 0xF0; | |
867 | opcodep[1] |= BRANCH_INCR_HIGH; | |
868 | md_number_to_chars (var_partp, | |
ae57792d HPN |
869 | (long) |
870 | (target_address | |
871 | - (address_of_var_part | |
872 | + (cris_arch == arch_crisv32 | |
873 | || cris_arch == arch_cris_common_v10_v32 | |
874 | ? -2 : 2))), | |
47926f60 KH |
875 | 2); |
876 | var_part_size = 2; | |
877 | break; | |
878 | ||
ae57792d | 879 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD): |
47926f60 KH |
880 | gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP, |
881 | fragP->fr_symbol, (symbolS *) NULL, | |
882 | fragP->fr_offset); | |
883 | /* Ten bytes added: a branch, nop and a jump. */ | |
884 | var_part_size = 2 + 2 + 4 + 2; | |
885 | break; | |
3bcbcc3d | 886 | |
d2aa3f9f HPN |
887 | case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD): |
888 | gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP, | |
889 | fragP->fr_symbol, (symbolS *) NULL, | |
890 | fragP->fr_offset); | |
891 | /* Twelve bytes added: a branch, nop and a pic-branch-32. */ | |
892 | var_part_size = 2 + 2 + 4 + 2 + 2; | |
893 | break; | |
894 | ||
ae57792d HPN |
895 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD): |
896 | gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP, | |
897 | fragP->fr_symbol, (symbolS *) NULL, | |
898 | fragP->fr_offset); | |
899 | /* Twelve bytes added: a branch, nop and another branch and nop. */ | |
900 | var_part_size = 2 + 2 + 2 + 4 + 2; | |
901 | break; | |
902 | ||
903 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD): | |
904 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
905 | _("Relaxation to long branches for .arch common_v10_v32\ | |
906 | not implemented")); | |
907 | /* Pretend we have twelve bytes for sake of quelling further | |
908 | errors. */ | |
909 | var_part_size = 2 + 2 + 2 + 4 + 2; | |
910 | break; | |
911 | ||
912 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD): | |
913 | /* We had a quick immediate branch or a word immediate ba. Now | |
914 | turn it into a dword one. */ | |
915 | opcodep[0] = BA_DWORD_OPCODE & 255; | |
916 | opcodep[1] = (BA_DWORD_OPCODE >> 8) & 255; | |
917 | fix_new (fragP, var_partp - fragP->fr_literal, 4, symbolP, | |
918 | fragP->fr_offset + 6, 1, BFD_RELOC_32_PCREL); | |
919 | var_part_size = 4; | |
920 | break; | |
921 | ||
922 | case ENCODE_RELAX (STATE_LAPC, STATE_BYTE): | |
923 | { | |
924 | long offset = target_address - (address_of_var_part - 2); | |
925 | ||
926 | /* This is mostly a sanity check; useful occurrences (if there | |
927 | really are any) should have been caught in | |
928 | md_estimate_size_before_relax. We can (at least | |
929 | theoretically) stumble over invalid code with odd sizes and | |
930 | .p2aligns within the code, so emit an error if that happens. | |
931 | (The generic relaxation machinery is not fit to check this.) */ | |
932 | ||
933 | if (offset & 1) | |
934 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
935 | _("Complicated LAPC target operand is not\ | |
936 | a multiple of two. Use LAPC.D")); | |
937 | ||
938 | /* FIXME: This *is* a sanity check. Remove when done with. */ | |
939 | if (offset > 15*2 || offset < 0) | |
940 | as_fatal (_("Internal error found in md_convert_frag: offset %ld.\ | |
941 | Please report this."), | |
942 | offset); | |
943 | ||
944 | opcodep[0] |= (offset / 2) & 0xf; | |
945 | var_part_size = 0; | |
946 | } | |
947 | break; | |
948 | ||
949 | case ENCODE_RELAX (STATE_LAPC, STATE_DWORD): | |
950 | { | |
951 | md_number_to_chars (opcodep, | |
952 | LAPC_DWORD_OPCODE + (opcodep[1] & 0xf0) * 256, | |
953 | 2); | |
954 | /* Remember that the reloc is against the position *after* the | |
955 | relocated contents, so we need to adjust to the start of | |
956 | the insn. */ | |
957 | fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol, | |
958 | fragP->fr_offset + 6, 1, BFD_RELOC_32_PCREL); | |
959 | var_part_size = 4; | |
960 | } | |
961 | break; | |
962 | ||
47926f60 | 963 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): |
1c971160 HPN |
964 | if (symbolP == NULL) |
965 | as_fatal (_("internal inconsistency in %s: bdapq no symbol"), | |
966 | __FUNCTION__); | |
967 | opcodep[0] = S_GET_VALUE (symbolP); | |
47926f60 KH |
968 | var_part_size = 0; |
969 | break; | |
970 | ||
971 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): | |
972 | /* We had a BDAP 8-bit "quick immediate", now turn it into a 16-bit | |
973 | one that uses PC autoincrement. */ | |
974 | opcodep[0] = BDAP_PC_LOW + (1 << 4); | |
975 | opcodep[1] &= 0xF0; | |
976 | opcodep[1] |= BDAP_INCR_HIGH; | |
1c971160 HPN |
977 | if (symbolP == NULL) |
978 | as_fatal (_("internal inconsistency in %s: bdap.w with no symbol"), | |
979 | __FUNCTION__); | |
980 | md_number_to_chars (var_partp, S_GET_VALUE (symbolP), 2); | |
47926f60 KH |
981 | var_part_size = 2; |
982 | break; | |
983 | ||
984 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): | |
985 | /* We had a BDAP 16-bit "word", change the offset to a dword. */ | |
986 | opcodep[0] = BDAP_PC_LOW + (2 << 4); | |
987 | opcodep[1] &= 0xF0; | |
988 | opcodep[1] |= BDAP_INCR_HIGH; | |
989 | if (fragP->fr_symbol == NULL) | |
990 | md_number_to_chars (var_partp, fragP->fr_offset, 4); | |
991 | else | |
992 | fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol, | |
993 | fragP->fr_offset, 0, BFD_RELOC_32); | |
994 | var_part_size = 4; | |
995 | break; | |
996 | ||
1048a9ba | 997 | case ENCODE_RELAX (STATE_MUL, STATE_BYTE): |
708587a4 | 998 | /* This is the only time we check position and alignment of the |
1048a9ba HPN |
999 | placement-tracking frag. */ |
1000 | if (sec->alignment_power < 2) | |
1001 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1002 | _("section alignment must be >= 4 bytes to check MULS/MULU safeness")); | |
1003 | else | |
1004 | { | |
1005 | /* If the address after the MULS/MULU has alignment which is | |
1006 | that of the section and may be that of a cache-size of the | |
1007 | buggy versions, then the MULS/MULU can be placed badly. */ | |
1008 | if ((address_of_var_part | |
1009 | & ((1 << sec->alignment_power) - 1) & 31) == 0) | |
1010 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1011 | _("dangerous MULS/MULU location; give it higher alignment")); | |
1012 | } | |
1013 | break; | |
1014 | ||
47926f60 KH |
1015 | default: |
1016 | BAD_CASE (fragP->fr_subtype); | |
1017 | break; | |
1018 | } | |
1019 | ||
1020 | fragP->fr_fix += var_part_size; | |
3bcbcc3d HPN |
1021 | } |
1022 | ||
1023 | /* Generate a short jump around a secondary jump table. | |
1024 | Used by md_create_long_jump. | |
1025 | ||
1026 | This used to be md_create_short_jump, but is now called from | |
ae57792d HPN |
1027 | md_create_long_jump instead, when sufficient, since the sizes of the |
1028 | jumps are the same for pre-v32. */ | |
3bcbcc3d HPN |
1029 | |
1030 | static void | |
695a4822 HPN |
1031 | cris_create_short_jump (char *storep, addressT from_addr, addressT to_addr, |
1032 | fragS *fragP ATTRIBUTE_UNUSED, | |
1033 | symbolS *to_symbol ATTRIBUTE_UNUSED) | |
3bcbcc3d HPN |
1034 | { |
1035 | long int distance; | |
1036 | ||
ae57792d HPN |
1037 | /* See md_create_long_jump about the comment on the "+ 2". */ |
1038 | long int max_minimal_minus_distance; | |
1039 | long int max_minimal_plus_distance; | |
1040 | int nop_opcode; | |
1041 | ||
1042 | if (cris_arch == arch_crisv32) | |
1043 | { | |
1044 | max_minimal_minus_distance = BRANCH_BB_V32 + 2; | |
1045 | max_minimal_plus_distance = BRANCH_BF_V32 + 2; | |
1046 | nop_opcode = NOP_OPCODE_V32; | |
1047 | } | |
1048 | else | |
1049 | { | |
1050 | max_minimal_minus_distance = BRANCH_BB + 2; | |
1051 | max_minimal_plus_distance = BRANCH_BF + 2; | |
1052 | nop_opcode = NOP_OPCODE; | |
1053 | } | |
1054 | ||
3bcbcc3d HPN |
1055 | distance = to_addr - from_addr; |
1056 | ||
ae57792d HPN |
1057 | if (max_minimal_minus_distance <= distance |
1058 | && distance <= max_minimal_plus_distance) | |
3bcbcc3d HPN |
1059 | { |
1060 | /* Create a "short" short jump: "BA distance - 2". */ | |
47926f60 | 1061 | storep[0] = branch_disp (distance - 2); |
3bcbcc3d HPN |
1062 | storep[1] = BA_QUICK_HIGH; |
1063 | ||
1064 | /* A nop for the delay slot. */ | |
ae57792d | 1065 | md_number_to_chars (storep + 2, nop_opcode, 2); |
3bcbcc3d HPN |
1066 | |
1067 | /* The extra word should be filled with something sane too. Make it | |
1068 | a nop to keep disassembly sane. */ | |
ae57792d | 1069 | md_number_to_chars (storep + 4, nop_opcode, 2); |
3bcbcc3d HPN |
1070 | } |
1071 | else | |
1072 | { | |
1073 | /* Make it a "long" short jump: "BA (PC+)". */ | |
1074 | md_number_to_chars (storep, BA_PC_INCR_OPCODE, 2); | |
1075 | ||
47926f60 | 1076 | /* ".WORD distance - 4". */ |
ae57792d HPN |
1077 | md_number_to_chars (storep + 2, |
1078 | (long) (distance - 4 | |
1079 | - (cris_arch == arch_crisv32 | |
1080 | ? -4 : 0)), | |
1081 | 2); | |
3bcbcc3d HPN |
1082 | |
1083 | /* A nop for the delay slot. */ | |
ae57792d | 1084 | md_number_to_chars (storep + 4, nop_opcode, 2); |
3bcbcc3d HPN |
1085 | } |
1086 | } | |
1087 | ||
3bcbcc3d HPN |
1088 | /* Generate a long jump in a secondary jump table. |
1089 | ||
1090 | storep Where to store the jump instruction. | |
1091 | from_addr Address of the jump instruction. | |
1092 | to_addr Destination address of the jump. | |
1093 | fragP Which frag the destination address operand | |
1094 | lies in. | |
1095 | to_symbol Destination symbol. */ | |
1096 | ||
1097 | void | |
695a4822 HPN |
1098 | md_create_long_jump (char *storep, addressT from_addr, addressT to_addr, |
1099 | fragS *fragP, symbolS *to_symbol) | |
3bcbcc3d HPN |
1100 | { |
1101 | long int distance; | |
1102 | ||
ae57792d HPN |
1103 | /* FIXME: What's that "+ 3"? It comes from the magic numbers that |
1104 | used to be here, it's just translated to the limit macros used in | |
1105 | the relax table. But why + 3? */ | |
1106 | long int max_short_minus_distance | |
1107 | = cris_arch != arch_crisv32 ? BRANCH_WB + 3 : BRANCH_WB_V32 + 3; | |
1108 | ||
1109 | long int max_short_plus_distance | |
1110 | = cris_arch != arch_crisv32 ? BRANCH_WF + 3 : BRANCH_WF_V32 + 3; | |
1111 | ||
1112 | /* Bail out for compatibility mode. (It seems it can be implemented, | |
1113 | perhaps with a 10-byte sequence: "move.d NNNN,$pc/$acr", "jump | |
1114 | $acr", "nop"; but doesn't seem worth it at the moment.) */ | |
1115 | if (cris_arch == arch_cris_common_v10_v32) | |
1116 | as_fatal (_("Out-of-range .word offset handling\ | |
1117 | is not implemented for .arch common_v10_v32")); | |
1118 | ||
3bcbcc3d HPN |
1119 | distance = to_addr - from_addr; |
1120 | ||
ae57792d HPN |
1121 | if (max_short_minus_distance <= distance |
1122 | && distance <= max_short_plus_distance) | |
1123 | /* Then make it a "short" long jump. */ | |
1124 | cris_create_short_jump (storep, from_addr, to_addr, fragP, | |
1125 | to_symbol); | |
3bcbcc3d HPN |
1126 | else |
1127 | { | |
ae57792d | 1128 | /* We have a "long" long jump: "JUMP [PC+]". If CRISv32, always |
d2aa3f9f | 1129 | make it a BA. Else make it an "MOVE [PC=PC+N],P0" if we're supposed |
ae57792d | 1130 | to emit PIC code. */ |
08caf3f8 | 1131 | md_number_to_chars (storep, |
ae57792d HPN |
1132 | cris_arch == arch_crisv32 |
1133 | ? BA_DWORD_OPCODE | |
d2aa3f9f HPN |
1134 | : (pic ? MOVE_PC_INCR_OPCODE_PREFIX |
1135 | : JUMP_PC_INCR_OPCODE), | |
ae57792d | 1136 | 2); |
3bcbcc3d | 1137 | |
08caf3f8 | 1138 | /* Follow with a ".DWORD to_addr", PC-relative for PIC. */ |
3bcbcc3d | 1139 | fix_new (fragP, storep + 2 - fragP->fr_literal, 4, to_symbol, |
ae57792d HPN |
1140 | cris_arch == arch_crisv32 ? 6 : 0, |
1141 | cris_arch == arch_crisv32 || pic ? 1 : 0, | |
1142 | cris_arch == arch_crisv32 || pic | |
1143 | ? BFD_RELOC_32_PCREL : BFD_RELOC_32); | |
1144 | ||
1145 | /* Follow it with a "NOP" for CRISv32. */ | |
1146 | if (cris_arch == arch_crisv32) | |
1147 | md_number_to_chars (storep + 6, NOP_OPCODE_V32, 2); | |
d2aa3f9f HPN |
1148 | else if (pic) |
1149 | /* ...and the rest of the move-opcode for pre-v32 PIC. */ | |
1150 | md_number_to_chars (storep + 6, MOVE_PC_INCR_OPCODE_SUFFIX, 2); | |
3bcbcc3d HPN |
1151 | } |
1152 | } | |
1153 | ||
ed67db7a HPN |
1154 | /* Allocate space for the first piece of an insn, and mark it as the |
1155 | start of the insn for debug-format use. */ | |
1156 | ||
1157 | static char * | |
695a4822 | 1158 | cris_insn_first_word_frag (void) |
ed67db7a HPN |
1159 | { |
1160 | char *insnp = frag_more (2); | |
1161 | ||
1162 | /* We need to mark the start of the insn by passing dwarf2_emit_insn | |
1163 | the offset from the current fragment position. This must be done | |
1164 | after the first fragment is created but before any other fragments | |
1165 | (fixed or varying) are created. Note that the offset only | |
1166 | corresponds to the "size" of the insn for a fixed-size, | |
1167 | non-expanded insn. */ | |
1168 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1169 | dwarf2_emit_insn (2); | |
1170 | ||
1171 | return insnp; | |
1172 | } | |
1173 | ||
3bcbcc3d | 1174 | /* Port-specific assembler initialization. */ |
47926f60 | 1175 | |
3bcbcc3d | 1176 | void |
695a4822 | 1177 | md_begin (void) |
3bcbcc3d HPN |
1178 | { |
1179 | const char *hashret = NULL; | |
1180 | int i = 0; | |
1181 | ||
47926f60 | 1182 | /* Set up a hash table for the instructions. */ |
3bcbcc3d HPN |
1183 | op_hash = hash_new (); |
1184 | if (op_hash == NULL) | |
1185 | as_fatal (_("Virtual memory exhausted")); | |
1186 | ||
ae57792d HPN |
1187 | /* Enable use of ".if ..asm.arch.cris.v32" |
1188 | and ".if ..asm.arch.cris.common_v10_v32" and a few others. */ | |
1189 | symbol_table_insert (symbol_new ("..asm.arch.cris.v32", absolute_section, | |
1190 | (cris_arch == arch_crisv32), | |
1191 | &zero_address_frag)); | |
1192 | symbol_table_insert (symbol_new ("..asm.arch.cris.v10", absolute_section, | |
1193 | (cris_arch == arch_crisv10), | |
1194 | &zero_address_frag)); | |
1195 | symbol_table_insert (symbol_new ("..asm.arch.cris.common_v10_v32", | |
1196 | absolute_section, | |
1197 | (cris_arch == arch_cris_common_v10_v32), | |
1198 | &zero_address_frag)); | |
1199 | symbol_table_insert (symbol_new ("..asm.arch.cris.any_v0_v10", | |
1200 | absolute_section, | |
1201 | (cris_arch == arch_cris_any_v0_v10), | |
1202 | &zero_address_frag)); | |
1203 | ||
3bcbcc3d HPN |
1204 | while (cris_opcodes[i].name != NULL) |
1205 | { | |
1206 | const char *name = cris_opcodes[i].name; | |
ae57792d HPN |
1207 | |
1208 | if (! cris_insn_ver_valid_for_arch (cris_opcodes[i].applicable_version, | |
1209 | cris_arch)) | |
1210 | { | |
1211 | i++; | |
1212 | continue; | |
1213 | } | |
1214 | ||
695a4822 HPN |
1215 | /* Need to cast to get rid of "const". FIXME: Fix hash_insert instead. */ |
1216 | hashret = hash_insert (op_hash, name, (void *) &cris_opcodes[i]); | |
3bcbcc3d HPN |
1217 | |
1218 | if (hashret != NULL && *hashret != '\0') | |
1219 | as_fatal (_("Can't hash `%s': %s\n"), cris_opcodes[i].name, | |
47926f60 | 1220 | *hashret == 0 ? _("(unknown reason)") : hashret); |
3bcbcc3d HPN |
1221 | do |
1222 | { | |
1223 | if (cris_opcodes[i].match & cris_opcodes[i].lose) | |
1224 | as_fatal (_("Buggy opcode: `%s' \"%s\"\n"), cris_opcodes[i].name, | |
1225 | cris_opcodes[i].args); | |
1226 | ||
1227 | ++i; | |
47926f60 KH |
1228 | } |
1229 | while (cris_opcodes[i].name != NULL | |
1230 | && strcmp (cris_opcodes[i].name, name) == 0); | |
3bcbcc3d HPN |
1231 | } |
1232 | } | |
1233 | ||
3bcbcc3d | 1234 | /* Assemble a source line. */ |
47926f60 | 1235 | |
3bcbcc3d | 1236 | void |
695a4822 | 1237 | md_assemble (char *str) |
3bcbcc3d HPN |
1238 | { |
1239 | struct cris_instruction output_instruction; | |
1240 | struct cris_prefix prefix; | |
1241 | char *opcodep; | |
1242 | char *p; | |
1243 | ||
1244 | know (str); | |
1245 | ||
1246 | /* Do the low-level grunt - assemble to bits and split up into a prefix | |
1247 | and ordinary insn. */ | |
1248 | cris_process_instruction (str, &output_instruction, &prefix); | |
1249 | ||
1250 | /* Handle any prefixes to the instruction. */ | |
1251 | switch (prefix.kind) | |
1252 | { | |
1253 | case PREFIX_NONE: | |
1254 | break; | |
1255 | ||
1256 | /* When the expression is unknown for a BDAP, it can need 0, 2 or 4 | |
1257 | extra bytes, so we handle it separately. */ | |
1258 | case PREFIX_BDAP_IMM: | |
cc99daad | 1259 | /* We only do it if the relocation is unspecified, i.e. not a PIC or TLS |
08caf3f8 HPN |
1260 | relocation. */ |
1261 | if (prefix.reloc == BFD_RELOC_NONE) | |
1262 | { | |
1263 | gen_bdap (prefix.base_reg_number, &prefix.expr); | |
1264 | break; | |
1265 | } | |
1266 | /* Fall through. */ | |
3bcbcc3d HPN |
1267 | case PREFIX_BDAP: |
1268 | case PREFIX_BIAP: | |
1269 | case PREFIX_DIP: | |
ed67db7a | 1270 | opcodep = cris_insn_first_word_frag (); |
3bcbcc3d HPN |
1271 | |
1272 | /* Output the prefix opcode. */ | |
1273 | md_number_to_chars (opcodep, (long) prefix.opcode, 2); | |
1274 | ||
08caf3f8 | 1275 | /* Having a specified reloc only happens for DIP and for BDAP with |
cc99daad | 1276 | PIC or TLS operands, but it is ok to drop through here for the other |
08caf3f8 | 1277 | prefixes as they can have no relocs specified. */ |
3bcbcc3d HPN |
1278 | if (prefix.reloc != BFD_RELOC_NONE) |
1279 | { | |
08caf3f8 HPN |
1280 | unsigned int relocsize |
1281 | = (prefix.kind == PREFIX_DIP | |
cc99daad | 1282 | ? 4 : cris_get_specified_reloc_size (prefix.reloc)); |
08caf3f8 | 1283 | |
08caf3f8 HPN |
1284 | p = frag_more (relocsize); |
1285 | fix_new_exp (frag_now, (p - frag_now->fr_literal), relocsize, | |
3bcbcc3d HPN |
1286 | &prefix.expr, 0, prefix.reloc); |
1287 | } | |
1288 | break; | |
1289 | ||
1290 | case PREFIX_PUSH: | |
ed67db7a | 1291 | opcodep = cris_insn_first_word_frag (); |
3bcbcc3d HPN |
1292 | |
1293 | /* Output the prefix opcode. Being a "push", we add the negative | |
1294 | size of the register to "sp". */ | |
1295 | if (output_instruction.spec_reg != NULL) | |
1296 | { | |
47926f60 | 1297 | /* Special register. */ |
3bcbcc3d HPN |
1298 | opcodep[0] = -output_instruction.spec_reg->reg_size; |
1299 | } | |
1300 | else | |
1301 | { | |
47926f60 | 1302 | /* General register. */ |
3bcbcc3d HPN |
1303 | opcodep[0] = -4; |
1304 | } | |
1305 | opcodep[1] = (REG_SP << 4) + (BDAP_QUICK_OPCODE >> 8); | |
1306 | break; | |
1307 | ||
1308 | default: | |
1309 | BAD_CASE (prefix.kind); | |
1310 | } | |
1311 | ||
1312 | /* If we only had a prefix insn, we're done. */ | |
1313 | if (output_instruction.insn_type == CRIS_INSN_NONE) | |
1314 | return; | |
1315 | ||
1316 | /* Done with the prefix. Continue with the main instruction. */ | |
ed67db7a HPN |
1317 | if (prefix.kind == PREFIX_NONE) |
1318 | opcodep = cris_insn_first_word_frag (); | |
1319 | else | |
1320 | opcodep = frag_more (2); | |
3bcbcc3d HPN |
1321 | |
1322 | /* Output the instruction opcode. */ | |
47926f60 | 1323 | md_number_to_chars (opcodep, (long) (output_instruction.opcode), 2); |
3bcbcc3d HPN |
1324 | |
1325 | /* Output the symbol-dependent instruction stuff. */ | |
1326 | if (output_instruction.insn_type == CRIS_INSN_BRANCH) | |
1327 | { | |
1328 | segT to_seg = absolute_section; | |
1329 | int is_undefined = 0; | |
1330 | int length_code; | |
1331 | ||
1332 | if (output_instruction.expr.X_op != O_constant) | |
1333 | { | |
1334 | to_seg = S_GET_SEGMENT (output_instruction.expr.X_add_symbol); | |
1335 | ||
1336 | if (to_seg == undefined_section) | |
1337 | is_undefined = 1; | |
1338 | } | |
1339 | ||
ae57792d HPN |
1340 | if (to_seg == now_seg || is_undefined |
1341 | /* In CRISv32, there *is* a 32-bit absolute branch, so don't | |
1342 | emit the 12-byte sequence for known symbols in other | |
1343 | segments. */ | |
1344 | || (cris_arch == arch_crisv32 | |
1345 | && output_instruction.opcode == BA_QUICK_OPCODE)) | |
3bcbcc3d | 1346 | { |
08caf3f8 HPN |
1347 | /* Handle complex expressions. */ |
1348 | valueT addvalue | |
1c971160 HPN |
1349 | = (SIMPLE_EXPR (&output_instruction.expr) |
1350 | ? output_instruction.expr.X_add_number | |
1351 | : 0); | |
08caf3f8 | 1352 | symbolS *sym |
1c971160 HPN |
1353 | = (SIMPLE_EXPR (&output_instruction.expr) |
1354 | ? output_instruction.expr.X_add_symbol | |
1355 | : make_expr_symbol (&output_instruction.expr)); | |
08caf3f8 | 1356 | |
ae57792d HPN |
1357 | /* If is_undefined, the expression may still become now_seg. |
1358 | That case is handled by md_estimate_size_before_relax. */ | |
1359 | length_code = to_seg == now_seg ? STATE_BYTE : STATE_UNDF; | |
1360 | ||
d2aa3f9f HPN |
1361 | /* Make room for max twelve bytes of variable length for v32 mode |
1362 | or PIC, ten for v10 and older. */ | |
ae57792d HPN |
1363 | frag_var (rs_machine_dependent, |
1364 | (cris_arch == arch_crisv32 | |
d2aa3f9f HPN |
1365 | || cris_arch == arch_cris_common_v10_v32 |
1366 | || pic) ? 12 : 10, 0, | |
ae57792d HPN |
1367 | ENCODE_RELAX (cris_arch == arch_crisv32 |
1368 | ? (output_instruction.opcode | |
1369 | == BA_QUICK_OPCODE | |
1370 | ? STATE_ABS_BRANCH_V32 | |
1371 | : STATE_COND_BRANCH_V32) | |
1372 | : (cris_arch == arch_cris_common_v10_v32 | |
1373 | ? STATE_COND_BRANCH_COMMON | |
d2aa3f9f HPN |
1374 | : (pic ? STATE_COND_BRANCH_PIC |
1375 | : STATE_COND_BRANCH)), | |
ae57792d | 1376 | length_code), |
08caf3f8 | 1377 | sym, addvalue, opcodep); |
3bcbcc3d HPN |
1378 | } |
1379 | else | |
1380 | { | |
1381 | /* We have: to_seg != now_seg && to_seg != undefined_section. | |
1382 | This means it is a branch to a known symbol in another | |
fb2fd3e1 | 1383 | section, perhaps an absolute address. Emit a 32-bit branch. */ |
ae57792d HPN |
1384 | char *cond_jump |
1385 | = frag_more ((cris_arch == arch_crisv32 | |
d2aa3f9f HPN |
1386 | || cris_arch == arch_cris_common_v10_v32 |
1387 | || pic) | |
ae57792d | 1388 | ? 12 : 10); |
08caf3f8 | 1389 | |
08caf3f8 | 1390 | gen_cond_branch_32 (opcodep, cond_jump, frag_now, |
3bcbcc3d | 1391 | output_instruction.expr.X_add_symbol, |
47926f60 | 1392 | (symbolS *) NULL, |
3bcbcc3d HPN |
1393 | output_instruction.expr.X_add_number); |
1394 | } | |
1395 | } | |
1048a9ba HPN |
1396 | else if (output_instruction.insn_type == CRIS_INSN_MUL |
1397 | && err_for_dangerous_mul_placement) | |
1398 | /* Create a frag which which we track the location of the mul insn | |
1399 | (in the last two bytes before the mul-frag). */ | |
1400 | frag_variant (rs_machine_dependent, 0, 0, | |
1401 | ENCODE_RELAX (STATE_MUL, STATE_BYTE), | |
1402 | NULL, 0, opcodep); | |
3bcbcc3d HPN |
1403 | else |
1404 | { | |
1405 | if (output_instruction.imm_oprnd_size > 0) | |
1406 | { | |
2d2255b5 | 1407 | /* The instruction has an immediate operand. */ |
08caf3f8 | 1408 | enum bfd_reloc_code_real reloc = BFD_RELOC_NONE; |
3bcbcc3d HPN |
1409 | |
1410 | switch (output_instruction.imm_oprnd_size) | |
1411 | { | |
1412 | /* Any byte-size immediate constants are treated as | |
1413 | word-size. FIXME: Thus overflow check does not work | |
1414 | correctly. */ | |
1415 | ||
1416 | case 2: | |
08caf3f8 HPN |
1417 | /* Note that size-check for the explicit reloc has already |
1418 | been done when we get here. */ | |
1419 | if (output_instruction.reloc != BFD_RELOC_NONE) | |
1420 | reloc = output_instruction.reloc; | |
1421 | else | |
1422 | reloc = BFD_RELOC_16; | |
3bcbcc3d HPN |
1423 | break; |
1424 | ||
1425 | case 4: | |
08caf3f8 HPN |
1426 | /* Allow a relocation specified in the operand. */ |
1427 | if (output_instruction.reloc != BFD_RELOC_NONE) | |
1428 | reloc = output_instruction.reloc; | |
1429 | else | |
1430 | reloc = BFD_RELOC_32; | |
3bcbcc3d HPN |
1431 | break; |
1432 | ||
1433 | default: | |
1434 | BAD_CASE (output_instruction.imm_oprnd_size); | |
1435 | } | |
1436 | ||
1437 | p = frag_more (output_instruction.imm_oprnd_size); | |
1438 | fix_new_exp (frag_now, (p - frag_now->fr_literal), | |
1439 | output_instruction.imm_oprnd_size, | |
ae57792d HPN |
1440 | &output_instruction.expr, |
1441 | reloc == BFD_RELOC_32_PCREL | |
1442 | || reloc == BFD_RELOC_16_PCREL | |
1443 | || reloc == BFD_RELOC_8_PCREL, reloc); | |
1444 | } | |
1445 | else if (output_instruction.reloc == BFD_RELOC_CRIS_LAPCQ_OFFSET | |
1446 | && output_instruction.expr.X_md != 0) | |
1447 | { | |
1448 | /* Handle complex expressions. */ | |
1449 | valueT addvalue | |
1450 | = (output_instruction.expr.X_op_symbol != NULL | |
1451 | ? 0 : output_instruction.expr.X_add_number); | |
1452 | symbolS *sym | |
1453 | = (output_instruction.expr.X_op_symbol != NULL | |
1454 | ? make_expr_symbol (&output_instruction.expr) | |
1455 | : output_instruction.expr.X_add_symbol); | |
1456 | ||
1457 | /* This is a relaxing construct, so we need a frag_var rather | |
1458 | than the fix_new_exp call below. */ | |
1459 | frag_var (rs_machine_dependent, | |
1460 | 4, 0, | |
1461 | ENCODE_RELAX (STATE_LAPC, STATE_UNDF), | |
1462 | sym, addvalue, opcodep); | |
3bcbcc3d HPN |
1463 | } |
1464 | else if (output_instruction.reloc != BFD_RELOC_NONE) | |
1465 | { | |
1466 | /* An immediate operand that has a relocation and needs to be | |
47926f60 | 1467 | processed further. */ |
3bcbcc3d HPN |
1468 | |
1469 | /* It is important to use fix_new_exp here and everywhere else | |
1470 | (and not fix_new), as fix_new_exp can handle "difference | |
1471 | expressions" - where the expression contains a difference of | |
1472 | two symbols in the same segment. */ | |
1473 | fix_new_exp (frag_now, (opcodep - frag_now->fr_literal), 2, | |
ae57792d HPN |
1474 | &output_instruction.expr, |
1475 | output_instruction.reloc == BFD_RELOC_32_PCREL | |
1476 | || output_instruction.reloc == BFD_RELOC_16_PCREL | |
1477 | || output_instruction.reloc == BFD_RELOC_8_PCREL | |
1478 | || (output_instruction.reloc | |
1479 | == BFD_RELOC_CRIS_LAPCQ_OFFSET), | |
3bcbcc3d HPN |
1480 | output_instruction.reloc); |
1481 | } | |
1482 | } | |
1483 | } | |
1484 | ||
3bcbcc3d | 1485 | /* Low level text-to-bits assembly. */ |
47926f60 | 1486 | |
3bcbcc3d | 1487 | static void |
695a4822 HPN |
1488 | cris_process_instruction (char *insn_text, struct cris_instruction *out_insnp, |
1489 | struct cris_prefix *prefixp) | |
3bcbcc3d | 1490 | { |
47926f60 KH |
1491 | char *s; |
1492 | char modified_char = 0; | |
1493 | const char *args; | |
3bcbcc3d | 1494 | struct cris_opcode *instruction; |
47926f60 KH |
1495 | char *operands; |
1496 | int match = 0; | |
1497 | int mode; | |
1498 | int regno; | |
1499 | int size_bits; | |
3bcbcc3d HPN |
1500 | |
1501 | /* Reset these fields to a harmless state in case we need to return in | |
1502 | error. */ | |
1503 | prefixp->kind = PREFIX_NONE; | |
1504 | prefixp->reloc = BFD_RELOC_NONE; | |
ae57792d | 1505 | out_insnp->insn_type = CRIS_INSN_NONE; |
3bcbcc3d HPN |
1506 | out_insnp->imm_oprnd_size = 0; |
1507 | ||
1508 | /* Find the end of the opcode mnemonic. We assume (true in 2.9.1) | |
1509 | that the caller has translated the opcode to lower-case, up to the | |
47926f60 | 1510 | first non-letter. */ |
3882b010 | 1511 | for (operands = insn_text; ISLOWER (*operands); ++operands) |
3bcbcc3d HPN |
1512 | ; |
1513 | ||
1514 | /* Terminate the opcode after letters, but save the character there if | |
1515 | it was of significance. */ | |
1516 | switch (*operands) | |
1517 | { | |
1518 | case '\0': | |
1519 | break; | |
1520 | ||
1521 | case '.': | |
47926f60 | 1522 | /* Put back the modified character later. */ |
3bcbcc3d | 1523 | modified_char = *operands; |
47926f60 | 1524 | /* Fall through. */ |
3bcbcc3d HPN |
1525 | |
1526 | case ' ': | |
47926f60 KH |
1527 | /* Consume the character after the mnemonic |
1528 | and replace it with '\0'. */ | |
3bcbcc3d HPN |
1529 | *operands++ = '\0'; |
1530 | break; | |
1531 | ||
1532 | default: | |
1533 | as_bad (_("Unknown opcode: `%s'"), insn_text); | |
1534 | return; | |
1535 | } | |
1536 | ||
1537 | /* Find the instruction. */ | |
1538 | instruction = (struct cris_opcode *) hash_find (op_hash, insn_text); | |
1539 | if (instruction == NULL) | |
1540 | { | |
1541 | as_bad (_("Unknown opcode: `%s'"), insn_text); | |
1542 | return; | |
1543 | } | |
1544 | ||
1545 | /* Put back the modified character. */ | |
1546 | switch (modified_char) | |
1547 | { | |
1548 | case 0: | |
1549 | break; | |
1550 | ||
1551 | default: | |
1552 | *--operands = modified_char; | |
1553 | } | |
1554 | ||
3bcbcc3d | 1555 | /* Try to match an opcode table slot. */ |
47926f60 | 1556 | for (s = operands;;) |
3bcbcc3d | 1557 | { |
47926f60 | 1558 | int imm_expr_found; |
3bcbcc3d HPN |
1559 | |
1560 | /* Initialize *prefixp, perhaps after being modified for a | |
47926f60 | 1561 | "near match". */ |
3bcbcc3d HPN |
1562 | prefixp->kind = PREFIX_NONE; |
1563 | prefixp->reloc = BFD_RELOC_NONE; | |
1564 | ||
1565 | /* Initialize *out_insnp. */ | |
1566 | memset (out_insnp, 0, sizeof (*out_insnp)); | |
1567 | out_insnp->opcode = instruction->match; | |
1568 | out_insnp->reloc = BFD_RELOC_NONE; | |
1569 | out_insnp->insn_type = CRIS_INSN_NORMAL; | |
1570 | out_insnp->imm_oprnd_size = 0; | |
1571 | ||
1572 | imm_expr_found = 0; | |
1573 | ||
1574 | /* Build the opcode, checking as we go to make sure that the | |
1575 | operands match. */ | |
47926f60 | 1576 | for (args = instruction->args;; ++args) |
3bcbcc3d HPN |
1577 | { |
1578 | switch (*args) | |
1579 | { | |
1580 | case '\0': | |
1581 | /* If we've come to the end of arguments, we're done. */ | |
1582 | if (*s == '\0') | |
1583 | match = 1; | |
1584 | break; | |
1585 | ||
1586 | case '!': | |
1587 | /* Non-matcher character for disassembly. | |
1588 | Ignore it here. */ | |
1589 | continue; | |
1590 | ||
ae57792d HPN |
1591 | case '[': |
1592 | case ']': | |
3bcbcc3d HPN |
1593 | case ',': |
1594 | case ' ': | |
1595 | /* These must match exactly. */ | |
1596 | if (*s++ == *args) | |
1597 | continue; | |
1598 | break; | |
1599 | ||
ae57792d HPN |
1600 | case 'A': |
1601 | /* "ACR", case-insensitive. | |
1602 | Handle a sometimes-mandatory dollar sign as register | |
1603 | prefix. */ | |
1604 | if (*s == REGISTER_PREFIX_CHAR) | |
1605 | s++; | |
1606 | else if (demand_register_prefix) | |
1607 | break; | |
1608 | ||
1609 | if ((*s++ != 'a' && s[-1] != 'A') | |
1610 | || (*s++ != 'c' && s[-1] != 'C') | |
1611 | || (*s++ != 'r' && s[-1] != 'R')) | |
1612 | break; | |
1613 | continue; | |
1614 | ||
3bcbcc3d HPN |
1615 | case 'B': |
1616 | /* This is not really an operand, but causes a "BDAP | |
47926f60 | 1617 | -size,SP" prefix to be output, for PUSH instructions. */ |
3bcbcc3d HPN |
1618 | prefixp->kind = PREFIX_PUSH; |
1619 | continue; | |
1620 | ||
1621 | case 'b': | |
1622 | /* This letter marks an operand that should not be matched | |
1623 | in the assembler. It is a branch with 16-bit | |
1624 | displacement. The assembler will create them from the | |
1625 | 8-bit flavor when necessary. The assembler does not | |
1626 | support the [rN+] operand, as the [r15+] that is | |
1627 | generated for 16-bit displacements. */ | |
1628 | break; | |
1629 | ||
1630 | case 'c': | |
1631 | /* A 5-bit unsigned immediate in bits <4:0>. */ | |
1632 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1633 | break; | |
1634 | else | |
1635 | { | |
1636 | if (out_insnp->expr.X_op == O_constant | |
1637 | && (out_insnp->expr.X_add_number < 0 | |
1638 | || out_insnp->expr.X_add_number > 31)) | |
1639 | as_bad (_("Immediate value not in 5 bit unsigned range: %ld"), | |
1640 | out_insnp->expr.X_add_number); | |
1641 | ||
1642 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_5; | |
1643 | continue; | |
1644 | } | |
1645 | ||
1646 | case 'C': | |
1647 | /* A 4-bit unsigned immediate in bits <3:0>. */ | |
1648 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1649 | break; | |
1650 | else | |
1651 | { | |
1652 | if (out_insnp->expr.X_op == O_constant | |
1653 | && (out_insnp->expr.X_add_number < 0 | |
1654 | || out_insnp->expr.X_add_number > 15)) | |
1655 | as_bad (_("Immediate value not in 4 bit unsigned range: %ld"), | |
1656 | out_insnp->expr.X_add_number); | |
1657 | ||
1658 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_4; | |
1659 | continue; | |
1660 | } | |
1661 | ||
ae57792d HPN |
1662 | /* For 'd', check for an optional ".d" or ".D" at the |
1663 | start of the operands, followed by a space character. */ | |
1664 | case 'd': | |
1665 | if (modified_char == '.' && *s == '.') | |
1666 | { | |
1667 | if ((s[1] != 'd' && s[1] == 'D') | |
1668 | || ! ISSPACE (s[2])) | |
1669 | break; | |
1670 | s += 2; | |
1671 | continue; | |
1672 | } | |
1673 | continue; | |
1674 | ||
3bcbcc3d HPN |
1675 | case 'D': |
1676 | /* General register in bits <15:12> and <3:0>. */ | |
1677 | if (! get_gen_reg (&s, ®no)) | |
1678 | break; | |
1679 | else | |
1680 | { | |
1681 | out_insnp->opcode |= regno /* << 0 */; | |
1682 | out_insnp->opcode |= regno << 12; | |
1683 | continue; | |
1684 | } | |
1685 | ||
1686 | case 'f': | |
1687 | /* Flags from the condition code register. */ | |
1688 | { | |
1689 | int flags = 0; | |
1690 | ||
1691 | if (! get_flags (&s, &flags)) | |
1692 | break; | |
1693 | ||
47926f60 | 1694 | out_insnp->opcode |= ((flags & 0xf0) << 8) | (flags & 0xf); |
3bcbcc3d HPN |
1695 | continue; |
1696 | } | |
1697 | ||
1698 | case 'i': | |
1699 | /* A 6-bit signed immediate in bits <5:0>. */ | |
1700 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1701 | break; | |
1702 | else | |
1703 | { | |
1704 | if (out_insnp->expr.X_op == O_constant | |
1705 | && (out_insnp->expr.X_add_number < -32 | |
1706 | || out_insnp->expr.X_add_number > 31)) | |
1707 | as_bad (_("Immediate value not in 6 bit range: %ld"), | |
1708 | out_insnp->expr.X_add_number); | |
1709 | out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_6; | |
1710 | continue; | |
1711 | } | |
1712 | ||
1713 | case 'I': | |
1714 | /* A 6-bit unsigned immediate in bits <5:0>. */ | |
1715 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1716 | break; | |
1717 | else | |
1718 | { | |
1719 | if (out_insnp->expr.X_op == O_constant | |
1720 | && (out_insnp->expr.X_add_number < 0 | |
1721 | || out_insnp->expr.X_add_number > 63)) | |
1722 | as_bad (_("Immediate value not in 6 bit unsigned range: %ld"), | |
1723 | out_insnp->expr.X_add_number); | |
1724 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_6; | |
1725 | continue; | |
1726 | } | |
1727 | ||
1728 | case 'M': | |
1729 | /* A size modifier, B, W or D, to be put in a bit position | |
1730 | suitable for CLEAR instructions (i.e. reflecting a zero | |
1731 | register). */ | |
1732 | if (! get_bwd_size_modifier (&s, &size_bits)) | |
1733 | break; | |
1734 | else | |
1735 | { | |
1736 | switch (size_bits) | |
1737 | { | |
1738 | case 0: | |
1739 | out_insnp->opcode |= 0 << 12; | |
1740 | break; | |
1741 | ||
1742 | case 1: | |
1743 | out_insnp->opcode |= 4 << 12; | |
1744 | break; | |
1745 | ||
1746 | case 2: | |
1747 | out_insnp->opcode |= 8 << 12; | |
1748 | break; | |
1749 | } | |
1750 | continue; | |
1751 | } | |
1752 | ||
1753 | case 'm': | |
1754 | /* A size modifier, B, W or D, to be put in bits <5:4>. */ | |
ae57792d HPN |
1755 | if (modified_char != '.' |
1756 | || ! get_bwd_size_modifier (&s, &size_bits)) | |
3bcbcc3d HPN |
1757 | break; |
1758 | else | |
1759 | { | |
1760 | out_insnp->opcode |= size_bits << 4; | |
1761 | continue; | |
1762 | } | |
1763 | ||
1764 | case 'o': | |
1765 | /* A branch expression. */ | |
1766 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1767 | break; | |
1768 | else | |
1769 | { | |
1770 | out_insnp->insn_type = CRIS_INSN_BRANCH; | |
1771 | continue; | |
1772 | } | |
1773 | ||
ae57792d HPN |
1774 | case 'Q': |
1775 | /* A 8-bit quick BDAP expression, "expr,R". */ | |
1776 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1777 | break; | |
1778 | ||
1779 | if (*s != ',') | |
1780 | break; | |
1781 | ||
1782 | s++; | |
1783 | ||
1784 | if (!get_gen_reg (&s, ®no)) | |
1785 | break; | |
1786 | ||
1787 | out_insnp->opcode |= regno << 12; | |
1788 | out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_8; | |
1789 | continue; | |
1790 | ||
3bcbcc3d | 1791 | case 'O': |
ae57792d | 1792 | /* A BDAP expression for any size, "expr,R". */ |
3bcbcc3d HPN |
1793 | if (! cris_get_expression (&s, &prefixp->expr)) |
1794 | break; | |
1795 | else | |
1796 | { | |
1797 | if (*s != ',') | |
1798 | break; | |
1799 | ||
1800 | s++; | |
1801 | ||
1802 | if (!get_gen_reg (&s, &prefixp->base_reg_number)) | |
1803 | break; | |
1804 | ||
1805 | /* Since 'O' is used with an explicit bdap, we have no | |
47926f60 | 1806 | "real" instruction. */ |
3bcbcc3d | 1807 | prefixp->kind = PREFIX_BDAP_IMM; |
08caf3f8 HPN |
1808 | prefixp->opcode |
1809 | = BDAP_QUICK_OPCODE | (prefixp->base_reg_number << 12); | |
1810 | ||
3bcbcc3d HPN |
1811 | out_insnp->insn_type = CRIS_INSN_NONE; |
1812 | continue; | |
1813 | } | |
1814 | ||
1815 | case 'P': | |
1816 | /* Special register in bits <15:12>. */ | |
1817 | if (! get_spec_reg (&s, &out_insnp->spec_reg)) | |
1818 | break; | |
1819 | else | |
1820 | { | |
1821 | /* Use of some special register names come with a | |
1822 | specific warning. Note that we have no ".cpu type" | |
1823 | pseudo yet, so some of this is just unused | |
1824 | framework. */ | |
1825 | if (out_insnp->spec_reg->warning) | |
1826 | as_warn (out_insnp->spec_reg->warning); | |
1827 | else if (out_insnp->spec_reg->applicable_version | |
1828 | == cris_ver_warning) | |
1829 | /* Others have a generic warning. */ | |
1830 | as_warn (_("Unimplemented register `%s' specified"), | |
1831 | out_insnp->spec_reg->name); | |
1832 | ||
1833 | out_insnp->opcode | |
1834 | |= out_insnp->spec_reg->number << 12; | |
1835 | continue; | |
1836 | } | |
1837 | ||
1838 | case 'p': | |
1839 | /* This character is used in the disassembler to | |
1840 | recognize a prefix instruction to fold into the | |
1841 | addressing mode for the next instruction. It is | |
47926f60 | 1842 | ignored here. */ |
3bcbcc3d HPN |
1843 | continue; |
1844 | ||
1845 | case 'R': | |
1846 | /* General register in bits <15:12>. */ | |
1847 | if (! get_gen_reg (&s, ®no)) | |
1848 | break; | |
1849 | else | |
1850 | { | |
1851 | out_insnp->opcode |= regno << 12; | |
1852 | continue; | |
1853 | } | |
1854 | ||
1855 | case 'r': | |
1856 | /* General register in bits <3:0>. */ | |
1857 | if (! get_gen_reg (&s, ®no)) | |
1858 | break; | |
1859 | else | |
1860 | { | |
1861 | out_insnp->opcode |= regno /* << 0 */; | |
1862 | continue; | |
1863 | } | |
1864 | ||
1865 | case 'S': | |
1866 | /* Source operand in bit <10> and a prefix; a 3-operand | |
1867 | prefix. */ | |
1868 | if (! get_3op_or_dip_prefix_op (&s, prefixp)) | |
1869 | break; | |
1870 | else | |
1871 | continue; | |
1872 | ||
1873 | case 's': | |
1874 | /* Source operand in bits <10>, <3:0> and optionally a | |
1875 | prefix; i.e. an indirect operand or an side-effect | |
ae57792d | 1876 | prefix (where valid). */ |
3bcbcc3d HPN |
1877 | if (! get_autoinc_prefix_or_indir_op (&s, prefixp, &mode, |
1878 | ®no, | |
1879 | &imm_expr_found, | |
1880 | &out_insnp->expr)) | |
1881 | break; | |
1882 | else | |
1883 | { | |
1884 | if (prefixp->kind != PREFIX_NONE) | |
1885 | { | |
1886 | /* A prefix, so it has the autoincrement bit | |
1887 | set. */ | |
1888 | out_insnp->opcode |= (AUTOINCR_BIT << 8); | |
1889 | } | |
1890 | else | |
08caf3f8 HPN |
1891 | { |
1892 | /* No prefix. The "mode" variable contains bits like | |
1893 | whether or not this is autoincrement mode. */ | |
1894 | out_insnp->opcode |= (mode << 10); | |
1895 | ||
cc99daad | 1896 | /* If there was a reloc specifier, then it was |
08caf3f8 HPN |
1897 | attached to the prefix. Note that we can't check |
1898 | that the reloc size matches, since we don't have | |
1899 | all the operands yet in all cases. */ | |
1900 | if (prefixp->reloc != BFD_RELOC_NONE) | |
1901 | out_insnp->reloc = prefixp->reloc; | |
1902 | } | |
3bcbcc3d HPN |
1903 | |
1904 | out_insnp->opcode |= regno /* << 0 */ ; | |
1905 | continue; | |
1906 | } | |
1907 | ||
ae57792d HPN |
1908 | case 'N': |
1909 | case 'Y': | |
cc99daad HPN |
1910 | /* Like 's', but immediate operand only. Also do not |
1911 | modify insn. There are no insns where an explicit reloc | |
ae57792d HPN |
1912 | specifier makes sense. */ |
1913 | if (cris_get_expression (&s, &out_insnp->expr)) | |
1914 | { | |
1915 | imm_expr_found = 1; | |
1916 | continue; | |
1917 | } | |
1918 | break; | |
1919 | ||
1920 | case 'n': | |
1921 | /* Like 'N', but PC-relative to the start of the insn. | |
1922 | There might be a :PLT to request a PLT entry. */ | |
1923 | if (cris_get_expression (&s, &out_insnp->expr)) | |
1924 | { | |
1925 | imm_expr_found = 1; | |
1926 | out_insnp->reloc = BFD_RELOC_32_PCREL; | |
1927 | ||
1928 | /* We have to adjust the expression, because that | |
1929 | relocation is to the location *after* the | |
1930 | relocation. So add 2 for the insn and 4 for the | |
1931 | relocation. */ | |
1932 | out_insnp->expr.X_add_number += 6; | |
1933 | ||
cc99daad HPN |
1934 | /* TLS specifiers do not make sense here. */ |
1935 | if (pic && *s == RELOC_SUFFIX_CHAR) | |
1936 | cris_get_reloc_suffix (&s, &out_insnp->reloc, | |
1937 | &out_insnp->expr); | |
ae57792d HPN |
1938 | |
1939 | continue; | |
1940 | } | |
1941 | break; | |
1942 | ||
1943 | case 'U': | |
1944 | /* Maybe 'u', maybe 'n'. Only for LAPC/LAPCQ. */ | |
1945 | if (cris_get_expression (&s, &out_insnp->expr)) | |
1946 | { | |
1947 | out_insnp->reloc = BFD_RELOC_CRIS_LAPCQ_OFFSET; | |
1948 | ||
1949 | /* Define 1 as relaxing. */ | |
1950 | out_insnp->expr.X_md = 1; | |
1951 | continue; | |
1952 | } | |
1953 | break; | |
1954 | ||
1955 | case 'u': | |
1956 | /* Four PC-relative bits in <3:0> representing <4:1>:0 of | |
1957 | an offset relative to the beginning of the current | |
1958 | insn. */ | |
1959 | if (cris_get_expression (&s, &out_insnp->expr)) | |
1960 | { | |
1961 | out_insnp->reloc = BFD_RELOC_CRIS_LAPCQ_OFFSET; | |
1962 | ||
1963 | /* Define 0 as non-relaxing. */ | |
1964 | out_insnp->expr.X_md = 0; | |
1965 | ||
1966 | /* We have to adjust the expression, because that | |
1967 | relocation is to the location *after* the | |
1968 | insn. So add 2 for the insn. */ | |
1969 | out_insnp->expr.X_add_number += 2; | |
1970 | continue; | |
1971 | } | |
1972 | break; | |
1973 | ||
3bcbcc3d HPN |
1974 | case 'x': |
1975 | /* Rs.m in bits <15:12> and <5:4>. */ | |
1976 | if (! get_gen_reg (&s, ®no) | |
1977 | || ! get_bwd_size_modifier (&s, &size_bits)) | |
1978 | break; | |
1979 | else | |
1980 | { | |
47926f60 | 1981 | out_insnp->opcode |= (regno << 12) | (size_bits << 4); |
3bcbcc3d HPN |
1982 | continue; |
1983 | } | |
1984 | ||
1985 | case 'y': | |
1986 | /* Source operand in bits <10>, <3:0> and optionally a | |
1987 | prefix; i.e. an indirect operand or an side-effect | |
1988 | prefix. | |
1989 | ||
1990 | The difference to 's' is that this does not allow an | |
81d4177b | 1991 | "immediate" expression. */ |
3bcbcc3d HPN |
1992 | if (! get_autoinc_prefix_or_indir_op (&s, prefixp, |
1993 | &mode, ®no, | |
1994 | &imm_expr_found, | |
1995 | &out_insnp->expr) | |
1996 | || imm_expr_found) | |
1997 | break; | |
1998 | else | |
1999 | { | |
2000 | if (prefixp->kind != PREFIX_NONE) | |
2001 | { | |
2002 | /* A prefix, and those matched here always have | |
2003 | side-effects (see 's' case). */ | |
2004 | out_insnp->opcode |= (AUTOINCR_BIT << 8); | |
2005 | } | |
2006 | else | |
2007 | { | |
2008 | /* No prefix. The "mode" variable contains bits | |
2009 | like whether or not this is autoincrement | |
2010 | mode. */ | |
2011 | out_insnp->opcode |= (mode << 10); | |
2012 | } | |
2013 | ||
2014 | out_insnp->opcode |= regno /* << 0 */; | |
2015 | continue; | |
2016 | } | |
2017 | ||
2018 | case 'z': | |
2019 | /* Size modifier (B or W) in bit <4>. */ | |
2020 | if (! get_bw_size_modifier (&s, &size_bits)) | |
2021 | break; | |
2022 | else | |
2023 | { | |
2024 | out_insnp->opcode |= size_bits << 4; | |
2025 | continue; | |
2026 | } | |
2027 | ||
ae57792d HPN |
2028 | case 'T': |
2029 | if (cris_arch == arch_crisv32 | |
2030 | && get_sup_reg (&s, ®no)) | |
2031 | { | |
2032 | out_insnp->opcode |= regno << 12; | |
2033 | continue; | |
2034 | } | |
2035 | break; | |
2036 | ||
3bcbcc3d HPN |
2037 | default: |
2038 | BAD_CASE (*args); | |
2039 | } | |
2040 | ||
2041 | /* We get here when we fail a match above or we found a | |
2042 | complete match. Break out of this loop. */ | |
2043 | break; | |
2044 | } | |
2045 | ||
2046 | /* Was it a match or a miss? */ | |
2047 | if (match == 0) | |
2048 | { | |
2049 | /* If it's just that the args don't match, maybe the next | |
2050 | item in the table is the same opcode but with | |
ae57792d HPN |
2051 | matching operands. First skip any invalid ones. */ |
2052 | while (instruction[1].name != NULL | |
2053 | && strcmp (instruction->name, instruction[1].name) == 0 | |
2054 | && ! cris_insn_ver_valid_for_arch (instruction[1] | |
2055 | .applicable_version, | |
2056 | cris_arch)) | |
2057 | ++instruction; | |
2058 | ||
3bcbcc3d | 2059 | if (instruction[1].name != NULL |
ae57792d HPN |
2060 | && strcmp (instruction->name, instruction[1].name) == 0 |
2061 | && cris_insn_ver_valid_for_arch (instruction[1] | |
2062 | .applicable_version, | |
2063 | cris_arch)) | |
3bcbcc3d HPN |
2064 | { |
2065 | /* Yep. Restart and try that one instead. */ | |
2066 | ++instruction; | |
2067 | s = operands; | |
2068 | continue; | |
2069 | } | |
2070 | else | |
2071 | { | |
2072 | /* We've come to the end of instructions with this | |
2073 | opcode, so it must be an error. */ | |
2074 | as_bad (_("Illegal operands")); | |
ae57792d HPN |
2075 | |
2076 | /* As discard_rest_of_line, but without continuing to the | |
2077 | next line. */ | |
2078 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2079 | input_line_pointer++; | |
3bcbcc3d HPN |
2080 | return; |
2081 | } | |
2082 | } | |
2083 | else | |
2084 | { | |
2085 | /* We have a match. Check if there's anything more to do. */ | |
2086 | if (imm_expr_found) | |
2087 | { | |
2088 | /* There was an immediate mode operand, so we must check | |
2089 | that it has an appropriate size. */ | |
3bcbcc3d HPN |
2090 | switch (instruction->imm_oprnd_size) |
2091 | { | |
2092 | default: | |
2093 | case SIZE_NONE: | |
2094 | /* Shouldn't happen; this one does not have immediate | |
2095 | operands with different sizes. */ | |
2096 | BAD_CASE (instruction->imm_oprnd_size); | |
2097 | break; | |
2098 | ||
2099 | case SIZE_FIX_32: | |
2100 | out_insnp->imm_oprnd_size = 4; | |
2101 | break; | |
2102 | ||
2103 | case SIZE_SPEC_REG: | |
ae57792d HPN |
2104 | if (cris_arch == arch_crisv32) |
2105 | /* All immediate loads of special registers are | |
2106 | 32-bit on CRISv32. */ | |
2107 | out_insnp->imm_oprnd_size = 4; | |
2108 | else | |
2109 | switch (out_insnp->spec_reg->reg_size) | |
2110 | { | |
2111 | case 1: | |
2112 | if (out_insnp->expr.X_op == O_constant | |
2113 | && (out_insnp->expr.X_add_number < -128 | |
2114 | || out_insnp->expr.X_add_number > 255)) | |
2115 | as_bad (_("Immediate value not in 8 bit range: %ld"), | |
2116 | out_insnp->expr.X_add_number); | |
2117 | /* Fall through. */ | |
2118 | case 2: | |
2119 | /* FIXME: We need an indicator in the instruction | |
2120 | table to pass on, to indicate if we need to check | |
2121 | overflow for a signed or unsigned number. */ | |
2122 | if (out_insnp->expr.X_op == O_constant | |
2123 | && (out_insnp->expr.X_add_number < -32768 | |
2124 | || out_insnp->expr.X_add_number > 65535)) | |
2125 | as_bad (_("Immediate value not in 16 bit range: %ld"), | |
2126 | out_insnp->expr.X_add_number); | |
2127 | out_insnp->imm_oprnd_size = 2; | |
2128 | break; | |
2129 | ||
2130 | case 4: | |
2131 | out_insnp->imm_oprnd_size = 4; | |
2132 | break; | |
2133 | ||
2134 | default: | |
2135 | BAD_CASE (out_insnp->spec_reg->reg_size); | |
2136 | } | |
3bcbcc3d HPN |
2137 | break; |
2138 | ||
2139 | case SIZE_FIELD: | |
ae57792d HPN |
2140 | case SIZE_FIELD_SIGNED: |
2141 | case SIZE_FIELD_UNSIGNED: | |
3bcbcc3d HPN |
2142 | switch (size_bits) |
2143 | { | |
ae57792d HPN |
2144 | /* FIXME: Find way to pass un/signedness to |
2145 | caller, and set reloc type instead, postponing | |
2146 | this check until cris_number_to_imm. That | |
2147 | necessarily corrects the reloc type for the | |
2148 | byte case, maybe requiring further changes. */ | |
3bcbcc3d | 2149 | case 0: |
ae57792d HPN |
2150 | if (out_insnp->expr.X_op == O_constant) |
2151 | { | |
2152 | if (instruction->imm_oprnd_size == SIZE_FIELD | |
2153 | && (out_insnp->expr.X_add_number < -128 | |
2154 | || out_insnp->expr.X_add_number > 255)) | |
2155 | as_bad (_("Immediate value not in 8 bit range: %ld"), | |
2156 | out_insnp->expr.X_add_number); | |
2157 | else if (instruction->imm_oprnd_size == SIZE_FIELD_SIGNED | |
2158 | && (out_insnp->expr.X_add_number < -128 | |
2159 | || out_insnp->expr.X_add_number > 127)) | |
2160 | as_bad (_("Immediate value not in 8 bit signed range: %ld"), | |
2161 | out_insnp->expr.X_add_number); | |
2162 | else if (instruction->imm_oprnd_size == SIZE_FIELD_UNSIGNED | |
2163 | && (out_insnp->expr.X_add_number < 0 | |
2164 | || out_insnp->expr.X_add_number > 255)) | |
2165 | as_bad (_("Immediate value not in 8 bit unsigned range: %ld"), | |
2166 | out_insnp->expr.X_add_number); | |
2167 | } | |
2168 | ||
47926f60 | 2169 | /* Fall through. */ |
3bcbcc3d | 2170 | case 1: |
ae57792d HPN |
2171 | if (out_insnp->expr.X_op == O_constant) |
2172 | { | |
2173 | if (instruction->imm_oprnd_size == SIZE_FIELD | |
2174 | && (out_insnp->expr.X_add_number < -32768 | |
2175 | || out_insnp->expr.X_add_number > 65535)) | |
2176 | as_bad (_("Immediate value not in 16 bit range: %ld"), | |
2177 | out_insnp->expr.X_add_number); | |
2178 | else if (instruction->imm_oprnd_size == SIZE_FIELD_SIGNED | |
2179 | && (out_insnp->expr.X_add_number < -32768 | |
2180 | || out_insnp->expr.X_add_number > 32767)) | |
2181 | as_bad (_("Immediate value not in 16 bit signed range: %ld"), | |
2182 | out_insnp->expr.X_add_number); | |
2183 | else if (instruction->imm_oprnd_size == SIZE_FIELD_UNSIGNED | |
2184 | && (out_insnp->expr.X_add_number < 0 | |
2185 | || out_insnp->expr.X_add_number > 65535)) | |
2186 | as_bad (_("Immediate value not in 16 bit unsigned range: %ld"), | |
2187 | out_insnp->expr.X_add_number); | |
2188 | } | |
3bcbcc3d HPN |
2189 | out_insnp->imm_oprnd_size = 2; |
2190 | break; | |
2191 | ||
2192 | case 2: | |
2193 | out_insnp->imm_oprnd_size = 4; | |
2194 | break; | |
2195 | ||
2196 | default: | |
2197 | BAD_CASE (out_insnp->spec_reg->reg_size); | |
2198 | } | |
2199 | } | |
08caf3f8 HPN |
2200 | |
2201 | /* If there was a relocation specified for the immediate | |
cc99daad HPN |
2202 | expression (i.e. it had a PIC or TLS modifier) check that the |
2203 | size of the relocation matches the size specified by | |
08caf3f8 HPN |
2204 | the opcode. */ |
2205 | if (out_insnp->reloc != BFD_RELOC_NONE | |
cc99daad | 2206 | && (cris_get_specified_reloc_size (out_insnp->reloc) |
08caf3f8 | 2207 | != (unsigned int) out_insnp->imm_oprnd_size)) |
cc99daad HPN |
2208 | as_bad (out_insnp->reloc == BFD_RELOC_CRIS_32_GD |
2209 | || out_insnp->reloc == BFD_RELOC_CRIS_32_TPREL | |
2210 | || out_insnp->reloc == BFD_RELOC_CRIS_16_TPREL | |
2211 | ? _("TLS relocation size does not match operand size") | |
2212 | : _("PIC relocation size does not match operand size")); | |
3bcbcc3d | 2213 | } |
1048a9ba HPN |
2214 | else if (instruction->op == cris_muls_op |
2215 | || instruction->op == cris_mulu_op) | |
2216 | out_insnp->insn_type = CRIS_INSN_MUL; | |
3bcbcc3d HPN |
2217 | } |
2218 | break; | |
2219 | } | |
2220 | } | |
2221 | ||
3bcbcc3d HPN |
2222 | /* Get a B, W, or D size modifier from the string pointed out by *cPP, |
2223 | which must point to a '.' in front of the modifier. On successful | |
2224 | return, *cPP is advanced to the character following the size | |
2225 | modifier, and is undefined otherwise. | |
2226 | ||
2227 | cPP Pointer to pointer to string starting | |
2228 | with the size modifier. | |
2229 | ||
2230 | size_bitsp Pointer to variable to contain the size bits on | |
2231 | successful return. | |
2232 | ||
2233 | Return 1 iff a correct size modifier is found, else 0. */ | |
2234 | ||
2235 | static int | |
695a4822 | 2236 | get_bwd_size_modifier (char **cPP, int *size_bitsp) |
3bcbcc3d HPN |
2237 | { |
2238 | if (**cPP != '.') | |
2239 | return 0; | |
2240 | else | |
2241 | { | |
47926f60 | 2242 | /* Consume the '.'. */ |
3bcbcc3d HPN |
2243 | (*cPP)++; |
2244 | ||
2245 | switch (**cPP) | |
2246 | { | |
2247 | case 'B': | |
2248 | case 'b': | |
2249 | *size_bitsp = 0; | |
2250 | break; | |
2251 | ||
2252 | case 'W': | |
2253 | case 'w': | |
2254 | *size_bitsp = 1; | |
2255 | break; | |
2256 | ||
2257 | case 'D': | |
2258 | case 'd': | |
2259 | *size_bitsp = 2; | |
2260 | break; | |
2261 | ||
2262 | default: | |
2263 | return 0; | |
2264 | } | |
2265 | ||
2266 | /* Consume the size letter. */ | |
2267 | (*cPP)++; | |
2268 | return 1; | |
2269 | } | |
2270 | } | |
2271 | ||
3bcbcc3d HPN |
2272 | /* Get a B or W size modifier from the string pointed out by *cPP, |
2273 | which must point to a '.' in front of the modifier. On successful | |
2274 | return, *cPP is advanced to the character following the size | |
2275 | modifier, and is undefined otherwise. | |
2276 | ||
2277 | cPP Pointer to pointer to string starting | |
2278 | with the size modifier. | |
2279 | ||
2280 | size_bitsp Pointer to variable to contain the size bits on | |
2281 | successful return. | |
2282 | ||
2283 | Return 1 iff a correct size modifier is found, else 0. */ | |
2284 | ||
2285 | static int | |
695a4822 | 2286 | get_bw_size_modifier (char **cPP, int *size_bitsp) |
3bcbcc3d HPN |
2287 | { |
2288 | if (**cPP != '.') | |
2289 | return 0; | |
2290 | else | |
2291 | { | |
47926f60 | 2292 | /* Consume the '.'. */ |
3bcbcc3d HPN |
2293 | (*cPP)++; |
2294 | ||
2295 | switch (**cPP) | |
2296 | { | |
2297 | case 'B': | |
2298 | case 'b': | |
2299 | *size_bitsp = 0; | |
2300 | break; | |
2301 | ||
2302 | case 'W': | |
2303 | case 'w': | |
2304 | *size_bitsp = 1; | |
2305 | break; | |
2306 | ||
2307 | default: | |
2308 | return 0; | |
2309 | } | |
2310 | ||
2311 | /* Consume the size letter. */ | |
2312 | (*cPP)++; | |
2313 | return 1; | |
2314 | } | |
2315 | } | |
2316 | ||
07e90ad5 | 2317 | /* Get a general register from the string pointed out by *cPP. The |
3bcbcc3d HPN |
2318 | variable *cPP is advanced to the character following the general |
2319 | register name on a successful return, and has its initial position | |
2320 | otherwise. | |
2321 | ||
2322 | cPP Pointer to pointer to string, beginning with a general | |
2323 | register name. | |
2324 | ||
2325 | regnop Pointer to int containing the register number. | |
2326 | ||
2327 | Return 1 iff a correct general register designator is found, | |
2328 | else 0. */ | |
2329 | ||
2330 | static int | |
695a4822 | 2331 | get_gen_reg (char **cPP, int *regnop) |
3bcbcc3d HPN |
2332 | { |
2333 | char *oldp; | |
2334 | oldp = *cPP; | |
2335 | ||
7b15d668 HPN |
2336 | /* Handle a sometimes-mandatory dollar sign as register prefix. */ |
2337 | if (**cPP == REGISTER_PREFIX_CHAR) | |
2338 | (*cPP)++; | |
2339 | else if (demand_register_prefix) | |
2340 | return 0; | |
2341 | ||
3bcbcc3d HPN |
2342 | switch (**cPP) |
2343 | { | |
2344 | case 'P': | |
2345 | case 'p': | |
2346 | /* "P" as in "PC"? Consume the "P". */ | |
2347 | (*cPP)++; | |
2348 | ||
2349 | if ((**cPP == 'C' || **cPP == 'c') | |
ae57792d HPN |
2350 | && ! ISALNUM ((*cPP)[1]) |
2351 | /* Here's a little twist: For v32 and the compatibility mode, | |
2352 | we only recognize PC as a register number if there's '+]' | |
2353 | after. We don't consume that, but the presence can only be | |
2354 | valid after a register in a post-increment context, which | |
2355 | is also the only valid context for PC as a register for | |
2356 | v32. Not that it's used very often, but saying "MOVE.D | |
2357 | [PC+],R5" should remain valid. It's not supported for | |
2358 | jump-type insns or other insns with no [Rn+] mode, though. */ | |
2359 | && ((cris_arch != arch_crisv32 | |
2360 | && cris_arch != arch_cris_common_v10_v32) | |
2361 | || ((*cPP)[1] == '+' && (*cPP)[2] == ']'))) | |
3bcbcc3d HPN |
2362 | { |
2363 | /* It's "PC": consume the "c" and we're done. */ | |
2364 | (*cPP)++; | |
2365 | *regnop = REG_PC; | |
2366 | return 1; | |
2367 | } | |
2368 | break; | |
2369 | ||
ae57792d HPN |
2370 | /* Like with PC, we recognize ACR, but only if it's *not* followed |
2371 | by '+', and only for v32. */ | |
2372 | case 'A': | |
2373 | case 'a': | |
2374 | if (cris_arch != arch_crisv32 | |
2375 | || ((*cPP)[1] != 'c' && (*cPP)[1] != 'C') | |
2376 | || ((*cPP)[2] != 'r' && (*cPP)[2] != 'R') | |
2377 | || ISALNUM ((*cPP)[3]) | |
2378 | || (*cPP)[3] == '+') | |
2379 | break; | |
2380 | (*cPP) += 3; | |
2381 | *regnop = 15; | |
2382 | return 1; | |
2383 | ||
3bcbcc3d HPN |
2384 | case 'R': |
2385 | case 'r': | |
47926f60 | 2386 | /* Hopefully r[0-9] or r1[0-5]. Consume 'R' or 'r'. */ |
3bcbcc3d HPN |
2387 | (*cPP)++; |
2388 | ||
3882b010 | 2389 | if (ISDIGIT (**cPP)) |
3bcbcc3d HPN |
2390 | { |
2391 | /* It's r[0-9]. Consume and check the next digit. */ | |
2392 | *regnop = **cPP - '0'; | |
2393 | (*cPP)++; | |
2394 | ||
3882b010 | 2395 | if (! ISALNUM (**cPP)) |
3bcbcc3d | 2396 | { |
47926f60 | 2397 | /* No more digits, we're done. */ |
3bcbcc3d HPN |
2398 | return 1; |
2399 | } | |
2400 | else | |
2401 | { | |
2402 | /* One more digit. Consume and add. */ | |
47926f60 | 2403 | *regnop = *regnop * 10 + (**cPP - '0'); |
3bcbcc3d HPN |
2404 | |
2405 | /* We need to check for a valid register number; Rn, | |
2406 | 0 <= n <= MAX_REG. */ | |
2407 | if (*regnop <= MAX_REG) | |
2408 | { | |
2409 | /* Consume second digit. */ | |
2410 | (*cPP)++; | |
2411 | return 1; | |
2412 | } | |
2413 | } | |
2414 | } | |
2415 | break; | |
2416 | ||
2417 | case 'S': | |
2418 | case 's': | |
2419 | /* "S" as in "SP"? Consume the "S". */ | |
2420 | (*cPP)++; | |
2421 | if (**cPP == 'P' || **cPP == 'p') | |
2422 | { | |
2423 | /* It's "SP": consume the "p" and we're done. */ | |
2424 | (*cPP)++; | |
2425 | *regnop = REG_SP; | |
2426 | return 1; | |
2427 | } | |
2428 | break; | |
2429 | ||
2430 | default: | |
2431 | /* Just here to silence compilation warnings. */ | |
2432 | ; | |
2433 | } | |
2434 | ||
2435 | /* We get here if we fail. Restore the pointer. */ | |
2436 | *cPP = oldp; | |
2437 | return 0; | |
2438 | } | |
2439 | ||
3bcbcc3d HPN |
2440 | /* Get a special register from the string pointed out by *cPP. The |
2441 | variable *cPP is advanced to the character following the special | |
2442 | register name if one is found, and retains its original position | |
2443 | otherwise. | |
2444 | ||
2445 | cPP Pointer to pointer to string starting with a special register | |
2446 | name. | |
2447 | ||
2448 | sregpp Pointer to Pointer to struct spec_reg, where a pointer to the | |
2449 | register description will be stored. | |
2450 | ||
2451 | Return 1 iff a correct special register name is found. */ | |
2452 | ||
2453 | static int | |
695a4822 | 2454 | get_spec_reg (char **cPP, const struct cris_spec_reg **sregpp) |
3bcbcc3d HPN |
2455 | { |
2456 | char *s1; | |
2457 | const char *s2; | |
7b15d668 | 2458 | char *name_begin = *cPP; |
3bcbcc3d HPN |
2459 | |
2460 | const struct cris_spec_reg *sregp; | |
2461 | ||
7b15d668 HPN |
2462 | /* Handle a sometimes-mandatory dollar sign as register prefix. */ |
2463 | if (*name_begin == REGISTER_PREFIX_CHAR) | |
2464 | name_begin++; | |
2465 | else if (demand_register_prefix) | |
2466 | return 0; | |
2467 | ||
3bcbcc3d | 2468 | /* Loop over all special registers. */ |
47926f60 | 2469 | for (sregp = cris_spec_regs; sregp->name != NULL; sregp++) |
3bcbcc3d | 2470 | { |
3bcbcc3d | 2471 | /* Start over from beginning of the supposed name. */ |
7b15d668 | 2472 | s1 = name_begin; |
3bcbcc3d HPN |
2473 | s2 = sregp->name; |
2474 | ||
3882b010 | 2475 | while (*s2 != '\0' && TOLOWER (*s1) == *s2) |
3bcbcc3d HPN |
2476 | { |
2477 | s1++; | |
2478 | s2++; | |
2479 | } | |
2480 | ||
2481 | /* For a match, we must have consumed the name in the table, and we | |
2482 | must be outside what could be part of a name. Assume here that a | |
47926f60 | 2483 | test for alphanumerics is sufficient for a name test. */ |
ae57792d HPN |
2484 | if (*s2 == 0 && ! ISALNUM (*s1) |
2485 | && cris_insn_ver_valid_for_arch (sregp->applicable_version, | |
2486 | cris_arch)) | |
3bcbcc3d | 2487 | { |
47926f60 | 2488 | /* We have a match. Update the pointer and be done. */ |
3bcbcc3d HPN |
2489 | *cPP = s1; |
2490 | *sregpp = sregp; | |
2491 | return 1; | |
2492 | } | |
2493 | } | |
2494 | ||
47926f60 | 2495 | /* If we got here, we did not find any name. */ |
3bcbcc3d HPN |
2496 | return 0; |
2497 | } | |
2498 | ||
ae57792d HPN |
2499 | /* Get a support register from the string pointed out by *cPP. The |
2500 | variable *cPP is advanced to the character following the support- | |
2501 | register name if one is found, and retains its original position | |
2502 | otherwise. | |
2503 | ||
2504 | cPP Pointer to pointer to string starting with a support-register | |
2505 | name. | |
2506 | ||
2507 | sregpp Pointer to int containing the register number. | |
2508 | ||
2509 | Return 1 iff a correct support-register name is found. */ | |
2510 | ||
2511 | static int | |
695a4822 | 2512 | get_sup_reg (char **cPP, int *regnop) |
ae57792d HPN |
2513 | { |
2514 | char *s1; | |
2515 | const char *s2; | |
2516 | char *name_begin = *cPP; | |
2517 | ||
2518 | const struct cris_support_reg *sregp; | |
2519 | ||
2520 | /* Handle a sometimes-mandatory dollar sign as register prefix. */ | |
2521 | if (*name_begin == REGISTER_PREFIX_CHAR) | |
2522 | name_begin++; | |
2523 | else if (demand_register_prefix) | |
2524 | return 0; | |
2525 | ||
2526 | /* Loop over all support-registers. */ | |
2527 | for (sregp = cris_support_regs; sregp->name != NULL; sregp++) | |
2528 | { | |
2529 | /* Start over from beginning of the supposed name. */ | |
2530 | s1 = name_begin; | |
2531 | s2 = sregp->name; | |
2532 | ||
2533 | while (*s2 != '\0' && TOLOWER (*s1) == *s2) | |
2534 | { | |
2535 | s1++; | |
2536 | s2++; | |
2537 | } | |
2538 | ||
2539 | /* For a match, we must have consumed the name in the table, and we | |
2540 | must be outside what could be part of a name. Assume here that a | |
2541 | test for alphanumerics is sufficient for a name test. */ | |
2542 | if (*s2 == 0 && ! ISALNUM (*s1)) | |
2543 | { | |
2544 | /* We have a match. Update the pointer and be done. */ | |
2545 | *cPP = s1; | |
2546 | *regnop = sregp->number; | |
2547 | return 1; | |
2548 | } | |
2549 | } | |
2550 | ||
2551 | /* If we got here, we did not find any name. */ | |
2552 | return 0; | |
2553 | } | |
2554 | ||
3bcbcc3d HPN |
2555 | /* Get an unprefixed or side-effect-prefix operand from the string pointed |
2556 | out by *cPP. The pointer *cPP is advanced to the character following | |
2557 | the indirect operand if we have success, else it contains an undefined | |
2558 | value. | |
2559 | ||
2560 | cPP Pointer to pointer to string beginning with the first | |
2561 | character of the supposed operand. | |
2562 | ||
2563 | prefixp Pointer to structure containing an optional instruction | |
2564 | prefix. | |
2565 | ||
2566 | is_autoincp Pointer to int indicating the indirect or autoincrement | |
2567 | bits. | |
2568 | ||
2569 | src_regnop Pointer to int containing the source register number in | |
2570 | the instruction. | |
2571 | ||
2572 | imm_foundp Pointer to an int indicating if an immediate expression | |
2573 | is found. | |
2574 | ||
2575 | imm_exprP Pointer to a structure containing an immediate | |
2576 | expression, if success and if *imm_foundp is nonzero. | |
2577 | ||
2578 | Return 1 iff a correct indirect operand is found. */ | |
2579 | ||
2580 | static int | |
695a4822 HPN |
2581 | get_autoinc_prefix_or_indir_op (char **cPP, struct cris_prefix *prefixp, |
2582 | int *is_autoincp, int *src_regnop, | |
2583 | int *imm_foundp, expressionS *imm_exprP) | |
3bcbcc3d HPN |
2584 | { |
2585 | /* Assume there was no immediate mode expression. */ | |
2586 | *imm_foundp = 0; | |
2587 | ||
2588 | if (**cPP == '[') | |
2589 | { | |
2590 | /* So this operand is one of: | |
2591 | Indirect: [rN] | |
2592 | Autoincrement: [rN+] | |
2593 | Indexed with assign: [rN=rM+rO.S] | |
2594 | Offset with assign: [rN=rM+I], [rN=rM+[rO].s], [rN=rM+[rO+].s] | |
2595 | ||
2596 | Either way, consume the '['. */ | |
2597 | (*cPP)++; | |
2598 | ||
2599 | /* Get the rN register. */ | |
2600 | if (! get_gen_reg (cPP, src_regnop)) | |
2601 | /* If there was no register, then this cannot match. */ | |
2602 | return 0; | |
2603 | else | |
2604 | { | |
2605 | /* We got the register, now check the next character. */ | |
2606 | switch (**cPP) | |
2607 | { | |
2608 | case ']': | |
2609 | /* Indirect mode. We're done here. */ | |
2610 | prefixp->kind = PREFIX_NONE; | |
2611 | *is_autoincp = 0; | |
2612 | break; | |
2613 | ||
2614 | case '+': | |
2615 | /* This must be an auto-increment mode, if there's a | |
2616 | match. */ | |
2617 | prefixp->kind = PREFIX_NONE; | |
2618 | *is_autoincp = 1; | |
2619 | ||
2620 | /* We consume this character and break out to check the | |
2621 | closing ']'. */ | |
2622 | (*cPP)++; | |
2623 | break; | |
2624 | ||
2625 | case '=': | |
2626 | /* This must be indexed with assign, or offset with assign | |
ae57792d HPN |
2627 | to match. Not supported for crisv32 or in |
2628 | compatibility mode. */ | |
2629 | if (cris_arch == arch_crisv32 | |
2630 | || cris_arch == arch_cris_common_v10_v32) | |
2631 | return 0; | |
2632 | ||
3bcbcc3d HPN |
2633 | (*cPP)++; |
2634 | ||
2635 | /* Either way, the next thing must be a register. */ | |
2636 | if (! get_gen_reg (cPP, &prefixp->base_reg_number)) | |
2637 | /* No register, no match. */ | |
2638 | return 0; | |
2639 | else | |
2640 | { | |
2641 | /* We've consumed "[rN=rM", so we must be looking at | |
2642 | "+rO.s]" or "+I]", or "-I]", or "+[rO].s]" or | |
2643 | "+[rO+].s]". */ | |
2644 | if (**cPP == '+') | |
2645 | { | |
2646 | int index_reg_number; | |
2647 | (*cPP)++; | |
2648 | ||
2649 | if (**cPP == '[') | |
2650 | { | |
2651 | int size_bits; | |
2652 | /* This must be [rx=ry+[rz].s] or | |
2653 | [rx=ry+[rz+].s] or no match. We must be | |
2654 | looking at rz after consuming the '['. */ | |
2655 | (*cPP)++; | |
2656 | ||
2657 | if (!get_gen_reg (cPP, &index_reg_number)) | |
2658 | return 0; | |
2659 | ||
2660 | prefixp->kind = PREFIX_BDAP; | |
2661 | prefixp->opcode | |
2662 | = (BDAP_INDIR_OPCODE | |
2663 | + (prefixp->base_reg_number << 12) | |
2664 | + index_reg_number); | |
2665 | ||
2666 | if (**cPP == '+') | |
2667 | { | |
2668 | /* We've seen "[rx=ry+[rz+" here, so now we | |
2669 | know that there must be "].s]" left to | |
2670 | check. */ | |
2671 | (*cPP)++; | |
2672 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
2673 | } | |
2674 | ||
2675 | /* If it wasn't autoincrement, we don't need to | |
2676 | add anything. */ | |
2677 | ||
2678 | /* Check the next-to-last ']'. */ | |
2679 | if (**cPP != ']') | |
2680 | return 0; | |
2681 | ||
2682 | (*cPP)++; | |
2683 | ||
2684 | /* Check the ".s" modifier. */ | |
2685 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
2686 | return 0; | |
2687 | ||
2688 | prefixp->opcode |= size_bits << 4; | |
2689 | ||
2690 | /* Now we got [rx=ry+[rz+].s or [rx=ry+[rz].s. | |
2691 | We break out to check the final ']'. */ | |
2692 | break; | |
2693 | } | |
ab3e48dc KH |
2694 | /* It wasn't an indirection. Check if it's a |
2695 | register. */ | |
2696 | else if (get_gen_reg (cPP, &index_reg_number)) | |
47926f60 KH |
2697 | { |
2698 | int size_bits; | |
2699 | ||
2700 | /* Indexed with assign mode: "[rN+rM.S]". */ | |
2701 | prefixp->kind = PREFIX_BIAP; | |
2702 | prefixp->opcode | |
2703 | = (BIAP_OPCODE + (index_reg_number << 12) | |
2704 | + prefixp->base_reg_number /* << 0 */); | |
2705 | ||
2706 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
2707 | /* Size missing, this isn't a match. */ | |
2708 | return 0; | |
2709 | else | |
3bcbcc3d | 2710 | { |
47926f60 | 2711 | /* Size found, break out to check the |
3bcbcc3d | 2712 | final ']'. */ |
47926f60 | 2713 | prefixp->opcode |= size_bits << 4; |
3bcbcc3d HPN |
2714 | break; |
2715 | } | |
47926f60 KH |
2716 | } |
2717 | /* Not a register. Then this must be "[rN+I]". */ | |
2718 | else if (cris_get_expression (cPP, &prefixp->expr)) | |
2719 | { | |
2720 | /* We've got offset with assign mode. Fill | |
2721 | in the blanks and break out to match the | |
2722 | final ']'. */ | |
2723 | prefixp->kind = PREFIX_BDAP_IMM; | |
08caf3f8 HPN |
2724 | |
2725 | /* We tentatively put an opcode corresponding to | |
2726 | a 32-bit operand here, although it may be | |
cc99daad HPN |
2727 | relaxed when there's no relocation |
2728 | specifier for the operand. */ | |
08caf3f8 HPN |
2729 | prefixp->opcode |
2730 | = (BDAP_INDIR_OPCODE | |
2731 | | (prefixp->base_reg_number << 12) | |
2732 | | (AUTOINCR_BIT << 8) | |
2733 | | (2 << 4) | |
2734 | | REG_PC /* << 0 */); | |
2735 | ||
2736 | /* This can have a PIC suffix, specifying reloc | |
2737 | type to use. */ | |
cc99daad | 2738 | if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR) |
08caf3f8 HPN |
2739 | { |
2740 | unsigned int relocsize; | |
2741 | ||
cc99daad HPN |
2742 | cris_get_reloc_suffix (cPP, &prefixp->reloc, |
2743 | &prefixp->expr); | |
08caf3f8 HPN |
2744 | |
2745 | /* Tweak the size of the immediate operand | |
2746 | in the prefix opcode if it isn't what we | |
2747 | set. */ | |
2748 | relocsize | |
cc99daad | 2749 | = cris_get_specified_reloc_size (prefixp->reloc); |
08caf3f8 HPN |
2750 | if (relocsize != 4) |
2751 | prefixp->opcode | |
2752 | = ((prefixp->opcode & ~(3 << 4)) | |
2753 | | ((relocsize >> 1) << 4)); | |
2754 | } | |
47926f60 KH |
2755 | break; |
2756 | } | |
2757 | else | |
2758 | /* Neither register nor expression found, so | |
2759 | this can't be a match. */ | |
2760 | return 0; | |
3bcbcc3d | 2761 | } |
47926f60 | 2762 | /* Not "[rN+" but perhaps "[rN-"? */ |
ab3e48dc | 2763 | else if (**cPP == '-') |
47926f60 KH |
2764 | { |
2765 | /* We must have an offset with assign mode. */ | |
2766 | if (! cris_get_expression (cPP, &prefixp->expr)) | |
2767 | /* No expression, no match. */ | |
2768 | return 0; | |
2769 | else | |
2770 | { | |
2771 | /* We've got offset with assign mode. Fill | |
2772 | in the blanks and break out to match the | |
08caf3f8 HPN |
2773 | final ']'. |
2774 | ||
cc99daad HPN |
2775 | Note that we don't allow a relocation |
2776 | suffix for an operand with a minus | |
2777 | sign. */ | |
47926f60 KH |
2778 | prefixp->kind = PREFIX_BDAP_IMM; |
2779 | break; | |
2780 | } | |
2781 | } | |
2782 | else | |
2783 | /* Neither '+' nor '-' after "[rN=rM". Lose. */ | |
2784 | return 0; | |
3bcbcc3d HPN |
2785 | } |
2786 | default: | |
2787 | /* Neither ']' nor '+' nor '=' after "[rN". Lose. */ | |
2788 | return 0; | |
2789 | } | |
2790 | } | |
2791 | ||
2792 | /* When we get here, we have a match and will just check the closing | |
2793 | ']'. We can still fail though. */ | |
2794 | if (**cPP != ']') | |
2795 | return 0; | |
2796 | else | |
2797 | { | |
2798 | /* Don't forget to consume the final ']'. | |
2799 | Then return in glory. */ | |
2800 | (*cPP)++; | |
2801 | return 1; | |
2802 | } | |
2803 | } | |
47926f60 | 2804 | /* No indirection. Perhaps a constant? */ |
ab3e48dc | 2805 | else if (cris_get_expression (cPP, imm_exprP)) |
47926f60 KH |
2806 | { |
2807 | /* Expression found, this is immediate mode. */ | |
2808 | prefixp->kind = PREFIX_NONE; | |
2809 | *is_autoincp = 1; | |
2810 | *src_regnop = REG_PC; | |
2811 | *imm_foundp = 1; | |
08caf3f8 HPN |
2812 | |
2813 | /* This can have a PIC suffix, specifying reloc type to use. The | |
2814 | caller must check that the reloc size matches the operand size. */ | |
cc99daad HPN |
2815 | if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR) |
2816 | cris_get_reloc_suffix (cPP, &prefixp->reloc, imm_exprP); | |
08caf3f8 | 2817 | |
47926f60 KH |
2818 | return 1; |
2819 | } | |
3bcbcc3d HPN |
2820 | |
2821 | /* No luck today. */ | |
2822 | return 0; | |
2823 | } | |
2824 | ||
3bcbcc3d HPN |
2825 | /* This function gets an indirect operand in a three-address operand |
2826 | combination from the string pointed out by *cPP. The pointer *cPP is | |
2827 | advanced to the character following the indirect operand on success, or | |
2828 | has an unspecified value on failure. | |
2829 | ||
2d2255b5 | 2830 | cPP Pointer to pointer to string beginning |
3bcbcc3d HPN |
2831 | with the operand |
2832 | ||
2833 | prefixp Pointer to structure containing an | |
2834 | instruction prefix | |
2835 | ||
2836 | Returns 1 iff a correct indirect operand is found. */ | |
2837 | ||
2838 | static int | |
695a4822 | 2839 | get_3op_or_dip_prefix_op (char **cPP, struct cris_prefix *prefixp) |
3bcbcc3d | 2840 | { |
ab3e48dc KH |
2841 | int reg_number; |
2842 | ||
3bcbcc3d HPN |
2843 | if (**cPP != '[') |
2844 | /* We must have a '[' or it's a clean failure. */ | |
2845 | return 0; | |
3bcbcc3d | 2846 | |
47926f60 KH |
2847 | /* Eat the first '['. */ |
2848 | (*cPP)++; | |
2849 | ||
2850 | if (**cPP == '[') | |
2851 | { | |
2852 | /* A second '[', so this must be double-indirect mode. */ | |
3bcbcc3d | 2853 | (*cPP)++; |
47926f60 KH |
2854 | prefixp->kind = PREFIX_DIP; |
2855 | prefixp->opcode = DIP_OPCODE; | |
3bcbcc3d | 2856 | |
47926f60 KH |
2857 | /* Get the register or fail entirely. */ |
2858 | if (! get_gen_reg (cPP, ®_number)) | |
2859 | return 0; | |
2860 | else | |
3bcbcc3d | 2861 | { |
47926f60 KH |
2862 | prefixp->opcode |= reg_number /* << 0 */ ; |
2863 | if (**cPP == '+') | |
2864 | { | |
2865 | /* Since we found a '+', this must be double-indirect | |
2866 | autoincrement mode. */ | |
2867 | (*cPP)++; | |
2868 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
2869 | } | |
2870 | ||
2871 | /* There's nothing particular to do, if this was a | |
2872 | double-indirect *without* autoincrement. */ | |
2873 | } | |
2874 | ||
2875 | /* Check the first ']'. The second one is checked at the end. */ | |
2876 | if (**cPP != ']') | |
2877 | return 0; | |
2878 | ||
2879 | /* Eat the first ']', so we'll be looking at a second ']'. */ | |
2880 | (*cPP)++; | |
2881 | } | |
2882 | /* No second '['. Then we should have a register here, making | |
2883 | it "[rN". */ | |
2884 | else if (get_gen_reg (cPP, &prefixp->base_reg_number)) | |
2885 | { | |
2886 | /* This must be indexed or offset mode: "[rN+I]" or | |
2887 | "[rN+rM.S]" or "[rN+[rM].S]" or "[rN+[rM+].S]". */ | |
2888 | if (**cPP == '+') | |
2889 | { | |
47926f60 KH |
2890 | int index_reg_number; |
2891 | ||
3bcbcc3d | 2892 | (*cPP)++; |
3bcbcc3d | 2893 | |
47926f60 | 2894 | if (**cPP == '[') |
3bcbcc3d | 2895 | { |
47926f60 KH |
2896 | /* This is "[rx+["... Expect a register next. */ |
2897 | int size_bits; | |
2898 | (*cPP)++; | |
2899 | ||
2900 | if (!get_gen_reg (cPP, &index_reg_number)) | |
2901 | return 0; | |
2902 | ||
2903 | prefixp->kind = PREFIX_BDAP; | |
2904 | prefixp->opcode | |
2905 | = (BDAP_INDIR_OPCODE | |
2906 | + (prefixp->base_reg_number << 12) | |
2907 | + index_reg_number); | |
2908 | ||
2909 | /* We've seen "[rx+[ry", so check if this is | |
2910 | autoincrement. */ | |
3bcbcc3d HPN |
2911 | if (**cPP == '+') |
2912 | { | |
47926f60 | 2913 | /* Yep, now at "[rx+[ry+". */ |
3bcbcc3d HPN |
2914 | (*cPP)++; |
2915 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
2916 | } | |
47926f60 KH |
2917 | /* If it wasn't autoincrement, we don't need to |
2918 | add anything. */ | |
3bcbcc3d | 2919 | |
47926f60 KH |
2920 | /* Check a first closing ']': "[rx+[ry]" or |
2921 | "[rx+[ry+]". */ | |
2922 | if (**cPP != ']') | |
2923 | return 0; | |
2924 | (*cPP)++; | |
3bcbcc3d | 2925 | |
47926f60 KH |
2926 | /* Now expect a size modifier ".S". */ |
2927 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
2928 | return 0; | |
3bcbcc3d | 2929 | |
47926f60 KH |
2930 | prefixp->opcode |= size_bits << 4; |
2931 | ||
2932 | /* Ok, all interesting stuff has been seen: | |
2933 | "[rx+[ry+].S" or "[rx+[ry].S". We only need to | |
2934 | expect a final ']', which we'll do in a common | |
2935 | closing session. */ | |
2936 | } | |
2937 | /* Seen "[rN+", but not a '[', so check if we have a | |
2938 | register. */ | |
2939 | else if (get_gen_reg (cPP, &index_reg_number)) | |
2940 | { | |
2941 | /* This is indexed mode: "[rN+rM.S]" or | |
2942 | "[rN+rM.S+]". */ | |
2943 | int size_bits; | |
2944 | prefixp->kind = PREFIX_BIAP; | |
2945 | prefixp->opcode | |
2946 | = (BIAP_OPCODE | |
2947 | | prefixp->base_reg_number /* << 0 */ | |
2948 | | (index_reg_number << 12)); | |
2949 | ||
07e90ad5 | 2950 | /* Consume the ".S". */ |
47926f60 KH |
2951 | if (! get_bwd_size_modifier (cPP, &size_bits)) |
2952 | /* Missing size, so fail. */ | |
2953 | return 0; | |
3bcbcc3d | 2954 | else |
47926f60 KH |
2955 | /* Size found. Add that piece and drop down to |
2956 | the common checking of the closing ']'. */ | |
2957 | prefixp->opcode |= size_bits << 4; | |
2958 | } | |
2959 | /* Seen "[rN+", but not a '[' or a register, so then | |
ae57792d HPN |
2960 | it must be a constant "I". |
2961 | ||
2962 | As a quality of implementation improvement, we check for a | |
2963 | closing ']', like in an erroneous "[rN+]". If we don't, | |
2964 | the expression parser will emit a confusing "bad | |
2965 | expression" when it sees the ']', probably because it | |
2966 | doesn't like seeing no expression. */ | |
2967 | else if (**cPP != ']' && cris_get_expression (cPP, &prefixp->expr)) | |
47926f60 KH |
2968 | { |
2969 | /* Expression found, so fill in the bits of offset | |
2970 | mode and drop down to check the closing ']'. */ | |
2971 | prefixp->kind = PREFIX_BDAP_IMM; | |
08caf3f8 HPN |
2972 | |
2973 | /* We tentatively put an opcode corresponding to a 32-bit | |
2974 | operand here, although it may be relaxed when there's no | |
2975 | PIC specifier for the operand. */ | |
2976 | prefixp->opcode | |
2977 | = (BDAP_INDIR_OPCODE | |
2978 | | (prefixp->base_reg_number << 12) | |
2979 | | (AUTOINCR_BIT << 8) | |
2980 | | (2 << 4) | |
2981 | | REG_PC /* << 0 */); | |
2982 | ||
2983 | /* This can have a PIC suffix, specifying reloc type to use. */ | |
cc99daad | 2984 | if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR) |
08caf3f8 HPN |
2985 | { |
2986 | unsigned int relocsize; | |
2987 | ||
cc99daad | 2988 | cris_get_reloc_suffix (cPP, &prefixp->reloc, &prefixp->expr); |
08caf3f8 HPN |
2989 | |
2990 | /* Tweak the size of the immediate operand in the prefix | |
2991 | opcode if it isn't what we set. */ | |
cc99daad | 2992 | relocsize = cris_get_specified_reloc_size (prefixp->reloc); |
08caf3f8 HPN |
2993 | if (relocsize != 4) |
2994 | prefixp->opcode | |
2995 | = ((prefixp->opcode & ~(3 << 4)) | |
2996 | | ((relocsize >> 1) << 4)); | |
2997 | } | |
47926f60 KH |
2998 | } |
2999 | else | |
3000 | /* Nothing valid here: lose. */ | |
3001 | return 0; | |
3002 | } | |
3003 | /* Seen "[rN" but no '+', so check if it's a '-'. */ | |
3004 | else if (**cPP == '-') | |
3005 | { | |
3006 | /* Yep, we must have offset mode. */ | |
3007 | if (! cris_get_expression (cPP, &prefixp->expr)) | |
3008 | /* No expression, so we lose. */ | |
3009 | return 0; | |
3010 | else | |
3011 | { | |
3012 | /* Expression found to make this offset mode, so | |
3013 | fill those bits and drop down to check the | |
08caf3f8 HPN |
3014 | closing ']'. |
3015 | ||
3016 | Note that we don't allow a PIC suffix for | |
3017 | an operand with a minus sign like this. */ | |
47926f60 KH |
3018 | prefixp->kind = PREFIX_BDAP_IMM; |
3019 | } | |
3020 | } | |
3021 | else | |
3022 | { | |
3023 | /* We've seen "[rN", but not '+' or '-'; rather a ']'. | |
3024 | Hmm. Normally this is a simple indirect mode that we | |
3025 | shouldn't match, but if we expect ']', then we have a | |
3026 | zero offset, so it can be a three-address-operand, | |
3027 | like "[rN],rO,rP", thus offset mode. | |
3028 | ||
3029 | Don't eat the ']', that will be done in the closing | |
3030 | ceremony. */ | |
3031 | prefixp->expr.X_op = O_constant; | |
3032 | prefixp->expr.X_add_number = 0; | |
3033 | prefixp->expr.X_add_symbol = NULL; | |
3034 | prefixp->expr.X_op_symbol = NULL; | |
3035 | prefixp->kind = PREFIX_BDAP_IMM; | |
3036 | } | |
3037 | } | |
3038 | /* A '[', but no second '[', and no register. Check if we | |
3039 | have an expression, making this "[I]" for a double-indirect | |
3040 | prefix. */ | |
3041 | else if (cris_get_expression (cPP, &prefixp->expr)) | |
3042 | { | |
3043 | /* Expression found, the so called absolute mode for a | |
3044 | double-indirect prefix on PC. */ | |
3045 | prefixp->kind = PREFIX_DIP; | |
3046 | prefixp->opcode = DIP_OPCODE | (AUTOINCR_BIT << 8) | REG_PC; | |
3047 | prefixp->reloc = BFD_RELOC_32; | |
3048 | } | |
3049 | else | |
3050 | /* Neither '[' nor register nor expression. We lose. */ | |
3051 | return 0; | |
3bcbcc3d HPN |
3052 | |
3053 | /* We get here as a closing ceremony to a successful match. We just | |
3054 | need to check the closing ']'. */ | |
3055 | if (**cPP != ']') | |
3056 | /* Oops. Close but no air-polluter. */ | |
3057 | return 0; | |
3058 | ||
3059 | /* Don't forget to consume that ']', before returning in glory. */ | |
3060 | (*cPP)++; | |
3061 | return 1; | |
3062 | } | |
3063 | ||
3bcbcc3d HPN |
3064 | /* Get an expression from the string pointed out by *cPP. |
3065 | The pointer *cPP is advanced to the character following the expression | |
3066 | on a success, or retains its original value otherwise. | |
3067 | ||
3068 | cPP Pointer to pointer to string beginning with the expression. | |
3069 | ||
3070 | exprP Pointer to structure containing the expression. | |
3071 | ||
47926f60 | 3072 | Return 1 iff a correct expression is found. */ |
3bcbcc3d HPN |
3073 | |
3074 | static int | |
695a4822 | 3075 | cris_get_expression (char **cPP, expressionS *exprP) |
3bcbcc3d HPN |
3076 | { |
3077 | char *saved_input_line_pointer; | |
3078 | segT exp; | |
3079 | ||
3080 | /* The "expression" function expects to find an expression at the | |
3081 | global variable input_line_pointer, so we have to save it to give | |
3082 | the impression that we don't fiddle with global variables. */ | |
3083 | saved_input_line_pointer = input_line_pointer; | |
3084 | input_line_pointer = *cPP; | |
3085 | ||
ae57792d HPN |
3086 | /* Avoid a common error, confusing addressing modes. Beware that the |
3087 | call to expression below does not signal that error; it treats [] | |
3088 | as parentheses, unless #define NEED_INDEX_OPERATOR in which case it | |
3089 | gives them other confusing semantics rather than plain outlawing | |
3090 | them, which is what we want. */ | |
3091 | if (*input_line_pointer == '[') | |
3092 | { | |
3093 | input_line_pointer = saved_input_line_pointer; | |
3094 | return 0; | |
3095 | } | |
3096 | ||
3bcbcc3d HPN |
3097 | exp = expression (exprP); |
3098 | if (exprP->X_op == O_illegal || exprP->X_op == O_absent) | |
3099 | { | |
3100 | input_line_pointer = saved_input_line_pointer; | |
3101 | return 0; | |
3102 | } | |
3103 | ||
3104 | /* Everything seems to be fine, just restore the global | |
3105 | input_line_pointer and say we're successful. */ | |
3106 | *cPP = input_line_pointer; | |
3107 | input_line_pointer = saved_input_line_pointer; | |
3108 | return 1; | |
3109 | } | |
3110 | ||
3bcbcc3d HPN |
3111 | /* Get a sequence of flag characters from *spp. The pointer *cPP is |
3112 | advanced to the character following the expression. The flag | |
3113 | characters are consecutive, no commas or spaces. | |
3114 | ||
3115 | cPP Pointer to pointer to string beginning with the expression. | |
3116 | ||
3117 | flagp Pointer to int to return the flags expression. | |
3118 | ||
3119 | Return 1 iff a correct flags expression is found. */ | |
3120 | ||
3121 | static int | |
695a4822 | 3122 | get_flags (char **cPP, int *flagsp) |
3bcbcc3d HPN |
3123 | { |
3124 | for (;;) | |
3125 | { | |
3126 | switch (**cPP) | |
3127 | { | |
3128 | case 'd': | |
3129 | case 'D': | |
ae57792d HPN |
3130 | if (! cris_insn_ver_valid_for_arch (cris_ver_v0_3, |
3131 | cris_arch)) | |
3132 | return 0; | |
3133 | *flagsp |= 0x80; | |
3134 | break; | |
3135 | ||
3bcbcc3d HPN |
3136 | case 'm': |
3137 | case 'M': | |
ae57792d HPN |
3138 | if (! cris_insn_ver_valid_for_arch (cris_ver_v8_10, |
3139 | cris_arch)) | |
3140 | return 0; | |
3bcbcc3d HPN |
3141 | *flagsp |= 0x80; |
3142 | break; | |
3143 | ||
3144 | case 'e': | |
3145 | case 'E': | |
ae57792d HPN |
3146 | if (! cris_insn_ver_valid_for_arch (cris_ver_v0_3, |
3147 | cris_arch)) | |
3148 | return 0; | |
3149 | *flagsp |= 0x40; | |
3150 | break; | |
3151 | ||
3bcbcc3d HPN |
3152 | case 'b': |
3153 | case 'B': | |
ae57792d HPN |
3154 | if (! cris_insn_ver_valid_for_arch (cris_ver_v8_10, |
3155 | cris_arch)) | |
3156 | return 0; | |
3157 | *flagsp |= 0x40; | |
3158 | break; | |
3159 | ||
3160 | case 'p': | |
3161 | case 'P': | |
3162 | if (! cris_insn_ver_valid_for_arch (cris_ver_v32p, | |
3163 | cris_arch)) | |
3164 | return 0; | |
3165 | *flagsp |= 0x80; | |
3166 | break; | |
3167 | ||
3168 | case 'u': | |
3169 | case 'U': | |
3170 | if (! cris_insn_ver_valid_for_arch (cris_ver_v32p, | |
3171 | cris_arch)) | |
3172 | return 0; | |
3bcbcc3d HPN |
3173 | *flagsp |= 0x40; |
3174 | break; | |
3175 | ||
3176 | case 'i': | |
3177 | case 'I': | |
3178 | *flagsp |= 0x20; | |
3179 | break; | |
3180 | ||
3181 | case 'x': | |
3182 | case 'X': | |
3183 | *flagsp |= 0x10; | |
3184 | break; | |
3185 | ||
3186 | case 'n': | |
3187 | case 'N': | |
3188 | *flagsp |= 0x8; | |
3189 | break; | |
3190 | ||
3191 | case 'z': | |
3192 | case 'Z': | |
3193 | *flagsp |= 0x4; | |
3194 | break; | |
3195 | ||
3196 | case 'v': | |
3197 | case 'V': | |
3198 | *flagsp |= 0x2; | |
3199 | break; | |
3200 | ||
3201 | case 'c': | |
3202 | case 'C': | |
3203 | *flagsp |= 1; | |
3204 | break; | |
3205 | ||
3206 | default: | |
3207 | /* We consider this successful if we stop at a comma or | |
47926f60 | 3208 | whitespace. Anything else, and we consider it a failure. */ |
3bcbcc3d HPN |
3209 | if (**cPP != ',' |
3210 | && **cPP != 0 | |
3882b010 | 3211 | && ! ISSPACE (**cPP)) |
3bcbcc3d HPN |
3212 | return 0; |
3213 | else | |
3214 | return 1; | |
3215 | } | |
3216 | ||
3217 | /* Don't forget to consume each flag character. */ | |
3218 | (*cPP)++; | |
3219 | } | |
3220 | } | |
3221 | ||
3bcbcc3d | 3222 | /* Generate code and fixes for a BDAP prefix. |
ae57792d HPN |
3223 | For v32, this handles ADDOQ because thankfully the opcodes are the |
3224 | same. | |
3bcbcc3d HPN |
3225 | |
3226 | base_regno Int containing the base register number. | |
3227 | ||
3228 | exprP Pointer to structure containing the offset expression. */ | |
3229 | ||
3230 | static void | |
695a4822 | 3231 | gen_bdap (int base_regno, expressionS *exprP) |
3bcbcc3d HPN |
3232 | { |
3233 | unsigned int opcode; | |
3234 | char *opcodep; | |
3235 | ||
3236 | /* Put out the prefix opcode; assume quick immediate mode at first. */ | |
3237 | opcode = BDAP_QUICK_OPCODE | (base_regno << 12); | |
ed67db7a | 3238 | opcodep = cris_insn_first_word_frag (); |
3bcbcc3d HPN |
3239 | md_number_to_chars (opcodep, opcode, 2); |
3240 | ||
3241 | if (exprP->X_op == O_constant) | |
3242 | { | |
3243 | /* We have an absolute expression that we know the size of right | |
47926f60 | 3244 | now. */ |
3bcbcc3d HPN |
3245 | long int value; |
3246 | int size; | |
3247 | ||
3248 | value = exprP->X_add_number; | |
3249 | if (value < -32768 || value > 32767) | |
3250 | /* Outside range for a "word", make it a dword. */ | |
3251 | size = 2; | |
3252 | else | |
47926f60 | 3253 | /* Assume "word" size. */ |
3bcbcc3d HPN |
3254 | size = 1; |
3255 | ||
3256 | /* If this is a signed-byte value, we can fit it into the prefix | |
3257 | insn itself. */ | |
3258 | if (value >= -128 && value <= 127) | |
3259 | opcodep[0] = value; | |
3260 | else | |
3261 | { | |
3262 | /* This is a word or dword displacement, which will be put in a | |
3263 | word or dword after the prefix. */ | |
3264 | char *p; | |
3265 | ||
3266 | opcodep[0] = BDAP_PC_LOW + (size << 4); | |
3267 | opcodep[1] &= 0xF0; | |
3268 | opcodep[1] |= BDAP_INCR_HIGH; | |
3269 | p = frag_more (1 << size); | |
3270 | md_number_to_chars (p, value, 1 << size); | |
3271 | } | |
3272 | } | |
3273 | else | |
08caf3f8 HPN |
3274 | { |
3275 | /* Handle complex expressions. */ | |
3276 | valueT addvalue | |
1c971160 | 3277 | = SIMPLE_EXPR (exprP) ? exprP->X_add_number : 0; |
08caf3f8 | 3278 | symbolS *sym |
1c971160 HPN |
3279 | = (SIMPLE_EXPR (exprP) |
3280 | ? exprP->X_add_symbol : make_expr_symbol (exprP)); | |
08caf3f8 HPN |
3281 | |
3282 | /* The expression is not defined yet but may become absolute. We | |
3283 | make it a relocation to be relaxed. */ | |
3284 | frag_var (rs_machine_dependent, 4, 0, | |
3285 | ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF), | |
3286 | sym, addvalue, opcodep); | |
3287 | } | |
3bcbcc3d HPN |
3288 | } |
3289 | ||
3bcbcc3d HPN |
3290 | /* Encode a branch displacement in the range -256..254 into the form used |
3291 | by CRIS conditional branch instructions. | |
3292 | ||
3293 | offset The displacement value in bytes. */ | |
3294 | ||
3295 | static int | |
695a4822 | 3296 | branch_disp (int offset) |
3bcbcc3d HPN |
3297 | { |
3298 | int disp; | |
3299 | ||
ae57792d HPN |
3300 | /* Adjust all short branch offsets here. */ |
3301 | if (cris_arch == arch_crisv32 || cris_arch == arch_cris_common_v10_v32) | |
3302 | offset += 2; | |
3303 | ||
3bcbcc3d HPN |
3304 | disp = offset & 0xFE; |
3305 | ||
3306 | if (offset < 0) | |
3307 | disp |= 1; | |
3308 | ||
3309 | return disp; | |
3310 | } | |
3311 | ||
3bcbcc3d HPN |
3312 | /* Generate code and fixes for a 32-bit conditional branch instruction |
3313 | created by "extending" an existing 8-bit branch instruction. | |
3314 | ||
3315 | opcodep Pointer to the word containing the original 8-bit branch | |
3316 | instruction. | |
3317 | ||
3318 | writep Pointer to "extension area" following the first instruction | |
3319 | word. | |
3320 | ||
3321 | fragP Pointer to the frag containing the instruction. | |
3322 | ||
3323 | add_symP, Parts of the destination address expression. | |
3324 | sub_symP, | |
3325 | add_num. */ | |
3326 | ||
3327 | static void | |
695a4822 HPN |
3328 | gen_cond_branch_32 (char *opcodep, char *writep, fragS *fragP, |
3329 | symbolS *add_symP, symbolS *sub_symP, long int add_num) | |
3bcbcc3d | 3330 | { |
ae57792d HPN |
3331 | int nop_opcode; |
3332 | int opc_offset; | |
3333 | int branch_offset; | |
3334 | ||
3335 | if (cris_arch == arch_crisv32) | |
3336 | { | |
3337 | nop_opcode = NOP_OPCODE_V32; | |
3338 | opc_offset = 10; | |
3339 | branch_offset = -2 - 8; | |
3340 | } | |
d2aa3f9f HPN |
3341 | else if (pic) |
3342 | { | |
3343 | nop_opcode = NOP_OPCODE; | |
3344 | opc_offset = 10; | |
3345 | branch_offset = -2 - 8; | |
3346 | } | |
ae57792d HPN |
3347 | else |
3348 | { | |
3349 | nop_opcode = NOP_OPCODE; | |
3350 | opc_offset = 8; | |
3351 | branch_offset = -2 - 6; | |
3352 | } | |
3353 | ||
3354 | /* We should never get here for compatibility mode. */ | |
3355 | if (cris_arch == arch_cris_common_v10_v32) | |
3356 | as_fatal (_("Calling gen_cond_branch_32 for .arch common_v10_v32\n")); | |
3357 | ||
3bcbcc3d | 3358 | if (warn_for_branch_expansion) |
08caf3f8 HPN |
3359 | as_warn_where (fragP->fr_file, fragP->fr_line, |
3360 | _("32-bit conditional branch generated")); | |
3bcbcc3d HPN |
3361 | |
3362 | /* Here, writep points to what will be opcodep + 2. First, we change | |
3363 | the actual branch in opcodep[0] and opcodep[1], so that in the | |
3364 | final insn, it will look like: | |
3365 | opcodep+10: Bcc .-6 | |
3366 | ||
3367 | This means we don't have to worry about changing the opcode or | |
08caf3f8 | 3368 | messing with the delay-slot instruction. So, we move it to last in |
3bcbcc3d HPN |
3369 | the "extended" branch, and just change the displacement. Admittedly, |
3370 | it's not the optimal extended construct, but we should get this | |
3371 | rarely enough that it shouldn't matter. */ | |
3372 | ||
ae57792d HPN |
3373 | writep[opc_offset] = branch_disp (branch_offset); |
3374 | writep[opc_offset + 1] = opcodep[1]; | |
3bcbcc3d HPN |
3375 | |
3376 | /* Then, we change the branch to an unconditional branch over the | |
3377 | extended part, to the new location of the Bcc: | |
3378 | opcodep: BA .+10 | |
3379 | opcodep+2: NOP | |
3380 | ||
3381 | Note that these two writes are to currently different locations, | |
3382 | merged later. */ | |
3383 | ||
ae57792d | 3384 | md_number_to_chars (opcodep, BA_QUICK_OPCODE |
d2aa3f9f HPN |
3385 | + (cris_arch == arch_crisv32 ? 12 : (pic ? 10 : 8)), |
3386 | 2); | |
ae57792d | 3387 | md_number_to_chars (writep, nop_opcode, 2); |
3bcbcc3d HPN |
3388 | |
3389 | /* Then the extended thing, the 32-bit jump insn. | |
08caf3f8 HPN |
3390 | opcodep+4: JUMP [PC+] |
3391 | or, in the PIC case, | |
d2aa3f9f | 3392 | opcodep+4: MOVE [PC=PC+N],P0. */ |
3bcbcc3d | 3393 | |
08caf3f8 | 3394 | md_number_to_chars (writep + 2, |
ae57792d HPN |
3395 | cris_arch == arch_crisv32 |
3396 | ? BA_DWORD_OPCODE | |
d2aa3f9f HPN |
3397 | : (pic ? MOVE_PC_INCR_OPCODE_PREFIX |
3398 | : JUMP_PC_INCR_OPCODE), 2); | |
3bcbcc3d HPN |
3399 | |
3400 | /* We have to fill in the actual value too. | |
3401 | opcodep+6: .DWORD | |
3402 | This is most probably an expression, but we can cope with an absolute | |
08caf3f8 | 3403 | value too. FIXME: Testcase needed with and without pic. */ |
3bcbcc3d HPN |
3404 | |
3405 | if (add_symP == NULL && sub_symP == NULL) | |
08caf3f8 HPN |
3406 | { |
3407 | /* An absolute address. */ | |
ae57792d | 3408 | if (pic || cris_arch == arch_crisv32) |
08caf3f8 HPN |
3409 | fix_new (fragP, writep + 4 - fragP->fr_literal, 4, |
3410 | section_symbol (absolute_section), | |
ae57792d HPN |
3411 | add_num |
3412 | + (cris_arch == arch_crisv32 ? 6 : 0), | |
3413 | 1, BFD_RELOC_32_PCREL); | |
08caf3f8 HPN |
3414 | else |
3415 | md_number_to_chars (writep + 4, add_num, 4); | |
3416 | } | |
3bcbcc3d HPN |
3417 | else |
3418 | { | |
08caf3f8 HPN |
3419 | if (sub_symP != NULL) |
3420 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
3421 | _("Complex expression not supported")); | |
3bcbcc3d | 3422 | |
08caf3f8 | 3423 | /* Not absolute, we have to make it a frag for later evaluation. */ |
3bcbcc3d | 3424 | fix_new (fragP, writep + 4 - fragP->fr_literal, 4, add_symP, |
ae57792d HPN |
3425 | add_num + (cris_arch == arch_crisv32 ? 6 : 0), |
3426 | pic || cris_arch == arch_crisv32 ? 1 : 0, | |
3427 | pic || cris_arch == arch_crisv32 | |
3428 | ? BFD_RELOC_32_PCREL : BFD_RELOC_32); | |
3bcbcc3d | 3429 | } |
ae57792d HPN |
3430 | |
3431 | if (cris_arch == arch_crisv32) | |
3432 | /* Follow it with a "NOP" for CRISv32. */ | |
3433 | md_number_to_chars (writep + 8, NOP_OPCODE_V32, 2); | |
d2aa3f9f HPN |
3434 | else if (pic) |
3435 | /* ...and the rest of the move-opcode for pre-v32 PIC. */ | |
3436 | md_number_to_chars (writep + 8, MOVE_PC_INCR_OPCODE_SUFFIX, 2); | |
3bcbcc3d HPN |
3437 | } |
3438 | ||
cc99daad HPN |
3439 | /* Get the size of an immediate-reloc in bytes. Only valid for |
3440 | specified relocs (TLS, PIC). */ | |
08caf3f8 HPN |
3441 | |
3442 | static unsigned int | |
cc99daad | 3443 | cris_get_specified_reloc_size (bfd_reloc_code_real_type reloc) |
08caf3f8 | 3444 | { |
cc99daad HPN |
3445 | return |
3446 | reloc == BFD_RELOC_CRIS_16_GOTPLT | |
3447 | || reloc == BFD_RELOC_CRIS_16_GOT | |
3448 | || reloc == BFD_RELOC_CRIS_16_GOT_GD | |
3449 | || reloc == BFD_RELOC_CRIS_16_DTPREL | |
3450 | || reloc == BFD_RELOC_CRIS_16_GOT_TPREL | |
3451 | || reloc == BFD_RELOC_CRIS_16_TPREL | |
08caf3f8 HPN |
3452 | ? 2 : 4; |
3453 | } | |
3454 | ||
3455 | /* Store a reloc type at *RELOCP corresponding to the PIC suffix at *CPP. | |
3456 | Adjust *EXPRP with any addend found after the PIC suffix. */ | |
3457 | ||
3458 | static void | |
cc99daad HPN |
3459 | cris_get_reloc_suffix (char **cPP, bfd_reloc_code_real_type *relocp, |
3460 | expressionS *exprP) | |
08caf3f8 HPN |
3461 | { |
3462 | char *s = *cPP; | |
3463 | unsigned int i; | |
3464 | expressionS const_expr; | |
3465 | ||
3466 | const struct pic_suffixes_struct | |
3467 | { | |
3468 | const char *const suffix; | |
3469 | unsigned int len; | |
3470 | bfd_reloc_code_real_type reloc; | |
cc99daad HPN |
3471 | bfd_boolean pic_p; |
3472 | bfd_boolean tls_p; | |
08caf3f8 HPN |
3473 | } pic_suffixes[] = |
3474 | { | |
3475 | #undef PICMAP | |
cc99daad HPN |
3476 | #define PICMAP(s, r) {s, sizeof (s) - 1, r, TRUE, FALSE} |
3477 | #define PICTLSMAP(s, r) {s, sizeof (s) - 1, r, TRUE, TRUE} | |
3478 | #define TLSMAP(s, r) {s, sizeof (s) - 1, r, FALSE, TRUE} | |
08caf3f8 HPN |
3479 | /* Keep this in order with longest unambiguous prefix first. */ |
3480 | PICMAP ("GOTPLT16", BFD_RELOC_CRIS_16_GOTPLT), | |
3481 | PICMAP ("GOTPLT", BFD_RELOC_CRIS_32_GOTPLT), | |
3482 | PICMAP ("PLTG", BFD_RELOC_CRIS_32_PLT_GOTREL), | |
3483 | PICMAP ("PLT", BFD_RELOC_CRIS_32_PLT_PCREL), | |
3484 | PICMAP ("GOTOFF", BFD_RELOC_CRIS_32_GOTREL), | |
3485 | PICMAP ("GOT16", BFD_RELOC_CRIS_16_GOT), | |
cc99daad HPN |
3486 | PICMAP ("GOT", BFD_RELOC_CRIS_32_GOT), |
3487 | PICTLSMAP ("GDGOTREL16", BFD_RELOC_CRIS_16_GOT_GD), | |
3488 | PICTLSMAP ("GDGOTREL", BFD_RELOC_CRIS_32_GOT_GD), | |
3489 | TLSMAP ("GD", BFD_RELOC_CRIS_32_GD), | |
3490 | PICTLSMAP ("DTPREL16", BFD_RELOC_CRIS_16_DTPREL), | |
3491 | PICTLSMAP ("DTPREL", BFD_RELOC_CRIS_32_DTPREL), | |
3492 | PICTLSMAP ("TPOFFGOT16", BFD_RELOC_CRIS_16_GOT_TPREL), | |
3493 | PICTLSMAP ("TPOFFGOT", BFD_RELOC_CRIS_32_GOT_TPREL), | |
3494 | TLSMAP ("TPOFF16", BFD_RELOC_CRIS_16_TPREL), | |
3495 | TLSMAP ("TPOFF", BFD_RELOC_CRIS_32_TPREL) | |
08caf3f8 HPN |
3496 | }; |
3497 | ||
3498 | /* We've already seen the ':', so consume it. */ | |
3499 | s++; | |
3500 | ||
3501 | for (i = 0; i < sizeof (pic_suffixes)/sizeof (pic_suffixes[0]); i++) | |
3502 | { | |
3503 | if (strncmp (s, pic_suffixes[i].suffix, pic_suffixes[i].len) == 0 | |
cc99daad HPN |
3504 | && ! is_part_of_name (s[pic_suffixes[i].len]) |
3505 | /* PIC and non-PIC relocations are exclusive. */ | |
3506 | && (pic != 0) == (pic_suffixes[i].pic_p != 0) | |
3507 | /* But TLS can be active for non-TLS relocations too. */ | |
3508 | && (pic_suffixes[i].tls_p == 0 || tls)) | |
08caf3f8 HPN |
3509 | { |
3510 | /* We have a match. Consume the suffix and set the relocation | |
3511 | type. */ | |
3512 | s += pic_suffixes[i].len; | |
3513 | ||
3514 | /* There can be a constant term appended. If so, we will add it | |
3515 | to *EXPRP. */ | |
3516 | if (*s == '+' || *s == '-') | |
3517 | { | |
3518 | if (! cris_get_expression (&s, &const_expr)) | |
3519 | /* There was some kind of syntax error. Bail out. */ | |
3520 | break; | |
3521 | ||
3522 | /* Allow complex expressions as the constant part. It still | |
b6ff326e | 3523 | has to be an assembly-time constant or there will be an |
08caf3f8 | 3524 | error emitting the reloc. This makes the PIC qualifiers |
d551a338 | 3525 | idempotent; foo:GOTOFF+32 == foo+32:GOTOFF. The former we |
08caf3f8 HPN |
3526 | recognize here; the latter is parsed in the incoming |
3527 | expression. */ | |
3528 | exprP->X_add_symbol = make_expr_symbol (exprP); | |
3529 | exprP->X_op = O_add; | |
3530 | exprP->X_add_number = 0; | |
3531 | exprP->X_op_symbol = make_expr_symbol (&const_expr); | |
3532 | } | |
3533 | ||
3534 | *relocp = pic_suffixes[i].reloc; | |
3535 | *cPP = s; | |
3536 | return; | |
3537 | } | |
3538 | } | |
3539 | ||
3540 | /* No match. Don't consume anything; fall back and there will be a | |
3541 | syntax error. */ | |
3542 | } | |
3543 | ||
ae57792d | 3544 | /* This *could* have been: |
3bcbcc3d | 3545 | |
47926f60 KH |
3546 | Turn a string in input_line_pointer into a floating point constant |
3547 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
3548 | of LITTLENUMS emitted is stored in *SIZEP. | |
3bcbcc3d HPN |
3549 | |
3550 | type A character from FLTCHARS that describes what kind of | |
3551 | floating-point number is wanted. | |
3552 | ||
3553 | litp A pointer to an array that the result should be stored in. | |
3554 | ||
3555 | sizep A pointer to an integer where the size of the result is stored. | |
3556 | ||
3557 | But we don't support floating point constants in assembly code *at all*, | |
3558 | since it's suboptimal and just opens up bug opportunities. GCC emits | |
3559 | the bit patterns as hex. All we could do here is to emit what GCC | |
3560 | would have done in the first place. *Nobody* writes floating-point | |
3561 | code as assembly code, but if they do, they should be able enough to | |
3562 | find out the correct bit patterns and use them. */ | |
3563 | ||
3564 | char * | |
695a4822 HPN |
3565 | md_atof (int type ATTRIBUTE_UNUSED, char *litp ATTRIBUTE_UNUSED, |
3566 | int *sizep ATTRIBUTE_UNUSED) | |
3bcbcc3d HPN |
3567 | { |
3568 | /* FIXME: Is this function mentioned in the internals.texi manual? If | |
3569 | not, add it. */ | |
3570 | return _("Bad call to md_atof () - floating point formats are not supported"); | |
3571 | } | |
3572 | ||
3bcbcc3d HPN |
3573 | /* Turn a number as a fixS * into a series of bytes that represents the |
3574 | number on the target machine. The purpose of this procedure is the | |
3575 | same as that of md_number_to_chars but this procedure is supposed to | |
3576 | handle general bit field fixes and machine-dependent fixups. | |
3577 | ||
3578 | bufp Pointer to an array where the result should be stored. | |
3579 | ||
3580 | val The value to store. | |
3581 | ||
3582 | n The number of bytes in "val" that should be stored. | |
3583 | ||
08caf3f8 HPN |
3584 | fixP The fix to be applied to the bit field starting at bufp. |
3585 | ||
3586 | seg The segment containing this number. */ | |
3bcbcc3d HPN |
3587 | |
3588 | static void | |
695a4822 | 3589 | cris_number_to_imm (char *bufp, long val, int n, fixS *fixP, segT seg) |
3bcbcc3d HPN |
3590 | { |
3591 | segT sym_seg; | |
3592 | ||
3593 | know (n <= 4); | |
3594 | know (fixP); | |
3595 | ||
3596 | /* We put the relative "vma" for the other segment for inter-segment | |
3597 | relocations in the object data to stay binary "compatible" (with an | |
3598 | uninteresting old version) for the relocation. | |
3599 | Maybe delete some day. */ | |
3600 | if (fixP->fx_addsy | |
08caf3f8 | 3601 | && (sym_seg = S_GET_SEGMENT (fixP->fx_addsy)) != seg) |
3bcbcc3d HPN |
3602 | val += sym_seg->vma; |
3603 | ||
08caf3f8 HPN |
3604 | if (fixP->fx_addsy != NULL || fixP->fx_pcrel) |
3605 | switch (fixP->fx_r_type) | |
3606 | { | |
3607 | /* These must be fully resolved when getting here. */ | |
08caf3f8 HPN |
3608 | case BFD_RELOC_16_PCREL: |
3609 | case BFD_RELOC_8_PCREL: | |
ae57792d | 3610 | as_bad_where (fixP->fx_file, fixP->fx_line, |
08caf3f8 HPN |
3611 | _("PC-relative relocation must be trivially resolved")); |
3612 | default: | |
3613 | ; | |
3614 | } | |
3615 | ||
bfa1b75c HPN |
3616 | /* Only use the computed value for old-arch binaries. For all |
3617 | others, where we're going to output a relocation, put 0 in the | |
3618 | code. */ | |
ae57792d HPN |
3619 | if (cris_arch != arch_cris_any_v0_v10 |
3620 | && (fixP->fx_addsy != NULL || fixP->fx_pcrel)) | |
bfa1b75c | 3621 | val = 0; |
ae57792d | 3622 | |
3bcbcc3d HPN |
3623 | switch (fixP->fx_r_type) |
3624 | { | |
3625 | /* Ditto here, we put the addend into the object code as | |
3626 | well as the reloc addend. Keep it that way for now, to simplify | |
3627 | regression tests on the object file contents. FIXME: Seems | |
3628 | uninteresting now that we have a test suite. */ | |
3629 | ||
cc99daad HPN |
3630 | case BFD_RELOC_CRIS_32_GOT_GD: |
3631 | case BFD_RELOC_CRIS_16_GOT_GD: | |
3632 | case BFD_RELOC_CRIS_32_GD: | |
3633 | case BFD_RELOC_CRIS_32_DTPREL: | |
3634 | case BFD_RELOC_CRIS_16_DTPREL: | |
3635 | case BFD_RELOC_CRIS_32_GOT_TPREL: | |
3636 | case BFD_RELOC_CRIS_16_GOT_TPREL: | |
3637 | case BFD_RELOC_CRIS_32_TPREL: | |
3638 | case BFD_RELOC_CRIS_16_TPREL: | |
f3294356 HPN |
3639 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3640 | if (IS_ELF && fixP->fx_addsy != NULL) | |
3641 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
3642 | #endif | |
3643 | /* Fall through. */ | |
3644 | ||
3645 | case BFD_RELOC_CRIS_16_GOT: | |
3646 | case BFD_RELOC_CRIS_32_GOT: | |
3647 | case BFD_RELOC_CRIS_32_GOTREL: | |
3648 | case BFD_RELOC_CRIS_16_GOTPLT: | |
3649 | case BFD_RELOC_CRIS_32_GOTPLT: | |
3650 | case BFD_RELOC_CRIS_32_PLT_GOTREL: | |
3651 | case BFD_RELOC_CRIS_32_PLT_PCREL: | |
08caf3f8 HPN |
3652 | /* We don't want to put in any kind of non-zero bits in the data |
3653 | being relocated for these. */ | |
bfa1b75c | 3654 | md_number_to_chars (bufp, 0, n); |
08caf3f8 HPN |
3655 | break; |
3656 | ||
08caf3f8 | 3657 | case BFD_RELOC_32_PCREL: |
bfa1b75c | 3658 | /* If this one isn't fully resolved, we don't want to put non-zero |
ae57792d HPN |
3659 | in the object. */ |
3660 | if (fixP->fx_addsy != NULL || fixP->fx_pcrel) | |
bfa1b75c | 3661 | val = 0; |
ae57792d HPN |
3662 | |
3663 | /* Fall through. */ | |
3664 | case BFD_RELOC_32: | |
3bcbcc3d HPN |
3665 | /* No use having warnings here, since most hosts have a 32-bit type |
3666 | for "long" (which will probably change soon, now that I wrote | |
3667 | this). */ | |
3668 | bufp[3] = (val >> 24) & 0xFF; | |
3669 | bufp[2] = (val >> 16) & 0xFF; | |
3670 | bufp[1] = (val >> 8) & 0xFF; | |
3671 | bufp[0] = val & 0xFF; | |
3672 | break; | |
3673 | ||
3674 | /* FIXME: The 16 and 8-bit cases should have a way to check | |
3675 | whether a signed or unsigned (or any signedness) number is | |
ae57792d | 3676 | accepted. */ |
3bcbcc3d HPN |
3677 | |
3678 | case BFD_RELOC_16: | |
08caf3f8 | 3679 | case BFD_RELOC_16_PCREL: |
3bcbcc3d | 3680 | if (val > 0xffff || val < -32768) |
ae57792d HPN |
3681 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3682 | _("Value not in 16 bit range: %ld"), val); | |
bfa1b75c HPN |
3683 | bufp[1] = (val >> 8) & 0xFF; |
3684 | bufp[0] = val & 0xFF; | |
ae57792d HPN |
3685 | break; |
3686 | ||
3687 | case BFD_RELOC_CRIS_SIGNED_16: | |
3688 | if (val > 32767 || val < -32768) | |
3689 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3690 | _("Value not in 16 bit signed range: %ld"), val); | |
bfa1b75c HPN |
3691 | bufp[1] = (val >> 8) & 0xFF; |
3692 | bufp[0] = val & 0xFF; | |
3bcbcc3d HPN |
3693 | break; |
3694 | ||
3695 | case BFD_RELOC_8: | |
08caf3f8 | 3696 | case BFD_RELOC_8_PCREL: |
3bcbcc3d | 3697 | if (val > 255 || val < -128) |
ae57792d | 3698 | as_bad_where (fixP->fx_file, fixP->fx_line, _("Value not in 8 bit range: %ld"), val); |
bfa1b75c | 3699 | bufp[0] = val & 0xFF; |
ae57792d HPN |
3700 | break; |
3701 | ||
3702 | case BFD_RELOC_CRIS_SIGNED_8: | |
3703 | if (val > 127 || val < -128) | |
3704 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3705 | _("Value not in 8 bit signed range: %ld"), val); | |
bfa1b75c | 3706 | bufp[0] = val & 0xFF; |
3bcbcc3d HPN |
3707 | break; |
3708 | ||
ae57792d HPN |
3709 | case BFD_RELOC_CRIS_LAPCQ_OFFSET: |
3710 | /* FIXME: Test-cases for out-of-range values. Probably also need | |
3711 | to use as_bad_where. */ | |
3bcbcc3d HPN |
3712 | case BFD_RELOC_CRIS_UNSIGNED_4: |
3713 | if (val > 15 || val < 0) | |
ae57792d HPN |
3714 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3715 | _("Value not in 4 bit unsigned range: %ld"), val); | |
bfa1b75c | 3716 | bufp[0] |= val & 0x0F; |
3bcbcc3d HPN |
3717 | break; |
3718 | ||
3719 | case BFD_RELOC_CRIS_UNSIGNED_5: | |
3720 | if (val > 31 || val < 0) | |
ae57792d HPN |
3721 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3722 | _("Value not in 5 bit unsigned range: %ld"), val); | |
bfa1b75c | 3723 | bufp[0] |= val & 0x1F; |
3bcbcc3d HPN |
3724 | break; |
3725 | ||
3726 | case BFD_RELOC_CRIS_SIGNED_6: | |
3727 | if (val > 31 || val < -32) | |
ae57792d HPN |
3728 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3729 | _("Value not in 6 bit range: %ld"), val); | |
bfa1b75c | 3730 | bufp[0] |= val & 0x3F; |
3bcbcc3d HPN |
3731 | break; |
3732 | ||
3733 | case BFD_RELOC_CRIS_UNSIGNED_6: | |
3734 | if (val > 63 || val < 0) | |
ae57792d HPN |
3735 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3736 | _("Value not in 6 bit unsigned range: %ld"), val); | |
bfa1b75c | 3737 | bufp[0] |= val & 0x3F; |
3bcbcc3d HPN |
3738 | break; |
3739 | ||
3740 | case BFD_RELOC_CRIS_BDISP8: | |
bfa1b75c | 3741 | bufp[0] = branch_disp (val); |
3bcbcc3d HPN |
3742 | break; |
3743 | ||
3744 | case BFD_RELOC_NONE: | |
3745 | /* May actually happen automatically. For example at broken | |
3746 | words, if the word turns out not to be broken. | |
47926f60 | 3747 | FIXME: When? Which testcase? */ |
3bcbcc3d HPN |
3748 | if (! fixP->fx_addsy) |
3749 | md_number_to_chars (bufp, val, n); | |
3750 | break; | |
3751 | ||
3752 | case BFD_RELOC_VTABLE_INHERIT: | |
3753 | /* This borrowed from tc-ppc.c on a whim. */ | |
3754 | if (fixP->fx_addsy | |
3755 | && !S_IS_DEFINED (fixP->fx_addsy) | |
3756 | && !S_IS_WEAK (fixP->fx_addsy)) | |
3757 | S_SET_WEAK (fixP->fx_addsy); | |
7b15d668 HPN |
3758 | /* Fall through. */ |
3759 | ||
3bcbcc3d | 3760 | case BFD_RELOC_VTABLE_ENTRY: |
3bcbcc3d HPN |
3761 | fixP->fx_done = 0; |
3762 | break; | |
3763 | ||
3764 | default: | |
3765 | BAD_CASE (fixP->fx_r_type); | |
3766 | } | |
3767 | } | |
3768 | ||
3bcbcc3d HPN |
3769 | /* Processes machine-dependent command line options. Called once for |
3770 | each option on the command line that the machine-independent part of | |
3771 | GAS does not understand. */ | |
47926f60 | 3772 | |
3bcbcc3d | 3773 | int |
695a4822 | 3774 | md_parse_option (int arg, char *argp ATTRIBUTE_UNUSED) |
3bcbcc3d HPN |
3775 | { |
3776 | switch (arg) | |
3777 | { | |
3778 | case 'H': | |
3779 | case 'h': | |
7b15d668 | 3780 | printf (_("Please use --help to see usage and options for this assembler.\n")); |
3bcbcc3d | 3781 | md_show_usage (stdout); |
7b15d668 | 3782 | exit (EXIT_SUCCESS); |
3bcbcc3d HPN |
3783 | |
3784 | case 'N': | |
3785 | warn_for_branch_expansion = 1; | |
ae57792d | 3786 | break; |
3bcbcc3d | 3787 | |
7b15d668 | 3788 | case OPTION_NO_US: |
b34976b6 | 3789 | demand_register_prefix = TRUE; |
7b15d668 HPN |
3790 | |
3791 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
08caf3f8 | 3792 | as_bad (_("--no-underscore is invalid with a.out format")); |
7b15d668 | 3793 | else |
b34976b6 | 3794 | symbols_have_leading_underscore = FALSE; |
ae57792d | 3795 | break; |
7b15d668 HPN |
3796 | |
3797 | case OPTION_US: | |
b34976b6 AM |
3798 | demand_register_prefix = FALSE; |
3799 | symbols_have_leading_underscore = TRUE; | |
ae57792d | 3800 | break; |
7b15d668 | 3801 | |
08caf3f8 | 3802 | case OPTION_PIC: |
b34976b6 | 3803 | pic = TRUE; |
d2aa3f9f HPN |
3804 | if (cris_arch != arch_crisv32) |
3805 | md_long_jump_size = cris_any_v0_v10_long_jump_size_pic; | |
3806 | else | |
3807 | md_long_jump_size = crisv32_long_jump_size; | |
ae57792d HPN |
3808 | break; |
3809 | ||
3810 | case OPTION_ARCH: | |
3811 | { | |
3812 | char *str = argp; | |
3813 | enum cris_archs argarch = cris_arch_from_string (&str); | |
3814 | ||
3815 | if (argarch == arch_cris_unknown) | |
3816 | as_bad (_("invalid <arch> in --march=<arch>: %s"), argp); | |
3817 | else | |
3818 | cris_arch = argarch; | |
3819 | ||
3820 | if (argarch == arch_crisv32) | |
3821 | { | |
3822 | err_for_dangerous_mul_placement = 0; | |
3823 | md_long_jump_size = crisv32_long_jump_size; | |
3824 | } | |
3825 | else | |
d2aa3f9f HPN |
3826 | { |
3827 | if (pic) | |
3828 | md_long_jump_size = cris_any_v0_v10_long_jump_size_pic; | |
3829 | else | |
3830 | md_long_jump_size = cris_any_v0_v10_long_jump_size; | |
3831 | } | |
ae57792d HPN |
3832 | } |
3833 | break; | |
08caf3f8 | 3834 | |
1048a9ba HPN |
3835 | case OPTION_MULBUG_ABORT_OFF: |
3836 | err_for_dangerous_mul_placement = 0; | |
ae57792d | 3837 | break; |
1048a9ba HPN |
3838 | |
3839 | case OPTION_MULBUG_ABORT_ON: | |
3840 | err_for_dangerous_mul_placement = 1; | |
ae57792d | 3841 | break; |
1048a9ba | 3842 | |
3bcbcc3d HPN |
3843 | default: |
3844 | return 0; | |
47926f60 | 3845 | } |
ae57792d HPN |
3846 | |
3847 | return 1; | |
3bcbcc3d HPN |
3848 | } |
3849 | ||
3850 | /* Round up a section size to the appropriate boundary. */ | |
3851 | valueT | |
695a4822 | 3852 | md_section_align (segT segment, valueT size) |
3bcbcc3d HPN |
3853 | { |
3854 | /* Round all sects to multiple of 4, except the bss section, which | |
3855 | we'll round to word-size. | |
3856 | ||
3857 | FIXME: Check if this really matters. All sections should be | |
3858 | rounded up, and all sections should (optionally) be assumed to be | |
3859 | dword-aligned, it's just that there is actual usage of linking to a | |
3860 | multiple of two. */ | |
3861 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
3862 | { | |
3863 | if (segment == bss_section) | |
3864 | return (size + 1) & ~1; | |
3865 | return (size + 3) & ~3; | |
3866 | } | |
3867 | else | |
3868 | { | |
3869 | /* FIXME: Is this wanted? It matches the testsuite, but that's not | |
3870 | really a valid reason. */ | |
3871 | if (segment == text_section) | |
3872 | return (size + 3) & ~3; | |
3873 | } | |
3874 | ||
3875 | return size; | |
3876 | } | |
3877 | ||
3bcbcc3d HPN |
3878 | /* Generate a machine-dependent relocation. */ |
3879 | arelent * | |
695a4822 | 3880 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP) |
3bcbcc3d HPN |
3881 | { |
3882 | arelent *relP; | |
3883 | bfd_reloc_code_real_type code; | |
3884 | ||
3885 | switch (fixP->fx_r_type) | |
3886 | { | |
ae57792d HPN |
3887 | case BFD_RELOC_CRIS_SIGNED_8: |
3888 | code = BFD_RELOC_8; | |
3889 | break; | |
3890 | ||
3891 | case BFD_RELOC_CRIS_SIGNED_16: | |
3892 | code = BFD_RELOC_16; | |
3893 | break; | |
3894 | ||
08caf3f8 HPN |
3895 | case BFD_RELOC_CRIS_16_GOT: |
3896 | case BFD_RELOC_CRIS_32_GOT: | |
3897 | case BFD_RELOC_CRIS_16_GOTPLT: | |
3898 | case BFD_RELOC_CRIS_32_GOTPLT: | |
3899 | case BFD_RELOC_CRIS_32_GOTREL: | |
3900 | case BFD_RELOC_CRIS_32_PLT_GOTREL: | |
3901 | case BFD_RELOC_CRIS_32_PLT_PCREL: | |
3bcbcc3d | 3902 | case BFD_RELOC_32: |
ae57792d | 3903 | case BFD_RELOC_32_PCREL: |
3bcbcc3d HPN |
3904 | case BFD_RELOC_16: |
3905 | case BFD_RELOC_8: | |
3906 | case BFD_RELOC_VTABLE_INHERIT: | |
3907 | case BFD_RELOC_VTABLE_ENTRY: | |
ae57792d HPN |
3908 | case BFD_RELOC_CRIS_UNSIGNED_8: |
3909 | case BFD_RELOC_CRIS_UNSIGNED_16: | |
3910 | case BFD_RELOC_CRIS_LAPCQ_OFFSET: | |
cc99daad HPN |
3911 | case BFD_RELOC_CRIS_32_GOT_GD: |
3912 | case BFD_RELOC_CRIS_16_GOT_GD: | |
3913 | case BFD_RELOC_CRIS_32_GD: | |
3914 | case BFD_RELOC_CRIS_32_DTPREL: | |
3915 | case BFD_RELOC_CRIS_16_DTPREL: | |
3916 | case BFD_RELOC_CRIS_32_GOT_TPREL: | |
3917 | case BFD_RELOC_CRIS_16_GOT_TPREL: | |
3918 | case BFD_RELOC_CRIS_32_TPREL: | |
3919 | case BFD_RELOC_CRIS_16_TPREL: | |
3bcbcc3d HPN |
3920 | code = fixP->fx_r_type; |
3921 | break; | |
3922 | default: | |
3923 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3924 | _("Semantics error. This type of operand can not be relocated, it must be an assembly-time constant")); | |
3925 | return 0; | |
3926 | } | |
3927 | ||
3928 | relP = (arelent *) xmalloc (sizeof (arelent)); | |
3929 | assert (relP != 0); | |
3930 | relP->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
3931 | *relP->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); | |
3932 | relP->address = fixP->fx_frag->fr_address + fixP->fx_where; | |
3933 | ||
ae57792d | 3934 | relP->addend = fixP->fx_offset; |
3bcbcc3d HPN |
3935 | |
3936 | /* This is the standard place for KLUDGEs to work around bugs in | |
3937 | bfd_install_relocation (first such note in the documentation | |
3938 | appears with binutils-2.8). | |
3939 | ||
3940 | That function bfd_install_relocation does the wrong thing with | |
3941 | putting stuff into the addend of a reloc (it should stay out) for a | |
3942 | weak symbol. The really bad thing is that it adds the | |
3943 | "segment-relative offset" of the symbol into the reloc. In this | |
3944 | case, the reloc should instead be relative to the symbol with no | |
3945 | other offset than the assembly code shows; and since the symbol is | |
3946 | weak, any local definition should be ignored until link time (or | |
3947 | thereafter). | |
3948 | To wit: weaksym+42 should be weaksym+42 in the reloc, | |
3949 | not weaksym+(offset_from_segment_of_local_weaksym_definition) | |
3950 | ||
3951 | To "work around" this, we subtract the segment-relative offset of | |
3952 | "known" weak symbols. This evens out the extra offset. | |
3953 | ||
3954 | That happens for a.out but not for ELF, since for ELF, | |
3955 | bfd_install_relocation uses the "special function" field of the | |
3956 | howto, and does not execute the code that needs to be undone. */ | |
3957 | ||
3958 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour | |
3959 | && fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy) | |
3960 | && ! bfd_is_und_section (S_GET_SEGMENT (fixP->fx_addsy))) | |
47926f60 KH |
3961 | { |
3962 | relP->addend -= S_GET_VALUE (fixP->fx_addsy); | |
3963 | } | |
3bcbcc3d HPN |
3964 | |
3965 | relP->howto = bfd_reloc_type_lookup (stdoutput, code); | |
3966 | if (! relP->howto) | |
3967 | { | |
3968 | const char *name; | |
3969 | ||
3970 | name = S_GET_NAME (fixP->fx_addsy); | |
3971 | if (name == NULL) | |
3972 | name = _("<unknown>"); | |
3973 | as_fatal (_("Cannot generate relocation type for symbol %s, code %s"), | |
3974 | name, bfd_get_reloc_code_name (code)); | |
3975 | } | |
3976 | ||
3977 | return relP; | |
3978 | } | |
3979 | ||
3bcbcc3d | 3980 | /* Machine-dependent usage-output. */ |
47926f60 | 3981 | |
3bcbcc3d | 3982 | void |
695a4822 | 3983 | md_show_usage (FILE *stream) |
3bcbcc3d | 3984 | { |
08caf3f8 | 3985 | /* The messages are formatted to line up with the generic options. */ |
7b15d668 HPN |
3986 | fprintf (stream, _("CRIS-specific options:\n")); |
3987 | fprintf (stream, "%s", | |
3988 | _(" -h, -H Don't execute, print this help text. Deprecated.\n")); | |
3989 | fprintf (stream, "%s", | |
3990 | _(" -N Warn when branches are expanded to jumps.\n")); | |
3991 | fprintf (stream, "%s", | |
3992 | _(" --underscore User symbols are normally prepended with underscore.\n")); | |
3993 | fprintf (stream, "%s", | |
3994 | _(" Registers will not need any prefix.\n")); | |
3995 | fprintf (stream, "%s", | |
3996 | _(" --no-underscore User symbols do not have any prefix.\n")); | |
3997 | fprintf (stream, "%s", | |
3998 | _(" Registers will require a `$'-prefix.\n")); | |
08caf3f8 HPN |
3999 | fprintf (stream, "%s", |
4000 | _(" --pic Enable generation of position-independent code.\n")); | |
ae57792d HPN |
4001 | fprintf (stream, "%s", |
4002 | _(" --march=<arch> Generate code for <arch>. Valid choices for <arch>\n\ | |
4003 | are v0_v10, v10, v32 and common_v10_v32.\n")); | |
3bcbcc3d HPN |
4004 | } |
4005 | ||
3bcbcc3d | 4006 | /* Apply a fixS (fixup of an instruction or data that we didn't have |
47926f60 | 4007 | enough info to complete immediately) to the data in a frag. */ |
3bcbcc3d | 4008 | |
94f592af | 4009 | void |
55cf6793 | 4010 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
3bcbcc3d | 4011 | { |
451a1fc5 HPN |
4012 | /* This assignment truncates upper bits if valueT is 64 bits (as with |
4013 | --enable-64-bit-bfd), which is fine here, though we cast to avoid | |
920e4177 | 4014 | any compiler warnings. */ |
451a1fc5 | 4015 | long val = (long) *valP; |
3bcbcc3d HPN |
4016 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; |
4017 | ||
4018 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
4019 | fixP->fx_done = 1; | |
4020 | ||
4021 | if (fixP->fx_bit_fixP || fixP->fx_im_disp != 0) | |
4022 | { | |
4023 | as_bad_where (fixP->fx_file, fixP->fx_line, _("Invalid relocation")); | |
4024 | fixP->fx_done = 1; | |
4025 | } | |
4026 | else | |
47926f60 | 4027 | { |
a161fe53 | 4028 | /* We can't actually support subtracting a symbol. */ |
47926f60 | 4029 | if (fixP->fx_subsy != (symbolS *) NULL) |
a161fe53 AM |
4030 | as_bad_where (fixP->fx_file, fixP->fx_line, |
4031 | _("expression too complex")); | |
47926f60 | 4032 | |
ae57792d HPN |
4033 | /* This operand-type is scaled. */ |
4034 | if (fixP->fx_r_type == BFD_RELOC_CRIS_LAPCQ_OFFSET) | |
4035 | val /= 2; | |
08caf3f8 | 4036 | cris_number_to_imm (buf, val, fixP->fx_size, fixP, seg); |
47926f60 | 4037 | } |
3bcbcc3d HPN |
4038 | } |
4039 | ||
3bcbcc3d HPN |
4040 | /* All relocations are relative to the location just after the fixup; |
4041 | the address of the fixup plus its size. */ | |
4042 | ||
4043 | long | |
695a4822 | 4044 | md_pcrel_from (fixS *fixP) |
3bcbcc3d HPN |
4045 | { |
4046 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
4047 | ||
4048 | /* FIXME: We get here only at the end of assembly, when X in ".-X" is | |
08caf3f8 HPN |
4049 | still unknown. Since we don't have pc-relative relocations in a.out, |
4050 | this is invalid. What to do if anything for a.out, is to add | |
3bcbcc3d | 4051 | pc-relative relocations everywhere including the elinux program |
08caf3f8 HPN |
4052 | loader. For ELF, allow straight-forward PC-relative relocations, |
4053 | which are always relative to the location after the relocation. */ | |
4054 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
4055 | || (fixP->fx_r_type != BFD_RELOC_8_PCREL | |
4056 | && fixP->fx_r_type != BFD_RELOC_16_PCREL | |
ae57792d HPN |
4057 | && fixP->fx_r_type != BFD_RELOC_32_PCREL |
4058 | && fixP->fx_r_type != BFD_RELOC_CRIS_LAPCQ_OFFSET)) | |
08caf3f8 HPN |
4059 | as_bad_where (fixP->fx_file, fixP->fx_line, |
4060 | _("Invalid pc-relative relocation")); | |
3bcbcc3d HPN |
4061 | return fixP->fx_size + addr; |
4062 | } | |
4063 | ||
47926f60 | 4064 | /* We have no need to give defaults for symbol-values. */ |
3bcbcc3d | 4065 | symbolS * |
695a4822 | 4066 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
3bcbcc3d HPN |
4067 | { |
4068 | return 0; | |
4069 | } | |
4070 | ||
a161fe53 AM |
4071 | /* If this function returns non-zero, it prevents the relocation |
4072 | against symbol(s) in the FIXP from being replaced with relocations | |
4073 | against section symbols, and guarantees that a relocation will be | |
4074 | emitted even when the value can be resolved locally. */ | |
3bcbcc3d | 4075 | int |
695a4822 | 4076 | md_cris_force_relocation (struct fix *fixp) |
3bcbcc3d | 4077 | { |
08caf3f8 HPN |
4078 | switch (fixp->fx_r_type) |
4079 | { | |
08caf3f8 HPN |
4080 | case BFD_RELOC_CRIS_16_GOT: |
4081 | case BFD_RELOC_CRIS_32_GOT: | |
4082 | case BFD_RELOC_CRIS_16_GOTPLT: | |
4083 | case BFD_RELOC_CRIS_32_GOTPLT: | |
4084 | case BFD_RELOC_CRIS_32_GOTREL: | |
4085 | case BFD_RELOC_CRIS_32_PLT_GOTREL: | |
4086 | case BFD_RELOC_CRIS_32_PLT_PCREL: | |
4087 | return 1; | |
4088 | default: | |
4089 | ; | |
4090 | } | |
4091 | ||
ae6063d4 | 4092 | return generic_force_reloc (fixp); |
3bcbcc3d HPN |
4093 | } |
4094 | ||
4095 | /* Check and emit error if broken-word handling has failed to fix up a | |
4096 | case-table. This is called from write.c, after doing everything it | |
4097 | knows about how to handle broken words. */ | |
4098 | ||
4099 | void | |
695a4822 | 4100 | tc_cris_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP) |
3bcbcc3d HPN |
4101 | { |
4102 | if (new_offset > 32767 || new_offset < -32768) | |
47926f60 | 4103 | /* We really want a genuine error, not a warning, so make it one. */ |
3bcbcc3d HPN |
4104 | as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line, |
4105 | _("Adjusted signed .word (%ld) overflows: `switch'-statement too large."), | |
4106 | (long) new_offset); | |
4107 | } | |
4108 | ||
7b15d668 HPN |
4109 | /* Make a leading REGISTER_PREFIX_CHAR mandatory for all registers. */ |
4110 | ||
695a4822 HPN |
4111 | static void |
4112 | cris_force_reg_prefix (void) | |
7b15d668 | 4113 | { |
b34976b6 | 4114 | demand_register_prefix = TRUE; |
7b15d668 HPN |
4115 | } |
4116 | ||
4117 | /* Do not demand a leading REGISTER_PREFIX_CHAR for all registers. */ | |
4118 | ||
695a4822 HPN |
4119 | static void |
4120 | cris_relax_reg_prefix (void) | |
7b15d668 | 4121 | { |
b34976b6 | 4122 | demand_register_prefix = FALSE; |
7b15d668 HPN |
4123 | } |
4124 | ||
4125 | /* Adjust for having a leading '_' on all user symbols. */ | |
4126 | ||
695a4822 HPN |
4127 | static void |
4128 | cris_sym_leading_underscore (void) | |
7b15d668 HPN |
4129 | { |
4130 | /* We can't really do anything more than assert that what the program | |
4131 | thinks symbol starts with agrees with the command-line options, since | |
4132 | the bfd is already created. */ | |
4133 | ||
b34976b6 | 4134 | if (!symbols_have_leading_underscore) |
ed67db7a | 4135 | as_bad (_(".syntax %s requires command-line option `--underscore'"), |
7b15d668 HPN |
4136 | SYNTAX_USER_SYM_LEADING_UNDERSCORE); |
4137 | } | |
4138 | ||
4139 | /* Adjust for not having any particular prefix on user symbols. */ | |
4140 | ||
695a4822 | 4141 | static void cris_sym_no_leading_underscore (void) |
7b15d668 | 4142 | { |
b34976b6 | 4143 | if (symbols_have_leading_underscore) |
ed67db7a | 4144 | as_bad (_(".syntax %s requires command-line option `--no-underscore'"), |
7b15d668 HPN |
4145 | SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE); |
4146 | } | |
4147 | ||
4148 | /* Handle the .syntax pseudo, which takes an argument that decides what | |
4149 | syntax the assembly code has. */ | |
4150 | ||
4151 | static void | |
695a4822 | 4152 | s_syntax (int ignore ATTRIBUTE_UNUSED) |
7b15d668 HPN |
4153 | { |
4154 | static const struct syntaxes | |
4155 | { | |
ae57792d | 4156 | const char *const operand; |
695a4822 | 4157 | void (*fn) (void); |
4a1805b1 | 4158 | } syntax_table[] = |
7b15d668 HPN |
4159 | {{SYNTAX_ENFORCE_REG_PREFIX, cris_force_reg_prefix}, |
4160 | {SYNTAX_RELAX_REG_PREFIX, cris_relax_reg_prefix}, | |
4161 | {SYNTAX_USER_SYM_LEADING_UNDERSCORE, cris_sym_leading_underscore}, | |
4162 | {SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE, cris_sym_no_leading_underscore}}; | |
4163 | ||
4164 | const struct syntaxes *sp; | |
4165 | ||
4166 | for (sp = syntax_table; | |
4167 | sp < syntax_table + sizeof (syntax_table) / sizeof (syntax_table[0]); | |
4168 | sp++) | |
4169 | { | |
4170 | if (strncmp (input_line_pointer, sp->operand, | |
4171 | strlen (sp->operand)) == 0) | |
4172 | { | |
bc805888 | 4173 | (sp->fn) (); |
7b15d668 HPN |
4174 | |
4175 | input_line_pointer += strlen (sp->operand); | |
4176 | demand_empty_rest_of_line (); | |
4177 | return; | |
4178 | } | |
4179 | } | |
4180 | ||
4181 | as_bad (_("Unknown .syntax operand")); | |
4182 | } | |
4183 | ||
fcdc20a4 HPN |
4184 | /* Wrapper for dwarf2_directive_file to emit error if this is seen when |
4185 | not emitting ELF. */ | |
4186 | ||
4187 | static void | |
695a4822 | 4188 | s_cris_file (int dummy) |
fcdc20a4 HPN |
4189 | { |
4190 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
ed67db7a | 4191 | as_bad (_("Pseudodirective .file is only valid when generating ELF")); |
fcdc20a4 HPN |
4192 | else |
4193 | dwarf2_directive_file (dummy); | |
4194 | } | |
4195 | ||
4196 | /* Wrapper for dwarf2_directive_loc to emit error if this is seen when not | |
4197 | emitting ELF. */ | |
4198 | ||
4199 | static void | |
695a4822 | 4200 | s_cris_loc (int dummy) |
fcdc20a4 HPN |
4201 | { |
4202 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
ed67db7a | 4203 | as_bad (_("Pseudodirective .loc is only valid when generating ELF")); |
fcdc20a4 HPN |
4204 | else |
4205 | dwarf2_directive_loc (dummy); | |
4206 | } | |
4207 | ||
ae57792d HPN |
4208 | /* Translate a <arch> string (as common to --march=<arch> and .arch <arch>) |
4209 | into an enum. If the string *STR is recognized, *STR is updated to point | |
4210 | to the end of the string. If the string is not recognized, | |
4211 | arch_cris_unknown is returned. */ | |
4212 | ||
4213 | static enum cris_archs | |
695a4822 | 4214 | cris_arch_from_string (char **str) |
ae57792d HPN |
4215 | { |
4216 | static const struct cris_arch_struct | |
4217 | { | |
4218 | const char *const name; | |
4219 | enum cris_archs arch; | |
4220 | } arch_table[] = | |
4221 | /* Keep in order longest-first for choices where one is a prefix | |
4222 | of another. */ | |
4223 | {{"v0_v10", arch_cris_any_v0_v10}, | |
4224 | {"v10", arch_crisv10}, | |
4225 | {"v32", arch_crisv32}, | |
4226 | {"common_v10_v32", arch_cris_common_v10_v32}}; | |
4227 | ||
4228 | const struct cris_arch_struct *ap; | |
4229 | ||
4230 | for (ap = arch_table; | |
4231 | ap < arch_table + sizeof (arch_table) / sizeof (arch_table[0]); | |
4232 | ap++) | |
4233 | { | |
4234 | int len = strlen (ap->name); | |
4235 | ||
4236 | if (strncmp (*str, ap->name, len) == 0 | |
4237 | && (str[0][len] == 0 || ISSPACE (str[0][len]))) | |
4238 | { | |
4239 | *str += strlen (ap->name); | |
4240 | return ap->arch; | |
4241 | } | |
4242 | } | |
4243 | ||
4244 | return arch_cris_unknown; | |
4245 | } | |
4246 | ||
4247 | /* Return nonzero if architecture version ARCH matches version range in | |
4248 | IVER. */ | |
4249 | ||
4250 | static int | |
695a4822 HPN |
4251 | cris_insn_ver_valid_for_arch (enum cris_insn_version_usage iver, |
4252 | enum cris_archs arch) | |
ae57792d HPN |
4253 | { |
4254 | switch (arch) | |
4255 | { | |
4256 | case arch_cris_any_v0_v10: | |
4257 | return | |
4258 | (iver == cris_ver_version_all | |
4259 | || iver == cris_ver_warning | |
4260 | || iver == cris_ver_v0_3 | |
4261 | || iver == cris_ver_v3p | |
4262 | || iver == cris_ver_v0_10 | |
4263 | || iver == cris_ver_sim_v0_10 | |
4264 | || iver == cris_ver_v3_10 | |
4265 | || iver == cris_ver_v8 | |
4266 | || iver == cris_ver_v8p | |
4267 | || iver == cris_ver_v8_10 | |
4268 | || iver == cris_ver_v10 | |
4269 | || iver == cris_ver_v10p); | |
4270 | ||
4271 | case arch_crisv32: | |
4272 | return | |
4273 | (iver == cris_ver_version_all | |
4274 | || iver == cris_ver_v3p | |
4275 | || iver == cris_ver_v8p | |
4276 | || iver == cris_ver_v10p | |
4277 | || iver == cris_ver_v32p); | |
4278 | ||
4279 | case arch_cris_common_v10_v32: | |
4280 | return | |
4281 | (iver == cris_ver_version_all | |
4282 | || iver == cris_ver_v3p | |
4283 | || iver == cris_ver_v8p | |
4284 | || iver == cris_ver_v10p); | |
4285 | ||
4286 | case arch_crisv0: | |
4287 | return | |
4288 | (iver == cris_ver_version_all | |
4289 | || iver == cris_ver_v0_3 | |
4290 | || iver == cris_ver_v0_10 | |
4291 | || iver == cris_ver_sim_v0_10); | |
4292 | ||
4293 | case arch_crisv3: | |
4294 | return | |
4295 | (iver == cris_ver_version_all | |
4296 | || iver == cris_ver_v0_3 | |
4297 | || iver == cris_ver_v3p | |
4298 | || iver == cris_ver_v0_10 | |
4299 | || iver == cris_ver_sim_v0_10 | |
4300 | || iver == cris_ver_v3_10); | |
4301 | ||
4302 | case arch_crisv8: | |
4303 | return | |
4304 | (iver == cris_ver_version_all | |
4305 | || iver == cris_ver_v3p | |
4306 | || iver == cris_ver_v0_10 | |
4307 | || iver == cris_ver_sim_v0_10 | |
4308 | || iver == cris_ver_v3_10 | |
4309 | || iver == cris_ver_v8 | |
4310 | || iver == cris_ver_v8p | |
4311 | || iver == cris_ver_v8_10); | |
4312 | ||
4313 | case arch_crisv10: | |
4314 | return | |
4315 | (iver == cris_ver_version_all | |
4316 | || iver == cris_ver_v3p | |
4317 | || iver == cris_ver_v0_10 | |
4318 | || iver == cris_ver_sim_v0_10 | |
4319 | || iver == cris_ver_v3_10 | |
4320 | || iver == cris_ver_v8p | |
4321 | || iver == cris_ver_v8_10 | |
4322 | || iver == cris_ver_v10 | |
4323 | || iver == cris_ver_v10p); | |
4324 | ||
4325 | default: | |
4326 | BAD_CASE (arch); | |
4327 | } | |
4328 | } | |
4329 | ||
4330 | /* Assert that the .arch ARCHCHOICE1 is compatible with the specified or | |
4331 | default --march=<ARCHCHOICE2> option. */ | |
4332 | ||
4333 | static void | |
695a4822 | 4334 | s_cris_arch (int dummy ATTRIBUTE_UNUSED) |
ae57792d HPN |
4335 | { |
4336 | /* Right now we take the easy route and check for sameness. It's not | |
4337 | obvious that allowing e.g. --march=v32 and .arch common_v0_v32 | |
4338 | would be more useful than confusing, implementation-wise and | |
4339 | user-wise. */ | |
4340 | ||
4341 | char *str = input_line_pointer; | |
4342 | enum cris_archs arch = cris_arch_from_string (&str); | |
4343 | ||
4344 | if (arch == arch_cris_unknown) | |
4345 | { | |
4346 | as_bad (_("unknown operand to .arch")); | |
4347 | ||
4348 | /* For this one, str does not reflect the end of the operand, | |
4349 | since there was no matching arch. Skip it manually; skip | |
4350 | things that can be part of a word (a name). */ | |
4351 | while (is_part_of_name (*str)) | |
4352 | str++; | |
4353 | } | |
4354 | else if (arch != cris_arch) | |
4355 | as_bad (_(".arch <arch> requires a matching --march=... option")); | |
4356 | ||
4357 | input_line_pointer = str; | |
4358 | demand_empty_rest_of_line (); | |
4359 | return; | |
4360 | } | |
4361 | ||
3bcbcc3d HPN |
4362 | /* |
4363 | * Local variables: | |
4364 | * eval: (c-set-style "gnu") | |
4365 | * indent-tabs-mode: t | |
4366 | * End: | |
4367 | */ |