Commit | Line | Data |
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3bcbcc3d | 1 | /* tc-cris.c -- Assembler code for the CRIS CPU core. |
aef6203b | 2 | Copyright 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
3bcbcc3d HPN |
3 | |
4 | Contributed by Axis Communications AB, Lund, Sweden. | |
5 | Originally written for GAS 1.38.1 by Mikael Asker. | |
08caf3f8 | 6 | Updates, BFDizing, GNUifying and ELF support by Hans-Peter Nilsson. |
3bcbcc3d HPN |
7 | |
8 | This file is part of GAS, the GNU Assembler. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the | |
22 | Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
47926f60 | 23 | MA 02111-1307, USA. */ |
3bcbcc3d HPN |
24 | |
25 | #include <stdio.h> | |
3bcbcc3d | 26 | #include "as.h" |
3882b010 | 27 | #include "safe-ctype.h" |
3bcbcc3d HPN |
28 | #include "subsegs.h" |
29 | #include "opcode/cris.h" | |
fcdc20a4 | 30 | #include "dwarf2dbg.h" |
3bcbcc3d HPN |
31 | |
32 | /* Conventions used here: | |
33 | Generally speaking, pointers to binutils types such as "fragS" and | |
34 | "expressionS" get parameter and variable names ending in "P", such as | |
35 | "fragP", to harmonize with the rest of the binutils code. Other | |
36 | pointers get a "p" suffix, such as "bufp". Any function or type-name | |
37 | that could clash with a current or future binutils or GAS function get | |
38 | a "cris_" prefix. */ | |
39 | ||
7b15d668 HPN |
40 | #define SYNTAX_RELAX_REG_PREFIX "no_register_prefix" |
41 | #define SYNTAX_ENFORCE_REG_PREFIX "register_prefix" | |
42 | #define SYNTAX_USER_SYM_LEADING_UNDERSCORE "leading_underscore" | |
43 | #define SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE "no_leading_underscore" | |
44 | #define REGISTER_PREFIX_CHAR '$' | |
45 | ||
1c971160 HPN |
46 | /* True for expressions where getting X_add_symbol and X_add_number is |
47 | enough to get the "base" and "offset"; no need to make_expr_symbol. | |
48 | It's not enough to check if X_op_symbol is NULL; that misses unary | |
49 | operations like O_uminus. */ | |
50 | #define SIMPLE_EXPR(EXP) \ | |
51 | ((EXP)->X_op == O_constant || (EXP)->X_op == O_symbol) | |
52 | ||
08caf3f8 HPN |
53 | /* Like in ":GOT", ":GOTOFF" etc. Other ports use '@', but that's in |
54 | line_separator_chars for CRIS, so we avoid it. */ | |
55 | #define PIC_SUFFIX_CHAR ':' | |
56 | ||
3bcbcc3d HPN |
57 | /* This might be CRIS_INSN_NONE if we're assembling a prefix-insn only. |
58 | Note that some prefix-insns might be assembled as CRIS_INSN_NORMAL. */ | |
59 | enum cris_insn_kind | |
60 | { | |
1048a9ba | 61 | CRIS_INSN_NORMAL, CRIS_INSN_NONE, CRIS_INSN_BRANCH, CRIS_INSN_MUL |
3bcbcc3d HPN |
62 | }; |
63 | ||
64 | /* An instruction will have one of these prefixes. | |
65 | Although the same bit-pattern, we handle BDAP with an immediate | |
66 | expression (eventually quick or [pc+]) different from when we only have | |
67 | register expressions. */ | |
68 | enum prefix_kind | |
69 | { | |
70 | PREFIX_NONE, PREFIX_BDAP_IMM, PREFIX_BDAP, PREFIX_BIAP, PREFIX_DIP, | |
71 | PREFIX_PUSH | |
72 | }; | |
73 | ||
74 | /* The prefix for an instruction. */ | |
75 | struct cris_prefix | |
76 | { | |
47926f60 KH |
77 | enum prefix_kind kind; |
78 | int base_reg_number; | |
79 | unsigned int opcode; | |
3bcbcc3d HPN |
80 | |
81 | /* There might be an expression to be evaluated, like I in [rN+I]. */ | |
47926f60 | 82 | expressionS expr; |
3bcbcc3d HPN |
83 | |
84 | /* If there's an expression, we might need a relocation. Here's the | |
85 | type of what relocation to start relaxaton with. | |
86 | The relocation is assumed to start immediately after the prefix insn, | |
87 | so we don't provide an offset. */ | |
88 | enum bfd_reloc_code_real reloc; | |
89 | }; | |
90 | ||
47926f60 | 91 | /* The description of the instruction being assembled. */ |
3bcbcc3d HPN |
92 | struct cris_instruction |
93 | { | |
94 | /* If CRIS_INSN_NONE, then this insn is of zero length. */ | |
47926f60 | 95 | enum cris_insn_kind insn_type; |
3bcbcc3d HPN |
96 | |
97 | /* If a special register was mentioned, this is its description, else | |
47926f60 | 98 | it is NULL. */ |
3bcbcc3d HPN |
99 | const struct cris_spec_reg *spec_reg; |
100 | ||
47926f60 | 101 | unsigned int opcode; |
3bcbcc3d HPN |
102 | |
103 | /* An insn may have at most one expression; theoretically there could be | |
47926f60 KH |
104 | another in its prefix (but I don't see how that could happen). */ |
105 | expressionS expr; | |
3bcbcc3d HPN |
106 | |
107 | /* The expression might need a relocation. Here's one to start | |
108 | relaxation with. */ | |
47926f60 | 109 | enum bfd_reloc_code_real reloc; |
3bcbcc3d | 110 | |
08caf3f8 | 111 | /* The size in bytes of an immediate expression, or zero if |
3bcbcc3d | 112 | nonapplicable. */ |
47926f60 | 113 | int imm_oprnd_size; |
3bcbcc3d HPN |
114 | }; |
115 | ||
ae57792d HPN |
116 | enum cris_archs |
117 | { | |
118 | arch_cris_unknown, | |
119 | arch_crisv0, arch_crisv3, arch_crisv8, arch_crisv10, | |
120 | arch_cris_any_v0_v10, arch_crisv32, arch_cris_common_v10_v32 | |
121 | }; | |
122 | ||
123 | static enum cris_archs cris_arch_from_string PARAMS ((char **)); | |
124 | static int cris_insn_ver_valid_for_arch PARAMS ((enum cris_insn_version_usage, | |
125 | enum cris_archs)); | |
126 | ||
3bcbcc3d HPN |
127 | static void cris_process_instruction PARAMS ((char *, |
128 | struct cris_instruction *, | |
129 | struct cris_prefix *)); | |
130 | static int get_bwd_size_modifier PARAMS ((char **, int *)); | |
131 | static int get_bw_size_modifier PARAMS ((char **, int *)); | |
132 | static int get_gen_reg PARAMS ((char **, int *)); | |
133 | static int get_spec_reg PARAMS ((char **, | |
134 | const struct cris_spec_reg **)); | |
ae57792d | 135 | static int get_sup_reg PARAMS ((char **, int *)); |
3bcbcc3d HPN |
136 | static int get_autoinc_prefix_or_indir_op PARAMS ((char **, |
137 | struct cris_prefix *, | |
138 | int *, int *, int *, | |
139 | expressionS *)); | |
140 | static int get_3op_or_dip_prefix_op PARAMS ((char **, | |
141 | struct cris_prefix *)); | |
142 | static int cris_get_expression PARAMS ((char **, expressionS *)); | |
143 | static int get_flags PARAMS ((char **, int *)); | |
144 | static void gen_bdap PARAMS ((int, expressionS *)); | |
145 | static int branch_disp PARAMS ((int)); | |
146 | static void gen_cond_branch_32 PARAMS ((char *, char *, fragS *, | |
147 | symbolS *, symbolS *, long int)); | |
08caf3f8 | 148 | static void cris_number_to_imm PARAMS ((char *, long, int, fixS *, segT)); |
3bcbcc3d HPN |
149 | static void cris_create_short_jump PARAMS ((char *, addressT, addressT, |
150 | fragS *, symbolS *)); | |
7b15d668 | 151 | static void s_syntax PARAMS ((int)); |
fcdc20a4 HPN |
152 | static void s_cris_file PARAMS ((int)); |
153 | static void s_cris_loc PARAMS ((int)); | |
ae57792d | 154 | static void s_cris_arch PARAMS ((int)); |
7b15d668 | 155 | |
08caf3f8 HPN |
156 | /* Get ":GOT", ":GOTOFF", ":PLT" etc. suffixes. */ |
157 | static void cris_get_pic_suffix PARAMS ((char **, | |
158 | bfd_reloc_code_real_type *, | |
159 | expressionS *)); | |
160 | static unsigned int cris_get_pic_reloc_size | |
161 | PARAMS ((bfd_reloc_code_real_type)); | |
162 | ||
7b15d668 HPN |
163 | /* All the .syntax functions. */ |
164 | static void cris_force_reg_prefix PARAMS ((void)); | |
165 | static void cris_relax_reg_prefix PARAMS ((void)); | |
166 | static void cris_sym_leading_underscore PARAMS ((void)); | |
167 | static void cris_sym_no_leading_underscore PARAMS ((void)); | |
ed67db7a | 168 | static char *cris_insn_first_word_frag PARAMS ((void)); |
7b15d668 | 169 | |
3bcbcc3d HPN |
170 | /* Handle to the opcode hash table. */ |
171 | static struct hash_control *op_hash = NULL; | |
172 | ||
399f703e HPN |
173 | /* If we target cris-axis-linux-gnu (as opposed to generic cris-axis-elf), |
174 | we default to no underscore and required register-prefixes. The | |
175 | difference is in the default values. */ | |
176 | #ifdef TE_LINUX | |
177 | #define DEFAULT_CRIS_AXIS_LINUX_GNU TRUE | |
178 | #else | |
179 | #define DEFAULT_CRIS_AXIS_LINUX_GNU FALSE | |
180 | #endif | |
181 | ||
7b15d668 | 182 | /* Whether we demand that registers have a `$' prefix. Default here. */ |
399f703e | 183 | static bfd_boolean demand_register_prefix = DEFAULT_CRIS_AXIS_LINUX_GNU; |
7b15d668 HPN |
184 | |
185 | /* Whether global user symbols have a leading underscore. Default here. */ | |
399f703e HPN |
186 | static bfd_boolean symbols_have_leading_underscore |
187 | = !DEFAULT_CRIS_AXIS_LINUX_GNU; | |
7b15d668 | 188 | |
08caf3f8 | 189 | /* Whether or not we allow PIC, and expand to PIC-friendly constructs. */ |
b34976b6 | 190 | static bfd_boolean pic = FALSE; |
08caf3f8 | 191 | |
ae57792d HPN |
192 | /* If we're configured for "cris", default to allow all v0..v10 |
193 | instructions and register names. */ | |
194 | #ifndef DEFAULT_CRIS_ARCH | |
195 | #define DEFAULT_CRIS_ARCH cris_any_v0_v10 | |
196 | #endif | |
197 | ||
198 | /* No whitespace in the CONCAT2 parameter list. */ | |
199 | static enum cris_archs cris_arch = XCONCAT2 (arch_,DEFAULT_CRIS_ARCH); | |
200 | ||
3bcbcc3d HPN |
201 | const pseudo_typeS md_pseudo_table[] = |
202 | { | |
203 | {"dword", cons, 4}, | |
7b15d668 | 204 | {"syntax", s_syntax, 0}, |
fcdc20a4 HPN |
205 | {"file", s_cris_file, 0}, |
206 | {"loc", s_cris_loc, 0}, | |
ae57792d | 207 | {"arch", s_cris_arch, 0}, |
3bcbcc3d HPN |
208 | {NULL, 0, 0} |
209 | }; | |
210 | ||
211 | static int warn_for_branch_expansion = 0; | |
212 | ||
1048a9ba HPN |
213 | /* Whether to emit error when a MULS/MULU could be located last on a |
214 | cache-line. */ | |
ae57792d HPN |
215 | static int err_for_dangerous_mul_placement |
216 | = (XCONCAT2 (arch_,DEFAULT_CRIS_ARCH) != arch_crisv32); | |
1048a9ba | 217 | |
3bcbcc3d HPN |
218 | const char cris_comment_chars[] = ";"; |
219 | ||
220 | /* This array holds the chars that only start a comment at the beginning of | |
221 | a line. If the line seems to have the form '# 123 filename' | |
47926f60 | 222 | .line and .file directives will appear in the pre-processed output. */ |
3bcbcc3d HPN |
223 | /* Note that input_file.c hand-checks for '#' at the beginning of the |
224 | first line of the input file. This is because the compiler outputs | |
47926f60 KH |
225 | #NO_APP at the beginning of its output. */ |
226 | /* Also note that slash-star will always start a comment. */ | |
3bcbcc3d HPN |
227 | const char line_comment_chars[] = "#"; |
228 | const char line_separator_chars[] = "@"; | |
229 | ||
230 | /* Now all floating point support is shut off. See md_atof. */ | |
231 | const char EXP_CHARS[] = ""; | |
232 | const char FLT_CHARS[] = ""; | |
233 | ||
3bcbcc3d HPN |
234 | /* For CRIS, we encode the relax_substateTs (in e.g. fr_substate) as: |
235 | 2 1 0 | |
236 | ---/ /--+-----------------+-----------------+-----------------+ | |
237 | | what state ? | how long ? | | |
238 | ---/ /--+-----------------+-----------------+-----------------+ | |
239 | ||
240 | The "how long" bits are 00 = byte, 01 = word, 10 = dword (long). | |
3bcbcc3d HPN |
241 | Not all lengths are legit for a given value of (what state). |
242 | ||
243 | Groups for CRIS address relaxing: | |
244 | ||
ae57792d | 245 | 1. Bcc (pre-V32) |
3bcbcc3d HPN |
246 | length: byte, word, 10-byte expansion |
247 | ||
248 | 2. BDAP | |
1048a9ba HPN |
249 | length: byte, word, dword |
250 | ||
251 | 3. MULS/MULU | |
252 | Not really a relaxation (no infrastructure to get delay-slots | |
253 | right), just an alignment and placement checker for the v10 | |
ae57792d HPN |
254 | multiply/cache-bug. |
255 | ||
256 | 4. Bcc (V32 and later) | |
257 | length: byte, word, 14-byte expansion | |
258 | ||
259 | 5. Bcc (V10+V32) | |
260 | length: byte, word, error | |
261 | ||
262 | 6. BA (V32) | |
263 | length: byte, word, dword | |
3bcbcc3d | 264 | |
ae57792d HPN |
265 | 7. LAPC (V32) |
266 | length: byte, dword | |
267 | */ | |
268 | ||
269 | #define STATE_COND_BRANCH (1) | |
3bcbcc3d | 270 | #define STATE_BASE_PLUS_DISP_PREFIX (2) |
1048a9ba | 271 | #define STATE_MUL (3) |
ae57792d HPN |
272 | #define STATE_COND_BRANCH_V32 (4) |
273 | #define STATE_COND_BRANCH_COMMON (5) | |
274 | #define STATE_ABS_BRANCH_V32 (6) | |
275 | #define STATE_LAPC (7) | |
3bcbcc3d HPN |
276 | |
277 | #define STATE_LENGTH_MASK (3) | |
278 | #define STATE_BYTE (0) | |
279 | #define STATE_WORD (1) | |
280 | #define STATE_DWORD (2) | |
281 | /* Symbol undefined. */ | |
282 | #define STATE_UNDF (3) | |
283 | #define STATE_MAX_LENGTH (3) | |
284 | ||
2d2255b5 | 285 | /* These displacements are relative to the address following the opcode |
3bcbcc3d HPN |
286 | word of the instruction. The first letter is Byte, Word. The 2nd |
287 | letter is Forward, Backward. */ | |
288 | ||
289 | #define BRANCH_BF ( 254) | |
290 | #define BRANCH_BB (-256) | |
ae57792d HPN |
291 | #define BRANCH_BF_V32 ( 252) |
292 | #define BRANCH_BB_V32 (-258) | |
47926f60 KH |
293 | #define BRANCH_WF (2 + 32767) |
294 | #define BRANCH_WB (2 + -32768) | |
ae57792d HPN |
295 | #define BRANCH_WF_V32 (-2 + 32767) |
296 | #define BRANCH_WB_V32 (-2 + -32768) | |
3bcbcc3d HPN |
297 | |
298 | #define BDAP_BF ( 127) | |
299 | #define BDAP_BB (-128) | |
300 | #define BDAP_WF ( 32767) | |
301 | #define BDAP_WB (-32768) | |
302 | ||
303 | #define ENCODE_RELAX(what, length) (((what) << 2) + (length)) | |
304 | ||
305 | const relax_typeS md_cris_relax_table[] = | |
306 | { | |
307 | /* Error sentinel (0, 0). */ | |
308 | {1, 1, 0, 0}, | |
309 | ||
310 | /* Unused (0, 1). */ | |
311 | {1, 1, 0, 0}, | |
312 | ||
313 | /* Unused (0, 2). */ | |
314 | {1, 1, 0, 0}, | |
315 | ||
316 | /* Unused (0, 3). */ | |
317 | {1, 1, 0, 0}, | |
318 | ||
319 | /* Bcc o (1, 0). */ | |
320 | {BRANCH_BF, BRANCH_BB, 0, ENCODE_RELAX (1, 1)}, | |
321 | ||
47926f60 | 322 | /* Bcc [PC+] (1, 1). */ |
3bcbcc3d HPN |
323 | {BRANCH_WF, BRANCH_WB, 2, ENCODE_RELAX (1, 2)}, |
324 | ||
325 | /* BEXT/BWF, BA, JUMP (external), JUMP (always), Bnot_cc, JUMP (default) | |
326 | (1, 2). */ | |
327 | {0, 0, 10, 0}, | |
328 | ||
329 | /* Unused (1, 3). */ | |
330 | {1, 1, 0, 0}, | |
331 | ||
332 | /* BDAP o (2, 0). */ | |
333 | {BDAP_BF, BDAP_BB, 0, ENCODE_RELAX (2, 1)}, | |
334 | ||
335 | /* BDAP.[bw] [PC+] (2, 1). */ | |
336 | {BDAP_WF, BDAP_WB, 2, ENCODE_RELAX (2, 2)}, | |
337 | ||
338 | /* BDAP.d [PC+] (2, 2). */ | |
1048a9ba HPN |
339 | {0, 0, 4, 0}, |
340 | ||
341 | /* Unused (2, 3). */ | |
ae57792d | 342 | {1, 1, 0, 0}, |
1048a9ba HPN |
343 | |
344 | /* MULS/MULU (3, 0). Positions (3, 1..3) are unused. */ | |
ae57792d HPN |
345 | {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, |
346 | ||
347 | /* V32: Bcc o (4, 0). */ | |
348 | {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (4, 1)}, | |
349 | ||
350 | /* V32: Bcc [PC+] (4, 1). */ | |
351 | {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (4, 2)}, | |
352 | ||
353 | /* V32: BA .+12; NOP; BA32 target; NOP; Bcc .-6 (4, 2). */ | |
354 | {0, 0, 12, 0}, | |
355 | ||
356 | /* Unused (4, 3). */ | |
357 | {1, 1, 0, 0}, | |
358 | ||
359 | /* COMMON: Bcc o (5, 0). The offsets are calculated as for v32. Code | |
360 | should contain two nop insns (or four if offset size is large or | |
361 | unknown) after every label. */ | |
362 | {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (5, 1)}, | |
363 | ||
364 | /* COMMON: Bcc [PC+] (5, 1). */ | |
365 | {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (5, 2)}, | |
366 | ||
367 | /* COMMON: FIXME: ???. Treat as error currently. */ | |
368 | {0, 0, 12, 0}, | |
369 | ||
370 | /* Unused (5, 3). */ | |
371 | {1, 1, 0, 0}, | |
372 | ||
373 | /* V32: BA o (6, 0). */ | |
374 | {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (6, 1)}, | |
375 | ||
376 | /* V32: BA.W (6, 1). */ | |
377 | {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (6, 2)}, | |
378 | ||
379 | /* V32: BA.D (6, 2). */ | |
380 | {0, 0, 4, 0}, | |
381 | ||
382 | /* Unused (6, 3). */ | |
383 | {1, 1, 0, 0}, | |
384 | ||
385 | /* LAPC: LAPCQ .+0..15*2,Rn (7, 0). */ | |
386 | {14*2, -1*2, 0, ENCODE_RELAX (7, 2)}, | |
387 | ||
388 | /* Unused (7, 1). | |
389 | While there's a shorter sequence, e.g. LAPCQ + an ADDQ or SUBQ, | |
390 | that would affect flags, so we can't do that as it wouldn't be a | |
391 | proper insn expansion of LAPCQ. This row is associated with a | |
392 | 2-byte expansion, so it's unused rather than the next. */ | |
393 | {1, 1, 0, 0}, | |
394 | ||
395 | /* LAPC: LAPC.D (7, 2). */ | |
396 | {0, 0, 4, 0}, | |
397 | ||
398 | /* Unused (7, 3). */ | |
399 | {1, 1, 0, 0} | |
3bcbcc3d HPN |
400 | }; |
401 | ||
3bcbcc3d HPN |
402 | #undef BDAP_BF |
403 | #undef BDAP_BB | |
404 | #undef BDAP_WF | |
405 | #undef BDAP_WB | |
406 | ||
ae57792d | 407 | /* Target-specific multicharacter options, not const-declared. */ |
3bcbcc3d HPN |
408 | struct option md_longopts[] = |
409 | { | |
7b15d668 HPN |
410 | #define OPTION_NO_US (OPTION_MD_BASE + 0) |
411 | {"no-underscore", no_argument, NULL, OPTION_NO_US}, | |
412 | #define OPTION_US (OPTION_MD_BASE + 1) | |
413 | {"underscore", no_argument, NULL, OPTION_US}, | |
ae57792d | 414 | #define OPTION_PIC (OPTION_US + 1) |
08caf3f8 | 415 | {"pic", no_argument, NULL, OPTION_PIC}, |
ae57792d | 416 | #define OPTION_MULBUG_ABORT_ON (OPTION_PIC + 1) |
1048a9ba | 417 | {"mul-bug-abort", no_argument, NULL, OPTION_MULBUG_ABORT_ON}, |
ae57792d | 418 | #define OPTION_MULBUG_ABORT_OFF (OPTION_MULBUG_ABORT_ON + 1) |
1048a9ba | 419 | {"no-mul-bug-abort", no_argument, NULL, OPTION_MULBUG_ABORT_OFF}, |
ae57792d HPN |
420 | #define OPTION_ARCH (OPTION_MULBUG_ABORT_OFF + 1) |
421 | {"march", required_argument, NULL, OPTION_ARCH}, | |
3bcbcc3d HPN |
422 | {NULL, no_argument, NULL, 0} |
423 | }; | |
424 | ||
ae57792d | 425 | /* Not const-declared. */ |
3bcbcc3d HPN |
426 | size_t md_longopts_size = sizeof (md_longopts); |
427 | const char *md_shortopts = "hHN"; | |
428 | ||
3bcbcc3d HPN |
429 | /* At first glance, this may seems wrong and should be 4 (ba + nop); but |
430 | since a short_jump must skip a *number* of long jumps, it must also be | |
431 | a long jump. Here, we hope to make it a "ba [16bit_offs]" and a "nop" | |
432 | for the delay slot and hope that the jump table at most needs | |
433 | 32767/4=8191 long-jumps. A branch is better than a jump, since it is | |
434 | relative; we will not have a reloc to fix up somewhere. | |
435 | ||
436 | Note that we can't add relocs, because relaxation uses these fixed | |
437 | numbers, and md_create_short_jump is called after relaxation. */ | |
438 | ||
2b4f075a | 439 | int md_short_jump_size = 6; |
ae57792d HPN |
440 | |
441 | /* The v32 version has a delay-slot, hence two bytes longer. */ | |
442 | #define cris_any_v0_v10_long_jump_size 6 | |
443 | #define crisv32_long_jump_size 8 | |
444 | ||
445 | int md_long_jump_size = XCONCAT2 (DEFAULT_CRIS_ARCH,_long_jump_size); | |
3bcbcc3d | 446 | |
7b15d668 | 447 | /* Report output format. Small changes in output format (like elf |
08caf3f8 HPN |
448 | variants below) can happen until all options are parsed, but after |
449 | that, the output format must remain fixed. */ | |
47926f60 | 450 | |
3bcbcc3d HPN |
451 | const char * |
452 | cris_target_format () | |
453 | { | |
454 | switch (OUTPUT_FLAVOR) | |
455 | { | |
456 | case bfd_target_aout_flavour: | |
457 | return "a.out-cris"; | |
458 | ||
459 | case bfd_target_elf_flavour: | |
7b15d668 HPN |
460 | if (symbols_have_leading_underscore) |
461 | return "elf32-us-cris"; | |
3bcbcc3d HPN |
462 | return "elf32-cris"; |
463 | ||
464 | default: | |
465 | abort (); | |
466 | return NULL; | |
467 | } | |
468 | } | |
469 | ||
ae57792d HPN |
470 | /* Return a bfd_mach_cris... value corresponding to the value of |
471 | cris_arch. */ | |
472 | ||
473 | unsigned int | |
474 | cris_mach () | |
475 | { | |
476 | unsigned int retval = 0; | |
477 | ||
478 | switch (cris_arch) | |
479 | { | |
480 | case arch_cris_common_v10_v32: | |
481 | retval = bfd_mach_cris_v10_v32; | |
482 | break; | |
483 | ||
484 | case arch_crisv32: | |
485 | retval = bfd_mach_cris_v32; | |
486 | break; | |
487 | ||
488 | case arch_crisv10: | |
489 | case arch_cris_any_v0_v10: | |
490 | retval = bfd_mach_cris_v0_v10; | |
491 | break; | |
492 | ||
493 | default: | |
494 | BAD_CASE (cris_arch); | |
495 | } | |
496 | ||
497 | return retval; | |
498 | } | |
499 | ||
1c971160 HPN |
500 | /* We need a port-specific relaxation function to cope with sym2 - sym1 |
501 | relative expressions with both symbols in the same segment (but not | |
502 | necessarily in the same frag as this insn), for example: | |
503 | move.d [pc+sym2-(sym1-2)],r10 | |
504 | sym1: | |
505 | The offset can be 8, 16 or 32 bits long. */ | |
506 | ||
507 | long | |
508 | cris_relax_frag (seg, fragP, stretch) | |
509 | segT seg ATTRIBUTE_UNUSED; | |
510 | fragS *fragP; | |
511 | long stretch ATTRIBUTE_UNUSED; | |
512 | { | |
513 | long growth; | |
514 | offsetT aim = 0; | |
515 | symbolS *symbolP; | |
516 | const relax_typeS *this_type; | |
517 | const relax_typeS *start_type; | |
518 | relax_substateT next_state; | |
519 | relax_substateT this_state; | |
520 | const relax_typeS *table = TC_GENERIC_RELAX_TABLE; | |
521 | ||
522 | /* We only have to cope with frags as prepared by | |
fb2fd3e1 | 523 | md_estimate_size_before_relax. The dword cases may get here |
1c971160 HPN |
524 | because of the different reasons that they aren't relaxable. */ |
525 | switch (fragP->fr_subtype) | |
526 | { | |
ae57792d HPN |
527 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD): |
528 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD): | |
529 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD): | |
530 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD): | |
531 | case ENCODE_RELAX (STATE_LAPC, STATE_DWORD): | |
1c971160 HPN |
532 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): |
533 | /* When we get to these states, the frag won't grow any more. */ | |
534 | return 0; | |
535 | ||
536 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): | |
537 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): | |
538 | if (fragP->fr_symbol == NULL | |
539 | || S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) | |
540 | as_fatal (_("internal inconsistency problem in %s: fr_symbol %lx"), | |
541 | __FUNCTION__, (long) fragP->fr_symbol); | |
542 | symbolP = fragP->fr_symbol; | |
543 | if (symbol_resolved_p (symbolP)) | |
544 | as_fatal (_("internal inconsistency problem in %s: resolved symbol"), | |
545 | __FUNCTION__); | |
546 | aim = S_GET_VALUE (symbolP); | |
547 | break; | |
548 | ||
1048a9ba HPN |
549 | case ENCODE_RELAX (STATE_MUL, STATE_BYTE): |
550 | /* Nothing to do here. */ | |
551 | return 0; | |
552 | ||
1c971160 HPN |
553 | default: |
554 | as_fatal (_("internal inconsistency problem in %s: fr_subtype %d"), | |
555 | __FUNCTION__, fragP->fr_subtype); | |
556 | } | |
557 | ||
558 | /* The rest is stolen from relax_frag. There's no obvious way to | |
559 | share the code, but fortunately no requirement to keep in sync as | |
560 | long as fragP->fr_symbol does not have its segment changed. */ | |
561 | ||
562 | this_state = fragP->fr_subtype; | |
563 | start_type = this_type = table + this_state; | |
564 | ||
565 | if (aim < 0) | |
566 | { | |
567 | /* Look backwards. */ | |
568 | for (next_state = this_type->rlx_more; next_state;) | |
569 | if (aim >= this_type->rlx_backward) | |
570 | next_state = 0; | |
571 | else | |
572 | { | |
573 | /* Grow to next state. */ | |
574 | this_state = next_state; | |
575 | this_type = table + this_state; | |
576 | next_state = this_type->rlx_more; | |
577 | } | |
578 | } | |
579 | else | |
580 | { | |
581 | /* Look forwards. */ | |
582 | for (next_state = this_type->rlx_more; next_state;) | |
583 | if (aim <= this_type->rlx_forward) | |
584 | next_state = 0; | |
585 | else | |
586 | { | |
587 | /* Grow to next state. */ | |
588 | this_state = next_state; | |
589 | this_type = table + this_state; | |
590 | next_state = this_type->rlx_more; | |
591 | } | |
592 | } | |
593 | ||
594 | growth = this_type->rlx_length - start_type->rlx_length; | |
595 | if (growth != 0) | |
596 | fragP->fr_subtype = this_state; | |
597 | return growth; | |
598 | } | |
599 | ||
3bcbcc3d HPN |
600 | /* Prepare machine-dependent frags for relaxation. |
601 | ||
602 | Called just before relaxation starts. Any symbol that is now undefined | |
603 | will not become defined. | |
604 | ||
605 | Return the correct fr_subtype in the frag. | |
606 | ||
607 | Return the initial "guess for fr_var" to caller. The guess for fr_var | |
608 | is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix | |
609 | or fr_var contributes to our returned value. | |
610 | ||
611 | Although it may not be explicit in the frag, pretend | |
47926f60 | 612 | fr_var starts with a value. */ |
3bcbcc3d HPN |
613 | |
614 | int | |
615 | md_estimate_size_before_relax (fragP, segment_type) | |
616 | fragS *fragP; | |
617 | /* The segment is either N_DATA or N_TEXT. */ | |
47926f60 | 618 | segT segment_type; |
3bcbcc3d | 619 | { |
47926f60 | 620 | int old_fr_fix; |
ae57792d HPN |
621 | symbolS *symbolP = fragP->fr_symbol; |
622 | ||
623 | #define HANDLE_RELAXABLE(state) \ | |
624 | case ENCODE_RELAX (state, STATE_UNDF): \ | |
625 | if (symbolP != NULL \ | |
626 | && S_GET_SEGMENT (symbolP) == segment_type \ | |
627 | && !S_IS_WEAK (symbolP)) \ | |
628 | /* The symbol lies in the same segment - a relaxable \ | |
629 | case. */ \ | |
630 | fragP->fr_subtype \ | |
631 | = ENCODE_RELAX (state, STATE_BYTE); \ | |
632 | else \ | |
633 | /* Unknown or not the same segment, so not relaxable. */ \ | |
634 | fragP->fr_subtype \ | |
635 | = ENCODE_RELAX (state, STATE_DWORD); \ | |
636 | fragP->fr_var \ | |
637 | = md_cris_relax_table[fragP->fr_subtype].rlx_length; \ | |
638 | break | |
3bcbcc3d HPN |
639 | |
640 | old_fr_fix = fragP->fr_fix; | |
641 | ||
642 | switch (fragP->fr_subtype) | |
643 | { | |
ae57792d HPN |
644 | HANDLE_RELAXABLE (STATE_COND_BRANCH); |
645 | HANDLE_RELAXABLE (STATE_COND_BRANCH_V32); | |
646 | HANDLE_RELAXABLE (STATE_COND_BRANCH_COMMON); | |
647 | HANDLE_RELAXABLE (STATE_ABS_BRANCH_V32); | |
648 | ||
649 | case ENCODE_RELAX (STATE_LAPC, STATE_UNDF): | |
650 | if (symbolP != NULL | |
651 | && S_GET_SEGMENT (symbolP) == segment_type | |
652 | && !S_IS_WEAK (symbolP)) | |
653 | { | |
654 | /* The symbol lies in the same segment - a relaxable case. | |
655 | Check if we currently have an odd offset; we can't code | |
656 | that into the instruction. Relaxing presumably only cause | |
657 | multiple-of-two changes, so we should only need to adjust | |
658 | for that here. */ | |
659 | bfd_vma target_address | |
660 | = (symbolP | |
661 | ? S_GET_VALUE (symbolP) | |
662 | : 0) + fragP->fr_offset; | |
663 | bfd_vma var_part_offset = fragP->fr_fix; | |
664 | bfd_vma address_of_var_part = fragP->fr_address + var_part_offset; | |
665 | long offset = target_address - (address_of_var_part - 2); | |
666 | ||
667 | fragP->fr_subtype | |
668 | = (offset & 1) | |
669 | ? ENCODE_RELAX (STATE_LAPC, STATE_DWORD) | |
670 | : ENCODE_RELAX (STATE_LAPC, STATE_BYTE); | |
671 | } | |
3bcbcc3d | 672 | else |
c335d394 HPN |
673 | /* Unknown or not the same segment, so not relaxable. */ |
674 | fragP->fr_subtype | |
ae57792d HPN |
675 | = ENCODE_RELAX (STATE_LAPC, STATE_DWORD); |
676 | fragP->fr_var | |
677 | = md_cris_relax_table[fragP->fr_subtype].rlx_length; | |
3bcbcc3d HPN |
678 | break; |
679 | ||
680 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF): | |
681 | /* Note that we can not do anything sane with relaxing | |
682 | [rX + a_known_symbol_in_text], it will have to be a 32-bit | |
683 | value. | |
684 | ||
685 | We could play tricks with managing a constant pool and make | |
08caf3f8 HPN |
686 | a_known_symbol_in_text a "bdap [pc + offset]" pointing there |
687 | (like the GOT for ELF shared libraries), but that's no use, it | |
688 | would in general be no shorter or faster code, only more | |
689 | complicated. */ | |
3bcbcc3d | 690 | |
ae57792d | 691 | if (S_GET_SEGMENT (symbolP) != absolute_section) |
3bcbcc3d HPN |
692 | { |
693 | /* Go for dword if not absolute or same segment. */ | |
694 | fragP->fr_subtype | |
695 | = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD); | |
c335d394 | 696 | fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; |
3bcbcc3d | 697 | } |
1c971160 HPN |
698 | else if (!symbol_resolved_p (fragP->fr_symbol)) |
699 | { | |
700 | /* The symbol will eventually be completely resolved as an | |
701 | absolute expression, but right now it depends on the result | |
702 | of relaxation and we don't know anything else about the | |
703 | value. We start relaxation with the assumption that it'll | |
704 | fit in a byte. */ | |
705 | fragP->fr_subtype | |
706 | = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE); | |
707 | fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; | |
708 | } | |
3bcbcc3d HPN |
709 | else |
710 | { | |
711 | /* Absolute expression. */ | |
712 | long int value; | |
ae57792d HPN |
713 | value = (symbolP != NULL |
714 | ? S_GET_VALUE (symbolP) : 0) + fragP->fr_offset; | |
3bcbcc3d HPN |
715 | |
716 | if (value >= -128 && value <= 127) | |
717 | { | |
718 | /* Byte displacement. */ | |
719 | (fragP->fr_opcode)[0] = value; | |
720 | } | |
721 | else | |
722 | { | |
723 | /* Word or dword displacement. */ | |
724 | int pow2_of_size = 1; | |
725 | char *writep; | |
726 | ||
727 | if (value < -32768 || value > 32767) | |
728 | { | |
729 | /* Outside word range, make it a dword. */ | |
730 | pow2_of_size = 2; | |
731 | } | |
732 | ||
733 | /* Modify the byte-offset BDAP into a word or dword offset | |
734 | BDAP. Or really, a BDAP rX,8bit into a | |
07e90ad5 | 735 | BDAP.[wd] rX,[PC+] followed by a word or dword. */ |
3bcbcc3d HPN |
736 | (fragP->fr_opcode)[0] = BDAP_PC_LOW + pow2_of_size * 16; |
737 | ||
738 | /* Keep the register number in the highest four bits. */ | |
739 | (fragP->fr_opcode)[1] &= 0xF0; | |
740 | (fragP->fr_opcode)[1] |= BDAP_INCR_HIGH; | |
741 | ||
47926f60 | 742 | /* It grew by two or four bytes. */ |
3bcbcc3d HPN |
743 | fragP->fr_fix += 1 << pow2_of_size; |
744 | writep = fragP->fr_literal + old_fr_fix; | |
745 | md_number_to_chars (writep, value, 1 << pow2_of_size); | |
746 | } | |
747 | frag_wane (fragP); | |
748 | } | |
749 | break; | |
750 | ||
ae57792d HPN |
751 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_BYTE): |
752 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_WORD): | |
753 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD): | |
754 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_BYTE): | |
755 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_WORD): | |
756 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD): | |
757 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_BYTE): | |
758 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_WORD): | |
759 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD): | |
760 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_BYTE): | |
761 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_WORD): | |
762 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD): | |
763 | case ENCODE_RELAX (STATE_LAPC, STATE_BYTE): | |
764 | case ENCODE_RELAX (STATE_LAPC, STATE_DWORD): | |
c335d394 HPN |
765 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): |
766 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): | |
93c2a809 AM |
767 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): |
768 | /* When relaxing a section for the second time, we don't need to | |
c335d394 HPN |
769 | do anything except making sure that fr_var is set right. */ |
770 | fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; | |
93c2a809 AM |
771 | break; |
772 | ||
1048a9ba HPN |
773 | case ENCODE_RELAX (STATE_MUL, STATE_BYTE): |
774 | /* Nothing to do here. */ | |
775 | break; | |
776 | ||
3bcbcc3d HPN |
777 | default: |
778 | BAD_CASE (fragP->fr_subtype); | |
779 | } | |
780 | ||
781 | return fragP->fr_var + (fragP->fr_fix - old_fr_fix); | |
782 | } | |
783 | ||
3bcbcc3d HPN |
784 | /* Perform post-processing of machine-dependent frags after relaxation. |
785 | Called after relaxation is finished. | |
786 | In: Address of frag. | |
787 | fr_type == rs_machine_dependent. | |
788 | fr_subtype is what the address relaxed to. | |
789 | ||
790 | Out: Any fixS:s and constants are set up. | |
791 | ||
792 | The caller will turn the frag into a ".space 0". */ | |
793 | ||
794 | void | |
795 | md_convert_frag (abfd, sec, fragP) | |
796 | bfd *abfd ATTRIBUTE_UNUSED; | |
797 | segT sec ATTRIBUTE_UNUSED; | |
798 | fragS *fragP; | |
799 | { | |
47926f60 | 800 | /* Pointer to first byte in variable-sized part of the frag. */ |
3bcbcc3d HPN |
801 | char *var_partp; |
802 | ||
803 | /* Pointer to first opcode byte in frag. */ | |
804 | char *opcodep; | |
805 | ||
806 | /* Used to check integrity of the relaxation. | |
807 | One of 2 = long, 1 = word, or 0 = byte. */ | |
808 | int length_code; | |
809 | ||
810 | /* Size in bytes of variable-sized part of frag. */ | |
811 | int var_part_size = 0; | |
812 | ||
813 | /* This is part of *fragP. It contains all information about addresses | |
814 | and offsets to varying parts. */ | |
815 | symbolS *symbolP; | |
816 | unsigned long var_part_offset; | |
817 | ||
818 | /* Where, in file space, is _var of *fragP? */ | |
819 | unsigned long address_of_var_part = 0; | |
820 | ||
821 | /* Where, in file space, does addr point? */ | |
822 | unsigned long target_address; | |
823 | ||
824 | know (fragP->fr_type == rs_machine_dependent); | |
825 | ||
826 | length_code = fragP->fr_subtype & STATE_LENGTH_MASK; | |
827 | know (length_code >= 0 && length_code < STATE_MAX_LENGTH); | |
828 | ||
829 | var_part_offset = fragP->fr_fix; | |
830 | var_partp = fragP->fr_literal + var_part_offset; | |
831 | opcodep = fragP->fr_opcode; | |
832 | ||
833 | symbolP = fragP->fr_symbol; | |
ac62c346 | 834 | target_address = (symbolP ? S_GET_VALUE (symbolP) : 0) + fragP->fr_offset; |
3bcbcc3d HPN |
835 | address_of_var_part = fragP->fr_address + var_part_offset; |
836 | ||
837 | switch (fragP->fr_subtype) | |
47926f60 | 838 | { |
ae57792d HPN |
839 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_BYTE): |
840 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_BYTE): | |
841 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_BYTE): | |
842 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_BYTE): | |
47926f60 KH |
843 | opcodep[0] = branch_disp ((target_address - address_of_var_part)); |
844 | var_part_size = 0; | |
845 | break; | |
3bcbcc3d | 846 | |
ae57792d HPN |
847 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_WORD): |
848 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_WORD): | |
849 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_WORD): | |
850 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_WORD): | |
47926f60 KH |
851 | /* We had a quick immediate branch, now turn it into a word one i.e. a |
852 | PC autoincrement. */ | |
853 | opcodep[0] = BRANCH_PC_LOW; | |
854 | opcodep[1] &= 0xF0; | |
855 | opcodep[1] |= BRANCH_INCR_HIGH; | |
856 | md_number_to_chars (var_partp, | |
ae57792d HPN |
857 | (long) |
858 | (target_address | |
859 | - (address_of_var_part | |
860 | + (cris_arch == arch_crisv32 | |
861 | || cris_arch == arch_cris_common_v10_v32 | |
862 | ? -2 : 2))), | |
47926f60 KH |
863 | 2); |
864 | var_part_size = 2; | |
865 | break; | |
866 | ||
ae57792d | 867 | case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD): |
47926f60 KH |
868 | gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP, |
869 | fragP->fr_symbol, (symbolS *) NULL, | |
870 | fragP->fr_offset); | |
871 | /* Ten bytes added: a branch, nop and a jump. */ | |
872 | var_part_size = 2 + 2 + 4 + 2; | |
873 | break; | |
3bcbcc3d | 874 | |
ae57792d HPN |
875 | case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD): |
876 | gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP, | |
877 | fragP->fr_symbol, (symbolS *) NULL, | |
878 | fragP->fr_offset); | |
879 | /* Twelve bytes added: a branch, nop and another branch and nop. */ | |
880 | var_part_size = 2 + 2 + 2 + 4 + 2; | |
881 | break; | |
882 | ||
883 | case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD): | |
884 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
885 | _("Relaxation to long branches for .arch common_v10_v32\ | |
886 | not implemented")); | |
887 | /* Pretend we have twelve bytes for sake of quelling further | |
888 | errors. */ | |
889 | var_part_size = 2 + 2 + 2 + 4 + 2; | |
890 | break; | |
891 | ||
892 | case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD): | |
893 | /* We had a quick immediate branch or a word immediate ba. Now | |
894 | turn it into a dword one. */ | |
895 | opcodep[0] = BA_DWORD_OPCODE & 255; | |
896 | opcodep[1] = (BA_DWORD_OPCODE >> 8) & 255; | |
897 | fix_new (fragP, var_partp - fragP->fr_literal, 4, symbolP, | |
898 | fragP->fr_offset + 6, 1, BFD_RELOC_32_PCREL); | |
899 | var_part_size = 4; | |
900 | break; | |
901 | ||
902 | case ENCODE_RELAX (STATE_LAPC, STATE_BYTE): | |
903 | { | |
904 | long offset = target_address - (address_of_var_part - 2); | |
905 | ||
906 | /* This is mostly a sanity check; useful occurrences (if there | |
907 | really are any) should have been caught in | |
908 | md_estimate_size_before_relax. We can (at least | |
909 | theoretically) stumble over invalid code with odd sizes and | |
910 | .p2aligns within the code, so emit an error if that happens. | |
911 | (The generic relaxation machinery is not fit to check this.) */ | |
912 | ||
913 | if (offset & 1) | |
914 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
915 | _("Complicated LAPC target operand is not\ | |
916 | a multiple of two. Use LAPC.D")); | |
917 | ||
918 | /* FIXME: This *is* a sanity check. Remove when done with. */ | |
919 | if (offset > 15*2 || offset < 0) | |
920 | as_fatal (_("Internal error found in md_convert_frag: offset %ld.\ | |
921 | Please report this."), | |
922 | offset); | |
923 | ||
924 | opcodep[0] |= (offset / 2) & 0xf; | |
925 | var_part_size = 0; | |
926 | } | |
927 | break; | |
928 | ||
929 | case ENCODE_RELAX (STATE_LAPC, STATE_DWORD): | |
930 | { | |
931 | md_number_to_chars (opcodep, | |
932 | LAPC_DWORD_OPCODE + (opcodep[1] & 0xf0) * 256, | |
933 | 2); | |
934 | /* Remember that the reloc is against the position *after* the | |
935 | relocated contents, so we need to adjust to the start of | |
936 | the insn. */ | |
937 | fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol, | |
938 | fragP->fr_offset + 6, 1, BFD_RELOC_32_PCREL); | |
939 | var_part_size = 4; | |
940 | } | |
941 | break; | |
942 | ||
47926f60 | 943 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): |
1c971160 HPN |
944 | if (symbolP == NULL) |
945 | as_fatal (_("internal inconsistency in %s: bdapq no symbol"), | |
946 | __FUNCTION__); | |
947 | opcodep[0] = S_GET_VALUE (symbolP); | |
47926f60 KH |
948 | var_part_size = 0; |
949 | break; | |
950 | ||
951 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): | |
952 | /* We had a BDAP 8-bit "quick immediate", now turn it into a 16-bit | |
953 | one that uses PC autoincrement. */ | |
954 | opcodep[0] = BDAP_PC_LOW + (1 << 4); | |
955 | opcodep[1] &= 0xF0; | |
956 | opcodep[1] |= BDAP_INCR_HIGH; | |
1c971160 HPN |
957 | if (symbolP == NULL) |
958 | as_fatal (_("internal inconsistency in %s: bdap.w with no symbol"), | |
959 | __FUNCTION__); | |
960 | md_number_to_chars (var_partp, S_GET_VALUE (symbolP), 2); | |
47926f60 KH |
961 | var_part_size = 2; |
962 | break; | |
963 | ||
964 | case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): | |
965 | /* We had a BDAP 16-bit "word", change the offset to a dword. */ | |
966 | opcodep[0] = BDAP_PC_LOW + (2 << 4); | |
967 | opcodep[1] &= 0xF0; | |
968 | opcodep[1] |= BDAP_INCR_HIGH; | |
969 | if (fragP->fr_symbol == NULL) | |
970 | md_number_to_chars (var_partp, fragP->fr_offset, 4); | |
971 | else | |
972 | fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol, | |
973 | fragP->fr_offset, 0, BFD_RELOC_32); | |
974 | var_part_size = 4; | |
975 | break; | |
976 | ||
1048a9ba HPN |
977 | case ENCODE_RELAX (STATE_MUL, STATE_BYTE): |
978 | /* This is the only time we check position and aligmnent of the | |
979 | placement-tracking frag. */ | |
980 | if (sec->alignment_power < 2) | |
981 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
982 | _("section alignment must be >= 4 bytes to check MULS/MULU safeness")); | |
983 | else | |
984 | { | |
985 | /* If the address after the MULS/MULU has alignment which is | |
986 | that of the section and may be that of a cache-size of the | |
987 | buggy versions, then the MULS/MULU can be placed badly. */ | |
988 | if ((address_of_var_part | |
989 | & ((1 << sec->alignment_power) - 1) & 31) == 0) | |
990 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
991 | _("dangerous MULS/MULU location; give it higher alignment")); | |
992 | } | |
993 | break; | |
994 | ||
47926f60 KH |
995 | default: |
996 | BAD_CASE (fragP->fr_subtype); | |
997 | break; | |
998 | } | |
999 | ||
1000 | fragP->fr_fix += var_part_size; | |
3bcbcc3d HPN |
1001 | } |
1002 | ||
1003 | /* Generate a short jump around a secondary jump table. | |
1004 | Used by md_create_long_jump. | |
1005 | ||
1006 | This used to be md_create_short_jump, but is now called from | |
ae57792d HPN |
1007 | md_create_long_jump instead, when sufficient, since the sizes of the |
1008 | jumps are the same for pre-v32. */ | |
3bcbcc3d HPN |
1009 | |
1010 | static void | |
1011 | cris_create_short_jump (storep, from_addr, to_addr, fragP, to_symbol) | |
1012 | char *storep; | |
1013 | addressT from_addr; | |
1014 | addressT to_addr; | |
1015 | fragS *fragP ATTRIBUTE_UNUSED; | |
1016 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
1017 | { | |
1018 | long int distance; | |
1019 | ||
ae57792d HPN |
1020 | /* See md_create_long_jump about the comment on the "+ 2". */ |
1021 | long int max_minimal_minus_distance; | |
1022 | long int max_minimal_plus_distance; | |
1023 | int nop_opcode; | |
1024 | ||
1025 | if (cris_arch == arch_crisv32) | |
1026 | { | |
1027 | max_minimal_minus_distance = BRANCH_BB_V32 + 2; | |
1028 | max_minimal_plus_distance = BRANCH_BF_V32 + 2; | |
1029 | nop_opcode = NOP_OPCODE_V32; | |
1030 | } | |
1031 | else | |
1032 | { | |
1033 | max_minimal_minus_distance = BRANCH_BB + 2; | |
1034 | max_minimal_plus_distance = BRANCH_BF + 2; | |
1035 | nop_opcode = NOP_OPCODE; | |
1036 | } | |
1037 | ||
3bcbcc3d HPN |
1038 | distance = to_addr - from_addr; |
1039 | ||
ae57792d HPN |
1040 | if (max_minimal_minus_distance <= distance |
1041 | && distance <= max_minimal_plus_distance) | |
3bcbcc3d HPN |
1042 | { |
1043 | /* Create a "short" short jump: "BA distance - 2". */ | |
47926f60 | 1044 | storep[0] = branch_disp (distance - 2); |
3bcbcc3d HPN |
1045 | storep[1] = BA_QUICK_HIGH; |
1046 | ||
1047 | /* A nop for the delay slot. */ | |
ae57792d | 1048 | md_number_to_chars (storep + 2, nop_opcode, 2); |
3bcbcc3d HPN |
1049 | |
1050 | /* The extra word should be filled with something sane too. Make it | |
1051 | a nop to keep disassembly sane. */ | |
ae57792d | 1052 | md_number_to_chars (storep + 4, nop_opcode, 2); |
3bcbcc3d HPN |
1053 | } |
1054 | else | |
1055 | { | |
1056 | /* Make it a "long" short jump: "BA (PC+)". */ | |
1057 | md_number_to_chars (storep, BA_PC_INCR_OPCODE, 2); | |
1058 | ||
47926f60 | 1059 | /* ".WORD distance - 4". */ |
ae57792d HPN |
1060 | md_number_to_chars (storep + 2, |
1061 | (long) (distance - 4 | |
1062 | - (cris_arch == arch_crisv32 | |
1063 | ? -4 : 0)), | |
1064 | 2); | |
3bcbcc3d HPN |
1065 | |
1066 | /* A nop for the delay slot. */ | |
ae57792d | 1067 | md_number_to_chars (storep + 4, nop_opcode, 2); |
3bcbcc3d HPN |
1068 | } |
1069 | } | |
1070 | ||
3bcbcc3d HPN |
1071 | /* Generate a long jump in a secondary jump table. |
1072 | ||
1073 | storep Where to store the jump instruction. | |
1074 | from_addr Address of the jump instruction. | |
1075 | to_addr Destination address of the jump. | |
1076 | fragP Which frag the destination address operand | |
1077 | lies in. | |
1078 | to_symbol Destination symbol. */ | |
1079 | ||
1080 | void | |
1081 | md_create_long_jump (storep, from_addr, to_addr, fragP, to_symbol) | |
1082 | char *storep; | |
1083 | addressT from_addr; | |
1084 | addressT to_addr; | |
1085 | fragS *fragP; | |
1086 | symbolS *to_symbol; | |
1087 | { | |
1088 | long int distance; | |
1089 | ||
ae57792d HPN |
1090 | /* FIXME: What's that "+ 3"? It comes from the magic numbers that |
1091 | used to be here, it's just translated to the limit macros used in | |
1092 | the relax table. But why + 3? */ | |
1093 | long int max_short_minus_distance | |
1094 | = cris_arch != arch_crisv32 ? BRANCH_WB + 3 : BRANCH_WB_V32 + 3; | |
1095 | ||
1096 | long int max_short_plus_distance | |
1097 | = cris_arch != arch_crisv32 ? BRANCH_WF + 3 : BRANCH_WF_V32 + 3; | |
1098 | ||
1099 | /* Bail out for compatibility mode. (It seems it can be implemented, | |
1100 | perhaps with a 10-byte sequence: "move.d NNNN,$pc/$acr", "jump | |
1101 | $acr", "nop"; but doesn't seem worth it at the moment.) */ | |
1102 | if (cris_arch == arch_cris_common_v10_v32) | |
1103 | as_fatal (_("Out-of-range .word offset handling\ | |
1104 | is not implemented for .arch common_v10_v32")); | |
1105 | ||
3bcbcc3d HPN |
1106 | distance = to_addr - from_addr; |
1107 | ||
ae57792d HPN |
1108 | if (max_short_minus_distance <= distance |
1109 | && distance <= max_short_plus_distance) | |
1110 | /* Then make it a "short" long jump. */ | |
1111 | cris_create_short_jump (storep, from_addr, to_addr, fragP, | |
1112 | to_symbol); | |
3bcbcc3d HPN |
1113 | else |
1114 | { | |
ae57792d HPN |
1115 | /* We have a "long" long jump: "JUMP [PC+]". If CRISv32, always |
1116 | make it a BA. Else make it an "ADD [PC+],PC" if we're supposed | |
1117 | to emit PIC code. */ | |
08caf3f8 | 1118 | md_number_to_chars (storep, |
ae57792d HPN |
1119 | cris_arch == arch_crisv32 |
1120 | ? BA_DWORD_OPCODE | |
1121 | : (pic ? ADD_PC_INCR_OPCODE : JUMP_PC_INCR_OPCODE), | |
1122 | 2); | |
3bcbcc3d | 1123 | |
08caf3f8 | 1124 | /* Follow with a ".DWORD to_addr", PC-relative for PIC. */ |
3bcbcc3d | 1125 | fix_new (fragP, storep + 2 - fragP->fr_literal, 4, to_symbol, |
ae57792d HPN |
1126 | cris_arch == arch_crisv32 ? 6 : 0, |
1127 | cris_arch == arch_crisv32 || pic ? 1 : 0, | |
1128 | cris_arch == arch_crisv32 || pic | |
1129 | ? BFD_RELOC_32_PCREL : BFD_RELOC_32); | |
1130 | ||
1131 | /* Follow it with a "NOP" for CRISv32. */ | |
1132 | if (cris_arch == arch_crisv32) | |
1133 | md_number_to_chars (storep + 6, NOP_OPCODE_V32, 2); | |
3bcbcc3d HPN |
1134 | } |
1135 | } | |
1136 | ||
ed67db7a HPN |
1137 | /* Allocate space for the first piece of an insn, and mark it as the |
1138 | start of the insn for debug-format use. */ | |
1139 | ||
1140 | static char * | |
1141 | cris_insn_first_word_frag () | |
1142 | { | |
1143 | char *insnp = frag_more (2); | |
1144 | ||
1145 | /* We need to mark the start of the insn by passing dwarf2_emit_insn | |
1146 | the offset from the current fragment position. This must be done | |
1147 | after the first fragment is created but before any other fragments | |
1148 | (fixed or varying) are created. Note that the offset only | |
1149 | corresponds to the "size" of the insn for a fixed-size, | |
1150 | non-expanded insn. */ | |
1151 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1152 | dwarf2_emit_insn (2); | |
1153 | ||
1154 | return insnp; | |
1155 | } | |
1156 | ||
3bcbcc3d | 1157 | /* Port-specific assembler initialization. */ |
47926f60 | 1158 | |
3bcbcc3d HPN |
1159 | void |
1160 | md_begin () | |
1161 | { | |
1162 | const char *hashret = NULL; | |
1163 | int i = 0; | |
1164 | ||
47926f60 | 1165 | /* Set up a hash table for the instructions. */ |
3bcbcc3d HPN |
1166 | op_hash = hash_new (); |
1167 | if (op_hash == NULL) | |
1168 | as_fatal (_("Virtual memory exhausted")); | |
1169 | ||
ae57792d HPN |
1170 | /* Enable use of ".if ..asm.arch.cris.v32" |
1171 | and ".if ..asm.arch.cris.common_v10_v32" and a few others. */ | |
1172 | symbol_table_insert (symbol_new ("..asm.arch.cris.v32", absolute_section, | |
1173 | (cris_arch == arch_crisv32), | |
1174 | &zero_address_frag)); | |
1175 | symbol_table_insert (symbol_new ("..asm.arch.cris.v10", absolute_section, | |
1176 | (cris_arch == arch_crisv10), | |
1177 | &zero_address_frag)); | |
1178 | symbol_table_insert (symbol_new ("..asm.arch.cris.common_v10_v32", | |
1179 | absolute_section, | |
1180 | (cris_arch == arch_cris_common_v10_v32), | |
1181 | &zero_address_frag)); | |
1182 | symbol_table_insert (symbol_new ("..asm.arch.cris.any_v0_v10", | |
1183 | absolute_section, | |
1184 | (cris_arch == arch_cris_any_v0_v10), | |
1185 | &zero_address_frag)); | |
1186 | ||
3bcbcc3d HPN |
1187 | while (cris_opcodes[i].name != NULL) |
1188 | { | |
1189 | const char *name = cris_opcodes[i].name; | |
ae57792d HPN |
1190 | |
1191 | if (! cris_insn_ver_valid_for_arch (cris_opcodes[i].applicable_version, | |
1192 | cris_arch)) | |
1193 | { | |
1194 | i++; | |
1195 | continue; | |
1196 | } | |
1197 | ||
3bcbcc3d HPN |
1198 | hashret = hash_insert (op_hash, name, (PTR) &cris_opcodes[i]); |
1199 | ||
1200 | if (hashret != NULL && *hashret != '\0') | |
1201 | as_fatal (_("Can't hash `%s': %s\n"), cris_opcodes[i].name, | |
47926f60 | 1202 | *hashret == 0 ? _("(unknown reason)") : hashret); |
3bcbcc3d HPN |
1203 | do |
1204 | { | |
1205 | if (cris_opcodes[i].match & cris_opcodes[i].lose) | |
1206 | as_fatal (_("Buggy opcode: `%s' \"%s\"\n"), cris_opcodes[i].name, | |
1207 | cris_opcodes[i].args); | |
1208 | ||
1209 | ++i; | |
47926f60 KH |
1210 | } |
1211 | while (cris_opcodes[i].name != NULL | |
1212 | && strcmp (cris_opcodes[i].name, name) == 0); | |
3bcbcc3d HPN |
1213 | } |
1214 | } | |
1215 | ||
3bcbcc3d | 1216 | /* Assemble a source line. */ |
47926f60 | 1217 | |
3bcbcc3d HPN |
1218 | void |
1219 | md_assemble (str) | |
1220 | char *str; | |
1221 | { | |
1222 | struct cris_instruction output_instruction; | |
1223 | struct cris_prefix prefix; | |
1224 | char *opcodep; | |
1225 | char *p; | |
1226 | ||
1227 | know (str); | |
1228 | ||
1229 | /* Do the low-level grunt - assemble to bits and split up into a prefix | |
1230 | and ordinary insn. */ | |
1231 | cris_process_instruction (str, &output_instruction, &prefix); | |
1232 | ||
1233 | /* Handle any prefixes to the instruction. */ | |
1234 | switch (prefix.kind) | |
1235 | { | |
1236 | case PREFIX_NONE: | |
1237 | break; | |
1238 | ||
1239 | /* When the expression is unknown for a BDAP, it can need 0, 2 or 4 | |
1240 | extra bytes, so we handle it separately. */ | |
1241 | case PREFIX_BDAP_IMM: | |
08caf3f8 HPN |
1242 | /* We only do it if the relocation is unspecified, i.e. not a PIC |
1243 | relocation. */ | |
1244 | if (prefix.reloc == BFD_RELOC_NONE) | |
1245 | { | |
1246 | gen_bdap (prefix.base_reg_number, &prefix.expr); | |
1247 | break; | |
1248 | } | |
1249 | /* Fall through. */ | |
3bcbcc3d HPN |
1250 | case PREFIX_BDAP: |
1251 | case PREFIX_BIAP: | |
1252 | case PREFIX_DIP: | |
ed67db7a | 1253 | opcodep = cris_insn_first_word_frag (); |
3bcbcc3d HPN |
1254 | |
1255 | /* Output the prefix opcode. */ | |
1256 | md_number_to_chars (opcodep, (long) prefix.opcode, 2); | |
1257 | ||
08caf3f8 HPN |
1258 | /* Having a specified reloc only happens for DIP and for BDAP with |
1259 | PIC operands, but it is ok to drop through here for the other | |
1260 | prefixes as they can have no relocs specified. */ | |
3bcbcc3d HPN |
1261 | if (prefix.reloc != BFD_RELOC_NONE) |
1262 | { | |
08caf3f8 HPN |
1263 | unsigned int relocsize |
1264 | = (prefix.kind == PREFIX_DIP | |
1265 | ? 4 : cris_get_pic_reloc_size (prefix.reloc)); | |
1266 | ||
08caf3f8 HPN |
1267 | p = frag_more (relocsize); |
1268 | fix_new_exp (frag_now, (p - frag_now->fr_literal), relocsize, | |
3bcbcc3d HPN |
1269 | &prefix.expr, 0, prefix.reloc); |
1270 | } | |
1271 | break; | |
1272 | ||
1273 | case PREFIX_PUSH: | |
ed67db7a | 1274 | opcodep = cris_insn_first_word_frag (); |
3bcbcc3d HPN |
1275 | |
1276 | /* Output the prefix opcode. Being a "push", we add the negative | |
1277 | size of the register to "sp". */ | |
1278 | if (output_instruction.spec_reg != NULL) | |
1279 | { | |
47926f60 | 1280 | /* Special register. */ |
3bcbcc3d HPN |
1281 | opcodep[0] = -output_instruction.spec_reg->reg_size; |
1282 | } | |
1283 | else | |
1284 | { | |
47926f60 | 1285 | /* General register. */ |
3bcbcc3d HPN |
1286 | opcodep[0] = -4; |
1287 | } | |
1288 | opcodep[1] = (REG_SP << 4) + (BDAP_QUICK_OPCODE >> 8); | |
1289 | break; | |
1290 | ||
1291 | default: | |
1292 | BAD_CASE (prefix.kind); | |
1293 | } | |
1294 | ||
1295 | /* If we only had a prefix insn, we're done. */ | |
1296 | if (output_instruction.insn_type == CRIS_INSN_NONE) | |
1297 | return; | |
1298 | ||
1299 | /* Done with the prefix. Continue with the main instruction. */ | |
ed67db7a HPN |
1300 | if (prefix.kind == PREFIX_NONE) |
1301 | opcodep = cris_insn_first_word_frag (); | |
1302 | else | |
1303 | opcodep = frag_more (2); | |
3bcbcc3d HPN |
1304 | |
1305 | /* Output the instruction opcode. */ | |
47926f60 | 1306 | md_number_to_chars (opcodep, (long) (output_instruction.opcode), 2); |
3bcbcc3d HPN |
1307 | |
1308 | /* Output the symbol-dependent instruction stuff. */ | |
1309 | if (output_instruction.insn_type == CRIS_INSN_BRANCH) | |
1310 | { | |
1311 | segT to_seg = absolute_section; | |
1312 | int is_undefined = 0; | |
1313 | int length_code; | |
1314 | ||
1315 | if (output_instruction.expr.X_op != O_constant) | |
1316 | { | |
1317 | to_seg = S_GET_SEGMENT (output_instruction.expr.X_add_symbol); | |
1318 | ||
1319 | if (to_seg == undefined_section) | |
1320 | is_undefined = 1; | |
1321 | } | |
1322 | ||
ae57792d HPN |
1323 | if (to_seg == now_seg || is_undefined |
1324 | /* In CRISv32, there *is* a 32-bit absolute branch, so don't | |
1325 | emit the 12-byte sequence for known symbols in other | |
1326 | segments. */ | |
1327 | || (cris_arch == arch_crisv32 | |
1328 | && output_instruction.opcode == BA_QUICK_OPCODE)) | |
3bcbcc3d | 1329 | { |
08caf3f8 HPN |
1330 | /* Handle complex expressions. */ |
1331 | valueT addvalue | |
1c971160 HPN |
1332 | = (SIMPLE_EXPR (&output_instruction.expr) |
1333 | ? output_instruction.expr.X_add_number | |
1334 | : 0); | |
08caf3f8 | 1335 | symbolS *sym |
1c971160 HPN |
1336 | = (SIMPLE_EXPR (&output_instruction.expr) |
1337 | ? output_instruction.expr.X_add_symbol | |
1338 | : make_expr_symbol (&output_instruction.expr)); | |
08caf3f8 | 1339 | |
ae57792d HPN |
1340 | /* If is_undefined, the expression may still become now_seg. |
1341 | That case is handled by md_estimate_size_before_relax. */ | |
1342 | length_code = to_seg == now_seg ? STATE_BYTE : STATE_UNDF; | |
1343 | ||
1344 | /* Make room for max twelve bytes of variable length for v32 mode, | |
1345 | ten for v10 and older. */ | |
1346 | frag_var (rs_machine_dependent, | |
1347 | (cris_arch == arch_crisv32 | |
1348 | || cris_arch == arch_cris_common_v10_v32) ? 12 : 10, 0, | |
1349 | ENCODE_RELAX (cris_arch == arch_crisv32 | |
1350 | ? (output_instruction.opcode | |
1351 | == BA_QUICK_OPCODE | |
1352 | ? STATE_ABS_BRANCH_V32 | |
1353 | : STATE_COND_BRANCH_V32) | |
1354 | : (cris_arch == arch_cris_common_v10_v32 | |
1355 | ? STATE_COND_BRANCH_COMMON | |
1356 | : STATE_COND_BRANCH), | |
1357 | length_code), | |
08caf3f8 | 1358 | sym, addvalue, opcodep); |
3bcbcc3d HPN |
1359 | } |
1360 | else | |
1361 | { | |
1362 | /* We have: to_seg != now_seg && to_seg != undefined_section. | |
1363 | This means it is a branch to a known symbol in another | |
fb2fd3e1 | 1364 | section, perhaps an absolute address. Emit a 32-bit branch. */ |
ae57792d HPN |
1365 | char *cond_jump |
1366 | = frag_more ((cris_arch == arch_crisv32 | |
1367 | || cris_arch == arch_cris_common_v10_v32) | |
1368 | ? 12 : 10); | |
08caf3f8 | 1369 | |
08caf3f8 | 1370 | gen_cond_branch_32 (opcodep, cond_jump, frag_now, |
3bcbcc3d | 1371 | output_instruction.expr.X_add_symbol, |
47926f60 | 1372 | (symbolS *) NULL, |
3bcbcc3d HPN |
1373 | output_instruction.expr.X_add_number); |
1374 | } | |
1375 | } | |
1048a9ba HPN |
1376 | else if (output_instruction.insn_type == CRIS_INSN_MUL |
1377 | && err_for_dangerous_mul_placement) | |
1378 | /* Create a frag which which we track the location of the mul insn | |
1379 | (in the last two bytes before the mul-frag). */ | |
1380 | frag_variant (rs_machine_dependent, 0, 0, | |
1381 | ENCODE_RELAX (STATE_MUL, STATE_BYTE), | |
1382 | NULL, 0, opcodep); | |
3bcbcc3d HPN |
1383 | else |
1384 | { | |
1385 | if (output_instruction.imm_oprnd_size > 0) | |
1386 | { | |
2d2255b5 | 1387 | /* The instruction has an immediate operand. */ |
08caf3f8 | 1388 | enum bfd_reloc_code_real reloc = BFD_RELOC_NONE; |
3bcbcc3d HPN |
1389 | |
1390 | switch (output_instruction.imm_oprnd_size) | |
1391 | { | |
1392 | /* Any byte-size immediate constants are treated as | |
1393 | word-size. FIXME: Thus overflow check does not work | |
1394 | correctly. */ | |
1395 | ||
1396 | case 2: | |
08caf3f8 HPN |
1397 | /* Note that size-check for the explicit reloc has already |
1398 | been done when we get here. */ | |
1399 | if (output_instruction.reloc != BFD_RELOC_NONE) | |
1400 | reloc = output_instruction.reloc; | |
1401 | else | |
1402 | reloc = BFD_RELOC_16; | |
3bcbcc3d HPN |
1403 | break; |
1404 | ||
1405 | case 4: | |
08caf3f8 HPN |
1406 | /* Allow a relocation specified in the operand. */ |
1407 | if (output_instruction.reloc != BFD_RELOC_NONE) | |
1408 | reloc = output_instruction.reloc; | |
1409 | else | |
1410 | reloc = BFD_RELOC_32; | |
3bcbcc3d HPN |
1411 | break; |
1412 | ||
1413 | default: | |
1414 | BAD_CASE (output_instruction.imm_oprnd_size); | |
1415 | } | |
1416 | ||
1417 | p = frag_more (output_instruction.imm_oprnd_size); | |
1418 | fix_new_exp (frag_now, (p - frag_now->fr_literal), | |
1419 | output_instruction.imm_oprnd_size, | |
ae57792d HPN |
1420 | &output_instruction.expr, |
1421 | reloc == BFD_RELOC_32_PCREL | |
1422 | || reloc == BFD_RELOC_16_PCREL | |
1423 | || reloc == BFD_RELOC_8_PCREL, reloc); | |
1424 | } | |
1425 | else if (output_instruction.reloc == BFD_RELOC_CRIS_LAPCQ_OFFSET | |
1426 | && output_instruction.expr.X_md != 0) | |
1427 | { | |
1428 | /* Handle complex expressions. */ | |
1429 | valueT addvalue | |
1430 | = (output_instruction.expr.X_op_symbol != NULL | |
1431 | ? 0 : output_instruction.expr.X_add_number); | |
1432 | symbolS *sym | |
1433 | = (output_instruction.expr.X_op_symbol != NULL | |
1434 | ? make_expr_symbol (&output_instruction.expr) | |
1435 | : output_instruction.expr.X_add_symbol); | |
1436 | ||
1437 | /* This is a relaxing construct, so we need a frag_var rather | |
1438 | than the fix_new_exp call below. */ | |
1439 | frag_var (rs_machine_dependent, | |
1440 | 4, 0, | |
1441 | ENCODE_RELAX (STATE_LAPC, STATE_UNDF), | |
1442 | sym, addvalue, opcodep); | |
3bcbcc3d HPN |
1443 | } |
1444 | else if (output_instruction.reloc != BFD_RELOC_NONE) | |
1445 | { | |
1446 | /* An immediate operand that has a relocation and needs to be | |
47926f60 | 1447 | processed further. */ |
3bcbcc3d HPN |
1448 | |
1449 | /* It is important to use fix_new_exp here and everywhere else | |
1450 | (and not fix_new), as fix_new_exp can handle "difference | |
1451 | expressions" - where the expression contains a difference of | |
1452 | two symbols in the same segment. */ | |
1453 | fix_new_exp (frag_now, (opcodep - frag_now->fr_literal), 2, | |
ae57792d HPN |
1454 | &output_instruction.expr, |
1455 | output_instruction.reloc == BFD_RELOC_32_PCREL | |
1456 | || output_instruction.reloc == BFD_RELOC_16_PCREL | |
1457 | || output_instruction.reloc == BFD_RELOC_8_PCREL | |
1458 | || (output_instruction.reloc | |
1459 | == BFD_RELOC_CRIS_LAPCQ_OFFSET), | |
3bcbcc3d HPN |
1460 | output_instruction.reloc); |
1461 | } | |
1462 | } | |
1463 | } | |
1464 | ||
3bcbcc3d | 1465 | /* Low level text-to-bits assembly. */ |
47926f60 | 1466 | |
3bcbcc3d HPN |
1467 | static void |
1468 | cris_process_instruction (insn_text, out_insnp, prefixp) | |
1469 | char *insn_text; | |
47926f60 | 1470 | struct cris_instruction *out_insnp; |
3bcbcc3d HPN |
1471 | struct cris_prefix *prefixp; |
1472 | { | |
47926f60 KH |
1473 | char *s; |
1474 | char modified_char = 0; | |
1475 | const char *args; | |
3bcbcc3d | 1476 | struct cris_opcode *instruction; |
47926f60 KH |
1477 | char *operands; |
1478 | int match = 0; | |
1479 | int mode; | |
1480 | int regno; | |
1481 | int size_bits; | |
3bcbcc3d HPN |
1482 | |
1483 | /* Reset these fields to a harmless state in case we need to return in | |
1484 | error. */ | |
1485 | prefixp->kind = PREFIX_NONE; | |
1486 | prefixp->reloc = BFD_RELOC_NONE; | |
ae57792d | 1487 | out_insnp->insn_type = CRIS_INSN_NONE; |
3bcbcc3d HPN |
1488 | out_insnp->imm_oprnd_size = 0; |
1489 | ||
1490 | /* Find the end of the opcode mnemonic. We assume (true in 2.9.1) | |
1491 | that the caller has translated the opcode to lower-case, up to the | |
47926f60 | 1492 | first non-letter. */ |
3882b010 | 1493 | for (operands = insn_text; ISLOWER (*operands); ++operands) |
3bcbcc3d HPN |
1494 | ; |
1495 | ||
1496 | /* Terminate the opcode after letters, but save the character there if | |
1497 | it was of significance. */ | |
1498 | switch (*operands) | |
1499 | { | |
1500 | case '\0': | |
1501 | break; | |
1502 | ||
1503 | case '.': | |
47926f60 | 1504 | /* Put back the modified character later. */ |
3bcbcc3d | 1505 | modified_char = *operands; |
47926f60 | 1506 | /* Fall through. */ |
3bcbcc3d HPN |
1507 | |
1508 | case ' ': | |
47926f60 KH |
1509 | /* Consume the character after the mnemonic |
1510 | and replace it with '\0'. */ | |
3bcbcc3d HPN |
1511 | *operands++ = '\0'; |
1512 | break; | |
1513 | ||
1514 | default: | |
1515 | as_bad (_("Unknown opcode: `%s'"), insn_text); | |
1516 | return; | |
1517 | } | |
1518 | ||
1519 | /* Find the instruction. */ | |
1520 | instruction = (struct cris_opcode *) hash_find (op_hash, insn_text); | |
1521 | if (instruction == NULL) | |
1522 | { | |
1523 | as_bad (_("Unknown opcode: `%s'"), insn_text); | |
1524 | return; | |
1525 | } | |
1526 | ||
1527 | /* Put back the modified character. */ | |
1528 | switch (modified_char) | |
1529 | { | |
1530 | case 0: | |
1531 | break; | |
1532 | ||
1533 | default: | |
1534 | *--operands = modified_char; | |
1535 | } | |
1536 | ||
3bcbcc3d | 1537 | /* Try to match an opcode table slot. */ |
47926f60 | 1538 | for (s = operands;;) |
3bcbcc3d | 1539 | { |
47926f60 | 1540 | int imm_expr_found; |
3bcbcc3d HPN |
1541 | |
1542 | /* Initialize *prefixp, perhaps after being modified for a | |
47926f60 | 1543 | "near match". */ |
3bcbcc3d HPN |
1544 | prefixp->kind = PREFIX_NONE; |
1545 | prefixp->reloc = BFD_RELOC_NONE; | |
1546 | ||
1547 | /* Initialize *out_insnp. */ | |
1548 | memset (out_insnp, 0, sizeof (*out_insnp)); | |
1549 | out_insnp->opcode = instruction->match; | |
1550 | out_insnp->reloc = BFD_RELOC_NONE; | |
1551 | out_insnp->insn_type = CRIS_INSN_NORMAL; | |
1552 | out_insnp->imm_oprnd_size = 0; | |
1553 | ||
1554 | imm_expr_found = 0; | |
1555 | ||
1556 | /* Build the opcode, checking as we go to make sure that the | |
1557 | operands match. */ | |
47926f60 | 1558 | for (args = instruction->args;; ++args) |
3bcbcc3d HPN |
1559 | { |
1560 | switch (*args) | |
1561 | { | |
1562 | case '\0': | |
1563 | /* If we've come to the end of arguments, we're done. */ | |
1564 | if (*s == '\0') | |
1565 | match = 1; | |
1566 | break; | |
1567 | ||
1568 | case '!': | |
1569 | /* Non-matcher character for disassembly. | |
1570 | Ignore it here. */ | |
1571 | continue; | |
1572 | ||
ae57792d HPN |
1573 | case '[': |
1574 | case ']': | |
3bcbcc3d HPN |
1575 | case ',': |
1576 | case ' ': | |
1577 | /* These must match exactly. */ | |
1578 | if (*s++ == *args) | |
1579 | continue; | |
1580 | break; | |
1581 | ||
ae57792d HPN |
1582 | case 'A': |
1583 | /* "ACR", case-insensitive. | |
1584 | Handle a sometimes-mandatory dollar sign as register | |
1585 | prefix. */ | |
1586 | if (*s == REGISTER_PREFIX_CHAR) | |
1587 | s++; | |
1588 | else if (demand_register_prefix) | |
1589 | break; | |
1590 | ||
1591 | if ((*s++ != 'a' && s[-1] != 'A') | |
1592 | || (*s++ != 'c' && s[-1] != 'C') | |
1593 | || (*s++ != 'r' && s[-1] != 'R')) | |
1594 | break; | |
1595 | continue; | |
1596 | ||
3bcbcc3d HPN |
1597 | case 'B': |
1598 | /* This is not really an operand, but causes a "BDAP | |
47926f60 | 1599 | -size,SP" prefix to be output, for PUSH instructions. */ |
3bcbcc3d HPN |
1600 | prefixp->kind = PREFIX_PUSH; |
1601 | continue; | |
1602 | ||
1603 | case 'b': | |
1604 | /* This letter marks an operand that should not be matched | |
1605 | in the assembler. It is a branch with 16-bit | |
1606 | displacement. The assembler will create them from the | |
1607 | 8-bit flavor when necessary. The assembler does not | |
1608 | support the [rN+] operand, as the [r15+] that is | |
1609 | generated for 16-bit displacements. */ | |
1610 | break; | |
1611 | ||
1612 | case 'c': | |
1613 | /* A 5-bit unsigned immediate in bits <4:0>. */ | |
1614 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1615 | break; | |
1616 | else | |
1617 | { | |
1618 | if (out_insnp->expr.X_op == O_constant | |
1619 | && (out_insnp->expr.X_add_number < 0 | |
1620 | || out_insnp->expr.X_add_number > 31)) | |
1621 | as_bad (_("Immediate value not in 5 bit unsigned range: %ld"), | |
1622 | out_insnp->expr.X_add_number); | |
1623 | ||
1624 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_5; | |
1625 | continue; | |
1626 | } | |
1627 | ||
1628 | case 'C': | |
1629 | /* A 4-bit unsigned immediate in bits <3:0>. */ | |
1630 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1631 | break; | |
1632 | else | |
1633 | { | |
1634 | if (out_insnp->expr.X_op == O_constant | |
1635 | && (out_insnp->expr.X_add_number < 0 | |
1636 | || out_insnp->expr.X_add_number > 15)) | |
1637 | as_bad (_("Immediate value not in 4 bit unsigned range: %ld"), | |
1638 | out_insnp->expr.X_add_number); | |
1639 | ||
1640 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_4; | |
1641 | continue; | |
1642 | } | |
1643 | ||
ae57792d HPN |
1644 | /* For 'd', check for an optional ".d" or ".D" at the |
1645 | start of the operands, followed by a space character. */ | |
1646 | case 'd': | |
1647 | if (modified_char == '.' && *s == '.') | |
1648 | { | |
1649 | if ((s[1] != 'd' && s[1] == 'D') | |
1650 | || ! ISSPACE (s[2])) | |
1651 | break; | |
1652 | s += 2; | |
1653 | continue; | |
1654 | } | |
1655 | continue; | |
1656 | ||
3bcbcc3d HPN |
1657 | case 'D': |
1658 | /* General register in bits <15:12> and <3:0>. */ | |
1659 | if (! get_gen_reg (&s, ®no)) | |
1660 | break; | |
1661 | else | |
1662 | { | |
1663 | out_insnp->opcode |= regno /* << 0 */; | |
1664 | out_insnp->opcode |= regno << 12; | |
1665 | continue; | |
1666 | } | |
1667 | ||
1668 | case 'f': | |
1669 | /* Flags from the condition code register. */ | |
1670 | { | |
1671 | int flags = 0; | |
1672 | ||
1673 | if (! get_flags (&s, &flags)) | |
1674 | break; | |
1675 | ||
47926f60 | 1676 | out_insnp->opcode |= ((flags & 0xf0) << 8) | (flags & 0xf); |
3bcbcc3d HPN |
1677 | continue; |
1678 | } | |
1679 | ||
1680 | case 'i': | |
1681 | /* A 6-bit signed immediate in bits <5:0>. */ | |
1682 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1683 | break; | |
1684 | else | |
1685 | { | |
1686 | if (out_insnp->expr.X_op == O_constant | |
1687 | && (out_insnp->expr.X_add_number < -32 | |
1688 | || out_insnp->expr.X_add_number > 31)) | |
1689 | as_bad (_("Immediate value not in 6 bit range: %ld"), | |
1690 | out_insnp->expr.X_add_number); | |
1691 | out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_6; | |
1692 | continue; | |
1693 | } | |
1694 | ||
1695 | case 'I': | |
1696 | /* A 6-bit unsigned immediate in bits <5:0>. */ | |
1697 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1698 | break; | |
1699 | else | |
1700 | { | |
1701 | if (out_insnp->expr.X_op == O_constant | |
1702 | && (out_insnp->expr.X_add_number < 0 | |
1703 | || out_insnp->expr.X_add_number > 63)) | |
1704 | as_bad (_("Immediate value not in 6 bit unsigned range: %ld"), | |
1705 | out_insnp->expr.X_add_number); | |
1706 | out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_6; | |
1707 | continue; | |
1708 | } | |
1709 | ||
1710 | case 'M': | |
1711 | /* A size modifier, B, W or D, to be put in a bit position | |
1712 | suitable for CLEAR instructions (i.e. reflecting a zero | |
1713 | register). */ | |
1714 | if (! get_bwd_size_modifier (&s, &size_bits)) | |
1715 | break; | |
1716 | else | |
1717 | { | |
1718 | switch (size_bits) | |
1719 | { | |
1720 | case 0: | |
1721 | out_insnp->opcode |= 0 << 12; | |
1722 | break; | |
1723 | ||
1724 | case 1: | |
1725 | out_insnp->opcode |= 4 << 12; | |
1726 | break; | |
1727 | ||
1728 | case 2: | |
1729 | out_insnp->opcode |= 8 << 12; | |
1730 | break; | |
1731 | } | |
1732 | continue; | |
1733 | } | |
1734 | ||
1735 | case 'm': | |
1736 | /* A size modifier, B, W or D, to be put in bits <5:4>. */ | |
ae57792d HPN |
1737 | if (modified_char != '.' |
1738 | || ! get_bwd_size_modifier (&s, &size_bits)) | |
3bcbcc3d HPN |
1739 | break; |
1740 | else | |
1741 | { | |
1742 | out_insnp->opcode |= size_bits << 4; | |
1743 | continue; | |
1744 | } | |
1745 | ||
1746 | case 'o': | |
1747 | /* A branch expression. */ | |
1748 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1749 | break; | |
1750 | else | |
1751 | { | |
1752 | out_insnp->insn_type = CRIS_INSN_BRANCH; | |
1753 | continue; | |
1754 | } | |
1755 | ||
ae57792d HPN |
1756 | case 'Q': |
1757 | /* A 8-bit quick BDAP expression, "expr,R". */ | |
1758 | if (! cris_get_expression (&s, &out_insnp->expr)) | |
1759 | break; | |
1760 | ||
1761 | if (*s != ',') | |
1762 | break; | |
1763 | ||
1764 | s++; | |
1765 | ||
1766 | if (!get_gen_reg (&s, ®no)) | |
1767 | break; | |
1768 | ||
1769 | out_insnp->opcode |= regno << 12; | |
1770 | out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_8; | |
1771 | continue; | |
1772 | ||
3bcbcc3d | 1773 | case 'O': |
ae57792d | 1774 | /* A BDAP expression for any size, "expr,R". */ |
3bcbcc3d HPN |
1775 | if (! cris_get_expression (&s, &prefixp->expr)) |
1776 | break; | |
1777 | else | |
1778 | { | |
1779 | if (*s != ',') | |
1780 | break; | |
1781 | ||
1782 | s++; | |
1783 | ||
1784 | if (!get_gen_reg (&s, &prefixp->base_reg_number)) | |
1785 | break; | |
1786 | ||
1787 | /* Since 'O' is used with an explicit bdap, we have no | |
47926f60 | 1788 | "real" instruction. */ |
3bcbcc3d | 1789 | prefixp->kind = PREFIX_BDAP_IMM; |
08caf3f8 HPN |
1790 | prefixp->opcode |
1791 | = BDAP_QUICK_OPCODE | (prefixp->base_reg_number << 12); | |
1792 | ||
3bcbcc3d HPN |
1793 | out_insnp->insn_type = CRIS_INSN_NONE; |
1794 | continue; | |
1795 | } | |
1796 | ||
1797 | case 'P': | |
1798 | /* Special register in bits <15:12>. */ | |
1799 | if (! get_spec_reg (&s, &out_insnp->spec_reg)) | |
1800 | break; | |
1801 | else | |
1802 | { | |
1803 | /* Use of some special register names come with a | |
1804 | specific warning. Note that we have no ".cpu type" | |
1805 | pseudo yet, so some of this is just unused | |
1806 | framework. */ | |
1807 | if (out_insnp->spec_reg->warning) | |
1808 | as_warn (out_insnp->spec_reg->warning); | |
1809 | else if (out_insnp->spec_reg->applicable_version | |
1810 | == cris_ver_warning) | |
1811 | /* Others have a generic warning. */ | |
1812 | as_warn (_("Unimplemented register `%s' specified"), | |
1813 | out_insnp->spec_reg->name); | |
1814 | ||
1815 | out_insnp->opcode | |
1816 | |= out_insnp->spec_reg->number << 12; | |
1817 | continue; | |
1818 | } | |
1819 | ||
1820 | case 'p': | |
1821 | /* This character is used in the disassembler to | |
1822 | recognize a prefix instruction to fold into the | |
1823 | addressing mode for the next instruction. It is | |
47926f60 | 1824 | ignored here. */ |
3bcbcc3d HPN |
1825 | continue; |
1826 | ||
1827 | case 'R': | |
1828 | /* General register in bits <15:12>. */ | |
1829 | if (! get_gen_reg (&s, ®no)) | |
1830 | break; | |
1831 | else | |
1832 | { | |
1833 | out_insnp->opcode |= regno << 12; | |
1834 | continue; | |
1835 | } | |
1836 | ||
1837 | case 'r': | |
1838 | /* General register in bits <3:0>. */ | |
1839 | if (! get_gen_reg (&s, ®no)) | |
1840 | break; | |
1841 | else | |
1842 | { | |
1843 | out_insnp->opcode |= regno /* << 0 */; | |
1844 | continue; | |
1845 | } | |
1846 | ||
1847 | case 'S': | |
1848 | /* Source operand in bit <10> and a prefix; a 3-operand | |
1849 | prefix. */ | |
1850 | if (! get_3op_or_dip_prefix_op (&s, prefixp)) | |
1851 | break; | |
1852 | else | |
1853 | continue; | |
1854 | ||
1855 | case 's': | |
1856 | /* Source operand in bits <10>, <3:0> and optionally a | |
1857 | prefix; i.e. an indirect operand or an side-effect | |
ae57792d | 1858 | prefix (where valid). */ |
3bcbcc3d HPN |
1859 | if (! get_autoinc_prefix_or_indir_op (&s, prefixp, &mode, |
1860 | ®no, | |
1861 | &imm_expr_found, | |
1862 | &out_insnp->expr)) | |
1863 | break; | |
1864 | else | |
1865 | { | |
1866 | if (prefixp->kind != PREFIX_NONE) | |
1867 | { | |
1868 | /* A prefix, so it has the autoincrement bit | |
1869 | set. */ | |
1870 | out_insnp->opcode |= (AUTOINCR_BIT << 8); | |
1871 | } | |
1872 | else | |
08caf3f8 HPN |
1873 | { |
1874 | /* No prefix. The "mode" variable contains bits like | |
1875 | whether or not this is autoincrement mode. */ | |
1876 | out_insnp->opcode |= (mode << 10); | |
1877 | ||
1878 | /* If there was a PIC reloc specifier, then it was | |
1879 | attached to the prefix. Note that we can't check | |
1880 | that the reloc size matches, since we don't have | |
1881 | all the operands yet in all cases. */ | |
1882 | if (prefixp->reloc != BFD_RELOC_NONE) | |
1883 | out_insnp->reloc = prefixp->reloc; | |
1884 | } | |
3bcbcc3d HPN |
1885 | |
1886 | out_insnp->opcode |= regno /* << 0 */ ; | |
1887 | continue; | |
1888 | } | |
1889 | ||
ae57792d HPN |
1890 | case 'N': |
1891 | case 'Y': | |
1892 | /* Like 's', but immediate operand only. Also does not | |
1893 | modify insn. There are no insns where a PIC reloc | |
1894 | specifier makes sense. */ | |
1895 | if (cris_get_expression (&s, &out_insnp->expr)) | |
1896 | { | |
1897 | imm_expr_found = 1; | |
1898 | continue; | |
1899 | } | |
1900 | break; | |
1901 | ||
1902 | case 'n': | |
1903 | /* Like 'N', but PC-relative to the start of the insn. | |
1904 | There might be a :PLT to request a PLT entry. */ | |
1905 | if (cris_get_expression (&s, &out_insnp->expr)) | |
1906 | { | |
1907 | imm_expr_found = 1; | |
1908 | out_insnp->reloc = BFD_RELOC_32_PCREL; | |
1909 | ||
1910 | /* We have to adjust the expression, because that | |
1911 | relocation is to the location *after* the | |
1912 | relocation. So add 2 for the insn and 4 for the | |
1913 | relocation. */ | |
1914 | out_insnp->expr.X_add_number += 6; | |
1915 | ||
1916 | if (pic && *s == PIC_SUFFIX_CHAR) | |
1917 | cris_get_pic_suffix (&s, &out_insnp->reloc, | |
1918 | &out_insnp->expr); | |
1919 | ||
1920 | continue; | |
1921 | } | |
1922 | break; | |
1923 | ||
1924 | case 'U': | |
1925 | /* Maybe 'u', maybe 'n'. Only for LAPC/LAPCQ. */ | |
1926 | if (cris_get_expression (&s, &out_insnp->expr)) | |
1927 | { | |
1928 | out_insnp->reloc = BFD_RELOC_CRIS_LAPCQ_OFFSET; | |
1929 | ||
1930 | /* Define 1 as relaxing. */ | |
1931 | out_insnp->expr.X_md = 1; | |
1932 | continue; | |
1933 | } | |
1934 | break; | |
1935 | ||
1936 | case 'u': | |
1937 | /* Four PC-relative bits in <3:0> representing <4:1>:0 of | |
1938 | an offset relative to the beginning of the current | |
1939 | insn. */ | |
1940 | if (cris_get_expression (&s, &out_insnp->expr)) | |
1941 | { | |
1942 | out_insnp->reloc = BFD_RELOC_CRIS_LAPCQ_OFFSET; | |
1943 | ||
1944 | /* Define 0 as non-relaxing. */ | |
1945 | out_insnp->expr.X_md = 0; | |
1946 | ||
1947 | /* We have to adjust the expression, because that | |
1948 | relocation is to the location *after* the | |
1949 | insn. So add 2 for the insn. */ | |
1950 | out_insnp->expr.X_add_number += 2; | |
1951 | continue; | |
1952 | } | |
1953 | break; | |
1954 | ||
3bcbcc3d HPN |
1955 | case 'x': |
1956 | /* Rs.m in bits <15:12> and <5:4>. */ | |
1957 | if (! get_gen_reg (&s, ®no) | |
1958 | || ! get_bwd_size_modifier (&s, &size_bits)) | |
1959 | break; | |
1960 | else | |
1961 | { | |
47926f60 | 1962 | out_insnp->opcode |= (regno << 12) | (size_bits << 4); |
3bcbcc3d HPN |
1963 | continue; |
1964 | } | |
1965 | ||
1966 | case 'y': | |
1967 | /* Source operand in bits <10>, <3:0> and optionally a | |
1968 | prefix; i.e. an indirect operand or an side-effect | |
1969 | prefix. | |
1970 | ||
1971 | The difference to 's' is that this does not allow an | |
81d4177b | 1972 | "immediate" expression. */ |
3bcbcc3d HPN |
1973 | if (! get_autoinc_prefix_or_indir_op (&s, prefixp, |
1974 | &mode, ®no, | |
1975 | &imm_expr_found, | |
1976 | &out_insnp->expr) | |
1977 | || imm_expr_found) | |
1978 | break; | |
1979 | else | |
1980 | { | |
1981 | if (prefixp->kind != PREFIX_NONE) | |
1982 | { | |
1983 | /* A prefix, and those matched here always have | |
1984 | side-effects (see 's' case). */ | |
1985 | out_insnp->opcode |= (AUTOINCR_BIT << 8); | |
1986 | } | |
1987 | else | |
1988 | { | |
1989 | /* No prefix. The "mode" variable contains bits | |
1990 | like whether or not this is autoincrement | |
1991 | mode. */ | |
1992 | out_insnp->opcode |= (mode << 10); | |
1993 | } | |
1994 | ||
1995 | out_insnp->opcode |= regno /* << 0 */; | |
1996 | continue; | |
1997 | } | |
1998 | ||
1999 | case 'z': | |
2000 | /* Size modifier (B or W) in bit <4>. */ | |
2001 | if (! get_bw_size_modifier (&s, &size_bits)) | |
2002 | break; | |
2003 | else | |
2004 | { | |
2005 | out_insnp->opcode |= size_bits << 4; | |
2006 | continue; | |
2007 | } | |
2008 | ||
ae57792d HPN |
2009 | case 'T': |
2010 | if (cris_arch == arch_crisv32 | |
2011 | && get_sup_reg (&s, ®no)) | |
2012 | { | |
2013 | out_insnp->opcode |= regno << 12; | |
2014 | continue; | |
2015 | } | |
2016 | break; | |
2017 | ||
3bcbcc3d HPN |
2018 | default: |
2019 | BAD_CASE (*args); | |
2020 | } | |
2021 | ||
2022 | /* We get here when we fail a match above or we found a | |
2023 | complete match. Break out of this loop. */ | |
2024 | break; | |
2025 | } | |
2026 | ||
2027 | /* Was it a match or a miss? */ | |
2028 | if (match == 0) | |
2029 | { | |
2030 | /* If it's just that the args don't match, maybe the next | |
2031 | item in the table is the same opcode but with | |
ae57792d HPN |
2032 | matching operands. First skip any invalid ones. */ |
2033 | while (instruction[1].name != NULL | |
2034 | && strcmp (instruction->name, instruction[1].name) == 0 | |
2035 | && ! cris_insn_ver_valid_for_arch (instruction[1] | |
2036 | .applicable_version, | |
2037 | cris_arch)) | |
2038 | ++instruction; | |
2039 | ||
3bcbcc3d | 2040 | if (instruction[1].name != NULL |
ae57792d HPN |
2041 | && strcmp (instruction->name, instruction[1].name) == 0 |
2042 | && cris_insn_ver_valid_for_arch (instruction[1] | |
2043 | .applicable_version, | |
2044 | cris_arch)) | |
3bcbcc3d HPN |
2045 | { |
2046 | /* Yep. Restart and try that one instead. */ | |
2047 | ++instruction; | |
2048 | s = operands; | |
2049 | continue; | |
2050 | } | |
2051 | else | |
2052 | { | |
2053 | /* We've come to the end of instructions with this | |
2054 | opcode, so it must be an error. */ | |
2055 | as_bad (_("Illegal operands")); | |
ae57792d HPN |
2056 | |
2057 | /* As discard_rest_of_line, but without continuing to the | |
2058 | next line. */ | |
2059 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2060 | input_line_pointer++; | |
3bcbcc3d HPN |
2061 | return; |
2062 | } | |
2063 | } | |
2064 | else | |
2065 | { | |
2066 | /* We have a match. Check if there's anything more to do. */ | |
2067 | if (imm_expr_found) | |
2068 | { | |
2069 | /* There was an immediate mode operand, so we must check | |
2070 | that it has an appropriate size. */ | |
3bcbcc3d HPN |
2071 | switch (instruction->imm_oprnd_size) |
2072 | { | |
2073 | default: | |
2074 | case SIZE_NONE: | |
2075 | /* Shouldn't happen; this one does not have immediate | |
2076 | operands with different sizes. */ | |
2077 | BAD_CASE (instruction->imm_oprnd_size); | |
2078 | break; | |
2079 | ||
2080 | case SIZE_FIX_32: | |
2081 | out_insnp->imm_oprnd_size = 4; | |
2082 | break; | |
2083 | ||
2084 | case SIZE_SPEC_REG: | |
ae57792d HPN |
2085 | if (cris_arch == arch_crisv32) |
2086 | /* All immediate loads of special registers are | |
2087 | 32-bit on CRISv32. */ | |
2088 | out_insnp->imm_oprnd_size = 4; | |
2089 | else | |
2090 | switch (out_insnp->spec_reg->reg_size) | |
2091 | { | |
2092 | case 1: | |
2093 | if (out_insnp->expr.X_op == O_constant | |
2094 | && (out_insnp->expr.X_add_number < -128 | |
2095 | || out_insnp->expr.X_add_number > 255)) | |
2096 | as_bad (_("Immediate value not in 8 bit range: %ld"), | |
2097 | out_insnp->expr.X_add_number); | |
2098 | /* Fall through. */ | |
2099 | case 2: | |
2100 | /* FIXME: We need an indicator in the instruction | |
2101 | table to pass on, to indicate if we need to check | |
2102 | overflow for a signed or unsigned number. */ | |
2103 | if (out_insnp->expr.X_op == O_constant | |
2104 | && (out_insnp->expr.X_add_number < -32768 | |
2105 | || out_insnp->expr.X_add_number > 65535)) | |
2106 | as_bad (_("Immediate value not in 16 bit range: %ld"), | |
2107 | out_insnp->expr.X_add_number); | |
2108 | out_insnp->imm_oprnd_size = 2; | |
2109 | break; | |
2110 | ||
2111 | case 4: | |
2112 | out_insnp->imm_oprnd_size = 4; | |
2113 | break; | |
2114 | ||
2115 | default: | |
2116 | BAD_CASE (out_insnp->spec_reg->reg_size); | |
2117 | } | |
3bcbcc3d HPN |
2118 | break; |
2119 | ||
2120 | case SIZE_FIELD: | |
ae57792d HPN |
2121 | case SIZE_FIELD_SIGNED: |
2122 | case SIZE_FIELD_UNSIGNED: | |
3bcbcc3d HPN |
2123 | switch (size_bits) |
2124 | { | |
ae57792d HPN |
2125 | /* FIXME: Find way to pass un/signedness to |
2126 | caller, and set reloc type instead, postponing | |
2127 | this check until cris_number_to_imm. That | |
2128 | necessarily corrects the reloc type for the | |
2129 | byte case, maybe requiring further changes. */ | |
3bcbcc3d | 2130 | case 0: |
ae57792d HPN |
2131 | if (out_insnp->expr.X_op == O_constant) |
2132 | { | |
2133 | if (instruction->imm_oprnd_size == SIZE_FIELD | |
2134 | && (out_insnp->expr.X_add_number < -128 | |
2135 | || out_insnp->expr.X_add_number > 255)) | |
2136 | as_bad (_("Immediate value not in 8 bit range: %ld"), | |
2137 | out_insnp->expr.X_add_number); | |
2138 | else if (instruction->imm_oprnd_size == SIZE_FIELD_SIGNED | |
2139 | && (out_insnp->expr.X_add_number < -128 | |
2140 | || out_insnp->expr.X_add_number > 127)) | |
2141 | as_bad (_("Immediate value not in 8 bit signed range: %ld"), | |
2142 | out_insnp->expr.X_add_number); | |
2143 | else if (instruction->imm_oprnd_size == SIZE_FIELD_UNSIGNED | |
2144 | && (out_insnp->expr.X_add_number < 0 | |
2145 | || out_insnp->expr.X_add_number > 255)) | |
2146 | as_bad (_("Immediate value not in 8 bit unsigned range: %ld"), | |
2147 | out_insnp->expr.X_add_number); | |
2148 | } | |
2149 | ||
47926f60 | 2150 | /* Fall through. */ |
3bcbcc3d | 2151 | case 1: |
ae57792d HPN |
2152 | if (out_insnp->expr.X_op == O_constant) |
2153 | { | |
2154 | if (instruction->imm_oprnd_size == SIZE_FIELD | |
2155 | && (out_insnp->expr.X_add_number < -32768 | |
2156 | || out_insnp->expr.X_add_number > 65535)) | |
2157 | as_bad (_("Immediate value not in 16 bit range: %ld"), | |
2158 | out_insnp->expr.X_add_number); | |
2159 | else if (instruction->imm_oprnd_size == SIZE_FIELD_SIGNED | |
2160 | && (out_insnp->expr.X_add_number < -32768 | |
2161 | || out_insnp->expr.X_add_number > 32767)) | |
2162 | as_bad (_("Immediate value not in 16 bit signed range: %ld"), | |
2163 | out_insnp->expr.X_add_number); | |
2164 | else if (instruction->imm_oprnd_size == SIZE_FIELD_UNSIGNED | |
2165 | && (out_insnp->expr.X_add_number < 0 | |
2166 | || out_insnp->expr.X_add_number > 65535)) | |
2167 | as_bad (_("Immediate value not in 16 bit unsigned range: %ld"), | |
2168 | out_insnp->expr.X_add_number); | |
2169 | } | |
3bcbcc3d HPN |
2170 | out_insnp->imm_oprnd_size = 2; |
2171 | break; | |
2172 | ||
2173 | case 2: | |
2174 | out_insnp->imm_oprnd_size = 4; | |
2175 | break; | |
2176 | ||
2177 | default: | |
2178 | BAD_CASE (out_insnp->spec_reg->reg_size); | |
2179 | } | |
2180 | } | |
08caf3f8 HPN |
2181 | |
2182 | /* If there was a relocation specified for the immediate | |
2183 | expression (i.e. it had a PIC modifier) check that the | |
2184 | size of the PIC relocation matches the size specified by | |
2185 | the opcode. */ | |
2186 | if (out_insnp->reloc != BFD_RELOC_NONE | |
2187 | && (cris_get_pic_reloc_size (out_insnp->reloc) | |
2188 | != (unsigned int) out_insnp->imm_oprnd_size)) | |
2189 | as_bad (_("PIC relocation size does not match operand size")); | |
3bcbcc3d | 2190 | } |
1048a9ba HPN |
2191 | else if (instruction->op == cris_muls_op |
2192 | || instruction->op == cris_mulu_op) | |
2193 | out_insnp->insn_type = CRIS_INSN_MUL; | |
3bcbcc3d HPN |
2194 | } |
2195 | break; | |
2196 | } | |
2197 | } | |
2198 | ||
3bcbcc3d HPN |
2199 | /* Get a B, W, or D size modifier from the string pointed out by *cPP, |
2200 | which must point to a '.' in front of the modifier. On successful | |
2201 | return, *cPP is advanced to the character following the size | |
2202 | modifier, and is undefined otherwise. | |
2203 | ||
2204 | cPP Pointer to pointer to string starting | |
2205 | with the size modifier. | |
2206 | ||
2207 | size_bitsp Pointer to variable to contain the size bits on | |
2208 | successful return. | |
2209 | ||
2210 | Return 1 iff a correct size modifier is found, else 0. */ | |
2211 | ||
2212 | static int | |
2213 | get_bwd_size_modifier (cPP, size_bitsp) | |
2214 | char **cPP; | |
2215 | int *size_bitsp; | |
2216 | { | |
2217 | if (**cPP != '.') | |
2218 | return 0; | |
2219 | else | |
2220 | { | |
47926f60 | 2221 | /* Consume the '.'. */ |
3bcbcc3d HPN |
2222 | (*cPP)++; |
2223 | ||
2224 | switch (**cPP) | |
2225 | { | |
2226 | case 'B': | |
2227 | case 'b': | |
2228 | *size_bitsp = 0; | |
2229 | break; | |
2230 | ||
2231 | case 'W': | |
2232 | case 'w': | |
2233 | *size_bitsp = 1; | |
2234 | break; | |
2235 | ||
2236 | case 'D': | |
2237 | case 'd': | |
2238 | *size_bitsp = 2; | |
2239 | break; | |
2240 | ||
2241 | default: | |
2242 | return 0; | |
2243 | } | |
2244 | ||
2245 | /* Consume the size letter. */ | |
2246 | (*cPP)++; | |
2247 | return 1; | |
2248 | } | |
2249 | } | |
2250 | ||
3bcbcc3d HPN |
2251 | /* Get a B or W size modifier from the string pointed out by *cPP, |
2252 | which must point to a '.' in front of the modifier. On successful | |
2253 | return, *cPP is advanced to the character following the size | |
2254 | modifier, and is undefined otherwise. | |
2255 | ||
2256 | cPP Pointer to pointer to string starting | |
2257 | with the size modifier. | |
2258 | ||
2259 | size_bitsp Pointer to variable to contain the size bits on | |
2260 | successful return. | |
2261 | ||
2262 | Return 1 iff a correct size modifier is found, else 0. */ | |
2263 | ||
2264 | static int | |
2265 | get_bw_size_modifier (cPP, size_bitsp) | |
2266 | char **cPP; | |
2267 | int *size_bitsp; | |
2268 | { | |
2269 | if (**cPP != '.') | |
2270 | return 0; | |
2271 | else | |
2272 | { | |
47926f60 | 2273 | /* Consume the '.'. */ |
3bcbcc3d HPN |
2274 | (*cPP)++; |
2275 | ||
2276 | switch (**cPP) | |
2277 | { | |
2278 | case 'B': | |
2279 | case 'b': | |
2280 | *size_bitsp = 0; | |
2281 | break; | |
2282 | ||
2283 | case 'W': | |
2284 | case 'w': | |
2285 | *size_bitsp = 1; | |
2286 | break; | |
2287 | ||
2288 | default: | |
2289 | return 0; | |
2290 | } | |
2291 | ||
2292 | /* Consume the size letter. */ | |
2293 | (*cPP)++; | |
2294 | return 1; | |
2295 | } | |
2296 | } | |
2297 | ||
07e90ad5 | 2298 | /* Get a general register from the string pointed out by *cPP. The |
3bcbcc3d HPN |
2299 | variable *cPP is advanced to the character following the general |
2300 | register name on a successful return, and has its initial position | |
2301 | otherwise. | |
2302 | ||
2303 | cPP Pointer to pointer to string, beginning with a general | |
2304 | register name. | |
2305 | ||
2306 | regnop Pointer to int containing the register number. | |
2307 | ||
2308 | Return 1 iff a correct general register designator is found, | |
2309 | else 0. */ | |
2310 | ||
2311 | static int | |
2312 | get_gen_reg (cPP, regnop) | |
2313 | char **cPP; | |
2314 | int *regnop; | |
2315 | { | |
2316 | char *oldp; | |
2317 | oldp = *cPP; | |
2318 | ||
7b15d668 HPN |
2319 | /* Handle a sometimes-mandatory dollar sign as register prefix. */ |
2320 | if (**cPP == REGISTER_PREFIX_CHAR) | |
2321 | (*cPP)++; | |
2322 | else if (demand_register_prefix) | |
2323 | return 0; | |
2324 | ||
3bcbcc3d HPN |
2325 | switch (**cPP) |
2326 | { | |
2327 | case 'P': | |
2328 | case 'p': | |
2329 | /* "P" as in "PC"? Consume the "P". */ | |
2330 | (*cPP)++; | |
2331 | ||
2332 | if ((**cPP == 'C' || **cPP == 'c') | |
ae57792d HPN |
2333 | && ! ISALNUM ((*cPP)[1]) |
2334 | /* Here's a little twist: For v32 and the compatibility mode, | |
2335 | we only recognize PC as a register number if there's '+]' | |
2336 | after. We don't consume that, but the presence can only be | |
2337 | valid after a register in a post-increment context, which | |
2338 | is also the only valid context for PC as a register for | |
2339 | v32. Not that it's used very often, but saying "MOVE.D | |
2340 | [PC+],R5" should remain valid. It's not supported for | |
2341 | jump-type insns or other insns with no [Rn+] mode, though. */ | |
2342 | && ((cris_arch != arch_crisv32 | |
2343 | && cris_arch != arch_cris_common_v10_v32) | |
2344 | || ((*cPP)[1] == '+' && (*cPP)[2] == ']'))) | |
3bcbcc3d HPN |
2345 | { |
2346 | /* It's "PC": consume the "c" and we're done. */ | |
2347 | (*cPP)++; | |
2348 | *regnop = REG_PC; | |
2349 | return 1; | |
2350 | } | |
2351 | break; | |
2352 | ||
ae57792d HPN |
2353 | /* Like with PC, we recognize ACR, but only if it's *not* followed |
2354 | by '+', and only for v32. */ | |
2355 | case 'A': | |
2356 | case 'a': | |
2357 | if (cris_arch != arch_crisv32 | |
2358 | || ((*cPP)[1] != 'c' && (*cPP)[1] != 'C') | |
2359 | || ((*cPP)[2] != 'r' && (*cPP)[2] != 'R') | |
2360 | || ISALNUM ((*cPP)[3]) | |
2361 | || (*cPP)[3] == '+') | |
2362 | break; | |
2363 | (*cPP) += 3; | |
2364 | *regnop = 15; | |
2365 | return 1; | |
2366 | ||
3bcbcc3d HPN |
2367 | case 'R': |
2368 | case 'r': | |
47926f60 | 2369 | /* Hopefully r[0-9] or r1[0-5]. Consume 'R' or 'r'. */ |
3bcbcc3d HPN |
2370 | (*cPP)++; |
2371 | ||
3882b010 | 2372 | if (ISDIGIT (**cPP)) |
3bcbcc3d HPN |
2373 | { |
2374 | /* It's r[0-9]. Consume and check the next digit. */ | |
2375 | *regnop = **cPP - '0'; | |
2376 | (*cPP)++; | |
2377 | ||
3882b010 | 2378 | if (! ISALNUM (**cPP)) |
3bcbcc3d | 2379 | { |
47926f60 | 2380 | /* No more digits, we're done. */ |
3bcbcc3d HPN |
2381 | return 1; |
2382 | } | |
2383 | else | |
2384 | { | |
2385 | /* One more digit. Consume and add. */ | |
47926f60 | 2386 | *regnop = *regnop * 10 + (**cPP - '0'); |
3bcbcc3d HPN |
2387 | |
2388 | /* We need to check for a valid register number; Rn, | |
2389 | 0 <= n <= MAX_REG. */ | |
2390 | if (*regnop <= MAX_REG) | |
2391 | { | |
2392 | /* Consume second digit. */ | |
2393 | (*cPP)++; | |
2394 | return 1; | |
2395 | } | |
2396 | } | |
2397 | } | |
2398 | break; | |
2399 | ||
2400 | case 'S': | |
2401 | case 's': | |
2402 | /* "S" as in "SP"? Consume the "S". */ | |
2403 | (*cPP)++; | |
2404 | if (**cPP == 'P' || **cPP == 'p') | |
2405 | { | |
2406 | /* It's "SP": consume the "p" and we're done. */ | |
2407 | (*cPP)++; | |
2408 | *regnop = REG_SP; | |
2409 | return 1; | |
2410 | } | |
2411 | break; | |
2412 | ||
2413 | default: | |
2414 | /* Just here to silence compilation warnings. */ | |
2415 | ; | |
2416 | } | |
2417 | ||
2418 | /* We get here if we fail. Restore the pointer. */ | |
2419 | *cPP = oldp; | |
2420 | return 0; | |
2421 | } | |
2422 | ||
3bcbcc3d HPN |
2423 | /* Get a special register from the string pointed out by *cPP. The |
2424 | variable *cPP is advanced to the character following the special | |
2425 | register name if one is found, and retains its original position | |
2426 | otherwise. | |
2427 | ||
2428 | cPP Pointer to pointer to string starting with a special register | |
2429 | name. | |
2430 | ||
2431 | sregpp Pointer to Pointer to struct spec_reg, where a pointer to the | |
2432 | register description will be stored. | |
2433 | ||
2434 | Return 1 iff a correct special register name is found. */ | |
2435 | ||
2436 | static int | |
2437 | get_spec_reg (cPP, sregpp) | |
2438 | char **cPP; | |
2439 | const struct cris_spec_reg **sregpp; | |
2440 | { | |
2441 | char *s1; | |
2442 | const char *s2; | |
7b15d668 | 2443 | char *name_begin = *cPP; |
3bcbcc3d HPN |
2444 | |
2445 | const struct cris_spec_reg *sregp; | |
2446 | ||
7b15d668 HPN |
2447 | /* Handle a sometimes-mandatory dollar sign as register prefix. */ |
2448 | if (*name_begin == REGISTER_PREFIX_CHAR) | |
2449 | name_begin++; | |
2450 | else if (demand_register_prefix) | |
2451 | return 0; | |
2452 | ||
3bcbcc3d | 2453 | /* Loop over all special registers. */ |
47926f60 | 2454 | for (sregp = cris_spec_regs; sregp->name != NULL; sregp++) |
3bcbcc3d | 2455 | { |
3bcbcc3d | 2456 | /* Start over from beginning of the supposed name. */ |
7b15d668 | 2457 | s1 = name_begin; |
3bcbcc3d HPN |
2458 | s2 = sregp->name; |
2459 | ||
3882b010 | 2460 | while (*s2 != '\0' && TOLOWER (*s1) == *s2) |
3bcbcc3d HPN |
2461 | { |
2462 | s1++; | |
2463 | s2++; | |
2464 | } | |
2465 | ||
2466 | /* For a match, we must have consumed the name in the table, and we | |
2467 | must be outside what could be part of a name. Assume here that a | |
47926f60 | 2468 | test for alphanumerics is sufficient for a name test. */ |
ae57792d HPN |
2469 | if (*s2 == 0 && ! ISALNUM (*s1) |
2470 | && cris_insn_ver_valid_for_arch (sregp->applicable_version, | |
2471 | cris_arch)) | |
3bcbcc3d | 2472 | { |
47926f60 | 2473 | /* We have a match. Update the pointer and be done. */ |
3bcbcc3d HPN |
2474 | *cPP = s1; |
2475 | *sregpp = sregp; | |
2476 | return 1; | |
2477 | } | |
2478 | } | |
2479 | ||
47926f60 | 2480 | /* If we got here, we did not find any name. */ |
3bcbcc3d HPN |
2481 | return 0; |
2482 | } | |
2483 | ||
ae57792d HPN |
2484 | /* Get a support register from the string pointed out by *cPP. The |
2485 | variable *cPP is advanced to the character following the support- | |
2486 | register name if one is found, and retains its original position | |
2487 | otherwise. | |
2488 | ||
2489 | cPP Pointer to pointer to string starting with a support-register | |
2490 | name. | |
2491 | ||
2492 | sregpp Pointer to int containing the register number. | |
2493 | ||
2494 | Return 1 iff a correct support-register name is found. */ | |
2495 | ||
2496 | static int | |
2497 | get_sup_reg (cPP, regnop) | |
2498 | char **cPP; | |
2499 | int *regnop; | |
2500 | { | |
2501 | char *s1; | |
2502 | const char *s2; | |
2503 | char *name_begin = *cPP; | |
2504 | ||
2505 | const struct cris_support_reg *sregp; | |
2506 | ||
2507 | /* Handle a sometimes-mandatory dollar sign as register prefix. */ | |
2508 | if (*name_begin == REGISTER_PREFIX_CHAR) | |
2509 | name_begin++; | |
2510 | else if (demand_register_prefix) | |
2511 | return 0; | |
2512 | ||
2513 | /* Loop over all support-registers. */ | |
2514 | for (sregp = cris_support_regs; sregp->name != NULL; sregp++) | |
2515 | { | |
2516 | /* Start over from beginning of the supposed name. */ | |
2517 | s1 = name_begin; | |
2518 | s2 = sregp->name; | |
2519 | ||
2520 | while (*s2 != '\0' && TOLOWER (*s1) == *s2) | |
2521 | { | |
2522 | s1++; | |
2523 | s2++; | |
2524 | } | |
2525 | ||
2526 | /* For a match, we must have consumed the name in the table, and we | |
2527 | must be outside what could be part of a name. Assume here that a | |
2528 | test for alphanumerics is sufficient for a name test. */ | |
2529 | if (*s2 == 0 && ! ISALNUM (*s1)) | |
2530 | { | |
2531 | /* We have a match. Update the pointer and be done. */ | |
2532 | *cPP = s1; | |
2533 | *regnop = sregp->number; | |
2534 | return 1; | |
2535 | } | |
2536 | } | |
2537 | ||
2538 | /* If we got here, we did not find any name. */ | |
2539 | return 0; | |
2540 | } | |
2541 | ||
3bcbcc3d HPN |
2542 | /* Get an unprefixed or side-effect-prefix operand from the string pointed |
2543 | out by *cPP. The pointer *cPP is advanced to the character following | |
2544 | the indirect operand if we have success, else it contains an undefined | |
2545 | value. | |
2546 | ||
2547 | cPP Pointer to pointer to string beginning with the first | |
2548 | character of the supposed operand. | |
2549 | ||
2550 | prefixp Pointer to structure containing an optional instruction | |
2551 | prefix. | |
2552 | ||
2553 | is_autoincp Pointer to int indicating the indirect or autoincrement | |
2554 | bits. | |
2555 | ||
2556 | src_regnop Pointer to int containing the source register number in | |
2557 | the instruction. | |
2558 | ||
2559 | imm_foundp Pointer to an int indicating if an immediate expression | |
2560 | is found. | |
2561 | ||
2562 | imm_exprP Pointer to a structure containing an immediate | |
2563 | expression, if success and if *imm_foundp is nonzero. | |
2564 | ||
2565 | Return 1 iff a correct indirect operand is found. */ | |
2566 | ||
2567 | static int | |
2568 | get_autoinc_prefix_or_indir_op (cPP, prefixp, is_autoincp, src_regnop, | |
2569 | imm_foundp, imm_exprP) | |
47926f60 KH |
2570 | char **cPP; |
2571 | struct cris_prefix *prefixp; | |
2572 | int *is_autoincp; | |
2573 | int *src_regnop; | |
2574 | int *imm_foundp; | |
2575 | expressionS *imm_exprP; | |
3bcbcc3d HPN |
2576 | { |
2577 | /* Assume there was no immediate mode expression. */ | |
2578 | *imm_foundp = 0; | |
2579 | ||
2580 | if (**cPP == '[') | |
2581 | { | |
2582 | /* So this operand is one of: | |
2583 | Indirect: [rN] | |
2584 | Autoincrement: [rN+] | |
2585 | Indexed with assign: [rN=rM+rO.S] | |
2586 | Offset with assign: [rN=rM+I], [rN=rM+[rO].s], [rN=rM+[rO+].s] | |
2587 | ||
2588 | Either way, consume the '['. */ | |
2589 | (*cPP)++; | |
2590 | ||
2591 | /* Get the rN register. */ | |
2592 | if (! get_gen_reg (cPP, src_regnop)) | |
2593 | /* If there was no register, then this cannot match. */ | |
2594 | return 0; | |
2595 | else | |
2596 | { | |
2597 | /* We got the register, now check the next character. */ | |
2598 | switch (**cPP) | |
2599 | { | |
2600 | case ']': | |
2601 | /* Indirect mode. We're done here. */ | |
2602 | prefixp->kind = PREFIX_NONE; | |
2603 | *is_autoincp = 0; | |
2604 | break; | |
2605 | ||
2606 | case '+': | |
2607 | /* This must be an auto-increment mode, if there's a | |
2608 | match. */ | |
2609 | prefixp->kind = PREFIX_NONE; | |
2610 | *is_autoincp = 1; | |
2611 | ||
2612 | /* We consume this character and break out to check the | |
2613 | closing ']'. */ | |
2614 | (*cPP)++; | |
2615 | break; | |
2616 | ||
2617 | case '=': | |
2618 | /* This must be indexed with assign, or offset with assign | |
ae57792d HPN |
2619 | to match. Not supported for crisv32 or in |
2620 | compatibility mode. */ | |
2621 | if (cris_arch == arch_crisv32 | |
2622 | || cris_arch == arch_cris_common_v10_v32) | |
2623 | return 0; | |
2624 | ||
3bcbcc3d HPN |
2625 | (*cPP)++; |
2626 | ||
2627 | /* Either way, the next thing must be a register. */ | |
2628 | if (! get_gen_reg (cPP, &prefixp->base_reg_number)) | |
2629 | /* No register, no match. */ | |
2630 | return 0; | |
2631 | else | |
2632 | { | |
2633 | /* We've consumed "[rN=rM", so we must be looking at | |
2634 | "+rO.s]" or "+I]", or "-I]", or "+[rO].s]" or | |
2635 | "+[rO+].s]". */ | |
2636 | if (**cPP == '+') | |
2637 | { | |
2638 | int index_reg_number; | |
2639 | (*cPP)++; | |
2640 | ||
2641 | if (**cPP == '[') | |
2642 | { | |
2643 | int size_bits; | |
2644 | /* This must be [rx=ry+[rz].s] or | |
2645 | [rx=ry+[rz+].s] or no match. We must be | |
2646 | looking at rz after consuming the '['. */ | |
2647 | (*cPP)++; | |
2648 | ||
2649 | if (!get_gen_reg (cPP, &index_reg_number)) | |
2650 | return 0; | |
2651 | ||
2652 | prefixp->kind = PREFIX_BDAP; | |
2653 | prefixp->opcode | |
2654 | = (BDAP_INDIR_OPCODE | |
2655 | + (prefixp->base_reg_number << 12) | |
2656 | + index_reg_number); | |
2657 | ||
2658 | if (**cPP == '+') | |
2659 | { | |
2660 | /* We've seen "[rx=ry+[rz+" here, so now we | |
2661 | know that there must be "].s]" left to | |
2662 | check. */ | |
2663 | (*cPP)++; | |
2664 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
2665 | } | |
2666 | ||
2667 | /* If it wasn't autoincrement, we don't need to | |
2668 | add anything. */ | |
2669 | ||
2670 | /* Check the next-to-last ']'. */ | |
2671 | if (**cPP != ']') | |
2672 | return 0; | |
2673 | ||
2674 | (*cPP)++; | |
2675 | ||
2676 | /* Check the ".s" modifier. */ | |
2677 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
2678 | return 0; | |
2679 | ||
2680 | prefixp->opcode |= size_bits << 4; | |
2681 | ||
2682 | /* Now we got [rx=ry+[rz+].s or [rx=ry+[rz].s. | |
2683 | We break out to check the final ']'. */ | |
2684 | break; | |
2685 | } | |
ab3e48dc KH |
2686 | /* It wasn't an indirection. Check if it's a |
2687 | register. */ | |
2688 | else if (get_gen_reg (cPP, &index_reg_number)) | |
47926f60 KH |
2689 | { |
2690 | int size_bits; | |
2691 | ||
2692 | /* Indexed with assign mode: "[rN+rM.S]". */ | |
2693 | prefixp->kind = PREFIX_BIAP; | |
2694 | prefixp->opcode | |
2695 | = (BIAP_OPCODE + (index_reg_number << 12) | |
2696 | + prefixp->base_reg_number /* << 0 */); | |
2697 | ||
2698 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
2699 | /* Size missing, this isn't a match. */ | |
2700 | return 0; | |
2701 | else | |
3bcbcc3d | 2702 | { |
47926f60 | 2703 | /* Size found, break out to check the |
3bcbcc3d | 2704 | final ']'. */ |
47926f60 | 2705 | prefixp->opcode |= size_bits << 4; |
3bcbcc3d HPN |
2706 | break; |
2707 | } | |
47926f60 KH |
2708 | } |
2709 | /* Not a register. Then this must be "[rN+I]". */ | |
2710 | else if (cris_get_expression (cPP, &prefixp->expr)) | |
2711 | { | |
2712 | /* We've got offset with assign mode. Fill | |
2713 | in the blanks and break out to match the | |
2714 | final ']'. */ | |
2715 | prefixp->kind = PREFIX_BDAP_IMM; | |
08caf3f8 HPN |
2716 | |
2717 | /* We tentatively put an opcode corresponding to | |
2718 | a 32-bit operand here, although it may be | |
2719 | relaxed when there's no PIC specifier for the | |
2720 | operand. */ | |
2721 | prefixp->opcode | |
2722 | = (BDAP_INDIR_OPCODE | |
2723 | | (prefixp->base_reg_number << 12) | |
2724 | | (AUTOINCR_BIT << 8) | |
2725 | | (2 << 4) | |
2726 | | REG_PC /* << 0 */); | |
2727 | ||
2728 | /* This can have a PIC suffix, specifying reloc | |
2729 | type to use. */ | |
2730 | if (pic && **cPP == PIC_SUFFIX_CHAR) | |
2731 | { | |
2732 | unsigned int relocsize; | |
2733 | ||
2734 | cris_get_pic_suffix (cPP, &prefixp->reloc, | |
2735 | &prefixp->expr); | |
2736 | ||
2737 | /* Tweak the size of the immediate operand | |
2738 | in the prefix opcode if it isn't what we | |
2739 | set. */ | |
2740 | relocsize | |
2741 | = cris_get_pic_reloc_size (prefixp->reloc); | |
2742 | if (relocsize != 4) | |
2743 | prefixp->opcode | |
2744 | = ((prefixp->opcode & ~(3 << 4)) | |
2745 | | ((relocsize >> 1) << 4)); | |
2746 | } | |
47926f60 KH |
2747 | break; |
2748 | } | |
2749 | else | |
2750 | /* Neither register nor expression found, so | |
2751 | this can't be a match. */ | |
2752 | return 0; | |
3bcbcc3d | 2753 | } |
47926f60 | 2754 | /* Not "[rN+" but perhaps "[rN-"? */ |
ab3e48dc | 2755 | else if (**cPP == '-') |
47926f60 KH |
2756 | { |
2757 | /* We must have an offset with assign mode. */ | |
2758 | if (! cris_get_expression (cPP, &prefixp->expr)) | |
2759 | /* No expression, no match. */ | |
2760 | return 0; | |
2761 | else | |
2762 | { | |
2763 | /* We've got offset with assign mode. Fill | |
2764 | in the blanks and break out to match the | |
08caf3f8 HPN |
2765 | final ']'. |
2766 | ||
2767 | Note that we don't allow a PIC suffix for an | |
2768 | operand with a minus sign. */ | |
47926f60 KH |
2769 | prefixp->kind = PREFIX_BDAP_IMM; |
2770 | break; | |
2771 | } | |
2772 | } | |
2773 | else | |
2774 | /* Neither '+' nor '-' after "[rN=rM". Lose. */ | |
2775 | return 0; | |
3bcbcc3d HPN |
2776 | } |
2777 | default: | |
2778 | /* Neither ']' nor '+' nor '=' after "[rN". Lose. */ | |
2779 | return 0; | |
2780 | } | |
2781 | } | |
2782 | ||
2783 | /* When we get here, we have a match and will just check the closing | |
2784 | ']'. We can still fail though. */ | |
2785 | if (**cPP != ']') | |
2786 | return 0; | |
2787 | else | |
2788 | { | |
2789 | /* Don't forget to consume the final ']'. | |
2790 | Then return in glory. */ | |
2791 | (*cPP)++; | |
2792 | return 1; | |
2793 | } | |
2794 | } | |
47926f60 | 2795 | /* No indirection. Perhaps a constant? */ |
ab3e48dc | 2796 | else if (cris_get_expression (cPP, imm_exprP)) |
47926f60 KH |
2797 | { |
2798 | /* Expression found, this is immediate mode. */ | |
2799 | prefixp->kind = PREFIX_NONE; | |
2800 | *is_autoincp = 1; | |
2801 | *src_regnop = REG_PC; | |
2802 | *imm_foundp = 1; | |
08caf3f8 HPN |
2803 | |
2804 | /* This can have a PIC suffix, specifying reloc type to use. The | |
2805 | caller must check that the reloc size matches the operand size. */ | |
2806 | if (pic && **cPP == PIC_SUFFIX_CHAR) | |
2807 | cris_get_pic_suffix (cPP, &prefixp->reloc, imm_exprP); | |
2808 | ||
47926f60 KH |
2809 | return 1; |
2810 | } | |
3bcbcc3d HPN |
2811 | |
2812 | /* No luck today. */ | |
2813 | return 0; | |
2814 | } | |
2815 | ||
3bcbcc3d HPN |
2816 | /* This function gets an indirect operand in a three-address operand |
2817 | combination from the string pointed out by *cPP. The pointer *cPP is | |
2818 | advanced to the character following the indirect operand on success, or | |
2819 | has an unspecified value on failure. | |
2820 | ||
2d2255b5 | 2821 | cPP Pointer to pointer to string beginning |
3bcbcc3d HPN |
2822 | with the operand |
2823 | ||
2824 | prefixp Pointer to structure containing an | |
2825 | instruction prefix | |
2826 | ||
2827 | Returns 1 iff a correct indirect operand is found. */ | |
2828 | ||
2829 | static int | |
2830 | get_3op_or_dip_prefix_op (cPP, prefixp) | |
2831 | char **cPP; | |
2832 | struct cris_prefix *prefixp; | |
2833 | { | |
ab3e48dc KH |
2834 | int reg_number; |
2835 | ||
3bcbcc3d HPN |
2836 | if (**cPP != '[') |
2837 | /* We must have a '[' or it's a clean failure. */ | |
2838 | return 0; | |
3bcbcc3d | 2839 | |
47926f60 KH |
2840 | /* Eat the first '['. */ |
2841 | (*cPP)++; | |
2842 | ||
2843 | if (**cPP == '[') | |
2844 | { | |
2845 | /* A second '[', so this must be double-indirect mode. */ | |
3bcbcc3d | 2846 | (*cPP)++; |
47926f60 KH |
2847 | prefixp->kind = PREFIX_DIP; |
2848 | prefixp->opcode = DIP_OPCODE; | |
3bcbcc3d | 2849 | |
47926f60 KH |
2850 | /* Get the register or fail entirely. */ |
2851 | if (! get_gen_reg (cPP, ®_number)) | |
2852 | return 0; | |
2853 | else | |
3bcbcc3d | 2854 | { |
47926f60 KH |
2855 | prefixp->opcode |= reg_number /* << 0 */ ; |
2856 | if (**cPP == '+') | |
2857 | { | |
2858 | /* Since we found a '+', this must be double-indirect | |
2859 | autoincrement mode. */ | |
2860 | (*cPP)++; | |
2861 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
2862 | } | |
2863 | ||
2864 | /* There's nothing particular to do, if this was a | |
2865 | double-indirect *without* autoincrement. */ | |
2866 | } | |
2867 | ||
2868 | /* Check the first ']'. The second one is checked at the end. */ | |
2869 | if (**cPP != ']') | |
2870 | return 0; | |
2871 | ||
2872 | /* Eat the first ']', so we'll be looking at a second ']'. */ | |
2873 | (*cPP)++; | |
2874 | } | |
2875 | /* No second '['. Then we should have a register here, making | |
2876 | it "[rN". */ | |
2877 | else if (get_gen_reg (cPP, &prefixp->base_reg_number)) | |
2878 | { | |
2879 | /* This must be indexed or offset mode: "[rN+I]" or | |
2880 | "[rN+rM.S]" or "[rN+[rM].S]" or "[rN+[rM+].S]". */ | |
2881 | if (**cPP == '+') | |
2882 | { | |
47926f60 KH |
2883 | int index_reg_number; |
2884 | ||
3bcbcc3d | 2885 | (*cPP)++; |
3bcbcc3d | 2886 | |
47926f60 | 2887 | if (**cPP == '[') |
3bcbcc3d | 2888 | { |
47926f60 KH |
2889 | /* This is "[rx+["... Expect a register next. */ |
2890 | int size_bits; | |
2891 | (*cPP)++; | |
2892 | ||
2893 | if (!get_gen_reg (cPP, &index_reg_number)) | |
2894 | return 0; | |
2895 | ||
2896 | prefixp->kind = PREFIX_BDAP; | |
2897 | prefixp->opcode | |
2898 | = (BDAP_INDIR_OPCODE | |
2899 | + (prefixp->base_reg_number << 12) | |
2900 | + index_reg_number); | |
2901 | ||
2902 | /* We've seen "[rx+[ry", so check if this is | |
2903 | autoincrement. */ | |
3bcbcc3d HPN |
2904 | if (**cPP == '+') |
2905 | { | |
47926f60 | 2906 | /* Yep, now at "[rx+[ry+". */ |
3bcbcc3d HPN |
2907 | (*cPP)++; |
2908 | prefixp->opcode |= AUTOINCR_BIT << 8; | |
2909 | } | |
47926f60 KH |
2910 | /* If it wasn't autoincrement, we don't need to |
2911 | add anything. */ | |
3bcbcc3d | 2912 | |
47926f60 KH |
2913 | /* Check a first closing ']': "[rx+[ry]" or |
2914 | "[rx+[ry+]". */ | |
2915 | if (**cPP != ']') | |
2916 | return 0; | |
2917 | (*cPP)++; | |
3bcbcc3d | 2918 | |
47926f60 KH |
2919 | /* Now expect a size modifier ".S". */ |
2920 | if (! get_bwd_size_modifier (cPP, &size_bits)) | |
2921 | return 0; | |
3bcbcc3d | 2922 | |
47926f60 KH |
2923 | prefixp->opcode |= size_bits << 4; |
2924 | ||
2925 | /* Ok, all interesting stuff has been seen: | |
2926 | "[rx+[ry+].S" or "[rx+[ry].S". We only need to | |
2927 | expect a final ']', which we'll do in a common | |
2928 | closing session. */ | |
2929 | } | |
2930 | /* Seen "[rN+", but not a '[', so check if we have a | |
2931 | register. */ | |
2932 | else if (get_gen_reg (cPP, &index_reg_number)) | |
2933 | { | |
2934 | /* This is indexed mode: "[rN+rM.S]" or | |
2935 | "[rN+rM.S+]". */ | |
2936 | int size_bits; | |
2937 | prefixp->kind = PREFIX_BIAP; | |
2938 | prefixp->opcode | |
2939 | = (BIAP_OPCODE | |
2940 | | prefixp->base_reg_number /* << 0 */ | |
2941 | | (index_reg_number << 12)); | |
2942 | ||
07e90ad5 | 2943 | /* Consume the ".S". */ |
47926f60 KH |
2944 | if (! get_bwd_size_modifier (cPP, &size_bits)) |
2945 | /* Missing size, so fail. */ | |
2946 | return 0; | |
3bcbcc3d | 2947 | else |
47926f60 KH |
2948 | /* Size found. Add that piece and drop down to |
2949 | the common checking of the closing ']'. */ | |
2950 | prefixp->opcode |= size_bits << 4; | |
2951 | } | |
2952 | /* Seen "[rN+", but not a '[' or a register, so then | |
ae57792d HPN |
2953 | it must be a constant "I". |
2954 | ||
2955 | As a quality of implementation improvement, we check for a | |
2956 | closing ']', like in an erroneous "[rN+]". If we don't, | |
2957 | the expression parser will emit a confusing "bad | |
2958 | expression" when it sees the ']', probably because it | |
2959 | doesn't like seeing no expression. */ | |
2960 | else if (**cPP != ']' && cris_get_expression (cPP, &prefixp->expr)) | |
47926f60 KH |
2961 | { |
2962 | /* Expression found, so fill in the bits of offset | |
2963 | mode and drop down to check the closing ']'. */ | |
2964 | prefixp->kind = PREFIX_BDAP_IMM; | |
08caf3f8 HPN |
2965 | |
2966 | /* We tentatively put an opcode corresponding to a 32-bit | |
2967 | operand here, although it may be relaxed when there's no | |
2968 | PIC specifier for the operand. */ | |
2969 | prefixp->opcode | |
2970 | = (BDAP_INDIR_OPCODE | |
2971 | | (prefixp->base_reg_number << 12) | |
2972 | | (AUTOINCR_BIT << 8) | |
2973 | | (2 << 4) | |
2974 | | REG_PC /* << 0 */); | |
2975 | ||
2976 | /* This can have a PIC suffix, specifying reloc type to use. */ | |
2977 | if (pic && **cPP == PIC_SUFFIX_CHAR) | |
2978 | { | |
2979 | unsigned int relocsize; | |
2980 | ||
2981 | cris_get_pic_suffix (cPP, &prefixp->reloc, &prefixp->expr); | |
2982 | ||
2983 | /* Tweak the size of the immediate operand in the prefix | |
2984 | opcode if it isn't what we set. */ | |
2985 | relocsize = cris_get_pic_reloc_size (prefixp->reloc); | |
2986 | if (relocsize != 4) | |
2987 | prefixp->opcode | |
2988 | = ((prefixp->opcode & ~(3 << 4)) | |
2989 | | ((relocsize >> 1) << 4)); | |
2990 | } | |
47926f60 KH |
2991 | } |
2992 | else | |
2993 | /* Nothing valid here: lose. */ | |
2994 | return 0; | |
2995 | } | |
2996 | /* Seen "[rN" but no '+', so check if it's a '-'. */ | |
2997 | else if (**cPP == '-') | |
2998 | { | |
2999 | /* Yep, we must have offset mode. */ | |
3000 | if (! cris_get_expression (cPP, &prefixp->expr)) | |
3001 | /* No expression, so we lose. */ | |
3002 | return 0; | |
3003 | else | |
3004 | { | |
3005 | /* Expression found to make this offset mode, so | |
3006 | fill those bits and drop down to check the | |
08caf3f8 HPN |
3007 | closing ']'. |
3008 | ||
3009 | Note that we don't allow a PIC suffix for | |
3010 | an operand with a minus sign like this. */ | |
47926f60 KH |
3011 | prefixp->kind = PREFIX_BDAP_IMM; |
3012 | } | |
3013 | } | |
3014 | else | |
3015 | { | |
3016 | /* We've seen "[rN", but not '+' or '-'; rather a ']'. | |
3017 | Hmm. Normally this is a simple indirect mode that we | |
3018 | shouldn't match, but if we expect ']', then we have a | |
3019 | zero offset, so it can be a three-address-operand, | |
3020 | like "[rN],rO,rP", thus offset mode. | |
3021 | ||
3022 | Don't eat the ']', that will be done in the closing | |
3023 | ceremony. */ | |
3024 | prefixp->expr.X_op = O_constant; | |
3025 | prefixp->expr.X_add_number = 0; | |
3026 | prefixp->expr.X_add_symbol = NULL; | |
3027 | prefixp->expr.X_op_symbol = NULL; | |
3028 | prefixp->kind = PREFIX_BDAP_IMM; | |
3029 | } | |
3030 | } | |
3031 | /* A '[', but no second '[', and no register. Check if we | |
3032 | have an expression, making this "[I]" for a double-indirect | |
3033 | prefix. */ | |
3034 | else if (cris_get_expression (cPP, &prefixp->expr)) | |
3035 | { | |
3036 | /* Expression found, the so called absolute mode for a | |
3037 | double-indirect prefix on PC. */ | |
3038 | prefixp->kind = PREFIX_DIP; | |
3039 | prefixp->opcode = DIP_OPCODE | (AUTOINCR_BIT << 8) | REG_PC; | |
3040 | prefixp->reloc = BFD_RELOC_32; | |
3041 | } | |
3042 | else | |
3043 | /* Neither '[' nor register nor expression. We lose. */ | |
3044 | return 0; | |
3bcbcc3d HPN |
3045 | |
3046 | /* We get here as a closing ceremony to a successful match. We just | |
3047 | need to check the closing ']'. */ | |
3048 | if (**cPP != ']') | |
3049 | /* Oops. Close but no air-polluter. */ | |
3050 | return 0; | |
3051 | ||
3052 | /* Don't forget to consume that ']', before returning in glory. */ | |
3053 | (*cPP)++; | |
3054 | return 1; | |
3055 | } | |
3056 | ||
3bcbcc3d HPN |
3057 | /* Get an expression from the string pointed out by *cPP. |
3058 | The pointer *cPP is advanced to the character following the expression | |
3059 | on a success, or retains its original value otherwise. | |
3060 | ||
3061 | cPP Pointer to pointer to string beginning with the expression. | |
3062 | ||
3063 | exprP Pointer to structure containing the expression. | |
3064 | ||
47926f60 | 3065 | Return 1 iff a correct expression is found. */ |
3bcbcc3d HPN |
3066 | |
3067 | static int | |
3068 | cris_get_expression (cPP, exprP) | |
47926f60 KH |
3069 | char **cPP; |
3070 | expressionS *exprP; | |
3bcbcc3d HPN |
3071 | { |
3072 | char *saved_input_line_pointer; | |
3073 | segT exp; | |
3074 | ||
3075 | /* The "expression" function expects to find an expression at the | |
3076 | global variable input_line_pointer, so we have to save it to give | |
3077 | the impression that we don't fiddle with global variables. */ | |
3078 | saved_input_line_pointer = input_line_pointer; | |
3079 | input_line_pointer = *cPP; | |
3080 | ||
ae57792d HPN |
3081 | /* Avoid a common error, confusing addressing modes. Beware that the |
3082 | call to expression below does not signal that error; it treats [] | |
3083 | as parentheses, unless #define NEED_INDEX_OPERATOR in which case it | |
3084 | gives them other confusing semantics rather than plain outlawing | |
3085 | them, which is what we want. */ | |
3086 | if (*input_line_pointer == '[') | |
3087 | { | |
3088 | input_line_pointer = saved_input_line_pointer; | |
3089 | return 0; | |
3090 | } | |
3091 | ||
3bcbcc3d HPN |
3092 | exp = expression (exprP); |
3093 | if (exprP->X_op == O_illegal || exprP->X_op == O_absent) | |
3094 | { | |
3095 | input_line_pointer = saved_input_line_pointer; | |
3096 | return 0; | |
3097 | } | |
3098 | ||
3099 | /* Everything seems to be fine, just restore the global | |
3100 | input_line_pointer and say we're successful. */ | |
3101 | *cPP = input_line_pointer; | |
3102 | input_line_pointer = saved_input_line_pointer; | |
3103 | return 1; | |
3104 | } | |
3105 | ||
3bcbcc3d HPN |
3106 | /* Get a sequence of flag characters from *spp. The pointer *cPP is |
3107 | advanced to the character following the expression. The flag | |
3108 | characters are consecutive, no commas or spaces. | |
3109 | ||
3110 | cPP Pointer to pointer to string beginning with the expression. | |
3111 | ||
3112 | flagp Pointer to int to return the flags expression. | |
3113 | ||
3114 | Return 1 iff a correct flags expression is found. */ | |
3115 | ||
3116 | static int | |
3117 | get_flags (cPP, flagsp) | |
3118 | char **cPP; | |
3119 | int *flagsp; | |
3120 | { | |
3121 | for (;;) | |
3122 | { | |
3123 | switch (**cPP) | |
3124 | { | |
3125 | case 'd': | |
3126 | case 'D': | |
ae57792d HPN |
3127 | if (! cris_insn_ver_valid_for_arch (cris_ver_v0_3, |
3128 | cris_arch)) | |
3129 | return 0; | |
3130 | *flagsp |= 0x80; | |
3131 | break; | |
3132 | ||
3bcbcc3d HPN |
3133 | case 'm': |
3134 | case 'M': | |
ae57792d HPN |
3135 | if (! cris_insn_ver_valid_for_arch (cris_ver_v8_10, |
3136 | cris_arch)) | |
3137 | return 0; | |
3bcbcc3d HPN |
3138 | *flagsp |= 0x80; |
3139 | break; | |
3140 | ||
3141 | case 'e': | |
3142 | case 'E': | |
ae57792d HPN |
3143 | if (! cris_insn_ver_valid_for_arch (cris_ver_v0_3, |
3144 | cris_arch)) | |
3145 | return 0; | |
3146 | *flagsp |= 0x40; | |
3147 | break; | |
3148 | ||
3bcbcc3d HPN |
3149 | case 'b': |
3150 | case 'B': | |
ae57792d HPN |
3151 | if (! cris_insn_ver_valid_for_arch (cris_ver_v8_10, |
3152 | cris_arch)) | |
3153 | return 0; | |
3154 | *flagsp |= 0x40; | |
3155 | break; | |
3156 | ||
3157 | case 'p': | |
3158 | case 'P': | |
3159 | if (! cris_insn_ver_valid_for_arch (cris_ver_v32p, | |
3160 | cris_arch)) | |
3161 | return 0; | |
3162 | *flagsp |= 0x80; | |
3163 | break; | |
3164 | ||
3165 | case 'u': | |
3166 | case 'U': | |
3167 | if (! cris_insn_ver_valid_for_arch (cris_ver_v32p, | |
3168 | cris_arch)) | |
3169 | return 0; | |
3bcbcc3d HPN |
3170 | *flagsp |= 0x40; |
3171 | break; | |
3172 | ||
3173 | case 'i': | |
3174 | case 'I': | |
3175 | *flagsp |= 0x20; | |
3176 | break; | |
3177 | ||
3178 | case 'x': | |
3179 | case 'X': | |
3180 | *flagsp |= 0x10; | |
3181 | break; | |
3182 | ||
3183 | case 'n': | |
3184 | case 'N': | |
3185 | *flagsp |= 0x8; | |
3186 | break; | |
3187 | ||
3188 | case 'z': | |
3189 | case 'Z': | |
3190 | *flagsp |= 0x4; | |
3191 | break; | |
3192 | ||
3193 | case 'v': | |
3194 | case 'V': | |
3195 | *flagsp |= 0x2; | |
3196 | break; | |
3197 | ||
3198 | case 'c': | |
3199 | case 'C': | |
3200 | *flagsp |= 1; | |
3201 | break; | |
3202 | ||
3203 | default: | |
3204 | /* We consider this successful if we stop at a comma or | |
47926f60 | 3205 | whitespace. Anything else, and we consider it a failure. */ |
3bcbcc3d HPN |
3206 | if (**cPP != ',' |
3207 | && **cPP != 0 | |
3882b010 | 3208 | && ! ISSPACE (**cPP)) |
3bcbcc3d HPN |
3209 | return 0; |
3210 | else | |
3211 | return 1; | |
3212 | } | |
3213 | ||
3214 | /* Don't forget to consume each flag character. */ | |
3215 | (*cPP)++; | |
3216 | } | |
3217 | } | |
3218 | ||
3bcbcc3d | 3219 | /* Generate code and fixes for a BDAP prefix. |
ae57792d HPN |
3220 | For v32, this handles ADDOQ because thankfully the opcodes are the |
3221 | same. | |
3bcbcc3d HPN |
3222 | |
3223 | base_regno Int containing the base register number. | |
3224 | ||
3225 | exprP Pointer to structure containing the offset expression. */ | |
3226 | ||
3227 | static void | |
3228 | gen_bdap (base_regno, exprP) | |
47926f60 KH |
3229 | int base_regno; |
3230 | expressionS *exprP; | |
3bcbcc3d HPN |
3231 | { |
3232 | unsigned int opcode; | |
3233 | char *opcodep; | |
3234 | ||
3235 | /* Put out the prefix opcode; assume quick immediate mode at first. */ | |
3236 | opcode = BDAP_QUICK_OPCODE | (base_regno << 12); | |
ed67db7a | 3237 | opcodep = cris_insn_first_word_frag (); |
3bcbcc3d HPN |
3238 | md_number_to_chars (opcodep, opcode, 2); |
3239 | ||
3240 | if (exprP->X_op == O_constant) | |
3241 | { | |
3242 | /* We have an absolute expression that we know the size of right | |
47926f60 | 3243 | now. */ |
3bcbcc3d HPN |
3244 | long int value; |
3245 | int size; | |
3246 | ||
3247 | value = exprP->X_add_number; | |
3248 | if (value < -32768 || value > 32767) | |
3249 | /* Outside range for a "word", make it a dword. */ | |
3250 | size = 2; | |
3251 | else | |
47926f60 | 3252 | /* Assume "word" size. */ |
3bcbcc3d HPN |
3253 | size = 1; |
3254 | ||
3255 | /* If this is a signed-byte value, we can fit it into the prefix | |
3256 | insn itself. */ | |
3257 | if (value >= -128 && value <= 127) | |
3258 | opcodep[0] = value; | |
3259 | else | |
3260 | { | |
3261 | /* This is a word or dword displacement, which will be put in a | |
3262 | word or dword after the prefix. */ | |
3263 | char *p; | |
3264 | ||
3265 | opcodep[0] = BDAP_PC_LOW + (size << 4); | |
3266 | opcodep[1] &= 0xF0; | |
3267 | opcodep[1] |= BDAP_INCR_HIGH; | |
3268 | p = frag_more (1 << size); | |
3269 | md_number_to_chars (p, value, 1 << size); | |
3270 | } | |
3271 | } | |
3272 | else | |
08caf3f8 HPN |
3273 | { |
3274 | /* Handle complex expressions. */ | |
3275 | valueT addvalue | |
1c971160 | 3276 | = SIMPLE_EXPR (exprP) ? exprP->X_add_number : 0; |
08caf3f8 | 3277 | symbolS *sym |
1c971160 HPN |
3278 | = (SIMPLE_EXPR (exprP) |
3279 | ? exprP->X_add_symbol : make_expr_symbol (exprP)); | |
08caf3f8 HPN |
3280 | |
3281 | /* The expression is not defined yet but may become absolute. We | |
3282 | make it a relocation to be relaxed. */ | |
3283 | frag_var (rs_machine_dependent, 4, 0, | |
3284 | ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF), | |
3285 | sym, addvalue, opcodep); | |
3286 | } | |
3bcbcc3d HPN |
3287 | } |
3288 | ||
3bcbcc3d HPN |
3289 | /* Encode a branch displacement in the range -256..254 into the form used |
3290 | by CRIS conditional branch instructions. | |
3291 | ||
3292 | offset The displacement value in bytes. */ | |
3293 | ||
3294 | static int | |
3295 | branch_disp (offset) | |
3296 | int offset; | |
3297 | { | |
3298 | int disp; | |
3299 | ||
ae57792d HPN |
3300 | /* Adjust all short branch offsets here. */ |
3301 | if (cris_arch == arch_crisv32 || cris_arch == arch_cris_common_v10_v32) | |
3302 | offset += 2; | |
3303 | ||
3bcbcc3d HPN |
3304 | disp = offset & 0xFE; |
3305 | ||
3306 | if (offset < 0) | |
3307 | disp |= 1; | |
3308 | ||
3309 | return disp; | |
3310 | } | |
3311 | ||
3bcbcc3d HPN |
3312 | /* Generate code and fixes for a 32-bit conditional branch instruction |
3313 | created by "extending" an existing 8-bit branch instruction. | |
3314 | ||
3315 | opcodep Pointer to the word containing the original 8-bit branch | |
3316 | instruction. | |
3317 | ||
3318 | writep Pointer to "extension area" following the first instruction | |
3319 | word. | |
3320 | ||
3321 | fragP Pointer to the frag containing the instruction. | |
3322 | ||
3323 | add_symP, Parts of the destination address expression. | |
3324 | sub_symP, | |
3325 | add_num. */ | |
3326 | ||
3327 | static void | |
3328 | gen_cond_branch_32 (opcodep, writep, fragP, add_symP, sub_symP, add_num) | |
3329 | char *opcodep; | |
3330 | char *writep; | |
3331 | fragS *fragP; | |
3332 | symbolS *add_symP; | |
3333 | symbolS *sub_symP; | |
3334 | long int add_num; | |
3335 | { | |
ae57792d HPN |
3336 | int nop_opcode; |
3337 | int opc_offset; | |
3338 | int branch_offset; | |
3339 | ||
3340 | if (cris_arch == arch_crisv32) | |
3341 | { | |
3342 | nop_opcode = NOP_OPCODE_V32; | |
3343 | opc_offset = 10; | |
3344 | branch_offset = -2 - 8; | |
3345 | } | |
3346 | else | |
3347 | { | |
3348 | nop_opcode = NOP_OPCODE; | |
3349 | opc_offset = 8; | |
3350 | branch_offset = -2 - 6; | |
3351 | } | |
3352 | ||
3353 | /* We should never get here for compatibility mode. */ | |
3354 | if (cris_arch == arch_cris_common_v10_v32) | |
3355 | as_fatal (_("Calling gen_cond_branch_32 for .arch common_v10_v32\n")); | |
3356 | ||
3bcbcc3d | 3357 | if (warn_for_branch_expansion) |
08caf3f8 HPN |
3358 | as_warn_where (fragP->fr_file, fragP->fr_line, |
3359 | _("32-bit conditional branch generated")); | |
3bcbcc3d HPN |
3360 | |
3361 | /* Here, writep points to what will be opcodep + 2. First, we change | |
3362 | the actual branch in opcodep[0] and opcodep[1], so that in the | |
3363 | final insn, it will look like: | |
3364 | opcodep+10: Bcc .-6 | |
3365 | ||
3366 | This means we don't have to worry about changing the opcode or | |
08caf3f8 | 3367 | messing with the delay-slot instruction. So, we move it to last in |
3bcbcc3d HPN |
3368 | the "extended" branch, and just change the displacement. Admittedly, |
3369 | it's not the optimal extended construct, but we should get this | |
3370 | rarely enough that it shouldn't matter. */ | |
3371 | ||
ae57792d HPN |
3372 | writep[opc_offset] = branch_disp (branch_offset); |
3373 | writep[opc_offset + 1] = opcodep[1]; | |
3bcbcc3d HPN |
3374 | |
3375 | /* Then, we change the branch to an unconditional branch over the | |
3376 | extended part, to the new location of the Bcc: | |
3377 | opcodep: BA .+10 | |
3378 | opcodep+2: NOP | |
3379 | ||
3380 | Note that these two writes are to currently different locations, | |
3381 | merged later. */ | |
3382 | ||
ae57792d HPN |
3383 | md_number_to_chars (opcodep, BA_QUICK_OPCODE |
3384 | + (cris_arch == arch_crisv32 ? 12 : 8), 2); | |
3385 | md_number_to_chars (writep, nop_opcode, 2); | |
3bcbcc3d HPN |
3386 | |
3387 | /* Then the extended thing, the 32-bit jump insn. | |
08caf3f8 HPN |
3388 | opcodep+4: JUMP [PC+] |
3389 | or, in the PIC case, | |
3390 | opcodep+4: ADD [PC+],PC. */ | |
3bcbcc3d | 3391 | |
08caf3f8 | 3392 | md_number_to_chars (writep + 2, |
ae57792d HPN |
3393 | cris_arch == arch_crisv32 |
3394 | ? BA_DWORD_OPCODE | |
3395 | : (pic ? ADD_PC_INCR_OPCODE : JUMP_PC_INCR_OPCODE), 2); | |
3bcbcc3d HPN |
3396 | |
3397 | /* We have to fill in the actual value too. | |
3398 | opcodep+6: .DWORD | |
3399 | This is most probably an expression, but we can cope with an absolute | |
08caf3f8 | 3400 | value too. FIXME: Testcase needed with and without pic. */ |
3bcbcc3d HPN |
3401 | |
3402 | if (add_symP == NULL && sub_symP == NULL) | |
08caf3f8 HPN |
3403 | { |
3404 | /* An absolute address. */ | |
ae57792d | 3405 | if (pic || cris_arch == arch_crisv32) |
08caf3f8 HPN |
3406 | fix_new (fragP, writep + 4 - fragP->fr_literal, 4, |
3407 | section_symbol (absolute_section), | |
ae57792d HPN |
3408 | add_num |
3409 | + (cris_arch == arch_crisv32 ? 6 : 0), | |
3410 | 1, BFD_RELOC_32_PCREL); | |
08caf3f8 HPN |
3411 | else |
3412 | md_number_to_chars (writep + 4, add_num, 4); | |
3413 | } | |
3bcbcc3d HPN |
3414 | else |
3415 | { | |
08caf3f8 HPN |
3416 | if (sub_symP != NULL) |
3417 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
3418 | _("Complex expression not supported")); | |
3bcbcc3d | 3419 | |
08caf3f8 | 3420 | /* Not absolute, we have to make it a frag for later evaluation. */ |
3bcbcc3d | 3421 | fix_new (fragP, writep + 4 - fragP->fr_literal, 4, add_symP, |
ae57792d HPN |
3422 | add_num + (cris_arch == arch_crisv32 ? 6 : 0), |
3423 | pic || cris_arch == arch_crisv32 ? 1 : 0, | |
3424 | pic || cris_arch == arch_crisv32 | |
3425 | ? BFD_RELOC_32_PCREL : BFD_RELOC_32); | |
3bcbcc3d | 3426 | } |
ae57792d HPN |
3427 | |
3428 | if (cris_arch == arch_crisv32) | |
3429 | /* Follow it with a "NOP" for CRISv32. */ | |
3430 | md_number_to_chars (writep + 8, NOP_OPCODE_V32, 2); | |
3bcbcc3d HPN |
3431 | } |
3432 | ||
08caf3f8 HPN |
3433 | /* Get the size of an immediate-reloc in bytes. Only valid for PIC |
3434 | relocs. */ | |
3435 | ||
3436 | static unsigned int | |
3437 | cris_get_pic_reloc_size (reloc) | |
3438 | bfd_reloc_code_real_type reloc; | |
3439 | { | |
3440 | return reloc == BFD_RELOC_CRIS_16_GOTPLT || reloc == BFD_RELOC_CRIS_16_GOT | |
3441 | ? 2 : 4; | |
3442 | } | |
3443 | ||
3444 | /* Store a reloc type at *RELOCP corresponding to the PIC suffix at *CPP. | |
3445 | Adjust *EXPRP with any addend found after the PIC suffix. */ | |
3446 | ||
3447 | static void | |
3448 | cris_get_pic_suffix (cPP, relocp, exprP) | |
3449 | char **cPP; | |
3450 | bfd_reloc_code_real_type *relocp; | |
3451 | expressionS *exprP; | |
3452 | { | |
3453 | char *s = *cPP; | |
3454 | unsigned int i; | |
3455 | expressionS const_expr; | |
3456 | ||
3457 | const struct pic_suffixes_struct | |
3458 | { | |
3459 | const char *const suffix; | |
3460 | unsigned int len; | |
3461 | bfd_reloc_code_real_type reloc; | |
3462 | } pic_suffixes[] = | |
3463 | { | |
3464 | #undef PICMAP | |
3465 | #define PICMAP(s, r) {s, sizeof (s) - 1, r} | |
3466 | /* Keep this in order with longest unambiguous prefix first. */ | |
3467 | PICMAP ("GOTPLT16", BFD_RELOC_CRIS_16_GOTPLT), | |
3468 | PICMAP ("GOTPLT", BFD_RELOC_CRIS_32_GOTPLT), | |
3469 | PICMAP ("PLTG", BFD_RELOC_CRIS_32_PLT_GOTREL), | |
3470 | PICMAP ("PLT", BFD_RELOC_CRIS_32_PLT_PCREL), | |
3471 | PICMAP ("GOTOFF", BFD_RELOC_CRIS_32_GOTREL), | |
3472 | PICMAP ("GOT16", BFD_RELOC_CRIS_16_GOT), | |
3473 | PICMAP ("GOT", BFD_RELOC_CRIS_32_GOT) | |
3474 | }; | |
3475 | ||
3476 | /* We've already seen the ':', so consume it. */ | |
3477 | s++; | |
3478 | ||
3479 | for (i = 0; i < sizeof (pic_suffixes)/sizeof (pic_suffixes[0]); i++) | |
3480 | { | |
3481 | if (strncmp (s, pic_suffixes[i].suffix, pic_suffixes[i].len) == 0 | |
3482 | && ! is_part_of_name (s[pic_suffixes[i].len])) | |
3483 | { | |
3484 | /* We have a match. Consume the suffix and set the relocation | |
3485 | type. */ | |
3486 | s += pic_suffixes[i].len; | |
3487 | ||
3488 | /* There can be a constant term appended. If so, we will add it | |
3489 | to *EXPRP. */ | |
3490 | if (*s == '+' || *s == '-') | |
3491 | { | |
3492 | if (! cris_get_expression (&s, &const_expr)) | |
3493 | /* There was some kind of syntax error. Bail out. */ | |
3494 | break; | |
3495 | ||
3496 | /* Allow complex expressions as the constant part. It still | |
b6ff326e | 3497 | has to be an assembly-time constant or there will be an |
08caf3f8 | 3498 | error emitting the reloc. This makes the PIC qualifiers |
d551a338 | 3499 | idempotent; foo:GOTOFF+32 == foo+32:GOTOFF. The former we |
08caf3f8 HPN |
3500 | recognize here; the latter is parsed in the incoming |
3501 | expression. */ | |
3502 | exprP->X_add_symbol = make_expr_symbol (exprP); | |
3503 | exprP->X_op = O_add; | |
3504 | exprP->X_add_number = 0; | |
3505 | exprP->X_op_symbol = make_expr_symbol (&const_expr); | |
3506 | } | |
3507 | ||
3508 | *relocp = pic_suffixes[i].reloc; | |
3509 | *cPP = s; | |
3510 | return; | |
3511 | } | |
3512 | } | |
3513 | ||
3514 | /* No match. Don't consume anything; fall back and there will be a | |
3515 | syntax error. */ | |
3516 | } | |
3517 | ||
ae57792d | 3518 | /* This *could* have been: |
3bcbcc3d | 3519 | |
47926f60 KH |
3520 | Turn a string in input_line_pointer into a floating point constant |
3521 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
3522 | of LITTLENUMS emitted is stored in *SIZEP. | |
3bcbcc3d HPN |
3523 | |
3524 | type A character from FLTCHARS that describes what kind of | |
3525 | floating-point number is wanted. | |
3526 | ||
3527 | litp A pointer to an array that the result should be stored in. | |
3528 | ||
3529 | sizep A pointer to an integer where the size of the result is stored. | |
3530 | ||
3531 | But we don't support floating point constants in assembly code *at all*, | |
3532 | since it's suboptimal and just opens up bug opportunities. GCC emits | |
3533 | the bit patterns as hex. All we could do here is to emit what GCC | |
3534 | would have done in the first place. *Nobody* writes floating-point | |
3535 | code as assembly code, but if they do, they should be able enough to | |
3536 | find out the correct bit patterns and use them. */ | |
3537 | ||
3538 | char * | |
3539 | md_atof (type, litp, sizep) | |
3540 | char type ATTRIBUTE_UNUSED; | |
3541 | char *litp ATTRIBUTE_UNUSED; | |
47926f60 | 3542 | int *sizep ATTRIBUTE_UNUSED; |
3bcbcc3d HPN |
3543 | { |
3544 | /* FIXME: Is this function mentioned in the internals.texi manual? If | |
3545 | not, add it. */ | |
3546 | return _("Bad call to md_atof () - floating point formats are not supported"); | |
3547 | } | |
3548 | ||
3bcbcc3d HPN |
3549 | /* Turn a number as a fixS * into a series of bytes that represents the |
3550 | number on the target machine. The purpose of this procedure is the | |
3551 | same as that of md_number_to_chars but this procedure is supposed to | |
3552 | handle general bit field fixes and machine-dependent fixups. | |
3553 | ||
3554 | bufp Pointer to an array where the result should be stored. | |
3555 | ||
3556 | val The value to store. | |
3557 | ||
3558 | n The number of bytes in "val" that should be stored. | |
3559 | ||
08caf3f8 HPN |
3560 | fixP The fix to be applied to the bit field starting at bufp. |
3561 | ||
3562 | seg The segment containing this number. */ | |
3bcbcc3d HPN |
3563 | |
3564 | static void | |
08caf3f8 | 3565 | cris_number_to_imm (bufp, val, n, fixP, seg) |
3bcbcc3d HPN |
3566 | char *bufp; |
3567 | long val; | |
3568 | int n; | |
3569 | fixS *fixP; | |
08caf3f8 | 3570 | segT seg; |
3bcbcc3d HPN |
3571 | { |
3572 | segT sym_seg; | |
3573 | ||
3574 | know (n <= 4); | |
3575 | know (fixP); | |
3576 | ||
3577 | /* We put the relative "vma" for the other segment for inter-segment | |
3578 | relocations in the object data to stay binary "compatible" (with an | |
3579 | uninteresting old version) for the relocation. | |
3580 | Maybe delete some day. */ | |
3581 | if (fixP->fx_addsy | |
08caf3f8 | 3582 | && (sym_seg = S_GET_SEGMENT (fixP->fx_addsy)) != seg) |
3bcbcc3d HPN |
3583 | val += sym_seg->vma; |
3584 | ||
08caf3f8 HPN |
3585 | if (fixP->fx_addsy != NULL || fixP->fx_pcrel) |
3586 | switch (fixP->fx_r_type) | |
3587 | { | |
3588 | /* These must be fully resolved when getting here. */ | |
08caf3f8 HPN |
3589 | case BFD_RELOC_16_PCREL: |
3590 | case BFD_RELOC_8_PCREL: | |
ae57792d | 3591 | as_bad_where (fixP->fx_file, fixP->fx_line, |
08caf3f8 HPN |
3592 | _("PC-relative relocation must be trivially resolved")); |
3593 | default: | |
3594 | ; | |
3595 | } | |
3596 | ||
ae57792d HPN |
3597 | /* Only do this for old-arch binaries. */ |
3598 | if (cris_arch != arch_cris_any_v0_v10 | |
3599 | && (fixP->fx_addsy != NULL || fixP->fx_pcrel)) | |
3600 | return; | |
3601 | ||
3bcbcc3d HPN |
3602 | switch (fixP->fx_r_type) |
3603 | { | |
3604 | /* Ditto here, we put the addend into the object code as | |
3605 | well as the reloc addend. Keep it that way for now, to simplify | |
3606 | regression tests on the object file contents. FIXME: Seems | |
3607 | uninteresting now that we have a test suite. */ | |
3608 | ||
08caf3f8 HPN |
3609 | case BFD_RELOC_CRIS_16_GOT: |
3610 | case BFD_RELOC_CRIS_32_GOT: | |
3611 | case BFD_RELOC_CRIS_32_GOTREL: | |
3612 | case BFD_RELOC_CRIS_16_GOTPLT: | |
3613 | case BFD_RELOC_CRIS_32_GOTPLT: | |
3614 | case BFD_RELOC_CRIS_32_PLT_GOTREL: | |
3615 | case BFD_RELOC_CRIS_32_PLT_PCREL: | |
3616 | /* We don't want to put in any kind of non-zero bits in the data | |
3617 | being relocated for these. */ | |
3618 | break; | |
3619 | ||
08caf3f8 | 3620 | case BFD_RELOC_32_PCREL: |
ae57792d HPN |
3621 | /* If this one isn't fully resolved, we don't want to put anything |
3622 | in the object. */ | |
3623 | if (fixP->fx_addsy != NULL || fixP->fx_pcrel) | |
3624 | break; | |
3625 | ||
3626 | /* Fall through. */ | |
3627 | case BFD_RELOC_32: | |
3bcbcc3d HPN |
3628 | /* No use having warnings here, since most hosts have a 32-bit type |
3629 | for "long" (which will probably change soon, now that I wrote | |
3630 | this). */ | |
3631 | bufp[3] = (val >> 24) & 0xFF; | |
3632 | bufp[2] = (val >> 16) & 0xFF; | |
3633 | bufp[1] = (val >> 8) & 0xFF; | |
3634 | bufp[0] = val & 0xFF; | |
3635 | break; | |
3636 | ||
3637 | /* FIXME: The 16 and 8-bit cases should have a way to check | |
3638 | whether a signed or unsigned (or any signedness) number is | |
ae57792d | 3639 | accepted. */ |
3bcbcc3d HPN |
3640 | |
3641 | case BFD_RELOC_16: | |
08caf3f8 | 3642 | case BFD_RELOC_16_PCREL: |
3bcbcc3d | 3643 | if (val > 0xffff || val < -32768) |
ae57792d HPN |
3644 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3645 | _("Value not in 16 bit range: %ld"), val); | |
3646 | if (! fixP->fx_addsy) | |
3647 | { | |
3648 | bufp[1] = (val >> 8) & 0xFF; | |
3649 | bufp[0] = val & 0xFF; | |
3650 | } | |
3651 | break; | |
3652 | ||
3653 | case BFD_RELOC_CRIS_SIGNED_16: | |
3654 | if (val > 32767 || val < -32768) | |
3655 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3656 | _("Value not in 16 bit signed range: %ld"), val); | |
3bcbcc3d HPN |
3657 | if (! fixP->fx_addsy) |
3658 | { | |
3659 | bufp[1] = (val >> 8) & 0xFF; | |
3660 | bufp[0] = val & 0xFF; | |
3661 | } | |
3662 | break; | |
3663 | ||
3664 | case BFD_RELOC_8: | |
08caf3f8 | 3665 | case BFD_RELOC_8_PCREL: |
3bcbcc3d | 3666 | if (val > 255 || val < -128) |
ae57792d HPN |
3667 | as_bad_where (fixP->fx_file, fixP->fx_line, _("Value not in 8 bit range: %ld"), val); |
3668 | if (! fixP->fx_addsy) | |
3669 | bufp[0] = val & 0xFF; | |
3670 | break; | |
3671 | ||
3672 | case BFD_RELOC_CRIS_SIGNED_8: | |
3673 | if (val > 127 || val < -128) | |
3674 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3675 | _("Value not in 8 bit signed range: %ld"), val); | |
3bcbcc3d HPN |
3676 | if (! fixP->fx_addsy) |
3677 | bufp[0] = val & 0xFF; | |
3678 | break; | |
3679 | ||
ae57792d HPN |
3680 | case BFD_RELOC_CRIS_LAPCQ_OFFSET: |
3681 | /* FIXME: Test-cases for out-of-range values. Probably also need | |
3682 | to use as_bad_where. */ | |
3bcbcc3d HPN |
3683 | case BFD_RELOC_CRIS_UNSIGNED_4: |
3684 | if (val > 15 || val < 0) | |
ae57792d HPN |
3685 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3686 | _("Value not in 4 bit unsigned range: %ld"), val); | |
3bcbcc3d HPN |
3687 | if (! fixP->fx_addsy) |
3688 | bufp[0] |= val & 0x0F; | |
3689 | break; | |
3690 | ||
3691 | case BFD_RELOC_CRIS_UNSIGNED_5: | |
3692 | if (val > 31 || val < 0) | |
ae57792d HPN |
3693 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3694 | _("Value not in 5 bit unsigned range: %ld"), val); | |
3bcbcc3d HPN |
3695 | if (! fixP->fx_addsy) |
3696 | bufp[0] |= val & 0x1F; | |
3697 | break; | |
3698 | ||
3699 | case BFD_RELOC_CRIS_SIGNED_6: | |
3700 | if (val > 31 || val < -32) | |
ae57792d HPN |
3701 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3702 | _("Value not in 6 bit range: %ld"), val); | |
3bcbcc3d HPN |
3703 | if (! fixP->fx_addsy) |
3704 | bufp[0] |= val & 0x3F; | |
3705 | break; | |
3706 | ||
3707 | case BFD_RELOC_CRIS_UNSIGNED_6: | |
3708 | if (val > 63 || val < 0) | |
ae57792d HPN |
3709 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3710 | _("Value not in 6 bit unsigned range: %ld"), val); | |
3bcbcc3d HPN |
3711 | if (! fixP->fx_addsy) |
3712 | bufp[0] |= val & 0x3F; | |
3713 | break; | |
3714 | ||
3715 | case BFD_RELOC_CRIS_BDISP8: | |
3716 | if (! fixP->fx_addsy) | |
3717 | bufp[0] = branch_disp (val); | |
3718 | break; | |
3719 | ||
3720 | case BFD_RELOC_NONE: | |
3721 | /* May actually happen automatically. For example at broken | |
3722 | words, if the word turns out not to be broken. | |
47926f60 | 3723 | FIXME: When? Which testcase? */ |
3bcbcc3d HPN |
3724 | if (! fixP->fx_addsy) |
3725 | md_number_to_chars (bufp, val, n); | |
3726 | break; | |
3727 | ||
3728 | case BFD_RELOC_VTABLE_INHERIT: | |
3729 | /* This borrowed from tc-ppc.c on a whim. */ | |
3730 | if (fixP->fx_addsy | |
3731 | && !S_IS_DEFINED (fixP->fx_addsy) | |
3732 | && !S_IS_WEAK (fixP->fx_addsy)) | |
3733 | S_SET_WEAK (fixP->fx_addsy); | |
7b15d668 HPN |
3734 | /* Fall through. */ |
3735 | ||
3bcbcc3d | 3736 | case BFD_RELOC_VTABLE_ENTRY: |
3bcbcc3d HPN |
3737 | fixP->fx_done = 0; |
3738 | break; | |
3739 | ||
3740 | default: | |
3741 | BAD_CASE (fixP->fx_r_type); | |
3742 | } | |
3743 | } | |
3744 | ||
3bcbcc3d HPN |
3745 | /* Processes machine-dependent command line options. Called once for |
3746 | each option on the command line that the machine-independent part of | |
3747 | GAS does not understand. */ | |
47926f60 | 3748 | |
3bcbcc3d HPN |
3749 | int |
3750 | md_parse_option (arg, argp) | |
3751 | int arg; | |
3752 | char *argp ATTRIBUTE_UNUSED; | |
3753 | { | |
3754 | switch (arg) | |
3755 | { | |
3756 | case 'H': | |
3757 | case 'h': | |
7b15d668 | 3758 | printf (_("Please use --help to see usage and options for this assembler.\n")); |
3bcbcc3d | 3759 | md_show_usage (stdout); |
7b15d668 | 3760 | exit (EXIT_SUCCESS); |
3bcbcc3d HPN |
3761 | |
3762 | case 'N': | |
3763 | warn_for_branch_expansion = 1; | |
ae57792d | 3764 | break; |
3bcbcc3d | 3765 | |
7b15d668 | 3766 | case OPTION_NO_US: |
b34976b6 | 3767 | demand_register_prefix = TRUE; |
7b15d668 HPN |
3768 | |
3769 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
08caf3f8 | 3770 | as_bad (_("--no-underscore is invalid with a.out format")); |
7b15d668 | 3771 | else |
b34976b6 | 3772 | symbols_have_leading_underscore = FALSE; |
ae57792d | 3773 | break; |
7b15d668 HPN |
3774 | |
3775 | case OPTION_US: | |
b34976b6 AM |
3776 | demand_register_prefix = FALSE; |
3777 | symbols_have_leading_underscore = TRUE; | |
ae57792d | 3778 | break; |
7b15d668 | 3779 | |
08caf3f8 | 3780 | case OPTION_PIC: |
b34976b6 | 3781 | pic = TRUE; |
ae57792d HPN |
3782 | break; |
3783 | ||
3784 | case OPTION_ARCH: | |
3785 | { | |
3786 | char *str = argp; | |
3787 | enum cris_archs argarch = cris_arch_from_string (&str); | |
3788 | ||
3789 | if (argarch == arch_cris_unknown) | |
3790 | as_bad (_("invalid <arch> in --march=<arch>: %s"), argp); | |
3791 | else | |
3792 | cris_arch = argarch; | |
3793 | ||
3794 | if (argarch == arch_crisv32) | |
3795 | { | |
3796 | err_for_dangerous_mul_placement = 0; | |
3797 | md_long_jump_size = crisv32_long_jump_size; | |
3798 | } | |
3799 | else | |
3800 | md_long_jump_size = cris_any_v0_v10_long_jump_size; | |
3801 | } | |
3802 | break; | |
08caf3f8 | 3803 | |
1048a9ba HPN |
3804 | case OPTION_MULBUG_ABORT_OFF: |
3805 | err_for_dangerous_mul_placement = 0; | |
ae57792d | 3806 | break; |
1048a9ba HPN |
3807 | |
3808 | case OPTION_MULBUG_ABORT_ON: | |
3809 | err_for_dangerous_mul_placement = 1; | |
ae57792d | 3810 | break; |
1048a9ba | 3811 | |
3bcbcc3d HPN |
3812 | default: |
3813 | return 0; | |
47926f60 | 3814 | } |
ae57792d HPN |
3815 | |
3816 | return 1; | |
3bcbcc3d HPN |
3817 | } |
3818 | ||
3819 | /* Round up a section size to the appropriate boundary. */ | |
3820 | valueT | |
3821 | md_section_align (segment, size) | |
3822 | segT segment; | |
3823 | valueT size; | |
3824 | { | |
3825 | /* Round all sects to multiple of 4, except the bss section, which | |
3826 | we'll round to word-size. | |
3827 | ||
3828 | FIXME: Check if this really matters. All sections should be | |
3829 | rounded up, and all sections should (optionally) be assumed to be | |
3830 | dword-aligned, it's just that there is actual usage of linking to a | |
3831 | multiple of two. */ | |
3832 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
3833 | { | |
3834 | if (segment == bss_section) | |
3835 | return (size + 1) & ~1; | |
3836 | return (size + 3) & ~3; | |
3837 | } | |
3838 | else | |
3839 | { | |
3840 | /* FIXME: Is this wanted? It matches the testsuite, but that's not | |
3841 | really a valid reason. */ | |
3842 | if (segment == text_section) | |
3843 | return (size + 3) & ~3; | |
3844 | } | |
3845 | ||
3846 | return size; | |
3847 | } | |
3848 | ||
3bcbcc3d HPN |
3849 | /* Generate a machine-dependent relocation. */ |
3850 | arelent * | |
3851 | tc_gen_reloc (section, fixP) | |
3852 | asection *section ATTRIBUTE_UNUSED; | |
3853 | fixS *fixP; | |
3854 | { | |
3855 | arelent *relP; | |
3856 | bfd_reloc_code_real_type code; | |
3857 | ||
3858 | switch (fixP->fx_r_type) | |
3859 | { | |
ae57792d HPN |
3860 | case BFD_RELOC_CRIS_SIGNED_8: |
3861 | code = BFD_RELOC_8; | |
3862 | break; | |
3863 | ||
3864 | case BFD_RELOC_CRIS_SIGNED_16: | |
3865 | code = BFD_RELOC_16; | |
3866 | break; | |
3867 | ||
08caf3f8 HPN |
3868 | case BFD_RELOC_CRIS_16_GOT: |
3869 | case BFD_RELOC_CRIS_32_GOT: | |
3870 | case BFD_RELOC_CRIS_16_GOTPLT: | |
3871 | case BFD_RELOC_CRIS_32_GOTPLT: | |
3872 | case BFD_RELOC_CRIS_32_GOTREL: | |
3873 | case BFD_RELOC_CRIS_32_PLT_GOTREL: | |
3874 | case BFD_RELOC_CRIS_32_PLT_PCREL: | |
3bcbcc3d | 3875 | case BFD_RELOC_32: |
ae57792d | 3876 | case BFD_RELOC_32_PCREL: |
3bcbcc3d HPN |
3877 | case BFD_RELOC_16: |
3878 | case BFD_RELOC_8: | |
3879 | case BFD_RELOC_VTABLE_INHERIT: | |
3880 | case BFD_RELOC_VTABLE_ENTRY: | |
ae57792d HPN |
3881 | case BFD_RELOC_CRIS_UNSIGNED_8: |
3882 | case BFD_RELOC_CRIS_UNSIGNED_16: | |
3883 | case BFD_RELOC_CRIS_LAPCQ_OFFSET: | |
3bcbcc3d HPN |
3884 | code = fixP->fx_r_type; |
3885 | break; | |
3886 | default: | |
3887 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3888 | _("Semantics error. This type of operand can not be relocated, it must be an assembly-time constant")); | |
3889 | return 0; | |
3890 | } | |
3891 | ||
3892 | relP = (arelent *) xmalloc (sizeof (arelent)); | |
3893 | assert (relP != 0); | |
3894 | relP->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
3895 | *relP->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); | |
3896 | relP->address = fixP->fx_frag->fr_address + fixP->fx_where; | |
3897 | ||
ae57792d | 3898 | relP->addend = fixP->fx_offset; |
3bcbcc3d HPN |
3899 | |
3900 | /* This is the standard place for KLUDGEs to work around bugs in | |
3901 | bfd_install_relocation (first such note in the documentation | |
3902 | appears with binutils-2.8). | |
3903 | ||
3904 | That function bfd_install_relocation does the wrong thing with | |
3905 | putting stuff into the addend of a reloc (it should stay out) for a | |
3906 | weak symbol. The really bad thing is that it adds the | |
3907 | "segment-relative offset" of the symbol into the reloc. In this | |
3908 | case, the reloc should instead be relative to the symbol with no | |
3909 | other offset than the assembly code shows; and since the symbol is | |
3910 | weak, any local definition should be ignored until link time (or | |
3911 | thereafter). | |
3912 | To wit: weaksym+42 should be weaksym+42 in the reloc, | |
3913 | not weaksym+(offset_from_segment_of_local_weaksym_definition) | |
3914 | ||
3915 | To "work around" this, we subtract the segment-relative offset of | |
3916 | "known" weak symbols. This evens out the extra offset. | |
3917 | ||
3918 | That happens for a.out but not for ELF, since for ELF, | |
3919 | bfd_install_relocation uses the "special function" field of the | |
3920 | howto, and does not execute the code that needs to be undone. */ | |
3921 | ||
3922 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour | |
3923 | && fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy) | |
3924 | && ! bfd_is_und_section (S_GET_SEGMENT (fixP->fx_addsy))) | |
47926f60 KH |
3925 | { |
3926 | relP->addend -= S_GET_VALUE (fixP->fx_addsy); | |
3927 | } | |
3bcbcc3d HPN |
3928 | |
3929 | relP->howto = bfd_reloc_type_lookup (stdoutput, code); | |
3930 | if (! relP->howto) | |
3931 | { | |
3932 | const char *name; | |
3933 | ||
3934 | name = S_GET_NAME (fixP->fx_addsy); | |
3935 | if (name == NULL) | |
3936 | name = _("<unknown>"); | |
3937 | as_fatal (_("Cannot generate relocation type for symbol %s, code %s"), | |
3938 | name, bfd_get_reloc_code_name (code)); | |
3939 | } | |
3940 | ||
3941 | return relP; | |
3942 | } | |
3943 | ||
3bcbcc3d | 3944 | /* Machine-dependent usage-output. */ |
47926f60 | 3945 | |
3bcbcc3d HPN |
3946 | void |
3947 | md_show_usage (stream) | |
3948 | FILE *stream; | |
3949 | { | |
08caf3f8 | 3950 | /* The messages are formatted to line up with the generic options. */ |
7b15d668 HPN |
3951 | fprintf (stream, _("CRIS-specific options:\n")); |
3952 | fprintf (stream, "%s", | |
3953 | _(" -h, -H Don't execute, print this help text. Deprecated.\n")); | |
3954 | fprintf (stream, "%s", | |
3955 | _(" -N Warn when branches are expanded to jumps.\n")); | |
3956 | fprintf (stream, "%s", | |
3957 | _(" --underscore User symbols are normally prepended with underscore.\n")); | |
3958 | fprintf (stream, "%s", | |
3959 | _(" Registers will not need any prefix.\n")); | |
3960 | fprintf (stream, "%s", | |
3961 | _(" --no-underscore User symbols do not have any prefix.\n")); | |
3962 | fprintf (stream, "%s", | |
3963 | _(" Registers will require a `$'-prefix.\n")); | |
08caf3f8 HPN |
3964 | fprintf (stream, "%s", |
3965 | _(" --pic Enable generation of position-independent code.\n")); | |
ae57792d HPN |
3966 | fprintf (stream, "%s", |
3967 | _(" --march=<arch> Generate code for <arch>. Valid choices for <arch>\n\ | |
3968 | are v0_v10, v10, v32 and common_v10_v32.\n")); | |
3bcbcc3d HPN |
3969 | } |
3970 | ||
3bcbcc3d | 3971 | /* Apply a fixS (fixup of an instruction or data that we didn't have |
47926f60 | 3972 | enough info to complete immediately) to the data in a frag. */ |
3bcbcc3d | 3973 | |
94f592af | 3974 | void |
08caf3f8 | 3975 | md_apply_fix3 (fixP, valP, seg) |
3bcbcc3d HPN |
3976 | fixS *fixP; |
3977 | valueT *valP; | |
08caf3f8 | 3978 | segT seg; |
3bcbcc3d | 3979 | { |
451a1fc5 HPN |
3980 | /* This assignment truncates upper bits if valueT is 64 bits (as with |
3981 | --enable-64-bit-bfd), which is fine here, though we cast to avoid | |
920e4177 | 3982 | any compiler warnings. */ |
451a1fc5 | 3983 | long val = (long) *valP; |
3bcbcc3d HPN |
3984 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; |
3985 | ||
3986 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
3987 | fixP->fx_done = 1; | |
3988 | ||
3989 | if (fixP->fx_bit_fixP || fixP->fx_im_disp != 0) | |
3990 | { | |
3991 | as_bad_where (fixP->fx_file, fixP->fx_line, _("Invalid relocation")); | |
3992 | fixP->fx_done = 1; | |
3993 | } | |
3994 | else | |
47926f60 | 3995 | { |
a161fe53 | 3996 | /* We can't actually support subtracting a symbol. */ |
47926f60 | 3997 | if (fixP->fx_subsy != (symbolS *) NULL) |
a161fe53 AM |
3998 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3999 | _("expression too complex")); | |
47926f60 | 4000 | |
ae57792d HPN |
4001 | /* This operand-type is scaled. */ |
4002 | if (fixP->fx_r_type == BFD_RELOC_CRIS_LAPCQ_OFFSET) | |
4003 | val /= 2; | |
08caf3f8 | 4004 | cris_number_to_imm (buf, val, fixP->fx_size, fixP, seg); |
47926f60 | 4005 | } |
3bcbcc3d HPN |
4006 | } |
4007 | ||
3bcbcc3d HPN |
4008 | /* All relocations are relative to the location just after the fixup; |
4009 | the address of the fixup plus its size. */ | |
4010 | ||
4011 | long | |
4012 | md_pcrel_from (fixP) | |
4013 | fixS *fixP; | |
4014 | { | |
4015 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
4016 | ||
4017 | /* FIXME: We get here only at the end of assembly, when X in ".-X" is | |
08caf3f8 HPN |
4018 | still unknown. Since we don't have pc-relative relocations in a.out, |
4019 | this is invalid. What to do if anything for a.out, is to add | |
3bcbcc3d | 4020 | pc-relative relocations everywhere including the elinux program |
08caf3f8 HPN |
4021 | loader. For ELF, allow straight-forward PC-relative relocations, |
4022 | which are always relative to the location after the relocation. */ | |
4023 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
4024 | || (fixP->fx_r_type != BFD_RELOC_8_PCREL | |
4025 | && fixP->fx_r_type != BFD_RELOC_16_PCREL | |
ae57792d HPN |
4026 | && fixP->fx_r_type != BFD_RELOC_32_PCREL |
4027 | && fixP->fx_r_type != BFD_RELOC_CRIS_LAPCQ_OFFSET)) | |
08caf3f8 HPN |
4028 | as_bad_where (fixP->fx_file, fixP->fx_line, |
4029 | _("Invalid pc-relative relocation")); | |
3bcbcc3d HPN |
4030 | return fixP->fx_size + addr; |
4031 | } | |
4032 | ||
47926f60 | 4033 | /* We have no need to give defaults for symbol-values. */ |
3bcbcc3d HPN |
4034 | symbolS * |
4035 | md_undefined_symbol (name) | |
4036 | char *name ATTRIBUTE_UNUSED; | |
4037 | { | |
4038 | return 0; | |
4039 | } | |
4040 | ||
a161fe53 AM |
4041 | /* If this function returns non-zero, it prevents the relocation |
4042 | against symbol(s) in the FIXP from being replaced with relocations | |
4043 | against section symbols, and guarantees that a relocation will be | |
4044 | emitted even when the value can be resolved locally. */ | |
3bcbcc3d HPN |
4045 | int |
4046 | md_cris_force_relocation (fixp) | |
4047 | struct fix *fixp; | |
4048 | { | |
08caf3f8 HPN |
4049 | switch (fixp->fx_r_type) |
4050 | { | |
08caf3f8 HPN |
4051 | case BFD_RELOC_CRIS_16_GOT: |
4052 | case BFD_RELOC_CRIS_32_GOT: | |
4053 | case BFD_RELOC_CRIS_16_GOTPLT: | |
4054 | case BFD_RELOC_CRIS_32_GOTPLT: | |
4055 | case BFD_RELOC_CRIS_32_GOTREL: | |
4056 | case BFD_RELOC_CRIS_32_PLT_GOTREL: | |
4057 | case BFD_RELOC_CRIS_32_PLT_PCREL: | |
4058 | return 1; | |
4059 | default: | |
4060 | ; | |
4061 | } | |
4062 | ||
ae6063d4 | 4063 | return generic_force_reloc (fixp); |
3bcbcc3d HPN |
4064 | } |
4065 | ||
4066 | /* Check and emit error if broken-word handling has failed to fix up a | |
4067 | case-table. This is called from write.c, after doing everything it | |
4068 | knows about how to handle broken words. */ | |
4069 | ||
4070 | void | |
4071 | tc_cris_check_adjusted_broken_word (new_offset, brokwP) | |
4072 | offsetT new_offset; | |
4073 | struct broken_word *brokwP; | |
4074 | { | |
4075 | if (new_offset > 32767 || new_offset < -32768) | |
47926f60 | 4076 | /* We really want a genuine error, not a warning, so make it one. */ |
3bcbcc3d HPN |
4077 | as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line, |
4078 | _("Adjusted signed .word (%ld) overflows: `switch'-statement too large."), | |
4079 | (long) new_offset); | |
4080 | } | |
4081 | ||
7b15d668 HPN |
4082 | /* Make a leading REGISTER_PREFIX_CHAR mandatory for all registers. */ |
4083 | ||
4084 | static void cris_force_reg_prefix () | |
4085 | { | |
b34976b6 | 4086 | demand_register_prefix = TRUE; |
7b15d668 HPN |
4087 | } |
4088 | ||
4089 | /* Do not demand a leading REGISTER_PREFIX_CHAR for all registers. */ | |
4090 | ||
4091 | static void cris_relax_reg_prefix () | |
4092 | { | |
b34976b6 | 4093 | demand_register_prefix = FALSE; |
7b15d668 HPN |
4094 | } |
4095 | ||
4096 | /* Adjust for having a leading '_' on all user symbols. */ | |
4097 | ||
4098 | static void cris_sym_leading_underscore () | |
4099 | { | |
4100 | /* We can't really do anything more than assert that what the program | |
4101 | thinks symbol starts with agrees with the command-line options, since | |
4102 | the bfd is already created. */ | |
4103 | ||
b34976b6 | 4104 | if (!symbols_have_leading_underscore) |
ed67db7a | 4105 | as_bad (_(".syntax %s requires command-line option `--underscore'"), |
7b15d668 HPN |
4106 | SYNTAX_USER_SYM_LEADING_UNDERSCORE); |
4107 | } | |
4108 | ||
4109 | /* Adjust for not having any particular prefix on user symbols. */ | |
4110 | ||
4111 | static void cris_sym_no_leading_underscore () | |
4112 | { | |
b34976b6 | 4113 | if (symbols_have_leading_underscore) |
ed67db7a | 4114 | as_bad (_(".syntax %s requires command-line option `--no-underscore'"), |
7b15d668 HPN |
4115 | SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE); |
4116 | } | |
4117 | ||
4118 | /* Handle the .syntax pseudo, which takes an argument that decides what | |
4119 | syntax the assembly code has. */ | |
4120 | ||
4121 | static void | |
4122 | s_syntax (ignore) | |
4123 | int ignore ATTRIBUTE_UNUSED; | |
4124 | { | |
4125 | static const struct syntaxes | |
4126 | { | |
ae57792d | 4127 | const char *const operand; |
7b15d668 | 4128 | void (*fn) PARAMS ((void)); |
4a1805b1 | 4129 | } syntax_table[] = |
7b15d668 HPN |
4130 | {{SYNTAX_ENFORCE_REG_PREFIX, cris_force_reg_prefix}, |
4131 | {SYNTAX_RELAX_REG_PREFIX, cris_relax_reg_prefix}, | |
4132 | {SYNTAX_USER_SYM_LEADING_UNDERSCORE, cris_sym_leading_underscore}, | |
4133 | {SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE, cris_sym_no_leading_underscore}}; | |
4134 | ||
4135 | const struct syntaxes *sp; | |
4136 | ||
4137 | for (sp = syntax_table; | |
4138 | sp < syntax_table + sizeof (syntax_table) / sizeof (syntax_table[0]); | |
4139 | sp++) | |
4140 | { | |
4141 | if (strncmp (input_line_pointer, sp->operand, | |
4142 | strlen (sp->operand)) == 0) | |
4143 | { | |
bc805888 | 4144 | (sp->fn) (); |
7b15d668 HPN |
4145 | |
4146 | input_line_pointer += strlen (sp->operand); | |
4147 | demand_empty_rest_of_line (); | |
4148 | return; | |
4149 | } | |
4150 | } | |
4151 | ||
4152 | as_bad (_("Unknown .syntax operand")); | |
4153 | } | |
4154 | ||
fcdc20a4 HPN |
4155 | /* Wrapper for dwarf2_directive_file to emit error if this is seen when |
4156 | not emitting ELF. */ | |
4157 | ||
4158 | static void | |
4159 | s_cris_file (dummy) | |
4160 | int dummy; | |
4161 | { | |
4162 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
ed67db7a | 4163 | as_bad (_("Pseudodirective .file is only valid when generating ELF")); |
fcdc20a4 HPN |
4164 | else |
4165 | dwarf2_directive_file (dummy); | |
4166 | } | |
4167 | ||
4168 | /* Wrapper for dwarf2_directive_loc to emit error if this is seen when not | |
4169 | emitting ELF. */ | |
4170 | ||
4171 | static void | |
4172 | s_cris_loc (dummy) | |
4173 | int dummy; | |
4174 | { | |
4175 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
ed67db7a | 4176 | as_bad (_("Pseudodirective .loc is only valid when generating ELF")); |
fcdc20a4 HPN |
4177 | else |
4178 | dwarf2_directive_loc (dummy); | |
4179 | } | |
4180 | ||
ae57792d HPN |
4181 | /* Translate a <arch> string (as common to --march=<arch> and .arch <arch>) |
4182 | into an enum. If the string *STR is recognized, *STR is updated to point | |
4183 | to the end of the string. If the string is not recognized, | |
4184 | arch_cris_unknown is returned. */ | |
4185 | ||
4186 | static enum cris_archs | |
4187 | cris_arch_from_string (str) | |
4188 | char **str; | |
4189 | { | |
4190 | static const struct cris_arch_struct | |
4191 | { | |
4192 | const char *const name; | |
4193 | enum cris_archs arch; | |
4194 | } arch_table[] = | |
4195 | /* Keep in order longest-first for choices where one is a prefix | |
4196 | of another. */ | |
4197 | {{"v0_v10", arch_cris_any_v0_v10}, | |
4198 | {"v10", arch_crisv10}, | |
4199 | {"v32", arch_crisv32}, | |
4200 | {"common_v10_v32", arch_cris_common_v10_v32}}; | |
4201 | ||
4202 | const struct cris_arch_struct *ap; | |
4203 | ||
4204 | for (ap = arch_table; | |
4205 | ap < arch_table + sizeof (arch_table) / sizeof (arch_table[0]); | |
4206 | ap++) | |
4207 | { | |
4208 | int len = strlen (ap->name); | |
4209 | ||
4210 | if (strncmp (*str, ap->name, len) == 0 | |
4211 | && (str[0][len] == 0 || ISSPACE (str[0][len]))) | |
4212 | { | |
4213 | *str += strlen (ap->name); | |
4214 | return ap->arch; | |
4215 | } | |
4216 | } | |
4217 | ||
4218 | return arch_cris_unknown; | |
4219 | } | |
4220 | ||
4221 | /* Return nonzero if architecture version ARCH matches version range in | |
4222 | IVER. */ | |
4223 | ||
4224 | static int | |
4225 | cris_insn_ver_valid_for_arch (iver, arch) | |
4226 | enum cris_insn_version_usage iver; | |
4227 | enum cris_archs arch; | |
4228 | { | |
4229 | switch (arch) | |
4230 | { | |
4231 | case arch_cris_any_v0_v10: | |
4232 | return | |
4233 | (iver == cris_ver_version_all | |
4234 | || iver == cris_ver_warning | |
4235 | || iver == cris_ver_v0_3 | |
4236 | || iver == cris_ver_v3p | |
4237 | || iver == cris_ver_v0_10 | |
4238 | || iver == cris_ver_sim_v0_10 | |
4239 | || iver == cris_ver_v3_10 | |
4240 | || iver == cris_ver_v8 | |
4241 | || iver == cris_ver_v8p | |
4242 | || iver == cris_ver_v8_10 | |
4243 | || iver == cris_ver_v10 | |
4244 | || iver == cris_ver_v10p); | |
4245 | ||
4246 | case arch_crisv32: | |
4247 | return | |
4248 | (iver == cris_ver_version_all | |
4249 | || iver == cris_ver_v3p | |
4250 | || iver == cris_ver_v8p | |
4251 | || iver == cris_ver_v10p | |
4252 | || iver == cris_ver_v32p); | |
4253 | ||
4254 | case arch_cris_common_v10_v32: | |
4255 | return | |
4256 | (iver == cris_ver_version_all | |
4257 | || iver == cris_ver_v3p | |
4258 | || iver == cris_ver_v8p | |
4259 | || iver == cris_ver_v10p); | |
4260 | ||
4261 | case arch_crisv0: | |
4262 | return | |
4263 | (iver == cris_ver_version_all | |
4264 | || iver == cris_ver_v0_3 | |
4265 | || iver == cris_ver_v0_10 | |
4266 | || iver == cris_ver_sim_v0_10); | |
4267 | ||
4268 | case arch_crisv3: | |
4269 | return | |
4270 | (iver == cris_ver_version_all | |
4271 | || iver == cris_ver_v0_3 | |
4272 | || iver == cris_ver_v3p | |
4273 | || iver == cris_ver_v0_10 | |
4274 | || iver == cris_ver_sim_v0_10 | |
4275 | || iver == cris_ver_v3_10); | |
4276 | ||
4277 | case arch_crisv8: | |
4278 | return | |
4279 | (iver == cris_ver_version_all | |
4280 | || iver == cris_ver_v3p | |
4281 | || iver == cris_ver_v0_10 | |
4282 | || iver == cris_ver_sim_v0_10 | |
4283 | || iver == cris_ver_v3_10 | |
4284 | || iver == cris_ver_v8 | |
4285 | || iver == cris_ver_v8p | |
4286 | || iver == cris_ver_v8_10); | |
4287 | ||
4288 | case arch_crisv10: | |
4289 | return | |
4290 | (iver == cris_ver_version_all | |
4291 | || iver == cris_ver_v3p | |
4292 | || iver == cris_ver_v0_10 | |
4293 | || iver == cris_ver_sim_v0_10 | |
4294 | || iver == cris_ver_v3_10 | |
4295 | || iver == cris_ver_v8p | |
4296 | || iver == cris_ver_v8_10 | |
4297 | || iver == cris_ver_v10 | |
4298 | || iver == cris_ver_v10p); | |
4299 | ||
4300 | default: | |
4301 | BAD_CASE (arch); | |
4302 | } | |
4303 | } | |
4304 | ||
4305 | /* Assert that the .arch ARCHCHOICE1 is compatible with the specified or | |
4306 | default --march=<ARCHCHOICE2> option. */ | |
4307 | ||
4308 | static void | |
4309 | s_cris_arch (dummy) | |
4310 | int dummy ATTRIBUTE_UNUSED; | |
4311 | { | |
4312 | /* Right now we take the easy route and check for sameness. It's not | |
4313 | obvious that allowing e.g. --march=v32 and .arch common_v0_v32 | |
4314 | would be more useful than confusing, implementation-wise and | |
4315 | user-wise. */ | |
4316 | ||
4317 | char *str = input_line_pointer; | |
4318 | enum cris_archs arch = cris_arch_from_string (&str); | |
4319 | ||
4320 | if (arch == arch_cris_unknown) | |
4321 | { | |
4322 | as_bad (_("unknown operand to .arch")); | |
4323 | ||
4324 | /* For this one, str does not reflect the end of the operand, | |
4325 | since there was no matching arch. Skip it manually; skip | |
4326 | things that can be part of a word (a name). */ | |
4327 | while (is_part_of_name (*str)) | |
4328 | str++; | |
4329 | } | |
4330 | else if (arch != cris_arch) | |
4331 | as_bad (_(".arch <arch> requires a matching --march=... option")); | |
4332 | ||
4333 | input_line_pointer = str; | |
4334 | demand_empty_rest_of_line (); | |
4335 | return; | |
4336 | } | |
4337 | ||
3bcbcc3d HPN |
4338 | /* |
4339 | * Local variables: | |
4340 | * eval: (c-set-style "gnu") | |
4341 | * indent-tabs-mode: t | |
4342 | * End: | |
4343 | */ |