Rearrange symbol_create parameters
[deliverable/binutils-gdb.git] / gas / config / tc-cris.c
CommitLineData
3bcbcc3d 1/* tc-cris.c -- Assembler code for the CRIS CPU core.
b3adc24a 2 Copyright (C) 2000-2020 Free Software Foundation, Inc.
3bcbcc3d
HPN
3
4 Contributed by Axis Communications AB, Lund, Sweden.
5 Originally written for GAS 1.38.1 by Mikael Asker.
08caf3f8 6 Updates, BFDizing, GNUifying and ELF support by Hans-Peter Nilsson.
3bcbcc3d
HPN
7
8 This file is part of GAS, the GNU Assembler.
9
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
ec2655a6 12 the Free Software Foundation; either version 3, or (at your option)
3bcbcc3d
HPN
13 any later version.
14
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the
4b4da160
NC
22 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
23 MA 02110-1301, USA. */
3bcbcc3d 24
3bcbcc3d 25#include "as.h"
3882b010 26#include "safe-ctype.h"
3bcbcc3d
HPN
27#include "subsegs.h"
28#include "opcode/cris.h"
fcdc20a4 29#include "dwarf2dbg.h"
3bcbcc3d
HPN
30
31/* Conventions used here:
32 Generally speaking, pointers to binutils types such as "fragS" and
33 "expressionS" get parameter and variable names ending in "P", such as
34 "fragP", to harmonize with the rest of the binutils code. Other
35 pointers get a "p" suffix, such as "bufp". Any function or type-name
36 that could clash with a current or future binutils or GAS function get
37 a "cris_" prefix. */
38
7b15d668
HPN
39#define SYNTAX_RELAX_REG_PREFIX "no_register_prefix"
40#define SYNTAX_ENFORCE_REG_PREFIX "register_prefix"
41#define SYNTAX_USER_SYM_LEADING_UNDERSCORE "leading_underscore"
42#define SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE "no_leading_underscore"
43#define REGISTER_PREFIX_CHAR '$'
44
1c971160
HPN
45/* True for expressions where getting X_add_symbol and X_add_number is
46 enough to get the "base" and "offset"; no need to make_expr_symbol.
47 It's not enough to check if X_op_symbol is NULL; that misses unary
48 operations like O_uminus. */
49#define SIMPLE_EXPR(EXP) \
50 ((EXP)->X_op == O_constant || (EXP)->X_op == O_symbol)
51
08caf3f8
HPN
52/* Like in ":GOT", ":GOTOFF" etc. Other ports use '@', but that's in
53 line_separator_chars for CRIS, so we avoid it. */
cc99daad 54#define RELOC_SUFFIX_CHAR ':'
08caf3f8 55
3bcbcc3d
HPN
56/* This might be CRIS_INSN_NONE if we're assembling a prefix-insn only.
57 Note that some prefix-insns might be assembled as CRIS_INSN_NORMAL. */
58enum cris_insn_kind
59{
1048a9ba 60 CRIS_INSN_NORMAL, CRIS_INSN_NONE, CRIS_INSN_BRANCH, CRIS_INSN_MUL
3bcbcc3d
HPN
61};
62
63/* An instruction will have one of these prefixes.
64 Although the same bit-pattern, we handle BDAP with an immediate
65 expression (eventually quick or [pc+]) different from when we only have
66 register expressions. */
67enum prefix_kind
68{
69 PREFIX_NONE, PREFIX_BDAP_IMM, PREFIX_BDAP, PREFIX_BIAP, PREFIX_DIP,
70 PREFIX_PUSH
71};
72
73/* The prefix for an instruction. */
74struct cris_prefix
75{
47926f60
KH
76 enum prefix_kind kind;
77 int base_reg_number;
78 unsigned int opcode;
3bcbcc3d
HPN
79
80 /* There might be an expression to be evaluated, like I in [rN+I]. */
47926f60 81 expressionS expr;
3bcbcc3d
HPN
82
83 /* If there's an expression, we might need a relocation. Here's the
33eaf5de 84 type of what relocation to start relaxation with.
3bcbcc3d
HPN
85 The relocation is assumed to start immediately after the prefix insn,
86 so we don't provide an offset. */
87 enum bfd_reloc_code_real reloc;
88};
89
47926f60 90/* The description of the instruction being assembled. */
3bcbcc3d
HPN
91struct cris_instruction
92{
93 /* If CRIS_INSN_NONE, then this insn is of zero length. */
47926f60 94 enum cris_insn_kind insn_type;
3bcbcc3d
HPN
95
96 /* If a special register was mentioned, this is its description, else
47926f60 97 it is NULL. */
3bcbcc3d
HPN
98 const struct cris_spec_reg *spec_reg;
99
47926f60 100 unsigned int opcode;
3bcbcc3d
HPN
101
102 /* An insn may have at most one expression; theoretically there could be
47926f60
KH
103 another in its prefix (but I don't see how that could happen). */
104 expressionS expr;
3bcbcc3d
HPN
105
106 /* The expression might need a relocation. Here's one to start
107 relaxation with. */
47926f60 108 enum bfd_reloc_code_real reloc;
3bcbcc3d 109
08caf3f8 110 /* The size in bytes of an immediate expression, or zero if
3bcbcc3d 111 nonapplicable. */
47926f60 112 int imm_oprnd_size;
3bcbcc3d
HPN
113};
114
ae57792d
HPN
115enum cris_archs
116{
117 arch_cris_unknown,
118 arch_crisv0, arch_crisv3, arch_crisv8, arch_crisv10,
119 arch_cris_any_v0_v10, arch_crisv32, arch_cris_common_v10_v32
120};
121
17b9d67d 122static enum cris_archs cris_arch_from_string (const char **);
695a4822
HPN
123static int cris_insn_ver_valid_for_arch (enum cris_insn_version_usage,
124 enum cris_archs);
125
126static void cris_process_instruction (char *, struct cris_instruction *,
127 struct cris_prefix *);
128static int get_bwd_size_modifier (char **, int *);
129static int get_bw_size_modifier (char **, int *);
130static int get_gen_reg (char **, int *);
131static int get_spec_reg (char **, const struct cris_spec_reg **);
132static int get_sup_reg (char **, int *);
133static int get_autoinc_prefix_or_indir_op (char **, struct cris_prefix *,
134 int *, int *, int *,
135 expressionS *);
136static int get_3op_or_dip_prefix_op (char **, struct cris_prefix *);
137static int cris_get_expression (char **, expressionS *);
138static int get_flags (char **, int *);
139static void gen_bdap (int, expressionS *);
140static int branch_disp (int);
141static void gen_cond_branch_32 (char *, char *, fragS *, symbolS *, symbolS *,
142 long int);
143static void cris_number_to_imm (char *, long, int, fixS *, segT);
695a4822
HPN
144static void s_syntax (int);
145static void s_cris_file (int);
146static void s_cris_loc (int);
147static void s_cris_arch (int);
d2b52762 148static void s_cris_dtpoff (int);
7b15d668 149
08caf3f8 150/* Get ":GOT", ":GOTOFF", ":PLT" etc. suffixes. */
cc99daad
HPN
151static void cris_get_reloc_suffix (char **, bfd_reloc_code_real_type *,
152 expressionS *);
153static unsigned int cris_get_specified_reloc_size (bfd_reloc_code_real_type);
08caf3f8 154
7b15d668 155/* All the .syntax functions. */
695a4822
HPN
156static void cris_force_reg_prefix (void);
157static void cris_relax_reg_prefix (void);
158static void cris_sym_leading_underscore (void);
159static void cris_sym_no_leading_underscore (void);
160static char *cris_insn_first_word_frag (void);
7b15d668 161
3bcbcc3d 162/* Handle to the opcode hash table. */
629310ab 163static htab_t op_hash = NULL;
3bcbcc3d 164
399f703e
HPN
165/* If we target cris-axis-linux-gnu (as opposed to generic cris-axis-elf),
166 we default to no underscore and required register-prefixes. The
167 difference is in the default values. */
168#ifdef TE_LINUX
169#define DEFAULT_CRIS_AXIS_LINUX_GNU TRUE
170#else
171#define DEFAULT_CRIS_AXIS_LINUX_GNU FALSE
172#endif
173
7b15d668 174/* Whether we demand that registers have a `$' prefix. Default here. */
399f703e 175static bfd_boolean demand_register_prefix = DEFAULT_CRIS_AXIS_LINUX_GNU;
7b15d668
HPN
176
177/* Whether global user symbols have a leading underscore. Default here. */
399f703e
HPN
178static bfd_boolean symbols_have_leading_underscore
179 = !DEFAULT_CRIS_AXIS_LINUX_GNU;
7b15d668 180
08caf3f8 181/* Whether or not we allow PIC, and expand to PIC-friendly constructs. */
b34976b6 182static bfd_boolean pic = FALSE;
08caf3f8 183
cc99daad
HPN
184/* Whether or not we allow TLS suffixes. For the moment, we always do. */
185static const bfd_boolean tls = TRUE;
186
ae57792d
HPN
187/* If we're configured for "cris", default to allow all v0..v10
188 instructions and register names. */
189#ifndef DEFAULT_CRIS_ARCH
190#define DEFAULT_CRIS_ARCH cris_any_v0_v10
191#endif
192
193/* No whitespace in the CONCAT2 parameter list. */
194static enum cris_archs cris_arch = XCONCAT2 (arch_,DEFAULT_CRIS_ARCH);
195
3bcbcc3d
HPN
196const pseudo_typeS md_pseudo_table[] =
197{
198 {"dword", cons, 4},
d2b52762 199 {"dtpoffd", s_cris_dtpoff, 4},
7b15d668 200 {"syntax", s_syntax, 0},
fcdc20a4
HPN
201 {"file", s_cris_file, 0},
202 {"loc", s_cris_loc, 0},
ae57792d 203 {"arch", s_cris_arch, 0},
3bcbcc3d
HPN
204 {NULL, 0, 0}
205};
206
207static int warn_for_branch_expansion = 0;
208
1048a9ba
HPN
209/* Whether to emit error when a MULS/MULU could be located last on a
210 cache-line. */
ae57792d
HPN
211static int err_for_dangerous_mul_placement
212 = (XCONCAT2 (arch_,DEFAULT_CRIS_ARCH) != arch_crisv32);
1048a9ba 213
3bcbcc3d
HPN
214const char cris_comment_chars[] = ";";
215
216/* This array holds the chars that only start a comment at the beginning of
217 a line. If the line seems to have the form '# 123 filename'
47926f60 218 .line and .file directives will appear in the pre-processed output. */
3bcbcc3d
HPN
219/* Note that input_file.c hand-checks for '#' at the beginning of the
220 first line of the input file. This is because the compiler outputs
47926f60
KH
221 #NO_APP at the beginning of its output. */
222/* Also note that slash-star will always start a comment. */
3bcbcc3d
HPN
223const char line_comment_chars[] = "#";
224const char line_separator_chars[] = "@";
225
226/* Now all floating point support is shut off. See md_atof. */
227const char EXP_CHARS[] = "";
228const char FLT_CHARS[] = "";
229
3bcbcc3d
HPN
230/* For CRIS, we encode the relax_substateTs (in e.g. fr_substate) as:
231 2 1 0
232 ---/ /--+-----------------+-----------------+-----------------+
233 | what state ? | how long ? |
234 ---/ /--+-----------------+-----------------+-----------------+
235
236 The "how long" bits are 00 = byte, 01 = word, 10 = dword (long).
3bcbcc3d
HPN
237 Not all lengths are legit for a given value of (what state).
238
239 Groups for CRIS address relaxing:
240
ae57792d 241 1. Bcc (pre-V32)
3bcbcc3d
HPN
242 length: byte, word, 10-byte expansion
243
244 2. BDAP
1048a9ba
HPN
245 length: byte, word, dword
246
247 3. MULS/MULU
248 Not really a relaxation (no infrastructure to get delay-slots
249 right), just an alignment and placement checker for the v10
ae57792d
HPN
250 multiply/cache-bug.
251
252 4. Bcc (V32 and later)
253 length: byte, word, 14-byte expansion
254
255 5. Bcc (V10+V32)
256 length: byte, word, error
257
258 6. BA (V32)
259 length: byte, word, dword
3bcbcc3d 260
ae57792d
HPN
261 7. LAPC (V32)
262 length: byte, dword
263 */
264
265#define STATE_COND_BRANCH (1)
3bcbcc3d 266#define STATE_BASE_PLUS_DISP_PREFIX (2)
1048a9ba 267#define STATE_MUL (3)
ae57792d
HPN
268#define STATE_COND_BRANCH_V32 (4)
269#define STATE_COND_BRANCH_COMMON (5)
270#define STATE_ABS_BRANCH_V32 (6)
271#define STATE_LAPC (7)
d2aa3f9f 272#define STATE_COND_BRANCH_PIC (8)
3bcbcc3d
HPN
273
274#define STATE_LENGTH_MASK (3)
275#define STATE_BYTE (0)
276#define STATE_WORD (1)
277#define STATE_DWORD (2)
278/* Symbol undefined. */
279#define STATE_UNDF (3)
280#define STATE_MAX_LENGTH (3)
281
2d2255b5 282/* These displacements are relative to the address following the opcode
3bcbcc3d
HPN
283 word of the instruction. The first letter is Byte, Word. The 2nd
284 letter is Forward, Backward. */
285
286#define BRANCH_BF ( 254)
287#define BRANCH_BB (-256)
ae57792d
HPN
288#define BRANCH_BF_V32 ( 252)
289#define BRANCH_BB_V32 (-258)
47926f60
KH
290#define BRANCH_WF (2 + 32767)
291#define BRANCH_WB (2 + -32768)
ae57792d
HPN
292#define BRANCH_WF_V32 (-2 + 32767)
293#define BRANCH_WB_V32 (-2 + -32768)
3bcbcc3d
HPN
294
295#define BDAP_BF ( 127)
296#define BDAP_BB (-128)
297#define BDAP_WF ( 32767)
298#define BDAP_WB (-32768)
299
300#define ENCODE_RELAX(what, length) (((what) << 2) + (length))
301
302const relax_typeS md_cris_relax_table[] =
303{
304 /* Error sentinel (0, 0). */
305 {1, 1, 0, 0},
306
307 /* Unused (0, 1). */
308 {1, 1, 0, 0},
309
310 /* Unused (0, 2). */
311 {1, 1, 0, 0},
312
313 /* Unused (0, 3). */
314 {1, 1, 0, 0},
315
316 /* Bcc o (1, 0). */
317 {BRANCH_BF, BRANCH_BB, 0, ENCODE_RELAX (1, 1)},
318
47926f60 319 /* Bcc [PC+] (1, 1). */
3bcbcc3d
HPN
320 {BRANCH_WF, BRANCH_WB, 2, ENCODE_RELAX (1, 2)},
321
322 /* BEXT/BWF, BA, JUMP (external), JUMP (always), Bnot_cc, JUMP (default)
323 (1, 2). */
324 {0, 0, 10, 0},
325
326 /* Unused (1, 3). */
327 {1, 1, 0, 0},
328
329 /* BDAP o (2, 0). */
330 {BDAP_BF, BDAP_BB, 0, ENCODE_RELAX (2, 1)},
331
332 /* BDAP.[bw] [PC+] (2, 1). */
333 {BDAP_WF, BDAP_WB, 2, ENCODE_RELAX (2, 2)},
334
335 /* BDAP.d [PC+] (2, 2). */
1048a9ba
HPN
336 {0, 0, 4, 0},
337
338 /* Unused (2, 3). */
ae57792d 339 {1, 1, 0, 0},
1048a9ba
HPN
340
341 /* MULS/MULU (3, 0). Positions (3, 1..3) are unused. */
ae57792d
HPN
342 {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0},
343
344 /* V32: Bcc o (4, 0). */
345 {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (4, 1)},
346
347 /* V32: Bcc [PC+] (4, 1). */
348 {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (4, 2)},
349
350 /* V32: BA .+12; NOP; BA32 target; NOP; Bcc .-6 (4, 2). */
351 {0, 0, 12, 0},
352
353 /* Unused (4, 3). */
354 {1, 1, 0, 0},
355
356 /* COMMON: Bcc o (5, 0). The offsets are calculated as for v32. Code
357 should contain two nop insns (or four if offset size is large or
358 unknown) after every label. */
359 {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (5, 1)},
360
361 /* COMMON: Bcc [PC+] (5, 1). */
362 {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (5, 2)},
363
364 /* COMMON: FIXME: ???. Treat as error currently. */
365 {0, 0, 12, 0},
366
367 /* Unused (5, 3). */
368 {1, 1, 0, 0},
369
370 /* V32: BA o (6, 0). */
371 {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (6, 1)},
372
373 /* V32: BA.W (6, 1). */
374 {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (6, 2)},
375
376 /* V32: BA.D (6, 2). */
377 {0, 0, 4, 0},
378
379 /* Unused (6, 3). */
380 {1, 1, 0, 0},
381
382 /* LAPC: LAPCQ .+0..15*2,Rn (7, 0). */
383 {14*2, -1*2, 0, ENCODE_RELAX (7, 2)},
384
385 /* Unused (7, 1).
386 While there's a shorter sequence, e.g. LAPCQ + an ADDQ or SUBQ,
387 that would affect flags, so we can't do that as it wouldn't be a
388 proper insn expansion of LAPCQ. This row is associated with a
389 2-byte expansion, so it's unused rather than the next. */
390 {1, 1, 0, 0},
391
392 /* LAPC: LAPC.D (7, 2). */
393 {0, 0, 4, 0},
394
395 /* Unused (7, 3). */
d2aa3f9f
HPN
396 {1, 1, 0, 0},
397
398 /* PIC for pre-v32: Bcc o (8, 0). */
399 {BRANCH_BF, BRANCH_BB, 0, ENCODE_RELAX (STATE_COND_BRANCH_PIC, 1)},
400
401 /* Bcc [PC+] (8, 1). */
402 {BRANCH_WF, BRANCH_WB, 2, ENCODE_RELAX (STATE_COND_BRANCH_PIC, 2)},
403
404 /* 32-bit expansion, PIC (8, 2). */
405 {0, 0, 12, 0},
406
407 /* Unused (8, 3). */
ae57792d 408 {1, 1, 0, 0}
3bcbcc3d
HPN
409};
410
3bcbcc3d
HPN
411#undef BDAP_BF
412#undef BDAP_BB
413#undef BDAP_WF
414#undef BDAP_WB
415
ae57792d 416/* Target-specific multicharacter options, not const-declared. */
3bcbcc3d
HPN
417struct option md_longopts[] =
418{
7b15d668
HPN
419#define OPTION_NO_US (OPTION_MD_BASE + 0)
420 {"no-underscore", no_argument, NULL, OPTION_NO_US},
421#define OPTION_US (OPTION_MD_BASE + 1)
422 {"underscore", no_argument, NULL, OPTION_US},
ae57792d 423#define OPTION_PIC (OPTION_US + 1)
08caf3f8 424 {"pic", no_argument, NULL, OPTION_PIC},
ae57792d 425#define OPTION_MULBUG_ABORT_ON (OPTION_PIC + 1)
1048a9ba 426 {"mul-bug-abort", no_argument, NULL, OPTION_MULBUG_ABORT_ON},
ae57792d 427#define OPTION_MULBUG_ABORT_OFF (OPTION_MULBUG_ABORT_ON + 1)
1048a9ba 428 {"no-mul-bug-abort", no_argument, NULL, OPTION_MULBUG_ABORT_OFF},
ae57792d
HPN
429#define OPTION_ARCH (OPTION_MULBUG_ABORT_OFF + 1)
430 {"march", required_argument, NULL, OPTION_ARCH},
3bcbcc3d
HPN
431 {NULL, no_argument, NULL, 0}
432};
433
ae57792d 434/* Not const-declared. */
3bcbcc3d
HPN
435size_t md_longopts_size = sizeof (md_longopts);
436const char *md_shortopts = "hHN";
437
3bcbcc3d
HPN
438/* At first glance, this may seems wrong and should be 4 (ba + nop); but
439 since a short_jump must skip a *number* of long jumps, it must also be
440 a long jump. Here, we hope to make it a "ba [16bit_offs]" and a "nop"
441 for the delay slot and hope that the jump table at most needs
442 32767/4=8191 long-jumps. A branch is better than a jump, since it is
443 relative; we will not have a reloc to fix up somewhere.
444
445 Note that we can't add relocs, because relaxation uses these fixed
446 numbers, and md_create_short_jump is called after relaxation. */
447
2b4f075a 448int md_short_jump_size = 6;
ae57792d 449
d2aa3f9f
HPN
450/* The v32 version has a delay-slot, hence two bytes longer.
451 The pre-v32 PIC version uses a prefixed insn. */
ae57792d 452#define cris_any_v0_v10_long_jump_size 6
d2aa3f9f 453#define cris_any_v0_v10_long_jump_size_pic 8
ae57792d
HPN
454#define crisv32_long_jump_size 8
455
456int md_long_jump_size = XCONCAT2 (DEFAULT_CRIS_ARCH,_long_jump_size);
3bcbcc3d 457
7b15d668 458/* Report output format. Small changes in output format (like elf
08caf3f8
HPN
459 variants below) can happen until all options are parsed, but after
460 that, the output format must remain fixed. */
47926f60 461
3bcbcc3d 462const char *
695a4822 463cris_target_format (void)
3bcbcc3d
HPN
464{
465 switch (OUTPUT_FLAVOR)
466 {
467 case bfd_target_aout_flavour:
468 return "a.out-cris";
469
470 case bfd_target_elf_flavour:
7b15d668
HPN
471 if (symbols_have_leading_underscore)
472 return "elf32-us-cris";
3bcbcc3d
HPN
473 return "elf32-cris";
474
475 default:
476 abort ();
477 return NULL;
478 }
479}
480
ae57792d
HPN
481/* Return a bfd_mach_cris... value corresponding to the value of
482 cris_arch. */
483
484unsigned int
695a4822 485cris_mach (void)
ae57792d
HPN
486{
487 unsigned int retval = 0;
488
489 switch (cris_arch)
490 {
491 case arch_cris_common_v10_v32:
492 retval = bfd_mach_cris_v10_v32;
493 break;
494
495 case arch_crisv32:
496 retval = bfd_mach_cris_v32;
497 break;
498
499 case arch_crisv10:
500 case arch_cris_any_v0_v10:
501 retval = bfd_mach_cris_v0_v10;
502 break;
503
504 default:
505 BAD_CASE (cris_arch);
506 }
507
508 return retval;
509}
510
1c971160
HPN
511/* We need a port-specific relaxation function to cope with sym2 - sym1
512 relative expressions with both symbols in the same segment (but not
513 necessarily in the same frag as this insn), for example:
514 move.d [pc+sym2-(sym1-2)],r10
515 sym1:
516 The offset can be 8, 16 or 32 bits long. */
517
518long
695a4822
HPN
519cris_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS *fragP,
520 long stretch ATTRIBUTE_UNUSED)
1c971160
HPN
521{
522 long growth;
523 offsetT aim = 0;
524 symbolS *symbolP;
525 const relax_typeS *this_type;
526 const relax_typeS *start_type;
527 relax_substateT next_state;
528 relax_substateT this_state;
529 const relax_typeS *table = TC_GENERIC_RELAX_TABLE;
530
531 /* We only have to cope with frags as prepared by
fb2fd3e1 532 md_estimate_size_before_relax. The dword cases may get here
1c971160
HPN
533 because of the different reasons that they aren't relaxable. */
534 switch (fragP->fr_subtype)
535 {
f6ce267c 536 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD):
ae57792d
HPN
537 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD):
538 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD):
539 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD):
540 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD):
541 case ENCODE_RELAX (STATE_LAPC, STATE_DWORD):
1c971160
HPN
542 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD):
543 /* When we get to these states, the frag won't grow any more. */
544 return 0;
545
546 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD):
547 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE):
548 if (fragP->fr_symbol == NULL
549 || S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
550 as_fatal (_("internal inconsistency problem in %s: fr_symbol %lx"),
551 __FUNCTION__, (long) fragP->fr_symbol);
552 symbolP = fragP->fr_symbol;
553 if (symbol_resolved_p (symbolP))
554 as_fatal (_("internal inconsistency problem in %s: resolved symbol"),
555 __FUNCTION__);
556 aim = S_GET_VALUE (symbolP);
557 break;
558
1048a9ba
HPN
559 case ENCODE_RELAX (STATE_MUL, STATE_BYTE):
560 /* Nothing to do here. */
561 return 0;
562
1c971160
HPN
563 default:
564 as_fatal (_("internal inconsistency problem in %s: fr_subtype %d"),
565 __FUNCTION__, fragP->fr_subtype);
566 }
567
568 /* The rest is stolen from relax_frag. There's no obvious way to
569 share the code, but fortunately no requirement to keep in sync as
570 long as fragP->fr_symbol does not have its segment changed. */
571
572 this_state = fragP->fr_subtype;
573 start_type = this_type = table + this_state;
574
575 if (aim < 0)
576 {
577 /* Look backwards. */
578 for (next_state = this_type->rlx_more; next_state;)
579 if (aim >= this_type->rlx_backward)
580 next_state = 0;
581 else
582 {
583 /* Grow to next state. */
584 this_state = next_state;
585 this_type = table + this_state;
586 next_state = this_type->rlx_more;
587 }
588 }
589 else
590 {
591 /* Look forwards. */
592 for (next_state = this_type->rlx_more; next_state;)
593 if (aim <= this_type->rlx_forward)
594 next_state = 0;
595 else
596 {
597 /* Grow to next state. */
598 this_state = next_state;
599 this_type = table + this_state;
600 next_state = this_type->rlx_more;
601 }
602 }
603
604 growth = this_type->rlx_length - start_type->rlx_length;
605 if (growth != 0)
606 fragP->fr_subtype = this_state;
607 return growth;
608}
609
3bcbcc3d
HPN
610/* Prepare machine-dependent frags for relaxation.
611
612 Called just before relaxation starts. Any symbol that is now undefined
613 will not become defined.
614
615 Return the correct fr_subtype in the frag.
616
617 Return the initial "guess for fr_var" to caller. The guess for fr_var
618 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
619 or fr_var contributes to our returned value.
620
621 Although it may not be explicit in the frag, pretend
47926f60 622 fr_var starts with a value. */
3bcbcc3d
HPN
623
624int
695a4822 625md_estimate_size_before_relax (fragS *fragP, segT segment_type)
3bcbcc3d 626{
47926f60 627 int old_fr_fix;
ae57792d
HPN
628 symbolS *symbolP = fragP->fr_symbol;
629
630#define HANDLE_RELAXABLE(state) \
631 case ENCODE_RELAX (state, STATE_UNDF): \
632 if (symbolP != NULL \
633 && S_GET_SEGMENT (symbolP) == segment_type \
634 && !S_IS_WEAK (symbolP)) \
635 /* The symbol lies in the same segment - a relaxable \
636 case. */ \
637 fragP->fr_subtype \
638 = ENCODE_RELAX (state, STATE_BYTE); \
639 else \
640 /* Unknown or not the same segment, so not relaxable. */ \
641 fragP->fr_subtype \
642 = ENCODE_RELAX (state, STATE_DWORD); \
643 fragP->fr_var \
644 = md_cris_relax_table[fragP->fr_subtype].rlx_length; \
645 break
3bcbcc3d
HPN
646
647 old_fr_fix = fragP->fr_fix;
648
649 switch (fragP->fr_subtype)
650 {
ae57792d
HPN
651 HANDLE_RELAXABLE (STATE_COND_BRANCH);
652 HANDLE_RELAXABLE (STATE_COND_BRANCH_V32);
653 HANDLE_RELAXABLE (STATE_COND_BRANCH_COMMON);
d2aa3f9f 654 HANDLE_RELAXABLE (STATE_COND_BRANCH_PIC);
ae57792d
HPN
655 HANDLE_RELAXABLE (STATE_ABS_BRANCH_V32);
656
657 case ENCODE_RELAX (STATE_LAPC, STATE_UNDF):
658 if (symbolP != NULL
659 && S_GET_SEGMENT (symbolP) == segment_type
660 && !S_IS_WEAK (symbolP))
661 {
662 /* The symbol lies in the same segment - a relaxable case.
663 Check if we currently have an odd offset; we can't code
664 that into the instruction. Relaxing presumably only cause
665 multiple-of-two changes, so we should only need to adjust
666 for that here. */
667 bfd_vma target_address
668 = (symbolP
669 ? S_GET_VALUE (symbolP)
670 : 0) + fragP->fr_offset;
671 bfd_vma var_part_offset = fragP->fr_fix;
672 bfd_vma address_of_var_part = fragP->fr_address + var_part_offset;
673 long offset = target_address - (address_of_var_part - 2);
674
675 fragP->fr_subtype
676 = (offset & 1)
677 ? ENCODE_RELAX (STATE_LAPC, STATE_DWORD)
678 : ENCODE_RELAX (STATE_LAPC, STATE_BYTE);
679 }
3bcbcc3d 680 else
c335d394
HPN
681 /* Unknown or not the same segment, so not relaxable. */
682 fragP->fr_subtype
ae57792d
HPN
683 = ENCODE_RELAX (STATE_LAPC, STATE_DWORD);
684 fragP->fr_var
685 = md_cris_relax_table[fragP->fr_subtype].rlx_length;
3bcbcc3d
HPN
686 break;
687
688 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF):
689 /* Note that we can not do anything sane with relaxing
690 [rX + a_known_symbol_in_text], it will have to be a 32-bit
691 value.
692
693 We could play tricks with managing a constant pool and make
08caf3f8
HPN
694 a_known_symbol_in_text a "bdap [pc + offset]" pointing there
695 (like the GOT for ELF shared libraries), but that's no use, it
696 would in general be no shorter or faster code, only more
697 complicated. */
3bcbcc3d 698
ae57792d 699 if (S_GET_SEGMENT (symbolP) != absolute_section)
3bcbcc3d
HPN
700 {
701 /* Go for dword if not absolute or same segment. */
702 fragP->fr_subtype
703 = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD);
c335d394 704 fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length;
3bcbcc3d 705 }
1c971160
HPN
706 else if (!symbol_resolved_p (fragP->fr_symbol))
707 {
708 /* The symbol will eventually be completely resolved as an
709 absolute expression, but right now it depends on the result
710 of relaxation and we don't know anything else about the
711 value. We start relaxation with the assumption that it'll
712 fit in a byte. */
713 fragP->fr_subtype
714 = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE);
715 fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length;
716 }
3bcbcc3d
HPN
717 else
718 {
719 /* Absolute expression. */
720 long int value;
ae57792d
HPN
721 value = (symbolP != NULL
722 ? S_GET_VALUE (symbolP) : 0) + fragP->fr_offset;
3bcbcc3d
HPN
723
724 if (value >= -128 && value <= 127)
725 {
726 /* Byte displacement. */
727 (fragP->fr_opcode)[0] = value;
728 }
729 else
730 {
731 /* Word or dword displacement. */
732 int pow2_of_size = 1;
733 char *writep;
734
735 if (value < -32768 || value > 32767)
736 {
737 /* Outside word range, make it a dword. */
738 pow2_of_size = 2;
739 }
740
741 /* Modify the byte-offset BDAP into a word or dword offset
742 BDAP. Or really, a BDAP rX,8bit into a
07e90ad5 743 BDAP.[wd] rX,[PC+] followed by a word or dword. */
3bcbcc3d
HPN
744 (fragP->fr_opcode)[0] = BDAP_PC_LOW + pow2_of_size * 16;
745
746 /* Keep the register number in the highest four bits. */
747 (fragP->fr_opcode)[1] &= 0xF0;
748 (fragP->fr_opcode)[1] |= BDAP_INCR_HIGH;
749
47926f60 750 /* It grew by two or four bytes. */
3bcbcc3d
HPN
751 fragP->fr_fix += 1 << pow2_of_size;
752 writep = fragP->fr_literal + old_fr_fix;
753 md_number_to_chars (writep, value, 1 << pow2_of_size);
754 }
755 frag_wane (fragP);
756 }
757 break;
758
ae57792d
HPN
759 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_BYTE):
760 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_WORD):
761 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD):
d2aa3f9f
HPN
762 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_BYTE):
763 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_WORD):
764 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD):
ae57792d
HPN
765 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_BYTE):
766 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_WORD):
767 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD):
768 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_BYTE):
769 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_WORD):
770 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD):
771 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_BYTE):
772 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_WORD):
773 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD):
774 case ENCODE_RELAX (STATE_LAPC, STATE_BYTE):
775 case ENCODE_RELAX (STATE_LAPC, STATE_DWORD):
c335d394
HPN
776 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE):
777 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD):
93c2a809
AM
778 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD):
779 /* When relaxing a section for the second time, we don't need to
c335d394
HPN
780 do anything except making sure that fr_var is set right. */
781 fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length;
93c2a809
AM
782 break;
783
1048a9ba
HPN
784 case ENCODE_RELAX (STATE_MUL, STATE_BYTE):
785 /* Nothing to do here. */
786 break;
787
3bcbcc3d
HPN
788 default:
789 BAD_CASE (fragP->fr_subtype);
790 }
791
792 return fragP->fr_var + (fragP->fr_fix - old_fr_fix);
793}
794
3bcbcc3d
HPN
795/* Perform post-processing of machine-dependent frags after relaxation.
796 Called after relaxation is finished.
797 In: Address of frag.
798 fr_type == rs_machine_dependent.
799 fr_subtype is what the address relaxed to.
800
801 Out: Any fixS:s and constants are set up.
802
803 The caller will turn the frag into a ".space 0". */
804
805void
695a4822
HPN
806md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
807 fragS *fragP)
3bcbcc3d 808{
47926f60 809 /* Pointer to first byte in variable-sized part of the frag. */
3bcbcc3d
HPN
810 char *var_partp;
811
812 /* Pointer to first opcode byte in frag. */
813 char *opcodep;
814
815 /* Used to check integrity of the relaxation.
816 One of 2 = long, 1 = word, or 0 = byte. */
66dbb2bb 817 int length_code ATTRIBUTE_UNUSED;
3bcbcc3d
HPN
818
819 /* Size in bytes of variable-sized part of frag. */
820 int var_part_size = 0;
821
822 /* This is part of *fragP. It contains all information about addresses
823 and offsets to varying parts. */
824 symbolS *symbolP;
825 unsigned long var_part_offset;
826
827 /* Where, in file space, is _var of *fragP? */
828 unsigned long address_of_var_part = 0;
829
830 /* Where, in file space, does addr point? */
831 unsigned long target_address;
832
833 know (fragP->fr_type == rs_machine_dependent);
834
835 length_code = fragP->fr_subtype & STATE_LENGTH_MASK;
836 know (length_code >= 0 && length_code < STATE_MAX_LENGTH);
837
838 var_part_offset = fragP->fr_fix;
839 var_partp = fragP->fr_literal + var_part_offset;
840 opcodep = fragP->fr_opcode;
841
842 symbolP = fragP->fr_symbol;
ac62c346 843 target_address = (symbolP ? S_GET_VALUE (symbolP) : 0) + fragP->fr_offset;
3bcbcc3d
HPN
844 address_of_var_part = fragP->fr_address + var_part_offset;
845
846 switch (fragP->fr_subtype)
47926f60 847 {
ae57792d 848 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_BYTE):
d2aa3f9f 849 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_BYTE):
ae57792d
HPN
850 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_BYTE):
851 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_BYTE):
852 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_BYTE):
47926f60
KH
853 opcodep[0] = branch_disp ((target_address - address_of_var_part));
854 var_part_size = 0;
855 break;
3bcbcc3d 856
ae57792d 857 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_WORD):
d2aa3f9f 858 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_WORD):
ae57792d
HPN
859 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_WORD):
860 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_WORD):
861 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_WORD):
47926f60
KH
862 /* We had a quick immediate branch, now turn it into a word one i.e. a
863 PC autoincrement. */
864 opcodep[0] = BRANCH_PC_LOW;
865 opcodep[1] &= 0xF0;
866 opcodep[1] |= BRANCH_INCR_HIGH;
867 md_number_to_chars (var_partp,
ae57792d
HPN
868 (long)
869 (target_address
870 - (address_of_var_part
871 + (cris_arch == arch_crisv32
872 || cris_arch == arch_cris_common_v10_v32
873 ? -2 : 2))),
47926f60
KH
874 2);
875 var_part_size = 2;
876 break;
877
ae57792d 878 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD):
47926f60
KH
879 gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP,
880 fragP->fr_symbol, (symbolS *) NULL,
881 fragP->fr_offset);
882 /* Ten bytes added: a branch, nop and a jump. */
883 var_part_size = 2 + 2 + 4 + 2;
884 break;
3bcbcc3d 885
d2aa3f9f
HPN
886 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD):
887 gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP,
888 fragP->fr_symbol, (symbolS *) NULL,
889 fragP->fr_offset);
890 /* Twelve bytes added: a branch, nop and a pic-branch-32. */
891 var_part_size = 2 + 2 + 4 + 2 + 2;
892 break;
893
ae57792d
HPN
894 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD):
895 gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP,
896 fragP->fr_symbol, (symbolS *) NULL,
897 fragP->fr_offset);
898 /* Twelve bytes added: a branch, nop and another branch and nop. */
899 var_part_size = 2 + 2 + 2 + 4 + 2;
900 break;
901
902 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD):
903 as_bad_where (fragP->fr_file, fragP->fr_line,
904 _("Relaxation to long branches for .arch common_v10_v32\
905 not implemented"));
906 /* Pretend we have twelve bytes for sake of quelling further
907 errors. */
908 var_part_size = 2 + 2 + 2 + 4 + 2;
909 break;
910
911 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD):
912 /* We had a quick immediate branch or a word immediate ba. Now
913 turn it into a dword one. */
914 opcodep[0] = BA_DWORD_OPCODE & 255;
915 opcodep[1] = (BA_DWORD_OPCODE >> 8) & 255;
916 fix_new (fragP, var_partp - fragP->fr_literal, 4, symbolP,
917 fragP->fr_offset + 6, 1, BFD_RELOC_32_PCREL);
918 var_part_size = 4;
919 break;
920
921 case ENCODE_RELAX (STATE_LAPC, STATE_BYTE):
922 {
923 long offset = target_address - (address_of_var_part - 2);
924
925 /* This is mostly a sanity check; useful occurrences (if there
926 really are any) should have been caught in
927 md_estimate_size_before_relax. We can (at least
928 theoretically) stumble over invalid code with odd sizes and
929 .p2aligns within the code, so emit an error if that happens.
930 (The generic relaxation machinery is not fit to check this.) */
931
932 if (offset & 1)
933 as_bad_where (fragP->fr_file, fragP->fr_line,
934 _("Complicated LAPC target operand is not\
935 a multiple of two. Use LAPC.D"));
936
937 /* FIXME: This *is* a sanity check. Remove when done with. */
938 if (offset > 15*2 || offset < 0)
939 as_fatal (_("Internal error found in md_convert_frag: offset %ld.\
940 Please report this."),
941 offset);
942
943 opcodep[0] |= (offset / 2) & 0xf;
944 var_part_size = 0;
945 }
946 break;
947
948 case ENCODE_RELAX (STATE_LAPC, STATE_DWORD):
949 {
950 md_number_to_chars (opcodep,
951 LAPC_DWORD_OPCODE + (opcodep[1] & 0xf0) * 256,
952 2);
953 /* Remember that the reloc is against the position *after* the
954 relocated contents, so we need to adjust to the start of
955 the insn. */
956 fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol,
957 fragP->fr_offset + 6, 1, BFD_RELOC_32_PCREL);
958 var_part_size = 4;
959 }
960 break;
961
47926f60 962 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE):
1c971160
HPN
963 if (symbolP == NULL)
964 as_fatal (_("internal inconsistency in %s: bdapq no symbol"),
965 __FUNCTION__);
966 opcodep[0] = S_GET_VALUE (symbolP);
47926f60
KH
967 var_part_size = 0;
968 break;
969
970 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD):
971 /* We had a BDAP 8-bit "quick immediate", now turn it into a 16-bit
972 one that uses PC autoincrement. */
973 opcodep[0] = BDAP_PC_LOW + (1 << 4);
974 opcodep[1] &= 0xF0;
975 opcodep[1] |= BDAP_INCR_HIGH;
1c971160
HPN
976 if (symbolP == NULL)
977 as_fatal (_("internal inconsistency in %s: bdap.w with no symbol"),
978 __FUNCTION__);
979 md_number_to_chars (var_partp, S_GET_VALUE (symbolP), 2);
47926f60
KH
980 var_part_size = 2;
981 break;
982
983 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD):
984 /* We had a BDAP 16-bit "word", change the offset to a dword. */
985 opcodep[0] = BDAP_PC_LOW + (2 << 4);
986 opcodep[1] &= 0xF0;
987 opcodep[1] |= BDAP_INCR_HIGH;
988 if (fragP->fr_symbol == NULL)
989 md_number_to_chars (var_partp, fragP->fr_offset, 4);
990 else
991 fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol,
992 fragP->fr_offset, 0, BFD_RELOC_32);
993 var_part_size = 4;
994 break;
995
1048a9ba 996 case ENCODE_RELAX (STATE_MUL, STATE_BYTE):
708587a4 997 /* This is the only time we check position and alignment of the
1048a9ba
HPN
998 placement-tracking frag. */
999 if (sec->alignment_power < 2)
1000 as_bad_where (fragP->fr_file, fragP->fr_line,
1001 _("section alignment must be >= 4 bytes to check MULS/MULU safeness"));
1002 else
1003 {
1004 /* If the address after the MULS/MULU has alignment which is
1005 that of the section and may be that of a cache-size of the
1006 buggy versions, then the MULS/MULU can be placed badly. */
1007 if ((address_of_var_part
1008 & ((1 << sec->alignment_power) - 1) & 31) == 0)
1009 as_bad_where (fragP->fr_file, fragP->fr_line,
1010 _("dangerous MULS/MULU location; give it higher alignment"));
1011 }
1012 break;
1013
47926f60
KH
1014 default:
1015 BAD_CASE (fragP->fr_subtype);
1016 break;
1017 }
1018
1019 fragP->fr_fix += var_part_size;
3bcbcc3d
HPN
1020}
1021
1022/* Generate a short jump around a secondary jump table.
a07dbd48 1023 Also called from md_create_long_jump, when sufficient. */
3bcbcc3d 1024
a07dbd48
HPN
1025void
1026md_create_short_jump (char *storep, addressT from_addr, addressT to_addr,
695a4822
HPN
1027 fragS *fragP ATTRIBUTE_UNUSED,
1028 symbolS *to_symbol ATTRIBUTE_UNUSED)
3bcbcc3d
HPN
1029{
1030 long int distance;
1031
ae57792d
HPN
1032 /* See md_create_long_jump about the comment on the "+ 2". */
1033 long int max_minimal_minus_distance;
1034 long int max_minimal_plus_distance;
a07dbd48
HPN
1035 long int max_minus_distance;
1036 long int max_plus_distance;
ae57792d
HPN
1037 int nop_opcode;
1038
1039 if (cris_arch == arch_crisv32)
1040 {
1041 max_minimal_minus_distance = BRANCH_BB_V32 + 2;
1042 max_minimal_plus_distance = BRANCH_BF_V32 + 2;
a07dbd48
HPN
1043 max_minus_distance = BRANCH_WB_V32 + 2;
1044 max_plus_distance = BRANCH_WF_V32 + 2;
ae57792d
HPN
1045 nop_opcode = NOP_OPCODE_V32;
1046 }
a07dbd48
HPN
1047 else if (cris_arch == arch_cris_common_v10_v32)
1048 /* Bail out for compatibility mode. (It seems it can be implemented,
1049 perhaps with a 10-byte sequence: "move.d NNNN,$pc/$acr", "jump
1050 $acr", "nop"; but doesn't seem worth it at the moment.) */
1051 as_fatal (_("Out-of-range .word offset handling\
1052 is not implemented for .arch common_v10_v32"));
ae57792d
HPN
1053 else
1054 {
1055 max_minimal_minus_distance = BRANCH_BB + 2;
1056 max_minimal_plus_distance = BRANCH_BF + 2;
a07dbd48
HPN
1057 max_minus_distance = BRANCH_WB + 2;
1058 max_plus_distance = BRANCH_WF + 2;
ae57792d
HPN
1059 nop_opcode = NOP_OPCODE;
1060 }
1061
3bcbcc3d
HPN
1062 distance = to_addr - from_addr;
1063
ae57792d
HPN
1064 if (max_minimal_minus_distance <= distance
1065 && distance <= max_minimal_plus_distance)
3bcbcc3d
HPN
1066 {
1067 /* Create a "short" short jump: "BA distance - 2". */
47926f60 1068 storep[0] = branch_disp (distance - 2);
3bcbcc3d
HPN
1069 storep[1] = BA_QUICK_HIGH;
1070
1071 /* A nop for the delay slot. */
ae57792d 1072 md_number_to_chars (storep + 2, nop_opcode, 2);
3bcbcc3d
HPN
1073
1074 /* The extra word should be filled with something sane too. Make it
1075 a nop to keep disassembly sane. */
ae57792d 1076 md_number_to_chars (storep + 4, nop_opcode, 2);
3bcbcc3d 1077 }
a07dbd48
HPN
1078 else if (max_minus_distance <= distance
1079 && distance <= max_plus_distance)
3bcbcc3d
HPN
1080 {
1081 /* Make it a "long" short jump: "BA (PC+)". */
1082 md_number_to_chars (storep, BA_PC_INCR_OPCODE, 2);
1083
47926f60 1084 /* ".WORD distance - 4". */
ae57792d
HPN
1085 md_number_to_chars (storep + 2,
1086 (long) (distance - 4
1087 - (cris_arch == arch_crisv32
1088 ? -4 : 0)),
1089 2);
3bcbcc3d
HPN
1090
1091 /* A nop for the delay slot. */
ae57792d 1092 md_number_to_chars (storep + 4, nop_opcode, 2);
3bcbcc3d 1093 }
a07dbd48
HPN
1094 else
1095 as_bad_where (fragP->fr_file, fragP->fr_line,
1096 _(".word case-table handling failed: table too large"));
3bcbcc3d
HPN
1097}
1098
3bcbcc3d
HPN
1099/* Generate a long jump in a secondary jump table.
1100
1101 storep Where to store the jump instruction.
1102 from_addr Address of the jump instruction.
1103 to_addr Destination address of the jump.
1104 fragP Which frag the destination address operand
1105 lies in.
1106 to_symbol Destination symbol. */
1107
1108void
695a4822
HPN
1109md_create_long_jump (char *storep, addressT from_addr, addressT to_addr,
1110 fragS *fragP, symbolS *to_symbol)
3bcbcc3d
HPN
1111{
1112 long int distance;
1113
ae57792d
HPN
1114 /* FIXME: What's that "+ 3"? It comes from the magic numbers that
1115 used to be here, it's just translated to the limit macros used in
1116 the relax table. But why + 3? */
1117 long int max_short_minus_distance
1118 = cris_arch != arch_crisv32 ? BRANCH_WB + 3 : BRANCH_WB_V32 + 3;
1119
1120 long int max_short_plus_distance
1121 = cris_arch != arch_crisv32 ? BRANCH_WF + 3 : BRANCH_WF_V32 + 3;
1122
3bcbcc3d
HPN
1123 distance = to_addr - from_addr;
1124
ae57792d
HPN
1125 if (max_short_minus_distance <= distance
1126 && distance <= max_short_plus_distance)
44ed9ef2
AM
1127 {
1128 /* Then make it a "short" long jump. */
1129 md_create_short_jump (storep, from_addr, to_addr, fragP,
ae57792d 1130 to_symbol);
44ed9ef2
AM
1131 if (cris_arch == arch_crisv32)
1132 md_number_to_chars (storep + 6, NOP_OPCODE_V32, 2);
1133 else
1134 md_number_to_chars (storep + 6, NOP_OPCODE, 2);
1135 }
3bcbcc3d
HPN
1136 else
1137 {
ae57792d 1138 /* We have a "long" long jump: "JUMP [PC+]". If CRISv32, always
d2aa3f9f 1139 make it a BA. Else make it an "MOVE [PC=PC+N],P0" if we're supposed
ae57792d 1140 to emit PIC code. */
08caf3f8 1141 md_number_to_chars (storep,
ae57792d
HPN
1142 cris_arch == arch_crisv32
1143 ? BA_DWORD_OPCODE
d2aa3f9f
HPN
1144 : (pic ? MOVE_PC_INCR_OPCODE_PREFIX
1145 : JUMP_PC_INCR_OPCODE),
ae57792d 1146 2);
3bcbcc3d 1147
08caf3f8 1148 /* Follow with a ".DWORD to_addr", PC-relative for PIC. */
3bcbcc3d 1149 fix_new (fragP, storep + 2 - fragP->fr_literal, 4, to_symbol,
ae57792d
HPN
1150 cris_arch == arch_crisv32 ? 6 : 0,
1151 cris_arch == arch_crisv32 || pic ? 1 : 0,
1152 cris_arch == arch_crisv32 || pic
1153 ? BFD_RELOC_32_PCREL : BFD_RELOC_32);
1154
1155 /* Follow it with a "NOP" for CRISv32. */
1156 if (cris_arch == arch_crisv32)
1157 md_number_to_chars (storep + 6, NOP_OPCODE_V32, 2);
d2aa3f9f
HPN
1158 else if (pic)
1159 /* ...and the rest of the move-opcode for pre-v32 PIC. */
1160 md_number_to_chars (storep + 6, MOVE_PC_INCR_OPCODE_SUFFIX, 2);
3bcbcc3d
HPN
1161 }
1162}
1163
ed67db7a
HPN
1164/* Allocate space for the first piece of an insn, and mark it as the
1165 start of the insn for debug-format use. */
1166
1167static char *
695a4822 1168cris_insn_first_word_frag (void)
ed67db7a
HPN
1169{
1170 char *insnp = frag_more (2);
1171
1172 /* We need to mark the start of the insn by passing dwarf2_emit_insn
1173 the offset from the current fragment position. This must be done
1174 after the first fragment is created but before any other fragments
1175 (fixed or varying) are created. Note that the offset only
1176 corresponds to the "size" of the insn for a fixed-size,
1177 non-expanded insn. */
1178 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1179 dwarf2_emit_insn (2);
1180
1181 return insnp;
1182}
1183
3bcbcc3d 1184/* Port-specific assembler initialization. */
47926f60 1185
3bcbcc3d 1186void
695a4822 1187md_begin (void)
3bcbcc3d 1188{
3bcbcc3d
HPN
1189 int i = 0;
1190
47926f60 1191 /* Set up a hash table for the instructions. */
629310ab 1192 op_hash = str_htab_create ();
3bcbcc3d
HPN
1193 if (op_hash == NULL)
1194 as_fatal (_("Virtual memory exhausted"));
1195
ae57792d
HPN
1196 /* Enable use of ".if ..asm.arch.cris.v32"
1197 and ".if ..asm.arch.cris.common_v10_v32" and a few others. */
1198 symbol_table_insert (symbol_new ("..asm.arch.cris.v32", absolute_section,
e01e1cee
AM
1199 &zero_address_frag,
1200 cris_arch == arch_crisv32));
ae57792d 1201 symbol_table_insert (symbol_new ("..asm.arch.cris.v10", absolute_section,
e01e1cee
AM
1202 &zero_address_frag,
1203 cris_arch == arch_crisv10));
ae57792d
HPN
1204 symbol_table_insert (symbol_new ("..asm.arch.cris.common_v10_v32",
1205 absolute_section,
e01e1cee
AM
1206 &zero_address_frag,
1207 cris_arch == arch_cris_common_v10_v32));
ae57792d
HPN
1208 symbol_table_insert (symbol_new ("..asm.arch.cris.any_v0_v10",
1209 absolute_section,
e01e1cee
AM
1210 &zero_address_frag,
1211 cris_arch == arch_cris_any_v0_v10));
ae57792d 1212
3bcbcc3d
HPN
1213 while (cris_opcodes[i].name != NULL)
1214 {
1215 const char *name = cris_opcodes[i].name;
ae57792d
HPN
1216
1217 if (! cris_insn_ver_valid_for_arch (cris_opcodes[i].applicable_version,
1218 cris_arch))
1219 {
1220 i++;
1221 continue;
1222 }
1223
629310ab
ML
1224 /* Need to cast to get rid of "const". FIXME: Fix str_hash_insert instead. */
1225 str_hash_insert (op_hash, name, (void *) &cris_opcodes[i]);
3bcbcc3d
HPN
1226 do
1227 {
1228 if (cris_opcodes[i].match & cris_opcodes[i].lose)
1229 as_fatal (_("Buggy opcode: `%s' \"%s\"\n"), cris_opcodes[i].name,
1230 cris_opcodes[i].args);
1231
1232 ++i;
47926f60
KH
1233 }
1234 while (cris_opcodes[i].name != NULL
1235 && strcmp (cris_opcodes[i].name, name) == 0);
3bcbcc3d
HPN
1236 }
1237}
1238
3bcbcc3d 1239/* Assemble a source line. */
47926f60 1240
3bcbcc3d 1241void
695a4822 1242md_assemble (char *str)
3bcbcc3d
HPN
1243{
1244 struct cris_instruction output_instruction;
1245 struct cris_prefix prefix;
1246 char *opcodep;
1247 char *p;
1248
1249 know (str);
1250
1251 /* Do the low-level grunt - assemble to bits and split up into a prefix
1252 and ordinary insn. */
1253 cris_process_instruction (str, &output_instruction, &prefix);
1254
1255 /* Handle any prefixes to the instruction. */
1256 switch (prefix.kind)
1257 {
1258 case PREFIX_NONE:
1259 break;
1260
1261 /* When the expression is unknown for a BDAP, it can need 0, 2 or 4
1262 extra bytes, so we handle it separately. */
1263 case PREFIX_BDAP_IMM:
cc99daad 1264 /* We only do it if the relocation is unspecified, i.e. not a PIC or TLS
08caf3f8
HPN
1265 relocation. */
1266 if (prefix.reloc == BFD_RELOC_NONE)
1267 {
1268 gen_bdap (prefix.base_reg_number, &prefix.expr);
1269 break;
1270 }
1271 /* Fall through. */
3bcbcc3d
HPN
1272 case PREFIX_BDAP:
1273 case PREFIX_BIAP:
1274 case PREFIX_DIP:
ed67db7a 1275 opcodep = cris_insn_first_word_frag ();
3bcbcc3d
HPN
1276
1277 /* Output the prefix opcode. */
1278 md_number_to_chars (opcodep, (long) prefix.opcode, 2);
1279
08caf3f8 1280 /* Having a specified reloc only happens for DIP and for BDAP with
cc99daad 1281 PIC or TLS operands, but it is ok to drop through here for the other
08caf3f8 1282 prefixes as they can have no relocs specified. */
3bcbcc3d
HPN
1283 if (prefix.reloc != BFD_RELOC_NONE)
1284 {
08caf3f8
HPN
1285 unsigned int relocsize
1286 = (prefix.kind == PREFIX_DIP
cc99daad 1287 ? 4 : cris_get_specified_reloc_size (prefix.reloc));
08caf3f8 1288
08caf3f8
HPN
1289 p = frag_more (relocsize);
1290 fix_new_exp (frag_now, (p - frag_now->fr_literal), relocsize,
3bcbcc3d
HPN
1291 &prefix.expr, 0, prefix.reloc);
1292 }
1293 break;
1294
1295 case PREFIX_PUSH:
ed67db7a 1296 opcodep = cris_insn_first_word_frag ();
3bcbcc3d
HPN
1297
1298 /* Output the prefix opcode. Being a "push", we add the negative
1299 size of the register to "sp". */
1300 if (output_instruction.spec_reg != NULL)
1301 {
47926f60 1302 /* Special register. */
3bcbcc3d
HPN
1303 opcodep[0] = -output_instruction.spec_reg->reg_size;
1304 }
1305 else
1306 {
47926f60 1307 /* General register. */
3bcbcc3d
HPN
1308 opcodep[0] = -4;
1309 }
1310 opcodep[1] = (REG_SP << 4) + (BDAP_QUICK_OPCODE >> 8);
1311 break;
1312
1313 default:
1314 BAD_CASE (prefix.kind);
1315 }
1316
1317 /* If we only had a prefix insn, we're done. */
1318 if (output_instruction.insn_type == CRIS_INSN_NONE)
1319 return;
1320
1321 /* Done with the prefix. Continue with the main instruction. */
ed67db7a
HPN
1322 if (prefix.kind == PREFIX_NONE)
1323 opcodep = cris_insn_first_word_frag ();
1324 else
1325 opcodep = frag_more (2);
3bcbcc3d
HPN
1326
1327 /* Output the instruction opcode. */
47926f60 1328 md_number_to_chars (opcodep, (long) (output_instruction.opcode), 2);
3bcbcc3d
HPN
1329
1330 /* Output the symbol-dependent instruction stuff. */
1331 if (output_instruction.insn_type == CRIS_INSN_BRANCH)
1332 {
1333 segT to_seg = absolute_section;
1334 int is_undefined = 0;
1335 int length_code;
1336
1337 if (output_instruction.expr.X_op != O_constant)
1338 {
1339 to_seg = S_GET_SEGMENT (output_instruction.expr.X_add_symbol);
1340
1341 if (to_seg == undefined_section)
1342 is_undefined = 1;
1343 }
1344
ae57792d
HPN
1345 if (to_seg == now_seg || is_undefined
1346 /* In CRISv32, there *is* a 32-bit absolute branch, so don't
1347 emit the 12-byte sequence for known symbols in other
1348 segments. */
1349 || (cris_arch == arch_crisv32
1350 && output_instruction.opcode == BA_QUICK_OPCODE))
3bcbcc3d 1351 {
08caf3f8
HPN
1352 /* Handle complex expressions. */
1353 valueT addvalue
1c971160
HPN
1354 = (SIMPLE_EXPR (&output_instruction.expr)
1355 ? output_instruction.expr.X_add_number
1356 : 0);
08caf3f8 1357 symbolS *sym
1c971160
HPN
1358 = (SIMPLE_EXPR (&output_instruction.expr)
1359 ? output_instruction.expr.X_add_symbol
1360 : make_expr_symbol (&output_instruction.expr));
08caf3f8 1361
ae57792d
HPN
1362 /* If is_undefined, the expression may still become now_seg.
1363 That case is handled by md_estimate_size_before_relax. */
1364 length_code = to_seg == now_seg ? STATE_BYTE : STATE_UNDF;
1365
d2aa3f9f
HPN
1366 /* Make room for max twelve bytes of variable length for v32 mode
1367 or PIC, ten for v10 and older. */
ae57792d
HPN
1368 frag_var (rs_machine_dependent,
1369 (cris_arch == arch_crisv32
d2aa3f9f
HPN
1370 || cris_arch == arch_cris_common_v10_v32
1371 || pic) ? 12 : 10, 0,
ae57792d
HPN
1372 ENCODE_RELAX (cris_arch == arch_crisv32
1373 ? (output_instruction.opcode
1374 == BA_QUICK_OPCODE
1375 ? STATE_ABS_BRANCH_V32
1376 : STATE_COND_BRANCH_V32)
1377 : (cris_arch == arch_cris_common_v10_v32
1378 ? STATE_COND_BRANCH_COMMON
d2aa3f9f
HPN
1379 : (pic ? STATE_COND_BRANCH_PIC
1380 : STATE_COND_BRANCH)),
ae57792d 1381 length_code),
08caf3f8 1382 sym, addvalue, opcodep);
3bcbcc3d
HPN
1383 }
1384 else
1385 {
1386 /* We have: to_seg != now_seg && to_seg != undefined_section.
1387 This means it is a branch to a known symbol in another
fb2fd3e1 1388 section, perhaps an absolute address. Emit a 32-bit branch. */
ae57792d
HPN
1389 char *cond_jump
1390 = frag_more ((cris_arch == arch_crisv32
d2aa3f9f
HPN
1391 || cris_arch == arch_cris_common_v10_v32
1392 || pic)
ae57792d 1393 ? 12 : 10);
08caf3f8 1394
08caf3f8 1395 gen_cond_branch_32 (opcodep, cond_jump, frag_now,
3bcbcc3d 1396 output_instruction.expr.X_add_symbol,
47926f60 1397 (symbolS *) NULL,
3bcbcc3d
HPN
1398 output_instruction.expr.X_add_number);
1399 }
1400 }
1048a9ba
HPN
1401 else if (output_instruction.insn_type == CRIS_INSN_MUL
1402 && err_for_dangerous_mul_placement)
1403 /* Create a frag which which we track the location of the mul insn
1404 (in the last two bytes before the mul-frag). */
1405 frag_variant (rs_machine_dependent, 0, 0,
1406 ENCODE_RELAX (STATE_MUL, STATE_BYTE),
1407 NULL, 0, opcodep);
3bcbcc3d
HPN
1408 else
1409 {
1410 if (output_instruction.imm_oprnd_size > 0)
1411 {
2d2255b5 1412 /* The instruction has an immediate operand. */
08caf3f8 1413 enum bfd_reloc_code_real reloc = BFD_RELOC_NONE;
3bcbcc3d
HPN
1414
1415 switch (output_instruction.imm_oprnd_size)
1416 {
1417 /* Any byte-size immediate constants are treated as
1418 word-size. FIXME: Thus overflow check does not work
1419 correctly. */
1420
1421 case 2:
08caf3f8
HPN
1422 /* Note that size-check for the explicit reloc has already
1423 been done when we get here. */
1424 if (output_instruction.reloc != BFD_RELOC_NONE)
1425 reloc = output_instruction.reloc;
1426 else
1427 reloc = BFD_RELOC_16;
3bcbcc3d
HPN
1428 break;
1429
1430 case 4:
08caf3f8
HPN
1431 /* Allow a relocation specified in the operand. */
1432 if (output_instruction.reloc != BFD_RELOC_NONE)
1433 reloc = output_instruction.reloc;
1434 else
1435 reloc = BFD_RELOC_32;
3bcbcc3d
HPN
1436 break;
1437
1438 default:
1439 BAD_CASE (output_instruction.imm_oprnd_size);
1440 }
1441
1442 p = frag_more (output_instruction.imm_oprnd_size);
1443 fix_new_exp (frag_now, (p - frag_now->fr_literal),
1444 output_instruction.imm_oprnd_size,
ae57792d
HPN
1445 &output_instruction.expr,
1446 reloc == BFD_RELOC_32_PCREL
1447 || reloc == BFD_RELOC_16_PCREL
1448 || reloc == BFD_RELOC_8_PCREL, reloc);
1449 }
1450 else if (output_instruction.reloc == BFD_RELOC_CRIS_LAPCQ_OFFSET
1451 && output_instruction.expr.X_md != 0)
1452 {
1453 /* Handle complex expressions. */
1454 valueT addvalue
1455 = (output_instruction.expr.X_op_symbol != NULL
1456 ? 0 : output_instruction.expr.X_add_number);
1457 symbolS *sym
1458 = (output_instruction.expr.X_op_symbol != NULL
1459 ? make_expr_symbol (&output_instruction.expr)
1460 : output_instruction.expr.X_add_symbol);
1461
1462 /* This is a relaxing construct, so we need a frag_var rather
1463 than the fix_new_exp call below. */
1464 frag_var (rs_machine_dependent,
1465 4, 0,
1466 ENCODE_RELAX (STATE_LAPC, STATE_UNDF),
1467 sym, addvalue, opcodep);
3bcbcc3d
HPN
1468 }
1469 else if (output_instruction.reloc != BFD_RELOC_NONE)
1470 {
1471 /* An immediate operand that has a relocation and needs to be
47926f60 1472 processed further. */
3bcbcc3d
HPN
1473
1474 /* It is important to use fix_new_exp here and everywhere else
1475 (and not fix_new), as fix_new_exp can handle "difference
1476 expressions" - where the expression contains a difference of
1477 two symbols in the same segment. */
1478 fix_new_exp (frag_now, (opcodep - frag_now->fr_literal), 2,
ae57792d
HPN
1479 &output_instruction.expr,
1480 output_instruction.reloc == BFD_RELOC_32_PCREL
1481 || output_instruction.reloc == BFD_RELOC_16_PCREL
1482 || output_instruction.reloc == BFD_RELOC_8_PCREL
1483 || (output_instruction.reloc
1484 == BFD_RELOC_CRIS_LAPCQ_OFFSET),
3bcbcc3d
HPN
1485 output_instruction.reloc);
1486 }
1487 }
1488}
1489
29cf29a2
HPN
1490/* Helper error-reporting function: calls as_bad for a format string
1491 for a single value and zeroes the offending value (zero assumed
1492 being a valid value) to avoid repeated error reports in later value
1493 checking. */
1494
1495static void
1496cris_bad (const char *format, offsetT *valp)
1497{
1498 /* We cast to long so the format string can assume that format. */
1499 as_bad (format, (long) *valp);
1500 *valp = 0;
1501}
1502
3bcbcc3d 1503/* Low level text-to-bits assembly. */
47926f60 1504
3bcbcc3d 1505static void
695a4822
HPN
1506cris_process_instruction (char *insn_text, struct cris_instruction *out_insnp,
1507 struct cris_prefix *prefixp)
3bcbcc3d 1508{
47926f60
KH
1509 char *s;
1510 char modified_char = 0;
1511 const char *args;
3bcbcc3d 1512 struct cris_opcode *instruction;
47926f60
KH
1513 char *operands;
1514 int match = 0;
1515 int mode;
1516 int regno;
1517 int size_bits;
3bcbcc3d
HPN
1518
1519 /* Reset these fields to a harmless state in case we need to return in
1520 error. */
1521 prefixp->kind = PREFIX_NONE;
1522 prefixp->reloc = BFD_RELOC_NONE;
ae57792d 1523 out_insnp->insn_type = CRIS_INSN_NONE;
3bcbcc3d
HPN
1524 out_insnp->imm_oprnd_size = 0;
1525
1526 /* Find the end of the opcode mnemonic. We assume (true in 2.9.1)
1527 that the caller has translated the opcode to lower-case, up to the
47926f60 1528 first non-letter. */
3882b010 1529 for (operands = insn_text; ISLOWER (*operands); ++operands)
3bcbcc3d
HPN
1530 ;
1531
1532 /* Terminate the opcode after letters, but save the character there if
1533 it was of significance. */
1534 switch (*operands)
1535 {
1536 case '\0':
1537 break;
1538
1539 case '.':
47926f60 1540 /* Put back the modified character later. */
3bcbcc3d 1541 modified_char = *operands;
47926f60 1542 /* Fall through. */
3bcbcc3d
HPN
1543
1544 case ' ':
47926f60
KH
1545 /* Consume the character after the mnemonic
1546 and replace it with '\0'. */
3bcbcc3d
HPN
1547 *operands++ = '\0';
1548 break;
1549
1550 default:
1551 as_bad (_("Unknown opcode: `%s'"), insn_text);
1552 return;
1553 }
1554
1555 /* Find the instruction. */
629310ab 1556 instruction = (struct cris_opcode *) str_hash_find (op_hash, insn_text);
3bcbcc3d
HPN
1557 if (instruction == NULL)
1558 {
1559 as_bad (_("Unknown opcode: `%s'"), insn_text);
1560 return;
1561 }
1562
1563 /* Put back the modified character. */
1564 switch (modified_char)
1565 {
1566 case 0:
1567 break;
1568
1569 default:
1570 *--operands = modified_char;
1571 }
1572
3bcbcc3d 1573 /* Try to match an opcode table slot. */
47926f60 1574 for (s = operands;;)
3bcbcc3d 1575 {
47926f60 1576 int imm_expr_found;
3bcbcc3d
HPN
1577
1578 /* Initialize *prefixp, perhaps after being modified for a
47926f60 1579 "near match". */
3bcbcc3d
HPN
1580 prefixp->kind = PREFIX_NONE;
1581 prefixp->reloc = BFD_RELOC_NONE;
1582
1583 /* Initialize *out_insnp. */
1584 memset (out_insnp, 0, sizeof (*out_insnp));
1585 out_insnp->opcode = instruction->match;
1586 out_insnp->reloc = BFD_RELOC_NONE;
1587 out_insnp->insn_type = CRIS_INSN_NORMAL;
1588 out_insnp->imm_oprnd_size = 0;
1589
1590 imm_expr_found = 0;
1591
1592 /* Build the opcode, checking as we go to make sure that the
1593 operands match. */
47926f60 1594 for (args = instruction->args;; ++args)
3bcbcc3d
HPN
1595 {
1596 switch (*args)
1597 {
1598 case '\0':
1599 /* If we've come to the end of arguments, we're done. */
1600 if (*s == '\0')
1601 match = 1;
1602 break;
1603
1604 case '!':
1605 /* Non-matcher character for disassembly.
1606 Ignore it here. */
1607 continue;
1608
ae57792d
HPN
1609 case '[':
1610 case ']':
3bcbcc3d
HPN
1611 case ',':
1612 case ' ':
1613 /* These must match exactly. */
1614 if (*s++ == *args)
1615 continue;
1616 break;
1617
ae57792d
HPN
1618 case 'A':
1619 /* "ACR", case-insensitive.
1620 Handle a sometimes-mandatory dollar sign as register
1621 prefix. */
1622 if (*s == REGISTER_PREFIX_CHAR)
1623 s++;
1624 else if (demand_register_prefix)
1625 break;
1626
1627 if ((*s++ != 'a' && s[-1] != 'A')
1628 || (*s++ != 'c' && s[-1] != 'C')
1629 || (*s++ != 'r' && s[-1] != 'R'))
1630 break;
1631 continue;
1632
3bcbcc3d
HPN
1633 case 'B':
1634 /* This is not really an operand, but causes a "BDAP
47926f60 1635 -size,SP" prefix to be output, for PUSH instructions. */
3bcbcc3d
HPN
1636 prefixp->kind = PREFIX_PUSH;
1637 continue;
1638
1639 case 'b':
1640 /* This letter marks an operand that should not be matched
1641 in the assembler. It is a branch with 16-bit
1642 displacement. The assembler will create them from the
1643 8-bit flavor when necessary. The assembler does not
1644 support the [rN+] operand, as the [r15+] that is
1645 generated for 16-bit displacements. */
1646 break;
1647
1648 case 'c':
1649 /* A 5-bit unsigned immediate in bits <4:0>. */
1650 if (! cris_get_expression (&s, &out_insnp->expr))
1651 break;
1652 else
1653 {
1654 if (out_insnp->expr.X_op == O_constant
1655 && (out_insnp->expr.X_add_number < 0
1656 || out_insnp->expr.X_add_number > 31))
29cf29a2
HPN
1657 cris_bad (_("Immediate value not in 5 bit unsigned range: %ld"),
1658 &out_insnp->expr.X_add_number);
3bcbcc3d
HPN
1659
1660 out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_5;
1661 continue;
1662 }
1663
1664 case 'C':
1665 /* A 4-bit unsigned immediate in bits <3:0>. */
1666 if (! cris_get_expression (&s, &out_insnp->expr))
1667 break;
1668 else
1669 {
1670 if (out_insnp->expr.X_op == O_constant
1671 && (out_insnp->expr.X_add_number < 0
1672 || out_insnp->expr.X_add_number > 15))
29cf29a2
HPN
1673 cris_bad (_("Immediate value not in 4 bit unsigned range: %ld"),
1674 &out_insnp->expr.X_add_number);
3bcbcc3d
HPN
1675
1676 out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_4;
1677 continue;
1678 }
1679
ae57792d
HPN
1680 /* For 'd', check for an optional ".d" or ".D" at the
1681 start of the operands, followed by a space character. */
1682 case 'd':
1683 if (modified_char == '.' && *s == '.')
1684 {
1685 if ((s[1] != 'd' && s[1] == 'D')
1686 || ! ISSPACE (s[2]))
1687 break;
1688 s += 2;
1689 continue;
1690 }
1691 continue;
1692
3bcbcc3d
HPN
1693 case 'D':
1694 /* General register in bits <15:12> and <3:0>. */
1695 if (! get_gen_reg (&s, &regno))
1696 break;
1697 else
1698 {
1699 out_insnp->opcode |= regno /* << 0 */;
1700 out_insnp->opcode |= regno << 12;
1701 continue;
1702 }
1703
1704 case 'f':
1705 /* Flags from the condition code register. */
1706 {
1707 int flags = 0;
1708
1709 if (! get_flags (&s, &flags))
1710 break;
1711
47926f60 1712 out_insnp->opcode |= ((flags & 0xf0) << 8) | (flags & 0xf);
3bcbcc3d
HPN
1713 continue;
1714 }
1715
1716 case 'i':
1717 /* A 6-bit signed immediate in bits <5:0>. */
1718 if (! cris_get_expression (&s, &out_insnp->expr))
1719 break;
1720 else
1721 {
1722 if (out_insnp->expr.X_op == O_constant
1723 && (out_insnp->expr.X_add_number < -32
1724 || out_insnp->expr.X_add_number > 31))
29cf29a2
HPN
1725 cris_bad (_("Immediate value not in 6 bit range: %ld"),
1726 &out_insnp->expr.X_add_number);
1727
3bcbcc3d
HPN
1728 out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_6;
1729 continue;
1730 }
1731
1732 case 'I':
1733 /* A 6-bit unsigned immediate in bits <5:0>. */
1734 if (! cris_get_expression (&s, &out_insnp->expr))
1735 break;
1736 else
1737 {
1738 if (out_insnp->expr.X_op == O_constant
1739 && (out_insnp->expr.X_add_number < 0
1740 || out_insnp->expr.X_add_number > 63))
29cf29a2
HPN
1741 cris_bad (_("Immediate value not in 6 bit unsigned range: %ld"),
1742 &out_insnp->expr.X_add_number);
1743
3bcbcc3d
HPN
1744 out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_6;
1745 continue;
1746 }
1747
1748 case 'M':
1749 /* A size modifier, B, W or D, to be put in a bit position
1750 suitable for CLEAR instructions (i.e. reflecting a zero
1751 register). */
1752 if (! get_bwd_size_modifier (&s, &size_bits))
1753 break;
1754 else
1755 {
1756 switch (size_bits)
1757 {
1758 case 0:
1759 out_insnp->opcode |= 0 << 12;
1760 break;
1761
1762 case 1:
1763 out_insnp->opcode |= 4 << 12;
1764 break;
1765
1766 case 2:
1767 out_insnp->opcode |= 8 << 12;
1768 break;
1769 }
1770 continue;
1771 }
1772
1773 case 'm':
1774 /* A size modifier, B, W or D, to be put in bits <5:4>. */
ae57792d
HPN
1775 if (modified_char != '.'
1776 || ! get_bwd_size_modifier (&s, &size_bits))
3bcbcc3d
HPN
1777 break;
1778 else
1779 {
1780 out_insnp->opcode |= size_bits << 4;
1781 continue;
1782 }
1783
1784 case 'o':
1785 /* A branch expression. */
1786 if (! cris_get_expression (&s, &out_insnp->expr))
1787 break;
1788 else
1789 {
1790 out_insnp->insn_type = CRIS_INSN_BRANCH;
1791 continue;
1792 }
1793
ae57792d
HPN
1794 case 'Q':
1795 /* A 8-bit quick BDAP expression, "expr,R". */
1796 if (! cris_get_expression (&s, &out_insnp->expr))
1797 break;
1798
1799 if (*s != ',')
1800 break;
1801
1802 s++;
1803
1804 if (!get_gen_reg (&s, &regno))
1805 break;
1806
1807 out_insnp->opcode |= regno << 12;
1808 out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_8;
1809 continue;
3739860c 1810
3bcbcc3d 1811 case 'O':
ae57792d 1812 /* A BDAP expression for any size, "expr,R". */
3bcbcc3d
HPN
1813 if (! cris_get_expression (&s, &prefixp->expr))
1814 break;
1815 else
1816 {
1817 if (*s != ',')
1818 break;
1819
1820 s++;
1821
1822 if (!get_gen_reg (&s, &prefixp->base_reg_number))
1823 break;
1824
1825 /* Since 'O' is used with an explicit bdap, we have no
47926f60 1826 "real" instruction. */
3bcbcc3d 1827 prefixp->kind = PREFIX_BDAP_IMM;
08caf3f8
HPN
1828 prefixp->opcode
1829 = BDAP_QUICK_OPCODE | (prefixp->base_reg_number << 12);
1830
3bcbcc3d
HPN
1831 out_insnp->insn_type = CRIS_INSN_NONE;
1832 continue;
1833 }
1834
1835 case 'P':
1836 /* Special register in bits <15:12>. */
1837 if (! get_spec_reg (&s, &out_insnp->spec_reg))
1838 break;
1839 else
1840 {
1841 /* Use of some special register names come with a
1842 specific warning. Note that we have no ".cpu type"
1843 pseudo yet, so some of this is just unused
1844 framework. */
1845 if (out_insnp->spec_reg->warning)
20203fb9 1846 as_warn ("%s", out_insnp->spec_reg->warning);
3bcbcc3d
HPN
1847 else if (out_insnp->spec_reg->applicable_version
1848 == cris_ver_warning)
1849 /* Others have a generic warning. */
1850 as_warn (_("Unimplemented register `%s' specified"),
1851 out_insnp->spec_reg->name);
1852
1853 out_insnp->opcode
1854 |= out_insnp->spec_reg->number << 12;
1855 continue;
1856 }
1857
1858 case 'p':
1859 /* This character is used in the disassembler to
1860 recognize a prefix instruction to fold into the
1861 addressing mode for the next instruction. It is
47926f60 1862 ignored here. */
3bcbcc3d
HPN
1863 continue;
1864
1865 case 'R':
1866 /* General register in bits <15:12>. */
1867 if (! get_gen_reg (&s, &regno))
1868 break;
1869 else
1870 {
1871 out_insnp->opcode |= regno << 12;
1872 continue;
1873 }
1874
1875 case 'r':
1876 /* General register in bits <3:0>. */
1877 if (! get_gen_reg (&s, &regno))
1878 break;
1879 else
1880 {
1881 out_insnp->opcode |= regno /* << 0 */;
1882 continue;
1883 }
1884
1885 case 'S':
1886 /* Source operand in bit <10> and a prefix; a 3-operand
1887 prefix. */
1888 if (! get_3op_or_dip_prefix_op (&s, prefixp))
1889 break;
1890 else
1891 continue;
1892
1893 case 's':
1894 /* Source operand in bits <10>, <3:0> and optionally a
1895 prefix; i.e. an indirect operand or an side-effect
ae57792d 1896 prefix (where valid). */
3bcbcc3d
HPN
1897 if (! get_autoinc_prefix_or_indir_op (&s, prefixp, &mode,
1898 &regno,
1899 &imm_expr_found,
1900 &out_insnp->expr))
1901 break;
1902 else
1903 {
1904 if (prefixp->kind != PREFIX_NONE)
1905 {
1906 /* A prefix, so it has the autoincrement bit
1907 set. */
1908 out_insnp->opcode |= (AUTOINCR_BIT << 8);
1909 }
1910 else
08caf3f8
HPN
1911 {
1912 /* No prefix. The "mode" variable contains bits like
1913 whether or not this is autoincrement mode. */
1914 out_insnp->opcode |= (mode << 10);
1915
cc99daad 1916 /* If there was a reloc specifier, then it was
08caf3f8
HPN
1917 attached to the prefix. Note that we can't check
1918 that the reloc size matches, since we don't have
1919 all the operands yet in all cases. */
1920 if (prefixp->reloc != BFD_RELOC_NONE)
1921 out_insnp->reloc = prefixp->reloc;
1922 }
3bcbcc3d
HPN
1923
1924 out_insnp->opcode |= regno /* << 0 */ ;
1925 continue;
1926 }
1927
ae57792d
HPN
1928 case 'N':
1929 case 'Y':
cc99daad
HPN
1930 /* Like 's', but immediate operand only. Also do not
1931 modify insn. There are no insns where an explicit reloc
ae57792d
HPN
1932 specifier makes sense. */
1933 if (cris_get_expression (&s, &out_insnp->expr))
1934 {
1935 imm_expr_found = 1;
1936 continue;
1937 }
1938 break;
1939
1940 case 'n':
1941 /* Like 'N', but PC-relative to the start of the insn.
1942 There might be a :PLT to request a PLT entry. */
1943 if (cris_get_expression (&s, &out_insnp->expr))
1944 {
1945 imm_expr_found = 1;
1946 out_insnp->reloc = BFD_RELOC_32_PCREL;
1947
1948 /* We have to adjust the expression, because that
1949 relocation is to the location *after* the
1950 relocation. So add 2 for the insn and 4 for the
1951 relocation. */
1952 out_insnp->expr.X_add_number += 6;
1953
cc99daad
HPN
1954 /* TLS specifiers do not make sense here. */
1955 if (pic && *s == RELOC_SUFFIX_CHAR)
1956 cris_get_reloc_suffix (&s, &out_insnp->reloc,
1957 &out_insnp->expr);
ae57792d
HPN
1958
1959 continue;
1960 }
1961 break;
1962
1963 case 'U':
1964 /* Maybe 'u', maybe 'n'. Only for LAPC/LAPCQ. */
1965 if (cris_get_expression (&s, &out_insnp->expr))
1966 {
1967 out_insnp->reloc = BFD_RELOC_CRIS_LAPCQ_OFFSET;
1968
1969 /* Define 1 as relaxing. */
1970 out_insnp->expr.X_md = 1;
1971 continue;
1972 }
1973 break;
1974
1975 case 'u':
1976 /* Four PC-relative bits in <3:0> representing <4:1>:0 of
1977 an offset relative to the beginning of the current
1978 insn. */
1979 if (cris_get_expression (&s, &out_insnp->expr))
1980 {
1981 out_insnp->reloc = BFD_RELOC_CRIS_LAPCQ_OFFSET;
1982
1983 /* Define 0 as non-relaxing. */
1984 out_insnp->expr.X_md = 0;
1985
1986 /* We have to adjust the expression, because that
1987 relocation is to the location *after* the
1988 insn. So add 2 for the insn. */
1989 out_insnp->expr.X_add_number += 2;
1990 continue;
1991 }
1992 break;
1993
3bcbcc3d
HPN
1994 case 'x':
1995 /* Rs.m in bits <15:12> and <5:4>. */
1996 if (! get_gen_reg (&s, &regno)
1997 || ! get_bwd_size_modifier (&s, &size_bits))
1998 break;
1999 else
2000 {
47926f60 2001 out_insnp->opcode |= (regno << 12) | (size_bits << 4);
3bcbcc3d
HPN
2002 continue;
2003 }
2004
2005 case 'y':
2006 /* Source operand in bits <10>, <3:0> and optionally a
2007 prefix; i.e. an indirect operand or an side-effect
2008 prefix.
2009
2010 The difference to 's' is that this does not allow an
81d4177b 2011 "immediate" expression. */
3bcbcc3d
HPN
2012 if (! get_autoinc_prefix_or_indir_op (&s, prefixp,
2013 &mode, &regno,
2014 &imm_expr_found,
2015 &out_insnp->expr)
2016 || imm_expr_found)
2017 break;
2018 else
2019 {
2020 if (prefixp->kind != PREFIX_NONE)
2021 {
2022 /* A prefix, and those matched here always have
2023 side-effects (see 's' case). */
2024 out_insnp->opcode |= (AUTOINCR_BIT << 8);
2025 }
2026 else
2027 {
2028 /* No prefix. The "mode" variable contains bits
2029 like whether or not this is autoincrement
2030 mode. */
2031 out_insnp->opcode |= (mode << 10);
2032 }
2033
2034 out_insnp->opcode |= regno /* << 0 */;
2035 continue;
2036 }
2037
2038 case 'z':
2039 /* Size modifier (B or W) in bit <4>. */
2040 if (! get_bw_size_modifier (&s, &size_bits))
2041 break;
2042 else
2043 {
2044 out_insnp->opcode |= size_bits << 4;
2045 continue;
2046 }
2047
ae57792d
HPN
2048 case 'T':
2049 if (cris_arch == arch_crisv32
2050 && get_sup_reg (&s, &regno))
2051 {
2052 out_insnp->opcode |= regno << 12;
2053 continue;
2054 }
2055 break;
2056
3bcbcc3d
HPN
2057 default:
2058 BAD_CASE (*args);
2059 }
2060
2061 /* We get here when we fail a match above or we found a
2062 complete match. Break out of this loop. */
2063 break;
2064 }
2065
2066 /* Was it a match or a miss? */
2067 if (match == 0)
2068 {
2069 /* If it's just that the args don't match, maybe the next
2070 item in the table is the same opcode but with
ae57792d
HPN
2071 matching operands. First skip any invalid ones. */
2072 while (instruction[1].name != NULL
2073 && strcmp (instruction->name, instruction[1].name) == 0
2074 && ! cris_insn_ver_valid_for_arch (instruction[1]
2075 .applicable_version,
2076 cris_arch))
2077 ++instruction;
2078
3bcbcc3d 2079 if (instruction[1].name != NULL
ae57792d
HPN
2080 && strcmp (instruction->name, instruction[1].name) == 0
2081 && cris_insn_ver_valid_for_arch (instruction[1]
2082 .applicable_version,
2083 cris_arch))
3bcbcc3d
HPN
2084 {
2085 /* Yep. Restart and try that one instead. */
2086 ++instruction;
2087 s = operands;
2088 continue;
2089 }
2090 else
2091 {
2092 /* We've come to the end of instructions with this
2093 opcode, so it must be an error. */
2094 as_bad (_("Illegal operands"));
ae57792d
HPN
2095
2096 /* As discard_rest_of_line, but without continuing to the
2097 next line. */
2098 while (!is_end_of_line[(unsigned char) *input_line_pointer])
2099 input_line_pointer++;
3bcbcc3d
HPN
2100 return;
2101 }
2102 }
2103 else
2104 {
2105 /* We have a match. Check if there's anything more to do. */
2106 if (imm_expr_found)
2107 {
2108 /* There was an immediate mode operand, so we must check
2109 that it has an appropriate size. */
3bcbcc3d
HPN
2110 switch (instruction->imm_oprnd_size)
2111 {
2112 default:
2113 case SIZE_NONE:
2114 /* Shouldn't happen; this one does not have immediate
2115 operands with different sizes. */
2116 BAD_CASE (instruction->imm_oprnd_size);
2117 break;
2118
2119 case SIZE_FIX_32:
2120 out_insnp->imm_oprnd_size = 4;
2121 break;
2122
2123 case SIZE_SPEC_REG:
ae57792d
HPN
2124 if (cris_arch == arch_crisv32)
2125 /* All immediate loads of special registers are
2126 32-bit on CRISv32. */
2127 out_insnp->imm_oprnd_size = 4;
2128 else
2129 switch (out_insnp->spec_reg->reg_size)
2130 {
2131 case 1:
2132 if (out_insnp->expr.X_op == O_constant
2133 && (out_insnp->expr.X_add_number < -128
2134 || out_insnp->expr.X_add_number > 255))
29cf29a2
HPN
2135 cris_bad (_("Immediate value not in 8 bit range: %ld"),
2136 &out_insnp->expr.X_add_number);
ae57792d
HPN
2137 /* Fall through. */
2138 case 2:
2139 /* FIXME: We need an indicator in the instruction
2140 table to pass on, to indicate if we need to check
2141 overflow for a signed or unsigned number. */
2142 if (out_insnp->expr.X_op == O_constant
2143 && (out_insnp->expr.X_add_number < -32768
2144 || out_insnp->expr.X_add_number > 65535))
29cf29a2
HPN
2145 cris_bad (_("Immediate value not in 16 bit range: %ld"),
2146 &out_insnp->expr.X_add_number);
ae57792d
HPN
2147 out_insnp->imm_oprnd_size = 2;
2148 break;
2149
2150 case 4:
2151 out_insnp->imm_oprnd_size = 4;
2152 break;
2153
2154 default:
2155 BAD_CASE (out_insnp->spec_reg->reg_size);
2156 }
3bcbcc3d
HPN
2157 break;
2158
2159 case SIZE_FIELD:
ae57792d
HPN
2160 case SIZE_FIELD_SIGNED:
2161 case SIZE_FIELD_UNSIGNED:
3bcbcc3d
HPN
2162 switch (size_bits)
2163 {
ae57792d
HPN
2164 /* FIXME: Find way to pass un/signedness to
2165 caller, and set reloc type instead, postponing
2166 this check until cris_number_to_imm. That
2167 necessarily corrects the reloc type for the
2168 byte case, maybe requiring further changes. */
3bcbcc3d 2169 case 0:
ae57792d
HPN
2170 if (out_insnp->expr.X_op == O_constant)
2171 {
2172 if (instruction->imm_oprnd_size == SIZE_FIELD
2173 && (out_insnp->expr.X_add_number < -128
2174 || out_insnp->expr.X_add_number > 255))
29cf29a2
HPN
2175 cris_bad (_("Immediate value not in 8 bit range: %ld"),
2176 &out_insnp->expr.X_add_number);
ae57792d
HPN
2177 else if (instruction->imm_oprnd_size == SIZE_FIELD_SIGNED
2178 && (out_insnp->expr.X_add_number < -128
2179 || out_insnp->expr.X_add_number > 127))
29cf29a2
HPN
2180 cris_bad (_("Immediate value not in 8 bit signed range: %ld"),
2181 &out_insnp->expr.X_add_number);
ae57792d
HPN
2182 else if (instruction->imm_oprnd_size == SIZE_FIELD_UNSIGNED
2183 && (out_insnp->expr.X_add_number < 0
2184 || out_insnp->expr.X_add_number > 255))
29cf29a2
HPN
2185 cris_bad (_("Immediate value not in 8 bit unsigned range: %ld"),
2186 &out_insnp->expr.X_add_number);
ae57792d
HPN
2187 }
2188
47926f60 2189 /* Fall through. */
3bcbcc3d 2190 case 1:
ae57792d
HPN
2191 if (out_insnp->expr.X_op == O_constant)
2192 {
2193 if (instruction->imm_oprnd_size == SIZE_FIELD
2194 && (out_insnp->expr.X_add_number < -32768
2195 || out_insnp->expr.X_add_number > 65535))
29cf29a2
HPN
2196 cris_bad (_("Immediate value not in 16 bit range: %ld"),
2197 &out_insnp->expr.X_add_number);
ae57792d
HPN
2198 else if (instruction->imm_oprnd_size == SIZE_FIELD_SIGNED
2199 && (out_insnp->expr.X_add_number < -32768
2200 || out_insnp->expr.X_add_number > 32767))
29cf29a2
HPN
2201 cris_bad (_("Immediate value not in 16 bit signed range: %ld"),
2202 &out_insnp->expr.X_add_number);
ae57792d
HPN
2203 else if (instruction->imm_oprnd_size == SIZE_FIELD_UNSIGNED
2204 && (out_insnp->expr.X_add_number < 0
2205 || out_insnp->expr.X_add_number > 65535))
29cf29a2
HPN
2206 cris_bad (_("Immediate value not in 16 bit unsigned range: %ld"),
2207 &out_insnp->expr.X_add_number);
ae57792d 2208 }
3bcbcc3d
HPN
2209 out_insnp->imm_oprnd_size = 2;
2210 break;
2211
2212 case 2:
2213 out_insnp->imm_oprnd_size = 4;
2214 break;
2215
2216 default:
2217 BAD_CASE (out_insnp->spec_reg->reg_size);
2218 }
2219 }
08caf3f8
HPN
2220
2221 /* If there was a relocation specified for the immediate
cc99daad
HPN
2222 expression (i.e. it had a PIC or TLS modifier) check that the
2223 size of the relocation matches the size specified by
08caf3f8
HPN
2224 the opcode. */
2225 if (out_insnp->reloc != BFD_RELOC_NONE
cc99daad 2226 && (cris_get_specified_reloc_size (out_insnp->reloc)
08caf3f8 2227 != (unsigned int) out_insnp->imm_oprnd_size))
cc99daad
HPN
2228 as_bad (out_insnp->reloc == BFD_RELOC_CRIS_32_GD
2229 || out_insnp->reloc == BFD_RELOC_CRIS_32_TPREL
2230 || out_insnp->reloc == BFD_RELOC_CRIS_16_TPREL
5a00ea25 2231 || out_insnp->reloc == BFD_RELOC_CRIS_32_IE
cc99daad
HPN
2232 ? _("TLS relocation size does not match operand size")
2233 : _("PIC relocation size does not match operand size"));
3bcbcc3d 2234 }
1048a9ba
HPN
2235 else if (instruction->op == cris_muls_op
2236 || instruction->op == cris_mulu_op)
2237 out_insnp->insn_type = CRIS_INSN_MUL;
3bcbcc3d
HPN
2238 }
2239 break;
2240 }
2241}
2242
3bcbcc3d
HPN
2243/* Get a B, W, or D size modifier from the string pointed out by *cPP,
2244 which must point to a '.' in front of the modifier. On successful
2245 return, *cPP is advanced to the character following the size
2246 modifier, and is undefined otherwise.
2247
2248 cPP Pointer to pointer to string starting
2249 with the size modifier.
2250
2251 size_bitsp Pointer to variable to contain the size bits on
2252 successful return.
2253
2254 Return 1 iff a correct size modifier is found, else 0. */
2255
2256static int
695a4822 2257get_bwd_size_modifier (char **cPP, int *size_bitsp)
3bcbcc3d
HPN
2258{
2259 if (**cPP != '.')
2260 return 0;
2261 else
2262 {
47926f60 2263 /* Consume the '.'. */
3bcbcc3d
HPN
2264 (*cPP)++;
2265
2266 switch (**cPP)
2267 {
2268 case 'B':
2269 case 'b':
2270 *size_bitsp = 0;
2271 break;
2272
2273 case 'W':
2274 case 'w':
2275 *size_bitsp = 1;
2276 break;
2277
2278 case 'D':
2279 case 'd':
2280 *size_bitsp = 2;
2281 break;
2282
2283 default:
2284 return 0;
2285 }
2286
2287 /* Consume the size letter. */
2288 (*cPP)++;
2289 return 1;
2290 }
2291}
2292
3bcbcc3d
HPN
2293/* Get a B or W size modifier from the string pointed out by *cPP,
2294 which must point to a '.' in front of the modifier. On successful
2295 return, *cPP is advanced to the character following the size
2296 modifier, and is undefined otherwise.
2297
2298 cPP Pointer to pointer to string starting
2299 with the size modifier.
2300
2301 size_bitsp Pointer to variable to contain the size bits on
2302 successful return.
2303
2304 Return 1 iff a correct size modifier is found, else 0. */
2305
2306static int
695a4822 2307get_bw_size_modifier (char **cPP, int *size_bitsp)
3bcbcc3d
HPN
2308{
2309 if (**cPP != '.')
2310 return 0;
2311 else
2312 {
47926f60 2313 /* Consume the '.'. */
3bcbcc3d
HPN
2314 (*cPP)++;
2315
2316 switch (**cPP)
2317 {
2318 case 'B':
2319 case 'b':
2320 *size_bitsp = 0;
2321 break;
2322
2323 case 'W':
2324 case 'w':
2325 *size_bitsp = 1;
2326 break;
2327
2328 default:
2329 return 0;
2330 }
2331
2332 /* Consume the size letter. */
2333 (*cPP)++;
2334 return 1;
2335 }
2336}
2337
07e90ad5 2338/* Get a general register from the string pointed out by *cPP. The
3bcbcc3d
HPN
2339 variable *cPP is advanced to the character following the general
2340 register name on a successful return, and has its initial position
2341 otherwise.
2342
2343 cPP Pointer to pointer to string, beginning with a general
2344 register name.
2345
2346 regnop Pointer to int containing the register number.
2347
2348 Return 1 iff a correct general register designator is found,
2349 else 0. */
2350
2351static int
695a4822 2352get_gen_reg (char **cPP, int *regnop)
3bcbcc3d
HPN
2353{
2354 char *oldp;
2355 oldp = *cPP;
2356
7b15d668
HPN
2357 /* Handle a sometimes-mandatory dollar sign as register prefix. */
2358 if (**cPP == REGISTER_PREFIX_CHAR)
2359 (*cPP)++;
2360 else if (demand_register_prefix)
2361 return 0;
2362
3bcbcc3d
HPN
2363 switch (**cPP)
2364 {
2365 case 'P':
2366 case 'p':
2367 /* "P" as in "PC"? Consume the "P". */
2368 (*cPP)++;
2369
2370 if ((**cPP == 'C' || **cPP == 'c')
ae57792d
HPN
2371 && ! ISALNUM ((*cPP)[1])
2372 /* Here's a little twist: For v32 and the compatibility mode,
2373 we only recognize PC as a register number if there's '+]'
2374 after. We don't consume that, but the presence can only be
2375 valid after a register in a post-increment context, which
2376 is also the only valid context for PC as a register for
2377 v32. Not that it's used very often, but saying "MOVE.D
2378 [PC+],R5" should remain valid. It's not supported for
2379 jump-type insns or other insns with no [Rn+] mode, though. */
2380 && ((cris_arch != arch_crisv32
2381 && cris_arch != arch_cris_common_v10_v32)
2382 || ((*cPP)[1] == '+' && (*cPP)[2] == ']')))
3bcbcc3d
HPN
2383 {
2384 /* It's "PC": consume the "c" and we're done. */
2385 (*cPP)++;
2386 *regnop = REG_PC;
2387 return 1;
2388 }
2389 break;
2390
ae57792d
HPN
2391 /* Like with PC, we recognize ACR, but only if it's *not* followed
2392 by '+', and only for v32. */
2393 case 'A':
2394 case 'a':
2395 if (cris_arch != arch_crisv32
2396 || ((*cPP)[1] != 'c' && (*cPP)[1] != 'C')
2397 || ((*cPP)[2] != 'r' && (*cPP)[2] != 'R')
2398 || ISALNUM ((*cPP)[3])
2399 || (*cPP)[3] == '+')
2400 break;
2401 (*cPP) += 3;
2402 *regnop = 15;
2403 return 1;
2404
3bcbcc3d
HPN
2405 case 'R':
2406 case 'r':
47926f60 2407 /* Hopefully r[0-9] or r1[0-5]. Consume 'R' or 'r'. */
3bcbcc3d
HPN
2408 (*cPP)++;
2409
3882b010 2410 if (ISDIGIT (**cPP))
3bcbcc3d
HPN
2411 {
2412 /* It's r[0-9]. Consume and check the next digit. */
2413 *regnop = **cPP - '0';
2414 (*cPP)++;
2415
3882b010 2416 if (! ISALNUM (**cPP))
3bcbcc3d 2417 {
47926f60 2418 /* No more digits, we're done. */
3bcbcc3d
HPN
2419 return 1;
2420 }
2421 else
2422 {
2423 /* One more digit. Consume and add. */
47926f60 2424 *regnop = *regnop * 10 + (**cPP - '0');
3bcbcc3d
HPN
2425
2426 /* We need to check for a valid register number; Rn,
2427 0 <= n <= MAX_REG. */
2428 if (*regnop <= MAX_REG)
2429 {
2430 /* Consume second digit. */
2431 (*cPP)++;
2432 return 1;
2433 }
2434 }
2435 }
2436 break;
2437
2438 case 'S':
2439 case 's':
2440 /* "S" as in "SP"? Consume the "S". */
2441 (*cPP)++;
2442 if (**cPP == 'P' || **cPP == 'p')
2443 {
2444 /* It's "SP": consume the "p" and we're done. */
2445 (*cPP)++;
2446 *regnop = REG_SP;
2447 return 1;
2448 }
2449 break;
2450
2451 default:
2452 /* Just here to silence compilation warnings. */
2453 ;
2454 }
2455
2456 /* We get here if we fail. Restore the pointer. */
2457 *cPP = oldp;
2458 return 0;
2459}
2460
3bcbcc3d
HPN
2461/* Get a special register from the string pointed out by *cPP. The
2462 variable *cPP is advanced to the character following the special
2463 register name if one is found, and retains its original position
2464 otherwise.
2465
2466 cPP Pointer to pointer to string starting with a special register
2467 name.
2468
2469 sregpp Pointer to Pointer to struct spec_reg, where a pointer to the
2470 register description will be stored.
2471
2472 Return 1 iff a correct special register name is found. */
2473
2474static int
695a4822 2475get_spec_reg (char **cPP, const struct cris_spec_reg **sregpp)
3bcbcc3d
HPN
2476{
2477 char *s1;
2478 const char *s2;
7b15d668 2479 char *name_begin = *cPP;
3bcbcc3d
HPN
2480
2481 const struct cris_spec_reg *sregp;
2482
7b15d668
HPN
2483 /* Handle a sometimes-mandatory dollar sign as register prefix. */
2484 if (*name_begin == REGISTER_PREFIX_CHAR)
2485 name_begin++;
2486 else if (demand_register_prefix)
2487 return 0;
2488
3bcbcc3d 2489 /* Loop over all special registers. */
47926f60 2490 for (sregp = cris_spec_regs; sregp->name != NULL; sregp++)
3bcbcc3d 2491 {
3bcbcc3d 2492 /* Start over from beginning of the supposed name. */
7b15d668 2493 s1 = name_begin;
3bcbcc3d
HPN
2494 s2 = sregp->name;
2495
3882b010 2496 while (*s2 != '\0' && TOLOWER (*s1) == *s2)
3bcbcc3d
HPN
2497 {
2498 s1++;
2499 s2++;
2500 }
2501
2502 /* For a match, we must have consumed the name in the table, and we
2503 must be outside what could be part of a name. Assume here that a
47926f60 2504 test for alphanumerics is sufficient for a name test. */
ae57792d
HPN
2505 if (*s2 == 0 && ! ISALNUM (*s1)
2506 && cris_insn_ver_valid_for_arch (sregp->applicable_version,
2507 cris_arch))
3bcbcc3d 2508 {
47926f60 2509 /* We have a match. Update the pointer and be done. */
3bcbcc3d
HPN
2510 *cPP = s1;
2511 *sregpp = sregp;
2512 return 1;
2513 }
2514 }
2515
47926f60 2516 /* If we got here, we did not find any name. */
3bcbcc3d
HPN
2517 return 0;
2518}
2519
ae57792d
HPN
2520/* Get a support register from the string pointed out by *cPP. The
2521 variable *cPP is advanced to the character following the support-
2522 register name if one is found, and retains its original position
2523 otherwise.
2524
2525 cPP Pointer to pointer to string starting with a support-register
2526 name.
2527
2528 sregpp Pointer to int containing the register number.
2529
2530 Return 1 iff a correct support-register name is found. */
2531
2532static int
695a4822 2533get_sup_reg (char **cPP, int *regnop)
ae57792d
HPN
2534{
2535 char *s1;
2536 const char *s2;
2537 char *name_begin = *cPP;
2538
2539 const struct cris_support_reg *sregp;
2540
2541 /* Handle a sometimes-mandatory dollar sign as register prefix. */
2542 if (*name_begin == REGISTER_PREFIX_CHAR)
2543 name_begin++;
2544 else if (demand_register_prefix)
2545 return 0;
2546
2547 /* Loop over all support-registers. */
2548 for (sregp = cris_support_regs; sregp->name != NULL; sregp++)
2549 {
2550 /* Start over from beginning of the supposed name. */
2551 s1 = name_begin;
2552 s2 = sregp->name;
2553
2554 while (*s2 != '\0' && TOLOWER (*s1) == *s2)
2555 {
2556 s1++;
2557 s2++;
2558 }
2559
2560 /* For a match, we must have consumed the name in the table, and we
2561 must be outside what could be part of a name. Assume here that a
2562 test for alphanumerics is sufficient for a name test. */
2563 if (*s2 == 0 && ! ISALNUM (*s1))
2564 {
2565 /* We have a match. Update the pointer and be done. */
2566 *cPP = s1;
2567 *regnop = sregp->number;
2568 return 1;
2569 }
2570 }
2571
2572 /* If we got here, we did not find any name. */
2573 return 0;
2574}
2575
3bcbcc3d
HPN
2576/* Get an unprefixed or side-effect-prefix operand from the string pointed
2577 out by *cPP. The pointer *cPP is advanced to the character following
2578 the indirect operand if we have success, else it contains an undefined
2579 value.
2580
2581 cPP Pointer to pointer to string beginning with the first
2582 character of the supposed operand.
2583
2584 prefixp Pointer to structure containing an optional instruction
2585 prefix.
2586
2587 is_autoincp Pointer to int indicating the indirect or autoincrement
2588 bits.
2589
2590 src_regnop Pointer to int containing the source register number in
2591 the instruction.
2592
2593 imm_foundp Pointer to an int indicating if an immediate expression
2594 is found.
2595
2596 imm_exprP Pointer to a structure containing an immediate
2597 expression, if success and if *imm_foundp is nonzero.
2598
2599 Return 1 iff a correct indirect operand is found. */
2600
2601static int
695a4822
HPN
2602get_autoinc_prefix_or_indir_op (char **cPP, struct cris_prefix *prefixp,
2603 int *is_autoincp, int *src_regnop,
2604 int *imm_foundp, expressionS *imm_exprP)
3bcbcc3d
HPN
2605{
2606 /* Assume there was no immediate mode expression. */
2607 *imm_foundp = 0;
2608
2609 if (**cPP == '[')
2610 {
2611 /* So this operand is one of:
2612 Indirect: [rN]
2613 Autoincrement: [rN+]
2614 Indexed with assign: [rN=rM+rO.S]
2615 Offset with assign: [rN=rM+I], [rN=rM+[rO].s], [rN=rM+[rO+].s]
2616
2617 Either way, consume the '['. */
2618 (*cPP)++;
2619
2620 /* Get the rN register. */
2621 if (! get_gen_reg (cPP, src_regnop))
2622 /* If there was no register, then this cannot match. */
2623 return 0;
2624 else
2625 {
2626 /* We got the register, now check the next character. */
2627 switch (**cPP)
2628 {
2629 case ']':
2630 /* Indirect mode. We're done here. */
2631 prefixp->kind = PREFIX_NONE;
2632 *is_autoincp = 0;
2633 break;
2634
2635 case '+':
2636 /* This must be an auto-increment mode, if there's a
2637 match. */
2638 prefixp->kind = PREFIX_NONE;
2639 *is_autoincp = 1;
2640
2641 /* We consume this character and break out to check the
2642 closing ']'. */
2643 (*cPP)++;
2644 break;
2645
2646 case '=':
2647 /* This must be indexed with assign, or offset with assign
ae57792d
HPN
2648 to match. Not supported for crisv32 or in
2649 compatibility mode. */
2650 if (cris_arch == arch_crisv32
2651 || cris_arch == arch_cris_common_v10_v32)
2652 return 0;
2653
3bcbcc3d
HPN
2654 (*cPP)++;
2655
2656 /* Either way, the next thing must be a register. */
2657 if (! get_gen_reg (cPP, &prefixp->base_reg_number))
2658 /* No register, no match. */
2659 return 0;
2660 else
2661 {
2662 /* We've consumed "[rN=rM", so we must be looking at
2663 "+rO.s]" or "+I]", or "-I]", or "+[rO].s]" or
2664 "+[rO+].s]". */
2665 if (**cPP == '+')
2666 {
2667 int index_reg_number;
2668 (*cPP)++;
2669
2670 if (**cPP == '[')
2671 {
2672 int size_bits;
2673 /* This must be [rx=ry+[rz].s] or
2674 [rx=ry+[rz+].s] or no match. We must be
2675 looking at rz after consuming the '['. */
2676 (*cPP)++;
2677
2678 if (!get_gen_reg (cPP, &index_reg_number))
2679 return 0;
2680
2681 prefixp->kind = PREFIX_BDAP;
2682 prefixp->opcode
2683 = (BDAP_INDIR_OPCODE
2684 + (prefixp->base_reg_number << 12)
2685 + index_reg_number);
2686
2687 if (**cPP == '+')
2688 {
2689 /* We've seen "[rx=ry+[rz+" here, so now we
2690 know that there must be "].s]" left to
2691 check. */
2692 (*cPP)++;
2693 prefixp->opcode |= AUTOINCR_BIT << 8;
2694 }
2695
2696 /* If it wasn't autoincrement, we don't need to
2697 add anything. */
2698
2699 /* Check the next-to-last ']'. */
2700 if (**cPP != ']')
2701 return 0;
2702
2703 (*cPP)++;
2704
2705 /* Check the ".s" modifier. */
2706 if (! get_bwd_size_modifier (cPP, &size_bits))
2707 return 0;
2708
2709 prefixp->opcode |= size_bits << 4;
2710
2711 /* Now we got [rx=ry+[rz+].s or [rx=ry+[rz].s.
2712 We break out to check the final ']'. */
2713 break;
2714 }
ab3e48dc
KH
2715 /* It wasn't an indirection. Check if it's a
2716 register. */
2717 else if (get_gen_reg (cPP, &index_reg_number))
47926f60
KH
2718 {
2719 int size_bits;
2720
2721 /* Indexed with assign mode: "[rN+rM.S]". */
2722 prefixp->kind = PREFIX_BIAP;
2723 prefixp->opcode
2724 = (BIAP_OPCODE + (index_reg_number << 12)
2725 + prefixp->base_reg_number /* << 0 */);
2726
2727 if (! get_bwd_size_modifier (cPP, &size_bits))
2728 /* Size missing, this isn't a match. */
2729 return 0;
2730 else
3bcbcc3d 2731 {
47926f60 2732 /* Size found, break out to check the
3bcbcc3d 2733 final ']'. */
47926f60 2734 prefixp->opcode |= size_bits << 4;
3bcbcc3d
HPN
2735 break;
2736 }
47926f60
KH
2737 }
2738 /* Not a register. Then this must be "[rN+I]". */
2739 else if (cris_get_expression (cPP, &prefixp->expr))
2740 {
2741 /* We've got offset with assign mode. Fill
2742 in the blanks and break out to match the
2743 final ']'. */
2744 prefixp->kind = PREFIX_BDAP_IMM;
08caf3f8
HPN
2745
2746 /* We tentatively put an opcode corresponding to
2747 a 32-bit operand here, although it may be
cc99daad
HPN
2748 relaxed when there's no relocation
2749 specifier for the operand. */
08caf3f8
HPN
2750 prefixp->opcode
2751 = (BDAP_INDIR_OPCODE
2752 | (prefixp->base_reg_number << 12)
2753 | (AUTOINCR_BIT << 8)
2754 | (2 << 4)
2755 | REG_PC /* << 0 */);
2756
2757 /* This can have a PIC suffix, specifying reloc
2758 type to use. */
cc99daad 2759 if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR)
08caf3f8
HPN
2760 {
2761 unsigned int relocsize;
2762
cc99daad
HPN
2763 cris_get_reloc_suffix (cPP, &prefixp->reloc,
2764 &prefixp->expr);
08caf3f8
HPN
2765
2766 /* Tweak the size of the immediate operand
2767 in the prefix opcode if it isn't what we
2768 set. */
2769 relocsize
cc99daad 2770 = cris_get_specified_reloc_size (prefixp->reloc);
08caf3f8
HPN
2771 if (relocsize != 4)
2772 prefixp->opcode
2773 = ((prefixp->opcode & ~(3 << 4))
2774 | ((relocsize >> 1) << 4));
2775 }
47926f60
KH
2776 break;
2777 }
2778 else
2779 /* Neither register nor expression found, so
2780 this can't be a match. */
2781 return 0;
3bcbcc3d 2782 }
47926f60 2783 /* Not "[rN+" but perhaps "[rN-"? */
ab3e48dc 2784 else if (**cPP == '-')
47926f60
KH
2785 {
2786 /* We must have an offset with assign mode. */
2787 if (! cris_get_expression (cPP, &prefixp->expr))
2788 /* No expression, no match. */
2789 return 0;
2790 else
2791 {
2792 /* We've got offset with assign mode. Fill
2793 in the blanks and break out to match the
08caf3f8
HPN
2794 final ']'.
2795
cc99daad
HPN
2796 Note that we don't allow a relocation
2797 suffix for an operand with a minus
2798 sign. */
47926f60
KH
2799 prefixp->kind = PREFIX_BDAP_IMM;
2800 break;
2801 }
2802 }
2803 else
2804 /* Neither '+' nor '-' after "[rN=rM". Lose. */
2805 return 0;
3bcbcc3d
HPN
2806 }
2807 default:
2808 /* Neither ']' nor '+' nor '=' after "[rN". Lose. */
2809 return 0;
2810 }
2811 }
2812
2813 /* When we get here, we have a match and will just check the closing
2814 ']'. We can still fail though. */
2815 if (**cPP != ']')
2816 return 0;
2817 else
2818 {
2819 /* Don't forget to consume the final ']'.
2820 Then return in glory. */
2821 (*cPP)++;
2822 return 1;
2823 }
2824 }
47926f60 2825 /* No indirection. Perhaps a constant? */
ab3e48dc 2826 else if (cris_get_expression (cPP, imm_exprP))
47926f60
KH
2827 {
2828 /* Expression found, this is immediate mode. */
2829 prefixp->kind = PREFIX_NONE;
2830 *is_autoincp = 1;
2831 *src_regnop = REG_PC;
2832 *imm_foundp = 1;
08caf3f8
HPN
2833
2834 /* This can have a PIC suffix, specifying reloc type to use. The
2835 caller must check that the reloc size matches the operand size. */
cc99daad
HPN
2836 if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR)
2837 cris_get_reloc_suffix (cPP, &prefixp->reloc, imm_exprP);
08caf3f8 2838
47926f60
KH
2839 return 1;
2840 }
3bcbcc3d
HPN
2841
2842 /* No luck today. */
2843 return 0;
2844}
2845
3bcbcc3d
HPN
2846/* This function gets an indirect operand in a three-address operand
2847 combination from the string pointed out by *cPP. The pointer *cPP is
2848 advanced to the character following the indirect operand on success, or
2849 has an unspecified value on failure.
2850
2d2255b5 2851 cPP Pointer to pointer to string beginning
3bcbcc3d
HPN
2852 with the operand
2853
2854 prefixp Pointer to structure containing an
2855 instruction prefix
2856
2857 Returns 1 iff a correct indirect operand is found. */
2858
2859static int
695a4822 2860get_3op_or_dip_prefix_op (char **cPP, struct cris_prefix *prefixp)
3bcbcc3d 2861{
ab3e48dc
KH
2862 int reg_number;
2863
3bcbcc3d
HPN
2864 if (**cPP != '[')
2865 /* We must have a '[' or it's a clean failure. */
2866 return 0;
3bcbcc3d 2867
47926f60
KH
2868 /* Eat the first '['. */
2869 (*cPP)++;
2870
2871 if (**cPP == '[')
2872 {
2873 /* A second '[', so this must be double-indirect mode. */
3bcbcc3d 2874 (*cPP)++;
47926f60
KH
2875 prefixp->kind = PREFIX_DIP;
2876 prefixp->opcode = DIP_OPCODE;
3bcbcc3d 2877
47926f60
KH
2878 /* Get the register or fail entirely. */
2879 if (! get_gen_reg (cPP, &reg_number))
2880 return 0;
2881 else
3bcbcc3d 2882 {
47926f60
KH
2883 prefixp->opcode |= reg_number /* << 0 */ ;
2884 if (**cPP == '+')
2885 {
2886 /* Since we found a '+', this must be double-indirect
2887 autoincrement mode. */
2888 (*cPP)++;
2889 prefixp->opcode |= AUTOINCR_BIT << 8;
2890 }
2891
2892 /* There's nothing particular to do, if this was a
2893 double-indirect *without* autoincrement. */
2894 }
2895
2896 /* Check the first ']'. The second one is checked at the end. */
2897 if (**cPP != ']')
2898 return 0;
2899
2900 /* Eat the first ']', so we'll be looking at a second ']'. */
2901 (*cPP)++;
2902 }
2903 /* No second '['. Then we should have a register here, making
2904 it "[rN". */
2905 else if (get_gen_reg (cPP, &prefixp->base_reg_number))
2906 {
2907 /* This must be indexed or offset mode: "[rN+I]" or
2908 "[rN+rM.S]" or "[rN+[rM].S]" or "[rN+[rM+].S]". */
2909 if (**cPP == '+')
2910 {
47926f60
KH
2911 int index_reg_number;
2912
3bcbcc3d 2913 (*cPP)++;
3bcbcc3d 2914
47926f60 2915 if (**cPP == '[')
3bcbcc3d 2916 {
47926f60
KH
2917 /* This is "[rx+["... Expect a register next. */
2918 int size_bits;
2919 (*cPP)++;
2920
2921 if (!get_gen_reg (cPP, &index_reg_number))
2922 return 0;
2923
2924 prefixp->kind = PREFIX_BDAP;
2925 prefixp->opcode
2926 = (BDAP_INDIR_OPCODE
2927 + (prefixp->base_reg_number << 12)
2928 + index_reg_number);
2929
2930 /* We've seen "[rx+[ry", so check if this is
2931 autoincrement. */
3bcbcc3d
HPN
2932 if (**cPP == '+')
2933 {
47926f60 2934 /* Yep, now at "[rx+[ry+". */
3bcbcc3d
HPN
2935 (*cPP)++;
2936 prefixp->opcode |= AUTOINCR_BIT << 8;
2937 }
47926f60
KH
2938 /* If it wasn't autoincrement, we don't need to
2939 add anything. */
3bcbcc3d 2940
47926f60
KH
2941 /* Check a first closing ']': "[rx+[ry]" or
2942 "[rx+[ry+]". */
2943 if (**cPP != ']')
2944 return 0;
2945 (*cPP)++;
3bcbcc3d 2946
47926f60
KH
2947 /* Now expect a size modifier ".S". */
2948 if (! get_bwd_size_modifier (cPP, &size_bits))
2949 return 0;
3bcbcc3d 2950
47926f60
KH
2951 prefixp->opcode |= size_bits << 4;
2952
2953 /* Ok, all interesting stuff has been seen:
2954 "[rx+[ry+].S" or "[rx+[ry].S". We only need to
2955 expect a final ']', which we'll do in a common
2956 closing session. */
2957 }
2958 /* Seen "[rN+", but not a '[', so check if we have a
2959 register. */
2960 else if (get_gen_reg (cPP, &index_reg_number))
2961 {
2962 /* This is indexed mode: "[rN+rM.S]" or
2963 "[rN+rM.S+]". */
2964 int size_bits;
2965 prefixp->kind = PREFIX_BIAP;
2966 prefixp->opcode
2967 = (BIAP_OPCODE
2968 | prefixp->base_reg_number /* << 0 */
2969 | (index_reg_number << 12));
2970
07e90ad5 2971 /* Consume the ".S". */
47926f60
KH
2972 if (! get_bwd_size_modifier (cPP, &size_bits))
2973 /* Missing size, so fail. */
2974 return 0;
3bcbcc3d 2975 else
47926f60
KH
2976 /* Size found. Add that piece and drop down to
2977 the common checking of the closing ']'. */
2978 prefixp->opcode |= size_bits << 4;
2979 }
2980 /* Seen "[rN+", but not a '[' or a register, so then
ae57792d
HPN
2981 it must be a constant "I".
2982
2983 As a quality of implementation improvement, we check for a
2984 closing ']', like in an erroneous "[rN+]". If we don't,
2985 the expression parser will emit a confusing "bad
2986 expression" when it sees the ']', probably because it
2987 doesn't like seeing no expression. */
2988 else if (**cPP != ']' && cris_get_expression (cPP, &prefixp->expr))
47926f60
KH
2989 {
2990 /* Expression found, so fill in the bits of offset
2991 mode and drop down to check the closing ']'. */
2992 prefixp->kind = PREFIX_BDAP_IMM;
08caf3f8
HPN
2993
2994 /* We tentatively put an opcode corresponding to a 32-bit
2995 operand here, although it may be relaxed when there's no
2996 PIC specifier for the operand. */
2997 prefixp->opcode
2998 = (BDAP_INDIR_OPCODE
2999 | (prefixp->base_reg_number << 12)
3000 | (AUTOINCR_BIT << 8)
3001 | (2 << 4)
3002 | REG_PC /* << 0 */);
3003
3004 /* This can have a PIC suffix, specifying reloc type to use. */
cc99daad 3005 if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR)
08caf3f8
HPN
3006 {
3007 unsigned int relocsize;
3008
cc99daad 3009 cris_get_reloc_suffix (cPP, &prefixp->reloc, &prefixp->expr);
08caf3f8
HPN
3010
3011 /* Tweak the size of the immediate operand in the prefix
3012 opcode if it isn't what we set. */
cc99daad 3013 relocsize = cris_get_specified_reloc_size (prefixp->reloc);
08caf3f8
HPN
3014 if (relocsize != 4)
3015 prefixp->opcode
3016 = ((prefixp->opcode & ~(3 << 4))
3017 | ((relocsize >> 1) << 4));
3018 }
47926f60
KH
3019 }
3020 else
3021 /* Nothing valid here: lose. */
3022 return 0;
3023 }
3024 /* Seen "[rN" but no '+', so check if it's a '-'. */
3025 else if (**cPP == '-')
3026 {
3027 /* Yep, we must have offset mode. */
3028 if (! cris_get_expression (cPP, &prefixp->expr))
3029 /* No expression, so we lose. */
3030 return 0;
3031 else
3032 {
3033 /* Expression found to make this offset mode, so
3034 fill those bits and drop down to check the
08caf3f8
HPN
3035 closing ']'.
3036
3037 Note that we don't allow a PIC suffix for
3038 an operand with a minus sign like this. */
47926f60
KH
3039 prefixp->kind = PREFIX_BDAP_IMM;
3040 }
3041 }
3042 else
3043 {
3044 /* We've seen "[rN", but not '+' or '-'; rather a ']'.
3045 Hmm. Normally this is a simple indirect mode that we
3046 shouldn't match, but if we expect ']', then we have a
3047 zero offset, so it can be a three-address-operand,
3048 like "[rN],rO,rP", thus offset mode.
3049
3050 Don't eat the ']', that will be done in the closing
3051 ceremony. */
3052 prefixp->expr.X_op = O_constant;
3053 prefixp->expr.X_add_number = 0;
3054 prefixp->expr.X_add_symbol = NULL;
3055 prefixp->expr.X_op_symbol = NULL;
3056 prefixp->kind = PREFIX_BDAP_IMM;
3057 }
3058 }
3059 /* A '[', but no second '[', and no register. Check if we
3060 have an expression, making this "[I]" for a double-indirect
3061 prefix. */
3062 else if (cris_get_expression (cPP, &prefixp->expr))
3063 {
3064 /* Expression found, the so called absolute mode for a
3065 double-indirect prefix on PC. */
3066 prefixp->kind = PREFIX_DIP;
3067 prefixp->opcode = DIP_OPCODE | (AUTOINCR_BIT << 8) | REG_PC;
3068 prefixp->reloc = BFD_RELOC_32;
5a00ea25
HPN
3069
3070 /* For :GD and :IE, it makes sense to have TLS specifiers here. */
3071 if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR)
3072 cris_get_reloc_suffix (cPP, &prefixp->reloc, &prefixp->expr);
47926f60
KH
3073 }
3074 else
3075 /* Neither '[' nor register nor expression. We lose. */
3076 return 0;
3bcbcc3d
HPN
3077
3078 /* We get here as a closing ceremony to a successful match. We just
3079 need to check the closing ']'. */
3080 if (**cPP != ']')
3081 /* Oops. Close but no air-polluter. */
3082 return 0;
3083
3084 /* Don't forget to consume that ']', before returning in glory. */
3085 (*cPP)++;
3086 return 1;
3087}
3088
3bcbcc3d
HPN
3089/* Get an expression from the string pointed out by *cPP.
3090 The pointer *cPP is advanced to the character following the expression
3091 on a success, or retains its original value otherwise.
3092
3093 cPP Pointer to pointer to string beginning with the expression.
3094
3095 exprP Pointer to structure containing the expression.
3096
47926f60 3097 Return 1 iff a correct expression is found. */
3bcbcc3d
HPN
3098
3099static int
695a4822 3100cris_get_expression (char **cPP, expressionS *exprP)
3bcbcc3d
HPN
3101{
3102 char *saved_input_line_pointer;
3bcbcc3d
HPN
3103
3104 /* The "expression" function expects to find an expression at the
3105 global variable input_line_pointer, so we have to save it to give
3106 the impression that we don't fiddle with global variables. */
3107 saved_input_line_pointer = input_line_pointer;
3108 input_line_pointer = *cPP;
3109
ae57792d
HPN
3110 /* Avoid a common error, confusing addressing modes. Beware that the
3111 call to expression below does not signal that error; it treats []
3112 as parentheses, unless #define NEED_INDEX_OPERATOR in which case it
3113 gives them other confusing semantics rather than plain outlawing
3114 them, which is what we want. */
3115 if (*input_line_pointer == '[')
3116 {
3117 input_line_pointer = saved_input_line_pointer;
3118 return 0;
3119 }
3120
87975d2a 3121 expression (exprP);
3bcbcc3d
HPN
3122 if (exprP->X_op == O_illegal || exprP->X_op == O_absent)
3123 {
3124 input_line_pointer = saved_input_line_pointer;
3125 return 0;
3126 }
3127
3128 /* Everything seems to be fine, just restore the global
3129 input_line_pointer and say we're successful. */
3130 *cPP = input_line_pointer;
3131 input_line_pointer = saved_input_line_pointer;
3132 return 1;
3133}
3134
3bcbcc3d
HPN
3135/* Get a sequence of flag characters from *spp. The pointer *cPP is
3136 advanced to the character following the expression. The flag
3137 characters are consecutive, no commas or spaces.
3138
3139 cPP Pointer to pointer to string beginning with the expression.
3140
3141 flagp Pointer to int to return the flags expression.
3142
3143 Return 1 iff a correct flags expression is found. */
3144
3145static int
695a4822 3146get_flags (char **cPP, int *flagsp)
3bcbcc3d
HPN
3147{
3148 for (;;)
3149 {
3150 switch (**cPP)
3151 {
3152 case 'd':
3153 case 'D':
ae57792d
HPN
3154 if (! cris_insn_ver_valid_for_arch (cris_ver_v0_3,
3155 cris_arch))
3156 return 0;
3157 *flagsp |= 0x80;
3158 break;
3159
3bcbcc3d
HPN
3160 case 'm':
3161 case 'M':
ae57792d
HPN
3162 if (! cris_insn_ver_valid_for_arch (cris_ver_v8_10,
3163 cris_arch))
3164 return 0;
3bcbcc3d
HPN
3165 *flagsp |= 0x80;
3166 break;
3167
3168 case 'e':
3169 case 'E':
ae57792d
HPN
3170 if (! cris_insn_ver_valid_for_arch (cris_ver_v0_3,
3171 cris_arch))
3172 return 0;
3173 *flagsp |= 0x40;
3174 break;
3175
3bcbcc3d
HPN
3176 case 'b':
3177 case 'B':
ae57792d
HPN
3178 if (! cris_insn_ver_valid_for_arch (cris_ver_v8_10,
3179 cris_arch))
3180 return 0;
3181 *flagsp |= 0x40;
3182 break;
3183
3184 case 'p':
3185 case 'P':
3186 if (! cris_insn_ver_valid_for_arch (cris_ver_v32p,
3187 cris_arch))
3188 return 0;
3189 *flagsp |= 0x80;
3190 break;
3191
3192 case 'u':
3193 case 'U':
3194 if (! cris_insn_ver_valid_for_arch (cris_ver_v32p,
3195 cris_arch))
3196 return 0;
3bcbcc3d
HPN
3197 *flagsp |= 0x40;
3198 break;
3199
3200 case 'i':
3201 case 'I':
3202 *flagsp |= 0x20;
3203 break;
3204
3205 case 'x':
3206 case 'X':
3207 *flagsp |= 0x10;
3208 break;
3209
3210 case 'n':
3211 case 'N':
3212 *flagsp |= 0x8;
3213 break;
3214
3215 case 'z':
3216 case 'Z':
3217 *flagsp |= 0x4;
3218 break;
3219
3220 case 'v':
3221 case 'V':
3222 *flagsp |= 0x2;
3223 break;
3224
3225 case 'c':
3226 case 'C':
3227 *flagsp |= 1;
3228 break;
3229
3230 default:
3231 /* We consider this successful if we stop at a comma or
47926f60 3232 whitespace. Anything else, and we consider it a failure. */
3bcbcc3d
HPN
3233 if (**cPP != ','
3234 && **cPP != 0
3882b010 3235 && ! ISSPACE (**cPP))
3bcbcc3d
HPN
3236 return 0;
3237 else
3238 return 1;
3239 }
3240
3241 /* Don't forget to consume each flag character. */
3242 (*cPP)++;
3243 }
3244}
3245
3bcbcc3d 3246/* Generate code and fixes for a BDAP prefix.
ae57792d
HPN
3247 For v32, this handles ADDOQ because thankfully the opcodes are the
3248 same.
3bcbcc3d
HPN
3249
3250 base_regno Int containing the base register number.
3251
3252 exprP Pointer to structure containing the offset expression. */
3253
3254static void
695a4822 3255gen_bdap (int base_regno, expressionS *exprP)
3bcbcc3d
HPN
3256{
3257 unsigned int opcode;
3258 char *opcodep;
3259
3260 /* Put out the prefix opcode; assume quick immediate mode at first. */
3261 opcode = BDAP_QUICK_OPCODE | (base_regno << 12);
ed67db7a 3262 opcodep = cris_insn_first_word_frag ();
3bcbcc3d
HPN
3263 md_number_to_chars (opcodep, opcode, 2);
3264
3265 if (exprP->X_op == O_constant)
3266 {
3267 /* We have an absolute expression that we know the size of right
47926f60 3268 now. */
3bcbcc3d
HPN
3269 long int value;
3270 int size;
3271
3272 value = exprP->X_add_number;
3273 if (value < -32768 || value > 32767)
3274 /* Outside range for a "word", make it a dword. */
3275 size = 2;
3276 else
47926f60 3277 /* Assume "word" size. */
3bcbcc3d
HPN
3278 size = 1;
3279
3280 /* If this is a signed-byte value, we can fit it into the prefix
3281 insn itself. */
3282 if (value >= -128 && value <= 127)
3283 opcodep[0] = value;
3284 else
3285 {
3286 /* This is a word or dword displacement, which will be put in a
3287 word or dword after the prefix. */
3288 char *p;
3289
3290 opcodep[0] = BDAP_PC_LOW + (size << 4);
3291 opcodep[1] &= 0xF0;
3292 opcodep[1] |= BDAP_INCR_HIGH;
3293 p = frag_more (1 << size);
3294 md_number_to_chars (p, value, 1 << size);
3295 }
3296 }
3297 else
08caf3f8
HPN
3298 {
3299 /* Handle complex expressions. */
3300 valueT addvalue
1c971160 3301 = SIMPLE_EXPR (exprP) ? exprP->X_add_number : 0;
08caf3f8 3302 symbolS *sym
1c971160
HPN
3303 = (SIMPLE_EXPR (exprP)
3304 ? exprP->X_add_symbol : make_expr_symbol (exprP));
08caf3f8
HPN
3305
3306 /* The expression is not defined yet but may become absolute. We
3307 make it a relocation to be relaxed. */
3308 frag_var (rs_machine_dependent, 4, 0,
3309 ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF),
3310 sym, addvalue, opcodep);
3311 }
3bcbcc3d
HPN
3312}
3313
3bcbcc3d
HPN
3314/* Encode a branch displacement in the range -256..254 into the form used
3315 by CRIS conditional branch instructions.
3316
3317 offset The displacement value in bytes. */
3318
3319static int
695a4822 3320branch_disp (int offset)
3bcbcc3d
HPN
3321{
3322 int disp;
3323
ae57792d
HPN
3324 /* Adjust all short branch offsets here. */
3325 if (cris_arch == arch_crisv32 || cris_arch == arch_cris_common_v10_v32)
3326 offset += 2;
3327
3bcbcc3d
HPN
3328 disp = offset & 0xFE;
3329
3330 if (offset < 0)
3331 disp |= 1;
3332
3333 return disp;
3334}
3335
3bcbcc3d
HPN
3336/* Generate code and fixes for a 32-bit conditional branch instruction
3337 created by "extending" an existing 8-bit branch instruction.
3338
3339 opcodep Pointer to the word containing the original 8-bit branch
3340 instruction.
3341
3342 writep Pointer to "extension area" following the first instruction
3343 word.
3344
3345 fragP Pointer to the frag containing the instruction.
3346
3347 add_symP, Parts of the destination address expression.
3348 sub_symP,
3349 add_num. */
3350
3351static void
695a4822
HPN
3352gen_cond_branch_32 (char *opcodep, char *writep, fragS *fragP,
3353 symbolS *add_symP, symbolS *sub_symP, long int add_num)
3bcbcc3d 3354{
ae57792d
HPN
3355 int nop_opcode;
3356 int opc_offset;
3357 int branch_offset;
3358
3359 if (cris_arch == arch_crisv32)
3360 {
3361 nop_opcode = NOP_OPCODE_V32;
3362 opc_offset = 10;
3363 branch_offset = -2 - 8;
3364 }
d2aa3f9f
HPN
3365 else if (pic)
3366 {
3367 nop_opcode = NOP_OPCODE;
3368 opc_offset = 10;
3369 branch_offset = -2 - 8;
3370 }
ae57792d
HPN
3371 else
3372 {
3373 nop_opcode = NOP_OPCODE;
3374 opc_offset = 8;
3375 branch_offset = -2 - 6;
3376 }
3377
3378 /* We should never get here for compatibility mode. */
3379 if (cris_arch == arch_cris_common_v10_v32)
3380 as_fatal (_("Calling gen_cond_branch_32 for .arch common_v10_v32\n"));
3381
3bcbcc3d 3382 if (warn_for_branch_expansion)
08caf3f8
HPN
3383 as_warn_where (fragP->fr_file, fragP->fr_line,
3384 _("32-bit conditional branch generated"));
3bcbcc3d
HPN
3385
3386 /* Here, writep points to what will be opcodep + 2. First, we change
3387 the actual branch in opcodep[0] and opcodep[1], so that in the
3388 final insn, it will look like:
3389 opcodep+10: Bcc .-6
3390
3391 This means we don't have to worry about changing the opcode or
08caf3f8 3392 messing with the delay-slot instruction. So, we move it to last in
3bcbcc3d
HPN
3393 the "extended" branch, and just change the displacement. Admittedly,
3394 it's not the optimal extended construct, but we should get this
3395 rarely enough that it shouldn't matter. */
3396
ae57792d
HPN
3397 writep[opc_offset] = branch_disp (branch_offset);
3398 writep[opc_offset + 1] = opcodep[1];
3bcbcc3d
HPN
3399
3400 /* Then, we change the branch to an unconditional branch over the
3401 extended part, to the new location of the Bcc:
3402 opcodep: BA .+10
3403 opcodep+2: NOP
3404
3405 Note that these two writes are to currently different locations,
3406 merged later. */
3407
ae57792d 3408 md_number_to_chars (opcodep, BA_QUICK_OPCODE
d2aa3f9f
HPN
3409 + (cris_arch == arch_crisv32 ? 12 : (pic ? 10 : 8)),
3410 2);
ae57792d 3411 md_number_to_chars (writep, nop_opcode, 2);
3bcbcc3d
HPN
3412
3413 /* Then the extended thing, the 32-bit jump insn.
08caf3f8
HPN
3414 opcodep+4: JUMP [PC+]
3415 or, in the PIC case,
d2aa3f9f 3416 opcodep+4: MOVE [PC=PC+N],P0. */
3bcbcc3d 3417
08caf3f8 3418 md_number_to_chars (writep + 2,
ae57792d
HPN
3419 cris_arch == arch_crisv32
3420 ? BA_DWORD_OPCODE
d2aa3f9f
HPN
3421 : (pic ? MOVE_PC_INCR_OPCODE_PREFIX
3422 : JUMP_PC_INCR_OPCODE), 2);
3bcbcc3d
HPN
3423
3424 /* We have to fill in the actual value too.
3425 opcodep+6: .DWORD
3426 This is most probably an expression, but we can cope with an absolute
08caf3f8 3427 value too. FIXME: Testcase needed with and without pic. */
3bcbcc3d
HPN
3428
3429 if (add_symP == NULL && sub_symP == NULL)
08caf3f8
HPN
3430 {
3431 /* An absolute address. */
ae57792d 3432 if (pic || cris_arch == arch_crisv32)
08caf3f8
HPN
3433 fix_new (fragP, writep + 4 - fragP->fr_literal, 4,
3434 section_symbol (absolute_section),
ae57792d
HPN
3435 add_num
3436 + (cris_arch == arch_crisv32 ? 6 : 0),
3437 1, BFD_RELOC_32_PCREL);
08caf3f8
HPN
3438 else
3439 md_number_to_chars (writep + 4, add_num, 4);
3440 }
3bcbcc3d
HPN
3441 else
3442 {
08caf3f8
HPN
3443 if (sub_symP != NULL)
3444 as_bad_where (fragP->fr_file, fragP->fr_line,
3445 _("Complex expression not supported"));
3bcbcc3d 3446
08caf3f8 3447 /* Not absolute, we have to make it a frag for later evaluation. */
3bcbcc3d 3448 fix_new (fragP, writep + 4 - fragP->fr_literal, 4, add_symP,
ae57792d
HPN
3449 add_num + (cris_arch == arch_crisv32 ? 6 : 0),
3450 pic || cris_arch == arch_crisv32 ? 1 : 0,
3451 pic || cris_arch == arch_crisv32
3452 ? BFD_RELOC_32_PCREL : BFD_RELOC_32);
3bcbcc3d 3453 }
ae57792d
HPN
3454
3455 if (cris_arch == arch_crisv32)
3456 /* Follow it with a "NOP" for CRISv32. */
3457 md_number_to_chars (writep + 8, NOP_OPCODE_V32, 2);
d2aa3f9f
HPN
3458 else if (pic)
3459 /* ...and the rest of the move-opcode for pre-v32 PIC. */
3460 md_number_to_chars (writep + 8, MOVE_PC_INCR_OPCODE_SUFFIX, 2);
3bcbcc3d
HPN
3461}
3462
cc99daad
HPN
3463/* Get the size of an immediate-reloc in bytes. Only valid for
3464 specified relocs (TLS, PIC). */
08caf3f8
HPN
3465
3466static unsigned int
cc99daad 3467cris_get_specified_reloc_size (bfd_reloc_code_real_type reloc)
08caf3f8 3468{
cc99daad
HPN
3469 return
3470 reloc == BFD_RELOC_CRIS_16_GOTPLT
3471 || reloc == BFD_RELOC_CRIS_16_GOT
3472 || reloc == BFD_RELOC_CRIS_16_GOT_GD
3473 || reloc == BFD_RELOC_CRIS_16_DTPREL
3474 || reloc == BFD_RELOC_CRIS_16_GOT_TPREL
3475 || reloc == BFD_RELOC_CRIS_16_TPREL
08caf3f8
HPN
3476 ? 2 : 4;
3477}
3478
3479/* Store a reloc type at *RELOCP corresponding to the PIC suffix at *CPP.
3480 Adjust *EXPRP with any addend found after the PIC suffix. */
3481
3482static void
cc99daad
HPN
3483cris_get_reloc_suffix (char **cPP, bfd_reloc_code_real_type *relocp,
3484 expressionS *exprP)
08caf3f8
HPN
3485{
3486 char *s = *cPP;
3487 unsigned int i;
3488 expressionS const_expr;
3489
3490 const struct pic_suffixes_struct
3491 {
3492 const char *const suffix;
3493 unsigned int len;
3494 bfd_reloc_code_real_type reloc;
cc99daad
HPN
3495 bfd_boolean pic_p;
3496 bfd_boolean tls_p;
08caf3f8
HPN
3497 } pic_suffixes[] =
3498 {
3499#undef PICMAP
cc99daad
HPN
3500#define PICMAP(s, r) {s, sizeof (s) - 1, r, TRUE, FALSE}
3501#define PICTLSMAP(s, r) {s, sizeof (s) - 1, r, TRUE, TRUE}
3502#define TLSMAP(s, r) {s, sizeof (s) - 1, r, FALSE, TRUE}
08caf3f8
HPN
3503 /* Keep this in order with longest unambiguous prefix first. */
3504 PICMAP ("GOTPLT16", BFD_RELOC_CRIS_16_GOTPLT),
3505 PICMAP ("GOTPLT", BFD_RELOC_CRIS_32_GOTPLT),
3506 PICMAP ("PLTG", BFD_RELOC_CRIS_32_PLT_GOTREL),
3507 PICMAP ("PLT", BFD_RELOC_CRIS_32_PLT_PCREL),
3508 PICMAP ("GOTOFF", BFD_RELOC_CRIS_32_GOTREL),
3509 PICMAP ("GOT16", BFD_RELOC_CRIS_16_GOT),
cc99daad
HPN
3510 PICMAP ("GOT", BFD_RELOC_CRIS_32_GOT),
3511 PICTLSMAP ("GDGOTREL16", BFD_RELOC_CRIS_16_GOT_GD),
3512 PICTLSMAP ("GDGOTREL", BFD_RELOC_CRIS_32_GOT_GD),
3513 TLSMAP ("GD", BFD_RELOC_CRIS_32_GD),
3514 PICTLSMAP ("DTPREL16", BFD_RELOC_CRIS_16_DTPREL),
3515 PICTLSMAP ("DTPREL", BFD_RELOC_CRIS_32_DTPREL),
5a00ea25 3516 TLSMAP ("IE", BFD_RELOC_CRIS_32_IE),
cc99daad
HPN
3517 PICTLSMAP ("TPOFFGOT16", BFD_RELOC_CRIS_16_GOT_TPREL),
3518 PICTLSMAP ("TPOFFGOT", BFD_RELOC_CRIS_32_GOT_TPREL),
3519 TLSMAP ("TPOFF16", BFD_RELOC_CRIS_16_TPREL),
3520 TLSMAP ("TPOFF", BFD_RELOC_CRIS_32_TPREL)
08caf3f8
HPN
3521 };
3522
3523 /* We've already seen the ':', so consume it. */
3524 s++;
3525
3526 for (i = 0; i < sizeof (pic_suffixes)/sizeof (pic_suffixes[0]); i++)
3527 {
3528 if (strncmp (s, pic_suffixes[i].suffix, pic_suffixes[i].len) == 0
cc99daad
HPN
3529 && ! is_part_of_name (s[pic_suffixes[i].len])
3530 /* PIC and non-PIC relocations are exclusive. */
3531 && (pic != 0) == (pic_suffixes[i].pic_p != 0)
3532 /* But TLS can be active for non-TLS relocations too. */
3533 && (pic_suffixes[i].tls_p == 0 || tls))
08caf3f8
HPN
3534 {
3535 /* We have a match. Consume the suffix and set the relocation
3536 type. */
3537 s += pic_suffixes[i].len;
3538
3539 /* There can be a constant term appended. If so, we will add it
3540 to *EXPRP. */
3541 if (*s == '+' || *s == '-')
3542 {
3543 if (! cris_get_expression (&s, &const_expr))
3544 /* There was some kind of syntax error. Bail out. */
3545 break;
3546
3547 /* Allow complex expressions as the constant part. It still
b6ff326e 3548 has to be an assembly-time constant or there will be an
08caf3f8 3549 error emitting the reloc. This makes the PIC qualifiers
d551a338 3550 idempotent; foo:GOTOFF+32 == foo+32:GOTOFF. The former we
08caf3f8
HPN
3551 recognize here; the latter is parsed in the incoming
3552 expression. */
3553 exprP->X_add_symbol = make_expr_symbol (exprP);
3554 exprP->X_op = O_add;
3555 exprP->X_add_number = 0;
3556 exprP->X_op_symbol = make_expr_symbol (&const_expr);
3557 }
3558
3559 *relocp = pic_suffixes[i].reloc;
3560 *cPP = s;
3561 return;
3562 }
3563 }
3564
3565 /* No match. Don't consume anything; fall back and there will be a
3566 syntax error. */
3567}
3568
ae57792d 3569/* This *could* have been:
3bcbcc3d 3570
47926f60
KH
3571 Turn a string in input_line_pointer into a floating point constant
3572 of type TYPE, and store the appropriate bytes in *LITP. The number
3573 of LITTLENUMS emitted is stored in *SIZEP.
3bcbcc3d
HPN
3574
3575 type A character from FLTCHARS that describes what kind of
3576 floating-point number is wanted.
3577
3578 litp A pointer to an array that the result should be stored in.
3579
3580 sizep A pointer to an integer where the size of the result is stored.
3581
3582 But we don't support floating point constants in assembly code *at all*,
3583 since it's suboptimal and just opens up bug opportunities. GCC emits
3584 the bit patterns as hex. All we could do here is to emit what GCC
3585 would have done in the first place. *Nobody* writes floating-point
3586 code as assembly code, but if they do, they should be able enough to
3587 find out the correct bit patterns and use them. */
3588
6d4af3c2 3589const char *
695a4822
HPN
3590md_atof (int type ATTRIBUTE_UNUSED, char *litp ATTRIBUTE_UNUSED,
3591 int *sizep ATTRIBUTE_UNUSED)
3bcbcc3d
HPN
3592{
3593 /* FIXME: Is this function mentioned in the internals.texi manual? If
3594 not, add it. */
3595 return _("Bad call to md_atof () - floating point formats are not supported");
3596}
3597
3bcbcc3d
HPN
3598/* Turn a number as a fixS * into a series of bytes that represents the
3599 number on the target machine. The purpose of this procedure is the
3600 same as that of md_number_to_chars but this procedure is supposed to
3601 handle general bit field fixes and machine-dependent fixups.
3602
3603 bufp Pointer to an array where the result should be stored.
3604
3605 val The value to store.
3606
3607 n The number of bytes in "val" that should be stored.
3608
08caf3f8
HPN
3609 fixP The fix to be applied to the bit field starting at bufp.
3610
3611 seg The segment containing this number. */
3bcbcc3d
HPN
3612
3613static void
695a4822 3614cris_number_to_imm (char *bufp, long val, int n, fixS *fixP, segT seg)
3bcbcc3d
HPN
3615{
3616 segT sym_seg;
3617
3618 know (n <= 4);
3619 know (fixP);
3620
3621 /* We put the relative "vma" for the other segment for inter-segment
3622 relocations in the object data to stay binary "compatible" (with an
3623 uninteresting old version) for the relocation.
3624 Maybe delete some day. */
3625 if (fixP->fx_addsy
08caf3f8 3626 && (sym_seg = S_GET_SEGMENT (fixP->fx_addsy)) != seg)
3bcbcc3d
HPN
3627 val += sym_seg->vma;
3628
08caf3f8
HPN
3629 if (fixP->fx_addsy != NULL || fixP->fx_pcrel)
3630 switch (fixP->fx_r_type)
3631 {
3632 /* These must be fully resolved when getting here. */
08caf3f8
HPN
3633 case BFD_RELOC_16_PCREL:
3634 case BFD_RELOC_8_PCREL:
ae57792d 3635 as_bad_where (fixP->fx_file, fixP->fx_line,
08caf3f8
HPN
3636 _("PC-relative relocation must be trivially resolved"));
3637 default:
3638 ;
3639 }
3640
bfa1b75c
HPN
3641 /* Only use the computed value for old-arch binaries. For all
3642 others, where we're going to output a relocation, put 0 in the
3643 code. */
ae57792d
HPN
3644 if (cris_arch != arch_cris_any_v0_v10
3645 && (fixP->fx_addsy != NULL || fixP->fx_pcrel))
bfa1b75c 3646 val = 0;
ae57792d 3647
3bcbcc3d
HPN
3648 switch (fixP->fx_r_type)
3649 {
3650 /* Ditto here, we put the addend into the object code as
3651 well as the reloc addend. Keep it that way for now, to simplify
3652 regression tests on the object file contents. FIXME: Seems
3653 uninteresting now that we have a test suite. */
3654
cc99daad
HPN
3655 case BFD_RELOC_CRIS_32_GOT_GD:
3656 case BFD_RELOC_CRIS_16_GOT_GD:
3657 case BFD_RELOC_CRIS_32_GD:
5a00ea25 3658 case BFD_RELOC_CRIS_32_IE:
cc99daad
HPN
3659 case BFD_RELOC_CRIS_32_DTPREL:
3660 case BFD_RELOC_CRIS_16_DTPREL:
3661 case BFD_RELOC_CRIS_32_GOT_TPREL:
3662 case BFD_RELOC_CRIS_16_GOT_TPREL:
3663 case BFD_RELOC_CRIS_32_TPREL:
3664 case BFD_RELOC_CRIS_16_TPREL:
f3294356
HPN
3665#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3666 if (IS_ELF && fixP->fx_addsy != NULL)
3667 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3668#endif
3669 /* Fall through. */
3670
3671 case BFD_RELOC_CRIS_16_GOT:
3672 case BFD_RELOC_CRIS_32_GOT:
3673 case BFD_RELOC_CRIS_32_GOTREL:
3674 case BFD_RELOC_CRIS_16_GOTPLT:
3675 case BFD_RELOC_CRIS_32_GOTPLT:
3676 case BFD_RELOC_CRIS_32_PLT_GOTREL:
3677 case BFD_RELOC_CRIS_32_PLT_PCREL:
08caf3f8
HPN
3678 /* We don't want to put in any kind of non-zero bits in the data
3679 being relocated for these. */
bfa1b75c 3680 md_number_to_chars (bufp, 0, n);
08caf3f8
HPN
3681 break;
3682
08caf3f8 3683 case BFD_RELOC_32_PCREL:
bfa1b75c 3684 /* If this one isn't fully resolved, we don't want to put non-zero
ae57792d
HPN
3685 in the object. */
3686 if (fixP->fx_addsy != NULL || fixP->fx_pcrel)
bfa1b75c 3687 val = 0;
ae57792d
HPN
3688
3689 /* Fall through. */
3690 case BFD_RELOC_32:
3bcbcc3d
HPN
3691 /* No use having warnings here, since most hosts have a 32-bit type
3692 for "long" (which will probably change soon, now that I wrote
3693 this). */
3694 bufp[3] = (val >> 24) & 0xFF;
3695 bufp[2] = (val >> 16) & 0xFF;
3696 bufp[1] = (val >> 8) & 0xFF;
3697 bufp[0] = val & 0xFF;
3698 break;
3699
3700 /* FIXME: The 16 and 8-bit cases should have a way to check
3701 whether a signed or unsigned (or any signedness) number is
ae57792d 3702 accepted. */
3bcbcc3d
HPN
3703
3704 case BFD_RELOC_16:
08caf3f8 3705 case BFD_RELOC_16_PCREL:
3bcbcc3d 3706 if (val > 0xffff || val < -32768)
ae57792d
HPN
3707 as_bad_where (fixP->fx_file, fixP->fx_line,
3708 _("Value not in 16 bit range: %ld"), val);
bfa1b75c
HPN
3709 bufp[1] = (val >> 8) & 0xFF;
3710 bufp[0] = val & 0xFF;
ae57792d
HPN
3711 break;
3712
3713 case BFD_RELOC_CRIS_SIGNED_16:
3714 if (val > 32767 || val < -32768)
3715 as_bad_where (fixP->fx_file, fixP->fx_line,
3716 _("Value not in 16 bit signed range: %ld"), val);
bfa1b75c
HPN
3717 bufp[1] = (val >> 8) & 0xFF;
3718 bufp[0] = val & 0xFF;
3bcbcc3d
HPN
3719 break;
3720
3721 case BFD_RELOC_8:
08caf3f8 3722 case BFD_RELOC_8_PCREL:
3bcbcc3d 3723 if (val > 255 || val < -128)
ae57792d 3724 as_bad_where (fixP->fx_file, fixP->fx_line, _("Value not in 8 bit range: %ld"), val);
bfa1b75c 3725 bufp[0] = val & 0xFF;
ae57792d
HPN
3726 break;
3727
3728 case BFD_RELOC_CRIS_SIGNED_8:
3729 if (val > 127 || val < -128)
3730 as_bad_where (fixP->fx_file, fixP->fx_line,
3731 _("Value not in 8 bit signed range: %ld"), val);
bfa1b75c 3732 bufp[0] = val & 0xFF;
3bcbcc3d
HPN
3733 break;
3734
ae57792d
HPN
3735 case BFD_RELOC_CRIS_LAPCQ_OFFSET:
3736 /* FIXME: Test-cases for out-of-range values. Probably also need
3737 to use as_bad_where. */
3bcbcc3d
HPN
3738 case BFD_RELOC_CRIS_UNSIGNED_4:
3739 if (val > 15 || val < 0)
ae57792d
HPN
3740 as_bad_where (fixP->fx_file, fixP->fx_line,
3741 _("Value not in 4 bit unsigned range: %ld"), val);
bfa1b75c 3742 bufp[0] |= val & 0x0F;
3bcbcc3d
HPN
3743 break;
3744
3745 case BFD_RELOC_CRIS_UNSIGNED_5:
3746 if (val > 31 || val < 0)
ae57792d
HPN
3747 as_bad_where (fixP->fx_file, fixP->fx_line,
3748 _("Value not in 5 bit unsigned range: %ld"), val);
bfa1b75c 3749 bufp[0] |= val & 0x1F;
3bcbcc3d
HPN
3750 break;
3751
3752 case BFD_RELOC_CRIS_SIGNED_6:
3753 if (val > 31 || val < -32)
ae57792d
HPN
3754 as_bad_where (fixP->fx_file, fixP->fx_line,
3755 _("Value not in 6 bit range: %ld"), val);
bfa1b75c 3756 bufp[0] |= val & 0x3F;
3bcbcc3d
HPN
3757 break;
3758
3759 case BFD_RELOC_CRIS_UNSIGNED_6:
3760 if (val > 63 || val < 0)
ae57792d
HPN
3761 as_bad_where (fixP->fx_file, fixP->fx_line,
3762 _("Value not in 6 bit unsigned range: %ld"), val);
bfa1b75c 3763 bufp[0] |= val & 0x3F;
3bcbcc3d
HPN
3764 break;
3765
3766 case BFD_RELOC_CRIS_BDISP8:
bfa1b75c 3767 bufp[0] = branch_disp (val);
3bcbcc3d
HPN
3768 break;
3769
3770 case BFD_RELOC_NONE:
3771 /* May actually happen automatically. For example at broken
3772 words, if the word turns out not to be broken.
47926f60 3773 FIXME: When? Which testcase? */
3bcbcc3d
HPN
3774 if (! fixP->fx_addsy)
3775 md_number_to_chars (bufp, val, n);
3776 break;
3777
3778 case BFD_RELOC_VTABLE_INHERIT:
3779 /* This borrowed from tc-ppc.c on a whim. */
3780 if (fixP->fx_addsy
3781 && !S_IS_DEFINED (fixP->fx_addsy)
3782 && !S_IS_WEAK (fixP->fx_addsy))
3783 S_SET_WEAK (fixP->fx_addsy);
7b15d668
HPN
3784 /* Fall through. */
3785
3bcbcc3d 3786 case BFD_RELOC_VTABLE_ENTRY:
3bcbcc3d
HPN
3787 fixP->fx_done = 0;
3788 break;
3789
3790 default:
3791 BAD_CASE (fixP->fx_r_type);
3792 }
3793}
3794
3bcbcc3d
HPN
3795/* Processes machine-dependent command line options. Called once for
3796 each option on the command line that the machine-independent part of
3797 GAS does not understand. */
47926f60 3798
3bcbcc3d 3799int
17b9d67d 3800md_parse_option (int arg, const char *argp ATTRIBUTE_UNUSED)
3bcbcc3d
HPN
3801{
3802 switch (arg)
3803 {
3804 case 'H':
3805 case 'h':
7b15d668 3806 printf (_("Please use --help to see usage and options for this assembler.\n"));
3bcbcc3d 3807 md_show_usage (stdout);
7b15d668 3808 exit (EXIT_SUCCESS);
3bcbcc3d
HPN
3809
3810 case 'N':
3811 warn_for_branch_expansion = 1;
ae57792d 3812 break;
3bcbcc3d 3813
7b15d668 3814 case OPTION_NO_US:
b34976b6 3815 demand_register_prefix = TRUE;
7b15d668
HPN
3816
3817 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
08caf3f8 3818 as_bad (_("--no-underscore is invalid with a.out format"));
7b15d668 3819 else
b34976b6 3820 symbols_have_leading_underscore = FALSE;
ae57792d 3821 break;
7b15d668
HPN
3822
3823 case OPTION_US:
b34976b6
AM
3824 demand_register_prefix = FALSE;
3825 symbols_have_leading_underscore = TRUE;
ae57792d 3826 break;
7b15d668 3827
08caf3f8 3828 case OPTION_PIC:
0d7e0060
HPN
3829 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
3830 as_bad (_("--pic is invalid for this object format"));
b34976b6 3831 pic = TRUE;
d2aa3f9f
HPN
3832 if (cris_arch != arch_crisv32)
3833 md_long_jump_size = cris_any_v0_v10_long_jump_size_pic;
3834 else
3835 md_long_jump_size = crisv32_long_jump_size;
ae57792d
HPN
3836 break;
3837
3838 case OPTION_ARCH:
3839 {
17b9d67d 3840 const char *str = argp;
ae57792d
HPN
3841 enum cris_archs argarch = cris_arch_from_string (&str);
3842
3843 if (argarch == arch_cris_unknown)
3844 as_bad (_("invalid <arch> in --march=<arch>: %s"), argp);
3845 else
3846 cris_arch = argarch;
3847
3848 if (argarch == arch_crisv32)
3849 {
3850 err_for_dangerous_mul_placement = 0;
3851 md_long_jump_size = crisv32_long_jump_size;
3852 }
3853 else
d2aa3f9f
HPN
3854 {
3855 if (pic)
3856 md_long_jump_size = cris_any_v0_v10_long_jump_size_pic;
3857 else
3858 md_long_jump_size = cris_any_v0_v10_long_jump_size;
3859 }
ae57792d
HPN
3860 }
3861 break;
08caf3f8 3862
1048a9ba
HPN
3863 case OPTION_MULBUG_ABORT_OFF:
3864 err_for_dangerous_mul_placement = 0;
ae57792d 3865 break;
1048a9ba
HPN
3866
3867 case OPTION_MULBUG_ABORT_ON:
3868 err_for_dangerous_mul_placement = 1;
ae57792d 3869 break;
1048a9ba 3870
3bcbcc3d
HPN
3871 default:
3872 return 0;
47926f60 3873 }
ae57792d
HPN
3874
3875 return 1;
3bcbcc3d
HPN
3876}
3877
3878/* Round up a section size to the appropriate boundary. */
3879valueT
695a4822 3880md_section_align (segT segment, valueT size)
3bcbcc3d
HPN
3881{
3882 /* Round all sects to multiple of 4, except the bss section, which
3883 we'll round to word-size.
3884
3885 FIXME: Check if this really matters. All sections should be
3886 rounded up, and all sections should (optionally) be assumed to be
3887 dword-aligned, it's just that there is actual usage of linking to a
3888 multiple of two. */
3889 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
3890 {
3891 if (segment == bss_section)
3892 return (size + 1) & ~1;
3893 return (size + 3) & ~3;
3894 }
3895 else
3896 {
3897 /* FIXME: Is this wanted? It matches the testsuite, but that's not
3898 really a valid reason. */
3899 if (segment == text_section)
3900 return (size + 3) & ~3;
3901 }
3902
3903 return size;
3904}
3905
3bcbcc3d
HPN
3906/* Generate a machine-dependent relocation. */
3907arelent *
695a4822 3908tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP)
3bcbcc3d
HPN
3909{
3910 arelent *relP;
3911 bfd_reloc_code_real_type code;
3912
3913 switch (fixP->fx_r_type)
3914 {
ae57792d
HPN
3915 case BFD_RELOC_CRIS_SIGNED_8:
3916 code = BFD_RELOC_8;
3917 break;
3918
3919 case BFD_RELOC_CRIS_SIGNED_16:
3920 code = BFD_RELOC_16;
3921 break;
3922
08caf3f8
HPN
3923 case BFD_RELOC_CRIS_16_GOT:
3924 case BFD_RELOC_CRIS_32_GOT:
3925 case BFD_RELOC_CRIS_16_GOTPLT:
3926 case BFD_RELOC_CRIS_32_GOTPLT:
3927 case BFD_RELOC_CRIS_32_GOTREL:
3928 case BFD_RELOC_CRIS_32_PLT_GOTREL:
3929 case BFD_RELOC_CRIS_32_PLT_PCREL:
3bcbcc3d 3930 case BFD_RELOC_32:
ae57792d 3931 case BFD_RELOC_32_PCREL:
3bcbcc3d
HPN
3932 case BFD_RELOC_16:
3933 case BFD_RELOC_8:
3934 case BFD_RELOC_VTABLE_INHERIT:
3935 case BFD_RELOC_VTABLE_ENTRY:
ae57792d
HPN
3936 case BFD_RELOC_CRIS_UNSIGNED_8:
3937 case BFD_RELOC_CRIS_UNSIGNED_16:
3938 case BFD_RELOC_CRIS_LAPCQ_OFFSET:
cc99daad
HPN
3939 case BFD_RELOC_CRIS_32_GOT_GD:
3940 case BFD_RELOC_CRIS_16_GOT_GD:
3941 case BFD_RELOC_CRIS_32_GD:
5a00ea25 3942 case BFD_RELOC_CRIS_32_IE:
cc99daad
HPN
3943 case BFD_RELOC_CRIS_32_DTPREL:
3944 case BFD_RELOC_CRIS_16_DTPREL:
3945 case BFD_RELOC_CRIS_32_GOT_TPREL:
3946 case BFD_RELOC_CRIS_16_GOT_TPREL:
3947 case BFD_RELOC_CRIS_32_TPREL:
3948 case BFD_RELOC_CRIS_16_TPREL:
3bcbcc3d
HPN
3949 code = fixP->fx_r_type;
3950 break;
3951 default:
3952 as_bad_where (fixP->fx_file, fixP->fx_line,
3953 _("Semantics error. This type of operand can not be relocated, it must be an assembly-time constant"));
3954 return 0;
3955 }
3956
add39d23 3957 relP = XNEW (arelent);
9c2799c2 3958 gas_assert (relP != 0);
add39d23 3959 relP->sym_ptr_ptr = XNEW (asymbol *);
3bcbcc3d
HPN
3960 *relP->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
3961 relP->address = fixP->fx_frag->fr_address + fixP->fx_where;
3962
ae57792d 3963 relP->addend = fixP->fx_offset;
3bcbcc3d
HPN
3964
3965 /* This is the standard place for KLUDGEs to work around bugs in
3966 bfd_install_relocation (first such note in the documentation
3967 appears with binutils-2.8).
3968
3969 That function bfd_install_relocation does the wrong thing with
3970 putting stuff into the addend of a reloc (it should stay out) for a
3971 weak symbol. The really bad thing is that it adds the
3972 "segment-relative offset" of the symbol into the reloc. In this
3973 case, the reloc should instead be relative to the symbol with no
3974 other offset than the assembly code shows; and since the symbol is
3975 weak, any local definition should be ignored until link time (or
3976 thereafter).
3977 To wit: weaksym+42 should be weaksym+42 in the reloc,
3978 not weaksym+(offset_from_segment_of_local_weaksym_definition)
3979
3980 To "work around" this, we subtract the segment-relative offset of
3981 "known" weak symbols. This evens out the extra offset.
3982
3983 That happens for a.out but not for ELF, since for ELF,
3984 bfd_install_relocation uses the "special function" field of the
3985 howto, and does not execute the code that needs to be undone. */
3986
3987 if (OUTPUT_FLAVOR == bfd_target_aout_flavour
3988 && fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy)
3989 && ! bfd_is_und_section (S_GET_SEGMENT (fixP->fx_addsy)))
47926f60
KH
3990 {
3991 relP->addend -= S_GET_VALUE (fixP->fx_addsy);
3992 }
3bcbcc3d
HPN
3993
3994 relP->howto = bfd_reloc_type_lookup (stdoutput, code);
3995 if (! relP->howto)
3996 {
3997 const char *name;
3998
3999 name = S_GET_NAME (fixP->fx_addsy);
4000 if (name == NULL)
4001 name = _("<unknown>");
4002 as_fatal (_("Cannot generate relocation type for symbol %s, code %s"),
4003 name, bfd_get_reloc_code_name (code));
4004 }
4005
4006 return relP;
4007}
4008
3bcbcc3d 4009/* Machine-dependent usage-output. */
47926f60 4010
3bcbcc3d 4011void
695a4822 4012md_show_usage (FILE *stream)
3bcbcc3d 4013{
08caf3f8 4014 /* The messages are formatted to line up with the generic options. */
7b15d668
HPN
4015 fprintf (stream, _("CRIS-specific options:\n"));
4016 fprintf (stream, "%s",
4017 _(" -h, -H Don't execute, print this help text. Deprecated.\n"));
4018 fprintf (stream, "%s",
4019 _(" -N Warn when branches are expanded to jumps.\n"));
4020 fprintf (stream, "%s",
4021 _(" --underscore User symbols are normally prepended with underscore.\n"));
4022 fprintf (stream, "%s",
4023 _(" Registers will not need any prefix.\n"));
4024 fprintf (stream, "%s",
4025 _(" --no-underscore User symbols do not have any prefix.\n"));
4026 fprintf (stream, "%s",
4027 _(" Registers will require a `$'-prefix.\n"));
0d7e0060 4028#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
08caf3f8
HPN
4029 fprintf (stream, "%s",
4030 _(" --pic Enable generation of position-independent code.\n"));
0d7e0060 4031#endif
ae57792d
HPN
4032 fprintf (stream, "%s",
4033 _(" --march=<arch> Generate code for <arch>. Valid choices for <arch>\n\
4034 are v0_v10, v10, v32 and common_v10_v32.\n"));
3bcbcc3d
HPN
4035}
4036
3bcbcc3d 4037/* Apply a fixS (fixup of an instruction or data that we didn't have
47926f60 4038 enough info to complete immediately) to the data in a frag. */
3bcbcc3d 4039
94f592af 4040void
55cf6793 4041md_apply_fix (fixS *fixP, valueT *valP, segT seg)
3bcbcc3d 4042{
451a1fc5
HPN
4043 /* This assignment truncates upper bits if valueT is 64 bits (as with
4044 --enable-64-bit-bfd), which is fine here, though we cast to avoid
920e4177 4045 any compiler warnings. */
451a1fc5 4046 long val = (long) *valP;
3bcbcc3d
HPN
4047 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
4048
4049 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
4050 fixP->fx_done = 1;
4051
5bc11336
AM
4052 /* We can't actually support subtracting a symbol. */
4053 if (fixP->fx_subsy != (symbolS *) NULL)
4054 as_bad_where (fixP->fx_file, fixP->fx_line,
4055 _("expression too complex"));
4056
4057 /* This operand-type is scaled. */
4058 if (fixP->fx_r_type == BFD_RELOC_CRIS_LAPCQ_OFFSET)
4059 val /= 2;
4060 cris_number_to_imm (buf, val, fixP->fx_size, fixP, seg);
3bcbcc3d
HPN
4061}
4062
3bcbcc3d
HPN
4063/* All relocations are relative to the location just after the fixup;
4064 the address of the fixup plus its size. */
4065
4066long
695a4822 4067md_pcrel_from (fixS *fixP)
3bcbcc3d
HPN
4068{
4069 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
4070
4071 /* FIXME: We get here only at the end of assembly, when X in ".-X" is
08caf3f8
HPN
4072 still unknown. Since we don't have pc-relative relocations in a.out,
4073 this is invalid. What to do if anything for a.out, is to add
3bcbcc3d 4074 pc-relative relocations everywhere including the elinux program
08caf3f8
HPN
4075 loader. For ELF, allow straight-forward PC-relative relocations,
4076 which are always relative to the location after the relocation. */
4077 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
4078 || (fixP->fx_r_type != BFD_RELOC_8_PCREL
4079 && fixP->fx_r_type != BFD_RELOC_16_PCREL
ae57792d
HPN
4080 && fixP->fx_r_type != BFD_RELOC_32_PCREL
4081 && fixP->fx_r_type != BFD_RELOC_CRIS_LAPCQ_OFFSET))
08caf3f8
HPN
4082 as_bad_where (fixP->fx_file, fixP->fx_line,
4083 _("Invalid pc-relative relocation"));
3bcbcc3d
HPN
4084 return fixP->fx_size + addr;
4085}
4086
47926f60 4087/* We have no need to give defaults for symbol-values. */
3bcbcc3d 4088symbolS *
695a4822 4089md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
3bcbcc3d
HPN
4090{
4091 return 0;
4092}
4093
a161fe53
AM
4094/* If this function returns non-zero, it prevents the relocation
4095 against symbol(s) in the FIXP from being replaced with relocations
4096 against section symbols, and guarantees that a relocation will be
4097 emitted even when the value can be resolved locally. */
3bcbcc3d 4098int
695a4822 4099md_cris_force_relocation (struct fix *fixp)
3bcbcc3d 4100{
08caf3f8
HPN
4101 switch (fixp->fx_r_type)
4102 {
08caf3f8
HPN
4103 case BFD_RELOC_CRIS_16_GOT:
4104 case BFD_RELOC_CRIS_32_GOT:
4105 case BFD_RELOC_CRIS_16_GOTPLT:
4106 case BFD_RELOC_CRIS_32_GOTPLT:
4107 case BFD_RELOC_CRIS_32_GOTREL:
4108 case BFD_RELOC_CRIS_32_PLT_GOTREL:
4109 case BFD_RELOC_CRIS_32_PLT_PCREL:
4110 return 1;
4111 default:
4112 ;
4113 }
4114
ae6063d4 4115 return generic_force_reloc (fixp);
3bcbcc3d
HPN
4116}
4117
4118/* Check and emit error if broken-word handling has failed to fix up a
4119 case-table. This is called from write.c, after doing everything it
4120 knows about how to handle broken words. */
4121
4122void
695a4822 4123tc_cris_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP)
3bcbcc3d
HPN
4124{
4125 if (new_offset > 32767 || new_offset < -32768)
47926f60 4126 /* We really want a genuine error, not a warning, so make it one. */
3bcbcc3d
HPN
4127 as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line,
4128 _("Adjusted signed .word (%ld) overflows: `switch'-statement too large."),
4129 (long) new_offset);
4130}
4131
7b15d668
HPN
4132/* Make a leading REGISTER_PREFIX_CHAR mandatory for all registers. */
4133
695a4822
HPN
4134static void
4135cris_force_reg_prefix (void)
7b15d668 4136{
b34976b6 4137 demand_register_prefix = TRUE;
7b15d668
HPN
4138}
4139
4140/* Do not demand a leading REGISTER_PREFIX_CHAR for all registers. */
4141
695a4822
HPN
4142static void
4143cris_relax_reg_prefix (void)
7b15d668 4144{
b34976b6 4145 demand_register_prefix = FALSE;
7b15d668
HPN
4146}
4147
4148/* Adjust for having a leading '_' on all user symbols. */
4149
695a4822
HPN
4150static void
4151cris_sym_leading_underscore (void)
7b15d668
HPN
4152{
4153 /* We can't really do anything more than assert that what the program
4154 thinks symbol starts with agrees with the command-line options, since
4155 the bfd is already created. */
4156
b34976b6 4157 if (!symbols_have_leading_underscore)
ed67db7a 4158 as_bad (_(".syntax %s requires command-line option `--underscore'"),
7b15d668
HPN
4159 SYNTAX_USER_SYM_LEADING_UNDERSCORE);
4160}
4161
4162/* Adjust for not having any particular prefix on user symbols. */
4163
695a4822 4164static void cris_sym_no_leading_underscore (void)
7b15d668 4165{
b34976b6 4166 if (symbols_have_leading_underscore)
ed67db7a 4167 as_bad (_(".syntax %s requires command-line option `--no-underscore'"),
7b15d668
HPN
4168 SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE);
4169}
4170
4171/* Handle the .syntax pseudo, which takes an argument that decides what
4172 syntax the assembly code has. */
4173
4174static void
695a4822 4175s_syntax (int ignore ATTRIBUTE_UNUSED)
7b15d668
HPN
4176{
4177 static const struct syntaxes
4178 {
ae57792d 4179 const char *const operand;
695a4822 4180 void (*fn) (void);
4a1805b1 4181 } syntax_table[] =
7b15d668
HPN
4182 {{SYNTAX_ENFORCE_REG_PREFIX, cris_force_reg_prefix},
4183 {SYNTAX_RELAX_REG_PREFIX, cris_relax_reg_prefix},
4184 {SYNTAX_USER_SYM_LEADING_UNDERSCORE, cris_sym_leading_underscore},
4185 {SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE, cris_sym_no_leading_underscore}};
4186
4187 const struct syntaxes *sp;
4188
4189 for (sp = syntax_table;
4190 sp < syntax_table + sizeof (syntax_table) / sizeof (syntax_table[0]);
4191 sp++)
4192 {
4193 if (strncmp (input_line_pointer, sp->operand,
4194 strlen (sp->operand)) == 0)
4195 {
bc805888 4196 (sp->fn) ();
7b15d668
HPN
4197
4198 input_line_pointer += strlen (sp->operand);
4199 demand_empty_rest_of_line ();
4200 return;
4201 }
4202 }
4203
4204 as_bad (_("Unknown .syntax operand"));
4205}
4206
fcdc20a4
HPN
4207/* Wrapper for dwarf2_directive_file to emit error if this is seen when
4208 not emitting ELF. */
4209
4210static void
695a4822 4211s_cris_file (int dummy)
fcdc20a4
HPN
4212{
4213 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
ed67db7a 4214 as_bad (_("Pseudodirective .file is only valid when generating ELF"));
fcdc20a4
HPN
4215 else
4216 dwarf2_directive_file (dummy);
4217}
4218
4219/* Wrapper for dwarf2_directive_loc to emit error if this is seen when not
4220 emitting ELF. */
4221
4222static void
695a4822 4223s_cris_loc (int dummy)
fcdc20a4
HPN
4224{
4225 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
ed67db7a 4226 as_bad (_("Pseudodirective .loc is only valid when generating ELF"));
fcdc20a4
HPN
4227 else
4228 dwarf2_directive_loc (dummy);
4229}
4230
d2b52762
HPN
4231/* Worker for .dtpoffd: generate a R_CRIS_32_DTPREL reloc, as for
4232 expr:DTPREL but for use in debug info. */
4233
4234static void
4235s_cris_dtpoff (int bytes)
4236{
4237 expressionS ex;
4238 char *p;
4239
4240 if (bytes != 4)
4241 as_fatal (_("internal inconsistency problem: %s called for %d bytes"),
4242 __FUNCTION__, bytes);
4243
4244 expression (&ex);
4245
4246 p = frag_more (bytes);
4247 md_number_to_chars (p, 0, bytes);
4248 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
4249 BFD_RELOC_CRIS_32_DTPREL);
4250
4251 demand_empty_rest_of_line ();
4252}
4253
4254
ae57792d
HPN
4255/* Translate a <arch> string (as common to --march=<arch> and .arch <arch>)
4256 into an enum. If the string *STR is recognized, *STR is updated to point
4257 to the end of the string. If the string is not recognized,
4258 arch_cris_unknown is returned. */
4259
4260static enum cris_archs
17b9d67d 4261cris_arch_from_string (const char **str)
ae57792d
HPN
4262{
4263 static const struct cris_arch_struct
4264 {
4265 const char *const name;
4266 enum cris_archs arch;
4267 } arch_table[] =
4268 /* Keep in order longest-first for choices where one is a prefix
4269 of another. */
4270 {{"v0_v10", arch_cris_any_v0_v10},
4271 {"v10", arch_crisv10},
4272 {"v32", arch_crisv32},
4273 {"common_v10_v32", arch_cris_common_v10_v32}};
4274
4275 const struct cris_arch_struct *ap;
4276
4277 for (ap = arch_table;
4278 ap < arch_table + sizeof (arch_table) / sizeof (arch_table[0]);
4279 ap++)
4280 {
4281 int len = strlen (ap->name);
4282
4283 if (strncmp (*str, ap->name, len) == 0
4284 && (str[0][len] == 0 || ISSPACE (str[0][len])))
4285 {
4286 *str += strlen (ap->name);
4287 return ap->arch;
4288 }
4289 }
4290
4291 return arch_cris_unknown;
4292}
4293
4294/* Return nonzero if architecture version ARCH matches version range in
4295 IVER. */
4296
4297static int
695a4822
HPN
4298cris_insn_ver_valid_for_arch (enum cris_insn_version_usage iver,
4299 enum cris_archs arch)
ae57792d
HPN
4300{
4301 switch (arch)
4302 {
4303 case arch_cris_any_v0_v10:
4304 return
4305 (iver == cris_ver_version_all
4306 || iver == cris_ver_warning
4307 || iver == cris_ver_v0_3
4308 || iver == cris_ver_v3p
4309 || iver == cris_ver_v0_10
4310 || iver == cris_ver_sim_v0_10
4311 || iver == cris_ver_v3_10
4312 || iver == cris_ver_v8
4313 || iver == cris_ver_v8p
4314 || iver == cris_ver_v8_10
4315 || iver == cris_ver_v10
4316 || iver == cris_ver_v10p);
3739860c 4317
ae57792d
HPN
4318 case arch_crisv32:
4319 return
4320 (iver == cris_ver_version_all
4321 || iver == cris_ver_v3p
4322 || iver == cris_ver_v8p
4323 || iver == cris_ver_v10p
4324 || iver == cris_ver_v32p);
4325
4326 case arch_cris_common_v10_v32:
4327 return
4328 (iver == cris_ver_version_all
4329 || iver == cris_ver_v3p
4330 || iver == cris_ver_v8p
4331 || iver == cris_ver_v10p);
4332
4333 case arch_crisv0:
4334 return
4335 (iver == cris_ver_version_all
4336 || iver == cris_ver_v0_3
4337 || iver == cris_ver_v0_10
4338 || iver == cris_ver_sim_v0_10);
4339
4340 case arch_crisv3:
4341 return
4342 (iver == cris_ver_version_all
4343 || iver == cris_ver_v0_3
4344 || iver == cris_ver_v3p
4345 || iver == cris_ver_v0_10
4346 || iver == cris_ver_sim_v0_10
4347 || iver == cris_ver_v3_10);
4348
4349 case arch_crisv8:
4350 return
4351 (iver == cris_ver_version_all
4352 || iver == cris_ver_v3p
4353 || iver == cris_ver_v0_10
4354 || iver == cris_ver_sim_v0_10
4355 || iver == cris_ver_v3_10
4356 || iver == cris_ver_v8
4357 || iver == cris_ver_v8p
4358 || iver == cris_ver_v8_10);
4359
4360 case arch_crisv10:
4361 return
4362 (iver == cris_ver_version_all
4363 || iver == cris_ver_v3p
4364 || iver == cris_ver_v0_10
4365 || iver == cris_ver_sim_v0_10
4366 || iver == cris_ver_v3_10
4367 || iver == cris_ver_v8p
4368 || iver == cris_ver_v8_10
4369 || iver == cris_ver_v10
4370 || iver == cris_ver_v10p);
4371
4372 default:
4373 BAD_CASE (arch);
4374 }
4375}
4376
4377/* Assert that the .arch ARCHCHOICE1 is compatible with the specified or
4378 default --march=<ARCHCHOICE2> option. */
4379
4380static void
695a4822 4381s_cris_arch (int dummy ATTRIBUTE_UNUSED)
ae57792d
HPN
4382{
4383 /* Right now we take the easy route and check for sameness. It's not
4384 obvious that allowing e.g. --march=v32 and .arch common_v0_v32
4385 would be more useful than confusing, implementation-wise and
4386 user-wise. */
4387
17b9d67d 4388 const char *str = input_line_pointer;
ae57792d
HPN
4389 enum cris_archs arch = cris_arch_from_string (&str);
4390
4391 if (arch == arch_cris_unknown)
4392 {
4393 as_bad (_("unknown operand to .arch"));
4394
4395 /* For this one, str does not reflect the end of the operand,
4396 since there was no matching arch. Skip it manually; skip
4397 things that can be part of a word (a name). */
4398 while (is_part_of_name (*str))
4399 str++;
4400 }
4401 else if (arch != cris_arch)
4402 as_bad (_(".arch <arch> requires a matching --march=... option"));
4403
17b9d67d 4404 input_line_pointer = (char *) str;
ae57792d
HPN
4405 demand_empty_rest_of_line ();
4406 return;
4407}
4408
3bcbcc3d
HPN
4409/*
4410 * Local variables:
4411 * eval: (c-set-style "gnu")
4412 * indent-tabs-mode: t
4413 * End:
4414 */
This page took 1.804924 seconds and 4 git commands to generate.