Commit | Line | Data |
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252b5132 | 1 | /* tc-d10v.c -- Assembler code for the Mitsubishi D10V |
49309057 | 2 | Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include <stdio.h> | |
22 | #include <ctype.h> | |
23 | #include "as.h" | |
24 | #include "subsegs.h" | |
25 | #include "opcode/d10v.h" | |
26 | #include "elf/ppc.h" | |
27 | ||
28 | const char comment_chars[] = ";"; | |
29 | const char line_comment_chars[] = "#"; | |
30 | const char line_separator_chars[] = ""; | |
31 | const char *md_shortopts = "O"; | |
32 | const char EXP_CHARS[] = "eE"; | |
33 | const char FLT_CHARS[] = "dD"; | |
34 | ||
35 | int Optimizing = 0; | |
36 | ||
37 | #define AT_WORD_P(X) ((X)->X_op == O_right_shift \ | |
38 | && (X)->X_op_symbol != NULL \ | |
a77f5182 ILT |
39 | && symbol_constant_p ((X)->X_op_symbol) \ |
40 | && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT) | |
252b5132 RH |
41 | #define AT_WORD_RIGHT_SHIFT 2 |
42 | ||
43 | ||
44 | /* fixups */ | |
45 | #define MAX_INSN_FIXUPS (5) | |
46 | struct d10v_fixup | |
47 | { | |
48 | expressionS exp; | |
49 | int operand; | |
50 | int pcrel; | |
51 | int size; | |
52 | bfd_reloc_code_real_type reloc; | |
53 | }; | |
54 | ||
55 | typedef struct _fixups | |
56 | { | |
57 | int fc; | |
58 | struct d10v_fixup fix[MAX_INSN_FIXUPS]; | |
59 | struct _fixups *next; | |
60 | } Fixups; | |
61 | ||
62 | static Fixups FixUps[2]; | |
63 | static Fixups *fixups; | |
64 | ||
0f94f4c8 NC |
65 | static int do_not_ignore_hash = 0; |
66 | ||
0a44c2b1 DL |
67 | typedef int packing_type; |
68 | #define PACK_UNSPEC (0) /* packing order not specified */ | |
69 | #define PACK_PARALLEL (1) /* "||" */ | |
70 | #define PACK_LEFT_RIGHT (2) /* "->" */ | |
71 | #define PACK_RIGHT_LEFT (3) /* "<-" */ | |
72 | static packing_type etype = PACK_UNSPEC; /* used by d10v_cleanup */ | |
73 | ||
252b5132 RH |
74 | /* True if instruction swapping warnings should be inhibited. */ |
75 | static unsigned char flag_warn_suppress_instructionswap; /* --nowarnswap */ | |
76 | ||
77 | /* local functions */ | |
78 | static int reg_name_search PARAMS ((char *name)); | |
79 | static int register_name PARAMS ((expressionS *expressionP)); | |
80 | static int check_range PARAMS ((unsigned long num, int bits, int flags)); | |
81 | static int postfix PARAMS ((char *p)); | |
82 | static bfd_reloc_code_real_type get_reloc PARAMS ((struct d10v_operand *op)); | |
83 | static int get_operands PARAMS ((expressionS exp[])); | |
84 | static struct d10v_opcode *find_opcode PARAMS ((struct d10v_opcode *opcode, expressionS ops[])); | |
85 | static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers, unsigned long insn)); | |
86 | static void write_long PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx)); | |
87 | static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx)); | |
88 | static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1, | |
0a44c2b1 | 89 | struct d10v_opcode *opcode2, unsigned long insn2, packing_type exec_type, Fixups *fx)); |
252b5132 RH |
90 | static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode)); |
91 | static unsigned long d10v_insert_operand PARAMS (( unsigned long insn, int op_type, | |
92 | offsetT value, int left, fixS *fix)); | |
93 | static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1, | |
94 | struct d10v_opcode *opcode2, unsigned long insn2, | |
0a44c2b1 | 95 | packing_type exec_type)); |
252b5132 RH |
96 | static symbolS * find_symbol_matching_register PARAMS ((expressionS *)); |
97 | ||
98 | struct option md_longopts[] = | |
99 | { | |
100 | #define OPTION_NOWARNSWAP (OPTION_MD_BASE) | |
101 | {"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP}, | |
102 | {NULL, no_argument, NULL, 0} | |
103 | }; | |
104 | size_t md_longopts_size = sizeof(md_longopts); | |
105 | ||
106 | static void d10v_dot_word PARAMS ((int)); | |
107 | ||
108 | /* The target specific pseudo-ops which we support. */ | |
109 | const pseudo_typeS md_pseudo_table[] = | |
110 | { | |
111 | { "word", d10v_dot_word, 2 }, | |
112 | { NULL, NULL, 0 } | |
113 | }; | |
114 | ||
115 | /* Opcode hash table. */ | |
116 | static struct hash_control *d10v_hash; | |
117 | ||
118 | /* reg_name_search does a binary search of the d10v_predefined_registers | |
119 | array to see if "name" is a valid regiter name. Returns the register | |
120 | number from the array on success, or -1 on failure. */ | |
121 | ||
122 | static int | |
123 | reg_name_search (name) | |
124 | char *name; | |
125 | { | |
126 | int middle, low, high; | |
127 | int cmp; | |
128 | ||
129 | low = 0; | |
130 | high = d10v_reg_name_cnt() - 1; | |
131 | ||
132 | do | |
133 | { | |
134 | middle = (low + high) / 2; | |
135 | cmp = strcasecmp (name, d10v_predefined_registers[middle].name); | |
136 | if (cmp < 0) | |
137 | high = middle - 1; | |
138 | else if (cmp > 0) | |
139 | low = middle + 1; | |
140 | else | |
141 | return d10v_predefined_registers[middle].value; | |
142 | } | |
143 | while (low <= high); | |
144 | return -1; | |
145 | } | |
146 | ||
147 | /* register_name() checks the string at input_line_pointer | |
148 | to see if it is a valid register name */ | |
149 | ||
150 | static int | |
151 | register_name (expressionP) | |
152 | expressionS *expressionP; | |
153 | { | |
154 | int reg_number; | |
155 | char c, *p = input_line_pointer; | |
156 | ||
157 | while (*p && *p!='\n' && *p!='\r' && *p !=',' && *p!=' ' && *p!=')') | |
158 | p++; | |
159 | ||
160 | c = *p; | |
161 | if (c) | |
162 | *p++ = 0; | |
163 | ||
164 | /* look to see if it's in the register table */ | |
165 | reg_number = reg_name_search (input_line_pointer); | |
166 | if (reg_number >= 0) | |
167 | { | |
168 | expressionP->X_op = O_register; | |
169 | /* temporarily store a pointer to the string here */ | |
49309057 | 170 | expressionP->X_op_symbol = (symbolS *)input_line_pointer; |
252b5132 RH |
171 | expressionP->X_add_number = reg_number; |
172 | input_line_pointer = p; | |
173 | return 1; | |
174 | } | |
175 | if (c) | |
176 | *(p-1) = c; | |
177 | return 0; | |
178 | } | |
179 | ||
180 | ||
181 | static int | |
182 | check_range (num, bits, flags) | |
183 | unsigned long num; | |
184 | int bits; | |
185 | int flags; | |
186 | { | |
187 | long min, max, bit1; | |
188 | int retval=0; | |
189 | ||
190 | /* don't bother checking 16-bit values */ | |
191 | if (bits == 16) | |
192 | return 0; | |
193 | ||
194 | if (flags & OPERAND_SHIFT) | |
195 | { | |
196 | /* all special shift operands are unsigned */ | |
197 | /* and <= 16. We allow 0 for now. */ | |
198 | if (num>16) | |
199 | return 1; | |
200 | else | |
201 | return 0; | |
202 | } | |
203 | ||
204 | if (flags & OPERAND_SIGNED) | |
205 | { | |
c43185de DN |
206 | /* Signed 3-bit integers are restricted to the (-2, 3) range */ |
207 | if (flags & RESTRICTED_NUM3) | |
208 | { | |
209 | if ((long) num < -2 || (long) num > 3) | |
210 | retval = 1; | |
211 | } | |
212 | else | |
213 | { | |
214 | max = (1 << (bits - 1)) - 1; | |
215 | min = - (1 << (bits - 1)); | |
216 | if (((long) num > max) || ((long) num < min)) | |
217 | retval = 1; | |
218 | } | |
252b5132 RH |
219 | } |
220 | else | |
221 | { | |
222 | max = (1 << bits) - 1; | |
223 | min = 0; | |
224 | if ((num > max) || (num < min)) | |
225 | retval = 1; | |
226 | } | |
227 | return retval; | |
228 | } | |
229 | ||
230 | ||
231 | void | |
232 | md_show_usage (stream) | |
233 | FILE *stream; | |
234 | { | |
235 | fprintf(stream, _("D10V options:\n\ | |
236 | -O optimize. Will do some operations in parallel.\n")); | |
237 | } | |
238 | ||
239 | int | |
240 | md_parse_option (c, arg) | |
241 | int c; | |
242 | char *arg; | |
243 | { | |
244 | switch (c) | |
245 | { | |
246 | case 'O': | |
247 | /* Optimize. Will attempt to parallelize operations */ | |
248 | Optimizing = 1; | |
249 | break; | |
250 | case OPTION_NOWARNSWAP: | |
251 | flag_warn_suppress_instructionswap = 1; | |
252 | break; | |
253 | default: | |
254 | return 0; | |
255 | } | |
256 | return 1; | |
257 | } | |
258 | ||
259 | symbolS * | |
260 | md_undefined_symbol (name) | |
261 | char *name; | |
262 | { | |
263 | return 0; | |
264 | } | |
265 | ||
266 | /* Turn a string in input_line_pointer into a floating point constant of type | |
267 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
268 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
269 | */ | |
270 | char * | |
271 | md_atof (type, litP, sizeP) | |
272 | int type; | |
273 | char *litP; | |
274 | int *sizeP; | |
275 | { | |
276 | int prec; | |
277 | LITTLENUM_TYPE words[4]; | |
278 | char *t; | |
279 | int i; | |
280 | ||
281 | switch (type) | |
282 | { | |
283 | case 'f': | |
284 | prec = 2; | |
285 | break; | |
286 | case 'd': | |
287 | prec = 4; | |
288 | break; | |
289 | default: | |
290 | *sizeP = 0; | |
291 | return _("bad call to md_atof"); | |
292 | } | |
293 | ||
294 | t = atof_ieee (input_line_pointer, type, words); | |
295 | if (t) | |
296 | input_line_pointer = t; | |
297 | ||
298 | *sizeP = prec * 2; | |
299 | ||
300 | for (i = 0; i < prec; i++) | |
301 | { | |
302 | md_number_to_chars (litP, (valueT) words[i], 2); | |
303 | litP += 2; | |
304 | } | |
305 | return NULL; | |
306 | } | |
307 | ||
308 | void | |
309 | md_convert_frag (abfd, sec, fragP) | |
310 | bfd *abfd; | |
311 | asection *sec; | |
312 | fragS *fragP; | |
313 | { | |
314 | abort (); | |
315 | } | |
316 | ||
317 | valueT | |
318 | md_section_align (seg, addr) | |
319 | asection *seg; | |
320 | valueT addr; | |
321 | { | |
322 | int align = bfd_get_section_alignment (stdoutput, seg); | |
323 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
324 | } | |
325 | ||
326 | ||
327 | void | |
328 | md_begin () | |
329 | { | |
330 | char *prev_name = ""; | |
331 | struct d10v_opcode *opcode; | |
332 | d10v_hash = hash_new(); | |
333 | ||
334 | /* Insert unique names into hash table. The D10v instruction set | |
335 | has many identical opcode names that have different opcodes based | |
336 | on the operands. This hash table then provides a quick index to | |
337 | the first opcode with a particular name in the opcode table. */ | |
338 | ||
339 | for (opcode = (struct d10v_opcode *)d10v_opcodes; opcode->name; opcode++) | |
340 | { | |
341 | if (strcmp (prev_name, opcode->name)) | |
342 | { | |
343 | prev_name = (char *)opcode->name; | |
344 | hash_insert (d10v_hash, opcode->name, (char *) opcode); | |
345 | } | |
346 | } | |
347 | ||
348 | fixups = &FixUps[0]; | |
349 | FixUps[0].next = &FixUps[1]; | |
350 | FixUps[1].next = &FixUps[0]; | |
351 | } | |
352 | ||
353 | ||
354 | /* this function removes the postincrement or postdecrement | |
355 | operator ( '+' or '-' ) from an expression */ | |
356 | ||
357 | static int postfix (p) | |
358 | char *p; | |
359 | { | |
360 | while (*p != '-' && *p != '+') | |
361 | { | |
362 | if (*p==0 || *p=='\n' || *p=='\r') | |
363 | break; | |
364 | p++; | |
365 | } | |
366 | ||
367 | if (*p == '-') | |
368 | { | |
369 | *p = ' '; | |
370 | return (-1); | |
371 | } | |
372 | if (*p == '+') | |
373 | { | |
374 | *p = ' '; | |
375 | return (1); | |
376 | } | |
377 | ||
378 | return (0); | |
379 | } | |
380 | ||
381 | ||
382 | static bfd_reloc_code_real_type | |
383 | get_reloc (op) | |
384 | struct d10v_operand *op; | |
385 | { | |
386 | int bits = op->bits; | |
387 | ||
388 | if (bits <= 4) | |
389 | return (0); | |
390 | ||
391 | if (op->flags & OPERAND_ADDR) | |
392 | { | |
393 | if (bits == 8) | |
394 | return (BFD_RELOC_D10V_10_PCREL_R); | |
395 | else | |
396 | return (BFD_RELOC_D10V_18_PCREL); | |
397 | } | |
398 | ||
399 | return (BFD_RELOC_16); | |
400 | } | |
401 | ||
402 | ||
403 | /* get_operands parses a string of operands and returns | |
404 | an array of expressions */ | |
405 | ||
406 | static int | |
407 | get_operands (exp) | |
408 | expressionS exp[]; | |
409 | { | |
410 | char *p = input_line_pointer; | |
411 | int numops = 0; | |
412 | int post = 0; | |
0f94f4c8 NC |
413 | int uses_at = 0; |
414 | ||
252b5132 RH |
415 | while (*p) |
416 | { | |
417 | while (*p == ' ' || *p == '\t' || *p == ',') | |
418 | p++; | |
419 | if (*p==0 || *p=='\n' || *p=='\r') | |
420 | break; | |
421 | ||
422 | if (*p == '@') | |
423 | { | |
0f94f4c8 NC |
424 | uses_at = 1; |
425 | ||
252b5132 RH |
426 | p++; |
427 | exp[numops].X_op = O_absent; | |
428 | if (*p == '(') | |
429 | { | |
430 | p++; | |
431 | exp[numops].X_add_number = OPERAND_ATPAR; | |
432 | } | |
433 | else if (*p == '-') | |
434 | { | |
435 | p++; | |
436 | exp[numops].X_add_number = OPERAND_ATMINUS; | |
437 | } | |
438 | else | |
439 | { | |
440 | exp[numops].X_add_number = OPERAND_ATSIGN; | |
441 | post = postfix (p); | |
442 | } | |
443 | numops++; | |
444 | continue; | |
445 | } | |
446 | ||
447 | if (*p == ')') | |
448 | { | |
449 | /* just skip the trailing paren */ | |
450 | p++; | |
451 | continue; | |
452 | } | |
453 | ||
454 | input_line_pointer = p; | |
455 | ||
456 | /* check to see if it might be a register name */ | |
457 | if (!register_name (&exp[numops])) | |
458 | { | |
459 | /* parse as an expression */ | |
0f94f4c8 NC |
460 | if (uses_at) |
461 | { | |
462 | /* Any expression that involves the indirect addressing | |
463 | cannot also involve immediate addressing. Therefore | |
464 | the use of the hash character is illegal. */ | |
465 | int save = do_not_ignore_hash; | |
466 | do_not_ignore_hash = 1; | |
467 | ||
468 | expression (&exp[numops]); | |
469 | ||
470 | do_not_ignore_hash = save; | |
471 | } | |
472 | else | |
473 | expression (&exp[numops]); | |
252b5132 RH |
474 | } |
475 | ||
476 | if (strncasecmp (input_line_pointer, "@word", 5) == 0) | |
477 | { | |
478 | input_line_pointer += 5; | |
479 | if (exp[numops].X_op == O_register) | |
480 | { | |
481 | /* if it looked like a register name but was followed by | |
482 | "@word" then it was really a symbol, so change it to | |
483 | one */ | |
484 | exp[numops].X_op = O_symbol; | |
485 | exp[numops].X_add_symbol = symbol_find_or_make ((char *)exp[numops].X_op_symbol); | |
486 | } | |
487 | ||
488 | /* check for identifier@word+constant */ | |
489 | if (*input_line_pointer == '-' || *input_line_pointer == '+') | |
490 | { | |
491 | char *orig_line = input_line_pointer; | |
492 | expressionS new_exp; | |
493 | expression (&new_exp); | |
494 | exp[numops].X_add_number = new_exp.X_add_number; | |
495 | } | |
496 | ||
497 | /* convert expr into a right shift by AT_WORD_RIGHT_SHIFT */ | |
498 | { | |
499 | expressionS new_exp; | |
500 | memset (&new_exp, 0, sizeof new_exp); | |
501 | new_exp.X_add_number = AT_WORD_RIGHT_SHIFT; | |
502 | new_exp.X_op = O_constant; | |
503 | new_exp.X_unsigned = 1; | |
504 | exp[numops].X_op_symbol = make_expr_symbol (&new_exp); | |
505 | exp[numops].X_op = O_right_shift; | |
506 | } | |
507 | ||
508 | know (AT_WORD_P (&exp[numops])); | |
509 | } | |
510 | ||
511 | if (exp[numops].X_op == O_illegal) | |
512 | as_bad (_("illegal operand")); | |
513 | else if (exp[numops].X_op == O_absent) | |
514 | as_bad (_("missing operand")); | |
515 | ||
516 | numops++; | |
517 | p = input_line_pointer; | |
518 | } | |
519 | ||
520 | switch (post) | |
521 | { | |
522 | case -1: /* postdecrement mode */ | |
523 | exp[numops].X_op = O_absent; | |
524 | exp[numops++].X_add_number = OPERAND_MINUS; | |
525 | break; | |
526 | case 1: /* postincrement mode */ | |
527 | exp[numops].X_op = O_absent; | |
528 | exp[numops++].X_add_number = OPERAND_PLUS; | |
529 | break; | |
530 | } | |
531 | ||
532 | exp[numops].X_op = 0; | |
533 | return (numops); | |
534 | } | |
535 | ||
536 | static unsigned long | |
537 | d10v_insert_operand (insn, op_type, value, left, fix) | |
538 | unsigned long insn; | |
539 | int op_type; | |
540 | offsetT value; | |
541 | int left; | |
542 | fixS *fix; | |
543 | { | |
544 | int shift, bits; | |
545 | ||
546 | shift = d10v_operands[op_type].shift; | |
547 | if (left) | |
548 | shift += 15; | |
549 | ||
550 | bits = d10v_operands[op_type].bits; | |
551 | ||
552 | /* truncate to the proper number of bits */ | |
553 | if (check_range (value, bits, d10v_operands[op_type].flags)) | |
554 | as_bad_where (fix->fx_file, fix->fx_line, _("operand out of range: %d"), value); | |
555 | ||
556 | value &= 0x7FFFFFFF >> (31 - bits); | |
557 | insn |= (value << shift); | |
558 | ||
559 | return insn; | |
560 | } | |
561 | ||
562 | ||
563 | /* build_insn takes a pointer to the opcode entry in the opcode table | |
564 | and the array of operand expressions and returns the instruction */ | |
565 | ||
566 | static unsigned long | |
567 | build_insn (opcode, opers, insn) | |
568 | struct d10v_opcode *opcode; | |
569 | expressionS *opers; | |
570 | unsigned long insn; | |
571 | { | |
572 | int i, bits, shift, flags, format; | |
573 | unsigned long number; | |
574 | ||
575 | /* the insn argument is only used for the DIVS kludge */ | |
576 | if (insn) | |
577 | format = LONG_R; | |
578 | else | |
579 | { | |
580 | insn = opcode->opcode; | |
581 | format = opcode->format; | |
582 | } | |
583 | ||
584 | for (i=0;opcode->operands[i];i++) | |
585 | { | |
586 | flags = d10v_operands[opcode->operands[i]].flags; | |
587 | bits = d10v_operands[opcode->operands[i]].bits; | |
588 | shift = d10v_operands[opcode->operands[i]].shift; | |
589 | number = opers[i].X_add_number; | |
590 | ||
591 | if (flags & OPERAND_REG) | |
592 | { | |
593 | number &= REGISTER_MASK; | |
594 | if (format == LONG_L) | |
595 | shift += 15; | |
596 | } | |
597 | ||
598 | if (opers[i].X_op != O_register && opers[i].X_op != O_constant) | |
599 | { | |
600 | /* now create a fixup */ | |
601 | ||
602 | if (fixups->fc >= MAX_INSN_FIXUPS) | |
603 | as_fatal (_("too many fixups")); | |
604 | ||
605 | if (AT_WORD_P (&opers[i])) | |
606 | { | |
607 | /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD) */ | |
608 | fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18; | |
609 | opers[i].X_op = O_symbol; | |
610 | opers[i].X_op_symbol = NULL; /* Should free it */ | |
611 | /* number is left shifted by AT_WORD_RIGHT_SHIFT so | |
612 | that, it is aligned with the symbol's value. Later, | |
613 | BFD_RELOC_D10V_18 will right shift (symbol_value + | |
614 | X_add_number). */ | |
615 | number <<= AT_WORD_RIGHT_SHIFT; | |
616 | opers[i].X_add_number = number; | |
617 | } | |
618 | else | |
619 | fixups->fix[fixups->fc].reloc = | |
620 | get_reloc((struct d10v_operand *)&d10v_operands[opcode->operands[i]]); | |
621 | ||
622 | if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 || | |
623 | fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18) | |
624 | fixups->fix[fixups->fc].size = 2; | |
625 | else | |
626 | fixups->fix[fixups->fc].size = 4; | |
627 | ||
628 | fixups->fix[fixups->fc].exp = opers[i]; | |
629 | fixups->fix[fixups->fc].operand = opcode->operands[i]; | |
630 | fixups->fix[fixups->fc].pcrel = (flags & OPERAND_ADDR) ? true : false; | |
631 | (fixups->fc)++; | |
632 | } | |
633 | ||
634 | /* truncate to the proper number of bits */ | |
635 | if ((opers[i].X_op == O_constant) && check_range (number, bits, flags)) | |
636 | as_bad (_("operand out of range: %d"),number); | |
637 | number &= 0x7FFFFFFF >> (31 - bits); | |
638 | insn = insn | (number << shift); | |
639 | } | |
640 | ||
641 | /* kludge: for DIVS, we need to put the operands in twice */ | |
642 | /* on the second pass, format is changed to LONG_R to force */ | |
643 | /* the second set of operands to not be shifted over 15 */ | |
644 | if ((opcode->opcode == OPCODE_DIVS) && (format==LONG_L)) | |
645 | insn = build_insn (opcode, opers, insn); | |
646 | ||
647 | return insn; | |
648 | } | |
649 | ||
650 | /* write out a long form instruction */ | |
651 | static void | |
652 | write_long (opcode, insn, fx) | |
653 | struct d10v_opcode *opcode; | |
654 | unsigned long insn; | |
655 | Fixups *fx; | |
656 | { | |
657 | int i, where; | |
658 | char *f = frag_more(4); | |
659 | ||
660 | insn |= FM11; | |
661 | number_to_chars_bigendian (f, insn, 4); | |
662 | ||
663 | for (i=0; i < fx->fc; i++) | |
664 | { | |
665 | if (fx->fix[i].reloc) | |
666 | { | |
667 | where = f - frag_now->fr_literal; | |
668 | if (fx->fix[i].size == 2) | |
669 | where += 2; | |
670 | ||
671 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) | |
672 | fx->fix[i].operand |= 4096; | |
673 | ||
674 | fix_new_exp (frag_now, | |
675 | where, | |
676 | fx->fix[i].size, | |
677 | &(fx->fix[i].exp), | |
678 | fx->fix[i].pcrel, | |
679 | fx->fix[i].operand|2048); | |
680 | } | |
681 | } | |
682 | fx->fc = 0; | |
683 | } | |
684 | ||
685 | ||
686 | /* write out a short form instruction by itself */ | |
687 | static void | |
688 | write_1_short (opcode, insn, fx) | |
689 | struct d10v_opcode *opcode; | |
690 | unsigned long insn; | |
691 | Fixups *fx; | |
692 | { | |
693 | char *f = frag_more(4); | |
694 | int i, where; | |
695 | ||
696 | if (opcode->exec_type & PARONLY) | |
697 | as_fatal (_("Instruction must be executed in parallel with another instruction.")); | |
698 | ||
699 | /* the other container needs to be NOP */ | |
700 | /* according to 4.3.1: for FM=00, sub-instructions performed only | |
701 | by IU cannot be encoded in L-container. */ | |
702 | if (opcode->unit == IU) | |
703 | insn |= FM00 | (NOP << 15); /* right container */ | |
704 | else | |
705 | insn = FM00 | (insn << 15) | NOP; /* left container */ | |
706 | ||
707 | number_to_chars_bigendian (f, insn, 4); | |
708 | for (i=0; i < fx->fc; i++) | |
709 | { | |
710 | if (fx->fix[i].reloc) | |
711 | { | |
712 | where = f - frag_now->fr_literal; | |
713 | if (fx->fix[i].size == 2) | |
714 | where += 2; | |
715 | ||
716 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) | |
717 | fx->fix[i].operand |= 4096; | |
718 | ||
719 | /* if it's an R reloc, we may have to switch it to L */ | |
720 | if ( (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) && (opcode->unit != IU) ) | |
721 | fx->fix[i].operand |= 1024; | |
722 | ||
723 | fix_new_exp (frag_now, | |
724 | where, | |
725 | fx->fix[i].size, | |
726 | &(fx->fix[i].exp), | |
727 | fx->fix[i].pcrel, | |
728 | fx->fix[i].operand|2048); | |
729 | } | |
730 | } | |
731 | fx->fc = 0; | |
732 | } | |
733 | ||
0a44c2b1 DL |
734 | /* Expects two short instructions. |
735 | If possible, writes out both as a single packed instruction. | |
736 | Otherwise, writes out the first one, packed with a NOP. | |
737 | Returns number of instructions not written out. */ | |
738 | ||
252b5132 RH |
739 | static int |
740 | write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx) | |
741 | struct d10v_opcode *opcode1, *opcode2; | |
742 | unsigned long insn1, insn2; | |
0a44c2b1 | 743 | packing_type exec_type; |
252b5132 RH |
744 | Fixups *fx; |
745 | { | |
746 | unsigned long insn; | |
747 | char *f; | |
748 | int i,j, where; | |
749 | ||
0a44c2b1 | 750 | if ( (exec_type != PACK_PARALLEL) && ((opcode1->exec_type & PARONLY) |
252b5132 RH |
751 | || (opcode2->exec_type & PARONLY))) |
752 | as_fatal (_("Instruction must be executed in parallel")); | |
753 | ||
754 | if ( (opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE)) | |
755 | as_fatal (_("Long instructions may not be combined.")); | |
756 | ||
252b5132 RH |
757 | |
758 | switch (exec_type) | |
759 | { | |
0a44c2b1 DL |
760 | case PACK_UNSPEC: /* order not specified */ |
761 | if (opcode1->exec_type & ALONE) | |
762 | { | |
763 | /* Case of a short branch on a separate GAS line. Pack with NOP. */ | |
764 | write_1_short (opcode1, insn1, fx->next); | |
765 | return 1; | |
766 | } | |
767 | if (Optimizing && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) | |
252b5132 RH |
768 | { |
769 | /* parallel */ | |
770 | if (opcode1->unit == IU) | |
771 | insn = FM00 | (insn2 << 15) | insn1; | |
772 | else if (opcode2->unit == MU) | |
773 | insn = FM00 | (insn2 << 15) | insn1; | |
774 | else | |
775 | { | |
776 | insn = FM00 | (insn1 << 15) | insn2; | |
0a44c2b1 | 777 | /* Advance over dummy fixup since packed insn1 in L */ |
252b5132 RH |
778 | fx = fx->next; |
779 | } | |
780 | } | |
781 | else if (opcode1->unit == IU) | |
0a44c2b1 DL |
782 | /* reverse sequential with IU opcode1 on right and done first */ |
783 | insn = FM10 | (insn2 << 15) | insn1; | |
252b5132 RH |
784 | else |
785 | { | |
0a44c2b1 | 786 | /* sequential with non-IU opcode1 on left and done first */ |
252b5132 | 787 | insn = FM01 | (insn1 << 15) | insn2; |
0a44c2b1 DL |
788 | /* Advance over dummy fixup since packed insn1 in L */ |
789 | fx = fx->next; | |
252b5132 RH |
790 | } |
791 | break; | |
252b5132 | 792 | |
0a44c2b1 DL |
793 | |
794 | case PACK_PARALLEL: | |
795 | if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ) | |
796 | as_fatal | |
797 | (_("One of these instructions may not be executed in parallel.")); | |
252b5132 RH |
798 | if (opcode1->unit == IU) |
799 | { | |
800 | if (opcode2->unit == IU) | |
801 | as_fatal (_("Two IU instructions may not be executed in parallel")); | |
802 | if (!flag_warn_suppress_instructionswap) | |
803 | as_warn (_("Swapping instruction order")); | |
804 | insn = FM00 | (insn2 << 15) | insn1; | |
805 | } | |
806 | else if (opcode2->unit == MU) | |
807 | { | |
808 | if (opcode1->unit == MU) | |
809 | as_fatal (_("Two MU instructions may not be executed in parallel")); | |
810 | if (!flag_warn_suppress_instructionswap) | |
811 | as_warn (_("Swapping instruction order")); | |
812 | insn = FM00 | (insn2 << 15) | insn1; | |
813 | } | |
814 | else | |
815 | { | |
816 | insn = FM00 | (insn1 << 15) | insn2; | |
0a44c2b1 | 817 | /* Advance over dummy fixup since packed insn1 in L */ |
252b5132 RH |
818 | fx = fx->next; |
819 | } | |
820 | break; | |
0a44c2b1 DL |
821 | |
822 | ||
823 | case PACK_LEFT_RIGHT: | |
252b5132 RH |
824 | if (opcode1->unit != IU) |
825 | insn = FM01 | (insn1 << 15) | insn2; | |
826 | else if (opcode2->unit == MU || opcode2->unit == EITHER) | |
827 | { | |
828 | if (!flag_warn_suppress_instructionswap) | |
829 | as_warn (_("Swapping instruction order")); | |
0a44c2b1 | 830 | insn = FM10 | (insn2 << 15) | insn1; |
252b5132 RH |
831 | } |
832 | else | |
833 | as_fatal (_("IU instruction may not be in the left container")); | |
0a44c2b1 DL |
834 | if (opcode1->exec_type & ALONE) |
835 | as_warn (_("Instruction in R container is squashed by flow control instruction in L container.")); | |
836 | /* Advance over dummy fixup */ | |
252b5132 RH |
837 | fx = fx->next; |
838 | break; | |
0a44c2b1 DL |
839 | |
840 | ||
841 | case PACK_RIGHT_LEFT: | |
252b5132 RH |
842 | if (opcode2->unit != MU) |
843 | insn = FM10 | (insn1 << 15) | insn2; | |
844 | else if (opcode1->unit == IU || opcode1->unit == EITHER) | |
845 | { | |
846 | if (!flag_warn_suppress_instructionswap) | |
847 | as_warn (_("Swapping instruction order")); | |
848 | insn = FM01 | (insn2 << 15) | insn1; | |
849 | } | |
850 | else | |
851 | as_fatal (_("MU instruction may not be in the right container")); | |
0a44c2b1 DL |
852 | if (opcode2->exec_type & ALONE) |
853 | as_warn (_("Instruction in R container is squashed by flow control instruction in L container.")); | |
854 | /* Advance over dummy fixup */ | |
252b5132 RH |
855 | fx = fx->next; |
856 | break; | |
0a44c2b1 DL |
857 | |
858 | ||
252b5132 RH |
859 | default: |
860 | as_fatal (_("unknown execution type passed to write_2_short()")); | |
861 | } | |
862 | ||
0a44c2b1 | 863 | |
252b5132 RH |
864 | f = frag_more(4); |
865 | number_to_chars_bigendian (f, insn, 4); | |
866 | ||
0a44c2b1 DL |
867 | /* Process fixup chains. |
868 | Note that the packing code above advanced fx conditionally. | |
869 | dlindsay@cygnus.com: There's something subtle going on here involving | |
870 | _dummy_first_bfd_reloc_code_real. This is related to the | |
871 | difference between BFD_RELOC_D10V_10_PCREL_R and _L, ie whether | |
872 | a fixup is done in the L or R container. A bug in this code | |
873 | can pass Plum Hall fine, yet still affect hand-written assembler. */ | |
874 | ||
252b5132 RH |
875 | for (j=0; j<2; j++) |
876 | { | |
877 | for (i=0; i < fx->fc; i++) | |
878 | { | |
879 | if (fx->fix[i].reloc) | |
880 | { | |
881 | where = f - frag_now->fr_literal; | |
882 | if (fx->fix[i].size == 2) | |
883 | where += 2; | |
884 | ||
885 | if ( (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) && (j == 0) ) | |
886 | fx->fix[i].operand |= 1024; | |
887 | ||
888 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) | |
889 | fx->fix[i].operand |= 4096; | |
890 | ||
891 | fix_new_exp (frag_now, | |
892 | where, | |
893 | fx->fix[i].size, | |
894 | &(fx->fix[i].exp), | |
895 | fx->fix[i].pcrel, | |
896 | fx->fix[i].operand|2048); | |
897 | } | |
898 | } | |
899 | fx->fc = 0; | |
900 | fx = fx->next; | |
901 | } | |
902 | return (0); | |
903 | } | |
904 | ||
905 | ||
906 | /* Check 2 instructions and determine if they can be safely */ | |
907 | /* executed in parallel. Returns 1 if they can be. */ | |
908 | static int | |
909 | parallel_ok (op1, insn1, op2, insn2, exec_type) | |
910 | struct d10v_opcode *op1, *op2; | |
911 | unsigned long insn1, insn2; | |
0a44c2b1 | 912 | packing_type exec_type; |
252b5132 RH |
913 | { |
914 | int i, j, flags, mask, shift, regno; | |
915 | unsigned long ins, mod[2], used[2]; | |
916 | struct d10v_opcode *op; | |
917 | ||
918 | if ((op1->exec_type & SEQ) != 0 || (op2->exec_type & SEQ) != 0 | |
919 | || (op1->exec_type & PAR) == 0 || (op2->exec_type & PAR) == 0 | |
920 | || (op1->unit == BOTH) || (op2->unit == BOTH) | |
921 | || (op1->unit == IU && op2->unit == IU) | |
922 | || (op1->unit == MU && op2->unit == MU)) | |
923 | return 0; | |
924 | ||
0a44c2b1 DL |
925 | /* If this is auto parallization, and either instruction is a branch, |
926 | don't parallel. */ | |
927 | if (exec_type == PACK_UNSPEC | |
928 | && (op1->exec_type & ALONE || op2->exec_type & ALONE)) | |
252b5132 RH |
929 | return 0; |
930 | ||
931 | /* The idea here is to create two sets of bitmasks (mod and used) | |
932 | which indicate which registers are modified or used by each | |
933 | instruction. The operation can only be done in parallel if | |
934 | instruction 1 and instruction 2 modify different registers, and | |
935 | the first instruction does not modify registers that the second | |
936 | is using (The second instruction can modify registers that the | |
937 | first is using as they are only written back after the first | |
938 | instruction has completed). Accesses to control registers, PSW, | |
939 | and memory are treated as accesses to a single register. So if | |
940 | both instructions write memory or if the first instruction writes | |
941 | memory and the second reads, then they cannot be done in | |
942 | parallel. Likewise, if the first instruction mucks with the psw | |
943 | and the second reads the PSW (which includes C, F0, and F1), then | |
944 | they cannot operate safely in parallel. */ | |
945 | ||
946 | /* the bitmasks (mod and used) look like this (bit 31 = MSB) */ | |
947 | /* r0-r15 0-15 */ | |
948 | /* a0-a1 16-17 */ | |
949 | /* cr (not psw) 18 */ | |
950 | /* psw 19 */ | |
951 | /* mem 20 */ | |
952 | ||
953 | for (j=0;j<2;j++) | |
954 | { | |
955 | if (j == 0) | |
956 | { | |
957 | op = op1; | |
958 | ins = insn1; | |
959 | } | |
960 | else | |
961 | { | |
962 | op = op2; | |
963 | ins = insn2; | |
964 | } | |
965 | mod[j] = used[j] = 0; | |
966 | if (op->exec_type & BRANCH_LINK) | |
967 | mod[j] |= 1 << 13; | |
968 | ||
969 | for (i = 0; op->operands[i]; i++) | |
970 | { | |
971 | flags = d10v_operands[op->operands[i]].flags; | |
972 | shift = d10v_operands[op->operands[i]].shift; | |
973 | mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits); | |
974 | if (flags & OPERAND_REG) | |
975 | { | |
976 | regno = (ins >> shift) & mask; | |
977 | if (flags & (OPERAND_ACC0|OPERAND_ACC1)) | |
978 | regno += 16; | |
979 | else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */ | |
980 | { | |
981 | if (regno == 0) | |
982 | regno = 19; | |
983 | else | |
984 | regno = 18; | |
985 | } | |
986 | else if (flags & (OPERAND_FFLAG|OPERAND_CFLAG)) | |
987 | regno = 19; | |
988 | ||
989 | if ( flags & OPERAND_DEST ) | |
990 | { | |
991 | mod[j] |= 1 << regno; | |
992 | if (flags & OPERAND_EVEN) | |
993 | mod[j] |= 1 << (regno + 1); | |
994 | } | |
995 | else | |
996 | { | |
997 | used[j] |= 1 << regno ; | |
998 | if (flags & OPERAND_EVEN) | |
999 | used[j] |= 1 << (regno + 1); | |
1000 | ||
1001 | /* Auto inc/dec also modifies the register. */ | |
1002 | if (op->operands[i+1] != 0 | |
1003 | && (d10v_operands[op->operands[i+1]].flags | |
1004 | & (OPERAND_PLUS | OPERAND_MINUS)) != 0) | |
1005 | mod[j] |= 1 << regno; | |
1006 | } | |
1007 | } | |
1008 | else if (flags & OPERAND_ATMINUS) | |
1009 | { | |
1010 | /* SP implicitly used/modified */ | |
1011 | mod[j] |= 1 << 15; | |
1012 | used[j] |= 1 << 15; | |
1013 | } | |
1014 | } | |
1015 | if (op->exec_type & RMEM) | |
1016 | used[j] |= 1 << 20; | |
1017 | else if (op->exec_type & WMEM) | |
1018 | mod[j] |= 1 << 20; | |
1019 | else if (op->exec_type & RF0) | |
1020 | used[j] |= 1 << 19; | |
1021 | else if (op->exec_type & WF0) | |
1022 | mod[j] |= 1 << 19; | |
1023 | else if (op->exec_type & WCAR) | |
1024 | mod[j] |= 1 << 19; | |
1025 | } | |
1026 | if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0) | |
1027 | return 1; | |
1028 | return 0; | |
1029 | } | |
1030 | ||
1031 | ||
1032 | /* This is the main entry point for the machine-dependent assembler. str points to a | |
1033 | machine-dependent instruction. This function is supposed to emit the frags/bytes | |
1034 | it assembles to. For the D10V, it mostly handles the special VLIW parsing and packing | |
1035 | and leaves the difficult stuff to do_assemble(). | |
1036 | */ | |
1037 | ||
1038 | static unsigned long prev_insn; | |
1039 | static struct d10v_opcode *prev_opcode = 0; | |
1040 | static subsegT prev_subseg; | |
1041 | static segT prev_seg = 0;; | |
252b5132 RH |
1042 | |
1043 | void | |
1044 | md_assemble (str) | |
1045 | char *str; | |
1046 | { | |
0a44c2b1 DL |
1047 | /* etype is saved extype. for multiline instructions */ |
1048 | ||
1049 | packing_type extype = PACK_UNSPEC; /* parallel, etc */ | |
1050 | ||
252b5132 RH |
1051 | struct d10v_opcode * opcode; |
1052 | unsigned long insn; | |
252b5132 RH |
1053 | char * str2; |
1054 | ||
0a44c2b1 | 1055 | if (etype == PACK_UNSPEC) |
252b5132 RH |
1056 | { |
1057 | /* look for the special multiple instruction separators */ | |
1058 | str2 = strstr (str, "||"); | |
1059 | if (str2) | |
0a44c2b1 | 1060 | extype = PACK_PARALLEL; |
252b5132 RH |
1061 | else |
1062 | { | |
1063 | str2 = strstr (str, "->"); | |
1064 | if (str2) | |
0a44c2b1 | 1065 | extype = PACK_LEFT_RIGHT; |
252b5132 RH |
1066 | else |
1067 | { | |
1068 | str2 = strstr (str, "<-"); | |
1069 | if (str2) | |
0a44c2b1 | 1070 | extype = PACK_RIGHT_LEFT; |
252b5132 RH |
1071 | } |
1072 | } | |
1073 | /* str2 points to the separator, if one */ | |
1074 | if (str2) | |
1075 | { | |
1076 | *str2 = 0; | |
1077 | ||
1078 | /* if two instructions are present and we already have one saved | |
0a44c2b1 | 1079 | then first write out the save one */ |
252b5132 RH |
1080 | d10v_cleanup (); |
1081 | ||
1082 | /* assemble first instruction and save it */ | |
1083 | prev_insn = do_assemble (str, &prev_opcode); | |
1084 | if (prev_insn == -1) | |
1085 | as_fatal (_("can't find opcode ")); | |
1086 | fixups = fixups->next; | |
1087 | str = str2 + 2; | |
1088 | } | |
1089 | } | |
1090 | ||
1091 | insn = do_assemble (str, &opcode); | |
1092 | if (insn == -1) | |
1093 | { | |
0a44c2b1 | 1094 | if (extype != PACK_UNSPEC) |
252b5132 RH |
1095 | { |
1096 | etype = extype; | |
1097 | return; | |
1098 | } | |
1099 | as_fatal (_("can't find opcode ")); | |
1100 | } | |
1101 | ||
0a44c2b1 | 1102 | if (etype != PACK_UNSPEC) |
252b5132 RH |
1103 | { |
1104 | extype = etype; | |
0a44c2b1 | 1105 | etype = PACK_UNSPEC; |
252b5132 RH |
1106 | } |
1107 | ||
1108 | /* if this is a long instruction, write it and any previous short instruction */ | |
1109 | if (opcode->format & LONG_OPCODE) | |
1110 | { | |
0a44c2b1 | 1111 | if (extype != PACK_UNSPEC) |
252b5132 RH |
1112 | as_fatal (_("Unable to mix instructions as specified")); |
1113 | d10v_cleanup (); | |
1114 | write_long (opcode, insn, fixups); | |
1115 | prev_opcode = NULL; | |
1116 | return; | |
1117 | } | |
1118 | ||
1119 | if (prev_opcode && prev_seg && ((prev_seg != now_seg) || (prev_subseg != now_subseg))) | |
0a44c2b1 | 1120 | d10v_cleanup (); |
252b5132 RH |
1121 | |
1122 | if (prev_opcode && (write_2_short (prev_opcode, prev_insn, opcode, insn, extype, fixups) == 0)) | |
1123 | { | |
1124 | /* no instructions saved */ | |
1125 | prev_opcode = NULL; | |
1126 | } | |
1127 | else | |
1128 | { | |
0a44c2b1 | 1129 | if (extype != PACK_UNSPEC) |
252b5132 RH |
1130 | as_fatal (_("Unable to mix instructions as specified")); |
1131 | /* save off last instruction so it may be packed on next pass */ | |
1132 | prev_opcode = opcode; | |
1133 | prev_insn = insn; | |
1134 | prev_seg = now_seg; | |
1135 | prev_subseg = now_subseg; | |
1136 | fixups = fixups->next; | |
1137 | } | |
1138 | } | |
1139 | ||
1140 | ||
1141 | /* do_assemble assembles a single instruction and returns an opcode */ | |
1142 | /* it returns -1 (an invalid opcode) on error */ | |
1143 | ||
1144 | static unsigned long | |
1145 | do_assemble (str, opcode) | |
1146 | char *str; | |
1147 | struct d10v_opcode **opcode; | |
1148 | { | |
1149 | unsigned char *op_start, *save; | |
1150 | unsigned char *op_end; | |
1151 | char name[20]; | |
1152 | int nlen = 0; | |
1153 | expressionS myops[6]; | |
1154 | unsigned long insn; | |
1155 | ||
1156 | /* Drop leading whitespace. */ | |
1157 | while (*str == ' ') | |
1158 | str++; | |
1159 | ||
1160 | /* Find the opcode end. */ | |
1161 | for (op_start = op_end = (unsigned char *) (str); | |
1162 | *op_end | |
1163 | && nlen < 20 | |
1164 | && !is_end_of_line[*op_end] && *op_end != ' '; | |
1165 | op_end++) | |
1166 | { | |
1167 | name[nlen] = tolower (op_start[nlen]); | |
1168 | nlen++; | |
1169 | } | |
1170 | name[nlen] = 0; | |
1171 | ||
1172 | if (nlen == 0) | |
1173 | return -1; | |
1174 | ||
1175 | /* Find the first opcode with the proper name. */ | |
1176 | *opcode = (struct d10v_opcode *)hash_find (d10v_hash, name); | |
1177 | if (*opcode == NULL) | |
1178 | as_fatal (_("unknown opcode: %s"),name); | |
1179 | ||
1180 | save = input_line_pointer; | |
1181 | input_line_pointer = op_end; | |
1182 | *opcode = find_opcode (*opcode, myops); | |
1183 | if (*opcode == 0) | |
1184 | return -1; | |
1185 | input_line_pointer = save; | |
1186 | ||
1187 | insn = build_insn ((*opcode), myops, 0); | |
1188 | return (insn); | |
1189 | } | |
1190 | ||
1191 | /* Find the symbol which has the same name as the register in the given expression. */ | |
1192 | static symbolS * | |
1193 | find_symbol_matching_register (exp) | |
1194 | expressionS * exp; | |
1195 | { | |
1196 | int i; | |
1197 | ||
1198 | if (exp->X_op != O_register) | |
1199 | return NULL; | |
1200 | ||
1201 | /* Find the name of the register. */ | |
1202 | for (i = d10v_reg_name_cnt (); i--;) | |
1203 | if (d10v_predefined_registers [i].value == exp->X_add_number) | |
1204 | break; | |
1205 | ||
1206 | if (i < 0) | |
1207 | abort (); | |
1208 | ||
1209 | /* Now see if a symbol has been defined with the same name. */ | |
1210 | return symbol_find (d10v_predefined_registers [i].name); | |
1211 | } | |
1212 | ||
1213 | ||
1214 | /* find_opcode() gets a pointer to an entry in the opcode table. */ | |
1215 | /* It must look at all opcodes with the same name and use the operands */ | |
1216 | /* to choose the correct opcode. */ | |
1217 | ||
1218 | static struct d10v_opcode * | |
1219 | find_opcode (opcode, myops) | |
1220 | struct d10v_opcode *opcode; | |
1221 | expressionS myops[]; | |
1222 | { | |
1223 | int i, match, done; | |
1224 | struct d10v_opcode *next_opcode; | |
1225 | ||
1226 | /* get all the operands and save them as expressions */ | |
1227 | get_operands (myops); | |
1228 | ||
1229 | /* now see if the operand is a fake. If so, find the correct size */ | |
1230 | /* instruction, if possible */ | |
1231 | if (opcode->format == OPCODE_FAKE) | |
1232 | { | |
1233 | int opnum = opcode->operands[0]; | |
1234 | int flags; | |
1235 | ||
1236 | if (myops[opnum].X_op == O_register) | |
1237 | { | |
1238 | myops[opnum].X_op = O_symbol; | |
1239 | myops[opnum].X_add_symbol = symbol_find_or_make ((char *)myops[opnum].X_op_symbol); | |
1240 | myops[opnum].X_add_number = 0; | |
1241 | myops[opnum].X_op_symbol = NULL; | |
1242 | } | |
1243 | ||
1244 | next_opcode=opcode+1; | |
1245 | ||
1246 | /* If the first operand is supposed to be a register, make sure | |
1247 | we got a valid one. */ | |
1248 | flags = d10v_operands[next_opcode->operands[0]].flags; | |
1249 | if (flags & OPERAND_REG) | |
1250 | { | |
1251 | int X_op = myops[0].X_op; | |
1252 | int num = myops[0].X_add_number; | |
1253 | ||
1254 | if (X_op != O_register | |
1255 | || (num & ~flags | |
1256 | & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 | |
1257 | | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL))) | |
1258 | { | |
1259 | as_bad (_("bad opcode or operands")); | |
1260 | return 0; | |
1261 | } | |
1262 | } | |
1263 | ||
1264 | if (myops[opnum].X_op == O_constant || (myops[opnum].X_op == O_symbol && | |
1265 | S_IS_DEFINED(myops[opnum].X_add_symbol) && | |
1266 | (S_GET_SEGMENT(myops[opnum].X_add_symbol) == now_seg))) | |
1267 | { | |
1268 | for (i=0; opcode->operands[i+1]; i++) | |
1269 | { | |
1270 | int bits = d10v_operands[next_opcode->operands[opnum]].bits; | |
1271 | int flags = d10v_operands[next_opcode->operands[opnum]].flags; | |
1272 | if (flags & OPERAND_ADDR) | |
1273 | bits += 2; | |
3db10f32 | 1274 | |
252b5132 RH |
1275 | if (myops[opnum].X_op == O_constant) |
1276 | { | |
1277 | if (!check_range (myops[opnum].X_add_number, bits, flags)) | |
1278 | return next_opcode; | |
1279 | } | |
1280 | else | |
1281 | { | |
3db10f32 NC |
1282 | fragS * sym_frag; |
1283 | fragS * f; | |
1284 | unsigned long current_position; | |
1285 | unsigned long symbol_position; | |
1286 | unsigned long value; | |
1287 | boolean found_symbol; | |
1288 | ||
1289 | /* Calculate the address of the current instruction | |
1290 | and the address of the symbol. Do this by summing | |
1291 | the offsets of previous frags until we reach the | |
1292 | frag containing the symbol, and the current frag. */ | |
1293 | sym_frag = symbol_get_frag (myops[opnum].X_add_symbol); | |
1294 | found_symbol = false; | |
1295 | ||
1296 | current_position = obstack_next_free (&frchain_now->frch_obstack) - frag_now->fr_literal; | |
1297 | symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol); | |
1298 | ||
1299 | for (f = frchain_now->frch_root; f; f = f->fr_next) | |
1300 | { | |
1301 | current_position += f->fr_fix + f->fr_offset; | |
1302 | ||
1303 | if (f == sym_frag) | |
1304 | found_symbol = true; | |
1305 | ||
1306 | if (! found_symbol) | |
1307 | symbol_position += f->fr_fix + f->fr_offset; | |
1308 | } | |
252b5132 | 1309 | |
3db10f32 NC |
1310 | value = symbol_position; |
1311 | ||
252b5132 | 1312 | if (flags & OPERAND_ADDR) |
3db10f32 NC |
1313 | value -= current_position; |
1314 | ||
252b5132 RH |
1315 | if (AT_WORD_P (&myops[opnum])) |
1316 | { | |
1317 | if (bits > 4) | |
1318 | { | |
1319 | bits += 2; | |
1320 | if (!check_range (value, bits, flags)) | |
1321 | return next_opcode; | |
1322 | } | |
1323 | } | |
1324 | else if (!check_range (value, bits, flags)) | |
1325 | return next_opcode; | |
1326 | } | |
1327 | next_opcode++; | |
1328 | } | |
1329 | as_fatal (_("value out of range")); | |
1330 | } | |
1331 | else | |
1332 | { | |
1333 | /* not a constant, so use a long instruction */ | |
1334 | return opcode+2; | |
1335 | } | |
1336 | } | |
1337 | else | |
1338 | { | |
1339 | match = 0; | |
1340 | /* now search the opcode table table for one with operands */ | |
1341 | /* that matches what we've got */ | |
1342 | while (!match) | |
1343 | { | |
1344 | match = 1; | |
1345 | for (i = 0; opcode->operands[i]; i++) | |
1346 | { | |
1347 | int flags = d10v_operands[opcode->operands[i]].flags; | |
1348 | int X_op = myops[i].X_op; | |
1349 | int num = myops[i].X_add_number; | |
1350 | ||
1351 | if (X_op == 0) | |
1352 | { | |
1353 | match = 0; | |
1354 | break; | |
1355 | } | |
1356 | ||
1357 | if (flags & OPERAND_REG) | |
1358 | { | |
1359 | if ((X_op != O_register) | |
1360 | || (num & ~flags | |
1361 | & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 | |
1362 | | OPERAND_FFLAG | OPERAND_CFLAG | |
1363 | | OPERAND_CONTROL))) | |
1364 | { | |
1365 | match = 0; | |
1366 | break; | |
1367 | } | |
1368 | } | |
1369 | ||
1370 | if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) || | |
1371 | ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) || | |
1372 | ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) || | |
1373 | ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) || | |
d9fd9852 | 1374 | ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || ((num != OPERAND_ATSIGN) && (num != OPERAND_ATPAR))))) |
252b5132 RH |
1375 | { |
1376 | match = 0; | |
1377 | break; | |
1378 | } | |
1379 | ||
1380 | /* Unfortunatly, for the indirect operand in instructions such as | |
1381 | ``ldb r1, @(c,r14)'' this function can be passed X_op == O_register | |
1382 | (because 'c' is a valid register name). However we cannot just | |
1383 | ignore the case when X_op == O_register but flags & OPERAND_REG is | |
1384 | null, so we check to see if a symbol of the same name as the register | |
1385 | exists. If the symbol does exist, then the parser was unable to | |
1386 | distinguish the two cases and we fix things here. (Ref: PR14826) */ | |
1387 | ||
1388 | if (!(flags & OPERAND_REG) && (X_op == O_register)) | |
1389 | { | |
1390 | symbolS * sym; | |
1391 | ||
1392 | sym = find_symbol_matching_register (& myops[i]); | |
1393 | ||
1394 | if (sym != NULL) | |
1395 | { | |
1396 | myops [i].X_op == X_op == O_symbol; | |
1397 | myops [i].X_add_symbol = sym; | |
1398 | } | |
1399 | else | |
1400 | as_bad | |
1401 | (_("illegal operand - register name found where none expected")); | |
1402 | } | |
1403 | } | |
1404 | ||
1405 | /* We're only done if the operands matched so far AND there | |
1406 | are no more to check. */ | |
1407 | if (match && myops[i].X_op == 0) | |
1408 | break; | |
1409 | else | |
1410 | match = 0; | |
1411 | ||
1412 | next_opcode = opcode + 1; | |
1413 | ||
1414 | if (next_opcode->opcode == 0) | |
1415 | break; | |
1416 | ||
1417 | if (strcmp (next_opcode->name, opcode->name)) | |
1418 | break; | |
1419 | ||
1420 | opcode = next_opcode; | |
1421 | } | |
1422 | } | |
1423 | ||
1424 | if (!match) | |
1425 | { | |
1426 | as_bad (_("bad opcode or operands")); | |
1427 | return (0); | |
1428 | } | |
1429 | ||
1430 | /* Check that all registers that are required to be even are. */ | |
1431 | /* Also, if any operands were marked as registers, but were really symbols */ | |
1432 | /* fix that here. */ | |
1433 | for (i=0; opcode->operands[i]; i++) | |
1434 | { | |
1435 | if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) && | |
1436 | (myops[i].X_add_number & 1)) | |
1437 | as_fatal (_("Register number must be EVEN")); | |
1438 | if (myops[i].X_op == O_register) | |
1439 | { | |
1440 | if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG)) | |
1441 | { | |
1442 | myops[i].X_op = O_symbol; | |
1443 | myops[i].X_add_symbol = symbol_find_or_make ((char *)myops[i].X_op_symbol); | |
1444 | myops[i].X_add_number = 0; | |
1445 | myops[i].X_op_symbol = NULL; | |
1446 | } | |
1447 | } | |
1448 | } | |
1449 | return opcode; | |
1450 | } | |
1451 | ||
1452 | /* if while processing a fixup, a reloc really needs to be created */ | |
1453 | /* then it is done here */ | |
1454 | ||
1455 | arelent * | |
1456 | tc_gen_reloc (seg, fixp) | |
1457 | asection *seg; | |
1458 | fixS *fixp; | |
1459 | { | |
1460 | arelent *reloc; | |
1461 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
310b5aa2 ILT |
1462 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
1463 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
1464 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
1465 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
1466 | if (reloc->howto == (reloc_howto_type *) NULL) | |
1467 | { | |
1468 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1469 | _("reloc %d not supported by object file format"), (int)fixp->fx_r_type); | |
1470 | return NULL; | |
1471 | } | |
1472 | ||
1473 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1474 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1475 | reloc->address = fixp->fx_offset; | |
1476 | ||
1477 | reloc->addend = fixp->fx_addnumber; | |
1478 | ||
1479 | return reloc; | |
1480 | } | |
1481 | ||
1482 | int | |
1483 | md_estimate_size_before_relax (fragp, seg) | |
1484 | fragS *fragp; | |
1485 | asection *seg; | |
1486 | { | |
1487 | abort (); | |
1488 | return 0; | |
1489 | } | |
1490 | ||
1491 | long | |
1492 | md_pcrel_from_section (fixp, sec) | |
1493 | fixS *fixp; | |
1494 | segT sec; | |
1495 | { | |
1496 | if (fixp->fx_addsy != (symbolS *)NULL && (!S_IS_DEFINED (fixp->fx_addsy) || | |
1497 | (S_GET_SEGMENT (fixp->fx_addsy) != sec))) | |
1498 | return 0; | |
1499 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
1500 | } | |
1501 | ||
1502 | int | |
1503 | md_apply_fix3 (fixp, valuep, seg) | |
1504 | fixS *fixp; | |
1505 | valueT *valuep; | |
1506 | segT seg; | |
1507 | { | |
1508 | char *where; | |
1509 | unsigned long insn; | |
1510 | long value; | |
1511 | int op_type; | |
1512 | int left=0; | |
1513 | ||
1514 | if (fixp->fx_addsy == (symbolS *) NULL) | |
1515 | { | |
1516 | value = *valuep; | |
1517 | fixp->fx_done = 1; | |
1518 | } | |
1519 | else if (fixp->fx_pcrel) | |
1520 | value = *valuep; | |
1521 | else | |
1522 | { | |
1523 | value = fixp->fx_offset; | |
1524 | if (fixp->fx_subsy != (symbolS *) NULL) | |
1525 | { | |
1526 | if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section) | |
1527 | value -= S_GET_VALUE (fixp->fx_subsy); | |
1528 | else | |
1529 | { | |
1530 | /* We don't actually support subtracting a symbol. */ | |
1531 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1532 | _("expression too complex")); | |
1533 | } | |
1534 | } | |
1535 | } | |
1536 | ||
1537 | op_type = fixp->fx_r_type; | |
1538 | if (op_type & 2048) | |
1539 | { | |
1540 | op_type -= 2048; | |
1541 | if (op_type & 1024) | |
1542 | { | |
1543 | op_type -= 1024; | |
1544 | fixp->fx_r_type = BFD_RELOC_D10V_10_PCREL_L; | |
1545 | left = 1; | |
1546 | } | |
1547 | else if (op_type & 4096) | |
1548 | { | |
1549 | op_type -= 4096; | |
1550 | fixp->fx_r_type = BFD_RELOC_D10V_18; | |
1551 | } | |
1552 | else | |
1553 | fixp->fx_r_type = get_reloc((struct d10v_operand *)&d10v_operands[op_type]); | |
1554 | } | |
1555 | ||
1556 | /* Fetch the instruction, insert the fully resolved operand | |
1557 | value, and stuff the instruction back again. */ | |
1558 | where = fixp->fx_frag->fr_literal + fixp->fx_where; | |
1559 | insn = bfd_getb32 ((unsigned char *) where); | |
1560 | ||
1561 | switch (fixp->fx_r_type) | |
1562 | { | |
1563 | case BFD_RELOC_D10V_10_PCREL_L: | |
1564 | case BFD_RELOC_D10V_10_PCREL_R: | |
1565 | case BFD_RELOC_D10V_18_PCREL: | |
1566 | case BFD_RELOC_D10V_18: | |
1567 | /* instruction addresses are always right-shifted by 2 */ | |
1568 | value >>= AT_WORD_RIGHT_SHIFT; | |
1569 | if (fixp->fx_size == 2) | |
1570 | bfd_putb16 ((bfd_vma) value, (unsigned char *) where); | |
1571 | else | |
1572 | { | |
1573 | struct d10v_opcode *rep, *repi; | |
1574 | ||
1575 | rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep"); | |
1576 | repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi"); | |
1577 | if ((insn & FM11) == FM11 | |
1ed18ec1 NC |
1578 | && ((repi != NULL && (insn & repi->mask) == repi->opcode) |
1579 | || (rep != NULL && (insn & rep->mask) == rep->opcode)) | |
252b5132 RH |
1580 | && value < 4) |
1581 | as_fatal | |
1582 | (_("line %d: rep or repi must include at least 4 instructions"), | |
1583 | fixp->fx_line); | |
1584 | insn = d10v_insert_operand (insn, op_type, (offsetT)value, left, fixp); | |
1585 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1586 | } | |
1587 | break; | |
1588 | case BFD_RELOC_32: | |
1589 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); | |
1590 | break; | |
1591 | case BFD_RELOC_16: | |
1592 | bfd_putb16 ((bfd_vma) value, (unsigned char *) where); | |
1593 | break; | |
1594 | ||
1595 | case BFD_RELOC_VTABLE_INHERIT: | |
1596 | case BFD_RELOC_VTABLE_ENTRY: | |
1597 | fixp->fx_done = 0; | |
1598 | return 1; | |
1599 | ||
1600 | default: | |
1601 | as_fatal (_("line %d: unknown relocation type: 0x%x"),fixp->fx_line,fixp->fx_r_type); | |
1602 | } | |
1603 | return 0; | |
1604 | } | |
1605 | ||
1606 | /* d10v_cleanup() is called after the assembler has finished parsing the input | |
1607 | file or after a label is defined. Because the D10V assembler sometimes saves short | |
1608 | instructions to see if it can package them with the next instruction, there may | |
0a44c2b1 DL |
1609 | be a short instruction that still needs written. |
1610 | NOTE: accesses a global, etype. | |
1611 | NOTE: invoked by various macros such as md_cleanup: see. */ | |
252b5132 RH |
1612 | int |
1613 | d10v_cleanup () | |
1614 | { | |
1615 | segT seg; | |
1616 | subsegT subseg; | |
1617 | ||
0a44c2b1 | 1618 | if (prev_opcode && etype == PACK_UNSPEC) |
252b5132 RH |
1619 | { |
1620 | seg = now_seg; | |
1621 | subseg = now_subseg; | |
1622 | if (prev_seg) | |
1623 | subseg_set (prev_seg, prev_subseg); | |
1624 | write_1_short (prev_opcode, prev_insn, fixups->next); | |
1625 | subseg_set (seg, subseg); | |
1626 | prev_opcode = NULL; | |
1627 | } | |
1628 | return 1; | |
1629 | } | |
1630 | ||
1631 | /* Like normal .word, except support @word */ | |
1632 | /* clobbers input_line_pointer, checks end-of-line. */ | |
1633 | static void | |
1634 | d10v_dot_word (nbytes) | |
1635 | register int nbytes; /* 1=.byte, 2=.word, 4=.long */ | |
1636 | { | |
1637 | expressionS exp; | |
1638 | bfd_reloc_code_real_type reloc; | |
1639 | char *p; | |
1640 | int offset; | |
1641 | ||
1642 | if (is_it_end_of_statement ()) | |
1643 | { | |
1644 | demand_empty_rest_of_line (); | |
1645 | return; | |
1646 | } | |
1647 | ||
1648 | do | |
1649 | { | |
1650 | expression (&exp); | |
1651 | if (!strncasecmp (input_line_pointer, "@word", 5)) | |
1652 | { | |
1653 | exp.X_add_number = 0; | |
1654 | input_line_pointer += 5; | |
1655 | ||
1656 | p = frag_more (2); | |
1657 | fix_new_exp (frag_now, p - frag_now->fr_literal, 2, | |
1658 | &exp, 0, BFD_RELOC_D10V_18); | |
1659 | } | |
1660 | else | |
1661 | emit_expr (&exp, 2); | |
1662 | } | |
1663 | while (*input_line_pointer++ == ','); | |
1664 | ||
1665 | input_line_pointer--; /* Put terminator back into stream. */ | |
1666 | demand_empty_rest_of_line (); | |
1667 | } | |
1668 | ||
1669 | ||
1670 | /* Mitsubishi asked that we support some old syntax that apparently */ | |
1671 | /* had immediate operands starting with '#'. This is in some of their */ | |
1672 | /* sample code but is not documented (although it appears in some */ | |
1673 | /* examples in their assembler manual). For now, we'll solve this */ | |
1674 | /* compatibility problem by simply ignoring any '#' at the beginning */ | |
1675 | /* of an operand. */ | |
1676 | ||
1677 | /* operands that begin with '#' should fall through to here */ | |
1678 | /* from expr.c */ | |
1679 | ||
1680 | void | |
1681 | md_operand (expressionP) | |
1682 | expressionS *expressionP; | |
1683 | { | |
0f94f4c8 | 1684 | if (*input_line_pointer == '#' && ! do_not_ignore_hash) |
252b5132 RH |
1685 | { |
1686 | input_line_pointer++; | |
1687 | expression (expressionP); | |
1688 | } | |
1689 | } | |
1690 | ||
1691 | boolean | |
1692 | d10v_fix_adjustable (fixP) | |
1693 | fixS *fixP; | |
1694 | { | |
1695 | ||
1696 | if (fixP->fx_addsy == NULL) | |
1697 | return 1; | |
1698 | ||
1699 | /* Prevent all adjustments to global symbols. */ | |
1700 | if (S_IS_EXTERN (fixP->fx_addsy)) | |
1701 | return 0; | |
1702 | if (S_IS_WEAK (fixP->fx_addsy)) | |
1703 | return 0; | |
1704 | ||
1705 | /* We need the symbol name for the VTABLE entries */ | |
1706 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1707 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1708 | return 0; | |
1709 | ||
1710 | return 1; | |
1711 | } | |
1712 | ||
1713 | int | |
1714 | d10v_force_relocation (fixp) | |
3db10f32 | 1715 | fixS *fixp; |
252b5132 RH |
1716 | { |
1717 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1718 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1719 | return 1; | |
1720 | ||
1721 | return 0; | |
1722 | } |