Commit | Line | Data |
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252b5132 | 1 | /* tc-d10v.c -- Assembler code for the Mitsubishi D10V |
2132e3a3 | 2 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 |
f7e42eb4 | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include <stdio.h> | |
252b5132 | 23 | #include "as.h" |
3882b010 | 24 | #include "safe-ctype.h" |
e0c6ed95 | 25 | #include "subsegs.h" |
252b5132 RH |
26 | #include "opcode/d10v.h" |
27 | #include "elf/ppc.h" | |
28 | ||
ea1562b3 NC |
29 | const char comment_chars[] = ";"; |
30 | const char line_comment_chars[] = "#"; | |
252b5132 | 31 | const char line_separator_chars[] = ""; |
ea1562b3 NC |
32 | const char *md_shortopts = "O"; |
33 | const char EXP_CHARS[] = "eE"; | |
34 | const char FLT_CHARS[] = "dD"; | |
252b5132 RH |
35 | |
36 | int Optimizing = 0; | |
37 | ||
38 | #define AT_WORD_P(X) ((X)->X_op == O_right_shift \ | |
39 | && (X)->X_op_symbol != NULL \ | |
a77f5182 ILT |
40 | && symbol_constant_p ((X)->X_op_symbol) \ |
41 | && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT) | |
252b5132 RH |
42 | #define AT_WORD_RIGHT_SHIFT 2 |
43 | ||
e0c6ed95 | 44 | /* Fixups. */ |
ea1562b3 NC |
45 | #define MAX_INSN_FIXUPS 5 |
46 | ||
252b5132 RH |
47 | struct d10v_fixup |
48 | { | |
49 | expressionS exp; | |
50 | int operand; | |
51 | int pcrel; | |
52 | int size; | |
53 | bfd_reloc_code_real_type reloc; | |
54 | }; | |
55 | ||
56 | typedef struct _fixups | |
57 | { | |
58 | int fc; | |
59 | struct d10v_fixup fix[MAX_INSN_FIXUPS]; | |
60 | struct _fixups *next; | |
61 | } Fixups; | |
62 | ||
63 | static Fixups FixUps[2]; | |
64 | static Fixups *fixups; | |
65 | ||
0f94f4c8 NC |
66 | static int do_not_ignore_hash = 0; |
67 | ||
0a44c2b1 | 68 | typedef int packing_type; |
e0c6ed95 AM |
69 | #define PACK_UNSPEC (0) /* Packing order not specified. */ |
70 | #define PACK_PARALLEL (1) /* "||" */ | |
71 | #define PACK_LEFT_RIGHT (2) /* "->" */ | |
72 | #define PACK_RIGHT_LEFT (3) /* "<-" */ | |
73 | static packing_type etype = PACK_UNSPEC; /* Used by d10v_cleanup. */ | |
0a44c2b1 | 74 | |
b34976b6 | 75 | /* TRUE if instruction swapping warnings should be inhibited. |
bfb32b52 | 76 | --nowarnswap. */ |
b34976b6 | 77 | static bfd_boolean flag_warn_suppress_instructionswap; |
bccba5f0 | 78 | |
b34976b6 | 79 | /* TRUE if instruction packing should be performed when --gstabs is specified. |
bccba5f0 | 80 | --gstabs-packing, --no-gstabs-packing. */ |
b34976b6 | 81 | static bfd_boolean flag_allow_gstabs_packing = 1; |
252b5132 | 82 | |
e0c6ed95 | 83 | /* Local functions. */ |
ea1562b3 NC |
84 | |
85 | enum options | |
86 | { | |
87 | OPTION_NOWARNSWAP = OPTION_MD_BASE, | |
88 | OPTION_GSTABSPACKING, | |
89 | OPTION_NOGSTABSPACKING | |
90 | }; | |
252b5132 RH |
91 | |
92 | struct option md_longopts[] = | |
93 | { | |
252b5132 | 94 | {"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP}, |
bccba5f0 NC |
95 | {"gstabspacking", no_argument, NULL, OPTION_GSTABSPACKING}, |
96 | {"gstabs-packing", no_argument, NULL, OPTION_GSTABSPACKING}, | |
bccba5f0 NC |
97 | {"nogstabspacking", no_argument, NULL, OPTION_NOGSTABSPACKING}, |
98 | {"no-gstabs-packing", no_argument, NULL, OPTION_NOGSTABSPACKING}, | |
252b5132 RH |
99 | {NULL, no_argument, NULL, 0} |
100 | }; | |
ab3e48dc KH |
101 | |
102 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 | 103 | |
252b5132 RH |
104 | /* Opcode hash table. */ |
105 | static struct hash_control *d10v_hash; | |
106 | ||
e0c6ed95 AM |
107 | /* Do a binary search of the d10v_predefined_registers array to see if |
108 | NAME is a valid regiter name. Return the register number from the | |
109 | array on success, or -1 on failure. */ | |
252b5132 RH |
110 | |
111 | static int | |
ea1562b3 | 112 | reg_name_search (char *name) |
252b5132 RH |
113 | { |
114 | int middle, low, high; | |
115 | int cmp; | |
116 | ||
117 | low = 0; | |
e0c6ed95 | 118 | high = d10v_reg_name_cnt () - 1; |
252b5132 RH |
119 | |
120 | do | |
121 | { | |
122 | middle = (low + high) / 2; | |
123 | cmp = strcasecmp (name, d10v_predefined_registers[middle].name); | |
124 | if (cmp < 0) | |
125 | high = middle - 1; | |
126 | else if (cmp > 0) | |
127 | low = middle + 1; | |
e0c6ed95 AM |
128 | else |
129 | return d10v_predefined_registers[middle].value; | |
252b5132 RH |
130 | } |
131 | while (low <= high); | |
132 | return -1; | |
133 | } | |
134 | ||
e0c6ed95 AM |
135 | /* Check the string at input_line_pointer |
136 | to see if it is a valid register name. */ | |
252b5132 RH |
137 | |
138 | static int | |
ea1562b3 | 139 | register_name (expressionS *expressionP) |
252b5132 RH |
140 | { |
141 | int reg_number; | |
142 | char c, *p = input_line_pointer; | |
e0c6ed95 AM |
143 | |
144 | while (*p | |
145 | && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')') | |
252b5132 RH |
146 | p++; |
147 | ||
148 | c = *p; | |
149 | if (c) | |
150 | *p++ = 0; | |
151 | ||
e0c6ed95 | 152 | /* Look to see if it's in the register table. */ |
252b5132 | 153 | reg_number = reg_name_search (input_line_pointer); |
e0c6ed95 | 154 | if (reg_number >= 0) |
252b5132 RH |
155 | { |
156 | expressionP->X_op = O_register; | |
e0c6ed95 AM |
157 | /* Temporarily store a pointer to the string here. */ |
158 | expressionP->X_op_symbol = (symbolS *) input_line_pointer; | |
252b5132 RH |
159 | expressionP->X_add_number = reg_number; |
160 | input_line_pointer = p; | |
161 | return 1; | |
162 | } | |
163 | if (c) | |
e0c6ed95 | 164 | *(p - 1) = c; |
252b5132 RH |
165 | return 0; |
166 | } | |
167 | ||
252b5132 | 168 | static int |
ea1562b3 | 169 | check_range (unsigned long num, int bits, int flags) |
252b5132 | 170 | { |
bccba5f0 | 171 | long min, max; |
e0c6ed95 | 172 | int retval = 0; |
252b5132 | 173 | |
e0c6ed95 | 174 | /* Don't bother checking 16-bit values. */ |
252b5132 RH |
175 | if (bits == 16) |
176 | return 0; | |
177 | ||
178 | if (flags & OPERAND_SHIFT) | |
179 | { | |
e0c6ed95 AM |
180 | /* All special shift operands are unsigned and <= 16. |
181 | We allow 0 for now. */ | |
182 | if (num > 16) | |
252b5132 RH |
183 | return 1; |
184 | else | |
185 | return 0; | |
186 | } | |
187 | ||
188 | if (flags & OPERAND_SIGNED) | |
189 | { | |
e0c6ed95 | 190 | /* Signed 3-bit integers are restricted to the (-2, 3) range. */ |
c43185de DN |
191 | if (flags & RESTRICTED_NUM3) |
192 | { | |
193 | if ((long) num < -2 || (long) num > 3) | |
194 | retval = 1; | |
195 | } | |
196 | else | |
197 | { | |
e0c6ed95 AM |
198 | max = (1 << (bits - 1)) - 1; |
199 | min = - (1 << (bits - 1)); | |
c43185de DN |
200 | if (((long) num > max) || ((long) num < min)) |
201 | retval = 1; | |
202 | } | |
252b5132 RH |
203 | } |
204 | else | |
205 | { | |
206 | max = (1 << bits) - 1; | |
207 | min = 0; | |
bccba5f0 | 208 | if (((long) num > max) || ((long) num < min)) |
252b5132 RH |
209 | retval = 1; |
210 | } | |
211 | return retval; | |
212 | } | |
213 | ||
252b5132 | 214 | void |
ea1562b3 | 215 | md_show_usage (FILE *stream) |
252b5132 | 216 | { |
e0c6ed95 | 217 | fprintf (stream, _("D10V options:\n\ |
bccba5f0 NC |
218 | -O Optimize. Will do some operations in parallel.\n\ |
219 | --gstabs-packing Pack adjacent short instructions together even\n\ | |
220 | when --gstabs is specified. On by default.\n\ | |
221 | --no-gstabs-packing If --gstabs is specified, do not pack adjacent\n\ | |
222 | instructions together.\n")); | |
e0c6ed95 | 223 | } |
252b5132 RH |
224 | |
225 | int | |
ea1562b3 | 226 | md_parse_option (int c, char *arg ATTRIBUTE_UNUSED) |
252b5132 RH |
227 | { |
228 | switch (c) | |
229 | { | |
230 | case 'O': | |
e0c6ed95 | 231 | /* Optimize. Will attempt to parallelize operations. */ |
252b5132 RH |
232 | Optimizing = 1; |
233 | break; | |
234 | case OPTION_NOWARNSWAP: | |
235 | flag_warn_suppress_instructionswap = 1; | |
236 | break; | |
bccba5f0 NC |
237 | case OPTION_GSTABSPACKING: |
238 | flag_allow_gstabs_packing = 1; | |
239 | break; | |
240 | case OPTION_NOGSTABSPACKING: | |
241 | flag_allow_gstabs_packing = 0; | |
242 | break; | |
252b5132 RH |
243 | default: |
244 | return 0; | |
245 | } | |
246 | return 1; | |
247 | } | |
248 | ||
249 | symbolS * | |
ea1562b3 | 250 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
251 | { |
252 | return 0; | |
253 | } | |
254 | ||
e0c6ed95 AM |
255 | /* Turn a string in input_line_pointer into a floating point constant |
256 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
257 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
258 | returned, or NULL on OK. */ | |
259 | ||
252b5132 | 260 | char * |
ea1562b3 | 261 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
262 | { |
263 | int prec; | |
264 | LITTLENUM_TYPE words[4]; | |
265 | char *t; | |
266 | int i; | |
e0c6ed95 | 267 | |
252b5132 RH |
268 | switch (type) |
269 | { | |
270 | case 'f': | |
271 | prec = 2; | |
272 | break; | |
273 | case 'd': | |
274 | prec = 4; | |
275 | break; | |
276 | default: | |
277 | *sizeP = 0; | |
278 | return _("bad call to md_atof"); | |
279 | } | |
280 | ||
281 | t = atof_ieee (input_line_pointer, type, words); | |
282 | if (t) | |
283 | input_line_pointer = t; | |
e0c6ed95 | 284 | |
252b5132 | 285 | *sizeP = prec * 2; |
e0c6ed95 | 286 | |
252b5132 RH |
287 | for (i = 0; i < prec; i++) |
288 | { | |
289 | md_number_to_chars (litP, (valueT) words[i], 2); | |
e0c6ed95 | 290 | litP += 2; |
252b5132 RH |
291 | } |
292 | return NULL; | |
293 | } | |
294 | ||
295 | void | |
ea1562b3 NC |
296 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
297 | asection *sec ATTRIBUTE_UNUSED, | |
298 | fragS *fragP ATTRIBUTE_UNUSED) | |
252b5132 RH |
299 | { |
300 | abort (); | |
301 | } | |
302 | ||
303 | valueT | |
ea1562b3 | 304 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
305 | { |
306 | int align = bfd_get_section_alignment (stdoutput, seg); | |
307 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
308 | } | |
309 | ||
252b5132 | 310 | void |
ea1562b3 | 311 | md_begin (void) |
252b5132 RH |
312 | { |
313 | char *prev_name = ""; | |
314 | struct d10v_opcode *opcode; | |
e0c6ed95 | 315 | d10v_hash = hash_new (); |
252b5132 RH |
316 | |
317 | /* Insert unique names into hash table. The D10v instruction set | |
318 | has many identical opcode names that have different opcodes based | |
319 | on the operands. This hash table then provides a quick index to | |
320 | the first opcode with a particular name in the opcode table. */ | |
321 | ||
e0c6ed95 | 322 | for (opcode = (struct d10v_opcode *) d10v_opcodes; opcode->name; opcode++) |
252b5132 RH |
323 | { |
324 | if (strcmp (prev_name, opcode->name)) | |
325 | { | |
e0c6ed95 | 326 | prev_name = (char *) opcode->name; |
252b5132 RH |
327 | hash_insert (d10v_hash, opcode->name, (char *) opcode); |
328 | } | |
329 | } | |
330 | ||
331 | fixups = &FixUps[0]; | |
332 | FixUps[0].next = &FixUps[1]; | |
333 | FixUps[1].next = &FixUps[0]; | |
334 | } | |
335 | ||
e0c6ed95 AM |
336 | /* Remove the postincrement or postdecrement operator ( '+' or '-' ) |
337 | from an expression. */ | |
252b5132 | 338 | |
e0c6ed95 | 339 | static int |
ea1562b3 | 340 | postfix (char *p) |
252b5132 | 341 | { |
e0c6ed95 | 342 | while (*p != '-' && *p != '+') |
252b5132 | 343 | { |
e0c6ed95 | 344 | if (*p == 0 || *p == '\n' || *p == '\r') |
252b5132 RH |
345 | break; |
346 | p++; | |
347 | } | |
348 | ||
e0c6ed95 | 349 | if (*p == '-') |
252b5132 RH |
350 | { |
351 | *p = ' '; | |
ea1562b3 | 352 | return -1; |
252b5132 | 353 | } |
e0c6ed95 | 354 | if (*p == '+') |
252b5132 RH |
355 | { |
356 | *p = ' '; | |
ea1562b3 | 357 | return 1; |
252b5132 RH |
358 | } |
359 | ||
ea1562b3 | 360 | return 0; |
252b5132 RH |
361 | } |
362 | ||
e0c6ed95 | 363 | static bfd_reloc_code_real_type |
ea1562b3 | 364 | get_reloc (struct d10v_operand *op) |
252b5132 RH |
365 | { |
366 | int bits = op->bits; | |
367 | ||
e0c6ed95 | 368 | if (bits <= 4) |
ea1562b3 | 369 | return 0; |
e0c6ed95 AM |
370 | |
371 | if (op->flags & OPERAND_ADDR) | |
252b5132 RH |
372 | { |
373 | if (bits == 8) | |
ea1562b3 | 374 | return BFD_RELOC_D10V_10_PCREL_R; |
252b5132 | 375 | else |
ea1562b3 | 376 | return BFD_RELOC_D10V_18_PCREL; |
252b5132 RH |
377 | } |
378 | ||
ea1562b3 | 379 | return BFD_RELOC_16; |
252b5132 RH |
380 | } |
381 | ||
e0c6ed95 | 382 | /* Parse a string of operands. Return an array of expressions. */ |
252b5132 RH |
383 | |
384 | static int | |
ea1562b3 | 385 | get_operands (expressionS exp[]) |
252b5132 RH |
386 | { |
387 | char *p = input_line_pointer; | |
388 | int numops = 0; | |
389 | int post = 0; | |
0f94f4c8 | 390 | int uses_at = 0; |
e0c6ed95 AM |
391 | |
392 | while (*p) | |
252b5132 | 393 | { |
e0c6ed95 | 394 | while (*p == ' ' || *p == '\t' || *p == ',') |
252b5132 | 395 | p++; |
e0c6ed95 | 396 | if (*p == 0 || *p == '\n' || *p == '\r') |
252b5132 | 397 | break; |
e0c6ed95 AM |
398 | |
399 | if (*p == '@') | |
252b5132 | 400 | { |
0f94f4c8 | 401 | uses_at = 1; |
e0c6ed95 | 402 | |
252b5132 RH |
403 | p++; |
404 | exp[numops].X_op = O_absent; | |
e0c6ed95 | 405 | if (*p == '(') |
252b5132 RH |
406 | { |
407 | p++; | |
408 | exp[numops].X_add_number = OPERAND_ATPAR; | |
409 | } | |
e0c6ed95 | 410 | else if (*p == '-') |
252b5132 RH |
411 | { |
412 | p++; | |
413 | exp[numops].X_add_number = OPERAND_ATMINUS; | |
414 | } | |
415 | else | |
416 | { | |
417 | exp[numops].X_add_number = OPERAND_ATSIGN; | |
3543a2f1 AO |
418 | if (*p == '+') |
419 | { | |
8c0392a9 AO |
420 | numops++; |
421 | exp[numops].X_op = O_absent; | |
422 | exp[numops].X_add_number = OPERAND_PLUS; | |
423 | p++; | |
3543a2f1 | 424 | } |
252b5132 RH |
425 | post = postfix (p); |
426 | } | |
427 | numops++; | |
428 | continue; | |
429 | } | |
430 | ||
e0c6ed95 | 431 | if (*p == ')') |
252b5132 | 432 | { |
e0c6ed95 | 433 | /* Just skip the trailing paren. */ |
252b5132 RH |
434 | p++; |
435 | continue; | |
436 | } | |
437 | ||
438 | input_line_pointer = p; | |
439 | ||
e0c6ed95 | 440 | /* Check to see if it might be a register name. */ |
252b5132 RH |
441 | if (!register_name (&exp[numops])) |
442 | { | |
e0c6ed95 | 443 | /* Parse as an expression. */ |
0f94f4c8 NC |
444 | if (uses_at) |
445 | { | |
446 | /* Any expression that involves the indirect addressing | |
447 | cannot also involve immediate addressing. Therefore | |
448 | the use of the hash character is illegal. */ | |
449 | int save = do_not_ignore_hash; | |
450 | do_not_ignore_hash = 1; | |
e0c6ed95 | 451 | |
0f94f4c8 | 452 | expression (&exp[numops]); |
e0c6ed95 | 453 | |
0f94f4c8 NC |
454 | do_not_ignore_hash = save; |
455 | } | |
456 | else | |
457 | expression (&exp[numops]); | |
252b5132 RH |
458 | } |
459 | ||
460 | if (strncasecmp (input_line_pointer, "@word", 5) == 0) | |
461 | { | |
462 | input_line_pointer += 5; | |
463 | if (exp[numops].X_op == O_register) | |
464 | { | |
e0c6ed95 | 465 | /* If it looked like a register name but was followed by |
252b5132 | 466 | "@word" then it was really a symbol, so change it to |
e0c6ed95 | 467 | one. */ |
252b5132 | 468 | exp[numops].X_op = O_symbol; |
e0c6ed95 AM |
469 | exp[numops].X_add_symbol = |
470 | symbol_find_or_make ((char *) exp[numops].X_op_symbol); | |
252b5132 RH |
471 | } |
472 | ||
e0c6ed95 | 473 | /* Check for identifier@word+constant. */ |
252b5132 | 474 | if (*input_line_pointer == '-' || *input_line_pointer == '+') |
e0c6ed95 | 475 | { |
e0c6ed95 AM |
476 | expressionS new_exp; |
477 | expression (&new_exp); | |
478 | exp[numops].X_add_number = new_exp.X_add_number; | |
479 | } | |
252b5132 | 480 | |
e0c6ed95 | 481 | /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT. */ |
252b5132 RH |
482 | { |
483 | expressionS new_exp; | |
484 | memset (&new_exp, 0, sizeof new_exp); | |
485 | new_exp.X_add_number = AT_WORD_RIGHT_SHIFT; | |
486 | new_exp.X_op = O_constant; | |
487 | new_exp.X_unsigned = 1; | |
488 | exp[numops].X_op_symbol = make_expr_symbol (&new_exp); | |
489 | exp[numops].X_op = O_right_shift; | |
490 | } | |
491 | ||
492 | know (AT_WORD_P (&exp[numops])); | |
493 | } | |
e0c6ed95 AM |
494 | |
495 | if (exp[numops].X_op == O_illegal) | |
252b5132 | 496 | as_bad (_("illegal operand")); |
e0c6ed95 | 497 | else if (exp[numops].X_op == O_absent) |
252b5132 RH |
498 | as_bad (_("missing operand")); |
499 | ||
500 | numops++; | |
501 | p = input_line_pointer; | |
502 | } | |
503 | ||
e0c6ed95 | 504 | switch (post) |
252b5132 | 505 | { |
e0c6ed95 | 506 | case -1: /* Postdecrement mode. */ |
252b5132 RH |
507 | exp[numops].X_op = O_absent; |
508 | exp[numops++].X_add_number = OPERAND_MINUS; | |
509 | break; | |
e0c6ed95 | 510 | case 1: /* Postincrement mode. */ |
252b5132 RH |
511 | exp[numops].X_op = O_absent; |
512 | exp[numops++].X_add_number = OPERAND_PLUS; | |
513 | break; | |
514 | } | |
515 | ||
516 | exp[numops].X_op = 0; | |
ea1562b3 | 517 | return numops; |
252b5132 RH |
518 | } |
519 | ||
520 | static unsigned long | |
ea1562b3 NC |
521 | d10v_insert_operand (unsigned long insn, |
522 | int op_type, | |
523 | offsetT value, | |
524 | int left, | |
525 | fixS *fix) | |
252b5132 RH |
526 | { |
527 | int shift, bits; | |
528 | ||
529 | shift = d10v_operands[op_type].shift; | |
530 | if (left) | |
531 | shift += 15; | |
532 | ||
533 | bits = d10v_operands[op_type].bits; | |
534 | ||
e0c6ed95 | 535 | /* Truncate to the proper number of bits. */ |
252b5132 | 536 | if (check_range (value, bits, d10v_operands[op_type].flags)) |
ab3e48dc | 537 | as_bad_where (fix->fx_file, fix->fx_line, |
fbdbf472 | 538 | _("operand out of range: %ld"), (long) value); |
252b5132 RH |
539 | |
540 | value &= 0x7FFFFFFF >> (31 - bits); | |
541 | insn |= (value << shift); | |
542 | ||
543 | return insn; | |
544 | } | |
545 | ||
e0c6ed95 AM |
546 | /* Take a pointer to the opcode entry in the opcode table and the |
547 | array of operand expressions. Return the instruction. */ | |
252b5132 RH |
548 | |
549 | static unsigned long | |
ea1562b3 NC |
550 | build_insn (struct d10v_opcode *opcode, |
551 | expressionS *opers, | |
552 | unsigned long insn) | |
252b5132 RH |
553 | { |
554 | int i, bits, shift, flags, format; | |
555 | unsigned long number; | |
e0c6ed95 AM |
556 | |
557 | /* The insn argument is only used for the DIVS kludge. */ | |
252b5132 RH |
558 | if (insn) |
559 | format = LONG_R; | |
560 | else | |
561 | { | |
562 | insn = opcode->opcode; | |
563 | format = opcode->format; | |
564 | } | |
e0c6ed95 AM |
565 | |
566 | for (i = 0; opcode->operands[i]; i++) | |
252b5132 RH |
567 | { |
568 | flags = d10v_operands[opcode->operands[i]].flags; | |
569 | bits = d10v_operands[opcode->operands[i]].bits; | |
570 | shift = d10v_operands[opcode->operands[i]].shift; | |
571 | number = opers[i].X_add_number; | |
572 | ||
e0c6ed95 | 573 | if (flags & OPERAND_REG) |
252b5132 RH |
574 | { |
575 | number &= REGISTER_MASK; | |
576 | if (format == LONG_L) | |
577 | shift += 15; | |
578 | } | |
579 | ||
e0c6ed95 | 580 | if (opers[i].X_op != O_register && opers[i].X_op != O_constant) |
252b5132 | 581 | { |
e0c6ed95 | 582 | /* Now create a fixup. */ |
252b5132 RH |
583 | |
584 | if (fixups->fc >= MAX_INSN_FIXUPS) | |
585 | as_fatal (_("too many fixups")); | |
586 | ||
587 | if (AT_WORD_P (&opers[i])) | |
588 | { | |
2d2255b5 | 589 | /* Recognize XXX>>1+N aka XXX@word+N as special (AT_WORD). */ |
252b5132 RH |
590 | fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18; |
591 | opers[i].X_op = O_symbol; | |
e0c6ed95 | 592 | opers[i].X_op_symbol = NULL; /* Should free it. */ |
252b5132 RH |
593 | /* number is left shifted by AT_WORD_RIGHT_SHIFT so |
594 | that, it is aligned with the symbol's value. Later, | |
595 | BFD_RELOC_D10V_18 will right shift (symbol_value + | |
e0c6ed95 | 596 | X_add_number). */ |
252b5132 RH |
597 | number <<= AT_WORD_RIGHT_SHIFT; |
598 | opers[i].X_add_number = number; | |
599 | } | |
600 | else | |
8ade06a8 TR |
601 | { |
602 | fixups->fix[fixups->fc].reloc = | |
603 | get_reloc ((struct d10v_operand *) &d10v_operands[opcode->operands[i]]); | |
604 | ||
c03099e6 | 605 | /* Check that an immediate was passed to ops that expect one. */ |
b34976b6 | 606 | if ((flags & OPERAND_NUM) |
8ade06a8 TR |
607 | && (fixups->fix[fixups->fc].reloc == 0)) |
608 | as_bad (_("operand is not an immediate")); | |
609 | } | |
252b5132 | 610 | |
e0c6ed95 | 611 | if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 || |
252b5132 | 612 | fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18) |
e0c6ed95 | 613 | fixups->fix[fixups->fc].size = 2; |
252b5132 RH |
614 | else |
615 | fixups->fix[fixups->fc].size = 4; | |
e0c6ed95 | 616 | |
252b5132 RH |
617 | fixups->fix[fixups->fc].exp = opers[i]; |
618 | fixups->fix[fixups->fc].operand = opcode->operands[i]; | |
e0c6ed95 | 619 | fixups->fix[fixups->fc].pcrel = |
b34976b6 | 620 | (flags & OPERAND_ADDR) ? TRUE : FALSE; |
252b5132 RH |
621 | (fixups->fc)++; |
622 | } | |
b34976b6 | 623 | |
e0c6ed95 | 624 | /* Truncate to the proper number of bits. */ |
252b5132 | 625 | if ((opers[i].X_op == O_constant) && check_range (number, bits, flags)) |
fbdbf472 | 626 | as_bad (_("operand out of range: %lu"), number); |
252b5132 RH |
627 | number &= 0x7FFFFFFF >> (31 - bits); |
628 | insn = insn | (number << shift); | |
629 | } | |
630 | ||
b34976b6 AM |
631 | /* kludge: for DIVS, we need to put the operands in twice on the second |
632 | pass, format is changed to LONG_R to force the second set of operands | |
fbdbf472 | 633 | to not be shifted over 15. */ |
e0c6ed95 | 634 | if ((opcode->opcode == OPCODE_DIVS) && (format == LONG_L)) |
252b5132 | 635 | insn = build_insn (opcode, opers, insn); |
e0c6ed95 | 636 | |
252b5132 RH |
637 | return insn; |
638 | } | |
639 | ||
e0c6ed95 AM |
640 | /* Write out a long form instruction. */ |
641 | ||
252b5132 | 642 | static void |
ea1562b3 | 643 | write_long (unsigned long insn, Fixups *fx) |
252b5132 RH |
644 | { |
645 | int i, where; | |
e0c6ed95 | 646 | char *f = frag_more (4); |
252b5132 RH |
647 | |
648 | insn |= FM11; | |
649 | number_to_chars_bigendian (f, insn, 4); | |
650 | ||
e0c6ed95 | 651 | for (i = 0; i < fx->fc; i++) |
252b5132 RH |
652 | { |
653 | if (fx->fix[i].reloc) | |
e0c6ed95 AM |
654 | { |
655 | where = f - frag_now->fr_literal; | |
252b5132 RH |
656 | if (fx->fix[i].size == 2) |
657 | where += 2; | |
658 | ||
659 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) | |
e0c6ed95 | 660 | fx->fix[i].operand |= 4096; |
252b5132 RH |
661 | |
662 | fix_new_exp (frag_now, | |
663 | where, | |
664 | fx->fix[i].size, | |
665 | &(fx->fix[i].exp), | |
666 | fx->fix[i].pcrel, | |
667 | fx->fix[i].operand|2048); | |
668 | } | |
669 | } | |
670 | fx->fc = 0; | |
671 | } | |
672 | ||
e0c6ed95 | 673 | /* Write out a short form instruction by itself. */ |
252b5132 | 674 | |
252b5132 | 675 | static void |
ea1562b3 NC |
676 | write_1_short (struct d10v_opcode *opcode, |
677 | unsigned long insn, | |
678 | Fixups *fx) | |
252b5132 | 679 | { |
e0c6ed95 | 680 | char *f = frag_more (4); |
252b5132 RH |
681 | int i, where; |
682 | ||
683 | if (opcode->exec_type & PARONLY) | |
684 | as_fatal (_("Instruction must be executed in parallel with another instruction.")); | |
685 | ||
b34976b6 AM |
686 | /* The other container needs to be NOP. |
687 | According to 4.3.1: for FM=00, sub-instructions performed only by IU | |
fbdbf472 | 688 | cannot be encoded in L-container. */ |
252b5132 | 689 | if (opcode->unit == IU) |
e0c6ed95 | 690 | insn |= FM00 | (NOP << 15); /* Right container. */ |
252b5132 | 691 | else |
e0c6ed95 | 692 | insn = FM00 | (insn << 15) | NOP; /* Left container. */ |
252b5132 RH |
693 | |
694 | number_to_chars_bigendian (f, insn, 4); | |
e0c6ed95 | 695 | for (i = 0; i < fx->fc; i++) |
252b5132 RH |
696 | { |
697 | if (fx->fix[i].reloc) | |
e0c6ed95 AM |
698 | { |
699 | where = f - frag_now->fr_literal; | |
252b5132 RH |
700 | if (fx->fix[i].size == 2) |
701 | where += 2; | |
702 | ||
703 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) | |
e0c6ed95 | 704 | fx->fix[i].operand |= 4096; |
252b5132 | 705 | |
e0c6ed95 AM |
706 | /* If it's an R reloc, we may have to switch it to L. */ |
707 | if ((fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) | |
708 | && (opcode->unit != IU)) | |
252b5132 RH |
709 | fx->fix[i].operand |= 1024; |
710 | ||
711 | fix_new_exp (frag_now, | |
e0c6ed95 | 712 | where, |
252b5132 RH |
713 | fx->fix[i].size, |
714 | &(fx->fix[i].exp), | |
715 | fx->fix[i].pcrel, | |
716 | fx->fix[i].operand|2048); | |
717 | } | |
718 | } | |
719 | fx->fc = 0; | |
720 | } | |
721 | ||
ea1562b3 NC |
722 | /* Determine if there are any resource conflicts among two manually |
723 | parallelized instructions. Some of this was lifted from parallel_ok. */ | |
0a44c2b1 | 724 | |
ea1562b3 NC |
725 | static void |
726 | check_resource_conflict (struct d10v_opcode *op1, | |
727 | unsigned long insn1, | |
728 | struct d10v_opcode *op2, | |
729 | unsigned long insn2) | |
252b5132 | 730 | { |
ea1562b3 NC |
731 | int i, j, flags, mask, shift, regno; |
732 | unsigned long ins, mod[2]; | |
733 | struct d10v_opcode *op; | |
252b5132 | 734 | |
ea1562b3 NC |
735 | if ((op1->exec_type & SEQ) |
736 | || ! ((op1->exec_type & PAR) || (op1->exec_type & PARONLY))) | |
737 | { | |
738 | as_warn (_("packing conflict: %s must dispatch sequentially"), | |
739 | op1->name); | |
740 | return; | |
741 | } | |
252b5132 | 742 | |
ea1562b3 NC |
743 | if ((op2->exec_type & SEQ) |
744 | || ! ((op2->exec_type & PAR) || (op2->exec_type & PARONLY))) | |
745 | { | |
746 | as_warn (_("packing conflict: %s must dispatch sequentially"), | |
747 | op2->name); | |
748 | return; | |
749 | } | |
252b5132 | 750 | |
ea1562b3 NC |
751 | /* See if both instructions write to the same resource. |
752 | ||
753 | The idea here is to create two sets of bitmasks (mod and used) which | |
754 | indicate which registers are modified or used by each instruction. | |
755 | The operation can only be done in parallel if neither instruction | |
756 | modifies the same register. Accesses to control registers and memory | |
757 | are treated as accesses to a single register. So if both instructions | |
758 | write memory or if the first instruction writes memory and the second | |
759 | reads, then they cannot be done in parallel. We treat reads to the PSW | |
760 | (which includes C, F0, and F1) in isolation. So simultaneously writing | |
761 | C and F0 in two different sub-instructions is permitted. */ | |
762 | ||
763 | /* The bitmasks (mod and used) look like this (bit 31 = MSB). | |
764 | r0-r15 0-15 | |
765 | a0-a1 16-17 | |
766 | cr (not psw) 18 | |
767 | psw(other) 19 | |
768 | mem 20 | |
769 | psw(C flag) 21 | |
770 | psw(F0 flag) 22 */ | |
771 | ||
772 | for (j = 0; j < 2; j++) | |
252b5132 | 773 | { |
ea1562b3 | 774 | if (j == 0) |
252b5132 | 775 | { |
ea1562b3 NC |
776 | op = op1; |
777 | ins = insn1; | |
252b5132 | 778 | } |
252b5132 | 779 | else |
252b5132 | 780 | { |
ea1562b3 NC |
781 | op = op2; |
782 | ins = insn2; | |
252b5132 | 783 | } |
ea1562b3 NC |
784 | mod[j] = 0; |
785 | if (op->exec_type & BRANCH_LINK) | |
786 | mod[j] |= 1 << 13; | |
0a44c2b1 | 787 | |
ea1562b3 | 788 | for (i = 0; op->operands[i]; i++) |
252b5132 | 789 | { |
ea1562b3 NC |
790 | flags = d10v_operands[op->operands[i]].flags; |
791 | shift = d10v_operands[op->operands[i]].shift; | |
792 | mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits); | |
793 | if (flags & OPERAND_REG) | |
794 | { | |
795 | regno = (ins >> shift) & mask; | |
796 | if (flags & (OPERAND_ACC0 | OPERAND_ACC1)) | |
797 | regno += 16; | |
798 | else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */ | |
799 | { | |
800 | if (regno == 0) | |
801 | regno = 19; | |
802 | else | |
803 | regno = 18; | |
804 | } | |
805 | else if (flags & OPERAND_FFLAG) | |
806 | regno = 22; | |
807 | else if (flags & OPERAND_CFLAG) | |
808 | regno = 21; | |
0a44c2b1 | 809 | |
ea1562b3 NC |
810 | if (flags & OPERAND_DEST |
811 | /* Auto inc/dec also modifies the register. */ | |
812 | || (op->operands[i + 1] != 0 | |
813 | && (d10v_operands[op->operands[i + 1]].flags | |
814 | & (OPERAND_PLUS | OPERAND_MINUS)) != 0)) | |
815 | { | |
816 | mod[j] |= 1 << regno; | |
817 | if (flags & OPERAND_EVEN) | |
818 | mod[j] |= 1 << (regno + 1); | |
819 | } | |
820 | } | |
821 | else if (flags & OPERAND_ATMINUS) | |
822 | { | |
823 | /* SP implicitly used/modified. */ | |
824 | mod[j] |= 1 << 15; | |
825 | } | |
252b5132 | 826 | } |
0a44c2b1 | 827 | |
ea1562b3 NC |
828 | if (op->exec_type & WMEM) |
829 | mod[j] |= 1 << 20; | |
830 | else if (op->exec_type & WF0) | |
831 | mod[j] |= 1 << 22; | |
832 | else if (op->exec_type & WCAR) | |
833 | mod[j] |= 1 << 21; | |
252b5132 RH |
834 | } |
835 | ||
ea1562b3 NC |
836 | if ((mod[0] & mod[1]) == 0) |
837 | return; | |
838 | else | |
252b5132 | 839 | { |
ea1562b3 NC |
840 | unsigned long x; |
841 | x = mod[0] & mod[1]; | |
252b5132 | 842 | |
ea1562b3 NC |
843 | for (j = 0; j <= 15; j++) |
844 | if (x & (1 << j)) | |
845 | as_warn (_("resource conflict (R%d)"), j); | |
846 | for (j = 16; j <= 17; j++) | |
847 | if (x & (1 << j)) | |
848 | as_warn (_("resource conflict (A%d)"), j - 16); | |
849 | if (x & (1 << 19)) | |
850 | as_warn (_("resource conflict (PSW)")); | |
851 | if (x & (1 << 21)) | |
852 | as_warn (_("resource conflict (C flag)")); | |
853 | if (x & (1 << 22)) | |
854 | as_warn (_("resource conflict (F flag)")); | |
252b5132 | 855 | } |
252b5132 RH |
856 | } |
857 | ||
e0c6ed95 AM |
858 | /* Check 2 instructions and determine if they can be safely |
859 | executed in parallel. Return 1 if they can be. */ | |
252b5132 | 860 | |
252b5132 | 861 | static int |
ea1562b3 NC |
862 | parallel_ok (struct d10v_opcode *op1, |
863 | unsigned long insn1, | |
864 | struct d10v_opcode *op2, | |
865 | unsigned long insn2, | |
866 | packing_type exec_type) | |
252b5132 RH |
867 | { |
868 | int i, j, flags, mask, shift, regno; | |
869 | unsigned long ins, mod[2], used[2]; | |
870 | struct d10v_opcode *op; | |
871 | ||
872 | if ((op1->exec_type & SEQ) != 0 || (op2->exec_type & SEQ) != 0 | |
873 | || (op1->exec_type & PAR) == 0 || (op2->exec_type & PAR) == 0 | |
874 | || (op1->unit == BOTH) || (op2->unit == BOTH) | |
875 | || (op1->unit == IU && op2->unit == IU) | |
876 | || (op1->unit == MU && op2->unit == MU)) | |
877 | return 0; | |
878 | ||
8ade06a8 TR |
879 | /* If this is auto parallelization, and the first instruction is a |
880 | branch or should not be packed, then don't parallelize. */ | |
0a44c2b1 | 881 | if (exec_type == PACK_UNSPEC |
8ade06a8 | 882 | && (op1->exec_type & (ALONE | BRANCH))) |
252b5132 RH |
883 | return 0; |
884 | ||
885 | /* The idea here is to create two sets of bitmasks (mod and used) | |
886 | which indicate which registers are modified or used by each | |
887 | instruction. The operation can only be done in parallel if | |
888 | instruction 1 and instruction 2 modify different registers, and | |
889 | the first instruction does not modify registers that the second | |
890 | is using (The second instruction can modify registers that the | |
891 | first is using as they are only written back after the first | |
892 | instruction has completed). Accesses to control registers, PSW, | |
893 | and memory are treated as accesses to a single register. So if | |
894 | both instructions write memory or if the first instruction writes | |
895 | memory and the second reads, then they cannot be done in | |
896 | parallel. Likewise, if the first instruction mucks with the psw | |
897 | and the second reads the PSW (which includes C, F0, and F1), then | |
e0c6ed95 | 898 | they cannot operate safely in parallel. */ |
252b5132 | 899 | |
b34976b6 AM |
900 | /* The bitmasks (mod and used) look like this (bit 31 = MSB). |
901 | r0-r15 0-15 | |
fbdbf472 TR |
902 | a0-a1 16-17 |
903 | cr (not psw) 18 | |
904 | psw 19 | |
905 | mem 20 */ | |
252b5132 | 906 | |
e0c6ed95 | 907 | for (j = 0; j < 2; j++) |
252b5132 RH |
908 | { |
909 | if (j == 0) | |
910 | { | |
911 | op = op1; | |
912 | ins = insn1; | |
913 | } | |
914 | else | |
915 | { | |
916 | op = op2; | |
917 | ins = insn2; | |
918 | } | |
919 | mod[j] = used[j] = 0; | |
920 | if (op->exec_type & BRANCH_LINK) | |
921 | mod[j] |= 1 << 13; | |
922 | ||
923 | for (i = 0; op->operands[i]; i++) | |
924 | { | |
925 | flags = d10v_operands[op->operands[i]].flags; | |
926 | shift = d10v_operands[op->operands[i]].shift; | |
927 | mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits); | |
928 | if (flags & OPERAND_REG) | |
929 | { | |
930 | regno = (ins >> shift) & mask; | |
e0c6ed95 | 931 | if (flags & (OPERAND_ACC0 | OPERAND_ACC1)) |
252b5132 | 932 | regno += 16; |
e0c6ed95 AM |
933 | else if (flags & OPERAND_CONTROL) /* mvtc or mvfc. */ |
934 | { | |
252b5132 RH |
935 | if (regno == 0) |
936 | regno = 19; | |
937 | else | |
e0c6ed95 | 938 | regno = 18; |
252b5132 | 939 | } |
e0c6ed95 | 940 | else if (flags & (OPERAND_FFLAG | OPERAND_CFLAG)) |
252b5132 | 941 | regno = 19; |
e0c6ed95 AM |
942 | |
943 | if (flags & OPERAND_DEST) | |
252b5132 RH |
944 | { |
945 | mod[j] |= 1 << regno; | |
946 | if (flags & OPERAND_EVEN) | |
947 | mod[j] |= 1 << (regno + 1); | |
948 | } | |
949 | else | |
950 | { | |
e0c6ed95 | 951 | used[j] |= 1 << regno; |
252b5132 RH |
952 | if (flags & OPERAND_EVEN) |
953 | used[j] |= 1 << (regno + 1); | |
954 | ||
955 | /* Auto inc/dec also modifies the register. */ | |
e0c6ed95 AM |
956 | if (op->operands[i + 1] != 0 |
957 | && (d10v_operands[op->operands[i + 1]].flags | |
252b5132 RH |
958 | & (OPERAND_PLUS | OPERAND_MINUS)) != 0) |
959 | mod[j] |= 1 << regno; | |
960 | } | |
961 | } | |
962 | else if (flags & OPERAND_ATMINUS) | |
963 | { | |
e0c6ed95 | 964 | /* SP implicitly used/modified. */ |
252b5132 RH |
965 | mod[j] |= 1 << 15; |
966 | used[j] |= 1 << 15; | |
967 | } | |
968 | } | |
969 | if (op->exec_type & RMEM) | |
970 | used[j] |= 1 << 20; | |
971 | else if (op->exec_type & WMEM) | |
972 | mod[j] |= 1 << 20; | |
973 | else if (op->exec_type & RF0) | |
974 | used[j] |= 1 << 19; | |
975 | else if (op->exec_type & WF0) | |
976 | mod[j] |= 1 << 19; | |
977 | else if (op->exec_type & WCAR) | |
978 | mod[j] |= 1 << 19; | |
979 | } | |
980 | if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0) | |
981 | return 1; | |
982 | return 0; | |
983 | } | |
984 | ||
ea1562b3 NC |
985 | /* Expects two short instructions. |
986 | If possible, writes out both as a single packed instruction. | |
987 | Otherwise, writes out the first one, packed with a NOP. | |
988 | Returns number of instructions not written out. */ | |
fbdbf472 | 989 | |
ea1562b3 NC |
990 | static int |
991 | write_2_short (struct d10v_opcode *opcode1, | |
992 | unsigned long insn1, | |
993 | struct d10v_opcode *opcode2, | |
994 | unsigned long insn2, | |
995 | packing_type exec_type, | |
996 | Fixups *fx) | |
997 | { | |
998 | unsigned long insn; | |
999 | char *f; | |
1000 | int i, j, where; | |
8ade06a8 | 1001 | |
ea1562b3 NC |
1002 | if ((exec_type != PACK_PARALLEL) |
1003 | && ((opcode1->exec_type & PARONLY) || (opcode2->exec_type & PARONLY))) | |
1004 | as_fatal (_("Instruction must be executed in parallel")); | |
fbdbf472 | 1005 | |
ea1562b3 NC |
1006 | if ((opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE)) |
1007 | as_fatal (_("Long instructions may not be combined.")); | |
fbdbf472 | 1008 | |
ea1562b3 | 1009 | switch (exec_type) |
fbdbf472 | 1010 | { |
ea1562b3 NC |
1011 | case PACK_UNSPEC: /* Order not specified. */ |
1012 | if (opcode1->exec_type & ALONE) | |
fbdbf472 | 1013 | { |
ea1562b3 NC |
1014 | /* Case of a short branch on a separate GAS line. Pack with NOP. */ |
1015 | write_1_short (opcode1, insn1, fx->next); | |
1016 | return 1; | |
fbdbf472 | 1017 | } |
ea1562b3 NC |
1018 | if (Optimizing |
1019 | && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) | |
fbdbf472 | 1020 | { |
ea1562b3 NC |
1021 | /* Parallel. */ |
1022 | if (opcode1->unit == IU) | |
1023 | insn = FM00 | (insn2 << 15) | insn1; | |
1024 | else if (opcode2->unit == MU) | |
1025 | insn = FM00 | (insn2 << 15) | insn1; | |
1026 | else | |
1027 | insn = FM00 | (insn1 << 15) | insn2; | |
fbdbf472 | 1028 | } |
ea1562b3 NC |
1029 | else if (opcode1->unit == IU) |
1030 | /* Reverse sequential with IU opcode1 on right and done first. */ | |
1031 | insn = FM10 | (insn2 << 15) | insn1; | |
252b5132 | 1032 | else |
ea1562b3 NC |
1033 | /* Sequential with non-IU opcode1 on left and done first. */ |
1034 | insn = FM01 | (insn1 << 15) | insn2; | |
1035 | break; | |
1036 | ||
1037 | case PACK_PARALLEL: | |
1038 | if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ) | |
1039 | as_fatal | |
1040 | (_("One of these instructions may not be executed in parallel.")); | |
1041 | if (opcode1->unit == IU) | |
252b5132 | 1042 | { |
ea1562b3 NC |
1043 | if (opcode2->unit == IU) |
1044 | as_fatal (_("Two IU instructions may not be executed in parallel")); | |
1045 | if (!flag_warn_suppress_instructionswap) | |
1046 | as_warn (_("Swapping instruction order")); | |
1047 | insn = FM00 | (insn2 << 15) | insn1; | |
252b5132 | 1048 | } |
ea1562b3 | 1049 | else if (opcode2->unit == MU) |
252b5132 | 1050 | { |
ea1562b3 NC |
1051 | if (opcode1->unit == MU) |
1052 | as_fatal (_("Two MU instructions may not be executed in parallel")); | |
1053 | if (!flag_warn_suppress_instructionswap) | |
1054 | as_warn (_("Swapping instruction order")); | |
1055 | insn = FM00 | (insn2 << 15) | insn1; | |
252b5132 | 1056 | } |
ea1562b3 NC |
1057 | else |
1058 | insn = FM00 | (insn1 << 15) | insn2; | |
1059 | check_resource_conflict (opcode1, insn1, opcode2, insn2); | |
1060 | break; | |
252b5132 | 1061 | |
ea1562b3 NC |
1062 | case PACK_LEFT_RIGHT: |
1063 | if (opcode1->unit != IU) | |
1064 | insn = FM01 | (insn1 << 15) | insn2; | |
1065 | else if (opcode2->unit == MU || opcode2->unit == EITHER) | |
252b5132 | 1066 | { |
ea1562b3 NC |
1067 | if (!flag_warn_suppress_instructionswap) |
1068 | as_warn (_("Swapping instruction order")); | |
1069 | insn = FM10 | (insn2 << 15) | insn1; | |
252b5132 | 1070 | } |
ea1562b3 NC |
1071 | else |
1072 | as_fatal (_("IU instruction may not be in the left container")); | |
1073 | if (opcode1->exec_type & ALONE) | |
1074 | as_warn (_("Instruction in R container is squashed by flow control instruction in L container.")); | |
1075 | break; | |
e0c6ed95 | 1076 | |
ea1562b3 NC |
1077 | case PACK_RIGHT_LEFT: |
1078 | if (opcode2->unit != MU) | |
1079 | insn = FM10 | (insn1 << 15) | insn2; | |
1080 | else if (opcode1->unit == IU || opcode1->unit == EITHER) | |
1081 | { | |
1082 | if (!flag_warn_suppress_instructionswap) | |
1083 | as_warn (_("Swapping instruction order")); | |
1084 | insn = FM01 | (insn2 << 15) | insn1; | |
1085 | } | |
1086 | else | |
1087 | as_fatal (_("MU instruction may not be in the right container")); | |
1088 | if (opcode2->exec_type & ALONE) | |
1089 | as_warn (_("Instruction in R container is squashed by flow control instruction in L container.")); | |
1090 | break; | |
252b5132 | 1091 | |
ea1562b3 NC |
1092 | default: |
1093 | as_fatal (_("unknown execution type passed to write_2_short()")); | |
1094 | } | |
252b5132 | 1095 | |
ea1562b3 NC |
1096 | f = frag_more (4); |
1097 | number_to_chars_bigendian (f, insn, 4); | |
252b5132 | 1098 | |
ea1562b3 NC |
1099 | /* Process fixup chains. fx refers to insn2 when j == 0, and to |
1100 | insn1 when j == 1. Yes, it's reversed. */ | |
252b5132 | 1101 | |
ea1562b3 | 1102 | for (j = 0; j < 2; j++) |
252b5132 | 1103 | { |
ea1562b3 NC |
1104 | for (i = 0; i < fx->fc; i++) |
1105 | { | |
1106 | if (fx->fix[i].reloc) | |
1107 | { | |
1108 | where = f - frag_now->fr_literal; | |
1109 | if (fx->fix[i].size == 2) | |
1110 | where += 2; | |
e0c6ed95 | 1111 | |
ea1562b3 NC |
1112 | if (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R |
1113 | /* A BFD_RELOC_D10V_10_PCREL_R relocation applied to | |
1114 | the instruction in the L container has to be | |
1115 | adjusted to BDF_RELOC_D10V_10_PCREL_L. When | |
1116 | j==0, we're processing insn2's operands, so we | |
1117 | want to mark the operand if insn2 is *not* in the | |
1118 | R container. When j==1, we're processing insn1's | |
1119 | operands, so we want to mark the operand if insn2 | |
1120 | *is* in the R container. Note that, if two | |
1121 | instructions are identical, we're never going to | |
1122 | swap them, so the test is safe. */ | |
1123 | && j == ((insn & 0x7fff) == insn2)) | |
1124 | fx->fix[i].operand |= 1024; | |
252b5132 | 1125 | |
ea1562b3 NC |
1126 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) |
1127 | fx->fix[i].operand |= 4096; | |
252b5132 | 1128 | |
ea1562b3 NC |
1129 | fix_new_exp (frag_now, |
1130 | where, | |
1131 | fx->fix[i].size, | |
1132 | &(fx->fix[i].exp), | |
1133 | fx->fix[i].pcrel, | |
1134 | fx->fix[i].operand|2048); | |
1135 | } | |
1136 | } | |
1137 | fx->fc = 0; | |
1138 | fx = fx->next; | |
1139 | } | |
1140 | return 0; | |
252b5132 RH |
1141 | } |
1142 | ||
ea1562b3 NC |
1143 | /* This is the main entry point for the machine-dependent assembler. |
1144 | str points to a machine-dependent instruction. This function is | |
1145 | supposed to emit the frags/bytes it assembles to. For the D10V, it | |
1146 | mostly handles the special VLIW parsing and packing and leaves the | |
1147 | difficult stuff to do_assemble(). */ | |
1148 | ||
1149 | static unsigned long prev_insn; | |
1150 | static struct d10v_opcode *prev_opcode = 0; | |
1151 | static subsegT prev_subseg; | |
1152 | static segT prev_seg = 0;; | |
1153 | ||
fbdbf472 | 1154 | /* Find the symbol which has the same name as the register in exp. */ |
e0c6ed95 | 1155 | |
252b5132 | 1156 | static symbolS * |
ea1562b3 | 1157 | find_symbol_matching_register (expressionS *exp) |
252b5132 RH |
1158 | { |
1159 | int i; | |
e0c6ed95 | 1160 | |
252b5132 RH |
1161 | if (exp->X_op != O_register) |
1162 | return NULL; | |
e0c6ed95 | 1163 | |
252b5132 RH |
1164 | /* Find the name of the register. */ |
1165 | for (i = d10v_reg_name_cnt (); i--;) | |
e0c6ed95 | 1166 | if (d10v_predefined_registers[i].value == exp->X_add_number) |
252b5132 RH |
1167 | break; |
1168 | ||
1169 | if (i < 0) | |
1170 | abort (); | |
1171 | ||
1172 | /* Now see if a symbol has been defined with the same name. */ | |
e0c6ed95 | 1173 | return symbol_find (d10v_predefined_registers[i].name); |
252b5132 RH |
1174 | } |
1175 | ||
e0c6ed95 AM |
1176 | /* Get a pointer to an entry in the opcode table. |
1177 | The function must look at all opcodes with the same name and use | |
1178 | the operands to choose the correct opcode. */ | |
252b5132 RH |
1179 | |
1180 | static struct d10v_opcode * | |
ea1562b3 | 1181 | find_opcode (struct d10v_opcode *opcode, expressionS myops[]) |
252b5132 | 1182 | { |
bccba5f0 | 1183 | int i, match; |
252b5132 RH |
1184 | struct d10v_opcode *next_opcode; |
1185 | ||
e0c6ed95 | 1186 | /* Get all the operands and save them as expressions. */ |
252b5132 RH |
1187 | get_operands (myops); |
1188 | ||
e0c6ed95 AM |
1189 | /* Now see if the operand is a fake. If so, find the correct size |
1190 | instruction, if possible. */ | |
252b5132 RH |
1191 | if (opcode->format == OPCODE_FAKE) |
1192 | { | |
1193 | int opnum = opcode->operands[0]; | |
1194 | int flags; | |
e0c6ed95 | 1195 | |
252b5132 RH |
1196 | if (myops[opnum].X_op == O_register) |
1197 | { | |
1198 | myops[opnum].X_op = O_symbol; | |
e0c6ed95 AM |
1199 | myops[opnum].X_add_symbol = |
1200 | symbol_find_or_make ((char *) myops[opnum].X_op_symbol); | |
252b5132 RH |
1201 | myops[opnum].X_add_number = 0; |
1202 | myops[opnum].X_op_symbol = NULL; | |
1203 | } | |
1204 | ||
e0c6ed95 | 1205 | next_opcode = opcode + 1; |
252b5132 RH |
1206 | |
1207 | /* If the first operand is supposed to be a register, make sure | |
1208 | we got a valid one. */ | |
1209 | flags = d10v_operands[next_opcode->operands[0]].flags; | |
1210 | if (flags & OPERAND_REG) | |
1211 | { | |
1212 | int X_op = myops[0].X_op; | |
1213 | int num = myops[0].X_add_number; | |
1214 | ||
1215 | if (X_op != O_register | |
1216 | || (num & ~flags | |
1217 | & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 | |
55aa1bc4 AO |
1218 | | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL)) |
1219 | || ((flags & OPERAND_SP) && ! (num & OPERAND_SP))) | |
252b5132 RH |
1220 | { |
1221 | as_bad (_("bad opcode or operands")); | |
1222 | return 0; | |
1223 | } | |
1224 | } | |
1225 | ||
e0c6ed95 AM |
1226 | if (myops[opnum].X_op == O_constant |
1227 | || (myops[opnum].X_op == O_symbol | |
1228 | && S_IS_DEFINED (myops[opnum].X_add_symbol) | |
1229 | && (S_GET_SEGMENT (myops[opnum].X_add_symbol) == now_seg))) | |
252b5132 | 1230 | { |
e0c6ed95 | 1231 | for (i = 0; opcode->operands[i + 1]; i++) |
252b5132 RH |
1232 | { |
1233 | int bits = d10v_operands[next_opcode->operands[opnum]].bits; | |
1234 | int flags = d10v_operands[next_opcode->operands[opnum]].flags; | |
1235 | if (flags & OPERAND_ADDR) | |
1236 | bits += 2; | |
e0c6ed95 | 1237 | |
252b5132 RH |
1238 | if (myops[opnum].X_op == O_constant) |
1239 | { | |
1240 | if (!check_range (myops[opnum].X_add_number, bits, flags)) | |
fbdbf472 | 1241 | break; |
252b5132 RH |
1242 | } |
1243 | else | |
1244 | { | |
e0c6ed95 AM |
1245 | fragS *sym_frag; |
1246 | fragS *f; | |
3db10f32 NC |
1247 | unsigned long current_position; |
1248 | unsigned long symbol_position; | |
1249 | unsigned long value; | |
b34976b6 | 1250 | bfd_boolean found_symbol; |
e0c6ed95 | 1251 | |
3db10f32 NC |
1252 | /* Calculate the address of the current instruction |
1253 | and the address of the symbol. Do this by summing | |
1254 | the offsets of previous frags until we reach the | |
1255 | frag containing the symbol, and the current frag. */ | |
1256 | sym_frag = symbol_get_frag (myops[opnum].X_add_symbol); | |
b34976b6 | 1257 | found_symbol = FALSE; |
3db10f32 | 1258 | |
e0c6ed95 AM |
1259 | current_position = |
1260 | obstack_next_free (&frchain_now->frch_obstack) | |
1261 | - frag_now->fr_literal; | |
3db10f32 | 1262 | symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol); |
e0c6ed95 | 1263 | |
3db10f32 NC |
1264 | for (f = frchain_now->frch_root; f; f = f->fr_next) |
1265 | { | |
1266 | current_position += f->fr_fix + f->fr_offset; | |
e0c6ed95 | 1267 | |
3db10f32 | 1268 | if (f == sym_frag) |
b34976b6 | 1269 | found_symbol = TRUE; |
e0c6ed95 | 1270 | |
3db10f32 NC |
1271 | if (! found_symbol) |
1272 | symbol_position += f->fr_fix + f->fr_offset; | |
1273 | } | |
252b5132 | 1274 | |
3db10f32 | 1275 | value = symbol_position; |
e0c6ed95 | 1276 | |
252b5132 | 1277 | if (flags & OPERAND_ADDR) |
3db10f32 | 1278 | value -= current_position; |
e0c6ed95 | 1279 | |
252b5132 RH |
1280 | if (AT_WORD_P (&myops[opnum])) |
1281 | { | |
1282 | if (bits > 4) | |
1283 | { | |
1284 | bits += 2; | |
1285 | if (!check_range (value, bits, flags)) | |
fbdbf472 | 1286 | break; |
252b5132 RH |
1287 | } |
1288 | } | |
1289 | else if (!check_range (value, bits, flags)) | |
fbdbf472 | 1290 | break; |
252b5132 RH |
1291 | } |
1292 | next_opcode++; | |
1293 | } | |
fbdbf472 TR |
1294 | |
1295 | if (opcode->operands [i + 1] == 0) | |
1296 | as_fatal (_("value out of range")); | |
1297 | else | |
1298 | opcode = next_opcode; | |
252b5132 RH |
1299 | } |
1300 | else | |
ea1562b3 NC |
1301 | /* Not a constant, so use a long instruction. */ |
1302 | opcode += 2; | |
252b5132 | 1303 | } |
fbdbf472 TR |
1304 | |
1305 | match = 0; | |
b34976b6 | 1306 | |
fbdbf472 TR |
1307 | /* Now search the opcode table table for one with operands |
1308 | that matches what we've got. */ | |
1309 | while (!match) | |
252b5132 | 1310 | { |
fbdbf472 TR |
1311 | match = 1; |
1312 | for (i = 0; opcode->operands[i]; i++) | |
252b5132 | 1313 | { |
fbdbf472 TR |
1314 | int flags = d10v_operands[opcode->operands[i]].flags; |
1315 | int X_op = myops[i].X_op; | |
1316 | int num = myops[i].X_add_number; | |
1317 | ||
1318 | if (X_op == 0) | |
252b5132 | 1319 | { |
fbdbf472 TR |
1320 | match = 0; |
1321 | break; | |
1322 | } | |
252b5132 | 1323 | |
fbdbf472 TR |
1324 | if (flags & OPERAND_REG) |
1325 | { | |
1326 | if ((X_op != O_register) | |
1327 | || (num & ~flags | |
1328 | & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 | |
1329 | | OPERAND_FFLAG | OPERAND_CFLAG | |
1330 | | OPERAND_CONTROL)) | |
1331 | || ((flags & OPERAND_SP) && ! (num & OPERAND_SP))) | |
252b5132 RH |
1332 | { |
1333 | match = 0; | |
1334 | break; | |
1335 | } | |
fbdbf472 | 1336 | } |
e0c6ed95 | 1337 | |
fbdbf472 TR |
1338 | if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) || |
1339 | ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) || | |
1340 | ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) || | |
1341 | ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) || | |
1342 | ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || ((num != OPERAND_ATSIGN) && (num != OPERAND_ATPAR))))) | |
1343 | { | |
1344 | match = 0; | |
1345 | break; | |
1346 | } | |
e0c6ed95 | 1347 | |
2d2255b5 | 1348 | /* Unfortunately, for the indirect operand in instructions such |
b34976b6 AM |
1349 | as ``ldb r1, @(c,r14)'' this function can be passed |
1350 | X_op == O_register (because 'c' is a valid register name). | |
1351 | However we cannot just ignore the case when X_op == O_register | |
1352 | but flags & OPERAND_REG is null, so we check to see if a symbol | |
1353 | of the same name as the register exists. If the symbol does | |
1354 | exist, then the parser was unable to distinguish the two cases | |
fbdbf472 | 1355 | and we fix things here. (Ref: PR14826) */ |
e0c6ed95 | 1356 | |
fbdbf472 TR |
1357 | if (!(flags & OPERAND_REG) && (X_op == O_register)) |
1358 | { | |
1359 | symbolS * sym; | |
b34976b6 | 1360 | |
fbdbf472 | 1361 | sym = find_symbol_matching_register (& myops[i]); |
e0c6ed95 | 1362 | |
fbdbf472 TR |
1363 | if (sym != NULL) |
1364 | { | |
1365 | myops[i].X_op = X_op = O_symbol; | |
1366 | myops[i].X_add_symbol = sym; | |
252b5132 | 1367 | } |
fbdbf472 TR |
1368 | else |
1369 | as_bad | |
1370 | (_("illegal operand - register name found where none expected")); | |
252b5132 | 1371 | } |
fbdbf472 | 1372 | } |
e0c6ed95 | 1373 | |
fbdbf472 | 1374 | /* We're only done if the operands matched so far AND there |
252b5132 | 1375 | are no more to check. */ |
fbdbf472 TR |
1376 | if (match && myops[i].X_op == 0) |
1377 | break; | |
1378 | else | |
1379 | match = 0; | |
252b5132 | 1380 | |
fbdbf472 | 1381 | next_opcode = opcode + 1; |
e0c6ed95 | 1382 | |
fbdbf472 TR |
1383 | if (next_opcode->opcode == 0) |
1384 | break; | |
e0c6ed95 | 1385 | |
fbdbf472 TR |
1386 | if (strcmp (next_opcode->name, opcode->name)) |
1387 | break; | |
e0c6ed95 | 1388 | |
fbdbf472 | 1389 | opcode = next_opcode; |
252b5132 RH |
1390 | } |
1391 | ||
e0c6ed95 | 1392 | if (!match) |
252b5132 RH |
1393 | { |
1394 | as_bad (_("bad opcode or operands")); | |
ea1562b3 | 1395 | return 0; |
252b5132 RH |
1396 | } |
1397 | ||
e0c6ed95 AM |
1398 | /* Check that all registers that are required to be even are. |
1399 | Also, if any operands were marked as registers, but were really symbols, | |
1400 | fix that here. */ | |
1401 | for (i = 0; opcode->operands[i]; i++) | |
252b5132 RH |
1402 | { |
1403 | if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) && | |
e0c6ed95 | 1404 | (myops[i].X_add_number & 1)) |
252b5132 | 1405 | as_fatal (_("Register number must be EVEN")); |
461448d8 AO |
1406 | if ((d10v_operands[opcode->operands[i]].flags & OPERAND_NOSP) |
1407 | && (myops[i].X_add_number & OPERAND_SP)) | |
1408 | as_bad (_("Unsupported use of sp")); | |
252b5132 RH |
1409 | if (myops[i].X_op == O_register) |
1410 | { | |
e0c6ed95 | 1411 | if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG)) |
252b5132 RH |
1412 | { |
1413 | myops[i].X_op = O_symbol; | |
e0c6ed95 AM |
1414 | myops[i].X_add_symbol = |
1415 | symbol_find_or_make ((char *) myops[i].X_op_symbol); | |
252b5132 RH |
1416 | myops[i].X_add_number = 0; |
1417 | myops[i].X_op_symbol = NULL; | |
1418 | } | |
1419 | } | |
fbdbf472 TR |
1420 | if ((d10v_operands[opcode->operands[i]].flags & OPERAND_CONTROL) |
1421 | && (myops[i].X_add_number == OPERAND_CONTROL + 4 | |
1422 | || myops[i].X_add_number == OPERAND_CONTROL + 5 | |
1423 | || myops[i].X_add_number == OPERAND_CONTROL + 6 | |
1424 | || myops[i].X_add_number == OPERAND_CONTROL + 12 | |
1425 | || myops[i].X_add_number == OPERAND_CONTROL + 13 | |
1426 | || myops[i].X_add_number == OPERAND_CONTROL + 15)) | |
1427 | as_warn (_("cr%ld is a reserved control register"), | |
1428 | myops[i].X_add_number - OPERAND_CONTROL); | |
252b5132 RH |
1429 | } |
1430 | return opcode; | |
1431 | } | |
1432 | ||
ea1562b3 NC |
1433 | /* Assemble a single instruction. |
1434 | Return an opcode, or -1 (an invalid opcode) on error. */ | |
1435 | ||
1436 | static unsigned long | |
1437 | do_assemble (char *str, struct d10v_opcode **opcode) | |
1438 | { | |
1439 | unsigned char *op_start, *op_end; | |
1440 | char *save; | |
1441 | char name[20]; | |
1442 | int nlen = 0; | |
1443 | expressionS myops[6]; | |
1444 | unsigned long insn; | |
1445 | ||
1446 | /* Drop leading whitespace. */ | |
1447 | while (*str == ' ') | |
1448 | str++; | |
1449 | ||
1450 | /* Find the opcode end. */ | |
1451 | for (op_start = op_end = (unsigned char *) str; | |
1452 | *op_end && nlen < 20 && !is_end_of_line[*op_end] && *op_end != ' '; | |
1453 | op_end++) | |
1454 | { | |
1455 | name[nlen] = TOLOWER (op_start[nlen]); | |
1456 | nlen++; | |
1457 | } | |
1458 | name[nlen] = 0; | |
1459 | ||
1460 | if (nlen == 0) | |
1461 | return -1; | |
1462 | ||
1463 | /* Find the first opcode with the proper name. */ | |
1464 | *opcode = (struct d10v_opcode *) hash_find (d10v_hash, name); | |
1465 | if (*opcode == NULL) | |
1466 | as_fatal (_("unknown opcode: %s"), name); | |
1467 | ||
1468 | save = input_line_pointer; | |
1469 | input_line_pointer = (char *) op_end; | |
1470 | *opcode = find_opcode (*opcode, myops); | |
1471 | if (*opcode == 0) | |
1472 | return -1; | |
1473 | input_line_pointer = save; | |
1474 | ||
1475 | insn = build_insn ((*opcode), myops, 0); | |
1476 | return insn; | |
1477 | } | |
1478 | ||
e0c6ed95 AM |
1479 | /* If while processing a fixup, a reloc really needs to be created. |
1480 | Then it is done here. */ | |
1481 | ||
252b5132 | 1482 | arelent * |
ea1562b3 | 1483 | tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
1484 | { |
1485 | arelent *reloc; | |
ea1562b3 NC |
1486 | reloc = xmalloc (sizeof (arelent)); |
1487 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); | |
310b5aa2 | 1488 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
1489 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
1490 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
1491 | if (reloc->howto == (reloc_howto_type *) NULL) | |
1492 | { | |
1493 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
e0c6ed95 AM |
1494 | _("reloc %d not supported by object file format"), |
1495 | (int) fixp->fx_r_type); | |
252b5132 RH |
1496 | return NULL; |
1497 | } | |
1498 | ||
a161fe53 | 1499 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
252b5132 | 1500 | reloc->address = fixp->fx_offset; |
cc8a6dd0 | 1501 | |
a161fe53 | 1502 | reloc->addend = 0; |
cc8a6dd0 | 1503 | |
252b5132 RH |
1504 | return reloc; |
1505 | } | |
1506 | ||
1507 | int | |
ea1562b3 NC |
1508 | md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, |
1509 | asection *seg ATTRIBUTE_UNUSED) | |
252b5132 RH |
1510 | { |
1511 | abort (); | |
1512 | return 0; | |
e0c6ed95 | 1513 | } |
252b5132 RH |
1514 | |
1515 | long | |
ea1562b3 | 1516 | md_pcrel_from_section (fixS *fixp, segT sec) |
252b5132 | 1517 | { |
e0c6ed95 AM |
1518 | if (fixp->fx_addsy != (symbolS *) NULL |
1519 | && (!S_IS_DEFINED (fixp->fx_addsy) | |
1520 | || (S_GET_SEGMENT (fixp->fx_addsy) != sec))) | |
252b5132 RH |
1521 | return 0; |
1522 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
1523 | } | |
1524 | ||
94f592af | 1525 | void |
ea1562b3 | 1526 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 RH |
1527 | { |
1528 | char *where; | |
1529 | unsigned long insn; | |
a161fe53 | 1530 | long value = *valP; |
252b5132 | 1531 | int op_type; |
e0c6ed95 | 1532 | int left = 0; |
252b5132 | 1533 | |
94f592af NC |
1534 | if (fixP->fx_addsy == (symbolS *) NULL) |
1535 | fixP->fx_done = 1; | |
1536 | ||
a161fe53 AM |
1537 | /* We don't actually support subtracting a symbol. */ |
1538 | if (fixP->fx_subsy != (symbolS *) NULL) | |
1539 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
252b5132 | 1540 | |
94f592af | 1541 | op_type = fixP->fx_r_type; |
252b5132 RH |
1542 | if (op_type & 2048) |
1543 | { | |
1544 | op_type -= 2048; | |
1545 | if (op_type & 1024) | |
1546 | { | |
1547 | op_type -= 1024; | |
94f592af | 1548 | fixP->fx_r_type = BFD_RELOC_D10V_10_PCREL_L; |
252b5132 RH |
1549 | left = 1; |
1550 | } | |
1551 | else if (op_type & 4096) | |
1552 | { | |
1553 | op_type -= 4096; | |
94f592af | 1554 | fixP->fx_r_type = BFD_RELOC_D10V_18; |
252b5132 RH |
1555 | } |
1556 | else | |
94f592af | 1557 | fixP->fx_r_type = |
e0c6ed95 | 1558 | get_reloc ((struct d10v_operand *) &d10v_operands[op_type]); |
252b5132 RH |
1559 | } |
1560 | ||
1561 | /* Fetch the instruction, insert the fully resolved operand | |
1562 | value, and stuff the instruction back again. */ | |
94f592af | 1563 | where = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
1564 | insn = bfd_getb32 ((unsigned char *) where); |
1565 | ||
94f592af | 1566 | switch (fixP->fx_r_type) |
252b5132 RH |
1567 | { |
1568 | case BFD_RELOC_D10V_10_PCREL_L: | |
1569 | case BFD_RELOC_D10V_10_PCREL_R: | |
1570 | case BFD_RELOC_D10V_18_PCREL: | |
fbdbf472 TR |
1571 | /* If the fix is relative to a global symbol, not a section |
1572 | symbol, then ignore the offset. | |
1573 | XXX - Do we have to worry about branches to a symbol + offset ? */ | |
1574 | if (fixP->fx_addsy != NULL | |
e97b3f28 | 1575 | && S_IS_EXTERNAL (fixP->fx_addsy) ) |
8ade06a8 TR |
1576 | { |
1577 | segT fseg = S_GET_SEGMENT (fixP->fx_addsy); | |
1578 | segment_info_type *segf = seg_info(fseg); | |
fbdbf472 TR |
1579 | |
1580 | if ( segf && segf->sym != fixP->fx_addsy) | |
1581 | value = 0; | |
8ade06a8 | 1582 | } |
fbdbf472 | 1583 | /* Drop through. */ |
252b5132 | 1584 | case BFD_RELOC_D10V_18: |
e0c6ed95 | 1585 | /* Instruction addresses are always right-shifted by 2. */ |
252b5132 | 1586 | value >>= AT_WORD_RIGHT_SHIFT; |
94f592af | 1587 | if (fixP->fx_size == 2) |
252b5132 RH |
1588 | bfd_putb16 ((bfd_vma) value, (unsigned char *) where); |
1589 | else | |
1590 | { | |
1591 | struct d10v_opcode *rep, *repi; | |
1592 | ||
1593 | rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep"); | |
1594 | repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi"); | |
1595 | if ((insn & FM11) == FM11 | |
b34976b6 | 1596 | && ((repi != NULL |
fbdbf472 | 1597 | && (insn & repi->mask) == (unsigned) repi->opcode) |
b34976b6 | 1598 | || (rep != NULL |
fbdbf472 | 1599 | && (insn & rep->mask) == (unsigned) rep->opcode)) |
252b5132 RH |
1600 | && value < 4) |
1601 | as_fatal | |
1602 | (_("line %d: rep or repi must include at least 4 instructions"), | |
94f592af | 1603 | fixP->fx_line); |
e0c6ed95 | 1604 | insn = |
94f592af | 1605 | d10v_insert_operand (insn, op_type, (offsetT) value, left, fixP); |
e0c6ed95 | 1606 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); |
252b5132 RH |
1607 | } |
1608 | break; | |
1609 | case BFD_RELOC_32: | |
1610 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); | |
1611 | break; | |
1612 | case BFD_RELOC_16: | |
1613 | bfd_putb16 ((bfd_vma) value, (unsigned char *) where); | |
1614 | break; | |
1615 | ||
1616 | case BFD_RELOC_VTABLE_INHERIT: | |
1617 | case BFD_RELOC_VTABLE_ENTRY: | |
94f592af NC |
1618 | fixP->fx_done = 0; |
1619 | return; | |
252b5132 RH |
1620 | |
1621 | default: | |
e0c6ed95 | 1622 | as_fatal (_("line %d: unknown relocation type: 0x%x"), |
94f592af | 1623 | fixP->fx_line, fixP->fx_r_type); |
252b5132 | 1624 | } |
252b5132 RH |
1625 | } |
1626 | ||
bccba5f0 NC |
1627 | /* d10v_cleanup() is called after the assembler has finished parsing |
1628 | the input file, when a label is read from the input file, or when a | |
1629 | stab directive is output. Because the D10V assembler sometimes | |
e0c6ed95 AM |
1630 | saves short instructions to see if it can package them with the |
1631 | next instruction, there may be a short instruction that still needs | |
1632 | to be written. | |
1633 | ||
0a44c2b1 DL |
1634 | NOTE: accesses a global, etype. |
1635 | NOTE: invoked by various macros such as md_cleanup: see. */ | |
e0c6ed95 | 1636 | |
252b5132 | 1637 | int |
ea1562b3 | 1638 | d10v_cleanup (void) |
252b5132 RH |
1639 | { |
1640 | segT seg; | |
1641 | subsegT subseg; | |
1642 | ||
bccba5f0 NC |
1643 | /* If cleanup was invoked because the assembler encountered, e.g., a |
1644 | user label, we write out the pending instruction, if any. If it | |
1645 | was invoked because the assembler is outputting a piece of line | |
1646 | debugging information, though, we write out the pending | |
1647 | instruction only if the --no-gstabs-packing command line switch | |
1648 | has been specified. */ | |
1649 | if (prev_opcode | |
1650 | && etype == PACK_UNSPEC | |
1651 | && (! outputting_stabs_line_debug || ! flag_allow_gstabs_packing)) | |
252b5132 RH |
1652 | { |
1653 | seg = now_seg; | |
1654 | subseg = now_subseg; | |
bccba5f0 | 1655 | |
252b5132 RH |
1656 | if (prev_seg) |
1657 | subseg_set (prev_seg, prev_subseg); | |
bccba5f0 | 1658 | |
252b5132 RH |
1659 | write_1_short (prev_opcode, prev_insn, fixups->next); |
1660 | subseg_set (seg, subseg); | |
1661 | prev_opcode = NULL; | |
1662 | } | |
1663 | return 1; | |
1664 | } | |
1665 | ||
fbdbf472 TR |
1666 | /* Like normal .word, except support @word. |
1667 | Clobbers input_line_pointer, checks end-of-line. */ | |
e0c6ed95 | 1668 | |
252b5132 | 1669 | static void |
ea1562b3 | 1670 | d10v_dot_word (int dummy ATTRIBUTE_UNUSED) |
252b5132 RH |
1671 | { |
1672 | expressionS exp; | |
252b5132 | 1673 | char *p; |
252b5132 RH |
1674 | |
1675 | if (is_it_end_of_statement ()) | |
1676 | { | |
1677 | demand_empty_rest_of_line (); | |
1678 | return; | |
1679 | } | |
1680 | ||
1681 | do | |
1682 | { | |
1683 | expression (&exp); | |
1684 | if (!strncasecmp (input_line_pointer, "@word", 5)) | |
1685 | { | |
1686 | exp.X_add_number = 0; | |
1687 | input_line_pointer += 5; | |
e0c6ed95 | 1688 | |
252b5132 | 1689 | p = frag_more (2); |
e0c6ed95 | 1690 | fix_new_exp (frag_now, p - frag_now->fr_literal, 2, |
252b5132 RH |
1691 | &exp, 0, BFD_RELOC_D10V_18); |
1692 | } | |
1693 | else | |
1694 | emit_expr (&exp, 2); | |
1695 | } | |
1696 | while (*input_line_pointer++ == ','); | |
1697 | ||
e0c6ed95 | 1698 | input_line_pointer--; /* Put terminator back into stream. */ |
252b5132 RH |
1699 | demand_empty_rest_of_line (); |
1700 | } | |
1701 | ||
e0c6ed95 AM |
1702 | /* Mitsubishi asked that we support some old syntax that apparently |
1703 | had immediate operands starting with '#'. This is in some of their | |
1704 | sample code but is not documented (although it appears in some | |
1705 | examples in their assembler manual). For now, we'll solve this | |
1706 | compatibility problem by simply ignoring any '#' at the beginning | |
1707 | of an operand. */ | |
252b5132 | 1708 | |
fbdbf472 TR |
1709 | /* Operands that begin with '#' should fall through to here. |
1710 | From expr.c. */ | |
252b5132 | 1711 | |
e0c6ed95 | 1712 | void |
ea1562b3 | 1713 | md_operand (expressionS *expressionP) |
252b5132 | 1714 | { |
0f94f4c8 | 1715 | if (*input_line_pointer == '#' && ! do_not_ignore_hash) |
252b5132 RH |
1716 | { |
1717 | input_line_pointer++; | |
1718 | expression (expressionP); | |
1719 | } | |
1720 | } | |
1721 | ||
b34976b6 | 1722 | bfd_boolean |
ea1562b3 | 1723 | d10v_fix_adjustable (fixS *fixP) |
252b5132 | 1724 | { |
e0c6ed95 | 1725 | /* We need the symbol name for the VTABLE entries. */ |
252b5132 RH |
1726 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
1727 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1728 | return 0; | |
1729 | ||
1730 | return 1; | |
1731 | } | |
ea1562b3 NC |
1732 | |
1733 | /* The target specific pseudo-ops which we support. */ | |
1734 | const pseudo_typeS md_pseudo_table[] = | |
1735 | { | |
1736 | { "word", d10v_dot_word, 2 }, | |
1737 | { NULL, NULL, 0 } | |
1738 | }; | |
1739 | ||
1740 | void | |
1741 | md_assemble (char *str) | |
1742 | { | |
1743 | /* etype is saved extype. For multi-line instructions. */ | |
1744 | packing_type extype = PACK_UNSPEC; /* Parallel, etc. */ | |
1745 | struct d10v_opcode *opcode; | |
1746 | unsigned long insn; | |
1747 | char *str2; | |
1748 | ||
1749 | if (etype == PACK_UNSPEC) | |
1750 | { | |
1751 | /* Look for the special multiple instruction separators. */ | |
1752 | str2 = strstr (str, "||"); | |
1753 | if (str2) | |
1754 | extype = PACK_PARALLEL; | |
1755 | else | |
1756 | { | |
1757 | str2 = strstr (str, "->"); | |
1758 | if (str2) | |
1759 | extype = PACK_LEFT_RIGHT; | |
1760 | else | |
1761 | { | |
1762 | str2 = strstr (str, "<-"); | |
1763 | if (str2) | |
1764 | extype = PACK_RIGHT_LEFT; | |
1765 | } | |
1766 | } | |
1767 | ||
1768 | /* str2 points to the separator, if there is one. */ | |
1769 | if (str2) | |
1770 | { | |
1771 | *str2 = 0; | |
1772 | ||
1773 | /* If two instructions are present and we already have one saved, | |
1774 | then first write out the saved one. */ | |
1775 | d10v_cleanup (); | |
1776 | ||
1777 | /* Assemble first instruction and save it. */ | |
1778 | prev_insn = do_assemble (str, &prev_opcode); | |
1779 | prev_seg = now_seg; | |
1780 | prev_subseg = now_subseg; | |
1781 | if (prev_insn == (unsigned long) -1) | |
1782 | as_fatal (_("can't find opcode ")); | |
1783 | fixups = fixups->next; | |
1784 | str = str2 + 2; | |
1785 | } | |
1786 | } | |
1787 | ||
1788 | insn = do_assemble (str, &opcode); | |
1789 | if (insn == (unsigned long) -1) | |
1790 | { | |
1791 | if (extype != PACK_UNSPEC) | |
1792 | { | |
1793 | etype = extype; | |
1794 | return; | |
1795 | } | |
1796 | as_fatal (_("can't find opcode ")); | |
1797 | } | |
1798 | ||
1799 | if (etype != PACK_UNSPEC) | |
1800 | { | |
1801 | extype = etype; | |
1802 | etype = PACK_UNSPEC; | |
1803 | } | |
1804 | ||
1805 | /* If this is a long instruction, write it and any previous short | |
1806 | instruction. */ | |
1807 | if (opcode->format & LONG_OPCODE) | |
1808 | { | |
1809 | if (extype != PACK_UNSPEC) | |
1810 | as_fatal (_("Unable to mix instructions as specified")); | |
1811 | d10v_cleanup (); | |
1812 | write_long (insn, fixups); | |
1813 | prev_opcode = NULL; | |
1814 | return; | |
1815 | } | |
1816 | ||
1817 | if (prev_opcode | |
1818 | && prev_seg | |
1819 | && ((prev_seg != now_seg) || (prev_subseg != now_subseg))) | |
1820 | d10v_cleanup (); | |
1821 | ||
1822 | if (prev_opcode | |
1823 | && (0 == write_2_short (prev_opcode, prev_insn, opcode, insn, extype, | |
1824 | fixups))) | |
1825 | { | |
1826 | /* No instructions saved. */ | |
1827 | prev_opcode = NULL; | |
1828 | } | |
1829 | else | |
1830 | { | |
1831 | if (extype != PACK_UNSPEC) | |
1832 | as_fatal (_("Unable to mix instructions as specified")); | |
1833 | /* Save last instruction so it may be packed on next pass. */ | |
1834 | prev_opcode = opcode; | |
1835 | prev_insn = insn; | |
1836 | prev_seg = now_seg; | |
1837 | prev_subseg = now_subseg; | |
1838 | fixups = fixups->next; | |
1839 | } | |
1840 | } | |
1841 |