Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-d30v.c -- Assembler code for the Mitsubishi D30V |
aef6203b | 2 | Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 |
2132e3a3 | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
19 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
20 | Boston, MA 02110-1301, USA. */ | |
252b5132 RH |
21 | |
22 | #include <stdio.h> | |
252b5132 | 23 | #include "as.h" |
3882b010 | 24 | #include "safe-ctype.h" |
2fd5405a | 25 | #include "subsegs.h" |
252b5132 RH |
26 | #include "opcode/d30v.h" |
27 | ||
ea1562b3 NC |
28 | const char comment_chars[] = ";"; |
29 | const char line_comment_chars[] = "#"; | |
252b5132 | 30 | const char line_separator_chars[] = ""; |
ea1562b3 NC |
31 | const char *md_shortopts = "OnNcC"; |
32 | const char EXP_CHARS[] = "eE"; | |
33 | const char FLT_CHARS[] = "dD"; | |
252b5132 | 34 | |
ba09cd8d DN |
35 | #if HAVE_LIMITS_H |
36 | #include <limits.h> | |
37 | #endif | |
38 | ||
39 | #ifndef CHAR_BIT | |
40 | #define CHAR_BIT 8 | |
41 | #endif | |
42 | ||
252b5132 RH |
43 | #define NOP_MULTIPLY 1 |
44 | #define NOP_ALL 2 | |
45 | static int warn_nops = 0; | |
46 | static int Optimizing = 0; | |
47 | static int warn_register_name_conflicts = 1; | |
48 | ||
49 | #define FORCE_SHORT 1 | |
50 | #define FORCE_LONG 2 | |
51 | ||
52 | /* EXEC types. */ | |
53 | typedef enum _exec_type | |
54 | { | |
ea1562b3 NC |
55 | EXEC_UNKNOWN, /* No order specified. */ |
56 | EXEC_PARALLEL, /* Done in parallel (FM=00). */ | |
57 | EXEC_SEQ, /* Sequential (FM=01). */ | |
58 | EXEC_REVSEQ /* Reverse sequential (FM=10). */ | |
252b5132 RH |
59 | } exec_type_enum; |
60 | ||
2fd5405a | 61 | /* Fixups. */ |
ea1562b3 NC |
62 | #define MAX_INSN_FIXUPS 5 |
63 | ||
252b5132 RH |
64 | struct d30v_fixup |
65 | { | |
66 | expressionS exp; | |
67 | int operand; | |
68 | int pcrel; | |
69 | int size; | |
70 | bfd_reloc_code_real_type reloc; | |
71 | }; | |
72 | ||
73 | typedef struct _fixups | |
74 | { | |
75 | int fc; | |
76 | struct d30v_fixup fix[MAX_INSN_FIXUPS]; | |
77 | struct _fixups *next; | |
78 | } Fixups; | |
79 | ||
80 | static Fixups FixUps[2]; | |
81 | static Fixups *fixups; | |
82 | ||
83 | /* Whether current and previous instruction are word multiply insns. */ | |
84 | static int cur_mul32_p = 0; | |
85 | static int prev_mul32_p = 0; | |
86 | ||
87 | /* The flag_explicitly_parallel is true iff the instruction being assembled | |
88 | has been explicitly written as a parallel short-instruction pair by the | |
2fd5405a | 89 | human programmer. It is used in parallel_ok () to distinguish between |
252b5132 RH |
90 | those dangerous parallelizations attempted by the human, which are to be |
91 | allowed, and those attempted by the assembler, which are not. It is set | |
2fd5405a NC |
92 | from md_assemble (). */ |
93 | static int flag_explicitly_parallel = 0; | |
252b5132 RH |
94 | static int flag_xp_state = 0; |
95 | ||
96 | /* Whether current and previous left sub-instruction disables | |
97 | execution of right sub-instruction. */ | |
98 | static int cur_left_kills_right_p = 0; | |
99 | static int prev_left_kills_right_p = 0; | |
100 | ||
101 | /* The known current alignment of the current section. */ | |
102 | static int d30v_current_align; | |
103 | static segT d30v_current_align_seg; | |
104 | ||
105 | /* The last seen label in the current section. This is used to auto-align | |
2d2255b5 | 106 | labels preceding instructions. */ |
252b5132 RH |
107 | static symbolS *d30v_last_label; |
108 | ||
2fd5405a | 109 | /* Two nops. */ |
252b5132 RH |
110 | #define NOP_LEFT ((long long) NOP << 32) |
111 | #define NOP_RIGHT ((long long) NOP) | |
112 | #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT) | |
113 | ||
2fd5405a NC |
114 | struct option md_longopts[] = |
115 | { | |
252b5132 RH |
116 | {NULL, no_argument, NULL, 0} |
117 | }; | |
252b5132 | 118 | |
2fd5405a | 119 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 120 | |
252b5132 RH |
121 | /* Opcode hash table. */ |
122 | static struct hash_control *d30v_hash; | |
123 | ||
2fd5405a NC |
124 | /* Do a binary search of the pre_defined_registers array to see if |
125 | NAME is a valid regiter name. Return the register number from the | |
126 | array on success, or -1 on failure. */ | |
252b5132 RH |
127 | |
128 | static int | |
ea1562b3 | 129 | reg_name_search (char *name) |
252b5132 RH |
130 | { |
131 | int middle, low, high; | |
132 | int cmp; | |
133 | ||
134 | low = 0; | |
135 | high = reg_name_cnt () - 1; | |
136 | ||
137 | do | |
138 | { | |
139 | middle = (low + high) / 2; | |
140 | cmp = strcasecmp (name, pre_defined_registers[middle].name); | |
141 | if (cmp < 0) | |
142 | high = middle - 1; | |
143 | else if (cmp > 0) | |
144 | low = middle + 1; | |
145 | else | |
146 | { | |
147 | if (symbol_find (name) != NULL) | |
148 | { | |
149 | if (warn_register_name_conflicts) | |
150 | as_warn (_("Register name %s conflicts with symbol of the same name"), | |
151 | name); | |
152 | } | |
2fd5405a | 153 | |
252b5132 RH |
154 | return pre_defined_registers[middle].value; |
155 | } | |
156 | } | |
157 | while (low <= high); | |
2fd5405a | 158 | |
252b5132 RH |
159 | return -1; |
160 | } | |
161 | ||
2fd5405a NC |
162 | /* Check the string at input_line_pointer to see if it is a valid |
163 | register name. */ | |
252b5132 RH |
164 | |
165 | static int | |
ea1562b3 | 166 | register_name (expressionS *expressionP) |
252b5132 RH |
167 | { |
168 | int reg_number; | |
169 | char c, *p = input_line_pointer; | |
2fd5405a NC |
170 | |
171 | while (*p && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')') | |
252b5132 RH |
172 | p++; |
173 | ||
174 | c = *p; | |
175 | if (c) | |
176 | *p++ = 0; | |
177 | ||
2fd5405a | 178 | /* Look to see if it's in the register table. */ |
252b5132 | 179 | reg_number = reg_name_search (input_line_pointer); |
2fd5405a | 180 | if (reg_number >= 0) |
252b5132 RH |
181 | { |
182 | expressionP->X_op = O_register; | |
2fd5405a NC |
183 | /* Temporarily store a pointer to the string here. */ |
184 | expressionP->X_op_symbol = (symbolS *) input_line_pointer; | |
252b5132 RH |
185 | expressionP->X_add_number = reg_number; |
186 | input_line_pointer = p; | |
187 | return 1; | |
188 | } | |
189 | if (c) | |
2fd5405a | 190 | *(p - 1) = c; |
252b5132 RH |
191 | return 0; |
192 | } | |
193 | ||
252b5132 | 194 | static int |
ea1562b3 | 195 | check_range (unsigned long num, int bits, int flags) |
252b5132 RH |
196 | { |
197 | long min, max; | |
252b5132 | 198 | |
bf80011a RH |
199 | /* Don't bother checking 32-bit values. */ |
200 | if (bits == 32) | |
201 | { | |
2fd5405a | 202 | if (sizeof (unsigned long) * CHAR_BIT == 32) |
cc8a6dd0 | 203 | return 0; |
bf80011a RH |
204 | |
205 | /* We don't record signed or unsigned for 32-bit quantities. | |
206 | Allow either. */ | |
2fd5405a NC |
207 | min = -((unsigned long) 1 << (bits - 1)); |
208 | max = ((unsigned long) 1 << bits) - 1; | |
30cdfbed | 209 | return (long) num < min || (long) num > max; |
bf80011a | 210 | } |
252b5132 RH |
211 | |
212 | if (flags & OPERAND_SHIFT) | |
213 | { | |
2fd5405a | 214 | /* We know that all shifts are right by three bits. */ |
30cdfbed | 215 | num >>= 3; |
2fd5405a | 216 | |
252b5132 | 217 | if (flags & OPERAND_SIGNED) |
30cdfbed AM |
218 | { |
219 | unsigned long sign_bit = ((unsigned long) -1L >> 4) + 1; | |
220 | num = (num ^ sign_bit) - sign_bit; | |
221 | } | |
252b5132 RH |
222 | } |
223 | ||
224 | if (flags & OPERAND_SIGNED) | |
225 | { | |
2fd5405a NC |
226 | max = ((unsigned long) 1 << (bits - 1)) - 1; |
227 | min = - ((unsigned long) 1 << (bits - 1)); | |
30cdfbed | 228 | return (long) num > max || (long) num < min; |
252b5132 RH |
229 | } |
230 | else | |
231 | { | |
2fd5405a | 232 | max = ((unsigned long) 1 << bits) - 1; |
30cdfbed | 233 | return num > (unsigned long) max; |
252b5132 | 234 | } |
252b5132 RH |
235 | } |
236 | ||
252b5132 | 237 | void |
ea1562b3 | 238 | md_show_usage (FILE *stream) |
252b5132 RH |
239 | { |
240 | fprintf (stream, _("\nD30V options:\n\ | |
241 | -O Make adjacent short instructions parallel if possible.\n\ | |
242 | -n Warn about all NOPs inserted by the assembler.\n\ | |
243 | -N Warn about NOPs inserted after word multiplies.\n\ | |
244 | -c Warn about symbols whoes names match register names.\n\ | |
245 | -C Opposite of -C. -c is the default.\n")); | |
246 | } | |
247 | ||
248 | int | |
ea1562b3 | 249 | md_parse_option (int c, char *arg ATTRIBUTE_UNUSED) |
252b5132 RH |
250 | { |
251 | switch (c) | |
252 | { | |
2fd5405a | 253 | /* Optimize. Will attempt to parallelize operations. */ |
252b5132 RH |
254 | case 'O': |
255 | Optimizing = 1; | |
256 | break; | |
257 | ||
258 | /* Warn about all NOPS that the assembler inserts. */ | |
259 | case 'n': | |
260 | warn_nops = NOP_ALL; | |
261 | break; | |
262 | ||
263 | /* Warn about the NOPS that the assembler inserts because of the | |
264 | multiply hazard. */ | |
265 | case 'N': | |
266 | warn_nops = NOP_MULTIPLY; | |
267 | break; | |
268 | ||
269 | case 'c': | |
270 | warn_register_name_conflicts = 1; | |
271 | break; | |
272 | ||
273 | case 'C': | |
274 | warn_register_name_conflicts = 0; | |
275 | break; | |
2fd5405a | 276 | |
252b5132 RH |
277 | default: |
278 | return 0; | |
279 | } | |
280 | return 1; | |
281 | } | |
282 | ||
283 | symbolS * | |
ea1562b3 | 284 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
285 | { |
286 | return 0; | |
287 | } | |
288 | ||
2fd5405a NC |
289 | /* Turn a string in input_line_pointer into a floating point constant |
290 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
291 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
292 | returned, or NULL on OK. */ | |
293 | ||
252b5132 | 294 | char * |
ea1562b3 | 295 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
296 | { |
297 | int prec; | |
298 | LITTLENUM_TYPE words[4]; | |
299 | char *t; | |
300 | int i; | |
2fd5405a | 301 | |
252b5132 RH |
302 | switch (type) |
303 | { | |
304 | case 'f': | |
305 | prec = 2; | |
306 | break; | |
307 | case 'd': | |
308 | prec = 4; | |
309 | break; | |
310 | default: | |
311 | *sizeP = 0; | |
312 | return _("bad call to md_atof"); | |
313 | } | |
314 | ||
315 | t = atof_ieee (input_line_pointer, type, words); | |
316 | if (t) | |
317 | input_line_pointer = t; | |
2fd5405a | 318 | |
252b5132 | 319 | *sizeP = prec * 2; |
2fd5405a | 320 | |
252b5132 RH |
321 | for (i = 0; i < prec; i++) |
322 | { | |
323 | md_number_to_chars (litP, (valueT) words[i], 2); | |
2fd5405a | 324 | litP += 2; |
252b5132 RH |
325 | } |
326 | return NULL; | |
327 | } | |
328 | ||
329 | void | |
ea1562b3 NC |
330 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
331 | asection *sec ATTRIBUTE_UNUSED, | |
332 | fragS *fragP ATTRIBUTE_UNUSED) | |
252b5132 RH |
333 | { |
334 | abort (); | |
335 | } | |
336 | ||
337 | valueT | |
ea1562b3 | 338 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
339 | { |
340 | int align = bfd_get_section_alignment (stdoutput, seg); | |
341 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
342 | } | |
343 | ||
252b5132 | 344 | void |
ea1562b3 | 345 | md_begin (void) |
252b5132 | 346 | { |
2fd5405a | 347 | struct d30v_opcode *opcode; |
252b5132 RH |
348 | d30v_hash = hash_new (); |
349 | ||
2fd5405a NC |
350 | /* Insert opcode names into a hash table. */ |
351 | for (opcode = (struct d30v_opcode *) d30v_opcode_table; opcode->name; opcode++) | |
252b5132 RH |
352 | hash_insert (d30v_hash, opcode->name, (char *) opcode); |
353 | ||
354 | fixups = &FixUps[0]; | |
355 | FixUps[0].next = &FixUps[1]; | |
356 | FixUps[1].next = &FixUps[0]; | |
357 | ||
358 | d30v_current_align_seg = now_seg; | |
359 | } | |
360 | ||
2fd5405a NC |
361 | /* Remove the postincrement or postdecrement operator ( '+' or '-' ) |
362 | from an expression. */ | |
252b5132 | 363 | |
2fd5405a | 364 | static int |
ea1562b3 | 365 | postfix (char *p) |
252b5132 | 366 | { |
2fd5405a | 367 | while (*p != '-' && *p != '+') |
252b5132 | 368 | { |
2fd5405a | 369 | if (*p == 0 || *p == '\n' || *p == '\r' || *p == ' ' || *p == ',') |
252b5132 RH |
370 | break; |
371 | p++; | |
372 | } | |
373 | ||
2fd5405a | 374 | if (*p == '-') |
252b5132 RH |
375 | { |
376 | *p = ' '; | |
2fd5405a | 377 | return -1; |
252b5132 | 378 | } |
81d4177b | 379 | |
2fd5405a | 380 | if (*p == '+') |
252b5132 RH |
381 | { |
382 | *p = ' '; | |
2fd5405a | 383 | return 1; |
252b5132 RH |
384 | } |
385 | ||
2fd5405a | 386 | return 0; |
252b5132 RH |
387 | } |
388 | ||
2fd5405a | 389 | static bfd_reloc_code_real_type |
ea1562b3 | 390 | get_reloc (struct d30v_operand *op, int rel_flag) |
252b5132 RH |
391 | { |
392 | switch (op->bits) | |
393 | { | |
394 | case 6: | |
395 | if (op->flags & OPERAND_SHIFT) | |
396 | return BFD_RELOC_D30V_9_PCREL; | |
397 | else | |
398 | return BFD_RELOC_D30V_6; | |
399 | break; | |
400 | case 12: | |
401 | if (!(op->flags & OPERAND_SHIFT)) | |
402 | as_warn (_("unexpected 12-bit reloc type")); | |
403 | if (rel_flag == RELOC_PCREL) | |
404 | return BFD_RELOC_D30V_15_PCREL; | |
405 | else | |
406 | return BFD_RELOC_D30V_15; | |
407 | case 18: | |
408 | if (!(op->flags & OPERAND_SHIFT)) | |
409 | as_warn (_("unexpected 18-bit reloc type")); | |
410 | if (rel_flag == RELOC_PCREL) | |
411 | return BFD_RELOC_D30V_21_PCREL; | |
412 | else | |
413 | return BFD_RELOC_D30V_21; | |
414 | case 32: | |
415 | if (rel_flag == RELOC_PCREL) | |
416 | return BFD_RELOC_D30V_32_PCREL; | |
417 | else | |
418 | return BFD_RELOC_D30V_32; | |
419 | default: | |
420 | return 0; | |
421 | } | |
422 | } | |
423 | ||
2fd5405a | 424 | /* Parse a string of operands and return an array of expressions. */ |
252b5132 RH |
425 | |
426 | static int | |
ea1562b3 | 427 | get_operands (expressionS exp[], int cmp_hack) |
252b5132 RH |
428 | { |
429 | char *p = input_line_pointer; | |
430 | int numops = 0; | |
431 | int post = 0; | |
432 | ||
433 | if (cmp_hack) | |
434 | { | |
435 | exp[numops].X_op = O_absent; | |
436 | exp[numops++].X_add_number = cmp_hack - 1; | |
437 | } | |
438 | ||
2fd5405a | 439 | while (*p) |
252b5132 | 440 | { |
2fd5405a | 441 | while (*p == ' ' || *p == '\t' || *p == ',') |
252b5132 | 442 | p++; |
81d4177b | 443 | |
2fd5405a NC |
444 | if (*p == 0 || *p == '\n' || *p == '\r') |
445 | break; | |
446 | ||
447 | if (*p == '@') | |
252b5132 RH |
448 | { |
449 | p++; | |
450 | exp[numops].X_op = O_absent; | |
2fd5405a | 451 | if (*p == '(') |
252b5132 RH |
452 | { |
453 | p++; | |
454 | exp[numops].X_add_number = OPERAND_ATPAR; | |
455 | post = postfix (p); | |
456 | } | |
2fd5405a | 457 | else if (*p == '-') |
252b5132 RH |
458 | { |
459 | p++; | |
460 | exp[numops].X_add_number = OPERAND_ATMINUS; | |
461 | } | |
462 | else | |
463 | { | |
464 | exp[numops].X_add_number = OPERAND_ATSIGN; | |
465 | post = postfix (p); | |
466 | } | |
467 | numops++; | |
468 | continue; | |
469 | } | |
470 | ||
2fd5405a | 471 | if (*p == ')') |
252b5132 | 472 | { |
2fd5405a | 473 | /* Just skip the trailing paren. */ |
252b5132 RH |
474 | p++; |
475 | continue; | |
476 | } | |
477 | ||
478 | input_line_pointer = p; | |
479 | ||
2fd5405a | 480 | /* Check to see if it might be a register name. */ |
252b5132 RH |
481 | if (!register_name (&exp[numops])) |
482 | { | |
2fd5405a | 483 | /* Parse as an expression. */ |
252b5132 RH |
484 | expression (&exp[numops]); |
485 | } | |
486 | ||
2fd5405a | 487 | if (exp[numops].X_op == O_illegal) |
252b5132 | 488 | as_bad (_("illegal operand")); |
2fd5405a | 489 | else if (exp[numops].X_op == O_absent) |
252b5132 RH |
490 | as_bad (_("missing operand")); |
491 | ||
492 | numops++; | |
493 | p = input_line_pointer; | |
494 | ||
2fd5405a | 495 | switch (post) |
252b5132 | 496 | { |
2fd5405a NC |
497 | case -1: |
498 | /* Postdecrement mode. */ | |
252b5132 RH |
499 | exp[numops].X_op = O_absent; |
500 | exp[numops++].X_add_number = OPERAND_MINUS; | |
501 | break; | |
2fd5405a NC |
502 | case 1: |
503 | /* Postincrement mode. */ | |
252b5132 RH |
504 | exp[numops].X_op = O_absent; |
505 | exp[numops++].X_add_number = OPERAND_PLUS; | |
506 | break; | |
507 | } | |
508 | post = 0; | |
509 | } | |
510 | ||
511 | exp[numops].X_op = 0; | |
81d4177b | 512 | |
2fd5405a | 513 | return numops; |
252b5132 RH |
514 | } |
515 | ||
2fd5405a NC |
516 | /* Generate the instruction. |
517 | It does everything but write the FM bits. */ | |
252b5132 RH |
518 | |
519 | static long long | |
ea1562b3 | 520 | build_insn (struct d30v_insn *opcode, expressionS *opers) |
252b5132 RH |
521 | { |
522 | int i, length, bits, shift, flags; | |
2fd5405a | 523 | unsigned long number, id = 0; |
252b5132 RH |
524 | long long insn; |
525 | struct d30v_opcode *op = opcode->op; | |
526 | struct d30v_format *form = opcode->form; | |
527 | ||
2fd5405a NC |
528 | insn = |
529 | opcode->ecc << 28 | op->op1 << 25 | op->op2 << 20 | form->modifier << 18; | |
252b5132 | 530 | |
2fd5405a NC |
531 | for (i = 0; form->operands[i]; i++) |
532 | { | |
252b5132 RH |
533 | flags = d30v_operand_table[form->operands[i]].flags; |
534 | ||
2fd5405a NC |
535 | /* Must be a register or number. */ |
536 | if (!(flags & OPERAND_REG) && !(flags & OPERAND_NUM) | |
537 | && !(flags & OPERAND_NAME) && !(flags & OPERAND_SPECIAL)) | |
252b5132 RH |
538 | continue; |
539 | ||
540 | bits = d30v_operand_table[form->operands[i]].bits; | |
541 | if (flags & OPERAND_SHIFT) | |
542 | bits += 3; | |
543 | ||
544 | length = d30v_operand_table[form->operands[i]].length; | |
545 | shift = 12 - d30v_operand_table[form->operands[i]].position; | |
546 | if (opers[i].X_op != O_symbol) | |
547 | number = opers[i].X_add_number; | |
548 | else | |
549 | number = 0; | |
550 | if (flags & OPERAND_REG) | |
551 | { | |
2fd5405a | 552 | /* Check for mvfsys or mvtsys control registers. */ |
252b5132 RH |
553 | if (flags & OPERAND_CONTROL && (number & 0x7f) > MAX_CONTROL_REG) |
554 | { | |
2fd5405a | 555 | /* PSWL or PSWH. */ |
252b5132 RH |
556 | id = (number & 0x7f) - MAX_CONTROL_REG; |
557 | number = 0; | |
558 | } | |
559 | else if (number & OPERAND_FLAG) | |
ea1562b3 NC |
560 | /* NUMBER is a flag register. */ |
561 | id = 3; | |
562 | ||
252b5132 RH |
563 | number &= 0x7F; |
564 | } | |
565 | else if (flags & OPERAND_SPECIAL) | |
ea1562b3 | 566 | number = id; |
252b5132 | 567 | |
2fd5405a NC |
568 | if (opers[i].X_op != O_register && opers[i].X_op != O_constant |
569 | && !(flags & OPERAND_NAME)) | |
252b5132 | 570 | { |
2fd5405a | 571 | /* Now create a fixup. */ |
252b5132 RH |
572 | if (fixups->fc >= MAX_INSN_FIXUPS) |
573 | as_fatal (_("too many fixups")); | |
574 | ||
2fd5405a NC |
575 | fixups->fix[fixups->fc].reloc = |
576 | get_reloc ((struct d30v_operand *) &d30v_operand_table[form->operands[i]], op->reloc_flag); | |
252b5132 RH |
577 | fixups->fix[fixups->fc].size = 4; |
578 | fixups->fix[fixups->fc].exp = opers[i]; | |
579 | fixups->fix[fixups->fc].operand = form->operands[i]; | |
580 | if (fixups->fix[fixups->fc].reloc == BFD_RELOC_D30V_9_PCREL) | |
581 | fixups->fix[fixups->fc].pcrel = RELOC_PCREL; | |
582 | else | |
583 | fixups->fix[fixups->fc].pcrel = op->reloc_flag; | |
584 | (fixups->fc)++; | |
585 | } | |
586 | ||
2fd5405a | 587 | /* Truncate to the proper number of bits. */ |
252b5132 | 588 | if ((opers[i].X_op == O_constant) && check_range (number, bits, flags)) |
ebf19f1b | 589 | as_bad (_("operand out of range: %ld"), number); |
252b5132 RH |
590 | if (bits < 31) |
591 | number &= 0x7FFFFFFF >> (31 - bits); | |
592 | if (flags & OPERAND_SHIFT) | |
593 | number >>= 3; | |
594 | if (bits == 32) | |
595 | { | |
2fd5405a | 596 | /* It's a LONG instruction. */ |
ea1562b3 NC |
597 | insn |= ((number & 0xffffffff) >> 26); /* Top 6 bits. */ |
598 | insn <<= 32; /* Shift the first word over. */ | |
599 | insn |= ((number & 0x03FC0000) << 2); /* Next 8 bits. */ | |
600 | insn |= number & 0x0003FFFF; /* Bottom 18 bits. */ | |
252b5132 RH |
601 | } |
602 | else | |
603 | insn |= number << shift; | |
604 | } | |
81d4177b | 605 | |
252b5132 RH |
606 | return insn; |
607 | } | |
608 | ||
ea1562b3 NC |
609 | static void |
610 | d30v_number_to_chars (char *buf, /* Return 'nbytes' of chars here. */ | |
611 | long long value, /* The value of the bits. */ | |
612 | int n) /* Number of bytes in the output. */ | |
613 | { | |
614 | while (n--) | |
615 | { | |
616 | buf[n] = value & 0xff; | |
617 | value >>= 8; | |
618 | } | |
619 | } | |
620 | ||
2fd5405a | 621 | /* Write out a long form instruction. */ |
252b5132 | 622 | |
252b5132 | 623 | static void |
ea1562b3 NC |
624 | write_long (struct d30v_insn *opcode ATTRIBUTE_UNUSED, |
625 | long long insn, | |
626 | Fixups *fx) | |
252b5132 RH |
627 | { |
628 | int i, where; | |
629 | char *f = frag_more (8); | |
630 | ||
631 | insn |= FM11; | |
632 | d30v_number_to_chars (f, insn, 8); | |
633 | ||
2fd5405a | 634 | for (i = 0; i < fx->fc; i++) |
252b5132 RH |
635 | { |
636 | if (fx->fix[i].reloc) | |
2fd5405a NC |
637 | { |
638 | where = f - frag_now->fr_literal; | |
ea1562b3 NC |
639 | fix_new_exp (frag_now, where, fx->fix[i].size, &(fx->fix[i].exp), |
640 | fx->fix[i].pcrel, fx->fix[i].reloc); | |
252b5132 RH |
641 | } |
642 | } | |
81d4177b | 643 | |
252b5132 RH |
644 | fx->fc = 0; |
645 | } | |
646 | ||
252b5132 | 647 | /* Write out a short form instruction by itself. */ |
2fd5405a | 648 | |
252b5132 | 649 | static void |
ea1562b3 NC |
650 | write_1_short (struct d30v_insn *opcode, |
651 | long long insn, | |
652 | Fixups *fx, | |
653 | int use_sequential) | |
252b5132 RH |
654 | { |
655 | char *f = frag_more (8); | |
656 | int i, where; | |
657 | ||
658 | if (warn_nops == NOP_ALL) | |
659 | as_warn (_("%s NOP inserted"), use_sequential ? | |
660 | _("sequential") : _("parallel")); | |
661 | ||
2fd5405a | 662 | /* The other container needs to be NOP. */ |
252b5132 RH |
663 | if (use_sequential) |
664 | { | |
665 | /* Use a sequential NOP rather than a parallel one, | |
666 | as the current instruction is a FLAG_MUL32 type one | |
667 | and the next instruction is a load. */ | |
2fd5405a | 668 | |
252b5132 | 669 | /* According to 4.3.1: for FM=01, sub-instructions performed |
2fd5405a | 670 | only by IU cannot be encoded in L-container. */ |
252b5132 | 671 | if (opcode->op->unit == IU) |
2fd5405a NC |
672 | /* Right then left. */ |
673 | insn |= FM10 | NOP_LEFT; | |
252b5132 | 674 | else |
2fd5405a NC |
675 | /* Left then right. */ |
676 | insn = FM01 | (insn << 32) | NOP_RIGHT; | |
252b5132 RH |
677 | } |
678 | else | |
679 | { | |
680 | /* According to 4.3.1: for FM=00, sub-instructions performed | |
2fd5405a | 681 | only by IU cannot be encoded in L-container. */ |
252b5132 | 682 | if (opcode->op->unit == IU) |
2fd5405a NC |
683 | /* Right container. */ |
684 | insn |= FM00 | NOP_LEFT; | |
252b5132 | 685 | else |
2fd5405a NC |
686 | /* Left container. */ |
687 | insn = FM00 | (insn << 32) | NOP_RIGHT; | |
252b5132 RH |
688 | } |
689 | ||
690 | d30v_number_to_chars (f, insn, 8); | |
691 | ||
2fd5405a | 692 | for (i = 0; i < fx->fc; i++) |
252b5132 RH |
693 | { |
694 | if (fx->fix[i].reloc) | |
2fd5405a NC |
695 | { |
696 | where = f - frag_now->fr_literal; | |
252b5132 | 697 | fix_new_exp (frag_now, |
2fd5405a | 698 | where, |
252b5132 RH |
699 | fx->fix[i].size, |
700 | &(fx->fix[i].exp), | |
701 | fx->fix[i].pcrel, | |
702 | fx->fix[i].reloc); | |
703 | } | |
704 | } | |
81d4177b | 705 | |
252b5132 RH |
706 | fx->fc = 0; |
707 | } | |
708 | ||
2fd5405a NC |
709 | /* Check 2 instructions and determine if they can be safely |
710 | executed in parallel. Return 1 if they can be. */ | |
252b5132 | 711 | |
252b5132 | 712 | static int |
ea1562b3 NC |
713 | parallel_ok (struct d30v_insn *op1, |
714 | unsigned long insn1, | |
715 | struct d30v_insn *op2, | |
716 | unsigned long insn2, | |
717 | exec_type_enum exec_type) | |
252b5132 RH |
718 | { |
719 | int i, j, shift, regno, bits, ecc; | |
720 | unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2; | |
721 | unsigned long ins, mod_reg[2][3], used_reg[2][3], flag_reg[2]; | |
722 | struct d30v_format *f; | |
723 | struct d30v_opcode *op; | |
724 | ||
2fd5405a | 725 | /* Section 4.3: Both instructions must not be IU or MU only. */ |
252b5132 RH |
726 | if ((op1->op->unit == IU && op2->op->unit == IU) |
727 | || (op1->op->unit == MU && op2->op->unit == MU)) | |
728 | return 0; | |
729 | ||
2fd5405a | 730 | /* First instruction must not be a jump to safely optimize, unless this |
252b5132 RH |
731 | is an explicit parallel operation. */ |
732 | if (exec_type != EXEC_PARALLEL | |
733 | && (op1->op->flags_used & (FLAG_JMP | FLAG_JSR))) | |
734 | return 0; | |
735 | ||
736 | /* If one instruction is /TX or /XT and the other is /FX or /XF respectively, | |
737 | then it is safe to allow the two to be done as parallel ops, since only | |
738 | one will ever be executed at a time. */ | |
739 | if ((op1->ecc == ECC_TX && op2->ecc == ECC_FX) | |
740 | || (op1->ecc == ECC_FX && op2->ecc == ECC_TX) | |
741 | || (op1->ecc == ECC_XT && op2->ecc == ECC_XF) | |
742 | || (op1->ecc == ECC_XF && op2->ecc == ECC_XT)) | |
2fd5405a | 743 | return 1; |
252b5132 RH |
744 | |
745 | /* [0] r0-r31 | |
746 | [1] r32-r63 | |
2fd5405a | 747 | [2] a0, a1, flag registers. */ |
252b5132 RH |
748 | for (j = 0; j < 2; j++) |
749 | { | |
750 | if (j == 0) | |
751 | { | |
752 | f = op1->form; | |
753 | op = op1->op; | |
754 | ecc = op1->ecc; | |
755 | ins = insn1; | |
756 | } | |
757 | else | |
758 | { | |
759 | f = op2->form; | |
760 | op = op2->op; | |
761 | ecc = op2->ecc; | |
762 | ins = insn2; | |
763 | } | |
81d4177b | 764 | |
252b5132 RH |
765 | flag_reg[j] = 0; |
766 | mod_reg[j][0] = mod_reg[j][1] = 0; | |
767 | used_reg[j][0] = used_reg[j][1] = 0; | |
768 | ||
769 | if (flag_explicitly_parallel) | |
770 | { | |
771 | /* For human specified parallel instructions we have been asked | |
772 | to ignore the possibility that both instructions could modify | |
773 | bits in the PSW, so we initialise the mod & used arrays to 0. | |
774 | We have been asked, however, to refuse to allow parallel | |
775 | instructions which explicitly set the same flag register, | |
776 | eg "cmpne f0,r1,0x10 || cmpeq f0, r5, 0x2", so further on we test | |
777 | for the use of a flag register and set a bit in the mod or used | |
778 | array appropriately. */ | |
252b5132 RH |
779 | mod_reg[j][2] = 0; |
780 | used_reg[j][2] = 0; | |
781 | } | |
782 | else | |
783 | { | |
784 | mod_reg[j][2] = (op->flags_set & FLAG_ALL); | |
785 | used_reg[j][2] = (op->flags_used & FLAG_ALL); | |
786 | } | |
2fd5405a NC |
787 | |
788 | /* BSR/JSR always sets R62. */ | |
252b5132 | 789 | if (op->flags_used & FLAG_JSR) |
2fd5405a | 790 | mod_reg[j][1] = (1L << (62 - 32)); |
252b5132 | 791 | |
2fd5405a | 792 | /* Conditional execution affects the flags_used. */ |
252b5132 RH |
793 | switch (ecc) |
794 | { | |
795 | case ECC_TX: | |
796 | case ECC_FX: | |
797 | used_reg[j][2] |= flag_reg[j] = FLAG_0; | |
798 | break; | |
799 | ||
800 | case ECC_XT: | |
801 | case ECC_XF: | |
802 | used_reg[j][2] |= flag_reg[j] = FLAG_1; | |
803 | break; | |
804 | ||
805 | case ECC_TT: | |
806 | case ECC_TF: | |
807 | used_reg[j][2] |= flag_reg[j] = (FLAG_0 | FLAG_1); | |
808 | break; | |
809 | } | |
810 | ||
811 | for (i = 0; f->operands[i]; i++) | |
812 | { | |
813 | flags = d30v_operand_table[f->operands[i]].flags; | |
814 | shift = 12 - d30v_operand_table[f->operands[i]].position; | |
815 | bits = d30v_operand_table[f->operands[i]].bits; | |
816 | if (bits == 32) | |
817 | mask = 0xffffffff; | |
818 | else | |
819 | mask = 0x7FFFFFFF >> (31 - bits); | |
820 | ||
821 | if ((flags & OPERAND_PLUS) || (flags & OPERAND_MINUS)) | |
822 | { | |
2fd5405a NC |
823 | /* This is a post-increment or post-decrement. |
824 | The previous register needs to be marked as modified. */ | |
825 | shift = 12 - d30v_operand_table[f->operands[i - 1]].position; | |
252b5132 RH |
826 | regno = (ins >> shift) & 0x3f; |
827 | if (regno >= 32) | |
828 | mod_reg[j][1] |= 1L << (regno - 32); | |
829 | else | |
830 | mod_reg[j][0] |= 1L << regno; | |
831 | } | |
832 | else if (flags & OPERAND_REG) | |
833 | { | |
834 | regno = (ins >> shift) & mask; | |
2fd5405a NC |
835 | /* The memory write functions don't have a destination |
836 | register. */ | |
252b5132 RH |
837 | if ((flags & OPERAND_DEST) && !(op->flags_set & FLAG_MEM)) |
838 | { | |
2fd5405a | 839 | /* MODIFIED registers and flags. */ |
252b5132 RH |
840 | if (flags & OPERAND_ACC) |
841 | { | |
842 | if (regno == 0) | |
843 | mod_reg[j][2] |= FLAG_A0; | |
844 | else if (regno == 1) | |
845 | mod_reg[j][2] |= FLAG_A1; | |
846 | else | |
847 | abort (); | |
848 | } | |
849 | else if (flags & OPERAND_FLAG) | |
850 | mod_reg[j][2] |= 1L << regno; | |
851 | else if (!(flags & OPERAND_CONTROL)) | |
852 | { | |
853 | int r, z; | |
854 | ||
2fd5405a NC |
855 | /* Need to check if there are two destination |
856 | registers, for example ld2w. */ | |
252b5132 RH |
857 | if (flags & OPERAND_2REG) |
858 | z = 1; | |
859 | else | |
860 | z = 0; | |
861 | ||
862 | for (r = regno; r <= regno + z; r++) | |
2fd5405a | 863 | { |
252b5132 RH |
864 | if (r >= 32) |
865 | mod_reg[j][1] |= 1L << (r - 32); | |
866 | else | |
867 | mod_reg[j][0] |= 1L << r; | |
868 | } | |
869 | } | |
870 | } | |
871 | else | |
872 | { | |
2fd5405a | 873 | /* USED, but not modified registers and flags. */ |
252b5132 RH |
874 | if (flags & OPERAND_ACC) |
875 | { | |
876 | if (regno == 0) | |
877 | used_reg[j][2] |= FLAG_A0; | |
878 | else if (regno == 1) | |
879 | used_reg[j][2] |= FLAG_A1; | |
880 | else | |
881 | abort (); | |
882 | } | |
883 | else if (flags & OPERAND_FLAG) | |
884 | used_reg[j][2] |= 1L << regno; | |
885 | else if (!(flags & OPERAND_CONTROL)) | |
886 | { | |
887 | int r, z; | |
888 | ||
2fd5405a NC |
889 | /* Need to check if there are two source |
890 | registers, for example st2w. */ | |
252b5132 RH |
891 | if (flags & OPERAND_2REG) |
892 | z = 1; | |
893 | else | |
894 | z = 0; | |
895 | ||
896 | for (r = regno; r <= regno + z; r++) | |
2fd5405a | 897 | { |
252b5132 RH |
898 | if (r >= 32) |
899 | used_reg[j][1] |= 1L << (r - 32); | |
900 | else | |
901 | used_reg[j][0] |= 1L << r; | |
902 | } | |
903 | } | |
904 | } | |
905 | } | |
906 | } | |
907 | } | |
2fd5405a | 908 | |
252b5132 RH |
909 | flags_set1 = op1->op->flags_set; |
910 | flags_set2 = op2->op->flags_set; | |
911 | flags_used1 = op1->op->flags_used; | |
912 | flags_used2 = op2->op->flags_used; | |
913 | ||
25f2196d CC |
914 | /* Check for illegal combinations with ADDppp/SUBppp. */ |
915 | if (((flags_set1 & FLAG_NOT_WITH_ADDSUBppp) != 0 | |
252b5132 | 916 | && (flags_used2 & FLAG_ADDSUBppp) != 0) |
25f2196d | 917 | || ((flags_set2 & FLAG_NOT_WITH_ADDSUBppp) != 0 |
252b5132 RH |
918 | && (flags_used1 & FLAG_ADDSUBppp) != 0)) |
919 | return 0; | |
920 | ||
921 | /* Load instruction combined with half-word multiply is illegal. */ | |
922 | if (((flags_used1 & FLAG_MEM) != 0 && (flags_used2 & FLAG_MUL16)) | |
923 | || ((flags_used2 & FLAG_MEM) != 0 && (flags_used1 & FLAG_MUL16))) | |
924 | return 0; | |
925 | ||
926 | /* Specifically allow add || add by removing carry, overflow bits dependency. | |
927 | This is safe, even if an addc follows since the IU takes the argument in | |
928 | the right container, and it writes its results last. | |
929 | However, don't paralellize add followed by addc or sub followed by | |
930 | subb. */ | |
252b5132 RH |
931 | if (mod_reg[0][2] == FLAG_CVVA && mod_reg[1][2] == FLAG_CVVA |
932 | && (used_reg[0][2] & ~flag_reg[0]) == 0 | |
933 | && (used_reg[1][2] & ~flag_reg[1]) == 0 | |
934 | && op1->op->unit == EITHER && op2->op->unit == EITHER) | |
935 | { | |
936 | mod_reg[0][2] = mod_reg[1][2] = 0; | |
937 | } | |
938 | ||
939 | for (j = 0; j < 3; j++) | |
940 | { | |
941 | /* If the second instruction depends on the first, we obviously | |
942 | cannot parallelize. Note, the mod flag implies use, so | |
943 | check that as well. */ | |
2fd5405a | 944 | /* If flag_explicitly_parallel is set, then the case of the |
252b5132 RH |
945 | second instruction using a register the first instruction |
946 | modifies is assumed to be okay; we trust the human. We | |
947 | don't trust the human if both instructions modify the same | |
948 | register but we do trust the human if they modify the same | |
2fd5405a | 949 | flags. */ |
252b5132 RH |
950 | /* We have now been requested not to trust the human if the |
951 | instructions modify the same flag registers either. */ | |
952 | if (flag_explicitly_parallel) | |
953 | { | |
954 | if ((mod_reg[0][j] & mod_reg[1][j]) != 0) | |
955 | return 0; | |
956 | } | |
957 | else | |
cc8a6dd0 | 958 | if ((mod_reg[0][j] & (mod_reg[1][j] | used_reg[1][j])) != 0) |
252b5132 RH |
959 | return 0; |
960 | } | |
961 | ||
962 | return 1; | |
963 | } | |
964 | ||
ea1562b3 NC |
965 | /* Write out a short form instruction if possible. |
966 | Return number of instructions not written out. */ | |
252b5132 | 967 | |
ea1562b3 NC |
968 | static int |
969 | write_2_short (struct d30v_insn *opcode1, | |
970 | long long insn1, | |
971 | struct d30v_insn *opcode2, | |
972 | long long insn2, | |
973 | exec_type_enum exec_type, | |
974 | Fixups *fx) | |
252b5132 | 975 | { |
ea1562b3 NC |
976 | long long insn = NOP2; |
977 | char *f; | |
978 | int i, j, where; | |
252b5132 | 979 | |
ea1562b3 NC |
980 | if (exec_type == EXEC_SEQ |
981 | && (opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR)) | |
982 | && ((opcode1->op->flags_used & FLAG_DELAY) == 0) | |
983 | && ((opcode1->ecc == ECC_AL) || ! Optimizing)) | |
984 | { | |
985 | /* Unconditional, non-delayed branches kill instructions in | |
986 | the right bin. Conditional branches don't always but if | |
987 | we are not optimizing, then we have been asked to produce | |
988 | an error about such constructs. For the purposes of this | |
989 | test, subroutine calls are considered to be branches. */ | |
990 | write_1_short (opcode1, insn1, fx->next, FALSE); | |
991 | return 1; | |
992 | } | |
252b5132 | 993 | |
ea1562b3 NC |
994 | /* Note: we do not have to worry about subroutine calls occurring |
995 | in the right hand container. The return address is always | |
996 | aligned to the next 64 bit boundary, be that 64 or 32 bit away. */ | |
997 | switch (exec_type) | |
252b5132 | 998 | { |
ea1562b3 NC |
999 | case EXEC_UNKNOWN: /* Order not specified. */ |
1000 | if (Optimizing | |
1001 | && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type) | |
1002 | && ! ( (opcode1->op->unit == EITHER_BUT_PREFER_MU | |
1003 | || opcode1->op->unit == MU) | |
1004 | && | |
1005 | ( opcode2->op->unit == EITHER_BUT_PREFER_MU | |
1006 | || opcode2->op->unit == MU))) | |
252b5132 | 1007 | { |
ea1562b3 NC |
1008 | /* Parallel. */ |
1009 | exec_type = EXEC_PARALLEL; | |
1010 | ||
1011 | if (opcode1->op->unit == IU | |
1012 | || opcode2->op->unit == MU | |
1013 | || opcode2->op->unit == EITHER_BUT_PREFER_MU) | |
1014 | insn = FM00 | (insn2 << 32) | insn1; | |
252b5132 RH |
1015 | else |
1016 | { | |
ea1562b3 NC |
1017 | insn = FM00 | (insn1 << 32) | insn2; |
1018 | fx = fx->next; | |
252b5132 RH |
1019 | } |
1020 | } | |
ea1562b3 NC |
1021 | else if ((opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR) |
1022 | && ((opcode1->op->flags_used & FLAG_DELAY) == 0)) | |
1023 | || opcode1->op->flags_used & FLAG_RP) | |
1024 | { | |
1025 | /* We must emit (non-delayed) branch type instructions | |
1026 | on their own with nothing in the right container. */ | |
1027 | /* We must treat repeat instructions likewise, since the | |
1028 | following instruction has to be separate from the repeat | |
1029 | in order to be repeated. */ | |
1030 | write_1_short (opcode1, insn1, fx->next, FALSE); | |
1031 | return 1; | |
1032 | } | |
1033 | else if (prev_left_kills_right_p) | |
1034 | { | |
1035 | /* The left instruction kils the right slot, so we | |
1036 | must leave it empty. */ | |
1037 | write_1_short (opcode1, insn1, fx->next, FALSE); | |
1038 | return 1; | |
1039 | } | |
1040 | else if (opcode1->op->unit == IU) | |
1041 | { | |
1042 | if (opcode2->op->unit == EITHER_BUT_PREFER_MU) | |
1043 | { | |
1044 | /* Case 103810 is a request from Mitsubishi that opcodes | |
1045 | with EITHER_BUT_PREFER_MU should not be executed in | |
1046 | reverse sequential order. */ | |
1047 | write_1_short (opcode1, insn1, fx->next, FALSE); | |
1048 | return 1; | |
1049 | } | |
81d4177b | 1050 | |
ea1562b3 NC |
1051 | /* Reverse sequential. */ |
1052 | insn = FM10 | (insn2 << 32) | insn1; | |
1053 | exec_type = EXEC_REVSEQ; | |
1054 | } | |
1055 | else | |
252b5132 | 1056 | { |
ea1562b3 NC |
1057 | /* Sequential. */ |
1058 | insn = FM01 | (insn1 << 32) | insn2; | |
1059 | fx = fx->next; | |
1060 | exec_type = EXEC_SEQ; | |
1061 | } | |
1062 | break; | |
2fd5405a | 1063 | |
ea1562b3 NC |
1064 | case EXEC_PARALLEL: /* Parallel. */ |
1065 | flag_explicitly_parallel = flag_xp_state; | |
1066 | if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) | |
1067 | as_bad (_("Instructions may not be executed in parallel")); | |
1068 | else if (opcode1->op->unit == IU) | |
1069 | { | |
1070 | if (opcode2->op->unit == IU) | |
1071 | as_bad (_("Two IU instructions may not be executed in parallel")); | |
1072 | as_warn (_("Swapping instruction order")); | |
1073 | insn = FM00 | (insn2 << 32) | insn1; | |
1074 | } | |
1075 | else if (opcode2->op->unit == MU) | |
1076 | { | |
1077 | if (opcode1->op->unit == MU) | |
1078 | as_bad (_("Two MU instructions may not be executed in parallel")); | |
1079 | else if (opcode1->op->unit == EITHER_BUT_PREFER_MU) | |
1080 | as_warn (_("Executing %s in IU may not work"), opcode1->op->name); | |
1081 | as_warn (_("Swapping instruction order")); | |
1082 | insn = FM00 | (insn2 << 32) | insn1; | |
1083 | } | |
1084 | else | |
1085 | { | |
1086 | if (opcode2->op->unit == EITHER_BUT_PREFER_MU) | |
1087 | as_warn (_("Executing %s in IU may not work in parallel execution"), | |
1088 | opcode2->op->name); | |
2fd5405a | 1089 | |
ea1562b3 NC |
1090 | insn = FM00 | (insn1 << 32) | insn2; |
1091 | fx = fx->next; | |
252b5132 | 1092 | } |
ea1562b3 NC |
1093 | flag_explicitly_parallel = 0; |
1094 | break; | |
252b5132 | 1095 | |
ea1562b3 NC |
1096 | case EXEC_SEQ: /* Sequential. */ |
1097 | if (opcode1->op->unit == IU) | |
1098 | as_bad (_("IU instruction may not be in the left container")); | |
1099 | if (prev_left_kills_right_p) | |
1100 | as_bad (_("special left instruction `%s' kills instruction " | |
1101 | "`%s' in right container"), | |
1102 | opcode1->op->name, opcode2->op->name); | |
1103 | insn = FM01 | (insn1 << 32) | insn2; | |
1104 | fx = fx->next; | |
1105 | break; | |
252b5132 | 1106 | |
ea1562b3 NC |
1107 | case EXEC_REVSEQ: /* Reverse sequential. */ |
1108 | if (opcode2->op->unit == MU) | |
1109 | as_bad (_("MU instruction may not be in the right container")); | |
1110 | if (opcode1->op->unit == EITHER_BUT_PREFER_MU) | |
1111 | as_warn (_("Executing %s in reverse serial with %s may not work"), | |
1112 | opcode1->op->name, opcode2->op->name); | |
1113 | else if (opcode2->op->unit == EITHER_BUT_PREFER_MU) | |
1114 | as_warn (_("Executing %s in IU in reverse serial may not work"), | |
1115 | opcode2->op->name); | |
1116 | insn = FM10 | (insn1 << 32) | insn2; | |
1117 | fx = fx->next; | |
1118 | break; | |
1119 | ||
1120 | default: | |
1121 | as_fatal (_("unknown execution type passed to write_2_short()")); | |
252b5132 RH |
1122 | } |
1123 | ||
ea1562b3 NC |
1124 | f = frag_more (8); |
1125 | d30v_number_to_chars (f, insn, 8); | |
1126 | ||
1127 | /* If the previous instruction was a 32-bit multiply but it is put into a | |
1128 | parallel container, mark the current instruction as being a 32-bit | |
1129 | multiply. */ | |
1130 | if (prev_mul32_p && exec_type == EXEC_PARALLEL) | |
1131 | cur_mul32_p = 1; | |
1132 | ||
1133 | for (j = 0; j < 2; j++) | |
252b5132 | 1134 | { |
ea1562b3 | 1135 | for (i = 0; i < fx->fc; i++) |
252b5132 | 1136 | { |
ea1562b3 | 1137 | if (fx->fix[i].reloc) |
252b5132 | 1138 | { |
ea1562b3 | 1139 | where = (f - frag_now->fr_literal) + 4 * j; |
2fd5405a | 1140 | |
ea1562b3 NC |
1141 | fix_new_exp (frag_now, |
1142 | where, | |
1143 | fx->fix[i].size, | |
1144 | &(fx->fix[i].exp), | |
1145 | fx->fix[i].pcrel, | |
1146 | fx->fix[i].reloc); | |
252b5132 | 1147 | } |
252b5132 | 1148 | } |
ea1562b3 NC |
1149 | |
1150 | fx->fc = 0; | |
1151 | fx = fx->next; | |
252b5132 | 1152 | } |
2fd5405a | 1153 | |
ea1562b3 NC |
1154 | return 0; |
1155 | } | |
252b5132 | 1156 | |
ea1562b3 NC |
1157 | /* Get a pointer to an entry in the format table. |
1158 | It must look at all formats for an opcode and use the operands | |
1159 | to choose the correct one. Return NULL on error. */ | |
1160 | ||
1161 | static struct d30v_format * | |
1162 | find_format (struct d30v_opcode *opcode, | |
1163 | expressionS myops[], | |
1164 | int fsize, | |
1165 | int cmp_hack) | |
1166 | { | |
1167 | int numops, match, index, i = 0, j, k; | |
1168 | struct d30v_format *fm; | |
1169 | ||
1170 | if (opcode == NULL) | |
1171 | return NULL; | |
1172 | ||
1173 | /* Get all the operands and save them as expressions. */ | |
1174 | numops = get_operands (myops, cmp_hack); | |
1175 | ||
1176 | while ((index = opcode->format[i++]) != 0) | |
252b5132 | 1177 | { |
ea1562b3 NC |
1178 | if (fsize == FORCE_SHORT && index >= LONG) |
1179 | continue; | |
2fd5405a | 1180 | |
ea1562b3 NC |
1181 | if (fsize == FORCE_LONG && index < LONG) |
1182 | continue; | |
1183 | ||
1184 | fm = (struct d30v_format *) &d30v_format_table[index]; | |
1185 | k = index; | |
1186 | while (fm->form == index) | |
1187 | { | |
1188 | match = 1; | |
1189 | /* Now check the operands for compatibility. */ | |
1190 | for (j = 0; match && fm->operands[j]; j++) | |
1191 | { | |
1192 | int flags = d30v_operand_table[fm->operands[j]].flags; | |
1193 | int bits = d30v_operand_table[fm->operands[j]].bits; | |
1194 | int X_op = myops[j].X_op; | |
1195 | int num = myops[j].X_add_number; | |
1196 | ||
1197 | if (flags & OPERAND_SPECIAL) | |
1198 | break; | |
1199 | else if (X_op == O_illegal) | |
1200 | match = 0; | |
1201 | else if (flags & OPERAND_REG) | |
1202 | { | |
1203 | if (X_op != O_register | |
1204 | || ((flags & OPERAND_ACC) && !(num & OPERAND_ACC)) | |
1205 | || (!(flags & OPERAND_ACC) && (num & OPERAND_ACC)) | |
1206 | || ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG)) | |
1207 | || (!(flags & (OPERAND_FLAG | OPERAND_CONTROL)) && (num & OPERAND_FLAG)) | |
1208 | || ((flags & OPERAND_CONTROL) | |
1209 | && !(num & (OPERAND_CONTROL | OPERAND_FLAG)))) | |
1210 | match = 0; | |
1211 | } | |
1212 | else if (((flags & OPERAND_MINUS) | |
1213 | && (X_op != O_absent || num != OPERAND_MINUS)) | |
1214 | || ((flags & OPERAND_PLUS) | |
1215 | && (X_op != O_absent || num != OPERAND_PLUS)) | |
1216 | || ((flags & OPERAND_ATMINUS) | |
1217 | && (X_op != O_absent || num != OPERAND_ATMINUS)) | |
1218 | || ((flags & OPERAND_ATPAR) | |
1219 | && (X_op != O_absent || num != OPERAND_ATPAR)) | |
1220 | || ((flags & OPERAND_ATSIGN) | |
1221 | && (X_op != O_absent || num != OPERAND_ATSIGN))) | |
1222 | match = 0; | |
1223 | else if (flags & OPERAND_NUM) | |
1224 | { | |
1225 | /* A number can be a constant or symbol expression. */ | |
1226 | ||
1227 | /* If we have found a register name, but that name | |
1228 | also matches a symbol, then re-parse the name as | |
1229 | an expression. */ | |
1230 | if (X_op == O_register | |
1231 | && symbol_find ((char *) myops[j].X_op_symbol)) | |
1232 | { | |
1233 | input_line_pointer = (char *) myops[j].X_op_symbol; | |
1234 | expression (&myops[j]); | |
1235 | } | |
1236 | ||
1237 | /* Turn an expression into a symbol for later resolution. */ | |
1238 | if (X_op != O_absent && X_op != O_constant | |
1239 | && X_op != O_symbol && X_op != O_register | |
1240 | && X_op != O_big) | |
1241 | { | |
1242 | symbolS *sym = make_expr_symbol (&myops[j]); | |
1243 | myops[j].X_op = X_op = O_symbol; | |
1244 | myops[j].X_add_symbol = sym; | |
1245 | myops[j].X_add_number = num = 0; | |
1246 | } | |
1247 | ||
1248 | if (fm->form >= LONG) | |
1249 | { | |
1250 | /* If we're testing for a LONG format, either fits. */ | |
1251 | if (X_op != O_constant && X_op != O_symbol) | |
1252 | match = 0; | |
1253 | } | |
1254 | else if (fm->form < LONG | |
1255 | && ((fsize == FORCE_SHORT && X_op == O_symbol) | |
1256 | || (fm->form == SHORT_D2 && j == 0))) | |
1257 | match = 1; | |
1258 | ||
1259 | /* This is the tricky part. Will the constant or symbol | |
1260 | fit into the space in the current format? */ | |
1261 | else if (X_op == O_constant) | |
1262 | { | |
1263 | if (check_range (num, bits, flags)) | |
1264 | match = 0; | |
1265 | } | |
1266 | else if (X_op == O_symbol | |
1267 | && S_IS_DEFINED (myops[j].X_add_symbol) | |
1268 | && S_GET_SEGMENT (myops[j].X_add_symbol) == now_seg | |
1269 | && opcode->reloc_flag == RELOC_PCREL) | |
1270 | { | |
1271 | /* If the symbol is defined, see if the value will fit | |
1272 | into the form we're considering. */ | |
1273 | fragS *f; | |
1274 | long value; | |
1275 | ||
1276 | /* Calculate the current address by running through the | |
1277 | previous frags and adding our current offset. */ | |
1278 | value = 0; | |
1279 | for (f = frchain_now->frch_root; f; f = f->fr_next) | |
1280 | value += f->fr_fix + f->fr_offset; | |
1281 | value = (S_GET_VALUE (myops[j].X_add_symbol) - value | |
1282 | - (obstack_next_free (&frchain_now->frch_obstack) | |
1283 | - frag_now->fr_literal)); | |
1284 | if (check_range (value, bits, flags)) | |
1285 | match = 0; | |
1286 | } | |
1287 | else | |
1288 | match = 0; | |
1289 | } | |
1290 | } | |
1291 | /* We're only done if the operands matched so far AND there | |
1292 | are no more to check. */ | |
1293 | if (match && myops[j].X_op == 0) | |
1294 | { | |
1295 | /* Final check - issue a warning if an odd numbered register | |
1296 | is used as the first register in an instruction that reads | |
1297 | or writes 2 registers. */ | |
1298 | ||
1299 | for (j = 0; fm->operands[j]; j++) | |
1300 | if (myops[j].X_op == O_register | |
1301 | && (myops[j].X_add_number & 1) | |
1302 | && (d30v_operand_table[fm->operands[j]].flags & OPERAND_2REG)) | |
1303 | as_warn (_("Odd numbered register used as target of multi-register instruction")); | |
1304 | ||
1305 | return fm; | |
1306 | } | |
1307 | fm = (struct d30v_format *) &d30v_format_table[++k]; | |
1308 | } | |
252b5132 | 1309 | } |
ea1562b3 | 1310 | return NULL; |
252b5132 RH |
1311 | } |
1312 | ||
2fd5405a NC |
1313 | /* Assemble a single instruction and return an opcode. |
1314 | Return -1 (an invalid opcode) on error. */ | |
252b5132 RH |
1315 | |
1316 | #define NAME_BUF_LEN 20 | |
1317 | ||
1318 | static long long | |
ea1562b3 NC |
1319 | do_assemble (char *str, |
1320 | struct d30v_insn *opcode, | |
1321 | int shortp, | |
1322 | int is_parallel) | |
252b5132 | 1323 | { |
2132e3a3 AM |
1324 | char *op_start; |
1325 | char *save; | |
1326 | char *op_end; | |
2fd5405a NC |
1327 | char name[NAME_BUF_LEN]; |
1328 | int cmp_hack; | |
1329 | int nlen = 0; | |
1330 | int fsize = (shortp ? FORCE_SHORT : 0); | |
1331 | expressionS myops[6]; | |
1332 | long long insn; | |
1333 | ||
1334 | /* Drop leading whitespace. */ | |
1335 | while (*str == ' ') | |
1336 | str++; | |
1337 | ||
1338 | /* Find the opcode end. */ | |
2132e3a3 | 1339 | for (op_start = op_end = str; |
2fd5405a | 1340 | *op_end |
252b5132 | 1341 | && nlen < (NAME_BUF_LEN - 1) |
2fd5405a | 1342 | && *op_end != '/' |
2132e3a3 | 1343 | && !is_end_of_line[(unsigned char) *op_end] && *op_end != ' '; |
252b5132 RH |
1344 | op_end++) |
1345 | { | |
3882b010 | 1346 | name[nlen] = TOLOWER (op_start[nlen]); |
252b5132 RH |
1347 | nlen++; |
1348 | } | |
1349 | ||
1350 | if (nlen == 0) | |
1351 | return -1; | |
1352 | ||
1353 | name[nlen] = 0; | |
1354 | ||
2fd5405a | 1355 | /* If there is an execution condition code, handle it. */ |
252b5132 RH |
1356 | if (*op_end == '/') |
1357 | { | |
1358 | int i = 0; | |
2fd5405a | 1359 | while ((i < ECC_MAX) && strncasecmp (d30v_ecc_names[i], op_end + 1, 2)) |
252b5132 | 1360 | i++; |
2fd5405a | 1361 | |
252b5132 RH |
1362 | if (i == ECC_MAX) |
1363 | { | |
1364 | char tmp[4]; | |
1365 | strncpy (tmp, op_end + 1, 2); | |
1366 | tmp[2] = 0; | |
2fd5405a | 1367 | as_bad (_("unknown condition code: %s"), tmp); |
252b5132 RH |
1368 | return -1; |
1369 | } | |
252b5132 RH |
1370 | opcode->ecc = i; |
1371 | op_end += 3; | |
1372 | } | |
1373 | else | |
1374 | opcode->ecc = ECC_AL; | |
252b5132 | 1375 | |
2fd5405a | 1376 | /* CMP and CMPU change their name based on condition codes. */ |
252b5132 RH |
1377 | if (!strncmp (name, "cmp", 3)) |
1378 | { | |
2fd5405a NC |
1379 | int p, i; |
1380 | char **str = (char **) d30v_cc_names; | |
252b5132 RH |
1381 | if (name[3] == 'u') |
1382 | p = 4; | |
1383 | else | |
1384 | p = 3; | |
1385 | ||
2fd5405a | 1386 | for (i = 1; *str && strncmp (*str, &name[p], 2); i++, str++) |
252b5132 RH |
1387 | ; |
1388 | ||
2fd5405a | 1389 | /* cmpu only supports some condition codes. */ |
252b5132 RH |
1390 | if (p == 4) |
1391 | { | |
1392 | if (i < 3 || i > 6) | |
1393 | { | |
2fd5405a NC |
1394 | name[p + 2] = 0; |
1395 | as_bad (_("cmpu doesn't support condition code %s"), &name[p]); | |
252b5132 RH |
1396 | } |
1397 | } | |
1398 | ||
1399 | if (!*str) | |
1400 | { | |
2fd5405a NC |
1401 | name[p + 2] = 0; |
1402 | as_bad (_("unknown condition code: %s"), &name[p]); | |
252b5132 | 1403 | } |
2fd5405a | 1404 | |
252b5132 RH |
1405 | cmp_hack = i; |
1406 | name[p] = 0; | |
1407 | } | |
1408 | else | |
1409 | cmp_hack = 0; | |
252b5132 | 1410 | |
2fd5405a NC |
1411 | /* Need to look for .s or .l. */ |
1412 | if (name[nlen - 2] == '.') | |
252b5132 | 1413 | { |
2fd5405a | 1414 | switch (name[nlen - 1]) |
252b5132 RH |
1415 | { |
1416 | case 's': | |
1417 | fsize = FORCE_SHORT; | |
1418 | break; | |
1419 | case 'l': | |
1420 | fsize = FORCE_LONG; | |
1421 | break; | |
1422 | } | |
2fd5405a | 1423 | name[nlen - 2] = 0; |
252b5132 RH |
1424 | } |
1425 | ||
2fd5405a NC |
1426 | /* Find the first opcode with the proper name. */ |
1427 | opcode->op = (struct d30v_opcode *) hash_find (d30v_hash, name); | |
252b5132 RH |
1428 | if (opcode->op == NULL) |
1429 | { | |
2fd5405a | 1430 | as_bad (_("unknown opcode: %s"), name); |
252b5132 RH |
1431 | return -1; |
1432 | } | |
1433 | ||
1434 | save = input_line_pointer; | |
1435 | input_line_pointer = op_end; | |
1436 | while (!(opcode->form = find_format (opcode->op, myops, fsize, cmp_hack))) | |
1437 | { | |
1438 | opcode->op++; | |
1439 | if (opcode->op->name == NULL || strcmp (opcode->op->name, name)) | |
1440 | { | |
2fd5405a NC |
1441 | as_bad (_("operands for opcode `%s' do not match any valid format"), |
1442 | name); | |
252b5132 RH |
1443 | return -1; |
1444 | } | |
1445 | } | |
1446 | input_line_pointer = save; | |
1447 | ||
2fd5405a | 1448 | insn = build_insn (opcode, myops); |
252b5132 | 1449 | |
2d2255b5 | 1450 | /* Propagate multiply status. */ |
252b5132 RH |
1451 | if (insn != -1) |
1452 | { | |
1453 | if (is_parallel && prev_mul32_p) | |
1454 | cur_mul32_p = 1; | |
1455 | else | |
1456 | { | |
1457 | prev_mul32_p = cur_mul32_p; | |
1458 | cur_mul32_p = (opcode->op->flags_used & FLAG_MUL32) != 0; | |
1459 | } | |
1460 | } | |
1461 | ||
2fd5405a | 1462 | /* Propagate left_kills_right status. */ |
252b5132 RH |
1463 | if (insn != -1) |
1464 | { | |
1465 | prev_left_kills_right_p = cur_left_kills_right_p; | |
1466 | ||
1467 | if (opcode->op->flags_set & FLAG_LKR) | |
1468 | { | |
1469 | cur_left_kills_right_p = 1; | |
2fd5405a | 1470 | |
252b5132 RH |
1471 | if (strcmp (opcode->op->name, "mvtsys") == 0) |
1472 | { | |
2fd5405a NC |
1473 | /* Left kills right for only mvtsys only for |
1474 | PSW/PSWH/PSWL/flags target. */ | |
252b5132 RH |
1475 | if ((myops[0].X_op == O_register) && |
1476 | ((myops[0].X_add_number == OPERAND_CONTROL) || /* psw */ | |
1477 | (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+2) || /* pswh */ | |
1478 | (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+1) || /* pswl */ | |
1479 | (myops[0].X_add_number == OPERAND_FLAG+0) || /* f0 */ | |
1480 | (myops[0].X_add_number == OPERAND_FLAG+1) || /* f1 */ | |
1481 | (myops[0].X_add_number == OPERAND_FLAG+2) || /* f2 */ | |
1482 | (myops[0].X_add_number == OPERAND_FLAG+3) || /* f3 */ | |
1483 | (myops[0].X_add_number == OPERAND_FLAG+4) || /* f4 */ | |
1484 | (myops[0].X_add_number == OPERAND_FLAG+5) || /* f5 */ | |
1485 | (myops[0].X_add_number == OPERAND_FLAG+6) || /* f6 */ | |
1486 | (myops[0].X_add_number == OPERAND_FLAG+7))) /* f7 */ | |
1487 | { | |
1488 | cur_left_kills_right_p = 1; | |
1489 | } | |
1490 | else | |
1491 | { | |
2fd5405a NC |
1492 | /* Other mvtsys target registers don't kill right |
1493 | instruction. */ | |
252b5132 RH |
1494 | cur_left_kills_right_p = 0; |
1495 | } | |
1496 | } /* mvtsys */ | |
1497 | } | |
1498 | else | |
1499 | cur_left_kills_right_p = 0; | |
1500 | } | |
1501 | ||
1502 | return insn; | |
1503 | } | |
1504 | ||
ea1562b3 NC |
1505 | /* Called internally to handle all alignment needs. This takes care |
1506 | of eliding calls to frag_align if'n the cached current alignment | |
1507 | says we've already got it, as well as taking care of the auto-aligning | |
1508 | labels wrt code. */ | |
252b5132 | 1509 | |
ea1562b3 NC |
1510 | static void |
1511 | d30v_align (int n, char *pfill, symbolS *label) | |
252b5132 | 1512 | { |
ea1562b3 NC |
1513 | /* The front end is prone to changing segments out from under us |
1514 | temporarily when -g is in effect. */ | |
1515 | int switched_seg_p = (d30v_current_align_seg != now_seg); | |
2fd5405a | 1516 | |
ea1562b3 NC |
1517 | /* Do not assume that if 'd30v_current_align >= n' and |
1518 | '! switched_seg_p' that it is safe to avoid performing | |
1519 | this alignment request. The alignment of the current frag | |
1520 | can be changed under our feet, for example by a .ascii | |
1521 | directive in the source code. cf testsuite/gas/d30v/reloc.s */ | |
1522 | d30v_cleanup (FALSE); | |
252b5132 | 1523 | |
ea1562b3 | 1524 | if (pfill == NULL) |
252b5132 | 1525 | { |
ea1562b3 NC |
1526 | if (n > 2 |
1527 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
1528 | { | |
1529 | static char const nop[4] = { 0x00, 0xf0, 0x00, 0x00 }; | |
252b5132 | 1530 | |
ea1562b3 NC |
1531 | /* First, make sure we're on a four-byte boundary, in case |
1532 | someone has been putting .byte values the text section. */ | |
1533 | if (d30v_current_align < 2 || switched_seg_p) | |
1534 | frag_align (2, 0, 0); | |
1535 | frag_align_pattern (n, nop, sizeof nop, 0); | |
1536 | } | |
1537 | else | |
1538 | frag_align (n, 0, 0); | |
1539 | } | |
1540 | else | |
1541 | frag_align (n, *pfill, 0); | |
252b5132 | 1542 | |
ea1562b3 NC |
1543 | if (!switched_seg_p) |
1544 | d30v_current_align = n; | |
2fd5405a | 1545 | |
ea1562b3 NC |
1546 | if (label != NULL) |
1547 | { | |
1548 | symbolS *sym; | |
1549 | int label_seen = FALSE; | |
1550 | struct frag *old_frag; | |
1551 | valueT old_value; | |
1552 | valueT new_value; | |
252b5132 | 1553 | |
ea1562b3 | 1554 | assert (S_GET_SEGMENT (label) == now_seg); |
2fd5405a | 1555 | |
ea1562b3 NC |
1556 | old_frag = symbol_get_frag (label); |
1557 | old_value = S_GET_VALUE (label); | |
1558 | new_value = (valueT) frag_now_fix (); | |
252b5132 | 1559 | |
ea1562b3 NC |
1560 | /* It is possible to have more than one label at a particular |
1561 | address, especially if debugging is enabled, so we must | |
1562 | take care to adjust all the labels at this address in this | |
1563 | fragment. To save time we search from the end of the symbol | |
1564 | list, backwards, since the symbols we are interested in are | |
1565 | almost certainly the ones that were most recently added. | |
1566 | Also to save time we stop searching once we have seen at least | |
1567 | one matching label, and we encounter a label that is no longer | |
1568 | in the target fragment. Note, this search is guaranteed to | |
1569 | find at least one match when sym == label, so no special case | |
1570 | code is necessary. */ | |
1571 | for (sym = symbol_lastP; sym != NULL; sym = symbol_previous (sym)) | |
1572 | { | |
1573 | if (symbol_get_frag (sym) == old_frag | |
1574 | && S_GET_VALUE (sym) == old_value) | |
1575 | { | |
1576 | label_seen = TRUE; | |
1577 | symbol_set_frag (sym, frag_now); | |
1578 | S_SET_VALUE (sym, new_value); | |
1579 | } | |
1580 | else if (label_seen && symbol_get_frag (sym) != old_frag) | |
1581 | break; | |
1582 | } | |
1583 | } | |
2fd5405a | 1584 | |
ea1562b3 NC |
1585 | record_alignment (now_seg, n); |
1586 | } | |
252b5132 | 1587 | |
ea1562b3 NC |
1588 | /* This is the main entry point for the machine-dependent assembler. |
1589 | STR points to a machine-dependent instruction. This function is | |
1590 | supposed to emit the frags/bytes it assembles to. For the D30V, it | |
1591 | mostly handles the special VLIW parsing and packing and leaves the | |
1592 | difficult stuff to do_assemble (). */ | |
1593 | ||
1594 | static long long prev_insn = -1; | |
1595 | static struct d30v_insn prev_opcode; | |
1596 | static subsegT prev_subseg; | |
1597 | static segT prev_seg = 0; | |
1598 | ||
1599 | void | |
1600 | md_assemble (char *str) | |
1601 | { | |
1602 | struct d30v_insn opcode; | |
1603 | long long insn; | |
1604 | /* Execution type; parallel, etc. */ | |
1605 | exec_type_enum extype = EXEC_UNKNOWN; | |
1606 | /* Saved extype. Used for multiline instructions. */ | |
1607 | static exec_type_enum etype = EXEC_UNKNOWN; | |
1608 | char *str2; | |
1609 | ||
1610 | if ((prev_insn != -1) && prev_seg | |
1611 | && ((prev_seg != now_seg) || (prev_subseg != now_subseg))) | |
1612 | d30v_cleanup (FALSE); | |
1613 | ||
1614 | if (d30v_current_align < 3) | |
1615 | d30v_align (3, NULL, d30v_last_label); | |
1616 | else if (d30v_current_align > 3) | |
1617 | d30v_current_align = 3; | |
1618 | d30v_last_label = NULL; | |
1619 | ||
1620 | flag_explicitly_parallel = 0; | |
1621 | flag_xp_state = 0; | |
1622 | if (etype == EXEC_UNKNOWN) | |
1623 | { | |
1624 | /* Look for the special multiple instruction separators. */ | |
1625 | str2 = strstr (str, "||"); | |
1626 | if (str2) | |
1627 | { | |
1628 | extype = EXEC_PARALLEL; | |
1629 | flag_xp_state = 1; | |
1630 | } | |
1631 | else | |
1632 | { | |
1633 | str2 = strstr (str, "->"); | |
1634 | if (str2) | |
1635 | extype = EXEC_SEQ; | |
1636 | else | |
1637 | { | |
1638 | str2 = strstr (str, "<-"); | |
1639 | if (str2) | |
1640 | extype = EXEC_REVSEQ; | |
1641 | } | |
1642 | } | |
1643 | ||
1644 | /* STR2 points to the separator, if one. */ | |
1645 | if (str2) | |
1646 | { | |
1647 | *str2 = 0; | |
1648 | ||
1649 | /* If two instructions are present and we already have one saved, | |
1650 | then first write it out. */ | |
1651 | d30v_cleanup (FALSE); | |
1652 | ||
1653 | /* Assemble first instruction and save it. */ | |
1654 | prev_insn = do_assemble (str, &prev_opcode, 1, 0); | |
1655 | if (prev_insn == -1) | |
1656 | as_bad (_("Cannot assemble instruction")); | |
1657 | if (prev_opcode.form != NULL && prev_opcode.form->form >= LONG) | |
1658 | as_bad (_("First opcode is long. Unable to mix instructions as specified.")); | |
1659 | fixups = fixups->next; | |
1660 | str = str2 + 2; | |
1661 | prev_seg = now_seg; | |
1662 | prev_subseg = now_subseg; | |
1663 | } | |
1664 | } | |
1665 | ||
1666 | insn = do_assemble (str, &opcode, | |
1667 | (extype != EXEC_UNKNOWN || etype != EXEC_UNKNOWN), | |
1668 | extype == EXEC_PARALLEL); | |
1669 | if (insn == -1) | |
1670 | { | |
1671 | if (extype != EXEC_UNKNOWN) | |
1672 | etype = extype; | |
1673 | as_bad (_("Cannot assemble instruction")); | |
1674 | return; | |
1675 | } | |
1676 | ||
1677 | if (etype != EXEC_UNKNOWN) | |
1678 | { | |
1679 | extype = etype; | |
1680 | etype = EXEC_UNKNOWN; | |
1681 | } | |
1682 | ||
1683 | /* Word multiply instructions must not be followed by either a load or a | |
1684 | 16-bit multiply instruction in the next cycle. */ | |
1685 | if ( (extype != EXEC_REVSEQ) | |
1686 | && prev_mul32_p | |
1687 | && (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16))) | |
1688 | { | |
1689 | /* However, load and multiply should able to be combined in a parallel | |
1690 | operation, so check for that first. */ | |
1691 | if (prev_insn != -1 | |
1692 | && (opcode.op->flags_used & FLAG_MEM) | |
1693 | && opcode.form->form < LONG | |
1694 | && (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN)) | |
1695 | && parallel_ok (&prev_opcode, (long) prev_insn, | |
1696 | &opcode, (long) insn, extype) | |
1697 | && write_2_short (&prev_opcode, (long) prev_insn, | |
1698 | &opcode, (long) insn, extype, fixups) == 0) | |
1699 | { | |
1700 | /* No instructions saved. */ | |
1701 | prev_insn = -1; | |
1702 | return; | |
1703 | } | |
1704 | else | |
1705 | { | |
1706 | /* Can't parallelize, flush previous instruction and emit a | |
1707 | word of NOPS, unless the previous instruction is a NOP, | |
1708 | in which case just flush it, as this will generate a word | |
1709 | of NOPs for us. */ | |
1710 | ||
1711 | if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0)) | |
1712 | d30v_cleanup (FALSE); | |
1713 | else | |
1714 | { | |
1715 | char *f; | |
1716 | ||
1717 | if (prev_insn != -1) | |
1718 | d30v_cleanup (TRUE); | |
1719 | else | |
1720 | { | |
1721 | f = frag_more (8); | |
1722 | d30v_number_to_chars (f, NOP2, 8); | |
1723 | ||
1724 | if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY) | |
1725 | { | |
1726 | if (opcode.op->flags_used & FLAG_MEM) | |
1727 | as_warn (_("word of NOPs added between word multiply and load")); | |
1728 | else | |
1729 | as_warn (_("word of NOPs added between word multiply and 16-bit multiply")); | |
252b5132 | 1730 | } |
252b5132 RH |
1731 | } |
1732 | } | |
252b5132 | 1733 | |
ea1562b3 NC |
1734 | extype = EXEC_UNKNOWN; |
1735 | } | |
1736 | } | |
1737 | else if ( (extype == EXEC_REVSEQ) | |
1738 | && cur_mul32_p | |
1739 | && (prev_opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16))) | |
1740 | { | |
1741 | /* Can't parallelize, flush current instruction and add a | |
1742 | sequential NOP. */ | |
1743 | write_1_short (&opcode, (long) insn, fixups->next->next, TRUE); | |
1744 | ||
1745 | /* Make the previous instruction the current one. */ | |
1746 | extype = EXEC_UNKNOWN; | |
1747 | insn = prev_insn; | |
1748 | now_seg = prev_seg; | |
1749 | now_subseg = prev_subseg; | |
1750 | prev_insn = -1; | |
1751 | cur_mul32_p = prev_mul32_p; | |
1752 | prev_mul32_p = 0; | |
1753 | memcpy (&opcode, &prev_opcode, sizeof (prev_opcode)); | |
1754 | } | |
1755 | ||
1756 | /* If this is a long instruction, write it and any previous short | |
1757 | instruction. */ | |
1758 | if (opcode.form->form >= LONG) | |
1759 | { | |
1760 | if (extype != EXEC_UNKNOWN) | |
1761 | as_bad (_("Instruction uses long version, so it cannot be mixed as specified")); | |
1762 | d30v_cleanup (FALSE); | |
1763 | write_long (&opcode, insn, fixups); | |
1764 | prev_insn = -1; | |
1765 | } | |
1766 | else if ((prev_insn != -1) | |
1767 | && (write_2_short | |
1768 | (&prev_opcode, (long) prev_insn, &opcode, | |
1769 | (long) insn, extype, fixups) == 0)) | |
1770 | { | |
1771 | /* No instructions saved. */ | |
1772 | prev_insn = -1; | |
1773 | } | |
1774 | else | |
1775 | { | |
1776 | if (extype != EXEC_UNKNOWN) | |
1777 | as_bad (_("Unable to mix instructions as specified")); | |
1778 | ||
1779 | /* Save off last instruction so it may be packed on next pass. */ | |
1780 | memcpy (&prev_opcode, &opcode, sizeof (prev_opcode)); | |
1781 | prev_insn = insn; | |
1782 | prev_seg = now_seg; | |
1783 | prev_subseg = now_subseg; | |
1784 | fixups = fixups->next; | |
1785 | prev_mul32_p = cur_mul32_p; | |
1786 | } | |
1787 | } | |
1788 | ||
1789 | /* If while processing a fixup, a reloc really needs to be created, | |
1790 | then it is done here. */ | |
1791 | ||
1792 | arelent * | |
1793 | tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) | |
1794 | { | |
1795 | arelent *reloc; | |
1796 | reloc = xmalloc (sizeof (arelent)); | |
1797 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); | |
1798 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
1799 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1800 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
1801 | if (reloc->howto == NULL) | |
1802 | { | |
1803 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1804 | _("reloc %d not supported by object file format"), | |
1805 | (int) fixp->fx_r_type); | |
1806 | return NULL; | |
1807 | } | |
1808 | ||
1809 | reloc->addend = 0; | |
1810 | return reloc; | |
1811 | } | |
1812 | ||
1813 | int | |
1814 | md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, | |
1815 | asection *seg ATTRIBUTE_UNUSED) | |
1816 | { | |
1817 | abort (); | |
1818 | return 0; | |
1819 | } | |
1820 | ||
1821 | long | |
1822 | md_pcrel_from_section (fixS *fixp, segT sec) | |
1823 | { | |
1824 | if (fixp->fx_addsy != (symbolS *) NULL | |
1825 | && (!S_IS_DEFINED (fixp->fx_addsy) | |
1826 | || (S_GET_SEGMENT (fixp->fx_addsy) != sec))) | |
1827 | return 0; | |
1828 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
1829 | } | |
1830 | ||
1831 | /* Called after the assembler has finished parsing the input file or | |
1832 | after a label is defined. Because the D30V assembler sometimes | |
1833 | saves short instructions to see if it can package them with the | |
1834 | next instruction, there may be a short instruction that still needs | |
1835 | written. */ | |
1836 | ||
1837 | int | |
1838 | d30v_cleanup (int use_sequential) | |
1839 | { | |
1840 | segT seg; | |
1841 | subsegT subseg; | |
1842 | ||
1843 | if (prev_insn != -1) | |
1844 | { | |
1845 | seg = now_seg; | |
1846 | subseg = now_subseg; | |
1847 | subseg_set (prev_seg, prev_subseg); | |
1848 | write_1_short (&prev_opcode, (long) prev_insn, fixups->next, | |
1849 | use_sequential); | |
1850 | subseg_set (seg, subseg); | |
1851 | prev_insn = -1; | |
1852 | if (use_sequential) | |
1853 | prev_mul32_p = FALSE; | |
1854 | } | |
1855 | ||
1856 | return 1; | |
1857 | } | |
1858 | ||
1859 | /* This function is called at the start of every line. It checks to | |
1860 | see if the first character is a '.', which indicates the start of a | |
1861 | pseudo-op. If it is, then write out any unwritten instructions. */ | |
1862 | ||
1863 | void | |
1864 | d30v_start_line (void) | |
1865 | { | |
1866 | char *c = input_line_pointer; | |
1867 | ||
1868 | while (ISSPACE (*c)) | |
1869 | c++; | |
1870 | ||
1871 | if (*c == '.') | |
1872 | d30v_cleanup (FALSE); | |
1873 | } | |
1874 | ||
1875 | static void | |
1876 | check_size (long value, int bits, char *file, int line) | |
1877 | { | |
1878 | int tmp, max; | |
1879 | ||
1880 | if (value < 0) | |
1881 | tmp = ~value; | |
1882 | else | |
1883 | tmp = value; | |
1884 | ||
1885 | max = (1 << (bits - 1)) - 1; | |
2fd5405a | 1886 | |
ea1562b3 NC |
1887 | if (tmp > max) |
1888 | as_bad_where (file, line, _("value too large to fit in %d bits"), bits); | |
252b5132 RH |
1889 | } |
1890 | ||
ea1562b3 | 1891 | /* d30v_frob_label() is called when after a label is recognized. */ |
2fd5405a | 1892 | |
ea1562b3 NC |
1893 | void |
1894 | d30v_frob_label (symbolS *lab) | |
252b5132 | 1895 | { |
ea1562b3 NC |
1896 | /* Emit any pending instructions. */ |
1897 | d30v_cleanup (FALSE); | |
a161fe53 | 1898 | |
ea1562b3 NC |
1899 | /* Update the label's address with the current output pointer. */ |
1900 | symbol_set_frag (lab, frag_now); | |
1901 | S_SET_VALUE (lab, (valueT) frag_now_fix ()); | |
252b5132 | 1902 | |
ea1562b3 NC |
1903 | /* Record this label for future adjustment after we find out what |
1904 | kind of data it references, and the required alignment therewith. */ | |
1905 | d30v_last_label = lab; | |
2fd5405a | 1906 | } |
252b5132 | 1907 | |
ea1562b3 NC |
1908 | /* Hook into cons for capturing alignment changes. */ |
1909 | ||
1910 | void | |
1911 | d30v_cons_align (int size) | |
252b5132 | 1912 | { |
ea1562b3 NC |
1913 | int log_size; |
1914 | ||
1915 | log_size = 0; | |
1916 | while ((size >>= 1) != 0) | |
1917 | ++log_size; | |
1918 | ||
1919 | if (d30v_current_align < log_size) | |
1920 | d30v_align (log_size, (char *) NULL, NULL); | |
1921 | else if (d30v_current_align > log_size) | |
1922 | d30v_current_align = log_size; | |
1923 | d30v_last_label = NULL; | |
252b5132 RH |
1924 | } |
1925 | ||
94f592af | 1926 | void |
ea1562b3 | 1927 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 1928 | { |
2fd5405a | 1929 | char *where; |
252b5132 | 1930 | unsigned long insn, insn2; |
a161fe53 | 1931 | long value = *valP; |
94f592af NC |
1932 | |
1933 | if (fixP->fx_addsy == (symbolS *) NULL) | |
1934 | fixP->fx_done = 1; | |
1935 | ||
a161fe53 AM |
1936 | /* We don't support subtracting a symbol. */ |
1937 | if (fixP->fx_subsy != (symbolS *) NULL) | |
1938 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
2fd5405a | 1939 | |
252b5132 RH |
1940 | /* Fetch the instruction, insert the fully resolved operand |
1941 | value, and stuff the instruction back again. */ | |
94f592af | 1942 | where = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 1943 | insn = bfd_getb32 ((unsigned char *) where); |
2fd5405a | 1944 | |
94f592af | 1945 | switch (fixP->fx_r_type) |
252b5132 RH |
1946 | { |
1947 | case BFD_RELOC_8: /* Check for a bad .byte directive. */ | |
94f592af | 1948 | if (fixP->fx_addsy != NULL) |
252b5132 | 1949 | as_bad (_("line %d: unable to place address of symbol '%s' into a byte"), |
94f592af | 1950 | fixP->fx_line, S_GET_NAME (fixP->fx_addsy)); |
252b5132 | 1951 | else if (((unsigned)value) > 0xff) |
ebf19f1b | 1952 | as_bad (_("line %d: unable to place value %lx into a byte"), |
94f592af | 1953 | fixP->fx_line, value); |
252b5132 | 1954 | else |
2fd5405a | 1955 | *(unsigned char *) where = value; |
252b5132 | 1956 | break; |
2fd5405a | 1957 | |
252b5132 | 1958 | case BFD_RELOC_16: /* Check for a bad .short directive. */ |
94f592af | 1959 | if (fixP->fx_addsy != NULL) |
252b5132 | 1960 | as_bad (_("line %d: unable to place address of symbol '%s' into a short"), |
94f592af | 1961 | fixP->fx_line, S_GET_NAME (fixP->fx_addsy)); |
252b5132 | 1962 | else if (((unsigned)value) > 0xffff) |
ebf19f1b | 1963 | as_bad (_("line %d: unable to place value %lx into a short"), |
94f592af | 1964 | fixP->fx_line, value); |
252b5132 RH |
1965 | else |
1966 | bfd_putb16 ((bfd_vma) value, (unsigned char *) where); | |
1967 | break; | |
2fd5405a | 1968 | |
252b5132 | 1969 | case BFD_RELOC_64: /* Check for a bad .quad directive. */ |
94f592af | 1970 | if (fixP->fx_addsy != NULL) |
252b5132 | 1971 | as_bad (_("line %d: unable to place address of symbol '%s' into a quad"), |
94f592af | 1972 | fixP->fx_line, S_GET_NAME (fixP->fx_addsy)); |
252b5132 RH |
1973 | else |
1974 | { | |
1975 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); | |
1976 | bfd_putb32 (0, ((unsigned char *) where) + 4); | |
1977 | } | |
1978 | break; | |
2fd5405a | 1979 | |
252b5132 | 1980 | case BFD_RELOC_D30V_6: |
94f592af | 1981 | check_size (value, 6, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
1982 | insn |= value & 0x3F; |
1983 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1984 | break; | |
1985 | ||
1986 | case BFD_RELOC_D30V_9_PCREL: | |
94f592af | 1987 | if (fixP->fx_where & 0x7) |
252b5132 | 1988 | { |
94f592af | 1989 | if (fixP->fx_done) |
252b5132 RH |
1990 | value += 4; |
1991 | else | |
94f592af | 1992 | fixP->fx_r_type = BFD_RELOC_D30V_9_PCREL_R; |
252b5132 | 1993 | } |
94f592af | 1994 | check_size (value, 9, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
1995 | insn |= ((value >> 3) & 0x3F) << 12; |
1996 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1997 | break; | |
1998 | ||
1999 | case BFD_RELOC_D30V_15: | |
94f592af | 2000 | check_size (value, 15, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
2001 | insn |= (value >> 3) & 0xFFF; |
2002 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
2003 | break; | |
2004 | ||
2005 | case BFD_RELOC_D30V_15_PCREL: | |
94f592af | 2006 | if (fixP->fx_where & 0x7) |
252b5132 | 2007 | { |
94f592af | 2008 | if (fixP->fx_done) |
252b5132 RH |
2009 | value += 4; |
2010 | else | |
94f592af | 2011 | fixP->fx_r_type = BFD_RELOC_D30V_15_PCREL_R; |
252b5132 | 2012 | } |
94f592af | 2013 | check_size (value, 15, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
2014 | insn |= (value >> 3) & 0xFFF; |
2015 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
2016 | break; | |
2017 | ||
2018 | case BFD_RELOC_D30V_21: | |
94f592af | 2019 | check_size (value, 21, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
2020 | insn |= (value >> 3) & 0x3FFFF; |
2021 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
2022 | break; | |
2023 | ||
2024 | case BFD_RELOC_D30V_21_PCREL: | |
94f592af | 2025 | if (fixP->fx_where & 0x7) |
252b5132 | 2026 | { |
94f592af | 2027 | if (fixP->fx_done) |
252b5132 RH |
2028 | value += 4; |
2029 | else | |
94f592af | 2030 | fixP->fx_r_type = BFD_RELOC_D30V_21_PCREL_R; |
252b5132 | 2031 | } |
94f592af | 2032 | check_size (value, 21, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
2033 | insn |= (value >> 3) & 0x3FFFF; |
2034 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
2035 | break; | |
2036 | ||
2037 | case BFD_RELOC_D30V_32: | |
2038 | insn2 = bfd_getb32 ((unsigned char *) where + 4); | |
2fd5405a NC |
2039 | insn |= (value >> 26) & 0x3F; /* Top 6 bits. */ |
2040 | insn2 |= ((value & 0x03FC0000) << 2); /* Next 8 bits. */ | |
2041 | insn2 |= value & 0x0003FFFF; /* Bottom 18 bits. */ | |
252b5132 RH |
2042 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); |
2043 | bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4); | |
2044 | break; | |
2045 | ||
2046 | case BFD_RELOC_D30V_32_PCREL: | |
2047 | insn2 = bfd_getb32 ((unsigned char *) where + 4); | |
81d4177b KH |
2048 | insn |= (value >> 26) & 0x3F; /* Top 6 bits. */ |
2049 | insn2 |= ((value & 0x03FC0000) << 2); /* Next 8 bits. */ | |
2050 | insn2 |= value & 0x0003FFFF; /* Bottom 18 bits. */ | |
252b5132 RH |
2051 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); |
2052 | bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4); | |
2053 | break; | |
2054 | ||
2055 | case BFD_RELOC_32: | |
2056 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); | |
2057 | break; | |
2058 | ||
2059 | default: | |
2060 | as_bad (_("line %d: unknown relocation type: 0x%x"), | |
94f592af | 2061 | fixP->fx_line, fixP->fx_r_type); |
252b5132 | 2062 | } |
252b5132 RH |
2063 | } |
2064 | ||
252b5132 RH |
2065 | /* Handle the .align pseudo-op. This aligns to a power of two. We |
2066 | hook here to latch the current alignment. */ | |
2067 | ||
2068 | static void | |
ea1562b3 | 2069 | s_d30v_align (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
2070 | { |
2071 | int align; | |
2072 | char fill, *pfill = NULL; | |
2073 | long max_alignment = 15; | |
2074 | ||
2075 | align = get_absolute_expression (); | |
2076 | if (align > max_alignment) | |
2077 | { | |
2078 | align = max_alignment; | |
2079 | as_warn (_("Alignment too large: %d assumed"), align); | |
2080 | } | |
2081 | else if (align < 0) | |
2082 | { | |
2083 | as_warn (_("Alignment negative: 0 assumed")); | |
2084 | align = 0; | |
2085 | } | |
2086 | ||
2087 | if (*input_line_pointer == ',') | |
2088 | { | |
2089 | input_line_pointer++; | |
2090 | fill = get_absolute_expression (); | |
2091 | pfill = &fill; | |
2092 | } | |
2093 | ||
2094 | d30v_last_label = NULL; | |
2095 | d30v_align (align, pfill, NULL); | |
2096 | ||
2097 | demand_empty_rest_of_line (); | |
2098 | } | |
2099 | ||
2100 | /* Handle the .text pseudo-op. This is like the usual one, but it | |
2101 | clears the saved last label and resets known alignment. */ | |
2102 | ||
2103 | static void | |
ea1562b3 | 2104 | s_d30v_text (int i) |
252b5132 RH |
2105 | |
2106 | { | |
2107 | s_text (i); | |
2108 | d30v_last_label = NULL; | |
2109 | d30v_current_align = 0; | |
2110 | d30v_current_align_seg = now_seg; | |
2111 | } | |
2112 | ||
2113 | /* Handle the .data pseudo-op. This is like the usual one, but it | |
2114 | clears the saved last label and resets known alignment. */ | |
2115 | ||
2116 | static void | |
ea1562b3 | 2117 | s_d30v_data (int i) |
252b5132 RH |
2118 | { |
2119 | s_data (i); | |
2120 | d30v_last_label = NULL; | |
2121 | d30v_current_align = 0; | |
2122 | d30v_current_align_seg = now_seg; | |
2123 | } | |
2124 | ||
2125 | /* Handle the .section pseudo-op. This is like the usual one, but it | |
2126 | clears the saved last label and resets known alignment. */ | |
2127 | ||
2128 | static void | |
ea1562b3 | 2129 | s_d30v_section (int ignore) |
252b5132 RH |
2130 | { |
2131 | obj_elf_section (ignore); | |
2132 | d30v_last_label = NULL; | |
2133 | d30v_current_align = 0; | |
2134 | d30v_current_align_seg = now_seg; | |
2135 | } | |
ea1562b3 NC |
2136 | |
2137 | /* The target specific pseudo-ops which we support. */ | |
2138 | const pseudo_typeS md_pseudo_table[] = | |
2139 | { | |
2140 | { "word", cons, 4 }, | |
2141 | { "hword", cons, 2 }, | |
2142 | { "align", s_d30v_align, 0 }, | |
2143 | { "text", s_d30v_text, 0 }, | |
2144 | { "data", s_d30v_data, 0 }, | |
2145 | { "section", s_d30v_section, 0 }, | |
2146 | { "section.s", s_d30v_section, 0 }, | |
2147 | { "sect", s_d30v_section, 0 }, | |
2148 | { "sect.s", s_d30v_section, 0 }, | |
2149 | { NULL, NULL, 0 } | |
2150 | }; | |
2151 |