Commit | Line | Data |
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252b5132 | 1 | /* tc-d30v.c -- Assembler code for the Mitsubishi D30V |
aa820537 | 2 | Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, |
87975d2a | 3 | 2009, 2010 Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
10 | any later version. |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
19 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
20 | Boston, MA 02110-1301, USA. */ | |
252b5132 | 21 | |
252b5132 | 22 | #include "as.h" |
3882b010 | 23 | #include "safe-ctype.h" |
2fd5405a | 24 | #include "subsegs.h" |
252b5132 | 25 | #include "opcode/d30v.h" |
d4f4f3fb | 26 | #include "dwarf2dbg.h" |
252b5132 | 27 | |
ea1562b3 NC |
28 | const char comment_chars[] = ";"; |
29 | const char line_comment_chars[] = "#"; | |
252b5132 | 30 | const char line_separator_chars[] = ""; |
ea1562b3 NC |
31 | const char *md_shortopts = "OnNcC"; |
32 | const char EXP_CHARS[] = "eE"; | |
33 | const char FLT_CHARS[] = "dD"; | |
252b5132 | 34 | |
ba09cd8d DN |
35 | #if HAVE_LIMITS_H |
36 | #include <limits.h> | |
37 | #endif | |
38 | ||
39 | #ifndef CHAR_BIT | |
40 | #define CHAR_BIT 8 | |
41 | #endif | |
42 | ||
252b5132 RH |
43 | #define NOP_MULTIPLY 1 |
44 | #define NOP_ALL 2 | |
45 | static int warn_nops = 0; | |
46 | static int Optimizing = 0; | |
47 | static int warn_register_name_conflicts = 1; | |
48 | ||
49 | #define FORCE_SHORT 1 | |
50 | #define FORCE_LONG 2 | |
51 | ||
52 | /* EXEC types. */ | |
53 | typedef enum _exec_type | |
54 | { | |
ea1562b3 NC |
55 | EXEC_UNKNOWN, /* No order specified. */ |
56 | EXEC_PARALLEL, /* Done in parallel (FM=00). */ | |
57 | EXEC_SEQ, /* Sequential (FM=01). */ | |
58 | EXEC_REVSEQ /* Reverse sequential (FM=10). */ | |
252b5132 RH |
59 | } exec_type_enum; |
60 | ||
2fd5405a | 61 | /* Fixups. */ |
ea1562b3 NC |
62 | #define MAX_INSN_FIXUPS 5 |
63 | ||
252b5132 RH |
64 | struct d30v_fixup |
65 | { | |
66 | expressionS exp; | |
67 | int operand; | |
68 | int pcrel; | |
69 | int size; | |
70 | bfd_reloc_code_real_type reloc; | |
71 | }; | |
72 | ||
73 | typedef struct _fixups | |
74 | { | |
75 | int fc; | |
76 | struct d30v_fixup fix[MAX_INSN_FIXUPS]; | |
77 | struct _fixups *next; | |
78 | } Fixups; | |
79 | ||
80 | static Fixups FixUps[2]; | |
81 | static Fixups *fixups; | |
82 | ||
83 | /* Whether current and previous instruction are word multiply insns. */ | |
84 | static int cur_mul32_p = 0; | |
85 | static int prev_mul32_p = 0; | |
86 | ||
87 | /* The flag_explicitly_parallel is true iff the instruction being assembled | |
88 | has been explicitly written as a parallel short-instruction pair by the | |
2fd5405a | 89 | human programmer. It is used in parallel_ok () to distinguish between |
252b5132 RH |
90 | those dangerous parallelizations attempted by the human, which are to be |
91 | allowed, and those attempted by the assembler, which are not. It is set | |
2fd5405a NC |
92 | from md_assemble (). */ |
93 | static int flag_explicitly_parallel = 0; | |
252b5132 RH |
94 | static int flag_xp_state = 0; |
95 | ||
96 | /* Whether current and previous left sub-instruction disables | |
97 | execution of right sub-instruction. */ | |
98 | static int cur_left_kills_right_p = 0; | |
99 | static int prev_left_kills_right_p = 0; | |
100 | ||
101 | /* The known current alignment of the current section. */ | |
102 | static int d30v_current_align; | |
103 | static segT d30v_current_align_seg; | |
104 | ||
105 | /* The last seen label in the current section. This is used to auto-align | |
2d2255b5 | 106 | labels preceding instructions. */ |
252b5132 RH |
107 | static symbolS *d30v_last_label; |
108 | ||
2fd5405a | 109 | /* Two nops. */ |
252b5132 RH |
110 | #define NOP_LEFT ((long long) NOP << 32) |
111 | #define NOP_RIGHT ((long long) NOP) | |
112 | #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT) | |
113 | ||
2fd5405a NC |
114 | struct option md_longopts[] = |
115 | { | |
252b5132 RH |
116 | {NULL, no_argument, NULL, 0} |
117 | }; | |
252b5132 | 118 | |
2fd5405a | 119 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 120 | |
252b5132 RH |
121 | /* Opcode hash table. */ |
122 | static struct hash_control *d30v_hash; | |
123 | ||
2fd5405a NC |
124 | /* Do a binary search of the pre_defined_registers array to see if |
125 | NAME is a valid regiter name. Return the register number from the | |
126 | array on success, or -1 on failure. */ | |
252b5132 RH |
127 | |
128 | static int | |
ea1562b3 | 129 | reg_name_search (char *name) |
252b5132 RH |
130 | { |
131 | int middle, low, high; | |
132 | int cmp; | |
133 | ||
134 | low = 0; | |
135 | high = reg_name_cnt () - 1; | |
136 | ||
137 | do | |
138 | { | |
139 | middle = (low + high) / 2; | |
140 | cmp = strcasecmp (name, pre_defined_registers[middle].name); | |
141 | if (cmp < 0) | |
142 | high = middle - 1; | |
143 | else if (cmp > 0) | |
144 | low = middle + 1; | |
145 | else | |
146 | { | |
147 | if (symbol_find (name) != NULL) | |
148 | { | |
149 | if (warn_register_name_conflicts) | |
150 | as_warn (_("Register name %s conflicts with symbol of the same name"), | |
151 | name); | |
152 | } | |
2fd5405a | 153 | |
252b5132 RH |
154 | return pre_defined_registers[middle].value; |
155 | } | |
156 | } | |
157 | while (low <= high); | |
2fd5405a | 158 | |
252b5132 RH |
159 | return -1; |
160 | } | |
161 | ||
2fd5405a NC |
162 | /* Check the string at input_line_pointer to see if it is a valid |
163 | register name. */ | |
252b5132 RH |
164 | |
165 | static int | |
ea1562b3 | 166 | register_name (expressionS *expressionP) |
252b5132 RH |
167 | { |
168 | int reg_number; | |
169 | char c, *p = input_line_pointer; | |
2fd5405a NC |
170 | |
171 | while (*p && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')') | |
252b5132 RH |
172 | p++; |
173 | ||
174 | c = *p; | |
175 | if (c) | |
176 | *p++ = 0; | |
177 | ||
2fd5405a | 178 | /* Look to see if it's in the register table. */ |
252b5132 | 179 | reg_number = reg_name_search (input_line_pointer); |
2fd5405a | 180 | if (reg_number >= 0) |
252b5132 RH |
181 | { |
182 | expressionP->X_op = O_register; | |
2fd5405a NC |
183 | /* Temporarily store a pointer to the string here. */ |
184 | expressionP->X_op_symbol = (symbolS *) input_line_pointer; | |
252b5132 RH |
185 | expressionP->X_add_number = reg_number; |
186 | input_line_pointer = p; | |
187 | return 1; | |
188 | } | |
189 | if (c) | |
2fd5405a | 190 | *(p - 1) = c; |
252b5132 RH |
191 | return 0; |
192 | } | |
193 | ||
252b5132 | 194 | static int |
ea1562b3 | 195 | check_range (unsigned long num, int bits, int flags) |
252b5132 RH |
196 | { |
197 | long min, max; | |
252b5132 | 198 | |
bf80011a RH |
199 | /* Don't bother checking 32-bit values. */ |
200 | if (bits == 32) | |
201 | { | |
2fd5405a | 202 | if (sizeof (unsigned long) * CHAR_BIT == 32) |
cc8a6dd0 | 203 | return 0; |
bf80011a RH |
204 | |
205 | /* We don't record signed or unsigned for 32-bit quantities. | |
206 | Allow either. */ | |
2fd5405a NC |
207 | min = -((unsigned long) 1 << (bits - 1)); |
208 | max = ((unsigned long) 1 << bits) - 1; | |
30cdfbed | 209 | return (long) num < min || (long) num > max; |
bf80011a | 210 | } |
252b5132 RH |
211 | |
212 | if (flags & OPERAND_SHIFT) | |
213 | { | |
2fd5405a | 214 | /* We know that all shifts are right by three bits. */ |
30cdfbed | 215 | num >>= 3; |
2fd5405a | 216 | |
252b5132 | 217 | if (flags & OPERAND_SIGNED) |
30cdfbed AM |
218 | { |
219 | unsigned long sign_bit = ((unsigned long) -1L >> 4) + 1; | |
220 | num = (num ^ sign_bit) - sign_bit; | |
221 | } | |
252b5132 RH |
222 | } |
223 | ||
224 | if (flags & OPERAND_SIGNED) | |
225 | { | |
2fd5405a NC |
226 | max = ((unsigned long) 1 << (bits - 1)) - 1; |
227 | min = - ((unsigned long) 1 << (bits - 1)); | |
30cdfbed | 228 | return (long) num > max || (long) num < min; |
252b5132 RH |
229 | } |
230 | else | |
231 | { | |
2fd5405a | 232 | max = ((unsigned long) 1 << bits) - 1; |
30cdfbed | 233 | return num > (unsigned long) max; |
252b5132 | 234 | } |
252b5132 RH |
235 | } |
236 | ||
252b5132 | 237 | void |
ea1562b3 | 238 | md_show_usage (FILE *stream) |
252b5132 RH |
239 | { |
240 | fprintf (stream, _("\nD30V options:\n\ | |
241 | -O Make adjacent short instructions parallel if possible.\n\ | |
242 | -n Warn about all NOPs inserted by the assembler.\n\ | |
243 | -N Warn about NOPs inserted after word multiplies.\n\ | |
244 | -c Warn about symbols whoes names match register names.\n\ | |
245 | -C Opposite of -C. -c is the default.\n")); | |
246 | } | |
247 | ||
248 | int | |
ea1562b3 | 249 | md_parse_option (int c, char *arg ATTRIBUTE_UNUSED) |
252b5132 RH |
250 | { |
251 | switch (c) | |
252 | { | |
2fd5405a | 253 | /* Optimize. Will attempt to parallelize operations. */ |
252b5132 RH |
254 | case 'O': |
255 | Optimizing = 1; | |
256 | break; | |
257 | ||
258 | /* Warn about all NOPS that the assembler inserts. */ | |
259 | case 'n': | |
260 | warn_nops = NOP_ALL; | |
261 | break; | |
262 | ||
263 | /* Warn about the NOPS that the assembler inserts because of the | |
264 | multiply hazard. */ | |
265 | case 'N': | |
266 | warn_nops = NOP_MULTIPLY; | |
267 | break; | |
268 | ||
269 | case 'c': | |
270 | warn_register_name_conflicts = 1; | |
271 | break; | |
272 | ||
273 | case 'C': | |
274 | warn_register_name_conflicts = 0; | |
275 | break; | |
2fd5405a | 276 | |
252b5132 RH |
277 | default: |
278 | return 0; | |
279 | } | |
280 | return 1; | |
281 | } | |
282 | ||
283 | symbolS * | |
ea1562b3 | 284 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
285 | { |
286 | return 0; | |
287 | } | |
288 | ||
252b5132 | 289 | char * |
ea1562b3 | 290 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 291 | { |
499ac353 | 292 | return ieee_md_atof (type, litP, sizeP, TRUE); |
252b5132 RH |
293 | } |
294 | ||
295 | void | |
ea1562b3 NC |
296 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
297 | asection *sec ATTRIBUTE_UNUSED, | |
298 | fragS *fragP ATTRIBUTE_UNUSED) | |
252b5132 RH |
299 | { |
300 | abort (); | |
301 | } | |
302 | ||
303 | valueT | |
ea1562b3 | 304 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
305 | { |
306 | int align = bfd_get_section_alignment (stdoutput, seg); | |
307 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
308 | } | |
309 | ||
252b5132 | 310 | void |
ea1562b3 | 311 | md_begin (void) |
252b5132 | 312 | { |
2fd5405a | 313 | struct d30v_opcode *opcode; |
252b5132 RH |
314 | d30v_hash = hash_new (); |
315 | ||
2fd5405a NC |
316 | /* Insert opcode names into a hash table. */ |
317 | for (opcode = (struct d30v_opcode *) d30v_opcode_table; opcode->name; opcode++) | |
252b5132 RH |
318 | hash_insert (d30v_hash, opcode->name, (char *) opcode); |
319 | ||
320 | fixups = &FixUps[0]; | |
321 | FixUps[0].next = &FixUps[1]; | |
322 | FixUps[1].next = &FixUps[0]; | |
323 | ||
324 | d30v_current_align_seg = now_seg; | |
325 | } | |
326 | ||
2fd5405a NC |
327 | /* Remove the postincrement or postdecrement operator ( '+' or '-' ) |
328 | from an expression. */ | |
252b5132 | 329 | |
2fd5405a | 330 | static int |
ea1562b3 | 331 | postfix (char *p) |
252b5132 | 332 | { |
2fd5405a | 333 | while (*p != '-' && *p != '+') |
252b5132 | 334 | { |
2fd5405a | 335 | if (*p == 0 || *p == '\n' || *p == '\r' || *p == ' ' || *p == ',') |
252b5132 RH |
336 | break; |
337 | p++; | |
338 | } | |
339 | ||
2fd5405a | 340 | if (*p == '-') |
252b5132 RH |
341 | { |
342 | *p = ' '; | |
2fd5405a | 343 | return -1; |
252b5132 | 344 | } |
81d4177b | 345 | |
2fd5405a | 346 | if (*p == '+') |
252b5132 RH |
347 | { |
348 | *p = ' '; | |
2fd5405a | 349 | return 1; |
252b5132 RH |
350 | } |
351 | ||
2fd5405a | 352 | return 0; |
252b5132 RH |
353 | } |
354 | ||
2fd5405a | 355 | static bfd_reloc_code_real_type |
9c95b521 | 356 | get_reloc (const struct d30v_operand *op, int rel_flag) |
252b5132 RH |
357 | { |
358 | switch (op->bits) | |
359 | { | |
360 | case 6: | |
361 | if (op->flags & OPERAND_SHIFT) | |
362 | return BFD_RELOC_D30V_9_PCREL; | |
363 | else | |
364 | return BFD_RELOC_D30V_6; | |
365 | break; | |
366 | case 12: | |
367 | if (!(op->flags & OPERAND_SHIFT)) | |
368 | as_warn (_("unexpected 12-bit reloc type")); | |
369 | if (rel_flag == RELOC_PCREL) | |
370 | return BFD_RELOC_D30V_15_PCREL; | |
371 | else | |
372 | return BFD_RELOC_D30V_15; | |
373 | case 18: | |
374 | if (!(op->flags & OPERAND_SHIFT)) | |
375 | as_warn (_("unexpected 18-bit reloc type")); | |
376 | if (rel_flag == RELOC_PCREL) | |
377 | return BFD_RELOC_D30V_21_PCREL; | |
378 | else | |
379 | return BFD_RELOC_D30V_21; | |
380 | case 32: | |
381 | if (rel_flag == RELOC_PCREL) | |
382 | return BFD_RELOC_D30V_32_PCREL; | |
383 | else | |
384 | return BFD_RELOC_D30V_32; | |
385 | default: | |
386 | return 0; | |
387 | } | |
388 | } | |
389 | ||
2fd5405a | 390 | /* Parse a string of operands and return an array of expressions. */ |
252b5132 RH |
391 | |
392 | static int | |
ea1562b3 | 393 | get_operands (expressionS exp[], int cmp_hack) |
252b5132 RH |
394 | { |
395 | char *p = input_line_pointer; | |
396 | int numops = 0; | |
397 | int post = 0; | |
398 | ||
399 | if (cmp_hack) | |
400 | { | |
401 | exp[numops].X_op = O_absent; | |
402 | exp[numops++].X_add_number = cmp_hack - 1; | |
403 | } | |
404 | ||
2fd5405a | 405 | while (*p) |
252b5132 | 406 | { |
2fd5405a | 407 | while (*p == ' ' || *p == '\t' || *p == ',') |
252b5132 | 408 | p++; |
81d4177b | 409 | |
2fd5405a NC |
410 | if (*p == 0 || *p == '\n' || *p == '\r') |
411 | break; | |
412 | ||
413 | if (*p == '@') | |
252b5132 RH |
414 | { |
415 | p++; | |
416 | exp[numops].X_op = O_absent; | |
2fd5405a | 417 | if (*p == '(') |
252b5132 RH |
418 | { |
419 | p++; | |
420 | exp[numops].X_add_number = OPERAND_ATPAR; | |
421 | post = postfix (p); | |
422 | } | |
2fd5405a | 423 | else if (*p == '-') |
252b5132 RH |
424 | { |
425 | p++; | |
426 | exp[numops].X_add_number = OPERAND_ATMINUS; | |
427 | } | |
428 | else | |
429 | { | |
430 | exp[numops].X_add_number = OPERAND_ATSIGN; | |
431 | post = postfix (p); | |
432 | } | |
433 | numops++; | |
434 | continue; | |
435 | } | |
436 | ||
2fd5405a | 437 | if (*p == ')') |
252b5132 | 438 | { |
2fd5405a | 439 | /* Just skip the trailing paren. */ |
252b5132 RH |
440 | p++; |
441 | continue; | |
442 | } | |
443 | ||
444 | input_line_pointer = p; | |
445 | ||
2fd5405a | 446 | /* Check to see if it might be a register name. */ |
252b5132 RH |
447 | if (!register_name (&exp[numops])) |
448 | { | |
2fd5405a | 449 | /* Parse as an expression. */ |
252b5132 RH |
450 | expression (&exp[numops]); |
451 | } | |
452 | ||
2fd5405a | 453 | if (exp[numops].X_op == O_illegal) |
252b5132 | 454 | as_bad (_("illegal operand")); |
2fd5405a | 455 | else if (exp[numops].X_op == O_absent) |
252b5132 RH |
456 | as_bad (_("missing operand")); |
457 | ||
458 | numops++; | |
459 | p = input_line_pointer; | |
460 | ||
2fd5405a | 461 | switch (post) |
252b5132 | 462 | { |
2fd5405a NC |
463 | case -1: |
464 | /* Postdecrement mode. */ | |
252b5132 RH |
465 | exp[numops].X_op = O_absent; |
466 | exp[numops++].X_add_number = OPERAND_MINUS; | |
467 | break; | |
2fd5405a NC |
468 | case 1: |
469 | /* Postincrement mode. */ | |
252b5132 RH |
470 | exp[numops].X_op = O_absent; |
471 | exp[numops++].X_add_number = OPERAND_PLUS; | |
472 | break; | |
473 | } | |
474 | post = 0; | |
475 | } | |
476 | ||
477 | exp[numops].X_op = 0; | |
81d4177b | 478 | |
2fd5405a | 479 | return numops; |
252b5132 RH |
480 | } |
481 | ||
2fd5405a NC |
482 | /* Generate the instruction. |
483 | It does everything but write the FM bits. */ | |
252b5132 RH |
484 | |
485 | static long long | |
ea1562b3 | 486 | build_insn (struct d30v_insn *opcode, expressionS *opers) |
252b5132 | 487 | { |
87975d2a | 488 | int i, bits, shift, flags; |
2fd5405a | 489 | unsigned long number, id = 0; |
252b5132 RH |
490 | long long insn; |
491 | struct d30v_opcode *op = opcode->op; | |
492 | struct d30v_format *form = opcode->form; | |
493 | ||
2fd5405a NC |
494 | insn = |
495 | opcode->ecc << 28 | op->op1 << 25 | op->op2 << 20 | form->modifier << 18; | |
252b5132 | 496 | |
2fd5405a NC |
497 | for (i = 0; form->operands[i]; i++) |
498 | { | |
252b5132 RH |
499 | flags = d30v_operand_table[form->operands[i]].flags; |
500 | ||
2fd5405a NC |
501 | /* Must be a register or number. */ |
502 | if (!(flags & OPERAND_REG) && !(flags & OPERAND_NUM) | |
503 | && !(flags & OPERAND_NAME) && !(flags & OPERAND_SPECIAL)) | |
252b5132 RH |
504 | continue; |
505 | ||
506 | bits = d30v_operand_table[form->operands[i]].bits; | |
507 | if (flags & OPERAND_SHIFT) | |
508 | bits += 3; | |
509 | ||
252b5132 RH |
510 | shift = 12 - d30v_operand_table[form->operands[i]].position; |
511 | if (opers[i].X_op != O_symbol) | |
512 | number = opers[i].X_add_number; | |
513 | else | |
514 | number = 0; | |
515 | if (flags & OPERAND_REG) | |
516 | { | |
2fd5405a | 517 | /* Check for mvfsys or mvtsys control registers. */ |
252b5132 RH |
518 | if (flags & OPERAND_CONTROL && (number & 0x7f) > MAX_CONTROL_REG) |
519 | { | |
2fd5405a | 520 | /* PSWL or PSWH. */ |
252b5132 RH |
521 | id = (number & 0x7f) - MAX_CONTROL_REG; |
522 | number = 0; | |
523 | } | |
524 | else if (number & OPERAND_FLAG) | |
ea1562b3 NC |
525 | /* NUMBER is a flag register. */ |
526 | id = 3; | |
527 | ||
252b5132 RH |
528 | number &= 0x7F; |
529 | } | |
530 | else if (flags & OPERAND_SPECIAL) | |
ea1562b3 | 531 | number = id; |
252b5132 | 532 | |
2fd5405a NC |
533 | if (opers[i].X_op != O_register && opers[i].X_op != O_constant |
534 | && !(flags & OPERAND_NAME)) | |
252b5132 | 535 | { |
2fd5405a | 536 | /* Now create a fixup. */ |
252b5132 RH |
537 | if (fixups->fc >= MAX_INSN_FIXUPS) |
538 | as_fatal (_("too many fixups")); | |
539 | ||
2fd5405a | 540 | fixups->fix[fixups->fc].reloc = |
9c95b521 | 541 | get_reloc (d30v_operand_table + form->operands[i], op->reloc_flag); |
252b5132 RH |
542 | fixups->fix[fixups->fc].size = 4; |
543 | fixups->fix[fixups->fc].exp = opers[i]; | |
544 | fixups->fix[fixups->fc].operand = form->operands[i]; | |
545 | if (fixups->fix[fixups->fc].reloc == BFD_RELOC_D30V_9_PCREL) | |
546 | fixups->fix[fixups->fc].pcrel = RELOC_PCREL; | |
547 | else | |
548 | fixups->fix[fixups->fc].pcrel = op->reloc_flag; | |
549 | (fixups->fc)++; | |
550 | } | |
551 | ||
2fd5405a | 552 | /* Truncate to the proper number of bits. */ |
252b5132 | 553 | if ((opers[i].X_op == O_constant) && check_range (number, bits, flags)) |
ebf19f1b | 554 | as_bad (_("operand out of range: %ld"), number); |
252b5132 RH |
555 | if (bits < 31) |
556 | number &= 0x7FFFFFFF >> (31 - bits); | |
557 | if (flags & OPERAND_SHIFT) | |
558 | number >>= 3; | |
559 | if (bits == 32) | |
560 | { | |
2fd5405a | 561 | /* It's a LONG instruction. */ |
ea1562b3 NC |
562 | insn |= ((number & 0xffffffff) >> 26); /* Top 6 bits. */ |
563 | insn <<= 32; /* Shift the first word over. */ | |
564 | insn |= ((number & 0x03FC0000) << 2); /* Next 8 bits. */ | |
565 | insn |= number & 0x0003FFFF; /* Bottom 18 bits. */ | |
252b5132 RH |
566 | } |
567 | else | |
568 | insn |= number << shift; | |
569 | } | |
81d4177b | 570 | |
252b5132 RH |
571 | return insn; |
572 | } | |
573 | ||
ea1562b3 NC |
574 | static void |
575 | d30v_number_to_chars (char *buf, /* Return 'nbytes' of chars here. */ | |
576 | long long value, /* The value of the bits. */ | |
577 | int n) /* Number of bytes in the output. */ | |
578 | { | |
579 | while (n--) | |
580 | { | |
581 | buf[n] = value & 0xff; | |
582 | value >>= 8; | |
583 | } | |
584 | } | |
585 | ||
2fd5405a | 586 | /* Write out a long form instruction. */ |
252b5132 | 587 | |
252b5132 | 588 | static void |
ea1562b3 NC |
589 | write_long (struct d30v_insn *opcode ATTRIBUTE_UNUSED, |
590 | long long insn, | |
591 | Fixups *fx) | |
252b5132 RH |
592 | { |
593 | int i, where; | |
594 | char *f = frag_more (8); | |
595 | ||
d4f4f3fb | 596 | dwarf2_emit_insn (8); |
252b5132 RH |
597 | insn |= FM11; |
598 | d30v_number_to_chars (f, insn, 8); | |
599 | ||
2fd5405a | 600 | for (i = 0; i < fx->fc; i++) |
252b5132 RH |
601 | { |
602 | if (fx->fix[i].reloc) | |
2fd5405a NC |
603 | { |
604 | where = f - frag_now->fr_literal; | |
ea1562b3 NC |
605 | fix_new_exp (frag_now, where, fx->fix[i].size, &(fx->fix[i].exp), |
606 | fx->fix[i].pcrel, fx->fix[i].reloc); | |
252b5132 RH |
607 | } |
608 | } | |
81d4177b | 609 | |
252b5132 RH |
610 | fx->fc = 0; |
611 | } | |
612 | ||
252b5132 | 613 | /* Write out a short form instruction by itself. */ |
2fd5405a | 614 | |
252b5132 | 615 | static void |
ea1562b3 NC |
616 | write_1_short (struct d30v_insn *opcode, |
617 | long long insn, | |
618 | Fixups *fx, | |
619 | int use_sequential) | |
252b5132 RH |
620 | { |
621 | char *f = frag_more (8); | |
622 | int i, where; | |
623 | ||
d4f4f3fb | 624 | dwarf2_emit_insn (8); |
252b5132 RH |
625 | if (warn_nops == NOP_ALL) |
626 | as_warn (_("%s NOP inserted"), use_sequential ? | |
627 | _("sequential") : _("parallel")); | |
628 | ||
2fd5405a | 629 | /* The other container needs to be NOP. */ |
252b5132 RH |
630 | if (use_sequential) |
631 | { | |
632 | /* Use a sequential NOP rather than a parallel one, | |
633 | as the current instruction is a FLAG_MUL32 type one | |
634 | and the next instruction is a load. */ | |
2fd5405a | 635 | |
252b5132 | 636 | /* According to 4.3.1: for FM=01, sub-instructions performed |
2fd5405a | 637 | only by IU cannot be encoded in L-container. */ |
252b5132 | 638 | if (opcode->op->unit == IU) |
2fd5405a NC |
639 | /* Right then left. */ |
640 | insn |= FM10 | NOP_LEFT; | |
252b5132 | 641 | else |
2fd5405a NC |
642 | /* Left then right. */ |
643 | insn = FM01 | (insn << 32) | NOP_RIGHT; | |
252b5132 RH |
644 | } |
645 | else | |
646 | { | |
647 | /* According to 4.3.1: for FM=00, sub-instructions performed | |
2fd5405a | 648 | only by IU cannot be encoded in L-container. */ |
252b5132 | 649 | if (opcode->op->unit == IU) |
2fd5405a NC |
650 | /* Right container. */ |
651 | insn |= FM00 | NOP_LEFT; | |
252b5132 | 652 | else |
2fd5405a NC |
653 | /* Left container. */ |
654 | insn = FM00 | (insn << 32) | NOP_RIGHT; | |
252b5132 RH |
655 | } |
656 | ||
657 | d30v_number_to_chars (f, insn, 8); | |
658 | ||
2fd5405a | 659 | for (i = 0; i < fx->fc; i++) |
252b5132 RH |
660 | { |
661 | if (fx->fix[i].reloc) | |
2fd5405a NC |
662 | { |
663 | where = f - frag_now->fr_literal; | |
252b5132 | 664 | fix_new_exp (frag_now, |
2fd5405a | 665 | where, |
252b5132 RH |
666 | fx->fix[i].size, |
667 | &(fx->fix[i].exp), | |
668 | fx->fix[i].pcrel, | |
669 | fx->fix[i].reloc); | |
670 | } | |
671 | } | |
81d4177b | 672 | |
252b5132 RH |
673 | fx->fc = 0; |
674 | } | |
675 | ||
2fd5405a NC |
676 | /* Check 2 instructions and determine if they can be safely |
677 | executed in parallel. Return 1 if they can be. */ | |
252b5132 | 678 | |
252b5132 | 679 | static int |
ea1562b3 NC |
680 | parallel_ok (struct d30v_insn *op1, |
681 | unsigned long insn1, | |
682 | struct d30v_insn *op2, | |
683 | unsigned long insn2, | |
684 | exec_type_enum exec_type) | |
252b5132 RH |
685 | { |
686 | int i, j, shift, regno, bits, ecc; | |
687 | unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2; | |
688 | unsigned long ins, mod_reg[2][3], used_reg[2][3], flag_reg[2]; | |
689 | struct d30v_format *f; | |
690 | struct d30v_opcode *op; | |
691 | ||
2fd5405a | 692 | /* Section 4.3: Both instructions must not be IU or MU only. */ |
252b5132 RH |
693 | if ((op1->op->unit == IU && op2->op->unit == IU) |
694 | || (op1->op->unit == MU && op2->op->unit == MU)) | |
695 | return 0; | |
696 | ||
2fd5405a | 697 | /* First instruction must not be a jump to safely optimize, unless this |
252b5132 RH |
698 | is an explicit parallel operation. */ |
699 | if (exec_type != EXEC_PARALLEL | |
700 | && (op1->op->flags_used & (FLAG_JMP | FLAG_JSR))) | |
701 | return 0; | |
702 | ||
703 | /* If one instruction is /TX or /XT and the other is /FX or /XF respectively, | |
704 | then it is safe to allow the two to be done as parallel ops, since only | |
705 | one will ever be executed at a time. */ | |
706 | if ((op1->ecc == ECC_TX && op2->ecc == ECC_FX) | |
707 | || (op1->ecc == ECC_FX && op2->ecc == ECC_TX) | |
708 | || (op1->ecc == ECC_XT && op2->ecc == ECC_XF) | |
709 | || (op1->ecc == ECC_XF && op2->ecc == ECC_XT)) | |
2fd5405a | 710 | return 1; |
252b5132 RH |
711 | |
712 | /* [0] r0-r31 | |
713 | [1] r32-r63 | |
2fd5405a | 714 | [2] a0, a1, flag registers. */ |
252b5132 RH |
715 | for (j = 0; j < 2; j++) |
716 | { | |
717 | if (j == 0) | |
718 | { | |
719 | f = op1->form; | |
720 | op = op1->op; | |
721 | ecc = op1->ecc; | |
722 | ins = insn1; | |
723 | } | |
724 | else | |
725 | { | |
726 | f = op2->form; | |
727 | op = op2->op; | |
728 | ecc = op2->ecc; | |
729 | ins = insn2; | |
730 | } | |
81d4177b | 731 | |
252b5132 RH |
732 | flag_reg[j] = 0; |
733 | mod_reg[j][0] = mod_reg[j][1] = 0; | |
734 | used_reg[j][0] = used_reg[j][1] = 0; | |
735 | ||
736 | if (flag_explicitly_parallel) | |
737 | { | |
738 | /* For human specified parallel instructions we have been asked | |
739 | to ignore the possibility that both instructions could modify | |
740 | bits in the PSW, so we initialise the mod & used arrays to 0. | |
741 | We have been asked, however, to refuse to allow parallel | |
742 | instructions which explicitly set the same flag register, | |
743 | eg "cmpne f0,r1,0x10 || cmpeq f0, r5, 0x2", so further on we test | |
744 | for the use of a flag register and set a bit in the mod or used | |
745 | array appropriately. */ | |
252b5132 RH |
746 | mod_reg[j][2] = 0; |
747 | used_reg[j][2] = 0; | |
748 | } | |
749 | else | |
750 | { | |
751 | mod_reg[j][2] = (op->flags_set & FLAG_ALL); | |
752 | used_reg[j][2] = (op->flags_used & FLAG_ALL); | |
753 | } | |
2fd5405a NC |
754 | |
755 | /* BSR/JSR always sets R62. */ | |
252b5132 | 756 | if (op->flags_used & FLAG_JSR) |
2fd5405a | 757 | mod_reg[j][1] = (1L << (62 - 32)); |
252b5132 | 758 | |
2fd5405a | 759 | /* Conditional execution affects the flags_used. */ |
252b5132 RH |
760 | switch (ecc) |
761 | { | |
762 | case ECC_TX: | |
763 | case ECC_FX: | |
764 | used_reg[j][2] |= flag_reg[j] = FLAG_0; | |
765 | break; | |
766 | ||
767 | case ECC_XT: | |
768 | case ECC_XF: | |
769 | used_reg[j][2] |= flag_reg[j] = FLAG_1; | |
770 | break; | |
771 | ||
772 | case ECC_TT: | |
773 | case ECC_TF: | |
774 | used_reg[j][2] |= flag_reg[j] = (FLAG_0 | FLAG_1); | |
775 | break; | |
776 | } | |
777 | ||
778 | for (i = 0; f->operands[i]; i++) | |
779 | { | |
780 | flags = d30v_operand_table[f->operands[i]].flags; | |
781 | shift = 12 - d30v_operand_table[f->operands[i]].position; | |
782 | bits = d30v_operand_table[f->operands[i]].bits; | |
783 | if (bits == 32) | |
784 | mask = 0xffffffff; | |
785 | else | |
786 | mask = 0x7FFFFFFF >> (31 - bits); | |
787 | ||
788 | if ((flags & OPERAND_PLUS) || (flags & OPERAND_MINUS)) | |
789 | { | |
2fd5405a NC |
790 | /* This is a post-increment or post-decrement. |
791 | The previous register needs to be marked as modified. */ | |
792 | shift = 12 - d30v_operand_table[f->operands[i - 1]].position; | |
252b5132 RH |
793 | regno = (ins >> shift) & 0x3f; |
794 | if (regno >= 32) | |
795 | mod_reg[j][1] |= 1L << (regno - 32); | |
796 | else | |
797 | mod_reg[j][0] |= 1L << regno; | |
798 | } | |
799 | else if (flags & OPERAND_REG) | |
800 | { | |
801 | regno = (ins >> shift) & mask; | |
2fd5405a NC |
802 | /* The memory write functions don't have a destination |
803 | register. */ | |
252b5132 RH |
804 | if ((flags & OPERAND_DEST) && !(op->flags_set & FLAG_MEM)) |
805 | { | |
2fd5405a | 806 | /* MODIFIED registers and flags. */ |
252b5132 RH |
807 | if (flags & OPERAND_ACC) |
808 | { | |
809 | if (regno == 0) | |
810 | mod_reg[j][2] |= FLAG_A0; | |
811 | else if (regno == 1) | |
812 | mod_reg[j][2] |= FLAG_A1; | |
813 | else | |
814 | abort (); | |
815 | } | |
816 | else if (flags & OPERAND_FLAG) | |
817 | mod_reg[j][2] |= 1L << regno; | |
818 | else if (!(flags & OPERAND_CONTROL)) | |
819 | { | |
820 | int r, z; | |
821 | ||
2fd5405a NC |
822 | /* Need to check if there are two destination |
823 | registers, for example ld2w. */ | |
252b5132 RH |
824 | if (flags & OPERAND_2REG) |
825 | z = 1; | |
826 | else | |
827 | z = 0; | |
828 | ||
829 | for (r = regno; r <= regno + z; r++) | |
2fd5405a | 830 | { |
252b5132 RH |
831 | if (r >= 32) |
832 | mod_reg[j][1] |= 1L << (r - 32); | |
833 | else | |
834 | mod_reg[j][0] |= 1L << r; | |
835 | } | |
836 | } | |
837 | } | |
838 | else | |
839 | { | |
2fd5405a | 840 | /* USED, but not modified registers and flags. */ |
252b5132 RH |
841 | if (flags & OPERAND_ACC) |
842 | { | |
843 | if (regno == 0) | |
844 | used_reg[j][2] |= FLAG_A0; | |
845 | else if (regno == 1) | |
846 | used_reg[j][2] |= FLAG_A1; | |
847 | else | |
848 | abort (); | |
849 | } | |
850 | else if (flags & OPERAND_FLAG) | |
851 | used_reg[j][2] |= 1L << regno; | |
852 | else if (!(flags & OPERAND_CONTROL)) | |
853 | { | |
854 | int r, z; | |
855 | ||
2fd5405a NC |
856 | /* Need to check if there are two source |
857 | registers, for example st2w. */ | |
252b5132 RH |
858 | if (flags & OPERAND_2REG) |
859 | z = 1; | |
860 | else | |
861 | z = 0; | |
862 | ||
863 | for (r = regno; r <= regno + z; r++) | |
2fd5405a | 864 | { |
252b5132 RH |
865 | if (r >= 32) |
866 | used_reg[j][1] |= 1L << (r - 32); | |
867 | else | |
868 | used_reg[j][0] |= 1L << r; | |
869 | } | |
870 | } | |
871 | } | |
872 | } | |
873 | } | |
874 | } | |
2fd5405a | 875 | |
252b5132 RH |
876 | flags_set1 = op1->op->flags_set; |
877 | flags_set2 = op2->op->flags_set; | |
878 | flags_used1 = op1->op->flags_used; | |
879 | flags_used2 = op2->op->flags_used; | |
880 | ||
25f2196d CC |
881 | /* Check for illegal combinations with ADDppp/SUBppp. */ |
882 | if (((flags_set1 & FLAG_NOT_WITH_ADDSUBppp) != 0 | |
252b5132 | 883 | && (flags_used2 & FLAG_ADDSUBppp) != 0) |
25f2196d | 884 | || ((flags_set2 & FLAG_NOT_WITH_ADDSUBppp) != 0 |
252b5132 RH |
885 | && (flags_used1 & FLAG_ADDSUBppp) != 0)) |
886 | return 0; | |
887 | ||
888 | /* Load instruction combined with half-word multiply is illegal. */ | |
889 | if (((flags_used1 & FLAG_MEM) != 0 && (flags_used2 & FLAG_MUL16)) | |
890 | || ((flags_used2 & FLAG_MEM) != 0 && (flags_used1 & FLAG_MUL16))) | |
891 | return 0; | |
892 | ||
893 | /* Specifically allow add || add by removing carry, overflow bits dependency. | |
894 | This is safe, even if an addc follows since the IU takes the argument in | |
895 | the right container, and it writes its results last. | |
896 | However, don't paralellize add followed by addc or sub followed by | |
897 | subb. */ | |
252b5132 RH |
898 | if (mod_reg[0][2] == FLAG_CVVA && mod_reg[1][2] == FLAG_CVVA |
899 | && (used_reg[0][2] & ~flag_reg[0]) == 0 | |
900 | && (used_reg[1][2] & ~flag_reg[1]) == 0 | |
901 | && op1->op->unit == EITHER && op2->op->unit == EITHER) | |
902 | { | |
903 | mod_reg[0][2] = mod_reg[1][2] = 0; | |
904 | } | |
905 | ||
906 | for (j = 0; j < 3; j++) | |
907 | { | |
908 | /* If the second instruction depends on the first, we obviously | |
909 | cannot parallelize. Note, the mod flag implies use, so | |
910 | check that as well. */ | |
2fd5405a | 911 | /* If flag_explicitly_parallel is set, then the case of the |
252b5132 RH |
912 | second instruction using a register the first instruction |
913 | modifies is assumed to be okay; we trust the human. We | |
914 | don't trust the human if both instructions modify the same | |
915 | register but we do trust the human if they modify the same | |
2fd5405a | 916 | flags. */ |
252b5132 RH |
917 | /* We have now been requested not to trust the human if the |
918 | instructions modify the same flag registers either. */ | |
919 | if (flag_explicitly_parallel) | |
920 | { | |
921 | if ((mod_reg[0][j] & mod_reg[1][j]) != 0) | |
922 | return 0; | |
923 | } | |
924 | else | |
cc8a6dd0 | 925 | if ((mod_reg[0][j] & (mod_reg[1][j] | used_reg[1][j])) != 0) |
252b5132 RH |
926 | return 0; |
927 | } | |
928 | ||
929 | return 1; | |
930 | } | |
931 | ||
ea1562b3 NC |
932 | /* Write out a short form instruction if possible. |
933 | Return number of instructions not written out. */ | |
252b5132 | 934 | |
ea1562b3 NC |
935 | static int |
936 | write_2_short (struct d30v_insn *opcode1, | |
937 | long long insn1, | |
938 | struct d30v_insn *opcode2, | |
939 | long long insn2, | |
940 | exec_type_enum exec_type, | |
941 | Fixups *fx) | |
252b5132 | 942 | { |
ea1562b3 NC |
943 | long long insn = NOP2; |
944 | char *f; | |
945 | int i, j, where; | |
252b5132 | 946 | |
ea1562b3 NC |
947 | if (exec_type == EXEC_SEQ |
948 | && (opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR)) | |
949 | && ((opcode1->op->flags_used & FLAG_DELAY) == 0) | |
950 | && ((opcode1->ecc == ECC_AL) || ! Optimizing)) | |
951 | { | |
952 | /* Unconditional, non-delayed branches kill instructions in | |
953 | the right bin. Conditional branches don't always but if | |
954 | we are not optimizing, then we have been asked to produce | |
955 | an error about such constructs. For the purposes of this | |
956 | test, subroutine calls are considered to be branches. */ | |
957 | write_1_short (opcode1, insn1, fx->next, FALSE); | |
958 | return 1; | |
959 | } | |
252b5132 | 960 | |
ea1562b3 NC |
961 | /* Note: we do not have to worry about subroutine calls occurring |
962 | in the right hand container. The return address is always | |
963 | aligned to the next 64 bit boundary, be that 64 or 32 bit away. */ | |
964 | switch (exec_type) | |
252b5132 | 965 | { |
ea1562b3 NC |
966 | case EXEC_UNKNOWN: /* Order not specified. */ |
967 | if (Optimizing | |
968 | && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type) | |
969 | && ! ( (opcode1->op->unit == EITHER_BUT_PREFER_MU | |
970 | || opcode1->op->unit == MU) | |
971 | && | |
972 | ( opcode2->op->unit == EITHER_BUT_PREFER_MU | |
973 | || opcode2->op->unit == MU))) | |
252b5132 | 974 | { |
ea1562b3 NC |
975 | /* Parallel. */ |
976 | exec_type = EXEC_PARALLEL; | |
977 | ||
978 | if (opcode1->op->unit == IU | |
979 | || opcode2->op->unit == MU | |
980 | || opcode2->op->unit == EITHER_BUT_PREFER_MU) | |
981 | insn = FM00 | (insn2 << 32) | insn1; | |
252b5132 RH |
982 | else |
983 | { | |
ea1562b3 NC |
984 | insn = FM00 | (insn1 << 32) | insn2; |
985 | fx = fx->next; | |
252b5132 RH |
986 | } |
987 | } | |
ea1562b3 NC |
988 | else if ((opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR) |
989 | && ((opcode1->op->flags_used & FLAG_DELAY) == 0)) | |
990 | || opcode1->op->flags_used & FLAG_RP) | |
991 | { | |
992 | /* We must emit (non-delayed) branch type instructions | |
993 | on their own with nothing in the right container. */ | |
994 | /* We must treat repeat instructions likewise, since the | |
995 | following instruction has to be separate from the repeat | |
996 | in order to be repeated. */ | |
997 | write_1_short (opcode1, insn1, fx->next, FALSE); | |
998 | return 1; | |
999 | } | |
1000 | else if (prev_left_kills_right_p) | |
1001 | { | |
1002 | /* The left instruction kils the right slot, so we | |
1003 | must leave it empty. */ | |
1004 | write_1_short (opcode1, insn1, fx->next, FALSE); | |
1005 | return 1; | |
1006 | } | |
1007 | else if (opcode1->op->unit == IU) | |
1008 | { | |
1009 | if (opcode2->op->unit == EITHER_BUT_PREFER_MU) | |
1010 | { | |
1011 | /* Case 103810 is a request from Mitsubishi that opcodes | |
1012 | with EITHER_BUT_PREFER_MU should not be executed in | |
1013 | reverse sequential order. */ | |
1014 | write_1_short (opcode1, insn1, fx->next, FALSE); | |
1015 | return 1; | |
1016 | } | |
81d4177b | 1017 | |
ea1562b3 NC |
1018 | /* Reverse sequential. */ |
1019 | insn = FM10 | (insn2 << 32) | insn1; | |
1020 | exec_type = EXEC_REVSEQ; | |
1021 | } | |
1022 | else | |
252b5132 | 1023 | { |
ea1562b3 NC |
1024 | /* Sequential. */ |
1025 | insn = FM01 | (insn1 << 32) | insn2; | |
1026 | fx = fx->next; | |
1027 | exec_type = EXEC_SEQ; | |
1028 | } | |
1029 | break; | |
2fd5405a | 1030 | |
ea1562b3 NC |
1031 | case EXEC_PARALLEL: /* Parallel. */ |
1032 | flag_explicitly_parallel = flag_xp_state; | |
1033 | if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) | |
1034 | as_bad (_("Instructions may not be executed in parallel")); | |
1035 | else if (opcode1->op->unit == IU) | |
1036 | { | |
1037 | if (opcode2->op->unit == IU) | |
1038 | as_bad (_("Two IU instructions may not be executed in parallel")); | |
1039 | as_warn (_("Swapping instruction order")); | |
1040 | insn = FM00 | (insn2 << 32) | insn1; | |
1041 | } | |
1042 | else if (opcode2->op->unit == MU) | |
1043 | { | |
1044 | if (opcode1->op->unit == MU) | |
1045 | as_bad (_("Two MU instructions may not be executed in parallel")); | |
1046 | else if (opcode1->op->unit == EITHER_BUT_PREFER_MU) | |
1047 | as_warn (_("Executing %s in IU may not work"), opcode1->op->name); | |
1048 | as_warn (_("Swapping instruction order")); | |
1049 | insn = FM00 | (insn2 << 32) | insn1; | |
1050 | } | |
1051 | else | |
1052 | { | |
1053 | if (opcode2->op->unit == EITHER_BUT_PREFER_MU) | |
1054 | as_warn (_("Executing %s in IU may not work in parallel execution"), | |
1055 | opcode2->op->name); | |
2fd5405a | 1056 | |
ea1562b3 NC |
1057 | insn = FM00 | (insn1 << 32) | insn2; |
1058 | fx = fx->next; | |
252b5132 | 1059 | } |
ea1562b3 NC |
1060 | flag_explicitly_parallel = 0; |
1061 | break; | |
252b5132 | 1062 | |
ea1562b3 NC |
1063 | case EXEC_SEQ: /* Sequential. */ |
1064 | if (opcode1->op->unit == IU) | |
1065 | as_bad (_("IU instruction may not be in the left container")); | |
1066 | if (prev_left_kills_right_p) | |
1067 | as_bad (_("special left instruction `%s' kills instruction " | |
1068 | "`%s' in right container"), | |
1069 | opcode1->op->name, opcode2->op->name); | |
1070 | insn = FM01 | (insn1 << 32) | insn2; | |
1071 | fx = fx->next; | |
1072 | break; | |
252b5132 | 1073 | |
ea1562b3 NC |
1074 | case EXEC_REVSEQ: /* Reverse sequential. */ |
1075 | if (opcode2->op->unit == MU) | |
1076 | as_bad (_("MU instruction may not be in the right container")); | |
1077 | if (opcode1->op->unit == EITHER_BUT_PREFER_MU) | |
1078 | as_warn (_("Executing %s in reverse serial with %s may not work"), | |
1079 | opcode1->op->name, opcode2->op->name); | |
1080 | else if (opcode2->op->unit == EITHER_BUT_PREFER_MU) | |
1081 | as_warn (_("Executing %s in IU in reverse serial may not work"), | |
1082 | opcode2->op->name); | |
1083 | insn = FM10 | (insn1 << 32) | insn2; | |
1084 | fx = fx->next; | |
1085 | break; | |
1086 | ||
1087 | default: | |
1088 | as_fatal (_("unknown execution type passed to write_2_short()")); | |
252b5132 RH |
1089 | } |
1090 | ||
ea1562b3 | 1091 | f = frag_more (8); |
d4f4f3fb | 1092 | dwarf2_emit_insn (8); |
ea1562b3 NC |
1093 | d30v_number_to_chars (f, insn, 8); |
1094 | ||
1095 | /* If the previous instruction was a 32-bit multiply but it is put into a | |
1096 | parallel container, mark the current instruction as being a 32-bit | |
1097 | multiply. */ | |
1098 | if (prev_mul32_p && exec_type == EXEC_PARALLEL) | |
1099 | cur_mul32_p = 1; | |
1100 | ||
1101 | for (j = 0; j < 2; j++) | |
252b5132 | 1102 | { |
ea1562b3 | 1103 | for (i = 0; i < fx->fc; i++) |
252b5132 | 1104 | { |
ea1562b3 | 1105 | if (fx->fix[i].reloc) |
252b5132 | 1106 | { |
ea1562b3 | 1107 | where = (f - frag_now->fr_literal) + 4 * j; |
2fd5405a | 1108 | |
ea1562b3 NC |
1109 | fix_new_exp (frag_now, |
1110 | where, | |
1111 | fx->fix[i].size, | |
1112 | &(fx->fix[i].exp), | |
1113 | fx->fix[i].pcrel, | |
1114 | fx->fix[i].reloc); | |
252b5132 | 1115 | } |
252b5132 | 1116 | } |
ea1562b3 NC |
1117 | |
1118 | fx->fc = 0; | |
1119 | fx = fx->next; | |
252b5132 | 1120 | } |
2fd5405a | 1121 | |
ea1562b3 NC |
1122 | return 0; |
1123 | } | |
252b5132 | 1124 | |
ea1562b3 NC |
1125 | /* Get a pointer to an entry in the format table. |
1126 | It must look at all formats for an opcode and use the operands | |
1127 | to choose the correct one. Return NULL on error. */ | |
1128 | ||
1129 | static struct d30v_format * | |
1130 | find_format (struct d30v_opcode *opcode, | |
1131 | expressionS myops[], | |
1132 | int fsize, | |
1133 | int cmp_hack) | |
1134 | { | |
87975d2a | 1135 | int match, opcode_index, i = 0, j, k; |
ea1562b3 NC |
1136 | struct d30v_format *fm; |
1137 | ||
1138 | if (opcode == NULL) | |
1139 | return NULL; | |
1140 | ||
1141 | /* Get all the operands and save them as expressions. */ | |
87975d2a | 1142 | get_operands (myops, cmp_hack); |
ea1562b3 | 1143 | |
91d6fa6a | 1144 | while ((opcode_index = opcode->format[i++]) != 0) |
252b5132 | 1145 | { |
91d6fa6a | 1146 | if (fsize == FORCE_SHORT && opcode_index >= LONG) |
ea1562b3 | 1147 | continue; |
2fd5405a | 1148 | |
91d6fa6a | 1149 | if (fsize == FORCE_LONG && opcode_index < LONG) |
ea1562b3 NC |
1150 | continue; |
1151 | ||
91d6fa6a NC |
1152 | fm = (struct d30v_format *) &d30v_format_table[opcode_index]; |
1153 | k = opcode_index; | |
1154 | while (fm->form == opcode_index) | |
ea1562b3 NC |
1155 | { |
1156 | match = 1; | |
1157 | /* Now check the operands for compatibility. */ | |
1158 | for (j = 0; match && fm->operands[j]; j++) | |
1159 | { | |
1160 | int flags = d30v_operand_table[fm->operands[j]].flags; | |
1161 | int bits = d30v_operand_table[fm->operands[j]].bits; | |
1162 | int X_op = myops[j].X_op; | |
1163 | int num = myops[j].X_add_number; | |
1164 | ||
1165 | if (flags & OPERAND_SPECIAL) | |
1166 | break; | |
1167 | else if (X_op == O_illegal) | |
1168 | match = 0; | |
1169 | else if (flags & OPERAND_REG) | |
1170 | { | |
1171 | if (X_op != O_register | |
1172 | || ((flags & OPERAND_ACC) && !(num & OPERAND_ACC)) | |
1173 | || (!(flags & OPERAND_ACC) && (num & OPERAND_ACC)) | |
1174 | || ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG)) | |
1175 | || (!(flags & (OPERAND_FLAG | OPERAND_CONTROL)) && (num & OPERAND_FLAG)) | |
1176 | || ((flags & OPERAND_CONTROL) | |
1177 | && !(num & (OPERAND_CONTROL | OPERAND_FLAG)))) | |
1178 | match = 0; | |
1179 | } | |
1180 | else if (((flags & OPERAND_MINUS) | |
1181 | && (X_op != O_absent || num != OPERAND_MINUS)) | |
1182 | || ((flags & OPERAND_PLUS) | |
1183 | && (X_op != O_absent || num != OPERAND_PLUS)) | |
1184 | || ((flags & OPERAND_ATMINUS) | |
1185 | && (X_op != O_absent || num != OPERAND_ATMINUS)) | |
1186 | || ((flags & OPERAND_ATPAR) | |
1187 | && (X_op != O_absent || num != OPERAND_ATPAR)) | |
1188 | || ((flags & OPERAND_ATSIGN) | |
1189 | && (X_op != O_absent || num != OPERAND_ATSIGN))) | |
1190 | match = 0; | |
1191 | else if (flags & OPERAND_NUM) | |
1192 | { | |
1193 | /* A number can be a constant or symbol expression. */ | |
1194 | ||
1195 | /* If we have found a register name, but that name | |
1196 | also matches a symbol, then re-parse the name as | |
1197 | an expression. */ | |
1198 | if (X_op == O_register | |
1199 | && symbol_find ((char *) myops[j].X_op_symbol)) | |
1200 | { | |
1201 | input_line_pointer = (char *) myops[j].X_op_symbol; | |
1202 | expression (&myops[j]); | |
1203 | } | |
1204 | ||
1205 | /* Turn an expression into a symbol for later resolution. */ | |
1206 | if (X_op != O_absent && X_op != O_constant | |
1207 | && X_op != O_symbol && X_op != O_register | |
1208 | && X_op != O_big) | |
1209 | { | |
1210 | symbolS *sym = make_expr_symbol (&myops[j]); | |
1211 | myops[j].X_op = X_op = O_symbol; | |
1212 | myops[j].X_add_symbol = sym; | |
1213 | myops[j].X_add_number = num = 0; | |
1214 | } | |
1215 | ||
1216 | if (fm->form >= LONG) | |
1217 | { | |
1218 | /* If we're testing for a LONG format, either fits. */ | |
1219 | if (X_op != O_constant && X_op != O_symbol) | |
1220 | match = 0; | |
1221 | } | |
1222 | else if (fm->form < LONG | |
1223 | && ((fsize == FORCE_SHORT && X_op == O_symbol) | |
1224 | || (fm->form == SHORT_D2 && j == 0))) | |
1225 | match = 1; | |
1226 | ||
1227 | /* This is the tricky part. Will the constant or symbol | |
1228 | fit into the space in the current format? */ | |
1229 | else if (X_op == O_constant) | |
1230 | { | |
1231 | if (check_range (num, bits, flags)) | |
1232 | match = 0; | |
1233 | } | |
1234 | else if (X_op == O_symbol | |
1235 | && S_IS_DEFINED (myops[j].X_add_symbol) | |
1236 | && S_GET_SEGMENT (myops[j].X_add_symbol) == now_seg | |
1237 | && opcode->reloc_flag == RELOC_PCREL) | |
1238 | { | |
1239 | /* If the symbol is defined, see if the value will fit | |
1240 | into the form we're considering. */ | |
1241 | fragS *f; | |
1242 | long value; | |
1243 | ||
1244 | /* Calculate the current address by running through the | |
1245 | previous frags and adding our current offset. */ | |
1246 | value = 0; | |
1247 | for (f = frchain_now->frch_root; f; f = f->fr_next) | |
1248 | value += f->fr_fix + f->fr_offset; | |
1249 | value = (S_GET_VALUE (myops[j].X_add_symbol) - value | |
1250 | - (obstack_next_free (&frchain_now->frch_obstack) | |
1251 | - frag_now->fr_literal)); | |
1252 | if (check_range (value, bits, flags)) | |
1253 | match = 0; | |
1254 | } | |
1255 | else | |
1256 | match = 0; | |
1257 | } | |
1258 | } | |
1259 | /* We're only done if the operands matched so far AND there | |
1260 | are no more to check. */ | |
1261 | if (match && myops[j].X_op == 0) | |
1262 | { | |
1263 | /* Final check - issue a warning if an odd numbered register | |
1264 | is used as the first register in an instruction that reads | |
1265 | or writes 2 registers. */ | |
1266 | ||
1267 | for (j = 0; fm->operands[j]; j++) | |
1268 | if (myops[j].X_op == O_register | |
1269 | && (myops[j].X_add_number & 1) | |
1270 | && (d30v_operand_table[fm->operands[j]].flags & OPERAND_2REG)) | |
1271 | as_warn (_("Odd numbered register used as target of multi-register instruction")); | |
1272 | ||
1273 | return fm; | |
1274 | } | |
1275 | fm = (struct d30v_format *) &d30v_format_table[++k]; | |
1276 | } | |
252b5132 | 1277 | } |
ea1562b3 | 1278 | return NULL; |
252b5132 RH |
1279 | } |
1280 | ||
2fd5405a NC |
1281 | /* Assemble a single instruction and return an opcode. |
1282 | Return -1 (an invalid opcode) on error. */ | |
252b5132 RH |
1283 | |
1284 | #define NAME_BUF_LEN 20 | |
1285 | ||
1286 | static long long | |
ea1562b3 NC |
1287 | do_assemble (char *str, |
1288 | struct d30v_insn *opcode, | |
1289 | int shortp, | |
1290 | int is_parallel) | |
252b5132 | 1291 | { |
2132e3a3 AM |
1292 | char *op_start; |
1293 | char *save; | |
1294 | char *op_end; | |
2fd5405a NC |
1295 | char name[NAME_BUF_LEN]; |
1296 | int cmp_hack; | |
1297 | int nlen = 0; | |
1298 | int fsize = (shortp ? FORCE_SHORT : 0); | |
1299 | expressionS myops[6]; | |
1300 | long long insn; | |
1301 | ||
1302 | /* Drop leading whitespace. */ | |
1303 | while (*str == ' ') | |
1304 | str++; | |
1305 | ||
1306 | /* Find the opcode end. */ | |
2132e3a3 | 1307 | for (op_start = op_end = str; |
2fd5405a | 1308 | *op_end |
252b5132 | 1309 | && nlen < (NAME_BUF_LEN - 1) |
2fd5405a | 1310 | && *op_end != '/' |
2132e3a3 | 1311 | && !is_end_of_line[(unsigned char) *op_end] && *op_end != ' '; |
252b5132 RH |
1312 | op_end++) |
1313 | { | |
3882b010 | 1314 | name[nlen] = TOLOWER (op_start[nlen]); |
252b5132 RH |
1315 | nlen++; |
1316 | } | |
1317 | ||
1318 | if (nlen == 0) | |
1319 | return -1; | |
1320 | ||
1321 | name[nlen] = 0; | |
1322 | ||
2fd5405a | 1323 | /* If there is an execution condition code, handle it. */ |
252b5132 RH |
1324 | if (*op_end == '/') |
1325 | { | |
1326 | int i = 0; | |
2fd5405a | 1327 | while ((i < ECC_MAX) && strncasecmp (d30v_ecc_names[i], op_end + 1, 2)) |
252b5132 | 1328 | i++; |
2fd5405a | 1329 | |
252b5132 RH |
1330 | if (i == ECC_MAX) |
1331 | { | |
1332 | char tmp[4]; | |
1333 | strncpy (tmp, op_end + 1, 2); | |
1334 | tmp[2] = 0; | |
2fd5405a | 1335 | as_bad (_("unknown condition code: %s"), tmp); |
252b5132 RH |
1336 | return -1; |
1337 | } | |
252b5132 RH |
1338 | opcode->ecc = i; |
1339 | op_end += 3; | |
1340 | } | |
1341 | else | |
1342 | opcode->ecc = ECC_AL; | |
252b5132 | 1343 | |
2fd5405a | 1344 | /* CMP and CMPU change their name based on condition codes. */ |
252b5132 RH |
1345 | if (!strncmp (name, "cmp", 3)) |
1346 | { | |
2fd5405a | 1347 | int p, i; |
91d6fa6a NC |
1348 | char **d30v_str = (char **) d30v_cc_names; |
1349 | ||
252b5132 RH |
1350 | if (name[3] == 'u') |
1351 | p = 4; | |
1352 | else | |
1353 | p = 3; | |
1354 | ||
91d6fa6a | 1355 | for (i = 1; *d30v_str && strncmp (*d30v_str, &name[p], 2); i++, d30v_str++) |
252b5132 RH |
1356 | ; |
1357 | ||
2fd5405a | 1358 | /* cmpu only supports some condition codes. */ |
252b5132 RH |
1359 | if (p == 4) |
1360 | { | |
1361 | if (i < 3 || i > 6) | |
1362 | { | |
2fd5405a NC |
1363 | name[p + 2] = 0; |
1364 | as_bad (_("cmpu doesn't support condition code %s"), &name[p]); | |
252b5132 RH |
1365 | } |
1366 | } | |
1367 | ||
91d6fa6a | 1368 | if (!*d30v_str) |
252b5132 | 1369 | { |
2fd5405a NC |
1370 | name[p + 2] = 0; |
1371 | as_bad (_("unknown condition code: %s"), &name[p]); | |
252b5132 | 1372 | } |
2fd5405a | 1373 | |
252b5132 RH |
1374 | cmp_hack = i; |
1375 | name[p] = 0; | |
1376 | } | |
1377 | else | |
1378 | cmp_hack = 0; | |
252b5132 | 1379 | |
2fd5405a NC |
1380 | /* Need to look for .s or .l. */ |
1381 | if (name[nlen - 2] == '.') | |
252b5132 | 1382 | { |
2fd5405a | 1383 | switch (name[nlen - 1]) |
252b5132 RH |
1384 | { |
1385 | case 's': | |
1386 | fsize = FORCE_SHORT; | |
1387 | break; | |
1388 | case 'l': | |
1389 | fsize = FORCE_LONG; | |
1390 | break; | |
1391 | } | |
2fd5405a | 1392 | name[nlen - 2] = 0; |
252b5132 RH |
1393 | } |
1394 | ||
2fd5405a NC |
1395 | /* Find the first opcode with the proper name. */ |
1396 | opcode->op = (struct d30v_opcode *) hash_find (d30v_hash, name); | |
252b5132 RH |
1397 | if (opcode->op == NULL) |
1398 | { | |
2fd5405a | 1399 | as_bad (_("unknown opcode: %s"), name); |
252b5132 RH |
1400 | return -1; |
1401 | } | |
1402 | ||
1403 | save = input_line_pointer; | |
1404 | input_line_pointer = op_end; | |
1405 | while (!(opcode->form = find_format (opcode->op, myops, fsize, cmp_hack))) | |
1406 | { | |
1407 | opcode->op++; | |
1408 | if (opcode->op->name == NULL || strcmp (opcode->op->name, name)) | |
1409 | { | |
2fd5405a NC |
1410 | as_bad (_("operands for opcode `%s' do not match any valid format"), |
1411 | name); | |
252b5132 RH |
1412 | return -1; |
1413 | } | |
1414 | } | |
1415 | input_line_pointer = save; | |
1416 | ||
2fd5405a | 1417 | insn = build_insn (opcode, myops); |
252b5132 | 1418 | |
2d2255b5 | 1419 | /* Propagate multiply status. */ |
252b5132 RH |
1420 | if (insn != -1) |
1421 | { | |
1422 | if (is_parallel && prev_mul32_p) | |
1423 | cur_mul32_p = 1; | |
1424 | else | |
1425 | { | |
1426 | prev_mul32_p = cur_mul32_p; | |
1427 | cur_mul32_p = (opcode->op->flags_used & FLAG_MUL32) != 0; | |
1428 | } | |
1429 | } | |
1430 | ||
2fd5405a | 1431 | /* Propagate left_kills_right status. */ |
252b5132 RH |
1432 | if (insn != -1) |
1433 | { | |
1434 | prev_left_kills_right_p = cur_left_kills_right_p; | |
1435 | ||
1436 | if (opcode->op->flags_set & FLAG_LKR) | |
1437 | { | |
1438 | cur_left_kills_right_p = 1; | |
2fd5405a | 1439 | |
252b5132 RH |
1440 | if (strcmp (opcode->op->name, "mvtsys") == 0) |
1441 | { | |
2fd5405a NC |
1442 | /* Left kills right for only mvtsys only for |
1443 | PSW/PSWH/PSWL/flags target. */ | |
252b5132 RH |
1444 | if ((myops[0].X_op == O_register) && |
1445 | ((myops[0].X_add_number == OPERAND_CONTROL) || /* psw */ | |
1446 | (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+2) || /* pswh */ | |
1447 | (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+1) || /* pswl */ | |
1448 | (myops[0].X_add_number == OPERAND_FLAG+0) || /* f0 */ | |
1449 | (myops[0].X_add_number == OPERAND_FLAG+1) || /* f1 */ | |
1450 | (myops[0].X_add_number == OPERAND_FLAG+2) || /* f2 */ | |
1451 | (myops[0].X_add_number == OPERAND_FLAG+3) || /* f3 */ | |
1452 | (myops[0].X_add_number == OPERAND_FLAG+4) || /* f4 */ | |
1453 | (myops[0].X_add_number == OPERAND_FLAG+5) || /* f5 */ | |
1454 | (myops[0].X_add_number == OPERAND_FLAG+6) || /* f6 */ | |
1455 | (myops[0].X_add_number == OPERAND_FLAG+7))) /* f7 */ | |
1456 | { | |
1457 | cur_left_kills_right_p = 1; | |
1458 | } | |
1459 | else | |
1460 | { | |
2fd5405a NC |
1461 | /* Other mvtsys target registers don't kill right |
1462 | instruction. */ | |
252b5132 RH |
1463 | cur_left_kills_right_p = 0; |
1464 | } | |
1465 | } /* mvtsys */ | |
1466 | } | |
1467 | else | |
1468 | cur_left_kills_right_p = 0; | |
1469 | } | |
1470 | ||
1471 | return insn; | |
1472 | } | |
1473 | ||
ea1562b3 NC |
1474 | /* Called internally to handle all alignment needs. This takes care |
1475 | of eliding calls to frag_align if'n the cached current alignment | |
1476 | says we've already got it, as well as taking care of the auto-aligning | |
1477 | labels wrt code. */ | |
252b5132 | 1478 | |
ea1562b3 NC |
1479 | static void |
1480 | d30v_align (int n, char *pfill, symbolS *label) | |
252b5132 | 1481 | { |
ea1562b3 NC |
1482 | /* The front end is prone to changing segments out from under us |
1483 | temporarily when -g is in effect. */ | |
1484 | int switched_seg_p = (d30v_current_align_seg != now_seg); | |
2fd5405a | 1485 | |
ea1562b3 NC |
1486 | /* Do not assume that if 'd30v_current_align >= n' and |
1487 | '! switched_seg_p' that it is safe to avoid performing | |
1488 | this alignment request. The alignment of the current frag | |
1489 | can be changed under our feet, for example by a .ascii | |
1490 | directive in the source code. cf testsuite/gas/d30v/reloc.s */ | |
1491 | d30v_cleanup (FALSE); | |
252b5132 | 1492 | |
ea1562b3 | 1493 | if (pfill == NULL) |
252b5132 | 1494 | { |
ea1562b3 NC |
1495 | if (n > 2 |
1496 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
1497 | { | |
1498 | static char const nop[4] = { 0x00, 0xf0, 0x00, 0x00 }; | |
252b5132 | 1499 | |
ea1562b3 NC |
1500 | /* First, make sure we're on a four-byte boundary, in case |
1501 | someone has been putting .byte values the text section. */ | |
1502 | if (d30v_current_align < 2 || switched_seg_p) | |
1503 | frag_align (2, 0, 0); | |
1504 | frag_align_pattern (n, nop, sizeof nop, 0); | |
1505 | } | |
1506 | else | |
1507 | frag_align (n, 0, 0); | |
1508 | } | |
1509 | else | |
1510 | frag_align (n, *pfill, 0); | |
252b5132 | 1511 | |
ea1562b3 NC |
1512 | if (!switched_seg_p) |
1513 | d30v_current_align = n; | |
2fd5405a | 1514 | |
ea1562b3 NC |
1515 | if (label != NULL) |
1516 | { | |
1517 | symbolS *sym; | |
1518 | int label_seen = FALSE; | |
1519 | struct frag *old_frag; | |
1520 | valueT old_value; | |
1521 | valueT new_value; | |
252b5132 | 1522 | |
9c2799c2 | 1523 | gas_assert (S_GET_SEGMENT (label) == now_seg); |
2fd5405a | 1524 | |
ea1562b3 NC |
1525 | old_frag = symbol_get_frag (label); |
1526 | old_value = S_GET_VALUE (label); | |
1527 | new_value = (valueT) frag_now_fix (); | |
252b5132 | 1528 | |
ea1562b3 NC |
1529 | /* It is possible to have more than one label at a particular |
1530 | address, especially if debugging is enabled, so we must | |
1531 | take care to adjust all the labels at this address in this | |
1532 | fragment. To save time we search from the end of the symbol | |
1533 | list, backwards, since the symbols we are interested in are | |
1534 | almost certainly the ones that were most recently added. | |
1535 | Also to save time we stop searching once we have seen at least | |
1536 | one matching label, and we encounter a label that is no longer | |
1537 | in the target fragment. Note, this search is guaranteed to | |
1538 | find at least one match when sym == label, so no special case | |
1539 | code is necessary. */ | |
1540 | for (sym = symbol_lastP; sym != NULL; sym = symbol_previous (sym)) | |
1541 | { | |
1542 | if (symbol_get_frag (sym) == old_frag | |
1543 | && S_GET_VALUE (sym) == old_value) | |
1544 | { | |
1545 | label_seen = TRUE; | |
1546 | symbol_set_frag (sym, frag_now); | |
1547 | S_SET_VALUE (sym, new_value); | |
1548 | } | |
1549 | else if (label_seen && symbol_get_frag (sym) != old_frag) | |
1550 | break; | |
1551 | } | |
1552 | } | |
2fd5405a | 1553 | |
ea1562b3 NC |
1554 | record_alignment (now_seg, n); |
1555 | } | |
252b5132 | 1556 | |
ea1562b3 NC |
1557 | /* This is the main entry point for the machine-dependent assembler. |
1558 | STR points to a machine-dependent instruction. This function is | |
1559 | supposed to emit the frags/bytes it assembles to. For the D30V, it | |
1560 | mostly handles the special VLIW parsing and packing and leaves the | |
1561 | difficult stuff to do_assemble (). */ | |
1562 | ||
1563 | static long long prev_insn = -1; | |
1564 | static struct d30v_insn prev_opcode; | |
1565 | static subsegT prev_subseg; | |
1566 | static segT prev_seg = 0; | |
1567 | ||
1568 | void | |
1569 | md_assemble (char *str) | |
1570 | { | |
1571 | struct d30v_insn opcode; | |
1572 | long long insn; | |
1573 | /* Execution type; parallel, etc. */ | |
1574 | exec_type_enum extype = EXEC_UNKNOWN; | |
1575 | /* Saved extype. Used for multiline instructions. */ | |
1576 | static exec_type_enum etype = EXEC_UNKNOWN; | |
1577 | char *str2; | |
1578 | ||
1579 | if ((prev_insn != -1) && prev_seg | |
1580 | && ((prev_seg != now_seg) || (prev_subseg != now_subseg))) | |
1581 | d30v_cleanup (FALSE); | |
1582 | ||
1583 | if (d30v_current_align < 3) | |
1584 | d30v_align (3, NULL, d30v_last_label); | |
1585 | else if (d30v_current_align > 3) | |
1586 | d30v_current_align = 3; | |
1587 | d30v_last_label = NULL; | |
1588 | ||
1589 | flag_explicitly_parallel = 0; | |
1590 | flag_xp_state = 0; | |
1591 | if (etype == EXEC_UNKNOWN) | |
1592 | { | |
1593 | /* Look for the special multiple instruction separators. */ | |
1594 | str2 = strstr (str, "||"); | |
1595 | if (str2) | |
1596 | { | |
1597 | extype = EXEC_PARALLEL; | |
1598 | flag_xp_state = 1; | |
1599 | } | |
1600 | else | |
1601 | { | |
1602 | str2 = strstr (str, "->"); | |
1603 | if (str2) | |
1604 | extype = EXEC_SEQ; | |
1605 | else | |
1606 | { | |
1607 | str2 = strstr (str, "<-"); | |
1608 | if (str2) | |
1609 | extype = EXEC_REVSEQ; | |
1610 | } | |
1611 | } | |
1612 | ||
1613 | /* STR2 points to the separator, if one. */ | |
1614 | if (str2) | |
1615 | { | |
1616 | *str2 = 0; | |
1617 | ||
1618 | /* If two instructions are present and we already have one saved, | |
1619 | then first write it out. */ | |
1620 | d30v_cleanup (FALSE); | |
1621 | ||
1622 | /* Assemble first instruction and save it. */ | |
1623 | prev_insn = do_assemble (str, &prev_opcode, 1, 0); | |
1624 | if (prev_insn == -1) | |
1625 | as_bad (_("Cannot assemble instruction")); | |
1626 | if (prev_opcode.form != NULL && prev_opcode.form->form >= LONG) | |
1627 | as_bad (_("First opcode is long. Unable to mix instructions as specified.")); | |
1628 | fixups = fixups->next; | |
1629 | str = str2 + 2; | |
1630 | prev_seg = now_seg; | |
1631 | prev_subseg = now_subseg; | |
1632 | } | |
1633 | } | |
1634 | ||
1635 | insn = do_assemble (str, &opcode, | |
1636 | (extype != EXEC_UNKNOWN || etype != EXEC_UNKNOWN), | |
1637 | extype == EXEC_PARALLEL); | |
1638 | if (insn == -1) | |
1639 | { | |
1640 | if (extype != EXEC_UNKNOWN) | |
1641 | etype = extype; | |
1642 | as_bad (_("Cannot assemble instruction")); | |
1643 | return; | |
1644 | } | |
1645 | ||
1646 | if (etype != EXEC_UNKNOWN) | |
1647 | { | |
1648 | extype = etype; | |
1649 | etype = EXEC_UNKNOWN; | |
1650 | } | |
1651 | ||
1652 | /* Word multiply instructions must not be followed by either a load or a | |
1653 | 16-bit multiply instruction in the next cycle. */ | |
1654 | if ( (extype != EXEC_REVSEQ) | |
1655 | && prev_mul32_p | |
1656 | && (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16))) | |
1657 | { | |
1658 | /* However, load and multiply should able to be combined in a parallel | |
1659 | operation, so check for that first. */ | |
1660 | if (prev_insn != -1 | |
1661 | && (opcode.op->flags_used & FLAG_MEM) | |
1662 | && opcode.form->form < LONG | |
1663 | && (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN)) | |
1664 | && parallel_ok (&prev_opcode, (long) prev_insn, | |
1665 | &opcode, (long) insn, extype) | |
1666 | && write_2_short (&prev_opcode, (long) prev_insn, | |
1667 | &opcode, (long) insn, extype, fixups) == 0) | |
1668 | { | |
1669 | /* No instructions saved. */ | |
1670 | prev_insn = -1; | |
1671 | return; | |
1672 | } | |
1673 | else | |
1674 | { | |
1675 | /* Can't parallelize, flush previous instruction and emit a | |
1676 | word of NOPS, unless the previous instruction is a NOP, | |
1677 | in which case just flush it, as this will generate a word | |
1678 | of NOPs for us. */ | |
1679 | ||
1680 | if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0)) | |
1681 | d30v_cleanup (FALSE); | |
1682 | else | |
1683 | { | |
1684 | char *f; | |
1685 | ||
1686 | if (prev_insn != -1) | |
1687 | d30v_cleanup (TRUE); | |
1688 | else | |
1689 | { | |
1690 | f = frag_more (8); | |
d4f4f3fb | 1691 | dwarf2_emit_insn (8); |
ea1562b3 NC |
1692 | d30v_number_to_chars (f, NOP2, 8); |
1693 | ||
1694 | if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY) | |
1695 | { | |
1696 | if (opcode.op->flags_used & FLAG_MEM) | |
1697 | as_warn (_("word of NOPs added between word multiply and load")); | |
1698 | else | |
1699 | as_warn (_("word of NOPs added between word multiply and 16-bit multiply")); | |
252b5132 | 1700 | } |
252b5132 RH |
1701 | } |
1702 | } | |
252b5132 | 1703 | |
ea1562b3 NC |
1704 | extype = EXEC_UNKNOWN; |
1705 | } | |
1706 | } | |
1707 | else if ( (extype == EXEC_REVSEQ) | |
1708 | && cur_mul32_p | |
1709 | && (prev_opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16))) | |
1710 | { | |
1711 | /* Can't parallelize, flush current instruction and add a | |
1712 | sequential NOP. */ | |
1713 | write_1_short (&opcode, (long) insn, fixups->next->next, TRUE); | |
1714 | ||
1715 | /* Make the previous instruction the current one. */ | |
1716 | extype = EXEC_UNKNOWN; | |
1717 | insn = prev_insn; | |
1718 | now_seg = prev_seg; | |
1719 | now_subseg = prev_subseg; | |
1720 | prev_insn = -1; | |
1721 | cur_mul32_p = prev_mul32_p; | |
1722 | prev_mul32_p = 0; | |
1723 | memcpy (&opcode, &prev_opcode, sizeof (prev_opcode)); | |
1724 | } | |
1725 | ||
1726 | /* If this is a long instruction, write it and any previous short | |
1727 | instruction. */ | |
1728 | if (opcode.form->form >= LONG) | |
1729 | { | |
1730 | if (extype != EXEC_UNKNOWN) | |
1731 | as_bad (_("Instruction uses long version, so it cannot be mixed as specified")); | |
1732 | d30v_cleanup (FALSE); | |
1733 | write_long (&opcode, insn, fixups); | |
1734 | prev_insn = -1; | |
1735 | } | |
1736 | else if ((prev_insn != -1) | |
1737 | && (write_2_short | |
1738 | (&prev_opcode, (long) prev_insn, &opcode, | |
1739 | (long) insn, extype, fixups) == 0)) | |
1740 | { | |
1741 | /* No instructions saved. */ | |
1742 | prev_insn = -1; | |
1743 | } | |
1744 | else | |
1745 | { | |
1746 | if (extype != EXEC_UNKNOWN) | |
1747 | as_bad (_("Unable to mix instructions as specified")); | |
1748 | ||
1749 | /* Save off last instruction so it may be packed on next pass. */ | |
1750 | memcpy (&prev_opcode, &opcode, sizeof (prev_opcode)); | |
1751 | prev_insn = insn; | |
1752 | prev_seg = now_seg; | |
1753 | prev_subseg = now_subseg; | |
1754 | fixups = fixups->next; | |
1755 | prev_mul32_p = cur_mul32_p; | |
1756 | } | |
1757 | } | |
1758 | ||
1759 | /* If while processing a fixup, a reloc really needs to be created, | |
1760 | then it is done here. */ | |
1761 | ||
1762 | arelent * | |
1763 | tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) | |
1764 | { | |
1765 | arelent *reloc; | |
1766 | reloc = xmalloc (sizeof (arelent)); | |
1767 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); | |
1768 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
1769 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1770 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
1771 | if (reloc->howto == NULL) | |
1772 | { | |
1773 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1774 | _("reloc %d not supported by object file format"), | |
1775 | (int) fixp->fx_r_type); | |
1776 | return NULL; | |
1777 | } | |
1778 | ||
1779 | reloc->addend = 0; | |
1780 | return reloc; | |
1781 | } | |
1782 | ||
1783 | int | |
1784 | md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, | |
1785 | asection *seg ATTRIBUTE_UNUSED) | |
1786 | { | |
1787 | abort (); | |
1788 | return 0; | |
1789 | } | |
1790 | ||
1791 | long | |
1792 | md_pcrel_from_section (fixS *fixp, segT sec) | |
1793 | { | |
1794 | if (fixp->fx_addsy != (symbolS *) NULL | |
1795 | && (!S_IS_DEFINED (fixp->fx_addsy) | |
1796 | || (S_GET_SEGMENT (fixp->fx_addsy) != sec))) | |
1797 | return 0; | |
1798 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
1799 | } | |
1800 | ||
1801 | /* Called after the assembler has finished parsing the input file or | |
1802 | after a label is defined. Because the D30V assembler sometimes | |
1803 | saves short instructions to see if it can package them with the | |
1804 | next instruction, there may be a short instruction that still needs | |
1805 | written. */ | |
1806 | ||
1807 | int | |
1808 | d30v_cleanup (int use_sequential) | |
1809 | { | |
1810 | segT seg; | |
1811 | subsegT subseg; | |
1812 | ||
1813 | if (prev_insn != -1) | |
1814 | { | |
1815 | seg = now_seg; | |
1816 | subseg = now_subseg; | |
1817 | subseg_set (prev_seg, prev_subseg); | |
1818 | write_1_short (&prev_opcode, (long) prev_insn, fixups->next, | |
1819 | use_sequential); | |
1820 | subseg_set (seg, subseg); | |
1821 | prev_insn = -1; | |
1822 | if (use_sequential) | |
1823 | prev_mul32_p = FALSE; | |
1824 | } | |
1825 | ||
1826 | return 1; | |
1827 | } | |
1828 | ||
1829 | /* This function is called at the start of every line. It checks to | |
1830 | see if the first character is a '.', which indicates the start of a | |
1831 | pseudo-op. If it is, then write out any unwritten instructions. */ | |
1832 | ||
1833 | void | |
1834 | d30v_start_line (void) | |
1835 | { | |
1836 | char *c = input_line_pointer; | |
1837 | ||
1838 | while (ISSPACE (*c)) | |
1839 | c++; | |
1840 | ||
1841 | if (*c == '.') | |
1842 | d30v_cleanup (FALSE); | |
1843 | } | |
1844 | ||
1845 | static void | |
1846 | check_size (long value, int bits, char *file, int line) | |
1847 | { | |
1848 | int tmp, max; | |
1849 | ||
1850 | if (value < 0) | |
1851 | tmp = ~value; | |
1852 | else | |
1853 | tmp = value; | |
1854 | ||
1855 | max = (1 << (bits - 1)) - 1; | |
2fd5405a | 1856 | |
ea1562b3 NC |
1857 | if (tmp > max) |
1858 | as_bad_where (file, line, _("value too large to fit in %d bits"), bits); | |
252b5132 RH |
1859 | } |
1860 | ||
ea1562b3 | 1861 | /* d30v_frob_label() is called when after a label is recognized. */ |
2fd5405a | 1862 | |
ea1562b3 NC |
1863 | void |
1864 | d30v_frob_label (symbolS *lab) | |
252b5132 | 1865 | { |
ea1562b3 NC |
1866 | /* Emit any pending instructions. */ |
1867 | d30v_cleanup (FALSE); | |
a161fe53 | 1868 | |
ea1562b3 NC |
1869 | /* Update the label's address with the current output pointer. */ |
1870 | symbol_set_frag (lab, frag_now); | |
1871 | S_SET_VALUE (lab, (valueT) frag_now_fix ()); | |
252b5132 | 1872 | |
ea1562b3 NC |
1873 | /* Record this label for future adjustment after we find out what |
1874 | kind of data it references, and the required alignment therewith. */ | |
1875 | d30v_last_label = lab; | |
f2e25d93 AM |
1876 | |
1877 | dwarf2_emit_label (lab); | |
2fd5405a | 1878 | } |
252b5132 | 1879 | |
ea1562b3 NC |
1880 | /* Hook into cons for capturing alignment changes. */ |
1881 | ||
1882 | void | |
1883 | d30v_cons_align (int size) | |
252b5132 | 1884 | { |
ea1562b3 NC |
1885 | int log_size; |
1886 | ||
69da848e | 1887 | /* Don't specially align anything in debug sections. */ |
c2ce945a AM |
1888 | if ((now_seg->flags & SEC_ALLOC) == 0 |
1889 | || strcmp (now_seg->name, ".eh_frame") == 0) | |
69da848e AM |
1890 | return; |
1891 | ||
ea1562b3 NC |
1892 | log_size = 0; |
1893 | while ((size >>= 1) != 0) | |
1894 | ++log_size; | |
1895 | ||
1896 | if (d30v_current_align < log_size) | |
1897 | d30v_align (log_size, (char *) NULL, NULL); | |
1898 | else if (d30v_current_align > log_size) | |
1899 | d30v_current_align = log_size; | |
1900 | d30v_last_label = NULL; | |
252b5132 RH |
1901 | } |
1902 | ||
94f592af | 1903 | void |
55cf6793 | 1904 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 1905 | { |
2fd5405a | 1906 | char *where; |
252b5132 | 1907 | unsigned long insn, insn2; |
a161fe53 | 1908 | long value = *valP; |
94f592af NC |
1909 | |
1910 | if (fixP->fx_addsy == (symbolS *) NULL) | |
1911 | fixP->fx_done = 1; | |
1912 | ||
a161fe53 AM |
1913 | /* We don't support subtracting a symbol. */ |
1914 | if (fixP->fx_subsy != (symbolS *) NULL) | |
1915 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
2fd5405a | 1916 | |
252b5132 RH |
1917 | /* Fetch the instruction, insert the fully resolved operand |
1918 | value, and stuff the instruction back again. */ | |
94f592af | 1919 | where = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 1920 | insn = bfd_getb32 ((unsigned char *) where); |
2fd5405a | 1921 | |
94f592af | 1922 | switch (fixP->fx_r_type) |
252b5132 RH |
1923 | { |
1924 | case BFD_RELOC_8: /* Check for a bad .byte directive. */ | |
94f592af | 1925 | if (fixP->fx_addsy != NULL) |
252b5132 | 1926 | as_bad (_("line %d: unable to place address of symbol '%s' into a byte"), |
94f592af | 1927 | fixP->fx_line, S_GET_NAME (fixP->fx_addsy)); |
252b5132 | 1928 | else if (((unsigned)value) > 0xff) |
ebf19f1b | 1929 | as_bad (_("line %d: unable to place value %lx into a byte"), |
94f592af | 1930 | fixP->fx_line, value); |
252b5132 | 1931 | else |
2fd5405a | 1932 | *(unsigned char *) where = value; |
252b5132 | 1933 | break; |
2fd5405a | 1934 | |
252b5132 | 1935 | case BFD_RELOC_16: /* Check for a bad .short directive. */ |
94f592af | 1936 | if (fixP->fx_addsy != NULL) |
252b5132 | 1937 | as_bad (_("line %d: unable to place address of symbol '%s' into a short"), |
94f592af | 1938 | fixP->fx_line, S_GET_NAME (fixP->fx_addsy)); |
252b5132 | 1939 | else if (((unsigned)value) > 0xffff) |
ebf19f1b | 1940 | as_bad (_("line %d: unable to place value %lx into a short"), |
94f592af | 1941 | fixP->fx_line, value); |
252b5132 RH |
1942 | else |
1943 | bfd_putb16 ((bfd_vma) value, (unsigned char *) where); | |
1944 | break; | |
2fd5405a | 1945 | |
252b5132 | 1946 | case BFD_RELOC_64: /* Check for a bad .quad directive. */ |
94f592af | 1947 | if (fixP->fx_addsy != NULL) |
252b5132 | 1948 | as_bad (_("line %d: unable to place address of symbol '%s' into a quad"), |
94f592af | 1949 | fixP->fx_line, S_GET_NAME (fixP->fx_addsy)); |
252b5132 RH |
1950 | else |
1951 | { | |
1952 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); | |
1953 | bfd_putb32 (0, ((unsigned char *) where) + 4); | |
1954 | } | |
1955 | break; | |
2fd5405a | 1956 | |
252b5132 | 1957 | case BFD_RELOC_D30V_6: |
94f592af | 1958 | check_size (value, 6, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
1959 | insn |= value & 0x3F; |
1960 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1961 | break; | |
1962 | ||
1963 | case BFD_RELOC_D30V_9_PCREL: | |
94f592af | 1964 | if (fixP->fx_where & 0x7) |
252b5132 | 1965 | { |
94f592af | 1966 | if (fixP->fx_done) |
252b5132 RH |
1967 | value += 4; |
1968 | else | |
94f592af | 1969 | fixP->fx_r_type = BFD_RELOC_D30V_9_PCREL_R; |
252b5132 | 1970 | } |
94f592af | 1971 | check_size (value, 9, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
1972 | insn |= ((value >> 3) & 0x3F) << 12; |
1973 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1974 | break; | |
1975 | ||
1976 | case BFD_RELOC_D30V_15: | |
94f592af | 1977 | check_size (value, 15, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
1978 | insn |= (value >> 3) & 0xFFF; |
1979 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1980 | break; | |
1981 | ||
1982 | case BFD_RELOC_D30V_15_PCREL: | |
94f592af | 1983 | if (fixP->fx_where & 0x7) |
252b5132 | 1984 | { |
94f592af | 1985 | if (fixP->fx_done) |
252b5132 RH |
1986 | value += 4; |
1987 | else | |
94f592af | 1988 | fixP->fx_r_type = BFD_RELOC_D30V_15_PCREL_R; |
252b5132 | 1989 | } |
94f592af | 1990 | check_size (value, 15, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
1991 | insn |= (value >> 3) & 0xFFF; |
1992 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1993 | break; | |
1994 | ||
1995 | case BFD_RELOC_D30V_21: | |
94f592af | 1996 | check_size (value, 21, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
1997 | insn |= (value >> 3) & 0x3FFFF; |
1998 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1999 | break; | |
2000 | ||
2001 | case BFD_RELOC_D30V_21_PCREL: | |
94f592af | 2002 | if (fixP->fx_where & 0x7) |
252b5132 | 2003 | { |
94f592af | 2004 | if (fixP->fx_done) |
252b5132 RH |
2005 | value += 4; |
2006 | else | |
94f592af | 2007 | fixP->fx_r_type = BFD_RELOC_D30V_21_PCREL_R; |
252b5132 | 2008 | } |
94f592af | 2009 | check_size (value, 21, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
2010 | insn |= (value >> 3) & 0x3FFFF; |
2011 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
2012 | break; | |
2013 | ||
2014 | case BFD_RELOC_D30V_32: | |
2015 | insn2 = bfd_getb32 ((unsigned char *) where + 4); | |
2fd5405a NC |
2016 | insn |= (value >> 26) & 0x3F; /* Top 6 bits. */ |
2017 | insn2 |= ((value & 0x03FC0000) << 2); /* Next 8 bits. */ | |
2018 | insn2 |= value & 0x0003FFFF; /* Bottom 18 bits. */ | |
252b5132 RH |
2019 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); |
2020 | bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4); | |
2021 | break; | |
2022 | ||
2023 | case BFD_RELOC_D30V_32_PCREL: | |
2024 | insn2 = bfd_getb32 ((unsigned char *) where + 4); | |
81d4177b KH |
2025 | insn |= (value >> 26) & 0x3F; /* Top 6 bits. */ |
2026 | insn2 |= ((value & 0x03FC0000) << 2); /* Next 8 bits. */ | |
2027 | insn2 |= value & 0x0003FFFF; /* Bottom 18 bits. */ | |
252b5132 RH |
2028 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); |
2029 | bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4); | |
2030 | break; | |
2031 | ||
2032 | case BFD_RELOC_32: | |
2033 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); | |
2034 | break; | |
2035 | ||
2036 | default: | |
2037 | as_bad (_("line %d: unknown relocation type: 0x%x"), | |
94f592af | 2038 | fixP->fx_line, fixP->fx_r_type); |
252b5132 | 2039 | } |
252b5132 RH |
2040 | } |
2041 | ||
252b5132 RH |
2042 | /* Handle the .align pseudo-op. This aligns to a power of two. We |
2043 | hook here to latch the current alignment. */ | |
2044 | ||
2045 | static void | |
ea1562b3 | 2046 | s_d30v_align (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
2047 | { |
2048 | int align; | |
2049 | char fill, *pfill = NULL; | |
2050 | long max_alignment = 15; | |
2051 | ||
2052 | align = get_absolute_expression (); | |
2053 | if (align > max_alignment) | |
2054 | { | |
2055 | align = max_alignment; | |
2056 | as_warn (_("Alignment too large: %d assumed"), align); | |
2057 | } | |
2058 | else if (align < 0) | |
2059 | { | |
2060 | as_warn (_("Alignment negative: 0 assumed")); | |
2061 | align = 0; | |
2062 | } | |
2063 | ||
2064 | if (*input_line_pointer == ',') | |
2065 | { | |
2066 | input_line_pointer++; | |
2067 | fill = get_absolute_expression (); | |
2068 | pfill = &fill; | |
2069 | } | |
2070 | ||
2071 | d30v_last_label = NULL; | |
2072 | d30v_align (align, pfill, NULL); | |
2073 | ||
2074 | demand_empty_rest_of_line (); | |
2075 | } | |
2076 | ||
2077 | /* Handle the .text pseudo-op. This is like the usual one, but it | |
2078 | clears the saved last label and resets known alignment. */ | |
2079 | ||
2080 | static void | |
ea1562b3 | 2081 | s_d30v_text (int i) |
252b5132 RH |
2082 | |
2083 | { | |
2084 | s_text (i); | |
2085 | d30v_last_label = NULL; | |
2086 | d30v_current_align = 0; | |
2087 | d30v_current_align_seg = now_seg; | |
2088 | } | |
2089 | ||
2090 | /* Handle the .data pseudo-op. This is like the usual one, but it | |
2091 | clears the saved last label and resets known alignment. */ | |
2092 | ||
2093 | static void | |
ea1562b3 | 2094 | s_d30v_data (int i) |
252b5132 RH |
2095 | { |
2096 | s_data (i); | |
2097 | d30v_last_label = NULL; | |
2098 | d30v_current_align = 0; | |
2099 | d30v_current_align_seg = now_seg; | |
2100 | } | |
2101 | ||
2102 | /* Handle the .section pseudo-op. This is like the usual one, but it | |
2103 | clears the saved last label and resets known alignment. */ | |
2104 | ||
2105 | static void | |
ea1562b3 | 2106 | s_d30v_section (int ignore) |
252b5132 RH |
2107 | { |
2108 | obj_elf_section (ignore); | |
2109 | d30v_last_label = NULL; | |
2110 | d30v_current_align = 0; | |
2111 | d30v_current_align_seg = now_seg; | |
2112 | } | |
ea1562b3 NC |
2113 | |
2114 | /* The target specific pseudo-ops which we support. */ | |
2115 | const pseudo_typeS md_pseudo_table[] = | |
2116 | { | |
2117 | { "word", cons, 4 }, | |
2118 | { "hword", cons, 2 }, | |
2119 | { "align", s_d30v_align, 0 }, | |
2120 | { "text", s_d30v_text, 0 }, | |
2121 | { "data", s_d30v_data, 0 }, | |
2122 | { "section", s_d30v_section, 0 }, | |
2123 | { "section.s", s_d30v_section, 0 }, | |
2124 | { "sect", s_d30v_section, 0 }, | |
2125 | { "sect.s", s_d30v_section, 0 }, | |
2126 | { NULL, NULL, 0 } | |
2127 | }; |