Commit | Line | Data |
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9b1168d6 MH |
1 | /* tc-d30v.c -- Assembler code for the Mitsubishi D30V |
2 | ||
ccc12f73 | 3 | Copyright (C) 1997, 1998 Free Software Foundation. |
9b1168d6 MH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include <stdio.h> | |
23 | #include <ctype.h> | |
24 | #include "as.h" | |
25 | #include "subsegs.h" | |
26 | #include "opcode/d30v.h" | |
27 | ||
28 | const char comment_chars[] = ";"; | |
29 | const char line_comment_chars[] = "#"; | |
30 | const char line_separator_chars[] = ""; | |
aa7bf2a8 | 31 | const char *md_shortopts = "OnNcC"; |
9b1168d6 MH |
32 | const char EXP_CHARS[] = "eE"; |
33 | const char FLT_CHARS[] = "dD"; | |
34 | ||
343b2ab8 MM |
35 | #define NOP_MULTIPLY 1 |
36 | #define NOP_ALL 2 | |
37 | static int warn_nops = 0; | |
38 | static int Optimizing = 0; | |
aa7bf2a8 | 39 | static int warn_register_name_conflicts = 1; |
9b1168d6 | 40 | |
e0882f34 MM |
41 | #define FORCE_SHORT 1 |
42 | #define FORCE_LONG 2 | |
43 | ||
343b2ab8 MM |
44 | /* EXEC types. */ |
45 | typedef enum _exec_type | |
46 | { | |
47 | EXEC_UNKNOWN, /* no order specified */ | |
ccc12f73 FF |
48 | EXEC_PARALLEL, /* done in parallel (FM=00) */ |
49 | EXEC_SEQ, /* sequential (FM=01) */ | |
50 | EXEC_REVSEQ /* reverse sequential (FM=10) */ | |
343b2ab8 MM |
51 | } exec_type_enum; |
52 | ||
9b1168d6 MH |
53 | /* fixups */ |
54 | #define MAX_INSN_FIXUPS (5) | |
55 | struct d30v_fixup | |
56 | { | |
57 | expressionS exp; | |
58 | int operand; | |
59 | int pcrel; | |
60 | int size; | |
61 | bfd_reloc_code_real_type reloc; | |
62 | }; | |
63 | ||
64 | typedef struct _fixups | |
65 | { | |
66 | int fc; | |
67 | struct d30v_fixup fix[MAX_INSN_FIXUPS]; | |
68 | struct _fixups *next; | |
69 | } Fixups; | |
70 | ||
71 | static Fixups FixUps[2]; | |
72 | static Fixups *fixups; | |
73 | ||
973e995d | 74 | /* Whether current and previous instruction are word multiply insns. */ |
7d515759 RH |
75 | static int cur_mul32_p = 0; |
76 | static int prev_mul32_p = 0; | |
343b2ab8 | 77 | |
ccc12f73 FF |
78 | /* The flag_explicitly_parallel is true iff the instruction being assembled |
79 | has been explicitly written as a parallel short-instruction pair by the | |
80 | human programmer. It is used in parallel_ok() to distinguish between | |
81 | those dangerous parallelizations attempted by the human, which are to be | |
82 | allowed, and those attempted by the assembler, which are not. It is set | |
83 | from md_assemble(). */ | |
84 | static int flag_explicitly_parallel = 0; | |
85 | static int flag_xp_state = 0; | |
86 | ||
e21cafde FCE |
87 | /* Whether current and previous left sub-instruction disables |
88 | execution of right sub-instruction. */ | |
89 | static int cur_left_kills_right_p = 0; | |
90 | static int prev_left_kills_right_p = 0; | |
91 | ||
7d515759 RH |
92 | /* The known current alignment of the current section. */ |
93 | static int d30v_current_align; | |
94 | static segT d30v_current_align_seg; | |
95 | ||
96 | /* The last seen label in the current section. This is used to auto-align | |
97 | labels preceeding instructions. */ | |
98 | static symbolS *d30v_last_label; | |
99 | ||
343b2ab8 | 100 | /* Two nops */ |
633f5016 NC |
101 | #define NOP_LEFT ((long long) NOP << 32) |
102 | #define NOP_RIGHT ((long long) NOP) | |
343b2ab8 MM |
103 | #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT) |
104 | ||
9b1168d6 MH |
105 | /* local functions */ |
106 | static int reg_name_search PARAMS ((char *name)); | |
107 | static int register_name PARAMS ((expressionS *expressionP)); | |
108 | static int check_range PARAMS ((unsigned long num, int bits, int flags)); | |
109 | static int postfix PARAMS ((char *p)); | |
110 | static bfd_reloc_code_real_type get_reloc PARAMS ((struct d30v_operand *op, int rel_flag)); | |
111 | static int get_operands PARAMS ((expressionS exp[], int cmp_hack)); | |
e0882f34 MM |
112 | static struct d30v_format *find_format PARAMS ((struct d30v_opcode *opcode, |
113 | expressionS ops[],int fsize, int cmp_hack)); | |
9b1168d6 MH |
114 | static long long build_insn PARAMS ((struct d30v_insn *opcode, expressionS *opers)); |
115 | static void write_long PARAMS ((struct d30v_insn *opcode, long long insn, Fixups *fx)); | |
aa7bf2a8 NC |
116 | static void write_1_short PARAMS ((struct d30v_insn *opcode, long long insn, |
117 | Fixups *fx, int use_sequential)); | |
9b1168d6 | 118 | static int write_2_short PARAMS ((struct d30v_insn *opcode1, long long insn1, |
343b2ab8 | 119 | struct d30v_insn *opcode2, long long insn2, exec_type_enum exec_type, Fixups *fx)); |
daaef8f8 | 120 | static long long do_assemble PARAMS ((char *str, struct d30v_insn *opcode, |
7a0f469b | 121 | int shortp, int is_parallel)); |
9b1168d6 MH |
122 | static int parallel_ok PARAMS ((struct d30v_insn *opcode1, unsigned long insn1, |
123 | struct d30v_insn *opcode2, unsigned long insn2, | |
343b2ab8 | 124 | exec_type_enum exec_type)); |
9b1168d6 | 125 | static void d30v_number_to_chars PARAMS ((char *buf, long long value, int nbytes)); |
e0882f34 | 126 | static void check_size PARAMS ((long value, int bits, char *file, int line)); |
7d515759 RH |
127 | static void d30v_align PARAMS ((int, char *, symbolS *)); |
128 | static void s_d30v_align PARAMS ((int)); | |
129 | static void s_d30v_text PARAMS ((int)); | |
130 | static void s_d30v_data PARAMS ((int)); | |
131 | static void s_d30v_section PARAMS ((int)); | |
9b1168d6 MH |
132 | |
133 | struct option md_longopts[] = { | |
134 | {NULL, no_argument, NULL, 0} | |
135 | }; | |
136 | size_t md_longopts_size = sizeof(md_longopts); | |
137 | ||
138 | ||
139 | /* The target specific pseudo-ops which we support. */ | |
140 | const pseudo_typeS md_pseudo_table[] = | |
141 | { | |
e0882f34 MM |
142 | { "word", cons, 4 }, |
143 | { "hword", cons, 2 }, | |
7d515759 RH |
144 | { "align", s_d30v_align, 0 }, |
145 | { "text", s_d30v_text, 0 }, | |
146 | { "data", s_d30v_data, 0 }, | |
147 | { "section", s_d30v_section, 0 }, | |
148 | { "section.s", s_d30v_section, 0 }, | |
149 | { "sect", s_d30v_section, 0 }, | |
150 | { "sect.s", s_d30v_section, 0 }, | |
e0882f34 | 151 | { NULL, NULL, 0 } |
9b1168d6 MH |
152 | }; |
153 | ||
154 | /* Opcode hash table. */ | |
155 | static struct hash_control *d30v_hash; | |
156 | ||
157 | /* reg_name_search does a binary search of the pre_defined_registers | |
158 | array to see if "name" is a valid regiter name. Returns the register | |
159 | number from the array on success, or -1 on failure. */ | |
160 | ||
161 | static int | |
162 | reg_name_search (name) | |
163 | char *name; | |
164 | { | |
165 | int middle, low, high; | |
166 | int cmp; | |
167 | ||
168 | low = 0; | |
7a0f469b | 169 | high = reg_name_cnt () - 1; |
9b1168d6 MH |
170 | |
171 | do | |
172 | { | |
173 | middle = (low + high) / 2; | |
174 | cmp = strcasecmp (name, pre_defined_registers[middle].name); | |
175 | if (cmp < 0) | |
176 | high = middle - 1; | |
177 | else if (cmp > 0) | |
178 | low = middle + 1; | |
21056c79 NC |
179 | else |
180 | { | |
181 | if (symbol_find (name) != NULL) | |
182 | { | |
183 | if (warn_register_name_conflicts) | |
a173c5db | 184 | as_warn (_("Register name %s conflicts with symbol of the same name"), |
21056c79 NC |
185 | name); |
186 | } | |
187 | ||
188 | return pre_defined_registers[middle].value; | |
189 | } | |
9b1168d6 MH |
190 | } |
191 | while (low <= high); | |
aa7bf2a8 | 192 | |
9b1168d6 MH |
193 | return -1; |
194 | } | |
195 | ||
196 | /* register_name() checks the string at input_line_pointer | |
a173c5db | 197 | to see if it is a valid register name. */ |
9b1168d6 MH |
198 | |
199 | static int | |
200 | register_name (expressionP) | |
201 | expressionS *expressionP; | |
202 | { | |
203 | int reg_number; | |
204 | char c, *p = input_line_pointer; | |
205 | ||
206 | while (*p && *p!='\n' && *p!='\r' && *p !=',' && *p!=' ' && *p!=')') | |
207 | p++; | |
208 | ||
209 | c = *p; | |
210 | if (c) | |
211 | *p++ = 0; | |
212 | ||
213 | /* look to see if it's in the register table */ | |
214 | reg_number = reg_name_search (input_line_pointer); | |
215 | if (reg_number >= 0) | |
216 | { | |
217 | expressionP->X_op = O_register; | |
218 | /* temporarily store a pointer to the string here */ | |
219 | expressionP->X_op_symbol = (struct symbol *)input_line_pointer; | |
220 | expressionP->X_add_number = reg_number; | |
221 | input_line_pointer = p; | |
222 | return 1; | |
223 | } | |
224 | if (c) | |
225 | *(p-1) = c; | |
226 | return 0; | |
227 | } | |
228 | ||
229 | ||
230 | static int | |
231 | check_range (num, bits, flags) | |
232 | unsigned long num; | |
233 | int bits; | |
234 | int flags; | |
235 | { | |
343b2ab8 | 236 | long min, max; |
9b1168d6 MH |
237 | int retval=0; |
238 | ||
239 | /* don't bother checking 32-bit values */ | |
240 | if (bits == 32) | |
241 | return 0; | |
242 | ||
e21cafde FCE |
243 | if (flags & OPERAND_SHIFT) |
244 | { | |
245 | /* We know that all shifts are right by three bits.... */ | |
246 | ||
247 | if (flags & OPERAND_SIGNED) | |
248 | num = (unsigned long) (((/*signed*/ long) num) >> 3); | |
249 | else | |
250 | num >>= 3; | |
251 | } | |
252 | ||
9b1168d6 MH |
253 | if (flags & OPERAND_SIGNED) |
254 | { | |
255 | max = (1 << (bits - 1))-1; | |
e0882f34 | 256 | min = - (1 << (bits - 1)); |
9b1168d6 MH |
257 | if (((long)num > max) || ((long)num < min)) |
258 | retval = 1; | |
259 | } | |
260 | else | |
261 | { | |
262 | max = (1 << bits) - 1; | |
263 | min = 0; | |
264 | if ((num > max) || (num < min)) | |
265 | retval = 1; | |
266 | } | |
633f5016 | 267 | |
9b1168d6 MH |
268 | return retval; |
269 | } | |
270 | ||
271 | ||
272 | void | |
273 | md_show_usage (stream) | |
274 | FILE *stream; | |
275 | { | |
7a0f469b | 276 | fprintf (stream, _("\nD30V options:\n\ |
343b2ab8 MM |
277 | -O Make adjacent short instructions parallel if possible.\n\ |
278 | -n Warn about all NOPs inserted by the assembler.\n\ | |
aa7bf2a8 NC |
279 | -N Warn about NOPs inserted after word multiplies.\n\ |
280 | -c Warn about symbols whoes names match register names.\n\ | |
281 | -C Opposite of -C. -c is the default.\n")); | |
282 | } | |
9b1168d6 MH |
283 | |
284 | int | |
285 | md_parse_option (c, arg) | |
286 | int c; | |
287 | char *arg; | |
288 | { | |
289 | switch (c) | |
290 | { | |
9b1168d6 | 291 | /* Optimize. Will attempt to parallelize operations */ |
343b2ab8 | 292 | case 'O': |
9b1168d6 MH |
293 | Optimizing = 1; |
294 | break; | |
343b2ab8 MM |
295 | |
296 | /* Warn about all NOPS that the assembler inserts. */ | |
297 | case 'n': | |
298 | warn_nops = NOP_ALL; | |
299 | break; | |
300 | ||
301 | /* Warn about the NOPS that the assembler inserts because of the | |
302 | multiply hazard. */ | |
303 | case 'N': | |
304 | warn_nops = NOP_MULTIPLY; | |
305 | break; | |
306 | ||
aa7bf2a8 NC |
307 | case 'c': |
308 | warn_register_name_conflicts = 1; | |
309 | break; | |
310 | ||
311 | case 'C': | |
312 | warn_register_name_conflicts = 0; | |
313 | break; | |
314 | ||
9b1168d6 MH |
315 | default: |
316 | return 0; | |
317 | } | |
318 | return 1; | |
319 | } | |
320 | ||
321 | symbolS * | |
322 | md_undefined_symbol (name) | |
323 | char *name; | |
324 | { | |
325 | return 0; | |
326 | } | |
327 | ||
328 | /* Turn a string in input_line_pointer into a floating point constant of type | |
329 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
330 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
331 | */ | |
332 | char * | |
333 | md_atof (type, litP, sizeP) | |
334 | int type; | |
335 | char *litP; | |
336 | int *sizeP; | |
337 | { | |
338 | int prec; | |
339 | LITTLENUM_TYPE words[4]; | |
340 | char *t; | |
341 | int i; | |
342 | ||
343 | switch (type) | |
344 | { | |
345 | case 'f': | |
346 | prec = 2; | |
347 | break; | |
348 | case 'd': | |
349 | prec = 4; | |
350 | break; | |
351 | default: | |
352 | *sizeP = 0; | |
48401fcf | 353 | return _("bad call to md_atof"); |
9b1168d6 MH |
354 | } |
355 | ||
356 | t = atof_ieee (input_line_pointer, type, words); | |
357 | if (t) | |
358 | input_line_pointer = t; | |
359 | ||
360 | *sizeP = prec * 2; | |
361 | ||
362 | for (i = 0; i < prec; i++) | |
363 | { | |
364 | md_number_to_chars (litP, (valueT) words[i], 2); | |
365 | litP += 2; | |
366 | } | |
367 | return NULL; | |
368 | } | |
369 | ||
370 | void | |
371 | md_convert_frag (abfd, sec, fragP) | |
372 | bfd *abfd; | |
373 | asection *sec; | |
374 | fragS *fragP; | |
375 | { | |
376 | abort (); | |
377 | } | |
378 | ||
379 | valueT | |
380 | md_section_align (seg, addr) | |
381 | asection *seg; | |
382 | valueT addr; | |
383 | { | |
384 | int align = bfd_get_section_alignment (stdoutput, seg); | |
385 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
386 | } | |
387 | ||
388 | ||
389 | void | |
390 | md_begin () | |
391 | { | |
633f5016 | 392 | struct d30v_opcode * opcode; |
7a0f469b | 393 | d30v_hash = hash_new (); |
9b1168d6 MH |
394 | |
395 | /* Insert opcode names into a hash table. */ | |
396 | for (opcode = (struct d30v_opcode *)d30v_opcode_table; opcode->name; opcode++) | |
397 | hash_insert (d30v_hash, opcode->name, (char *) opcode); | |
398 | ||
399 | fixups = &FixUps[0]; | |
400 | FixUps[0].next = &FixUps[1]; | |
401 | FixUps[1].next = &FixUps[0]; | |
7d515759 RH |
402 | |
403 | d30v_current_align_seg = now_seg; | |
9b1168d6 MH |
404 | } |
405 | ||
406 | ||
407 | /* this function removes the postincrement or postdecrement | |
408 | operator ( '+' or '-' ) from an expression */ | |
409 | ||
410 | static int postfix (p) | |
411 | char *p; | |
412 | { | |
413 | while (*p != '-' && *p != '+') | |
414 | { | |
2c268a85 | 415 | if (*p==0 || *p=='\n' || *p=='\r' || *p==' ' || *p==',') |
9b1168d6 MH |
416 | break; |
417 | p++; | |
418 | } | |
419 | ||
420 | if (*p == '-') | |
421 | { | |
422 | *p = ' '; | |
423 | return (-1); | |
424 | } | |
425 | if (*p == '+') | |
426 | { | |
427 | *p = ' '; | |
428 | return (1); | |
429 | } | |
430 | ||
431 | return (0); | |
432 | } | |
433 | ||
434 | ||
435 | static bfd_reloc_code_real_type | |
436 | get_reloc (op, rel_flag) | |
437 | struct d30v_operand *op; | |
438 | int rel_flag; | |
439 | { | |
440 | switch (op->bits) | |
441 | { | |
442 | case 6: | |
e0882f34 MM |
443 | if (op->flags & OPERAND_SHIFT) |
444 | return BFD_RELOC_D30V_9_PCREL; | |
445 | else | |
446 | return BFD_RELOC_D30V_6; | |
447 | break; | |
9b1168d6 MH |
448 | case 12: |
449 | if (!(op->flags & OPERAND_SHIFT)) | |
7a0f469b | 450 | as_warn (_("unexpected 12-bit reloc type")); |
9b1168d6 MH |
451 | if (rel_flag == RELOC_PCREL) |
452 | return BFD_RELOC_D30V_15_PCREL; | |
453 | else | |
454 | return BFD_RELOC_D30V_15; | |
455 | case 18: | |
456 | if (!(op->flags & OPERAND_SHIFT)) | |
7a0f469b | 457 | as_warn (_("unexpected 18-bit reloc type")); |
9b1168d6 MH |
458 | if (rel_flag == RELOC_PCREL) |
459 | return BFD_RELOC_D30V_21_PCREL; | |
460 | else | |
461 | return BFD_RELOC_D30V_21; | |
462 | case 32: | |
463 | if (rel_flag == RELOC_PCREL) | |
464 | return BFD_RELOC_D30V_32_PCREL; | |
465 | else | |
466 | return BFD_RELOC_D30V_32; | |
467 | default: | |
468 | return 0; | |
469 | } | |
470 | } | |
471 | ||
472 | /* get_operands parses a string of operands and returns | |
473 | an array of expressions */ | |
474 | ||
475 | static int | |
476 | get_operands (exp, cmp_hack) | |
477 | expressionS exp[]; | |
478 | int cmp_hack; | |
479 | { | |
480 | char *p = input_line_pointer; | |
481 | int numops = 0; | |
482 | int post = 0; | |
483 | ||
484 | if (cmp_hack) | |
485 | { | |
486 | exp[numops].X_op = O_absent; | |
487 | exp[numops++].X_add_number = cmp_hack - 1; | |
488 | } | |
489 | ||
490 | while (*p) | |
491 | { | |
492 | while (*p == ' ' || *p == '\t' || *p == ',') | |
493 | p++; | |
494 | if (*p==0 || *p=='\n' || *p=='\r') | |
495 | break; | |
496 | ||
497 | if (*p == '@') | |
498 | { | |
499 | p++; | |
500 | exp[numops].X_op = O_absent; | |
501 | if (*p == '(') | |
502 | { | |
503 | p++; | |
504 | exp[numops].X_add_number = OPERAND_ATPAR; | |
505 | post = postfix (p); | |
506 | } | |
507 | else if (*p == '-') | |
508 | { | |
509 | p++; | |
510 | exp[numops].X_add_number = OPERAND_ATMINUS; | |
511 | } | |
512 | else | |
513 | { | |
514 | exp[numops].X_add_number = OPERAND_ATSIGN; | |
515 | post = postfix (p); | |
516 | } | |
517 | numops++; | |
518 | continue; | |
519 | } | |
520 | ||
521 | if (*p == ')') | |
522 | { | |
523 | /* just skip the trailing paren */ | |
524 | p++; | |
525 | continue; | |
526 | } | |
527 | ||
528 | input_line_pointer = p; | |
529 | ||
530 | /* check to see if it might be a register name */ | |
531 | if (!register_name (&exp[numops])) | |
532 | { | |
533 | /* parse as an expression */ | |
534 | expression (&exp[numops]); | |
535 | } | |
536 | ||
537 | if (exp[numops].X_op == O_illegal) | |
48401fcf | 538 | as_bad (_("illegal operand")); |
9b1168d6 | 539 | else if (exp[numops].X_op == O_absent) |
48401fcf | 540 | as_bad (_("missing operand")); |
9b1168d6 MH |
541 | |
542 | numops++; | |
543 | p = input_line_pointer; | |
544 | ||
545 | switch (post) | |
546 | { | |
547 | case -1: /* postdecrement mode */ | |
548 | exp[numops].X_op = O_absent; | |
549 | exp[numops++].X_add_number = OPERAND_MINUS; | |
550 | break; | |
551 | case 1: /* postincrement mode */ | |
552 | exp[numops].X_op = O_absent; | |
553 | exp[numops++].X_add_number = OPERAND_PLUS; | |
554 | break; | |
555 | } | |
556 | post = 0; | |
557 | } | |
558 | ||
559 | exp[numops].X_op = 0; | |
560 | return (numops); | |
561 | } | |
562 | ||
9b1168d6 MH |
563 | /* build_insn generates the instruction. It does everything */ |
564 | /* but write the FM bits. */ | |
565 | ||
566 | static long long | |
567 | build_insn (opcode, opers) | |
568 | struct d30v_insn *opcode; | |
569 | expressionS *opers; | |
570 | { | |
343b2ab8 | 571 | int i, length, bits, shift, flags; |
9b1168d6 MH |
572 | unsigned int number, id=0; |
573 | long long insn; | |
574 | struct d30v_opcode *op = opcode->op; | |
575 | struct d30v_format *form = opcode->form; | |
576 | ||
9b1168d6 | 577 | insn = opcode->ecc << 28 | op->op1 << 25 | op->op2 << 20 | form->modifier << 18; |
e0882f34 | 578 | |
9b1168d6 MH |
579 | for (i=0; form->operands[i]; i++) |
580 | { | |
581 | flags = d30v_operand_table[form->operands[i]].flags; | |
582 | ||
9b1168d6 MH |
583 | /* must be a register or number */ |
584 | if (!(flags & OPERAND_REG) && !(flags & OPERAND_NUM) && | |
585 | !(flags & OPERAND_NAME) && !(flags & OPERAND_SPECIAL)) | |
586 | continue; | |
587 | ||
588 | bits = d30v_operand_table[form->operands[i]].bits; | |
e0882f34 MM |
589 | if (flags & OPERAND_SHIFT) |
590 | bits += 3; | |
591 | ||
9b1168d6 MH |
592 | length = d30v_operand_table[form->operands[i]].length; |
593 | shift = 12 - d30v_operand_table[form->operands[i]].position; | |
e0882f34 MM |
594 | if (opers[i].X_op != O_symbol) |
595 | number = opers[i].X_add_number; | |
596 | else | |
597 | number = 0; | |
9b1168d6 MH |
598 | if (flags & OPERAND_REG) |
599 | { | |
e0882f34 MM |
600 | /* check for mvfsys or mvtsys control registers */ |
601 | if (flags & OPERAND_CONTROL && (number & 0x7f) > MAX_CONTROL_REG) | |
9b1168d6 MH |
602 | { |
603 | /* PSWL or PSWH */ | |
e0882f34 MM |
604 | id = (number & 0x7f) - MAX_CONTROL_REG; |
605 | number = 0; | |
9b1168d6 MH |
606 | } |
607 | else if (number & OPERAND_FLAG) | |
608 | { | |
609 | id = 3; /* number is a flag register */ | |
610 | } | |
e0882f34 | 611 | number &= 0x7F; |
9b1168d6 MH |
612 | } |
613 | else if (flags & OPERAND_SPECIAL) | |
614 | { | |
615 | number = id; | |
616 | } | |
9b1168d6 MH |
617 | |
618 | if (opers[i].X_op != O_register && opers[i].X_op != O_constant && !(flags & OPERAND_NAME)) | |
619 | { | |
620 | /* now create a fixup */ | |
621 | ||
622 | if (fixups->fc >= MAX_INSN_FIXUPS) | |
48401fcf | 623 | as_fatal (_("too many fixups")); |
9b1168d6 MH |
624 | |
625 | fixups->fix[fixups->fc].reloc = | |
7a0f469b | 626 | get_reloc ((struct d30v_operand *)&d30v_operand_table[form->operands[i]], op->reloc_flag); |
9b1168d6 MH |
627 | fixups->fix[fixups->fc].size = 4; |
628 | fixups->fix[fixups->fc].exp = opers[i]; | |
629 | fixups->fix[fixups->fc].operand = form->operands[i]; | |
e0882f34 MM |
630 | if (fixups->fix[fixups->fc].reloc == BFD_RELOC_D30V_9_PCREL) |
631 | fixups->fix[fixups->fc].pcrel = RELOC_PCREL; | |
632 | else | |
633 | fixups->fix[fixups->fc].pcrel = op->reloc_flag; | |
9b1168d6 MH |
634 | (fixups->fc)++; |
635 | } | |
636 | ||
637 | /* truncate to the proper number of bits */ | |
2c268a85 | 638 | if ((opers[i].X_op == O_constant) && check_range (number, bits, flags)) |
7a0f469b | 639 | as_bad (_("operand out of range: %d"),number); |
2c268a85 | 640 | if (bits < 31) |
9b1168d6 | 641 | number &= 0x7FFFFFFF >> (31 - bits); |
e0882f34 MM |
642 | if (flags & OPERAND_SHIFT) |
643 | number >>= 3; | |
9b1168d6 MH |
644 | if (bits == 32) |
645 | { | |
646 | /* it's a LONG instruction */ | |
647 | insn |= (number >> 26); /* top 6 bits */ | |
648 | insn <<= 32; /* shift the first word over */ | |
649 | insn |= ((number & 0x03FC0000) << 2); /* next 8 bits */ | |
650 | insn |= number & 0x0003FFFF; /* bottom 18 bits */ | |
651 | } | |
652 | else | |
653 | insn |= number << shift; | |
654 | } | |
655 | return insn; | |
656 | } | |
657 | ||
658 | ||
659 | /* write out a long form instruction */ | |
660 | static void | |
661 | write_long (opcode, insn, fx) | |
662 | struct d30v_insn *opcode; | |
663 | long long insn; | |
664 | Fixups *fx; | |
665 | { | |
666 | int i, where; | |
7a0f469b | 667 | char *f = frag_more (8); |
9b1168d6 MH |
668 | |
669 | insn |= FM11; | |
670 | d30v_number_to_chars (f, insn, 8); | |
671 | ||
672 | for (i=0; i < fx->fc; i++) | |
673 | { | |
674 | if (fx->fix[i].reloc) | |
675 | { | |
676 | where = f - frag_now->fr_literal; | |
9b1168d6 MH |
677 | fix_new_exp (frag_now, |
678 | where, | |
679 | fx->fix[i].size, | |
680 | &(fx->fix[i].exp), | |
681 | fx->fix[i].pcrel, | |
682 | fx->fix[i].reloc); | |
683 | } | |
684 | } | |
685 | fx->fc = 0; | |
686 | } | |
687 | ||
688 | ||
aa7bf2a8 | 689 | /* Write out a short form instruction by itself. */ |
9b1168d6 | 690 | static void |
aa7bf2a8 | 691 | write_1_short (opcode, insn, fx, use_sequential) |
9b1168d6 MH |
692 | struct d30v_insn *opcode; |
693 | long long insn; | |
694 | Fixups *fx; | |
aa7bf2a8 | 695 | int use_sequential; |
9b1168d6 | 696 | { |
7a0f469b | 697 | char *f = frag_more (8); |
9b1168d6 MH |
698 | int i, where; |
699 | ||
343b2ab8 | 700 | if (warn_nops == NOP_ALL) |
aa7bf2a8 NC |
701 | as_warn (_("%s NOP inserted"), use_sequential ? |
702 | _("sequential") : _("parallel")); | |
343b2ab8 | 703 | |
aa7bf2a8 NC |
704 | /* The other container needs to be NOP. */ |
705 | if (use_sequential) | |
706 | { | |
707 | /* Use a sequential NOP rather than a parallel one, | |
708 | as the current instruction is a FLAG_MUL32 type one | |
709 | and the next instruction is a load. */ | |
710 | ||
711 | /* According to 4.3.1: for FM=01, sub-instructions performed | |
712 | only by IU cannot be encoded in L-container. */ | |
713 | ||
714 | if (opcode->op->unit == IU) | |
715 | insn |= FM10 | NOP_LEFT; /* right then left */ | |
716 | else | |
717 | insn = FM01 | (insn << 32) | NOP_RIGHT; /* left then right */ | |
718 | } | |
719 | else | |
720 | { | |
721 | /* According to 4.3.1: for FM=00, sub-instructions performed | |
722 | only by IU cannot be encoded in L-container. */ | |
723 | ||
973e995d NC |
724 | if (opcode->op->unit == IU) |
725 | insn |= FM00 | NOP_LEFT; /* right container */ | |
726 | else | |
727 | insn = FM00 | (insn << 32) | NOP_RIGHT; /* left container */ | |
aa7bf2a8 | 728 | } |
9b1168d6 MH |
729 | |
730 | d30v_number_to_chars (f, insn, 8); | |
731 | ||
732 | for (i=0; i < fx->fc; i++) | |
733 | { | |
734 | if (fx->fix[i].reloc) | |
735 | { | |
736 | where = f - frag_now->fr_literal; | |
9b1168d6 MH |
737 | fix_new_exp (frag_now, |
738 | where, | |
739 | fx->fix[i].size, | |
740 | &(fx->fix[i].exp), | |
741 | fx->fix[i].pcrel, | |
742 | fx->fix[i].reloc); | |
743 | } | |
744 | } | |
745 | fx->fc = 0; | |
746 | } | |
747 | ||
633f5016 NC |
748 | /* Write out a short form instruction if possible. |
749 | Return number of instructions not written out. */ | |
9b1168d6 MH |
750 | static int |
751 | write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx) | |
752 | struct d30v_insn *opcode1, *opcode2; | |
753 | long long insn1, insn2; | |
343b2ab8 | 754 | exec_type_enum exec_type; |
9b1168d6 MH |
755 | Fixups *fx; |
756 | { | |
343b2ab8 | 757 | long long insn = NOP2; |
9b1168d6 MH |
758 | char *f; |
759 | int i,j, where; | |
760 | ||
a173c5db NC |
761 | if (exec_type == EXEC_SEQ |
762 | && (opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR)) | |
644a2654 | 763 | && ((opcode1->op->flags_used & FLAG_DELAY) == 0) |
a173c5db | 764 | && ((opcode1->ecc == ECC_AL) || ! Optimizing)) |
9b1168d6 | 765 | { |
644a2654 NC |
766 | /* Unconditional, non-delayed branches kill instructions in |
767 | the right bin. Conditional branches don't always but if | |
768 | we are not optimizing, then we have been asked to produce | |
769 | an error about such constructs. For the purposes of this | |
770 | test, subroutine calls are considered to be branches. */ | |
aa7bf2a8 NC |
771 | write_1_short (opcode1, insn1, fx->next, false); |
772 | return 1; | |
9b1168d6 | 773 | } |
a173c5db NC |
774 | |
775 | /* Note: we do not have to worry about subroutine calls occuring | |
776 | in the right hand container. The return address is always | |
777 | aligned to the next 64 bit boundary, be that 64 or 32 bit away. */ | |
778 | ||
9b1168d6 MH |
779 | switch (exec_type) |
780 | { | |
a173c5db | 781 | case EXEC_UNKNOWN: /* Order not specified. */ |
973e995d NC |
782 | if (Optimizing |
783 | && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type) | |
784 | && ! ( (opcode1->op->unit == EITHER_BUT_PREFER_MU | |
785 | || opcode1->op->unit == MU) | |
786 | && | |
787 | ( opcode2->op->unit == EITHER_BUT_PREFER_MU | |
788 | || opcode2->op->unit == MU))) | |
9b1168d6 MH |
789 | { |
790 | /* parallel */ | |
343b2ab8 | 791 | exec_type = EXEC_PARALLEL; |
973e995d NC |
792 | |
793 | if (opcode1->op->unit == IU | |
794 | || opcode2->op->unit == MU | |
795 | || opcode2->op->unit == EITHER_BUT_PREFER_MU) | |
9b1168d6 MH |
796 | insn = FM00 | (insn2 << 32) | insn1; |
797 | else | |
798 | { | |
799 | insn = FM00 | (insn1 << 32) | insn2; | |
800 | fx = fx->next; | |
801 | } | |
802 | } | |
a173c5db | 803 | else if (opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR) |
644a2654 | 804 | && ((opcode1->op->flags_used & FLAG_DELAY) == 0) |
a173c5db NC |
805 | && ((opcode1->ecc == ECC_AL) || ! Optimizing)) |
806 | { | |
644a2654 NC |
807 | /* We must emit (non-delayed) branch type instructions |
808 | on their own with nothing in the right container. */ | |
a173c5db NC |
809 | write_1_short (opcode1, insn1, fx->next, false); |
810 | return 1; | |
811 | } | |
973e995d NC |
812 | else if (opcode1->op->unit == IU |
813 | || (opcode1->op->unit == EITHER | |
814 | && opcode2->op->unit == EITHER_BUT_PREFER_MU)) | |
9b1168d6 MH |
815 | { |
816 | /* reverse sequential */ | |
817 | insn = FM10 | (insn2 << 32) | insn1; | |
343b2ab8 | 818 | exec_type = EXEC_REVSEQ; |
9b1168d6 MH |
819 | } |
820 | else | |
821 | { | |
822 | /* sequential */ | |
823 | insn = FM01 | (insn1 << 32) | insn2; | |
343b2ab8 MM |
824 | fx = fx->next; |
825 | exec_type = EXEC_SEQ; | |
9b1168d6 MH |
826 | } |
827 | break; | |
343b2ab8 MM |
828 | |
829 | case EXEC_PARALLEL: /* parallel */ | |
ccc12f73 | 830 | flag_explicitly_parallel = flag_xp_state; |
343b2ab8 | 831 | if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) |
633f5016 | 832 | as_bad (_("Instructions may not be executed in parallel")); |
343b2ab8 | 833 | else if (opcode1->op->unit == IU) |
9b1168d6 MH |
834 | { |
835 | if (opcode2->op->unit == IU) | |
633f5016 | 836 | as_bad (_("Two IU instructions may not be executed in parallel")); |
48401fcf | 837 | as_warn (_("Swapping instruction order")); |
9b1168d6 MH |
838 | insn = FM00 | (insn2 << 32) | insn1; |
839 | } | |
840 | else if (opcode2->op->unit == MU) | |
841 | { | |
842 | if (opcode1->op->unit == MU) | |
633f5016 | 843 | as_bad (_("Two MU instructions may not be executed in parallel")); |
973e995d | 844 | else if (opcode1->op->unit == EITHER_BUT_PREFER_MU) |
a173c5db | 845 | as_warn (_("Executing %s in IU may not work"), opcode1->op->name); |
48401fcf | 846 | as_warn (_("Swapping instruction order")); |
9b1168d6 MH |
847 | insn = FM00 | (insn2 << 32) | insn1; |
848 | } | |
849 | else | |
850 | { | |
973e995d | 851 | if (opcode2->op->unit == EITHER_BUT_PREFER_MU) |
a173c5db | 852 | as_warn (_("Executing %s in IU may not work"), opcode2->op->name); |
973e995d | 853 | |
9b1168d6 MH |
854 | insn = FM00 | (insn1 << 32) | insn2; |
855 | fx = fx->next; | |
856 | } | |
ccc12f73 | 857 | flag_explicitly_parallel = 0; |
9b1168d6 | 858 | break; |
343b2ab8 MM |
859 | |
860 | case EXEC_SEQ: /* sequential */ | |
9b1168d6 | 861 | if (opcode1->op->unit == IU) |
633f5016 | 862 | as_bad (_("IU instruction may not be in the left container")); |
e21cafde | 863 | if (prev_left_kills_right_p) |
633f5016 | 864 | as_bad (_("special left instruction `%s' kills instruction " |
e21cafde FCE |
865 | "`%s' in right container"), |
866 | opcode1->op->name, opcode2->op->name); | |
973e995d NC |
867 | if (opcode2->op->unit == EITHER_BUT_PREFER_MU) |
868 | as_warn (_("Executing %s in IU may not work"), opcode2->op->name); | |
9b1168d6 MH |
869 | insn = FM01 | (insn1 << 32) | insn2; |
870 | fx = fx->next; | |
871 | break; | |
343b2ab8 MM |
872 | |
873 | case EXEC_REVSEQ: /* reverse sequential */ | |
9b1168d6 | 874 | if (opcode2->op->unit == MU) |
633f5016 | 875 | as_bad (_("MU instruction may not be in the right container")); |
973e995d NC |
876 | if (opcode2->op->unit == EITHER_BUT_PREFER_MU) |
877 | as_warn (_("Executing %s in IU may not work"), opcode2->op->name); | |
9b1168d6 MH |
878 | insn = FM10 | (insn1 << 32) | insn2; |
879 | fx = fx->next; | |
880 | break; | |
343b2ab8 | 881 | |
9b1168d6 | 882 | default: |
7a0f469b | 883 | as_fatal (_("unknown execution type passed to write_2_short()")); |
9b1168d6 MH |
884 | } |
885 | ||
a173c5db | 886 | /* printf ("writing out %llx\n",insn); */ |
7a0f469b | 887 | f = frag_more (8); |
9b1168d6 MH |
888 | d30v_number_to_chars (f, insn, 8); |
889 | ||
343b2ab8 MM |
890 | /* If the previous instruction was a 32-bit multiply but it is put into a |
891 | parallel container, mark the current instruction as being a 32-bit | |
892 | multiply. */ | |
893 | if (prev_mul32_p && exec_type == EXEC_PARALLEL) | |
894 | cur_mul32_p = 1; | |
895 | ||
9b1168d6 MH |
896 | for (j=0; j<2; j++) |
897 | { | |
898 | for (i=0; i < fx->fc; i++) | |
899 | { | |
900 | if (fx->fix[i].reloc) | |
901 | { | |
902 | where = (f - frag_now->fr_literal) + 4*j; | |
903 | ||
9b1168d6 MH |
904 | fix_new_exp (frag_now, |
905 | where, | |
906 | fx->fix[i].size, | |
907 | &(fx->fix[i].exp), | |
908 | fx->fix[i].pcrel, | |
909 | fx->fix[i].reloc); | |
910 | } | |
911 | } | |
973e995d | 912 | |
9b1168d6 MH |
913 | fx->fc = 0; |
914 | fx = fx->next; | |
915 | } | |
973e995d NC |
916 | |
917 | return 0; | |
9b1168d6 MH |
918 | } |
919 | ||
920 | ||
921 | /* Check 2 instructions and determine if they can be safely */ | |
922 | /* executed in parallel. Returns 1 if they can be. */ | |
923 | static int | |
924 | parallel_ok (op1, insn1, op2, insn2, exec_type) | |
925 | struct d30v_insn *op1, *op2; | |
926 | unsigned long insn1, insn2; | |
343b2ab8 | 927 | exec_type_enum exec_type; |
9b1168d6 | 928 | { |
e0882f34 MM |
929 | int i, j, shift, regno, bits, ecc; |
930 | unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2; | |
343b2ab8 | 931 | unsigned long ins, mod_reg[2][3], used_reg[2][3], flag_reg[2]; |
1b524697 MH |
932 | struct d30v_format *f; |
933 | struct d30v_opcode *op; | |
934 | ||
935 | /* section 4.3: both instructions must not be IU or MU only */ | |
936 | if ((op1->op->unit == IU && op2->op->unit == IU) | |
937 | || (op1->op->unit == MU && op2->op->unit == MU)) | |
9b1168d6 MH |
938 | return 0; |
939 | ||
343b2ab8 MM |
940 | /* first instruction must not be a jump to safely optimize, unless this |
941 | is an explicit parallel operation. */ | |
942 | if (exec_type != EXEC_PARALLEL | |
943 | && (op1->op->flags_used & (FLAG_JMP | FLAG_JSR))) | |
e0882f34 MM |
944 | return 0; |
945 | ||
946 | /* If one instruction is /TX or /XT and the other is /FX or /XF respectively, | |
947 | then it is safe to allow the two to be done as parallel ops, since only | |
948 | one will ever be executed at a time. */ | |
949 | if ((op1->ecc == ECC_TX && op2->ecc == ECC_FX) | |
950 | || (op1->ecc == ECC_FX && op2->ecc == ECC_TX) | |
951 | || (op1->ecc == ECC_XT && op2->ecc == ECC_XF) | |
952 | || (op1->ecc == ECC_XF && op2->ecc == ECC_XT)) | |
953 | return 1; | |
954 | ||
955 | /* [0] r0-r31 | |
956 | [1] r32-r63 | |
957 | [2] a0, a1, flag registers */ | |
9b1168d6 | 958 | |
1b524697 | 959 | for (j = 0; j < 2; j++) |
9b1168d6 MH |
960 | { |
961 | if (j == 0) | |
962 | { | |
1b524697 MH |
963 | f = op1->form; |
964 | op = op1->op; | |
e0882f34 | 965 | ecc = op1->ecc; |
9b1168d6 MH |
966 | ins = insn1; |
967 | } | |
968 | else | |
969 | { | |
1b524697 MH |
970 | f = op2->form; |
971 | op = op2->op; | |
e0882f34 | 972 | ecc = op2->ecc; |
9b1168d6 MH |
973 | ins = insn2; |
974 | } | |
343b2ab8 | 975 | flag_reg[j] = 0; |
1b524697 | 976 | mod_reg[j][0] = mod_reg[j][1] = 0; |
e0882f34 | 977 | mod_reg[j][2] = (op->flags_set & FLAG_ALL); |
1b524697 | 978 | used_reg[j][0] = used_reg[j][1] = 0; |
e0882f34 MM |
979 | used_reg[j][2] = (op->flags_used & FLAG_ALL); |
980 | ||
981 | /* BSR/JSR always sets R62 */ | |
982 | if (op->flags_used & FLAG_JSR) | |
983 | mod_reg[j][1] = (1L << (62-32)); | |
984 | ||
985 | /* conditional execution affects the flags_used */ | |
986 | switch (ecc) | |
987 | { | |
988 | case ECC_TX: | |
989 | case ECC_FX: | |
343b2ab8 | 990 | used_reg[j][2] |= flag_reg[j] = FLAG_0; |
e0882f34 MM |
991 | break; |
992 | ||
993 | case ECC_XT: | |
994 | case ECC_XF: | |
343b2ab8 | 995 | used_reg[j][2] |= flag_reg[j] = FLAG_1; |
e0882f34 MM |
996 | break; |
997 | ||
998 | case ECC_TT: | |
999 | case ECC_TF: | |
343b2ab8 | 1000 | used_reg[j][2] |= flag_reg[j] = (FLAG_0 | FLAG_1); |
e0882f34 MM |
1001 | break; |
1002 | } | |
1003 | ||
1b524697 | 1004 | for (i = 0; f->operands[i]; i++) |
9b1168d6 | 1005 | { |
1b524697 MH |
1006 | flags = d30v_operand_table[f->operands[i]].flags; |
1007 | shift = 12 - d30v_operand_table[f->operands[i]].position; | |
1008 | bits = d30v_operand_table[f->operands[i]].bits; | |
1009 | if (bits == 32) | |
1010 | mask = 0xffffffff; | |
1011 | else | |
1012 | mask = 0x7FFFFFFF >> (31 - bits); | |
e0882f34 MM |
1013 | |
1014 | if ((flags & OPERAND_PLUS) || (flags & OPERAND_MINUS)) | |
1015 | { | |
1016 | /* this is a post-increment or post-decrement */ | |
1017 | /* the previous register needs to be marked as modified */ | |
1018 | ||
1019 | shift = 12 - d30v_operand_table[f->operands[i-1]].position; | |
1020 | regno = (ins >> shift) & 0x3f; | |
1021 | if (regno >= 32) | |
1022 | mod_reg[j][1] |= 1L << (regno - 32); | |
1023 | else | |
1024 | mod_reg[j][0] |= 1L << regno; | |
1025 | } | |
1026 | else if (flags & OPERAND_REG) | |
9b1168d6 MH |
1027 | { |
1028 | regno = (ins >> shift) & mask; | |
e0882f34 MM |
1029 | /* the memory write functions don't have a destination register */ |
1030 | if ((flags & OPERAND_DEST) && !(op->flags_set & FLAG_MEM)) | |
9b1168d6 | 1031 | { |
e0882f34 | 1032 | /* MODIFIED registers and flags */ |
1b524697 | 1033 | if (flags & OPERAND_ACC) |
e0882f34 MM |
1034 | { |
1035 | if (regno == 0) | |
1036 | mod_reg[j][2] |= FLAG_A0; | |
1037 | else if (regno == 1) | |
1038 | mod_reg[j][2] |= FLAG_A1; | |
1039 | else | |
1040 | abort (); | |
1041 | } | |
1b524697 | 1042 | else if (flags & OPERAND_FLAG) |
e0882f34 | 1043 | mod_reg[j][2] |= 1L << regno; |
1b524697 MH |
1044 | else if (!(flags & OPERAND_CONTROL)) |
1045 | { | |
e0882f34 MM |
1046 | int r, z; |
1047 | ||
1048 | /* need to check if there are two destination */ | |
1049 | /* registers, for example ld2w */ | |
1050 | if (flags & OPERAND_2REG) | |
1051 | z = 1; | |
1b524697 | 1052 | else |
e0882f34 MM |
1053 | z = 0; |
1054 | ||
1055 | for (r = regno; r <= regno + z; r++) | |
1056 | { | |
1057 | if (r >= 32) | |
1058 | mod_reg[j][1] |= 1L << (r - 32); | |
1059 | else | |
1060 | mod_reg[j][0] |= 1L << r; | |
1061 | } | |
1b524697 | 1062 | } |
9b1168d6 MH |
1063 | } |
1064 | else | |
1065 | { | |
e0882f34 | 1066 | /* USED, but not modified registers and flags */ |
1b524697 | 1067 | if (flags & OPERAND_ACC) |
e0882f34 MM |
1068 | { |
1069 | if (regno == 0) | |
1070 | used_reg[j][2] |= FLAG_A0; | |
1071 | else if (regno == 1) | |
1072 | used_reg[j][2] |= FLAG_A1; | |
1073 | else | |
1074 | abort (); | |
1075 | } | |
1b524697 | 1076 | else if (flags & OPERAND_FLAG) |
e0882f34 | 1077 | used_reg[j][2] |= 1L << regno; |
1b524697 MH |
1078 | else if (!(flags & OPERAND_CONTROL)) |
1079 | { | |
e0882f34 MM |
1080 | int r, z; |
1081 | ||
1082 | /* need to check if there are two source */ | |
1083 | /* registers, for example st2w */ | |
1084 | if (flags & OPERAND_2REG) | |
1085 | z = 1; | |
1b524697 | 1086 | else |
e0882f34 MM |
1087 | z = 0; |
1088 | ||
1089 | for (r = regno; r <= regno + z; r++) | |
1090 | { | |
1091 | if (r >= 32) | |
1092 | used_reg[j][1] |= 1L << (r - 32); | |
1093 | else | |
1094 | used_reg[j][0] |= 1L << r; | |
1095 | } | |
1b524697 | 1096 | } |
9b1168d6 MH |
1097 | } |
1098 | } | |
1099 | } | |
9b1168d6 | 1100 | } |
633f5016 | 1101 | |
e0882f34 MM |
1102 | flags_set1 = op1->op->flags_set; |
1103 | flags_set2 = op2->op->flags_set; | |
1104 | flags_used1 = op1->op->flags_used; | |
1105 | flags_used2 = op2->op->flags_used; | |
1106 | ||
1107 | /* ST2W/ST4HB combined with ADDppp/SUBppp is illegal. */ | |
1108 | if (((flags_set1 & (FLAG_MEM | FLAG_2WORD)) == (FLAG_MEM | FLAG_2WORD) | |
1109 | && (flags_used2 & FLAG_ADDSUBppp) != 0) | |
1110 | || ((flags_set2 & (FLAG_MEM | FLAG_2WORD)) == (FLAG_MEM | FLAG_2WORD) | |
1111 | && (flags_used1 & FLAG_ADDSUBppp) != 0)) | |
1112 | return 0; | |
1113 | ||
1114 | /* Load instruction combined with half-word multiply is illegal. */ | |
1115 | if (((flags_used1 & FLAG_MEM) != 0 && (flags_used2 & FLAG_MUL16)) | |
1116 | || ((flags_used2 & FLAG_MEM) != 0 && (flags_used1 & FLAG_MUL16))) | |
1117 | return 0; | |
1118 | ||
1119 | /* Specifically allow add || add by removing carry, overflow bits dependency. | |
1120 | This is safe, even if an addc follows since the IU takes the argument in | |
1121 | the right container, and it writes its results last. | |
1122 | However, don't paralellize add followed by addc or sub followed by | |
1123 | subb. */ | |
1124 | ||
1125 | if (mod_reg[0][2] == FLAG_CVVA && mod_reg[1][2] == FLAG_CVVA | |
343b2ab8 MM |
1126 | && (used_reg[0][2] & ~flag_reg[0]) == 0 |
1127 | && (used_reg[1][2] & ~flag_reg[1]) == 0 | |
e0882f34 MM |
1128 | && op1->op->unit == EITHER && op2->op->unit == EITHER) |
1129 | { | |
1130 | mod_reg[0][2] = mod_reg[1][2] = 0; | |
1131 | } | |
1132 | ||
7a0f469b | 1133 | for (j = 0; j < 3; j++) |
e0882f34 MM |
1134 | { |
1135 | /* If the second instruction depends on the first, we obviously | |
1136 | cannot parallelize. Note, the mod flag implies use, so | |
1137 | check that as well. */ | |
ccc12f73 FF |
1138 | /* If flag_explicitly_parallel is set, then the case of the |
1139 | second instruction using a register the first instruction | |
1140 | modifies is assumed to be okay; we trust the human. We | |
1141 | don't trust the human if both instructions modify the same | |
1142 | register but we do trust the human if they modify the same | |
1143 | flags. */ | |
633f5016 NC |
1144 | /* We have now been requested not to trust the human if the |
1145 | instructions modify the same flag registers either. */ | |
ccc12f73 FF |
1146 | if (flag_explicitly_parallel) |
1147 | { | |
633f5016 | 1148 | if ((mod_reg[0][j] & mod_reg[1][j]) != 0) |
ccc12f73 FF |
1149 | return 0; |
1150 | } | |
1151 | else | |
1152 | if ((mod_reg[0][j] & (mod_reg[1][j] | used_reg[1][j])) != 0) | |
1153 | return 0; | |
e0882f34 MM |
1154 | } |
1155 | ||
1b524697 | 1156 | return 1; |
9b1168d6 MH |
1157 | } |
1158 | ||
1159 | ||
9b1168d6 MH |
1160 | /* This is the main entry point for the machine-dependent assembler. str points to a |
1161 | machine-dependent instruction. This function is supposed to emit the frags/bytes | |
1162 | it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing | |
343b2ab8 | 1163 | and leaves the difficult stuff to do_assemble(). */ |
9b1168d6 MH |
1164 | |
1165 | static long long prev_insn = -1; | |
1166 | static struct d30v_insn prev_opcode; | |
1167 | static subsegT prev_subseg; | |
1168 | static segT prev_seg = 0; | |
1169 | ||
1170 | void | |
1171 | md_assemble (str) | |
1172 | char *str; | |
1173 | { | |
1174 | struct d30v_insn opcode; | |
1175 | long long insn; | |
343b2ab8 MM |
1176 | exec_type_enum extype = EXEC_UNKNOWN; /* execution type; parallel, etc */ |
1177 | static exec_type_enum etype = EXEC_UNKNOWN; /* saved extype. used for multiline instructions */ | |
9b1168d6 MH |
1178 | char *str2; |
1179 | ||
7d515759 RH |
1180 | if ((prev_insn != -1) && prev_seg |
1181 | && ((prev_seg != now_seg) || (prev_subseg != now_subseg))) | |
aa7bf2a8 | 1182 | d30v_cleanup (false); |
e0882f34 | 1183 | |
7d515759 RH |
1184 | if (d30v_current_align < 3) |
1185 | d30v_align (3, NULL, d30v_last_label); | |
1186 | else if (d30v_current_align > 3) | |
1187 | d30v_current_align = 3; | |
1188 | d30v_last_label = NULL; | |
1189 | ||
ccc12f73 FF |
1190 | flag_explicitly_parallel = 0; |
1191 | flag_xp_state = 0; | |
343b2ab8 | 1192 | if (etype == EXEC_UNKNOWN) |
9b1168d6 MH |
1193 | { |
1194 | /* look for the special multiple instruction separators */ | |
1195 | str2 = strstr (str, "||"); | |
1196 | if (str2) | |
ccc12f73 FF |
1197 | { |
1198 | extype = EXEC_PARALLEL; | |
1199 | flag_xp_state = 1; | |
1200 | } | |
9b1168d6 MH |
1201 | else |
1202 | { | |
1203 | str2 = strstr (str, "->"); | |
1204 | if (str2) | |
343b2ab8 | 1205 | extype = EXEC_SEQ; |
9b1168d6 MH |
1206 | else |
1207 | { | |
1208 | str2 = strstr (str, "<-"); | |
1209 | if (str2) | |
343b2ab8 | 1210 | extype = EXEC_REVSEQ; |
9b1168d6 MH |
1211 | } |
1212 | } | |
1213 | /* str2 points to the separator, if one */ | |
1214 | if (str2) | |
1215 | { | |
1216 | *str2 = 0; | |
1217 | ||
1218 | /* if two instructions are present and we already have one saved | |
1219 | then first write it out */ | |
aa7bf2a8 | 1220 | d30v_cleanup (false); |
9b1168d6 | 1221 | |
973e995d | 1222 | /* Assemble first instruction and save it. */ |
7a0f469b | 1223 | prev_insn = do_assemble (str, &prev_opcode, 1, 0); |
9b1168d6 | 1224 | if (prev_insn == -1) |
633f5016 | 1225 | as_bad (_("Cannot assemble instruction")); |
e0882f34 | 1226 | if (prev_opcode.form->form >= LONG) |
633f5016 | 1227 | as_bad (_("First opcode is long. Unable to mix instructions as specified.")); |
9b1168d6 MH |
1228 | fixups = fixups->next; |
1229 | str = str2 + 2; | |
bc67c823 NC |
1230 | prev_seg = now_seg; |
1231 | prev_subseg = now_subseg; | |
9b1168d6 MH |
1232 | } |
1233 | } | |
1234 | ||
daaef8f8 | 1235 | insn = do_assemble (str, &opcode, |
7a0f469b NC |
1236 | (extype != EXEC_UNKNOWN || etype != EXEC_UNKNOWN), |
1237 | extype == EXEC_PARALLEL); | |
9b1168d6 MH |
1238 | if (insn == -1) |
1239 | { | |
daaef8f8 | 1240 | if (extype != EXEC_UNKNOWN) |
9b1168d6 MH |
1241 | { |
1242 | etype = extype; | |
1243 | return; | |
1244 | } | |
633f5016 | 1245 | as_bad (_("Cannot assemble instruction")); |
9b1168d6 MH |
1246 | } |
1247 | ||
daaef8f8 | 1248 | if (etype != EXEC_UNKNOWN) |
9b1168d6 MH |
1249 | { |
1250 | extype = etype; | |
daaef8f8 | 1251 | etype = EXEC_UNKNOWN; |
9b1168d6 MH |
1252 | } |
1253 | ||
343b2ab8 MM |
1254 | /* Word multiply instructions must not be followed by either a load or a |
1255 | 16-bit multiply instruction in the next cycle. */ | |
7a0f469b NC |
1256 | if ( (extype != EXEC_REVSEQ) |
1257 | && prev_mul32_p | |
1258 | && (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16))) | |
343b2ab8 MM |
1259 | { |
1260 | /* However, load and multiply should able to be combined in a parallel | |
1261 | operation, so check for that first. */ | |
343b2ab8 MM |
1262 | if (prev_insn != -1 |
1263 | && (opcode.op->flags_used & FLAG_MEM) | |
1264 | && opcode.form->form < LONG | |
1265 | && (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN)) | |
1266 | && parallel_ok (&prev_opcode, (long)prev_insn, | |
1267 | &opcode, (long)insn, extype) | |
1268 | && write_2_short (&prev_opcode, (long)prev_insn, | |
1269 | &opcode, (long)insn, extype, fixups) == 0) | |
1270 | { | |
1271 | /* no instructions saved */ | |
1272 | prev_insn = -1; | |
1273 | return; | |
1274 | } | |
343b2ab8 MM |
1275 | else |
1276 | { | |
7a0f469b | 1277 | /* Can't parallelize, flush previous instruction and emit a word of NOPS, |
aa7bf2a8 | 1278 | unless the previous instruction is a NOP, in which case just flush it, |
7a0f469b | 1279 | as this will generate a word of NOPs for us. */ |
343b2ab8 | 1280 | |
7a0f469b | 1281 | if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0)) |
aa7bf2a8 | 1282 | d30v_cleanup (false); |
7a0f469b NC |
1283 | else |
1284 | { | |
1285 | char * f; | |
1286 | ||
aa7bf2a8 NC |
1287 | if (prev_insn != -1) |
1288 | d30v_cleanup (true); | |
1289 | else | |
7a0f469b | 1290 | { |
aa7bf2a8 NC |
1291 | f = frag_more (8); |
1292 | d30v_number_to_chars (f, NOP2, 8); | |
1293 | ||
1294 | if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY) | |
1295 | { | |
1296 | if (opcode.op->flags_used & FLAG_MEM) | |
1297 | as_warn (_("word of NOPs added between word multiply and load")); | |
1298 | else | |
1299 | as_warn (_("word of NOPs added between word multiply and 16-bit multiply")); | |
1300 | } | |
7a0f469b NC |
1301 | } |
1302 | } | |
aa7bf2a8 | 1303 | |
7a0f469b NC |
1304 | extype = EXEC_UNKNOWN; |
1305 | } | |
1306 | } | |
1307 | else if ( (extype == EXEC_REVSEQ) | |
1308 | && cur_mul32_p | |
1309 | && (prev_opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16))) | |
1310 | { | |
aa7bf2a8 NC |
1311 | /* Can't parallelize, flush current instruction and add a sequential NOP. */ |
1312 | write_1_short (& opcode, (long) insn, fixups->next->next, true); | |
7a0f469b NC |
1313 | |
1314 | /* Make the previous instruction the current one. */ | |
1315 | extype = EXEC_UNKNOWN; | |
1316 | insn = prev_insn; | |
1317 | now_seg = prev_seg; | |
1318 | now_subseg = prev_subseg; | |
1319 | prev_insn = -1; | |
1320 | cur_mul32_p = prev_mul32_p; | |
1321 | prev_mul32_p = 0; | |
aa7bf2a8 | 1322 | memcpy (&opcode, &prev_opcode, sizeof (prev_opcode)); |
343b2ab8 MM |
1323 | } |
1324 | ||
7a0f469b | 1325 | /* If this is a long instruction, write it and any previous short instruction. */ |
9b1168d6 MH |
1326 | if (opcode.form->form >= LONG) |
1327 | { | |
7a0f469b | 1328 | if (extype != EXEC_UNKNOWN) |
633f5016 | 1329 | as_bad (_("Instruction uses long version, so it cannot be mixed as specified")); |
aa7bf2a8 | 1330 | d30v_cleanup (false); |
973e995d | 1331 | write_long (& opcode, insn, fixups); |
9b1168d6 | 1332 | prev_insn = -1; |
9b1168d6 | 1333 | } |
633f5016 NC |
1334 | else if ((prev_insn != -1) |
1335 | && (write_2_short | |
1336 | (& prev_opcode, (long) prev_insn, & opcode, | |
1337 | (long) insn, extype, fixups) == 0)) | |
9b1168d6 | 1338 | { |
7a0f469b | 1339 | /* No instructions saved. */ |
9b1168d6 MH |
1340 | prev_insn = -1; |
1341 | } | |
1342 | else | |
1343 | { | |
7a0f469b | 1344 | if (extype != EXEC_UNKNOWN) |
633f5016 | 1345 | as_bad (_("Unable to mix instructions as specified")); |
7a0f469b NC |
1346 | |
1347 | /* Save off last instruction so it may be packed on next pass. */ | |
1348 | memcpy (&prev_opcode, &opcode, sizeof (prev_opcode)); | |
9b1168d6 MH |
1349 | prev_insn = insn; |
1350 | prev_seg = now_seg; | |
1351 | prev_subseg = now_subseg; | |
1352 | fixups = fixups->next; | |
973e995d | 1353 | prev_mul32_p = cur_mul32_p; |
9b1168d6 MH |
1354 | } |
1355 | } | |
1356 | ||
1357 | ||
1358 | /* do_assemble assembles a single instruction and returns an opcode */ | |
1359 | /* it returns -1 (an invalid opcode) on error */ | |
1360 | ||
1361 | static long long | |
7a0f469b | 1362 | do_assemble (str, opcode, shortp, is_parallel) |
9b1168d6 MH |
1363 | char *str; |
1364 | struct d30v_insn *opcode; | |
daaef8f8 | 1365 | int shortp; |
7a0f469b | 1366 | int is_parallel; |
9b1168d6 MH |
1367 | { |
1368 | unsigned char *op_start, *save; | |
1369 | unsigned char *op_end; | |
1370 | char name[20]; | |
daaef8f8 | 1371 | int cmp_hack, nlen = 0, fsize = (shortp ? FORCE_SHORT : 0); |
9b1168d6 MH |
1372 | expressionS myops[6]; |
1373 | long long insn; | |
1374 | ||
9b1168d6 MH |
1375 | /* Drop leading whitespace */ |
1376 | while (*str == ' ') | |
1377 | str++; | |
1378 | ||
1379 | /* find the opcode end */ | |
1380 | for (op_start = op_end = (unsigned char *) (str); | |
1381 | *op_end | |
1382 | && nlen < 20 | |
1383 | && *op_end != '/' | |
1384 | && !is_end_of_line[*op_end] && *op_end != ' '; | |
1385 | op_end++) | |
1386 | { | |
7a0f469b | 1387 | name[nlen] = tolower (op_start[nlen]); |
9b1168d6 MH |
1388 | nlen++; |
1389 | } | |
1390 | ||
1391 | if (nlen == 0) | |
633f5016 | 1392 | return -1; |
9b1168d6 MH |
1393 | |
1394 | name[nlen] = 0; | |
1395 | ||
1396 | /* if there is an execution condition code, handle it */ | |
1397 | if (*op_end == '/') | |
1398 | { | |
1399 | int i = 0; | |
973e995d | 1400 | while ( (i < ECC_MAX) && strncasecmp (d30v_ecc_names[i], op_end + 1, 2)) |
9b1168d6 MH |
1401 | i++; |
1402 | ||
1403 | if (i == ECC_MAX) | |
1404 | { | |
1405 | char tmp[4]; | |
973e995d | 1406 | strncpy (tmp, op_end + 1, 2); |
9b1168d6 | 1407 | tmp[2] = 0; |
633f5016 | 1408 | as_bad (_("unknown condition code: %s"),tmp); |
9b1168d6 MH |
1409 | return -1; |
1410 | } | |
633f5016 | 1411 | /* printf ("condition code=%d\n",i); */ |
9b1168d6 MH |
1412 | opcode->ecc = i; |
1413 | op_end += 3; | |
1414 | } | |
1415 | else | |
1416 | opcode->ecc = ECC_AL; | |
1417 | ||
1418 | ||
1419 | /* CMP and CMPU change their name based on condition codes */ | |
973e995d | 1420 | if (!strncmp (name, "cmp", 3)) |
9b1168d6 MH |
1421 | { |
1422 | int p,i; | |
1423 | char **str = (char **)d30v_cc_names; | |
1424 | if (name[3] == 'u') | |
1425 | p = 4; | |
1426 | else | |
1427 | p = 3; | |
1428 | ||
973e995d | 1429 | for (i=1; *str && strncmp (*str, & name[p], 2); i++, str++) |
9b1168d6 MH |
1430 | ; |
1431 | ||
e0882f34 MM |
1432 | /* cmpu only supports some condition codes */ |
1433 | if (p == 4) | |
1434 | { | |
1435 | if (i < 3 || i > 6) | |
1436 | { | |
1437 | name[p+2]=0; | |
633f5016 | 1438 | as_bad (_("cmpu doesn't support condition code %s"),&name[p]); |
e0882f34 MM |
1439 | } |
1440 | } | |
1441 | ||
9b1168d6 MH |
1442 | if (!*str) |
1443 | { | |
1444 | name[p+2]=0; | |
633f5016 | 1445 | as_bad (_("unknown condition code: %s"),&name[p]); |
9b1168d6 MH |
1446 | } |
1447 | ||
1448 | cmp_hack = i; | |
1449 | name[p] = 0; | |
1450 | } | |
1451 | else | |
1452 | cmp_hack = 0; | |
1453 | ||
1454 | /* printf("cmp_hack=%d\n",cmp_hack); */ | |
1455 | ||
e0882f34 MM |
1456 | /* need to look for .s or .l */ |
1457 | if (name[nlen-2] == '.') | |
1458 | { | |
1459 | switch (name[nlen-1]) | |
1460 | { | |
1461 | case 's': | |
1462 | fsize = FORCE_SHORT; | |
1463 | break; | |
1464 | case 'l': | |
1465 | fsize = FORCE_LONG; | |
ccc12f73 | 1466 | break; |
e0882f34 MM |
1467 | } |
1468 | name[nlen-2] = 0; | |
1469 | } | |
1470 | ||
9b1168d6 MH |
1471 | /* find the first opcode with the proper name */ |
1472 | opcode->op = (struct d30v_opcode *)hash_find (d30v_hash, name); | |
1473 | if (opcode->op == NULL) | |
633f5016 | 1474 | as_bad (_("unknown opcode: %s"),name); |
9b1168d6 MH |
1475 | |
1476 | save = input_line_pointer; | |
1477 | input_line_pointer = op_end; | |
e0882f34 | 1478 | while (!(opcode->form = find_format (opcode->op, myops, fsize, cmp_hack))) |
9b1168d6 MH |
1479 | { |
1480 | opcode->op++; | |
973e995d | 1481 | if (strcmp (opcode->op->name, name)) |
633f5016 | 1482 | as_bad (_("operands for opcode `%s' do not match any valid format"), name); |
9b1168d6 MH |
1483 | } |
1484 | input_line_pointer = save; | |
1485 | ||
1486 | insn = build_insn (opcode, myops); | |
343b2ab8 MM |
1487 | |
1488 | /* Propigate multiply status */ | |
1489 | if (insn != -1) | |
1490 | { | |
7a0f469b NC |
1491 | if (is_parallel && prev_mul32_p) |
1492 | cur_mul32_p = 1; | |
1493 | else | |
1494 | { | |
1495 | prev_mul32_p = cur_mul32_p; | |
1496 | cur_mul32_p = (opcode->op->flags_used & FLAG_MUL32) != 0; | |
1497 | } | |
343b2ab8 MM |
1498 | } |
1499 | ||
e21cafde FCE |
1500 | /* Propagate left_kills_right status */ |
1501 | if (insn != -1) | |
1502 | { | |
1503 | prev_left_kills_right_p = cur_left_kills_right_p; | |
1504 | ||
1505 | if (opcode->op->flags_set & FLAG_LKR) | |
1506 | { | |
1507 | cur_left_kills_right_p = 1; | |
1508 | ||
1509 | if (strcmp (opcode->op->name, "mvtsys") == 0) | |
1510 | { | |
1511 | /* Left kills right for only mvtsys only for PSW/PSWH/PSWL/flags target. */ | |
1512 | if ((myops[0].X_op == O_register) && | |
1513 | ((myops[0].X_add_number == OPERAND_CONTROL) || /* psw */ | |
1514 | (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+2) || /* pswh */ | |
1515 | (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+1) || /* pswl */ | |
1516 | (myops[0].X_add_number == OPERAND_FLAG+0) || /* f0 */ | |
1517 | (myops[0].X_add_number == OPERAND_FLAG+1) || /* f1 */ | |
1518 | (myops[0].X_add_number == OPERAND_FLAG+2) || /* f2 */ | |
1519 | (myops[0].X_add_number == OPERAND_FLAG+3) || /* f3 */ | |
1520 | (myops[0].X_add_number == OPERAND_FLAG+4) || /* f4 */ | |
1521 | (myops[0].X_add_number == OPERAND_FLAG+5) || /* f5 */ | |
1522 | (myops[0].X_add_number == OPERAND_FLAG+6) || /* f6 */ | |
1523 | (myops[0].X_add_number == OPERAND_FLAG+7))) /* f7 */ | |
1524 | { | |
1525 | cur_left_kills_right_p = 1; | |
1526 | } | |
1527 | else | |
1528 | { | |
1529 | /* Other mvtsys target registers don't kill right instruction. */ | |
1530 | cur_left_kills_right_p = 0; | |
1531 | } | |
1532 | } /* mvtsys */ | |
1533 | } | |
1534 | else | |
1535 | cur_left_kills_right_p = 0; | |
1536 | } | |
1537 | ||
1538 | ||
973e995d | 1539 | return insn; |
9b1168d6 MH |
1540 | } |
1541 | ||
1542 | ||
7d515759 RH |
1543 | /* find_format() gets a pointer to an entry in the format table. |
1544 | It must look at all formats for an opcode and use the operands | |
1545 | to choose the correct one. Returns NULL on error. */ | |
9b1168d6 MH |
1546 | |
1547 | static struct d30v_format * | |
e0882f34 | 1548 | find_format (opcode, myops, fsize, cmp_hack) |
9b1168d6 MH |
1549 | struct d30v_opcode *opcode; |
1550 | expressionS myops[]; | |
e0882f34 | 1551 | int fsize; |
9b1168d6 MH |
1552 | int cmp_hack; |
1553 | { | |
1554 | int numops, match, index, i=0, j, k; | |
1555 | struct d30v_format *fm; | |
9b1168d6 | 1556 | |
7d515759 | 1557 | /* Get all the operands and save them as expressions. */ |
9b1168d6 MH |
1558 | numops = get_operands (myops, cmp_hack); |
1559 | ||
343b2ab8 | 1560 | while ((index = opcode->format[i++]) != 0) |
9b1168d6 | 1561 | { |
7d515759 | 1562 | if (fsize == FORCE_SHORT && index >= LONG) |
e0882f34 MM |
1563 | continue; |
1564 | ||
7d515759 | 1565 | if (fsize == FORCE_LONG && index < LONG) |
e0882f34 MM |
1566 | continue; |
1567 | ||
9b1168d6 MH |
1568 | fm = (struct d30v_format *)&d30v_format_table[index]; |
1569 | k = index; | |
1570 | while (fm->form == index) | |
1571 | { | |
1572 | match = 1; | |
7d515759 | 1573 | /* Now check the operands for compatibility. */ |
9b1168d6 MH |
1574 | for (j = 0; match && fm->operands[j]; j++) |
1575 | { | |
1576 | int flags = d30v_operand_table[fm->operands[j]].flags; | |
7d515759 | 1577 | int bits = d30v_operand_table[fm->operands[j]].bits; |
9b1168d6 MH |
1578 | int X_op = myops[j].X_op; |
1579 | int num = myops[j].X_add_number; | |
1580 | ||
7d515759 | 1581 | if (flags & OPERAND_SPECIAL) |
9b1168d6 | 1582 | break; |
7d515759 | 1583 | else if (X_op == O_illegal) |
9b1168d6 MH |
1584 | match = 0; |
1585 | else if (flags & OPERAND_REG) | |
1586 | { | |
7d515759 | 1587 | if (X_op != O_register |
343b2ab8 | 1588 | || ((flags & OPERAND_ACC) && !(num & OPERAND_ACC)) |
aa7bf2a8 | 1589 | || (!(flags & OPERAND_ACC) && (num & OPERAND_ACC)) |
343b2ab8 | 1590 | || ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG)) |
726a3946 | 1591 | || (!(flags & (OPERAND_FLAG | OPERAND_CONTROL)) && (num & OPERAND_FLAG)) |
343b2ab8 MM |
1592 | || ((flags & OPERAND_CONTROL) |
1593 | && !(num & (OPERAND_CONTROL | OPERAND_FLAG)))) | |
9b1168d6 MH |
1594 | { |
1595 | match = 0; | |
9b1168d6 MH |
1596 | } |
1597 | } | |
7d515759 RH |
1598 | else if (((flags & OPERAND_MINUS) |
1599 | && (X_op != O_absent || num != OPERAND_MINUS)) | |
1600 | || ((flags & OPERAND_PLUS) | |
1601 | && (X_op != O_absent || num != OPERAND_PLUS)) | |
1602 | || ((flags & OPERAND_ATMINUS) | |
1603 | && (X_op != O_absent || num != OPERAND_ATMINUS)) | |
1604 | || ((flags & OPERAND_ATPAR) | |
1605 | && (X_op != O_absent || num != OPERAND_ATPAR)) | |
1606 | || ((flags & OPERAND_ATSIGN) | |
1607 | && (X_op != O_absent || num != OPERAND_ATSIGN))) | |
1608 | { | |
1609 | match=0; | |
1610 | } | |
1611 | else if (flags & OPERAND_NUM) | |
1612 | { | |
1613 | /* A number can be a constant or symbol expression. */ | |
1614 | ||
aa7bf2a8 NC |
1615 | /* If we have found a register name, but that name also |
1616 | matches a symbol, then re-parse the name as an expression. */ | |
1617 | if (X_op == O_register | |
1618 | && symbol_find ((char *) myops[j].X_op_symbol)) | |
1619 | { | |
1620 | input_line_pointer = (char *) myops[j].X_op_symbol; | |
1621 | expression (& myops[j]); | |
1622 | } | |
1623 | ||
7d515759 RH |
1624 | /* Turn an expression into a symbol for later resolution. */ |
1625 | if (X_op != O_absent && X_op != O_constant | |
1626 | && X_op != O_symbol && X_op != O_register | |
1627 | && X_op != O_big) | |
1628 | { | |
1629 | symbolS *sym = make_expr_symbol (&myops[j]); | |
1630 | myops[j].X_op = X_op = O_symbol; | |
1631 | myops[j].X_add_symbol = sym; | |
1632 | myops[j].X_add_number = num = 0; | |
1633 | } | |
1634 | ||
1635 | if (fm->form >= LONG) | |
1636 | { | |
1637 | /* If we're testing for a LONG format, either fits. */ | |
1638 | if (X_op != O_constant && X_op != O_symbol) | |
1639 | match = 0; | |
1640 | } | |
1641 | else if (fm->form < LONG | |
1642 | && ((fsize == FORCE_SHORT && X_op == O_symbol) | |
1643 | || (fm->form == SHORT_D2 && j == 0))) | |
1644 | match = 1; | |
1645 | /* This is the tricky part. Will the constant or symbol | |
1646 | fit into the space in the current format? */ | |
1647 | else if (X_op == O_constant) | |
1648 | { | |
1649 | if (check_range (num, bits, flags)) | |
1650 | match = 0; | |
1651 | } | |
1652 | else if (X_op == O_symbol | |
7a0f469b NC |
1653 | && S_IS_DEFINED (myops[j].X_add_symbol) |
1654 | && S_GET_SEGMENT (myops[j].X_add_symbol) == now_seg | |
7d515759 RH |
1655 | && opcode->reloc_flag == RELOC_PCREL) |
1656 | { | |
1657 | /* If the symbol is defined, see if the value will fit | |
1658 | into the form we're considering. */ | |
1659 | fragS *f; | |
1660 | long value; | |
1661 | ||
1662 | /* Calculate the current address by running through the | |
1663 | previous frags and adding our current offset. */ | |
1664 | value = 0; | |
1665 | for (f = frchain_now->frch_root; f; f = f->fr_next) | |
1666 | value += f->fr_fix + f->fr_offset; | |
7a0f469b NC |
1667 | value = (S_GET_VALUE (myops[j].X_add_symbol) - value |
1668 | - (obstack_next_free (&frchain_now->frch_obstack) | |
7d515759 RH |
1669 | - frag_now->fr_literal)); |
1670 | if (check_range (value, bits, flags)) | |
1671 | match = 0; | |
1672 | } | |
1673 | else | |
1674 | match = 0; | |
1675 | } | |
9b1168d6 MH |
1676 | } |
1677 | /* printf("through the loop: match=%d\n",match); */ | |
7d515759 RH |
1678 | /* We're only done if the operands matched so far AND there |
1679 | are no more to check. */ | |
633f5016 NC |
1680 | if (match && myops[j].X_op == 0) |
1681 | { | |
1682 | /* Final check - issue a warning if an odd numbered register | |
1683 | is used as the first register in an instruction that reads | |
1684 | or writes 2 registers. */ | |
1685 | ||
1686 | for (j = 0; fm->operands[j]; j++) | |
1687 | if (myops[j].X_op == O_register | |
1688 | && (myops[j].X_add_number & 1) | |
1689 | && (d30v_operand_table[fm->operands[j]].flags & OPERAND_2REG)) | |
1690 | as_warn (\ | |
1691 | _("Odd numbered register used as target of multi-register instruction")); | |
1692 | ||
1693 | return fm; | |
1694 | } | |
9b1168d6 MH |
1695 | fm = (struct d30v_format *)&d30v_format_table[++k]; |
1696 | } | |
1697 | /* printf("trying another format: i=%d\n",i); */ | |
1698 | } | |
1699 | return NULL; | |
1700 | } | |
1701 | ||
1702 | /* if while processing a fixup, a reloc really needs to be created */ | |
1703 | /* then it is done here */ | |
1704 | ||
1705 | arelent * | |
1706 | tc_gen_reloc (seg, fixp) | |
1707 | asection *seg; | |
1708 | fixS *fixp; | |
1709 | { | |
1710 | arelent *reloc; | |
2c268a85 | 1711 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
9b1168d6 MH |
1712 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; |
1713 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1714 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
9b1168d6 MH |
1715 | if (reloc->howto == (reloc_howto_type *) NULL) |
1716 | { | |
1717 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
48401fcf | 1718 | _("reloc %d not supported by object file format"), (int)fixp->fx_r_type); |
9b1168d6 MH |
1719 | return NULL; |
1720 | } | |
1721 | reloc->addend = fixp->fx_addnumber; | |
1722 | return reloc; | |
1723 | } | |
1724 | ||
1725 | int | |
1726 | md_estimate_size_before_relax (fragp, seg) | |
1727 | fragS *fragp; | |
1728 | asection *seg; | |
1729 | { | |
1730 | abort (); | |
1731 | return 0; | |
1732 | } | |
1733 | ||
1734 | long | |
1735 | md_pcrel_from_section (fixp, sec) | |
1736 | fixS *fixp; | |
1737 | segT sec; | |
1738 | { | |
e0882f34 MM |
1739 | if (fixp->fx_addsy != (symbolS *)NULL && (!S_IS_DEFINED (fixp->fx_addsy) || |
1740 | (S_GET_SEGMENT (fixp->fx_addsy) != sec))) | |
9b1168d6 MH |
1741 | return 0; |
1742 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
1743 | } | |
1744 | ||
1745 | int | |
1746 | md_apply_fix3 (fixp, valuep, seg) | |
644a2654 NC |
1747 | fixS * fixp; |
1748 | valueT * valuep; | |
9b1168d6 MH |
1749 | segT seg; |
1750 | { | |
644a2654 | 1751 | char * where; |
9b1168d6 MH |
1752 | unsigned long insn, insn2; |
1753 | long value; | |
633f5016 | 1754 | |
9b1168d6 MH |
1755 | if (fixp->fx_addsy == (symbolS *) NULL) |
1756 | { | |
644a2654 | 1757 | value = * valuep; |
9b1168d6 MH |
1758 | fixp->fx_done = 1; |
1759 | } | |
9b1168d6 | 1760 | else if (fixp->fx_pcrel) |
644a2654 | 1761 | value = * valuep; |
1b524697 | 1762 | else |
9b1168d6 MH |
1763 | { |
1764 | value = fixp->fx_offset; | |
644a2654 | 1765 | |
9b1168d6 MH |
1766 | if (fixp->fx_subsy != (symbolS *) NULL) |
1767 | { | |
e0882f34 | 1768 | if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section) |
9b1168d6 MH |
1769 | value -= S_GET_VALUE (fixp->fx_subsy); |
1770 | else | |
1771 | { | |
1772 | /* We don't actually support subtracting a symbol. */ | |
1b524697 | 1773 | as_bad_where (fixp->fx_file, fixp->fx_line, |
48401fcf | 1774 | _("expression too complex")); |
9b1168d6 MH |
1775 | } |
1776 | } | |
1777 | } | |
1778 | ||
1779 | /* Fetch the instruction, insert the fully resolved operand | |
1780 | value, and stuff the instruction back again. */ | |
1781 | where = fixp->fx_frag->fr_literal + fixp->fx_where; | |
1782 | insn = bfd_getb32 ((unsigned char *) where); | |
1b524697 | 1783 | |
9b1168d6 MH |
1784 | switch (fixp->fx_r_type) |
1785 | { | |
644a2654 NC |
1786 | case BFD_RELOC_8: /* Caused by a bad .byte directive. */ |
1787 | /* Drop trhough. */ | |
d32f7037 | 1788 | |
644a2654 NC |
1789 | case BFD_RELOC_16: /* Caused by a bad .short directive. */ |
1790 | /* Drop through. */ | |
d32f7037 | 1791 | |
644a2654 NC |
1792 | case BFD_RELOC_64: /* Caused by a bad .quad directive. */ |
1793 | { | |
1794 | char * size; | |
1795 | ||
1796 | size = (fixp->fx_r_type == BFD_RELOC_8) ? _("byte") | |
1797 | : (fixp->fx_r_type == BFD_RELOC_16) ? _("short") | |
1798 | : _("quad"); | |
1799 | ||
1800 | if (fixp->fx_addsy == NULL) | |
1801 | as_bad (_("line %d: unable to place address into a %s"), | |
1802 | fixp->fx_line, size); | |
1803 | else | |
1804 | as_bad (_("line %d: unable to place address of symbol '%s' into a %s"), | |
1805 | fixp->fx_line, | |
1806 | S_GET_NAME (fixp->fx_addsy), | |
1807 | size); | |
1808 | break; | |
1809 | } | |
d32f7037 | 1810 | |
9b1168d6 | 1811 | case BFD_RELOC_D30V_6: |
e0882f34 | 1812 | check_size (value, 6, fixp->fx_file, fixp->fx_line); |
9b1168d6 MH |
1813 | insn |= value & 0x3F; |
1814 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1815 | break; | |
343b2ab8 | 1816 | |
e0882f34 MM |
1817 | case BFD_RELOC_D30V_9_PCREL: |
1818 | if (fixp->fx_where & 0x7) | |
1819 | { | |
1820 | if (fixp->fx_done) | |
1821 | value += 4; | |
1822 | else | |
1823 | fixp->fx_r_type = BFD_RELOC_D30V_9_PCREL_R; | |
1824 | } | |
1825 | check_size (value, 9, fixp->fx_file, fixp->fx_line); | |
1826 | insn |= ((value >> 3) & 0x3F) << 12; | |
1827 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1828 | break; | |
343b2ab8 | 1829 | |
9b1168d6 | 1830 | case BFD_RELOC_D30V_15: |
e0882f34 | 1831 | check_size (value, 15, fixp->fx_file, fixp->fx_line); |
9b1168d6 MH |
1832 | insn |= (value >> 3) & 0xFFF; |
1833 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1834 | break; | |
343b2ab8 | 1835 | |
9b1168d6 | 1836 | case BFD_RELOC_D30V_15_PCREL: |
e0882f34 MM |
1837 | if (fixp->fx_where & 0x7) |
1838 | { | |
1839 | if (fixp->fx_done) | |
1840 | value += 4; | |
1841 | else | |
1842 | fixp->fx_r_type = BFD_RELOC_D30V_15_PCREL_R; | |
1843 | } | |
1844 | check_size (value, 15, fixp->fx_file, fixp->fx_line); | |
9b1168d6 MH |
1845 | insn |= (value >> 3) & 0xFFF; |
1846 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1847 | break; | |
343b2ab8 | 1848 | |
9b1168d6 | 1849 | case BFD_RELOC_D30V_21: |
e0882f34 | 1850 | check_size (value, 21, fixp->fx_file, fixp->fx_line); |
9b1168d6 MH |
1851 | insn |= (value >> 3) & 0x3FFFF; |
1852 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1853 | break; | |
343b2ab8 | 1854 | |
9b1168d6 | 1855 | case BFD_RELOC_D30V_21_PCREL: |
e0882f34 MM |
1856 | if (fixp->fx_where & 0x7) |
1857 | { | |
1858 | if (fixp->fx_done) | |
1859 | value += 4; | |
1860 | else | |
1861 | fixp->fx_r_type = BFD_RELOC_D30V_21_PCREL_R; | |
1862 | } | |
1863 | check_size (value, 21, fixp->fx_file, fixp->fx_line); | |
9b1168d6 MH |
1864 | insn |= (value >> 3) & 0x3FFFF; |
1865 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1866 | break; | |
343b2ab8 | 1867 | |
9b1168d6 MH |
1868 | case BFD_RELOC_D30V_32: |
1869 | insn2 = bfd_getb32 ((unsigned char *) where + 4); | |
343b2ab8 MM |
1870 | insn |= (value >> 26) & 0x3F; /* top 6 bits */ |
1871 | insn2 |= ((value & 0x03FC0000) << 2); /* next 8 bits */ | |
9b1168d6 MH |
1872 | insn2 |= value & 0x0003FFFF; /* bottom 18 bits */ |
1873 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1874 | bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4); | |
1875 | break; | |
343b2ab8 | 1876 | |
9b1168d6 | 1877 | case BFD_RELOC_D30V_32_PCREL: |
9b1168d6 | 1878 | insn2 = bfd_getb32 ((unsigned char *) where + 4); |
343b2ab8 MM |
1879 | insn |= (value >> 26) & 0x3F; /* top 6 bits */ |
1880 | insn2 |= ((value & 0x03FC0000) << 2); /* next 8 bits */ | |
9b1168d6 MH |
1881 | insn2 |= value & 0x0003FFFF; /* bottom 18 bits */ |
1882 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1883 | bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4); | |
1884 | break; | |
343b2ab8 | 1885 | |
9b1168d6 | 1886 | case BFD_RELOC_32: |
9b1168d6 MH |
1887 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); |
1888 | break; | |
343b2ab8 | 1889 | |
9b1168d6 | 1890 | default: |
633f5016 NC |
1891 | as_bad (_("line %d: unknown relocation type: 0x%x"), |
1892 | fixp->fx_line,fixp->fx_r_type); | |
9b1168d6 | 1893 | } |
633f5016 | 1894 | |
9b1168d6 MH |
1895 | return 0; |
1896 | } | |
1897 | ||
1898 | ||
1899 | /* d30v_cleanup() is called after the assembler has finished parsing the input | |
1900 | file or after a label is defined. Because the D30V assembler sometimes saves short | |
1901 | instructions to see if it can package them with the next instruction, there may | |
1902 | be a short instruction that still needs written. */ | |
1903 | int | |
aa7bf2a8 NC |
1904 | d30v_cleanup (use_sequential) |
1905 | int use_sequential; | |
9b1168d6 MH |
1906 | { |
1907 | segT seg; | |
1908 | subsegT subseg; | |
1909 | ||
1910 | if (prev_insn != -1) | |
1911 | { | |
1912 | seg = now_seg; | |
1913 | subseg = now_subseg; | |
1914 | subseg_set (prev_seg, prev_subseg); | |
aa7bf2a8 | 1915 | write_1_short (&prev_opcode, (long)prev_insn, fixups->next, use_sequential); |
9b1168d6 MH |
1916 | subseg_set (seg, subseg); |
1917 | prev_insn = -1; | |
aa7bf2a8 NC |
1918 | if (use_sequential) |
1919 | prev_mul32_p = false; | |
9b1168d6 MH |
1920 | } |
1921 | return 1; | |
1922 | } | |
1923 | ||
9b1168d6 MH |
1924 | static void |
1925 | d30v_number_to_chars (buf, value, n) | |
1926 | char *buf; /* Return 'nbytes' of chars here. */ | |
1927 | long long value; /* The value of the bits. */ | |
1928 | int n; /* Number of bytes in the output. */ | |
1929 | { | |
1930 | while (n--) | |
1931 | { | |
1932 | buf[n] = value & 0xff; | |
1933 | value >>= 8; | |
1934 | } | |
1935 | } | |
e0882f34 MM |
1936 | |
1937 | ||
1938 | /* This function is called at the start of every line. */ | |
1939 | /* it checks to see if the first character is a '.' */ | |
1940 | /* which indicates the start of a pseudo-op. If it is, */ | |
1941 | /* then write out any unwritten instructions */ | |
1942 | ||
1943 | void | |
7a0f469b | 1944 | d30v_start_line () |
e0882f34 MM |
1945 | { |
1946 | char *c = input_line_pointer; | |
1947 | ||
7a0f469b | 1948 | while (isspace (*c)) |
e0882f34 MM |
1949 | c++; |
1950 | ||
7a0f469b | 1951 | if (*c == '.') |
aa7bf2a8 | 1952 | d30v_cleanup (false); |
e0882f34 MM |
1953 | } |
1954 | ||
1955 | static void | |
1956 | check_size (value, bits, file, line) | |
1957 | long value; | |
1958 | int bits; | |
1959 | char *file; | |
1960 | int line; | |
1961 | { | |
1962 | int tmp, max; | |
1963 | ||
1964 | if (value < 0) | |
1965 | tmp = ~value; | |
1966 | else | |
1967 | tmp = value; | |
1968 | ||
1969 | max = (1 << (bits - 1)) - 1; | |
1970 | ||
1971 | if (tmp > max) | |
7d515759 | 1972 | as_bad_where (file, line, _("value too large to fit in %d bits"), bits); |
e0882f34 MM |
1973 | |
1974 | return; | |
1975 | } | |
7d515759 RH |
1976 | |
1977 | /* d30v_frob_label() is called when after a label is recognized. */ | |
1978 | ||
1979 | void | |
1980 | d30v_frob_label (lab) | |
1981 | symbolS *lab; | |
1982 | { | |
1983 | /* Emit any pending instructions. */ | |
aa7bf2a8 | 1984 | d30v_cleanup (false); |
7d515759 RH |
1985 | |
1986 | /* Update the label's address with the current output pointer. */ | |
1987 | lab->sy_frag = frag_now; | |
1988 | S_SET_VALUE (lab, (valueT) frag_now_fix ()); | |
1989 | ||
1990 | /* Record this label for future adjustment after we find out what | |
1991 | kind of data it references, and the required alignment therewith. */ | |
1992 | d30v_last_label = lab; | |
1993 | } | |
1994 | ||
1995 | /* Hook into cons for capturing alignment changes. */ | |
1996 | ||
1997 | void | |
1998 | d30v_cons_align (size) | |
1999 | int size; | |
2000 | { | |
2001 | int log_size; | |
2002 | ||
2003 | log_size = 0; | |
2004 | while ((size >>= 1) != 0) | |
2005 | ++log_size; | |
2006 | ||
2007 | if (d30v_current_align < log_size) | |
2008 | d30v_align (log_size, (char *) NULL, NULL); | |
2009 | else if (d30v_current_align > log_size) | |
2010 | d30v_current_align = log_size; | |
2011 | d30v_last_label = NULL; | |
2012 | } | |
2013 | ||
2014 | /* Called internally to handle all alignment needs. This takes care | |
2015 | of eliding calls to frag_align if'n the cached current alignment | |
2016 | says we've already got it, as well as taking care of the auto-aligning | |
2017 | labels wrt code. */ | |
2018 | ||
2019 | static void | |
2020 | d30v_align (n, pfill, label) | |
2021 | int n; | |
2022 | char *pfill; | |
2023 | symbolS *label; | |
2024 | { | |
2025 | /* The front end is prone to changing segments out from under us | |
2026 | temporarily when -g is in effect. */ | |
2027 | int switched_seg_p = (d30v_current_align_seg != now_seg); | |
2028 | ||
e21cafde FCE |
2029 | /* Do not assume that if 'd30v_current_align >= n' and |
2030 | '! switched_seg_p' that it is safe to avoid performing | |
2031 | this alignement request. The alignment of the current frag | |
2032 | can be changed under our feet, for example by a .ascii | |
2033 | directive in the source code. cf testsuite/gas/d30v/reloc.s */ | |
973e995d | 2034 | |
aa7bf2a8 | 2035 | d30v_cleanup (false); |
7d515759 RH |
2036 | |
2037 | if (pfill == NULL) | |
2038 | { | |
2039 | if (n > 2 | |
2040 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
2041 | { | |
2042 | static char const nop[4] = { 0x00, 0xf0, 0x00, 0x00 }; | |
2043 | ||
2044 | /* First, make sure we're on a four-byte boundary, in case | |
2045 | someone has been putting .byte values the text section. */ | |
2046 | if (d30v_current_align < 2 || switched_seg_p) | |
2047 | frag_align (2, 0, 0); | |
2048 | frag_align_pattern (n, nop, sizeof nop, 0); | |
2049 | } | |
2050 | else | |
2051 | frag_align (n, 0, 0); | |
2052 | } | |
2053 | else | |
2054 | frag_align (n, *pfill, 0); | |
2055 | ||
2056 | if (!switched_seg_p) | |
2057 | d30v_current_align = n; | |
2058 | ||
2059 | if (label != NULL) | |
2060 | { | |
bc67c823 NC |
2061 | symbolS * sym; |
2062 | int label_seen = false; | |
2063 | struct frag * old_frag; | |
2064 | valueT old_value; | |
2065 | valueT new_value; | |
2066 | ||
7d515759 | 2067 | assert (S_GET_SEGMENT (label) == now_seg); |
bc67c823 NC |
2068 | |
2069 | old_frag = label->sy_frag; | |
2070 | old_value = S_GET_VALUE (label); | |
7a0f469b | 2071 | new_value = (valueT) frag_now_fix (); |
bc67c823 NC |
2072 | |
2073 | /* It is possible to have more than one label at a particular | |
2074 | address, especially if debugging is enabled, so we must | |
2075 | take care to adjust all the labels at this address in this | |
2076 | fragment. To save time we search from the end of the symbol | |
2077 | list, backwards, since the symbols we are interested in are | |
2078 | almost certainly the ones that were most recently added. | |
2079 | Also to save time we stop searching once we have seen at least | |
2080 | one matching label, and we encounter a label that is no longer | |
2081 | in the target fragment. Note, this search is guaranteed to | |
2082 | find at least one match when sym == label, so no special case | |
2083 | code is necessary. */ | |
2084 | for (sym = symbol_lastP; sym != NULL; sym = sym->sy_previous) | |
2085 | { | |
2086 | if (sym->sy_frag == old_frag && S_GET_VALUE (sym) == old_value) | |
2087 | { | |
2088 | label_seen = true; | |
2089 | sym->sy_frag = frag_now; | |
2090 | S_SET_VALUE (sym, new_value); | |
2091 | } | |
2092 | else if (label_seen && sym->sy_frag != old_frag) | |
2093 | break; | |
2094 | } | |
7d515759 RH |
2095 | } |
2096 | ||
7a0f469b | 2097 | record_alignment (now_seg, n); |
7d515759 RH |
2098 | } |
2099 | ||
2100 | /* Handle the .align pseudo-op. This aligns to a power of two. We | |
2101 | hook here to latch the current alignment. */ | |
2102 | ||
2103 | static void | |
2104 | s_d30v_align (ignore) | |
2105 | int ignore; | |
2106 | { | |
2107 | int align; | |
2108 | char fill, *pfill = NULL; | |
2109 | long max_alignment = 15; | |
2110 | ||
2111 | align = get_absolute_expression (); | |
2112 | if (align > max_alignment) | |
2113 | { | |
2114 | align = max_alignment; | |
2115 | as_warn (_("Alignment too large: %d assumed"), align); | |
2116 | } | |
2117 | else if (align < 0) | |
2118 | { | |
2119 | as_warn (_("Alignment negative: 0 assumed")); | |
2120 | align = 0; | |
2121 | } | |
2122 | ||
2123 | if (*input_line_pointer == ',') | |
2124 | { | |
2125 | input_line_pointer++; | |
2126 | fill = get_absolute_expression (); | |
2127 | pfill = &fill; | |
2128 | } | |
2129 | ||
2130 | d30v_last_label = NULL; | |
2131 | d30v_align (align, pfill, NULL); | |
2132 | ||
2133 | demand_empty_rest_of_line (); | |
2134 | } | |
2135 | ||
2136 | /* Handle the .text pseudo-op. This is like the usual one, but it | |
2137 | clears the saved last label and resets known alignment. */ | |
2138 | ||
2139 | static void | |
2140 | s_d30v_text (i) | |
2141 | int i; | |
2142 | ||
2143 | { | |
2144 | s_text (i); | |
2145 | d30v_last_label = NULL; | |
2146 | d30v_current_align = 0; | |
2147 | d30v_current_align_seg = now_seg; | |
2148 | } | |
2149 | ||
2150 | /* Handle the .data pseudo-op. This is like the usual one, but it | |
2151 | clears the saved last label and resets known alignment. */ | |
2152 | ||
2153 | static void | |
2154 | s_d30v_data (i) | |
2155 | int i; | |
2156 | { | |
2157 | s_data (i); | |
2158 | d30v_last_label = NULL; | |
2159 | d30v_current_align = 0; | |
2160 | d30v_current_align_seg = now_seg; | |
2161 | } | |
2162 | ||
2163 | /* Handle the .section pseudo-op. This is like the usual one, but it | |
2164 | clears the saved last label and resets known alignment. */ | |
2165 | ||
2166 | static void | |
2167 | s_d30v_section (ignore) | |
2168 | int ignore; | |
2169 | { | |
2170 | obj_elf_section (ignore); | |
2171 | d30v_last_label = NULL; | |
2172 | d30v_current_align = 0; | |
2173 | d30v_current_align_seg = now_seg; | |
2174 | } |