Commit | Line | Data |
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9b1168d6 MH |
1 | /* tc-d30v.c -- Assembler code for the Mitsubishi D30V |
2 | ||
ccc12f73 | 3 | Copyright (C) 1997, 1998 Free Software Foundation. |
9b1168d6 MH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include <stdio.h> | |
23 | #include <ctype.h> | |
24 | #include "as.h" | |
25 | #include "subsegs.h" | |
26 | #include "opcode/d30v.h" | |
27 | ||
28 | const char comment_chars[] = ";"; | |
29 | const char line_comment_chars[] = "#"; | |
30 | const char line_separator_chars[] = ""; | |
343b2ab8 | 31 | const char *md_shortopts = "OnN"; |
9b1168d6 MH |
32 | const char EXP_CHARS[] = "eE"; |
33 | const char FLT_CHARS[] = "dD"; | |
34 | ||
343b2ab8 MM |
35 | #define NOP_MULTIPLY 1 |
36 | #define NOP_ALL 2 | |
37 | static int warn_nops = 0; | |
38 | static int Optimizing = 0; | |
9b1168d6 | 39 | |
e0882f34 MM |
40 | #define FORCE_SHORT 1 |
41 | #define FORCE_LONG 2 | |
42 | ||
343b2ab8 MM |
43 | /* EXEC types. */ |
44 | typedef enum _exec_type | |
45 | { | |
46 | EXEC_UNKNOWN, /* no order specified */ | |
ccc12f73 FF |
47 | EXEC_PARALLEL, /* done in parallel (FM=00) */ |
48 | EXEC_SEQ, /* sequential (FM=01) */ | |
49 | EXEC_REVSEQ /* reverse sequential (FM=10) */ | |
343b2ab8 MM |
50 | } exec_type_enum; |
51 | ||
9b1168d6 MH |
52 | /* fixups */ |
53 | #define MAX_INSN_FIXUPS (5) | |
54 | struct d30v_fixup | |
55 | { | |
56 | expressionS exp; | |
57 | int operand; | |
58 | int pcrel; | |
59 | int size; | |
60 | bfd_reloc_code_real_type reloc; | |
61 | }; | |
62 | ||
63 | typedef struct _fixups | |
64 | { | |
65 | int fc; | |
66 | struct d30v_fixup fix[MAX_INSN_FIXUPS]; | |
67 | struct _fixups *next; | |
68 | } Fixups; | |
69 | ||
70 | static Fixups FixUps[2]; | |
71 | static Fixups *fixups; | |
72 | ||
343b2ab8 | 73 | /* Whether current and previous instruction is a word multiply. */ |
7d515759 RH |
74 | static int cur_mul32_p = 0; |
75 | static int prev_mul32_p = 0; | |
343b2ab8 | 76 | |
ccc12f73 FF |
77 | /* The flag_explicitly_parallel is true iff the instruction being assembled |
78 | has been explicitly written as a parallel short-instruction pair by the | |
79 | human programmer. It is used in parallel_ok() to distinguish between | |
80 | those dangerous parallelizations attempted by the human, which are to be | |
81 | allowed, and those attempted by the assembler, which are not. It is set | |
82 | from md_assemble(). */ | |
83 | static int flag_explicitly_parallel = 0; | |
84 | static int flag_xp_state = 0; | |
85 | ||
7d515759 RH |
86 | /* The known current alignment of the current section. */ |
87 | static int d30v_current_align; | |
88 | static segT d30v_current_align_seg; | |
89 | ||
90 | /* The last seen label in the current section. This is used to auto-align | |
91 | labels preceeding instructions. */ | |
92 | static symbolS *d30v_last_label; | |
93 | ||
343b2ab8 MM |
94 | /* Two nops */ |
95 | #define NOP_LEFT ((long long)NOP << 32) | |
96 | #define NOP_RIGHT ((long long)NOP) | |
97 | #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT) | |
98 | ||
9b1168d6 MH |
99 | /* local functions */ |
100 | static int reg_name_search PARAMS ((char *name)); | |
101 | static int register_name PARAMS ((expressionS *expressionP)); | |
102 | static int check_range PARAMS ((unsigned long num, int bits, int flags)); | |
103 | static int postfix PARAMS ((char *p)); | |
104 | static bfd_reloc_code_real_type get_reloc PARAMS ((struct d30v_operand *op, int rel_flag)); | |
105 | static int get_operands PARAMS ((expressionS exp[], int cmp_hack)); | |
e0882f34 MM |
106 | static struct d30v_format *find_format PARAMS ((struct d30v_opcode *opcode, |
107 | expressionS ops[],int fsize, int cmp_hack)); | |
9b1168d6 MH |
108 | static long long build_insn PARAMS ((struct d30v_insn *opcode, expressionS *opers)); |
109 | static void write_long PARAMS ((struct d30v_insn *opcode, long long insn, Fixups *fx)); | |
110 | static void write_1_short PARAMS ((struct d30v_insn *opcode, long long insn, Fixups *fx)); | |
111 | static int write_2_short PARAMS ((struct d30v_insn *opcode1, long long insn1, | |
343b2ab8 | 112 | struct d30v_insn *opcode2, long long insn2, exec_type_enum exec_type, Fixups *fx)); |
daaef8f8 RH |
113 | static long long do_assemble PARAMS ((char *str, struct d30v_insn *opcode, |
114 | int shortp)); | |
9b1168d6 MH |
115 | static int parallel_ok PARAMS ((struct d30v_insn *opcode1, unsigned long insn1, |
116 | struct d30v_insn *opcode2, unsigned long insn2, | |
343b2ab8 | 117 | exec_type_enum exec_type)); |
9b1168d6 | 118 | static void d30v_number_to_chars PARAMS ((char *buf, long long value, int nbytes)); |
e0882f34 | 119 | static void check_size PARAMS ((long value, int bits, char *file, int line)); |
7d515759 RH |
120 | static void d30v_align PARAMS ((int, char *, symbolS *)); |
121 | static void s_d30v_align PARAMS ((int)); | |
122 | static void s_d30v_text PARAMS ((int)); | |
123 | static void s_d30v_data PARAMS ((int)); | |
124 | static void s_d30v_section PARAMS ((int)); | |
9b1168d6 MH |
125 | |
126 | struct option md_longopts[] = { | |
127 | {NULL, no_argument, NULL, 0} | |
128 | }; | |
129 | size_t md_longopts_size = sizeof(md_longopts); | |
130 | ||
131 | ||
132 | /* The target specific pseudo-ops which we support. */ | |
133 | const pseudo_typeS md_pseudo_table[] = | |
134 | { | |
e0882f34 MM |
135 | { "word", cons, 4 }, |
136 | { "hword", cons, 2 }, | |
7d515759 RH |
137 | { "align", s_d30v_align, 0 }, |
138 | { "text", s_d30v_text, 0 }, | |
139 | { "data", s_d30v_data, 0 }, | |
140 | { "section", s_d30v_section, 0 }, | |
141 | { "section.s", s_d30v_section, 0 }, | |
142 | { "sect", s_d30v_section, 0 }, | |
143 | { "sect.s", s_d30v_section, 0 }, | |
e0882f34 | 144 | { NULL, NULL, 0 } |
9b1168d6 MH |
145 | }; |
146 | ||
147 | /* Opcode hash table. */ | |
148 | static struct hash_control *d30v_hash; | |
149 | ||
150 | /* reg_name_search does a binary search of the pre_defined_registers | |
151 | array to see if "name" is a valid regiter name. Returns the register | |
152 | number from the array on success, or -1 on failure. */ | |
153 | ||
154 | static int | |
155 | reg_name_search (name) | |
156 | char *name; | |
157 | { | |
158 | int middle, low, high; | |
159 | int cmp; | |
160 | ||
161 | low = 0; | |
162 | high = reg_name_cnt() - 1; | |
163 | ||
164 | do | |
165 | { | |
166 | middle = (low + high) / 2; | |
167 | cmp = strcasecmp (name, pre_defined_registers[middle].name); | |
168 | if (cmp < 0) | |
169 | high = middle - 1; | |
170 | else if (cmp > 0) | |
171 | low = middle + 1; | |
172 | else | |
173 | return pre_defined_registers[middle].value; | |
174 | } | |
175 | while (low <= high); | |
176 | return -1; | |
177 | } | |
178 | ||
179 | /* register_name() checks the string at input_line_pointer | |
180 | to see if it is a valid register name */ | |
181 | ||
182 | static int | |
183 | register_name (expressionP) | |
184 | expressionS *expressionP; | |
185 | { | |
186 | int reg_number; | |
187 | char c, *p = input_line_pointer; | |
188 | ||
189 | while (*p && *p!='\n' && *p!='\r' && *p !=',' && *p!=' ' && *p!=')') | |
190 | p++; | |
191 | ||
192 | c = *p; | |
193 | if (c) | |
194 | *p++ = 0; | |
195 | ||
196 | /* look to see if it's in the register table */ | |
197 | reg_number = reg_name_search (input_line_pointer); | |
198 | if (reg_number >= 0) | |
199 | { | |
200 | expressionP->X_op = O_register; | |
201 | /* temporarily store a pointer to the string here */ | |
202 | expressionP->X_op_symbol = (struct symbol *)input_line_pointer; | |
203 | expressionP->X_add_number = reg_number; | |
204 | input_line_pointer = p; | |
205 | return 1; | |
206 | } | |
207 | if (c) | |
208 | *(p-1) = c; | |
209 | return 0; | |
210 | } | |
211 | ||
212 | ||
213 | static int | |
214 | check_range (num, bits, flags) | |
215 | unsigned long num; | |
216 | int bits; | |
217 | int flags; | |
218 | { | |
343b2ab8 | 219 | long min, max; |
9b1168d6 MH |
220 | int retval=0; |
221 | ||
222 | /* don't bother checking 32-bit values */ | |
223 | if (bits == 32) | |
224 | return 0; | |
225 | ||
226 | if (flags & OPERAND_SIGNED) | |
227 | { | |
228 | max = (1 << (bits - 1))-1; | |
e0882f34 | 229 | min = - (1 << (bits - 1)); |
9b1168d6 MH |
230 | if (((long)num > max) || ((long)num < min)) |
231 | retval = 1; | |
232 | } | |
233 | else | |
234 | { | |
235 | max = (1 << bits) - 1; | |
236 | min = 0; | |
237 | if ((num > max) || (num < min)) | |
238 | retval = 1; | |
239 | } | |
240 | return retval; | |
241 | } | |
242 | ||
243 | ||
244 | void | |
245 | md_show_usage (stream) | |
246 | FILE *stream; | |
247 | { | |
7d515759 | 248 | fprintf(stream, _("\nD30V options:\n\ |
343b2ab8 MM |
249 | -O Make adjacent short instructions parallel if possible.\n\ |
250 | -n Warn about all NOPs inserted by the assembler.\n\ | |
7d515759 | 251 | -N Warn about NOPs inserted after word multiplies.\n")); |
9b1168d6 MH |
252 | } |
253 | ||
254 | int | |
255 | md_parse_option (c, arg) | |
256 | int c; | |
257 | char *arg; | |
258 | { | |
259 | switch (c) | |
260 | { | |
9b1168d6 | 261 | /* Optimize. Will attempt to parallelize operations */ |
343b2ab8 | 262 | case 'O': |
9b1168d6 MH |
263 | Optimizing = 1; |
264 | break; | |
343b2ab8 MM |
265 | |
266 | /* Warn about all NOPS that the assembler inserts. */ | |
267 | case 'n': | |
268 | warn_nops = NOP_ALL; | |
269 | break; | |
270 | ||
271 | /* Warn about the NOPS that the assembler inserts because of the | |
272 | multiply hazard. */ | |
273 | case 'N': | |
274 | warn_nops = NOP_MULTIPLY; | |
275 | break; | |
276 | ||
9b1168d6 MH |
277 | default: |
278 | return 0; | |
279 | } | |
280 | return 1; | |
281 | } | |
282 | ||
283 | symbolS * | |
284 | md_undefined_symbol (name) | |
285 | char *name; | |
286 | { | |
287 | return 0; | |
288 | } | |
289 | ||
290 | /* Turn a string in input_line_pointer into a floating point constant of type | |
291 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
292 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
293 | */ | |
294 | char * | |
295 | md_atof (type, litP, sizeP) | |
296 | int type; | |
297 | char *litP; | |
298 | int *sizeP; | |
299 | { | |
300 | int prec; | |
301 | LITTLENUM_TYPE words[4]; | |
302 | char *t; | |
303 | int i; | |
304 | ||
305 | switch (type) | |
306 | { | |
307 | case 'f': | |
308 | prec = 2; | |
309 | break; | |
310 | case 'd': | |
311 | prec = 4; | |
312 | break; | |
313 | default: | |
314 | *sizeP = 0; | |
48401fcf | 315 | return _("bad call to md_atof"); |
9b1168d6 MH |
316 | } |
317 | ||
318 | t = atof_ieee (input_line_pointer, type, words); | |
319 | if (t) | |
320 | input_line_pointer = t; | |
321 | ||
322 | *sizeP = prec * 2; | |
323 | ||
324 | for (i = 0; i < prec; i++) | |
325 | { | |
326 | md_number_to_chars (litP, (valueT) words[i], 2); | |
327 | litP += 2; | |
328 | } | |
329 | return NULL; | |
330 | } | |
331 | ||
332 | void | |
333 | md_convert_frag (abfd, sec, fragP) | |
334 | bfd *abfd; | |
335 | asection *sec; | |
336 | fragS *fragP; | |
337 | { | |
338 | abort (); | |
339 | } | |
340 | ||
341 | valueT | |
342 | md_section_align (seg, addr) | |
343 | asection *seg; | |
344 | valueT addr; | |
345 | { | |
346 | int align = bfd_get_section_alignment (stdoutput, seg); | |
347 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
348 | } | |
349 | ||
350 | ||
351 | void | |
352 | md_begin () | |
353 | { | |
354 | struct d30v_opcode *opcode; | |
355 | d30v_hash = hash_new(); | |
356 | ||
357 | /* Insert opcode names into a hash table. */ | |
358 | for (opcode = (struct d30v_opcode *)d30v_opcode_table; opcode->name; opcode++) | |
359 | hash_insert (d30v_hash, opcode->name, (char *) opcode); | |
360 | ||
361 | fixups = &FixUps[0]; | |
362 | FixUps[0].next = &FixUps[1]; | |
363 | FixUps[1].next = &FixUps[0]; | |
7d515759 RH |
364 | |
365 | d30v_current_align_seg = now_seg; | |
9b1168d6 MH |
366 | } |
367 | ||
368 | ||
369 | /* this function removes the postincrement or postdecrement | |
370 | operator ( '+' or '-' ) from an expression */ | |
371 | ||
372 | static int postfix (p) | |
373 | char *p; | |
374 | { | |
375 | while (*p != '-' && *p != '+') | |
376 | { | |
2c268a85 | 377 | if (*p==0 || *p=='\n' || *p=='\r' || *p==' ' || *p==',') |
9b1168d6 MH |
378 | break; |
379 | p++; | |
380 | } | |
381 | ||
382 | if (*p == '-') | |
383 | { | |
384 | *p = ' '; | |
385 | return (-1); | |
386 | } | |
387 | if (*p == '+') | |
388 | { | |
389 | *p = ' '; | |
390 | return (1); | |
391 | } | |
392 | ||
393 | return (0); | |
394 | } | |
395 | ||
396 | ||
397 | static bfd_reloc_code_real_type | |
398 | get_reloc (op, rel_flag) | |
399 | struct d30v_operand *op; | |
400 | int rel_flag; | |
401 | { | |
402 | switch (op->bits) | |
403 | { | |
404 | case 6: | |
e0882f34 MM |
405 | if (op->flags & OPERAND_SHIFT) |
406 | return BFD_RELOC_D30V_9_PCREL; | |
407 | else | |
408 | return BFD_RELOC_D30V_6; | |
409 | break; | |
9b1168d6 MH |
410 | case 12: |
411 | if (!(op->flags & OPERAND_SHIFT)) | |
48401fcf | 412 | as_warn(_("unexpected 12-bit reloc type")); |
9b1168d6 MH |
413 | if (rel_flag == RELOC_PCREL) |
414 | return BFD_RELOC_D30V_15_PCREL; | |
415 | else | |
416 | return BFD_RELOC_D30V_15; | |
417 | case 18: | |
418 | if (!(op->flags & OPERAND_SHIFT)) | |
48401fcf | 419 | as_warn(_("unexpected 18-bit reloc type")); |
9b1168d6 MH |
420 | if (rel_flag == RELOC_PCREL) |
421 | return BFD_RELOC_D30V_21_PCREL; | |
422 | else | |
423 | return BFD_RELOC_D30V_21; | |
424 | case 32: | |
425 | if (rel_flag == RELOC_PCREL) | |
426 | return BFD_RELOC_D30V_32_PCREL; | |
427 | else | |
428 | return BFD_RELOC_D30V_32; | |
429 | default: | |
430 | return 0; | |
431 | } | |
432 | } | |
433 | ||
434 | /* get_operands parses a string of operands and returns | |
435 | an array of expressions */ | |
436 | ||
437 | static int | |
438 | get_operands (exp, cmp_hack) | |
439 | expressionS exp[]; | |
440 | int cmp_hack; | |
441 | { | |
442 | char *p = input_line_pointer; | |
443 | int numops = 0; | |
444 | int post = 0; | |
445 | ||
446 | if (cmp_hack) | |
447 | { | |
448 | exp[numops].X_op = O_absent; | |
449 | exp[numops++].X_add_number = cmp_hack - 1; | |
450 | } | |
451 | ||
452 | while (*p) | |
453 | { | |
454 | while (*p == ' ' || *p == '\t' || *p == ',') | |
455 | p++; | |
456 | if (*p==0 || *p=='\n' || *p=='\r') | |
457 | break; | |
458 | ||
459 | if (*p == '@') | |
460 | { | |
461 | p++; | |
462 | exp[numops].X_op = O_absent; | |
463 | if (*p == '(') | |
464 | { | |
465 | p++; | |
466 | exp[numops].X_add_number = OPERAND_ATPAR; | |
467 | post = postfix (p); | |
468 | } | |
469 | else if (*p == '-') | |
470 | { | |
471 | p++; | |
472 | exp[numops].X_add_number = OPERAND_ATMINUS; | |
473 | } | |
474 | else | |
475 | { | |
476 | exp[numops].X_add_number = OPERAND_ATSIGN; | |
477 | post = postfix (p); | |
478 | } | |
479 | numops++; | |
480 | continue; | |
481 | } | |
482 | ||
483 | if (*p == ')') | |
484 | { | |
485 | /* just skip the trailing paren */ | |
486 | p++; | |
487 | continue; | |
488 | } | |
489 | ||
490 | input_line_pointer = p; | |
491 | ||
492 | /* check to see if it might be a register name */ | |
493 | if (!register_name (&exp[numops])) | |
494 | { | |
495 | /* parse as an expression */ | |
496 | expression (&exp[numops]); | |
497 | } | |
498 | ||
499 | if (exp[numops].X_op == O_illegal) | |
48401fcf | 500 | as_bad (_("illegal operand")); |
9b1168d6 | 501 | else if (exp[numops].X_op == O_absent) |
48401fcf | 502 | as_bad (_("missing operand")); |
9b1168d6 MH |
503 | |
504 | numops++; | |
505 | p = input_line_pointer; | |
506 | ||
507 | switch (post) | |
508 | { | |
509 | case -1: /* postdecrement mode */ | |
510 | exp[numops].X_op = O_absent; | |
511 | exp[numops++].X_add_number = OPERAND_MINUS; | |
512 | break; | |
513 | case 1: /* postincrement mode */ | |
514 | exp[numops].X_op = O_absent; | |
515 | exp[numops++].X_add_number = OPERAND_PLUS; | |
516 | break; | |
517 | } | |
518 | post = 0; | |
519 | } | |
520 | ||
521 | exp[numops].X_op = 0; | |
522 | return (numops); | |
523 | } | |
524 | ||
9b1168d6 MH |
525 | /* build_insn generates the instruction. It does everything */ |
526 | /* but write the FM bits. */ | |
527 | ||
528 | static long long | |
529 | build_insn (opcode, opers) | |
530 | struct d30v_insn *opcode; | |
531 | expressionS *opers; | |
532 | { | |
343b2ab8 | 533 | int i, length, bits, shift, flags; |
9b1168d6 MH |
534 | unsigned int number, id=0; |
535 | long long insn; | |
536 | struct d30v_opcode *op = opcode->op; | |
537 | struct d30v_format *form = opcode->form; | |
538 | ||
9b1168d6 | 539 | insn = opcode->ecc << 28 | op->op1 << 25 | op->op2 << 20 | form->modifier << 18; |
e0882f34 | 540 | |
9b1168d6 MH |
541 | for (i=0; form->operands[i]; i++) |
542 | { | |
543 | flags = d30v_operand_table[form->operands[i]].flags; | |
544 | ||
9b1168d6 MH |
545 | /* must be a register or number */ |
546 | if (!(flags & OPERAND_REG) && !(flags & OPERAND_NUM) && | |
547 | !(flags & OPERAND_NAME) && !(flags & OPERAND_SPECIAL)) | |
548 | continue; | |
549 | ||
550 | bits = d30v_operand_table[form->operands[i]].bits; | |
e0882f34 MM |
551 | if (flags & OPERAND_SHIFT) |
552 | bits += 3; | |
553 | ||
9b1168d6 MH |
554 | length = d30v_operand_table[form->operands[i]].length; |
555 | shift = 12 - d30v_operand_table[form->operands[i]].position; | |
e0882f34 MM |
556 | if (opers[i].X_op != O_symbol) |
557 | number = opers[i].X_add_number; | |
558 | else | |
559 | number = 0; | |
9b1168d6 MH |
560 | if (flags & OPERAND_REG) |
561 | { | |
e0882f34 MM |
562 | /* check for mvfsys or mvtsys control registers */ |
563 | if (flags & OPERAND_CONTROL && (number & 0x7f) > MAX_CONTROL_REG) | |
9b1168d6 MH |
564 | { |
565 | /* PSWL or PSWH */ | |
e0882f34 MM |
566 | id = (number & 0x7f) - MAX_CONTROL_REG; |
567 | number = 0; | |
9b1168d6 MH |
568 | } |
569 | else if (number & OPERAND_FLAG) | |
570 | { | |
571 | id = 3; /* number is a flag register */ | |
572 | } | |
e0882f34 | 573 | number &= 0x7F; |
9b1168d6 MH |
574 | } |
575 | else if (flags & OPERAND_SPECIAL) | |
576 | { | |
577 | number = id; | |
578 | } | |
9b1168d6 MH |
579 | |
580 | if (opers[i].X_op != O_register && opers[i].X_op != O_constant && !(flags & OPERAND_NAME)) | |
581 | { | |
582 | /* now create a fixup */ | |
583 | ||
584 | if (fixups->fc >= MAX_INSN_FIXUPS) | |
48401fcf | 585 | as_fatal (_("too many fixups")); |
9b1168d6 MH |
586 | |
587 | fixups->fix[fixups->fc].reloc = | |
588 | get_reloc((struct d30v_operand *)&d30v_operand_table[form->operands[i]], op->reloc_flag); | |
589 | fixups->fix[fixups->fc].size = 4; | |
590 | fixups->fix[fixups->fc].exp = opers[i]; | |
591 | fixups->fix[fixups->fc].operand = form->operands[i]; | |
e0882f34 MM |
592 | if (fixups->fix[fixups->fc].reloc == BFD_RELOC_D30V_9_PCREL) |
593 | fixups->fix[fixups->fc].pcrel = RELOC_PCREL; | |
594 | else | |
595 | fixups->fix[fixups->fc].pcrel = op->reloc_flag; | |
9b1168d6 MH |
596 | (fixups->fc)++; |
597 | } | |
598 | ||
599 | /* truncate to the proper number of bits */ | |
2c268a85 | 600 | if ((opers[i].X_op == O_constant) && check_range (number, bits, flags)) |
48401fcf | 601 | as_bad(_("operand out of range: %d"),number); |
2c268a85 | 602 | if (bits < 31) |
9b1168d6 | 603 | number &= 0x7FFFFFFF >> (31 - bits); |
e0882f34 MM |
604 | if (flags & OPERAND_SHIFT) |
605 | number >>= 3; | |
9b1168d6 MH |
606 | if (bits == 32) |
607 | { | |
608 | /* it's a LONG instruction */ | |
609 | insn |= (number >> 26); /* top 6 bits */ | |
610 | insn <<= 32; /* shift the first word over */ | |
611 | insn |= ((number & 0x03FC0000) << 2); /* next 8 bits */ | |
612 | insn |= number & 0x0003FFFF; /* bottom 18 bits */ | |
613 | } | |
614 | else | |
615 | insn |= number << shift; | |
616 | } | |
617 | return insn; | |
618 | } | |
619 | ||
620 | ||
621 | /* write out a long form instruction */ | |
622 | static void | |
623 | write_long (opcode, insn, fx) | |
624 | struct d30v_insn *opcode; | |
625 | long long insn; | |
626 | Fixups *fx; | |
627 | { | |
628 | int i, where; | |
629 | char *f = frag_more(8); | |
630 | ||
631 | insn |= FM11; | |
632 | d30v_number_to_chars (f, insn, 8); | |
633 | ||
634 | for (i=0; i < fx->fc; i++) | |
635 | { | |
636 | if (fx->fix[i].reloc) | |
637 | { | |
638 | where = f - frag_now->fr_literal; | |
9b1168d6 MH |
639 | fix_new_exp (frag_now, |
640 | where, | |
641 | fx->fix[i].size, | |
642 | &(fx->fix[i].exp), | |
643 | fx->fix[i].pcrel, | |
644 | fx->fix[i].reloc); | |
645 | } | |
646 | } | |
647 | fx->fc = 0; | |
648 | } | |
649 | ||
650 | ||
651 | /* write out a short form instruction by itself */ | |
652 | static void | |
653 | write_1_short (opcode, insn, fx) | |
654 | struct d30v_insn *opcode; | |
655 | long long insn; | |
656 | Fixups *fx; | |
657 | { | |
658 | char *f = frag_more(8); | |
659 | int i, where; | |
660 | ||
343b2ab8 | 661 | if (warn_nops == NOP_ALL) |
48401fcf | 662 | as_warn (_("NOP inserted")); |
343b2ab8 | 663 | |
9b1168d6 MH |
664 | /* the other container needs to be NOP */ |
665 | /* according to 4.3.1: for FM=00, sub-instructions performed only | |
666 | by IU cannot be encoded in L-container. */ | |
667 | if (opcode->op->unit == IU) | |
343b2ab8 | 668 | insn |= FM00 | NOP_LEFT; /* right container */ |
9b1168d6 | 669 | else |
343b2ab8 | 670 | insn = FM00 | (insn << 32) | NOP_RIGHT; /* left container */ |
9b1168d6 MH |
671 | |
672 | d30v_number_to_chars (f, insn, 8); | |
673 | ||
674 | for (i=0; i < fx->fc; i++) | |
675 | { | |
676 | if (fx->fix[i].reloc) | |
677 | { | |
678 | where = f - frag_now->fr_literal; | |
9b1168d6 MH |
679 | fix_new_exp (frag_now, |
680 | where, | |
681 | fx->fix[i].size, | |
682 | &(fx->fix[i].exp), | |
683 | fx->fix[i].pcrel, | |
684 | fx->fix[i].reloc); | |
685 | } | |
686 | } | |
687 | fx->fc = 0; | |
688 | } | |
689 | ||
690 | /* write out a short form instruction if possible */ | |
691 | /* return number of instructions not written out */ | |
692 | static int | |
693 | write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx) | |
694 | struct d30v_insn *opcode1, *opcode2; | |
695 | long long insn1, insn2; | |
343b2ab8 | 696 | exec_type_enum exec_type; |
9b1168d6 MH |
697 | Fixups *fx; |
698 | { | |
343b2ab8 | 699 | long long insn = NOP2; |
9b1168d6 MH |
700 | char *f; |
701 | int i,j, where; | |
702 | ||
48401fcf TT |
703 | if(exec_type != EXEC_PARALLEL && |
704 | ((opcode1->op->flags_used & (FLAG_JSR | FLAG_DELAY)) == FLAG_JSR)) | |
9b1168d6 MH |
705 | { |
706 | /* subroutines must be called from 32-bit boundaries */ | |
707 | /* so the return address will be correct */ | |
708 | write_1_short (opcode1, insn1, fx->next); | |
709 | return (1); | |
710 | } | |
711 | ||
712 | switch (exec_type) | |
713 | { | |
343b2ab8 MM |
714 | case EXEC_UNKNOWN: /* order not specified */ |
715 | if (Optimizing && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) | |
9b1168d6 MH |
716 | { |
717 | /* parallel */ | |
343b2ab8 | 718 | exec_type = EXEC_PARALLEL; |
9b1168d6 MH |
719 | if (opcode1->op->unit == IU) |
720 | insn = FM00 | (insn2 << 32) | insn1; | |
721 | else if (opcode2->op->unit == MU) | |
722 | insn = FM00 | (insn2 << 32) | insn1; | |
723 | else | |
724 | { | |
725 | insn = FM00 | (insn1 << 32) | insn2; | |
726 | fx = fx->next; | |
727 | } | |
728 | } | |
343b2ab8 | 729 | else if (opcode1->op->unit == IU) |
9b1168d6 MH |
730 | { |
731 | /* reverse sequential */ | |
732 | insn = FM10 | (insn2 << 32) | insn1; | |
343b2ab8 | 733 | exec_type = EXEC_REVSEQ; |
9b1168d6 MH |
734 | } |
735 | else | |
736 | { | |
737 | /* sequential */ | |
738 | insn = FM01 | (insn1 << 32) | insn2; | |
343b2ab8 MM |
739 | fx = fx->next; |
740 | exec_type = EXEC_SEQ; | |
9b1168d6 MH |
741 | } |
742 | break; | |
343b2ab8 MM |
743 | |
744 | case EXEC_PARALLEL: /* parallel */ | |
ccc12f73 | 745 | flag_explicitly_parallel = flag_xp_state; |
343b2ab8 | 746 | if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) |
48401fcf | 747 | as_fatal (_("Instructions may not be executed in parallel")); |
343b2ab8 | 748 | else if (opcode1->op->unit == IU) |
9b1168d6 MH |
749 | { |
750 | if (opcode2->op->unit == IU) | |
48401fcf TT |
751 | as_fatal (_("Two IU instructions may not be executed in parallel")); |
752 | as_warn (_("Swapping instruction order")); | |
9b1168d6 MH |
753 | insn = FM00 | (insn2 << 32) | insn1; |
754 | } | |
755 | else if (opcode2->op->unit == MU) | |
756 | { | |
757 | if (opcode1->op->unit == MU) | |
48401fcf TT |
758 | as_fatal (_("Two MU instructions may not be executed in parallel")); |
759 | as_warn (_("Swapping instruction order")); | |
9b1168d6 MH |
760 | insn = FM00 | (insn2 << 32) | insn1; |
761 | } | |
762 | else | |
763 | { | |
764 | insn = FM00 | (insn1 << 32) | insn2; | |
765 | fx = fx->next; | |
766 | } | |
ccc12f73 | 767 | flag_explicitly_parallel = 0; |
9b1168d6 | 768 | break; |
343b2ab8 MM |
769 | |
770 | case EXEC_SEQ: /* sequential */ | |
9b1168d6 | 771 | if (opcode1->op->unit == IU) |
48401fcf | 772 | as_fatal (_("IU instruction may not be in the left container")); |
9b1168d6 MH |
773 | insn = FM01 | (insn1 << 32) | insn2; |
774 | fx = fx->next; | |
775 | break; | |
343b2ab8 MM |
776 | |
777 | case EXEC_REVSEQ: /* reverse sequential */ | |
9b1168d6 | 778 | if (opcode2->op->unit == MU) |
48401fcf | 779 | as_fatal (_("MU instruction may not be in the right container")); |
9b1168d6 MH |
780 | insn = FM10 | (insn1 << 32) | insn2; |
781 | fx = fx->next; | |
782 | break; | |
343b2ab8 | 783 | |
9b1168d6 | 784 | default: |
48401fcf | 785 | as_fatal(_("unknown execution type passed to write_2_short()")); |
9b1168d6 MH |
786 | } |
787 | ||
788 | /* printf("writing out %llx\n",insn); */ | |
789 | f = frag_more(8); | |
790 | d30v_number_to_chars (f, insn, 8); | |
791 | ||
343b2ab8 MM |
792 | /* If the previous instruction was a 32-bit multiply but it is put into a |
793 | parallel container, mark the current instruction as being a 32-bit | |
794 | multiply. */ | |
795 | if (prev_mul32_p && exec_type == EXEC_PARALLEL) | |
796 | cur_mul32_p = 1; | |
797 | ||
9b1168d6 MH |
798 | for (j=0; j<2; j++) |
799 | { | |
800 | for (i=0; i < fx->fc; i++) | |
801 | { | |
802 | if (fx->fix[i].reloc) | |
803 | { | |
804 | where = (f - frag_now->fr_literal) + 4*j; | |
805 | ||
9b1168d6 MH |
806 | fix_new_exp (frag_now, |
807 | where, | |
808 | fx->fix[i].size, | |
809 | &(fx->fix[i].exp), | |
810 | fx->fix[i].pcrel, | |
811 | fx->fix[i].reloc); | |
812 | } | |
813 | } | |
814 | fx->fc = 0; | |
815 | fx = fx->next; | |
816 | } | |
817 | return (0); | |
818 | } | |
819 | ||
820 | ||
821 | /* Check 2 instructions and determine if they can be safely */ | |
822 | /* executed in parallel. Returns 1 if they can be. */ | |
823 | static int | |
824 | parallel_ok (op1, insn1, op2, insn2, exec_type) | |
825 | struct d30v_insn *op1, *op2; | |
826 | unsigned long insn1, insn2; | |
343b2ab8 | 827 | exec_type_enum exec_type; |
9b1168d6 | 828 | { |
e0882f34 MM |
829 | int i, j, shift, regno, bits, ecc; |
830 | unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2; | |
343b2ab8 | 831 | unsigned long ins, mod_reg[2][3], used_reg[2][3], flag_reg[2]; |
1b524697 MH |
832 | struct d30v_format *f; |
833 | struct d30v_opcode *op; | |
834 | ||
835 | /* section 4.3: both instructions must not be IU or MU only */ | |
836 | if ((op1->op->unit == IU && op2->op->unit == IU) | |
837 | || (op1->op->unit == MU && op2->op->unit == MU)) | |
9b1168d6 MH |
838 | return 0; |
839 | ||
343b2ab8 MM |
840 | /* first instruction must not be a jump to safely optimize, unless this |
841 | is an explicit parallel operation. */ | |
842 | if (exec_type != EXEC_PARALLEL | |
843 | && (op1->op->flags_used & (FLAG_JMP | FLAG_JSR))) | |
e0882f34 MM |
844 | return 0; |
845 | ||
846 | /* If one instruction is /TX or /XT and the other is /FX or /XF respectively, | |
847 | then it is safe to allow the two to be done as parallel ops, since only | |
848 | one will ever be executed at a time. */ | |
849 | if ((op1->ecc == ECC_TX && op2->ecc == ECC_FX) | |
850 | || (op1->ecc == ECC_FX && op2->ecc == ECC_TX) | |
851 | || (op1->ecc == ECC_XT && op2->ecc == ECC_XF) | |
852 | || (op1->ecc == ECC_XF && op2->ecc == ECC_XT)) | |
853 | return 1; | |
854 | ||
855 | /* [0] r0-r31 | |
856 | [1] r32-r63 | |
857 | [2] a0, a1, flag registers */ | |
9b1168d6 | 858 | |
1b524697 | 859 | for (j = 0; j < 2; j++) |
9b1168d6 MH |
860 | { |
861 | if (j == 0) | |
862 | { | |
1b524697 MH |
863 | f = op1->form; |
864 | op = op1->op; | |
e0882f34 | 865 | ecc = op1->ecc; |
9b1168d6 MH |
866 | ins = insn1; |
867 | } | |
868 | else | |
869 | { | |
1b524697 MH |
870 | f = op2->form; |
871 | op = op2->op; | |
e0882f34 | 872 | ecc = op2->ecc; |
9b1168d6 MH |
873 | ins = insn2; |
874 | } | |
343b2ab8 | 875 | flag_reg[j] = 0; |
1b524697 | 876 | mod_reg[j][0] = mod_reg[j][1] = 0; |
e0882f34 | 877 | mod_reg[j][2] = (op->flags_set & FLAG_ALL); |
1b524697 | 878 | used_reg[j][0] = used_reg[j][1] = 0; |
e0882f34 MM |
879 | used_reg[j][2] = (op->flags_used & FLAG_ALL); |
880 | ||
881 | /* BSR/JSR always sets R62 */ | |
882 | if (op->flags_used & FLAG_JSR) | |
883 | mod_reg[j][1] = (1L << (62-32)); | |
884 | ||
885 | /* conditional execution affects the flags_used */ | |
886 | switch (ecc) | |
887 | { | |
888 | case ECC_TX: | |
889 | case ECC_FX: | |
343b2ab8 | 890 | used_reg[j][2] |= flag_reg[j] = FLAG_0; |
e0882f34 MM |
891 | break; |
892 | ||
893 | case ECC_XT: | |
894 | case ECC_XF: | |
343b2ab8 | 895 | used_reg[j][2] |= flag_reg[j] = FLAG_1; |
e0882f34 MM |
896 | break; |
897 | ||
898 | case ECC_TT: | |
899 | case ECC_TF: | |
343b2ab8 | 900 | used_reg[j][2] |= flag_reg[j] = (FLAG_0 | FLAG_1); |
e0882f34 MM |
901 | break; |
902 | } | |
903 | ||
1b524697 | 904 | for (i = 0; f->operands[i]; i++) |
9b1168d6 | 905 | { |
1b524697 MH |
906 | flags = d30v_operand_table[f->operands[i]].flags; |
907 | shift = 12 - d30v_operand_table[f->operands[i]].position; | |
908 | bits = d30v_operand_table[f->operands[i]].bits; | |
909 | if (bits == 32) | |
910 | mask = 0xffffffff; | |
911 | else | |
912 | mask = 0x7FFFFFFF >> (31 - bits); | |
e0882f34 MM |
913 | |
914 | if ((flags & OPERAND_PLUS) || (flags & OPERAND_MINUS)) | |
915 | { | |
916 | /* this is a post-increment or post-decrement */ | |
917 | /* the previous register needs to be marked as modified */ | |
918 | ||
919 | shift = 12 - d30v_operand_table[f->operands[i-1]].position; | |
920 | regno = (ins >> shift) & 0x3f; | |
921 | if (regno >= 32) | |
922 | mod_reg[j][1] |= 1L << (regno - 32); | |
923 | else | |
924 | mod_reg[j][0] |= 1L << regno; | |
925 | } | |
926 | else if (flags & OPERAND_REG) | |
9b1168d6 MH |
927 | { |
928 | regno = (ins >> shift) & mask; | |
e0882f34 MM |
929 | /* the memory write functions don't have a destination register */ |
930 | if ((flags & OPERAND_DEST) && !(op->flags_set & FLAG_MEM)) | |
9b1168d6 | 931 | { |
e0882f34 | 932 | /* MODIFIED registers and flags */ |
1b524697 | 933 | if (flags & OPERAND_ACC) |
e0882f34 MM |
934 | { |
935 | if (regno == 0) | |
936 | mod_reg[j][2] |= FLAG_A0; | |
937 | else if (regno == 1) | |
938 | mod_reg[j][2] |= FLAG_A1; | |
939 | else | |
940 | abort (); | |
941 | } | |
1b524697 | 942 | else if (flags & OPERAND_FLAG) |
e0882f34 | 943 | mod_reg[j][2] |= 1L << regno; |
1b524697 MH |
944 | else if (!(flags & OPERAND_CONTROL)) |
945 | { | |
e0882f34 MM |
946 | int r, z; |
947 | ||
948 | /* need to check if there are two destination */ | |
949 | /* registers, for example ld2w */ | |
950 | if (flags & OPERAND_2REG) | |
951 | z = 1; | |
1b524697 | 952 | else |
e0882f34 MM |
953 | z = 0; |
954 | ||
955 | for (r = regno; r <= regno + z; r++) | |
956 | { | |
957 | if (r >= 32) | |
958 | mod_reg[j][1] |= 1L << (r - 32); | |
959 | else | |
960 | mod_reg[j][0] |= 1L << r; | |
961 | } | |
1b524697 | 962 | } |
9b1168d6 MH |
963 | } |
964 | else | |
965 | { | |
e0882f34 | 966 | /* USED, but not modified registers and flags */ |
1b524697 | 967 | if (flags & OPERAND_ACC) |
e0882f34 MM |
968 | { |
969 | if (regno == 0) | |
970 | used_reg[j][2] |= FLAG_A0; | |
971 | else if (regno == 1) | |
972 | used_reg[j][2] |= FLAG_A1; | |
973 | else | |
974 | abort (); | |
975 | } | |
1b524697 | 976 | else if (flags & OPERAND_FLAG) |
e0882f34 | 977 | used_reg[j][2] |= 1L << regno; |
1b524697 MH |
978 | else if (!(flags & OPERAND_CONTROL)) |
979 | { | |
e0882f34 MM |
980 | int r, z; |
981 | ||
982 | /* need to check if there are two source */ | |
983 | /* registers, for example st2w */ | |
984 | if (flags & OPERAND_2REG) | |
985 | z = 1; | |
1b524697 | 986 | else |
e0882f34 MM |
987 | z = 0; |
988 | ||
989 | for (r = regno; r <= regno + z; r++) | |
990 | { | |
991 | if (r >= 32) | |
992 | used_reg[j][1] |= 1L << (r - 32); | |
993 | else | |
994 | used_reg[j][0] |= 1L << r; | |
995 | } | |
1b524697 | 996 | } |
9b1168d6 MH |
997 | } |
998 | } | |
999 | } | |
9b1168d6 | 1000 | } |
1b524697 | 1001 | |
e0882f34 MM |
1002 | flags_set1 = op1->op->flags_set; |
1003 | flags_set2 = op2->op->flags_set; | |
1004 | flags_used1 = op1->op->flags_used; | |
1005 | flags_used2 = op2->op->flags_used; | |
1006 | ||
1007 | /* ST2W/ST4HB combined with ADDppp/SUBppp is illegal. */ | |
1008 | if (((flags_set1 & (FLAG_MEM | FLAG_2WORD)) == (FLAG_MEM | FLAG_2WORD) | |
1009 | && (flags_used2 & FLAG_ADDSUBppp) != 0) | |
1010 | || ((flags_set2 & (FLAG_MEM | FLAG_2WORD)) == (FLAG_MEM | FLAG_2WORD) | |
1011 | && (flags_used1 & FLAG_ADDSUBppp) != 0)) | |
1012 | return 0; | |
1013 | ||
1014 | /* Load instruction combined with half-word multiply is illegal. */ | |
1015 | if (((flags_used1 & FLAG_MEM) != 0 && (flags_used2 & FLAG_MUL16)) | |
1016 | || ((flags_used2 & FLAG_MEM) != 0 && (flags_used1 & FLAG_MUL16))) | |
1017 | return 0; | |
1018 | ||
1019 | /* Specifically allow add || add by removing carry, overflow bits dependency. | |
1020 | This is safe, even if an addc follows since the IU takes the argument in | |
1021 | the right container, and it writes its results last. | |
1022 | However, don't paralellize add followed by addc or sub followed by | |
1023 | subb. */ | |
1024 | ||
1025 | if (mod_reg[0][2] == FLAG_CVVA && mod_reg[1][2] == FLAG_CVVA | |
343b2ab8 MM |
1026 | && (used_reg[0][2] & ~flag_reg[0]) == 0 |
1027 | && (used_reg[1][2] & ~flag_reg[1]) == 0 | |
e0882f34 MM |
1028 | && op1->op->unit == EITHER && op2->op->unit == EITHER) |
1029 | { | |
1030 | mod_reg[0][2] = mod_reg[1][2] = 0; | |
1031 | } | |
1032 | ||
1b524697 | 1033 | for(j = 0; j < 3; j++) |
e0882f34 MM |
1034 | { |
1035 | /* If the second instruction depends on the first, we obviously | |
1036 | cannot parallelize. Note, the mod flag implies use, so | |
1037 | check that as well. */ | |
ccc12f73 FF |
1038 | /* If flag_explicitly_parallel is set, then the case of the |
1039 | second instruction using a register the first instruction | |
1040 | modifies is assumed to be okay; we trust the human. We | |
1041 | don't trust the human if both instructions modify the same | |
1042 | register but we do trust the human if they modify the same | |
1043 | flags. */ | |
1044 | if (flag_explicitly_parallel) | |
1045 | { | |
1046 | if ((j < 2) && (mod_reg[0][j] & mod_reg[1][j]) != 0) | |
1047 | return 0; | |
1048 | } | |
1049 | else | |
1050 | if ((mod_reg[0][j] & (mod_reg[1][j] | used_reg[1][j])) != 0) | |
1051 | return 0; | |
e0882f34 MM |
1052 | } |
1053 | ||
1b524697 | 1054 | return 1; |
9b1168d6 MH |
1055 | } |
1056 | ||
1057 | ||
1058 | ||
1059 | /* This is the main entry point for the machine-dependent assembler. str points to a | |
1060 | machine-dependent instruction. This function is supposed to emit the frags/bytes | |
1061 | it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing | |
343b2ab8 | 1062 | and leaves the difficult stuff to do_assemble(). */ |
9b1168d6 MH |
1063 | |
1064 | static long long prev_insn = -1; | |
1065 | static struct d30v_insn prev_opcode; | |
1066 | static subsegT prev_subseg; | |
1067 | static segT prev_seg = 0; | |
1068 | ||
1069 | void | |
1070 | md_assemble (str) | |
1071 | char *str; | |
1072 | { | |
1073 | struct d30v_insn opcode; | |
1074 | long long insn; | |
343b2ab8 MM |
1075 | exec_type_enum extype = EXEC_UNKNOWN; /* execution type; parallel, etc */ |
1076 | static exec_type_enum etype = EXEC_UNKNOWN; /* saved extype. used for multiline instructions */ | |
9b1168d6 MH |
1077 | char *str2; |
1078 | ||
7d515759 RH |
1079 | if ((prev_insn != -1) && prev_seg |
1080 | && ((prev_seg != now_seg) || (prev_subseg != now_subseg))) | |
e0882f34 MM |
1081 | d30v_cleanup(); |
1082 | ||
7d515759 RH |
1083 | if (d30v_current_align < 3) |
1084 | d30v_align (3, NULL, d30v_last_label); | |
1085 | else if (d30v_current_align > 3) | |
1086 | d30v_current_align = 3; | |
1087 | d30v_last_label = NULL; | |
1088 | ||
ccc12f73 FF |
1089 | flag_explicitly_parallel = 0; |
1090 | flag_xp_state = 0; | |
343b2ab8 | 1091 | if (etype == EXEC_UNKNOWN) |
9b1168d6 MH |
1092 | { |
1093 | /* look for the special multiple instruction separators */ | |
1094 | str2 = strstr (str, "||"); | |
1095 | if (str2) | |
ccc12f73 FF |
1096 | { |
1097 | extype = EXEC_PARALLEL; | |
1098 | flag_xp_state = 1; | |
1099 | } | |
9b1168d6 MH |
1100 | else |
1101 | { | |
1102 | str2 = strstr (str, "->"); | |
1103 | if (str2) | |
343b2ab8 | 1104 | extype = EXEC_SEQ; |
9b1168d6 MH |
1105 | else |
1106 | { | |
1107 | str2 = strstr (str, "<-"); | |
1108 | if (str2) | |
343b2ab8 | 1109 | extype = EXEC_REVSEQ; |
9b1168d6 MH |
1110 | } |
1111 | } | |
1112 | /* str2 points to the separator, if one */ | |
1113 | if (str2) | |
1114 | { | |
1115 | *str2 = 0; | |
1116 | ||
1117 | /* if two instructions are present and we already have one saved | |
1118 | then first write it out */ | |
1119 | d30v_cleanup(); | |
1120 | ||
1121 | /* assemble first instruction and save it */ | |
daaef8f8 | 1122 | prev_insn = do_assemble (str, &prev_opcode, 1); |
9b1168d6 | 1123 | if (prev_insn == -1) |
7d515759 | 1124 | as_fatal (_("Cannot assemble instruction")); |
e0882f34 | 1125 | if (prev_opcode.form->form >= LONG) |
48401fcf | 1126 | as_fatal (_("First opcode is long. Unable to mix instructions as specified.")); |
9b1168d6 MH |
1127 | fixups = fixups->next; |
1128 | str = str2 + 2; | |
1129 | } | |
1130 | } | |
1131 | ||
daaef8f8 RH |
1132 | insn = do_assemble (str, &opcode, |
1133 | (extype != EXEC_UNKNOWN || etype != EXEC_UNKNOWN)); | |
9b1168d6 MH |
1134 | if (insn == -1) |
1135 | { | |
daaef8f8 | 1136 | if (extype != EXEC_UNKNOWN) |
9b1168d6 MH |
1137 | { |
1138 | etype = extype; | |
1139 | return; | |
1140 | } | |
7d515759 | 1141 | as_fatal (_("Cannot assemble instruction")); |
9b1168d6 MH |
1142 | } |
1143 | ||
daaef8f8 | 1144 | if (etype != EXEC_UNKNOWN) |
9b1168d6 MH |
1145 | { |
1146 | extype = etype; | |
daaef8f8 | 1147 | etype = EXEC_UNKNOWN; |
9b1168d6 MH |
1148 | } |
1149 | ||
343b2ab8 MM |
1150 | /* Word multiply instructions must not be followed by either a load or a |
1151 | 16-bit multiply instruction in the next cycle. */ | |
1152 | if (prev_mul32_p && (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16))) | |
1153 | { | |
1154 | /* However, load and multiply should able to be combined in a parallel | |
1155 | operation, so check for that first. */ | |
1156 | ||
1157 | if (prev_insn != -1 | |
1158 | && (opcode.op->flags_used & FLAG_MEM) | |
1159 | && opcode.form->form < LONG | |
1160 | && (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN)) | |
1161 | && parallel_ok (&prev_opcode, (long)prev_insn, | |
1162 | &opcode, (long)insn, extype) | |
1163 | && write_2_short (&prev_opcode, (long)prev_insn, | |
1164 | &opcode, (long)insn, extype, fixups) == 0) | |
1165 | { | |
1166 | /* no instructions saved */ | |
1167 | prev_insn = -1; | |
1168 | return; | |
1169 | } | |
1170 | ||
1171 | /* Can't parallelize, flush current instruction and emit a word of NOPS */ | |
1172 | else | |
1173 | { | |
1174 | char *f; | |
1175 | d30v_cleanup(); | |
1176 | ||
1177 | f = frag_more(8); | |
1178 | d30v_number_to_chars (f, NOP2, 8); | |
1179 | if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY) | |
48401fcf | 1180 | { |
7d515759 | 1181 | if (opcode.op->flags_used & FLAG_MEM) |
48401fcf TT |
1182 | as_warn (_("word of NOPs added between word multiply and load")); |
1183 | else | |
1184 | as_warn (_("word of NOPs added between word multiply and 16-bit multiply")); | |
1185 | } | |
343b2ab8 MM |
1186 | } |
1187 | } | |
1188 | ||
9b1168d6 MH |
1189 | /* if this is a long instruction, write it and any previous short instruction */ |
1190 | if (opcode.form->form >= LONG) | |
1191 | { | |
1192 | if (extype) | |
48401fcf | 1193 | as_fatal(_("Unable to mix instructions as specified")); |
9b1168d6 MH |
1194 | d30v_cleanup(); |
1195 | write_long (&opcode, insn, fixups); | |
1196 | prev_insn = -1; | |
1197 | return; | |
1198 | } | |
343b2ab8 MM |
1199 | |
1200 | if ((prev_insn != -1) && | |
1201 | (write_2_short (&prev_opcode, (long)prev_insn, &opcode, (long)insn, extype, fixups) == 0)) | |
9b1168d6 MH |
1202 | { |
1203 | /* no instructions saved */ | |
1204 | prev_insn = -1; | |
1205 | } | |
343b2ab8 | 1206 | |
9b1168d6 MH |
1207 | else |
1208 | { | |
1209 | if (extype) | |
48401fcf | 1210 | as_fatal(_("Unable to mix instructions as specified")); |
9b1168d6 | 1211 | /* save off last instruction so it may be packed on next pass */ |
343b2ab8 | 1212 | memcpy(&prev_opcode, &opcode, sizeof(prev_opcode)); |
9b1168d6 MH |
1213 | prev_insn = insn; |
1214 | prev_seg = now_seg; | |
1215 | prev_subseg = now_subseg; | |
1216 | fixups = fixups->next; | |
1217 | } | |
1218 | } | |
1219 | ||
1220 | ||
1221 | /* do_assemble assembles a single instruction and returns an opcode */ | |
1222 | /* it returns -1 (an invalid opcode) on error */ | |
1223 | ||
1224 | static long long | |
daaef8f8 | 1225 | do_assemble (str, opcode, shortp) |
9b1168d6 MH |
1226 | char *str; |
1227 | struct d30v_insn *opcode; | |
daaef8f8 | 1228 | int shortp; |
9b1168d6 MH |
1229 | { |
1230 | unsigned char *op_start, *save; | |
1231 | unsigned char *op_end; | |
1232 | char name[20]; | |
daaef8f8 | 1233 | int cmp_hack, nlen = 0, fsize = (shortp ? FORCE_SHORT : 0); |
9b1168d6 MH |
1234 | expressionS myops[6]; |
1235 | long long insn; | |
1236 | ||
9b1168d6 MH |
1237 | /* Drop leading whitespace */ |
1238 | while (*str == ' ') | |
1239 | str++; | |
1240 | ||
1241 | /* find the opcode end */ | |
1242 | for (op_start = op_end = (unsigned char *) (str); | |
1243 | *op_end | |
1244 | && nlen < 20 | |
1245 | && *op_end != '/' | |
1246 | && !is_end_of_line[*op_end] && *op_end != ' '; | |
1247 | op_end++) | |
1248 | { | |
1249 | name[nlen] = tolower(op_start[nlen]); | |
1250 | nlen++; | |
1251 | } | |
1252 | ||
1253 | if (nlen == 0) | |
1254 | return (-1); | |
1255 | ||
1256 | name[nlen] = 0; | |
1257 | ||
1258 | /* if there is an execution condition code, handle it */ | |
1259 | if (*op_end == '/') | |
1260 | { | |
1261 | int i = 0; | |
1262 | while ( (i < ECC_MAX) && strncasecmp(d30v_ecc_names[i],op_end+1,2)) | |
1263 | i++; | |
1264 | ||
1265 | if (i == ECC_MAX) | |
1266 | { | |
1267 | char tmp[4]; | |
1268 | strncpy(tmp,op_end+1,2); | |
1269 | tmp[2] = 0; | |
48401fcf | 1270 | as_fatal (_("unknown condition code: %s"),tmp); |
9b1168d6 MH |
1271 | return -1; |
1272 | } | |
1273 | /* printf("condition code=%d\n",i); */ | |
1274 | opcode->ecc = i; | |
1275 | op_end += 3; | |
1276 | } | |
1277 | else | |
1278 | opcode->ecc = ECC_AL; | |
1279 | ||
1280 | ||
1281 | /* CMP and CMPU change their name based on condition codes */ | |
1282 | if (!strncmp(name,"cmp",3)) | |
1283 | { | |
1284 | int p,i; | |
1285 | char **str = (char **)d30v_cc_names; | |
1286 | if (name[3] == 'u') | |
1287 | p = 4; | |
1288 | else | |
1289 | p = 3; | |
1290 | ||
343b2ab8 | 1291 | for(i=1; *str && strncmp(*str,&name[p],2); i++, str++) |
9b1168d6 MH |
1292 | ; |
1293 | ||
e0882f34 MM |
1294 | /* cmpu only supports some condition codes */ |
1295 | if (p == 4) | |
1296 | { | |
1297 | if (i < 3 || i > 6) | |
1298 | { | |
1299 | name[p+2]=0; | |
7d515759 | 1300 | as_fatal (_("cmpu doesn't support condition code %s"),&name[p]); |
e0882f34 MM |
1301 | } |
1302 | } | |
1303 | ||
9b1168d6 MH |
1304 | if (!*str) |
1305 | { | |
1306 | name[p+2]=0; | |
48401fcf | 1307 | as_fatal (_("unknown condition code: %s"),&name[p]); |
9b1168d6 MH |
1308 | } |
1309 | ||
1310 | cmp_hack = i; | |
1311 | name[p] = 0; | |
1312 | } | |
1313 | else | |
1314 | cmp_hack = 0; | |
1315 | ||
1316 | /* printf("cmp_hack=%d\n",cmp_hack); */ | |
1317 | ||
e0882f34 MM |
1318 | /* need to look for .s or .l */ |
1319 | if (name[nlen-2] == '.') | |
1320 | { | |
1321 | switch (name[nlen-1]) | |
1322 | { | |
1323 | case 's': | |
1324 | fsize = FORCE_SHORT; | |
1325 | break; | |
1326 | case 'l': | |
1327 | fsize = FORCE_LONG; | |
ccc12f73 | 1328 | break; |
e0882f34 MM |
1329 | } |
1330 | name[nlen-2] = 0; | |
1331 | } | |
1332 | ||
9b1168d6 MH |
1333 | /* find the first opcode with the proper name */ |
1334 | opcode->op = (struct d30v_opcode *)hash_find (d30v_hash, name); | |
1335 | if (opcode->op == NULL) | |
48401fcf | 1336 | as_fatal (_("unknown opcode: %s"),name); |
9b1168d6 MH |
1337 | |
1338 | save = input_line_pointer; | |
1339 | input_line_pointer = op_end; | |
e0882f34 | 1340 | while (!(opcode->form = find_format (opcode->op, myops, fsize, cmp_hack))) |
9b1168d6 MH |
1341 | { |
1342 | opcode->op++; | |
1343 | if (strcmp(opcode->op->name,name)) | |
7d515759 | 1344 | as_fatal (_("operands for opcode `%s' do not match any valid format"), name); |
9b1168d6 MH |
1345 | } |
1346 | input_line_pointer = save; | |
1347 | ||
1348 | insn = build_insn (opcode, myops); | |
343b2ab8 MM |
1349 | |
1350 | /* Propigate multiply status */ | |
1351 | if (insn != -1) | |
1352 | { | |
1353 | prev_mul32_p = cur_mul32_p; | |
1354 | cur_mul32_p = (opcode->op->flags_used & FLAG_MUL32) != 0; | |
1355 | } | |
1356 | ||
9b1168d6 MH |
1357 | return (insn); |
1358 | } | |
1359 | ||
1360 | ||
7d515759 RH |
1361 | /* find_format() gets a pointer to an entry in the format table. |
1362 | It must look at all formats for an opcode and use the operands | |
1363 | to choose the correct one. Returns NULL on error. */ | |
9b1168d6 MH |
1364 | |
1365 | static struct d30v_format * | |
e0882f34 | 1366 | find_format (opcode, myops, fsize, cmp_hack) |
9b1168d6 MH |
1367 | struct d30v_opcode *opcode; |
1368 | expressionS myops[]; | |
e0882f34 | 1369 | int fsize; |
9b1168d6 MH |
1370 | int cmp_hack; |
1371 | { | |
1372 | int numops, match, index, i=0, j, k; | |
1373 | struct d30v_format *fm; | |
9b1168d6 | 1374 | |
7d515759 | 1375 | /* Get all the operands and save them as expressions. */ |
9b1168d6 MH |
1376 | numops = get_operands (myops, cmp_hack); |
1377 | ||
343b2ab8 | 1378 | while ((index = opcode->format[i++]) != 0) |
9b1168d6 | 1379 | { |
7d515759 | 1380 | if (fsize == FORCE_SHORT && index >= LONG) |
e0882f34 MM |
1381 | continue; |
1382 | ||
7d515759 | 1383 | if (fsize == FORCE_LONG && index < LONG) |
e0882f34 MM |
1384 | continue; |
1385 | ||
9b1168d6 MH |
1386 | fm = (struct d30v_format *)&d30v_format_table[index]; |
1387 | k = index; | |
1388 | while (fm->form == index) | |
1389 | { | |
1390 | match = 1; | |
7d515759 | 1391 | /* Now check the operands for compatibility. */ |
9b1168d6 MH |
1392 | for (j = 0; match && fm->operands[j]; j++) |
1393 | { | |
1394 | int flags = d30v_operand_table[fm->operands[j]].flags; | |
7d515759 | 1395 | int bits = d30v_operand_table[fm->operands[j]].bits; |
9b1168d6 MH |
1396 | int X_op = myops[j].X_op; |
1397 | int num = myops[j].X_add_number; | |
1398 | ||
7d515759 | 1399 | if (flags & OPERAND_SPECIAL) |
9b1168d6 | 1400 | break; |
7d515759 | 1401 | else if (X_op == O_illegal) |
9b1168d6 MH |
1402 | match = 0; |
1403 | else if (flags & OPERAND_REG) | |
1404 | { | |
7d515759 | 1405 | if (X_op != O_register |
343b2ab8 MM |
1406 | || ((flags & OPERAND_ACC) && !(num & OPERAND_ACC)) |
1407 | || ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG)) | |
1408 | || ((flags & OPERAND_CONTROL) | |
1409 | && !(num & (OPERAND_CONTROL | OPERAND_FLAG)))) | |
9b1168d6 MH |
1410 | { |
1411 | match = 0; | |
9b1168d6 MH |
1412 | } |
1413 | } | |
7d515759 RH |
1414 | else if (((flags & OPERAND_MINUS) |
1415 | && (X_op != O_absent || num != OPERAND_MINUS)) | |
1416 | || ((flags & OPERAND_PLUS) | |
1417 | && (X_op != O_absent || num != OPERAND_PLUS)) | |
1418 | || ((flags & OPERAND_ATMINUS) | |
1419 | && (X_op != O_absent || num != OPERAND_ATMINUS)) | |
1420 | || ((flags & OPERAND_ATPAR) | |
1421 | && (X_op != O_absent || num != OPERAND_ATPAR)) | |
1422 | || ((flags & OPERAND_ATSIGN) | |
1423 | && (X_op != O_absent || num != OPERAND_ATSIGN))) | |
1424 | { | |
1425 | match=0; | |
1426 | } | |
1427 | else if (flags & OPERAND_NUM) | |
1428 | { | |
1429 | /* A number can be a constant or symbol expression. */ | |
1430 | ||
1431 | /* Turn an expression into a symbol for later resolution. */ | |
1432 | if (X_op != O_absent && X_op != O_constant | |
1433 | && X_op != O_symbol && X_op != O_register | |
1434 | && X_op != O_big) | |
1435 | { | |
1436 | symbolS *sym = make_expr_symbol (&myops[j]); | |
1437 | myops[j].X_op = X_op = O_symbol; | |
1438 | myops[j].X_add_symbol = sym; | |
1439 | myops[j].X_add_number = num = 0; | |
1440 | } | |
1441 | ||
1442 | if (fm->form >= LONG) | |
1443 | { | |
1444 | /* If we're testing for a LONG format, either fits. */ | |
1445 | if (X_op != O_constant && X_op != O_symbol) | |
1446 | match = 0; | |
1447 | } | |
1448 | else if (fm->form < LONG | |
1449 | && ((fsize == FORCE_SHORT && X_op == O_symbol) | |
1450 | || (fm->form == SHORT_D2 && j == 0))) | |
1451 | match = 1; | |
1452 | /* This is the tricky part. Will the constant or symbol | |
1453 | fit into the space in the current format? */ | |
1454 | else if (X_op == O_constant) | |
1455 | { | |
1456 | if (check_range (num, bits, flags)) | |
1457 | match = 0; | |
1458 | } | |
1459 | else if (X_op == O_symbol | |
1460 | && S_IS_DEFINED(myops[j].X_add_symbol) | |
1461 | && S_GET_SEGMENT(myops[j].X_add_symbol) == now_seg | |
1462 | && opcode->reloc_flag == RELOC_PCREL) | |
1463 | { | |
1464 | /* If the symbol is defined, see if the value will fit | |
1465 | into the form we're considering. */ | |
1466 | fragS *f; | |
1467 | long value; | |
1468 | ||
1469 | /* Calculate the current address by running through the | |
1470 | previous frags and adding our current offset. */ | |
1471 | value = 0; | |
1472 | for (f = frchain_now->frch_root; f; f = f->fr_next) | |
1473 | value += f->fr_fix + f->fr_offset; | |
1474 | value = (S_GET_VALUE(myops[j].X_add_symbol) - value | |
1475 | - (obstack_next_free(&frchain_now->frch_obstack) | |
1476 | - frag_now->fr_literal)); | |
1477 | if (check_range (value, bits, flags)) | |
1478 | match = 0; | |
1479 | } | |
1480 | else | |
1481 | match = 0; | |
1482 | } | |
9b1168d6 MH |
1483 | } |
1484 | /* printf("through the loop: match=%d\n",match); */ | |
7d515759 RH |
1485 | /* We're only done if the operands matched so far AND there |
1486 | are no more to check. */ | |
1487 | if (match && myops[j].X_op == 0) | |
9b1168d6 | 1488 | return fm; |
9b1168d6 MH |
1489 | fm = (struct d30v_format *)&d30v_format_table[++k]; |
1490 | } | |
1491 | /* printf("trying another format: i=%d\n",i); */ | |
1492 | } | |
1493 | return NULL; | |
1494 | } | |
1495 | ||
1496 | /* if while processing a fixup, a reloc really needs to be created */ | |
1497 | /* then it is done here */ | |
1498 | ||
1499 | arelent * | |
1500 | tc_gen_reloc (seg, fixp) | |
1501 | asection *seg; | |
1502 | fixS *fixp; | |
1503 | { | |
1504 | arelent *reloc; | |
2c268a85 | 1505 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
9b1168d6 MH |
1506 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; |
1507 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1508 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
9b1168d6 MH |
1509 | if (reloc->howto == (reloc_howto_type *) NULL) |
1510 | { | |
1511 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
48401fcf | 1512 | _("reloc %d not supported by object file format"), (int)fixp->fx_r_type); |
9b1168d6 MH |
1513 | return NULL; |
1514 | } | |
1515 | reloc->addend = fixp->fx_addnumber; | |
1516 | return reloc; | |
1517 | } | |
1518 | ||
1519 | int | |
1520 | md_estimate_size_before_relax (fragp, seg) | |
1521 | fragS *fragp; | |
1522 | asection *seg; | |
1523 | { | |
1524 | abort (); | |
1525 | return 0; | |
1526 | } | |
1527 | ||
1528 | long | |
1529 | md_pcrel_from_section (fixp, sec) | |
1530 | fixS *fixp; | |
1531 | segT sec; | |
1532 | { | |
e0882f34 MM |
1533 | if (fixp->fx_addsy != (symbolS *)NULL && (!S_IS_DEFINED (fixp->fx_addsy) || |
1534 | (S_GET_SEGMENT (fixp->fx_addsy) != sec))) | |
9b1168d6 MH |
1535 | return 0; |
1536 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
1537 | } | |
1538 | ||
1539 | int | |
1540 | md_apply_fix3 (fixp, valuep, seg) | |
1541 | fixS *fixp; | |
1542 | valueT *valuep; | |
1543 | segT seg; | |
1544 | { | |
1545 | char *where; | |
1546 | unsigned long insn, insn2; | |
1547 | long value; | |
9b1168d6 MH |
1548 | |
1549 | if (fixp->fx_addsy == (symbolS *) NULL) | |
1550 | { | |
1551 | value = *valuep; | |
1552 | fixp->fx_done = 1; | |
1553 | } | |
9b1168d6 MH |
1554 | else if (fixp->fx_pcrel) |
1555 | { | |
1556 | value = *valuep; | |
e0882f34 | 1557 | } |
1b524697 | 1558 | else |
9b1168d6 MH |
1559 | { |
1560 | value = fixp->fx_offset; | |
9b1168d6 MH |
1561 | if (fixp->fx_subsy != (symbolS *) NULL) |
1562 | { | |
e0882f34 | 1563 | if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section) |
9b1168d6 MH |
1564 | value -= S_GET_VALUE (fixp->fx_subsy); |
1565 | else | |
1566 | { | |
1567 | /* We don't actually support subtracting a symbol. */ | |
1b524697 | 1568 | as_bad_where (fixp->fx_file, fixp->fx_line, |
48401fcf | 1569 | _("expression too complex")); |
9b1168d6 MH |
1570 | } |
1571 | } | |
1572 | } | |
1573 | ||
1574 | /* Fetch the instruction, insert the fully resolved operand | |
1575 | value, and stuff the instruction back again. */ | |
1576 | where = fixp->fx_frag->fr_literal + fixp->fx_where; | |
1577 | insn = bfd_getb32 ((unsigned char *) where); | |
1b524697 | 1578 | |
9b1168d6 MH |
1579 | switch (fixp->fx_r_type) |
1580 | { | |
1581 | case BFD_RELOC_D30V_6: | |
e0882f34 | 1582 | check_size (value, 6, fixp->fx_file, fixp->fx_line); |
9b1168d6 MH |
1583 | insn |= value & 0x3F; |
1584 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1585 | break; | |
343b2ab8 | 1586 | |
e0882f34 MM |
1587 | case BFD_RELOC_D30V_9_PCREL: |
1588 | if (fixp->fx_where & 0x7) | |
1589 | { | |
1590 | if (fixp->fx_done) | |
1591 | value += 4; | |
1592 | else | |
1593 | fixp->fx_r_type = BFD_RELOC_D30V_9_PCREL_R; | |
1594 | } | |
1595 | check_size (value, 9, fixp->fx_file, fixp->fx_line); | |
1596 | insn |= ((value >> 3) & 0x3F) << 12; | |
1597 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1598 | break; | |
343b2ab8 | 1599 | |
9b1168d6 | 1600 | case BFD_RELOC_D30V_15: |
e0882f34 | 1601 | check_size (value, 15, fixp->fx_file, fixp->fx_line); |
9b1168d6 MH |
1602 | insn |= (value >> 3) & 0xFFF; |
1603 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1604 | break; | |
343b2ab8 | 1605 | |
9b1168d6 | 1606 | case BFD_RELOC_D30V_15_PCREL: |
e0882f34 MM |
1607 | if (fixp->fx_where & 0x7) |
1608 | { | |
1609 | if (fixp->fx_done) | |
1610 | value += 4; | |
1611 | else | |
1612 | fixp->fx_r_type = BFD_RELOC_D30V_15_PCREL_R; | |
1613 | } | |
1614 | check_size (value, 15, fixp->fx_file, fixp->fx_line); | |
9b1168d6 MH |
1615 | insn |= (value >> 3) & 0xFFF; |
1616 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1617 | break; | |
343b2ab8 | 1618 | |
9b1168d6 | 1619 | case BFD_RELOC_D30V_21: |
e0882f34 | 1620 | check_size (value, 21, fixp->fx_file, fixp->fx_line); |
9b1168d6 MH |
1621 | insn |= (value >> 3) & 0x3FFFF; |
1622 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1623 | break; | |
343b2ab8 | 1624 | |
9b1168d6 | 1625 | case BFD_RELOC_D30V_21_PCREL: |
e0882f34 MM |
1626 | if (fixp->fx_where & 0x7) |
1627 | { | |
1628 | if (fixp->fx_done) | |
1629 | value += 4; | |
1630 | else | |
1631 | fixp->fx_r_type = BFD_RELOC_D30V_21_PCREL_R; | |
1632 | } | |
1633 | check_size (value, 21, fixp->fx_file, fixp->fx_line); | |
9b1168d6 MH |
1634 | insn |= (value >> 3) & 0x3FFFF; |
1635 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1636 | break; | |
343b2ab8 | 1637 | |
9b1168d6 MH |
1638 | case BFD_RELOC_D30V_32: |
1639 | insn2 = bfd_getb32 ((unsigned char *) where + 4); | |
343b2ab8 MM |
1640 | insn |= (value >> 26) & 0x3F; /* top 6 bits */ |
1641 | insn2 |= ((value & 0x03FC0000) << 2); /* next 8 bits */ | |
9b1168d6 MH |
1642 | insn2 |= value & 0x0003FFFF; /* bottom 18 bits */ |
1643 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1644 | bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4); | |
1645 | break; | |
343b2ab8 | 1646 | |
9b1168d6 | 1647 | case BFD_RELOC_D30V_32_PCREL: |
9b1168d6 | 1648 | insn2 = bfd_getb32 ((unsigned char *) where + 4); |
343b2ab8 MM |
1649 | insn |= (value >> 26) & 0x3F; /* top 6 bits */ |
1650 | insn2 |= ((value & 0x03FC0000) << 2); /* next 8 bits */ | |
9b1168d6 MH |
1651 | insn2 |= value & 0x0003FFFF; /* bottom 18 bits */ |
1652 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1653 | bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4); | |
1654 | break; | |
343b2ab8 | 1655 | |
9b1168d6 | 1656 | case BFD_RELOC_32: |
9b1168d6 MH |
1657 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); |
1658 | break; | |
343b2ab8 | 1659 | |
9b1168d6 | 1660 | default: |
48401fcf | 1661 | as_fatal (_("line %d: unknown relocation type: 0x%x"),fixp->fx_line,fixp->fx_r_type); |
9b1168d6 | 1662 | } |
9b1168d6 MH |
1663 | return 0; |
1664 | } | |
1665 | ||
1666 | ||
1667 | /* d30v_cleanup() is called after the assembler has finished parsing the input | |
1668 | file or after a label is defined. Because the D30V assembler sometimes saves short | |
1669 | instructions to see if it can package them with the next instruction, there may | |
1670 | be a short instruction that still needs written. */ | |
1671 | int | |
1672 | d30v_cleanup () | |
1673 | { | |
1674 | segT seg; | |
1675 | subsegT subseg; | |
1676 | ||
1677 | if (prev_insn != -1) | |
1678 | { | |
1679 | seg = now_seg; | |
1680 | subseg = now_subseg; | |
1681 | subseg_set (prev_seg, prev_subseg); | |
1682 | write_1_short (&prev_opcode, (long)prev_insn, fixups->next); | |
1683 | subseg_set (seg, subseg); | |
1684 | prev_insn = -1; | |
1685 | } | |
1686 | return 1; | |
1687 | } | |
1688 | ||
9b1168d6 MH |
1689 | static void |
1690 | d30v_number_to_chars (buf, value, n) | |
1691 | char *buf; /* Return 'nbytes' of chars here. */ | |
1692 | long long value; /* The value of the bits. */ | |
1693 | int n; /* Number of bytes in the output. */ | |
1694 | { | |
1695 | while (n--) | |
1696 | { | |
1697 | buf[n] = value & 0xff; | |
1698 | value >>= 8; | |
1699 | } | |
1700 | } | |
e0882f34 MM |
1701 | |
1702 | ||
1703 | /* This function is called at the start of every line. */ | |
1704 | /* it checks to see if the first character is a '.' */ | |
1705 | /* which indicates the start of a pseudo-op. If it is, */ | |
1706 | /* then write out any unwritten instructions */ | |
1707 | ||
1708 | void | |
1709 | d30v_start_line() | |
1710 | { | |
1711 | char *c = input_line_pointer; | |
1712 | ||
1713 | while(isspace(*c)) | |
1714 | c++; | |
1715 | ||
1716 | if (*c == '.') | |
1717 | d30v_cleanup(); | |
1718 | } | |
1719 | ||
1720 | static void | |
1721 | check_size (value, bits, file, line) | |
1722 | long value; | |
1723 | int bits; | |
1724 | char *file; | |
1725 | int line; | |
1726 | { | |
1727 | int tmp, max; | |
1728 | ||
1729 | if (value < 0) | |
1730 | tmp = ~value; | |
1731 | else | |
1732 | tmp = value; | |
1733 | ||
1734 | max = (1 << (bits - 1)) - 1; | |
1735 | ||
1736 | if (tmp > max) | |
7d515759 | 1737 | as_bad_where (file, line, _("value too large to fit in %d bits"), bits); |
e0882f34 MM |
1738 | |
1739 | return; | |
1740 | } | |
7d515759 RH |
1741 | |
1742 | /* d30v_frob_label() is called when after a label is recognized. */ | |
1743 | ||
1744 | void | |
1745 | d30v_frob_label (lab) | |
1746 | symbolS *lab; | |
1747 | { | |
1748 | /* Emit any pending instructions. */ | |
1749 | d30v_cleanup(); | |
1750 | ||
1751 | /* Update the label's address with the current output pointer. */ | |
1752 | lab->sy_frag = frag_now; | |
1753 | S_SET_VALUE (lab, (valueT) frag_now_fix ()); | |
1754 | ||
1755 | /* Record this label for future adjustment after we find out what | |
1756 | kind of data it references, and the required alignment therewith. */ | |
1757 | d30v_last_label = lab; | |
1758 | } | |
1759 | ||
1760 | /* Hook into cons for capturing alignment changes. */ | |
1761 | ||
1762 | void | |
1763 | d30v_cons_align (size) | |
1764 | int size; | |
1765 | { | |
1766 | int log_size; | |
1767 | ||
1768 | log_size = 0; | |
1769 | while ((size >>= 1) != 0) | |
1770 | ++log_size; | |
1771 | ||
1772 | if (d30v_current_align < log_size) | |
1773 | d30v_align (log_size, (char *) NULL, NULL); | |
1774 | else if (d30v_current_align > log_size) | |
1775 | d30v_current_align = log_size; | |
1776 | d30v_last_label = NULL; | |
1777 | } | |
1778 | ||
1779 | /* Called internally to handle all alignment needs. This takes care | |
1780 | of eliding calls to frag_align if'n the cached current alignment | |
1781 | says we've already got it, as well as taking care of the auto-aligning | |
1782 | labels wrt code. */ | |
1783 | ||
1784 | static void | |
1785 | d30v_align (n, pfill, label) | |
1786 | int n; | |
1787 | char *pfill; | |
1788 | symbolS *label; | |
1789 | { | |
1790 | /* The front end is prone to changing segments out from under us | |
1791 | temporarily when -g is in effect. */ | |
1792 | int switched_seg_p = (d30v_current_align_seg != now_seg); | |
1793 | ||
1794 | if (d30v_current_align >= n && !switched_seg_p) | |
1795 | return; | |
1796 | ||
1797 | d30v_cleanup(); | |
1798 | ||
1799 | if (pfill == NULL) | |
1800 | { | |
1801 | if (n > 2 | |
1802 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
1803 | { | |
1804 | static char const nop[4] = { 0x00, 0xf0, 0x00, 0x00 }; | |
1805 | ||
1806 | /* First, make sure we're on a four-byte boundary, in case | |
1807 | someone has been putting .byte values the text section. */ | |
1808 | if (d30v_current_align < 2 || switched_seg_p) | |
1809 | frag_align (2, 0, 0); | |
1810 | frag_align_pattern (n, nop, sizeof nop, 0); | |
1811 | } | |
1812 | else | |
1813 | frag_align (n, 0, 0); | |
1814 | } | |
1815 | else | |
1816 | frag_align (n, *pfill, 0); | |
1817 | ||
1818 | if (!switched_seg_p) | |
1819 | d30v_current_align = n; | |
1820 | ||
1821 | if (label != NULL) | |
1822 | { | |
1823 | assert (S_GET_SEGMENT (label) == now_seg); | |
1824 | label->sy_frag = frag_now; | |
1825 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
1826 | } | |
1827 | ||
1828 | record_alignment(now_seg, n); | |
1829 | } | |
1830 | ||
1831 | /* Handle the .align pseudo-op. This aligns to a power of two. We | |
1832 | hook here to latch the current alignment. */ | |
1833 | ||
1834 | static void | |
1835 | s_d30v_align (ignore) | |
1836 | int ignore; | |
1837 | { | |
1838 | int align; | |
1839 | char fill, *pfill = NULL; | |
1840 | long max_alignment = 15; | |
1841 | ||
1842 | align = get_absolute_expression (); | |
1843 | if (align > max_alignment) | |
1844 | { | |
1845 | align = max_alignment; | |
1846 | as_warn (_("Alignment too large: %d assumed"), align); | |
1847 | } | |
1848 | else if (align < 0) | |
1849 | { | |
1850 | as_warn (_("Alignment negative: 0 assumed")); | |
1851 | align = 0; | |
1852 | } | |
1853 | ||
1854 | if (*input_line_pointer == ',') | |
1855 | { | |
1856 | input_line_pointer++; | |
1857 | fill = get_absolute_expression (); | |
1858 | pfill = &fill; | |
1859 | } | |
1860 | ||
1861 | d30v_last_label = NULL; | |
1862 | d30v_align (align, pfill, NULL); | |
1863 | ||
1864 | demand_empty_rest_of_line (); | |
1865 | } | |
1866 | ||
1867 | /* Handle the .text pseudo-op. This is like the usual one, but it | |
1868 | clears the saved last label and resets known alignment. */ | |
1869 | ||
1870 | static void | |
1871 | s_d30v_text (i) | |
1872 | int i; | |
1873 | ||
1874 | { | |
1875 | s_text (i); | |
1876 | d30v_last_label = NULL; | |
1877 | d30v_current_align = 0; | |
1878 | d30v_current_align_seg = now_seg; | |
1879 | } | |
1880 | ||
1881 | /* Handle the .data pseudo-op. This is like the usual one, but it | |
1882 | clears the saved last label and resets known alignment. */ | |
1883 | ||
1884 | static void | |
1885 | s_d30v_data (i) | |
1886 | int i; | |
1887 | { | |
1888 | s_data (i); | |
1889 | d30v_last_label = NULL; | |
1890 | d30v_current_align = 0; | |
1891 | d30v_current_align_seg = now_seg; | |
1892 | } | |
1893 | ||
1894 | /* Handle the .section pseudo-op. This is like the usual one, but it | |
1895 | clears the saved last label and resets known alignment. */ | |
1896 | ||
1897 | static void | |
1898 | s_d30v_section (ignore) | |
1899 | int ignore; | |
1900 | { | |
1901 | obj_elf_section (ignore); | |
1902 | d30v_last_label = NULL; | |
1903 | d30v_current_align = 0; | |
1904 | d30v_current_align_seg = now_seg; | |
1905 | } |