Commit | Line | Data |
---|---|---|
9b1168d6 MH |
1 | /* tc-d30v.c -- Assembler code for the Mitsubishi D30V |
2 | ||
3 | Copyright (C) 1997 Free Software Foundation. | |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include <stdio.h> | |
23 | #include <ctype.h> | |
24 | #include "as.h" | |
25 | #include "subsegs.h" | |
26 | #include "opcode/d30v.h" | |
27 | ||
28 | const char comment_chars[] = ";"; | |
29 | const char line_comment_chars[] = "#"; | |
30 | const char line_separator_chars[] = ""; | |
343b2ab8 | 31 | const char *md_shortopts = "OnN"; |
9b1168d6 MH |
32 | const char EXP_CHARS[] = "eE"; |
33 | const char FLT_CHARS[] = "dD"; | |
34 | ||
343b2ab8 MM |
35 | #define NOP_MULTIPLY 1 |
36 | #define NOP_ALL 2 | |
37 | static int warn_nops = 0; | |
38 | static int Optimizing = 0; | |
9b1168d6 | 39 | |
e0882f34 MM |
40 | #define FORCE_SHORT 1 |
41 | #define FORCE_LONG 2 | |
42 | ||
343b2ab8 MM |
43 | /* EXEC types. */ |
44 | typedef enum _exec_type | |
45 | { | |
46 | EXEC_UNKNOWN, /* no order specified */ | |
47 | EXEC_PARALLEL, /* done in parallel */ | |
48 | EXEC_SEQ, /* sequential */ | |
49 | EXEC_REVSEQ /* reverse sequential */ | |
50 | } exec_type_enum; | |
51 | ||
9b1168d6 MH |
52 | /* fixups */ |
53 | #define MAX_INSN_FIXUPS (5) | |
54 | struct d30v_fixup | |
55 | { | |
56 | expressionS exp; | |
57 | int operand; | |
58 | int pcrel; | |
59 | int size; | |
60 | bfd_reloc_code_real_type reloc; | |
61 | }; | |
62 | ||
63 | typedef struct _fixups | |
64 | { | |
65 | int fc; | |
66 | struct d30v_fixup fix[MAX_INSN_FIXUPS]; | |
67 | struct _fixups *next; | |
68 | } Fixups; | |
69 | ||
70 | static Fixups FixUps[2]; | |
71 | static Fixups *fixups; | |
72 | ||
343b2ab8 MM |
73 | /* Whether current and previous instruction is a word multiply. */ |
74 | int cur_mul32_p = 0; | |
75 | int prev_mul32_p = 0; | |
76 | ||
77 | /* Two nops */ | |
78 | #define NOP_LEFT ((long long)NOP << 32) | |
79 | #define NOP_RIGHT ((long long)NOP) | |
80 | #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT) | |
81 | ||
9b1168d6 MH |
82 | /* local functions */ |
83 | static int reg_name_search PARAMS ((char *name)); | |
84 | static int register_name PARAMS ((expressionS *expressionP)); | |
85 | static int check_range PARAMS ((unsigned long num, int bits, int flags)); | |
86 | static int postfix PARAMS ((char *p)); | |
87 | static bfd_reloc_code_real_type get_reloc PARAMS ((struct d30v_operand *op, int rel_flag)); | |
88 | static int get_operands PARAMS ((expressionS exp[], int cmp_hack)); | |
e0882f34 MM |
89 | static struct d30v_format *find_format PARAMS ((struct d30v_opcode *opcode, |
90 | expressionS ops[],int fsize, int cmp_hack)); | |
9b1168d6 MH |
91 | static long long build_insn PARAMS ((struct d30v_insn *opcode, expressionS *opers)); |
92 | static void write_long PARAMS ((struct d30v_insn *opcode, long long insn, Fixups *fx)); | |
93 | static void write_1_short PARAMS ((struct d30v_insn *opcode, long long insn, Fixups *fx)); | |
94 | static int write_2_short PARAMS ((struct d30v_insn *opcode1, long long insn1, | |
343b2ab8 | 95 | struct d30v_insn *opcode2, long long insn2, exec_type_enum exec_type, Fixups *fx)); |
9b1168d6 | 96 | static long long do_assemble PARAMS ((char *str, struct d30v_insn *opcode)); |
9b1168d6 MH |
97 | static int parallel_ok PARAMS ((struct d30v_insn *opcode1, unsigned long insn1, |
98 | struct d30v_insn *opcode2, unsigned long insn2, | |
343b2ab8 | 99 | exec_type_enum exec_type)); |
9b1168d6 | 100 | static void d30v_number_to_chars PARAMS ((char *buf, long long value, int nbytes)); |
e0882f34 | 101 | static void check_size PARAMS ((long value, int bits, char *file, int line)); |
9b1168d6 MH |
102 | |
103 | struct option md_longopts[] = { | |
104 | {NULL, no_argument, NULL, 0} | |
105 | }; | |
106 | size_t md_longopts_size = sizeof(md_longopts); | |
107 | ||
108 | ||
109 | /* The target specific pseudo-ops which we support. */ | |
110 | const pseudo_typeS md_pseudo_table[] = | |
111 | { | |
e0882f34 MM |
112 | { "word", cons, 4 }, |
113 | { "hword", cons, 2 }, | |
114 | { NULL, NULL, 0 } | |
9b1168d6 MH |
115 | }; |
116 | ||
117 | /* Opcode hash table. */ | |
118 | static struct hash_control *d30v_hash; | |
119 | ||
120 | /* reg_name_search does a binary search of the pre_defined_registers | |
121 | array to see if "name" is a valid regiter name. Returns the register | |
122 | number from the array on success, or -1 on failure. */ | |
123 | ||
124 | static int | |
125 | reg_name_search (name) | |
126 | char *name; | |
127 | { | |
128 | int middle, low, high; | |
129 | int cmp; | |
130 | ||
131 | low = 0; | |
132 | high = reg_name_cnt() - 1; | |
133 | ||
134 | do | |
135 | { | |
136 | middle = (low + high) / 2; | |
137 | cmp = strcasecmp (name, pre_defined_registers[middle].name); | |
138 | if (cmp < 0) | |
139 | high = middle - 1; | |
140 | else if (cmp > 0) | |
141 | low = middle + 1; | |
142 | else | |
143 | return pre_defined_registers[middle].value; | |
144 | } | |
145 | while (low <= high); | |
146 | return -1; | |
147 | } | |
148 | ||
149 | /* register_name() checks the string at input_line_pointer | |
150 | to see if it is a valid register name */ | |
151 | ||
152 | static int | |
153 | register_name (expressionP) | |
154 | expressionS *expressionP; | |
155 | { | |
156 | int reg_number; | |
157 | char c, *p = input_line_pointer; | |
158 | ||
159 | while (*p && *p!='\n' && *p!='\r' && *p !=',' && *p!=' ' && *p!=')') | |
160 | p++; | |
161 | ||
162 | c = *p; | |
163 | if (c) | |
164 | *p++ = 0; | |
165 | ||
166 | /* look to see if it's in the register table */ | |
167 | reg_number = reg_name_search (input_line_pointer); | |
168 | if (reg_number >= 0) | |
169 | { | |
170 | expressionP->X_op = O_register; | |
171 | /* temporarily store a pointer to the string here */ | |
172 | expressionP->X_op_symbol = (struct symbol *)input_line_pointer; | |
173 | expressionP->X_add_number = reg_number; | |
174 | input_line_pointer = p; | |
175 | return 1; | |
176 | } | |
177 | if (c) | |
178 | *(p-1) = c; | |
179 | return 0; | |
180 | } | |
181 | ||
182 | ||
183 | static int | |
184 | check_range (num, bits, flags) | |
185 | unsigned long num; | |
186 | int bits; | |
187 | int flags; | |
188 | { | |
343b2ab8 | 189 | long min, max; |
9b1168d6 MH |
190 | int retval=0; |
191 | ||
192 | /* don't bother checking 32-bit values */ | |
193 | if (bits == 32) | |
194 | return 0; | |
195 | ||
196 | if (flags & OPERAND_SIGNED) | |
197 | { | |
198 | max = (1 << (bits - 1))-1; | |
e0882f34 | 199 | min = - (1 << (bits - 1)); |
9b1168d6 MH |
200 | if (((long)num > max) || ((long)num < min)) |
201 | retval = 1; | |
202 | } | |
203 | else | |
204 | { | |
205 | max = (1 << bits) - 1; | |
206 | min = 0; | |
207 | if ((num > max) || (num < min)) | |
208 | retval = 1; | |
209 | } | |
210 | return retval; | |
211 | } | |
212 | ||
213 | ||
214 | void | |
215 | md_show_usage (stream) | |
216 | FILE *stream; | |
217 | { | |
343b2ab8 MM |
218 | fprintf(stream, "\nD30V options:\n\ |
219 | -O Make adjacent short instructions parallel if possible.\n\ | |
220 | -n Warn about all NOPs inserted by the assembler.\n\ | |
221 | -N Warn about NOPs inserted after word multiplies.\n"); | |
9b1168d6 MH |
222 | } |
223 | ||
224 | int | |
225 | md_parse_option (c, arg) | |
226 | int c; | |
227 | char *arg; | |
228 | { | |
229 | switch (c) | |
230 | { | |
9b1168d6 | 231 | /* Optimize. Will attempt to parallelize operations */ |
343b2ab8 | 232 | case 'O': |
9b1168d6 MH |
233 | Optimizing = 1; |
234 | break; | |
343b2ab8 MM |
235 | |
236 | /* Warn about all NOPS that the assembler inserts. */ | |
237 | case 'n': | |
238 | warn_nops = NOP_ALL; | |
239 | break; | |
240 | ||
241 | /* Warn about the NOPS that the assembler inserts because of the | |
242 | multiply hazard. */ | |
243 | case 'N': | |
244 | warn_nops = NOP_MULTIPLY; | |
245 | break; | |
246 | ||
9b1168d6 MH |
247 | default: |
248 | return 0; | |
249 | } | |
250 | return 1; | |
251 | } | |
252 | ||
253 | symbolS * | |
254 | md_undefined_symbol (name) | |
255 | char *name; | |
256 | { | |
257 | return 0; | |
258 | } | |
259 | ||
260 | /* Turn a string in input_line_pointer into a floating point constant of type | |
261 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
262 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
263 | */ | |
264 | char * | |
265 | md_atof (type, litP, sizeP) | |
266 | int type; | |
267 | char *litP; | |
268 | int *sizeP; | |
269 | { | |
270 | int prec; | |
271 | LITTLENUM_TYPE words[4]; | |
272 | char *t; | |
273 | int i; | |
274 | ||
275 | switch (type) | |
276 | { | |
277 | case 'f': | |
278 | prec = 2; | |
279 | break; | |
280 | case 'd': | |
281 | prec = 4; | |
282 | break; | |
283 | default: | |
284 | *sizeP = 0; | |
285 | return "bad call to md_atof"; | |
286 | } | |
287 | ||
288 | t = atof_ieee (input_line_pointer, type, words); | |
289 | if (t) | |
290 | input_line_pointer = t; | |
291 | ||
292 | *sizeP = prec * 2; | |
293 | ||
294 | for (i = 0; i < prec; i++) | |
295 | { | |
296 | md_number_to_chars (litP, (valueT) words[i], 2); | |
297 | litP += 2; | |
298 | } | |
299 | return NULL; | |
300 | } | |
301 | ||
302 | void | |
303 | md_convert_frag (abfd, sec, fragP) | |
304 | bfd *abfd; | |
305 | asection *sec; | |
306 | fragS *fragP; | |
307 | { | |
308 | abort (); | |
309 | } | |
310 | ||
311 | valueT | |
312 | md_section_align (seg, addr) | |
313 | asection *seg; | |
314 | valueT addr; | |
315 | { | |
316 | int align = bfd_get_section_alignment (stdoutput, seg); | |
317 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
318 | } | |
319 | ||
320 | ||
321 | void | |
322 | md_begin () | |
323 | { | |
324 | struct d30v_opcode *opcode; | |
325 | d30v_hash = hash_new(); | |
326 | ||
327 | /* Insert opcode names into a hash table. */ | |
328 | for (opcode = (struct d30v_opcode *)d30v_opcode_table; opcode->name; opcode++) | |
329 | hash_insert (d30v_hash, opcode->name, (char *) opcode); | |
330 | ||
331 | fixups = &FixUps[0]; | |
332 | FixUps[0].next = &FixUps[1]; | |
333 | FixUps[1].next = &FixUps[0]; | |
334 | } | |
335 | ||
336 | ||
337 | /* this function removes the postincrement or postdecrement | |
338 | operator ( '+' or '-' ) from an expression */ | |
339 | ||
340 | static int postfix (p) | |
341 | char *p; | |
342 | { | |
343 | while (*p != '-' && *p != '+') | |
344 | { | |
2c268a85 | 345 | if (*p==0 || *p=='\n' || *p=='\r' || *p==' ' || *p==',') |
9b1168d6 MH |
346 | break; |
347 | p++; | |
348 | } | |
349 | ||
350 | if (*p == '-') | |
351 | { | |
352 | *p = ' '; | |
353 | return (-1); | |
354 | } | |
355 | if (*p == '+') | |
356 | { | |
357 | *p = ' '; | |
358 | return (1); | |
359 | } | |
360 | ||
361 | return (0); | |
362 | } | |
363 | ||
364 | ||
365 | static bfd_reloc_code_real_type | |
366 | get_reloc (op, rel_flag) | |
367 | struct d30v_operand *op; | |
368 | int rel_flag; | |
369 | { | |
370 | switch (op->bits) | |
371 | { | |
372 | case 6: | |
e0882f34 MM |
373 | if (op->flags & OPERAND_SHIFT) |
374 | return BFD_RELOC_D30V_9_PCREL; | |
375 | else | |
376 | return BFD_RELOC_D30V_6; | |
377 | break; | |
9b1168d6 MH |
378 | case 12: |
379 | if (!(op->flags & OPERAND_SHIFT)) | |
380 | as_warn("unexpected 12-bit reloc type"); | |
381 | if (rel_flag == RELOC_PCREL) | |
382 | return BFD_RELOC_D30V_15_PCREL; | |
383 | else | |
384 | return BFD_RELOC_D30V_15; | |
385 | case 18: | |
386 | if (!(op->flags & OPERAND_SHIFT)) | |
387 | as_warn("unexpected 18-bit reloc type"); | |
388 | if (rel_flag == RELOC_PCREL) | |
389 | return BFD_RELOC_D30V_21_PCREL; | |
390 | else | |
391 | return BFD_RELOC_D30V_21; | |
392 | case 32: | |
393 | if (rel_flag == RELOC_PCREL) | |
394 | return BFD_RELOC_D30V_32_PCREL; | |
395 | else | |
396 | return BFD_RELOC_D30V_32; | |
397 | default: | |
398 | return 0; | |
399 | } | |
400 | } | |
401 | ||
402 | /* get_operands parses a string of operands and returns | |
403 | an array of expressions */ | |
404 | ||
405 | static int | |
406 | get_operands (exp, cmp_hack) | |
407 | expressionS exp[]; | |
408 | int cmp_hack; | |
409 | { | |
410 | char *p = input_line_pointer; | |
411 | int numops = 0; | |
412 | int post = 0; | |
413 | ||
414 | if (cmp_hack) | |
415 | { | |
416 | exp[numops].X_op = O_absent; | |
417 | exp[numops++].X_add_number = cmp_hack - 1; | |
418 | } | |
419 | ||
420 | while (*p) | |
421 | { | |
422 | while (*p == ' ' || *p == '\t' || *p == ',') | |
423 | p++; | |
424 | if (*p==0 || *p=='\n' || *p=='\r') | |
425 | break; | |
426 | ||
427 | if (*p == '@') | |
428 | { | |
429 | p++; | |
430 | exp[numops].X_op = O_absent; | |
431 | if (*p == '(') | |
432 | { | |
433 | p++; | |
434 | exp[numops].X_add_number = OPERAND_ATPAR; | |
435 | post = postfix (p); | |
436 | } | |
437 | else if (*p == '-') | |
438 | { | |
439 | p++; | |
440 | exp[numops].X_add_number = OPERAND_ATMINUS; | |
441 | } | |
442 | else | |
443 | { | |
444 | exp[numops].X_add_number = OPERAND_ATSIGN; | |
445 | post = postfix (p); | |
446 | } | |
447 | numops++; | |
448 | continue; | |
449 | } | |
450 | ||
451 | if (*p == ')') | |
452 | { | |
453 | /* just skip the trailing paren */ | |
454 | p++; | |
455 | continue; | |
456 | } | |
457 | ||
458 | input_line_pointer = p; | |
459 | ||
460 | /* check to see if it might be a register name */ | |
461 | if (!register_name (&exp[numops])) | |
462 | { | |
463 | /* parse as an expression */ | |
464 | expression (&exp[numops]); | |
465 | } | |
466 | ||
467 | if (exp[numops].X_op == O_illegal) | |
468 | as_bad ("illegal operand"); | |
469 | else if (exp[numops].X_op == O_absent) | |
470 | as_bad ("missing operand"); | |
471 | ||
472 | numops++; | |
473 | p = input_line_pointer; | |
474 | ||
475 | switch (post) | |
476 | { | |
477 | case -1: /* postdecrement mode */ | |
478 | exp[numops].X_op = O_absent; | |
479 | exp[numops++].X_add_number = OPERAND_MINUS; | |
480 | break; | |
481 | case 1: /* postincrement mode */ | |
482 | exp[numops].X_op = O_absent; | |
483 | exp[numops++].X_add_number = OPERAND_PLUS; | |
484 | break; | |
485 | } | |
486 | post = 0; | |
487 | } | |
488 | ||
489 | exp[numops].X_op = 0; | |
490 | return (numops); | |
491 | } | |
492 | ||
9b1168d6 MH |
493 | /* build_insn generates the instruction. It does everything */ |
494 | /* but write the FM bits. */ | |
495 | ||
496 | static long long | |
497 | build_insn (opcode, opers) | |
498 | struct d30v_insn *opcode; | |
499 | expressionS *opers; | |
500 | { | |
343b2ab8 | 501 | int i, length, bits, shift, flags; |
9b1168d6 MH |
502 | unsigned int number, id=0; |
503 | long long insn; | |
504 | struct d30v_opcode *op = opcode->op; | |
505 | struct d30v_format *form = opcode->form; | |
506 | ||
9b1168d6 | 507 | insn = opcode->ecc << 28 | op->op1 << 25 | op->op2 << 20 | form->modifier << 18; |
e0882f34 | 508 | |
9b1168d6 MH |
509 | for (i=0; form->operands[i]; i++) |
510 | { | |
511 | flags = d30v_operand_table[form->operands[i]].flags; | |
512 | ||
9b1168d6 MH |
513 | /* must be a register or number */ |
514 | if (!(flags & OPERAND_REG) && !(flags & OPERAND_NUM) && | |
515 | !(flags & OPERAND_NAME) && !(flags & OPERAND_SPECIAL)) | |
516 | continue; | |
517 | ||
518 | bits = d30v_operand_table[form->operands[i]].bits; | |
e0882f34 MM |
519 | if (flags & OPERAND_SHIFT) |
520 | bits += 3; | |
521 | ||
9b1168d6 MH |
522 | length = d30v_operand_table[form->operands[i]].length; |
523 | shift = 12 - d30v_operand_table[form->operands[i]].position; | |
e0882f34 MM |
524 | if (opers[i].X_op != O_symbol) |
525 | number = opers[i].X_add_number; | |
526 | else | |
527 | number = 0; | |
9b1168d6 MH |
528 | if (flags & OPERAND_REG) |
529 | { | |
e0882f34 MM |
530 | /* check for mvfsys or mvtsys control registers */ |
531 | if (flags & OPERAND_CONTROL && (number & 0x7f) > MAX_CONTROL_REG) | |
9b1168d6 MH |
532 | { |
533 | /* PSWL or PSWH */ | |
e0882f34 MM |
534 | id = (number & 0x7f) - MAX_CONTROL_REG; |
535 | number = 0; | |
9b1168d6 MH |
536 | } |
537 | else if (number & OPERAND_FLAG) | |
538 | { | |
539 | id = 3; /* number is a flag register */ | |
540 | } | |
e0882f34 | 541 | number &= 0x7F; |
9b1168d6 MH |
542 | } |
543 | else if (flags & OPERAND_SPECIAL) | |
544 | { | |
545 | number = id; | |
546 | } | |
9b1168d6 MH |
547 | |
548 | if (opers[i].X_op != O_register && opers[i].X_op != O_constant && !(flags & OPERAND_NAME)) | |
549 | { | |
550 | /* now create a fixup */ | |
551 | ||
552 | if (fixups->fc >= MAX_INSN_FIXUPS) | |
553 | as_fatal ("too many fixups"); | |
554 | ||
555 | fixups->fix[fixups->fc].reloc = | |
556 | get_reloc((struct d30v_operand *)&d30v_operand_table[form->operands[i]], op->reloc_flag); | |
557 | fixups->fix[fixups->fc].size = 4; | |
558 | fixups->fix[fixups->fc].exp = opers[i]; | |
559 | fixups->fix[fixups->fc].operand = form->operands[i]; | |
e0882f34 MM |
560 | if (fixups->fix[fixups->fc].reloc == BFD_RELOC_D30V_9_PCREL) |
561 | fixups->fix[fixups->fc].pcrel = RELOC_PCREL; | |
562 | else | |
563 | fixups->fix[fixups->fc].pcrel = op->reloc_flag; | |
9b1168d6 MH |
564 | (fixups->fc)++; |
565 | } | |
566 | ||
567 | /* truncate to the proper number of bits */ | |
2c268a85 | 568 | if ((opers[i].X_op == O_constant) && check_range (number, bits, flags)) |
9b1168d6 | 569 | as_bad("operand out of range: %d",number); |
2c268a85 | 570 | if (bits < 31) |
9b1168d6 | 571 | number &= 0x7FFFFFFF >> (31 - bits); |
e0882f34 MM |
572 | if (flags & OPERAND_SHIFT) |
573 | number >>= 3; | |
9b1168d6 MH |
574 | if (bits == 32) |
575 | { | |
576 | /* it's a LONG instruction */ | |
577 | insn |= (number >> 26); /* top 6 bits */ | |
578 | insn <<= 32; /* shift the first word over */ | |
579 | insn |= ((number & 0x03FC0000) << 2); /* next 8 bits */ | |
580 | insn |= number & 0x0003FFFF; /* bottom 18 bits */ | |
581 | } | |
582 | else | |
583 | insn |= number << shift; | |
584 | } | |
585 | return insn; | |
586 | } | |
587 | ||
588 | ||
589 | /* write out a long form instruction */ | |
590 | static void | |
591 | write_long (opcode, insn, fx) | |
592 | struct d30v_insn *opcode; | |
593 | long long insn; | |
594 | Fixups *fx; | |
595 | { | |
596 | int i, where; | |
597 | char *f = frag_more(8); | |
598 | ||
599 | insn |= FM11; | |
600 | d30v_number_to_chars (f, insn, 8); | |
601 | ||
602 | for (i=0; i < fx->fc; i++) | |
603 | { | |
604 | if (fx->fix[i].reloc) | |
605 | { | |
606 | where = f - frag_now->fr_literal; | |
9b1168d6 MH |
607 | fix_new_exp (frag_now, |
608 | where, | |
609 | fx->fix[i].size, | |
610 | &(fx->fix[i].exp), | |
611 | fx->fix[i].pcrel, | |
612 | fx->fix[i].reloc); | |
613 | } | |
614 | } | |
615 | fx->fc = 0; | |
616 | } | |
617 | ||
618 | ||
619 | /* write out a short form instruction by itself */ | |
620 | static void | |
621 | write_1_short (opcode, insn, fx) | |
622 | struct d30v_insn *opcode; | |
623 | long long insn; | |
624 | Fixups *fx; | |
625 | { | |
626 | char *f = frag_more(8); | |
627 | int i, where; | |
628 | ||
343b2ab8 MM |
629 | if (warn_nops == NOP_ALL) |
630 | as_warn ("NOP inserted"); | |
631 | ||
9b1168d6 MH |
632 | /* the other container needs to be NOP */ |
633 | /* according to 4.3.1: for FM=00, sub-instructions performed only | |
634 | by IU cannot be encoded in L-container. */ | |
635 | if (opcode->op->unit == IU) | |
343b2ab8 | 636 | insn |= FM00 | NOP_LEFT; /* right container */ |
9b1168d6 | 637 | else |
343b2ab8 | 638 | insn = FM00 | (insn << 32) | NOP_RIGHT; /* left container */ |
9b1168d6 MH |
639 | |
640 | d30v_number_to_chars (f, insn, 8); | |
641 | ||
642 | for (i=0; i < fx->fc; i++) | |
643 | { | |
644 | if (fx->fix[i].reloc) | |
645 | { | |
646 | where = f - frag_now->fr_literal; | |
9b1168d6 MH |
647 | fix_new_exp (frag_now, |
648 | where, | |
649 | fx->fix[i].size, | |
650 | &(fx->fix[i].exp), | |
651 | fx->fix[i].pcrel, | |
652 | fx->fix[i].reloc); | |
653 | } | |
654 | } | |
655 | fx->fc = 0; | |
656 | } | |
657 | ||
658 | /* write out a short form instruction if possible */ | |
659 | /* return number of instructions not written out */ | |
660 | static int | |
661 | write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx) | |
662 | struct d30v_insn *opcode1, *opcode2; | |
663 | long long insn1, insn2; | |
343b2ab8 | 664 | exec_type_enum exec_type; |
9b1168d6 MH |
665 | Fixups *fx; |
666 | { | |
343b2ab8 | 667 | long long insn = NOP2; |
9b1168d6 MH |
668 | char *f; |
669 | int i,j, where; | |
670 | ||
343b2ab8 | 671 | if(exec_type != EXEC_PARALLEL && (opcode1->op->flags_used == FLAG_JSR)) |
9b1168d6 MH |
672 | { |
673 | /* subroutines must be called from 32-bit boundaries */ | |
674 | /* so the return address will be correct */ | |
675 | write_1_short (opcode1, insn1, fx->next); | |
676 | return (1); | |
677 | } | |
678 | ||
679 | switch (exec_type) | |
680 | { | |
343b2ab8 MM |
681 | case EXEC_UNKNOWN: /* order not specified */ |
682 | if (Optimizing && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) | |
9b1168d6 MH |
683 | { |
684 | /* parallel */ | |
343b2ab8 | 685 | exec_type = EXEC_PARALLEL; |
9b1168d6 MH |
686 | if (opcode1->op->unit == IU) |
687 | insn = FM00 | (insn2 << 32) | insn1; | |
688 | else if (opcode2->op->unit == MU) | |
689 | insn = FM00 | (insn2 << 32) | insn1; | |
690 | else | |
691 | { | |
692 | insn = FM00 | (insn1 << 32) | insn2; | |
693 | fx = fx->next; | |
694 | } | |
695 | } | |
343b2ab8 | 696 | else if (opcode1->op->unit == IU) |
9b1168d6 MH |
697 | { |
698 | /* reverse sequential */ | |
699 | insn = FM10 | (insn2 << 32) | insn1; | |
343b2ab8 | 700 | exec_type = EXEC_REVSEQ; |
9b1168d6 MH |
701 | } |
702 | else | |
703 | { | |
704 | /* sequential */ | |
705 | insn = FM01 | (insn1 << 32) | insn2; | |
343b2ab8 MM |
706 | fx = fx->next; |
707 | exec_type = EXEC_SEQ; | |
9b1168d6 MH |
708 | } |
709 | break; | |
343b2ab8 MM |
710 | |
711 | case EXEC_PARALLEL: /* parallel */ | |
712 | if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) | |
713 | as_fatal ("Instructions may not be executed in parallel"); | |
714 | else if (opcode1->op->unit == IU) | |
9b1168d6 MH |
715 | { |
716 | if (opcode2->op->unit == IU) | |
717 | as_fatal ("Two IU instructions may not be executed in parallel"); | |
718 | as_warn ("Swapping instruction order"); | |
719 | insn = FM00 | (insn2 << 32) | insn1; | |
720 | } | |
721 | else if (opcode2->op->unit == MU) | |
722 | { | |
723 | if (opcode1->op->unit == MU) | |
724 | as_fatal ("Two MU instructions may not be executed in parallel"); | |
725 | as_warn ("Swapping instruction order"); | |
726 | insn = FM00 | (insn2 << 32) | insn1; | |
727 | } | |
728 | else | |
729 | { | |
730 | insn = FM00 | (insn1 << 32) | insn2; | |
731 | fx = fx->next; | |
732 | } | |
733 | break; | |
343b2ab8 MM |
734 | |
735 | case EXEC_SEQ: /* sequential */ | |
9b1168d6 MH |
736 | if (opcode1->op->unit == IU) |
737 | as_fatal ("IU instruction may not be in the left container"); | |
738 | insn = FM01 | (insn1 << 32) | insn2; | |
739 | fx = fx->next; | |
740 | break; | |
343b2ab8 MM |
741 | |
742 | case EXEC_REVSEQ: /* reverse sequential */ | |
9b1168d6 MH |
743 | if (opcode2->op->unit == MU) |
744 | as_fatal ("MU instruction may not be in the right container"); | |
745 | insn = FM10 | (insn1 << 32) | insn2; | |
746 | fx = fx->next; | |
747 | break; | |
343b2ab8 | 748 | |
9b1168d6 MH |
749 | default: |
750 | as_fatal("unknown execution type passed to write_2_short()"); | |
751 | } | |
752 | ||
753 | /* printf("writing out %llx\n",insn); */ | |
754 | f = frag_more(8); | |
755 | d30v_number_to_chars (f, insn, 8); | |
756 | ||
343b2ab8 MM |
757 | /* If the previous instruction was a 32-bit multiply but it is put into a |
758 | parallel container, mark the current instruction as being a 32-bit | |
759 | multiply. */ | |
760 | if (prev_mul32_p && exec_type == EXEC_PARALLEL) | |
761 | cur_mul32_p = 1; | |
762 | ||
9b1168d6 MH |
763 | for (j=0; j<2; j++) |
764 | { | |
765 | for (i=0; i < fx->fc; i++) | |
766 | { | |
767 | if (fx->fix[i].reloc) | |
768 | { | |
769 | where = (f - frag_now->fr_literal) + 4*j; | |
770 | ||
9b1168d6 MH |
771 | fix_new_exp (frag_now, |
772 | where, | |
773 | fx->fix[i].size, | |
774 | &(fx->fix[i].exp), | |
775 | fx->fix[i].pcrel, | |
776 | fx->fix[i].reloc); | |
777 | } | |
778 | } | |
779 | fx->fc = 0; | |
780 | fx = fx->next; | |
781 | } | |
782 | return (0); | |
783 | } | |
784 | ||
785 | ||
786 | /* Check 2 instructions and determine if they can be safely */ | |
787 | /* executed in parallel. Returns 1 if they can be. */ | |
788 | static int | |
789 | parallel_ok (op1, insn1, op2, insn2, exec_type) | |
790 | struct d30v_insn *op1, *op2; | |
791 | unsigned long insn1, insn2; | |
343b2ab8 | 792 | exec_type_enum exec_type; |
9b1168d6 | 793 | { |
e0882f34 MM |
794 | int i, j, shift, regno, bits, ecc; |
795 | unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2; | |
343b2ab8 | 796 | unsigned long ins, mod_reg[2][3], used_reg[2][3], flag_reg[2]; |
1b524697 MH |
797 | struct d30v_format *f; |
798 | struct d30v_opcode *op; | |
799 | ||
800 | /* section 4.3: both instructions must not be IU or MU only */ | |
801 | if ((op1->op->unit == IU && op2->op->unit == IU) | |
802 | || (op1->op->unit == MU && op2->op->unit == MU)) | |
9b1168d6 MH |
803 | return 0; |
804 | ||
343b2ab8 MM |
805 | /* first instruction must not be a jump to safely optimize, unless this |
806 | is an explicit parallel operation. */ | |
807 | if (exec_type != EXEC_PARALLEL | |
808 | && (op1->op->flags_used & (FLAG_JMP | FLAG_JSR))) | |
e0882f34 MM |
809 | return 0; |
810 | ||
811 | /* If one instruction is /TX or /XT and the other is /FX or /XF respectively, | |
812 | then it is safe to allow the two to be done as parallel ops, since only | |
813 | one will ever be executed at a time. */ | |
814 | if ((op1->ecc == ECC_TX && op2->ecc == ECC_FX) | |
815 | || (op1->ecc == ECC_FX && op2->ecc == ECC_TX) | |
816 | || (op1->ecc == ECC_XT && op2->ecc == ECC_XF) | |
817 | || (op1->ecc == ECC_XF && op2->ecc == ECC_XT)) | |
818 | return 1; | |
819 | ||
820 | /* [0] r0-r31 | |
821 | [1] r32-r63 | |
822 | [2] a0, a1, flag registers */ | |
9b1168d6 | 823 | |
1b524697 | 824 | for (j = 0; j < 2; j++) |
9b1168d6 MH |
825 | { |
826 | if (j == 0) | |
827 | { | |
1b524697 MH |
828 | f = op1->form; |
829 | op = op1->op; | |
e0882f34 | 830 | ecc = op1->ecc; |
9b1168d6 MH |
831 | ins = insn1; |
832 | } | |
833 | else | |
834 | { | |
1b524697 MH |
835 | f = op2->form; |
836 | op = op2->op; | |
e0882f34 | 837 | ecc = op2->ecc; |
9b1168d6 MH |
838 | ins = insn2; |
839 | } | |
343b2ab8 | 840 | flag_reg[j] = 0; |
1b524697 | 841 | mod_reg[j][0] = mod_reg[j][1] = 0; |
e0882f34 | 842 | mod_reg[j][2] = (op->flags_set & FLAG_ALL); |
1b524697 | 843 | used_reg[j][0] = used_reg[j][1] = 0; |
e0882f34 MM |
844 | used_reg[j][2] = (op->flags_used & FLAG_ALL); |
845 | ||
846 | /* BSR/JSR always sets R62 */ | |
847 | if (op->flags_used & FLAG_JSR) | |
848 | mod_reg[j][1] = (1L << (62-32)); | |
849 | ||
850 | /* conditional execution affects the flags_used */ | |
851 | switch (ecc) | |
852 | { | |
853 | case ECC_TX: | |
854 | case ECC_FX: | |
343b2ab8 | 855 | used_reg[j][2] |= flag_reg[j] = FLAG_0; |
e0882f34 MM |
856 | break; |
857 | ||
858 | case ECC_XT: | |
859 | case ECC_XF: | |
343b2ab8 | 860 | used_reg[j][2] |= flag_reg[j] = FLAG_1; |
e0882f34 MM |
861 | break; |
862 | ||
863 | case ECC_TT: | |
864 | case ECC_TF: | |
343b2ab8 | 865 | used_reg[j][2] |= flag_reg[j] = (FLAG_0 | FLAG_1); |
e0882f34 MM |
866 | break; |
867 | } | |
868 | ||
1b524697 | 869 | for (i = 0; f->operands[i]; i++) |
9b1168d6 | 870 | { |
1b524697 MH |
871 | flags = d30v_operand_table[f->operands[i]].flags; |
872 | shift = 12 - d30v_operand_table[f->operands[i]].position; | |
873 | bits = d30v_operand_table[f->operands[i]].bits; | |
874 | if (bits == 32) | |
875 | mask = 0xffffffff; | |
876 | else | |
877 | mask = 0x7FFFFFFF >> (31 - bits); | |
e0882f34 MM |
878 | |
879 | if ((flags & OPERAND_PLUS) || (flags & OPERAND_MINUS)) | |
880 | { | |
881 | /* this is a post-increment or post-decrement */ | |
882 | /* the previous register needs to be marked as modified */ | |
883 | ||
884 | shift = 12 - d30v_operand_table[f->operands[i-1]].position; | |
885 | regno = (ins >> shift) & 0x3f; | |
886 | if (regno >= 32) | |
887 | mod_reg[j][1] |= 1L << (regno - 32); | |
888 | else | |
889 | mod_reg[j][0] |= 1L << regno; | |
890 | } | |
891 | else if (flags & OPERAND_REG) | |
9b1168d6 MH |
892 | { |
893 | regno = (ins >> shift) & mask; | |
e0882f34 MM |
894 | /* the memory write functions don't have a destination register */ |
895 | if ((flags & OPERAND_DEST) && !(op->flags_set & FLAG_MEM)) | |
9b1168d6 | 896 | { |
e0882f34 | 897 | /* MODIFIED registers and flags */ |
1b524697 | 898 | if (flags & OPERAND_ACC) |
e0882f34 MM |
899 | { |
900 | if (regno == 0) | |
901 | mod_reg[j][2] |= FLAG_A0; | |
902 | else if (regno == 1) | |
903 | mod_reg[j][2] |= FLAG_A1; | |
904 | else | |
905 | abort (); | |
906 | } | |
1b524697 | 907 | else if (flags & OPERAND_FLAG) |
e0882f34 | 908 | mod_reg[j][2] |= 1L << regno; |
1b524697 MH |
909 | else if (!(flags & OPERAND_CONTROL)) |
910 | { | |
e0882f34 MM |
911 | int r, z; |
912 | ||
913 | /* need to check if there are two destination */ | |
914 | /* registers, for example ld2w */ | |
915 | if (flags & OPERAND_2REG) | |
916 | z = 1; | |
1b524697 | 917 | else |
e0882f34 MM |
918 | z = 0; |
919 | ||
920 | for (r = regno; r <= regno + z; r++) | |
921 | { | |
922 | if (r >= 32) | |
923 | mod_reg[j][1] |= 1L << (r - 32); | |
924 | else | |
925 | mod_reg[j][0] |= 1L << r; | |
926 | } | |
1b524697 | 927 | } |
9b1168d6 MH |
928 | } |
929 | else | |
930 | { | |
e0882f34 | 931 | /* USED, but not modified registers and flags */ |
1b524697 | 932 | if (flags & OPERAND_ACC) |
e0882f34 MM |
933 | { |
934 | if (regno == 0) | |
935 | used_reg[j][2] |= FLAG_A0; | |
936 | else if (regno == 1) | |
937 | used_reg[j][2] |= FLAG_A1; | |
938 | else | |
939 | abort (); | |
940 | } | |
1b524697 | 941 | else if (flags & OPERAND_FLAG) |
e0882f34 | 942 | used_reg[j][2] |= 1L << regno; |
1b524697 MH |
943 | else if (!(flags & OPERAND_CONTROL)) |
944 | { | |
e0882f34 MM |
945 | int r, z; |
946 | ||
947 | /* need to check if there are two source */ | |
948 | /* registers, for example st2w */ | |
949 | if (flags & OPERAND_2REG) | |
950 | z = 1; | |
1b524697 | 951 | else |
e0882f34 MM |
952 | z = 0; |
953 | ||
954 | for (r = regno; r <= regno + z; r++) | |
955 | { | |
956 | if (r >= 32) | |
957 | used_reg[j][1] |= 1L << (r - 32); | |
958 | else | |
959 | used_reg[j][0] |= 1L << r; | |
960 | } | |
1b524697 | 961 | } |
9b1168d6 MH |
962 | } |
963 | } | |
964 | } | |
9b1168d6 | 965 | } |
1b524697 | 966 | |
e0882f34 MM |
967 | flags_set1 = op1->op->flags_set; |
968 | flags_set2 = op2->op->flags_set; | |
969 | flags_used1 = op1->op->flags_used; | |
970 | flags_used2 = op2->op->flags_used; | |
971 | ||
972 | /* ST2W/ST4HB combined with ADDppp/SUBppp is illegal. */ | |
973 | if (((flags_set1 & (FLAG_MEM | FLAG_2WORD)) == (FLAG_MEM | FLAG_2WORD) | |
974 | && (flags_used2 & FLAG_ADDSUBppp) != 0) | |
975 | || ((flags_set2 & (FLAG_MEM | FLAG_2WORD)) == (FLAG_MEM | FLAG_2WORD) | |
976 | && (flags_used1 & FLAG_ADDSUBppp) != 0)) | |
977 | return 0; | |
978 | ||
979 | /* Load instruction combined with half-word multiply is illegal. */ | |
980 | if (((flags_used1 & FLAG_MEM) != 0 && (flags_used2 & FLAG_MUL16)) | |
981 | || ((flags_used2 & FLAG_MEM) != 0 && (flags_used1 & FLAG_MUL16))) | |
982 | return 0; | |
983 | ||
984 | /* Specifically allow add || add by removing carry, overflow bits dependency. | |
985 | This is safe, even if an addc follows since the IU takes the argument in | |
986 | the right container, and it writes its results last. | |
987 | However, don't paralellize add followed by addc or sub followed by | |
988 | subb. */ | |
989 | ||
990 | if (mod_reg[0][2] == FLAG_CVVA && mod_reg[1][2] == FLAG_CVVA | |
343b2ab8 MM |
991 | && (used_reg[0][2] & ~flag_reg[0]) == 0 |
992 | && (used_reg[1][2] & ~flag_reg[1]) == 0 | |
e0882f34 MM |
993 | && op1->op->unit == EITHER && op2->op->unit == EITHER) |
994 | { | |
995 | mod_reg[0][2] = mod_reg[1][2] = 0; | |
996 | } | |
997 | ||
1b524697 | 998 | for(j = 0; j < 3; j++) |
e0882f34 MM |
999 | { |
1000 | /* If the second instruction depends on the first, we obviously | |
1001 | cannot parallelize. Note, the mod flag implies use, so | |
1002 | check that as well. */ | |
1003 | if ((mod_reg[0][j] & (mod_reg[1][j] | used_reg[1][j])) != 0) | |
1004 | return 0; | |
1005 | } | |
1006 | ||
1b524697 | 1007 | return 1; |
9b1168d6 MH |
1008 | } |
1009 | ||
1010 | ||
1011 | ||
1012 | /* This is the main entry point for the machine-dependent assembler. str points to a | |
1013 | machine-dependent instruction. This function is supposed to emit the frags/bytes | |
1014 | it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing | |
343b2ab8 | 1015 | and leaves the difficult stuff to do_assemble(). */ |
9b1168d6 MH |
1016 | |
1017 | static long long prev_insn = -1; | |
1018 | static struct d30v_insn prev_opcode; | |
1019 | static subsegT prev_subseg; | |
1020 | static segT prev_seg = 0; | |
1021 | ||
1022 | void | |
1023 | md_assemble (str) | |
1024 | char *str; | |
1025 | { | |
1026 | struct d30v_insn opcode; | |
1027 | long long insn; | |
343b2ab8 MM |
1028 | exec_type_enum extype = EXEC_UNKNOWN; /* execution type; parallel, etc */ |
1029 | static exec_type_enum etype = EXEC_UNKNOWN; /* saved extype. used for multiline instructions */ | |
9b1168d6 MH |
1030 | char *str2; |
1031 | ||
e0882f34 MM |
1032 | if ( (prev_insn != -1) && prev_seg && ((prev_seg != now_seg) || (prev_subseg != now_subseg))) |
1033 | d30v_cleanup(); | |
1034 | ||
343b2ab8 | 1035 | if (etype == EXEC_UNKNOWN) |
9b1168d6 MH |
1036 | { |
1037 | /* look for the special multiple instruction separators */ | |
1038 | str2 = strstr (str, "||"); | |
1039 | if (str2) | |
343b2ab8 | 1040 | extype = EXEC_PARALLEL; |
9b1168d6 MH |
1041 | else |
1042 | { | |
1043 | str2 = strstr (str, "->"); | |
1044 | if (str2) | |
343b2ab8 | 1045 | extype = EXEC_SEQ; |
9b1168d6 MH |
1046 | else |
1047 | { | |
1048 | str2 = strstr (str, "<-"); | |
1049 | if (str2) | |
343b2ab8 | 1050 | extype = EXEC_REVSEQ; |
9b1168d6 MH |
1051 | } |
1052 | } | |
1053 | /* str2 points to the separator, if one */ | |
1054 | if (str2) | |
1055 | { | |
1056 | *str2 = 0; | |
1057 | ||
1058 | /* if two instructions are present and we already have one saved | |
1059 | then first write it out */ | |
1060 | d30v_cleanup(); | |
1061 | ||
1062 | /* assemble first instruction and save it */ | |
1063 | prev_insn = do_assemble (str, &prev_opcode); | |
1064 | if (prev_insn == -1) | |
2c268a85 | 1065 | as_fatal ("cannot assemble instruction "); |
e0882f34 MM |
1066 | if (prev_opcode.form->form >= LONG) |
1067 | as_fatal ("First opcode is long. Unable to mix instructions as specified."); | |
9b1168d6 MH |
1068 | fixups = fixups->next; |
1069 | str = str2 + 2; | |
1070 | } | |
1071 | } | |
1072 | ||
1073 | insn = do_assemble (str, &opcode); | |
1074 | if (insn == -1) | |
1075 | { | |
1076 | if (extype) | |
1077 | { | |
1078 | etype = extype; | |
1079 | return; | |
1080 | } | |
2c268a85 | 1081 | as_fatal ("cannot assemble instruction "); |
9b1168d6 MH |
1082 | } |
1083 | ||
1084 | if (etype) | |
1085 | { | |
1086 | extype = etype; | |
1087 | etype = 0; | |
1088 | } | |
1089 | ||
343b2ab8 MM |
1090 | /* Word multiply instructions must not be followed by either a load or a |
1091 | 16-bit multiply instruction in the next cycle. */ | |
1092 | if (prev_mul32_p && (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16))) | |
1093 | { | |
1094 | /* However, load and multiply should able to be combined in a parallel | |
1095 | operation, so check for that first. */ | |
1096 | ||
1097 | if (prev_insn != -1 | |
1098 | && (opcode.op->flags_used & FLAG_MEM) | |
1099 | && opcode.form->form < LONG | |
1100 | && (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN)) | |
1101 | && parallel_ok (&prev_opcode, (long)prev_insn, | |
1102 | &opcode, (long)insn, extype) | |
1103 | && write_2_short (&prev_opcode, (long)prev_insn, | |
1104 | &opcode, (long)insn, extype, fixups) == 0) | |
1105 | { | |
1106 | /* no instructions saved */ | |
1107 | prev_insn = -1; | |
1108 | return; | |
1109 | } | |
1110 | ||
1111 | /* Can't parallelize, flush current instruction and emit a word of NOPS */ | |
1112 | else | |
1113 | { | |
1114 | char *f; | |
1115 | d30v_cleanup(); | |
1116 | ||
1117 | f = frag_more(8); | |
1118 | d30v_number_to_chars (f, NOP2, 8); | |
1119 | if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY) | |
1120 | as_warn ("word of NOPs added between word multiply and %s", | |
1121 | ((opcode.op->flags_used & FLAG_MEM) | |
1122 | ? "load" | |
1123 | : "16-bit multiply")); | |
1124 | } | |
1125 | } | |
1126 | ||
9b1168d6 MH |
1127 | /* if this is a long instruction, write it and any previous short instruction */ |
1128 | if (opcode.form->form >= LONG) | |
1129 | { | |
1130 | if (extype) | |
1131 | as_fatal("Unable to mix instructions as specified"); | |
1132 | d30v_cleanup(); | |
1133 | write_long (&opcode, insn, fixups); | |
1134 | prev_insn = -1; | |
1135 | return; | |
1136 | } | |
343b2ab8 MM |
1137 | |
1138 | if ((prev_insn != -1) && | |
1139 | (write_2_short (&prev_opcode, (long)prev_insn, &opcode, (long)insn, extype, fixups) == 0)) | |
9b1168d6 MH |
1140 | { |
1141 | /* no instructions saved */ | |
1142 | prev_insn = -1; | |
1143 | } | |
343b2ab8 | 1144 | |
9b1168d6 MH |
1145 | else |
1146 | { | |
1147 | if (extype) | |
1148 | as_fatal("Unable to mix instructions as specified"); | |
1149 | /* save off last instruction so it may be packed on next pass */ | |
343b2ab8 | 1150 | memcpy(&prev_opcode, &opcode, sizeof(prev_opcode)); |
9b1168d6 MH |
1151 | prev_insn = insn; |
1152 | prev_seg = now_seg; | |
1153 | prev_subseg = now_subseg; | |
1154 | fixups = fixups->next; | |
1155 | } | |
1156 | } | |
1157 | ||
1158 | ||
1159 | /* do_assemble assembles a single instruction and returns an opcode */ | |
1160 | /* it returns -1 (an invalid opcode) on error */ | |
1161 | ||
1162 | static long long | |
1163 | do_assemble (str, opcode) | |
1164 | char *str; | |
1165 | struct d30v_insn *opcode; | |
1166 | { | |
1167 | unsigned char *op_start, *save; | |
1168 | unsigned char *op_end; | |
1169 | char name[20]; | |
e0882f34 | 1170 | int cmp_hack, nlen = 0, fsize = 0; |
9b1168d6 MH |
1171 | expressionS myops[6]; |
1172 | long long insn; | |
1173 | ||
9b1168d6 MH |
1174 | /* Drop leading whitespace */ |
1175 | while (*str == ' ') | |
1176 | str++; | |
1177 | ||
1178 | /* find the opcode end */ | |
1179 | for (op_start = op_end = (unsigned char *) (str); | |
1180 | *op_end | |
1181 | && nlen < 20 | |
1182 | && *op_end != '/' | |
1183 | && !is_end_of_line[*op_end] && *op_end != ' '; | |
1184 | op_end++) | |
1185 | { | |
1186 | name[nlen] = tolower(op_start[nlen]); | |
1187 | nlen++; | |
1188 | } | |
1189 | ||
1190 | if (nlen == 0) | |
1191 | return (-1); | |
1192 | ||
1193 | name[nlen] = 0; | |
1194 | ||
1195 | /* if there is an execution condition code, handle it */ | |
1196 | if (*op_end == '/') | |
1197 | { | |
1198 | int i = 0; | |
1199 | while ( (i < ECC_MAX) && strncasecmp(d30v_ecc_names[i],op_end+1,2)) | |
1200 | i++; | |
1201 | ||
1202 | if (i == ECC_MAX) | |
1203 | { | |
1204 | char tmp[4]; | |
1205 | strncpy(tmp,op_end+1,2); | |
1206 | tmp[2] = 0; | |
1207 | as_fatal ("unknown condition code: %s",tmp); | |
1208 | return -1; | |
1209 | } | |
1210 | /* printf("condition code=%d\n",i); */ | |
1211 | opcode->ecc = i; | |
1212 | op_end += 3; | |
1213 | } | |
1214 | else | |
1215 | opcode->ecc = ECC_AL; | |
1216 | ||
1217 | ||
1218 | /* CMP and CMPU change their name based on condition codes */ | |
1219 | if (!strncmp(name,"cmp",3)) | |
1220 | { | |
1221 | int p,i; | |
1222 | char **str = (char **)d30v_cc_names; | |
1223 | if (name[3] == 'u') | |
1224 | p = 4; | |
1225 | else | |
1226 | p = 3; | |
1227 | ||
343b2ab8 | 1228 | for(i=1; *str && strncmp(*str,&name[p],2); i++, str++) |
9b1168d6 MH |
1229 | ; |
1230 | ||
e0882f34 MM |
1231 | /* cmpu only supports some condition codes */ |
1232 | if (p == 4) | |
1233 | { | |
1234 | if (i < 3 || i > 6) | |
1235 | { | |
1236 | name[p+2]=0; | |
1237 | as_fatal ("cmpu doesn't support condition code %s",&name[p]); | |
1238 | } | |
1239 | } | |
1240 | ||
9b1168d6 MH |
1241 | if (!*str) |
1242 | { | |
1243 | name[p+2]=0; | |
1244 | as_fatal ("unknown condition code: %s",&name[p]); | |
1245 | } | |
1246 | ||
1247 | cmp_hack = i; | |
1248 | name[p] = 0; | |
1249 | } | |
1250 | else | |
1251 | cmp_hack = 0; | |
1252 | ||
1253 | /* printf("cmp_hack=%d\n",cmp_hack); */ | |
1254 | ||
e0882f34 MM |
1255 | /* need to look for .s or .l */ |
1256 | if (name[nlen-2] == '.') | |
1257 | { | |
1258 | switch (name[nlen-1]) | |
1259 | { | |
1260 | case 's': | |
1261 | fsize = FORCE_SHORT; | |
1262 | break; | |
1263 | case 'l': | |
1264 | fsize = FORCE_LONG; | |
1265 | default: | |
1266 | } | |
1267 | name[nlen-2] = 0; | |
1268 | } | |
1269 | ||
9b1168d6 MH |
1270 | /* find the first opcode with the proper name */ |
1271 | opcode->op = (struct d30v_opcode *)hash_find (d30v_hash, name); | |
1272 | if (opcode->op == NULL) | |
1273 | as_fatal ("unknown opcode: %s",name); | |
1274 | ||
1275 | save = input_line_pointer; | |
1276 | input_line_pointer = op_end; | |
e0882f34 | 1277 | while (!(opcode->form = find_format (opcode->op, myops, fsize, cmp_hack))) |
9b1168d6 MH |
1278 | { |
1279 | opcode->op++; | |
1280 | if (strcmp(opcode->op->name,name)) | |
1281 | return -1; | |
1282 | } | |
1283 | input_line_pointer = save; | |
1284 | ||
1285 | insn = build_insn (opcode, myops); | |
343b2ab8 MM |
1286 | |
1287 | /* Propigate multiply status */ | |
1288 | if (insn != -1) | |
1289 | { | |
1290 | prev_mul32_p = cur_mul32_p; | |
1291 | cur_mul32_p = (opcode->op->flags_used & FLAG_MUL32) != 0; | |
1292 | } | |
1293 | ||
9b1168d6 MH |
1294 | return (insn); |
1295 | } | |
1296 | ||
1297 | ||
1298 | /* find_format() gets a pointer to an entry in the format table. */ | |
1299 | /* It must look at all formats for an opcode and use the operands */ | |
1300 | /* to choose the correct one. Returns NULL on error. */ | |
1301 | ||
1302 | static struct d30v_format * | |
e0882f34 | 1303 | find_format (opcode, myops, fsize, cmp_hack) |
9b1168d6 MH |
1304 | struct d30v_opcode *opcode; |
1305 | expressionS myops[]; | |
e0882f34 | 1306 | int fsize; |
9b1168d6 MH |
1307 | int cmp_hack; |
1308 | { | |
1309 | int numops, match, index, i=0, j, k; | |
1310 | struct d30v_format *fm; | |
9b1168d6 | 1311 | |
9b1168d6 MH |
1312 | /* get all the operands and save them as expressions */ |
1313 | numops = get_operands (myops, cmp_hack); | |
1314 | ||
343b2ab8 | 1315 | while ((index = opcode->format[i++]) != 0) |
9b1168d6 | 1316 | { |
e0882f34 MM |
1317 | if ((fsize == FORCE_SHORT) && (index >= LONG)) |
1318 | continue; | |
1319 | ||
1320 | if ((fsize == FORCE_LONG) && (index < LONG)) | |
1321 | continue; | |
1322 | ||
9b1168d6 MH |
1323 | fm = (struct d30v_format *)&d30v_format_table[index]; |
1324 | k = index; | |
1325 | while (fm->form == index) | |
1326 | { | |
1327 | match = 1; | |
1328 | /* now check the operands for compatibility */ | |
1329 | for (j = 0; match && fm->operands[j]; j++) | |
1330 | { | |
1331 | int flags = d30v_operand_table[fm->operands[j]].flags; | |
1332 | int X_op = myops[j].X_op; | |
1333 | int num = myops[j].X_add_number; | |
1334 | ||
9b1168d6 MH |
1335 | if ( flags & OPERAND_SPECIAL ) |
1336 | break; | |
1337 | else if (X_op == 0) | |
1338 | match = 0; | |
1339 | else if (flags & OPERAND_REG) | |
1340 | { | |
343b2ab8 MM |
1341 | if ((X_op != O_register) |
1342 | || ((flags & OPERAND_ACC) && !(num & OPERAND_ACC)) | |
1343 | || ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG)) | |
1344 | || ((flags & OPERAND_CONTROL) | |
1345 | && !(num & (OPERAND_CONTROL | OPERAND_FLAG)))) | |
9b1168d6 MH |
1346 | { |
1347 | match = 0; | |
9b1168d6 MH |
1348 | } |
1349 | } | |
343b2ab8 MM |
1350 | else |
1351 | if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) | |
1352 | || ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) | |
1353 | || ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) | |
1354 | || ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) | |
1355 | || ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || (num != OPERAND_ATSIGN)))) | |
9b1168d6 | 1356 | { |
9b1168d6 MH |
1357 | match=0; |
1358 | } | |
1359 | else if (flags & OPERAND_NUM) | |
1360 | { | |
1361 | /* a number can be a constant or symbol expression */ | |
1362 | if (fm->form >= LONG) | |
1363 | { | |
1364 | /* If we're testing for a LONG format, either fits */ | |
1365 | if (X_op != O_constant && X_op != O_symbol) | |
1366 | match = 0; | |
1367 | } | |
e0882f34 MM |
1368 | else if ((fm->form < LONG) && (((fsize == FORCE_SHORT) && (X_op == O_symbol)) || |
1369 | (fm->form == SHORT_D2 && j == 0))) | |
1370 | match = 1; | |
9b1168d6 MH |
1371 | /* This is the tricky part. Will the constant or symbol */ |
1372 | /* fit into the space in the current format? */ | |
1373 | else if (X_op == O_constant) | |
1374 | { | |
1375 | if (check_range (num, d30v_operand_table[fm->operands[j]].bits, flags)) | |
1376 | match = 0; | |
1377 | } | |
1378 | else if (X_op == O_symbol && S_IS_DEFINED(myops[j].X_add_symbol) && | |
e0882f34 MM |
1379 | (S_GET_SEGMENT(myops[j].X_add_symbol) == now_seg) && |
1380 | opcode->reloc_flag == RELOC_PCREL) | |
9b1168d6 MH |
1381 | { |
1382 | /* if the symbol is defined, see if the value will fit */ | |
1383 | /* into the form we're considering */ | |
1384 | fragS *f; | |
1385 | long value; | |
1386 | /* calculate the current address by running through the previous frags */ | |
1387 | /* and adding our current offset */ | |
1388 | for (value = 0, f = frchain_now->frch_root; f; f = f->fr_next) | |
1389 | value += f->fr_fix + f->fr_offset; | |
e0882f34 MM |
1390 | value = S_GET_VALUE(myops[j].X_add_symbol) - value - |
1391 | (obstack_next_free(&frchain_now->frch_obstack) - frag_now->fr_literal); | |
9b1168d6 MH |
1392 | if (check_range (value, d30v_operand_table[fm->operands[j]].bits, flags)) |
1393 | match = 0; | |
9b1168d6 MH |
1394 | } |
1395 | else | |
1396 | match = 0; | |
1397 | } | |
1398 | } | |
1399 | /* printf("through the loop: match=%d\n",match); */ | |
1400 | /* we're only done if the operands matched so far AND there | |
1401 | are no more to check */ | |
1402 | if (match && myops[j].X_op==0) | |
1403 | return fm; | |
1404 | match = 0; | |
1405 | fm = (struct d30v_format *)&d30v_format_table[++k]; | |
1406 | } | |
1407 | /* printf("trying another format: i=%d\n",i); */ | |
1408 | } | |
1409 | return NULL; | |
1410 | } | |
1411 | ||
1412 | /* if while processing a fixup, a reloc really needs to be created */ | |
1413 | /* then it is done here */ | |
1414 | ||
1415 | arelent * | |
1416 | tc_gen_reloc (seg, fixp) | |
1417 | asection *seg; | |
1418 | fixS *fixp; | |
1419 | { | |
1420 | arelent *reloc; | |
2c268a85 | 1421 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
9b1168d6 MH |
1422 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; |
1423 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1424 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
9b1168d6 MH |
1425 | if (reloc->howto == (reloc_howto_type *) NULL) |
1426 | { | |
1427 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1428 | "reloc %d not supported by object file format", (int)fixp->fx_r_type); | |
1429 | return NULL; | |
1430 | } | |
1431 | reloc->addend = fixp->fx_addnumber; | |
1432 | return reloc; | |
1433 | } | |
1434 | ||
1435 | int | |
1436 | md_estimate_size_before_relax (fragp, seg) | |
1437 | fragS *fragp; | |
1438 | asection *seg; | |
1439 | { | |
1440 | abort (); | |
1441 | return 0; | |
1442 | } | |
1443 | ||
1444 | long | |
1445 | md_pcrel_from_section (fixp, sec) | |
1446 | fixS *fixp; | |
1447 | segT sec; | |
1448 | { | |
e0882f34 MM |
1449 | if (fixp->fx_addsy != (symbolS *)NULL && (!S_IS_DEFINED (fixp->fx_addsy) || |
1450 | (S_GET_SEGMENT (fixp->fx_addsy) != sec))) | |
9b1168d6 MH |
1451 | return 0; |
1452 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
1453 | } | |
1454 | ||
1455 | int | |
1456 | md_apply_fix3 (fixp, valuep, seg) | |
1457 | fixS *fixp; | |
1458 | valueT *valuep; | |
1459 | segT seg; | |
1460 | { | |
1461 | char *where; | |
1462 | unsigned long insn, insn2; | |
1463 | long value; | |
9b1168d6 MH |
1464 | |
1465 | if (fixp->fx_addsy == (symbolS *) NULL) | |
1466 | { | |
1467 | value = *valuep; | |
1468 | fixp->fx_done = 1; | |
1469 | } | |
9b1168d6 MH |
1470 | else if (fixp->fx_pcrel) |
1471 | { | |
1472 | value = *valuep; | |
e0882f34 | 1473 | } |
1b524697 | 1474 | else |
9b1168d6 MH |
1475 | { |
1476 | value = fixp->fx_offset; | |
9b1168d6 MH |
1477 | if (fixp->fx_subsy != (symbolS *) NULL) |
1478 | { | |
e0882f34 | 1479 | if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section) |
9b1168d6 MH |
1480 | value -= S_GET_VALUE (fixp->fx_subsy); |
1481 | else | |
1482 | { | |
1483 | /* We don't actually support subtracting a symbol. */ | |
1b524697 | 1484 | as_bad_where (fixp->fx_file, fixp->fx_line, |
9b1168d6 MH |
1485 | "expression too complex"); |
1486 | } | |
1487 | } | |
1488 | } | |
1489 | ||
1490 | /* Fetch the instruction, insert the fully resolved operand | |
1491 | value, and stuff the instruction back again. */ | |
1492 | where = fixp->fx_frag->fr_literal + fixp->fx_where; | |
1493 | insn = bfd_getb32 ((unsigned char *) where); | |
1b524697 | 1494 | |
9b1168d6 MH |
1495 | switch (fixp->fx_r_type) |
1496 | { | |
1497 | case BFD_RELOC_D30V_6: | |
e0882f34 | 1498 | check_size (value, 6, fixp->fx_file, fixp->fx_line); |
9b1168d6 MH |
1499 | insn |= value & 0x3F; |
1500 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1501 | break; | |
343b2ab8 | 1502 | |
e0882f34 MM |
1503 | case BFD_RELOC_D30V_9_PCREL: |
1504 | if (fixp->fx_where & 0x7) | |
1505 | { | |
1506 | if (fixp->fx_done) | |
1507 | value += 4; | |
1508 | else | |
1509 | fixp->fx_r_type = BFD_RELOC_D30V_9_PCREL_R; | |
1510 | } | |
1511 | check_size (value, 9, fixp->fx_file, fixp->fx_line); | |
1512 | insn |= ((value >> 3) & 0x3F) << 12; | |
1513 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1514 | break; | |
343b2ab8 | 1515 | |
9b1168d6 | 1516 | case BFD_RELOC_D30V_15: |
e0882f34 | 1517 | check_size (value, 15, fixp->fx_file, fixp->fx_line); |
9b1168d6 MH |
1518 | insn |= (value >> 3) & 0xFFF; |
1519 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1520 | break; | |
343b2ab8 | 1521 | |
9b1168d6 | 1522 | case BFD_RELOC_D30V_15_PCREL: |
e0882f34 MM |
1523 | if (fixp->fx_where & 0x7) |
1524 | { | |
1525 | if (fixp->fx_done) | |
1526 | value += 4; | |
1527 | else | |
1528 | fixp->fx_r_type = BFD_RELOC_D30V_15_PCREL_R; | |
1529 | } | |
1530 | check_size (value, 15, fixp->fx_file, fixp->fx_line); | |
9b1168d6 MH |
1531 | insn |= (value >> 3) & 0xFFF; |
1532 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1533 | break; | |
343b2ab8 | 1534 | |
9b1168d6 | 1535 | case BFD_RELOC_D30V_21: |
e0882f34 | 1536 | check_size (value, 21, fixp->fx_file, fixp->fx_line); |
9b1168d6 MH |
1537 | insn |= (value >> 3) & 0x3FFFF; |
1538 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1539 | break; | |
343b2ab8 | 1540 | |
9b1168d6 | 1541 | case BFD_RELOC_D30V_21_PCREL: |
e0882f34 MM |
1542 | if (fixp->fx_where & 0x7) |
1543 | { | |
1544 | if (fixp->fx_done) | |
1545 | value += 4; | |
1546 | else | |
1547 | fixp->fx_r_type = BFD_RELOC_D30V_21_PCREL_R; | |
1548 | } | |
1549 | check_size (value, 21, fixp->fx_file, fixp->fx_line); | |
9b1168d6 MH |
1550 | insn |= (value >> 3) & 0x3FFFF; |
1551 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1552 | break; | |
343b2ab8 | 1553 | |
9b1168d6 MH |
1554 | case BFD_RELOC_D30V_32: |
1555 | insn2 = bfd_getb32 ((unsigned char *) where + 4); | |
343b2ab8 MM |
1556 | insn |= (value >> 26) & 0x3F; /* top 6 bits */ |
1557 | insn2 |= ((value & 0x03FC0000) << 2); /* next 8 bits */ | |
9b1168d6 MH |
1558 | insn2 |= value & 0x0003FFFF; /* bottom 18 bits */ |
1559 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1560 | bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4); | |
1561 | break; | |
343b2ab8 | 1562 | |
9b1168d6 | 1563 | case BFD_RELOC_D30V_32_PCREL: |
9b1168d6 | 1564 | insn2 = bfd_getb32 ((unsigned char *) where + 4); |
343b2ab8 MM |
1565 | insn |= (value >> 26) & 0x3F; /* top 6 bits */ |
1566 | insn2 |= ((value & 0x03FC0000) << 2); /* next 8 bits */ | |
9b1168d6 MH |
1567 | insn2 |= value & 0x0003FFFF; /* bottom 18 bits */ |
1568 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1569 | bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4); | |
1570 | break; | |
343b2ab8 | 1571 | |
9b1168d6 | 1572 | case BFD_RELOC_32: |
9b1168d6 MH |
1573 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); |
1574 | break; | |
343b2ab8 | 1575 | |
9b1168d6 MH |
1576 | default: |
1577 | as_fatal ("line %d: unknown relocation type: 0x%x",fixp->fx_line,fixp->fx_r_type); | |
1578 | } | |
9b1168d6 MH |
1579 | return 0; |
1580 | } | |
1581 | ||
1582 | ||
1583 | /* d30v_cleanup() is called after the assembler has finished parsing the input | |
1584 | file or after a label is defined. Because the D30V assembler sometimes saves short | |
1585 | instructions to see if it can package them with the next instruction, there may | |
1586 | be a short instruction that still needs written. */ | |
1587 | int | |
1588 | d30v_cleanup () | |
1589 | { | |
1590 | segT seg; | |
1591 | subsegT subseg; | |
1592 | ||
1593 | if (prev_insn != -1) | |
1594 | { | |
1595 | seg = now_seg; | |
1596 | subseg = now_subseg; | |
1597 | subseg_set (prev_seg, prev_subseg); | |
1598 | write_1_short (&prev_opcode, (long)prev_insn, fixups->next); | |
1599 | subseg_set (seg, subseg); | |
1600 | prev_insn = -1; | |
1601 | } | |
1602 | return 1; | |
1603 | } | |
1604 | ||
1605 | ||
1606 | static void | |
1607 | d30v_number_to_chars (buf, value, n) | |
1608 | char *buf; /* Return 'nbytes' of chars here. */ | |
1609 | long long value; /* The value of the bits. */ | |
1610 | int n; /* Number of bytes in the output. */ | |
1611 | { | |
1612 | while (n--) | |
1613 | { | |
1614 | buf[n] = value & 0xff; | |
1615 | value >>= 8; | |
1616 | } | |
1617 | } | |
e0882f34 MM |
1618 | |
1619 | ||
1620 | /* This function is called at the start of every line. */ | |
1621 | /* it checks to see if the first character is a '.' */ | |
1622 | /* which indicates the start of a pseudo-op. If it is, */ | |
1623 | /* then write out any unwritten instructions */ | |
1624 | ||
1625 | void | |
1626 | d30v_start_line() | |
1627 | { | |
1628 | char *c = input_line_pointer; | |
1629 | ||
1630 | while(isspace(*c)) | |
1631 | c++; | |
1632 | ||
1633 | if (*c == '.') | |
1634 | d30v_cleanup(); | |
1635 | } | |
1636 | ||
1637 | static void | |
1638 | check_size (value, bits, file, line) | |
1639 | long value; | |
1640 | int bits; | |
1641 | char *file; | |
1642 | int line; | |
1643 | { | |
1644 | int tmp, max; | |
1645 | ||
1646 | if (value < 0) | |
1647 | tmp = ~value; | |
1648 | else | |
1649 | tmp = value; | |
1650 | ||
1651 | max = (1 << (bits - 1)) - 1; | |
1652 | ||
1653 | if (tmp > max) | |
1654 | as_bad_where (file, line,"value too large to fit in %d bits",bits); | |
1655 | ||
1656 | return; | |
1657 | } |