Commit | Line | Data |
---|---|---|
c2dcd04e | 1 | /* tc-h8300.c -- Assemble code for the Renesas H8/300 |
cc8a6dd0 | 2 | Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, |
aa820537 AM |
3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
4 | Free Software Foundation, Inc. | |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 | 22 | |
bc0d738a | 23 | /* Written By Steve Chamberlain <sac@cygnus.com>. */ |
252b5132 | 24 | |
252b5132 RH |
25 | #include "as.h" |
26 | #include "subsegs.h" | |
2c8714f2 | 27 | #include "dwarf2dbg.h" |
2c8714f2 | 28 | |
252b5132 RH |
29 | #define DEFINE_TABLE |
30 | #define h8_opcodes ops | |
31 | #include "opcode/h8300.h" | |
3882b010 | 32 | #include "safe-ctype.h" |
252b5132 | 33 | |
7e0de7bf JL |
34 | #ifdef OBJ_ELF |
35 | #include "elf/h8.h" | |
7e0de7bf JL |
36 | #endif |
37 | ||
63a0b638 | 38 | const char comment_chars[] = ";"; |
252b5132 | 39 | const char line_comment_chars[] = "#"; |
63a0b638 | 40 | const char line_separator_chars[] = ""; |
252b5132 | 41 | |
600e9c99 KH |
42 | static void sbranch (int); |
43 | static void h8300hmode (int); | |
44 | static void h8300smode (int); | |
45 | static void h8300hnmode (int); | |
46 | static void h8300snmode (int); | |
47 | static void h8300sxmode (int); | |
48 | static void h8300sxnmode (int); | |
b54a3392 | 49 | static void pint (int); |
252b5132 | 50 | |
66faad26 KH |
51 | int Hmode; |
52 | int Smode; | |
53 | int Nmode; | |
54 | int SXmode; | |
3048287a | 55 | |
d4e2de6b | 56 | #define PSIZE (Hmode && !Nmode ? L_32 : L_16) |
3048287a | 57 | |
600e9c99 | 58 | static int bsize = L_8; /* Default branch displacement. */ |
252b5132 | 59 | |
a720f7bc KD |
60 | struct h8_instruction |
61 | { | |
62 | int length; | |
63 | int noperands; | |
64 | int idx; | |
65 | int size; | |
66 | const struct h8_opcode *opcode; | |
67 | }; | |
68 | ||
600e9c99 | 69 | static struct h8_instruction *h8_instructions; |
a720f7bc | 70 | |
600e9c99 | 71 | static void |
b54a3392 | 72 | h8300hmode (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
73 | { |
74 | Hmode = 1; | |
75 | Smode = 0; | |
83e20b45 JL |
76 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h)) |
77 | as_warn (_("could not set architecture and machine")); | |
252b5132 RH |
78 | } |
79 | ||
600e9c99 | 80 | static void |
b54a3392 | 81 | h8300smode (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
82 | { |
83 | Smode = 1; | |
84 | Hmode = 1; | |
83e20b45 JL |
85 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s)) |
86 | as_warn (_("could not set architecture and machine")); | |
252b5132 | 87 | } |
70d6ecf3 | 88 | |
600e9c99 | 89 | static void |
b54a3392 | 90 | h8300hnmode (int arg ATTRIBUTE_UNUSED) |
8d9cd6b1 NC |
91 | { |
92 | Hmode = 1; | |
93 | Smode = 0; | |
94 | Nmode = 1; | |
8d9cd6b1 NC |
95 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn)) |
96 | as_warn (_("could not set architecture and machine")); | |
8d9cd6b1 NC |
97 | } |
98 | ||
600e9c99 | 99 | static void |
b54a3392 | 100 | h8300snmode (int arg ATTRIBUTE_UNUSED) |
8d9cd6b1 NC |
101 | { |
102 | Smode = 1; | |
103 | Hmode = 1; | |
104 | Nmode = 1; | |
8d9cd6b1 NC |
105 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn)) |
106 | as_warn (_("could not set architecture and machine")); | |
8d9cd6b1 NC |
107 | } |
108 | ||
600e9c99 | 109 | static void |
b54a3392 | 110 | h8300sxmode (int arg ATTRIBUTE_UNUSED) |
7ee7b84d MS |
111 | { |
112 | Smode = 1; | |
113 | Hmode = 1; | |
114 | SXmode = 1; | |
7ee7b84d MS |
115 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx)) |
116 | as_warn (_("could not set architecture and machine")); | |
7ee7b84d MS |
117 | } |
118 | ||
600e9c99 | 119 | static void |
b54a3392 | 120 | h8300sxnmode (int arg ATTRIBUTE_UNUSED) |
f4984206 RS |
121 | { |
122 | Smode = 1; | |
123 | Hmode = 1; | |
124 | SXmode = 1; | |
125 | Nmode = 1; | |
f4984206 RS |
126 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn)) |
127 | as_warn (_("could not set architecture and machine")); | |
f4984206 RS |
128 | } |
129 | ||
600e9c99 | 130 | static void |
b54a3392 | 131 | sbranch (int size) |
252b5132 RH |
132 | { |
133 | bsize = size; | |
134 | } | |
135 | ||
70d6ecf3 | 136 | static void |
b54a3392 | 137 | pint (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
138 | { |
139 | cons (Hmode ? 4 : 2); | |
140 | } | |
141 | ||
3048287a NC |
142 | /* This table describes all the machine specific pseudo-ops the assembler |
143 | has to support. The fields are: | |
144 | pseudo-op name without dot | |
145 | function to call to execute this pseudo-op | |
146 | Integer arg to pass to the function. */ | |
147 | ||
252b5132 RH |
148 | const pseudo_typeS md_pseudo_table[] = |
149 | { | |
7ee7b84d | 150 | {"h8300h", h8300hmode, 0}, |
8d9cd6b1 | 151 | {"h8300hn", h8300hnmode, 0}, |
7ee7b84d | 152 | {"h8300s", h8300smode, 0}, |
8d9cd6b1 | 153 | {"h8300sn", h8300snmode, 0}, |
7ee7b84d | 154 | {"h8300sx", h8300sxmode, 0}, |
f4984206 | 155 | {"h8300sxn", h8300sxnmode, 0}, |
252b5132 RH |
156 | {"sbranch", sbranch, L_8}, |
157 | {"lbranch", sbranch, L_16}, | |
158 | ||
159 | {"int", pint, 0}, | |
160 | {"data.b", cons, 1}, | |
161 | {"data.w", cons, 2}, | |
162 | {"data.l", cons, 4}, | |
163 | {"form", listing_psize, 0}, | |
164 | {"heading", listing_title, 0}, | |
7ee7b84d MS |
165 | {"import", s_ignore, 0}, |
166 | {"page", listing_eject, 0}, | |
252b5132 RH |
167 | {"program", s_ignore, 0}, |
168 | {0, 0, 0} | |
169 | }; | |
170 | ||
252b5132 RH |
171 | const char EXP_CHARS[] = "eE"; |
172 | ||
3048287a NC |
173 | /* Chars that mean this number is a floating point constant |
174 | As in 0f12.456 | |
175 | or 0d1.2345e12. */ | |
252b5132 RH |
176 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
177 | ||
3048287a | 178 | static struct hash_control *opcode_hash_control; /* Opcode mnemonics. */ |
252b5132 | 179 | |
70d6ecf3 AM |
180 | /* This function is called once, at assembler startup time. This |
181 | should set up all the tables, etc. that the MD part of the assembler | |
182 | needs. */ | |
3048287a | 183 | |
252b5132 | 184 | void |
b54a3392 | 185 | md_begin (void) |
252b5132 | 186 | { |
a720f7bc | 187 | unsigned int nopcodes; |
7ee7b84d | 188 | struct h8_opcode *p, *p1; |
a720f7bc | 189 | struct h8_instruction *pi; |
252b5132 RH |
190 | char prev_buffer[100]; |
191 | int idx = 0; | |
192 | ||
83e20b45 JL |
193 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300)) |
194 | as_warn (_("could not set architecture and machine")); | |
83e20b45 | 195 | |
252b5132 RH |
196 | opcode_hash_control = hash_new (); |
197 | prev_buffer[0] = 0; | |
198 | ||
a720f7bc KD |
199 | nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); |
200 | ||
201 | h8_instructions = (struct h8_instruction *) | |
202 | xmalloc (nopcodes * sizeof (struct h8_instruction)); | |
203 | ||
7ee7b84d MS |
204 | pi = h8_instructions; |
205 | p1 = h8_opcodes; | |
206 | /* We do a minimum amount of sorting on the opcode table; this is to | |
207 | make it easy to describe the mova instructions without unnecessary | |
208 | code duplication. | |
209 | Sorting only takes place inside blocks of instructions of the form | |
210 | X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */ | |
211 | while (p1) | |
252b5132 | 212 | { |
7ee7b84d MS |
213 | struct h8_opcode *first_skipped = 0; |
214 | int len, cmplen = 0; | |
215 | char *src = p1->name; | |
216 | char *dst, *buffer; | |
252b5132 | 217 | |
7ee7b84d MS |
218 | if (p1->name == 0) |
219 | break; | |
220 | /* Strip off any . part when inserting the opcode and only enter | |
221 | unique codes into the hash table. */ | |
222 | dst = buffer = malloc (strlen (src) + 1); | |
252b5132 RH |
223 | while (*src) |
224 | { | |
225 | if (*src == '.') | |
226 | { | |
227 | src++; | |
252b5132 RH |
228 | break; |
229 | } | |
7ee7b84d MS |
230 | if (*src == '/') |
231 | cmplen = src - p1->name + 1; | |
252b5132 RH |
232 | *dst++ = *src++; |
233 | } | |
7ee7b84d MS |
234 | *dst = 0; |
235 | len = dst - buffer; | |
236 | if (cmplen == 0) | |
237 | cmplen = len; | |
238 | hash_insert (opcode_hash_control, buffer, (char *) pi); | |
239 | strcpy (prev_buffer, buffer); | |
240 | idx++; | |
241 | ||
242 | for (p = p1; p->name; p++) | |
252b5132 | 243 | { |
7ee7b84d MS |
244 | /* A negative TIME is used to indicate that we've added this opcode |
245 | already. */ | |
246 | if (p->time == -1) | |
247 | continue; | |
248 | if (strncmp (p->name, buffer, cmplen) != 0 | |
249 | || (p->name[cmplen] != '\0' && p->name[cmplen] != '.' | |
250 | && p->name[cmplen - 1] != '/')) | |
251 | { | |
252 | if (first_skipped == 0) | |
253 | first_skipped = p; | |
254 | break; | |
255 | } | |
256 | if (strncmp (p->name, buffer, len) != 0) | |
257 | { | |
258 | if (first_skipped == 0) | |
259 | first_skipped = p; | |
260 | continue; | |
261 | } | |
262 | ||
263 | p->time = -1; | |
264 | pi->size = p->name[len] == '.' ? p->name[len + 1] : 0; | |
265 | pi->idx = idx; | |
252b5132 | 266 | |
7ee7b84d MS |
267 | /* Find the number of operands. */ |
268 | pi->noperands = 0; | |
269 | while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E) | |
270 | pi->noperands++; | |
70d6ecf3 | 271 | |
7ee7b84d MS |
272 | /* Find the length of the opcode in bytes. */ |
273 | pi->length = 0; | |
274 | while (p->data.nib[pi->length * 2] != (op_type) E) | |
275 | pi->length++; | |
a720f7bc | 276 | |
7ee7b84d MS |
277 | pi->opcode = p; |
278 | pi++; | |
279 | } | |
280 | p1 = first_skipped; | |
252b5132 RH |
281 | } |
282 | ||
a720f7bc KD |
283 | /* Add entry for the NULL vector terminator. */ |
284 | pi->length = 0; | |
285 | pi->noperands = 0; | |
286 | pi->idx = 0; | |
287 | pi->size = 0; | |
7ee7b84d | 288 | pi->opcode = 0; |
a720f7bc | 289 | |
252b5132 RH |
290 | linkrelax = 1; |
291 | } | |
292 | ||
252b5132 RH |
293 | struct h8_op |
294 | { | |
295 | op_type mode; | |
296 | unsigned reg; | |
297 | expressionS exp; | |
298 | }; | |
299 | ||
b54a3392 KH |
300 | static void clever_message (const struct h8_instruction *, struct h8_op *); |
301 | static void fix_operand_size (struct h8_op *, int); | |
302 | static void build_bytes (const struct h8_instruction *, struct h8_op *); | |
bcb012d3 | 303 | static void do_a_fix_imm (int, int, struct h8_op *, int, const struct h8_instruction *); |
b54a3392 KH |
304 | static void check_operand (struct h8_op *, unsigned int, char *); |
305 | static const struct h8_instruction * get_specific (const struct h8_instruction *, struct h8_op *, int) ; | |
306 | static char *get_operands (unsigned, char *, struct h8_op *); | |
307 | static void get_operand (char **, struct h8_op *, int); | |
308 | static int parse_reg (char *, op_type *, unsigned *, int); | |
309 | static char *skip_colonthing (char *, int *); | |
310 | static char *parse_exp (char *, struct h8_op *); | |
311 | ||
312 | static int constant_fits_width_p (struct h8_op *, unsigned int); | |
313 | static int constant_fits_size_p (struct h8_op *, int, int); | |
7ee7b84d | 314 | |
252b5132 RH |
315 | /* |
316 | parse operands | |
317 | WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp | |
318 | r0l,r0h,..r7l,r7h | |
319 | @WREG | |
320 | @WREG+ | |
321 | @-WREG | |
322 | #const | |
323 | ccr | |
324 | */ | |
325 | ||
bc0d738a NC |
326 | /* Try to parse a reg name. Return the number of chars consumed. */ |
327 | ||
40f09f82 | 328 | static int |
b54a3392 | 329 | parse_reg (char *src, op_type *mode, unsigned int *reg, int direction) |
252b5132 RH |
330 | { |
331 | char *end; | |
332 | int len; | |
333 | ||
70d6ecf3 | 334 | /* Cribbed from get_symbol_end. */ |
252b5132 RH |
335 | if (!is_name_beginner (*src) || *src == '\001') |
336 | return 0; | |
70d6ecf3 | 337 | end = src + 1; |
7ee7b84d | 338 | while ((is_part_of_name (*end) && *end != '.') || *end == '\001') |
252b5132 RH |
339 | end++; |
340 | len = end - src; | |
341 | ||
7ee7b84d | 342 | if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
343 | { |
344 | *mode = PSIZE | REG | direction; | |
345 | *reg = 7; | |
346 | return len; | |
347 | } | |
7ee7b84d MS |
348 | if (len == 3 && |
349 | TOLOWER (src[0]) == 'c' && | |
350 | TOLOWER (src[1]) == 'c' && | |
351 | TOLOWER (src[2]) == 'r') | |
252b5132 RH |
352 | { |
353 | *mode = CCR; | |
354 | *reg = 0; | |
355 | return len; | |
356 | } | |
7ee7b84d MS |
357 | if (len == 3 && |
358 | TOLOWER (src[0]) == 'e' && | |
359 | TOLOWER (src[1]) == 'x' && | |
360 | TOLOWER (src[2]) == 'r') | |
252b5132 RH |
361 | { |
362 | *mode = EXR; | |
7ee7b84d MS |
363 | *reg = 1; |
364 | return len; | |
365 | } | |
366 | if (len == 3 && | |
367 | TOLOWER (src[0]) == 'v' && | |
368 | TOLOWER (src[1]) == 'b' && | |
369 | TOLOWER (src[2]) == 'r') | |
370 | { | |
371 | *mode = VBR; | |
372 | *reg = 6; | |
373 | return len; | |
374 | } | |
375 | if (len == 3 && | |
376 | TOLOWER (src[0]) == 's' && | |
377 | TOLOWER (src[1]) == 'b' && | |
378 | TOLOWER (src[2]) == 'r') | |
379 | { | |
380 | *mode = SBR; | |
381 | *reg = 7; | |
252b5132 RH |
382 | return len; |
383 | } | |
7ee7b84d | 384 | if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
385 | { |
386 | *mode = PSIZE | REG | direction; | |
387 | *reg = 6; | |
388 | return len; | |
389 | } | |
7ee7b84d MS |
390 | if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
391 | src[2] >= '0' && src[2] <= '7') | |
252b5132 RH |
392 | { |
393 | *mode = L_32 | REG | direction; | |
394 | *reg = src[2] - '0'; | |
395 | if (!Hmode) | |
396 | as_warn (_("Reg not valid for H8/300")); | |
397 | return len; | |
398 | } | |
7ee7b84d | 399 | if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7') |
252b5132 RH |
400 | { |
401 | *mode = L_16 | REG | direction; | |
402 | *reg = src[1] - '0' + 8; | |
403 | if (!Hmode) | |
404 | as_warn (_("Reg not valid for H8/300")); | |
405 | return len; | |
406 | } | |
407 | ||
7ee7b84d | 408 | if (TOLOWER (src[0]) == 'r') |
252b5132 RH |
409 | { |
410 | if (src[1] >= '0' && src[1] <= '7') | |
411 | { | |
7ee7b84d | 412 | if (len == 3 && TOLOWER (src[2]) == 'l') |
252b5132 RH |
413 | { |
414 | *mode = L_8 | REG | direction; | |
415 | *reg = (src[1] - '0') + 8; | |
416 | return len; | |
417 | } | |
7ee7b84d | 418 | if (len == 3 && TOLOWER (src[2]) == 'h') |
252b5132 RH |
419 | { |
420 | *mode = L_8 | REG | direction; | |
421 | *reg = (src[1] - '0'); | |
422 | return len; | |
423 | } | |
424 | if (len == 2) | |
425 | { | |
426 | *mode = L_16 | REG | direction; | |
427 | *reg = (src[1] - '0'); | |
428 | return len; | |
429 | } | |
430 | } | |
431 | } | |
432 | ||
433 | return 0; | |
434 | } | |
435 | ||
1b680e4f RS |
436 | |
437 | /* Parse an immediate or address-related constant and store it in OP. | |
438 | If the user also specifies the operand's size, store that size | |
439 | in OP->MODE, otherwise leave it for later code to decide. */ | |
440 | ||
40f09f82 | 441 | static char * |
b54a3392 | 442 | parse_exp (char *src, struct h8_op *op) |
252b5132 | 443 | { |
1b680e4f | 444 | char *save; |
252b5132 | 445 | |
1b680e4f RS |
446 | save = input_line_pointer; |
447 | input_line_pointer = src; | |
448 | expression (&op->exp); | |
449 | if (op->exp.X_op == O_absent) | |
252b5132 | 450 | as_bad (_("missing operand")); |
1b680e4f | 451 | src = input_line_pointer; |
252b5132 | 452 | input_line_pointer = save; |
1b680e4f RS |
453 | |
454 | return skip_colonthing (src, &op->mode); | |
252b5132 RH |
455 | } |
456 | ||
1b680e4f RS |
457 | |
458 | /* If SRC starts with an explicit operand size, skip it and store the size | |
459 | in *MODE. Leave *MODE unchanged otherwise. */ | |
460 | ||
252b5132 | 461 | static char * |
b54a3392 | 462 | skip_colonthing (char *src, int *mode) |
252b5132 | 463 | { |
1b680e4f | 464 | if (*src == ':') |
252b5132 | 465 | { |
1b680e4f | 466 | src++; |
252b5132 | 467 | *mode &= ~SIZE; |
1b680e4f | 468 | if (src[0] == '8' && !ISDIGIT (src[1])) |
7ee7b84d | 469 | *mode |= L_8; |
1b680e4f | 470 | else if (src[0] == '2' && !ISDIGIT (src[1])) |
7ee7b84d | 471 | *mode |= L_2; |
1b680e4f | 472 | else if (src[0] == '3' && !ISDIGIT (src[1])) |
7ee7b84d | 473 | *mode |= L_3; |
1b680e4f | 474 | else if (src[0] == '4' && !ISDIGIT (src[1])) |
7ee7b84d | 475 | *mode |= L_4; |
1b680e4f | 476 | else if (src[0] == '5' && !ISDIGIT (src[1])) |
7ee7b84d | 477 | *mode |= L_5; |
1b680e4f | 478 | else if (src[0] == '2' && src[1] == '4' && !ISDIGIT (src[2])) |
7ee7b84d | 479 | *mode |= L_24; |
1b680e4f | 480 | else if (src[0] == '3' && src[1] == '2' && !ISDIGIT (src[2])) |
7ee7b84d | 481 | *mode |= L_32; |
1b680e4f | 482 | else if (src[0] == '1' && src[1] == '6' && !ISDIGIT (src[2])) |
7ee7b84d | 483 | *mode |= L_16; |
252b5132 | 484 | else |
7ee7b84d MS |
485 | as_bad (_("invalid operand size requested")); |
486 | ||
1b680e4f RS |
487 | while (ISDIGIT (*src)) |
488 | src++; | |
252b5132 | 489 | } |
1b680e4f | 490 | return src; |
252b5132 RH |
491 | } |
492 | ||
493 | /* The many forms of operand: | |
494 | ||
495 | Rn Register direct | |
496 | @Rn Register indirect | |
497 | @(exp[:16], Rn) Register indirect with displacement | |
498 | @Rn+ | |
499 | @-Rn | |
70d6ecf3 AM |
500 | @aa:8 absolute 8 bit |
501 | @aa:16 absolute 16 bit | |
252b5132 RH |
502 | @aa absolute 16 bit |
503 | ||
504 | #xx[:size] immediate data | |
70d6ecf3 | 505 | @(exp:[8], pc) pc rel |
3048287a | 506 | @@aa[:8] memory indirect. */ |
252b5132 | 507 | |
7ee7b84d | 508 | static int |
b54a3392 | 509 | constant_fits_width_p (struct h8_op *operand, unsigned int width) |
7ee7b84d MS |
510 | { |
511 | return ((operand->exp.X_add_number & ~width) == 0 | |
512 | || (operand->exp.X_add_number | width) == (unsigned)(~0)); | |
513 | } | |
514 | ||
515 | static int | |
b54a3392 | 516 | constant_fits_size_p (struct h8_op *operand, int size, int no_symbols) |
7ee7b84d MS |
517 | { |
518 | offsetT num = operand->exp.X_add_number; | |
519 | if (no_symbols | |
520 | && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0)) | |
521 | return 0; | |
522 | switch (size) | |
523 | { | |
524 | case L_2: | |
525 | return (num & ~3) == 0; | |
526 | case L_3: | |
527 | return (num & ~7) == 0; | |
528 | case L_3NZ: | |
529 | return num >= 1 && num < 8; | |
530 | case L_4: | |
531 | return (num & ~15) == 0; | |
532 | case L_5: | |
533 | return num >= 1 && num < 32; | |
534 | case L_8: | |
535 | return (num & ~0xFF) == 0 || ((unsigned)num | 0x7F) == ~0u; | |
536 | case L_8U: | |
537 | return (num & ~0xFF) == 0; | |
538 | case L_16: | |
539 | return (num & ~0xFFFF) == 0 || ((unsigned)num | 0x7FFF) == ~0u; | |
540 | case L_16U: | |
541 | return (num & ~0xFFFF) == 0; | |
542 | case L_32: | |
543 | return 1; | |
544 | default: | |
545 | abort (); | |
546 | } | |
547 | } | |
548 | ||
252b5132 | 549 | static void |
b54a3392 | 550 | get_operand (char **ptr, struct h8_op *op, int direction) |
252b5132 RH |
551 | { |
552 | char *src = *ptr; | |
553 | op_type mode; | |
554 | unsigned int num; | |
555 | unsigned int len; | |
556 | ||
7ee7b84d | 557 | op->mode = 0; |
252b5132 | 558 | |
3048287a NC |
559 | /* Check for '(' and ')' for instructions ldm and stm. */ |
560 | if (src[0] == '(' && src[8] == ')') | |
561 | ++ src; | |
562 | ||
252b5132 RH |
563 | /* Gross. Gross. ldm and stm have a format not easily handled |
564 | by get_operand. We deal with it explicitly here. */ | |
7ee7b84d MS |
565 | if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
566 | ISDIGIT (src[2]) && src[3] == '-' && | |
567 | TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6])) | |
252b5132 RH |
568 | { |
569 | int low, high; | |
570 | ||
571 | low = src[2] - '0'; | |
572 | high = src[6] - '0'; | |
573 | ||
4892e510 NC |
574 | /* Check register pair's validity as per tech note TN-H8*-193A/E |
575 | from Renesas for H8S and H8SX hardware manual. */ | |
576 | if ( !(low == 0 && (high == 1 || high == 2 || high == 3)) | |
577 | && !(low == 1 && (high == 2 || high == 3 || high == 4) && SXmode) | |
578 | && !(low == 2 && (high == 3 || ((high == 4 || high == 5) && SXmode))) | |
579 | && !(low == 3 && (high == 4 || high == 5 || high == 6) && SXmode) | |
580 | && !(low == 4 && (high == 5 || high == 6)) | |
b4f16abb | 581 | && !(low == 4 && high == 7 && SXmode) |
4892e510 NC |
582 | && !(low == 5 && (high == 6 || high == 7) && SXmode) |
583 | && !(low == 6 && high == 7 && SXmode)) | |
252b5132 RH |
584 | as_bad (_("Invalid register list for ldm/stm\n")); |
585 | ||
252b5132 RH |
586 | /* Even sicker. We encode two registers into op->reg. One |
587 | for the low register to save, the other for the high | |
588 | register to save; we also set the high bit in op->reg | |
589 | so we know this is "very special". */ | |
590 | op->reg = 0x80000000 | (high << 8) | low; | |
591 | op->mode = REG; | |
3048287a NC |
592 | if (src[7] == ')') |
593 | *ptr = src + 8; | |
594 | else | |
595 | *ptr = src + 7; | |
252b5132 RH |
596 | return; |
597 | } | |
598 | ||
599 | len = parse_reg (src, &op->mode, &op->reg, direction); | |
600 | if (len) | |
601 | { | |
7ee7b84d MS |
602 | src += len; |
603 | if (*src == '.') | |
604 | { | |
605 | int size = op->mode & SIZE; | |
606 | switch (src[1]) | |
607 | { | |
608 | case 'l': case 'L': | |
609 | if (size != L_32) | |
610 | as_warn (_("mismatch between register and suffix")); | |
611 | op->mode = (op->mode & ~MODE) | LOWREG; | |
612 | break; | |
613 | case 'w': case 'W': | |
614 | if (size != L_32 && size != L_16) | |
615 | as_warn (_("mismatch between register and suffix")); | |
616 | op->mode = (op->mode & ~MODE) | LOWREG; | |
617 | op->mode = (op->mode & ~SIZE) | L_16; | |
618 | break; | |
619 | case 'b': case 'B': | |
620 | op->mode = (op->mode & ~MODE) | LOWREG; | |
621 | if (size != L_32 && size != L_8) | |
622 | as_warn (_("mismatch between register and suffix")); | |
623 | op->mode = (op->mode & ~MODE) | LOWREG; | |
624 | op->mode = (op->mode & ~SIZE) | L_8; | |
625 | break; | |
626 | default: | |
20203fb9 | 627 | as_warn (_("invalid suffix after register.")); |
7ee7b84d MS |
628 | break; |
629 | } | |
630 | src += 2; | |
631 | } | |
632 | *ptr = src; | |
252b5132 RH |
633 | return; |
634 | } | |
635 | ||
636 | if (*src == '@') | |
637 | { | |
638 | src++; | |
639 | if (*src == '@') | |
640 | { | |
1b680e4f | 641 | *ptr = parse_exp (src + 1, op); |
7ee7b84d MS |
642 | if (op->exp.X_add_number >= 0x100) |
643 | { | |
d4e2de6b | 644 | int divisor = 1; |
7ee7b84d MS |
645 | |
646 | op->mode = VECIND; | |
647 | /* FIXME : 2? or 4? */ | |
648 | if (op->exp.X_add_number >= 0x400) | |
649 | as_bad (_("address too high for vector table jmp/jsr")); | |
650 | else if (op->exp.X_add_number >= 0x200) | |
651 | divisor = 4; | |
652 | else | |
653 | divisor = 2; | |
654 | ||
655 | op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80; | |
656 | } | |
657 | else | |
658 | op->mode = MEMIND; | |
252b5132 | 659 | return; |
252b5132 RH |
660 | } |
661 | ||
7ee7b84d | 662 | if (*src == '-' || *src == '+') |
252b5132 | 663 | { |
1b680e4f | 664 | len = parse_reg (src + 1, &mode, &num, direction); |
252b5132 RH |
665 | if (len == 0) |
666 | { | |
70d6ecf3 | 667 | /* Oops, not a reg after all, must be ordinary exp. */ |
1b680e4f RS |
668 | op->mode = ABS | direction; |
669 | *ptr = parse_exp (src, op); | |
252b5132 | 670 | return; |
252b5132 RH |
671 | } |
672 | ||
d4e2de6b NC |
673 | if (((mode & SIZE) != PSIZE) |
674 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
675 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 676 | as_bad (_("Wrong size pointer register for architecture.")); |
1b680e4f RS |
677 | |
678 | op->mode = src[0] == '-' ? RDPREDEC : RDPREINC; | |
252b5132 | 679 | op->reg = num; |
1b680e4f | 680 | *ptr = src + 1 + len; |
252b5132 RH |
681 | return; |
682 | } | |
683 | if (*src == '(') | |
684 | { | |
252b5132 RH |
685 | src++; |
686 | ||
7ee7b84d MS |
687 | /* See if this is @(ERn.x, PC). */ |
688 | len = parse_reg (src, &mode, &op->reg, direction); | |
689 | if (len != 0 && (mode & MODE) == REG && src[len] == '.') | |
690 | { | |
691 | switch (TOLOWER (src[len + 1])) | |
692 | { | |
693 | case 'b': | |
694 | mode = PCIDXB | direction; | |
695 | break; | |
696 | case 'w': | |
697 | mode = PCIDXW | direction; | |
698 | break; | |
699 | case 'l': | |
700 | mode = PCIDXL | direction; | |
701 | break; | |
702 | default: | |
703 | mode = 0; | |
704 | break; | |
705 | } | |
706 | if (mode | |
707 | && src[len + 2] == ',' | |
708 | && TOLOWER (src[len + 3]) != 'p' | |
709 | && TOLOWER (src[len + 4]) != 'c' | |
710 | && src[len + 5] != ')') | |
711 | { | |
712 | *ptr = src + len + 6; | |
713 | op->mode |= mode; | |
714 | return; | |
715 | } | |
716 | /* Fall through into disp case - the grammar is somewhat | |
717 | ambiguous, so we should try whether it's a DISP operand | |
718 | after all ("ER3.L" might be a poorly named label...). */ | |
719 | } | |
720 | ||
721 | /* Disp. */ | |
722 | ||
70d6ecf3 | 723 | /* Start off assuming a 16 bit offset. */ |
252b5132 | 724 | |
1b680e4f | 725 | src = parse_exp (src, op); |
252b5132 RH |
726 | if (*src == ')') |
727 | { | |
252b5132 | 728 | op->mode |= ABS | direction; |
1b680e4f | 729 | *ptr = src + 1; |
252b5132 RH |
730 | return; |
731 | } | |
732 | ||
733 | if (*src != ',') | |
734 | { | |
735 | as_bad (_("expected @(exp, reg16)")); | |
736 | return; | |
252b5132 RH |
737 | } |
738 | src++; | |
739 | ||
740 | len = parse_reg (src, &mode, &op->reg, direction); | |
7ee7b84d | 741 | if (len == 0 || (mode & MODE) != REG) |
252b5132 RH |
742 | { |
743 | as_bad (_("expected @(exp, reg16)")); | |
744 | return; | |
745 | } | |
252b5132 | 746 | src += len; |
7ee7b84d MS |
747 | if (src[0] == '.') |
748 | { | |
749 | switch (TOLOWER (src[1])) | |
750 | { | |
751 | case 'b': | |
752 | op->mode |= INDEXB | direction; | |
753 | break; | |
754 | case 'w': | |
755 | op->mode |= INDEXW | direction; | |
756 | break; | |
757 | case 'l': | |
758 | op->mode |= INDEXL | direction; | |
759 | break; | |
760 | default: | |
761 | as_bad (_("expected .L, .W or .B for register in indexed addressing mode")); | |
762 | } | |
763 | src += 2; | |
764 | op->reg &= 7; | |
765 | } | |
766 | else | |
767 | op->mode |= DISP | direction; | |
1b680e4f | 768 | src = skip_colonthing (src, &op->mode); |
252b5132 RH |
769 | |
770 | if (*src != ')' && '(') | |
771 | { | |
772 | as_bad (_("expected @(exp, reg16)")); | |
773 | return; | |
774 | } | |
775 | *ptr = src + 1; | |
252b5132 RH |
776 | return; |
777 | } | |
778 | len = parse_reg (src, &mode, &num, direction); | |
779 | ||
780 | if (len) | |
781 | { | |
782 | src += len; | |
7ee7b84d | 783 | if (*src == '+' || *src == '-') |
252b5132 | 784 | { |
d4e2de6b NC |
785 | if (((mode & SIZE) != PSIZE) |
786 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
787 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 788 | as_bad (_("Wrong size pointer register for architecture.")); |
7ee7b84d | 789 | op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC; |
252b5132 | 790 | op->reg = num; |
7ee7b84d | 791 | src++; |
252b5132 RH |
792 | *ptr = src; |
793 | return; | |
794 | } | |
d4e2de6b NC |
795 | if (((mode & SIZE) != PSIZE) |
796 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
797 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 RH |
798 | as_bad (_("Wrong size pointer register for architecture.")); |
799 | ||
800 | op->mode = direction | IND | PSIZE; | |
801 | op->reg = num; | |
802 | *ptr = src; | |
803 | ||
804 | return; | |
805 | } | |
806 | else | |
807 | { | |
808 | /* must be a symbol */ | |
809 | ||
810 | op->mode = ABS | direction; | |
1b680e4f | 811 | *ptr = parse_exp (src, op); |
252b5132 RH |
812 | return; |
813 | } | |
814 | } | |
815 | ||
252b5132 RH |
816 | if (*src == '#') |
817 | { | |
252b5132 | 818 | op->mode = IMM; |
1b680e4f | 819 | *ptr = parse_exp (src + 1, op); |
252b5132 RH |
820 | return; |
821 | } | |
7ee7b84d MS |
822 | else if (strncmp (src, "mach", 4) == 0 || |
823 | strncmp (src, "macl", 4) == 0 || | |
824 | strncmp (src, "MACH", 4) == 0 || | |
825 | strncmp (src, "MACL", 4) == 0) | |
252b5132 | 826 | { |
7ee7b84d | 827 | op->reg = TOLOWER (src[3]) == 'l'; |
252b5132 RH |
828 | op->mode = MACREG; |
829 | *ptr = src + 4; | |
830 | return; | |
831 | } | |
832 | else | |
833 | { | |
1b680e4f RS |
834 | op->mode = PCREL; |
835 | *ptr = parse_exp (src, op); | |
252b5132 RH |
836 | } |
837 | } | |
838 | ||
70d6ecf3 | 839 | static char * |
b54a3392 | 840 | get_operands (unsigned int noperands, char *op_end, struct h8_op *operand) |
252b5132 RH |
841 | { |
842 | char *ptr = op_end; | |
843 | ||
844 | switch (noperands) | |
845 | { | |
846 | case 0: | |
252b5132 RH |
847 | break; |
848 | ||
849 | case 1: | |
850 | ptr++; | |
7ee7b84d | 851 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
852 | if (*ptr == ',') |
853 | { | |
854 | ptr++; | |
7ee7b84d | 855 | get_operand (&ptr, operand + 1, DST); |
252b5132 | 856 | } |
252b5132 | 857 | break; |
70d6ecf3 | 858 | |
252b5132 RH |
859 | case 2: |
860 | ptr++; | |
7ee7b84d | 861 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
862 | if (*ptr == ',') |
863 | ptr++; | |
7ee7b84d MS |
864 | get_operand (&ptr, operand + 1, DST); |
865 | break; | |
866 | ||
867 | case 3: | |
868 | ptr++; | |
869 | get_operand (&ptr, operand + 0, SRC); | |
870 | if (*ptr == ',') | |
871 | ptr++; | |
872 | get_operand (&ptr, operand + 1, DST); | |
873 | if (*ptr == ',') | |
874 | ptr++; | |
875 | get_operand (&ptr, operand + 2, OP3); | |
252b5132 RH |
876 | break; |
877 | ||
878 | default: | |
879 | abort (); | |
880 | } | |
881 | ||
252b5132 RH |
882 | return ptr; |
883 | } | |
884 | ||
7ee7b84d MS |
885 | /* MOVA has special requirements. Rather than adding twice the amount of |
886 | addressing modes, we simply special case it a bit. */ | |
887 | static void | |
888 | get_mova_operands (char *op_end, struct h8_op *operand) | |
889 | { | |
890 | char *ptr = op_end; | |
891 | ||
892 | if (ptr[1] != '@' || ptr[2] != '(') | |
893 | goto error; | |
894 | ptr += 3; | |
895 | operand[0].mode = 0; | |
1b680e4f | 896 | ptr = parse_exp (ptr, &operand[0]); |
7ee7b84d MS |
897 | |
898 | if (*ptr !=',') | |
899 | goto error; | |
900 | ptr++; | |
901 | get_operand (&ptr, operand + 1, DST); | |
902 | ||
903 | if (*ptr =='.') | |
904 | { | |
905 | ptr++; | |
906 | switch (*ptr++) | |
907 | { | |
908 | case 'b': case 'B': | |
909 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
910 | break; | |
911 | case 'w': case 'W': | |
912 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
913 | break; | |
914 | case 'l': case 'L': | |
915 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
916 | break; | |
917 | default: | |
918 | goto error; | |
919 | } | |
920 | } | |
921 | else if ((operand[1].mode & MODE) == LOWREG) | |
922 | { | |
923 | switch (operand[1].mode & SIZE) | |
924 | { | |
925 | case L_8: | |
926 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
927 | break; | |
928 | case L_16: | |
929 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
930 | break; | |
931 | case L_32: | |
932 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
933 | break; | |
934 | default: | |
935 | goto error; | |
936 | } | |
937 | } | |
938 | else | |
939 | goto error; | |
940 | ||
941 | if (*ptr++ != ')' || *ptr++ != ',') | |
942 | goto error; | |
943 | get_operand (&ptr, operand + 2, OP3); | |
944 | /* See if we can use the short form of MOVA. */ | |
945 | if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG) | |
946 | && (operand[2].mode & MODE) == REG | |
947 | && (operand[1].reg & 7) == (operand[2].reg & 7)) | |
948 | { | |
949 | operand[1].mode = operand[2].mode = 0; | |
950 | operand[0].reg = operand[2].reg & 7; | |
951 | } | |
952 | return; | |
953 | ||
954 | error: | |
955 | as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\"")); | |
7ee7b84d MS |
956 | } |
957 | ||
958 | static void | |
959 | get_rtsl_operands (char *ptr, struct h8_op *operand) | |
960 | { | |
2132e3a3 AM |
961 | int mode, len, type = 0; |
962 | unsigned int num, num2; | |
7ee7b84d MS |
963 | |
964 | ptr++; | |
965 | if (*ptr == '(') | |
966 | { | |
967 | ptr++; | |
968 | type = 1; | |
969 | } | |
970 | len = parse_reg (ptr, &mode, &num, SRC); | |
971 | if (len == 0 || (mode & MODE) != REG) | |
972 | { | |
973 | as_bad (_("expected register")); | |
974 | return; | |
975 | } | |
0613284f RS |
976 | ptr += len; |
977 | if (*ptr == '-') | |
7ee7b84d | 978 | { |
0613284f | 979 | len = parse_reg (++ptr, &mode, &num2, SRC); |
7ee7b84d MS |
980 | if (len == 0 || (mode & MODE) != REG) |
981 | { | |
982 | as_bad (_("expected register")); | |
983 | return; | |
984 | } | |
985 | ptr += len; | |
7ee7b84d MS |
986 | /* CONST_xxx are used as placeholders in the opcode table. */ |
987 | num = num2 - num; | |
2132e3a3 | 988 | if (num > 3) |
7ee7b84d MS |
989 | { |
990 | as_bad (_("invalid register list")); | |
991 | return; | |
992 | } | |
993 | } | |
994 | else | |
995 | num2 = num, num = 0; | |
0613284f RS |
996 | if (type == 1 && *ptr++ != ')') |
997 | { | |
998 | as_bad (_("expected closing paren")); | |
999 | return; | |
1000 | } | |
7ee7b84d MS |
1001 | operand[0].mode = RS32; |
1002 | operand[1].mode = RD32; | |
1003 | operand[0].reg = num; | |
1004 | operand[1].reg = num2; | |
1005 | } | |
1006 | ||
252b5132 RH |
1007 | /* Passed a pointer to a list of opcodes which use different |
1008 | addressing modes, return the opcode which matches the opcodes | |
70d6ecf3 | 1009 | provided. */ |
3048287a | 1010 | |
a720f7bc | 1011 | static const struct h8_instruction * |
b54a3392 KH |
1012 | get_specific (const struct h8_instruction *instruction, |
1013 | struct h8_op *operands, int size) | |
252b5132 | 1014 | { |
a720f7bc | 1015 | const struct h8_instruction *this_try = instruction; |
7ee7b84d | 1016 | const struct h8_instruction *found_other = 0, *found_mismatched = 0; |
252b5132 | 1017 | int found = 0; |
a720f7bc | 1018 | int this_index = instruction->idx; |
7ee7b84d | 1019 | int noperands = 0; |
252b5132 RH |
1020 | |
1021 | /* There's only one ldm/stm and it's easier to just | |
1022 | get out quick for them. */ | |
7ee7b84d MS |
1023 | if (OP_KIND (instruction->opcode->how) == O_LDM |
1024 | || OP_KIND (instruction->opcode->how) == O_STM) | |
252b5132 RH |
1025 | return this_try; |
1026 | ||
7ee7b84d MS |
1027 | while (noperands < 3 && operands[noperands].mode != 0) |
1028 | noperands++; | |
1029 | ||
a720f7bc | 1030 | while (this_index == instruction->idx && !found) |
252b5132 | 1031 | { |
7ee7b84d | 1032 | int this_size; |
252b5132 | 1033 | |
7ee7b84d | 1034 | found = 1; |
a720f7bc | 1035 | this_try = instruction++; |
7ee7b84d | 1036 | this_size = this_try->opcode->how & SN; |
252b5132 | 1037 | |
7ee7b84d MS |
1038 | if (this_try->noperands != noperands) |
1039 | found = 0; | |
1040 | else if (this_try->noperands > 0) | |
252b5132 | 1041 | { |
3048287a | 1042 | int i; |
252b5132 RH |
1043 | |
1044 | for (i = 0; i < this_try->noperands && found; i++) | |
1045 | { | |
a720f7bc | 1046 | op_type op = this_try->opcode->args.nib[i]; |
7ee7b84d MS |
1047 | int op_mode = op & MODE; |
1048 | int op_size = op & SIZE; | |
252b5132 | 1049 | int x = operands[i].mode; |
7ee7b84d MS |
1050 | int x_mode = x & MODE; |
1051 | int x_size = x & SIZE; | |
252b5132 | 1052 | |
7ee7b84d | 1053 | if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG)) |
252b5132 | 1054 | { |
7ee7b84d MS |
1055 | if ((x_size == L_8 && (operands[i].reg & 8) == 0) |
1056 | || (x_size == L_16 && (operands[i].reg & 8) == 8)) | |
1057 | as_warn (_("can't use high part of register in operand %d"), i); | |
1058 | ||
1059 | if (x_size != op_size) | |
1060 | found = 0; | |
252b5132 | 1061 | } |
7ee7b84d | 1062 | else if (op_mode == REG) |
252b5132 | 1063 | { |
7ee7b84d MS |
1064 | if (x_mode == LOWREG) |
1065 | x_mode = REG; | |
1066 | if (x_mode != REG) | |
252b5132 RH |
1067 | found = 0; |
1068 | ||
7ee7b84d MS |
1069 | if (x_size == L_P) |
1070 | x_size = (Hmode ? L_32 : L_16); | |
1071 | if (op_size == L_P) | |
1072 | op_size = (Hmode ? L_32 : L_16); | |
252b5132 | 1073 | |
70d6ecf3 | 1074 | /* The size of the reg is v important. */ |
7ee7b84d | 1075 | if (op_size != x_size) |
252b5132 RH |
1076 | found = 0; |
1077 | } | |
7ee7b84d | 1078 | else if (op_mode & CTRL) /* control register */ |
252b5132 | 1079 | { |
7ee7b84d MS |
1080 | if (!(x_mode & CTRL)) |
1081 | found = 0; | |
1082 | ||
1083 | switch (x_mode) | |
1084 | { | |
1085 | case CCR: | |
1086 | if (op_mode != CCR && | |
1087 | op_mode != CCR_EXR && | |
1088 | op_mode != CC_EX_VB_SB) | |
1089 | found = 0; | |
1090 | break; | |
1091 | case EXR: | |
1092 | if (op_mode != EXR && | |
1093 | op_mode != CCR_EXR && | |
1094 | op_mode != CC_EX_VB_SB) | |
1095 | found = 0; | |
1096 | break; | |
1097 | case MACH: | |
1098 | if (op_mode != MACH && | |
1099 | op_mode != MACREG) | |
1100 | found = 0; | |
1101 | break; | |
1102 | case MACL: | |
1103 | if (op_mode != MACL && | |
1104 | op_mode != MACREG) | |
1105 | found = 0; | |
1106 | break; | |
1107 | case VBR: | |
1108 | if (op_mode != VBR && | |
1109 | op_mode != VBR_SBR && | |
1110 | op_mode != CC_EX_VB_SB) | |
1111 | found = 0; | |
1112 | break; | |
1113 | case SBR: | |
1114 | if (op_mode != SBR && | |
1115 | op_mode != VBR_SBR && | |
1116 | op_mode != CC_EX_VB_SB) | |
1117 | found = 0; | |
1118 | break; | |
1119 | } | |
1120 | } | |
1121 | else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL)) | |
1122 | { | |
1123 | operands[i].mode &= ~MODE; | |
252b5132 | 1124 | operands[i].mode |= ABSJMP; |
70d6ecf3 | 1125 | /* But it may not be 24 bits long. */ |
7ee7b84d | 1126 | if (x_mode == ABS && !Hmode) |
252b5132 RH |
1127 | { |
1128 | operands[i].mode &= ~SIZE; | |
1129 | operands[i].mode |= L_16; | |
1130 | } | |
7ee7b84d MS |
1131 | if ((operands[i].mode & SIZE) == L_32 |
1132 | && (op_mode & SIZE) != L_32) | |
1133 | found = 0; | |
252b5132 | 1134 | } |
7ee7b84d | 1135 | else if (x_mode == IMM && op_mode != IMM) |
252b5132 | 1136 | { |
7ee7b84d MS |
1137 | offsetT num = operands[i].exp.X_add_number; |
1138 | if (op_mode == KBIT || op_mode == DBIT) | |
1139 | /* This is ok if the immediate value is sensible. */; | |
1140 | else if (op_mode == CONST_2) | |
1141 | found = num == 2; | |
1142 | else if (op_mode == CONST_4) | |
1143 | found = num == 4; | |
1144 | else if (op_mode == CONST_8) | |
1145 | found = num == 8; | |
1146 | else if (op_mode == CONST_16) | |
1147 | found = num == 16; | |
1148 | else | |
1149 | found = 0; | |
252b5132 | 1150 | } |
7ee7b84d | 1151 | else if (op_mode == PCREL && op_mode == x_mode) |
252b5132 | 1152 | { |
ba18dd6f | 1153 | /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour: |
7ee7b84d | 1154 | If x_size is L_8, promote it. */ |
ba18dd6f AO |
1155 | if (OP_KIND (this_try->opcode->how) == O_MOVSD |
1156 | || OP_KIND (this_try->opcode->how) == O_BSRBC | |
1157 | || OP_KIND (this_try->opcode->how) == O_BSRBS) | |
7ee7b84d MS |
1158 | if (x_size == L_8) |
1159 | x_size = L_16; | |
1160 | ||
70d6ecf3 | 1161 | /* The size of the displacement is important. */ |
7ee7b84d | 1162 | if (op_size != x_size) |
252b5132 RH |
1163 | found = 0; |
1164 | } | |
7ee7b84d MS |
1165 | else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS |
1166 | || op_mode == INDEXB || op_mode == INDEXW | |
1167 | || op_mode == INDEXL) | |
1168 | && op_mode == x_mode) | |
252b5132 RH |
1169 | { |
1170 | /* Promote a L_24 to L_32 if it makes us match. */ | |
7ee7b84d | 1171 | if (x_size == L_24 && op_size == L_32) |
252b5132 | 1172 | { |
7ee7b84d MS |
1173 | x &= ~SIZE; |
1174 | x |= x_size = L_32; | |
252b5132 | 1175 | } |
7ee7b84d | 1176 | |
7ee7b84d | 1177 | if (((x_size == L_16 && op_size == L_16U) |
2d0d09ca | 1178 | || (x_size == L_8 && op_size == L_8U) |
7ee7b84d MS |
1179 | || (x_size == L_3 && op_size == L_3NZ)) |
1180 | /* We're deliberately more permissive for ABS modes. */ | |
1181 | && (op_mode == ABS | |
1182 | || constant_fits_size_p (operands + i, op_size, | |
1183 | op & NO_SYMBOLS))) | |
1184 | x_size = op_size; | |
1185 | ||
1186 | if (x_size != 0 && op_size != x_size) | |
1187 | found = 0; | |
1188 | else if (x_size == 0 | |
1189 | && ! constant_fits_size_p (operands + i, op_size, | |
1190 | op & NO_SYMBOLS)) | |
252b5132 RH |
1191 | found = 0; |
1192 | } | |
7ee7b84d | 1193 | else if (op_mode != x_mode) |
252b5132 RH |
1194 | { |
1195 | found = 0; | |
70d6ecf3 | 1196 | } |
252b5132 RH |
1197 | } |
1198 | } | |
7ee7b84d MS |
1199 | if (found) |
1200 | { | |
1201 | if ((this_try->opcode->available == AV_H8SX && ! SXmode) | |
d4ea8842 | 1202 | || (this_try->opcode->available == AV_H8S && ! Smode) |
7ee7b84d MS |
1203 | || (this_try->opcode->available == AV_H8H && ! Hmode)) |
1204 | found = 0, found_other = this_try; | |
1205 | else if (this_size != size && (this_size != SN && size != SN)) | |
1206 | found_mismatched = this_try, found = 0; | |
1207 | ||
1208 | } | |
252b5132 RH |
1209 | } |
1210 | if (found) | |
1211 | return this_try; | |
7ee7b84d MS |
1212 | if (found_other) |
1213 | { | |
1214 | as_warn (_("Opcode `%s' with these operand types not available in %s mode"), | |
1215 | found_other->opcode->name, | |
1216 | (! Hmode && ! Smode ? "H8/300" | |
1217 | : SXmode ? "H8sx" | |
1218 | : Smode ? "H8/300S" | |
1219 | : "H8/300H")); | |
1220 | } | |
1221 | else if (found_mismatched) | |
1222 | { | |
1223 | as_warn (_("mismatch between opcode size and operand size")); | |
1224 | return found_mismatched; | |
1225 | } | |
1226 | return 0; | |
252b5132 RH |
1227 | } |
1228 | ||
1229 | static void | |
b54a3392 | 1230 | check_operand (struct h8_op *operand, unsigned int width, char *string) |
252b5132 RH |
1231 | { |
1232 | if (operand->exp.X_add_symbol == 0 | |
1233 | && operand->exp.X_op_symbol == 0) | |
1234 | { | |
70d6ecf3 AM |
1235 | /* No symbol involved, let's look at offset, it's dangerous if |
1236 | any of the high bits are not 0 or ff's, find out by oring or | |
1237 | anding with the width and seeing if the answer is 0 or all | |
1238 | fs. */ | |
252b5132 | 1239 | |
7ee7b84d | 1240 | if (! constant_fits_width_p (operand, width)) |
252b5132 | 1241 | { |
70d6ecf3 | 1242 | if (width == 255 |
252b5132 RH |
1243 | && (operand->exp.X_add_number & 0xff00) == 0xff00) |
1244 | { | |
1245 | /* Just ignore this one - which happens when trying to | |
1246 | fit a 16 bit address truncated into an 8 bit address | |
1247 | of something like bset. */ | |
1248 | } | |
166e23f9 KH |
1249 | else if (strcmp (string, "@") == 0 |
1250 | && width == 0xffff | |
1251 | && (operand->exp.X_add_number & 0xff8000) == 0xff8000) | |
1252 | { | |
1253 | /* Just ignore this one - which happens when trying to | |
1254 | fit a 24 bit address truncated into a 16 bit address | |
1255 | of something like mov.w. */ | |
1256 | } | |
70d6ecf3 | 1257 | else |
252b5132 RH |
1258 | { |
1259 | as_warn (_("operand %s0x%lx out of range."), string, | |
1260 | (unsigned long) operand->exp.X_add_number); | |
1261 | } | |
1262 | } | |
1263 | } | |
252b5132 RH |
1264 | } |
1265 | ||
1266 | /* RELAXMODE has one of 3 values: | |
1267 | ||
1268 | 0 Output a "normal" reloc, no relaxing possible for this insn/reloc | |
1269 | ||
1270 | 1 Output a relaxable 24bit absolute mov.w address relocation | |
1271 | (may relax into a 16bit absolute address). | |
1272 | ||
1273 | 2 Output a relaxable 16/24 absolute mov.b address relocation | |
1274 | (may relax into an 8bit absolute address). */ | |
1275 | ||
1276 | static void | |
bcb012d3 | 1277 | do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode, const struct h8_instruction *this_try) |
252b5132 RH |
1278 | { |
1279 | int idx; | |
1280 | int size; | |
1281 | int where; | |
7ee7b84d | 1282 | char *bytes = frag_now->fr_literal + offset; |
252b5132 | 1283 | |
7ee7b84d | 1284 | char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; |
252b5132 RH |
1285 | |
1286 | if (operand->exp.X_add_symbol == 0) | |
1287 | { | |
252b5132 RH |
1288 | switch (operand->mode & SIZE) |
1289 | { | |
1290 | case L_2: | |
1291 | check_operand (operand, 0x3, t); | |
7ee7b84d | 1292 | bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4); |
252b5132 RH |
1293 | break; |
1294 | case L_3: | |
7ee7b84d | 1295 | case L_3NZ: |
252b5132 | 1296 | check_operand (operand, 0x7, t); |
7ee7b84d MS |
1297 | bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4); |
1298 | break; | |
1299 | case L_4: | |
1300 | check_operand (operand, 0xF, t); | |
1301 | bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4); | |
1302 | break; | |
1303 | case L_5: | |
1304 | check_operand (operand, 0x1F, t); | |
1305 | bytes[0] |= operand->exp.X_add_number & 31; | |
252b5132 RH |
1306 | break; |
1307 | case L_8: | |
7ee7b84d | 1308 | case L_8U: |
252b5132 | 1309 | check_operand (operand, 0xff, t); |
7ee7b84d | 1310 | bytes[0] |= operand->exp.X_add_number; |
252b5132 RH |
1311 | break; |
1312 | case L_16: | |
7ee7b84d | 1313 | case L_16U: |
252b5132 | 1314 | check_operand (operand, 0xffff, t); |
7ee7b84d MS |
1315 | bytes[0] |= operand->exp.X_add_number >> 8; |
1316 | bytes[1] |= operand->exp.X_add_number >> 0; | |
bcb012d3 DD |
1317 | #ifdef OBJ_ELF |
1318 | /* MOVA needs both relocs to relax the second operand properly. */ | |
1319 | if (relaxmode != 0 | |
1320 | && (OP_KIND(this_try->opcode->how) == O_MOVAB | |
1321 | || OP_KIND(this_try->opcode->how) == O_MOVAW | |
1322 | || OP_KIND(this_try->opcode->how) == O_MOVAL)) | |
1323 | { | |
1324 | idx = BFD_RELOC_16; | |
1325 | fix_new_exp (frag_now, offset, 2, &operand->exp, 0, idx); | |
1326 | } | |
1327 | #endif | |
252b5132 RH |
1328 | break; |
1329 | case L_24: | |
1330 | check_operand (operand, 0xffffff, t); | |
7ee7b84d MS |
1331 | bytes[0] |= operand->exp.X_add_number >> 16; |
1332 | bytes[1] |= operand->exp.X_add_number >> 8; | |
1333 | bytes[2] |= operand->exp.X_add_number >> 0; | |
252b5132 RH |
1334 | break; |
1335 | ||
1336 | case L_32: | |
70d6ecf3 | 1337 | /* This should be done with bfd. */ |
7ee7b84d MS |
1338 | bytes[0] |= operand->exp.X_add_number >> 24; |
1339 | bytes[1] |= operand->exp.X_add_number >> 16; | |
1340 | bytes[2] |= operand->exp.X_add_number >> 8; | |
1341 | bytes[3] |= operand->exp.X_add_number >> 0; | |
4132022d AM |
1342 | if (relaxmode != 0) |
1343 | { | |
1344 | idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1; | |
1345 | fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx); | |
1346 | } | |
252b5132 RH |
1347 | break; |
1348 | } | |
252b5132 RH |
1349 | } |
1350 | else | |
1351 | { | |
1352 | switch (operand->mode & SIZE) | |
1353 | { | |
252b5132 RH |
1354 | case L_24: |
1355 | case L_32: | |
1356 | size = 4; | |
1357 | where = (operand->mode & SIZE) == L_24 ? -1 : 0; | |
1358 | if (relaxmode == 2) | |
1359 | idx = R_MOV24B1; | |
1360 | else if (relaxmode == 1) | |
1361 | idx = R_MOVL1; | |
1362 | else | |
1363 | idx = R_RELLONG; | |
1364 | break; | |
1365 | default: | |
70d6ecf3 | 1366 | as_bad (_("Can't work out size of operand.\n")); |
252b5132 | 1367 | case L_16: |
7ee7b84d | 1368 | case L_16U: |
252b5132 RH |
1369 | size = 2; |
1370 | where = 0; | |
1371 | if (relaxmode == 2) | |
1372 | idx = R_MOV16B1; | |
1373 | else | |
1374 | idx = R_RELWORD; | |
4132022d AM |
1375 | operand->exp.X_add_number = |
1376 | ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
7ee7b84d | 1377 | operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1]; |
252b5132 RH |
1378 | break; |
1379 | case L_8: | |
1380 | size = 1; | |
1381 | where = 0; | |
1382 | idx = R_RELBYTE; | |
4132022d AM |
1383 | operand->exp.X_add_number = |
1384 | ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
7ee7b84d | 1385 | operand->exp.X_add_number |= bytes[0]; |
252b5132 RH |
1386 | } |
1387 | ||
1388 | fix_new_exp (frag_now, | |
1389 | offset + where, | |
1390 | size, | |
1391 | &operand->exp, | |
1392 | 0, | |
1393 | idx); | |
1394 | } | |
252b5132 RH |
1395 | } |
1396 | ||
70d6ecf3 | 1397 | /* Now we know what sort of opcodes it is, let's build the bytes. */ |
3048287a | 1398 | |
252b5132 | 1399 | static void |
b54a3392 | 1400 | build_bytes (const struct h8_instruction *this_try, struct h8_op *operand) |
252b5132 | 1401 | { |
3048287a | 1402 | int i; |
252b5132 | 1403 | char *output = frag_more (this_try->length); |
d1e50f8a | 1404 | const op_type *nibble_ptr = this_try->opcode->data.nib; |
252b5132 RH |
1405 | op_type c; |
1406 | unsigned int nibble_count = 0; | |
7ee7b84d | 1407 | int op_at[3]; |
3048287a | 1408 | int nib = 0; |
252b5132 | 1409 | int movb = 0; |
7ee7b84d | 1410 | char asnibbles[100]; |
252b5132 | 1411 | char *p = asnibbles; |
7ee7b84d | 1412 | int high, low; |
252b5132 | 1413 | |
d4ea8842 | 1414 | if (!Hmode && this_try->opcode->available != AV_H8) |
252b5132 | 1415 | as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"), |
a720f7bc | 1416 | this_try->opcode->name); |
d4ea8842 MS |
1417 | else if (!Smode |
1418 | && this_try->opcode->available != AV_H8 | |
1419 | && this_try->opcode->available != AV_H8H) | |
1420 | as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"), | |
1421 | this_try->opcode->name); | |
1422 | else if (!SXmode | |
1423 | && this_try->opcode->available != AV_H8 | |
1424 | && this_try->opcode->available != AV_H8H | |
1425 | && this_try->opcode->available != AV_H8S) | |
1426 | as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"), | |
1427 | this_try->opcode->name); | |
252b5132 | 1428 | |
7ee7b84d | 1429 | while (*nibble_ptr != (op_type) E) |
252b5132 RH |
1430 | { |
1431 | int d; | |
7ee7b84d MS |
1432 | |
1433 | nib = 0; | |
252b5132 RH |
1434 | c = *nibble_ptr++; |
1435 | ||
7ee7b84d | 1436 | d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0; |
252b5132 RH |
1437 | |
1438 | if (c < 16) | |
3048287a | 1439 | nib = c; |
252b5132 RH |
1440 | else |
1441 | { | |
7ee7b84d MS |
1442 | int c2 = c & MODE; |
1443 | ||
1444 | if (c2 == REG || c2 == LOWREG | |
1445 | || c2 == IND || c2 == PREINC || c2 == PREDEC | |
1446 | || c2 == POSTINC || c2 == POSTDEC) | |
1447 | { | |
1448 | nib = operand[d].reg; | |
1449 | if (c2 == LOWREG) | |
1450 | nib &= 7; | |
1451 | } | |
1452 | ||
1453 | else if (c & CTRL) /* Control reg operand. */ | |
3048287a NC |
1454 | nib = operand[d].reg; |
1455 | ||
252b5132 | 1456 | else if ((c & DISPREG) == (DISPREG)) |
7ee7b84d MS |
1457 | { |
1458 | nib = operand[d].reg; | |
1459 | } | |
1460 | else if (c2 == ABS) | |
252b5132 RH |
1461 | { |
1462 | operand[d].mode = c; | |
7ee7b84d | 1463 | op_at[d] = nibble_count; |
252b5132 RH |
1464 | nib = 0; |
1465 | } | |
7ee7b84d MS |
1466 | else if (c2 == IMM || c2 == PCREL || c2 == ABS |
1467 | || (c & ABSJMP) || c2 == DISP) | |
252b5132 RH |
1468 | { |
1469 | operand[d].mode = c; | |
7ee7b84d | 1470 | op_at[d] = nibble_count; |
252b5132 RH |
1471 | nib = 0; |
1472 | } | |
7ee7b84d | 1473 | else if ((c & IGNORE) || (c & DATA)) |
3048287a NC |
1474 | nib = 0; |
1475 | ||
7ee7b84d | 1476 | else if (c2 == DBIT) |
252b5132 RH |
1477 | { |
1478 | switch (operand[0].exp.X_add_number) | |
1479 | { | |
1480 | case 1: | |
1481 | nib = c; | |
1482 | break; | |
1483 | case 2: | |
1484 | nib = 0x8 | c; | |
1485 | break; | |
1486 | default: | |
1487 | as_bad (_("Need #1 or #2 here")); | |
1488 | } | |
1489 | } | |
7ee7b84d | 1490 | else if (c2 == KBIT) |
252b5132 RH |
1491 | { |
1492 | switch (operand[0].exp.X_add_number) | |
1493 | { | |
1494 | case 1: | |
1495 | nib = 0; | |
1496 | break; | |
1497 | case 2: | |
1498 | nib = 8; | |
1499 | break; | |
1500 | case 4: | |
1501 | if (!Hmode) | |
1502 | as_warn (_("#4 not valid on H8/300.")); | |
1503 | nib = 9; | |
1504 | break; | |
1505 | ||
1506 | default: | |
1507 | as_bad (_("Need #1 or #2 here")); | |
1508 | break; | |
1509 | } | |
70d6ecf3 | 1510 | /* Stop it making a fix. */ |
252b5132 RH |
1511 | operand[0].mode = 0; |
1512 | } | |
1513 | ||
1514 | if (c & MEMRELAX) | |
3048287a | 1515 | operand[d].mode |= MEMRELAX; |
252b5132 RH |
1516 | |
1517 | if (c & B31) | |
3048287a | 1518 | nib |= 0x8; |
252b5132 | 1519 | |
7ee7b84d MS |
1520 | if (c & B21) |
1521 | nib |= 0x4; | |
1522 | ||
1523 | if (c & B11) | |
1524 | nib |= 0x2; | |
1525 | ||
1526 | if (c & B01) | |
1527 | nib |= 0x1; | |
1528 | ||
1529 | if (c2 == MACREG) | |
252b5132 | 1530 | { |
f0c56b90 NC |
1531 | if (operand[0].mode == MACREG) |
1532 | /* stmac has mac[hl] as the first operand. */ | |
1533 | nib = 2 + operand[0].reg; | |
1534 | else | |
1535 | /* ldmac has mac[hl] as the second operand. */ | |
1536 | nib = 2 + operand[1].reg; | |
252b5132 RH |
1537 | } |
1538 | } | |
1539 | nibble_count++; | |
1540 | ||
1541 | *p++ = nib; | |
1542 | } | |
1543 | ||
1544 | /* Disgusting. Why, oh why didn't someone ask us for advice | |
1545 | on the assembler format. */ | |
7ee7b84d | 1546 | if (OP_KIND (this_try->opcode->how) == O_LDM) |
252b5132 | 1547 | { |
7ee7b84d MS |
1548 | high = (operand[1].reg >> 8) & 0xf; |
1549 | low = (operand[1].reg) & 0xf; | |
252b5132 | 1550 | asnibbles[2] = high - low; |
7ee7b84d MS |
1551 | asnibbles[7] = high; |
1552 | } | |
1553 | else if (OP_KIND (this_try->opcode->how) == O_STM) | |
1554 | { | |
1555 | high = (operand[0].reg >> 8) & 0xf; | |
1556 | low = (operand[0].reg) & 0xf; | |
1557 | asnibbles[2] = high - low; | |
1558 | asnibbles[7] = low; | |
252b5132 RH |
1559 | } |
1560 | ||
1561 | for (i = 0; i < this_try->length; i++) | |
3048287a | 1562 | output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1]; |
252b5132 | 1563 | |
ca9a79a1 NC |
1564 | /* Note if this is a movb or a bit manipulation instruction |
1565 | there is a special relaxation which only applies. */ | |
1566 | if ( this_try->opcode->how == O (O_MOV, SB) | |
1567 | || this_try->opcode->how == O (O_BCLR, SB) | |
1568 | || this_try->opcode->how == O (O_BAND, SB) | |
1569 | || this_try->opcode->how == O (O_BIAND, SB) | |
1570 | || this_try->opcode->how == O (O_BILD, SB) | |
1571 | || this_try->opcode->how == O (O_BIOR, SB) | |
1572 | || this_try->opcode->how == O (O_BIST, SB) | |
1573 | || this_try->opcode->how == O (O_BIXOR, SB) | |
1574 | || this_try->opcode->how == O (O_BLD, SB) | |
1575 | || this_try->opcode->how == O (O_BNOT, SB) | |
1576 | || this_try->opcode->how == O (O_BOR, SB) | |
1577 | || this_try->opcode->how == O (O_BSET, SB) | |
1578 | || this_try->opcode->how == O (O_BST, SB) | |
1579 | || this_try->opcode->how == O (O_BTST, SB) | |
1580 | || this_try->opcode->how == O (O_BXOR, SB)) | |
252b5132 RH |
1581 | movb = 1; |
1582 | ||
70d6ecf3 | 1583 | /* Output any fixes. */ |
7ee7b84d | 1584 | for (i = 0; i < this_try->noperands; i++) |
252b5132 RH |
1585 | { |
1586 | int x = operand[i].mode; | |
7ee7b84d | 1587 | int x_mode = x & MODE; |
252b5132 | 1588 | |
7ee7b84d MS |
1589 | if (x_mode == IMM || x_mode == DISP) |
1590 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, | |
bcb012d3 DD |
1591 | op_at[i] & 1, operand + i, (x & MEMRELAX) != 0, |
1592 | this_try); | |
3048287a | 1593 | |
7ee7b84d MS |
1594 | else if (x_mode == ABS) |
1595 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, | |
1596 | op_at[i] & 1, operand + i, | |
bcb012d3 DD |
1597 | (x & MEMRELAX) ? movb + 1 : 0, |
1598 | this_try); | |
3048287a | 1599 | |
7ee7b84d | 1600 | else if (x_mode == PCREL) |
252b5132 | 1601 | { |
7ee7b84d | 1602 | int size16 = (x & SIZE) == L_16; |
252b5132 RH |
1603 | int size = size16 ? 2 : 1; |
1604 | int type = size16 ? R_PCRWORD : R_PCRBYTE; | |
36ed2fff | 1605 | fixS *fixP; |
252b5132 RH |
1606 | |
1607 | check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@"); | |
1608 | ||
1609 | if (operand[i].exp.X_add_number & 1) | |
3048287a NC |
1610 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1611 | (unsigned long) operand->exp.X_add_number); | |
36ed2fff JL |
1612 | #ifndef OBJ_ELF |
1613 | /* The COFF port has always been off by one, changing it | |
1614 | now would be an incompatible change, so we leave it as-is. | |
1615 | ||
1616 | We don't want to do this for ELF as we want to be | |
1617 | compatible with the proposed ELF format from Hitachi. */ | |
252b5132 | 1618 | operand[i].exp.X_add_number -= 1; |
36ed2fff | 1619 | #endif |
7ee7b84d MS |
1620 | if (size16) |
1621 | { | |
1622 | operand[i].exp.X_add_number = | |
1623 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
1624 | } | |
1625 | else | |
1626 | { | |
1627 | operand[i].exp.X_add_number = | |
1628 | ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
1629 | } | |
1630 | ||
1631 | /* For BRA/S. */ | |
1632 | if (! size16) | |
1633 | operand[i].exp.X_add_number |= output[op_at[i] / 2]; | |
252b5132 | 1634 | |
36ed2fff | 1635 | fixP = fix_new_exp (frag_now, |
7ee7b84d | 1636 | output - frag_now->fr_literal + op_at[i] / 2, |
36ed2fff JL |
1637 | size, |
1638 | &operand[i].exp, | |
1639 | 1, | |
1640 | type); | |
1641 | fixP->fx_signed = 1; | |
252b5132 | 1642 | } |
7ee7b84d | 1643 | else if (x_mode == MEMIND) |
252b5132 | 1644 | { |
252b5132 RH |
1645 | check_operand (operand + i, 0xff, "@@"); |
1646 | fix_new_exp (frag_now, | |
1647 | output - frag_now->fr_literal + 1, | |
1648 | 1, | |
1649 | &operand[i].exp, | |
1650 | 0, | |
1651 | R_MEM_INDIRECT); | |
1652 | } | |
7ee7b84d MS |
1653 | else if (x_mode == VECIND) |
1654 | { | |
1655 | check_operand (operand + i, 0x7f, "@@"); | |
1656 | /* FIXME: approximating the effect of "B31" here... | |
1657 | This is very hackish, and ought to be done a better way. */ | |
1658 | operand[i].exp.X_add_number |= 0x80; | |
1659 | fix_new_exp (frag_now, | |
1660 | output - frag_now->fr_literal + 1, | |
1661 | 1, | |
1662 | &operand[i].exp, | |
1663 | 0, | |
1664 | R_MEM_INDIRECT); | |
1665 | } | |
252b5132 RH |
1666 | else if (x & ABSJMP) |
1667 | { | |
3c1ba8a3 | 1668 | int where = 0; |
7ee7b84d | 1669 | bfd_reloc_code_real_type reloc_type = R_JMPL1; |
3c1ba8a3 JL |
1670 | |
1671 | #ifdef OBJ_ELF | |
1672 | /* To be compatible with the proposed H8 ELF format, we | |
1673 | want the relocation's offset to point to the first byte | |
1674 | that will be modified, not to the start of the instruction. */ | |
7ee7b84d MS |
1675 | |
1676 | if ((operand->mode & SIZE) == L_32) | |
1677 | { | |
1678 | where = 2; | |
1679 | reloc_type = R_RELLONG; | |
1680 | } | |
1681 | else | |
1682 | where = 1; | |
3c1ba8a3 | 1683 | #endif |
de342d07 | 1684 | |
70d6ecf3 | 1685 | /* This jmp may be a jump or a branch. */ |
252b5132 | 1686 | |
7ee7b84d MS |
1687 | check_operand (operand + i, |
1688 | SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff, | |
1689 | "@"); | |
3048287a | 1690 | |
252b5132 | 1691 | if (operand[i].exp.X_add_number & 1) |
3048287a NC |
1692 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1693 | (unsigned long) operand->exp.X_add_number); | |
1694 | ||
252b5132 | 1695 | if (!Hmode) |
70d6ecf3 | 1696 | operand[i].exp.X_add_number = |
4132022d | 1697 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; |
252b5132 | 1698 | fix_new_exp (frag_now, |
3c1ba8a3 | 1699 | output - frag_now->fr_literal + where, |
252b5132 RH |
1700 | 4, |
1701 | &operand[i].exp, | |
1702 | 0, | |
7ee7b84d | 1703 | reloc_type); |
252b5132 RH |
1704 | } |
1705 | } | |
252b5132 RH |
1706 | } |
1707 | ||
70d6ecf3 AM |
1708 | /* Try to give an intelligent error message for common and simple to |
1709 | detect errors. */ | |
3048287a | 1710 | |
252b5132 | 1711 | static void |
b54a3392 KH |
1712 | clever_message (const struct h8_instruction *instruction, |
1713 | struct h8_op *operand) | |
252b5132 | 1714 | { |
70d6ecf3 | 1715 | /* Find out if there was more than one possible opcode. */ |
252b5132 | 1716 | |
a720f7bc | 1717 | if ((instruction + 1)->idx != instruction->idx) |
252b5132 | 1718 | { |
3048287a | 1719 | int argn; |
252b5132 | 1720 | |
70d6ecf3 AM |
1721 | /* Only one opcode of this flavour, try to guess which operand |
1722 | didn't match. */ | |
a720f7bc | 1723 | for (argn = 0; argn < instruction->noperands; argn++) |
252b5132 | 1724 | { |
a720f7bc | 1725 | switch (instruction->opcode->args.nib[argn]) |
252b5132 RH |
1726 | { |
1727 | case RD16: | |
1728 | if (operand[argn].mode != RD16) | |
1729 | { | |
1730 | as_bad (_("destination operand must be 16 bit register")); | |
1731 | return; | |
1732 | ||
1733 | } | |
1734 | break; | |
1735 | ||
1736 | case RS8: | |
252b5132 RH |
1737 | if (operand[argn].mode != RS8) |
1738 | { | |
1739 | as_bad (_("source operand must be 8 bit register")); | |
1740 | return; | |
1741 | } | |
1742 | break; | |
1743 | ||
1744 | case ABS16DST: | |
1745 | if (operand[argn].mode != ABS16DST) | |
1746 | { | |
1747 | as_bad (_("destination operand must be 16bit absolute address")); | |
1748 | return; | |
1749 | } | |
1750 | break; | |
1751 | case RD8: | |
1752 | if (operand[argn].mode != RD8) | |
1753 | { | |
1754 | as_bad (_("destination operand must be 8 bit register")); | |
1755 | return; | |
1756 | } | |
1757 | break; | |
1758 | ||
252b5132 RH |
1759 | case ABS16SRC: |
1760 | if (operand[argn].mode != ABS16SRC) | |
1761 | { | |
1762 | as_bad (_("source operand must be 16bit absolute address")); | |
1763 | return; | |
1764 | } | |
1765 | break; | |
1766 | ||
1767 | } | |
1768 | } | |
1769 | } | |
1770 | as_bad (_("invalid operands")); | |
1771 | } | |
1772 | ||
d4ea8842 | 1773 | |
1b680e4f RS |
1774 | /* If OPERAND is part of an address, adjust its size and value given |
1775 | that it addresses SIZE bytes. | |
d4ea8842 | 1776 | |
1b680e4f RS |
1777 | This function decides how big non-immediate constants are when no |
1778 | size was explicitly given. It also scales down the assembly-level | |
d4ea8842 MS |
1779 | displacement in an @(d:2,ERn) operand. */ |
1780 | ||
1781 | static void | |
b54a3392 | 1782 | fix_operand_size (struct h8_op *operand, int size) |
d4ea8842 | 1783 | { |
1b680e4f | 1784 | if (SXmode && (operand->mode & MODE) == DISP) |
d4ea8842 MS |
1785 | { |
1786 | /* If the user didn't specify an operand width, see if we | |
1787 | can use @(d:2,ERn). */ | |
1b680e4f RS |
1788 | if ((operand->mode & SIZE) == 0 |
1789 | && operand->exp.X_add_symbol == 0 | |
1790 | && operand->exp.X_op_symbol == 0 | |
d4ea8842 MS |
1791 | && (operand->exp.X_add_number == size |
1792 | || operand->exp.X_add_number == size * 2 | |
1793 | || operand->exp.X_add_number == size * 3)) | |
1794 | operand->mode |= L_2; | |
1795 | ||
1796 | /* Scale down the displacement in an @(d:2,ERn) operand. | |
1797 | X_add_number then contains the desired field value. */ | |
1798 | if ((operand->mode & SIZE) == L_2) | |
1799 | { | |
1800 | if (operand->exp.X_add_number % size != 0) | |
1801 | as_warn (_("operand/size mis-match")); | |
1802 | operand->exp.X_add_number /= size; | |
1803 | } | |
1804 | } | |
1805 | ||
d4ea8842 MS |
1806 | if ((operand->mode & SIZE) == 0) |
1807 | switch (operand->mode & MODE) | |
1808 | { | |
1809 | case DISP: | |
1810 | case INDEXB: | |
1811 | case INDEXW: | |
1812 | case INDEXL: | |
1813 | case ABS: | |
1b680e4f RS |
1814 | /* Pick a 24-bit address unless we know that a 16-bit address |
1815 | is safe. get_specific() will relax L_24 into L_32 where | |
1816 | necessary. */ | |
1817 | if (Hmode | |
d4e2de6b | 1818 | && !Nmode |
1b680e4f RS |
1819 | && (operand->exp.X_add_number < -32768 |
1820 | || operand->exp.X_add_number > 32767 | |
1821 | || operand->exp.X_add_symbol != 0 | |
1822 | || operand->exp.X_op_symbol != 0)) | |
1823 | operand->mode |= L_24; | |
1824 | else | |
1825 | operand->mode |= L_16; | |
1826 | break; | |
1827 | ||
1828 | case PCREL: | |
1829 | /* This condition is long standing, though somewhat suspect. */ | |
1830 | if (operand->exp.X_add_number > -128 | |
1831 | && operand->exp.X_add_number < 127) | |
cc189afc DD |
1832 | { |
1833 | if (operand->exp.X_add_symbol != NULL) | |
1834 | operand->mode |= bsize; | |
1835 | else | |
1836 | operand->mode |= L_8; | |
1837 | } | |
1b680e4f RS |
1838 | else |
1839 | operand->mode |= L_16; | |
d4ea8842 MS |
1840 | break; |
1841 | } | |
1842 | } | |
1843 | ||
1844 | ||
70d6ecf3 AM |
1845 | /* This is the guts of the machine-dependent assembler. STR points to |
1846 | a machine dependent instruction. This function is supposed to emit | |
1847 | the frags/bytes it assembles. */ | |
3048287a | 1848 | |
252b5132 | 1849 | void |
b54a3392 | 1850 | md_assemble (char *str) |
252b5132 RH |
1851 | { |
1852 | char *op_start; | |
1853 | char *op_end; | |
7ee7b84d | 1854 | struct h8_op operand[3]; |
a720f7bc KD |
1855 | const struct h8_instruction *instruction; |
1856 | const struct h8_instruction *prev_instruction; | |
252b5132 RH |
1857 | |
1858 | char *dot = 0; | |
0c0b9be0 | 1859 | char *slash = 0; |
252b5132 | 1860 | char c; |
7ee7b84d | 1861 | int size, i; |
252b5132 | 1862 | |
70d6ecf3 | 1863 | /* Drop leading whitespace. */ |
252b5132 RH |
1864 | while (*str == ' ') |
1865 | str++; | |
1866 | ||
70d6ecf3 | 1867 | /* Find the op code end. */ |
252b5132 RH |
1868 | for (op_start = op_end = str; |
1869 | *op_end != 0 && *op_end != ' '; | |
1870 | op_end++) | |
1871 | { | |
1872 | if (*op_end == '.') | |
1873 | { | |
1874 | dot = op_end + 1; | |
1875 | *op_end = 0; | |
1876 | op_end += 2; | |
1877 | break; | |
1878 | } | |
0c0b9be0 AO |
1879 | else if (*op_end == '/' && ! slash) |
1880 | slash = op_end; | |
252b5132 RH |
1881 | } |
1882 | ||
252b5132 RH |
1883 | if (op_end == op_start) |
1884 | { | |
1885 | as_bad (_("can't find opcode ")); | |
1886 | } | |
1887 | c = *op_end; | |
1888 | ||
1889 | *op_end = 0; | |
1890 | ||
0c0b9be0 AO |
1891 | /* The assembler stops scanning the opcode at slashes, so it fails |
1892 | to make characters following them lower case. Fix them. */ | |
1893 | if (slash) | |
1894 | while (*++slash) | |
1895 | *slash = TOLOWER (*slash); | |
1896 | ||
a720f7bc KD |
1897 | instruction = (const struct h8_instruction *) |
1898 | hash_find (opcode_hash_control, op_start); | |
252b5132 | 1899 | |
a720f7bc | 1900 | if (instruction == NULL) |
252b5132 RH |
1901 | { |
1902 | as_bad (_("unknown opcode")); | |
1903 | return; | |
1904 | } | |
1905 | ||
70d6ecf3 | 1906 | /* We used to set input_line_pointer to the result of get_operands, |
252b5132 RH |
1907 | but that is wrong. Our caller assumes we don't change it. */ |
1908 | ||
7ee7b84d MS |
1909 | operand[0].mode = 0; |
1910 | operand[1].mode = 0; | |
1911 | operand[2].mode = 0; | |
1912 | ||
1913 | if (OP_KIND (instruction->opcode->how) == O_MOVAB | |
1914 | || OP_KIND (instruction->opcode->how) == O_MOVAW | |
1915 | || OP_KIND (instruction->opcode->how) == O_MOVAL) | |
1916 | get_mova_operands (op_end, operand); | |
1917 | else if (OP_KIND (instruction->opcode->how) == O_RTEL | |
1918 | || OP_KIND (instruction->opcode->how) == O_RTSL) | |
1919 | get_rtsl_operands (op_end, operand); | |
1920 | else | |
1921 | get_operands (instruction->noperands, op_end, operand); | |
1922 | ||
252b5132 | 1923 | *op_end = c; |
a720f7bc | 1924 | prev_instruction = instruction; |
252b5132 | 1925 | |
4892e510 NC |
1926 | /* Now we have operands from instruction. |
1927 | Let's check them out for ldm and stm. */ | |
1928 | if (OP_KIND (instruction->opcode->how) == O_LDM) | |
1929 | { | |
1930 | /* The first operand must be @er7+, and the | |
1931 | second operand must be a register pair. */ | |
1932 | if ((operand[0].mode != RSINC) | |
1933 | || (operand[0].reg != 7) | |
1934 | || ((operand[1].reg & 0x80000000) == 0)) | |
1935 | as_bad (_("invalid operand in ldm")); | |
1936 | } | |
1937 | else if (OP_KIND (instruction->opcode->how) == O_STM) | |
1938 | { | |
1939 | /* The first operand must be a register pair, | |
1940 | and the second operand must be @-er7. */ | |
1941 | if (((operand[0].reg & 0x80000000) == 0) | |
1942 | || (operand[1].mode != RDDEC) | |
1943 | || (operand[1].reg != 7)) | |
1944 | as_bad (_("invalid operand in stm")); | |
1945 | } | |
1946 | ||
252b5132 RH |
1947 | size = SN; |
1948 | if (dot) | |
1949 | { | |
0c0b9be0 | 1950 | switch (TOLOWER (*dot)) |
252b5132 RH |
1951 | { |
1952 | case 'b': | |
1953 | size = SB; | |
1954 | break; | |
1955 | ||
1956 | case 'w': | |
1957 | size = SW; | |
1958 | break; | |
1959 | ||
1960 | case 'l': | |
1961 | size = SL; | |
1962 | break; | |
1963 | } | |
1964 | } | |
7ee7b84d MS |
1965 | if (OP_KIND (instruction->opcode->how) == O_MOVAB || |
1966 | OP_KIND (instruction->opcode->how) == O_MOVAW || | |
1967 | OP_KIND (instruction->opcode->how) == O_MOVAL) | |
252b5132 | 1968 | { |
d4ea8842 MS |
1969 | switch (operand[0].mode & MODE) |
1970 | { | |
7ee7b84d MS |
1971 | case INDEXB: |
1972 | default: | |
d4ea8842 | 1973 | fix_operand_size (&operand[1], 1); |
7ee7b84d MS |
1974 | break; |
1975 | case INDEXW: | |
d4ea8842 | 1976 | fix_operand_size (&operand[1], 2); |
7ee7b84d MS |
1977 | break; |
1978 | case INDEXL: | |
d4ea8842 | 1979 | fix_operand_size (&operand[1], 4); |
7ee7b84d | 1980 | break; |
252b5132 RH |
1981 | } |
1982 | } | |
7ee7b84d MS |
1983 | else |
1984 | { | |
d4ea8842 MS |
1985 | for (i = 0; i < 3 && operand[i].mode != 0; i++) |
1986 | switch (size) | |
1987 | { | |
7ee7b84d MS |
1988 | case SN: |
1989 | case SB: | |
1990 | default: | |
d4ea8842 | 1991 | fix_operand_size (&operand[i], 1); |
7ee7b84d MS |
1992 | break; |
1993 | case SW: | |
d4ea8842 | 1994 | fix_operand_size (&operand[i], 2); |
7ee7b84d MS |
1995 | break; |
1996 | case SL: | |
d4ea8842 | 1997 | fix_operand_size (&operand[i], 4); |
7ee7b84d MS |
1998 | break; |
1999 | } | |
2000 | } | |
252b5132 | 2001 | |
d4ea8842 MS |
2002 | instruction = get_specific (instruction, operand, size); |
2003 | ||
2004 | if (instruction == 0) | |
2005 | { | |
2006 | /* Couldn't find an opcode which matched the operands. */ | |
2007 | char *where = frag_more (2); | |
2008 | ||
2009 | where[0] = 0x0; | |
2010 | where[1] = 0x0; | |
2011 | clever_message (prev_instruction, operand); | |
2012 | ||
2013 | return; | |
2014 | } | |
2015 | ||
a720f7bc | 2016 | build_bytes (instruction, operand); |
2c8714f2 | 2017 | |
2c8714f2 | 2018 | dwarf2_emit_insn (instruction->length); |
252b5132 RH |
2019 | } |
2020 | ||
2021 | symbolS * | |
b54a3392 | 2022 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
2023 | { |
2024 | return 0; | |
2025 | } | |
2026 | ||
499ac353 | 2027 | /* Various routines to kill one day. */ |
bc0d738a | 2028 | |
252b5132 | 2029 | char * |
b54a3392 | 2030 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 2031 | { |
499ac353 | 2032 | return ieee_md_atof (type, litP, sizeP, TRUE); |
252b5132 RH |
2033 | } |
2034 | \f | |
6fd4f6cc DD |
2035 | #define OPTION_H_TICK_HEX (OPTION_MD_BASE) |
2036 | ||
5a38dc70 | 2037 | const char *md_shortopts = ""; |
252b5132 | 2038 | struct option md_longopts[] = { |
6fd4f6cc | 2039 | { "h-tick-hex", no_argument, NULL, OPTION_H_TICK_HEX }, |
252b5132 RH |
2040 | {NULL, no_argument, NULL, 0} |
2041 | }; | |
70d6ecf3 AM |
2042 | |
2043 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
2044 | |
2045 | int | |
b54a3392 | 2046 | md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED) |
252b5132 | 2047 | { |
6fd4f6cc DD |
2048 | switch (c) |
2049 | { | |
2050 | case OPTION_H_TICK_HEX: | |
2051 | enable_h_tick_hex = 1; | |
2052 | break; | |
2053 | ||
2054 | default: | |
2055 | return 0; | |
2056 | } | |
2057 | return 1; | |
252b5132 RH |
2058 | } |
2059 | ||
2060 | void | |
b54a3392 | 2061 | md_show_usage (FILE *stream ATTRIBUTE_UNUSED) |
252b5132 RH |
2062 | { |
2063 | } | |
2064 | \f | |
b54a3392 | 2065 | void tc_aout_fix_to_chars (void); |
3048287a | 2066 | |
252b5132 | 2067 | void |
b54a3392 | 2068 | tc_aout_fix_to_chars (void) |
252b5132 RH |
2069 | { |
2070 | printf (_("call to tc_aout_fix_to_chars \n")); | |
2071 | abort (); | |
2072 | } | |
2073 | ||
2074 | void | |
7be1c489 | 2075 | md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, |
b54a3392 KH |
2076 | segT seg ATTRIBUTE_UNUSED, |
2077 | fragS *fragP ATTRIBUTE_UNUSED) | |
252b5132 RH |
2078 | { |
2079 | printf (_("call to md_convert_frag \n")); | |
2080 | abort (); | |
2081 | } | |
2082 | ||
3c1ba8a3 | 2083 | valueT |
b54a3392 | 2084 | md_section_align (segT segment, valueT size) |
3c1ba8a3 JL |
2085 | { |
2086 | int align = bfd_get_section_alignment (stdoutput, segment); | |
2087 | return ((size + (1 << align) - 1) & (-1 << align)); | |
2088 | } | |
252b5132 RH |
2089 | |
2090 | void | |
55cf6793 | 2091 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 RH |
2092 | { |
2093 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
a161fe53 | 2094 | long val = *valP; |
252b5132 RH |
2095 | |
2096 | switch (fixP->fx_size) | |
2097 | { | |
2098 | case 1: | |
2099 | *buf++ = val; | |
2100 | break; | |
2101 | case 2: | |
2102 | *buf++ = (val >> 8); | |
2103 | *buf++ = val; | |
2104 | break; | |
2105 | case 4: | |
2106 | *buf++ = (val >> 24); | |
2107 | *buf++ = (val >> 16); | |
2108 | *buf++ = (val >> 8); | |
2109 | *buf++ = val; | |
2110 | break; | |
550c1888 NC |
2111 | case 8: |
2112 | /* This can arise when the .quad or .8byte pseudo-ops are used. | |
2113 | Returning here (without setting fx_done) will cause the code | |
2114 | to attempt to generate a reloc which will then fail with the | |
2115 | slightly more helpful error message: "Cannot represent | |
2116 | relocation type BFD_RELOC_64". */ | |
2117 | return; | |
252b5132 RH |
2118 | default: |
2119 | abort (); | |
2120 | } | |
94f592af NC |
2121 | |
2122 | if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) | |
2123 | fixP->fx_done = 1; | |
252b5132 RH |
2124 | } |
2125 | ||
2126 | int | |
c85dd50d NC |
2127 | md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, |
2128 | segT segment_type ATTRIBUTE_UNUSED) | |
252b5132 | 2129 | { |
c85dd50d | 2130 | printf (_("call to md_estimate_size_before_relax \n")); |
252b5132 RH |
2131 | abort (); |
2132 | } | |
2133 | ||
70d6ecf3 | 2134 | /* Put number into target byte order. */ |
252b5132 | 2135 | void |
b54a3392 | 2136 | md_number_to_chars (char *ptr, valueT use, int nbytes) |
252b5132 RH |
2137 | { |
2138 | number_to_chars_bigendian (ptr, use, nbytes); | |
2139 | } | |
70d6ecf3 | 2140 | |
252b5132 | 2141 | long |
b54a3392 | 2142 | md_pcrel_from (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 RH |
2143 | { |
2144 | abort (); | |
2145 | } | |
2146 | ||
f333765f | 2147 | arelent * |
b54a3392 | 2148 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
f333765f JL |
2149 | { |
2150 | arelent *rel; | |
2151 | bfd_reloc_code_real_type r_type; | |
2152 | ||
de342d07 JL |
2153 | if (fixp->fx_addsy && fixp->fx_subsy) |
2154 | { | |
2155 | if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy)) | |
2156 | || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section) | |
2157 | { | |
2158 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
c85dd50d | 2159 | _("Difference of symbols in different sections is not supported")); |
de342d07 JL |
2160 | return NULL; |
2161 | } | |
2162 | } | |
2163 | ||
c85dd50d NC |
2164 | rel = xmalloc (sizeof (arelent)); |
2165 | rel->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); | |
f333765f JL |
2166 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
2167 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
2168 | rel->addend = fixp->fx_offset; | |
2169 | ||
2170 | r_type = fixp->fx_r_type; | |
2171 | ||
2172 | #define DEBUG 0 | |
2173 | #if DEBUG | |
2174 | fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type)); | |
c85dd50d | 2175 | fflush (stderr); |
f333765f JL |
2176 | #endif |
2177 | rel->howto = bfd_reloc_type_lookup (stdoutput, r_type); | |
2178 | if (rel->howto == NULL) | |
2179 | { | |
2180 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
2181 | _("Cannot represent relocation type %s"), | |
2182 | bfd_get_reloc_code_name (r_type)); | |
2183 | return NULL; | |
2184 | } | |
2185 | ||
2186 | return rel; | |
2187 | } |