Commit | Line | Data |
---|---|---|
c2dcd04e | 1 | /* tc-h8300.c -- Assemble code for the Renesas H8/300 |
2571583a | 2 | Copyright (C) 1991-2017 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
bc0d738a | 21 | /* Written By Steve Chamberlain <sac@cygnus.com>. */ |
252b5132 | 22 | |
252b5132 RH |
23 | #include "as.h" |
24 | #include "subsegs.h" | |
2c8714f2 | 25 | #include "dwarf2dbg.h" |
2c8714f2 | 26 | |
252b5132 RH |
27 | #define DEFINE_TABLE |
28 | #define h8_opcodes ops | |
29 | #include "opcode/h8300.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
7e0de7bf JL |
32 | #ifdef OBJ_ELF |
33 | #include "elf/h8.h" | |
7e0de7bf JL |
34 | #endif |
35 | ||
63a0b638 | 36 | const char comment_chars[] = ";"; |
252b5132 | 37 | const char line_comment_chars[] = "#"; |
5518c738 YS |
38 | #ifdef TE_LINUX |
39 | const char line_separator_chars[] = "!"; | |
40 | #else | |
63a0b638 | 41 | const char line_separator_chars[] = ""; |
5518c738 | 42 | #endif |
252b5132 | 43 | |
600e9c99 KH |
44 | static void sbranch (int); |
45 | static void h8300hmode (int); | |
46 | static void h8300smode (int); | |
47 | static void h8300hnmode (int); | |
48 | static void h8300snmode (int); | |
49 | static void h8300sxmode (int); | |
50 | static void h8300sxnmode (int); | |
b54a3392 | 51 | static void pint (int); |
252b5132 | 52 | |
66faad26 KH |
53 | int Hmode; |
54 | int Smode; | |
55 | int Nmode; | |
56 | int SXmode; | |
3048287a | 57 | |
5518c738 YS |
58 | static int default_mach = bfd_mach_h8300; |
59 | ||
d4e2de6b | 60 | #define PSIZE (Hmode && !Nmode ? L_32 : L_16) |
3048287a | 61 | |
600e9c99 | 62 | static int bsize = L_8; /* Default branch displacement. */ |
252b5132 | 63 | |
a720f7bc KD |
64 | struct h8_instruction |
65 | { | |
66 | int length; | |
67 | int noperands; | |
68 | int idx; | |
69 | int size; | |
70 | const struct h8_opcode *opcode; | |
71 | }; | |
72 | ||
600e9c99 | 73 | static struct h8_instruction *h8_instructions; |
a720f7bc | 74 | |
600e9c99 | 75 | static void |
b54a3392 | 76 | h8300hmode (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
77 | { |
78 | Hmode = 1; | |
79 | Smode = 0; | |
83e20b45 JL |
80 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h)) |
81 | as_warn (_("could not set architecture and machine")); | |
252b5132 RH |
82 | } |
83 | ||
600e9c99 | 84 | static void |
b54a3392 | 85 | h8300smode (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
86 | { |
87 | Smode = 1; | |
88 | Hmode = 1; | |
83e20b45 JL |
89 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s)) |
90 | as_warn (_("could not set architecture and machine")); | |
252b5132 | 91 | } |
70d6ecf3 | 92 | |
600e9c99 | 93 | static void |
b54a3392 | 94 | h8300hnmode (int arg ATTRIBUTE_UNUSED) |
8d9cd6b1 NC |
95 | { |
96 | Hmode = 1; | |
97 | Smode = 0; | |
98 | Nmode = 1; | |
8d9cd6b1 NC |
99 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn)) |
100 | as_warn (_("could not set architecture and machine")); | |
8d9cd6b1 NC |
101 | } |
102 | ||
600e9c99 | 103 | static void |
b54a3392 | 104 | h8300snmode (int arg ATTRIBUTE_UNUSED) |
8d9cd6b1 NC |
105 | { |
106 | Smode = 1; | |
107 | Hmode = 1; | |
108 | Nmode = 1; | |
8d9cd6b1 NC |
109 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn)) |
110 | as_warn (_("could not set architecture and machine")); | |
8d9cd6b1 NC |
111 | } |
112 | ||
600e9c99 | 113 | static void |
b54a3392 | 114 | h8300sxmode (int arg ATTRIBUTE_UNUSED) |
7ee7b84d MS |
115 | { |
116 | Smode = 1; | |
117 | Hmode = 1; | |
118 | SXmode = 1; | |
7ee7b84d MS |
119 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx)) |
120 | as_warn (_("could not set architecture and machine")); | |
7ee7b84d MS |
121 | } |
122 | ||
600e9c99 | 123 | static void |
b54a3392 | 124 | h8300sxnmode (int arg ATTRIBUTE_UNUSED) |
f4984206 RS |
125 | { |
126 | Smode = 1; | |
127 | Hmode = 1; | |
128 | SXmode = 1; | |
129 | Nmode = 1; | |
f4984206 RS |
130 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn)) |
131 | as_warn (_("could not set architecture and machine")); | |
f4984206 RS |
132 | } |
133 | ||
600e9c99 | 134 | static void |
b54a3392 | 135 | sbranch (int size) |
252b5132 RH |
136 | { |
137 | bsize = size; | |
138 | } | |
139 | ||
70d6ecf3 | 140 | static void |
b54a3392 | 141 | pint (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
142 | { |
143 | cons (Hmode ? 4 : 2); | |
144 | } | |
145 | ||
52b010e4 NC |
146 | /* Like obj_elf_section, but issues a warning for new |
147 | sections which do not have an attribute specification. */ | |
148 | ||
149 | static void | |
150 | h8300_elf_section (int push) | |
151 | { | |
152 | static const char * known_data_sections [] = { ".rodata", ".tdata", ".tbss" }; | |
9c8b3bfe | 153 | static const char * known_data_prefixes [] = { ".debug", ".zdebug", ".gnu.warning" }; |
52b010e4 | 154 | char * saved_ilp = input_line_pointer; |
b9bb4a93 | 155 | const char * name; |
52b010e4 NC |
156 | |
157 | name = obj_elf_section_name (); | |
158 | if (name == NULL) | |
159 | return; | |
160 | ||
161 | if (* input_line_pointer != ',' | |
162 | && bfd_get_section_by_name (stdoutput, name) == NULL) | |
163 | { | |
164 | signed int i; | |
165 | ||
166 | /* Ignore this warning for well known data sections. */ | |
167 | for (i = ARRAY_SIZE (known_data_sections); i--;) | |
168 | if (strcmp (name, known_data_sections[i]) == 0) | |
169 | break; | |
170 | ||
171 | if (i < 0) | |
172 | for (i = ARRAY_SIZE (known_data_prefixes); i--;) | |
173 | if (strncmp (name, known_data_prefixes[i], | |
174 | strlen (known_data_prefixes[i])) == 0) | |
175 | break; | |
176 | ||
177 | if (i < 0) | |
178 | as_warn (_("new section '%s' defined without attributes - this might cause problems"), name); | |
179 | } | |
180 | ||
181 | /* FIXME: We ought to free the memory allocated by obj_elf_section_name() | |
182 | for 'name', but we do not know if it was taken from the obstack, via | |
183 | demand_copy_C_string(), or xmalloc()ed. */ | |
184 | input_line_pointer = saved_ilp; | |
185 | obj_elf_section (push); | |
186 | } | |
187 | ||
3048287a NC |
188 | /* This table describes all the machine specific pseudo-ops the assembler |
189 | has to support. The fields are: | |
190 | pseudo-op name without dot | |
191 | function to call to execute this pseudo-op | |
192 | Integer arg to pass to the function. */ | |
193 | ||
252b5132 RH |
194 | const pseudo_typeS md_pseudo_table[] = |
195 | { | |
7ee7b84d | 196 | {"h8300h", h8300hmode, 0}, |
8d9cd6b1 | 197 | {"h8300hn", h8300hnmode, 0}, |
7ee7b84d | 198 | {"h8300s", h8300smode, 0}, |
8d9cd6b1 | 199 | {"h8300sn", h8300snmode, 0}, |
7ee7b84d | 200 | {"h8300sx", h8300sxmode, 0}, |
f4984206 | 201 | {"h8300sxn", h8300sxnmode, 0}, |
252b5132 RH |
202 | {"sbranch", sbranch, L_8}, |
203 | {"lbranch", sbranch, L_16}, | |
204 | ||
205 | {"int", pint, 0}, | |
206 | {"data.b", cons, 1}, | |
207 | {"data.w", cons, 2}, | |
208 | {"data.l", cons, 4}, | |
209 | {"form", listing_psize, 0}, | |
210 | {"heading", listing_title, 0}, | |
7ee7b84d MS |
211 | {"import", s_ignore, 0}, |
212 | {"page", listing_eject, 0}, | |
252b5132 | 213 | {"program", s_ignore, 0}, |
52b010e4 NC |
214 | |
215 | #ifdef OBJ_ELF | |
216 | {"section", h8300_elf_section, 0}, | |
217 | {"section.s", h8300_elf_section, 0}, | |
218 | {"sect", h8300_elf_section, 0}, | |
219 | {"sect.s", h8300_elf_section, 0}, | |
220 | #endif | |
221 | ||
252b5132 RH |
222 | {0, 0, 0} |
223 | }; | |
224 | ||
252b5132 RH |
225 | const char EXP_CHARS[] = "eE"; |
226 | ||
3048287a NC |
227 | /* Chars that mean this number is a floating point constant |
228 | As in 0f12.456 | |
229 | or 0d1.2345e12. */ | |
252b5132 RH |
230 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
231 | ||
3048287a | 232 | static struct hash_control *opcode_hash_control; /* Opcode mnemonics. */ |
252b5132 | 233 | |
70d6ecf3 AM |
234 | /* This function is called once, at assembler startup time. This |
235 | should set up all the tables, etc. that the MD part of the assembler | |
236 | needs. */ | |
3048287a | 237 | |
252b5132 | 238 | void |
b54a3392 | 239 | md_begin (void) |
252b5132 | 240 | { |
a720f7bc | 241 | unsigned int nopcodes; |
7ee7b84d | 242 | struct h8_opcode *p, *p1; |
a720f7bc | 243 | struct h8_instruction *pi; |
252b5132 RH |
244 | char prev_buffer[100]; |
245 | int idx = 0; | |
246 | ||
5518c738 | 247 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, default_mach)) |
83e20b45 | 248 | as_warn (_("could not set architecture and machine")); |
83e20b45 | 249 | |
252b5132 RH |
250 | opcode_hash_control = hash_new (); |
251 | prev_buffer[0] = 0; | |
252 | ||
a720f7bc | 253 | nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); |
3739860c | 254 | |
add39d23 | 255 | h8_instructions = XNEWVEC (struct h8_instruction, nopcodes); |
a720f7bc | 256 | |
7ee7b84d MS |
257 | pi = h8_instructions; |
258 | p1 = h8_opcodes; | |
259 | /* We do a minimum amount of sorting on the opcode table; this is to | |
260 | make it easy to describe the mova instructions without unnecessary | |
261 | code duplication. | |
262 | Sorting only takes place inside blocks of instructions of the form | |
263 | X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */ | |
264 | while (p1) | |
252b5132 | 265 | { |
7ee7b84d MS |
266 | struct h8_opcode *first_skipped = 0; |
267 | int len, cmplen = 0; | |
f86f5863 | 268 | const char *src = p1->name; |
7ee7b84d | 269 | char *dst, *buffer; |
252b5132 | 270 | |
7ee7b84d MS |
271 | if (p1->name == 0) |
272 | break; | |
273 | /* Strip off any . part when inserting the opcode and only enter | |
274 | unique codes into the hash table. */ | |
add39d23 | 275 | dst = buffer = XNEWVEC (char, strlen (src) + 1); |
252b5132 RH |
276 | while (*src) |
277 | { | |
278 | if (*src == '.') | |
279 | { | |
280 | src++; | |
252b5132 RH |
281 | break; |
282 | } | |
7ee7b84d MS |
283 | if (*src == '/') |
284 | cmplen = src - p1->name + 1; | |
252b5132 RH |
285 | *dst++ = *src++; |
286 | } | |
7ee7b84d MS |
287 | *dst = 0; |
288 | len = dst - buffer; | |
289 | if (cmplen == 0) | |
290 | cmplen = len; | |
291 | hash_insert (opcode_hash_control, buffer, (char *) pi); | |
292 | strcpy (prev_buffer, buffer); | |
293 | idx++; | |
294 | ||
295 | for (p = p1; p->name; p++) | |
252b5132 | 296 | { |
7ee7b84d MS |
297 | /* A negative TIME is used to indicate that we've added this opcode |
298 | already. */ | |
299 | if (p->time == -1) | |
300 | continue; | |
301 | if (strncmp (p->name, buffer, cmplen) != 0 | |
302 | || (p->name[cmplen] != '\0' && p->name[cmplen] != '.' | |
303 | && p->name[cmplen - 1] != '/')) | |
304 | { | |
305 | if (first_skipped == 0) | |
306 | first_skipped = p; | |
307 | break; | |
308 | } | |
309 | if (strncmp (p->name, buffer, len) != 0) | |
310 | { | |
311 | if (first_skipped == 0) | |
312 | first_skipped = p; | |
313 | continue; | |
314 | } | |
315 | ||
316 | p->time = -1; | |
317 | pi->size = p->name[len] == '.' ? p->name[len + 1] : 0; | |
318 | pi->idx = idx; | |
252b5132 | 319 | |
7ee7b84d MS |
320 | /* Find the number of operands. */ |
321 | pi->noperands = 0; | |
322 | while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E) | |
323 | pi->noperands++; | |
70d6ecf3 | 324 | |
7ee7b84d MS |
325 | /* Find the length of the opcode in bytes. */ |
326 | pi->length = 0; | |
327 | while (p->data.nib[pi->length * 2] != (op_type) E) | |
328 | pi->length++; | |
a720f7bc | 329 | |
7ee7b84d MS |
330 | pi->opcode = p; |
331 | pi++; | |
332 | } | |
333 | p1 = first_skipped; | |
252b5132 RH |
334 | } |
335 | ||
a720f7bc KD |
336 | /* Add entry for the NULL vector terminator. */ |
337 | pi->length = 0; | |
338 | pi->noperands = 0; | |
339 | pi->idx = 0; | |
340 | pi->size = 0; | |
7ee7b84d | 341 | pi->opcode = 0; |
a720f7bc | 342 | |
252b5132 RH |
343 | linkrelax = 1; |
344 | } | |
345 | ||
252b5132 RH |
346 | struct h8_op |
347 | { | |
348 | op_type mode; | |
349 | unsigned reg; | |
350 | expressionS exp; | |
351 | }; | |
352 | ||
b54a3392 KH |
353 | static void clever_message (const struct h8_instruction *, struct h8_op *); |
354 | static void fix_operand_size (struct h8_op *, int); | |
355 | static void build_bytes (const struct h8_instruction *, struct h8_op *); | |
bcb012d3 | 356 | static void do_a_fix_imm (int, int, struct h8_op *, int, const struct h8_instruction *); |
e0471c16 | 357 | static void check_operand (struct h8_op *, unsigned int, const char *); |
b54a3392 KH |
358 | static const struct h8_instruction * get_specific (const struct h8_instruction *, struct h8_op *, int) ; |
359 | static char *get_operands (unsigned, char *, struct h8_op *); | |
360 | static void get_operand (char **, struct h8_op *, int); | |
361 | static int parse_reg (char *, op_type *, unsigned *, int); | |
362 | static char *skip_colonthing (char *, int *); | |
363 | static char *parse_exp (char *, struct h8_op *); | |
364 | ||
b54a3392 | 365 | static int constant_fits_size_p (struct h8_op *, int, int); |
7ee7b84d | 366 | |
252b5132 RH |
367 | /* |
368 | parse operands | |
369 | WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp | |
370 | r0l,r0h,..r7l,r7h | |
371 | @WREG | |
372 | @WREG+ | |
373 | @-WREG | |
374 | #const | |
375 | ccr | |
376 | */ | |
377 | ||
bc0d738a NC |
378 | /* Try to parse a reg name. Return the number of chars consumed. */ |
379 | ||
40f09f82 | 380 | static int |
b54a3392 | 381 | parse_reg (char *src, op_type *mode, unsigned int *reg, int direction) |
252b5132 RH |
382 | { |
383 | char *end; | |
384 | int len; | |
385 | ||
d02603dc | 386 | /* Cribbed from get_symbol_name. */ |
252b5132 RH |
387 | if (!is_name_beginner (*src) || *src == '\001') |
388 | return 0; | |
70d6ecf3 | 389 | end = src + 1; |
7ee7b84d | 390 | while ((is_part_of_name (*end) && *end != '.') || *end == '\001') |
252b5132 RH |
391 | end++; |
392 | len = end - src; | |
393 | ||
7ee7b84d | 394 | if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
395 | { |
396 | *mode = PSIZE | REG | direction; | |
397 | *reg = 7; | |
398 | return len; | |
399 | } | |
3739860c L |
400 | if (len == 3 && |
401 | TOLOWER (src[0]) == 'c' && | |
402 | TOLOWER (src[1]) == 'c' && | |
7ee7b84d | 403 | TOLOWER (src[2]) == 'r') |
252b5132 RH |
404 | { |
405 | *mode = CCR; | |
406 | *reg = 0; | |
407 | return len; | |
408 | } | |
3739860c L |
409 | if (len == 3 && |
410 | TOLOWER (src[0]) == 'e' && | |
411 | TOLOWER (src[1]) == 'x' && | |
7ee7b84d | 412 | TOLOWER (src[2]) == 'r') |
252b5132 RH |
413 | { |
414 | *mode = EXR; | |
7ee7b84d MS |
415 | *reg = 1; |
416 | return len; | |
417 | } | |
3739860c L |
418 | if (len == 3 && |
419 | TOLOWER (src[0]) == 'v' && | |
420 | TOLOWER (src[1]) == 'b' && | |
7ee7b84d MS |
421 | TOLOWER (src[2]) == 'r') |
422 | { | |
423 | *mode = VBR; | |
424 | *reg = 6; | |
425 | return len; | |
426 | } | |
3739860c L |
427 | if (len == 3 && |
428 | TOLOWER (src[0]) == 's' && | |
429 | TOLOWER (src[1]) == 'b' && | |
7ee7b84d MS |
430 | TOLOWER (src[2]) == 'r') |
431 | { | |
432 | *mode = SBR; | |
433 | *reg = 7; | |
252b5132 RH |
434 | return len; |
435 | } | |
7ee7b84d | 436 | if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
437 | { |
438 | *mode = PSIZE | REG | direction; | |
439 | *reg = 6; | |
440 | return len; | |
441 | } | |
7ee7b84d MS |
442 | if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
443 | src[2] >= '0' && src[2] <= '7') | |
252b5132 RH |
444 | { |
445 | *mode = L_32 | REG | direction; | |
446 | *reg = src[2] - '0'; | |
447 | if (!Hmode) | |
448 | as_warn (_("Reg not valid for H8/300")); | |
449 | return len; | |
450 | } | |
7ee7b84d | 451 | if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7') |
252b5132 RH |
452 | { |
453 | *mode = L_16 | REG | direction; | |
454 | *reg = src[1] - '0' + 8; | |
455 | if (!Hmode) | |
456 | as_warn (_("Reg not valid for H8/300")); | |
457 | return len; | |
458 | } | |
459 | ||
7ee7b84d | 460 | if (TOLOWER (src[0]) == 'r') |
252b5132 RH |
461 | { |
462 | if (src[1] >= '0' && src[1] <= '7') | |
463 | { | |
7ee7b84d | 464 | if (len == 3 && TOLOWER (src[2]) == 'l') |
252b5132 RH |
465 | { |
466 | *mode = L_8 | REG | direction; | |
467 | *reg = (src[1] - '0') + 8; | |
468 | return len; | |
469 | } | |
7ee7b84d | 470 | if (len == 3 && TOLOWER (src[2]) == 'h') |
252b5132 RH |
471 | { |
472 | *mode = L_8 | REG | direction; | |
473 | *reg = (src[1] - '0'); | |
474 | return len; | |
475 | } | |
476 | if (len == 2) | |
477 | { | |
478 | *mode = L_16 | REG | direction; | |
479 | *reg = (src[1] - '0'); | |
480 | return len; | |
481 | } | |
482 | } | |
483 | } | |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
1b680e4f RS |
488 | |
489 | /* Parse an immediate or address-related constant and store it in OP. | |
490 | If the user also specifies the operand's size, store that size | |
491 | in OP->MODE, otherwise leave it for later code to decide. */ | |
492 | ||
40f09f82 | 493 | static char * |
b54a3392 | 494 | parse_exp (char *src, struct h8_op *op) |
252b5132 | 495 | { |
1b680e4f | 496 | char *save; |
252b5132 | 497 | |
1b680e4f RS |
498 | save = input_line_pointer; |
499 | input_line_pointer = src; | |
500 | expression (&op->exp); | |
501 | if (op->exp.X_op == O_absent) | |
252b5132 | 502 | as_bad (_("missing operand")); |
1b680e4f | 503 | src = input_line_pointer; |
252b5132 | 504 | input_line_pointer = save; |
1b680e4f RS |
505 | |
506 | return skip_colonthing (src, &op->mode); | |
252b5132 RH |
507 | } |
508 | ||
1b680e4f RS |
509 | |
510 | /* If SRC starts with an explicit operand size, skip it and store the size | |
511 | in *MODE. Leave *MODE unchanged otherwise. */ | |
512 | ||
252b5132 | 513 | static char * |
b54a3392 | 514 | skip_colonthing (char *src, int *mode) |
252b5132 | 515 | { |
1b680e4f | 516 | if (*src == ':') |
252b5132 | 517 | { |
1b680e4f | 518 | src++; |
252b5132 | 519 | *mode &= ~SIZE; |
1b680e4f | 520 | if (src[0] == '8' && !ISDIGIT (src[1])) |
7ee7b84d | 521 | *mode |= L_8; |
1b680e4f | 522 | else if (src[0] == '2' && !ISDIGIT (src[1])) |
7ee7b84d | 523 | *mode |= L_2; |
1b680e4f | 524 | else if (src[0] == '3' && !ISDIGIT (src[1])) |
7ee7b84d | 525 | *mode |= L_3; |
1b680e4f | 526 | else if (src[0] == '4' && !ISDIGIT (src[1])) |
7ee7b84d | 527 | *mode |= L_4; |
1b680e4f | 528 | else if (src[0] == '5' && !ISDIGIT (src[1])) |
7ee7b84d | 529 | *mode |= L_5; |
1b680e4f | 530 | else if (src[0] == '2' && src[1] == '4' && !ISDIGIT (src[2])) |
7ee7b84d | 531 | *mode |= L_24; |
1b680e4f | 532 | else if (src[0] == '3' && src[1] == '2' && !ISDIGIT (src[2])) |
7ee7b84d | 533 | *mode |= L_32; |
1b680e4f | 534 | else if (src[0] == '1' && src[1] == '6' && !ISDIGIT (src[2])) |
7ee7b84d | 535 | *mode |= L_16; |
252b5132 | 536 | else |
7ee7b84d MS |
537 | as_bad (_("invalid operand size requested")); |
538 | ||
1b680e4f RS |
539 | while (ISDIGIT (*src)) |
540 | src++; | |
252b5132 | 541 | } |
1b680e4f | 542 | return src; |
252b5132 RH |
543 | } |
544 | ||
545 | /* The many forms of operand: | |
546 | ||
547 | Rn Register direct | |
548 | @Rn Register indirect | |
549 | @(exp[:16], Rn) Register indirect with displacement | |
550 | @Rn+ | |
551 | @-Rn | |
70d6ecf3 AM |
552 | @aa:8 absolute 8 bit |
553 | @aa:16 absolute 16 bit | |
252b5132 RH |
554 | @aa absolute 16 bit |
555 | ||
556 | #xx[:size] immediate data | |
70d6ecf3 | 557 | @(exp:[8], pc) pc rel |
3048287a | 558 | @@aa[:8] memory indirect. */ |
252b5132 | 559 | |
7ee7b84d | 560 | static int |
df7b86aa | 561 | constant_fits_width_p (struct h8_op *operand, offsetT width) |
7ee7b84d | 562 | { |
35a35807 AM |
563 | offsetT num; |
564 | ||
565 | num = ((operand->exp.X_add_number & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
566 | return (num & ~width) == 0 || (num | width) == ~0; | |
7ee7b84d MS |
567 | } |
568 | ||
569 | static int | |
b54a3392 | 570 | constant_fits_size_p (struct h8_op *operand, int size, int no_symbols) |
7ee7b84d | 571 | { |
35a35807 AM |
572 | offsetT num; |
573 | ||
7ee7b84d MS |
574 | if (no_symbols |
575 | && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0)) | |
576 | return 0; | |
35a35807 | 577 | num = operand->exp.X_add_number & 0xffffffff; |
7ee7b84d MS |
578 | switch (size) |
579 | { | |
580 | case L_2: | |
581 | return (num & ~3) == 0; | |
582 | case L_3: | |
583 | return (num & ~7) == 0; | |
584 | case L_3NZ: | |
585 | return num >= 1 && num < 8; | |
586 | case L_4: | |
587 | return (num & ~15) == 0; | |
588 | case L_5: | |
589 | return num >= 1 && num < 32; | |
590 | case L_8: | |
35a35807 AM |
591 | num = (num ^ 0x80000000) - 0x80000000; |
592 | return (num & ~0xFF) == 0 || (num | 0x7F) == ~0; | |
7ee7b84d MS |
593 | case L_8U: |
594 | return (num & ~0xFF) == 0; | |
595 | case L_16: | |
35a35807 AM |
596 | num = (num ^ 0x80000000) - 0x80000000; |
597 | return (num & ~0xFFFF) == 0 || (num | 0x7FFF) == ~0; | |
7ee7b84d MS |
598 | case L_16U: |
599 | return (num & ~0xFFFF) == 0; | |
600 | case L_32: | |
601 | return 1; | |
602 | default: | |
603 | abort (); | |
604 | } | |
605 | } | |
606 | ||
252b5132 | 607 | static void |
b54a3392 | 608 | get_operand (char **ptr, struct h8_op *op, int direction) |
252b5132 RH |
609 | { |
610 | char *src = *ptr; | |
611 | op_type mode; | |
612 | unsigned int num; | |
613 | unsigned int len; | |
614 | ||
7ee7b84d | 615 | op->mode = 0; |
252b5132 | 616 | |
3048287a NC |
617 | /* Check for '(' and ')' for instructions ldm and stm. */ |
618 | if (src[0] == '(' && src[8] == ')') | |
619 | ++ src; | |
620 | ||
252b5132 RH |
621 | /* Gross. Gross. ldm and stm have a format not easily handled |
622 | by get_operand. We deal with it explicitly here. */ | |
3739860c | 623 | if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
7ee7b84d MS |
624 | ISDIGIT (src[2]) && src[3] == '-' && |
625 | TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6])) | |
252b5132 RH |
626 | { |
627 | int low, high; | |
628 | ||
629 | low = src[2] - '0'; | |
630 | high = src[6] - '0'; | |
631 | ||
4892e510 NC |
632 | /* Check register pair's validity as per tech note TN-H8*-193A/E |
633 | from Renesas for H8S and H8SX hardware manual. */ | |
634 | if ( !(low == 0 && (high == 1 || high == 2 || high == 3)) | |
635 | && !(low == 1 && (high == 2 || high == 3 || high == 4) && SXmode) | |
636 | && !(low == 2 && (high == 3 || ((high == 4 || high == 5) && SXmode))) | |
637 | && !(low == 3 && (high == 4 || high == 5 || high == 6) && SXmode) | |
638 | && !(low == 4 && (high == 5 || high == 6)) | |
b4f16abb | 639 | && !(low == 4 && high == 7 && SXmode) |
4892e510 NC |
640 | && !(low == 5 && (high == 6 || high == 7) && SXmode) |
641 | && !(low == 6 && high == 7 && SXmode)) | |
252b5132 RH |
642 | as_bad (_("Invalid register list for ldm/stm\n")); |
643 | ||
252b5132 RH |
644 | /* Even sicker. We encode two registers into op->reg. One |
645 | for the low register to save, the other for the high | |
646 | register to save; we also set the high bit in op->reg | |
647 | so we know this is "very special". */ | |
648 | op->reg = 0x80000000 | (high << 8) | low; | |
649 | op->mode = REG; | |
3048287a NC |
650 | if (src[7] == ')') |
651 | *ptr = src + 8; | |
652 | else | |
653 | *ptr = src + 7; | |
252b5132 RH |
654 | return; |
655 | } | |
656 | ||
657 | len = parse_reg (src, &op->mode, &op->reg, direction); | |
658 | if (len) | |
659 | { | |
7ee7b84d MS |
660 | src += len; |
661 | if (*src == '.') | |
662 | { | |
663 | int size = op->mode & SIZE; | |
664 | switch (src[1]) | |
665 | { | |
666 | case 'l': case 'L': | |
667 | if (size != L_32) | |
668 | as_warn (_("mismatch between register and suffix")); | |
669 | op->mode = (op->mode & ~MODE) | LOWREG; | |
670 | break; | |
671 | case 'w': case 'W': | |
672 | if (size != L_32 && size != L_16) | |
673 | as_warn (_("mismatch between register and suffix")); | |
674 | op->mode = (op->mode & ~MODE) | LOWREG; | |
675 | op->mode = (op->mode & ~SIZE) | L_16; | |
676 | break; | |
677 | case 'b': case 'B': | |
678 | op->mode = (op->mode & ~MODE) | LOWREG; | |
679 | if (size != L_32 && size != L_8) | |
680 | as_warn (_("mismatch between register and suffix")); | |
681 | op->mode = (op->mode & ~MODE) | LOWREG; | |
682 | op->mode = (op->mode & ~SIZE) | L_8; | |
683 | break; | |
684 | default: | |
20203fb9 | 685 | as_warn (_("invalid suffix after register.")); |
7ee7b84d MS |
686 | break; |
687 | } | |
688 | src += 2; | |
689 | } | |
690 | *ptr = src; | |
252b5132 RH |
691 | return; |
692 | } | |
693 | ||
694 | if (*src == '@') | |
695 | { | |
696 | src++; | |
697 | if (*src == '@') | |
698 | { | |
1b680e4f | 699 | *ptr = parse_exp (src + 1, op); |
7ee7b84d MS |
700 | if (op->exp.X_add_number >= 0x100) |
701 | { | |
d4e2de6b | 702 | int divisor = 1; |
7ee7b84d MS |
703 | |
704 | op->mode = VECIND; | |
705 | /* FIXME : 2? or 4? */ | |
706 | if (op->exp.X_add_number >= 0x400) | |
707 | as_bad (_("address too high for vector table jmp/jsr")); | |
708 | else if (op->exp.X_add_number >= 0x200) | |
709 | divisor = 4; | |
710 | else | |
711 | divisor = 2; | |
712 | ||
713 | op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80; | |
714 | } | |
715 | else | |
716 | op->mode = MEMIND; | |
252b5132 | 717 | return; |
252b5132 RH |
718 | } |
719 | ||
7ee7b84d | 720 | if (*src == '-' || *src == '+') |
252b5132 | 721 | { |
1b680e4f | 722 | len = parse_reg (src + 1, &mode, &num, direction); |
252b5132 RH |
723 | if (len == 0) |
724 | { | |
70d6ecf3 | 725 | /* Oops, not a reg after all, must be ordinary exp. */ |
1b680e4f RS |
726 | op->mode = ABS | direction; |
727 | *ptr = parse_exp (src, op); | |
252b5132 | 728 | return; |
252b5132 RH |
729 | } |
730 | ||
d4e2de6b NC |
731 | if (((mode & SIZE) != PSIZE) |
732 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
733 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 734 | as_bad (_("Wrong size pointer register for architecture.")); |
1b680e4f RS |
735 | |
736 | op->mode = src[0] == '-' ? RDPREDEC : RDPREINC; | |
252b5132 | 737 | op->reg = num; |
1b680e4f | 738 | *ptr = src + 1 + len; |
252b5132 RH |
739 | return; |
740 | } | |
741 | if (*src == '(') | |
742 | { | |
252b5132 RH |
743 | src++; |
744 | ||
7ee7b84d MS |
745 | /* See if this is @(ERn.x, PC). */ |
746 | len = parse_reg (src, &mode, &op->reg, direction); | |
747 | if (len != 0 && (mode & MODE) == REG && src[len] == '.') | |
748 | { | |
749 | switch (TOLOWER (src[len + 1])) | |
750 | { | |
751 | case 'b': | |
752 | mode = PCIDXB | direction; | |
753 | break; | |
754 | case 'w': | |
755 | mode = PCIDXW | direction; | |
756 | break; | |
757 | case 'l': | |
758 | mode = PCIDXL | direction; | |
759 | break; | |
760 | default: | |
761 | mode = 0; | |
762 | break; | |
763 | } | |
764 | if (mode | |
765 | && src[len + 2] == ',' | |
3739860c | 766 | && TOLOWER (src[len + 3]) != 'p' |
7ee7b84d MS |
767 | && TOLOWER (src[len + 4]) != 'c' |
768 | && src[len + 5] != ')') | |
769 | { | |
770 | *ptr = src + len + 6; | |
771 | op->mode |= mode; | |
772 | return; | |
773 | } | |
774 | /* Fall through into disp case - the grammar is somewhat | |
775 | ambiguous, so we should try whether it's a DISP operand | |
776 | after all ("ER3.L" might be a poorly named label...). */ | |
777 | } | |
778 | ||
779 | /* Disp. */ | |
780 | ||
70d6ecf3 | 781 | /* Start off assuming a 16 bit offset. */ |
252b5132 | 782 | |
1b680e4f | 783 | src = parse_exp (src, op); |
252b5132 RH |
784 | if (*src == ')') |
785 | { | |
252b5132 | 786 | op->mode |= ABS | direction; |
1b680e4f | 787 | *ptr = src + 1; |
252b5132 RH |
788 | return; |
789 | } | |
790 | ||
791 | if (*src != ',') | |
792 | { | |
793 | as_bad (_("expected @(exp, reg16)")); | |
794 | return; | |
252b5132 RH |
795 | } |
796 | src++; | |
797 | ||
798 | len = parse_reg (src, &mode, &op->reg, direction); | |
7ee7b84d | 799 | if (len == 0 || (mode & MODE) != REG) |
252b5132 RH |
800 | { |
801 | as_bad (_("expected @(exp, reg16)")); | |
802 | return; | |
803 | } | |
252b5132 | 804 | src += len; |
7ee7b84d MS |
805 | if (src[0] == '.') |
806 | { | |
807 | switch (TOLOWER (src[1])) | |
808 | { | |
809 | case 'b': | |
810 | op->mode |= INDEXB | direction; | |
811 | break; | |
812 | case 'w': | |
813 | op->mode |= INDEXW | direction; | |
814 | break; | |
815 | case 'l': | |
816 | op->mode |= INDEXL | direction; | |
817 | break; | |
818 | default: | |
819 | as_bad (_("expected .L, .W or .B for register in indexed addressing mode")); | |
820 | } | |
821 | src += 2; | |
822 | op->reg &= 7; | |
823 | } | |
824 | else | |
825 | op->mode |= DISP | direction; | |
1b680e4f | 826 | src = skip_colonthing (src, &op->mode); |
252b5132 | 827 | |
8a4c2869 | 828 | if (*src != ')') |
252b5132 RH |
829 | { |
830 | as_bad (_("expected @(exp, reg16)")); | |
831 | return; | |
832 | } | |
833 | *ptr = src + 1; | |
252b5132 RH |
834 | return; |
835 | } | |
836 | len = parse_reg (src, &mode, &num, direction); | |
837 | ||
838 | if (len) | |
839 | { | |
840 | src += len; | |
7ee7b84d | 841 | if (*src == '+' || *src == '-') |
252b5132 | 842 | { |
d4e2de6b NC |
843 | if (((mode & SIZE) != PSIZE) |
844 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
845 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 846 | as_bad (_("Wrong size pointer register for architecture.")); |
7ee7b84d | 847 | op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC; |
252b5132 | 848 | op->reg = num; |
7ee7b84d | 849 | src++; |
252b5132 RH |
850 | *ptr = src; |
851 | return; | |
852 | } | |
d4e2de6b NC |
853 | if (((mode & SIZE) != PSIZE) |
854 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
855 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 RH |
856 | as_bad (_("Wrong size pointer register for architecture.")); |
857 | ||
858 | op->mode = direction | IND | PSIZE; | |
859 | op->reg = num; | |
860 | *ptr = src; | |
861 | ||
862 | return; | |
863 | } | |
864 | else | |
865 | { | |
866 | /* must be a symbol */ | |
867 | ||
868 | op->mode = ABS | direction; | |
1b680e4f | 869 | *ptr = parse_exp (src, op); |
252b5132 RH |
870 | return; |
871 | } | |
872 | } | |
873 | ||
252b5132 RH |
874 | if (*src == '#') |
875 | { | |
252b5132 | 876 | op->mode = IMM; |
1b680e4f | 877 | *ptr = parse_exp (src + 1, op); |
252b5132 RH |
878 | return; |
879 | } | |
3739860c | 880 | else if (strncmp (src, "mach", 4) == 0 || |
7ee7b84d | 881 | strncmp (src, "macl", 4) == 0 || |
3739860c | 882 | strncmp (src, "MACH", 4) == 0 || |
7ee7b84d | 883 | strncmp (src, "MACL", 4) == 0) |
252b5132 | 884 | { |
7ee7b84d | 885 | op->reg = TOLOWER (src[3]) == 'l'; |
252b5132 RH |
886 | op->mode = MACREG; |
887 | *ptr = src + 4; | |
888 | return; | |
889 | } | |
890 | else | |
891 | { | |
1b680e4f RS |
892 | op->mode = PCREL; |
893 | *ptr = parse_exp (src, op); | |
252b5132 RH |
894 | } |
895 | } | |
896 | ||
70d6ecf3 | 897 | static char * |
b54a3392 | 898 | get_operands (unsigned int noperands, char *op_end, struct h8_op *operand) |
252b5132 RH |
899 | { |
900 | char *ptr = op_end; | |
901 | ||
902 | switch (noperands) | |
903 | { | |
904 | case 0: | |
252b5132 RH |
905 | break; |
906 | ||
907 | case 1: | |
908 | ptr++; | |
7ee7b84d | 909 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
910 | if (*ptr == ',') |
911 | { | |
912 | ptr++; | |
7ee7b84d | 913 | get_operand (&ptr, operand + 1, DST); |
252b5132 | 914 | } |
252b5132 | 915 | break; |
70d6ecf3 | 916 | |
252b5132 RH |
917 | case 2: |
918 | ptr++; | |
7ee7b84d | 919 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
920 | if (*ptr == ',') |
921 | ptr++; | |
7ee7b84d MS |
922 | get_operand (&ptr, operand + 1, DST); |
923 | break; | |
924 | ||
925 | case 3: | |
926 | ptr++; | |
927 | get_operand (&ptr, operand + 0, SRC); | |
928 | if (*ptr == ',') | |
929 | ptr++; | |
930 | get_operand (&ptr, operand + 1, DST); | |
931 | if (*ptr == ',') | |
932 | ptr++; | |
933 | get_operand (&ptr, operand + 2, OP3); | |
252b5132 RH |
934 | break; |
935 | ||
936 | default: | |
937 | abort (); | |
938 | } | |
939 | ||
252b5132 RH |
940 | return ptr; |
941 | } | |
942 | ||
7ee7b84d MS |
943 | /* MOVA has special requirements. Rather than adding twice the amount of |
944 | addressing modes, we simply special case it a bit. */ | |
945 | static void | |
946 | get_mova_operands (char *op_end, struct h8_op *operand) | |
947 | { | |
948 | char *ptr = op_end; | |
949 | ||
950 | if (ptr[1] != '@' || ptr[2] != '(') | |
951 | goto error; | |
952 | ptr += 3; | |
953 | operand[0].mode = 0; | |
1b680e4f | 954 | ptr = parse_exp (ptr, &operand[0]); |
7ee7b84d MS |
955 | |
956 | if (*ptr !=',') | |
957 | goto error; | |
958 | ptr++; | |
959 | get_operand (&ptr, operand + 1, DST); | |
960 | ||
961 | if (*ptr =='.') | |
962 | { | |
963 | ptr++; | |
964 | switch (*ptr++) | |
965 | { | |
966 | case 'b': case 'B': | |
967 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
968 | break; | |
969 | case 'w': case 'W': | |
970 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
971 | break; | |
972 | case 'l': case 'L': | |
973 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
974 | break; | |
975 | default: | |
976 | goto error; | |
977 | } | |
978 | } | |
979 | else if ((operand[1].mode & MODE) == LOWREG) | |
980 | { | |
3739860c | 981 | switch (operand[1].mode & SIZE) |
7ee7b84d MS |
982 | { |
983 | case L_8: | |
984 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
985 | break; | |
986 | case L_16: | |
987 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
988 | break; | |
989 | case L_32: | |
990 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
991 | break; | |
992 | default: | |
993 | goto error; | |
994 | } | |
995 | } | |
996 | else | |
997 | goto error; | |
998 | ||
999 | if (*ptr++ != ')' || *ptr++ != ',') | |
1000 | goto error; | |
1001 | get_operand (&ptr, operand + 2, OP3); | |
1002 | /* See if we can use the short form of MOVA. */ | |
1003 | if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG) | |
1004 | && (operand[2].mode & MODE) == REG | |
1005 | && (operand[1].reg & 7) == (operand[2].reg & 7)) | |
1006 | { | |
1007 | operand[1].mode = operand[2].mode = 0; | |
1008 | operand[0].reg = operand[2].reg & 7; | |
1009 | } | |
1010 | return; | |
1011 | ||
1012 | error: | |
1013 | as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\"")); | |
7ee7b84d MS |
1014 | } |
1015 | ||
1016 | static void | |
1017 | get_rtsl_operands (char *ptr, struct h8_op *operand) | |
1018 | { | |
2132e3a3 AM |
1019 | int mode, len, type = 0; |
1020 | unsigned int num, num2; | |
7ee7b84d MS |
1021 | |
1022 | ptr++; | |
1023 | if (*ptr == '(') | |
1024 | { | |
1025 | ptr++; | |
1026 | type = 1; | |
1027 | } | |
1028 | len = parse_reg (ptr, &mode, &num, SRC); | |
1029 | if (len == 0 || (mode & MODE) != REG) | |
1030 | { | |
1031 | as_bad (_("expected register")); | |
1032 | return; | |
1033 | } | |
0613284f RS |
1034 | ptr += len; |
1035 | if (*ptr == '-') | |
7ee7b84d | 1036 | { |
0613284f | 1037 | len = parse_reg (++ptr, &mode, &num2, SRC); |
7ee7b84d MS |
1038 | if (len == 0 || (mode & MODE) != REG) |
1039 | { | |
1040 | as_bad (_("expected register")); | |
1041 | return; | |
1042 | } | |
1043 | ptr += len; | |
7ee7b84d MS |
1044 | /* CONST_xxx are used as placeholders in the opcode table. */ |
1045 | num = num2 - num; | |
2132e3a3 | 1046 | if (num > 3) |
7ee7b84d MS |
1047 | { |
1048 | as_bad (_("invalid register list")); | |
1049 | return; | |
1050 | } | |
1051 | } | |
1052 | else | |
1053 | num2 = num, num = 0; | |
0613284f RS |
1054 | if (type == 1 && *ptr++ != ')') |
1055 | { | |
1056 | as_bad (_("expected closing paren")); | |
1057 | return; | |
1058 | } | |
7ee7b84d MS |
1059 | operand[0].mode = RS32; |
1060 | operand[1].mode = RD32; | |
1061 | operand[0].reg = num; | |
1062 | operand[1].reg = num2; | |
1063 | } | |
1064 | ||
252b5132 RH |
1065 | /* Passed a pointer to a list of opcodes which use different |
1066 | addressing modes, return the opcode which matches the opcodes | |
70d6ecf3 | 1067 | provided. */ |
3048287a | 1068 | |
a720f7bc | 1069 | static const struct h8_instruction * |
b54a3392 KH |
1070 | get_specific (const struct h8_instruction *instruction, |
1071 | struct h8_op *operands, int size) | |
252b5132 | 1072 | { |
a720f7bc | 1073 | const struct h8_instruction *this_try = instruction; |
7ee7b84d | 1074 | const struct h8_instruction *found_other = 0, *found_mismatched = 0; |
252b5132 | 1075 | int found = 0; |
a720f7bc | 1076 | int this_index = instruction->idx; |
7ee7b84d | 1077 | int noperands = 0; |
252b5132 RH |
1078 | |
1079 | /* There's only one ldm/stm and it's easier to just | |
1080 | get out quick for them. */ | |
7ee7b84d MS |
1081 | if (OP_KIND (instruction->opcode->how) == O_LDM |
1082 | || OP_KIND (instruction->opcode->how) == O_STM) | |
252b5132 RH |
1083 | return this_try; |
1084 | ||
7ee7b84d MS |
1085 | while (noperands < 3 && operands[noperands].mode != 0) |
1086 | noperands++; | |
1087 | ||
a720f7bc | 1088 | while (this_index == instruction->idx && !found) |
252b5132 | 1089 | { |
7ee7b84d | 1090 | int this_size; |
252b5132 | 1091 | |
7ee7b84d | 1092 | found = 1; |
a720f7bc | 1093 | this_try = instruction++; |
7ee7b84d | 1094 | this_size = this_try->opcode->how & SN; |
252b5132 | 1095 | |
7ee7b84d MS |
1096 | if (this_try->noperands != noperands) |
1097 | found = 0; | |
1098 | else if (this_try->noperands > 0) | |
252b5132 | 1099 | { |
3048287a | 1100 | int i; |
252b5132 RH |
1101 | |
1102 | for (i = 0; i < this_try->noperands && found; i++) | |
1103 | { | |
a720f7bc | 1104 | op_type op = this_try->opcode->args.nib[i]; |
7ee7b84d MS |
1105 | int op_mode = op & MODE; |
1106 | int op_size = op & SIZE; | |
252b5132 | 1107 | int x = operands[i].mode; |
7ee7b84d MS |
1108 | int x_mode = x & MODE; |
1109 | int x_size = x & SIZE; | |
252b5132 | 1110 | |
7ee7b84d | 1111 | if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG)) |
252b5132 | 1112 | { |
7ee7b84d MS |
1113 | if ((x_size == L_8 && (operands[i].reg & 8) == 0) |
1114 | || (x_size == L_16 && (operands[i].reg & 8) == 8)) | |
1115 | as_warn (_("can't use high part of register in operand %d"), i); | |
1116 | ||
1117 | if (x_size != op_size) | |
1118 | found = 0; | |
252b5132 | 1119 | } |
7ee7b84d | 1120 | else if (op_mode == REG) |
252b5132 | 1121 | { |
7ee7b84d MS |
1122 | if (x_mode == LOWREG) |
1123 | x_mode = REG; | |
1124 | if (x_mode != REG) | |
252b5132 RH |
1125 | found = 0; |
1126 | ||
7ee7b84d MS |
1127 | if (x_size == L_P) |
1128 | x_size = (Hmode ? L_32 : L_16); | |
1129 | if (op_size == L_P) | |
1130 | op_size = (Hmode ? L_32 : L_16); | |
252b5132 | 1131 | |
70d6ecf3 | 1132 | /* The size of the reg is v important. */ |
7ee7b84d | 1133 | if (op_size != x_size) |
252b5132 RH |
1134 | found = 0; |
1135 | } | |
7ee7b84d | 1136 | else if (op_mode & CTRL) /* control register */ |
252b5132 | 1137 | { |
7ee7b84d MS |
1138 | if (!(x_mode & CTRL)) |
1139 | found = 0; | |
1140 | ||
1141 | switch (x_mode) | |
1142 | { | |
1143 | case CCR: | |
1144 | if (op_mode != CCR && | |
1145 | op_mode != CCR_EXR && | |
1146 | op_mode != CC_EX_VB_SB) | |
1147 | found = 0; | |
1148 | break; | |
1149 | case EXR: | |
1150 | if (op_mode != EXR && | |
1151 | op_mode != CCR_EXR && | |
1152 | op_mode != CC_EX_VB_SB) | |
1153 | found = 0; | |
1154 | break; | |
1155 | case MACH: | |
1156 | if (op_mode != MACH && | |
1157 | op_mode != MACREG) | |
1158 | found = 0; | |
1159 | break; | |
1160 | case MACL: | |
1161 | if (op_mode != MACL && | |
1162 | op_mode != MACREG) | |
1163 | found = 0; | |
1164 | break; | |
1165 | case VBR: | |
1166 | if (op_mode != VBR && | |
1167 | op_mode != VBR_SBR && | |
1168 | op_mode != CC_EX_VB_SB) | |
1169 | found = 0; | |
1170 | break; | |
1171 | case SBR: | |
1172 | if (op_mode != SBR && | |
1173 | op_mode != VBR_SBR && | |
1174 | op_mode != CC_EX_VB_SB) | |
1175 | found = 0; | |
1176 | break; | |
1177 | } | |
1178 | } | |
1179 | else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL)) | |
1180 | { | |
1181 | operands[i].mode &= ~MODE; | |
252b5132 | 1182 | operands[i].mode |= ABSJMP; |
70d6ecf3 | 1183 | /* But it may not be 24 bits long. */ |
7ee7b84d | 1184 | if (x_mode == ABS && !Hmode) |
252b5132 RH |
1185 | { |
1186 | operands[i].mode &= ~SIZE; | |
1187 | operands[i].mode |= L_16; | |
1188 | } | |
7ee7b84d MS |
1189 | if ((operands[i].mode & SIZE) == L_32 |
1190 | && (op_mode & SIZE) != L_32) | |
1191 | found = 0; | |
252b5132 | 1192 | } |
7ee7b84d | 1193 | else if (x_mode == IMM && op_mode != IMM) |
252b5132 | 1194 | { |
35a35807 | 1195 | offsetT num = operands[i].exp.X_add_number & 0xffffffff; |
7ee7b84d MS |
1196 | if (op_mode == KBIT || op_mode == DBIT) |
1197 | /* This is ok if the immediate value is sensible. */; | |
1198 | else if (op_mode == CONST_2) | |
1199 | found = num == 2; | |
1200 | else if (op_mode == CONST_4) | |
1201 | found = num == 4; | |
1202 | else if (op_mode == CONST_8) | |
1203 | found = num == 8; | |
1204 | else if (op_mode == CONST_16) | |
1205 | found = num == 16; | |
1206 | else | |
1207 | found = 0; | |
252b5132 | 1208 | } |
7ee7b84d | 1209 | else if (op_mode == PCREL && op_mode == x_mode) |
252b5132 | 1210 | { |
ba18dd6f | 1211 | /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour: |
7ee7b84d | 1212 | If x_size is L_8, promote it. */ |
ba18dd6f AO |
1213 | if (OP_KIND (this_try->opcode->how) == O_MOVSD |
1214 | || OP_KIND (this_try->opcode->how) == O_BSRBC | |
1215 | || OP_KIND (this_try->opcode->how) == O_BSRBS) | |
7ee7b84d MS |
1216 | if (x_size == L_8) |
1217 | x_size = L_16; | |
1218 | ||
70d6ecf3 | 1219 | /* The size of the displacement is important. */ |
7ee7b84d | 1220 | if (op_size != x_size) |
252b5132 RH |
1221 | found = 0; |
1222 | } | |
7ee7b84d MS |
1223 | else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS |
1224 | || op_mode == INDEXB || op_mode == INDEXW | |
1225 | || op_mode == INDEXL) | |
1226 | && op_mode == x_mode) | |
252b5132 RH |
1227 | { |
1228 | /* Promote a L_24 to L_32 if it makes us match. */ | |
7ee7b84d | 1229 | if (x_size == L_24 && op_size == L_32) |
252b5132 | 1230 | { |
7ee7b84d MS |
1231 | x &= ~SIZE; |
1232 | x |= x_size = L_32; | |
252b5132 | 1233 | } |
7ee7b84d | 1234 | |
7ee7b84d | 1235 | if (((x_size == L_16 && op_size == L_16U) |
2d0d09ca | 1236 | || (x_size == L_8 && op_size == L_8U) |
7ee7b84d MS |
1237 | || (x_size == L_3 && op_size == L_3NZ)) |
1238 | /* We're deliberately more permissive for ABS modes. */ | |
1239 | && (op_mode == ABS | |
1240 | || constant_fits_size_p (operands + i, op_size, | |
1241 | op & NO_SYMBOLS))) | |
1242 | x_size = op_size; | |
1243 | ||
1244 | if (x_size != 0 && op_size != x_size) | |
1245 | found = 0; | |
1246 | else if (x_size == 0 | |
1247 | && ! constant_fits_size_p (operands + i, op_size, | |
1248 | op & NO_SYMBOLS)) | |
252b5132 RH |
1249 | found = 0; |
1250 | } | |
7ee7b84d | 1251 | else if (op_mode != x_mode) |
252b5132 RH |
1252 | { |
1253 | found = 0; | |
70d6ecf3 | 1254 | } |
252b5132 RH |
1255 | } |
1256 | } | |
7ee7b84d MS |
1257 | if (found) |
1258 | { | |
1259 | if ((this_try->opcode->available == AV_H8SX && ! SXmode) | |
d4ea8842 | 1260 | || (this_try->opcode->available == AV_H8S && ! Smode) |
7ee7b84d MS |
1261 | || (this_try->opcode->available == AV_H8H && ! Hmode)) |
1262 | found = 0, found_other = this_try; | |
1263 | else if (this_size != size && (this_size != SN && size != SN)) | |
1264 | found_mismatched = this_try, found = 0; | |
1265 | ||
1266 | } | |
252b5132 RH |
1267 | } |
1268 | if (found) | |
1269 | return this_try; | |
7ee7b84d MS |
1270 | if (found_other) |
1271 | { | |
1272 | as_warn (_("Opcode `%s' with these operand types not available in %s mode"), | |
1273 | found_other->opcode->name, | |
1274 | (! Hmode && ! Smode ? "H8/300" | |
1275 | : SXmode ? "H8sx" | |
1276 | : Smode ? "H8/300S" | |
1277 | : "H8/300H")); | |
1278 | } | |
1279 | else if (found_mismatched) | |
1280 | { | |
1281 | as_warn (_("mismatch between opcode size and operand size")); | |
1282 | return found_mismatched; | |
1283 | } | |
1284 | return 0; | |
252b5132 RH |
1285 | } |
1286 | ||
1287 | static void | |
e0471c16 | 1288 | check_operand (struct h8_op *operand, unsigned int width, const char *string) |
252b5132 RH |
1289 | { |
1290 | if (operand->exp.X_add_symbol == 0 | |
1291 | && operand->exp.X_op_symbol == 0) | |
1292 | { | |
70d6ecf3 AM |
1293 | /* No symbol involved, let's look at offset, it's dangerous if |
1294 | any of the high bits are not 0 or ff's, find out by oring or | |
1295 | anding with the width and seeing if the answer is 0 or all | |
1296 | fs. */ | |
252b5132 | 1297 | |
7ee7b84d | 1298 | if (! constant_fits_width_p (operand, width)) |
252b5132 | 1299 | { |
70d6ecf3 | 1300 | if (width == 255 |
252b5132 RH |
1301 | && (operand->exp.X_add_number & 0xff00) == 0xff00) |
1302 | { | |
1303 | /* Just ignore this one - which happens when trying to | |
1304 | fit a 16 bit address truncated into an 8 bit address | |
1305 | of something like bset. */ | |
1306 | } | |
166e23f9 KH |
1307 | else if (strcmp (string, "@") == 0 |
1308 | && width == 0xffff | |
1309 | && (operand->exp.X_add_number & 0xff8000) == 0xff8000) | |
1310 | { | |
1311 | /* Just ignore this one - which happens when trying to | |
1312 | fit a 24 bit address truncated into a 16 bit address | |
1313 | of something like mov.w. */ | |
1314 | } | |
70d6ecf3 | 1315 | else |
252b5132 RH |
1316 | { |
1317 | as_warn (_("operand %s0x%lx out of range."), string, | |
1318 | (unsigned long) operand->exp.X_add_number); | |
1319 | } | |
1320 | } | |
1321 | } | |
252b5132 RH |
1322 | } |
1323 | ||
1324 | /* RELAXMODE has one of 3 values: | |
1325 | ||
1326 | 0 Output a "normal" reloc, no relaxing possible for this insn/reloc | |
1327 | ||
1328 | 1 Output a relaxable 24bit absolute mov.w address relocation | |
1329 | (may relax into a 16bit absolute address). | |
1330 | ||
1331 | 2 Output a relaxable 16/24 absolute mov.b address relocation | |
1332 | (may relax into an 8bit absolute address). */ | |
1333 | ||
1334 | static void | |
bcb012d3 | 1335 | do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode, const struct h8_instruction *this_try) |
252b5132 RH |
1336 | { |
1337 | int idx; | |
1338 | int size; | |
1339 | int where; | |
7ee7b84d | 1340 | char *bytes = frag_now->fr_literal + offset; |
252b5132 | 1341 | |
e0471c16 | 1342 | const char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; |
252b5132 RH |
1343 | |
1344 | if (operand->exp.X_add_symbol == 0) | |
1345 | { | |
252b5132 RH |
1346 | switch (operand->mode & SIZE) |
1347 | { | |
1348 | case L_2: | |
1349 | check_operand (operand, 0x3, t); | |
7ee7b84d | 1350 | bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4); |
252b5132 RH |
1351 | break; |
1352 | case L_3: | |
7ee7b84d | 1353 | case L_3NZ: |
252b5132 | 1354 | check_operand (operand, 0x7, t); |
7ee7b84d MS |
1355 | bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4); |
1356 | break; | |
1357 | case L_4: | |
1358 | check_operand (operand, 0xF, t); | |
1359 | bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4); | |
1360 | break; | |
1361 | case L_5: | |
1362 | check_operand (operand, 0x1F, t); | |
1363 | bytes[0] |= operand->exp.X_add_number & 31; | |
252b5132 RH |
1364 | break; |
1365 | case L_8: | |
7ee7b84d | 1366 | case L_8U: |
252b5132 | 1367 | check_operand (operand, 0xff, t); |
7ee7b84d | 1368 | bytes[0] |= operand->exp.X_add_number; |
252b5132 RH |
1369 | break; |
1370 | case L_16: | |
7ee7b84d | 1371 | case L_16U: |
252b5132 | 1372 | check_operand (operand, 0xffff, t); |
7ee7b84d MS |
1373 | bytes[0] |= operand->exp.X_add_number >> 8; |
1374 | bytes[1] |= operand->exp.X_add_number >> 0; | |
bcb012d3 DD |
1375 | #ifdef OBJ_ELF |
1376 | /* MOVA needs both relocs to relax the second operand properly. */ | |
1377 | if (relaxmode != 0 | |
1378 | && (OP_KIND(this_try->opcode->how) == O_MOVAB | |
1379 | || OP_KIND(this_try->opcode->how) == O_MOVAW | |
1380 | || OP_KIND(this_try->opcode->how) == O_MOVAL)) | |
1381 | { | |
1382 | idx = BFD_RELOC_16; | |
1383 | fix_new_exp (frag_now, offset, 2, &operand->exp, 0, idx); | |
1384 | } | |
1385 | #endif | |
252b5132 RH |
1386 | break; |
1387 | case L_24: | |
1388 | check_operand (operand, 0xffffff, t); | |
7ee7b84d MS |
1389 | bytes[0] |= operand->exp.X_add_number >> 16; |
1390 | bytes[1] |= operand->exp.X_add_number >> 8; | |
1391 | bytes[2] |= operand->exp.X_add_number >> 0; | |
252b5132 RH |
1392 | break; |
1393 | ||
1394 | case L_32: | |
70d6ecf3 | 1395 | /* This should be done with bfd. */ |
7ee7b84d MS |
1396 | bytes[0] |= operand->exp.X_add_number >> 24; |
1397 | bytes[1] |= operand->exp.X_add_number >> 16; | |
1398 | bytes[2] |= operand->exp.X_add_number >> 8; | |
1399 | bytes[3] |= operand->exp.X_add_number >> 0; | |
4132022d AM |
1400 | if (relaxmode != 0) |
1401 | { | |
81f5558e NC |
1402 | #ifdef OBJ_ELF |
1403 | if ((operand->mode & MODE) == DISP && relaxmode == 1) | |
1404 | idx = BFD_RELOC_H8_DISP32A16; | |
1405 | else | |
1406 | #endif | |
1407 | idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1; | |
4132022d AM |
1408 | fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx); |
1409 | } | |
252b5132 RH |
1410 | break; |
1411 | } | |
252b5132 RH |
1412 | } |
1413 | else | |
1414 | { | |
1415 | switch (operand->mode & SIZE) | |
1416 | { | |
252b5132 RH |
1417 | case L_24: |
1418 | case L_32: | |
1419 | size = 4; | |
1420 | where = (operand->mode & SIZE) == L_24 ? -1 : 0; | |
81f5558e NC |
1421 | #ifdef OBJ_ELF |
1422 | if ((operand->mode & MODE) == DISP && relaxmode == 1) | |
1423 | idx = BFD_RELOC_H8_DISP32A16; | |
1424 | else | |
1425 | #endif | |
252b5132 RH |
1426 | if (relaxmode == 2) |
1427 | idx = R_MOV24B1; | |
1428 | else if (relaxmode == 1) | |
1429 | idx = R_MOVL1; | |
1430 | else | |
1431 | idx = R_RELLONG; | |
1432 | break; | |
1433 | default: | |
70d6ecf3 | 1434 | as_bad (_("Can't work out size of operand.\n")); |
1a0670f3 | 1435 | /* Fall through. */ |
252b5132 | 1436 | case L_16: |
7ee7b84d | 1437 | case L_16U: |
252b5132 RH |
1438 | size = 2; |
1439 | where = 0; | |
1440 | if (relaxmode == 2) | |
1441 | idx = R_MOV16B1; | |
1442 | else | |
1443 | idx = R_RELWORD; | |
4132022d AM |
1444 | operand->exp.X_add_number = |
1445 | ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
7ee7b84d | 1446 | operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1]; |
252b5132 RH |
1447 | break; |
1448 | case L_8: | |
1449 | size = 1; | |
1450 | where = 0; | |
1451 | idx = R_RELBYTE; | |
4132022d AM |
1452 | operand->exp.X_add_number = |
1453 | ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
7ee7b84d | 1454 | operand->exp.X_add_number |= bytes[0]; |
252b5132 RH |
1455 | } |
1456 | ||
1457 | fix_new_exp (frag_now, | |
1458 | offset + where, | |
1459 | size, | |
1460 | &operand->exp, | |
1461 | 0, | |
1462 | idx); | |
1463 | } | |
252b5132 RH |
1464 | } |
1465 | ||
70d6ecf3 | 1466 | /* Now we know what sort of opcodes it is, let's build the bytes. */ |
3048287a | 1467 | |
252b5132 | 1468 | static void |
b54a3392 | 1469 | build_bytes (const struct h8_instruction *this_try, struct h8_op *operand) |
252b5132 | 1470 | { |
3048287a | 1471 | int i; |
252b5132 | 1472 | char *output = frag_more (this_try->length); |
d1e50f8a | 1473 | const op_type *nibble_ptr = this_try->opcode->data.nib; |
252b5132 RH |
1474 | op_type c; |
1475 | unsigned int nibble_count = 0; | |
7ee7b84d | 1476 | int op_at[3]; |
3048287a | 1477 | int nib = 0; |
252b5132 | 1478 | int movb = 0; |
7ee7b84d | 1479 | char asnibbles[100]; |
252b5132 | 1480 | char *p = asnibbles; |
7ee7b84d | 1481 | int high, low; |
252b5132 | 1482 | |
d4ea8842 | 1483 | if (!Hmode && this_try->opcode->available != AV_H8) |
252b5132 | 1484 | as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"), |
a720f7bc | 1485 | this_try->opcode->name); |
3739860c L |
1486 | else if (!Smode |
1487 | && this_try->opcode->available != AV_H8 | |
d4ea8842 MS |
1488 | && this_try->opcode->available != AV_H8H) |
1489 | as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"), | |
1490 | this_try->opcode->name); | |
3739860c | 1491 | else if (!SXmode |
d4ea8842 MS |
1492 | && this_try->opcode->available != AV_H8 |
1493 | && this_try->opcode->available != AV_H8H | |
1494 | && this_try->opcode->available != AV_H8S) | |
1495 | as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"), | |
1496 | this_try->opcode->name); | |
252b5132 | 1497 | |
7ee7b84d | 1498 | while (*nibble_ptr != (op_type) E) |
252b5132 RH |
1499 | { |
1500 | int d; | |
7ee7b84d MS |
1501 | |
1502 | nib = 0; | |
252b5132 RH |
1503 | c = *nibble_ptr++; |
1504 | ||
7ee7b84d | 1505 | d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0; |
252b5132 RH |
1506 | |
1507 | if (c < 16) | |
3048287a | 1508 | nib = c; |
252b5132 RH |
1509 | else |
1510 | { | |
7ee7b84d MS |
1511 | int c2 = c & MODE; |
1512 | ||
1513 | if (c2 == REG || c2 == LOWREG | |
1514 | || c2 == IND || c2 == PREINC || c2 == PREDEC | |
1515 | || c2 == POSTINC || c2 == POSTDEC) | |
1516 | { | |
1517 | nib = operand[d].reg; | |
1518 | if (c2 == LOWREG) | |
1519 | nib &= 7; | |
1520 | } | |
1521 | ||
1522 | else if (c & CTRL) /* Control reg operand. */ | |
3048287a NC |
1523 | nib = operand[d].reg; |
1524 | ||
252b5132 | 1525 | else if ((c & DISPREG) == (DISPREG)) |
7ee7b84d MS |
1526 | { |
1527 | nib = operand[d].reg; | |
1528 | } | |
1529 | else if (c2 == ABS) | |
252b5132 RH |
1530 | { |
1531 | operand[d].mode = c; | |
7ee7b84d | 1532 | op_at[d] = nibble_count; |
252b5132 RH |
1533 | nib = 0; |
1534 | } | |
7ee7b84d MS |
1535 | else if (c2 == IMM || c2 == PCREL || c2 == ABS |
1536 | || (c & ABSJMP) || c2 == DISP) | |
252b5132 RH |
1537 | { |
1538 | operand[d].mode = c; | |
7ee7b84d | 1539 | op_at[d] = nibble_count; |
252b5132 RH |
1540 | nib = 0; |
1541 | } | |
7ee7b84d | 1542 | else if ((c & IGNORE) || (c & DATA)) |
3048287a NC |
1543 | nib = 0; |
1544 | ||
7ee7b84d | 1545 | else if (c2 == DBIT) |
252b5132 RH |
1546 | { |
1547 | switch (operand[0].exp.X_add_number) | |
1548 | { | |
1549 | case 1: | |
1550 | nib = c; | |
1551 | break; | |
1552 | case 2: | |
1553 | nib = 0x8 | c; | |
1554 | break; | |
1555 | default: | |
1556 | as_bad (_("Need #1 or #2 here")); | |
1557 | } | |
1558 | } | |
7ee7b84d | 1559 | else if (c2 == KBIT) |
252b5132 RH |
1560 | { |
1561 | switch (operand[0].exp.X_add_number) | |
1562 | { | |
1563 | case 1: | |
1564 | nib = 0; | |
1565 | break; | |
1566 | case 2: | |
1567 | nib = 8; | |
1568 | break; | |
1569 | case 4: | |
1570 | if (!Hmode) | |
1571 | as_warn (_("#4 not valid on H8/300.")); | |
1572 | nib = 9; | |
1573 | break; | |
1574 | ||
1575 | default: | |
1576 | as_bad (_("Need #1 or #2 here")); | |
1577 | break; | |
1578 | } | |
70d6ecf3 | 1579 | /* Stop it making a fix. */ |
252b5132 RH |
1580 | operand[0].mode = 0; |
1581 | } | |
1582 | ||
1583 | if (c & MEMRELAX) | |
3048287a | 1584 | operand[d].mode |= MEMRELAX; |
252b5132 RH |
1585 | |
1586 | if (c & B31) | |
3048287a | 1587 | nib |= 0x8; |
252b5132 | 1588 | |
7ee7b84d MS |
1589 | if (c & B21) |
1590 | nib |= 0x4; | |
1591 | ||
1592 | if (c & B11) | |
1593 | nib |= 0x2; | |
1594 | ||
1595 | if (c & B01) | |
1596 | nib |= 0x1; | |
1597 | ||
1598 | if (c2 == MACREG) | |
252b5132 | 1599 | { |
f0c56b90 NC |
1600 | if (operand[0].mode == MACREG) |
1601 | /* stmac has mac[hl] as the first operand. */ | |
1602 | nib = 2 + operand[0].reg; | |
1603 | else | |
1604 | /* ldmac has mac[hl] as the second operand. */ | |
1605 | nib = 2 + operand[1].reg; | |
252b5132 RH |
1606 | } |
1607 | } | |
1608 | nibble_count++; | |
1609 | ||
1610 | *p++ = nib; | |
1611 | } | |
1612 | ||
1613 | /* Disgusting. Why, oh why didn't someone ask us for advice | |
1614 | on the assembler format. */ | |
7ee7b84d | 1615 | if (OP_KIND (this_try->opcode->how) == O_LDM) |
252b5132 | 1616 | { |
7ee7b84d MS |
1617 | high = (operand[1].reg >> 8) & 0xf; |
1618 | low = (operand[1].reg) & 0xf; | |
252b5132 | 1619 | asnibbles[2] = high - low; |
7ee7b84d MS |
1620 | asnibbles[7] = high; |
1621 | } | |
1622 | else if (OP_KIND (this_try->opcode->how) == O_STM) | |
1623 | { | |
1624 | high = (operand[0].reg >> 8) & 0xf; | |
1625 | low = (operand[0].reg) & 0xf; | |
1626 | asnibbles[2] = high - low; | |
1627 | asnibbles[7] = low; | |
252b5132 RH |
1628 | } |
1629 | ||
1630 | for (i = 0; i < this_try->length; i++) | |
3048287a | 1631 | output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1]; |
252b5132 | 1632 | |
81f5558e | 1633 | /* Note if this is a mov.b or a bit manipulation instruction |
ca9a79a1 NC |
1634 | there is a special relaxation which only applies. */ |
1635 | if ( this_try->opcode->how == O (O_MOV, SB) | |
1636 | || this_try->opcode->how == O (O_BCLR, SB) | |
1637 | || this_try->opcode->how == O (O_BAND, SB) | |
1638 | || this_try->opcode->how == O (O_BIAND, SB) | |
1639 | || this_try->opcode->how == O (O_BILD, SB) | |
1640 | || this_try->opcode->how == O (O_BIOR, SB) | |
1641 | || this_try->opcode->how == O (O_BIST, SB) | |
1642 | || this_try->opcode->how == O (O_BIXOR, SB) | |
1643 | || this_try->opcode->how == O (O_BLD, SB) | |
1644 | || this_try->opcode->how == O (O_BNOT, SB) | |
1645 | || this_try->opcode->how == O (O_BOR, SB) | |
1646 | || this_try->opcode->how == O (O_BSET, SB) | |
1647 | || this_try->opcode->how == O (O_BST, SB) | |
1648 | || this_try->opcode->how == O (O_BTST, SB) | |
1649 | || this_try->opcode->how == O (O_BXOR, SB)) | |
252b5132 RH |
1650 | movb = 1; |
1651 | ||
70d6ecf3 | 1652 | /* Output any fixes. */ |
7ee7b84d | 1653 | for (i = 0; i < this_try->noperands; i++) |
252b5132 RH |
1654 | { |
1655 | int x = operand[i].mode; | |
7ee7b84d | 1656 | int x_mode = x & MODE; |
252b5132 | 1657 | |
7ee7b84d | 1658 | if (x_mode == IMM || x_mode == DISP) |
81f5558e NC |
1659 | { |
1660 | #ifndef OBJ_ELF | |
1661 | /* Remove MEMRELAX flag added in h8300.h on mov with | |
1662 | addressing mode "register indirect with displacement". */ | |
1663 | if (x_mode == DISP) | |
1664 | x &= ~MEMRELAX; | |
1665 | #endif | |
1666 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, | |
1667 | op_at[i] & 1, operand + i, (x & MEMRELAX) != 0, | |
1668 | this_try); | |
1669 | } | |
7ee7b84d MS |
1670 | else if (x_mode == ABS) |
1671 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, | |
1672 | op_at[i] & 1, operand + i, | |
bcb012d3 DD |
1673 | (x & MEMRELAX) ? movb + 1 : 0, |
1674 | this_try); | |
3048287a | 1675 | |
7ee7b84d | 1676 | else if (x_mode == PCREL) |
252b5132 | 1677 | { |
7ee7b84d | 1678 | int size16 = (x & SIZE) == L_16; |
252b5132 RH |
1679 | int size = size16 ? 2 : 1; |
1680 | int type = size16 ? R_PCRWORD : R_PCRBYTE; | |
36ed2fff | 1681 | fixS *fixP; |
252b5132 RH |
1682 | |
1683 | check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@"); | |
1684 | ||
1685 | if (operand[i].exp.X_add_number & 1) | |
3048287a NC |
1686 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1687 | (unsigned long) operand->exp.X_add_number); | |
36ed2fff JL |
1688 | #ifndef OBJ_ELF |
1689 | /* The COFF port has always been off by one, changing it | |
1690 | now would be an incompatible change, so we leave it as-is. | |
1691 | ||
1692 | We don't want to do this for ELF as we want to be | |
1693 | compatible with the proposed ELF format from Hitachi. */ | |
252b5132 | 1694 | operand[i].exp.X_add_number -= 1; |
36ed2fff | 1695 | #endif |
7ee7b84d MS |
1696 | if (size16) |
1697 | { | |
1698 | operand[i].exp.X_add_number = | |
1699 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
1700 | } | |
1701 | else | |
1702 | { | |
1703 | operand[i].exp.X_add_number = | |
1704 | ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
1705 | } | |
1706 | ||
1707 | /* For BRA/S. */ | |
1708 | if (! size16) | |
1709 | operand[i].exp.X_add_number |= output[op_at[i] / 2]; | |
252b5132 | 1710 | |
36ed2fff | 1711 | fixP = fix_new_exp (frag_now, |
7ee7b84d | 1712 | output - frag_now->fr_literal + op_at[i] / 2, |
36ed2fff JL |
1713 | size, |
1714 | &operand[i].exp, | |
1715 | 1, | |
1716 | type); | |
1717 | fixP->fx_signed = 1; | |
252b5132 | 1718 | } |
7ee7b84d | 1719 | else if (x_mode == MEMIND) |
252b5132 | 1720 | { |
252b5132 RH |
1721 | check_operand (operand + i, 0xff, "@@"); |
1722 | fix_new_exp (frag_now, | |
1723 | output - frag_now->fr_literal + 1, | |
1724 | 1, | |
1725 | &operand[i].exp, | |
1726 | 0, | |
1727 | R_MEM_INDIRECT); | |
1728 | } | |
7ee7b84d MS |
1729 | else if (x_mode == VECIND) |
1730 | { | |
1731 | check_operand (operand + i, 0x7f, "@@"); | |
1732 | /* FIXME: approximating the effect of "B31" here... | |
1733 | This is very hackish, and ought to be done a better way. */ | |
1734 | operand[i].exp.X_add_number |= 0x80; | |
1735 | fix_new_exp (frag_now, | |
1736 | output - frag_now->fr_literal + 1, | |
1737 | 1, | |
1738 | &operand[i].exp, | |
1739 | 0, | |
1740 | R_MEM_INDIRECT); | |
1741 | } | |
252b5132 RH |
1742 | else if (x & ABSJMP) |
1743 | { | |
3c1ba8a3 | 1744 | int where = 0; |
7ee7b84d | 1745 | bfd_reloc_code_real_type reloc_type = R_JMPL1; |
3c1ba8a3 JL |
1746 | |
1747 | #ifdef OBJ_ELF | |
1748 | /* To be compatible with the proposed H8 ELF format, we | |
1749 | want the relocation's offset to point to the first byte | |
1750 | that will be modified, not to the start of the instruction. */ | |
3739860c | 1751 | |
7ee7b84d MS |
1752 | if ((operand->mode & SIZE) == L_32) |
1753 | { | |
1754 | where = 2; | |
1755 | reloc_type = R_RELLONG; | |
1756 | } | |
1757 | else | |
1758 | where = 1; | |
3c1ba8a3 | 1759 | #endif |
de342d07 | 1760 | |
70d6ecf3 | 1761 | /* This jmp may be a jump or a branch. */ |
252b5132 | 1762 | |
3739860c L |
1763 | check_operand (operand + i, |
1764 | SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff, | |
7ee7b84d | 1765 | "@"); |
3048287a | 1766 | |
252b5132 | 1767 | if (operand[i].exp.X_add_number & 1) |
3048287a NC |
1768 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1769 | (unsigned long) operand->exp.X_add_number); | |
1770 | ||
252b5132 | 1771 | if (!Hmode) |
70d6ecf3 | 1772 | operand[i].exp.X_add_number = |
4132022d | 1773 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; |
252b5132 | 1774 | fix_new_exp (frag_now, |
3c1ba8a3 | 1775 | output - frag_now->fr_literal + where, |
252b5132 RH |
1776 | 4, |
1777 | &operand[i].exp, | |
1778 | 0, | |
7ee7b84d | 1779 | reloc_type); |
252b5132 RH |
1780 | } |
1781 | } | |
252b5132 RH |
1782 | } |
1783 | ||
70d6ecf3 AM |
1784 | /* Try to give an intelligent error message for common and simple to |
1785 | detect errors. */ | |
3048287a | 1786 | |
252b5132 | 1787 | static void |
b54a3392 KH |
1788 | clever_message (const struct h8_instruction *instruction, |
1789 | struct h8_op *operand) | |
252b5132 | 1790 | { |
70d6ecf3 | 1791 | /* Find out if there was more than one possible opcode. */ |
252b5132 | 1792 | |
a720f7bc | 1793 | if ((instruction + 1)->idx != instruction->idx) |
252b5132 | 1794 | { |
3048287a | 1795 | int argn; |
252b5132 | 1796 | |
70d6ecf3 AM |
1797 | /* Only one opcode of this flavour, try to guess which operand |
1798 | didn't match. */ | |
a720f7bc | 1799 | for (argn = 0; argn < instruction->noperands; argn++) |
252b5132 | 1800 | { |
a720f7bc | 1801 | switch (instruction->opcode->args.nib[argn]) |
252b5132 RH |
1802 | { |
1803 | case RD16: | |
1804 | if (operand[argn].mode != RD16) | |
1805 | { | |
1806 | as_bad (_("destination operand must be 16 bit register")); | |
1807 | return; | |
1808 | ||
1809 | } | |
1810 | break; | |
1811 | ||
1812 | case RS8: | |
252b5132 RH |
1813 | if (operand[argn].mode != RS8) |
1814 | { | |
1815 | as_bad (_("source operand must be 8 bit register")); | |
1816 | return; | |
1817 | } | |
1818 | break; | |
1819 | ||
1820 | case ABS16DST: | |
1821 | if (operand[argn].mode != ABS16DST) | |
1822 | { | |
1823 | as_bad (_("destination operand must be 16bit absolute address")); | |
1824 | return; | |
1825 | } | |
1826 | break; | |
1827 | case RD8: | |
1828 | if (operand[argn].mode != RD8) | |
1829 | { | |
1830 | as_bad (_("destination operand must be 8 bit register")); | |
1831 | return; | |
1832 | } | |
1833 | break; | |
1834 | ||
252b5132 RH |
1835 | case ABS16SRC: |
1836 | if (operand[argn].mode != ABS16SRC) | |
1837 | { | |
1838 | as_bad (_("source operand must be 16bit absolute address")); | |
1839 | return; | |
1840 | } | |
1841 | break; | |
1842 | ||
1843 | } | |
1844 | } | |
1845 | } | |
1846 | as_bad (_("invalid operands")); | |
1847 | } | |
1848 | ||
d4ea8842 | 1849 | |
1b680e4f RS |
1850 | /* If OPERAND is part of an address, adjust its size and value given |
1851 | that it addresses SIZE bytes. | |
d4ea8842 | 1852 | |
1b680e4f RS |
1853 | This function decides how big non-immediate constants are when no |
1854 | size was explicitly given. It also scales down the assembly-level | |
d4ea8842 MS |
1855 | displacement in an @(d:2,ERn) operand. */ |
1856 | ||
1857 | static void | |
b54a3392 | 1858 | fix_operand_size (struct h8_op *operand, int size) |
d4ea8842 | 1859 | { |
1b680e4f | 1860 | if (SXmode && (operand->mode & MODE) == DISP) |
d4ea8842 MS |
1861 | { |
1862 | /* If the user didn't specify an operand width, see if we | |
1863 | can use @(d:2,ERn). */ | |
1b680e4f RS |
1864 | if ((operand->mode & SIZE) == 0 |
1865 | && operand->exp.X_add_symbol == 0 | |
1866 | && operand->exp.X_op_symbol == 0 | |
d4ea8842 MS |
1867 | && (operand->exp.X_add_number == size |
1868 | || operand->exp.X_add_number == size * 2 | |
1869 | || operand->exp.X_add_number == size * 3)) | |
1870 | operand->mode |= L_2; | |
1871 | ||
1872 | /* Scale down the displacement in an @(d:2,ERn) operand. | |
1873 | X_add_number then contains the desired field value. */ | |
1874 | if ((operand->mode & SIZE) == L_2) | |
1875 | { | |
1876 | if (operand->exp.X_add_number % size != 0) | |
1877 | as_warn (_("operand/size mis-match")); | |
1878 | operand->exp.X_add_number /= size; | |
1879 | } | |
1880 | } | |
1881 | ||
d4ea8842 MS |
1882 | if ((operand->mode & SIZE) == 0) |
1883 | switch (operand->mode & MODE) | |
1884 | { | |
1885 | case DISP: | |
1886 | case INDEXB: | |
1887 | case INDEXW: | |
1888 | case INDEXL: | |
1889 | case ABS: | |
1b680e4f RS |
1890 | /* Pick a 24-bit address unless we know that a 16-bit address |
1891 | is safe. get_specific() will relax L_24 into L_32 where | |
1892 | necessary. */ | |
1893 | if (Hmode | |
3739860c | 1894 | && !Nmode |
35a35807 AM |
1895 | && ((((addressT) operand->exp.X_add_number + 0x8000) |
1896 | & 0xffffffff) > 0xffff | |
1b680e4f RS |
1897 | || operand->exp.X_add_symbol != 0 |
1898 | || operand->exp.X_op_symbol != 0)) | |
1899 | operand->mode |= L_24; | |
1900 | else | |
1901 | operand->mode |= L_16; | |
1902 | break; | |
1903 | ||
1904 | case PCREL: | |
35a35807 AM |
1905 | if ((((addressT) operand->exp.X_add_number + 0x80) |
1906 | & 0xffffffff) <= 0xff) | |
cc189afc DD |
1907 | { |
1908 | if (operand->exp.X_add_symbol != NULL) | |
1909 | operand->mode |= bsize; | |
1910 | else | |
1911 | operand->mode |= L_8; | |
1912 | } | |
1b680e4f RS |
1913 | else |
1914 | operand->mode |= L_16; | |
d4ea8842 MS |
1915 | break; |
1916 | } | |
1917 | } | |
1918 | ||
1919 | ||
70d6ecf3 AM |
1920 | /* This is the guts of the machine-dependent assembler. STR points to |
1921 | a machine dependent instruction. This function is supposed to emit | |
1922 | the frags/bytes it assembles. */ | |
3048287a | 1923 | |
252b5132 | 1924 | void |
b54a3392 | 1925 | md_assemble (char *str) |
252b5132 RH |
1926 | { |
1927 | char *op_start; | |
1928 | char *op_end; | |
7ee7b84d | 1929 | struct h8_op operand[3]; |
a720f7bc KD |
1930 | const struct h8_instruction *instruction; |
1931 | const struct h8_instruction *prev_instruction; | |
252b5132 RH |
1932 | |
1933 | char *dot = 0; | |
0c0b9be0 | 1934 | char *slash = 0; |
252b5132 | 1935 | char c; |
7ee7b84d | 1936 | int size, i; |
252b5132 | 1937 | |
70d6ecf3 | 1938 | /* Drop leading whitespace. */ |
252b5132 RH |
1939 | while (*str == ' ') |
1940 | str++; | |
1941 | ||
70d6ecf3 | 1942 | /* Find the op code end. */ |
252b5132 RH |
1943 | for (op_start = op_end = str; |
1944 | *op_end != 0 && *op_end != ' '; | |
1945 | op_end++) | |
1946 | { | |
1947 | if (*op_end == '.') | |
1948 | { | |
1949 | dot = op_end + 1; | |
1950 | *op_end = 0; | |
1951 | op_end += 2; | |
1952 | break; | |
1953 | } | |
0c0b9be0 AO |
1954 | else if (*op_end == '/' && ! slash) |
1955 | slash = op_end; | |
252b5132 RH |
1956 | } |
1957 | ||
252b5132 RH |
1958 | if (op_end == op_start) |
1959 | { | |
1960 | as_bad (_("can't find opcode ")); | |
1961 | } | |
1962 | c = *op_end; | |
1963 | ||
1964 | *op_end = 0; | |
1965 | ||
0c0b9be0 AO |
1966 | /* The assembler stops scanning the opcode at slashes, so it fails |
1967 | to make characters following them lower case. Fix them. */ | |
1968 | if (slash) | |
1969 | while (*++slash) | |
1970 | *slash = TOLOWER (*slash); | |
1971 | ||
a720f7bc KD |
1972 | instruction = (const struct h8_instruction *) |
1973 | hash_find (opcode_hash_control, op_start); | |
252b5132 | 1974 | |
a720f7bc | 1975 | if (instruction == NULL) |
252b5132 RH |
1976 | { |
1977 | as_bad (_("unknown opcode")); | |
1978 | return; | |
1979 | } | |
1980 | ||
70d6ecf3 | 1981 | /* We used to set input_line_pointer to the result of get_operands, |
252b5132 RH |
1982 | but that is wrong. Our caller assumes we don't change it. */ |
1983 | ||
7ee7b84d MS |
1984 | operand[0].mode = 0; |
1985 | operand[1].mode = 0; | |
1986 | operand[2].mode = 0; | |
1987 | ||
1988 | if (OP_KIND (instruction->opcode->how) == O_MOVAB | |
1989 | || OP_KIND (instruction->opcode->how) == O_MOVAW | |
1990 | || OP_KIND (instruction->opcode->how) == O_MOVAL) | |
1991 | get_mova_operands (op_end, operand); | |
1992 | else if (OP_KIND (instruction->opcode->how) == O_RTEL | |
1993 | || OP_KIND (instruction->opcode->how) == O_RTSL) | |
1994 | get_rtsl_operands (op_end, operand); | |
1995 | else | |
1996 | get_operands (instruction->noperands, op_end, operand); | |
1997 | ||
252b5132 | 1998 | *op_end = c; |
a720f7bc | 1999 | prev_instruction = instruction; |
252b5132 | 2000 | |
4892e510 NC |
2001 | /* Now we have operands from instruction. |
2002 | Let's check them out for ldm and stm. */ | |
2003 | if (OP_KIND (instruction->opcode->how) == O_LDM) | |
2004 | { | |
2005 | /* The first operand must be @er7+, and the | |
2006 | second operand must be a register pair. */ | |
2007 | if ((operand[0].mode != RSINC) | |
2008 | || (operand[0].reg != 7) | |
2009 | || ((operand[1].reg & 0x80000000) == 0)) | |
2010 | as_bad (_("invalid operand in ldm")); | |
2011 | } | |
2012 | else if (OP_KIND (instruction->opcode->how) == O_STM) | |
2013 | { | |
2014 | /* The first operand must be a register pair, | |
2015 | and the second operand must be @-er7. */ | |
2016 | if (((operand[0].reg & 0x80000000) == 0) | |
2017 | || (operand[1].mode != RDDEC) | |
2018 | || (operand[1].reg != 7)) | |
2019 | as_bad (_("invalid operand in stm")); | |
2020 | } | |
2021 | ||
252b5132 RH |
2022 | size = SN; |
2023 | if (dot) | |
2024 | { | |
0c0b9be0 | 2025 | switch (TOLOWER (*dot)) |
252b5132 RH |
2026 | { |
2027 | case 'b': | |
2028 | size = SB; | |
2029 | break; | |
2030 | ||
2031 | case 'w': | |
2032 | size = SW; | |
2033 | break; | |
2034 | ||
2035 | case 'l': | |
2036 | size = SL; | |
2037 | break; | |
2038 | } | |
2039 | } | |
7ee7b84d MS |
2040 | if (OP_KIND (instruction->opcode->how) == O_MOVAB || |
2041 | OP_KIND (instruction->opcode->how) == O_MOVAW || | |
2042 | OP_KIND (instruction->opcode->how) == O_MOVAL) | |
252b5132 | 2043 | { |
d4ea8842 MS |
2044 | switch (operand[0].mode & MODE) |
2045 | { | |
7ee7b84d MS |
2046 | case INDEXB: |
2047 | default: | |
d4ea8842 | 2048 | fix_operand_size (&operand[1], 1); |
7ee7b84d MS |
2049 | break; |
2050 | case INDEXW: | |
d4ea8842 | 2051 | fix_operand_size (&operand[1], 2); |
7ee7b84d MS |
2052 | break; |
2053 | case INDEXL: | |
d4ea8842 | 2054 | fix_operand_size (&operand[1], 4); |
7ee7b84d | 2055 | break; |
252b5132 RH |
2056 | } |
2057 | } | |
7ee7b84d MS |
2058 | else |
2059 | { | |
d4ea8842 MS |
2060 | for (i = 0; i < 3 && operand[i].mode != 0; i++) |
2061 | switch (size) | |
2062 | { | |
7ee7b84d MS |
2063 | case SN: |
2064 | case SB: | |
2065 | default: | |
d4ea8842 | 2066 | fix_operand_size (&operand[i], 1); |
7ee7b84d MS |
2067 | break; |
2068 | case SW: | |
d4ea8842 | 2069 | fix_operand_size (&operand[i], 2); |
7ee7b84d MS |
2070 | break; |
2071 | case SL: | |
d4ea8842 | 2072 | fix_operand_size (&operand[i], 4); |
7ee7b84d MS |
2073 | break; |
2074 | } | |
2075 | } | |
252b5132 | 2076 | |
d4ea8842 MS |
2077 | instruction = get_specific (instruction, operand, size); |
2078 | ||
2079 | if (instruction == 0) | |
2080 | { | |
2081 | /* Couldn't find an opcode which matched the operands. */ | |
2082 | char *where = frag_more (2); | |
2083 | ||
2084 | where[0] = 0x0; | |
2085 | where[1] = 0x0; | |
2086 | clever_message (prev_instruction, operand); | |
2087 | ||
2088 | return; | |
2089 | } | |
2090 | ||
a720f7bc | 2091 | build_bytes (instruction, operand); |
2c8714f2 | 2092 | |
2c8714f2 | 2093 | dwarf2_emit_insn (instruction->length); |
252b5132 RH |
2094 | } |
2095 | ||
2096 | symbolS * | |
b54a3392 | 2097 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
2098 | { |
2099 | return 0; | |
2100 | } | |
2101 | ||
499ac353 | 2102 | /* Various routines to kill one day. */ |
bc0d738a | 2103 | |
6d4af3c2 | 2104 | const char * |
b54a3392 | 2105 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 2106 | { |
499ac353 | 2107 | return ieee_md_atof (type, litP, sizeP, TRUE); |
252b5132 RH |
2108 | } |
2109 | \f | |
6fd4f6cc | 2110 | #define OPTION_H_TICK_HEX (OPTION_MD_BASE) |
5518c738 | 2111 | #define OPTION_MACH (OPTION_MD_BASE+1) |
6fd4f6cc | 2112 | |
5a38dc70 | 2113 | const char *md_shortopts = ""; |
5518c738 YS |
2114 | struct option md_longopts[] = |
2115 | { | |
6fd4f6cc | 2116 | { "h-tick-hex", no_argument, NULL, OPTION_H_TICK_HEX }, |
5518c738 | 2117 | { "mach", required_argument, NULL, OPTION_MACH }, |
252b5132 RH |
2118 | {NULL, no_argument, NULL, 0} |
2119 | }; | |
70d6ecf3 AM |
2120 | |
2121 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 | 2122 | |
5518c738 YS |
2123 | struct mach_func |
2124 | { | |
2125 | const char *name; | |
2126 | void (*func) (void); | |
2127 | }; | |
2128 | ||
2129 | static void | |
2130 | mach_h8300h (void) | |
2131 | { | |
2132 | Hmode = 1; | |
2133 | Smode = 0; | |
2134 | Nmode = 0; | |
2135 | SXmode = 0; | |
2136 | default_mach = bfd_mach_h8300h; | |
2137 | } | |
2138 | ||
2139 | static void | |
2140 | mach_h8300hn (void) | |
2141 | { | |
2142 | Hmode = 1; | |
2143 | Smode = 0; | |
2144 | Nmode = 1; | |
2145 | SXmode = 0; | |
2146 | default_mach = bfd_mach_h8300hn; | |
2147 | } | |
2148 | ||
2149 | static void | |
2150 | mach_h8300s (void) | |
2151 | { | |
2152 | Hmode = 1; | |
2153 | Smode = 1; | |
2154 | Nmode = 0; | |
2155 | SXmode = 0; | |
2156 | default_mach = bfd_mach_h8300s; | |
2157 | } | |
2158 | ||
2159 | static void | |
2160 | mach_h8300sn (void) | |
2161 | { | |
2162 | Hmode = 1; | |
2163 | Smode = 1; | |
2164 | Nmode = 1; | |
2165 | SXmode = 0; | |
2166 | default_mach = bfd_mach_h8300sn; | |
2167 | } | |
2168 | ||
2169 | static void | |
2170 | mach_h8300sx (void) | |
2171 | { | |
2172 | Hmode = 1; | |
2173 | Smode = 1; | |
2174 | Nmode = 0; | |
2175 | SXmode = 1; | |
2176 | default_mach = bfd_mach_h8300sx; | |
2177 | } | |
2178 | ||
2179 | static void | |
2180 | mach_h8300sxn (void) | |
2181 | { | |
2182 | Hmode = 1; | |
2183 | Smode = 1; | |
2184 | Nmode = 1; | |
2185 | SXmode = 1; | |
2186 | default_mach = bfd_mach_h8300sxn; | |
2187 | } | |
2188 | ||
2189 | const struct mach_func mach_table[] = | |
2190 | { | |
2191 | {"h8300h", mach_h8300h}, | |
2192 | {"h8300hn", mach_h8300hn}, | |
2193 | {"h8300s", mach_h8300s}, | |
2194 | {"h8300sn", mach_h8300sn}, | |
2195 | {"h8300sx", mach_h8300sx}, | |
2196 | {"h8300sxn", mach_h8300sxn} | |
2197 | }; | |
2198 | ||
252b5132 | 2199 | int |
17b9d67d | 2200 | md_parse_option (int c ATTRIBUTE_UNUSED, const char *arg ATTRIBUTE_UNUSED) |
252b5132 | 2201 | { |
5518c738 | 2202 | unsigned int i; |
6fd4f6cc DD |
2203 | switch (c) |
2204 | { | |
2205 | case OPTION_H_TICK_HEX: | |
2206 | enable_h_tick_hex = 1; | |
2207 | break; | |
5518c738 YS |
2208 | case OPTION_MACH: |
2209 | for (i = 0; i < sizeof(mach_table) / sizeof(struct mach_func); i++) | |
2210 | { | |
2211 | if (strcasecmp (arg, mach_table[i].name) == 0) | |
2212 | { | |
2213 | mach_table[i].func(); | |
2214 | break; | |
2215 | } | |
2216 | } | |
2217 | if (i >= sizeof(mach_table) / sizeof(struct mach_func)) | |
2218 | as_bad (_("Invalid argument to --mach option: %s"), arg); | |
2219 | break; | |
6fd4f6cc DD |
2220 | default: |
2221 | return 0; | |
2222 | } | |
2223 | return 1; | |
252b5132 RH |
2224 | } |
2225 | ||
2226 | void | |
5518c738 | 2227 | md_show_usage (FILE *stream) |
252b5132 | 2228 | { |
5518c738 YS |
2229 | fprintf (stream, _(" H8300-specific assembler options:\n")); |
2230 | fprintf (stream, _("\ | |
2231 | -mach=<name> Set the H8300 machine type to one of:\n\ | |
2232 | h8300h, h8300hn, h8300s, h8300sn, h8300sx, h8300sxn\n")); | |
2233 | fprintf (stream, _("\ | |
2234 | -h-tick-hex Support H'00 style hex constants\n")); | |
252b5132 RH |
2235 | } |
2236 | \f | |
b54a3392 | 2237 | void tc_aout_fix_to_chars (void); |
3048287a | 2238 | |
252b5132 | 2239 | void |
b54a3392 | 2240 | tc_aout_fix_to_chars (void) |
252b5132 RH |
2241 | { |
2242 | printf (_("call to tc_aout_fix_to_chars \n")); | |
2243 | abort (); | |
2244 | } | |
2245 | ||
2246 | void | |
7be1c489 | 2247 | md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, |
b54a3392 KH |
2248 | segT seg ATTRIBUTE_UNUSED, |
2249 | fragS *fragP ATTRIBUTE_UNUSED) | |
252b5132 RH |
2250 | { |
2251 | printf (_("call to md_convert_frag \n")); | |
2252 | abort (); | |
2253 | } | |
2254 | ||
3c1ba8a3 | 2255 | valueT |
b54a3392 | 2256 | md_section_align (segT segment, valueT size) |
3c1ba8a3 JL |
2257 | { |
2258 | int align = bfd_get_section_alignment (stdoutput, segment); | |
239c0f4c | 2259 | return ((size + (1 << align) - 1) & (-1U << align)); |
3c1ba8a3 | 2260 | } |
252b5132 RH |
2261 | |
2262 | void | |
55cf6793 | 2263 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 RH |
2264 | { |
2265 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
a161fe53 | 2266 | long val = *valP; |
252b5132 RH |
2267 | |
2268 | switch (fixP->fx_size) | |
2269 | { | |
2270 | case 1: | |
2271 | *buf++ = val; | |
2272 | break; | |
2273 | case 2: | |
2274 | *buf++ = (val >> 8); | |
2275 | *buf++ = val; | |
2276 | break; | |
2277 | case 4: | |
2278 | *buf++ = (val >> 24); | |
2279 | *buf++ = (val >> 16); | |
2280 | *buf++ = (val >> 8); | |
2281 | *buf++ = val; | |
2282 | break; | |
550c1888 NC |
2283 | case 8: |
2284 | /* This can arise when the .quad or .8byte pseudo-ops are used. | |
2285 | Returning here (without setting fx_done) will cause the code | |
2286 | to attempt to generate a reloc which will then fail with the | |
2287 | slightly more helpful error message: "Cannot represent | |
2288 | relocation type BFD_RELOC_64". */ | |
2289 | return; | |
252b5132 RH |
2290 | default: |
2291 | abort (); | |
2292 | } | |
94f592af NC |
2293 | |
2294 | if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) | |
2295 | fixP->fx_done = 1; | |
252b5132 RH |
2296 | } |
2297 | ||
2298 | int | |
c85dd50d NC |
2299 | md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, |
2300 | segT segment_type ATTRIBUTE_UNUSED) | |
252b5132 | 2301 | { |
c85dd50d | 2302 | printf (_("call to md_estimate_size_before_relax \n")); |
252b5132 RH |
2303 | abort (); |
2304 | } | |
2305 | ||
70d6ecf3 | 2306 | /* Put number into target byte order. */ |
252b5132 | 2307 | void |
b54a3392 | 2308 | md_number_to_chars (char *ptr, valueT use, int nbytes) |
252b5132 RH |
2309 | { |
2310 | number_to_chars_bigendian (ptr, use, nbytes); | |
2311 | } | |
70d6ecf3 | 2312 | |
252b5132 | 2313 | long |
52b010e4 | 2314 | md_pcrel_from (fixS *fixp) |
252b5132 | 2315 | { |
52b010e4 NC |
2316 | as_bad_where (fixp->fx_file, fixp->fx_line, |
2317 | _("Unexpected reference to a symbol in a non-code section")); | |
2318 | return 0; | |
252b5132 RH |
2319 | } |
2320 | ||
f333765f | 2321 | arelent * |
b54a3392 | 2322 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
f333765f JL |
2323 | { |
2324 | arelent *rel; | |
2325 | bfd_reloc_code_real_type r_type; | |
2326 | ||
de342d07 JL |
2327 | if (fixp->fx_addsy && fixp->fx_subsy) |
2328 | { | |
2329 | if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy)) | |
2330 | || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section) | |
2331 | { | |
2332 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
c85dd50d | 2333 | _("Difference of symbols in different sections is not supported")); |
de342d07 JL |
2334 | return NULL; |
2335 | } | |
2336 | } | |
2337 | ||
325801bd TS |
2338 | rel = XNEW (arelent); |
2339 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
f333765f JL |
2340 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
2341 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
2342 | rel->addend = fixp->fx_offset; | |
2343 | ||
2344 | r_type = fixp->fx_r_type; | |
2345 | ||
2346 | #define DEBUG 0 | |
2347 | #if DEBUG | |
2348 | fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type)); | |
c85dd50d | 2349 | fflush (stderr); |
f333765f JL |
2350 | #endif |
2351 | rel->howto = bfd_reloc_type_lookup (stdoutput, r_type); | |
2352 | if (rel->howto == NULL) | |
2353 | { | |
2354 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
2355 | _("Cannot represent relocation type %s"), | |
2356 | bfd_get_reloc_code_name (r_type)); | |
2357 | return NULL; | |
2358 | } | |
2359 | ||
2360 | return rel; | |
2361 | } |