Commit | Line | Data |
---|---|---|
c2dcd04e | 1 | /* tc-h8300.c -- Assemble code for the Renesas H8/300 |
4b95cf5c | 2 | Copyright (C) 1991-2014 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
bc0d738a | 21 | /* Written By Steve Chamberlain <sac@cygnus.com>. */ |
252b5132 | 22 | |
252b5132 RH |
23 | #include "as.h" |
24 | #include "subsegs.h" | |
2c8714f2 | 25 | #include "dwarf2dbg.h" |
2c8714f2 | 26 | |
252b5132 RH |
27 | #define DEFINE_TABLE |
28 | #define h8_opcodes ops | |
29 | #include "opcode/h8300.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
7e0de7bf JL |
32 | #ifdef OBJ_ELF |
33 | #include "elf/h8.h" | |
7e0de7bf JL |
34 | #endif |
35 | ||
63a0b638 | 36 | const char comment_chars[] = ";"; |
252b5132 | 37 | const char line_comment_chars[] = "#"; |
63a0b638 | 38 | const char line_separator_chars[] = ""; |
252b5132 | 39 | |
600e9c99 KH |
40 | static void sbranch (int); |
41 | static void h8300hmode (int); | |
42 | static void h8300smode (int); | |
43 | static void h8300hnmode (int); | |
44 | static void h8300snmode (int); | |
45 | static void h8300sxmode (int); | |
46 | static void h8300sxnmode (int); | |
b54a3392 | 47 | static void pint (int); |
252b5132 | 48 | |
66faad26 KH |
49 | int Hmode; |
50 | int Smode; | |
51 | int Nmode; | |
52 | int SXmode; | |
3048287a | 53 | |
d4e2de6b | 54 | #define PSIZE (Hmode && !Nmode ? L_32 : L_16) |
3048287a | 55 | |
600e9c99 | 56 | static int bsize = L_8; /* Default branch displacement. */ |
252b5132 | 57 | |
a720f7bc KD |
58 | struct h8_instruction |
59 | { | |
60 | int length; | |
61 | int noperands; | |
62 | int idx; | |
63 | int size; | |
64 | const struct h8_opcode *opcode; | |
65 | }; | |
66 | ||
600e9c99 | 67 | static struct h8_instruction *h8_instructions; |
a720f7bc | 68 | |
600e9c99 | 69 | static void |
b54a3392 | 70 | h8300hmode (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
71 | { |
72 | Hmode = 1; | |
73 | Smode = 0; | |
83e20b45 JL |
74 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h)) |
75 | as_warn (_("could not set architecture and machine")); | |
252b5132 RH |
76 | } |
77 | ||
600e9c99 | 78 | static void |
b54a3392 | 79 | h8300smode (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
80 | { |
81 | Smode = 1; | |
82 | Hmode = 1; | |
83e20b45 JL |
83 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s)) |
84 | as_warn (_("could not set architecture and machine")); | |
252b5132 | 85 | } |
70d6ecf3 | 86 | |
600e9c99 | 87 | static void |
b54a3392 | 88 | h8300hnmode (int arg ATTRIBUTE_UNUSED) |
8d9cd6b1 NC |
89 | { |
90 | Hmode = 1; | |
91 | Smode = 0; | |
92 | Nmode = 1; | |
8d9cd6b1 NC |
93 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn)) |
94 | as_warn (_("could not set architecture and machine")); | |
8d9cd6b1 NC |
95 | } |
96 | ||
600e9c99 | 97 | static void |
b54a3392 | 98 | h8300snmode (int arg ATTRIBUTE_UNUSED) |
8d9cd6b1 NC |
99 | { |
100 | Smode = 1; | |
101 | Hmode = 1; | |
102 | Nmode = 1; | |
8d9cd6b1 NC |
103 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn)) |
104 | as_warn (_("could not set architecture and machine")); | |
8d9cd6b1 NC |
105 | } |
106 | ||
600e9c99 | 107 | static void |
b54a3392 | 108 | h8300sxmode (int arg ATTRIBUTE_UNUSED) |
7ee7b84d MS |
109 | { |
110 | Smode = 1; | |
111 | Hmode = 1; | |
112 | SXmode = 1; | |
7ee7b84d MS |
113 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx)) |
114 | as_warn (_("could not set architecture and machine")); | |
7ee7b84d MS |
115 | } |
116 | ||
600e9c99 | 117 | static void |
b54a3392 | 118 | h8300sxnmode (int arg ATTRIBUTE_UNUSED) |
f4984206 RS |
119 | { |
120 | Smode = 1; | |
121 | Hmode = 1; | |
122 | SXmode = 1; | |
123 | Nmode = 1; | |
f4984206 RS |
124 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn)) |
125 | as_warn (_("could not set architecture and machine")); | |
f4984206 RS |
126 | } |
127 | ||
600e9c99 | 128 | static void |
b54a3392 | 129 | sbranch (int size) |
252b5132 RH |
130 | { |
131 | bsize = size; | |
132 | } | |
133 | ||
70d6ecf3 | 134 | static void |
b54a3392 | 135 | pint (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
136 | { |
137 | cons (Hmode ? 4 : 2); | |
138 | } | |
139 | ||
52b010e4 NC |
140 | /* Like obj_elf_section, but issues a warning for new |
141 | sections which do not have an attribute specification. */ | |
142 | ||
143 | static void | |
144 | h8300_elf_section (int push) | |
145 | { | |
146 | static const char * known_data_sections [] = { ".rodata", ".tdata", ".tbss" }; | |
9c8b3bfe | 147 | static const char * known_data_prefixes [] = { ".debug", ".zdebug", ".gnu.warning" }; |
52b010e4 NC |
148 | char * saved_ilp = input_line_pointer; |
149 | char * name; | |
150 | ||
151 | name = obj_elf_section_name (); | |
152 | if (name == NULL) | |
153 | return; | |
154 | ||
155 | if (* input_line_pointer != ',' | |
156 | && bfd_get_section_by_name (stdoutput, name) == NULL) | |
157 | { | |
158 | signed int i; | |
159 | ||
160 | /* Ignore this warning for well known data sections. */ | |
161 | for (i = ARRAY_SIZE (known_data_sections); i--;) | |
162 | if (strcmp (name, known_data_sections[i]) == 0) | |
163 | break; | |
164 | ||
165 | if (i < 0) | |
166 | for (i = ARRAY_SIZE (known_data_prefixes); i--;) | |
167 | if (strncmp (name, known_data_prefixes[i], | |
168 | strlen (known_data_prefixes[i])) == 0) | |
169 | break; | |
170 | ||
171 | if (i < 0) | |
172 | as_warn (_("new section '%s' defined without attributes - this might cause problems"), name); | |
173 | } | |
174 | ||
175 | /* FIXME: We ought to free the memory allocated by obj_elf_section_name() | |
176 | for 'name', but we do not know if it was taken from the obstack, via | |
177 | demand_copy_C_string(), or xmalloc()ed. */ | |
178 | input_line_pointer = saved_ilp; | |
179 | obj_elf_section (push); | |
180 | } | |
181 | ||
3048287a NC |
182 | /* This table describes all the machine specific pseudo-ops the assembler |
183 | has to support. The fields are: | |
184 | pseudo-op name without dot | |
185 | function to call to execute this pseudo-op | |
186 | Integer arg to pass to the function. */ | |
187 | ||
252b5132 RH |
188 | const pseudo_typeS md_pseudo_table[] = |
189 | { | |
7ee7b84d | 190 | {"h8300h", h8300hmode, 0}, |
8d9cd6b1 | 191 | {"h8300hn", h8300hnmode, 0}, |
7ee7b84d | 192 | {"h8300s", h8300smode, 0}, |
8d9cd6b1 | 193 | {"h8300sn", h8300snmode, 0}, |
7ee7b84d | 194 | {"h8300sx", h8300sxmode, 0}, |
f4984206 | 195 | {"h8300sxn", h8300sxnmode, 0}, |
252b5132 RH |
196 | {"sbranch", sbranch, L_8}, |
197 | {"lbranch", sbranch, L_16}, | |
198 | ||
199 | {"int", pint, 0}, | |
200 | {"data.b", cons, 1}, | |
201 | {"data.w", cons, 2}, | |
202 | {"data.l", cons, 4}, | |
203 | {"form", listing_psize, 0}, | |
204 | {"heading", listing_title, 0}, | |
7ee7b84d MS |
205 | {"import", s_ignore, 0}, |
206 | {"page", listing_eject, 0}, | |
252b5132 | 207 | {"program", s_ignore, 0}, |
52b010e4 NC |
208 | |
209 | #ifdef OBJ_ELF | |
210 | {"section", h8300_elf_section, 0}, | |
211 | {"section.s", h8300_elf_section, 0}, | |
212 | {"sect", h8300_elf_section, 0}, | |
213 | {"sect.s", h8300_elf_section, 0}, | |
214 | #endif | |
215 | ||
252b5132 RH |
216 | {0, 0, 0} |
217 | }; | |
218 | ||
252b5132 RH |
219 | const char EXP_CHARS[] = "eE"; |
220 | ||
3048287a NC |
221 | /* Chars that mean this number is a floating point constant |
222 | As in 0f12.456 | |
223 | or 0d1.2345e12. */ | |
252b5132 RH |
224 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
225 | ||
3048287a | 226 | static struct hash_control *opcode_hash_control; /* Opcode mnemonics. */ |
252b5132 | 227 | |
70d6ecf3 AM |
228 | /* This function is called once, at assembler startup time. This |
229 | should set up all the tables, etc. that the MD part of the assembler | |
230 | needs. */ | |
3048287a | 231 | |
252b5132 | 232 | void |
b54a3392 | 233 | md_begin (void) |
252b5132 | 234 | { |
a720f7bc | 235 | unsigned int nopcodes; |
7ee7b84d | 236 | struct h8_opcode *p, *p1; |
a720f7bc | 237 | struct h8_instruction *pi; |
252b5132 RH |
238 | char prev_buffer[100]; |
239 | int idx = 0; | |
240 | ||
83e20b45 JL |
241 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300)) |
242 | as_warn (_("could not set architecture and machine")); | |
83e20b45 | 243 | |
252b5132 RH |
244 | opcode_hash_control = hash_new (); |
245 | prev_buffer[0] = 0; | |
246 | ||
a720f7bc KD |
247 | nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); |
248 | ||
249 | h8_instructions = (struct h8_instruction *) | |
250 | xmalloc (nopcodes * sizeof (struct h8_instruction)); | |
251 | ||
7ee7b84d MS |
252 | pi = h8_instructions; |
253 | p1 = h8_opcodes; | |
254 | /* We do a minimum amount of sorting on the opcode table; this is to | |
255 | make it easy to describe the mova instructions without unnecessary | |
256 | code duplication. | |
257 | Sorting only takes place inside blocks of instructions of the form | |
258 | X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */ | |
259 | while (p1) | |
252b5132 | 260 | { |
7ee7b84d MS |
261 | struct h8_opcode *first_skipped = 0; |
262 | int len, cmplen = 0; | |
263 | char *src = p1->name; | |
264 | char *dst, *buffer; | |
252b5132 | 265 | |
7ee7b84d MS |
266 | if (p1->name == 0) |
267 | break; | |
268 | /* Strip off any . part when inserting the opcode and only enter | |
269 | unique codes into the hash table. */ | |
270 | dst = buffer = malloc (strlen (src) + 1); | |
252b5132 RH |
271 | while (*src) |
272 | { | |
273 | if (*src == '.') | |
274 | { | |
275 | src++; | |
252b5132 RH |
276 | break; |
277 | } | |
7ee7b84d MS |
278 | if (*src == '/') |
279 | cmplen = src - p1->name + 1; | |
252b5132 RH |
280 | *dst++ = *src++; |
281 | } | |
7ee7b84d MS |
282 | *dst = 0; |
283 | len = dst - buffer; | |
284 | if (cmplen == 0) | |
285 | cmplen = len; | |
286 | hash_insert (opcode_hash_control, buffer, (char *) pi); | |
287 | strcpy (prev_buffer, buffer); | |
288 | idx++; | |
289 | ||
290 | for (p = p1; p->name; p++) | |
252b5132 | 291 | { |
7ee7b84d MS |
292 | /* A negative TIME is used to indicate that we've added this opcode |
293 | already. */ | |
294 | if (p->time == -1) | |
295 | continue; | |
296 | if (strncmp (p->name, buffer, cmplen) != 0 | |
297 | || (p->name[cmplen] != '\0' && p->name[cmplen] != '.' | |
298 | && p->name[cmplen - 1] != '/')) | |
299 | { | |
300 | if (first_skipped == 0) | |
301 | first_skipped = p; | |
302 | break; | |
303 | } | |
304 | if (strncmp (p->name, buffer, len) != 0) | |
305 | { | |
306 | if (first_skipped == 0) | |
307 | first_skipped = p; | |
308 | continue; | |
309 | } | |
310 | ||
311 | p->time = -1; | |
312 | pi->size = p->name[len] == '.' ? p->name[len + 1] : 0; | |
313 | pi->idx = idx; | |
252b5132 | 314 | |
7ee7b84d MS |
315 | /* Find the number of operands. */ |
316 | pi->noperands = 0; | |
317 | while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E) | |
318 | pi->noperands++; | |
70d6ecf3 | 319 | |
7ee7b84d MS |
320 | /* Find the length of the opcode in bytes. */ |
321 | pi->length = 0; | |
322 | while (p->data.nib[pi->length * 2] != (op_type) E) | |
323 | pi->length++; | |
a720f7bc | 324 | |
7ee7b84d MS |
325 | pi->opcode = p; |
326 | pi++; | |
327 | } | |
328 | p1 = first_skipped; | |
252b5132 RH |
329 | } |
330 | ||
a720f7bc KD |
331 | /* Add entry for the NULL vector terminator. */ |
332 | pi->length = 0; | |
333 | pi->noperands = 0; | |
334 | pi->idx = 0; | |
335 | pi->size = 0; | |
7ee7b84d | 336 | pi->opcode = 0; |
a720f7bc | 337 | |
252b5132 RH |
338 | linkrelax = 1; |
339 | } | |
340 | ||
252b5132 RH |
341 | struct h8_op |
342 | { | |
343 | op_type mode; | |
344 | unsigned reg; | |
345 | expressionS exp; | |
346 | }; | |
347 | ||
b54a3392 KH |
348 | static void clever_message (const struct h8_instruction *, struct h8_op *); |
349 | static void fix_operand_size (struct h8_op *, int); | |
350 | static void build_bytes (const struct h8_instruction *, struct h8_op *); | |
bcb012d3 | 351 | static void do_a_fix_imm (int, int, struct h8_op *, int, const struct h8_instruction *); |
b54a3392 KH |
352 | static void check_operand (struct h8_op *, unsigned int, char *); |
353 | static const struct h8_instruction * get_specific (const struct h8_instruction *, struct h8_op *, int) ; | |
354 | static char *get_operands (unsigned, char *, struct h8_op *); | |
355 | static void get_operand (char **, struct h8_op *, int); | |
356 | static int parse_reg (char *, op_type *, unsigned *, int); | |
357 | static char *skip_colonthing (char *, int *); | |
358 | static char *parse_exp (char *, struct h8_op *); | |
359 | ||
b54a3392 | 360 | static int constant_fits_size_p (struct h8_op *, int, int); |
7ee7b84d | 361 | |
252b5132 RH |
362 | /* |
363 | parse operands | |
364 | WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp | |
365 | r0l,r0h,..r7l,r7h | |
366 | @WREG | |
367 | @WREG+ | |
368 | @-WREG | |
369 | #const | |
370 | ccr | |
371 | */ | |
372 | ||
bc0d738a NC |
373 | /* Try to parse a reg name. Return the number of chars consumed. */ |
374 | ||
40f09f82 | 375 | static int |
b54a3392 | 376 | parse_reg (char *src, op_type *mode, unsigned int *reg, int direction) |
252b5132 RH |
377 | { |
378 | char *end; | |
379 | int len; | |
380 | ||
70d6ecf3 | 381 | /* Cribbed from get_symbol_end. */ |
252b5132 RH |
382 | if (!is_name_beginner (*src) || *src == '\001') |
383 | return 0; | |
70d6ecf3 | 384 | end = src + 1; |
7ee7b84d | 385 | while ((is_part_of_name (*end) && *end != '.') || *end == '\001') |
252b5132 RH |
386 | end++; |
387 | len = end - src; | |
388 | ||
7ee7b84d | 389 | if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
390 | { |
391 | *mode = PSIZE | REG | direction; | |
392 | *reg = 7; | |
393 | return len; | |
394 | } | |
7ee7b84d MS |
395 | if (len == 3 && |
396 | TOLOWER (src[0]) == 'c' && | |
397 | TOLOWER (src[1]) == 'c' && | |
398 | TOLOWER (src[2]) == 'r') | |
252b5132 RH |
399 | { |
400 | *mode = CCR; | |
401 | *reg = 0; | |
402 | return len; | |
403 | } | |
7ee7b84d MS |
404 | if (len == 3 && |
405 | TOLOWER (src[0]) == 'e' && | |
406 | TOLOWER (src[1]) == 'x' && | |
407 | TOLOWER (src[2]) == 'r') | |
252b5132 RH |
408 | { |
409 | *mode = EXR; | |
7ee7b84d MS |
410 | *reg = 1; |
411 | return len; | |
412 | } | |
413 | if (len == 3 && | |
414 | TOLOWER (src[0]) == 'v' && | |
415 | TOLOWER (src[1]) == 'b' && | |
416 | TOLOWER (src[2]) == 'r') | |
417 | { | |
418 | *mode = VBR; | |
419 | *reg = 6; | |
420 | return len; | |
421 | } | |
422 | if (len == 3 && | |
423 | TOLOWER (src[0]) == 's' && | |
424 | TOLOWER (src[1]) == 'b' && | |
425 | TOLOWER (src[2]) == 'r') | |
426 | { | |
427 | *mode = SBR; | |
428 | *reg = 7; | |
252b5132 RH |
429 | return len; |
430 | } | |
7ee7b84d | 431 | if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
432 | { |
433 | *mode = PSIZE | REG | direction; | |
434 | *reg = 6; | |
435 | return len; | |
436 | } | |
7ee7b84d MS |
437 | if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
438 | src[2] >= '0' && src[2] <= '7') | |
252b5132 RH |
439 | { |
440 | *mode = L_32 | REG | direction; | |
441 | *reg = src[2] - '0'; | |
442 | if (!Hmode) | |
443 | as_warn (_("Reg not valid for H8/300")); | |
444 | return len; | |
445 | } | |
7ee7b84d | 446 | if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7') |
252b5132 RH |
447 | { |
448 | *mode = L_16 | REG | direction; | |
449 | *reg = src[1] - '0' + 8; | |
450 | if (!Hmode) | |
451 | as_warn (_("Reg not valid for H8/300")); | |
452 | return len; | |
453 | } | |
454 | ||
7ee7b84d | 455 | if (TOLOWER (src[0]) == 'r') |
252b5132 RH |
456 | { |
457 | if (src[1] >= '0' && src[1] <= '7') | |
458 | { | |
7ee7b84d | 459 | if (len == 3 && TOLOWER (src[2]) == 'l') |
252b5132 RH |
460 | { |
461 | *mode = L_8 | REG | direction; | |
462 | *reg = (src[1] - '0') + 8; | |
463 | return len; | |
464 | } | |
7ee7b84d | 465 | if (len == 3 && TOLOWER (src[2]) == 'h') |
252b5132 RH |
466 | { |
467 | *mode = L_8 | REG | direction; | |
468 | *reg = (src[1] - '0'); | |
469 | return len; | |
470 | } | |
471 | if (len == 2) | |
472 | { | |
473 | *mode = L_16 | REG | direction; | |
474 | *reg = (src[1] - '0'); | |
475 | return len; | |
476 | } | |
477 | } | |
478 | } | |
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
1b680e4f RS |
483 | |
484 | /* Parse an immediate or address-related constant and store it in OP. | |
485 | If the user also specifies the operand's size, store that size | |
486 | in OP->MODE, otherwise leave it for later code to decide. */ | |
487 | ||
40f09f82 | 488 | static char * |
b54a3392 | 489 | parse_exp (char *src, struct h8_op *op) |
252b5132 | 490 | { |
1b680e4f | 491 | char *save; |
252b5132 | 492 | |
1b680e4f RS |
493 | save = input_line_pointer; |
494 | input_line_pointer = src; | |
495 | expression (&op->exp); | |
496 | if (op->exp.X_op == O_absent) | |
252b5132 | 497 | as_bad (_("missing operand")); |
1b680e4f | 498 | src = input_line_pointer; |
252b5132 | 499 | input_line_pointer = save; |
1b680e4f RS |
500 | |
501 | return skip_colonthing (src, &op->mode); | |
252b5132 RH |
502 | } |
503 | ||
1b680e4f RS |
504 | |
505 | /* If SRC starts with an explicit operand size, skip it and store the size | |
506 | in *MODE. Leave *MODE unchanged otherwise. */ | |
507 | ||
252b5132 | 508 | static char * |
b54a3392 | 509 | skip_colonthing (char *src, int *mode) |
252b5132 | 510 | { |
1b680e4f | 511 | if (*src == ':') |
252b5132 | 512 | { |
1b680e4f | 513 | src++; |
252b5132 | 514 | *mode &= ~SIZE; |
1b680e4f | 515 | if (src[0] == '8' && !ISDIGIT (src[1])) |
7ee7b84d | 516 | *mode |= L_8; |
1b680e4f | 517 | else if (src[0] == '2' && !ISDIGIT (src[1])) |
7ee7b84d | 518 | *mode |= L_2; |
1b680e4f | 519 | else if (src[0] == '3' && !ISDIGIT (src[1])) |
7ee7b84d | 520 | *mode |= L_3; |
1b680e4f | 521 | else if (src[0] == '4' && !ISDIGIT (src[1])) |
7ee7b84d | 522 | *mode |= L_4; |
1b680e4f | 523 | else if (src[0] == '5' && !ISDIGIT (src[1])) |
7ee7b84d | 524 | *mode |= L_5; |
1b680e4f | 525 | else if (src[0] == '2' && src[1] == '4' && !ISDIGIT (src[2])) |
7ee7b84d | 526 | *mode |= L_24; |
1b680e4f | 527 | else if (src[0] == '3' && src[1] == '2' && !ISDIGIT (src[2])) |
7ee7b84d | 528 | *mode |= L_32; |
1b680e4f | 529 | else if (src[0] == '1' && src[1] == '6' && !ISDIGIT (src[2])) |
7ee7b84d | 530 | *mode |= L_16; |
252b5132 | 531 | else |
7ee7b84d MS |
532 | as_bad (_("invalid operand size requested")); |
533 | ||
1b680e4f RS |
534 | while (ISDIGIT (*src)) |
535 | src++; | |
252b5132 | 536 | } |
1b680e4f | 537 | return src; |
252b5132 RH |
538 | } |
539 | ||
540 | /* The many forms of operand: | |
541 | ||
542 | Rn Register direct | |
543 | @Rn Register indirect | |
544 | @(exp[:16], Rn) Register indirect with displacement | |
545 | @Rn+ | |
546 | @-Rn | |
70d6ecf3 AM |
547 | @aa:8 absolute 8 bit |
548 | @aa:16 absolute 16 bit | |
252b5132 RH |
549 | @aa absolute 16 bit |
550 | ||
551 | #xx[:size] immediate data | |
70d6ecf3 | 552 | @(exp:[8], pc) pc rel |
3048287a | 553 | @@aa[:8] memory indirect. */ |
252b5132 | 554 | |
7ee7b84d | 555 | static int |
df7b86aa | 556 | constant_fits_width_p (struct h8_op *operand, offsetT width) |
7ee7b84d | 557 | { |
35a35807 AM |
558 | offsetT num; |
559 | ||
560 | num = ((operand->exp.X_add_number & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
561 | return (num & ~width) == 0 || (num | width) == ~0; | |
7ee7b84d MS |
562 | } |
563 | ||
564 | static int | |
b54a3392 | 565 | constant_fits_size_p (struct h8_op *operand, int size, int no_symbols) |
7ee7b84d | 566 | { |
35a35807 AM |
567 | offsetT num; |
568 | ||
7ee7b84d MS |
569 | if (no_symbols |
570 | && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0)) | |
571 | return 0; | |
35a35807 | 572 | num = operand->exp.X_add_number & 0xffffffff; |
7ee7b84d MS |
573 | switch (size) |
574 | { | |
575 | case L_2: | |
576 | return (num & ~3) == 0; | |
577 | case L_3: | |
578 | return (num & ~7) == 0; | |
579 | case L_3NZ: | |
580 | return num >= 1 && num < 8; | |
581 | case L_4: | |
582 | return (num & ~15) == 0; | |
583 | case L_5: | |
584 | return num >= 1 && num < 32; | |
585 | case L_8: | |
35a35807 AM |
586 | num = (num ^ 0x80000000) - 0x80000000; |
587 | return (num & ~0xFF) == 0 || (num | 0x7F) == ~0; | |
7ee7b84d MS |
588 | case L_8U: |
589 | return (num & ~0xFF) == 0; | |
590 | case L_16: | |
35a35807 AM |
591 | num = (num ^ 0x80000000) - 0x80000000; |
592 | return (num & ~0xFFFF) == 0 || (num | 0x7FFF) == ~0; | |
7ee7b84d MS |
593 | case L_16U: |
594 | return (num & ~0xFFFF) == 0; | |
595 | case L_32: | |
596 | return 1; | |
597 | default: | |
598 | abort (); | |
599 | } | |
600 | } | |
601 | ||
252b5132 | 602 | static void |
b54a3392 | 603 | get_operand (char **ptr, struct h8_op *op, int direction) |
252b5132 RH |
604 | { |
605 | char *src = *ptr; | |
606 | op_type mode; | |
607 | unsigned int num; | |
608 | unsigned int len; | |
609 | ||
7ee7b84d | 610 | op->mode = 0; |
252b5132 | 611 | |
3048287a NC |
612 | /* Check for '(' and ')' for instructions ldm and stm. */ |
613 | if (src[0] == '(' && src[8] == ')') | |
614 | ++ src; | |
615 | ||
252b5132 RH |
616 | /* Gross. Gross. ldm and stm have a format not easily handled |
617 | by get_operand. We deal with it explicitly here. */ | |
7ee7b84d MS |
618 | if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
619 | ISDIGIT (src[2]) && src[3] == '-' && | |
620 | TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6])) | |
252b5132 RH |
621 | { |
622 | int low, high; | |
623 | ||
624 | low = src[2] - '0'; | |
625 | high = src[6] - '0'; | |
626 | ||
4892e510 NC |
627 | /* Check register pair's validity as per tech note TN-H8*-193A/E |
628 | from Renesas for H8S and H8SX hardware manual. */ | |
629 | if ( !(low == 0 && (high == 1 || high == 2 || high == 3)) | |
630 | && !(low == 1 && (high == 2 || high == 3 || high == 4) && SXmode) | |
631 | && !(low == 2 && (high == 3 || ((high == 4 || high == 5) && SXmode))) | |
632 | && !(low == 3 && (high == 4 || high == 5 || high == 6) && SXmode) | |
633 | && !(low == 4 && (high == 5 || high == 6)) | |
b4f16abb | 634 | && !(low == 4 && high == 7 && SXmode) |
4892e510 NC |
635 | && !(low == 5 && (high == 6 || high == 7) && SXmode) |
636 | && !(low == 6 && high == 7 && SXmode)) | |
252b5132 RH |
637 | as_bad (_("Invalid register list for ldm/stm\n")); |
638 | ||
252b5132 RH |
639 | /* Even sicker. We encode two registers into op->reg. One |
640 | for the low register to save, the other for the high | |
641 | register to save; we also set the high bit in op->reg | |
642 | so we know this is "very special". */ | |
643 | op->reg = 0x80000000 | (high << 8) | low; | |
644 | op->mode = REG; | |
3048287a NC |
645 | if (src[7] == ')') |
646 | *ptr = src + 8; | |
647 | else | |
648 | *ptr = src + 7; | |
252b5132 RH |
649 | return; |
650 | } | |
651 | ||
652 | len = parse_reg (src, &op->mode, &op->reg, direction); | |
653 | if (len) | |
654 | { | |
7ee7b84d MS |
655 | src += len; |
656 | if (*src == '.') | |
657 | { | |
658 | int size = op->mode & SIZE; | |
659 | switch (src[1]) | |
660 | { | |
661 | case 'l': case 'L': | |
662 | if (size != L_32) | |
663 | as_warn (_("mismatch between register and suffix")); | |
664 | op->mode = (op->mode & ~MODE) | LOWREG; | |
665 | break; | |
666 | case 'w': case 'W': | |
667 | if (size != L_32 && size != L_16) | |
668 | as_warn (_("mismatch between register and suffix")); | |
669 | op->mode = (op->mode & ~MODE) | LOWREG; | |
670 | op->mode = (op->mode & ~SIZE) | L_16; | |
671 | break; | |
672 | case 'b': case 'B': | |
673 | op->mode = (op->mode & ~MODE) | LOWREG; | |
674 | if (size != L_32 && size != L_8) | |
675 | as_warn (_("mismatch between register and suffix")); | |
676 | op->mode = (op->mode & ~MODE) | LOWREG; | |
677 | op->mode = (op->mode & ~SIZE) | L_8; | |
678 | break; | |
679 | default: | |
20203fb9 | 680 | as_warn (_("invalid suffix after register.")); |
7ee7b84d MS |
681 | break; |
682 | } | |
683 | src += 2; | |
684 | } | |
685 | *ptr = src; | |
252b5132 RH |
686 | return; |
687 | } | |
688 | ||
689 | if (*src == '@') | |
690 | { | |
691 | src++; | |
692 | if (*src == '@') | |
693 | { | |
1b680e4f | 694 | *ptr = parse_exp (src + 1, op); |
7ee7b84d MS |
695 | if (op->exp.X_add_number >= 0x100) |
696 | { | |
d4e2de6b | 697 | int divisor = 1; |
7ee7b84d MS |
698 | |
699 | op->mode = VECIND; | |
700 | /* FIXME : 2? or 4? */ | |
701 | if (op->exp.X_add_number >= 0x400) | |
702 | as_bad (_("address too high for vector table jmp/jsr")); | |
703 | else if (op->exp.X_add_number >= 0x200) | |
704 | divisor = 4; | |
705 | else | |
706 | divisor = 2; | |
707 | ||
708 | op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80; | |
709 | } | |
710 | else | |
711 | op->mode = MEMIND; | |
252b5132 | 712 | return; |
252b5132 RH |
713 | } |
714 | ||
7ee7b84d | 715 | if (*src == '-' || *src == '+') |
252b5132 | 716 | { |
1b680e4f | 717 | len = parse_reg (src + 1, &mode, &num, direction); |
252b5132 RH |
718 | if (len == 0) |
719 | { | |
70d6ecf3 | 720 | /* Oops, not a reg after all, must be ordinary exp. */ |
1b680e4f RS |
721 | op->mode = ABS | direction; |
722 | *ptr = parse_exp (src, op); | |
252b5132 | 723 | return; |
252b5132 RH |
724 | } |
725 | ||
d4e2de6b NC |
726 | if (((mode & SIZE) != PSIZE) |
727 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
728 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 729 | as_bad (_("Wrong size pointer register for architecture.")); |
1b680e4f RS |
730 | |
731 | op->mode = src[0] == '-' ? RDPREDEC : RDPREINC; | |
252b5132 | 732 | op->reg = num; |
1b680e4f | 733 | *ptr = src + 1 + len; |
252b5132 RH |
734 | return; |
735 | } | |
736 | if (*src == '(') | |
737 | { | |
252b5132 RH |
738 | src++; |
739 | ||
7ee7b84d MS |
740 | /* See if this is @(ERn.x, PC). */ |
741 | len = parse_reg (src, &mode, &op->reg, direction); | |
742 | if (len != 0 && (mode & MODE) == REG && src[len] == '.') | |
743 | { | |
744 | switch (TOLOWER (src[len + 1])) | |
745 | { | |
746 | case 'b': | |
747 | mode = PCIDXB | direction; | |
748 | break; | |
749 | case 'w': | |
750 | mode = PCIDXW | direction; | |
751 | break; | |
752 | case 'l': | |
753 | mode = PCIDXL | direction; | |
754 | break; | |
755 | default: | |
756 | mode = 0; | |
757 | break; | |
758 | } | |
759 | if (mode | |
760 | && src[len + 2] == ',' | |
761 | && TOLOWER (src[len + 3]) != 'p' | |
762 | && TOLOWER (src[len + 4]) != 'c' | |
763 | && src[len + 5] != ')') | |
764 | { | |
765 | *ptr = src + len + 6; | |
766 | op->mode |= mode; | |
767 | return; | |
768 | } | |
769 | /* Fall through into disp case - the grammar is somewhat | |
770 | ambiguous, so we should try whether it's a DISP operand | |
771 | after all ("ER3.L" might be a poorly named label...). */ | |
772 | } | |
773 | ||
774 | /* Disp. */ | |
775 | ||
70d6ecf3 | 776 | /* Start off assuming a 16 bit offset. */ |
252b5132 | 777 | |
1b680e4f | 778 | src = parse_exp (src, op); |
252b5132 RH |
779 | if (*src == ')') |
780 | { | |
252b5132 | 781 | op->mode |= ABS | direction; |
1b680e4f | 782 | *ptr = src + 1; |
252b5132 RH |
783 | return; |
784 | } | |
785 | ||
786 | if (*src != ',') | |
787 | { | |
788 | as_bad (_("expected @(exp, reg16)")); | |
789 | return; | |
252b5132 RH |
790 | } |
791 | src++; | |
792 | ||
793 | len = parse_reg (src, &mode, &op->reg, direction); | |
7ee7b84d | 794 | if (len == 0 || (mode & MODE) != REG) |
252b5132 RH |
795 | { |
796 | as_bad (_("expected @(exp, reg16)")); | |
797 | return; | |
798 | } | |
252b5132 | 799 | src += len; |
7ee7b84d MS |
800 | if (src[0] == '.') |
801 | { | |
802 | switch (TOLOWER (src[1])) | |
803 | { | |
804 | case 'b': | |
805 | op->mode |= INDEXB | direction; | |
806 | break; | |
807 | case 'w': | |
808 | op->mode |= INDEXW | direction; | |
809 | break; | |
810 | case 'l': | |
811 | op->mode |= INDEXL | direction; | |
812 | break; | |
813 | default: | |
814 | as_bad (_("expected .L, .W or .B for register in indexed addressing mode")); | |
815 | } | |
816 | src += 2; | |
817 | op->reg &= 7; | |
818 | } | |
819 | else | |
820 | op->mode |= DISP | direction; | |
1b680e4f | 821 | src = skip_colonthing (src, &op->mode); |
252b5132 RH |
822 | |
823 | if (*src != ')' && '(') | |
824 | { | |
825 | as_bad (_("expected @(exp, reg16)")); | |
826 | return; | |
827 | } | |
828 | *ptr = src + 1; | |
252b5132 RH |
829 | return; |
830 | } | |
831 | len = parse_reg (src, &mode, &num, direction); | |
832 | ||
833 | if (len) | |
834 | { | |
835 | src += len; | |
7ee7b84d | 836 | if (*src == '+' || *src == '-') |
252b5132 | 837 | { |
d4e2de6b NC |
838 | if (((mode & SIZE) != PSIZE) |
839 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
840 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 841 | as_bad (_("Wrong size pointer register for architecture.")); |
7ee7b84d | 842 | op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC; |
252b5132 | 843 | op->reg = num; |
7ee7b84d | 844 | src++; |
252b5132 RH |
845 | *ptr = src; |
846 | return; | |
847 | } | |
d4e2de6b NC |
848 | if (((mode & SIZE) != PSIZE) |
849 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
850 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 RH |
851 | as_bad (_("Wrong size pointer register for architecture.")); |
852 | ||
853 | op->mode = direction | IND | PSIZE; | |
854 | op->reg = num; | |
855 | *ptr = src; | |
856 | ||
857 | return; | |
858 | } | |
859 | else | |
860 | { | |
861 | /* must be a symbol */ | |
862 | ||
863 | op->mode = ABS | direction; | |
1b680e4f | 864 | *ptr = parse_exp (src, op); |
252b5132 RH |
865 | return; |
866 | } | |
867 | } | |
868 | ||
252b5132 RH |
869 | if (*src == '#') |
870 | { | |
252b5132 | 871 | op->mode = IMM; |
1b680e4f | 872 | *ptr = parse_exp (src + 1, op); |
252b5132 RH |
873 | return; |
874 | } | |
7ee7b84d MS |
875 | else if (strncmp (src, "mach", 4) == 0 || |
876 | strncmp (src, "macl", 4) == 0 || | |
877 | strncmp (src, "MACH", 4) == 0 || | |
878 | strncmp (src, "MACL", 4) == 0) | |
252b5132 | 879 | { |
7ee7b84d | 880 | op->reg = TOLOWER (src[3]) == 'l'; |
252b5132 RH |
881 | op->mode = MACREG; |
882 | *ptr = src + 4; | |
883 | return; | |
884 | } | |
885 | else | |
886 | { | |
1b680e4f RS |
887 | op->mode = PCREL; |
888 | *ptr = parse_exp (src, op); | |
252b5132 RH |
889 | } |
890 | } | |
891 | ||
70d6ecf3 | 892 | static char * |
b54a3392 | 893 | get_operands (unsigned int noperands, char *op_end, struct h8_op *operand) |
252b5132 RH |
894 | { |
895 | char *ptr = op_end; | |
896 | ||
897 | switch (noperands) | |
898 | { | |
899 | case 0: | |
252b5132 RH |
900 | break; |
901 | ||
902 | case 1: | |
903 | ptr++; | |
7ee7b84d | 904 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
905 | if (*ptr == ',') |
906 | { | |
907 | ptr++; | |
7ee7b84d | 908 | get_operand (&ptr, operand + 1, DST); |
252b5132 | 909 | } |
252b5132 | 910 | break; |
70d6ecf3 | 911 | |
252b5132 RH |
912 | case 2: |
913 | ptr++; | |
7ee7b84d | 914 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
915 | if (*ptr == ',') |
916 | ptr++; | |
7ee7b84d MS |
917 | get_operand (&ptr, operand + 1, DST); |
918 | break; | |
919 | ||
920 | case 3: | |
921 | ptr++; | |
922 | get_operand (&ptr, operand + 0, SRC); | |
923 | if (*ptr == ',') | |
924 | ptr++; | |
925 | get_operand (&ptr, operand + 1, DST); | |
926 | if (*ptr == ',') | |
927 | ptr++; | |
928 | get_operand (&ptr, operand + 2, OP3); | |
252b5132 RH |
929 | break; |
930 | ||
931 | default: | |
932 | abort (); | |
933 | } | |
934 | ||
252b5132 RH |
935 | return ptr; |
936 | } | |
937 | ||
7ee7b84d MS |
938 | /* MOVA has special requirements. Rather than adding twice the amount of |
939 | addressing modes, we simply special case it a bit. */ | |
940 | static void | |
941 | get_mova_operands (char *op_end, struct h8_op *operand) | |
942 | { | |
943 | char *ptr = op_end; | |
944 | ||
945 | if (ptr[1] != '@' || ptr[2] != '(') | |
946 | goto error; | |
947 | ptr += 3; | |
948 | operand[0].mode = 0; | |
1b680e4f | 949 | ptr = parse_exp (ptr, &operand[0]); |
7ee7b84d MS |
950 | |
951 | if (*ptr !=',') | |
952 | goto error; | |
953 | ptr++; | |
954 | get_operand (&ptr, operand + 1, DST); | |
955 | ||
956 | if (*ptr =='.') | |
957 | { | |
958 | ptr++; | |
959 | switch (*ptr++) | |
960 | { | |
961 | case 'b': case 'B': | |
962 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
963 | break; | |
964 | case 'w': case 'W': | |
965 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
966 | break; | |
967 | case 'l': case 'L': | |
968 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
969 | break; | |
970 | default: | |
971 | goto error; | |
972 | } | |
973 | } | |
974 | else if ((operand[1].mode & MODE) == LOWREG) | |
975 | { | |
976 | switch (operand[1].mode & SIZE) | |
977 | { | |
978 | case L_8: | |
979 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
980 | break; | |
981 | case L_16: | |
982 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
983 | break; | |
984 | case L_32: | |
985 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
986 | break; | |
987 | default: | |
988 | goto error; | |
989 | } | |
990 | } | |
991 | else | |
992 | goto error; | |
993 | ||
994 | if (*ptr++ != ')' || *ptr++ != ',') | |
995 | goto error; | |
996 | get_operand (&ptr, operand + 2, OP3); | |
997 | /* See if we can use the short form of MOVA. */ | |
998 | if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG) | |
999 | && (operand[2].mode & MODE) == REG | |
1000 | && (operand[1].reg & 7) == (operand[2].reg & 7)) | |
1001 | { | |
1002 | operand[1].mode = operand[2].mode = 0; | |
1003 | operand[0].reg = operand[2].reg & 7; | |
1004 | } | |
1005 | return; | |
1006 | ||
1007 | error: | |
1008 | as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\"")); | |
7ee7b84d MS |
1009 | } |
1010 | ||
1011 | static void | |
1012 | get_rtsl_operands (char *ptr, struct h8_op *operand) | |
1013 | { | |
2132e3a3 AM |
1014 | int mode, len, type = 0; |
1015 | unsigned int num, num2; | |
7ee7b84d MS |
1016 | |
1017 | ptr++; | |
1018 | if (*ptr == '(') | |
1019 | { | |
1020 | ptr++; | |
1021 | type = 1; | |
1022 | } | |
1023 | len = parse_reg (ptr, &mode, &num, SRC); | |
1024 | if (len == 0 || (mode & MODE) != REG) | |
1025 | { | |
1026 | as_bad (_("expected register")); | |
1027 | return; | |
1028 | } | |
0613284f RS |
1029 | ptr += len; |
1030 | if (*ptr == '-') | |
7ee7b84d | 1031 | { |
0613284f | 1032 | len = parse_reg (++ptr, &mode, &num2, SRC); |
7ee7b84d MS |
1033 | if (len == 0 || (mode & MODE) != REG) |
1034 | { | |
1035 | as_bad (_("expected register")); | |
1036 | return; | |
1037 | } | |
1038 | ptr += len; | |
7ee7b84d MS |
1039 | /* CONST_xxx are used as placeholders in the opcode table. */ |
1040 | num = num2 - num; | |
2132e3a3 | 1041 | if (num > 3) |
7ee7b84d MS |
1042 | { |
1043 | as_bad (_("invalid register list")); | |
1044 | return; | |
1045 | } | |
1046 | } | |
1047 | else | |
1048 | num2 = num, num = 0; | |
0613284f RS |
1049 | if (type == 1 && *ptr++ != ')') |
1050 | { | |
1051 | as_bad (_("expected closing paren")); | |
1052 | return; | |
1053 | } | |
7ee7b84d MS |
1054 | operand[0].mode = RS32; |
1055 | operand[1].mode = RD32; | |
1056 | operand[0].reg = num; | |
1057 | operand[1].reg = num2; | |
1058 | } | |
1059 | ||
252b5132 RH |
1060 | /* Passed a pointer to a list of opcodes which use different |
1061 | addressing modes, return the opcode which matches the opcodes | |
70d6ecf3 | 1062 | provided. */ |
3048287a | 1063 | |
a720f7bc | 1064 | static const struct h8_instruction * |
b54a3392 KH |
1065 | get_specific (const struct h8_instruction *instruction, |
1066 | struct h8_op *operands, int size) | |
252b5132 | 1067 | { |
a720f7bc | 1068 | const struct h8_instruction *this_try = instruction; |
7ee7b84d | 1069 | const struct h8_instruction *found_other = 0, *found_mismatched = 0; |
252b5132 | 1070 | int found = 0; |
a720f7bc | 1071 | int this_index = instruction->idx; |
7ee7b84d | 1072 | int noperands = 0; |
252b5132 RH |
1073 | |
1074 | /* There's only one ldm/stm and it's easier to just | |
1075 | get out quick for them. */ | |
7ee7b84d MS |
1076 | if (OP_KIND (instruction->opcode->how) == O_LDM |
1077 | || OP_KIND (instruction->opcode->how) == O_STM) | |
252b5132 RH |
1078 | return this_try; |
1079 | ||
7ee7b84d MS |
1080 | while (noperands < 3 && operands[noperands].mode != 0) |
1081 | noperands++; | |
1082 | ||
a720f7bc | 1083 | while (this_index == instruction->idx && !found) |
252b5132 | 1084 | { |
7ee7b84d | 1085 | int this_size; |
252b5132 | 1086 | |
7ee7b84d | 1087 | found = 1; |
a720f7bc | 1088 | this_try = instruction++; |
7ee7b84d | 1089 | this_size = this_try->opcode->how & SN; |
252b5132 | 1090 | |
7ee7b84d MS |
1091 | if (this_try->noperands != noperands) |
1092 | found = 0; | |
1093 | else if (this_try->noperands > 0) | |
252b5132 | 1094 | { |
3048287a | 1095 | int i; |
252b5132 RH |
1096 | |
1097 | for (i = 0; i < this_try->noperands && found; i++) | |
1098 | { | |
a720f7bc | 1099 | op_type op = this_try->opcode->args.nib[i]; |
7ee7b84d MS |
1100 | int op_mode = op & MODE; |
1101 | int op_size = op & SIZE; | |
252b5132 | 1102 | int x = operands[i].mode; |
7ee7b84d MS |
1103 | int x_mode = x & MODE; |
1104 | int x_size = x & SIZE; | |
252b5132 | 1105 | |
7ee7b84d | 1106 | if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG)) |
252b5132 | 1107 | { |
7ee7b84d MS |
1108 | if ((x_size == L_8 && (operands[i].reg & 8) == 0) |
1109 | || (x_size == L_16 && (operands[i].reg & 8) == 8)) | |
1110 | as_warn (_("can't use high part of register in operand %d"), i); | |
1111 | ||
1112 | if (x_size != op_size) | |
1113 | found = 0; | |
252b5132 | 1114 | } |
7ee7b84d | 1115 | else if (op_mode == REG) |
252b5132 | 1116 | { |
7ee7b84d MS |
1117 | if (x_mode == LOWREG) |
1118 | x_mode = REG; | |
1119 | if (x_mode != REG) | |
252b5132 RH |
1120 | found = 0; |
1121 | ||
7ee7b84d MS |
1122 | if (x_size == L_P) |
1123 | x_size = (Hmode ? L_32 : L_16); | |
1124 | if (op_size == L_P) | |
1125 | op_size = (Hmode ? L_32 : L_16); | |
252b5132 | 1126 | |
70d6ecf3 | 1127 | /* The size of the reg is v important. */ |
7ee7b84d | 1128 | if (op_size != x_size) |
252b5132 RH |
1129 | found = 0; |
1130 | } | |
7ee7b84d | 1131 | else if (op_mode & CTRL) /* control register */ |
252b5132 | 1132 | { |
7ee7b84d MS |
1133 | if (!(x_mode & CTRL)) |
1134 | found = 0; | |
1135 | ||
1136 | switch (x_mode) | |
1137 | { | |
1138 | case CCR: | |
1139 | if (op_mode != CCR && | |
1140 | op_mode != CCR_EXR && | |
1141 | op_mode != CC_EX_VB_SB) | |
1142 | found = 0; | |
1143 | break; | |
1144 | case EXR: | |
1145 | if (op_mode != EXR && | |
1146 | op_mode != CCR_EXR && | |
1147 | op_mode != CC_EX_VB_SB) | |
1148 | found = 0; | |
1149 | break; | |
1150 | case MACH: | |
1151 | if (op_mode != MACH && | |
1152 | op_mode != MACREG) | |
1153 | found = 0; | |
1154 | break; | |
1155 | case MACL: | |
1156 | if (op_mode != MACL && | |
1157 | op_mode != MACREG) | |
1158 | found = 0; | |
1159 | break; | |
1160 | case VBR: | |
1161 | if (op_mode != VBR && | |
1162 | op_mode != VBR_SBR && | |
1163 | op_mode != CC_EX_VB_SB) | |
1164 | found = 0; | |
1165 | break; | |
1166 | case SBR: | |
1167 | if (op_mode != SBR && | |
1168 | op_mode != VBR_SBR && | |
1169 | op_mode != CC_EX_VB_SB) | |
1170 | found = 0; | |
1171 | break; | |
1172 | } | |
1173 | } | |
1174 | else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL)) | |
1175 | { | |
1176 | operands[i].mode &= ~MODE; | |
252b5132 | 1177 | operands[i].mode |= ABSJMP; |
70d6ecf3 | 1178 | /* But it may not be 24 bits long. */ |
7ee7b84d | 1179 | if (x_mode == ABS && !Hmode) |
252b5132 RH |
1180 | { |
1181 | operands[i].mode &= ~SIZE; | |
1182 | operands[i].mode |= L_16; | |
1183 | } | |
7ee7b84d MS |
1184 | if ((operands[i].mode & SIZE) == L_32 |
1185 | && (op_mode & SIZE) != L_32) | |
1186 | found = 0; | |
252b5132 | 1187 | } |
7ee7b84d | 1188 | else if (x_mode == IMM && op_mode != IMM) |
252b5132 | 1189 | { |
35a35807 | 1190 | offsetT num = operands[i].exp.X_add_number & 0xffffffff; |
7ee7b84d MS |
1191 | if (op_mode == KBIT || op_mode == DBIT) |
1192 | /* This is ok if the immediate value is sensible. */; | |
1193 | else if (op_mode == CONST_2) | |
1194 | found = num == 2; | |
1195 | else if (op_mode == CONST_4) | |
1196 | found = num == 4; | |
1197 | else if (op_mode == CONST_8) | |
1198 | found = num == 8; | |
1199 | else if (op_mode == CONST_16) | |
1200 | found = num == 16; | |
1201 | else | |
1202 | found = 0; | |
252b5132 | 1203 | } |
7ee7b84d | 1204 | else if (op_mode == PCREL && op_mode == x_mode) |
252b5132 | 1205 | { |
ba18dd6f | 1206 | /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour: |
7ee7b84d | 1207 | If x_size is L_8, promote it. */ |
ba18dd6f AO |
1208 | if (OP_KIND (this_try->opcode->how) == O_MOVSD |
1209 | || OP_KIND (this_try->opcode->how) == O_BSRBC | |
1210 | || OP_KIND (this_try->opcode->how) == O_BSRBS) | |
7ee7b84d MS |
1211 | if (x_size == L_8) |
1212 | x_size = L_16; | |
1213 | ||
70d6ecf3 | 1214 | /* The size of the displacement is important. */ |
7ee7b84d | 1215 | if (op_size != x_size) |
252b5132 RH |
1216 | found = 0; |
1217 | } | |
7ee7b84d MS |
1218 | else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS |
1219 | || op_mode == INDEXB || op_mode == INDEXW | |
1220 | || op_mode == INDEXL) | |
1221 | && op_mode == x_mode) | |
252b5132 RH |
1222 | { |
1223 | /* Promote a L_24 to L_32 if it makes us match. */ | |
7ee7b84d | 1224 | if (x_size == L_24 && op_size == L_32) |
252b5132 | 1225 | { |
7ee7b84d MS |
1226 | x &= ~SIZE; |
1227 | x |= x_size = L_32; | |
252b5132 | 1228 | } |
7ee7b84d | 1229 | |
7ee7b84d | 1230 | if (((x_size == L_16 && op_size == L_16U) |
2d0d09ca | 1231 | || (x_size == L_8 && op_size == L_8U) |
7ee7b84d MS |
1232 | || (x_size == L_3 && op_size == L_3NZ)) |
1233 | /* We're deliberately more permissive for ABS modes. */ | |
1234 | && (op_mode == ABS | |
1235 | || constant_fits_size_p (operands + i, op_size, | |
1236 | op & NO_SYMBOLS))) | |
1237 | x_size = op_size; | |
1238 | ||
1239 | if (x_size != 0 && op_size != x_size) | |
1240 | found = 0; | |
1241 | else if (x_size == 0 | |
1242 | && ! constant_fits_size_p (operands + i, op_size, | |
1243 | op & NO_SYMBOLS)) | |
252b5132 RH |
1244 | found = 0; |
1245 | } | |
7ee7b84d | 1246 | else if (op_mode != x_mode) |
252b5132 RH |
1247 | { |
1248 | found = 0; | |
70d6ecf3 | 1249 | } |
252b5132 RH |
1250 | } |
1251 | } | |
7ee7b84d MS |
1252 | if (found) |
1253 | { | |
1254 | if ((this_try->opcode->available == AV_H8SX && ! SXmode) | |
d4ea8842 | 1255 | || (this_try->opcode->available == AV_H8S && ! Smode) |
7ee7b84d MS |
1256 | || (this_try->opcode->available == AV_H8H && ! Hmode)) |
1257 | found = 0, found_other = this_try; | |
1258 | else if (this_size != size && (this_size != SN && size != SN)) | |
1259 | found_mismatched = this_try, found = 0; | |
1260 | ||
1261 | } | |
252b5132 RH |
1262 | } |
1263 | if (found) | |
1264 | return this_try; | |
7ee7b84d MS |
1265 | if (found_other) |
1266 | { | |
1267 | as_warn (_("Opcode `%s' with these operand types not available in %s mode"), | |
1268 | found_other->opcode->name, | |
1269 | (! Hmode && ! Smode ? "H8/300" | |
1270 | : SXmode ? "H8sx" | |
1271 | : Smode ? "H8/300S" | |
1272 | : "H8/300H")); | |
1273 | } | |
1274 | else if (found_mismatched) | |
1275 | { | |
1276 | as_warn (_("mismatch between opcode size and operand size")); | |
1277 | return found_mismatched; | |
1278 | } | |
1279 | return 0; | |
252b5132 RH |
1280 | } |
1281 | ||
1282 | static void | |
b54a3392 | 1283 | check_operand (struct h8_op *operand, unsigned int width, char *string) |
252b5132 RH |
1284 | { |
1285 | if (operand->exp.X_add_symbol == 0 | |
1286 | && operand->exp.X_op_symbol == 0) | |
1287 | { | |
70d6ecf3 AM |
1288 | /* No symbol involved, let's look at offset, it's dangerous if |
1289 | any of the high bits are not 0 or ff's, find out by oring or | |
1290 | anding with the width and seeing if the answer is 0 or all | |
1291 | fs. */ | |
252b5132 | 1292 | |
7ee7b84d | 1293 | if (! constant_fits_width_p (operand, width)) |
252b5132 | 1294 | { |
70d6ecf3 | 1295 | if (width == 255 |
252b5132 RH |
1296 | && (operand->exp.X_add_number & 0xff00) == 0xff00) |
1297 | { | |
1298 | /* Just ignore this one - which happens when trying to | |
1299 | fit a 16 bit address truncated into an 8 bit address | |
1300 | of something like bset. */ | |
1301 | } | |
166e23f9 KH |
1302 | else if (strcmp (string, "@") == 0 |
1303 | && width == 0xffff | |
1304 | && (operand->exp.X_add_number & 0xff8000) == 0xff8000) | |
1305 | { | |
1306 | /* Just ignore this one - which happens when trying to | |
1307 | fit a 24 bit address truncated into a 16 bit address | |
1308 | of something like mov.w. */ | |
1309 | } | |
70d6ecf3 | 1310 | else |
252b5132 RH |
1311 | { |
1312 | as_warn (_("operand %s0x%lx out of range."), string, | |
1313 | (unsigned long) operand->exp.X_add_number); | |
1314 | } | |
1315 | } | |
1316 | } | |
252b5132 RH |
1317 | } |
1318 | ||
1319 | /* RELAXMODE has one of 3 values: | |
1320 | ||
1321 | 0 Output a "normal" reloc, no relaxing possible for this insn/reloc | |
1322 | ||
1323 | 1 Output a relaxable 24bit absolute mov.w address relocation | |
1324 | (may relax into a 16bit absolute address). | |
1325 | ||
1326 | 2 Output a relaxable 16/24 absolute mov.b address relocation | |
1327 | (may relax into an 8bit absolute address). */ | |
1328 | ||
1329 | static void | |
bcb012d3 | 1330 | do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode, const struct h8_instruction *this_try) |
252b5132 RH |
1331 | { |
1332 | int idx; | |
1333 | int size; | |
1334 | int where; | |
7ee7b84d | 1335 | char *bytes = frag_now->fr_literal + offset; |
252b5132 | 1336 | |
7ee7b84d | 1337 | char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; |
252b5132 RH |
1338 | |
1339 | if (operand->exp.X_add_symbol == 0) | |
1340 | { | |
252b5132 RH |
1341 | switch (operand->mode & SIZE) |
1342 | { | |
1343 | case L_2: | |
1344 | check_operand (operand, 0x3, t); | |
7ee7b84d | 1345 | bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4); |
252b5132 RH |
1346 | break; |
1347 | case L_3: | |
7ee7b84d | 1348 | case L_3NZ: |
252b5132 | 1349 | check_operand (operand, 0x7, t); |
7ee7b84d MS |
1350 | bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4); |
1351 | break; | |
1352 | case L_4: | |
1353 | check_operand (operand, 0xF, t); | |
1354 | bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4); | |
1355 | break; | |
1356 | case L_5: | |
1357 | check_operand (operand, 0x1F, t); | |
1358 | bytes[0] |= operand->exp.X_add_number & 31; | |
252b5132 RH |
1359 | break; |
1360 | case L_8: | |
7ee7b84d | 1361 | case L_8U: |
252b5132 | 1362 | check_operand (operand, 0xff, t); |
7ee7b84d | 1363 | bytes[0] |= operand->exp.X_add_number; |
252b5132 RH |
1364 | break; |
1365 | case L_16: | |
7ee7b84d | 1366 | case L_16U: |
252b5132 | 1367 | check_operand (operand, 0xffff, t); |
7ee7b84d MS |
1368 | bytes[0] |= operand->exp.X_add_number >> 8; |
1369 | bytes[1] |= operand->exp.X_add_number >> 0; | |
bcb012d3 DD |
1370 | #ifdef OBJ_ELF |
1371 | /* MOVA needs both relocs to relax the second operand properly. */ | |
1372 | if (relaxmode != 0 | |
1373 | && (OP_KIND(this_try->opcode->how) == O_MOVAB | |
1374 | || OP_KIND(this_try->opcode->how) == O_MOVAW | |
1375 | || OP_KIND(this_try->opcode->how) == O_MOVAL)) | |
1376 | { | |
1377 | idx = BFD_RELOC_16; | |
1378 | fix_new_exp (frag_now, offset, 2, &operand->exp, 0, idx); | |
1379 | } | |
1380 | #endif | |
252b5132 RH |
1381 | break; |
1382 | case L_24: | |
1383 | check_operand (operand, 0xffffff, t); | |
7ee7b84d MS |
1384 | bytes[0] |= operand->exp.X_add_number >> 16; |
1385 | bytes[1] |= operand->exp.X_add_number >> 8; | |
1386 | bytes[2] |= operand->exp.X_add_number >> 0; | |
252b5132 RH |
1387 | break; |
1388 | ||
1389 | case L_32: | |
70d6ecf3 | 1390 | /* This should be done with bfd. */ |
7ee7b84d MS |
1391 | bytes[0] |= operand->exp.X_add_number >> 24; |
1392 | bytes[1] |= operand->exp.X_add_number >> 16; | |
1393 | bytes[2] |= operand->exp.X_add_number >> 8; | |
1394 | bytes[3] |= operand->exp.X_add_number >> 0; | |
4132022d AM |
1395 | if (relaxmode != 0) |
1396 | { | |
81f5558e NC |
1397 | #ifdef OBJ_ELF |
1398 | if ((operand->mode & MODE) == DISP && relaxmode == 1) | |
1399 | idx = BFD_RELOC_H8_DISP32A16; | |
1400 | else | |
1401 | #endif | |
1402 | idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1; | |
4132022d AM |
1403 | fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx); |
1404 | } | |
252b5132 RH |
1405 | break; |
1406 | } | |
252b5132 RH |
1407 | } |
1408 | else | |
1409 | { | |
1410 | switch (operand->mode & SIZE) | |
1411 | { | |
252b5132 RH |
1412 | case L_24: |
1413 | case L_32: | |
1414 | size = 4; | |
1415 | where = (operand->mode & SIZE) == L_24 ? -1 : 0; | |
81f5558e NC |
1416 | #ifdef OBJ_ELF |
1417 | if ((operand->mode & MODE) == DISP && relaxmode == 1) | |
1418 | idx = BFD_RELOC_H8_DISP32A16; | |
1419 | else | |
1420 | #endif | |
252b5132 RH |
1421 | if (relaxmode == 2) |
1422 | idx = R_MOV24B1; | |
1423 | else if (relaxmode == 1) | |
1424 | idx = R_MOVL1; | |
1425 | else | |
1426 | idx = R_RELLONG; | |
1427 | break; | |
1428 | default: | |
70d6ecf3 | 1429 | as_bad (_("Can't work out size of operand.\n")); |
252b5132 | 1430 | case L_16: |
7ee7b84d | 1431 | case L_16U: |
252b5132 RH |
1432 | size = 2; |
1433 | where = 0; | |
1434 | if (relaxmode == 2) | |
1435 | idx = R_MOV16B1; | |
1436 | else | |
1437 | idx = R_RELWORD; | |
4132022d AM |
1438 | operand->exp.X_add_number = |
1439 | ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
7ee7b84d | 1440 | operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1]; |
252b5132 RH |
1441 | break; |
1442 | case L_8: | |
1443 | size = 1; | |
1444 | where = 0; | |
1445 | idx = R_RELBYTE; | |
4132022d AM |
1446 | operand->exp.X_add_number = |
1447 | ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
7ee7b84d | 1448 | operand->exp.X_add_number |= bytes[0]; |
252b5132 RH |
1449 | } |
1450 | ||
1451 | fix_new_exp (frag_now, | |
1452 | offset + where, | |
1453 | size, | |
1454 | &operand->exp, | |
1455 | 0, | |
1456 | idx); | |
1457 | } | |
252b5132 RH |
1458 | } |
1459 | ||
70d6ecf3 | 1460 | /* Now we know what sort of opcodes it is, let's build the bytes. */ |
3048287a | 1461 | |
252b5132 | 1462 | static void |
b54a3392 | 1463 | build_bytes (const struct h8_instruction *this_try, struct h8_op *operand) |
252b5132 | 1464 | { |
3048287a | 1465 | int i; |
252b5132 | 1466 | char *output = frag_more (this_try->length); |
d1e50f8a | 1467 | const op_type *nibble_ptr = this_try->opcode->data.nib; |
252b5132 RH |
1468 | op_type c; |
1469 | unsigned int nibble_count = 0; | |
7ee7b84d | 1470 | int op_at[3]; |
3048287a | 1471 | int nib = 0; |
252b5132 | 1472 | int movb = 0; |
7ee7b84d | 1473 | char asnibbles[100]; |
252b5132 | 1474 | char *p = asnibbles; |
7ee7b84d | 1475 | int high, low; |
252b5132 | 1476 | |
d4ea8842 | 1477 | if (!Hmode && this_try->opcode->available != AV_H8) |
252b5132 | 1478 | as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"), |
a720f7bc | 1479 | this_try->opcode->name); |
d4ea8842 MS |
1480 | else if (!Smode |
1481 | && this_try->opcode->available != AV_H8 | |
1482 | && this_try->opcode->available != AV_H8H) | |
1483 | as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"), | |
1484 | this_try->opcode->name); | |
1485 | else if (!SXmode | |
1486 | && this_try->opcode->available != AV_H8 | |
1487 | && this_try->opcode->available != AV_H8H | |
1488 | && this_try->opcode->available != AV_H8S) | |
1489 | as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"), | |
1490 | this_try->opcode->name); | |
252b5132 | 1491 | |
7ee7b84d | 1492 | while (*nibble_ptr != (op_type) E) |
252b5132 RH |
1493 | { |
1494 | int d; | |
7ee7b84d MS |
1495 | |
1496 | nib = 0; | |
252b5132 RH |
1497 | c = *nibble_ptr++; |
1498 | ||
7ee7b84d | 1499 | d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0; |
252b5132 RH |
1500 | |
1501 | if (c < 16) | |
3048287a | 1502 | nib = c; |
252b5132 RH |
1503 | else |
1504 | { | |
7ee7b84d MS |
1505 | int c2 = c & MODE; |
1506 | ||
1507 | if (c2 == REG || c2 == LOWREG | |
1508 | || c2 == IND || c2 == PREINC || c2 == PREDEC | |
1509 | || c2 == POSTINC || c2 == POSTDEC) | |
1510 | { | |
1511 | nib = operand[d].reg; | |
1512 | if (c2 == LOWREG) | |
1513 | nib &= 7; | |
1514 | } | |
1515 | ||
1516 | else if (c & CTRL) /* Control reg operand. */ | |
3048287a NC |
1517 | nib = operand[d].reg; |
1518 | ||
252b5132 | 1519 | else if ((c & DISPREG) == (DISPREG)) |
7ee7b84d MS |
1520 | { |
1521 | nib = operand[d].reg; | |
1522 | } | |
1523 | else if (c2 == ABS) | |
252b5132 RH |
1524 | { |
1525 | operand[d].mode = c; | |
7ee7b84d | 1526 | op_at[d] = nibble_count; |
252b5132 RH |
1527 | nib = 0; |
1528 | } | |
7ee7b84d MS |
1529 | else if (c2 == IMM || c2 == PCREL || c2 == ABS |
1530 | || (c & ABSJMP) || c2 == DISP) | |
252b5132 RH |
1531 | { |
1532 | operand[d].mode = c; | |
7ee7b84d | 1533 | op_at[d] = nibble_count; |
252b5132 RH |
1534 | nib = 0; |
1535 | } | |
7ee7b84d | 1536 | else if ((c & IGNORE) || (c & DATA)) |
3048287a NC |
1537 | nib = 0; |
1538 | ||
7ee7b84d | 1539 | else if (c2 == DBIT) |
252b5132 RH |
1540 | { |
1541 | switch (operand[0].exp.X_add_number) | |
1542 | { | |
1543 | case 1: | |
1544 | nib = c; | |
1545 | break; | |
1546 | case 2: | |
1547 | nib = 0x8 | c; | |
1548 | break; | |
1549 | default: | |
1550 | as_bad (_("Need #1 or #2 here")); | |
1551 | } | |
1552 | } | |
7ee7b84d | 1553 | else if (c2 == KBIT) |
252b5132 RH |
1554 | { |
1555 | switch (operand[0].exp.X_add_number) | |
1556 | { | |
1557 | case 1: | |
1558 | nib = 0; | |
1559 | break; | |
1560 | case 2: | |
1561 | nib = 8; | |
1562 | break; | |
1563 | case 4: | |
1564 | if (!Hmode) | |
1565 | as_warn (_("#4 not valid on H8/300.")); | |
1566 | nib = 9; | |
1567 | break; | |
1568 | ||
1569 | default: | |
1570 | as_bad (_("Need #1 or #2 here")); | |
1571 | break; | |
1572 | } | |
70d6ecf3 | 1573 | /* Stop it making a fix. */ |
252b5132 RH |
1574 | operand[0].mode = 0; |
1575 | } | |
1576 | ||
1577 | if (c & MEMRELAX) | |
3048287a | 1578 | operand[d].mode |= MEMRELAX; |
252b5132 RH |
1579 | |
1580 | if (c & B31) | |
3048287a | 1581 | nib |= 0x8; |
252b5132 | 1582 | |
7ee7b84d MS |
1583 | if (c & B21) |
1584 | nib |= 0x4; | |
1585 | ||
1586 | if (c & B11) | |
1587 | nib |= 0x2; | |
1588 | ||
1589 | if (c & B01) | |
1590 | nib |= 0x1; | |
1591 | ||
1592 | if (c2 == MACREG) | |
252b5132 | 1593 | { |
f0c56b90 NC |
1594 | if (operand[0].mode == MACREG) |
1595 | /* stmac has mac[hl] as the first operand. */ | |
1596 | nib = 2 + operand[0].reg; | |
1597 | else | |
1598 | /* ldmac has mac[hl] as the second operand. */ | |
1599 | nib = 2 + operand[1].reg; | |
252b5132 RH |
1600 | } |
1601 | } | |
1602 | nibble_count++; | |
1603 | ||
1604 | *p++ = nib; | |
1605 | } | |
1606 | ||
1607 | /* Disgusting. Why, oh why didn't someone ask us for advice | |
1608 | on the assembler format. */ | |
7ee7b84d | 1609 | if (OP_KIND (this_try->opcode->how) == O_LDM) |
252b5132 | 1610 | { |
7ee7b84d MS |
1611 | high = (operand[1].reg >> 8) & 0xf; |
1612 | low = (operand[1].reg) & 0xf; | |
252b5132 | 1613 | asnibbles[2] = high - low; |
7ee7b84d MS |
1614 | asnibbles[7] = high; |
1615 | } | |
1616 | else if (OP_KIND (this_try->opcode->how) == O_STM) | |
1617 | { | |
1618 | high = (operand[0].reg >> 8) & 0xf; | |
1619 | low = (operand[0].reg) & 0xf; | |
1620 | asnibbles[2] = high - low; | |
1621 | asnibbles[7] = low; | |
252b5132 RH |
1622 | } |
1623 | ||
1624 | for (i = 0; i < this_try->length; i++) | |
3048287a | 1625 | output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1]; |
252b5132 | 1626 | |
81f5558e | 1627 | /* Note if this is a mov.b or a bit manipulation instruction |
ca9a79a1 NC |
1628 | there is a special relaxation which only applies. */ |
1629 | if ( this_try->opcode->how == O (O_MOV, SB) | |
1630 | || this_try->opcode->how == O (O_BCLR, SB) | |
1631 | || this_try->opcode->how == O (O_BAND, SB) | |
1632 | || this_try->opcode->how == O (O_BIAND, SB) | |
1633 | || this_try->opcode->how == O (O_BILD, SB) | |
1634 | || this_try->opcode->how == O (O_BIOR, SB) | |
1635 | || this_try->opcode->how == O (O_BIST, SB) | |
1636 | || this_try->opcode->how == O (O_BIXOR, SB) | |
1637 | || this_try->opcode->how == O (O_BLD, SB) | |
1638 | || this_try->opcode->how == O (O_BNOT, SB) | |
1639 | || this_try->opcode->how == O (O_BOR, SB) | |
1640 | || this_try->opcode->how == O (O_BSET, SB) | |
1641 | || this_try->opcode->how == O (O_BST, SB) | |
1642 | || this_try->opcode->how == O (O_BTST, SB) | |
1643 | || this_try->opcode->how == O (O_BXOR, SB)) | |
252b5132 RH |
1644 | movb = 1; |
1645 | ||
70d6ecf3 | 1646 | /* Output any fixes. */ |
7ee7b84d | 1647 | for (i = 0; i < this_try->noperands; i++) |
252b5132 RH |
1648 | { |
1649 | int x = operand[i].mode; | |
7ee7b84d | 1650 | int x_mode = x & MODE; |
252b5132 | 1651 | |
7ee7b84d | 1652 | if (x_mode == IMM || x_mode == DISP) |
81f5558e NC |
1653 | { |
1654 | #ifndef OBJ_ELF | |
1655 | /* Remove MEMRELAX flag added in h8300.h on mov with | |
1656 | addressing mode "register indirect with displacement". */ | |
1657 | if (x_mode == DISP) | |
1658 | x &= ~MEMRELAX; | |
1659 | #endif | |
1660 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, | |
1661 | op_at[i] & 1, operand + i, (x & MEMRELAX) != 0, | |
1662 | this_try); | |
1663 | } | |
7ee7b84d MS |
1664 | else if (x_mode == ABS) |
1665 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, | |
1666 | op_at[i] & 1, operand + i, | |
bcb012d3 DD |
1667 | (x & MEMRELAX) ? movb + 1 : 0, |
1668 | this_try); | |
3048287a | 1669 | |
7ee7b84d | 1670 | else if (x_mode == PCREL) |
252b5132 | 1671 | { |
7ee7b84d | 1672 | int size16 = (x & SIZE) == L_16; |
252b5132 RH |
1673 | int size = size16 ? 2 : 1; |
1674 | int type = size16 ? R_PCRWORD : R_PCRBYTE; | |
36ed2fff | 1675 | fixS *fixP; |
252b5132 RH |
1676 | |
1677 | check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@"); | |
1678 | ||
1679 | if (operand[i].exp.X_add_number & 1) | |
3048287a NC |
1680 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1681 | (unsigned long) operand->exp.X_add_number); | |
36ed2fff JL |
1682 | #ifndef OBJ_ELF |
1683 | /* The COFF port has always been off by one, changing it | |
1684 | now would be an incompatible change, so we leave it as-is. | |
1685 | ||
1686 | We don't want to do this for ELF as we want to be | |
1687 | compatible with the proposed ELF format from Hitachi. */ | |
252b5132 | 1688 | operand[i].exp.X_add_number -= 1; |
36ed2fff | 1689 | #endif |
7ee7b84d MS |
1690 | if (size16) |
1691 | { | |
1692 | operand[i].exp.X_add_number = | |
1693 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
1694 | } | |
1695 | else | |
1696 | { | |
1697 | operand[i].exp.X_add_number = | |
1698 | ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
1699 | } | |
1700 | ||
1701 | /* For BRA/S. */ | |
1702 | if (! size16) | |
1703 | operand[i].exp.X_add_number |= output[op_at[i] / 2]; | |
252b5132 | 1704 | |
36ed2fff | 1705 | fixP = fix_new_exp (frag_now, |
7ee7b84d | 1706 | output - frag_now->fr_literal + op_at[i] / 2, |
36ed2fff JL |
1707 | size, |
1708 | &operand[i].exp, | |
1709 | 1, | |
1710 | type); | |
1711 | fixP->fx_signed = 1; | |
252b5132 | 1712 | } |
7ee7b84d | 1713 | else if (x_mode == MEMIND) |
252b5132 | 1714 | { |
252b5132 RH |
1715 | check_operand (operand + i, 0xff, "@@"); |
1716 | fix_new_exp (frag_now, | |
1717 | output - frag_now->fr_literal + 1, | |
1718 | 1, | |
1719 | &operand[i].exp, | |
1720 | 0, | |
1721 | R_MEM_INDIRECT); | |
1722 | } | |
7ee7b84d MS |
1723 | else if (x_mode == VECIND) |
1724 | { | |
1725 | check_operand (operand + i, 0x7f, "@@"); | |
1726 | /* FIXME: approximating the effect of "B31" here... | |
1727 | This is very hackish, and ought to be done a better way. */ | |
1728 | operand[i].exp.X_add_number |= 0x80; | |
1729 | fix_new_exp (frag_now, | |
1730 | output - frag_now->fr_literal + 1, | |
1731 | 1, | |
1732 | &operand[i].exp, | |
1733 | 0, | |
1734 | R_MEM_INDIRECT); | |
1735 | } | |
252b5132 RH |
1736 | else if (x & ABSJMP) |
1737 | { | |
3c1ba8a3 | 1738 | int where = 0; |
7ee7b84d | 1739 | bfd_reloc_code_real_type reloc_type = R_JMPL1; |
3c1ba8a3 JL |
1740 | |
1741 | #ifdef OBJ_ELF | |
1742 | /* To be compatible with the proposed H8 ELF format, we | |
1743 | want the relocation's offset to point to the first byte | |
1744 | that will be modified, not to the start of the instruction. */ | |
7ee7b84d MS |
1745 | |
1746 | if ((operand->mode & SIZE) == L_32) | |
1747 | { | |
1748 | where = 2; | |
1749 | reloc_type = R_RELLONG; | |
1750 | } | |
1751 | else | |
1752 | where = 1; | |
3c1ba8a3 | 1753 | #endif |
de342d07 | 1754 | |
70d6ecf3 | 1755 | /* This jmp may be a jump or a branch. */ |
252b5132 | 1756 | |
7ee7b84d MS |
1757 | check_operand (operand + i, |
1758 | SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff, | |
1759 | "@"); | |
3048287a | 1760 | |
252b5132 | 1761 | if (operand[i].exp.X_add_number & 1) |
3048287a NC |
1762 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1763 | (unsigned long) operand->exp.X_add_number); | |
1764 | ||
252b5132 | 1765 | if (!Hmode) |
70d6ecf3 | 1766 | operand[i].exp.X_add_number = |
4132022d | 1767 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; |
252b5132 | 1768 | fix_new_exp (frag_now, |
3c1ba8a3 | 1769 | output - frag_now->fr_literal + where, |
252b5132 RH |
1770 | 4, |
1771 | &operand[i].exp, | |
1772 | 0, | |
7ee7b84d | 1773 | reloc_type); |
252b5132 RH |
1774 | } |
1775 | } | |
252b5132 RH |
1776 | } |
1777 | ||
70d6ecf3 AM |
1778 | /* Try to give an intelligent error message for common and simple to |
1779 | detect errors. */ | |
3048287a | 1780 | |
252b5132 | 1781 | static void |
b54a3392 KH |
1782 | clever_message (const struct h8_instruction *instruction, |
1783 | struct h8_op *operand) | |
252b5132 | 1784 | { |
70d6ecf3 | 1785 | /* Find out if there was more than one possible opcode. */ |
252b5132 | 1786 | |
a720f7bc | 1787 | if ((instruction + 1)->idx != instruction->idx) |
252b5132 | 1788 | { |
3048287a | 1789 | int argn; |
252b5132 | 1790 | |
70d6ecf3 AM |
1791 | /* Only one opcode of this flavour, try to guess which operand |
1792 | didn't match. */ | |
a720f7bc | 1793 | for (argn = 0; argn < instruction->noperands; argn++) |
252b5132 | 1794 | { |
a720f7bc | 1795 | switch (instruction->opcode->args.nib[argn]) |
252b5132 RH |
1796 | { |
1797 | case RD16: | |
1798 | if (operand[argn].mode != RD16) | |
1799 | { | |
1800 | as_bad (_("destination operand must be 16 bit register")); | |
1801 | return; | |
1802 | ||
1803 | } | |
1804 | break; | |
1805 | ||
1806 | case RS8: | |
252b5132 RH |
1807 | if (operand[argn].mode != RS8) |
1808 | { | |
1809 | as_bad (_("source operand must be 8 bit register")); | |
1810 | return; | |
1811 | } | |
1812 | break; | |
1813 | ||
1814 | case ABS16DST: | |
1815 | if (operand[argn].mode != ABS16DST) | |
1816 | { | |
1817 | as_bad (_("destination operand must be 16bit absolute address")); | |
1818 | return; | |
1819 | } | |
1820 | break; | |
1821 | case RD8: | |
1822 | if (operand[argn].mode != RD8) | |
1823 | { | |
1824 | as_bad (_("destination operand must be 8 bit register")); | |
1825 | return; | |
1826 | } | |
1827 | break; | |
1828 | ||
252b5132 RH |
1829 | case ABS16SRC: |
1830 | if (operand[argn].mode != ABS16SRC) | |
1831 | { | |
1832 | as_bad (_("source operand must be 16bit absolute address")); | |
1833 | return; | |
1834 | } | |
1835 | break; | |
1836 | ||
1837 | } | |
1838 | } | |
1839 | } | |
1840 | as_bad (_("invalid operands")); | |
1841 | } | |
1842 | ||
d4ea8842 | 1843 | |
1b680e4f RS |
1844 | /* If OPERAND is part of an address, adjust its size and value given |
1845 | that it addresses SIZE bytes. | |
d4ea8842 | 1846 | |
1b680e4f RS |
1847 | This function decides how big non-immediate constants are when no |
1848 | size was explicitly given. It also scales down the assembly-level | |
d4ea8842 MS |
1849 | displacement in an @(d:2,ERn) operand. */ |
1850 | ||
1851 | static void | |
b54a3392 | 1852 | fix_operand_size (struct h8_op *operand, int size) |
d4ea8842 | 1853 | { |
1b680e4f | 1854 | if (SXmode && (operand->mode & MODE) == DISP) |
d4ea8842 MS |
1855 | { |
1856 | /* If the user didn't specify an operand width, see if we | |
1857 | can use @(d:2,ERn). */ | |
1b680e4f RS |
1858 | if ((operand->mode & SIZE) == 0 |
1859 | && operand->exp.X_add_symbol == 0 | |
1860 | && operand->exp.X_op_symbol == 0 | |
d4ea8842 MS |
1861 | && (operand->exp.X_add_number == size |
1862 | || operand->exp.X_add_number == size * 2 | |
1863 | || operand->exp.X_add_number == size * 3)) | |
1864 | operand->mode |= L_2; | |
1865 | ||
1866 | /* Scale down the displacement in an @(d:2,ERn) operand. | |
1867 | X_add_number then contains the desired field value. */ | |
1868 | if ((operand->mode & SIZE) == L_2) | |
1869 | { | |
1870 | if (operand->exp.X_add_number % size != 0) | |
1871 | as_warn (_("operand/size mis-match")); | |
1872 | operand->exp.X_add_number /= size; | |
1873 | } | |
1874 | } | |
1875 | ||
d4ea8842 MS |
1876 | if ((operand->mode & SIZE) == 0) |
1877 | switch (operand->mode & MODE) | |
1878 | { | |
1879 | case DISP: | |
1880 | case INDEXB: | |
1881 | case INDEXW: | |
1882 | case INDEXL: | |
1883 | case ABS: | |
1b680e4f RS |
1884 | /* Pick a 24-bit address unless we know that a 16-bit address |
1885 | is safe. get_specific() will relax L_24 into L_32 where | |
1886 | necessary. */ | |
1887 | if (Hmode | |
d4e2de6b | 1888 | && !Nmode |
35a35807 AM |
1889 | && ((((addressT) operand->exp.X_add_number + 0x8000) |
1890 | & 0xffffffff) > 0xffff | |
1b680e4f RS |
1891 | || operand->exp.X_add_symbol != 0 |
1892 | || operand->exp.X_op_symbol != 0)) | |
1893 | operand->mode |= L_24; | |
1894 | else | |
1895 | operand->mode |= L_16; | |
1896 | break; | |
1897 | ||
1898 | case PCREL: | |
35a35807 AM |
1899 | if ((((addressT) operand->exp.X_add_number + 0x80) |
1900 | & 0xffffffff) <= 0xff) | |
cc189afc DD |
1901 | { |
1902 | if (operand->exp.X_add_symbol != NULL) | |
1903 | operand->mode |= bsize; | |
1904 | else | |
1905 | operand->mode |= L_8; | |
1906 | } | |
1b680e4f RS |
1907 | else |
1908 | operand->mode |= L_16; | |
d4ea8842 MS |
1909 | break; |
1910 | } | |
1911 | } | |
1912 | ||
1913 | ||
70d6ecf3 AM |
1914 | /* This is the guts of the machine-dependent assembler. STR points to |
1915 | a machine dependent instruction. This function is supposed to emit | |
1916 | the frags/bytes it assembles. */ | |
3048287a | 1917 | |
252b5132 | 1918 | void |
b54a3392 | 1919 | md_assemble (char *str) |
252b5132 RH |
1920 | { |
1921 | char *op_start; | |
1922 | char *op_end; | |
7ee7b84d | 1923 | struct h8_op operand[3]; |
a720f7bc KD |
1924 | const struct h8_instruction *instruction; |
1925 | const struct h8_instruction *prev_instruction; | |
252b5132 RH |
1926 | |
1927 | char *dot = 0; | |
0c0b9be0 | 1928 | char *slash = 0; |
252b5132 | 1929 | char c; |
7ee7b84d | 1930 | int size, i; |
252b5132 | 1931 | |
70d6ecf3 | 1932 | /* Drop leading whitespace. */ |
252b5132 RH |
1933 | while (*str == ' ') |
1934 | str++; | |
1935 | ||
70d6ecf3 | 1936 | /* Find the op code end. */ |
252b5132 RH |
1937 | for (op_start = op_end = str; |
1938 | *op_end != 0 && *op_end != ' '; | |
1939 | op_end++) | |
1940 | { | |
1941 | if (*op_end == '.') | |
1942 | { | |
1943 | dot = op_end + 1; | |
1944 | *op_end = 0; | |
1945 | op_end += 2; | |
1946 | break; | |
1947 | } | |
0c0b9be0 AO |
1948 | else if (*op_end == '/' && ! slash) |
1949 | slash = op_end; | |
252b5132 RH |
1950 | } |
1951 | ||
252b5132 RH |
1952 | if (op_end == op_start) |
1953 | { | |
1954 | as_bad (_("can't find opcode ")); | |
1955 | } | |
1956 | c = *op_end; | |
1957 | ||
1958 | *op_end = 0; | |
1959 | ||
0c0b9be0 AO |
1960 | /* The assembler stops scanning the opcode at slashes, so it fails |
1961 | to make characters following them lower case. Fix them. */ | |
1962 | if (slash) | |
1963 | while (*++slash) | |
1964 | *slash = TOLOWER (*slash); | |
1965 | ||
a720f7bc KD |
1966 | instruction = (const struct h8_instruction *) |
1967 | hash_find (opcode_hash_control, op_start); | |
252b5132 | 1968 | |
a720f7bc | 1969 | if (instruction == NULL) |
252b5132 RH |
1970 | { |
1971 | as_bad (_("unknown opcode")); | |
1972 | return; | |
1973 | } | |
1974 | ||
70d6ecf3 | 1975 | /* We used to set input_line_pointer to the result of get_operands, |
252b5132 RH |
1976 | but that is wrong. Our caller assumes we don't change it. */ |
1977 | ||
7ee7b84d MS |
1978 | operand[0].mode = 0; |
1979 | operand[1].mode = 0; | |
1980 | operand[2].mode = 0; | |
1981 | ||
1982 | if (OP_KIND (instruction->opcode->how) == O_MOVAB | |
1983 | || OP_KIND (instruction->opcode->how) == O_MOVAW | |
1984 | || OP_KIND (instruction->opcode->how) == O_MOVAL) | |
1985 | get_mova_operands (op_end, operand); | |
1986 | else if (OP_KIND (instruction->opcode->how) == O_RTEL | |
1987 | || OP_KIND (instruction->opcode->how) == O_RTSL) | |
1988 | get_rtsl_operands (op_end, operand); | |
1989 | else | |
1990 | get_operands (instruction->noperands, op_end, operand); | |
1991 | ||
252b5132 | 1992 | *op_end = c; |
a720f7bc | 1993 | prev_instruction = instruction; |
252b5132 | 1994 | |
4892e510 NC |
1995 | /* Now we have operands from instruction. |
1996 | Let's check them out for ldm and stm. */ | |
1997 | if (OP_KIND (instruction->opcode->how) == O_LDM) | |
1998 | { | |
1999 | /* The first operand must be @er7+, and the | |
2000 | second operand must be a register pair. */ | |
2001 | if ((operand[0].mode != RSINC) | |
2002 | || (operand[0].reg != 7) | |
2003 | || ((operand[1].reg & 0x80000000) == 0)) | |
2004 | as_bad (_("invalid operand in ldm")); | |
2005 | } | |
2006 | else if (OP_KIND (instruction->opcode->how) == O_STM) | |
2007 | { | |
2008 | /* The first operand must be a register pair, | |
2009 | and the second operand must be @-er7. */ | |
2010 | if (((operand[0].reg & 0x80000000) == 0) | |
2011 | || (operand[1].mode != RDDEC) | |
2012 | || (operand[1].reg != 7)) | |
2013 | as_bad (_("invalid operand in stm")); | |
2014 | } | |
2015 | ||
252b5132 RH |
2016 | size = SN; |
2017 | if (dot) | |
2018 | { | |
0c0b9be0 | 2019 | switch (TOLOWER (*dot)) |
252b5132 RH |
2020 | { |
2021 | case 'b': | |
2022 | size = SB; | |
2023 | break; | |
2024 | ||
2025 | case 'w': | |
2026 | size = SW; | |
2027 | break; | |
2028 | ||
2029 | case 'l': | |
2030 | size = SL; | |
2031 | break; | |
2032 | } | |
2033 | } | |
7ee7b84d MS |
2034 | if (OP_KIND (instruction->opcode->how) == O_MOVAB || |
2035 | OP_KIND (instruction->opcode->how) == O_MOVAW || | |
2036 | OP_KIND (instruction->opcode->how) == O_MOVAL) | |
252b5132 | 2037 | { |
d4ea8842 MS |
2038 | switch (operand[0].mode & MODE) |
2039 | { | |
7ee7b84d MS |
2040 | case INDEXB: |
2041 | default: | |
d4ea8842 | 2042 | fix_operand_size (&operand[1], 1); |
7ee7b84d MS |
2043 | break; |
2044 | case INDEXW: | |
d4ea8842 | 2045 | fix_operand_size (&operand[1], 2); |
7ee7b84d MS |
2046 | break; |
2047 | case INDEXL: | |
d4ea8842 | 2048 | fix_operand_size (&operand[1], 4); |
7ee7b84d | 2049 | break; |
252b5132 RH |
2050 | } |
2051 | } | |
7ee7b84d MS |
2052 | else |
2053 | { | |
d4ea8842 MS |
2054 | for (i = 0; i < 3 && operand[i].mode != 0; i++) |
2055 | switch (size) | |
2056 | { | |
7ee7b84d MS |
2057 | case SN: |
2058 | case SB: | |
2059 | default: | |
d4ea8842 | 2060 | fix_operand_size (&operand[i], 1); |
7ee7b84d MS |
2061 | break; |
2062 | case SW: | |
d4ea8842 | 2063 | fix_operand_size (&operand[i], 2); |
7ee7b84d MS |
2064 | break; |
2065 | case SL: | |
d4ea8842 | 2066 | fix_operand_size (&operand[i], 4); |
7ee7b84d MS |
2067 | break; |
2068 | } | |
2069 | } | |
252b5132 | 2070 | |
d4ea8842 MS |
2071 | instruction = get_specific (instruction, operand, size); |
2072 | ||
2073 | if (instruction == 0) | |
2074 | { | |
2075 | /* Couldn't find an opcode which matched the operands. */ | |
2076 | char *where = frag_more (2); | |
2077 | ||
2078 | where[0] = 0x0; | |
2079 | where[1] = 0x0; | |
2080 | clever_message (prev_instruction, operand); | |
2081 | ||
2082 | return; | |
2083 | } | |
2084 | ||
a720f7bc | 2085 | build_bytes (instruction, operand); |
2c8714f2 | 2086 | |
2c8714f2 | 2087 | dwarf2_emit_insn (instruction->length); |
252b5132 RH |
2088 | } |
2089 | ||
2090 | symbolS * | |
b54a3392 | 2091 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
2092 | { |
2093 | return 0; | |
2094 | } | |
2095 | ||
499ac353 | 2096 | /* Various routines to kill one day. */ |
bc0d738a | 2097 | |
252b5132 | 2098 | char * |
b54a3392 | 2099 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 2100 | { |
499ac353 | 2101 | return ieee_md_atof (type, litP, sizeP, TRUE); |
252b5132 RH |
2102 | } |
2103 | \f | |
6fd4f6cc DD |
2104 | #define OPTION_H_TICK_HEX (OPTION_MD_BASE) |
2105 | ||
5a38dc70 | 2106 | const char *md_shortopts = ""; |
252b5132 | 2107 | struct option md_longopts[] = { |
6fd4f6cc | 2108 | { "h-tick-hex", no_argument, NULL, OPTION_H_TICK_HEX }, |
252b5132 RH |
2109 | {NULL, no_argument, NULL, 0} |
2110 | }; | |
70d6ecf3 AM |
2111 | |
2112 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
2113 | |
2114 | int | |
b54a3392 | 2115 | md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED) |
252b5132 | 2116 | { |
6fd4f6cc DD |
2117 | switch (c) |
2118 | { | |
2119 | case OPTION_H_TICK_HEX: | |
2120 | enable_h_tick_hex = 1; | |
2121 | break; | |
2122 | ||
2123 | default: | |
2124 | return 0; | |
2125 | } | |
2126 | return 1; | |
252b5132 RH |
2127 | } |
2128 | ||
2129 | void | |
b54a3392 | 2130 | md_show_usage (FILE *stream ATTRIBUTE_UNUSED) |
252b5132 RH |
2131 | { |
2132 | } | |
2133 | \f | |
b54a3392 | 2134 | void tc_aout_fix_to_chars (void); |
3048287a | 2135 | |
252b5132 | 2136 | void |
b54a3392 | 2137 | tc_aout_fix_to_chars (void) |
252b5132 RH |
2138 | { |
2139 | printf (_("call to tc_aout_fix_to_chars \n")); | |
2140 | abort (); | |
2141 | } | |
2142 | ||
2143 | void | |
7be1c489 | 2144 | md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, |
b54a3392 KH |
2145 | segT seg ATTRIBUTE_UNUSED, |
2146 | fragS *fragP ATTRIBUTE_UNUSED) | |
252b5132 RH |
2147 | { |
2148 | printf (_("call to md_convert_frag \n")); | |
2149 | abort (); | |
2150 | } | |
2151 | ||
3c1ba8a3 | 2152 | valueT |
b54a3392 | 2153 | md_section_align (segT segment, valueT size) |
3c1ba8a3 JL |
2154 | { |
2155 | int align = bfd_get_section_alignment (stdoutput, segment); | |
2156 | return ((size + (1 << align) - 1) & (-1 << align)); | |
2157 | } | |
252b5132 RH |
2158 | |
2159 | void | |
55cf6793 | 2160 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 RH |
2161 | { |
2162 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
a161fe53 | 2163 | long val = *valP; |
252b5132 RH |
2164 | |
2165 | switch (fixP->fx_size) | |
2166 | { | |
2167 | case 1: | |
2168 | *buf++ = val; | |
2169 | break; | |
2170 | case 2: | |
2171 | *buf++ = (val >> 8); | |
2172 | *buf++ = val; | |
2173 | break; | |
2174 | case 4: | |
2175 | *buf++ = (val >> 24); | |
2176 | *buf++ = (val >> 16); | |
2177 | *buf++ = (val >> 8); | |
2178 | *buf++ = val; | |
2179 | break; | |
550c1888 NC |
2180 | case 8: |
2181 | /* This can arise when the .quad or .8byte pseudo-ops are used. | |
2182 | Returning here (without setting fx_done) will cause the code | |
2183 | to attempt to generate a reloc which will then fail with the | |
2184 | slightly more helpful error message: "Cannot represent | |
2185 | relocation type BFD_RELOC_64". */ | |
2186 | return; | |
252b5132 RH |
2187 | default: |
2188 | abort (); | |
2189 | } | |
94f592af NC |
2190 | |
2191 | if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) | |
2192 | fixP->fx_done = 1; | |
252b5132 RH |
2193 | } |
2194 | ||
2195 | int | |
c85dd50d NC |
2196 | md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, |
2197 | segT segment_type ATTRIBUTE_UNUSED) | |
252b5132 | 2198 | { |
c85dd50d | 2199 | printf (_("call to md_estimate_size_before_relax \n")); |
252b5132 RH |
2200 | abort (); |
2201 | } | |
2202 | ||
70d6ecf3 | 2203 | /* Put number into target byte order. */ |
252b5132 | 2204 | void |
b54a3392 | 2205 | md_number_to_chars (char *ptr, valueT use, int nbytes) |
252b5132 RH |
2206 | { |
2207 | number_to_chars_bigendian (ptr, use, nbytes); | |
2208 | } | |
70d6ecf3 | 2209 | |
252b5132 | 2210 | long |
52b010e4 | 2211 | md_pcrel_from (fixS *fixp) |
252b5132 | 2212 | { |
52b010e4 NC |
2213 | as_bad_where (fixp->fx_file, fixp->fx_line, |
2214 | _("Unexpected reference to a symbol in a non-code section")); | |
2215 | return 0; | |
252b5132 RH |
2216 | } |
2217 | ||
f333765f | 2218 | arelent * |
b54a3392 | 2219 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
f333765f JL |
2220 | { |
2221 | arelent *rel; | |
2222 | bfd_reloc_code_real_type r_type; | |
2223 | ||
de342d07 JL |
2224 | if (fixp->fx_addsy && fixp->fx_subsy) |
2225 | { | |
2226 | if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy)) | |
2227 | || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section) | |
2228 | { | |
2229 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
c85dd50d | 2230 | _("Difference of symbols in different sections is not supported")); |
de342d07 JL |
2231 | return NULL; |
2232 | } | |
2233 | } | |
2234 | ||
c85dd50d NC |
2235 | rel = xmalloc (sizeof (arelent)); |
2236 | rel->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); | |
f333765f JL |
2237 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
2238 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
2239 | rel->addend = fixp->fx_offset; | |
2240 | ||
2241 | r_type = fixp->fx_r_type; | |
2242 | ||
2243 | #define DEBUG 0 | |
2244 | #if DEBUG | |
2245 | fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type)); | |
c85dd50d | 2246 | fflush (stderr); |
f333765f JL |
2247 | #endif |
2248 | rel->howto = bfd_reloc_type_lookup (stdoutput, r_type); | |
2249 | if (rel->howto == NULL) | |
2250 | { | |
2251 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
2252 | _("Cannot represent relocation type %s"), | |
2253 | bfd_get_reloc_code_name (r_type)); | |
2254 | return NULL; | |
2255 | } | |
2256 | ||
2257 | return rel; | |
2258 | } |