Commit | Line | Data |
---|---|---|
c2dcd04e | 1 | /* tc-h8300.c -- Assemble code for the Renesas H8/300 |
cc8a6dd0 | 2 | Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, |
35a35807 | 3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2012 |
aa820537 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 | 22 | |
bc0d738a | 23 | /* Written By Steve Chamberlain <sac@cygnus.com>. */ |
252b5132 | 24 | |
252b5132 RH |
25 | #include "as.h" |
26 | #include "subsegs.h" | |
2c8714f2 | 27 | #include "dwarf2dbg.h" |
2c8714f2 | 28 | |
252b5132 RH |
29 | #define DEFINE_TABLE |
30 | #define h8_opcodes ops | |
31 | #include "opcode/h8300.h" | |
3882b010 | 32 | #include "safe-ctype.h" |
252b5132 | 33 | |
7e0de7bf JL |
34 | #ifdef OBJ_ELF |
35 | #include "elf/h8.h" | |
7e0de7bf JL |
36 | #endif |
37 | ||
63a0b638 | 38 | const char comment_chars[] = ";"; |
252b5132 | 39 | const char line_comment_chars[] = "#"; |
63a0b638 | 40 | const char line_separator_chars[] = ""; |
252b5132 | 41 | |
600e9c99 KH |
42 | static void sbranch (int); |
43 | static void h8300hmode (int); | |
44 | static void h8300smode (int); | |
45 | static void h8300hnmode (int); | |
46 | static void h8300snmode (int); | |
47 | static void h8300sxmode (int); | |
48 | static void h8300sxnmode (int); | |
b54a3392 | 49 | static void pint (int); |
252b5132 | 50 | |
66faad26 KH |
51 | int Hmode; |
52 | int Smode; | |
53 | int Nmode; | |
54 | int SXmode; | |
3048287a | 55 | |
d4e2de6b | 56 | #define PSIZE (Hmode && !Nmode ? L_32 : L_16) |
3048287a | 57 | |
600e9c99 | 58 | static int bsize = L_8; /* Default branch displacement. */ |
252b5132 | 59 | |
a720f7bc KD |
60 | struct h8_instruction |
61 | { | |
62 | int length; | |
63 | int noperands; | |
64 | int idx; | |
65 | int size; | |
66 | const struct h8_opcode *opcode; | |
67 | }; | |
68 | ||
600e9c99 | 69 | static struct h8_instruction *h8_instructions; |
a720f7bc | 70 | |
600e9c99 | 71 | static void |
b54a3392 | 72 | h8300hmode (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
73 | { |
74 | Hmode = 1; | |
75 | Smode = 0; | |
83e20b45 JL |
76 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h)) |
77 | as_warn (_("could not set architecture and machine")); | |
252b5132 RH |
78 | } |
79 | ||
600e9c99 | 80 | static void |
b54a3392 | 81 | h8300smode (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
82 | { |
83 | Smode = 1; | |
84 | Hmode = 1; | |
83e20b45 JL |
85 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s)) |
86 | as_warn (_("could not set architecture and machine")); | |
252b5132 | 87 | } |
70d6ecf3 | 88 | |
600e9c99 | 89 | static void |
b54a3392 | 90 | h8300hnmode (int arg ATTRIBUTE_UNUSED) |
8d9cd6b1 NC |
91 | { |
92 | Hmode = 1; | |
93 | Smode = 0; | |
94 | Nmode = 1; | |
8d9cd6b1 NC |
95 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn)) |
96 | as_warn (_("could not set architecture and machine")); | |
8d9cd6b1 NC |
97 | } |
98 | ||
600e9c99 | 99 | static void |
b54a3392 | 100 | h8300snmode (int arg ATTRIBUTE_UNUSED) |
8d9cd6b1 NC |
101 | { |
102 | Smode = 1; | |
103 | Hmode = 1; | |
104 | Nmode = 1; | |
8d9cd6b1 NC |
105 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn)) |
106 | as_warn (_("could not set architecture and machine")); | |
8d9cd6b1 NC |
107 | } |
108 | ||
600e9c99 | 109 | static void |
b54a3392 | 110 | h8300sxmode (int arg ATTRIBUTE_UNUSED) |
7ee7b84d MS |
111 | { |
112 | Smode = 1; | |
113 | Hmode = 1; | |
114 | SXmode = 1; | |
7ee7b84d MS |
115 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx)) |
116 | as_warn (_("could not set architecture and machine")); | |
7ee7b84d MS |
117 | } |
118 | ||
600e9c99 | 119 | static void |
b54a3392 | 120 | h8300sxnmode (int arg ATTRIBUTE_UNUSED) |
f4984206 RS |
121 | { |
122 | Smode = 1; | |
123 | Hmode = 1; | |
124 | SXmode = 1; | |
125 | Nmode = 1; | |
f4984206 RS |
126 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn)) |
127 | as_warn (_("could not set architecture and machine")); | |
f4984206 RS |
128 | } |
129 | ||
600e9c99 | 130 | static void |
b54a3392 | 131 | sbranch (int size) |
252b5132 RH |
132 | { |
133 | bsize = size; | |
134 | } | |
135 | ||
70d6ecf3 | 136 | static void |
b54a3392 | 137 | pint (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
138 | { |
139 | cons (Hmode ? 4 : 2); | |
140 | } | |
141 | ||
52b010e4 NC |
142 | /* Like obj_elf_section, but issues a warning for new |
143 | sections which do not have an attribute specification. */ | |
144 | ||
145 | static void | |
146 | h8300_elf_section (int push) | |
147 | { | |
148 | static const char * known_data_sections [] = { ".rodata", ".tdata", ".tbss" }; | |
9c8b3bfe | 149 | static const char * known_data_prefixes [] = { ".debug", ".zdebug", ".gnu.warning" }; |
52b010e4 NC |
150 | char * saved_ilp = input_line_pointer; |
151 | char * name; | |
152 | ||
153 | name = obj_elf_section_name (); | |
154 | if (name == NULL) | |
155 | return; | |
156 | ||
157 | if (* input_line_pointer != ',' | |
158 | && bfd_get_section_by_name (stdoutput, name) == NULL) | |
159 | { | |
160 | signed int i; | |
161 | ||
162 | /* Ignore this warning for well known data sections. */ | |
163 | for (i = ARRAY_SIZE (known_data_sections); i--;) | |
164 | if (strcmp (name, known_data_sections[i]) == 0) | |
165 | break; | |
166 | ||
167 | if (i < 0) | |
168 | for (i = ARRAY_SIZE (known_data_prefixes); i--;) | |
169 | if (strncmp (name, known_data_prefixes[i], | |
170 | strlen (known_data_prefixes[i])) == 0) | |
171 | break; | |
172 | ||
173 | if (i < 0) | |
174 | as_warn (_("new section '%s' defined without attributes - this might cause problems"), name); | |
175 | } | |
176 | ||
177 | /* FIXME: We ought to free the memory allocated by obj_elf_section_name() | |
178 | for 'name', but we do not know if it was taken from the obstack, via | |
179 | demand_copy_C_string(), or xmalloc()ed. */ | |
180 | input_line_pointer = saved_ilp; | |
181 | obj_elf_section (push); | |
182 | } | |
183 | ||
3048287a NC |
184 | /* This table describes all the machine specific pseudo-ops the assembler |
185 | has to support. The fields are: | |
186 | pseudo-op name without dot | |
187 | function to call to execute this pseudo-op | |
188 | Integer arg to pass to the function. */ | |
189 | ||
252b5132 RH |
190 | const pseudo_typeS md_pseudo_table[] = |
191 | { | |
7ee7b84d | 192 | {"h8300h", h8300hmode, 0}, |
8d9cd6b1 | 193 | {"h8300hn", h8300hnmode, 0}, |
7ee7b84d | 194 | {"h8300s", h8300smode, 0}, |
8d9cd6b1 | 195 | {"h8300sn", h8300snmode, 0}, |
7ee7b84d | 196 | {"h8300sx", h8300sxmode, 0}, |
f4984206 | 197 | {"h8300sxn", h8300sxnmode, 0}, |
252b5132 RH |
198 | {"sbranch", sbranch, L_8}, |
199 | {"lbranch", sbranch, L_16}, | |
200 | ||
201 | {"int", pint, 0}, | |
202 | {"data.b", cons, 1}, | |
203 | {"data.w", cons, 2}, | |
204 | {"data.l", cons, 4}, | |
205 | {"form", listing_psize, 0}, | |
206 | {"heading", listing_title, 0}, | |
7ee7b84d MS |
207 | {"import", s_ignore, 0}, |
208 | {"page", listing_eject, 0}, | |
252b5132 | 209 | {"program", s_ignore, 0}, |
52b010e4 NC |
210 | |
211 | #ifdef OBJ_ELF | |
212 | {"section", h8300_elf_section, 0}, | |
213 | {"section.s", h8300_elf_section, 0}, | |
214 | {"sect", h8300_elf_section, 0}, | |
215 | {"sect.s", h8300_elf_section, 0}, | |
216 | #endif | |
217 | ||
252b5132 RH |
218 | {0, 0, 0} |
219 | }; | |
220 | ||
252b5132 RH |
221 | const char EXP_CHARS[] = "eE"; |
222 | ||
3048287a NC |
223 | /* Chars that mean this number is a floating point constant |
224 | As in 0f12.456 | |
225 | or 0d1.2345e12. */ | |
252b5132 RH |
226 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
227 | ||
3048287a | 228 | static struct hash_control *opcode_hash_control; /* Opcode mnemonics. */ |
252b5132 | 229 | |
70d6ecf3 AM |
230 | /* This function is called once, at assembler startup time. This |
231 | should set up all the tables, etc. that the MD part of the assembler | |
232 | needs. */ | |
3048287a | 233 | |
252b5132 | 234 | void |
b54a3392 | 235 | md_begin (void) |
252b5132 | 236 | { |
a720f7bc | 237 | unsigned int nopcodes; |
7ee7b84d | 238 | struct h8_opcode *p, *p1; |
a720f7bc | 239 | struct h8_instruction *pi; |
252b5132 RH |
240 | char prev_buffer[100]; |
241 | int idx = 0; | |
242 | ||
83e20b45 JL |
243 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300)) |
244 | as_warn (_("could not set architecture and machine")); | |
83e20b45 | 245 | |
252b5132 RH |
246 | opcode_hash_control = hash_new (); |
247 | prev_buffer[0] = 0; | |
248 | ||
a720f7bc KD |
249 | nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); |
250 | ||
251 | h8_instructions = (struct h8_instruction *) | |
252 | xmalloc (nopcodes * sizeof (struct h8_instruction)); | |
253 | ||
7ee7b84d MS |
254 | pi = h8_instructions; |
255 | p1 = h8_opcodes; | |
256 | /* We do a minimum amount of sorting on the opcode table; this is to | |
257 | make it easy to describe the mova instructions without unnecessary | |
258 | code duplication. | |
259 | Sorting only takes place inside blocks of instructions of the form | |
260 | X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */ | |
261 | while (p1) | |
252b5132 | 262 | { |
7ee7b84d MS |
263 | struct h8_opcode *first_skipped = 0; |
264 | int len, cmplen = 0; | |
265 | char *src = p1->name; | |
266 | char *dst, *buffer; | |
252b5132 | 267 | |
7ee7b84d MS |
268 | if (p1->name == 0) |
269 | break; | |
270 | /* Strip off any . part when inserting the opcode and only enter | |
271 | unique codes into the hash table. */ | |
272 | dst = buffer = malloc (strlen (src) + 1); | |
252b5132 RH |
273 | while (*src) |
274 | { | |
275 | if (*src == '.') | |
276 | { | |
277 | src++; | |
252b5132 RH |
278 | break; |
279 | } | |
7ee7b84d MS |
280 | if (*src == '/') |
281 | cmplen = src - p1->name + 1; | |
252b5132 RH |
282 | *dst++ = *src++; |
283 | } | |
7ee7b84d MS |
284 | *dst = 0; |
285 | len = dst - buffer; | |
286 | if (cmplen == 0) | |
287 | cmplen = len; | |
288 | hash_insert (opcode_hash_control, buffer, (char *) pi); | |
289 | strcpy (prev_buffer, buffer); | |
290 | idx++; | |
291 | ||
292 | for (p = p1; p->name; p++) | |
252b5132 | 293 | { |
7ee7b84d MS |
294 | /* A negative TIME is used to indicate that we've added this opcode |
295 | already. */ | |
296 | if (p->time == -1) | |
297 | continue; | |
298 | if (strncmp (p->name, buffer, cmplen) != 0 | |
299 | || (p->name[cmplen] != '\0' && p->name[cmplen] != '.' | |
300 | && p->name[cmplen - 1] != '/')) | |
301 | { | |
302 | if (first_skipped == 0) | |
303 | first_skipped = p; | |
304 | break; | |
305 | } | |
306 | if (strncmp (p->name, buffer, len) != 0) | |
307 | { | |
308 | if (first_skipped == 0) | |
309 | first_skipped = p; | |
310 | continue; | |
311 | } | |
312 | ||
313 | p->time = -1; | |
314 | pi->size = p->name[len] == '.' ? p->name[len + 1] : 0; | |
315 | pi->idx = idx; | |
252b5132 | 316 | |
7ee7b84d MS |
317 | /* Find the number of operands. */ |
318 | pi->noperands = 0; | |
319 | while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E) | |
320 | pi->noperands++; | |
70d6ecf3 | 321 | |
7ee7b84d MS |
322 | /* Find the length of the opcode in bytes. */ |
323 | pi->length = 0; | |
324 | while (p->data.nib[pi->length * 2] != (op_type) E) | |
325 | pi->length++; | |
a720f7bc | 326 | |
7ee7b84d MS |
327 | pi->opcode = p; |
328 | pi++; | |
329 | } | |
330 | p1 = first_skipped; | |
252b5132 RH |
331 | } |
332 | ||
a720f7bc KD |
333 | /* Add entry for the NULL vector terminator. */ |
334 | pi->length = 0; | |
335 | pi->noperands = 0; | |
336 | pi->idx = 0; | |
337 | pi->size = 0; | |
7ee7b84d | 338 | pi->opcode = 0; |
a720f7bc | 339 | |
252b5132 RH |
340 | linkrelax = 1; |
341 | } | |
342 | ||
252b5132 RH |
343 | struct h8_op |
344 | { | |
345 | op_type mode; | |
346 | unsigned reg; | |
347 | expressionS exp; | |
348 | }; | |
349 | ||
b54a3392 KH |
350 | static void clever_message (const struct h8_instruction *, struct h8_op *); |
351 | static void fix_operand_size (struct h8_op *, int); | |
352 | static void build_bytes (const struct h8_instruction *, struct h8_op *); | |
bcb012d3 | 353 | static void do_a_fix_imm (int, int, struct h8_op *, int, const struct h8_instruction *); |
b54a3392 KH |
354 | static void check_operand (struct h8_op *, unsigned int, char *); |
355 | static const struct h8_instruction * get_specific (const struct h8_instruction *, struct h8_op *, int) ; | |
356 | static char *get_operands (unsigned, char *, struct h8_op *); | |
357 | static void get_operand (char **, struct h8_op *, int); | |
358 | static int parse_reg (char *, op_type *, unsigned *, int); | |
359 | static char *skip_colonthing (char *, int *); | |
360 | static char *parse_exp (char *, struct h8_op *); | |
361 | ||
362 | static int constant_fits_width_p (struct h8_op *, unsigned int); | |
363 | static int constant_fits_size_p (struct h8_op *, int, int); | |
7ee7b84d | 364 | |
252b5132 RH |
365 | /* |
366 | parse operands | |
367 | WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp | |
368 | r0l,r0h,..r7l,r7h | |
369 | @WREG | |
370 | @WREG+ | |
371 | @-WREG | |
372 | #const | |
373 | ccr | |
374 | */ | |
375 | ||
bc0d738a NC |
376 | /* Try to parse a reg name. Return the number of chars consumed. */ |
377 | ||
40f09f82 | 378 | static int |
b54a3392 | 379 | parse_reg (char *src, op_type *mode, unsigned int *reg, int direction) |
252b5132 RH |
380 | { |
381 | char *end; | |
382 | int len; | |
383 | ||
70d6ecf3 | 384 | /* Cribbed from get_symbol_end. */ |
252b5132 RH |
385 | if (!is_name_beginner (*src) || *src == '\001') |
386 | return 0; | |
70d6ecf3 | 387 | end = src + 1; |
7ee7b84d | 388 | while ((is_part_of_name (*end) && *end != '.') || *end == '\001') |
252b5132 RH |
389 | end++; |
390 | len = end - src; | |
391 | ||
7ee7b84d | 392 | if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
393 | { |
394 | *mode = PSIZE | REG | direction; | |
395 | *reg = 7; | |
396 | return len; | |
397 | } | |
7ee7b84d MS |
398 | if (len == 3 && |
399 | TOLOWER (src[0]) == 'c' && | |
400 | TOLOWER (src[1]) == 'c' && | |
401 | TOLOWER (src[2]) == 'r') | |
252b5132 RH |
402 | { |
403 | *mode = CCR; | |
404 | *reg = 0; | |
405 | return len; | |
406 | } | |
7ee7b84d MS |
407 | if (len == 3 && |
408 | TOLOWER (src[0]) == 'e' && | |
409 | TOLOWER (src[1]) == 'x' && | |
410 | TOLOWER (src[2]) == 'r') | |
252b5132 RH |
411 | { |
412 | *mode = EXR; | |
7ee7b84d MS |
413 | *reg = 1; |
414 | return len; | |
415 | } | |
416 | if (len == 3 && | |
417 | TOLOWER (src[0]) == 'v' && | |
418 | TOLOWER (src[1]) == 'b' && | |
419 | TOLOWER (src[2]) == 'r') | |
420 | { | |
421 | *mode = VBR; | |
422 | *reg = 6; | |
423 | return len; | |
424 | } | |
425 | if (len == 3 && | |
426 | TOLOWER (src[0]) == 's' && | |
427 | TOLOWER (src[1]) == 'b' && | |
428 | TOLOWER (src[2]) == 'r') | |
429 | { | |
430 | *mode = SBR; | |
431 | *reg = 7; | |
252b5132 RH |
432 | return len; |
433 | } | |
7ee7b84d | 434 | if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
435 | { |
436 | *mode = PSIZE | REG | direction; | |
437 | *reg = 6; | |
438 | return len; | |
439 | } | |
7ee7b84d MS |
440 | if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
441 | src[2] >= '0' && src[2] <= '7') | |
252b5132 RH |
442 | { |
443 | *mode = L_32 | REG | direction; | |
444 | *reg = src[2] - '0'; | |
445 | if (!Hmode) | |
446 | as_warn (_("Reg not valid for H8/300")); | |
447 | return len; | |
448 | } | |
7ee7b84d | 449 | if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7') |
252b5132 RH |
450 | { |
451 | *mode = L_16 | REG | direction; | |
452 | *reg = src[1] - '0' + 8; | |
453 | if (!Hmode) | |
454 | as_warn (_("Reg not valid for H8/300")); | |
455 | return len; | |
456 | } | |
457 | ||
7ee7b84d | 458 | if (TOLOWER (src[0]) == 'r') |
252b5132 RH |
459 | { |
460 | if (src[1] >= '0' && src[1] <= '7') | |
461 | { | |
7ee7b84d | 462 | if (len == 3 && TOLOWER (src[2]) == 'l') |
252b5132 RH |
463 | { |
464 | *mode = L_8 | REG | direction; | |
465 | *reg = (src[1] - '0') + 8; | |
466 | return len; | |
467 | } | |
7ee7b84d | 468 | if (len == 3 && TOLOWER (src[2]) == 'h') |
252b5132 RH |
469 | { |
470 | *mode = L_8 | REG | direction; | |
471 | *reg = (src[1] - '0'); | |
472 | return len; | |
473 | } | |
474 | if (len == 2) | |
475 | { | |
476 | *mode = L_16 | REG | direction; | |
477 | *reg = (src[1] - '0'); | |
478 | return len; | |
479 | } | |
480 | } | |
481 | } | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
1b680e4f RS |
486 | |
487 | /* Parse an immediate or address-related constant and store it in OP. | |
488 | If the user also specifies the operand's size, store that size | |
489 | in OP->MODE, otherwise leave it for later code to decide. */ | |
490 | ||
40f09f82 | 491 | static char * |
b54a3392 | 492 | parse_exp (char *src, struct h8_op *op) |
252b5132 | 493 | { |
1b680e4f | 494 | char *save; |
252b5132 | 495 | |
1b680e4f RS |
496 | save = input_line_pointer; |
497 | input_line_pointer = src; | |
498 | expression (&op->exp); | |
499 | if (op->exp.X_op == O_absent) | |
252b5132 | 500 | as_bad (_("missing operand")); |
1b680e4f | 501 | src = input_line_pointer; |
252b5132 | 502 | input_line_pointer = save; |
1b680e4f RS |
503 | |
504 | return skip_colonthing (src, &op->mode); | |
252b5132 RH |
505 | } |
506 | ||
1b680e4f RS |
507 | |
508 | /* If SRC starts with an explicit operand size, skip it and store the size | |
509 | in *MODE. Leave *MODE unchanged otherwise. */ | |
510 | ||
252b5132 | 511 | static char * |
b54a3392 | 512 | skip_colonthing (char *src, int *mode) |
252b5132 | 513 | { |
1b680e4f | 514 | if (*src == ':') |
252b5132 | 515 | { |
1b680e4f | 516 | src++; |
252b5132 | 517 | *mode &= ~SIZE; |
1b680e4f | 518 | if (src[0] == '8' && !ISDIGIT (src[1])) |
7ee7b84d | 519 | *mode |= L_8; |
1b680e4f | 520 | else if (src[0] == '2' && !ISDIGIT (src[1])) |
7ee7b84d | 521 | *mode |= L_2; |
1b680e4f | 522 | else if (src[0] == '3' && !ISDIGIT (src[1])) |
7ee7b84d | 523 | *mode |= L_3; |
1b680e4f | 524 | else if (src[0] == '4' && !ISDIGIT (src[1])) |
7ee7b84d | 525 | *mode |= L_4; |
1b680e4f | 526 | else if (src[0] == '5' && !ISDIGIT (src[1])) |
7ee7b84d | 527 | *mode |= L_5; |
1b680e4f | 528 | else if (src[0] == '2' && src[1] == '4' && !ISDIGIT (src[2])) |
7ee7b84d | 529 | *mode |= L_24; |
1b680e4f | 530 | else if (src[0] == '3' && src[1] == '2' && !ISDIGIT (src[2])) |
7ee7b84d | 531 | *mode |= L_32; |
1b680e4f | 532 | else if (src[0] == '1' && src[1] == '6' && !ISDIGIT (src[2])) |
7ee7b84d | 533 | *mode |= L_16; |
252b5132 | 534 | else |
7ee7b84d MS |
535 | as_bad (_("invalid operand size requested")); |
536 | ||
1b680e4f RS |
537 | while (ISDIGIT (*src)) |
538 | src++; | |
252b5132 | 539 | } |
1b680e4f | 540 | return src; |
252b5132 RH |
541 | } |
542 | ||
543 | /* The many forms of operand: | |
544 | ||
545 | Rn Register direct | |
546 | @Rn Register indirect | |
547 | @(exp[:16], Rn) Register indirect with displacement | |
548 | @Rn+ | |
549 | @-Rn | |
70d6ecf3 AM |
550 | @aa:8 absolute 8 bit |
551 | @aa:16 absolute 16 bit | |
252b5132 RH |
552 | @aa absolute 16 bit |
553 | ||
554 | #xx[:size] immediate data | |
70d6ecf3 | 555 | @(exp:[8], pc) pc rel |
3048287a | 556 | @@aa[:8] memory indirect. */ |
252b5132 | 557 | |
7ee7b84d | 558 | static int |
b54a3392 | 559 | constant_fits_width_p (struct h8_op *operand, unsigned int width) |
7ee7b84d | 560 | { |
35a35807 AM |
561 | offsetT num; |
562 | ||
563 | num = ((operand->exp.X_add_number & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
564 | return (num & ~width) == 0 || (num | width) == ~0; | |
7ee7b84d MS |
565 | } |
566 | ||
567 | static int | |
b54a3392 | 568 | constant_fits_size_p (struct h8_op *operand, int size, int no_symbols) |
7ee7b84d | 569 | { |
35a35807 AM |
570 | offsetT num; |
571 | ||
7ee7b84d MS |
572 | if (no_symbols |
573 | && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0)) | |
574 | return 0; | |
35a35807 | 575 | num = operand->exp.X_add_number & 0xffffffff; |
7ee7b84d MS |
576 | switch (size) |
577 | { | |
578 | case L_2: | |
579 | return (num & ~3) == 0; | |
580 | case L_3: | |
581 | return (num & ~7) == 0; | |
582 | case L_3NZ: | |
583 | return num >= 1 && num < 8; | |
584 | case L_4: | |
585 | return (num & ~15) == 0; | |
586 | case L_5: | |
587 | return num >= 1 && num < 32; | |
588 | case L_8: | |
35a35807 AM |
589 | num = (num ^ 0x80000000) - 0x80000000; |
590 | return (num & ~0xFF) == 0 || (num | 0x7F) == ~0; | |
7ee7b84d MS |
591 | case L_8U: |
592 | return (num & ~0xFF) == 0; | |
593 | case L_16: | |
35a35807 AM |
594 | num = (num ^ 0x80000000) - 0x80000000; |
595 | return (num & ~0xFFFF) == 0 || (num | 0x7FFF) == ~0; | |
7ee7b84d MS |
596 | case L_16U: |
597 | return (num & ~0xFFFF) == 0; | |
598 | case L_32: | |
599 | return 1; | |
600 | default: | |
601 | abort (); | |
602 | } | |
603 | } | |
604 | ||
252b5132 | 605 | static void |
b54a3392 | 606 | get_operand (char **ptr, struct h8_op *op, int direction) |
252b5132 RH |
607 | { |
608 | char *src = *ptr; | |
609 | op_type mode; | |
610 | unsigned int num; | |
611 | unsigned int len; | |
612 | ||
7ee7b84d | 613 | op->mode = 0; |
252b5132 | 614 | |
3048287a NC |
615 | /* Check for '(' and ')' for instructions ldm and stm. */ |
616 | if (src[0] == '(' && src[8] == ')') | |
617 | ++ src; | |
618 | ||
252b5132 RH |
619 | /* Gross. Gross. ldm and stm have a format not easily handled |
620 | by get_operand. We deal with it explicitly here. */ | |
7ee7b84d MS |
621 | if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
622 | ISDIGIT (src[2]) && src[3] == '-' && | |
623 | TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6])) | |
252b5132 RH |
624 | { |
625 | int low, high; | |
626 | ||
627 | low = src[2] - '0'; | |
628 | high = src[6] - '0'; | |
629 | ||
4892e510 NC |
630 | /* Check register pair's validity as per tech note TN-H8*-193A/E |
631 | from Renesas for H8S and H8SX hardware manual. */ | |
632 | if ( !(low == 0 && (high == 1 || high == 2 || high == 3)) | |
633 | && !(low == 1 && (high == 2 || high == 3 || high == 4) && SXmode) | |
634 | && !(low == 2 && (high == 3 || ((high == 4 || high == 5) && SXmode))) | |
635 | && !(low == 3 && (high == 4 || high == 5 || high == 6) && SXmode) | |
636 | && !(low == 4 && (high == 5 || high == 6)) | |
b4f16abb | 637 | && !(low == 4 && high == 7 && SXmode) |
4892e510 NC |
638 | && !(low == 5 && (high == 6 || high == 7) && SXmode) |
639 | && !(low == 6 && high == 7 && SXmode)) | |
252b5132 RH |
640 | as_bad (_("Invalid register list for ldm/stm\n")); |
641 | ||
252b5132 RH |
642 | /* Even sicker. We encode two registers into op->reg. One |
643 | for the low register to save, the other for the high | |
644 | register to save; we also set the high bit in op->reg | |
645 | so we know this is "very special". */ | |
646 | op->reg = 0x80000000 | (high << 8) | low; | |
647 | op->mode = REG; | |
3048287a NC |
648 | if (src[7] == ')') |
649 | *ptr = src + 8; | |
650 | else | |
651 | *ptr = src + 7; | |
252b5132 RH |
652 | return; |
653 | } | |
654 | ||
655 | len = parse_reg (src, &op->mode, &op->reg, direction); | |
656 | if (len) | |
657 | { | |
7ee7b84d MS |
658 | src += len; |
659 | if (*src == '.') | |
660 | { | |
661 | int size = op->mode & SIZE; | |
662 | switch (src[1]) | |
663 | { | |
664 | case 'l': case 'L': | |
665 | if (size != L_32) | |
666 | as_warn (_("mismatch between register and suffix")); | |
667 | op->mode = (op->mode & ~MODE) | LOWREG; | |
668 | break; | |
669 | case 'w': case 'W': | |
670 | if (size != L_32 && size != L_16) | |
671 | as_warn (_("mismatch between register and suffix")); | |
672 | op->mode = (op->mode & ~MODE) | LOWREG; | |
673 | op->mode = (op->mode & ~SIZE) | L_16; | |
674 | break; | |
675 | case 'b': case 'B': | |
676 | op->mode = (op->mode & ~MODE) | LOWREG; | |
677 | if (size != L_32 && size != L_8) | |
678 | as_warn (_("mismatch between register and suffix")); | |
679 | op->mode = (op->mode & ~MODE) | LOWREG; | |
680 | op->mode = (op->mode & ~SIZE) | L_8; | |
681 | break; | |
682 | default: | |
20203fb9 | 683 | as_warn (_("invalid suffix after register.")); |
7ee7b84d MS |
684 | break; |
685 | } | |
686 | src += 2; | |
687 | } | |
688 | *ptr = src; | |
252b5132 RH |
689 | return; |
690 | } | |
691 | ||
692 | if (*src == '@') | |
693 | { | |
694 | src++; | |
695 | if (*src == '@') | |
696 | { | |
1b680e4f | 697 | *ptr = parse_exp (src + 1, op); |
7ee7b84d MS |
698 | if (op->exp.X_add_number >= 0x100) |
699 | { | |
d4e2de6b | 700 | int divisor = 1; |
7ee7b84d MS |
701 | |
702 | op->mode = VECIND; | |
703 | /* FIXME : 2? or 4? */ | |
704 | if (op->exp.X_add_number >= 0x400) | |
705 | as_bad (_("address too high for vector table jmp/jsr")); | |
706 | else if (op->exp.X_add_number >= 0x200) | |
707 | divisor = 4; | |
708 | else | |
709 | divisor = 2; | |
710 | ||
711 | op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80; | |
712 | } | |
713 | else | |
714 | op->mode = MEMIND; | |
252b5132 | 715 | return; |
252b5132 RH |
716 | } |
717 | ||
7ee7b84d | 718 | if (*src == '-' || *src == '+') |
252b5132 | 719 | { |
1b680e4f | 720 | len = parse_reg (src + 1, &mode, &num, direction); |
252b5132 RH |
721 | if (len == 0) |
722 | { | |
70d6ecf3 | 723 | /* Oops, not a reg after all, must be ordinary exp. */ |
1b680e4f RS |
724 | op->mode = ABS | direction; |
725 | *ptr = parse_exp (src, op); | |
252b5132 | 726 | return; |
252b5132 RH |
727 | } |
728 | ||
d4e2de6b NC |
729 | if (((mode & SIZE) != PSIZE) |
730 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
731 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 732 | as_bad (_("Wrong size pointer register for architecture.")); |
1b680e4f RS |
733 | |
734 | op->mode = src[0] == '-' ? RDPREDEC : RDPREINC; | |
252b5132 | 735 | op->reg = num; |
1b680e4f | 736 | *ptr = src + 1 + len; |
252b5132 RH |
737 | return; |
738 | } | |
739 | if (*src == '(') | |
740 | { | |
252b5132 RH |
741 | src++; |
742 | ||
7ee7b84d MS |
743 | /* See if this is @(ERn.x, PC). */ |
744 | len = parse_reg (src, &mode, &op->reg, direction); | |
745 | if (len != 0 && (mode & MODE) == REG && src[len] == '.') | |
746 | { | |
747 | switch (TOLOWER (src[len + 1])) | |
748 | { | |
749 | case 'b': | |
750 | mode = PCIDXB | direction; | |
751 | break; | |
752 | case 'w': | |
753 | mode = PCIDXW | direction; | |
754 | break; | |
755 | case 'l': | |
756 | mode = PCIDXL | direction; | |
757 | break; | |
758 | default: | |
759 | mode = 0; | |
760 | break; | |
761 | } | |
762 | if (mode | |
763 | && src[len + 2] == ',' | |
764 | && TOLOWER (src[len + 3]) != 'p' | |
765 | && TOLOWER (src[len + 4]) != 'c' | |
766 | && src[len + 5] != ')') | |
767 | { | |
768 | *ptr = src + len + 6; | |
769 | op->mode |= mode; | |
770 | return; | |
771 | } | |
772 | /* Fall through into disp case - the grammar is somewhat | |
773 | ambiguous, so we should try whether it's a DISP operand | |
774 | after all ("ER3.L" might be a poorly named label...). */ | |
775 | } | |
776 | ||
777 | /* Disp. */ | |
778 | ||
70d6ecf3 | 779 | /* Start off assuming a 16 bit offset. */ |
252b5132 | 780 | |
1b680e4f | 781 | src = parse_exp (src, op); |
252b5132 RH |
782 | if (*src == ')') |
783 | { | |
252b5132 | 784 | op->mode |= ABS | direction; |
1b680e4f | 785 | *ptr = src + 1; |
252b5132 RH |
786 | return; |
787 | } | |
788 | ||
789 | if (*src != ',') | |
790 | { | |
791 | as_bad (_("expected @(exp, reg16)")); | |
792 | return; | |
252b5132 RH |
793 | } |
794 | src++; | |
795 | ||
796 | len = parse_reg (src, &mode, &op->reg, direction); | |
7ee7b84d | 797 | if (len == 0 || (mode & MODE) != REG) |
252b5132 RH |
798 | { |
799 | as_bad (_("expected @(exp, reg16)")); | |
800 | return; | |
801 | } | |
252b5132 | 802 | src += len; |
7ee7b84d MS |
803 | if (src[0] == '.') |
804 | { | |
805 | switch (TOLOWER (src[1])) | |
806 | { | |
807 | case 'b': | |
808 | op->mode |= INDEXB | direction; | |
809 | break; | |
810 | case 'w': | |
811 | op->mode |= INDEXW | direction; | |
812 | break; | |
813 | case 'l': | |
814 | op->mode |= INDEXL | direction; | |
815 | break; | |
816 | default: | |
817 | as_bad (_("expected .L, .W or .B for register in indexed addressing mode")); | |
818 | } | |
819 | src += 2; | |
820 | op->reg &= 7; | |
821 | } | |
822 | else | |
823 | op->mode |= DISP | direction; | |
1b680e4f | 824 | src = skip_colonthing (src, &op->mode); |
252b5132 RH |
825 | |
826 | if (*src != ')' && '(') | |
827 | { | |
828 | as_bad (_("expected @(exp, reg16)")); | |
829 | return; | |
830 | } | |
831 | *ptr = src + 1; | |
252b5132 RH |
832 | return; |
833 | } | |
834 | len = parse_reg (src, &mode, &num, direction); | |
835 | ||
836 | if (len) | |
837 | { | |
838 | src += len; | |
7ee7b84d | 839 | if (*src == '+' || *src == '-') |
252b5132 | 840 | { |
d4e2de6b NC |
841 | if (((mode & SIZE) != PSIZE) |
842 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
843 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 844 | as_bad (_("Wrong size pointer register for architecture.")); |
7ee7b84d | 845 | op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC; |
252b5132 | 846 | op->reg = num; |
7ee7b84d | 847 | src++; |
252b5132 RH |
848 | *ptr = src; |
849 | return; | |
850 | } | |
d4e2de6b NC |
851 | if (((mode & SIZE) != PSIZE) |
852 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
853 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 RH |
854 | as_bad (_("Wrong size pointer register for architecture.")); |
855 | ||
856 | op->mode = direction | IND | PSIZE; | |
857 | op->reg = num; | |
858 | *ptr = src; | |
859 | ||
860 | return; | |
861 | } | |
862 | else | |
863 | { | |
864 | /* must be a symbol */ | |
865 | ||
866 | op->mode = ABS | direction; | |
1b680e4f | 867 | *ptr = parse_exp (src, op); |
252b5132 RH |
868 | return; |
869 | } | |
870 | } | |
871 | ||
252b5132 RH |
872 | if (*src == '#') |
873 | { | |
252b5132 | 874 | op->mode = IMM; |
1b680e4f | 875 | *ptr = parse_exp (src + 1, op); |
252b5132 RH |
876 | return; |
877 | } | |
7ee7b84d MS |
878 | else if (strncmp (src, "mach", 4) == 0 || |
879 | strncmp (src, "macl", 4) == 0 || | |
880 | strncmp (src, "MACH", 4) == 0 || | |
881 | strncmp (src, "MACL", 4) == 0) | |
252b5132 | 882 | { |
7ee7b84d | 883 | op->reg = TOLOWER (src[3]) == 'l'; |
252b5132 RH |
884 | op->mode = MACREG; |
885 | *ptr = src + 4; | |
886 | return; | |
887 | } | |
888 | else | |
889 | { | |
1b680e4f RS |
890 | op->mode = PCREL; |
891 | *ptr = parse_exp (src, op); | |
252b5132 RH |
892 | } |
893 | } | |
894 | ||
70d6ecf3 | 895 | static char * |
b54a3392 | 896 | get_operands (unsigned int noperands, char *op_end, struct h8_op *operand) |
252b5132 RH |
897 | { |
898 | char *ptr = op_end; | |
899 | ||
900 | switch (noperands) | |
901 | { | |
902 | case 0: | |
252b5132 RH |
903 | break; |
904 | ||
905 | case 1: | |
906 | ptr++; | |
7ee7b84d | 907 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
908 | if (*ptr == ',') |
909 | { | |
910 | ptr++; | |
7ee7b84d | 911 | get_operand (&ptr, operand + 1, DST); |
252b5132 | 912 | } |
252b5132 | 913 | break; |
70d6ecf3 | 914 | |
252b5132 RH |
915 | case 2: |
916 | ptr++; | |
7ee7b84d | 917 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
918 | if (*ptr == ',') |
919 | ptr++; | |
7ee7b84d MS |
920 | get_operand (&ptr, operand + 1, DST); |
921 | break; | |
922 | ||
923 | case 3: | |
924 | ptr++; | |
925 | get_operand (&ptr, operand + 0, SRC); | |
926 | if (*ptr == ',') | |
927 | ptr++; | |
928 | get_operand (&ptr, operand + 1, DST); | |
929 | if (*ptr == ',') | |
930 | ptr++; | |
931 | get_operand (&ptr, operand + 2, OP3); | |
252b5132 RH |
932 | break; |
933 | ||
934 | default: | |
935 | abort (); | |
936 | } | |
937 | ||
252b5132 RH |
938 | return ptr; |
939 | } | |
940 | ||
7ee7b84d MS |
941 | /* MOVA has special requirements. Rather than adding twice the amount of |
942 | addressing modes, we simply special case it a bit. */ | |
943 | static void | |
944 | get_mova_operands (char *op_end, struct h8_op *operand) | |
945 | { | |
946 | char *ptr = op_end; | |
947 | ||
948 | if (ptr[1] != '@' || ptr[2] != '(') | |
949 | goto error; | |
950 | ptr += 3; | |
951 | operand[0].mode = 0; | |
1b680e4f | 952 | ptr = parse_exp (ptr, &operand[0]); |
7ee7b84d MS |
953 | |
954 | if (*ptr !=',') | |
955 | goto error; | |
956 | ptr++; | |
957 | get_operand (&ptr, operand + 1, DST); | |
958 | ||
959 | if (*ptr =='.') | |
960 | { | |
961 | ptr++; | |
962 | switch (*ptr++) | |
963 | { | |
964 | case 'b': case 'B': | |
965 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
966 | break; | |
967 | case 'w': case 'W': | |
968 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
969 | break; | |
970 | case 'l': case 'L': | |
971 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
972 | break; | |
973 | default: | |
974 | goto error; | |
975 | } | |
976 | } | |
977 | else if ((operand[1].mode & MODE) == LOWREG) | |
978 | { | |
979 | switch (operand[1].mode & SIZE) | |
980 | { | |
981 | case L_8: | |
982 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
983 | break; | |
984 | case L_16: | |
985 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
986 | break; | |
987 | case L_32: | |
988 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
989 | break; | |
990 | default: | |
991 | goto error; | |
992 | } | |
993 | } | |
994 | else | |
995 | goto error; | |
996 | ||
997 | if (*ptr++ != ')' || *ptr++ != ',') | |
998 | goto error; | |
999 | get_operand (&ptr, operand + 2, OP3); | |
1000 | /* See if we can use the short form of MOVA. */ | |
1001 | if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG) | |
1002 | && (operand[2].mode & MODE) == REG | |
1003 | && (operand[1].reg & 7) == (operand[2].reg & 7)) | |
1004 | { | |
1005 | operand[1].mode = operand[2].mode = 0; | |
1006 | operand[0].reg = operand[2].reg & 7; | |
1007 | } | |
1008 | return; | |
1009 | ||
1010 | error: | |
1011 | as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\"")); | |
7ee7b84d MS |
1012 | } |
1013 | ||
1014 | static void | |
1015 | get_rtsl_operands (char *ptr, struct h8_op *operand) | |
1016 | { | |
2132e3a3 AM |
1017 | int mode, len, type = 0; |
1018 | unsigned int num, num2; | |
7ee7b84d MS |
1019 | |
1020 | ptr++; | |
1021 | if (*ptr == '(') | |
1022 | { | |
1023 | ptr++; | |
1024 | type = 1; | |
1025 | } | |
1026 | len = parse_reg (ptr, &mode, &num, SRC); | |
1027 | if (len == 0 || (mode & MODE) != REG) | |
1028 | { | |
1029 | as_bad (_("expected register")); | |
1030 | return; | |
1031 | } | |
0613284f RS |
1032 | ptr += len; |
1033 | if (*ptr == '-') | |
7ee7b84d | 1034 | { |
0613284f | 1035 | len = parse_reg (++ptr, &mode, &num2, SRC); |
7ee7b84d MS |
1036 | if (len == 0 || (mode & MODE) != REG) |
1037 | { | |
1038 | as_bad (_("expected register")); | |
1039 | return; | |
1040 | } | |
1041 | ptr += len; | |
7ee7b84d MS |
1042 | /* CONST_xxx are used as placeholders in the opcode table. */ |
1043 | num = num2 - num; | |
2132e3a3 | 1044 | if (num > 3) |
7ee7b84d MS |
1045 | { |
1046 | as_bad (_("invalid register list")); | |
1047 | return; | |
1048 | } | |
1049 | } | |
1050 | else | |
1051 | num2 = num, num = 0; | |
0613284f RS |
1052 | if (type == 1 && *ptr++ != ')') |
1053 | { | |
1054 | as_bad (_("expected closing paren")); | |
1055 | return; | |
1056 | } | |
7ee7b84d MS |
1057 | operand[0].mode = RS32; |
1058 | operand[1].mode = RD32; | |
1059 | operand[0].reg = num; | |
1060 | operand[1].reg = num2; | |
1061 | } | |
1062 | ||
252b5132 RH |
1063 | /* Passed a pointer to a list of opcodes which use different |
1064 | addressing modes, return the opcode which matches the opcodes | |
70d6ecf3 | 1065 | provided. */ |
3048287a | 1066 | |
a720f7bc | 1067 | static const struct h8_instruction * |
b54a3392 KH |
1068 | get_specific (const struct h8_instruction *instruction, |
1069 | struct h8_op *operands, int size) | |
252b5132 | 1070 | { |
a720f7bc | 1071 | const struct h8_instruction *this_try = instruction; |
7ee7b84d | 1072 | const struct h8_instruction *found_other = 0, *found_mismatched = 0; |
252b5132 | 1073 | int found = 0; |
a720f7bc | 1074 | int this_index = instruction->idx; |
7ee7b84d | 1075 | int noperands = 0; |
252b5132 RH |
1076 | |
1077 | /* There's only one ldm/stm and it's easier to just | |
1078 | get out quick for them. */ | |
7ee7b84d MS |
1079 | if (OP_KIND (instruction->opcode->how) == O_LDM |
1080 | || OP_KIND (instruction->opcode->how) == O_STM) | |
252b5132 RH |
1081 | return this_try; |
1082 | ||
7ee7b84d MS |
1083 | while (noperands < 3 && operands[noperands].mode != 0) |
1084 | noperands++; | |
1085 | ||
a720f7bc | 1086 | while (this_index == instruction->idx && !found) |
252b5132 | 1087 | { |
7ee7b84d | 1088 | int this_size; |
252b5132 | 1089 | |
7ee7b84d | 1090 | found = 1; |
a720f7bc | 1091 | this_try = instruction++; |
7ee7b84d | 1092 | this_size = this_try->opcode->how & SN; |
252b5132 | 1093 | |
7ee7b84d MS |
1094 | if (this_try->noperands != noperands) |
1095 | found = 0; | |
1096 | else if (this_try->noperands > 0) | |
252b5132 | 1097 | { |
3048287a | 1098 | int i; |
252b5132 RH |
1099 | |
1100 | for (i = 0; i < this_try->noperands && found; i++) | |
1101 | { | |
a720f7bc | 1102 | op_type op = this_try->opcode->args.nib[i]; |
7ee7b84d MS |
1103 | int op_mode = op & MODE; |
1104 | int op_size = op & SIZE; | |
252b5132 | 1105 | int x = operands[i].mode; |
7ee7b84d MS |
1106 | int x_mode = x & MODE; |
1107 | int x_size = x & SIZE; | |
252b5132 | 1108 | |
7ee7b84d | 1109 | if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG)) |
252b5132 | 1110 | { |
7ee7b84d MS |
1111 | if ((x_size == L_8 && (operands[i].reg & 8) == 0) |
1112 | || (x_size == L_16 && (operands[i].reg & 8) == 8)) | |
1113 | as_warn (_("can't use high part of register in operand %d"), i); | |
1114 | ||
1115 | if (x_size != op_size) | |
1116 | found = 0; | |
252b5132 | 1117 | } |
7ee7b84d | 1118 | else if (op_mode == REG) |
252b5132 | 1119 | { |
7ee7b84d MS |
1120 | if (x_mode == LOWREG) |
1121 | x_mode = REG; | |
1122 | if (x_mode != REG) | |
252b5132 RH |
1123 | found = 0; |
1124 | ||
7ee7b84d MS |
1125 | if (x_size == L_P) |
1126 | x_size = (Hmode ? L_32 : L_16); | |
1127 | if (op_size == L_P) | |
1128 | op_size = (Hmode ? L_32 : L_16); | |
252b5132 | 1129 | |
70d6ecf3 | 1130 | /* The size of the reg is v important. */ |
7ee7b84d | 1131 | if (op_size != x_size) |
252b5132 RH |
1132 | found = 0; |
1133 | } | |
7ee7b84d | 1134 | else if (op_mode & CTRL) /* control register */ |
252b5132 | 1135 | { |
7ee7b84d MS |
1136 | if (!(x_mode & CTRL)) |
1137 | found = 0; | |
1138 | ||
1139 | switch (x_mode) | |
1140 | { | |
1141 | case CCR: | |
1142 | if (op_mode != CCR && | |
1143 | op_mode != CCR_EXR && | |
1144 | op_mode != CC_EX_VB_SB) | |
1145 | found = 0; | |
1146 | break; | |
1147 | case EXR: | |
1148 | if (op_mode != EXR && | |
1149 | op_mode != CCR_EXR && | |
1150 | op_mode != CC_EX_VB_SB) | |
1151 | found = 0; | |
1152 | break; | |
1153 | case MACH: | |
1154 | if (op_mode != MACH && | |
1155 | op_mode != MACREG) | |
1156 | found = 0; | |
1157 | break; | |
1158 | case MACL: | |
1159 | if (op_mode != MACL && | |
1160 | op_mode != MACREG) | |
1161 | found = 0; | |
1162 | break; | |
1163 | case VBR: | |
1164 | if (op_mode != VBR && | |
1165 | op_mode != VBR_SBR && | |
1166 | op_mode != CC_EX_VB_SB) | |
1167 | found = 0; | |
1168 | break; | |
1169 | case SBR: | |
1170 | if (op_mode != SBR && | |
1171 | op_mode != VBR_SBR && | |
1172 | op_mode != CC_EX_VB_SB) | |
1173 | found = 0; | |
1174 | break; | |
1175 | } | |
1176 | } | |
1177 | else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL)) | |
1178 | { | |
1179 | operands[i].mode &= ~MODE; | |
252b5132 | 1180 | operands[i].mode |= ABSJMP; |
70d6ecf3 | 1181 | /* But it may not be 24 bits long. */ |
7ee7b84d | 1182 | if (x_mode == ABS && !Hmode) |
252b5132 RH |
1183 | { |
1184 | operands[i].mode &= ~SIZE; | |
1185 | operands[i].mode |= L_16; | |
1186 | } | |
7ee7b84d MS |
1187 | if ((operands[i].mode & SIZE) == L_32 |
1188 | && (op_mode & SIZE) != L_32) | |
1189 | found = 0; | |
252b5132 | 1190 | } |
7ee7b84d | 1191 | else if (x_mode == IMM && op_mode != IMM) |
252b5132 | 1192 | { |
35a35807 | 1193 | offsetT num = operands[i].exp.X_add_number & 0xffffffff; |
7ee7b84d MS |
1194 | if (op_mode == KBIT || op_mode == DBIT) |
1195 | /* This is ok if the immediate value is sensible. */; | |
1196 | else if (op_mode == CONST_2) | |
1197 | found = num == 2; | |
1198 | else if (op_mode == CONST_4) | |
1199 | found = num == 4; | |
1200 | else if (op_mode == CONST_8) | |
1201 | found = num == 8; | |
1202 | else if (op_mode == CONST_16) | |
1203 | found = num == 16; | |
1204 | else | |
1205 | found = 0; | |
252b5132 | 1206 | } |
7ee7b84d | 1207 | else if (op_mode == PCREL && op_mode == x_mode) |
252b5132 | 1208 | { |
ba18dd6f | 1209 | /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour: |
7ee7b84d | 1210 | If x_size is L_8, promote it. */ |
ba18dd6f AO |
1211 | if (OP_KIND (this_try->opcode->how) == O_MOVSD |
1212 | || OP_KIND (this_try->opcode->how) == O_BSRBC | |
1213 | || OP_KIND (this_try->opcode->how) == O_BSRBS) | |
7ee7b84d MS |
1214 | if (x_size == L_8) |
1215 | x_size = L_16; | |
1216 | ||
70d6ecf3 | 1217 | /* The size of the displacement is important. */ |
7ee7b84d | 1218 | if (op_size != x_size) |
252b5132 RH |
1219 | found = 0; |
1220 | } | |
7ee7b84d MS |
1221 | else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS |
1222 | || op_mode == INDEXB || op_mode == INDEXW | |
1223 | || op_mode == INDEXL) | |
1224 | && op_mode == x_mode) | |
252b5132 RH |
1225 | { |
1226 | /* Promote a L_24 to L_32 if it makes us match. */ | |
7ee7b84d | 1227 | if (x_size == L_24 && op_size == L_32) |
252b5132 | 1228 | { |
7ee7b84d MS |
1229 | x &= ~SIZE; |
1230 | x |= x_size = L_32; | |
252b5132 | 1231 | } |
7ee7b84d | 1232 | |
7ee7b84d | 1233 | if (((x_size == L_16 && op_size == L_16U) |
2d0d09ca | 1234 | || (x_size == L_8 && op_size == L_8U) |
7ee7b84d MS |
1235 | || (x_size == L_3 && op_size == L_3NZ)) |
1236 | /* We're deliberately more permissive for ABS modes. */ | |
1237 | && (op_mode == ABS | |
1238 | || constant_fits_size_p (operands + i, op_size, | |
1239 | op & NO_SYMBOLS))) | |
1240 | x_size = op_size; | |
1241 | ||
1242 | if (x_size != 0 && op_size != x_size) | |
1243 | found = 0; | |
1244 | else if (x_size == 0 | |
1245 | && ! constant_fits_size_p (operands + i, op_size, | |
1246 | op & NO_SYMBOLS)) | |
252b5132 RH |
1247 | found = 0; |
1248 | } | |
7ee7b84d | 1249 | else if (op_mode != x_mode) |
252b5132 RH |
1250 | { |
1251 | found = 0; | |
70d6ecf3 | 1252 | } |
252b5132 RH |
1253 | } |
1254 | } | |
7ee7b84d MS |
1255 | if (found) |
1256 | { | |
1257 | if ((this_try->opcode->available == AV_H8SX && ! SXmode) | |
d4ea8842 | 1258 | || (this_try->opcode->available == AV_H8S && ! Smode) |
7ee7b84d MS |
1259 | || (this_try->opcode->available == AV_H8H && ! Hmode)) |
1260 | found = 0, found_other = this_try; | |
1261 | else if (this_size != size && (this_size != SN && size != SN)) | |
1262 | found_mismatched = this_try, found = 0; | |
1263 | ||
1264 | } | |
252b5132 RH |
1265 | } |
1266 | if (found) | |
1267 | return this_try; | |
7ee7b84d MS |
1268 | if (found_other) |
1269 | { | |
1270 | as_warn (_("Opcode `%s' with these operand types not available in %s mode"), | |
1271 | found_other->opcode->name, | |
1272 | (! Hmode && ! Smode ? "H8/300" | |
1273 | : SXmode ? "H8sx" | |
1274 | : Smode ? "H8/300S" | |
1275 | : "H8/300H")); | |
1276 | } | |
1277 | else if (found_mismatched) | |
1278 | { | |
1279 | as_warn (_("mismatch between opcode size and operand size")); | |
1280 | return found_mismatched; | |
1281 | } | |
1282 | return 0; | |
252b5132 RH |
1283 | } |
1284 | ||
1285 | static void | |
b54a3392 | 1286 | check_operand (struct h8_op *operand, unsigned int width, char *string) |
252b5132 RH |
1287 | { |
1288 | if (operand->exp.X_add_symbol == 0 | |
1289 | && operand->exp.X_op_symbol == 0) | |
1290 | { | |
70d6ecf3 AM |
1291 | /* No symbol involved, let's look at offset, it's dangerous if |
1292 | any of the high bits are not 0 or ff's, find out by oring or | |
1293 | anding with the width and seeing if the answer is 0 or all | |
1294 | fs. */ | |
252b5132 | 1295 | |
7ee7b84d | 1296 | if (! constant_fits_width_p (operand, width)) |
252b5132 | 1297 | { |
70d6ecf3 | 1298 | if (width == 255 |
252b5132 RH |
1299 | && (operand->exp.X_add_number & 0xff00) == 0xff00) |
1300 | { | |
1301 | /* Just ignore this one - which happens when trying to | |
1302 | fit a 16 bit address truncated into an 8 bit address | |
1303 | of something like bset. */ | |
1304 | } | |
166e23f9 KH |
1305 | else if (strcmp (string, "@") == 0 |
1306 | && width == 0xffff | |
1307 | && (operand->exp.X_add_number & 0xff8000) == 0xff8000) | |
1308 | { | |
1309 | /* Just ignore this one - which happens when trying to | |
1310 | fit a 24 bit address truncated into a 16 bit address | |
1311 | of something like mov.w. */ | |
1312 | } | |
70d6ecf3 | 1313 | else |
252b5132 RH |
1314 | { |
1315 | as_warn (_("operand %s0x%lx out of range."), string, | |
1316 | (unsigned long) operand->exp.X_add_number); | |
1317 | } | |
1318 | } | |
1319 | } | |
252b5132 RH |
1320 | } |
1321 | ||
1322 | /* RELAXMODE has one of 3 values: | |
1323 | ||
1324 | 0 Output a "normal" reloc, no relaxing possible for this insn/reloc | |
1325 | ||
1326 | 1 Output a relaxable 24bit absolute mov.w address relocation | |
1327 | (may relax into a 16bit absolute address). | |
1328 | ||
1329 | 2 Output a relaxable 16/24 absolute mov.b address relocation | |
1330 | (may relax into an 8bit absolute address). */ | |
1331 | ||
1332 | static void | |
bcb012d3 | 1333 | do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode, const struct h8_instruction *this_try) |
252b5132 RH |
1334 | { |
1335 | int idx; | |
1336 | int size; | |
1337 | int where; | |
7ee7b84d | 1338 | char *bytes = frag_now->fr_literal + offset; |
252b5132 | 1339 | |
7ee7b84d | 1340 | char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; |
252b5132 RH |
1341 | |
1342 | if (operand->exp.X_add_symbol == 0) | |
1343 | { | |
252b5132 RH |
1344 | switch (operand->mode & SIZE) |
1345 | { | |
1346 | case L_2: | |
1347 | check_operand (operand, 0x3, t); | |
7ee7b84d | 1348 | bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4); |
252b5132 RH |
1349 | break; |
1350 | case L_3: | |
7ee7b84d | 1351 | case L_3NZ: |
252b5132 | 1352 | check_operand (operand, 0x7, t); |
7ee7b84d MS |
1353 | bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4); |
1354 | break; | |
1355 | case L_4: | |
1356 | check_operand (operand, 0xF, t); | |
1357 | bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4); | |
1358 | break; | |
1359 | case L_5: | |
1360 | check_operand (operand, 0x1F, t); | |
1361 | bytes[0] |= operand->exp.X_add_number & 31; | |
252b5132 RH |
1362 | break; |
1363 | case L_8: | |
7ee7b84d | 1364 | case L_8U: |
252b5132 | 1365 | check_operand (operand, 0xff, t); |
7ee7b84d | 1366 | bytes[0] |= operand->exp.X_add_number; |
252b5132 RH |
1367 | break; |
1368 | case L_16: | |
7ee7b84d | 1369 | case L_16U: |
252b5132 | 1370 | check_operand (operand, 0xffff, t); |
7ee7b84d MS |
1371 | bytes[0] |= operand->exp.X_add_number >> 8; |
1372 | bytes[1] |= operand->exp.X_add_number >> 0; | |
bcb012d3 DD |
1373 | #ifdef OBJ_ELF |
1374 | /* MOVA needs both relocs to relax the second operand properly. */ | |
1375 | if (relaxmode != 0 | |
1376 | && (OP_KIND(this_try->opcode->how) == O_MOVAB | |
1377 | || OP_KIND(this_try->opcode->how) == O_MOVAW | |
1378 | || OP_KIND(this_try->opcode->how) == O_MOVAL)) | |
1379 | { | |
1380 | idx = BFD_RELOC_16; | |
1381 | fix_new_exp (frag_now, offset, 2, &operand->exp, 0, idx); | |
1382 | } | |
1383 | #endif | |
252b5132 RH |
1384 | break; |
1385 | case L_24: | |
1386 | check_operand (operand, 0xffffff, t); | |
7ee7b84d MS |
1387 | bytes[0] |= operand->exp.X_add_number >> 16; |
1388 | bytes[1] |= operand->exp.X_add_number >> 8; | |
1389 | bytes[2] |= operand->exp.X_add_number >> 0; | |
252b5132 RH |
1390 | break; |
1391 | ||
1392 | case L_32: | |
70d6ecf3 | 1393 | /* This should be done with bfd. */ |
7ee7b84d MS |
1394 | bytes[0] |= operand->exp.X_add_number >> 24; |
1395 | bytes[1] |= operand->exp.X_add_number >> 16; | |
1396 | bytes[2] |= operand->exp.X_add_number >> 8; | |
1397 | bytes[3] |= operand->exp.X_add_number >> 0; | |
4132022d AM |
1398 | if (relaxmode != 0) |
1399 | { | |
1400 | idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1; | |
1401 | fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx); | |
1402 | } | |
252b5132 RH |
1403 | break; |
1404 | } | |
252b5132 RH |
1405 | } |
1406 | else | |
1407 | { | |
1408 | switch (operand->mode & SIZE) | |
1409 | { | |
252b5132 RH |
1410 | case L_24: |
1411 | case L_32: | |
1412 | size = 4; | |
1413 | where = (operand->mode & SIZE) == L_24 ? -1 : 0; | |
1414 | if (relaxmode == 2) | |
1415 | idx = R_MOV24B1; | |
1416 | else if (relaxmode == 1) | |
1417 | idx = R_MOVL1; | |
1418 | else | |
1419 | idx = R_RELLONG; | |
1420 | break; | |
1421 | default: | |
70d6ecf3 | 1422 | as_bad (_("Can't work out size of operand.\n")); |
252b5132 | 1423 | case L_16: |
7ee7b84d | 1424 | case L_16U: |
252b5132 RH |
1425 | size = 2; |
1426 | where = 0; | |
1427 | if (relaxmode == 2) | |
1428 | idx = R_MOV16B1; | |
1429 | else | |
1430 | idx = R_RELWORD; | |
4132022d AM |
1431 | operand->exp.X_add_number = |
1432 | ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
7ee7b84d | 1433 | operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1]; |
252b5132 RH |
1434 | break; |
1435 | case L_8: | |
1436 | size = 1; | |
1437 | where = 0; | |
1438 | idx = R_RELBYTE; | |
4132022d AM |
1439 | operand->exp.X_add_number = |
1440 | ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
7ee7b84d | 1441 | operand->exp.X_add_number |= bytes[0]; |
252b5132 RH |
1442 | } |
1443 | ||
1444 | fix_new_exp (frag_now, | |
1445 | offset + where, | |
1446 | size, | |
1447 | &operand->exp, | |
1448 | 0, | |
1449 | idx); | |
1450 | } | |
252b5132 RH |
1451 | } |
1452 | ||
70d6ecf3 | 1453 | /* Now we know what sort of opcodes it is, let's build the bytes. */ |
3048287a | 1454 | |
252b5132 | 1455 | static void |
b54a3392 | 1456 | build_bytes (const struct h8_instruction *this_try, struct h8_op *operand) |
252b5132 | 1457 | { |
3048287a | 1458 | int i; |
252b5132 | 1459 | char *output = frag_more (this_try->length); |
d1e50f8a | 1460 | const op_type *nibble_ptr = this_try->opcode->data.nib; |
252b5132 RH |
1461 | op_type c; |
1462 | unsigned int nibble_count = 0; | |
7ee7b84d | 1463 | int op_at[3]; |
3048287a | 1464 | int nib = 0; |
252b5132 | 1465 | int movb = 0; |
7ee7b84d | 1466 | char asnibbles[100]; |
252b5132 | 1467 | char *p = asnibbles; |
7ee7b84d | 1468 | int high, low; |
252b5132 | 1469 | |
d4ea8842 | 1470 | if (!Hmode && this_try->opcode->available != AV_H8) |
252b5132 | 1471 | as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"), |
a720f7bc | 1472 | this_try->opcode->name); |
d4ea8842 MS |
1473 | else if (!Smode |
1474 | && this_try->opcode->available != AV_H8 | |
1475 | && this_try->opcode->available != AV_H8H) | |
1476 | as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"), | |
1477 | this_try->opcode->name); | |
1478 | else if (!SXmode | |
1479 | && this_try->opcode->available != AV_H8 | |
1480 | && this_try->opcode->available != AV_H8H | |
1481 | && this_try->opcode->available != AV_H8S) | |
1482 | as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"), | |
1483 | this_try->opcode->name); | |
252b5132 | 1484 | |
7ee7b84d | 1485 | while (*nibble_ptr != (op_type) E) |
252b5132 RH |
1486 | { |
1487 | int d; | |
7ee7b84d MS |
1488 | |
1489 | nib = 0; | |
252b5132 RH |
1490 | c = *nibble_ptr++; |
1491 | ||
7ee7b84d | 1492 | d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0; |
252b5132 RH |
1493 | |
1494 | if (c < 16) | |
3048287a | 1495 | nib = c; |
252b5132 RH |
1496 | else |
1497 | { | |
7ee7b84d MS |
1498 | int c2 = c & MODE; |
1499 | ||
1500 | if (c2 == REG || c2 == LOWREG | |
1501 | || c2 == IND || c2 == PREINC || c2 == PREDEC | |
1502 | || c2 == POSTINC || c2 == POSTDEC) | |
1503 | { | |
1504 | nib = operand[d].reg; | |
1505 | if (c2 == LOWREG) | |
1506 | nib &= 7; | |
1507 | } | |
1508 | ||
1509 | else if (c & CTRL) /* Control reg operand. */ | |
3048287a NC |
1510 | nib = operand[d].reg; |
1511 | ||
252b5132 | 1512 | else if ((c & DISPREG) == (DISPREG)) |
7ee7b84d MS |
1513 | { |
1514 | nib = operand[d].reg; | |
1515 | } | |
1516 | else if (c2 == ABS) | |
252b5132 RH |
1517 | { |
1518 | operand[d].mode = c; | |
7ee7b84d | 1519 | op_at[d] = nibble_count; |
252b5132 RH |
1520 | nib = 0; |
1521 | } | |
7ee7b84d MS |
1522 | else if (c2 == IMM || c2 == PCREL || c2 == ABS |
1523 | || (c & ABSJMP) || c2 == DISP) | |
252b5132 RH |
1524 | { |
1525 | operand[d].mode = c; | |
7ee7b84d | 1526 | op_at[d] = nibble_count; |
252b5132 RH |
1527 | nib = 0; |
1528 | } | |
7ee7b84d | 1529 | else if ((c & IGNORE) || (c & DATA)) |
3048287a NC |
1530 | nib = 0; |
1531 | ||
7ee7b84d | 1532 | else if (c2 == DBIT) |
252b5132 RH |
1533 | { |
1534 | switch (operand[0].exp.X_add_number) | |
1535 | { | |
1536 | case 1: | |
1537 | nib = c; | |
1538 | break; | |
1539 | case 2: | |
1540 | nib = 0x8 | c; | |
1541 | break; | |
1542 | default: | |
1543 | as_bad (_("Need #1 or #2 here")); | |
1544 | } | |
1545 | } | |
7ee7b84d | 1546 | else if (c2 == KBIT) |
252b5132 RH |
1547 | { |
1548 | switch (operand[0].exp.X_add_number) | |
1549 | { | |
1550 | case 1: | |
1551 | nib = 0; | |
1552 | break; | |
1553 | case 2: | |
1554 | nib = 8; | |
1555 | break; | |
1556 | case 4: | |
1557 | if (!Hmode) | |
1558 | as_warn (_("#4 not valid on H8/300.")); | |
1559 | nib = 9; | |
1560 | break; | |
1561 | ||
1562 | default: | |
1563 | as_bad (_("Need #1 or #2 here")); | |
1564 | break; | |
1565 | } | |
70d6ecf3 | 1566 | /* Stop it making a fix. */ |
252b5132 RH |
1567 | operand[0].mode = 0; |
1568 | } | |
1569 | ||
1570 | if (c & MEMRELAX) | |
3048287a | 1571 | operand[d].mode |= MEMRELAX; |
252b5132 RH |
1572 | |
1573 | if (c & B31) | |
3048287a | 1574 | nib |= 0x8; |
252b5132 | 1575 | |
7ee7b84d MS |
1576 | if (c & B21) |
1577 | nib |= 0x4; | |
1578 | ||
1579 | if (c & B11) | |
1580 | nib |= 0x2; | |
1581 | ||
1582 | if (c & B01) | |
1583 | nib |= 0x1; | |
1584 | ||
1585 | if (c2 == MACREG) | |
252b5132 | 1586 | { |
f0c56b90 NC |
1587 | if (operand[0].mode == MACREG) |
1588 | /* stmac has mac[hl] as the first operand. */ | |
1589 | nib = 2 + operand[0].reg; | |
1590 | else | |
1591 | /* ldmac has mac[hl] as the second operand. */ | |
1592 | nib = 2 + operand[1].reg; | |
252b5132 RH |
1593 | } |
1594 | } | |
1595 | nibble_count++; | |
1596 | ||
1597 | *p++ = nib; | |
1598 | } | |
1599 | ||
1600 | /* Disgusting. Why, oh why didn't someone ask us for advice | |
1601 | on the assembler format. */ | |
7ee7b84d | 1602 | if (OP_KIND (this_try->opcode->how) == O_LDM) |
252b5132 | 1603 | { |
7ee7b84d MS |
1604 | high = (operand[1].reg >> 8) & 0xf; |
1605 | low = (operand[1].reg) & 0xf; | |
252b5132 | 1606 | asnibbles[2] = high - low; |
7ee7b84d MS |
1607 | asnibbles[7] = high; |
1608 | } | |
1609 | else if (OP_KIND (this_try->opcode->how) == O_STM) | |
1610 | { | |
1611 | high = (operand[0].reg >> 8) & 0xf; | |
1612 | low = (operand[0].reg) & 0xf; | |
1613 | asnibbles[2] = high - low; | |
1614 | asnibbles[7] = low; | |
252b5132 RH |
1615 | } |
1616 | ||
1617 | for (i = 0; i < this_try->length; i++) | |
3048287a | 1618 | output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1]; |
252b5132 | 1619 | |
ca9a79a1 NC |
1620 | /* Note if this is a movb or a bit manipulation instruction |
1621 | there is a special relaxation which only applies. */ | |
1622 | if ( this_try->opcode->how == O (O_MOV, SB) | |
1623 | || this_try->opcode->how == O (O_BCLR, SB) | |
1624 | || this_try->opcode->how == O (O_BAND, SB) | |
1625 | || this_try->opcode->how == O (O_BIAND, SB) | |
1626 | || this_try->opcode->how == O (O_BILD, SB) | |
1627 | || this_try->opcode->how == O (O_BIOR, SB) | |
1628 | || this_try->opcode->how == O (O_BIST, SB) | |
1629 | || this_try->opcode->how == O (O_BIXOR, SB) | |
1630 | || this_try->opcode->how == O (O_BLD, SB) | |
1631 | || this_try->opcode->how == O (O_BNOT, SB) | |
1632 | || this_try->opcode->how == O (O_BOR, SB) | |
1633 | || this_try->opcode->how == O (O_BSET, SB) | |
1634 | || this_try->opcode->how == O (O_BST, SB) | |
1635 | || this_try->opcode->how == O (O_BTST, SB) | |
1636 | || this_try->opcode->how == O (O_BXOR, SB)) | |
252b5132 RH |
1637 | movb = 1; |
1638 | ||
70d6ecf3 | 1639 | /* Output any fixes. */ |
7ee7b84d | 1640 | for (i = 0; i < this_try->noperands; i++) |
252b5132 RH |
1641 | { |
1642 | int x = operand[i].mode; | |
7ee7b84d | 1643 | int x_mode = x & MODE; |
252b5132 | 1644 | |
7ee7b84d MS |
1645 | if (x_mode == IMM || x_mode == DISP) |
1646 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, | |
bcb012d3 DD |
1647 | op_at[i] & 1, operand + i, (x & MEMRELAX) != 0, |
1648 | this_try); | |
3048287a | 1649 | |
7ee7b84d MS |
1650 | else if (x_mode == ABS) |
1651 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, | |
1652 | op_at[i] & 1, operand + i, | |
bcb012d3 DD |
1653 | (x & MEMRELAX) ? movb + 1 : 0, |
1654 | this_try); | |
3048287a | 1655 | |
7ee7b84d | 1656 | else if (x_mode == PCREL) |
252b5132 | 1657 | { |
7ee7b84d | 1658 | int size16 = (x & SIZE) == L_16; |
252b5132 RH |
1659 | int size = size16 ? 2 : 1; |
1660 | int type = size16 ? R_PCRWORD : R_PCRBYTE; | |
36ed2fff | 1661 | fixS *fixP; |
252b5132 RH |
1662 | |
1663 | check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@"); | |
1664 | ||
1665 | if (operand[i].exp.X_add_number & 1) | |
3048287a NC |
1666 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1667 | (unsigned long) operand->exp.X_add_number); | |
36ed2fff JL |
1668 | #ifndef OBJ_ELF |
1669 | /* The COFF port has always been off by one, changing it | |
1670 | now would be an incompatible change, so we leave it as-is. | |
1671 | ||
1672 | We don't want to do this for ELF as we want to be | |
1673 | compatible with the proposed ELF format from Hitachi. */ | |
252b5132 | 1674 | operand[i].exp.X_add_number -= 1; |
36ed2fff | 1675 | #endif |
7ee7b84d MS |
1676 | if (size16) |
1677 | { | |
1678 | operand[i].exp.X_add_number = | |
1679 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
1680 | } | |
1681 | else | |
1682 | { | |
1683 | operand[i].exp.X_add_number = | |
1684 | ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
1685 | } | |
1686 | ||
1687 | /* For BRA/S. */ | |
1688 | if (! size16) | |
1689 | operand[i].exp.X_add_number |= output[op_at[i] / 2]; | |
252b5132 | 1690 | |
36ed2fff | 1691 | fixP = fix_new_exp (frag_now, |
7ee7b84d | 1692 | output - frag_now->fr_literal + op_at[i] / 2, |
36ed2fff JL |
1693 | size, |
1694 | &operand[i].exp, | |
1695 | 1, | |
1696 | type); | |
1697 | fixP->fx_signed = 1; | |
252b5132 | 1698 | } |
7ee7b84d | 1699 | else if (x_mode == MEMIND) |
252b5132 | 1700 | { |
252b5132 RH |
1701 | check_operand (operand + i, 0xff, "@@"); |
1702 | fix_new_exp (frag_now, | |
1703 | output - frag_now->fr_literal + 1, | |
1704 | 1, | |
1705 | &operand[i].exp, | |
1706 | 0, | |
1707 | R_MEM_INDIRECT); | |
1708 | } | |
7ee7b84d MS |
1709 | else if (x_mode == VECIND) |
1710 | { | |
1711 | check_operand (operand + i, 0x7f, "@@"); | |
1712 | /* FIXME: approximating the effect of "B31" here... | |
1713 | This is very hackish, and ought to be done a better way. */ | |
1714 | operand[i].exp.X_add_number |= 0x80; | |
1715 | fix_new_exp (frag_now, | |
1716 | output - frag_now->fr_literal + 1, | |
1717 | 1, | |
1718 | &operand[i].exp, | |
1719 | 0, | |
1720 | R_MEM_INDIRECT); | |
1721 | } | |
252b5132 RH |
1722 | else if (x & ABSJMP) |
1723 | { | |
3c1ba8a3 | 1724 | int where = 0; |
7ee7b84d | 1725 | bfd_reloc_code_real_type reloc_type = R_JMPL1; |
3c1ba8a3 JL |
1726 | |
1727 | #ifdef OBJ_ELF | |
1728 | /* To be compatible with the proposed H8 ELF format, we | |
1729 | want the relocation's offset to point to the first byte | |
1730 | that will be modified, not to the start of the instruction. */ | |
7ee7b84d MS |
1731 | |
1732 | if ((operand->mode & SIZE) == L_32) | |
1733 | { | |
1734 | where = 2; | |
1735 | reloc_type = R_RELLONG; | |
1736 | } | |
1737 | else | |
1738 | where = 1; | |
3c1ba8a3 | 1739 | #endif |
de342d07 | 1740 | |
70d6ecf3 | 1741 | /* This jmp may be a jump or a branch. */ |
252b5132 | 1742 | |
7ee7b84d MS |
1743 | check_operand (operand + i, |
1744 | SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff, | |
1745 | "@"); | |
3048287a | 1746 | |
252b5132 | 1747 | if (operand[i].exp.X_add_number & 1) |
3048287a NC |
1748 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1749 | (unsigned long) operand->exp.X_add_number); | |
1750 | ||
252b5132 | 1751 | if (!Hmode) |
70d6ecf3 | 1752 | operand[i].exp.X_add_number = |
4132022d | 1753 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; |
252b5132 | 1754 | fix_new_exp (frag_now, |
3c1ba8a3 | 1755 | output - frag_now->fr_literal + where, |
252b5132 RH |
1756 | 4, |
1757 | &operand[i].exp, | |
1758 | 0, | |
7ee7b84d | 1759 | reloc_type); |
252b5132 RH |
1760 | } |
1761 | } | |
252b5132 RH |
1762 | } |
1763 | ||
70d6ecf3 AM |
1764 | /* Try to give an intelligent error message for common and simple to |
1765 | detect errors. */ | |
3048287a | 1766 | |
252b5132 | 1767 | static void |
b54a3392 KH |
1768 | clever_message (const struct h8_instruction *instruction, |
1769 | struct h8_op *operand) | |
252b5132 | 1770 | { |
70d6ecf3 | 1771 | /* Find out if there was more than one possible opcode. */ |
252b5132 | 1772 | |
a720f7bc | 1773 | if ((instruction + 1)->idx != instruction->idx) |
252b5132 | 1774 | { |
3048287a | 1775 | int argn; |
252b5132 | 1776 | |
70d6ecf3 AM |
1777 | /* Only one opcode of this flavour, try to guess which operand |
1778 | didn't match. */ | |
a720f7bc | 1779 | for (argn = 0; argn < instruction->noperands; argn++) |
252b5132 | 1780 | { |
a720f7bc | 1781 | switch (instruction->opcode->args.nib[argn]) |
252b5132 RH |
1782 | { |
1783 | case RD16: | |
1784 | if (operand[argn].mode != RD16) | |
1785 | { | |
1786 | as_bad (_("destination operand must be 16 bit register")); | |
1787 | return; | |
1788 | ||
1789 | } | |
1790 | break; | |
1791 | ||
1792 | case RS8: | |
252b5132 RH |
1793 | if (operand[argn].mode != RS8) |
1794 | { | |
1795 | as_bad (_("source operand must be 8 bit register")); | |
1796 | return; | |
1797 | } | |
1798 | break; | |
1799 | ||
1800 | case ABS16DST: | |
1801 | if (operand[argn].mode != ABS16DST) | |
1802 | { | |
1803 | as_bad (_("destination operand must be 16bit absolute address")); | |
1804 | return; | |
1805 | } | |
1806 | break; | |
1807 | case RD8: | |
1808 | if (operand[argn].mode != RD8) | |
1809 | { | |
1810 | as_bad (_("destination operand must be 8 bit register")); | |
1811 | return; | |
1812 | } | |
1813 | break; | |
1814 | ||
252b5132 RH |
1815 | case ABS16SRC: |
1816 | if (operand[argn].mode != ABS16SRC) | |
1817 | { | |
1818 | as_bad (_("source operand must be 16bit absolute address")); | |
1819 | return; | |
1820 | } | |
1821 | break; | |
1822 | ||
1823 | } | |
1824 | } | |
1825 | } | |
1826 | as_bad (_("invalid operands")); | |
1827 | } | |
1828 | ||
d4ea8842 | 1829 | |
1b680e4f RS |
1830 | /* If OPERAND is part of an address, adjust its size and value given |
1831 | that it addresses SIZE bytes. | |
d4ea8842 | 1832 | |
1b680e4f RS |
1833 | This function decides how big non-immediate constants are when no |
1834 | size was explicitly given. It also scales down the assembly-level | |
d4ea8842 MS |
1835 | displacement in an @(d:2,ERn) operand. */ |
1836 | ||
1837 | static void | |
b54a3392 | 1838 | fix_operand_size (struct h8_op *operand, int size) |
d4ea8842 | 1839 | { |
1b680e4f | 1840 | if (SXmode && (operand->mode & MODE) == DISP) |
d4ea8842 MS |
1841 | { |
1842 | /* If the user didn't specify an operand width, see if we | |
1843 | can use @(d:2,ERn). */ | |
1b680e4f RS |
1844 | if ((operand->mode & SIZE) == 0 |
1845 | && operand->exp.X_add_symbol == 0 | |
1846 | && operand->exp.X_op_symbol == 0 | |
d4ea8842 MS |
1847 | && (operand->exp.X_add_number == size |
1848 | || operand->exp.X_add_number == size * 2 | |
1849 | || operand->exp.X_add_number == size * 3)) | |
1850 | operand->mode |= L_2; | |
1851 | ||
1852 | /* Scale down the displacement in an @(d:2,ERn) operand. | |
1853 | X_add_number then contains the desired field value. */ | |
1854 | if ((operand->mode & SIZE) == L_2) | |
1855 | { | |
1856 | if (operand->exp.X_add_number % size != 0) | |
1857 | as_warn (_("operand/size mis-match")); | |
1858 | operand->exp.X_add_number /= size; | |
1859 | } | |
1860 | } | |
1861 | ||
d4ea8842 MS |
1862 | if ((operand->mode & SIZE) == 0) |
1863 | switch (operand->mode & MODE) | |
1864 | { | |
1865 | case DISP: | |
1866 | case INDEXB: | |
1867 | case INDEXW: | |
1868 | case INDEXL: | |
1869 | case ABS: | |
1b680e4f RS |
1870 | /* Pick a 24-bit address unless we know that a 16-bit address |
1871 | is safe. get_specific() will relax L_24 into L_32 where | |
1872 | necessary. */ | |
1873 | if (Hmode | |
d4e2de6b | 1874 | && !Nmode |
35a35807 AM |
1875 | && ((((addressT) operand->exp.X_add_number + 0x8000) |
1876 | & 0xffffffff) > 0xffff | |
1b680e4f RS |
1877 | || operand->exp.X_add_symbol != 0 |
1878 | || operand->exp.X_op_symbol != 0)) | |
1879 | operand->mode |= L_24; | |
1880 | else | |
1881 | operand->mode |= L_16; | |
1882 | break; | |
1883 | ||
1884 | case PCREL: | |
35a35807 AM |
1885 | if ((((addressT) operand->exp.X_add_number + 0x80) |
1886 | & 0xffffffff) <= 0xff) | |
cc189afc DD |
1887 | { |
1888 | if (operand->exp.X_add_symbol != NULL) | |
1889 | operand->mode |= bsize; | |
1890 | else | |
1891 | operand->mode |= L_8; | |
1892 | } | |
1b680e4f RS |
1893 | else |
1894 | operand->mode |= L_16; | |
d4ea8842 MS |
1895 | break; |
1896 | } | |
1897 | } | |
1898 | ||
1899 | ||
70d6ecf3 AM |
1900 | /* This is the guts of the machine-dependent assembler. STR points to |
1901 | a machine dependent instruction. This function is supposed to emit | |
1902 | the frags/bytes it assembles. */ | |
3048287a | 1903 | |
252b5132 | 1904 | void |
b54a3392 | 1905 | md_assemble (char *str) |
252b5132 RH |
1906 | { |
1907 | char *op_start; | |
1908 | char *op_end; | |
7ee7b84d | 1909 | struct h8_op operand[3]; |
a720f7bc KD |
1910 | const struct h8_instruction *instruction; |
1911 | const struct h8_instruction *prev_instruction; | |
252b5132 RH |
1912 | |
1913 | char *dot = 0; | |
0c0b9be0 | 1914 | char *slash = 0; |
252b5132 | 1915 | char c; |
7ee7b84d | 1916 | int size, i; |
252b5132 | 1917 | |
70d6ecf3 | 1918 | /* Drop leading whitespace. */ |
252b5132 RH |
1919 | while (*str == ' ') |
1920 | str++; | |
1921 | ||
70d6ecf3 | 1922 | /* Find the op code end. */ |
252b5132 RH |
1923 | for (op_start = op_end = str; |
1924 | *op_end != 0 && *op_end != ' '; | |
1925 | op_end++) | |
1926 | { | |
1927 | if (*op_end == '.') | |
1928 | { | |
1929 | dot = op_end + 1; | |
1930 | *op_end = 0; | |
1931 | op_end += 2; | |
1932 | break; | |
1933 | } | |
0c0b9be0 AO |
1934 | else if (*op_end == '/' && ! slash) |
1935 | slash = op_end; | |
252b5132 RH |
1936 | } |
1937 | ||
252b5132 RH |
1938 | if (op_end == op_start) |
1939 | { | |
1940 | as_bad (_("can't find opcode ")); | |
1941 | } | |
1942 | c = *op_end; | |
1943 | ||
1944 | *op_end = 0; | |
1945 | ||
0c0b9be0 AO |
1946 | /* The assembler stops scanning the opcode at slashes, so it fails |
1947 | to make characters following them lower case. Fix them. */ | |
1948 | if (slash) | |
1949 | while (*++slash) | |
1950 | *slash = TOLOWER (*slash); | |
1951 | ||
a720f7bc KD |
1952 | instruction = (const struct h8_instruction *) |
1953 | hash_find (opcode_hash_control, op_start); | |
252b5132 | 1954 | |
a720f7bc | 1955 | if (instruction == NULL) |
252b5132 RH |
1956 | { |
1957 | as_bad (_("unknown opcode")); | |
1958 | return; | |
1959 | } | |
1960 | ||
70d6ecf3 | 1961 | /* We used to set input_line_pointer to the result of get_operands, |
252b5132 RH |
1962 | but that is wrong. Our caller assumes we don't change it. */ |
1963 | ||
7ee7b84d MS |
1964 | operand[0].mode = 0; |
1965 | operand[1].mode = 0; | |
1966 | operand[2].mode = 0; | |
1967 | ||
1968 | if (OP_KIND (instruction->opcode->how) == O_MOVAB | |
1969 | || OP_KIND (instruction->opcode->how) == O_MOVAW | |
1970 | || OP_KIND (instruction->opcode->how) == O_MOVAL) | |
1971 | get_mova_operands (op_end, operand); | |
1972 | else if (OP_KIND (instruction->opcode->how) == O_RTEL | |
1973 | || OP_KIND (instruction->opcode->how) == O_RTSL) | |
1974 | get_rtsl_operands (op_end, operand); | |
1975 | else | |
1976 | get_operands (instruction->noperands, op_end, operand); | |
1977 | ||
252b5132 | 1978 | *op_end = c; |
a720f7bc | 1979 | prev_instruction = instruction; |
252b5132 | 1980 | |
4892e510 NC |
1981 | /* Now we have operands from instruction. |
1982 | Let's check them out for ldm and stm. */ | |
1983 | if (OP_KIND (instruction->opcode->how) == O_LDM) | |
1984 | { | |
1985 | /* The first operand must be @er7+, and the | |
1986 | second operand must be a register pair. */ | |
1987 | if ((operand[0].mode != RSINC) | |
1988 | || (operand[0].reg != 7) | |
1989 | || ((operand[1].reg & 0x80000000) == 0)) | |
1990 | as_bad (_("invalid operand in ldm")); | |
1991 | } | |
1992 | else if (OP_KIND (instruction->opcode->how) == O_STM) | |
1993 | { | |
1994 | /* The first operand must be a register pair, | |
1995 | and the second operand must be @-er7. */ | |
1996 | if (((operand[0].reg & 0x80000000) == 0) | |
1997 | || (operand[1].mode != RDDEC) | |
1998 | || (operand[1].reg != 7)) | |
1999 | as_bad (_("invalid operand in stm")); | |
2000 | } | |
2001 | ||
252b5132 RH |
2002 | size = SN; |
2003 | if (dot) | |
2004 | { | |
0c0b9be0 | 2005 | switch (TOLOWER (*dot)) |
252b5132 RH |
2006 | { |
2007 | case 'b': | |
2008 | size = SB; | |
2009 | break; | |
2010 | ||
2011 | case 'w': | |
2012 | size = SW; | |
2013 | break; | |
2014 | ||
2015 | case 'l': | |
2016 | size = SL; | |
2017 | break; | |
2018 | } | |
2019 | } | |
7ee7b84d MS |
2020 | if (OP_KIND (instruction->opcode->how) == O_MOVAB || |
2021 | OP_KIND (instruction->opcode->how) == O_MOVAW || | |
2022 | OP_KIND (instruction->opcode->how) == O_MOVAL) | |
252b5132 | 2023 | { |
d4ea8842 MS |
2024 | switch (operand[0].mode & MODE) |
2025 | { | |
7ee7b84d MS |
2026 | case INDEXB: |
2027 | default: | |
d4ea8842 | 2028 | fix_operand_size (&operand[1], 1); |
7ee7b84d MS |
2029 | break; |
2030 | case INDEXW: | |
d4ea8842 | 2031 | fix_operand_size (&operand[1], 2); |
7ee7b84d MS |
2032 | break; |
2033 | case INDEXL: | |
d4ea8842 | 2034 | fix_operand_size (&operand[1], 4); |
7ee7b84d | 2035 | break; |
252b5132 RH |
2036 | } |
2037 | } | |
7ee7b84d MS |
2038 | else |
2039 | { | |
d4ea8842 MS |
2040 | for (i = 0; i < 3 && operand[i].mode != 0; i++) |
2041 | switch (size) | |
2042 | { | |
7ee7b84d MS |
2043 | case SN: |
2044 | case SB: | |
2045 | default: | |
d4ea8842 | 2046 | fix_operand_size (&operand[i], 1); |
7ee7b84d MS |
2047 | break; |
2048 | case SW: | |
d4ea8842 | 2049 | fix_operand_size (&operand[i], 2); |
7ee7b84d MS |
2050 | break; |
2051 | case SL: | |
d4ea8842 | 2052 | fix_operand_size (&operand[i], 4); |
7ee7b84d MS |
2053 | break; |
2054 | } | |
2055 | } | |
252b5132 | 2056 | |
d4ea8842 MS |
2057 | instruction = get_specific (instruction, operand, size); |
2058 | ||
2059 | if (instruction == 0) | |
2060 | { | |
2061 | /* Couldn't find an opcode which matched the operands. */ | |
2062 | char *where = frag_more (2); | |
2063 | ||
2064 | where[0] = 0x0; | |
2065 | where[1] = 0x0; | |
2066 | clever_message (prev_instruction, operand); | |
2067 | ||
2068 | return; | |
2069 | } | |
2070 | ||
a720f7bc | 2071 | build_bytes (instruction, operand); |
2c8714f2 | 2072 | |
2c8714f2 | 2073 | dwarf2_emit_insn (instruction->length); |
252b5132 RH |
2074 | } |
2075 | ||
2076 | symbolS * | |
b54a3392 | 2077 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
2078 | { |
2079 | return 0; | |
2080 | } | |
2081 | ||
499ac353 | 2082 | /* Various routines to kill one day. */ |
bc0d738a | 2083 | |
252b5132 | 2084 | char * |
b54a3392 | 2085 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 2086 | { |
499ac353 | 2087 | return ieee_md_atof (type, litP, sizeP, TRUE); |
252b5132 RH |
2088 | } |
2089 | \f | |
6fd4f6cc DD |
2090 | #define OPTION_H_TICK_HEX (OPTION_MD_BASE) |
2091 | ||
5a38dc70 | 2092 | const char *md_shortopts = ""; |
252b5132 | 2093 | struct option md_longopts[] = { |
6fd4f6cc | 2094 | { "h-tick-hex", no_argument, NULL, OPTION_H_TICK_HEX }, |
252b5132 RH |
2095 | {NULL, no_argument, NULL, 0} |
2096 | }; | |
70d6ecf3 AM |
2097 | |
2098 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
2099 | |
2100 | int | |
b54a3392 | 2101 | md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED) |
252b5132 | 2102 | { |
6fd4f6cc DD |
2103 | switch (c) |
2104 | { | |
2105 | case OPTION_H_TICK_HEX: | |
2106 | enable_h_tick_hex = 1; | |
2107 | break; | |
2108 | ||
2109 | default: | |
2110 | return 0; | |
2111 | } | |
2112 | return 1; | |
252b5132 RH |
2113 | } |
2114 | ||
2115 | void | |
b54a3392 | 2116 | md_show_usage (FILE *stream ATTRIBUTE_UNUSED) |
252b5132 RH |
2117 | { |
2118 | } | |
2119 | \f | |
b54a3392 | 2120 | void tc_aout_fix_to_chars (void); |
3048287a | 2121 | |
252b5132 | 2122 | void |
b54a3392 | 2123 | tc_aout_fix_to_chars (void) |
252b5132 RH |
2124 | { |
2125 | printf (_("call to tc_aout_fix_to_chars \n")); | |
2126 | abort (); | |
2127 | } | |
2128 | ||
2129 | void | |
7be1c489 | 2130 | md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, |
b54a3392 KH |
2131 | segT seg ATTRIBUTE_UNUSED, |
2132 | fragS *fragP ATTRIBUTE_UNUSED) | |
252b5132 RH |
2133 | { |
2134 | printf (_("call to md_convert_frag \n")); | |
2135 | abort (); | |
2136 | } | |
2137 | ||
3c1ba8a3 | 2138 | valueT |
b54a3392 | 2139 | md_section_align (segT segment, valueT size) |
3c1ba8a3 JL |
2140 | { |
2141 | int align = bfd_get_section_alignment (stdoutput, segment); | |
2142 | return ((size + (1 << align) - 1) & (-1 << align)); | |
2143 | } | |
252b5132 RH |
2144 | |
2145 | void | |
55cf6793 | 2146 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 RH |
2147 | { |
2148 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
a161fe53 | 2149 | long val = *valP; |
252b5132 RH |
2150 | |
2151 | switch (fixP->fx_size) | |
2152 | { | |
2153 | case 1: | |
2154 | *buf++ = val; | |
2155 | break; | |
2156 | case 2: | |
2157 | *buf++ = (val >> 8); | |
2158 | *buf++ = val; | |
2159 | break; | |
2160 | case 4: | |
2161 | *buf++ = (val >> 24); | |
2162 | *buf++ = (val >> 16); | |
2163 | *buf++ = (val >> 8); | |
2164 | *buf++ = val; | |
2165 | break; | |
550c1888 NC |
2166 | case 8: |
2167 | /* This can arise when the .quad or .8byte pseudo-ops are used. | |
2168 | Returning here (without setting fx_done) will cause the code | |
2169 | to attempt to generate a reloc which will then fail with the | |
2170 | slightly more helpful error message: "Cannot represent | |
2171 | relocation type BFD_RELOC_64". */ | |
2172 | return; | |
252b5132 RH |
2173 | default: |
2174 | abort (); | |
2175 | } | |
94f592af NC |
2176 | |
2177 | if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) | |
2178 | fixP->fx_done = 1; | |
252b5132 RH |
2179 | } |
2180 | ||
2181 | int | |
c85dd50d NC |
2182 | md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, |
2183 | segT segment_type ATTRIBUTE_UNUSED) | |
252b5132 | 2184 | { |
c85dd50d | 2185 | printf (_("call to md_estimate_size_before_relax \n")); |
252b5132 RH |
2186 | abort (); |
2187 | } | |
2188 | ||
70d6ecf3 | 2189 | /* Put number into target byte order. */ |
252b5132 | 2190 | void |
b54a3392 | 2191 | md_number_to_chars (char *ptr, valueT use, int nbytes) |
252b5132 RH |
2192 | { |
2193 | number_to_chars_bigendian (ptr, use, nbytes); | |
2194 | } | |
70d6ecf3 | 2195 | |
252b5132 | 2196 | long |
52b010e4 | 2197 | md_pcrel_from (fixS *fixp) |
252b5132 | 2198 | { |
52b010e4 NC |
2199 | as_bad_where (fixp->fx_file, fixp->fx_line, |
2200 | _("Unexpected reference to a symbol in a non-code section")); | |
2201 | return 0; | |
252b5132 RH |
2202 | } |
2203 | ||
f333765f | 2204 | arelent * |
b54a3392 | 2205 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
f333765f JL |
2206 | { |
2207 | arelent *rel; | |
2208 | bfd_reloc_code_real_type r_type; | |
2209 | ||
de342d07 JL |
2210 | if (fixp->fx_addsy && fixp->fx_subsy) |
2211 | { | |
2212 | if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy)) | |
2213 | || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section) | |
2214 | { | |
2215 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
c85dd50d | 2216 | _("Difference of symbols in different sections is not supported")); |
de342d07 JL |
2217 | return NULL; |
2218 | } | |
2219 | } | |
2220 | ||
c85dd50d NC |
2221 | rel = xmalloc (sizeof (arelent)); |
2222 | rel->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); | |
f333765f JL |
2223 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
2224 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
2225 | rel->addend = fixp->fx_offset; | |
2226 | ||
2227 | r_type = fixp->fx_r_type; | |
2228 | ||
2229 | #define DEBUG 0 | |
2230 | #if DEBUG | |
2231 | fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type)); | |
c85dd50d | 2232 | fflush (stderr); |
f333765f JL |
2233 | #endif |
2234 | rel->howto = bfd_reloc_type_lookup (stdoutput, r_type); | |
2235 | if (rel->howto == NULL) | |
2236 | { | |
2237 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
2238 | _("Cannot represent relocation type %s"), | |
2239 | bfd_get_reloc_code_name (r_type)); | |
2240 | return NULL; | |
2241 | } | |
2242 | ||
2243 | return rel; | |
2244 | } |