Commit | Line | Data |
---|---|---|
c2dcd04e | 1 | /* tc-h8300.c -- Assemble code for the Renesas H8/300 |
cc8a6dd0 | 2 | Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, |
aa820537 AM |
3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
4 | Free Software Foundation, Inc. | |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 | 22 | |
bc0d738a | 23 | /* Written By Steve Chamberlain <sac@cygnus.com>. */ |
252b5132 | 24 | |
252b5132 RH |
25 | #include "as.h" |
26 | #include "subsegs.h" | |
2c8714f2 | 27 | #include "dwarf2dbg.h" |
2c8714f2 | 28 | |
252b5132 RH |
29 | #define DEFINE_TABLE |
30 | #define h8_opcodes ops | |
31 | #include "opcode/h8300.h" | |
3882b010 | 32 | #include "safe-ctype.h" |
252b5132 | 33 | |
7e0de7bf JL |
34 | #ifdef OBJ_ELF |
35 | #include "elf/h8.h" | |
7e0de7bf JL |
36 | #endif |
37 | ||
63a0b638 | 38 | const char comment_chars[] = ";"; |
252b5132 | 39 | const char line_comment_chars[] = "#"; |
63a0b638 | 40 | const char line_separator_chars[] = ""; |
252b5132 | 41 | |
600e9c99 KH |
42 | static void sbranch (int); |
43 | static void h8300hmode (int); | |
44 | static void h8300smode (int); | |
45 | static void h8300hnmode (int); | |
46 | static void h8300snmode (int); | |
47 | static void h8300sxmode (int); | |
48 | static void h8300sxnmode (int); | |
b54a3392 | 49 | static void pint (int); |
252b5132 | 50 | |
66faad26 KH |
51 | int Hmode; |
52 | int Smode; | |
53 | int Nmode; | |
54 | int SXmode; | |
3048287a | 55 | |
d4e2de6b | 56 | #define PSIZE (Hmode && !Nmode ? L_32 : L_16) |
3048287a | 57 | |
600e9c99 | 58 | static int bsize = L_8; /* Default branch displacement. */ |
252b5132 | 59 | |
a720f7bc KD |
60 | struct h8_instruction |
61 | { | |
62 | int length; | |
63 | int noperands; | |
64 | int idx; | |
65 | int size; | |
66 | const struct h8_opcode *opcode; | |
67 | }; | |
68 | ||
600e9c99 | 69 | static struct h8_instruction *h8_instructions; |
a720f7bc | 70 | |
600e9c99 | 71 | static void |
b54a3392 | 72 | h8300hmode (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
73 | { |
74 | Hmode = 1; | |
75 | Smode = 0; | |
83e20b45 JL |
76 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h)) |
77 | as_warn (_("could not set architecture and machine")); | |
252b5132 RH |
78 | } |
79 | ||
600e9c99 | 80 | static void |
b54a3392 | 81 | h8300smode (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
82 | { |
83 | Smode = 1; | |
84 | Hmode = 1; | |
83e20b45 JL |
85 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s)) |
86 | as_warn (_("could not set architecture and machine")); | |
252b5132 | 87 | } |
70d6ecf3 | 88 | |
600e9c99 | 89 | static void |
b54a3392 | 90 | h8300hnmode (int arg ATTRIBUTE_UNUSED) |
8d9cd6b1 NC |
91 | { |
92 | Hmode = 1; | |
93 | Smode = 0; | |
94 | Nmode = 1; | |
8d9cd6b1 NC |
95 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn)) |
96 | as_warn (_("could not set architecture and machine")); | |
8d9cd6b1 NC |
97 | } |
98 | ||
600e9c99 | 99 | static void |
b54a3392 | 100 | h8300snmode (int arg ATTRIBUTE_UNUSED) |
8d9cd6b1 NC |
101 | { |
102 | Smode = 1; | |
103 | Hmode = 1; | |
104 | Nmode = 1; | |
8d9cd6b1 NC |
105 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn)) |
106 | as_warn (_("could not set architecture and machine")); | |
8d9cd6b1 NC |
107 | } |
108 | ||
600e9c99 | 109 | static void |
b54a3392 | 110 | h8300sxmode (int arg ATTRIBUTE_UNUSED) |
7ee7b84d MS |
111 | { |
112 | Smode = 1; | |
113 | Hmode = 1; | |
114 | SXmode = 1; | |
7ee7b84d MS |
115 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx)) |
116 | as_warn (_("could not set architecture and machine")); | |
7ee7b84d MS |
117 | } |
118 | ||
600e9c99 | 119 | static void |
b54a3392 | 120 | h8300sxnmode (int arg ATTRIBUTE_UNUSED) |
f4984206 RS |
121 | { |
122 | Smode = 1; | |
123 | Hmode = 1; | |
124 | SXmode = 1; | |
125 | Nmode = 1; | |
f4984206 RS |
126 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn)) |
127 | as_warn (_("could not set architecture and machine")); | |
f4984206 RS |
128 | } |
129 | ||
600e9c99 | 130 | static void |
b54a3392 | 131 | sbranch (int size) |
252b5132 RH |
132 | { |
133 | bsize = size; | |
134 | } | |
135 | ||
70d6ecf3 | 136 | static void |
b54a3392 | 137 | pint (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
138 | { |
139 | cons (Hmode ? 4 : 2); | |
140 | } | |
141 | ||
52b010e4 NC |
142 | /* Like obj_elf_section, but issues a warning for new |
143 | sections which do not have an attribute specification. */ | |
144 | ||
145 | static void | |
146 | h8300_elf_section (int push) | |
147 | { | |
148 | static const char * known_data_sections [] = { ".rodata", ".tdata", ".tbss" }; | |
9c8b3bfe | 149 | static const char * known_data_prefixes [] = { ".debug", ".zdebug", ".gnu.warning" }; |
52b010e4 NC |
150 | char * saved_ilp = input_line_pointer; |
151 | char * name; | |
152 | ||
153 | name = obj_elf_section_name (); | |
154 | if (name == NULL) | |
155 | return; | |
156 | ||
157 | if (* input_line_pointer != ',' | |
158 | && bfd_get_section_by_name (stdoutput, name) == NULL) | |
159 | { | |
160 | signed int i; | |
161 | ||
162 | /* Ignore this warning for well known data sections. */ | |
163 | for (i = ARRAY_SIZE (known_data_sections); i--;) | |
164 | if (strcmp (name, known_data_sections[i]) == 0) | |
165 | break; | |
166 | ||
167 | if (i < 0) | |
168 | for (i = ARRAY_SIZE (known_data_prefixes); i--;) | |
169 | if (strncmp (name, known_data_prefixes[i], | |
170 | strlen (known_data_prefixes[i])) == 0) | |
171 | break; | |
172 | ||
173 | if (i < 0) | |
174 | as_warn (_("new section '%s' defined without attributes - this might cause problems"), name); | |
175 | } | |
176 | ||
177 | /* FIXME: We ought to free the memory allocated by obj_elf_section_name() | |
178 | for 'name', but we do not know if it was taken from the obstack, via | |
179 | demand_copy_C_string(), or xmalloc()ed. */ | |
180 | input_line_pointer = saved_ilp; | |
181 | obj_elf_section (push); | |
182 | } | |
183 | ||
3048287a NC |
184 | /* This table describes all the machine specific pseudo-ops the assembler |
185 | has to support. The fields are: | |
186 | pseudo-op name without dot | |
187 | function to call to execute this pseudo-op | |
188 | Integer arg to pass to the function. */ | |
189 | ||
252b5132 RH |
190 | const pseudo_typeS md_pseudo_table[] = |
191 | { | |
7ee7b84d | 192 | {"h8300h", h8300hmode, 0}, |
8d9cd6b1 | 193 | {"h8300hn", h8300hnmode, 0}, |
7ee7b84d | 194 | {"h8300s", h8300smode, 0}, |
8d9cd6b1 | 195 | {"h8300sn", h8300snmode, 0}, |
7ee7b84d | 196 | {"h8300sx", h8300sxmode, 0}, |
f4984206 | 197 | {"h8300sxn", h8300sxnmode, 0}, |
252b5132 RH |
198 | {"sbranch", sbranch, L_8}, |
199 | {"lbranch", sbranch, L_16}, | |
200 | ||
201 | {"int", pint, 0}, | |
202 | {"data.b", cons, 1}, | |
203 | {"data.w", cons, 2}, | |
204 | {"data.l", cons, 4}, | |
205 | {"form", listing_psize, 0}, | |
206 | {"heading", listing_title, 0}, | |
7ee7b84d MS |
207 | {"import", s_ignore, 0}, |
208 | {"page", listing_eject, 0}, | |
252b5132 | 209 | {"program", s_ignore, 0}, |
52b010e4 NC |
210 | |
211 | #ifdef OBJ_ELF | |
212 | {"section", h8300_elf_section, 0}, | |
213 | {"section.s", h8300_elf_section, 0}, | |
214 | {"sect", h8300_elf_section, 0}, | |
215 | {"sect.s", h8300_elf_section, 0}, | |
216 | #endif | |
217 | ||
252b5132 RH |
218 | {0, 0, 0} |
219 | }; | |
220 | ||
252b5132 RH |
221 | const char EXP_CHARS[] = "eE"; |
222 | ||
3048287a NC |
223 | /* Chars that mean this number is a floating point constant |
224 | As in 0f12.456 | |
225 | or 0d1.2345e12. */ | |
252b5132 RH |
226 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
227 | ||
3048287a | 228 | static struct hash_control *opcode_hash_control; /* Opcode mnemonics. */ |
252b5132 | 229 | |
70d6ecf3 AM |
230 | /* This function is called once, at assembler startup time. This |
231 | should set up all the tables, etc. that the MD part of the assembler | |
232 | needs. */ | |
3048287a | 233 | |
252b5132 | 234 | void |
b54a3392 | 235 | md_begin (void) |
252b5132 | 236 | { |
a720f7bc | 237 | unsigned int nopcodes; |
7ee7b84d | 238 | struct h8_opcode *p, *p1; |
a720f7bc | 239 | struct h8_instruction *pi; |
252b5132 RH |
240 | char prev_buffer[100]; |
241 | int idx = 0; | |
242 | ||
83e20b45 JL |
243 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300)) |
244 | as_warn (_("could not set architecture and machine")); | |
83e20b45 | 245 | |
252b5132 RH |
246 | opcode_hash_control = hash_new (); |
247 | prev_buffer[0] = 0; | |
248 | ||
a720f7bc KD |
249 | nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); |
250 | ||
251 | h8_instructions = (struct h8_instruction *) | |
252 | xmalloc (nopcodes * sizeof (struct h8_instruction)); | |
253 | ||
7ee7b84d MS |
254 | pi = h8_instructions; |
255 | p1 = h8_opcodes; | |
256 | /* We do a minimum amount of sorting on the opcode table; this is to | |
257 | make it easy to describe the mova instructions without unnecessary | |
258 | code duplication. | |
259 | Sorting only takes place inside blocks of instructions of the form | |
260 | X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */ | |
261 | while (p1) | |
252b5132 | 262 | { |
7ee7b84d MS |
263 | struct h8_opcode *first_skipped = 0; |
264 | int len, cmplen = 0; | |
265 | char *src = p1->name; | |
266 | char *dst, *buffer; | |
252b5132 | 267 | |
7ee7b84d MS |
268 | if (p1->name == 0) |
269 | break; | |
270 | /* Strip off any . part when inserting the opcode and only enter | |
271 | unique codes into the hash table. */ | |
272 | dst = buffer = malloc (strlen (src) + 1); | |
252b5132 RH |
273 | while (*src) |
274 | { | |
275 | if (*src == '.') | |
276 | { | |
277 | src++; | |
252b5132 RH |
278 | break; |
279 | } | |
7ee7b84d MS |
280 | if (*src == '/') |
281 | cmplen = src - p1->name + 1; | |
252b5132 RH |
282 | *dst++ = *src++; |
283 | } | |
7ee7b84d MS |
284 | *dst = 0; |
285 | len = dst - buffer; | |
286 | if (cmplen == 0) | |
287 | cmplen = len; | |
288 | hash_insert (opcode_hash_control, buffer, (char *) pi); | |
289 | strcpy (prev_buffer, buffer); | |
290 | idx++; | |
291 | ||
292 | for (p = p1; p->name; p++) | |
252b5132 | 293 | { |
7ee7b84d MS |
294 | /* A negative TIME is used to indicate that we've added this opcode |
295 | already. */ | |
296 | if (p->time == -1) | |
297 | continue; | |
298 | if (strncmp (p->name, buffer, cmplen) != 0 | |
299 | || (p->name[cmplen] != '\0' && p->name[cmplen] != '.' | |
300 | && p->name[cmplen - 1] != '/')) | |
301 | { | |
302 | if (first_skipped == 0) | |
303 | first_skipped = p; | |
304 | break; | |
305 | } | |
306 | if (strncmp (p->name, buffer, len) != 0) | |
307 | { | |
308 | if (first_skipped == 0) | |
309 | first_skipped = p; | |
310 | continue; | |
311 | } | |
312 | ||
313 | p->time = -1; | |
314 | pi->size = p->name[len] == '.' ? p->name[len + 1] : 0; | |
315 | pi->idx = idx; | |
252b5132 | 316 | |
7ee7b84d MS |
317 | /* Find the number of operands. */ |
318 | pi->noperands = 0; | |
319 | while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E) | |
320 | pi->noperands++; | |
70d6ecf3 | 321 | |
7ee7b84d MS |
322 | /* Find the length of the opcode in bytes. */ |
323 | pi->length = 0; | |
324 | while (p->data.nib[pi->length * 2] != (op_type) E) | |
325 | pi->length++; | |
a720f7bc | 326 | |
7ee7b84d MS |
327 | pi->opcode = p; |
328 | pi++; | |
329 | } | |
330 | p1 = first_skipped; | |
252b5132 RH |
331 | } |
332 | ||
a720f7bc KD |
333 | /* Add entry for the NULL vector terminator. */ |
334 | pi->length = 0; | |
335 | pi->noperands = 0; | |
336 | pi->idx = 0; | |
337 | pi->size = 0; | |
7ee7b84d | 338 | pi->opcode = 0; |
a720f7bc | 339 | |
252b5132 RH |
340 | linkrelax = 1; |
341 | } | |
342 | ||
252b5132 RH |
343 | struct h8_op |
344 | { | |
345 | op_type mode; | |
346 | unsigned reg; | |
347 | expressionS exp; | |
348 | }; | |
349 | ||
b54a3392 KH |
350 | static void clever_message (const struct h8_instruction *, struct h8_op *); |
351 | static void fix_operand_size (struct h8_op *, int); | |
352 | static void build_bytes (const struct h8_instruction *, struct h8_op *); | |
bcb012d3 | 353 | static void do_a_fix_imm (int, int, struct h8_op *, int, const struct h8_instruction *); |
b54a3392 KH |
354 | static void check_operand (struct h8_op *, unsigned int, char *); |
355 | static const struct h8_instruction * get_specific (const struct h8_instruction *, struct h8_op *, int) ; | |
356 | static char *get_operands (unsigned, char *, struct h8_op *); | |
357 | static void get_operand (char **, struct h8_op *, int); | |
358 | static int parse_reg (char *, op_type *, unsigned *, int); | |
359 | static char *skip_colonthing (char *, int *); | |
360 | static char *parse_exp (char *, struct h8_op *); | |
361 | ||
362 | static int constant_fits_width_p (struct h8_op *, unsigned int); | |
363 | static int constant_fits_size_p (struct h8_op *, int, int); | |
7ee7b84d | 364 | |
252b5132 RH |
365 | /* |
366 | parse operands | |
367 | WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp | |
368 | r0l,r0h,..r7l,r7h | |
369 | @WREG | |
370 | @WREG+ | |
371 | @-WREG | |
372 | #const | |
373 | ccr | |
374 | */ | |
375 | ||
bc0d738a NC |
376 | /* Try to parse a reg name. Return the number of chars consumed. */ |
377 | ||
40f09f82 | 378 | static int |
b54a3392 | 379 | parse_reg (char *src, op_type *mode, unsigned int *reg, int direction) |
252b5132 RH |
380 | { |
381 | char *end; | |
382 | int len; | |
383 | ||
70d6ecf3 | 384 | /* Cribbed from get_symbol_end. */ |
252b5132 RH |
385 | if (!is_name_beginner (*src) || *src == '\001') |
386 | return 0; | |
70d6ecf3 | 387 | end = src + 1; |
7ee7b84d | 388 | while ((is_part_of_name (*end) && *end != '.') || *end == '\001') |
252b5132 RH |
389 | end++; |
390 | len = end - src; | |
391 | ||
7ee7b84d | 392 | if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
393 | { |
394 | *mode = PSIZE | REG | direction; | |
395 | *reg = 7; | |
396 | return len; | |
397 | } | |
7ee7b84d MS |
398 | if (len == 3 && |
399 | TOLOWER (src[0]) == 'c' && | |
400 | TOLOWER (src[1]) == 'c' && | |
401 | TOLOWER (src[2]) == 'r') | |
252b5132 RH |
402 | { |
403 | *mode = CCR; | |
404 | *reg = 0; | |
405 | return len; | |
406 | } | |
7ee7b84d MS |
407 | if (len == 3 && |
408 | TOLOWER (src[0]) == 'e' && | |
409 | TOLOWER (src[1]) == 'x' && | |
410 | TOLOWER (src[2]) == 'r') | |
252b5132 RH |
411 | { |
412 | *mode = EXR; | |
7ee7b84d MS |
413 | *reg = 1; |
414 | return len; | |
415 | } | |
416 | if (len == 3 && | |
417 | TOLOWER (src[0]) == 'v' && | |
418 | TOLOWER (src[1]) == 'b' && | |
419 | TOLOWER (src[2]) == 'r') | |
420 | { | |
421 | *mode = VBR; | |
422 | *reg = 6; | |
423 | return len; | |
424 | } | |
425 | if (len == 3 && | |
426 | TOLOWER (src[0]) == 's' && | |
427 | TOLOWER (src[1]) == 'b' && | |
428 | TOLOWER (src[2]) == 'r') | |
429 | { | |
430 | *mode = SBR; | |
431 | *reg = 7; | |
252b5132 RH |
432 | return len; |
433 | } | |
7ee7b84d | 434 | if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
435 | { |
436 | *mode = PSIZE | REG | direction; | |
437 | *reg = 6; | |
438 | return len; | |
439 | } | |
7ee7b84d MS |
440 | if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
441 | src[2] >= '0' && src[2] <= '7') | |
252b5132 RH |
442 | { |
443 | *mode = L_32 | REG | direction; | |
444 | *reg = src[2] - '0'; | |
445 | if (!Hmode) | |
446 | as_warn (_("Reg not valid for H8/300")); | |
447 | return len; | |
448 | } | |
7ee7b84d | 449 | if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7') |
252b5132 RH |
450 | { |
451 | *mode = L_16 | REG | direction; | |
452 | *reg = src[1] - '0' + 8; | |
453 | if (!Hmode) | |
454 | as_warn (_("Reg not valid for H8/300")); | |
455 | return len; | |
456 | } | |
457 | ||
7ee7b84d | 458 | if (TOLOWER (src[0]) == 'r') |
252b5132 RH |
459 | { |
460 | if (src[1] >= '0' && src[1] <= '7') | |
461 | { | |
7ee7b84d | 462 | if (len == 3 && TOLOWER (src[2]) == 'l') |
252b5132 RH |
463 | { |
464 | *mode = L_8 | REG | direction; | |
465 | *reg = (src[1] - '0') + 8; | |
466 | return len; | |
467 | } | |
7ee7b84d | 468 | if (len == 3 && TOLOWER (src[2]) == 'h') |
252b5132 RH |
469 | { |
470 | *mode = L_8 | REG | direction; | |
471 | *reg = (src[1] - '0'); | |
472 | return len; | |
473 | } | |
474 | if (len == 2) | |
475 | { | |
476 | *mode = L_16 | REG | direction; | |
477 | *reg = (src[1] - '0'); | |
478 | return len; | |
479 | } | |
480 | } | |
481 | } | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
1b680e4f RS |
486 | |
487 | /* Parse an immediate or address-related constant and store it in OP. | |
488 | If the user also specifies the operand's size, store that size | |
489 | in OP->MODE, otherwise leave it for later code to decide. */ | |
490 | ||
40f09f82 | 491 | static char * |
b54a3392 | 492 | parse_exp (char *src, struct h8_op *op) |
252b5132 | 493 | { |
1b680e4f | 494 | char *save; |
252b5132 | 495 | |
1b680e4f RS |
496 | save = input_line_pointer; |
497 | input_line_pointer = src; | |
498 | expression (&op->exp); | |
499 | if (op->exp.X_op == O_absent) | |
252b5132 | 500 | as_bad (_("missing operand")); |
1b680e4f | 501 | src = input_line_pointer; |
252b5132 | 502 | input_line_pointer = save; |
1b680e4f RS |
503 | |
504 | return skip_colonthing (src, &op->mode); | |
252b5132 RH |
505 | } |
506 | ||
1b680e4f RS |
507 | |
508 | /* If SRC starts with an explicit operand size, skip it and store the size | |
509 | in *MODE. Leave *MODE unchanged otherwise. */ | |
510 | ||
252b5132 | 511 | static char * |
b54a3392 | 512 | skip_colonthing (char *src, int *mode) |
252b5132 | 513 | { |
1b680e4f | 514 | if (*src == ':') |
252b5132 | 515 | { |
1b680e4f | 516 | src++; |
252b5132 | 517 | *mode &= ~SIZE; |
1b680e4f | 518 | if (src[0] == '8' && !ISDIGIT (src[1])) |
7ee7b84d | 519 | *mode |= L_8; |
1b680e4f | 520 | else if (src[0] == '2' && !ISDIGIT (src[1])) |
7ee7b84d | 521 | *mode |= L_2; |
1b680e4f | 522 | else if (src[0] == '3' && !ISDIGIT (src[1])) |
7ee7b84d | 523 | *mode |= L_3; |
1b680e4f | 524 | else if (src[0] == '4' && !ISDIGIT (src[1])) |
7ee7b84d | 525 | *mode |= L_4; |
1b680e4f | 526 | else if (src[0] == '5' && !ISDIGIT (src[1])) |
7ee7b84d | 527 | *mode |= L_5; |
1b680e4f | 528 | else if (src[0] == '2' && src[1] == '4' && !ISDIGIT (src[2])) |
7ee7b84d | 529 | *mode |= L_24; |
1b680e4f | 530 | else if (src[0] == '3' && src[1] == '2' && !ISDIGIT (src[2])) |
7ee7b84d | 531 | *mode |= L_32; |
1b680e4f | 532 | else if (src[0] == '1' && src[1] == '6' && !ISDIGIT (src[2])) |
7ee7b84d | 533 | *mode |= L_16; |
252b5132 | 534 | else |
7ee7b84d MS |
535 | as_bad (_("invalid operand size requested")); |
536 | ||
1b680e4f RS |
537 | while (ISDIGIT (*src)) |
538 | src++; | |
252b5132 | 539 | } |
1b680e4f | 540 | return src; |
252b5132 RH |
541 | } |
542 | ||
543 | /* The many forms of operand: | |
544 | ||
545 | Rn Register direct | |
546 | @Rn Register indirect | |
547 | @(exp[:16], Rn) Register indirect with displacement | |
548 | @Rn+ | |
549 | @-Rn | |
70d6ecf3 AM |
550 | @aa:8 absolute 8 bit |
551 | @aa:16 absolute 16 bit | |
252b5132 RH |
552 | @aa absolute 16 bit |
553 | ||
554 | #xx[:size] immediate data | |
70d6ecf3 | 555 | @(exp:[8], pc) pc rel |
3048287a | 556 | @@aa[:8] memory indirect. */ |
252b5132 | 557 | |
7ee7b84d | 558 | static int |
b54a3392 | 559 | constant_fits_width_p (struct h8_op *operand, unsigned int width) |
7ee7b84d MS |
560 | { |
561 | return ((operand->exp.X_add_number & ~width) == 0 | |
562 | || (operand->exp.X_add_number | width) == (unsigned)(~0)); | |
563 | } | |
564 | ||
565 | static int | |
b54a3392 | 566 | constant_fits_size_p (struct h8_op *operand, int size, int no_symbols) |
7ee7b84d MS |
567 | { |
568 | offsetT num = operand->exp.X_add_number; | |
569 | if (no_symbols | |
570 | && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0)) | |
571 | return 0; | |
572 | switch (size) | |
573 | { | |
574 | case L_2: | |
575 | return (num & ~3) == 0; | |
576 | case L_3: | |
577 | return (num & ~7) == 0; | |
578 | case L_3NZ: | |
579 | return num >= 1 && num < 8; | |
580 | case L_4: | |
581 | return (num & ~15) == 0; | |
582 | case L_5: | |
583 | return num >= 1 && num < 32; | |
584 | case L_8: | |
585 | return (num & ~0xFF) == 0 || ((unsigned)num | 0x7F) == ~0u; | |
586 | case L_8U: | |
587 | return (num & ~0xFF) == 0; | |
588 | case L_16: | |
589 | return (num & ~0xFFFF) == 0 || ((unsigned)num | 0x7FFF) == ~0u; | |
590 | case L_16U: | |
591 | return (num & ~0xFFFF) == 0; | |
592 | case L_32: | |
593 | return 1; | |
594 | default: | |
595 | abort (); | |
596 | } | |
597 | } | |
598 | ||
252b5132 | 599 | static void |
b54a3392 | 600 | get_operand (char **ptr, struct h8_op *op, int direction) |
252b5132 RH |
601 | { |
602 | char *src = *ptr; | |
603 | op_type mode; | |
604 | unsigned int num; | |
605 | unsigned int len; | |
606 | ||
7ee7b84d | 607 | op->mode = 0; |
252b5132 | 608 | |
3048287a NC |
609 | /* Check for '(' and ')' for instructions ldm and stm. */ |
610 | if (src[0] == '(' && src[8] == ')') | |
611 | ++ src; | |
612 | ||
252b5132 RH |
613 | /* Gross. Gross. ldm and stm have a format not easily handled |
614 | by get_operand. We deal with it explicitly here. */ | |
7ee7b84d MS |
615 | if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
616 | ISDIGIT (src[2]) && src[3] == '-' && | |
617 | TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6])) | |
252b5132 RH |
618 | { |
619 | int low, high; | |
620 | ||
621 | low = src[2] - '0'; | |
622 | high = src[6] - '0'; | |
623 | ||
4892e510 NC |
624 | /* Check register pair's validity as per tech note TN-H8*-193A/E |
625 | from Renesas for H8S and H8SX hardware manual. */ | |
626 | if ( !(low == 0 && (high == 1 || high == 2 || high == 3)) | |
627 | && !(low == 1 && (high == 2 || high == 3 || high == 4) && SXmode) | |
628 | && !(low == 2 && (high == 3 || ((high == 4 || high == 5) && SXmode))) | |
629 | && !(low == 3 && (high == 4 || high == 5 || high == 6) && SXmode) | |
630 | && !(low == 4 && (high == 5 || high == 6)) | |
b4f16abb | 631 | && !(low == 4 && high == 7 && SXmode) |
4892e510 NC |
632 | && !(low == 5 && (high == 6 || high == 7) && SXmode) |
633 | && !(low == 6 && high == 7 && SXmode)) | |
252b5132 RH |
634 | as_bad (_("Invalid register list for ldm/stm\n")); |
635 | ||
252b5132 RH |
636 | /* Even sicker. We encode two registers into op->reg. One |
637 | for the low register to save, the other for the high | |
638 | register to save; we also set the high bit in op->reg | |
639 | so we know this is "very special". */ | |
640 | op->reg = 0x80000000 | (high << 8) | low; | |
641 | op->mode = REG; | |
3048287a NC |
642 | if (src[7] == ')') |
643 | *ptr = src + 8; | |
644 | else | |
645 | *ptr = src + 7; | |
252b5132 RH |
646 | return; |
647 | } | |
648 | ||
649 | len = parse_reg (src, &op->mode, &op->reg, direction); | |
650 | if (len) | |
651 | { | |
7ee7b84d MS |
652 | src += len; |
653 | if (*src == '.') | |
654 | { | |
655 | int size = op->mode & SIZE; | |
656 | switch (src[1]) | |
657 | { | |
658 | case 'l': case 'L': | |
659 | if (size != L_32) | |
660 | as_warn (_("mismatch between register and suffix")); | |
661 | op->mode = (op->mode & ~MODE) | LOWREG; | |
662 | break; | |
663 | case 'w': case 'W': | |
664 | if (size != L_32 && size != L_16) | |
665 | as_warn (_("mismatch between register and suffix")); | |
666 | op->mode = (op->mode & ~MODE) | LOWREG; | |
667 | op->mode = (op->mode & ~SIZE) | L_16; | |
668 | break; | |
669 | case 'b': case 'B': | |
670 | op->mode = (op->mode & ~MODE) | LOWREG; | |
671 | if (size != L_32 && size != L_8) | |
672 | as_warn (_("mismatch between register and suffix")); | |
673 | op->mode = (op->mode & ~MODE) | LOWREG; | |
674 | op->mode = (op->mode & ~SIZE) | L_8; | |
675 | break; | |
676 | default: | |
20203fb9 | 677 | as_warn (_("invalid suffix after register.")); |
7ee7b84d MS |
678 | break; |
679 | } | |
680 | src += 2; | |
681 | } | |
682 | *ptr = src; | |
252b5132 RH |
683 | return; |
684 | } | |
685 | ||
686 | if (*src == '@') | |
687 | { | |
688 | src++; | |
689 | if (*src == '@') | |
690 | { | |
1b680e4f | 691 | *ptr = parse_exp (src + 1, op); |
7ee7b84d MS |
692 | if (op->exp.X_add_number >= 0x100) |
693 | { | |
d4e2de6b | 694 | int divisor = 1; |
7ee7b84d MS |
695 | |
696 | op->mode = VECIND; | |
697 | /* FIXME : 2? or 4? */ | |
698 | if (op->exp.X_add_number >= 0x400) | |
699 | as_bad (_("address too high for vector table jmp/jsr")); | |
700 | else if (op->exp.X_add_number >= 0x200) | |
701 | divisor = 4; | |
702 | else | |
703 | divisor = 2; | |
704 | ||
705 | op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80; | |
706 | } | |
707 | else | |
708 | op->mode = MEMIND; | |
252b5132 | 709 | return; |
252b5132 RH |
710 | } |
711 | ||
7ee7b84d | 712 | if (*src == '-' || *src == '+') |
252b5132 | 713 | { |
1b680e4f | 714 | len = parse_reg (src + 1, &mode, &num, direction); |
252b5132 RH |
715 | if (len == 0) |
716 | { | |
70d6ecf3 | 717 | /* Oops, not a reg after all, must be ordinary exp. */ |
1b680e4f RS |
718 | op->mode = ABS | direction; |
719 | *ptr = parse_exp (src, op); | |
252b5132 | 720 | return; |
252b5132 RH |
721 | } |
722 | ||
d4e2de6b NC |
723 | if (((mode & SIZE) != PSIZE) |
724 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
725 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 726 | as_bad (_("Wrong size pointer register for architecture.")); |
1b680e4f RS |
727 | |
728 | op->mode = src[0] == '-' ? RDPREDEC : RDPREINC; | |
252b5132 | 729 | op->reg = num; |
1b680e4f | 730 | *ptr = src + 1 + len; |
252b5132 RH |
731 | return; |
732 | } | |
733 | if (*src == '(') | |
734 | { | |
252b5132 RH |
735 | src++; |
736 | ||
7ee7b84d MS |
737 | /* See if this is @(ERn.x, PC). */ |
738 | len = parse_reg (src, &mode, &op->reg, direction); | |
739 | if (len != 0 && (mode & MODE) == REG && src[len] == '.') | |
740 | { | |
741 | switch (TOLOWER (src[len + 1])) | |
742 | { | |
743 | case 'b': | |
744 | mode = PCIDXB | direction; | |
745 | break; | |
746 | case 'w': | |
747 | mode = PCIDXW | direction; | |
748 | break; | |
749 | case 'l': | |
750 | mode = PCIDXL | direction; | |
751 | break; | |
752 | default: | |
753 | mode = 0; | |
754 | break; | |
755 | } | |
756 | if (mode | |
757 | && src[len + 2] == ',' | |
758 | && TOLOWER (src[len + 3]) != 'p' | |
759 | && TOLOWER (src[len + 4]) != 'c' | |
760 | && src[len + 5] != ')') | |
761 | { | |
762 | *ptr = src + len + 6; | |
763 | op->mode |= mode; | |
764 | return; | |
765 | } | |
766 | /* Fall through into disp case - the grammar is somewhat | |
767 | ambiguous, so we should try whether it's a DISP operand | |
768 | after all ("ER3.L" might be a poorly named label...). */ | |
769 | } | |
770 | ||
771 | /* Disp. */ | |
772 | ||
70d6ecf3 | 773 | /* Start off assuming a 16 bit offset. */ |
252b5132 | 774 | |
1b680e4f | 775 | src = parse_exp (src, op); |
252b5132 RH |
776 | if (*src == ')') |
777 | { | |
252b5132 | 778 | op->mode |= ABS | direction; |
1b680e4f | 779 | *ptr = src + 1; |
252b5132 RH |
780 | return; |
781 | } | |
782 | ||
783 | if (*src != ',') | |
784 | { | |
785 | as_bad (_("expected @(exp, reg16)")); | |
786 | return; | |
252b5132 RH |
787 | } |
788 | src++; | |
789 | ||
790 | len = parse_reg (src, &mode, &op->reg, direction); | |
7ee7b84d | 791 | if (len == 0 || (mode & MODE) != REG) |
252b5132 RH |
792 | { |
793 | as_bad (_("expected @(exp, reg16)")); | |
794 | return; | |
795 | } | |
252b5132 | 796 | src += len; |
7ee7b84d MS |
797 | if (src[0] == '.') |
798 | { | |
799 | switch (TOLOWER (src[1])) | |
800 | { | |
801 | case 'b': | |
802 | op->mode |= INDEXB | direction; | |
803 | break; | |
804 | case 'w': | |
805 | op->mode |= INDEXW | direction; | |
806 | break; | |
807 | case 'l': | |
808 | op->mode |= INDEXL | direction; | |
809 | break; | |
810 | default: | |
811 | as_bad (_("expected .L, .W or .B for register in indexed addressing mode")); | |
812 | } | |
813 | src += 2; | |
814 | op->reg &= 7; | |
815 | } | |
816 | else | |
817 | op->mode |= DISP | direction; | |
1b680e4f | 818 | src = skip_colonthing (src, &op->mode); |
252b5132 RH |
819 | |
820 | if (*src != ')' && '(') | |
821 | { | |
822 | as_bad (_("expected @(exp, reg16)")); | |
823 | return; | |
824 | } | |
825 | *ptr = src + 1; | |
252b5132 RH |
826 | return; |
827 | } | |
828 | len = parse_reg (src, &mode, &num, direction); | |
829 | ||
830 | if (len) | |
831 | { | |
832 | src += len; | |
7ee7b84d | 833 | if (*src == '+' || *src == '-') |
252b5132 | 834 | { |
d4e2de6b NC |
835 | if (((mode & SIZE) != PSIZE) |
836 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
837 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 838 | as_bad (_("Wrong size pointer register for architecture.")); |
7ee7b84d | 839 | op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC; |
252b5132 | 840 | op->reg = num; |
7ee7b84d | 841 | src++; |
252b5132 RH |
842 | *ptr = src; |
843 | return; | |
844 | } | |
d4e2de6b NC |
845 | if (((mode & SIZE) != PSIZE) |
846 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
847 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 RH |
848 | as_bad (_("Wrong size pointer register for architecture.")); |
849 | ||
850 | op->mode = direction | IND | PSIZE; | |
851 | op->reg = num; | |
852 | *ptr = src; | |
853 | ||
854 | return; | |
855 | } | |
856 | else | |
857 | { | |
858 | /* must be a symbol */ | |
859 | ||
860 | op->mode = ABS | direction; | |
1b680e4f | 861 | *ptr = parse_exp (src, op); |
252b5132 RH |
862 | return; |
863 | } | |
864 | } | |
865 | ||
252b5132 RH |
866 | if (*src == '#') |
867 | { | |
252b5132 | 868 | op->mode = IMM; |
1b680e4f | 869 | *ptr = parse_exp (src + 1, op); |
252b5132 RH |
870 | return; |
871 | } | |
7ee7b84d MS |
872 | else if (strncmp (src, "mach", 4) == 0 || |
873 | strncmp (src, "macl", 4) == 0 || | |
874 | strncmp (src, "MACH", 4) == 0 || | |
875 | strncmp (src, "MACL", 4) == 0) | |
252b5132 | 876 | { |
7ee7b84d | 877 | op->reg = TOLOWER (src[3]) == 'l'; |
252b5132 RH |
878 | op->mode = MACREG; |
879 | *ptr = src + 4; | |
880 | return; | |
881 | } | |
882 | else | |
883 | { | |
1b680e4f RS |
884 | op->mode = PCREL; |
885 | *ptr = parse_exp (src, op); | |
252b5132 RH |
886 | } |
887 | } | |
888 | ||
70d6ecf3 | 889 | static char * |
b54a3392 | 890 | get_operands (unsigned int noperands, char *op_end, struct h8_op *operand) |
252b5132 RH |
891 | { |
892 | char *ptr = op_end; | |
893 | ||
894 | switch (noperands) | |
895 | { | |
896 | case 0: | |
252b5132 RH |
897 | break; |
898 | ||
899 | case 1: | |
900 | ptr++; | |
7ee7b84d | 901 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
902 | if (*ptr == ',') |
903 | { | |
904 | ptr++; | |
7ee7b84d | 905 | get_operand (&ptr, operand + 1, DST); |
252b5132 | 906 | } |
252b5132 | 907 | break; |
70d6ecf3 | 908 | |
252b5132 RH |
909 | case 2: |
910 | ptr++; | |
7ee7b84d | 911 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
912 | if (*ptr == ',') |
913 | ptr++; | |
7ee7b84d MS |
914 | get_operand (&ptr, operand + 1, DST); |
915 | break; | |
916 | ||
917 | case 3: | |
918 | ptr++; | |
919 | get_operand (&ptr, operand + 0, SRC); | |
920 | if (*ptr == ',') | |
921 | ptr++; | |
922 | get_operand (&ptr, operand + 1, DST); | |
923 | if (*ptr == ',') | |
924 | ptr++; | |
925 | get_operand (&ptr, operand + 2, OP3); | |
252b5132 RH |
926 | break; |
927 | ||
928 | default: | |
929 | abort (); | |
930 | } | |
931 | ||
252b5132 RH |
932 | return ptr; |
933 | } | |
934 | ||
7ee7b84d MS |
935 | /* MOVA has special requirements. Rather than adding twice the amount of |
936 | addressing modes, we simply special case it a bit. */ | |
937 | static void | |
938 | get_mova_operands (char *op_end, struct h8_op *operand) | |
939 | { | |
940 | char *ptr = op_end; | |
941 | ||
942 | if (ptr[1] != '@' || ptr[2] != '(') | |
943 | goto error; | |
944 | ptr += 3; | |
945 | operand[0].mode = 0; | |
1b680e4f | 946 | ptr = parse_exp (ptr, &operand[0]); |
7ee7b84d MS |
947 | |
948 | if (*ptr !=',') | |
949 | goto error; | |
950 | ptr++; | |
951 | get_operand (&ptr, operand + 1, DST); | |
952 | ||
953 | if (*ptr =='.') | |
954 | { | |
955 | ptr++; | |
956 | switch (*ptr++) | |
957 | { | |
958 | case 'b': case 'B': | |
959 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
960 | break; | |
961 | case 'w': case 'W': | |
962 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
963 | break; | |
964 | case 'l': case 'L': | |
965 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
966 | break; | |
967 | default: | |
968 | goto error; | |
969 | } | |
970 | } | |
971 | else if ((operand[1].mode & MODE) == LOWREG) | |
972 | { | |
973 | switch (operand[1].mode & SIZE) | |
974 | { | |
975 | case L_8: | |
976 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
977 | break; | |
978 | case L_16: | |
979 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
980 | break; | |
981 | case L_32: | |
982 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
983 | break; | |
984 | default: | |
985 | goto error; | |
986 | } | |
987 | } | |
988 | else | |
989 | goto error; | |
990 | ||
991 | if (*ptr++ != ')' || *ptr++ != ',') | |
992 | goto error; | |
993 | get_operand (&ptr, operand + 2, OP3); | |
994 | /* See if we can use the short form of MOVA. */ | |
995 | if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG) | |
996 | && (operand[2].mode & MODE) == REG | |
997 | && (operand[1].reg & 7) == (operand[2].reg & 7)) | |
998 | { | |
999 | operand[1].mode = operand[2].mode = 0; | |
1000 | operand[0].reg = operand[2].reg & 7; | |
1001 | } | |
1002 | return; | |
1003 | ||
1004 | error: | |
1005 | as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\"")); | |
7ee7b84d MS |
1006 | } |
1007 | ||
1008 | static void | |
1009 | get_rtsl_operands (char *ptr, struct h8_op *operand) | |
1010 | { | |
2132e3a3 AM |
1011 | int mode, len, type = 0; |
1012 | unsigned int num, num2; | |
7ee7b84d MS |
1013 | |
1014 | ptr++; | |
1015 | if (*ptr == '(') | |
1016 | { | |
1017 | ptr++; | |
1018 | type = 1; | |
1019 | } | |
1020 | len = parse_reg (ptr, &mode, &num, SRC); | |
1021 | if (len == 0 || (mode & MODE) != REG) | |
1022 | { | |
1023 | as_bad (_("expected register")); | |
1024 | return; | |
1025 | } | |
0613284f RS |
1026 | ptr += len; |
1027 | if (*ptr == '-') | |
7ee7b84d | 1028 | { |
0613284f | 1029 | len = parse_reg (++ptr, &mode, &num2, SRC); |
7ee7b84d MS |
1030 | if (len == 0 || (mode & MODE) != REG) |
1031 | { | |
1032 | as_bad (_("expected register")); | |
1033 | return; | |
1034 | } | |
1035 | ptr += len; | |
7ee7b84d MS |
1036 | /* CONST_xxx are used as placeholders in the opcode table. */ |
1037 | num = num2 - num; | |
2132e3a3 | 1038 | if (num > 3) |
7ee7b84d MS |
1039 | { |
1040 | as_bad (_("invalid register list")); | |
1041 | return; | |
1042 | } | |
1043 | } | |
1044 | else | |
1045 | num2 = num, num = 0; | |
0613284f RS |
1046 | if (type == 1 && *ptr++ != ')') |
1047 | { | |
1048 | as_bad (_("expected closing paren")); | |
1049 | return; | |
1050 | } | |
7ee7b84d MS |
1051 | operand[0].mode = RS32; |
1052 | operand[1].mode = RD32; | |
1053 | operand[0].reg = num; | |
1054 | operand[1].reg = num2; | |
1055 | } | |
1056 | ||
252b5132 RH |
1057 | /* Passed a pointer to a list of opcodes which use different |
1058 | addressing modes, return the opcode which matches the opcodes | |
70d6ecf3 | 1059 | provided. */ |
3048287a | 1060 | |
a720f7bc | 1061 | static const struct h8_instruction * |
b54a3392 KH |
1062 | get_specific (const struct h8_instruction *instruction, |
1063 | struct h8_op *operands, int size) | |
252b5132 | 1064 | { |
a720f7bc | 1065 | const struct h8_instruction *this_try = instruction; |
7ee7b84d | 1066 | const struct h8_instruction *found_other = 0, *found_mismatched = 0; |
252b5132 | 1067 | int found = 0; |
a720f7bc | 1068 | int this_index = instruction->idx; |
7ee7b84d | 1069 | int noperands = 0; |
252b5132 RH |
1070 | |
1071 | /* There's only one ldm/stm and it's easier to just | |
1072 | get out quick for them. */ | |
7ee7b84d MS |
1073 | if (OP_KIND (instruction->opcode->how) == O_LDM |
1074 | || OP_KIND (instruction->opcode->how) == O_STM) | |
252b5132 RH |
1075 | return this_try; |
1076 | ||
7ee7b84d MS |
1077 | while (noperands < 3 && operands[noperands].mode != 0) |
1078 | noperands++; | |
1079 | ||
a720f7bc | 1080 | while (this_index == instruction->idx && !found) |
252b5132 | 1081 | { |
7ee7b84d | 1082 | int this_size; |
252b5132 | 1083 | |
7ee7b84d | 1084 | found = 1; |
a720f7bc | 1085 | this_try = instruction++; |
7ee7b84d | 1086 | this_size = this_try->opcode->how & SN; |
252b5132 | 1087 | |
7ee7b84d MS |
1088 | if (this_try->noperands != noperands) |
1089 | found = 0; | |
1090 | else if (this_try->noperands > 0) | |
252b5132 | 1091 | { |
3048287a | 1092 | int i; |
252b5132 RH |
1093 | |
1094 | for (i = 0; i < this_try->noperands && found; i++) | |
1095 | { | |
a720f7bc | 1096 | op_type op = this_try->opcode->args.nib[i]; |
7ee7b84d MS |
1097 | int op_mode = op & MODE; |
1098 | int op_size = op & SIZE; | |
252b5132 | 1099 | int x = operands[i].mode; |
7ee7b84d MS |
1100 | int x_mode = x & MODE; |
1101 | int x_size = x & SIZE; | |
252b5132 | 1102 | |
7ee7b84d | 1103 | if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG)) |
252b5132 | 1104 | { |
7ee7b84d MS |
1105 | if ((x_size == L_8 && (operands[i].reg & 8) == 0) |
1106 | || (x_size == L_16 && (operands[i].reg & 8) == 8)) | |
1107 | as_warn (_("can't use high part of register in operand %d"), i); | |
1108 | ||
1109 | if (x_size != op_size) | |
1110 | found = 0; | |
252b5132 | 1111 | } |
7ee7b84d | 1112 | else if (op_mode == REG) |
252b5132 | 1113 | { |
7ee7b84d MS |
1114 | if (x_mode == LOWREG) |
1115 | x_mode = REG; | |
1116 | if (x_mode != REG) | |
252b5132 RH |
1117 | found = 0; |
1118 | ||
7ee7b84d MS |
1119 | if (x_size == L_P) |
1120 | x_size = (Hmode ? L_32 : L_16); | |
1121 | if (op_size == L_P) | |
1122 | op_size = (Hmode ? L_32 : L_16); | |
252b5132 | 1123 | |
70d6ecf3 | 1124 | /* The size of the reg is v important. */ |
7ee7b84d | 1125 | if (op_size != x_size) |
252b5132 RH |
1126 | found = 0; |
1127 | } | |
7ee7b84d | 1128 | else if (op_mode & CTRL) /* control register */ |
252b5132 | 1129 | { |
7ee7b84d MS |
1130 | if (!(x_mode & CTRL)) |
1131 | found = 0; | |
1132 | ||
1133 | switch (x_mode) | |
1134 | { | |
1135 | case CCR: | |
1136 | if (op_mode != CCR && | |
1137 | op_mode != CCR_EXR && | |
1138 | op_mode != CC_EX_VB_SB) | |
1139 | found = 0; | |
1140 | break; | |
1141 | case EXR: | |
1142 | if (op_mode != EXR && | |
1143 | op_mode != CCR_EXR && | |
1144 | op_mode != CC_EX_VB_SB) | |
1145 | found = 0; | |
1146 | break; | |
1147 | case MACH: | |
1148 | if (op_mode != MACH && | |
1149 | op_mode != MACREG) | |
1150 | found = 0; | |
1151 | break; | |
1152 | case MACL: | |
1153 | if (op_mode != MACL && | |
1154 | op_mode != MACREG) | |
1155 | found = 0; | |
1156 | break; | |
1157 | case VBR: | |
1158 | if (op_mode != VBR && | |
1159 | op_mode != VBR_SBR && | |
1160 | op_mode != CC_EX_VB_SB) | |
1161 | found = 0; | |
1162 | break; | |
1163 | case SBR: | |
1164 | if (op_mode != SBR && | |
1165 | op_mode != VBR_SBR && | |
1166 | op_mode != CC_EX_VB_SB) | |
1167 | found = 0; | |
1168 | break; | |
1169 | } | |
1170 | } | |
1171 | else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL)) | |
1172 | { | |
1173 | operands[i].mode &= ~MODE; | |
252b5132 | 1174 | operands[i].mode |= ABSJMP; |
70d6ecf3 | 1175 | /* But it may not be 24 bits long. */ |
7ee7b84d | 1176 | if (x_mode == ABS && !Hmode) |
252b5132 RH |
1177 | { |
1178 | operands[i].mode &= ~SIZE; | |
1179 | operands[i].mode |= L_16; | |
1180 | } | |
7ee7b84d MS |
1181 | if ((operands[i].mode & SIZE) == L_32 |
1182 | && (op_mode & SIZE) != L_32) | |
1183 | found = 0; | |
252b5132 | 1184 | } |
7ee7b84d | 1185 | else if (x_mode == IMM && op_mode != IMM) |
252b5132 | 1186 | { |
7ee7b84d MS |
1187 | offsetT num = operands[i].exp.X_add_number; |
1188 | if (op_mode == KBIT || op_mode == DBIT) | |
1189 | /* This is ok if the immediate value is sensible. */; | |
1190 | else if (op_mode == CONST_2) | |
1191 | found = num == 2; | |
1192 | else if (op_mode == CONST_4) | |
1193 | found = num == 4; | |
1194 | else if (op_mode == CONST_8) | |
1195 | found = num == 8; | |
1196 | else if (op_mode == CONST_16) | |
1197 | found = num == 16; | |
1198 | else | |
1199 | found = 0; | |
252b5132 | 1200 | } |
7ee7b84d | 1201 | else if (op_mode == PCREL && op_mode == x_mode) |
252b5132 | 1202 | { |
ba18dd6f | 1203 | /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour: |
7ee7b84d | 1204 | If x_size is L_8, promote it. */ |
ba18dd6f AO |
1205 | if (OP_KIND (this_try->opcode->how) == O_MOVSD |
1206 | || OP_KIND (this_try->opcode->how) == O_BSRBC | |
1207 | || OP_KIND (this_try->opcode->how) == O_BSRBS) | |
7ee7b84d MS |
1208 | if (x_size == L_8) |
1209 | x_size = L_16; | |
1210 | ||
70d6ecf3 | 1211 | /* The size of the displacement is important. */ |
7ee7b84d | 1212 | if (op_size != x_size) |
252b5132 RH |
1213 | found = 0; |
1214 | } | |
7ee7b84d MS |
1215 | else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS |
1216 | || op_mode == INDEXB || op_mode == INDEXW | |
1217 | || op_mode == INDEXL) | |
1218 | && op_mode == x_mode) | |
252b5132 RH |
1219 | { |
1220 | /* Promote a L_24 to L_32 if it makes us match. */ | |
7ee7b84d | 1221 | if (x_size == L_24 && op_size == L_32) |
252b5132 | 1222 | { |
7ee7b84d MS |
1223 | x &= ~SIZE; |
1224 | x |= x_size = L_32; | |
252b5132 | 1225 | } |
7ee7b84d | 1226 | |
7ee7b84d | 1227 | if (((x_size == L_16 && op_size == L_16U) |
2d0d09ca | 1228 | || (x_size == L_8 && op_size == L_8U) |
7ee7b84d MS |
1229 | || (x_size == L_3 && op_size == L_3NZ)) |
1230 | /* We're deliberately more permissive for ABS modes. */ | |
1231 | && (op_mode == ABS | |
1232 | || constant_fits_size_p (operands + i, op_size, | |
1233 | op & NO_SYMBOLS))) | |
1234 | x_size = op_size; | |
1235 | ||
1236 | if (x_size != 0 && op_size != x_size) | |
1237 | found = 0; | |
1238 | else if (x_size == 0 | |
1239 | && ! constant_fits_size_p (operands + i, op_size, | |
1240 | op & NO_SYMBOLS)) | |
252b5132 RH |
1241 | found = 0; |
1242 | } | |
7ee7b84d | 1243 | else if (op_mode != x_mode) |
252b5132 RH |
1244 | { |
1245 | found = 0; | |
70d6ecf3 | 1246 | } |
252b5132 RH |
1247 | } |
1248 | } | |
7ee7b84d MS |
1249 | if (found) |
1250 | { | |
1251 | if ((this_try->opcode->available == AV_H8SX && ! SXmode) | |
d4ea8842 | 1252 | || (this_try->opcode->available == AV_H8S && ! Smode) |
7ee7b84d MS |
1253 | || (this_try->opcode->available == AV_H8H && ! Hmode)) |
1254 | found = 0, found_other = this_try; | |
1255 | else if (this_size != size && (this_size != SN && size != SN)) | |
1256 | found_mismatched = this_try, found = 0; | |
1257 | ||
1258 | } | |
252b5132 RH |
1259 | } |
1260 | if (found) | |
1261 | return this_try; | |
7ee7b84d MS |
1262 | if (found_other) |
1263 | { | |
1264 | as_warn (_("Opcode `%s' with these operand types not available in %s mode"), | |
1265 | found_other->opcode->name, | |
1266 | (! Hmode && ! Smode ? "H8/300" | |
1267 | : SXmode ? "H8sx" | |
1268 | : Smode ? "H8/300S" | |
1269 | : "H8/300H")); | |
1270 | } | |
1271 | else if (found_mismatched) | |
1272 | { | |
1273 | as_warn (_("mismatch between opcode size and operand size")); | |
1274 | return found_mismatched; | |
1275 | } | |
1276 | return 0; | |
252b5132 RH |
1277 | } |
1278 | ||
1279 | static void | |
b54a3392 | 1280 | check_operand (struct h8_op *operand, unsigned int width, char *string) |
252b5132 RH |
1281 | { |
1282 | if (operand->exp.X_add_symbol == 0 | |
1283 | && operand->exp.X_op_symbol == 0) | |
1284 | { | |
70d6ecf3 AM |
1285 | /* No symbol involved, let's look at offset, it's dangerous if |
1286 | any of the high bits are not 0 or ff's, find out by oring or | |
1287 | anding with the width and seeing if the answer is 0 or all | |
1288 | fs. */ | |
252b5132 | 1289 | |
7ee7b84d | 1290 | if (! constant_fits_width_p (operand, width)) |
252b5132 | 1291 | { |
70d6ecf3 | 1292 | if (width == 255 |
252b5132 RH |
1293 | && (operand->exp.X_add_number & 0xff00) == 0xff00) |
1294 | { | |
1295 | /* Just ignore this one - which happens when trying to | |
1296 | fit a 16 bit address truncated into an 8 bit address | |
1297 | of something like bset. */ | |
1298 | } | |
166e23f9 KH |
1299 | else if (strcmp (string, "@") == 0 |
1300 | && width == 0xffff | |
1301 | && (operand->exp.X_add_number & 0xff8000) == 0xff8000) | |
1302 | { | |
1303 | /* Just ignore this one - which happens when trying to | |
1304 | fit a 24 bit address truncated into a 16 bit address | |
1305 | of something like mov.w. */ | |
1306 | } | |
70d6ecf3 | 1307 | else |
252b5132 RH |
1308 | { |
1309 | as_warn (_("operand %s0x%lx out of range."), string, | |
1310 | (unsigned long) operand->exp.X_add_number); | |
1311 | } | |
1312 | } | |
1313 | } | |
252b5132 RH |
1314 | } |
1315 | ||
1316 | /* RELAXMODE has one of 3 values: | |
1317 | ||
1318 | 0 Output a "normal" reloc, no relaxing possible for this insn/reloc | |
1319 | ||
1320 | 1 Output a relaxable 24bit absolute mov.w address relocation | |
1321 | (may relax into a 16bit absolute address). | |
1322 | ||
1323 | 2 Output a relaxable 16/24 absolute mov.b address relocation | |
1324 | (may relax into an 8bit absolute address). */ | |
1325 | ||
1326 | static void | |
bcb012d3 | 1327 | do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode, const struct h8_instruction *this_try) |
252b5132 RH |
1328 | { |
1329 | int idx; | |
1330 | int size; | |
1331 | int where; | |
7ee7b84d | 1332 | char *bytes = frag_now->fr_literal + offset; |
252b5132 | 1333 | |
7ee7b84d | 1334 | char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; |
252b5132 RH |
1335 | |
1336 | if (operand->exp.X_add_symbol == 0) | |
1337 | { | |
252b5132 RH |
1338 | switch (operand->mode & SIZE) |
1339 | { | |
1340 | case L_2: | |
1341 | check_operand (operand, 0x3, t); | |
7ee7b84d | 1342 | bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4); |
252b5132 RH |
1343 | break; |
1344 | case L_3: | |
7ee7b84d | 1345 | case L_3NZ: |
252b5132 | 1346 | check_operand (operand, 0x7, t); |
7ee7b84d MS |
1347 | bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4); |
1348 | break; | |
1349 | case L_4: | |
1350 | check_operand (operand, 0xF, t); | |
1351 | bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4); | |
1352 | break; | |
1353 | case L_5: | |
1354 | check_operand (operand, 0x1F, t); | |
1355 | bytes[0] |= operand->exp.X_add_number & 31; | |
252b5132 RH |
1356 | break; |
1357 | case L_8: | |
7ee7b84d | 1358 | case L_8U: |
252b5132 | 1359 | check_operand (operand, 0xff, t); |
7ee7b84d | 1360 | bytes[0] |= operand->exp.X_add_number; |
252b5132 RH |
1361 | break; |
1362 | case L_16: | |
7ee7b84d | 1363 | case L_16U: |
252b5132 | 1364 | check_operand (operand, 0xffff, t); |
7ee7b84d MS |
1365 | bytes[0] |= operand->exp.X_add_number >> 8; |
1366 | bytes[1] |= operand->exp.X_add_number >> 0; | |
bcb012d3 DD |
1367 | #ifdef OBJ_ELF |
1368 | /* MOVA needs both relocs to relax the second operand properly. */ | |
1369 | if (relaxmode != 0 | |
1370 | && (OP_KIND(this_try->opcode->how) == O_MOVAB | |
1371 | || OP_KIND(this_try->opcode->how) == O_MOVAW | |
1372 | || OP_KIND(this_try->opcode->how) == O_MOVAL)) | |
1373 | { | |
1374 | idx = BFD_RELOC_16; | |
1375 | fix_new_exp (frag_now, offset, 2, &operand->exp, 0, idx); | |
1376 | } | |
1377 | #endif | |
252b5132 RH |
1378 | break; |
1379 | case L_24: | |
1380 | check_operand (operand, 0xffffff, t); | |
7ee7b84d MS |
1381 | bytes[0] |= operand->exp.X_add_number >> 16; |
1382 | bytes[1] |= operand->exp.X_add_number >> 8; | |
1383 | bytes[2] |= operand->exp.X_add_number >> 0; | |
252b5132 RH |
1384 | break; |
1385 | ||
1386 | case L_32: | |
70d6ecf3 | 1387 | /* This should be done with bfd. */ |
7ee7b84d MS |
1388 | bytes[0] |= operand->exp.X_add_number >> 24; |
1389 | bytes[1] |= operand->exp.X_add_number >> 16; | |
1390 | bytes[2] |= operand->exp.X_add_number >> 8; | |
1391 | bytes[3] |= operand->exp.X_add_number >> 0; | |
4132022d AM |
1392 | if (relaxmode != 0) |
1393 | { | |
1394 | idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1; | |
1395 | fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx); | |
1396 | } | |
252b5132 RH |
1397 | break; |
1398 | } | |
252b5132 RH |
1399 | } |
1400 | else | |
1401 | { | |
1402 | switch (operand->mode & SIZE) | |
1403 | { | |
252b5132 RH |
1404 | case L_24: |
1405 | case L_32: | |
1406 | size = 4; | |
1407 | where = (operand->mode & SIZE) == L_24 ? -1 : 0; | |
1408 | if (relaxmode == 2) | |
1409 | idx = R_MOV24B1; | |
1410 | else if (relaxmode == 1) | |
1411 | idx = R_MOVL1; | |
1412 | else | |
1413 | idx = R_RELLONG; | |
1414 | break; | |
1415 | default: | |
70d6ecf3 | 1416 | as_bad (_("Can't work out size of operand.\n")); |
252b5132 | 1417 | case L_16: |
7ee7b84d | 1418 | case L_16U: |
252b5132 RH |
1419 | size = 2; |
1420 | where = 0; | |
1421 | if (relaxmode == 2) | |
1422 | idx = R_MOV16B1; | |
1423 | else | |
1424 | idx = R_RELWORD; | |
4132022d AM |
1425 | operand->exp.X_add_number = |
1426 | ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
7ee7b84d | 1427 | operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1]; |
252b5132 RH |
1428 | break; |
1429 | case L_8: | |
1430 | size = 1; | |
1431 | where = 0; | |
1432 | idx = R_RELBYTE; | |
4132022d AM |
1433 | operand->exp.X_add_number = |
1434 | ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
7ee7b84d | 1435 | operand->exp.X_add_number |= bytes[0]; |
252b5132 RH |
1436 | } |
1437 | ||
1438 | fix_new_exp (frag_now, | |
1439 | offset + where, | |
1440 | size, | |
1441 | &operand->exp, | |
1442 | 0, | |
1443 | idx); | |
1444 | } | |
252b5132 RH |
1445 | } |
1446 | ||
70d6ecf3 | 1447 | /* Now we know what sort of opcodes it is, let's build the bytes. */ |
3048287a | 1448 | |
252b5132 | 1449 | static void |
b54a3392 | 1450 | build_bytes (const struct h8_instruction *this_try, struct h8_op *operand) |
252b5132 | 1451 | { |
3048287a | 1452 | int i; |
252b5132 | 1453 | char *output = frag_more (this_try->length); |
d1e50f8a | 1454 | const op_type *nibble_ptr = this_try->opcode->data.nib; |
252b5132 RH |
1455 | op_type c; |
1456 | unsigned int nibble_count = 0; | |
7ee7b84d | 1457 | int op_at[3]; |
3048287a | 1458 | int nib = 0; |
252b5132 | 1459 | int movb = 0; |
7ee7b84d | 1460 | char asnibbles[100]; |
252b5132 | 1461 | char *p = asnibbles; |
7ee7b84d | 1462 | int high, low; |
252b5132 | 1463 | |
d4ea8842 | 1464 | if (!Hmode && this_try->opcode->available != AV_H8) |
252b5132 | 1465 | as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"), |
a720f7bc | 1466 | this_try->opcode->name); |
d4ea8842 MS |
1467 | else if (!Smode |
1468 | && this_try->opcode->available != AV_H8 | |
1469 | && this_try->opcode->available != AV_H8H) | |
1470 | as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"), | |
1471 | this_try->opcode->name); | |
1472 | else if (!SXmode | |
1473 | && this_try->opcode->available != AV_H8 | |
1474 | && this_try->opcode->available != AV_H8H | |
1475 | && this_try->opcode->available != AV_H8S) | |
1476 | as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"), | |
1477 | this_try->opcode->name); | |
252b5132 | 1478 | |
7ee7b84d | 1479 | while (*nibble_ptr != (op_type) E) |
252b5132 RH |
1480 | { |
1481 | int d; | |
7ee7b84d MS |
1482 | |
1483 | nib = 0; | |
252b5132 RH |
1484 | c = *nibble_ptr++; |
1485 | ||
7ee7b84d | 1486 | d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0; |
252b5132 RH |
1487 | |
1488 | if (c < 16) | |
3048287a | 1489 | nib = c; |
252b5132 RH |
1490 | else |
1491 | { | |
7ee7b84d MS |
1492 | int c2 = c & MODE; |
1493 | ||
1494 | if (c2 == REG || c2 == LOWREG | |
1495 | || c2 == IND || c2 == PREINC || c2 == PREDEC | |
1496 | || c2 == POSTINC || c2 == POSTDEC) | |
1497 | { | |
1498 | nib = operand[d].reg; | |
1499 | if (c2 == LOWREG) | |
1500 | nib &= 7; | |
1501 | } | |
1502 | ||
1503 | else if (c & CTRL) /* Control reg operand. */ | |
3048287a NC |
1504 | nib = operand[d].reg; |
1505 | ||
252b5132 | 1506 | else if ((c & DISPREG) == (DISPREG)) |
7ee7b84d MS |
1507 | { |
1508 | nib = operand[d].reg; | |
1509 | } | |
1510 | else if (c2 == ABS) | |
252b5132 RH |
1511 | { |
1512 | operand[d].mode = c; | |
7ee7b84d | 1513 | op_at[d] = nibble_count; |
252b5132 RH |
1514 | nib = 0; |
1515 | } | |
7ee7b84d MS |
1516 | else if (c2 == IMM || c2 == PCREL || c2 == ABS |
1517 | || (c & ABSJMP) || c2 == DISP) | |
252b5132 RH |
1518 | { |
1519 | operand[d].mode = c; | |
7ee7b84d | 1520 | op_at[d] = nibble_count; |
252b5132 RH |
1521 | nib = 0; |
1522 | } | |
7ee7b84d | 1523 | else if ((c & IGNORE) || (c & DATA)) |
3048287a NC |
1524 | nib = 0; |
1525 | ||
7ee7b84d | 1526 | else if (c2 == DBIT) |
252b5132 RH |
1527 | { |
1528 | switch (operand[0].exp.X_add_number) | |
1529 | { | |
1530 | case 1: | |
1531 | nib = c; | |
1532 | break; | |
1533 | case 2: | |
1534 | nib = 0x8 | c; | |
1535 | break; | |
1536 | default: | |
1537 | as_bad (_("Need #1 or #2 here")); | |
1538 | } | |
1539 | } | |
7ee7b84d | 1540 | else if (c2 == KBIT) |
252b5132 RH |
1541 | { |
1542 | switch (operand[0].exp.X_add_number) | |
1543 | { | |
1544 | case 1: | |
1545 | nib = 0; | |
1546 | break; | |
1547 | case 2: | |
1548 | nib = 8; | |
1549 | break; | |
1550 | case 4: | |
1551 | if (!Hmode) | |
1552 | as_warn (_("#4 not valid on H8/300.")); | |
1553 | nib = 9; | |
1554 | break; | |
1555 | ||
1556 | default: | |
1557 | as_bad (_("Need #1 or #2 here")); | |
1558 | break; | |
1559 | } | |
70d6ecf3 | 1560 | /* Stop it making a fix. */ |
252b5132 RH |
1561 | operand[0].mode = 0; |
1562 | } | |
1563 | ||
1564 | if (c & MEMRELAX) | |
3048287a | 1565 | operand[d].mode |= MEMRELAX; |
252b5132 RH |
1566 | |
1567 | if (c & B31) | |
3048287a | 1568 | nib |= 0x8; |
252b5132 | 1569 | |
7ee7b84d MS |
1570 | if (c & B21) |
1571 | nib |= 0x4; | |
1572 | ||
1573 | if (c & B11) | |
1574 | nib |= 0x2; | |
1575 | ||
1576 | if (c & B01) | |
1577 | nib |= 0x1; | |
1578 | ||
1579 | if (c2 == MACREG) | |
252b5132 | 1580 | { |
f0c56b90 NC |
1581 | if (operand[0].mode == MACREG) |
1582 | /* stmac has mac[hl] as the first operand. */ | |
1583 | nib = 2 + operand[0].reg; | |
1584 | else | |
1585 | /* ldmac has mac[hl] as the second operand. */ | |
1586 | nib = 2 + operand[1].reg; | |
252b5132 RH |
1587 | } |
1588 | } | |
1589 | nibble_count++; | |
1590 | ||
1591 | *p++ = nib; | |
1592 | } | |
1593 | ||
1594 | /* Disgusting. Why, oh why didn't someone ask us for advice | |
1595 | on the assembler format. */ | |
7ee7b84d | 1596 | if (OP_KIND (this_try->opcode->how) == O_LDM) |
252b5132 | 1597 | { |
7ee7b84d MS |
1598 | high = (operand[1].reg >> 8) & 0xf; |
1599 | low = (operand[1].reg) & 0xf; | |
252b5132 | 1600 | asnibbles[2] = high - low; |
7ee7b84d MS |
1601 | asnibbles[7] = high; |
1602 | } | |
1603 | else if (OP_KIND (this_try->opcode->how) == O_STM) | |
1604 | { | |
1605 | high = (operand[0].reg >> 8) & 0xf; | |
1606 | low = (operand[0].reg) & 0xf; | |
1607 | asnibbles[2] = high - low; | |
1608 | asnibbles[7] = low; | |
252b5132 RH |
1609 | } |
1610 | ||
1611 | for (i = 0; i < this_try->length; i++) | |
3048287a | 1612 | output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1]; |
252b5132 | 1613 | |
ca9a79a1 NC |
1614 | /* Note if this is a movb or a bit manipulation instruction |
1615 | there is a special relaxation which only applies. */ | |
1616 | if ( this_try->opcode->how == O (O_MOV, SB) | |
1617 | || this_try->opcode->how == O (O_BCLR, SB) | |
1618 | || this_try->opcode->how == O (O_BAND, SB) | |
1619 | || this_try->opcode->how == O (O_BIAND, SB) | |
1620 | || this_try->opcode->how == O (O_BILD, SB) | |
1621 | || this_try->opcode->how == O (O_BIOR, SB) | |
1622 | || this_try->opcode->how == O (O_BIST, SB) | |
1623 | || this_try->opcode->how == O (O_BIXOR, SB) | |
1624 | || this_try->opcode->how == O (O_BLD, SB) | |
1625 | || this_try->opcode->how == O (O_BNOT, SB) | |
1626 | || this_try->opcode->how == O (O_BOR, SB) | |
1627 | || this_try->opcode->how == O (O_BSET, SB) | |
1628 | || this_try->opcode->how == O (O_BST, SB) | |
1629 | || this_try->opcode->how == O (O_BTST, SB) | |
1630 | || this_try->opcode->how == O (O_BXOR, SB)) | |
252b5132 RH |
1631 | movb = 1; |
1632 | ||
70d6ecf3 | 1633 | /* Output any fixes. */ |
7ee7b84d | 1634 | for (i = 0; i < this_try->noperands; i++) |
252b5132 RH |
1635 | { |
1636 | int x = operand[i].mode; | |
7ee7b84d | 1637 | int x_mode = x & MODE; |
252b5132 | 1638 | |
7ee7b84d MS |
1639 | if (x_mode == IMM || x_mode == DISP) |
1640 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, | |
bcb012d3 DD |
1641 | op_at[i] & 1, operand + i, (x & MEMRELAX) != 0, |
1642 | this_try); | |
3048287a | 1643 | |
7ee7b84d MS |
1644 | else if (x_mode == ABS) |
1645 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, | |
1646 | op_at[i] & 1, operand + i, | |
bcb012d3 DD |
1647 | (x & MEMRELAX) ? movb + 1 : 0, |
1648 | this_try); | |
3048287a | 1649 | |
7ee7b84d | 1650 | else if (x_mode == PCREL) |
252b5132 | 1651 | { |
7ee7b84d | 1652 | int size16 = (x & SIZE) == L_16; |
252b5132 RH |
1653 | int size = size16 ? 2 : 1; |
1654 | int type = size16 ? R_PCRWORD : R_PCRBYTE; | |
36ed2fff | 1655 | fixS *fixP; |
252b5132 RH |
1656 | |
1657 | check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@"); | |
1658 | ||
1659 | if (operand[i].exp.X_add_number & 1) | |
3048287a NC |
1660 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1661 | (unsigned long) operand->exp.X_add_number); | |
36ed2fff JL |
1662 | #ifndef OBJ_ELF |
1663 | /* The COFF port has always been off by one, changing it | |
1664 | now would be an incompatible change, so we leave it as-is. | |
1665 | ||
1666 | We don't want to do this for ELF as we want to be | |
1667 | compatible with the proposed ELF format from Hitachi. */ | |
252b5132 | 1668 | operand[i].exp.X_add_number -= 1; |
36ed2fff | 1669 | #endif |
7ee7b84d MS |
1670 | if (size16) |
1671 | { | |
1672 | operand[i].exp.X_add_number = | |
1673 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
1674 | } | |
1675 | else | |
1676 | { | |
1677 | operand[i].exp.X_add_number = | |
1678 | ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
1679 | } | |
1680 | ||
1681 | /* For BRA/S. */ | |
1682 | if (! size16) | |
1683 | operand[i].exp.X_add_number |= output[op_at[i] / 2]; | |
252b5132 | 1684 | |
36ed2fff | 1685 | fixP = fix_new_exp (frag_now, |
7ee7b84d | 1686 | output - frag_now->fr_literal + op_at[i] / 2, |
36ed2fff JL |
1687 | size, |
1688 | &operand[i].exp, | |
1689 | 1, | |
1690 | type); | |
1691 | fixP->fx_signed = 1; | |
252b5132 | 1692 | } |
7ee7b84d | 1693 | else if (x_mode == MEMIND) |
252b5132 | 1694 | { |
252b5132 RH |
1695 | check_operand (operand + i, 0xff, "@@"); |
1696 | fix_new_exp (frag_now, | |
1697 | output - frag_now->fr_literal + 1, | |
1698 | 1, | |
1699 | &operand[i].exp, | |
1700 | 0, | |
1701 | R_MEM_INDIRECT); | |
1702 | } | |
7ee7b84d MS |
1703 | else if (x_mode == VECIND) |
1704 | { | |
1705 | check_operand (operand + i, 0x7f, "@@"); | |
1706 | /* FIXME: approximating the effect of "B31" here... | |
1707 | This is very hackish, and ought to be done a better way. */ | |
1708 | operand[i].exp.X_add_number |= 0x80; | |
1709 | fix_new_exp (frag_now, | |
1710 | output - frag_now->fr_literal + 1, | |
1711 | 1, | |
1712 | &operand[i].exp, | |
1713 | 0, | |
1714 | R_MEM_INDIRECT); | |
1715 | } | |
252b5132 RH |
1716 | else if (x & ABSJMP) |
1717 | { | |
3c1ba8a3 | 1718 | int where = 0; |
7ee7b84d | 1719 | bfd_reloc_code_real_type reloc_type = R_JMPL1; |
3c1ba8a3 JL |
1720 | |
1721 | #ifdef OBJ_ELF | |
1722 | /* To be compatible with the proposed H8 ELF format, we | |
1723 | want the relocation's offset to point to the first byte | |
1724 | that will be modified, not to the start of the instruction. */ | |
7ee7b84d MS |
1725 | |
1726 | if ((operand->mode & SIZE) == L_32) | |
1727 | { | |
1728 | where = 2; | |
1729 | reloc_type = R_RELLONG; | |
1730 | } | |
1731 | else | |
1732 | where = 1; | |
3c1ba8a3 | 1733 | #endif |
de342d07 | 1734 | |
70d6ecf3 | 1735 | /* This jmp may be a jump or a branch. */ |
252b5132 | 1736 | |
7ee7b84d MS |
1737 | check_operand (operand + i, |
1738 | SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff, | |
1739 | "@"); | |
3048287a | 1740 | |
252b5132 | 1741 | if (operand[i].exp.X_add_number & 1) |
3048287a NC |
1742 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1743 | (unsigned long) operand->exp.X_add_number); | |
1744 | ||
252b5132 | 1745 | if (!Hmode) |
70d6ecf3 | 1746 | operand[i].exp.X_add_number = |
4132022d | 1747 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; |
252b5132 | 1748 | fix_new_exp (frag_now, |
3c1ba8a3 | 1749 | output - frag_now->fr_literal + where, |
252b5132 RH |
1750 | 4, |
1751 | &operand[i].exp, | |
1752 | 0, | |
7ee7b84d | 1753 | reloc_type); |
252b5132 RH |
1754 | } |
1755 | } | |
252b5132 RH |
1756 | } |
1757 | ||
70d6ecf3 AM |
1758 | /* Try to give an intelligent error message for common and simple to |
1759 | detect errors. */ | |
3048287a | 1760 | |
252b5132 | 1761 | static void |
b54a3392 KH |
1762 | clever_message (const struct h8_instruction *instruction, |
1763 | struct h8_op *operand) | |
252b5132 | 1764 | { |
70d6ecf3 | 1765 | /* Find out if there was more than one possible opcode. */ |
252b5132 | 1766 | |
a720f7bc | 1767 | if ((instruction + 1)->idx != instruction->idx) |
252b5132 | 1768 | { |
3048287a | 1769 | int argn; |
252b5132 | 1770 | |
70d6ecf3 AM |
1771 | /* Only one opcode of this flavour, try to guess which operand |
1772 | didn't match. */ | |
a720f7bc | 1773 | for (argn = 0; argn < instruction->noperands; argn++) |
252b5132 | 1774 | { |
a720f7bc | 1775 | switch (instruction->opcode->args.nib[argn]) |
252b5132 RH |
1776 | { |
1777 | case RD16: | |
1778 | if (operand[argn].mode != RD16) | |
1779 | { | |
1780 | as_bad (_("destination operand must be 16 bit register")); | |
1781 | return; | |
1782 | ||
1783 | } | |
1784 | break; | |
1785 | ||
1786 | case RS8: | |
252b5132 RH |
1787 | if (operand[argn].mode != RS8) |
1788 | { | |
1789 | as_bad (_("source operand must be 8 bit register")); | |
1790 | return; | |
1791 | } | |
1792 | break; | |
1793 | ||
1794 | case ABS16DST: | |
1795 | if (operand[argn].mode != ABS16DST) | |
1796 | { | |
1797 | as_bad (_("destination operand must be 16bit absolute address")); | |
1798 | return; | |
1799 | } | |
1800 | break; | |
1801 | case RD8: | |
1802 | if (operand[argn].mode != RD8) | |
1803 | { | |
1804 | as_bad (_("destination operand must be 8 bit register")); | |
1805 | return; | |
1806 | } | |
1807 | break; | |
1808 | ||
252b5132 RH |
1809 | case ABS16SRC: |
1810 | if (operand[argn].mode != ABS16SRC) | |
1811 | { | |
1812 | as_bad (_("source operand must be 16bit absolute address")); | |
1813 | return; | |
1814 | } | |
1815 | break; | |
1816 | ||
1817 | } | |
1818 | } | |
1819 | } | |
1820 | as_bad (_("invalid operands")); | |
1821 | } | |
1822 | ||
d4ea8842 | 1823 | |
1b680e4f RS |
1824 | /* If OPERAND is part of an address, adjust its size and value given |
1825 | that it addresses SIZE bytes. | |
d4ea8842 | 1826 | |
1b680e4f RS |
1827 | This function decides how big non-immediate constants are when no |
1828 | size was explicitly given. It also scales down the assembly-level | |
d4ea8842 MS |
1829 | displacement in an @(d:2,ERn) operand. */ |
1830 | ||
1831 | static void | |
b54a3392 | 1832 | fix_operand_size (struct h8_op *operand, int size) |
d4ea8842 | 1833 | { |
1b680e4f | 1834 | if (SXmode && (operand->mode & MODE) == DISP) |
d4ea8842 MS |
1835 | { |
1836 | /* If the user didn't specify an operand width, see if we | |
1837 | can use @(d:2,ERn). */ | |
1b680e4f RS |
1838 | if ((operand->mode & SIZE) == 0 |
1839 | && operand->exp.X_add_symbol == 0 | |
1840 | && operand->exp.X_op_symbol == 0 | |
d4ea8842 MS |
1841 | && (operand->exp.X_add_number == size |
1842 | || operand->exp.X_add_number == size * 2 | |
1843 | || operand->exp.X_add_number == size * 3)) | |
1844 | operand->mode |= L_2; | |
1845 | ||
1846 | /* Scale down the displacement in an @(d:2,ERn) operand. | |
1847 | X_add_number then contains the desired field value. */ | |
1848 | if ((operand->mode & SIZE) == L_2) | |
1849 | { | |
1850 | if (operand->exp.X_add_number % size != 0) | |
1851 | as_warn (_("operand/size mis-match")); | |
1852 | operand->exp.X_add_number /= size; | |
1853 | } | |
1854 | } | |
1855 | ||
d4ea8842 MS |
1856 | if ((operand->mode & SIZE) == 0) |
1857 | switch (operand->mode & MODE) | |
1858 | { | |
1859 | case DISP: | |
1860 | case INDEXB: | |
1861 | case INDEXW: | |
1862 | case INDEXL: | |
1863 | case ABS: | |
1b680e4f RS |
1864 | /* Pick a 24-bit address unless we know that a 16-bit address |
1865 | is safe. get_specific() will relax L_24 into L_32 where | |
1866 | necessary. */ | |
1867 | if (Hmode | |
d4e2de6b | 1868 | && !Nmode |
1b680e4f RS |
1869 | && (operand->exp.X_add_number < -32768 |
1870 | || operand->exp.X_add_number > 32767 | |
1871 | || operand->exp.X_add_symbol != 0 | |
1872 | || operand->exp.X_op_symbol != 0)) | |
1873 | operand->mode |= L_24; | |
1874 | else | |
1875 | operand->mode |= L_16; | |
1876 | break; | |
1877 | ||
1878 | case PCREL: | |
1879 | /* This condition is long standing, though somewhat suspect. */ | |
1880 | if (operand->exp.X_add_number > -128 | |
1881 | && operand->exp.X_add_number < 127) | |
cc189afc DD |
1882 | { |
1883 | if (operand->exp.X_add_symbol != NULL) | |
1884 | operand->mode |= bsize; | |
1885 | else | |
1886 | operand->mode |= L_8; | |
1887 | } | |
1b680e4f RS |
1888 | else |
1889 | operand->mode |= L_16; | |
d4ea8842 MS |
1890 | break; |
1891 | } | |
1892 | } | |
1893 | ||
1894 | ||
70d6ecf3 AM |
1895 | /* This is the guts of the machine-dependent assembler. STR points to |
1896 | a machine dependent instruction. This function is supposed to emit | |
1897 | the frags/bytes it assembles. */ | |
3048287a | 1898 | |
252b5132 | 1899 | void |
b54a3392 | 1900 | md_assemble (char *str) |
252b5132 RH |
1901 | { |
1902 | char *op_start; | |
1903 | char *op_end; | |
7ee7b84d | 1904 | struct h8_op operand[3]; |
a720f7bc KD |
1905 | const struct h8_instruction *instruction; |
1906 | const struct h8_instruction *prev_instruction; | |
252b5132 RH |
1907 | |
1908 | char *dot = 0; | |
0c0b9be0 | 1909 | char *slash = 0; |
252b5132 | 1910 | char c; |
7ee7b84d | 1911 | int size, i; |
252b5132 | 1912 | |
70d6ecf3 | 1913 | /* Drop leading whitespace. */ |
252b5132 RH |
1914 | while (*str == ' ') |
1915 | str++; | |
1916 | ||
70d6ecf3 | 1917 | /* Find the op code end. */ |
252b5132 RH |
1918 | for (op_start = op_end = str; |
1919 | *op_end != 0 && *op_end != ' '; | |
1920 | op_end++) | |
1921 | { | |
1922 | if (*op_end == '.') | |
1923 | { | |
1924 | dot = op_end + 1; | |
1925 | *op_end = 0; | |
1926 | op_end += 2; | |
1927 | break; | |
1928 | } | |
0c0b9be0 AO |
1929 | else if (*op_end == '/' && ! slash) |
1930 | slash = op_end; | |
252b5132 RH |
1931 | } |
1932 | ||
252b5132 RH |
1933 | if (op_end == op_start) |
1934 | { | |
1935 | as_bad (_("can't find opcode ")); | |
1936 | } | |
1937 | c = *op_end; | |
1938 | ||
1939 | *op_end = 0; | |
1940 | ||
0c0b9be0 AO |
1941 | /* The assembler stops scanning the opcode at slashes, so it fails |
1942 | to make characters following them lower case. Fix them. */ | |
1943 | if (slash) | |
1944 | while (*++slash) | |
1945 | *slash = TOLOWER (*slash); | |
1946 | ||
a720f7bc KD |
1947 | instruction = (const struct h8_instruction *) |
1948 | hash_find (opcode_hash_control, op_start); | |
252b5132 | 1949 | |
a720f7bc | 1950 | if (instruction == NULL) |
252b5132 RH |
1951 | { |
1952 | as_bad (_("unknown opcode")); | |
1953 | return; | |
1954 | } | |
1955 | ||
70d6ecf3 | 1956 | /* We used to set input_line_pointer to the result of get_operands, |
252b5132 RH |
1957 | but that is wrong. Our caller assumes we don't change it. */ |
1958 | ||
7ee7b84d MS |
1959 | operand[0].mode = 0; |
1960 | operand[1].mode = 0; | |
1961 | operand[2].mode = 0; | |
1962 | ||
1963 | if (OP_KIND (instruction->opcode->how) == O_MOVAB | |
1964 | || OP_KIND (instruction->opcode->how) == O_MOVAW | |
1965 | || OP_KIND (instruction->opcode->how) == O_MOVAL) | |
1966 | get_mova_operands (op_end, operand); | |
1967 | else if (OP_KIND (instruction->opcode->how) == O_RTEL | |
1968 | || OP_KIND (instruction->opcode->how) == O_RTSL) | |
1969 | get_rtsl_operands (op_end, operand); | |
1970 | else | |
1971 | get_operands (instruction->noperands, op_end, operand); | |
1972 | ||
252b5132 | 1973 | *op_end = c; |
a720f7bc | 1974 | prev_instruction = instruction; |
252b5132 | 1975 | |
4892e510 NC |
1976 | /* Now we have operands from instruction. |
1977 | Let's check them out for ldm and stm. */ | |
1978 | if (OP_KIND (instruction->opcode->how) == O_LDM) | |
1979 | { | |
1980 | /* The first operand must be @er7+, and the | |
1981 | second operand must be a register pair. */ | |
1982 | if ((operand[0].mode != RSINC) | |
1983 | || (operand[0].reg != 7) | |
1984 | || ((operand[1].reg & 0x80000000) == 0)) | |
1985 | as_bad (_("invalid operand in ldm")); | |
1986 | } | |
1987 | else if (OP_KIND (instruction->opcode->how) == O_STM) | |
1988 | { | |
1989 | /* The first operand must be a register pair, | |
1990 | and the second operand must be @-er7. */ | |
1991 | if (((operand[0].reg & 0x80000000) == 0) | |
1992 | || (operand[1].mode != RDDEC) | |
1993 | || (operand[1].reg != 7)) | |
1994 | as_bad (_("invalid operand in stm")); | |
1995 | } | |
1996 | ||
252b5132 RH |
1997 | size = SN; |
1998 | if (dot) | |
1999 | { | |
0c0b9be0 | 2000 | switch (TOLOWER (*dot)) |
252b5132 RH |
2001 | { |
2002 | case 'b': | |
2003 | size = SB; | |
2004 | break; | |
2005 | ||
2006 | case 'w': | |
2007 | size = SW; | |
2008 | break; | |
2009 | ||
2010 | case 'l': | |
2011 | size = SL; | |
2012 | break; | |
2013 | } | |
2014 | } | |
7ee7b84d MS |
2015 | if (OP_KIND (instruction->opcode->how) == O_MOVAB || |
2016 | OP_KIND (instruction->opcode->how) == O_MOVAW || | |
2017 | OP_KIND (instruction->opcode->how) == O_MOVAL) | |
252b5132 | 2018 | { |
d4ea8842 MS |
2019 | switch (operand[0].mode & MODE) |
2020 | { | |
7ee7b84d MS |
2021 | case INDEXB: |
2022 | default: | |
d4ea8842 | 2023 | fix_operand_size (&operand[1], 1); |
7ee7b84d MS |
2024 | break; |
2025 | case INDEXW: | |
d4ea8842 | 2026 | fix_operand_size (&operand[1], 2); |
7ee7b84d MS |
2027 | break; |
2028 | case INDEXL: | |
d4ea8842 | 2029 | fix_operand_size (&operand[1], 4); |
7ee7b84d | 2030 | break; |
252b5132 RH |
2031 | } |
2032 | } | |
7ee7b84d MS |
2033 | else |
2034 | { | |
d4ea8842 MS |
2035 | for (i = 0; i < 3 && operand[i].mode != 0; i++) |
2036 | switch (size) | |
2037 | { | |
7ee7b84d MS |
2038 | case SN: |
2039 | case SB: | |
2040 | default: | |
d4ea8842 | 2041 | fix_operand_size (&operand[i], 1); |
7ee7b84d MS |
2042 | break; |
2043 | case SW: | |
d4ea8842 | 2044 | fix_operand_size (&operand[i], 2); |
7ee7b84d MS |
2045 | break; |
2046 | case SL: | |
d4ea8842 | 2047 | fix_operand_size (&operand[i], 4); |
7ee7b84d MS |
2048 | break; |
2049 | } | |
2050 | } | |
252b5132 | 2051 | |
d4ea8842 MS |
2052 | instruction = get_specific (instruction, operand, size); |
2053 | ||
2054 | if (instruction == 0) | |
2055 | { | |
2056 | /* Couldn't find an opcode which matched the operands. */ | |
2057 | char *where = frag_more (2); | |
2058 | ||
2059 | where[0] = 0x0; | |
2060 | where[1] = 0x0; | |
2061 | clever_message (prev_instruction, operand); | |
2062 | ||
2063 | return; | |
2064 | } | |
2065 | ||
a720f7bc | 2066 | build_bytes (instruction, operand); |
2c8714f2 | 2067 | |
2c8714f2 | 2068 | dwarf2_emit_insn (instruction->length); |
252b5132 RH |
2069 | } |
2070 | ||
2071 | symbolS * | |
b54a3392 | 2072 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
2073 | { |
2074 | return 0; | |
2075 | } | |
2076 | ||
499ac353 | 2077 | /* Various routines to kill one day. */ |
bc0d738a | 2078 | |
252b5132 | 2079 | char * |
b54a3392 | 2080 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 2081 | { |
499ac353 | 2082 | return ieee_md_atof (type, litP, sizeP, TRUE); |
252b5132 RH |
2083 | } |
2084 | \f | |
6fd4f6cc DD |
2085 | #define OPTION_H_TICK_HEX (OPTION_MD_BASE) |
2086 | ||
5a38dc70 | 2087 | const char *md_shortopts = ""; |
252b5132 | 2088 | struct option md_longopts[] = { |
6fd4f6cc | 2089 | { "h-tick-hex", no_argument, NULL, OPTION_H_TICK_HEX }, |
252b5132 RH |
2090 | {NULL, no_argument, NULL, 0} |
2091 | }; | |
70d6ecf3 AM |
2092 | |
2093 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
2094 | |
2095 | int | |
b54a3392 | 2096 | md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED) |
252b5132 | 2097 | { |
6fd4f6cc DD |
2098 | switch (c) |
2099 | { | |
2100 | case OPTION_H_TICK_HEX: | |
2101 | enable_h_tick_hex = 1; | |
2102 | break; | |
2103 | ||
2104 | default: | |
2105 | return 0; | |
2106 | } | |
2107 | return 1; | |
252b5132 RH |
2108 | } |
2109 | ||
2110 | void | |
b54a3392 | 2111 | md_show_usage (FILE *stream ATTRIBUTE_UNUSED) |
252b5132 RH |
2112 | { |
2113 | } | |
2114 | \f | |
b54a3392 | 2115 | void tc_aout_fix_to_chars (void); |
3048287a | 2116 | |
252b5132 | 2117 | void |
b54a3392 | 2118 | tc_aout_fix_to_chars (void) |
252b5132 RH |
2119 | { |
2120 | printf (_("call to tc_aout_fix_to_chars \n")); | |
2121 | abort (); | |
2122 | } | |
2123 | ||
2124 | void | |
7be1c489 | 2125 | md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, |
b54a3392 KH |
2126 | segT seg ATTRIBUTE_UNUSED, |
2127 | fragS *fragP ATTRIBUTE_UNUSED) | |
252b5132 RH |
2128 | { |
2129 | printf (_("call to md_convert_frag \n")); | |
2130 | abort (); | |
2131 | } | |
2132 | ||
3c1ba8a3 | 2133 | valueT |
b54a3392 | 2134 | md_section_align (segT segment, valueT size) |
3c1ba8a3 JL |
2135 | { |
2136 | int align = bfd_get_section_alignment (stdoutput, segment); | |
2137 | return ((size + (1 << align) - 1) & (-1 << align)); | |
2138 | } | |
252b5132 RH |
2139 | |
2140 | void | |
55cf6793 | 2141 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 RH |
2142 | { |
2143 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
a161fe53 | 2144 | long val = *valP; |
252b5132 RH |
2145 | |
2146 | switch (fixP->fx_size) | |
2147 | { | |
2148 | case 1: | |
2149 | *buf++ = val; | |
2150 | break; | |
2151 | case 2: | |
2152 | *buf++ = (val >> 8); | |
2153 | *buf++ = val; | |
2154 | break; | |
2155 | case 4: | |
2156 | *buf++ = (val >> 24); | |
2157 | *buf++ = (val >> 16); | |
2158 | *buf++ = (val >> 8); | |
2159 | *buf++ = val; | |
2160 | break; | |
550c1888 NC |
2161 | case 8: |
2162 | /* This can arise when the .quad or .8byte pseudo-ops are used. | |
2163 | Returning here (without setting fx_done) will cause the code | |
2164 | to attempt to generate a reloc which will then fail with the | |
2165 | slightly more helpful error message: "Cannot represent | |
2166 | relocation type BFD_RELOC_64". */ | |
2167 | return; | |
252b5132 RH |
2168 | default: |
2169 | abort (); | |
2170 | } | |
94f592af NC |
2171 | |
2172 | if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) | |
2173 | fixP->fx_done = 1; | |
252b5132 RH |
2174 | } |
2175 | ||
2176 | int | |
c85dd50d NC |
2177 | md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, |
2178 | segT segment_type ATTRIBUTE_UNUSED) | |
252b5132 | 2179 | { |
c85dd50d | 2180 | printf (_("call to md_estimate_size_before_relax \n")); |
252b5132 RH |
2181 | abort (); |
2182 | } | |
2183 | ||
70d6ecf3 | 2184 | /* Put number into target byte order. */ |
252b5132 | 2185 | void |
b54a3392 | 2186 | md_number_to_chars (char *ptr, valueT use, int nbytes) |
252b5132 RH |
2187 | { |
2188 | number_to_chars_bigendian (ptr, use, nbytes); | |
2189 | } | |
70d6ecf3 | 2190 | |
252b5132 | 2191 | long |
52b010e4 | 2192 | md_pcrel_from (fixS *fixp) |
252b5132 | 2193 | { |
52b010e4 NC |
2194 | as_bad_where (fixp->fx_file, fixp->fx_line, |
2195 | _("Unexpected reference to a symbol in a non-code section")); | |
2196 | return 0; | |
252b5132 RH |
2197 | } |
2198 | ||
f333765f | 2199 | arelent * |
b54a3392 | 2200 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
f333765f JL |
2201 | { |
2202 | arelent *rel; | |
2203 | bfd_reloc_code_real_type r_type; | |
2204 | ||
de342d07 JL |
2205 | if (fixp->fx_addsy && fixp->fx_subsy) |
2206 | { | |
2207 | if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy)) | |
2208 | || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section) | |
2209 | { | |
2210 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
c85dd50d | 2211 | _("Difference of symbols in different sections is not supported")); |
de342d07 JL |
2212 | return NULL; |
2213 | } | |
2214 | } | |
2215 | ||
c85dd50d NC |
2216 | rel = xmalloc (sizeof (arelent)); |
2217 | rel->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); | |
f333765f JL |
2218 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
2219 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
2220 | rel->addend = fixp->fx_offset; | |
2221 | ||
2222 | r_type = fixp->fx_r_type; | |
2223 | ||
2224 | #define DEBUG 0 | |
2225 | #if DEBUG | |
2226 | fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type)); | |
c85dd50d | 2227 | fflush (stderr); |
f333765f JL |
2228 | #endif |
2229 | rel->howto = bfd_reloc_type_lookup (stdoutput, r_type); | |
2230 | if (rel->howto == NULL) | |
2231 | { | |
2232 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
2233 | _("Cannot represent relocation type %s"), | |
2234 | bfd_get_reloc_code_name (r_type)); | |
2235 | return NULL; | |
2236 | } | |
2237 | ||
2238 | return rel; | |
2239 | } |