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* configure.in (WIN32LDFLAGS): Rename to SHARED_LDFLAGS.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
e3bb37b5
L		 58static void set_code_flag (int);
59static void set_16bit_gcc_code_flag (int);
60static void set_intel_syntax (int);
db51cc60 61static void set_allow_index_reg (int);
e3bb37b5 62static void set_cpu_arch (int);
6482c264 63#ifdef TE_PE
e3bb37b5 64static void pe_directive_secrel (int);
6482c264 65#endif
e3bb37b5
L		 66static void signed_cons (int);
67static char *output_invalid (int c);
68static int i386_operand (char *);
69static int i386_intel_operand (char *, int);
70static const reg_entry *parse_register (char *, char **);
71static char *parse_insn (char *, char *);
72static char *parse_operands (char *, const char *);
73static void swap_operands (void);
4d456e3d 74static void swap_2_operands (int, int);
e3bb37b5
L		 75static void optimize_imm (void);
76static void optimize_disp (void);
77static int match_template (void);
78static int check_string (void);
79static int process_suffix (void);
80static int check_byte_reg (void);
81static int check_long_reg (void);
82static int check_qword_reg (void);
83static int check_word_reg (void);
84static int finalize_imm (void);
85f10a01 85static void process_drex (void);
e3bb37b5
L		 86static int process_operands (void);
87static const seg_entry *build_modrm_byte (void);
88static void output_insn (void);
89static void output_imm (fragS *, offsetT);
90static void output_disp (fragS *, offsetT);
29b0f896 91#ifndef I386COFF
e3bb37b5 92static void s_bss (int);
252b5132 93#endif
17d4e2a2
L		 94#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
95static void handle_large_common (int small ATTRIBUTE_UNUSED);
96#endif
252b5132 97
a847613f 98static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 99
252b5132 100/* 'md_assemble ()' gathers together information and puts it into a
47926f60 101 i386_insn. */
252b5132 102
520dc8e8
AM		 103union i386_op
104 {
105 expressionS *disps;
106 expressionS *imms;
107 const reg_entry *regs;
108 };
109
252b5132
RH		 110struct _i386_insn
111 {
47926f60 112 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 113 template tm;
114
115 /* SUFFIX holds the instruction mnemonic suffix if given.
116 (e.g. 'l' for 'movl') */
117 char suffix;
118
47926f60 119 /* OPERANDS gives the number of given operands. */
252b5132
RH		 120 unsigned int operands;
121
122 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
123 of given register, displacement, memory operands and immediate
47926f60 124 operands. */
252b5132
RH		 125 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
126
127 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 128 use OP[i] for the corresponding operand. */
40fb9820 129 i386_operand_type types[MAX_OPERANDS];
252b5132 130
520dc8e8
AM		 131 /* Displacement expression, immediate expression, or register for each
132 operand. */
133 union i386_op op[MAX_OPERANDS];
252b5132 134
3e73aa7c
JH		 135 /* Flags for operands. */
136 unsigned int flags[MAX_OPERANDS];
137#define Operand_PCrel 1
138
252b5132 139 /* Relocation type for operand */
f86103b7 140 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 141
252b5132
RH		 142 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
143 the base index byte below. */
144 const reg_entry *base_reg;
145 const reg_entry *index_reg;
146 unsigned int log2_scale_factor;
147
148 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 149 explicit segment overrides are given. */
ce8a8b2f 150 const seg_entry *seg[2];
252b5132
RH		 151
152 /* PREFIX holds all the given prefix opcodes (usually null).
153 PREFIXES is the number of prefix opcodes. */
154 unsigned int prefixes;
155 unsigned char prefix[MAX_PREFIXES];
156
157 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 158 addressing modes of this insn are encoded. DREX is the byte
159 added by the SSE5 instructions. */
252b5132
RH		 160
161 modrm_byte rm;
3e73aa7c 162 rex_byte rex;
252b5132 163 sib_byte sib;
85f10a01 164 drex_byte drex;
252b5132
RH		 165 };
166
167typedef struct _i386_insn i386_insn;
168
169/* List of chars besides those in app.c:symbol_chars that can start an
170 operand. Used to prevent the scrubber eating vital white-space. */
32137342 171const char extra_symbol_chars[] = "*%-(["
252b5132 172#ifdef LEX_AT
32137342
NC		 173 "@"
174#endif
175#ifdef LEX_QM
176 "?"
252b5132 177#endif
32137342 178 ;
252b5132 179
29b0f896
AM		 180#if (defined (TE_I386AIX) \
181 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 182 && !defined (TE_GNU) \
29b0f896 183 && !defined (TE_LINUX) \
32137342 184 && !defined (TE_NETWARE) \
29b0f896
AM		 185 && !defined (TE_FreeBSD) \
186 && !defined (TE_NetBSD)))
252b5132 187/* This array holds the chars that always start a comment. If the
b3b91714
AM		 188 pre-processor is disabled, these aren't very useful. The option
189 --divide will remove '/' from this list. */
190const char *i386_comment_chars = "#/";
191#define SVR4_COMMENT_CHARS 1
252b5132 192#define PREFIX_SEPARATOR '\\'
252b5132 193
b3b91714
AM		 194#else
195const char *i386_comment_chars = "#";
196#define PREFIX_SEPARATOR '/'
197#endif
198
252b5132
RH		 199/* This array holds the chars that only start a comment at the beginning of
200 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 201 .line and .file directives will appear in the pre-processed output.
202 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 203 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 204 #NO_APP at the beginning of its output.
205 Also note that comments started like this one will always work if
252b5132 206 '/' isn't otherwise defined. */
b3b91714 207const char line_comment_chars[] = "#/";
252b5132 208
63a0b638 209const char line_separator_chars[] = ";";
252b5132 210
ce8a8b2f
AM		 211/* Chars that can be used to separate mant from exp in floating point
212 nums. */
252b5132
RH		 213const char EXP_CHARS[] = "eE";
214
ce8a8b2f
AM		 215/* Chars that mean this number is a floating point constant
216 As in 0f12.456
217 or 0d1.2345e12. */
252b5132
RH		 218const char FLT_CHARS[] = "fFdDxX";
219
ce8a8b2f 220/* Tables for lexical analysis. */
252b5132
RH		 221static char mnemonic_chars[256];
222static char register_chars[256];
223static char operand_chars[256];
224static char identifier_chars[256];
225static char digit_chars[256];
226
ce8a8b2f 227/* Lexical macros. */
252b5132
RH		 228#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
229#define is_operand_char(x) (operand_chars[(unsigned char) x])
230#define is_register_char(x) (register_chars[(unsigned char) x])
231#define is_space_char(x) ((x) == ' ')
232#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
233#define is_digit_char(x) (digit_chars[(unsigned char) x])
234
0234cb7c 235/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 236static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
237
238/* md_assemble() always leaves the strings it's passed unaltered. To
239 effect this we maintain a stack of saved characters that we've smashed
240 with '\0's (indicating end of strings for various sub-fields of the
47926f60 241 assembler instruction). */
252b5132 242static char save_stack[32];
ce8a8b2f 243static char *save_stack_p;
252b5132
RH		 244#define END_STRING_AND_SAVE(s) \
245 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
246#define RESTORE_END_STRING(s) \
247 do { *(s) = *--save_stack_p; } while (0)
248
47926f60 249/* The instruction we're assembling. */
252b5132
RH		 250static i386_insn i;
251
252/* Possible templates for current insn. */
253static const templates *current_templates;
254
31b2323c
L		 255/* Per instruction expressionS buffers: max displacements & immediates. */
256static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
257static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 258
47926f60
KH		 259/* Current operand we are working on. */
260static int this_operand;
252b5132 261
3e73aa7c
JH		 262/* We support four different modes. FLAG_CODE variable is used to distinguish
263 these. */
264
265enum flag_code {
266 CODE_32BIT,
267 CODE_16BIT,
268 CODE_64BIT };
269
270static enum flag_code flag_code;
4fa24527 271static unsigned int object_64bit;
3e73aa7c
JH		 272static int use_rela_relocations = 0;
273
274/* The names used to print error messages. */
b77a7acd 275static const char *flag_code_names[] =
3e73aa7c
JH		 276 {
277 "32",
278 "16",
279 "64"
280 };
252b5132 281
47926f60
KH		 282/* 1 for intel syntax,
283 0 if att syntax. */
284static int intel_syntax = 0;
252b5132 285
47926f60
KH		 286/* 1 if register prefix % not required. */
287static int allow_naked_reg = 0;
252b5132 288
db51cc60
L		 289/* 1 if fake index register, eiz/riz, is allowed . */
290static int allow_index_reg = 0;
291
2ca3ace5
L		 292/* Register prefix used for error message. */
293static const char *register_prefix = "%";
294
47926f60
KH		 295/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
296 leave, push, and pop instructions so that gcc has the same stack
297 frame as in 32 bit mode. */
298static char stackop_size = '\0';
eecb386c 299
12b55ccc
L		 300/* Non-zero to optimize code alignment. */
301int optimize_align_code = 1;
302
47926f60
KH		 303/* Non-zero to quieten some warnings. */
304static int quiet_warnings = 0;
a38cf1db 305
47926f60
KH		 306/* CPU name. */
307static const char *cpu_arch_name = NULL;
5c6af06e 308static const char *cpu_sub_arch_name = NULL;
a38cf1db 309
47926f60 310/* CPU feature flags. */
40fb9820
L		 311static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
312
313/* Bitwise NOT of cpu_arch_flags. */
314static i386_cpu_flags cpu_arch_flags_not;
a38cf1db 315
ccc9c027
L		 316/* If we have selected a cpu we are generating instructions for. */
317static int cpu_arch_tune_set = 0;
318
9103f4f4
L		 319/* Cpu we are generating instructions for. */
320static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
321
322/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 323static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 324
ccc9c027
L		 325/* CPU instruction set architecture used. */
326static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
327
9103f4f4 328/* CPU feature flags of instruction set architecture used. */
40fb9820 329static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 330
fddf5b5b
AM		 331/* If set, conditional jumps are not automatically promoted to handle
332 larger than a byte offset. */
333static unsigned int no_cond_jump_promotion = 0;
334
29b0f896 335/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 336static symbolS *GOT_symbol;
29b0f896 337
a4447b93
RH		 338/* The dwarf2 return column, adjusted for 32 or 64 bit. */
339unsigned int x86_dwarf2_return_column;
340
341/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
342int x86_cie_data_alignment;
343
252b5132 344/* Interface to relax_segment.
fddf5b5b
AM		 345 There are 3 major relax states for 386 jump insns because the
346 different types of jumps add different sizes to frags when we're
347 figuring out what sort of jump to choose to reach a given label. */
252b5132 348
47926f60 349/* Types. */
93c2a809
AM		 350#define UNCOND_JUMP 0
351#define COND_JUMP 1
352#define COND_JUMP86 2
fddf5b5b 353
47926f60 354/* Sizes. */
252b5132
RH		 355#define CODE16 1
356#define SMALL 0
29b0f896 357#define SMALL16 (SMALL | CODE16)
252b5132 358#define BIG 2
29b0f896 359#define BIG16 (BIG | CODE16)
252b5132
RH		 360
361#ifndef INLINE
362#ifdef __GNUC__
363#define INLINE __inline__
364#else
365#define INLINE
366#endif
367#endif
368
fddf5b5b
AM		 369#define ENCODE_RELAX_STATE(type, size) \
370 ((relax_substateT) (((type) << 2) | (size)))
371#define TYPE_FROM_RELAX_STATE(s) \
372 ((s) >> 2)
373#define DISP_SIZE_FROM_RELAX_STATE(s) \
374 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 375
376/* This table is used by relax_frag to promote short jumps to long
377 ones where necessary. SMALL (short) jumps may be promoted to BIG
378 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
379 don't allow a short jump in a 32 bit code segment to be promoted to
380 a 16 bit offset jump because it's slower (requires data size
381 prefix), and doesn't work, unless the destination is in the bottom
382 64k of the code segment (The top 16 bits of eip are zeroed). */
383
384const relax_typeS md_relax_table[] =
385{
24eab124
AM		 386 /* The fields are:
387 1) most positive reach of this state,
388 2) most negative reach of this state,
93c2a809 389 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 390 4) which index into the table to try if we can't fit into this one. */
252b5132 391
fddf5b5b 392 /* UNCOND_JUMP states. */
93c2a809
AM		 393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
395 /* dword jmp adds 4 bytes to frag:
396 0 extra opcode bytes, 4 displacement bytes. */
252b5132 397 {0, 0, 4, 0},
93c2a809
AM		 398 /* word jmp adds 2 byte2 to frag:
399 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 400 {0, 0, 2, 0},
401
93c2a809
AM		 402 /* COND_JUMP states. */
403 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
405 /* dword conditionals adds 5 bytes to frag:
406 1 extra opcode byte, 4 displacement bytes. */
407 {0, 0, 5, 0},
fddf5b5b 408 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 409 1 extra opcode byte, 2 displacement bytes. */
410 {0, 0, 3, 0},
411
412 /* COND_JUMP86 states. */
413 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
415 /* dword conditionals adds 5 bytes to frag:
416 1 extra opcode byte, 4 displacement bytes. */
417 {0, 0, 5, 0},
418 /* word conditionals add 4 bytes to frag:
419 1 displacement byte and a 3 byte long branch insn. */
420 {0, 0, 4, 0}
252b5132
RH		 421};
422
9103f4f4
L		 423static const arch_entry cpu_arch[] =
424{
425 {"generic32", PROCESSOR_GENERIC32,
40fb9820 426 CPU_GENERIC32_FLAGS },
9103f4f4 427 {"generic64", PROCESSOR_GENERIC64,
40fb9820 428 CPU_GENERIC64_FLAGS },
9103f4f4 429 {"i8086", PROCESSOR_UNKNOWN,
40fb9820 430 CPU_NONE_FLAGS },
9103f4f4 431 {"i186", PROCESSOR_UNKNOWN,
40fb9820 432 CPU_I186_FLAGS },
9103f4f4 433 {"i286", PROCESSOR_UNKNOWN,
40fb9820 434 CPU_I286_FLAGS },
76bc74dc 435 {"i386", PROCESSOR_I386,
40fb9820 436 CPU_I386_FLAGS },
9103f4f4 437 {"i486", PROCESSOR_I486,
40fb9820 438 CPU_I486_FLAGS },
9103f4f4 439 {"i586", PROCESSOR_PENTIUM,
40fb9820 440 CPU_I586_FLAGS },
9103f4f4 441 {"i686", PROCESSOR_PENTIUMPRO,
40fb9820 442 CPU_I686_FLAGS },
9103f4f4 443 {"pentium", PROCESSOR_PENTIUM,
40fb9820 444 CPU_I586_FLAGS },
9103f4f4 445 {"pentiumpro",PROCESSOR_PENTIUMPRO,
40fb9820 446 CPU_I686_FLAGS },
9103f4f4 447 {"pentiumii", PROCESSOR_PENTIUMPRO,
40fb9820 448 CPU_P2_FLAGS },
9103f4f4 449 {"pentiumiii",PROCESSOR_PENTIUMPRO,
40fb9820 450 CPU_P3_FLAGS },
9103f4f4 451 {"pentium4", PROCESSOR_PENTIUM4,
40fb9820 452 CPU_P4_FLAGS },
9103f4f4 453 {"prescott", PROCESSOR_NOCONA,
40fb9820 454 CPU_CORE_FLAGS },
9103f4f4 455 {"nocona", PROCESSOR_NOCONA,
40fb9820 456 CPU_NOCONA_FLAGS },
ef05d495 457 {"yonah", PROCESSOR_CORE,
40fb9820 458 CPU_CORE_FLAGS },
ef05d495 459 {"core", PROCESSOR_CORE,
40fb9820 460 CPU_CORE_FLAGS },
ef05d495 461 {"merom", PROCESSOR_CORE2,
40fb9820 462 CPU_CORE2_FLAGS },
ef05d495 463 {"core2", PROCESSOR_CORE2,
40fb9820 464 CPU_CORE2_FLAGS },
9103f4f4 465 {"k6", PROCESSOR_K6,
40fb9820 466 CPU_K6_FLAGS },
9103f4f4 467 {"k6_2", PROCESSOR_K6,
40fb9820 468 CPU_K6_2_FLAGS },
9103f4f4 469 {"athlon", PROCESSOR_ATHLON,
40fb9820 470 CPU_ATHLON_FLAGS },
9103f4f4 471 {"sledgehammer", PROCESSOR_K8,
40fb9820 472 CPU_K8_FLAGS },
9103f4f4 473 {"opteron", PROCESSOR_K8,
40fb9820 474 CPU_K8_FLAGS },
9103f4f4 475 {"k8", PROCESSOR_K8,
40fb9820 476 CPU_K8_FLAGS },
050dfa73 477 {"amdfam10", PROCESSOR_AMDFAM10,
40fb9820 478 CPU_AMDFAM10_FLAGS },
9103f4f4 479 {".mmx", PROCESSOR_UNKNOWN,
40fb9820 480 CPU_MMX_FLAGS },
9103f4f4 481 {".sse", PROCESSOR_UNKNOWN,
40fb9820 482 CPU_SSE_FLAGS },
9103f4f4 483 {".sse2", PROCESSOR_UNKNOWN,
40fb9820 484 CPU_SSE2_FLAGS },
9103f4f4 485 {".sse3", PROCESSOR_UNKNOWN,
40fb9820 486 CPU_SSE3_FLAGS },
ef05d495 487 {".ssse3", PROCESSOR_UNKNOWN,
40fb9820 488 CPU_SSSE3_FLAGS },
42903f7f 489 {".sse4.1", PROCESSOR_UNKNOWN,
40fb9820 490 CPU_SSE4_1_FLAGS },
381d071f 491 {".sse4.2", PROCESSOR_UNKNOWN,
40fb9820 492 CPU_SSE4_2_FLAGS },
381d071f 493 {".sse4", PROCESSOR_UNKNOWN,
40fb9820 494 CPU_SSE4_2_FLAGS },
9103f4f4 495 {".3dnow", PROCESSOR_UNKNOWN,
40fb9820 496 CPU_3DNOW_FLAGS },
9103f4f4 497 {".3dnowa", PROCESSOR_UNKNOWN,
40fb9820 498 CPU_3DNOWA_FLAGS },
9103f4f4 499 {".padlock", PROCESSOR_UNKNOWN,
40fb9820 500 CPU_PADLOCK_FLAGS },
9103f4f4 501 {".pacifica", PROCESSOR_UNKNOWN,
40fb9820 502 CPU_SVME_FLAGS },
9103f4f4 503 {".svme", PROCESSOR_UNKNOWN,
40fb9820 504 CPU_SVME_FLAGS },
050dfa73 505 {".sse4a", PROCESSOR_UNKNOWN,
40fb9820 506 CPU_SSE4A_FLAGS },
050dfa73 507 {".abm", PROCESSOR_UNKNOWN,
40fb9820 508 CPU_ABM_FLAGS },
85f10a01
MM		 509 {".sse5", PROCESSOR_UNKNOWN,
510 CPU_SSE5_FLAGS },
e413e4e9
AM		 511};
512
29b0f896
AM		 513const pseudo_typeS md_pseudo_table[] =
514{
515#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
516 {"align", s_align_bytes, 0},
517#else
518 {"align", s_align_ptwo, 0},
519#endif
520 {"arch", set_cpu_arch, 0},
521#ifndef I386COFF
522 {"bss", s_bss, 0},
523#endif
524 {"ffloat", float_cons, 'f'},
525 {"dfloat", float_cons, 'd'},
526 {"tfloat", float_cons, 'x'},
527 {"value", cons, 2},
d182319b 528 {"slong", signed_cons, 4},
29b0f896
AM		 529 {"noopt", s_ignore, 0},
530 {"optim", s_ignore, 0},
531 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
532 {"code16", set_code_flag, CODE_16BIT},
533 {"code32", set_code_flag, CODE_32BIT},
534 {"code64", set_code_flag, CODE_64BIT},
535 {"intel_syntax", set_intel_syntax, 1},
536 {"att_syntax", set_intel_syntax, 0},
db51cc60
L		 537 {"allow_index_reg", set_allow_index_reg, 1},
538 {"disallow_index_reg", set_allow_index_reg, 0},
3b22753a
L		 539#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
540 {"largecomm", handle_large_common, 0},
07a53e5c 541#else
e3bb37b5 542 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 543 {"loc", dwarf2_directive_loc, 0},
544 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 545#endif
6482c264
NC		 546#ifdef TE_PE
547 {"secrel32", pe_directive_secrel, 0},
548#endif
29b0f896
AM		 549 {0, 0, 0}
550};
551
552/* For interface with expression (). */
553extern char *input_line_pointer;
554
555/* Hash table for instruction mnemonic lookup. */
556static struct hash_control *op_hash;
557
558/* Hash table for register lookup. */
559static struct hash_control *reg_hash;
560\f
252b5132 561void
e3bb37b5 562i386_align_code (fragS *fragP, int count)
252b5132 563{
ce8a8b2f
AM		 564 /* Various efficient no-op patterns for aligning code labels.
565 Note: Don't try to assemble the instructions in the comments.
566 0L and 0w are not legal. */
252b5132
RH		 567 static const char f32_1[] =
568 {0x90}; /* nop */
569 static const char f32_2[] =
ccc9c027 570 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 571 static const char f32_3[] =
572 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
573 static const char f32_4[] =
574 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
575 static const char f32_5[] =
576 {0x90, /* nop */
577 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
578 static const char f32_6[] =
579 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
580 static const char f32_7[] =
581 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
582 static const char f32_8[] =
583 {0x90, /* nop */
584 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
585 static const char f32_9[] =
586 {0x89,0xf6, /* movl %esi,%esi */
587 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
588 static const char f32_10[] =
589 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
590 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
591 static const char f32_11[] =
592 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
593 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
594 static const char f32_12[] =
595 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
596 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
597 static const char f32_13[] =
598 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
599 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
600 static const char f32_14[] =
601 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 603 static const char f16_3[] =
604 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 605 static const char f16_4[] =
606 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
607 static const char f16_5[] =
608 {0x90, /* nop */
609 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
610 static const char f16_6[] =
611 {0x89,0xf6, /* mov %si,%si */
612 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
613 static const char f16_7[] =
614 {0x8d,0x74,0x00, /* lea 0(%si),%si */
615 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
616 static const char f16_8[] =
617 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
618 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 619 static const char jump_31[] =
620 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
621 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
622 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
623 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 624 static const char *const f32_patt[] = {
625 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 626 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 627 };
628 static const char *const f16_patt[] = {
76bc74dc 629 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 630 };
ccc9c027
L		 631 /* nopl (%[re]ax) */
632 static const char alt_3[] =
633 {0x0f,0x1f,0x00};
634 /* nopl 0(%[re]ax) */
635 static const char alt_4[] =
636 {0x0f,0x1f,0x40,0x00};
637 /* nopl 0(%[re]ax,%[re]ax,1) */
638 static const char alt_5[] =
639 {0x0f,0x1f,0x44,0x00,0x00};
640 /* nopw 0(%[re]ax,%[re]ax,1) */
641 static const char alt_6[] =
642 {0x66,0x0f,0x1f,0x44,0x00,0x00};
643 /* nopl 0L(%[re]ax) */
644 static const char alt_7[] =
645 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
646 /* nopl 0L(%[re]ax,%[re]ax,1) */
647 static const char alt_8[] =
648 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
649 /* nopw 0L(%[re]ax,%[re]ax,1) */
650 static const char alt_9[] =
651 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
652 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
653 static const char alt_10[] =
654 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
655 /* data16
656 nopw %cs:0L(%[re]ax,%[re]ax,1) */
657 static const char alt_long_11[] =
658 {0x66,
659 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
660 /* data16
661 data16
662 nopw %cs:0L(%[re]ax,%[re]ax,1) */
663 static const char alt_long_12[] =
664 {0x66,
665 0x66,
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
667 /* data16
668 data16
669 data16
670 nopw %cs:0L(%[re]ax,%[re]ax,1) */
671 static const char alt_long_13[] =
672 {0x66,
673 0x66,
674 0x66,
675 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
676 /* data16
677 data16
678 data16
679 data16
680 nopw %cs:0L(%[re]ax,%[re]ax,1) */
681 static const char alt_long_14[] =
682 {0x66,
683 0x66,
684 0x66,
685 0x66,
686 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
687 /* data16
688 data16
689 data16
690 data16
691 data16
692 nopw %cs:0L(%[re]ax,%[re]ax,1) */
693 static const char alt_long_15[] =
694 {0x66,
695 0x66,
696 0x66,
697 0x66,
698 0x66,
699 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
700 /* nopl 0(%[re]ax,%[re]ax,1)
701 nopw 0(%[re]ax,%[re]ax,1) */
702 static const char alt_short_11[] =
703 {0x0f,0x1f,0x44,0x00,0x00,
704 0x66,0x0f,0x1f,0x44,0x00,0x00};
705 /* nopw 0(%[re]ax,%[re]ax,1)
706 nopw 0(%[re]ax,%[re]ax,1) */
707 static const char alt_short_12[] =
708 {0x66,0x0f,0x1f,0x44,0x00,0x00,
709 0x66,0x0f,0x1f,0x44,0x00,0x00};
710 /* nopw 0(%[re]ax,%[re]ax,1)
711 nopl 0L(%[re]ax) */
712 static const char alt_short_13[] =
713 {0x66,0x0f,0x1f,0x44,0x00,0x00,
714 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
715 /* nopl 0L(%[re]ax)
716 nopl 0L(%[re]ax) */
717 static const char alt_short_14[] =
718 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
719 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
720 /* nopl 0L(%[re]ax)
721 nopl 0L(%[re]ax,%[re]ax,1) */
722 static const char alt_short_15[] =
723 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
724 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
725 static const char *const alt_short_patt[] = {
726 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
727 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
728 alt_short_14, alt_short_15
729 };
730 static const char *const alt_long_patt[] = {
731 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
732 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
733 alt_long_14, alt_long_15
734 };
252b5132 735
76bc74dc
L		 736 /* Only align for at least a positive non-zero boundary. */
737 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 738 return;
3e73aa7c 739
ccc9c027
L		 740 /* We need to decide which NOP sequence to use for 32bit and
741 64bit. When -mtune= is used:
4eed87de 742
76bc74dc
L		 743 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
744 PROCESSOR_GENERIC32, f32_patt will be used.
745 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
746 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
747 alt_long_patt will be used.
748 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
749 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 750
76bc74dc
L		 751 When -mtune= isn't used, alt_long_patt will be used if
752 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
753 be used.
ccc9c027
L		 754
755 When -march= or .arch is used, we can't use anything beyond
756 cpu_arch_isa_flags. */
757
758 if (flag_code == CODE_16BIT)
759 {
ccc9c027 760 if (count > 8)
33fef721 761 {
76bc74dc
L		 762 memcpy (fragP->fr_literal + fragP->fr_fix,
763 jump_31, count);
764 /* Adjust jump offset. */
765 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 766 }
76bc74dc
L		 767 else
768 memcpy (fragP->fr_literal + fragP->fr_fix,
769 f16_patt[count - 1], count);
252b5132 770 }
33fef721 771 else
ccc9c027
L		 772 {
773 const char *const *patt = NULL;
774
775 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
776 {
777 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
778 switch (cpu_arch_tune)
779 {
780 case PROCESSOR_UNKNOWN:
781 /* We use cpu_arch_isa_flags to check if we SHOULD
782 optimize for Cpu686. */
40fb9820 783 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 784 patt = alt_long_patt;
ccc9c027
L		 785 else
786 patt = f32_patt;
787 break;
ccc9c027
L		 788 case PROCESSOR_PENTIUMPRO:
789 case PROCESSOR_PENTIUM4:
790 case PROCESSOR_NOCONA:
ef05d495 791 case PROCESSOR_CORE:
76bc74dc
L		 792 case PROCESSOR_CORE2:
793 case PROCESSOR_GENERIC64:
794 patt = alt_long_patt;
795 break;
ccc9c027
L		 796 case PROCESSOR_K6:
797 case PROCESSOR_ATHLON:
798 case PROCESSOR_K8:
4eed87de 799 case PROCESSOR_AMDFAM10:
ccc9c027
L		 800 patt = alt_short_patt;
801 break;
76bc74dc 802 case PROCESSOR_I386:
ccc9c027
L		 803 case PROCESSOR_I486:
804 case PROCESSOR_PENTIUM:
805 case PROCESSOR_GENERIC32:
806 patt = f32_patt;
807 break;
4eed87de 808 }
ccc9c027
L		 809 }
810 else
811 {
812 switch (cpu_arch_tune)
813 {
814 case PROCESSOR_UNKNOWN:
815 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
816 PROCESSOR_UNKNOWN. */
817 abort ();
818 break;
819
76bc74dc 820 case PROCESSOR_I386:
ccc9c027
L		 821 case PROCESSOR_I486:
822 case PROCESSOR_PENTIUM:
ccc9c027
L		 823 case PROCESSOR_K6:
824 case PROCESSOR_ATHLON:
825 case PROCESSOR_K8:
4eed87de 826 case PROCESSOR_AMDFAM10:
ccc9c027
L		 827 case PROCESSOR_GENERIC32:
828 /* We use cpu_arch_isa_flags to check if we CAN optimize
829 for Cpu686. */
40fb9820 830 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 831 patt = alt_short_patt;
832 else
833 patt = f32_patt;
834 break;
76bc74dc
L		 835 case PROCESSOR_PENTIUMPRO:
836 case PROCESSOR_PENTIUM4:
837 case PROCESSOR_NOCONA:
838 case PROCESSOR_CORE:
ef05d495 839 case PROCESSOR_CORE2:
40fb9820 840 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 841 patt = alt_long_patt;
842 else
843 patt = f32_patt;
844 break;
845 case PROCESSOR_GENERIC64:
76bc74dc 846 patt = alt_long_patt;
ccc9c027 847 break;
4eed87de 848 }
ccc9c027
L		 849 }
850
76bc74dc
L		 851 if (patt == f32_patt)
852 {
853 /* If the padding is less than 15 bytes, we use the normal
854 ones. Otherwise, we use a jump instruction and adjust
855 its offset. */
856 if (count < 15)
857 memcpy (fragP->fr_literal + fragP->fr_fix,
858 patt[count - 1], count);
859 else
860 {
861 memcpy (fragP->fr_literal + fragP->fr_fix,
862 jump_31, count);
863 /* Adjust jump offset. */
864 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
865 }
866 }
867 else
868 {
869 /* Maximum length of an instruction is 15 byte. If the
870 padding is greater than 15 bytes and we don't use jump,
871 we have to break it into smaller pieces. */
872 int padding = count;
873 while (padding > 15)
874 {
875 padding -= 15;
876 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
877 patt [14], 15);
878 }
879
880 if (padding)
881 memcpy (fragP->fr_literal + fragP->fr_fix,
882 patt [padding - 1], padding);
883 }
ccc9c027 884 }
33fef721 885 fragP->fr_var = count;
252b5132
RH		 886}
887
c6fb90c8
L		 888static INLINE int
889uints_all_zero (const unsigned int *x, unsigned int size)
40fb9820 890{
c6fb90c8
L		 891 switch (size)
892 {
893 case 3:
894 if (x[2])
895 return 0;
896 case 2:
897 if (x[1])
898 return 0;
899 case 1:
900 return !x[0];
901 default:
902 abort ();
903 }
40fb9820
L		 904}
905
c6fb90c8
L		 906static INLINE void
907uints_set (unsigned int *x, unsigned int v, unsigned int size)
40fb9820 908{
c6fb90c8
L		 909 switch (size)
910 {
911 case 3:
912 x[2] = v;
913 case 2:
914 x[1] = v;
915 case 1:
916 x[0] = v;
917 break;
918 default:
919 abort ();
920 }
921}
40fb9820 922
c6fb90c8
L		 923static INLINE int
924uints_equal (const unsigned int *x, const unsigned int *y,
925 unsigned int size)
926{
927 switch (size)
928 {
929 case 3:
930 if (x[2] != y [2])
931 return 0;
932 case 2:
933 if (x[1] != y [1])
934 return 0;
935 case 1:
936 return x[0] == y [0];
937 break;
938 default:
939 abort ();
940 }
941}
40fb9820 942
c6fb90c8
L		 943#define UINTS_ALL_ZERO(x) \
944 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
945#define UINTS_SET(x, v) \
946 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
947#define UINTS_CLEAR(x) \
948 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
949#define UINTS_EQUAL(x, y) \
950 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
951
952static INLINE int
953cpu_flags_check_cpu64 (i386_cpu_flags f)
954{
955 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
956 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 957}
958
c6fb90c8 959static INLINE i386_cpu_flags
40fb9820
L		 960cpu_flags_not (i386_cpu_flags x)
961{
c6fb90c8
L		 962 switch (ARRAY_SIZE (x.array))
963 {
964 case 3:
965 x.array [2] = ~x.array [2];
966 case 2:
967 x.array [1] = ~x.array [1];
968 case 1:
969 x.array [0] = ~x.array [0];
970 break;
971 default:
972 abort ();
973 }
40fb9820
L		 974
975#ifdef CpuUnused
976 x.bitfield.unused = 0;
977#endif
978
979 return x;
980}
981
c6fb90c8
L		 982static INLINE i386_cpu_flags
983cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 984{
c6fb90c8
L		 985 switch (ARRAY_SIZE (x.array))
986 {
987 case 3:
988 x.array [2] &= y.array [2];
989 case 2:
990 x.array [1] &= y.array [1];
991 case 1:
992 x.array [0] &= y.array [0];
993 break;
994 default:
995 abort ();
996 }
997 return x;
998}
40fb9820 999
c6fb90c8
L		 1000static INLINE i386_cpu_flags
1001cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1002{
c6fb90c8 1003 switch (ARRAY_SIZE (x.array))
40fb9820 1004 {
c6fb90c8
L		 1005 case 3:
1006 x.array [2] |= y.array [2];
1007 case 2:
1008 x.array [1] |= y.array [1];
1009 case 1:
1010 x.array [0] |= y.array [0];
40fb9820
L		 1011 break;
1012 default:
1013 abort ();
1014 }
40fb9820
L		 1015 return x;
1016}
1017
1018static int
1019cpu_flags_match (i386_cpu_flags x)
1020{
1021 i386_cpu_flags not = cpu_arch_flags_not;
1022
1023 not.bitfield.cpu64 = 1;
1024 not.bitfield.cpuno64 = 1;
1025
1026 x.bitfield.cpu64 = 0;
1027 x.bitfield.cpuno64 = 0;
1028
c6fb90c8
L		 1029 not = cpu_flags_and (x, not);
1030 return UINTS_ALL_ZERO (not);
40fb9820
L		 1031}
1032
c6fb90c8
L		 1033static INLINE i386_operand_type
1034operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1035{
c6fb90c8
L		 1036 switch (ARRAY_SIZE (x.array))
1037 {
1038 case 3:
1039 x.array [2] &= y.array [2];
1040 case 2:
1041 x.array [1] &= y.array [1];
1042 case 1:
1043 x.array [0] &= y.array [0];
1044 break;
1045 default:
1046 abort ();
1047 }
1048 return x;
40fb9820
L		 1049}
1050
c6fb90c8
L		 1051static INLINE i386_operand_type
1052operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1053{
c6fb90c8 1054 switch (ARRAY_SIZE (x.array))
40fb9820 1055 {
c6fb90c8
L		 1056 case 3:
1057 x.array [2] |= y.array [2];
1058 case 2:
1059 x.array [1] |= y.array [1];
1060 case 1:
1061 x.array [0] |= y.array [0];
40fb9820
L		 1062 break;
1063 default:
1064 abort ();
1065 }
c6fb90c8
L		 1066 return x;
1067}
40fb9820 1068
c6fb90c8
L		 1069static INLINE i386_operand_type
1070operand_type_xor (i386_operand_type x, i386_operand_type y)
1071{
1072 switch (ARRAY_SIZE (x.array))
1073 {
1074 case 3:
1075 x.array [2] ^= y.array [2];
1076 case 2:
1077 x.array [1] ^= y.array [1];
1078 case 1:
1079 x.array [0] ^= y.array [0];
1080 break;
1081 default:
1082 abort ();
1083 }
40fb9820
L		 1084 return x;
1085}
1086
1087static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1088static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1089static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1090static const i386_operand_type reg16_inoutportreg
1091 = OPERAND_TYPE_REG16_INOUTPORTREG;
1092static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1093static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1094static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1095static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1096static const i386_operand_type anydisp
1097 = OPERAND_TYPE_ANYDISP;
40fb9820
L		 1098static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1099static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1100static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1101static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1102static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1103static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1104static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1105static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1106static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1107static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1108
1109enum operand_type
1110{
1111 reg,
40fb9820
L		 1112 imm,
1113 disp,
1114 anymem
1115};
1116
c6fb90c8 1117static INLINE int
40fb9820
L		 1118operand_type_check (i386_operand_type t, enum operand_type c)
1119{
1120 switch (c)
1121 {
1122 case reg:
1123 return (t.bitfield.reg8
1124 || t.bitfield.reg16
1125 || t.bitfield.reg32
1126 || t.bitfield.reg64);
1127
40fb9820
L		 1128 case imm:
1129 return (t.bitfield.imm8
1130 || t.bitfield.imm8s
1131 || t.bitfield.imm16
1132 || t.bitfield.imm32
1133 || t.bitfield.imm32s
1134 || t.bitfield.imm64);
1135
1136 case disp:
1137 return (t.bitfield.disp8
1138 || t.bitfield.disp16
1139 || t.bitfield.disp32
1140 || t.bitfield.disp32s
1141 || t.bitfield.disp64);
1142
1143 case anymem:
1144 return (t.bitfield.disp8
1145 || t.bitfield.disp16
1146 || t.bitfield.disp32
1147 || t.bitfield.disp32s
1148 || t.bitfield.disp64
1149 || t.bitfield.baseindex);
1150
1151 default:
1152 abort ();
1153 }
1154}
1155
c6fb90c8 1156static INLINE int
40fb9820
L		 1157operand_type_match (i386_operand_type overlap,
1158 i386_operand_type given)
1159{
1160 i386_operand_type temp = overlap;
1161
1162 temp.bitfield.jumpabsolute = 0;
c6fb90c8 1163 if (UINTS_ALL_ZERO (temp))
40fb9820
L		 1164 return 0;
1165
1166 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1167 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1168}
1169
1170/* If given types r0 and r1 are registers they must be of the same type
1171 unless the expected operand type register overlap is null.
1172 Note that Acc in a template matches every size of reg. */
1173
c6fb90c8 1174static INLINE int
40fb9820
L		 1175operand_type_register_match (i386_operand_type m0,
1176 i386_operand_type g0,
1177 i386_operand_type t0,
1178 i386_operand_type m1,
1179 i386_operand_type g1,
1180 i386_operand_type t1)
1181{
1182 if (!operand_type_check (g0, reg))
1183 return 1;
1184
1185 if (!operand_type_check (g1, reg))
1186 return 1;
1187
1188 if (g0.bitfield.reg8 == g1.bitfield.reg8
1189 && g0.bitfield.reg16 == g1.bitfield.reg16
1190 && g0.bitfield.reg32 == g1.bitfield.reg32
1191 && g0.bitfield.reg64 == g1.bitfield.reg64)
1192 return 1;
1193
1194 if (m0.bitfield.acc)
1195 {
1196 t0.bitfield.reg8 = 1;
1197 t0.bitfield.reg16 = 1;
1198 t0.bitfield.reg32 = 1;
1199 t0.bitfield.reg64 = 1;
1200 }
1201
1202 if (m1.bitfield.acc)
1203 {
1204 t1.bitfield.reg8 = 1;
1205 t1.bitfield.reg16 = 1;
1206 t1.bitfield.reg32 = 1;
1207 t1.bitfield.reg64 = 1;
1208 }
1209
1210 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1211 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1212 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1213 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1214}
1215
252b5132 1216static INLINE unsigned int
40fb9820 1217mode_from_disp_size (i386_operand_type t)
252b5132 1218{
40fb9820
L		 1219 if (t.bitfield.disp8)
1220 return 1;
1221 else if (t.bitfield.disp16
1222 || t.bitfield.disp32
1223 || t.bitfield.disp32s)
1224 return 2;
1225 else
1226 return 0;
252b5132
RH		 1227}
1228
1229static INLINE int
e3bb37b5 1230fits_in_signed_byte (offsetT num)
252b5132
RH		 1231{
1232 return (num >= -128) && (num <= 127);
47926f60 1233}
252b5132
RH		 1234
1235static INLINE int
e3bb37b5 1236fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1237{
1238 return (num & 0xff) == num;
47926f60 1239}
252b5132
RH		 1240
1241static INLINE int
e3bb37b5 1242fits_in_unsigned_word (offsetT num)
252b5132
RH		 1243{
1244 return (num & 0xffff) == num;
47926f60 1245}
252b5132
RH		 1246
1247static INLINE int
e3bb37b5 1248fits_in_signed_word (offsetT num)
252b5132
RH		 1249{
1250 return (-32768 <= num) && (num <= 32767);
47926f60 1251}
2a962e6d 1252
3e73aa7c 1253static INLINE int
e3bb37b5 1254fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1255{
1256#ifndef BFD64
1257 return 1;
1258#else
1259 return (!(((offsetT) -1 << 31) & num)
1260 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1261#endif
1262} /* fits_in_signed_long() */
2a962e6d 1263
3e73aa7c 1264static INLINE int
e3bb37b5 1265fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1266{
1267#ifndef BFD64
1268 return 1;
1269#else
1270 return (num & (((offsetT) 2 << 31) - 1)) == num;
1271#endif
1272} /* fits_in_unsigned_long() */
252b5132 1273
40fb9820 1274static i386_operand_type
e3bb37b5 1275smallest_imm_type (offsetT num)
252b5132 1276{
40fb9820
L		 1277 i386_operand_type t;
1278
c6fb90c8 1279 UINTS_CLEAR (t);
40fb9820
L		 1280 t.bitfield.imm64 = 1;
1281
1282 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1283 {
1284 /* This code is disabled on the 486 because all the Imm1 forms
1285 in the opcode table are slower on the i486. They're the
1286 versions with the implicitly specified single-position
1287 displacement, which has another syntax if you really want to
1288 use that form. */
40fb9820
L		 1289 t.bitfield.imm1 = 1;
1290 t.bitfield.imm8 = 1;
1291 t.bitfield.imm8s = 1;
1292 t.bitfield.imm16 = 1;
1293 t.bitfield.imm32 = 1;
1294 t.bitfield.imm32s = 1;
1295 }
1296 else if (fits_in_signed_byte (num))
1297 {
1298 t.bitfield.imm8 = 1;
1299 t.bitfield.imm8s = 1;
1300 t.bitfield.imm16 = 1;
1301 t.bitfield.imm32 = 1;
1302 t.bitfield.imm32s = 1;
1303 }
1304 else if (fits_in_unsigned_byte (num))
1305 {
1306 t.bitfield.imm8 = 1;
1307 t.bitfield.imm16 = 1;
1308 t.bitfield.imm32 = 1;
1309 t.bitfield.imm32s = 1;
1310 }
1311 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1312 {
1313 t.bitfield.imm16 = 1;
1314 t.bitfield.imm32 = 1;
1315 t.bitfield.imm32s = 1;
1316 }
1317 else if (fits_in_signed_long (num))
1318 {
1319 t.bitfield.imm32 = 1;
1320 t.bitfield.imm32s = 1;
1321 }
1322 else if (fits_in_unsigned_long (num))
1323 t.bitfield.imm32 = 1;
1324
1325 return t;
47926f60 1326}
252b5132 1327
847f7ad4 1328static offsetT
e3bb37b5 1329offset_in_range (offsetT val, int size)
847f7ad4 1330{
508866be 1331 addressT mask;
ba2adb93 1332
847f7ad4
AM		 1333 switch (size)
1334 {
508866be
L		 1335 case 1: mask = ((addressT) 1 << 8) - 1; break;
1336 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1337 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1338#ifdef BFD64
1339 case 8: mask = ((addressT) 2 << 63) - 1; break;
1340#endif
47926f60 1341 default: abort ();
847f7ad4
AM		 1342 }
1343
ba2adb93 1344 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1345 if (!use_rela_relocations)
1346 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1347 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1348
47926f60 1349 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1350 {
1351 char buf1[40], buf2[40];
1352
1353 sprint_value (buf1, val);
1354 sprint_value (buf2, val & mask);
1355 as_warn (_("%s shortened to %s"), buf1, buf2);
1356 }
1357 return val & mask;
1358}
1359
252b5132
RH		 1360/* Returns 0 if attempting to add a prefix where one from the same
1361 class already exists, 1 if non rep/repne added, 2 if rep/repne
1362 added. */
1363static int
e3bb37b5 1364add_prefix (unsigned int prefix)
252b5132
RH		 1365{
1366 int ret = 1;
b1905489 1367 unsigned int q;
252b5132 1368
29b0f896
AM		 1369 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1370 && flag_code == CODE_64BIT)
b1905489 1371 {
161a04f6
L		 1372 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1373 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1374 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1375 ret = 0;
1376 q = REX_PREFIX;
1377 }
3e73aa7c 1378 else
b1905489
JB		 1379 {
1380 switch (prefix)
1381 {
1382 default:
1383 abort ();
1384
1385 case CS_PREFIX_OPCODE:
1386 case DS_PREFIX_OPCODE:
1387 case ES_PREFIX_OPCODE:
1388 case FS_PREFIX_OPCODE:
1389 case GS_PREFIX_OPCODE:
1390 case SS_PREFIX_OPCODE:
1391 q = SEG_PREFIX;
1392 break;
1393
1394 case REPNE_PREFIX_OPCODE:
1395 case REPE_PREFIX_OPCODE:
1396 ret = 2;
1397 /* fall thru */
1398 case LOCK_PREFIX_OPCODE:
1399 q = LOCKREP_PREFIX;
1400 break;
1401
1402 case FWAIT_OPCODE:
1403 q = WAIT_PREFIX;
1404 break;
1405
1406 case ADDR_PREFIX_OPCODE:
1407 q = ADDR_PREFIX;
1408 break;
1409
1410 case DATA_PREFIX_OPCODE:
1411 q = DATA_PREFIX;
1412 break;
1413 }
1414 if (i.prefix[q] != 0)
1415 ret = 0;
1416 }
252b5132 1417
b1905489 1418 if (ret)
252b5132 1419 {
b1905489
JB		 1420 if (!i.prefix[q])
1421 ++i.prefixes;
1422 i.prefix[q] |= prefix;
252b5132 1423 }
b1905489
JB		 1424 else
1425 as_bad (_("same type of prefix used twice"));
252b5132 1426
252b5132
RH		 1427 return ret;
1428}
1429
1430static void
e3bb37b5 1431set_code_flag (int value)
eecb386c 1432{
3e73aa7c 1433 flag_code = value;
40fb9820
L		 1434 if (flag_code == CODE_64BIT)
1435 {
1436 cpu_arch_flags.bitfield.cpu64 = 1;
1437 cpu_arch_flags.bitfield.cpuno64 = 0;
1438 cpu_arch_flags_not.bitfield.cpu64 = 0;
1439 cpu_arch_flags_not.bitfield.cpuno64 = 1;
1440 }
1441 else
1442 {
1443 cpu_arch_flags.bitfield.cpu64 = 0;
1444 cpu_arch_flags.bitfield.cpuno64 = 1;
1445 cpu_arch_flags_not.bitfield.cpu64 = 1;
1446 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1447 }
1448 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1449 {
1450 as_bad (_("64bit mode not supported on this CPU."));
1451 }
40fb9820 1452 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1453 {
1454 as_bad (_("32bit mode not supported on this CPU."));
1455 }
eecb386c
AM		 1456 stackop_size = '\0';
1457}
1458
1459static void
e3bb37b5 1460set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1461{
3e73aa7c 1462 flag_code = new_code_flag;
40fb9820
L		 1463 if (flag_code != CODE_16BIT)
1464 abort ();
1465 cpu_arch_flags.bitfield.cpu64 = 0;
1466 cpu_arch_flags.bitfield.cpuno64 = 1;
1467 cpu_arch_flags_not.bitfield.cpu64 = 1;
1468 cpu_arch_flags_not.bitfield.cpuno64 = 0;
9306ca4a 1469 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1470}
1471
1472static void
e3bb37b5 1473set_intel_syntax (int syntax_flag)
252b5132
RH		 1474{
1475 /* Find out if register prefixing is specified. */
1476 int ask_naked_reg = 0;
1477
1478 SKIP_WHITESPACE ();
29b0f896 1479 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1480 {
1481 char *string = input_line_pointer;
1482 int e = get_symbol_end ();
1483
47926f60 1484 if (strcmp (string, "prefix") == 0)
252b5132 1485 ask_naked_reg = 1;
47926f60 1486 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1487 ask_naked_reg = -1;
1488 else
d0b47220 1489 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1490 *input_line_pointer = e;
1491 }
1492 demand_empty_rest_of_line ();
c3332e24 1493
252b5132
RH		 1494 intel_syntax = syntax_flag;
1495
1496 if (ask_naked_reg == 0)
f86103b7
AM		 1497 allow_naked_reg = (intel_syntax
1498 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1499 else
1500 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1501
e4a3b5a4 1502 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1503 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1504 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1505}
1506
db51cc60
L		 1507static void
1508set_allow_index_reg (int flag)
1509{
1510 allow_index_reg = flag;
1511}
1512
e413e4e9 1513static void
e3bb37b5 1514set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1515{
47926f60 1516 SKIP_WHITESPACE ();
e413e4e9 1517
29b0f896 1518 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1519 {
1520 char *string = input_line_pointer;
1521 int e = get_symbol_end ();
9103f4f4 1522 unsigned int i;
40fb9820 1523 i386_cpu_flags flags;
e413e4e9 1524
9103f4f4 1525 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1526 {
1527 if (strcmp (string, cpu_arch[i].name) == 0)
1528 {
5c6af06e
JB		 1529 if (*string != '.')
1530 {
1531 cpu_arch_name = cpu_arch[i].name;
1532 cpu_sub_arch_name = NULL;
40fb9820
L		 1533 cpu_arch_flags = cpu_arch[i].flags;
1534 if (flag_code == CODE_64BIT)
1535 {
1536 cpu_arch_flags.bitfield.cpu64 = 1;
1537 cpu_arch_flags.bitfield.cpuno64 = 0;
1538 }
1539 else
1540 {
1541 cpu_arch_flags.bitfield.cpu64 = 0;
1542 cpu_arch_flags.bitfield.cpuno64 = 1;
1543 }
1544 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
ccc9c027 1545 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1546 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1547 if (!cpu_arch_tune_set)
1548 {
1549 cpu_arch_tune = cpu_arch_isa;
1550 cpu_arch_tune_flags = cpu_arch_isa_flags;
1551 }
5c6af06e
JB		 1552 break;
1553 }
40fb9820 1554
c6fb90c8
L		 1555 flags = cpu_flags_or (cpu_arch_flags,
1556 cpu_arch[i].flags);
1557 if (!UINTS_EQUAL (flags, cpu_arch_flags))
5c6af06e
JB		 1558 {
1559 cpu_sub_arch_name = cpu_arch[i].name;
40fb9820
L		 1560 cpu_arch_flags = flags;
1561 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
5c6af06e
JB		 1562 }
1563 *input_line_pointer = e;
1564 demand_empty_rest_of_line ();
1565 return;
e413e4e9
AM		 1566 }
1567 }
9103f4f4 1568 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1569 as_bad (_("no such architecture: `%s'"), string);
1570
1571 *input_line_pointer = e;
1572 }
1573 else
1574 as_bad (_("missing cpu architecture"));
1575
fddf5b5b
AM		 1576 no_cond_jump_promotion = 0;
1577 if (*input_line_pointer == ','
29b0f896 1578 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1579 {
1580 char *string = ++input_line_pointer;
1581 int e = get_symbol_end ();
1582
1583 if (strcmp (string, "nojumps") == 0)
1584 no_cond_jump_promotion = 1;
1585 else if (strcmp (string, "jumps") == 0)
1586 ;
1587 else
1588 as_bad (_("no such architecture modifier: `%s'"), string);
1589
1590 *input_line_pointer = e;
1591 }
1592
e413e4e9
AM		 1593 demand_empty_rest_of_line ();
1594}
1595
b9d79e03
JH		 1596unsigned long
1597i386_mach ()
1598{
1599 if (!strcmp (default_arch, "x86_64"))
1600 return bfd_mach_x86_64;
1601 else if (!strcmp (default_arch, "i386"))
1602 return bfd_mach_i386_i386;
1603 else
1604 as_fatal (_("Unknown architecture"));
1605}
b9d79e03 1606\f
252b5132
RH		 1607void
1608md_begin ()
1609{
1610 const char *hash_err;
1611
40fb9820
L		 1612 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1613
47926f60 1614 /* Initialize op_hash hash table. */
252b5132
RH		 1615 op_hash = hash_new ();
1616
1617 {
29b0f896
AM		 1618 const template *optab;
1619 templates *core_optab;
252b5132 1620
47926f60
KH		 1621 /* Setup for loop. */
1622 optab = i386_optab;
252b5132
RH		 1623 core_optab = (templates *) xmalloc (sizeof (templates));
1624 core_optab->start = optab;
1625
1626 while (1)
1627 {
1628 ++optab;
1629 if (optab->name == NULL
1630 || strcmp (optab->name, (optab - 1)->name) != 0)
1631 {
1632 /* different name --> ship out current template list;
47926f60 1633 add to hash table; & begin anew. */
252b5132
RH		 1634 core_optab->end = optab;
1635 hash_err = hash_insert (op_hash,
1636 (optab - 1)->name,
1637 (PTR) core_optab);
1638 if (hash_err)
1639 {
252b5132
RH		 1640 as_fatal (_("Internal Error: Can't hash %s: %s"),
1641 (optab - 1)->name,
1642 hash_err);
1643 }
1644 if (optab->name == NULL)
1645 break;
1646 core_optab = (templates *) xmalloc (sizeof (templates));
1647 core_optab->start = optab;
1648 }
1649 }
1650 }
1651
47926f60 1652 /* Initialize reg_hash hash table. */
252b5132
RH		 1653 reg_hash = hash_new ();
1654 {
29b0f896 1655 const reg_entry *regtab;
c3fe08fa 1656 unsigned int regtab_size = i386_regtab_size;
252b5132 1657
c3fe08fa 1658 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1659 {
1660 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1661 if (hash_err)
3e73aa7c
JH		 1662 as_fatal (_("Internal Error: Can't hash %s: %s"),
1663 regtab->reg_name,
1664 hash_err);
252b5132
RH		 1665 }
1666 }
1667
47926f60 1668 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1669 {
29b0f896
AM		 1670 int c;
1671 char *p;
252b5132
RH		 1672
1673 for (c = 0; c < 256; c++)
1674 {
3882b010 1675 if (ISDIGIT (c))
252b5132
RH		 1676 {
1677 digit_chars[c] = c;
1678 mnemonic_chars[c] = c;
1679 register_chars[c] = c;
1680 operand_chars[c] = c;
1681 }
3882b010 1682 else if (ISLOWER (c))
252b5132
RH		 1683 {
1684 mnemonic_chars[c] = c;
1685 register_chars[c] = c;
1686 operand_chars[c] = c;
1687 }
3882b010 1688 else if (ISUPPER (c))
252b5132 1689 {
3882b010 1690 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1691 register_chars[c] = mnemonic_chars[c];
1692 operand_chars[c] = c;
1693 }
1694
3882b010 1695 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1696 identifier_chars[c] = c;
1697 else if (c >= 128)
1698 {
1699 identifier_chars[c] = c;
1700 operand_chars[c] = c;
1701 }
1702 }
1703
1704#ifdef LEX_AT
1705 identifier_chars['@'] = '@';
32137342
NC		 1706#endif
1707#ifdef LEX_QM
1708 identifier_chars['?'] = '?';
1709 operand_chars['?'] = '?';
252b5132 1710#endif
252b5132 1711 digit_chars['-'] = '-';
791fe849 1712 mnemonic_chars['-'] = '-';
0003779b 1713 mnemonic_chars['.'] = '.';
252b5132
RH		 1714 identifier_chars['_'] = '_';
1715 identifier_chars['.'] = '.';
1716
1717 for (p = operand_special_chars; *p != '\0'; p++)
1718 operand_chars[(unsigned char) *p] = *p;
1719 }
1720
1721#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1722 if (IS_ELF)
252b5132
RH		 1723 {
1724 record_alignment (text_section, 2);
1725 record_alignment (data_section, 2);
1726 record_alignment (bss_section, 2);
1727 }
1728#endif
a4447b93
RH		 1729
1730 if (flag_code == CODE_64BIT)
1731 {
1732 x86_dwarf2_return_column = 16;
1733 x86_cie_data_alignment = -8;
1734 }
1735 else
1736 {
1737 x86_dwarf2_return_column = 8;
1738 x86_cie_data_alignment = -4;
1739 }
252b5132
RH		 1740}
1741
1742void
e3bb37b5 1743i386_print_statistics (FILE *file)
252b5132
RH		 1744{
1745 hash_print_statistics (file, "i386 opcode", op_hash);
1746 hash_print_statistics (file, "i386 register", reg_hash);
1747}
1748\f
252b5132
RH		 1749#ifdef DEBUG386
1750
ce8a8b2f 1751/* Debugging routines for md_assemble. */
e3bb37b5 1752static void pte (template *);
40fb9820 1753static void pt (i386_operand_type);
e3bb37b5
L		 1754static void pe (expressionS *);
1755static void ps (symbolS *);
252b5132
RH		 1756
1757static void
e3bb37b5 1758pi (char *line, i386_insn *x)
252b5132 1759{
09f131f2 1760 unsigned int i;
252b5132
RH		 1761
1762 fprintf (stdout, "%s: template ", line);
1763 pte (&x->tm);
09f131f2
JH		 1764 fprintf (stdout, " address: base %s index %s scale %x\n",
1765 x->base_reg ? x->base_reg->reg_name : "none",
1766 x->index_reg ? x->index_reg->reg_name : "none",
1767 x->log2_scale_factor);
1768 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1769 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1770 fprintf (stdout, " sib: base %x index %x scale %x\n",
1771 x->sib.base, x->sib.index, x->sib.scale);
1772 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1773 (x->rex & REX_W) != 0,
1774 (x->rex & REX_R) != 0,
1775 (x->rex & REX_X) != 0,
1776 (x->rex & REX_B) != 0);
85f10a01
MM		 1777 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1778 x->drex.reg, x->drex.rex);
252b5132
RH		 1779 for (i = 0; i < x->operands; i++)
1780 {
1781 fprintf (stdout, " #%d: ", i + 1);
1782 pt (x->types[i]);
1783 fprintf (stdout, "\n");
40fb9820
L		 1784 if (x->types[i].bitfield.reg8
1785 || x->types[i].bitfield.reg16
1786 || x->types[i].bitfield.reg32
1787 || x->types[i].bitfield.reg64
1788 || x->types[i].bitfield.regmmx
1789 || x->types[i].bitfield.regxmm
1790 || x->types[i].bitfield.sreg2
1791 || x->types[i].bitfield.sreg3
1792 || x->types[i].bitfield.control
1793 || x->types[i].bitfield.debug
1794 || x->types[i].bitfield.test)
520dc8e8 1795 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 1796 if (operand_type_check (x->types[i], imm))
520dc8e8 1797 pe (x->op[i].imms);
40fb9820 1798 if (operand_type_check (x->types[i], disp))
520dc8e8 1799 pe (x->op[i].disps);
252b5132
RH		 1800 }
1801}
1802
1803static void
e3bb37b5 1804pte (template *t)
252b5132 1805{
09f131f2 1806 unsigned int i;
252b5132 1807 fprintf (stdout, " %d operands ", t->operands);
47926f60 1808 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1809 if (t->extension_opcode != None)
1810 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 1811 if (t->opcode_modifier.d)
252b5132 1812 fprintf (stdout, "D");
40fb9820 1813 if (t->opcode_modifier.w)
252b5132
RH		 1814 fprintf (stdout, "W");
1815 fprintf (stdout, "\n");
1816 for (i = 0; i < t->operands; i++)
1817 {
1818 fprintf (stdout, " #%d type ", i + 1);
1819 pt (t->operand_types[i]);
1820 fprintf (stdout, "\n");
1821 }
1822}
1823
1824static void
e3bb37b5 1825pe (expressionS *e)
252b5132 1826{
24eab124 1827 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1828 fprintf (stdout, " add_number %ld (%lx)\n",
1829 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1830 if (e->X_add_symbol)
1831 {
1832 fprintf (stdout, " add_symbol ");
1833 ps (e->X_add_symbol);
1834 fprintf (stdout, "\n");
1835 }
1836 if (e->X_op_symbol)
1837 {
1838 fprintf (stdout, " op_symbol ");
1839 ps (e->X_op_symbol);
1840 fprintf (stdout, "\n");
1841 }
1842}
1843
1844static void
e3bb37b5 1845ps (symbolS *s)
252b5132
RH		 1846{
1847 fprintf (stdout, "%s type %s%s",
1848 S_GET_NAME (s),
1849 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1850 segment_name (S_GET_SEGMENT (s)));
1851}
1852
7b81dfbb 1853static struct type_name
252b5132 1854 {
40fb9820
L		 1855 i386_operand_type mask;
1856 const char *name;
252b5132 1857 }
7b81dfbb 1858const type_names[] =
252b5132 1859{
40fb9820
L		 1860 { OPERAND_TYPE_REG8, "r8" },
1861 { OPERAND_TYPE_REG16, "r16" },
1862 { OPERAND_TYPE_REG32, "r32" },
1863 { OPERAND_TYPE_REG64, "r64" },
1864 { OPERAND_TYPE_IMM8, "i8" },
1865 { OPERAND_TYPE_IMM8, "i8s" },
1866 { OPERAND_TYPE_IMM16, "i16" },
1867 { OPERAND_TYPE_IMM32, "i32" },
1868 { OPERAND_TYPE_IMM32S, "i32s" },
1869 { OPERAND_TYPE_IMM64, "i64" },
1870 { OPERAND_TYPE_IMM1, "i1" },
1871 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1872 { OPERAND_TYPE_DISP8, "d8" },
1873 { OPERAND_TYPE_DISP16, "d16" },
1874 { OPERAND_TYPE_DISP32, "d32" },
1875 { OPERAND_TYPE_DISP32S, "d32s" },
1876 { OPERAND_TYPE_DISP64, "d64" },
1877 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1878 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1879 { OPERAND_TYPE_CONTROL, "control reg" },
1880 { OPERAND_TYPE_TEST, "test reg" },
1881 { OPERAND_TYPE_DEBUG, "debug reg" },
1882 { OPERAND_TYPE_FLOATREG, "FReg" },
1883 { OPERAND_TYPE_FLOATACC, "FAcc" },
1884 { OPERAND_TYPE_SREG2, "SReg2" },
1885 { OPERAND_TYPE_SREG3, "SReg3" },
1886 { OPERAND_TYPE_ACC, "Acc" },
1887 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1888 { OPERAND_TYPE_REGMMX, "rMMX" },
1889 { OPERAND_TYPE_REGXMM, "rXMM" },
1890 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 1891};
1892
1893static void
40fb9820 1894pt (i386_operand_type t)
252b5132 1895{
40fb9820 1896 unsigned int j;
c6fb90c8 1897 i386_operand_type a;
252b5132 1898
40fb9820 1899 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 1900 {
1901 a = operand_type_and (t, type_names[j].mask);
1902 if (!UINTS_ALL_ZERO (a))
1903 fprintf (stdout, "%s, ", type_names[j].name);
1904 }
252b5132
RH		 1905 fflush (stdout);
1906}
1907
1908#endif /* DEBUG386 */
1909\f
252b5132 1910static bfd_reloc_code_real_type
3956db08 1911reloc (unsigned int size,
64e74474
AM		 1912 int pcrel,
1913 int sign,
1914 bfd_reloc_code_real_type other)
252b5132 1915{
47926f60 1916 if (other != NO_RELOC)
3956db08
JB		 1917 {
1918 reloc_howto_type *reloc;
1919
1920 if (size == 8)
1921 switch (other)
1922 {
64e74474
AM		 1923 case BFD_RELOC_X86_64_GOT32:
1924 return BFD_RELOC_X86_64_GOT64;
1925 break;
1926 case BFD_RELOC_X86_64_PLTOFF64:
1927 return BFD_RELOC_X86_64_PLTOFF64;
1928 break;
1929 case BFD_RELOC_X86_64_GOTPC32:
1930 other = BFD_RELOC_X86_64_GOTPC64;
1931 break;
1932 case BFD_RELOC_X86_64_GOTPCREL:
1933 other = BFD_RELOC_X86_64_GOTPCREL64;
1934 break;
1935 case BFD_RELOC_X86_64_TPOFF32:
1936 other = BFD_RELOC_X86_64_TPOFF64;
1937 break;
1938 case BFD_RELOC_X86_64_DTPOFF32:
1939 other = BFD_RELOC_X86_64_DTPOFF64;
1940 break;
1941 default:
1942 break;
3956db08 1943 }
e05278af
JB		 1944
1945 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1946 if (size == 4 && flag_code != CODE_64BIT)
1947 sign = -1;
1948
3956db08
JB		 1949 reloc = bfd_reloc_type_lookup (stdoutput, other);
1950 if (!reloc)
1951 as_bad (_("unknown relocation (%u)"), other);
1952 else if (size != bfd_get_reloc_size (reloc))
1953 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1954 bfd_get_reloc_size (reloc),
1955 size);
1956 else if (pcrel && !reloc->pc_relative)
1957 as_bad (_("non-pc-relative relocation for pc-relative field"));
1958 else if ((reloc->complain_on_overflow == complain_overflow_signed
1959 && !sign)
1960 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1961 && sign > 0))
3956db08
JB		 1962 as_bad (_("relocated field and relocation type differ in signedness"));
1963 else
1964 return other;
1965 return NO_RELOC;
1966 }
252b5132
RH		 1967
1968 if (pcrel)
1969 {
3e73aa7c 1970 if (!sign)
3956db08 1971 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1972 switch (size)
1973 {
1974 case 1: return BFD_RELOC_8_PCREL;
1975 case 2: return BFD_RELOC_16_PCREL;
1976 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1977 case 8: return BFD_RELOC_64_PCREL;
252b5132 1978 }
3956db08 1979 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1980 }
1981 else
1982 {
3956db08 1983 if (sign > 0)
e5cb08ac 1984 switch (size)
3e73aa7c
JH		 1985 {
1986 case 4: return BFD_RELOC_X86_64_32S;
1987 }
1988 else
1989 switch (size)
1990 {
1991 case 1: return BFD_RELOC_8;
1992 case 2: return BFD_RELOC_16;
1993 case 4: return BFD_RELOC_32;
1994 case 8: return BFD_RELOC_64;
1995 }
3956db08
JB		 1996 as_bad (_("cannot do %s %u byte relocation"),
1997 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1998 }
1999
bfb32b52 2000 abort ();
252b5132
RH		 2001 return BFD_RELOC_NONE;
2002}
2003
47926f60
KH		 2004/* Here we decide which fixups can be adjusted to make them relative to
2005 the beginning of the section instead of the symbol. Basically we need
2006 to make sure that the dynamic relocations are done correctly, so in
2007 some cases we force the original symbol to be used. */
2008
252b5132 2009int
e3bb37b5 2010tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2011{
6d249963 2012#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2013 if (!IS_ELF)
31312f95
AM		 2014 return 1;
2015
a161fe53
AM		 2016 /* Don't adjust pc-relative references to merge sections in 64-bit
2017 mode. */
2018 if (use_rela_relocations
2019 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2020 && fixP->fx_pcrel)
252b5132 2021 return 0;
31312f95 2022
8d01d9a9
AJ		 2023 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2024 and changed later by validate_fix. */
2025 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2026 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2027 return 0;
2028
ce8a8b2f 2029 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2030 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2031 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2032 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2033 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2034 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2035 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2036 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2037 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2038 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2039 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2040 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2041 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2042 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2043 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2044 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2045 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2046 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2047 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2048 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2049 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2050 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2051 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2052 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2053 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2054 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2055 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2056 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2057 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2058 return 0;
31312f95 2059#endif
252b5132
RH		 2060 return 1;
2061}
252b5132 2062
b4cac588 2063static int
e3bb37b5 2064intel_float_operand (const char *mnemonic)
252b5132 2065{
9306ca4a
JB		 2066 /* Note that the value returned is meaningful only for opcodes with (memory)
2067 operands, hence the code here is free to improperly handle opcodes that
2068 have no operands (for better performance and smaller code). */
2069
2070 if (mnemonic[0] != 'f')
2071 return 0; /* non-math */
2072
2073 switch (mnemonic[1])
2074 {
2075 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2076 the fs segment override prefix not currently handled because no
2077 call path can make opcodes without operands get here */
2078 case 'i':
2079 return 2 /* integer op */;
2080 case 'l':
2081 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2082 return 3; /* fldcw/fldenv */
2083 break;
2084 case 'n':
2085 if (mnemonic[2] != 'o' /* fnop */)
2086 return 3; /* non-waiting control op */
2087 break;
2088 case 'r':
2089 if (mnemonic[2] == 's')
2090 return 3; /* frstor/frstpm */
2091 break;
2092 case 's':
2093 if (mnemonic[2] == 'a')
2094 return 3; /* fsave */
2095 if (mnemonic[2] == 't')
2096 {
2097 switch (mnemonic[3])
2098 {
2099 case 'c': /* fstcw */
2100 case 'd': /* fstdw */
2101 case 'e': /* fstenv */
2102 case 's': /* fsts[gw] */
2103 return 3;
2104 }
2105 }
2106 break;
2107 case 'x':
2108 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2109 return 0; /* fxsave/fxrstor are not really math ops */
2110 break;
2111 }
252b5132 2112
9306ca4a 2113 return 1;
252b5132
RH		 2114}
2115
2116/* This is the guts of the machine-dependent assembler. LINE points to a
2117 machine dependent instruction. This function is supposed to emit
2118 the frags/bytes it assembles to. */
2119
2120void
2121md_assemble (line)
2122 char *line;
2123{
40fb9820 2124 unsigned int j;
252b5132
RH		 2125 char mnemonic[MAX_MNEM_SIZE];
2126
47926f60 2127 /* Initialize globals. */
252b5132
RH		 2128 memset (&i, '\0', sizeof (i));
2129 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2130 i.reloc[j] = NO_RELOC;
252b5132
RH		 2131 memset (disp_expressions, '\0', sizeof (disp_expressions));
2132 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2133 save_stack_p = save_stack;
252b5132
RH		 2134
2135 /* First parse an instruction mnemonic & call i386_operand for the operands.
2136 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2137 start of a (possibly prefixed) mnemonic. */
252b5132 2138
29b0f896
AM		 2139 line = parse_insn (line, mnemonic);
2140 if (line == NULL)
2141 return;
252b5132 2142
29b0f896
AM		 2143 line = parse_operands (line, mnemonic);
2144 if (line == NULL)
2145 return;
252b5132 2146
29b0f896
AM		 2147 /* Now we've parsed the mnemonic into a set of templates, and have the
2148 operands at hand. */
2149
2150 /* All intel opcodes have reversed operands except for "bound" and
2151 "enter". We also don't reverse intersegment "jmp" and "call"
2152 instructions with 2 immediate operands so that the immediate segment
050dfa73 2153 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2154 if (intel_syntax
2155 && i.operands > 1
29b0f896 2156 && (strcmp (mnemonic, "bound") != 0)
30123838 2157 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2158 && !(operand_type_check (i.types[0], imm)
2159 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2160 swap_operands ();
2161
ec56d5c0
JB		 2162 /* The order of the immediates should be reversed
2163 for 2 immediates extrq and insertq instructions */
2164 if (i.imm_operands == 2
2165 && (strcmp (mnemonic, "extrq") == 0
2166 || strcmp (mnemonic, "insertq") == 0))
2167 swap_2_operands (0, 1);
2168
29b0f896
AM		 2169 if (i.imm_operands)
2170 optimize_imm ();
2171
b300c311
L		 2172 /* Don't optimize displacement for movabs since it only takes 64bit
2173 displacement. */
2174 if (i.disp_operands
2175 && (flag_code != CODE_64BIT
2176 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2177 optimize_disp ();
2178
2179 /* Next, we find a template that matches the given insn,
2180 making sure the overlap of the given operands types is consistent
2181 with the template operand types. */
252b5132 2182
29b0f896
AM		 2183 if (!match_template ())
2184 return;
252b5132 2185
cd61ebfe
AM		 2186 if (intel_syntax)
2187 {
2188 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2189 if (SYSV386_COMPAT
2190 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 2191 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 2192
2193 /* Zap movzx and movsx suffix. The suffix may have been set from
2194 "word ptr" or "byte ptr" on the source operand, but we'll use
2195 the suffix later to choose the destination register. */
2196 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 2197 {
2198 if (i.reg_operands < 2
2199 && !i.suffix
40fb9820
L		 2200 && (!i.tm.opcode_modifier.no_bsuf
2201 || !i.tm.opcode_modifier.no_wsuf
2202 || !i.tm.opcode_modifier.no_lsuf
2203 || !i.tm.opcode_modifier.no_ssuf
2204 || !i.tm.opcode_modifier.no_xsuf
2205 || !i.tm.opcode_modifier.no_qsuf))
9306ca4a
JB		 2206 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2207
2208 i.suffix = 0;
2209 }
cd61ebfe 2210 }
24eab124 2211
40fb9820 2212 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2213 if (!add_prefix (FWAIT_OPCODE))
2214 return;
252b5132 2215
29b0f896 2216 /* Check string instruction segment overrides. */
40fb9820 2217 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2218 {
2219 if (!check_string ())
5dd0794d 2220 return;
29b0f896 2221 }
5dd0794d 2222
29b0f896
AM		 2223 if (!process_suffix ())
2224 return;
e413e4e9 2225
29b0f896
AM		 2226 /* Make still unresolved immediate matches conform to size of immediate
2227 given in i.suffix. */
2228 if (!finalize_imm ())
2229 return;
252b5132 2230
40fb9820 2231 if (i.types[0].bitfield.imm1)
29b0f896 2232 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2233
40fb9820 2234 for (j = 0; j < 3; j++)
c6fb90c8
L		 2235 if (i.types[j].bitfield.inoutportreg
2236 || i.types[j].bitfield.shiftcount
2237 || i.types[j].bitfield.acc
2238 || i.types[j].bitfield.floatacc)
40fb9820
L		 2239 i.reg_operands--;
2240
2241 if (i.tm.opcode_modifier.immext)
29b0f896 2242 {
02fc3089
L		 2243 expressionS *exp;
2244
40fb9820 2245 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
ca164297 2246 {
b7d9ef37 2247 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 2248 operands with an opcode suffix which is coded in the same
2249 place as an 8-bit immediate field would be. Here we check
2250 those operands and remove them afterwards. */
2251 unsigned int x;
2252
a4622f40 2253 for (x = 0; x < i.operands; x++)
ca164297 2254 if (i.op[x].regs->reg_num != x)
a540244d
L		 2255 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2256 register_prefix,
2257 i.op[x].regs->reg_name,
2258 x + 1,
2259 i.tm.name);
ca164297
L		 2260 i.operands = 0;
2261 }
2262
29b0f896
AM		 2263 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2264 opcode suffix which is coded in the same place as an 8-bit
2265 immediate field would be. Here we fake an 8-bit immediate
85f10a01
MM		 2266 operand from the opcode suffix stored in tm.extension_opcode.
2267 SSE5 also uses this encoding, for some of its 3 argument
2268 instructions. */
252b5132 2269
85f10a01
MM		 2270 assert (i.imm_operands == 0
2271 && (i.operands <= 2
2272 || (i.tm.cpu_flags.bitfield.cpusse5
2273 && i.operands <= 3)));
252b5132 2274
29b0f896
AM		 2275 exp = &im_expressions[i.imm_operands++];
2276 i.op[i.operands].imms = exp;
c6fb90c8 2277 UINTS_CLEAR (i.types[i.operands]);
40fb9820
L		 2278 i.types[i.operands].bitfield.imm8 = 1;
2279 i.operands++;
29b0f896
AM		 2280 exp->X_op = O_constant;
2281 exp->X_add_number = i.tm.extension_opcode;
2282 i.tm.extension_opcode = None;
2283 }
252b5132 2284
29b0f896
AM		 2285 /* For insns with operands there are more diddles to do to the opcode. */
2286 if (i.operands)
2287 {
2288 if (!process_operands ())
2289 return;
2290 }
40fb9820 2291 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2292 {
2293 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2294 as_warn (_("translating to `%sp'"), i.tm.name);
2295 }
252b5132 2296
29b0f896
AM		 2297 /* Handle conversion of 'int $3' --> special int3 insn. */
2298 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2299 {
2300 i.tm.base_opcode = INT3_OPCODE;
2301 i.imm_operands = 0;
2302 }
252b5132 2303
40fb9820
L		 2304 if ((i.tm.opcode_modifier.jump
2305 || i.tm.opcode_modifier.jumpbyte
2306 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2307 && i.op[0].disps->X_op == O_constant)
2308 {
2309 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2310 the absolute address given by the constant. Since ix86 jumps and
2311 calls are pc relative, we need to generate a reloc. */
2312 i.op[0].disps->X_add_symbol = &abs_symbol;
2313 i.op[0].disps->X_op = O_symbol;
2314 }
252b5132 2315
40fb9820 2316 if (i.tm.opcode_modifier.rex64)
161a04f6 2317 i.rex |= REX_W;
252b5132 2318
29b0f896
AM		 2319 /* For 8 bit registers we need an empty rex prefix. Also if the
2320 instruction already has a prefix, we need to convert old
2321 registers to new ones. */
773f551c 2322
40fb9820 2323 if ((i.types[0].bitfield.reg8
29b0f896 2324 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2325 || (i.types[1].bitfield.reg8
29b0f896 2326 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2327 || ((i.types[0].bitfield.reg8
2328 || i.types[1].bitfield.reg8)
29b0f896
AM		 2329 && i.rex != 0))
2330 {
2331 int x;
726c5dcd 2332
29b0f896
AM		 2333 i.rex |= REX_OPCODE;
2334 for (x = 0; x < 2; x++)
2335 {
2336 /* Look for 8 bit operand that uses old registers. */
40fb9820 2337 if (i.types[x].bitfield.reg8
29b0f896 2338 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2339 {
29b0f896
AM		 2340 /* In case it is "hi" register, give up. */
2341 if (i.op[x].regs->reg_num > 3)
a540244d 2342 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2343 "instruction requiring REX prefix."),
a540244d 2344 register_prefix, i.op[x].regs->reg_name);
773f551c 2345
29b0f896
AM		 2346 /* Otherwise it is equivalent to the extended register.
2347 Since the encoding doesn't change this is merely
2348 cosmetic cleanup for debug output. */
2349
2350 i.op[x].regs = i.op[x].regs + 8;
773f551c 2351 }
29b0f896
AM		 2352 }
2353 }
773f551c 2354
85f10a01
MM		 2355 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2356 REX prefix. */
2357 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2358 {
2359 i.drex.rex = i.rex;
2360 i.rex = 0;
2361 }
2362 else if (i.rex != 0)
29b0f896
AM		 2363 add_prefix (REX_OPCODE | i.rex);
2364
2365 /* We are ready to output the insn. */
2366 output_insn ();
2367}
2368
2369static char *
e3bb37b5 2370parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2371{
2372 char *l = line;
2373 char *token_start = l;
2374 char *mnem_p;
5c6af06e
JB		 2375 int supported;
2376 const template *t;
29b0f896
AM		 2377
2378 /* Non-zero if we found a prefix only acceptable with string insns. */
2379 const char *expecting_string_instruction = NULL;
45288df1 2380
29b0f896
AM		 2381 while (1)
2382 {
2383 mnem_p = mnemonic;
2384 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2385 {
2386 mnem_p++;
2387 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2388 {
29b0f896
AM		 2389 as_bad (_("no such instruction: `%s'"), token_start);
2390 return NULL;
2391 }
2392 l++;
2393 }
2394 if (!is_space_char (*l)
2395 && *l != END_OF_INSN
e44823cf
JB		 2396 && (intel_syntax
2397 || (*l != PREFIX_SEPARATOR
2398 && *l != ',')))
29b0f896
AM		 2399 {
2400 as_bad (_("invalid character %s in mnemonic"),
2401 output_invalid (*l));
2402 return NULL;
2403 }
2404 if (token_start == l)
2405 {
e44823cf 2406 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2407 as_bad (_("expecting prefix; got nothing"));
2408 else
2409 as_bad (_("expecting mnemonic; got nothing"));
2410 return NULL;
2411 }
45288df1 2412
29b0f896
AM		 2413 /* Look up instruction (or prefix) via hash table. */
2414 current_templates = hash_find (op_hash, mnemonic);
47926f60 2415
29b0f896
AM		 2416 if (*l != END_OF_INSN
2417 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2418 && current_templates
40fb9820 2419 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2420 {
c6fb90c8 2421 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2422 {
2423 as_bad ((flag_code != CODE_64BIT
2424 ? _("`%s' is only supported in 64-bit mode")
2425 : _("`%s' is not supported in 64-bit mode")),
2426 current_templates->start->name);
2427 return NULL;
2428 }
29b0f896
AM		 2429 /* If we are in 16-bit mode, do not allow addr16 or data16.
2430 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2431 if ((current_templates->start->opcode_modifier.size16
2432 || current_templates->start->opcode_modifier.size32)
29b0f896 2433 && flag_code != CODE_64BIT
40fb9820 2434 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2435 ^ (flag_code == CODE_16BIT)))
2436 {
2437 as_bad (_("redundant %s prefix"),
2438 current_templates->start->name);
2439 return NULL;
45288df1 2440 }
29b0f896
AM		 2441 /* Add prefix, checking for repeated prefixes. */
2442 switch (add_prefix (current_templates->start->base_opcode))
2443 {
2444 case 0:
2445 return NULL;
2446 case 2:
2447 expecting_string_instruction = current_templates->start->name;
2448 break;
2449 }
2450 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2451 token_start = ++l;
2452 }
2453 else
2454 break;
2455 }
45288df1 2456
29b0f896
AM		 2457 if (!current_templates)
2458 {
2459 /* See if we can get a match by trimming off a suffix. */
2460 switch (mnem_p[-1])
2461 {
2462 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2463 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2464 i.suffix = SHORT_MNEM_SUFFIX;
2465 else
29b0f896
AM		 2466 case BYTE_MNEM_SUFFIX:
2467 case QWORD_MNEM_SUFFIX:
2468 i.suffix = mnem_p[-1];
2469 mnem_p[-1] = '\0';
2470 current_templates = hash_find (op_hash, mnemonic);
2471 break;
2472 case SHORT_MNEM_SUFFIX:
2473 case LONG_MNEM_SUFFIX:
2474 if (!intel_syntax)
2475 {
2476 i.suffix = mnem_p[-1];
2477 mnem_p[-1] = '\0';
2478 current_templates = hash_find (op_hash, mnemonic);
2479 }
2480 break;
252b5132 2481
29b0f896
AM		 2482 /* Intel Syntax. */
2483 case 'd':
2484 if (intel_syntax)
2485 {
9306ca4a 2486 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2487 i.suffix = SHORT_MNEM_SUFFIX;
2488 else
2489 i.suffix = LONG_MNEM_SUFFIX;
2490 mnem_p[-1] = '\0';
2491 current_templates = hash_find (op_hash, mnemonic);
2492 }
2493 break;
2494 }
2495 if (!current_templates)
2496 {
2497 as_bad (_("no such instruction: `%s'"), token_start);
2498 return NULL;
2499 }
2500 }
252b5132 2501
40fb9820
L		 2502 if (current_templates->start->opcode_modifier.jump
2503 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2504 {
2505 /* Check for a branch hint. We allow ",pt" and ",pn" for
2506 predict taken and predict not taken respectively.
2507 I'm not sure that branch hints actually do anything on loop
2508 and jcxz insns (JumpByte) for current Pentium4 chips. They
2509 may work in the future and it doesn't hurt to accept them
2510 now. */
2511 if (l[0] == ',' && l[1] == 'p')
2512 {
2513 if (l[2] == 't')
2514 {
2515 if (!add_prefix (DS_PREFIX_OPCODE))
2516 return NULL;
2517 l += 3;
2518 }
2519 else if (l[2] == 'n')
2520 {
2521 if (!add_prefix (CS_PREFIX_OPCODE))
2522 return NULL;
2523 l += 3;
2524 }
2525 }
2526 }
2527 /* Any other comma loses. */
2528 if (*l == ',')
2529 {
2530 as_bad (_("invalid character %s in mnemonic"),
2531 output_invalid (*l));
2532 return NULL;
2533 }
252b5132 2534
29b0f896 2535 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2536 supported = 0;
2537 for (t = current_templates->start; t < current_templates->end; ++t)
2538 {
40fb9820 2539 if (cpu_flags_match (t->cpu_flags))
64e74474 2540 supported |= 1;
c6fb90c8 2541 if (cpu_flags_check_cpu64 (t->cpu_flags))
64e74474 2542 supported |= 2;
5c6af06e
JB		 2543 }
2544 if (!(supported & 2))
2545 {
2546 as_bad (flag_code == CODE_64BIT
2547 ? _("`%s' is not supported in 64-bit mode")
2548 : _("`%s' is only supported in 64-bit mode"),
2549 current_templates->start->name);
2550 return NULL;
2551 }
2552 if (!(supported & 1))
29b0f896 2553 {
5c6af06e
JB		 2554 as_warn (_("`%s' is not supported on `%s%s'"),
2555 current_templates->start->name,
2556 cpu_arch_name,
2557 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896 2558 }
40fb9820
L		 2559 else if (!cpu_arch_flags.bitfield.cpui386
2560 && (flag_code != CODE_16BIT))
29b0f896
AM		 2561 {
2562 as_warn (_("use .code16 to ensure correct addressing mode"));
2563 }
252b5132 2564
29b0f896 2565 /* Check for rep/repne without a string instruction. */
f41bbced 2566 if (expecting_string_instruction)
29b0f896 2567 {
f41bbced
JB		 2568 static templates override;
2569
2570 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2571 if (t->opcode_modifier.isstring)
f41bbced
JB		 2572 break;
2573 if (t >= current_templates->end)
2574 {
2575 as_bad (_("expecting string instruction after `%s'"),
64e74474 2576 expecting_string_instruction);
f41bbced
JB		 2577 return NULL;
2578 }
2579 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2580 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2581 break;
2582 override.end = t;
2583 current_templates = &override;
29b0f896 2584 }
252b5132 2585
29b0f896
AM		 2586 return l;
2587}
252b5132 2588
29b0f896 2589static char *
e3bb37b5 2590parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2591{
2592 char *token_start;
3138f287 2593
29b0f896
AM		 2594 /* 1 if operand is pending after ','. */
2595 unsigned int expecting_operand = 0;
252b5132 2596
29b0f896
AM		 2597 /* Non-zero if operand parens not balanced. */
2598 unsigned int paren_not_balanced;
2599
2600 while (*l != END_OF_INSN)
2601 {
2602 /* Skip optional white space before operand. */
2603 if (is_space_char (*l))
2604 ++l;
2605 if (!is_operand_char (*l) && *l != END_OF_INSN)
2606 {
2607 as_bad (_("invalid character %s before operand %d"),
2608 output_invalid (*l),
2609 i.operands + 1);
2610 return NULL;
2611 }
2612 token_start = l; /* after white space */
2613 paren_not_balanced = 0;
2614 while (paren_not_balanced || *l != ',')
2615 {
2616 if (*l == END_OF_INSN)
2617 {
2618 if (paren_not_balanced)
2619 {
2620 if (!intel_syntax)
2621 as_bad (_("unbalanced parenthesis in operand %d."),
2622 i.operands + 1);
2623 else
2624 as_bad (_("unbalanced brackets in operand %d."),
2625 i.operands + 1);
2626 return NULL;
2627 }
2628 else
2629 break; /* we are done */
2630 }
2631 else if (!is_operand_char (*l) && !is_space_char (*l))
2632 {
2633 as_bad (_("invalid character %s in operand %d"),
2634 output_invalid (*l),
2635 i.operands + 1);
2636 return NULL;
2637 }
2638 if (!intel_syntax)
2639 {
2640 if (*l == '(')
2641 ++paren_not_balanced;
2642 if (*l == ')')
2643 --paren_not_balanced;
2644 }
2645 else
2646 {
2647 if (*l == '[')
2648 ++paren_not_balanced;
2649 if (*l == ']')
2650 --paren_not_balanced;
2651 }
2652 l++;
2653 }
2654 if (l != token_start)
2655 { /* Yes, we've read in another operand. */
2656 unsigned int operand_ok;
2657 this_operand = i.operands++;
2658 if (i.operands > MAX_OPERANDS)
2659 {
2660 as_bad (_("spurious operands; (%d operands/instruction max)"),
2661 MAX_OPERANDS);
2662 return NULL;
2663 }
2664 /* Now parse operand adding info to 'i' as we go along. */
2665 END_STRING_AND_SAVE (l);
2666
2667 if (intel_syntax)
2668 operand_ok =
2669 i386_intel_operand (token_start,
2670 intel_float_operand (mnemonic));
2671 else
2672 operand_ok = i386_operand (token_start);
2673
2674 RESTORE_END_STRING (l);
2675 if (!operand_ok)
2676 return NULL;
2677 }
2678 else
2679 {
2680 if (expecting_operand)
2681 {
2682 expecting_operand_after_comma:
2683 as_bad (_("expecting operand after ','; got nothing"));
2684 return NULL;
2685 }
2686 if (*l == ',')
2687 {
2688 as_bad (_("expecting operand before ','; got nothing"));
2689 return NULL;
2690 }
2691 }
7f3f1ea2 2692
29b0f896
AM		 2693 /* Now *l must be either ',' or END_OF_INSN. */
2694 if (*l == ',')
2695 {
2696 if (*++l == END_OF_INSN)
2697 {
2698 /* Just skip it, if it's \n complain. */
2699 goto expecting_operand_after_comma;
2700 }
2701 expecting_operand = 1;
2702 }
2703 }
2704 return l;
2705}
7f3f1ea2 2706
050dfa73 2707static void
4d456e3d 2708swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2709{
2710 union i386_op temp_op;
40fb9820 2711 i386_operand_type temp_type;
050dfa73 2712 enum bfd_reloc_code_real temp_reloc;
4eed87de 2713
050dfa73
MM		 2714 temp_type = i.types[xchg2];
2715 i.types[xchg2] = i.types[xchg1];
2716 i.types[xchg1] = temp_type;
2717 temp_op = i.op[xchg2];
2718 i.op[xchg2] = i.op[xchg1];
2719 i.op[xchg1] = temp_op;
2720 temp_reloc = i.reloc[xchg2];
2721 i.reloc[xchg2] = i.reloc[xchg1];
2722 i.reloc[xchg1] = temp_reloc;
2723}
2724
29b0f896 2725static void
e3bb37b5 2726swap_operands (void)
29b0f896 2727{
b7c61d9a 2728 switch (i.operands)
050dfa73 2729 {
b7c61d9a 2730 case 4:
4d456e3d 2731 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2732 case 3:
2733 case 2:
4d456e3d 2734 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2735 break;
2736 default:
2737 abort ();
29b0f896 2738 }
29b0f896
AM		 2739
2740 if (i.mem_operands == 2)
2741 {
2742 const seg_entry *temp_seg;
2743 temp_seg = i.seg[0];
2744 i.seg[0] = i.seg[1];
2745 i.seg[1] = temp_seg;
2746 }
2747}
252b5132 2748
29b0f896
AM		 2749/* Try to ensure constant immediates are represented in the smallest
2750 opcode possible. */
2751static void
e3bb37b5 2752optimize_imm (void)
29b0f896
AM		 2753{
2754 char guess_suffix = 0;
2755 int op;
252b5132 2756
29b0f896
AM		 2757 if (i.suffix)
2758 guess_suffix = i.suffix;
2759 else if (i.reg_operands)
2760 {
2761 /* Figure out a suffix from the last register operand specified.
2762 We can't do this properly yet, ie. excluding InOutPortReg,
2763 but the following works for instructions with immediates.
2764 In any case, we can't set i.suffix yet. */
2765 for (op = i.operands; --op >= 0;)
40fb9820
L		 2766 if (i.types[op].bitfield.reg8)
2767 {
2768 guess_suffix = BYTE_MNEM_SUFFIX;
2769 break;
2770 }
2771 else if (i.types[op].bitfield.reg16)
252b5132 2772 {
40fb9820
L		 2773 guess_suffix = WORD_MNEM_SUFFIX;
2774 break;
2775 }
2776 else if (i.types[op].bitfield.reg32)
2777 {
2778 guess_suffix = LONG_MNEM_SUFFIX;
2779 break;
2780 }
2781 else if (i.types[op].bitfield.reg64)
2782 {
2783 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 2784 break;
252b5132 2785 }
29b0f896
AM		 2786 }
2787 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2788 guess_suffix = WORD_MNEM_SUFFIX;
2789
2790 for (op = i.operands; --op >= 0;)
40fb9820 2791 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 2792 {
2793 switch (i.op[op].imms->X_op)
252b5132 2794 {
29b0f896
AM		 2795 case O_constant:
2796 /* If a suffix is given, this operand may be shortened. */
2797 switch (guess_suffix)
252b5132 2798 {
29b0f896 2799 case LONG_MNEM_SUFFIX:
40fb9820
L		 2800 i.types[op].bitfield.imm32 = 1;
2801 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2802 break;
2803 case WORD_MNEM_SUFFIX:
40fb9820
L		 2804 i.types[op].bitfield.imm16 = 1;
2805 i.types[op].bitfield.imm32 = 1;
2806 i.types[op].bitfield.imm32s = 1;
2807 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2808 break;
2809 case BYTE_MNEM_SUFFIX:
40fb9820
L		 2810 i.types[op].bitfield.imm8 = 1;
2811 i.types[op].bitfield.imm8s = 1;
2812 i.types[op].bitfield.imm16 = 1;
2813 i.types[op].bitfield.imm32 = 1;
2814 i.types[op].bitfield.imm32s = 1;
2815 i.types[op].bitfield.imm64 = 1;
29b0f896 2816 break;
252b5132 2817 }
252b5132 2818
29b0f896
AM		 2819 /* If this operand is at most 16 bits, convert it
2820 to a signed 16 bit number before trying to see
2821 whether it will fit in an even smaller size.
2822 This allows a 16-bit operand such as $0xffe0 to
2823 be recognised as within Imm8S range. */
40fb9820 2824 if ((i.types[op].bitfield.imm16)
29b0f896 2825 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2826 {
29b0f896
AM		 2827 i.op[op].imms->X_add_number =
2828 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2829 }
40fb9820 2830 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 2831 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2832 == 0))
2833 {
2834 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2835 ^ ((offsetT) 1 << 31))
2836 - ((offsetT) 1 << 31));
2837 }
40fb9820 2838 i.types[op]
c6fb90c8
L		 2839 = operand_type_or (i.types[op],
2840 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 2841
29b0f896
AM		 2842 /* We must avoid matching of Imm32 templates when 64bit
2843 only immediate is available. */
2844 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 2845 i.types[op].bitfield.imm32 = 0;
29b0f896 2846 break;
252b5132 2847
29b0f896
AM		 2848 case O_absent:
2849 case O_register:
2850 abort ();
2851
2852 /* Symbols and expressions. */
2853 default:
9cd96992
JB		 2854 /* Convert symbolic operand to proper sizes for matching, but don't
2855 prevent matching a set of insns that only supports sizes other
2856 than those matching the insn suffix. */
2857 {
40fb9820 2858 i386_operand_type mask, allowed;
9cd96992
JB		 2859 const template *t;
2860
c6fb90c8
L		 2861 UINTS_CLEAR (mask);
2862 UINTS_CLEAR (allowed);
40fb9820 2863
4eed87de
AM		 2864 for (t = current_templates->start;
2865 t < current_templates->end;
2866 ++t)
c6fb90c8
L		 2867 allowed = operand_type_or (allowed,
2868 t->operand_types[op]);
9cd96992
JB		 2869 switch (guess_suffix)
2870 {
2871 case QWORD_MNEM_SUFFIX:
40fb9820
L		 2872 mask.bitfield.imm64 = 1;
2873 mask.bitfield.imm32s = 1;
9cd96992
JB		 2874 break;
2875 case LONG_MNEM_SUFFIX:
40fb9820 2876 mask.bitfield.imm32 = 1;
9cd96992
JB		 2877 break;
2878 case WORD_MNEM_SUFFIX:
40fb9820 2879 mask.bitfield.imm16 = 1;
9cd96992
JB		 2880 break;
2881 case BYTE_MNEM_SUFFIX:
40fb9820 2882 mask.bitfield.imm8 = 1;
9cd96992
JB		 2883 break;
2884 default:
9cd96992
JB		 2885 break;
2886 }
c6fb90c8
L		 2887 allowed = operand_type_and (mask, allowed);
2888 if (!UINTS_ALL_ZERO (allowed))
2889 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 2890 }
29b0f896 2891 break;
252b5132 2892 }
29b0f896
AM		 2893 }
2894}
47926f60 2895
29b0f896
AM		 2896/* Try to use the smallest displacement type too. */
2897static void
e3bb37b5 2898optimize_disp (void)
29b0f896
AM		 2899{
2900 int op;
3e73aa7c 2901
29b0f896 2902 for (op = i.operands; --op >= 0;)
40fb9820 2903 if (operand_type_check (i.types[op], disp))
252b5132 2904 {
b300c311 2905 if (i.op[op].disps->X_op == O_constant)
252b5132 2906 {
b300c311 2907 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2908
40fb9820 2909 if (i.types[op].bitfield.disp16
b300c311
L		 2910 && (disp & ~(offsetT) 0xffff) == 0)
2911 {
2912 /* If this operand is at most 16 bits, convert
2913 to a signed 16 bit number and don't use 64bit
2914 displacement. */
2915 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 2916 i.types[op].bitfield.disp64 = 0;
b300c311 2917 }
40fb9820 2918 if (i.types[op].bitfield.disp32
b300c311
L		 2919 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2920 {
2921 /* If this operand is at most 32 bits, convert
2922 to a signed 32 bit number and don't use 64bit
2923 displacement. */
2924 disp &= (((offsetT) 2 << 31) - 1);
2925 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 2926 i.types[op].bitfield.disp64 = 0;
b300c311 2927 }
40fb9820 2928 if (!disp && i.types[op].bitfield.baseindex)
b300c311 2929 {
40fb9820
L		 2930 i.types[op].bitfield.disp8 = 0;
2931 i.types[op].bitfield.disp16 = 0;
2932 i.types[op].bitfield.disp32 = 0;
2933 i.types[op].bitfield.disp32s = 0;
2934 i.types[op].bitfield.disp64 = 0;
b300c311
L		 2935 i.op[op].disps = 0;
2936 i.disp_operands--;
2937 }
2938 else if (flag_code == CODE_64BIT)
2939 {
2940 if (fits_in_signed_long (disp))
28a9d8f5 2941 {
40fb9820
L		 2942 i.types[op].bitfield.disp64 = 0;
2943 i.types[op].bitfield.disp32s = 1;
28a9d8f5 2944 }
b300c311 2945 if (fits_in_unsigned_long (disp))
40fb9820 2946 i.types[op].bitfield.disp32 = 1;
b300c311 2947 }
40fb9820
L		 2948 if ((i.types[op].bitfield.disp32
2949 || i.types[op].bitfield.disp32s
2950 || i.types[op].bitfield.disp16)
b300c311 2951 && fits_in_signed_byte (disp))
40fb9820 2952 i.types[op].bitfield.disp8 = 1;
252b5132 2953 }
67a4f2b7
AO		 2954 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2955 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2956 {
2957 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2958 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 2959 i.types[op].bitfield.disp8 = 0;
2960 i.types[op].bitfield.disp16 = 0;
2961 i.types[op].bitfield.disp32 = 0;
2962 i.types[op].bitfield.disp32s = 0;
2963 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 2964 }
2965 else
b300c311 2966 /* We only support 64bit displacement on constants. */
40fb9820 2967 i.types[op].bitfield.disp64 = 0;
252b5132 2968 }
29b0f896
AM		 2969}
2970
2971static int
e3bb37b5 2972match_template (void)
29b0f896
AM		 2973{
2974 /* Points to template once we've found it. */
2975 const template *t;
40fb9820 2976 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 2977 unsigned int found_reverse_match;
40fb9820
L		 2978 i386_opcode_modifier suffix_check;
2979 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 2980 int addr_prefix_disp;
a5c311ca 2981 unsigned int j;
c6fb90c8 2982 i386_cpu_flags overlap;
29b0f896 2983
f48ff2ae
L		 2984#if MAX_OPERANDS != 4
2985# error "MAX_OPERANDS must be 4."
2986#endif
2987
29b0f896 2988 found_reverse_match = 0;
539e75ad 2989 addr_prefix_disp = -1;
40fb9820
L		 2990
2991 memset (&suffix_check, 0, sizeof (suffix_check));
2992 if (i.suffix == BYTE_MNEM_SUFFIX)
2993 suffix_check.no_bsuf = 1;
2994 else if (i.suffix == WORD_MNEM_SUFFIX)
2995 suffix_check.no_wsuf = 1;
2996 else if (i.suffix == SHORT_MNEM_SUFFIX)
2997 suffix_check.no_ssuf = 1;
2998 else if (i.suffix == LONG_MNEM_SUFFIX)
2999 suffix_check.no_lsuf = 1;
3000 else if (i.suffix == QWORD_MNEM_SUFFIX)
3001 suffix_check.no_qsuf = 1;
3002 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3003 suffix_check.no_xsuf = 1;
29b0f896 3004
45aa61fe 3005 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3006 {
539e75ad
L		 3007 addr_prefix_disp = -1;
3008
29b0f896
AM		 3009 /* Must have right number of operands. */
3010 if (i.operands != t->operands)
3011 continue;
3012
20592a94 3013 /* Check the suffix, except for some instructions in intel mode. */
40fb9820
L		 3014 if (((t->opcode_modifier.no_bsuf & suffix_check.no_bsuf)
3015 || (t->opcode_modifier.no_wsuf & suffix_check.no_wsuf)
3016 || (t->opcode_modifier.no_lsuf & suffix_check.no_lsuf)
3017 || (t->opcode_modifier.no_ssuf & suffix_check.no_ssuf)
3018 || (t->opcode_modifier.no_qsuf & suffix_check.no_qsuf)
3019 || (t->opcode_modifier.no_xsuf & suffix_check.no_xsuf))
3020 && !(intel_syntax && t->opcode_modifier.ignoresize))
29b0f896
AM		 3021 continue;
3022
a5c311ca
L		 3023 for (j = 0; j < MAX_OPERANDS; j++)
3024 operand_types [j] = t->operand_types [j];
539e75ad 3025
45aa61fe
AM		 3026 /* In general, don't allow 64-bit operands in 32-bit mode. */
3027 if (i.suffix == QWORD_MNEM_SUFFIX
3028 && flag_code != CODE_64BIT
3029 && (intel_syntax
40fb9820 3030 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3031 && !intel_float_operand (t->name))
3032 : intel_float_operand (t->name) != 2)
40fb9820
L		 3033 && ((!operand_types[0].bitfield.regmmx
3034 && !operand_types[0].bitfield.regxmm)
3035 || (!operand_types[t->operands > 1].bitfield.regmmx
3036 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3037 && (t->base_opcode != 0x0fc7
3038 || t->extension_opcode != 1 /* cmpxchg8b */))
3039 continue;
3040
29b0f896 3041 /* Do not verify operands when there are none. */
c6fb90c8 3042 else
29b0f896 3043 {
c6fb90c8
L		 3044 overlap = cpu_flags_and (t->cpu_flags, cpu_arch_flags_not);
3045 if (!t->operands)
3046 {
3047 if (!UINTS_ALL_ZERO (overlap))
3048 continue;
3049 /* We've found a match; break out of loop. */
3050 break;
3051 }
29b0f896 3052 }
252b5132 3053
539e75ad
L		 3054 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3055 into Disp32/Disp16/Disp32 operand. */
3056 if (i.prefix[ADDR_PREFIX] != 0)
3057 {
40fb9820 3058 /* There should be only one Disp operand. */
539e75ad
L		 3059 switch (flag_code)
3060 {
3061 case CODE_16BIT:
40fb9820
L		 3062 for (j = 0; j < MAX_OPERANDS; j++)
3063 {
3064 if (operand_types[j].bitfield.disp16)
3065 {
3066 addr_prefix_disp = j;
3067 operand_types[j].bitfield.disp32 = 1;
3068 operand_types[j].bitfield.disp16 = 0;
3069 break;
3070 }
3071 }
539e75ad
L		 3072 break;
3073 case CODE_32BIT:
40fb9820
L		 3074 for (j = 0; j < MAX_OPERANDS; j++)
3075 {
3076 if (operand_types[j].bitfield.disp32)
3077 {
3078 addr_prefix_disp = j;
3079 operand_types[j].bitfield.disp32 = 0;
3080 operand_types[j].bitfield.disp16 = 1;
3081 break;
3082 }
3083 }
539e75ad
L		 3084 break;
3085 case CODE_64BIT:
40fb9820
L		 3086 for (j = 0; j < MAX_OPERANDS; j++)
3087 {
3088 if (operand_types[j].bitfield.disp64)
3089 {
3090 addr_prefix_disp = j;
3091 operand_types[j].bitfield.disp64 = 0;
3092 operand_types[j].bitfield.disp32 = 1;
3093 break;
3094 }
3095 }
539e75ad
L		 3096 break;
3097 }
539e75ad
L		 3098 }
3099
c6fb90c8 3100 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3101 switch (t->operands)
3102 {
3103 case 1:
40fb9820 3104 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3105 continue;
3106 break;
3107 case 2:
8b38ad71
L		 3108 /* xchg %eax, %eax is a special case. It is an aliase for nop
3109 only in 32bit mode and we can use opcode 0x90. In 64bit
3110 mode, we can't use 0x90 for xchg %eax, %eax since it should
3111 zero-extend %eax to %rax. */
3112 if (flag_code == CODE_64BIT
3113 && t->base_opcode == 0x90
c6fb90c8
L		 3114 && UINTS_EQUAL (i.types [0], acc32)
3115 && UINTS_EQUAL (i.types [1], acc32))
8b38ad71 3116 continue;
29b0f896 3117 case 3:
f48ff2ae 3118 case 4:
c6fb90c8 3119 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3120 if (!operand_type_match (overlap0, i.types[0])
3121 || !operand_type_match (overlap1, i.types[1])
cb712a9e 3122 /* monitor in SSE3 is a very special case. The first
708587a4 3123 register and the second register may have different
26186d74
L		 3124 sizes. The same applies to crc32 in SSE4.2. It is
3125 also true for invlpga, vmload, vmrun and vmsave in
3126 SVME. */
cb712a9e 3127 || !((t->base_opcode == 0x0f01
26186d74
L		 3128 && (t->extension_opcode == 0xc8
3129 || t->extension_opcode == 0xd8
3130 || t->extension_opcode == 0xda
3131 || t->extension_opcode == 0xdb
3132 || t->extension_opcode == 0xdf))
381d071f 3133 || t->base_opcode == 0xf20f38f1
40fb9820
L		 3134 || operand_type_register_match (overlap0, i.types[0],
3135 operand_types[0],
3136 overlap1, i.types[1],
3137 operand_types[1])))
29b0f896
AM		 3138 {
3139 /* Check if other direction is valid ... */
40fb9820 3140 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3141 continue;
3142
3143 /* Try reversing direction of operands. */
c6fb90c8
L		 3144 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3145 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3146 if (!operand_type_match (overlap0, i.types[0])
3147 || !operand_type_match (overlap1, i.types[1])
3148 || !operand_type_register_match (overlap0, i.types[0],
3149 operand_types[1],
3150 overlap1, i.types[1],
3151 operand_types[0]))
29b0f896
AM		 3152 {
3153 /* Does not match either direction. */
3154 continue;
3155 }
3156 /* found_reverse_match holds which of D or FloatDR
3157 we've found. */
40fb9820 3158 if (t->opcode_modifier.d)
8a2ed489 3159 found_reverse_match = Opcode_D;
40fb9820 3160 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3161 found_reverse_match = Opcode_FloatD;
3162 else
3163 found_reverse_match = 0;
40fb9820 3164 if (t->opcode_modifier.floatr)
8a2ed489 3165 found_reverse_match |= Opcode_FloatR;
29b0f896 3166 }
f48ff2ae 3167 else
29b0f896 3168 {
f48ff2ae 3169 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3170 switch (t->operands)
3171 {
3172 case 4:
c6fb90c8
L		 3173 overlap3 = operand_type_and (i.types[3],
3174 operand_types[3]);
d1cbb4db 3175 case 3:
c6fb90c8
L		 3176 overlap2 = operand_type_and (i.types[2],
3177 operand_types[2]);
d1cbb4db
L		 3178 break;
3179 }
29b0f896 3180
f48ff2ae
L		 3181 switch (t->operands)
3182 {
3183 case 4:
40fb9820
L		 3184 if (!operand_type_match (overlap3, i.types[3])
3185 || !operand_type_register_match (overlap2,
3186 i.types[2],
3187 operand_types[2],
3188 overlap3,
3189 i.types[3],
3190 operand_types[3]))
f48ff2ae
L		 3191 continue;
3192 case 3:
3193 /* Here we make use of the fact that there are no
3194 reverse match 3 operand instructions, and all 3
3195 operand instructions only need to be checked for
3196 register consistency between operands 2 and 3. */
40fb9820
L		 3197 if (!operand_type_match (overlap2, i.types[2])
3198 || !operand_type_register_match (overlap1,
3199 i.types[1],
3200 operand_types[1],
3201 overlap2,
3202 i.types[2],
3203 operand_types[2]))
f48ff2ae
L		 3204 continue;
3205 break;
3206 }
29b0f896 3207 }
f48ff2ae 3208 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3209 slip through to break. */
3210 }
c6fb90c8 3211 if (!UINTS_ALL_ZERO (overlap))
29b0f896
AM		 3212 {
3213 found_reverse_match = 0;
3214 continue;
3215 }
3216 /* We've found a match; break out of loop. */
3217 break;
3218 }
3219
3220 if (t == current_templates->end)
3221 {
3222 /* We found no match. */
3223 as_bad (_("suffix or operands invalid for `%s'"),
3224 current_templates->start->name);
3225 return 0;
3226 }
252b5132 3227
29b0f896
AM		 3228 if (!quiet_warnings)
3229 {
3230 if (!intel_syntax
40fb9820
L		 3231 && (i.types[0].bitfield.jumpabsolute
3232 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3233 {
3234 as_warn (_("indirect %s without `*'"), t->name);
3235 }
3236
40fb9820
L		 3237 if (t->opcode_modifier.isprefix
3238 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3239 {
3240 /* Warn them that a data or address size prefix doesn't
3241 affect assembly of the next line of code. */
3242 as_warn (_("stand-alone `%s' prefix"), t->name);
3243 }
3244 }
3245
3246 /* Copy the template we found. */
3247 i.tm = *t;
539e75ad
L		 3248
3249 if (addr_prefix_disp != -1)
3250 i.tm.operand_types[addr_prefix_disp]
3251 = operand_types[addr_prefix_disp];
3252
29b0f896
AM		 3253 if (found_reverse_match)
3254 {
3255 /* If we found a reverse match we must alter the opcode
3256 direction bit. found_reverse_match holds bits to change
3257 (different for int & float insns). */
3258
3259 i.tm.base_opcode ^= found_reverse_match;
3260
539e75ad
L		 3261 i.tm.operand_types[0] = operand_types[1];
3262 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3263 }
3264
3265 return 1;
3266}
3267
3268static int
e3bb37b5 3269check_string (void)
29b0f896 3270{
40fb9820
L		 3271 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3272 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3273 {
3274 if (i.seg[0] != NULL && i.seg[0] != &es)
3275 {
3276 as_bad (_("`%s' operand %d must use `%%es' segment"),
3277 i.tm.name,
3278 mem_op + 1);
3279 return 0;
3280 }
3281 /* There's only ever one segment override allowed per instruction.
3282 This instruction possibly has a legal segment override on the
3283 second operand, so copy the segment to where non-string
3284 instructions store it, allowing common code. */
3285 i.seg[0] = i.seg[1];
3286 }
40fb9820 3287 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3288 {
3289 if (i.seg[1] != NULL && i.seg[1] != &es)
3290 {
3291 as_bad (_("`%s' operand %d must use `%%es' segment"),
3292 i.tm.name,
3293 mem_op + 2);
3294 return 0;
3295 }
3296 }
3297 return 1;
3298}
3299
3300static int
543613e9 3301process_suffix (void)
29b0f896
AM		 3302{
3303 /* If matched instruction specifies an explicit instruction mnemonic
3304 suffix, use it. */
40fb9820
L		 3305 if (i.tm.opcode_modifier.size16)
3306 i.suffix = WORD_MNEM_SUFFIX;
3307 else if (i.tm.opcode_modifier.size32)
3308 i.suffix = LONG_MNEM_SUFFIX;
3309 else if (i.tm.opcode_modifier.size64)
3310 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3311 else if (i.reg_operands)
3312 {
3313 /* If there's no instruction mnemonic suffix we try to invent one
3314 based on register operands. */
3315 if (!i.suffix)
3316 {
3317 /* We take i.suffix from the last register operand specified,
3318 Destination register type is more significant than source
381d071f
L		 3319 register type. crc32 in SSE4.2 prefers source register
3320 type. */
3321 if (i.tm.base_opcode == 0xf20f38f1)
3322 {
40fb9820
L		 3323 if (i.types[0].bitfield.reg16)
3324 i.suffix = WORD_MNEM_SUFFIX;
3325 else if (i.types[0].bitfield.reg32)
3326 i.suffix = LONG_MNEM_SUFFIX;
3327 else if (i.types[0].bitfield.reg64)
3328 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3329 }
9344ff29 3330 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3331 {
40fb9820 3332 if (i.types[0].bitfield.reg8)
20592a94
L		 3333 i.suffix = BYTE_MNEM_SUFFIX;
3334 }
381d071f
L		 3335
3336 if (!i.suffix)
3337 {
3338 int op;
3339
20592a94
L		 3340 if (i.tm.base_opcode == 0xf20f38f1
3341 || i.tm.base_opcode == 0xf20f38f0)
3342 {
3343 /* We have to know the operand size for crc32. */
3344 as_bad (_("ambiguous memory operand size for `%s`"),
3345 i.tm.name);
3346 return 0;
3347 }
3348
381d071f 3349 for (op = i.operands; --op >= 0;)
40fb9820 3350 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3351 {
40fb9820
L		 3352 if (i.types[op].bitfield.reg8)
3353 {
3354 i.suffix = BYTE_MNEM_SUFFIX;
3355 break;
3356 }
3357 else if (i.types[op].bitfield.reg16)
3358 {
3359 i.suffix = WORD_MNEM_SUFFIX;
3360 break;
3361 }
3362 else if (i.types[op].bitfield.reg32)
3363 {
3364 i.suffix = LONG_MNEM_SUFFIX;
3365 break;
3366 }
3367 else if (i.types[op].bitfield.reg64)
3368 {
3369 i.suffix = QWORD_MNEM_SUFFIX;
3370 break;
3371 }
381d071f
L		 3372 }
3373 }
29b0f896
AM		 3374 }
3375 else if (i.suffix == BYTE_MNEM_SUFFIX)
3376 {
3377 if (!check_byte_reg ())
3378 return 0;
3379 }
3380 else if (i.suffix == LONG_MNEM_SUFFIX)
3381 {
3382 if (!check_long_reg ())
3383 return 0;
3384 }
3385 else if (i.suffix == QWORD_MNEM_SUFFIX)
3386 {
3387 if (!check_qword_reg ())
3388 return 0;
3389 }
3390 else if (i.suffix == WORD_MNEM_SUFFIX)
3391 {
3392 if (!check_word_reg ())
3393 return 0;
3394 }
40fb9820 3395 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3396 /* Do nothing if the instruction is going to ignore the prefix. */
3397 ;
3398 else
3399 abort ();
3400 }
40fb9820 3401 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3402 && !i.suffix
3403 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3404 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3405 {
3406 i.suffix = stackop_size;
3407 }
9306ca4a
JB		 3408 else if (intel_syntax
3409 && !i.suffix
40fb9820
L		 3410 && (i.tm.operand_types[0].bitfield.jumpabsolute
3411 || i.tm.opcode_modifier.jumpbyte
3412 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3413 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3414 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3415 {
3416 switch (flag_code)
3417 {
3418 case CODE_64BIT:
40fb9820 3419 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3420 {
3421 i.suffix = QWORD_MNEM_SUFFIX;
3422 break;
3423 }
3424 case CODE_32BIT:
40fb9820 3425 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3426 i.suffix = LONG_MNEM_SUFFIX;
3427 break;
3428 case CODE_16BIT:
40fb9820 3429 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3430 i.suffix = WORD_MNEM_SUFFIX;
3431 break;
3432 }
3433 }
252b5132 3434
9306ca4a 3435 if (!i.suffix)
29b0f896 3436 {
9306ca4a
JB		 3437 if (!intel_syntax)
3438 {
40fb9820 3439 if (i.tm.opcode_modifier.w)
9306ca4a 3440 {
4eed87de
AM		 3441 as_bad (_("no instruction mnemonic suffix given and "
3442 "no register operands; can't size instruction"));
9306ca4a
JB		 3443 return 0;
3444 }
3445 }
3446 else
3447 {
40fb9820
L		 3448 unsigned int suffixes;
3449
3450 suffixes = !i.tm.opcode_modifier.no_bsuf;
3451 if (!i.tm.opcode_modifier.no_wsuf)
3452 suffixes |= 1 << 1;
3453 if (!i.tm.opcode_modifier.no_lsuf)
3454 suffixes |= 1 << 2;
3455 if (!i.tm.opcode_modifier.no_lsuf)
3456 suffixes |= 1 << 3;
3457 if (!i.tm.opcode_modifier.no_ssuf)
3458 suffixes |= 1 << 4;
3459 if (!i.tm.opcode_modifier.no_qsuf)
3460 suffixes |= 1 << 5;
3461
3462 /* There are more than suffix matches. */
3463 if (i.tm.opcode_modifier.w
9306ca4a 3464 || ((suffixes & (suffixes - 1))
40fb9820
L		 3465 && !i.tm.opcode_modifier.defaultsize
3466 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3467 {
3468 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3469 return 0;
3470 }
3471 }
29b0f896 3472 }
252b5132 3473
9306ca4a
JB		 3474 /* Change the opcode based on the operand size given by i.suffix;
3475 We don't need to change things for byte insns. */
3476
29b0f896
AM		 3477 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
3478 {
3479 /* It's not a byte, select word/dword operation. */
40fb9820 3480 if (i.tm.opcode_modifier.w)
29b0f896 3481 {
40fb9820 3482 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3483 i.tm.base_opcode |= 8;
3484 else
3485 i.tm.base_opcode |= 1;
3486 }
0f3f3d8b 3487
29b0f896
AM		 3488 /* Now select between word & dword operations via the operand
3489 size prefix, except for instructions that will ignore this
3490 prefix anyway. */
26186d74
L		 3491 if (i.tm.base_opcode == 0x0f01
3492 && (i.tm.extension_opcode == 0xc8
3493 || i.tm.extension_opcode == 0xd8
3494 || i.tm.extension_opcode == 0xda
3495 || i.tm.extension_opcode == 0xdb
3496 || i.tm.extension_opcode == 0xdf))
cb712a9e
L		 3497 {
3498 /* monitor in SSE3 is a very special case. The default size
3499 of AX is the size of mode. The address size override
26186d74
L		 3500 prefix will change the size of AX. It is also true for
3501 invlpga, vmload, vmrun and vmsave in SVME. */
40fb9820
L		 3502 if ((flag_code == CODE_32BIT
3503 && i.op->regs[0].reg_type.bitfield.reg16)
3504 || (flag_code != CODE_32BIT
3505 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3506 if (!add_prefix (ADDR_PREFIX_OPCODE))
3507 return 0;
3508 }
3509 else if (i.suffix != QWORD_MNEM_SUFFIX
3510 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3511 && !i.tm.opcode_modifier.ignoresize
3512 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3513 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3514 || (flag_code == CODE_64BIT
40fb9820 3515 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3516 {
3517 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3518
40fb9820 3519 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3520 prefix = ADDR_PREFIX_OPCODE;
252b5132 3521
29b0f896
AM		 3522 if (!add_prefix (prefix))
3523 return 0;
24eab124 3524 }
252b5132 3525
29b0f896
AM		 3526 /* Set mode64 for an operand. */
3527 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3528 && flag_code == CODE_64BIT
40fb9820 3529 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3530 {
3531 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3532 need rex64. cmpxchg8b is also a special case. */
3533 if (! (i.operands == 2
3534 && i.tm.base_opcode == 0x90
3535 && i.tm.extension_opcode == None
c6fb90c8
L		 3536 && UINTS_EQUAL (i.types [0], acc64)
3537 && UINTS_EQUAL (i.types [1], acc64))
d9a5e5e5
L		 3538 && ! (i.operands == 1
3539 && i.tm.base_opcode == 0xfc7
3540 && i.tm.extension_opcode == 1
40fb9820
L		 3541 && !operand_type_check (i.types [0], reg)
3542 && operand_type_check (i.types [0], anymem)))
f6bee062 3543 i.rex |= REX_W;
46e883c5 3544 }
3e73aa7c 3545
29b0f896
AM		 3546 /* Size floating point instruction. */
3547 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3548 if (i.tm.opcode_modifier.floatmf)
543613e9 3549 i.tm.base_opcode ^= 4;
29b0f896 3550 }
7ecd2f8b 3551
29b0f896
AM		 3552 return 1;
3553}
3e73aa7c 3554
29b0f896 3555static int
543613e9 3556check_byte_reg (void)
29b0f896
AM		 3557{
3558 int op;
543613e9 3559
29b0f896
AM		 3560 for (op = i.operands; --op >= 0;)
3561 {
3562 /* If this is an eight bit register, it's OK. If it's the 16 or
3563 32 bit version of an eight bit register, we will just use the
3564 low portion, and that's OK too. */
40fb9820 3565 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3566 continue;
3567
c3ad16c0
L		 3568 /* movzx, movsx, pextrb and pinsrb should not generate this
3569 warning. */
29b0f896
AM		 3570 if (intel_syntax
3571 && (i.tm.base_opcode == 0xfb7
3572 || i.tm.base_opcode == 0xfb6
3573 || i.tm.base_opcode == 0x63
3574 || i.tm.base_opcode == 0xfbe
c3ad16c0
L		 3575 || i.tm.base_opcode == 0xfbf
3576 || i.tm.base_opcode == 0x660f3a14
3577 || i.tm.base_opcode == 0x660f3a20))
29b0f896
AM		 3578 continue;
3579
9344ff29
L		 3580 /* crc32 doesn't generate this warning. */
3581 if (i.tm.base_opcode == 0xf20f38f0)
3582 continue;
3583
40fb9820
L		 3584 if ((i.types[op].bitfield.reg16
3585 || i.types[op].bitfield.reg32
3586 || i.types[op].bitfield.reg64)
3587 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3588 {
3589 /* Prohibit these changes in the 64bit mode, since the
3590 lowering is more complicated. */
3591 if (flag_code == CODE_64BIT
40fb9820 3592 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3593 {
2ca3ace5
L		 3594 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3595 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3596 i.suffix);
3597 return 0;
3598 }
3599#if REGISTER_WARNINGS
3600 if (!quiet_warnings
40fb9820 3601 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3602 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3603 register_prefix,
40fb9820 3604 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3605 ? REGNAM_AL - REGNAM_AX
3606 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3607 register_prefix,
29b0f896
AM		 3608 i.op[op].regs->reg_name,
3609 i.suffix);
3610#endif
3611 continue;
3612 }
3613 /* Any other register is bad. */
40fb9820
L		 3614 if (i.types[op].bitfield.reg16
3615 || i.types[op].bitfield.reg32
3616 || i.types[op].bitfield.reg64
3617 || i.types[op].bitfield.regmmx
3618 || i.types[op].bitfield.regxmm
3619 || i.types[op].bitfield.sreg2
3620 || i.types[op].bitfield.sreg3
3621 || i.types[op].bitfield.control
3622 || i.types[op].bitfield.debug
3623 || i.types[op].bitfield.test
3624 || i.types[op].bitfield.floatreg
3625 || i.types[op].bitfield.floatacc)
29b0f896 3626 {
a540244d
L		 3627 as_bad (_("`%s%s' not allowed with `%s%c'"),
3628 register_prefix,
29b0f896
AM		 3629 i.op[op].regs->reg_name,
3630 i.tm.name,
3631 i.suffix);
3632 return 0;
3633 }
3634 }
3635 return 1;
3636}
3637
3638static int
e3bb37b5 3639check_long_reg (void)
29b0f896
AM		 3640{
3641 int op;
3642
3643 for (op = i.operands; --op >= 0;)
3644 /* Reject eight bit registers, except where the template requires
3645 them. (eg. movzb) */
40fb9820
L		 3646 if (i.types[op].bitfield.reg8
3647 && (i.tm.operand_types[op].bitfield.reg16
3648 || i.tm.operand_types[op].bitfield.reg32
3649 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3650 {
a540244d
L		 3651 as_bad (_("`%s%s' not allowed with `%s%c'"),
3652 register_prefix,
29b0f896
AM		 3653 i.op[op].regs->reg_name,
3654 i.tm.name,
3655 i.suffix);
3656 return 0;
3657 }
3658 /* Warn if the e prefix on a general reg is missing. */
3659 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3660 && i.types[op].bitfield.reg16
3661 && (i.tm.operand_types[op].bitfield.reg32
3662 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3663 {
3664 /* Prohibit these changes in the 64bit mode, since the
3665 lowering is more complicated. */
3666 if (flag_code == CODE_64BIT)
252b5132 3667 {
2ca3ace5
L		 3668 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3669 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3670 i.suffix);
3671 return 0;
252b5132 3672 }
29b0f896
AM		 3673#if REGISTER_WARNINGS
3674 else
a540244d
L		 3675 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3676 register_prefix,
29b0f896 3677 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3678 register_prefix,
29b0f896
AM		 3679 i.op[op].regs->reg_name,
3680 i.suffix);
3681#endif
252b5132 3682 }
29b0f896 3683 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3684 else if (i.types[op].bitfield.reg64
3685 && (i.tm.operand_types[op].bitfield.reg32
3686 || i.tm.operand_types[op].bitfield.acc))
252b5132 3687 {
34828aad 3688 if (intel_syntax
07e8d93c
L		 3689 && (i.tm.base_opcode == 0xf30f2d
3690 || i.tm.base_opcode == 0xf30f2c)
40fb9820 3691 && !i.types[0].bitfield.regxmm)
34828aad 3692 {
07e8d93c
L		 3693 /* cvtss2si/cvttss2si convert DWORD memory to Reg64. We
3694 want REX byte. */
34828aad
L		 3695 i.suffix = QWORD_MNEM_SUFFIX;
3696 }
3697 else
3698 {
3699 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3700 register_prefix, i.op[op].regs->reg_name,
3701 i.suffix);
3702 return 0;
3703 }
29b0f896
AM		 3704 }
3705 return 1;
3706}
252b5132 3707
29b0f896 3708static int
e3bb37b5 3709check_qword_reg (void)
29b0f896
AM		 3710{
3711 int op;
252b5132 3712
29b0f896
AM		 3713 for (op = i.operands; --op >= 0; )
3714 /* Reject eight bit registers, except where the template requires
3715 them. (eg. movzb) */
40fb9820
L		 3716 if (i.types[op].bitfield.reg8
3717 && (i.tm.operand_types[op].bitfield.reg16
3718 || i.tm.operand_types[op].bitfield.reg32
3719 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3720 {
a540244d
L		 3721 as_bad (_("`%s%s' not allowed with `%s%c'"),
3722 register_prefix,
29b0f896
AM		 3723 i.op[op].regs->reg_name,
3724 i.tm.name,
3725 i.suffix);
3726 return 0;
3727 }
3728 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 3729 else if ((i.types[op].bitfield.reg16
3730 || i.types[op].bitfield.reg32)
3731 && (i.tm.operand_types[op].bitfield.reg32
3732 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3733 {
3734 /* Prohibit these changes in the 64bit mode, since the
3735 lowering is more complicated. */
34828aad 3736 if (intel_syntax
07e8d93c
L		 3737 && (i.tm.base_opcode == 0xf20f2d
3738 || i.tm.base_opcode == 0xf20f2c)
40fb9820 3739 && !i.types[0].bitfield.regxmm)
34828aad 3740 {
07e8d93c
L		 3741 /* cvtsd2si/cvttsd2si convert QWORD memory to Reg32. We
3742 don't want REX byte. */
34828aad
L		 3743 i.suffix = LONG_MNEM_SUFFIX;
3744 }
3745 else
3746 {
3747 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3748 register_prefix, i.op[op].regs->reg_name,
3749 i.suffix);
3750 return 0;
3751 }
252b5132 3752 }
29b0f896
AM		 3753 return 1;
3754}
252b5132 3755
29b0f896 3756static int
e3bb37b5 3757check_word_reg (void)
29b0f896
AM		 3758{
3759 int op;
3760 for (op = i.operands; --op >= 0;)
3761 /* Reject eight bit registers, except where the template requires
3762 them. (eg. movzb) */
40fb9820
L		 3763 if (i.types[op].bitfield.reg8
3764 && (i.tm.operand_types[op].bitfield.reg16
3765 || i.tm.operand_types[op].bitfield.reg32
3766 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3767 {
a540244d
L		 3768 as_bad (_("`%s%s' not allowed with `%s%c'"),
3769 register_prefix,
29b0f896
AM		 3770 i.op[op].regs->reg_name,
3771 i.tm.name,
3772 i.suffix);
3773 return 0;
3774 }
3775 /* Warn if the e prefix on a general reg is present. */
3776 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3777 && i.types[op].bitfield.reg32
3778 && (i.tm.operand_types[op].bitfield.reg16
3779 || i.tm.operand_types[op].bitfield.acc))
252b5132 3780 {
29b0f896
AM		 3781 /* Prohibit these changes in the 64bit mode, since the
3782 lowering is more complicated. */
3783 if (flag_code == CODE_64BIT)
252b5132 3784 {
2ca3ace5
L		 3785 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3786 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3787 i.suffix);
3788 return 0;
252b5132 3789 }
29b0f896
AM		 3790 else
3791#if REGISTER_WARNINGS
a540244d
L		 3792 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3793 register_prefix,
29b0f896 3794 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3795 register_prefix,
29b0f896
AM		 3796 i.op[op].regs->reg_name,
3797 i.suffix);
3798#endif
3799 }
3800 return 1;
3801}
252b5132 3802
29b0f896 3803static int
40fb9820 3804update_imm (unsigned int j)
29b0f896 3805{
40fb9820
L		 3806 i386_operand_type overlap;
3807
c6fb90c8 3808 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 3809 if ((overlap.bitfield.imm8
3810 || overlap.bitfield.imm8s
3811 || overlap.bitfield.imm16
3812 || overlap.bitfield.imm32
3813 || overlap.bitfield.imm32s
3814 || overlap.bitfield.imm64)
c6fb90c8
L		 3815 && !UINTS_EQUAL (overlap, imm8)
3816 && !UINTS_EQUAL (overlap, imm8s)
3817 && !UINTS_EQUAL (overlap, imm16)
3818 && !UINTS_EQUAL (overlap, imm32)
3819 && !UINTS_EQUAL (overlap, imm32s)
3820 && !UINTS_EQUAL (overlap, imm64))
29b0f896
AM		 3821 {
3822 if (i.suffix)
3823 {
40fb9820
L		 3824 i386_operand_type temp;
3825
c6fb90c8 3826 UINTS_CLEAR (temp);
40fb9820
L		 3827 if (i.suffix == BYTE_MNEM_SUFFIX)
3828 {
3829 temp.bitfield.imm8 = overlap.bitfield.imm8;
3830 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3831 }
3832 else if (i.suffix == WORD_MNEM_SUFFIX)
3833 temp.bitfield.imm16 = overlap.bitfield.imm16;
3834 else if (i.suffix == QWORD_MNEM_SUFFIX)
3835 {
3836 temp.bitfield.imm64 = overlap.bitfield.imm64;
3837 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3838 }
3839 else
3840 temp.bitfield.imm32 = overlap.bitfield.imm32;
3841 overlap = temp;
29b0f896 3842 }
c6fb90c8
L		 3843 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3844 || UINTS_EQUAL (overlap, imm16_32)
3845 || UINTS_EQUAL (overlap, imm16_32s))
29b0f896 3846 {
c6fb90c8 3847 UINTS_CLEAR (overlap);
40fb9820
L		 3848 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3849 overlap.bitfield.imm16 = 1;
3850 else
3851 overlap.bitfield.imm32s = 1;
29b0f896 3852 }
c6fb90c8
L		 3853 if (!UINTS_EQUAL (overlap, imm8)
3854 && !UINTS_EQUAL (overlap, imm8s)
3855 && !UINTS_EQUAL (overlap, imm16)
3856 && !UINTS_EQUAL (overlap, imm32)
3857 && !UINTS_EQUAL (overlap, imm32s)
3858 && !UINTS_EQUAL (overlap, imm64))
29b0f896 3859 {
4eed87de
AM		 3860 as_bad (_("no instruction mnemonic suffix given; "
3861 "can't determine immediate size"));
29b0f896
AM		 3862 return 0;
3863 }
3864 }
40fb9820 3865 i.types[j] = overlap;
29b0f896 3866
40fb9820
L		 3867 return 1;
3868}
3869
3870static int
3871finalize_imm (void)
3872{
3873 unsigned int j;
29b0f896 3874
40fb9820
L		 3875 for (j = 0; j < 2; j++)
3876 if (update_imm (j) == 0)
3877 return 0;
3878
c6fb90c8 3879 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 3880 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 3881
3882 return 1;
3883}
3884
85f10a01
MM		 3885static void
3886process_drex (void)
3887{
3888 i.drex.modrm_reg = None;
3889 i.drex.modrm_regmem = None;
3890
3891 /* SSE5 4 operand instructions must have the destination the same as
3892 one of the inputs. Figure out the destination register and cache
3893 it away in the drex field, and remember which fields to use for
3894 the modrm byte. */
3895 if (i.tm.opcode_modifier.drex
3896 && i.tm.opcode_modifier.drexv
3897 && i.operands == 4)
3898 {
3899 i.tm.extension_opcode = None;
3900
3901 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3902 if (i.types[0].bitfield.regxmm != 0
3903 && i.types[1].bitfield.regxmm != 0
3904 && i.types[2].bitfield.regxmm != 0
3905 && i.types[3].bitfield.regxmm != 0
3906 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3907 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3908 {
3909 /* Clear the arguments that are stored in drex. */
3910 UINTS_CLEAR (i.types[0]);
3911 UINTS_CLEAR (i.types[3]);
3912 i.reg_operands -= 2;
3913
3914 /* There are two different ways to encode a 4 operand
3915 instruction with all registers that uses OC1 set to
3916 0 or 1. Favor setting OC1 to 0 since this mimics the
3917 actions of other SSE5 assemblers. Use modrm encoding 2
3918 for register/register. Include the high order bit that
3919 is normally stored in the REX byte in the register
3920 field. */
3921 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3922 i.drex.modrm_reg = 2;
3923 i.drex.modrm_regmem = 1;
3924 i.drex.reg = (i.op[3].regs->reg_num
3925 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3926 }
3927
3928 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3929 else if (i.types[0].bitfield.regxmm != 0
3930 && i.types[1].bitfield.regxmm != 0
3931 && (i.types[2].bitfield.regxmm
3932 || operand_type_check (i.types[2], anymem))
3933 && i.types[3].bitfield.regxmm != 0
3934 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3935 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3936 {
3937 /* clear the arguments that are stored in drex */
3938 UINTS_CLEAR (i.types[0]);
3939 UINTS_CLEAR (i.types[3]);
3940 i.reg_operands -= 2;
3941
3942 /* Specify the modrm encoding for memory addressing. Include
3943 the high order bit that is normally stored in the REX byte
3944 in the register field. */
3945 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
3946 i.drex.modrm_reg = 1;
3947 i.drex.modrm_regmem = 2;
3948 i.drex.reg = (i.op[3].regs->reg_num
3949 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3950 }
3951
3952 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3953 else if (i.types[0].bitfield.regxmm != 0
3954 && operand_type_check (i.types[1], anymem) != 0
3955 && i.types[2].bitfield.regxmm != 0
3956 && i.types[3].bitfield.regxmm != 0
3957 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3958 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3959 {
3960 /* Clear the arguments that are stored in drex. */
3961 UINTS_CLEAR (i.types[0]);
3962 UINTS_CLEAR (i.types[3]);
3963 i.reg_operands -= 2;
3964
3965 /* Specify the modrm encoding for memory addressing. Include
3966 the high order bit that is normally stored in the REX byte
3967 in the register field. */
3968 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3969 i.drex.modrm_reg = 2;
3970 i.drex.modrm_regmem = 1;
3971 i.drex.reg = (i.op[3].regs->reg_num
3972 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3973 }
3974
3975 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
3976 else if (i.types[0].bitfield.regxmm != 0
3977 && i.types[1].bitfield.regxmm != 0
3978 && i.types[2].bitfield.regxmm != 0
3979 && i.types[3].bitfield.regxmm != 0
3980 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
3981 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
3982 {
3983 /* clear the arguments that are stored in drex */
3984 UINTS_CLEAR (i.types[2]);
3985 UINTS_CLEAR (i.types[3]);
3986 i.reg_operands -= 2;
3987
3988 /* There are two different ways to encode a 4 operand
3989 instruction with all registers that uses OC1 set to
3990 0 or 1. Favor setting OC1 to 0 since this mimics the
3991 actions of other SSE5 assemblers. Use modrm encoding
3992 2 for register/register. Include the high order bit that
3993 is normally stored in the REX byte in the register
3994 field. */
3995 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
3996 i.drex.modrm_reg = 1;
3997 i.drex.modrm_regmem = 0;
3998
3999 /* Remember the register, including the upper bits */
4000 i.drex.reg = (i.op[3].regs->reg_num
4001 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4002 }
4003
4004 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4005 else if (i.types[0].bitfield.regxmm != 0
4006 && (i.types[1].bitfield.regxmm
4007 || operand_type_check (i.types[1], anymem))
4008 && i.types[2].bitfield.regxmm != 0
4009 && i.types[3].bitfield.regxmm != 0
4010 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4011 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4012 {
4013 /* Clear the arguments that are stored in drex. */
4014 UINTS_CLEAR (i.types[2]);
4015 UINTS_CLEAR (i.types[3]);
4016 i.reg_operands -= 2;
4017
4018 /* Specify the modrm encoding and remember the register
4019 including the bits normally stored in the REX byte. */
4020 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4021 i.drex.modrm_reg = 0;
4022 i.drex.modrm_regmem = 1;
4023 i.drex.reg = (i.op[3].regs->reg_num
4024 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4025 }
4026
4027 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4028 else if (operand_type_check (i.types[0], anymem) != 0
4029 && i.types[1].bitfield.regxmm != 0
4030 && i.types[2].bitfield.regxmm != 0
4031 && i.types[3].bitfield.regxmm != 0
4032 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4033 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4034 {
4035 /* clear the arguments that are stored in drex */
4036 UINTS_CLEAR (i.types[2]);
4037 UINTS_CLEAR (i.types[3]);
4038 i.reg_operands -= 2;
4039
4040 /* Specify the modrm encoding and remember the register
4041 including the bits normally stored in the REX byte. */
4042 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4043 i.drex.modrm_reg = 1;
4044 i.drex.modrm_regmem = 0;
4045 i.drex.reg = (i.op[3].regs->reg_num
4046 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4047 }
4048
4049 else
4050 as_bad (_("Incorrect operands for the '%s' instruction"),
4051 i.tm.name);
4052 }
4053
4054 /* SSE5 instructions with the DREX byte where the only memory operand
4055 is in the 2nd argument, and the first and last xmm register must
4056 match, and is encoded in the DREX byte. */
4057 else if (i.tm.opcode_modifier.drex
4058 && !i.tm.opcode_modifier.drexv
4059 && i.operands == 4)
4060 {
4061 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4062 if (i.types[0].bitfield.regxmm != 0
4063 && (i.types[1].bitfield.regxmm
4064 || operand_type_check(i.types[1], anymem))
4065 && i.types[2].bitfield.regxmm != 0
4066 && i.types[3].bitfield.regxmm != 0
4067 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4068 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4069 {
4070 /* clear the arguments that are stored in drex */
4071 UINTS_CLEAR (i.types[0]);
4072 UINTS_CLEAR (i.types[3]);
4073 i.reg_operands -= 2;
4074
4075 /* Specify the modrm encoding and remember the register
4076 including the high bit normally stored in the REX
4077 byte. */
4078 i.drex.modrm_reg = 2;
4079 i.drex.modrm_regmem = 1;
4080 i.drex.reg = (i.op[3].regs->reg_num
4081 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4082 }
4083
4084 else
4085 as_bad (_("Incorrect operands for the '%s' instruction"),
4086 i.tm.name);
4087 }
4088
4089 /* SSE5 3 operand instructions that the result is a register, being
4090 either operand can be a memory operand, using OC0 to note which
4091 one is the memory. */
4092 else if (i.tm.opcode_modifier.drex
4093 && i.tm.opcode_modifier.drexv
4094 && i.operands == 3)
4095 {
4096 i.tm.extension_opcode = None;
4097
4098 /* Case 1: 3 operand insn, src1 = register. */
4099 if (i.types[0].bitfield.regxmm != 0
4100 && i.types[1].bitfield.regxmm != 0
4101 && i.types[2].bitfield.regxmm != 0)
4102 {
4103 /* Clear the arguments that are stored in drex. */
4104 UINTS_CLEAR (i.types[2]);
4105 i.reg_operands--;
4106
4107 /* Specify the modrm encoding and remember the register
4108 including the high bit normally stored in the REX byte. */
4109 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4110 i.drex.modrm_reg = 1;
4111 i.drex.modrm_regmem = 0;
4112 i.drex.reg = (i.op[2].regs->reg_num
4113 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4114 }
4115
4116 /* Case 2: 3 operand insn, src1 = memory. */
4117 else if (operand_type_check (i.types[0], anymem) != 0
4118 && i.types[1].bitfield.regxmm != 0
4119 && i.types[2].bitfield.regxmm != 0)
4120 {
4121 /* Clear the arguments that are stored in drex. */
4122 UINTS_CLEAR (i.types[2]);
4123 i.reg_operands--;
4124
4125 /* Specify the modrm encoding and remember the register
4126 including the high bit normally stored in the REX
4127 byte. */
4128 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4129 i.drex.modrm_reg = 1;
4130 i.drex.modrm_regmem = 0;
4131 i.drex.reg = (i.op[2].regs->reg_num
4132 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4133 }
4134
4135 /* Case 3: 3 operand insn, src2 = memory. */
4136 else if (i.types[0].bitfield.regxmm != 0
4137 && operand_type_check (i.types[1], anymem) != 0
4138 && i.types[2].bitfield.regxmm != 0)
4139 {
4140 /* Clear the arguments that are stored in drex. */
4141 UINTS_CLEAR (i.types[2]);
4142 i.reg_operands--;
4143
4144 /* Specify the modrm encoding and remember the register
4145 including the high bit normally stored in the REX byte. */
4146 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4147 i.drex.modrm_reg = 0;
4148 i.drex.modrm_regmem = 1;
4149 i.drex.reg = (i.op[2].regs->reg_num
4150 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4151 }
4152
4153 else
4154 as_bad (_("Incorrect operands for the '%s' instruction"),
4155 i.tm.name);
4156 }
4157
4158 /* SSE5 4 operand instructions that are the comparison instructions
4159 where the first operand is the immediate value of the comparison
4160 to be done. */
4161 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4162 {
4163 /* Case 1: 4 operand insn, src1 = reg/memory. */
4164 if (operand_type_check (i.types[0], imm) != 0
4165 && (i.types[1].bitfield.regxmm
4166 || operand_type_check (i.types[1], anymem))
4167 && i.types[2].bitfield.regxmm != 0
4168 && i.types[3].bitfield.regxmm != 0)
4169 {
4170 /* clear the arguments that are stored in drex */
4171 UINTS_CLEAR (i.types[3]);
4172 i.reg_operands--;
4173
4174 /* Specify the modrm encoding and remember the register
4175 including the high bit normally stored in the REX byte. */
4176 i.drex.modrm_reg = 2;
4177 i.drex.modrm_regmem = 1;
4178 i.drex.reg = (i.op[3].regs->reg_num
4179 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4180 }
4181
4182 /* Case 2: 3 operand insn with ImmExt that places the
4183 opcode_extension as an immediate argument. This is used for
4184 all of the varients of comparison that supplies the appropriate
4185 value as part of the instruction. */
4186 else if ((i.types[0].bitfield.regxmm
4187 || operand_type_check (i.types[0], anymem))
4188 && i.types[1].bitfield.regxmm != 0
4189 && i.types[2].bitfield.regxmm != 0
4190 && operand_type_check (i.types[3], imm) != 0)
4191 {
4192 /* clear the arguments that are stored in drex */
4193 UINTS_CLEAR (i.types[2]);
4194 i.reg_operands--;
4195
4196 /* Specify the modrm encoding and remember the register
4197 including the high bit normally stored in the REX byte. */
4198 i.drex.modrm_reg = 1;
4199 i.drex.modrm_regmem = 0;
4200 i.drex.reg = (i.op[2].regs->reg_num
4201 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4202 }
4203
4204 else
4205 as_bad (_("Incorrect operands for the '%s' instruction"),
4206 i.tm.name);
4207 }
4208
4209 else if (i.tm.opcode_modifier.drex
4210 || i.tm.opcode_modifier.drexv
4211 || i.tm.opcode_modifier.drexc)
4212 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4213}
4214
29b0f896 4215static int
e3bb37b5 4216process_operands (void)
29b0f896
AM		 4217{
4218 /* Default segment register this instruction will use for memory
4219 accesses. 0 means unknown. This is only for optimizing out
4220 unnecessary segment overrides. */
4221 const seg_entry *default_seg = 0;
4222
85f10a01
MM		 4223 /* Handle all of the DREX munging that SSE5 needs. */
4224 if (i.tm.opcode_modifier.drex
4225 || i.tm.opcode_modifier.drexv
4226 || i.tm.opcode_modifier.drexc)
4227 process_drex ();
4228
29b0f896
AM		 4229 /* The imul $imm, %reg instruction is converted into
4230 imul $imm, %reg, %reg, and the clr %reg instruction
4231 is converted into xor %reg, %reg. */
40fb9820 4232 if (i.tm.opcode_modifier.regkludge)
29b0f896 4233 {
40fb9820 4234 if (i.tm.cpu_flags.bitfield.cpusse4_1)
42903f7f
L		 4235 {
4236 /* The first operand in instruction blendvpd, blendvps and
4237 pblendvb in SSE4.1 is implicit and must be xmm0. */
4238 assert (i.operands == 3
4239 && i.reg_operands >= 2
c6fb90c8 4240 && UINTS_EQUAL (i.types[0], regxmm));
42903f7f
L		 4241 if (i.op[0].regs->reg_num != 0)
4242 {
4243 if (intel_syntax)
4244 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4245 i.tm.name, register_prefix);
4246 else
4247 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4248 i.tm.name, register_prefix);
4249 return 0;
4250 }
4251 i.op[0] = i.op[1];
4252 i.op[1] = i.op[2];
4253 i.types[0] = i.types[1];
4254 i.types[1] = i.types[2];
4255 i.operands--;
4256 i.reg_operands--;
4257
4258 /* We need to adjust fields in i.tm since they are used by
4259 build_modrm_byte. */
4260 i.tm.operand_types [0] = i.tm.operand_types [1];
4261 i.tm.operand_types [1] = i.tm.operand_types [2];
4262 i.tm.operands--;
4263 }
4264 else
4265 {
40fb9820
L		 4266 unsigned int first_reg_op;
4267
4268 if (operand_type_check (i.types[0], reg))
4269 first_reg_op = 0;
4270 else
4271 first_reg_op = 1;
42903f7f
L		 4272 /* Pretend we saw the extra register operand. */
4273 assert (i.reg_operands == 1
4274 && i.op[first_reg_op + 1].regs == 0);
4275 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4276 i.types[first_reg_op + 1] = i.types[first_reg_op];
4277 i.operands++;
4278 i.reg_operands++;
4279 }
29b0f896
AM		 4280 }
4281
40fb9820 4282 if (i.tm.opcode_modifier.shortform)
29b0f896 4283 {
40fb9820
L		 4284 if (i.types[0].bitfield.sreg2
4285 || i.types[0].bitfield.sreg3)
29b0f896 4286 {
4eed87de
AM		 4287 if (i.tm.base_opcode == POP_SEG_SHORT
4288 && i.op[0].regs->reg_num == 1)
29b0f896 4289 {
4eed87de
AM		 4290 as_bad (_("you can't `pop %%cs'"));
4291 return 0;
29b0f896 4292 }
4eed87de
AM		 4293 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4294 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4295 i.rex |= REX_B;
4eed87de
AM		 4296 }
4297 else
4298 {
85f10a01
MM		 4299 /* The register or float register operand is in operand
4300 0 or 1. */
40fb9820
L		 4301 unsigned int op;
4302
4303 if (i.types[0].bitfield.floatreg
4304 || operand_type_check (i.types[0], reg))
4305 op = 0;
4306 else
4307 op = 1;
4eed87de
AM		 4308 /* Register goes in low 3 bits of opcode. */
4309 i.tm.base_opcode |= i.op[op].regs->reg_num;
4310 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4311 i.rex |= REX_B;
40fb9820 4312 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4313 {
4eed87de
AM		 4314 /* Warn about some common errors, but press on regardless.
4315 The first case can be generated by gcc (<= 2.8.1). */
4316 if (i.operands == 2)
4317 {
4318 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4319 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4320 register_prefix, i.op[1].regs->reg_name,
4321 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4322 }
4323 else
4324 {
4325 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4326 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4327 register_prefix, i.op[0].regs->reg_name);
4eed87de 4328 }
29b0f896
AM		 4329 }
4330 }
4331 }
40fb9820 4332 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4333 {
4334 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4335 must be put into the modrm byte). Now, we make the modrm and
4336 index base bytes based on all the info we've collected. */
29b0f896
AM		 4337
4338 default_seg = build_modrm_byte ();
4339 }
8a2ed489 4340 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4341 {
4342 default_seg = &ds;
4343 }
40fb9820 4344 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4345 {
4346 /* For the string instructions that allow a segment override
4347 on one of their operands, the default segment is ds. */
4348 default_seg = &ds;
4349 }
4350
75178d9d
L		 4351 if (i.tm.base_opcode == 0x8d /* lea */
4352 && i.seg[0]
4353 && !quiet_warnings)
30123838 4354 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4355
4356 /* If a segment was explicitly specified, and the specified segment
4357 is not the default, use an opcode prefix to select it. If we
4358 never figured out what the default segment is, then default_seg
4359 will be zero at this point, and the specified segment prefix will
4360 always be used. */
29b0f896
AM		 4361 if ((i.seg[0]) && (i.seg[0] != default_seg))
4362 {
4363 if (!add_prefix (i.seg[0]->seg_prefix))
4364 return 0;
4365 }
4366 return 1;
4367}
4368
4369static const seg_entry *
e3bb37b5 4370build_modrm_byte (void)
29b0f896
AM		 4371{
4372 const seg_entry *default_seg = 0;
4373
85f10a01
MM		 4374 /* SSE5 4 operand instructions are encoded in such a way that one of
4375 the inputs must match the destination register. Process_drex hides
4376 the 3rd argument in the drex field, so that by the time we get
4377 here, it looks to GAS as if this is a 2 operand instruction. */
4378 if ((i.tm.opcode_modifier.drex
4379 || i.tm.opcode_modifier.drexv
b5016f89 4380 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4381 && i.reg_operands == 2)
4382 {
4383 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4384 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4385
4386 i.rm.reg = reg->reg_num;
4387 i.rm.regmem = regmem->reg_num;
4388 i.rm.mode = 3;
4389 if ((reg->reg_flags & RegRex) != 0)
4390 i.rex |= REX_R;
4391 if ((regmem->reg_flags & RegRex) != 0)
4392 i.rex |= REX_B;
4393 }
4394
29b0f896
AM		 4395 /* i.reg_operands MUST be the number of real register operands;
4396 implicit registers do not count. */
85f10a01 4397 else if (i.reg_operands == 2)
29b0f896
AM		 4398 {
4399 unsigned int source, dest;
cab737b9
L		 4400
4401 switch (i.operands)
4402 {
4403 case 2:
4404 source = 0;
4405 break;
4406 case 3:
c81128dc
L		 4407 /* When there are 3 operands, one of them may be immediate,
4408 which may be the first or the last operand. Otherwise,
4409 the first operand must be shift count register (cl). */
4410 assert (i.imm_operands == 1
4411 || (i.imm_operands == 0
40fb9820
L		 4412 && i.types[0].bitfield.shiftcount));
4413 if (operand_type_check (i.types[0], imm)
4414 || i.types[0].bitfield.shiftcount)
4415 source = 1;
4416 else
4417 source = 0;
cab737b9
L		 4418 break;
4419 case 4:
4420 /* When there are 4 operands, the first two must be immediate
4421 operands. The source operand will be the 3rd one. */
4422 assert (i.imm_operands == 2
40fb9820
L		 4423 && operand_type_check (i.types[0], imm)
4424 && operand_type_check (i.types[1], imm));
cab737b9
L		 4425 source = 2;
4426 break;
4427 default:
4428 abort ();
4429 }
4430
29b0f896
AM		 4431 dest = source + 1;
4432
4433 i.rm.mode = 3;
4434 /* One of the register operands will be encoded in the i.tm.reg
4435 field, the other in the combined i.tm.mode and i.tm.regmem
4436 fields. If no form of this instruction supports a memory
4437 destination operand, then we assume the source operand may
4438 sometimes be a memory operand and so we need to store the
4439 destination in the i.rm.reg field. */
40fb9820
L		 4440 if (!i.tm.operand_types[dest].bitfield.regmem
4441 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4442 {
4443 i.rm.reg = i.op[dest].regs->reg_num;
4444 i.rm.regmem = i.op[source].regs->reg_num;
4445 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4446 i.rex |= REX_R;
29b0f896 4447 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4448 i.rex |= REX_B;
29b0f896
AM		 4449 }
4450 else
4451 {
4452 i.rm.reg = i.op[source].regs->reg_num;
4453 i.rm.regmem = i.op[dest].regs->reg_num;
4454 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4455 i.rex |= REX_B;
29b0f896 4456 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4457 i.rex |= REX_R;
29b0f896 4458 }
161a04f6 4459 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4460 {
40fb9820
L		 4461 if (!i.types[0].bitfield.control
4462 && !i.types[1].bitfield.control)
c4a530c5 4463 abort ();
161a04f6 4464 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4465 add_prefix (LOCK_PREFIX_OPCODE);
4466 }
29b0f896
AM		 4467 }
4468 else
4469 { /* If it's not 2 reg operands... */
4470 if (i.mem_operands)
4471 {
4472 unsigned int fake_zero_displacement = 0;
99018f42 4473 unsigned int op;
4eed87de 4474
85f10a01
MM		 4475 /* This has been precalculated for SSE5 instructions
4476 that have a DREX field earlier in process_drex. */
b5016f89
L		 4477 if (i.tm.opcode_modifier.drex
4478 || i.tm.opcode_modifier.drexv
4479 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4480 op = i.drex.modrm_regmem;
4481 else
4482 {
c0209578
L		 4483 for (op = 0; op < i.operands; op++)
4484 if (operand_type_check (i.types[op], anymem))
4485 break;
4486 assert (op < i.operands);
85f10a01 4487 }
29b0f896
AM		 4488
4489 default_seg = &ds;
4490
4491 if (i.base_reg == 0)
4492 {
4493 i.rm.mode = 0;
4494 if (!i.disp_operands)
4495 fake_zero_displacement = 1;
4496 if (i.index_reg == 0)
4497 {
4498 /* Operand is just <disp> */
20f0a1fc 4499 if (flag_code == CODE_64BIT)
29b0f896
AM		 4500 {
4501 /* 64bit mode overwrites the 32bit absolute
4502 addressing by RIP relative addressing and
4503 absolute addressing is encoded by one of the
4504 redundant SIB forms. */
4505 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4506 i.sib.base = NO_BASE_REGISTER;
4507 i.sib.index = NO_INDEX_REGISTER;
fc225355 4508 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4509 ? disp32s : disp32);
20f0a1fc 4510 }
fc225355
L		 4511 else if ((flag_code == CODE_16BIT)
4512 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4513 {
4514 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4515 i.types[op] = disp16;
20f0a1fc
NC		 4516 }
4517 else
4518 {
4519 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4520 i.types[op] = disp32;
29b0f896
AM		 4521 }
4522 }
4523 else /* !i.base_reg && i.index_reg */
4524 {
db51cc60
L		 4525 if (i.index_reg->reg_num == RegEiz
4526 || i.index_reg->reg_num == RegRiz)
4527 i.sib.index = NO_INDEX_REGISTER;
4528 else
4529 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4530 i.sib.base = NO_BASE_REGISTER;
4531 i.sib.scale = i.log2_scale_factor;
4532 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4533 i.types[op].bitfield.disp8 = 0;
4534 i.types[op].bitfield.disp16 = 0;
4535 i.types[op].bitfield.disp64 = 0;
29b0f896 4536 if (flag_code != CODE_64BIT)
40fb9820
L		 4537 {
4538 /* Must be 32 bit */
4539 i.types[op].bitfield.disp32 = 1;
4540 i.types[op].bitfield.disp32s = 0;
4541 }
29b0f896 4542 else
40fb9820
L		 4543 {
4544 i.types[op].bitfield.disp32 = 0;
4545 i.types[op].bitfield.disp32s = 1;
4546 }
29b0f896 4547 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4548 i.rex |= REX_X;
29b0f896
AM		 4549 }
4550 }
4551 /* RIP addressing for 64bit mode. */
9a04903e
JB		 4552 else if (i.base_reg->reg_num == RegRip ||
4553 i.base_reg->reg_num == RegEip)
29b0f896
AM		 4554 {
4555 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4556 i.types[op].bitfield.disp8 = 0;
4557 i.types[op].bitfield.disp16 = 0;
4558 i.types[op].bitfield.disp32 = 0;
4559 i.types[op].bitfield.disp32s = 1;
4560 i.types[op].bitfield.disp64 = 0;
71903a11 4561 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4562 if (! i.disp_operands)
4563 fake_zero_displacement = 1;
29b0f896 4564 }
40fb9820 4565 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4566 {
4567 switch (i.base_reg->reg_num)
4568 {
4569 case 3: /* (%bx) */
4570 if (i.index_reg == 0)
4571 i.rm.regmem = 7;
4572 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4573 i.rm.regmem = i.index_reg->reg_num - 6;
4574 break;
4575 case 5: /* (%bp) */
4576 default_seg = &ss;
4577 if (i.index_reg == 0)
4578 {
4579 i.rm.regmem = 6;
40fb9820 4580 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4581 {
4582 /* fake (%bp) into 0(%bp) */
40fb9820 4583 i.types[op].bitfield.disp8 = 1;
252b5132 4584 fake_zero_displacement = 1;
29b0f896
AM		 4585 }
4586 }
4587 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4588 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4589 break;
4590 default: /* (%si) -> 4 or (%di) -> 5 */
4591 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4592 }
4593 i.rm.mode = mode_from_disp_size (i.types[op]);
4594 }
4595 else /* i.base_reg and 32/64 bit mode */
4596 {
4597 if (flag_code == CODE_64BIT
40fb9820
L		 4598 && operand_type_check (i.types[op], disp))
4599 {
4600 i386_operand_type temp;
c6fb90c8 4601 UINTS_CLEAR (temp);
40fb9820
L		 4602 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4603 i.types[op] = temp;
4604 if (i.prefix[ADDR_PREFIX] == 0)
4605 i.types[op].bitfield.disp32s = 1;
4606 else
4607 i.types[op].bitfield.disp32 = 1;
4608 }
20f0a1fc 4609
29b0f896
AM		 4610 i.rm.regmem = i.base_reg->reg_num;
4611 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4612 i.rex |= REX_B;
29b0f896
AM		 4613 i.sib.base = i.base_reg->reg_num;
4614 /* x86-64 ignores REX prefix bit here to avoid decoder
4615 complications. */
4616 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4617 {
4618 default_seg = &ss;
4619 if (i.disp_operands == 0)
4620 {
4621 fake_zero_displacement = 1;
40fb9820 4622 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4623 }
4624 }
4625 else if (i.base_reg->reg_num == ESP_REG_NUM)
4626 {
4627 default_seg = &ss;
4628 }
4629 i.sib.scale = i.log2_scale_factor;
4630 if (i.index_reg == 0)
4631 {
4632 /* <disp>(%esp) becomes two byte modrm with no index
4633 register. We've already stored the code for esp
4634 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4635 Any base register besides %esp will not use the
4636 extra modrm byte. */
4637 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 4638 }
4639 else
4640 {
db51cc60
L		 4641 if (i.index_reg->reg_num == RegEiz
4642 || i.index_reg->reg_num == RegRiz)
4643 i.sib.index = NO_INDEX_REGISTER;
4644 else
4645 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4646 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4647 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4648 i.rex |= REX_X;
29b0f896 4649 }
67a4f2b7
AO		 4650
4651 if (i.disp_operands
4652 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4653 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4654 i.rm.mode = 0;
4655 else
4656 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4657 }
252b5132 4658
29b0f896
AM		 4659 if (fake_zero_displacement)
4660 {
4661 /* Fakes a zero displacement assuming that i.types[op]
4662 holds the correct displacement size. */
4663 expressionS *exp;
4664
4665 assert (i.op[op].disps == 0);
4666 exp = &disp_expressions[i.disp_operands++];
4667 i.op[op].disps = exp;
4668 exp->X_op = O_constant;
4669 exp->X_add_number = 0;
4670 exp->X_add_symbol = (symbolS *) 0;
4671 exp->X_op_symbol = (symbolS *) 0;
4672 }
4673 }
252b5132 4674
29b0f896
AM		 4675 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4676 (if any) based on i.tm.extension_opcode. Again, we must be
4677 careful to make sure that segment/control/debug/test/MMX
4678 registers are coded into the i.rm.reg field. */
4679 if (i.reg_operands)
4680 {
99018f42
L		 4681 unsigned int op;
4682
85f10a01
MM		 4683 /* This has been precalculated for SSE5 instructions
4684 that have a DREX field earlier in process_drex. */
b5016f89
L		 4685 if (i.tm.opcode_modifier.drex
4686 || i.tm.opcode_modifier.drexv
4687 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4688 {
4689 op = i.drex.modrm_reg;
4690 i.rm.reg = i.op[op].regs->reg_num;
4691 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4692 i.rex |= REX_R;
4693 }
4694 else
4695 {
c0209578
L		 4696 for (op = 0; op < i.operands; op++)
4697 if (i.types[op].bitfield.reg8
4698 || i.types[op].bitfield.reg16
4699 || i.types[op].bitfield.reg32
4700 || i.types[op].bitfield.reg64
4701 || i.types[op].bitfield.regmmx
4702 || i.types[op].bitfield.regxmm
4703 || i.types[op].bitfield.sreg2
4704 || i.types[op].bitfield.sreg3
4705 || i.types[op].bitfield.control
4706 || i.types[op].bitfield.debug
4707 || i.types[op].bitfield.test)
4708 break;
4709
4710 assert (op < i.operands);
99018f42 4711
85f10a01
MM		 4712 /* If there is an extension opcode to put here, the
4713 register number must be put into the regmem field. */
c0209578
L		 4714 if (i.tm.extension_opcode != None)
4715 {
4716 i.rm.regmem = i.op[op].regs->reg_num;
4717 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4718 i.rex |= REX_B;
4719 }
4720 else
4721 {
4722 i.rm.reg = i.op[op].regs->reg_num;
4723 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4724 i.rex |= REX_R;
4725 }
85f10a01 4726 }
252b5132 4727
29b0f896
AM		 4728 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4729 must set it to 3 to indicate this is a register operand
4730 in the regmem field. */
4731 if (!i.mem_operands)
4732 i.rm.mode = 3;
4733 }
252b5132 4734
29b0f896 4735 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 4736 if (i.tm.extension_opcode != None
4737 && !(i.tm.opcode_modifier.drex
4738 || i.tm.opcode_modifier.drexv
4739 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 4740 i.rm.reg = i.tm.extension_opcode;
4741 }
4742 return default_seg;
4743}
252b5132 4744
29b0f896 4745static void
e3bb37b5 4746output_branch (void)
29b0f896
AM		 4747{
4748 char *p;
4749 int code16;
4750 int prefix;
4751 relax_substateT subtype;
4752 symbolS *sym;
4753 offsetT off;
4754
4755 code16 = 0;
4756 if (flag_code == CODE_16BIT)
4757 code16 = CODE16;
4758
4759 prefix = 0;
4760 if (i.prefix[DATA_PREFIX] != 0)
252b5132 4761 {
29b0f896
AM		 4762 prefix = 1;
4763 i.prefixes -= 1;
4764 code16 ^= CODE16;
252b5132 4765 }
29b0f896
AM		 4766 /* Pentium4 branch hints. */
4767 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4768 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 4769 {
29b0f896
AM		 4770 prefix++;
4771 i.prefixes--;
4772 }
4773 if (i.prefix[REX_PREFIX] != 0)
4774 {
4775 prefix++;
4776 i.prefixes--;
2f66722d
AM		 4777 }
4778
29b0f896
AM		 4779 if (i.prefixes != 0 && !intel_syntax)
4780 as_warn (_("skipping prefixes on this instruction"));
4781
4782 /* It's always a symbol; End frag & setup for relax.
4783 Make sure there is enough room in this frag for the largest
4784 instruction we may generate in md_convert_frag. This is 2
4785 bytes for the opcode and room for the prefix and largest
4786 displacement. */
4787 frag_grow (prefix + 2 + 4);
4788 /* Prefix and 1 opcode byte go in fr_fix. */
4789 p = frag_more (prefix + 1);
4790 if (i.prefix[DATA_PREFIX] != 0)
4791 *p++ = DATA_PREFIX_OPCODE;
4792 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4793 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4794 *p++ = i.prefix[SEG_PREFIX];
4795 if (i.prefix[REX_PREFIX] != 0)
4796 *p++ = i.prefix[REX_PREFIX];
4797 *p = i.tm.base_opcode;
4798
4799 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4800 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 4801 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 4802 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4803 else
4804 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4805 subtype |= code16;
3e73aa7c 4806
29b0f896
AM		 4807 sym = i.op[0].disps->X_add_symbol;
4808 off = i.op[0].disps->X_add_number;
3e73aa7c 4809
29b0f896
AM		 4810 if (i.op[0].disps->X_op != O_constant
4811 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 4812 {
29b0f896
AM		 4813 /* Handle complex expressions. */
4814 sym = make_expr_symbol (i.op[0].disps);
4815 off = 0;
4816 }
3e73aa7c 4817
29b0f896
AM		 4818 /* 1 possible extra opcode + 4 byte displacement go in var part.
4819 Pass reloc in fr_var. */
4820 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4821}
3e73aa7c 4822
29b0f896 4823static void
e3bb37b5 4824output_jump (void)
29b0f896
AM		 4825{
4826 char *p;
4827 int size;
3e02c1cc 4828 fixS *fixP;
29b0f896 4829
40fb9820 4830 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 4831 {
4832 /* This is a loop or jecxz type instruction. */
4833 size = 1;
4834 if (i.prefix[ADDR_PREFIX] != 0)
4835 {
4836 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4837 i.prefixes -= 1;
4838 }
4839 /* Pentium4 branch hints. */
4840 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4841 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4842 {
4843 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4844 i.prefixes--;
3e73aa7c
JH		 4845 }
4846 }
29b0f896
AM		 4847 else
4848 {
4849 int code16;
3e73aa7c 4850
29b0f896
AM		 4851 code16 = 0;
4852 if (flag_code == CODE_16BIT)
4853 code16 = CODE16;
3e73aa7c 4854
29b0f896
AM		 4855 if (i.prefix[DATA_PREFIX] != 0)
4856 {
4857 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4858 i.prefixes -= 1;
4859 code16 ^= CODE16;
4860 }
252b5132 4861
29b0f896
AM		 4862 size = 4;
4863 if (code16)
4864 size = 2;
4865 }
9fcc94b6 4866
29b0f896
AM		 4867 if (i.prefix[REX_PREFIX] != 0)
4868 {
4869 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4870 i.prefixes -= 1;
4871 }
252b5132 4872
29b0f896
AM		 4873 if (i.prefixes != 0 && !intel_syntax)
4874 as_warn (_("skipping prefixes on this instruction"));
e0890092 4875
29b0f896
AM		 4876 p = frag_more (1 + size);
4877 *p++ = i.tm.base_opcode;
e0890092 4878
3e02c1cc
AM		 4879 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4880 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4881
4882 /* All jumps handled here are signed, but don't use a signed limit
4883 check for 32 and 16 bit jumps as we want to allow wrap around at
4884 4G and 64k respectively. */
4885 if (size == 1)
4886 fixP->fx_signed = 1;
29b0f896 4887}
e0890092 4888
29b0f896 4889static void
e3bb37b5 4890output_interseg_jump (void)
29b0f896
AM		 4891{
4892 char *p;
4893 int size;
4894 int prefix;
4895 int code16;
252b5132 4896
29b0f896
AM		 4897 code16 = 0;
4898 if (flag_code == CODE_16BIT)
4899 code16 = CODE16;
a217f122 4900
29b0f896
AM		 4901 prefix = 0;
4902 if (i.prefix[DATA_PREFIX] != 0)
4903 {
4904 prefix = 1;
4905 i.prefixes -= 1;
4906 code16 ^= CODE16;
4907 }
4908 if (i.prefix[REX_PREFIX] != 0)
4909 {
4910 prefix++;
4911 i.prefixes -= 1;
4912 }
252b5132 4913
29b0f896
AM		 4914 size = 4;
4915 if (code16)
4916 size = 2;
252b5132 4917
29b0f896
AM		 4918 if (i.prefixes != 0 && !intel_syntax)
4919 as_warn (_("skipping prefixes on this instruction"));
252b5132 4920
29b0f896
AM		 4921 /* 1 opcode; 2 segment; offset */
4922 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 4923
29b0f896
AM		 4924 if (i.prefix[DATA_PREFIX] != 0)
4925 *p++ = DATA_PREFIX_OPCODE;
252b5132 4926
29b0f896
AM		 4927 if (i.prefix[REX_PREFIX] != 0)
4928 *p++ = i.prefix[REX_PREFIX];
252b5132 4929
29b0f896
AM		 4930 *p++ = i.tm.base_opcode;
4931 if (i.op[1].imms->X_op == O_constant)
4932 {
4933 offsetT n = i.op[1].imms->X_add_number;
252b5132 4934
29b0f896
AM		 4935 if (size == 2
4936 && !fits_in_unsigned_word (n)
4937 && !fits_in_signed_word (n))
4938 {
4939 as_bad (_("16-bit jump out of range"));
4940 return;
4941 }
4942 md_number_to_chars (p, n, size);
4943 }
4944 else
4945 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4946 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4947 if (i.op[0].imms->X_op != O_constant)
4948 as_bad (_("can't handle non absolute segment in `%s'"),
4949 i.tm.name);
4950 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4951}
a217f122 4952
29b0f896 4953static void
e3bb37b5 4954output_insn (void)
29b0f896 4955{
2bbd9c25
JJ		 4956 fragS *insn_start_frag;
4957 offsetT insn_start_off;
4958
29b0f896
AM		 4959 /* Tie dwarf2 debug info to the address at the start of the insn.
4960 We can't do this after the insn has been output as the current
4961 frag may have been closed off. eg. by frag_var. */
4962 dwarf2_emit_insn (0);
4963
2bbd9c25
JJ		 4964 insn_start_frag = frag_now;
4965 insn_start_off = frag_now_fix ();
4966
29b0f896 4967 /* Output jumps. */
40fb9820 4968 if (i.tm.opcode_modifier.jump)
29b0f896 4969 output_branch ();
40fb9820
L		 4970 else if (i.tm.opcode_modifier.jumpbyte
4971 || i.tm.opcode_modifier.jumpdword)
29b0f896 4972 output_jump ();
40fb9820 4973 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 4974 output_interseg_jump ();
4975 else
4976 {
4977 /* Output normal instructions here. */
4978 char *p;
4979 unsigned char *q;
331d2d0d 4980 unsigned int prefix;
4dffcebc
L		 4981
4982 switch (i.tm.opcode_length)
bc4bd9ab 4983 {
4dffcebc 4984 case 3:
331d2d0d
L		 4985 if (i.tm.base_opcode & 0xff000000)
4986 {
4987 prefix = (i.tm.base_opcode >> 24) & 0xff;
4988 goto check_prefix;
4989 }
4dffcebc
L		 4990 break;
4991 case 2:
4992 if ((i.tm.base_opcode & 0xff0000) != 0)
bc4bd9ab 4993 {
4dffcebc
L		 4994 prefix = (i.tm.base_opcode >> 16) & 0xff;
4995 if (i.tm.cpu_flags.bitfield.cpupadlock)
4996 {
4997check_prefix:
4998 if (prefix != REPE_PREFIX_OPCODE
4999 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5000 add_prefix (prefix);
5001 }
5002 else
bc4bd9ab
MK		 5003 add_prefix (prefix);
5004 }
4dffcebc
L		 5005 break;
5006 case 1:
5007 break;
5008 default:
5009 abort ();
0f10071e 5010 }
252b5132 5011
29b0f896
AM		 5012 /* The prefix bytes. */
5013 for (q = i.prefix;
5014 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
5015 q++)
5016 {
5017 if (*q)
5018 {
5019 p = frag_more (1);
5020 md_number_to_chars (p, (valueT) *q, 1);
5021 }
5022 }
252b5132 5023
29b0f896 5024 /* Now the opcode; be careful about word order here! */
4dffcebc 5025 if (i.tm.opcode_length == 1)
29b0f896
AM		 5026 {
5027 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5028 }
5029 else
5030 {
4dffcebc 5031 switch (i.tm.opcode_length)
331d2d0d 5032 {
4dffcebc 5033 case 3:
331d2d0d
L		 5034 p = frag_more (3);
5035 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5036 break;
5037 case 2:
5038 p = frag_more (2);
5039 break;
5040 default:
5041 abort ();
5042 break;
331d2d0d 5043 }
0f10071e 5044
29b0f896
AM		 5045 /* Put out high byte first: can't use md_number_to_chars! */
5046 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5047 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5048
5049 /* On SSE5, encode the OC1 bit in the DREX field if this
5050 encoding has multiple formats. */
5051 if (i.tm.opcode_modifier.drex
5052 && i.tm.opcode_modifier.drexv
5053 && DREX_OC1 (i.tm.extension_opcode))
5054 *p |= DREX_OC1_MASK;
29b0f896 5055 }
3e73aa7c 5056
29b0f896 5057 /* Now the modrm byte and sib byte (if present). */
40fb9820 5058 if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5059 {
5060 p = frag_more (1);
5061 md_number_to_chars (p,
5062 (valueT) (i.rm.regmem << 0
5063 | i.rm.reg << 3
5064 | i.rm.mode << 6),
5065 1);
5066 /* If i.rm.regmem == ESP (4)
5067 && i.rm.mode != (Register mode)
5068 && not 16 bit
5069 ==> need second modrm byte. */
5070 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5071 && i.rm.mode != 3
40fb9820 5072 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
29b0f896
AM		 5073 {
5074 p = frag_more (1);
5075 md_number_to_chars (p,
5076 (valueT) (i.sib.base << 0
5077 | i.sib.index << 3
5078 | i.sib.scale << 6),
5079 1);
5080 }
5081 }
3e73aa7c 5082
85f10a01
MM		 5083 /* Write the DREX byte if needed. */
5084 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5085 {
5086 p = frag_more (1);
5087 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5088
5089 /* Encode the OC0 bit if this encoding has multiple
5090 formats. */
5091 if ((i.tm.opcode_modifier.drex
5092 || i.tm.opcode_modifier.drexv)
5093 && DREX_OC0 (i.tm.extension_opcode))
5094 *p |= DREX_OC0_MASK;
5095 }
5096
29b0f896 5097 if (i.disp_operands)
2bbd9c25 5098 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5099
29b0f896 5100 if (i.imm_operands)
2bbd9c25 5101 output_imm (insn_start_frag, insn_start_off);
29b0f896 5102 }
252b5132 5103
29b0f896
AM		 5104#ifdef DEBUG386
5105 if (flag_debug)
5106 {
7b81dfbb 5107 pi ("" /*line*/, &i);
29b0f896
AM		 5108 }
5109#endif /* DEBUG386 */
5110}
252b5132 5111
e205caa7
L		 5112/* Return the size of the displacement operand N. */
5113
5114static int
5115disp_size (unsigned int n)
5116{
5117 int size = 4;
40fb9820
L		 5118 if (i.types[n].bitfield.disp64)
5119 size = 8;
5120 else if (i.types[n].bitfield.disp8)
5121 size = 1;
5122 else if (i.types[n].bitfield.disp16)
5123 size = 2;
e205caa7
L		 5124 return size;
5125}
5126
5127/* Return the size of the immediate operand N. */
5128
5129static int
5130imm_size (unsigned int n)
5131{
5132 int size = 4;
40fb9820
L		 5133 if (i.types[n].bitfield.imm64)
5134 size = 8;
5135 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5136 size = 1;
5137 else if (i.types[n].bitfield.imm16)
5138 size = 2;
e205caa7
L		 5139 return size;
5140}
5141
29b0f896 5142static void
64e74474 5143output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5144{
5145 char *p;
5146 unsigned int n;
252b5132 5147
29b0f896
AM		 5148 for (n = 0; n < i.operands; n++)
5149 {
40fb9820 5150 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5151 {
5152 if (i.op[n].disps->X_op == O_constant)
5153 {
e205caa7 5154 int size = disp_size (n);
29b0f896 5155 offsetT val;
252b5132 5156
29b0f896
AM		 5157 val = offset_in_range (i.op[n].disps->X_add_number,
5158 size);
5159 p = frag_more (size);
5160 md_number_to_chars (p, val, size);
5161 }
5162 else
5163 {
f86103b7 5164 enum bfd_reloc_code_real reloc_type;
e205caa7 5165 int size = disp_size (n);
40fb9820 5166 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5167 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5168
e205caa7 5169 /* We can't have 8 bit displacement here. */
40fb9820 5170 assert (!i.types[n].bitfield.disp8);
e205caa7 5171
29b0f896
AM		 5172 /* The PC relative address is computed relative
5173 to the instruction boundary, so in case immediate
5174 fields follows, we need to adjust the value. */
5175 if (pcrel && i.imm_operands)
5176 {
29b0f896 5177 unsigned int n1;
e205caa7 5178 int sz = 0;
252b5132 5179
29b0f896 5180 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5181 if (operand_type_check (i.types[n1], imm))
252b5132 5182 {
e205caa7
L		 5183 /* Only one immediate is allowed for PC
5184 relative address. */
5185 assert (sz == 0);
5186 sz = imm_size (n1);
5187 i.op[n].disps->X_add_number -= sz;
252b5132 5188 }
29b0f896 5189 /* We should find the immediate. */
e205caa7 5190 assert (sz != 0);
29b0f896 5191 }
520dc8e8 5192
29b0f896 5193 p = frag_more (size);
2bbd9c25 5194 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5195 if (GOT_symbol
2bbd9c25 5196 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5197 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5198 || reloc_type == BFD_RELOC_X86_64_32S
5199 || (reloc_type == BFD_RELOC_64
5200 && object_64bit))
d6ab8113
JB		 5201 && (i.op[n].disps->X_op == O_symbol
5202 || (i.op[n].disps->X_op == O_add
5203 && ((symbol_get_value_expression
5204 (i.op[n].disps->X_op_symbol)->X_op)
5205 == O_subtract))))
5206 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5207 {
5208 offsetT add;
5209
5210 if (insn_start_frag == frag_now)
5211 add = (p - frag_now->fr_literal) - insn_start_off;
5212 else
5213 {
5214 fragS *fr;
5215
5216 add = insn_start_frag->fr_fix - insn_start_off;
5217 for (fr = insn_start_frag->fr_next;
5218 fr && fr != frag_now; fr = fr->fr_next)
5219 add += fr->fr_fix;
5220 add += p - frag_now->fr_literal;
5221 }
5222
4fa24527 5223 if (!object_64bit)
7b81dfbb
AJ		 5224 {
5225 reloc_type = BFD_RELOC_386_GOTPC;
5226 i.op[n].imms->X_add_number += add;
5227 }
5228 else if (reloc_type == BFD_RELOC_64)
5229 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5230 else
7b81dfbb
AJ		 5231 /* Don't do the adjustment for x86-64, as there
5232 the pcrel addressing is relative to the _next_
5233 insn, and that is taken care of in other code. */
d6ab8113 5234 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5235 }
062cd5e7 5236 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5237 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5238 }
5239 }
5240 }
5241}
252b5132 5242
29b0f896 5243static void
64e74474 5244output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5245{
5246 char *p;
5247 unsigned int n;
252b5132 5248
29b0f896
AM		 5249 for (n = 0; n < i.operands; n++)
5250 {
40fb9820 5251 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5252 {
5253 if (i.op[n].imms->X_op == O_constant)
5254 {
e205caa7 5255 int size = imm_size (n);
29b0f896 5256 offsetT val;
b4cac588 5257
29b0f896
AM		 5258 val = offset_in_range (i.op[n].imms->X_add_number,
5259 size);
5260 p = frag_more (size);
5261 md_number_to_chars (p, val, size);
5262 }
5263 else
5264 {
5265 /* Not absolute_section.
5266 Need a 32-bit fixup (don't support 8bit
5267 non-absolute imms). Try to support other
5268 sizes ... */
f86103b7 5269 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5270 int size = imm_size (n);
5271 int sign;
29b0f896 5272
40fb9820 5273 if (i.types[n].bitfield.imm32s
a7d61044 5274 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5275 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5276 sign = 1;
e205caa7
L		 5277 else
5278 sign = 0;
520dc8e8 5279
29b0f896
AM		 5280 p = frag_more (size);
5281 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5282
2bbd9c25
JJ		 5283 /* This is tough to explain. We end up with this one if we
5284 * have operands that look like
5285 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5286 * obtain the absolute address of the GOT, and it is strongly
5287 * preferable from a performance point of view to avoid using
5288 * a runtime relocation for this. The actual sequence of
5289 * instructions often look something like:
5290 *
5291 * call .L66
5292 * .L66:
5293 * popl %ebx
5294 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5295 *
5296 * The call and pop essentially return the absolute address
5297 * of the label .L66 and store it in %ebx. The linker itself
5298 * will ultimately change the first operand of the addl so
5299 * that %ebx points to the GOT, but to keep things simple, the
5300 * .o file must have this operand set so that it generates not
5301 * the absolute address of .L66, but the absolute address of
5302 * itself. This allows the linker itself simply treat a GOTPC
5303 * relocation as asking for a pcrel offset to the GOT to be
5304 * added in, and the addend of the relocation is stored in the
5305 * operand field for the instruction itself.
5306 *
5307 * Our job here is to fix the operand so that it would add
5308 * the correct offset so that %ebx would point to itself. The
5309 * thing that is tricky is that .-.L66 will point to the
5310 * beginning of the instruction, so we need to further modify
5311 * the operand so that it will point to itself. There are
5312 * other cases where you have something like:
5313 *
5314 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5315 *
5316 * and here no correction would be required. Internally in
5317 * the assembler we treat operands of this form as not being
5318 * pcrel since the '.' is explicitly mentioned, and I wonder
5319 * whether it would simplify matters to do it this way. Who
5320 * knows. In earlier versions of the PIC patches, the
5321 * pcrel_adjust field was used to store the correction, but
5322 * since the expression is not pcrel, I felt it would be
5323 * confusing to do it this way. */
5324
d6ab8113 5325 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5326 || reloc_type == BFD_RELOC_X86_64_32S
5327 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5328 && GOT_symbol
5329 && GOT_symbol == i.op[n].imms->X_add_symbol
5330 && (i.op[n].imms->X_op == O_symbol
5331 || (i.op[n].imms->X_op == O_add
5332 && ((symbol_get_value_expression
5333 (i.op[n].imms->X_op_symbol)->X_op)
5334 == O_subtract))))
5335 {
2bbd9c25
JJ		 5336 offsetT add;
5337
5338 if (insn_start_frag == frag_now)
5339 add = (p - frag_now->fr_literal) - insn_start_off;
5340 else
5341 {
5342 fragS *fr;
5343
5344 add = insn_start_frag->fr_fix - insn_start_off;
5345 for (fr = insn_start_frag->fr_next;
5346 fr && fr != frag_now; fr = fr->fr_next)
5347 add += fr->fr_fix;
5348 add += p - frag_now->fr_literal;
5349 }
5350
4fa24527 5351 if (!object_64bit)
d6ab8113 5352 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5353 else if (size == 4)
d6ab8113 5354 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5355 else if (size == 8)
5356 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5357 i.op[n].imms->X_add_number += add;
29b0f896 5358 }
29b0f896
AM		 5359 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5360 i.op[n].imms, 0, reloc_type);
5361 }
5362 }
5363 }
252b5132
RH		 5364}
5365\f
d182319b
JB		 5366/* x86_cons_fix_new is called via the expression parsing code when a
5367 reloc is needed. We use this hook to get the correct .got reloc. */
5368static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5369static int cons_sign = -1;
5370
5371void
e3bb37b5 5372x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5373 expressionS *exp)
d182319b
JB		 5374{
5375 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5376
5377 got_reloc = NO_RELOC;
5378
5379#ifdef TE_PE
5380 if (exp->X_op == O_secrel)
5381 {
5382 exp->X_op = O_symbol;
5383 r = BFD_RELOC_32_SECREL;
5384 }
5385#endif
5386
5387 fix_new_exp (frag, off, len, exp, 0, r);
5388}
5389
718ddfc0
JB		 5390#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5391# define lex_got(reloc, adjust, types) NULL
5392#else
f3c180ae
AM		 5393/* Parse operands of the form
5394 <symbol>@GOTOFF+<nnn>
5395 and similar .plt or .got references.
5396
5397 If we find one, set up the correct relocation in RELOC and copy the
5398 input string, minus the `@GOTOFF' into a malloc'd buffer for
5399 parsing by the calling routine. Return this buffer, and if ADJUST
5400 is non-null set it to the length of the string we removed from the
5401 input line. Otherwise return NULL. */
5402static char *
3956db08 5403lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5404 int *adjust,
40fb9820 5405 i386_operand_type *types)
f3c180ae 5406{
7b81dfbb
AJ		 5407 /* Some of the relocations depend on the size of what field is to
5408 be relocated. But in our callers i386_immediate and i386_displacement
5409 we don't yet know the operand size (this will be set by insn
5410 matching). Hence we record the word32 relocation here,
5411 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5412 static const struct {
5413 const char *str;
4fa24527 5414 const enum bfd_reloc_code_real rel[2];
40fb9820 5415 const i386_operand_type types64;
f3c180ae 5416 } gotrel[] = {
4eed87de
AM		 5417 { "PLTOFF", { 0,
5418 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5419 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5420 { "PLT", { BFD_RELOC_386_PLT32,
5421 BFD_RELOC_X86_64_PLT32 },
40fb9820 5422 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5423 { "GOTPLT", { 0,
5424 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5425 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5426 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5427 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5428 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5429 { "GOTPCREL", { 0,
5430 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5431 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5432 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5433 BFD_RELOC_X86_64_TLSGD },
40fb9820 5434 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5435 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5436 0 },
40fb9820 5437 OPERAND_TYPE_NONE },
4eed87de
AM		 5438 { "TLSLD", { 0,
5439 BFD_RELOC_X86_64_TLSLD },
40fb9820 5440 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5441 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5442 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5443 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5444 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5445 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5446 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5447 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5448 0 },
40fb9820 5449 OPERAND_TYPE_NONE },
4eed87de
AM		 5450 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5451 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5452
5453 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5454 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5455 0 },
40fb9820 5456 OPERAND_TYPE_NONE },
4eed87de
AM		 5457 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5458 0 },
40fb9820 5459 OPERAND_TYPE_NONE },
4eed87de
AM		 5460 { "GOT", { BFD_RELOC_386_GOT32,
5461 BFD_RELOC_X86_64_GOT32 },
40fb9820 5462 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5463 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5464 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5465 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5466 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5467 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5468 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5469 };
5470 char *cp;
5471 unsigned int j;
5472
718ddfc0
JB		 5473 if (!IS_ELF)
5474 return NULL;
5475
f3c180ae 5476 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5477 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5478 return NULL;
5479
5480 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
5481 {
5482 int len;
5483
5484 len = strlen (gotrel[j].str);
28f81592 5485 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5486 {
4fa24527 5487 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5488 {
28f81592
AM		 5489 int first, second;
5490 char *tmpbuf, *past_reloc;
f3c180ae 5491
4fa24527 5492 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5493 if (adjust)
5494 *adjust = len;
f3c180ae 5495
3956db08
JB		 5496 if (types)
5497 {
5498 if (flag_code != CODE_64BIT)
40fb9820
L		 5499 {
5500 types->bitfield.imm32 = 1;
5501 types->bitfield.disp32 = 1;
5502 }
3956db08
JB		 5503 else
5504 *types = gotrel[j].types64;
5505 }
5506
f3c180ae
AM		 5507 if (GOT_symbol == NULL)
5508 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5509
28f81592 5510 /* The length of the first part of our input line. */
f3c180ae 5511 first = cp - input_line_pointer;
28f81592
AM		 5512
5513 /* The second part goes from after the reloc token until
67c11a9b 5514 (and including) an end_of_line char or comma. */
28f81592 5515 past_reloc = cp + 1 + len;
67c11a9b
AM		 5516 cp = past_reloc;
5517 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5518 ++cp;
5519 second = cp + 1 - past_reloc;
28f81592
AM		 5520
5521 /* Allocate and copy string. The trailing NUL shouldn't
5522 be necessary, but be safe. */
5523 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5524 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5525 if (second != 0 && *past_reloc != ' ')
5526 /* Replace the relocation token with ' ', so that
5527 errors like foo@GOTOFF1 will be detected. */
5528 tmpbuf[first++] = ' ';
5529 memcpy (tmpbuf + first, past_reloc, second);
5530 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5531 return tmpbuf;
5532 }
5533
4fa24527
JB		 5534 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5535 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5536 return NULL;
5537 }
5538 }
5539
5540 /* Might be a symbol version string. Don't as_bad here. */
5541 return NULL;
5542}
5543
f3c180ae 5544void
e3bb37b5 5545x86_cons (expressionS *exp, int size)
f3c180ae 5546{
4fa24527 5547 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5548 {
5549 /* Handle @GOTOFF and the like in an expression. */
5550 char *save;
5551 char *gotfree_input_line;
5552 int adjust;
5553
5554 save = input_line_pointer;
3956db08 5555 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5556 if (gotfree_input_line)
5557 input_line_pointer = gotfree_input_line;
5558
5559 expression (exp);
5560
5561 if (gotfree_input_line)
5562 {
5563 /* expression () has merrily parsed up to the end of line,
5564 or a comma - in the wrong buffer. Transfer how far
5565 input_line_pointer has moved to the right buffer. */
5566 input_line_pointer = (save
5567 + (input_line_pointer - gotfree_input_line)
5568 + adjust);
5569 free (gotfree_input_line);
3992d3b7
AM		 5570 if (exp->X_op == O_constant
5571 || exp->X_op == O_absent
5572 || exp->X_op == O_illegal
5573 || exp->X_op == O_register
5574 || exp->X_op == O_big)
5575 {
5576 char c = *input_line_pointer;
5577 *input_line_pointer = 0;
5578 as_bad (_("missing or invalid expression `%s'"), save);
5579 *input_line_pointer = c;
5580 }
f3c180ae
AM		 5581 }
5582 }
5583 else
5584 expression (exp);
5585}
5586#endif
5587
d182319b 5588static void signed_cons (int size)
6482c264 5589{
d182319b
JB		 5590 if (flag_code == CODE_64BIT)
5591 cons_sign = 1;
5592 cons (size);
5593 cons_sign = -1;
6482c264
NC		 5594}
5595
d182319b 5596#ifdef TE_PE
6482c264
NC		 5597static void
5598pe_directive_secrel (dummy)
5599 int dummy ATTRIBUTE_UNUSED;
5600{
5601 expressionS exp;
5602
5603 do
5604 {
5605 expression (&exp);
5606 if (exp.X_op == O_symbol)
5607 exp.X_op = O_secrel;
5608
5609 emit_expr (&exp, 4);
5610 }
5611 while (*input_line_pointer++ == ',');
5612
5613 input_line_pointer--;
5614 demand_empty_rest_of_line ();
5615}
6482c264
NC		 5616#endif
5617
252b5132 5618static int
70e41ade 5619i386_immediate (char *imm_start)
252b5132
RH		 5620{
5621 char *save_input_line_pointer;
f3c180ae 5622 char *gotfree_input_line;
252b5132 5623 segT exp_seg = 0;
47926f60 5624 expressionS *exp;
40fb9820
L		 5625 i386_operand_type types;
5626
c6fb90c8 5627 UINTS_SET (types, ~0);
252b5132
RH		 5628
5629 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5630 {
31b2323c
L		 5631 as_bad (_("at most %d immediate operands are allowed"),
5632 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5633 return 0;
5634 }
5635
5636 exp = &im_expressions[i.imm_operands++];
520dc8e8 5637 i.op[this_operand].imms = exp;
252b5132
RH		 5638
5639 if (is_space_char (*imm_start))
5640 ++imm_start;
5641
5642 save_input_line_pointer = input_line_pointer;
5643 input_line_pointer = imm_start;
5644
3956db08 5645 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5646 if (gotfree_input_line)
5647 input_line_pointer = gotfree_input_line;
252b5132
RH		 5648
5649 exp_seg = expression (exp);
5650
83183c0c 5651 SKIP_WHITESPACE ();
252b5132 5652 if (*input_line_pointer)
f3c180ae 5653 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5654
5655 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5656 if (gotfree_input_line)
5657 free (gotfree_input_line);
252b5132 5658
3992d3b7
AM		 5659 if (exp->X_op == O_absent
5660 || exp->X_op == O_illegal
5661 || exp->X_op == O_big
5662 || (gotfree_input_line
5663 && (exp->X_op == O_constant
5664 || exp->X_op == O_register)))
252b5132 5665 {
3992d3b7 5666 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5667 imm_start);
3992d3b7 5668 return 0;
252b5132 5669 }
3e73aa7c 5670 else if (exp->X_op == O_constant)
252b5132 5671 {
47926f60 5672 /* Size it properly later. */
40fb9820 5673 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5674 /* If BFD64, sign extend val. */
4eed87de
AM		 5675 if (!use_rela_relocations
5676 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5677 exp->X_add_number
5678 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5679 }
4c63da97 5680#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5681 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5682 && exp_seg != absolute_section
47926f60 5683 && exp_seg != text_section
24eab124
AM		 5684 && exp_seg != data_section
5685 && exp_seg != bss_section
5686 && exp_seg != undefined_section
f86103b7 5687 && !bfd_is_com_section (exp_seg))
252b5132 5688 {
d0b47220 5689 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5690 return 0;
5691 }
5692#endif
bb8f5920
L		 5693 else if (!intel_syntax && exp->X_op == O_register)
5694 {
5695 as_bad (_("illegal immediate register operand %s"), imm_start);
5696 return 0;
5697 }
252b5132
RH		 5698 else
5699 {
5700 /* This is an address. The size of the address will be
24eab124 5701 determined later, depending on destination register,
3e73aa7c 5702 suffix, or the default for the section. */
40fb9820
L		 5703 i.types[this_operand].bitfield.imm8 = 1;
5704 i.types[this_operand].bitfield.imm16 = 1;
5705 i.types[this_operand].bitfield.imm32 = 1;
5706 i.types[this_operand].bitfield.imm32s = 1;
5707 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5708 i.types[this_operand] = operand_type_and (i.types[this_operand],
5709 types);
252b5132
RH		 5710 }
5711
5712 return 1;
5713}
5714
551c1ca1 5715static char *
e3bb37b5 5716i386_scale (char *scale)
252b5132 5717{
551c1ca1
AM		 5718 offsetT val;
5719 char *save = input_line_pointer;
252b5132 5720
551c1ca1
AM		 5721 input_line_pointer = scale;
5722 val = get_absolute_expression ();
5723
5724 switch (val)
252b5132 5725 {
551c1ca1 5726 case 1:
252b5132
RH		 5727 i.log2_scale_factor = 0;
5728 break;
551c1ca1 5729 case 2:
252b5132
RH		 5730 i.log2_scale_factor = 1;
5731 break;
551c1ca1 5732 case 4:
252b5132
RH		 5733 i.log2_scale_factor = 2;
5734 break;
551c1ca1 5735 case 8:
252b5132
RH		 5736 i.log2_scale_factor = 3;
5737 break;
5738 default:
a724f0f4
JB		 5739 {
5740 char sep = *input_line_pointer;
5741
5742 *input_line_pointer = '\0';
5743 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5744 scale);
5745 *input_line_pointer = sep;
5746 input_line_pointer = save;
5747 return NULL;
5748 }
252b5132 5749 }
29b0f896 5750 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 5751 {
5752 as_warn (_("scale factor of %d without an index register"),
24eab124 5753 1 << i.log2_scale_factor);
252b5132 5754 i.log2_scale_factor = 0;
252b5132 5755 }
551c1ca1
AM		 5756 scale = input_line_pointer;
5757 input_line_pointer = save;
5758 return scale;
252b5132
RH		 5759}
5760
252b5132 5761static int
e3bb37b5 5762i386_displacement (char *disp_start, char *disp_end)
252b5132 5763{
29b0f896 5764 expressionS *exp;
252b5132
RH		 5765 segT exp_seg = 0;
5766 char *save_input_line_pointer;
f3c180ae 5767 char *gotfree_input_line;
40fb9820
L		 5768 int override;
5769 i386_operand_type bigdisp, types = anydisp;
3992d3b7 5770 int ret;
252b5132 5771
31b2323c
L		 5772 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5773 {
5774 as_bad (_("at most %d displacement operands are allowed"),
5775 MAX_MEMORY_OPERANDS);
5776 return 0;
5777 }
5778
c6fb90c8 5779 UINTS_CLEAR (bigdisp);
40fb9820
L		 5780 if ((i.types[this_operand].bitfield.jumpabsolute)
5781 || (!current_templates->start->opcode_modifier.jump
5782 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 5783 {
40fb9820 5784 bigdisp.bitfield.disp32 = 1;
e05278af 5785 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 5786 if (flag_code == CODE_64BIT)
5787 {
5788 if (!override)
5789 {
5790 bigdisp.bitfield.disp32s = 1;
5791 bigdisp.bitfield.disp64 = 1;
5792 }
5793 }
5794 else if ((flag_code == CODE_16BIT) ^ override)
5795 {
5796 bigdisp.bitfield.disp32 = 0;
5797 bigdisp.bitfield.disp16 = 1;
5798 }
e05278af
JB		 5799 }
5800 else
5801 {
5802 /* For PC-relative branches, the width of the displacement
5803 is dependent upon data size, not address size. */
e05278af 5804 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 5805 if (flag_code == CODE_64BIT)
5806 {
5807 if (override || i.suffix == WORD_MNEM_SUFFIX)
5808 bigdisp.bitfield.disp16 = 1;
5809 else
5810 {
5811 bigdisp.bitfield.disp32 = 1;
5812 bigdisp.bitfield.disp32s = 1;
5813 }
5814 }
5815 else
e05278af
JB		 5816 {
5817 if (!override)
5818 override = (i.suffix == (flag_code != CODE_16BIT
5819 ? WORD_MNEM_SUFFIX
5820 : LONG_MNEM_SUFFIX));
40fb9820
L		 5821 bigdisp.bitfield.disp32 = 1;
5822 if ((flag_code == CODE_16BIT) ^ override)
5823 {
5824 bigdisp.bitfield.disp32 = 0;
5825 bigdisp.bitfield.disp16 = 1;
5826 }
e05278af 5827 }
e05278af 5828 }
c6fb90c8
L		 5829 i.types[this_operand] = operand_type_or (i.types[this_operand],
5830 bigdisp);
252b5132
RH		 5831
5832 exp = &disp_expressions[i.disp_operands];
520dc8e8 5833 i.op[this_operand].disps = exp;
252b5132
RH		 5834 i.disp_operands++;
5835 save_input_line_pointer = input_line_pointer;
5836 input_line_pointer = disp_start;
5837 END_STRING_AND_SAVE (disp_end);
5838
5839#ifndef GCC_ASM_O_HACK
5840#define GCC_ASM_O_HACK 0
5841#endif
5842#if GCC_ASM_O_HACK
5843 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 5844 if (i.types[this_operand].bitfield.baseIndex
24eab124 5845 && displacement_string_end[-1] == '+')
252b5132
RH		 5846 {
5847 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 5848 constraint within gcc asm statements.
5849 For instance:
5850
5851 #define _set_tssldt_desc(n,addr,limit,type) \
5852 __asm__ __volatile__ ( \
5853 "movw %w2,%0\n\t" \
5854 "movw %w1,2+%0\n\t" \
5855 "rorl $16,%1\n\t" \
5856 "movb %b1,4+%0\n\t" \
5857 "movb %4,5+%0\n\t" \
5858 "movb $0,6+%0\n\t" \
5859 "movb %h1,7+%0\n\t" \
5860 "rorl $16,%1" \
5861 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5862
5863 This works great except that the output assembler ends
5864 up looking a bit weird if it turns out that there is
5865 no offset. You end up producing code that looks like:
5866
5867 #APP
5868 movw $235,(%eax)
5869 movw %dx,2+(%eax)
5870 rorl $16,%edx
5871 movb %dl,4+(%eax)
5872 movb $137,5+(%eax)
5873 movb $0,6+(%eax)
5874 movb %dh,7+(%eax)
5875 rorl $16,%edx
5876 #NO_APP
5877
47926f60 5878 So here we provide the missing zero. */
24eab124
AM		 5879
5880 *displacement_string_end = '0';
252b5132
RH		 5881 }
5882#endif
3956db08 5883 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5884 if (gotfree_input_line)
5885 input_line_pointer = gotfree_input_line;
252b5132 5886
24eab124 5887 exp_seg = expression (exp);
252b5132 5888
636c26b0
AM		 5889 SKIP_WHITESPACE ();
5890 if (*input_line_pointer)
5891 as_bad (_("junk `%s' after expression"), input_line_pointer);
5892#if GCC_ASM_O_HACK
5893 RESTORE_END_STRING (disp_end + 1);
5894#endif
636c26b0 5895 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 5896 if (gotfree_input_line)
5897 free (gotfree_input_line);
3992d3b7 5898 ret = 1;
636c26b0 5899
24eab124
AM		 5900 /* We do this to make sure that the section symbol is in
5901 the symbol table. We will ultimately change the relocation
47926f60 5902 to be relative to the beginning of the section. */
1ae12ab7 5903 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 5904 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5905 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 5906 {
636c26b0 5907 if (exp->X_op != O_symbol)
3992d3b7 5908 goto inv_disp;
636c26b0 5909
e5cb08ac 5910 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 5911 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5912 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 5913 exp->X_op = O_subtract;
5914 exp->X_op_symbol = GOT_symbol;
1ae12ab7 5915 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 5916 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 5917 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5918 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 5919 else
29b0f896 5920 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 5921 }
252b5132 5922
3992d3b7
AM		 5923 else if (exp->X_op == O_absent
5924 || exp->X_op == O_illegal
5925 || exp->X_op == O_big
5926 || (gotfree_input_line
5927 && (exp->X_op == O_constant
5928 || exp->X_op == O_register)))
2daf4fd8 5929 {
3992d3b7
AM		 5930 inv_disp:
5931 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 5932 disp_start);
3992d3b7 5933 ret = 0;
2daf4fd8
AM		 5934 }
5935
4c63da97 5936#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 5937 else if (exp->X_op != O_constant
5938 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5939 && exp_seg != absolute_section
5940 && exp_seg != text_section
5941 && exp_seg != data_section
5942 && exp_seg != bss_section
5943 && exp_seg != undefined_section
5944 && !bfd_is_com_section (exp_seg))
24eab124 5945 {
d0b47220 5946 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 5947 ret = 0;
24eab124 5948 }
252b5132 5949#endif
3956db08 5950
3992d3b7
AM		 5951 RESTORE_END_STRING (disp_end);
5952
40fb9820
L		 5953 /* Check if this is a displacement only operand. */
5954 bigdisp = i.types[this_operand];
5955 bigdisp.bitfield.disp8 = 0;
5956 bigdisp.bitfield.disp16 = 0;
5957 bigdisp.bitfield.disp32 = 0;
5958 bigdisp.bitfield.disp32s = 0;
5959 bigdisp.bitfield.disp64 = 0;
c6fb90c8
L		 5960 if (UINTS_ALL_ZERO (bigdisp))
5961 i.types[this_operand] = operand_type_and (i.types[this_operand],
5962 types);
3956db08 5963
3992d3b7 5964 return ret;
252b5132
RH		 5965}
5966
eecb386c 5967/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 5968 Return 1 on success, 0 on a failure. */
5969
252b5132 5970static int
e3bb37b5 5971i386_index_check (const char *operand_string)
252b5132 5972{
3e73aa7c 5973 int ok;
24eab124 5974#if INFER_ADDR_PREFIX
eecb386c
AM		 5975 int fudged = 0;
5976
24eab124
AM		 5977 tryprefix:
5978#endif
3e73aa7c 5979 ok = 1;
75178d9d 5980 if (flag_code == CODE_64BIT)
64e74474 5981 {
64e74474 5982 if ((i.base_reg
40fb9820
L		 5983 && ((i.prefix[ADDR_PREFIX] == 0
5984 && !i.base_reg->reg_type.bitfield.reg64)
5985 || (i.prefix[ADDR_PREFIX]
5986 && !i.base_reg->reg_type.bitfield.reg32))
5987 && (i.index_reg
9a04903e
JB		 5988 || i.base_reg->reg_num !=
5989 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 5990 || (i.index_reg
40fb9820
L		 5991 && (!i.index_reg->reg_type.bitfield.baseindex
5992 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 5993 && i.index_reg->reg_num != RegRiz
5994 && !i.index_reg->reg_type.bitfield.reg64
5995 )
40fb9820 5996 || (i.prefix[ADDR_PREFIX]
db51cc60 5997 && i.index_reg->reg_num != RegEiz
40fb9820 5998 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 5999 ok = 0;
3e73aa7c
JH		 6000 }
6001 else
6002 {
6003 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6004 {
6005 /* 16bit checks. */
6006 if ((i.base_reg
40fb9820
L		 6007 && (!i.base_reg->reg_type.bitfield.reg16
6008 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6009 || (i.index_reg
40fb9820
L		 6010 && (!i.index_reg->reg_type.bitfield.reg16
6011 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6012 || !(i.base_reg
6013 && i.base_reg->reg_num < 6
6014 && i.index_reg->reg_num >= 6
6015 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6016 ok = 0;
6017 }
6018 else
e5cb08ac 6019 {
3e73aa7c
JH		 6020 /* 32bit checks. */
6021 if ((i.base_reg
40fb9820 6022 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6023 || (i.index_reg
db51cc60
L		 6024 && ((!i.index_reg->reg_type.bitfield.reg32
6025 && i.index_reg->reg_num != RegEiz)
40fb9820 6026 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6027 ok = 0;
3e73aa7c
JH		 6028 }
6029 }
6030 if (!ok)
24eab124
AM		 6031 {
6032#if INFER_ADDR_PREFIX
20f0a1fc 6033 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6034 {
6035 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6036 i.prefixes += 1;
b23bac36
AM		 6037 /* Change the size of any displacement too. At most one of
6038 Disp16 or Disp32 is set.
6039 FIXME. There doesn't seem to be any real need for separate
6040 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6041 Removing them would probably clean up the code quite a lot. */
4eed87de 6042 if (flag_code != CODE_64BIT
40fb9820
L		 6043 && (i.types[this_operand].bitfield.disp16
6044 || i.types[this_operand].bitfield.disp32))
6045 i.types[this_operand]
c6fb90c8 6046 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6047 fudged = 1;
24eab124
AM		 6048 goto tryprefix;
6049 }
eecb386c
AM		 6050 if (fudged)
6051 as_bad (_("`%s' is not a valid base/index expression"),
6052 operand_string);
6053 else
c388dee8 6054#endif
eecb386c
AM		 6055 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6056 operand_string,
3e73aa7c 6057 flag_code_names[flag_code]);
24eab124 6058 }
20f0a1fc 6059 return ok;
24eab124 6060}
252b5132 6061
252b5132 6062/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6063 on error. */
252b5132 6064
252b5132 6065static int
e3bb37b5 6066i386_operand (char *operand_string)
252b5132 6067{
af6bdddf
AM		 6068 const reg_entry *r;
6069 char *end_op;
24eab124 6070 char *op_string = operand_string;
252b5132 6071
24eab124 6072 if (is_space_char (*op_string))
252b5132
RH		 6073 ++op_string;
6074
24eab124 6075 /* We check for an absolute prefix (differentiating,
47926f60 6076 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6077 if (*op_string == ABSOLUTE_PREFIX)
6078 {
6079 ++op_string;
6080 if (is_space_char (*op_string))
6081 ++op_string;
40fb9820 6082 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6083 }
252b5132 6084
47926f60 6085 /* Check if operand is a register. */
4d1bb795 6086 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6087 {
40fb9820
L		 6088 i386_operand_type temp;
6089
24eab124
AM		 6090 /* Check for a segment override by searching for ':' after a
6091 segment register. */
6092 op_string = end_op;
6093 if (is_space_char (*op_string))
6094 ++op_string;
40fb9820
L		 6095 if (*op_string == ':'
6096 && (r->reg_type.bitfield.sreg2
6097 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6098 {
6099 switch (r->reg_num)
6100 {
6101 case 0:
6102 i.seg[i.mem_operands] = &es;
6103 break;
6104 case 1:
6105 i.seg[i.mem_operands] = &cs;
6106 break;
6107 case 2:
6108 i.seg[i.mem_operands] = &ss;
6109 break;
6110 case 3:
6111 i.seg[i.mem_operands] = &ds;
6112 break;
6113 case 4:
6114 i.seg[i.mem_operands] = &fs;
6115 break;
6116 case 5:
6117 i.seg[i.mem_operands] = &gs;
6118 break;
6119 }
252b5132 6120
24eab124 6121 /* Skip the ':' and whitespace. */
252b5132
RH		 6122 ++op_string;
6123 if (is_space_char (*op_string))
24eab124 6124 ++op_string;
252b5132 6125
24eab124
AM		 6126 if (!is_digit_char (*op_string)
6127 && !is_identifier_char (*op_string)
6128 && *op_string != '('
6129 && *op_string != ABSOLUTE_PREFIX)
6130 {
6131 as_bad (_("bad memory operand `%s'"), op_string);
6132 return 0;
6133 }
47926f60 6134 /* Handle case of %es:*foo. */
24eab124
AM		 6135 if (*op_string == ABSOLUTE_PREFIX)
6136 {
6137 ++op_string;
6138 if (is_space_char (*op_string))
6139 ++op_string;
40fb9820 6140 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6141 }
6142 goto do_memory_reference;
6143 }
6144 if (*op_string)
6145 {
d0b47220 6146 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6147 return 0;
6148 }
40fb9820
L		 6149 temp = r->reg_type;
6150 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6151 i.types[this_operand] = operand_type_or (i.types[this_operand],
6152 temp);
520dc8e8 6153 i.op[this_operand].regs = r;
24eab124
AM		 6154 i.reg_operands++;
6155 }
af6bdddf
AM		 6156 else if (*op_string == REGISTER_PREFIX)
6157 {
6158 as_bad (_("bad register name `%s'"), op_string);
6159 return 0;
6160 }
24eab124 6161 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6162 {
24eab124 6163 ++op_string;
40fb9820 6164 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6165 {
d0b47220 6166 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6167 return 0;
6168 }
6169 if (!i386_immediate (op_string))
6170 return 0;
6171 }
6172 else if (is_digit_char (*op_string)
6173 || is_identifier_char (*op_string)
e5cb08ac 6174 || *op_string == '(')
24eab124 6175 {
47926f60 6176 /* This is a memory reference of some sort. */
af6bdddf 6177 char *base_string;
252b5132 6178
47926f60 6179 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6180 char *displacement_string_start;
6181 char *displacement_string_end;
252b5132 6182
24eab124 6183 do_memory_reference:
24eab124 6184 if ((i.mem_operands == 1
40fb9820 6185 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6186 || i.mem_operands == 2)
6187 {
6188 as_bad (_("too many memory references for `%s'"),
6189 current_templates->start->name);
6190 return 0;
6191 }
252b5132 6192
24eab124
AM		 6193 /* Check for base index form. We detect the base index form by
6194 looking for an ')' at the end of the operand, searching
6195 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6196 after the '('. */
af6bdddf 6197 base_string = op_string + strlen (op_string);
c3332e24 6198
af6bdddf
AM		 6199 --base_string;
6200 if (is_space_char (*base_string))
6201 --base_string;
252b5132 6202
47926f60 6203 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6204 displacement_string_start = op_string;
6205 displacement_string_end = base_string + 1;
252b5132 6206
24eab124
AM		 6207 if (*base_string == ')')
6208 {
af6bdddf 6209 char *temp_string;
24eab124
AM		 6210 unsigned int parens_balanced = 1;
6211 /* We've already checked that the number of left & right ()'s are
47926f60 6212 equal, so this loop will not be infinite. */
24eab124
AM		 6213 do
6214 {
6215 base_string--;
6216 if (*base_string == ')')
6217 parens_balanced++;
6218 if (*base_string == '(')
6219 parens_balanced--;
6220 }
6221 while (parens_balanced);
c3332e24 6222
af6bdddf 6223 temp_string = base_string;
c3332e24 6224
24eab124 6225 /* Skip past '(' and whitespace. */
252b5132
RH		 6226 ++base_string;
6227 if (is_space_char (*base_string))
24eab124 6228 ++base_string;
252b5132 6229
af6bdddf 6230 if (*base_string == ','
4eed87de
AM		 6231 || ((i.base_reg = parse_register (base_string, &end_op))
6232 != NULL))
252b5132 6233 {
af6bdddf 6234 displacement_string_end = temp_string;
252b5132 6235
40fb9820 6236 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6237
af6bdddf 6238 if (i.base_reg)
24eab124 6239 {
24eab124
AM		 6240 base_string = end_op;
6241 if (is_space_char (*base_string))
6242 ++base_string;
af6bdddf
AM		 6243 }
6244
6245 /* There may be an index reg or scale factor here. */
6246 if (*base_string == ',')
6247 {
6248 ++base_string;
6249 if (is_space_char (*base_string))
6250 ++base_string;
6251
4eed87de
AM		 6252 if ((i.index_reg = parse_register (base_string, &end_op))
6253 != NULL)
24eab124 6254 {
af6bdddf 6255 base_string = end_op;
24eab124
AM		 6256 if (is_space_char (*base_string))
6257 ++base_string;
af6bdddf
AM		 6258 if (*base_string == ',')
6259 {
6260 ++base_string;
6261 if (is_space_char (*base_string))
6262 ++base_string;
6263 }
e5cb08ac 6264 else if (*base_string != ')')
af6bdddf 6265 {
4eed87de
AM		 6266 as_bad (_("expecting `,' or `)' "
6267 "after index register in `%s'"),
af6bdddf
AM		 6268 operand_string);
6269 return 0;
6270 }
24eab124 6271 }
af6bdddf 6272 else if (*base_string == REGISTER_PREFIX)
24eab124 6273 {
af6bdddf 6274 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6275 return 0;
6276 }
252b5132 6277
47926f60 6278 /* Check for scale factor. */
551c1ca1 6279 if (*base_string != ')')
af6bdddf 6280 {
551c1ca1
AM		 6281 char *end_scale = i386_scale (base_string);
6282
6283 if (!end_scale)
af6bdddf 6284 return 0;
24eab124 6285
551c1ca1 6286 base_string = end_scale;
af6bdddf
AM		 6287 if (is_space_char (*base_string))
6288 ++base_string;
6289 if (*base_string != ')')
6290 {
4eed87de
AM		 6291 as_bad (_("expecting `)' "
6292 "after scale factor in `%s'"),
af6bdddf
AM		 6293 operand_string);
6294 return 0;
6295 }
6296 }
6297 else if (!i.index_reg)
24eab124 6298 {
4eed87de
AM		 6299 as_bad (_("expecting index register or scale factor "
6300 "after `,'; got '%c'"),
af6bdddf 6301 *base_string);
24eab124
AM		 6302 return 0;
6303 }
6304 }
af6bdddf 6305 else if (*base_string != ')')
24eab124 6306 {
4eed87de
AM		 6307 as_bad (_("expecting `,' or `)' "
6308 "after base register in `%s'"),
af6bdddf 6309 operand_string);
24eab124
AM		 6310 return 0;
6311 }
c3332e24 6312 }
af6bdddf 6313 else if (*base_string == REGISTER_PREFIX)
c3332e24 6314 {
af6bdddf 6315 as_bad (_("bad register name `%s'"), base_string);
24eab124 6316 return 0;
c3332e24 6317 }
24eab124
AM		 6318 }
6319
6320 /* If there's an expression beginning the operand, parse it,
6321 assuming displacement_string_start and
6322 displacement_string_end are meaningful. */
6323 if (displacement_string_start != displacement_string_end)
6324 {
6325 if (!i386_displacement (displacement_string_start,
6326 displacement_string_end))
6327 return 0;
6328 }
6329
6330 /* Special case for (%dx) while doing input/output op. */
6331 if (i.base_reg
c6fb90c8 6332 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
24eab124
AM		 6333 && i.index_reg == 0
6334 && i.log2_scale_factor == 0
6335 && i.seg[i.mem_operands] == 0
40fb9820 6336 && !operand_type_check (i.types[this_operand], disp))
24eab124 6337 {
c6fb90c8 6338 UINTS_CLEAR (i.types[this_operand]);
40fb9820 6339 i.types[this_operand].bitfield.inoutportreg = 1;
24eab124
AM		 6340 return 1;
6341 }
6342
eecb386c
AM		 6343 if (i386_index_check (operand_string) == 0)
6344 return 0;
24eab124
AM		 6345 i.mem_operands++;
6346 }
6347 else
ce8a8b2f
AM		 6348 {
6349 /* It's not a memory operand; argh! */
24eab124
AM		 6350 as_bad (_("invalid char %s beginning operand %d `%s'"),
6351 output_invalid (*op_string),
6352 this_operand + 1,
6353 op_string);
6354 return 0;
6355 }
47926f60 6356 return 1; /* Normal return. */
252b5132
RH		 6357}
6358\f
ee7fcc42
AM		 6359/* md_estimate_size_before_relax()
6360
6361 Called just before relax() for rs_machine_dependent frags. The x86
6362 assembler uses these frags to handle variable size jump
6363 instructions.
6364
6365 Any symbol that is now undefined will not become defined.
6366 Return the correct fr_subtype in the frag.
6367 Return the initial "guess for variable size of frag" to caller.
6368 The guess is actually the growth beyond the fixed part. Whatever
6369 we do to grow the fixed or variable part contributes to our
6370 returned value. */
6371
252b5132
RH		 6372int
6373md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6374 fragS *fragP;
6375 segT segment;
252b5132 6376{
252b5132 6377 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6378 check for un-relaxable symbols. On an ELF system, we can't relax
6379 an externally visible symbol, because it may be overridden by a
6380 shared library. */
6381 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6382#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6383 || (IS_ELF
31312f95
AM		 6384 && (S_IS_EXTERNAL (fragP->fr_symbol)
6385 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 6386#endif
6387 )
252b5132 6388 {
b98ef147
AM		 6389 /* Symbol is undefined in this segment, or we need to keep a
6390 reloc so that weak symbols can be overridden. */
6391 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6392 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6393 unsigned char *opcode;
6394 int old_fr_fix;
f6af82bd 6395
ee7fcc42
AM		 6396 if (fragP->fr_var != NO_RELOC)
6397 reloc_type = fragP->fr_var;
b98ef147 6398 else if (size == 2)
f6af82bd
AM		 6399 reloc_type = BFD_RELOC_16_PCREL;
6400 else
6401 reloc_type = BFD_RELOC_32_PCREL;
252b5132 6402
ee7fcc42
AM		 6403 old_fr_fix = fragP->fr_fix;
6404 opcode = (unsigned char *) fragP->fr_opcode;
6405
fddf5b5b 6406 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 6407 {
fddf5b5b
AM		 6408 case UNCOND_JUMP:
6409 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 6410 opcode[0] = 0xe9;
252b5132 6411 fragP->fr_fix += size;
062cd5e7
AS		 6412 fix_new (fragP, old_fr_fix, size,
6413 fragP->fr_symbol,
6414 fragP->fr_offset, 1,
6415 reloc_type);
252b5132
RH		 6416 break;
6417
fddf5b5b 6418 case COND_JUMP86:
412167cb
AM		 6419 if (size == 2
6420 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 6421 {
6422 /* Negate the condition, and branch past an
6423 unconditional jump. */
6424 opcode[0] ^= 1;
6425 opcode[1] = 3;
6426 /* Insert an unconditional jump. */
6427 opcode[2] = 0xe9;
6428 /* We added two extra opcode bytes, and have a two byte
6429 offset. */
6430 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 6431 fix_new (fragP, old_fr_fix + 2, 2,
6432 fragP->fr_symbol,
6433 fragP->fr_offset, 1,
6434 reloc_type);
fddf5b5b
AM		 6435 break;
6436 }
6437 /* Fall through. */
6438
6439 case COND_JUMP:
412167cb
AM		 6440 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6441 {
3e02c1cc
AM		 6442 fixS *fixP;
6443
412167cb 6444 fragP->fr_fix += 1;
3e02c1cc
AM		 6445 fixP = fix_new (fragP, old_fr_fix, 1,
6446 fragP->fr_symbol,
6447 fragP->fr_offset, 1,
6448 BFD_RELOC_8_PCREL);
6449 fixP->fx_signed = 1;
412167cb
AM		 6450 break;
6451 }
93c2a809 6452
24eab124 6453 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6454 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6455 opcode[1] = opcode[0] + 0x10;
f6af82bd 6456 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6457 /* We've added an opcode byte. */
6458 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6459 fix_new (fragP, old_fr_fix + 1, size,
6460 fragP->fr_symbol,
6461 fragP->fr_offset, 1,
6462 reloc_type);
252b5132 6463 break;
fddf5b5b
AM		 6464
6465 default:
6466 BAD_CASE (fragP->fr_subtype);
6467 break;
252b5132
RH		 6468 }
6469 frag_wane (fragP);
ee7fcc42 6470 return fragP->fr_fix - old_fr_fix;
252b5132 6471 }
93c2a809 6472
93c2a809
AM		 6473 /* Guess size depending on current relax state. Initially the relax
6474 state will correspond to a short jump and we return 1, because
6475 the variable part of the frag (the branch offset) is one byte
6476 long. However, we can relax a section more than once and in that
6477 case we must either set fr_subtype back to the unrelaxed state,
6478 or return the value for the appropriate branch. */
6479 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6480}
6481
47926f60
KH		 6482/* Called after relax() is finished.
6483
6484 In: Address of frag.
6485 fr_type == rs_machine_dependent.
6486 fr_subtype is what the address relaxed to.
6487
6488 Out: Any fixSs and constants are set up.
6489 Caller will turn frag into a ".space 0". */
6490
252b5132
RH		 6491void
6492md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6493 bfd *abfd ATTRIBUTE_UNUSED;
6494 segT sec ATTRIBUTE_UNUSED;
29b0f896 6495 fragS *fragP;
252b5132 6496{
29b0f896 6497 unsigned char *opcode;
252b5132 6498 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6499 offsetT target_address;
6500 offsetT opcode_address;
252b5132 6501 unsigned int extension = 0;
847f7ad4 6502 offsetT displacement_from_opcode_start;
252b5132
RH		 6503
6504 opcode = (unsigned char *) fragP->fr_opcode;
6505
47926f60 6506 /* Address we want to reach in file space. */
252b5132 6507 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6508
47926f60 6509 /* Address opcode resides at in file space. */
252b5132
RH		 6510 opcode_address = fragP->fr_address + fragP->fr_fix;
6511
47926f60 6512 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6513 displacement_from_opcode_start = target_address - opcode_address;
6514
fddf5b5b 6515 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6516 {
47926f60
KH		 6517 /* Don't have to change opcode. */
6518 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6519 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6520 }
6521 else
6522 {
6523 if (no_cond_jump_promotion
6524 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6525 as_warn_where (fragP->fr_file, fragP->fr_line,
6526 _("long jump required"));
252b5132 6527
fddf5b5b
AM		 6528 switch (fragP->fr_subtype)
6529 {
6530 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6531 extension = 4; /* 1 opcode + 4 displacement */
6532 opcode[0] = 0xe9;
6533 where_to_put_displacement = &opcode[1];
6534 break;
252b5132 6535
fddf5b5b
AM		 6536 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6537 extension = 2; /* 1 opcode + 2 displacement */
6538 opcode[0] = 0xe9;
6539 where_to_put_displacement = &opcode[1];
6540 break;
252b5132 6541
fddf5b5b
AM		 6542 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6543 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6544 extension = 5; /* 2 opcode + 4 displacement */
6545 opcode[1] = opcode[0] + 0x10;
6546 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6547 where_to_put_displacement = &opcode[2];
6548 break;
252b5132 6549
fddf5b5b
AM		 6550 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6551 extension = 3; /* 2 opcode + 2 displacement */
6552 opcode[1] = opcode[0] + 0x10;
6553 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6554 where_to_put_displacement = &opcode[2];
6555 break;
252b5132 6556
fddf5b5b
AM		 6557 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6558 extension = 4;
6559 opcode[0] ^= 1;
6560 opcode[1] = 3;
6561 opcode[2] = 0xe9;
6562 where_to_put_displacement = &opcode[3];
6563 break;
6564
6565 default:
6566 BAD_CASE (fragP->fr_subtype);
6567 break;
6568 }
252b5132 6569 }
fddf5b5b 6570
7b81dfbb
AJ		 6571 /* If size if less then four we are sure that the operand fits,
6572 but if it's 4, then it could be that the displacement is larger
6573 then -/+ 2GB. */
6574 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6575 && object_64bit
6576 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6577 + ((addressT) 1 << 31))
6578 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6579 {
6580 as_bad_where (fragP->fr_file, fragP->fr_line,
6581 _("jump target out of range"));
6582 /* Make us emit 0. */
6583 displacement_from_opcode_start = extension;
6584 }
47926f60 6585 /* Now put displacement after opcode. */
252b5132
RH		 6586 md_number_to_chars ((char *) where_to_put_displacement,
6587 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6588 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6589 fragP->fr_fix += extension;
6590}
6591\f
47926f60
KH		 6592/* Size of byte displacement jmp. */
6593int md_short_jump_size = 2;
6594
6595/* Size of dword displacement jmp. */
6596int md_long_jump_size = 5;
252b5132 6597
252b5132
RH		 6598void
6599md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
6600 char *ptr;
6601 addressT from_addr, to_addr;
ab9da554
ILT		 6602 fragS *frag ATTRIBUTE_UNUSED;
6603 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6604{
847f7ad4 6605 offsetT offset;
252b5132
RH		 6606
6607 offset = to_addr - (from_addr + 2);
47926f60
KH		 6608 /* Opcode for byte-disp jump. */
6609 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 6610 md_number_to_chars (ptr + 1, (valueT) offset, 1);
6611}
6612
6613void
6614md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
6615 char *ptr;
6616 addressT from_addr, to_addr;
a38cf1db
AM		 6617 fragS *frag ATTRIBUTE_UNUSED;
6618 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6619{
847f7ad4 6620 offsetT offset;
252b5132 6621
a38cf1db
AM		 6622 offset = to_addr - (from_addr + 5);
6623 md_number_to_chars (ptr, (valueT) 0xe9, 1);
6624 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 6625}
6626\f
6627/* Apply a fixup (fixS) to segment data, once it has been determined
6628 by our caller that we have all the info we need to fix it up.
6629
6630 On the 386, immediates, displacements, and data pointers are all in
6631 the same (little-endian) format, so we don't need to care about which
6632 we are handling. */
6633
94f592af 6634void
55cf6793 6635md_apply_fix (fixP, valP, seg)
47926f60
KH		 6636 /* The fix we're to put in. */
6637 fixS *fixP;
47926f60 6638 /* Pointer to the value of the bits. */
c6682705 6639 valueT *valP;
47926f60
KH		 6640 /* Segment fix is from. */
6641 segT seg ATTRIBUTE_UNUSED;
252b5132 6642{
94f592af 6643 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6644 valueT value = *valP;
252b5132 6645
f86103b7 6646#if !defined (TE_Mach)
93382f6d
AM		 6647 if (fixP->fx_pcrel)
6648 {
6649 switch (fixP->fx_r_type)
6650 {
5865bb77
ILT		 6651 default:
6652 break;
6653
d6ab8113
JB		 6654 case BFD_RELOC_64:
6655 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6656 break;
93382f6d 6657 case BFD_RELOC_32:
ae8887b5 6658 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6659 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6660 break;
6661 case BFD_RELOC_16:
6662 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6663 break;
6664 case BFD_RELOC_8:
6665 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6666 break;
6667 }
6668 }
252b5132 6669
a161fe53 6670 if (fixP->fx_addsy != NULL
31312f95 6671 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6672 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6673 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6674 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6675 && !use_rela_relocations)
252b5132 6676 {
31312f95
AM		 6677 /* This is a hack. There should be a better way to handle this.
6678 This covers for the fact that bfd_install_relocation will
6679 subtract the current location (for partial_inplace, PC relative
6680 relocations); see more below. */
252b5132 6681#ifndef OBJ_AOUT
718ddfc0 6682 if (IS_ELF
252b5132
RH		 6683#ifdef TE_PE
6684 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6685#endif
6686 )
6687 value += fixP->fx_where + fixP->fx_frag->fr_address;
6688#endif
6689#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6690 if (IS_ELF)
252b5132 6691 {
6539b54b 6692 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6693
6539b54b 6694 if ((sym_seg == seg
2f66722d 6695 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6696 && sym_seg != absolute_section))
ae6063d4 6697 && !generic_force_reloc (fixP))
2f66722d
AM		 6698 {
6699 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6700 bfd_install_relocation subtracts them out again. I think
6701 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6702 it. FIXME. */
6703 value += fixP->fx_where + fixP->fx_frag->fr_address;
6704 }
252b5132
RH		 6705 }
6706#endif
6707#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6708 /* For some reason, the PE format does not store a
6709 section address offset for a PC relative symbol. */
6710 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6711 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6712 value += md_pcrel_from (fixP);
6713#endif
6714 }
6715
6716 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6717 and we must not disappoint it. */
252b5132 6718#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6719 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6720 switch (fixP->fx_r_type)
6721 {
6722 case BFD_RELOC_386_PLT32:
3e73aa7c 6723 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6724 /* Make the jump instruction point to the address of the operand. At
6725 runtime we merely add the offset to the actual PLT entry. */
6726 value = -4;
6727 break;
31312f95 6728
13ae64f3
JJ		 6729 case BFD_RELOC_386_TLS_GD:
6730 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6731 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6732 case BFD_RELOC_386_TLS_IE:
6733 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6734 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6735 case BFD_RELOC_X86_64_TLSGD:
6736 case BFD_RELOC_X86_64_TLSLD:
6737 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6738 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6739 value = 0; /* Fully resolved at runtime. No addend. */
6740 /* Fallthrough */
6741 case BFD_RELOC_386_TLS_LE:
6742 case BFD_RELOC_386_TLS_LDO_32:
6743 case BFD_RELOC_386_TLS_LE_32:
6744 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6745 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6746 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6747 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6748 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6749 break;
6750
67a4f2b7
AO		 6751 case BFD_RELOC_386_TLS_DESC_CALL:
6752 case BFD_RELOC_X86_64_TLSDESC_CALL:
6753 value = 0; /* Fully resolved at runtime. No addend. */
6754 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6755 fixP->fx_done = 0;
6756 return;
6757
00f7efb6
JJ		 6758 case BFD_RELOC_386_GOT32:
6759 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6760 value = 0; /* Fully resolved at runtime. No addend. */
6761 break;
47926f60
KH		 6762
6763 case BFD_RELOC_VTABLE_INHERIT:
6764 case BFD_RELOC_VTABLE_ENTRY:
6765 fixP->fx_done = 0;
94f592af 6766 return;
47926f60
KH		 6767
6768 default:
6769 break;
6770 }
6771#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 6772 *valP = value;
f86103b7 6773#endif /* !defined (TE_Mach) */
3e73aa7c 6774
3e73aa7c 6775 /* Are we finished with this relocation now? */
c6682705 6776 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 6777 fixP->fx_done = 1;
6778 else if (use_rela_relocations)
6779 {
6780 fixP->fx_no_overflow = 1;
062cd5e7
AS		 6781 /* Remember value for tc_gen_reloc. */
6782 fixP->fx_addnumber = value;
3e73aa7c
JH		 6783 value = 0;
6784 }
f86103b7 6785
94f592af 6786 md_number_to_chars (p, value, fixP->fx_size);
252b5132 6787}
252b5132 6788\f
252b5132
RH		 6789#define MAX_LITTLENUMS 6
6790
47926f60
KH		 6791/* Turn the string pointed to by litP into a floating point constant
6792 of type TYPE, and emit the appropriate bytes. The number of
6793 LITTLENUMS emitted is stored in *SIZEP. An error message is
6794 returned, or NULL on OK. */
6795
252b5132
RH		 6796char *
6797md_atof (type, litP, sizeP)
2ab9b79e 6798 int type;
252b5132
RH		 6799 char *litP;
6800 int *sizeP;
6801{
6802 int prec;
6803 LITTLENUM_TYPE words[MAX_LITTLENUMS];
6804 LITTLENUM_TYPE *wordP;
6805 char *t;
6806
6807 switch (type)
6808 {
6809 case 'f':
6810 case 'F':
6811 prec = 2;
6812 break;
6813
6814 case 'd':
6815 case 'D':
6816 prec = 4;
6817 break;
6818
6819 case 'x':
6820 case 'X':
6821 prec = 5;
6822 break;
6823
6824 default:
6825 *sizeP = 0;
6826 return _("Bad call to md_atof ()");
6827 }
6828 t = atof_ieee (input_line_pointer, type, words);
6829 if (t)
6830 input_line_pointer = t;
6831
6832 *sizeP = prec * sizeof (LITTLENUM_TYPE);
6833 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
6834 the bigendian 386. */
6835 for (wordP = words + prec - 1; prec--;)
6836 {
6837 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
6838 litP += sizeof (LITTLENUM_TYPE);
6839 }
6840 return 0;
6841}
6842\f
2d545b82 6843static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 6844
252b5132 6845static char *
e3bb37b5 6846output_invalid (int c)
252b5132 6847{
3882b010 6848 if (ISPRINT (c))
f9f21a03
L		 6849 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6850 "'%c'", c);
252b5132 6851 else
f9f21a03 6852 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 6853 "(0x%x)", (unsigned char) c);
252b5132
RH		 6854 return output_invalid_buf;
6855}
6856
af6bdddf 6857/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 6858
6859static const reg_entry *
4d1bb795 6860parse_real_register (char *reg_string, char **end_op)
252b5132 6861{
af6bdddf
AM		 6862 char *s = reg_string;
6863 char *p;
252b5132
RH		 6864 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6865 const reg_entry *r;
6866
6867 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6868 if (*s == REGISTER_PREFIX)
6869 ++s;
6870
6871 if (is_space_char (*s))
6872 ++s;
6873
6874 p = reg_name_given;
af6bdddf 6875 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 6876 {
6877 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 6878 return (const reg_entry *) NULL;
6879 s++;
252b5132
RH		 6880 }
6881
6588847e
DN		 6882 /* For naked regs, make sure that we are not dealing with an identifier.
6883 This prevents confusing an identifier like `eax_var' with register
6884 `eax'. */
6885 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6886 return (const reg_entry *) NULL;
6887
af6bdddf 6888 *end_op = s;
252b5132
RH		 6889
6890 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6891
5f47d35b 6892 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 6893 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 6894 {
5f47d35b
AM		 6895 if (is_space_char (*s))
6896 ++s;
6897 if (*s == '(')
6898 {
af6bdddf 6899 ++s;
5f47d35b
AM		 6900 if (is_space_char (*s))
6901 ++s;
6902 if (*s >= '0' && *s <= '7')
6903 {
db557034 6904 int fpr = *s - '0';
af6bdddf 6905 ++s;
5f47d35b
AM		 6906 if (is_space_char (*s))
6907 ++s;
6908 if (*s == ')')
6909 {
6910 *end_op = s + 1;
db557034
AM		 6911 r = hash_find (reg_hash, "st(0)");
6912 know (r);
6913 return r + fpr;
5f47d35b 6914 }
5f47d35b 6915 }
47926f60 6916 /* We have "%st(" then garbage. */
5f47d35b
AM		 6917 return (const reg_entry *) NULL;
6918 }
6919 }
6920
db51cc60
L		 6921 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6922 if (r != NULL
6923 && !allow_index_reg
6924 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
6925 return (const reg_entry *) NULL;
6926
1ae00879 6927 if (r != NULL
d946b91f 6928 && ((r->reg_flags & (RegRex64 | RegRex))
40fb9820
L		 6929 || r->reg_type.bitfield.reg64)
6930 && (!cpu_arch_flags.bitfield.cpulm
c6fb90c8 6931 || !UINTS_EQUAL (r->reg_type, control))
1ae00879 6932 && flag_code != CODE_64BIT)
20f0a1fc 6933 return (const reg_entry *) NULL;
1ae00879 6934
252b5132
RH		 6935 return r;
6936}
4d1bb795
JB		 6937
6938/* REG_STRING starts *before* REGISTER_PREFIX. */
6939
6940static const reg_entry *
6941parse_register (char *reg_string, char **end_op)
6942{
6943 const reg_entry *r;
6944
6945 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6946 r = parse_real_register (reg_string, end_op);
6947 else
6948 r = NULL;
6949 if (!r)
6950 {
6951 char *save = input_line_pointer;
6952 char c;
6953 symbolS *symbolP;
6954
6955 input_line_pointer = reg_string;
6956 c = get_symbol_end ();
6957 symbolP = symbol_find (reg_string);
6958 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6959 {
6960 const expressionS *e = symbol_get_value_expression (symbolP);
6961
6962 know (e->X_op == O_register);
4eed87de 6963 know (e->X_add_number >= 0
c3fe08fa 6964 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 6965 r = i386_regtab + e->X_add_number;
6966 *end_op = input_line_pointer;
6967 }
6968 *input_line_pointer = c;
6969 input_line_pointer = save;
6970 }
6971 return r;
6972}
6973
6974int
6975i386_parse_name (char *name, expressionS *e, char *nextcharP)
6976{
6977 const reg_entry *r;
6978 char *end = input_line_pointer;
6979
6980 *end = *nextcharP;
6981 r = parse_register (name, &input_line_pointer);
6982 if (r && end <= input_line_pointer)
6983 {
6984 *nextcharP = *input_line_pointer;
6985 *input_line_pointer = 0;
6986 e->X_op = O_register;
6987 e->X_add_number = r - i386_regtab;
6988 return 1;
6989 }
6990 input_line_pointer = end;
6991 *end = 0;
6992 return 0;
6993}
6994
6995void
6996md_operand (expressionS *e)
6997{
6998 if (*input_line_pointer == REGISTER_PREFIX)
6999 {
7000 char *end;
7001 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7002
7003 if (r)
7004 {
7005 e->X_op = O_register;
7006 e->X_add_number = r - i386_regtab;
7007 input_line_pointer = end;
7008 }
7009 }
7010}
7011
252b5132 7012\f
4cc782b5 7013#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7014const char *md_shortopts = "kVQ:sqn";
252b5132 7015#else
12b55ccc 7016const char *md_shortopts = "qn";
252b5132 7017#endif
6e0b89ee 7018
3e73aa7c 7019#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7020#define OPTION_64 (OPTION_MD_BASE + 1)
7021#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7022#define OPTION_MARCH (OPTION_MD_BASE + 3)
7023#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 7024
99ad8390
NC		 7025struct option md_longopts[] =
7026{
3e73aa7c 7027 {"32", no_argument, NULL, OPTION_32},
99ad8390 7028#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7029 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7030#endif
b3b91714 7031 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7032 {"march", required_argument, NULL, OPTION_MARCH},
7033 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 7034 {NULL, no_argument, NULL, 0}
7035};
7036size_t md_longopts_size = sizeof (md_longopts);
7037
7038int
9103f4f4 7039md_parse_option (int c, char *arg)
252b5132 7040{
9103f4f4
L		 7041 unsigned int i;
7042
252b5132
RH		 7043 switch (c)
7044 {
12b55ccc
L		 7045 case 'n':
7046 optimize_align_code = 0;
7047 break;
7048
a38cf1db
AM		 7049 case 'q':
7050 quiet_warnings = 1;
252b5132
RH		 7051 break;
7052
7053#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7054 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7055 should be emitted or not. FIXME: Not implemented. */
7056 case 'Q':
252b5132
RH		 7057 break;
7058
7059 /* -V: SVR4 argument to print version ID. */
7060 case 'V':
7061 print_version_id ();
7062 break;
7063
a38cf1db
AM		 7064 /* -k: Ignore for FreeBSD compatibility. */
7065 case 'k':
252b5132 7066 break;
4cc782b5
ILT		 7067
7068 case 's':
7069 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7070 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7071 break;
99ad8390
NC		 7072#endif
7073#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7074 case OPTION_64:
7075 {
7076 const char **list, **l;
7077
3e73aa7c
JH		 7078 list = bfd_target_list ();
7079 for (l = list; *l != NULL; l++)
8620418b 7080 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7081 || strcmp (*l, "coff-x86-64") == 0
7082 || strcmp (*l, "pe-x86-64") == 0
7083 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7084 {
7085 default_arch = "x86_64";
7086 break;
7087 }
3e73aa7c 7088 if (*l == NULL)
6e0b89ee 7089 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7090 free (list);
7091 }
7092 break;
7093#endif
252b5132 7094
6e0b89ee
AM		 7095 case OPTION_32:
7096 default_arch = "i386";
7097 break;
7098
b3b91714
AM		 7099 case OPTION_DIVIDE:
7100#ifdef SVR4_COMMENT_CHARS
7101 {
7102 char *n, *t;
7103 const char *s;
7104
7105 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7106 t = n;
7107 for (s = i386_comment_chars; *s != '\0'; s++)
7108 if (*s != '/')
7109 *t++ = *s;
7110 *t = '\0';
7111 i386_comment_chars = n;
7112 }
7113#endif
7114 break;
7115
9103f4f4
L		 7116 case OPTION_MARCH:
7117 if (*arg == '.')
7118 as_fatal (_("Invalid -march= option: `%s'"), arg);
7119 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7120 {
7121 if (strcmp (arg, cpu_arch [i].name) == 0)
7122 {
ccc9c027 7123 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 7124 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 7125 if (!cpu_arch_tune_set)
7126 {
7127 cpu_arch_tune = cpu_arch_isa;
7128 cpu_arch_tune_flags = cpu_arch_isa_flags;
7129 }
9103f4f4
L		 7130 break;
7131 }
7132 }
7133 if (i >= ARRAY_SIZE (cpu_arch))
7134 as_fatal (_("Invalid -march= option: `%s'"), arg);
7135 break;
7136
7137 case OPTION_MTUNE:
7138 if (*arg == '.')
7139 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7140 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7141 {
7142 if (strcmp (arg, cpu_arch [i].name) == 0)
7143 {
ccc9c027 7144 cpu_arch_tune_set = 1;
9103f4f4
L		 7145 cpu_arch_tune = cpu_arch [i].type;
7146 cpu_arch_tune_flags = cpu_arch[i].flags;
7147 break;
7148 }
7149 }
7150 if (i >= ARRAY_SIZE (cpu_arch))
7151 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7152 break;
7153
252b5132
RH		 7154 default:
7155 return 0;
7156 }
7157 return 1;
7158}
7159
7160void
7161md_show_usage (stream)
7162 FILE *stream;
7163{
4cc782b5
ILT		 7164#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7165 fprintf (stream, _("\
a38cf1db
AM		 7166 -Q ignored\n\
7167 -V print assembler version number\n\
b3b91714
AM		 7168 -k ignored\n"));
7169#endif
7170 fprintf (stream, _("\
12b55ccc 7171 -n Do not optimize code alignment\n\
b3b91714
AM		 7172 -q quieten some warnings\n"));
7173#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7174 fprintf (stream, _("\
a38cf1db 7175 -s ignored\n"));
b3b91714 7176#endif
751d281c
L		 7177#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7178 fprintf (stream, _("\
7179 --32/--64 generate 32bit/64bit code\n"));
7180#endif
b3b91714
AM		 7181#ifdef SVR4_COMMENT_CHARS
7182 fprintf (stream, _("\
7183 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7184#else
7185 fprintf (stream, _("\
b3b91714 7186 --divide ignored\n"));
4cc782b5 7187#endif
9103f4f4
L		 7188 fprintf (stream, _("\
7189 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7190 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 7191 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 7192
252b5132
RH		 7193}
7194
3e73aa7c 7195#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 7196 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 7197
7198/* Pick the target format to use. */
7199
47926f60 7200const char *
e3bb37b5 7201i386_target_format (void)
252b5132 7202{
3e73aa7c 7203 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7204 {
7205 set_code_flag (CODE_64BIT);
c6fb90c8 7206 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7207 {
7208 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7209 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7210 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7211 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7212 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7213 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7214 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7215 cpu_arch_isa_flags.bitfield.cpummx= 1;
7216 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7217 cpu_arch_isa_flags.bitfield.cpusse = 1;
7218 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7219 }
c6fb90c8 7220 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7221 {
7222 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7223 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7224 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7225 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7226 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7227 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7228 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7229 cpu_arch_tune_flags.bitfield.cpummx= 1;
7230 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7231 cpu_arch_tune_flags.bitfield.cpusse = 1;
7232 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7233 }
9103f4f4 7234 }
3e73aa7c 7235 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7236 {
7237 set_code_flag (CODE_32BIT);
c6fb90c8 7238 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7239 {
7240 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7241 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7242 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7243 }
c6fb90c8 7244 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7245 {
7246 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7247 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7248 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7249 }
9103f4f4 7250 }
3e73aa7c
JH		 7251 else
7252 as_fatal (_("Unknown architecture"));
252b5132
RH		 7253 switch (OUTPUT_FLAVOR)
7254 {
872ce6ff
L		 7255#ifdef TE_PEP
7256 case bfd_target_coff_flavour:
7257 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7258 break;
7259#endif
4c63da97
AM		 7260#ifdef OBJ_MAYBE_AOUT
7261 case bfd_target_aout_flavour:
47926f60 7262 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7263#endif
7264#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7265 case bfd_target_coff_flavour:
7266 return "coff-i386";
4c63da97 7267#endif
3e73aa7c 7268#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7269 case bfd_target_elf_flavour:
3e73aa7c 7270 {
e5cb08ac 7271 if (flag_code == CODE_64BIT)
4fa24527
JB		 7272 {
7273 object_64bit = 1;
7274 use_rela_relocations = 1;
7275 }
9d7cbccd 7276 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7277 }
4c63da97 7278#endif
252b5132
RH		 7279 default:
7280 abort ();
7281 return NULL;
7282 }
7283}
7284
47926f60 7285#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7286
7287#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7288void
7289i386_elf_emit_arch_note (void)
a847613f 7290{
718ddfc0 7291 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 7292 {
7293 char *p;
7294 asection *seg = now_seg;
7295 subsegT subseg = now_subseg;
7296 Elf_Internal_Note i_note;
7297 Elf_External_Note e_note;
7298 asection *note_secp;
7299 int len;
7300
7301 /* Create the .note section. */
7302 note_secp = subseg_new (".note", 0);
7303 bfd_set_section_flags (stdoutput,
7304 note_secp,
7305 SEC_HAS_CONTENTS | SEC_READONLY);
7306
7307 /* Process the arch string. */
7308 len = strlen (cpu_arch_name);
7309
7310 i_note.namesz = len + 1;
7311 i_note.descsz = 0;
7312 i_note.type = NT_ARCH;
7313 p = frag_more (sizeof (e_note.namesz));
7314 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7315 p = frag_more (sizeof (e_note.descsz));
7316 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7317 p = frag_more (sizeof (e_note.type));
7318 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7319 p = frag_more (len + 1);
7320 strcpy (p, cpu_arch_name);
7321
7322 frag_align (2, 0, 0);
7323
7324 subseg_set (seg, subseg);
7325 }
7326}
7327#endif
252b5132 7328\f
252b5132
RH		 7329symbolS *
7330md_undefined_symbol (name)
7331 char *name;
7332{
18dc2407
ILT		 7333 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7334 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7335 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7336 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 7337 {
7338 if (!GOT_symbol)
7339 {
7340 if (symbol_find (name))
7341 as_bad (_("GOT already in symbol table"));
7342 GOT_symbol = symbol_new (name, undefined_section,
7343 (valueT) 0, &zero_address_frag);
7344 };
7345 return GOT_symbol;
7346 }
252b5132
RH		 7347 return 0;
7348}
7349
7350/* Round up a section size to the appropriate boundary. */
47926f60 7351
252b5132
RH		 7352valueT
7353md_section_align (segment, size)
ab9da554 7354 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7355 valueT size;
7356{
4c63da97
AM		 7357#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7358 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7359 {
7360 /* For a.out, force the section size to be aligned. If we don't do
7361 this, BFD will align it for us, but it will not write out the
7362 final bytes of the section. This may be a bug in BFD, but it is
7363 easier to fix it here since that is how the other a.out targets
7364 work. */
7365 int align;
7366
7367 align = bfd_get_section_alignment (stdoutput, segment);
7368 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7369 }
252b5132
RH		 7370#endif
7371
7372 return size;
7373}
7374
7375/* On the i386, PC-relative offsets are relative to the start of the
7376 next instruction. That is, the address of the offset, plus its
7377 size, since the offset is always the last part of the insn. */
7378
7379long
e3bb37b5 7380md_pcrel_from (fixS *fixP)
252b5132
RH		 7381{
7382 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7383}
7384
7385#ifndef I386COFF
7386
7387static void
e3bb37b5 7388s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 7389{
29b0f896 7390 int temp;
252b5132 7391
8a75718c
JB		 7392#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7393 if (IS_ELF)
7394 obj_elf_section_change_hook ();
7395#endif
252b5132
RH		 7396 temp = get_absolute_expression ();
7397 subseg_set (bss_section, (subsegT) temp);
7398 demand_empty_rest_of_line ();
7399}
7400
7401#endif
7402
252b5132 7403void
e3bb37b5 7404i386_validate_fix (fixS *fixp)
252b5132
RH		 7405{
7406 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7407 {
23df1078
JH		 7408 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7409 {
4fa24527 7410 if (!object_64bit)
23df1078
JH		 7411 abort ();
7412 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7413 }
7414 else
7415 {
4fa24527 7416 if (!object_64bit)
d6ab8113
JB		 7417 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7418 else
7419 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 7420 }
252b5132
RH		 7421 fixp->fx_subsy = 0;
7422 }
7423}
7424
252b5132
RH		 7425arelent *
7426tc_gen_reloc (section, fixp)
ab9da554 7427 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 7428 fixS *fixp;
7429{
7430 arelent *rel;
7431 bfd_reloc_code_real_type code;
7432
7433 switch (fixp->fx_r_type)
7434 {
3e73aa7c
JH		 7435 case BFD_RELOC_X86_64_PLT32:
7436 case BFD_RELOC_X86_64_GOT32:
7437 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 7438 case BFD_RELOC_386_PLT32:
7439 case BFD_RELOC_386_GOT32:
7440 case BFD_RELOC_386_GOTOFF:
7441 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 7442 case BFD_RELOC_386_TLS_GD:
7443 case BFD_RELOC_386_TLS_LDM:
7444 case BFD_RELOC_386_TLS_LDO_32:
7445 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7446 case BFD_RELOC_386_TLS_IE:
7447 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7448 case BFD_RELOC_386_TLS_LE_32:
7449 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7450 case BFD_RELOC_386_TLS_GOTDESC:
7451 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7452 case BFD_RELOC_X86_64_TLSGD:
7453 case BFD_RELOC_X86_64_TLSLD:
7454 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7455 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7456 case BFD_RELOC_X86_64_GOTTPOFF:
7457 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7458 case BFD_RELOC_X86_64_TPOFF64:
7459 case BFD_RELOC_X86_64_GOTOFF64:
7460 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7461 case BFD_RELOC_X86_64_GOT64:
7462 case BFD_RELOC_X86_64_GOTPCREL64:
7463 case BFD_RELOC_X86_64_GOTPC64:
7464 case BFD_RELOC_X86_64_GOTPLT64:
7465 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7466 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7467 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7468 case BFD_RELOC_RVA:
7469 case BFD_RELOC_VTABLE_ENTRY:
7470 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7471#ifdef TE_PE
7472 case BFD_RELOC_32_SECREL:
7473#endif
252b5132
RH		 7474 code = fixp->fx_r_type;
7475 break;
dbbaec26
L		 7476 case BFD_RELOC_X86_64_32S:
7477 if (!fixp->fx_pcrel)
7478 {
7479 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7480 code = fixp->fx_r_type;
7481 break;
7482 }
252b5132 7483 default:
93382f6d 7484 if (fixp->fx_pcrel)
252b5132 7485 {
93382f6d
AM		 7486 switch (fixp->fx_size)
7487 {
7488 default:
b091f402
AM		 7489 as_bad_where (fixp->fx_file, fixp->fx_line,
7490 _("can not do %d byte pc-relative relocation"),
7491 fixp->fx_size);
93382f6d
AM		 7492 code = BFD_RELOC_32_PCREL;
7493 break;
7494 case 1: code = BFD_RELOC_8_PCREL; break;
7495 case 2: code = BFD_RELOC_16_PCREL; break;
7496 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7497#ifdef BFD64
7498 case 8: code = BFD_RELOC_64_PCREL; break;
7499#endif
93382f6d
AM		 7500 }
7501 }
7502 else
7503 {
7504 switch (fixp->fx_size)
7505 {
7506 default:
b091f402
AM		 7507 as_bad_where (fixp->fx_file, fixp->fx_line,
7508 _("can not do %d byte relocation"),
7509 fixp->fx_size);
93382f6d
AM		 7510 code = BFD_RELOC_32;
7511 break;
7512 case 1: code = BFD_RELOC_8; break;
7513 case 2: code = BFD_RELOC_16; break;
7514 case 4: code = BFD_RELOC_32; break;
937149dd 7515#ifdef BFD64
3e73aa7c 7516 case 8: code = BFD_RELOC_64; break;
937149dd 7517#endif
93382f6d 7518 }
252b5132
RH		 7519 }
7520 break;
7521 }
252b5132 7522
d182319b
JB		 7523 if ((code == BFD_RELOC_32
7524 || code == BFD_RELOC_32_PCREL
7525 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7526 && GOT_symbol
7527 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7528 {
4fa24527 7529 if (!object_64bit)
d6ab8113
JB		 7530 code = BFD_RELOC_386_GOTPC;
7531 else
7532 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7533 }
7b81dfbb
AJ		 7534 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7535 && GOT_symbol
7536 && fixp->fx_addsy == GOT_symbol)
7537 {
7538 code = BFD_RELOC_X86_64_GOTPC64;
7539 }
252b5132
RH		 7540
7541 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7542 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7543 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7544
7545 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7546
3e73aa7c
JH		 7547 if (!use_rela_relocations)
7548 {
7549 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7550 vtable entry to be used in the relocation's section offset. */
7551 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7552 rel->address = fixp->fx_offset;
252b5132 7553
c6682705 7554 rel->addend = 0;
3e73aa7c
JH		 7555 }
7556 /* Use the rela in 64bit mode. */
252b5132 7557 else
3e73aa7c 7558 {
062cd5e7
AS		 7559 if (!fixp->fx_pcrel)
7560 rel->addend = fixp->fx_offset;
7561 else
7562 switch (code)
7563 {
7564 case BFD_RELOC_X86_64_PLT32:
7565 case BFD_RELOC_X86_64_GOT32:
7566 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7567 case BFD_RELOC_X86_64_TLSGD:
7568 case BFD_RELOC_X86_64_TLSLD:
7569 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7570 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7571 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7572 rel->addend = fixp->fx_offset - fixp->fx_size;
7573 break;
7574 default:
7575 rel->addend = (section->vma
7576 - fixp->fx_size
7577 + fixp->fx_addnumber
7578 + md_pcrel_from (fixp));
7579 break;
7580 }
3e73aa7c
JH		 7581 }
7582
252b5132
RH		 7583 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7584 if (rel->howto == NULL)
7585 {
7586 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7587 _("cannot represent relocation type %s"),
252b5132
RH		 7588 bfd_get_reloc_code_name (code));
7589 /* Set howto to a garbage value so that we can keep going. */
7590 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7591 assert (rel->howto != NULL);
7592 }
7593
7594 return rel;
7595}
7596
64a0c779
DN		 7597\f
7598/* Parse operands using Intel syntax. This implements a recursive descent
7599 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7600 Programmer's Guide.
7601
7602 FIXME: We do not recognize the full operand grammar defined in the MASM
7603 documentation. In particular, all the structure/union and
7604 high-level macro operands are missing.
7605
7606 Uppercase words are terminals, lower case words are non-terminals.
7607 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7608 bars '|' denote choices. Most grammar productions are implemented in
7609 functions called 'intel_<production>'.
7610
7611 Initial production is 'expr'.
7612
9306ca4a 7613 addOp + | -
64a0c779
DN		 7614
7615 alpha [a-zA-Z]
7616
9306ca4a
JB		 7617 binOp & | AND | \| | OR | ^ | XOR
7618
64a0c779
DN		 7619 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7620
7621 constant digits [[ radixOverride ]]
7622
9306ca4a 7623 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7624
7625 digits decdigit
b77a7acd
AJ		 7626 | digits decdigit
7627 | digits hexdigit
64a0c779
DN		 7628
7629 decdigit [0-9]
7630
9306ca4a
JB		 7631 e04 e04 addOp e05
7632 | e05
7633
7634 e05 e05 binOp e06
b77a7acd 7635 | e06
64a0c779
DN		 7636
7637 e06 e06 mulOp e09
b77a7acd 7638 | e09
64a0c779
DN		 7639
7640 e09 OFFSET e10
a724f0f4
JB		 7641 | SHORT e10
7642 | + e10
7643 | - e10
9306ca4a
JB		 7644 | ~ e10
7645 | NOT e10
64a0c779
DN		 7646 | e09 PTR e10
7647 | e09 : e10
7648 | e10
7649
7650 e10 e10 [ expr ]
b77a7acd 7651 | e11
64a0c779
DN		 7652
7653 e11 ( expr )
b77a7acd 7654 | [ expr ]
64a0c779
DN		 7655 | constant
7656 | dataType
7657 | id
7658 | $
7659 | register
7660
a724f0f4 7661 => expr expr cmpOp e04
9306ca4a 7662 | e04
64a0c779
DN		 7663
7664 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7665 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7666
7667 hexdigit a | b | c | d | e | f
b77a7acd 7668 | A | B | C | D | E | F
64a0c779
DN		 7669
7670 id alpha
b77a7acd 7671 | id alpha
64a0c779
DN		 7672 | id decdigit
7673
9306ca4a 7674 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7675
7676 quote " | '
7677
7678 register specialRegister
b77a7acd 7679 | gpRegister
64a0c779
DN		 7680 | byteRegister
7681
7682 segmentRegister CS | DS | ES | FS | GS | SS
7683
9306ca4a 7684 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7685 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7686 | TR3 | TR4 | TR5 | TR6 | TR7
7687
64a0c779
DN		 7688 We simplify the grammar in obvious places (e.g., register parsing is
7689 done by calling parse_register) and eliminate immediate left recursion
7690 to implement a recursive-descent parser.
7691
a724f0f4
JB		 7692 expr e04 expr'
7693
7694 expr' cmpOp e04 expr'
7695 | Empty
9306ca4a
JB		 7696
7697 e04 e05 e04'
7698
7699 e04' addOp e05 e04'
7700 | Empty
64a0c779
DN		 7701
7702 e05 e06 e05'
7703
9306ca4a 7704 e05' binOp e06 e05'
b77a7acd 7705 | Empty
64a0c779
DN		 7706
7707 e06 e09 e06'
7708
7709 e06' mulOp e09 e06'
b77a7acd 7710 | Empty
64a0c779
DN		 7711
7712 e09 OFFSET e10 e09'
a724f0f4
JB		 7713 | SHORT e10'
7714 | + e10'
7715 | - e10'
7716 | ~ e10'
7717 | NOT e10'
b77a7acd 7718 | e10 e09'
64a0c779
DN		 7719
7720 e09' PTR e10 e09'
b77a7acd 7721 | : e10 e09'
64a0c779
DN		 7722 | Empty
7723
7724 e10 e11 e10'
7725
7726 e10' [ expr ] e10'
b77a7acd 7727 | Empty
64a0c779
DN		 7728
7729 e11 ( expr )
b77a7acd 7730 | [ expr ]
64a0c779
DN		 7731 | BYTE
7732 | WORD
7733 | DWORD
9306ca4a 7734 | FWORD
64a0c779 7735 | QWORD
9306ca4a
JB		 7736 | TBYTE
7737 | OWORD
7738 | XMMWORD
64a0c779
DN		 7739 | .
7740 | $
7741 | register
7742 | id
7743 | constant */
7744
7745/* Parsing structure for the intel syntax parser. Used to implement the
7746 semantic actions for the operand grammar. */
7747struct intel_parser_s
7748 {
7749 char *op_string; /* The string being parsed. */
7750 int got_a_float; /* Whether the operand is a float. */
4a1805b1 7751 int op_modifier; /* Operand modifier. */
64a0c779 7752 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 7753 int in_offset; /* >=1 if parsing operand of offset. */
7754 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 7755 const reg_entry *reg; /* Last register reference found. */
7756 char *disp; /* Displacement string being built. */
a724f0f4 7757 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 7758 };
7759
7760static struct intel_parser_s intel_parser;
7761
7762/* Token structure for parsing intel syntax. */
7763struct intel_token
7764 {
7765 int code; /* Token code. */
7766 const reg_entry *reg; /* Register entry for register tokens. */
7767 char *str; /* String representation. */
7768 };
7769
7770static struct intel_token cur_token, prev_token;
7771
50705ef4
AM		 7772/* Token codes for the intel parser. Since T_SHORT is already used
7773 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 7774#define T_NIL -1
7775#define T_CONST 1
7776#define T_REG 2
7777#define T_BYTE 3
7778#define T_WORD 4
9306ca4a
JB		 7779#define T_DWORD 5
7780#define T_FWORD 6
7781#define T_QWORD 7
7782#define T_TBYTE 8
7783#define T_XMMWORD 9
50705ef4 7784#undef T_SHORT
9306ca4a
JB		 7785#define T_SHORT 10
7786#define T_OFFSET 11
7787#define T_PTR 12
7788#define T_ID 13
7789#define T_SHL 14
7790#define T_SHR 15
64a0c779
DN		 7791
7792/* Prototypes for intel parser functions. */
e3bb37b5
L		 7793static int intel_match_token (int);
7794static void intel_putback_token (void);
7795static void intel_get_token (void);
7796static int intel_expr (void);
7797static int intel_e04 (void);
7798static int intel_e05 (void);
7799static int intel_e06 (void);
7800static int intel_e09 (void);
7801static int intel_e10 (void);
7802static int intel_e11 (void);
64a0c779 7803
64a0c779 7804static int
e3bb37b5 7805i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 7806{
7807 int ret;
7808 char *p;
7809
a724f0f4
JB		 7810 p = intel_parser.op_string = xstrdup (operand_string);
7811 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7812
7813 for (;;)
64a0c779 7814 {
a724f0f4
JB		 7815 /* Initialize token holders. */
7816 cur_token.code = prev_token.code = T_NIL;
7817 cur_token.reg = prev_token.reg = NULL;
7818 cur_token.str = prev_token.str = NULL;
7819
7820 /* Initialize parser structure. */
7821 intel_parser.got_a_float = got_a_float;
7822 intel_parser.op_modifier = 0;
7823 intel_parser.is_mem = 0;
7824 intel_parser.in_offset = 0;
7825 intel_parser.in_bracket = 0;
7826 intel_parser.reg = NULL;
7827 intel_parser.disp[0] = '\0';
7828 intel_parser.next_operand = NULL;
7829
7830 /* Read the first token and start the parser. */
7831 intel_get_token ();
7832 ret = intel_expr ();
7833
7834 if (!ret)
7835 break;
7836
9306ca4a
JB		 7837 if (cur_token.code != T_NIL)
7838 {
7839 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7840 current_templates->start->name, cur_token.str);
7841 ret = 0;
7842 }
64a0c779
DN		 7843 /* If we found a memory reference, hand it over to i386_displacement
7844 to fill in the rest of the operand fields. */
9306ca4a 7845 else if (intel_parser.is_mem)
64a0c779
DN		 7846 {
7847 if ((i.mem_operands == 1
40fb9820 7848 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 7849 || i.mem_operands == 2)
7850 {
7851 as_bad (_("too many memory references for '%s'"),
7852 current_templates->start->name);
7853 ret = 0;
7854 }
7855 else
7856 {
7857 char *s = intel_parser.disp;
7858 i.mem_operands++;
7859
a724f0f4
JB		 7860 if (!quiet_warnings && intel_parser.is_mem < 0)
7861 /* See the comments in intel_bracket_expr. */
7862 as_warn (_("Treating `%s' as memory reference"), operand_string);
7863
64a0c779
DN		 7864 /* Add the displacement expression. */
7865 if (*s != '\0')
a4622f40
AM		 7866 ret = i386_displacement (s, s + strlen (s));
7867 if (ret)
a724f0f4
JB		 7868 {
7869 /* Swap base and index in 16-bit memory operands like
7870 [si+bx]. Since i386_index_check is also used in AT&T
7871 mode we have to do that here. */
7872 if (i.base_reg
7873 && i.index_reg
40fb9820
L		 7874 && i.base_reg->reg_type.bitfield.reg16
7875 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 7876 && i.base_reg->reg_num >= 6
7877 && i.index_reg->reg_num < 6)
7878 {
7879 const reg_entry *base = i.index_reg;
7880
7881 i.index_reg = i.base_reg;
7882 i.base_reg = base;
7883 }
7884 ret = i386_index_check (operand_string);
7885 }
64a0c779
DN		 7886 }
7887 }
7888
7889 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 7890 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 7891 || intel_parser.reg == NULL)
7892 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 7893
7894 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 7895 ret = 0;
a724f0f4
JB		 7896 if (!ret || !intel_parser.next_operand)
7897 break;
7898 intel_parser.op_string = intel_parser.next_operand;
7899 this_operand = i.operands++;
64a0c779
DN		 7900 }
7901
7902 free (p);
7903 free (intel_parser.disp);
7904
7905 return ret;
7906}
7907
a724f0f4
JB		 7908#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7909
7910/* expr e04 expr'
7911
7912 expr' cmpOp e04 expr'
7913 | Empty */
64a0c779 7914static int
e3bb37b5 7915intel_expr (void)
64a0c779 7916{
a724f0f4
JB		 7917 /* XXX Implement the comparison operators. */
7918 return intel_e04 ();
9306ca4a
JB		 7919}
7920
a724f0f4 7921/* e04 e05 e04'
9306ca4a 7922
a724f0f4 7923 e04' addOp e05 e04'
9306ca4a
JB		 7924 | Empty */
7925static int
e3bb37b5 7926intel_e04 (void)
9306ca4a 7927{
a724f0f4 7928 int nregs = -1;
9306ca4a 7929
a724f0f4 7930 for (;;)
9306ca4a 7931 {
a724f0f4
JB		 7932 if (!intel_e05())
7933 return 0;
9306ca4a 7934
a724f0f4
JB		 7935 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7936 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 7937
a724f0f4
JB		 7938 if (cur_token.code == '+')
7939 nregs = -1;
7940 else if (cur_token.code == '-')
7941 nregs = NUM_ADDRESS_REGS;
7942 else
7943 return 1;
64a0c779 7944
a724f0f4
JB		 7945 strcat (intel_parser.disp, cur_token.str);
7946 intel_match_token (cur_token.code);
7947 }
64a0c779
DN		 7948}
7949
64a0c779
DN		 7950/* e05 e06 e05'
7951
9306ca4a 7952 e05' binOp e06 e05'
64a0c779
DN		 7953 | Empty */
7954static int
e3bb37b5 7955intel_e05 (void)
64a0c779 7956{
a724f0f4 7957 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7958
a724f0f4 7959 for (;;)
64a0c779 7960 {
a724f0f4
JB		 7961 if (!intel_e06())
7962 return 0;
7963
4eed87de
AM		 7964 if (cur_token.code == '&'
7965 || cur_token.code == '|'
7966 || cur_token.code == '^')
a724f0f4
JB		 7967 {
7968 char str[2];
7969
7970 str[0] = cur_token.code;
7971 str[1] = 0;
7972 strcat (intel_parser.disp, str);
7973 }
7974 else
7975 break;
9306ca4a 7976
64a0c779
DN		 7977 intel_match_token (cur_token.code);
7978
a724f0f4
JB		 7979 if (nregs < 0)
7980 nregs = ~nregs;
64a0c779 7981 }
a724f0f4
JB		 7982 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7983 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7984 return 1;
4a1805b1 7985}
64a0c779
DN		 7986
7987/* e06 e09 e06'
7988
7989 e06' mulOp e09 e06'
b77a7acd 7990 | Empty */
64a0c779 7991static int
e3bb37b5 7992intel_e06 (void)
64a0c779 7993{
a724f0f4 7994 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7995
a724f0f4 7996 for (;;)
64a0c779 7997 {
a724f0f4
JB		 7998 if (!intel_e09())
7999 return 0;
9306ca4a 8000
4eed87de
AM		 8001 if (cur_token.code == '*'
8002 || cur_token.code == '/'
8003 || cur_token.code == '%')
a724f0f4
JB		 8004 {
8005 char str[2];
9306ca4a 8006
a724f0f4
JB		 8007 str[0] = cur_token.code;
8008 str[1] = 0;
8009 strcat (intel_parser.disp, str);
8010 }
8011 else if (cur_token.code == T_SHL)
8012 strcat (intel_parser.disp, "<<");
8013 else if (cur_token.code == T_SHR)
8014 strcat (intel_parser.disp, ">>");
8015 else
8016 break;
9306ca4a 8017
64e74474 8018 intel_match_token (cur_token.code);
64a0c779 8019
a724f0f4
JB		 8020 if (nregs < 0)
8021 nregs = ~nregs;
64a0c779 8022 }
a724f0f4
JB		 8023 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8024 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8025 return 1;
64a0c779
DN		 8026}
8027
a724f0f4
JB		 8028/* e09 OFFSET e09
8029 | SHORT e09
8030 | + e09
8031 | - e09
8032 | ~ e09
8033 | NOT e09
9306ca4a
JB		 8034 | e10 e09'
8035
64a0c779 8036 e09' PTR e10 e09'
b77a7acd 8037 | : e10 e09'
64a0c779
DN		 8038 | Empty */
8039static int
e3bb37b5 8040intel_e09 (void)
64a0c779 8041{
a724f0f4
JB		 8042 int nregs = ~NUM_ADDRESS_REGS;
8043 int in_offset = 0;
8044
8045 for (;;)
64a0c779 8046 {
a724f0f4
JB		 8047 /* Don't consume constants here. */
8048 if (cur_token.code == '+' || cur_token.code == '-')
8049 {
8050 /* Need to look one token ahead - if the next token
8051 is a constant, the current token is its sign. */
8052 int next_code;
8053
8054 intel_match_token (cur_token.code);
8055 next_code = cur_token.code;
8056 intel_putback_token ();
8057 if (next_code == T_CONST)
8058 break;
8059 }
8060
8061 /* e09 OFFSET e09 */
8062 if (cur_token.code == T_OFFSET)
8063 {
8064 if (!in_offset++)
8065 ++intel_parser.in_offset;
8066 }
8067
8068 /* e09 SHORT e09 */
8069 else if (cur_token.code == T_SHORT)
8070 intel_parser.op_modifier |= 1 << T_SHORT;
8071
8072 /* e09 + e09 */
8073 else if (cur_token.code == '+')
8074 strcat (intel_parser.disp, "+");
8075
8076 /* e09 - e09
8077 | ~ e09
8078 | NOT e09 */
8079 else if (cur_token.code == '-' || cur_token.code == '~')
8080 {
8081 char str[2];
64a0c779 8082
a724f0f4
JB		 8083 if (nregs < 0)
8084 nregs = ~nregs;
8085 str[0] = cur_token.code;
8086 str[1] = 0;
8087 strcat (intel_parser.disp, str);
8088 }
8089
8090 /* e09 e10 e09' */
8091 else
8092 break;
8093
8094 intel_match_token (cur_token.code);
64a0c779
DN		 8095 }
8096
a724f0f4 8097 for (;;)
9306ca4a 8098 {
a724f0f4
JB		 8099 if (!intel_e10 ())
8100 return 0;
9306ca4a 8101
a724f0f4
JB		 8102 /* e09' PTR e10 e09' */
8103 if (cur_token.code == T_PTR)
8104 {
8105 char suffix;
9306ca4a 8106
a724f0f4
JB		 8107 if (prev_token.code == T_BYTE)
8108 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 8109
a724f0f4
JB		 8110 else if (prev_token.code == T_WORD)
8111 {
8112 if (current_templates->start->name[0] == 'l'
8113 && current_templates->start->name[2] == 's'
8114 && current_templates->start->name[3] == 0)
8115 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8116 else if (intel_parser.got_a_float == 2) /* "fi..." */
8117 suffix = SHORT_MNEM_SUFFIX;
8118 else
8119 suffix = WORD_MNEM_SUFFIX;
8120 }
64a0c779 8121
a724f0f4
JB		 8122 else if (prev_token.code == T_DWORD)
8123 {
8124 if (current_templates->start->name[0] == 'l'
8125 && current_templates->start->name[2] == 's'
8126 && current_templates->start->name[3] == 0)
8127 suffix = WORD_MNEM_SUFFIX;
8128 else if (flag_code == CODE_16BIT
40fb9820
L		 8129 && (current_templates->start->opcode_modifier.jump
8130 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 8131 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8132 else if (intel_parser.got_a_float == 1) /* "f..." */
8133 suffix = SHORT_MNEM_SUFFIX;
8134 else
8135 suffix = LONG_MNEM_SUFFIX;
8136 }
9306ca4a 8137
a724f0f4
JB		 8138 else if (prev_token.code == T_FWORD)
8139 {
8140 if (current_templates->start->name[0] == 'l'
8141 && current_templates->start->name[2] == 's'
8142 && current_templates->start->name[3] == 0)
8143 suffix = LONG_MNEM_SUFFIX;
8144 else if (!intel_parser.got_a_float)
8145 {
8146 if (flag_code == CODE_16BIT)
8147 add_prefix (DATA_PREFIX_OPCODE);
8148 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8149 }
8150 else
8151 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8152 }
64a0c779 8153
a724f0f4
JB		 8154 else if (prev_token.code == T_QWORD)
8155 {
8156 if (intel_parser.got_a_float == 1) /* "f..." */
8157 suffix = LONG_MNEM_SUFFIX;
8158 else
8159 suffix = QWORD_MNEM_SUFFIX;
8160 }
64a0c779 8161
a724f0f4
JB		 8162 else if (prev_token.code == T_TBYTE)
8163 {
8164 if (intel_parser.got_a_float == 1)
8165 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8166 else
8167 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8168 }
9306ca4a 8169
a724f0f4 8170 else if (prev_token.code == T_XMMWORD)
9306ca4a 8171 {
a724f0f4
JB		 8172 /* XXX ignored for now, but accepted since gcc uses it */
8173 suffix = 0;
9306ca4a 8174 }
64a0c779 8175
f16b83df 8176 else
a724f0f4
JB		 8177 {
8178 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8179 return 0;
8180 }
8181
435acd52
JB		 8182 /* Operands for jump/call using 'ptr' notation denote absolute
8183 addresses. */
40fb9820
L		 8184 if (current_templates->start->opcode_modifier.jump
8185 || current_templates->start->opcode_modifier.jumpdword)
8186 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8187
a724f0f4
JB		 8188 if (current_templates->start->base_opcode == 0x8d /* lea */)
8189 ;
8190 else if (!i.suffix)
8191 i.suffix = suffix;
8192 else if (i.suffix != suffix)
8193 {
8194 as_bad (_("Conflicting operand modifiers"));
8195 return 0;
8196 }
64a0c779 8197
9306ca4a
JB		 8198 }
8199
a724f0f4
JB		 8200 /* e09' : e10 e09' */
8201 else if (cur_token.code == ':')
9306ca4a 8202 {
a724f0f4
JB		 8203 if (prev_token.code != T_REG)
8204 {
8205 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8206 segment/group identifier (which we don't have), using comma
8207 as the operand separator there is even less consistent, since
8208 there all branches only have a single operand. */
8209 if (this_operand != 0
8210 || intel_parser.in_offset
8211 || intel_parser.in_bracket
40fb9820
L		 8212 || (!current_templates->start->opcode_modifier.jump
8213 && !current_templates->start->opcode_modifier.jumpdword
8214 && !current_templates->start->opcode_modifier.jumpintersegment
8215 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 8216 return intel_match_token (T_NIL);
8217 /* Remember the start of the 2nd operand and terminate 1st
8218 operand here.
8219 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8220 another expression), but it gets at least the simplest case
8221 (a plain number or symbol on the left side) right. */
8222 intel_parser.next_operand = intel_parser.op_string;
8223 *--intel_parser.op_string = '\0';
8224 return intel_match_token (':');
8225 }
9306ca4a 8226 }
64a0c779 8227
a724f0f4 8228 /* e09' Empty */
64a0c779 8229 else
a724f0f4 8230 break;
64a0c779 8231
a724f0f4
JB		 8232 intel_match_token (cur_token.code);
8233
8234 }
8235
8236 if (in_offset)
8237 {
8238 --intel_parser.in_offset;
8239 if (nregs < 0)
8240 nregs = ~nregs;
8241 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 8242 {
a724f0f4 8243 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 8244 return 0;
8245 }
a724f0f4
JB		 8246 intel_parser.op_modifier |= 1 << T_OFFSET;
8247 }
9306ca4a 8248
a724f0f4
JB		 8249 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8250 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8251 return 1;
8252}
64a0c779 8253
a724f0f4 8254static int
e3bb37b5 8255intel_bracket_expr (void)
a724f0f4
JB		 8256{
8257 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8258 const char *start = intel_parser.op_string;
8259 int len;
8260
8261 if (i.op[this_operand].regs)
8262 return intel_match_token (T_NIL);
8263
8264 intel_match_token ('[');
8265
8266 /* Mark as a memory operand only if it's not already known to be an
8267 offset expression. If it's an offset expression, we need to keep
8268 the brace in. */
8269 if (!intel_parser.in_offset)
8270 {
8271 ++intel_parser.in_bracket;
435acd52
JB		 8272
8273 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 8274 if (current_templates->start->opcode_modifier.jump
8275 || current_templates->start->opcode_modifier.jumpdword)
8276 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8277
a724f0f4
JB		 8278 /* Unfortunately gas always diverged from MASM in a respect that can't
8279 be easily fixed without risking to break code sequences likely to be
8280 encountered (the testsuite even check for this): MASM doesn't consider
8281 an expression inside brackets unconditionally as a memory reference.
8282 When that is e.g. a constant, an offset expression, or the sum of the
8283 two, this is still taken as a constant load. gas, however, always
8284 treated these as memory references. As a compromise, we'll try to make
8285 offset expressions inside brackets work the MASM way (since that's
8286 less likely to be found in real world code), but make constants alone
8287 continue to work the traditional gas way. In either case, issue a
8288 warning. */
8289 intel_parser.op_modifier &= ~was_offset;
64a0c779 8290 }
a724f0f4 8291 else
64e74474 8292 strcat (intel_parser.disp, "[");
a724f0f4
JB		 8293
8294 /* Add a '+' to the displacement string if necessary. */
8295 if (*intel_parser.disp != '\0'
8296 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8297 strcat (intel_parser.disp, "+");
64a0c779 8298
a724f0f4
JB		 8299 if (intel_expr ()
8300 && (len = intel_parser.op_string - start - 1,
8301 intel_match_token (']')))
64a0c779 8302 {
a724f0f4
JB		 8303 /* Preserve brackets when the operand is an offset expression. */
8304 if (intel_parser.in_offset)
8305 strcat (intel_parser.disp, "]");
8306 else
8307 {
8308 --intel_parser.in_bracket;
8309 if (i.base_reg || i.index_reg)
8310 intel_parser.is_mem = 1;
8311 if (!intel_parser.is_mem)
8312 {
8313 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8314 /* Defer the warning until all of the operand was parsed. */
8315 intel_parser.is_mem = -1;
8316 else if (!quiet_warnings)
4eed87de
AM		 8317 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8318 len, start, len, start);
a724f0f4
JB		 8319 }
8320 }
8321 intel_parser.op_modifier |= was_offset;
64a0c779 8322
a724f0f4 8323 return 1;
64a0c779 8324 }
a724f0f4 8325 return 0;
64a0c779
DN		 8326}
8327
8328/* e10 e11 e10'
8329
8330 e10' [ expr ] e10'
b77a7acd 8331 | Empty */
64a0c779 8332static int
e3bb37b5 8333intel_e10 (void)
64a0c779 8334{
a724f0f4
JB		 8335 if (!intel_e11 ())
8336 return 0;
64a0c779 8337
a724f0f4 8338 while (cur_token.code == '[')
64a0c779 8339 {
a724f0f4 8340 if (!intel_bracket_expr ())
21d6c4af 8341 return 0;
64a0c779
DN		 8342 }
8343
a724f0f4 8344 return 1;
64a0c779
DN		 8345}
8346
64a0c779 8347/* e11 ( expr )
b77a7acd 8348 | [ expr ]
64a0c779
DN		 8349 | BYTE
8350 | WORD
8351 | DWORD
9306ca4a 8352 | FWORD
64a0c779 8353 | QWORD
9306ca4a
JB		 8354 | TBYTE
8355 | OWORD
8356 | XMMWORD
4a1805b1 8357 | $
64a0c779
DN		 8358 | .
8359 | register
8360 | id
8361 | constant */
8362static int
e3bb37b5 8363intel_e11 (void)
64a0c779 8364{
a724f0f4 8365 switch (cur_token.code)
64a0c779 8366 {
a724f0f4
JB		 8367 /* e11 ( expr ) */
8368 case '(':
64a0c779
DN		 8369 intel_match_token ('(');
8370 strcat (intel_parser.disp, "(");
8371
8372 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 8373 {
8374 strcat (intel_parser.disp, ")");
8375 return 1;
8376 }
a724f0f4 8377 return 0;
4a1805b1 8378
a724f0f4
JB		 8379 /* e11 [ expr ] */
8380 case '[':
a724f0f4 8381 return intel_bracket_expr ();
64a0c779 8382
a724f0f4
JB		 8383 /* e11 $
8384 | . */
8385 case '.':
64a0c779
DN		 8386 strcat (intel_parser.disp, cur_token.str);
8387 intel_match_token (cur_token.code);
21d6c4af
DN		 8388
8389 /* Mark as a memory operand only if it's not already known to be an
8390 offset expression. */
a724f0f4 8391 if (!intel_parser.in_offset)
21d6c4af 8392 intel_parser.is_mem = 1;
64a0c779
DN		 8393
8394 return 1;
64a0c779 8395
a724f0f4
JB		 8396 /* e11 register */
8397 case T_REG:
8398 {
8399 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 8400
a724f0f4 8401 intel_match_token (T_REG);
64a0c779 8402
a724f0f4
JB		 8403 /* Check for segment change. */
8404 if (cur_token.code == ':')
8405 {
40fb9820
L		 8406 if (!reg->reg_type.bitfield.sreg2
8407 && !reg->reg_type.bitfield.sreg3)
a724f0f4 8408 {
4eed87de
AM		 8409 as_bad (_("`%s' is not a valid segment register"),
8410 reg->reg_name);
a724f0f4
JB		 8411 return 0;
8412 }
8413 else if (i.seg[i.mem_operands])
8414 as_warn (_("Extra segment override ignored"));
8415 else
8416 {
8417 if (!intel_parser.in_offset)
8418 intel_parser.is_mem = 1;
8419 switch (reg->reg_num)
8420 {
8421 case 0:
8422 i.seg[i.mem_operands] = &es;
8423 break;
8424 case 1:
8425 i.seg[i.mem_operands] = &cs;
8426 break;
8427 case 2:
8428 i.seg[i.mem_operands] = &ss;
8429 break;
8430 case 3:
8431 i.seg[i.mem_operands] = &ds;
8432 break;
8433 case 4:
8434 i.seg[i.mem_operands] = &fs;
8435 break;
8436 case 5:
8437 i.seg[i.mem_operands] = &gs;
8438 break;
8439 }
8440 }
8441 }
64a0c779 8442
a724f0f4
JB		 8443 /* Not a segment register. Check for register scaling. */
8444 else if (cur_token.code == '*')
8445 {
8446 if (!intel_parser.in_bracket)
8447 {
8448 as_bad (_("Register scaling only allowed in memory operands"));
8449 return 0;
8450 }
64a0c779 8451
40fb9820 8452 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8453 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8454 else if (i.index_reg)
8455 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8456
a724f0f4
JB		 8457 /* What follows must be a valid scale. */
8458 intel_match_token ('*');
8459 i.index_reg = reg;
40fb9820 8460 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8461
a724f0f4
JB		 8462 /* Set the scale after setting the register (otherwise,
8463 i386_scale will complain) */
8464 if (cur_token.code == '+' || cur_token.code == '-')
8465 {
8466 char *str, sign = cur_token.code;
8467 intel_match_token (cur_token.code);
8468 if (cur_token.code != T_CONST)
8469 {
8470 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8471 cur_token.str);
8472 return 0;
8473 }
8474 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8475 strcpy (str + 1, cur_token.str);
8476 *str = sign;
8477 if (!i386_scale (str))
8478 return 0;
8479 free (str);
8480 }
8481 else if (!i386_scale (cur_token.str))
64a0c779 8482 return 0;
a724f0f4
JB		 8483 intel_match_token (cur_token.code);
8484 }
64a0c779 8485
a724f0f4
JB		 8486 /* No scaling. If this is a memory operand, the register is either a
8487 base register (first occurrence) or an index register (second
8488 occurrence). */
7b0441f6 8489 else if (intel_parser.in_bracket)
a724f0f4 8490 {
64a0c779 8491
a724f0f4
JB		 8492 if (!i.base_reg)
8493 i.base_reg = reg;
8494 else if (!i.index_reg)
8495 i.index_reg = reg;
8496 else
8497 {
8498 as_bad (_("Too many register references in memory operand"));
8499 return 0;
8500 }
64a0c779 8501
40fb9820 8502 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8503 }
4a1805b1 8504
4d1bb795
JB		 8505 /* It's neither base nor index. */
8506 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8507 {
40fb9820
L		 8508 i386_operand_type temp = reg->reg_type;
8509 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8510 i.types[this_operand] = operand_type_or (i.types[this_operand],
8511 temp);
a724f0f4
JB		 8512 i.op[this_operand].regs = reg;
8513 i.reg_operands++;
8514 }
8515 else
8516 {
8517 as_bad (_("Invalid use of register"));
8518 return 0;
8519 }
64a0c779 8520
a724f0f4
JB		 8521 /* Since registers are not part of the displacement string (except
8522 when we're parsing offset operands), we may need to remove any
8523 preceding '+' from the displacement string. */
8524 if (*intel_parser.disp != '\0'
8525 && !intel_parser.in_offset)
8526 {
8527 char *s = intel_parser.disp;
8528 s += strlen (s) - 1;
8529 if (*s == '+')
8530 *s = '\0';
8531 }
4a1805b1 8532
a724f0f4
JB		 8533 return 1;
8534 }
8535
8536 /* e11 BYTE
8537 | WORD
8538 | DWORD
8539 | FWORD
8540 | QWORD
8541 | TBYTE
8542 | OWORD
8543 | XMMWORD */
8544 case T_BYTE:
8545 case T_WORD:
8546 case T_DWORD:
8547 case T_FWORD:
8548 case T_QWORD:
8549 case T_TBYTE:
8550 case T_XMMWORD:
8551 intel_match_token (cur_token.code);
64a0c779 8552
a724f0f4
JB		 8553 if (cur_token.code == T_PTR)
8554 return 1;
8555
8556 /* It must have been an identifier. */
8557 intel_putback_token ();
8558 cur_token.code = T_ID;
8559 /* FALLTHRU */
8560
8561 /* e11 id
8562 | constant */
8563 case T_ID:
8564 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8565 {
8566 symbolS *symbolP;
8567
a724f0f4
JB		 8568 /* The identifier represents a memory reference only if it's not
8569 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8570 symbolP = symbol_find(cur_token.str);
8571 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8572 intel_parser.is_mem = 1;
8573 }
a724f0f4 8574 /* FALLTHRU */
64a0c779 8575
a724f0f4
JB		 8576 case T_CONST:
8577 case '-':
8578 case '+':
8579 {
8580 char *save_str, sign = 0;
64a0c779 8581
a724f0f4
JB		 8582 /* Allow constants that start with `+' or `-'. */
8583 if (cur_token.code == '-' || cur_token.code == '+')
8584 {
8585 sign = cur_token.code;
8586 intel_match_token (cur_token.code);
8587 if (cur_token.code != T_CONST)
8588 {
8589 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8590 cur_token.str);
8591 return 0;
8592 }
8593 }
64a0c779 8594
a724f0f4
JB		 8595 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8596 strcpy (save_str + !!sign, cur_token.str);
8597 if (sign)
8598 *save_str = sign;
64a0c779 8599
a724f0f4
JB		 8600 /* Get the next token to check for register scaling. */
8601 intel_match_token (cur_token.code);
64a0c779 8602
4eed87de
AM		 8603 /* Check if this constant is a scaling factor for an
8604 index register. */
a724f0f4
JB		 8605 if (cur_token.code == '*')
8606 {
8607 if (intel_match_token ('*') && cur_token.code == T_REG)
8608 {
8609 const reg_entry *reg = cur_token.reg;
8610
8611 if (!intel_parser.in_bracket)
8612 {
4eed87de
AM		 8613 as_bad (_("Register scaling only allowed "
8614 "in memory operands"));
a724f0f4
JB		 8615 return 0;
8616 }
8617
4eed87de
AM		 8618 /* Disallow things like [1*si].
8619 sp and esp are invalid as index. */
40fb9820 8620 if (reg->reg_type.bitfield.reg16)
4eed87de 8621 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8622 else if (i.index_reg)
4eed87de 8623 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8624
8625 /* The constant is followed by `* reg', so it must be
8626 a valid scale. */
8627 i.index_reg = reg;
40fb9820 8628 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8629
8630 /* Set the scale after setting the register (otherwise,
8631 i386_scale will complain) */
8632 if (!i386_scale (save_str))
64a0c779 8633 return 0;
a724f0f4
JB		 8634 intel_match_token (T_REG);
8635
8636 /* Since registers are not part of the displacement
8637 string, we may need to remove any preceding '+' from
8638 the displacement string. */
8639 if (*intel_parser.disp != '\0')
8640 {
8641 char *s = intel_parser.disp;
8642 s += strlen (s) - 1;
8643 if (*s == '+')
8644 *s = '\0';
8645 }
8646
8647 free (save_str);
8648
8649 return 1;
8650 }
64a0c779 8651
a724f0f4
JB		 8652 /* The constant was not used for register scaling. Since we have
8653 already consumed the token following `*' we now need to put it
8654 back in the stream. */
64a0c779 8655 intel_putback_token ();
a724f0f4 8656 }
64a0c779 8657
a724f0f4
JB		 8658 /* Add the constant to the displacement string. */
8659 strcat (intel_parser.disp, save_str);
8660 free (save_str);
64a0c779 8661
a724f0f4
JB		 8662 return 1;
8663 }
64a0c779
DN		 8664 }
8665
64a0c779
DN		 8666 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8667 return 0;
8668}
8669
64a0c779
DN		 8670/* Match the given token against cur_token. If they match, read the next
8671 token from the operand string. */
8672static int
e3bb37b5 8673intel_match_token (int code)
64a0c779
DN		 8674{
8675 if (cur_token.code == code)
8676 {
8677 intel_get_token ();
8678 return 1;
8679 }
8680 else
8681 {
0477af35 8682 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 8683 return 0;
8684 }
8685}
8686
64a0c779
DN		 8687/* Read a new token from intel_parser.op_string and store it in cur_token. */
8688static void
e3bb37b5 8689intel_get_token (void)
64a0c779
DN		 8690{
8691 char *end_op;
8692 const reg_entry *reg;
8693 struct intel_token new_token;
8694
8695 new_token.code = T_NIL;
8696 new_token.reg = NULL;
8697 new_token.str = NULL;
8698
4a1805b1 8699 /* Free the memory allocated to the previous token and move
64a0c779
DN		 8700 cur_token to prev_token. */
8701 if (prev_token.str)
8702 free (prev_token.str);
8703
8704 prev_token = cur_token;
8705
8706 /* Skip whitespace. */
8707 while (is_space_char (*intel_parser.op_string))
8708 intel_parser.op_string++;
8709
8710 /* Return an empty token if we find nothing else on the line. */
8711 if (*intel_parser.op_string == '\0')
8712 {
8713 cur_token = new_token;
8714 return;
8715 }
8716
8717 /* The new token cannot be larger than the remainder of the operand
8718 string. */
a724f0f4 8719 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 8720 new_token.str[0] = '\0';
8721
8722 if (strchr ("0123456789", *intel_parser.op_string))
8723 {
8724 char *p = new_token.str;
8725 char *q = intel_parser.op_string;
8726 new_token.code = T_CONST;
8727
8728 /* Allow any kind of identifier char to encompass floating point and
8729 hexadecimal numbers. */
8730 while (is_identifier_char (*q))
8731 *p++ = *q++;
8732 *p = '\0';
8733
8734 /* Recognize special symbol names [0-9][bf]. */
8735 if (strlen (intel_parser.op_string) == 2
4a1805b1 8736 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 8737 || intel_parser.op_string[1] == 'f'))
8738 new_token.code = T_ID;
8739 }
8740
4d1bb795 8741 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 8742 {
4d1bb795
JB		 8743 size_t len = end_op - intel_parser.op_string;
8744
64a0c779
DN		 8745 new_token.code = T_REG;
8746 new_token.reg = reg;
8747
4d1bb795
JB		 8748 memcpy (new_token.str, intel_parser.op_string, len);
8749 new_token.str[len] = '\0';
64a0c779
DN		 8750 }
8751
8752 else if (is_identifier_char (*intel_parser.op_string))
8753 {
8754 char *p = new_token.str;
8755 char *q = intel_parser.op_string;
8756
8757 /* A '.' or '$' followed by an identifier char is an identifier.
8758 Otherwise, it's operator '.' followed by an expression. */
8759 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8760 {
9306ca4a
JB		 8761 new_token.code = '.';
8762 new_token.str[0] = '.';
64a0c779
DN		 8763 new_token.str[1] = '\0';
8764 }
8765 else
8766 {
8767 while (is_identifier_char (*q) || *q == '@')
8768 *p++ = *q++;
8769 *p = '\0';
8770
9306ca4a
JB		 8771 if (strcasecmp (new_token.str, "NOT") == 0)
8772 new_token.code = '~';
8773
8774 else if (strcasecmp (new_token.str, "MOD") == 0)
8775 new_token.code = '%';
8776
8777 else if (strcasecmp (new_token.str, "AND") == 0)
8778 new_token.code = '&';
8779
8780 else if (strcasecmp (new_token.str, "OR") == 0)
8781 new_token.code = '|';
8782
8783 else if (strcasecmp (new_token.str, "XOR") == 0)
8784 new_token.code = '^';
8785
8786 else if (strcasecmp (new_token.str, "SHL") == 0)
8787 new_token.code = T_SHL;
8788
8789 else if (strcasecmp (new_token.str, "SHR") == 0)
8790 new_token.code = T_SHR;
8791
8792 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 8793 new_token.code = T_BYTE;
8794
8795 else if (strcasecmp (new_token.str, "WORD") == 0)
8796 new_token.code = T_WORD;
8797
8798 else if (strcasecmp (new_token.str, "DWORD") == 0)
8799 new_token.code = T_DWORD;
8800
9306ca4a
JB		 8801 else if (strcasecmp (new_token.str, "FWORD") == 0)
8802 new_token.code = T_FWORD;
8803
64a0c779
DN		 8804 else if (strcasecmp (new_token.str, "QWORD") == 0)
8805 new_token.code = T_QWORD;
8806
9306ca4a
JB		 8807 else if (strcasecmp (new_token.str, "TBYTE") == 0
8808 /* XXX remove (gcc still uses it) */
8809 || strcasecmp (new_token.str, "XWORD") == 0)
8810 new_token.code = T_TBYTE;
8811
8812 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8813 || strcasecmp (new_token.str, "OWORD") == 0)
8814 new_token.code = T_XMMWORD;
64a0c779
DN		 8815
8816 else if (strcasecmp (new_token.str, "PTR") == 0)
8817 new_token.code = T_PTR;
8818
8819 else if (strcasecmp (new_token.str, "SHORT") == 0)
8820 new_token.code = T_SHORT;
8821
8822 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8823 {
8824 new_token.code = T_OFFSET;
8825
8826 /* ??? This is not mentioned in the MASM grammar but gcc
8827 makes use of it with -mintel-syntax. OFFSET may be
8828 followed by FLAT: */
8829 if (strncasecmp (q, " FLAT:", 6) == 0)
8830 strcat (new_token.str, " FLAT:");
8831 }
8832
8833 /* ??? This is not mentioned in the MASM grammar. */
8834 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 8835 {
8836 new_token.code = T_OFFSET;
8837 if (*q == ':')
8838 strcat (new_token.str, ":");
8839 else
8840 as_bad (_("`:' expected"));
8841 }
64a0c779
DN		 8842
8843 else
8844 new_token.code = T_ID;
8845 }
8846 }
8847
9306ca4a
JB		 8848 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8849 {
8850 new_token.code = *intel_parser.op_string;
8851 new_token.str[0] = *intel_parser.op_string;
8852 new_token.str[1] = '\0';
8853 }
8854
8855 else if (strchr ("<>", *intel_parser.op_string)
8856 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8857 {
8858 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8859 new_token.str[0] = *intel_parser.op_string;
8860 new_token.str[1] = *intel_parser.op_string;
8861 new_token.str[2] = '\0';
8862 }
8863
64a0c779 8864 else
0477af35 8865 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 8866
8867 intel_parser.op_string += strlen (new_token.str);
8868 cur_token = new_token;
8869}
8870
64a0c779
DN		 8871/* Put cur_token back into the token stream and make cur_token point to
8872 prev_token. */
8873static void
e3bb37b5 8874intel_putback_token (void)
64a0c779 8875{
a724f0f4
JB		 8876 if (cur_token.code != T_NIL)
8877 {
8878 intel_parser.op_string -= strlen (cur_token.str);
8879 free (cur_token.str);
8880 }
64a0c779 8881 cur_token = prev_token;
4a1805b1 8882
64a0c779
DN		 8883 /* Forget prev_token. */
8884 prev_token.code = T_NIL;
8885 prev_token.reg = NULL;
8886 prev_token.str = NULL;
8887}
54cfded0 8888
a4447b93 8889int
1df69f4f 8890tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 8891{
8892 unsigned int regnum;
8893 unsigned int regnames_count;
089dfecd 8894 static const char *const regnames_32[] =
54cfded0 8895 {
a4447b93
RH		 8896 "eax", "ecx", "edx", "ebx",
8897 "esp", "ebp", "esi", "edi",
089dfecd
JB		 8898 "eip", "eflags", NULL,
8899 "st0", "st1", "st2", "st3",
8900 "st4", "st5", "st6", "st7",
8901 NULL, NULL,
8902 "xmm0", "xmm1", "xmm2", "xmm3",
8903 "xmm4", "xmm5", "xmm6", "xmm7",
8904 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8905 "mm4", "mm5", "mm6", "mm7",
8906 "fcw", "fsw", "mxcsr",
8907 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8908 "tr", "ldtr"
54cfded0 8909 };
089dfecd 8910 static const char *const regnames_64[] =
54cfded0 8911 {
089dfecd
JB		 8912 "rax", "rdx", "rcx", "rbx",
8913 "rsi", "rdi", "rbp", "rsp",
8914 "r8", "r9", "r10", "r11",
54cfded0 8915 "r12", "r13", "r14", "r15",
089dfecd
JB		 8916 "rip",
8917 "xmm0", "xmm1", "xmm2", "xmm3",
8918 "xmm4", "xmm5", "xmm6", "xmm7",
8919 "xmm8", "xmm9", "xmm10", "xmm11",
8920 "xmm12", "xmm13", "xmm14", "xmm15",
8921 "st0", "st1", "st2", "st3",
8922 "st4", "st5", "st6", "st7",
8923 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8924 "mm4", "mm5", "mm6", "mm7",
8925 "rflags",
8926 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8927 "fs.base", "gs.base", NULL, NULL,
8928 "tr", "ldtr",
8929 "mxcsr", "fcw", "fsw"
54cfded0 8930 };
089dfecd 8931 const char *const *regnames;
54cfded0
AM		 8932
8933 if (flag_code == CODE_64BIT)
8934 {
8935 regnames = regnames_64;
0cea6190 8936 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 8937 }
8938 else
8939 {
8940 regnames = regnames_32;
0cea6190 8941 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 8942 }
8943
8944 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 8945 if (regnames[regnum] != NULL
8946 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 8947 return regnum;
8948
54cfded0
AM		 8949 return -1;
8950}
8951
8952void
8953tc_x86_frame_initial_instructions (void)
8954{
a4447b93
RH		 8955 static unsigned int sp_regno;
8956
8957 if (!sp_regno)
8958 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8959 ? "rsp" : "esp");
8960
8961 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8962 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8963}
d2b2c203
DJ		 8964
8965int
8966i386_elf_section_type (const char *str, size_t len)
8967{
8968 if (flag_code == CODE_64BIT
8969 && len == sizeof ("unwind") - 1
8970 && strncmp (str, "unwind", 6) == 0)
8971 return SHT_X86_64_UNWIND;
8972
8973 return -1;
8974}
bb41ade5
AM		 8975
8976#ifdef TE_PE
8977void
8978tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8979{
8980 expressionS expr;
8981
8982 expr.X_op = O_secrel;
8983 expr.X_add_symbol = symbol;
8984 expr.X_add_number = 0;
8985 emit_expr (&expr, size);
8986}
8987#endif
3b22753a
L		 8988
8989#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8990/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8991
8992int
8993x86_64_section_letter (int letter, char **ptr_msg)
8994{
8995 if (flag_code == CODE_64BIT)
8996 {
8997 if (letter == 'l')
8998 return SHF_X86_64_LARGE;
8999
9000 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9001 }
3b22753a 9002 else
64e74474 9003 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9004 return -1;
9005}
9006
9007int
9008x86_64_section_word (char *str, size_t len)
9009{
8620418b 9010 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9011 return SHF_X86_64_LARGE;
9012
9013 return -1;
9014}
9015
9016static void
9017handle_large_common (int small ATTRIBUTE_UNUSED)
9018{
9019 if (flag_code != CODE_64BIT)
9020 {
9021 s_comm_internal (0, elf_common_parse);
9022 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9023 }
9024 else
9025 {
9026 static segT lbss_section;
9027 asection *saved_com_section_ptr = elf_com_section_ptr;
9028 asection *saved_bss_section = bss_section;
9029
9030 if (lbss_section == NULL)
9031 {
9032 flagword applicable;
9033 segT seg = now_seg;
9034 subsegT subseg = now_subseg;
9035
9036 /* The .lbss section is for local .largecomm symbols. */
9037 lbss_section = subseg_new (".lbss", 0);
9038 applicable = bfd_applicable_section_flags (stdoutput);
9039 bfd_set_section_flags (stdoutput, lbss_section,
9040 applicable & SEC_ALLOC);
9041 seg_info (lbss_section)->bss = 1;
9042
9043 subseg_set (seg, subseg);
9044 }
9045
9046 elf_com_section_ptr = &_bfd_elf_large_com_section;
9047 bss_section = lbss_section;
9048
9049 s_comm_internal (0, elf_common_parse);
9050
9051 elf_com_section_ptr = saved_com_section_ptr;
9052 bss_section = saved_bss_section;
9053 }
9054}
9055#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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