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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
0b1cf022 35#include "opcodes/i386-opc.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
e3bb37b5
L		 66static void set_code_flag (int);
67static void set_16bit_gcc_code_flag (int);
68static void set_intel_syntax (int);
69static void set_cpu_arch (int);
6482c264 70#ifdef TE_PE
e3bb37b5 71static void pe_directive_secrel (int);
6482c264 72#endif
e3bb37b5
L		 73static void signed_cons (int);
74static char *output_invalid (int c);
75static int i386_operand (char *);
76static int i386_intel_operand (char *, int);
77static const reg_entry *parse_register (char *, char **);
78static char *parse_insn (char *, char *);
79static char *parse_operands (char *, const char *);
80static void swap_operands (void);
4d456e3d 81static void swap_2_operands (int, int);
e3bb37b5
L		 82static void optimize_imm (void);
83static void optimize_disp (void);
84static int match_template (void);
85static int check_string (void);
86static int process_suffix (void);
87static int check_byte_reg (void);
88static int check_long_reg (void);
89static int check_qword_reg (void);
90static int check_word_reg (void);
91static int finalize_imm (void);
92static int process_operands (void);
93static const seg_entry *build_modrm_byte (void);
94static void output_insn (void);
95static void output_imm (fragS *, offsetT);
96static void output_disp (fragS *, offsetT);
29b0f896 97#ifndef I386COFF
e3bb37b5 98static void s_bss (int);
252b5132 99#endif
17d4e2a2
L		 100#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
101static void handle_large_common (int small ATTRIBUTE_UNUSED);
102#endif
252b5132 103
a847613f 104static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 105
252b5132 106/* 'md_assemble ()' gathers together information and puts it into a
47926f60 107 i386_insn. */
252b5132 108
520dc8e8
AM		 109union i386_op
110 {
111 expressionS *disps;
112 expressionS *imms;
113 const reg_entry *regs;
114 };
115
252b5132
RH		 116struct _i386_insn
117 {
47926f60 118 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 119 template tm;
120
121 /* SUFFIX holds the instruction mnemonic suffix if given.
122 (e.g. 'l' for 'movl') */
123 char suffix;
124
47926f60 125 /* OPERANDS gives the number of given operands. */
252b5132
RH		 126 unsigned int operands;
127
128 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
129 of given register, displacement, memory operands and immediate
47926f60 130 operands. */
252b5132
RH		 131 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
132
133 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 134 use OP[i] for the corresponding operand. */
252b5132
RH		 135 unsigned int types[MAX_OPERANDS];
136
520dc8e8
AM		 137 /* Displacement expression, immediate expression, or register for each
138 operand. */
139 union i386_op op[MAX_OPERANDS];
252b5132 140
3e73aa7c
JH		 141 /* Flags for operands. */
142 unsigned int flags[MAX_OPERANDS];
143#define Operand_PCrel 1
144
252b5132 145 /* Relocation type for operand */
f86103b7 146 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 147
252b5132
RH		 148 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
149 the base index byte below. */
150 const reg_entry *base_reg;
151 const reg_entry *index_reg;
152 unsigned int log2_scale_factor;
153
154 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 155 explicit segment overrides are given. */
ce8a8b2f 156 const seg_entry *seg[2];
252b5132
RH		 157
158 /* PREFIX holds all the given prefix opcodes (usually null).
159 PREFIXES is the number of prefix opcodes. */
160 unsigned int prefixes;
161 unsigned char prefix[MAX_PREFIXES];
162
163 /* RM and SIB are the modrm byte and the sib byte where the
164 addressing modes of this insn are encoded. */
165
166 modrm_byte rm;
3e73aa7c 167 rex_byte rex;
252b5132
RH		 168 sib_byte sib;
169 };
170
171typedef struct _i386_insn i386_insn;
172
173/* List of chars besides those in app.c:symbol_chars that can start an
174 operand. Used to prevent the scrubber eating vital white-space. */
32137342 175const char extra_symbol_chars[] = "*%-(["
252b5132 176#ifdef LEX_AT
32137342
NC		 177 "@"
178#endif
179#ifdef LEX_QM
180 "?"
252b5132 181#endif
32137342 182 ;
252b5132 183
29b0f896
AM		 184#if (defined (TE_I386AIX) \
185 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 186 && !defined (TE_GNU) \
29b0f896 187 && !defined (TE_LINUX) \
32137342 188 && !defined (TE_NETWARE) \
29b0f896
AM		 189 && !defined (TE_FreeBSD) \
190 && !defined (TE_NetBSD)))
252b5132 191/* This array holds the chars that always start a comment. If the
b3b91714
AM		 192 pre-processor is disabled, these aren't very useful. The option
193 --divide will remove '/' from this list. */
194const char *i386_comment_chars = "#/";
195#define SVR4_COMMENT_CHARS 1
252b5132 196#define PREFIX_SEPARATOR '\\'
252b5132 197
b3b91714
AM		 198#else
199const char *i386_comment_chars = "#";
200#define PREFIX_SEPARATOR '/'
201#endif
202
252b5132
RH		 203/* This array holds the chars that only start a comment at the beginning of
204 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 205 .line and .file directives will appear in the pre-processed output.
206 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 207 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 208 #NO_APP at the beginning of its output.
209 Also note that comments started like this one will always work if
252b5132 210 '/' isn't otherwise defined. */
b3b91714 211const char line_comment_chars[] = "#/";
252b5132 212
63a0b638 213const char line_separator_chars[] = ";";
252b5132 214
ce8a8b2f
AM		 215/* Chars that can be used to separate mant from exp in floating point
216 nums. */
252b5132
RH		 217const char EXP_CHARS[] = "eE";
218
ce8a8b2f
AM		 219/* Chars that mean this number is a floating point constant
220 As in 0f12.456
221 or 0d1.2345e12. */
252b5132
RH		 222const char FLT_CHARS[] = "fFdDxX";
223
ce8a8b2f 224/* Tables for lexical analysis. */
252b5132
RH		 225static char mnemonic_chars[256];
226static char register_chars[256];
227static char operand_chars[256];
228static char identifier_chars[256];
229static char digit_chars[256];
230
ce8a8b2f 231/* Lexical macros. */
252b5132
RH		 232#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
233#define is_operand_char(x) (operand_chars[(unsigned char) x])
234#define is_register_char(x) (register_chars[(unsigned char) x])
235#define is_space_char(x) ((x) == ' ')
236#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
237#define is_digit_char(x) (digit_chars[(unsigned char) x])
238
0234cb7c 239/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 240static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
241
242/* md_assemble() always leaves the strings it's passed unaltered. To
243 effect this we maintain a stack of saved characters that we've smashed
244 with '\0's (indicating end of strings for various sub-fields of the
47926f60 245 assembler instruction). */
252b5132 246static char save_stack[32];
ce8a8b2f 247static char *save_stack_p;
252b5132
RH		 248#define END_STRING_AND_SAVE(s) \
249 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
250#define RESTORE_END_STRING(s) \
251 do { *(s) = *--save_stack_p; } while (0)
252
47926f60 253/* The instruction we're assembling. */
252b5132
RH		 254static i386_insn i;
255
256/* Possible templates for current insn. */
257static const templates *current_templates;
258
31b2323c
L		 259/* Per instruction expressionS buffers: max displacements & immediates. */
260static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
261static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 262
47926f60
KH		 263/* Current operand we are working on. */
264static int this_operand;
252b5132 265
3e73aa7c
JH		 266/* We support four different modes. FLAG_CODE variable is used to distinguish
267 these. */
268
269enum flag_code {
270 CODE_32BIT,
271 CODE_16BIT,
272 CODE_64BIT };
f3c180ae 273#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 274
275static enum flag_code flag_code;
4fa24527 276static unsigned int object_64bit;
3e73aa7c
JH		 277static int use_rela_relocations = 0;
278
279/* The names used to print error messages. */
b77a7acd 280static const char *flag_code_names[] =
3e73aa7c
JH		 281 {
282 "32",
283 "16",
284 "64"
285 };
252b5132 286
47926f60
KH		 287/* 1 for intel syntax,
288 0 if att syntax. */
289static int intel_syntax = 0;
252b5132 290
47926f60
KH		 291/* 1 if register prefix % not required. */
292static int allow_naked_reg = 0;
252b5132 293
2ca3ace5
L		 294/* Register prefix used for error message. */
295static const char *register_prefix = "%";
296
47926f60
KH		 297/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
298 leave, push, and pop instructions so that gcc has the same stack
299 frame as in 32 bit mode. */
300static char stackop_size = '\0';
eecb386c 301
12b55ccc
L		 302/* Non-zero to optimize code alignment. */
303int optimize_align_code = 1;
304
47926f60
KH		 305/* Non-zero to quieten some warnings. */
306static int quiet_warnings = 0;
a38cf1db 307
47926f60
KH		 308/* CPU name. */
309static const char *cpu_arch_name = NULL;
5c6af06e 310static const char *cpu_sub_arch_name = NULL;
a38cf1db 311
47926f60 312/* CPU feature flags. */
29b0f896 313static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 314
ccc9c027
L		 315/* If we have selected a cpu we are generating instructions for. */
316static int cpu_arch_tune_set = 0;
317
9103f4f4
L		 318/* Cpu we are generating instructions for. */
319static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
320
321/* CPU feature flags of cpu we are generating instructions for. */
322static unsigned int cpu_arch_tune_flags = 0;
323
ccc9c027
L		 324/* CPU instruction set architecture used. */
325static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
326
9103f4f4
L		 327/* CPU feature flags of instruction set architecture used. */
328static unsigned int cpu_arch_isa_flags = 0;
329
fddf5b5b
AM		 330/* If set, conditional jumps are not automatically promoted to handle
331 larger than a byte offset. */
332static unsigned int no_cond_jump_promotion = 0;
333
29b0f896 334/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 335static symbolS *GOT_symbol;
29b0f896 336
a4447b93
RH		 337/* The dwarf2 return column, adjusted for 32 or 64 bit. */
338unsigned int x86_dwarf2_return_column;
339
340/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
341int x86_cie_data_alignment;
342
252b5132 343/* Interface to relax_segment.
fddf5b5b
AM		 344 There are 3 major relax states for 386 jump insns because the
345 different types of jumps add different sizes to frags when we're
346 figuring out what sort of jump to choose to reach a given label. */
252b5132 347
47926f60 348/* Types. */
93c2a809
AM		 349#define UNCOND_JUMP 0
350#define COND_JUMP 1
351#define COND_JUMP86 2
fddf5b5b 352
47926f60 353/* Sizes. */
252b5132
RH		 354#define CODE16 1
355#define SMALL 0
29b0f896 356#define SMALL16 (SMALL | CODE16)
252b5132 357#define BIG 2
29b0f896 358#define BIG16 (BIG | CODE16)
252b5132
RH		 359
360#ifndef INLINE
361#ifdef __GNUC__
362#define INLINE __inline__
363#else
364#define INLINE
365#endif
366#endif
367
fddf5b5b
AM		 368#define ENCODE_RELAX_STATE(type, size) \
369 ((relax_substateT) (((type) << 2) | (size)))
370#define TYPE_FROM_RELAX_STATE(s) \
371 ((s) >> 2)
372#define DISP_SIZE_FROM_RELAX_STATE(s) \
373 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 374
375/* This table is used by relax_frag to promote short jumps to long
376 ones where necessary. SMALL (short) jumps may be promoted to BIG
377 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
378 don't allow a short jump in a 32 bit code segment to be promoted to
379 a 16 bit offset jump because it's slower (requires data size
380 prefix), and doesn't work, unless the destination is in the bottom
381 64k of the code segment (The top 16 bits of eip are zeroed). */
382
383const relax_typeS md_relax_table[] =
384{
24eab124
AM		 385 /* The fields are:
386 1) most positive reach of this state,
387 2) most negative reach of this state,
93c2a809 388 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 389 4) which index into the table to try if we can't fit into this one. */
252b5132 390
fddf5b5b 391 /* UNCOND_JUMP states. */
93c2a809
AM		 392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
394 /* dword jmp adds 4 bytes to frag:
395 0 extra opcode bytes, 4 displacement bytes. */
252b5132 396 {0, 0, 4, 0},
93c2a809
AM		 397 /* word jmp adds 2 byte2 to frag:
398 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 399 {0, 0, 2, 0},
400
93c2a809
AM		 401 /* COND_JUMP states. */
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
403 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
404 /* dword conditionals adds 5 bytes to frag:
405 1 extra opcode byte, 4 displacement bytes. */
406 {0, 0, 5, 0},
fddf5b5b 407 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 408 1 extra opcode byte, 2 displacement bytes. */
409 {0, 0, 3, 0},
410
411 /* COND_JUMP86 states. */
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
413 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
414 /* dword conditionals adds 5 bytes to frag:
415 1 extra opcode byte, 4 displacement bytes. */
416 {0, 0, 5, 0},
417 /* word conditionals add 4 bytes to frag:
418 1 displacement byte and a 3 byte long branch insn. */
419 {0, 0, 4, 0}
252b5132
RH		 420};
421
9103f4f4
L		 422static const arch_entry cpu_arch[] =
423{
424 {"generic32", PROCESSOR_GENERIC32,
d32cad65 425 Cpu186|Cpu286|Cpu386},
9103f4f4 426 {"generic64", PROCESSOR_GENERIC64,
d32cad65 427 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 428 |CpuMMX2|CpuSSE|CpuSSE2},
429 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 430 0},
9103f4f4 431 {"i186", PROCESSOR_UNKNOWN,
d32cad65 432 Cpu186},
9103f4f4 433 {"i286", PROCESSOR_UNKNOWN,
d32cad65 434 Cpu186|Cpu286},
9103f4f4 435 {"i386", PROCESSOR_GENERIC32,
d32cad65 436 Cpu186|Cpu286|Cpu386},
9103f4f4 437 {"i486", PROCESSOR_I486,
d32cad65 438 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 439 {"i586", PROCESSOR_PENTIUM,
d32cad65 440 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 441 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 442 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 443 {"pentium", PROCESSOR_PENTIUM,
d32cad65 444 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 445 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 446 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 447 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 448 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 449 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 450 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 451 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 452 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 453 |CpuMMX2|CpuSSE|CpuSSE2},
454 {"prescott", PROCESSOR_NOCONA,
d32cad65 455 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 456 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
457 {"nocona", PROCESSOR_NOCONA,
d32cad65 458 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 459 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 460 {"yonah", PROCESSOR_CORE,
d32cad65 461 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 462 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 463 {"core", PROCESSOR_CORE,
d32cad65 464 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 465 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
466 {"merom", PROCESSOR_CORE2,
467 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
468 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
469 {"core2", PROCESSOR_CORE2,
470 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
471 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 472 {"k6", PROCESSOR_K6,
d32cad65 473 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 474 {"k6_2", PROCESSOR_K6,
d32cad65 475 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 476 {"athlon", PROCESSOR_ATHLON,
d32cad65 477 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 478 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
479 {"sledgehammer", PROCESSOR_K8,
d32cad65 480 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 481 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
482 {"opteron", PROCESSOR_K8,
d32cad65 483 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 484 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
485 {"k8", PROCESSOR_K8,
d32cad65 486 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 487 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 488 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 489 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
490 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
491 |CpuABM},
9103f4f4
L		 492 {".mmx", PROCESSOR_UNKNOWN,
493 CpuMMX},
494 {".sse", PROCESSOR_UNKNOWN,
495 CpuMMX|CpuMMX2|CpuSSE},
496 {".sse2", PROCESSOR_UNKNOWN,
497 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
498 {".sse3", PROCESSOR_UNKNOWN,
499 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 500 {".ssse3", PROCESSOR_UNKNOWN,
501 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4
L		 502 {".3dnow", PROCESSOR_UNKNOWN,
503 CpuMMX|Cpu3dnow},
504 {".3dnowa", PROCESSOR_UNKNOWN,
505 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
506 {".padlock", PROCESSOR_UNKNOWN,
507 CpuPadLock},
508 {".pacifica", PROCESSOR_UNKNOWN,
509 CpuSVME},
510 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 511 CpuSVME},
512 {".sse4a", PROCESSOR_UNKNOWN,
513 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
514 {".abm", PROCESSOR_UNKNOWN,
515 CpuABM}
e413e4e9
AM		 516};
517
29b0f896
AM		 518const pseudo_typeS md_pseudo_table[] =
519{
520#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes, 0},
522#else
523 {"align", s_align_ptwo, 0},
524#endif
525 {"arch", set_cpu_arch, 0},
526#ifndef I386COFF
527 {"bss", s_bss, 0},
528#endif
529 {"ffloat", float_cons, 'f'},
530 {"dfloat", float_cons, 'd'},
531 {"tfloat", float_cons, 'x'},
532 {"value", cons, 2},
d182319b 533 {"slong", signed_cons, 4},
29b0f896
AM		 534 {"noopt", s_ignore, 0},
535 {"optim", s_ignore, 0},
536 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
537 {"code16", set_code_flag, CODE_16BIT},
538 {"code32", set_code_flag, CODE_32BIT},
539 {"code64", set_code_flag, CODE_64BIT},
540 {"intel_syntax", set_intel_syntax, 1},
541 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 542#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
543 {"largecomm", handle_large_common, 0},
07a53e5c 544#else
e3bb37b5 545 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 546 {"loc", dwarf2_directive_loc, 0},
547 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 548#endif
6482c264
NC		 549#ifdef TE_PE
550 {"secrel32", pe_directive_secrel, 0},
551#endif
29b0f896
AM		 552 {0, 0, 0}
553};
554
555/* For interface with expression (). */
556extern char *input_line_pointer;
557
558/* Hash table for instruction mnemonic lookup. */
559static struct hash_control *op_hash;
560
561/* Hash table for register lookup. */
562static struct hash_control *reg_hash;
563\f
252b5132 564void
e3bb37b5 565i386_align_code (fragS *fragP, int count)
252b5132 566{
ce8a8b2f
AM		 567 /* Various efficient no-op patterns for aligning code labels.
568 Note: Don't try to assemble the instructions in the comments.
569 0L and 0w are not legal. */
252b5132
RH		 570 static const char f32_1[] =
571 {0x90}; /* nop */
572 static const char f32_2[] =
ccc9c027 573 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 574 static const char f32_3[] =
575 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
576 static const char f32_4[] =
577 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
578 static const char f32_5[] =
579 {0x90, /* nop */
580 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
581 static const char f32_6[] =
582 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
583 static const char f32_7[] =
584 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
585 static const char f32_8[] =
586 {0x90, /* nop */
587 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
588 static const char f32_9[] =
589 {0x89,0xf6, /* movl %esi,%esi */
590 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
591 static const char f32_10[] =
592 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
593 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
594 static const char f32_11[] =
595 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
596 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
597 static const char f32_12[] =
598 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
599 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
600 static const char f32_13[] =
601 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_14[] =
604 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
605 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
606 static const char f32_15[] =
607 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
608 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 609 static const char f16_3[] =
610 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 611 static const char f16_4[] =
612 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
613 static const char f16_5[] =
614 {0x90, /* nop */
615 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
616 static const char f16_6[] =
617 {0x89,0xf6, /* mov %si,%si */
618 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
619 static const char f16_7[] =
620 {0x8d,0x74,0x00, /* lea 0(%si),%si */
621 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
622 static const char f16_8[] =
623 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
624 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
625 static const char *const f32_patt[] = {
626 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
627 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
628 };
629 static const char *const f16_patt[] = {
c3332e24 630 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 631 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
632 };
ccc9c027
L		 633 /* nopl (%[re]ax) */
634 static const char alt_3[] =
635 {0x0f,0x1f,0x00};
636 /* nopl 0(%[re]ax) */
637 static const char alt_4[] =
638 {0x0f,0x1f,0x40,0x00};
639 /* nopl 0(%[re]ax,%[re]ax,1) */
640 static const char alt_5[] =
641 {0x0f,0x1f,0x44,0x00,0x00};
642 /* nopw 0(%[re]ax,%[re]ax,1) */
643 static const char alt_6[] =
644 {0x66,0x0f,0x1f,0x44,0x00,0x00};
645 /* nopl 0L(%[re]ax) */
646 static const char alt_7[] =
647 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
648 /* nopl 0L(%[re]ax,%[re]ax,1) */
649 static const char alt_8[] =
650 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
651 /* nopw 0L(%[re]ax,%[re]ax,1) */
652 static const char alt_9[] =
653 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
654 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
655 static const char alt_10[] =
656 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
657 /* data16
658 nopw %cs:0L(%[re]ax,%[re]ax,1) */
659 static const char alt_long_11[] =
660 {0x66,
661 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
662 /* data16
663 data16
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_12[] =
666 {0x66,
667 0x66,
668 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
669 /* data16
670 data16
671 data16
672 nopw %cs:0L(%[re]ax,%[re]ax,1) */
673 static const char alt_long_13[] =
674 {0x66,
675 0x66,
676 0x66,
677 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
678 /* data16
679 data16
680 data16
681 data16
682 nopw %cs:0L(%[re]ax,%[re]ax,1) */
683 static const char alt_long_14[] =
684 {0x66,
685 0x66,
686 0x66,
687 0x66,
688 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
689 /* data16
690 data16
691 data16
692 data16
693 data16
694 nopw %cs:0L(%[re]ax,%[re]ax,1) */
695 static const char alt_long_15[] =
696 {0x66,
697 0x66,
698 0x66,
699 0x66,
700 0x66,
701 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
702 /* nopl 0(%[re]ax,%[re]ax,1)
703 nopw 0(%[re]ax,%[re]ax,1) */
704 static const char alt_short_11[] =
705 {0x0f,0x1f,0x44,0x00,0x00,
706 0x66,0x0f,0x1f,0x44,0x00,0x00};
707 /* nopw 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_12[] =
710 {0x66,0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopl 0L(%[re]ax) */
714 static const char alt_short_13[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
717 /* nopl 0L(%[re]ax)
718 nopl 0L(%[re]ax) */
719 static const char alt_short_14[] =
720 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
722 /* nopl 0L(%[re]ax)
723 nopl 0L(%[re]ax,%[re]ax,1) */
724 static const char alt_short_15[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
727 static const char *const alt_short_patt[] = {
728 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
729 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
730 alt_short_14, alt_short_15
731 };
732 static const char *const alt_long_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
735 alt_long_14, alt_long_15
736 };
252b5132 737
33fef721
JH		 738 if (count <= 0 || count > 15)
739 return;
3e73aa7c 740
ccc9c027
L		 741 /* We need to decide which NOP sequence to use for 32bit and
742 64bit. When -mtune= is used:
4eed87de 743
ccc9c027
L		 744 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
745 f32_patt will be used.
4eed87de
AM		 746 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
747 0x66 prefix will be used.
ef05d495 748 3. For PROCESSOR_CORE2, alt_long_patt will be used.
ccc9c027 749 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
ef05d495 750 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
ccc9c027
L		 751 and PROCESSOR_GENERIC64, alt_short_patt will be used.
752
753 When -mtune= isn't used, alt_short_patt will be used if
754 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
755
756 When -march= or .arch is used, we can't use anything beyond
757 cpu_arch_isa_flags. */
758
759 if (flag_code == CODE_16BIT)
760 {
761 memcpy (fragP->fr_literal + fragP->fr_fix,
762 f16_patt[count - 1], count);
763 if (count > 8)
764 /* Adjust jump offset. */
765 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
766 }
767 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 768 {
33fef721
JH		 769 int i;
770 int nnops = (count + 3) / 4;
771 int len = count / nnops;
772 int remains = count - nnops * len;
773 int pos = 0;
774
ccc9c027 775 /* The recommended way to pad 64bit code is to use NOPs preceded
4eed87de 776 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 777 for (i = 0; i < remains; i++)
252b5132 778 {
33fef721
JH		 779 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
780 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
781 pos += len + 1;
782 }
783 for (; i < nnops; i++)
784 {
785 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
786 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
787 pos += len;
252b5132 788 }
252b5132 789 }
33fef721 790 else
ccc9c027
L		 791 {
792 const char *const *patt = NULL;
793
794 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
795 {
796 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
797 switch (cpu_arch_tune)
798 {
799 case PROCESSOR_UNKNOWN:
800 /* We use cpu_arch_isa_flags to check if we SHOULD
801 optimize for Cpu686. */
802 if ((cpu_arch_isa_flags & Cpu686) != 0)
803 patt = alt_short_patt;
804 else
805 patt = f32_patt;
806 break;
ef05d495 807 case PROCESSOR_CORE2:
ccc9c027
L		 808 patt = alt_long_patt;
809 break;
810 case PROCESSOR_PENTIUMPRO:
811 case PROCESSOR_PENTIUM4:
812 case PROCESSOR_NOCONA:
ef05d495 813 case PROCESSOR_CORE:
ccc9c027
L		 814 case PROCESSOR_K6:
815 case PROCESSOR_ATHLON:
816 case PROCESSOR_K8:
817 case PROCESSOR_GENERIC64:
4eed87de 818 case PROCESSOR_AMDFAM10:
ccc9c027
L		 819 patt = alt_short_patt;
820 break;
821 case PROCESSOR_I486:
822 case PROCESSOR_PENTIUM:
823 case PROCESSOR_GENERIC32:
824 patt = f32_patt;
825 break;
4eed87de 826 }
ccc9c027
L		 827 }
828 else
829 {
830 switch (cpu_arch_tune)
831 {
832 case PROCESSOR_UNKNOWN:
833 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
834 PROCESSOR_UNKNOWN. */
835 abort ();
836 break;
837
838 case PROCESSOR_I486:
839 case PROCESSOR_PENTIUM:
840 case PROCESSOR_PENTIUMPRO:
841 case PROCESSOR_PENTIUM4:
842 case PROCESSOR_NOCONA:
ef05d495 843 case PROCESSOR_CORE:
ccc9c027
L		 844 case PROCESSOR_K6:
845 case PROCESSOR_ATHLON:
846 case PROCESSOR_K8:
4eed87de 847 case PROCESSOR_AMDFAM10:
ccc9c027
L		 848 case PROCESSOR_GENERIC32:
849 /* We use cpu_arch_isa_flags to check if we CAN optimize
850 for Cpu686. */
851 if ((cpu_arch_isa_flags & Cpu686) != 0)
852 patt = alt_short_patt;
853 else
854 patt = f32_patt;
855 break;
ef05d495 856 case PROCESSOR_CORE2:
ccc9c027
L		 857 if ((cpu_arch_isa_flags & Cpu686) != 0)
858 patt = alt_long_patt;
859 else
860 patt = f32_patt;
861 break;
862 case PROCESSOR_GENERIC64:
863 patt = alt_short_patt;
864 break;
4eed87de 865 }
ccc9c027
L		 866 }
867
33fef721 868 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 869 patt[count - 1], count);
870 }
33fef721 871 fragP->fr_var = count;
252b5132
RH		 872}
873
252b5132 874static INLINE unsigned int
e3bb37b5 875mode_from_disp_size (unsigned int t)
252b5132 876{
3e73aa7c 877 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 878}
879
880static INLINE int
e3bb37b5 881fits_in_signed_byte (offsetT num)
252b5132
RH		 882{
883 return (num >= -128) && (num <= 127);
47926f60 884}
252b5132
RH		 885
886static INLINE int
e3bb37b5 887fits_in_unsigned_byte (offsetT num)
252b5132
RH		 888{
889 return (num & 0xff) == num;
47926f60 890}
252b5132
RH		 891
892static INLINE int
e3bb37b5 893fits_in_unsigned_word (offsetT num)
252b5132
RH		 894{
895 return (num & 0xffff) == num;
47926f60 896}
252b5132
RH		 897
898static INLINE int
e3bb37b5 899fits_in_signed_word (offsetT num)
252b5132
RH		 900{
901 return (-32768 <= num) && (num <= 32767);
47926f60 902}
2a962e6d 903
3e73aa7c 904static INLINE int
e3bb37b5 905fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 906{
907#ifndef BFD64
908 return 1;
909#else
910 return (!(((offsetT) -1 << 31) & num)
911 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
912#endif
913} /* fits_in_signed_long() */
2a962e6d 914
3e73aa7c 915static INLINE int
e3bb37b5 916fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 917{
918#ifndef BFD64
919 return 1;
920#else
921 return (num & (((offsetT) 2 << 31) - 1)) == num;
922#endif
923} /* fits_in_unsigned_long() */
252b5132 924
1509aa9a 925static unsigned int
e3bb37b5 926smallest_imm_type (offsetT num)
252b5132 927{
d32cad65 928 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 929 {
930 /* This code is disabled on the 486 because all the Imm1 forms
931 in the opcode table are slower on the i486. They're the
932 versions with the implicitly specified single-position
933 displacement, which has another syntax if you really want to
934 use that form. */
935 if (num == 1)
3e73aa7c 936 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 937 }
252b5132 938 return (fits_in_signed_byte (num)
3e73aa7c 939 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 940 : fits_in_unsigned_byte (num)
3e73aa7c 941 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 942 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 943 ? (Imm16 | Imm32 | Imm32S | Imm64)
944 : fits_in_signed_long (num)
945 ? (Imm32 | Imm32S | Imm64)
946 : fits_in_unsigned_long (num)
947 ? (Imm32 | Imm64)
948 : Imm64);
47926f60 949}
252b5132 950
847f7ad4 951static offsetT
e3bb37b5 952offset_in_range (offsetT val, int size)
847f7ad4 953{
508866be 954 addressT mask;
ba2adb93 955
847f7ad4
AM		 956 switch (size)
957 {
508866be
L		 958 case 1: mask = ((addressT) 1 << 8) - 1; break;
959 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 960 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 961#ifdef BFD64
962 case 8: mask = ((addressT) 2 << 63) - 1; break;
963#endif
47926f60 964 default: abort ();
847f7ad4
AM		 965 }
966
ba2adb93 967 /* If BFD64, sign extend val. */
3e73aa7c
JH		 968 if (!use_rela_relocations)
969 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
970 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 971
47926f60 972 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 973 {
974 char buf1[40], buf2[40];
975
976 sprint_value (buf1, val);
977 sprint_value (buf2, val & mask);
978 as_warn (_("%s shortened to %s"), buf1, buf2);
979 }
980 return val & mask;
981}
982
252b5132
RH		 983/* Returns 0 if attempting to add a prefix where one from the same
984 class already exists, 1 if non rep/repne added, 2 if rep/repne
985 added. */
986static int
e3bb37b5 987add_prefix (unsigned int prefix)
252b5132
RH		 988{
989 int ret = 1;
b1905489 990 unsigned int q;
252b5132 991
29b0f896
AM		 992 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
993 && flag_code == CODE_64BIT)
b1905489
JB		 994 {
995 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
996 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
997 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
998 ret = 0;
999 q = REX_PREFIX;
1000 }
3e73aa7c 1001 else
b1905489
JB		 1002 {
1003 switch (prefix)
1004 {
1005 default:
1006 abort ();
1007
1008 case CS_PREFIX_OPCODE:
1009 case DS_PREFIX_OPCODE:
1010 case ES_PREFIX_OPCODE:
1011 case FS_PREFIX_OPCODE:
1012 case GS_PREFIX_OPCODE:
1013 case SS_PREFIX_OPCODE:
1014 q = SEG_PREFIX;
1015 break;
1016
1017 case REPNE_PREFIX_OPCODE:
1018 case REPE_PREFIX_OPCODE:
1019 ret = 2;
1020 /* fall thru */
1021 case LOCK_PREFIX_OPCODE:
1022 q = LOCKREP_PREFIX;
1023 break;
1024
1025 case FWAIT_OPCODE:
1026 q = WAIT_PREFIX;
1027 break;
1028
1029 case ADDR_PREFIX_OPCODE:
1030 q = ADDR_PREFIX;
1031 break;
1032
1033 case DATA_PREFIX_OPCODE:
1034 q = DATA_PREFIX;
1035 break;
1036 }
1037 if (i.prefix[q] != 0)
1038 ret = 0;
1039 }
252b5132 1040
b1905489 1041 if (ret)
252b5132 1042 {
b1905489
JB		 1043 if (!i.prefix[q])
1044 ++i.prefixes;
1045 i.prefix[q] |= prefix;
252b5132 1046 }
b1905489
JB		 1047 else
1048 as_bad (_("same type of prefix used twice"));
252b5132 1049
252b5132
RH		 1050 return ret;
1051}
1052
1053static void
e3bb37b5 1054set_code_flag (int value)
eecb386c 1055{
3e73aa7c
JH		 1056 flag_code = value;
1057 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1058 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1059 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1060 {
1061 as_bad (_("64bit mode not supported on this CPU."));
1062 }
1063 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1064 {
1065 as_bad (_("32bit mode not supported on this CPU."));
1066 }
eecb386c
AM		 1067 stackop_size = '\0';
1068}
1069
1070static void
e3bb37b5 1071set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1072{
3e73aa7c
JH		 1073 flag_code = new_code_flag;
1074 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1075 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1076 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1077}
1078
1079static void
e3bb37b5 1080set_intel_syntax (int syntax_flag)
252b5132
RH		 1081{
1082 /* Find out if register prefixing is specified. */
1083 int ask_naked_reg = 0;
1084
1085 SKIP_WHITESPACE ();
29b0f896 1086 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1087 {
1088 char *string = input_line_pointer;
1089 int e = get_symbol_end ();
1090
47926f60 1091 if (strcmp (string, "prefix") == 0)
252b5132 1092 ask_naked_reg = 1;
47926f60 1093 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1094 ask_naked_reg = -1;
1095 else
d0b47220 1096 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1097 *input_line_pointer = e;
1098 }
1099 demand_empty_rest_of_line ();
c3332e24 1100
252b5132
RH		 1101 intel_syntax = syntax_flag;
1102
1103 if (ask_naked_reg == 0)
f86103b7
AM		 1104 allow_naked_reg = (intel_syntax
1105 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1106 else
1107 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1108
e4a3b5a4 1109 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1110 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1111 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1112}
1113
e413e4e9 1114static void
e3bb37b5 1115set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1116{
47926f60 1117 SKIP_WHITESPACE ();
e413e4e9 1118
29b0f896 1119 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1120 {
1121 char *string = input_line_pointer;
1122 int e = get_symbol_end ();
9103f4f4 1123 unsigned int i;
e413e4e9 1124
9103f4f4 1125 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1126 {
1127 if (strcmp (string, cpu_arch[i].name) == 0)
1128 {
5c6af06e
JB		 1129 if (*string != '.')
1130 {
1131 cpu_arch_name = cpu_arch[i].name;
1132 cpu_sub_arch_name = NULL;
1133 cpu_arch_flags = (cpu_arch[i].flags
4eed87de
AM		 1134 | (flag_code == CODE_64BIT
1135 ? Cpu64 : CpuNo64));
ccc9c027 1136 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1137 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1138 if (!cpu_arch_tune_set)
1139 {
1140 cpu_arch_tune = cpu_arch_isa;
1141 cpu_arch_tune_flags = cpu_arch_isa_flags;
1142 }
5c6af06e
JB		 1143 break;
1144 }
1145 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1146 {
1147 cpu_sub_arch_name = cpu_arch[i].name;
1148 cpu_arch_flags |= cpu_arch[i].flags;
1149 }
1150 *input_line_pointer = e;
1151 demand_empty_rest_of_line ();
1152 return;
e413e4e9
AM		 1153 }
1154 }
9103f4f4 1155 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1156 as_bad (_("no such architecture: `%s'"), string);
1157
1158 *input_line_pointer = e;
1159 }
1160 else
1161 as_bad (_("missing cpu architecture"));
1162
fddf5b5b
AM		 1163 no_cond_jump_promotion = 0;
1164 if (*input_line_pointer == ','
29b0f896 1165 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1166 {
1167 char *string = ++input_line_pointer;
1168 int e = get_symbol_end ();
1169
1170 if (strcmp (string, "nojumps") == 0)
1171 no_cond_jump_promotion = 1;
1172 else if (strcmp (string, "jumps") == 0)
1173 ;
1174 else
1175 as_bad (_("no such architecture modifier: `%s'"), string);
1176
1177 *input_line_pointer = e;
1178 }
1179
e413e4e9
AM		 1180 demand_empty_rest_of_line ();
1181}
1182
b9d79e03
JH		 1183unsigned long
1184i386_mach ()
1185{
1186 if (!strcmp (default_arch, "x86_64"))
1187 return bfd_mach_x86_64;
1188 else if (!strcmp (default_arch, "i386"))
1189 return bfd_mach_i386_i386;
1190 else
1191 as_fatal (_("Unknown architecture"));
1192}
b9d79e03 1193\f
252b5132
RH		 1194void
1195md_begin ()
1196{
1197 const char *hash_err;
1198
47926f60 1199 /* Initialize op_hash hash table. */
252b5132
RH		 1200 op_hash = hash_new ();
1201
1202 {
29b0f896
AM		 1203 const template *optab;
1204 templates *core_optab;
252b5132 1205
47926f60
KH		 1206 /* Setup for loop. */
1207 optab = i386_optab;
252b5132
RH		 1208 core_optab = (templates *) xmalloc (sizeof (templates));
1209 core_optab->start = optab;
1210
1211 while (1)
1212 {
1213 ++optab;
1214 if (optab->name == NULL
1215 || strcmp (optab->name, (optab - 1)->name) != 0)
1216 {
1217 /* different name --> ship out current template list;
47926f60 1218 add to hash table; & begin anew. */
252b5132
RH		 1219 core_optab->end = optab;
1220 hash_err = hash_insert (op_hash,
1221 (optab - 1)->name,
1222 (PTR) core_optab);
1223 if (hash_err)
1224 {
252b5132
RH		 1225 as_fatal (_("Internal Error: Can't hash %s: %s"),
1226 (optab - 1)->name,
1227 hash_err);
1228 }
1229 if (optab->name == NULL)
1230 break;
1231 core_optab = (templates *) xmalloc (sizeof (templates));
1232 core_optab->start = optab;
1233 }
1234 }
1235 }
1236
47926f60 1237 /* Initialize reg_hash hash table. */
252b5132
RH		 1238 reg_hash = hash_new ();
1239 {
29b0f896 1240 const reg_entry *regtab;
c3fe08fa 1241 unsigned int regtab_size = i386_regtab_size;
252b5132 1242
c3fe08fa 1243 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1244 {
1245 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1246 if (hash_err)
3e73aa7c
JH		 1247 as_fatal (_("Internal Error: Can't hash %s: %s"),
1248 regtab->reg_name,
1249 hash_err);
252b5132
RH		 1250 }
1251 }
1252
47926f60 1253 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1254 {
29b0f896
AM		 1255 int c;
1256 char *p;
252b5132
RH		 1257
1258 for (c = 0; c < 256; c++)
1259 {
3882b010 1260 if (ISDIGIT (c))
252b5132
RH		 1261 {
1262 digit_chars[c] = c;
1263 mnemonic_chars[c] = c;
1264 register_chars[c] = c;
1265 operand_chars[c] = c;
1266 }
3882b010 1267 else if (ISLOWER (c))
252b5132
RH		 1268 {
1269 mnemonic_chars[c] = c;
1270 register_chars[c] = c;
1271 operand_chars[c] = c;
1272 }
3882b010 1273 else if (ISUPPER (c))
252b5132 1274 {
3882b010 1275 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1276 register_chars[c] = mnemonic_chars[c];
1277 operand_chars[c] = c;
1278 }
1279
3882b010 1280 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1281 identifier_chars[c] = c;
1282 else if (c >= 128)
1283 {
1284 identifier_chars[c] = c;
1285 operand_chars[c] = c;
1286 }
1287 }
1288
1289#ifdef LEX_AT
1290 identifier_chars['@'] = '@';
32137342
NC		 1291#endif
1292#ifdef LEX_QM
1293 identifier_chars['?'] = '?';
1294 operand_chars['?'] = '?';
252b5132 1295#endif
252b5132 1296 digit_chars['-'] = '-';
791fe849 1297 mnemonic_chars['-'] = '-';
252b5132
RH		 1298 identifier_chars['_'] = '_';
1299 identifier_chars['.'] = '.';
1300
1301 for (p = operand_special_chars; *p != '\0'; p++)
1302 operand_chars[(unsigned char) *p] = *p;
1303 }
1304
1305#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1306 if (IS_ELF)
252b5132
RH		 1307 {
1308 record_alignment (text_section, 2);
1309 record_alignment (data_section, 2);
1310 record_alignment (bss_section, 2);
1311 }
1312#endif
a4447b93
RH		 1313
1314 if (flag_code == CODE_64BIT)
1315 {
1316 x86_dwarf2_return_column = 16;
1317 x86_cie_data_alignment = -8;
1318 }
1319 else
1320 {
1321 x86_dwarf2_return_column = 8;
1322 x86_cie_data_alignment = -4;
1323 }
252b5132
RH		 1324}
1325
1326void
e3bb37b5 1327i386_print_statistics (FILE *file)
252b5132
RH		 1328{
1329 hash_print_statistics (file, "i386 opcode", op_hash);
1330 hash_print_statistics (file, "i386 register", reg_hash);
1331}
1332\f
252b5132
RH		 1333#ifdef DEBUG386
1334
ce8a8b2f 1335/* Debugging routines for md_assemble. */
e3bb37b5
L		 1336static void pte (template *);
1337static void pt (unsigned int);
1338static void pe (expressionS *);
1339static void ps (symbolS *);
252b5132
RH		 1340
1341static void
e3bb37b5 1342pi (char *line, i386_insn *x)
252b5132 1343{
09f131f2 1344 unsigned int i;
252b5132
RH		 1345
1346 fprintf (stdout, "%s: template ", line);
1347 pte (&x->tm);
09f131f2
JH		 1348 fprintf (stdout, " address: base %s index %s scale %x\n",
1349 x->base_reg ? x->base_reg->reg_name : "none",
1350 x->index_reg ? x->index_reg->reg_name : "none",
1351 x->log2_scale_factor);
1352 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1353 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1354 fprintf (stdout, " sib: base %x index %x scale %x\n",
1355 x->sib.base, x->sib.index, x->sib.scale);
1356 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1357 (x->rex & REX_MODE64) != 0,
1358 (x->rex & REX_EXTX) != 0,
1359 (x->rex & REX_EXTY) != 0,
1360 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1361 for (i = 0; i < x->operands; i++)
1362 {
1363 fprintf (stdout, " #%d: ", i + 1);
1364 pt (x->types[i]);
1365 fprintf (stdout, "\n");
1366 if (x->types[i]
3f4438ab 1367 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1368 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1369 if (x->types[i] & Imm)
520dc8e8 1370 pe (x->op[i].imms);
252b5132 1371 if (x->types[i] & Disp)
520dc8e8 1372 pe (x->op[i].disps);
252b5132
RH		 1373 }
1374}
1375
1376static void
e3bb37b5 1377pte (template *t)
252b5132 1378{
09f131f2 1379 unsigned int i;
252b5132 1380 fprintf (stdout, " %d operands ", t->operands);
47926f60 1381 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1382 if (t->extension_opcode != None)
1383 fprintf (stdout, "ext %x ", t->extension_opcode);
1384 if (t->opcode_modifier & D)
1385 fprintf (stdout, "D");
1386 if (t->opcode_modifier & W)
1387 fprintf (stdout, "W");
1388 fprintf (stdout, "\n");
1389 for (i = 0; i < t->operands; i++)
1390 {
1391 fprintf (stdout, " #%d type ", i + 1);
1392 pt (t->operand_types[i]);
1393 fprintf (stdout, "\n");
1394 }
1395}
1396
1397static void
e3bb37b5 1398pe (expressionS *e)
252b5132 1399{
24eab124 1400 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1401 fprintf (stdout, " add_number %ld (%lx)\n",
1402 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1403 if (e->X_add_symbol)
1404 {
1405 fprintf (stdout, " add_symbol ");
1406 ps (e->X_add_symbol);
1407 fprintf (stdout, "\n");
1408 }
1409 if (e->X_op_symbol)
1410 {
1411 fprintf (stdout, " op_symbol ");
1412 ps (e->X_op_symbol);
1413 fprintf (stdout, "\n");
1414 }
1415}
1416
1417static void
e3bb37b5 1418ps (symbolS *s)
252b5132
RH		 1419{
1420 fprintf (stdout, "%s type %s%s",
1421 S_GET_NAME (s),
1422 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1423 segment_name (S_GET_SEGMENT (s)));
1424}
1425
7b81dfbb 1426static struct type_name
252b5132
RH		 1427 {
1428 unsigned int mask;
1429 char *tname;
1430 }
7b81dfbb 1431const type_names[] =
252b5132
RH		 1432{
1433 { Reg8, "r8" },
1434 { Reg16, "r16" },
1435 { Reg32, "r32" },
09f131f2 1436 { Reg64, "r64" },
252b5132
RH		 1437 { Imm8, "i8" },
1438 { Imm8S, "i8s" },
1439 { Imm16, "i16" },
1440 { Imm32, "i32" },
09f131f2
JH		 1441 { Imm32S, "i32s" },
1442 { Imm64, "i64" },
252b5132
RH		 1443 { Imm1, "i1" },
1444 { BaseIndex, "BaseIndex" },
1445 { Disp8, "d8" },
1446 { Disp16, "d16" },
1447 { Disp32, "d32" },
09f131f2
JH		 1448 { Disp32S, "d32s" },
1449 { Disp64, "d64" },
252b5132
RH		 1450 { InOutPortReg, "InOutPortReg" },
1451 { ShiftCount, "ShiftCount" },
1452 { Control, "control reg" },
1453 { Test, "test reg" },
1454 { Debug, "debug reg" },
1455 { FloatReg, "FReg" },
1456 { FloatAcc, "FAcc" },
1457 { SReg2, "SReg2" },
1458 { SReg3, "SReg3" },
1459 { Acc, "Acc" },
1460 { JumpAbsolute, "Jump Absolute" },
1461 { RegMMX, "rMMX" },
3f4438ab 1462 { RegXMM, "rXMM" },
252b5132
RH		 1463 { EsSeg, "es" },
1464 { 0, "" }
1465};
1466
1467static void
1468pt (t)
1469 unsigned int t;
1470{
29b0f896 1471 const struct type_name *ty;
252b5132 1472
09f131f2
JH		 1473 for (ty = type_names; ty->mask; ty++)
1474 if (t & ty->mask)
1475 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1476 fflush (stdout);
1477}
1478
1479#endif /* DEBUG386 */
1480\f
252b5132 1481static bfd_reloc_code_real_type
3956db08 1482reloc (unsigned int size,
64e74474
AM		 1483 int pcrel,
1484 int sign,
1485 bfd_reloc_code_real_type other)
252b5132 1486{
47926f60 1487 if (other != NO_RELOC)
3956db08
JB		 1488 {
1489 reloc_howto_type *reloc;
1490
1491 if (size == 8)
1492 switch (other)
1493 {
64e74474
AM		 1494 case BFD_RELOC_X86_64_GOT32:
1495 return BFD_RELOC_X86_64_GOT64;
1496 break;
1497 case BFD_RELOC_X86_64_PLTOFF64:
1498 return BFD_RELOC_X86_64_PLTOFF64;
1499 break;
1500 case BFD_RELOC_X86_64_GOTPC32:
1501 other = BFD_RELOC_X86_64_GOTPC64;
1502 break;
1503 case BFD_RELOC_X86_64_GOTPCREL:
1504 other = BFD_RELOC_X86_64_GOTPCREL64;
1505 break;
1506 case BFD_RELOC_X86_64_TPOFF32:
1507 other = BFD_RELOC_X86_64_TPOFF64;
1508 break;
1509 case BFD_RELOC_X86_64_DTPOFF32:
1510 other = BFD_RELOC_X86_64_DTPOFF64;
1511 break;
1512 default:
1513 break;
3956db08 1514 }
e05278af
JB		 1515
1516 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1517 if (size == 4 && flag_code != CODE_64BIT)
1518 sign = -1;
1519
3956db08
JB		 1520 reloc = bfd_reloc_type_lookup (stdoutput, other);
1521 if (!reloc)
1522 as_bad (_("unknown relocation (%u)"), other);
1523 else if (size != bfd_get_reloc_size (reloc))
1524 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1525 bfd_get_reloc_size (reloc),
1526 size);
1527 else if (pcrel && !reloc->pc_relative)
1528 as_bad (_("non-pc-relative relocation for pc-relative field"));
1529 else if ((reloc->complain_on_overflow == complain_overflow_signed
1530 && !sign)
1531 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1532 && sign > 0))
3956db08
JB		 1533 as_bad (_("relocated field and relocation type differ in signedness"));
1534 else
1535 return other;
1536 return NO_RELOC;
1537 }
252b5132
RH		 1538
1539 if (pcrel)
1540 {
3e73aa7c 1541 if (!sign)
3956db08 1542 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1543 switch (size)
1544 {
1545 case 1: return BFD_RELOC_8_PCREL;
1546 case 2: return BFD_RELOC_16_PCREL;
1547 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1548 case 8: return BFD_RELOC_64_PCREL;
252b5132 1549 }
3956db08 1550 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1551 }
1552 else
1553 {
3956db08 1554 if (sign > 0)
e5cb08ac 1555 switch (size)
3e73aa7c
JH		 1556 {
1557 case 4: return BFD_RELOC_X86_64_32S;
1558 }
1559 else
1560 switch (size)
1561 {
1562 case 1: return BFD_RELOC_8;
1563 case 2: return BFD_RELOC_16;
1564 case 4: return BFD_RELOC_32;
1565 case 8: return BFD_RELOC_64;
1566 }
3956db08
JB		 1567 as_bad (_("cannot do %s %u byte relocation"),
1568 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1569 }
1570
bfb32b52 1571 abort ();
252b5132
RH		 1572 return BFD_RELOC_NONE;
1573}
1574
47926f60
KH		 1575/* Here we decide which fixups can be adjusted to make them relative to
1576 the beginning of the section instead of the symbol. Basically we need
1577 to make sure that the dynamic relocations are done correctly, so in
1578 some cases we force the original symbol to be used. */
1579
252b5132 1580int
e3bb37b5 1581tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 1582{
6d249963 1583#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1584 if (!IS_ELF)
31312f95
AM		 1585 return 1;
1586
a161fe53
AM		 1587 /* Don't adjust pc-relative references to merge sections in 64-bit
1588 mode. */
1589 if (use_rela_relocations
1590 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1591 && fixP->fx_pcrel)
252b5132 1592 return 0;
31312f95 1593
8d01d9a9
AJ		 1594 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1595 and changed later by validate_fix. */
1596 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1597 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1598 return 0;
1599
ce8a8b2f 1600 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1601 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1602 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1603 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1604 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1605 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1606 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1607 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1608 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1609 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1610 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1611 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1612 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1613 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1614 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1615 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1616 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1617 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1618 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1619 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1620 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1621 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1622 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1623 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1624 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1625 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1626 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1627 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1628 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1629 return 0;
31312f95 1630#endif
252b5132
RH		 1631 return 1;
1632}
252b5132 1633
b4cac588 1634static int
e3bb37b5 1635intel_float_operand (const char *mnemonic)
252b5132 1636{
9306ca4a
JB		 1637 /* Note that the value returned is meaningful only for opcodes with (memory)
1638 operands, hence the code here is free to improperly handle opcodes that
1639 have no operands (for better performance and smaller code). */
1640
1641 if (mnemonic[0] != 'f')
1642 return 0; /* non-math */
1643
1644 switch (mnemonic[1])
1645 {
1646 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1647 the fs segment override prefix not currently handled because no
1648 call path can make opcodes without operands get here */
1649 case 'i':
1650 return 2 /* integer op */;
1651 case 'l':
1652 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1653 return 3; /* fldcw/fldenv */
1654 break;
1655 case 'n':
1656 if (mnemonic[2] != 'o' /* fnop */)
1657 return 3; /* non-waiting control op */
1658 break;
1659 case 'r':
1660 if (mnemonic[2] == 's')
1661 return 3; /* frstor/frstpm */
1662 break;
1663 case 's':
1664 if (mnemonic[2] == 'a')
1665 return 3; /* fsave */
1666 if (mnemonic[2] == 't')
1667 {
1668 switch (mnemonic[3])
1669 {
1670 case 'c': /* fstcw */
1671 case 'd': /* fstdw */
1672 case 'e': /* fstenv */
1673 case 's': /* fsts[gw] */
1674 return 3;
1675 }
1676 }
1677 break;
1678 case 'x':
1679 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1680 return 0; /* fxsave/fxrstor are not really math ops */
1681 break;
1682 }
252b5132 1683
9306ca4a 1684 return 1;
252b5132
RH		 1685}
1686
1687/* This is the guts of the machine-dependent assembler. LINE points to a
1688 machine dependent instruction. This function is supposed to emit
1689 the frags/bytes it assembles to. */
1690
1691void
1692md_assemble (line)
1693 char *line;
1694{
252b5132 1695 int j;
252b5132
RH		 1696 char mnemonic[MAX_MNEM_SIZE];
1697
47926f60 1698 /* Initialize globals. */
252b5132
RH		 1699 memset (&i, '\0', sizeof (i));
1700 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1701 i.reloc[j] = NO_RELOC;
252b5132
RH		 1702 memset (disp_expressions, '\0', sizeof (disp_expressions));
1703 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1704 save_stack_p = save_stack;
252b5132
RH		 1705
1706 /* First parse an instruction mnemonic & call i386_operand for the operands.
1707 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1708 start of a (possibly prefixed) mnemonic. */
252b5132 1709
29b0f896
AM		 1710 line = parse_insn (line, mnemonic);
1711 if (line == NULL)
1712 return;
252b5132 1713
29b0f896
AM		 1714 line = parse_operands (line, mnemonic);
1715 if (line == NULL)
1716 return;
252b5132 1717
4eed87de 1718 /* The order of the immediates should be reversed
050dfa73 1719 for 2 immediates extrq and insertq instructions */
4d456e3d
L		 1720 if ((i.imm_operands == 2)
1721 && ((strcmp (mnemonic, "extrq") == 0)
1722 || (strcmp (mnemonic, "insertq") == 0)))
050dfa73 1723 {
4eed87de
AM		 1724 swap_2_operands (0, 1);
1725 /* "extrq" and insertq" are the only two instructions whose operands
050dfa73
MM		 1726 have to be reversed even though they have two immediate operands.
1727 */
1728 if (intel_syntax)
1729 swap_operands ();
1730 }
1731
29b0f896
AM		 1732 /* Now we've parsed the mnemonic into a set of templates, and have the
1733 operands at hand. */
1734
1735 /* All intel opcodes have reversed operands except for "bound" and
1736 "enter". We also don't reverse intersegment "jmp" and "call"
1737 instructions with 2 immediate operands so that the immediate segment
050dfa73 1738 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 1739 if (intel_syntax
1740 && i.operands > 1
29b0f896 1741 && (strcmp (mnemonic, "bound") != 0)
30123838 1742 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1743 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1744 swap_operands ();
1745
1746 if (i.imm_operands)
1747 optimize_imm ();
1748
b300c311
L		 1749 /* Don't optimize displacement for movabs since it only takes 64bit
1750 displacement. */
1751 if (i.disp_operands
1752 && (flag_code != CODE_64BIT
1753 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1754 optimize_disp ();
1755
1756 /* Next, we find a template that matches the given insn,
1757 making sure the overlap of the given operands types is consistent
1758 with the template operand types. */
252b5132 1759
29b0f896
AM		 1760 if (!match_template ())
1761 return;
252b5132 1762
cd61ebfe
AM		 1763 if (intel_syntax)
1764 {
1765 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1766 if (SYSV386_COMPAT
1767 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 1768 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 1769
1770 /* Zap movzx and movsx suffix. The suffix may have been set from
1771 "word ptr" or "byte ptr" on the source operand, but we'll use
1772 the suffix later to choose the destination register. */
1773 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1774 {
1775 if (i.reg_operands < 2
1776 && !i.suffix
1777 && (~i.tm.opcode_modifier
1778 & (No_bSuf
1779 | No_wSuf
1780 | No_lSuf
1781 | No_sSuf
1782 | No_xSuf
1783 | No_qSuf)))
1784 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1785
1786 i.suffix = 0;
1787 }
cd61ebfe 1788 }
24eab124 1789
29b0f896
AM		 1790 if (i.tm.opcode_modifier & FWait)
1791 if (!add_prefix (FWAIT_OPCODE))
1792 return;
252b5132 1793
29b0f896
AM		 1794 /* Check string instruction segment overrides. */
1795 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1796 {
1797 if (!check_string ())
5dd0794d 1798 return;
29b0f896 1799 }
5dd0794d 1800
29b0f896
AM		 1801 if (!process_suffix ())
1802 return;
e413e4e9 1803
29b0f896
AM		 1804 /* Make still unresolved immediate matches conform to size of immediate
1805 given in i.suffix. */
1806 if (!finalize_imm ())
1807 return;
252b5132 1808
29b0f896
AM		 1809 if (i.types[0] & Imm1)
1810 i.imm_operands = 0; /* kludge for shift insns. */
1811 if (i.types[0] & ImplicitRegister)
1812 i.reg_operands--;
1813 if (i.types[1] & ImplicitRegister)
1814 i.reg_operands--;
1815 if (i.types[2] & ImplicitRegister)
1816 i.reg_operands--;
252b5132 1817
29b0f896
AM		 1818 if (i.tm.opcode_modifier & ImmExt)
1819 {
02fc3089
L		 1820 expressionS *exp;
1821
b7d9ef37 1822 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1823 {
b7d9ef37 1824 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1825 operands with an opcode suffix which is coded in the same
1826 place as an 8-bit immediate field would be. Here we check
1827 those operands and remove them afterwards. */
1828 unsigned int x;
1829
a4622f40 1830 for (x = 0; x < i.operands; x++)
ca164297
L		 1831 if (i.op[x].regs->reg_num != x)
1832 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1833 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1834 i.operands = 0;
1835 }
1836
29b0f896
AM		 1837 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1838 opcode suffix which is coded in the same place as an 8-bit
1839 immediate field would be. Here we fake an 8-bit immediate
1840 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1841
29b0f896 1842 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1843
29b0f896
AM		 1844 exp = &im_expressions[i.imm_operands++];
1845 i.op[i.operands].imms = exp;
1846 i.types[i.operands++] = Imm8;
1847 exp->X_op = O_constant;
1848 exp->X_add_number = i.tm.extension_opcode;
1849 i.tm.extension_opcode = None;
1850 }
252b5132 1851
29b0f896
AM		 1852 /* For insns with operands there are more diddles to do to the opcode. */
1853 if (i.operands)
1854 {
1855 if (!process_operands ())
1856 return;
1857 }
1858 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1859 {
1860 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1861 as_warn (_("translating to `%sp'"), i.tm.name);
1862 }
252b5132 1863
29b0f896
AM		 1864 /* Handle conversion of 'int $3' --> special int3 insn. */
1865 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1866 {
1867 i.tm.base_opcode = INT3_OPCODE;
1868 i.imm_operands = 0;
1869 }
252b5132 1870
29b0f896
AM		 1871 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1872 && i.op[0].disps->X_op == O_constant)
1873 {
1874 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1875 the absolute address given by the constant. Since ix86 jumps and
1876 calls are pc relative, we need to generate a reloc. */
1877 i.op[0].disps->X_add_symbol = &abs_symbol;
1878 i.op[0].disps->X_op = O_symbol;
1879 }
252b5132 1880
29b0f896
AM		 1881 if ((i.tm.opcode_modifier & Rex64) != 0)
1882 i.rex |= REX_MODE64;
252b5132 1883
29b0f896
AM		 1884 /* For 8 bit registers we need an empty rex prefix. Also if the
1885 instruction already has a prefix, we need to convert old
1886 registers to new ones. */
773f551c 1887
29b0f896
AM		 1888 if (((i.types[0] & Reg8) != 0
1889 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1890 || ((i.types[1] & Reg8) != 0
1891 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1892 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1893 && i.rex != 0))
1894 {
1895 int x;
726c5dcd 1896
29b0f896
AM		 1897 i.rex |= REX_OPCODE;
1898 for (x = 0; x < 2; x++)
1899 {
1900 /* Look for 8 bit operand that uses old registers. */
1901 if ((i.types[x] & Reg8) != 0
1902 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1903 {
29b0f896
AM		 1904 /* In case it is "hi" register, give up. */
1905 if (i.op[x].regs->reg_num > 3)
4eed87de
AM		 1906 as_bad (_("can't encode register '%%%s' in an "
1907 "instruction requiring REX prefix."),
29b0f896 1908 i.op[x].regs->reg_name);
773f551c 1909
29b0f896
AM		 1910 /* Otherwise it is equivalent to the extended register.
1911 Since the encoding doesn't change this is merely
1912 cosmetic cleanup for debug output. */
1913
1914 i.op[x].regs = i.op[x].regs + 8;
773f551c 1915 }
29b0f896
AM		 1916 }
1917 }
773f551c 1918
29b0f896
AM		 1919 if (i.rex != 0)
1920 add_prefix (REX_OPCODE | i.rex);
1921
1922 /* We are ready to output the insn. */
1923 output_insn ();
1924}
1925
1926static char *
e3bb37b5 1927parse_insn (char *line, char *mnemonic)
29b0f896
AM		 1928{
1929 char *l = line;
1930 char *token_start = l;
1931 char *mnem_p;
5c6af06e
JB		 1932 int supported;
1933 const template *t;
29b0f896
AM		 1934
1935 /* Non-zero if we found a prefix only acceptable with string insns. */
1936 const char *expecting_string_instruction = NULL;
45288df1 1937
29b0f896
AM		 1938 while (1)
1939 {
1940 mnem_p = mnemonic;
1941 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1942 {
1943 mnem_p++;
1944 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1945 {
29b0f896
AM		 1946 as_bad (_("no such instruction: `%s'"), token_start);
1947 return NULL;
1948 }
1949 l++;
1950 }
1951 if (!is_space_char (*l)
1952 && *l != END_OF_INSN
e44823cf
JB		 1953 && (intel_syntax
1954 || (*l != PREFIX_SEPARATOR
1955 && *l != ',')))
29b0f896
AM		 1956 {
1957 as_bad (_("invalid character %s in mnemonic"),
1958 output_invalid (*l));
1959 return NULL;
1960 }
1961 if (token_start == l)
1962 {
e44823cf 1963 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1964 as_bad (_("expecting prefix; got nothing"));
1965 else
1966 as_bad (_("expecting mnemonic; got nothing"));
1967 return NULL;
1968 }
45288df1 1969
29b0f896
AM		 1970 /* Look up instruction (or prefix) via hash table. */
1971 current_templates = hash_find (op_hash, mnemonic);
47926f60 1972
29b0f896
AM		 1973 if (*l != END_OF_INSN
1974 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1975 && current_templates
1976 && (current_templates->start->opcode_modifier & IsPrefix))
1977 {
2dd88dca
JB		 1978 if (current_templates->start->cpu_flags
1979 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1980 {
1981 as_bad ((flag_code != CODE_64BIT
1982 ? _("`%s' is only supported in 64-bit mode")
1983 : _("`%s' is not supported in 64-bit mode")),
1984 current_templates->start->name);
1985 return NULL;
1986 }
29b0f896
AM		 1987 /* If we are in 16-bit mode, do not allow addr16 or data16.
1988 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1989 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1990 && flag_code != CODE_64BIT
1991 && (((current_templates->start->opcode_modifier & Size32) != 0)
1992 ^ (flag_code == CODE_16BIT)))
1993 {
1994 as_bad (_("redundant %s prefix"),
1995 current_templates->start->name);
1996 return NULL;
45288df1 1997 }
29b0f896
AM		 1998 /* Add prefix, checking for repeated prefixes. */
1999 switch (add_prefix (current_templates->start->base_opcode))
2000 {
2001 case 0:
2002 return NULL;
2003 case 2:
2004 expecting_string_instruction = current_templates->start->name;
2005 break;
2006 }
2007 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2008 token_start = ++l;
2009 }
2010 else
2011 break;
2012 }
45288df1 2013
29b0f896
AM		 2014 if (!current_templates)
2015 {
2016 /* See if we can get a match by trimming off a suffix. */
2017 switch (mnem_p[-1])
2018 {
2019 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2020 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2021 i.suffix = SHORT_MNEM_SUFFIX;
2022 else
29b0f896
AM		 2023 case BYTE_MNEM_SUFFIX:
2024 case QWORD_MNEM_SUFFIX:
2025 i.suffix = mnem_p[-1];
2026 mnem_p[-1] = '\0';
2027 current_templates = hash_find (op_hash, mnemonic);
2028 break;
2029 case SHORT_MNEM_SUFFIX:
2030 case LONG_MNEM_SUFFIX:
2031 if (!intel_syntax)
2032 {
2033 i.suffix = mnem_p[-1];
2034 mnem_p[-1] = '\0';
2035 current_templates = hash_find (op_hash, mnemonic);
2036 }
2037 break;
252b5132 2038
29b0f896
AM		 2039 /* Intel Syntax. */
2040 case 'd':
2041 if (intel_syntax)
2042 {
9306ca4a 2043 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2044 i.suffix = SHORT_MNEM_SUFFIX;
2045 else
2046 i.suffix = LONG_MNEM_SUFFIX;
2047 mnem_p[-1] = '\0';
2048 current_templates = hash_find (op_hash, mnemonic);
2049 }
2050 break;
2051 }
2052 if (!current_templates)
2053 {
2054 as_bad (_("no such instruction: `%s'"), token_start);
2055 return NULL;
2056 }
2057 }
252b5132 2058
29b0f896
AM		 2059 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2060 {
2061 /* Check for a branch hint. We allow ",pt" and ",pn" for
2062 predict taken and predict not taken respectively.
2063 I'm not sure that branch hints actually do anything on loop
2064 and jcxz insns (JumpByte) for current Pentium4 chips. They
2065 may work in the future and it doesn't hurt to accept them
2066 now. */
2067 if (l[0] == ',' && l[1] == 'p')
2068 {
2069 if (l[2] == 't')
2070 {
2071 if (!add_prefix (DS_PREFIX_OPCODE))
2072 return NULL;
2073 l += 3;
2074 }
2075 else if (l[2] == 'n')
2076 {
2077 if (!add_prefix (CS_PREFIX_OPCODE))
2078 return NULL;
2079 l += 3;
2080 }
2081 }
2082 }
2083 /* Any other comma loses. */
2084 if (*l == ',')
2085 {
2086 as_bad (_("invalid character %s in mnemonic"),
2087 output_invalid (*l));
2088 return NULL;
2089 }
252b5132 2090
29b0f896 2091 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2092 supported = 0;
2093 for (t = current_templates->start; t < current_templates->end; ++t)
2094 {
2095 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2096 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2097 supported |= 1;
5c6af06e 2098 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2099 supported |= 2;
5c6af06e
JB		 2100 }
2101 if (!(supported & 2))
2102 {
2103 as_bad (flag_code == CODE_64BIT
2104 ? _("`%s' is not supported in 64-bit mode")
2105 : _("`%s' is only supported in 64-bit mode"),
2106 current_templates->start->name);
2107 return NULL;
2108 }
2109 if (!(supported & 1))
29b0f896 2110 {
5c6af06e
JB		 2111 as_warn (_("`%s' is not supported on `%s%s'"),
2112 current_templates->start->name,
2113 cpu_arch_name,
2114 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2115 }
2116 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2117 {
2118 as_warn (_("use .code16 to ensure correct addressing mode"));
2119 }
252b5132 2120
29b0f896 2121 /* Check for rep/repne without a string instruction. */
f41bbced 2122 if (expecting_string_instruction)
29b0f896 2123 {
f41bbced
JB		 2124 static templates override;
2125
2126 for (t = current_templates->start; t < current_templates->end; ++t)
2127 if (t->opcode_modifier & IsString)
2128 break;
2129 if (t >= current_templates->end)
2130 {
2131 as_bad (_("expecting string instruction after `%s'"),
64e74474 2132 expecting_string_instruction);
f41bbced
JB		 2133 return NULL;
2134 }
2135 for (override.start = t; t < current_templates->end; ++t)
2136 if (!(t->opcode_modifier & IsString))
2137 break;
2138 override.end = t;
2139 current_templates = &override;
29b0f896 2140 }
252b5132 2141
29b0f896
AM		 2142 return l;
2143}
252b5132 2144
29b0f896 2145static char *
e3bb37b5 2146parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2147{
2148 char *token_start;
3138f287 2149
29b0f896
AM		 2150 /* 1 if operand is pending after ','. */
2151 unsigned int expecting_operand = 0;
252b5132 2152
29b0f896
AM		 2153 /* Non-zero if operand parens not balanced. */
2154 unsigned int paren_not_balanced;
2155
2156 while (*l != END_OF_INSN)
2157 {
2158 /* Skip optional white space before operand. */
2159 if (is_space_char (*l))
2160 ++l;
2161 if (!is_operand_char (*l) && *l != END_OF_INSN)
2162 {
2163 as_bad (_("invalid character %s before operand %d"),
2164 output_invalid (*l),
2165 i.operands + 1);
2166 return NULL;
2167 }
2168 token_start = l; /* after white space */
2169 paren_not_balanced = 0;
2170 while (paren_not_balanced || *l != ',')
2171 {
2172 if (*l == END_OF_INSN)
2173 {
2174 if (paren_not_balanced)
2175 {
2176 if (!intel_syntax)
2177 as_bad (_("unbalanced parenthesis in operand %d."),
2178 i.operands + 1);
2179 else
2180 as_bad (_("unbalanced brackets in operand %d."),
2181 i.operands + 1);
2182 return NULL;
2183 }
2184 else
2185 break; /* we are done */
2186 }
2187 else if (!is_operand_char (*l) && !is_space_char (*l))
2188 {
2189 as_bad (_("invalid character %s in operand %d"),
2190 output_invalid (*l),
2191 i.operands + 1);
2192 return NULL;
2193 }
2194 if (!intel_syntax)
2195 {
2196 if (*l == '(')
2197 ++paren_not_balanced;
2198 if (*l == ')')
2199 --paren_not_balanced;
2200 }
2201 else
2202 {
2203 if (*l == '[')
2204 ++paren_not_balanced;
2205 if (*l == ']')
2206 --paren_not_balanced;
2207 }
2208 l++;
2209 }
2210 if (l != token_start)
2211 { /* Yes, we've read in another operand. */
2212 unsigned int operand_ok;
2213 this_operand = i.operands++;
2214 if (i.operands > MAX_OPERANDS)
2215 {
2216 as_bad (_("spurious operands; (%d operands/instruction max)"),
2217 MAX_OPERANDS);
2218 return NULL;
2219 }
2220 /* Now parse operand adding info to 'i' as we go along. */
2221 END_STRING_AND_SAVE (l);
2222
2223 if (intel_syntax)
2224 operand_ok =
2225 i386_intel_operand (token_start,
2226 intel_float_operand (mnemonic));
2227 else
2228 operand_ok = i386_operand (token_start);
2229
2230 RESTORE_END_STRING (l);
2231 if (!operand_ok)
2232 return NULL;
2233 }
2234 else
2235 {
2236 if (expecting_operand)
2237 {
2238 expecting_operand_after_comma:
2239 as_bad (_("expecting operand after ','; got nothing"));
2240 return NULL;
2241 }
2242 if (*l == ',')
2243 {
2244 as_bad (_("expecting operand before ','; got nothing"));
2245 return NULL;
2246 }
2247 }
7f3f1ea2 2248
29b0f896
AM		 2249 /* Now *l must be either ',' or END_OF_INSN. */
2250 if (*l == ',')
2251 {
2252 if (*++l == END_OF_INSN)
2253 {
2254 /* Just skip it, if it's \n complain. */
2255 goto expecting_operand_after_comma;
2256 }
2257 expecting_operand = 1;
2258 }
2259 }
2260 return l;
2261}
7f3f1ea2 2262
050dfa73 2263static void
4d456e3d 2264swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2265{
2266 union i386_op temp_op;
2267 unsigned int temp_type;
2268 enum bfd_reloc_code_real temp_reloc;
4eed87de 2269
050dfa73
MM		 2270 temp_type = i.types[xchg2];
2271 i.types[xchg2] = i.types[xchg1];
2272 i.types[xchg1] = temp_type;
2273 temp_op = i.op[xchg2];
2274 i.op[xchg2] = i.op[xchg1];
2275 i.op[xchg1] = temp_op;
2276 temp_reloc = i.reloc[xchg2];
2277 i.reloc[xchg2] = i.reloc[xchg1];
2278 i.reloc[xchg1] = temp_reloc;
2279}
2280
29b0f896 2281static void
e3bb37b5 2282swap_operands (void)
29b0f896 2283{
b7c61d9a 2284 switch (i.operands)
050dfa73 2285 {
b7c61d9a 2286 case 4:
4d456e3d 2287 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2288 case 3:
2289 case 2:
4d456e3d 2290 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2291 break;
2292 default:
2293 abort ();
29b0f896 2294 }
29b0f896
AM		 2295
2296 if (i.mem_operands == 2)
2297 {
2298 const seg_entry *temp_seg;
2299 temp_seg = i.seg[0];
2300 i.seg[0] = i.seg[1];
2301 i.seg[1] = temp_seg;
2302 }
2303}
252b5132 2304
29b0f896
AM		 2305/* Try to ensure constant immediates are represented in the smallest
2306 opcode possible. */
2307static void
e3bb37b5 2308optimize_imm (void)
29b0f896
AM		 2309{
2310 char guess_suffix = 0;
2311 int op;
252b5132 2312
29b0f896
AM		 2313 if (i.suffix)
2314 guess_suffix = i.suffix;
2315 else if (i.reg_operands)
2316 {
2317 /* Figure out a suffix from the last register operand specified.
2318 We can't do this properly yet, ie. excluding InOutPortReg,
2319 but the following works for instructions with immediates.
2320 In any case, we can't set i.suffix yet. */
2321 for (op = i.operands; --op >= 0;)
2322 if (i.types[op] & Reg)
252b5132 2323 {
29b0f896
AM		 2324 if (i.types[op] & Reg8)
2325 guess_suffix = BYTE_MNEM_SUFFIX;
2326 else if (i.types[op] & Reg16)
2327 guess_suffix = WORD_MNEM_SUFFIX;
2328 else if (i.types[op] & Reg32)
2329 guess_suffix = LONG_MNEM_SUFFIX;
2330 else if (i.types[op] & Reg64)
2331 guess_suffix = QWORD_MNEM_SUFFIX;
2332 break;
252b5132 2333 }
29b0f896
AM		 2334 }
2335 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2336 guess_suffix = WORD_MNEM_SUFFIX;
2337
2338 for (op = i.operands; --op >= 0;)
2339 if (i.types[op] & Imm)
2340 {
2341 switch (i.op[op].imms->X_op)
252b5132 2342 {
29b0f896
AM		 2343 case O_constant:
2344 /* If a suffix is given, this operand may be shortened. */
2345 switch (guess_suffix)
252b5132 2346 {
29b0f896
AM		 2347 case LONG_MNEM_SUFFIX:
2348 i.types[op] |= Imm32 | Imm64;
2349 break;
2350 case WORD_MNEM_SUFFIX:
2351 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2352 break;
2353 case BYTE_MNEM_SUFFIX:
2354 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2355 break;
252b5132 2356 }
252b5132 2357
29b0f896
AM		 2358 /* If this operand is at most 16 bits, convert it
2359 to a signed 16 bit number before trying to see
2360 whether it will fit in an even smaller size.
2361 This allows a 16-bit operand such as $0xffe0 to
2362 be recognised as within Imm8S range. */
2363 if ((i.types[op] & Imm16)
2364 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2365 {
29b0f896
AM		 2366 i.op[op].imms->X_add_number =
2367 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2368 }
2369 if ((i.types[op] & Imm32)
2370 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2371 == 0))
2372 {
2373 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2374 ^ ((offsetT) 1 << 31))
2375 - ((offsetT) 1 << 31));
2376 }
2377 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2378
29b0f896
AM		 2379 /* We must avoid matching of Imm32 templates when 64bit
2380 only immediate is available. */
2381 if (guess_suffix == QWORD_MNEM_SUFFIX)
2382 i.types[op] &= ~Imm32;
2383 break;
252b5132 2384
29b0f896
AM		 2385 case O_absent:
2386 case O_register:
2387 abort ();
2388
2389 /* Symbols and expressions. */
2390 default:
9cd96992
JB		 2391 /* Convert symbolic operand to proper sizes for matching, but don't
2392 prevent matching a set of insns that only supports sizes other
2393 than those matching the insn suffix. */
2394 {
2395 unsigned int mask, allowed = 0;
2396 const template *t;
2397
4eed87de
AM		 2398 for (t = current_templates->start;
2399 t < current_templates->end;
2400 ++t)
2401 allowed |= t->operand_types[op];
9cd96992
JB		 2402 switch (guess_suffix)
2403 {
2404 case QWORD_MNEM_SUFFIX:
2405 mask = Imm64 | Imm32S;
2406 break;
2407 case LONG_MNEM_SUFFIX:
2408 mask = Imm32;
2409 break;
2410 case WORD_MNEM_SUFFIX:
2411 mask = Imm16;
2412 break;
2413 case BYTE_MNEM_SUFFIX:
2414 mask = Imm8;
2415 break;
2416 default:
2417 mask = 0;
2418 break;
2419 }
64e74474
AM		 2420 if (mask & allowed)
2421 i.types[op] &= mask;
9cd96992 2422 }
29b0f896 2423 break;
252b5132 2424 }
29b0f896
AM		 2425 }
2426}
47926f60 2427
29b0f896
AM		 2428/* Try to use the smallest displacement type too. */
2429static void
e3bb37b5 2430optimize_disp (void)
29b0f896
AM		 2431{
2432 int op;
3e73aa7c 2433
29b0f896 2434 for (op = i.operands; --op >= 0;)
b300c311 2435 if (i.types[op] & Disp)
252b5132 2436 {
b300c311 2437 if (i.op[op].disps->X_op == O_constant)
252b5132 2438 {
b300c311 2439 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2440
b300c311
L		 2441 if ((i.types[op] & Disp16)
2442 && (disp & ~(offsetT) 0xffff) == 0)
2443 {
2444 /* If this operand is at most 16 bits, convert
2445 to a signed 16 bit number and don't use 64bit
2446 displacement. */
2447 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2448 i.types[op] &= ~Disp64;
2449 }
2450 if ((i.types[op] & Disp32)
2451 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2452 {
2453 /* If this operand is at most 32 bits, convert
2454 to a signed 32 bit number and don't use 64bit
2455 displacement. */
2456 disp &= (((offsetT) 2 << 31) - 1);
2457 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2458 i.types[op] &= ~Disp64;
2459 }
2460 if (!disp && (i.types[op] & BaseIndex))
2461 {
2462 i.types[op] &= ~Disp;
2463 i.op[op].disps = 0;
2464 i.disp_operands--;
2465 }
2466 else if (flag_code == CODE_64BIT)
2467 {
2468 if (fits_in_signed_long (disp))
28a9d8f5
L		 2469 {
2470 i.types[op] &= ~Disp64;
2471 i.types[op] |= Disp32S;
2472 }
b300c311
L		 2473 if (fits_in_unsigned_long (disp))
2474 i.types[op] |= Disp32;
2475 }
2476 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2477 && fits_in_signed_byte (disp))
2478 i.types[op] |= Disp8;
252b5132 2479 }
67a4f2b7
AO		 2480 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2481 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2482 {
2483 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2484 i.op[op].disps, 0, i.reloc[op]);
2485 i.types[op] &= ~Disp;
2486 }
2487 else
b300c311
L		 2488 /* We only support 64bit displacement on constants. */
2489 i.types[op] &= ~Disp64;
252b5132 2490 }
29b0f896
AM		 2491}
2492
2493static int
e3bb37b5 2494match_template (void)
29b0f896
AM		 2495{
2496 /* Points to template once we've found it. */
2497 const template *t;
f48ff2ae 2498 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2499 unsigned int found_reverse_match;
2500 int suffix_check;
f48ff2ae 2501 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2502 int addr_prefix_disp;
a5c311ca 2503 unsigned int j;
29b0f896 2504
f48ff2ae
L		 2505#if MAX_OPERANDS != 4
2506# error "MAX_OPERANDS must be 4."
2507#endif
2508
29b0f896
AM		 2509#define MATCH(overlap, given, template) \
2510 ((overlap & ~JumpAbsolute) \
2511 && (((given) & (BaseIndex | JumpAbsolute)) \
2512 == ((overlap) & (BaseIndex | JumpAbsolute))))
2513
2514 /* If given types r0 and r1 are registers they must be of the same type
2515 unless the expected operand type register overlap is null.
2516 Note that Acc in a template matches every size of reg. */
2517#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2518 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2519 || ((g0) & Reg) == ((g1) & Reg) \
2520 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2521
2522 overlap0 = 0;
2523 overlap1 = 0;
2524 overlap2 = 0;
f48ff2ae 2525 overlap3 = 0;
29b0f896 2526 found_reverse_match = 0;
a5c311ca
L		 2527 for (j = 0; j < MAX_OPERANDS; j++)
2528 operand_types [j] = 0;
539e75ad 2529 addr_prefix_disp = -1;
29b0f896
AM		 2530 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2531 ? No_bSuf
2532 : (i.suffix == WORD_MNEM_SUFFIX
2533 ? No_wSuf
2534 : (i.suffix == SHORT_MNEM_SUFFIX
2535 ? No_sSuf
2536 : (i.suffix == LONG_MNEM_SUFFIX
2537 ? No_lSuf
2538 : (i.suffix == QWORD_MNEM_SUFFIX
2539 ? No_qSuf
2540 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2541 ? No_xSuf : 0))))));
2542
45aa61fe 2543 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2544 {
539e75ad
L		 2545 addr_prefix_disp = -1;
2546
29b0f896
AM		 2547 /* Must have right number of operands. */
2548 if (i.operands != t->operands)
2549 continue;
2550
2551 /* Check the suffix, except for some instructions in intel mode. */
2552 if ((t->opcode_modifier & suffix_check)
2553 && !(intel_syntax
9306ca4a 2554 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2555 continue;
2556
a5c311ca
L		 2557 for (j = 0; j < MAX_OPERANDS; j++)
2558 operand_types [j] = t->operand_types [j];
539e75ad 2559
45aa61fe
AM		 2560 /* In general, don't allow 64-bit operands in 32-bit mode. */
2561 if (i.suffix == QWORD_MNEM_SUFFIX
2562 && flag_code != CODE_64BIT
2563 && (intel_syntax
2564 ? (!(t->opcode_modifier & IgnoreSize)
2565 && !intel_float_operand (t->name))
2566 : intel_float_operand (t->name) != 2)
539e75ad
L		 2567 && (!(operand_types[0] & (RegMMX | RegXMM))
2568 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2569 && (t->base_opcode != 0x0fc7
2570 || t->extension_opcode != 1 /* cmpxchg8b */))
2571 continue;
2572
29b0f896
AM		 2573 /* Do not verify operands when there are none. */
2574 else if (!t->operands)
2575 {
2576 if (t->cpu_flags & ~cpu_arch_flags)
2577 continue;
2578 /* We've found a match; break out of loop. */
2579 break;
2580 }
252b5132 2581
539e75ad
L		 2582 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2583 into Disp32/Disp16/Disp32 operand. */
2584 if (i.prefix[ADDR_PREFIX] != 0)
2585 {
a5c311ca 2586 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2587
2588 switch (flag_code)
2589 {
2590 case CODE_16BIT:
2591 DispOn = Disp32;
2592 DispOff = Disp16;
2593 break;
2594 case CODE_32BIT:
2595 DispOn = Disp16;
2596 DispOff = Disp32;
2597 break;
2598 case CODE_64BIT:
2599 DispOn = Disp32;
2600 DispOff = Disp64;
2601 break;
2602 }
2603
f48ff2ae 2604 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2605 {
2606 /* There should be only one Disp operand. */
2607 if ((operand_types[j] & DispOff))
2608 {
2609 addr_prefix_disp = j;
2610 operand_types[j] |= DispOn;
2611 operand_types[j] &= ~DispOff;
2612 break;
2613 }
2614 }
2615 }
2616
2617 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2618 switch (t->operands)
2619 {
2620 case 1:
539e75ad 2621 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2622 continue;
2623 break;
2624 case 2:
2625 case 3:
f48ff2ae 2626 case 4:
539e75ad
L		 2627 overlap1 = i.types[1] & operand_types[1];
2628 if (!MATCH (overlap0, i.types[0], operand_types[0])
2629 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2630 /* monitor in SSE3 is a very special case. The first
708587a4 2631 register and the second register may have different
cb712a9e
L		 2632 sizes. */
2633 || !((t->base_opcode == 0x0f01
2634 && t->extension_opcode == 0xc8)
2635 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2636 operand_types[0],
cb712a9e 2637 overlap1, i.types[1],
539e75ad 2638 operand_types[1])))
29b0f896
AM		 2639 {
2640 /* Check if other direction is valid ... */
2641 if ((t->opcode_modifier & (D | FloatD)) == 0)
2642 continue;
2643
2644 /* Try reversing direction of operands. */
539e75ad
L		 2645 overlap0 = i.types[0] & operand_types[1];
2646 overlap1 = i.types[1] & operand_types[0];
2647 if (!MATCH (overlap0, i.types[0], operand_types[1])
2648 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2649 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2650 operand_types[1],
29b0f896 2651 overlap1, i.types[1],
539e75ad 2652 operand_types[0]))
29b0f896
AM		 2653 {
2654 /* Does not match either direction. */
2655 continue;
2656 }
2657 /* found_reverse_match holds which of D or FloatDR
2658 we've found. */
8a2ed489
L		 2659 if ((t->opcode_modifier & D))
2660 found_reverse_match = Opcode_D;
2661 else if ((t->opcode_modifier & FloatD))
2662 found_reverse_match = Opcode_FloatD;
2663 else
2664 found_reverse_match = 0;
2665 if ((t->opcode_modifier & FloatR))
2666 found_reverse_match |= Opcode_FloatR;
29b0f896 2667 }
f48ff2ae 2668 else
29b0f896 2669 {
f48ff2ae 2670 /* Found a forward 2 operand match here. */
d1cbb4db
L		 2671 switch (t->operands)
2672 {
2673 case 4:
2674 overlap3 = i.types[3] & operand_types[3];
2675 case 3:
2676 overlap2 = i.types[2] & operand_types[2];
2677 break;
2678 }
29b0f896 2679
f48ff2ae
L		 2680 switch (t->operands)
2681 {
2682 case 4:
2683 if (!MATCH (overlap3, i.types[3], operand_types[3])
2684 || !CONSISTENT_REGISTER_MATCH (overlap2,
2685 i.types[2],
2686 operand_types[2],
2687 overlap3,
2688 i.types[3],
2689 operand_types[3]))
2690 continue;
2691 case 3:
2692 /* Here we make use of the fact that there are no
2693 reverse match 3 operand instructions, and all 3
2694 operand instructions only need to be checked for
2695 register consistency between operands 2 and 3. */
2696 if (!MATCH (overlap2, i.types[2], operand_types[2])
2697 || !CONSISTENT_REGISTER_MATCH (overlap1,
2698 i.types[1],
2699 operand_types[1],
2700 overlap2,
2701 i.types[2],
2702 operand_types[2]))
2703 continue;
2704 break;
2705 }
29b0f896 2706 }
f48ff2ae 2707 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2708 slip through to break. */
2709 }
2710 if (t->cpu_flags & ~cpu_arch_flags)
2711 {
2712 found_reverse_match = 0;
2713 continue;
2714 }
2715 /* We've found a match; break out of loop. */
2716 break;
2717 }
2718
2719 if (t == current_templates->end)
2720 {
2721 /* We found no match. */
2722 as_bad (_("suffix or operands invalid for `%s'"),
2723 current_templates->start->name);
2724 return 0;
2725 }
252b5132 2726
29b0f896
AM		 2727 if (!quiet_warnings)
2728 {
2729 if (!intel_syntax
2730 && ((i.types[0] & JumpAbsolute)
539e75ad 2731 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2732 {
2733 as_warn (_("indirect %s without `*'"), t->name);
2734 }
2735
2736 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2737 == (IsPrefix | IgnoreSize))
2738 {
2739 /* Warn them that a data or address size prefix doesn't
2740 affect assembly of the next line of code. */
2741 as_warn (_("stand-alone `%s' prefix"), t->name);
2742 }
2743 }
2744
2745 /* Copy the template we found. */
2746 i.tm = *t;
539e75ad
L		 2747
2748 if (addr_prefix_disp != -1)
2749 i.tm.operand_types[addr_prefix_disp]
2750 = operand_types[addr_prefix_disp];
2751
29b0f896
AM		 2752 if (found_reverse_match)
2753 {
2754 /* If we found a reverse match we must alter the opcode
2755 direction bit. found_reverse_match holds bits to change
2756 (different for int & float insns). */
2757
2758 i.tm.base_opcode ^= found_reverse_match;
2759
539e75ad
L		 2760 i.tm.operand_types[0] = operand_types[1];
2761 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2762 }
2763
2764 return 1;
2765}
2766
2767static int
e3bb37b5 2768check_string (void)
29b0f896
AM		 2769{
2770 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2771 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2772 {
2773 if (i.seg[0] != NULL && i.seg[0] != &es)
2774 {
2775 as_bad (_("`%s' operand %d must use `%%es' segment"),
2776 i.tm.name,
2777 mem_op + 1);
2778 return 0;
2779 }
2780 /* There's only ever one segment override allowed per instruction.
2781 This instruction possibly has a legal segment override on the
2782 second operand, so copy the segment to where non-string
2783 instructions store it, allowing common code. */
2784 i.seg[0] = i.seg[1];
2785 }
2786 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2787 {
2788 if (i.seg[1] != NULL && i.seg[1] != &es)
2789 {
2790 as_bad (_("`%s' operand %d must use `%%es' segment"),
2791 i.tm.name,
2792 mem_op + 2);
2793 return 0;
2794 }
2795 }
2796 return 1;
2797}
2798
2799static int
543613e9 2800process_suffix (void)
29b0f896
AM		 2801{
2802 /* If matched instruction specifies an explicit instruction mnemonic
2803 suffix, use it. */
2804 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2805 {
2806 if (i.tm.opcode_modifier & Size16)
2807 i.suffix = WORD_MNEM_SUFFIX;
2808 else if (i.tm.opcode_modifier & Size64)
2809 i.suffix = QWORD_MNEM_SUFFIX;
2810 else
2811 i.suffix = LONG_MNEM_SUFFIX;
2812 }
2813 else if (i.reg_operands)
2814 {
2815 /* If there's no instruction mnemonic suffix we try to invent one
2816 based on register operands. */
2817 if (!i.suffix)
2818 {
2819 /* We take i.suffix from the last register operand specified,
2820 Destination register type is more significant than source
2821 register type. */
2822 int op;
543613e9 2823
29b0f896
AM		 2824 for (op = i.operands; --op >= 0;)
2825 if ((i.types[op] & Reg)
2826 && !(i.tm.operand_types[op] & InOutPortReg))
2827 {
2828 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2829 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2830 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2831 LONG_MNEM_SUFFIX);
2832 break;
2833 }
2834 }
2835 else if (i.suffix == BYTE_MNEM_SUFFIX)
2836 {
2837 if (!check_byte_reg ())
2838 return 0;
2839 }
2840 else if (i.suffix == LONG_MNEM_SUFFIX)
2841 {
2842 if (!check_long_reg ())
2843 return 0;
2844 }
2845 else if (i.suffix == QWORD_MNEM_SUFFIX)
2846 {
2847 if (!check_qword_reg ())
2848 return 0;
2849 }
2850 else if (i.suffix == WORD_MNEM_SUFFIX)
2851 {
2852 if (!check_word_reg ())
2853 return 0;
2854 }
2855 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2856 /* Do nothing if the instruction is going to ignore the prefix. */
2857 ;
2858 else
2859 abort ();
2860 }
9306ca4a
JB		 2861 else if ((i.tm.opcode_modifier & DefaultSize)
2862 && !i.suffix
2863 /* exclude fldenv/frstor/fsave/fstenv */
2864 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2865 {
2866 i.suffix = stackop_size;
2867 }
9306ca4a
JB		 2868 else if (intel_syntax
2869 && !i.suffix
2870 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2871 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2872 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2873 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2874 {
2875 switch (flag_code)
2876 {
2877 case CODE_64BIT:
2878 if (!(i.tm.opcode_modifier & No_qSuf))
2879 {
2880 i.suffix = QWORD_MNEM_SUFFIX;
2881 break;
2882 }
2883 case CODE_32BIT:
2884 if (!(i.tm.opcode_modifier & No_lSuf))
2885 i.suffix = LONG_MNEM_SUFFIX;
2886 break;
2887 case CODE_16BIT:
2888 if (!(i.tm.opcode_modifier & No_wSuf))
2889 i.suffix = WORD_MNEM_SUFFIX;
2890 break;
2891 }
2892 }
252b5132 2893
9306ca4a 2894 if (!i.suffix)
29b0f896 2895 {
9306ca4a
JB		 2896 if (!intel_syntax)
2897 {
2898 if (i.tm.opcode_modifier & W)
2899 {
4eed87de
AM		 2900 as_bad (_("no instruction mnemonic suffix given and "
2901 "no register operands; can't size instruction"));
9306ca4a
JB		 2902 return 0;
2903 }
2904 }
2905 else
2906 {
64e74474
AM		 2907 unsigned int suffixes = (~i.tm.opcode_modifier
2908 & (No_bSuf
2909 | No_wSuf
2910 | No_lSuf
2911 | No_sSuf
2912 | No_xSuf
2913 | No_qSuf));
9306ca4a
JB		 2914
2915 if ((i.tm.opcode_modifier & W)
2916 || ((suffixes & (suffixes - 1))
2917 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2918 {
2919 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2920 return 0;
2921 }
2922 }
29b0f896 2923 }
252b5132 2924
9306ca4a
JB		 2925 /* Change the opcode based on the operand size given by i.suffix;
2926 We don't need to change things for byte insns. */
2927
29b0f896
AM		 2928 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2929 {
2930 /* It's not a byte, select word/dword operation. */
2931 if (i.tm.opcode_modifier & W)
2932 {
2933 if (i.tm.opcode_modifier & ShortForm)
2934 i.tm.base_opcode |= 8;
2935 else
2936 i.tm.base_opcode |= 1;
2937 }
0f3f3d8b 2938
29b0f896
AM		 2939 /* Now select between word & dword operations via the operand
2940 size prefix, except for instructions that will ignore this
2941 prefix anyway. */
cb712a9e
L		 2942 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2943 {
2944 /* monitor in SSE3 is a very special case. The default size
2945 of AX is the size of mode. The address size override
2946 prefix will change the size of AX. */
2947 if (i.op->regs[0].reg_type &
2948 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2949 if (!add_prefix (ADDR_PREFIX_OPCODE))
2950 return 0;
2951 }
2952 else if (i.suffix != QWORD_MNEM_SUFFIX
2953 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2954 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2955 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2956 || (flag_code == CODE_64BIT
2957 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2958 {
2959 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2960
29b0f896
AM		 2961 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2962 prefix = ADDR_PREFIX_OPCODE;
252b5132 2963
29b0f896
AM		 2964 if (!add_prefix (prefix))
2965 return 0;
24eab124 2966 }
252b5132 2967
29b0f896
AM		 2968 /* Set mode64 for an operand. */
2969 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2970 && flag_code == CODE_64BIT
29b0f896 2971 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 2972 {
2973 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2974 need rex64. */
2975 if (i.operands != 2
2976 || i.types [0] != (Acc | Reg64)
2977 || i.types [1] != (Acc | Reg64)
2978 || strcmp (i.tm.name, "xchg") != 0)
2979 i.rex |= REX_MODE64;
2980 }
3e73aa7c 2981
29b0f896
AM		 2982 /* Size floating point instruction. */
2983 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2984 if (i.tm.opcode_modifier & FloatMF)
2985 i.tm.base_opcode ^= 4;
29b0f896 2986 }
7ecd2f8b 2987
29b0f896
AM		 2988 return 1;
2989}
3e73aa7c 2990
29b0f896 2991static int
543613e9 2992check_byte_reg (void)
29b0f896
AM		 2993{
2994 int op;
543613e9 2995
29b0f896
AM		 2996 for (op = i.operands; --op >= 0;)
2997 {
2998 /* If this is an eight bit register, it's OK. If it's the 16 or
2999 32 bit version of an eight bit register, we will just use the
3000 low portion, and that's OK too. */
3001 if (i.types[op] & Reg8)
3002 continue;
3003
3004 /* movzx and movsx should not generate this warning. */
3005 if (intel_syntax
3006 && (i.tm.base_opcode == 0xfb7
3007 || i.tm.base_opcode == 0xfb6
3008 || i.tm.base_opcode == 0x63
3009 || i.tm.base_opcode == 0xfbe
3010 || i.tm.base_opcode == 0xfbf))
3011 continue;
3012
65ec77d2 3013 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3014 {
3015 /* Prohibit these changes in the 64bit mode, since the
3016 lowering is more complicated. */
3017 if (flag_code == CODE_64BIT
3018 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3019 {
2ca3ace5
L		 3020 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3021 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3022 i.suffix);
3023 return 0;
3024 }
3025#if REGISTER_WARNINGS
3026 if (!quiet_warnings
3027 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3028 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3029 (i.op[op].regs + (i.types[op] & Reg16
3030 ? REGNAM_AL - REGNAM_AX
3031 : REGNAM_AL - REGNAM_EAX))->reg_name,
3032 i.op[op].regs->reg_name,
3033 i.suffix);
3034#endif
3035 continue;
3036 }
3037 /* Any other register is bad. */
3038 if (i.types[op] & (Reg | RegMMX | RegXMM
3039 | SReg2 | SReg3
3040 | Control | Debug | Test
3041 | FloatReg | FloatAcc))
3042 {
3043 as_bad (_("`%%%s' not allowed with `%s%c'"),
3044 i.op[op].regs->reg_name,
3045 i.tm.name,
3046 i.suffix);
3047 return 0;
3048 }
3049 }
3050 return 1;
3051}
3052
3053static int
e3bb37b5 3054check_long_reg (void)
29b0f896
AM		 3055{
3056 int op;
3057
3058 for (op = i.operands; --op >= 0;)
3059 /* Reject eight bit registers, except where the template requires
3060 them. (eg. movzb) */
3061 if ((i.types[op] & Reg8) != 0
3062 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3063 {
3064 as_bad (_("`%%%s' not allowed with `%s%c'"),
3065 i.op[op].regs->reg_name,
3066 i.tm.name,
3067 i.suffix);
3068 return 0;
3069 }
3070 /* Warn if the e prefix on a general reg is missing. */
3071 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3072 && (i.types[op] & Reg16) != 0
3073 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3074 {
3075 /* Prohibit these changes in the 64bit mode, since the
3076 lowering is more complicated. */
3077 if (flag_code == CODE_64BIT)
252b5132 3078 {
2ca3ace5
L		 3079 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3080 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3081 i.suffix);
3082 return 0;
252b5132 3083 }
29b0f896
AM		 3084#if REGISTER_WARNINGS
3085 else
3086 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3087 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3088 i.op[op].regs->reg_name,
3089 i.suffix);
3090#endif
252b5132 3091 }
29b0f896
AM		 3092 /* Warn if the r prefix on a general reg is missing. */
3093 else if ((i.types[op] & Reg64) != 0
3094 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3095 {
2ca3ace5
L		 3096 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3097 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3098 i.suffix);
3099 return 0;
3100 }
3101 return 1;
3102}
252b5132 3103
29b0f896 3104static int
e3bb37b5 3105check_qword_reg (void)
29b0f896
AM		 3106{
3107 int op;
252b5132 3108
29b0f896
AM		 3109 for (op = i.operands; --op >= 0; )
3110 /* Reject eight bit registers, except where the template requires
3111 them. (eg. movzb) */
3112 if ((i.types[op] & Reg8) != 0
3113 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3114 {
3115 as_bad (_("`%%%s' not allowed with `%s%c'"),
3116 i.op[op].regs->reg_name,
3117 i.tm.name,
3118 i.suffix);
3119 return 0;
3120 }
3121 /* Warn if the e prefix on a general reg is missing. */
3122 else if (((i.types[op] & Reg16) != 0
3123 || (i.types[op] & Reg32) != 0)
3124 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3125 {
3126 /* Prohibit these changes in the 64bit mode, since the
3127 lowering is more complicated. */
2ca3ace5
L		 3128 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3129 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3130 i.suffix);
3131 return 0;
252b5132 3132 }
29b0f896
AM		 3133 return 1;
3134}
252b5132 3135
29b0f896 3136static int
e3bb37b5 3137check_word_reg (void)
29b0f896
AM		 3138{
3139 int op;
3140 for (op = i.operands; --op >= 0;)
3141 /* Reject eight bit registers, except where the template requires
3142 them. (eg. movzb) */
3143 if ((i.types[op] & Reg8) != 0
3144 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3145 {
3146 as_bad (_("`%%%s' not allowed with `%s%c'"),
3147 i.op[op].regs->reg_name,
3148 i.tm.name,
3149 i.suffix);
3150 return 0;
3151 }
3152 /* Warn if the e prefix on a general reg is present. */
3153 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3154 && (i.types[op] & Reg32) != 0
3155 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3156 {
29b0f896
AM		 3157 /* Prohibit these changes in the 64bit mode, since the
3158 lowering is more complicated. */
3159 if (flag_code == CODE_64BIT)
252b5132 3160 {
2ca3ace5
L		 3161 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3162 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3163 i.suffix);
3164 return 0;
252b5132 3165 }
29b0f896
AM		 3166 else
3167#if REGISTER_WARNINGS
3168 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3169 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3170 i.op[op].regs->reg_name,
3171 i.suffix);
3172#endif
3173 }
3174 return 1;
3175}
252b5132 3176
29b0f896 3177static int
e3bb37b5 3178finalize_imm (void)
29b0f896
AM		 3179{
3180 unsigned int overlap0, overlap1, overlap2;
3181
3182 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3183 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3184 && overlap0 != Imm8 && overlap0 != Imm8S
3185 && overlap0 != Imm16 && overlap0 != Imm32S
3186 && overlap0 != Imm32 && overlap0 != Imm64)
3187 {
3188 if (i.suffix)
3189 {
3190 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3191 ? Imm8 | Imm8S
3192 : (i.suffix == WORD_MNEM_SUFFIX
3193 ? Imm16
3194 : (i.suffix == QWORD_MNEM_SUFFIX
3195 ? Imm64 | Imm32S
3196 : Imm32)));
3197 }
3198 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3199 || overlap0 == (Imm16 | Imm32)
3200 || overlap0 == (Imm16 | Imm32S))
3201 {
3202 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3203 ? Imm16 : Imm32S);
3204 }
3205 if (overlap0 != Imm8 && overlap0 != Imm8S
3206 && overlap0 != Imm16 && overlap0 != Imm32S
3207 && overlap0 != Imm32 && overlap0 != Imm64)
3208 {
4eed87de
AM		 3209 as_bad (_("no instruction mnemonic suffix given; "
3210 "can't determine immediate size"));
29b0f896
AM		 3211 return 0;
3212 }
3213 }
3214 i.types[0] = overlap0;
3215
3216 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3217 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3218 && overlap1 != Imm8 && overlap1 != Imm8S
3219 && overlap1 != Imm16 && overlap1 != Imm32S
3220 && overlap1 != Imm32 && overlap1 != Imm64)
3221 {
3222 if (i.suffix)
3223 {
3224 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3225 ? Imm8 | Imm8S
3226 : (i.suffix == WORD_MNEM_SUFFIX
3227 ? Imm16
3228 : (i.suffix == QWORD_MNEM_SUFFIX
3229 ? Imm64 | Imm32S
3230 : Imm32)));
3231 }
3232 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3233 || overlap1 == (Imm16 | Imm32)
3234 || overlap1 == (Imm16 | Imm32S))
3235 {
3236 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3237 ? Imm16 : Imm32S);
3238 }
3239 if (overlap1 != Imm8 && overlap1 != Imm8S
3240 && overlap1 != Imm16 && overlap1 != Imm32S
3241 && overlap1 != Imm32 && overlap1 != Imm64)
3242 {
4eed87de
AM		 3243 as_bad (_("no instruction mnemonic suffix given; "
3244 "can't determine immediate size %x %c"),
3245 overlap1, i.suffix);
29b0f896
AM		 3246 return 0;
3247 }
3248 }
3249 i.types[1] = overlap1;
3250
3251 overlap2 = i.types[2] & i.tm.operand_types[2];
3252 assert ((overlap2 & Imm) == 0);
3253 i.types[2] = overlap2;
3254
3255 return 1;
3256}
3257
3258static int
e3bb37b5 3259process_operands (void)
29b0f896
AM		 3260{
3261 /* Default segment register this instruction will use for memory
3262 accesses. 0 means unknown. This is only for optimizing out
3263 unnecessary segment overrides. */
3264 const seg_entry *default_seg = 0;
3265
3266 /* The imul $imm, %reg instruction is converted into
3267 imul $imm, %reg, %reg, and the clr %reg instruction
3268 is converted into xor %reg, %reg. */
3269 if (i.tm.opcode_modifier & regKludge)
3270 {
3271 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3272 /* Pretend we saw the extra register operand. */
cab737b9
L		 3273 assert (i.reg_operands == 1
3274 && i.op[first_reg_op + 1].regs == 0);
29b0f896
AM		 3275 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3276 i.types[first_reg_op + 1] = i.types[first_reg_op];
cab737b9
L		 3277 i.operands++;
3278 i.reg_operands++;
29b0f896
AM		 3279 }
3280
3281 if (i.tm.opcode_modifier & ShortForm)
3282 {
4eed87de 3283 if (i.types[0] & (SReg2 | SReg3))
29b0f896 3284 {
4eed87de
AM		 3285 if (i.tm.base_opcode == POP_SEG_SHORT
3286 && i.op[0].regs->reg_num == 1)
29b0f896 3287 {
4eed87de
AM		 3288 as_bad (_("you can't `pop %%cs'"));
3289 return 0;
29b0f896 3290 }
4eed87de
AM		 3291 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3292 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3293 i.rex |= REX_EXTZ;
3294 }
3295 else
3296 {
3297 /* The register or float register operand is in operand 0 or 1. */
3298 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3299 /* Register goes in low 3 bits of opcode. */
3300 i.tm.base_opcode |= i.op[op].regs->reg_num;
3301 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3302 i.rex |= REX_EXTZ;
3303 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
29b0f896 3304 {
4eed87de
AM		 3305 /* Warn about some common errors, but press on regardless.
3306 The first case can be generated by gcc (<= 2.8.1). */
3307 if (i.operands == 2)
3308 {
3309 /* Reversed arguments on faddp, fsubp, etc. */
3310 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3311 i.op[1].regs->reg_name,
3312 i.op[0].regs->reg_name);
3313 }
3314 else
3315 {
3316 /* Extraneous `l' suffix on fp insn. */
3317 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3318 i.op[0].regs->reg_name);
3319 }
29b0f896
AM		 3320 }
3321 }
3322 }
3323 else if (i.tm.opcode_modifier & Modrm)
3324 {
3325 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3326 must be put into the modrm byte). Now, we make the modrm and
3327 index base bytes based on all the info we've collected. */
29b0f896
AM		 3328
3329 default_seg = build_modrm_byte ();
3330 }
8a2ed489 3331 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 3332 {
3333 default_seg = &ds;
3334 }
3335 else if ((i.tm.opcode_modifier & IsString) != 0)
3336 {
3337 /* For the string instructions that allow a segment override
3338 on one of their operands, the default segment is ds. */
3339 default_seg = &ds;
3340 }
3341
30123838
JB		 3342 if ((i.tm.base_opcode == 0x8d /* lea */
3343 || (i.tm.cpu_flags & CpuSVME))
3344 && i.seg[0] && !quiet_warnings)
3345 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3346
3347 /* If a segment was explicitly specified, and the specified segment
3348 is not the default, use an opcode prefix to select it. If we
3349 never figured out what the default segment is, then default_seg
3350 will be zero at this point, and the specified segment prefix will
3351 always be used. */
29b0f896
AM		 3352 if ((i.seg[0]) && (i.seg[0] != default_seg))
3353 {
3354 if (!add_prefix (i.seg[0]->seg_prefix))
3355 return 0;
3356 }
3357 return 1;
3358}
3359
3360static const seg_entry *
e3bb37b5 3361build_modrm_byte (void)
29b0f896
AM		 3362{
3363 const seg_entry *default_seg = 0;
3364
3365 /* i.reg_operands MUST be the number of real register operands;
3366 implicit registers do not count. */
3367 if (i.reg_operands == 2)
3368 {
3369 unsigned int source, dest;
cab737b9
L		 3370
3371 switch (i.operands)
3372 {
3373 case 2:
3374 source = 0;
3375 break;
3376 case 3:
c81128dc
L		 3377 /* When there are 3 operands, one of them may be immediate,
3378 which may be the first or the last operand. Otherwise,
3379 the first operand must be shift count register (cl). */
3380 assert (i.imm_operands == 1
3381 || (i.imm_operands == 0
3382 && (i.types[0] & ShiftCount)));
3383 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
cab737b9
L		 3384 break;
3385 case 4:
3386 /* When there are 4 operands, the first two must be immediate
3387 operands. The source operand will be the 3rd one. */
3388 assert (i.imm_operands == 2
3389 && (i.types[0] & Imm)
3390 && (i.types[1] & Imm));
3391 source = 2;
3392 break;
3393 default:
3394 abort ();
3395 }
3396
29b0f896
AM		 3397 dest = source + 1;
3398
3399 i.rm.mode = 3;
3400 /* One of the register operands will be encoded in the i.tm.reg
3401 field, the other in the combined i.tm.mode and i.tm.regmem
3402 fields. If no form of this instruction supports a memory
3403 destination operand, then we assume the source operand may
3404 sometimes be a memory operand and so we need to store the
3405 destination in the i.rm.reg field. */
3406 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3407 {
3408 i.rm.reg = i.op[dest].regs->reg_num;
3409 i.rm.regmem = i.op[source].regs->reg_num;
3410 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3411 i.rex |= REX_EXTX;
3412 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3413 i.rex |= REX_EXTZ;
3414 }
3415 else
3416 {
3417 i.rm.reg = i.op[source].regs->reg_num;
3418 i.rm.regmem = i.op[dest].regs->reg_num;
3419 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3420 i.rex |= REX_EXTZ;
3421 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3422 i.rex |= REX_EXTX;
3423 }
c4a530c5
JB		 3424 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3425 {
3426 if (!((i.types[0] | i.types[1]) & Control))
3427 abort ();
3428 i.rex &= ~(REX_EXTX | REX_EXTZ);
3429 add_prefix (LOCK_PREFIX_OPCODE);
3430 }
29b0f896
AM		 3431 }
3432 else
3433 { /* If it's not 2 reg operands... */
3434 if (i.mem_operands)
3435 {
3436 unsigned int fake_zero_displacement = 0;
99018f42 3437 unsigned int op;
4eed87de 3438
99018f42
L		 3439 for (op = 0; op < i.operands; op++)
3440 if ((i.types[op] & AnyMem))
3441 break;
3442 assert (op < i.operands);
29b0f896
AM		 3443
3444 default_seg = &ds;
3445
3446 if (i.base_reg == 0)
3447 {
3448 i.rm.mode = 0;
3449 if (!i.disp_operands)
3450 fake_zero_displacement = 1;
3451 if (i.index_reg == 0)
3452 {
3453 /* Operand is just <disp> */
20f0a1fc 3454 if (flag_code == CODE_64BIT)
29b0f896
AM		 3455 {
3456 /* 64bit mode overwrites the 32bit absolute
3457 addressing by RIP relative addressing and
3458 absolute addressing is encoded by one of the
3459 redundant SIB forms. */
3460 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3461 i.sib.base = NO_BASE_REGISTER;
3462 i.sib.index = NO_INDEX_REGISTER;
fc225355
L		 3463 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3464 ? Disp32S : Disp32);
20f0a1fc 3465 }
fc225355
L		 3466 else if ((flag_code == CODE_16BIT)
3467 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 3468 {
3469 i.rm.regmem = NO_BASE_REGISTER_16;
3470 i.types[op] = Disp16;
3471 }
3472 else
3473 {
3474 i.rm.regmem = NO_BASE_REGISTER;
3475 i.types[op] = Disp32;
29b0f896
AM		 3476 }
3477 }
3478 else /* !i.base_reg && i.index_reg */
3479 {
3480 i.sib.index = i.index_reg->reg_num;
3481 i.sib.base = NO_BASE_REGISTER;
3482 i.sib.scale = i.log2_scale_factor;
3483 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3484 i.types[op] &= ~Disp;
3485 if (flag_code != CODE_64BIT)
3486 i.types[op] |= Disp32; /* Must be 32 bit */
3487 else
3488 i.types[op] |= Disp32S;
3489 if ((i.index_reg->reg_flags & RegRex) != 0)
3490 i.rex |= REX_EXTY;
3491 }
3492 }
3493 /* RIP addressing for 64bit mode. */
3494 else if (i.base_reg->reg_type == BaseIndex)
3495 {
3496 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3497 i.types[op] &= ~ Disp;
29b0f896 3498 i.types[op] |= Disp32S;
71903a11 3499 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3500 if (! i.disp_operands)
3501 fake_zero_displacement = 1;
29b0f896
AM		 3502 }
3503 else if (i.base_reg->reg_type & Reg16)
3504 {
3505 switch (i.base_reg->reg_num)
3506 {
3507 case 3: /* (%bx) */
3508 if (i.index_reg == 0)
3509 i.rm.regmem = 7;
3510 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3511 i.rm.regmem = i.index_reg->reg_num - 6;
3512 break;
3513 case 5: /* (%bp) */
3514 default_seg = &ss;
3515 if (i.index_reg == 0)
3516 {
3517 i.rm.regmem = 6;
3518 if ((i.types[op] & Disp) == 0)
3519 {
3520 /* fake (%bp) into 0(%bp) */
3521 i.types[op] |= Disp8;
252b5132 3522 fake_zero_displacement = 1;
29b0f896
AM		 3523 }
3524 }
3525 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3526 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3527 break;
3528 default: /* (%si) -> 4 or (%di) -> 5 */
3529 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3530 }
3531 i.rm.mode = mode_from_disp_size (i.types[op]);
3532 }
3533 else /* i.base_reg and 32/64 bit mode */
3534 {
3535 if (flag_code == CODE_64BIT
3536 && (i.types[op] & Disp))
fc225355
L		 3537 i.types[op] = ((i.types[op] & Disp8)
3538 | (i.prefix[ADDR_PREFIX] == 0
3539 ? Disp32S : Disp32));
20f0a1fc 3540
29b0f896
AM		 3541 i.rm.regmem = i.base_reg->reg_num;
3542 if ((i.base_reg->reg_flags & RegRex) != 0)
3543 i.rex |= REX_EXTZ;
3544 i.sib.base = i.base_reg->reg_num;
3545 /* x86-64 ignores REX prefix bit here to avoid decoder
3546 complications. */
3547 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3548 {
3549 default_seg = &ss;
3550 if (i.disp_operands == 0)
3551 {
3552 fake_zero_displacement = 1;
3553 i.types[op] |= Disp8;
3554 }
3555 }
3556 else if (i.base_reg->reg_num == ESP_REG_NUM)
3557 {
3558 default_seg = &ss;
3559 }
3560 i.sib.scale = i.log2_scale_factor;
3561 if (i.index_reg == 0)
3562 {
3563 /* <disp>(%esp) becomes two byte modrm with no index
3564 register. We've already stored the code for esp
3565 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3566 Any base register besides %esp will not use the
3567 extra modrm byte. */
3568 i.sib.index = NO_INDEX_REGISTER;
3569#if !SCALE1_WHEN_NO_INDEX
3570 /* Another case where we force the second modrm byte. */
3571 if (i.log2_scale_factor)
3572 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3573#endif
29b0f896
AM		 3574 }
3575 else
3576 {
3577 i.sib.index = i.index_reg->reg_num;
3578 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3579 if ((i.index_reg->reg_flags & RegRex) != 0)
3580 i.rex |= REX_EXTY;
3581 }
67a4f2b7
AO		 3582
3583 if (i.disp_operands
3584 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3585 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3586 i.rm.mode = 0;
3587 else
3588 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3589 }
252b5132 3590
29b0f896
AM		 3591 if (fake_zero_displacement)
3592 {
3593 /* Fakes a zero displacement assuming that i.types[op]
3594 holds the correct displacement size. */
3595 expressionS *exp;
3596
3597 assert (i.op[op].disps == 0);
3598 exp = &disp_expressions[i.disp_operands++];
3599 i.op[op].disps = exp;
3600 exp->X_op = O_constant;
3601 exp->X_add_number = 0;
3602 exp->X_add_symbol = (symbolS *) 0;
3603 exp->X_op_symbol = (symbolS *) 0;
3604 }
3605 }
252b5132 3606
29b0f896
AM		 3607 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3608 (if any) based on i.tm.extension_opcode. Again, we must be
3609 careful to make sure that segment/control/debug/test/MMX
3610 registers are coded into the i.rm.reg field. */
3611 if (i.reg_operands)
3612 {
99018f42
L		 3613 unsigned int op;
3614
3615 for (op = 0; op < i.operands; op++)
3616 if ((i.types[op] & (Reg | RegMMX | RegXMM
3617 | SReg2 | SReg3
3618 | Control | Debug | Test)))
3619 break;
3620 assert (op < i.operands);
3621
29b0f896
AM		 3622 /* If there is an extension opcode to put here, the register
3623 number must be put into the regmem field. */
3624 if (i.tm.extension_opcode != None)
3625 {
3626 i.rm.regmem = i.op[op].regs->reg_num;
3627 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3628 i.rex |= REX_EXTZ;
3629 }
3630 else
3631 {
3632 i.rm.reg = i.op[op].regs->reg_num;
3633 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3634 i.rex |= REX_EXTX;
3635 }
252b5132 3636
29b0f896
AM		 3637 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3638 must set it to 3 to indicate this is a register operand
3639 in the regmem field. */
3640 if (!i.mem_operands)
3641 i.rm.mode = 3;
3642 }
252b5132 3643
29b0f896
AM		 3644 /* Fill in i.rm.reg field with extension opcode (if any). */
3645 if (i.tm.extension_opcode != None)
3646 i.rm.reg = i.tm.extension_opcode;
3647 }
3648 return default_seg;
3649}
252b5132 3650
29b0f896 3651static void
e3bb37b5 3652output_branch (void)
29b0f896
AM		 3653{
3654 char *p;
3655 int code16;
3656 int prefix;
3657 relax_substateT subtype;
3658 symbolS *sym;
3659 offsetT off;
3660
3661 code16 = 0;
3662 if (flag_code == CODE_16BIT)
3663 code16 = CODE16;
3664
3665 prefix = 0;
3666 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3667 {
29b0f896
AM		 3668 prefix = 1;
3669 i.prefixes -= 1;
3670 code16 ^= CODE16;
252b5132 3671 }
29b0f896
AM		 3672 /* Pentium4 branch hints. */
3673 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3674 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3675 {
29b0f896
AM		 3676 prefix++;
3677 i.prefixes--;
3678 }
3679 if (i.prefix[REX_PREFIX] != 0)
3680 {
3681 prefix++;
3682 i.prefixes--;
2f66722d
AM		 3683 }
3684
29b0f896
AM		 3685 if (i.prefixes != 0 && !intel_syntax)
3686 as_warn (_("skipping prefixes on this instruction"));
3687
3688 /* It's always a symbol; End frag & setup for relax.
3689 Make sure there is enough room in this frag for the largest
3690 instruction we may generate in md_convert_frag. This is 2
3691 bytes for the opcode and room for the prefix and largest
3692 displacement. */
3693 frag_grow (prefix + 2 + 4);
3694 /* Prefix and 1 opcode byte go in fr_fix. */
3695 p = frag_more (prefix + 1);
3696 if (i.prefix[DATA_PREFIX] != 0)
3697 *p++ = DATA_PREFIX_OPCODE;
3698 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3699 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3700 *p++ = i.prefix[SEG_PREFIX];
3701 if (i.prefix[REX_PREFIX] != 0)
3702 *p++ = i.prefix[REX_PREFIX];
3703 *p = i.tm.base_opcode;
3704
3705 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3706 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3707 else if ((cpu_arch_flags & Cpu386) != 0)
3708 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3709 else
3710 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3711 subtype |= code16;
3e73aa7c 3712
29b0f896
AM		 3713 sym = i.op[0].disps->X_add_symbol;
3714 off = i.op[0].disps->X_add_number;
3e73aa7c 3715
29b0f896
AM		 3716 if (i.op[0].disps->X_op != O_constant
3717 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3718 {
29b0f896
AM		 3719 /* Handle complex expressions. */
3720 sym = make_expr_symbol (i.op[0].disps);
3721 off = 0;
3722 }
3e73aa7c 3723
29b0f896
AM		 3724 /* 1 possible extra opcode + 4 byte displacement go in var part.
3725 Pass reloc in fr_var. */
3726 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3727}
3e73aa7c 3728
29b0f896 3729static void
e3bb37b5 3730output_jump (void)
29b0f896
AM		 3731{
3732 char *p;
3733 int size;
3e02c1cc 3734 fixS *fixP;
29b0f896
AM		 3735
3736 if (i.tm.opcode_modifier & JumpByte)
3737 {
3738 /* This is a loop or jecxz type instruction. */
3739 size = 1;
3740 if (i.prefix[ADDR_PREFIX] != 0)
3741 {
3742 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3743 i.prefixes -= 1;
3744 }
3745 /* Pentium4 branch hints. */
3746 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3747 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3748 {
3749 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3750 i.prefixes--;
3e73aa7c
JH		 3751 }
3752 }
29b0f896
AM		 3753 else
3754 {
3755 int code16;
3e73aa7c 3756
29b0f896
AM		 3757 code16 = 0;
3758 if (flag_code == CODE_16BIT)
3759 code16 = CODE16;
3e73aa7c 3760
29b0f896
AM		 3761 if (i.prefix[DATA_PREFIX] != 0)
3762 {
3763 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3764 i.prefixes -= 1;
3765 code16 ^= CODE16;
3766 }
252b5132 3767
29b0f896
AM		 3768 size = 4;
3769 if (code16)
3770 size = 2;
3771 }
9fcc94b6 3772
29b0f896
AM		 3773 if (i.prefix[REX_PREFIX] != 0)
3774 {
3775 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3776 i.prefixes -= 1;
3777 }
252b5132 3778
29b0f896
AM		 3779 if (i.prefixes != 0 && !intel_syntax)
3780 as_warn (_("skipping prefixes on this instruction"));
e0890092 3781
29b0f896
AM		 3782 p = frag_more (1 + size);
3783 *p++ = i.tm.base_opcode;
e0890092 3784
3e02c1cc
AM		 3785 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3786 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3787
3788 /* All jumps handled here are signed, but don't use a signed limit
3789 check for 32 and 16 bit jumps as we want to allow wrap around at
3790 4G and 64k respectively. */
3791 if (size == 1)
3792 fixP->fx_signed = 1;
29b0f896 3793}
e0890092 3794
29b0f896 3795static void
e3bb37b5 3796output_interseg_jump (void)
29b0f896
AM		 3797{
3798 char *p;
3799 int size;
3800 int prefix;
3801 int code16;
252b5132 3802
29b0f896
AM		 3803 code16 = 0;
3804 if (flag_code == CODE_16BIT)
3805 code16 = CODE16;
a217f122 3806
29b0f896
AM		 3807 prefix = 0;
3808 if (i.prefix[DATA_PREFIX] != 0)
3809 {
3810 prefix = 1;
3811 i.prefixes -= 1;
3812 code16 ^= CODE16;
3813 }
3814 if (i.prefix[REX_PREFIX] != 0)
3815 {
3816 prefix++;
3817 i.prefixes -= 1;
3818 }
252b5132 3819
29b0f896
AM		 3820 size = 4;
3821 if (code16)
3822 size = 2;
252b5132 3823
29b0f896
AM		 3824 if (i.prefixes != 0 && !intel_syntax)
3825 as_warn (_("skipping prefixes on this instruction"));
252b5132 3826
29b0f896
AM		 3827 /* 1 opcode; 2 segment; offset */
3828 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3829
29b0f896
AM		 3830 if (i.prefix[DATA_PREFIX] != 0)
3831 *p++ = DATA_PREFIX_OPCODE;
252b5132 3832
29b0f896
AM		 3833 if (i.prefix[REX_PREFIX] != 0)
3834 *p++ = i.prefix[REX_PREFIX];
252b5132 3835
29b0f896
AM		 3836 *p++ = i.tm.base_opcode;
3837 if (i.op[1].imms->X_op == O_constant)
3838 {
3839 offsetT n = i.op[1].imms->X_add_number;
252b5132 3840
29b0f896
AM		 3841 if (size == 2
3842 && !fits_in_unsigned_word (n)
3843 && !fits_in_signed_word (n))
3844 {
3845 as_bad (_("16-bit jump out of range"));
3846 return;
3847 }
3848 md_number_to_chars (p, n, size);
3849 }
3850 else
3851 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3852 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3853 if (i.op[0].imms->X_op != O_constant)
3854 as_bad (_("can't handle non absolute segment in `%s'"),
3855 i.tm.name);
3856 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3857}
a217f122 3858
29b0f896 3859static void
e3bb37b5 3860output_insn (void)
29b0f896 3861{
2bbd9c25
JJ		 3862 fragS *insn_start_frag;
3863 offsetT insn_start_off;
3864
29b0f896
AM		 3865 /* Tie dwarf2 debug info to the address at the start of the insn.
3866 We can't do this after the insn has been output as the current
3867 frag may have been closed off. eg. by frag_var. */
3868 dwarf2_emit_insn (0);
3869
2bbd9c25
JJ		 3870 insn_start_frag = frag_now;
3871 insn_start_off = frag_now_fix ();
3872
29b0f896
AM		 3873 /* Output jumps. */
3874 if (i.tm.opcode_modifier & Jump)
3875 output_branch ();
3876 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3877 output_jump ();
3878 else if (i.tm.opcode_modifier & JumpInterSegment)
3879 output_interseg_jump ();
3880 else
3881 {
3882 /* Output normal instructions here. */
3883 char *p;
3884 unsigned char *q;
331d2d0d 3885 unsigned int prefix;
252b5132 3886
ef05d495
L		 3887 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3888 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3889 use one more higher byte to specify a prefix the instruction
3890 requires. */
3891 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
bc4bd9ab 3892 {
331d2d0d
L		 3893 if (i.tm.base_opcode & 0xff000000)
3894 {
3895 prefix = (i.tm.base_opcode >> 24) & 0xff;
3896 goto check_prefix;
3897 }
3898 }
3899 else if ((i.tm.base_opcode & 0xff0000) != 0)
3900 {
3901 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3902 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3903 {
64e74474 3904 check_prefix:
bc4bd9ab
MK		 3905 if (prefix != REPE_PREFIX_OPCODE
3906 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3907 add_prefix (prefix);
3908 }
3909 else
331d2d0d 3910 add_prefix (prefix);
0f10071e 3911 }
252b5132 3912
29b0f896
AM		 3913 /* The prefix bytes. */
3914 for (q = i.prefix;
3915 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3916 q++)
3917 {
3918 if (*q)
3919 {
3920 p = frag_more (1);
3921 md_number_to_chars (p, (valueT) *q, 1);
3922 }
3923 }
252b5132 3924
29b0f896
AM		 3925 /* Now the opcode; be careful about word order here! */
3926 if (fits_in_unsigned_byte (i.tm.base_opcode))
3927 {
3928 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3929 }
3930 else
3931 {
ef05d495 3932 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
331d2d0d
L		 3933 {
3934 p = frag_more (3);
3935 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3936 }
3937 else
3938 p = frag_more (2);
0f10071e 3939
29b0f896
AM		 3940 /* Put out high byte first: can't use md_number_to_chars! */
3941 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3942 *p = i.tm.base_opcode & 0xff;
3943 }
3e73aa7c 3944
29b0f896
AM		 3945 /* Now the modrm byte and sib byte (if present). */
3946 if (i.tm.opcode_modifier & Modrm)
3947 {
3948 p = frag_more (1);
3949 md_number_to_chars (p,
3950 (valueT) (i.rm.regmem << 0
3951 | i.rm.reg << 3
3952 | i.rm.mode << 6),
3953 1);
3954 /* If i.rm.regmem == ESP (4)
3955 && i.rm.mode != (Register mode)
3956 && not 16 bit
3957 ==> need second modrm byte. */
3958 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3959 && i.rm.mode != 3
3960 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3961 {
3962 p = frag_more (1);
3963 md_number_to_chars (p,
3964 (valueT) (i.sib.base << 0
3965 | i.sib.index << 3
3966 | i.sib.scale << 6),
3967 1);
3968 }
3969 }
3e73aa7c 3970
29b0f896 3971 if (i.disp_operands)
2bbd9c25 3972 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3973
29b0f896 3974 if (i.imm_operands)
2bbd9c25 3975 output_imm (insn_start_frag, insn_start_off);
29b0f896 3976 }
252b5132 3977
29b0f896
AM		 3978#ifdef DEBUG386
3979 if (flag_debug)
3980 {
7b81dfbb 3981 pi ("" /*line*/, &i);
29b0f896
AM		 3982 }
3983#endif /* DEBUG386 */
3984}
252b5132 3985
29b0f896 3986static void
64e74474 3987output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 3988{
3989 char *p;
3990 unsigned int n;
252b5132 3991
29b0f896
AM		 3992 for (n = 0; n < i.operands; n++)
3993 {
3994 if (i.types[n] & Disp)
3995 {
3996 if (i.op[n].disps->X_op == O_constant)
3997 {
3998 int size;
3999 offsetT val;
252b5132 4000
29b0f896
AM		 4001 size = 4;
4002 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4003 {
4004 size = 2;
4005 if (i.types[n] & Disp8)
4006 size = 1;
4007 if (i.types[n] & Disp64)
4008 size = 8;
4009 }
4010 val = offset_in_range (i.op[n].disps->X_add_number,
4011 size);
4012 p = frag_more (size);
4013 md_number_to_chars (p, val, size);
4014 }
4015 else
4016 {
f86103b7 4017 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4018 int size = 4;
4019 int sign = 0;
4020 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4021
4022 /* The PC relative address is computed relative
4023 to the instruction boundary, so in case immediate
4024 fields follows, we need to adjust the value. */
4025 if (pcrel && i.imm_operands)
4026 {
4027 int imm_size = 4;
4028 unsigned int n1;
252b5132 4029
29b0f896
AM		 4030 for (n1 = 0; n1 < i.operands; n1++)
4031 if (i.types[n1] & Imm)
252b5132 4032 {
29b0f896 4033 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 4034 {
29b0f896
AM		 4035 imm_size = 2;
4036 if (i.types[n1] & (Imm8 | Imm8S))
4037 imm_size = 1;
4038 if (i.types[n1] & Imm64)
4039 imm_size = 8;
252b5132 4040 }
29b0f896 4041 break;
252b5132 4042 }
29b0f896
AM		 4043 /* We should find the immediate. */
4044 if (n1 == i.operands)
4045 abort ();
4046 i.op[n].disps->X_add_number -= imm_size;
4047 }
520dc8e8 4048
29b0f896
AM		 4049 if (i.types[n] & Disp32S)
4050 sign = 1;
3e73aa7c 4051
29b0f896
AM		 4052 if (i.types[n] & (Disp16 | Disp64))
4053 {
4054 size = 2;
4055 if (i.types[n] & Disp64)
4056 size = 8;
4057 }
520dc8e8 4058
29b0f896 4059 p = frag_more (size);
2bbd9c25 4060 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4061 if (GOT_symbol
2bbd9c25 4062 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4063 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4064 || reloc_type == BFD_RELOC_X86_64_32S
4065 || (reloc_type == BFD_RELOC_64
4066 && object_64bit))
d6ab8113
JB		 4067 && (i.op[n].disps->X_op == O_symbol
4068 || (i.op[n].disps->X_op == O_add
4069 && ((symbol_get_value_expression
4070 (i.op[n].disps->X_op_symbol)->X_op)
4071 == O_subtract))))
4072 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4073 {
4074 offsetT add;
4075
4076 if (insn_start_frag == frag_now)
4077 add = (p - frag_now->fr_literal) - insn_start_off;
4078 else
4079 {
4080 fragS *fr;
4081
4082 add = insn_start_frag->fr_fix - insn_start_off;
4083 for (fr = insn_start_frag->fr_next;
4084 fr && fr != frag_now; fr = fr->fr_next)
4085 add += fr->fr_fix;
4086 add += p - frag_now->fr_literal;
4087 }
4088
4fa24527 4089 if (!object_64bit)
7b81dfbb
AJ		 4090 {
4091 reloc_type = BFD_RELOC_386_GOTPC;
4092 i.op[n].imms->X_add_number += add;
4093 }
4094 else if (reloc_type == BFD_RELOC_64)
4095 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4096 else
7b81dfbb
AJ		 4097 /* Don't do the adjustment for x86-64, as there
4098 the pcrel addressing is relative to the _next_
4099 insn, and that is taken care of in other code. */
d6ab8113 4100 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4101 }
062cd5e7 4102 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4103 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4104 }
4105 }
4106 }
4107}
252b5132 4108
29b0f896 4109static void
64e74474 4110output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4111{
4112 char *p;
4113 unsigned int n;
252b5132 4114
29b0f896
AM		 4115 for (n = 0; n < i.operands; n++)
4116 {
4117 if (i.types[n] & Imm)
4118 {
4119 if (i.op[n].imms->X_op == O_constant)
4120 {
4121 int size;
4122 offsetT val;
b4cac588 4123
29b0f896
AM		 4124 size = 4;
4125 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4126 {
4127 size = 2;
4128 if (i.types[n] & (Imm8 | Imm8S))
4129 size = 1;
4130 else if (i.types[n] & Imm64)
4131 size = 8;
4132 }
4133 val = offset_in_range (i.op[n].imms->X_add_number,
4134 size);
4135 p = frag_more (size);
4136 md_number_to_chars (p, val, size);
4137 }
4138 else
4139 {
4140 /* Not absolute_section.
4141 Need a 32-bit fixup (don't support 8bit
4142 non-absolute imms). Try to support other
4143 sizes ... */
f86103b7 4144 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4145 int size = 4;
4146 int sign = 0;
4147
4148 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4149 && (i.suffix == QWORD_MNEM_SUFFIX
4150 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4151 sign = 1;
4152 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4153 {
4154 size = 2;
4155 if (i.types[n] & (Imm8 | Imm8S))
4156 size = 1;
4157 if (i.types[n] & Imm64)
4158 size = 8;
4159 }
520dc8e8 4160
29b0f896
AM		 4161 p = frag_more (size);
4162 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4163
2bbd9c25
JJ		 4164 /* This is tough to explain. We end up with this one if we
4165 * have operands that look like
4166 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4167 * obtain the absolute address of the GOT, and it is strongly
4168 * preferable from a performance point of view to avoid using
4169 * a runtime relocation for this. The actual sequence of
4170 * instructions often look something like:
4171 *
4172 * call .L66
4173 * .L66:
4174 * popl %ebx
4175 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4176 *
4177 * The call and pop essentially return the absolute address
4178 * of the label .L66 and store it in %ebx. The linker itself
4179 * will ultimately change the first operand of the addl so
4180 * that %ebx points to the GOT, but to keep things simple, the
4181 * .o file must have this operand set so that it generates not
4182 * the absolute address of .L66, but the absolute address of
4183 * itself. This allows the linker itself simply treat a GOTPC
4184 * relocation as asking for a pcrel offset to the GOT to be
4185 * added in, and the addend of the relocation is stored in the
4186 * operand field for the instruction itself.
4187 *
4188 * Our job here is to fix the operand so that it would add
4189 * the correct offset so that %ebx would point to itself. The
4190 * thing that is tricky is that .-.L66 will point to the
4191 * beginning of the instruction, so we need to further modify
4192 * the operand so that it will point to itself. There are
4193 * other cases where you have something like:
4194 *
4195 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4196 *
4197 * and here no correction would be required. Internally in
4198 * the assembler we treat operands of this form as not being
4199 * pcrel since the '.' is explicitly mentioned, and I wonder
4200 * whether it would simplify matters to do it this way. Who
4201 * knows. In earlier versions of the PIC patches, the
4202 * pcrel_adjust field was used to store the correction, but
4203 * since the expression is not pcrel, I felt it would be
4204 * confusing to do it this way. */
4205
d6ab8113 4206 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4207 || reloc_type == BFD_RELOC_X86_64_32S
4208 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4209 && GOT_symbol
4210 && GOT_symbol == i.op[n].imms->X_add_symbol
4211 && (i.op[n].imms->X_op == O_symbol
4212 || (i.op[n].imms->X_op == O_add
4213 && ((symbol_get_value_expression
4214 (i.op[n].imms->X_op_symbol)->X_op)
4215 == O_subtract))))
4216 {
2bbd9c25
JJ		 4217 offsetT add;
4218
4219 if (insn_start_frag == frag_now)
4220 add = (p - frag_now->fr_literal) - insn_start_off;
4221 else
4222 {
4223 fragS *fr;
4224
4225 add = insn_start_frag->fr_fix - insn_start_off;
4226 for (fr = insn_start_frag->fr_next;
4227 fr && fr != frag_now; fr = fr->fr_next)
4228 add += fr->fr_fix;
4229 add += p - frag_now->fr_literal;
4230 }
4231
4fa24527 4232 if (!object_64bit)
d6ab8113 4233 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4234 else if (size == 4)
d6ab8113 4235 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4236 else if (size == 8)
4237 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4238 i.op[n].imms->X_add_number += add;
29b0f896 4239 }
29b0f896
AM		 4240 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4241 i.op[n].imms, 0, reloc_type);
4242 }
4243 }
4244 }
252b5132
RH		 4245}
4246\f
d182319b
JB		 4247/* x86_cons_fix_new is called via the expression parsing code when a
4248 reloc is needed. We use this hook to get the correct .got reloc. */
4249static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4250static int cons_sign = -1;
4251
4252void
e3bb37b5 4253x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 4254 expressionS *exp)
d182319b
JB		 4255{
4256 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4257
4258 got_reloc = NO_RELOC;
4259
4260#ifdef TE_PE
4261 if (exp->X_op == O_secrel)
4262 {
4263 exp->X_op = O_symbol;
4264 r = BFD_RELOC_32_SECREL;
4265 }
4266#endif
4267
4268 fix_new_exp (frag, off, len, exp, 0, r);
4269}
4270
718ddfc0
JB		 4271#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4272# define lex_got(reloc, adjust, types) NULL
4273#else
f3c180ae
AM		 4274/* Parse operands of the form
4275 <symbol>@GOTOFF+<nnn>
4276 and similar .plt or .got references.
4277
4278 If we find one, set up the correct relocation in RELOC and copy the
4279 input string, minus the `@GOTOFF' into a malloc'd buffer for
4280 parsing by the calling routine. Return this buffer, and if ADJUST
4281 is non-null set it to the length of the string we removed from the
4282 input line. Otherwise return NULL. */
4283static char *
3956db08 4284lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4285 int *adjust,
4286 unsigned int *types)
f3c180ae 4287{
7b81dfbb
AJ		 4288 /* Some of the relocations depend on the size of what field is to
4289 be relocated. But in our callers i386_immediate and i386_displacement
4290 we don't yet know the operand size (this will be set by insn
4291 matching). Hence we record the word32 relocation here,
4292 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4293 static const struct {
4294 const char *str;
4fa24527 4295 const enum bfd_reloc_code_real rel[2];
3956db08 4296 const unsigned int types64;
f3c180ae 4297 } gotrel[] = {
4eed87de
AM		 4298 { "PLTOFF", { 0,
4299 BFD_RELOC_X86_64_PLTOFF64 },
4300 Imm64 },
4301 { "PLT", { BFD_RELOC_386_PLT32,
4302 BFD_RELOC_X86_64_PLT32 },
4303 Imm32 | Imm32S | Disp32 },
4304 { "GOTPLT", { 0,
4305 BFD_RELOC_X86_64_GOTPLT64 },
4306 Imm64 | Disp64 },
4307 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
4308 BFD_RELOC_X86_64_GOTOFF64 },
4309 Imm64 | Disp64 },
4310 { "GOTPCREL", { 0,
4311 BFD_RELOC_X86_64_GOTPCREL },
4312 Imm32 | Imm32S | Disp32 },
4313 { "TLSGD", { BFD_RELOC_386_TLS_GD,
4314 BFD_RELOC_X86_64_TLSGD },
4315 Imm32 | Imm32S | Disp32 },
4316 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
4317 0 },
4318 0 },
4319 { "TLSLD", { 0,
4320 BFD_RELOC_X86_64_TLSLD },
4321 Imm32 | Imm32S | Disp32 },
4322 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
4323 BFD_RELOC_X86_64_GOTTPOFF },
4324 Imm32 | Imm32S | Disp32 },
4325 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
4326 BFD_RELOC_X86_64_TPOFF32 },
4327 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4328 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
4329 0 },
4330 0 },
4331 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
4332 BFD_RELOC_X86_64_DTPOFF32 },
4333 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4334 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
4335 0 },
4336 0 },
4337 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
4338 0 },
4339 0 },
4340 { "GOT", { BFD_RELOC_386_GOT32,
4341 BFD_RELOC_X86_64_GOT32 },
4342 Imm32 | Imm32S | Disp32 | Imm64 },
4343 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
4344 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
4345 Imm32 | Imm32S | Disp32 },
4346 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
4347 BFD_RELOC_X86_64_TLSDESC_CALL },
4348 Imm32 | Imm32S | Disp32 }
f3c180ae
AM		 4349 };
4350 char *cp;
4351 unsigned int j;
4352
718ddfc0
JB		 4353 if (!IS_ELF)
4354 return NULL;
4355
f3c180ae
AM		 4356 for (cp = input_line_pointer; *cp != '@'; cp++)
4357 if (is_end_of_line[(unsigned char) *cp])
4358 return NULL;
4359
4360 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4361 {
4362 int len;
4363
4364 len = strlen (gotrel[j].str);
28f81592 4365 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4366 {
4fa24527 4367 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4368 {
28f81592
AM		 4369 int first, second;
4370 char *tmpbuf, *past_reloc;
f3c180ae 4371
4fa24527 4372 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4373 if (adjust)
4374 *adjust = len;
f3c180ae 4375
3956db08
JB		 4376 if (types)
4377 {
4378 if (flag_code != CODE_64BIT)
4eed87de 4379 *types = Imm32 | Disp32;
3956db08
JB		 4380 else
4381 *types = gotrel[j].types64;
4382 }
4383
f3c180ae
AM		 4384 if (GOT_symbol == NULL)
4385 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4386
4387 /* Replace the relocation token with ' ', so that
4388 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4389
4390 /* The length of the first part of our input line. */
f3c180ae 4391 first = cp - input_line_pointer;
28f81592
AM		 4392
4393 /* The second part goes from after the reloc token until
4394 (and including) an end_of_line char. Don't use strlen
4395 here as the end_of_line char may not be a NUL. */
4396 past_reloc = cp + 1 + len;
4397 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4398 ;
4399 second = cp - past_reloc;
4400
4401 /* Allocate and copy string. The trailing NUL shouldn't
4402 be necessary, but be safe. */
4403 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4404 memcpy (tmpbuf, input_line_pointer, first);
4405 tmpbuf[first] = ' ';
28f81592
AM		 4406 memcpy (tmpbuf + first + 1, past_reloc, second);
4407 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4408 return tmpbuf;
4409 }
4410
4fa24527
JB		 4411 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4412 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4413 return NULL;
4414 }
4415 }
4416
4417 /* Might be a symbol version string. Don't as_bad here. */
4418 return NULL;
4419}
4420
f3c180ae 4421void
e3bb37b5 4422x86_cons (expressionS *exp, int size)
f3c180ae 4423{
4fa24527 4424 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4425 {
4426 /* Handle @GOTOFF and the like in an expression. */
4427 char *save;
4428 char *gotfree_input_line;
4429 int adjust;
4430
4431 save = input_line_pointer;
3956db08 4432 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4433 if (gotfree_input_line)
4434 input_line_pointer = gotfree_input_line;
4435
4436 expression (exp);
4437
4438 if (gotfree_input_line)
4439 {
4440 /* expression () has merrily parsed up to the end of line,
4441 or a comma - in the wrong buffer. Transfer how far
4442 input_line_pointer has moved to the right buffer. */
4443 input_line_pointer = (save
4444 + (input_line_pointer - gotfree_input_line)
4445 + adjust);
4446 free (gotfree_input_line);
4447 }
4448 }
4449 else
4450 expression (exp);
4451}
4452#endif
4453
d182319b 4454static void signed_cons (int size)
6482c264 4455{
d182319b
JB		 4456 if (flag_code == CODE_64BIT)
4457 cons_sign = 1;
4458 cons (size);
4459 cons_sign = -1;
6482c264
NC		 4460}
4461
d182319b 4462#ifdef TE_PE
6482c264
NC		 4463static void
4464pe_directive_secrel (dummy)
4465 int dummy ATTRIBUTE_UNUSED;
4466{
4467 expressionS exp;
4468
4469 do
4470 {
4471 expression (&exp);
4472 if (exp.X_op == O_symbol)
4473 exp.X_op = O_secrel;
4474
4475 emit_expr (&exp, 4);
4476 }
4477 while (*input_line_pointer++ == ',');
4478
4479 input_line_pointer--;
4480 demand_empty_rest_of_line ();
4481}
6482c264
NC		 4482#endif
4483
252b5132 4484static int
70e41ade 4485i386_immediate (char *imm_start)
252b5132
RH		 4486{
4487 char *save_input_line_pointer;
f3c180ae 4488 char *gotfree_input_line;
252b5132 4489 segT exp_seg = 0;
47926f60 4490 expressionS *exp;
3956db08 4491 unsigned int types = ~0U;
252b5132
RH		 4492
4493 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4494 {
31b2323c
L		 4495 as_bad (_("at most %d immediate operands are allowed"),
4496 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 4497 return 0;
4498 }
4499
4500 exp = &im_expressions[i.imm_operands++];
520dc8e8 4501 i.op[this_operand].imms = exp;
252b5132
RH		 4502
4503 if (is_space_char (*imm_start))
4504 ++imm_start;
4505
4506 save_input_line_pointer = input_line_pointer;
4507 input_line_pointer = imm_start;
4508
3956db08 4509 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4510 if (gotfree_input_line)
4511 input_line_pointer = gotfree_input_line;
252b5132
RH		 4512
4513 exp_seg = expression (exp);
4514
83183c0c 4515 SKIP_WHITESPACE ();
252b5132 4516 if (*input_line_pointer)
f3c180ae 4517 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4518
4519 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4520 if (gotfree_input_line)
4521 free (gotfree_input_line);
252b5132 4522
2daf4fd8 4523 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4524 {
47926f60 4525 /* Missing or bad expr becomes absolute 0. */
d0b47220 4526 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4527 imm_start);
252b5132
RH		 4528 exp->X_op = O_constant;
4529 exp->X_add_number = 0;
4530 exp->X_add_symbol = (symbolS *) 0;
4531 exp->X_op_symbol = (symbolS *) 0;
252b5132 4532 }
3e73aa7c 4533 else if (exp->X_op == O_constant)
252b5132 4534 {
47926f60 4535 /* Size it properly later. */
3e73aa7c
JH		 4536 i.types[this_operand] |= Imm64;
4537 /* If BFD64, sign extend val. */
4eed87de
AM		 4538 if (!use_rela_relocations
4539 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4540 exp->X_add_number
4541 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4542 }
4c63da97 4543#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4544 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4545 && exp_seg != absolute_section
47926f60 4546 && exp_seg != text_section
24eab124
AM		 4547 && exp_seg != data_section
4548 && exp_seg != bss_section
4549 && exp_seg != undefined_section
f86103b7 4550 && !bfd_is_com_section (exp_seg))
252b5132 4551 {
d0b47220 4552 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4553 return 0;
4554 }
4555#endif
bb8f5920
L		 4556 else if (!intel_syntax && exp->X_op == O_register)
4557 {
4558 as_bad (_("illegal immediate register operand %s"), imm_start);
4559 return 0;
4560 }
252b5132
RH		 4561 else
4562 {
4563 /* This is an address. The size of the address will be
24eab124 4564 determined later, depending on destination register,
3e73aa7c
JH		 4565 suffix, or the default for the section. */
4566 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4567 i.types[this_operand] &= types;
252b5132
RH		 4568 }
4569
4570 return 1;
4571}
4572
551c1ca1 4573static char *
e3bb37b5 4574i386_scale (char *scale)
252b5132 4575{
551c1ca1
AM		 4576 offsetT val;
4577 char *save = input_line_pointer;
252b5132 4578
551c1ca1
AM		 4579 input_line_pointer = scale;
4580 val = get_absolute_expression ();
4581
4582 switch (val)
252b5132 4583 {
551c1ca1 4584 case 1:
252b5132
RH		 4585 i.log2_scale_factor = 0;
4586 break;
551c1ca1 4587 case 2:
252b5132
RH		 4588 i.log2_scale_factor = 1;
4589 break;
551c1ca1 4590 case 4:
252b5132
RH		 4591 i.log2_scale_factor = 2;
4592 break;
551c1ca1 4593 case 8:
252b5132
RH		 4594 i.log2_scale_factor = 3;
4595 break;
4596 default:
a724f0f4
JB		 4597 {
4598 char sep = *input_line_pointer;
4599
4600 *input_line_pointer = '\0';
4601 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4602 scale);
4603 *input_line_pointer = sep;
4604 input_line_pointer = save;
4605 return NULL;
4606 }
252b5132 4607 }
29b0f896 4608 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4609 {
4610 as_warn (_("scale factor of %d without an index register"),
24eab124 4611 1 << i.log2_scale_factor);
252b5132
RH		 4612#if SCALE1_WHEN_NO_INDEX
4613 i.log2_scale_factor = 0;
4614#endif
4615 }
551c1ca1
AM		 4616 scale = input_line_pointer;
4617 input_line_pointer = save;
4618 return scale;
252b5132
RH		 4619}
4620
252b5132 4621static int
e3bb37b5 4622i386_displacement (char *disp_start, char *disp_end)
252b5132 4623{
29b0f896 4624 expressionS *exp;
252b5132
RH		 4625 segT exp_seg = 0;
4626 char *save_input_line_pointer;
f3c180ae 4627 char *gotfree_input_line;
e05278af 4628 int bigdisp, override;
3956db08 4629 unsigned int types = Disp;
252b5132 4630
31b2323c
L		 4631 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4632 {
4633 as_bad (_("at most %d displacement operands are allowed"),
4634 MAX_MEMORY_OPERANDS);
4635 return 0;
4636 }
4637
e05278af
JB		 4638 if ((i.types[this_operand] & JumpAbsolute)
4639 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4640 {
4641 bigdisp = Disp32;
4642 override = (i.prefix[ADDR_PREFIX] != 0);
4643 }
4644 else
4645 {
4646 /* For PC-relative branches, the width of the displacement
4647 is dependent upon data size, not address size. */
4648 bigdisp = 0;
4649 override = (i.prefix[DATA_PREFIX] != 0);
4650 }
3e73aa7c 4651 if (flag_code == CODE_64BIT)
7ecd2f8b 4652 {
e05278af 4653 if (!bigdisp)
64e74474
AM		 4654 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4655 ? Disp16
4656 : Disp32S | Disp32);
e05278af 4657 else if (!override)
3956db08 4658 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4659 }
e05278af
JB		 4660 else
4661 {
4662 if (!bigdisp)
4663 {
4664 if (!override)
4665 override = (i.suffix == (flag_code != CODE_16BIT
4666 ? WORD_MNEM_SUFFIX
4667 : LONG_MNEM_SUFFIX));
4668 bigdisp = Disp32;
4669 }
4670 if ((flag_code == CODE_16BIT) ^ override)
4671 bigdisp = Disp16;
4672 }
252b5132
RH		 4673 i.types[this_operand] |= bigdisp;
4674
4675 exp = &disp_expressions[i.disp_operands];
520dc8e8 4676 i.op[this_operand].disps = exp;
252b5132
RH		 4677 i.disp_operands++;
4678 save_input_line_pointer = input_line_pointer;
4679 input_line_pointer = disp_start;
4680 END_STRING_AND_SAVE (disp_end);
4681
4682#ifndef GCC_ASM_O_HACK
4683#define GCC_ASM_O_HACK 0
4684#endif
4685#if GCC_ASM_O_HACK
4686 END_STRING_AND_SAVE (disp_end + 1);
4687 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4688 && displacement_string_end[-1] == '+')
252b5132
RH		 4689 {
4690 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4691 constraint within gcc asm statements.
4692 For instance:
4693
4694 #define _set_tssldt_desc(n,addr,limit,type) \
4695 __asm__ __volatile__ ( \
4696 "movw %w2,%0\n\t" \
4697 "movw %w1,2+%0\n\t" \
4698 "rorl $16,%1\n\t" \
4699 "movb %b1,4+%0\n\t" \
4700 "movb %4,5+%0\n\t" \
4701 "movb $0,6+%0\n\t" \
4702 "movb %h1,7+%0\n\t" \
4703 "rorl $16,%1" \
4704 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4705
4706 This works great except that the output assembler ends
4707 up looking a bit weird if it turns out that there is
4708 no offset. You end up producing code that looks like:
4709
4710 #APP
4711 movw $235,(%eax)
4712 movw %dx,2+(%eax)
4713 rorl $16,%edx
4714 movb %dl,4+(%eax)
4715 movb $137,5+(%eax)
4716 movb $0,6+(%eax)
4717 movb %dh,7+(%eax)
4718 rorl $16,%edx
4719 #NO_APP
4720
47926f60 4721 So here we provide the missing zero. */
24eab124
AM		 4722
4723 *displacement_string_end = '0';
252b5132
RH		 4724 }
4725#endif
3956db08 4726 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4727 if (gotfree_input_line)
4728 input_line_pointer = gotfree_input_line;
252b5132 4729
24eab124 4730 exp_seg = expression (exp);
252b5132 4731
636c26b0
AM		 4732 SKIP_WHITESPACE ();
4733 if (*input_line_pointer)
4734 as_bad (_("junk `%s' after expression"), input_line_pointer);
4735#if GCC_ASM_O_HACK
4736 RESTORE_END_STRING (disp_end + 1);
4737#endif
4738 RESTORE_END_STRING (disp_end);
4739 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4740 if (gotfree_input_line)
4741 free (gotfree_input_line);
636c26b0 4742
24eab124
AM		 4743 /* We do this to make sure that the section symbol is in
4744 the symbol table. We will ultimately change the relocation
47926f60 4745 to be relative to the beginning of the section. */
1ae12ab7 4746 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4747 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4748 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4749 {
636c26b0
AM		 4750 if (exp->X_op != O_symbol)
4751 {
4752 as_bad (_("bad expression used with @%s"),
4753 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4754 ? "GOTPCREL"
4755 : "GOTOFF"));
4756 return 0;
4757 }
4758
e5cb08ac 4759 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4760 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4761 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4762 exp->X_op = O_subtract;
4763 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4764 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4765 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4766 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4767 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4768 else
29b0f896 4769 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4770 }
252b5132 4771
2daf4fd8
AM		 4772 if (exp->X_op == O_absent || exp->X_op == O_big)
4773 {
47926f60 4774 /* Missing or bad expr becomes absolute 0. */
d0b47220 4775 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4776 disp_start);
4777 exp->X_op = O_constant;
4778 exp->X_add_number = 0;
4779 exp->X_add_symbol = (symbolS *) 0;
4780 exp->X_op_symbol = (symbolS *) 0;
4781 }
4782
4c63da97 4783#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4784 if (exp->X_op != O_constant
45288df1 4785 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4786 && exp_seg != absolute_section
45288df1
AM		 4787 && exp_seg != text_section
4788 && exp_seg != data_section
4789 && exp_seg != bss_section
31312f95 4790 && exp_seg != undefined_section
f86103b7 4791 && !bfd_is_com_section (exp_seg))
24eab124 4792 {
d0b47220 4793 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4794 return 0;
4795 }
252b5132 4796#endif
3956db08
JB		 4797
4798 if (!(i.types[this_operand] & ~Disp))
4799 i.types[this_operand] &= types;
4800
252b5132
RH		 4801 return 1;
4802}
4803
eecb386c 4804/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4805 Return 1 on success, 0 on a failure. */
4806
252b5132 4807static int
e3bb37b5 4808i386_index_check (const char *operand_string)
252b5132 4809{
3e73aa7c 4810 int ok;
24eab124 4811#if INFER_ADDR_PREFIX
eecb386c
AM		 4812 int fudged = 0;
4813
24eab124
AM		 4814 tryprefix:
4815#endif
3e73aa7c 4816 ok = 1;
30123838
JB		 4817 if ((current_templates->start->cpu_flags & CpuSVME)
4818 && current_templates->end[-1].operand_types[0] == AnyMem)
4819 {
4820 /* Memory operands of SVME insns are special in that they only allow
4821 rAX as their memory address and ignore any segment override. */
4822 unsigned RegXX;
4823
4824 /* SKINIT is even more restrictive: it always requires EAX. */
4825 if (strcmp (current_templates->start->name, "skinit") == 0)
4826 RegXX = Reg32;
4827 else if (flag_code == CODE_64BIT)
4828 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4829 else
64e74474
AM		 4830 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4831 ? Reg16
4832 : Reg32);
30123838
JB		 4833 if (!i.base_reg
4834 || !(i.base_reg->reg_type & Acc)
4835 || !(i.base_reg->reg_type & RegXX)
4836 || i.index_reg
4837 || (i.types[0] & Disp))
4838 ok = 0;
4839 }
4840 else if (flag_code == CODE_64BIT)
64e74474
AM		 4841 {
4842 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4843
4844 if ((i.base_reg
4845 && ((i.base_reg->reg_type & RegXX) == 0)
4846 && (i.base_reg->reg_type != BaseIndex
4847 || i.index_reg))
4848 || (i.index_reg
4849 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4850 != (RegXX | BaseIndex))))
4851 ok = 0;
3e73aa7c
JH		 4852 }
4853 else
4854 {
4855 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4856 {
4857 /* 16bit checks. */
4858 if ((i.base_reg
29b0f896
AM		 4859 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4860 != (Reg16 | BaseIndex)))
3e73aa7c 4861 || (i.index_reg
29b0f896
AM		 4862 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4863 != (Reg16 | BaseIndex))
4864 || !(i.base_reg
4865 && i.base_reg->reg_num < 6
4866 && i.index_reg->reg_num >= 6
4867 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4868 ok = 0;
4869 }
4870 else
e5cb08ac 4871 {
3e73aa7c
JH		 4872 /* 32bit checks. */
4873 if ((i.base_reg
4874 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4875 || (i.index_reg
29b0f896
AM		 4876 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4877 != (Reg32 | BaseIndex))))
e5cb08ac 4878 ok = 0;
3e73aa7c
JH		 4879 }
4880 }
4881 if (!ok)
24eab124
AM		 4882 {
4883#if INFER_ADDR_PREFIX
20f0a1fc 4884 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4885 {
4886 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4887 i.prefixes += 1;
b23bac36
AM		 4888 /* Change the size of any displacement too. At most one of
4889 Disp16 or Disp32 is set.
4890 FIXME. There doesn't seem to be any real need for separate
4891 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4892 Removing them would probably clean up the code quite a lot. */
4eed87de
AM		 4893 if (flag_code != CODE_64BIT
4894 && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4895 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4896 fudged = 1;
24eab124
AM		 4897 goto tryprefix;
4898 }
eecb386c
AM		 4899 if (fudged)
4900 as_bad (_("`%s' is not a valid base/index expression"),
4901 operand_string);
4902 else
c388dee8 4903#endif
eecb386c
AM		 4904 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4905 operand_string,
3e73aa7c 4906 flag_code_names[flag_code]);
24eab124 4907 }
20f0a1fc 4908 return ok;
24eab124 4909}
252b5132 4910
252b5132 4911/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4912 on error. */
252b5132 4913
252b5132 4914static int
e3bb37b5 4915i386_operand (char *operand_string)
252b5132 4916{
af6bdddf
AM		 4917 const reg_entry *r;
4918 char *end_op;
24eab124 4919 char *op_string = operand_string;
252b5132 4920
24eab124 4921 if (is_space_char (*op_string))
252b5132
RH		 4922 ++op_string;
4923
24eab124 4924 /* We check for an absolute prefix (differentiating,
47926f60 4925 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4926 if (*op_string == ABSOLUTE_PREFIX)
4927 {
4928 ++op_string;
4929 if (is_space_char (*op_string))
4930 ++op_string;
4931 i.types[this_operand] |= JumpAbsolute;
4932 }
252b5132 4933
47926f60 4934 /* Check if operand is a register. */
4d1bb795 4935 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4936 {
24eab124
AM		 4937 /* Check for a segment override by searching for ':' after a
4938 segment register. */
4939 op_string = end_op;
4940 if (is_space_char (*op_string))
4941 ++op_string;
4942 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4943 {
4944 switch (r->reg_num)
4945 {
4946 case 0:
4947 i.seg[i.mem_operands] = &es;
4948 break;
4949 case 1:
4950 i.seg[i.mem_operands] = &cs;
4951 break;
4952 case 2:
4953 i.seg[i.mem_operands] = &ss;
4954 break;
4955 case 3:
4956 i.seg[i.mem_operands] = &ds;
4957 break;
4958 case 4:
4959 i.seg[i.mem_operands] = &fs;
4960 break;
4961 case 5:
4962 i.seg[i.mem_operands] = &gs;
4963 break;
4964 }
252b5132 4965
24eab124 4966 /* Skip the ':' and whitespace. */
252b5132
RH		 4967 ++op_string;
4968 if (is_space_char (*op_string))
24eab124 4969 ++op_string;
252b5132 4970
24eab124
AM		 4971 if (!is_digit_char (*op_string)
4972 && !is_identifier_char (*op_string)
4973 && *op_string != '('
4974 && *op_string != ABSOLUTE_PREFIX)
4975 {
4976 as_bad (_("bad memory operand `%s'"), op_string);
4977 return 0;
4978 }
47926f60 4979 /* Handle case of %es:*foo. */
24eab124
AM		 4980 if (*op_string == ABSOLUTE_PREFIX)
4981 {
4982 ++op_string;
4983 if (is_space_char (*op_string))
4984 ++op_string;
4985 i.types[this_operand] |= JumpAbsolute;
4986 }
4987 goto do_memory_reference;
4988 }
4989 if (*op_string)
4990 {
d0b47220 4991 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4992 return 0;
4993 }
4994 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4995 i.op[this_operand].regs = r;
24eab124
AM		 4996 i.reg_operands++;
4997 }
af6bdddf
AM		 4998 else if (*op_string == REGISTER_PREFIX)
4999 {
5000 as_bad (_("bad register name `%s'"), op_string);
5001 return 0;
5002 }
24eab124 5003 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5004 {
24eab124
AM		 5005 ++op_string;
5006 if (i.types[this_operand] & JumpAbsolute)
5007 {
d0b47220 5008 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5009 return 0;
5010 }
5011 if (!i386_immediate (op_string))
5012 return 0;
5013 }
5014 else if (is_digit_char (*op_string)
5015 || is_identifier_char (*op_string)
e5cb08ac 5016 || *op_string == '(')
24eab124 5017 {
47926f60 5018 /* This is a memory reference of some sort. */
af6bdddf 5019 char *base_string;
252b5132 5020
47926f60 5021 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5022 char *displacement_string_start;
5023 char *displacement_string_end;
252b5132 5024
24eab124 5025 do_memory_reference:
24eab124
AM		 5026 if ((i.mem_operands == 1
5027 && (current_templates->start->opcode_modifier & IsString) == 0)
5028 || i.mem_operands == 2)
5029 {
5030 as_bad (_("too many memory references for `%s'"),
5031 current_templates->start->name);
5032 return 0;
5033 }
252b5132 5034
24eab124
AM		 5035 /* Check for base index form. We detect the base index form by
5036 looking for an ')' at the end of the operand, searching
5037 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5038 after the '('. */
af6bdddf 5039 base_string = op_string + strlen (op_string);
c3332e24 5040
af6bdddf
AM		 5041 --base_string;
5042 if (is_space_char (*base_string))
5043 --base_string;
252b5132 5044
47926f60 5045 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5046 displacement_string_start = op_string;
5047 displacement_string_end = base_string + 1;
252b5132 5048
24eab124
AM		 5049 if (*base_string == ')')
5050 {
af6bdddf 5051 char *temp_string;
24eab124
AM		 5052 unsigned int parens_balanced = 1;
5053 /* We've already checked that the number of left & right ()'s are
47926f60 5054 equal, so this loop will not be infinite. */
24eab124
AM		 5055 do
5056 {
5057 base_string--;
5058 if (*base_string == ')')
5059 parens_balanced++;
5060 if (*base_string == '(')
5061 parens_balanced--;
5062 }
5063 while (parens_balanced);
c3332e24 5064
af6bdddf 5065 temp_string = base_string;
c3332e24 5066
24eab124 5067 /* Skip past '(' and whitespace. */
252b5132
RH		 5068 ++base_string;
5069 if (is_space_char (*base_string))
24eab124 5070 ++base_string;
252b5132 5071
af6bdddf 5072 if (*base_string == ','
4eed87de
AM		 5073 || ((i.base_reg = parse_register (base_string, &end_op))
5074 != NULL))
252b5132 5075 {
af6bdddf 5076 displacement_string_end = temp_string;
252b5132 5077
af6bdddf 5078 i.types[this_operand] |= BaseIndex;
252b5132 5079
af6bdddf 5080 if (i.base_reg)
24eab124 5081 {
24eab124
AM		 5082 base_string = end_op;
5083 if (is_space_char (*base_string))
5084 ++base_string;
af6bdddf
AM		 5085 }
5086
5087 /* There may be an index reg or scale factor here. */
5088 if (*base_string == ',')
5089 {
5090 ++base_string;
5091 if (is_space_char (*base_string))
5092 ++base_string;
5093
4eed87de
AM		 5094 if ((i.index_reg = parse_register (base_string, &end_op))
5095 != NULL)
24eab124 5096 {
af6bdddf 5097 base_string = end_op;
24eab124
AM		 5098 if (is_space_char (*base_string))
5099 ++base_string;
af6bdddf
AM		 5100 if (*base_string == ',')
5101 {
5102 ++base_string;
5103 if (is_space_char (*base_string))
5104 ++base_string;
5105 }
e5cb08ac 5106 else if (*base_string != ')')
af6bdddf 5107 {
4eed87de
AM		 5108 as_bad (_("expecting `,' or `)' "
5109 "after index register in `%s'"),
af6bdddf
AM		 5110 operand_string);
5111 return 0;
5112 }
24eab124 5113 }
af6bdddf 5114 else if (*base_string == REGISTER_PREFIX)
24eab124 5115 {
af6bdddf 5116 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5117 return 0;
5118 }
252b5132 5119
47926f60 5120 /* Check for scale factor. */
551c1ca1 5121 if (*base_string != ')')
af6bdddf 5122 {
551c1ca1
AM		 5123 char *end_scale = i386_scale (base_string);
5124
5125 if (!end_scale)
af6bdddf 5126 return 0;
24eab124 5127
551c1ca1 5128 base_string = end_scale;
af6bdddf
AM		 5129 if (is_space_char (*base_string))
5130 ++base_string;
5131 if (*base_string != ')')
5132 {
4eed87de
AM		 5133 as_bad (_("expecting `)' "
5134 "after scale factor in `%s'"),
af6bdddf
AM		 5135 operand_string);
5136 return 0;
5137 }
5138 }
5139 else if (!i.index_reg)
24eab124 5140 {
4eed87de
AM		 5141 as_bad (_("expecting index register or scale factor "
5142 "after `,'; got '%c'"),
af6bdddf 5143 *base_string);
24eab124
AM		 5144 return 0;
5145 }
5146 }
af6bdddf 5147 else if (*base_string != ')')
24eab124 5148 {
4eed87de
AM		 5149 as_bad (_("expecting `,' or `)' "
5150 "after base register in `%s'"),
af6bdddf 5151 operand_string);
24eab124
AM		 5152 return 0;
5153 }
c3332e24 5154 }
af6bdddf 5155 else if (*base_string == REGISTER_PREFIX)
c3332e24 5156 {
af6bdddf 5157 as_bad (_("bad register name `%s'"), base_string);
24eab124 5158 return 0;
c3332e24 5159 }
24eab124
AM		 5160 }
5161
5162 /* If there's an expression beginning the operand, parse it,
5163 assuming displacement_string_start and
5164 displacement_string_end are meaningful. */
5165 if (displacement_string_start != displacement_string_end)
5166 {
5167 if (!i386_displacement (displacement_string_start,
5168 displacement_string_end))
5169 return 0;
5170 }
5171
5172 /* Special case for (%dx) while doing input/output op. */
5173 if (i.base_reg
5174 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5175 && i.index_reg == 0
5176 && i.log2_scale_factor == 0
5177 && i.seg[i.mem_operands] == 0
5178 && (i.types[this_operand] & Disp) == 0)
5179 {
5180 i.types[this_operand] = InOutPortReg;
5181 return 1;
5182 }
5183
eecb386c
AM		 5184 if (i386_index_check (operand_string) == 0)
5185 return 0;
24eab124
AM		 5186 i.mem_operands++;
5187 }
5188 else
ce8a8b2f
AM		 5189 {
5190 /* It's not a memory operand; argh! */
24eab124
AM		 5191 as_bad (_("invalid char %s beginning operand %d `%s'"),
5192 output_invalid (*op_string),
5193 this_operand + 1,
5194 op_string);
5195 return 0;
5196 }
47926f60 5197 return 1; /* Normal return. */
252b5132
RH		 5198}
5199\f
ee7fcc42
AM		 5200/* md_estimate_size_before_relax()
5201
5202 Called just before relax() for rs_machine_dependent frags. The x86
5203 assembler uses these frags to handle variable size jump
5204 instructions.
5205
5206 Any symbol that is now undefined will not become defined.
5207 Return the correct fr_subtype in the frag.
5208 Return the initial "guess for variable size of frag" to caller.
5209 The guess is actually the growth beyond the fixed part. Whatever
5210 we do to grow the fixed or variable part contributes to our
5211 returned value. */
5212
252b5132
RH		 5213int
5214md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5215 fragS *fragP;
5216 segT segment;
252b5132 5217{
252b5132 5218 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5219 check for un-relaxable symbols. On an ELF system, we can't relax
5220 an externally visible symbol, because it may be overridden by a
5221 shared library. */
5222 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5223#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5224 || (IS_ELF
31312f95
AM		 5225 && (S_IS_EXTERNAL (fragP->fr_symbol)
5226 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5227#endif
5228 )
252b5132 5229 {
b98ef147
AM		 5230 /* Symbol is undefined in this segment, or we need to keep a
5231 reloc so that weak symbols can be overridden. */
5232 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5233 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5234 unsigned char *opcode;
5235 int old_fr_fix;
f6af82bd 5236
ee7fcc42
AM		 5237 if (fragP->fr_var != NO_RELOC)
5238 reloc_type = fragP->fr_var;
b98ef147 5239 else if (size == 2)
f6af82bd
AM		 5240 reloc_type = BFD_RELOC_16_PCREL;
5241 else
5242 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5243
ee7fcc42
AM		 5244 old_fr_fix = fragP->fr_fix;
5245 opcode = (unsigned char *) fragP->fr_opcode;
5246
fddf5b5b 5247 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5248 {
fddf5b5b
AM		 5249 case UNCOND_JUMP:
5250 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5251 opcode[0] = 0xe9;
252b5132 5252 fragP->fr_fix += size;
062cd5e7
AS		 5253 fix_new (fragP, old_fr_fix, size,
5254 fragP->fr_symbol,
5255 fragP->fr_offset, 1,
5256 reloc_type);
252b5132
RH		 5257 break;
5258
fddf5b5b 5259 case COND_JUMP86:
412167cb
AM		 5260 if (size == 2
5261 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5262 {
5263 /* Negate the condition, and branch past an
5264 unconditional jump. */
5265 opcode[0] ^= 1;
5266 opcode[1] = 3;
5267 /* Insert an unconditional jump. */
5268 opcode[2] = 0xe9;
5269 /* We added two extra opcode bytes, and have a two byte
5270 offset. */
5271 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5272 fix_new (fragP, old_fr_fix + 2, 2,
5273 fragP->fr_symbol,
5274 fragP->fr_offset, 1,
5275 reloc_type);
fddf5b5b
AM		 5276 break;
5277 }
5278 /* Fall through. */
5279
5280 case COND_JUMP:
412167cb
AM		 5281 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5282 {
3e02c1cc
AM		 5283 fixS *fixP;
5284
412167cb 5285 fragP->fr_fix += 1;
3e02c1cc
AM		 5286 fixP = fix_new (fragP, old_fr_fix, 1,
5287 fragP->fr_symbol,
5288 fragP->fr_offset, 1,
5289 BFD_RELOC_8_PCREL);
5290 fixP->fx_signed = 1;
412167cb
AM		 5291 break;
5292 }
93c2a809 5293
24eab124 5294 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5295 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5296 opcode[1] = opcode[0] + 0x10;
f6af82bd 5297 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5298 /* We've added an opcode byte. */
5299 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5300 fix_new (fragP, old_fr_fix + 1, size,
5301 fragP->fr_symbol,
5302 fragP->fr_offset, 1,
5303 reloc_type);
252b5132 5304 break;
fddf5b5b
AM		 5305
5306 default:
5307 BAD_CASE (fragP->fr_subtype);
5308 break;
252b5132
RH		 5309 }
5310 frag_wane (fragP);
ee7fcc42 5311 return fragP->fr_fix - old_fr_fix;
252b5132 5312 }
93c2a809 5313
93c2a809
AM		 5314 /* Guess size depending on current relax state. Initially the relax
5315 state will correspond to a short jump and we return 1, because
5316 the variable part of the frag (the branch offset) is one byte
5317 long. However, we can relax a section more than once and in that
5318 case we must either set fr_subtype back to the unrelaxed state,
5319 or return the value for the appropriate branch. */
5320 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5321}
5322
47926f60
KH		 5323/* Called after relax() is finished.
5324
5325 In: Address of frag.
5326 fr_type == rs_machine_dependent.
5327 fr_subtype is what the address relaxed to.
5328
5329 Out: Any fixSs and constants are set up.
5330 Caller will turn frag into a ".space 0". */
5331
252b5132
RH		 5332void
5333md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5334 bfd *abfd ATTRIBUTE_UNUSED;
5335 segT sec ATTRIBUTE_UNUSED;
29b0f896 5336 fragS *fragP;
252b5132 5337{
29b0f896 5338 unsigned char *opcode;
252b5132 5339 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5340 offsetT target_address;
5341 offsetT opcode_address;
252b5132 5342 unsigned int extension = 0;
847f7ad4 5343 offsetT displacement_from_opcode_start;
252b5132
RH		 5344
5345 opcode = (unsigned char *) fragP->fr_opcode;
5346
47926f60 5347 /* Address we want to reach in file space. */
252b5132 5348 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5349
47926f60 5350 /* Address opcode resides at in file space. */
252b5132
RH		 5351 opcode_address = fragP->fr_address + fragP->fr_fix;
5352
47926f60 5353 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5354 displacement_from_opcode_start = target_address - opcode_address;
5355
fddf5b5b 5356 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5357 {
47926f60
KH		 5358 /* Don't have to change opcode. */
5359 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5360 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5361 }
5362 else
5363 {
5364 if (no_cond_jump_promotion
5365 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 5366 as_warn_where (fragP->fr_file, fragP->fr_line,
5367 _("long jump required"));
252b5132 5368
fddf5b5b
AM		 5369 switch (fragP->fr_subtype)
5370 {
5371 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5372 extension = 4; /* 1 opcode + 4 displacement */
5373 opcode[0] = 0xe9;
5374 where_to_put_displacement = &opcode[1];
5375 break;
252b5132 5376
fddf5b5b
AM		 5377 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5378 extension = 2; /* 1 opcode + 2 displacement */
5379 opcode[0] = 0xe9;
5380 where_to_put_displacement = &opcode[1];
5381 break;
252b5132 5382
fddf5b5b
AM		 5383 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5384 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5385 extension = 5; /* 2 opcode + 4 displacement */
5386 opcode[1] = opcode[0] + 0x10;
5387 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5388 where_to_put_displacement = &opcode[2];
5389 break;
252b5132 5390
fddf5b5b
AM		 5391 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5392 extension = 3; /* 2 opcode + 2 displacement */
5393 opcode[1] = opcode[0] + 0x10;
5394 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5395 where_to_put_displacement = &opcode[2];
5396 break;
252b5132 5397
fddf5b5b
AM		 5398 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5399 extension = 4;
5400 opcode[0] ^= 1;
5401 opcode[1] = 3;
5402 opcode[2] = 0xe9;
5403 where_to_put_displacement = &opcode[3];
5404 break;
5405
5406 default:
5407 BAD_CASE (fragP->fr_subtype);
5408 break;
5409 }
252b5132 5410 }
fddf5b5b 5411
7b81dfbb
AJ		 5412 /* If size if less then four we are sure that the operand fits,
5413 but if it's 4, then it could be that the displacement is larger
5414 then -/+ 2GB. */
5415 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5416 && object_64bit
5417 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 5418 + ((addressT) 1 << 31))
5419 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 5420 {
5421 as_bad_where (fragP->fr_file, fragP->fr_line,
5422 _("jump target out of range"));
5423 /* Make us emit 0. */
5424 displacement_from_opcode_start = extension;
5425 }
47926f60 5426 /* Now put displacement after opcode. */
252b5132
RH		 5427 md_number_to_chars ((char *) where_to_put_displacement,
5428 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5429 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5430 fragP->fr_fix += extension;
5431}
5432\f
47926f60
KH		 5433/* Size of byte displacement jmp. */
5434int md_short_jump_size = 2;
5435
5436/* Size of dword displacement jmp. */
5437int md_long_jump_size = 5;
252b5132 5438
252b5132
RH		 5439void
5440md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5441 char *ptr;
5442 addressT from_addr, to_addr;
ab9da554
ILT		 5443 fragS *frag ATTRIBUTE_UNUSED;
5444 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5445{
847f7ad4 5446 offsetT offset;
252b5132
RH		 5447
5448 offset = to_addr - (from_addr + 2);
47926f60
KH		 5449 /* Opcode for byte-disp jump. */
5450 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5451 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5452}
5453
5454void
5455md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5456 char *ptr;
5457 addressT from_addr, to_addr;
a38cf1db
AM		 5458 fragS *frag ATTRIBUTE_UNUSED;
5459 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5460{
847f7ad4 5461 offsetT offset;
252b5132 5462
a38cf1db
AM		 5463 offset = to_addr - (from_addr + 5);
5464 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5465 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5466}
5467\f
5468/* Apply a fixup (fixS) to segment data, once it has been determined
5469 by our caller that we have all the info we need to fix it up.
5470
5471 On the 386, immediates, displacements, and data pointers are all in
5472 the same (little-endian) format, so we don't need to care about which
5473 we are handling. */
5474
94f592af 5475void
55cf6793 5476md_apply_fix (fixP, valP, seg)
47926f60
KH		 5477 /* The fix we're to put in. */
5478 fixS *fixP;
47926f60 5479 /* Pointer to the value of the bits. */
c6682705 5480 valueT *valP;
47926f60
KH		 5481 /* Segment fix is from. */
5482 segT seg ATTRIBUTE_UNUSED;
252b5132 5483{
94f592af 5484 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5485 valueT value = *valP;
252b5132 5486
f86103b7 5487#if !defined (TE_Mach)
93382f6d
AM		 5488 if (fixP->fx_pcrel)
5489 {
5490 switch (fixP->fx_r_type)
5491 {
5865bb77
ILT		 5492 default:
5493 break;
5494
d6ab8113
JB		 5495 case BFD_RELOC_64:
5496 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5497 break;
93382f6d 5498 case BFD_RELOC_32:
ae8887b5 5499 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5500 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5501 break;
5502 case BFD_RELOC_16:
5503 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5504 break;
5505 case BFD_RELOC_8:
5506 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5507 break;
5508 }
5509 }
252b5132 5510
a161fe53 5511 if (fixP->fx_addsy != NULL
31312f95 5512 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5513 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5514 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5515 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5516 && !use_rela_relocations)
252b5132 5517 {
31312f95
AM		 5518 /* This is a hack. There should be a better way to handle this.
5519 This covers for the fact that bfd_install_relocation will
5520 subtract the current location (for partial_inplace, PC relative
5521 relocations); see more below. */
252b5132 5522#ifndef OBJ_AOUT
718ddfc0 5523 if (IS_ELF
252b5132
RH		 5524#ifdef TE_PE
5525 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5526#endif
5527 )
5528 value += fixP->fx_where + fixP->fx_frag->fr_address;
5529#endif
5530#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5531 if (IS_ELF)
252b5132 5532 {
6539b54b 5533 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5534
6539b54b 5535 if ((sym_seg == seg
2f66722d 5536 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5537 && sym_seg != absolute_section))
ae6063d4 5538 && !generic_force_reloc (fixP))
2f66722d
AM		 5539 {
5540 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5541 bfd_install_relocation subtracts them out again. I think
5542 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5543 it. FIXME. */
5544 value += fixP->fx_where + fixP->fx_frag->fr_address;
5545 }
252b5132
RH		 5546 }
5547#endif
5548#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5549 /* For some reason, the PE format does not store a
5550 section address offset for a PC relative symbol. */
5551 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5552 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5553 value += md_pcrel_from (fixP);
5554#endif
5555 }
5556
5557 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5558 and we must not disappoint it. */
252b5132 5559#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5560 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5561 switch (fixP->fx_r_type)
5562 {
5563 case BFD_RELOC_386_PLT32:
3e73aa7c 5564 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5565 /* Make the jump instruction point to the address of the operand. At
5566 runtime we merely add the offset to the actual PLT entry. */
5567 value = -4;
5568 break;
31312f95 5569
13ae64f3
JJ		 5570 case BFD_RELOC_386_TLS_GD:
5571 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5572 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5573 case BFD_RELOC_386_TLS_IE:
5574 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5575 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5576 case BFD_RELOC_X86_64_TLSGD:
5577 case BFD_RELOC_X86_64_TLSLD:
5578 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5579 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5580 value = 0; /* Fully resolved at runtime. No addend. */
5581 /* Fallthrough */
5582 case BFD_RELOC_386_TLS_LE:
5583 case BFD_RELOC_386_TLS_LDO_32:
5584 case BFD_RELOC_386_TLS_LE_32:
5585 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5586 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5587 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5588 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5589 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5590 break;
5591
67a4f2b7
AO		 5592 case BFD_RELOC_386_TLS_DESC_CALL:
5593 case BFD_RELOC_X86_64_TLSDESC_CALL:
5594 value = 0; /* Fully resolved at runtime. No addend. */
5595 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5596 fixP->fx_done = 0;
5597 return;
5598
00f7efb6
JJ		 5599 case BFD_RELOC_386_GOT32:
5600 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5601 value = 0; /* Fully resolved at runtime. No addend. */
5602 break;
47926f60
KH		 5603
5604 case BFD_RELOC_VTABLE_INHERIT:
5605 case BFD_RELOC_VTABLE_ENTRY:
5606 fixP->fx_done = 0;
94f592af 5607 return;
47926f60
KH		 5608
5609 default:
5610 break;
5611 }
5612#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5613 *valP = value;
f86103b7 5614#endif /* !defined (TE_Mach) */
3e73aa7c 5615
3e73aa7c 5616 /* Are we finished with this relocation now? */
c6682705 5617 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5618 fixP->fx_done = 1;
5619 else if (use_rela_relocations)
5620 {
5621 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5622 /* Remember value for tc_gen_reloc. */
5623 fixP->fx_addnumber = value;
3e73aa7c
JH		 5624 value = 0;
5625 }
f86103b7 5626
94f592af 5627 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5628}
252b5132 5629\f
252b5132
RH		 5630#define MAX_LITTLENUMS 6
5631
47926f60
KH		 5632/* Turn the string pointed to by litP into a floating point constant
5633 of type TYPE, and emit the appropriate bytes. The number of
5634 LITTLENUMS emitted is stored in *SIZEP. An error message is
5635 returned, or NULL on OK. */
5636
252b5132
RH		 5637char *
5638md_atof (type, litP, sizeP)
2ab9b79e 5639 int type;
252b5132
RH		 5640 char *litP;
5641 int *sizeP;
5642{
5643 int prec;
5644 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5645 LITTLENUM_TYPE *wordP;
5646 char *t;
5647
5648 switch (type)
5649 {
5650 case 'f':
5651 case 'F':
5652 prec = 2;
5653 break;
5654
5655 case 'd':
5656 case 'D':
5657 prec = 4;
5658 break;
5659
5660 case 'x':
5661 case 'X':
5662 prec = 5;
5663 break;
5664
5665 default:
5666 *sizeP = 0;
5667 return _("Bad call to md_atof ()");
5668 }
5669 t = atof_ieee (input_line_pointer, type, words);
5670 if (t)
5671 input_line_pointer = t;
5672
5673 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5674 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5675 the bigendian 386. */
5676 for (wordP = words + prec - 1; prec--;)
5677 {
5678 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5679 litP += sizeof (LITTLENUM_TYPE);
5680 }
5681 return 0;
5682}
5683\f
2d545b82 5684static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5685
252b5132 5686static char *
e3bb37b5 5687output_invalid (int c)
252b5132 5688{
3882b010 5689 if (ISPRINT (c))
f9f21a03
L		 5690 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5691 "'%c'", c);
252b5132 5692 else
f9f21a03 5693 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5694 "(0x%x)", (unsigned char) c);
252b5132
RH		 5695 return output_invalid_buf;
5696}
5697
af6bdddf 5698/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5699
5700static const reg_entry *
4d1bb795 5701parse_real_register (char *reg_string, char **end_op)
252b5132 5702{
af6bdddf
AM		 5703 char *s = reg_string;
5704 char *p;
252b5132
RH		 5705 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5706 const reg_entry *r;
5707
5708 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5709 if (*s == REGISTER_PREFIX)
5710 ++s;
5711
5712 if (is_space_char (*s))
5713 ++s;
5714
5715 p = reg_name_given;
af6bdddf 5716 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5717 {
5718 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5719 return (const reg_entry *) NULL;
5720 s++;
252b5132
RH		 5721 }
5722
6588847e
DN		 5723 /* For naked regs, make sure that we are not dealing with an identifier.
5724 This prevents confusing an identifier like `eax_var' with register
5725 `eax'. */
5726 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5727 return (const reg_entry *) NULL;
5728
af6bdddf 5729 *end_op = s;
252b5132
RH		 5730
5731 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5732
5f47d35b 5733 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5734 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5735 {
5f47d35b
AM		 5736 if (is_space_char (*s))
5737 ++s;
5738 if (*s == '(')
5739 {
af6bdddf 5740 ++s;
5f47d35b
AM		 5741 if (is_space_char (*s))
5742 ++s;
5743 if (*s >= '0' && *s <= '7')
5744 {
5745 r = &i386_float_regtab[*s - '0'];
af6bdddf 5746 ++s;
5f47d35b
AM		 5747 if (is_space_char (*s))
5748 ++s;
5749 if (*s == ')')
5750 {
5751 *end_op = s + 1;
5752 return r;
5753 }
5f47d35b 5754 }
47926f60 5755 /* We have "%st(" then garbage. */
5f47d35b
AM		 5756 return (const reg_entry *) NULL;
5757 }
5758 }
5759
1ae00879 5760 if (r != NULL
20f0a1fc 5761 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5762 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5763 && flag_code != CODE_64BIT)
20f0a1fc 5764 return (const reg_entry *) NULL;
1ae00879 5765
252b5132
RH		 5766 return r;
5767}
4d1bb795
JB		 5768
5769/* REG_STRING starts *before* REGISTER_PREFIX. */
5770
5771static const reg_entry *
5772parse_register (char *reg_string, char **end_op)
5773{
5774 const reg_entry *r;
5775
5776 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5777 r = parse_real_register (reg_string, end_op);
5778 else
5779 r = NULL;
5780 if (!r)
5781 {
5782 char *save = input_line_pointer;
5783 char c;
5784 symbolS *symbolP;
5785
5786 input_line_pointer = reg_string;
5787 c = get_symbol_end ();
5788 symbolP = symbol_find (reg_string);
5789 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5790 {
5791 const expressionS *e = symbol_get_value_expression (symbolP);
5792
5793 know (e->X_op == O_register);
4eed87de 5794 know (e->X_add_number >= 0
c3fe08fa 5795 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 5796 r = i386_regtab + e->X_add_number;
5797 *end_op = input_line_pointer;
5798 }
5799 *input_line_pointer = c;
5800 input_line_pointer = save;
5801 }
5802 return r;
5803}
5804
5805int
5806i386_parse_name (char *name, expressionS *e, char *nextcharP)
5807{
5808 const reg_entry *r;
5809 char *end = input_line_pointer;
5810
5811 *end = *nextcharP;
5812 r = parse_register (name, &input_line_pointer);
5813 if (r && end <= input_line_pointer)
5814 {
5815 *nextcharP = *input_line_pointer;
5816 *input_line_pointer = 0;
5817 e->X_op = O_register;
5818 e->X_add_number = r - i386_regtab;
5819 return 1;
5820 }
5821 input_line_pointer = end;
5822 *end = 0;
5823 return 0;
5824}
5825
5826void
5827md_operand (expressionS *e)
5828{
5829 if (*input_line_pointer == REGISTER_PREFIX)
5830 {
5831 char *end;
5832 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5833
5834 if (r)
5835 {
5836 e->X_op = O_register;
5837 e->X_add_number = r - i386_regtab;
5838 input_line_pointer = end;
5839 }
5840 }
5841}
5842
252b5132 5843\f
4cc782b5 5844#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5845const char *md_shortopts = "kVQ:sqn";
252b5132 5846#else
12b55ccc 5847const char *md_shortopts = "qn";
252b5132 5848#endif
6e0b89ee 5849
3e73aa7c 5850#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5851#define OPTION_64 (OPTION_MD_BASE + 1)
5852#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5853#define OPTION_MARCH (OPTION_MD_BASE + 3)
5854#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5855
99ad8390
NC		 5856struct option md_longopts[] =
5857{
3e73aa7c 5858 {"32", no_argument, NULL, OPTION_32},
99ad8390 5859#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5860 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5861#endif
b3b91714 5862 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5863 {"march", required_argument, NULL, OPTION_MARCH},
5864 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5865 {NULL, no_argument, NULL, 0}
5866};
5867size_t md_longopts_size = sizeof (md_longopts);
5868
5869int
9103f4f4 5870md_parse_option (int c, char *arg)
252b5132 5871{
9103f4f4
L		 5872 unsigned int i;
5873
252b5132
RH		 5874 switch (c)
5875 {
12b55ccc
L		 5876 case 'n':
5877 optimize_align_code = 0;
5878 break;
5879
a38cf1db
AM		 5880 case 'q':
5881 quiet_warnings = 1;
252b5132
RH		 5882 break;
5883
5884#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5885 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5886 should be emitted or not. FIXME: Not implemented. */
5887 case 'Q':
252b5132
RH		 5888 break;
5889
5890 /* -V: SVR4 argument to print version ID. */
5891 case 'V':
5892 print_version_id ();
5893 break;
5894
a38cf1db
AM		 5895 /* -k: Ignore for FreeBSD compatibility. */
5896 case 'k':
252b5132 5897 break;
4cc782b5
ILT		 5898
5899 case 's':
5900 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5901 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5902 break;
99ad8390
NC		 5903#endif
5904#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5905 case OPTION_64:
5906 {
5907 const char **list, **l;
5908
3e73aa7c
JH		 5909 list = bfd_target_list ();
5910 for (l = list; *l != NULL; l++)
8620418b 5911 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 5912 || strcmp (*l, "coff-x86-64") == 0
5913 || strcmp (*l, "pe-x86-64") == 0
5914 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 5915 {
5916 default_arch = "x86_64";
5917 break;
5918 }
3e73aa7c 5919 if (*l == NULL)
6e0b89ee 5920 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5921 free (list);
5922 }
5923 break;
5924#endif
252b5132 5925
6e0b89ee
AM		 5926 case OPTION_32:
5927 default_arch = "i386";
5928 break;
5929
b3b91714
AM		 5930 case OPTION_DIVIDE:
5931#ifdef SVR4_COMMENT_CHARS
5932 {
5933 char *n, *t;
5934 const char *s;
5935
5936 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5937 t = n;
5938 for (s = i386_comment_chars; *s != '\0'; s++)
5939 if (*s != '/')
5940 *t++ = *s;
5941 *t = '\0';
5942 i386_comment_chars = n;
5943 }
5944#endif
5945 break;
5946
9103f4f4
L		 5947 case OPTION_MARCH:
5948 if (*arg == '.')
5949 as_fatal (_("Invalid -march= option: `%s'"), arg);
5950 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5951 {
5952 if (strcmp (arg, cpu_arch [i].name) == 0)
5953 {
ccc9c027 5954 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 5955 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 5956 if (!cpu_arch_tune_set)
5957 {
5958 cpu_arch_tune = cpu_arch_isa;
5959 cpu_arch_tune_flags = cpu_arch_isa_flags;
5960 }
9103f4f4
L		 5961 break;
5962 }
5963 }
5964 if (i >= ARRAY_SIZE (cpu_arch))
5965 as_fatal (_("Invalid -march= option: `%s'"), arg);
5966 break;
5967
5968 case OPTION_MTUNE:
5969 if (*arg == '.')
5970 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5971 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5972 {
5973 if (strcmp (arg, cpu_arch [i].name) == 0)
5974 {
ccc9c027 5975 cpu_arch_tune_set = 1;
9103f4f4
L		 5976 cpu_arch_tune = cpu_arch [i].type;
5977 cpu_arch_tune_flags = cpu_arch[i].flags;
5978 break;
5979 }
5980 }
5981 if (i >= ARRAY_SIZE (cpu_arch))
5982 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5983 break;
5984
252b5132
RH		 5985 default:
5986 return 0;
5987 }
5988 return 1;
5989}
5990
5991void
5992md_show_usage (stream)
5993 FILE *stream;
5994{
4cc782b5
ILT		 5995#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5996 fprintf (stream, _("\
a38cf1db
AM		 5997 -Q ignored\n\
5998 -V print assembler version number\n\
b3b91714
AM		 5999 -k ignored\n"));
6000#endif
6001 fprintf (stream, _("\
12b55ccc 6002 -n Do not optimize code alignment\n\
b3b91714
AM		 6003 -q quieten some warnings\n"));
6004#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6005 fprintf (stream, _("\
a38cf1db 6006 -s ignored\n"));
b3b91714 6007#endif
751d281c
L		 6008#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6009 fprintf (stream, _("\
6010 --32/--64 generate 32bit/64bit code\n"));
6011#endif
b3b91714
AM		 6012#ifdef SVR4_COMMENT_CHARS
6013 fprintf (stream, _("\
6014 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6015#else
6016 fprintf (stream, _("\
b3b91714 6017 --divide ignored\n"));
4cc782b5 6018#endif
9103f4f4
L		 6019 fprintf (stream, _("\
6020 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6021 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 6022 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6023
252b5132
RH		 6024}
6025
99ad8390
NC		 6026#if defined(TE_PEP)
6027const char *
6028x86_64_target_format (void)
6029{
6030 if (strcmp (default_arch, "x86_64") == 0)
6031 {
6032 set_code_flag (CODE_64BIT);
6033 return COFF_TARGET_FORMAT;
6034 }
6035 else if (strcmp (default_arch, "i386") == 0)
6036 {
6037 set_code_flag (CODE_32BIT);
6038 return "coff-i386";
6039 }
6040
6041 as_fatal (_("Unknown architecture"));
6042 return NULL;
6043}
6044#endif
6045
3e73aa7c
JH		 6046#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6047 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 6048
6049/* Pick the target format to use. */
6050
47926f60 6051const char *
e3bb37b5 6052i386_target_format (void)
252b5132 6053{
3e73aa7c 6054 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6055 {
6056 set_code_flag (CODE_64BIT);
6057 if (cpu_arch_isa_flags == 0)
d32cad65 6058 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6059 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6060 |CpuSSE|CpuSSE2;
ccc9c027 6061 if (cpu_arch_tune_flags == 0)
d32cad65 6062 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6063 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6064 |CpuSSE|CpuSSE2;
9103f4f4 6065 }
3e73aa7c 6066 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6067 {
6068 set_code_flag (CODE_32BIT);
6069 if (cpu_arch_isa_flags == 0)
d32cad65 6070 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6071 if (cpu_arch_tune_flags == 0)
d32cad65 6072 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6073 }
3e73aa7c
JH		 6074 else
6075 as_fatal (_("Unknown architecture"));
252b5132
RH		 6076 switch (OUTPUT_FLAVOR)
6077 {
4c63da97
AM		 6078#ifdef OBJ_MAYBE_AOUT
6079 case bfd_target_aout_flavour:
47926f60 6080 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6081#endif
6082#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6083 case bfd_target_coff_flavour:
6084 return "coff-i386";
4c63da97 6085#endif
3e73aa7c 6086#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6087 case bfd_target_elf_flavour:
3e73aa7c 6088 {
e5cb08ac 6089 if (flag_code == CODE_64BIT)
4fa24527
JB		 6090 {
6091 object_64bit = 1;
6092 use_rela_relocations = 1;
6093 }
9d7cbccd 6094 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6095 }
4c63da97 6096#endif
252b5132
RH		 6097 default:
6098 abort ();
6099 return NULL;
6100 }
6101}
6102
47926f60 6103#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6104
6105#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 6106void
6107i386_elf_emit_arch_note (void)
a847613f 6108{
718ddfc0 6109 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6110 {
6111 char *p;
6112 asection *seg = now_seg;
6113 subsegT subseg = now_subseg;
6114 Elf_Internal_Note i_note;
6115 Elf_External_Note e_note;
6116 asection *note_secp;
6117 int len;
6118
6119 /* Create the .note section. */
6120 note_secp = subseg_new (".note", 0);
6121 bfd_set_section_flags (stdoutput,
6122 note_secp,
6123 SEC_HAS_CONTENTS | SEC_READONLY);
6124
6125 /* Process the arch string. */
6126 len = strlen (cpu_arch_name);
6127
6128 i_note.namesz = len + 1;
6129 i_note.descsz = 0;
6130 i_note.type = NT_ARCH;
6131 p = frag_more (sizeof (e_note.namesz));
6132 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6133 p = frag_more (sizeof (e_note.descsz));
6134 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6135 p = frag_more (sizeof (e_note.type));
6136 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6137 p = frag_more (len + 1);
6138 strcpy (p, cpu_arch_name);
6139
6140 frag_align (2, 0, 0);
6141
6142 subseg_set (seg, subseg);
6143 }
6144}
6145#endif
252b5132 6146\f
252b5132
RH		 6147symbolS *
6148md_undefined_symbol (name)
6149 char *name;
6150{
18dc2407
ILT		 6151 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6152 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6153 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6154 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6155 {
6156 if (!GOT_symbol)
6157 {
6158 if (symbol_find (name))
6159 as_bad (_("GOT already in symbol table"));
6160 GOT_symbol = symbol_new (name, undefined_section,
6161 (valueT) 0, &zero_address_frag);
6162 };
6163 return GOT_symbol;
6164 }
252b5132
RH		 6165 return 0;
6166}
6167
6168/* Round up a section size to the appropriate boundary. */
47926f60 6169
252b5132
RH		 6170valueT
6171md_section_align (segment, size)
ab9da554 6172 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6173 valueT size;
6174{
4c63da97
AM		 6175#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6176 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6177 {
6178 /* For a.out, force the section size to be aligned. If we don't do
6179 this, BFD will align it for us, but it will not write out the
6180 final bytes of the section. This may be a bug in BFD, but it is
6181 easier to fix it here since that is how the other a.out targets
6182 work. */
6183 int align;
6184
6185 align = bfd_get_section_alignment (stdoutput, segment);
6186 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6187 }
252b5132
RH		 6188#endif
6189
6190 return size;
6191}
6192
6193/* On the i386, PC-relative offsets are relative to the start of the
6194 next instruction. That is, the address of the offset, plus its
6195 size, since the offset is always the last part of the insn. */
6196
6197long
e3bb37b5 6198md_pcrel_from (fixS *fixP)
252b5132
RH		 6199{
6200 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6201}
6202
6203#ifndef I386COFF
6204
6205static void
e3bb37b5 6206s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 6207{
29b0f896 6208 int temp;
252b5132 6209
8a75718c
JB		 6210#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6211 if (IS_ELF)
6212 obj_elf_section_change_hook ();
6213#endif
252b5132
RH		 6214 temp = get_absolute_expression ();
6215 subseg_set (bss_section, (subsegT) temp);
6216 demand_empty_rest_of_line ();
6217}
6218
6219#endif
6220
252b5132 6221void
e3bb37b5 6222i386_validate_fix (fixS *fixp)
252b5132
RH		 6223{
6224 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6225 {
23df1078
JH		 6226 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6227 {
4fa24527 6228 if (!object_64bit)
23df1078
JH		 6229 abort ();
6230 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6231 }
6232 else
6233 {
4fa24527 6234 if (!object_64bit)
d6ab8113
JB		 6235 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6236 else
6237 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6238 }
252b5132
RH		 6239 fixp->fx_subsy = 0;
6240 }
6241}
6242
252b5132
RH		 6243arelent *
6244tc_gen_reloc (section, fixp)
ab9da554 6245 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6246 fixS *fixp;
6247{
6248 arelent *rel;
6249 bfd_reloc_code_real_type code;
6250
6251 switch (fixp->fx_r_type)
6252 {
3e73aa7c
JH		 6253 case BFD_RELOC_X86_64_PLT32:
6254 case BFD_RELOC_X86_64_GOT32:
6255 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6256 case BFD_RELOC_386_PLT32:
6257 case BFD_RELOC_386_GOT32:
6258 case BFD_RELOC_386_GOTOFF:
6259 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6260 case BFD_RELOC_386_TLS_GD:
6261 case BFD_RELOC_386_TLS_LDM:
6262 case BFD_RELOC_386_TLS_LDO_32:
6263 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6264 case BFD_RELOC_386_TLS_IE:
6265 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6266 case BFD_RELOC_386_TLS_LE_32:
6267 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6268 case BFD_RELOC_386_TLS_GOTDESC:
6269 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6270 case BFD_RELOC_X86_64_TLSGD:
6271 case BFD_RELOC_X86_64_TLSLD:
6272 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6273 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6274 case BFD_RELOC_X86_64_GOTTPOFF:
6275 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6276 case BFD_RELOC_X86_64_TPOFF64:
6277 case BFD_RELOC_X86_64_GOTOFF64:
6278 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6279 case BFD_RELOC_X86_64_GOT64:
6280 case BFD_RELOC_X86_64_GOTPCREL64:
6281 case BFD_RELOC_X86_64_GOTPC64:
6282 case BFD_RELOC_X86_64_GOTPLT64:
6283 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6284 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6285 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6286 case BFD_RELOC_RVA:
6287 case BFD_RELOC_VTABLE_ENTRY:
6288 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6289#ifdef TE_PE
6290 case BFD_RELOC_32_SECREL:
6291#endif
252b5132
RH		 6292 code = fixp->fx_r_type;
6293 break;
dbbaec26
L		 6294 case BFD_RELOC_X86_64_32S:
6295 if (!fixp->fx_pcrel)
6296 {
6297 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6298 code = fixp->fx_r_type;
6299 break;
6300 }
252b5132 6301 default:
93382f6d 6302 if (fixp->fx_pcrel)
252b5132 6303 {
93382f6d
AM		 6304 switch (fixp->fx_size)
6305 {
6306 default:
b091f402
AM		 6307 as_bad_where (fixp->fx_file, fixp->fx_line,
6308 _("can not do %d byte pc-relative relocation"),
6309 fixp->fx_size);
93382f6d
AM		 6310 code = BFD_RELOC_32_PCREL;
6311 break;
6312 case 1: code = BFD_RELOC_8_PCREL; break;
6313 case 2: code = BFD_RELOC_16_PCREL; break;
6314 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6315#ifdef BFD64
6316 case 8: code = BFD_RELOC_64_PCREL; break;
6317#endif
93382f6d
AM		 6318 }
6319 }
6320 else
6321 {
6322 switch (fixp->fx_size)
6323 {
6324 default:
b091f402
AM		 6325 as_bad_where (fixp->fx_file, fixp->fx_line,
6326 _("can not do %d byte relocation"),
6327 fixp->fx_size);
93382f6d
AM		 6328 code = BFD_RELOC_32;
6329 break;
6330 case 1: code = BFD_RELOC_8; break;
6331 case 2: code = BFD_RELOC_16; break;
6332 case 4: code = BFD_RELOC_32; break;
937149dd 6333#ifdef BFD64
3e73aa7c 6334 case 8: code = BFD_RELOC_64; break;
937149dd 6335#endif
93382f6d 6336 }
252b5132
RH		 6337 }
6338 break;
6339 }
252b5132 6340
d182319b
JB		 6341 if ((code == BFD_RELOC_32
6342 || code == BFD_RELOC_32_PCREL
6343 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6344 && GOT_symbol
6345 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6346 {
4fa24527 6347 if (!object_64bit)
d6ab8113
JB		 6348 code = BFD_RELOC_386_GOTPC;
6349 else
6350 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6351 }
7b81dfbb
AJ		 6352 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6353 && GOT_symbol
6354 && fixp->fx_addsy == GOT_symbol)
6355 {
6356 code = BFD_RELOC_X86_64_GOTPC64;
6357 }
252b5132
RH		 6358
6359 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6360 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6361 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6362
6363 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6364
3e73aa7c
JH		 6365 if (!use_rela_relocations)
6366 {
6367 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6368 vtable entry to be used in the relocation's section offset. */
6369 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6370 rel->address = fixp->fx_offset;
252b5132 6371
c6682705 6372 rel->addend = 0;
3e73aa7c
JH		 6373 }
6374 /* Use the rela in 64bit mode. */
252b5132 6375 else
3e73aa7c 6376 {
062cd5e7
AS		 6377 if (!fixp->fx_pcrel)
6378 rel->addend = fixp->fx_offset;
6379 else
6380 switch (code)
6381 {
6382 case BFD_RELOC_X86_64_PLT32:
6383 case BFD_RELOC_X86_64_GOT32:
6384 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6385 case BFD_RELOC_X86_64_TLSGD:
6386 case BFD_RELOC_X86_64_TLSLD:
6387 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6388 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6389 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6390 rel->addend = fixp->fx_offset - fixp->fx_size;
6391 break;
6392 default:
6393 rel->addend = (section->vma
6394 - fixp->fx_size
6395 + fixp->fx_addnumber
6396 + md_pcrel_from (fixp));
6397 break;
6398 }
3e73aa7c
JH		 6399 }
6400
252b5132
RH		 6401 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6402 if (rel->howto == NULL)
6403 {
6404 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6405 _("cannot represent relocation type %s"),
252b5132
RH		 6406 bfd_get_reloc_code_name (code));
6407 /* Set howto to a garbage value so that we can keep going. */
6408 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6409 assert (rel->howto != NULL);
6410 }
6411
6412 return rel;
6413}
6414
64a0c779
DN		 6415\f
6416/* Parse operands using Intel syntax. This implements a recursive descent
6417 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6418 Programmer's Guide.
6419
6420 FIXME: We do not recognize the full operand grammar defined in the MASM
6421 documentation. In particular, all the structure/union and
6422 high-level macro operands are missing.
6423
6424 Uppercase words are terminals, lower case words are non-terminals.
6425 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6426 bars '|' denote choices. Most grammar productions are implemented in
6427 functions called 'intel_<production>'.
6428
6429 Initial production is 'expr'.
6430
9306ca4a 6431 addOp + | -
64a0c779
DN		 6432
6433 alpha [a-zA-Z]
6434
9306ca4a
JB		 6435 binOp & | AND | \| | OR | ^ | XOR
6436
64a0c779
DN		 6437 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6438
6439 constant digits [[ radixOverride ]]
6440
9306ca4a 6441 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6442
6443 digits decdigit
b77a7acd
AJ		 6444 | digits decdigit
6445 | digits hexdigit
64a0c779
DN		 6446
6447 decdigit [0-9]
6448
9306ca4a
JB		 6449 e04 e04 addOp e05
6450 | e05
6451
6452 e05 e05 binOp e06
b77a7acd 6453 | e06
64a0c779
DN		 6454
6455 e06 e06 mulOp e09
b77a7acd 6456 | e09
64a0c779
DN		 6457
6458 e09 OFFSET e10
a724f0f4
JB		 6459 | SHORT e10
6460 | + e10
6461 | - e10
9306ca4a
JB		 6462 | ~ e10
6463 | NOT e10
64a0c779
DN		 6464 | e09 PTR e10
6465 | e09 : e10
6466 | e10
6467
6468 e10 e10 [ expr ]
b77a7acd 6469 | e11
64a0c779
DN		 6470
6471 e11 ( expr )
b77a7acd 6472 | [ expr ]
64a0c779
DN		 6473 | constant
6474 | dataType
6475 | id
6476 | $
6477 | register
6478
a724f0f4 6479 => expr expr cmpOp e04
9306ca4a 6480 | e04
64a0c779
DN		 6481
6482 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6483 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6484
6485 hexdigit a | b | c | d | e | f
b77a7acd 6486 | A | B | C | D | E | F
64a0c779
DN		 6487
6488 id alpha
b77a7acd 6489 | id alpha
64a0c779
DN		 6490 | id decdigit
6491
9306ca4a 6492 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6493
6494 quote " | '
6495
6496 register specialRegister
b77a7acd 6497 | gpRegister
64a0c779
DN		 6498 | byteRegister
6499
6500 segmentRegister CS | DS | ES | FS | GS | SS
6501
9306ca4a 6502 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6503 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6504 | TR3 | TR4 | TR5 | TR6 | TR7
6505
64a0c779
DN		 6506 We simplify the grammar in obvious places (e.g., register parsing is
6507 done by calling parse_register) and eliminate immediate left recursion
6508 to implement a recursive-descent parser.
6509
a724f0f4
JB		 6510 expr e04 expr'
6511
6512 expr' cmpOp e04 expr'
6513 | Empty
9306ca4a
JB		 6514
6515 e04 e05 e04'
6516
6517 e04' addOp e05 e04'
6518 | Empty
64a0c779
DN		 6519
6520 e05 e06 e05'
6521
9306ca4a 6522 e05' binOp e06 e05'
b77a7acd 6523 | Empty
64a0c779
DN		 6524
6525 e06 e09 e06'
6526
6527 e06' mulOp e09 e06'
b77a7acd 6528 | Empty
64a0c779
DN		 6529
6530 e09 OFFSET e10 e09'
a724f0f4
JB		 6531 | SHORT e10'
6532 | + e10'
6533 | - e10'
6534 | ~ e10'
6535 | NOT e10'
b77a7acd 6536 | e10 e09'
64a0c779
DN		 6537
6538 e09' PTR e10 e09'
b77a7acd 6539 | : e10 e09'
64a0c779
DN		 6540 | Empty
6541
6542 e10 e11 e10'
6543
6544 e10' [ expr ] e10'
b77a7acd 6545 | Empty
64a0c779
DN		 6546
6547 e11 ( expr )
b77a7acd 6548 | [ expr ]
64a0c779
DN		 6549 | BYTE
6550 | WORD
6551 | DWORD
9306ca4a 6552 | FWORD
64a0c779 6553 | QWORD
9306ca4a
JB		 6554 | TBYTE
6555 | OWORD
6556 | XMMWORD
64a0c779
DN		 6557 | .
6558 | $
6559 | register
6560 | id
6561 | constant */
6562
6563/* Parsing structure for the intel syntax parser. Used to implement the
6564 semantic actions for the operand grammar. */
6565struct intel_parser_s
6566 {
6567 char *op_string; /* The string being parsed. */
6568 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6569 int op_modifier; /* Operand modifier. */
64a0c779 6570 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 6571 int in_offset; /* >=1 if parsing operand of offset. */
6572 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6573 const reg_entry *reg; /* Last register reference found. */
6574 char *disp; /* Displacement string being built. */
a724f0f4 6575 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6576 };
6577
6578static struct intel_parser_s intel_parser;
6579
6580/* Token structure for parsing intel syntax. */
6581struct intel_token
6582 {
6583 int code; /* Token code. */
6584 const reg_entry *reg; /* Register entry for register tokens. */
6585 char *str; /* String representation. */
6586 };
6587
6588static struct intel_token cur_token, prev_token;
6589
50705ef4
AM		 6590/* Token codes for the intel parser. Since T_SHORT is already used
6591 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6592#define T_NIL -1
6593#define T_CONST 1
6594#define T_REG 2
6595#define T_BYTE 3
6596#define T_WORD 4
9306ca4a
JB		 6597#define T_DWORD 5
6598#define T_FWORD 6
6599#define T_QWORD 7
6600#define T_TBYTE 8
6601#define T_XMMWORD 9
50705ef4 6602#undef T_SHORT
9306ca4a
JB		 6603#define T_SHORT 10
6604#define T_OFFSET 11
6605#define T_PTR 12
6606#define T_ID 13
6607#define T_SHL 14
6608#define T_SHR 15
64a0c779
DN		 6609
6610/* Prototypes for intel parser functions. */
e3bb37b5
L		 6611static int intel_match_token (int);
6612static void intel_putback_token (void);
6613static void intel_get_token (void);
6614static int intel_expr (void);
6615static int intel_e04 (void);
6616static int intel_e05 (void);
6617static int intel_e06 (void);
6618static int intel_e09 (void);
6619static int intel_e10 (void);
6620static int intel_e11 (void);
64a0c779 6621
64a0c779 6622static int
e3bb37b5 6623i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 6624{
6625 int ret;
6626 char *p;
6627
a724f0f4
JB		 6628 p = intel_parser.op_string = xstrdup (operand_string);
6629 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6630
6631 for (;;)
64a0c779 6632 {
a724f0f4
JB		 6633 /* Initialize token holders. */
6634 cur_token.code = prev_token.code = T_NIL;
6635 cur_token.reg = prev_token.reg = NULL;
6636 cur_token.str = prev_token.str = NULL;
6637
6638 /* Initialize parser structure. */
6639 intel_parser.got_a_float = got_a_float;
6640 intel_parser.op_modifier = 0;
6641 intel_parser.is_mem = 0;
6642 intel_parser.in_offset = 0;
6643 intel_parser.in_bracket = 0;
6644 intel_parser.reg = NULL;
6645 intel_parser.disp[0] = '\0';
6646 intel_parser.next_operand = NULL;
6647
6648 /* Read the first token and start the parser. */
6649 intel_get_token ();
6650 ret = intel_expr ();
6651
6652 if (!ret)
6653 break;
6654
9306ca4a
JB		 6655 if (cur_token.code != T_NIL)
6656 {
6657 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6658 current_templates->start->name, cur_token.str);
6659 ret = 0;
6660 }
64a0c779
DN		 6661 /* If we found a memory reference, hand it over to i386_displacement
6662 to fill in the rest of the operand fields. */
9306ca4a 6663 else if (intel_parser.is_mem)
64a0c779
DN		 6664 {
6665 if ((i.mem_operands == 1
6666 && (current_templates->start->opcode_modifier & IsString) == 0)
6667 || i.mem_operands == 2)
6668 {
6669 as_bad (_("too many memory references for '%s'"),
6670 current_templates->start->name);
6671 ret = 0;
6672 }
6673 else
6674 {
6675 char *s = intel_parser.disp;
6676 i.mem_operands++;
6677
a724f0f4
JB		 6678 if (!quiet_warnings && intel_parser.is_mem < 0)
6679 /* See the comments in intel_bracket_expr. */
6680 as_warn (_("Treating `%s' as memory reference"), operand_string);
6681
64a0c779
DN		 6682 /* Add the displacement expression. */
6683 if (*s != '\0')
a4622f40
AM		 6684 ret = i386_displacement (s, s + strlen (s));
6685 if (ret)
a724f0f4
JB		 6686 {
6687 /* Swap base and index in 16-bit memory operands like
6688 [si+bx]. Since i386_index_check is also used in AT&T
6689 mode we have to do that here. */
6690 if (i.base_reg
6691 && i.index_reg
6692 && (i.base_reg->reg_type & Reg16)
6693 && (i.index_reg->reg_type & Reg16)
6694 && i.base_reg->reg_num >= 6
6695 && i.index_reg->reg_num < 6)
6696 {
6697 const reg_entry *base = i.index_reg;
6698
6699 i.index_reg = i.base_reg;
6700 i.base_reg = base;
6701 }
6702 ret = i386_index_check (operand_string);
6703 }
64a0c779
DN		 6704 }
6705 }
6706
6707 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6708 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6709 || intel_parser.reg == NULL)
6710 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6711
6712 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 6713 ret = 0;
a724f0f4
JB		 6714 if (!ret || !intel_parser.next_operand)
6715 break;
6716 intel_parser.op_string = intel_parser.next_operand;
6717 this_operand = i.operands++;
64a0c779
DN		 6718 }
6719
6720 free (p);
6721 free (intel_parser.disp);
6722
6723 return ret;
6724}
6725
a724f0f4
JB		 6726#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6727
6728/* expr e04 expr'
6729
6730 expr' cmpOp e04 expr'
6731 | Empty */
64a0c779 6732static int
e3bb37b5 6733intel_expr (void)
64a0c779 6734{
a724f0f4
JB		 6735 /* XXX Implement the comparison operators. */
6736 return intel_e04 ();
9306ca4a
JB		 6737}
6738
a724f0f4 6739/* e04 e05 e04'
9306ca4a 6740
a724f0f4 6741 e04' addOp e05 e04'
9306ca4a
JB		 6742 | Empty */
6743static int
e3bb37b5 6744intel_e04 (void)
9306ca4a 6745{
a724f0f4 6746 int nregs = -1;
9306ca4a 6747
a724f0f4 6748 for (;;)
9306ca4a 6749 {
a724f0f4
JB		 6750 if (!intel_e05())
6751 return 0;
9306ca4a 6752
a724f0f4
JB		 6753 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6754 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6755
a724f0f4
JB		 6756 if (cur_token.code == '+')
6757 nregs = -1;
6758 else if (cur_token.code == '-')
6759 nregs = NUM_ADDRESS_REGS;
6760 else
6761 return 1;
64a0c779 6762
a724f0f4
JB		 6763 strcat (intel_parser.disp, cur_token.str);
6764 intel_match_token (cur_token.code);
6765 }
64a0c779
DN		 6766}
6767
64a0c779
DN		 6768/* e05 e06 e05'
6769
9306ca4a 6770 e05' binOp e06 e05'
64a0c779
DN		 6771 | Empty */
6772static int
e3bb37b5 6773intel_e05 (void)
64a0c779 6774{
a724f0f4 6775 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6776
a724f0f4 6777 for (;;)
64a0c779 6778 {
a724f0f4
JB		 6779 if (!intel_e06())
6780 return 0;
6781
4eed87de
AM		 6782 if (cur_token.code == '&'
6783 || cur_token.code == '|'
6784 || cur_token.code == '^')
a724f0f4
JB		 6785 {
6786 char str[2];
6787
6788 str[0] = cur_token.code;
6789 str[1] = 0;
6790 strcat (intel_parser.disp, str);
6791 }
6792 else
6793 break;
9306ca4a 6794
64a0c779
DN		 6795 intel_match_token (cur_token.code);
6796
a724f0f4
JB		 6797 if (nregs < 0)
6798 nregs = ~nregs;
64a0c779 6799 }
a724f0f4
JB		 6800 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6801 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6802 return 1;
4a1805b1 6803}
64a0c779
DN		 6804
6805/* e06 e09 e06'
6806
6807 e06' mulOp e09 e06'
b77a7acd 6808 | Empty */
64a0c779 6809static int
e3bb37b5 6810intel_e06 (void)
64a0c779 6811{
a724f0f4 6812 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6813
a724f0f4 6814 for (;;)
64a0c779 6815 {
a724f0f4
JB		 6816 if (!intel_e09())
6817 return 0;
9306ca4a 6818
4eed87de
AM		 6819 if (cur_token.code == '*'
6820 || cur_token.code == '/'
6821 || cur_token.code == '%')
a724f0f4
JB		 6822 {
6823 char str[2];
9306ca4a 6824
a724f0f4
JB		 6825 str[0] = cur_token.code;
6826 str[1] = 0;
6827 strcat (intel_parser.disp, str);
6828 }
6829 else if (cur_token.code == T_SHL)
6830 strcat (intel_parser.disp, "<<");
6831 else if (cur_token.code == T_SHR)
6832 strcat (intel_parser.disp, ">>");
6833 else
6834 break;
9306ca4a 6835
64e74474 6836 intel_match_token (cur_token.code);
64a0c779 6837
a724f0f4
JB		 6838 if (nregs < 0)
6839 nregs = ~nregs;
64a0c779 6840 }
a724f0f4
JB		 6841 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6842 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6843 return 1;
64a0c779
DN		 6844}
6845
a724f0f4
JB		 6846/* e09 OFFSET e09
6847 | SHORT e09
6848 | + e09
6849 | - e09
6850 | ~ e09
6851 | NOT e09
9306ca4a
JB		 6852 | e10 e09'
6853
64a0c779 6854 e09' PTR e10 e09'
b77a7acd 6855 | : e10 e09'
64a0c779
DN		 6856 | Empty */
6857static int
e3bb37b5 6858intel_e09 (void)
64a0c779 6859{
a724f0f4
JB		 6860 int nregs = ~NUM_ADDRESS_REGS;
6861 int in_offset = 0;
6862
6863 for (;;)
64a0c779 6864 {
a724f0f4
JB		 6865 /* Don't consume constants here. */
6866 if (cur_token.code == '+' || cur_token.code == '-')
6867 {
6868 /* Need to look one token ahead - if the next token
6869 is a constant, the current token is its sign. */
6870 int next_code;
6871
6872 intel_match_token (cur_token.code);
6873 next_code = cur_token.code;
6874 intel_putback_token ();
6875 if (next_code == T_CONST)
6876 break;
6877 }
6878
6879 /* e09 OFFSET e09 */
6880 if (cur_token.code == T_OFFSET)
6881 {
6882 if (!in_offset++)
6883 ++intel_parser.in_offset;
6884 }
6885
6886 /* e09 SHORT e09 */
6887 else if (cur_token.code == T_SHORT)
6888 intel_parser.op_modifier |= 1 << T_SHORT;
6889
6890 /* e09 + e09 */
6891 else if (cur_token.code == '+')
6892 strcat (intel_parser.disp, "+");
6893
6894 /* e09 - e09
6895 | ~ e09
6896 | NOT e09 */
6897 else if (cur_token.code == '-' || cur_token.code == '~')
6898 {
6899 char str[2];
64a0c779 6900
a724f0f4
JB		 6901 if (nregs < 0)
6902 nregs = ~nregs;
6903 str[0] = cur_token.code;
6904 str[1] = 0;
6905 strcat (intel_parser.disp, str);
6906 }
6907
6908 /* e09 e10 e09' */
6909 else
6910 break;
6911
6912 intel_match_token (cur_token.code);
64a0c779
DN		 6913 }
6914
a724f0f4 6915 for (;;)
9306ca4a 6916 {
a724f0f4
JB		 6917 if (!intel_e10 ())
6918 return 0;
9306ca4a 6919
a724f0f4
JB		 6920 /* e09' PTR e10 e09' */
6921 if (cur_token.code == T_PTR)
6922 {
6923 char suffix;
9306ca4a 6924
a724f0f4
JB		 6925 if (prev_token.code == T_BYTE)
6926 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6927
a724f0f4
JB		 6928 else if (prev_token.code == T_WORD)
6929 {
6930 if (current_templates->start->name[0] == 'l'
6931 && current_templates->start->name[2] == 's'
6932 && current_templates->start->name[3] == 0)
6933 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6934 else if (intel_parser.got_a_float == 2) /* "fi..." */
6935 suffix = SHORT_MNEM_SUFFIX;
6936 else
6937 suffix = WORD_MNEM_SUFFIX;
6938 }
64a0c779 6939
a724f0f4
JB		 6940 else if (prev_token.code == T_DWORD)
6941 {
6942 if (current_templates->start->name[0] == 'l'
6943 && current_templates->start->name[2] == 's'
6944 && current_templates->start->name[3] == 0)
6945 suffix = WORD_MNEM_SUFFIX;
6946 else if (flag_code == CODE_16BIT
6947 && (current_templates->start->opcode_modifier
435acd52 6948 & (Jump | JumpDword)))
a724f0f4
JB		 6949 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6950 else if (intel_parser.got_a_float == 1) /* "f..." */
6951 suffix = SHORT_MNEM_SUFFIX;
6952 else
6953 suffix = LONG_MNEM_SUFFIX;
6954 }
9306ca4a 6955
a724f0f4
JB		 6956 else if (prev_token.code == T_FWORD)
6957 {
6958 if (current_templates->start->name[0] == 'l'
6959 && current_templates->start->name[2] == 's'
6960 && current_templates->start->name[3] == 0)
6961 suffix = LONG_MNEM_SUFFIX;
6962 else if (!intel_parser.got_a_float)
6963 {
6964 if (flag_code == CODE_16BIT)
6965 add_prefix (DATA_PREFIX_OPCODE);
6966 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6967 }
6968 else
6969 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6970 }
64a0c779 6971
a724f0f4
JB		 6972 else if (prev_token.code == T_QWORD)
6973 {
6974 if (intel_parser.got_a_float == 1) /* "f..." */
6975 suffix = LONG_MNEM_SUFFIX;
6976 else
6977 suffix = QWORD_MNEM_SUFFIX;
6978 }
64a0c779 6979
a724f0f4
JB		 6980 else if (prev_token.code == T_TBYTE)
6981 {
6982 if (intel_parser.got_a_float == 1)
6983 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6984 else
6985 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6986 }
9306ca4a 6987
a724f0f4 6988 else if (prev_token.code == T_XMMWORD)
9306ca4a 6989 {
a724f0f4
JB		 6990 /* XXX ignored for now, but accepted since gcc uses it */
6991 suffix = 0;
9306ca4a 6992 }
64a0c779 6993
f16b83df 6994 else
a724f0f4
JB		 6995 {
6996 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6997 return 0;
6998 }
6999
435acd52
JB		 7000 /* Operands for jump/call using 'ptr' notation denote absolute
7001 addresses. */
7002 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7003 i.types[this_operand] |= JumpAbsolute;
7004
a724f0f4
JB		 7005 if (current_templates->start->base_opcode == 0x8d /* lea */)
7006 ;
7007 else if (!i.suffix)
7008 i.suffix = suffix;
7009 else if (i.suffix != suffix)
7010 {
7011 as_bad (_("Conflicting operand modifiers"));
7012 return 0;
7013 }
64a0c779 7014
9306ca4a
JB		 7015 }
7016
a724f0f4
JB		 7017 /* e09' : e10 e09' */
7018 else if (cur_token.code == ':')
9306ca4a 7019 {
a724f0f4
JB		 7020 if (prev_token.code != T_REG)
7021 {
7022 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7023 segment/group identifier (which we don't have), using comma
7024 as the operand separator there is even less consistent, since
7025 there all branches only have a single operand. */
7026 if (this_operand != 0
7027 || intel_parser.in_offset
7028 || intel_parser.in_bracket
7029 || (!(current_templates->start->opcode_modifier
7030 & (Jump|JumpDword|JumpInterSegment))
7031 && !(current_templates->start->operand_types[0]
7032 & JumpAbsolute)))
7033 return intel_match_token (T_NIL);
7034 /* Remember the start of the 2nd operand and terminate 1st
7035 operand here.
7036 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7037 another expression), but it gets at least the simplest case
7038 (a plain number or symbol on the left side) right. */
7039 intel_parser.next_operand = intel_parser.op_string;
7040 *--intel_parser.op_string = '\0';
7041 return intel_match_token (':');
7042 }
9306ca4a 7043 }
64a0c779 7044
a724f0f4 7045 /* e09' Empty */
64a0c779 7046 else
a724f0f4 7047 break;
64a0c779 7048
a724f0f4
JB		 7049 intel_match_token (cur_token.code);
7050
7051 }
7052
7053 if (in_offset)
7054 {
7055 --intel_parser.in_offset;
7056 if (nregs < 0)
7057 nregs = ~nregs;
7058 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7059 {
a724f0f4 7060 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7061 return 0;
7062 }
a724f0f4
JB		 7063 intel_parser.op_modifier |= 1 << T_OFFSET;
7064 }
9306ca4a 7065
a724f0f4
JB		 7066 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7067 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7068 return 1;
7069}
64a0c779 7070
a724f0f4 7071static int
e3bb37b5 7072intel_bracket_expr (void)
a724f0f4
JB		 7073{
7074 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7075 const char *start = intel_parser.op_string;
7076 int len;
7077
7078 if (i.op[this_operand].regs)
7079 return intel_match_token (T_NIL);
7080
7081 intel_match_token ('[');
7082
7083 /* Mark as a memory operand only if it's not already known to be an
7084 offset expression. If it's an offset expression, we need to keep
7085 the brace in. */
7086 if (!intel_parser.in_offset)
7087 {
7088 ++intel_parser.in_bracket;
435acd52
JB		 7089
7090 /* Operands for jump/call inside brackets denote absolute addresses. */
7091 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7092 i.types[this_operand] |= JumpAbsolute;
7093
a724f0f4
JB		 7094 /* Unfortunately gas always diverged from MASM in a respect that can't
7095 be easily fixed without risking to break code sequences likely to be
7096 encountered (the testsuite even check for this): MASM doesn't consider
7097 an expression inside brackets unconditionally as a memory reference.
7098 When that is e.g. a constant, an offset expression, or the sum of the
7099 two, this is still taken as a constant load. gas, however, always
7100 treated these as memory references. As a compromise, we'll try to make
7101 offset expressions inside brackets work the MASM way (since that's
7102 less likely to be found in real world code), but make constants alone
7103 continue to work the traditional gas way. In either case, issue a
7104 warning. */
7105 intel_parser.op_modifier &= ~was_offset;
64a0c779 7106 }
a724f0f4 7107 else
64e74474 7108 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7109
7110 /* Add a '+' to the displacement string if necessary. */
7111 if (*intel_parser.disp != '\0'
7112 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7113 strcat (intel_parser.disp, "+");
64a0c779 7114
a724f0f4
JB		 7115 if (intel_expr ()
7116 && (len = intel_parser.op_string - start - 1,
7117 intel_match_token (']')))
64a0c779 7118 {
a724f0f4
JB		 7119 /* Preserve brackets when the operand is an offset expression. */
7120 if (intel_parser.in_offset)
7121 strcat (intel_parser.disp, "]");
7122 else
7123 {
7124 --intel_parser.in_bracket;
7125 if (i.base_reg || i.index_reg)
7126 intel_parser.is_mem = 1;
7127 if (!intel_parser.is_mem)
7128 {
7129 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7130 /* Defer the warning until all of the operand was parsed. */
7131 intel_parser.is_mem = -1;
7132 else if (!quiet_warnings)
4eed87de
AM		 7133 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7134 len, start, len, start);
a724f0f4
JB		 7135 }
7136 }
7137 intel_parser.op_modifier |= was_offset;
64a0c779 7138
a724f0f4 7139 return 1;
64a0c779 7140 }
a724f0f4 7141 return 0;
64a0c779
DN		 7142}
7143
7144/* e10 e11 e10'
7145
7146 e10' [ expr ] e10'
b77a7acd 7147 | Empty */
64a0c779 7148static int
e3bb37b5 7149intel_e10 (void)
64a0c779 7150{
a724f0f4
JB		 7151 if (!intel_e11 ())
7152 return 0;
64a0c779 7153
a724f0f4 7154 while (cur_token.code == '[')
64a0c779 7155 {
a724f0f4 7156 if (!intel_bracket_expr ())
21d6c4af 7157 return 0;
64a0c779
DN		 7158 }
7159
a724f0f4 7160 return 1;
64a0c779
DN		 7161}
7162
64a0c779 7163/* e11 ( expr )
b77a7acd 7164 | [ expr ]
64a0c779
DN		 7165 | BYTE
7166 | WORD
7167 | DWORD
9306ca4a 7168 | FWORD
64a0c779 7169 | QWORD
9306ca4a
JB		 7170 | TBYTE
7171 | OWORD
7172 | XMMWORD
4a1805b1 7173 | $
64a0c779
DN		 7174 | .
7175 | register
7176 | id
7177 | constant */
7178static int
e3bb37b5 7179intel_e11 (void)
64a0c779 7180{
a724f0f4 7181 switch (cur_token.code)
64a0c779 7182 {
a724f0f4
JB		 7183 /* e11 ( expr ) */
7184 case '(':
64a0c779
DN		 7185 intel_match_token ('(');
7186 strcat (intel_parser.disp, "(");
7187
7188 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7189 {
7190 strcat (intel_parser.disp, ")");
7191 return 1;
7192 }
a724f0f4 7193 return 0;
4a1805b1 7194
a724f0f4
JB		 7195 /* e11 [ expr ] */
7196 case '[':
a724f0f4 7197 return intel_bracket_expr ();
64a0c779 7198
a724f0f4
JB		 7199 /* e11 $
7200 | . */
7201 case '.':
64a0c779
DN		 7202 strcat (intel_parser.disp, cur_token.str);
7203 intel_match_token (cur_token.code);
21d6c4af
DN		 7204
7205 /* Mark as a memory operand only if it's not already known to be an
7206 offset expression. */
a724f0f4 7207 if (!intel_parser.in_offset)
21d6c4af 7208 intel_parser.is_mem = 1;
64a0c779
DN		 7209
7210 return 1;
64a0c779 7211
a724f0f4
JB		 7212 /* e11 register */
7213 case T_REG:
7214 {
7215 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7216
a724f0f4 7217 intel_match_token (T_REG);
64a0c779 7218
a724f0f4
JB		 7219 /* Check for segment change. */
7220 if (cur_token.code == ':')
7221 {
7222 if (!(reg->reg_type & (SReg2 | SReg3)))
7223 {
4eed87de
AM		 7224 as_bad (_("`%s' is not a valid segment register"),
7225 reg->reg_name);
a724f0f4
JB		 7226 return 0;
7227 }
7228 else if (i.seg[i.mem_operands])
7229 as_warn (_("Extra segment override ignored"));
7230 else
7231 {
7232 if (!intel_parser.in_offset)
7233 intel_parser.is_mem = 1;
7234 switch (reg->reg_num)
7235 {
7236 case 0:
7237 i.seg[i.mem_operands] = &es;
7238 break;
7239 case 1:
7240 i.seg[i.mem_operands] = &cs;
7241 break;
7242 case 2:
7243 i.seg[i.mem_operands] = &ss;
7244 break;
7245 case 3:
7246 i.seg[i.mem_operands] = &ds;
7247 break;
7248 case 4:
7249 i.seg[i.mem_operands] = &fs;
7250 break;
7251 case 5:
7252 i.seg[i.mem_operands] = &gs;
7253 break;
7254 }
7255 }
7256 }
64a0c779 7257
a724f0f4
JB		 7258 /* Not a segment register. Check for register scaling. */
7259 else if (cur_token.code == '*')
7260 {
7261 if (!intel_parser.in_bracket)
7262 {
7263 as_bad (_("Register scaling only allowed in memory operands"));
7264 return 0;
7265 }
64a0c779 7266
a724f0f4
JB		 7267 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7268 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7269 else if (i.index_reg)
7270 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7271
a724f0f4
JB		 7272 /* What follows must be a valid scale. */
7273 intel_match_token ('*');
7274 i.index_reg = reg;
7275 i.types[this_operand] |= BaseIndex;
64a0c779 7276
a724f0f4
JB		 7277 /* Set the scale after setting the register (otherwise,
7278 i386_scale will complain) */
7279 if (cur_token.code == '+' || cur_token.code == '-')
7280 {
7281 char *str, sign = cur_token.code;
7282 intel_match_token (cur_token.code);
7283 if (cur_token.code != T_CONST)
7284 {
7285 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7286 cur_token.str);
7287 return 0;
7288 }
7289 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7290 strcpy (str + 1, cur_token.str);
7291 *str = sign;
7292 if (!i386_scale (str))
7293 return 0;
7294 free (str);
7295 }
7296 else if (!i386_scale (cur_token.str))
64a0c779 7297 return 0;
a724f0f4
JB		 7298 intel_match_token (cur_token.code);
7299 }
64a0c779 7300
a724f0f4
JB		 7301 /* No scaling. If this is a memory operand, the register is either a
7302 base register (first occurrence) or an index register (second
7303 occurrence). */
7b0441f6 7304 else if (intel_parser.in_bracket)
a724f0f4 7305 {
64a0c779 7306
a724f0f4
JB		 7307 if (!i.base_reg)
7308 i.base_reg = reg;
7309 else if (!i.index_reg)
7310 i.index_reg = reg;
7311 else
7312 {
7313 as_bad (_("Too many register references in memory operand"));
7314 return 0;
7315 }
64a0c779 7316
a724f0f4
JB		 7317 i.types[this_operand] |= BaseIndex;
7318 }
4a1805b1 7319
4d1bb795
JB		 7320 /* It's neither base nor index. */
7321 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7322 {
7323 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7324 i.op[this_operand].regs = reg;
7325 i.reg_operands++;
7326 }
7327 else
7328 {
7329 as_bad (_("Invalid use of register"));
7330 return 0;
7331 }
64a0c779 7332
a724f0f4
JB		 7333 /* Since registers are not part of the displacement string (except
7334 when we're parsing offset operands), we may need to remove any
7335 preceding '+' from the displacement string. */
7336 if (*intel_parser.disp != '\0'
7337 && !intel_parser.in_offset)
7338 {
7339 char *s = intel_parser.disp;
7340 s += strlen (s) - 1;
7341 if (*s == '+')
7342 *s = '\0';
7343 }
4a1805b1 7344
a724f0f4
JB		 7345 return 1;
7346 }
7347
7348 /* e11 BYTE
7349 | WORD
7350 | DWORD
7351 | FWORD
7352 | QWORD
7353 | TBYTE
7354 | OWORD
7355 | XMMWORD */
7356 case T_BYTE:
7357 case T_WORD:
7358 case T_DWORD:
7359 case T_FWORD:
7360 case T_QWORD:
7361 case T_TBYTE:
7362 case T_XMMWORD:
7363 intel_match_token (cur_token.code);
64a0c779 7364
a724f0f4
JB		 7365 if (cur_token.code == T_PTR)
7366 return 1;
7367
7368 /* It must have been an identifier. */
7369 intel_putback_token ();
7370 cur_token.code = T_ID;
7371 /* FALLTHRU */
7372
7373 /* e11 id
7374 | constant */
7375 case T_ID:
7376 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7377 {
7378 symbolS *symbolP;
7379
a724f0f4
JB		 7380 /* The identifier represents a memory reference only if it's not
7381 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7382 symbolP = symbol_find(cur_token.str);
7383 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7384 intel_parser.is_mem = 1;
7385 }
a724f0f4 7386 /* FALLTHRU */
64a0c779 7387
a724f0f4
JB		 7388 case T_CONST:
7389 case '-':
7390 case '+':
7391 {
7392 char *save_str, sign = 0;
64a0c779 7393
a724f0f4
JB		 7394 /* Allow constants that start with `+' or `-'. */
7395 if (cur_token.code == '-' || cur_token.code == '+')
7396 {
7397 sign = cur_token.code;
7398 intel_match_token (cur_token.code);
7399 if (cur_token.code != T_CONST)
7400 {
7401 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7402 cur_token.str);
7403 return 0;
7404 }
7405 }
64a0c779 7406
a724f0f4
JB		 7407 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7408 strcpy (save_str + !!sign, cur_token.str);
7409 if (sign)
7410 *save_str = sign;
64a0c779 7411
a724f0f4
JB		 7412 /* Get the next token to check for register scaling. */
7413 intel_match_token (cur_token.code);
64a0c779 7414
4eed87de
AM		 7415 /* Check if this constant is a scaling factor for an
7416 index register. */
a724f0f4
JB		 7417 if (cur_token.code == '*')
7418 {
7419 if (intel_match_token ('*') && cur_token.code == T_REG)
7420 {
7421 const reg_entry *reg = cur_token.reg;
7422
7423 if (!intel_parser.in_bracket)
7424 {
4eed87de
AM		 7425 as_bad (_("Register scaling only allowed "
7426 "in memory operands"));
a724f0f4
JB		 7427 return 0;
7428 }
7429
4eed87de
AM		 7430 /* Disallow things like [1*si].
7431 sp and esp are invalid as index. */
7432 if (reg->reg_type & Reg16)
7433 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 7434 else if (i.index_reg)
4eed87de 7435 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 7436
7437 /* The constant is followed by `* reg', so it must be
7438 a valid scale. */
7439 i.index_reg = reg;
7440 i.types[this_operand] |= BaseIndex;
7441
7442 /* Set the scale after setting the register (otherwise,
7443 i386_scale will complain) */
7444 if (!i386_scale (save_str))
64a0c779 7445 return 0;
a724f0f4
JB		 7446 intel_match_token (T_REG);
7447
7448 /* Since registers are not part of the displacement
7449 string, we may need to remove any preceding '+' from
7450 the displacement string. */
7451 if (*intel_parser.disp != '\0')
7452 {
7453 char *s = intel_parser.disp;
7454 s += strlen (s) - 1;
7455 if (*s == '+')
7456 *s = '\0';
7457 }
7458
7459 free (save_str);
7460
7461 return 1;
7462 }
64a0c779 7463
a724f0f4
JB		 7464 /* The constant was not used for register scaling. Since we have
7465 already consumed the token following `*' we now need to put it
7466 back in the stream. */
64a0c779 7467 intel_putback_token ();
a724f0f4 7468 }
64a0c779 7469
a724f0f4
JB		 7470 /* Add the constant to the displacement string. */
7471 strcat (intel_parser.disp, save_str);
7472 free (save_str);
64a0c779 7473
a724f0f4
JB		 7474 return 1;
7475 }
64a0c779
DN		 7476 }
7477
64a0c779
DN		 7478 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7479 return 0;
7480}
7481
64a0c779
DN		 7482/* Match the given token against cur_token. If they match, read the next
7483 token from the operand string. */
7484static int
e3bb37b5 7485intel_match_token (int code)
64a0c779
DN		 7486{
7487 if (cur_token.code == code)
7488 {
7489 intel_get_token ();
7490 return 1;
7491 }
7492 else
7493 {
0477af35 7494 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7495 return 0;
7496 }
7497}
7498
64a0c779
DN		 7499/* Read a new token from intel_parser.op_string and store it in cur_token. */
7500static void
e3bb37b5 7501intel_get_token (void)
64a0c779
DN		 7502{
7503 char *end_op;
7504 const reg_entry *reg;
7505 struct intel_token new_token;
7506
7507 new_token.code = T_NIL;
7508 new_token.reg = NULL;
7509 new_token.str = NULL;
7510
4a1805b1 7511 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7512 cur_token to prev_token. */
7513 if (prev_token.str)
7514 free (prev_token.str);
7515
7516 prev_token = cur_token;
7517
7518 /* Skip whitespace. */
7519 while (is_space_char (*intel_parser.op_string))
7520 intel_parser.op_string++;
7521
7522 /* Return an empty token if we find nothing else on the line. */
7523 if (*intel_parser.op_string == '\0')
7524 {
7525 cur_token = new_token;
7526 return;
7527 }
7528
7529 /* The new token cannot be larger than the remainder of the operand
7530 string. */
a724f0f4 7531 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7532 new_token.str[0] = '\0';
7533
7534 if (strchr ("0123456789", *intel_parser.op_string))
7535 {
7536 char *p = new_token.str;
7537 char *q = intel_parser.op_string;
7538 new_token.code = T_CONST;
7539
7540 /* Allow any kind of identifier char to encompass floating point and
7541 hexadecimal numbers. */
7542 while (is_identifier_char (*q))
7543 *p++ = *q++;
7544 *p = '\0';
7545
7546 /* Recognize special symbol names [0-9][bf]. */
7547 if (strlen (intel_parser.op_string) == 2
4a1805b1 7548 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7549 || intel_parser.op_string[1] == 'f'))
7550 new_token.code = T_ID;
7551 }
7552
4d1bb795 7553 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7554 {
4d1bb795
JB		 7555 size_t len = end_op - intel_parser.op_string;
7556
64a0c779
DN		 7557 new_token.code = T_REG;
7558 new_token.reg = reg;
7559
4d1bb795
JB		 7560 memcpy (new_token.str, intel_parser.op_string, len);
7561 new_token.str[len] = '\0';
64a0c779
DN		 7562 }
7563
7564 else if (is_identifier_char (*intel_parser.op_string))
7565 {
7566 char *p = new_token.str;
7567 char *q = intel_parser.op_string;
7568
7569 /* A '.' or '$' followed by an identifier char is an identifier.
7570 Otherwise, it's operator '.' followed by an expression. */
7571 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7572 {
9306ca4a
JB		 7573 new_token.code = '.';
7574 new_token.str[0] = '.';
64a0c779
DN		 7575 new_token.str[1] = '\0';
7576 }
7577 else
7578 {
7579 while (is_identifier_char (*q) || *q == '@')
7580 *p++ = *q++;
7581 *p = '\0';
7582
9306ca4a
JB		 7583 if (strcasecmp (new_token.str, "NOT") == 0)
7584 new_token.code = '~';
7585
7586 else if (strcasecmp (new_token.str, "MOD") == 0)
7587 new_token.code = '%';
7588
7589 else if (strcasecmp (new_token.str, "AND") == 0)
7590 new_token.code = '&';
7591
7592 else if (strcasecmp (new_token.str, "OR") == 0)
7593 new_token.code = '|';
7594
7595 else if (strcasecmp (new_token.str, "XOR") == 0)
7596 new_token.code = '^';
7597
7598 else if (strcasecmp (new_token.str, "SHL") == 0)
7599 new_token.code = T_SHL;
7600
7601 else if (strcasecmp (new_token.str, "SHR") == 0)
7602 new_token.code = T_SHR;
7603
7604 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7605 new_token.code = T_BYTE;
7606
7607 else if (strcasecmp (new_token.str, "WORD") == 0)
7608 new_token.code = T_WORD;
7609
7610 else if (strcasecmp (new_token.str, "DWORD") == 0)
7611 new_token.code = T_DWORD;
7612
9306ca4a
JB		 7613 else if (strcasecmp (new_token.str, "FWORD") == 0)
7614 new_token.code = T_FWORD;
7615
64a0c779
DN		 7616 else if (strcasecmp (new_token.str, "QWORD") == 0)
7617 new_token.code = T_QWORD;
7618
9306ca4a
JB		 7619 else if (strcasecmp (new_token.str, "TBYTE") == 0
7620 /* XXX remove (gcc still uses it) */
7621 || strcasecmp (new_token.str, "XWORD") == 0)
7622 new_token.code = T_TBYTE;
7623
7624 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7625 || strcasecmp (new_token.str, "OWORD") == 0)
7626 new_token.code = T_XMMWORD;
64a0c779
DN		 7627
7628 else if (strcasecmp (new_token.str, "PTR") == 0)
7629 new_token.code = T_PTR;
7630
7631 else if (strcasecmp (new_token.str, "SHORT") == 0)
7632 new_token.code = T_SHORT;
7633
7634 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7635 {
7636 new_token.code = T_OFFSET;
7637
7638 /* ??? This is not mentioned in the MASM grammar but gcc
7639 makes use of it with -mintel-syntax. OFFSET may be
7640 followed by FLAT: */
7641 if (strncasecmp (q, " FLAT:", 6) == 0)
7642 strcat (new_token.str, " FLAT:");
7643 }
7644
7645 /* ??? This is not mentioned in the MASM grammar. */
7646 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7647 {
7648 new_token.code = T_OFFSET;
7649 if (*q == ':')
7650 strcat (new_token.str, ":");
7651 else
7652 as_bad (_("`:' expected"));
7653 }
64a0c779
DN		 7654
7655 else
7656 new_token.code = T_ID;
7657 }
7658 }
7659
9306ca4a
JB		 7660 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7661 {
7662 new_token.code = *intel_parser.op_string;
7663 new_token.str[0] = *intel_parser.op_string;
7664 new_token.str[1] = '\0';
7665 }
7666
7667 else if (strchr ("<>", *intel_parser.op_string)
7668 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7669 {
7670 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7671 new_token.str[0] = *intel_parser.op_string;
7672 new_token.str[1] = *intel_parser.op_string;
7673 new_token.str[2] = '\0';
7674 }
7675
64a0c779 7676 else
0477af35 7677 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7678
7679 intel_parser.op_string += strlen (new_token.str);
7680 cur_token = new_token;
7681}
7682
64a0c779
DN		 7683/* Put cur_token back into the token stream and make cur_token point to
7684 prev_token. */
7685static void
e3bb37b5 7686intel_putback_token (void)
64a0c779 7687{
a724f0f4
JB		 7688 if (cur_token.code != T_NIL)
7689 {
7690 intel_parser.op_string -= strlen (cur_token.str);
7691 free (cur_token.str);
7692 }
64a0c779 7693 cur_token = prev_token;
4a1805b1 7694
64a0c779
DN		 7695 /* Forget prev_token. */
7696 prev_token.code = T_NIL;
7697 prev_token.reg = NULL;
7698 prev_token.str = NULL;
7699}
54cfded0 7700
a4447b93 7701int
1df69f4f 7702tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7703{
7704 unsigned int regnum;
7705 unsigned int regnames_count;
089dfecd 7706 static const char *const regnames_32[] =
54cfded0 7707 {
a4447b93
RH		 7708 "eax", "ecx", "edx", "ebx",
7709 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7710 "eip", "eflags", NULL,
7711 "st0", "st1", "st2", "st3",
7712 "st4", "st5", "st6", "st7",
7713 NULL, NULL,
7714 "xmm0", "xmm1", "xmm2", "xmm3",
7715 "xmm4", "xmm5", "xmm6", "xmm7",
7716 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7717 "mm4", "mm5", "mm6", "mm7",
7718 "fcw", "fsw", "mxcsr",
7719 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7720 "tr", "ldtr"
54cfded0 7721 };
089dfecd 7722 static const char *const regnames_64[] =
54cfded0 7723 {
089dfecd
JB		 7724 "rax", "rdx", "rcx", "rbx",
7725 "rsi", "rdi", "rbp", "rsp",
7726 "r8", "r9", "r10", "r11",
54cfded0 7727 "r12", "r13", "r14", "r15",
089dfecd
JB		 7728 "rip",
7729 "xmm0", "xmm1", "xmm2", "xmm3",
7730 "xmm4", "xmm5", "xmm6", "xmm7",
7731 "xmm8", "xmm9", "xmm10", "xmm11",
7732 "xmm12", "xmm13", "xmm14", "xmm15",
7733 "st0", "st1", "st2", "st3",
7734 "st4", "st5", "st6", "st7",
7735 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7736 "mm4", "mm5", "mm6", "mm7",
7737 "rflags",
7738 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7739 "fs.base", "gs.base", NULL, NULL,
7740 "tr", "ldtr",
7741 "mxcsr", "fcw", "fsw"
54cfded0 7742 };
089dfecd 7743 const char *const *regnames;
54cfded0
AM		 7744
7745 if (flag_code == CODE_64BIT)
7746 {
7747 regnames = regnames_64;
0cea6190 7748 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7749 }
7750 else
7751 {
7752 regnames = regnames_32;
0cea6190 7753 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7754 }
7755
7756 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7757 if (regnames[regnum] != NULL
7758 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7759 return regnum;
7760
54cfded0
AM		 7761 return -1;
7762}
7763
7764void
7765tc_x86_frame_initial_instructions (void)
7766{
a4447b93
RH		 7767 static unsigned int sp_regno;
7768
7769 if (!sp_regno)
7770 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7771 ? "rsp" : "esp");
7772
7773 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7774 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7775}
d2b2c203
DJ		 7776
7777int
7778i386_elf_section_type (const char *str, size_t len)
7779{
7780 if (flag_code == CODE_64BIT
7781 && len == sizeof ("unwind") - 1
7782 && strncmp (str, "unwind", 6) == 0)
7783 return SHT_X86_64_UNWIND;
7784
7785 return -1;
7786}
bb41ade5
AM		 7787
7788#ifdef TE_PE
7789void
7790tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7791{
7792 expressionS expr;
7793
7794 expr.X_op = O_secrel;
7795 expr.X_add_symbol = symbol;
7796 expr.X_add_number = 0;
7797 emit_expr (&expr, size);
7798}
7799#endif
3b22753a
L		 7800
7801#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7802/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7803
7804int
7805x86_64_section_letter (int letter, char **ptr_msg)
7806{
7807 if (flag_code == CODE_64BIT)
7808 {
7809 if (letter == 'l')
7810 return SHF_X86_64_LARGE;
7811
7812 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7813 }
3b22753a 7814 else
64e74474 7815 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7816 return -1;
7817}
7818
7819int
7820x86_64_section_word (char *str, size_t len)
7821{
8620418b 7822 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7823 return SHF_X86_64_LARGE;
7824
7825 return -1;
7826}
7827
7828static void
7829handle_large_common (int small ATTRIBUTE_UNUSED)
7830{
7831 if (flag_code != CODE_64BIT)
7832 {
7833 s_comm_internal (0, elf_common_parse);
7834 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7835 }
7836 else
7837 {
7838 static segT lbss_section;
7839 asection *saved_com_section_ptr = elf_com_section_ptr;
7840 asection *saved_bss_section = bss_section;
7841
7842 if (lbss_section == NULL)
7843 {
7844 flagword applicable;
7845 segT seg = now_seg;
7846 subsegT subseg = now_subseg;
7847
7848 /* The .lbss section is for local .largecomm symbols. */
7849 lbss_section = subseg_new (".lbss", 0);
7850 applicable = bfd_applicable_section_flags (stdoutput);
7851 bfd_set_section_flags (stdoutput, lbss_section,
7852 applicable & SEC_ALLOC);
7853 seg_info (lbss_section)->bss = 1;
7854
7855 subseg_set (seg, subseg);
7856 }
7857
7858 elf_com_section_ptr = &_bfd_elf_large_com_section;
7859 bss_section = lbss_section;
7860
7861 s_comm_internal (0, elf_common_parse);
7862
7863 elf_com_section_ptr = saved_com_section_ptr;
7864 bss_section = saved_bss_section;
7865 }
7866}
7867#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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