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* gdb.mi/var-cmd.c: Give long_array in _struct_decl 12 elements.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
aef6203b 3 2000, 2001, 2002, 2003, 2004, 2005
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 107static void output_imm PARAMS ((fragS *insn_start_frag,
108 offsetT insn_start_off));
109static void output_disp PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
29b0f896
AM		 111#ifndef I386COFF
112static void s_bss PARAMS ((int));
252b5132
RH		 113#endif
114
a847613f 115static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 116
252b5132 117/* 'md_assemble ()' gathers together information and puts it into a
47926f60 118 i386_insn. */
252b5132 119
520dc8e8
AM		 120union i386_op
121 {
122 expressionS *disps;
123 expressionS *imms;
124 const reg_entry *regs;
125 };
126
252b5132
RH		 127struct _i386_insn
128 {
47926f60 129 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 130 template tm;
131
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
134 char suffix;
135
47926f60 136 /* OPERANDS gives the number of given operands. */
252b5132
RH		 137 unsigned int operands;
138
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
47926f60 141 operands. */
252b5132
RH		 142 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
143
144 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 145 use OP[i] for the corresponding operand. */
252b5132
RH		 146 unsigned int types[MAX_OPERANDS];
147
520dc8e8
AM		 148 /* Displacement expression, immediate expression, or register for each
149 operand. */
150 union i386_op op[MAX_OPERANDS];
252b5132 151
3e73aa7c
JH		 152 /* Flags for operands. */
153 unsigned int flags[MAX_OPERANDS];
154#define Operand_PCrel 1
155
252b5132 156 /* Relocation type for operand */
f86103b7 157 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 158
252b5132
RH		 159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry *base_reg;
162 const reg_entry *index_reg;
163 unsigned int log2_scale_factor;
164
165 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 166 explicit segment overrides are given. */
ce8a8b2f 167 const seg_entry *seg[2];
252b5132
RH		 168
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes;
172 unsigned char prefix[MAX_PREFIXES];
173
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
176
177 modrm_byte rm;
3e73aa7c 178 rex_byte rex;
252b5132
RH		 179 sib_byte sib;
180 };
181
182typedef struct _i386_insn i386_insn;
183
184/* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
32137342 186const char extra_symbol_chars[] = "*%-(["
252b5132 187#ifdef LEX_AT
32137342
NC		 188 "@"
189#endif
190#ifdef LEX_QM
191 "?"
252b5132 192#endif
32137342 193 ;
252b5132 194
29b0f896
AM		 195#if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
32137342 198 && !defined (TE_NETWARE) \
29b0f896
AM		 199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
252b5132 201/* This array holds the chars that always start a comment. If the
ce8a8b2f 202 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 203const char comment_chars[] = "#/";
204#define PREFIX_SEPARATOR '\\'
252b5132
RH		 205
206/* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 210 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
252b5132 213 '/' isn't otherwise defined. */
0d9f6d04 214const char line_comment_chars[] = "#";
29b0f896 215
252b5132 216#else
29b0f896
AM		 217/* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219const char comment_chars[] = "#";
220#define PREFIX_SEPARATOR '/'
221
0d9f6d04 222const char line_comment_chars[] = "/#";
252b5132
RH		 223#endif
224
63a0b638 225const char line_separator_chars[] = ";";
252b5132 226
ce8a8b2f
AM		 227/* Chars that can be used to separate mant from exp in floating point
228 nums. */
252b5132
RH		 229const char EXP_CHARS[] = "eE";
230
ce8a8b2f
AM		 231/* Chars that mean this number is a floating point constant
232 As in 0f12.456
233 or 0d1.2345e12. */
252b5132
RH		 234const char FLT_CHARS[] = "fFdDxX";
235
ce8a8b2f 236/* Tables for lexical analysis. */
252b5132
RH		 237static char mnemonic_chars[256];
238static char register_chars[256];
239static char operand_chars[256];
240static char identifier_chars[256];
241static char digit_chars[256];
242
ce8a8b2f 243/* Lexical macros. */
252b5132
RH		 244#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245#define is_operand_char(x) (operand_chars[(unsigned char) x])
246#define is_register_char(x) (register_chars[(unsigned char) x])
247#define is_space_char(x) ((x) == ' ')
248#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249#define is_digit_char(x) (digit_chars[(unsigned char) x])
250
0234cb7c 251/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 252static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
253
254/* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
47926f60 257 assembler instruction). */
252b5132 258static char save_stack[32];
ce8a8b2f 259static char *save_stack_p;
252b5132
RH		 260#define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262#define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
264
47926f60 265/* The instruction we're assembling. */
252b5132
RH		 266static i386_insn i;
267
268/* Possible templates for current insn. */
269static const templates *current_templates;
270
47926f60 271/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 272static expressionS disp_expressions[2], im_expressions[2];
273
47926f60
KH		 274/* Current operand we are working on. */
275static int this_operand;
252b5132 276
3e73aa7c
JH		 277/* We support four different modes. FLAG_CODE variable is used to distinguish
278 these. */
279
280enum flag_code {
281 CODE_32BIT,
282 CODE_16BIT,
283 CODE_64BIT };
f3c180ae 284#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 285
286static enum flag_code flag_code;
287static int use_rela_relocations = 0;
288
289/* The names used to print error messages. */
b77a7acd 290static const char *flag_code_names[] =
3e73aa7c
JH		 291 {
292 "32",
293 "16",
294 "64"
295 };
252b5132 296
47926f60
KH		 297/* 1 for intel syntax,
298 0 if att syntax. */
299static int intel_syntax = 0;
252b5132 300
47926f60
KH		 301/* 1 if register prefix % not required. */
302static int allow_naked_reg = 0;
252b5132 303
47926f60
KH		 304/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307static char stackop_size = '\0';
3b22753a 308static void handle_large_common (int small ATTRIBUTE_UNUSED);
eecb386c 309
12b55ccc
L		 310/* Non-zero to optimize code alignment. */
311int optimize_align_code = 1;
312
47926f60
KH		 313/* Non-zero to quieten some warnings. */
314static int quiet_warnings = 0;
a38cf1db 315
47926f60
KH		 316/* CPU name. */
317static const char *cpu_arch_name = NULL;
5c6af06e 318static const char *cpu_sub_arch_name = NULL;
a38cf1db 319
47926f60 320/* CPU feature flags. */
29b0f896 321static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 322
fddf5b5b
AM		 323/* If set, conditional jumps are not automatically promoted to handle
324 larger than a byte offset. */
325static unsigned int no_cond_jump_promotion = 0;
326
29b0f896 327/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 328static symbolS *GOT_symbol;
29b0f896 329
a4447b93
RH		 330/* The dwarf2 return column, adjusted for 32 or 64 bit. */
331unsigned int x86_dwarf2_return_column;
332
333/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
334int x86_cie_data_alignment;
335
252b5132 336/* Interface to relax_segment.
fddf5b5b
AM		 337 There are 3 major relax states for 386 jump insns because the
338 different types of jumps add different sizes to frags when we're
339 figuring out what sort of jump to choose to reach a given label. */
252b5132 340
47926f60 341/* Types. */
93c2a809
AM		 342#define UNCOND_JUMP 0
343#define COND_JUMP 1
344#define COND_JUMP86 2
fddf5b5b 345
47926f60 346/* Sizes. */
252b5132
RH		 347#define CODE16 1
348#define SMALL 0
29b0f896 349#define SMALL16 (SMALL | CODE16)
252b5132 350#define BIG 2
29b0f896 351#define BIG16 (BIG | CODE16)
252b5132
RH		 352
353#ifndef INLINE
354#ifdef __GNUC__
355#define INLINE __inline__
356#else
357#define INLINE
358#endif
359#endif
360
fddf5b5b
AM		 361#define ENCODE_RELAX_STATE(type, size) \
362 ((relax_substateT) (((type) << 2) | (size)))
363#define TYPE_FROM_RELAX_STATE(s) \
364 ((s) >> 2)
365#define DISP_SIZE_FROM_RELAX_STATE(s) \
366 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 367
368/* This table is used by relax_frag to promote short jumps to long
369 ones where necessary. SMALL (short) jumps may be promoted to BIG
370 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
371 don't allow a short jump in a 32 bit code segment to be promoted to
372 a 16 bit offset jump because it's slower (requires data size
373 prefix), and doesn't work, unless the destination is in the bottom
374 64k of the code segment (The top 16 bits of eip are zeroed). */
375
376const relax_typeS md_relax_table[] =
377{
24eab124
AM		 378 /* The fields are:
379 1) most positive reach of this state,
380 2) most negative reach of this state,
93c2a809 381 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 382 4) which index into the table to try if we can't fit into this one. */
252b5132 383
fddf5b5b 384 /* UNCOND_JUMP states. */
93c2a809
AM		 385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
386 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
387 /* dword jmp adds 4 bytes to frag:
388 0 extra opcode bytes, 4 displacement bytes. */
252b5132 389 {0, 0, 4, 0},
93c2a809
AM		 390 /* word jmp adds 2 byte2 to frag:
391 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 392 {0, 0, 2, 0},
393
93c2a809
AM		 394 /* COND_JUMP states. */
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
396 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
397 /* dword conditionals adds 5 bytes to frag:
398 1 extra opcode byte, 4 displacement bytes. */
399 {0, 0, 5, 0},
fddf5b5b 400 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 401 1 extra opcode byte, 2 displacement bytes. */
402 {0, 0, 3, 0},
403
404 /* COND_JUMP86 states. */
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
406 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
407 /* dword conditionals adds 5 bytes to frag:
408 1 extra opcode byte, 4 displacement bytes. */
409 {0, 0, 5, 0},
410 /* word conditionals add 4 bytes to frag:
411 1 displacement byte and a 3 byte long branch insn. */
412 {0, 0, 4, 0}
252b5132
RH		 413};
414
e413e4e9
AM		 415static const arch_entry cpu_arch[] = {
416 {"i8086", Cpu086 },
417 {"i186", Cpu086|Cpu186 },
418 {"i286", Cpu086|Cpu186|Cpu286 },
419 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
420 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
5c6af06e
JB		 421 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
422 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
423 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
424 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
425 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
426 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
427 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
428 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
429 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
430 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
431 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
432 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
30123838 433 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
5c6af06e
JB		 434 {".mmx", CpuMMX },
435 {".sse", CpuMMX|CpuMMX2|CpuSSE },
436 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
bf50992e 437 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
5c6af06e
JB		 438 {".3dnow", CpuMMX|Cpu3dnow },
439 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
440 {".padlock", CpuPadLock },
30123838
JB		 441 {".pacifica", CpuSVME },
442 {".svme", CpuSVME },
e413e4e9
AM		 443 {NULL, 0 }
444};
445
29b0f896
AM		 446const pseudo_typeS md_pseudo_table[] =
447{
448#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
449 {"align", s_align_bytes, 0},
450#else
451 {"align", s_align_ptwo, 0},
452#endif
453 {"arch", set_cpu_arch, 0},
454#ifndef I386COFF
455 {"bss", s_bss, 0},
456#endif
457 {"ffloat", float_cons, 'f'},
458 {"dfloat", float_cons, 'd'},
459 {"tfloat", float_cons, 'x'},
460 {"value", cons, 2},
461 {"noopt", s_ignore, 0},
462 {"optim", s_ignore, 0},
463 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
464 {"code16", set_code_flag, CODE_16BIT},
465 {"code32", set_code_flag, CODE_32BIT},
466 {"code64", set_code_flag, CODE_64BIT},
467 {"intel_syntax", set_intel_syntax, 1},
468 {"att_syntax", set_intel_syntax, 0},
c6682705 469 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
29b0f896 470 {"loc", dwarf2_directive_loc, 0},
3b22753a
L		 471#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
472 {"largecomm", handle_large_common, 0},
473#endif
6482c264
NC		 474#ifdef TE_PE
475 {"secrel32", pe_directive_secrel, 0},
476#endif
29b0f896
AM		 477 {0, 0, 0}
478};
479
480/* For interface with expression (). */
481extern char *input_line_pointer;
482
483/* Hash table for instruction mnemonic lookup. */
484static struct hash_control *op_hash;
485
486/* Hash table for register lookup. */
487static struct hash_control *reg_hash;
488\f
252b5132
RH		 489void
490i386_align_code (fragP, count)
491 fragS *fragP;
492 int count;
493{
ce8a8b2f
AM		 494 /* Various efficient no-op patterns for aligning code labels.
495 Note: Don't try to assemble the instructions in the comments.
496 0L and 0w are not legal. */
252b5132
RH		 497 static const char f32_1[] =
498 {0x90}; /* nop */
499 static const char f32_2[] =
500 {0x89,0xf6}; /* movl %esi,%esi */
501 static const char f32_3[] =
502 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
503 static const char f32_4[] =
504 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
505 static const char f32_5[] =
506 {0x90, /* nop */
507 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
508 static const char f32_6[] =
509 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
510 static const char f32_7[] =
511 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
512 static const char f32_8[] =
513 {0x90, /* nop */
514 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
515 static const char f32_9[] =
516 {0x89,0xf6, /* movl %esi,%esi */
517 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
518 static const char f32_10[] =
519 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
520 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
521 static const char f32_11[] =
522 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
523 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
524 static const char f32_12[] =
525 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
526 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
527 static const char f32_13[] =
528 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
529 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
530 static const char f32_14[] =
531 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
532 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
533 static const char f32_15[] =
534 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
535 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 536 static const char f16_3[] =
537 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 538 static const char f16_4[] =
539 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
540 static const char f16_5[] =
541 {0x90, /* nop */
542 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
543 static const char f16_6[] =
544 {0x89,0xf6, /* mov %si,%si */
545 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
546 static const char f16_7[] =
547 {0x8d,0x74,0x00, /* lea 0(%si),%si */
548 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
549 static const char f16_8[] =
550 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
551 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
552 static const char *const f32_patt[] = {
553 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
554 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
555 };
556 static const char *const f16_patt[] = {
c3332e24 557 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 558 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
559 };
560
33fef721
JH		 561 if (count <= 0 || count > 15)
562 return;
3e73aa7c 563
33fef721
JH		 564 /* The recommended way to pad 64bit code is to use NOPs preceded by
565 maximally four 0x66 prefixes. Balance the size of nops. */
566 if (flag_code == CODE_64BIT)
252b5132 567 {
33fef721
JH		 568 int i;
569 int nnops = (count + 3) / 4;
570 int len = count / nnops;
571 int remains = count - nnops * len;
572 int pos = 0;
573
574 for (i = 0; i < remains; i++)
252b5132 575 {
33fef721
JH		 576 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
577 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
578 pos += len + 1;
579 }
580 for (; i < nnops; i++)
581 {
582 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
583 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
584 pos += len;
252b5132 585 }
252b5132 586 }
33fef721
JH		 587 else
588 if (flag_code == CODE_16BIT)
589 {
590 memcpy (fragP->fr_literal + fragP->fr_fix,
591 f16_patt[count - 1], count);
592 if (count > 8)
593 /* Adjust jump offset. */
594 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
595 }
596 else
597 memcpy (fragP->fr_literal + fragP->fr_fix,
598 f32_patt[count - 1], count);
599 fragP->fr_var = count;
252b5132
RH		 600}
601
252b5132
RH		 602static INLINE unsigned int
603mode_from_disp_size (t)
604 unsigned int t;
605{
3e73aa7c 606 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 607}
608
609static INLINE int
610fits_in_signed_byte (num)
847f7ad4 611 offsetT num;
252b5132
RH		 612{
613 return (num >= -128) && (num <= 127);
47926f60 614}
252b5132
RH		 615
616static INLINE int
617fits_in_unsigned_byte (num)
847f7ad4 618 offsetT num;
252b5132
RH		 619{
620 return (num & 0xff) == num;
47926f60 621}
252b5132
RH		 622
623static INLINE int
624fits_in_unsigned_word (num)
847f7ad4 625 offsetT num;
252b5132
RH		 626{
627 return (num & 0xffff) == num;
47926f60 628}
252b5132
RH		 629
630static INLINE int
631fits_in_signed_word (num)
847f7ad4 632 offsetT num;
252b5132
RH		 633{
634 return (-32768 <= num) && (num <= 32767);
47926f60 635}
3e73aa7c
JH		 636static INLINE int
637fits_in_signed_long (num)
638 offsetT num ATTRIBUTE_UNUSED;
639{
640#ifndef BFD64
641 return 1;
642#else
643 return (!(((offsetT) -1 << 31) & num)
644 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
645#endif
646} /* fits_in_signed_long() */
647static INLINE int
648fits_in_unsigned_long (num)
649 offsetT num ATTRIBUTE_UNUSED;
650{
651#ifndef BFD64
652 return 1;
653#else
654 return (num & (((offsetT) 2 << 31) - 1)) == num;
655#endif
656} /* fits_in_unsigned_long() */
252b5132
RH		 657
658static int
659smallest_imm_type (num)
847f7ad4 660 offsetT num;
252b5132 661{
a847613f 662 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 663 {
664 /* This code is disabled on the 486 because all the Imm1 forms
665 in the opcode table are slower on the i486. They're the
666 versions with the implicitly specified single-position
667 displacement, which has another syntax if you really want to
668 use that form. */
669 if (num == 1)
3e73aa7c 670 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 671 }
252b5132 672 return (fits_in_signed_byte (num)
3e73aa7c 673 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 674 : fits_in_unsigned_byte (num)
3e73aa7c 675 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 676 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 677 ? (Imm16 | Imm32 | Imm32S | Imm64)
678 : fits_in_signed_long (num)
679 ? (Imm32 | Imm32S | Imm64)
680 : fits_in_unsigned_long (num)
681 ? (Imm32 | Imm64)
682 : Imm64);
47926f60 683}
252b5132 684
847f7ad4
AM		 685static offsetT
686offset_in_range (val, size)
687 offsetT val;
688 int size;
689{
508866be 690 addressT mask;
ba2adb93 691
847f7ad4
AM		 692 switch (size)
693 {
508866be
L		 694 case 1: mask = ((addressT) 1 << 8) - 1; break;
695 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 696 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 697#ifdef BFD64
698 case 8: mask = ((addressT) 2 << 63) - 1; break;
699#endif
47926f60 700 default: abort ();
847f7ad4
AM		 701 }
702
ba2adb93 703 /* If BFD64, sign extend val. */
3e73aa7c
JH		 704 if (!use_rela_relocations)
705 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
706 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 707
47926f60 708 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 709 {
710 char buf1[40], buf2[40];
711
712 sprint_value (buf1, val);
713 sprint_value (buf2, val & mask);
714 as_warn (_("%s shortened to %s"), buf1, buf2);
715 }
716 return val & mask;
717}
718
252b5132
RH		 719/* Returns 0 if attempting to add a prefix where one from the same
720 class already exists, 1 if non rep/repne added, 2 if rep/repne
721 added. */
722static int
723add_prefix (prefix)
724 unsigned int prefix;
725{
726 int ret = 1;
727 int q;
728
29b0f896
AM		 729 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
730 && flag_code == CODE_64BIT)
3e73aa7c
JH		 731 q = REX_PREFIX;
732 else
733 switch (prefix)
734 {
735 default:
736 abort ();
737
738 case CS_PREFIX_OPCODE:
739 case DS_PREFIX_OPCODE:
740 case ES_PREFIX_OPCODE:
741 case FS_PREFIX_OPCODE:
742 case GS_PREFIX_OPCODE:
743 case SS_PREFIX_OPCODE:
744 q = SEG_PREFIX;
745 break;
252b5132 746
3e73aa7c
JH		 747 case REPNE_PREFIX_OPCODE:
748 case REPE_PREFIX_OPCODE:
749 ret = 2;
750 /* fall thru */
751 case LOCK_PREFIX_OPCODE:
752 q = LOCKREP_PREFIX;
753 break;
252b5132 754
3e73aa7c
JH		 755 case FWAIT_OPCODE:
756 q = WAIT_PREFIX;
757 break;
252b5132 758
3e73aa7c
JH		 759 case ADDR_PREFIX_OPCODE:
760 q = ADDR_PREFIX;
761 break;
252b5132 762
3e73aa7c
JH		 763 case DATA_PREFIX_OPCODE:
764 q = DATA_PREFIX;
765 break;
766 }
252b5132 767
29b0f896 768 if (i.prefix[q] != 0)
252b5132
RH		 769 {
770 as_bad (_("same type of prefix used twice"));
771 return 0;
772 }
773
774 i.prefixes += 1;
775 i.prefix[q] = prefix;
776 return ret;
777}
778
779static void
3e73aa7c 780set_code_flag (value)
e5cb08ac 781 int value;
eecb386c 782{
3e73aa7c
JH		 783 flag_code = value;
784 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
785 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
786 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
787 {
788 as_bad (_("64bit mode not supported on this CPU."));
789 }
790 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
791 {
792 as_bad (_("32bit mode not supported on this CPU."));
793 }
eecb386c
AM		 794 stackop_size = '\0';
795}
796
797static void
3e73aa7c
JH		 798set_16bit_gcc_code_flag (new_code_flag)
799 int new_code_flag;
252b5132 800{
3e73aa7c
JH		 801 flag_code = new_code_flag;
802 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
803 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 804 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 805}
806
807static void
808set_intel_syntax (syntax_flag)
eecb386c 809 int syntax_flag;
252b5132
RH		 810{
811 /* Find out if register prefixing is specified. */
812 int ask_naked_reg = 0;
813
814 SKIP_WHITESPACE ();
29b0f896 815 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 816 {
817 char *string = input_line_pointer;
818 int e = get_symbol_end ();
819
47926f60 820 if (strcmp (string, "prefix") == 0)
252b5132 821 ask_naked_reg = 1;
47926f60 822 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 823 ask_naked_reg = -1;
824 else
d0b47220 825 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 826 *input_line_pointer = e;
827 }
828 demand_empty_rest_of_line ();
c3332e24 829
252b5132
RH		 830 intel_syntax = syntax_flag;
831
832 if (ask_naked_reg == 0)
f86103b7
AM		 833 allow_naked_reg = (intel_syntax
834 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 835 else
836 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 837
838 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
839 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 840}
841
e413e4e9
AM		 842static void
843set_cpu_arch (dummy)
47926f60 844 int dummy ATTRIBUTE_UNUSED;
e413e4e9 845{
47926f60 846 SKIP_WHITESPACE ();
e413e4e9 847
29b0f896 848 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 849 {
850 char *string = input_line_pointer;
851 int e = get_symbol_end ();
852 int i;
853
854 for (i = 0; cpu_arch[i].name; i++)
855 {
856 if (strcmp (string, cpu_arch[i].name) == 0)
857 {
5c6af06e
JB		 858 if (*string != '.')
859 {
860 cpu_arch_name = cpu_arch[i].name;
861 cpu_sub_arch_name = NULL;
862 cpu_arch_flags = (cpu_arch[i].flags
863 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
864 break;
865 }
866 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
867 {
868 cpu_sub_arch_name = cpu_arch[i].name;
869 cpu_arch_flags |= cpu_arch[i].flags;
870 }
871 *input_line_pointer = e;
872 demand_empty_rest_of_line ();
873 return;
e413e4e9
AM		 874 }
875 }
876 if (!cpu_arch[i].name)
877 as_bad (_("no such architecture: `%s'"), string);
878
879 *input_line_pointer = e;
880 }
881 else
882 as_bad (_("missing cpu architecture"));
883
fddf5b5b
AM		 884 no_cond_jump_promotion = 0;
885 if (*input_line_pointer == ','
29b0f896 886 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 887 {
888 char *string = ++input_line_pointer;
889 int e = get_symbol_end ();
890
891 if (strcmp (string, "nojumps") == 0)
892 no_cond_jump_promotion = 1;
893 else if (strcmp (string, "jumps") == 0)
894 ;
895 else
896 as_bad (_("no such architecture modifier: `%s'"), string);
897
898 *input_line_pointer = e;
899 }
900
e413e4e9
AM		 901 demand_empty_rest_of_line ();
902}
903
b9d79e03
JH		 904unsigned long
905i386_mach ()
906{
907 if (!strcmp (default_arch, "x86_64"))
908 return bfd_mach_x86_64;
909 else if (!strcmp (default_arch, "i386"))
910 return bfd_mach_i386_i386;
911 else
912 as_fatal (_("Unknown architecture"));
913}
b9d79e03 914\f
252b5132
RH		 915void
916md_begin ()
917{
918 const char *hash_err;
919
47926f60 920 /* Initialize op_hash hash table. */
252b5132
RH		 921 op_hash = hash_new ();
922
923 {
29b0f896
AM		 924 const template *optab;
925 templates *core_optab;
252b5132 926
47926f60
KH		 927 /* Setup for loop. */
928 optab = i386_optab;
252b5132
RH		 929 core_optab = (templates *) xmalloc (sizeof (templates));
930 core_optab->start = optab;
931
932 while (1)
933 {
934 ++optab;
935 if (optab->name == NULL
936 || strcmp (optab->name, (optab - 1)->name) != 0)
937 {
938 /* different name --> ship out current template list;
47926f60 939 add to hash table; & begin anew. */
252b5132
RH		 940 core_optab->end = optab;
941 hash_err = hash_insert (op_hash,
942 (optab - 1)->name,
943 (PTR) core_optab);
944 if (hash_err)
945 {
252b5132
RH		 946 as_fatal (_("Internal Error: Can't hash %s: %s"),
947 (optab - 1)->name,
948 hash_err);
949 }
950 if (optab->name == NULL)
951 break;
952 core_optab = (templates *) xmalloc (sizeof (templates));
953 core_optab->start = optab;
954 }
955 }
956 }
957
47926f60 958 /* Initialize reg_hash hash table. */
252b5132
RH		 959 reg_hash = hash_new ();
960 {
29b0f896 961 const reg_entry *regtab;
252b5132
RH		 962
963 for (regtab = i386_regtab;
964 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
965 regtab++)
966 {
967 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
968 if (hash_err)
3e73aa7c
JH		 969 as_fatal (_("Internal Error: Can't hash %s: %s"),
970 regtab->reg_name,
971 hash_err);
252b5132
RH		 972 }
973 }
974
47926f60 975 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 976 {
29b0f896
AM		 977 int c;
978 char *p;
252b5132
RH		 979
980 for (c = 0; c < 256; c++)
981 {
3882b010 982 if (ISDIGIT (c))
252b5132
RH		 983 {
984 digit_chars[c] = c;
985 mnemonic_chars[c] = c;
986 register_chars[c] = c;
987 operand_chars[c] = c;
988 }
3882b010 989 else if (ISLOWER (c))
252b5132
RH		 990 {
991 mnemonic_chars[c] = c;
992 register_chars[c] = c;
993 operand_chars[c] = c;
994 }
3882b010 995 else if (ISUPPER (c))
252b5132 996 {
3882b010 997 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 998 register_chars[c] = mnemonic_chars[c];
999 operand_chars[c] = c;
1000 }
1001
3882b010 1002 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1003 identifier_chars[c] = c;
1004 else if (c >= 128)
1005 {
1006 identifier_chars[c] = c;
1007 operand_chars[c] = c;
1008 }
1009 }
1010
1011#ifdef LEX_AT
1012 identifier_chars['@'] = '@';
32137342
NC		 1013#endif
1014#ifdef LEX_QM
1015 identifier_chars['?'] = '?';
1016 operand_chars['?'] = '?';
252b5132 1017#endif
252b5132 1018 digit_chars['-'] = '-';
791fe849 1019 mnemonic_chars['-'] = '-';
252b5132
RH		 1020 identifier_chars['_'] = '_';
1021 identifier_chars['.'] = '.';
1022
1023 for (p = operand_special_chars; *p != '\0'; p++)
1024 operand_chars[(unsigned char) *p] = *p;
1025 }
1026
1027#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1028 if (IS_ELF)
252b5132
RH		 1029 {
1030 record_alignment (text_section, 2);
1031 record_alignment (data_section, 2);
1032 record_alignment (bss_section, 2);
1033 }
1034#endif
a4447b93
RH		 1035
1036 if (flag_code == CODE_64BIT)
1037 {
1038 x86_dwarf2_return_column = 16;
1039 x86_cie_data_alignment = -8;
1040 }
1041 else
1042 {
1043 x86_dwarf2_return_column = 8;
1044 x86_cie_data_alignment = -4;
1045 }
252b5132
RH		 1046}
1047
1048void
1049i386_print_statistics (file)
1050 FILE *file;
1051{
1052 hash_print_statistics (file, "i386 opcode", op_hash);
1053 hash_print_statistics (file, "i386 register", reg_hash);
1054}
1055\f
252b5132
RH		 1056#ifdef DEBUG386
1057
ce8a8b2f 1058/* Debugging routines for md_assemble. */
252b5132
RH		 1059static void pi PARAMS ((char *, i386_insn *));
1060static void pte PARAMS ((template *));
1061static void pt PARAMS ((unsigned int));
1062static void pe PARAMS ((expressionS *));
1063static void ps PARAMS ((symbolS *));
1064
1065static void
1066pi (line, x)
1067 char *line;
1068 i386_insn *x;
1069{
09f131f2 1070 unsigned int i;
252b5132
RH		 1071
1072 fprintf (stdout, "%s: template ", line);
1073 pte (&x->tm);
09f131f2
JH		 1074 fprintf (stdout, " address: base %s index %s scale %x\n",
1075 x->base_reg ? x->base_reg->reg_name : "none",
1076 x->index_reg ? x->index_reg->reg_name : "none",
1077 x->log2_scale_factor);
1078 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1079 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1080 fprintf (stdout, " sib: base %x index %x scale %x\n",
1081 x->sib.base, x->sib.index, x->sib.scale);
1082 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1083 (x->rex & REX_MODE64) != 0,
1084 (x->rex & REX_EXTX) != 0,
1085 (x->rex & REX_EXTY) != 0,
1086 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1087 for (i = 0; i < x->operands; i++)
1088 {
1089 fprintf (stdout, " #%d: ", i + 1);
1090 pt (x->types[i]);
1091 fprintf (stdout, "\n");
1092 if (x->types[i]
3f4438ab 1093 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1094 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1095 if (x->types[i] & Imm)
520dc8e8 1096 pe (x->op[i].imms);
252b5132 1097 if (x->types[i] & Disp)
520dc8e8 1098 pe (x->op[i].disps);
252b5132
RH		 1099 }
1100}
1101
1102static void
1103pte (t)
1104 template *t;
1105{
09f131f2 1106 unsigned int i;
252b5132 1107 fprintf (stdout, " %d operands ", t->operands);
47926f60 1108 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1109 if (t->extension_opcode != None)
1110 fprintf (stdout, "ext %x ", t->extension_opcode);
1111 if (t->opcode_modifier & D)
1112 fprintf (stdout, "D");
1113 if (t->opcode_modifier & W)
1114 fprintf (stdout, "W");
1115 fprintf (stdout, "\n");
1116 for (i = 0; i < t->operands; i++)
1117 {
1118 fprintf (stdout, " #%d type ", i + 1);
1119 pt (t->operand_types[i]);
1120 fprintf (stdout, "\n");
1121 }
1122}
1123
1124static void
1125pe (e)
1126 expressionS *e;
1127{
24eab124 1128 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1129 fprintf (stdout, " add_number %ld (%lx)\n",
1130 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1131 if (e->X_add_symbol)
1132 {
1133 fprintf (stdout, " add_symbol ");
1134 ps (e->X_add_symbol);
1135 fprintf (stdout, "\n");
1136 }
1137 if (e->X_op_symbol)
1138 {
1139 fprintf (stdout, " op_symbol ");
1140 ps (e->X_op_symbol);
1141 fprintf (stdout, "\n");
1142 }
1143}
1144
1145static void
1146ps (s)
1147 symbolS *s;
1148{
1149 fprintf (stdout, "%s type %s%s",
1150 S_GET_NAME (s),
1151 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1152 segment_name (S_GET_SEGMENT (s)));
1153}
1154
1155struct type_name
1156 {
1157 unsigned int mask;
1158 char *tname;
1159 }
1160
29b0f896 1161static const type_names[] =
252b5132
RH		 1162{
1163 { Reg8, "r8" },
1164 { Reg16, "r16" },
1165 { Reg32, "r32" },
09f131f2 1166 { Reg64, "r64" },
252b5132
RH		 1167 { Imm8, "i8" },
1168 { Imm8S, "i8s" },
1169 { Imm16, "i16" },
1170 { Imm32, "i32" },
09f131f2
JH		 1171 { Imm32S, "i32s" },
1172 { Imm64, "i64" },
252b5132
RH		 1173 { Imm1, "i1" },
1174 { BaseIndex, "BaseIndex" },
1175 { Disp8, "d8" },
1176 { Disp16, "d16" },
1177 { Disp32, "d32" },
09f131f2
JH		 1178 { Disp32S, "d32s" },
1179 { Disp64, "d64" },
252b5132
RH		 1180 { InOutPortReg, "InOutPortReg" },
1181 { ShiftCount, "ShiftCount" },
1182 { Control, "control reg" },
1183 { Test, "test reg" },
1184 { Debug, "debug reg" },
1185 { FloatReg, "FReg" },
1186 { FloatAcc, "FAcc" },
1187 { SReg2, "SReg2" },
1188 { SReg3, "SReg3" },
1189 { Acc, "Acc" },
1190 { JumpAbsolute, "Jump Absolute" },
1191 { RegMMX, "rMMX" },
3f4438ab 1192 { RegXMM, "rXMM" },
252b5132
RH		 1193 { EsSeg, "es" },
1194 { 0, "" }
1195};
1196
1197static void
1198pt (t)
1199 unsigned int t;
1200{
29b0f896 1201 const struct type_name *ty;
252b5132 1202
09f131f2
JH		 1203 for (ty = type_names; ty->mask; ty++)
1204 if (t & ty->mask)
1205 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1206 fflush (stdout);
1207}
1208
1209#endif /* DEBUG386 */
1210\f
252b5132 1211static bfd_reloc_code_real_type
3956db08
JB		 1212reloc (unsigned int size,
1213 int pcrel,
1214 int sign,
1215 bfd_reloc_code_real_type other)
252b5132 1216{
47926f60 1217 if (other != NO_RELOC)
3956db08
JB		 1218 {
1219 reloc_howto_type *reloc;
1220
1221 if (size == 8)
1222 switch (other)
1223 {
1224 case BFD_RELOC_X86_64_TPOFF32:
1225 other = BFD_RELOC_X86_64_TPOFF64;
1226 break;
1227 case BFD_RELOC_X86_64_DTPOFF32:
1228 other = BFD_RELOC_X86_64_DTPOFF64;
1229 break;
1230 default:
1231 break;
1232 }
1233 reloc = bfd_reloc_type_lookup (stdoutput, other);
1234 if (!reloc)
1235 as_bad (_("unknown relocation (%u)"), other);
1236 else if (size != bfd_get_reloc_size (reloc))
1237 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1238 bfd_get_reloc_size (reloc),
1239 size);
1240 else if (pcrel && !reloc->pc_relative)
1241 as_bad (_("non-pc-relative relocation for pc-relative field"));
1242 else if ((reloc->complain_on_overflow == complain_overflow_signed
1243 && !sign)
1244 || (reloc->complain_on_overflow == complain_overflow_unsigned
1245 && sign > 0))
1246 as_bad (_("relocated field and relocation type differ in signedness"));
1247 else
1248 return other;
1249 return NO_RELOC;
1250 }
252b5132
RH		 1251
1252 if (pcrel)
1253 {
3e73aa7c 1254 if (!sign)
3956db08 1255 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1256 switch (size)
1257 {
1258 case 1: return BFD_RELOC_8_PCREL;
1259 case 2: return BFD_RELOC_16_PCREL;
1260 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1261 case 8: return BFD_RELOC_64_PCREL;
252b5132 1262 }
3956db08 1263 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1264 }
1265 else
1266 {
3956db08 1267 if (sign > 0)
e5cb08ac 1268 switch (size)
3e73aa7c
JH		 1269 {
1270 case 4: return BFD_RELOC_X86_64_32S;
1271 }
1272 else
1273 switch (size)
1274 {
1275 case 1: return BFD_RELOC_8;
1276 case 2: return BFD_RELOC_16;
1277 case 4: return BFD_RELOC_32;
1278 case 8: return BFD_RELOC_64;
1279 }
3956db08
JB		 1280 as_bad (_("cannot do %s %u byte relocation"),
1281 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1282 }
1283
bfb32b52 1284 abort ();
252b5132
RH		 1285 return BFD_RELOC_NONE;
1286}
1287
47926f60
KH		 1288/* Here we decide which fixups can be adjusted to make them relative to
1289 the beginning of the section instead of the symbol. Basically we need
1290 to make sure that the dynamic relocations are done correctly, so in
1291 some cases we force the original symbol to be used. */
1292
252b5132 1293int
c0c949c7 1294tc_i386_fix_adjustable (fixP)
31312f95 1295 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1296{
6d249963 1297#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1298 if (!IS_ELF)
31312f95
AM		 1299 return 1;
1300
a161fe53
AM		 1301 /* Don't adjust pc-relative references to merge sections in 64-bit
1302 mode. */
1303 if (use_rela_relocations
1304 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1305 && fixP->fx_pcrel)
252b5132 1306 return 0;
31312f95 1307
8d01d9a9
AJ		 1308 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1309 and changed later by validate_fix. */
1310 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1311 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1312 return 0;
1313
ce8a8b2f 1314 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1315 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1316 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1317 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1318 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1319 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1320 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1321 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1322 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1323 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1324 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1325 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1326 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1327 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1328 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1329 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1330 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1331 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1332 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1333 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1334 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1335 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1336 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
252b5132
RH		 1337 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1338 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1339 return 0;
31312f95 1340#endif
252b5132
RH		 1341 return 1;
1342}
252b5132 1343
29b0f896 1344static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1345
1346static int
252b5132 1347intel_float_operand (mnemonic)
29b0f896 1348 const char *mnemonic;
252b5132 1349{
9306ca4a
JB		 1350 /* Note that the value returned is meaningful only for opcodes with (memory)
1351 operands, hence the code here is free to improperly handle opcodes that
1352 have no operands (for better performance and smaller code). */
1353
1354 if (mnemonic[0] != 'f')
1355 return 0; /* non-math */
1356
1357 switch (mnemonic[1])
1358 {
1359 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1360 the fs segment override prefix not currently handled because no
1361 call path can make opcodes without operands get here */
1362 case 'i':
1363 return 2 /* integer op */;
1364 case 'l':
1365 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1366 return 3; /* fldcw/fldenv */
1367 break;
1368 case 'n':
1369 if (mnemonic[2] != 'o' /* fnop */)
1370 return 3; /* non-waiting control op */
1371 break;
1372 case 'r':
1373 if (mnemonic[2] == 's')
1374 return 3; /* frstor/frstpm */
1375 break;
1376 case 's':
1377 if (mnemonic[2] == 'a')
1378 return 3; /* fsave */
1379 if (mnemonic[2] == 't')
1380 {
1381 switch (mnemonic[3])
1382 {
1383 case 'c': /* fstcw */
1384 case 'd': /* fstdw */
1385 case 'e': /* fstenv */
1386 case 's': /* fsts[gw] */
1387 return 3;
1388 }
1389 }
1390 break;
1391 case 'x':
1392 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1393 return 0; /* fxsave/fxrstor are not really math ops */
1394 break;
1395 }
252b5132 1396
9306ca4a 1397 return 1;
252b5132
RH		 1398}
1399
1400/* This is the guts of the machine-dependent assembler. LINE points to a
1401 machine dependent instruction. This function is supposed to emit
1402 the frags/bytes it assembles to. */
1403
1404void
1405md_assemble (line)
1406 char *line;
1407{
252b5132 1408 int j;
252b5132
RH		 1409 char mnemonic[MAX_MNEM_SIZE];
1410
47926f60 1411 /* Initialize globals. */
252b5132
RH		 1412 memset (&i, '\0', sizeof (i));
1413 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1414 i.reloc[j] = NO_RELOC;
252b5132
RH		 1415 memset (disp_expressions, '\0', sizeof (disp_expressions));
1416 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1417 save_stack_p = save_stack;
252b5132
RH		 1418
1419 /* First parse an instruction mnemonic & call i386_operand for the operands.
1420 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1421 start of a (possibly prefixed) mnemonic. */
252b5132 1422
29b0f896
AM		 1423 line = parse_insn (line, mnemonic);
1424 if (line == NULL)
1425 return;
252b5132 1426
29b0f896
AM		 1427 line = parse_operands (line, mnemonic);
1428 if (line == NULL)
1429 return;
252b5132 1430
29b0f896
AM		 1431 /* Now we've parsed the mnemonic into a set of templates, and have the
1432 operands at hand. */
1433
1434 /* All intel opcodes have reversed operands except for "bound" and
1435 "enter". We also don't reverse intersegment "jmp" and "call"
1436 instructions with 2 immediate operands so that the immediate segment
1437 precedes the offset, as it does when in AT&T mode. "enter" and the
1438 intersegment "jmp" and "call" instructions are the only ones that
1439 have two immediate operands. */
1440 if (intel_syntax && i.operands > 1
1441 && (strcmp (mnemonic, "bound") != 0)
30123838 1442 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1443 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1444 swap_operands ();
1445
1446 if (i.imm_operands)
1447 optimize_imm ();
1448
b300c311
L		 1449 /* Don't optimize displacement for movabs since it only takes 64bit
1450 displacement. */
1451 if (i.disp_operands
1452 && (flag_code != CODE_64BIT
1453 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1454 optimize_disp ();
1455
1456 /* Next, we find a template that matches the given insn,
1457 making sure the overlap of the given operands types is consistent
1458 with the template operand types. */
252b5132 1459
29b0f896
AM		 1460 if (!match_template ())
1461 return;
252b5132 1462
cd61ebfe
AM		 1463 if (intel_syntax)
1464 {
1465 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1466 if (SYSV386_COMPAT
1467 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1468 i.tm.base_opcode ^= FloatR;
1469
1470 /* Zap movzx and movsx suffix. The suffix may have been set from
1471 "word ptr" or "byte ptr" on the source operand, but we'll use
1472 the suffix later to choose the destination register. */
1473 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1474 {
1475 if (i.reg_operands < 2
1476 && !i.suffix
1477 && (~i.tm.opcode_modifier
1478 & (No_bSuf
1479 | No_wSuf
1480 | No_lSuf
1481 | No_sSuf
1482 | No_xSuf
1483 | No_qSuf)))
1484 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1485
1486 i.suffix = 0;
1487 }
cd61ebfe 1488 }
24eab124 1489
29b0f896
AM		 1490 if (i.tm.opcode_modifier & FWait)
1491 if (!add_prefix (FWAIT_OPCODE))
1492 return;
252b5132 1493
29b0f896
AM		 1494 /* Check string instruction segment overrides. */
1495 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1496 {
1497 if (!check_string ())
5dd0794d 1498 return;
29b0f896 1499 }
5dd0794d 1500
29b0f896
AM		 1501 if (!process_suffix ())
1502 return;
e413e4e9 1503
29b0f896
AM		 1504 /* Make still unresolved immediate matches conform to size of immediate
1505 given in i.suffix. */
1506 if (!finalize_imm ())
1507 return;
252b5132 1508
29b0f896
AM		 1509 if (i.types[0] & Imm1)
1510 i.imm_operands = 0; /* kludge for shift insns. */
1511 if (i.types[0] & ImplicitRegister)
1512 i.reg_operands--;
1513 if (i.types[1] & ImplicitRegister)
1514 i.reg_operands--;
1515 if (i.types[2] & ImplicitRegister)
1516 i.reg_operands--;
252b5132 1517
29b0f896
AM		 1518 if (i.tm.opcode_modifier & ImmExt)
1519 {
02fc3089
L		 1520 expressionS *exp;
1521
ca164297
L		 1522 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1523 {
67c1ffbe 1524 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1525 operands with an opcode suffix which is coded in the same
1526 place as an 8-bit immediate field would be. Here we check
1527 those operands and remove them afterwards. */
1528 unsigned int x;
1529
a4622f40 1530 for (x = 0; x < i.operands; x++)
ca164297
L		 1531 if (i.op[x].regs->reg_num != x)
1532 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1533 i.op[x].regs->reg_name, x + 1, i.tm.name);
1534 i.operands = 0;
1535 }
1536
29b0f896
AM		 1537 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1538 opcode suffix which is coded in the same place as an 8-bit
1539 immediate field would be. Here we fake an 8-bit immediate
1540 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1541
29b0f896 1542 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1543
29b0f896
AM		 1544 exp = &im_expressions[i.imm_operands++];
1545 i.op[i.operands].imms = exp;
1546 i.types[i.operands++] = Imm8;
1547 exp->X_op = O_constant;
1548 exp->X_add_number = i.tm.extension_opcode;
1549 i.tm.extension_opcode = None;
1550 }
252b5132 1551
29b0f896
AM		 1552 /* For insns with operands there are more diddles to do to the opcode. */
1553 if (i.operands)
1554 {
1555 if (!process_operands ())
1556 return;
1557 }
1558 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1559 {
1560 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1561 as_warn (_("translating to `%sp'"), i.tm.name);
1562 }
252b5132 1563
29b0f896
AM		 1564 /* Handle conversion of 'int $3' --> special int3 insn. */
1565 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1566 {
1567 i.tm.base_opcode = INT3_OPCODE;
1568 i.imm_operands = 0;
1569 }
252b5132 1570
29b0f896
AM		 1571 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1572 && i.op[0].disps->X_op == O_constant)
1573 {
1574 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1575 the absolute address given by the constant. Since ix86 jumps and
1576 calls are pc relative, we need to generate a reloc. */
1577 i.op[0].disps->X_add_symbol = &abs_symbol;
1578 i.op[0].disps->X_op = O_symbol;
1579 }
252b5132 1580
29b0f896
AM		 1581 if ((i.tm.opcode_modifier & Rex64) != 0)
1582 i.rex |= REX_MODE64;
252b5132 1583
29b0f896
AM		 1584 /* For 8 bit registers we need an empty rex prefix. Also if the
1585 instruction already has a prefix, we need to convert old
1586 registers to new ones. */
773f551c 1587
29b0f896
AM		 1588 if (((i.types[0] & Reg8) != 0
1589 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1590 || ((i.types[1] & Reg8) != 0
1591 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1592 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1593 && i.rex != 0))
1594 {
1595 int x;
726c5dcd 1596
29b0f896
AM		 1597 i.rex |= REX_OPCODE;
1598 for (x = 0; x < 2; x++)
1599 {
1600 /* Look for 8 bit operand that uses old registers. */
1601 if ((i.types[x] & Reg8) != 0
1602 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1603 {
29b0f896
AM		 1604 /* In case it is "hi" register, give up. */
1605 if (i.op[x].regs->reg_num > 3)
0477af35 1606 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1607 i.op[x].regs->reg_name);
773f551c 1608
29b0f896
AM		 1609 /* Otherwise it is equivalent to the extended register.
1610 Since the encoding doesn't change this is merely
1611 cosmetic cleanup for debug output. */
1612
1613 i.op[x].regs = i.op[x].regs + 8;
773f551c 1614 }
29b0f896
AM		 1615 }
1616 }
773f551c 1617
29b0f896
AM		 1618 if (i.rex != 0)
1619 add_prefix (REX_OPCODE | i.rex);
1620
1621 /* We are ready to output the insn. */
1622 output_insn ();
1623}
1624
1625static char *
1626parse_insn (line, mnemonic)
1627 char *line;
1628 char *mnemonic;
1629{
1630 char *l = line;
1631 char *token_start = l;
1632 char *mnem_p;
5c6af06e
JB		 1633 int supported;
1634 const template *t;
29b0f896
AM		 1635
1636 /* Non-zero if we found a prefix only acceptable with string insns. */
1637 const char *expecting_string_instruction = NULL;
45288df1 1638
29b0f896
AM		 1639 while (1)
1640 {
1641 mnem_p = mnemonic;
1642 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1643 {
1644 mnem_p++;
1645 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1646 {
29b0f896
AM		 1647 as_bad (_("no such instruction: `%s'"), token_start);
1648 return NULL;
1649 }
1650 l++;
1651 }
1652 if (!is_space_char (*l)
1653 && *l != END_OF_INSN
e44823cf
JB		 1654 && (intel_syntax
1655 || (*l != PREFIX_SEPARATOR
1656 && *l != ',')))
29b0f896
AM		 1657 {
1658 as_bad (_("invalid character %s in mnemonic"),
1659 output_invalid (*l));
1660 return NULL;
1661 }
1662 if (token_start == l)
1663 {
e44823cf 1664 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1665 as_bad (_("expecting prefix; got nothing"));
1666 else
1667 as_bad (_("expecting mnemonic; got nothing"));
1668 return NULL;
1669 }
45288df1 1670
29b0f896
AM		 1671 /* Look up instruction (or prefix) via hash table. */
1672 current_templates = hash_find (op_hash, mnemonic);
47926f60 1673
29b0f896
AM		 1674 if (*l != END_OF_INSN
1675 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1676 && current_templates
1677 && (current_templates->start->opcode_modifier & IsPrefix))
1678 {
2dd88dca
JB		 1679 if (current_templates->start->cpu_flags
1680 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1681 {
1682 as_bad ((flag_code != CODE_64BIT
1683 ? _("`%s' is only supported in 64-bit mode")
1684 : _("`%s' is not supported in 64-bit mode")),
1685 current_templates->start->name);
1686 return NULL;
1687 }
29b0f896
AM		 1688 /* If we are in 16-bit mode, do not allow addr16 or data16.
1689 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1690 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1691 && flag_code != CODE_64BIT
1692 && (((current_templates->start->opcode_modifier & Size32) != 0)
1693 ^ (flag_code == CODE_16BIT)))
1694 {
1695 as_bad (_("redundant %s prefix"),
1696 current_templates->start->name);
1697 return NULL;
45288df1 1698 }
29b0f896
AM		 1699 /* Add prefix, checking for repeated prefixes. */
1700 switch (add_prefix (current_templates->start->base_opcode))
1701 {
1702 case 0:
1703 return NULL;
1704 case 2:
1705 expecting_string_instruction = current_templates->start->name;
1706 break;
1707 }
1708 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1709 token_start = ++l;
1710 }
1711 else
1712 break;
1713 }
45288df1 1714
29b0f896
AM		 1715 if (!current_templates)
1716 {
1717 /* See if we can get a match by trimming off a suffix. */
1718 switch (mnem_p[-1])
1719 {
1720 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 1721 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1722 i.suffix = SHORT_MNEM_SUFFIX;
1723 else
29b0f896
AM		 1724 case BYTE_MNEM_SUFFIX:
1725 case QWORD_MNEM_SUFFIX:
1726 i.suffix = mnem_p[-1];
1727 mnem_p[-1] = '\0';
1728 current_templates = hash_find (op_hash, mnemonic);
1729 break;
1730 case SHORT_MNEM_SUFFIX:
1731 case LONG_MNEM_SUFFIX:
1732 if (!intel_syntax)
1733 {
1734 i.suffix = mnem_p[-1];
1735 mnem_p[-1] = '\0';
1736 current_templates = hash_find (op_hash, mnemonic);
1737 }
1738 break;
252b5132 1739
29b0f896
AM		 1740 /* Intel Syntax. */
1741 case 'd':
1742 if (intel_syntax)
1743 {
9306ca4a 1744 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 1745 i.suffix = SHORT_MNEM_SUFFIX;
1746 else
1747 i.suffix = LONG_MNEM_SUFFIX;
1748 mnem_p[-1] = '\0';
1749 current_templates = hash_find (op_hash, mnemonic);
1750 }
1751 break;
1752 }
1753 if (!current_templates)
1754 {
1755 as_bad (_("no such instruction: `%s'"), token_start);
1756 return NULL;
1757 }
1758 }
252b5132 1759
29b0f896
AM		 1760 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1761 {
1762 /* Check for a branch hint. We allow ",pt" and ",pn" for
1763 predict taken and predict not taken respectively.
1764 I'm not sure that branch hints actually do anything on loop
1765 and jcxz insns (JumpByte) for current Pentium4 chips. They
1766 may work in the future and it doesn't hurt to accept them
1767 now. */
1768 if (l[0] == ',' && l[1] == 'p')
1769 {
1770 if (l[2] == 't')
1771 {
1772 if (!add_prefix (DS_PREFIX_OPCODE))
1773 return NULL;
1774 l += 3;
1775 }
1776 else if (l[2] == 'n')
1777 {
1778 if (!add_prefix (CS_PREFIX_OPCODE))
1779 return NULL;
1780 l += 3;
1781 }
1782 }
1783 }
1784 /* Any other comma loses. */
1785 if (*l == ',')
1786 {
1787 as_bad (_("invalid character %s in mnemonic"),
1788 output_invalid (*l));
1789 return NULL;
1790 }
252b5132 1791
29b0f896 1792 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 1793 supported = 0;
1794 for (t = current_templates->start; t < current_templates->end; ++t)
1795 {
1796 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1797 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1798 supported |= 1;
1799 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1800 supported |= 2;
1801 }
1802 if (!(supported & 2))
1803 {
1804 as_bad (flag_code == CODE_64BIT
1805 ? _("`%s' is not supported in 64-bit mode")
1806 : _("`%s' is only supported in 64-bit mode"),
1807 current_templates->start->name);
1808 return NULL;
1809 }
1810 if (!(supported & 1))
29b0f896 1811 {
5c6af06e
JB		 1812 as_warn (_("`%s' is not supported on `%s%s'"),
1813 current_templates->start->name,
1814 cpu_arch_name,
1815 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 1816 }
1817 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1818 {
1819 as_warn (_("use .code16 to ensure correct addressing mode"));
1820 }
252b5132 1821
29b0f896 1822 /* Check for rep/repne without a string instruction. */
f41bbced 1823 if (expecting_string_instruction)
29b0f896 1824 {
f41bbced
JB		 1825 static templates override;
1826
1827 for (t = current_templates->start; t < current_templates->end; ++t)
1828 if (t->opcode_modifier & IsString)
1829 break;
1830 if (t >= current_templates->end)
1831 {
1832 as_bad (_("expecting string instruction after `%s'"),
1833 expecting_string_instruction);
1834 return NULL;
1835 }
1836 for (override.start = t; t < current_templates->end; ++t)
1837 if (!(t->opcode_modifier & IsString))
1838 break;
1839 override.end = t;
1840 current_templates = &override;
29b0f896 1841 }
252b5132 1842
29b0f896
AM		 1843 return l;
1844}
252b5132 1845
29b0f896
AM		 1846static char *
1847parse_operands (l, mnemonic)
1848 char *l;
1849 const char *mnemonic;
1850{
1851 char *token_start;
3138f287 1852
29b0f896
AM		 1853 /* 1 if operand is pending after ','. */
1854 unsigned int expecting_operand = 0;
252b5132 1855
29b0f896
AM		 1856 /* Non-zero if operand parens not balanced. */
1857 unsigned int paren_not_balanced;
1858
1859 while (*l != END_OF_INSN)
1860 {
1861 /* Skip optional white space before operand. */
1862 if (is_space_char (*l))
1863 ++l;
1864 if (!is_operand_char (*l) && *l != END_OF_INSN)
1865 {
1866 as_bad (_("invalid character %s before operand %d"),
1867 output_invalid (*l),
1868 i.operands + 1);
1869 return NULL;
1870 }
1871 token_start = l; /* after white space */
1872 paren_not_balanced = 0;
1873 while (paren_not_balanced || *l != ',')
1874 {
1875 if (*l == END_OF_INSN)
1876 {
1877 if (paren_not_balanced)
1878 {
1879 if (!intel_syntax)
1880 as_bad (_("unbalanced parenthesis in operand %d."),
1881 i.operands + 1);
1882 else
1883 as_bad (_("unbalanced brackets in operand %d."),
1884 i.operands + 1);
1885 return NULL;
1886 }
1887 else
1888 break; /* we are done */
1889 }
1890 else if (!is_operand_char (*l) && !is_space_char (*l))
1891 {
1892 as_bad (_("invalid character %s in operand %d"),
1893 output_invalid (*l),
1894 i.operands + 1);
1895 return NULL;
1896 }
1897 if (!intel_syntax)
1898 {
1899 if (*l == '(')
1900 ++paren_not_balanced;
1901 if (*l == ')')
1902 --paren_not_balanced;
1903 }
1904 else
1905 {
1906 if (*l == '[')
1907 ++paren_not_balanced;
1908 if (*l == ']')
1909 --paren_not_balanced;
1910 }
1911 l++;
1912 }
1913 if (l != token_start)
1914 { /* Yes, we've read in another operand. */
1915 unsigned int operand_ok;
1916 this_operand = i.operands++;
1917 if (i.operands > MAX_OPERANDS)
1918 {
1919 as_bad (_("spurious operands; (%d operands/instruction max)"),
1920 MAX_OPERANDS);
1921 return NULL;
1922 }
1923 /* Now parse operand adding info to 'i' as we go along. */
1924 END_STRING_AND_SAVE (l);
1925
1926 if (intel_syntax)
1927 operand_ok =
1928 i386_intel_operand (token_start,
1929 intel_float_operand (mnemonic));
1930 else
1931 operand_ok = i386_operand (token_start);
1932
1933 RESTORE_END_STRING (l);
1934 if (!operand_ok)
1935 return NULL;
1936 }
1937 else
1938 {
1939 if (expecting_operand)
1940 {
1941 expecting_operand_after_comma:
1942 as_bad (_("expecting operand after ','; got nothing"));
1943 return NULL;
1944 }
1945 if (*l == ',')
1946 {
1947 as_bad (_("expecting operand before ','; got nothing"));
1948 return NULL;
1949 }
1950 }
7f3f1ea2 1951
29b0f896
AM		 1952 /* Now *l must be either ',' or END_OF_INSN. */
1953 if (*l == ',')
1954 {
1955 if (*++l == END_OF_INSN)
1956 {
1957 /* Just skip it, if it's \n complain. */
1958 goto expecting_operand_after_comma;
1959 }
1960 expecting_operand = 1;
1961 }
1962 }
1963 return l;
1964}
7f3f1ea2 1965
29b0f896
AM		 1966static void
1967swap_operands ()
1968{
1969 union i386_op temp_op;
1970 unsigned int temp_type;
f86103b7 1971 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 1972 int xchg1 = 0;
1973 int xchg2 = 0;
252b5132 1974
29b0f896
AM		 1975 if (i.operands == 2)
1976 {
1977 xchg1 = 0;
1978 xchg2 = 1;
1979 }
1980 else if (i.operands == 3)
1981 {
1982 xchg1 = 0;
1983 xchg2 = 2;
1984 }
1985 temp_type = i.types[xchg2];
1986 i.types[xchg2] = i.types[xchg1];
1987 i.types[xchg1] = temp_type;
1988 temp_op = i.op[xchg2];
1989 i.op[xchg2] = i.op[xchg1];
1990 i.op[xchg1] = temp_op;
1991 temp_reloc = i.reloc[xchg2];
1992 i.reloc[xchg2] = i.reloc[xchg1];
1993 i.reloc[xchg1] = temp_reloc;
1994
1995 if (i.mem_operands == 2)
1996 {
1997 const seg_entry *temp_seg;
1998 temp_seg = i.seg[0];
1999 i.seg[0] = i.seg[1];
2000 i.seg[1] = temp_seg;
2001 }
2002}
252b5132 2003
29b0f896
AM		 2004/* Try to ensure constant immediates are represented in the smallest
2005 opcode possible. */
2006static void
2007optimize_imm ()
2008{
2009 char guess_suffix = 0;
2010 int op;
252b5132 2011
29b0f896
AM		 2012 if (i.suffix)
2013 guess_suffix = i.suffix;
2014 else if (i.reg_operands)
2015 {
2016 /* Figure out a suffix from the last register operand specified.
2017 We can't do this properly yet, ie. excluding InOutPortReg,
2018 but the following works for instructions with immediates.
2019 In any case, we can't set i.suffix yet. */
2020 for (op = i.operands; --op >= 0;)
2021 if (i.types[op] & Reg)
252b5132 2022 {
29b0f896
AM		 2023 if (i.types[op] & Reg8)
2024 guess_suffix = BYTE_MNEM_SUFFIX;
2025 else if (i.types[op] & Reg16)
2026 guess_suffix = WORD_MNEM_SUFFIX;
2027 else if (i.types[op] & Reg32)
2028 guess_suffix = LONG_MNEM_SUFFIX;
2029 else if (i.types[op] & Reg64)
2030 guess_suffix = QWORD_MNEM_SUFFIX;
2031 break;
252b5132 2032 }
29b0f896
AM		 2033 }
2034 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2035 guess_suffix = WORD_MNEM_SUFFIX;
2036
2037 for (op = i.operands; --op >= 0;)
2038 if (i.types[op] & Imm)
2039 {
2040 switch (i.op[op].imms->X_op)
252b5132 2041 {
29b0f896
AM		 2042 case O_constant:
2043 /* If a suffix is given, this operand may be shortened. */
2044 switch (guess_suffix)
252b5132 2045 {
29b0f896
AM		 2046 case LONG_MNEM_SUFFIX:
2047 i.types[op] |= Imm32 | Imm64;
2048 break;
2049 case WORD_MNEM_SUFFIX:
2050 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2051 break;
2052 case BYTE_MNEM_SUFFIX:
2053 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2054 break;
252b5132 2055 }
252b5132 2056
29b0f896
AM		 2057 /* If this operand is at most 16 bits, convert it
2058 to a signed 16 bit number before trying to see
2059 whether it will fit in an even smaller size.
2060 This allows a 16-bit operand such as $0xffe0 to
2061 be recognised as within Imm8S range. */
2062 if ((i.types[op] & Imm16)
2063 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2064 {
29b0f896
AM		 2065 i.op[op].imms->X_add_number =
2066 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2067 }
2068 if ((i.types[op] & Imm32)
2069 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2070 == 0))
2071 {
2072 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2073 ^ ((offsetT) 1 << 31))
2074 - ((offsetT) 1 << 31));
2075 }
2076 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2077
29b0f896
AM		 2078 /* We must avoid matching of Imm32 templates when 64bit
2079 only immediate is available. */
2080 if (guess_suffix == QWORD_MNEM_SUFFIX)
2081 i.types[op] &= ~Imm32;
2082 break;
252b5132 2083
29b0f896
AM		 2084 case O_absent:
2085 case O_register:
2086 abort ();
2087
2088 /* Symbols and expressions. */
2089 default:
9cd96992
JB		 2090 /* Convert symbolic operand to proper sizes for matching, but don't
2091 prevent matching a set of insns that only supports sizes other
2092 than those matching the insn suffix. */
2093 {
2094 unsigned int mask, allowed = 0;
2095 const template *t;
2096
2097 for (t = current_templates->start; t < current_templates->end; ++t)
2098 allowed |= t->operand_types[op];
2099 switch (guess_suffix)
2100 {
2101 case QWORD_MNEM_SUFFIX:
2102 mask = Imm64 | Imm32S;
2103 break;
2104 case LONG_MNEM_SUFFIX:
2105 mask = Imm32;
2106 break;
2107 case WORD_MNEM_SUFFIX:
2108 mask = Imm16;
2109 break;
2110 case BYTE_MNEM_SUFFIX:
2111 mask = Imm8;
2112 break;
2113 default:
2114 mask = 0;
2115 break;
2116 }
2117 if (mask & allowed)
2118 i.types[op] &= mask;
2119 }
29b0f896 2120 break;
252b5132 2121 }
29b0f896
AM		 2122 }
2123}
47926f60 2124
29b0f896
AM		 2125/* Try to use the smallest displacement type too. */
2126static void
2127optimize_disp ()
2128{
2129 int op;
3e73aa7c 2130
29b0f896 2131 for (op = i.operands; --op >= 0;)
b300c311 2132 if (i.types[op] & Disp)
252b5132 2133 {
b300c311 2134 if (i.op[op].disps->X_op == O_constant)
252b5132 2135 {
b300c311 2136 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2137
b300c311
L		 2138 if ((i.types[op] & Disp16)
2139 && (disp & ~(offsetT) 0xffff) == 0)
2140 {
2141 /* If this operand is at most 16 bits, convert
2142 to a signed 16 bit number and don't use 64bit
2143 displacement. */
2144 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2145 i.types[op] &= ~Disp64;
2146 }
2147 if ((i.types[op] & Disp32)
2148 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2149 {
2150 /* If this operand is at most 32 bits, convert
2151 to a signed 32 bit number and don't use 64bit
2152 displacement. */
2153 disp &= (((offsetT) 2 << 31) - 1);
2154 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2155 i.types[op] &= ~Disp64;
2156 }
2157 if (!disp && (i.types[op] & BaseIndex))
2158 {
2159 i.types[op] &= ~Disp;
2160 i.op[op].disps = 0;
2161 i.disp_operands--;
2162 }
2163 else if (flag_code == CODE_64BIT)
2164 {
2165 if (fits_in_signed_long (disp))
28a9d8f5
L		 2166 {
2167 i.types[op] &= ~Disp64;
2168 i.types[op] |= Disp32S;
2169 }
b300c311
L		 2170 if (fits_in_unsigned_long (disp))
2171 i.types[op] |= Disp32;
2172 }
2173 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2174 && fits_in_signed_byte (disp))
2175 i.types[op] |= Disp8;
252b5132 2176 }
b300c311
L		 2177 else
2178 /* We only support 64bit displacement on constants. */
2179 i.types[op] &= ~Disp64;
252b5132 2180 }
29b0f896
AM		 2181}
2182
2183static int
2184match_template ()
2185{
2186 /* Points to template once we've found it. */
2187 const template *t;
2188 unsigned int overlap0, overlap1, overlap2;
2189 unsigned int found_reverse_match;
2190 int suffix_check;
2191
2192#define MATCH(overlap, given, template) \
2193 ((overlap & ~JumpAbsolute) \
2194 && (((given) & (BaseIndex | JumpAbsolute)) \
2195 == ((overlap) & (BaseIndex | JumpAbsolute))))
2196
2197 /* If given types r0 and r1 are registers they must be of the same type
2198 unless the expected operand type register overlap is null.
2199 Note that Acc in a template matches every size of reg. */
2200#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2201 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2202 || ((g0) & Reg) == ((g1) & Reg) \
2203 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2204
2205 overlap0 = 0;
2206 overlap1 = 0;
2207 overlap2 = 0;
2208 found_reverse_match = 0;
2209 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2210 ? No_bSuf
2211 : (i.suffix == WORD_MNEM_SUFFIX
2212 ? No_wSuf
2213 : (i.suffix == SHORT_MNEM_SUFFIX
2214 ? No_sSuf
2215 : (i.suffix == LONG_MNEM_SUFFIX
2216 ? No_lSuf
2217 : (i.suffix == QWORD_MNEM_SUFFIX
2218 ? No_qSuf
2219 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2220 ? No_xSuf : 0))))));
2221
20f0a1fc
NC		 2222 t = current_templates->start;
2223 if (i.suffix == QWORD_MNEM_SUFFIX
2224 && flag_code != CODE_64BIT
9306ca4a
JB		 2225 && (intel_syntax
2226 ? !(t->opcode_modifier & IgnoreSize)
2227 && !intel_float_operand (t->name)
2228 : intel_float_operand (t->name) != 2)
20f0a1fc
NC		 2229 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2230 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2231 && (t->base_opcode != 0x0fc7
2232 || t->extension_opcode != 1 /* cmpxchg8b */))
2233 t = current_templates->end;
2234 for (; t < current_templates->end; t++)
29b0f896
AM		 2235 {
2236 /* Must have right number of operands. */
2237 if (i.operands != t->operands)
2238 continue;
2239
2240 /* Check the suffix, except for some instructions in intel mode. */
2241 if ((t->opcode_modifier & suffix_check)
2242 && !(intel_syntax
9306ca4a 2243 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2244 continue;
2245
2246 /* Do not verify operands when there are none. */
2247 else if (!t->operands)
2248 {
2249 if (t->cpu_flags & ~cpu_arch_flags)
2250 continue;
2251 /* We've found a match; break out of loop. */
2252 break;
2253 }
252b5132 2254
29b0f896
AM		 2255 overlap0 = i.types[0] & t->operand_types[0];
2256 switch (t->operands)
2257 {
2258 case 1:
2259 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2260 continue;
2261 break;
2262 case 2:
2263 case 3:
2264 overlap1 = i.types[1] & t->operand_types[1];
2265 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2266 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2267 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2268 t->operand_types[0],
2269 overlap1, i.types[1],
2270 t->operand_types[1]))
2271 {
2272 /* Check if other direction is valid ... */
2273 if ((t->opcode_modifier & (D | FloatD)) == 0)
2274 continue;
2275
2276 /* Try reversing direction of operands. */
2277 overlap0 = i.types[0] & t->operand_types[1];
2278 overlap1 = i.types[1] & t->operand_types[0];
2279 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2280 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2281 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2282 t->operand_types[1],
2283 overlap1, i.types[1],
2284 t->operand_types[0]))
2285 {
2286 /* Does not match either direction. */
2287 continue;
2288 }
2289 /* found_reverse_match holds which of D or FloatDR
2290 we've found. */
2291 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2292 }
2293 /* Found a forward 2 operand match here. */
2294 else if (t->operands == 3)
2295 {
2296 /* Here we make use of the fact that there are no
2297 reverse match 3 operand instructions, and all 3
2298 operand instructions only need to be checked for
2299 register consistency between operands 2 and 3. */
2300 overlap2 = i.types[2] & t->operand_types[2];
2301 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2302 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2303 t->operand_types[1],
2304 overlap2, i.types[2],
2305 t->operand_types[2]))
2306
2307 continue;
2308 }
2309 /* Found either forward/reverse 2 or 3 operand match here:
2310 slip through to break. */
2311 }
2312 if (t->cpu_flags & ~cpu_arch_flags)
2313 {
2314 found_reverse_match = 0;
2315 continue;
2316 }
2317 /* We've found a match; break out of loop. */
2318 break;
2319 }
2320
2321 if (t == current_templates->end)
2322 {
2323 /* We found no match. */
2324 as_bad (_("suffix or operands invalid for `%s'"),
2325 current_templates->start->name);
2326 return 0;
2327 }
252b5132 2328
29b0f896
AM		 2329 if (!quiet_warnings)
2330 {
2331 if (!intel_syntax
2332 && ((i.types[0] & JumpAbsolute)
2333 != (t->operand_types[0] & JumpAbsolute)))
2334 {
2335 as_warn (_("indirect %s without `*'"), t->name);
2336 }
2337
2338 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2339 == (IsPrefix | IgnoreSize))
2340 {
2341 /* Warn them that a data or address size prefix doesn't
2342 affect assembly of the next line of code. */
2343 as_warn (_("stand-alone `%s' prefix"), t->name);
2344 }
2345 }
2346
2347 /* Copy the template we found. */
2348 i.tm = *t;
2349 if (found_reverse_match)
2350 {
2351 /* If we found a reverse match we must alter the opcode
2352 direction bit. found_reverse_match holds bits to change
2353 (different for int & float insns). */
2354
2355 i.tm.base_opcode ^= found_reverse_match;
2356
2357 i.tm.operand_types[0] = t->operand_types[1];
2358 i.tm.operand_types[1] = t->operand_types[0];
2359 }
2360
2361 return 1;
2362}
2363
2364static int
2365check_string ()
2366{
2367 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2368 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2369 {
2370 if (i.seg[0] != NULL && i.seg[0] != &es)
2371 {
2372 as_bad (_("`%s' operand %d must use `%%es' segment"),
2373 i.tm.name,
2374 mem_op + 1);
2375 return 0;
2376 }
2377 /* There's only ever one segment override allowed per instruction.
2378 This instruction possibly has a legal segment override on the
2379 second operand, so copy the segment to where non-string
2380 instructions store it, allowing common code. */
2381 i.seg[0] = i.seg[1];
2382 }
2383 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2384 {
2385 if (i.seg[1] != NULL && i.seg[1] != &es)
2386 {
2387 as_bad (_("`%s' operand %d must use `%%es' segment"),
2388 i.tm.name,
2389 mem_op + 2);
2390 return 0;
2391 }
2392 }
2393 return 1;
2394}
2395
2396static int
543613e9 2397process_suffix (void)
29b0f896
AM		 2398{
2399 /* If matched instruction specifies an explicit instruction mnemonic
2400 suffix, use it. */
2401 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2402 {
2403 if (i.tm.opcode_modifier & Size16)
2404 i.suffix = WORD_MNEM_SUFFIX;
2405 else if (i.tm.opcode_modifier & Size64)
2406 i.suffix = QWORD_MNEM_SUFFIX;
2407 else
2408 i.suffix = LONG_MNEM_SUFFIX;
2409 }
2410 else if (i.reg_operands)
2411 {
2412 /* If there's no instruction mnemonic suffix we try to invent one
2413 based on register operands. */
2414 if (!i.suffix)
2415 {
2416 /* We take i.suffix from the last register operand specified,
2417 Destination register type is more significant than source
2418 register type. */
2419 int op;
543613e9 2420
29b0f896
AM		 2421 for (op = i.operands; --op >= 0;)
2422 if ((i.types[op] & Reg)
2423 && !(i.tm.operand_types[op] & InOutPortReg))
2424 {
2425 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2426 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2427 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2428 LONG_MNEM_SUFFIX);
2429 break;
2430 }
2431 }
2432 else if (i.suffix == BYTE_MNEM_SUFFIX)
2433 {
2434 if (!check_byte_reg ())
2435 return 0;
2436 }
2437 else if (i.suffix == LONG_MNEM_SUFFIX)
2438 {
2439 if (!check_long_reg ())
2440 return 0;
2441 }
2442 else if (i.suffix == QWORD_MNEM_SUFFIX)
2443 {
2444 if (!check_qword_reg ())
2445 return 0;
2446 }
2447 else if (i.suffix == WORD_MNEM_SUFFIX)
2448 {
2449 if (!check_word_reg ())
2450 return 0;
2451 }
2452 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2453 /* Do nothing if the instruction is going to ignore the prefix. */
2454 ;
2455 else
2456 abort ();
2457 }
9306ca4a
JB		 2458 else if ((i.tm.opcode_modifier & DefaultSize)
2459 && !i.suffix
2460 /* exclude fldenv/frstor/fsave/fstenv */
2461 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2462 {
2463 i.suffix = stackop_size;
2464 }
9306ca4a
JB		 2465 else if (intel_syntax
2466 && !i.suffix
2467 && ((i.tm.operand_types[0] & JumpAbsolute)
2468 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2469 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2470 && i.tm.extension_opcode <= 3)))
2471 {
2472 switch (flag_code)
2473 {
2474 case CODE_64BIT:
2475 if (!(i.tm.opcode_modifier & No_qSuf))
2476 {
2477 i.suffix = QWORD_MNEM_SUFFIX;
2478 break;
2479 }
2480 case CODE_32BIT:
2481 if (!(i.tm.opcode_modifier & No_lSuf))
2482 i.suffix = LONG_MNEM_SUFFIX;
2483 break;
2484 case CODE_16BIT:
2485 if (!(i.tm.opcode_modifier & No_wSuf))
2486 i.suffix = WORD_MNEM_SUFFIX;
2487 break;
2488 }
2489 }
252b5132 2490
9306ca4a 2491 if (!i.suffix)
29b0f896 2492 {
9306ca4a
JB		 2493 if (!intel_syntax)
2494 {
2495 if (i.tm.opcode_modifier & W)
2496 {
2497 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2498 return 0;
2499 }
2500 }
2501 else
2502 {
2503 unsigned int suffixes = ~i.tm.opcode_modifier
2504 & (No_bSuf
2505 | No_wSuf
2506 | No_lSuf
2507 | No_sSuf
2508 | No_xSuf
2509 | No_qSuf);
2510
2511 if ((i.tm.opcode_modifier & W)
2512 || ((suffixes & (suffixes - 1))
2513 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2514 {
2515 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2516 return 0;
2517 }
2518 }
29b0f896 2519 }
252b5132 2520
9306ca4a
JB		 2521 /* Change the opcode based on the operand size given by i.suffix;
2522 We don't need to change things for byte insns. */
2523
29b0f896
AM		 2524 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2525 {
2526 /* It's not a byte, select word/dword operation. */
2527 if (i.tm.opcode_modifier & W)
2528 {
2529 if (i.tm.opcode_modifier & ShortForm)
2530 i.tm.base_opcode |= 8;
2531 else
2532 i.tm.base_opcode |= 1;
2533 }
0f3f3d8b 2534
29b0f896
AM		 2535 /* Now select between word & dword operations via the operand
2536 size prefix, except for instructions that will ignore this
2537 prefix anyway. */
2538 if (i.suffix != QWORD_MNEM_SUFFIX
9306ca4a
JB		 2539 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2540 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
9146926a
AM		 2541 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2542 || (flag_code == CODE_64BIT
2543 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2544 {
2545 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2546
29b0f896
AM		 2547 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2548 prefix = ADDR_PREFIX_OPCODE;
252b5132 2549
29b0f896
AM		 2550 if (!add_prefix (prefix))
2551 return 0;
24eab124 2552 }
252b5132 2553
29b0f896
AM		 2554 /* Set mode64 for an operand. */
2555 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2556 && flag_code == CODE_64BIT
29b0f896 2557 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2558 i.rex |= REX_MODE64;
3e73aa7c 2559
29b0f896
AM		 2560 /* Size floating point instruction. */
2561 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2562 if (i.tm.opcode_modifier & FloatMF)
2563 i.tm.base_opcode ^= 4;
29b0f896 2564 }
7ecd2f8b 2565
29b0f896
AM		 2566 return 1;
2567}
3e73aa7c 2568
29b0f896 2569static int
543613e9 2570check_byte_reg (void)
29b0f896
AM		 2571{
2572 int op;
543613e9 2573
29b0f896
AM		 2574 for (op = i.operands; --op >= 0;)
2575 {
2576 /* If this is an eight bit register, it's OK. If it's the 16 or
2577 32 bit version of an eight bit register, we will just use the
2578 low portion, and that's OK too. */
2579 if (i.types[op] & Reg8)
2580 continue;
2581
2582 /* movzx and movsx should not generate this warning. */
2583 if (intel_syntax
2584 && (i.tm.base_opcode == 0xfb7
2585 || i.tm.base_opcode == 0xfb6
2586 || i.tm.base_opcode == 0x63
2587 || i.tm.base_opcode == 0xfbe
2588 || i.tm.base_opcode == 0xfbf))
2589 continue;
2590
65ec77d2 2591 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2592 {
2593 /* Prohibit these changes in the 64bit mode, since the
2594 lowering is more complicated. */
2595 if (flag_code == CODE_64BIT
2596 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2597 {
0f3f3d8b 2598 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2599 i.op[op].regs->reg_name,
2600 i.suffix);
2601 return 0;
2602 }
2603#if REGISTER_WARNINGS
2604 if (!quiet_warnings
2605 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2606 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2607 (i.op[op].regs + (i.types[op] & Reg16
2608 ? REGNAM_AL - REGNAM_AX
2609 : REGNAM_AL - REGNAM_EAX))->reg_name,
2610 i.op[op].regs->reg_name,
2611 i.suffix);
2612#endif
2613 continue;
2614 }
2615 /* Any other register is bad. */
2616 if (i.types[op] & (Reg | RegMMX | RegXMM
2617 | SReg2 | SReg3
2618 | Control | Debug | Test
2619 | FloatReg | FloatAcc))
2620 {
2621 as_bad (_("`%%%s' not allowed with `%s%c'"),
2622 i.op[op].regs->reg_name,
2623 i.tm.name,
2624 i.suffix);
2625 return 0;
2626 }
2627 }
2628 return 1;
2629}
2630
2631static int
2632check_long_reg ()
2633{
2634 int op;
2635
2636 for (op = i.operands; --op >= 0;)
2637 /* Reject eight bit registers, except where the template requires
2638 them. (eg. movzb) */
2639 if ((i.types[op] & Reg8) != 0
2640 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2641 {
2642 as_bad (_("`%%%s' not allowed with `%s%c'"),
2643 i.op[op].regs->reg_name,
2644 i.tm.name,
2645 i.suffix);
2646 return 0;
2647 }
2648 /* Warn if the e prefix on a general reg is missing. */
2649 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2650 && (i.types[op] & Reg16) != 0
2651 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2652 {
2653 /* Prohibit these changes in the 64bit mode, since the
2654 lowering is more complicated. */
2655 if (flag_code == CODE_64BIT)
252b5132 2656 {
0f3f3d8b 2657 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2658 i.op[op].regs->reg_name,
2659 i.suffix);
2660 return 0;
252b5132 2661 }
29b0f896
AM		 2662#if REGISTER_WARNINGS
2663 else
2664 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2665 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2666 i.op[op].regs->reg_name,
2667 i.suffix);
2668#endif
252b5132 2669 }
29b0f896
AM		 2670 /* Warn if the r prefix on a general reg is missing. */
2671 else if ((i.types[op] & Reg64) != 0
2672 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2673 {
0f3f3d8b 2674 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2675 i.op[op].regs->reg_name,
2676 i.suffix);
2677 return 0;
2678 }
2679 return 1;
2680}
252b5132 2681
29b0f896
AM		 2682static int
2683check_qword_reg ()
2684{
2685 int op;
252b5132 2686
29b0f896
AM		 2687 for (op = i.operands; --op >= 0; )
2688 /* Reject eight bit registers, except where the template requires
2689 them. (eg. movzb) */
2690 if ((i.types[op] & Reg8) != 0
2691 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2692 {
2693 as_bad (_("`%%%s' not allowed with `%s%c'"),
2694 i.op[op].regs->reg_name,
2695 i.tm.name,
2696 i.suffix);
2697 return 0;
2698 }
2699 /* Warn if the e prefix on a general reg is missing. */
2700 else if (((i.types[op] & Reg16) != 0
2701 || (i.types[op] & Reg32) != 0)
2702 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2703 {
2704 /* Prohibit these changes in the 64bit mode, since the
2705 lowering is more complicated. */
0f3f3d8b 2706 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2707 i.op[op].regs->reg_name,
2708 i.suffix);
2709 return 0;
252b5132 2710 }
29b0f896
AM		 2711 return 1;
2712}
252b5132 2713
29b0f896
AM		 2714static int
2715check_word_reg ()
2716{
2717 int op;
2718 for (op = i.operands; --op >= 0;)
2719 /* Reject eight bit registers, except where the template requires
2720 them. (eg. movzb) */
2721 if ((i.types[op] & Reg8) != 0
2722 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2723 {
2724 as_bad (_("`%%%s' not allowed with `%s%c'"),
2725 i.op[op].regs->reg_name,
2726 i.tm.name,
2727 i.suffix);
2728 return 0;
2729 }
2730 /* Warn if the e prefix on a general reg is present. */
2731 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2732 && (i.types[op] & Reg32) != 0
2733 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2734 {
29b0f896
AM		 2735 /* Prohibit these changes in the 64bit mode, since the
2736 lowering is more complicated. */
2737 if (flag_code == CODE_64BIT)
252b5132 2738 {
0f3f3d8b 2739 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2740 i.op[op].regs->reg_name,
2741 i.suffix);
2742 return 0;
252b5132 2743 }
29b0f896
AM		 2744 else
2745#if REGISTER_WARNINGS
2746 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2747 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2748 i.op[op].regs->reg_name,
2749 i.suffix);
2750#endif
2751 }
2752 return 1;
2753}
252b5132 2754
29b0f896
AM		 2755static int
2756finalize_imm ()
2757{
2758 unsigned int overlap0, overlap1, overlap2;
2759
2760 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 2761 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 2762 && overlap0 != Imm8 && overlap0 != Imm8S
2763 && overlap0 != Imm16 && overlap0 != Imm32S
2764 && overlap0 != Imm32 && overlap0 != Imm64)
2765 {
2766 if (i.suffix)
2767 {
2768 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2769 ? Imm8 | Imm8S
2770 : (i.suffix == WORD_MNEM_SUFFIX
2771 ? Imm16
2772 : (i.suffix == QWORD_MNEM_SUFFIX
2773 ? Imm64 | Imm32S
2774 : Imm32)));
2775 }
2776 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2777 || overlap0 == (Imm16 | Imm32)
2778 || overlap0 == (Imm16 | Imm32S))
2779 {
2780 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2781 ? Imm16 : Imm32S);
2782 }
2783 if (overlap0 != Imm8 && overlap0 != Imm8S
2784 && overlap0 != Imm16 && overlap0 != Imm32S
2785 && overlap0 != Imm32 && overlap0 != Imm64)
2786 {
2787 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2788 return 0;
2789 }
2790 }
2791 i.types[0] = overlap0;
2792
2793 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 2794 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 2795 && overlap1 != Imm8 && overlap1 != Imm8S
2796 && overlap1 != Imm16 && overlap1 != Imm32S
2797 && overlap1 != Imm32 && overlap1 != Imm64)
2798 {
2799 if (i.suffix)
2800 {
2801 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2802 ? Imm8 | Imm8S
2803 : (i.suffix == WORD_MNEM_SUFFIX
2804 ? Imm16
2805 : (i.suffix == QWORD_MNEM_SUFFIX
2806 ? Imm64 | Imm32S
2807 : Imm32)));
2808 }
2809 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2810 || overlap1 == (Imm16 | Imm32)
2811 || overlap1 == (Imm16 | Imm32S))
2812 {
2813 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2814 ? Imm16 : Imm32S);
2815 }
2816 if (overlap1 != Imm8 && overlap1 != Imm8S
2817 && overlap1 != Imm16 && overlap1 != Imm32S
2818 && overlap1 != Imm32 && overlap1 != Imm64)
2819 {
2820 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2821 return 0;
2822 }
2823 }
2824 i.types[1] = overlap1;
2825
2826 overlap2 = i.types[2] & i.tm.operand_types[2];
2827 assert ((overlap2 & Imm) == 0);
2828 i.types[2] = overlap2;
2829
2830 return 1;
2831}
2832
2833static int
2834process_operands ()
2835{
2836 /* Default segment register this instruction will use for memory
2837 accesses. 0 means unknown. This is only for optimizing out
2838 unnecessary segment overrides. */
2839 const seg_entry *default_seg = 0;
2840
2841 /* The imul $imm, %reg instruction is converted into
2842 imul $imm, %reg, %reg, and the clr %reg instruction
2843 is converted into xor %reg, %reg. */
2844 if (i.tm.opcode_modifier & regKludge)
2845 {
2846 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2847 /* Pretend we saw the extra register operand. */
2848 assert (i.op[first_reg_op + 1].regs == 0);
2849 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2850 i.types[first_reg_op + 1] = i.types[first_reg_op];
2851 i.reg_operands = 2;
2852 }
2853
2854 if (i.tm.opcode_modifier & ShortForm)
2855 {
2856 /* The register or float register operand is in operand 0 or 1. */
2857 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2858 /* Register goes in low 3 bits of opcode. */
2859 i.tm.base_opcode |= i.op[op].regs->reg_num;
2860 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2861 i.rex |= REX_EXTZ;
2862 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2863 {
2864 /* Warn about some common errors, but press on regardless.
2865 The first case can be generated by gcc (<= 2.8.1). */
2866 if (i.operands == 2)
2867 {
2868 /* Reversed arguments on faddp, fsubp, etc. */
2869 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2870 i.op[1].regs->reg_name,
2871 i.op[0].regs->reg_name);
2872 }
2873 else
2874 {
2875 /* Extraneous `l' suffix on fp insn. */
2876 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2877 i.op[0].regs->reg_name);
2878 }
2879 }
2880 }
2881 else if (i.tm.opcode_modifier & Modrm)
2882 {
2883 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2884 must be put into the modrm byte). Now, we make the modrm and
2885 index base bytes based on all the info we've collected. */
29b0f896
AM		 2886
2887 default_seg = build_modrm_byte ();
2888 }
2889 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2890 {
2891 if (i.tm.base_opcode == POP_SEG_SHORT
2892 && i.op[0].regs->reg_num == 1)
2893 {
2894 as_bad (_("you can't `pop %%cs'"));
2895 return 0;
2896 }
2897 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2898 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2899 i.rex |= REX_EXTZ;
2900 }
2901 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2902 {
2903 default_seg = &ds;
2904 }
2905 else if ((i.tm.opcode_modifier & IsString) != 0)
2906 {
2907 /* For the string instructions that allow a segment override
2908 on one of their operands, the default segment is ds. */
2909 default_seg = &ds;
2910 }
2911
30123838
JB		 2912 if ((i.tm.base_opcode == 0x8d /* lea */
2913 || (i.tm.cpu_flags & CpuSVME))
2914 && i.seg[0] && !quiet_warnings)
2915 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 2916
2917 /* If a segment was explicitly specified, and the specified segment
2918 is not the default, use an opcode prefix to select it. If we
2919 never figured out what the default segment is, then default_seg
2920 will be zero at this point, and the specified segment prefix will
2921 always be used. */
29b0f896
AM		 2922 if ((i.seg[0]) && (i.seg[0] != default_seg))
2923 {
2924 if (!add_prefix (i.seg[0]->seg_prefix))
2925 return 0;
2926 }
2927 return 1;
2928}
2929
2930static const seg_entry *
2931build_modrm_byte ()
2932{
2933 const seg_entry *default_seg = 0;
2934
2935 /* i.reg_operands MUST be the number of real register operands;
2936 implicit registers do not count. */
2937 if (i.reg_operands == 2)
2938 {
2939 unsigned int source, dest;
2940 source = ((i.types[0]
2941 & (Reg | RegMMX | RegXMM
2942 | SReg2 | SReg3
2943 | Control | Debug | Test))
2944 ? 0 : 1);
2945 dest = source + 1;
2946
2947 i.rm.mode = 3;
2948 /* One of the register operands will be encoded in the i.tm.reg
2949 field, the other in the combined i.tm.mode and i.tm.regmem
2950 fields. If no form of this instruction supports a memory
2951 destination operand, then we assume the source operand may
2952 sometimes be a memory operand and so we need to store the
2953 destination in the i.rm.reg field. */
2954 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2955 {
2956 i.rm.reg = i.op[dest].regs->reg_num;
2957 i.rm.regmem = i.op[source].regs->reg_num;
2958 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2959 i.rex |= REX_EXTX;
2960 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2961 i.rex |= REX_EXTZ;
2962 }
2963 else
2964 {
2965 i.rm.reg = i.op[source].regs->reg_num;
2966 i.rm.regmem = i.op[dest].regs->reg_num;
2967 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2968 i.rex |= REX_EXTZ;
2969 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2970 i.rex |= REX_EXTX;
2971 }
c4a530c5
JB		 2972 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
2973 {
2974 if (!((i.types[0] | i.types[1]) & Control))
2975 abort ();
2976 i.rex &= ~(REX_EXTX | REX_EXTZ);
2977 add_prefix (LOCK_PREFIX_OPCODE);
2978 }
29b0f896
AM		 2979 }
2980 else
2981 { /* If it's not 2 reg operands... */
2982 if (i.mem_operands)
2983 {
2984 unsigned int fake_zero_displacement = 0;
2985 unsigned int op = ((i.types[0] & AnyMem)
2986 ? 0
2987 : (i.types[1] & AnyMem) ? 1 : 2);
2988
2989 default_seg = &ds;
2990
2991 if (i.base_reg == 0)
2992 {
2993 i.rm.mode = 0;
2994 if (!i.disp_operands)
2995 fake_zero_displacement = 1;
2996 if (i.index_reg == 0)
2997 {
2998 /* Operand is just <disp> */
20f0a1fc 2999 if (flag_code == CODE_64BIT)
29b0f896
AM		 3000 {
3001 /* 64bit mode overwrites the 32bit absolute
3002 addressing by RIP relative addressing and
3003 absolute addressing is encoded by one of the
3004 redundant SIB forms. */
3005 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3006 i.sib.base = NO_BASE_REGISTER;
3007 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 3008 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3009 }
3010 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3011 {
3012 i.rm.regmem = NO_BASE_REGISTER_16;
3013 i.types[op] = Disp16;
3014 }
3015 else
3016 {
3017 i.rm.regmem = NO_BASE_REGISTER;
3018 i.types[op] = Disp32;
29b0f896
AM		 3019 }
3020 }
3021 else /* !i.base_reg && i.index_reg */
3022 {
3023 i.sib.index = i.index_reg->reg_num;
3024 i.sib.base = NO_BASE_REGISTER;
3025 i.sib.scale = i.log2_scale_factor;
3026 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3027 i.types[op] &= ~Disp;
3028 if (flag_code != CODE_64BIT)
3029 i.types[op] |= Disp32; /* Must be 32 bit */
3030 else
3031 i.types[op] |= Disp32S;
3032 if ((i.index_reg->reg_flags & RegRex) != 0)
3033 i.rex |= REX_EXTY;
3034 }
3035 }
3036 /* RIP addressing for 64bit mode. */
3037 else if (i.base_reg->reg_type == BaseIndex)
3038 {
3039 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3040 i.types[op] &= ~ Disp;
29b0f896
AM		 3041 i.types[op] |= Disp32S;
3042 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 3043 if (! i.disp_operands)
3044 fake_zero_displacement = 1;
29b0f896
AM		 3045 }
3046 else if (i.base_reg->reg_type & Reg16)
3047 {
3048 switch (i.base_reg->reg_num)
3049 {
3050 case 3: /* (%bx) */
3051 if (i.index_reg == 0)
3052 i.rm.regmem = 7;
3053 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3054 i.rm.regmem = i.index_reg->reg_num - 6;
3055 break;
3056 case 5: /* (%bp) */
3057 default_seg = &ss;
3058 if (i.index_reg == 0)
3059 {
3060 i.rm.regmem = 6;
3061 if ((i.types[op] & Disp) == 0)
3062 {
3063 /* fake (%bp) into 0(%bp) */
3064 i.types[op] |= Disp8;
252b5132 3065 fake_zero_displacement = 1;
29b0f896
AM		 3066 }
3067 }
3068 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3069 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3070 break;
3071 default: /* (%si) -> 4 or (%di) -> 5 */
3072 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3073 }
3074 i.rm.mode = mode_from_disp_size (i.types[op]);
3075 }
3076 else /* i.base_reg and 32/64 bit mode */
3077 {
3078 if (flag_code == CODE_64BIT
3079 && (i.types[op] & Disp))
20f0a1fc
NC		 3080 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3081
29b0f896
AM		 3082 i.rm.regmem = i.base_reg->reg_num;
3083 if ((i.base_reg->reg_flags & RegRex) != 0)
3084 i.rex |= REX_EXTZ;
3085 i.sib.base = i.base_reg->reg_num;
3086 /* x86-64 ignores REX prefix bit here to avoid decoder
3087 complications. */
3088 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3089 {
3090 default_seg = &ss;
3091 if (i.disp_operands == 0)
3092 {
3093 fake_zero_displacement = 1;
3094 i.types[op] |= Disp8;
3095 }
3096 }
3097 else if (i.base_reg->reg_num == ESP_REG_NUM)
3098 {
3099 default_seg = &ss;
3100 }
3101 i.sib.scale = i.log2_scale_factor;
3102 if (i.index_reg == 0)
3103 {
3104 /* <disp>(%esp) becomes two byte modrm with no index
3105 register. We've already stored the code for esp
3106 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3107 Any base register besides %esp will not use the
3108 extra modrm byte. */
3109 i.sib.index = NO_INDEX_REGISTER;
3110#if !SCALE1_WHEN_NO_INDEX
3111 /* Another case where we force the second modrm byte. */
3112 if (i.log2_scale_factor)
3113 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3114#endif
29b0f896
AM		 3115 }
3116 else
3117 {
3118 i.sib.index = i.index_reg->reg_num;
3119 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3120 if ((i.index_reg->reg_flags & RegRex) != 0)
3121 i.rex |= REX_EXTY;
3122 }
3123 i.rm.mode = mode_from_disp_size (i.types[op]);
3124 }
252b5132 3125
29b0f896
AM		 3126 if (fake_zero_displacement)
3127 {
3128 /* Fakes a zero displacement assuming that i.types[op]
3129 holds the correct displacement size. */
3130 expressionS *exp;
3131
3132 assert (i.op[op].disps == 0);
3133 exp = &disp_expressions[i.disp_operands++];
3134 i.op[op].disps = exp;
3135 exp->X_op = O_constant;
3136 exp->X_add_number = 0;
3137 exp->X_add_symbol = (symbolS *) 0;
3138 exp->X_op_symbol = (symbolS *) 0;
3139 }
3140 }
252b5132 3141
29b0f896
AM		 3142 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3143 (if any) based on i.tm.extension_opcode. Again, we must be
3144 careful to make sure that segment/control/debug/test/MMX
3145 registers are coded into the i.rm.reg field. */
3146 if (i.reg_operands)
3147 {
3148 unsigned int op =
3149 ((i.types[0]
3150 & (Reg | RegMMX | RegXMM
3151 | SReg2 | SReg3
3152 | Control | Debug | Test))
3153 ? 0
3154 : ((i.types[1]
3155 & (Reg | RegMMX | RegXMM
3156 | SReg2 | SReg3
3157 | Control | Debug | Test))
3158 ? 1
3159 : 2));
3160 /* If there is an extension opcode to put here, the register
3161 number must be put into the regmem field. */
3162 if (i.tm.extension_opcode != None)
3163 {
3164 i.rm.regmem = i.op[op].regs->reg_num;
3165 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3166 i.rex |= REX_EXTZ;
3167 }
3168 else
3169 {
3170 i.rm.reg = i.op[op].regs->reg_num;
3171 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3172 i.rex |= REX_EXTX;
3173 }
252b5132 3174
29b0f896
AM		 3175 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3176 must set it to 3 to indicate this is a register operand
3177 in the regmem field. */
3178 if (!i.mem_operands)
3179 i.rm.mode = 3;
3180 }
252b5132 3181
29b0f896
AM		 3182 /* Fill in i.rm.reg field with extension opcode (if any). */
3183 if (i.tm.extension_opcode != None)
3184 i.rm.reg = i.tm.extension_opcode;
3185 }
3186 return default_seg;
3187}
252b5132 3188
29b0f896
AM		 3189static void
3190output_branch ()
3191{
3192 char *p;
3193 int code16;
3194 int prefix;
3195 relax_substateT subtype;
3196 symbolS *sym;
3197 offsetT off;
3198
3199 code16 = 0;
3200 if (flag_code == CODE_16BIT)
3201 code16 = CODE16;
3202
3203 prefix = 0;
3204 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3205 {
29b0f896
AM		 3206 prefix = 1;
3207 i.prefixes -= 1;
3208 code16 ^= CODE16;
252b5132 3209 }
29b0f896
AM		 3210 /* Pentium4 branch hints. */
3211 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3212 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3213 {
29b0f896
AM		 3214 prefix++;
3215 i.prefixes--;
3216 }
3217 if (i.prefix[REX_PREFIX] != 0)
3218 {
3219 prefix++;
3220 i.prefixes--;
2f66722d
AM		 3221 }
3222
29b0f896
AM		 3223 if (i.prefixes != 0 && !intel_syntax)
3224 as_warn (_("skipping prefixes on this instruction"));
3225
3226 /* It's always a symbol; End frag & setup for relax.
3227 Make sure there is enough room in this frag for the largest
3228 instruction we may generate in md_convert_frag. This is 2
3229 bytes for the opcode and room for the prefix and largest
3230 displacement. */
3231 frag_grow (prefix + 2 + 4);
3232 /* Prefix and 1 opcode byte go in fr_fix. */
3233 p = frag_more (prefix + 1);
3234 if (i.prefix[DATA_PREFIX] != 0)
3235 *p++ = DATA_PREFIX_OPCODE;
3236 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3237 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3238 *p++ = i.prefix[SEG_PREFIX];
3239 if (i.prefix[REX_PREFIX] != 0)
3240 *p++ = i.prefix[REX_PREFIX];
3241 *p = i.tm.base_opcode;
3242
3243 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3244 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3245 else if ((cpu_arch_flags & Cpu386) != 0)
3246 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3247 else
3248 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3249 subtype |= code16;
3e73aa7c 3250
29b0f896
AM		 3251 sym = i.op[0].disps->X_add_symbol;
3252 off = i.op[0].disps->X_add_number;
3e73aa7c 3253
29b0f896
AM		 3254 if (i.op[0].disps->X_op != O_constant
3255 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3256 {
29b0f896
AM		 3257 /* Handle complex expressions. */
3258 sym = make_expr_symbol (i.op[0].disps);
3259 off = 0;
3260 }
3e73aa7c 3261
29b0f896
AM		 3262 /* 1 possible extra opcode + 4 byte displacement go in var part.
3263 Pass reloc in fr_var. */
3264 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3265}
3e73aa7c 3266
29b0f896
AM		 3267static void
3268output_jump ()
3269{
3270 char *p;
3271 int size;
3e02c1cc 3272 fixS *fixP;
29b0f896
AM		 3273
3274 if (i.tm.opcode_modifier & JumpByte)
3275 {
3276 /* This is a loop or jecxz type instruction. */
3277 size = 1;
3278 if (i.prefix[ADDR_PREFIX] != 0)
3279 {
3280 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3281 i.prefixes -= 1;
3282 }
3283 /* Pentium4 branch hints. */
3284 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3285 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3286 {
3287 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3288 i.prefixes--;
3e73aa7c
JH		 3289 }
3290 }
29b0f896
AM		 3291 else
3292 {
3293 int code16;
3e73aa7c 3294
29b0f896
AM		 3295 code16 = 0;
3296 if (flag_code == CODE_16BIT)
3297 code16 = CODE16;
3e73aa7c 3298
29b0f896
AM		 3299 if (i.prefix[DATA_PREFIX] != 0)
3300 {
3301 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3302 i.prefixes -= 1;
3303 code16 ^= CODE16;
3304 }
252b5132 3305
29b0f896
AM		 3306 size = 4;
3307 if (code16)
3308 size = 2;
3309 }
9fcc94b6 3310
29b0f896
AM		 3311 if (i.prefix[REX_PREFIX] != 0)
3312 {
3313 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3314 i.prefixes -= 1;
3315 }
252b5132 3316
29b0f896
AM		 3317 if (i.prefixes != 0 && !intel_syntax)
3318 as_warn (_("skipping prefixes on this instruction"));
e0890092 3319
29b0f896
AM		 3320 p = frag_more (1 + size);
3321 *p++ = i.tm.base_opcode;
e0890092 3322
3e02c1cc
AM		 3323 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3324 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3325
3326 /* All jumps handled here are signed, but don't use a signed limit
3327 check for 32 and 16 bit jumps as we want to allow wrap around at
3328 4G and 64k respectively. */
3329 if (size == 1)
3330 fixP->fx_signed = 1;
29b0f896 3331}
e0890092 3332
29b0f896
AM		 3333static void
3334output_interseg_jump ()
3335{
3336 char *p;
3337 int size;
3338 int prefix;
3339 int code16;
252b5132 3340
29b0f896
AM		 3341 code16 = 0;
3342 if (flag_code == CODE_16BIT)
3343 code16 = CODE16;
a217f122 3344
29b0f896
AM		 3345 prefix = 0;
3346 if (i.prefix[DATA_PREFIX] != 0)
3347 {
3348 prefix = 1;
3349 i.prefixes -= 1;
3350 code16 ^= CODE16;
3351 }
3352 if (i.prefix[REX_PREFIX] != 0)
3353 {
3354 prefix++;
3355 i.prefixes -= 1;
3356 }
252b5132 3357
29b0f896
AM		 3358 size = 4;
3359 if (code16)
3360 size = 2;
252b5132 3361
29b0f896
AM		 3362 if (i.prefixes != 0 && !intel_syntax)
3363 as_warn (_("skipping prefixes on this instruction"));
252b5132 3364
29b0f896
AM		 3365 /* 1 opcode; 2 segment; offset */
3366 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3367
29b0f896
AM		 3368 if (i.prefix[DATA_PREFIX] != 0)
3369 *p++ = DATA_PREFIX_OPCODE;
252b5132 3370
29b0f896
AM		 3371 if (i.prefix[REX_PREFIX] != 0)
3372 *p++ = i.prefix[REX_PREFIX];
252b5132 3373
29b0f896
AM		 3374 *p++ = i.tm.base_opcode;
3375 if (i.op[1].imms->X_op == O_constant)
3376 {
3377 offsetT n = i.op[1].imms->X_add_number;
252b5132 3378
29b0f896
AM		 3379 if (size == 2
3380 && !fits_in_unsigned_word (n)
3381 && !fits_in_signed_word (n))
3382 {
3383 as_bad (_("16-bit jump out of range"));
3384 return;
3385 }
3386 md_number_to_chars (p, n, size);
3387 }
3388 else
3389 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3390 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3391 if (i.op[0].imms->X_op != O_constant)
3392 as_bad (_("can't handle non absolute segment in `%s'"),
3393 i.tm.name);
3394 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3395}
a217f122 3396
29b0f896
AM		 3397static void
3398output_insn ()
3399{
2bbd9c25
JJ		 3400 fragS *insn_start_frag;
3401 offsetT insn_start_off;
3402
29b0f896
AM		 3403 /* Tie dwarf2 debug info to the address at the start of the insn.
3404 We can't do this after the insn has been output as the current
3405 frag may have been closed off. eg. by frag_var. */
3406 dwarf2_emit_insn (0);
3407
2bbd9c25
JJ		 3408 insn_start_frag = frag_now;
3409 insn_start_off = frag_now_fix ();
3410
29b0f896
AM		 3411 /* Output jumps. */
3412 if (i.tm.opcode_modifier & Jump)
3413 output_branch ();
3414 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3415 output_jump ();
3416 else if (i.tm.opcode_modifier & JumpInterSegment)
3417 output_interseg_jump ();
3418 else
3419 {
3420 /* Output normal instructions here. */
3421 char *p;
3422 unsigned char *q;
252b5132 3423
bc4bd9ab
MK		 3424 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3425 more higher byte to specify a prefix the instruction
3426 requires. */
3427 if ((i.tm.base_opcode & 0xff0000) != 0)
3428 {
3429 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3430 {
3431 unsigned int prefix;
3432 prefix = (i.tm.base_opcode >> 16) & 0xff;
3433
3434 if (prefix != REPE_PREFIX_OPCODE
3435 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3436 add_prefix (prefix);
3437 }
3438 else
3439 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
0f10071e 3440 }
252b5132 3441
29b0f896
AM		 3442 /* The prefix bytes. */
3443 for (q = i.prefix;
3444 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3445 q++)
3446 {
3447 if (*q)
3448 {
3449 p = frag_more (1);
3450 md_number_to_chars (p, (valueT) *q, 1);
3451 }
3452 }
252b5132 3453
29b0f896
AM		 3454 /* Now the opcode; be careful about word order here! */
3455 if (fits_in_unsigned_byte (i.tm.base_opcode))
3456 {
3457 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3458 }
3459 else
3460 {
bc4bd9ab 3461 p = frag_more (2);
0f10071e 3462
29b0f896
AM		 3463 /* Put out high byte first: can't use md_number_to_chars! */
3464 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3465 *p = i.tm.base_opcode & 0xff;
3466 }
3e73aa7c 3467
29b0f896
AM		 3468 /* Now the modrm byte and sib byte (if present). */
3469 if (i.tm.opcode_modifier & Modrm)
3470 {
3471 p = frag_more (1);
3472 md_number_to_chars (p,
3473 (valueT) (i.rm.regmem << 0
3474 | i.rm.reg << 3
3475 | i.rm.mode << 6),
3476 1);
3477 /* If i.rm.regmem == ESP (4)
3478 && i.rm.mode != (Register mode)
3479 && not 16 bit
3480 ==> need second modrm byte. */
3481 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3482 && i.rm.mode != 3
3483 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3484 {
3485 p = frag_more (1);
3486 md_number_to_chars (p,
3487 (valueT) (i.sib.base << 0
3488 | i.sib.index << 3
3489 | i.sib.scale << 6),
3490 1);
3491 }
3492 }
3e73aa7c 3493
29b0f896 3494 if (i.disp_operands)
2bbd9c25 3495 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3496
29b0f896 3497 if (i.imm_operands)
2bbd9c25 3498 output_imm (insn_start_frag, insn_start_off);
29b0f896 3499 }
252b5132 3500
29b0f896
AM		 3501#ifdef DEBUG386
3502 if (flag_debug)
3503 {
3504 pi (line, &i);
3505 }
3506#endif /* DEBUG386 */
3507}
252b5132 3508
29b0f896 3509static void
2bbd9c25
JJ		 3510output_disp (insn_start_frag, insn_start_off)
3511 fragS *insn_start_frag;
3512 offsetT insn_start_off;
29b0f896
AM		 3513{
3514 char *p;
3515 unsigned int n;
252b5132 3516
29b0f896
AM		 3517 for (n = 0; n < i.operands; n++)
3518 {
3519 if (i.types[n] & Disp)
3520 {
3521 if (i.op[n].disps->X_op == O_constant)
3522 {
3523 int size;
3524 offsetT val;
252b5132 3525
29b0f896
AM		 3526 size = 4;
3527 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3528 {
3529 size = 2;
3530 if (i.types[n] & Disp8)
3531 size = 1;
3532 if (i.types[n] & Disp64)
3533 size = 8;
3534 }
3535 val = offset_in_range (i.op[n].disps->X_add_number,
3536 size);
3537 p = frag_more (size);
3538 md_number_to_chars (p, val, size);
3539 }
3540 else
3541 {
f86103b7 3542 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3543 int size = 4;
3544 int sign = 0;
3545 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3546
3547 /* The PC relative address is computed relative
3548 to the instruction boundary, so in case immediate
3549 fields follows, we need to adjust the value. */
3550 if (pcrel && i.imm_operands)
3551 {
3552 int imm_size = 4;
3553 unsigned int n1;
252b5132 3554
29b0f896
AM		 3555 for (n1 = 0; n1 < i.operands; n1++)
3556 if (i.types[n1] & Imm)
252b5132 3557 {
29b0f896 3558 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3559 {
29b0f896
AM		 3560 imm_size = 2;
3561 if (i.types[n1] & (Imm8 | Imm8S))
3562 imm_size = 1;
3563 if (i.types[n1] & Imm64)
3564 imm_size = 8;
252b5132 3565 }
29b0f896 3566 break;
252b5132 3567 }
29b0f896
AM		 3568 /* We should find the immediate. */
3569 if (n1 == i.operands)
3570 abort ();
3571 i.op[n].disps->X_add_number -= imm_size;
3572 }
520dc8e8 3573
29b0f896
AM		 3574 if (i.types[n] & Disp32S)
3575 sign = 1;
3e73aa7c 3576
29b0f896
AM		 3577 if (i.types[n] & (Disp16 | Disp64))
3578 {
3579 size = 2;
3580 if (i.types[n] & Disp64)
3581 size = 8;
3582 }
520dc8e8 3583
29b0f896 3584 p = frag_more (size);
2bbd9c25 3585 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 3586 if (GOT_symbol
2bbd9c25 3587 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113
JB		 3588 && (((reloc_type == BFD_RELOC_32
3589 || reloc_type == BFD_RELOC_X86_64_32S)
3590 && (i.op[n].disps->X_op == O_symbol
3591 || (i.op[n].disps->X_op == O_add
3592 && ((symbol_get_value_expression
3593 (i.op[n].disps->X_op_symbol)->X_op)
3594 == O_subtract))))
3595 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 3596 {
3597 offsetT add;
3598
3599 if (insn_start_frag == frag_now)
3600 add = (p - frag_now->fr_literal) - insn_start_off;
3601 else
3602 {
3603 fragS *fr;
3604
3605 add = insn_start_frag->fr_fix - insn_start_off;
3606 for (fr = insn_start_frag->fr_next;
3607 fr && fr != frag_now; fr = fr->fr_next)
3608 add += fr->fr_fix;
3609 add += p - frag_now->fr_literal;
3610 }
3611
d6ab8113
JB		 3612 if (flag_code != CODE_64BIT)
3613 reloc_type = BFD_RELOC_386_GOTPC;
3614 else
3615 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25
JJ		 3616 i.op[n].disps->X_add_number += add;
3617 }
062cd5e7 3618 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3619 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3620 }
3621 }
3622 }
3623}
252b5132 3624
29b0f896 3625static void
2bbd9c25
JJ		 3626output_imm (insn_start_frag, insn_start_off)
3627 fragS *insn_start_frag;
3628 offsetT insn_start_off;
29b0f896
AM		 3629{
3630 char *p;
3631 unsigned int n;
252b5132 3632
29b0f896
AM		 3633 for (n = 0; n < i.operands; n++)
3634 {
3635 if (i.types[n] & Imm)
3636 {
3637 if (i.op[n].imms->X_op == O_constant)
3638 {
3639 int size;
3640 offsetT val;
b4cac588 3641
29b0f896
AM		 3642 size = 4;
3643 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3644 {
3645 size = 2;
3646 if (i.types[n] & (Imm8 | Imm8S))
3647 size = 1;
3648 else if (i.types[n] & Imm64)
3649 size = 8;
3650 }
3651 val = offset_in_range (i.op[n].imms->X_add_number,
3652 size);
3653 p = frag_more (size);
3654 md_number_to_chars (p, val, size);
3655 }
3656 else
3657 {
3658 /* Not absolute_section.
3659 Need a 32-bit fixup (don't support 8bit
3660 non-absolute imms). Try to support other
3661 sizes ... */
f86103b7 3662 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3663 int size = 4;
3664 int sign = 0;
3665
3666 if ((i.types[n] & (Imm32S))
a7d61044
JB		 3667 && (i.suffix == QWORD_MNEM_SUFFIX
3668 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 3669 sign = 1;
3670 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3671 {
3672 size = 2;
3673 if (i.types[n] & (Imm8 | Imm8S))
3674 size = 1;
3675 if (i.types[n] & Imm64)
3676 size = 8;
3677 }
520dc8e8 3678
29b0f896
AM		 3679 p = frag_more (size);
3680 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3681
2bbd9c25
JJ		 3682 /* This is tough to explain. We end up with this one if we
3683 * have operands that look like
3684 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3685 * obtain the absolute address of the GOT, and it is strongly
3686 * preferable from a performance point of view to avoid using
3687 * a runtime relocation for this. The actual sequence of
3688 * instructions often look something like:
3689 *
3690 * call .L66
3691 * .L66:
3692 * popl %ebx
3693 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3694 *
3695 * The call and pop essentially return the absolute address
3696 * of the label .L66 and store it in %ebx. The linker itself
3697 * will ultimately change the first operand of the addl so
3698 * that %ebx points to the GOT, but to keep things simple, the
3699 * .o file must have this operand set so that it generates not
3700 * the absolute address of .L66, but the absolute address of
3701 * itself. This allows the linker itself simply treat a GOTPC
3702 * relocation as asking for a pcrel offset to the GOT to be
3703 * added in, and the addend of the relocation is stored in the
3704 * operand field for the instruction itself.
3705 *
3706 * Our job here is to fix the operand so that it would add
3707 * the correct offset so that %ebx would point to itself. The
3708 * thing that is tricky is that .-.L66 will point to the
3709 * beginning of the instruction, so we need to further modify
3710 * the operand so that it will point to itself. There are
3711 * other cases where you have something like:
3712 *
3713 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3714 *
3715 * and here no correction would be required. Internally in
3716 * the assembler we treat operands of this form as not being
3717 * pcrel since the '.' is explicitly mentioned, and I wonder
3718 * whether it would simplify matters to do it this way. Who
3719 * knows. In earlier versions of the PIC patches, the
3720 * pcrel_adjust field was used to store the correction, but
3721 * since the expression is not pcrel, I felt it would be
3722 * confusing to do it this way. */
3723
d6ab8113
JB		 3724 if ((reloc_type == BFD_RELOC_32
3725 || reloc_type == BFD_RELOC_X86_64_32S)
29b0f896
AM		 3726 && GOT_symbol
3727 && GOT_symbol == i.op[n].imms->X_add_symbol
3728 && (i.op[n].imms->X_op == O_symbol
3729 || (i.op[n].imms->X_op == O_add
3730 && ((symbol_get_value_expression
3731 (i.op[n].imms->X_op_symbol)->X_op)
3732 == O_subtract))))
3733 {
2bbd9c25
JJ		 3734 offsetT add;
3735
3736 if (insn_start_frag == frag_now)
3737 add = (p - frag_now->fr_literal) - insn_start_off;
3738 else
3739 {
3740 fragS *fr;
3741
3742 add = insn_start_frag->fr_fix - insn_start_off;
3743 for (fr = insn_start_frag->fr_next;
3744 fr && fr != frag_now; fr = fr->fr_next)
3745 add += fr->fr_fix;
3746 add += p - frag_now->fr_literal;
3747 }
3748
d6ab8113
JB		 3749 if (flag_code != CODE_64BIT)
3750 reloc_type = BFD_RELOC_386_GOTPC;
3751 else
3752 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 3753 i.op[n].imms->X_add_number += add;
29b0f896 3754 }
29b0f896
AM		 3755 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3756 i.op[n].imms, 0, reloc_type);
3757 }
3758 }
3759 }
252b5132
RH		 3760}
3761\f
718ddfc0
JB		 3762#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3763# define lex_got(reloc, adjust, types) NULL
3764#else
f3c180ae
AM		 3765/* Parse operands of the form
3766 <symbol>@GOTOFF+<nnn>
3767 and similar .plt or .got references.
3768
3769 If we find one, set up the correct relocation in RELOC and copy the
3770 input string, minus the `@GOTOFF' into a malloc'd buffer for
3771 parsing by the calling routine. Return this buffer, and if ADJUST
3772 is non-null set it to the length of the string we removed from the
3773 input line. Otherwise return NULL. */
3774static char *
3956db08
JB		 3775lex_got (enum bfd_reloc_code_real *reloc,
3776 int *adjust,
3777 unsigned int *types)
f3c180ae
AM		 3778{
3779 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3780 static const struct {
3781 const char *str;
f86103b7 3782 const enum bfd_reloc_code_real rel[NUM_FLAG_CODE];
3956db08 3783 const unsigned int types64;
f3c180ae 3784 } gotrel[] = {
3956db08
JB		 3785 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
3786 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
3787 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
3788 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
3789 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 }, 0 },
3790 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
3791 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
3792 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3793 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 }, 0 },
3794 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3795 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 }, 0 },
3796 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 }, 0 },
3797 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 3798 };
3799 char *cp;
3800 unsigned int j;
3801
718ddfc0
JB		 3802 if (!IS_ELF)
3803 return NULL;
3804
f3c180ae
AM		 3805 for (cp = input_line_pointer; *cp != '@'; cp++)
3806 if (is_end_of_line[(unsigned char) *cp])
3807 return NULL;
3808
3809 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3810 {
3811 int len;
3812
3813 len = strlen (gotrel[j].str);
28f81592 3814 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3815 {
3816 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3817 {
28f81592
AM		 3818 int first, second;
3819 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3820
3821 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3822 if (adjust)
3823 *adjust = len;
f3c180ae 3824
3956db08
JB		 3825 if (types)
3826 {
3827 if (flag_code != CODE_64BIT)
3828 *types = Imm32|Disp32;
3829 else
3830 *types = gotrel[j].types64;
3831 }
3832
f3c180ae
AM		 3833 if (GOT_symbol == NULL)
3834 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3835
3836 /* Replace the relocation token with ' ', so that
3837 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3838
3839 /* The length of the first part of our input line. */
f3c180ae 3840 first = cp - input_line_pointer;
28f81592
AM		 3841
3842 /* The second part goes from after the reloc token until
3843 (and including) an end_of_line char. Don't use strlen
3844 here as the end_of_line char may not be a NUL. */
3845 past_reloc = cp + 1 + len;
3846 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3847 ;
3848 second = cp - past_reloc;
3849
3850 /* Allocate and copy string. The trailing NUL shouldn't
3851 be necessary, but be safe. */
3852 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3853 memcpy (tmpbuf, input_line_pointer, first);
3854 tmpbuf[first] = ' ';
28f81592
AM		 3855 memcpy (tmpbuf + first + 1, past_reloc, second);
3856 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3857 return tmpbuf;
3858 }
3859
3860 as_bad (_("@%s reloc is not supported in %s bit mode"),
3861 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3862 return NULL;
3863 }
3864 }
3865
3866 /* Might be a symbol version string. Don't as_bad here. */
3867 return NULL;
3868}
3869
3870/* x86_cons_fix_new is called via the expression parsing code when a
3871 reloc is needed. We use this hook to get the correct .got reloc. */
f86103b7 3872static enum bfd_reloc_code_real got_reloc = NO_RELOC;
f3c180ae
AM		 3873
3874void
3875x86_cons_fix_new (frag, off, len, exp)
3876 fragS *frag;
3877 unsigned int off;
3878 unsigned int len;
3879 expressionS *exp;
3880{
3956db08 3881 enum bfd_reloc_code_real r = reloc (len, 0, -1, got_reloc);
f3c180ae
AM		 3882 got_reloc = NO_RELOC;
3883 fix_new_exp (frag, off, len, exp, 0, r);
3884}
3885
3886void
3887x86_cons (exp, size)
3888 expressionS *exp;
3889 int size;
3890{
d6ab8113 3891 if (size == 4 || (flag_code == CODE_64BIT && size == 8))
f3c180ae
AM		 3892 {
3893 /* Handle @GOTOFF and the like in an expression. */
3894 char *save;
3895 char *gotfree_input_line;
3896 int adjust;
3897
3898 save = input_line_pointer;
3956db08 3899 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 3900 if (gotfree_input_line)
3901 input_line_pointer = gotfree_input_line;
3902
3903 expression (exp);
3904
3905 if (gotfree_input_line)
3906 {
3907 /* expression () has merrily parsed up to the end of line,
3908 or a comma - in the wrong buffer. Transfer how far
3909 input_line_pointer has moved to the right buffer. */
3910 input_line_pointer = (save
3911 + (input_line_pointer - gotfree_input_line)
3912 + adjust);
3913 free (gotfree_input_line);
3914 }
3915 }
3916 else
3917 expression (exp);
3918}
3919#endif
3920
6482c264
NC		 3921#ifdef TE_PE
3922
6482c264
NC		 3923void
3924x86_pe_cons_fix_new (frag, off, len, exp)
3925 fragS *frag;
3926 unsigned int off;
3927 unsigned int len;
3928 expressionS *exp;
3929{
3956db08 3930 enum bfd_reloc_code_real r = reloc (len, 0, -1, NO_RELOC);
6482c264
NC		 3931
3932 if (exp->X_op == O_secrel)
3933 {
3934 exp->X_op = O_symbol;
3935 r = BFD_RELOC_32_SECREL;
3936 }
3937
3938 fix_new_exp (frag, off, len, exp, 0, r);
3939}
3940
3941static void
3942pe_directive_secrel (dummy)
3943 int dummy ATTRIBUTE_UNUSED;
3944{
3945 expressionS exp;
3946
3947 do
3948 {
3949 expression (&exp);
3950 if (exp.X_op == O_symbol)
3951 exp.X_op = O_secrel;
3952
3953 emit_expr (&exp, 4);
3954 }
3955 while (*input_line_pointer++ == ',');
3956
3957 input_line_pointer--;
3958 demand_empty_rest_of_line ();
3959}
3960
3961#endif
3962
252b5132
RH		 3963static int i386_immediate PARAMS ((char *));
3964
3965static int
3966i386_immediate (imm_start)
3967 char *imm_start;
3968{
3969 char *save_input_line_pointer;
f3c180ae 3970 char *gotfree_input_line;
252b5132 3971 segT exp_seg = 0;
47926f60 3972 expressionS *exp;
3956db08 3973 unsigned int types = ~0U;
252b5132
RH		 3974
3975 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3976 {
d0b47220 3977 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3978 return 0;
3979 }
3980
3981 exp = &im_expressions[i.imm_operands++];
520dc8e8 3982 i.op[this_operand].imms = exp;
252b5132
RH		 3983
3984 if (is_space_char (*imm_start))
3985 ++imm_start;
3986
3987 save_input_line_pointer = input_line_pointer;
3988 input_line_pointer = imm_start;
3989
3956db08 3990 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 3991 if (gotfree_input_line)
3992 input_line_pointer = gotfree_input_line;
252b5132
RH		 3993
3994 exp_seg = expression (exp);
3995
83183c0c 3996 SKIP_WHITESPACE ();
252b5132 3997 if (*input_line_pointer)
f3c180ae 3998 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3999
4000 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4001 if (gotfree_input_line)
4002 free (gotfree_input_line);
252b5132 4003
2daf4fd8 4004 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4005 {
47926f60 4006 /* Missing or bad expr becomes absolute 0. */
d0b47220 4007 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4008 imm_start);
252b5132
RH		 4009 exp->X_op = O_constant;
4010 exp->X_add_number = 0;
4011 exp->X_add_symbol = (symbolS *) 0;
4012 exp->X_op_symbol = (symbolS *) 0;
252b5132 4013 }
3e73aa7c 4014 else if (exp->X_op == O_constant)
252b5132 4015 {
47926f60 4016 /* Size it properly later. */
3e73aa7c
JH		 4017 i.types[this_operand] |= Imm64;
4018 /* If BFD64, sign extend val. */
4019 if (!use_rela_relocations)
4020 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4021 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4022 }
4c63da97 4023#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4024 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4025 && exp_seg != absolute_section
47926f60 4026 && exp_seg != text_section
24eab124
AM		 4027 && exp_seg != data_section
4028 && exp_seg != bss_section
4029 && exp_seg != undefined_section
f86103b7 4030 && !bfd_is_com_section (exp_seg))
252b5132 4031 {
d0b47220 4032 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4033 return 0;
4034 }
4035#endif
4036 else
4037 {
4038 /* This is an address. The size of the address will be
24eab124 4039 determined later, depending on destination register,
3e73aa7c
JH		 4040 suffix, or the default for the section. */
4041 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4042 i.types[this_operand] &= types;
252b5132
RH		 4043 }
4044
4045 return 1;
4046}
4047
551c1ca1 4048static char *i386_scale PARAMS ((char *));
252b5132 4049
551c1ca1 4050static char *
252b5132
RH		 4051i386_scale (scale)
4052 char *scale;
4053{
551c1ca1
AM		 4054 offsetT val;
4055 char *save = input_line_pointer;
252b5132 4056
551c1ca1
AM		 4057 input_line_pointer = scale;
4058 val = get_absolute_expression ();
4059
4060 switch (val)
252b5132 4061 {
551c1ca1 4062 case 1:
252b5132
RH		 4063 i.log2_scale_factor = 0;
4064 break;
551c1ca1 4065 case 2:
252b5132
RH		 4066 i.log2_scale_factor = 1;
4067 break;
551c1ca1 4068 case 4:
252b5132
RH		 4069 i.log2_scale_factor = 2;
4070 break;
551c1ca1 4071 case 8:
252b5132
RH		 4072 i.log2_scale_factor = 3;
4073 break;
4074 default:
a724f0f4
JB		 4075 {
4076 char sep = *input_line_pointer;
4077
4078 *input_line_pointer = '\0';
4079 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4080 scale);
4081 *input_line_pointer = sep;
4082 input_line_pointer = save;
4083 return NULL;
4084 }
252b5132 4085 }
29b0f896 4086 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4087 {
4088 as_warn (_("scale factor of %d without an index register"),
24eab124 4089 1 << i.log2_scale_factor);
252b5132
RH		 4090#if SCALE1_WHEN_NO_INDEX
4091 i.log2_scale_factor = 0;
4092#endif
4093 }
551c1ca1
AM		 4094 scale = input_line_pointer;
4095 input_line_pointer = save;
4096 return scale;
252b5132
RH		 4097}
4098
4099static int i386_displacement PARAMS ((char *, char *));
4100
4101static int
4102i386_displacement (disp_start, disp_end)
4103 char *disp_start;
4104 char *disp_end;
4105{
29b0f896 4106 expressionS *exp;
252b5132
RH		 4107 segT exp_seg = 0;
4108 char *save_input_line_pointer;
f3c180ae 4109 char *gotfree_input_line;
252b5132 4110 int bigdisp = Disp32;
3956db08 4111 unsigned int types = Disp;
252b5132 4112
3e73aa7c 4113 if (flag_code == CODE_64BIT)
7ecd2f8b 4114 {
29b0f896 4115 if (i.prefix[ADDR_PREFIX] == 0)
3956db08 4116 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b
JH		 4117 }
4118 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4119 bigdisp = Disp16;
252b5132
RH		 4120 i.types[this_operand] |= bigdisp;
4121
4122 exp = &disp_expressions[i.disp_operands];
520dc8e8 4123 i.op[this_operand].disps = exp;
252b5132
RH		 4124 i.disp_operands++;
4125 save_input_line_pointer = input_line_pointer;
4126 input_line_pointer = disp_start;
4127 END_STRING_AND_SAVE (disp_end);
4128
4129#ifndef GCC_ASM_O_HACK
4130#define GCC_ASM_O_HACK 0
4131#endif
4132#if GCC_ASM_O_HACK
4133 END_STRING_AND_SAVE (disp_end + 1);
4134 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4135 && displacement_string_end[-1] == '+')
252b5132
RH		 4136 {
4137 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4138 constraint within gcc asm statements.
4139 For instance:
4140
4141 #define _set_tssldt_desc(n,addr,limit,type) \
4142 __asm__ __volatile__ ( \
4143 "movw %w2,%0\n\t" \
4144 "movw %w1,2+%0\n\t" \
4145 "rorl $16,%1\n\t" \
4146 "movb %b1,4+%0\n\t" \
4147 "movb %4,5+%0\n\t" \
4148 "movb $0,6+%0\n\t" \
4149 "movb %h1,7+%0\n\t" \
4150 "rorl $16,%1" \
4151 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4152
4153 This works great except that the output assembler ends
4154 up looking a bit weird if it turns out that there is
4155 no offset. You end up producing code that looks like:
4156
4157 #APP
4158 movw $235,(%eax)
4159 movw %dx,2+(%eax)
4160 rorl $16,%edx
4161 movb %dl,4+(%eax)
4162 movb $137,5+(%eax)
4163 movb $0,6+(%eax)
4164 movb %dh,7+(%eax)
4165 rorl $16,%edx
4166 #NO_APP
4167
47926f60 4168 So here we provide the missing zero. */
24eab124
AM		 4169
4170 *displacement_string_end = '0';
252b5132
RH		 4171 }
4172#endif
3956db08 4173 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4174 if (gotfree_input_line)
4175 input_line_pointer = gotfree_input_line;
252b5132 4176
24eab124 4177 exp_seg = expression (exp);
252b5132 4178
636c26b0
AM		 4179 SKIP_WHITESPACE ();
4180 if (*input_line_pointer)
4181 as_bad (_("junk `%s' after expression"), input_line_pointer);
4182#if GCC_ASM_O_HACK
4183 RESTORE_END_STRING (disp_end + 1);
4184#endif
4185 RESTORE_END_STRING (disp_end);
4186 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4187 if (gotfree_input_line)
4188 free (gotfree_input_line);
636c26b0 4189
24eab124
AM		 4190 /* We do this to make sure that the section symbol is in
4191 the symbol table. We will ultimately change the relocation
47926f60 4192 to be relative to the beginning of the section. */
1ae12ab7 4193 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4194 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4195 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4196 {
636c26b0
AM		 4197 if (exp->X_op != O_symbol)
4198 {
4199 as_bad (_("bad expression used with @%s"),
4200 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4201 ? "GOTPCREL"
4202 : "GOTOFF"));
4203 return 0;
4204 }
4205
e5cb08ac 4206 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4207 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4208 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4209 exp->X_op = O_subtract;
4210 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4211 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4212 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4213 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4214 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4215 else
29b0f896 4216 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4217 }
252b5132 4218
2daf4fd8
AM		 4219 if (exp->X_op == O_absent || exp->X_op == O_big)
4220 {
47926f60 4221 /* Missing or bad expr becomes absolute 0. */
d0b47220 4222 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4223 disp_start);
4224 exp->X_op = O_constant;
4225 exp->X_add_number = 0;
4226 exp->X_add_symbol = (symbolS *) 0;
4227 exp->X_op_symbol = (symbolS *) 0;
4228 }
4229
4c63da97 4230#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4231 if (exp->X_op != O_constant
45288df1 4232 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4233 && exp_seg != absolute_section
45288df1
AM		 4234 && exp_seg != text_section
4235 && exp_seg != data_section
4236 && exp_seg != bss_section
31312f95 4237 && exp_seg != undefined_section
f86103b7 4238 && !bfd_is_com_section (exp_seg))
24eab124 4239 {
d0b47220 4240 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4241 return 0;
4242 }
252b5132 4243#endif
3956db08
JB		 4244
4245 if (!(i.types[this_operand] & ~Disp))
4246 i.types[this_operand] &= types;
4247
252b5132
RH		 4248 return 1;
4249}
4250
e5cb08ac 4251static int i386_index_check PARAMS ((const char *));
252b5132 4252
eecb386c 4253/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4254 Return 1 on success, 0 on a failure. */
4255
252b5132 4256static int
eecb386c
AM		 4257i386_index_check (operand_string)
4258 const char *operand_string;
252b5132 4259{
3e73aa7c 4260 int ok;
24eab124 4261#if INFER_ADDR_PREFIX
eecb386c
AM		 4262 int fudged = 0;
4263
24eab124
AM		 4264 tryprefix:
4265#endif
3e73aa7c 4266 ok = 1;
30123838
JB		 4267 if ((current_templates->start->cpu_flags & CpuSVME)
4268 && current_templates->end[-1].operand_types[0] == AnyMem)
4269 {
4270 /* Memory operands of SVME insns are special in that they only allow
4271 rAX as their memory address and ignore any segment override. */
4272 unsigned RegXX;
4273
4274 /* SKINIT is even more restrictive: it always requires EAX. */
4275 if (strcmp (current_templates->start->name, "skinit") == 0)
4276 RegXX = Reg32;
4277 else if (flag_code == CODE_64BIT)
4278 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4279 else
4280 RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4281 ? Reg16
4282 : Reg32;
4283 if (!i.base_reg
4284 || !(i.base_reg->reg_type & Acc)
4285 || !(i.base_reg->reg_type & RegXX)
4286 || i.index_reg
4287 || (i.types[0] & Disp))
4288 ok = 0;
4289 }
4290 else if (flag_code == CODE_64BIT)
20f0a1fc
NC		 4291 {
4292 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4293
4294 if ((i.base_reg
4295 && ((i.base_reg->reg_type & RegXX) == 0)
4296 && (i.base_reg->reg_type != BaseIndex
4297 || i.index_reg))
4298 || (i.index_reg
4299 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4300 != (RegXX | BaseIndex))))
4301 ok = 0;
3e73aa7c
JH		 4302 }
4303 else
4304 {
4305 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4306 {
4307 /* 16bit checks. */
4308 if ((i.base_reg
29b0f896
AM		 4309 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4310 != (Reg16 | BaseIndex)))
3e73aa7c 4311 || (i.index_reg
29b0f896
AM		 4312 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4313 != (Reg16 | BaseIndex))
4314 || !(i.base_reg
4315 && i.base_reg->reg_num < 6
4316 && i.index_reg->reg_num >= 6
4317 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4318 ok = 0;
4319 }
4320 else
e5cb08ac 4321 {
3e73aa7c
JH		 4322 /* 32bit checks. */
4323 if ((i.base_reg
4324 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4325 || (i.index_reg
29b0f896
AM		 4326 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4327 != (Reg32 | BaseIndex))))
e5cb08ac 4328 ok = 0;
3e73aa7c
JH		 4329 }
4330 }
4331 if (!ok)
24eab124
AM		 4332 {
4333#if INFER_ADDR_PREFIX
20f0a1fc 4334 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4335 {
4336 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4337 i.prefixes += 1;
b23bac36
AM		 4338 /* Change the size of any displacement too. At most one of
4339 Disp16 or Disp32 is set.
4340 FIXME. There doesn't seem to be any real need for separate
4341 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4342 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4343 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
29b0f896 4344 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4345 fudged = 1;
24eab124
AM		 4346 goto tryprefix;
4347 }
eecb386c
AM		 4348 if (fudged)
4349 as_bad (_("`%s' is not a valid base/index expression"),
4350 operand_string);
4351 else
c388dee8 4352#endif
eecb386c
AM		 4353 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4354 operand_string,
3e73aa7c 4355 flag_code_names[flag_code]);
24eab124 4356 }
20f0a1fc 4357 return ok;
24eab124 4358}
252b5132 4359
252b5132 4360/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4361 on error. */
252b5132 4362
252b5132
RH		 4363static int
4364i386_operand (operand_string)
4365 char *operand_string;
4366{
af6bdddf
AM		 4367 const reg_entry *r;
4368 char *end_op;
24eab124 4369 char *op_string = operand_string;
252b5132 4370
24eab124 4371 if (is_space_char (*op_string))
252b5132
RH		 4372 ++op_string;
4373
24eab124 4374 /* We check for an absolute prefix (differentiating,
47926f60 4375 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4376 if (*op_string == ABSOLUTE_PREFIX)
4377 {
4378 ++op_string;
4379 if (is_space_char (*op_string))
4380 ++op_string;
4381 i.types[this_operand] |= JumpAbsolute;
4382 }
252b5132 4383
47926f60 4384 /* Check if operand is a register. */
af6bdddf
AM		 4385 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4386 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4387 {
24eab124
AM		 4388 /* Check for a segment override by searching for ':' after a
4389 segment register. */
4390 op_string = end_op;
4391 if (is_space_char (*op_string))
4392 ++op_string;
4393 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4394 {
4395 switch (r->reg_num)
4396 {
4397 case 0:
4398 i.seg[i.mem_operands] = &es;
4399 break;
4400 case 1:
4401 i.seg[i.mem_operands] = &cs;
4402 break;
4403 case 2:
4404 i.seg[i.mem_operands] = &ss;
4405 break;
4406 case 3:
4407 i.seg[i.mem_operands] = &ds;
4408 break;
4409 case 4:
4410 i.seg[i.mem_operands] = &fs;
4411 break;
4412 case 5:
4413 i.seg[i.mem_operands] = &gs;
4414 break;
4415 }
252b5132 4416
24eab124 4417 /* Skip the ':' and whitespace. */
252b5132
RH		 4418 ++op_string;
4419 if (is_space_char (*op_string))
24eab124 4420 ++op_string;
252b5132 4421
24eab124
AM		 4422 if (!is_digit_char (*op_string)
4423 && !is_identifier_char (*op_string)
4424 && *op_string != '('
4425 && *op_string != ABSOLUTE_PREFIX)
4426 {
4427 as_bad (_("bad memory operand `%s'"), op_string);
4428 return 0;
4429 }
47926f60 4430 /* Handle case of %es:*foo. */
24eab124
AM		 4431 if (*op_string == ABSOLUTE_PREFIX)
4432 {
4433 ++op_string;
4434 if (is_space_char (*op_string))
4435 ++op_string;
4436 i.types[this_operand] |= JumpAbsolute;
4437 }
4438 goto do_memory_reference;
4439 }
4440 if (*op_string)
4441 {
d0b47220 4442 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4443 return 0;
4444 }
4445 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4446 i.op[this_operand].regs = r;
24eab124
AM		 4447 i.reg_operands++;
4448 }
af6bdddf
AM		 4449 else if (*op_string == REGISTER_PREFIX)
4450 {
4451 as_bad (_("bad register name `%s'"), op_string);
4452 return 0;
4453 }
24eab124 4454 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4455 {
24eab124
AM		 4456 ++op_string;
4457 if (i.types[this_operand] & JumpAbsolute)
4458 {
d0b47220 4459 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4460 return 0;
4461 }
4462 if (!i386_immediate (op_string))
4463 return 0;
4464 }
4465 else if (is_digit_char (*op_string)
4466 || is_identifier_char (*op_string)
e5cb08ac 4467 || *op_string == '(')
24eab124 4468 {
47926f60 4469 /* This is a memory reference of some sort. */
af6bdddf 4470 char *base_string;
252b5132 4471
47926f60 4472 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4473 char *displacement_string_start;
4474 char *displacement_string_end;
252b5132 4475
24eab124 4476 do_memory_reference:
24eab124
AM		 4477 if ((i.mem_operands == 1
4478 && (current_templates->start->opcode_modifier & IsString) == 0)
4479 || i.mem_operands == 2)
4480 {
4481 as_bad (_("too many memory references for `%s'"),
4482 current_templates->start->name);
4483 return 0;
4484 }
252b5132 4485
24eab124
AM		 4486 /* Check for base index form. We detect the base index form by
4487 looking for an ')' at the end of the operand, searching
4488 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4489 after the '('. */
af6bdddf 4490 base_string = op_string + strlen (op_string);
c3332e24 4491
af6bdddf
AM		 4492 --base_string;
4493 if (is_space_char (*base_string))
4494 --base_string;
252b5132 4495
47926f60 4496 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4497 displacement_string_start = op_string;
4498 displacement_string_end = base_string + 1;
252b5132 4499
24eab124
AM		 4500 if (*base_string == ')')
4501 {
af6bdddf 4502 char *temp_string;
24eab124
AM		 4503 unsigned int parens_balanced = 1;
4504 /* We've already checked that the number of left & right ()'s are
47926f60 4505 equal, so this loop will not be infinite. */
24eab124
AM		 4506 do
4507 {
4508 base_string--;
4509 if (*base_string == ')')
4510 parens_balanced++;
4511 if (*base_string == '(')
4512 parens_balanced--;
4513 }
4514 while (parens_balanced);
c3332e24 4515
af6bdddf 4516 temp_string = base_string;
c3332e24 4517
24eab124 4518 /* Skip past '(' and whitespace. */
252b5132
RH		 4519 ++base_string;
4520 if (is_space_char (*base_string))
24eab124 4521 ++base_string;
252b5132 4522
af6bdddf
AM		 4523 if (*base_string == ','
4524 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4525 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4526 {
af6bdddf 4527 displacement_string_end = temp_string;
252b5132 4528
af6bdddf 4529 i.types[this_operand] |= BaseIndex;
252b5132 4530
af6bdddf 4531 if (i.base_reg)
24eab124 4532 {
24eab124
AM		 4533 base_string = end_op;
4534 if (is_space_char (*base_string))
4535 ++base_string;
af6bdddf
AM		 4536 }
4537
4538 /* There may be an index reg or scale factor here. */
4539 if (*base_string == ',')
4540 {
4541 ++base_string;
4542 if (is_space_char (*base_string))
4543 ++base_string;
4544
4545 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4546 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4547 {
af6bdddf 4548 base_string = end_op;
24eab124
AM		 4549 if (is_space_char (*base_string))
4550 ++base_string;
af6bdddf
AM		 4551 if (*base_string == ',')
4552 {
4553 ++base_string;
4554 if (is_space_char (*base_string))
4555 ++base_string;
4556 }
e5cb08ac 4557 else if (*base_string != ')')
af6bdddf
AM		 4558 {
4559 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4560 operand_string);
4561 return 0;
4562 }
24eab124 4563 }
af6bdddf 4564 else if (*base_string == REGISTER_PREFIX)
24eab124 4565 {
af6bdddf 4566 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4567 return 0;
4568 }
252b5132 4569
47926f60 4570 /* Check for scale factor. */
551c1ca1 4571 if (*base_string != ')')
af6bdddf 4572 {
551c1ca1
AM		 4573 char *end_scale = i386_scale (base_string);
4574
4575 if (!end_scale)
af6bdddf 4576 return 0;
24eab124 4577
551c1ca1 4578 base_string = end_scale;
af6bdddf
AM		 4579 if (is_space_char (*base_string))
4580 ++base_string;
4581 if (*base_string != ')')
4582 {
4583 as_bad (_("expecting `)' after scale factor in `%s'"),
4584 operand_string);
4585 return 0;
4586 }
4587 }
4588 else if (!i.index_reg)
24eab124 4589 {
af6bdddf
AM		 4590 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4591 *base_string);
24eab124
AM		 4592 return 0;
4593 }
4594 }
af6bdddf 4595 else if (*base_string != ')')
24eab124 4596 {
af6bdddf
AM		 4597 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4598 operand_string);
24eab124
AM		 4599 return 0;
4600 }
c3332e24 4601 }
af6bdddf 4602 else if (*base_string == REGISTER_PREFIX)
c3332e24 4603 {
af6bdddf 4604 as_bad (_("bad register name `%s'"), base_string);
24eab124 4605 return 0;
c3332e24 4606 }
24eab124
AM		 4607 }
4608
4609 /* If there's an expression beginning the operand, parse it,
4610 assuming displacement_string_start and
4611 displacement_string_end are meaningful. */
4612 if (displacement_string_start != displacement_string_end)
4613 {
4614 if (!i386_displacement (displacement_string_start,
4615 displacement_string_end))
4616 return 0;
4617 }
4618
4619 /* Special case for (%dx) while doing input/output op. */
4620 if (i.base_reg
4621 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4622 && i.index_reg == 0
4623 && i.log2_scale_factor == 0
4624 && i.seg[i.mem_operands] == 0
4625 && (i.types[this_operand] & Disp) == 0)
4626 {
4627 i.types[this_operand] = InOutPortReg;
4628 return 1;
4629 }
4630
eecb386c
AM		 4631 if (i386_index_check (operand_string) == 0)
4632 return 0;
24eab124
AM		 4633 i.mem_operands++;
4634 }
4635 else
ce8a8b2f
AM		 4636 {
4637 /* It's not a memory operand; argh! */
24eab124
AM		 4638 as_bad (_("invalid char %s beginning operand %d `%s'"),
4639 output_invalid (*op_string),
4640 this_operand + 1,
4641 op_string);
4642 return 0;
4643 }
47926f60 4644 return 1; /* Normal return. */
252b5132
RH		 4645}
4646\f
ee7fcc42
AM		 4647/* md_estimate_size_before_relax()
4648
4649 Called just before relax() for rs_machine_dependent frags. The x86
4650 assembler uses these frags to handle variable size jump
4651 instructions.
4652
4653 Any symbol that is now undefined will not become defined.
4654 Return the correct fr_subtype in the frag.
4655 Return the initial "guess for variable size of frag" to caller.
4656 The guess is actually the growth beyond the fixed part. Whatever
4657 we do to grow the fixed or variable part contributes to our
4658 returned value. */
4659
252b5132
RH		 4660int
4661md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4662 fragS *fragP;
4663 segT segment;
252b5132 4664{
252b5132 4665 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4666 check for un-relaxable symbols. On an ELF system, we can't relax
4667 an externally visible symbol, because it may be overridden by a
4668 shared library. */
4669 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4670#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4671 || (IS_ELF
31312f95
AM		 4672 && (S_IS_EXTERNAL (fragP->fr_symbol)
4673 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4674#endif
4675 )
252b5132 4676 {
b98ef147
AM		 4677 /* Symbol is undefined in this segment, or we need to keep a
4678 reloc so that weak symbols can be overridden. */
4679 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4680 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4681 unsigned char *opcode;
4682 int old_fr_fix;
f6af82bd 4683
ee7fcc42
AM		 4684 if (fragP->fr_var != NO_RELOC)
4685 reloc_type = fragP->fr_var;
b98ef147 4686 else if (size == 2)
f6af82bd
AM		 4687 reloc_type = BFD_RELOC_16_PCREL;
4688 else
4689 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4690
ee7fcc42
AM		 4691 old_fr_fix = fragP->fr_fix;
4692 opcode = (unsigned char *) fragP->fr_opcode;
4693
fddf5b5b 4694 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4695 {
fddf5b5b
AM		 4696 case UNCOND_JUMP:
4697 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4698 opcode[0] = 0xe9;
252b5132 4699 fragP->fr_fix += size;
062cd5e7
AS		 4700 fix_new (fragP, old_fr_fix, size,
4701 fragP->fr_symbol,
4702 fragP->fr_offset, 1,
4703 reloc_type);
252b5132
RH		 4704 break;
4705
fddf5b5b 4706 case COND_JUMP86:
412167cb
AM		 4707 if (size == 2
4708 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4709 {
4710 /* Negate the condition, and branch past an
4711 unconditional jump. */
4712 opcode[0] ^= 1;
4713 opcode[1] = 3;
4714 /* Insert an unconditional jump. */
4715 opcode[2] = 0xe9;
4716 /* We added two extra opcode bytes, and have a two byte
4717 offset. */
4718 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4719 fix_new (fragP, old_fr_fix + 2, 2,
4720 fragP->fr_symbol,
4721 fragP->fr_offset, 1,
4722 reloc_type);
fddf5b5b
AM		 4723 break;
4724 }
4725 /* Fall through. */
4726
4727 case COND_JUMP:
412167cb
AM		 4728 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4729 {
3e02c1cc
AM		 4730 fixS *fixP;
4731
412167cb 4732 fragP->fr_fix += 1;
3e02c1cc
AM		 4733 fixP = fix_new (fragP, old_fr_fix, 1,
4734 fragP->fr_symbol,
4735 fragP->fr_offset, 1,
4736 BFD_RELOC_8_PCREL);
4737 fixP->fx_signed = 1;
412167cb
AM		 4738 break;
4739 }
93c2a809 4740
24eab124 4741 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4742 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4743 opcode[1] = opcode[0] + 0x10;
f6af82bd 4744 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4745 /* We've added an opcode byte. */
4746 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4747 fix_new (fragP, old_fr_fix + 1, size,
4748 fragP->fr_symbol,
4749 fragP->fr_offset, 1,
4750 reloc_type);
252b5132 4751 break;
fddf5b5b
AM		 4752
4753 default:
4754 BAD_CASE (fragP->fr_subtype);
4755 break;
252b5132
RH		 4756 }
4757 frag_wane (fragP);
ee7fcc42 4758 return fragP->fr_fix - old_fr_fix;
252b5132 4759 }
93c2a809 4760
93c2a809
AM		 4761 /* Guess size depending on current relax state. Initially the relax
4762 state will correspond to a short jump and we return 1, because
4763 the variable part of the frag (the branch offset) is one byte
4764 long. However, we can relax a section more than once and in that
4765 case we must either set fr_subtype back to the unrelaxed state,
4766 or return the value for the appropriate branch. */
4767 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4768}
4769
47926f60
KH		 4770/* Called after relax() is finished.
4771
4772 In: Address of frag.
4773 fr_type == rs_machine_dependent.
4774 fr_subtype is what the address relaxed to.
4775
4776 Out: Any fixSs and constants are set up.
4777 Caller will turn frag into a ".space 0". */
4778
252b5132
RH		 4779void
4780md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4781 bfd *abfd ATTRIBUTE_UNUSED;
4782 segT sec ATTRIBUTE_UNUSED;
29b0f896 4783 fragS *fragP;
252b5132 4784{
29b0f896 4785 unsigned char *opcode;
252b5132 4786 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4787 offsetT target_address;
4788 offsetT opcode_address;
252b5132 4789 unsigned int extension = 0;
847f7ad4 4790 offsetT displacement_from_opcode_start;
252b5132
RH		 4791
4792 opcode = (unsigned char *) fragP->fr_opcode;
4793
47926f60 4794 /* Address we want to reach in file space. */
252b5132 4795 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4796
47926f60 4797 /* Address opcode resides at in file space. */
252b5132
RH		 4798 opcode_address = fragP->fr_address + fragP->fr_fix;
4799
47926f60 4800 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4801 displacement_from_opcode_start = target_address - opcode_address;
4802
fddf5b5b 4803 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4804 {
47926f60
KH		 4805 /* Don't have to change opcode. */
4806 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4807 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4808 }
4809 else
4810 {
4811 if (no_cond_jump_promotion
4812 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4813 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4814
fddf5b5b
AM		 4815 switch (fragP->fr_subtype)
4816 {
4817 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4818 extension = 4; /* 1 opcode + 4 displacement */
4819 opcode[0] = 0xe9;
4820 where_to_put_displacement = &opcode[1];
4821 break;
252b5132 4822
fddf5b5b
AM		 4823 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4824 extension = 2; /* 1 opcode + 2 displacement */
4825 opcode[0] = 0xe9;
4826 where_to_put_displacement = &opcode[1];
4827 break;
252b5132 4828
fddf5b5b
AM		 4829 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4830 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4831 extension = 5; /* 2 opcode + 4 displacement */
4832 opcode[1] = opcode[0] + 0x10;
4833 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4834 where_to_put_displacement = &opcode[2];
4835 break;
252b5132 4836
fddf5b5b
AM		 4837 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4838 extension = 3; /* 2 opcode + 2 displacement */
4839 opcode[1] = opcode[0] + 0x10;
4840 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4841 where_to_put_displacement = &opcode[2];
4842 break;
252b5132 4843
fddf5b5b
AM		 4844 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4845 extension = 4;
4846 opcode[0] ^= 1;
4847 opcode[1] = 3;
4848 opcode[2] = 0xe9;
4849 where_to_put_displacement = &opcode[3];
4850 break;
4851
4852 default:
4853 BAD_CASE (fragP->fr_subtype);
4854 break;
4855 }
252b5132 4856 }
fddf5b5b 4857
47926f60 4858 /* Now put displacement after opcode. */
252b5132
RH		 4859 md_number_to_chars ((char *) where_to_put_displacement,
4860 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4861 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4862 fragP->fr_fix += extension;
4863}
4864\f
47926f60
KH		 4865/* Size of byte displacement jmp. */
4866int md_short_jump_size = 2;
4867
4868/* Size of dword displacement jmp. */
4869int md_long_jump_size = 5;
252b5132 4870
47926f60
KH		 4871/* Size of relocation record. */
4872const int md_reloc_size = 8;
252b5132
RH		 4873
4874void
4875md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4876 char *ptr;
4877 addressT from_addr, to_addr;
ab9da554
ILT		 4878 fragS *frag ATTRIBUTE_UNUSED;
4879 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4880{
847f7ad4 4881 offsetT offset;
252b5132
RH		 4882
4883 offset = to_addr - (from_addr + 2);
47926f60
KH		 4884 /* Opcode for byte-disp jump. */
4885 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4886 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4887}
4888
4889void
4890md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4891 char *ptr;
4892 addressT from_addr, to_addr;
a38cf1db
AM		 4893 fragS *frag ATTRIBUTE_UNUSED;
4894 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4895{
847f7ad4 4896 offsetT offset;
252b5132 4897
a38cf1db
AM		 4898 offset = to_addr - (from_addr + 5);
4899 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4900 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4901}
4902\f
4903/* Apply a fixup (fixS) to segment data, once it has been determined
4904 by our caller that we have all the info we need to fix it up.
4905
4906 On the 386, immediates, displacements, and data pointers are all in
4907 the same (little-endian) format, so we don't need to care about which
4908 we are handling. */
4909
94f592af 4910void
55cf6793 4911md_apply_fix (fixP, valP, seg)
47926f60
KH		 4912 /* The fix we're to put in. */
4913 fixS *fixP;
47926f60 4914 /* Pointer to the value of the bits. */
c6682705 4915 valueT *valP;
47926f60
KH		 4916 /* Segment fix is from. */
4917 segT seg ATTRIBUTE_UNUSED;
252b5132 4918{
94f592af 4919 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4920 valueT value = *valP;
252b5132 4921
f86103b7 4922#if !defined (TE_Mach)
93382f6d
AM		 4923 if (fixP->fx_pcrel)
4924 {
4925 switch (fixP->fx_r_type)
4926 {
5865bb77
ILT		 4927 default:
4928 break;
4929
d6ab8113
JB		 4930 case BFD_RELOC_64:
4931 fixP->fx_r_type = BFD_RELOC_64_PCREL;
4932 break;
93382f6d 4933 case BFD_RELOC_32:
ae8887b5 4934 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 4935 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4936 break;
4937 case BFD_RELOC_16:
4938 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4939 break;
4940 case BFD_RELOC_8:
4941 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4942 break;
4943 }
4944 }
252b5132 4945
a161fe53 4946 if (fixP->fx_addsy != NULL
31312f95 4947 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 4948 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 4949 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4950 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4951 && !use_rela_relocations)
252b5132 4952 {
31312f95
AM		 4953 /* This is a hack. There should be a better way to handle this.
4954 This covers for the fact that bfd_install_relocation will
4955 subtract the current location (for partial_inplace, PC relative
4956 relocations); see more below. */
252b5132 4957#ifndef OBJ_AOUT
718ddfc0 4958 if (IS_ELF
252b5132
RH		 4959#ifdef TE_PE
4960 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4961#endif
4962 )
4963 value += fixP->fx_where + fixP->fx_frag->fr_address;
4964#endif
4965#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4966 if (IS_ELF)
252b5132 4967 {
6539b54b 4968 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 4969
6539b54b 4970 if ((sym_seg == seg
2f66722d 4971 || (symbol_section_p (fixP->fx_addsy)
6539b54b 4972 && sym_seg != absolute_section))
ae6063d4 4973 && !generic_force_reloc (fixP))
2f66722d
AM		 4974 {
4975 /* Yes, we add the values in twice. This is because
6539b54b
AM		 4976 bfd_install_relocation subtracts them out again. I think
4977 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 4978 it. FIXME. */
4979 value += fixP->fx_where + fixP->fx_frag->fr_address;
4980 }
252b5132
RH		 4981 }
4982#endif
4983#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 4984 /* For some reason, the PE format does not store a
4985 section address offset for a PC relative symbol. */
4986 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
4987#if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4988 || S_IS_WEAK (fixP->fx_addsy)
4989#endif
4990 )
252b5132
RH		 4991 value += md_pcrel_from (fixP);
4992#endif
4993 }
4994
4995 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 4996 and we must not disappoint it. */
252b5132 4997#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4998 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 4999 switch (fixP->fx_r_type)
5000 {
5001 case BFD_RELOC_386_PLT32:
3e73aa7c 5002 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5003 /* Make the jump instruction point to the address of the operand. At
5004 runtime we merely add the offset to the actual PLT entry. */
5005 value = -4;
5006 break;
31312f95 5007
13ae64f3
JJ		 5008 case BFD_RELOC_386_TLS_GD:
5009 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5010 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5011 case BFD_RELOC_386_TLS_IE:
5012 case BFD_RELOC_386_TLS_GOTIE:
bffbf940
JJ		 5013 case BFD_RELOC_X86_64_TLSGD:
5014 case BFD_RELOC_X86_64_TLSLD:
5015 case BFD_RELOC_X86_64_GOTTPOFF:
00f7efb6
JJ		 5016 value = 0; /* Fully resolved at runtime. No addend. */
5017 /* Fallthrough */
5018 case BFD_RELOC_386_TLS_LE:
5019 case BFD_RELOC_386_TLS_LDO_32:
5020 case BFD_RELOC_386_TLS_LE_32:
5021 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5022 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5023 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5024 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5025 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5026 break;
5027
5028 case BFD_RELOC_386_GOT32:
5029 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5030 value = 0; /* Fully resolved at runtime. No addend. */
5031 break;
47926f60
KH		 5032
5033 case BFD_RELOC_VTABLE_INHERIT:
5034 case BFD_RELOC_VTABLE_ENTRY:
5035 fixP->fx_done = 0;
94f592af 5036 return;
47926f60
KH		 5037
5038 default:
5039 break;
5040 }
5041#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5042 *valP = value;
f86103b7 5043#endif /* !defined (TE_Mach) */
3e73aa7c 5044
3e73aa7c 5045 /* Are we finished with this relocation now? */
c6682705 5046 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5047 fixP->fx_done = 1;
5048 else if (use_rela_relocations)
5049 {
5050 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5051 /* Remember value for tc_gen_reloc. */
5052 fixP->fx_addnumber = value;
3e73aa7c
JH		 5053 value = 0;
5054 }
f86103b7 5055
94f592af 5056 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5057}
252b5132 5058\f
252b5132
RH		 5059#define MAX_LITTLENUMS 6
5060
47926f60
KH		 5061/* Turn the string pointed to by litP into a floating point constant
5062 of type TYPE, and emit the appropriate bytes. The number of
5063 LITTLENUMS emitted is stored in *SIZEP. An error message is
5064 returned, or NULL on OK. */
5065
252b5132
RH		 5066char *
5067md_atof (type, litP, sizeP)
2ab9b79e 5068 int type;
252b5132
RH		 5069 char *litP;
5070 int *sizeP;
5071{
5072 int prec;
5073 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5074 LITTLENUM_TYPE *wordP;
5075 char *t;
5076
5077 switch (type)
5078 {
5079 case 'f':
5080 case 'F':
5081 prec = 2;
5082 break;
5083
5084 case 'd':
5085 case 'D':
5086 prec = 4;
5087 break;
5088
5089 case 'x':
5090 case 'X':
5091 prec = 5;
5092 break;
5093
5094 default:
5095 *sizeP = 0;
5096 return _("Bad call to md_atof ()");
5097 }
5098 t = atof_ieee (input_line_pointer, type, words);
5099 if (t)
5100 input_line_pointer = t;
5101
5102 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5103 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5104 the bigendian 386. */
5105 for (wordP = words + prec - 1; prec--;)
5106 {
5107 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5108 litP += sizeof (LITTLENUM_TYPE);
5109 }
5110 return 0;
5111}
5112\f
87c245cc 5113static char output_invalid_buf[8];
252b5132 5114
252b5132
RH		 5115static char *
5116output_invalid (c)
5117 int c;
5118{
3882b010 5119 if (ISPRINT (c))
252b5132
RH		 5120 sprintf (output_invalid_buf, "'%c'", c);
5121 else
5122 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
5123 return output_invalid_buf;
5124}
5125
af6bdddf 5126/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5127
5128static const reg_entry *
5129parse_register (reg_string, end_op)
5130 char *reg_string;
5131 char **end_op;
5132{
af6bdddf
AM		 5133 char *s = reg_string;
5134 char *p;
252b5132
RH		 5135 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5136 const reg_entry *r;
5137
5138 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5139 if (*s == REGISTER_PREFIX)
5140 ++s;
5141
5142 if (is_space_char (*s))
5143 ++s;
5144
5145 p = reg_name_given;
af6bdddf 5146 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5147 {
5148 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5149 return (const reg_entry *) NULL;
5150 s++;
252b5132
RH		 5151 }
5152
6588847e
DN		 5153 /* For naked regs, make sure that we are not dealing with an identifier.
5154 This prevents confusing an identifier like `eax_var' with register
5155 `eax'. */
5156 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5157 return (const reg_entry *) NULL;
5158
af6bdddf 5159 *end_op = s;
252b5132
RH		 5160
5161 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5162
5f47d35b 5163 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5164 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5165 {
5f47d35b
AM		 5166 if (is_space_char (*s))
5167 ++s;
5168 if (*s == '(')
5169 {
af6bdddf 5170 ++s;
5f47d35b
AM		 5171 if (is_space_char (*s))
5172 ++s;
5173 if (*s >= '0' && *s <= '7')
5174 {
5175 r = &i386_float_regtab[*s - '0'];
af6bdddf 5176 ++s;
5f47d35b
AM		 5177 if (is_space_char (*s))
5178 ++s;
5179 if (*s == ')')
5180 {
5181 *end_op = s + 1;
5182 return r;
5183 }
5f47d35b 5184 }
47926f60 5185 /* We have "%st(" then garbage. */
5f47d35b
AM		 5186 return (const reg_entry *) NULL;
5187 }
5188 }
5189
1ae00879 5190 if (r != NULL
20f0a1fc 5191 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5192 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5193 && flag_code != CODE_64BIT)
20f0a1fc 5194 return (const reg_entry *) NULL;
1ae00879 5195
252b5132
RH		 5196 return r;
5197}
5198\f
4cc782b5 5199#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5200const char *md_shortopts = "kVQ:sqn";
252b5132 5201#else
12b55ccc 5202const char *md_shortopts = "qn";
252b5132 5203#endif
6e0b89ee 5204
252b5132 5205struct option md_longopts[] = {
3e73aa7c
JH		 5206#define OPTION_32 (OPTION_MD_BASE + 0)
5207 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 5208#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 5209#define OPTION_64 (OPTION_MD_BASE + 1)
5210 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5211#endif
252b5132
RH		 5212 {NULL, no_argument, NULL, 0}
5213};
5214size_t md_longopts_size = sizeof (md_longopts);
5215
5216int
5217md_parse_option (c, arg)
5218 int c;
ab9da554 5219 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 5220{
5221 switch (c)
5222 {
12b55ccc
L		 5223 case 'n':
5224 optimize_align_code = 0;
5225 break;
5226
a38cf1db
AM		 5227 case 'q':
5228 quiet_warnings = 1;
252b5132
RH		 5229 break;
5230
5231#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5232 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5233 should be emitted or not. FIXME: Not implemented. */
5234 case 'Q':
252b5132
RH		 5235 break;
5236
5237 /* -V: SVR4 argument to print version ID. */
5238 case 'V':
5239 print_version_id ();
5240 break;
5241
a38cf1db
AM		 5242 /* -k: Ignore for FreeBSD compatibility. */
5243 case 'k':
252b5132 5244 break;
4cc782b5
ILT		 5245
5246 case 's':
5247 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5248 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5249 break;
6e0b89ee 5250
3e73aa7c
JH		 5251 case OPTION_64:
5252 {
5253 const char **list, **l;
5254
3e73aa7c
JH		 5255 list = bfd_target_list ();
5256 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 5257 if (strcmp (*l, "elf64-x86-64") == 0)
5258 {
5259 default_arch = "x86_64";
5260 break;
5261 }
3e73aa7c 5262 if (*l == NULL)
6e0b89ee 5263 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5264 free (list);
5265 }
5266 break;
5267#endif
252b5132 5268
6e0b89ee
AM		 5269 case OPTION_32:
5270 default_arch = "i386";
5271 break;
5272
252b5132
RH		 5273 default:
5274 return 0;
5275 }
5276 return 1;
5277}
5278
5279void
5280md_show_usage (stream)
5281 FILE *stream;
5282{
4cc782b5
ILT		 5283#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5284 fprintf (stream, _("\
a38cf1db
AM		 5285 -Q ignored\n\
5286 -V print assembler version number\n\
5287 -k ignored\n\
12b55ccc 5288 -n Do not optimize code alignment\n\
a38cf1db
AM		 5289 -q quieten some warnings\n\
5290 -s ignored\n"));
5291#else
5292 fprintf (stream, _("\
12b55ccc 5293 -n Do not optimize code alignment\n\
a38cf1db 5294 -q quieten some warnings\n"));
4cc782b5 5295#endif
252b5132
RH		 5296}
5297
3e73aa7c
JH		 5298#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5299 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5300
5301/* Pick the target format to use. */
5302
47926f60 5303const char *
252b5132
RH		 5304i386_target_format ()
5305{
3e73aa7c
JH		 5306 if (!strcmp (default_arch, "x86_64"))
5307 set_code_flag (CODE_64BIT);
5308 else if (!strcmp (default_arch, "i386"))
5309 set_code_flag (CODE_32BIT);
5310 else
5311 as_fatal (_("Unknown architecture"));
252b5132
RH		 5312 switch (OUTPUT_FLAVOR)
5313 {
4c63da97
AM		 5314#ifdef OBJ_MAYBE_AOUT
5315 case bfd_target_aout_flavour:
47926f60 5316 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5317#endif
5318#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5319 case bfd_target_coff_flavour:
5320 return "coff-i386";
4c63da97 5321#endif
3e73aa7c 5322#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5323 case bfd_target_elf_flavour:
3e73aa7c 5324 {
e5cb08ac
KH		 5325 if (flag_code == CODE_64BIT)
5326 use_rela_relocations = 1;
4ada7262 5327 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5328 }
4c63da97 5329#endif
252b5132
RH		 5330 default:
5331 abort ();
5332 return NULL;
5333 }
5334}
5335
47926f60 5336#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5337
5338#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5339void i386_elf_emit_arch_note ()
5340{
718ddfc0 5341 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 5342 {
5343 char *p;
5344 asection *seg = now_seg;
5345 subsegT subseg = now_subseg;
5346 Elf_Internal_Note i_note;
5347 Elf_External_Note e_note;
5348 asection *note_secp;
5349 int len;
5350
5351 /* Create the .note section. */
5352 note_secp = subseg_new (".note", 0);
5353 bfd_set_section_flags (stdoutput,
5354 note_secp,
5355 SEC_HAS_CONTENTS | SEC_READONLY);
5356
5357 /* Process the arch string. */
5358 len = strlen (cpu_arch_name);
5359
5360 i_note.namesz = len + 1;
5361 i_note.descsz = 0;
5362 i_note.type = NT_ARCH;
5363 p = frag_more (sizeof (e_note.namesz));
5364 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5365 p = frag_more (sizeof (e_note.descsz));
5366 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5367 p = frag_more (sizeof (e_note.type));
5368 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5369 p = frag_more (len + 1);
5370 strcpy (p, cpu_arch_name);
5371
5372 frag_align (2, 0, 0);
5373
5374 subseg_set (seg, subseg);
5375 }
5376}
5377#endif
252b5132 5378\f
252b5132
RH		 5379symbolS *
5380md_undefined_symbol (name)
5381 char *name;
5382{
18dc2407
ILT		 5383 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5384 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5385 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5386 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5387 {
5388 if (!GOT_symbol)
5389 {
5390 if (symbol_find (name))
5391 as_bad (_("GOT already in symbol table"));
5392 GOT_symbol = symbol_new (name, undefined_section,
5393 (valueT) 0, &zero_address_frag);
5394 };
5395 return GOT_symbol;
5396 }
252b5132
RH		 5397 return 0;
5398}
5399
5400/* Round up a section size to the appropriate boundary. */
47926f60 5401
252b5132
RH		 5402valueT
5403md_section_align (segment, size)
ab9da554 5404 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5405 valueT size;
5406{
4c63da97
AM		 5407#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5408 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5409 {
5410 /* For a.out, force the section size to be aligned. If we don't do
5411 this, BFD will align it for us, but it will not write out the
5412 final bytes of the section. This may be a bug in BFD, but it is
5413 easier to fix it here since that is how the other a.out targets
5414 work. */
5415 int align;
5416
5417 align = bfd_get_section_alignment (stdoutput, segment);
5418 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5419 }
252b5132
RH		 5420#endif
5421
5422 return size;
5423}
5424
5425/* On the i386, PC-relative offsets are relative to the start of the
5426 next instruction. That is, the address of the offset, plus its
5427 size, since the offset is always the last part of the insn. */
5428
5429long
5430md_pcrel_from (fixP)
5431 fixS *fixP;
5432{
5433 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5434}
5435
5436#ifndef I386COFF
5437
5438static void
5439s_bss (ignore)
ab9da554 5440 int ignore ATTRIBUTE_UNUSED;
252b5132 5441{
29b0f896 5442 int temp;
252b5132 5443
8a75718c
JB		 5444#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5445 if (IS_ELF)
5446 obj_elf_section_change_hook ();
5447#endif
252b5132
RH		 5448 temp = get_absolute_expression ();
5449 subseg_set (bss_section, (subsegT) temp);
5450 demand_empty_rest_of_line ();
5451}
5452
5453#endif
5454
252b5132
RH		 5455void
5456i386_validate_fix (fixp)
5457 fixS *fixp;
5458{
5459 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5460 {
23df1078
JH		 5461 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5462 {
5463 if (flag_code != CODE_64BIT)
5464 abort ();
5465 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5466 }
5467 else
5468 {
d6ab8113
JB		 5469 if (flag_code != CODE_64BIT)
5470 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5471 else
5472 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 5473 }
252b5132
RH		 5474 fixp->fx_subsy = 0;
5475 }
5476}
5477
252b5132
RH		 5478arelent *
5479tc_gen_reloc (section, fixp)
ab9da554 5480 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5481 fixS *fixp;
5482{
5483 arelent *rel;
5484 bfd_reloc_code_real_type code;
5485
5486 switch (fixp->fx_r_type)
5487 {
3e73aa7c
JH		 5488 case BFD_RELOC_X86_64_PLT32:
5489 case BFD_RELOC_X86_64_GOT32:
5490 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5491 case BFD_RELOC_386_PLT32:
5492 case BFD_RELOC_386_GOT32:
5493 case BFD_RELOC_386_GOTOFF:
5494 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5495 case BFD_RELOC_386_TLS_GD:
5496 case BFD_RELOC_386_TLS_LDM:
5497 case BFD_RELOC_386_TLS_LDO_32:
5498 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5499 case BFD_RELOC_386_TLS_IE:
5500 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5501 case BFD_RELOC_386_TLS_LE_32:
5502 case BFD_RELOC_386_TLS_LE:
bffbf940
JJ		 5503 case BFD_RELOC_X86_64_TLSGD:
5504 case BFD_RELOC_X86_64_TLSLD:
5505 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5506 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 5507 case BFD_RELOC_X86_64_GOTTPOFF:
5508 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 5509 case BFD_RELOC_X86_64_TPOFF64:
5510 case BFD_RELOC_X86_64_GOTOFF64:
5511 case BFD_RELOC_X86_64_GOTPC32:
252b5132
RH		 5512 case BFD_RELOC_RVA:
5513 case BFD_RELOC_VTABLE_ENTRY:
5514 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5515#ifdef TE_PE
5516 case BFD_RELOC_32_SECREL:
5517#endif
252b5132
RH		 5518 code = fixp->fx_r_type;
5519 break;
dbbaec26
L		 5520 case BFD_RELOC_X86_64_32S:
5521 if (!fixp->fx_pcrel)
5522 {
5523 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5524 code = fixp->fx_r_type;
5525 break;
5526 }
252b5132 5527 default:
93382f6d 5528 if (fixp->fx_pcrel)
252b5132 5529 {
93382f6d
AM		 5530 switch (fixp->fx_size)
5531 {
5532 default:
b091f402
AM		 5533 as_bad_where (fixp->fx_file, fixp->fx_line,
5534 _("can not do %d byte pc-relative relocation"),
5535 fixp->fx_size);
93382f6d
AM		 5536 code = BFD_RELOC_32_PCREL;
5537 break;
5538 case 1: code = BFD_RELOC_8_PCREL; break;
5539 case 2: code = BFD_RELOC_16_PCREL; break;
5540 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 5541#ifdef BFD64
5542 case 8: code = BFD_RELOC_64_PCREL; break;
5543#endif
93382f6d
AM		 5544 }
5545 }
5546 else
5547 {
5548 switch (fixp->fx_size)
5549 {
5550 default:
b091f402
AM		 5551 as_bad_where (fixp->fx_file, fixp->fx_line,
5552 _("can not do %d byte relocation"),
5553 fixp->fx_size);
93382f6d
AM		 5554 code = BFD_RELOC_32;
5555 break;
5556 case 1: code = BFD_RELOC_8; break;
5557 case 2: code = BFD_RELOC_16; break;
5558 case 4: code = BFD_RELOC_32; break;
937149dd 5559#ifdef BFD64
3e73aa7c 5560 case 8: code = BFD_RELOC_64; break;
937149dd 5561#endif
93382f6d 5562 }
252b5132
RH		 5563 }
5564 break;
5565 }
252b5132 5566
d6ab8113 5567 if ((code == BFD_RELOC_32 || code == BFD_RELOC_32_PCREL)
252b5132
RH		 5568 && GOT_symbol
5569 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 5570 {
d6ab8113
JB		 5571 if (flag_code != CODE_64BIT)
5572 code = BFD_RELOC_386_GOTPC;
5573 else
5574 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 5575 }
252b5132
RH		 5576
5577 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5578 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5579 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5580
5581 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 5582
3e73aa7c
JH		 5583 if (!use_rela_relocations)
5584 {
5585 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5586 vtable entry to be used in the relocation's section offset. */
5587 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5588 rel->address = fixp->fx_offset;
252b5132 5589
c6682705 5590 rel->addend = 0;
3e73aa7c
JH		 5591 }
5592 /* Use the rela in 64bit mode. */
252b5132 5593 else
3e73aa7c 5594 {
062cd5e7
AS		 5595 if (!fixp->fx_pcrel)
5596 rel->addend = fixp->fx_offset;
5597 else
5598 switch (code)
5599 {
5600 case BFD_RELOC_X86_64_PLT32:
5601 case BFD_RELOC_X86_64_GOT32:
5602 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5603 case BFD_RELOC_X86_64_TLSGD:
5604 case BFD_RELOC_X86_64_TLSLD:
5605 case BFD_RELOC_X86_64_GOTTPOFF:
062cd5e7
AS		 5606 rel->addend = fixp->fx_offset - fixp->fx_size;
5607 break;
5608 default:
5609 rel->addend = (section->vma
5610 - fixp->fx_size
5611 + fixp->fx_addnumber
5612 + md_pcrel_from (fixp));
5613 break;
5614 }
3e73aa7c
JH		 5615 }
5616
252b5132
RH		 5617 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5618 if (rel->howto == NULL)
5619 {
5620 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5621 _("cannot represent relocation type %s"),
252b5132
RH		 5622 bfd_get_reloc_code_name (code));
5623 /* Set howto to a garbage value so that we can keep going. */
5624 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5625 assert (rel->howto != NULL);
5626 }
5627
5628 return rel;
5629}
5630
64a0c779
DN		 5631\f
5632/* Parse operands using Intel syntax. This implements a recursive descent
5633 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5634 Programmer's Guide.
5635
5636 FIXME: We do not recognize the full operand grammar defined in the MASM
5637 documentation. In particular, all the structure/union and
5638 high-level macro operands are missing.
5639
5640 Uppercase words are terminals, lower case words are non-terminals.
5641 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5642 bars '|' denote choices. Most grammar productions are implemented in
5643 functions called 'intel_<production>'.
5644
5645 Initial production is 'expr'.
5646
9306ca4a 5647 addOp + | -
64a0c779
DN		 5648
5649 alpha [a-zA-Z]
5650
9306ca4a
JB		 5651 binOp & | AND | \| | OR | ^ | XOR
5652
64a0c779
DN		 5653 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5654
5655 constant digits [[ radixOverride ]]
5656
9306ca4a 5657 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 5658
5659 digits decdigit
b77a7acd
AJ		 5660 | digits decdigit
5661 | digits hexdigit
64a0c779
DN		 5662
5663 decdigit [0-9]
5664
9306ca4a
JB		 5665 e04 e04 addOp e05
5666 | e05
5667
5668 e05 e05 binOp e06
b77a7acd 5669 | e06
64a0c779
DN		 5670
5671 e06 e06 mulOp e09
b77a7acd 5672 | e09
64a0c779
DN		 5673
5674 e09 OFFSET e10
a724f0f4
JB		 5675 | SHORT e10
5676 | + e10
5677 | - e10
9306ca4a
JB		 5678 | ~ e10
5679 | NOT e10
64a0c779
DN		 5680 | e09 PTR e10
5681 | e09 : e10
5682 | e10
5683
5684 e10 e10 [ expr ]
b77a7acd 5685 | e11
64a0c779
DN		 5686
5687 e11 ( expr )
b77a7acd 5688 | [ expr ]
64a0c779
DN		 5689 | constant
5690 | dataType
5691 | id
5692 | $
5693 | register
5694
a724f0f4 5695 => expr expr cmpOp e04
9306ca4a 5696 | e04
64a0c779
DN		 5697
5698 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5699 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5700
5701 hexdigit a | b | c | d | e | f
b77a7acd 5702 | A | B | C | D | E | F
64a0c779
DN		 5703
5704 id alpha
b77a7acd 5705 | id alpha
64a0c779
DN		 5706 | id decdigit
5707
9306ca4a 5708 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 5709
5710 quote " | '
5711
5712 register specialRegister
b77a7acd 5713 | gpRegister
64a0c779
DN		 5714 | byteRegister
5715
5716 segmentRegister CS | DS | ES | FS | GS | SS
5717
9306ca4a 5718 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 5719 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5720 | TR3 | TR4 | TR5 | TR6 | TR7
5721
64a0c779
DN		 5722 We simplify the grammar in obvious places (e.g., register parsing is
5723 done by calling parse_register) and eliminate immediate left recursion
5724 to implement a recursive-descent parser.
5725
a724f0f4
JB		 5726 expr e04 expr'
5727
5728 expr' cmpOp e04 expr'
5729 | Empty
9306ca4a
JB		 5730
5731 e04 e05 e04'
5732
5733 e04' addOp e05 e04'
5734 | Empty
64a0c779
DN		 5735
5736 e05 e06 e05'
5737
9306ca4a 5738 e05' binOp e06 e05'
b77a7acd 5739 | Empty
64a0c779
DN		 5740
5741 e06 e09 e06'
5742
5743 e06' mulOp e09 e06'
b77a7acd 5744 | Empty
64a0c779
DN		 5745
5746 e09 OFFSET e10 e09'
a724f0f4
JB		 5747 | SHORT e10'
5748 | + e10'
5749 | - e10'
5750 | ~ e10'
5751 | NOT e10'
b77a7acd 5752 | e10 e09'
64a0c779
DN		 5753
5754 e09' PTR e10 e09'
b77a7acd 5755 | : e10 e09'
64a0c779
DN		 5756 | Empty
5757
5758 e10 e11 e10'
5759
5760 e10' [ expr ] e10'
b77a7acd 5761 | Empty
64a0c779
DN		 5762
5763 e11 ( expr )
b77a7acd 5764 | [ expr ]
64a0c779
DN		 5765 | BYTE
5766 | WORD
5767 | DWORD
9306ca4a 5768 | FWORD
64a0c779 5769 | QWORD
9306ca4a
JB		 5770 | TBYTE
5771 | OWORD
5772 | XMMWORD
64a0c779
DN		 5773 | .
5774 | $
5775 | register
5776 | id
5777 | constant */
5778
5779/* Parsing structure for the intel syntax parser. Used to implement the
5780 semantic actions for the operand grammar. */
5781struct intel_parser_s
5782 {
5783 char *op_string; /* The string being parsed. */
5784 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5785 int op_modifier; /* Operand modifier. */
64a0c779 5786 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 5787 int in_offset; /* >=1 if parsing operand of offset. */
5788 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 5789 const reg_entry *reg; /* Last register reference found. */
5790 char *disp; /* Displacement string being built. */
a724f0f4 5791 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 5792 };
5793
5794static struct intel_parser_s intel_parser;
5795
5796/* Token structure for parsing intel syntax. */
5797struct intel_token
5798 {
5799 int code; /* Token code. */
5800 const reg_entry *reg; /* Register entry for register tokens. */
5801 char *str; /* String representation. */
5802 };
5803
5804static struct intel_token cur_token, prev_token;
5805
50705ef4
AM		 5806/* Token codes for the intel parser. Since T_SHORT is already used
5807 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5808#define T_NIL -1
5809#define T_CONST 1
5810#define T_REG 2
5811#define T_BYTE 3
5812#define T_WORD 4
9306ca4a
JB		 5813#define T_DWORD 5
5814#define T_FWORD 6
5815#define T_QWORD 7
5816#define T_TBYTE 8
5817#define T_XMMWORD 9
50705ef4 5818#undef T_SHORT
9306ca4a
JB		 5819#define T_SHORT 10
5820#define T_OFFSET 11
5821#define T_PTR 12
5822#define T_ID 13
5823#define T_SHL 14
5824#define T_SHR 15
64a0c779
DN		 5825
5826/* Prototypes for intel parser functions. */
5827static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5828static void intel_get_token PARAMS ((void));
5829static void intel_putback_token PARAMS ((void));
5830static int intel_expr PARAMS ((void));
9306ca4a 5831static int intel_e04 PARAMS ((void));
cce0cbdc 5832static int intel_e05 PARAMS ((void));
cce0cbdc 5833static int intel_e06 PARAMS ((void));
cce0cbdc 5834static int intel_e09 PARAMS ((void));
a724f0f4 5835static int intel_bracket_expr PARAMS ((void));
cce0cbdc 5836static int intel_e10 PARAMS ((void));
cce0cbdc 5837static int intel_e11 PARAMS ((void));
64a0c779 5838
64a0c779
DN		 5839static int
5840i386_intel_operand (operand_string, got_a_float)
5841 char *operand_string;
5842 int got_a_float;
5843{
5844 int ret;
5845 char *p;
5846
a724f0f4
JB		 5847 p = intel_parser.op_string = xstrdup (operand_string);
5848 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
5849
5850 for (;;)
64a0c779 5851 {
a724f0f4
JB		 5852 /* Initialize token holders. */
5853 cur_token.code = prev_token.code = T_NIL;
5854 cur_token.reg = prev_token.reg = NULL;
5855 cur_token.str = prev_token.str = NULL;
5856
5857 /* Initialize parser structure. */
5858 intel_parser.got_a_float = got_a_float;
5859 intel_parser.op_modifier = 0;
5860 intel_parser.is_mem = 0;
5861 intel_parser.in_offset = 0;
5862 intel_parser.in_bracket = 0;
5863 intel_parser.reg = NULL;
5864 intel_parser.disp[0] = '\0';
5865 intel_parser.next_operand = NULL;
5866
5867 /* Read the first token and start the parser. */
5868 intel_get_token ();
5869 ret = intel_expr ();
5870
5871 if (!ret)
5872 break;
5873
9306ca4a
JB		 5874 if (cur_token.code != T_NIL)
5875 {
5876 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5877 current_templates->start->name, cur_token.str);
5878 ret = 0;
5879 }
64a0c779
DN		 5880 /* If we found a memory reference, hand it over to i386_displacement
5881 to fill in the rest of the operand fields. */
9306ca4a 5882 else if (intel_parser.is_mem)
64a0c779
DN		 5883 {
5884 if ((i.mem_operands == 1
5885 && (current_templates->start->opcode_modifier & IsString) == 0)
5886 || i.mem_operands == 2)
5887 {
5888 as_bad (_("too many memory references for '%s'"),
5889 current_templates->start->name);
5890 ret = 0;
5891 }
5892 else
5893 {
5894 char *s = intel_parser.disp;
5895 i.mem_operands++;
5896
a724f0f4
JB		 5897 if (!quiet_warnings && intel_parser.is_mem < 0)
5898 /* See the comments in intel_bracket_expr. */
5899 as_warn (_("Treating `%s' as memory reference"), operand_string);
5900
64a0c779
DN		 5901 /* Add the displacement expression. */
5902 if (*s != '\0')
a4622f40
AM		 5903 ret = i386_displacement (s, s + strlen (s));
5904 if (ret)
a724f0f4
JB		 5905 {
5906 /* Swap base and index in 16-bit memory operands like
5907 [si+bx]. Since i386_index_check is also used in AT&T
5908 mode we have to do that here. */
5909 if (i.base_reg
5910 && i.index_reg
5911 && (i.base_reg->reg_type & Reg16)
5912 && (i.index_reg->reg_type & Reg16)
5913 && i.base_reg->reg_num >= 6
5914 && i.index_reg->reg_num < 6)
5915 {
5916 const reg_entry *base = i.index_reg;
5917
5918 i.index_reg = i.base_reg;
5919 i.base_reg = base;
5920 }
5921 ret = i386_index_check (operand_string);
5922 }
64a0c779
DN		 5923 }
5924 }
5925
5926 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 5927 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 5928 || intel_parser.reg == NULL)
5929 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 5930
5931 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
5932 ret = 0;
5933 if (!ret || !intel_parser.next_operand)
5934 break;
5935 intel_parser.op_string = intel_parser.next_operand;
5936 this_operand = i.operands++;
64a0c779
DN		 5937 }
5938
5939 free (p);
5940 free (intel_parser.disp);
5941
5942 return ret;
5943}
5944
a724f0f4
JB		 5945#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5946
5947/* expr e04 expr'
5948
5949 expr' cmpOp e04 expr'
5950 | Empty */
64a0c779
DN		 5951static int
5952intel_expr ()
5953{
a724f0f4
JB		 5954 /* XXX Implement the comparison operators. */
5955 return intel_e04 ();
9306ca4a
JB		 5956}
5957
a724f0f4 5958/* e04 e05 e04'
9306ca4a 5959
a724f0f4 5960 e04' addOp e05 e04'
9306ca4a
JB		 5961 | Empty */
5962static int
5963intel_e04 ()
5964{
a724f0f4 5965 int nregs = -1;
9306ca4a 5966
a724f0f4 5967 for (;;)
9306ca4a 5968 {
a724f0f4
JB		 5969 if (!intel_e05())
5970 return 0;
9306ca4a 5971
a724f0f4
JB		 5972 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5973 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 5974
a724f0f4
JB		 5975 if (cur_token.code == '+')
5976 nregs = -1;
5977 else if (cur_token.code == '-')
5978 nregs = NUM_ADDRESS_REGS;
5979 else
5980 return 1;
64a0c779 5981
a724f0f4
JB		 5982 strcat (intel_parser.disp, cur_token.str);
5983 intel_match_token (cur_token.code);
5984 }
64a0c779
DN		 5985}
5986
64a0c779
DN		 5987/* e05 e06 e05'
5988
9306ca4a 5989 e05' binOp e06 e05'
64a0c779
DN		 5990 | Empty */
5991static int
5992intel_e05 ()
5993{
a724f0f4 5994 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 5995
a724f0f4 5996 for (;;)
64a0c779 5997 {
a724f0f4
JB		 5998 if (!intel_e06())
5999 return 0;
6000
6001 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6002 {
6003 char str[2];
6004
6005 str[0] = cur_token.code;
6006 str[1] = 0;
6007 strcat (intel_parser.disp, str);
6008 }
6009 else
6010 break;
9306ca4a 6011
64a0c779
DN		 6012 intel_match_token (cur_token.code);
6013
a724f0f4
JB		 6014 if (nregs < 0)
6015 nregs = ~nregs;
64a0c779 6016 }
a724f0f4
JB		 6017 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6018 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6019 return 1;
4a1805b1 6020}
64a0c779
DN		 6021
6022/* e06 e09 e06'
6023
6024 e06' mulOp e09 e06'
b77a7acd 6025 | Empty */
64a0c779
DN		 6026static int
6027intel_e06 ()
6028{
a724f0f4 6029 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6030
a724f0f4 6031 for (;;)
64a0c779 6032 {
a724f0f4
JB		 6033 if (!intel_e09())
6034 return 0;
9306ca4a 6035
a724f0f4
JB		 6036 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6037 {
6038 char str[2];
9306ca4a 6039
a724f0f4
JB		 6040 str[0] = cur_token.code;
6041 str[1] = 0;
6042 strcat (intel_parser.disp, str);
6043 }
6044 else if (cur_token.code == T_SHL)
6045 strcat (intel_parser.disp, "<<");
6046 else if (cur_token.code == T_SHR)
6047 strcat (intel_parser.disp, ">>");
6048 else
6049 break;
9306ca4a 6050
a724f0f4 6051 intel_match_token (cur_token.code);
64a0c779 6052
a724f0f4
JB		 6053 if (nregs < 0)
6054 nregs = ~nregs;
64a0c779 6055 }
a724f0f4
JB		 6056 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6057 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6058 return 1;
64a0c779
DN		 6059}
6060
a724f0f4
JB		 6061/* e09 OFFSET e09
6062 | SHORT e09
6063 | + e09
6064 | - e09
6065 | ~ e09
6066 | NOT e09
9306ca4a
JB		 6067 | e10 e09'
6068
64a0c779 6069 e09' PTR e10 e09'
b77a7acd 6070 | : e10 e09'
64a0c779
DN		 6071 | Empty */
6072static int
6073intel_e09 ()
6074{
a724f0f4
JB		 6075 int nregs = ~NUM_ADDRESS_REGS;
6076 int in_offset = 0;
6077
6078 for (;;)
64a0c779 6079 {
a724f0f4
JB		 6080 /* Don't consume constants here. */
6081 if (cur_token.code == '+' || cur_token.code == '-')
6082 {
6083 /* Need to look one token ahead - if the next token
6084 is a constant, the current token is its sign. */
6085 int next_code;
6086
6087 intel_match_token (cur_token.code);
6088 next_code = cur_token.code;
6089 intel_putback_token ();
6090 if (next_code == T_CONST)
6091 break;
6092 }
6093
6094 /* e09 OFFSET e09 */
6095 if (cur_token.code == T_OFFSET)
6096 {
6097 if (!in_offset++)
6098 ++intel_parser.in_offset;
6099 }
6100
6101 /* e09 SHORT e09 */
6102 else if (cur_token.code == T_SHORT)
6103 intel_parser.op_modifier |= 1 << T_SHORT;
6104
6105 /* e09 + e09 */
6106 else if (cur_token.code == '+')
6107 strcat (intel_parser.disp, "+");
6108
6109 /* e09 - e09
6110 | ~ e09
6111 | NOT e09 */
6112 else if (cur_token.code == '-' || cur_token.code == '~')
6113 {
6114 char str[2];
64a0c779 6115
a724f0f4
JB		 6116 if (nregs < 0)
6117 nregs = ~nregs;
6118 str[0] = cur_token.code;
6119 str[1] = 0;
6120 strcat (intel_parser.disp, str);
6121 }
6122
6123 /* e09 e10 e09' */
6124 else
6125 break;
6126
6127 intel_match_token (cur_token.code);
64a0c779
DN		 6128 }
6129
a724f0f4 6130 for (;;)
9306ca4a 6131 {
a724f0f4
JB		 6132 if (!intel_e10 ())
6133 return 0;
9306ca4a 6134
a724f0f4
JB		 6135 /* e09' PTR e10 e09' */
6136 if (cur_token.code == T_PTR)
6137 {
6138 char suffix;
9306ca4a 6139
a724f0f4
JB		 6140 if (prev_token.code == T_BYTE)
6141 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6142
a724f0f4
JB		 6143 else if (prev_token.code == T_WORD)
6144 {
6145 if (current_templates->start->name[0] == 'l'
6146 && current_templates->start->name[2] == 's'
6147 && current_templates->start->name[3] == 0)
6148 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6149 else if (intel_parser.got_a_float == 2) /* "fi..." */
6150 suffix = SHORT_MNEM_SUFFIX;
6151 else
6152 suffix = WORD_MNEM_SUFFIX;
6153 }
64a0c779 6154
a724f0f4
JB		 6155 else if (prev_token.code == T_DWORD)
6156 {
6157 if (current_templates->start->name[0] == 'l'
6158 && current_templates->start->name[2] == 's'
6159 && current_templates->start->name[3] == 0)
6160 suffix = WORD_MNEM_SUFFIX;
6161 else if (flag_code == CODE_16BIT
6162 && (current_templates->start->opcode_modifier
6163 & (Jump|JumpDword|JumpInterSegment)))
6164 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6165 else if (intel_parser.got_a_float == 1) /* "f..." */
6166 suffix = SHORT_MNEM_SUFFIX;
6167 else
6168 suffix = LONG_MNEM_SUFFIX;
6169 }
9306ca4a 6170
a724f0f4
JB		 6171 else if (prev_token.code == T_FWORD)
6172 {
6173 if (current_templates->start->name[0] == 'l'
6174 && current_templates->start->name[2] == 's'
6175 && current_templates->start->name[3] == 0)
6176 suffix = LONG_MNEM_SUFFIX;
6177 else if (!intel_parser.got_a_float)
6178 {
6179 if (flag_code == CODE_16BIT)
6180 add_prefix (DATA_PREFIX_OPCODE);
6181 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6182 }
6183 else
6184 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6185 }
64a0c779 6186
a724f0f4
JB		 6187 else if (prev_token.code == T_QWORD)
6188 {
6189 if (intel_parser.got_a_float == 1) /* "f..." */
6190 suffix = LONG_MNEM_SUFFIX;
6191 else
6192 suffix = QWORD_MNEM_SUFFIX;
6193 }
64a0c779 6194
a724f0f4
JB		 6195 else if (prev_token.code == T_TBYTE)
6196 {
6197 if (intel_parser.got_a_float == 1)
6198 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6199 else
6200 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6201 }
9306ca4a 6202
a724f0f4 6203 else if (prev_token.code == T_XMMWORD)
9306ca4a 6204 {
a724f0f4
JB		 6205 /* XXX ignored for now, but accepted since gcc uses it */
6206 suffix = 0;
9306ca4a 6207 }
64a0c779 6208
f16b83df 6209 else
a724f0f4
JB		 6210 {
6211 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6212 return 0;
6213 }
6214
6215 if (current_templates->start->base_opcode == 0x8d /* lea */)
6216 ;
6217 else if (!i.suffix)
6218 i.suffix = suffix;
6219 else if (i.suffix != suffix)
6220 {
6221 as_bad (_("Conflicting operand modifiers"));
6222 return 0;
6223 }
64a0c779 6224
9306ca4a
JB		 6225 }
6226
a724f0f4
JB		 6227 /* e09' : e10 e09' */
6228 else if (cur_token.code == ':')
9306ca4a 6229 {
a724f0f4
JB		 6230 if (prev_token.code != T_REG)
6231 {
6232 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6233 segment/group identifier (which we don't have), using comma
6234 as the operand separator there is even less consistent, since
6235 there all branches only have a single operand. */
6236 if (this_operand != 0
6237 || intel_parser.in_offset
6238 || intel_parser.in_bracket
6239 || (!(current_templates->start->opcode_modifier
6240 & (Jump|JumpDword|JumpInterSegment))
6241 && !(current_templates->start->operand_types[0]
6242 & JumpAbsolute)))
6243 return intel_match_token (T_NIL);
6244 /* Remember the start of the 2nd operand and terminate 1st
6245 operand here.
6246 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6247 another expression), but it gets at least the simplest case
6248 (a plain number or symbol on the left side) right. */
6249 intel_parser.next_operand = intel_parser.op_string;
6250 *--intel_parser.op_string = '\0';
6251 return intel_match_token (':');
6252 }
9306ca4a 6253 }
64a0c779 6254
a724f0f4 6255 /* e09' Empty */
64a0c779 6256 else
a724f0f4 6257 break;
64a0c779 6258
a724f0f4
JB		 6259 intel_match_token (cur_token.code);
6260
6261 }
6262
6263 if (in_offset)
6264 {
6265 --intel_parser.in_offset;
6266 if (nregs < 0)
6267 nregs = ~nregs;
6268 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6269 {
a724f0f4 6270 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6271 return 0;
6272 }
a724f0f4
JB		 6273 intel_parser.op_modifier |= 1 << T_OFFSET;
6274 }
9306ca4a 6275
a724f0f4
JB		 6276 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6277 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6278 return 1;
6279}
64a0c779 6280
a724f0f4
JB		 6281static int
6282intel_bracket_expr ()
6283{
6284 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6285 const char *start = intel_parser.op_string;
6286 int len;
6287
6288 if (i.op[this_operand].regs)
6289 return intel_match_token (T_NIL);
6290
6291 intel_match_token ('[');
6292
6293 /* Mark as a memory operand only if it's not already known to be an
6294 offset expression. If it's an offset expression, we need to keep
6295 the brace in. */
6296 if (!intel_parser.in_offset)
6297 {
6298 ++intel_parser.in_bracket;
6299 /* Unfortunately gas always diverged from MASM in a respect that can't
6300 be easily fixed without risking to break code sequences likely to be
6301 encountered (the testsuite even check for this): MASM doesn't consider
6302 an expression inside brackets unconditionally as a memory reference.
6303 When that is e.g. a constant, an offset expression, or the sum of the
6304 two, this is still taken as a constant load. gas, however, always
6305 treated these as memory references. As a compromise, we'll try to make
6306 offset expressions inside brackets work the MASM way (since that's
6307 less likely to be found in real world code), but make constants alone
6308 continue to work the traditional gas way. In either case, issue a
6309 warning. */
6310 intel_parser.op_modifier &= ~was_offset;
64a0c779 6311 }
a724f0f4
JB		 6312 else
6313 strcat (intel_parser.disp, "[");
6314
6315 /* Add a '+' to the displacement string if necessary. */
6316 if (*intel_parser.disp != '\0'
6317 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6318 strcat (intel_parser.disp, "+");
64a0c779 6319
a724f0f4
JB		 6320 if (intel_expr ()
6321 && (len = intel_parser.op_string - start - 1,
6322 intel_match_token (']')))
64a0c779 6323 {
a724f0f4
JB		 6324 /* Preserve brackets when the operand is an offset expression. */
6325 if (intel_parser.in_offset)
6326 strcat (intel_parser.disp, "]");
6327 else
6328 {
6329 --intel_parser.in_bracket;
6330 if (i.base_reg || i.index_reg)
6331 intel_parser.is_mem = 1;
6332 if (!intel_parser.is_mem)
6333 {
6334 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6335 /* Defer the warning until all of the operand was parsed. */
6336 intel_parser.is_mem = -1;
6337 else if (!quiet_warnings)
6338 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6339 }
6340 }
6341 intel_parser.op_modifier |= was_offset;
64a0c779 6342
a724f0f4 6343 return 1;
64a0c779 6344 }
a724f0f4 6345 return 0;
64a0c779
DN		 6346}
6347
6348/* e10 e11 e10'
6349
6350 e10' [ expr ] e10'
b77a7acd 6351 | Empty */
64a0c779
DN		 6352static int
6353intel_e10 ()
6354{
a724f0f4
JB		 6355 if (!intel_e11 ())
6356 return 0;
64a0c779 6357
a724f0f4 6358 while (cur_token.code == '[')
64a0c779 6359 {
a724f0f4 6360 if (!intel_bracket_expr ())
21d6c4af 6361 return 0;
64a0c779
DN		 6362 }
6363
a724f0f4 6364 return 1;
64a0c779
DN		 6365}
6366
64a0c779 6367/* e11 ( expr )
b77a7acd 6368 | [ expr ]
64a0c779
DN		 6369 | BYTE
6370 | WORD
6371 | DWORD
9306ca4a 6372 | FWORD
64a0c779 6373 | QWORD
9306ca4a
JB		 6374 | TBYTE
6375 | OWORD
6376 | XMMWORD
4a1805b1 6377 | $
64a0c779
DN		 6378 | .
6379 | register
6380 | id
6381 | constant */
6382static int
6383intel_e11 ()
6384{
a724f0f4 6385 switch (cur_token.code)
64a0c779 6386 {
a724f0f4
JB		 6387 /* e11 ( expr ) */
6388 case '(':
64a0c779
DN		 6389 intel_match_token ('(');
6390 strcat (intel_parser.disp, "(");
6391
6392 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 6393 {
6394 strcat (intel_parser.disp, ")");
6395 return 1;
6396 }
a724f0f4 6397 return 0;
4a1805b1 6398
a724f0f4
JB		 6399 /* e11 [ expr ] */
6400 case '[':
6401 /* Operands for jump/call inside brackets denote absolute addresses.
6402 XXX This shouldn't be needed anymore (or if it should rather live
6403 in intel_bracket_expr). */
9306ca4a
JB		 6404 if (current_templates->start->opcode_modifier
6405 & (Jump|JumpDword|JumpByte|JumpInterSegment))
64a0c779
DN		 6406 i.types[this_operand] |= JumpAbsolute;
6407
a724f0f4 6408 return intel_bracket_expr ();
64a0c779 6409
a724f0f4
JB		 6410 /* e11 $
6411 | . */
6412 case '.':
64a0c779
DN		 6413 strcat (intel_parser.disp, cur_token.str);
6414 intel_match_token (cur_token.code);
21d6c4af
DN		 6415
6416 /* Mark as a memory operand only if it's not already known to be an
6417 offset expression. */
a724f0f4 6418 if (!intel_parser.in_offset)
21d6c4af 6419 intel_parser.is_mem = 1;
64a0c779
DN		 6420
6421 return 1;
64a0c779 6422
a724f0f4
JB		 6423 /* e11 register */
6424 case T_REG:
6425 {
6426 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 6427
a724f0f4 6428 intel_match_token (T_REG);
64a0c779 6429
a724f0f4
JB		 6430 /* Check for segment change. */
6431 if (cur_token.code == ':')
6432 {
6433 if (!(reg->reg_type & (SReg2 | SReg3)))
6434 {
6435 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6436 return 0;
6437 }
6438 else if (i.seg[i.mem_operands])
6439 as_warn (_("Extra segment override ignored"));
6440 else
6441 {
6442 if (!intel_parser.in_offset)
6443 intel_parser.is_mem = 1;
6444 switch (reg->reg_num)
6445 {
6446 case 0:
6447 i.seg[i.mem_operands] = &es;
6448 break;
6449 case 1:
6450 i.seg[i.mem_operands] = &cs;
6451 break;
6452 case 2:
6453 i.seg[i.mem_operands] = &ss;
6454 break;
6455 case 3:
6456 i.seg[i.mem_operands] = &ds;
6457 break;
6458 case 4:
6459 i.seg[i.mem_operands] = &fs;
6460 break;
6461 case 5:
6462 i.seg[i.mem_operands] = &gs;
6463 break;
6464 }
6465 }
6466 }
64a0c779 6467
a724f0f4
JB		 6468 /* Not a segment register. Check for register scaling. */
6469 else if (cur_token.code == '*')
6470 {
6471 if (!intel_parser.in_bracket)
6472 {
6473 as_bad (_("Register scaling only allowed in memory operands"));
6474 return 0;
6475 }
64a0c779 6476
a724f0f4
JB		 6477 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6478 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6479 else if (i.index_reg)
6480 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 6481
a724f0f4
JB		 6482 /* What follows must be a valid scale. */
6483 intel_match_token ('*');
6484 i.index_reg = reg;
6485 i.types[this_operand] |= BaseIndex;
64a0c779 6486
a724f0f4
JB		 6487 /* Set the scale after setting the register (otherwise,
6488 i386_scale will complain) */
6489 if (cur_token.code == '+' || cur_token.code == '-')
6490 {
6491 char *str, sign = cur_token.code;
6492 intel_match_token (cur_token.code);
6493 if (cur_token.code != T_CONST)
6494 {
6495 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6496 cur_token.str);
6497 return 0;
6498 }
6499 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6500 strcpy (str + 1, cur_token.str);
6501 *str = sign;
6502 if (!i386_scale (str))
6503 return 0;
6504 free (str);
6505 }
6506 else if (!i386_scale (cur_token.str))
64a0c779 6507 return 0;
a724f0f4
JB		 6508 intel_match_token (cur_token.code);
6509 }
64a0c779 6510
a724f0f4
JB		 6511 /* No scaling. If this is a memory operand, the register is either a
6512 base register (first occurrence) or an index register (second
6513 occurrence). */
6514 else if (intel_parser.in_bracket && !(reg->reg_type & (SReg2 | SReg3)))
6515 {
64a0c779 6516
a724f0f4
JB		 6517 if (!i.base_reg)
6518 i.base_reg = reg;
6519 else if (!i.index_reg)
6520 i.index_reg = reg;
6521 else
6522 {
6523 as_bad (_("Too many register references in memory operand"));
6524 return 0;
6525 }
64a0c779 6526
a724f0f4
JB		 6527 i.types[this_operand] |= BaseIndex;
6528 }
4a1805b1 6529
a724f0f4
JB		 6530 /* Offset modifier. Add the register to the displacement string to be
6531 parsed as an immediate expression after we're done. */
6532 else if (intel_parser.in_offset)
6533 {
6534 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6535 strcat (intel_parser.disp, reg->reg_name);
6536 }
64a0c779 6537
a724f0f4
JB		 6538 /* It's neither base nor index nor offset. */
6539 else if (!intel_parser.is_mem)
6540 {
6541 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6542 i.op[this_operand].regs = reg;
6543 i.reg_operands++;
6544 }
6545 else
6546 {
6547 as_bad (_("Invalid use of register"));
6548 return 0;
6549 }
64a0c779 6550
a724f0f4
JB		 6551 /* Since registers are not part of the displacement string (except
6552 when we're parsing offset operands), we may need to remove any
6553 preceding '+' from the displacement string. */
6554 if (*intel_parser.disp != '\0'
6555 && !intel_parser.in_offset)
6556 {
6557 char *s = intel_parser.disp;
6558 s += strlen (s) - 1;
6559 if (*s == '+')
6560 *s = '\0';
6561 }
4a1805b1 6562
a724f0f4
JB		 6563 return 1;
6564 }
6565
6566 /* e11 BYTE
6567 | WORD
6568 | DWORD
6569 | FWORD
6570 | QWORD
6571 | TBYTE
6572 | OWORD
6573 | XMMWORD */
6574 case T_BYTE:
6575 case T_WORD:
6576 case T_DWORD:
6577 case T_FWORD:
6578 case T_QWORD:
6579 case T_TBYTE:
6580 case T_XMMWORD:
6581 intel_match_token (cur_token.code);
64a0c779 6582
a724f0f4
JB		 6583 if (cur_token.code == T_PTR)
6584 return 1;
6585
6586 /* It must have been an identifier. */
6587 intel_putback_token ();
6588 cur_token.code = T_ID;
6589 /* FALLTHRU */
6590
6591 /* e11 id
6592 | constant */
6593 case T_ID:
6594 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 6595 {
6596 symbolS *symbolP;
6597
a724f0f4
JB		 6598 /* The identifier represents a memory reference only if it's not
6599 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 6600 symbolP = symbol_find(cur_token.str);
6601 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6602 intel_parser.is_mem = 1;
6603 }
a724f0f4 6604 /* FALLTHRU */
64a0c779 6605
a724f0f4
JB		 6606 case T_CONST:
6607 case '-':
6608 case '+':
6609 {
6610 char *save_str, sign = 0;
64a0c779 6611
a724f0f4
JB		 6612 /* Allow constants that start with `+' or `-'. */
6613 if (cur_token.code == '-' || cur_token.code == '+')
6614 {
6615 sign = cur_token.code;
6616 intel_match_token (cur_token.code);
6617 if (cur_token.code != T_CONST)
6618 {
6619 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6620 cur_token.str);
6621 return 0;
6622 }
6623 }
64a0c779 6624
a724f0f4
JB		 6625 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6626 strcpy (save_str + !!sign, cur_token.str);
6627 if (sign)
6628 *save_str = sign;
64a0c779 6629
a724f0f4
JB		 6630 /* Get the next token to check for register scaling. */
6631 intel_match_token (cur_token.code);
64a0c779 6632
a724f0f4
JB		 6633 /* Check if this constant is a scaling factor for an index register. */
6634 if (cur_token.code == '*')
6635 {
6636 if (intel_match_token ('*') && cur_token.code == T_REG)
6637 {
6638 const reg_entry *reg = cur_token.reg;
6639
6640 if (!intel_parser.in_bracket)
6641 {
6642 as_bad (_("Register scaling only allowed in memory operands"));
6643 return 0;
6644 }
6645
6646 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6647 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6648 else if (i.index_reg)
6649 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6650
6651 /* The constant is followed by `* reg', so it must be
6652 a valid scale. */
6653 i.index_reg = reg;
6654 i.types[this_operand] |= BaseIndex;
6655
6656 /* Set the scale after setting the register (otherwise,
6657 i386_scale will complain) */
6658 if (!i386_scale (save_str))
64a0c779 6659 return 0;
a724f0f4
JB		 6660 intel_match_token (T_REG);
6661
6662 /* Since registers are not part of the displacement
6663 string, we may need to remove any preceding '+' from
6664 the displacement string. */
6665 if (*intel_parser.disp != '\0')
6666 {
6667 char *s = intel_parser.disp;
6668 s += strlen (s) - 1;
6669 if (*s == '+')
6670 *s = '\0';
6671 }
6672
6673 free (save_str);
6674
6675 return 1;
6676 }
64a0c779 6677
a724f0f4
JB		 6678 /* The constant was not used for register scaling. Since we have
6679 already consumed the token following `*' we now need to put it
6680 back in the stream. */
64a0c779 6681 intel_putback_token ();
a724f0f4 6682 }
64a0c779 6683
a724f0f4
JB		 6684 /* Add the constant to the displacement string. */
6685 strcat (intel_parser.disp, save_str);
6686 free (save_str);
64a0c779 6687
a724f0f4
JB		 6688 return 1;
6689 }
64a0c779
DN		 6690 }
6691
64a0c779
DN		 6692 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6693 return 0;
6694}
6695
64a0c779
DN		 6696/* Match the given token against cur_token. If they match, read the next
6697 token from the operand string. */
6698static int
6699intel_match_token (code)
e5cb08ac 6700 int code;
64a0c779
DN		 6701{
6702 if (cur_token.code == code)
6703 {
6704 intel_get_token ();
6705 return 1;
6706 }
6707 else
6708 {
0477af35 6709 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 6710 return 0;
6711 }
6712}
6713
64a0c779
DN		 6714/* Read a new token from intel_parser.op_string and store it in cur_token. */
6715static void
6716intel_get_token ()
6717{
6718 char *end_op;
6719 const reg_entry *reg;
6720 struct intel_token new_token;
6721
6722 new_token.code = T_NIL;
6723 new_token.reg = NULL;
6724 new_token.str = NULL;
6725
4a1805b1 6726 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6727 cur_token to prev_token. */
6728 if (prev_token.str)
6729 free (prev_token.str);
6730
6731 prev_token = cur_token;
6732
6733 /* Skip whitespace. */
6734 while (is_space_char (*intel_parser.op_string))
6735 intel_parser.op_string++;
6736
6737 /* Return an empty token if we find nothing else on the line. */
6738 if (*intel_parser.op_string == '\0')
6739 {
6740 cur_token = new_token;
6741 return;
6742 }
6743
6744 /* The new token cannot be larger than the remainder of the operand
6745 string. */
a724f0f4 6746 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 6747 new_token.str[0] = '\0';
6748
6749 if (strchr ("0123456789", *intel_parser.op_string))
6750 {
6751 char *p = new_token.str;
6752 char *q = intel_parser.op_string;
6753 new_token.code = T_CONST;
6754
6755 /* Allow any kind of identifier char to encompass floating point and
6756 hexadecimal numbers. */
6757 while (is_identifier_char (*q))
6758 *p++ = *q++;
6759 *p = '\0';
6760
6761 /* Recognize special symbol names [0-9][bf]. */
6762 if (strlen (intel_parser.op_string) == 2
4a1805b1 6763 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6764 || intel_parser.op_string[1] == 'f'))
6765 new_token.code = T_ID;
6766 }
6767
64a0c779
DN		 6768 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6769 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6770 {
6771 new_token.code = T_REG;
6772 new_token.reg = reg;
6773
6774 if (*intel_parser.op_string == REGISTER_PREFIX)
6775 {
6776 new_token.str[0] = REGISTER_PREFIX;
6777 new_token.str[1] = '\0';
6778 }
6779
6780 strcat (new_token.str, reg->reg_name);
6781 }
6782
6783 else if (is_identifier_char (*intel_parser.op_string))
6784 {
6785 char *p = new_token.str;
6786 char *q = intel_parser.op_string;
6787
6788 /* A '.' or '$' followed by an identifier char is an identifier.
6789 Otherwise, it's operator '.' followed by an expression. */
6790 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6791 {
9306ca4a
JB		 6792 new_token.code = '.';
6793 new_token.str[0] = '.';
64a0c779
DN		 6794 new_token.str[1] = '\0';
6795 }
6796 else
6797 {
6798 while (is_identifier_char (*q) || *q == '@')
6799 *p++ = *q++;
6800 *p = '\0';
6801
9306ca4a
JB		 6802 if (strcasecmp (new_token.str, "NOT") == 0)
6803 new_token.code = '~';
6804
6805 else if (strcasecmp (new_token.str, "MOD") == 0)
6806 new_token.code = '%';
6807
6808 else if (strcasecmp (new_token.str, "AND") == 0)
6809 new_token.code = '&';
6810
6811 else if (strcasecmp (new_token.str, "OR") == 0)
6812 new_token.code = '|';
6813
6814 else if (strcasecmp (new_token.str, "XOR") == 0)
6815 new_token.code = '^';
6816
6817 else if (strcasecmp (new_token.str, "SHL") == 0)
6818 new_token.code = T_SHL;
6819
6820 else if (strcasecmp (new_token.str, "SHR") == 0)
6821 new_token.code = T_SHR;
6822
6823 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 6824 new_token.code = T_BYTE;
6825
6826 else if (strcasecmp (new_token.str, "WORD") == 0)
6827 new_token.code = T_WORD;
6828
6829 else if (strcasecmp (new_token.str, "DWORD") == 0)
6830 new_token.code = T_DWORD;
6831
9306ca4a
JB		 6832 else if (strcasecmp (new_token.str, "FWORD") == 0)
6833 new_token.code = T_FWORD;
6834
64a0c779
DN		 6835 else if (strcasecmp (new_token.str, "QWORD") == 0)
6836 new_token.code = T_QWORD;
6837
9306ca4a
JB		 6838 else if (strcasecmp (new_token.str, "TBYTE") == 0
6839 /* XXX remove (gcc still uses it) */
6840 || strcasecmp (new_token.str, "XWORD") == 0)
6841 new_token.code = T_TBYTE;
6842
6843 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6844 || strcasecmp (new_token.str, "OWORD") == 0)
6845 new_token.code = T_XMMWORD;
64a0c779
DN		 6846
6847 else if (strcasecmp (new_token.str, "PTR") == 0)
6848 new_token.code = T_PTR;
6849
6850 else if (strcasecmp (new_token.str, "SHORT") == 0)
6851 new_token.code = T_SHORT;
6852
6853 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6854 {
6855 new_token.code = T_OFFSET;
6856
6857 /* ??? This is not mentioned in the MASM grammar but gcc
6858 makes use of it with -mintel-syntax. OFFSET may be
6859 followed by FLAT: */
6860 if (strncasecmp (q, " FLAT:", 6) == 0)
6861 strcat (new_token.str, " FLAT:");
6862 }
6863
6864 /* ??? This is not mentioned in the MASM grammar. */
6865 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 6866 {
6867 new_token.code = T_OFFSET;
6868 if (*q == ':')
6869 strcat (new_token.str, ":");
6870 else
6871 as_bad (_("`:' expected"));
6872 }
64a0c779
DN		 6873
6874 else
6875 new_token.code = T_ID;
6876 }
6877 }
6878
9306ca4a
JB		 6879 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
6880 {
6881 new_token.code = *intel_parser.op_string;
6882 new_token.str[0] = *intel_parser.op_string;
6883 new_token.str[1] = '\0';
6884 }
6885
6886 else if (strchr ("<>", *intel_parser.op_string)
6887 && *intel_parser.op_string == *(intel_parser.op_string + 1))
6888 {
6889 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
6890 new_token.str[0] = *intel_parser.op_string;
6891 new_token.str[1] = *intel_parser.op_string;
6892 new_token.str[2] = '\0';
6893 }
6894
64a0c779 6895 else
0477af35 6896 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 6897
6898 intel_parser.op_string += strlen (new_token.str);
6899 cur_token = new_token;
6900}
6901
64a0c779
DN		 6902/* Put cur_token back into the token stream and make cur_token point to
6903 prev_token. */
6904static void
6905intel_putback_token ()
6906{
a724f0f4
JB		 6907 if (cur_token.code != T_NIL)
6908 {
6909 intel_parser.op_string -= strlen (cur_token.str);
6910 free (cur_token.str);
6911 }
64a0c779 6912 cur_token = prev_token;
4a1805b1 6913
64a0c779
DN		 6914 /* Forget prev_token. */
6915 prev_token.code = T_NIL;
6916 prev_token.reg = NULL;
6917 prev_token.str = NULL;
6918}
54cfded0 6919
a4447b93 6920int
54cfded0
AM		 6921tc_x86_regname_to_dw2regnum (const char *regname)
6922{
6923 unsigned int regnum;
6924 unsigned int regnames_count;
089dfecd 6925 static const char *const regnames_32[] =
54cfded0 6926 {
a4447b93
RH		 6927 "eax", "ecx", "edx", "ebx",
6928 "esp", "ebp", "esi", "edi",
089dfecd
JB		 6929 "eip", "eflags", NULL,
6930 "st0", "st1", "st2", "st3",
6931 "st4", "st5", "st6", "st7",
6932 NULL, NULL,
6933 "xmm0", "xmm1", "xmm2", "xmm3",
6934 "xmm4", "xmm5", "xmm6", "xmm7",
6935 "mm0", "mm1", "mm2", "mm3",
6936 "mm4", "mm5", "mm6", "mm7"
54cfded0 6937 };
089dfecd 6938 static const char *const regnames_64[] =
54cfded0 6939 {
089dfecd
JB		 6940 "rax", "rdx", "rcx", "rbx",
6941 "rsi", "rdi", "rbp", "rsp",
6942 "r8", "r9", "r10", "r11",
54cfded0 6943 "r12", "r13", "r14", "r15",
089dfecd
JB		 6944 "rip",
6945 "xmm0", "xmm1", "xmm2", "xmm3",
6946 "xmm4", "xmm5", "xmm6", "xmm7",
6947 "xmm8", "xmm9", "xmm10", "xmm11",
6948 "xmm12", "xmm13", "xmm14", "xmm15",
6949 "st0", "st1", "st2", "st3",
6950 "st4", "st5", "st6", "st7",
6951 "mm0", "mm1", "mm2", "mm3",
6952 "mm4", "mm5", "mm6", "mm7"
54cfded0 6953 };
089dfecd 6954 const char *const *regnames;
54cfded0
AM		 6955
6956 if (flag_code == CODE_64BIT)
6957 {
6958 regnames = regnames_64;
0cea6190 6959 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 6960 }
6961 else
6962 {
6963 regnames = regnames_32;
0cea6190 6964 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 6965 }
6966
6967 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 6968 if (regnames[regnum] != NULL
6969 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 6970 return regnum;
6971
54cfded0
AM		 6972 return -1;
6973}
6974
6975void
6976tc_x86_frame_initial_instructions (void)
6977{
a4447b93
RH		 6978 static unsigned int sp_regno;
6979
6980 if (!sp_regno)
6981 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
6982 ? "rsp" : "esp");
6983
6984 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
6985 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 6986}
d2b2c203
DJ		 6987
6988int
6989i386_elf_section_type (const char *str, size_t len)
6990{
6991 if (flag_code == CODE_64BIT
6992 && len == sizeof ("unwind") - 1
6993 && strncmp (str, "unwind", 6) == 0)
6994 return SHT_X86_64_UNWIND;
6995
6996 return -1;
6997}
bb41ade5
AM		 6998
6999#ifdef TE_PE
7000void
7001tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7002{
7003 expressionS expr;
7004
7005 expr.X_op = O_secrel;
7006 expr.X_add_symbol = symbol;
7007 expr.X_add_number = 0;
7008 emit_expr (&expr, size);
7009}
7010#endif
3b22753a
L		 7011
7012#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7013/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7014
7015int
7016x86_64_section_letter (int letter, char **ptr_msg)
7017{
7018 if (flag_code == CODE_64BIT)
7019 {
7020 if (letter == 'l')
7021 return SHF_X86_64_LARGE;
7022
7023 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7024 }
7025 else
7026 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7027 return -1;
7028}
7029
7030int
7031x86_64_section_word (char *str, size_t len)
7032{
7033 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7034 return SHF_X86_64_LARGE;
7035
7036 return -1;
7037}
7038
7039static void
7040handle_large_common (int small ATTRIBUTE_UNUSED)
7041{
7042 if (flag_code != CODE_64BIT)
7043 {
7044 s_comm_internal (0, elf_common_parse);
7045 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7046 }
7047 else
7048 {
7049 static segT lbss_section;
7050 asection *saved_com_section_ptr = elf_com_section_ptr;
7051 asection *saved_bss_section = bss_section;
7052
7053 if (lbss_section == NULL)
7054 {
7055 flagword applicable;
7056 segT seg = now_seg;
7057 subsegT subseg = now_subseg;
7058
7059 /* The .lbss section is for local .largecomm symbols. */
7060 lbss_section = subseg_new (".lbss", 0);
7061 applicable = bfd_applicable_section_flags (stdoutput);
7062 bfd_set_section_flags (stdoutput, lbss_section,
7063 applicable & SEC_ALLOC);
7064 seg_info (lbss_section)->bss = 1;
7065
7066 subseg_set (seg, subseg);
7067 }
7068
7069 elf_com_section_ptr = &_bfd_elf_large_com_section;
7070 bss_section = lbss_section;
7071
7072 s_comm_internal (0, elf_common_parse);
7073
7074 elf_com_section_ptr = saved_com_section_ptr;
7075 bss_section = saved_bss_section;
7076 }
7077}
7078#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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