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* config/tc-mips.c (s_change_section): Fix parsing. Code cleanup.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5db1645b 3 2000, 2001, 2002
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
47926f60
KH		 26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
252b5132 28
252b5132 29#include "as.h"
3882b010 30#include "safe-ctype.h"
252b5132 31#include "subsegs.h"
316e2c05 32#include "dwarf2dbg.h"
252b5132
RH		 33#include "opcode/i386.h"
34
252b5132
RH		 35#ifndef REGISTER_WARNINGS
36#define REGISTER_WARNINGS 1
37#endif
38
c3332e24 39#ifndef INFER_ADDR_PREFIX
eecb386c 40#define INFER_ADDR_PREFIX 1
c3332e24
AM		 41#endif
42
252b5132
RH		 43#ifndef SCALE1_WHEN_NO_INDEX
44/* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48#define SCALE1_WHEN_NO_INDEX 1
49#endif
50
29b0f896
AM		 51#ifdef BFD_ASSEMBLER
52#define RELOC_ENUM enum bfd_reloc_code_real
53#else
54#define RELOC_ENUM int
246fcdee 55#endif
29b0f896
AM		 56
57#ifndef DEFAULT_ARCH
58#define DEFAULT_ARCH "i386"
246fcdee 59#endif
252b5132 60
edde18a5
AM		 61#ifndef INLINE
62#if __GNUC__ >= 2
63#define INLINE __inline__
64#else
65#define INLINE
66#endif
67#endif
68
29b0f896
AM		 69static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
70static INLINE int fits_in_signed_byte PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
72static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
73static INLINE int fits_in_signed_word PARAMS ((offsetT));
74static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
75static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 76static int smallest_imm_type PARAMS ((offsetT));
77static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 78static int add_prefix PARAMS ((unsigned int));
3e73aa7c 79static void set_code_flag PARAMS ((int));
47926f60 80static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 81static void set_intel_syntax PARAMS ((int));
e413e4e9 82static void set_cpu_arch PARAMS ((int));
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 107static void output_imm PARAMS ((fragS *insn_start_frag,
108 offsetT insn_start_off));
109static void output_disp PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
29b0f896
AM		 111#ifndef I386COFF
112static void s_bss PARAMS ((int));
252b5132
RH		 113#endif
114
a847613f 115static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 116
252b5132 117/* 'md_assemble ()' gathers together information and puts it into a
47926f60 118 i386_insn. */
252b5132 119
520dc8e8
AM		 120union i386_op
121 {
122 expressionS *disps;
123 expressionS *imms;
124 const reg_entry *regs;
125 };
126
252b5132
RH		 127struct _i386_insn
128 {
47926f60 129 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 130 template tm;
131
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
134 char suffix;
135
47926f60 136 /* OPERANDS gives the number of given operands. */
252b5132
RH		 137 unsigned int operands;
138
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
47926f60 141 operands. */
252b5132
RH		 142 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
143
144 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 145 use OP[i] for the corresponding operand. */
252b5132
RH		 146 unsigned int types[MAX_OPERANDS];
147
520dc8e8
AM		 148 /* Displacement expression, immediate expression, or register for each
149 operand. */
150 union i386_op op[MAX_OPERANDS];
252b5132 151
3e73aa7c
JH		 152 /* Flags for operands. */
153 unsigned int flags[MAX_OPERANDS];
154#define Operand_PCrel 1
155
252b5132 156 /* Relocation type for operand */
f3c180ae 157 RELOC_ENUM reloc[MAX_OPERANDS];
252b5132 158
252b5132
RH		 159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry *base_reg;
162 const reg_entry *index_reg;
163 unsigned int log2_scale_factor;
164
165 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 166 explicit segment overrides are given. */
ce8a8b2f 167 const seg_entry *seg[2];
252b5132
RH		 168
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes;
172 unsigned char prefix[MAX_PREFIXES];
173
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
176
177 modrm_byte rm;
3e73aa7c 178 rex_byte rex;
252b5132
RH		 179 sib_byte sib;
180 };
181
182typedef struct _i386_insn i386_insn;
183
184/* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
186#ifdef LEX_AT
200dbde8 187const char extra_symbol_chars[] = "*%-(@[";
252b5132 188#else
200dbde8 189const char extra_symbol_chars[] = "*%-([";
252b5132
RH		 190#endif
191
29b0f896
AM		 192#if (defined (TE_I386AIX) \
193 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
194 && !defined (TE_LINUX) \
195 && !defined (TE_FreeBSD) \
196 && !defined (TE_NetBSD)))
252b5132 197/* This array holds the chars that always start a comment. If the
ce8a8b2f 198 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 199const char comment_chars[] = "#/";
200#define PREFIX_SEPARATOR '\\'
252b5132
RH		 201
202/* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 206 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
252b5132 209 '/' isn't otherwise defined. */
252b5132 210const char line_comment_chars[] = "";
29b0f896 211
252b5132 212#else
29b0f896
AM		 213/* Putting '/' here makes it impossible to use the divide operator.
214 However, we need it for compatibility with SVR4 systems. */
215const char comment_chars[] = "#";
216#define PREFIX_SEPARATOR '/'
217
252b5132
RH		 218const char line_comment_chars[] = "/";
219#endif
220
63a0b638 221const char line_separator_chars[] = ";";
252b5132 222
ce8a8b2f
AM		 223/* Chars that can be used to separate mant from exp in floating point
224 nums. */
252b5132
RH		 225const char EXP_CHARS[] = "eE";
226
ce8a8b2f
AM		 227/* Chars that mean this number is a floating point constant
228 As in 0f12.456
229 or 0d1.2345e12. */
252b5132
RH		 230const char FLT_CHARS[] = "fFdDxX";
231
ce8a8b2f 232/* Tables for lexical analysis. */
252b5132
RH		 233static char mnemonic_chars[256];
234static char register_chars[256];
235static char operand_chars[256];
236static char identifier_chars[256];
237static char digit_chars[256];
238
ce8a8b2f 239/* Lexical macros. */
252b5132
RH		 240#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
241#define is_operand_char(x) (operand_chars[(unsigned char) x])
242#define is_register_char(x) (register_chars[(unsigned char) x])
243#define is_space_char(x) ((x) == ' ')
244#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
245#define is_digit_char(x) (digit_chars[(unsigned char) x])
246
ce8a8b2f 247/* All non-digit non-letter charcters that may occur in an operand. */
252b5132
RH		 248static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
249
250/* md_assemble() always leaves the strings it's passed unaltered. To
251 effect this we maintain a stack of saved characters that we've smashed
252 with '\0's (indicating end of strings for various sub-fields of the
47926f60 253 assembler instruction). */
252b5132 254static char save_stack[32];
ce8a8b2f 255static char *save_stack_p;
252b5132
RH		 256#define END_STRING_AND_SAVE(s) \
257 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
258#define RESTORE_END_STRING(s) \
259 do { *(s) = *--save_stack_p; } while (0)
260
47926f60 261/* The instruction we're assembling. */
252b5132
RH		 262static i386_insn i;
263
264/* Possible templates for current insn. */
265static const templates *current_templates;
266
47926f60 267/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 268static expressionS disp_expressions[2], im_expressions[2];
269
47926f60
KH		 270/* Current operand we are working on. */
271static int this_operand;
252b5132 272
3e73aa7c
JH		 273/* We support four different modes. FLAG_CODE variable is used to distinguish
274 these. */
275
276enum flag_code {
277 CODE_32BIT,
278 CODE_16BIT,
279 CODE_64BIT };
f3c180ae 280#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 281
282static enum flag_code flag_code;
283static int use_rela_relocations = 0;
284
285/* The names used to print error messages. */
b77a7acd 286static const char *flag_code_names[] =
3e73aa7c
JH		 287 {
288 "32",
289 "16",
290 "64"
291 };
252b5132 292
47926f60
KH		 293/* 1 for intel syntax,
294 0 if att syntax. */
295static int intel_syntax = 0;
252b5132 296
47926f60
KH		 297/* 1 if register prefix % not required. */
298static int allow_naked_reg = 0;
252b5132 299
47926f60
KH		 300/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
301 leave, push, and pop instructions so that gcc has the same stack
302 frame as in 32 bit mode. */
303static char stackop_size = '\0';
eecb386c 304
47926f60
KH		 305/* Non-zero to quieten some warnings. */
306static int quiet_warnings = 0;
a38cf1db 307
47926f60
KH		 308/* CPU name. */
309static const char *cpu_arch_name = NULL;
a38cf1db 310
47926f60 311/* CPU feature flags. */
29b0f896 312static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 313
fddf5b5b
AM		 314/* If set, conditional jumps are not automatically promoted to handle
315 larger than a byte offset. */
316static unsigned int no_cond_jump_promotion = 0;
317
29b0f896
AM		 318/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
319symbolS *GOT_symbol;
320
252b5132 321/* Interface to relax_segment.
fddf5b5b
AM		 322 There are 3 major relax states for 386 jump insns because the
323 different types of jumps add different sizes to frags when we're
324 figuring out what sort of jump to choose to reach a given label. */
252b5132 325
47926f60 326/* Types. */
93c2a809
AM		 327#define UNCOND_JUMP 0
328#define COND_JUMP 1
329#define COND_JUMP86 2
fddf5b5b 330
47926f60 331/* Sizes. */
252b5132
RH		 332#define CODE16 1
333#define SMALL 0
29b0f896 334#define SMALL16 (SMALL | CODE16)
252b5132 335#define BIG 2
29b0f896 336#define BIG16 (BIG | CODE16)
252b5132
RH		 337
338#ifndef INLINE
339#ifdef __GNUC__
340#define INLINE __inline__
341#else
342#define INLINE
343#endif
344#endif
345
fddf5b5b
AM		 346#define ENCODE_RELAX_STATE(type, size) \
347 ((relax_substateT) (((type) << 2) | (size)))
348#define TYPE_FROM_RELAX_STATE(s) \
349 ((s) >> 2)
350#define DISP_SIZE_FROM_RELAX_STATE(s) \
351 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 352
353/* This table is used by relax_frag to promote short jumps to long
354 ones where necessary. SMALL (short) jumps may be promoted to BIG
355 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
356 don't allow a short jump in a 32 bit code segment to be promoted to
357 a 16 bit offset jump because it's slower (requires data size
358 prefix), and doesn't work, unless the destination is in the bottom
359 64k of the code segment (The top 16 bits of eip are zeroed). */
360
361const relax_typeS md_relax_table[] =
362{
24eab124
AM		 363 /* The fields are:
364 1) most positive reach of this state,
365 2) most negative reach of this state,
93c2a809 366 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 367 4) which index into the table to try if we can't fit into this one. */
252b5132 368
fddf5b5b 369 /* UNCOND_JUMP states. */
93c2a809
AM		 370 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
371 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
372 /* dword jmp adds 4 bytes to frag:
373 0 extra opcode bytes, 4 displacement bytes. */
252b5132 374 {0, 0, 4, 0},
93c2a809
AM		 375 /* word jmp adds 2 byte2 to frag:
376 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 377 {0, 0, 2, 0},
378
93c2a809
AM		 379 /* COND_JUMP states. */
380 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
381 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
382 /* dword conditionals adds 5 bytes to frag:
383 1 extra opcode byte, 4 displacement bytes. */
384 {0, 0, 5, 0},
fddf5b5b 385 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 386 1 extra opcode byte, 2 displacement bytes. */
387 {0, 0, 3, 0},
388
389 /* COND_JUMP86 states. */
390 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
392 /* dword conditionals adds 5 bytes to frag:
393 1 extra opcode byte, 4 displacement bytes. */
394 {0, 0, 5, 0},
395 /* word conditionals add 4 bytes to frag:
396 1 displacement byte and a 3 byte long branch insn. */
397 {0, 0, 4, 0}
252b5132
RH		 398};
399
e413e4e9
AM		 400static const arch_entry cpu_arch[] = {
401 {"i8086", Cpu086 },
402 {"i186", Cpu086|Cpu186 },
403 {"i286", Cpu086|Cpu186|Cpu286 },
404 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
405 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
406 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
407 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
408 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
409 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
a167610d 410 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
3e73aa7c
JH		 411 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
412 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
a167610d 413 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
e413e4e9
AM		 414 {NULL, 0 }
415};
416
29b0f896
AM		 417const pseudo_typeS md_pseudo_table[] =
418{
419#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
420 {"align", s_align_bytes, 0},
421#else
422 {"align", s_align_ptwo, 0},
423#endif
424 {"arch", set_cpu_arch, 0},
425#ifndef I386COFF
426 {"bss", s_bss, 0},
427#endif
428 {"ffloat", float_cons, 'f'},
429 {"dfloat", float_cons, 'd'},
430 {"tfloat", float_cons, 'x'},
431 {"value", cons, 2},
432 {"noopt", s_ignore, 0},
433 {"optim", s_ignore, 0},
434 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
435 {"code16", set_code_flag, CODE_16BIT},
436 {"code32", set_code_flag, CODE_32BIT},
437 {"code64", set_code_flag, CODE_64BIT},
438 {"intel_syntax", set_intel_syntax, 1},
439 {"att_syntax", set_intel_syntax, 0},
c6682705 440 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
29b0f896
AM		 441 {"loc", dwarf2_directive_loc, 0},
442 {0, 0, 0}
443};
444
445/* For interface with expression (). */
446extern char *input_line_pointer;
447
448/* Hash table for instruction mnemonic lookup. */
449static struct hash_control *op_hash;
450
451/* Hash table for register lookup. */
452static struct hash_control *reg_hash;
453\f
252b5132
RH		 454void
455i386_align_code (fragP, count)
456 fragS *fragP;
457 int count;
458{
ce8a8b2f
AM		 459 /* Various efficient no-op patterns for aligning code labels.
460 Note: Don't try to assemble the instructions in the comments.
461 0L and 0w are not legal. */
252b5132
RH		 462 static const char f32_1[] =
463 {0x90}; /* nop */
464 static const char f32_2[] =
465 {0x89,0xf6}; /* movl %esi,%esi */
466 static const char f32_3[] =
467 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
468 static const char f32_4[] =
469 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
470 static const char f32_5[] =
471 {0x90, /* nop */
472 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
473 static const char f32_6[] =
474 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
475 static const char f32_7[] =
476 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
477 static const char f32_8[] =
478 {0x90, /* nop */
479 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
480 static const char f32_9[] =
481 {0x89,0xf6, /* movl %esi,%esi */
482 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
483 static const char f32_10[] =
484 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
485 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
486 static const char f32_11[] =
487 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
488 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
489 static const char f32_12[] =
490 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
491 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
492 static const char f32_13[] =
493 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
494 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
495 static const char f32_14[] =
496 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
497 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
498 static const char f32_15[] =
499 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
500 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 501 static const char f16_3[] =
502 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 503 static const char f16_4[] =
504 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
505 static const char f16_5[] =
506 {0x90, /* nop */
507 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
508 static const char f16_6[] =
509 {0x89,0xf6, /* mov %si,%si */
510 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
511 static const char f16_7[] =
512 {0x8d,0x74,0x00, /* lea 0(%si),%si */
513 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
514 static const char f16_8[] =
515 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
516 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
517 static const char *const f32_patt[] = {
518 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
519 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
520 };
521 static const char *const f16_patt[] = {
c3332e24 522 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 523 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
524 };
525
33fef721
JH		 526 if (count <= 0 || count > 15)
527 return;
3e73aa7c 528
33fef721
JH		 529 /* The recommended way to pad 64bit code is to use NOPs preceded by
530 maximally four 0x66 prefixes. Balance the size of nops. */
531 if (flag_code == CODE_64BIT)
252b5132 532 {
33fef721
JH		 533 int i;
534 int nnops = (count + 3) / 4;
535 int len = count / nnops;
536 int remains = count - nnops * len;
537 int pos = 0;
538
539 for (i = 0; i < remains; i++)
252b5132 540 {
33fef721
JH		 541 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
542 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
543 pos += len + 1;
544 }
545 for (; i < nnops; i++)
546 {
547 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
548 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
549 pos += len;
252b5132 550 }
252b5132 551 }
33fef721
JH		 552 else
553 if (flag_code == CODE_16BIT)
554 {
555 memcpy (fragP->fr_literal + fragP->fr_fix,
556 f16_patt[count - 1], count);
557 if (count > 8)
558 /* Adjust jump offset. */
559 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
560 }
561 else
562 memcpy (fragP->fr_literal + fragP->fr_fix,
563 f32_patt[count - 1], count);
564 fragP->fr_var = count;
252b5132
RH		 565}
566
252b5132
RH		 567static INLINE unsigned int
568mode_from_disp_size (t)
569 unsigned int t;
570{
3e73aa7c 571 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 572}
573
574static INLINE int
575fits_in_signed_byte (num)
847f7ad4 576 offsetT num;
252b5132
RH		 577{
578 return (num >= -128) && (num <= 127);
47926f60 579}
252b5132
RH		 580
581static INLINE int
582fits_in_unsigned_byte (num)
847f7ad4 583 offsetT num;
252b5132
RH		 584{
585 return (num & 0xff) == num;
47926f60 586}
252b5132
RH		 587
588static INLINE int
589fits_in_unsigned_word (num)
847f7ad4 590 offsetT num;
252b5132
RH		 591{
592 return (num & 0xffff) == num;
47926f60 593}
252b5132
RH		 594
595static INLINE int
596fits_in_signed_word (num)
847f7ad4 597 offsetT num;
252b5132
RH		 598{
599 return (-32768 <= num) && (num <= 32767);
47926f60 600}
3e73aa7c
JH		 601static INLINE int
602fits_in_signed_long (num)
603 offsetT num ATTRIBUTE_UNUSED;
604{
605#ifndef BFD64
606 return 1;
607#else
608 return (!(((offsetT) -1 << 31) & num)
609 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
610#endif
611} /* fits_in_signed_long() */
612static INLINE int
613fits_in_unsigned_long (num)
614 offsetT num ATTRIBUTE_UNUSED;
615{
616#ifndef BFD64
617 return 1;
618#else
619 return (num & (((offsetT) 2 << 31) - 1)) == num;
620#endif
621} /* fits_in_unsigned_long() */
252b5132
RH		 622
623static int
624smallest_imm_type (num)
847f7ad4 625 offsetT num;
252b5132 626{
a847613f 627 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 628 {
629 /* This code is disabled on the 486 because all the Imm1 forms
630 in the opcode table are slower on the i486. They're the
631 versions with the implicitly specified single-position
632 displacement, which has another syntax if you really want to
633 use that form. */
634 if (num == 1)
3e73aa7c 635 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 636 }
252b5132 637 return (fits_in_signed_byte (num)
3e73aa7c 638 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 639 : fits_in_unsigned_byte (num)
3e73aa7c 640 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 641 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 642 ? (Imm16 | Imm32 | Imm32S | Imm64)
643 : fits_in_signed_long (num)
644 ? (Imm32 | Imm32S | Imm64)
645 : fits_in_unsigned_long (num)
646 ? (Imm32 | Imm64)
647 : Imm64);
47926f60 648}
252b5132 649
847f7ad4
AM		 650static offsetT
651offset_in_range (val, size)
652 offsetT val;
653 int size;
654{
508866be 655 addressT mask;
ba2adb93 656
847f7ad4
AM		 657 switch (size)
658 {
508866be
L		 659 case 1: mask = ((addressT) 1 << 8) - 1; break;
660 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 661 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 662#ifdef BFD64
663 case 8: mask = ((addressT) 2 << 63) - 1; break;
664#endif
47926f60 665 default: abort ();
847f7ad4
AM		 666 }
667
ba2adb93 668 /* If BFD64, sign extend val. */
3e73aa7c
JH		 669 if (!use_rela_relocations)
670 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
671 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 672
47926f60 673 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 674 {
675 char buf1[40], buf2[40];
676
677 sprint_value (buf1, val);
678 sprint_value (buf2, val & mask);
679 as_warn (_("%s shortened to %s"), buf1, buf2);
680 }
681 return val & mask;
682}
683
252b5132
RH		 684/* Returns 0 if attempting to add a prefix where one from the same
685 class already exists, 1 if non rep/repne added, 2 if rep/repne
686 added. */
687static int
688add_prefix (prefix)
689 unsigned int prefix;
690{
691 int ret = 1;
692 int q;
693
29b0f896
AM		 694 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
695 && flag_code == CODE_64BIT)
3e73aa7c
JH		 696 q = REX_PREFIX;
697 else
698 switch (prefix)
699 {
700 default:
701 abort ();
702
703 case CS_PREFIX_OPCODE:
704 case DS_PREFIX_OPCODE:
705 case ES_PREFIX_OPCODE:
706 case FS_PREFIX_OPCODE:
707 case GS_PREFIX_OPCODE:
708 case SS_PREFIX_OPCODE:
709 q = SEG_PREFIX;
710 break;
252b5132 711
3e73aa7c
JH		 712 case REPNE_PREFIX_OPCODE:
713 case REPE_PREFIX_OPCODE:
714 ret = 2;
715 /* fall thru */
716 case LOCK_PREFIX_OPCODE:
717 q = LOCKREP_PREFIX;
718 break;
252b5132 719
3e73aa7c
JH		 720 case FWAIT_OPCODE:
721 q = WAIT_PREFIX;
722 break;
252b5132 723
3e73aa7c
JH		 724 case ADDR_PREFIX_OPCODE:
725 q = ADDR_PREFIX;
726 break;
252b5132 727
3e73aa7c
JH		 728 case DATA_PREFIX_OPCODE:
729 q = DATA_PREFIX;
730 break;
731 }
252b5132 732
29b0f896 733 if (i.prefix[q] != 0)
252b5132
RH		 734 {
735 as_bad (_("same type of prefix used twice"));
736 return 0;
737 }
738
739 i.prefixes += 1;
740 i.prefix[q] = prefix;
741 return ret;
742}
743
744static void
3e73aa7c 745set_code_flag (value)
e5cb08ac 746 int value;
eecb386c 747{
3e73aa7c
JH		 748 flag_code = value;
749 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
750 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
751 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
752 {
753 as_bad (_("64bit mode not supported on this CPU."));
754 }
755 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
756 {
757 as_bad (_("32bit mode not supported on this CPU."));
758 }
eecb386c
AM		 759 stackop_size = '\0';
760}
761
762static void
3e73aa7c
JH		 763set_16bit_gcc_code_flag (new_code_flag)
764 int new_code_flag;
252b5132 765{
3e73aa7c
JH		 766 flag_code = new_code_flag;
767 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
768 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
769 stackop_size = 'l';
252b5132
RH		 770}
771
772static void
773set_intel_syntax (syntax_flag)
eecb386c 774 int syntax_flag;
252b5132
RH		 775{
776 /* Find out if register prefixing is specified. */
777 int ask_naked_reg = 0;
778
779 SKIP_WHITESPACE ();
29b0f896 780 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 781 {
782 char *string = input_line_pointer;
783 int e = get_symbol_end ();
784
47926f60 785 if (strcmp (string, "prefix") == 0)
252b5132 786 ask_naked_reg = 1;
47926f60 787 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 788 ask_naked_reg = -1;
789 else
d0b47220 790 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 791 *input_line_pointer = e;
792 }
793 demand_empty_rest_of_line ();
c3332e24 794
252b5132
RH		 795 intel_syntax = syntax_flag;
796
797 if (ask_naked_reg == 0)
798 {
799#ifdef BFD_ASSEMBLER
800 allow_naked_reg = (intel_syntax
24eab124 801 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132 802#else
47926f60
KH		 803 /* Conservative default. */
804 allow_naked_reg = 0;
252b5132
RH		 805#endif
806 }
807 else
808 allow_naked_reg = (ask_naked_reg < 0);
809}
810
e413e4e9
AM		 811static void
812set_cpu_arch (dummy)
47926f60 813 int dummy ATTRIBUTE_UNUSED;
e413e4e9 814{
47926f60 815 SKIP_WHITESPACE ();
e413e4e9 816
29b0f896 817 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 818 {
819 char *string = input_line_pointer;
820 int e = get_symbol_end ();
821 int i;
822
823 for (i = 0; cpu_arch[i].name; i++)
824 {
825 if (strcmp (string, cpu_arch[i].name) == 0)
826 {
827 cpu_arch_name = cpu_arch[i].name;
fddf5b5b
AM		 828 cpu_arch_flags = (cpu_arch[i].flags
829 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
e413e4e9
AM		 830 break;
831 }
832 }
833 if (!cpu_arch[i].name)
834 as_bad (_("no such architecture: `%s'"), string);
835
836 *input_line_pointer = e;
837 }
838 else
839 as_bad (_("missing cpu architecture"));
840
fddf5b5b
AM		 841 no_cond_jump_promotion = 0;
842 if (*input_line_pointer == ','
29b0f896 843 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 844 {
845 char *string = ++input_line_pointer;
846 int e = get_symbol_end ();
847
848 if (strcmp (string, "nojumps") == 0)
849 no_cond_jump_promotion = 1;
850 else if (strcmp (string, "jumps") == 0)
851 ;
852 else
853 as_bad (_("no such architecture modifier: `%s'"), string);
854
855 *input_line_pointer = e;
856 }
857
e413e4e9
AM		 858 demand_empty_rest_of_line ();
859}
860
b9d79e03
JH		 861#ifdef BFD_ASSEMBLER
862unsigned long
863i386_mach ()
864{
865 if (!strcmp (default_arch, "x86_64"))
866 return bfd_mach_x86_64;
867 else if (!strcmp (default_arch, "i386"))
868 return bfd_mach_i386_i386;
869 else
870 as_fatal (_("Unknown architecture"));
871}
872#endif
873\f
252b5132
RH		 874void
875md_begin ()
876{
877 const char *hash_err;
878
47926f60 879 /* Initialize op_hash hash table. */
252b5132
RH		 880 op_hash = hash_new ();
881
882 {
29b0f896
AM		 883 const template *optab;
884 templates *core_optab;
252b5132 885
47926f60
KH		 886 /* Setup for loop. */
887 optab = i386_optab;
252b5132
RH		 888 core_optab = (templates *) xmalloc (sizeof (templates));
889 core_optab->start = optab;
890
891 while (1)
892 {
893 ++optab;
894 if (optab->name == NULL
895 || strcmp (optab->name, (optab - 1)->name) != 0)
896 {
897 /* different name --> ship out current template list;
47926f60 898 add to hash table; & begin anew. */
252b5132
RH		 899 core_optab->end = optab;
900 hash_err = hash_insert (op_hash,
901 (optab - 1)->name,
902 (PTR) core_optab);
903 if (hash_err)
904 {
252b5132
RH		 905 as_fatal (_("Internal Error: Can't hash %s: %s"),
906 (optab - 1)->name,
907 hash_err);
908 }
909 if (optab->name == NULL)
910 break;
911 core_optab = (templates *) xmalloc (sizeof (templates));
912 core_optab->start = optab;
913 }
914 }
915 }
916
47926f60 917 /* Initialize reg_hash hash table. */
252b5132
RH		 918 reg_hash = hash_new ();
919 {
29b0f896 920 const reg_entry *regtab;
252b5132
RH		 921
922 for (regtab = i386_regtab;
923 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
924 regtab++)
925 {
926 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
927 if (hash_err)
3e73aa7c
JH		 928 as_fatal (_("Internal Error: Can't hash %s: %s"),
929 regtab->reg_name,
930 hash_err);
252b5132
RH		 931 }
932 }
933
47926f60 934 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 935 {
29b0f896
AM		 936 int c;
937 char *p;
252b5132
RH		 938
939 for (c = 0; c < 256; c++)
940 {
3882b010 941 if (ISDIGIT (c))
252b5132
RH		 942 {
943 digit_chars[c] = c;
944 mnemonic_chars[c] = c;
945 register_chars[c] = c;
946 operand_chars[c] = c;
947 }
3882b010 948 else if (ISLOWER (c))
252b5132
RH		 949 {
950 mnemonic_chars[c] = c;
951 register_chars[c] = c;
952 operand_chars[c] = c;
953 }
3882b010 954 else if (ISUPPER (c))
252b5132 955 {
3882b010 956 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 957 register_chars[c] = mnemonic_chars[c];
958 operand_chars[c] = c;
959 }
960
3882b010 961 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 962 identifier_chars[c] = c;
963 else if (c >= 128)
964 {
965 identifier_chars[c] = c;
966 operand_chars[c] = c;
967 }
968 }
969
970#ifdef LEX_AT
971 identifier_chars['@'] = '@';
972#endif
252b5132
RH		 973 digit_chars['-'] = '-';
974 identifier_chars['_'] = '_';
975 identifier_chars['.'] = '.';
976
977 for (p = operand_special_chars; *p != '\0'; p++)
978 operand_chars[(unsigned char) *p] = *p;
979 }
980
981#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
982 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
983 {
984 record_alignment (text_section, 2);
985 record_alignment (data_section, 2);
986 record_alignment (bss_section, 2);
987 }
988#endif
989}
990
991void
992i386_print_statistics (file)
993 FILE *file;
994{
995 hash_print_statistics (file, "i386 opcode", op_hash);
996 hash_print_statistics (file, "i386 register", reg_hash);
997}
998\f
252b5132
RH		 999#ifdef DEBUG386
1000
ce8a8b2f 1001/* Debugging routines for md_assemble. */
252b5132
RH		 1002static void pi PARAMS ((char *, i386_insn *));
1003static void pte PARAMS ((template *));
1004static void pt PARAMS ((unsigned int));
1005static void pe PARAMS ((expressionS *));
1006static void ps PARAMS ((symbolS *));
1007
1008static void
1009pi (line, x)
1010 char *line;
1011 i386_insn *x;
1012{
09f131f2 1013 unsigned int i;
252b5132
RH		 1014
1015 fprintf (stdout, "%s: template ", line);
1016 pte (&x->tm);
09f131f2
JH		 1017 fprintf (stdout, " address: base %s index %s scale %x\n",
1018 x->base_reg ? x->base_reg->reg_name : "none",
1019 x->index_reg ? x->index_reg->reg_name : "none",
1020 x->log2_scale_factor);
1021 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1022 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1023 fprintf (stdout, " sib: base %x index %x scale %x\n",
1024 x->sib.base, x->sib.index, x->sib.scale);
1025 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1026 (x->rex & REX_MODE64) != 0,
1027 (x->rex & REX_EXTX) != 0,
1028 (x->rex & REX_EXTY) != 0,
1029 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1030 for (i = 0; i < x->operands; i++)
1031 {
1032 fprintf (stdout, " #%d: ", i + 1);
1033 pt (x->types[i]);
1034 fprintf (stdout, "\n");
1035 if (x->types[i]
3f4438ab 1036 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1037 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1038 if (x->types[i] & Imm)
520dc8e8 1039 pe (x->op[i].imms);
252b5132 1040 if (x->types[i] & Disp)
520dc8e8 1041 pe (x->op[i].disps);
252b5132
RH		 1042 }
1043}
1044
1045static void
1046pte (t)
1047 template *t;
1048{
09f131f2 1049 unsigned int i;
252b5132 1050 fprintf (stdout, " %d operands ", t->operands);
47926f60 1051 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1052 if (t->extension_opcode != None)
1053 fprintf (stdout, "ext %x ", t->extension_opcode);
1054 if (t->opcode_modifier & D)
1055 fprintf (stdout, "D");
1056 if (t->opcode_modifier & W)
1057 fprintf (stdout, "W");
1058 fprintf (stdout, "\n");
1059 for (i = 0; i < t->operands; i++)
1060 {
1061 fprintf (stdout, " #%d type ", i + 1);
1062 pt (t->operand_types[i]);
1063 fprintf (stdout, "\n");
1064 }
1065}
1066
1067static void
1068pe (e)
1069 expressionS *e;
1070{
24eab124 1071 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1072 fprintf (stdout, " add_number %ld (%lx)\n",
1073 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1074 if (e->X_add_symbol)
1075 {
1076 fprintf (stdout, " add_symbol ");
1077 ps (e->X_add_symbol);
1078 fprintf (stdout, "\n");
1079 }
1080 if (e->X_op_symbol)
1081 {
1082 fprintf (stdout, " op_symbol ");
1083 ps (e->X_op_symbol);
1084 fprintf (stdout, "\n");
1085 }
1086}
1087
1088static void
1089ps (s)
1090 symbolS *s;
1091{
1092 fprintf (stdout, "%s type %s%s",
1093 S_GET_NAME (s),
1094 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1095 segment_name (S_GET_SEGMENT (s)));
1096}
1097
1098struct type_name
1099 {
1100 unsigned int mask;
1101 char *tname;
1102 }
1103
29b0f896 1104static const type_names[] =
252b5132
RH		 1105{
1106 { Reg8, "r8" },
1107 { Reg16, "r16" },
1108 { Reg32, "r32" },
09f131f2 1109 { Reg64, "r64" },
252b5132
RH		 1110 { Imm8, "i8" },
1111 { Imm8S, "i8s" },
1112 { Imm16, "i16" },
1113 { Imm32, "i32" },
09f131f2
JH		 1114 { Imm32S, "i32s" },
1115 { Imm64, "i64" },
252b5132
RH		 1116 { Imm1, "i1" },
1117 { BaseIndex, "BaseIndex" },
1118 { Disp8, "d8" },
1119 { Disp16, "d16" },
1120 { Disp32, "d32" },
09f131f2
JH		 1121 { Disp32S, "d32s" },
1122 { Disp64, "d64" },
252b5132
RH		 1123 { InOutPortReg, "InOutPortReg" },
1124 { ShiftCount, "ShiftCount" },
1125 { Control, "control reg" },
1126 { Test, "test reg" },
1127 { Debug, "debug reg" },
1128 { FloatReg, "FReg" },
1129 { FloatAcc, "FAcc" },
1130 { SReg2, "SReg2" },
1131 { SReg3, "SReg3" },
1132 { Acc, "Acc" },
1133 { JumpAbsolute, "Jump Absolute" },
1134 { RegMMX, "rMMX" },
3f4438ab 1135 { RegXMM, "rXMM" },
252b5132
RH		 1136 { EsSeg, "es" },
1137 { 0, "" }
1138};
1139
1140static void
1141pt (t)
1142 unsigned int t;
1143{
29b0f896 1144 const struct type_name *ty;
252b5132 1145
09f131f2
JH		 1146 for (ty = type_names; ty->mask; ty++)
1147 if (t & ty->mask)
1148 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1149 fflush (stdout);
1150}
1151
1152#endif /* DEBUG386 */
1153\f
252b5132 1154#ifdef BFD_ASSEMBLER
29b0f896
AM		 1155static bfd_reloc_code_real_type reloc
1156 PARAMS ((int, int, int, bfd_reloc_code_real_type));
252b5132
RH		 1157
1158static bfd_reloc_code_real_type
3e73aa7c 1159reloc (size, pcrel, sign, other)
252b5132
RH		 1160 int size;
1161 int pcrel;
3e73aa7c 1162 int sign;
252b5132
RH		 1163 bfd_reloc_code_real_type other;
1164{
47926f60
KH		 1165 if (other != NO_RELOC)
1166 return other;
252b5132
RH		 1167
1168 if (pcrel)
1169 {
3e73aa7c 1170 if (!sign)
e5cb08ac 1171 as_bad (_("There are no unsigned pc-relative relocations"));
252b5132
RH		 1172 switch (size)
1173 {
1174 case 1: return BFD_RELOC_8_PCREL;
1175 case 2: return BFD_RELOC_16_PCREL;
1176 case 4: return BFD_RELOC_32_PCREL;
1177 }
d0b47220 1178 as_bad (_("can not do %d byte pc-relative relocation"), size);
252b5132
RH		 1179 }
1180 else
1181 {
3e73aa7c 1182 if (sign)
e5cb08ac 1183 switch (size)
3e73aa7c
JH		 1184 {
1185 case 4: return BFD_RELOC_X86_64_32S;
1186 }
1187 else
1188 switch (size)
1189 {
1190 case 1: return BFD_RELOC_8;
1191 case 2: return BFD_RELOC_16;
1192 case 4: return BFD_RELOC_32;
1193 case 8: return BFD_RELOC_64;
1194 }
1195 as_bad (_("can not do %s %d byte relocation"),
1196 sign ? "signed" : "unsigned", size);
252b5132
RH		 1197 }
1198
bfb32b52 1199 abort ();
252b5132
RH		 1200 return BFD_RELOC_NONE;
1201}
1202
47926f60
KH		 1203/* Here we decide which fixups can be adjusted to make them relative to
1204 the beginning of the section instead of the symbol. Basically we need
1205 to make sure that the dynamic relocations are done correctly, so in
1206 some cases we force the original symbol to be used. */
1207
252b5132 1208int
c0c949c7 1209tc_i386_fix_adjustable (fixP)
31312f95 1210 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1211{
6d249963 1212#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 1213 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
1214 return 1;
1215
a161fe53
AM		 1216 /* Don't adjust pc-relative references to merge sections in 64-bit
1217 mode. */
1218 if (use_rela_relocations
1219 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1220 && fixP->fx_pcrel)
252b5132 1221 return 0;
31312f95 1222
ce8a8b2f 1223 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1224 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1225 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1226 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1227 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1228 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1229 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1230 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1231 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1232 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1233 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1234 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
252b5132
RH		 1236 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1237 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1238 return 0;
31312f95 1239#endif
252b5132
RH		 1240 return 1;
1241}
1242#else
ec56dfb4 1243#define reloc(SIZE,PCREL,SIGN,OTHER) 0
c6682705 1244#define BFD_RELOC_8 0
ec56dfb4
L		 1245#define BFD_RELOC_16 0
1246#define BFD_RELOC_32 0
c6682705 1247#define BFD_RELOC_8_PCREL 0
ec56dfb4
L		 1248#define BFD_RELOC_16_PCREL 0
1249#define BFD_RELOC_32_PCREL 0
1250#define BFD_RELOC_386_PLT32 0
1251#define BFD_RELOC_386_GOT32 0
1252#define BFD_RELOC_386_GOTOFF 0
13ae64f3
JJ		 1253#define BFD_RELOC_386_TLS_GD 0
1254#define BFD_RELOC_386_TLS_LDM 0
1255#define BFD_RELOC_386_TLS_LDO_32 0
1256#define BFD_RELOC_386_TLS_IE_32 0
1257#define BFD_RELOC_386_TLS_LE_32 0
1258#define BFD_RELOC_386_TLS_LE 0
ec56dfb4
L		 1259#define BFD_RELOC_X86_64_PLT32 0
1260#define BFD_RELOC_X86_64_GOT32 0
1261#define BFD_RELOC_X86_64_GOTPCREL 0
252b5132
RH		 1262#endif
1263
29b0f896 1264static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1265
1266static int
252b5132 1267intel_float_operand (mnemonic)
29b0f896 1268 const char *mnemonic;
252b5132 1269{
47926f60 1270 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
cc5ca5ce 1271 return 2;
252b5132
RH		 1272
1273 if (mnemonic[0] == 'f')
1274 return 1;
1275
1276 return 0;
1277}
1278
1279/* This is the guts of the machine-dependent assembler. LINE points to a
1280 machine dependent instruction. This function is supposed to emit
1281 the frags/bytes it assembles to. */
1282
1283void
1284md_assemble (line)
1285 char *line;
1286{
252b5132 1287 int j;
252b5132
RH		 1288 char mnemonic[MAX_MNEM_SIZE];
1289
47926f60 1290 /* Initialize globals. */
252b5132
RH		 1291 memset (&i, '\0', sizeof (i));
1292 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1293 i.reloc[j] = NO_RELOC;
252b5132
RH		 1294 memset (disp_expressions, '\0', sizeof (disp_expressions));
1295 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1296 save_stack_p = save_stack;
252b5132
RH		 1297
1298 /* First parse an instruction mnemonic & call i386_operand for the operands.
1299 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1300 start of a (possibly prefixed) mnemonic. */
252b5132 1301
29b0f896
AM		 1302 line = parse_insn (line, mnemonic);
1303 if (line == NULL)
1304 return;
252b5132 1305
29b0f896
AM		 1306 line = parse_operands (line, mnemonic);
1307 if (line == NULL)
1308 return;
252b5132 1309
29b0f896
AM		 1310 /* Now we've parsed the mnemonic into a set of templates, and have the
1311 operands at hand. */
1312
1313 /* All intel opcodes have reversed operands except for "bound" and
1314 "enter". We also don't reverse intersegment "jmp" and "call"
1315 instructions with 2 immediate operands so that the immediate segment
1316 precedes the offset, as it does when in AT&T mode. "enter" and the
1317 intersegment "jmp" and "call" instructions are the only ones that
1318 have two immediate operands. */
1319 if (intel_syntax && i.operands > 1
1320 && (strcmp (mnemonic, "bound") != 0)
1321 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1322 swap_operands ();
1323
1324 if (i.imm_operands)
1325 optimize_imm ();
1326
1327 if (i.disp_operands)
1328 optimize_disp ();
1329
1330 /* Next, we find a template that matches the given insn,
1331 making sure the overlap of the given operands types is consistent
1332 with the template operand types. */
252b5132 1333
29b0f896
AM		 1334 if (!match_template ())
1335 return;
252b5132 1336
cd61ebfe
AM		 1337 if (intel_syntax)
1338 {
1339 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1340 if (SYSV386_COMPAT
1341 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1342 i.tm.base_opcode ^= FloatR;
1343
1344 /* Zap movzx and movsx suffix. The suffix may have been set from
1345 "word ptr" or "byte ptr" on the source operand, but we'll use
1346 the suffix later to choose the destination register. */
1347 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1348 i.suffix = 0;
1349 }
24eab124 1350
29b0f896
AM		 1351 if (i.tm.opcode_modifier & FWait)
1352 if (!add_prefix (FWAIT_OPCODE))
1353 return;
252b5132 1354
29b0f896
AM		 1355 /* Check string instruction segment overrides. */
1356 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1357 {
1358 if (!check_string ())
5dd0794d 1359 return;
29b0f896 1360 }
5dd0794d 1361
29b0f896
AM		 1362 if (!process_suffix ())
1363 return;
e413e4e9 1364
29b0f896
AM		 1365 /* Make still unresolved immediate matches conform to size of immediate
1366 given in i.suffix. */
1367 if (!finalize_imm ())
1368 return;
252b5132 1369
29b0f896
AM		 1370 if (i.types[0] & Imm1)
1371 i.imm_operands = 0; /* kludge for shift insns. */
1372 if (i.types[0] & ImplicitRegister)
1373 i.reg_operands--;
1374 if (i.types[1] & ImplicitRegister)
1375 i.reg_operands--;
1376 if (i.types[2] & ImplicitRegister)
1377 i.reg_operands--;
252b5132 1378
29b0f896
AM		 1379 if (i.tm.opcode_modifier & ImmExt)
1380 {
1381 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1382 opcode suffix which is coded in the same place as an 8-bit
1383 immediate field would be. Here we fake an 8-bit immediate
1384 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1385
29b0f896 1386 expressionS *exp;
252b5132 1387
29b0f896 1388 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1389
29b0f896
AM		 1390 exp = &im_expressions[i.imm_operands++];
1391 i.op[i.operands].imms = exp;
1392 i.types[i.operands++] = Imm8;
1393 exp->X_op = O_constant;
1394 exp->X_add_number = i.tm.extension_opcode;
1395 i.tm.extension_opcode = None;
1396 }
252b5132 1397
29b0f896
AM		 1398 /* For insns with operands there are more diddles to do to the opcode. */
1399 if (i.operands)
1400 {
1401 if (!process_operands ())
1402 return;
1403 }
1404 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1405 {
1406 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1407 as_warn (_("translating to `%sp'"), i.tm.name);
1408 }
252b5132 1409
29b0f896
AM		 1410 /* Handle conversion of 'int $3' --> special int3 insn. */
1411 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1412 {
1413 i.tm.base_opcode = INT3_OPCODE;
1414 i.imm_operands = 0;
1415 }
252b5132 1416
29b0f896
AM		 1417 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1418 && i.op[0].disps->X_op == O_constant)
1419 {
1420 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1421 the absolute address given by the constant. Since ix86 jumps and
1422 calls are pc relative, we need to generate a reloc. */
1423 i.op[0].disps->X_add_symbol = &abs_symbol;
1424 i.op[0].disps->X_op = O_symbol;
1425 }
252b5132 1426
29b0f896
AM		 1427 if ((i.tm.opcode_modifier & Rex64) != 0)
1428 i.rex |= REX_MODE64;
252b5132 1429
29b0f896
AM		 1430 /* For 8 bit registers we need an empty rex prefix. Also if the
1431 instruction already has a prefix, we need to convert old
1432 registers to new ones. */
773f551c 1433
29b0f896
AM		 1434 if (((i.types[0] & Reg8) != 0
1435 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1436 || ((i.types[1] & Reg8) != 0
1437 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1438 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1439 && i.rex != 0))
1440 {
1441 int x;
726c5dcd 1442
29b0f896
AM		 1443 i.rex |= REX_OPCODE;
1444 for (x = 0; x < 2; x++)
1445 {
1446 /* Look for 8 bit operand that uses old registers. */
1447 if ((i.types[x] & Reg8) != 0
1448 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1449 {
29b0f896
AM		 1450 /* In case it is "hi" register, give up. */
1451 if (i.op[x].regs->reg_num > 3)
1452 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1453 i.op[x].regs->reg_name);
773f551c 1454
29b0f896
AM		 1455 /* Otherwise it is equivalent to the extended register.
1456 Since the encoding doesn't change this is merely
1457 cosmetic cleanup for debug output. */
1458
1459 i.op[x].regs = i.op[x].regs + 8;
773f551c 1460 }
29b0f896
AM		 1461 }
1462 }
773f551c 1463
29b0f896
AM		 1464 if (i.rex != 0)
1465 add_prefix (REX_OPCODE | i.rex);
1466
1467 /* We are ready to output the insn. */
1468 output_insn ();
1469}
1470
1471static char *
1472parse_insn (line, mnemonic)
1473 char *line;
1474 char *mnemonic;
1475{
1476 char *l = line;
1477 char *token_start = l;
1478 char *mnem_p;
1479
1480 /* Non-zero if we found a prefix only acceptable with string insns. */
1481 const char *expecting_string_instruction = NULL;
45288df1 1482
29b0f896
AM		 1483 while (1)
1484 {
1485 mnem_p = mnemonic;
1486 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1487 {
1488 mnem_p++;
1489 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1490 {
29b0f896
AM		 1491 as_bad (_("no such instruction: `%s'"), token_start);
1492 return NULL;
1493 }
1494 l++;
1495 }
1496 if (!is_space_char (*l)
1497 && *l != END_OF_INSN
1498 && *l != PREFIX_SEPARATOR
1499 && *l != ',')
1500 {
1501 as_bad (_("invalid character %s in mnemonic"),
1502 output_invalid (*l));
1503 return NULL;
1504 }
1505 if (token_start == l)
1506 {
1507 if (*l == PREFIX_SEPARATOR)
1508 as_bad (_("expecting prefix; got nothing"));
1509 else
1510 as_bad (_("expecting mnemonic; got nothing"));
1511 return NULL;
1512 }
45288df1 1513
29b0f896
AM		 1514 /* Look up instruction (or prefix) via hash table. */
1515 current_templates = hash_find (op_hash, mnemonic);
47926f60 1516
29b0f896
AM		 1517 if (*l != END_OF_INSN
1518 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1519 && current_templates
1520 && (current_templates->start->opcode_modifier & IsPrefix))
1521 {
1522 /* If we are in 16-bit mode, do not allow addr16 or data16.
1523 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1524 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1525 && flag_code != CODE_64BIT
1526 && (((current_templates->start->opcode_modifier & Size32) != 0)
1527 ^ (flag_code == CODE_16BIT)))
1528 {
1529 as_bad (_("redundant %s prefix"),
1530 current_templates->start->name);
1531 return NULL;
45288df1 1532 }
29b0f896
AM		 1533 /* Add prefix, checking for repeated prefixes. */
1534 switch (add_prefix (current_templates->start->base_opcode))
1535 {
1536 case 0:
1537 return NULL;
1538 case 2:
1539 expecting_string_instruction = current_templates->start->name;
1540 break;
1541 }
1542 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1543 token_start = ++l;
1544 }
1545 else
1546 break;
1547 }
45288df1 1548
29b0f896
AM		 1549 if (!current_templates)
1550 {
1551 /* See if we can get a match by trimming off a suffix. */
1552 switch (mnem_p[-1])
1553 {
1554 case WORD_MNEM_SUFFIX:
1555 case BYTE_MNEM_SUFFIX:
1556 case QWORD_MNEM_SUFFIX:
1557 i.suffix = mnem_p[-1];
1558 mnem_p[-1] = '\0';
1559 current_templates = hash_find (op_hash, mnemonic);
1560 break;
1561 case SHORT_MNEM_SUFFIX:
1562 case LONG_MNEM_SUFFIX:
1563 if (!intel_syntax)
1564 {
1565 i.suffix = mnem_p[-1];
1566 mnem_p[-1] = '\0';
1567 current_templates = hash_find (op_hash, mnemonic);
1568 }
1569 break;
252b5132 1570
29b0f896
AM		 1571 /* Intel Syntax. */
1572 case 'd':
1573 if (intel_syntax)
1574 {
1575 if (intel_float_operand (mnemonic))
1576 i.suffix = SHORT_MNEM_SUFFIX;
1577 else
1578 i.suffix = LONG_MNEM_SUFFIX;
1579 mnem_p[-1] = '\0';
1580 current_templates = hash_find (op_hash, mnemonic);
1581 }
1582 break;
1583 }
1584 if (!current_templates)
1585 {
1586 as_bad (_("no such instruction: `%s'"), token_start);
1587 return NULL;
1588 }
1589 }
252b5132 1590
29b0f896
AM		 1591 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1592 {
1593 /* Check for a branch hint. We allow ",pt" and ",pn" for
1594 predict taken and predict not taken respectively.
1595 I'm not sure that branch hints actually do anything on loop
1596 and jcxz insns (JumpByte) for current Pentium4 chips. They
1597 may work in the future and it doesn't hurt to accept them
1598 now. */
1599 if (l[0] == ',' && l[1] == 'p')
1600 {
1601 if (l[2] == 't')
1602 {
1603 if (!add_prefix (DS_PREFIX_OPCODE))
1604 return NULL;
1605 l += 3;
1606 }
1607 else if (l[2] == 'n')
1608 {
1609 if (!add_prefix (CS_PREFIX_OPCODE))
1610 return NULL;
1611 l += 3;
1612 }
1613 }
1614 }
1615 /* Any other comma loses. */
1616 if (*l == ',')
1617 {
1618 as_bad (_("invalid character %s in mnemonic"),
1619 output_invalid (*l));
1620 return NULL;
1621 }
252b5132 1622
29b0f896
AM		 1623 /* Check if instruction is supported on specified architecture. */
1624 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1625 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1626 {
1627 as_warn (_("`%s' is not supported on `%s'"),
1628 current_templates->start->name, cpu_arch_name);
1629 }
1630 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1631 {
1632 as_warn (_("use .code16 to ensure correct addressing mode"));
1633 }
252b5132 1634
29b0f896
AM		 1635 /* Check for rep/repne without a string instruction. */
1636 if (expecting_string_instruction
1637 && !(current_templates->start->opcode_modifier & IsString))
1638 {
1639 as_bad (_("expecting string instruction after `%s'"),
1640 expecting_string_instruction);
1641 return NULL;
1642 }
252b5132 1643
29b0f896
AM		 1644 return l;
1645}
252b5132 1646
29b0f896
AM		 1647static char *
1648parse_operands (l, mnemonic)
1649 char *l;
1650 const char *mnemonic;
1651{
1652 char *token_start;
3138f287 1653
29b0f896
AM		 1654 /* 1 if operand is pending after ','. */
1655 unsigned int expecting_operand = 0;
252b5132 1656
29b0f896
AM		 1657 /* Non-zero if operand parens not balanced. */
1658 unsigned int paren_not_balanced;
1659
1660 while (*l != END_OF_INSN)
1661 {
1662 /* Skip optional white space before operand. */
1663 if (is_space_char (*l))
1664 ++l;
1665 if (!is_operand_char (*l) && *l != END_OF_INSN)
1666 {
1667 as_bad (_("invalid character %s before operand %d"),
1668 output_invalid (*l),
1669 i.operands + 1);
1670 return NULL;
1671 }
1672 token_start = l; /* after white space */
1673 paren_not_balanced = 0;
1674 while (paren_not_balanced || *l != ',')
1675 {
1676 if (*l == END_OF_INSN)
1677 {
1678 if (paren_not_balanced)
1679 {
1680 if (!intel_syntax)
1681 as_bad (_("unbalanced parenthesis in operand %d."),
1682 i.operands + 1);
1683 else
1684 as_bad (_("unbalanced brackets in operand %d."),
1685 i.operands + 1);
1686 return NULL;
1687 }
1688 else
1689 break; /* we are done */
1690 }
1691 else if (!is_operand_char (*l) && !is_space_char (*l))
1692 {
1693 as_bad (_("invalid character %s in operand %d"),
1694 output_invalid (*l),
1695 i.operands + 1);
1696 return NULL;
1697 }
1698 if (!intel_syntax)
1699 {
1700 if (*l == '(')
1701 ++paren_not_balanced;
1702 if (*l == ')')
1703 --paren_not_balanced;
1704 }
1705 else
1706 {
1707 if (*l == '[')
1708 ++paren_not_balanced;
1709 if (*l == ']')
1710 --paren_not_balanced;
1711 }
1712 l++;
1713 }
1714 if (l != token_start)
1715 { /* Yes, we've read in another operand. */
1716 unsigned int operand_ok;
1717 this_operand = i.operands++;
1718 if (i.operands > MAX_OPERANDS)
1719 {
1720 as_bad (_("spurious operands; (%d operands/instruction max)"),
1721 MAX_OPERANDS);
1722 return NULL;
1723 }
1724 /* Now parse operand adding info to 'i' as we go along. */
1725 END_STRING_AND_SAVE (l);
1726
1727 if (intel_syntax)
1728 operand_ok =
1729 i386_intel_operand (token_start,
1730 intel_float_operand (mnemonic));
1731 else
1732 operand_ok = i386_operand (token_start);
1733
1734 RESTORE_END_STRING (l);
1735 if (!operand_ok)
1736 return NULL;
1737 }
1738 else
1739 {
1740 if (expecting_operand)
1741 {
1742 expecting_operand_after_comma:
1743 as_bad (_("expecting operand after ','; got nothing"));
1744 return NULL;
1745 }
1746 if (*l == ',')
1747 {
1748 as_bad (_("expecting operand before ','; got nothing"));
1749 return NULL;
1750 }
1751 }
7f3f1ea2 1752
29b0f896
AM		 1753 /* Now *l must be either ',' or END_OF_INSN. */
1754 if (*l == ',')
1755 {
1756 if (*++l == END_OF_INSN)
1757 {
1758 /* Just skip it, if it's \n complain. */
1759 goto expecting_operand_after_comma;
1760 }
1761 expecting_operand = 1;
1762 }
1763 }
1764 return l;
1765}
7f3f1ea2 1766
29b0f896
AM		 1767static void
1768swap_operands ()
1769{
1770 union i386_op temp_op;
1771 unsigned int temp_type;
1772 RELOC_ENUM temp_reloc;
1773 int xchg1 = 0;
1774 int xchg2 = 0;
252b5132 1775
29b0f896
AM		 1776 if (i.operands == 2)
1777 {
1778 xchg1 = 0;
1779 xchg2 = 1;
1780 }
1781 else if (i.operands == 3)
1782 {
1783 xchg1 = 0;
1784 xchg2 = 2;
1785 }
1786 temp_type = i.types[xchg2];
1787 i.types[xchg2] = i.types[xchg1];
1788 i.types[xchg1] = temp_type;
1789 temp_op = i.op[xchg2];
1790 i.op[xchg2] = i.op[xchg1];
1791 i.op[xchg1] = temp_op;
1792 temp_reloc = i.reloc[xchg2];
1793 i.reloc[xchg2] = i.reloc[xchg1];
1794 i.reloc[xchg1] = temp_reloc;
1795
1796 if (i.mem_operands == 2)
1797 {
1798 const seg_entry *temp_seg;
1799 temp_seg = i.seg[0];
1800 i.seg[0] = i.seg[1];
1801 i.seg[1] = temp_seg;
1802 }
1803}
252b5132 1804
29b0f896
AM		 1805/* Try to ensure constant immediates are represented in the smallest
1806 opcode possible. */
1807static void
1808optimize_imm ()
1809{
1810 char guess_suffix = 0;
1811 int op;
252b5132 1812
29b0f896
AM		 1813 if (i.suffix)
1814 guess_suffix = i.suffix;
1815 else if (i.reg_operands)
1816 {
1817 /* Figure out a suffix from the last register operand specified.
1818 We can't do this properly yet, ie. excluding InOutPortReg,
1819 but the following works for instructions with immediates.
1820 In any case, we can't set i.suffix yet. */
1821 for (op = i.operands; --op >= 0;)
1822 if (i.types[op] & Reg)
252b5132 1823 {
29b0f896
AM		 1824 if (i.types[op] & Reg8)
1825 guess_suffix = BYTE_MNEM_SUFFIX;
1826 else if (i.types[op] & Reg16)
1827 guess_suffix = WORD_MNEM_SUFFIX;
1828 else if (i.types[op] & Reg32)
1829 guess_suffix = LONG_MNEM_SUFFIX;
1830 else if (i.types[op] & Reg64)
1831 guess_suffix = QWORD_MNEM_SUFFIX;
1832 break;
252b5132 1833 }
29b0f896
AM		 1834 }
1835 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1836 guess_suffix = WORD_MNEM_SUFFIX;
1837
1838 for (op = i.operands; --op >= 0;)
1839 if (i.types[op] & Imm)
1840 {
1841 switch (i.op[op].imms->X_op)
252b5132 1842 {
29b0f896
AM		 1843 case O_constant:
1844 /* If a suffix is given, this operand may be shortened. */
1845 switch (guess_suffix)
252b5132 1846 {
29b0f896
AM		 1847 case LONG_MNEM_SUFFIX:
1848 i.types[op] |= Imm32 | Imm64;
1849 break;
1850 case WORD_MNEM_SUFFIX:
1851 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1852 break;
1853 case BYTE_MNEM_SUFFIX:
1854 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1855 break;
252b5132 1856 }
252b5132 1857
29b0f896
AM		 1858 /* If this operand is at most 16 bits, convert it
1859 to a signed 16 bit number before trying to see
1860 whether it will fit in an even smaller size.
1861 This allows a 16-bit operand such as $0xffe0 to
1862 be recognised as within Imm8S range. */
1863 if ((i.types[op] & Imm16)
1864 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 1865 {
29b0f896
AM		 1866 i.op[op].imms->X_add_number =
1867 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1868 }
1869 if ((i.types[op] & Imm32)
1870 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1871 == 0))
1872 {
1873 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1874 ^ ((offsetT) 1 << 31))
1875 - ((offsetT) 1 << 31));
1876 }
1877 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 1878
29b0f896
AM		 1879 /* We must avoid matching of Imm32 templates when 64bit
1880 only immediate is available. */
1881 if (guess_suffix == QWORD_MNEM_SUFFIX)
1882 i.types[op] &= ~Imm32;
1883 break;
252b5132 1884
29b0f896
AM		 1885 case O_absent:
1886 case O_register:
1887 abort ();
1888
1889 /* Symbols and expressions. */
1890 default:
1891 /* Convert symbolic operand to proper sizes for matching. */
1892 switch (guess_suffix)
1893 {
1894 case QWORD_MNEM_SUFFIX:
1895 i.types[op] = Imm64 | Imm32S;
1896 break;
1897 case LONG_MNEM_SUFFIX:
1898 i.types[op] = Imm32 | Imm64;
1899 break;
1900 case WORD_MNEM_SUFFIX:
1901 i.types[op] = Imm16 | Imm32 | Imm64;
1902 break;
1903 break;
1904 case BYTE_MNEM_SUFFIX:
1905 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1906 break;
1907 break;
252b5132 1908 }
29b0f896 1909 break;
252b5132 1910 }
29b0f896
AM		 1911 }
1912}
47926f60 1913
29b0f896
AM		 1914/* Try to use the smallest displacement type too. */
1915static void
1916optimize_disp ()
1917{
1918 int op;
3e73aa7c 1919
29b0f896
AM		 1920 for (op = i.operands; --op >= 0;)
1921 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
252b5132 1922 {
29b0f896
AM		 1923 offsetT disp = i.op[op].disps->X_add_number;
1924
1925 if (i.types[op] & Disp16)
252b5132 1926 {
29b0f896
AM		 1927 /* We know this operand is at most 16 bits, so
1928 convert to a signed 16 bit number before trying
1929 to see whether it will fit in an even smaller
1930 size. */
1931
1932 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
252b5132 1933 }
29b0f896 1934 else if (i.types[op] & Disp32)
252b5132 1935 {
29b0f896
AM		 1936 /* We know this operand is at most 32 bits, so convert to a
1937 signed 32 bit number before trying to see whether it will
1938 fit in an even smaller size. */
1939 disp &= (((offsetT) 2 << 31) - 1);
1940 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 1941 }
29b0f896 1942 if (flag_code == CODE_64BIT)
252b5132 1943 {
29b0f896
AM		 1944 if (fits_in_signed_long (disp))
1945 i.types[op] |= Disp32S;
1946 if (fits_in_unsigned_long (disp))
1947 i.types[op] |= Disp32;
252b5132 1948 }
29b0f896
AM		 1949 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1950 && fits_in_signed_byte (disp))
1951 i.types[op] |= Disp8;
252b5132 1952 }
29b0f896
AM		 1953}
1954
1955static int
1956match_template ()
1957{
1958 /* Points to template once we've found it. */
1959 const template *t;
1960 unsigned int overlap0, overlap1, overlap2;
1961 unsigned int found_reverse_match;
1962 int suffix_check;
1963
1964#define MATCH(overlap, given, template) \
1965 ((overlap & ~JumpAbsolute) \
1966 && (((given) & (BaseIndex | JumpAbsolute)) \
1967 == ((overlap) & (BaseIndex | JumpAbsolute))))
1968
1969 /* If given types r0 and r1 are registers they must be of the same type
1970 unless the expected operand type register overlap is null.
1971 Note that Acc in a template matches every size of reg. */
1972#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1973 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1974 || ((g0) & Reg) == ((g1) & Reg) \
1975 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1976
1977 overlap0 = 0;
1978 overlap1 = 0;
1979 overlap2 = 0;
1980 found_reverse_match = 0;
1981 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1982 ? No_bSuf
1983 : (i.suffix == WORD_MNEM_SUFFIX
1984 ? No_wSuf
1985 : (i.suffix == SHORT_MNEM_SUFFIX
1986 ? No_sSuf
1987 : (i.suffix == LONG_MNEM_SUFFIX
1988 ? No_lSuf
1989 : (i.suffix == QWORD_MNEM_SUFFIX
1990 ? No_qSuf
1991 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
1992 ? No_xSuf : 0))))));
1993
1994 for (t = current_templates->start;
1995 t < current_templates->end;
1996 t++)
1997 {
1998 /* Must have right number of operands. */
1999 if (i.operands != t->operands)
2000 continue;
2001
2002 /* Check the suffix, except for some instructions in intel mode. */
2003 if ((t->opcode_modifier & suffix_check)
2004 && !(intel_syntax
2005 && (t->opcode_modifier & IgnoreSize))
2006 && !(intel_syntax
2007 && t->base_opcode == 0xd9
2008 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
2009 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
2010 continue;
2011
2012 /* Do not verify operands when there are none. */
2013 else if (!t->operands)
2014 {
2015 if (t->cpu_flags & ~cpu_arch_flags)
2016 continue;
2017 /* We've found a match; break out of loop. */
2018 break;
2019 }
252b5132 2020
29b0f896
AM		 2021 overlap0 = i.types[0] & t->operand_types[0];
2022 switch (t->operands)
2023 {
2024 case 1:
2025 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2026 continue;
2027 break;
2028 case 2:
2029 case 3:
2030 overlap1 = i.types[1] & t->operand_types[1];
2031 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2032 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2033 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2034 t->operand_types[0],
2035 overlap1, i.types[1],
2036 t->operand_types[1]))
2037 {
2038 /* Check if other direction is valid ... */
2039 if ((t->opcode_modifier & (D | FloatD)) == 0)
2040 continue;
2041
2042 /* Try reversing direction of operands. */
2043 overlap0 = i.types[0] & t->operand_types[1];
2044 overlap1 = i.types[1] & t->operand_types[0];
2045 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2046 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2047 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2048 t->operand_types[1],
2049 overlap1, i.types[1],
2050 t->operand_types[0]))
2051 {
2052 /* Does not match either direction. */
2053 continue;
2054 }
2055 /* found_reverse_match holds which of D or FloatDR
2056 we've found. */
2057 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2058 }
2059 /* Found a forward 2 operand match here. */
2060 else if (t->operands == 3)
2061 {
2062 /* Here we make use of the fact that there are no
2063 reverse match 3 operand instructions, and all 3
2064 operand instructions only need to be checked for
2065 register consistency between operands 2 and 3. */
2066 overlap2 = i.types[2] & t->operand_types[2];
2067 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2068 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2069 t->operand_types[1],
2070 overlap2, i.types[2],
2071 t->operand_types[2]))
2072
2073 continue;
2074 }
2075 /* Found either forward/reverse 2 or 3 operand match here:
2076 slip through to break. */
2077 }
2078 if (t->cpu_flags & ~cpu_arch_flags)
2079 {
2080 found_reverse_match = 0;
2081 continue;
2082 }
2083 /* We've found a match; break out of loop. */
2084 break;
2085 }
2086
2087 if (t == current_templates->end)
2088 {
2089 /* We found no match. */
2090 as_bad (_("suffix or operands invalid for `%s'"),
2091 current_templates->start->name);
2092 return 0;
2093 }
252b5132 2094
29b0f896
AM		 2095 if (!quiet_warnings)
2096 {
2097 if (!intel_syntax
2098 && ((i.types[0] & JumpAbsolute)
2099 != (t->operand_types[0] & JumpAbsolute)))
2100 {
2101 as_warn (_("indirect %s without `*'"), t->name);
2102 }
2103
2104 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2105 == (IsPrefix | IgnoreSize))
2106 {
2107 /* Warn them that a data or address size prefix doesn't
2108 affect assembly of the next line of code. */
2109 as_warn (_("stand-alone `%s' prefix"), t->name);
2110 }
2111 }
2112
2113 /* Copy the template we found. */
2114 i.tm = *t;
2115 if (found_reverse_match)
2116 {
2117 /* If we found a reverse match we must alter the opcode
2118 direction bit. found_reverse_match holds bits to change
2119 (different for int & float insns). */
2120
2121 i.tm.base_opcode ^= found_reverse_match;
2122
2123 i.tm.operand_types[0] = t->operand_types[1];
2124 i.tm.operand_types[1] = t->operand_types[0];
2125 }
2126
2127 return 1;
2128}
2129
2130static int
2131check_string ()
2132{
2133 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2134 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2135 {
2136 if (i.seg[0] != NULL && i.seg[0] != &es)
2137 {
2138 as_bad (_("`%s' operand %d must use `%%es' segment"),
2139 i.tm.name,
2140 mem_op + 1);
2141 return 0;
2142 }
2143 /* There's only ever one segment override allowed per instruction.
2144 This instruction possibly has a legal segment override on the
2145 second operand, so copy the segment to where non-string
2146 instructions store it, allowing common code. */
2147 i.seg[0] = i.seg[1];
2148 }
2149 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2150 {
2151 if (i.seg[1] != NULL && i.seg[1] != &es)
2152 {
2153 as_bad (_("`%s' operand %d must use `%%es' segment"),
2154 i.tm.name,
2155 mem_op + 2);
2156 return 0;
2157 }
2158 }
2159 return 1;
2160}
2161
2162static int
2163process_suffix ()
2164{
2165 /* If matched instruction specifies an explicit instruction mnemonic
2166 suffix, use it. */
2167 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2168 {
2169 if (i.tm.opcode_modifier & Size16)
2170 i.suffix = WORD_MNEM_SUFFIX;
2171 else if (i.tm.opcode_modifier & Size64)
2172 i.suffix = QWORD_MNEM_SUFFIX;
2173 else
2174 i.suffix = LONG_MNEM_SUFFIX;
2175 }
2176 else if (i.reg_operands)
2177 {
2178 /* If there's no instruction mnemonic suffix we try to invent one
2179 based on register operands. */
2180 if (!i.suffix)
2181 {
2182 /* We take i.suffix from the last register operand specified,
2183 Destination register type is more significant than source
2184 register type. */
2185 int op;
2186 for (op = i.operands; --op >= 0;)
2187 if ((i.types[op] & Reg)
2188 && !(i.tm.operand_types[op] & InOutPortReg))
2189 {
2190 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2191 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2192 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2193 LONG_MNEM_SUFFIX);
2194 break;
2195 }
2196 }
2197 else if (i.suffix == BYTE_MNEM_SUFFIX)
2198 {
2199 if (!check_byte_reg ())
2200 return 0;
2201 }
2202 else if (i.suffix == LONG_MNEM_SUFFIX)
2203 {
2204 if (!check_long_reg ())
2205 return 0;
2206 }
2207 else if (i.suffix == QWORD_MNEM_SUFFIX)
2208 {
2209 if (!check_qword_reg ())
2210 return 0;
2211 }
2212 else if (i.suffix == WORD_MNEM_SUFFIX)
2213 {
2214 if (!check_word_reg ())
2215 return 0;
2216 }
2217 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2218 /* Do nothing if the instruction is going to ignore the prefix. */
2219 ;
2220 else
2221 abort ();
2222 }
2223 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2224 {
2225 i.suffix = stackop_size;
2226 }
252b5132 2227
29b0f896
AM		 2228 /* Change the opcode based on the operand size given by i.suffix;
2229 We need not change things for byte insns. */
252b5132 2230
29b0f896
AM		 2231 if (!i.suffix && (i.tm.opcode_modifier & W))
2232 {
2233 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2234 return 0;
2235 }
252b5132 2236
29b0f896
AM		 2237 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2238 {
2239 /* It's not a byte, select word/dword operation. */
2240 if (i.tm.opcode_modifier & W)
2241 {
2242 if (i.tm.opcode_modifier & ShortForm)
2243 i.tm.base_opcode |= 8;
2244 else
2245 i.tm.base_opcode |= 1;
2246 }
0f3f3d8b 2247
29b0f896
AM		 2248 /* Now select between word & dword operations via the operand
2249 size prefix, except for instructions that will ignore this
2250 prefix anyway. */
2251 if (i.suffix != QWORD_MNEM_SUFFIX
9146926a
AM		 2252 && !(i.tm.opcode_modifier & IgnoreSize)
2253 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2254 || (flag_code == CODE_64BIT
2255 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2256 {
2257 unsigned int prefix = DATA_PREFIX_OPCODE;
29b0f896
AM		 2258 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2259 prefix = ADDR_PREFIX_OPCODE;
252b5132 2260
29b0f896
AM		 2261 if (!add_prefix (prefix))
2262 return 0;
24eab124 2263 }
252b5132 2264
29b0f896
AM		 2265 /* Set mode64 for an operand. */
2266 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2267 && flag_code == CODE_64BIT
29b0f896 2268 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2269 i.rex |= REX_MODE64;
3e73aa7c 2270
29b0f896
AM		 2271 /* Size floating point instruction. */
2272 if (i.suffix == LONG_MNEM_SUFFIX)
2273 {
2274 if (i.tm.opcode_modifier & FloatMF)
2275 i.tm.base_opcode ^= 4;
2276 }
2277 }
7ecd2f8b 2278
29b0f896
AM		 2279 return 1;
2280}
3e73aa7c 2281
29b0f896
AM		 2282static int
2283check_byte_reg ()
2284{
2285 int op;
2286 for (op = i.operands; --op >= 0;)
2287 {
2288 /* If this is an eight bit register, it's OK. If it's the 16 or
2289 32 bit version of an eight bit register, we will just use the
2290 low portion, and that's OK too. */
2291 if (i.types[op] & Reg8)
2292 continue;
2293
2294 /* movzx and movsx should not generate this warning. */
2295 if (intel_syntax
2296 && (i.tm.base_opcode == 0xfb7
2297 || i.tm.base_opcode == 0xfb6
2298 || i.tm.base_opcode == 0x63
2299 || i.tm.base_opcode == 0xfbe
2300 || i.tm.base_opcode == 0xfbf))
2301 continue;
2302
2303 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2304#if 0
2305 /* Check that the template allows eight bit regs. This
2306 kills insns such as `orb $1,%edx', which maybe should be
2307 allowed. */
2308 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2309#endif
2310 )
2311 {
2312 /* Prohibit these changes in the 64bit mode, since the
2313 lowering is more complicated. */
2314 if (flag_code == CODE_64BIT
2315 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2316 {
0f3f3d8b 2317 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2318 i.op[op].regs->reg_name,
2319 i.suffix);
2320 return 0;
2321 }
2322#if REGISTER_WARNINGS
2323 if (!quiet_warnings
2324 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2325 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2326 (i.op[op].regs + (i.types[op] & Reg16
2327 ? REGNAM_AL - REGNAM_AX
2328 : REGNAM_AL - REGNAM_EAX))->reg_name,
2329 i.op[op].regs->reg_name,
2330 i.suffix);
2331#endif
2332 continue;
2333 }
2334 /* Any other register is bad. */
2335 if (i.types[op] & (Reg | RegMMX | RegXMM
2336 | SReg2 | SReg3
2337 | Control | Debug | Test
2338 | FloatReg | FloatAcc))
2339 {
2340 as_bad (_("`%%%s' not allowed with `%s%c'"),
2341 i.op[op].regs->reg_name,
2342 i.tm.name,
2343 i.suffix);
2344 return 0;
2345 }
2346 }
2347 return 1;
2348}
2349
2350static int
2351check_long_reg ()
2352{
2353 int op;
2354
2355 for (op = i.operands; --op >= 0;)
2356 /* Reject eight bit registers, except where the template requires
2357 them. (eg. movzb) */
2358 if ((i.types[op] & Reg8) != 0
2359 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2360 {
2361 as_bad (_("`%%%s' not allowed with `%s%c'"),
2362 i.op[op].regs->reg_name,
2363 i.tm.name,
2364 i.suffix);
2365 return 0;
2366 }
2367 /* Warn if the e prefix on a general reg is missing. */
2368 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2369 && (i.types[op] & Reg16) != 0
2370 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2371 {
2372 /* Prohibit these changes in the 64bit mode, since the
2373 lowering is more complicated. */
2374 if (flag_code == CODE_64BIT)
252b5132 2375 {
0f3f3d8b 2376 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2377 i.op[op].regs->reg_name,
2378 i.suffix);
2379 return 0;
252b5132 2380 }
29b0f896
AM		 2381#if REGISTER_WARNINGS
2382 else
2383 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2384 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2385 i.op[op].regs->reg_name,
2386 i.suffix);
2387#endif
252b5132 2388 }
29b0f896
AM		 2389 /* Warn if the r prefix on a general reg is missing. */
2390 else if ((i.types[op] & Reg64) != 0
2391 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2392 {
0f3f3d8b 2393 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2394 i.op[op].regs->reg_name,
2395 i.suffix);
2396 return 0;
2397 }
2398 return 1;
2399}
252b5132 2400
29b0f896
AM		 2401static int
2402check_qword_reg ()
2403{
2404 int op;
252b5132 2405
29b0f896
AM		 2406 for (op = i.operands; --op >= 0; )
2407 /* Reject eight bit registers, except where the template requires
2408 them. (eg. movzb) */
2409 if ((i.types[op] & Reg8) != 0
2410 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2411 {
2412 as_bad (_("`%%%s' not allowed with `%s%c'"),
2413 i.op[op].regs->reg_name,
2414 i.tm.name,
2415 i.suffix);
2416 return 0;
2417 }
2418 /* Warn if the e prefix on a general reg is missing. */
2419 else if (((i.types[op] & Reg16) != 0
2420 || (i.types[op] & Reg32) != 0)
2421 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2422 {
2423 /* Prohibit these changes in the 64bit mode, since the
2424 lowering is more complicated. */
0f3f3d8b 2425 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2426 i.op[op].regs->reg_name,
2427 i.suffix);
2428 return 0;
252b5132 2429 }
29b0f896
AM		 2430 return 1;
2431}
252b5132 2432
29b0f896
AM		 2433static int
2434check_word_reg ()
2435{
2436 int op;
2437 for (op = i.operands; --op >= 0;)
2438 /* Reject eight bit registers, except where the template requires
2439 them. (eg. movzb) */
2440 if ((i.types[op] & Reg8) != 0
2441 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2442 {
2443 as_bad (_("`%%%s' not allowed with `%s%c'"),
2444 i.op[op].regs->reg_name,
2445 i.tm.name,
2446 i.suffix);
2447 return 0;
2448 }
2449 /* Warn if the e prefix on a general reg is present. */
2450 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2451 && (i.types[op] & Reg32) != 0
2452 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2453 {
29b0f896
AM		 2454 /* Prohibit these changes in the 64bit mode, since the
2455 lowering is more complicated. */
2456 if (flag_code == CODE_64BIT)
252b5132 2457 {
0f3f3d8b 2458 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2459 i.op[op].regs->reg_name,
2460 i.suffix);
2461 return 0;
252b5132 2462 }
29b0f896
AM		 2463 else
2464#if REGISTER_WARNINGS
2465 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2466 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2467 i.op[op].regs->reg_name,
2468 i.suffix);
2469#endif
2470 }
2471 return 1;
2472}
252b5132 2473
29b0f896
AM		 2474static int
2475finalize_imm ()
2476{
2477 unsigned int overlap0, overlap1, overlap2;
2478
2479 overlap0 = i.types[0] & i.tm.operand_types[0];
2480 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2481 && overlap0 != Imm8 && overlap0 != Imm8S
2482 && overlap0 != Imm16 && overlap0 != Imm32S
2483 && overlap0 != Imm32 && overlap0 != Imm64)
2484 {
2485 if (i.suffix)
2486 {
2487 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2488 ? Imm8 | Imm8S
2489 : (i.suffix == WORD_MNEM_SUFFIX
2490 ? Imm16
2491 : (i.suffix == QWORD_MNEM_SUFFIX
2492 ? Imm64 | Imm32S
2493 : Imm32)));
2494 }
2495 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2496 || overlap0 == (Imm16 | Imm32)
2497 || overlap0 == (Imm16 | Imm32S))
2498 {
2499 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2500 ? Imm16 : Imm32S);
2501 }
2502 if (overlap0 != Imm8 && overlap0 != Imm8S
2503 && overlap0 != Imm16 && overlap0 != Imm32S
2504 && overlap0 != Imm32 && overlap0 != Imm64)
2505 {
2506 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2507 return 0;
2508 }
2509 }
2510 i.types[0] = overlap0;
2511
2512 overlap1 = i.types[1] & i.tm.operand_types[1];
2513 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2514 && overlap1 != Imm8 && overlap1 != Imm8S
2515 && overlap1 != Imm16 && overlap1 != Imm32S
2516 && overlap1 != Imm32 && overlap1 != Imm64)
2517 {
2518 if (i.suffix)
2519 {
2520 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2521 ? Imm8 | Imm8S
2522 : (i.suffix == WORD_MNEM_SUFFIX
2523 ? Imm16
2524 : (i.suffix == QWORD_MNEM_SUFFIX
2525 ? Imm64 | Imm32S
2526 : Imm32)));
2527 }
2528 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2529 || overlap1 == (Imm16 | Imm32)
2530 || overlap1 == (Imm16 | Imm32S))
2531 {
2532 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2533 ? Imm16 : Imm32S);
2534 }
2535 if (overlap1 != Imm8 && overlap1 != Imm8S
2536 && overlap1 != Imm16 && overlap1 != Imm32S
2537 && overlap1 != Imm32 && overlap1 != Imm64)
2538 {
2539 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2540 return 0;
2541 }
2542 }
2543 i.types[1] = overlap1;
2544
2545 overlap2 = i.types[2] & i.tm.operand_types[2];
2546 assert ((overlap2 & Imm) == 0);
2547 i.types[2] = overlap2;
2548
2549 return 1;
2550}
2551
2552static int
2553process_operands ()
2554{
2555 /* Default segment register this instruction will use for memory
2556 accesses. 0 means unknown. This is only for optimizing out
2557 unnecessary segment overrides. */
2558 const seg_entry *default_seg = 0;
2559
2560 /* The imul $imm, %reg instruction is converted into
2561 imul $imm, %reg, %reg, and the clr %reg instruction
2562 is converted into xor %reg, %reg. */
2563 if (i.tm.opcode_modifier & regKludge)
2564 {
2565 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2566 /* Pretend we saw the extra register operand. */
2567 assert (i.op[first_reg_op + 1].regs == 0);
2568 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2569 i.types[first_reg_op + 1] = i.types[first_reg_op];
2570 i.reg_operands = 2;
2571 }
2572
2573 if (i.tm.opcode_modifier & ShortForm)
2574 {
2575 /* The register or float register operand is in operand 0 or 1. */
2576 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2577 /* Register goes in low 3 bits of opcode. */
2578 i.tm.base_opcode |= i.op[op].regs->reg_num;
2579 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2580 i.rex |= REX_EXTZ;
2581 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2582 {
2583 /* Warn about some common errors, but press on regardless.
2584 The first case can be generated by gcc (<= 2.8.1). */
2585 if (i.operands == 2)
2586 {
2587 /* Reversed arguments on faddp, fsubp, etc. */
2588 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2589 i.op[1].regs->reg_name,
2590 i.op[0].regs->reg_name);
2591 }
2592 else
2593 {
2594 /* Extraneous `l' suffix on fp insn. */
2595 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2596 i.op[0].regs->reg_name);
2597 }
2598 }
2599 }
2600 else if (i.tm.opcode_modifier & Modrm)
2601 {
2602 /* The opcode is completed (modulo i.tm.extension_opcode which
2603 must be put into the modrm byte).
2604 Now, we make the modrm & index base bytes based on all the
2605 info we've collected. */
2606
2607 default_seg = build_modrm_byte ();
2608 }
2609 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2610 {
2611 if (i.tm.base_opcode == POP_SEG_SHORT
2612 && i.op[0].regs->reg_num == 1)
2613 {
2614 as_bad (_("you can't `pop %%cs'"));
2615 return 0;
2616 }
2617 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2618 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2619 i.rex |= REX_EXTZ;
2620 }
2621 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2622 {
2623 default_seg = &ds;
2624 }
2625 else if ((i.tm.opcode_modifier & IsString) != 0)
2626 {
2627 /* For the string instructions that allow a segment override
2628 on one of their operands, the default segment is ds. */
2629 default_seg = &ds;
2630 }
2631
2632 /* If a segment was explicitly specified,
2633 and the specified segment is not the default,
2634 use an opcode prefix to select it.
2635 If we never figured out what the default segment is,
2636 then default_seg will be zero at this point,
2637 and the specified segment prefix will always be used. */
2638 if ((i.seg[0]) && (i.seg[0] != default_seg))
2639 {
2640 if (!add_prefix (i.seg[0]->seg_prefix))
2641 return 0;
2642 }
2643 return 1;
2644}
2645
2646static const seg_entry *
2647build_modrm_byte ()
2648{
2649 const seg_entry *default_seg = 0;
2650
2651 /* i.reg_operands MUST be the number of real register operands;
2652 implicit registers do not count. */
2653 if (i.reg_operands == 2)
2654 {
2655 unsigned int source, dest;
2656 source = ((i.types[0]
2657 & (Reg | RegMMX | RegXMM
2658 | SReg2 | SReg3
2659 | Control | Debug | Test))
2660 ? 0 : 1);
2661 dest = source + 1;
2662
2663 i.rm.mode = 3;
2664 /* One of the register operands will be encoded in the i.tm.reg
2665 field, the other in the combined i.tm.mode and i.tm.regmem
2666 fields. If no form of this instruction supports a memory
2667 destination operand, then we assume the source operand may
2668 sometimes be a memory operand and so we need to store the
2669 destination in the i.rm.reg field. */
2670 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2671 {
2672 i.rm.reg = i.op[dest].regs->reg_num;
2673 i.rm.regmem = i.op[source].regs->reg_num;
2674 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2675 i.rex |= REX_EXTX;
2676 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2677 i.rex |= REX_EXTZ;
2678 }
2679 else
2680 {
2681 i.rm.reg = i.op[source].regs->reg_num;
2682 i.rm.regmem = i.op[dest].regs->reg_num;
2683 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2684 i.rex |= REX_EXTZ;
2685 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2686 i.rex |= REX_EXTX;
2687 }
2688 }
2689 else
2690 { /* If it's not 2 reg operands... */
2691 if (i.mem_operands)
2692 {
2693 unsigned int fake_zero_displacement = 0;
2694 unsigned int op = ((i.types[0] & AnyMem)
2695 ? 0
2696 : (i.types[1] & AnyMem) ? 1 : 2);
2697
2698 default_seg = &ds;
2699
2700 if (i.base_reg == 0)
2701 {
2702 i.rm.mode = 0;
2703 if (!i.disp_operands)
2704 fake_zero_displacement = 1;
2705 if (i.index_reg == 0)
2706 {
2707 /* Operand is just <disp> */
2708 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
2709 && (flag_code != CODE_64BIT))
2710 {
2711 i.rm.regmem = NO_BASE_REGISTER_16;
2712 i.types[op] &= ~Disp;
2713 i.types[op] |= Disp16;
2714 }
2715 else if (flag_code != CODE_64BIT
2716 || (i.prefix[ADDR_PREFIX] != 0))
2717 {
2718 i.rm.regmem = NO_BASE_REGISTER;
2719 i.types[op] &= ~Disp;
2720 i.types[op] |= Disp32;
2721 }
2722 else
2723 {
2724 /* 64bit mode overwrites the 32bit absolute
2725 addressing by RIP relative addressing and
2726 absolute addressing is encoded by one of the
2727 redundant SIB forms. */
2728 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2729 i.sib.base = NO_BASE_REGISTER;
2730 i.sib.index = NO_INDEX_REGISTER;
2731 i.types[op] &= ~Disp;
2732 i.types[op] |= Disp32S;
2733 }
2734 }
2735 else /* !i.base_reg && i.index_reg */
2736 {
2737 i.sib.index = i.index_reg->reg_num;
2738 i.sib.base = NO_BASE_REGISTER;
2739 i.sib.scale = i.log2_scale_factor;
2740 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2741 i.types[op] &= ~Disp;
2742 if (flag_code != CODE_64BIT)
2743 i.types[op] |= Disp32; /* Must be 32 bit */
2744 else
2745 i.types[op] |= Disp32S;
2746 if ((i.index_reg->reg_flags & RegRex) != 0)
2747 i.rex |= REX_EXTY;
2748 }
2749 }
2750 /* RIP addressing for 64bit mode. */
2751 else if (i.base_reg->reg_type == BaseIndex)
2752 {
2753 i.rm.regmem = NO_BASE_REGISTER;
2754 i.types[op] &= ~Disp;
2755 i.types[op] |= Disp32S;
2756 i.flags[op] = Operand_PCrel;
2757 }
2758 else if (i.base_reg->reg_type & Reg16)
2759 {
2760 switch (i.base_reg->reg_num)
2761 {
2762 case 3: /* (%bx) */
2763 if (i.index_reg == 0)
2764 i.rm.regmem = 7;
2765 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2766 i.rm.regmem = i.index_reg->reg_num - 6;
2767 break;
2768 case 5: /* (%bp) */
2769 default_seg = &ss;
2770 if (i.index_reg == 0)
2771 {
2772 i.rm.regmem = 6;
2773 if ((i.types[op] & Disp) == 0)
2774 {
2775 /* fake (%bp) into 0(%bp) */
2776 i.types[op] |= Disp8;
252b5132 2777 fake_zero_displacement = 1;
29b0f896
AM		 2778 }
2779 }
2780 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2781 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2782 break;
2783 default: /* (%si) -> 4 or (%di) -> 5 */
2784 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2785 }
2786 i.rm.mode = mode_from_disp_size (i.types[op]);
2787 }
2788 else /* i.base_reg and 32/64 bit mode */
2789 {
2790 if (flag_code == CODE_64BIT
2791 && (i.types[op] & Disp))
2792 {
2793 if (i.types[op] & Disp8)
2794 i.types[op] = Disp8 | Disp32S;
2795 else
2796 i.types[op] = Disp32S;
2797 }
2798 i.rm.regmem = i.base_reg->reg_num;
2799 if ((i.base_reg->reg_flags & RegRex) != 0)
2800 i.rex |= REX_EXTZ;
2801 i.sib.base = i.base_reg->reg_num;
2802 /* x86-64 ignores REX prefix bit here to avoid decoder
2803 complications. */
2804 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2805 {
2806 default_seg = &ss;
2807 if (i.disp_operands == 0)
2808 {
2809 fake_zero_displacement = 1;
2810 i.types[op] |= Disp8;
2811 }
2812 }
2813 else if (i.base_reg->reg_num == ESP_REG_NUM)
2814 {
2815 default_seg = &ss;
2816 }
2817 i.sib.scale = i.log2_scale_factor;
2818 if (i.index_reg == 0)
2819 {
2820 /* <disp>(%esp) becomes two byte modrm with no index
2821 register. We've already stored the code for esp
2822 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2823 Any base register besides %esp will not use the
2824 extra modrm byte. */
2825 i.sib.index = NO_INDEX_REGISTER;
2826#if !SCALE1_WHEN_NO_INDEX
2827 /* Another case where we force the second modrm byte. */
2828 if (i.log2_scale_factor)
2829 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 2830#endif
29b0f896
AM		 2831 }
2832 else
2833 {
2834 i.sib.index = i.index_reg->reg_num;
2835 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2836 if ((i.index_reg->reg_flags & RegRex) != 0)
2837 i.rex |= REX_EXTY;
2838 }
2839 i.rm.mode = mode_from_disp_size (i.types[op]);
2840 }
252b5132 2841
29b0f896
AM		 2842 if (fake_zero_displacement)
2843 {
2844 /* Fakes a zero displacement assuming that i.types[op]
2845 holds the correct displacement size. */
2846 expressionS *exp;
2847
2848 assert (i.op[op].disps == 0);
2849 exp = &disp_expressions[i.disp_operands++];
2850 i.op[op].disps = exp;
2851 exp->X_op = O_constant;
2852 exp->X_add_number = 0;
2853 exp->X_add_symbol = (symbolS *) 0;
2854 exp->X_op_symbol = (symbolS *) 0;
2855 }
2856 }
252b5132 2857
29b0f896
AM		 2858 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2859 (if any) based on i.tm.extension_opcode. Again, we must be
2860 careful to make sure that segment/control/debug/test/MMX
2861 registers are coded into the i.rm.reg field. */
2862 if (i.reg_operands)
2863 {
2864 unsigned int op =
2865 ((i.types[0]
2866 & (Reg | RegMMX | RegXMM
2867 | SReg2 | SReg3
2868 | Control | Debug | Test))
2869 ? 0
2870 : ((i.types[1]
2871 & (Reg | RegMMX | RegXMM
2872 | SReg2 | SReg3
2873 | Control | Debug | Test))
2874 ? 1
2875 : 2));
2876 /* If there is an extension opcode to put here, the register
2877 number must be put into the regmem field. */
2878 if (i.tm.extension_opcode != None)
2879 {
2880 i.rm.regmem = i.op[op].regs->reg_num;
2881 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2882 i.rex |= REX_EXTZ;
2883 }
2884 else
2885 {
2886 i.rm.reg = i.op[op].regs->reg_num;
2887 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2888 i.rex |= REX_EXTX;
2889 }
252b5132 2890
29b0f896
AM		 2891 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2892 must set it to 3 to indicate this is a register operand
2893 in the regmem field. */
2894 if (!i.mem_operands)
2895 i.rm.mode = 3;
2896 }
252b5132 2897
29b0f896
AM		 2898 /* Fill in i.rm.reg field with extension opcode (if any). */
2899 if (i.tm.extension_opcode != None)
2900 i.rm.reg = i.tm.extension_opcode;
2901 }
2902 return default_seg;
2903}
252b5132 2904
29b0f896
AM		 2905static void
2906output_branch ()
2907{
2908 char *p;
2909 int code16;
2910 int prefix;
2911 relax_substateT subtype;
2912 symbolS *sym;
2913 offsetT off;
2914
2915 code16 = 0;
2916 if (flag_code == CODE_16BIT)
2917 code16 = CODE16;
2918
2919 prefix = 0;
2920 if (i.prefix[DATA_PREFIX] != 0)
252b5132 2921 {
29b0f896
AM		 2922 prefix = 1;
2923 i.prefixes -= 1;
2924 code16 ^= CODE16;
252b5132 2925 }
29b0f896
AM		 2926 /* Pentium4 branch hints. */
2927 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2928 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 2929 {
29b0f896
AM		 2930 prefix++;
2931 i.prefixes--;
2932 }
2933 if (i.prefix[REX_PREFIX] != 0)
2934 {
2935 prefix++;
2936 i.prefixes--;
2f66722d
AM		 2937 }
2938
29b0f896
AM		 2939 if (i.prefixes != 0 && !intel_syntax)
2940 as_warn (_("skipping prefixes on this instruction"));
2941
2942 /* It's always a symbol; End frag & setup for relax.
2943 Make sure there is enough room in this frag for the largest
2944 instruction we may generate in md_convert_frag. This is 2
2945 bytes for the opcode and room for the prefix and largest
2946 displacement. */
2947 frag_grow (prefix + 2 + 4);
2948 /* Prefix and 1 opcode byte go in fr_fix. */
2949 p = frag_more (prefix + 1);
2950 if (i.prefix[DATA_PREFIX] != 0)
2951 *p++ = DATA_PREFIX_OPCODE;
2952 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2953 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2954 *p++ = i.prefix[SEG_PREFIX];
2955 if (i.prefix[REX_PREFIX] != 0)
2956 *p++ = i.prefix[REX_PREFIX];
2957 *p = i.tm.base_opcode;
2958
2959 if ((unsigned char) *p == JUMP_PC_RELATIVE)
2960 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
2961 else if ((cpu_arch_flags & Cpu386) != 0)
2962 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
2963 else
2964 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
2965 subtype |= code16;
3e73aa7c 2966
29b0f896
AM		 2967 sym = i.op[0].disps->X_add_symbol;
2968 off = i.op[0].disps->X_add_number;
3e73aa7c 2969
29b0f896
AM		 2970 if (i.op[0].disps->X_op != O_constant
2971 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 2972 {
29b0f896
AM		 2973 /* Handle complex expressions. */
2974 sym = make_expr_symbol (i.op[0].disps);
2975 off = 0;
2976 }
3e73aa7c 2977
29b0f896
AM		 2978 /* 1 possible extra opcode + 4 byte displacement go in var part.
2979 Pass reloc in fr_var. */
2980 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
2981}
3e73aa7c 2982
29b0f896
AM		 2983static void
2984output_jump ()
2985{
2986 char *p;
2987 int size;
2988
2989 if (i.tm.opcode_modifier & JumpByte)
2990 {
2991 /* This is a loop or jecxz type instruction. */
2992 size = 1;
2993 if (i.prefix[ADDR_PREFIX] != 0)
2994 {
2995 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
2996 i.prefixes -= 1;
2997 }
2998 /* Pentium4 branch hints. */
2999 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3000 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3001 {
3002 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3003 i.prefixes--;
3e73aa7c
JH		 3004 }
3005 }
29b0f896
AM		 3006 else
3007 {
3008 int code16;
3e73aa7c 3009
29b0f896
AM		 3010 code16 = 0;
3011 if (flag_code == CODE_16BIT)
3012 code16 = CODE16;
3e73aa7c 3013
29b0f896
AM		 3014 if (i.prefix[DATA_PREFIX] != 0)
3015 {
3016 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3017 i.prefixes -= 1;
3018 code16 ^= CODE16;
3019 }
252b5132 3020
29b0f896
AM		 3021 size = 4;
3022 if (code16)
3023 size = 2;
3024 }
9fcc94b6 3025
29b0f896
AM		 3026 if (i.prefix[REX_PREFIX] != 0)
3027 {
3028 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3029 i.prefixes -= 1;
3030 }
252b5132 3031
29b0f896
AM		 3032 if (i.prefixes != 0 && !intel_syntax)
3033 as_warn (_("skipping prefixes on this instruction"));
e0890092 3034
29b0f896
AM		 3035 p = frag_more (1 + size);
3036 *p++ = i.tm.base_opcode;
e0890092 3037
062cd5e7
AS		 3038 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3039 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
29b0f896 3040}
e0890092 3041
29b0f896
AM		 3042static void
3043output_interseg_jump ()
3044{
3045 char *p;
3046 int size;
3047 int prefix;
3048 int code16;
252b5132 3049
29b0f896
AM		 3050 code16 = 0;
3051 if (flag_code == CODE_16BIT)
3052 code16 = CODE16;
a217f122 3053
29b0f896
AM		 3054 prefix = 0;
3055 if (i.prefix[DATA_PREFIX] != 0)
3056 {
3057 prefix = 1;
3058 i.prefixes -= 1;
3059 code16 ^= CODE16;
3060 }
3061 if (i.prefix[REX_PREFIX] != 0)
3062 {
3063 prefix++;
3064 i.prefixes -= 1;
3065 }
252b5132 3066
29b0f896
AM		 3067 size = 4;
3068 if (code16)
3069 size = 2;
252b5132 3070
29b0f896
AM		 3071 if (i.prefixes != 0 && !intel_syntax)
3072 as_warn (_("skipping prefixes on this instruction"));
252b5132 3073
29b0f896
AM		 3074 /* 1 opcode; 2 segment; offset */
3075 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3076
29b0f896
AM		 3077 if (i.prefix[DATA_PREFIX] != 0)
3078 *p++ = DATA_PREFIX_OPCODE;
252b5132 3079
29b0f896
AM		 3080 if (i.prefix[REX_PREFIX] != 0)
3081 *p++ = i.prefix[REX_PREFIX];
252b5132 3082
29b0f896
AM		 3083 *p++ = i.tm.base_opcode;
3084 if (i.op[1].imms->X_op == O_constant)
3085 {
3086 offsetT n = i.op[1].imms->X_add_number;
252b5132 3087
29b0f896
AM		 3088 if (size == 2
3089 && !fits_in_unsigned_word (n)
3090 && !fits_in_signed_word (n))
3091 {
3092 as_bad (_("16-bit jump out of range"));
3093 return;
3094 }
3095 md_number_to_chars (p, n, size);
3096 }
3097 else
3098 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3099 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3100 if (i.op[0].imms->X_op != O_constant)
3101 as_bad (_("can't handle non absolute segment in `%s'"),
3102 i.tm.name);
3103 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3104}
a217f122 3105
2bbd9c25 3106
29b0f896
AM		 3107static void
3108output_insn ()
3109{
2bbd9c25
JJ		 3110 fragS *insn_start_frag;
3111 offsetT insn_start_off;
3112
29b0f896
AM		 3113 /* Tie dwarf2 debug info to the address at the start of the insn.
3114 We can't do this after the insn has been output as the current
3115 frag may have been closed off. eg. by frag_var. */
3116 dwarf2_emit_insn (0);
3117
2bbd9c25
JJ		 3118 insn_start_frag = frag_now;
3119 insn_start_off = frag_now_fix ();
3120
29b0f896
AM		 3121 /* Output jumps. */
3122 if (i.tm.opcode_modifier & Jump)
3123 output_branch ();
3124 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3125 output_jump ();
3126 else if (i.tm.opcode_modifier & JumpInterSegment)
3127 output_interseg_jump ();
3128 else
3129 {
3130 /* Output normal instructions here. */
3131 char *p;
3132 unsigned char *q;
252b5132 3133
29b0f896
AM		 3134 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3135 byte for the SSE instructions to specify a prefix they require. */
3136 if (i.tm.base_opcode & 0xff0000)
3137 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
252b5132 3138
29b0f896
AM		 3139 /* The prefix bytes. */
3140 for (q = i.prefix;
3141 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3142 q++)
3143 {
3144 if (*q)
3145 {
3146 p = frag_more (1);
3147 md_number_to_chars (p, (valueT) *q, 1);
3148 }
3149 }
252b5132 3150
29b0f896
AM		 3151 /* Now the opcode; be careful about word order here! */
3152 if (fits_in_unsigned_byte (i.tm.base_opcode))
3153 {
3154 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3155 }
3156 else
3157 {
3158 p = frag_more (2);
3159 /* Put out high byte first: can't use md_number_to_chars! */
3160 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3161 *p = i.tm.base_opcode & 0xff;
3162 }
3e73aa7c 3163
29b0f896
AM		 3164 /* Now the modrm byte and sib byte (if present). */
3165 if (i.tm.opcode_modifier & Modrm)
3166 {
3167 p = frag_more (1);
3168 md_number_to_chars (p,
3169 (valueT) (i.rm.regmem << 0
3170 | i.rm.reg << 3
3171 | i.rm.mode << 6),
3172 1);
3173 /* If i.rm.regmem == ESP (4)
3174 && i.rm.mode != (Register mode)
3175 && not 16 bit
3176 ==> need second modrm byte. */
3177 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3178 && i.rm.mode != 3
3179 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3180 {
3181 p = frag_more (1);
3182 md_number_to_chars (p,
3183 (valueT) (i.sib.base << 0
3184 | i.sib.index << 3
3185 | i.sib.scale << 6),
3186 1);
3187 }
3188 }
3e73aa7c 3189
29b0f896 3190 if (i.disp_operands)
2bbd9c25 3191 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3192
29b0f896 3193 if (i.imm_operands)
2bbd9c25 3194 output_imm (insn_start_frag, insn_start_off);
29b0f896 3195 }
252b5132 3196
29b0f896
AM		 3197#ifdef DEBUG386
3198 if (flag_debug)
3199 {
3200 pi (line, &i);
3201 }
3202#endif /* DEBUG386 */
3203}
252b5132 3204
29b0f896 3205static void
2bbd9c25
JJ		 3206output_disp (insn_start_frag, insn_start_off)
3207 fragS *insn_start_frag;
3208 offsetT insn_start_off;
29b0f896
AM		 3209{
3210 char *p;
3211 unsigned int n;
252b5132 3212
29b0f896
AM		 3213 for (n = 0; n < i.operands; n++)
3214 {
3215 if (i.types[n] & Disp)
3216 {
3217 if (i.op[n].disps->X_op == O_constant)
3218 {
3219 int size;
3220 offsetT val;
252b5132 3221
29b0f896
AM		 3222 size = 4;
3223 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3224 {
3225 size = 2;
3226 if (i.types[n] & Disp8)
3227 size = 1;
3228 if (i.types[n] & Disp64)
3229 size = 8;
3230 }
3231 val = offset_in_range (i.op[n].disps->X_add_number,
3232 size);
3233 p = frag_more (size);
3234 md_number_to_chars (p, val, size);
3235 }
3236 else
3237 {
2bbd9c25 3238 RELOC_ENUM reloc_type;
29b0f896
AM		 3239 int size = 4;
3240 int sign = 0;
3241 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3242
3243 /* The PC relative address is computed relative
3244 to the instruction boundary, so in case immediate
3245 fields follows, we need to adjust the value. */
3246 if (pcrel && i.imm_operands)
3247 {
3248 int imm_size = 4;
3249 unsigned int n1;
252b5132 3250
29b0f896
AM		 3251 for (n1 = 0; n1 < i.operands; n1++)
3252 if (i.types[n1] & Imm)
252b5132 3253 {
29b0f896 3254 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3255 {
29b0f896
AM		 3256 imm_size = 2;
3257 if (i.types[n1] & (Imm8 | Imm8S))
3258 imm_size = 1;
3259 if (i.types[n1] & Imm64)
3260 imm_size = 8;
252b5132 3261 }
29b0f896 3262 break;
252b5132 3263 }
29b0f896
AM		 3264 /* We should find the immediate. */
3265 if (n1 == i.operands)
3266 abort ();
3267 i.op[n].disps->X_add_number -= imm_size;
3268 }
520dc8e8 3269
29b0f896
AM		 3270 if (i.types[n] & Disp32S)
3271 sign = 1;
3e73aa7c 3272
29b0f896
AM		 3273 if (i.types[n] & (Disp16 | Disp64))
3274 {
3275 size = 2;
3276 if (i.types[n] & Disp64)
3277 size = 8;
3278 }
520dc8e8 3279
29b0f896 3280 p = frag_more (size);
2bbd9c25
JJ		 3281 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
3282#ifdef BFD_ASSEMBLER
3283 if (reloc_type == BFD_RELOC_32
3284 && GOT_symbol
3285 && GOT_symbol == i.op[n].disps->X_add_symbol
3286 && (i.op[n].disps->X_op == O_symbol
3287 || (i.op[n].disps->X_op == O_add
3288 && ((symbol_get_value_expression
3289 (i.op[n].disps->X_op_symbol)->X_op)
3290 == O_subtract))))
3291 {
3292 offsetT add;
3293
3294 if (insn_start_frag == frag_now)
3295 add = (p - frag_now->fr_literal) - insn_start_off;
3296 else
3297 {
3298 fragS *fr;
3299
3300 add = insn_start_frag->fr_fix - insn_start_off;
3301 for (fr = insn_start_frag->fr_next;
3302 fr && fr != frag_now; fr = fr->fr_next)
3303 add += fr->fr_fix;
3304 add += p - frag_now->fr_literal;
3305 }
3306
3307 /* We don't support dynamic linking on x86-64 yet. */
3308 if (flag_code == CODE_64BIT)
3309 abort ();
3310 reloc_type = BFD_RELOC_386_GOTPC;
3311 i.op[n].disps->X_add_number += add;
3312 }
3313#endif
062cd5e7 3314 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3315 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3316 }
3317 }
3318 }
3319}
252b5132 3320
29b0f896 3321static void
2bbd9c25
JJ		 3322output_imm (insn_start_frag, insn_start_off)
3323 fragS *insn_start_frag;
3324 offsetT insn_start_off;
29b0f896
AM		 3325{
3326 char *p;
3327 unsigned int n;
252b5132 3328
29b0f896
AM		 3329 for (n = 0; n < i.operands; n++)
3330 {
3331 if (i.types[n] & Imm)
3332 {
3333 if (i.op[n].imms->X_op == O_constant)
3334 {
3335 int size;
3336 offsetT val;
b4cac588 3337
29b0f896
AM		 3338 size = 4;
3339 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3340 {
3341 size = 2;
3342 if (i.types[n] & (Imm8 | Imm8S))
3343 size = 1;
3344 else if (i.types[n] & Imm64)
3345 size = 8;
3346 }
3347 val = offset_in_range (i.op[n].imms->X_add_number,
3348 size);
3349 p = frag_more (size);
3350 md_number_to_chars (p, val, size);
3351 }
3352 else
3353 {
3354 /* Not absolute_section.
3355 Need a 32-bit fixup (don't support 8bit
3356 non-absolute imms). Try to support other
3357 sizes ... */
3358 RELOC_ENUM reloc_type;
3359 int size = 4;
3360 int sign = 0;
3361
3362 if ((i.types[n] & (Imm32S))
3363 && i.suffix == QWORD_MNEM_SUFFIX)
3364 sign = 1;
3365 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3366 {
3367 size = 2;
3368 if (i.types[n] & (Imm8 | Imm8S))
3369 size = 1;
3370 if (i.types[n] & Imm64)
3371 size = 8;
3372 }
520dc8e8 3373
29b0f896
AM		 3374 p = frag_more (size);
3375 reloc_type = reloc (size, 0, sign, i.reloc[n]);
252b5132 3376#ifdef BFD_ASSEMBLER
2bbd9c25
JJ		 3377 /* This is tough to explain. We end up with this one if we
3378 * have operands that look like
3379 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3380 * obtain the absolute address of the GOT, and it is strongly
3381 * preferable from a performance point of view to avoid using
3382 * a runtime relocation for this. The actual sequence of
3383 * instructions often look something like:
3384 *
3385 * call .L66
3386 * .L66:
3387 * popl %ebx
3388 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3389 *
3390 * The call and pop essentially return the absolute address
3391 * of the label .L66 and store it in %ebx. The linker itself
3392 * will ultimately change the first operand of the addl so
3393 * that %ebx points to the GOT, but to keep things simple, the
3394 * .o file must have this operand set so that it generates not
3395 * the absolute address of .L66, but the absolute address of
3396 * itself. This allows the linker itself simply treat a GOTPC
3397 * relocation as asking for a pcrel offset to the GOT to be
3398 * added in, and the addend of the relocation is stored in the
3399 * operand field for the instruction itself.
3400 *
3401 * Our job here is to fix the operand so that it would add
3402 * the correct offset so that %ebx would point to itself. The
3403 * thing that is tricky is that .-.L66 will point to the
3404 * beginning of the instruction, so we need to further modify
3405 * the operand so that it will point to itself. There are
3406 * other cases where you have something like:
3407 *
3408 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3409 *
3410 * and here no correction would be required. Internally in
3411 * the assembler we treat operands of this form as not being
3412 * pcrel since the '.' is explicitly mentioned, and I wonder
3413 * whether it would simplify matters to do it this way. Who
3414 * knows. In earlier versions of the PIC patches, the
3415 * pcrel_adjust field was used to store the correction, but
3416 * since the expression is not pcrel, I felt it would be
3417 * confusing to do it this way. */
3418
29b0f896
AM		 3419 if (reloc_type == BFD_RELOC_32
3420 && GOT_symbol
3421 && GOT_symbol == i.op[n].imms->X_add_symbol
3422 && (i.op[n].imms->X_op == O_symbol
3423 || (i.op[n].imms->X_op == O_add
3424 && ((symbol_get_value_expression
3425 (i.op[n].imms->X_op_symbol)->X_op)
3426 == O_subtract))))
3427 {
2bbd9c25
JJ		 3428 offsetT add;
3429
3430 if (insn_start_frag == frag_now)
3431 add = (p - frag_now->fr_literal) - insn_start_off;
3432 else
3433 {
3434 fragS *fr;
3435
3436 add = insn_start_frag->fr_fix - insn_start_off;
3437 for (fr = insn_start_frag->fr_next;
3438 fr && fr != frag_now; fr = fr->fr_next)
3439 add += fr->fr_fix;
3440 add += p - frag_now->fr_literal;
3441 }
3442
29b0f896
AM		 3443 /* We don't support dynamic linking on x86-64 yet. */
3444 if (flag_code == CODE_64BIT)
3445 abort ();
3446 reloc_type = BFD_RELOC_386_GOTPC;
2bbd9c25 3447 i.op[n].imms->X_add_number += add;
29b0f896 3448 }
252b5132 3449#endif
29b0f896
AM		 3450 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3451 i.op[n].imms, 0, reloc_type);
3452 }
3453 }
3454 }
252b5132
RH		 3455}
3456\f
f3c180ae
AM		 3457#ifndef LEX_AT
3458static char *lex_got PARAMS ((RELOC_ENUM *, int *));
3459
3460/* Parse operands of the form
3461 <symbol>@GOTOFF+<nnn>
3462 and similar .plt or .got references.
3463
3464 If we find one, set up the correct relocation in RELOC and copy the
3465 input string, minus the `@GOTOFF' into a malloc'd buffer for
3466 parsing by the calling routine. Return this buffer, and if ADJUST
3467 is non-null set it to the length of the string we removed from the
3468 input line. Otherwise return NULL. */
3469static char *
3470lex_got (reloc, adjust)
3471 RELOC_ENUM *reloc;
3472 int *adjust;
3473{
3474 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3475 static const struct {
3476 const char *str;
3477 const RELOC_ENUM rel[NUM_FLAG_CODE];
3478 } gotrel[] = {
13ae64f3
JJ		 3479 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3480 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3481 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3482 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, 0 } },
3483 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
3484 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, 0 } },
3485 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, 0 } },
3486 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
3487 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, 0 } },
3488 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
f3c180ae
AM		 3489 };
3490 char *cp;
3491 unsigned int j;
3492
3493 for (cp = input_line_pointer; *cp != '@'; cp++)
3494 if (is_end_of_line[(unsigned char) *cp])
3495 return NULL;
3496
3497 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3498 {
3499 int len;
3500
3501 len = strlen (gotrel[j].str);
28f81592 3502 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3503 {
3504 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3505 {
28f81592
AM		 3506 int first, second;
3507 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3508
3509 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3510 if (adjust)
3511 *adjust = len;
f3c180ae
AM		 3512
3513 if (GOT_symbol == NULL)
3514 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3515
3516 /* Replace the relocation token with ' ', so that
3517 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3518
3519 /* The length of the first part of our input line. */
f3c180ae 3520 first = cp - input_line_pointer;
28f81592
AM		 3521
3522 /* The second part goes from after the reloc token until
3523 (and including) an end_of_line char. Don't use strlen
3524 here as the end_of_line char may not be a NUL. */
3525 past_reloc = cp + 1 + len;
3526 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3527 ;
3528 second = cp - past_reloc;
3529
3530 /* Allocate and copy string. The trailing NUL shouldn't
3531 be necessary, but be safe. */
3532 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3533 memcpy (tmpbuf, input_line_pointer, first);
3534 tmpbuf[first] = ' ';
28f81592
AM		 3535 memcpy (tmpbuf + first + 1, past_reloc, second);
3536 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3537 return tmpbuf;
3538 }
3539
3540 as_bad (_("@%s reloc is not supported in %s bit mode"),
3541 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3542 return NULL;
3543 }
3544 }
3545
3546 /* Might be a symbol version string. Don't as_bad here. */
3547 return NULL;
3548}
3549
3550/* x86_cons_fix_new is called via the expression parsing code when a
3551 reloc is needed. We use this hook to get the correct .got reloc. */
3552static RELOC_ENUM got_reloc = NO_RELOC;
3553
3554void
3555x86_cons_fix_new (frag, off, len, exp)
3556 fragS *frag;
3557 unsigned int off;
3558 unsigned int len;
3559 expressionS *exp;
3560{
3561 RELOC_ENUM r = reloc (len, 0, 0, got_reloc);
3562 got_reloc = NO_RELOC;
3563 fix_new_exp (frag, off, len, exp, 0, r);
3564}
3565
3566void
3567x86_cons (exp, size)
3568 expressionS *exp;
3569 int size;
3570{
3571 if (size == 4)
3572 {
3573 /* Handle @GOTOFF and the like in an expression. */
3574 char *save;
3575 char *gotfree_input_line;
3576 int adjust;
3577
3578 save = input_line_pointer;
3579 gotfree_input_line = lex_got (&got_reloc, &adjust);
3580 if (gotfree_input_line)
3581 input_line_pointer = gotfree_input_line;
3582
3583 expression (exp);
3584
3585 if (gotfree_input_line)
3586 {
3587 /* expression () has merrily parsed up to the end of line,
3588 or a comma - in the wrong buffer. Transfer how far
3589 input_line_pointer has moved to the right buffer. */
3590 input_line_pointer = (save
3591 + (input_line_pointer - gotfree_input_line)
3592 + adjust);
3593 free (gotfree_input_line);
3594 }
3595 }
3596 else
3597 expression (exp);
3598}
3599#endif
3600
252b5132
RH		 3601static int i386_immediate PARAMS ((char *));
3602
3603static int
3604i386_immediate (imm_start)
3605 char *imm_start;
3606{
3607 char *save_input_line_pointer;
f3c180ae
AM		 3608#ifndef LEX_AT
3609 char *gotfree_input_line;
3610#endif
252b5132 3611 segT exp_seg = 0;
47926f60 3612 expressionS *exp;
252b5132
RH		 3613
3614 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3615 {
d0b47220 3616 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3617 return 0;
3618 }
3619
3620 exp = &im_expressions[i.imm_operands++];
520dc8e8 3621 i.op[this_operand].imms = exp;
252b5132
RH		 3622
3623 if (is_space_char (*imm_start))
3624 ++imm_start;
3625
3626 save_input_line_pointer = input_line_pointer;
3627 input_line_pointer = imm_start;
3628
3629#ifndef LEX_AT
f3c180ae
AM		 3630 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3631 if (gotfree_input_line)
3632 input_line_pointer = gotfree_input_line;
252b5132
RH		 3633#endif
3634
3635 exp_seg = expression (exp);
3636
83183c0c 3637 SKIP_WHITESPACE ();
252b5132 3638 if (*input_line_pointer)
f3c180ae 3639 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3640
3641 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3642#ifndef LEX_AT
3643 if (gotfree_input_line)
3644 free (gotfree_input_line);
3645#endif
252b5132 3646
2daf4fd8 3647 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3648 {
47926f60 3649 /* Missing or bad expr becomes absolute 0. */
d0b47220 3650 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3651 imm_start);
252b5132
RH		 3652 exp->X_op = O_constant;
3653 exp->X_add_number = 0;
3654 exp->X_add_symbol = (symbolS *) 0;
3655 exp->X_op_symbol = (symbolS *) 0;
252b5132 3656 }
3e73aa7c 3657 else if (exp->X_op == O_constant)
252b5132 3658 {
47926f60 3659 /* Size it properly later. */
3e73aa7c
JH		 3660 i.types[this_operand] |= Imm64;
3661 /* If BFD64, sign extend val. */
3662 if (!use_rela_relocations)
3663 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3664 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 3665 }
4c63da97 3666#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
47926f60 3667 else if (1
4c63da97 3668#ifdef BFD_ASSEMBLER
47926f60 3669 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3670#endif
31312f95 3671 && exp_seg != absolute_section
47926f60 3672 && exp_seg != text_section
24eab124
AM		 3673 && exp_seg != data_section
3674 && exp_seg != bss_section
3675 && exp_seg != undefined_section
252b5132 3676#ifdef BFD_ASSEMBLER
24eab124 3677 && !bfd_is_com_section (exp_seg)
252b5132 3678#endif
24eab124 3679 )
252b5132 3680 {
4c63da97 3681#ifdef BFD_ASSEMBLER
d0b47220 3682 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3683#else
d0b47220 3684 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3685#endif
252b5132
RH		 3686 return 0;
3687 }
3688#endif
3689 else
3690 {
3691 /* This is an address. The size of the address will be
24eab124 3692 determined later, depending on destination register,
3e73aa7c
JH		 3693 suffix, or the default for the section. */
3694 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
252b5132
RH		 3695 }
3696
3697 return 1;
3698}
3699
551c1ca1 3700static char *i386_scale PARAMS ((char *));
252b5132 3701
551c1ca1 3702static char *
252b5132
RH		 3703i386_scale (scale)
3704 char *scale;
3705{
551c1ca1
AM		 3706 offsetT val;
3707 char *save = input_line_pointer;
252b5132 3708
551c1ca1
AM		 3709 input_line_pointer = scale;
3710 val = get_absolute_expression ();
3711
3712 switch (val)
252b5132 3713 {
551c1ca1
AM		 3714 case 0:
3715 case 1:
252b5132
RH		 3716 i.log2_scale_factor = 0;
3717 break;
551c1ca1 3718 case 2:
252b5132
RH		 3719 i.log2_scale_factor = 1;
3720 break;
551c1ca1 3721 case 4:
252b5132
RH		 3722 i.log2_scale_factor = 2;
3723 break;
551c1ca1 3724 case 8:
252b5132
RH		 3725 i.log2_scale_factor = 3;
3726 break;
3727 default:
252b5132 3728 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
24eab124 3729 scale);
551c1ca1
AM		 3730 input_line_pointer = save;
3731 return NULL;
252b5132 3732 }
29b0f896 3733 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 3734 {
3735 as_warn (_("scale factor of %d without an index register"),
24eab124 3736 1 << i.log2_scale_factor);
252b5132
RH		 3737#if SCALE1_WHEN_NO_INDEX
3738 i.log2_scale_factor = 0;
3739#endif
3740 }
551c1ca1
AM		 3741 scale = input_line_pointer;
3742 input_line_pointer = save;
3743 return scale;
252b5132
RH		 3744}
3745
3746static int i386_displacement PARAMS ((char *, char *));
3747
3748static int
3749i386_displacement (disp_start, disp_end)
3750 char *disp_start;
3751 char *disp_end;
3752{
29b0f896 3753 expressionS *exp;
252b5132
RH		 3754 segT exp_seg = 0;
3755 char *save_input_line_pointer;
f3c180ae
AM		 3756#ifndef LEX_AT
3757 char *gotfree_input_line;
3758#endif
252b5132
RH		 3759 int bigdisp = Disp32;
3760
3e73aa7c 3761 if (flag_code == CODE_64BIT)
7ecd2f8b 3762 {
29b0f896
AM		 3763 if (i.prefix[ADDR_PREFIX] == 0)
3764 bigdisp = Disp64;
7ecd2f8b
JH		 3765 }
3766 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3767 bigdisp = Disp16;
252b5132
RH		 3768 i.types[this_operand] |= bigdisp;
3769
3770 exp = &disp_expressions[i.disp_operands];
520dc8e8 3771 i.op[this_operand].disps = exp;
252b5132
RH		 3772 i.disp_operands++;
3773 save_input_line_pointer = input_line_pointer;
3774 input_line_pointer = disp_start;
3775 END_STRING_AND_SAVE (disp_end);
3776
3777#ifndef GCC_ASM_O_HACK
3778#define GCC_ASM_O_HACK 0
3779#endif
3780#if GCC_ASM_O_HACK
3781 END_STRING_AND_SAVE (disp_end + 1);
3782 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 3783 && displacement_string_end[-1] == '+')
252b5132
RH		 3784 {
3785 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 3786 constraint within gcc asm statements.
3787 For instance:
3788
3789 #define _set_tssldt_desc(n,addr,limit,type) \
3790 __asm__ __volatile__ ( \
3791 "movw %w2,%0\n\t" \
3792 "movw %w1,2+%0\n\t" \
3793 "rorl $16,%1\n\t" \
3794 "movb %b1,4+%0\n\t" \
3795 "movb %4,5+%0\n\t" \
3796 "movb $0,6+%0\n\t" \
3797 "movb %h1,7+%0\n\t" \
3798 "rorl $16,%1" \
3799 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3800
3801 This works great except that the output assembler ends
3802 up looking a bit weird if it turns out that there is
3803 no offset. You end up producing code that looks like:
3804
3805 #APP
3806 movw $235,(%eax)
3807 movw %dx,2+(%eax)
3808 rorl $16,%edx
3809 movb %dl,4+(%eax)
3810 movb $137,5+(%eax)
3811 movb $0,6+(%eax)
3812 movb %dh,7+(%eax)
3813 rorl $16,%edx
3814 #NO_APP
3815
47926f60 3816 So here we provide the missing zero. */
24eab124
AM		 3817
3818 *displacement_string_end = '0';
252b5132
RH		 3819 }
3820#endif
3821#ifndef LEX_AT
f3c180ae
AM		 3822 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3823 if (gotfree_input_line)
3824 input_line_pointer = gotfree_input_line;
252b5132
RH		 3825#endif
3826
24eab124 3827 exp_seg = expression (exp);
252b5132 3828
636c26b0
AM		 3829 SKIP_WHITESPACE ();
3830 if (*input_line_pointer)
3831 as_bad (_("junk `%s' after expression"), input_line_pointer);
3832#if GCC_ASM_O_HACK
3833 RESTORE_END_STRING (disp_end + 1);
3834#endif
3835 RESTORE_END_STRING (disp_end);
3836 input_line_pointer = save_input_line_pointer;
3837#ifndef LEX_AT
3838 if (gotfree_input_line)
3839 free (gotfree_input_line);
3840#endif
3841
252b5132 3842#ifdef BFD_ASSEMBLER
24eab124
AM		 3843 /* We do this to make sure that the section symbol is in
3844 the symbol table. We will ultimately change the relocation
47926f60 3845 to be relative to the beginning of the section. */
1ae12ab7
AM		 3846 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3847 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
24eab124 3848 {
636c26b0
AM		 3849 if (exp->X_op != O_symbol)
3850 {
3851 as_bad (_("bad expression used with @%s"),
3852 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3853 ? "GOTPCREL"
3854 : "GOTOFF"));
3855 return 0;
3856 }
3857
e5cb08ac 3858 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 3859 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3860 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 3861 exp->X_op = O_subtract;
3862 exp->X_op_symbol = GOT_symbol;
1ae12ab7 3863 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 3864 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
23df1078 3865 else
29b0f896 3866 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 3867 }
252b5132
RH		 3868#endif
3869
2daf4fd8
AM		 3870 if (exp->X_op == O_absent || exp->X_op == O_big)
3871 {
47926f60 3872 /* Missing or bad expr becomes absolute 0. */
d0b47220 3873 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 3874 disp_start);
3875 exp->X_op = O_constant;
3876 exp->X_add_number = 0;
3877 exp->X_add_symbol = (symbolS *) 0;
3878 exp->X_op_symbol = (symbolS *) 0;
3879 }
3880
4c63da97 3881#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 3882 if (exp->X_op != O_constant
4c63da97 3883#ifdef BFD_ASSEMBLER
45288df1 3884 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3885#endif
31312f95 3886 && exp_seg != absolute_section
45288df1
AM		 3887 && exp_seg != text_section
3888 && exp_seg != data_section
3889 && exp_seg != bss_section
31312f95
AM		 3890 && exp_seg != undefined_section
3891#ifdef BFD_ASSEMBLER
3892 && !bfd_is_com_section (exp_seg)
3893#endif
3894 )
24eab124 3895 {
4c63da97 3896#ifdef BFD_ASSEMBLER
d0b47220 3897 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3898#else
d0b47220 3899 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3900#endif
24eab124
AM		 3901 return 0;
3902 }
252b5132 3903#endif
3e73aa7c
JH		 3904 else if (flag_code == CODE_64BIT)
3905 i.types[this_operand] |= Disp32S | Disp32;
252b5132
RH		 3906 return 1;
3907}
3908
e5cb08ac 3909static int i386_index_check PARAMS ((const char *));
252b5132 3910
eecb386c 3911/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 3912 Return 1 on success, 0 on a failure. */
3913
252b5132 3914static int
eecb386c
AM		 3915i386_index_check (operand_string)
3916 const char *operand_string;
252b5132 3917{
3e73aa7c 3918 int ok;
24eab124 3919#if INFER_ADDR_PREFIX
eecb386c
AM		 3920 int fudged = 0;
3921
24eab124
AM		 3922 tryprefix:
3923#endif
3e73aa7c
JH		 3924 ok = 1;
3925 if (flag_code == CODE_64BIT)
3926 {
7ecd2f8b
JH		 3927 if (i.prefix[ADDR_PREFIX] == 0)
3928 {
3929 /* 64bit checks. */
3930 if ((i.base_reg
3931 && ((i.base_reg->reg_type & Reg64) == 0)
3932 && (i.base_reg->reg_type != BaseIndex
3933 || i.index_reg))
3934 || (i.index_reg
29b0f896
AM		 3935 && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
3936 != (Reg64 | BaseIndex))))
7ecd2f8b
JH		 3937 ok = 0;
3938 }
3939 else
3940 {
3941 /* 32bit checks. */
3942 if ((i.base_reg
3943 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3944 || (i.index_reg
29b0f896
AM		 3945 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3946 != (Reg32 | BaseIndex))))
7ecd2f8b
JH		 3947 ok = 0;
3948 }
3e73aa7c
JH		 3949 }
3950 else
3951 {
3952 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3953 {
3954 /* 16bit checks. */
3955 if ((i.base_reg
29b0f896
AM		 3956 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
3957 != (Reg16 | BaseIndex)))
3e73aa7c 3958 || (i.index_reg
29b0f896
AM		 3959 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
3960 != (Reg16 | BaseIndex))
3961 || !(i.base_reg
3962 && i.base_reg->reg_num < 6
3963 && i.index_reg->reg_num >= 6
3964 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 3965 ok = 0;
3966 }
3967 else
e5cb08ac 3968 {
3e73aa7c
JH		 3969 /* 32bit checks. */
3970 if ((i.base_reg
3971 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3972 || (i.index_reg
29b0f896
AM		 3973 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3974 != (Reg32 | BaseIndex))))
e5cb08ac 3975 ok = 0;
3e73aa7c
JH		 3976 }
3977 }
3978 if (!ok)
24eab124
AM		 3979 {
3980#if INFER_ADDR_PREFIX
3e73aa7c
JH		 3981 if (flag_code != CODE_64BIT
3982 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
24eab124
AM		 3983 {
3984 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3985 i.prefixes += 1;
b23bac36
AM		 3986 /* Change the size of any displacement too. At most one of
3987 Disp16 or Disp32 is set.
3988 FIXME. There doesn't seem to be any real need for separate
3989 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 3990 Removing them would probably clean up the code quite a lot. */
29b0f896
AM		 3991 if (i.types[this_operand] & (Disp16 | Disp32))
3992 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 3993 fudged = 1;
24eab124
AM		 3994 goto tryprefix;
3995 }
eecb386c
AM		 3996 if (fudged)
3997 as_bad (_("`%s' is not a valid base/index expression"),
3998 operand_string);
3999 else
c388dee8 4000#endif
eecb386c
AM		 4001 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4002 operand_string,
3e73aa7c 4003 flag_code_names[flag_code]);
eecb386c 4004 return 0;
24eab124
AM		 4005 }
4006 return 1;
4007}
252b5132 4008
252b5132 4009/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4010 on error. */
252b5132 4011
252b5132
RH		 4012static int
4013i386_operand (operand_string)
4014 char *operand_string;
4015{
af6bdddf
AM		 4016 const reg_entry *r;
4017 char *end_op;
24eab124 4018 char *op_string = operand_string;
252b5132 4019
24eab124 4020 if (is_space_char (*op_string))
252b5132
RH		 4021 ++op_string;
4022
24eab124 4023 /* We check for an absolute prefix (differentiating,
47926f60 4024 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4025 if (*op_string == ABSOLUTE_PREFIX)
4026 {
4027 ++op_string;
4028 if (is_space_char (*op_string))
4029 ++op_string;
4030 i.types[this_operand] |= JumpAbsolute;
4031 }
252b5132 4032
47926f60 4033 /* Check if operand is a register. */
af6bdddf
AM		 4034 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4035 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4036 {
24eab124
AM		 4037 /* Check for a segment override by searching for ':' after a
4038 segment register. */
4039 op_string = end_op;
4040 if (is_space_char (*op_string))
4041 ++op_string;
4042 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4043 {
4044 switch (r->reg_num)
4045 {
4046 case 0:
4047 i.seg[i.mem_operands] = &es;
4048 break;
4049 case 1:
4050 i.seg[i.mem_operands] = &cs;
4051 break;
4052 case 2:
4053 i.seg[i.mem_operands] = &ss;
4054 break;
4055 case 3:
4056 i.seg[i.mem_operands] = &ds;
4057 break;
4058 case 4:
4059 i.seg[i.mem_operands] = &fs;
4060 break;
4061 case 5:
4062 i.seg[i.mem_operands] = &gs;
4063 break;
4064 }
252b5132 4065
24eab124 4066 /* Skip the ':' and whitespace. */
252b5132
RH		 4067 ++op_string;
4068 if (is_space_char (*op_string))
24eab124 4069 ++op_string;
252b5132 4070
24eab124
AM		 4071 if (!is_digit_char (*op_string)
4072 && !is_identifier_char (*op_string)
4073 && *op_string != '('
4074 && *op_string != ABSOLUTE_PREFIX)
4075 {
4076 as_bad (_("bad memory operand `%s'"), op_string);
4077 return 0;
4078 }
47926f60 4079 /* Handle case of %es:*foo. */
24eab124
AM		 4080 if (*op_string == ABSOLUTE_PREFIX)
4081 {
4082 ++op_string;
4083 if (is_space_char (*op_string))
4084 ++op_string;
4085 i.types[this_operand] |= JumpAbsolute;
4086 }
4087 goto do_memory_reference;
4088 }
4089 if (*op_string)
4090 {
d0b47220 4091 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4092 return 0;
4093 }
4094 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4095 i.op[this_operand].regs = r;
24eab124
AM		 4096 i.reg_operands++;
4097 }
af6bdddf
AM		 4098 else if (*op_string == REGISTER_PREFIX)
4099 {
4100 as_bad (_("bad register name `%s'"), op_string);
4101 return 0;
4102 }
24eab124 4103 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4104 {
24eab124
AM		 4105 ++op_string;
4106 if (i.types[this_operand] & JumpAbsolute)
4107 {
d0b47220 4108 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4109 return 0;
4110 }
4111 if (!i386_immediate (op_string))
4112 return 0;
4113 }
4114 else if (is_digit_char (*op_string)
4115 || is_identifier_char (*op_string)
e5cb08ac 4116 || *op_string == '(')
24eab124 4117 {
47926f60 4118 /* This is a memory reference of some sort. */
af6bdddf 4119 char *base_string;
252b5132 4120
47926f60 4121 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4122 char *displacement_string_start;
4123 char *displacement_string_end;
252b5132 4124
24eab124 4125 do_memory_reference:
24eab124
AM		 4126 if ((i.mem_operands == 1
4127 && (current_templates->start->opcode_modifier & IsString) == 0)
4128 || i.mem_operands == 2)
4129 {
4130 as_bad (_("too many memory references for `%s'"),
4131 current_templates->start->name);
4132 return 0;
4133 }
252b5132 4134
24eab124
AM		 4135 /* Check for base index form. We detect the base index form by
4136 looking for an ')' at the end of the operand, searching
4137 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4138 after the '('. */
af6bdddf 4139 base_string = op_string + strlen (op_string);
c3332e24 4140
af6bdddf
AM		 4141 --base_string;
4142 if (is_space_char (*base_string))
4143 --base_string;
252b5132 4144
47926f60 4145 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4146 displacement_string_start = op_string;
4147 displacement_string_end = base_string + 1;
252b5132 4148
24eab124
AM		 4149 if (*base_string == ')')
4150 {
af6bdddf 4151 char *temp_string;
24eab124
AM		 4152 unsigned int parens_balanced = 1;
4153 /* We've already checked that the number of left & right ()'s are
47926f60 4154 equal, so this loop will not be infinite. */
24eab124
AM		 4155 do
4156 {
4157 base_string--;
4158 if (*base_string == ')')
4159 parens_balanced++;
4160 if (*base_string == '(')
4161 parens_balanced--;
4162 }
4163 while (parens_balanced);
c3332e24 4164
af6bdddf 4165 temp_string = base_string;
c3332e24 4166
24eab124 4167 /* Skip past '(' and whitespace. */
252b5132
RH		 4168 ++base_string;
4169 if (is_space_char (*base_string))
24eab124 4170 ++base_string;
252b5132 4171
af6bdddf
AM		 4172 if (*base_string == ','
4173 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4174 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4175 {
af6bdddf 4176 displacement_string_end = temp_string;
252b5132 4177
af6bdddf 4178 i.types[this_operand] |= BaseIndex;
252b5132 4179
af6bdddf 4180 if (i.base_reg)
24eab124 4181 {
24eab124
AM		 4182 base_string = end_op;
4183 if (is_space_char (*base_string))
4184 ++base_string;
af6bdddf
AM		 4185 }
4186
4187 /* There may be an index reg or scale factor here. */
4188 if (*base_string == ',')
4189 {
4190 ++base_string;
4191 if (is_space_char (*base_string))
4192 ++base_string;
4193
4194 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4195 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4196 {
af6bdddf 4197 base_string = end_op;
24eab124
AM		 4198 if (is_space_char (*base_string))
4199 ++base_string;
af6bdddf
AM		 4200 if (*base_string == ',')
4201 {
4202 ++base_string;
4203 if (is_space_char (*base_string))
4204 ++base_string;
4205 }
e5cb08ac 4206 else if (*base_string != ')')
af6bdddf
AM		 4207 {
4208 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4209 operand_string);
4210 return 0;
4211 }
24eab124 4212 }
af6bdddf 4213 else if (*base_string == REGISTER_PREFIX)
24eab124 4214 {
af6bdddf 4215 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4216 return 0;
4217 }
252b5132 4218
47926f60 4219 /* Check for scale factor. */
551c1ca1 4220 if (*base_string != ')')
af6bdddf 4221 {
551c1ca1
AM		 4222 char *end_scale = i386_scale (base_string);
4223
4224 if (!end_scale)
af6bdddf 4225 return 0;
24eab124 4226
551c1ca1 4227 base_string = end_scale;
af6bdddf
AM		 4228 if (is_space_char (*base_string))
4229 ++base_string;
4230 if (*base_string != ')')
4231 {
4232 as_bad (_("expecting `)' after scale factor in `%s'"),
4233 operand_string);
4234 return 0;
4235 }
4236 }
4237 else if (!i.index_reg)
24eab124 4238 {
af6bdddf
AM		 4239 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4240 *base_string);
24eab124
AM		 4241 return 0;
4242 }
4243 }
af6bdddf 4244 else if (*base_string != ')')
24eab124 4245 {
af6bdddf
AM		 4246 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4247 operand_string);
24eab124
AM		 4248 return 0;
4249 }
c3332e24 4250 }
af6bdddf 4251 else if (*base_string == REGISTER_PREFIX)
c3332e24 4252 {
af6bdddf 4253 as_bad (_("bad register name `%s'"), base_string);
24eab124 4254 return 0;
c3332e24 4255 }
24eab124
AM		 4256 }
4257
4258 /* If there's an expression beginning the operand, parse it,
4259 assuming displacement_string_start and
4260 displacement_string_end are meaningful. */
4261 if (displacement_string_start != displacement_string_end)
4262 {
4263 if (!i386_displacement (displacement_string_start,
4264 displacement_string_end))
4265 return 0;
4266 }
4267
4268 /* Special case for (%dx) while doing input/output op. */
4269 if (i.base_reg
4270 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4271 && i.index_reg == 0
4272 && i.log2_scale_factor == 0
4273 && i.seg[i.mem_operands] == 0
4274 && (i.types[this_operand] & Disp) == 0)
4275 {
4276 i.types[this_operand] = InOutPortReg;
4277 return 1;
4278 }
4279
eecb386c
AM		 4280 if (i386_index_check (operand_string) == 0)
4281 return 0;
24eab124
AM		 4282 i.mem_operands++;
4283 }
4284 else
ce8a8b2f
AM		 4285 {
4286 /* It's not a memory operand; argh! */
24eab124
AM		 4287 as_bad (_("invalid char %s beginning operand %d `%s'"),
4288 output_invalid (*op_string),
4289 this_operand + 1,
4290 op_string);
4291 return 0;
4292 }
47926f60 4293 return 1; /* Normal return. */
252b5132
RH		 4294}
4295\f
ee7fcc42
AM		 4296/* md_estimate_size_before_relax()
4297
4298 Called just before relax() for rs_machine_dependent frags. The x86
4299 assembler uses these frags to handle variable size jump
4300 instructions.
4301
4302 Any symbol that is now undefined will not become defined.
4303 Return the correct fr_subtype in the frag.
4304 Return the initial "guess for variable size of frag" to caller.
4305 The guess is actually the growth beyond the fixed part. Whatever
4306 we do to grow the fixed or variable part contributes to our
4307 returned value. */
4308
252b5132
RH		 4309int
4310md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4311 fragS *fragP;
4312 segT segment;
252b5132 4313{
252b5132 4314 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4315 check for un-relaxable symbols. On an ELF system, we can't relax
4316 an externally visible symbol, because it may be overridden by a
4317 shared library. */
4318 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4319#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 4320 || (OUTPUT_FLAVOR == bfd_target_elf_flavour
4321 && (S_IS_EXTERNAL (fragP->fr_symbol)
4322 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4323#endif
4324 )
252b5132 4325 {
b98ef147
AM		 4326 /* Symbol is undefined in this segment, or we need to keep a
4327 reloc so that weak symbols can be overridden. */
4328 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f3c180ae 4329 RELOC_ENUM reloc_type;
ee7fcc42
AM		 4330 unsigned char *opcode;
4331 int old_fr_fix;
f6af82bd 4332
ee7fcc42
AM		 4333 if (fragP->fr_var != NO_RELOC)
4334 reloc_type = fragP->fr_var;
b98ef147 4335 else if (size == 2)
f6af82bd
AM		 4336 reloc_type = BFD_RELOC_16_PCREL;
4337 else
4338 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4339
ee7fcc42
AM		 4340 old_fr_fix = fragP->fr_fix;
4341 opcode = (unsigned char *) fragP->fr_opcode;
4342
fddf5b5b 4343 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4344 {
fddf5b5b
AM		 4345 case UNCOND_JUMP:
4346 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4347 opcode[0] = 0xe9;
252b5132 4348 fragP->fr_fix += size;
062cd5e7
AS		 4349 fix_new (fragP, old_fr_fix, size,
4350 fragP->fr_symbol,
4351 fragP->fr_offset, 1,
4352 reloc_type);
252b5132
RH		 4353 break;
4354
fddf5b5b 4355 case COND_JUMP86:
412167cb
AM		 4356 if (size == 2
4357 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4358 {
4359 /* Negate the condition, and branch past an
4360 unconditional jump. */
4361 opcode[0] ^= 1;
4362 opcode[1] = 3;
4363 /* Insert an unconditional jump. */
4364 opcode[2] = 0xe9;
4365 /* We added two extra opcode bytes, and have a two byte
4366 offset. */
4367 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4368 fix_new (fragP, old_fr_fix + 2, 2,
4369 fragP->fr_symbol,
4370 fragP->fr_offset, 1,
4371 reloc_type);
fddf5b5b
AM		 4372 break;
4373 }
4374 /* Fall through. */
4375
4376 case COND_JUMP:
412167cb
AM		 4377 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4378 {
4379 fragP->fr_fix += 1;
4380 fix_new (fragP, old_fr_fix, 1,
4381 fragP->fr_symbol,
4382 fragP->fr_offset, 1,
4383 BFD_RELOC_8_PCREL);
4384 break;
4385 }
93c2a809 4386
24eab124 4387 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4388 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4389 opcode[1] = opcode[0] + 0x10;
f6af82bd 4390 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4391 /* We've added an opcode byte. */
4392 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4393 fix_new (fragP, old_fr_fix + 1, size,
4394 fragP->fr_symbol,
4395 fragP->fr_offset, 1,
4396 reloc_type);
252b5132 4397 break;
fddf5b5b
AM		 4398
4399 default:
4400 BAD_CASE (fragP->fr_subtype);
4401 break;
252b5132
RH		 4402 }
4403 frag_wane (fragP);
ee7fcc42 4404 return fragP->fr_fix - old_fr_fix;
252b5132 4405 }
93c2a809 4406
93c2a809
AM		 4407 /* Guess size depending on current relax state. Initially the relax
4408 state will correspond to a short jump and we return 1, because
4409 the variable part of the frag (the branch offset) is one byte
4410 long. However, we can relax a section more than once and in that
4411 case we must either set fr_subtype back to the unrelaxed state,
4412 or return the value for the appropriate branch. */
4413 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4414}
4415
47926f60
KH		 4416/* Called after relax() is finished.
4417
4418 In: Address of frag.
4419 fr_type == rs_machine_dependent.
4420 fr_subtype is what the address relaxed to.
4421
4422 Out: Any fixSs and constants are set up.
4423 Caller will turn frag into a ".space 0". */
4424
252b5132
RH		 4425#ifndef BFD_ASSEMBLER
4426void
4427md_convert_frag (headers, sec, fragP)
a04b544b
ILT		 4428 object_headers *headers ATTRIBUTE_UNUSED;
4429 segT sec ATTRIBUTE_UNUSED;
29b0f896 4430 fragS *fragP;
252b5132
RH		 4431#else
4432void
4433md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4434 bfd *abfd ATTRIBUTE_UNUSED;
4435 segT sec ATTRIBUTE_UNUSED;
29b0f896 4436 fragS *fragP;
252b5132
RH		 4437#endif
4438{
29b0f896 4439 unsigned char *opcode;
252b5132 4440 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4441 offsetT target_address;
4442 offsetT opcode_address;
252b5132 4443 unsigned int extension = 0;
847f7ad4 4444 offsetT displacement_from_opcode_start;
252b5132
RH		 4445
4446 opcode = (unsigned char *) fragP->fr_opcode;
4447
47926f60 4448 /* Address we want to reach in file space. */
252b5132 4449 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4450
47926f60 4451 /* Address opcode resides at in file space. */
252b5132
RH		 4452 opcode_address = fragP->fr_address + fragP->fr_fix;
4453
47926f60 4454 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4455 displacement_from_opcode_start = target_address - opcode_address;
4456
fddf5b5b 4457 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4458 {
47926f60
KH		 4459 /* Don't have to change opcode. */
4460 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4461 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4462 }
4463 else
4464 {
4465 if (no_cond_jump_promotion
4466 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4467 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4468
fddf5b5b
AM		 4469 switch (fragP->fr_subtype)
4470 {
4471 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4472 extension = 4; /* 1 opcode + 4 displacement */
4473 opcode[0] = 0xe9;
4474 where_to_put_displacement = &opcode[1];
4475 break;
252b5132 4476
fddf5b5b
AM		 4477 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4478 extension = 2; /* 1 opcode + 2 displacement */
4479 opcode[0] = 0xe9;
4480 where_to_put_displacement = &opcode[1];
4481 break;
252b5132 4482
fddf5b5b
AM		 4483 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4484 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4485 extension = 5; /* 2 opcode + 4 displacement */
4486 opcode[1] = opcode[0] + 0x10;
4487 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4488 where_to_put_displacement = &opcode[2];
4489 break;
252b5132 4490
fddf5b5b
AM		 4491 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4492 extension = 3; /* 2 opcode + 2 displacement */
4493 opcode[1] = opcode[0] + 0x10;
4494 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4495 where_to_put_displacement = &opcode[2];
4496 break;
252b5132 4497
fddf5b5b
AM		 4498 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4499 extension = 4;
4500 opcode[0] ^= 1;
4501 opcode[1] = 3;
4502 opcode[2] = 0xe9;
4503 where_to_put_displacement = &opcode[3];
4504 break;
4505
4506 default:
4507 BAD_CASE (fragP->fr_subtype);
4508 break;
4509 }
252b5132 4510 }
fddf5b5b 4511
47926f60 4512 /* Now put displacement after opcode. */
252b5132
RH		 4513 md_number_to_chars ((char *) where_to_put_displacement,
4514 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4515 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4516 fragP->fr_fix += extension;
4517}
4518\f
47926f60
KH		 4519/* Size of byte displacement jmp. */
4520int md_short_jump_size = 2;
4521
4522/* Size of dword displacement jmp. */
4523int md_long_jump_size = 5;
252b5132 4524
47926f60
KH		 4525/* Size of relocation record. */
4526const int md_reloc_size = 8;
252b5132
RH		 4527
4528void
4529md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4530 char *ptr;
4531 addressT from_addr, to_addr;
ab9da554
ILT		 4532 fragS *frag ATTRIBUTE_UNUSED;
4533 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4534{
847f7ad4 4535 offsetT offset;
252b5132
RH		 4536
4537 offset = to_addr - (from_addr + 2);
47926f60
KH		 4538 /* Opcode for byte-disp jump. */
4539 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4540 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4541}
4542
4543void
4544md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4545 char *ptr;
4546 addressT from_addr, to_addr;
a38cf1db
AM		 4547 fragS *frag ATTRIBUTE_UNUSED;
4548 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4549{
847f7ad4 4550 offsetT offset;
252b5132 4551
a38cf1db
AM		 4552 offset = to_addr - (from_addr + 5);
4553 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4554 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4555}
4556\f
4557/* Apply a fixup (fixS) to segment data, once it has been determined
4558 by our caller that we have all the info we need to fix it up.
4559
4560 On the 386, immediates, displacements, and data pointers are all in
4561 the same (little-endian) format, so we don't need to care about which
4562 we are handling. */
4563
94f592af
NC		 4564void
4565md_apply_fix3 (fixP, valP, seg)
47926f60
KH		 4566 /* The fix we're to put in. */
4567 fixS *fixP;
47926f60 4568 /* Pointer to the value of the bits. */
c6682705 4569 valueT *valP;
47926f60
KH		 4570 /* Segment fix is from. */
4571 segT seg ATTRIBUTE_UNUSED;
252b5132 4572{
94f592af 4573 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4574 valueT value = *valP;
252b5132 4575
e1b283bb 4576#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
93382f6d
AM		 4577 if (fixP->fx_pcrel)
4578 {
4579 switch (fixP->fx_r_type)
4580 {
5865bb77
ILT		 4581 default:
4582 break;
4583
93382f6d
AM		 4584 case BFD_RELOC_32:
4585 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4586 break;
4587 case BFD_RELOC_16:
4588 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4589 break;
4590 case BFD_RELOC_8:
4591 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4592 break;
4593 }
4594 }
252b5132 4595
a161fe53 4596 if (fixP->fx_addsy != NULL
31312f95
AM		 4597 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
4598 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4599 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4600 && !use_rela_relocations)
252b5132 4601 {
31312f95
AM		 4602 /* This is a hack. There should be a better way to handle this.
4603 This covers for the fact that bfd_install_relocation will
4604 subtract the current location (for partial_inplace, PC relative
4605 relocations); see more below. */
252b5132
RH		 4606#ifndef OBJ_AOUT
4607 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4608#ifdef TE_PE
4609 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4610#endif
4611 )
4612 value += fixP->fx_where + fixP->fx_frag->fr_address;
4613#endif
4614#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 4615 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 4616 {
2f66722d
AM		 4617 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
4618
4619 if ((fseg == seg
4620 || (symbol_section_p (fixP->fx_addsy)
4621 && fseg != absolute_section))
29b0f896
AM		 4622 && !S_IS_EXTERNAL (fixP->fx_addsy)
4623 && !S_IS_WEAK (fixP->fx_addsy)
2f66722d 4624 && S_IS_DEFINED (fixP->fx_addsy)
29b0f896 4625 && !S_IS_COMMON (fixP->fx_addsy))
2f66722d
AM		 4626 {
4627 /* Yes, we add the values in twice. This is because
4628 bfd_perform_relocation subtracts them out again. I think
4629 bfd_perform_relocation is broken, but I don't dare change
4630 it. FIXME. */
4631 value += fixP->fx_where + fixP->fx_frag->fr_address;
4632 }
252b5132
RH		 4633 }
4634#endif
4635#if defined (OBJ_COFF) && defined (TE_PE)
4636 /* For some reason, the PE format does not store a section
24eab124 4637 address offset for a PC relative symbol. */
252b5132
RH		 4638 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4639 value += md_pcrel_from (fixP);
4640#endif
4641 }
4642
4643 /* Fix a few things - the dynamic linker expects certain values here,
47926f60 4644 and we must not dissappoint it. */
252b5132
RH		 4645#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4646 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4647 && fixP->fx_addsy)
47926f60
KH		 4648 switch (fixP->fx_r_type)
4649 {
4650 case BFD_RELOC_386_PLT32:
3e73aa7c 4651 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4652 /* Make the jump instruction point to the address of the operand. At
4653 runtime we merely add the offset to the actual PLT entry. */
4654 value = -4;
4655 break;
31312f95 4656
47926f60 4657 case BFD_RELOC_386_GOT32:
13ae64f3
JJ		 4658 case BFD_RELOC_386_TLS_GD:
4659 case BFD_RELOC_386_TLS_LDM:
13ae64f3 4660 case BFD_RELOC_386_TLS_IE_32:
3e73aa7c 4661 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 4662 value = 0; /* Fully resolved at runtime. No addend. */
4663 break;
47926f60
KH		 4664
4665 case BFD_RELOC_VTABLE_INHERIT:
4666 case BFD_RELOC_VTABLE_ENTRY:
4667 fixP->fx_done = 0;
94f592af 4668 return;
47926f60
KH		 4669
4670 default:
4671 break;
4672 }
4673#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 4674 *valP = value;
47926f60 4675#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
3e73aa7c 4676
3e73aa7c 4677 /* Are we finished with this relocation now? */
c6682705 4678 if (fixP->fx_addsy == NULL)
3e73aa7c 4679 fixP->fx_done = 1;
94f592af 4680#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4681 else if (use_rela_relocations)
4682 {
4683 fixP->fx_no_overflow = 1;
062cd5e7
AS		 4684 /* Remember value for tc_gen_reloc. */
4685 fixP->fx_addnumber = value;
3e73aa7c
JH		 4686 value = 0;
4687 }
3e73aa7c 4688#endif
94f592af 4689 md_number_to_chars (p, value, fixP->fx_size);
252b5132 4690}
252b5132 4691\f
252b5132
RH		 4692#define MAX_LITTLENUMS 6
4693
47926f60
KH		 4694/* Turn the string pointed to by litP into a floating point constant
4695 of type TYPE, and emit the appropriate bytes. The number of
4696 LITTLENUMS emitted is stored in *SIZEP. An error message is
4697 returned, or NULL on OK. */
4698
252b5132
RH		 4699char *
4700md_atof (type, litP, sizeP)
2ab9b79e 4701 int type;
252b5132
RH		 4702 char *litP;
4703 int *sizeP;
4704{
4705 int prec;
4706 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4707 LITTLENUM_TYPE *wordP;
4708 char *t;
4709
4710 switch (type)
4711 {
4712 case 'f':
4713 case 'F':
4714 prec = 2;
4715 break;
4716
4717 case 'd':
4718 case 'D':
4719 prec = 4;
4720 break;
4721
4722 case 'x':
4723 case 'X':
4724 prec = 5;
4725 break;
4726
4727 default:
4728 *sizeP = 0;
4729 return _("Bad call to md_atof ()");
4730 }
4731 t = atof_ieee (input_line_pointer, type, words);
4732 if (t)
4733 input_line_pointer = t;
4734
4735 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4736 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4737 the bigendian 386. */
4738 for (wordP = words + prec - 1; prec--;)
4739 {
4740 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4741 litP += sizeof (LITTLENUM_TYPE);
4742 }
4743 return 0;
4744}
4745\f
4746char output_invalid_buf[8];
4747
252b5132
RH		 4748static char *
4749output_invalid (c)
4750 int c;
4751{
3882b010 4752 if (ISPRINT (c))
252b5132
RH		 4753 sprintf (output_invalid_buf, "'%c'", c);
4754 else
4755 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4756 return output_invalid_buf;
4757}
4758
af6bdddf 4759/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 4760
4761static const reg_entry *
4762parse_register (reg_string, end_op)
4763 char *reg_string;
4764 char **end_op;
4765{
af6bdddf
AM		 4766 char *s = reg_string;
4767 char *p;
252b5132
RH		 4768 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4769 const reg_entry *r;
4770
4771 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4772 if (*s == REGISTER_PREFIX)
4773 ++s;
4774
4775 if (is_space_char (*s))
4776 ++s;
4777
4778 p = reg_name_given;
af6bdddf 4779 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 4780 {
4781 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 4782 return (const reg_entry *) NULL;
4783 s++;
252b5132
RH		 4784 }
4785
6588847e
DN		 4786 /* For naked regs, make sure that we are not dealing with an identifier.
4787 This prevents confusing an identifier like `eax_var' with register
4788 `eax'. */
4789 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4790 return (const reg_entry *) NULL;
4791
af6bdddf 4792 *end_op = s;
252b5132
RH		 4793
4794 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4795
5f47d35b 4796 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 4797 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 4798 {
5f47d35b
AM		 4799 if (is_space_char (*s))
4800 ++s;
4801 if (*s == '(')
4802 {
af6bdddf 4803 ++s;
5f47d35b
AM		 4804 if (is_space_char (*s))
4805 ++s;
4806 if (*s >= '0' && *s <= '7')
4807 {
4808 r = &i386_float_regtab[*s - '0'];
af6bdddf 4809 ++s;
5f47d35b
AM		 4810 if (is_space_char (*s))
4811 ++s;
4812 if (*s == ')')
4813 {
4814 *end_op = s + 1;
4815 return r;
4816 }
5f47d35b 4817 }
47926f60 4818 /* We have "%st(" then garbage. */
5f47d35b
AM		 4819 return (const reg_entry *) NULL;
4820 }
4821 }
4822
1ae00879 4823 if (r != NULL
29b0f896 4824 && (r->reg_flags & (RegRex64 | RegRex)) != 0
1ae00879
AM		 4825 && flag_code != CODE_64BIT)
4826 {
4827 return (const reg_entry *) NULL;
4828 }
4829
252b5132
RH		 4830 return r;
4831}
4832\f
4cc782b5 4833#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
65172ab8 4834const char *md_shortopts = "kVQ:sq";
252b5132 4835#else
65172ab8 4836const char *md_shortopts = "q";
252b5132 4837#endif
6e0b89ee 4838
252b5132 4839struct option md_longopts[] = {
3e73aa7c
JH		 4840#define OPTION_32 (OPTION_MD_BASE + 0)
4841 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 4842#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 4843#define OPTION_64 (OPTION_MD_BASE + 1)
4844 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 4845#endif
252b5132
RH		 4846 {NULL, no_argument, NULL, 0}
4847};
4848size_t md_longopts_size = sizeof (md_longopts);
4849
4850int
4851md_parse_option (c, arg)
4852 int c;
ab9da554 4853 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 4854{
4855 switch (c)
4856 {
a38cf1db
AM		 4857 case 'q':
4858 quiet_warnings = 1;
252b5132
RH		 4859 break;
4860
4861#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 4862 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4863 should be emitted or not. FIXME: Not implemented. */
4864 case 'Q':
252b5132
RH		 4865 break;
4866
4867 /* -V: SVR4 argument to print version ID. */
4868 case 'V':
4869 print_version_id ();
4870 break;
4871
a38cf1db
AM		 4872 /* -k: Ignore for FreeBSD compatibility. */
4873 case 'k':
252b5132 4874 break;
4cc782b5
ILT		 4875
4876 case 's':
4877 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 4878 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 4879 break;
6e0b89ee 4880
3e73aa7c
JH		 4881 case OPTION_64:
4882 {
4883 const char **list, **l;
4884
3e73aa7c
JH		 4885 list = bfd_target_list ();
4886 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 4887 if (strcmp (*l, "elf64-x86-64") == 0)
4888 {
4889 default_arch = "x86_64";
4890 break;
4891 }
3e73aa7c 4892 if (*l == NULL)
6e0b89ee 4893 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 4894 free (list);
4895 }
4896 break;
4897#endif
252b5132 4898
6e0b89ee
AM		 4899 case OPTION_32:
4900 default_arch = "i386";
4901 break;
4902
252b5132
RH		 4903 default:
4904 return 0;
4905 }
4906 return 1;
4907}
4908
4909void
4910md_show_usage (stream)
4911 FILE *stream;
4912{
4cc782b5
ILT		 4913#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4914 fprintf (stream, _("\
a38cf1db
AM		 4915 -Q ignored\n\
4916 -V print assembler version number\n\
4917 -k ignored\n\
4918 -q quieten some warnings\n\
4919 -s ignored\n"));
4920#else
4921 fprintf (stream, _("\
4922 -q quieten some warnings\n"));
4cc782b5 4923#endif
252b5132
RH		 4924}
4925
4926#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4927#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4928 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 4929
4930/* Pick the target format to use. */
4931
47926f60 4932const char *
252b5132
RH		 4933i386_target_format ()
4934{
3e73aa7c
JH		 4935 if (!strcmp (default_arch, "x86_64"))
4936 set_code_flag (CODE_64BIT);
4937 else if (!strcmp (default_arch, "i386"))
4938 set_code_flag (CODE_32BIT);
4939 else
4940 as_fatal (_("Unknown architecture"));
252b5132
RH		 4941 switch (OUTPUT_FLAVOR)
4942 {
4c63da97
AM		 4943#ifdef OBJ_MAYBE_AOUT
4944 case bfd_target_aout_flavour:
47926f60 4945 return AOUT_TARGET_FORMAT;
4c63da97
AM		 4946#endif
4947#ifdef OBJ_MAYBE_COFF
252b5132
RH		 4948 case bfd_target_coff_flavour:
4949 return "coff-i386";
4c63da97 4950#endif
3e73aa7c 4951#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 4952 case bfd_target_elf_flavour:
3e73aa7c 4953 {
e5cb08ac
KH		 4954 if (flag_code == CODE_64BIT)
4955 use_rela_relocations = 1;
4ada7262 4956 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 4957 }
4c63da97 4958#endif
252b5132
RH		 4959 default:
4960 abort ();
4961 return NULL;
4962 }
4963}
4964
47926f60 4965#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 4966
4967#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4968void i386_elf_emit_arch_note ()
4969{
4970 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4971 && cpu_arch_name != NULL)
4972 {
4973 char *p;
4974 asection *seg = now_seg;
4975 subsegT subseg = now_subseg;
4976 Elf_Internal_Note i_note;
4977 Elf_External_Note e_note;
4978 asection *note_secp;
4979 int len;
4980
4981 /* Create the .note section. */
4982 note_secp = subseg_new (".note", 0);
4983 bfd_set_section_flags (stdoutput,
4984 note_secp,
4985 SEC_HAS_CONTENTS | SEC_READONLY);
4986
4987 /* Process the arch string. */
4988 len = strlen (cpu_arch_name);
4989
4990 i_note.namesz = len + 1;
4991 i_note.descsz = 0;
4992 i_note.type = NT_ARCH;
4993 p = frag_more (sizeof (e_note.namesz));
4994 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
4995 p = frag_more (sizeof (e_note.descsz));
4996 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
4997 p = frag_more (sizeof (e_note.type));
4998 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
4999 p = frag_more (len + 1);
5000 strcpy (p, cpu_arch_name);
5001
5002 frag_align (2, 0, 0);
5003
5004 subseg_set (seg, subseg);
5005 }
5006}
5007#endif
47926f60 5008#endif /* BFD_ASSEMBLER */
252b5132 5009\f
252b5132
RH		 5010symbolS *
5011md_undefined_symbol (name)
5012 char *name;
5013{
18dc2407
ILT		 5014 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5015 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5016 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5017 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5018 {
5019 if (!GOT_symbol)
5020 {
5021 if (symbol_find (name))
5022 as_bad (_("GOT already in symbol table"));
5023 GOT_symbol = symbol_new (name, undefined_section,
5024 (valueT) 0, &zero_address_frag);
5025 };
5026 return GOT_symbol;
5027 }
252b5132
RH		 5028 return 0;
5029}
5030
5031/* Round up a section size to the appropriate boundary. */
47926f60 5032
252b5132
RH		 5033valueT
5034md_section_align (segment, size)
ab9da554 5035 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5036 valueT size;
5037{
252b5132 5038#ifdef BFD_ASSEMBLER
4c63da97
AM		 5039#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5040 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5041 {
5042 /* For a.out, force the section size to be aligned. If we don't do
5043 this, BFD will align it for us, but it will not write out the
5044 final bytes of the section. This may be a bug in BFD, but it is
5045 easier to fix it here since that is how the other a.out targets
5046 work. */
5047 int align;
5048
5049 align = bfd_get_section_alignment (stdoutput, segment);
5050 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5051 }
252b5132
RH		 5052#endif
5053#endif
5054
5055 return size;
5056}
5057
5058/* On the i386, PC-relative offsets are relative to the start of the
5059 next instruction. That is, the address of the offset, plus its
5060 size, since the offset is always the last part of the insn. */
5061
5062long
5063md_pcrel_from (fixP)
5064 fixS *fixP;
5065{
5066 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5067}
5068
5069#ifndef I386COFF
5070
5071static void
5072s_bss (ignore)
ab9da554 5073 int ignore ATTRIBUTE_UNUSED;
252b5132 5074{
29b0f896 5075 int temp;
252b5132
RH		 5076
5077 temp = get_absolute_expression ();
5078 subseg_set (bss_section, (subsegT) temp);
5079 demand_empty_rest_of_line ();
5080}
5081
5082#endif
5083
252b5132
RH		 5084#ifdef BFD_ASSEMBLER
5085
5086void
5087i386_validate_fix (fixp)
5088 fixS *fixp;
5089{
5090 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5091 {
3e73aa7c 5092 /* GOTOFF relocation are nonsense in 64bit mode. */
23df1078
JH		 5093 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5094 {
5095 if (flag_code != CODE_64BIT)
5096 abort ();
5097 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5098 }
5099 else
5100 {
5101 if (flag_code == CODE_64BIT)
5102 abort ();
5103 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5104 }
252b5132
RH		 5105 fixp->fx_subsy = 0;
5106 }
5107}
5108
a161fe53
AM		 5109boolean
5110i386_force_relocation (fixp)
5111 fixS *fixp;
5112{
5113 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
5114 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5115 return 1;
5116
5117 return S_FORCE_RELOC (fixp->fx_addsy);
5118}
5119
252b5132
RH		 5120arelent *
5121tc_gen_reloc (section, fixp)
ab9da554 5122 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5123 fixS *fixp;
5124{
5125 arelent *rel;
5126 bfd_reloc_code_real_type code;
5127
5128 switch (fixp->fx_r_type)
5129 {
3e73aa7c
JH		 5130 case BFD_RELOC_X86_64_PLT32:
5131 case BFD_RELOC_X86_64_GOT32:
5132 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5133 case BFD_RELOC_386_PLT32:
5134 case BFD_RELOC_386_GOT32:
5135 case BFD_RELOC_386_GOTOFF:
5136 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5137 case BFD_RELOC_386_TLS_GD:
5138 case BFD_RELOC_386_TLS_LDM:
5139 case BFD_RELOC_386_TLS_LDO_32:
5140 case BFD_RELOC_386_TLS_IE_32:
5141 case BFD_RELOC_386_TLS_LE_32:
5142 case BFD_RELOC_386_TLS_LE:
3e73aa7c 5143 case BFD_RELOC_X86_64_32S:
252b5132
RH		 5144 case BFD_RELOC_RVA:
5145 case BFD_RELOC_VTABLE_ENTRY:
5146 case BFD_RELOC_VTABLE_INHERIT:
5147 code = fixp->fx_r_type;
5148 break;
5149 default:
93382f6d 5150 if (fixp->fx_pcrel)
252b5132 5151 {
93382f6d
AM		 5152 switch (fixp->fx_size)
5153 {
5154 default:
b091f402
AM		 5155 as_bad_where (fixp->fx_file, fixp->fx_line,
5156 _("can not do %d byte pc-relative relocation"),
5157 fixp->fx_size);
93382f6d
AM		 5158 code = BFD_RELOC_32_PCREL;
5159 break;
5160 case 1: code = BFD_RELOC_8_PCREL; break;
5161 case 2: code = BFD_RELOC_16_PCREL; break;
5162 case 4: code = BFD_RELOC_32_PCREL; break;
5163 }
5164 }
5165 else
5166 {
5167 switch (fixp->fx_size)
5168 {
5169 default:
b091f402
AM		 5170 as_bad_where (fixp->fx_file, fixp->fx_line,
5171 _("can not do %d byte relocation"),
5172 fixp->fx_size);
93382f6d
AM		 5173 code = BFD_RELOC_32;
5174 break;
5175 case 1: code = BFD_RELOC_8; break;
5176 case 2: code = BFD_RELOC_16; break;
5177 case 4: code = BFD_RELOC_32; break;
937149dd 5178#ifdef BFD64
3e73aa7c 5179 case 8: code = BFD_RELOC_64; break;
937149dd 5180#endif
93382f6d 5181 }
252b5132
RH		 5182 }
5183 break;
5184 }
252b5132
RH		 5185
5186 if (code == BFD_RELOC_32
5187 && GOT_symbol
5188 && fixp->fx_addsy == GOT_symbol)
3e73aa7c
JH		 5189 {
5190 /* We don't support GOTPC on 64bit targets. */
5191 if (flag_code == CODE_64BIT)
bfb32b52 5192 abort ();
3e73aa7c
JH		 5193 code = BFD_RELOC_386_GOTPC;
5194 }
252b5132
RH		 5195
5196 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5197 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5198 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5199
5200 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
3e73aa7c
JH		 5201 if (!use_rela_relocations)
5202 {
5203 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5204 vtable entry to be used in the relocation's section offset. */
5205 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5206 rel->address = fixp->fx_offset;
252b5132 5207
c6682705 5208 rel->addend = 0;
3e73aa7c
JH		 5209 }
5210 /* Use the rela in 64bit mode. */
252b5132 5211 else
3e73aa7c 5212 {
062cd5e7
AS		 5213 if (!fixp->fx_pcrel)
5214 rel->addend = fixp->fx_offset;
5215 else
5216 switch (code)
5217 {
5218 case BFD_RELOC_X86_64_PLT32:
5219 case BFD_RELOC_X86_64_GOT32:
5220 case BFD_RELOC_X86_64_GOTPCREL:
5221 rel->addend = fixp->fx_offset - fixp->fx_size;
5222 break;
5223 default:
5224 rel->addend = (section->vma
5225 - fixp->fx_size
5226 + fixp->fx_addnumber
5227 + md_pcrel_from (fixp));
5228 break;
5229 }
3e73aa7c
JH		 5230 }
5231
252b5132
RH		 5232 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5233 if (rel->howto == NULL)
5234 {
5235 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5236 _("cannot represent relocation type %s"),
252b5132
RH		 5237 bfd_get_reloc_code_name (code));
5238 /* Set howto to a garbage value so that we can keep going. */
5239 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5240 assert (rel->howto != NULL);
5241 }
5242
5243 return rel;
5244}
5245
29b0f896 5246#else /* !BFD_ASSEMBLER */
252b5132
RH		 5247
5248#if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5249void
5250tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
5251 char *where;
5252 fixS *fixP;
5253 relax_addressT segment_address_in_file;
5254{
47926f60
KH		 5255 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5256 Out: GNU LD relocation length code: 0, 1, or 2. */
252b5132 5257
47926f60 5258 static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
252b5132
RH		 5259 long r_symbolnum;
5260
5261 know (fixP->fx_addsy != NULL);
5262
5263 md_number_to_chars (where,
5264 (valueT) (fixP->fx_frag->fr_address
5265 + fixP->fx_where - segment_address_in_file),
5266 4);
5267
5268 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5269 ? S_GET_TYPE (fixP->fx_addsy)
5270 : fixP->fx_addsy->sy_number);
5271
5272 where[6] = (r_symbolnum >> 16) & 0x0ff;
5273 where[5] = (r_symbolnum >> 8) & 0x0ff;
5274 where[4] = r_symbolnum & 0x0ff;
5275 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
5276 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
5277 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
5278}
5279
47926f60 5280#endif /* OBJ_AOUT or OBJ_BOUT. */
252b5132
RH		 5281
5282#if defined (I386COFF)
5283
5284short
5285tc_coff_fix2rtype (fixP)
5286 fixS *fixP;
5287{
5288 if (fixP->fx_r_type == R_IMAGEBASE)
5289 return R_IMAGEBASE;
5290
5291 return (fixP->fx_pcrel ?
5292 (fixP->fx_size == 1 ? R_PCRBYTE :
5293 fixP->fx_size == 2 ? R_PCRWORD :
5294 R_PCRLONG) :
5295 (fixP->fx_size == 1 ? R_RELBYTE :
5296 fixP->fx_size == 2 ? R_RELWORD :
5297 R_DIR32));
5298}
5299
5300int
5301tc_coff_sizemachdep (frag)
5302 fragS *frag;
5303{
5304 if (frag->fr_next)
5305 return (frag->fr_next->fr_address - frag->fr_address);
5306 else
5307 return 0;
5308}
5309
47926f60 5310#endif /* I386COFF */
252b5132 5311
29b0f896 5312#endif /* !BFD_ASSEMBLER */
64a0c779
DN		 5313\f
5314/* Parse operands using Intel syntax. This implements a recursive descent
5315 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5316 Programmer's Guide.
5317
5318 FIXME: We do not recognize the full operand grammar defined in the MASM
5319 documentation. In particular, all the structure/union and
5320 high-level macro operands are missing.
5321
5322 Uppercase words are terminals, lower case words are non-terminals.
5323 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5324 bars '|' denote choices. Most grammar productions are implemented in
5325 functions called 'intel_<production>'.
5326
5327 Initial production is 'expr'.
5328
64a0c779
DN		 5329 addOp + | -
5330
5331 alpha [a-zA-Z]
5332
5333 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5334
5335 constant digits [[ radixOverride ]]
5336
5337 dataType BYTE | WORD | DWORD | QWORD | XWORD
5338
5339 digits decdigit
b77a7acd
AJ		 5340 | digits decdigit
5341 | digits hexdigit
64a0c779
DN		 5342
5343 decdigit [0-9]
5344
5345 e05 e05 addOp e06
b77a7acd 5346 | e06
64a0c779
DN		 5347
5348 e06 e06 mulOp e09
b77a7acd 5349 | e09
64a0c779
DN		 5350
5351 e09 OFFSET e10
5352 | e09 PTR e10
5353 | e09 : e10
5354 | e10
5355
5356 e10 e10 [ expr ]
b77a7acd 5357 | e11
64a0c779
DN		 5358
5359 e11 ( expr )
b77a7acd 5360 | [ expr ]
64a0c779
DN		 5361 | constant
5362 | dataType
5363 | id
5364 | $
5365 | register
5366
5367 => expr SHORT e05
b77a7acd 5368 | e05
64a0c779
DN		 5369
5370 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5371 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5372
5373 hexdigit a | b | c | d | e | f
b77a7acd 5374 | A | B | C | D | E | F
64a0c779
DN		 5375
5376 id alpha
b77a7acd 5377 | id alpha
64a0c779
DN		 5378 | id decdigit
5379
5380 mulOp * | / | MOD
5381
5382 quote " | '
5383
5384 register specialRegister
b77a7acd 5385 | gpRegister
64a0c779
DN		 5386 | byteRegister
5387
5388 segmentRegister CS | DS | ES | FS | GS | SS
5389
5390 specialRegister CR0 | CR2 | CR3
b77a7acd 5391 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5392 | TR3 | TR4 | TR5 | TR6 | TR7
5393
64a0c779
DN		 5394 We simplify the grammar in obvious places (e.g., register parsing is
5395 done by calling parse_register) and eliminate immediate left recursion
5396 to implement a recursive-descent parser.
5397
5398 expr SHORT e05
b77a7acd 5399 | e05
64a0c779
DN		 5400
5401 e05 e06 e05'
5402
5403 e05' addOp e06 e05'
b77a7acd 5404 | Empty
64a0c779
DN		 5405
5406 e06 e09 e06'
5407
5408 e06' mulOp e09 e06'
b77a7acd 5409 | Empty
64a0c779
DN		 5410
5411 e09 OFFSET e10 e09'
b77a7acd 5412 | e10 e09'
64a0c779
DN		 5413
5414 e09' PTR e10 e09'
b77a7acd 5415 | : e10 e09'
64a0c779
DN		 5416 | Empty
5417
5418 e10 e11 e10'
5419
5420 e10' [ expr ] e10'
b77a7acd 5421 | Empty
64a0c779
DN		 5422
5423 e11 ( expr )
b77a7acd 5424 | [ expr ]
64a0c779
DN		 5425 | BYTE
5426 | WORD
5427 | DWORD
5428 | QWORD
5429 | XWORD
5430 | .
5431 | $
5432 | register
5433 | id
5434 | constant */
5435
5436/* Parsing structure for the intel syntax parser. Used to implement the
5437 semantic actions for the operand grammar. */
5438struct intel_parser_s
5439 {
5440 char *op_string; /* The string being parsed. */
5441 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5442 int op_modifier; /* Operand modifier. */
64a0c779
DN		 5443 int is_mem; /* 1 if operand is memory reference. */
5444 const reg_entry *reg; /* Last register reference found. */
5445 char *disp; /* Displacement string being built. */
5446 };
5447
5448static struct intel_parser_s intel_parser;
5449
5450/* Token structure for parsing intel syntax. */
5451struct intel_token
5452 {
5453 int code; /* Token code. */
5454 const reg_entry *reg; /* Register entry for register tokens. */
5455 char *str; /* String representation. */
5456 };
5457
5458static struct intel_token cur_token, prev_token;
5459
50705ef4
AM		 5460/* Token codes for the intel parser. Since T_SHORT is already used
5461 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5462#define T_NIL -1
5463#define T_CONST 1
5464#define T_REG 2
5465#define T_BYTE 3
5466#define T_WORD 4
5467#define T_DWORD 5
5468#define T_QWORD 6
5469#define T_XWORD 7
50705ef4 5470#undef T_SHORT
64a0c779
DN		 5471#define T_SHORT 8
5472#define T_OFFSET 9
5473#define T_PTR 10
5474#define T_ID 11
5475
5476/* Prototypes for intel parser functions. */
5477static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5478static void intel_get_token PARAMS ((void));
5479static void intel_putback_token PARAMS ((void));
5480static int intel_expr PARAMS ((void));
5481static int intel_e05 PARAMS ((void));
5482static int intel_e05_1 PARAMS ((void));
5483static int intel_e06 PARAMS ((void));
5484static int intel_e06_1 PARAMS ((void));
5485static int intel_e09 PARAMS ((void));
5486static int intel_e09_1 PARAMS ((void));
5487static int intel_e10 PARAMS ((void));
5488static int intel_e10_1 PARAMS ((void));
5489static int intel_e11 PARAMS ((void));
64a0c779 5490
64a0c779
DN		 5491static int
5492i386_intel_operand (operand_string, got_a_float)
5493 char *operand_string;
5494 int got_a_float;
5495{
5496 int ret;
5497 char *p;
5498
5499 /* Initialize token holders. */
5500 cur_token.code = prev_token.code = T_NIL;
5501 cur_token.reg = prev_token.reg = NULL;
5502 cur_token.str = prev_token.str = NULL;
5503
5504 /* Initialize parser structure. */
e5cb08ac 5505 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5506 if (p == NULL)
5507 abort ();
5508 strcpy (intel_parser.op_string, operand_string);
5509 intel_parser.got_a_float = got_a_float;
5510 intel_parser.op_modifier = -1;
5511 intel_parser.is_mem = 0;
5512 intel_parser.reg = NULL;
e5cb08ac 5513 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5514 if (intel_parser.disp == NULL)
5515 abort ();
5516 intel_parser.disp[0] = '\0';
5517
5518 /* Read the first token and start the parser. */
5519 intel_get_token ();
5520 ret = intel_expr ();
5521
5522 if (ret)
5523 {
5524 /* If we found a memory reference, hand it over to i386_displacement
5525 to fill in the rest of the operand fields. */
5526 if (intel_parser.is_mem)
5527 {
5528 if ((i.mem_operands == 1
5529 && (current_templates->start->opcode_modifier & IsString) == 0)
5530 || i.mem_operands == 2)
5531 {
5532 as_bad (_("too many memory references for '%s'"),
5533 current_templates->start->name);
5534 ret = 0;
5535 }
5536 else
5537 {
5538 char *s = intel_parser.disp;
5539 i.mem_operands++;
5540
5541 /* Add the displacement expression. */
5542 if (*s != '\0')
5543 ret = i386_displacement (s, s + strlen (s))
5544 && i386_index_check (s);
5545 }
5546 }
5547
5548 /* Constant and OFFSET expressions are handled by i386_immediate. */
5549 else if (intel_parser.op_modifier == OFFSET_FLAT
5550 || intel_parser.reg == NULL)
5551 ret = i386_immediate (intel_parser.disp);
5552 }
5553
5554 free (p);
5555 free (intel_parser.disp);
5556
5557 return ret;
5558}
5559
64a0c779 5560/* expr SHORT e05
b77a7acd 5561 | e05 */
64a0c779
DN		 5562static int
5563intel_expr ()
5564{
5565 /* expr SHORT e05 */
5566 if (cur_token.code == T_SHORT)
5567 {
5568 intel_parser.op_modifier = SHORT;
5569 intel_match_token (T_SHORT);
5570
5571 return (intel_e05 ());
5572 }
5573
5574 /* expr e05 */
5575 else
5576 return intel_e05 ();
5577}
5578
64a0c779
DN		 5579/* e05 e06 e05'
5580
4a1805b1 5581 e05' addOp e06 e05'
64a0c779
DN		 5582 | Empty */
5583static int
5584intel_e05 ()
5585{
5586 return (intel_e06 () && intel_e05_1 ());
5587}
5588
5589static int
5590intel_e05_1 ()
5591{
5592 /* e05' addOp e06 e05' */
5593 if (cur_token.code == '+' || cur_token.code == '-')
5594 {
5595 strcat (intel_parser.disp, cur_token.str);
5596 intel_match_token (cur_token.code);
5597
5598 return (intel_e06 () && intel_e05_1 ());
5599 }
5600
5601 /* e05' Empty */
5602 else
5603 return 1;
4a1805b1 5604}
64a0c779
DN		 5605
5606/* e06 e09 e06'
5607
5608 e06' mulOp e09 e06'
b77a7acd 5609 | Empty */
64a0c779
DN		 5610static int
5611intel_e06 ()
5612{
5613 return (intel_e09 () && intel_e06_1 ());
5614}
5615
5616static int
5617intel_e06_1 ()
5618{
5619 /* e06' mulOp e09 e06' */
5620 if (cur_token.code == '*' || cur_token.code == '/')
5621 {
5622 strcat (intel_parser.disp, cur_token.str);
5623 intel_match_token (cur_token.code);
5624
5625 return (intel_e09 () && intel_e06_1 ());
5626 }
4a1805b1 5627
64a0c779 5628 /* e06' Empty */
4a1805b1 5629 else
64a0c779
DN		 5630 return 1;
5631}
5632
64a0c779 5633/* e09 OFFSET e10 e09'
b77a7acd 5634 | e10 e09'
64a0c779
DN		 5635
5636 e09' PTR e10 e09'
b77a7acd 5637 | : e10 e09'
64a0c779
DN		 5638 | Empty */
5639static int
5640intel_e09 ()
5641{
5642 /* e09 OFFSET e10 e09' */
5643 if (cur_token.code == T_OFFSET)
5644 {
5645 intel_parser.is_mem = 0;
5646 intel_parser.op_modifier = OFFSET_FLAT;
5647 intel_match_token (T_OFFSET);
5648
5649 return (intel_e10 () && intel_e09_1 ());
5650 }
5651
5652 /* e09 e10 e09' */
5653 else
5654 return (intel_e10 () && intel_e09_1 ());
5655}
5656
5657static int
5658intel_e09_1 ()
5659{
5660 /* e09' PTR e10 e09' */
5661 if (cur_token.code == T_PTR)
5662 {
5663 if (prev_token.code == T_BYTE)
5664 i.suffix = BYTE_MNEM_SUFFIX;
5665
5666 else if (prev_token.code == T_WORD)
5667 {
5668 if (intel_parser.got_a_float == 2) /* "fi..." */
5669 i.suffix = SHORT_MNEM_SUFFIX;
5670 else
5671 i.suffix = WORD_MNEM_SUFFIX;
5672 }
5673
5674 else if (prev_token.code == T_DWORD)
5675 {
5676 if (intel_parser.got_a_float == 1) /* "f..." */
5677 i.suffix = SHORT_MNEM_SUFFIX;
5678 else
5679 i.suffix = LONG_MNEM_SUFFIX;
5680 }
5681
5682 else if (prev_token.code == T_QWORD)
f16b83df
JH		 5683 {
5684 if (intel_parser.got_a_float == 1) /* "f..." */
5685 i.suffix = LONG_MNEM_SUFFIX;
5686 else
3e73aa7c 5687 i.suffix = QWORD_MNEM_SUFFIX;
f16b83df 5688 }
64a0c779
DN		 5689
5690 else if (prev_token.code == T_XWORD)
5691 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5692
5693 else
5694 {
5695 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5696 return 0;
5697 }
5698
5699 intel_match_token (T_PTR);
5700
5701 return (intel_e10 () && intel_e09_1 ());
5702 }
5703
5704 /* e09 : e10 e09' */
5705 else if (cur_token.code == ':')
5706 {
21d6c4af
DN		 5707 /* Mark as a memory operand only if it's not already known to be an
5708 offset expression. */
5709 if (intel_parser.op_modifier != OFFSET_FLAT)
5710 intel_parser.is_mem = 1;
64a0c779
DN		 5711
5712 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5713 }
5714
5715 /* e09' Empty */
5716 else
5717 return 1;
5718}
5719
5720/* e10 e11 e10'
5721
5722 e10' [ expr ] e10'
b77a7acd 5723 | Empty */
64a0c779
DN		 5724static int
5725intel_e10 ()
5726{
5727 return (intel_e11 () && intel_e10_1 ());
5728}
5729
5730static int
5731intel_e10_1 ()
5732{
5733 /* e10' [ expr ] e10' */
5734 if (cur_token.code == '[')
5735 {
5736 intel_match_token ('[');
21d6c4af
DN		 5737
5738 /* Mark as a memory operand only if it's not already known to be an
5739 offset expression. If it's an offset expression, we need to keep
5740 the brace in. */
5741 if (intel_parser.op_modifier != OFFSET_FLAT)
5742 intel_parser.is_mem = 1;
5743 else
5744 strcat (intel_parser.disp, "[");
4a1805b1 5745
64a0c779 5746 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5747 if (*intel_parser.disp != '\0'
5748 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5749 strcat (intel_parser.disp, "+");
5750
21d6c4af
DN		 5751 if (intel_expr () && intel_match_token (']'))
5752 {
5753 /* Preserve brackets when the operand is an offset expression. */
5754 if (intel_parser.op_modifier == OFFSET_FLAT)
5755 strcat (intel_parser.disp, "]");
5756
5757 return intel_e10_1 ();
5758 }
5759 else
5760 return 0;
64a0c779
DN		 5761 }
5762
5763 /* e10' Empty */
5764 else
5765 return 1;
5766}
5767
64a0c779 5768/* e11 ( expr )
b77a7acd 5769 | [ expr ]
64a0c779
DN		 5770 | BYTE
5771 | WORD
5772 | DWORD
5773 | QWORD
5774 | XWORD
4a1805b1 5775 | $
64a0c779
DN		 5776 | .
5777 | register
5778 | id
5779 | constant */
5780static int
5781intel_e11 ()
5782{
5783 /* e11 ( expr ) */
5784 if (cur_token.code == '(')
5785 {
5786 intel_match_token ('(');
5787 strcat (intel_parser.disp, "(");
5788
5789 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 5790 {
5791 strcat (intel_parser.disp, ")");
5792 return 1;
5793 }
64a0c779
DN		 5794 else
5795 return 0;
5796 }
5797
5798 /* e11 [ expr ] */
5799 else if (cur_token.code == '[')
5800 {
5801 intel_match_token ('[');
21d6c4af
DN		 5802
5803 /* Mark as a memory operand only if it's not already known to be an
5804 offset expression. If it's an offset expression, we need to keep
5805 the brace in. */
5806 if (intel_parser.op_modifier != OFFSET_FLAT)
5807 intel_parser.is_mem = 1;
5808 else
5809 strcat (intel_parser.disp, "[");
4a1805b1 5810
64a0c779
DN		 5811 /* Operands for jump/call inside brackets denote absolute addresses. */
5812 if (current_templates->start->opcode_modifier & Jump
5813 || current_templates->start->opcode_modifier & JumpDword
5814 || current_templates->start->opcode_modifier & JumpByte
5815 || current_templates->start->opcode_modifier & JumpInterSegment)
5816 i.types[this_operand] |= JumpAbsolute;
5817
5818 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5819 if (*intel_parser.disp != '\0'
5820 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5821 strcat (intel_parser.disp, "+");
5822
21d6c4af
DN		 5823 if (intel_expr () && intel_match_token (']'))
5824 {
5825 /* Preserve brackets when the operand is an offset expression. */
5826 if (intel_parser.op_modifier == OFFSET_FLAT)
5827 strcat (intel_parser.disp, "]");
5828
5829 return 1;
5830 }
5831 else
5832 return 0;
64a0c779
DN		 5833 }
5834
4a1805b1 5835 /* e11 BYTE
64a0c779
DN		 5836 | WORD
5837 | DWORD
5838 | QWORD
5839 | XWORD */
5840 else if (cur_token.code == T_BYTE
5841 || cur_token.code == T_WORD
5842 || cur_token.code == T_DWORD
5843 || cur_token.code == T_QWORD
5844 || cur_token.code == T_XWORD)
5845 {
5846 intel_match_token (cur_token.code);
5847
5848 return 1;
5849 }
5850
5851 /* e11 $
5852 | . */
5853 else if (cur_token.code == '$' || cur_token.code == '.')
5854 {
5855 strcat (intel_parser.disp, cur_token.str);
5856 intel_match_token (cur_token.code);
21d6c4af
DN		 5857
5858 /* Mark as a memory operand only if it's not already known to be an
5859 offset expression. */
5860 if (intel_parser.op_modifier != OFFSET_FLAT)
5861 intel_parser.is_mem = 1;
64a0c779
DN		 5862
5863 return 1;
5864 }
5865
5866 /* e11 register */
5867 else if (cur_token.code == T_REG)
5868 {
5869 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5870
5871 intel_match_token (T_REG);
5872
5873 /* Check for segment change. */
5874 if (cur_token.code == ':')
5875 {
5876 if (reg->reg_type & (SReg2 | SReg3))
5877 {
5878 switch (reg->reg_num)
5879 {
5880 case 0:
5881 i.seg[i.mem_operands] = &es;
5882 break;
5883 case 1:
5884 i.seg[i.mem_operands] = &cs;
5885 break;
5886 case 2:
5887 i.seg[i.mem_operands] = &ss;
5888 break;
5889 case 3:
5890 i.seg[i.mem_operands] = &ds;
5891 break;
5892 case 4:
5893 i.seg[i.mem_operands] = &fs;
5894 break;
5895 case 5:
5896 i.seg[i.mem_operands] = &gs;
5897 break;
5898 }
5899 }
5900 else
5901 {
5902 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5903 return 0;
5904 }
5905 }
5906
5907 /* Not a segment register. Check for register scaling. */
5908 else if (cur_token.code == '*')
5909 {
5910 if (!intel_parser.is_mem)
5911 {
5912 as_bad (_("Register scaling only allowed in memory operands."));
5913 return 0;
5914 }
5915
4a1805b1 5916 /* What follows must be a valid scale. */
64a0c779
DN		 5917 if (intel_match_token ('*')
5918 && strchr ("01248", *cur_token.str))
5919 {
5920 i.index_reg = reg;
5921 i.types[this_operand] |= BaseIndex;
5922
5923 /* Set the scale after setting the register (otherwise,
5924 i386_scale will complain) */
5925 i386_scale (cur_token.str);
5926 intel_match_token (T_CONST);
5927 }
5928 else
5929 {
5930 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5931 cur_token.str);
5932 return 0;
5933 }
5934 }
5935
5936 /* No scaling. If this is a memory operand, the register is either a
5937 base register (first occurrence) or an index register (second
5938 occurrence). */
5939 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5940 {
5941 if (i.base_reg && i.index_reg)
5942 {
5943 as_bad (_("Too many register references in memory operand.\n"));
5944 return 0;
5945 }
5946
5947 if (i.base_reg == NULL)
5948 i.base_reg = reg;
5949 else
5950 i.index_reg = reg;
5951
5952 i.types[this_operand] |= BaseIndex;
5953 }
5954
5955 /* Offset modifier. Add the register to the displacement string to be
5956 parsed as an immediate expression after we're done. */
5957 else if (intel_parser.op_modifier == OFFSET_FLAT)
5958 strcat (intel_parser.disp, reg->reg_name);
4a1805b1 5959
64a0c779
DN		 5960 /* It's neither base nor index nor offset. */
5961 else
5962 {
5963 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5964 i.op[this_operand].regs = reg;
5965 i.reg_operands++;
5966 }
5967
5968 /* Since registers are not part of the displacement string (except
5969 when we're parsing offset operands), we may need to remove any
5970 preceding '+' from the displacement string. */
5971 if (*intel_parser.disp != '\0'
5972 && intel_parser.op_modifier != OFFSET_FLAT)
5973 {
5974 char *s = intel_parser.disp;
5975 s += strlen (s) - 1;
5976 if (*s == '+')
5977 *s = '\0';
5978 }
5979
5980 return 1;
5981 }
4a1805b1 5982
64a0c779
DN		 5983 /* e11 id */
5984 else if (cur_token.code == T_ID)
5985 {
5986 /* Add the identifier to the displacement string. */
5987 strcat (intel_parser.disp, cur_token.str);
5988 intel_match_token (T_ID);
5989
5990 /* The identifier represents a memory reference only if it's not
5991 preceded by an offset modifier. */
21d6c4af 5992 if (intel_parser.op_modifier != OFFSET_FLAT)
64a0c779
DN		 5993 intel_parser.is_mem = 1;
5994
5995 return 1;
5996 }
5997
5998 /* e11 constant */
5999 else if (cur_token.code == T_CONST
e5cb08ac 6000 || cur_token.code == '-'
64a0c779
DN		 6001 || cur_token.code == '+')
6002 {
6003 char *save_str;
6004
6005 /* Allow constants that start with `+' or `-'. */
6006 if (cur_token.code == '-' || cur_token.code == '+')
6007 {
6008 strcat (intel_parser.disp, cur_token.str);
6009 intel_match_token (cur_token.code);
6010 if (cur_token.code != T_CONST)
6011 {
6012 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
6013 cur_token.str);
6014 return 0;
6015 }
6016 }
6017
e5cb08ac 6018 save_str = (char *) malloc (strlen (cur_token.str) + 1);
64a0c779 6019 if (save_str == NULL)
bc805888 6020 abort ();
64a0c779
DN		 6021 strcpy (save_str, cur_token.str);
6022
6023 /* Get the next token to check for register scaling. */
6024 intel_match_token (cur_token.code);
6025
6026 /* Check if this constant is a scaling factor for an index register. */
6027 if (cur_token.code == '*')
6028 {
6029 if (intel_match_token ('*') && cur_token.code == T_REG)
6030 {
6031 if (!intel_parser.is_mem)
6032 {
6033 as_bad (_("Register scaling only allowed in memory operands."));
6034 return 0;
6035 }
6036
4a1805b1 6037 /* The constant is followed by `* reg', so it must be
64a0c779
DN		 6038 a valid scale. */
6039 if (strchr ("01248", *save_str))
6040 {
6041 i.index_reg = cur_token.reg;
6042 i.types[this_operand] |= BaseIndex;
6043
6044 /* Set the scale after setting the register (otherwise,
6045 i386_scale will complain) */
6046 i386_scale (save_str);
6047 intel_match_token (T_REG);
6048
6049 /* Since registers are not part of the displacement
6050 string, we may need to remove any preceding '+' from
6051 the displacement string. */
6052 if (*intel_parser.disp != '\0')
6053 {
6054 char *s = intel_parser.disp;
6055 s += strlen (s) - 1;
6056 if (*s == '+')
6057 *s = '\0';
6058 }
6059
6060 free (save_str);
6061
6062 return 1;
6063 }
6064 else
6065 return 0;
6066 }
6067
6068 /* The constant was not used for register scaling. Since we have
6069 already consumed the token following `*' we now need to put it
6070 back in the stream. */
6071 else
6072 intel_putback_token ();
6073 }
6074
6075 /* Add the constant to the displacement string. */
6076 strcat (intel_parser.disp, save_str);
6077 free (save_str);
6078
6079 return 1;
6080 }
6081
64a0c779
DN		 6082 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6083 return 0;
6084}
6085
64a0c779
DN		 6086/* Match the given token against cur_token. If they match, read the next
6087 token from the operand string. */
6088static int
6089intel_match_token (code)
e5cb08ac 6090 int code;
64a0c779
DN		 6091{
6092 if (cur_token.code == code)
6093 {
6094 intel_get_token ();
6095 return 1;
6096 }
6097 else
6098 {
6099 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
6100 return 0;
6101 }
6102}
6103
64a0c779
DN		 6104/* Read a new token from intel_parser.op_string and store it in cur_token. */
6105static void
6106intel_get_token ()
6107{
6108 char *end_op;
6109 const reg_entry *reg;
6110 struct intel_token new_token;
6111
6112 new_token.code = T_NIL;
6113 new_token.reg = NULL;
6114 new_token.str = NULL;
6115
4a1805b1 6116 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6117 cur_token to prev_token. */
6118 if (prev_token.str)
6119 free (prev_token.str);
6120
6121 prev_token = cur_token;
6122
6123 /* Skip whitespace. */
6124 while (is_space_char (*intel_parser.op_string))
6125 intel_parser.op_string++;
6126
6127 /* Return an empty token if we find nothing else on the line. */
6128 if (*intel_parser.op_string == '\0')
6129 {
6130 cur_token = new_token;
6131 return;
6132 }
6133
6134 /* The new token cannot be larger than the remainder of the operand
6135 string. */
e5cb08ac 6136 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
64a0c779 6137 if (new_token.str == NULL)
bc805888 6138 abort ();
64a0c779
DN		 6139 new_token.str[0] = '\0';
6140
6141 if (strchr ("0123456789", *intel_parser.op_string))
6142 {
6143 char *p = new_token.str;
6144 char *q = intel_parser.op_string;
6145 new_token.code = T_CONST;
6146
6147 /* Allow any kind of identifier char to encompass floating point and
6148 hexadecimal numbers. */
6149 while (is_identifier_char (*q))
6150 *p++ = *q++;
6151 *p = '\0';
6152
6153 /* Recognize special symbol names [0-9][bf]. */
6154 if (strlen (intel_parser.op_string) == 2
4a1805b1 6155 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6156 || intel_parser.op_string[1] == 'f'))
6157 new_token.code = T_ID;
6158 }
6159
6160 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
6161 {
6162 new_token.code = *intel_parser.op_string;
6163 new_token.str[0] = *intel_parser.op_string;
6164 new_token.str[1] = '\0';
6165 }
6166
6167 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6168 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6169 {
6170 new_token.code = T_REG;
6171 new_token.reg = reg;
6172
6173 if (*intel_parser.op_string == REGISTER_PREFIX)
6174 {
6175 new_token.str[0] = REGISTER_PREFIX;
6176 new_token.str[1] = '\0';
6177 }
6178
6179 strcat (new_token.str, reg->reg_name);
6180 }
6181
6182 else if (is_identifier_char (*intel_parser.op_string))
6183 {
6184 char *p = new_token.str;
6185 char *q = intel_parser.op_string;
6186
6187 /* A '.' or '$' followed by an identifier char is an identifier.
6188 Otherwise, it's operator '.' followed by an expression. */
6189 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6190 {
6191 new_token.code = *q;
6192 new_token.str[0] = *q;
6193 new_token.str[1] = '\0';
6194 }
6195 else
6196 {
6197 while (is_identifier_char (*q) || *q == '@')
6198 *p++ = *q++;
6199 *p = '\0';
6200
6201 if (strcasecmp (new_token.str, "BYTE") == 0)
6202 new_token.code = T_BYTE;
6203
6204 else if (strcasecmp (new_token.str, "WORD") == 0)
6205 new_token.code = T_WORD;
6206
6207 else if (strcasecmp (new_token.str, "DWORD") == 0)
6208 new_token.code = T_DWORD;
6209
6210 else if (strcasecmp (new_token.str, "QWORD") == 0)
6211 new_token.code = T_QWORD;
6212
6213 else if (strcasecmp (new_token.str, "XWORD") == 0)
6214 new_token.code = T_XWORD;
6215
6216 else if (strcasecmp (new_token.str, "PTR") == 0)
6217 new_token.code = T_PTR;
6218
6219 else if (strcasecmp (new_token.str, "SHORT") == 0)
6220 new_token.code = T_SHORT;
6221
6222 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6223 {
6224 new_token.code = T_OFFSET;
6225
6226 /* ??? This is not mentioned in the MASM grammar but gcc
6227 makes use of it with -mintel-syntax. OFFSET may be
6228 followed by FLAT: */
6229 if (strncasecmp (q, " FLAT:", 6) == 0)
6230 strcat (new_token.str, " FLAT:");
6231 }
6232
6233 /* ??? This is not mentioned in the MASM grammar. */
6234 else if (strcasecmp (new_token.str, "FLAT") == 0)
6235 new_token.code = T_OFFSET;
6236
6237 else
6238 new_token.code = T_ID;
6239 }
6240 }
6241
6242 else
6243 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
6244
6245 intel_parser.op_string += strlen (new_token.str);
6246 cur_token = new_token;
6247}
6248
64a0c779
DN		 6249/* Put cur_token back into the token stream and make cur_token point to
6250 prev_token. */
6251static void
6252intel_putback_token ()
6253{
6254 intel_parser.op_string -= strlen (cur_token.str);
6255 free (cur_token.str);
6256 cur_token = prev_token;
4a1805b1 6257
64a0c779
DN		 6258 /* Forget prev_token. */
6259 prev_token.code = T_NIL;
6260 prev_token.reg = NULL;
6261 prev_token.str = NULL;
6262}
GDB Binutils - Deliverables
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