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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
219d1afa | 2 | Copyright (C) 1989-2018 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
252b5132 RH |
36 | #ifndef REGISTER_WARNINGS |
37 | #define REGISTER_WARNINGS 1 | |
38 | #endif | |
39 | ||
c3332e24 | 40 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 41 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
42 | #endif |
43 | ||
29b0f896 AM |
44 | #ifndef DEFAULT_ARCH |
45 | #define DEFAULT_ARCH "i386" | |
246fcdee | 46 | #endif |
252b5132 | 47 | |
edde18a5 AM |
48 | #ifndef INLINE |
49 | #if __GNUC__ >= 2 | |
50 | #define INLINE __inline__ | |
51 | #else | |
52 | #define INLINE | |
53 | #endif | |
54 | #endif | |
55 | ||
6305a203 L |
56 | /* Prefixes will be emitted in the order defined below. |
57 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
58 | instruction, and so must come before any prefixes. | |
59 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 60 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
61 | #define WAIT_PREFIX 0 |
62 | #define SEG_PREFIX 1 | |
63 | #define ADDR_PREFIX 2 | |
64 | #define DATA_PREFIX 3 | |
c32fa91d | 65 | #define REP_PREFIX 4 |
42164a71 | 66 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 67 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 68 | #define LOCK_PREFIX 5 |
4e9ac44a L |
69 | #define REX_PREFIX 6 /* must come last. */ |
70 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
71 | |
72 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
73 | #define REGISTER_PREFIX '%' | |
74 | #define IMMEDIATE_PREFIX '$' | |
75 | #define ABSOLUTE_PREFIX '*' | |
76 | ||
77 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
78 | memory operand size in Intel syntax. */ | |
79 | #define WORD_MNEM_SUFFIX 'w' | |
80 | #define BYTE_MNEM_SUFFIX 'b' | |
81 | #define SHORT_MNEM_SUFFIX 's' | |
82 | #define LONG_MNEM_SUFFIX 'l' | |
83 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
84 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
85 | in instructions. */ | |
86 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
87 | ||
88 | #define END_OF_INSN '\0' | |
89 | ||
90 | /* | |
91 | 'templates' is for grouping together 'template' structures for opcodes | |
92 | of the same name. This is only used for storing the insns in the grand | |
93 | ole hash table of insns. | |
94 | The templates themselves start at START and range up to (but not including) | |
95 | END. | |
96 | */ | |
97 | typedef struct | |
98 | { | |
d3ce72d0 NC |
99 | const insn_template *start; |
100 | const insn_template *end; | |
6305a203 L |
101 | } |
102 | templates; | |
103 | ||
104 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
105 | typedef struct | |
106 | { | |
107 | unsigned int regmem; /* codes register or memory operand */ | |
108 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
109 | unsigned int mode; /* how to interpret regmem & reg */ | |
110 | } | |
111 | modrm_byte; | |
112 | ||
113 | /* x86-64 extension prefix. */ | |
114 | typedef int rex_byte; | |
115 | ||
6305a203 L |
116 | /* 386 opcode byte to code indirect addressing. */ |
117 | typedef struct | |
118 | { | |
119 | unsigned base; | |
120 | unsigned index; | |
121 | unsigned scale; | |
122 | } | |
123 | sib_byte; | |
124 | ||
6305a203 L |
125 | /* x86 arch names, types and features */ |
126 | typedef struct | |
127 | { | |
128 | const char *name; /* arch name */ | |
8a2c8fef | 129 | unsigned int len; /* arch string length */ |
6305a203 L |
130 | enum processor_type type; /* arch type */ |
131 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 132 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
133 | } |
134 | arch_entry; | |
135 | ||
293f5f65 L |
136 | /* Used to turn off indicated flags. */ |
137 | typedef struct | |
138 | { | |
139 | const char *name; /* arch name */ | |
140 | unsigned int len; /* arch string length */ | |
141 | i386_cpu_flags flags; /* cpu feature flags */ | |
142 | } | |
143 | noarch_entry; | |
144 | ||
78f12dd3 | 145 | static void update_code_flag (int, int); |
e3bb37b5 L |
146 | static void set_code_flag (int); |
147 | static void set_16bit_gcc_code_flag (int); | |
148 | static void set_intel_syntax (int); | |
1efbbeb4 | 149 | static void set_intel_mnemonic (int); |
db51cc60 | 150 | static void set_allow_index_reg (int); |
7bab8ab5 | 151 | static void set_check (int); |
e3bb37b5 | 152 | static void set_cpu_arch (int); |
6482c264 | 153 | #ifdef TE_PE |
e3bb37b5 | 154 | static void pe_directive_secrel (int); |
6482c264 | 155 | #endif |
e3bb37b5 L |
156 | static void signed_cons (int); |
157 | static char *output_invalid (int c); | |
ee86248c JB |
158 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
159 | const char *); | |
160 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
161 | const char *); | |
a7619375 | 162 | static int i386_att_operand (char *); |
e3bb37b5 | 163 | static int i386_intel_operand (char *, int); |
ee86248c JB |
164 | static int i386_intel_simplify (expressionS *); |
165 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
166 | static const reg_entry *parse_register (char *, char **); |
167 | static char *parse_insn (char *, char *); | |
168 | static char *parse_operands (char *, const char *); | |
169 | static void swap_operands (void); | |
4d456e3d | 170 | static void swap_2_operands (int, int); |
e3bb37b5 L |
171 | static void optimize_imm (void); |
172 | static void optimize_disp (void); | |
83b16ac6 | 173 | static const insn_template *match_template (char); |
e3bb37b5 L |
174 | static int check_string (void); |
175 | static int process_suffix (void); | |
176 | static int check_byte_reg (void); | |
177 | static int check_long_reg (void); | |
178 | static int check_qword_reg (void); | |
179 | static int check_word_reg (void); | |
180 | static int finalize_imm (void); | |
181 | static int process_operands (void); | |
182 | static const seg_entry *build_modrm_byte (void); | |
183 | static void output_insn (void); | |
184 | static void output_imm (fragS *, offsetT); | |
185 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 186 | #ifndef I386COFF |
e3bb37b5 | 187 | static void s_bss (int); |
252b5132 | 188 | #endif |
17d4e2a2 L |
189 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
190 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
191 | #endif | |
252b5132 | 192 | |
a847613f | 193 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 194 | |
43234a1e L |
195 | /* This struct describes rounding control and SAE in the instruction. */ |
196 | struct RC_Operation | |
197 | { | |
198 | enum rc_type | |
199 | { | |
200 | rne = 0, | |
201 | rd, | |
202 | ru, | |
203 | rz, | |
204 | saeonly | |
205 | } type; | |
206 | int operand; | |
207 | }; | |
208 | ||
209 | static struct RC_Operation rc_op; | |
210 | ||
211 | /* The struct describes masking, applied to OPERAND in the instruction. | |
212 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
213 | whether merging or zeroing mask is used. */ | |
214 | struct Mask_Operation | |
215 | { | |
216 | const reg_entry *mask; | |
217 | unsigned int zeroing; | |
218 | /* The operand where this operation is associated. */ | |
219 | int operand; | |
220 | }; | |
221 | ||
222 | static struct Mask_Operation mask_op; | |
223 | ||
224 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
225 | broadcast factor. */ | |
226 | struct Broadcast_Operation | |
227 | { | |
228 | /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */ | |
229 | int type; | |
230 | ||
231 | /* Index of broadcasted operand. */ | |
232 | int operand; | |
233 | }; | |
234 | ||
235 | static struct Broadcast_Operation broadcast_op; | |
236 | ||
c0f3af97 L |
237 | /* VEX prefix. */ |
238 | typedef struct | |
239 | { | |
43234a1e L |
240 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
241 | unsigned char bytes[4]; | |
c0f3af97 L |
242 | unsigned int length; |
243 | /* Destination or source register specifier. */ | |
244 | const reg_entry *register_specifier; | |
245 | } vex_prefix; | |
246 | ||
252b5132 | 247 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 248 | i386_insn. */ |
252b5132 | 249 | |
520dc8e8 AM |
250 | union i386_op |
251 | { | |
252 | expressionS *disps; | |
253 | expressionS *imms; | |
254 | const reg_entry *regs; | |
255 | }; | |
256 | ||
a65babc9 L |
257 | enum i386_error |
258 | { | |
86e026a4 | 259 | operand_size_mismatch, |
a65babc9 L |
260 | operand_type_mismatch, |
261 | register_type_mismatch, | |
262 | number_of_operands_mismatch, | |
263 | invalid_instruction_suffix, | |
264 | bad_imm4, | |
a65babc9 L |
265 | unsupported_with_intel_mnemonic, |
266 | unsupported_syntax, | |
6c30d220 L |
267 | unsupported, |
268 | invalid_vsib_address, | |
7bab8ab5 | 269 | invalid_vector_register_set, |
43234a1e L |
270 | unsupported_vector_index_register, |
271 | unsupported_broadcast, | |
272 | broadcast_not_on_src_operand, | |
273 | broadcast_needed, | |
274 | unsupported_masking, | |
275 | mask_not_on_destination, | |
276 | no_default_mask, | |
277 | unsupported_rc_sae, | |
278 | rc_sae_operand_not_last_imm, | |
279 | invalid_register_operand, | |
a65babc9 L |
280 | }; |
281 | ||
252b5132 RH |
282 | struct _i386_insn |
283 | { | |
47926f60 | 284 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 285 | insn_template tm; |
252b5132 | 286 | |
7d5e4556 L |
287 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
288 | or qword, if given. */ | |
252b5132 RH |
289 | char suffix; |
290 | ||
47926f60 | 291 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
292 | unsigned int operands; |
293 | ||
294 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
295 | of given register, displacement, memory operands and immediate | |
47926f60 | 296 | operands. */ |
252b5132 RH |
297 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
298 | ||
299 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 300 | use OP[i] for the corresponding operand. */ |
40fb9820 | 301 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 302 | |
520dc8e8 AM |
303 | /* Displacement expression, immediate expression, or register for each |
304 | operand. */ | |
305 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 306 | |
3e73aa7c JH |
307 | /* Flags for operands. */ |
308 | unsigned int flags[MAX_OPERANDS]; | |
309 | #define Operand_PCrel 1 | |
310 | ||
252b5132 | 311 | /* Relocation type for operand */ |
f86103b7 | 312 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 313 | |
252b5132 RH |
314 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
315 | the base index byte below. */ | |
316 | const reg_entry *base_reg; | |
317 | const reg_entry *index_reg; | |
318 | unsigned int log2_scale_factor; | |
319 | ||
320 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 321 | explicit segment overrides are given. */ |
ce8a8b2f | 322 | const seg_entry *seg[2]; |
252b5132 | 323 | |
8325cc63 JB |
324 | /* Copied first memory operand string, for re-checking. */ |
325 | char *memop1_string; | |
326 | ||
252b5132 RH |
327 | /* PREFIX holds all the given prefix opcodes (usually null). |
328 | PREFIXES is the number of prefix opcodes. */ | |
329 | unsigned int prefixes; | |
330 | unsigned char prefix[MAX_PREFIXES]; | |
331 | ||
332 | /* RM and SIB are the modrm byte and the sib byte where the | |
c1e679ec | 333 | addressing modes of this insn are encoded. */ |
252b5132 | 334 | modrm_byte rm; |
3e73aa7c | 335 | rex_byte rex; |
43234a1e | 336 | rex_byte vrex; |
252b5132 | 337 | sib_byte sib; |
c0f3af97 | 338 | vex_prefix vex; |
b6169b20 | 339 | |
43234a1e L |
340 | /* Masking attributes. */ |
341 | struct Mask_Operation *mask; | |
342 | ||
343 | /* Rounding control and SAE attributes. */ | |
344 | struct RC_Operation *rounding; | |
345 | ||
346 | /* Broadcasting attributes. */ | |
347 | struct Broadcast_Operation *broadcast; | |
348 | ||
349 | /* Compressed disp8*N attribute. */ | |
350 | unsigned int memshift; | |
351 | ||
86fa6981 L |
352 | /* Prefer load or store in encoding. */ |
353 | enum | |
354 | { | |
355 | dir_encoding_default = 0, | |
356 | dir_encoding_load, | |
357 | dir_encoding_store | |
358 | } dir_encoding; | |
891edac4 | 359 | |
a501d77e L |
360 | /* Prefer 8bit or 32bit displacement in encoding. */ |
361 | enum | |
362 | { | |
363 | disp_encoding_default = 0, | |
364 | disp_encoding_8bit, | |
365 | disp_encoding_32bit | |
366 | } disp_encoding; | |
f8a5c266 | 367 | |
6b6b6807 L |
368 | /* Prefer the REX byte in encoding. */ |
369 | bfd_boolean rex_encoding; | |
370 | ||
b6f8c7c4 L |
371 | /* Disable instruction size optimization. */ |
372 | bfd_boolean no_optimize; | |
373 | ||
86fa6981 L |
374 | /* How to encode vector instructions. */ |
375 | enum | |
376 | { | |
377 | vex_encoding_default = 0, | |
378 | vex_encoding_vex2, | |
379 | vex_encoding_vex3, | |
380 | vex_encoding_evex | |
381 | } vec_encoding; | |
382 | ||
d5de92cf L |
383 | /* REP prefix. */ |
384 | const char *rep_prefix; | |
385 | ||
165de32a L |
386 | /* HLE prefix. */ |
387 | const char *hle_prefix; | |
42164a71 | 388 | |
7e8b059b L |
389 | /* Have BND prefix. */ |
390 | const char *bnd_prefix; | |
391 | ||
04ef582a L |
392 | /* Have NOTRACK prefix. */ |
393 | const char *notrack_prefix; | |
394 | ||
891edac4 | 395 | /* Error message. */ |
a65babc9 | 396 | enum i386_error error; |
252b5132 RH |
397 | }; |
398 | ||
399 | typedef struct _i386_insn i386_insn; | |
400 | ||
43234a1e L |
401 | /* Link RC type with corresponding string, that'll be looked for in |
402 | asm. */ | |
403 | struct RC_name | |
404 | { | |
405 | enum rc_type type; | |
406 | const char *name; | |
407 | unsigned int len; | |
408 | }; | |
409 | ||
410 | static const struct RC_name RC_NamesTable[] = | |
411 | { | |
412 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
413 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
414 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
415 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
416 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
417 | }; | |
418 | ||
252b5132 RH |
419 | /* List of chars besides those in app.c:symbol_chars that can start an |
420 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 421 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 422 | #ifdef LEX_AT |
32137342 NC |
423 | "@" |
424 | #endif | |
425 | #ifdef LEX_QM | |
426 | "?" | |
252b5132 | 427 | #endif |
32137342 | 428 | ; |
252b5132 | 429 | |
29b0f896 AM |
430 | #if (defined (TE_I386AIX) \ |
431 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 432 | && !defined (TE_GNU) \ |
29b0f896 | 433 | && !defined (TE_LINUX) \ |
8d63c93e RM |
434 | && !defined (TE_NACL) \ |
435 | && !defined (TE_NETWARE) \ | |
29b0f896 | 436 | && !defined (TE_FreeBSD) \ |
5b806d27 | 437 | && !defined (TE_DragonFly) \ |
29b0f896 | 438 | && !defined (TE_NetBSD))) |
252b5132 | 439 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
440 | pre-processor is disabled, these aren't very useful. The option |
441 | --divide will remove '/' from this list. */ | |
442 | const char *i386_comment_chars = "#/"; | |
443 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 444 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 445 | |
b3b91714 AM |
446 | #else |
447 | const char *i386_comment_chars = "#"; | |
448 | #define PREFIX_SEPARATOR '/' | |
449 | #endif | |
450 | ||
252b5132 RH |
451 | /* This array holds the chars that only start a comment at the beginning of |
452 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
453 | .line and .file directives will appear in the pre-processed output. |
454 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 455 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
456 | #NO_APP at the beginning of its output. |
457 | Also note that comments started like this one will always work if | |
252b5132 | 458 | '/' isn't otherwise defined. */ |
b3b91714 | 459 | const char line_comment_chars[] = "#/"; |
252b5132 | 460 | |
63a0b638 | 461 | const char line_separator_chars[] = ";"; |
252b5132 | 462 | |
ce8a8b2f AM |
463 | /* Chars that can be used to separate mant from exp in floating point |
464 | nums. */ | |
252b5132 RH |
465 | const char EXP_CHARS[] = "eE"; |
466 | ||
ce8a8b2f AM |
467 | /* Chars that mean this number is a floating point constant |
468 | As in 0f12.456 | |
469 | or 0d1.2345e12. */ | |
252b5132 RH |
470 | const char FLT_CHARS[] = "fFdDxX"; |
471 | ||
ce8a8b2f | 472 | /* Tables for lexical analysis. */ |
252b5132 RH |
473 | static char mnemonic_chars[256]; |
474 | static char register_chars[256]; | |
475 | static char operand_chars[256]; | |
476 | static char identifier_chars[256]; | |
477 | static char digit_chars[256]; | |
478 | ||
ce8a8b2f | 479 | /* Lexical macros. */ |
252b5132 RH |
480 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
481 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
482 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
483 | #define is_space_char(x) ((x) == ' ') | |
484 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
485 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
486 | ||
0234cb7c | 487 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
488 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
489 | ||
490 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
491 | effect this we maintain a stack of saved characters that we've smashed | |
492 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 493 | assembler instruction). */ |
252b5132 | 494 | static char save_stack[32]; |
ce8a8b2f | 495 | static char *save_stack_p; |
252b5132 RH |
496 | #define END_STRING_AND_SAVE(s) \ |
497 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
498 | #define RESTORE_END_STRING(s) \ | |
499 | do { *(s) = *--save_stack_p; } while (0) | |
500 | ||
47926f60 | 501 | /* The instruction we're assembling. */ |
252b5132 RH |
502 | static i386_insn i; |
503 | ||
504 | /* Possible templates for current insn. */ | |
505 | static const templates *current_templates; | |
506 | ||
31b2323c L |
507 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
508 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
509 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 510 | |
47926f60 | 511 | /* Current operand we are working on. */ |
ee86248c | 512 | static int this_operand = -1; |
252b5132 | 513 | |
3e73aa7c JH |
514 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
515 | these. */ | |
516 | ||
517 | enum flag_code { | |
518 | CODE_32BIT, | |
519 | CODE_16BIT, | |
520 | CODE_64BIT }; | |
521 | ||
522 | static enum flag_code flag_code; | |
4fa24527 | 523 | static unsigned int object_64bit; |
862be3fb | 524 | static unsigned int disallow_64bit_reloc; |
3e73aa7c JH |
525 | static int use_rela_relocations = 0; |
526 | ||
7af8ed2d NC |
527 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
528 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
529 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
530 | ||
351f65ca L |
531 | /* The ELF ABI to use. */ |
532 | enum x86_elf_abi | |
533 | { | |
534 | I386_ABI, | |
7f56bc95 L |
535 | X86_64_ABI, |
536 | X86_64_X32_ABI | |
351f65ca L |
537 | }; |
538 | ||
539 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 540 | #endif |
351f65ca | 541 | |
167ad85b TG |
542 | #if defined (TE_PE) || defined (TE_PEP) |
543 | /* Use big object file format. */ | |
544 | static int use_big_obj = 0; | |
545 | #endif | |
546 | ||
8dcea932 L |
547 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
548 | /* 1 if generating code for a shared library. */ | |
549 | static int shared = 0; | |
550 | #endif | |
551 | ||
47926f60 KH |
552 | /* 1 for intel syntax, |
553 | 0 if att syntax. */ | |
554 | static int intel_syntax = 0; | |
252b5132 | 555 | |
e89c5eaa L |
556 | /* 1 for Intel64 ISA, |
557 | 0 if AMD64 ISA. */ | |
558 | static int intel64; | |
559 | ||
1efbbeb4 L |
560 | /* 1 for intel mnemonic, |
561 | 0 if att mnemonic. */ | |
562 | static int intel_mnemonic = !SYSV386_COMPAT; | |
563 | ||
a60de03c JB |
564 | /* 1 if pseudo registers are permitted. */ |
565 | static int allow_pseudo_reg = 0; | |
566 | ||
47926f60 KH |
567 | /* 1 if register prefix % not required. */ |
568 | static int allow_naked_reg = 0; | |
252b5132 | 569 | |
33eaf5de | 570 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
571 | instructions supporting it, even if this prefix wasn't specified |
572 | explicitly. */ | |
573 | static int add_bnd_prefix = 0; | |
574 | ||
ba104c83 | 575 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
576 | static int allow_index_reg = 0; |
577 | ||
d022bddd IT |
578 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
579 | specified explicitly. */ | |
580 | static int omit_lock_prefix = 0; | |
581 | ||
e4e00185 AS |
582 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
583 | "lock addl $0, (%{re}sp)". */ | |
584 | static int avoid_fence = 0; | |
585 | ||
0cb4071e L |
586 | /* 1 if the assembler should generate relax relocations. */ |
587 | ||
588 | static int generate_relax_relocations | |
589 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
590 | ||
7bab8ab5 | 591 | static enum check_kind |
daf50ae7 | 592 | { |
7bab8ab5 JB |
593 | check_none = 0, |
594 | check_warning, | |
595 | check_error | |
daf50ae7 | 596 | } |
7bab8ab5 | 597 | sse_check, operand_check = check_warning; |
daf50ae7 | 598 | |
b6f8c7c4 L |
599 | /* Optimization: |
600 | 1. Clear the REX_W bit with register operand if possible. | |
601 | 2. Above plus use 128bit vector instruction to clear the full vector | |
602 | register. | |
603 | */ | |
604 | static int optimize = 0; | |
605 | ||
606 | /* Optimization: | |
607 | 1. Clear the REX_W bit with register operand if possible. | |
608 | 2. Above plus use 128bit vector instruction to clear the full vector | |
609 | register. | |
610 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
611 | "testb $imm7,%r8". | |
612 | */ | |
613 | static int optimize_for_space = 0; | |
614 | ||
2ca3ace5 L |
615 | /* Register prefix used for error message. */ |
616 | static const char *register_prefix = "%"; | |
617 | ||
47926f60 KH |
618 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
619 | leave, push, and pop instructions so that gcc has the same stack | |
620 | frame as in 32 bit mode. */ | |
621 | static char stackop_size = '\0'; | |
eecb386c | 622 | |
12b55ccc L |
623 | /* Non-zero to optimize code alignment. */ |
624 | int optimize_align_code = 1; | |
625 | ||
47926f60 KH |
626 | /* Non-zero to quieten some warnings. */ |
627 | static int quiet_warnings = 0; | |
a38cf1db | 628 | |
47926f60 KH |
629 | /* CPU name. */ |
630 | static const char *cpu_arch_name = NULL; | |
6305a203 | 631 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 632 | |
47926f60 | 633 | /* CPU feature flags. */ |
40fb9820 L |
634 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
635 | ||
ccc9c027 L |
636 | /* If we have selected a cpu we are generating instructions for. */ |
637 | static int cpu_arch_tune_set = 0; | |
638 | ||
9103f4f4 | 639 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 640 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
641 | |
642 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 643 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 644 | |
ccc9c027 | 645 | /* CPU instruction set architecture used. */ |
fbf3f584 | 646 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 647 | |
9103f4f4 | 648 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 649 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 650 | |
fddf5b5b AM |
651 | /* If set, conditional jumps are not automatically promoted to handle |
652 | larger than a byte offset. */ | |
653 | static unsigned int no_cond_jump_promotion = 0; | |
654 | ||
c0f3af97 L |
655 | /* Encode SSE instructions with VEX prefix. */ |
656 | static unsigned int sse2avx; | |
657 | ||
539f890d L |
658 | /* Encode scalar AVX instructions with specific vector length. */ |
659 | static enum | |
660 | { | |
661 | vex128 = 0, | |
662 | vex256 | |
663 | } avxscalar; | |
664 | ||
43234a1e L |
665 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
666 | static enum | |
667 | { | |
668 | evexl128 = 0, | |
669 | evexl256, | |
670 | evexl512 | |
671 | } evexlig; | |
672 | ||
673 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
674 | static enum | |
675 | { | |
676 | evexw0 = 0, | |
677 | evexw1 | |
678 | } evexwig; | |
679 | ||
d3d3c6db IT |
680 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
681 | static enum rc_type evexrcig = rne; | |
682 | ||
29b0f896 | 683 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 684 | static symbolS *GOT_symbol; |
29b0f896 | 685 | |
a4447b93 RH |
686 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
687 | unsigned int x86_dwarf2_return_column; | |
688 | ||
689 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
690 | int x86_cie_data_alignment; | |
691 | ||
252b5132 | 692 | /* Interface to relax_segment. |
fddf5b5b AM |
693 | There are 3 major relax states for 386 jump insns because the |
694 | different types of jumps add different sizes to frags when we're | |
695 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 696 | |
47926f60 | 697 | /* Types. */ |
93c2a809 AM |
698 | #define UNCOND_JUMP 0 |
699 | #define COND_JUMP 1 | |
700 | #define COND_JUMP86 2 | |
fddf5b5b | 701 | |
47926f60 | 702 | /* Sizes. */ |
252b5132 RH |
703 | #define CODE16 1 |
704 | #define SMALL 0 | |
29b0f896 | 705 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 706 | #define BIG 2 |
29b0f896 | 707 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
708 | |
709 | #ifndef INLINE | |
710 | #ifdef __GNUC__ | |
711 | #define INLINE __inline__ | |
712 | #else | |
713 | #define INLINE | |
714 | #endif | |
715 | #endif | |
716 | ||
fddf5b5b AM |
717 | #define ENCODE_RELAX_STATE(type, size) \ |
718 | ((relax_substateT) (((type) << 2) | (size))) | |
719 | #define TYPE_FROM_RELAX_STATE(s) \ | |
720 | ((s) >> 2) | |
721 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
722 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
723 | |
724 | /* This table is used by relax_frag to promote short jumps to long | |
725 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
726 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
727 | don't allow a short jump in a 32 bit code segment to be promoted to | |
728 | a 16 bit offset jump because it's slower (requires data size | |
729 | prefix), and doesn't work, unless the destination is in the bottom | |
730 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
731 | ||
732 | const relax_typeS md_relax_table[] = | |
733 | { | |
24eab124 AM |
734 | /* The fields are: |
735 | 1) most positive reach of this state, | |
736 | 2) most negative reach of this state, | |
93c2a809 | 737 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 738 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 739 | |
fddf5b5b | 740 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
741 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
742 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
743 | /* dword jmp adds 4 bytes to frag: | |
744 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 745 | {0, 0, 4, 0}, |
93c2a809 AM |
746 | /* word jmp adds 2 byte2 to frag: |
747 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
748 | {0, 0, 2, 0}, |
749 | ||
93c2a809 AM |
750 | /* COND_JUMP states. */ |
751 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
752 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
753 | /* dword conditionals adds 5 bytes to frag: | |
754 | 1 extra opcode byte, 4 displacement bytes. */ | |
755 | {0, 0, 5, 0}, | |
fddf5b5b | 756 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
757 | 1 extra opcode byte, 2 displacement bytes. */ |
758 | {0, 0, 3, 0}, | |
759 | ||
760 | /* COND_JUMP86 states. */ | |
761 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
762 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
763 | /* dword conditionals adds 5 bytes to frag: | |
764 | 1 extra opcode byte, 4 displacement bytes. */ | |
765 | {0, 0, 5, 0}, | |
766 | /* word conditionals add 4 bytes to frag: | |
767 | 1 displacement byte and a 3 byte long branch insn. */ | |
768 | {0, 0, 4, 0} | |
252b5132 RH |
769 | }; |
770 | ||
9103f4f4 L |
771 | static const arch_entry cpu_arch[] = |
772 | { | |
89507696 JB |
773 | /* Do not replace the first two entries - i386_target_format() |
774 | relies on them being there in this order. */ | |
8a2c8fef | 775 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 776 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 777 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 778 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 779 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 780 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 781 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 782 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 783 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 784 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 785 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 786 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 787 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 788 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 789 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 790 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 791 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 792 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 793 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 794 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 795 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 796 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 797 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 798 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 799 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 800 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 801 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 802 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 803 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 804 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 805 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 806 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 807 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 808 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 809 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 810 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 811 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 812 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 813 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 814 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 815 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 816 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 817 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 818 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 819 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 820 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 821 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 822 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 823 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 824 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 825 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 826 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 827 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 828 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 829 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 830 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 831 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 832 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 833 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 834 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 835 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 836 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 837 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 838 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 839 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 840 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 841 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 842 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 843 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 844 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 845 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 846 | CPU_ZNVER1_FLAGS, 0 }, |
7b458c12 | 847 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 848 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 849 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 850 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 851 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 852 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 853 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 854 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 855 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 856 | CPU_387_FLAGS, 0 }, |
1848e567 L |
857 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
858 | CPU_687_FLAGS, 0 }, | |
8a2c8fef | 859 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 860 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 861 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 862 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 863 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 864 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 865 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 866 | CPU_SSE3_FLAGS, 0 }, |
8a2c8fef | 867 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 868 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 869 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 870 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 871 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 872 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 873 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 874 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 875 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 876 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 877 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 878 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 879 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 880 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 881 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 882 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 883 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 884 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 885 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 886 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 887 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 888 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 889 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 890 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 891 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 892 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 893 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 894 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 895 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 896 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 897 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 898 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 899 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 900 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 901 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 902 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 903 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 904 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 905 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 906 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 907 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 908 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 909 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 910 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 911 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 912 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 913 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 914 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 915 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 916 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 917 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 918 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 919 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 920 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 921 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 922 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 923 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 924 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 925 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 926 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 927 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 928 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 929 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 930 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 931 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 932 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 933 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 934 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 935 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 936 | CPU_LZCNT_FLAGS, 0 }, |
42164a71 | 937 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 938 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 939 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 940 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 941 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 942 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 943 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 944 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 945 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 946 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 947 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 948 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 949 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 950 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 951 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 952 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 953 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 954 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 955 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 956 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 957 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 958 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 959 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 960 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 961 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 962 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 963 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 964 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 965 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 966 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 967 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 968 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 969 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 970 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 971 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 972 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 973 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 974 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 975 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 976 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 977 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 978 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 979 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 980 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 981 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 982 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 983 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 984 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 985 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 986 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 987 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 988 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 989 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 990 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 991 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 992 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
993 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
994 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
995 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
996 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
997 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
998 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
999 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1000 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1001 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1002 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1003 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1004 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 1005 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1006 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1007 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1008 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1009 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1010 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1011 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1012 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1013 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1014 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1015 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1016 | CPU_IBT_FLAGS, 0 }, | |
1017 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1018 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1019 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1020 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1021 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1022 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1023 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1024 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1025 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1026 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1027 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1028 | CPU_PCONFIG_FLAGS, 0 }, | |
293f5f65 L |
1029 | }; |
1030 | ||
1031 | static const noarch_entry cpu_noarch[] = | |
1032 | { | |
1033 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1034 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1035 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1036 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
293f5f65 L |
1037 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1038 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1039 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1040 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
1041 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, | |
1042 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1043 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
1044 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, | |
293f5f65 | 1045 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1046 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1047 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1048 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1049 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1050 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1051 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1052 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1053 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1054 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1055 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1056 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1057 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1058 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1059 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1060 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1061 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1062 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1063 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
e413e4e9 AM |
1064 | }; |
1065 | ||
704209c0 | 1066 | #ifdef I386COFF |
a6c24e68 NC |
1067 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1068 | is allowed to be optional. */ | |
1069 | ||
1070 | static symbolS * | |
1071 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1072 | { | |
1073 | addressT align = 0; | |
1074 | ||
1075 | SKIP_WHITESPACE (); | |
1076 | ||
7ab9ffdd | 1077 | if (needs_align |
a6c24e68 NC |
1078 | && *input_line_pointer == ',') |
1079 | { | |
1080 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1081 | |
a6c24e68 NC |
1082 | if (align == (addressT) -1) |
1083 | return NULL; | |
1084 | } | |
1085 | else | |
1086 | { | |
1087 | if (size >= 8) | |
1088 | align = 3; | |
1089 | else if (size >= 4) | |
1090 | align = 2; | |
1091 | else if (size >= 2) | |
1092 | align = 1; | |
1093 | else | |
1094 | align = 0; | |
1095 | } | |
1096 | ||
1097 | bss_alloc (symbolP, size, align); | |
1098 | return symbolP; | |
1099 | } | |
1100 | ||
704209c0 | 1101 | static void |
a6c24e68 NC |
1102 | pe_lcomm (int needs_align) |
1103 | { | |
1104 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1105 | } | |
704209c0 | 1106 | #endif |
a6c24e68 | 1107 | |
29b0f896 AM |
1108 | const pseudo_typeS md_pseudo_table[] = |
1109 | { | |
1110 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1111 | {"align", s_align_bytes, 0}, | |
1112 | #else | |
1113 | {"align", s_align_ptwo, 0}, | |
1114 | #endif | |
1115 | {"arch", set_cpu_arch, 0}, | |
1116 | #ifndef I386COFF | |
1117 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1118 | #else |
1119 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1120 | #endif |
1121 | {"ffloat", float_cons, 'f'}, | |
1122 | {"dfloat", float_cons, 'd'}, | |
1123 | {"tfloat", float_cons, 'x'}, | |
1124 | {"value", cons, 2}, | |
d182319b | 1125 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1126 | {"noopt", s_ignore, 0}, |
1127 | {"optim", s_ignore, 0}, | |
1128 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1129 | {"code16", set_code_flag, CODE_16BIT}, | |
1130 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1131 | #ifdef BFD64 |
29b0f896 | 1132 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1133 | #endif |
29b0f896 AM |
1134 | {"intel_syntax", set_intel_syntax, 1}, |
1135 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1136 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1137 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1138 | {"allow_index_reg", set_allow_index_reg, 1}, |
1139 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1140 | {"sse_check", set_check, 0}, |
1141 | {"operand_check", set_check, 1}, | |
3b22753a L |
1142 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1143 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1144 | #else |
68d20676 | 1145 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1146 | {"loc", dwarf2_directive_loc, 0}, |
1147 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1148 | #endif |
6482c264 NC |
1149 | #ifdef TE_PE |
1150 | {"secrel32", pe_directive_secrel, 0}, | |
1151 | #endif | |
29b0f896 AM |
1152 | {0, 0, 0} |
1153 | }; | |
1154 | ||
1155 | /* For interface with expression (). */ | |
1156 | extern char *input_line_pointer; | |
1157 | ||
1158 | /* Hash table for instruction mnemonic lookup. */ | |
1159 | static struct hash_control *op_hash; | |
1160 | ||
1161 | /* Hash table for register lookup. */ | |
1162 | static struct hash_control *reg_hash; | |
1163 | \f | |
ce8a8b2f AM |
1164 | /* Various efficient no-op patterns for aligning code labels. |
1165 | Note: Don't try to assemble the instructions in the comments. | |
1166 | 0L and 0w are not legal. */ | |
62a02d25 L |
1167 | static const unsigned char f32_1[] = |
1168 | {0x90}; /* nop */ | |
1169 | static const unsigned char f32_2[] = | |
1170 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1171 | static const unsigned char f32_3[] = | |
1172 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1173 | static const unsigned char f32_4[] = | |
1174 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1175 | static const unsigned char f32_6[] = |
1176 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1177 | static const unsigned char f32_7[] = | |
1178 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1179 | static const unsigned char f16_3[] = |
3ae729d5 | 1180 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1181 | static const unsigned char f16_4[] = |
3ae729d5 L |
1182 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1183 | static const unsigned char jump_disp8[] = | |
1184 | {0xeb}; /* jmp disp8 */ | |
1185 | static const unsigned char jump32_disp32[] = | |
1186 | {0xe9}; /* jmp disp32 */ | |
1187 | static const unsigned char jump16_disp32[] = | |
1188 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1189 | /* 32-bit NOPs patterns. */ |
1190 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1191 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1192 | }; |
1193 | /* 16-bit NOPs patterns. */ | |
1194 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1195 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1196 | }; |
1197 | /* nopl (%[re]ax) */ | |
1198 | static const unsigned char alt_3[] = | |
1199 | {0x0f,0x1f,0x00}; | |
1200 | /* nopl 0(%[re]ax) */ | |
1201 | static const unsigned char alt_4[] = | |
1202 | {0x0f,0x1f,0x40,0x00}; | |
1203 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1204 | static const unsigned char alt_5[] = | |
1205 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1206 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1207 | static const unsigned char alt_6[] = | |
1208 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1209 | /* nopl 0L(%[re]ax) */ | |
1210 | static const unsigned char alt_7[] = | |
1211 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1212 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1213 | static const unsigned char alt_8[] = | |
1214 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1215 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1216 | static const unsigned char alt_9[] = | |
1217 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1218 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1219 | static const unsigned char alt_10[] = | |
1220 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1221 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1222 | static const unsigned char alt_11[] = | |
1223 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1224 | /* 32-bit and 64-bit NOPs patterns. */ |
1225 | static const unsigned char *const alt_patt[] = { | |
1226 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1227 | alt_9, alt_10, alt_11 |
62a02d25 L |
1228 | }; |
1229 | ||
1230 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1231 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1232 | ||
1233 | static void | |
1234 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1235 | int count, int max_single_nop_size) | |
1236 | ||
1237 | { | |
3ae729d5 L |
1238 | /* Place the longer NOP first. */ |
1239 | int last; | |
1240 | int offset; | |
1241 | const unsigned char *nops = patt[max_single_nop_size - 1]; | |
1242 | ||
1243 | /* Use the smaller one if the requsted one isn't available. */ | |
1244 | if (nops == NULL) | |
62a02d25 | 1245 | { |
3ae729d5 L |
1246 | max_single_nop_size--; |
1247 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1248 | } |
1249 | ||
3ae729d5 L |
1250 | last = count % max_single_nop_size; |
1251 | ||
1252 | count -= last; | |
1253 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1254 | memcpy (where + offset, nops, max_single_nop_size); | |
1255 | ||
1256 | if (last) | |
1257 | { | |
1258 | nops = patt[last - 1]; | |
1259 | if (nops == NULL) | |
1260 | { | |
1261 | /* Use the smaller one plus one-byte NOP if the needed one | |
1262 | isn't available. */ | |
1263 | last--; | |
1264 | nops = patt[last - 1]; | |
1265 | memcpy (where + offset, nops, last); | |
1266 | where[offset + last] = *patt[0]; | |
1267 | } | |
1268 | else | |
1269 | memcpy (where + offset, nops, last); | |
1270 | } | |
62a02d25 L |
1271 | } |
1272 | ||
3ae729d5 L |
1273 | static INLINE int |
1274 | fits_in_imm7 (offsetT num) | |
1275 | { | |
1276 | return (num & 0x7f) == num; | |
1277 | } | |
1278 | ||
1279 | static INLINE int | |
1280 | fits_in_imm31 (offsetT num) | |
1281 | { | |
1282 | return (num & 0x7fffffff) == num; | |
1283 | } | |
62a02d25 L |
1284 | |
1285 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1286 | single NOP instruction LIMIT. */ | |
1287 | ||
1288 | void | |
3ae729d5 | 1289 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1290 | { |
3ae729d5 | 1291 | const unsigned char *const *patt = NULL; |
62a02d25 | 1292 | int max_single_nop_size; |
3ae729d5 L |
1293 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1294 | int max_number_of_nops; | |
62a02d25 | 1295 | |
3ae729d5 | 1296 | switch (fragP->fr_type) |
62a02d25 | 1297 | { |
3ae729d5 L |
1298 | case rs_fill_nop: |
1299 | case rs_align_code: | |
1300 | break; | |
1301 | default: | |
62a02d25 L |
1302 | return; |
1303 | } | |
1304 | ||
ccc9c027 L |
1305 | /* We need to decide which NOP sequence to use for 32bit and |
1306 | 64bit. When -mtune= is used: | |
4eed87de | 1307 | |
76bc74dc L |
1308 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1309 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1310 | 2. For the rest, alt_patt will be used. |
1311 | ||
1312 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1313 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1314 | be used. |
ccc9c027 L |
1315 | |
1316 | When -march= or .arch is used, we can't use anything beyond | |
1317 | cpu_arch_isa_flags. */ | |
1318 | ||
1319 | if (flag_code == CODE_16BIT) | |
1320 | { | |
3ae729d5 L |
1321 | patt = f16_patt; |
1322 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1323 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1324 | max_number_of_nops = 2; | |
252b5132 | 1325 | } |
33fef721 | 1326 | else |
ccc9c027 | 1327 | { |
fbf3f584 | 1328 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1329 | { |
1330 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1331 | switch (cpu_arch_tune) | |
1332 | { | |
1333 | case PROCESSOR_UNKNOWN: | |
1334 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1335 | optimize with nops. */ |
1336 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1337 | patt = alt_patt; |
ccc9c027 L |
1338 | else |
1339 | patt = f32_patt; | |
1340 | break; | |
ccc9c027 L |
1341 | case PROCESSOR_PENTIUM4: |
1342 | case PROCESSOR_NOCONA: | |
ef05d495 | 1343 | case PROCESSOR_CORE: |
76bc74dc | 1344 | case PROCESSOR_CORE2: |
bd5295b2 | 1345 | case PROCESSOR_COREI7: |
3632d14b | 1346 | case PROCESSOR_L1OM: |
7a9068fe | 1347 | case PROCESSOR_K1OM: |
76bc74dc | 1348 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1349 | case PROCESSOR_K6: |
1350 | case PROCESSOR_ATHLON: | |
1351 | case PROCESSOR_K8: | |
4eed87de | 1352 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1353 | case PROCESSOR_BD: |
029f3522 | 1354 | case PROCESSOR_ZNVER: |
7b458c12 | 1355 | case PROCESSOR_BT: |
80b8656c | 1356 | patt = alt_patt; |
ccc9c027 | 1357 | break; |
76bc74dc | 1358 | case PROCESSOR_I386: |
ccc9c027 L |
1359 | case PROCESSOR_I486: |
1360 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1361 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1362 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1363 | case PROCESSOR_GENERIC32: |
1364 | patt = f32_patt; | |
1365 | break; | |
4eed87de | 1366 | } |
ccc9c027 L |
1367 | } |
1368 | else | |
1369 | { | |
fbf3f584 | 1370 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1371 | { |
1372 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1373 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1374 | PROCESSOR_UNKNOWN. */ |
1375 | abort (); | |
1376 | break; | |
1377 | ||
76bc74dc | 1378 | case PROCESSOR_I386: |
ccc9c027 L |
1379 | case PROCESSOR_I486: |
1380 | case PROCESSOR_PENTIUM: | |
81486035 | 1381 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1382 | case PROCESSOR_K6: |
1383 | case PROCESSOR_ATHLON: | |
1384 | case PROCESSOR_K8: | |
4eed87de | 1385 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1386 | case PROCESSOR_BD: |
029f3522 | 1387 | case PROCESSOR_ZNVER: |
7b458c12 | 1388 | case PROCESSOR_BT: |
ccc9c027 L |
1389 | case PROCESSOR_GENERIC32: |
1390 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1391 | with nops. */ |
1392 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1393 | patt = alt_patt; |
ccc9c027 L |
1394 | else |
1395 | patt = f32_patt; | |
1396 | break; | |
76bc74dc L |
1397 | case PROCESSOR_PENTIUMPRO: |
1398 | case PROCESSOR_PENTIUM4: | |
1399 | case PROCESSOR_NOCONA: | |
1400 | case PROCESSOR_CORE: | |
ef05d495 | 1401 | case PROCESSOR_CORE2: |
bd5295b2 | 1402 | case PROCESSOR_COREI7: |
3632d14b | 1403 | case PROCESSOR_L1OM: |
7a9068fe | 1404 | case PROCESSOR_K1OM: |
22109423 | 1405 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1406 | patt = alt_patt; |
ccc9c027 L |
1407 | else |
1408 | patt = f32_patt; | |
1409 | break; | |
1410 | case PROCESSOR_GENERIC64: | |
80b8656c | 1411 | patt = alt_patt; |
ccc9c027 | 1412 | break; |
4eed87de | 1413 | } |
ccc9c027 L |
1414 | } |
1415 | ||
76bc74dc L |
1416 | if (patt == f32_patt) |
1417 | { | |
3ae729d5 L |
1418 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1419 | /* Limit number of NOPs to 2 for older processors. */ | |
1420 | max_number_of_nops = 2; | |
76bc74dc L |
1421 | } |
1422 | else | |
1423 | { | |
3ae729d5 L |
1424 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1425 | /* Limit number of NOPs to 7 for newer processors. */ | |
1426 | max_number_of_nops = 7; | |
1427 | } | |
1428 | } | |
1429 | ||
1430 | if (limit == 0) | |
1431 | limit = max_single_nop_size; | |
1432 | ||
1433 | if (fragP->fr_type == rs_fill_nop) | |
1434 | { | |
1435 | /* Output NOPs for .nop directive. */ | |
1436 | if (limit > max_single_nop_size) | |
1437 | { | |
1438 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1439 | _("invalid single nop size: %d " | |
1440 | "(expect within [0, %d])"), | |
1441 | limit, max_single_nop_size); | |
1442 | return; | |
1443 | } | |
1444 | } | |
1445 | else | |
1446 | fragP->fr_var = count; | |
1447 | ||
1448 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1449 | { | |
1450 | /* Generate jump over NOPs. */ | |
1451 | offsetT disp = count - 2; | |
1452 | if (fits_in_imm7 (disp)) | |
1453 | { | |
1454 | /* Use "jmp disp8" if possible. */ | |
1455 | count = disp; | |
1456 | where[0] = jump_disp8[0]; | |
1457 | where[1] = count; | |
1458 | where += 2; | |
1459 | } | |
1460 | else | |
1461 | { | |
1462 | unsigned int size_of_jump; | |
1463 | ||
1464 | if (flag_code == CODE_16BIT) | |
1465 | { | |
1466 | where[0] = jump16_disp32[0]; | |
1467 | where[1] = jump16_disp32[1]; | |
1468 | size_of_jump = 2; | |
1469 | } | |
1470 | else | |
1471 | { | |
1472 | where[0] = jump32_disp32[0]; | |
1473 | size_of_jump = 1; | |
1474 | } | |
1475 | ||
1476 | count -= size_of_jump + 4; | |
1477 | if (!fits_in_imm31 (count)) | |
1478 | { | |
1479 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1480 | _("jump over nop padding out of range")); | |
1481 | return; | |
1482 | } | |
1483 | ||
1484 | md_number_to_chars (where + size_of_jump, count, 4); | |
1485 | where += size_of_jump + 4; | |
76bc74dc | 1486 | } |
ccc9c027 | 1487 | } |
3ae729d5 L |
1488 | |
1489 | /* Generate multiple NOPs. */ | |
1490 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1491 | } |
1492 | ||
c6fb90c8 | 1493 | static INLINE int |
0dfbf9d7 | 1494 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1495 | { |
0dfbf9d7 | 1496 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1497 | { |
1498 | case 3: | |
0dfbf9d7 | 1499 | if (x->array[2]) |
c6fb90c8 | 1500 | return 0; |
1a0670f3 | 1501 | /* Fall through. */ |
c6fb90c8 | 1502 | case 2: |
0dfbf9d7 | 1503 | if (x->array[1]) |
c6fb90c8 | 1504 | return 0; |
1a0670f3 | 1505 | /* Fall through. */ |
c6fb90c8 | 1506 | case 1: |
0dfbf9d7 | 1507 | return !x->array[0]; |
c6fb90c8 L |
1508 | default: |
1509 | abort (); | |
1510 | } | |
40fb9820 L |
1511 | } |
1512 | ||
c6fb90c8 | 1513 | static INLINE void |
0dfbf9d7 | 1514 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1515 | { |
0dfbf9d7 | 1516 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1517 | { |
1518 | case 3: | |
0dfbf9d7 | 1519 | x->array[2] = v; |
1a0670f3 | 1520 | /* Fall through. */ |
c6fb90c8 | 1521 | case 2: |
0dfbf9d7 | 1522 | x->array[1] = v; |
1a0670f3 | 1523 | /* Fall through. */ |
c6fb90c8 | 1524 | case 1: |
0dfbf9d7 | 1525 | x->array[0] = v; |
1a0670f3 | 1526 | /* Fall through. */ |
c6fb90c8 L |
1527 | break; |
1528 | default: | |
1529 | abort (); | |
1530 | } | |
1531 | } | |
40fb9820 | 1532 | |
c6fb90c8 | 1533 | static INLINE int |
0dfbf9d7 L |
1534 | operand_type_equal (const union i386_operand_type *x, |
1535 | const union i386_operand_type *y) | |
c6fb90c8 | 1536 | { |
0dfbf9d7 | 1537 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1538 | { |
1539 | case 3: | |
0dfbf9d7 | 1540 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1541 | return 0; |
1a0670f3 | 1542 | /* Fall through. */ |
c6fb90c8 | 1543 | case 2: |
0dfbf9d7 | 1544 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1545 | return 0; |
1a0670f3 | 1546 | /* Fall through. */ |
c6fb90c8 | 1547 | case 1: |
0dfbf9d7 | 1548 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1549 | break; |
1550 | default: | |
1551 | abort (); | |
1552 | } | |
1553 | } | |
40fb9820 | 1554 | |
0dfbf9d7 L |
1555 | static INLINE int |
1556 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1557 | { | |
1558 | switch (ARRAY_SIZE(x->array)) | |
1559 | { | |
53467f57 IT |
1560 | case 4: |
1561 | if (x->array[3]) | |
1562 | return 0; | |
1563 | /* Fall through. */ | |
0dfbf9d7 L |
1564 | case 3: |
1565 | if (x->array[2]) | |
1566 | return 0; | |
1a0670f3 | 1567 | /* Fall through. */ |
0dfbf9d7 L |
1568 | case 2: |
1569 | if (x->array[1]) | |
1570 | return 0; | |
1a0670f3 | 1571 | /* Fall through. */ |
0dfbf9d7 L |
1572 | case 1: |
1573 | return !x->array[0]; | |
1574 | default: | |
1575 | abort (); | |
1576 | } | |
1577 | } | |
1578 | ||
0dfbf9d7 L |
1579 | static INLINE int |
1580 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1581 | const union i386_cpu_flags *y) | |
1582 | { | |
1583 | switch (ARRAY_SIZE(x->array)) | |
1584 | { | |
53467f57 IT |
1585 | case 4: |
1586 | if (x->array[3] != y->array[3]) | |
1587 | return 0; | |
1588 | /* Fall through. */ | |
0dfbf9d7 L |
1589 | case 3: |
1590 | if (x->array[2] != y->array[2]) | |
1591 | return 0; | |
1a0670f3 | 1592 | /* Fall through. */ |
0dfbf9d7 L |
1593 | case 2: |
1594 | if (x->array[1] != y->array[1]) | |
1595 | return 0; | |
1a0670f3 | 1596 | /* Fall through. */ |
0dfbf9d7 L |
1597 | case 1: |
1598 | return x->array[0] == y->array[0]; | |
1599 | break; | |
1600 | default: | |
1601 | abort (); | |
1602 | } | |
1603 | } | |
c6fb90c8 L |
1604 | |
1605 | static INLINE int | |
1606 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1607 | { | |
1608 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1609 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1610 | } |
1611 | ||
c6fb90c8 L |
1612 | static INLINE i386_cpu_flags |
1613 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1614 | { |
c6fb90c8 L |
1615 | switch (ARRAY_SIZE (x.array)) |
1616 | { | |
53467f57 IT |
1617 | case 4: |
1618 | x.array [3] &= y.array [3]; | |
1619 | /* Fall through. */ | |
c6fb90c8 L |
1620 | case 3: |
1621 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1622 | /* Fall through. */ |
c6fb90c8 L |
1623 | case 2: |
1624 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1625 | /* Fall through. */ |
c6fb90c8 L |
1626 | case 1: |
1627 | x.array [0] &= y.array [0]; | |
1628 | break; | |
1629 | default: | |
1630 | abort (); | |
1631 | } | |
1632 | return x; | |
1633 | } | |
40fb9820 | 1634 | |
c6fb90c8 L |
1635 | static INLINE i386_cpu_flags |
1636 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1637 | { |
c6fb90c8 | 1638 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1639 | { |
53467f57 IT |
1640 | case 4: |
1641 | x.array [3] |= y.array [3]; | |
1642 | /* Fall through. */ | |
c6fb90c8 L |
1643 | case 3: |
1644 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1645 | /* Fall through. */ |
c6fb90c8 L |
1646 | case 2: |
1647 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1648 | /* Fall through. */ |
c6fb90c8 L |
1649 | case 1: |
1650 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1651 | break; |
1652 | default: | |
1653 | abort (); | |
1654 | } | |
40fb9820 L |
1655 | return x; |
1656 | } | |
1657 | ||
309d3373 JB |
1658 | static INLINE i386_cpu_flags |
1659 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1660 | { | |
1661 | switch (ARRAY_SIZE (x.array)) | |
1662 | { | |
53467f57 IT |
1663 | case 4: |
1664 | x.array [3] &= ~y.array [3]; | |
1665 | /* Fall through. */ | |
309d3373 JB |
1666 | case 3: |
1667 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1668 | /* Fall through. */ |
309d3373 JB |
1669 | case 2: |
1670 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1671 | /* Fall through. */ |
309d3373 JB |
1672 | case 1: |
1673 | x.array [0] &= ~y.array [0]; | |
1674 | break; | |
1675 | default: | |
1676 | abort (); | |
1677 | } | |
1678 | return x; | |
1679 | } | |
1680 | ||
c0f3af97 L |
1681 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1682 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1683 | ||
c0f3af97 | 1684 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1685 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1686 | |
1687 | /* Return CPU flags match bits. */ | |
3629bb00 | 1688 | |
40fb9820 | 1689 | static int |
d3ce72d0 | 1690 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1691 | { |
c0f3af97 L |
1692 | i386_cpu_flags x = t->cpu_flags; |
1693 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1694 | |
1695 | x.bitfield.cpu64 = 0; | |
1696 | x.bitfield.cpuno64 = 0; | |
1697 | ||
0dfbf9d7 | 1698 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1699 | { |
1700 | /* This instruction is available on all archs. */ | |
db12e14e | 1701 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1702 | } |
3629bb00 L |
1703 | else |
1704 | { | |
c0f3af97 | 1705 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1706 | i386_cpu_flags cpu = cpu_arch_flags; |
1707 | ||
ab592e75 JB |
1708 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1709 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1710 | return match; | |
1711 | x.bitfield.cpuavx512vl = 0; | |
1712 | ||
3629bb00 | 1713 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1714 | if (!cpu_flags_all_zero (&cpu)) |
1715 | { | |
a5ff0eb2 L |
1716 | if (x.bitfield.cpuavx) |
1717 | { | |
929f69fa | 1718 | /* We need to check a few extra flags with AVX. */ |
b9d49817 JB |
1719 | if (cpu.bitfield.cpuavx |
1720 | && (!t->opcode_modifier.sse2avx || sse2avx) | |
1721 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
929f69fa | 1722 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1723 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1724 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1725 | } |
929f69fa JB |
1726 | else if (x.bitfield.cpuavx512f) |
1727 | { | |
1728 | /* We need to check a few extra flags with AVX512F. */ | |
1729 | if (cpu.bitfield.cpuavx512f | |
1730 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1731 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1732 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1733 | match |= CPU_FLAGS_ARCH_MATCH; | |
1734 | } | |
a5ff0eb2 | 1735 | else |
db12e14e | 1736 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1737 | } |
3629bb00 | 1738 | } |
c0f3af97 | 1739 | return match; |
40fb9820 L |
1740 | } |
1741 | ||
c6fb90c8 L |
1742 | static INLINE i386_operand_type |
1743 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1744 | { |
c6fb90c8 L |
1745 | switch (ARRAY_SIZE (x.array)) |
1746 | { | |
1747 | case 3: | |
1748 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1749 | /* Fall through. */ |
c6fb90c8 L |
1750 | case 2: |
1751 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1752 | /* Fall through. */ |
c6fb90c8 L |
1753 | case 1: |
1754 | x.array [0] &= y.array [0]; | |
1755 | break; | |
1756 | default: | |
1757 | abort (); | |
1758 | } | |
1759 | return x; | |
40fb9820 L |
1760 | } |
1761 | ||
73053c1f JB |
1762 | static INLINE i386_operand_type |
1763 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1764 | { | |
1765 | switch (ARRAY_SIZE (x.array)) | |
1766 | { | |
1767 | case 3: | |
1768 | x.array [2] &= ~y.array [2]; | |
1769 | /* Fall through. */ | |
1770 | case 2: | |
1771 | x.array [1] &= ~y.array [1]; | |
1772 | /* Fall through. */ | |
1773 | case 1: | |
1774 | x.array [0] &= ~y.array [0]; | |
1775 | break; | |
1776 | default: | |
1777 | abort (); | |
1778 | } | |
1779 | return x; | |
1780 | } | |
1781 | ||
c6fb90c8 L |
1782 | static INLINE i386_operand_type |
1783 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1784 | { |
c6fb90c8 | 1785 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1786 | { |
c6fb90c8 L |
1787 | case 3: |
1788 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1789 | /* Fall through. */ |
c6fb90c8 L |
1790 | case 2: |
1791 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1792 | /* Fall through. */ |
c6fb90c8 L |
1793 | case 1: |
1794 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1795 | break; |
1796 | default: | |
1797 | abort (); | |
1798 | } | |
c6fb90c8 L |
1799 | return x; |
1800 | } | |
40fb9820 | 1801 | |
c6fb90c8 L |
1802 | static INLINE i386_operand_type |
1803 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1804 | { | |
1805 | switch (ARRAY_SIZE (x.array)) | |
1806 | { | |
1807 | case 3: | |
1808 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 1809 | /* Fall through. */ |
c6fb90c8 L |
1810 | case 2: |
1811 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 1812 | /* Fall through. */ |
c6fb90c8 L |
1813 | case 1: |
1814 | x.array [0] ^= y.array [0]; | |
1815 | break; | |
1816 | default: | |
1817 | abort (); | |
1818 | } | |
40fb9820 L |
1819 | return x; |
1820 | } | |
1821 | ||
1822 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1823 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
1824 | static const i386_operand_type control = OPERAND_TYPE_CONTROL; | |
65da13b5 L |
1825 | static const i386_operand_type inoutportreg |
1826 | = OPERAND_TYPE_INOUTPORTREG; | |
40fb9820 L |
1827 | static const i386_operand_type reg16_inoutportreg |
1828 | = OPERAND_TYPE_REG16_INOUTPORTREG; | |
1829 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; | |
1830 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1831 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1832 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1833 | static const i386_operand_type anydisp | |
1834 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1835 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 1836 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
1837 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1838 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1839 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1840 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1841 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1842 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1843 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1844 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1845 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
a683cc34 | 1846 | static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; |
40fb9820 L |
1847 | |
1848 | enum operand_type | |
1849 | { | |
1850 | reg, | |
40fb9820 L |
1851 | imm, |
1852 | disp, | |
1853 | anymem | |
1854 | }; | |
1855 | ||
c6fb90c8 | 1856 | static INLINE int |
40fb9820 L |
1857 | operand_type_check (i386_operand_type t, enum operand_type c) |
1858 | { | |
1859 | switch (c) | |
1860 | { | |
1861 | case reg: | |
dc821c5f | 1862 | return t.bitfield.reg; |
40fb9820 | 1863 | |
40fb9820 L |
1864 | case imm: |
1865 | return (t.bitfield.imm8 | |
1866 | || t.bitfield.imm8s | |
1867 | || t.bitfield.imm16 | |
1868 | || t.bitfield.imm32 | |
1869 | || t.bitfield.imm32s | |
1870 | || t.bitfield.imm64); | |
1871 | ||
1872 | case disp: | |
1873 | return (t.bitfield.disp8 | |
1874 | || t.bitfield.disp16 | |
1875 | || t.bitfield.disp32 | |
1876 | || t.bitfield.disp32s | |
1877 | || t.bitfield.disp64); | |
1878 | ||
1879 | case anymem: | |
1880 | return (t.bitfield.disp8 | |
1881 | || t.bitfield.disp16 | |
1882 | || t.bitfield.disp32 | |
1883 | || t.bitfield.disp32s | |
1884 | || t.bitfield.disp64 | |
1885 | || t.bitfield.baseindex); | |
1886 | ||
1887 | default: | |
1888 | abort (); | |
1889 | } | |
2cfe26b6 AM |
1890 | |
1891 | return 0; | |
40fb9820 L |
1892 | } |
1893 | ||
ca0d63fe | 1894 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on |
5c07affc L |
1895 | operand J for instruction template T. */ |
1896 | ||
1897 | static INLINE int | |
d3ce72d0 | 1898 | match_reg_size (const insn_template *t, unsigned int j) |
5c07affc L |
1899 | { |
1900 | return !((i.types[j].bitfield.byte | |
1901 | && !t->operand_types[j].bitfield.byte) | |
1902 | || (i.types[j].bitfield.word | |
1903 | && !t->operand_types[j].bitfield.word) | |
1904 | || (i.types[j].bitfield.dword | |
1905 | && !t->operand_types[j].bitfield.dword) | |
1906 | || (i.types[j].bitfield.qword | |
ca0d63fe JB |
1907 | && !t->operand_types[j].bitfield.qword) |
1908 | || (i.types[j].bitfield.tbyte | |
1909 | && !t->operand_types[j].bitfield.tbyte)); | |
5c07affc L |
1910 | } |
1911 | ||
1b54b8d7 JB |
1912 | /* Return 1 if there is no conflict in SIMD register on |
1913 | operand J for instruction template T. */ | |
1914 | ||
1915 | static INLINE int | |
1916 | match_simd_size (const insn_template *t, unsigned int j) | |
1917 | { | |
1918 | return !((i.types[j].bitfield.xmmword | |
1919 | && !t->operand_types[j].bitfield.xmmword) | |
1920 | || (i.types[j].bitfield.ymmword | |
1921 | && !t->operand_types[j].bitfield.ymmword) | |
1922 | || (i.types[j].bitfield.zmmword | |
1923 | && !t->operand_types[j].bitfield.zmmword)); | |
1924 | } | |
1925 | ||
5c07affc L |
1926 | /* Return 1 if there is no conflict in any size on operand J for |
1927 | instruction template T. */ | |
1928 | ||
1929 | static INLINE int | |
d3ce72d0 | 1930 | match_mem_size (const insn_template *t, unsigned int j) |
5c07affc L |
1931 | { |
1932 | return (match_reg_size (t, j) | |
1933 | && !((i.types[j].bitfield.unspecified | |
af508cb9 | 1934 | && !i.broadcast |
5c07affc L |
1935 | && !t->operand_types[j].bitfield.unspecified) |
1936 | || (i.types[j].bitfield.fword | |
1937 | && !t->operand_types[j].bitfield.fword) | |
1b54b8d7 JB |
1938 | /* For scalar opcode templates to allow register and memory |
1939 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
1940 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
1941 | down-conversion vpmov*. */ | |
1b54b8d7 JB |
1942 | || ((t->operand_types[j].bitfield.regsimd |
1943 | && !t->opcode_modifier.broadcast | |
d6793fa1 JB |
1944 | && (t->operand_types[j].bitfield.byte |
1945 | || t->operand_types[j].bitfield.word | |
1946 | || t->operand_types[j].bitfield.dword | |
1b54b8d7 JB |
1947 | || t->operand_types[j].bitfield.qword)) |
1948 | ? (i.types[j].bitfield.xmmword | |
1949 | || i.types[j].bitfield.ymmword | |
1950 | || i.types[j].bitfield.zmmword) | |
1951 | : !match_simd_size(t, j)))); | |
5c07affc L |
1952 | } |
1953 | ||
1954 | /* Return 1 if there is no size conflict on any operands for | |
1955 | instruction template T. */ | |
1956 | ||
1957 | static INLINE int | |
d3ce72d0 | 1958 | operand_size_match (const insn_template *t) |
5c07affc L |
1959 | { |
1960 | unsigned int j; | |
1961 | int match = 1; | |
1962 | ||
1963 | /* Don't check jump instructions. */ | |
1964 | if (t->opcode_modifier.jump | |
1965 | || t->opcode_modifier.jumpbyte | |
1966 | || t->opcode_modifier.jumpdword | |
1967 | || t->opcode_modifier.jumpintersegment) | |
1968 | return match; | |
1969 | ||
1970 | /* Check memory and accumulator operand size. */ | |
1971 | for (j = 0; j < i.operands; j++) | |
1972 | { | |
1b54b8d7 JB |
1973 | if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd |
1974 | && t->operand_types[j].bitfield.anysize) | |
5c07affc L |
1975 | continue; |
1976 | ||
1b54b8d7 | 1977 | if (t->operand_types[j].bitfield.reg |
dc821c5f | 1978 | && !match_reg_size (t, j)) |
5c07affc L |
1979 | { |
1980 | match = 0; | |
1981 | break; | |
1982 | } | |
1983 | ||
1b54b8d7 JB |
1984 | if (t->operand_types[j].bitfield.regsimd |
1985 | && !match_simd_size (t, j)) | |
1986 | { | |
1987 | match = 0; | |
1988 | break; | |
1989 | } | |
1990 | ||
1991 | if (t->operand_types[j].bitfield.acc | |
1992 | && (!match_reg_size (t, j) || !match_simd_size (t, j))) | |
1993 | { | |
1994 | match = 0; | |
1995 | break; | |
1996 | } | |
1997 | ||
5c07affc L |
1998 | if (i.types[j].bitfield.mem && !match_mem_size (t, j)) |
1999 | { | |
2000 | match = 0; | |
2001 | break; | |
2002 | } | |
2003 | } | |
2004 | ||
891edac4 | 2005 | if (match) |
5c07affc | 2006 | return match; |
38e314eb | 2007 | else if (!t->opcode_modifier.d) |
891edac4 L |
2008 | { |
2009 | mismatch: | |
86e026a4 | 2010 | i.error = operand_size_mismatch; |
891edac4 L |
2011 | return 0; |
2012 | } | |
5c07affc L |
2013 | |
2014 | /* Check reverse. */ | |
9c2799c2 | 2015 | gas_assert (i.operands == 2); |
5c07affc L |
2016 | |
2017 | match = 1; | |
2018 | for (j = 0; j < 2; j++) | |
2019 | { | |
dc821c5f JB |
2020 | if ((t->operand_types[j].bitfield.reg |
2021 | || t->operand_types[j].bitfield.acc) | |
5c07affc | 2022 | && !match_reg_size (t, j ? 0 : 1)) |
891edac4 | 2023 | goto mismatch; |
5c07affc L |
2024 | |
2025 | if (i.types[j].bitfield.mem | |
2026 | && !match_mem_size (t, j ? 0 : 1)) | |
891edac4 | 2027 | goto mismatch; |
5c07affc L |
2028 | } |
2029 | ||
2030 | return match; | |
2031 | } | |
2032 | ||
c6fb90c8 | 2033 | static INLINE int |
40fb9820 L |
2034 | operand_type_match (i386_operand_type overlap, |
2035 | i386_operand_type given) | |
2036 | { | |
2037 | i386_operand_type temp = overlap; | |
2038 | ||
2039 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 2040 | temp.bitfield.unspecified = 0; |
5c07affc L |
2041 | temp.bitfield.byte = 0; |
2042 | temp.bitfield.word = 0; | |
2043 | temp.bitfield.dword = 0; | |
2044 | temp.bitfield.fword = 0; | |
2045 | temp.bitfield.qword = 0; | |
2046 | temp.bitfield.tbyte = 0; | |
2047 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2048 | temp.bitfield.ymmword = 0; |
43234a1e | 2049 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 2050 | if (operand_type_all_zero (&temp)) |
891edac4 | 2051 | goto mismatch; |
40fb9820 | 2052 | |
891edac4 L |
2053 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
2054 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) | |
2055 | return 1; | |
2056 | ||
2057 | mismatch: | |
a65babc9 | 2058 | i.error = operand_type_mismatch; |
891edac4 | 2059 | return 0; |
40fb9820 L |
2060 | } |
2061 | ||
7d5e4556 | 2062 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd JB |
2063 | unless the expected operand type register overlap is null. |
2064 | Memory operand size of certain SIMD instructions is also being checked | |
2065 | here. */ | |
40fb9820 | 2066 | |
c6fb90c8 | 2067 | static INLINE int |
dc821c5f | 2068 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2069 | i386_operand_type t0, |
40fb9820 L |
2070 | i386_operand_type g1, |
2071 | i386_operand_type t1) | |
2072 | { | |
10c17abd JB |
2073 | if (!g0.bitfield.reg |
2074 | && !g0.bitfield.regsimd | |
2075 | && (!operand_type_check (g0, anymem) | |
2076 | || g0.bitfield.unspecified | |
2077 | || !t0.bitfield.regsimd)) | |
40fb9820 L |
2078 | return 1; |
2079 | ||
10c17abd JB |
2080 | if (!g1.bitfield.reg |
2081 | && !g1.bitfield.regsimd | |
2082 | && (!operand_type_check (g1, anymem) | |
2083 | || g1.bitfield.unspecified | |
2084 | || !t1.bitfield.regsimd)) | |
40fb9820 L |
2085 | return 1; |
2086 | ||
dc821c5f JB |
2087 | if (g0.bitfield.byte == g1.bitfield.byte |
2088 | && g0.bitfield.word == g1.bitfield.word | |
2089 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2090 | && g0.bitfield.qword == g1.bitfield.qword |
2091 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2092 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2093 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2094 | return 1; |
2095 | ||
dc821c5f JB |
2096 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2097 | && !(t0.bitfield.word & t1.bitfield.word) | |
2098 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2099 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2100 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2101 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2102 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2103 | return 1; |
2104 | ||
a65babc9 | 2105 | i.error = register_type_mismatch; |
891edac4 L |
2106 | |
2107 | return 0; | |
40fb9820 L |
2108 | } |
2109 | ||
4c692bc7 JB |
2110 | static INLINE unsigned int |
2111 | register_number (const reg_entry *r) | |
2112 | { | |
2113 | unsigned int nr = r->reg_num; | |
2114 | ||
2115 | if (r->reg_flags & RegRex) | |
2116 | nr += 8; | |
2117 | ||
200cbe0f L |
2118 | if (r->reg_flags & RegVRex) |
2119 | nr += 16; | |
2120 | ||
4c692bc7 JB |
2121 | return nr; |
2122 | } | |
2123 | ||
252b5132 | 2124 | static INLINE unsigned int |
40fb9820 | 2125 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2126 | { |
b5014f7a | 2127 | if (t.bitfield.disp8) |
40fb9820 L |
2128 | return 1; |
2129 | else if (t.bitfield.disp16 | |
2130 | || t.bitfield.disp32 | |
2131 | || t.bitfield.disp32s) | |
2132 | return 2; | |
2133 | else | |
2134 | return 0; | |
252b5132 RH |
2135 | } |
2136 | ||
2137 | static INLINE int | |
65879393 | 2138 | fits_in_signed_byte (addressT num) |
252b5132 | 2139 | { |
65879393 | 2140 | return num + 0x80 <= 0xff; |
47926f60 | 2141 | } |
252b5132 RH |
2142 | |
2143 | static INLINE int | |
65879393 | 2144 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2145 | { |
65879393 | 2146 | return num <= 0xff; |
47926f60 | 2147 | } |
252b5132 RH |
2148 | |
2149 | static INLINE int | |
65879393 | 2150 | fits_in_unsigned_word (addressT num) |
252b5132 | 2151 | { |
65879393 | 2152 | return num <= 0xffff; |
47926f60 | 2153 | } |
252b5132 RH |
2154 | |
2155 | static INLINE int | |
65879393 | 2156 | fits_in_signed_word (addressT num) |
252b5132 | 2157 | { |
65879393 | 2158 | return num + 0x8000 <= 0xffff; |
47926f60 | 2159 | } |
2a962e6d | 2160 | |
3e73aa7c | 2161 | static INLINE int |
65879393 | 2162 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2163 | { |
2164 | #ifndef BFD64 | |
2165 | return 1; | |
2166 | #else | |
65879393 | 2167 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2168 | #endif |
2169 | } /* fits_in_signed_long() */ | |
2a962e6d | 2170 | |
3e73aa7c | 2171 | static INLINE int |
65879393 | 2172 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2173 | { |
2174 | #ifndef BFD64 | |
2175 | return 1; | |
2176 | #else | |
65879393 | 2177 | return num <= 0xffffffff; |
3e73aa7c JH |
2178 | #endif |
2179 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2180 | |
43234a1e | 2181 | static INLINE int |
b5014f7a | 2182 | fits_in_disp8 (offsetT num) |
43234a1e L |
2183 | { |
2184 | int shift = i.memshift; | |
2185 | unsigned int mask; | |
2186 | ||
2187 | if (shift == -1) | |
2188 | abort (); | |
2189 | ||
2190 | mask = (1 << shift) - 1; | |
2191 | ||
2192 | /* Return 0 if NUM isn't properly aligned. */ | |
2193 | if ((num & mask)) | |
2194 | return 0; | |
2195 | ||
2196 | /* Check if NUM will fit in 8bit after shift. */ | |
2197 | return fits_in_signed_byte (num >> shift); | |
2198 | } | |
2199 | ||
a683cc34 SP |
2200 | static INLINE int |
2201 | fits_in_imm4 (offsetT num) | |
2202 | { | |
2203 | return (num & 0xf) == num; | |
2204 | } | |
2205 | ||
40fb9820 | 2206 | static i386_operand_type |
e3bb37b5 | 2207 | smallest_imm_type (offsetT num) |
252b5132 | 2208 | { |
40fb9820 | 2209 | i386_operand_type t; |
7ab9ffdd | 2210 | |
0dfbf9d7 | 2211 | operand_type_set (&t, 0); |
40fb9820 L |
2212 | t.bitfield.imm64 = 1; |
2213 | ||
2214 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2215 | { |
2216 | /* This code is disabled on the 486 because all the Imm1 forms | |
2217 | in the opcode table are slower on the i486. They're the | |
2218 | versions with the implicitly specified single-position | |
2219 | displacement, which has another syntax if you really want to | |
2220 | use that form. */ | |
40fb9820 L |
2221 | t.bitfield.imm1 = 1; |
2222 | t.bitfield.imm8 = 1; | |
2223 | t.bitfield.imm8s = 1; | |
2224 | t.bitfield.imm16 = 1; | |
2225 | t.bitfield.imm32 = 1; | |
2226 | t.bitfield.imm32s = 1; | |
2227 | } | |
2228 | else if (fits_in_signed_byte (num)) | |
2229 | { | |
2230 | t.bitfield.imm8 = 1; | |
2231 | t.bitfield.imm8s = 1; | |
2232 | t.bitfield.imm16 = 1; | |
2233 | t.bitfield.imm32 = 1; | |
2234 | t.bitfield.imm32s = 1; | |
2235 | } | |
2236 | else if (fits_in_unsigned_byte (num)) | |
2237 | { | |
2238 | t.bitfield.imm8 = 1; | |
2239 | t.bitfield.imm16 = 1; | |
2240 | t.bitfield.imm32 = 1; | |
2241 | t.bitfield.imm32s = 1; | |
2242 | } | |
2243 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2244 | { | |
2245 | t.bitfield.imm16 = 1; | |
2246 | t.bitfield.imm32 = 1; | |
2247 | t.bitfield.imm32s = 1; | |
2248 | } | |
2249 | else if (fits_in_signed_long (num)) | |
2250 | { | |
2251 | t.bitfield.imm32 = 1; | |
2252 | t.bitfield.imm32s = 1; | |
2253 | } | |
2254 | else if (fits_in_unsigned_long (num)) | |
2255 | t.bitfield.imm32 = 1; | |
2256 | ||
2257 | return t; | |
47926f60 | 2258 | } |
252b5132 | 2259 | |
847f7ad4 | 2260 | static offsetT |
e3bb37b5 | 2261 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2262 | { |
508866be | 2263 | addressT mask; |
ba2adb93 | 2264 | |
847f7ad4 AM |
2265 | switch (size) |
2266 | { | |
508866be L |
2267 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2268 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2269 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2270 | #ifdef BFD64 |
2271 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2272 | #endif | |
47926f60 | 2273 | default: abort (); |
847f7ad4 AM |
2274 | } |
2275 | ||
9de868bf L |
2276 | #ifdef BFD64 |
2277 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2278 | if (flag_code != CODE_64BIT | |
2279 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2280 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2281 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2282 | #endif |
ba2adb93 | 2283 | |
47926f60 | 2284 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2285 | { |
2286 | char buf1[40], buf2[40]; | |
2287 | ||
2288 | sprint_value (buf1, val); | |
2289 | sprint_value (buf2, val & mask); | |
2290 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2291 | } | |
2292 | return val & mask; | |
2293 | } | |
2294 | ||
c32fa91d L |
2295 | enum PREFIX_GROUP |
2296 | { | |
2297 | PREFIX_EXIST = 0, | |
2298 | PREFIX_LOCK, | |
2299 | PREFIX_REP, | |
04ef582a | 2300 | PREFIX_DS, |
c32fa91d L |
2301 | PREFIX_OTHER |
2302 | }; | |
2303 | ||
2304 | /* Returns | |
2305 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2306 | same class already exists. | |
2307 | b. PREFIX_LOCK if lock prefix is added. | |
2308 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2309 | d. PREFIX_DS if ds prefix is added. |
2310 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2311 | */ |
2312 | ||
2313 | static enum PREFIX_GROUP | |
e3bb37b5 | 2314 | add_prefix (unsigned int prefix) |
252b5132 | 2315 | { |
c32fa91d | 2316 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2317 | unsigned int q; |
252b5132 | 2318 | |
29b0f896 AM |
2319 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2320 | && flag_code == CODE_64BIT) | |
b1905489 | 2321 | { |
161a04f6 L |
2322 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
2323 | || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) | |
2324 | && (prefix & (REX_R | REX_X | REX_B)))) | |
c32fa91d | 2325 | ret = PREFIX_EXIST; |
b1905489 JB |
2326 | q = REX_PREFIX; |
2327 | } | |
3e73aa7c | 2328 | else |
b1905489 JB |
2329 | { |
2330 | switch (prefix) | |
2331 | { | |
2332 | default: | |
2333 | abort (); | |
2334 | ||
b1905489 | 2335 | case DS_PREFIX_OPCODE: |
04ef582a L |
2336 | ret = PREFIX_DS; |
2337 | /* Fall through. */ | |
2338 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2339 | case ES_PREFIX_OPCODE: |
2340 | case FS_PREFIX_OPCODE: | |
2341 | case GS_PREFIX_OPCODE: | |
2342 | case SS_PREFIX_OPCODE: | |
2343 | q = SEG_PREFIX; | |
2344 | break; | |
2345 | ||
2346 | case REPNE_PREFIX_OPCODE: | |
2347 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2348 | q = REP_PREFIX; |
2349 | ret = PREFIX_REP; | |
2350 | break; | |
2351 | ||
b1905489 | 2352 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2353 | q = LOCK_PREFIX; |
2354 | ret = PREFIX_LOCK; | |
b1905489 JB |
2355 | break; |
2356 | ||
2357 | case FWAIT_OPCODE: | |
2358 | q = WAIT_PREFIX; | |
2359 | break; | |
2360 | ||
2361 | case ADDR_PREFIX_OPCODE: | |
2362 | q = ADDR_PREFIX; | |
2363 | break; | |
2364 | ||
2365 | case DATA_PREFIX_OPCODE: | |
2366 | q = DATA_PREFIX; | |
2367 | break; | |
2368 | } | |
2369 | if (i.prefix[q] != 0) | |
c32fa91d | 2370 | ret = PREFIX_EXIST; |
b1905489 | 2371 | } |
252b5132 | 2372 | |
b1905489 | 2373 | if (ret) |
252b5132 | 2374 | { |
b1905489 JB |
2375 | if (!i.prefix[q]) |
2376 | ++i.prefixes; | |
2377 | i.prefix[q] |= prefix; | |
252b5132 | 2378 | } |
b1905489 JB |
2379 | else |
2380 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2381 | |
252b5132 RH |
2382 | return ret; |
2383 | } | |
2384 | ||
2385 | static void | |
78f12dd3 | 2386 | update_code_flag (int value, int check) |
eecb386c | 2387 | { |
78f12dd3 L |
2388 | PRINTF_LIKE ((*as_error)); |
2389 | ||
1e9cc1c2 | 2390 | flag_code = (enum flag_code) value; |
40fb9820 L |
2391 | if (flag_code == CODE_64BIT) |
2392 | { | |
2393 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2394 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2395 | } |
2396 | else | |
2397 | { | |
2398 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2399 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2400 | } |
2401 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2402 | { |
78f12dd3 L |
2403 | if (check) |
2404 | as_error = as_fatal; | |
2405 | else | |
2406 | as_error = as_bad; | |
2407 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2408 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2409 | } |
40fb9820 | 2410 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2411 | { |
78f12dd3 L |
2412 | if (check) |
2413 | as_error = as_fatal; | |
2414 | else | |
2415 | as_error = as_bad; | |
2416 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2417 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2418 | } |
eecb386c AM |
2419 | stackop_size = '\0'; |
2420 | } | |
2421 | ||
78f12dd3 L |
2422 | static void |
2423 | set_code_flag (int value) | |
2424 | { | |
2425 | update_code_flag (value, 0); | |
2426 | } | |
2427 | ||
eecb386c | 2428 | static void |
e3bb37b5 | 2429 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2430 | { |
1e9cc1c2 | 2431 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2432 | if (flag_code != CODE_16BIT) |
2433 | abort (); | |
2434 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2435 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2436 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2437 | } |
2438 | ||
2439 | static void | |
e3bb37b5 | 2440 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2441 | { |
2442 | /* Find out if register prefixing is specified. */ | |
2443 | int ask_naked_reg = 0; | |
2444 | ||
2445 | SKIP_WHITESPACE (); | |
29b0f896 | 2446 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2447 | { |
d02603dc NC |
2448 | char *string; |
2449 | int e = get_symbol_name (&string); | |
252b5132 | 2450 | |
47926f60 | 2451 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2452 | ask_naked_reg = 1; |
47926f60 | 2453 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2454 | ask_naked_reg = -1; |
2455 | else | |
d0b47220 | 2456 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2457 | (void) restore_line_pointer (e); |
252b5132 RH |
2458 | } |
2459 | demand_empty_rest_of_line (); | |
c3332e24 | 2460 | |
252b5132 RH |
2461 | intel_syntax = syntax_flag; |
2462 | ||
2463 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2464 | allow_naked_reg = (intel_syntax |
2465 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2466 | else |
2467 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2468 | |
ee86248c | 2469 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2470 | |
e4a3b5a4 | 2471 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2472 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2473 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2474 | } |
2475 | ||
1efbbeb4 L |
2476 | static void |
2477 | set_intel_mnemonic (int mnemonic_flag) | |
2478 | { | |
e1d4d893 | 2479 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2480 | } |
2481 | ||
db51cc60 L |
2482 | static void |
2483 | set_allow_index_reg (int flag) | |
2484 | { | |
2485 | allow_index_reg = flag; | |
2486 | } | |
2487 | ||
cb19c032 | 2488 | static void |
7bab8ab5 | 2489 | set_check (int what) |
cb19c032 | 2490 | { |
7bab8ab5 JB |
2491 | enum check_kind *kind; |
2492 | const char *str; | |
2493 | ||
2494 | if (what) | |
2495 | { | |
2496 | kind = &operand_check; | |
2497 | str = "operand"; | |
2498 | } | |
2499 | else | |
2500 | { | |
2501 | kind = &sse_check; | |
2502 | str = "sse"; | |
2503 | } | |
2504 | ||
cb19c032 L |
2505 | SKIP_WHITESPACE (); |
2506 | ||
2507 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2508 | { | |
d02603dc NC |
2509 | char *string; |
2510 | int e = get_symbol_name (&string); | |
cb19c032 L |
2511 | |
2512 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2513 | *kind = check_none; |
cb19c032 | 2514 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2515 | *kind = check_warning; |
cb19c032 | 2516 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2517 | *kind = check_error; |
cb19c032 | 2518 | else |
7bab8ab5 | 2519 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2520 | (void) restore_line_pointer (e); |
cb19c032 L |
2521 | } |
2522 | else | |
7bab8ab5 | 2523 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2524 | |
2525 | demand_empty_rest_of_line (); | |
2526 | } | |
2527 | ||
8a9036a4 L |
2528 | static void |
2529 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2530 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2531 | { |
2532 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2533 | static const char *arch; | |
2534 | ||
2535 | /* Intel LIOM is only supported on ELF. */ | |
2536 | if (!IS_ELF) | |
2537 | return; | |
2538 | ||
2539 | if (!arch) | |
2540 | { | |
2541 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2542 | use default_arch. */ | |
2543 | arch = cpu_arch_name; | |
2544 | if (!arch) | |
2545 | arch = default_arch; | |
2546 | } | |
2547 | ||
81486035 L |
2548 | /* If we are targeting Intel MCU, we must enable it. */ |
2549 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2550 | || new_flag.bitfield.cpuiamcu) | |
2551 | return; | |
2552 | ||
3632d14b | 2553 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2554 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2555 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2556 | return; |
76ba9986 | 2557 | |
7a9068fe L |
2558 | /* If we are targeting Intel K1OM, we must enable it. */ |
2559 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2560 | || new_flag.bitfield.cpuk1om) | |
2561 | return; | |
2562 | ||
8a9036a4 L |
2563 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2564 | #endif | |
2565 | } | |
2566 | ||
e413e4e9 | 2567 | static void |
e3bb37b5 | 2568 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2569 | { |
47926f60 | 2570 | SKIP_WHITESPACE (); |
e413e4e9 | 2571 | |
29b0f896 | 2572 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2573 | { |
d02603dc NC |
2574 | char *string; |
2575 | int e = get_symbol_name (&string); | |
91d6fa6a | 2576 | unsigned int j; |
40fb9820 | 2577 | i386_cpu_flags flags; |
e413e4e9 | 2578 | |
91d6fa6a | 2579 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2580 | { |
91d6fa6a | 2581 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2582 | { |
91d6fa6a | 2583 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2584 | |
5c6af06e JB |
2585 | if (*string != '.') |
2586 | { | |
91d6fa6a | 2587 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2588 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2589 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2590 | if (flag_code == CODE_64BIT) |
2591 | { | |
2592 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2593 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2594 | } | |
2595 | else | |
2596 | { | |
2597 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2598 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2599 | } | |
91d6fa6a NC |
2600 | cpu_arch_isa = cpu_arch[j].type; |
2601 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2602 | if (!cpu_arch_tune_set) |
2603 | { | |
2604 | cpu_arch_tune = cpu_arch_isa; | |
2605 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2606 | } | |
5c6af06e JB |
2607 | break; |
2608 | } | |
40fb9820 | 2609 | |
293f5f65 L |
2610 | flags = cpu_flags_or (cpu_arch_flags, |
2611 | cpu_arch[j].flags); | |
81486035 | 2612 | |
5b64d091 | 2613 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2614 | { |
6305a203 L |
2615 | if (cpu_sub_arch_name) |
2616 | { | |
2617 | char *name = cpu_sub_arch_name; | |
2618 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2619 | cpu_arch[j].name, |
1bf57e9f | 2620 | (const char *) NULL); |
6305a203 L |
2621 | free (name); |
2622 | } | |
2623 | else | |
91d6fa6a | 2624 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2625 | cpu_arch_flags = flags; |
a586129e | 2626 | cpu_arch_isa_flags = flags; |
5c6af06e | 2627 | } |
0089dace L |
2628 | else |
2629 | cpu_arch_isa_flags | |
2630 | = cpu_flags_or (cpu_arch_isa_flags, | |
2631 | cpu_arch[j].flags); | |
d02603dc | 2632 | (void) restore_line_pointer (e); |
5c6af06e JB |
2633 | demand_empty_rest_of_line (); |
2634 | return; | |
e413e4e9 AM |
2635 | } |
2636 | } | |
293f5f65 L |
2637 | |
2638 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2639 | { | |
33eaf5de | 2640 | /* Disable an ISA extension. */ |
293f5f65 L |
2641 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2642 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2643 | { | |
2644 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2645 | cpu_noarch[j].flags); | |
2646 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2647 | { | |
2648 | if (cpu_sub_arch_name) | |
2649 | { | |
2650 | char *name = cpu_sub_arch_name; | |
2651 | cpu_sub_arch_name = concat (name, string, | |
2652 | (const char *) NULL); | |
2653 | free (name); | |
2654 | } | |
2655 | else | |
2656 | cpu_sub_arch_name = xstrdup (string); | |
2657 | cpu_arch_flags = flags; | |
2658 | cpu_arch_isa_flags = flags; | |
2659 | } | |
2660 | (void) restore_line_pointer (e); | |
2661 | demand_empty_rest_of_line (); | |
2662 | return; | |
2663 | } | |
2664 | ||
2665 | j = ARRAY_SIZE (cpu_arch); | |
2666 | } | |
2667 | ||
91d6fa6a | 2668 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2669 | as_bad (_("no such architecture: `%s'"), string); |
2670 | ||
2671 | *input_line_pointer = e; | |
2672 | } | |
2673 | else | |
2674 | as_bad (_("missing cpu architecture")); | |
2675 | ||
fddf5b5b AM |
2676 | no_cond_jump_promotion = 0; |
2677 | if (*input_line_pointer == ',' | |
29b0f896 | 2678 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2679 | { |
d02603dc NC |
2680 | char *string; |
2681 | char e; | |
2682 | ||
2683 | ++input_line_pointer; | |
2684 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2685 | |
2686 | if (strcmp (string, "nojumps") == 0) | |
2687 | no_cond_jump_promotion = 1; | |
2688 | else if (strcmp (string, "jumps") == 0) | |
2689 | ; | |
2690 | else | |
2691 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2692 | ||
d02603dc | 2693 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2694 | } |
2695 | ||
e413e4e9 AM |
2696 | demand_empty_rest_of_line (); |
2697 | } | |
2698 | ||
8a9036a4 L |
2699 | enum bfd_architecture |
2700 | i386_arch (void) | |
2701 | { | |
3632d14b | 2702 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2703 | { |
2704 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2705 | || flag_code != CODE_64BIT) | |
2706 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2707 | return bfd_arch_l1om; | |
2708 | } | |
7a9068fe L |
2709 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2710 | { | |
2711 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2712 | || flag_code != CODE_64BIT) | |
2713 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2714 | return bfd_arch_k1om; | |
2715 | } | |
81486035 L |
2716 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2717 | { | |
2718 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2719 | || flag_code == CODE_64BIT) | |
2720 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2721 | return bfd_arch_iamcu; | |
2722 | } | |
8a9036a4 L |
2723 | else |
2724 | return bfd_arch_i386; | |
2725 | } | |
2726 | ||
b9d79e03 | 2727 | unsigned long |
7016a5d5 | 2728 | i386_mach (void) |
b9d79e03 | 2729 | { |
351f65ca | 2730 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2731 | { |
3632d14b | 2732 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2733 | { |
351f65ca L |
2734 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2735 | || default_arch[6] != '\0') | |
8a9036a4 L |
2736 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2737 | return bfd_mach_l1om; | |
2738 | } | |
7a9068fe L |
2739 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2740 | { | |
2741 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2742 | || default_arch[6] != '\0') | |
2743 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2744 | return bfd_mach_k1om; | |
2745 | } | |
351f65ca | 2746 | else if (default_arch[6] == '\0') |
8a9036a4 | 2747 | return bfd_mach_x86_64; |
351f65ca L |
2748 | else |
2749 | return bfd_mach_x64_32; | |
8a9036a4 | 2750 | } |
5197d474 L |
2751 | else if (!strcmp (default_arch, "i386") |
2752 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2753 | { |
2754 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2755 | { | |
2756 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2757 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2758 | return bfd_mach_i386_iamcu; | |
2759 | } | |
2760 | else | |
2761 | return bfd_mach_i386_i386; | |
2762 | } | |
b9d79e03 | 2763 | else |
2b5d6a91 | 2764 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2765 | } |
b9d79e03 | 2766 | \f |
252b5132 | 2767 | void |
7016a5d5 | 2768 | md_begin (void) |
252b5132 RH |
2769 | { |
2770 | const char *hash_err; | |
2771 | ||
86fa6981 L |
2772 | /* Support pseudo prefixes like {disp32}. */ |
2773 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2774 | ||
47926f60 | 2775 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2776 | op_hash = hash_new (); |
2777 | ||
2778 | { | |
d3ce72d0 | 2779 | const insn_template *optab; |
29b0f896 | 2780 | templates *core_optab; |
252b5132 | 2781 | |
47926f60 KH |
2782 | /* Setup for loop. */ |
2783 | optab = i386_optab; | |
add39d23 | 2784 | core_optab = XNEW (templates); |
252b5132 RH |
2785 | core_optab->start = optab; |
2786 | ||
2787 | while (1) | |
2788 | { | |
2789 | ++optab; | |
2790 | if (optab->name == NULL | |
2791 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2792 | { | |
2793 | /* different name --> ship out current template list; | |
47926f60 | 2794 | add to hash table; & begin anew. */ |
252b5132 RH |
2795 | core_optab->end = optab; |
2796 | hash_err = hash_insert (op_hash, | |
2797 | (optab - 1)->name, | |
5a49b8ac | 2798 | (void *) core_optab); |
252b5132 RH |
2799 | if (hash_err) |
2800 | { | |
b37df7c4 | 2801 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
2802 | (optab - 1)->name, |
2803 | hash_err); | |
2804 | } | |
2805 | if (optab->name == NULL) | |
2806 | break; | |
add39d23 | 2807 | core_optab = XNEW (templates); |
252b5132 RH |
2808 | core_optab->start = optab; |
2809 | } | |
2810 | } | |
2811 | } | |
2812 | ||
47926f60 | 2813 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2814 | reg_hash = hash_new (); |
2815 | { | |
29b0f896 | 2816 | const reg_entry *regtab; |
c3fe08fa | 2817 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2818 | |
c3fe08fa | 2819 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2820 | { |
5a49b8ac | 2821 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2822 | if (hash_err) |
b37df7c4 | 2823 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
2824 | regtab->reg_name, |
2825 | hash_err); | |
252b5132 RH |
2826 | } |
2827 | } | |
2828 | ||
47926f60 | 2829 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2830 | { |
29b0f896 AM |
2831 | int c; |
2832 | char *p; | |
252b5132 RH |
2833 | |
2834 | for (c = 0; c < 256; c++) | |
2835 | { | |
3882b010 | 2836 | if (ISDIGIT (c)) |
252b5132 RH |
2837 | { |
2838 | digit_chars[c] = c; | |
2839 | mnemonic_chars[c] = c; | |
2840 | register_chars[c] = c; | |
2841 | operand_chars[c] = c; | |
2842 | } | |
3882b010 | 2843 | else if (ISLOWER (c)) |
252b5132 RH |
2844 | { |
2845 | mnemonic_chars[c] = c; | |
2846 | register_chars[c] = c; | |
2847 | operand_chars[c] = c; | |
2848 | } | |
3882b010 | 2849 | else if (ISUPPER (c)) |
252b5132 | 2850 | { |
3882b010 | 2851 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2852 | register_chars[c] = mnemonic_chars[c]; |
2853 | operand_chars[c] = c; | |
2854 | } | |
43234a1e | 2855 | else if (c == '{' || c == '}') |
86fa6981 L |
2856 | { |
2857 | mnemonic_chars[c] = c; | |
2858 | operand_chars[c] = c; | |
2859 | } | |
252b5132 | 2860 | |
3882b010 | 2861 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2862 | identifier_chars[c] = c; |
2863 | else if (c >= 128) | |
2864 | { | |
2865 | identifier_chars[c] = c; | |
2866 | operand_chars[c] = c; | |
2867 | } | |
2868 | } | |
2869 | ||
2870 | #ifdef LEX_AT | |
2871 | identifier_chars['@'] = '@'; | |
32137342 NC |
2872 | #endif |
2873 | #ifdef LEX_QM | |
2874 | identifier_chars['?'] = '?'; | |
2875 | operand_chars['?'] = '?'; | |
252b5132 | 2876 | #endif |
252b5132 | 2877 | digit_chars['-'] = '-'; |
c0f3af97 | 2878 | mnemonic_chars['_'] = '_'; |
791fe849 | 2879 | mnemonic_chars['-'] = '-'; |
0003779b | 2880 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2881 | identifier_chars['_'] = '_'; |
2882 | identifier_chars['.'] = '.'; | |
2883 | ||
2884 | for (p = operand_special_chars; *p != '\0'; p++) | |
2885 | operand_chars[(unsigned char) *p] = *p; | |
2886 | } | |
2887 | ||
a4447b93 RH |
2888 | if (flag_code == CODE_64BIT) |
2889 | { | |
ca19b261 KT |
2890 | #if defined (OBJ_COFF) && defined (TE_PE) |
2891 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
2892 | ? 32 : 16); | |
2893 | #else | |
a4447b93 | 2894 | x86_dwarf2_return_column = 16; |
ca19b261 | 2895 | #endif |
61ff971f | 2896 | x86_cie_data_alignment = -8; |
a4447b93 RH |
2897 | } |
2898 | else | |
2899 | { | |
2900 | x86_dwarf2_return_column = 8; | |
2901 | x86_cie_data_alignment = -4; | |
2902 | } | |
252b5132 RH |
2903 | } |
2904 | ||
2905 | void | |
e3bb37b5 | 2906 | i386_print_statistics (FILE *file) |
252b5132 RH |
2907 | { |
2908 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2909 | hash_print_statistics (file, "i386 register", reg_hash); | |
2910 | } | |
2911 | \f | |
252b5132 RH |
2912 | #ifdef DEBUG386 |
2913 | ||
ce8a8b2f | 2914 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 2915 | static void pte (insn_template *); |
40fb9820 | 2916 | static void pt (i386_operand_type); |
e3bb37b5 L |
2917 | static void pe (expressionS *); |
2918 | static void ps (symbolS *); | |
252b5132 RH |
2919 | |
2920 | static void | |
e3bb37b5 | 2921 | pi (char *line, i386_insn *x) |
252b5132 | 2922 | { |
09137c09 | 2923 | unsigned int j; |
252b5132 RH |
2924 | |
2925 | fprintf (stdout, "%s: template ", line); | |
2926 | pte (&x->tm); | |
09f131f2 JH |
2927 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2928 | x->base_reg ? x->base_reg->reg_name : "none", | |
2929 | x->index_reg ? x->index_reg->reg_name : "none", | |
2930 | x->log2_scale_factor); | |
2931 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 2932 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
2933 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
2934 | x->sib.base, x->sib.index, x->sib.scale); | |
2935 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
2936 | (x->rex & REX_W) != 0, |
2937 | (x->rex & REX_R) != 0, | |
2938 | (x->rex & REX_X) != 0, | |
2939 | (x->rex & REX_B) != 0); | |
09137c09 | 2940 | for (j = 0; j < x->operands; j++) |
252b5132 | 2941 | { |
09137c09 SP |
2942 | fprintf (stdout, " #%d: ", j + 1); |
2943 | pt (x->types[j]); | |
252b5132 | 2944 | fprintf (stdout, "\n"); |
dc821c5f | 2945 | if (x->types[j].bitfield.reg |
09137c09 | 2946 | || x->types[j].bitfield.regmmx |
1b54b8d7 | 2947 | || x->types[j].bitfield.regsimd |
09137c09 SP |
2948 | || x->types[j].bitfield.sreg2 |
2949 | || x->types[j].bitfield.sreg3 | |
2950 | || x->types[j].bitfield.control | |
2951 | || x->types[j].bitfield.debug | |
2952 | || x->types[j].bitfield.test) | |
2953 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); | |
2954 | if (operand_type_check (x->types[j], imm)) | |
2955 | pe (x->op[j].imms); | |
2956 | if (operand_type_check (x->types[j], disp)) | |
2957 | pe (x->op[j].disps); | |
252b5132 RH |
2958 | } |
2959 | } | |
2960 | ||
2961 | static void | |
d3ce72d0 | 2962 | pte (insn_template *t) |
252b5132 | 2963 | { |
09137c09 | 2964 | unsigned int j; |
252b5132 | 2965 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 2966 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
2967 | if (t->extension_opcode != None) |
2968 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 2969 | if (t->opcode_modifier.d) |
252b5132 | 2970 | fprintf (stdout, "D"); |
40fb9820 | 2971 | if (t->opcode_modifier.w) |
252b5132 RH |
2972 | fprintf (stdout, "W"); |
2973 | fprintf (stdout, "\n"); | |
09137c09 | 2974 | for (j = 0; j < t->operands; j++) |
252b5132 | 2975 | { |
09137c09 SP |
2976 | fprintf (stdout, " #%d type ", j + 1); |
2977 | pt (t->operand_types[j]); | |
252b5132 RH |
2978 | fprintf (stdout, "\n"); |
2979 | } | |
2980 | } | |
2981 | ||
2982 | static void | |
e3bb37b5 | 2983 | pe (expressionS *e) |
252b5132 | 2984 | { |
24eab124 | 2985 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
2986 | fprintf (stdout, " add_number %ld (%lx)\n", |
2987 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
2988 | if (e->X_add_symbol) |
2989 | { | |
2990 | fprintf (stdout, " add_symbol "); | |
2991 | ps (e->X_add_symbol); | |
2992 | fprintf (stdout, "\n"); | |
2993 | } | |
2994 | if (e->X_op_symbol) | |
2995 | { | |
2996 | fprintf (stdout, " op_symbol "); | |
2997 | ps (e->X_op_symbol); | |
2998 | fprintf (stdout, "\n"); | |
2999 | } | |
3000 | } | |
3001 | ||
3002 | static void | |
e3bb37b5 | 3003 | ps (symbolS *s) |
252b5132 RH |
3004 | { |
3005 | fprintf (stdout, "%s type %s%s", | |
3006 | S_GET_NAME (s), | |
3007 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3008 | segment_name (S_GET_SEGMENT (s))); | |
3009 | } | |
3010 | ||
7b81dfbb | 3011 | static struct type_name |
252b5132 | 3012 | { |
40fb9820 L |
3013 | i386_operand_type mask; |
3014 | const char *name; | |
252b5132 | 3015 | } |
7b81dfbb | 3016 | const type_names[] = |
252b5132 | 3017 | { |
40fb9820 L |
3018 | { OPERAND_TYPE_REG8, "r8" }, |
3019 | { OPERAND_TYPE_REG16, "r16" }, | |
3020 | { OPERAND_TYPE_REG32, "r32" }, | |
3021 | { OPERAND_TYPE_REG64, "r64" }, | |
3022 | { OPERAND_TYPE_IMM8, "i8" }, | |
3023 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3024 | { OPERAND_TYPE_IMM16, "i16" }, | |
3025 | { OPERAND_TYPE_IMM32, "i32" }, | |
3026 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3027 | { OPERAND_TYPE_IMM64, "i64" }, | |
3028 | { OPERAND_TYPE_IMM1, "i1" }, | |
3029 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3030 | { OPERAND_TYPE_DISP8, "d8" }, | |
3031 | { OPERAND_TYPE_DISP16, "d16" }, | |
3032 | { OPERAND_TYPE_DISP32, "d32" }, | |
3033 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3034 | { OPERAND_TYPE_DISP64, "d64" }, | |
3035 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3036 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3037 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3038 | { OPERAND_TYPE_TEST, "test reg" }, | |
3039 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3040 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3041 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
3042 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
3043 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
3044 | { OPERAND_TYPE_ACC, "Acc" }, | |
3045 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
3046 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
3047 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3048 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
3049 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
3050 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
40fb9820 | 3051 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
3052 | }; |
3053 | ||
3054 | static void | |
40fb9820 | 3055 | pt (i386_operand_type t) |
252b5132 | 3056 | { |
40fb9820 | 3057 | unsigned int j; |
c6fb90c8 | 3058 | i386_operand_type a; |
252b5132 | 3059 | |
40fb9820 | 3060 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3061 | { |
3062 | a = operand_type_and (t, type_names[j].mask); | |
0349dc08 | 3063 | if (!operand_type_all_zero (&a)) |
c6fb90c8 L |
3064 | fprintf (stdout, "%s, ", type_names[j].name); |
3065 | } | |
252b5132 RH |
3066 | fflush (stdout); |
3067 | } | |
3068 | ||
3069 | #endif /* DEBUG386 */ | |
3070 | \f | |
252b5132 | 3071 | static bfd_reloc_code_real_type |
3956db08 | 3072 | reloc (unsigned int size, |
64e74474 AM |
3073 | int pcrel, |
3074 | int sign, | |
3075 | bfd_reloc_code_real_type other) | |
252b5132 | 3076 | { |
47926f60 | 3077 | if (other != NO_RELOC) |
3956db08 | 3078 | { |
91d6fa6a | 3079 | reloc_howto_type *rel; |
3956db08 JB |
3080 | |
3081 | if (size == 8) | |
3082 | switch (other) | |
3083 | { | |
64e74474 AM |
3084 | case BFD_RELOC_X86_64_GOT32: |
3085 | return BFD_RELOC_X86_64_GOT64; | |
3086 | break; | |
553d1284 L |
3087 | case BFD_RELOC_X86_64_GOTPLT64: |
3088 | return BFD_RELOC_X86_64_GOTPLT64; | |
3089 | break; | |
64e74474 AM |
3090 | case BFD_RELOC_X86_64_PLTOFF64: |
3091 | return BFD_RELOC_X86_64_PLTOFF64; | |
3092 | break; | |
3093 | case BFD_RELOC_X86_64_GOTPC32: | |
3094 | other = BFD_RELOC_X86_64_GOTPC64; | |
3095 | break; | |
3096 | case BFD_RELOC_X86_64_GOTPCREL: | |
3097 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3098 | break; | |
3099 | case BFD_RELOC_X86_64_TPOFF32: | |
3100 | other = BFD_RELOC_X86_64_TPOFF64; | |
3101 | break; | |
3102 | case BFD_RELOC_X86_64_DTPOFF32: | |
3103 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3104 | break; | |
3105 | default: | |
3106 | break; | |
3956db08 | 3107 | } |
e05278af | 3108 | |
8ce3d284 | 3109 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3110 | if (other == BFD_RELOC_SIZE32) |
3111 | { | |
3112 | if (size == 8) | |
1ab668bf | 3113 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3114 | if (pcrel) |
1ab668bf AM |
3115 | { |
3116 | as_bad (_("there are no pc-relative size relocations")); | |
3117 | return NO_RELOC; | |
3118 | } | |
8fd4256d | 3119 | } |
8ce3d284 | 3120 | #endif |
8fd4256d | 3121 | |
e05278af | 3122 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3123 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3124 | sign = -1; |
3125 | ||
91d6fa6a NC |
3126 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3127 | if (!rel) | |
3956db08 | 3128 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3129 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3130 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3131 | bfd_get_reloc_size (rel), |
3956db08 | 3132 | size); |
91d6fa6a | 3133 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3134 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3135 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3136 | && !sign) |
91d6fa6a | 3137 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3138 | && sign > 0)) |
3956db08 JB |
3139 | as_bad (_("relocated field and relocation type differ in signedness")); |
3140 | else | |
3141 | return other; | |
3142 | return NO_RELOC; | |
3143 | } | |
252b5132 RH |
3144 | |
3145 | if (pcrel) | |
3146 | { | |
3e73aa7c | 3147 | if (!sign) |
3956db08 | 3148 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3149 | switch (size) |
3150 | { | |
3151 | case 1: return BFD_RELOC_8_PCREL; | |
3152 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3153 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3154 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3155 | } |
3956db08 | 3156 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3157 | } |
3158 | else | |
3159 | { | |
3956db08 | 3160 | if (sign > 0) |
e5cb08ac | 3161 | switch (size) |
3e73aa7c JH |
3162 | { |
3163 | case 4: return BFD_RELOC_X86_64_32S; | |
3164 | } | |
3165 | else | |
3166 | switch (size) | |
3167 | { | |
3168 | case 1: return BFD_RELOC_8; | |
3169 | case 2: return BFD_RELOC_16; | |
3170 | case 4: return BFD_RELOC_32; | |
3171 | case 8: return BFD_RELOC_64; | |
3172 | } | |
3956db08 JB |
3173 | as_bad (_("cannot do %s %u byte relocation"), |
3174 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3175 | } |
3176 | ||
0cc9e1d3 | 3177 | return NO_RELOC; |
252b5132 RH |
3178 | } |
3179 | ||
47926f60 KH |
3180 | /* Here we decide which fixups can be adjusted to make them relative to |
3181 | the beginning of the section instead of the symbol. Basically we need | |
3182 | to make sure that the dynamic relocations are done correctly, so in | |
3183 | some cases we force the original symbol to be used. */ | |
3184 | ||
252b5132 | 3185 | int |
e3bb37b5 | 3186 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3187 | { |
6d249963 | 3188 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3189 | if (!IS_ELF) |
31312f95 AM |
3190 | return 1; |
3191 | ||
a161fe53 AM |
3192 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3193 | mode. */ | |
3194 | if (use_rela_relocations | |
3195 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3196 | && fixP->fx_pcrel) | |
252b5132 | 3197 | return 0; |
31312f95 | 3198 | |
8d01d9a9 AJ |
3199 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3200 | and changed later by validate_fix. */ | |
3201 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3202 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3203 | return 0; | |
3204 | ||
8fd4256d L |
3205 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3206 | for size relocations. */ | |
3207 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3208 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3209 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 RH |
3210 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
3211 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
02a86693 | 3212 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3213 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3214 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3215 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3216 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3217 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3218 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3219 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3220 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3221 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3222 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
3223 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
3224 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 3225 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3226 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3227 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3228 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3229 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3230 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3231 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3232 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3233 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3234 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3235 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3236 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3237 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3238 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3239 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3240 | return 0; | |
31312f95 | 3241 | #endif |
252b5132 RH |
3242 | return 1; |
3243 | } | |
252b5132 | 3244 | |
b4cac588 | 3245 | static int |
e3bb37b5 | 3246 | intel_float_operand (const char *mnemonic) |
252b5132 | 3247 | { |
9306ca4a JB |
3248 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3249 | operands, hence the code here is free to improperly handle opcodes that | |
3250 | have no operands (for better performance and smaller code). */ | |
3251 | ||
3252 | if (mnemonic[0] != 'f') | |
3253 | return 0; /* non-math */ | |
3254 | ||
3255 | switch (mnemonic[1]) | |
3256 | { | |
3257 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3258 | the fs segment override prefix not currently handled because no | |
3259 | call path can make opcodes without operands get here */ | |
3260 | case 'i': | |
3261 | return 2 /* integer op */; | |
3262 | case 'l': | |
3263 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3264 | return 3; /* fldcw/fldenv */ | |
3265 | break; | |
3266 | case 'n': | |
3267 | if (mnemonic[2] != 'o' /* fnop */) | |
3268 | return 3; /* non-waiting control op */ | |
3269 | break; | |
3270 | case 'r': | |
3271 | if (mnemonic[2] == 's') | |
3272 | return 3; /* frstor/frstpm */ | |
3273 | break; | |
3274 | case 's': | |
3275 | if (mnemonic[2] == 'a') | |
3276 | return 3; /* fsave */ | |
3277 | if (mnemonic[2] == 't') | |
3278 | { | |
3279 | switch (mnemonic[3]) | |
3280 | { | |
3281 | case 'c': /* fstcw */ | |
3282 | case 'd': /* fstdw */ | |
3283 | case 'e': /* fstenv */ | |
3284 | case 's': /* fsts[gw] */ | |
3285 | return 3; | |
3286 | } | |
3287 | } | |
3288 | break; | |
3289 | case 'x': | |
3290 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3291 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3292 | break; | |
3293 | } | |
252b5132 | 3294 | |
9306ca4a | 3295 | return 1; |
252b5132 RH |
3296 | } |
3297 | ||
c0f3af97 L |
3298 | /* Build the VEX prefix. */ |
3299 | ||
3300 | static void | |
d3ce72d0 | 3301 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3302 | { |
3303 | unsigned int register_specifier; | |
3304 | unsigned int implied_prefix; | |
3305 | unsigned int vector_length; | |
3306 | ||
3307 | /* Check register specifier. */ | |
3308 | if (i.vex.register_specifier) | |
43234a1e L |
3309 | { |
3310 | register_specifier = | |
3311 | ~register_number (i.vex.register_specifier) & 0xf; | |
3312 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3313 | } | |
c0f3af97 L |
3314 | else |
3315 | register_specifier = 0xf; | |
3316 | ||
33eaf5de | 3317 | /* Use 2-byte VEX prefix by swapping destination and source |
fa99fab2 | 3318 | operand. */ |
86fa6981 L |
3319 | if (i.vec_encoding != vex_encoding_vex3 |
3320 | && i.dir_encoding == dir_encoding_default | |
fa99fab2 | 3321 | && i.operands == i.reg_operands |
7f399153 | 3322 | && i.tm.opcode_modifier.vexopcode == VEX0F |
86fa6981 | 3323 | && i.tm.opcode_modifier.load |
fa99fab2 L |
3324 | && i.rex == REX_B) |
3325 | { | |
3326 | unsigned int xchg = i.operands - 1; | |
3327 | union i386_op temp_op; | |
3328 | i386_operand_type temp_type; | |
3329 | ||
3330 | temp_type = i.types[xchg]; | |
3331 | i.types[xchg] = i.types[0]; | |
3332 | i.types[0] = temp_type; | |
3333 | temp_op = i.op[xchg]; | |
3334 | i.op[xchg] = i.op[0]; | |
3335 | i.op[0] = temp_op; | |
3336 | ||
9c2799c2 | 3337 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3338 | |
3339 | i.rex = REX_R; | |
3340 | xchg = i.rm.regmem; | |
3341 | i.rm.regmem = i.rm.reg; | |
3342 | i.rm.reg = xchg; | |
3343 | ||
3344 | /* Use the next insn. */ | |
3345 | i.tm = t[1]; | |
3346 | } | |
3347 | ||
539f890d L |
3348 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3349 | vector_length = avxscalar; | |
10c17abd JB |
3350 | else if (i.tm.opcode_modifier.vex == VEX256) |
3351 | vector_length = 1; | |
539f890d | 3352 | else |
10c17abd JB |
3353 | { |
3354 | unsigned int op; | |
3355 | ||
3356 | vector_length = 0; | |
3357 | for (op = 0; op < t->operands; ++op) | |
3358 | if (t->operand_types[op].bitfield.xmmword | |
3359 | && t->operand_types[op].bitfield.ymmword | |
3360 | && i.types[op].bitfield.ymmword) | |
3361 | { | |
3362 | vector_length = 1; | |
3363 | break; | |
3364 | } | |
3365 | } | |
c0f3af97 L |
3366 | |
3367 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3368 | { | |
3369 | case 0: | |
3370 | implied_prefix = 0; | |
3371 | break; | |
3372 | case DATA_PREFIX_OPCODE: | |
3373 | implied_prefix = 1; | |
3374 | break; | |
3375 | case REPE_PREFIX_OPCODE: | |
3376 | implied_prefix = 2; | |
3377 | break; | |
3378 | case REPNE_PREFIX_OPCODE: | |
3379 | implied_prefix = 3; | |
3380 | break; | |
3381 | default: | |
3382 | abort (); | |
3383 | } | |
3384 | ||
3385 | /* Use 2-byte VEX prefix if possible. */ | |
86fa6981 L |
3386 | if (i.vec_encoding != vex_encoding_vex3 |
3387 | && i.tm.opcode_modifier.vexopcode == VEX0F | |
04251de0 | 3388 | && i.tm.opcode_modifier.vexw != VEXW1 |
c0f3af97 L |
3389 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3390 | { | |
3391 | /* 2-byte VEX prefix. */ | |
3392 | unsigned int r; | |
3393 | ||
3394 | i.vex.length = 2; | |
3395 | i.vex.bytes[0] = 0xc5; | |
3396 | ||
3397 | /* Check the REX.R bit. */ | |
3398 | r = (i.rex & REX_R) ? 0 : 1; | |
3399 | i.vex.bytes[1] = (r << 7 | |
3400 | | register_specifier << 3 | |
3401 | | vector_length << 2 | |
3402 | | implied_prefix); | |
3403 | } | |
3404 | else | |
3405 | { | |
3406 | /* 3-byte VEX prefix. */ | |
3407 | unsigned int m, w; | |
3408 | ||
f88c9eb0 | 3409 | i.vex.length = 3; |
f88c9eb0 | 3410 | |
7f399153 | 3411 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3412 | { |
7f399153 L |
3413 | case VEX0F: |
3414 | m = 0x1; | |
80de6e00 | 3415 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3416 | break; |
3417 | case VEX0F38: | |
3418 | m = 0x2; | |
80de6e00 | 3419 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3420 | break; |
3421 | case VEX0F3A: | |
3422 | m = 0x3; | |
80de6e00 | 3423 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3424 | break; |
3425 | case XOP08: | |
5dd85c99 SP |
3426 | m = 0x8; |
3427 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3428 | break; |
3429 | case XOP09: | |
f88c9eb0 SP |
3430 | m = 0x9; |
3431 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3432 | break; |
3433 | case XOP0A: | |
f88c9eb0 SP |
3434 | m = 0xa; |
3435 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3436 | break; |
3437 | default: | |
3438 | abort (); | |
f88c9eb0 | 3439 | } |
c0f3af97 | 3440 | |
c0f3af97 L |
3441 | /* The high 3 bits of the second VEX byte are 1's compliment |
3442 | of RXB bits from REX. */ | |
3443 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3444 | ||
3445 | /* Check the REX.W bit. */ | |
3446 | w = (i.rex & REX_W) ? 1 : 0; | |
b28d1bda IT |
3447 | if (i.tm.opcode_modifier.vexw == VEXW1) |
3448 | w = 1; | |
c0f3af97 L |
3449 | |
3450 | i.vex.bytes[2] = (w << 7 | |
3451 | | register_specifier << 3 | |
3452 | | vector_length << 2 | |
3453 | | implied_prefix); | |
3454 | } | |
3455 | } | |
3456 | ||
e771e7c9 JB |
3457 | static INLINE bfd_boolean |
3458 | is_evex_encoding (const insn_template *t) | |
3459 | { | |
3460 | return t->opcode_modifier.evex | |
3461 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking | |
3462 | || t->opcode_modifier.staticrounding || t->opcode_modifier.sae; | |
3463 | } | |
3464 | ||
43234a1e L |
3465 | /* Build the EVEX prefix. */ |
3466 | ||
3467 | static void | |
3468 | build_evex_prefix (void) | |
3469 | { | |
3470 | unsigned int register_specifier; | |
3471 | unsigned int implied_prefix; | |
3472 | unsigned int m, w; | |
3473 | rex_byte vrex_used = 0; | |
3474 | ||
3475 | /* Check register specifier. */ | |
3476 | if (i.vex.register_specifier) | |
3477 | { | |
3478 | gas_assert ((i.vrex & REX_X) == 0); | |
3479 | ||
3480 | register_specifier = i.vex.register_specifier->reg_num; | |
3481 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3482 | register_specifier += 8; | |
3483 | /* The upper 16 registers are encoded in the fourth byte of the | |
3484 | EVEX prefix. */ | |
3485 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3486 | i.vex.bytes[3] = 0x8; | |
3487 | register_specifier = ~register_specifier & 0xf; | |
3488 | } | |
3489 | else | |
3490 | { | |
3491 | register_specifier = 0xf; | |
3492 | ||
3493 | /* Encode upper 16 vector index register in the fourth byte of | |
3494 | the EVEX prefix. */ | |
3495 | if (!(i.vrex & REX_X)) | |
3496 | i.vex.bytes[3] = 0x8; | |
3497 | else | |
3498 | vrex_used |= REX_X; | |
3499 | } | |
3500 | ||
3501 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3502 | { | |
3503 | case 0: | |
3504 | implied_prefix = 0; | |
3505 | break; | |
3506 | case DATA_PREFIX_OPCODE: | |
3507 | implied_prefix = 1; | |
3508 | break; | |
3509 | case REPE_PREFIX_OPCODE: | |
3510 | implied_prefix = 2; | |
3511 | break; | |
3512 | case REPNE_PREFIX_OPCODE: | |
3513 | implied_prefix = 3; | |
3514 | break; | |
3515 | default: | |
3516 | abort (); | |
3517 | } | |
3518 | ||
3519 | /* 4 byte EVEX prefix. */ | |
3520 | i.vex.length = 4; | |
3521 | i.vex.bytes[0] = 0x62; | |
3522 | ||
3523 | /* mmmm bits. */ | |
3524 | switch (i.tm.opcode_modifier.vexopcode) | |
3525 | { | |
3526 | case VEX0F: | |
3527 | m = 1; | |
3528 | break; | |
3529 | case VEX0F38: | |
3530 | m = 2; | |
3531 | break; | |
3532 | case VEX0F3A: | |
3533 | m = 3; | |
3534 | break; | |
3535 | default: | |
3536 | abort (); | |
3537 | break; | |
3538 | } | |
3539 | ||
3540 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3541 | bits from REX. */ | |
3542 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3543 | ||
3544 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3545 | REX_R bit in VREX. */ | |
3546 | if (!(i.vrex & REX_R)) | |
3547 | i.vex.bytes[1] |= 0x10; | |
3548 | else | |
3549 | vrex_used |= REX_R; | |
3550 | ||
3551 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3552 | { | |
3553 | /* When all operands are registers, the REX_X bit in REX is not | |
3554 | used. We reuse it to encode the upper 16 registers, which is | |
3555 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3556 | as 1's compliment. */ | |
3557 | if ((i.vrex & REX_B)) | |
3558 | { | |
3559 | vrex_used |= REX_B; | |
3560 | i.vex.bytes[1] &= ~0x40; | |
3561 | } | |
3562 | } | |
3563 | ||
3564 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3565 | i.vrex &= ~vrex_used; | |
3566 | gas_assert (i.vrex == 0); | |
3567 | ||
3568 | /* Check the REX.W bit. */ | |
3569 | w = (i.rex & REX_W) ? 1 : 0; | |
3570 | if (i.tm.opcode_modifier.vexw) | |
3571 | { | |
3572 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
3573 | w = 1; | |
3574 | } | |
3575 | /* If w is not set it means we are dealing with WIG instruction. */ | |
3576 | else if (!w) | |
3577 | { | |
3578 | if (evexwig == evexw1) | |
3579 | w = 1; | |
3580 | } | |
3581 | ||
3582 | /* Encode the U bit. */ | |
3583 | implied_prefix |= 0x4; | |
3584 | ||
3585 | /* The third byte of the EVEX prefix. */ | |
3586 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3587 | ||
3588 | /* The fourth byte of the EVEX prefix. */ | |
3589 | /* The zeroing-masking bit. */ | |
3590 | if (i.mask && i.mask->zeroing) | |
3591 | i.vex.bytes[3] |= 0x80; | |
3592 | ||
3593 | /* Don't always set the broadcast bit if there is no RC. */ | |
3594 | if (!i.rounding) | |
3595 | { | |
3596 | /* Encode the vector length. */ | |
3597 | unsigned int vec_length; | |
3598 | ||
e771e7c9 JB |
3599 | if (!i.tm.opcode_modifier.evex |
3600 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3601 | { | |
3602 | unsigned int op; | |
3603 | ||
3604 | vec_length = 0; | |
3605 | for (op = 0; op < i.tm.operands; ++op) | |
3606 | if (i.tm.operand_types[op].bitfield.xmmword | |
3607 | + i.tm.operand_types[op].bitfield.ymmword | |
3608 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3609 | { | |
3610 | if (i.types[op].bitfield.zmmword) | |
3611 | i.tm.opcode_modifier.evex = EVEX512; | |
3612 | else if (i.types[op].bitfield.ymmword) | |
3613 | i.tm.opcode_modifier.evex = EVEX256; | |
3614 | else if (i.types[op].bitfield.xmmword) | |
3615 | i.tm.opcode_modifier.evex = EVEX128; | |
3616 | else | |
3617 | continue; | |
3618 | break; | |
3619 | } | |
3620 | } | |
3621 | ||
43234a1e L |
3622 | switch (i.tm.opcode_modifier.evex) |
3623 | { | |
3624 | case EVEXLIG: /* LL' is ignored */ | |
3625 | vec_length = evexlig << 5; | |
3626 | break; | |
3627 | case EVEX128: | |
3628 | vec_length = 0 << 5; | |
3629 | break; | |
3630 | case EVEX256: | |
3631 | vec_length = 1 << 5; | |
3632 | break; | |
3633 | case EVEX512: | |
3634 | vec_length = 2 << 5; | |
3635 | break; | |
3636 | default: | |
3637 | abort (); | |
3638 | break; | |
3639 | } | |
3640 | i.vex.bytes[3] |= vec_length; | |
3641 | /* Encode the broadcast bit. */ | |
3642 | if (i.broadcast) | |
3643 | i.vex.bytes[3] |= 0x10; | |
3644 | } | |
3645 | else | |
3646 | { | |
3647 | if (i.rounding->type != saeonly) | |
3648 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3649 | else | |
d3d3c6db | 3650 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3651 | } |
3652 | ||
3653 | if (i.mask && i.mask->mask) | |
3654 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3655 | } | |
3656 | ||
65da13b5 L |
3657 | static void |
3658 | process_immext (void) | |
3659 | { | |
3660 | expressionS *exp; | |
3661 | ||
4c692bc7 JB |
3662 | if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) |
3663 | && i.operands > 0) | |
65da13b5 | 3664 | { |
4c692bc7 JB |
3665 | /* MONITOR/MWAIT as well as SVME instructions have fixed operands |
3666 | with an opcode suffix which is coded in the same place as an | |
3667 | 8-bit immediate field would be. | |
3668 | Here we check those operands and remove them afterwards. */ | |
65da13b5 L |
3669 | unsigned int x; |
3670 | ||
3671 | for (x = 0; x < i.operands; x++) | |
4c692bc7 | 3672 | if (register_number (i.op[x].regs) != x) |
65da13b5 | 3673 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
1fed0ba1 L |
3674 | register_prefix, i.op[x].regs->reg_name, x + 1, |
3675 | i.tm.name); | |
3676 | ||
3677 | i.operands = 0; | |
65da13b5 L |
3678 | } |
3679 | ||
9916071f AP |
3680 | if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0) |
3681 | { | |
3682 | /* MONITORX/MWAITX instructions have fixed operands with an opcode | |
3683 | suffix which is coded in the same place as an 8-bit immediate | |
3684 | field would be. | |
3685 | Here we check those operands and remove them afterwards. */ | |
3686 | unsigned int x; | |
3687 | ||
3688 | if (i.operands != 3) | |
3689 | abort(); | |
3690 | ||
3691 | for (x = 0; x < 2; x++) | |
3692 | if (register_number (i.op[x].regs) != x) | |
3693 | goto bad_register_operand; | |
3694 | ||
3695 | /* Check for third operand for mwaitx/monitorx insn. */ | |
3696 | if (register_number (i.op[x].regs) | |
3697 | != (x + (i.tm.extension_opcode == 0xfb))) | |
3698 | { | |
3699 | bad_register_operand: | |
3700 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
3701 | register_prefix, i.op[x].regs->reg_name, x+1, | |
3702 | i.tm.name); | |
3703 | } | |
3704 | ||
3705 | i.operands = 0; | |
3706 | } | |
3707 | ||
c0f3af97 | 3708 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3709 | which is coded in the same place as an 8-bit immediate field |
3710 | would be. Here we fake an 8-bit immediate operand from the | |
3711 | opcode suffix stored in tm.extension_opcode. | |
3712 | ||
c1e679ec | 3713 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3714 | 3 argument instructions. */ |
65da13b5 | 3715 | |
43234a1e | 3716 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3717 | && (i.operands <= 2 |
43234a1e | 3718 | || ((i.tm.opcode_modifier.vex |
e771e7c9 JB |
3719 | || i.tm.opcode_modifier.vexopcode |
3720 | || is_evex_encoding (&i.tm)) | |
7ab9ffdd | 3721 | && i.operands <= 4))); |
65da13b5 L |
3722 | |
3723 | exp = &im_expressions[i.imm_operands++]; | |
3724 | i.op[i.operands].imms = exp; | |
3725 | i.types[i.operands] = imm8; | |
3726 | i.operands++; | |
3727 | exp->X_op = O_constant; | |
3728 | exp->X_add_number = i.tm.extension_opcode; | |
3729 | i.tm.extension_opcode = None; | |
3730 | } | |
3731 | ||
42164a71 L |
3732 | |
3733 | static int | |
3734 | check_hle (void) | |
3735 | { | |
3736 | switch (i.tm.opcode_modifier.hleprefixok) | |
3737 | { | |
3738 | default: | |
3739 | abort (); | |
82c2def5 | 3740 | case HLEPrefixNone: |
165de32a L |
3741 | as_bad (_("invalid instruction `%s' after `%s'"), |
3742 | i.tm.name, i.hle_prefix); | |
42164a71 | 3743 | return 0; |
82c2def5 | 3744 | case HLEPrefixLock: |
42164a71 L |
3745 | if (i.prefix[LOCK_PREFIX]) |
3746 | return 1; | |
165de32a | 3747 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3748 | return 0; |
82c2def5 | 3749 | case HLEPrefixAny: |
42164a71 | 3750 | return 1; |
82c2def5 | 3751 | case HLEPrefixRelease: |
42164a71 L |
3752 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3753 | { | |
3754 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3755 | i.tm.name); | |
3756 | return 0; | |
3757 | } | |
3758 | if (i.mem_operands == 0 | |
3759 | || !operand_type_check (i.types[i.operands - 1], anymem)) | |
3760 | { | |
3761 | as_bad (_("memory destination needed for instruction `%s'" | |
3762 | " after `xrelease'"), i.tm.name); | |
3763 | return 0; | |
3764 | } | |
3765 | return 1; | |
3766 | } | |
3767 | } | |
3768 | ||
b6f8c7c4 L |
3769 | /* Try the shortest encoding by shortening operand size. */ |
3770 | ||
3771 | static void | |
3772 | optimize_encoding (void) | |
3773 | { | |
3774 | int j; | |
3775 | ||
3776 | if (optimize_for_space | |
3777 | && i.reg_operands == 1 | |
3778 | && i.imm_operands == 1 | |
3779 | && !i.types[1].bitfield.byte | |
3780 | && i.op[0].imms->X_op == O_constant | |
3781 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
3782 | && ((i.tm.base_opcode == 0xa8 | |
3783 | && i.tm.extension_opcode == None) | |
3784 | || (i.tm.base_opcode == 0xf6 | |
3785 | && i.tm.extension_opcode == 0x0))) | |
3786 | { | |
3787 | /* Optimize: -Os: | |
3788 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
3789 | */ | |
3790 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
3791 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
3792 | { | |
3793 | i.types[1].bitfield.byte = 1; | |
3794 | /* Ignore the suffix. */ | |
3795 | i.suffix = 0; | |
3796 | if (base_regnum >= 4 | |
3797 | && !(i.op[1].regs->reg_flags & RegRex)) | |
3798 | { | |
3799 | /* Handle SP, BP, SI and DI registers. */ | |
3800 | if (i.types[1].bitfield.word) | |
3801 | j = 16; | |
3802 | else if (i.types[1].bitfield.dword) | |
3803 | j = 32; | |
3804 | else | |
3805 | j = 48; | |
3806 | i.op[1].regs -= j; | |
3807 | } | |
3808 | } | |
3809 | } | |
3810 | else if (flag_code == CODE_64BIT | |
d3d50934 L |
3811 | && ((i.types[1].bitfield.qword |
3812 | && i.reg_operands == 1 | |
b6f8c7c4 L |
3813 | && i.imm_operands == 1 |
3814 | && i.op[0].imms->X_op == O_constant | |
3815 | && ((i.tm.base_opcode == 0xb0 | |
3816 | && i.tm.extension_opcode == None | |
3817 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
3818 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
3819 | && (((i.tm.base_opcode == 0x24 | |
3820 | || i.tm.base_opcode == 0xa8) | |
3821 | && i.tm.extension_opcode == None) | |
3822 | || (i.tm.base_opcode == 0x80 | |
3823 | && i.tm.extension_opcode == 0x4) | |
3824 | || ((i.tm.base_opcode == 0xf6 | |
3825 | || i.tm.base_opcode == 0xc6) | |
3826 | && i.tm.extension_opcode == 0x0))))) | |
d3d50934 L |
3827 | || (i.types[0].bitfield.qword |
3828 | && ((i.reg_operands == 2 | |
3829 | && i.op[0].regs == i.op[1].regs | |
3830 | && ((i.tm.base_opcode == 0x30 | |
3831 | || i.tm.base_opcode == 0x28) | |
3832 | && i.tm.extension_opcode == None)) | |
3833 | || (i.reg_operands == 1 | |
3834 | && i.operands == 1 | |
3835 | && i.tm.base_opcode == 0x30 | |
3836 | && i.tm.extension_opcode == None))))) | |
b6f8c7c4 L |
3837 | { |
3838 | /* Optimize: -O: | |
3839 | andq $imm31, %r64 -> andl $imm31, %r32 | |
3840 | testq $imm31, %r64 -> testl $imm31, %r32 | |
3841 | xorq %r64, %r64 -> xorl %r32, %r32 | |
3842 | subq %r64, %r64 -> subl %r32, %r32 | |
3843 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3844 | movq $imm32, %r64 -> movl $imm32, %r32 | |
3845 | */ | |
3846 | i.tm.opcode_modifier.norex64 = 1; | |
3847 | if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6) | |
3848 | { | |
3849 | /* Handle | |
3850 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3851 | movq $imm32, %r64 -> movl $imm32, %r32 | |
3852 | */ | |
3853 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
3854 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
3855 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
3856 | i.types[0].bitfield.imm32 = 1; | |
3857 | i.types[0].bitfield.imm32s = 0; | |
3858 | i.types[0].bitfield.imm64 = 0; | |
3859 | i.types[1].bitfield.dword = 1; | |
3860 | i.types[1].bitfield.qword = 0; | |
3861 | if (i.tm.base_opcode == 0xc6) | |
3862 | { | |
3863 | /* Handle | |
3864 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3865 | */ | |
3866 | i.tm.base_opcode = 0xb0; | |
3867 | i.tm.extension_opcode = None; | |
3868 | i.tm.opcode_modifier.shortform = 1; | |
3869 | i.tm.opcode_modifier.modrm = 0; | |
3870 | } | |
3871 | } | |
3872 | } | |
3873 | else if (optimize > 1 | |
3874 | && i.reg_operands == 3 | |
3875 | && i.op[0].regs == i.op[1].regs | |
3876 | && !i.types[2].bitfield.xmmword | |
3877 | && (i.tm.opcode_modifier.vex | |
3878 | || (!i.mask | |
3879 | && !i.rounding | |
e771e7c9 | 3880 | && is_evex_encoding (&i.tm) |
80c34c38 L |
3881 | && (i.vec_encoding != vex_encoding_evex |
3882 | || i.tm.cpu_flags.bitfield.cpuavx512vl | |
0089dace | 3883 | || cpu_arch_isa_flags.bitfield.cpuavx512vl))) |
b6f8c7c4 L |
3884 | && ((i.tm.base_opcode == 0x55 |
3885 | || i.tm.base_opcode == 0x6655 | |
3886 | || i.tm.base_opcode == 0x66df | |
3887 | || i.tm.base_opcode == 0x57 | |
3888 | || i.tm.base_opcode == 0x6657 | |
8305403a L |
3889 | || i.tm.base_opcode == 0x66ef |
3890 | || i.tm.base_opcode == 0x66f8 | |
3891 | || i.tm.base_opcode == 0x66f9 | |
3892 | || i.tm.base_opcode == 0x66fa | |
3893 | || i.tm.base_opcode == 0x66fb) | |
b6f8c7c4 L |
3894 | && i.tm.extension_opcode == None)) |
3895 | { | |
3896 | /* Optimize: -O2: | |
8305403a L |
3897 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
3898 | vpsubq and vpsubw: | |
b6f8c7c4 L |
3899 | EVEX VOP %zmmM, %zmmM, %zmmN |
3900 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
3901 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3902 | EVEX VOP %ymmM, %ymmM, %ymmN | |
3903 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
3904 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3905 | VEX VOP %ymmM, %ymmM, %ymmN | |
3906 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
3907 | VOP, one of vpandn and vpxor: | |
3908 | VEX VOP %ymmM, %ymmM, %ymmN | |
3909 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
3910 | VOP, one of vpandnd and vpandnq: | |
3911 | EVEX VOP %zmmM, %zmmM, %zmmN | |
3912 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
3913 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3914 | EVEX VOP %ymmM, %ymmM, %ymmN | |
3915 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
3916 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3917 | VOP, one of vpxord and vpxorq: | |
3918 | EVEX VOP %zmmM, %zmmM, %zmmN | |
3919 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
3920 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3921 | EVEX VOP %ymmM, %ymmM, %ymmN | |
3922 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
3923 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3924 | */ | |
e771e7c9 | 3925 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 3926 | { |
0089dace | 3927 | if (i.vec_encoding == vex_encoding_evex) |
b6f8c7c4 L |
3928 | i.tm.opcode_modifier.evex = EVEX128; |
3929 | else | |
3930 | { | |
3931 | i.tm.opcode_modifier.vex = VEX128; | |
3932 | i.tm.opcode_modifier.vexw = VEXW0; | |
3933 | i.tm.opcode_modifier.evex = 0; | |
3934 | } | |
3935 | } | |
3936 | else | |
3937 | i.tm.opcode_modifier.vex = VEX128; | |
3938 | ||
3939 | if (i.tm.opcode_modifier.vex) | |
3940 | for (j = 0; j < 3; j++) | |
3941 | { | |
3942 | i.types[j].bitfield.xmmword = 1; | |
3943 | i.types[j].bitfield.ymmword = 0; | |
3944 | } | |
3945 | } | |
3946 | } | |
3947 | ||
252b5132 RH |
3948 | /* This is the guts of the machine-dependent assembler. LINE points to a |
3949 | machine dependent instruction. This function is supposed to emit | |
3950 | the frags/bytes it assembles to. */ | |
3951 | ||
3952 | void | |
65da13b5 | 3953 | md_assemble (char *line) |
252b5132 | 3954 | { |
40fb9820 | 3955 | unsigned int j; |
83b16ac6 | 3956 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 3957 | const insn_template *t; |
252b5132 | 3958 | |
47926f60 | 3959 | /* Initialize globals. */ |
252b5132 RH |
3960 | memset (&i, '\0', sizeof (i)); |
3961 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 3962 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
3963 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
3964 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 3965 | save_stack_p = save_stack; |
252b5132 RH |
3966 | |
3967 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
3968 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 3969 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 3970 | |
29b0f896 AM |
3971 | line = parse_insn (line, mnemonic); |
3972 | if (line == NULL) | |
3973 | return; | |
83b16ac6 | 3974 | mnem_suffix = i.suffix; |
252b5132 | 3975 | |
29b0f896 | 3976 | line = parse_operands (line, mnemonic); |
ee86248c | 3977 | this_operand = -1; |
8325cc63 JB |
3978 | xfree (i.memop1_string); |
3979 | i.memop1_string = NULL; | |
29b0f896 AM |
3980 | if (line == NULL) |
3981 | return; | |
252b5132 | 3982 | |
29b0f896 AM |
3983 | /* Now we've parsed the mnemonic into a set of templates, and have the |
3984 | operands at hand. */ | |
3985 | ||
3986 | /* All intel opcodes have reversed operands except for "bound" and | |
3987 | "enter". We also don't reverse intersegment "jmp" and "call" | |
3988 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 3989 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
3990 | if (intel_syntax |
3991 | && i.operands > 1 | |
29b0f896 | 3992 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 3993 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
3994 | && !(operand_type_check (i.types[0], imm) |
3995 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
3996 | swap_operands (); |
3997 | ||
ec56d5c0 JB |
3998 | /* The order of the immediates should be reversed |
3999 | for 2 immediates extrq and insertq instructions */ | |
4000 | if (i.imm_operands == 2 | |
4001 | && (strcmp (mnemonic, "extrq") == 0 | |
4002 | || strcmp (mnemonic, "insertq") == 0)) | |
4003 | swap_2_operands (0, 1); | |
4004 | ||
29b0f896 AM |
4005 | if (i.imm_operands) |
4006 | optimize_imm (); | |
4007 | ||
b300c311 L |
4008 | /* Don't optimize displacement for movabs since it only takes 64bit |
4009 | displacement. */ | |
4010 | if (i.disp_operands | |
a501d77e | 4011 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
4012 | && (flag_code != CODE_64BIT |
4013 | || strcmp (mnemonic, "movabs") != 0)) | |
4014 | optimize_disp (); | |
29b0f896 AM |
4015 | |
4016 | /* Next, we find a template that matches the given insn, | |
4017 | making sure the overlap of the given operands types is consistent | |
4018 | with the template operand types. */ | |
252b5132 | 4019 | |
83b16ac6 | 4020 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4021 | return; |
252b5132 | 4022 | |
7bab8ab5 | 4023 | if (sse_check != check_none |
81f8a913 | 4024 | && !i.tm.opcode_modifier.noavx |
6e3e5c9e | 4025 | && !i.tm.cpu_flags.bitfield.cpuavx |
daf50ae7 L |
4026 | && (i.tm.cpu_flags.bitfield.cpusse |
4027 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4028 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4029 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4030 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
6e3e5c9e JB |
4031 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
4032 | || i.tm.cpu_flags.bitfield.cpupclmul | |
4033 | || i.tm.cpu_flags.bitfield.cpuaes | |
4034 | || i.tm.cpu_flags.bitfield.cpugfni)) | |
daf50ae7 | 4035 | { |
7bab8ab5 | 4036 | (sse_check == check_warning |
daf50ae7 L |
4037 | ? as_warn |
4038 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4039 | } | |
4040 | ||
321fd21e L |
4041 | /* Zap movzx and movsx suffix. The suffix has been set from |
4042 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
4043 | or extracted from mnemonic in AT&T syntax. But we'll use | |
4044 | the destination register to choose the suffix for encoding. */ | |
4045 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 4046 | { |
321fd21e L |
4047 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
4048 | there is no suffix, the default will be byte extension. */ | |
4049 | if (i.reg_operands != 2 | |
4050 | && !i.suffix | |
7ab9ffdd | 4051 | && intel_syntax) |
321fd21e L |
4052 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
4053 | ||
4054 | i.suffix = 0; | |
cd61ebfe | 4055 | } |
24eab124 | 4056 | |
40fb9820 | 4057 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4058 | if (!add_prefix (FWAIT_OPCODE)) |
4059 | return; | |
252b5132 | 4060 | |
d5de92cf L |
4061 | /* Check if REP prefix is OK. */ |
4062 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
4063 | { | |
4064 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4065 | i.tm.name, i.rep_prefix); | |
4066 | return; | |
4067 | } | |
4068 | ||
c1ba0266 L |
4069 | /* Check for lock without a lockable instruction. Destination operand |
4070 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
4071 | if (i.prefix[LOCK_PREFIX] |
4072 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
4073 | || i.mem_operands == 0 |
4074 | || (i.tm.base_opcode != 0x86 | |
4075 | && !operand_type_check (i.types[i.operands - 1], anymem)))) | |
c32fa91d L |
4076 | { |
4077 | as_bad (_("expecting lockable instruction after `lock'")); | |
4078 | return; | |
4079 | } | |
4080 | ||
42164a71 | 4081 | /* Check if HLE prefix is OK. */ |
165de32a | 4082 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
4083 | return; |
4084 | ||
7e8b059b L |
4085 | /* Check BND prefix. */ |
4086 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
4087 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
4088 | ||
04ef582a | 4089 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
4090 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
4091 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 4092 | |
327e8c42 JB |
4093 | if (i.tm.cpu_flags.bitfield.cpumpx) |
4094 | { | |
4095 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4096 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
4097 | else if (flag_code != CODE_16BIT | |
4098 | ? i.prefix[ADDR_PREFIX] | |
4099 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
4100 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
4101 | } | |
7e8b059b L |
4102 | |
4103 | /* Insert BND prefix. */ | |
4104 | if (add_bnd_prefix | |
4105 | && i.tm.opcode_modifier.bndprefixok | |
4106 | && !i.prefix[BND_PREFIX]) | |
4107 | add_prefix (BND_PREFIX_OPCODE); | |
4108 | ||
29b0f896 | 4109 | /* Check string instruction segment overrides. */ |
40fb9820 | 4110 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
4111 | { |
4112 | if (!check_string ()) | |
5dd0794d | 4113 | return; |
fc0763e6 | 4114 | i.disp_operands = 0; |
29b0f896 | 4115 | } |
5dd0794d | 4116 | |
b6f8c7c4 L |
4117 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
4118 | optimize_encoding (); | |
4119 | ||
29b0f896 AM |
4120 | if (!process_suffix ()) |
4121 | return; | |
e413e4e9 | 4122 | |
bc0844ae L |
4123 | /* Update operand types. */ |
4124 | for (j = 0; j < i.operands; j++) | |
4125 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
4126 | ||
29b0f896 AM |
4127 | /* Make still unresolved immediate matches conform to size of immediate |
4128 | given in i.suffix. */ | |
4129 | if (!finalize_imm ()) | |
4130 | return; | |
252b5132 | 4131 | |
40fb9820 | 4132 | if (i.types[0].bitfield.imm1) |
29b0f896 | 4133 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 4134 | |
9afe6eb8 L |
4135 | /* We only need to check those implicit registers for instructions |
4136 | with 3 operands or less. */ | |
4137 | if (i.operands <= 3) | |
4138 | for (j = 0; j < i.operands; j++) | |
4139 | if (i.types[j].bitfield.inoutportreg | |
4140 | || i.types[j].bitfield.shiftcount | |
1b54b8d7 | 4141 | || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword)) |
9afe6eb8 | 4142 | i.reg_operands--; |
40fb9820 | 4143 | |
c0f3af97 L |
4144 | /* ImmExt should be processed after SSE2AVX. */ |
4145 | if (!i.tm.opcode_modifier.sse2avx | |
4146 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 4147 | process_immext (); |
252b5132 | 4148 | |
29b0f896 AM |
4149 | /* For insns with operands there are more diddles to do to the opcode. */ |
4150 | if (i.operands) | |
4151 | { | |
4152 | if (!process_operands ()) | |
4153 | return; | |
4154 | } | |
40fb9820 | 4155 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
4156 | { |
4157 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
4158 | as_warn (_("translating to `%sp'"), i.tm.name); | |
4159 | } | |
252b5132 | 4160 | |
e771e7c9 JB |
4161 | if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode |
4162 | || is_evex_encoding (&i.tm)) | |
9e5e5283 L |
4163 | { |
4164 | if (flag_code == CODE_16BIT) | |
4165 | { | |
4166 | as_bad (_("instruction `%s' isn't supported in 16-bit mode."), | |
4167 | i.tm.name); | |
4168 | return; | |
4169 | } | |
c0f3af97 | 4170 | |
9e5e5283 L |
4171 | if (i.tm.opcode_modifier.vex) |
4172 | build_vex_prefix (t); | |
4173 | else | |
4174 | build_evex_prefix (); | |
4175 | } | |
43234a1e | 4176 | |
5dd85c99 SP |
4177 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
4178 | instructions may define INT_OPCODE as well, so avoid this corner | |
4179 | case for those instructions that use MODRM. */ | |
4180 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
4181 | && !i.tm.opcode_modifier.modrm |
4182 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
4183 | { |
4184 | i.tm.base_opcode = INT3_OPCODE; | |
4185 | i.imm_operands = 0; | |
4186 | } | |
252b5132 | 4187 | |
40fb9820 L |
4188 | if ((i.tm.opcode_modifier.jump |
4189 | || i.tm.opcode_modifier.jumpbyte | |
4190 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
4191 | && i.op[0].disps->X_op == O_constant) |
4192 | { | |
4193 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
4194 | the absolute address given by the constant. Since ix86 jumps and | |
4195 | calls are pc relative, we need to generate a reloc. */ | |
4196 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
4197 | i.op[0].disps->X_op = O_symbol; | |
4198 | } | |
252b5132 | 4199 | |
40fb9820 | 4200 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 4201 | i.rex |= REX_W; |
252b5132 | 4202 | |
29b0f896 AM |
4203 | /* For 8 bit registers we need an empty rex prefix. Also if the |
4204 | instruction already has a prefix, we need to convert old | |
4205 | registers to new ones. */ | |
773f551c | 4206 | |
dc821c5f | 4207 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte |
29b0f896 | 4208 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
dc821c5f | 4209 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte |
29b0f896 | 4210 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
dc821c5f JB |
4211 | || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte) |
4212 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
4213 | && i.rex != 0)) |
4214 | { | |
4215 | int x; | |
726c5dcd | 4216 | |
29b0f896 AM |
4217 | i.rex |= REX_OPCODE; |
4218 | for (x = 0; x < 2; x++) | |
4219 | { | |
4220 | /* Look for 8 bit operand that uses old registers. */ | |
dc821c5f | 4221 | if (i.types[x].bitfield.reg && i.types[x].bitfield.byte |
29b0f896 | 4222 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 4223 | { |
29b0f896 AM |
4224 | /* In case it is "hi" register, give up. */ |
4225 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 4226 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 4227 | "instruction requiring REX prefix."), |
a540244d | 4228 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 4229 | |
29b0f896 AM |
4230 | /* Otherwise it is equivalent to the extended register. |
4231 | Since the encoding doesn't change this is merely | |
4232 | cosmetic cleanup for debug output. */ | |
4233 | ||
4234 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 4235 | } |
29b0f896 AM |
4236 | } |
4237 | } | |
773f551c | 4238 | |
6b6b6807 L |
4239 | if (i.rex == 0 && i.rex_encoding) |
4240 | { | |
4241 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
4242 | that uses legacy register. If it is "hi" register, don't add | |
4243 | the REX_OPCODE byte. */ | |
4244 | int x; | |
4245 | for (x = 0; x < 2; x++) | |
4246 | if (i.types[x].bitfield.reg | |
4247 | && i.types[x].bitfield.byte | |
4248 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4249 | && i.op[x].regs->reg_num > 3) | |
4250 | { | |
4251 | i.rex_encoding = FALSE; | |
4252 | break; | |
4253 | } | |
4254 | ||
4255 | if (i.rex_encoding) | |
4256 | i.rex = REX_OPCODE; | |
4257 | } | |
4258 | ||
7ab9ffdd | 4259 | if (i.rex != 0) |
29b0f896 AM |
4260 | add_prefix (REX_OPCODE | i.rex); |
4261 | ||
4262 | /* We are ready to output the insn. */ | |
4263 | output_insn (); | |
4264 | } | |
4265 | ||
4266 | static char * | |
e3bb37b5 | 4267 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
4268 | { |
4269 | char *l = line; | |
4270 | char *token_start = l; | |
4271 | char *mnem_p; | |
5c6af06e | 4272 | int supported; |
d3ce72d0 | 4273 | const insn_template *t; |
b6169b20 | 4274 | char *dot_p = NULL; |
29b0f896 | 4275 | |
29b0f896 AM |
4276 | while (1) |
4277 | { | |
4278 | mnem_p = mnemonic; | |
4279 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
4280 | { | |
b6169b20 L |
4281 | if (*mnem_p == '.') |
4282 | dot_p = mnem_p; | |
29b0f896 AM |
4283 | mnem_p++; |
4284 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 4285 | { |
29b0f896 AM |
4286 | as_bad (_("no such instruction: `%s'"), token_start); |
4287 | return NULL; | |
4288 | } | |
4289 | l++; | |
4290 | } | |
4291 | if (!is_space_char (*l) | |
4292 | && *l != END_OF_INSN | |
e44823cf JB |
4293 | && (intel_syntax |
4294 | || (*l != PREFIX_SEPARATOR | |
4295 | && *l != ','))) | |
29b0f896 AM |
4296 | { |
4297 | as_bad (_("invalid character %s in mnemonic"), | |
4298 | output_invalid (*l)); | |
4299 | return NULL; | |
4300 | } | |
4301 | if (token_start == l) | |
4302 | { | |
e44823cf | 4303 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
4304 | as_bad (_("expecting prefix; got nothing")); |
4305 | else | |
4306 | as_bad (_("expecting mnemonic; got nothing")); | |
4307 | return NULL; | |
4308 | } | |
45288df1 | 4309 | |
29b0f896 | 4310 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 4311 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 4312 | |
29b0f896 AM |
4313 | if (*l != END_OF_INSN |
4314 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
4315 | && current_templates | |
40fb9820 | 4316 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 4317 | { |
c6fb90c8 | 4318 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
4319 | { |
4320 | as_bad ((flag_code != CODE_64BIT | |
4321 | ? _("`%s' is only supported in 64-bit mode") | |
4322 | : _("`%s' is not supported in 64-bit mode")), | |
4323 | current_templates->start->name); | |
4324 | return NULL; | |
4325 | } | |
29b0f896 AM |
4326 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
4327 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
4328 | if ((current_templates->start->opcode_modifier.size16 |
4329 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 4330 | && flag_code != CODE_64BIT |
40fb9820 | 4331 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
4332 | ^ (flag_code == CODE_16BIT))) |
4333 | { | |
4334 | as_bad (_("redundant %s prefix"), | |
4335 | current_templates->start->name); | |
4336 | return NULL; | |
45288df1 | 4337 | } |
86fa6981 | 4338 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 4339 | { |
86fa6981 L |
4340 | /* Handle pseudo prefixes. */ |
4341 | switch (current_templates->start->base_opcode) | |
4342 | { | |
4343 | case 0x0: | |
4344 | /* {disp8} */ | |
4345 | i.disp_encoding = disp_encoding_8bit; | |
4346 | break; | |
4347 | case 0x1: | |
4348 | /* {disp32} */ | |
4349 | i.disp_encoding = disp_encoding_32bit; | |
4350 | break; | |
4351 | case 0x2: | |
4352 | /* {load} */ | |
4353 | i.dir_encoding = dir_encoding_load; | |
4354 | break; | |
4355 | case 0x3: | |
4356 | /* {store} */ | |
4357 | i.dir_encoding = dir_encoding_store; | |
4358 | break; | |
4359 | case 0x4: | |
4360 | /* {vex2} */ | |
4361 | i.vec_encoding = vex_encoding_vex2; | |
4362 | break; | |
4363 | case 0x5: | |
4364 | /* {vex3} */ | |
4365 | i.vec_encoding = vex_encoding_vex3; | |
4366 | break; | |
4367 | case 0x6: | |
4368 | /* {evex} */ | |
4369 | i.vec_encoding = vex_encoding_evex; | |
4370 | break; | |
6b6b6807 L |
4371 | case 0x7: |
4372 | /* {rex} */ | |
4373 | i.rex_encoding = TRUE; | |
4374 | break; | |
b6f8c7c4 L |
4375 | case 0x8: |
4376 | /* {nooptimize} */ | |
4377 | i.no_optimize = TRUE; | |
4378 | break; | |
86fa6981 L |
4379 | default: |
4380 | abort (); | |
4381 | } | |
4382 | } | |
4383 | else | |
4384 | { | |
4385 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 4386 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 4387 | { |
4e9ac44a L |
4388 | case PREFIX_EXIST: |
4389 | return NULL; | |
4390 | case PREFIX_DS: | |
d777820b | 4391 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
4392 | i.notrack_prefix = current_templates->start->name; |
4393 | break; | |
4394 | case PREFIX_REP: | |
4395 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
4396 | i.hle_prefix = current_templates->start->name; | |
4397 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
4398 | i.bnd_prefix = current_templates->start->name; | |
4399 | else | |
4400 | i.rep_prefix = current_templates->start->name; | |
4401 | break; | |
4402 | default: | |
4403 | break; | |
86fa6981 | 4404 | } |
29b0f896 AM |
4405 | } |
4406 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
4407 | token_start = ++l; | |
4408 | } | |
4409 | else | |
4410 | break; | |
4411 | } | |
45288df1 | 4412 | |
30a55f88 | 4413 | if (!current_templates) |
b6169b20 | 4414 | { |
f8a5c266 L |
4415 | /* Check if we should swap operand or force 32bit displacement in |
4416 | encoding. */ | |
30a55f88 | 4417 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
86fa6981 | 4418 | i.dir_encoding = dir_encoding_store; |
8d63c93e | 4419 | else if (mnem_p - 3 == dot_p |
a501d77e L |
4420 | && dot_p[1] == 'd' |
4421 | && dot_p[2] == '8') | |
4422 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 4423 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
4424 | && dot_p[1] == 'd' |
4425 | && dot_p[2] == '3' | |
4426 | && dot_p[3] == '2') | |
a501d77e | 4427 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
4428 | else |
4429 | goto check_suffix; | |
4430 | mnem_p = dot_p; | |
4431 | *dot_p = '\0'; | |
d3ce72d0 | 4432 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
4433 | } |
4434 | ||
29b0f896 AM |
4435 | if (!current_templates) |
4436 | { | |
b6169b20 | 4437 | check_suffix: |
29b0f896 AM |
4438 | /* See if we can get a match by trimming off a suffix. */ |
4439 | switch (mnem_p[-1]) | |
4440 | { | |
4441 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
4442 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
4443 | i.suffix = SHORT_MNEM_SUFFIX; | |
4444 | else | |
1a0670f3 | 4445 | /* Fall through. */ |
29b0f896 AM |
4446 | case BYTE_MNEM_SUFFIX: |
4447 | case QWORD_MNEM_SUFFIX: | |
4448 | i.suffix = mnem_p[-1]; | |
4449 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4450 | current_templates = (const templates *) hash_find (op_hash, |
4451 | mnemonic); | |
29b0f896 AM |
4452 | break; |
4453 | case SHORT_MNEM_SUFFIX: | |
4454 | case LONG_MNEM_SUFFIX: | |
4455 | if (!intel_syntax) | |
4456 | { | |
4457 | i.suffix = mnem_p[-1]; | |
4458 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4459 | current_templates = (const templates *) hash_find (op_hash, |
4460 | mnemonic); | |
29b0f896 AM |
4461 | } |
4462 | break; | |
252b5132 | 4463 | |
29b0f896 AM |
4464 | /* Intel Syntax. */ |
4465 | case 'd': | |
4466 | if (intel_syntax) | |
4467 | { | |
9306ca4a | 4468 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
4469 | i.suffix = SHORT_MNEM_SUFFIX; |
4470 | else | |
4471 | i.suffix = LONG_MNEM_SUFFIX; | |
4472 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4473 | current_templates = (const templates *) hash_find (op_hash, |
4474 | mnemonic); | |
29b0f896 AM |
4475 | } |
4476 | break; | |
4477 | } | |
4478 | if (!current_templates) | |
4479 | { | |
4480 | as_bad (_("no such instruction: `%s'"), token_start); | |
4481 | return NULL; | |
4482 | } | |
4483 | } | |
252b5132 | 4484 | |
40fb9820 L |
4485 | if (current_templates->start->opcode_modifier.jump |
4486 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
4487 | { |
4488 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4489 | predict taken and predict not taken respectively. | |
4490 | I'm not sure that branch hints actually do anything on loop | |
4491 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4492 | may work in the future and it doesn't hurt to accept them | |
4493 | now. */ | |
4494 | if (l[0] == ',' && l[1] == 'p') | |
4495 | { | |
4496 | if (l[2] == 't') | |
4497 | { | |
4498 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4499 | return NULL; | |
4500 | l += 3; | |
4501 | } | |
4502 | else if (l[2] == 'n') | |
4503 | { | |
4504 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4505 | return NULL; | |
4506 | l += 3; | |
4507 | } | |
4508 | } | |
4509 | } | |
4510 | /* Any other comma loses. */ | |
4511 | if (*l == ',') | |
4512 | { | |
4513 | as_bad (_("invalid character %s in mnemonic"), | |
4514 | output_invalid (*l)); | |
4515 | return NULL; | |
4516 | } | |
252b5132 | 4517 | |
29b0f896 | 4518 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4519 | supported = 0; |
4520 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4521 | { | |
c0f3af97 L |
4522 | supported |= cpu_flags_match (t); |
4523 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
548d0ee6 JB |
4524 | { |
4525 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) | |
4526 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3629bb00 | 4527 | |
548d0ee6 JB |
4528 | return l; |
4529 | } | |
29b0f896 | 4530 | } |
3629bb00 | 4531 | |
548d0ee6 JB |
4532 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
4533 | as_bad (flag_code == CODE_64BIT | |
4534 | ? _("`%s' is not supported in 64-bit mode") | |
4535 | : _("`%s' is only supported in 64-bit mode"), | |
4536 | current_templates->start->name); | |
4537 | else | |
4538 | as_bad (_("`%s' is not supported on `%s%s'"), | |
4539 | current_templates->start->name, | |
4540 | cpu_arch_name ? cpu_arch_name : default_arch, | |
4541 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 4542 | |
548d0ee6 | 4543 | return NULL; |
29b0f896 | 4544 | } |
252b5132 | 4545 | |
29b0f896 | 4546 | static char * |
e3bb37b5 | 4547 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4548 | { |
4549 | char *token_start; | |
3138f287 | 4550 | |
29b0f896 AM |
4551 | /* 1 if operand is pending after ','. */ |
4552 | unsigned int expecting_operand = 0; | |
252b5132 | 4553 | |
29b0f896 AM |
4554 | /* Non-zero if operand parens not balanced. */ |
4555 | unsigned int paren_not_balanced; | |
4556 | ||
4557 | while (*l != END_OF_INSN) | |
4558 | { | |
4559 | /* Skip optional white space before operand. */ | |
4560 | if (is_space_char (*l)) | |
4561 | ++l; | |
d02603dc | 4562 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4563 | { |
4564 | as_bad (_("invalid character %s before operand %d"), | |
4565 | output_invalid (*l), | |
4566 | i.operands + 1); | |
4567 | return NULL; | |
4568 | } | |
d02603dc | 4569 | token_start = l; /* After white space. */ |
29b0f896 AM |
4570 | paren_not_balanced = 0; |
4571 | while (paren_not_balanced || *l != ',') | |
4572 | { | |
4573 | if (*l == END_OF_INSN) | |
4574 | { | |
4575 | if (paren_not_balanced) | |
4576 | { | |
4577 | if (!intel_syntax) | |
4578 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4579 | i.operands + 1); | |
4580 | else | |
4581 | as_bad (_("unbalanced brackets in operand %d."), | |
4582 | i.operands + 1); | |
4583 | return NULL; | |
4584 | } | |
4585 | else | |
4586 | break; /* we are done */ | |
4587 | } | |
d02603dc | 4588 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4589 | { |
4590 | as_bad (_("invalid character %s in operand %d"), | |
4591 | output_invalid (*l), | |
4592 | i.operands + 1); | |
4593 | return NULL; | |
4594 | } | |
4595 | if (!intel_syntax) | |
4596 | { | |
4597 | if (*l == '(') | |
4598 | ++paren_not_balanced; | |
4599 | if (*l == ')') | |
4600 | --paren_not_balanced; | |
4601 | } | |
4602 | else | |
4603 | { | |
4604 | if (*l == '[') | |
4605 | ++paren_not_balanced; | |
4606 | if (*l == ']') | |
4607 | --paren_not_balanced; | |
4608 | } | |
4609 | l++; | |
4610 | } | |
4611 | if (l != token_start) | |
4612 | { /* Yes, we've read in another operand. */ | |
4613 | unsigned int operand_ok; | |
4614 | this_operand = i.operands++; | |
4615 | if (i.operands > MAX_OPERANDS) | |
4616 | { | |
4617 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
4618 | MAX_OPERANDS); | |
4619 | return NULL; | |
4620 | } | |
9d46ce34 | 4621 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
4622 | /* Now parse operand adding info to 'i' as we go along. */ |
4623 | END_STRING_AND_SAVE (l); | |
4624 | ||
4625 | if (intel_syntax) | |
4626 | operand_ok = | |
4627 | i386_intel_operand (token_start, | |
4628 | intel_float_operand (mnemonic)); | |
4629 | else | |
a7619375 | 4630 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
4631 | |
4632 | RESTORE_END_STRING (l); | |
4633 | if (!operand_ok) | |
4634 | return NULL; | |
4635 | } | |
4636 | else | |
4637 | { | |
4638 | if (expecting_operand) | |
4639 | { | |
4640 | expecting_operand_after_comma: | |
4641 | as_bad (_("expecting operand after ','; got nothing")); | |
4642 | return NULL; | |
4643 | } | |
4644 | if (*l == ',') | |
4645 | { | |
4646 | as_bad (_("expecting operand before ','; got nothing")); | |
4647 | return NULL; | |
4648 | } | |
4649 | } | |
7f3f1ea2 | 4650 | |
29b0f896 AM |
4651 | /* Now *l must be either ',' or END_OF_INSN. */ |
4652 | if (*l == ',') | |
4653 | { | |
4654 | if (*++l == END_OF_INSN) | |
4655 | { | |
4656 | /* Just skip it, if it's \n complain. */ | |
4657 | goto expecting_operand_after_comma; | |
4658 | } | |
4659 | expecting_operand = 1; | |
4660 | } | |
4661 | } | |
4662 | return l; | |
4663 | } | |
7f3f1ea2 | 4664 | |
050dfa73 | 4665 | static void |
4d456e3d | 4666 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
4667 | { |
4668 | union i386_op temp_op; | |
40fb9820 | 4669 | i386_operand_type temp_type; |
050dfa73 | 4670 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 4671 | |
050dfa73 MM |
4672 | temp_type = i.types[xchg2]; |
4673 | i.types[xchg2] = i.types[xchg1]; | |
4674 | i.types[xchg1] = temp_type; | |
4675 | temp_op = i.op[xchg2]; | |
4676 | i.op[xchg2] = i.op[xchg1]; | |
4677 | i.op[xchg1] = temp_op; | |
4678 | temp_reloc = i.reloc[xchg2]; | |
4679 | i.reloc[xchg2] = i.reloc[xchg1]; | |
4680 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
4681 | |
4682 | if (i.mask) | |
4683 | { | |
4684 | if (i.mask->operand == xchg1) | |
4685 | i.mask->operand = xchg2; | |
4686 | else if (i.mask->operand == xchg2) | |
4687 | i.mask->operand = xchg1; | |
4688 | } | |
4689 | if (i.broadcast) | |
4690 | { | |
4691 | if (i.broadcast->operand == xchg1) | |
4692 | i.broadcast->operand = xchg2; | |
4693 | else if (i.broadcast->operand == xchg2) | |
4694 | i.broadcast->operand = xchg1; | |
4695 | } | |
4696 | if (i.rounding) | |
4697 | { | |
4698 | if (i.rounding->operand == xchg1) | |
4699 | i.rounding->operand = xchg2; | |
4700 | else if (i.rounding->operand == xchg2) | |
4701 | i.rounding->operand = xchg1; | |
4702 | } | |
050dfa73 MM |
4703 | } |
4704 | ||
29b0f896 | 4705 | static void |
e3bb37b5 | 4706 | swap_operands (void) |
29b0f896 | 4707 | { |
b7c61d9a | 4708 | switch (i.operands) |
050dfa73 | 4709 | { |
c0f3af97 | 4710 | case 5: |
b7c61d9a | 4711 | case 4: |
4d456e3d | 4712 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 4713 | /* Fall through. */ |
b7c61d9a L |
4714 | case 3: |
4715 | case 2: | |
4d456e3d | 4716 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
4717 | break; |
4718 | default: | |
4719 | abort (); | |
29b0f896 | 4720 | } |
29b0f896 AM |
4721 | |
4722 | if (i.mem_operands == 2) | |
4723 | { | |
4724 | const seg_entry *temp_seg; | |
4725 | temp_seg = i.seg[0]; | |
4726 | i.seg[0] = i.seg[1]; | |
4727 | i.seg[1] = temp_seg; | |
4728 | } | |
4729 | } | |
252b5132 | 4730 | |
29b0f896 AM |
4731 | /* Try to ensure constant immediates are represented in the smallest |
4732 | opcode possible. */ | |
4733 | static void | |
e3bb37b5 | 4734 | optimize_imm (void) |
29b0f896 AM |
4735 | { |
4736 | char guess_suffix = 0; | |
4737 | int op; | |
252b5132 | 4738 | |
29b0f896 AM |
4739 | if (i.suffix) |
4740 | guess_suffix = i.suffix; | |
4741 | else if (i.reg_operands) | |
4742 | { | |
4743 | /* Figure out a suffix from the last register operand specified. | |
4744 | We can't do this properly yet, ie. excluding InOutPortReg, | |
4745 | but the following works for instructions with immediates. | |
4746 | In any case, we can't set i.suffix yet. */ | |
4747 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 4748 | if (i.types[op].bitfield.reg && i.types[op].bitfield.byte) |
7ab9ffdd | 4749 | { |
40fb9820 L |
4750 | guess_suffix = BYTE_MNEM_SUFFIX; |
4751 | break; | |
4752 | } | |
dc821c5f | 4753 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.word) |
252b5132 | 4754 | { |
40fb9820 L |
4755 | guess_suffix = WORD_MNEM_SUFFIX; |
4756 | break; | |
4757 | } | |
dc821c5f | 4758 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword) |
40fb9820 L |
4759 | { |
4760 | guess_suffix = LONG_MNEM_SUFFIX; | |
4761 | break; | |
4762 | } | |
dc821c5f | 4763 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword) |
40fb9820 L |
4764 | { |
4765 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 4766 | break; |
252b5132 | 4767 | } |
29b0f896 AM |
4768 | } |
4769 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
4770 | guess_suffix = WORD_MNEM_SUFFIX; | |
4771 | ||
4772 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 4773 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
4774 | { |
4775 | switch (i.op[op].imms->X_op) | |
252b5132 | 4776 | { |
29b0f896 AM |
4777 | case O_constant: |
4778 | /* If a suffix is given, this operand may be shortened. */ | |
4779 | switch (guess_suffix) | |
252b5132 | 4780 | { |
29b0f896 | 4781 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
4782 | i.types[op].bitfield.imm32 = 1; |
4783 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4784 | break; |
4785 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
4786 | i.types[op].bitfield.imm16 = 1; |
4787 | i.types[op].bitfield.imm32 = 1; | |
4788 | i.types[op].bitfield.imm32s = 1; | |
4789 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4790 | break; |
4791 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
4792 | i.types[op].bitfield.imm8 = 1; |
4793 | i.types[op].bitfield.imm8s = 1; | |
4794 | i.types[op].bitfield.imm16 = 1; | |
4795 | i.types[op].bitfield.imm32 = 1; | |
4796 | i.types[op].bitfield.imm32s = 1; | |
4797 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 4798 | break; |
252b5132 | 4799 | } |
252b5132 | 4800 | |
29b0f896 AM |
4801 | /* If this operand is at most 16 bits, convert it |
4802 | to a signed 16 bit number before trying to see | |
4803 | whether it will fit in an even smaller size. | |
4804 | This allows a 16-bit operand such as $0xffe0 to | |
4805 | be recognised as within Imm8S range. */ | |
40fb9820 | 4806 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 4807 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 4808 | { |
29b0f896 AM |
4809 | i.op[op].imms->X_add_number = |
4810 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
4811 | } | |
a28def75 L |
4812 | #ifdef BFD64 |
4813 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 4814 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
4815 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
4816 | == 0)) | |
4817 | { | |
4818 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
4819 | ^ ((offsetT) 1 << 31)) | |
4820 | - ((offsetT) 1 << 31)); | |
4821 | } | |
a28def75 | 4822 | #endif |
40fb9820 | 4823 | i.types[op] |
c6fb90c8 L |
4824 | = operand_type_or (i.types[op], |
4825 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 4826 | |
29b0f896 AM |
4827 | /* We must avoid matching of Imm32 templates when 64bit |
4828 | only immediate is available. */ | |
4829 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 4830 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 4831 | break; |
252b5132 | 4832 | |
29b0f896 AM |
4833 | case O_absent: |
4834 | case O_register: | |
4835 | abort (); | |
4836 | ||
4837 | /* Symbols and expressions. */ | |
4838 | default: | |
9cd96992 JB |
4839 | /* Convert symbolic operand to proper sizes for matching, but don't |
4840 | prevent matching a set of insns that only supports sizes other | |
4841 | than those matching the insn suffix. */ | |
4842 | { | |
40fb9820 | 4843 | i386_operand_type mask, allowed; |
d3ce72d0 | 4844 | const insn_template *t; |
9cd96992 | 4845 | |
0dfbf9d7 L |
4846 | operand_type_set (&mask, 0); |
4847 | operand_type_set (&allowed, 0); | |
40fb9820 | 4848 | |
4eed87de AM |
4849 | for (t = current_templates->start; |
4850 | t < current_templates->end; | |
4851 | ++t) | |
c6fb90c8 L |
4852 | allowed = operand_type_or (allowed, |
4853 | t->operand_types[op]); | |
9cd96992 JB |
4854 | switch (guess_suffix) |
4855 | { | |
4856 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
4857 | mask.bitfield.imm64 = 1; |
4858 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
4859 | break; |
4860 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 4861 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
4862 | break; |
4863 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 4864 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
4865 | break; |
4866 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 4867 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
4868 | break; |
4869 | default: | |
9cd96992 JB |
4870 | break; |
4871 | } | |
c6fb90c8 | 4872 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 4873 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 4874 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 4875 | } |
29b0f896 | 4876 | break; |
252b5132 | 4877 | } |
29b0f896 AM |
4878 | } |
4879 | } | |
47926f60 | 4880 | |
29b0f896 AM |
4881 | /* Try to use the smallest displacement type too. */ |
4882 | static void | |
e3bb37b5 | 4883 | optimize_disp (void) |
29b0f896 AM |
4884 | { |
4885 | int op; | |
3e73aa7c | 4886 | |
29b0f896 | 4887 | for (op = i.operands; --op >= 0;) |
40fb9820 | 4888 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 4889 | { |
b300c311 | 4890 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 4891 | { |
91d6fa6a | 4892 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 4893 | |
40fb9820 | 4894 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 4895 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
4896 | { |
4897 | /* If this operand is at most 16 bits, convert | |
4898 | to a signed 16 bit number and don't use 64bit | |
4899 | displacement. */ | |
91d6fa6a | 4900 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 4901 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 4902 | } |
a28def75 L |
4903 | #ifdef BFD64 |
4904 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 4905 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 4906 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
4907 | { |
4908 | /* If this operand is at most 32 bits, convert | |
4909 | to a signed 32 bit number and don't use 64bit | |
4910 | displacement. */ | |
91d6fa6a NC |
4911 | op_disp &= (((offsetT) 2 << 31) - 1); |
4912 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 4913 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 4914 | } |
a28def75 | 4915 | #endif |
91d6fa6a | 4916 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 4917 | { |
40fb9820 L |
4918 | i.types[op].bitfield.disp8 = 0; |
4919 | i.types[op].bitfield.disp16 = 0; | |
4920 | i.types[op].bitfield.disp32 = 0; | |
4921 | i.types[op].bitfield.disp32s = 0; | |
4922 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
4923 | i.op[op].disps = 0; |
4924 | i.disp_operands--; | |
4925 | } | |
4926 | else if (flag_code == CODE_64BIT) | |
4927 | { | |
91d6fa6a | 4928 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 4929 | { |
40fb9820 L |
4930 | i.types[op].bitfield.disp64 = 0; |
4931 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 4932 | } |
0e1147d9 | 4933 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 4934 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 4935 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 4936 | } |
40fb9820 L |
4937 | if ((i.types[op].bitfield.disp32 |
4938 | || i.types[op].bitfield.disp32s | |
4939 | || i.types[op].bitfield.disp16) | |
b5014f7a | 4940 | && fits_in_disp8 (op_disp)) |
40fb9820 | 4941 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 4942 | } |
67a4f2b7 AO |
4943 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
4944 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
4945 | { | |
4946 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
4947 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
4948 | i.types[op].bitfield.disp8 = 0; |
4949 | i.types[op].bitfield.disp16 = 0; | |
4950 | i.types[op].bitfield.disp32 = 0; | |
4951 | i.types[op].bitfield.disp32s = 0; | |
4952 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
4953 | } |
4954 | else | |
b300c311 | 4955 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 4956 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 4957 | } |
29b0f896 AM |
4958 | } |
4959 | ||
6c30d220 L |
4960 | /* Check if operands are valid for the instruction. */ |
4961 | ||
4962 | static int | |
4963 | check_VecOperands (const insn_template *t) | |
4964 | { | |
43234a1e L |
4965 | unsigned int op; |
4966 | ||
6c30d220 L |
4967 | /* Without VSIB byte, we can't have a vector register for index. */ |
4968 | if (!t->opcode_modifier.vecsib | |
4969 | && i.index_reg | |
1b54b8d7 JB |
4970 | && (i.index_reg->reg_type.bitfield.xmmword |
4971 | || i.index_reg->reg_type.bitfield.ymmword | |
4972 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
4973 | { |
4974 | i.error = unsupported_vector_index_register; | |
4975 | return 1; | |
4976 | } | |
4977 | ||
ad8ecc81 MZ |
4978 | /* Check if default mask is allowed. */ |
4979 | if (t->opcode_modifier.nodefmask | |
4980 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
4981 | { | |
4982 | i.error = no_default_mask; | |
4983 | return 1; | |
4984 | } | |
4985 | ||
7bab8ab5 JB |
4986 | /* For VSIB byte, we need a vector register for index, and all vector |
4987 | registers must be distinct. */ | |
4988 | if (t->opcode_modifier.vecsib) | |
4989 | { | |
4990 | if (!i.index_reg | |
6c30d220 | 4991 | || !((t->opcode_modifier.vecsib == VecSIB128 |
1b54b8d7 | 4992 | && i.index_reg->reg_type.bitfield.xmmword) |
6c30d220 | 4993 | || (t->opcode_modifier.vecsib == VecSIB256 |
1b54b8d7 | 4994 | && i.index_reg->reg_type.bitfield.ymmword) |
43234a1e | 4995 | || (t->opcode_modifier.vecsib == VecSIB512 |
1b54b8d7 | 4996 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
4997 | { |
4998 | i.error = invalid_vsib_address; | |
4999 | return 1; | |
5000 | } | |
5001 | ||
43234a1e L |
5002 | gas_assert (i.reg_operands == 2 || i.mask); |
5003 | if (i.reg_operands == 2 && !i.mask) | |
5004 | { | |
1b54b8d7 JB |
5005 | gas_assert (i.types[0].bitfield.regsimd); |
5006 | gas_assert (i.types[0].bitfield.xmmword | |
5007 | || i.types[0].bitfield.ymmword); | |
5008 | gas_assert (i.types[2].bitfield.regsimd); | |
5009 | gas_assert (i.types[2].bitfield.xmmword | |
5010 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
5011 | if (operand_check == check_none) |
5012 | return 0; | |
5013 | if (register_number (i.op[0].regs) | |
5014 | != register_number (i.index_reg) | |
5015 | && register_number (i.op[2].regs) | |
5016 | != register_number (i.index_reg) | |
5017 | && register_number (i.op[0].regs) | |
5018 | != register_number (i.op[2].regs)) | |
5019 | return 0; | |
5020 | if (operand_check == check_error) | |
5021 | { | |
5022 | i.error = invalid_vector_register_set; | |
5023 | return 1; | |
5024 | } | |
5025 | as_warn (_("mask, index, and destination registers should be distinct")); | |
5026 | } | |
8444f82a MZ |
5027 | else if (i.reg_operands == 1 && i.mask) |
5028 | { | |
1b54b8d7 JB |
5029 | if (i.types[1].bitfield.regsimd |
5030 | && (i.types[1].bitfield.xmmword | |
5031 | || i.types[1].bitfield.ymmword | |
5032 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
5033 | && (register_number (i.op[1].regs) |
5034 | == register_number (i.index_reg))) | |
5035 | { | |
5036 | if (operand_check == check_error) | |
5037 | { | |
5038 | i.error = invalid_vector_register_set; | |
5039 | return 1; | |
5040 | } | |
5041 | if (operand_check != check_none) | |
5042 | as_warn (_("index and destination registers should be distinct")); | |
5043 | } | |
5044 | } | |
43234a1e | 5045 | } |
7bab8ab5 | 5046 | |
43234a1e L |
5047 | /* Check if broadcast is supported by the instruction and is applied |
5048 | to the memory operand. */ | |
5049 | if (i.broadcast) | |
5050 | { | |
5051 | int broadcasted_opnd_size; | |
5052 | ||
5053 | /* Check if specified broadcast is supported in this instruction, | |
5054 | and it's applied to memory operand of DWORD or QWORD type, | |
5055 | depending on VecESize. */ | |
32546502 | 5056 | op = i.broadcast->operand; |
43234a1e | 5057 | if (i.broadcast->type != t->opcode_modifier.broadcast |
32546502 | 5058 | || !i.types[op].bitfield.mem |
43234a1e | 5059 | || (t->opcode_modifier.vecesize == 0 |
32546502 JB |
5060 | && !i.types[op].bitfield.dword |
5061 | && !i.types[op].bitfield.unspecified) | |
43234a1e | 5062 | || (t->opcode_modifier.vecesize == 1 |
32546502 JB |
5063 | && !i.types[op].bitfield.qword |
5064 | && !i.types[op].bitfield.unspecified)) | |
43234a1e L |
5065 | goto bad_broadcast; |
5066 | ||
5067 | broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32; | |
5068 | if (i.broadcast->type == BROADCAST_1TO16) | |
5069 | broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */ | |
5070 | else if (i.broadcast->type == BROADCAST_1TO8) | |
5071 | broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */ | |
b28d1bda IT |
5072 | else if (i.broadcast->type == BROADCAST_1TO4) |
5073 | broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */ | |
5074 | else if (i.broadcast->type == BROADCAST_1TO2) | |
5075 | broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */ | |
43234a1e L |
5076 | else |
5077 | goto bad_broadcast; | |
5078 | ||
5079 | if ((broadcasted_opnd_size == 256 | |
32546502 | 5080 | && !t->operand_types[op].bitfield.ymmword) |
43234a1e | 5081 | || (broadcasted_opnd_size == 512 |
32546502 | 5082 | && !t->operand_types[op].bitfield.zmmword)) |
43234a1e L |
5083 | { |
5084 | bad_broadcast: | |
5085 | i.error = unsupported_broadcast; | |
5086 | return 1; | |
5087 | } | |
5088 | } | |
5089 | /* If broadcast is supported in this instruction, we need to check if | |
5090 | operand of one-element size isn't specified without broadcast. */ | |
5091 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
5092 | { | |
5093 | /* Find memory operand. */ | |
5094 | for (op = 0; op < i.operands; op++) | |
5095 | if (operand_type_check (i.types[op], anymem)) | |
5096 | break; | |
5097 | gas_assert (op < i.operands); | |
5098 | /* Check size of the memory operand. */ | |
5099 | if ((t->opcode_modifier.vecesize == 0 | |
5100 | && i.types[op].bitfield.dword) | |
5101 | || (t->opcode_modifier.vecesize == 1 | |
5102 | && i.types[op].bitfield.qword)) | |
5103 | { | |
5104 | i.error = broadcast_needed; | |
5105 | return 1; | |
5106 | } | |
5107 | } | |
5108 | ||
5109 | /* Check if requested masking is supported. */ | |
5110 | if (i.mask | |
5111 | && (!t->opcode_modifier.masking | |
5112 | || (i.mask->zeroing | |
5113 | && t->opcode_modifier.masking == MERGING_MASKING))) | |
5114 | { | |
5115 | i.error = unsupported_masking; | |
5116 | return 1; | |
5117 | } | |
5118 | ||
5119 | /* Check if masking is applied to dest operand. */ | |
5120 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
5121 | { | |
5122 | i.error = mask_not_on_destination; | |
5123 | return 1; | |
5124 | } | |
5125 | ||
43234a1e L |
5126 | /* Check RC/SAE. */ |
5127 | if (i.rounding) | |
5128 | { | |
5129 | if ((i.rounding->type != saeonly | |
5130 | && !t->opcode_modifier.staticrounding) | |
5131 | || (i.rounding->type == saeonly | |
5132 | && (t->opcode_modifier.staticrounding | |
5133 | || !t->opcode_modifier.sae))) | |
5134 | { | |
5135 | i.error = unsupported_rc_sae; | |
5136 | return 1; | |
5137 | } | |
5138 | /* If the instruction has several immediate operands and one of | |
5139 | them is rounding, the rounding operand should be the last | |
5140 | immediate operand. */ | |
5141 | if (i.imm_operands > 1 | |
5142 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 5143 | { |
43234a1e | 5144 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
5145 | return 1; |
5146 | } | |
6c30d220 L |
5147 | } |
5148 | ||
43234a1e | 5149 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
5150 | if (t->opcode_modifier.disp8memshift |
5151 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
5152 | { |
5153 | if (i.broadcast) | |
5154 | i.memshift = t->opcode_modifier.vecesize ? 3 : 2; | |
5155 | else | |
5156 | i.memshift = t->opcode_modifier.disp8memshift; | |
5157 | ||
5158 | for (op = 0; op < i.operands; op++) | |
5159 | if (operand_type_check (i.types[op], disp) | |
5160 | && i.op[op].disps->X_op == O_constant) | |
5161 | { | |
b5014f7a | 5162 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 5163 | { |
b5014f7a JB |
5164 | i.types[op].bitfield.disp8 = 1; |
5165 | return 0; | |
43234a1e | 5166 | } |
b5014f7a | 5167 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
5168 | } |
5169 | } | |
b5014f7a JB |
5170 | |
5171 | i.memshift = 0; | |
43234a1e | 5172 | |
6c30d220 L |
5173 | return 0; |
5174 | } | |
5175 | ||
43f3e2ee | 5176 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
5177 | operand types. */ |
5178 | ||
5179 | static int | |
5180 | VEX_check_operands (const insn_template *t) | |
5181 | { | |
86fa6981 | 5182 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 5183 | { |
86fa6981 | 5184 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 5185 | if (!is_evex_encoding (t)) |
86fa6981 L |
5186 | { |
5187 | i.error = unsupported; | |
5188 | return 1; | |
5189 | } | |
5190 | return 0; | |
43234a1e L |
5191 | } |
5192 | ||
a683cc34 | 5193 | if (!t->opcode_modifier.vex) |
86fa6981 L |
5194 | { |
5195 | /* This instruction template doesn't have VEX prefix. */ | |
5196 | if (i.vec_encoding != vex_encoding_default) | |
5197 | { | |
5198 | i.error = unsupported; | |
5199 | return 1; | |
5200 | } | |
5201 | return 0; | |
5202 | } | |
a683cc34 SP |
5203 | |
5204 | /* Only check VEX_Imm4, which must be the first operand. */ | |
5205 | if (t->operand_types[0].bitfield.vec_imm4) | |
5206 | { | |
5207 | if (i.op[0].imms->X_op != O_constant | |
5208 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 5209 | { |
a65babc9 | 5210 | i.error = bad_imm4; |
891edac4 L |
5211 | return 1; |
5212 | } | |
a683cc34 SP |
5213 | |
5214 | /* Turn off Imm8 so that update_imm won't complain. */ | |
5215 | i.types[0] = vec_imm4; | |
5216 | } | |
5217 | ||
5218 | return 0; | |
5219 | } | |
5220 | ||
d3ce72d0 | 5221 | static const insn_template * |
83b16ac6 | 5222 | match_template (char mnem_suffix) |
29b0f896 AM |
5223 | { |
5224 | /* Points to template once we've found it. */ | |
d3ce72d0 | 5225 | const insn_template *t; |
40fb9820 | 5226 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 5227 | i386_operand_type overlap4; |
29b0f896 | 5228 | unsigned int found_reverse_match; |
83b16ac6 | 5229 | i386_opcode_modifier suffix_check, mnemsuf_check; |
40fb9820 | 5230 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 5231 | int addr_prefix_disp; |
a5c311ca | 5232 | unsigned int j; |
3629bb00 | 5233 | unsigned int found_cpu_match; |
45664ddb | 5234 | unsigned int check_register; |
5614d22c | 5235 | enum i386_error specific_error = 0; |
29b0f896 | 5236 | |
c0f3af97 L |
5237 | #if MAX_OPERANDS != 5 |
5238 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
5239 | #endif |
5240 | ||
29b0f896 | 5241 | found_reverse_match = 0; |
539e75ad | 5242 | addr_prefix_disp = -1; |
40fb9820 L |
5243 | |
5244 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
5245 | if (i.suffix == BYTE_MNEM_SUFFIX) | |
5246 | suffix_check.no_bsuf = 1; | |
5247 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5248 | suffix_check.no_wsuf = 1; | |
5249 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
5250 | suffix_check.no_ssuf = 1; | |
5251 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
5252 | suffix_check.no_lsuf = 1; | |
5253 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5254 | suffix_check.no_qsuf = 1; | |
5255 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 5256 | suffix_check.no_ldsuf = 1; |
29b0f896 | 5257 | |
83b16ac6 JB |
5258 | memset (&mnemsuf_check, 0, sizeof (mnemsuf_check)); |
5259 | if (intel_syntax) | |
5260 | { | |
5261 | switch (mnem_suffix) | |
5262 | { | |
5263 | case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break; | |
5264 | case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break; | |
5265 | case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break; | |
5266 | case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break; | |
5267 | case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break; | |
5268 | } | |
5269 | } | |
5270 | ||
01559ecc L |
5271 | /* Must have right number of operands. */ |
5272 | i.error = number_of_operands_mismatch; | |
5273 | ||
45aa61fe | 5274 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 5275 | { |
539e75ad L |
5276 | addr_prefix_disp = -1; |
5277 | ||
29b0f896 AM |
5278 | if (i.operands != t->operands) |
5279 | continue; | |
5280 | ||
50aecf8c | 5281 | /* Check processor support. */ |
a65babc9 | 5282 | i.error = unsupported; |
c0f3af97 L |
5283 | found_cpu_match = (cpu_flags_match (t) |
5284 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
5285 | if (!found_cpu_match) |
5286 | continue; | |
5287 | ||
e1d4d893 | 5288 | /* Check AT&T mnemonic. */ |
a65babc9 | 5289 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 5290 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
5291 | continue; |
5292 | ||
e92bae62 | 5293 | /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ |
a65babc9 | 5294 | i.error = unsupported_syntax; |
5c07affc | 5295 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
e92bae62 L |
5296 | || (!intel_syntax && t->opcode_modifier.intelsyntax) |
5297 | || (intel64 && t->opcode_modifier.amd64) | |
5298 | || (!intel64 && t->opcode_modifier.intel64)) | |
1efbbeb4 L |
5299 | continue; |
5300 | ||
20592a94 | 5301 | /* Check the suffix, except for some instructions in intel mode. */ |
a65babc9 | 5302 | i.error = invalid_instruction_suffix; |
567e4e96 L |
5303 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
5304 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
5305 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
5306 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
5307 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
5308 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
5309 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 | 5310 | continue; |
83b16ac6 JB |
5311 | /* In Intel mode all mnemonic suffixes must be explicitly allowed. */ |
5312 | if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf) | |
5313 | || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf) | |
5314 | || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf) | |
5315 | || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf) | |
5316 | || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf) | |
5317 | || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf)) | |
5318 | continue; | |
29b0f896 | 5319 | |
5c07affc | 5320 | if (!operand_size_match (t)) |
7d5e4556 | 5321 | continue; |
539e75ad | 5322 | |
5c07affc L |
5323 | for (j = 0; j < MAX_OPERANDS; j++) |
5324 | operand_types[j] = t->operand_types[j]; | |
5325 | ||
45aa61fe AM |
5326 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
5327 | if (i.suffix == QWORD_MNEM_SUFFIX | |
5328 | && flag_code != CODE_64BIT | |
5329 | && (intel_syntax | |
40fb9820 | 5330 | ? (!t->opcode_modifier.ignoresize |
45aa61fe AM |
5331 | && !intel_float_operand (t->name)) |
5332 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 5333 | && ((!operand_types[0].bitfield.regmmx |
1b54b8d7 | 5334 | && !operand_types[0].bitfield.regsimd) |
40fb9820 | 5335 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5336 | && !operand_types[t->operands > 1].bitfield.regsimd)) |
45aa61fe AM |
5337 | && (t->base_opcode != 0x0fc7 |
5338 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
5339 | continue; | |
5340 | ||
192dc9c6 JB |
5341 | /* In general, don't allow 32-bit operands on pre-386. */ |
5342 | else if (i.suffix == LONG_MNEM_SUFFIX | |
5343 | && !cpu_arch_flags.bitfield.cpui386 | |
5344 | && (intel_syntax | |
5345 | ? (!t->opcode_modifier.ignoresize | |
5346 | && !intel_float_operand (t->name)) | |
5347 | : intel_float_operand (t->name) != 2) | |
5348 | && ((!operand_types[0].bitfield.regmmx | |
1b54b8d7 | 5349 | && !operand_types[0].bitfield.regsimd) |
192dc9c6 | 5350 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5351 | && !operand_types[t->operands > 1].bitfield.regsimd))) |
192dc9c6 JB |
5352 | continue; |
5353 | ||
29b0f896 | 5354 | /* Do not verify operands when there are none. */ |
50aecf8c | 5355 | else |
29b0f896 | 5356 | { |
c6fb90c8 | 5357 | if (!t->operands) |
2dbab7d5 L |
5358 | /* We've found a match; break out of loop. */ |
5359 | break; | |
29b0f896 | 5360 | } |
252b5132 | 5361 | |
539e75ad L |
5362 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
5363 | into Disp32/Disp16/Disp32 operand. */ | |
5364 | if (i.prefix[ADDR_PREFIX] != 0) | |
5365 | { | |
40fb9820 | 5366 | /* There should be only one Disp operand. */ |
539e75ad L |
5367 | switch (flag_code) |
5368 | { | |
5369 | case CODE_16BIT: | |
40fb9820 L |
5370 | for (j = 0; j < MAX_OPERANDS; j++) |
5371 | { | |
5372 | if (operand_types[j].bitfield.disp16) | |
5373 | { | |
5374 | addr_prefix_disp = j; | |
5375 | operand_types[j].bitfield.disp32 = 1; | |
5376 | operand_types[j].bitfield.disp16 = 0; | |
5377 | break; | |
5378 | } | |
5379 | } | |
539e75ad L |
5380 | break; |
5381 | case CODE_32BIT: | |
40fb9820 L |
5382 | for (j = 0; j < MAX_OPERANDS; j++) |
5383 | { | |
5384 | if (operand_types[j].bitfield.disp32) | |
5385 | { | |
5386 | addr_prefix_disp = j; | |
5387 | operand_types[j].bitfield.disp32 = 0; | |
5388 | operand_types[j].bitfield.disp16 = 1; | |
5389 | break; | |
5390 | } | |
5391 | } | |
539e75ad L |
5392 | break; |
5393 | case CODE_64BIT: | |
40fb9820 L |
5394 | for (j = 0; j < MAX_OPERANDS; j++) |
5395 | { | |
5396 | if (operand_types[j].bitfield.disp64) | |
5397 | { | |
5398 | addr_prefix_disp = j; | |
5399 | operand_types[j].bitfield.disp64 = 0; | |
5400 | operand_types[j].bitfield.disp32 = 1; | |
5401 | break; | |
5402 | } | |
5403 | } | |
539e75ad L |
5404 | break; |
5405 | } | |
539e75ad L |
5406 | } |
5407 | ||
02a86693 L |
5408 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
5409 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
5410 | continue; | |
5411 | ||
56ffb741 L |
5412 | /* We check register size if needed. */ |
5413 | check_register = t->opcode_modifier.checkregsize; | |
c6fb90c8 | 5414 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
5415 | switch (t->operands) |
5416 | { | |
5417 | case 1: | |
40fb9820 | 5418 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
5419 | continue; |
5420 | break; | |
5421 | case 2: | |
33eaf5de | 5422 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
5423 | only in 32bit mode and we can use opcode 0x90. In 64bit |
5424 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
5425 | zero-extend %eax to %rax. */ | |
5426 | if (flag_code == CODE_64BIT | |
5427 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
5428 | && operand_type_equal (&i.types [0], &acc32) |
5429 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 5430 | continue; |
1212781b JB |
5431 | /* xrelease mov %eax, <disp> is another special case. It must not |
5432 | match the accumulator-only encoding of mov. */ | |
5433 | if (flag_code != CODE_64BIT | |
5434 | && i.hle_prefix | |
5435 | && t->base_opcode == 0xa0 | |
5436 | && i.types[0].bitfield.acc | |
5437 | && operand_type_check (i.types[1], anymem)) | |
5438 | continue; | |
86fa6981 L |
5439 | /* If we want store form, we reverse direction of operands. */ |
5440 | if (i.dir_encoding == dir_encoding_store | |
5441 | && t->opcode_modifier.d) | |
5442 | goto check_reverse; | |
1a0670f3 | 5443 | /* Fall through. */ |
b6169b20 | 5444 | |
29b0f896 | 5445 | case 3: |
86fa6981 L |
5446 | /* If we want store form, we skip the current load. */ |
5447 | if (i.dir_encoding == dir_encoding_store | |
5448 | && i.mem_operands == 0 | |
5449 | && t->opcode_modifier.load) | |
fa99fab2 | 5450 | continue; |
1a0670f3 | 5451 | /* Fall through. */ |
f48ff2ae | 5452 | case 4: |
c0f3af97 | 5453 | case 5: |
c6fb90c8 | 5454 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
5455 | if (!operand_type_match (overlap0, i.types[0]) |
5456 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb | 5457 | || (check_register |
dc821c5f | 5458 | && !operand_type_register_match (i.types[0], |
40fb9820 | 5459 | operand_types[0], |
dc821c5f | 5460 | i.types[1], |
40fb9820 | 5461 | operand_types[1]))) |
29b0f896 AM |
5462 | { |
5463 | /* Check if other direction is valid ... */ | |
38e314eb | 5464 | if (!t->opcode_modifier.d) |
29b0f896 AM |
5465 | continue; |
5466 | ||
b6169b20 | 5467 | check_reverse: |
29b0f896 | 5468 | /* Try reversing direction of operands. */ |
c6fb90c8 L |
5469 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
5470 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
5471 | if (!operand_type_match (overlap0, i.types[0]) |
5472 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb | 5473 | || (check_register |
dc821c5f | 5474 | && !operand_type_register_match (i.types[0], |
45664ddb | 5475 | operand_types[1], |
45664ddb L |
5476 | i.types[1], |
5477 | operand_types[0]))) | |
29b0f896 AM |
5478 | { |
5479 | /* Does not match either direction. */ | |
5480 | continue; | |
5481 | } | |
38e314eb | 5482 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 5483 | we've found. */ |
38e314eb JB |
5484 | if (!t->opcode_modifier.d) |
5485 | found_reverse_match = 0; | |
5486 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 L |
5487 | found_reverse_match = Opcode_FloatD; |
5488 | else | |
38e314eb | 5489 | found_reverse_match = Opcode_D; |
40fb9820 | 5490 | if (t->opcode_modifier.floatr) |
8a2ed489 | 5491 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 5492 | } |
f48ff2ae | 5493 | else |
29b0f896 | 5494 | { |
f48ff2ae | 5495 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
5496 | switch (t->operands) |
5497 | { | |
c0f3af97 L |
5498 | case 5: |
5499 | overlap4 = operand_type_and (i.types[4], | |
5500 | operand_types[4]); | |
1a0670f3 | 5501 | /* Fall through. */ |
d1cbb4db | 5502 | case 4: |
c6fb90c8 L |
5503 | overlap3 = operand_type_and (i.types[3], |
5504 | operand_types[3]); | |
1a0670f3 | 5505 | /* Fall through. */ |
d1cbb4db | 5506 | case 3: |
c6fb90c8 L |
5507 | overlap2 = operand_type_and (i.types[2], |
5508 | operand_types[2]); | |
d1cbb4db L |
5509 | break; |
5510 | } | |
29b0f896 | 5511 | |
f48ff2ae L |
5512 | switch (t->operands) |
5513 | { | |
c0f3af97 L |
5514 | case 5: |
5515 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 5516 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 5517 | operand_types[3], |
c0f3af97 L |
5518 | i.types[4], |
5519 | operand_types[4])) | |
5520 | continue; | |
1a0670f3 | 5521 | /* Fall through. */ |
f48ff2ae | 5522 | case 4: |
40fb9820 | 5523 | if (!operand_type_match (overlap3, i.types[3]) |
45664ddb | 5524 | || (check_register |
f7768225 JB |
5525 | && (!operand_type_register_match (i.types[1], |
5526 | operand_types[1], | |
5527 | i.types[3], | |
5528 | operand_types[3]) | |
5529 | || !operand_type_register_match (i.types[2], | |
5530 | operand_types[2], | |
5531 | i.types[3], | |
5532 | operand_types[3])))) | |
f48ff2ae | 5533 | continue; |
1a0670f3 | 5534 | /* Fall through. */ |
f48ff2ae L |
5535 | case 3: |
5536 | /* Here we make use of the fact that there are no | |
23e42951 | 5537 | reverse match 3 operand instructions. */ |
40fb9820 | 5538 | if (!operand_type_match (overlap2, i.types[2]) |
45664ddb | 5539 | || (check_register |
23e42951 JB |
5540 | && (!operand_type_register_match (i.types[0], |
5541 | operand_types[0], | |
5542 | i.types[2], | |
5543 | operand_types[2]) | |
5544 | || !operand_type_register_match (i.types[1], | |
5545 | operand_types[1], | |
5546 | i.types[2], | |
5547 | operand_types[2])))) | |
f48ff2ae L |
5548 | continue; |
5549 | break; | |
5550 | } | |
29b0f896 | 5551 | } |
f48ff2ae | 5552 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
5553 | slip through to break. */ |
5554 | } | |
3629bb00 | 5555 | if (!found_cpu_match) |
29b0f896 AM |
5556 | { |
5557 | found_reverse_match = 0; | |
5558 | continue; | |
5559 | } | |
c0f3af97 | 5560 | |
5614d22c JB |
5561 | /* Check if vector and VEX operands are valid. */ |
5562 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
5563 | { | |
5564 | specific_error = i.error; | |
5565 | continue; | |
5566 | } | |
a683cc34 | 5567 | |
29b0f896 AM |
5568 | /* We've found a match; break out of loop. */ |
5569 | break; | |
5570 | } | |
5571 | ||
5572 | if (t == current_templates->end) | |
5573 | { | |
5574 | /* We found no match. */ | |
a65babc9 | 5575 | const char *err_msg; |
5614d22c | 5576 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
5577 | { |
5578 | default: | |
5579 | abort (); | |
86e026a4 | 5580 | case operand_size_mismatch: |
a65babc9 L |
5581 | err_msg = _("operand size mismatch"); |
5582 | break; | |
5583 | case operand_type_mismatch: | |
5584 | err_msg = _("operand type mismatch"); | |
5585 | break; | |
5586 | case register_type_mismatch: | |
5587 | err_msg = _("register type mismatch"); | |
5588 | break; | |
5589 | case number_of_operands_mismatch: | |
5590 | err_msg = _("number of operands mismatch"); | |
5591 | break; | |
5592 | case invalid_instruction_suffix: | |
5593 | err_msg = _("invalid instruction suffix"); | |
5594 | break; | |
5595 | case bad_imm4: | |
4a2608e3 | 5596 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 5597 | break; |
a65babc9 L |
5598 | case unsupported_with_intel_mnemonic: |
5599 | err_msg = _("unsupported with Intel mnemonic"); | |
5600 | break; | |
5601 | case unsupported_syntax: | |
5602 | err_msg = _("unsupported syntax"); | |
5603 | break; | |
5604 | case unsupported: | |
35262a23 | 5605 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
5606 | current_templates->start->name); |
5607 | return NULL; | |
6c30d220 L |
5608 | case invalid_vsib_address: |
5609 | err_msg = _("invalid VSIB address"); | |
5610 | break; | |
7bab8ab5 JB |
5611 | case invalid_vector_register_set: |
5612 | err_msg = _("mask, index, and destination registers must be distinct"); | |
5613 | break; | |
6c30d220 L |
5614 | case unsupported_vector_index_register: |
5615 | err_msg = _("unsupported vector index register"); | |
5616 | break; | |
43234a1e L |
5617 | case unsupported_broadcast: |
5618 | err_msg = _("unsupported broadcast"); | |
5619 | break; | |
5620 | case broadcast_not_on_src_operand: | |
5621 | err_msg = _("broadcast not on source memory operand"); | |
5622 | break; | |
5623 | case broadcast_needed: | |
5624 | err_msg = _("broadcast is needed for operand of such type"); | |
5625 | break; | |
5626 | case unsupported_masking: | |
5627 | err_msg = _("unsupported masking"); | |
5628 | break; | |
5629 | case mask_not_on_destination: | |
5630 | err_msg = _("mask not on destination operand"); | |
5631 | break; | |
5632 | case no_default_mask: | |
5633 | err_msg = _("default mask isn't allowed"); | |
5634 | break; | |
5635 | case unsupported_rc_sae: | |
5636 | err_msg = _("unsupported static rounding/sae"); | |
5637 | break; | |
5638 | case rc_sae_operand_not_last_imm: | |
5639 | if (intel_syntax) | |
5640 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
5641 | else | |
5642 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
5643 | break; | |
5644 | case invalid_register_operand: | |
5645 | err_msg = _("invalid register operand"); | |
5646 | break; | |
a65babc9 L |
5647 | } |
5648 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 5649 | current_templates->start->name); |
fa99fab2 | 5650 | return NULL; |
29b0f896 | 5651 | } |
252b5132 | 5652 | |
29b0f896 AM |
5653 | if (!quiet_warnings) |
5654 | { | |
5655 | if (!intel_syntax | |
40fb9820 L |
5656 | && (i.types[0].bitfield.jumpabsolute |
5657 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
5658 | { |
5659 | as_warn (_("indirect %s without `*'"), t->name); | |
5660 | } | |
5661 | ||
40fb9820 L |
5662 | if (t->opcode_modifier.isprefix |
5663 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
5664 | { |
5665 | /* Warn them that a data or address size prefix doesn't | |
5666 | affect assembly of the next line of code. */ | |
5667 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
5668 | } | |
5669 | } | |
5670 | ||
5671 | /* Copy the template we found. */ | |
5672 | i.tm = *t; | |
539e75ad L |
5673 | |
5674 | if (addr_prefix_disp != -1) | |
5675 | i.tm.operand_types[addr_prefix_disp] | |
5676 | = operand_types[addr_prefix_disp]; | |
5677 | ||
29b0f896 AM |
5678 | if (found_reverse_match) |
5679 | { | |
5680 | /* If we found a reverse match we must alter the opcode | |
5681 | direction bit. found_reverse_match holds bits to change | |
5682 | (different for int & float insns). */ | |
5683 | ||
5684 | i.tm.base_opcode ^= found_reverse_match; | |
5685 | ||
539e75ad L |
5686 | i.tm.operand_types[0] = operand_types[1]; |
5687 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
5688 | } |
5689 | ||
fa99fab2 | 5690 | return t; |
29b0f896 AM |
5691 | } |
5692 | ||
5693 | static int | |
e3bb37b5 | 5694 | check_string (void) |
29b0f896 | 5695 | { |
40fb9820 L |
5696 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
5697 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
5698 | { |
5699 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
5700 | { | |
a87af027 | 5701 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 5702 | i.tm.name, |
a87af027 JB |
5703 | mem_op + 1, |
5704 | register_prefix); | |
29b0f896 AM |
5705 | return 0; |
5706 | } | |
5707 | /* There's only ever one segment override allowed per instruction. | |
5708 | This instruction possibly has a legal segment override on the | |
5709 | second operand, so copy the segment to where non-string | |
5710 | instructions store it, allowing common code. */ | |
5711 | i.seg[0] = i.seg[1]; | |
5712 | } | |
40fb9820 | 5713 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
5714 | { |
5715 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
5716 | { | |
a87af027 | 5717 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 5718 | i.tm.name, |
a87af027 JB |
5719 | mem_op + 2, |
5720 | register_prefix); | |
29b0f896 AM |
5721 | return 0; |
5722 | } | |
5723 | } | |
5724 | return 1; | |
5725 | } | |
5726 | ||
5727 | static int | |
543613e9 | 5728 | process_suffix (void) |
29b0f896 AM |
5729 | { |
5730 | /* If matched instruction specifies an explicit instruction mnemonic | |
5731 | suffix, use it. */ | |
40fb9820 L |
5732 | if (i.tm.opcode_modifier.size16) |
5733 | i.suffix = WORD_MNEM_SUFFIX; | |
5734 | else if (i.tm.opcode_modifier.size32) | |
5735 | i.suffix = LONG_MNEM_SUFFIX; | |
5736 | else if (i.tm.opcode_modifier.size64) | |
5737 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
5738 | else if (i.reg_operands) |
5739 | { | |
5740 | /* If there's no instruction mnemonic suffix we try to invent one | |
5741 | based on register operands. */ | |
5742 | if (!i.suffix) | |
5743 | { | |
5744 | /* We take i.suffix from the last register operand specified, | |
5745 | Destination register type is more significant than source | |
381d071f L |
5746 | register type. crc32 in SSE4.2 prefers source register |
5747 | type. */ | |
5748 | if (i.tm.base_opcode == 0xf20f38f1) | |
5749 | { | |
dc821c5f | 5750 | if (i.types[0].bitfield.reg && i.types[0].bitfield.word) |
40fb9820 | 5751 | i.suffix = WORD_MNEM_SUFFIX; |
dc821c5f | 5752 | else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword) |
40fb9820 | 5753 | i.suffix = LONG_MNEM_SUFFIX; |
dc821c5f | 5754 | else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword) |
40fb9820 | 5755 | i.suffix = QWORD_MNEM_SUFFIX; |
381d071f | 5756 | } |
9344ff29 | 5757 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 5758 | { |
dc821c5f | 5759 | if (i.types[0].bitfield.reg && i.types[0].bitfield.byte) |
20592a94 L |
5760 | i.suffix = BYTE_MNEM_SUFFIX; |
5761 | } | |
381d071f L |
5762 | |
5763 | if (!i.suffix) | |
5764 | { | |
5765 | int op; | |
5766 | ||
20592a94 L |
5767 | if (i.tm.base_opcode == 0xf20f38f1 |
5768 | || i.tm.base_opcode == 0xf20f38f0) | |
5769 | { | |
5770 | /* We have to know the operand size for crc32. */ | |
5771 | as_bad (_("ambiguous memory operand size for `%s`"), | |
5772 | i.tm.name); | |
5773 | return 0; | |
5774 | } | |
5775 | ||
381d071f | 5776 | for (op = i.operands; --op >= 0;) |
b76bc5d5 JB |
5777 | if (!i.tm.operand_types[op].bitfield.inoutportreg |
5778 | && !i.tm.operand_types[op].bitfield.shiftcount) | |
381d071f | 5779 | { |
8819ada6 JB |
5780 | if (!i.types[op].bitfield.reg) |
5781 | continue; | |
5782 | if (i.types[op].bitfield.byte) | |
5783 | i.suffix = BYTE_MNEM_SUFFIX; | |
5784 | else if (i.types[op].bitfield.word) | |
5785 | i.suffix = WORD_MNEM_SUFFIX; | |
5786 | else if (i.types[op].bitfield.dword) | |
5787 | i.suffix = LONG_MNEM_SUFFIX; | |
5788 | else if (i.types[op].bitfield.qword) | |
5789 | i.suffix = QWORD_MNEM_SUFFIX; | |
5790 | else | |
5791 | continue; | |
5792 | break; | |
381d071f L |
5793 | } |
5794 | } | |
29b0f896 AM |
5795 | } |
5796 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
5797 | { | |
2eb952a4 L |
5798 | if (intel_syntax |
5799 | && i.tm.opcode_modifier.ignoresize | |
5800 | && i.tm.opcode_modifier.no_bsuf) | |
5801 | i.suffix = 0; | |
5802 | else if (!check_byte_reg ()) | |
29b0f896 AM |
5803 | return 0; |
5804 | } | |
5805 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
5806 | { | |
2eb952a4 L |
5807 | if (intel_syntax |
5808 | && i.tm.opcode_modifier.ignoresize | |
5809 | && i.tm.opcode_modifier.no_lsuf) | |
5810 | i.suffix = 0; | |
5811 | else if (!check_long_reg ()) | |
29b0f896 AM |
5812 | return 0; |
5813 | } | |
5814 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5815 | { | |
955e1e6a L |
5816 | if (intel_syntax |
5817 | && i.tm.opcode_modifier.ignoresize | |
5818 | && i.tm.opcode_modifier.no_qsuf) | |
5819 | i.suffix = 0; | |
5820 | else if (!check_qword_reg ()) | |
29b0f896 AM |
5821 | return 0; |
5822 | } | |
5823 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5824 | { | |
2eb952a4 L |
5825 | if (intel_syntax |
5826 | && i.tm.opcode_modifier.ignoresize | |
5827 | && i.tm.opcode_modifier.no_wsuf) | |
5828 | i.suffix = 0; | |
5829 | else if (!check_word_reg ()) | |
29b0f896 AM |
5830 | return 0; |
5831 | } | |
40fb9820 | 5832 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
5833 | /* Do nothing if the instruction is going to ignore the prefix. */ |
5834 | ; | |
5835 | else | |
5836 | abort (); | |
5837 | } | |
40fb9820 | 5838 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
5839 | && !i.suffix |
5840 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 5841 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
5842 | { |
5843 | i.suffix = stackop_size; | |
5844 | } | |
9306ca4a JB |
5845 | else if (intel_syntax |
5846 | && !i.suffix | |
40fb9820 L |
5847 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
5848 | || i.tm.opcode_modifier.jumpbyte | |
5849 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
5850 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
5851 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
5852 | { |
5853 | switch (flag_code) | |
5854 | { | |
5855 | case CODE_64BIT: | |
40fb9820 | 5856 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
5857 | { |
5858 | i.suffix = QWORD_MNEM_SUFFIX; | |
5859 | break; | |
5860 | } | |
1a0670f3 | 5861 | /* Fall through. */ |
9306ca4a | 5862 | case CODE_32BIT: |
40fb9820 | 5863 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
5864 | i.suffix = LONG_MNEM_SUFFIX; |
5865 | break; | |
5866 | case CODE_16BIT: | |
40fb9820 | 5867 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
5868 | i.suffix = WORD_MNEM_SUFFIX; |
5869 | break; | |
5870 | } | |
5871 | } | |
252b5132 | 5872 | |
9306ca4a | 5873 | if (!i.suffix) |
29b0f896 | 5874 | { |
9306ca4a JB |
5875 | if (!intel_syntax) |
5876 | { | |
40fb9820 | 5877 | if (i.tm.opcode_modifier.w) |
9306ca4a | 5878 | { |
4eed87de AM |
5879 | as_bad (_("no instruction mnemonic suffix given and " |
5880 | "no register operands; can't size instruction")); | |
9306ca4a JB |
5881 | return 0; |
5882 | } | |
5883 | } | |
5884 | else | |
5885 | { | |
40fb9820 | 5886 | unsigned int suffixes; |
7ab9ffdd | 5887 | |
40fb9820 L |
5888 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
5889 | if (!i.tm.opcode_modifier.no_wsuf) | |
5890 | suffixes |= 1 << 1; | |
5891 | if (!i.tm.opcode_modifier.no_lsuf) | |
5892 | suffixes |= 1 << 2; | |
fc4adea1 | 5893 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
5894 | suffixes |= 1 << 3; |
5895 | if (!i.tm.opcode_modifier.no_ssuf) | |
5896 | suffixes |= 1 << 4; | |
c2b9da16 | 5897 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) |
40fb9820 L |
5898 | suffixes |= 1 << 5; |
5899 | ||
5900 | /* There are more than suffix matches. */ | |
5901 | if (i.tm.opcode_modifier.w | |
9306ca4a | 5902 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
5903 | && !i.tm.opcode_modifier.defaultsize |
5904 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
5905 | { |
5906 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
5907 | return 0; | |
5908 | } | |
5909 | } | |
29b0f896 | 5910 | } |
252b5132 | 5911 | |
d2224064 JB |
5912 | /* Change the opcode based on the operand size given by i.suffix. */ |
5913 | switch (i.suffix) | |
29b0f896 | 5914 | { |
d2224064 JB |
5915 | /* Size floating point instruction. */ |
5916 | case LONG_MNEM_SUFFIX: | |
5917 | if (i.tm.opcode_modifier.floatmf) | |
5918 | { | |
5919 | i.tm.base_opcode ^= 4; | |
5920 | break; | |
5921 | } | |
5922 | /* fall through */ | |
5923 | case WORD_MNEM_SUFFIX: | |
5924 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 5925 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 5926 | if (i.tm.opcode_modifier.w) |
29b0f896 | 5927 | { |
40fb9820 | 5928 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
5929 | i.tm.base_opcode |= 8; |
5930 | else | |
5931 | i.tm.base_opcode |= 1; | |
5932 | } | |
d2224064 JB |
5933 | /* fall through */ |
5934 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
5935 | /* Now select between word & dword operations via the operand |
5936 | size prefix, except for instructions that will ignore this | |
5937 | prefix anyway. */ | |
ca61edf2 | 5938 | if (i.tm.opcode_modifier.addrprefixop0) |
cb712a9e | 5939 | { |
ca61edf2 L |
5940 | /* The address size override prefix changes the size of the |
5941 | first operand. */ | |
40fb9820 | 5942 | if ((flag_code == CODE_32BIT |
dc821c5f | 5943 | && i.op->regs[0].reg_type.bitfield.word) |
40fb9820 | 5944 | || (flag_code != CODE_32BIT |
dc821c5f | 5945 | && i.op->regs[0].reg_type.bitfield.dword)) |
cb712a9e L |
5946 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
5947 | return 0; | |
5948 | } | |
5949 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
40fb9820 L |
5950 | && !i.tm.opcode_modifier.ignoresize |
5951 | && !i.tm.opcode_modifier.floatmf | |
cb712a9e L |
5952 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
5953 | || (flag_code == CODE_64BIT | |
40fb9820 | 5954 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
5955 | { |
5956 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 5957 | |
40fb9820 | 5958 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 5959 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 5960 | |
29b0f896 AM |
5961 | if (!add_prefix (prefix)) |
5962 | return 0; | |
24eab124 | 5963 | } |
252b5132 | 5964 | |
29b0f896 AM |
5965 | /* Set mode64 for an operand. */ |
5966 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 5967 | && flag_code == CODE_64BIT |
d2224064 | 5968 | && !i.tm.opcode_modifier.norex64 |
46e883c5 | 5969 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
5970 | need rex64. */ |
5971 | && ! (i.operands == 2 | |
5972 | && i.tm.base_opcode == 0x90 | |
5973 | && i.tm.extension_opcode == None | |
5974 | && operand_type_equal (&i.types [0], &acc64) | |
5975 | && operand_type_equal (&i.types [1], &acc64))) | |
5976 | i.rex |= REX_W; | |
3e73aa7c | 5977 | |
d2224064 | 5978 | break; |
29b0f896 | 5979 | } |
7ecd2f8b | 5980 | |
29b0f896 AM |
5981 | return 1; |
5982 | } | |
3e73aa7c | 5983 | |
29b0f896 | 5984 | static int |
543613e9 | 5985 | check_byte_reg (void) |
29b0f896 AM |
5986 | { |
5987 | int op; | |
543613e9 | 5988 | |
29b0f896 AM |
5989 | for (op = i.operands; --op >= 0;) |
5990 | { | |
dc821c5f JB |
5991 | /* Skip non-register operands. */ |
5992 | if (!i.types[op].bitfield.reg) | |
5993 | continue; | |
5994 | ||
29b0f896 AM |
5995 | /* If this is an eight bit register, it's OK. If it's the 16 or |
5996 | 32 bit version of an eight bit register, we will just use the | |
5997 | low portion, and that's OK too. */ | |
dc821c5f | 5998 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
5999 | continue; |
6000 | ||
5a819eb9 JB |
6001 | /* I/O port address operands are OK too. */ |
6002 | if (i.tm.operand_types[op].bitfield.inoutportreg) | |
6003 | continue; | |
6004 | ||
9344ff29 L |
6005 | /* crc32 doesn't generate this warning. */ |
6006 | if (i.tm.base_opcode == 0xf20f38f0) | |
6007 | continue; | |
6008 | ||
dc821c5f JB |
6009 | if ((i.types[op].bitfield.word |
6010 | || i.types[op].bitfield.dword | |
6011 | || i.types[op].bitfield.qword) | |
5a819eb9 JB |
6012 | && i.op[op].regs->reg_num < 4 |
6013 | /* Prohibit these changes in 64bit mode, since the lowering | |
6014 | would be more complicated. */ | |
6015 | && flag_code != CODE_64BIT) | |
29b0f896 | 6016 | { |
29b0f896 | 6017 | #if REGISTER_WARNINGS |
5a819eb9 | 6018 | if (!quiet_warnings) |
a540244d L |
6019 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6020 | register_prefix, | |
dc821c5f | 6021 | (i.op[op].regs + (i.types[op].bitfield.word |
29b0f896 AM |
6022 | ? REGNAM_AL - REGNAM_AX |
6023 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 6024 | register_prefix, |
29b0f896 AM |
6025 | i.op[op].regs->reg_name, |
6026 | i.suffix); | |
6027 | #endif | |
6028 | continue; | |
6029 | } | |
6030 | /* Any other register is bad. */ | |
dc821c5f | 6031 | if (i.types[op].bitfield.reg |
40fb9820 | 6032 | || i.types[op].bitfield.regmmx |
1b54b8d7 | 6033 | || i.types[op].bitfield.regsimd |
40fb9820 L |
6034 | || i.types[op].bitfield.sreg2 |
6035 | || i.types[op].bitfield.sreg3 | |
6036 | || i.types[op].bitfield.control | |
6037 | || i.types[op].bitfield.debug | |
ca0d63fe | 6038 | || i.types[op].bitfield.test) |
29b0f896 | 6039 | { |
a540244d L |
6040 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6041 | register_prefix, | |
29b0f896 AM |
6042 | i.op[op].regs->reg_name, |
6043 | i.tm.name, | |
6044 | i.suffix); | |
6045 | return 0; | |
6046 | } | |
6047 | } | |
6048 | return 1; | |
6049 | } | |
6050 | ||
6051 | static int | |
e3bb37b5 | 6052 | check_long_reg (void) |
29b0f896 AM |
6053 | { |
6054 | int op; | |
6055 | ||
6056 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
6057 | /* Skip non-register operands. */ |
6058 | if (!i.types[op].bitfield.reg) | |
6059 | continue; | |
29b0f896 AM |
6060 | /* Reject eight bit registers, except where the template requires |
6061 | them. (eg. movzb) */ | |
dc821c5f JB |
6062 | else if (i.types[op].bitfield.byte |
6063 | && (i.tm.operand_types[op].bitfield.reg | |
6064 | || i.tm.operand_types[op].bitfield.acc) | |
6065 | && (i.tm.operand_types[op].bitfield.word | |
6066 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6067 | { |
a540244d L |
6068 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6069 | register_prefix, | |
29b0f896 AM |
6070 | i.op[op].regs->reg_name, |
6071 | i.tm.name, | |
6072 | i.suffix); | |
6073 | return 0; | |
6074 | } | |
e4630f71 | 6075 | /* Warn if the e prefix on a general reg is missing. */ |
29b0f896 | 6076 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
6077 | && i.types[op].bitfield.word |
6078 | && (i.tm.operand_types[op].bitfield.reg | |
6079 | || i.tm.operand_types[op].bitfield.acc) | |
6080 | && i.tm.operand_types[op].bitfield.dword) | |
29b0f896 AM |
6081 | { |
6082 | /* Prohibit these changes in the 64bit mode, since the | |
6083 | lowering is more complicated. */ | |
6084 | if (flag_code == CODE_64BIT) | |
252b5132 | 6085 | { |
2b5d6a91 | 6086 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6087 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6088 | i.suffix); |
6089 | return 0; | |
252b5132 | 6090 | } |
29b0f896 | 6091 | #if REGISTER_WARNINGS |
cecf1424 JB |
6092 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6093 | register_prefix, | |
6094 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
6095 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 | 6096 | #endif |
252b5132 | 6097 | } |
e4630f71 | 6098 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f JB |
6099 | else if (i.types[op].bitfield.qword |
6100 | && (i.tm.operand_types[op].bitfield.reg | |
6101 | || i.tm.operand_types[op].bitfield.acc) | |
6102 | && i.tm.operand_types[op].bitfield.dword) | |
252b5132 | 6103 | { |
34828aad | 6104 | if (intel_syntax |
ca61edf2 | 6105 | && i.tm.opcode_modifier.toqword |
1b54b8d7 | 6106 | && !i.types[0].bitfield.regsimd) |
34828aad | 6107 | { |
ca61edf2 | 6108 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
6109 | i.suffix = QWORD_MNEM_SUFFIX; |
6110 | } | |
6111 | else | |
6112 | { | |
2b5d6a91 | 6113 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6114 | register_prefix, i.op[op].regs->reg_name, |
6115 | i.suffix); | |
6116 | return 0; | |
6117 | } | |
29b0f896 AM |
6118 | } |
6119 | return 1; | |
6120 | } | |
252b5132 | 6121 | |
29b0f896 | 6122 | static int |
e3bb37b5 | 6123 | check_qword_reg (void) |
29b0f896 AM |
6124 | { |
6125 | int op; | |
252b5132 | 6126 | |
29b0f896 | 6127 | for (op = i.operands; --op >= 0; ) |
dc821c5f JB |
6128 | /* Skip non-register operands. */ |
6129 | if (!i.types[op].bitfield.reg) | |
6130 | continue; | |
29b0f896 AM |
6131 | /* Reject eight bit registers, except where the template requires |
6132 | them. (eg. movzb) */ | |
dc821c5f JB |
6133 | else if (i.types[op].bitfield.byte |
6134 | && (i.tm.operand_types[op].bitfield.reg | |
6135 | || i.tm.operand_types[op].bitfield.acc) | |
6136 | && (i.tm.operand_types[op].bitfield.word | |
6137 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6138 | { |
a540244d L |
6139 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6140 | register_prefix, | |
29b0f896 AM |
6141 | i.op[op].regs->reg_name, |
6142 | i.tm.name, | |
6143 | i.suffix); | |
6144 | return 0; | |
6145 | } | |
e4630f71 | 6146 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
6147 | else if ((i.types[op].bitfield.word |
6148 | || i.types[op].bitfield.dword) | |
6149 | && (i.tm.operand_types[op].bitfield.reg | |
6150 | || i.tm.operand_types[op].bitfield.acc) | |
6151 | && i.tm.operand_types[op].bitfield.qword) | |
29b0f896 AM |
6152 | { |
6153 | /* Prohibit these changes in the 64bit mode, since the | |
6154 | lowering is more complicated. */ | |
34828aad | 6155 | if (intel_syntax |
ca61edf2 | 6156 | && i.tm.opcode_modifier.todword |
1b54b8d7 | 6157 | && !i.types[0].bitfield.regsimd) |
34828aad | 6158 | { |
ca61edf2 | 6159 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
6160 | i.suffix = LONG_MNEM_SUFFIX; |
6161 | } | |
6162 | else | |
6163 | { | |
2b5d6a91 | 6164 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6165 | register_prefix, i.op[op].regs->reg_name, |
6166 | i.suffix); | |
6167 | return 0; | |
6168 | } | |
252b5132 | 6169 | } |
29b0f896 AM |
6170 | return 1; |
6171 | } | |
252b5132 | 6172 | |
29b0f896 | 6173 | static int |
e3bb37b5 | 6174 | check_word_reg (void) |
29b0f896 AM |
6175 | { |
6176 | int op; | |
6177 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
6178 | /* Skip non-register operands. */ |
6179 | if (!i.types[op].bitfield.reg) | |
6180 | continue; | |
29b0f896 AM |
6181 | /* Reject eight bit registers, except where the template requires |
6182 | them. (eg. movzb) */ | |
dc821c5f JB |
6183 | else if (i.types[op].bitfield.byte |
6184 | && (i.tm.operand_types[op].bitfield.reg | |
6185 | || i.tm.operand_types[op].bitfield.acc) | |
6186 | && (i.tm.operand_types[op].bitfield.word | |
6187 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6188 | { |
a540244d L |
6189 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6190 | register_prefix, | |
29b0f896 AM |
6191 | i.op[op].regs->reg_name, |
6192 | i.tm.name, | |
6193 | i.suffix); | |
6194 | return 0; | |
6195 | } | |
e4630f71 | 6196 | /* Warn if the e or r prefix on a general reg is present. */ |
29b0f896 | 6197 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
6198 | && (i.types[op].bitfield.dword |
6199 | || i.types[op].bitfield.qword) | |
6200 | && (i.tm.operand_types[op].bitfield.reg | |
6201 | || i.tm.operand_types[op].bitfield.acc) | |
6202 | && i.tm.operand_types[op].bitfield.word) | |
252b5132 | 6203 | { |
29b0f896 AM |
6204 | /* Prohibit these changes in the 64bit mode, since the |
6205 | lowering is more complicated. */ | |
6206 | if (flag_code == CODE_64BIT) | |
252b5132 | 6207 | { |
2b5d6a91 | 6208 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6209 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6210 | i.suffix); |
6211 | return 0; | |
252b5132 | 6212 | } |
29b0f896 | 6213 | #if REGISTER_WARNINGS |
cecf1424 JB |
6214 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6215 | register_prefix, | |
6216 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
6217 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 AM |
6218 | #endif |
6219 | } | |
6220 | return 1; | |
6221 | } | |
252b5132 | 6222 | |
29b0f896 | 6223 | static int |
40fb9820 | 6224 | update_imm (unsigned int j) |
29b0f896 | 6225 | { |
bc0844ae | 6226 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
6227 | if ((overlap.bitfield.imm8 |
6228 | || overlap.bitfield.imm8s | |
6229 | || overlap.bitfield.imm16 | |
6230 | || overlap.bitfield.imm32 | |
6231 | || overlap.bitfield.imm32s | |
6232 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
6233 | && !operand_type_equal (&overlap, &imm8) |
6234 | && !operand_type_equal (&overlap, &imm8s) | |
6235 | && !operand_type_equal (&overlap, &imm16) | |
6236 | && !operand_type_equal (&overlap, &imm32) | |
6237 | && !operand_type_equal (&overlap, &imm32s) | |
6238 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
6239 | { |
6240 | if (i.suffix) | |
6241 | { | |
40fb9820 L |
6242 | i386_operand_type temp; |
6243 | ||
0dfbf9d7 | 6244 | operand_type_set (&temp, 0); |
7ab9ffdd | 6245 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
6246 | { |
6247 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
6248 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
6249 | } | |
6250 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6251 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
6252 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6253 | { | |
6254 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
6255 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
6256 | } | |
6257 | else | |
6258 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
6259 | overlap = temp; | |
29b0f896 | 6260 | } |
0dfbf9d7 L |
6261 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
6262 | || operand_type_equal (&overlap, &imm16_32) | |
6263 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 6264 | { |
40fb9820 | 6265 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 6266 | overlap = imm16; |
40fb9820 | 6267 | else |
65da13b5 | 6268 | overlap = imm32s; |
29b0f896 | 6269 | } |
0dfbf9d7 L |
6270 | if (!operand_type_equal (&overlap, &imm8) |
6271 | && !operand_type_equal (&overlap, &imm8s) | |
6272 | && !operand_type_equal (&overlap, &imm16) | |
6273 | && !operand_type_equal (&overlap, &imm32) | |
6274 | && !operand_type_equal (&overlap, &imm32s) | |
6275 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 6276 | { |
4eed87de AM |
6277 | as_bad (_("no instruction mnemonic suffix given; " |
6278 | "can't determine immediate size")); | |
29b0f896 AM |
6279 | return 0; |
6280 | } | |
6281 | } | |
40fb9820 | 6282 | i.types[j] = overlap; |
29b0f896 | 6283 | |
40fb9820 L |
6284 | return 1; |
6285 | } | |
6286 | ||
6287 | static int | |
6288 | finalize_imm (void) | |
6289 | { | |
bc0844ae | 6290 | unsigned int j, n; |
29b0f896 | 6291 | |
bc0844ae L |
6292 | /* Update the first 2 immediate operands. */ |
6293 | n = i.operands > 2 ? 2 : i.operands; | |
6294 | if (n) | |
6295 | { | |
6296 | for (j = 0; j < n; j++) | |
6297 | if (update_imm (j) == 0) | |
6298 | return 0; | |
40fb9820 | 6299 | |
bc0844ae L |
6300 | /* The 3rd operand can't be immediate operand. */ |
6301 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
6302 | } | |
29b0f896 AM |
6303 | |
6304 | return 1; | |
6305 | } | |
6306 | ||
6307 | static int | |
e3bb37b5 | 6308 | process_operands (void) |
29b0f896 AM |
6309 | { |
6310 | /* Default segment register this instruction will use for memory | |
6311 | accesses. 0 means unknown. This is only for optimizing out | |
6312 | unnecessary segment overrides. */ | |
6313 | const seg_entry *default_seg = 0; | |
6314 | ||
2426c15f | 6315 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 6316 | { |
91d6fa6a NC |
6317 | unsigned int dupl = i.operands; |
6318 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
6319 | unsigned int j; |
6320 | ||
c0f3af97 | 6321 | /* The destination must be an xmm register. */ |
9c2799c2 | 6322 | gas_assert (i.reg_operands |
91d6fa6a | 6323 | && MAX_OPERANDS > dupl |
7ab9ffdd | 6324 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 6325 | |
1b54b8d7 JB |
6326 | if (i.tm.operand_types[0].bitfield.acc |
6327 | && i.tm.operand_types[0].bitfield.xmmword) | |
e2ec9d29 | 6328 | { |
8cd7925b | 6329 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
6330 | { |
6331 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
6332 | sources. */ | |
1b54b8d7 JB |
6333 | i.tm.operand_types[0].bitfield.acc = 0; |
6334 | i.tm.operand_types[0].bitfield.regsimd = 1; | |
c0f3af97 L |
6335 | goto duplicate; |
6336 | } | |
e2ec9d29 | 6337 | else |
c0f3af97 L |
6338 | { |
6339 | /* We remove the first xmm0 and keep the number of | |
6340 | operands unchanged, which in fact duplicates the | |
6341 | destination. */ | |
6342 | for (j = 1; j < i.operands; j++) | |
6343 | { | |
6344 | i.op[j - 1] = i.op[j]; | |
6345 | i.types[j - 1] = i.types[j]; | |
6346 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
6347 | } | |
6348 | } | |
6349 | } | |
6350 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 6351 | { |
91d6fa6a | 6352 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
6353 | && (i.tm.opcode_modifier.vexsources |
6354 | == VEX3SOURCES)); | |
c0f3af97 L |
6355 | |
6356 | /* Add the implicit xmm0 for instructions with VEX prefix | |
6357 | and 3 sources. */ | |
6358 | for (j = i.operands; j > 0; j--) | |
6359 | { | |
6360 | i.op[j] = i.op[j - 1]; | |
6361 | i.types[j] = i.types[j - 1]; | |
6362 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
6363 | } | |
6364 | i.op[0].regs | |
6365 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 6366 | i.types[0] = regxmm; |
c0f3af97 L |
6367 | i.tm.operand_types[0] = regxmm; |
6368 | ||
6369 | i.operands += 2; | |
6370 | i.reg_operands += 2; | |
6371 | i.tm.operands += 2; | |
6372 | ||
91d6fa6a | 6373 | dupl++; |
c0f3af97 | 6374 | dest++; |
91d6fa6a NC |
6375 | i.op[dupl] = i.op[dest]; |
6376 | i.types[dupl] = i.types[dest]; | |
6377 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
e2ec9d29 | 6378 | } |
c0f3af97 L |
6379 | else |
6380 | { | |
6381 | duplicate: | |
6382 | i.operands++; | |
6383 | i.reg_operands++; | |
6384 | i.tm.operands++; | |
6385 | ||
91d6fa6a NC |
6386 | i.op[dupl] = i.op[dest]; |
6387 | i.types[dupl] = i.types[dest]; | |
6388 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
c0f3af97 L |
6389 | } |
6390 | ||
6391 | if (i.tm.opcode_modifier.immext) | |
6392 | process_immext (); | |
6393 | } | |
1b54b8d7 JB |
6394 | else if (i.tm.operand_types[0].bitfield.acc |
6395 | && i.tm.operand_types[0].bitfield.xmmword) | |
c0f3af97 L |
6396 | { |
6397 | unsigned int j; | |
6398 | ||
9fcfb3d7 L |
6399 | for (j = 1; j < i.operands; j++) |
6400 | { | |
6401 | i.op[j - 1] = i.op[j]; | |
6402 | i.types[j - 1] = i.types[j]; | |
6403 | ||
6404 | /* We need to adjust fields in i.tm since they are used by | |
6405 | build_modrm_byte. */ | |
6406 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
6407 | } | |
6408 | ||
e2ec9d29 L |
6409 | i.operands--; |
6410 | i.reg_operands--; | |
e2ec9d29 L |
6411 | i.tm.operands--; |
6412 | } | |
920d2ddc IT |
6413 | else if (i.tm.opcode_modifier.implicitquadgroup) |
6414 | { | |
a477a8c4 JB |
6415 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
6416 | ||
920d2ddc | 6417 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
10c17abd | 6418 | gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd); |
a477a8c4 JB |
6419 | regnum = register_number (i.op[1].regs); |
6420 | first_reg_in_group = regnum & ~3; | |
6421 | last_reg_in_group = first_reg_in_group + 3; | |
6422 | if (regnum != first_reg_in_group) | |
6423 | as_warn (_("source register `%s%s' implicitly denotes" | |
6424 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
6425 | register_prefix, i.op[1].regs->reg_name, | |
6426 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
6427 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
6428 | i.tm.name); | |
6429 | } | |
e2ec9d29 L |
6430 | else if (i.tm.opcode_modifier.regkludge) |
6431 | { | |
6432 | /* The imul $imm, %reg instruction is converted into | |
6433 | imul $imm, %reg, %reg, and the clr %reg instruction | |
6434 | is converted into xor %reg, %reg. */ | |
6435 | ||
6436 | unsigned int first_reg_op; | |
6437 | ||
6438 | if (operand_type_check (i.types[0], reg)) | |
6439 | first_reg_op = 0; | |
6440 | else | |
6441 | first_reg_op = 1; | |
6442 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 6443 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 6444 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
6445 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
6446 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
6447 | i.operands++; | |
6448 | i.reg_operands++; | |
29b0f896 AM |
6449 | } |
6450 | ||
40fb9820 | 6451 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 6452 | { |
40fb9820 L |
6453 | if (i.types[0].bitfield.sreg2 |
6454 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 6455 | { |
4eed87de AM |
6456 | if (i.tm.base_opcode == POP_SEG_SHORT |
6457 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 6458 | { |
a87af027 | 6459 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 6460 | return 0; |
29b0f896 | 6461 | } |
4eed87de AM |
6462 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
6463 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6464 | i.rex |= REX_B; |
4eed87de AM |
6465 | } |
6466 | else | |
6467 | { | |
7ab9ffdd | 6468 | /* The register or float register operand is in operand |
85f10a01 | 6469 | 0 or 1. */ |
40fb9820 | 6470 | unsigned int op; |
7ab9ffdd | 6471 | |
ca0d63fe | 6472 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte) |
7ab9ffdd L |
6473 | || operand_type_check (i.types[0], reg)) |
6474 | op = 0; | |
6475 | else | |
6476 | op = 1; | |
4eed87de AM |
6477 | /* Register goes in low 3 bits of opcode. */ |
6478 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
6479 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6480 | i.rex |= REX_B; |
40fb9820 | 6481 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 6482 | { |
4eed87de AM |
6483 | /* Warn about some common errors, but press on regardless. |
6484 | The first case can be generated by gcc (<= 2.8.1). */ | |
6485 | if (i.operands == 2) | |
6486 | { | |
6487 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d | 6488 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
d8a1b51e JB |
6489 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
6490 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
4eed87de AM |
6491 | } |
6492 | else | |
6493 | { | |
6494 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
6495 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
6496 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 6497 | } |
29b0f896 AM |
6498 | } |
6499 | } | |
6500 | } | |
40fb9820 | 6501 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
6502 | { |
6503 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
6504 | must be put into the modrm byte). Now, we make the modrm and |
6505 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
6506 | |
6507 | default_seg = build_modrm_byte (); | |
6508 | } | |
8a2ed489 | 6509 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
6510 | { |
6511 | default_seg = &ds; | |
6512 | } | |
40fb9820 | 6513 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
6514 | { |
6515 | /* For the string instructions that allow a segment override | |
6516 | on one of their operands, the default segment is ds. */ | |
6517 | default_seg = &ds; | |
6518 | } | |
6519 | ||
75178d9d L |
6520 | if (i.tm.base_opcode == 0x8d /* lea */ |
6521 | && i.seg[0] | |
6522 | && !quiet_warnings) | |
30123838 | 6523 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
6524 | |
6525 | /* If a segment was explicitly specified, and the specified segment | |
6526 | is not the default, use an opcode prefix to select it. If we | |
6527 | never figured out what the default segment is, then default_seg | |
6528 | will be zero at this point, and the specified segment prefix will | |
6529 | always be used. */ | |
29b0f896 AM |
6530 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
6531 | { | |
6532 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
6533 | return 0; | |
6534 | } | |
6535 | return 1; | |
6536 | } | |
6537 | ||
6538 | static const seg_entry * | |
e3bb37b5 | 6539 | build_modrm_byte (void) |
29b0f896 AM |
6540 | { |
6541 | const seg_entry *default_seg = 0; | |
c0f3af97 | 6542 | unsigned int source, dest; |
8cd7925b | 6543 | int vex_3_sources; |
c0f3af97 L |
6544 | |
6545 | /* The first operand of instructions with VEX prefix and 3 sources | |
6546 | must be VEX_Imm4. */ | |
8cd7925b | 6547 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
6548 | if (vex_3_sources) |
6549 | { | |
91d6fa6a | 6550 | unsigned int nds, reg_slot; |
4c2c6516 | 6551 | expressionS *exp; |
c0f3af97 | 6552 | |
922d8de8 | 6553 | if (i.tm.opcode_modifier.veximmext |
a683cc34 SP |
6554 | && i.tm.opcode_modifier.immext) |
6555 | { | |
6556 | dest = i.operands - 2; | |
6557 | gas_assert (dest == 3); | |
6558 | } | |
922d8de8 | 6559 | else |
a683cc34 | 6560 | dest = i.operands - 1; |
c0f3af97 | 6561 | nds = dest - 1; |
922d8de8 | 6562 | |
a683cc34 SP |
6563 | /* There are 2 kinds of instructions: |
6564 | 1. 5 operands: 4 register operands or 3 register operands | |
6565 | plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and | |
43234a1e L |
6566 | VexW0 or VexW1. The destination must be either XMM, YMM or |
6567 | ZMM register. | |
a683cc34 SP |
6568 | 2. 4 operands: 4 register operands or 3 register operands |
6569 | plus 1 memory operand, VexXDS, and VexImmExt */ | |
922d8de8 | 6570 | gas_assert ((i.reg_operands == 4 |
a683cc34 SP |
6571 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
6572 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
6573 | && (i.tm.opcode_modifier.veximmext | |
6574 | || (i.imm_operands == 1 | |
6575 | && i.types[0].bitfield.vec_imm4 | |
6576 | && (i.tm.opcode_modifier.vexw == VEXW0 | |
6577 | || i.tm.opcode_modifier.vexw == VEXW1) | |
10c17abd | 6578 | && i.tm.operand_types[dest].bitfield.regsimd))); |
a683cc34 SP |
6579 | |
6580 | if (i.imm_operands == 0) | |
6581 | { | |
6582 | /* When there is no immediate operand, generate an 8bit | |
6583 | immediate operand to encode the first operand. */ | |
6584 | exp = &im_expressions[i.imm_operands++]; | |
6585 | i.op[i.operands].imms = exp; | |
6586 | i.types[i.operands] = imm8; | |
6587 | i.operands++; | |
6588 | /* If VexW1 is set, the first operand is the source and | |
6589 | the second operand is encoded in the immediate operand. */ | |
6590 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
6591 | { | |
6592 | source = 0; | |
6593 | reg_slot = 1; | |
6594 | } | |
6595 | else | |
6596 | { | |
6597 | source = 1; | |
6598 | reg_slot = 0; | |
6599 | } | |
6600 | ||
6601 | /* FMA swaps REG and NDS. */ | |
6602 | if (i.tm.cpu_flags.bitfield.cpufma) | |
6603 | { | |
6604 | unsigned int tmp; | |
6605 | tmp = reg_slot; | |
6606 | reg_slot = nds; | |
6607 | nds = tmp; | |
6608 | } | |
6609 | ||
10c17abd | 6610 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); |
a683cc34 | 6611 | exp->X_op = O_constant; |
4c692bc7 | 6612 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; |
43234a1e L |
6613 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
6614 | } | |
922d8de8 | 6615 | else |
a683cc34 SP |
6616 | { |
6617 | unsigned int imm_slot; | |
6618 | ||
6619 | if (i.tm.opcode_modifier.vexw == VEXW0) | |
6620 | { | |
6621 | /* If VexW0 is set, the third operand is the source and | |
6622 | the second operand is encoded in the immediate | |
6623 | operand. */ | |
6624 | source = 2; | |
6625 | reg_slot = 1; | |
6626 | } | |
6627 | else | |
6628 | { | |
6629 | /* VexW1 is set, the second operand is the source and | |
6630 | the third operand is encoded in the immediate | |
6631 | operand. */ | |
6632 | source = 1; | |
6633 | reg_slot = 2; | |
6634 | } | |
6635 | ||
6636 | if (i.tm.opcode_modifier.immext) | |
6637 | { | |
33eaf5de | 6638 | /* When ImmExt is set, the immediate byte is the last |
a683cc34 SP |
6639 | operand. */ |
6640 | imm_slot = i.operands - 1; | |
6641 | source--; | |
6642 | reg_slot--; | |
6643 | } | |
6644 | else | |
6645 | { | |
6646 | imm_slot = 0; | |
6647 | ||
6648 | /* Turn on Imm8 so that output_imm will generate it. */ | |
6649 | i.types[imm_slot].bitfield.imm8 = 1; | |
6650 | } | |
6651 | ||
10c17abd | 6652 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); |
a683cc34 | 6653 | i.op[imm_slot].imms->X_add_number |
4c692bc7 | 6654 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 6655 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
a683cc34 SP |
6656 | } |
6657 | ||
10c17abd | 6658 | gas_assert (i.tm.operand_types[nds].bitfield.regsimd); |
dae39acc | 6659 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
6660 | } |
6661 | else | |
6662 | source = dest = 0; | |
29b0f896 AM |
6663 | |
6664 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
6665 | implicit registers do not count. If there are 3 register |
6666 | operands, it must be a instruction with VexNDS. For a | |
6667 | instruction with VexNDD, the destination register is encoded | |
6668 | in VEX prefix. If there are 4 register operands, it must be | |
6669 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
6670 | if (i.mem_operands == 0 |
6671 | && ((i.reg_operands == 2 | |
2426c15f | 6672 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 6673 | || (i.reg_operands == 3 |
2426c15f | 6674 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 6675 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 6676 | { |
cab737b9 L |
6677 | switch (i.operands) |
6678 | { | |
6679 | case 2: | |
6680 | source = 0; | |
6681 | break; | |
6682 | case 3: | |
c81128dc L |
6683 | /* When there are 3 operands, one of them may be immediate, |
6684 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
6685 | the first operand must be shift count register (cl) or it |
6686 | is an instruction with VexNDS. */ | |
9c2799c2 | 6687 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 6688 | || (i.imm_operands == 0 |
2426c15f | 6689 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd | 6690 | || i.types[0].bitfield.shiftcount))); |
40fb9820 L |
6691 | if (operand_type_check (i.types[0], imm) |
6692 | || i.types[0].bitfield.shiftcount) | |
6693 | source = 1; | |
6694 | else | |
6695 | source = 0; | |
cab737b9 L |
6696 | break; |
6697 | case 4: | |
368d64cc L |
6698 | /* When there are 4 operands, the first two must be 8bit |
6699 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
6700 | one. |
6701 | ||
6702 | For instructions with VexNDS, if the first operand | |
6703 | an imm8, the source operand is the 2nd one. If the last | |
6704 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 6705 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
6706 | && i.types[0].bitfield.imm8 |
6707 | && i.types[1].bitfield.imm8) | |
2426c15f | 6708 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
6709 | && i.imm_operands == 1 |
6710 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
6711 | || i.types[i.operands - 1].bitfield.imm8 |
6712 | || i.rounding))); | |
9f2670f2 L |
6713 | if (i.imm_operands == 2) |
6714 | source = 2; | |
6715 | else | |
c0f3af97 L |
6716 | { |
6717 | if (i.types[0].bitfield.imm8) | |
6718 | source = 1; | |
6719 | else | |
6720 | source = 0; | |
6721 | } | |
c0f3af97 L |
6722 | break; |
6723 | case 5: | |
e771e7c9 | 6724 | if (is_evex_encoding (&i.tm)) |
43234a1e L |
6725 | { |
6726 | /* For EVEX instructions, when there are 5 operands, the | |
6727 | first one must be immediate operand. If the second one | |
6728 | is immediate operand, the source operand is the 3th | |
6729 | one. If the last one is immediate operand, the source | |
6730 | operand is the 2nd one. */ | |
6731 | gas_assert (i.imm_operands == 2 | |
6732 | && i.tm.opcode_modifier.sae | |
6733 | && operand_type_check (i.types[0], imm)); | |
6734 | if (operand_type_check (i.types[1], imm)) | |
6735 | source = 2; | |
6736 | else if (operand_type_check (i.types[4], imm)) | |
6737 | source = 1; | |
6738 | else | |
6739 | abort (); | |
6740 | } | |
cab737b9 L |
6741 | break; |
6742 | default: | |
6743 | abort (); | |
6744 | } | |
6745 | ||
c0f3af97 L |
6746 | if (!vex_3_sources) |
6747 | { | |
6748 | dest = source + 1; | |
6749 | ||
43234a1e L |
6750 | /* RC/SAE operand could be between DEST and SRC. That happens |
6751 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
6752 | register. */ | |
6753 | if (i.rounding && i.rounding->operand == (int) dest) | |
6754 | dest++; | |
6755 | ||
2426c15f | 6756 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 6757 | { |
43234a1e | 6758 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 6759 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
43234a1e L |
6760 | register. It is encoded in VEX prefix. We need to |
6761 | clear RegMem bit before calling operand_type_equal. */ | |
f12dc422 L |
6762 | |
6763 | i386_operand_type op; | |
6764 | unsigned int vvvv; | |
6765 | ||
6766 | /* Check register-only source operand when two source | |
6767 | operands are swapped. */ | |
6768 | if (!i.tm.operand_types[source].bitfield.baseindex | |
6769 | && i.tm.operand_types[dest].bitfield.baseindex) | |
6770 | { | |
6771 | vvvv = source; | |
6772 | source = dest; | |
6773 | } | |
6774 | else | |
6775 | vvvv = dest; | |
6776 | ||
6777 | op = i.tm.operand_types[vvvv]; | |
fa99fab2 | 6778 | op.bitfield.regmem = 0; |
c0f3af97 | 6779 | if ((dest + 1) >= i.operands |
dc821c5f JB |
6780 | || ((!op.bitfield.reg |
6781 | || (!op.bitfield.dword && !op.bitfield.qword)) | |
10c17abd | 6782 | && !op.bitfield.regsimd |
43234a1e | 6783 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 6784 | abort (); |
f12dc422 | 6785 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
6786 | dest++; |
6787 | } | |
6788 | } | |
29b0f896 AM |
6789 | |
6790 | i.rm.mode = 3; | |
6791 | /* One of the register operands will be encoded in the i.tm.reg | |
6792 | field, the other in the combined i.tm.mode and i.tm.regmem | |
6793 | fields. If no form of this instruction supports a memory | |
6794 | destination operand, then we assume the source operand may | |
6795 | sometimes be a memory operand and so we need to store the | |
6796 | destination in the i.rm.reg field. */ | |
40fb9820 L |
6797 | if (!i.tm.operand_types[dest].bitfield.regmem |
6798 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
6799 | { |
6800 | i.rm.reg = i.op[dest].regs->reg_num; | |
6801 | i.rm.regmem = i.op[source].regs->reg_num; | |
6802 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6803 | i.rex |= REX_R; |
43234a1e L |
6804 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
6805 | i.vrex |= REX_R; | |
29b0f896 | 6806 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 6807 | i.rex |= REX_B; |
43234a1e L |
6808 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
6809 | i.vrex |= REX_B; | |
29b0f896 AM |
6810 | } |
6811 | else | |
6812 | { | |
6813 | i.rm.reg = i.op[source].regs->reg_num; | |
6814 | i.rm.regmem = i.op[dest].regs->reg_num; | |
6815 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6816 | i.rex |= REX_B; |
43234a1e L |
6817 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
6818 | i.vrex |= REX_B; | |
29b0f896 | 6819 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 6820 | i.rex |= REX_R; |
43234a1e L |
6821 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
6822 | i.vrex |= REX_R; | |
29b0f896 | 6823 | } |
161a04f6 | 6824 | if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) |
c4a530c5 | 6825 | { |
40fb9820 L |
6826 | if (!i.types[0].bitfield.control |
6827 | && !i.types[1].bitfield.control) | |
c4a530c5 | 6828 | abort (); |
161a04f6 | 6829 | i.rex &= ~(REX_R | REX_B); |
c4a530c5 JB |
6830 | add_prefix (LOCK_PREFIX_OPCODE); |
6831 | } | |
29b0f896 AM |
6832 | } |
6833 | else | |
6834 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
6835 | unsigned int mem; |
6836 | ||
29b0f896 AM |
6837 | if (i.mem_operands) |
6838 | { | |
6839 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 6840 | unsigned int op; |
4eed87de | 6841 | |
7ab9ffdd L |
6842 | for (op = 0; op < i.operands; op++) |
6843 | if (operand_type_check (i.types[op], anymem)) | |
6844 | break; | |
7ab9ffdd | 6845 | gas_assert (op < i.operands); |
29b0f896 | 6846 | |
6c30d220 L |
6847 | if (i.tm.opcode_modifier.vecsib) |
6848 | { | |
6849 | if (i.index_reg->reg_num == RegEiz | |
6850 | || i.index_reg->reg_num == RegRiz) | |
6851 | abort (); | |
6852 | ||
6853 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
6854 | if (!i.base_reg) | |
6855 | { | |
6856 | i.sib.base = NO_BASE_REGISTER; | |
6857 | i.sib.scale = i.log2_scale_factor; | |
6858 | i.types[op].bitfield.disp8 = 0; | |
6859 | i.types[op].bitfield.disp16 = 0; | |
6860 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 6861 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
6862 | { |
6863 | /* Must be 32 bit */ | |
6864 | i.types[op].bitfield.disp32 = 1; | |
6865 | i.types[op].bitfield.disp32s = 0; | |
6866 | } | |
6867 | else | |
6868 | { | |
6869 | i.types[op].bitfield.disp32 = 0; | |
6870 | i.types[op].bitfield.disp32s = 1; | |
6871 | } | |
6872 | } | |
6873 | i.sib.index = i.index_reg->reg_num; | |
6874 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
6875 | i.rex |= REX_X; | |
43234a1e L |
6876 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
6877 | i.vrex |= REX_X; | |
6c30d220 L |
6878 | } |
6879 | ||
29b0f896 AM |
6880 | default_seg = &ds; |
6881 | ||
6882 | if (i.base_reg == 0) | |
6883 | { | |
6884 | i.rm.mode = 0; | |
6885 | if (!i.disp_operands) | |
9bb129e8 | 6886 | fake_zero_displacement = 1; |
29b0f896 AM |
6887 | if (i.index_reg == 0) |
6888 | { | |
73053c1f JB |
6889 | i386_operand_type newdisp; |
6890 | ||
6c30d220 | 6891 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 6892 | /* Operand is just <disp> */ |
20f0a1fc | 6893 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
6894 | { |
6895 | /* 64bit mode overwrites the 32bit absolute | |
6896 | addressing by RIP relative addressing and | |
6897 | absolute addressing is encoded by one of the | |
6898 | redundant SIB forms. */ | |
6899 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
6900 | i.sib.base = NO_BASE_REGISTER; | |
6901 | i.sib.index = NO_INDEX_REGISTER; | |
73053c1f | 6902 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
20f0a1fc | 6903 | } |
fc225355 L |
6904 | else if ((flag_code == CODE_16BIT) |
6905 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
6906 | { |
6907 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 6908 | newdisp = disp16; |
20f0a1fc NC |
6909 | } |
6910 | else | |
6911 | { | |
6912 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 6913 | newdisp = disp32; |
29b0f896 | 6914 | } |
73053c1f JB |
6915 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
6916 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 6917 | } |
6c30d220 | 6918 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 6919 | { |
6c30d220 | 6920 | /* !i.base_reg && i.index_reg */ |
db51cc60 L |
6921 | if (i.index_reg->reg_num == RegEiz |
6922 | || i.index_reg->reg_num == RegRiz) | |
6923 | i.sib.index = NO_INDEX_REGISTER; | |
6924 | else | |
6925 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
6926 | i.sib.base = NO_BASE_REGISTER; |
6927 | i.sib.scale = i.log2_scale_factor; | |
6928 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
6929 | i.types[op].bitfield.disp8 = 0; |
6930 | i.types[op].bitfield.disp16 = 0; | |
6931 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 6932 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
6933 | { |
6934 | /* Must be 32 bit */ | |
6935 | i.types[op].bitfield.disp32 = 1; | |
6936 | i.types[op].bitfield.disp32s = 0; | |
6937 | } | |
29b0f896 | 6938 | else |
40fb9820 L |
6939 | { |
6940 | i.types[op].bitfield.disp32 = 0; | |
6941 | i.types[op].bitfield.disp32s = 1; | |
6942 | } | |
29b0f896 | 6943 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 6944 | i.rex |= REX_X; |
29b0f896 AM |
6945 | } |
6946 | } | |
6947 | /* RIP addressing for 64bit mode. */ | |
9a04903e JB |
6948 | else if (i.base_reg->reg_num == RegRip || |
6949 | i.base_reg->reg_num == RegEip) | |
29b0f896 | 6950 | { |
6c30d220 | 6951 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 6952 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
6953 | i.types[op].bitfield.disp8 = 0; |
6954 | i.types[op].bitfield.disp16 = 0; | |
6955 | i.types[op].bitfield.disp32 = 0; | |
6956 | i.types[op].bitfield.disp32s = 1; | |
6957 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 6958 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
6959 | if (! i.disp_operands) |
6960 | fake_zero_displacement = 1; | |
29b0f896 | 6961 | } |
dc821c5f | 6962 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 6963 | { |
6c30d220 | 6964 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
6965 | switch (i.base_reg->reg_num) |
6966 | { | |
6967 | case 3: /* (%bx) */ | |
6968 | if (i.index_reg == 0) | |
6969 | i.rm.regmem = 7; | |
6970 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
6971 | i.rm.regmem = i.index_reg->reg_num - 6; | |
6972 | break; | |
6973 | case 5: /* (%bp) */ | |
6974 | default_seg = &ss; | |
6975 | if (i.index_reg == 0) | |
6976 | { | |
6977 | i.rm.regmem = 6; | |
40fb9820 | 6978 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
6979 | { |
6980 | /* fake (%bp) into 0(%bp) */ | |
b5014f7a | 6981 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 6982 | fake_zero_displacement = 1; |
29b0f896 AM |
6983 | } |
6984 | } | |
6985 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
6986 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
6987 | break; | |
6988 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
6989 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
6990 | } | |
6991 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
6992 | } | |
6993 | else /* i.base_reg and 32/64 bit mode */ | |
6994 | { | |
6995 | if (flag_code == CODE_64BIT | |
40fb9820 L |
6996 | && operand_type_check (i.types[op], disp)) |
6997 | { | |
73053c1f JB |
6998 | i.types[op].bitfield.disp16 = 0; |
6999 | i.types[op].bitfield.disp64 = 0; | |
40fb9820 | 7000 | if (i.prefix[ADDR_PREFIX] == 0) |
73053c1f JB |
7001 | { |
7002 | i.types[op].bitfield.disp32 = 0; | |
7003 | i.types[op].bitfield.disp32s = 1; | |
7004 | } | |
40fb9820 | 7005 | else |
73053c1f JB |
7006 | { |
7007 | i.types[op].bitfield.disp32 = 1; | |
7008 | i.types[op].bitfield.disp32s = 0; | |
7009 | } | |
40fb9820 | 7010 | } |
20f0a1fc | 7011 | |
6c30d220 L |
7012 | if (!i.tm.opcode_modifier.vecsib) |
7013 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 7014 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7015 | i.rex |= REX_B; |
29b0f896 AM |
7016 | i.sib.base = i.base_reg->reg_num; |
7017 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
7018 | complications. */ | |
848930b2 JB |
7019 | if (!(i.base_reg->reg_flags & RegRex) |
7020 | && (i.base_reg->reg_num == EBP_REG_NUM | |
7021 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 7022 | default_seg = &ss; |
848930b2 | 7023 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 7024 | { |
848930b2 | 7025 | fake_zero_displacement = 1; |
b5014f7a | 7026 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
7027 | } |
7028 | i.sib.scale = i.log2_scale_factor; | |
7029 | if (i.index_reg == 0) | |
7030 | { | |
6c30d220 | 7031 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7032 | /* <disp>(%esp) becomes two byte modrm with no index |
7033 | register. We've already stored the code for esp | |
7034 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
7035 | Any base register besides %esp will not use the | |
7036 | extra modrm byte. */ | |
7037 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 7038 | } |
6c30d220 | 7039 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7040 | { |
db51cc60 L |
7041 | if (i.index_reg->reg_num == RegEiz |
7042 | || i.index_reg->reg_num == RegRiz) | |
7043 | i.sib.index = NO_INDEX_REGISTER; | |
7044 | else | |
7045 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7046 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
7047 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 7048 | i.rex |= REX_X; |
29b0f896 | 7049 | } |
67a4f2b7 AO |
7050 | |
7051 | if (i.disp_operands | |
7052 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
7053 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
7054 | i.rm.mode = 0; | |
7055 | else | |
a501d77e L |
7056 | { |
7057 | if (!fake_zero_displacement | |
7058 | && !i.disp_operands | |
7059 | && i.disp_encoding) | |
7060 | { | |
7061 | fake_zero_displacement = 1; | |
7062 | if (i.disp_encoding == disp_encoding_8bit) | |
7063 | i.types[op].bitfield.disp8 = 1; | |
7064 | else | |
7065 | i.types[op].bitfield.disp32 = 1; | |
7066 | } | |
7067 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7068 | } | |
29b0f896 | 7069 | } |
252b5132 | 7070 | |
29b0f896 AM |
7071 | if (fake_zero_displacement) |
7072 | { | |
7073 | /* Fakes a zero displacement assuming that i.types[op] | |
7074 | holds the correct displacement size. */ | |
7075 | expressionS *exp; | |
7076 | ||
9c2799c2 | 7077 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
7078 | exp = &disp_expressions[i.disp_operands++]; |
7079 | i.op[op].disps = exp; | |
7080 | exp->X_op = O_constant; | |
7081 | exp->X_add_number = 0; | |
7082 | exp->X_add_symbol = (symbolS *) 0; | |
7083 | exp->X_op_symbol = (symbolS *) 0; | |
7084 | } | |
c0f3af97 L |
7085 | |
7086 | mem = op; | |
29b0f896 | 7087 | } |
c0f3af97 L |
7088 | else |
7089 | mem = ~0; | |
252b5132 | 7090 | |
8c43a48b | 7091 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
7092 | { |
7093 | if (operand_type_check (i.types[0], imm)) | |
7094 | i.vex.register_specifier = NULL; | |
7095 | else | |
7096 | { | |
7097 | /* VEX.vvvv encodes one of the sources when the first | |
7098 | operand is not an immediate. */ | |
1ef99a7b | 7099 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7100 | i.vex.register_specifier = i.op[0].regs; |
7101 | else | |
7102 | i.vex.register_specifier = i.op[1].regs; | |
7103 | } | |
7104 | ||
7105 | /* Destination is a XMM register encoded in the ModRM.reg | |
7106 | and VEX.R bit. */ | |
7107 | i.rm.reg = i.op[2].regs->reg_num; | |
7108 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
7109 | i.rex |= REX_R; | |
7110 | ||
7111 | /* ModRM.rm and VEX.B encodes the other source. */ | |
7112 | if (!i.mem_operands) | |
7113 | { | |
7114 | i.rm.mode = 3; | |
7115 | ||
1ef99a7b | 7116 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7117 | i.rm.regmem = i.op[1].regs->reg_num; |
7118 | else | |
7119 | i.rm.regmem = i.op[0].regs->reg_num; | |
7120 | ||
7121 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7122 | i.rex |= REX_B; | |
7123 | } | |
7124 | } | |
2426c15f | 7125 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
7126 | { |
7127 | i.vex.register_specifier = i.op[2].regs; | |
7128 | if (!i.mem_operands) | |
7129 | { | |
7130 | i.rm.mode = 3; | |
7131 | i.rm.regmem = i.op[1].regs->reg_num; | |
7132 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7133 | i.rex |= REX_B; | |
7134 | } | |
7135 | } | |
29b0f896 AM |
7136 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
7137 | (if any) based on i.tm.extension_opcode. Again, we must be | |
7138 | careful to make sure that segment/control/debug/test/MMX | |
7139 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 7140 | else if (i.reg_operands) |
29b0f896 | 7141 | { |
99018f42 | 7142 | unsigned int op; |
7ab9ffdd L |
7143 | unsigned int vex_reg = ~0; |
7144 | ||
7145 | for (op = 0; op < i.operands; op++) | |
dc821c5f | 7146 | if (i.types[op].bitfield.reg |
7ab9ffdd | 7147 | || i.types[op].bitfield.regmmx |
1b54b8d7 | 7148 | || i.types[op].bitfield.regsimd |
7e8b059b | 7149 | || i.types[op].bitfield.regbnd |
43234a1e | 7150 | || i.types[op].bitfield.regmask |
7ab9ffdd L |
7151 | || i.types[op].bitfield.sreg2 |
7152 | || i.types[op].bitfield.sreg3 | |
7153 | || i.types[op].bitfield.control | |
7154 | || i.types[op].bitfield.debug | |
7155 | || i.types[op].bitfield.test) | |
7156 | break; | |
c0209578 | 7157 | |
7ab9ffdd L |
7158 | if (vex_3_sources) |
7159 | op = dest; | |
2426c15f | 7160 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
7161 | { |
7162 | /* For instructions with VexNDS, the register-only | |
7163 | source operand is encoded in VEX prefix. */ | |
7164 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 7165 | |
7ab9ffdd | 7166 | if (op > mem) |
c0f3af97 | 7167 | { |
7ab9ffdd L |
7168 | vex_reg = op++; |
7169 | gas_assert (op < i.operands); | |
c0f3af97 L |
7170 | } |
7171 | else | |
c0f3af97 | 7172 | { |
f12dc422 L |
7173 | /* Check register-only source operand when two source |
7174 | operands are swapped. */ | |
7175 | if (!i.tm.operand_types[op].bitfield.baseindex | |
7176 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
7177 | { | |
7178 | vex_reg = op; | |
7179 | op += 2; | |
7180 | gas_assert (mem == (vex_reg + 1) | |
7181 | && op < i.operands); | |
7182 | } | |
7183 | else | |
7184 | { | |
7185 | vex_reg = op + 1; | |
7186 | gas_assert (vex_reg < i.operands); | |
7187 | } | |
c0f3af97 | 7188 | } |
7ab9ffdd | 7189 | } |
2426c15f | 7190 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 7191 | { |
f12dc422 | 7192 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 7193 | is encoded in VEX prefix. */ |
f12dc422 L |
7194 | if (i.mem_operands == 0) |
7195 | { | |
7196 | /* There is no memory operand. */ | |
7197 | gas_assert ((op + 2) == i.operands); | |
7198 | vex_reg = op + 1; | |
7199 | } | |
7200 | else | |
8d63c93e | 7201 | { |
ed438a93 JB |
7202 | /* There are only 2 non-immediate operands. */ |
7203 | gas_assert (op < i.imm_operands + 2 | |
7204 | && i.operands == i.imm_operands + 2); | |
7205 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 7206 | } |
7ab9ffdd L |
7207 | } |
7208 | else | |
7209 | gas_assert (op < i.operands); | |
99018f42 | 7210 | |
7ab9ffdd L |
7211 | if (vex_reg != (unsigned int) ~0) |
7212 | { | |
f12dc422 | 7213 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 7214 | |
dc821c5f JB |
7215 | if ((!type->bitfield.reg |
7216 | || (!type->bitfield.dword && !type->bitfield.qword)) | |
10c17abd | 7217 | && !type->bitfield.regsimd |
43234a1e | 7218 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 7219 | abort (); |
f88c9eb0 | 7220 | |
7ab9ffdd L |
7221 | i.vex.register_specifier = i.op[vex_reg].regs; |
7222 | } | |
7223 | ||
1b9f0c97 L |
7224 | /* Don't set OP operand twice. */ |
7225 | if (vex_reg != op) | |
7ab9ffdd | 7226 | { |
1b9f0c97 L |
7227 | /* If there is an extension opcode to put here, the |
7228 | register number must be put into the regmem field. */ | |
7229 | if (i.tm.extension_opcode != None) | |
7230 | { | |
7231 | i.rm.regmem = i.op[op].regs->reg_num; | |
7232 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7233 | i.rex |= REX_B; | |
43234a1e L |
7234 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7235 | i.vrex |= REX_B; | |
1b9f0c97 L |
7236 | } |
7237 | else | |
7238 | { | |
7239 | i.rm.reg = i.op[op].regs->reg_num; | |
7240 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7241 | i.rex |= REX_R; | |
43234a1e L |
7242 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7243 | i.vrex |= REX_R; | |
1b9f0c97 | 7244 | } |
7ab9ffdd | 7245 | } |
252b5132 | 7246 | |
29b0f896 AM |
7247 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
7248 | must set it to 3 to indicate this is a register operand | |
7249 | in the regmem field. */ | |
7250 | if (!i.mem_operands) | |
7251 | i.rm.mode = 3; | |
7252 | } | |
252b5132 | 7253 | |
29b0f896 | 7254 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 7255 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
7256 | i.rm.reg = i.tm.extension_opcode; |
7257 | } | |
7258 | return default_seg; | |
7259 | } | |
252b5132 | 7260 | |
29b0f896 | 7261 | static void |
e3bb37b5 | 7262 | output_branch (void) |
29b0f896 AM |
7263 | { |
7264 | char *p; | |
f8a5c266 | 7265 | int size; |
29b0f896 AM |
7266 | int code16; |
7267 | int prefix; | |
7268 | relax_substateT subtype; | |
7269 | symbolS *sym; | |
7270 | offsetT off; | |
7271 | ||
f8a5c266 | 7272 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 7273 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
7274 | |
7275 | prefix = 0; | |
7276 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 7277 | { |
29b0f896 AM |
7278 | prefix = 1; |
7279 | i.prefixes -= 1; | |
7280 | code16 ^= CODE16; | |
252b5132 | 7281 | } |
29b0f896 AM |
7282 | /* Pentium4 branch hints. */ |
7283 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7284 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 7285 | { |
29b0f896 AM |
7286 | prefix++; |
7287 | i.prefixes--; | |
7288 | } | |
7289 | if (i.prefix[REX_PREFIX] != 0) | |
7290 | { | |
7291 | prefix++; | |
7292 | i.prefixes--; | |
2f66722d AM |
7293 | } |
7294 | ||
7e8b059b L |
7295 | /* BND prefixed jump. */ |
7296 | if (i.prefix[BND_PREFIX] != 0) | |
7297 | { | |
7298 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7299 | i.prefixes -= 1; | |
7300 | } | |
7301 | ||
29b0f896 AM |
7302 | if (i.prefixes != 0 && !intel_syntax) |
7303 | as_warn (_("skipping prefixes on this instruction")); | |
7304 | ||
7305 | /* It's always a symbol; End frag & setup for relax. | |
7306 | Make sure there is enough room in this frag for the largest | |
7307 | instruction we may generate in md_convert_frag. This is 2 | |
7308 | bytes for the opcode and room for the prefix and largest | |
7309 | displacement. */ | |
7310 | frag_grow (prefix + 2 + 4); | |
7311 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
7312 | p = frag_more (prefix + 1); | |
7313 | if (i.prefix[DATA_PREFIX] != 0) | |
7314 | *p++ = DATA_PREFIX_OPCODE; | |
7315 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
7316 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
7317 | *p++ = i.prefix[SEG_PREFIX]; | |
7318 | if (i.prefix[REX_PREFIX] != 0) | |
7319 | *p++ = i.prefix[REX_PREFIX]; | |
7320 | *p = i.tm.base_opcode; | |
7321 | ||
7322 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 7323 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 7324 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 7325 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 7326 | else |
f8a5c266 | 7327 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 7328 | subtype |= code16; |
3e73aa7c | 7329 | |
29b0f896 AM |
7330 | sym = i.op[0].disps->X_add_symbol; |
7331 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 7332 | |
29b0f896 AM |
7333 | if (i.op[0].disps->X_op != O_constant |
7334 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 7335 | { |
29b0f896 AM |
7336 | /* Handle complex expressions. */ |
7337 | sym = make_expr_symbol (i.op[0].disps); | |
7338 | off = 0; | |
7339 | } | |
3e73aa7c | 7340 | |
29b0f896 AM |
7341 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
7342 | Pass reloc in fr_var. */ | |
d258b828 | 7343 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 7344 | } |
3e73aa7c | 7345 | |
bd7ab16b L |
7346 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7347 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
7348 | symbol S. */ | |
7349 | ||
7350 | static bfd_boolean | |
7351 | need_plt32_p (symbolS *s) | |
7352 | { | |
7353 | /* PLT32 relocation is ELF only. */ | |
7354 | if (!IS_ELF) | |
7355 | return FALSE; | |
7356 | ||
7357 | /* Since there is no need to prepare for PLT branch on x86-64, we | |
7358 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
7359 | be used as a marker for 32-bit PC-relative branches. */ | |
7360 | if (!object_64bit) | |
7361 | return FALSE; | |
7362 | ||
7363 | /* Weak or undefined symbol need PLT32 relocation. */ | |
7364 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
7365 | return TRUE; | |
7366 | ||
7367 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
7368 | if (! S_IS_EXTERNAL (s)) | |
7369 | return FALSE; | |
7370 | ||
7371 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
7372 | non-default visibilities are treated as normal global symbol | |
7373 | so that PLT32 relocation can be used as a marker for 32-bit | |
7374 | PC-relative branches. It is useful for linker relaxation. */ | |
7375 | return TRUE; | |
7376 | } | |
7377 | #endif | |
7378 | ||
29b0f896 | 7379 | static void |
e3bb37b5 | 7380 | output_jump (void) |
29b0f896 AM |
7381 | { |
7382 | char *p; | |
7383 | int size; | |
3e02c1cc | 7384 | fixS *fixP; |
bd7ab16b | 7385 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 7386 | |
40fb9820 | 7387 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
7388 | { |
7389 | /* This is a loop or jecxz type instruction. */ | |
7390 | size = 1; | |
7391 | if (i.prefix[ADDR_PREFIX] != 0) | |
7392 | { | |
7393 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
7394 | i.prefixes -= 1; | |
7395 | } | |
7396 | /* Pentium4 branch hints. */ | |
7397 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7398 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
7399 | { | |
7400 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
7401 | i.prefixes--; | |
3e73aa7c JH |
7402 | } |
7403 | } | |
29b0f896 AM |
7404 | else |
7405 | { | |
7406 | int code16; | |
3e73aa7c | 7407 | |
29b0f896 AM |
7408 | code16 = 0; |
7409 | if (flag_code == CODE_16BIT) | |
7410 | code16 = CODE16; | |
3e73aa7c | 7411 | |
29b0f896 AM |
7412 | if (i.prefix[DATA_PREFIX] != 0) |
7413 | { | |
7414 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
7415 | i.prefixes -= 1; | |
7416 | code16 ^= CODE16; | |
7417 | } | |
252b5132 | 7418 | |
29b0f896 AM |
7419 | size = 4; |
7420 | if (code16) | |
7421 | size = 2; | |
7422 | } | |
9fcc94b6 | 7423 | |
29b0f896 AM |
7424 | if (i.prefix[REX_PREFIX] != 0) |
7425 | { | |
7426 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
7427 | i.prefixes -= 1; | |
7428 | } | |
252b5132 | 7429 | |
7e8b059b L |
7430 | /* BND prefixed jump. */ |
7431 | if (i.prefix[BND_PREFIX] != 0) | |
7432 | { | |
7433 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7434 | i.prefixes -= 1; | |
7435 | } | |
7436 | ||
29b0f896 AM |
7437 | if (i.prefixes != 0 && !intel_syntax) |
7438 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 7439 | |
42164a71 L |
7440 | p = frag_more (i.tm.opcode_length + size); |
7441 | switch (i.tm.opcode_length) | |
7442 | { | |
7443 | case 2: | |
7444 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 7445 | /* Fall through. */ |
42164a71 L |
7446 | case 1: |
7447 | *p++ = i.tm.base_opcode; | |
7448 | break; | |
7449 | default: | |
7450 | abort (); | |
7451 | } | |
e0890092 | 7452 | |
bd7ab16b L |
7453 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7454 | if (size == 4 | |
7455 | && jump_reloc == NO_RELOC | |
7456 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
7457 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
7458 | #endif | |
7459 | ||
7460 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
7461 | ||
3e02c1cc | 7462 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 7463 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc AM |
7464 | |
7465 | /* All jumps handled here are signed, but don't use a signed limit | |
7466 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
7467 | 4G and 64k respectively. */ | |
7468 | if (size == 1) | |
7469 | fixP->fx_signed = 1; | |
29b0f896 | 7470 | } |
e0890092 | 7471 | |
29b0f896 | 7472 | static void |
e3bb37b5 | 7473 | output_interseg_jump (void) |
29b0f896 AM |
7474 | { |
7475 | char *p; | |
7476 | int size; | |
7477 | int prefix; | |
7478 | int code16; | |
252b5132 | 7479 | |
29b0f896 AM |
7480 | code16 = 0; |
7481 | if (flag_code == CODE_16BIT) | |
7482 | code16 = CODE16; | |
a217f122 | 7483 | |
29b0f896 AM |
7484 | prefix = 0; |
7485 | if (i.prefix[DATA_PREFIX] != 0) | |
7486 | { | |
7487 | prefix = 1; | |
7488 | i.prefixes -= 1; | |
7489 | code16 ^= CODE16; | |
7490 | } | |
7491 | if (i.prefix[REX_PREFIX] != 0) | |
7492 | { | |
7493 | prefix++; | |
7494 | i.prefixes -= 1; | |
7495 | } | |
252b5132 | 7496 | |
29b0f896 AM |
7497 | size = 4; |
7498 | if (code16) | |
7499 | size = 2; | |
252b5132 | 7500 | |
29b0f896 AM |
7501 | if (i.prefixes != 0 && !intel_syntax) |
7502 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 7503 | |
29b0f896 AM |
7504 | /* 1 opcode; 2 segment; offset */ |
7505 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 7506 | |
29b0f896 AM |
7507 | if (i.prefix[DATA_PREFIX] != 0) |
7508 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 7509 | |
29b0f896 AM |
7510 | if (i.prefix[REX_PREFIX] != 0) |
7511 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 7512 | |
29b0f896 AM |
7513 | *p++ = i.tm.base_opcode; |
7514 | if (i.op[1].imms->X_op == O_constant) | |
7515 | { | |
7516 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 7517 | |
29b0f896 AM |
7518 | if (size == 2 |
7519 | && !fits_in_unsigned_word (n) | |
7520 | && !fits_in_signed_word (n)) | |
7521 | { | |
7522 | as_bad (_("16-bit jump out of range")); | |
7523 | return; | |
7524 | } | |
7525 | md_number_to_chars (p, n, size); | |
7526 | } | |
7527 | else | |
7528 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 7529 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
7530 | if (i.op[0].imms->X_op != O_constant) |
7531 | as_bad (_("can't handle non absolute segment in `%s'"), | |
7532 | i.tm.name); | |
7533 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
7534 | } | |
a217f122 | 7535 | |
29b0f896 | 7536 | static void |
e3bb37b5 | 7537 | output_insn (void) |
29b0f896 | 7538 | { |
2bbd9c25 JJ |
7539 | fragS *insn_start_frag; |
7540 | offsetT insn_start_off; | |
7541 | ||
29b0f896 AM |
7542 | /* Tie dwarf2 debug info to the address at the start of the insn. |
7543 | We can't do this after the insn has been output as the current | |
7544 | frag may have been closed off. eg. by frag_var. */ | |
7545 | dwarf2_emit_insn (0); | |
7546 | ||
2bbd9c25 JJ |
7547 | insn_start_frag = frag_now; |
7548 | insn_start_off = frag_now_fix (); | |
7549 | ||
29b0f896 | 7550 | /* Output jumps. */ |
40fb9820 | 7551 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 7552 | output_branch (); |
40fb9820 L |
7553 | else if (i.tm.opcode_modifier.jumpbyte |
7554 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 7555 | output_jump (); |
40fb9820 | 7556 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
7557 | output_interseg_jump (); |
7558 | else | |
7559 | { | |
7560 | /* Output normal instructions here. */ | |
7561 | char *p; | |
7562 | unsigned char *q; | |
47465058 | 7563 | unsigned int j; |
331d2d0d | 7564 | unsigned int prefix; |
4dffcebc | 7565 | |
e4e00185 AS |
7566 | if (avoid_fence |
7567 | && i.tm.base_opcode == 0xfae | |
7568 | && i.operands == 1 | |
7569 | && i.imm_operands == 1 | |
7570 | && (i.op[0].imms->X_add_number == 0xe8 | |
7571 | || i.op[0].imms->X_add_number == 0xf0 | |
7572 | || i.op[0].imms->X_add_number == 0xf8)) | |
7573 | { | |
7574 | /* Encode lfence, mfence, and sfence as | |
7575 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
7576 | offsetT val = 0x240483f0ULL; | |
7577 | p = frag_more (5); | |
7578 | md_number_to_chars (p, val, 5); | |
7579 | return; | |
7580 | } | |
7581 | ||
d022bddd IT |
7582 | /* Some processors fail on LOCK prefix. This options makes |
7583 | assembler ignore LOCK prefix and serves as a workaround. */ | |
7584 | if (omit_lock_prefix) | |
7585 | { | |
7586 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
7587 | return; | |
7588 | i.prefix[LOCK_PREFIX] = 0; | |
7589 | } | |
7590 | ||
43234a1e L |
7591 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
7592 | don't need the explicit prefix. */ | |
7593 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 7594 | { |
c0f3af97 | 7595 | switch (i.tm.opcode_length) |
bc4bd9ab | 7596 | { |
c0f3af97 L |
7597 | case 3: |
7598 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 7599 | { |
c0f3af97 L |
7600 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
7601 | goto check_prefix; | |
7602 | } | |
7603 | break; | |
7604 | case 2: | |
7605 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
7606 | { | |
7607 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
7608 | if (i.tm.cpu_flags.bitfield.cpupadlock) | |
7609 | { | |
4dffcebc | 7610 | check_prefix: |
c0f3af97 | 7611 | if (prefix != REPE_PREFIX_OPCODE |
c32fa91d | 7612 | || (i.prefix[REP_PREFIX] |
c0f3af97 L |
7613 | != REPE_PREFIX_OPCODE)) |
7614 | add_prefix (prefix); | |
7615 | } | |
7616 | else | |
4dffcebc L |
7617 | add_prefix (prefix); |
7618 | } | |
c0f3af97 L |
7619 | break; |
7620 | case 1: | |
7621 | break; | |
390c91cf L |
7622 | case 0: |
7623 | /* Check for pseudo prefixes. */ | |
7624 | as_bad_where (insn_start_frag->fr_file, | |
7625 | insn_start_frag->fr_line, | |
7626 | _("pseudo prefix without instruction")); | |
7627 | return; | |
c0f3af97 L |
7628 | default: |
7629 | abort (); | |
bc4bd9ab | 7630 | } |
c0f3af97 | 7631 | |
6d19a37a | 7632 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
7633 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
7634 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
7635 | perform IE->LE optimization. */ | |
7636 | if (x86_elf_abi == X86_64_X32_ABI | |
7637 | && i.operands == 2 | |
7638 | && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF | |
7639 | && i.prefix[REX_PREFIX] == 0) | |
7640 | add_prefix (REX_OPCODE); | |
6d19a37a | 7641 | #endif |
cf61b747 | 7642 | |
c0f3af97 L |
7643 | /* The prefix bytes. */ |
7644 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
7645 | if (*q) | |
7646 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 7647 | } |
ae5c1c7b | 7648 | else |
c0f3af97 L |
7649 | { |
7650 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
7651 | if (*q) | |
7652 | switch (j) | |
7653 | { | |
7654 | case REX_PREFIX: | |
7655 | /* REX byte is encoded in VEX prefix. */ | |
7656 | break; | |
7657 | case SEG_PREFIX: | |
7658 | case ADDR_PREFIX: | |
7659 | FRAG_APPEND_1_CHAR (*q); | |
7660 | break; | |
7661 | default: | |
7662 | /* There should be no other prefixes for instructions | |
7663 | with VEX prefix. */ | |
7664 | abort (); | |
7665 | } | |
7666 | ||
43234a1e L |
7667 | /* For EVEX instructions i.vrex should become 0 after |
7668 | build_evex_prefix. For VEX instructions upper 16 registers | |
7669 | aren't available, so VREX should be 0. */ | |
7670 | if (i.vrex) | |
7671 | abort (); | |
c0f3af97 L |
7672 | /* Now the VEX prefix. */ |
7673 | p = frag_more (i.vex.length); | |
7674 | for (j = 0; j < i.vex.length; j++) | |
7675 | p[j] = i.vex.bytes[j]; | |
7676 | } | |
252b5132 | 7677 | |
29b0f896 | 7678 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 7679 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
7680 | { |
7681 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
7682 | } | |
7683 | else | |
7684 | { | |
4dffcebc | 7685 | switch (i.tm.opcode_length) |
331d2d0d | 7686 | { |
43234a1e L |
7687 | case 4: |
7688 | p = frag_more (4); | |
7689 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
7690 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
7691 | break; | |
4dffcebc | 7692 | case 3: |
331d2d0d L |
7693 | p = frag_more (3); |
7694 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
7695 | break; |
7696 | case 2: | |
7697 | p = frag_more (2); | |
7698 | break; | |
7699 | default: | |
7700 | abort (); | |
7701 | break; | |
331d2d0d | 7702 | } |
0f10071e | 7703 | |
29b0f896 AM |
7704 | /* Put out high byte first: can't use md_number_to_chars! */ |
7705 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
7706 | *p = i.tm.base_opcode & 0xff; | |
7707 | } | |
3e73aa7c | 7708 | |
29b0f896 | 7709 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 7710 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 7711 | { |
4a3523fa L |
7712 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
7713 | | i.rm.reg << 3 | |
7714 | | i.rm.mode << 6)); | |
29b0f896 AM |
7715 | /* If i.rm.regmem == ESP (4) |
7716 | && i.rm.mode != (Register mode) | |
7717 | && not 16 bit | |
7718 | ==> need second modrm byte. */ | |
7719 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
7720 | && i.rm.mode != 3 | |
dc821c5f | 7721 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
4a3523fa L |
7722 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
7723 | | i.sib.index << 3 | |
7724 | | i.sib.scale << 6)); | |
29b0f896 | 7725 | } |
3e73aa7c | 7726 | |
29b0f896 | 7727 | if (i.disp_operands) |
2bbd9c25 | 7728 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 7729 | |
29b0f896 | 7730 | if (i.imm_operands) |
2bbd9c25 | 7731 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 7732 | } |
252b5132 | 7733 | |
29b0f896 AM |
7734 | #ifdef DEBUG386 |
7735 | if (flag_debug) | |
7736 | { | |
7b81dfbb | 7737 | pi ("" /*line*/, &i); |
29b0f896 AM |
7738 | } |
7739 | #endif /* DEBUG386 */ | |
7740 | } | |
252b5132 | 7741 | |
e205caa7 L |
7742 | /* Return the size of the displacement operand N. */ |
7743 | ||
7744 | static int | |
7745 | disp_size (unsigned int n) | |
7746 | { | |
7747 | int size = 4; | |
43234a1e | 7748 | |
b5014f7a | 7749 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
7750 | size = 8; |
7751 | else if (i.types[n].bitfield.disp8) | |
7752 | size = 1; | |
7753 | else if (i.types[n].bitfield.disp16) | |
7754 | size = 2; | |
e205caa7 L |
7755 | return size; |
7756 | } | |
7757 | ||
7758 | /* Return the size of the immediate operand N. */ | |
7759 | ||
7760 | static int | |
7761 | imm_size (unsigned int n) | |
7762 | { | |
7763 | int size = 4; | |
40fb9820 L |
7764 | if (i.types[n].bitfield.imm64) |
7765 | size = 8; | |
7766 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
7767 | size = 1; | |
7768 | else if (i.types[n].bitfield.imm16) | |
7769 | size = 2; | |
e205caa7 L |
7770 | return size; |
7771 | } | |
7772 | ||
29b0f896 | 7773 | static void |
64e74474 | 7774 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
7775 | { |
7776 | char *p; | |
7777 | unsigned int n; | |
252b5132 | 7778 | |
29b0f896 AM |
7779 | for (n = 0; n < i.operands; n++) |
7780 | { | |
b5014f7a | 7781 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
7782 | { |
7783 | if (i.op[n].disps->X_op == O_constant) | |
7784 | { | |
e205caa7 | 7785 | int size = disp_size (n); |
43234a1e | 7786 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 7787 | |
b5014f7a | 7788 | val = offset_in_range (val >> i.memshift, size); |
29b0f896 AM |
7789 | p = frag_more (size); |
7790 | md_number_to_chars (p, val, size); | |
7791 | } | |
7792 | else | |
7793 | { | |
f86103b7 | 7794 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 7795 | int size = disp_size (n); |
40fb9820 | 7796 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 7797 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 7798 | fixS *fixP; |
29b0f896 | 7799 | |
e205caa7 | 7800 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 7801 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 7802 | |
29b0f896 AM |
7803 | /* The PC relative address is computed relative |
7804 | to the instruction boundary, so in case immediate | |
7805 | fields follows, we need to adjust the value. */ | |
7806 | if (pcrel && i.imm_operands) | |
7807 | { | |
29b0f896 | 7808 | unsigned int n1; |
e205caa7 | 7809 | int sz = 0; |
252b5132 | 7810 | |
29b0f896 | 7811 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 7812 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 7813 | { |
e205caa7 L |
7814 | /* Only one immediate is allowed for PC |
7815 | relative address. */ | |
9c2799c2 | 7816 | gas_assert (sz == 0); |
e205caa7 L |
7817 | sz = imm_size (n1); |
7818 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 7819 | } |
29b0f896 | 7820 | /* We should find the immediate. */ |
9c2799c2 | 7821 | gas_assert (sz != 0); |
29b0f896 | 7822 | } |
520dc8e8 | 7823 | |
29b0f896 | 7824 | p = frag_more (size); |
d258b828 | 7825 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 7826 | if (GOT_symbol |
2bbd9c25 | 7827 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 7828 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
7829 | || reloc_type == BFD_RELOC_X86_64_32S |
7830 | || (reloc_type == BFD_RELOC_64 | |
7831 | && object_64bit)) | |
d6ab8113 JB |
7832 | && (i.op[n].disps->X_op == O_symbol |
7833 | || (i.op[n].disps->X_op == O_add | |
7834 | && ((symbol_get_value_expression | |
7835 | (i.op[n].disps->X_op_symbol)->X_op) | |
7836 | == O_subtract)))) | |
7837 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
7838 | { |
7839 | offsetT add; | |
7840 | ||
7841 | if (insn_start_frag == frag_now) | |
7842 | add = (p - frag_now->fr_literal) - insn_start_off; | |
7843 | else | |
7844 | { | |
7845 | fragS *fr; | |
7846 | ||
7847 | add = insn_start_frag->fr_fix - insn_start_off; | |
7848 | for (fr = insn_start_frag->fr_next; | |
7849 | fr && fr != frag_now; fr = fr->fr_next) | |
7850 | add += fr->fr_fix; | |
7851 | add += p - frag_now->fr_literal; | |
7852 | } | |
7853 | ||
4fa24527 | 7854 | if (!object_64bit) |
7b81dfbb AJ |
7855 | { |
7856 | reloc_type = BFD_RELOC_386_GOTPC; | |
7857 | i.op[n].imms->X_add_number += add; | |
7858 | } | |
7859 | else if (reloc_type == BFD_RELOC_64) | |
7860 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 7861 | else |
7b81dfbb AJ |
7862 | /* Don't do the adjustment for x86-64, as there |
7863 | the pcrel addressing is relative to the _next_ | |
7864 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 7865 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 7866 | } |
02a86693 L |
7867 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
7868 | size, i.op[n].disps, pcrel, | |
7869 | reloc_type); | |
7870 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
7871 | "test %reg, mem" and "binop mem, %reg" where binop | |
7872 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
0cb4071e L |
7873 | instructions. Always generate R_386_GOT32X for |
7874 | "sym*GOT" operand in 32-bit mode. */ | |
7875 | if ((generate_relax_relocations | |
7876 | || (!object_64bit | |
7877 | && i.rm.mode == 0 | |
7878 | && i.rm.regmem == 5)) | |
7879 | && (i.rm.mode == 2 | |
7880 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
02a86693 L |
7881 | && ((i.operands == 1 |
7882 | && i.tm.base_opcode == 0xff | |
7883 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
7884 | || (i.operands == 2 | |
7885 | && (i.tm.base_opcode == 0x8b | |
7886 | || i.tm.base_opcode == 0x85 | |
7887 | || (i.tm.base_opcode & 0xc7) == 0x03)))) | |
7888 | { | |
7889 | if (object_64bit) | |
7890 | { | |
7891 | fixP->fx_tcbit = i.rex != 0; | |
7892 | if (i.base_reg | |
7893 | && (i.base_reg->reg_num == RegRip | |
7894 | || i.base_reg->reg_num == RegEip)) | |
7895 | fixP->fx_tcbit2 = 1; | |
7896 | } | |
7897 | else | |
7898 | fixP->fx_tcbit2 = 1; | |
7899 | } | |
29b0f896 AM |
7900 | } |
7901 | } | |
7902 | } | |
7903 | } | |
252b5132 | 7904 | |
29b0f896 | 7905 | static void |
64e74474 | 7906 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
7907 | { |
7908 | char *p; | |
7909 | unsigned int n; | |
252b5132 | 7910 | |
29b0f896 AM |
7911 | for (n = 0; n < i.operands; n++) |
7912 | { | |
43234a1e L |
7913 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
7914 | if (i.rounding && (int) n == i.rounding->operand) | |
7915 | continue; | |
7916 | ||
40fb9820 | 7917 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
7918 | { |
7919 | if (i.op[n].imms->X_op == O_constant) | |
7920 | { | |
e205caa7 | 7921 | int size = imm_size (n); |
29b0f896 | 7922 | offsetT val; |
b4cac588 | 7923 | |
29b0f896 AM |
7924 | val = offset_in_range (i.op[n].imms->X_add_number, |
7925 | size); | |
7926 | p = frag_more (size); | |
7927 | md_number_to_chars (p, val, size); | |
7928 | } | |
7929 | else | |
7930 | { | |
7931 | /* Not absolute_section. | |
7932 | Need a 32-bit fixup (don't support 8bit | |
7933 | non-absolute imms). Try to support other | |
7934 | sizes ... */ | |
f86103b7 | 7935 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
7936 | int size = imm_size (n); |
7937 | int sign; | |
29b0f896 | 7938 | |
40fb9820 | 7939 | if (i.types[n].bitfield.imm32s |
a7d61044 | 7940 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 7941 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 7942 | sign = 1; |
e205caa7 L |
7943 | else |
7944 | sign = 0; | |
520dc8e8 | 7945 | |
29b0f896 | 7946 | p = frag_more (size); |
d258b828 | 7947 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 7948 | |
2bbd9c25 JJ |
7949 | /* This is tough to explain. We end up with this one if we |
7950 | * have operands that look like | |
7951 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
7952 | * obtain the absolute address of the GOT, and it is strongly | |
7953 | * preferable from a performance point of view to avoid using | |
7954 | * a runtime relocation for this. The actual sequence of | |
7955 | * instructions often look something like: | |
7956 | * | |
7957 | * call .L66 | |
7958 | * .L66: | |
7959 | * popl %ebx | |
7960 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
7961 | * | |
7962 | * The call and pop essentially return the absolute address | |
7963 | * of the label .L66 and store it in %ebx. The linker itself | |
7964 | * will ultimately change the first operand of the addl so | |
7965 | * that %ebx points to the GOT, but to keep things simple, the | |
7966 | * .o file must have this operand set so that it generates not | |
7967 | * the absolute address of .L66, but the absolute address of | |
7968 | * itself. This allows the linker itself simply treat a GOTPC | |
7969 | * relocation as asking for a pcrel offset to the GOT to be | |
7970 | * added in, and the addend of the relocation is stored in the | |
7971 | * operand field for the instruction itself. | |
7972 | * | |
7973 | * Our job here is to fix the operand so that it would add | |
7974 | * the correct offset so that %ebx would point to itself. The | |
7975 | * thing that is tricky is that .-.L66 will point to the | |
7976 | * beginning of the instruction, so we need to further modify | |
7977 | * the operand so that it will point to itself. There are | |
7978 | * other cases where you have something like: | |
7979 | * | |
7980 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
7981 | * | |
7982 | * and here no correction would be required. Internally in | |
7983 | * the assembler we treat operands of this form as not being | |
7984 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
7985 | * whether it would simplify matters to do it this way. Who | |
7986 | * knows. In earlier versions of the PIC patches, the | |
7987 | * pcrel_adjust field was used to store the correction, but | |
7988 | * since the expression is not pcrel, I felt it would be | |
7989 | * confusing to do it this way. */ | |
7990 | ||
d6ab8113 | 7991 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
7992 | || reloc_type == BFD_RELOC_X86_64_32S |
7993 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
7994 | && GOT_symbol |
7995 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
7996 | && (i.op[n].imms->X_op == O_symbol | |
7997 | || (i.op[n].imms->X_op == O_add | |
7998 | && ((symbol_get_value_expression | |
7999 | (i.op[n].imms->X_op_symbol)->X_op) | |
8000 | == O_subtract)))) | |
8001 | { | |
2bbd9c25 JJ |
8002 | offsetT add; |
8003 | ||
8004 | if (insn_start_frag == frag_now) | |
8005 | add = (p - frag_now->fr_literal) - insn_start_off; | |
8006 | else | |
8007 | { | |
8008 | fragS *fr; | |
8009 | ||
8010 | add = insn_start_frag->fr_fix - insn_start_off; | |
8011 | for (fr = insn_start_frag->fr_next; | |
8012 | fr && fr != frag_now; fr = fr->fr_next) | |
8013 | add += fr->fr_fix; | |
8014 | add += p - frag_now->fr_literal; | |
8015 | } | |
8016 | ||
4fa24527 | 8017 | if (!object_64bit) |
d6ab8113 | 8018 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 8019 | else if (size == 4) |
d6ab8113 | 8020 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
8021 | else if (size == 8) |
8022 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 8023 | i.op[n].imms->X_add_number += add; |
29b0f896 | 8024 | } |
29b0f896 AM |
8025 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
8026 | i.op[n].imms, 0, reloc_type); | |
8027 | } | |
8028 | } | |
8029 | } | |
252b5132 RH |
8030 | } |
8031 | \f | |
d182319b JB |
8032 | /* x86_cons_fix_new is called via the expression parsing code when a |
8033 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
8034 | static int cons_sign = -1; |
8035 | ||
8036 | void | |
e3bb37b5 | 8037 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 8038 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 8039 | { |
d258b828 | 8040 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
8041 | |
8042 | #ifdef TE_PE | |
8043 | if (exp->X_op == O_secrel) | |
8044 | { | |
8045 | exp->X_op = O_symbol; | |
8046 | r = BFD_RELOC_32_SECREL; | |
8047 | } | |
8048 | #endif | |
8049 | ||
8050 | fix_new_exp (frag, off, len, exp, 0, r); | |
8051 | } | |
8052 | ||
357d1bd8 L |
8053 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
8054 | purpose of the `.dc.a' internal pseudo-op. */ | |
8055 | ||
8056 | int | |
8057 | x86_address_bytes (void) | |
8058 | { | |
8059 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
8060 | return 4; | |
8061 | return stdoutput->arch_info->bits_per_address / 8; | |
8062 | } | |
8063 | ||
d382c579 TG |
8064 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
8065 | || defined (LEX_AT) | |
d258b828 | 8066 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 8067 | #else |
f3c180ae AM |
8068 | /* Parse operands of the form |
8069 | <symbol>@GOTOFF+<nnn> | |
8070 | and similar .plt or .got references. | |
8071 | ||
8072 | If we find one, set up the correct relocation in RELOC and copy the | |
8073 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
8074 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8075 | is non-null set it to the length of the string we removed from the | |
8076 | input line. Otherwise return NULL. */ | |
8077 | static char * | |
91d6fa6a | 8078 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 8079 | int *adjust, |
d258b828 | 8080 | i386_operand_type *types) |
f3c180ae | 8081 | { |
7b81dfbb AJ |
8082 | /* Some of the relocations depend on the size of what field is to |
8083 | be relocated. But in our callers i386_immediate and i386_displacement | |
8084 | we don't yet know the operand size (this will be set by insn | |
8085 | matching). Hence we record the word32 relocation here, | |
8086 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
8087 | static const struct { |
8088 | const char *str; | |
cff8d58a | 8089 | int len; |
4fa24527 | 8090 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 8091 | const i386_operand_type types64; |
f3c180ae | 8092 | } gotrel[] = { |
8ce3d284 | 8093 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
8094 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
8095 | BFD_RELOC_SIZE32 }, | |
8096 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 8097 | #endif |
cff8d58a L |
8098 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
8099 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 8100 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
8101 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
8102 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 8103 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8104 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
8105 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 8106 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8107 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
8108 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 8109 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8110 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
8111 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 8112 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8113 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
8114 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 8115 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8116 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
8117 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8118 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8119 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
8120 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 8121 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8122 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
8123 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 8124 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8125 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
8126 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 8127 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8128 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
8129 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8130 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8131 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
8132 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 8133 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8134 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
8135 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8136 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8137 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
8138 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8139 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8140 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
8141 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 8142 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
8143 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
8144 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 8145 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8146 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
8147 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 8148 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
8149 | }; |
8150 | char *cp; | |
8151 | unsigned int j; | |
8152 | ||
d382c579 | 8153 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
8154 | if (!IS_ELF) |
8155 | return NULL; | |
d382c579 | 8156 | #endif |
718ddfc0 | 8157 | |
f3c180ae | 8158 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 8159 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
8160 | return NULL; |
8161 | ||
47465058 | 8162 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 8163 | { |
cff8d58a | 8164 | int len = gotrel[j].len; |
28f81592 | 8165 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 8166 | { |
4fa24527 | 8167 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 8168 | { |
28f81592 AM |
8169 | int first, second; |
8170 | char *tmpbuf, *past_reloc; | |
f3c180ae | 8171 | |
91d6fa6a | 8172 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 8173 | |
3956db08 JB |
8174 | if (types) |
8175 | { | |
8176 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
8177 | { |
8178 | types->bitfield.imm32 = 1; | |
8179 | types->bitfield.disp32 = 1; | |
8180 | } | |
3956db08 JB |
8181 | else |
8182 | *types = gotrel[j].types64; | |
8183 | } | |
8184 | ||
8fd4256d | 8185 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
8186 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
8187 | ||
28f81592 | 8188 | /* The length of the first part of our input line. */ |
f3c180ae | 8189 | first = cp - input_line_pointer; |
28f81592 AM |
8190 | |
8191 | /* The second part goes from after the reloc token until | |
67c11a9b | 8192 | (and including) an end_of_line char or comma. */ |
28f81592 | 8193 | past_reloc = cp + 1 + len; |
67c11a9b AM |
8194 | cp = past_reloc; |
8195 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
8196 | ++cp; | |
8197 | second = cp + 1 - past_reloc; | |
28f81592 AM |
8198 | |
8199 | /* Allocate and copy string. The trailing NUL shouldn't | |
8200 | be necessary, but be safe. */ | |
add39d23 | 8201 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 8202 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
8203 | if (second != 0 && *past_reloc != ' ') |
8204 | /* Replace the relocation token with ' ', so that | |
8205 | errors like foo@GOTOFF1 will be detected. */ | |
8206 | tmpbuf[first++] = ' '; | |
af89796a L |
8207 | else |
8208 | /* Increment length by 1 if the relocation token is | |
8209 | removed. */ | |
8210 | len++; | |
8211 | if (adjust) | |
8212 | *adjust = len; | |
0787a12d AM |
8213 | memcpy (tmpbuf + first, past_reloc, second); |
8214 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
8215 | return tmpbuf; |
8216 | } | |
8217 | ||
4fa24527 JB |
8218 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
8219 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
8220 | return NULL; |
8221 | } | |
8222 | } | |
8223 | ||
8224 | /* Might be a symbol version string. Don't as_bad here. */ | |
8225 | return NULL; | |
8226 | } | |
4e4f7c87 | 8227 | #endif |
f3c180ae | 8228 | |
a988325c NC |
8229 | #ifdef TE_PE |
8230 | #ifdef lex_got | |
8231 | #undef lex_got | |
8232 | #endif | |
8233 | /* Parse operands of the form | |
8234 | <symbol>@SECREL32+<nnn> | |
8235 | ||
8236 | If we find one, set up the correct relocation in RELOC and copy the | |
8237 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
8238 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8239 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
8240 | input line. Otherwise return NULL. |
8241 | ||
a988325c NC |
8242 | This function is copied from the ELF version above adjusted for PE targets. */ |
8243 | ||
8244 | static char * | |
8245 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
8246 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 8247 | i386_operand_type *types) |
a988325c NC |
8248 | { |
8249 | static const struct | |
8250 | { | |
8251 | const char *str; | |
8252 | int len; | |
8253 | const enum bfd_reloc_code_real rel[2]; | |
8254 | const i386_operand_type types64; | |
8255 | } | |
8256 | gotrel[] = | |
8257 | { | |
8258 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
8259 | BFD_RELOC_32_SECREL }, | |
8260 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
8261 | }; | |
8262 | ||
8263 | char *cp; | |
8264 | unsigned j; | |
8265 | ||
8266 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
8267 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
8268 | return NULL; | |
8269 | ||
8270 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
8271 | { | |
8272 | int len = gotrel[j].len; | |
8273 | ||
8274 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
8275 | { | |
8276 | if (gotrel[j].rel[object_64bit] != 0) | |
8277 | { | |
8278 | int first, second; | |
8279 | char *tmpbuf, *past_reloc; | |
8280 | ||
8281 | *rel = gotrel[j].rel[object_64bit]; | |
8282 | if (adjust) | |
8283 | *adjust = len; | |
8284 | ||
8285 | if (types) | |
8286 | { | |
8287 | if (flag_code != CODE_64BIT) | |
8288 | { | |
8289 | types->bitfield.imm32 = 1; | |
8290 | types->bitfield.disp32 = 1; | |
8291 | } | |
8292 | else | |
8293 | *types = gotrel[j].types64; | |
8294 | } | |
8295 | ||
8296 | /* The length of the first part of our input line. */ | |
8297 | first = cp - input_line_pointer; | |
8298 | ||
8299 | /* The second part goes from after the reloc token until | |
8300 | (and including) an end_of_line char or comma. */ | |
8301 | past_reloc = cp + 1 + len; | |
8302 | cp = past_reloc; | |
8303 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
8304 | ++cp; | |
8305 | second = cp + 1 - past_reloc; | |
8306 | ||
8307 | /* Allocate and copy string. The trailing NUL shouldn't | |
8308 | be necessary, but be safe. */ | |
add39d23 | 8309 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
8310 | memcpy (tmpbuf, input_line_pointer, first); |
8311 | if (second != 0 && *past_reloc != ' ') | |
8312 | /* Replace the relocation token with ' ', so that | |
8313 | errors like foo@SECLREL321 will be detected. */ | |
8314 | tmpbuf[first++] = ' '; | |
8315 | memcpy (tmpbuf + first, past_reloc, second); | |
8316 | tmpbuf[first + second] = '\0'; | |
8317 | return tmpbuf; | |
8318 | } | |
8319 | ||
8320 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
8321 | gotrel[j].str, 1 << (5 + object_64bit)); | |
8322 | return NULL; | |
8323 | } | |
8324 | } | |
8325 | ||
8326 | /* Might be a symbol version string. Don't as_bad here. */ | |
8327 | return NULL; | |
8328 | } | |
8329 | ||
8330 | #endif /* TE_PE */ | |
8331 | ||
62ebcb5c | 8332 | bfd_reloc_code_real_type |
e3bb37b5 | 8333 | x86_cons (expressionS *exp, int size) |
f3c180ae | 8334 | { |
62ebcb5c AM |
8335 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
8336 | ||
ee86248c JB |
8337 | intel_syntax = -intel_syntax; |
8338 | ||
3c7b9c2c | 8339 | exp->X_md = 0; |
4fa24527 | 8340 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
8341 | { |
8342 | /* Handle @GOTOFF and the like in an expression. */ | |
8343 | char *save; | |
8344 | char *gotfree_input_line; | |
4a57f2cf | 8345 | int adjust = 0; |
f3c180ae AM |
8346 | |
8347 | save = input_line_pointer; | |
d258b828 | 8348 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
8349 | if (gotfree_input_line) |
8350 | input_line_pointer = gotfree_input_line; | |
8351 | ||
8352 | expression (exp); | |
8353 | ||
8354 | if (gotfree_input_line) | |
8355 | { | |
8356 | /* expression () has merrily parsed up to the end of line, | |
8357 | or a comma - in the wrong buffer. Transfer how far | |
8358 | input_line_pointer has moved to the right buffer. */ | |
8359 | input_line_pointer = (save | |
8360 | + (input_line_pointer - gotfree_input_line) | |
8361 | + adjust); | |
8362 | free (gotfree_input_line); | |
3992d3b7 AM |
8363 | if (exp->X_op == O_constant |
8364 | || exp->X_op == O_absent | |
8365 | || exp->X_op == O_illegal | |
0398aac5 | 8366 | || exp->X_op == O_register |
3992d3b7 AM |
8367 | || exp->X_op == O_big) |
8368 | { | |
8369 | char c = *input_line_pointer; | |
8370 | *input_line_pointer = 0; | |
8371 | as_bad (_("missing or invalid expression `%s'"), save); | |
8372 | *input_line_pointer = c; | |
8373 | } | |
f3c180ae AM |
8374 | } |
8375 | } | |
8376 | else | |
8377 | expression (exp); | |
ee86248c JB |
8378 | |
8379 | intel_syntax = -intel_syntax; | |
8380 | ||
8381 | if (intel_syntax) | |
8382 | i386_intel_simplify (exp); | |
62ebcb5c AM |
8383 | |
8384 | return got_reloc; | |
f3c180ae | 8385 | } |
f3c180ae | 8386 | |
9f32dd5b L |
8387 | static void |
8388 | signed_cons (int size) | |
6482c264 | 8389 | { |
d182319b JB |
8390 | if (flag_code == CODE_64BIT) |
8391 | cons_sign = 1; | |
8392 | cons (size); | |
8393 | cons_sign = -1; | |
6482c264 NC |
8394 | } |
8395 | ||
d182319b | 8396 | #ifdef TE_PE |
6482c264 | 8397 | static void |
7016a5d5 | 8398 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
8399 | { |
8400 | expressionS exp; | |
8401 | ||
8402 | do | |
8403 | { | |
8404 | expression (&exp); | |
8405 | if (exp.X_op == O_symbol) | |
8406 | exp.X_op = O_secrel; | |
8407 | ||
8408 | emit_expr (&exp, 4); | |
8409 | } | |
8410 | while (*input_line_pointer++ == ','); | |
8411 | ||
8412 | input_line_pointer--; | |
8413 | demand_empty_rest_of_line (); | |
8414 | } | |
6482c264 NC |
8415 | #endif |
8416 | ||
43234a1e L |
8417 | /* Handle Vector operations. */ |
8418 | ||
8419 | static char * | |
8420 | check_VecOperations (char *op_string, char *op_end) | |
8421 | { | |
8422 | const reg_entry *mask; | |
8423 | const char *saved; | |
8424 | char *end_op; | |
8425 | ||
8426 | while (*op_string | |
8427 | && (op_end == NULL || op_string < op_end)) | |
8428 | { | |
8429 | saved = op_string; | |
8430 | if (*op_string == '{') | |
8431 | { | |
8432 | op_string++; | |
8433 | ||
8434 | /* Check broadcasts. */ | |
8435 | if (strncmp (op_string, "1to", 3) == 0) | |
8436 | { | |
8437 | int bcst_type; | |
8438 | ||
8439 | if (i.broadcast) | |
8440 | goto duplicated_vec_op; | |
8441 | ||
8442 | op_string += 3; | |
8443 | if (*op_string == '8') | |
8444 | bcst_type = BROADCAST_1TO8; | |
b28d1bda IT |
8445 | else if (*op_string == '4') |
8446 | bcst_type = BROADCAST_1TO4; | |
8447 | else if (*op_string == '2') | |
8448 | bcst_type = BROADCAST_1TO2; | |
43234a1e L |
8449 | else if (*op_string == '1' |
8450 | && *(op_string+1) == '6') | |
8451 | { | |
8452 | bcst_type = BROADCAST_1TO16; | |
8453 | op_string++; | |
8454 | } | |
8455 | else | |
8456 | { | |
8457 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
8458 | return NULL; | |
8459 | } | |
8460 | op_string++; | |
8461 | ||
8462 | broadcast_op.type = bcst_type; | |
8463 | broadcast_op.operand = this_operand; | |
8464 | i.broadcast = &broadcast_op; | |
8465 | } | |
8466 | /* Check masking operation. */ | |
8467 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
8468 | { | |
8469 | /* k0 can't be used for write mask. */ | |
6d2cd6b2 | 8470 | if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0) |
43234a1e | 8471 | { |
6d2cd6b2 JB |
8472 | as_bad (_("`%s%s' can't be used for write mask"), |
8473 | register_prefix, mask->reg_name); | |
43234a1e L |
8474 | return NULL; |
8475 | } | |
8476 | ||
8477 | if (!i.mask) | |
8478 | { | |
8479 | mask_op.mask = mask; | |
8480 | mask_op.zeroing = 0; | |
8481 | mask_op.operand = this_operand; | |
8482 | i.mask = &mask_op; | |
8483 | } | |
8484 | else | |
8485 | { | |
8486 | if (i.mask->mask) | |
8487 | goto duplicated_vec_op; | |
8488 | ||
8489 | i.mask->mask = mask; | |
8490 | ||
8491 | /* Only "{z}" is allowed here. No need to check | |
8492 | zeroing mask explicitly. */ | |
8493 | if (i.mask->operand != this_operand) | |
8494 | { | |
8495 | as_bad (_("invalid write mask `%s'"), saved); | |
8496 | return NULL; | |
8497 | } | |
8498 | } | |
8499 | ||
8500 | op_string = end_op; | |
8501 | } | |
8502 | /* Check zeroing-flag for masking operation. */ | |
8503 | else if (*op_string == 'z') | |
8504 | { | |
8505 | if (!i.mask) | |
8506 | { | |
8507 | mask_op.mask = NULL; | |
8508 | mask_op.zeroing = 1; | |
8509 | mask_op.operand = this_operand; | |
8510 | i.mask = &mask_op; | |
8511 | } | |
8512 | else | |
8513 | { | |
8514 | if (i.mask->zeroing) | |
8515 | { | |
8516 | duplicated_vec_op: | |
8517 | as_bad (_("duplicated `%s'"), saved); | |
8518 | return NULL; | |
8519 | } | |
8520 | ||
8521 | i.mask->zeroing = 1; | |
8522 | ||
8523 | /* Only "{%k}" is allowed here. No need to check mask | |
8524 | register explicitly. */ | |
8525 | if (i.mask->operand != this_operand) | |
8526 | { | |
8527 | as_bad (_("invalid zeroing-masking `%s'"), | |
8528 | saved); | |
8529 | return NULL; | |
8530 | } | |
8531 | } | |
8532 | ||
8533 | op_string++; | |
8534 | } | |
8535 | else | |
8536 | goto unknown_vec_op; | |
8537 | ||
8538 | if (*op_string != '}') | |
8539 | { | |
8540 | as_bad (_("missing `}' in `%s'"), saved); | |
8541 | return NULL; | |
8542 | } | |
8543 | op_string++; | |
0ba3a731 L |
8544 | |
8545 | /* Strip whitespace since the addition of pseudo prefixes | |
8546 | changed how the scrubber treats '{'. */ | |
8547 | if (is_space_char (*op_string)) | |
8548 | ++op_string; | |
8549 | ||
43234a1e L |
8550 | continue; |
8551 | } | |
8552 | unknown_vec_op: | |
8553 | /* We don't know this one. */ | |
8554 | as_bad (_("unknown vector operation: `%s'"), saved); | |
8555 | return NULL; | |
8556 | } | |
8557 | ||
6d2cd6b2 JB |
8558 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
8559 | { | |
8560 | as_bad (_("zeroing-masking only allowed with write mask")); | |
8561 | return NULL; | |
8562 | } | |
8563 | ||
43234a1e L |
8564 | return op_string; |
8565 | } | |
8566 | ||
252b5132 | 8567 | static int |
70e41ade | 8568 | i386_immediate (char *imm_start) |
252b5132 RH |
8569 | { |
8570 | char *save_input_line_pointer; | |
f3c180ae | 8571 | char *gotfree_input_line; |
252b5132 | 8572 | segT exp_seg = 0; |
47926f60 | 8573 | expressionS *exp; |
40fb9820 L |
8574 | i386_operand_type types; |
8575 | ||
0dfbf9d7 | 8576 | operand_type_set (&types, ~0); |
252b5132 RH |
8577 | |
8578 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
8579 | { | |
31b2323c L |
8580 | as_bad (_("at most %d immediate operands are allowed"), |
8581 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
8582 | return 0; |
8583 | } | |
8584 | ||
8585 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 8586 | i.op[this_operand].imms = exp; |
252b5132 RH |
8587 | |
8588 | if (is_space_char (*imm_start)) | |
8589 | ++imm_start; | |
8590 | ||
8591 | save_input_line_pointer = input_line_pointer; | |
8592 | input_line_pointer = imm_start; | |
8593 | ||
d258b828 | 8594 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
8595 | if (gotfree_input_line) |
8596 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
8597 | |
8598 | exp_seg = expression (exp); | |
8599 | ||
83183c0c | 8600 | SKIP_WHITESPACE (); |
43234a1e L |
8601 | |
8602 | /* Handle vector operations. */ | |
8603 | if (*input_line_pointer == '{') | |
8604 | { | |
8605 | input_line_pointer = check_VecOperations (input_line_pointer, | |
8606 | NULL); | |
8607 | if (input_line_pointer == NULL) | |
8608 | return 0; | |
8609 | } | |
8610 | ||
252b5132 | 8611 | if (*input_line_pointer) |
f3c180ae | 8612 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
8613 | |
8614 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 8615 | if (gotfree_input_line) |
ee86248c JB |
8616 | { |
8617 | free (gotfree_input_line); | |
8618 | ||
8619 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
8620 | exp->X_op = O_illegal; | |
8621 | } | |
8622 | ||
8623 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
8624 | } | |
252b5132 | 8625 | |
ee86248c JB |
8626 | static int |
8627 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
8628 | i386_operand_type types, const char *imm_start) | |
8629 | { | |
8630 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 8631 | { |
313c53d1 L |
8632 | if (imm_start) |
8633 | as_bad (_("missing or invalid immediate expression `%s'"), | |
8634 | imm_start); | |
3992d3b7 | 8635 | return 0; |
252b5132 | 8636 | } |
3e73aa7c | 8637 | else if (exp->X_op == O_constant) |
252b5132 | 8638 | { |
47926f60 | 8639 | /* Size it properly later. */ |
40fb9820 | 8640 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
8641 | /* If not 64bit, sign extend val. */ |
8642 | if (flag_code != CODE_64BIT | |
4eed87de AM |
8643 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
8644 | exp->X_add_number | |
8645 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 8646 | } |
4c63da97 | 8647 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 8648 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 8649 | && exp_seg != absolute_section |
47926f60 | 8650 | && exp_seg != text_section |
24eab124 AM |
8651 | && exp_seg != data_section |
8652 | && exp_seg != bss_section | |
8653 | && exp_seg != undefined_section | |
f86103b7 | 8654 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 8655 | { |
d0b47220 | 8656 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
8657 | return 0; |
8658 | } | |
8659 | #endif | |
a841bdf5 | 8660 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 8661 | { |
313c53d1 L |
8662 | if (imm_start) |
8663 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
8664 | return 0; |
8665 | } | |
252b5132 RH |
8666 | else |
8667 | { | |
8668 | /* This is an address. The size of the address will be | |
24eab124 | 8669 | determined later, depending on destination register, |
3e73aa7c | 8670 | suffix, or the default for the section. */ |
40fb9820 L |
8671 | i.types[this_operand].bitfield.imm8 = 1; |
8672 | i.types[this_operand].bitfield.imm16 = 1; | |
8673 | i.types[this_operand].bitfield.imm32 = 1; | |
8674 | i.types[this_operand].bitfield.imm32s = 1; | |
8675 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
8676 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
8677 | types); | |
252b5132 RH |
8678 | } |
8679 | ||
8680 | return 1; | |
8681 | } | |
8682 | ||
551c1ca1 | 8683 | static char * |
e3bb37b5 | 8684 | i386_scale (char *scale) |
252b5132 | 8685 | { |
551c1ca1 AM |
8686 | offsetT val; |
8687 | char *save = input_line_pointer; | |
252b5132 | 8688 | |
551c1ca1 AM |
8689 | input_line_pointer = scale; |
8690 | val = get_absolute_expression (); | |
8691 | ||
8692 | switch (val) | |
252b5132 | 8693 | { |
551c1ca1 | 8694 | case 1: |
252b5132 RH |
8695 | i.log2_scale_factor = 0; |
8696 | break; | |
551c1ca1 | 8697 | case 2: |
252b5132 RH |
8698 | i.log2_scale_factor = 1; |
8699 | break; | |
551c1ca1 | 8700 | case 4: |
252b5132 RH |
8701 | i.log2_scale_factor = 2; |
8702 | break; | |
551c1ca1 | 8703 | case 8: |
252b5132 RH |
8704 | i.log2_scale_factor = 3; |
8705 | break; | |
8706 | default: | |
a724f0f4 JB |
8707 | { |
8708 | char sep = *input_line_pointer; | |
8709 | ||
8710 | *input_line_pointer = '\0'; | |
8711 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
8712 | scale); | |
8713 | *input_line_pointer = sep; | |
8714 | input_line_pointer = save; | |
8715 | return NULL; | |
8716 | } | |
252b5132 | 8717 | } |
29b0f896 | 8718 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
8719 | { |
8720 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 8721 | 1 << i.log2_scale_factor); |
252b5132 | 8722 | i.log2_scale_factor = 0; |
252b5132 | 8723 | } |
551c1ca1 AM |
8724 | scale = input_line_pointer; |
8725 | input_line_pointer = save; | |
8726 | return scale; | |
252b5132 RH |
8727 | } |
8728 | ||
252b5132 | 8729 | static int |
e3bb37b5 | 8730 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 8731 | { |
29b0f896 | 8732 | expressionS *exp; |
252b5132 RH |
8733 | segT exp_seg = 0; |
8734 | char *save_input_line_pointer; | |
f3c180ae | 8735 | char *gotfree_input_line; |
40fb9820 L |
8736 | int override; |
8737 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 8738 | int ret; |
252b5132 | 8739 | |
31b2323c L |
8740 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
8741 | { | |
8742 | as_bad (_("at most %d displacement operands are allowed"), | |
8743 | MAX_MEMORY_OPERANDS); | |
8744 | return 0; | |
8745 | } | |
8746 | ||
0dfbf9d7 | 8747 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
8748 | if ((i.types[this_operand].bitfield.jumpabsolute) |
8749 | || (!current_templates->start->opcode_modifier.jump | |
8750 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 8751 | { |
40fb9820 | 8752 | bigdisp.bitfield.disp32 = 1; |
e05278af | 8753 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
8754 | if (flag_code == CODE_64BIT) |
8755 | { | |
8756 | if (!override) | |
8757 | { | |
8758 | bigdisp.bitfield.disp32s = 1; | |
8759 | bigdisp.bitfield.disp64 = 1; | |
8760 | } | |
8761 | } | |
8762 | else if ((flag_code == CODE_16BIT) ^ override) | |
8763 | { | |
8764 | bigdisp.bitfield.disp32 = 0; | |
8765 | bigdisp.bitfield.disp16 = 1; | |
8766 | } | |
e05278af JB |
8767 | } |
8768 | else | |
8769 | { | |
8770 | /* For PC-relative branches, the width of the displacement | |
8771 | is dependent upon data size, not address size. */ | |
e05278af | 8772 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
8773 | if (flag_code == CODE_64BIT) |
8774 | { | |
8775 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
8776 | bigdisp.bitfield.disp16 = 1; | |
8777 | else | |
8778 | { | |
8779 | bigdisp.bitfield.disp32 = 1; | |
8780 | bigdisp.bitfield.disp32s = 1; | |
8781 | } | |
8782 | } | |
8783 | else | |
e05278af JB |
8784 | { |
8785 | if (!override) | |
8786 | override = (i.suffix == (flag_code != CODE_16BIT | |
8787 | ? WORD_MNEM_SUFFIX | |
8788 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
8789 | bigdisp.bitfield.disp32 = 1; |
8790 | if ((flag_code == CODE_16BIT) ^ override) | |
8791 | { | |
8792 | bigdisp.bitfield.disp32 = 0; | |
8793 | bigdisp.bitfield.disp16 = 1; | |
8794 | } | |
e05278af | 8795 | } |
e05278af | 8796 | } |
c6fb90c8 L |
8797 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
8798 | bigdisp); | |
252b5132 RH |
8799 | |
8800 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 8801 | i.op[this_operand].disps = exp; |
252b5132 RH |
8802 | i.disp_operands++; |
8803 | save_input_line_pointer = input_line_pointer; | |
8804 | input_line_pointer = disp_start; | |
8805 | END_STRING_AND_SAVE (disp_end); | |
8806 | ||
8807 | #ifndef GCC_ASM_O_HACK | |
8808 | #define GCC_ASM_O_HACK 0 | |
8809 | #endif | |
8810 | #if GCC_ASM_O_HACK | |
8811 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 8812 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 8813 | && displacement_string_end[-1] == '+') |
252b5132 RH |
8814 | { |
8815 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
8816 | constraint within gcc asm statements. |
8817 | For instance: | |
8818 | ||
8819 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
8820 | __asm__ __volatile__ ( \ | |
8821 | "movw %w2,%0\n\t" \ | |
8822 | "movw %w1,2+%0\n\t" \ | |
8823 | "rorl $16,%1\n\t" \ | |
8824 | "movb %b1,4+%0\n\t" \ | |
8825 | "movb %4,5+%0\n\t" \ | |
8826 | "movb $0,6+%0\n\t" \ | |
8827 | "movb %h1,7+%0\n\t" \ | |
8828 | "rorl $16,%1" \ | |
8829 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
8830 | ||
8831 | This works great except that the output assembler ends | |
8832 | up looking a bit weird if it turns out that there is | |
8833 | no offset. You end up producing code that looks like: | |
8834 | ||
8835 | #APP | |
8836 | movw $235,(%eax) | |
8837 | movw %dx,2+(%eax) | |
8838 | rorl $16,%edx | |
8839 | movb %dl,4+(%eax) | |
8840 | movb $137,5+(%eax) | |
8841 | movb $0,6+(%eax) | |
8842 | movb %dh,7+(%eax) | |
8843 | rorl $16,%edx | |
8844 | #NO_APP | |
8845 | ||
47926f60 | 8846 | So here we provide the missing zero. */ |
24eab124 AM |
8847 | |
8848 | *displacement_string_end = '0'; | |
252b5132 RH |
8849 | } |
8850 | #endif | |
d258b828 | 8851 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
8852 | if (gotfree_input_line) |
8853 | input_line_pointer = gotfree_input_line; | |
252b5132 | 8854 | |
24eab124 | 8855 | exp_seg = expression (exp); |
252b5132 | 8856 | |
636c26b0 AM |
8857 | SKIP_WHITESPACE (); |
8858 | if (*input_line_pointer) | |
8859 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
8860 | #if GCC_ASM_O_HACK | |
8861 | RESTORE_END_STRING (disp_end + 1); | |
8862 | #endif | |
636c26b0 | 8863 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 8864 | if (gotfree_input_line) |
ee86248c JB |
8865 | { |
8866 | free (gotfree_input_line); | |
8867 | ||
8868 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
8869 | exp->X_op = O_illegal; | |
8870 | } | |
8871 | ||
8872 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
8873 | ||
8874 | RESTORE_END_STRING (disp_end); | |
8875 | ||
8876 | return ret; | |
8877 | } | |
8878 | ||
8879 | static int | |
8880 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
8881 | i386_operand_type types, const char *disp_start) | |
8882 | { | |
8883 | i386_operand_type bigdisp; | |
8884 | int ret = 1; | |
636c26b0 | 8885 | |
24eab124 AM |
8886 | /* We do this to make sure that the section symbol is in |
8887 | the symbol table. We will ultimately change the relocation | |
47926f60 | 8888 | to be relative to the beginning of the section. */ |
1ae12ab7 | 8889 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
8890 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
8891 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 8892 | { |
636c26b0 | 8893 | if (exp->X_op != O_symbol) |
3992d3b7 | 8894 | goto inv_disp; |
636c26b0 | 8895 | |
e5cb08ac | 8896 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
8897 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
8898 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 8899 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
8900 | exp->X_op = O_subtract; |
8901 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 8902 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 8903 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
8904 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
8905 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 8906 | else |
29b0f896 | 8907 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 8908 | } |
252b5132 | 8909 | |
3992d3b7 AM |
8910 | else if (exp->X_op == O_absent |
8911 | || exp->X_op == O_illegal | |
ee86248c | 8912 | || exp->X_op == O_big) |
2daf4fd8 | 8913 | { |
3992d3b7 AM |
8914 | inv_disp: |
8915 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 8916 | disp_start); |
3992d3b7 | 8917 | ret = 0; |
2daf4fd8 AM |
8918 | } |
8919 | ||
0e1147d9 L |
8920 | else if (flag_code == CODE_64BIT |
8921 | && !i.prefix[ADDR_PREFIX] | |
8922 | && exp->X_op == O_constant) | |
8923 | { | |
8924 | /* Since displacement is signed extended to 64bit, don't allow | |
8925 | disp32 and turn off disp32s if they are out of range. */ | |
8926 | i.types[this_operand].bitfield.disp32 = 0; | |
8927 | if (!fits_in_signed_long (exp->X_add_number)) | |
8928 | { | |
8929 | i.types[this_operand].bitfield.disp32s = 0; | |
8930 | if (i.types[this_operand].bitfield.baseindex) | |
8931 | { | |
8932 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
8933 | (long) exp->X_add_number); | |
8934 | ret = 0; | |
8935 | } | |
8936 | } | |
8937 | } | |
8938 | ||
4c63da97 | 8939 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
8940 | else if (exp->X_op != O_constant |
8941 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
8942 | && exp_seg != absolute_section | |
8943 | && exp_seg != text_section | |
8944 | && exp_seg != data_section | |
8945 | && exp_seg != bss_section | |
8946 | && exp_seg != undefined_section | |
8947 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 8948 | { |
d0b47220 | 8949 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 8950 | ret = 0; |
24eab124 | 8951 | } |
252b5132 | 8952 | #endif |
3956db08 | 8953 | |
40fb9820 L |
8954 | /* Check if this is a displacement only operand. */ |
8955 | bigdisp = i.types[this_operand]; | |
8956 | bigdisp.bitfield.disp8 = 0; | |
8957 | bigdisp.bitfield.disp16 = 0; | |
8958 | bigdisp.bitfield.disp32 = 0; | |
8959 | bigdisp.bitfield.disp32s = 0; | |
8960 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 8961 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
8962 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
8963 | types); | |
3956db08 | 8964 | |
3992d3b7 | 8965 | return ret; |
252b5132 RH |
8966 | } |
8967 | ||
2abc2bec JB |
8968 | /* Return the active addressing mode, taking address override and |
8969 | registers forming the address into consideration. Update the | |
8970 | address override prefix if necessary. */ | |
47926f60 | 8971 | |
2abc2bec JB |
8972 | static enum flag_code |
8973 | i386_addressing_mode (void) | |
252b5132 | 8974 | { |
be05d201 L |
8975 | enum flag_code addr_mode; |
8976 | ||
8977 | if (i.prefix[ADDR_PREFIX]) | |
8978 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
8979 | else | |
8980 | { | |
8981 | addr_mode = flag_code; | |
8982 | ||
24eab124 | 8983 | #if INFER_ADDR_PREFIX |
be05d201 L |
8984 | if (i.mem_operands == 0) |
8985 | { | |
8986 | /* Infer address prefix from the first memory operand. */ | |
8987 | const reg_entry *addr_reg = i.base_reg; | |
8988 | ||
8989 | if (addr_reg == NULL) | |
8990 | addr_reg = i.index_reg; | |
eecb386c | 8991 | |
be05d201 L |
8992 | if (addr_reg) |
8993 | { | |
8994 | if (addr_reg->reg_num == RegEip | |
8995 | || addr_reg->reg_num == RegEiz | |
dc821c5f | 8996 | || addr_reg->reg_type.bitfield.dword) |
be05d201 L |
8997 | addr_mode = CODE_32BIT; |
8998 | else if (flag_code != CODE_64BIT | |
dc821c5f | 8999 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
9000 | addr_mode = CODE_16BIT; |
9001 | ||
9002 | if (addr_mode != flag_code) | |
9003 | { | |
9004 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
9005 | i.prefixes += 1; | |
9006 | /* Change the size of any displacement too. At most one | |
9007 | of Disp16 or Disp32 is set. | |
9008 | FIXME. There doesn't seem to be any real need for | |
9009 | separate Disp16 and Disp32 flags. The same goes for | |
9010 | Imm16 and Imm32. Removing them would probably clean | |
9011 | up the code quite a lot. */ | |
9012 | if (flag_code != CODE_64BIT | |
9013 | && (i.types[this_operand].bitfield.disp16 | |
9014 | || i.types[this_operand].bitfield.disp32)) | |
9015 | i.types[this_operand] | |
9016 | = operand_type_xor (i.types[this_operand], disp16_32); | |
9017 | } | |
9018 | } | |
9019 | } | |
24eab124 | 9020 | #endif |
be05d201 L |
9021 | } |
9022 | ||
2abc2bec JB |
9023 | return addr_mode; |
9024 | } | |
9025 | ||
9026 | /* Make sure the memory operand we've been dealt is valid. | |
9027 | Return 1 on success, 0 on a failure. */ | |
9028 | ||
9029 | static int | |
9030 | i386_index_check (const char *operand_string) | |
9031 | { | |
9032 | const char *kind = "base/index"; | |
9033 | enum flag_code addr_mode = i386_addressing_mode (); | |
9034 | ||
fc0763e6 JB |
9035 | if (current_templates->start->opcode_modifier.isstring |
9036 | && !current_templates->start->opcode_modifier.immext | |
9037 | && (current_templates->end[-1].opcode_modifier.isstring | |
9038 | || i.mem_operands)) | |
9039 | { | |
9040 | /* Memory operands of string insns are special in that they only allow | |
9041 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
9042 | const reg_entry *expected_reg; |
9043 | static const char *di_si[][2] = | |
9044 | { | |
9045 | { "esi", "edi" }, | |
9046 | { "si", "di" }, | |
9047 | { "rsi", "rdi" } | |
9048 | }; | |
9049 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
9050 | |
9051 | kind = "string address"; | |
9052 | ||
8325cc63 | 9053 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 JB |
9054 | { |
9055 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
9056 | ||
9057 | if (!type.bitfield.baseindex | |
9058 | || ((!i.mem_operands != !intel_syntax) | |
9059 | && current_templates->end[-1].operand_types[1] | |
9060 | .bitfield.baseindex)) | |
9061 | type = current_templates->end[-1].operand_types[1]; | |
be05d201 L |
9062 | expected_reg = hash_find (reg_hash, |
9063 | di_si[addr_mode][type.bitfield.esseg]); | |
9064 | ||
fc0763e6 JB |
9065 | } |
9066 | else | |
be05d201 | 9067 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 9068 | |
be05d201 L |
9069 | if (i.base_reg != expected_reg |
9070 | || i.index_reg | |
fc0763e6 | 9071 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 9072 | { |
be05d201 L |
9073 | /* The second memory operand must have the same size as |
9074 | the first one. */ | |
9075 | if (i.mem_operands | |
9076 | && i.base_reg | |
9077 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 9078 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 9079 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
9080 | ? i.base_reg->reg_type.bitfield.dword |
9081 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
9082 | goto bad_address; |
9083 | ||
fc0763e6 JB |
9084 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
9085 | operand_string, | |
9086 | intel_syntax ? '[' : '(', | |
9087 | register_prefix, | |
be05d201 | 9088 | expected_reg->reg_name, |
fc0763e6 | 9089 | intel_syntax ? ']' : ')'); |
be05d201 | 9090 | return 1; |
fc0763e6 | 9091 | } |
be05d201 L |
9092 | else |
9093 | return 1; | |
9094 | ||
9095 | bad_address: | |
9096 | as_bad (_("`%s' is not a valid %s expression"), | |
9097 | operand_string, kind); | |
9098 | return 0; | |
3e73aa7c JH |
9099 | } |
9100 | else | |
9101 | { | |
be05d201 L |
9102 | if (addr_mode != CODE_16BIT) |
9103 | { | |
9104 | /* 32-bit/64-bit checks. */ | |
9105 | if ((i.base_reg | |
9106 | && (addr_mode == CODE_64BIT | |
dc821c5f JB |
9107 | ? !i.base_reg->reg_type.bitfield.qword |
9108 | : !i.base_reg->reg_type.bitfield.dword) | |
be05d201 L |
9109 | && (i.index_reg |
9110 | || (i.base_reg->reg_num | |
9111 | != (addr_mode == CODE_64BIT ? RegRip : RegEip)))) | |
9112 | || (i.index_reg | |
1b54b8d7 JB |
9113 | && !i.index_reg->reg_type.bitfield.xmmword |
9114 | && !i.index_reg->reg_type.bitfield.ymmword | |
9115 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 9116 | && ((addr_mode == CODE_64BIT |
dc821c5f | 9117 | ? !(i.index_reg->reg_type.bitfield.qword |
be05d201 | 9118 | || i.index_reg->reg_num == RegRiz) |
dc821c5f | 9119 | : !(i.index_reg->reg_type.bitfield.dword |
be05d201 L |
9120 | || i.index_reg->reg_num == RegEiz)) |
9121 | || !i.index_reg->reg_type.bitfield.baseindex))) | |
9122 | goto bad_address; | |
8178be5b JB |
9123 | |
9124 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
9125 | if (current_templates->start->base_opcode == 0xf30f1b | |
9126 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
9127 | { | |
9128 | /* They cannot use RIP-relative addressing. */ | |
9129 | if (i.base_reg && i.base_reg->reg_num == RegRip) | |
9130 | { | |
9131 | as_bad (_("`%s' cannot be used here"), operand_string); | |
9132 | return 0; | |
9133 | } | |
9134 | ||
9135 | /* bndldx and bndstx ignore their scale factor. */ | |
9136 | if (current_templates->start->base_opcode != 0xf30f1b | |
9137 | && i.log2_scale_factor) | |
9138 | as_warn (_("register scaling is being ignored here")); | |
9139 | } | |
be05d201 L |
9140 | } |
9141 | else | |
3e73aa7c | 9142 | { |
be05d201 | 9143 | /* 16-bit checks. */ |
3e73aa7c | 9144 | if ((i.base_reg |
dc821c5f | 9145 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 9146 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 9147 | || (i.index_reg |
dc821c5f | 9148 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 9149 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
9150 | || !(i.base_reg |
9151 | && i.base_reg->reg_num < 6 | |
9152 | && i.index_reg->reg_num >= 6 | |
9153 | && i.log2_scale_factor == 0)))) | |
be05d201 | 9154 | goto bad_address; |
3e73aa7c JH |
9155 | } |
9156 | } | |
be05d201 | 9157 | return 1; |
24eab124 | 9158 | } |
252b5132 | 9159 | |
43234a1e L |
9160 | /* Handle vector immediates. */ |
9161 | ||
9162 | static int | |
9163 | RC_SAE_immediate (const char *imm_start) | |
9164 | { | |
9165 | unsigned int match_found, j; | |
9166 | const char *pstr = imm_start; | |
9167 | expressionS *exp; | |
9168 | ||
9169 | if (*pstr != '{') | |
9170 | return 0; | |
9171 | ||
9172 | pstr++; | |
9173 | match_found = 0; | |
9174 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
9175 | { | |
9176 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
9177 | { | |
9178 | if (!i.rounding) | |
9179 | { | |
9180 | rc_op.type = RC_NamesTable[j].type; | |
9181 | rc_op.operand = this_operand; | |
9182 | i.rounding = &rc_op; | |
9183 | } | |
9184 | else | |
9185 | { | |
9186 | as_bad (_("duplicated `%s'"), imm_start); | |
9187 | return 0; | |
9188 | } | |
9189 | pstr += RC_NamesTable[j].len; | |
9190 | match_found = 1; | |
9191 | break; | |
9192 | } | |
9193 | } | |
9194 | if (!match_found) | |
9195 | return 0; | |
9196 | ||
9197 | if (*pstr++ != '}') | |
9198 | { | |
9199 | as_bad (_("Missing '}': '%s'"), imm_start); | |
9200 | return 0; | |
9201 | } | |
9202 | /* RC/SAE immediate string should contain nothing more. */; | |
9203 | if (*pstr != 0) | |
9204 | { | |
9205 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
9206 | return 0; | |
9207 | } | |
9208 | ||
9209 | exp = &im_expressions[i.imm_operands++]; | |
9210 | i.op[this_operand].imms = exp; | |
9211 | ||
9212 | exp->X_op = O_constant; | |
9213 | exp->X_add_number = 0; | |
9214 | exp->X_add_symbol = (symbolS *) 0; | |
9215 | exp->X_op_symbol = (symbolS *) 0; | |
9216 | ||
9217 | i.types[this_operand].bitfield.imm8 = 1; | |
9218 | return 1; | |
9219 | } | |
9220 | ||
8325cc63 JB |
9221 | /* Only string instructions can have a second memory operand, so |
9222 | reduce current_templates to just those if it contains any. */ | |
9223 | static int | |
9224 | maybe_adjust_templates (void) | |
9225 | { | |
9226 | const insn_template *t; | |
9227 | ||
9228 | gas_assert (i.mem_operands == 1); | |
9229 | ||
9230 | for (t = current_templates->start; t < current_templates->end; ++t) | |
9231 | if (t->opcode_modifier.isstring) | |
9232 | break; | |
9233 | ||
9234 | if (t < current_templates->end) | |
9235 | { | |
9236 | static templates aux_templates; | |
9237 | bfd_boolean recheck; | |
9238 | ||
9239 | aux_templates.start = t; | |
9240 | for (; t < current_templates->end; ++t) | |
9241 | if (!t->opcode_modifier.isstring) | |
9242 | break; | |
9243 | aux_templates.end = t; | |
9244 | ||
9245 | /* Determine whether to re-check the first memory operand. */ | |
9246 | recheck = (aux_templates.start != current_templates->start | |
9247 | || t != current_templates->end); | |
9248 | ||
9249 | current_templates = &aux_templates; | |
9250 | ||
9251 | if (recheck) | |
9252 | { | |
9253 | i.mem_operands = 0; | |
9254 | if (i.memop1_string != NULL | |
9255 | && i386_index_check (i.memop1_string) == 0) | |
9256 | return 0; | |
9257 | i.mem_operands = 1; | |
9258 | } | |
9259 | } | |
9260 | ||
9261 | return 1; | |
9262 | } | |
9263 | ||
fc0763e6 | 9264 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 9265 | on error. */ |
252b5132 | 9266 | |
252b5132 | 9267 | static int |
a7619375 | 9268 | i386_att_operand (char *operand_string) |
252b5132 | 9269 | { |
af6bdddf AM |
9270 | const reg_entry *r; |
9271 | char *end_op; | |
24eab124 | 9272 | char *op_string = operand_string; |
252b5132 | 9273 | |
24eab124 | 9274 | if (is_space_char (*op_string)) |
252b5132 RH |
9275 | ++op_string; |
9276 | ||
24eab124 | 9277 | /* We check for an absolute prefix (differentiating, |
47926f60 | 9278 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
9279 | if (*op_string == ABSOLUTE_PREFIX) |
9280 | { | |
9281 | ++op_string; | |
9282 | if (is_space_char (*op_string)) | |
9283 | ++op_string; | |
40fb9820 | 9284 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 9285 | } |
252b5132 | 9286 | |
47926f60 | 9287 | /* Check if operand is a register. */ |
4d1bb795 | 9288 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 9289 | { |
40fb9820 L |
9290 | i386_operand_type temp; |
9291 | ||
24eab124 AM |
9292 | /* Check for a segment override by searching for ':' after a |
9293 | segment register. */ | |
9294 | op_string = end_op; | |
9295 | if (is_space_char (*op_string)) | |
9296 | ++op_string; | |
40fb9820 L |
9297 | if (*op_string == ':' |
9298 | && (r->reg_type.bitfield.sreg2 | |
9299 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
9300 | { |
9301 | switch (r->reg_num) | |
9302 | { | |
9303 | case 0: | |
9304 | i.seg[i.mem_operands] = &es; | |
9305 | break; | |
9306 | case 1: | |
9307 | i.seg[i.mem_operands] = &cs; | |
9308 | break; | |
9309 | case 2: | |
9310 | i.seg[i.mem_operands] = &ss; | |
9311 | break; | |
9312 | case 3: | |
9313 | i.seg[i.mem_operands] = &ds; | |
9314 | break; | |
9315 | case 4: | |
9316 | i.seg[i.mem_operands] = &fs; | |
9317 | break; | |
9318 | case 5: | |
9319 | i.seg[i.mem_operands] = &gs; | |
9320 | break; | |
9321 | } | |
252b5132 | 9322 | |
24eab124 | 9323 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
9324 | ++op_string; |
9325 | if (is_space_char (*op_string)) | |
24eab124 | 9326 | ++op_string; |
252b5132 | 9327 | |
24eab124 AM |
9328 | if (!is_digit_char (*op_string) |
9329 | && !is_identifier_char (*op_string) | |
9330 | && *op_string != '(' | |
9331 | && *op_string != ABSOLUTE_PREFIX) | |
9332 | { | |
9333 | as_bad (_("bad memory operand `%s'"), op_string); | |
9334 | return 0; | |
9335 | } | |
47926f60 | 9336 | /* Handle case of %es:*foo. */ |
24eab124 AM |
9337 | if (*op_string == ABSOLUTE_PREFIX) |
9338 | { | |
9339 | ++op_string; | |
9340 | if (is_space_char (*op_string)) | |
9341 | ++op_string; | |
40fb9820 | 9342 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
9343 | } |
9344 | goto do_memory_reference; | |
9345 | } | |
43234a1e L |
9346 | |
9347 | /* Handle vector operations. */ | |
9348 | if (*op_string == '{') | |
9349 | { | |
9350 | op_string = check_VecOperations (op_string, NULL); | |
9351 | if (op_string == NULL) | |
9352 | return 0; | |
9353 | } | |
9354 | ||
24eab124 AM |
9355 | if (*op_string) |
9356 | { | |
d0b47220 | 9357 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
9358 | return 0; |
9359 | } | |
40fb9820 L |
9360 | temp = r->reg_type; |
9361 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
9362 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
9363 | temp); | |
7d5e4556 | 9364 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 9365 | i.op[this_operand].regs = r; |
24eab124 AM |
9366 | i.reg_operands++; |
9367 | } | |
af6bdddf AM |
9368 | else if (*op_string == REGISTER_PREFIX) |
9369 | { | |
9370 | as_bad (_("bad register name `%s'"), op_string); | |
9371 | return 0; | |
9372 | } | |
24eab124 | 9373 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 9374 | { |
24eab124 | 9375 | ++op_string; |
40fb9820 | 9376 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 9377 | { |
d0b47220 | 9378 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
9379 | return 0; |
9380 | } | |
9381 | if (!i386_immediate (op_string)) | |
9382 | return 0; | |
9383 | } | |
43234a1e L |
9384 | else if (RC_SAE_immediate (operand_string)) |
9385 | { | |
9386 | /* If it is a RC or SAE immediate, do nothing. */ | |
9387 | ; | |
9388 | } | |
24eab124 AM |
9389 | else if (is_digit_char (*op_string) |
9390 | || is_identifier_char (*op_string) | |
d02603dc | 9391 | || *op_string == '"' |
e5cb08ac | 9392 | || *op_string == '(') |
24eab124 | 9393 | { |
47926f60 | 9394 | /* This is a memory reference of some sort. */ |
af6bdddf | 9395 | char *base_string; |
252b5132 | 9396 | |
47926f60 | 9397 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
9398 | char *displacement_string_start; |
9399 | char *displacement_string_end; | |
43234a1e | 9400 | char *vop_start; |
252b5132 | 9401 | |
24eab124 | 9402 | do_memory_reference: |
8325cc63 JB |
9403 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
9404 | return 0; | |
24eab124 | 9405 | if ((i.mem_operands == 1 |
40fb9820 | 9406 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
9407 | || i.mem_operands == 2) |
9408 | { | |
9409 | as_bad (_("too many memory references for `%s'"), | |
9410 | current_templates->start->name); | |
9411 | return 0; | |
9412 | } | |
252b5132 | 9413 | |
24eab124 AM |
9414 | /* Check for base index form. We detect the base index form by |
9415 | looking for an ')' at the end of the operand, searching | |
9416 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
9417 | after the '('. */ | |
af6bdddf | 9418 | base_string = op_string + strlen (op_string); |
c3332e24 | 9419 | |
43234a1e L |
9420 | /* Handle vector operations. */ |
9421 | vop_start = strchr (op_string, '{'); | |
9422 | if (vop_start && vop_start < base_string) | |
9423 | { | |
9424 | if (check_VecOperations (vop_start, base_string) == NULL) | |
9425 | return 0; | |
9426 | base_string = vop_start; | |
9427 | } | |
9428 | ||
af6bdddf AM |
9429 | --base_string; |
9430 | if (is_space_char (*base_string)) | |
9431 | --base_string; | |
252b5132 | 9432 | |
47926f60 | 9433 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
9434 | displacement_string_start = op_string; |
9435 | displacement_string_end = base_string + 1; | |
252b5132 | 9436 | |
24eab124 AM |
9437 | if (*base_string == ')') |
9438 | { | |
af6bdddf | 9439 | char *temp_string; |
24eab124 AM |
9440 | unsigned int parens_balanced = 1; |
9441 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 9442 | equal, so this loop will not be infinite. */ |
24eab124 AM |
9443 | do |
9444 | { | |
9445 | base_string--; | |
9446 | if (*base_string == ')') | |
9447 | parens_balanced++; | |
9448 | if (*base_string == '(') | |
9449 | parens_balanced--; | |
9450 | } | |
9451 | while (parens_balanced); | |
c3332e24 | 9452 | |
af6bdddf | 9453 | temp_string = base_string; |
c3332e24 | 9454 | |
24eab124 | 9455 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
9456 | ++base_string; |
9457 | if (is_space_char (*base_string)) | |
24eab124 | 9458 | ++base_string; |
252b5132 | 9459 | |
af6bdddf | 9460 | if (*base_string == ',' |
4eed87de AM |
9461 | || ((i.base_reg = parse_register (base_string, &end_op)) |
9462 | != NULL)) | |
252b5132 | 9463 | { |
af6bdddf | 9464 | displacement_string_end = temp_string; |
252b5132 | 9465 | |
40fb9820 | 9466 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 9467 | |
af6bdddf | 9468 | if (i.base_reg) |
24eab124 | 9469 | { |
24eab124 AM |
9470 | base_string = end_op; |
9471 | if (is_space_char (*base_string)) | |
9472 | ++base_string; | |
af6bdddf AM |
9473 | } |
9474 | ||
9475 | /* There may be an index reg or scale factor here. */ | |
9476 | if (*base_string == ',') | |
9477 | { | |
9478 | ++base_string; | |
9479 | if (is_space_char (*base_string)) | |
9480 | ++base_string; | |
9481 | ||
4eed87de AM |
9482 | if ((i.index_reg = parse_register (base_string, &end_op)) |
9483 | != NULL) | |
24eab124 | 9484 | { |
af6bdddf | 9485 | base_string = end_op; |
24eab124 AM |
9486 | if (is_space_char (*base_string)) |
9487 | ++base_string; | |
af6bdddf AM |
9488 | if (*base_string == ',') |
9489 | { | |
9490 | ++base_string; | |
9491 | if (is_space_char (*base_string)) | |
9492 | ++base_string; | |
9493 | } | |
e5cb08ac | 9494 | else if (*base_string != ')') |
af6bdddf | 9495 | { |
4eed87de AM |
9496 | as_bad (_("expecting `,' or `)' " |
9497 | "after index register in `%s'"), | |
af6bdddf AM |
9498 | operand_string); |
9499 | return 0; | |
9500 | } | |
24eab124 | 9501 | } |
af6bdddf | 9502 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 9503 | { |
f76bf5e0 L |
9504 | end_op = strchr (base_string, ','); |
9505 | if (end_op) | |
9506 | *end_op = '\0'; | |
af6bdddf | 9507 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
9508 | return 0; |
9509 | } | |
252b5132 | 9510 | |
47926f60 | 9511 | /* Check for scale factor. */ |
551c1ca1 | 9512 | if (*base_string != ')') |
af6bdddf | 9513 | { |
551c1ca1 AM |
9514 | char *end_scale = i386_scale (base_string); |
9515 | ||
9516 | if (!end_scale) | |
af6bdddf | 9517 | return 0; |
24eab124 | 9518 | |
551c1ca1 | 9519 | base_string = end_scale; |
af6bdddf AM |
9520 | if (is_space_char (*base_string)) |
9521 | ++base_string; | |
9522 | if (*base_string != ')') | |
9523 | { | |
4eed87de AM |
9524 | as_bad (_("expecting `)' " |
9525 | "after scale factor in `%s'"), | |
af6bdddf AM |
9526 | operand_string); |
9527 | return 0; | |
9528 | } | |
9529 | } | |
9530 | else if (!i.index_reg) | |
24eab124 | 9531 | { |
4eed87de AM |
9532 | as_bad (_("expecting index register or scale factor " |
9533 | "after `,'; got '%c'"), | |
af6bdddf | 9534 | *base_string); |
24eab124 AM |
9535 | return 0; |
9536 | } | |
9537 | } | |
af6bdddf | 9538 | else if (*base_string != ')') |
24eab124 | 9539 | { |
4eed87de AM |
9540 | as_bad (_("expecting `,' or `)' " |
9541 | "after base register in `%s'"), | |
af6bdddf | 9542 | operand_string); |
24eab124 AM |
9543 | return 0; |
9544 | } | |
c3332e24 | 9545 | } |
af6bdddf | 9546 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 9547 | { |
f76bf5e0 L |
9548 | end_op = strchr (base_string, ','); |
9549 | if (end_op) | |
9550 | *end_op = '\0'; | |
af6bdddf | 9551 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 9552 | return 0; |
c3332e24 | 9553 | } |
24eab124 AM |
9554 | } |
9555 | ||
9556 | /* If there's an expression beginning the operand, parse it, | |
9557 | assuming displacement_string_start and | |
9558 | displacement_string_end are meaningful. */ | |
9559 | if (displacement_string_start != displacement_string_end) | |
9560 | { | |
9561 | if (!i386_displacement (displacement_string_start, | |
9562 | displacement_string_end)) | |
9563 | return 0; | |
9564 | } | |
9565 | ||
9566 | /* Special case for (%dx) while doing input/output op. */ | |
9567 | if (i.base_reg | |
0dfbf9d7 L |
9568 | && operand_type_equal (&i.base_reg->reg_type, |
9569 | ®16_inoutportreg) | |
24eab124 AM |
9570 | && i.index_reg == 0 |
9571 | && i.log2_scale_factor == 0 | |
9572 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 9573 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 9574 | { |
65da13b5 | 9575 | i.types[this_operand] = inoutportreg; |
24eab124 AM |
9576 | return 1; |
9577 | } | |
9578 | ||
eecb386c AM |
9579 | if (i386_index_check (operand_string) == 0) |
9580 | return 0; | |
5c07affc | 9581 | i.types[this_operand].bitfield.mem = 1; |
8325cc63 JB |
9582 | if (i.mem_operands == 0) |
9583 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
9584 | i.mem_operands++; |
9585 | } | |
9586 | else | |
ce8a8b2f AM |
9587 | { |
9588 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
9589 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
9590 | output_invalid (*op_string), | |
9591 | this_operand + 1, | |
9592 | op_string); | |
9593 | return 0; | |
9594 | } | |
47926f60 | 9595 | return 1; /* Normal return. */ |
252b5132 RH |
9596 | } |
9597 | \f | |
fa94de6b RM |
9598 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
9599 | that an rs_machine_dependent frag may reach. */ | |
9600 | ||
9601 | unsigned int | |
9602 | i386_frag_max_var (fragS *frag) | |
9603 | { | |
9604 | /* The only relaxable frags are for jumps. | |
9605 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
9606 | gas_assert (frag->fr_type == rs_machine_dependent); | |
9607 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
9608 | } | |
9609 | ||
b084df0b L |
9610 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9611 | static int | |
8dcea932 | 9612 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
9613 | { |
9614 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
9615 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
9616 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
9617 | return 0; | |
9618 | ||
9619 | if (!S_IS_EXTERNAL (fr_symbol)) | |
9620 | /* Symbol may be weak or local. */ | |
9621 | return !S_IS_WEAK (fr_symbol); | |
9622 | ||
8dcea932 L |
9623 | /* Global symbols with non-default visibility can't be preempted. */ |
9624 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
9625 | return 1; | |
9626 | ||
9627 | if (fr_var != NO_RELOC) | |
9628 | switch ((enum bfd_reloc_code_real) fr_var) | |
9629 | { | |
9630 | case BFD_RELOC_386_PLT32: | |
9631 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 9632 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
9633 | return 0; |
9634 | default: | |
9635 | abort (); | |
9636 | } | |
9637 | ||
b084df0b L |
9638 | /* Global symbols with default visibility in a shared library may be |
9639 | preempted by another definition. */ | |
8dcea932 | 9640 | return !shared; |
b084df0b L |
9641 | } |
9642 | #endif | |
9643 | ||
ee7fcc42 AM |
9644 | /* md_estimate_size_before_relax() |
9645 | ||
9646 | Called just before relax() for rs_machine_dependent frags. The x86 | |
9647 | assembler uses these frags to handle variable size jump | |
9648 | instructions. | |
9649 | ||
9650 | Any symbol that is now undefined will not become defined. | |
9651 | Return the correct fr_subtype in the frag. | |
9652 | Return the initial "guess for variable size of frag" to caller. | |
9653 | The guess is actually the growth beyond the fixed part. Whatever | |
9654 | we do to grow the fixed or variable part contributes to our | |
9655 | returned value. */ | |
9656 | ||
252b5132 | 9657 | int |
7016a5d5 | 9658 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 9659 | { |
252b5132 | 9660 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
9661 | check for un-relaxable symbols. On an ELF system, we can't relax |
9662 | an externally visible symbol, because it may be overridden by a | |
9663 | shared library. */ | |
9664 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 9665 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 9666 | || (IS_ELF |
8dcea932 L |
9667 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
9668 | fragP->fr_var)) | |
fbeb56a4 DK |
9669 | #endif |
9670 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 9671 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 9672 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
9673 | #endif |
9674 | ) | |
252b5132 | 9675 | { |
b98ef147 AM |
9676 | /* Symbol is undefined in this segment, or we need to keep a |
9677 | reloc so that weak symbols can be overridden. */ | |
9678 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 9679 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
9680 | unsigned char *opcode; |
9681 | int old_fr_fix; | |
f6af82bd | 9682 | |
ee7fcc42 | 9683 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 9684 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 9685 | else if (size == 2) |
f6af82bd | 9686 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
9687 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9688 | else if (need_plt32_p (fragP->fr_symbol)) | |
9689 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
9690 | #endif | |
f6af82bd AM |
9691 | else |
9692 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 9693 | |
ee7fcc42 AM |
9694 | old_fr_fix = fragP->fr_fix; |
9695 | opcode = (unsigned char *) fragP->fr_opcode; | |
9696 | ||
fddf5b5b | 9697 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 9698 | { |
fddf5b5b AM |
9699 | case UNCOND_JUMP: |
9700 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 9701 | opcode[0] = 0xe9; |
252b5132 | 9702 | fragP->fr_fix += size; |
062cd5e7 AS |
9703 | fix_new (fragP, old_fr_fix, size, |
9704 | fragP->fr_symbol, | |
9705 | fragP->fr_offset, 1, | |
9706 | reloc_type); | |
252b5132 RH |
9707 | break; |
9708 | ||
fddf5b5b | 9709 | case COND_JUMP86: |
412167cb AM |
9710 | if (size == 2 |
9711 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
9712 | { |
9713 | /* Negate the condition, and branch past an | |
9714 | unconditional jump. */ | |
9715 | opcode[0] ^= 1; | |
9716 | opcode[1] = 3; | |
9717 | /* Insert an unconditional jump. */ | |
9718 | opcode[2] = 0xe9; | |
9719 | /* We added two extra opcode bytes, and have a two byte | |
9720 | offset. */ | |
9721 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
9722 | fix_new (fragP, old_fr_fix + 2, 2, |
9723 | fragP->fr_symbol, | |
9724 | fragP->fr_offset, 1, | |
9725 | reloc_type); | |
fddf5b5b AM |
9726 | break; |
9727 | } | |
9728 | /* Fall through. */ | |
9729 | ||
9730 | case COND_JUMP: | |
412167cb AM |
9731 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
9732 | { | |
3e02c1cc AM |
9733 | fixS *fixP; |
9734 | ||
412167cb | 9735 | fragP->fr_fix += 1; |
3e02c1cc AM |
9736 | fixP = fix_new (fragP, old_fr_fix, 1, |
9737 | fragP->fr_symbol, | |
9738 | fragP->fr_offset, 1, | |
9739 | BFD_RELOC_8_PCREL); | |
9740 | fixP->fx_signed = 1; | |
412167cb AM |
9741 | break; |
9742 | } | |
93c2a809 | 9743 | |
24eab124 | 9744 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 9745 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 9746 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 9747 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
9748 | /* We've added an opcode byte. */ |
9749 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
9750 | fix_new (fragP, old_fr_fix + 1, size, |
9751 | fragP->fr_symbol, | |
9752 | fragP->fr_offset, 1, | |
9753 | reloc_type); | |
252b5132 | 9754 | break; |
fddf5b5b AM |
9755 | |
9756 | default: | |
9757 | BAD_CASE (fragP->fr_subtype); | |
9758 | break; | |
252b5132 RH |
9759 | } |
9760 | frag_wane (fragP); | |
ee7fcc42 | 9761 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 9762 | } |
93c2a809 | 9763 | |
93c2a809 AM |
9764 | /* Guess size depending on current relax state. Initially the relax |
9765 | state will correspond to a short jump and we return 1, because | |
9766 | the variable part of the frag (the branch offset) is one byte | |
9767 | long. However, we can relax a section more than once and in that | |
9768 | case we must either set fr_subtype back to the unrelaxed state, | |
9769 | or return the value for the appropriate branch. */ | |
9770 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
9771 | } |
9772 | ||
47926f60 KH |
9773 | /* Called after relax() is finished. |
9774 | ||
9775 | In: Address of frag. | |
9776 | fr_type == rs_machine_dependent. | |
9777 | fr_subtype is what the address relaxed to. | |
9778 | ||
9779 | Out: Any fixSs and constants are set up. | |
9780 | Caller will turn frag into a ".space 0". */ | |
9781 | ||
252b5132 | 9782 | void |
7016a5d5 TG |
9783 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
9784 | fragS *fragP) | |
252b5132 | 9785 | { |
29b0f896 | 9786 | unsigned char *opcode; |
252b5132 | 9787 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
9788 | offsetT target_address; |
9789 | offsetT opcode_address; | |
252b5132 | 9790 | unsigned int extension = 0; |
847f7ad4 | 9791 | offsetT displacement_from_opcode_start; |
252b5132 RH |
9792 | |
9793 | opcode = (unsigned char *) fragP->fr_opcode; | |
9794 | ||
47926f60 | 9795 | /* Address we want to reach in file space. */ |
252b5132 | 9796 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 9797 | |
47926f60 | 9798 | /* Address opcode resides at in file space. */ |
252b5132 RH |
9799 | opcode_address = fragP->fr_address + fragP->fr_fix; |
9800 | ||
47926f60 | 9801 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
9802 | displacement_from_opcode_start = target_address - opcode_address; |
9803 | ||
fddf5b5b | 9804 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 9805 | { |
47926f60 KH |
9806 | /* Don't have to change opcode. */ |
9807 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 9808 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
9809 | } |
9810 | else | |
9811 | { | |
9812 | if (no_cond_jump_promotion | |
9813 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
9814 | as_warn_where (fragP->fr_file, fragP->fr_line, |
9815 | _("long jump required")); | |
252b5132 | 9816 | |
fddf5b5b AM |
9817 | switch (fragP->fr_subtype) |
9818 | { | |
9819 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
9820 | extension = 4; /* 1 opcode + 4 displacement */ | |
9821 | opcode[0] = 0xe9; | |
9822 | where_to_put_displacement = &opcode[1]; | |
9823 | break; | |
252b5132 | 9824 | |
fddf5b5b AM |
9825 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
9826 | extension = 2; /* 1 opcode + 2 displacement */ | |
9827 | opcode[0] = 0xe9; | |
9828 | where_to_put_displacement = &opcode[1]; | |
9829 | break; | |
252b5132 | 9830 | |
fddf5b5b AM |
9831 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
9832 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
9833 | extension = 5; /* 2 opcode + 4 displacement */ | |
9834 | opcode[1] = opcode[0] + 0x10; | |
9835 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
9836 | where_to_put_displacement = &opcode[2]; | |
9837 | break; | |
252b5132 | 9838 | |
fddf5b5b AM |
9839 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
9840 | extension = 3; /* 2 opcode + 2 displacement */ | |
9841 | opcode[1] = opcode[0] + 0x10; | |
9842 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
9843 | where_to_put_displacement = &opcode[2]; | |
9844 | break; | |
252b5132 | 9845 | |
fddf5b5b AM |
9846 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
9847 | extension = 4; | |
9848 | opcode[0] ^= 1; | |
9849 | opcode[1] = 3; | |
9850 | opcode[2] = 0xe9; | |
9851 | where_to_put_displacement = &opcode[3]; | |
9852 | break; | |
9853 | ||
9854 | default: | |
9855 | BAD_CASE (fragP->fr_subtype); | |
9856 | break; | |
9857 | } | |
252b5132 | 9858 | } |
fddf5b5b | 9859 | |
7b81dfbb AJ |
9860 | /* If size if less then four we are sure that the operand fits, |
9861 | but if it's 4, then it could be that the displacement is larger | |
9862 | then -/+ 2GB. */ | |
9863 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
9864 | && object_64bit | |
9865 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
9866 | + ((addressT) 1 << 31)) |
9867 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
9868 | { |
9869 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9870 | _("jump target out of range")); | |
9871 | /* Make us emit 0. */ | |
9872 | displacement_from_opcode_start = extension; | |
9873 | } | |
47926f60 | 9874 | /* Now put displacement after opcode. */ |
252b5132 RH |
9875 | md_number_to_chars ((char *) where_to_put_displacement, |
9876 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 9877 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
9878 | fragP->fr_fix += extension; |
9879 | } | |
9880 | \f | |
7016a5d5 | 9881 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
9882 | by our caller that we have all the info we need to fix it up. |
9883 | ||
7016a5d5 TG |
9884 | Parameter valP is the pointer to the value of the bits. |
9885 | ||
252b5132 RH |
9886 | On the 386, immediates, displacements, and data pointers are all in |
9887 | the same (little-endian) format, so we don't need to care about which | |
9888 | we are handling. */ | |
9889 | ||
94f592af | 9890 | void |
7016a5d5 | 9891 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 9892 | { |
94f592af | 9893 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 9894 | valueT value = *valP; |
252b5132 | 9895 | |
f86103b7 | 9896 | #if !defined (TE_Mach) |
93382f6d AM |
9897 | if (fixP->fx_pcrel) |
9898 | { | |
9899 | switch (fixP->fx_r_type) | |
9900 | { | |
5865bb77 ILT |
9901 | default: |
9902 | break; | |
9903 | ||
d6ab8113 JB |
9904 | case BFD_RELOC_64: |
9905 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
9906 | break; | |
93382f6d | 9907 | case BFD_RELOC_32: |
ae8887b5 | 9908 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
9909 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
9910 | break; | |
9911 | case BFD_RELOC_16: | |
9912 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
9913 | break; | |
9914 | case BFD_RELOC_8: | |
9915 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
9916 | break; | |
9917 | } | |
9918 | } | |
252b5132 | 9919 | |
a161fe53 | 9920 | if (fixP->fx_addsy != NULL |
31312f95 | 9921 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 9922 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 9923 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 9924 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 9925 | && !use_rela_relocations) |
252b5132 | 9926 | { |
31312f95 AM |
9927 | /* This is a hack. There should be a better way to handle this. |
9928 | This covers for the fact that bfd_install_relocation will | |
9929 | subtract the current location (for partial_inplace, PC relative | |
9930 | relocations); see more below. */ | |
252b5132 | 9931 | #ifndef OBJ_AOUT |
718ddfc0 | 9932 | if (IS_ELF |
252b5132 RH |
9933 | #ifdef TE_PE |
9934 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
9935 | #endif | |
9936 | ) | |
9937 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
9938 | #endif | |
9939 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 9940 | if (IS_ELF) |
252b5132 | 9941 | { |
6539b54b | 9942 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 9943 | |
6539b54b | 9944 | if ((sym_seg == seg |
2f66722d | 9945 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 9946 | && sym_seg != absolute_section)) |
af65af87 | 9947 | && !generic_force_reloc (fixP)) |
2f66722d AM |
9948 | { |
9949 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
9950 | bfd_install_relocation subtracts them out again. I think |
9951 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
9952 | it. FIXME. */ |
9953 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
9954 | } | |
252b5132 RH |
9955 | } |
9956 | #endif | |
9957 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
9958 | /* For some reason, the PE format does not store a |
9959 | section address offset for a PC relative symbol. */ | |
9960 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 9961 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
9962 | value += md_pcrel_from (fixP); |
9963 | #endif | |
9964 | } | |
fbeb56a4 | 9965 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
9966 | if (fixP->fx_addsy != NULL |
9967 | && S_IS_WEAK (fixP->fx_addsy) | |
9968 | /* PR 16858: Do not modify weak function references. */ | |
9969 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 9970 | { |
296a8689 NC |
9971 | #if !defined (TE_PEP) |
9972 | /* For x86 PE weak function symbols are neither PC-relative | |
9973 | nor do they set S_IS_FUNCTION. So the only reliable way | |
9974 | to detect them is to check the flags of their containing | |
9975 | section. */ | |
9976 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
9977 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
9978 | ; | |
9979 | else | |
9980 | #endif | |
fbeb56a4 DK |
9981 | value -= S_GET_VALUE (fixP->fx_addsy); |
9982 | } | |
9983 | #endif | |
252b5132 RH |
9984 | |
9985 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 9986 | and we must not disappoint it. */ |
252b5132 | 9987 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 9988 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
9989 | switch (fixP->fx_r_type) |
9990 | { | |
9991 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 9992 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
9993 | /* Make the jump instruction point to the address of the operand. At |
9994 | runtime we merely add the offset to the actual PLT entry. */ | |
9995 | value = -4; | |
9996 | break; | |
31312f95 | 9997 | |
13ae64f3 JJ |
9998 | case BFD_RELOC_386_TLS_GD: |
9999 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 10000 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
10001 | case BFD_RELOC_386_TLS_IE: |
10002 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 10003 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
10004 | case BFD_RELOC_X86_64_TLSGD: |
10005 | case BFD_RELOC_X86_64_TLSLD: | |
10006 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 10007 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
10008 | value = 0; /* Fully resolved at runtime. No addend. */ |
10009 | /* Fallthrough */ | |
10010 | case BFD_RELOC_386_TLS_LE: | |
10011 | case BFD_RELOC_386_TLS_LDO_32: | |
10012 | case BFD_RELOC_386_TLS_LE_32: | |
10013 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 10014 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 10015 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 10016 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
10017 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
10018 | break; | |
10019 | ||
67a4f2b7 AO |
10020 | case BFD_RELOC_386_TLS_DESC_CALL: |
10021 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
10022 | value = 0; /* Fully resolved at runtime. No addend. */ | |
10023 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
10024 | fixP->fx_done = 0; | |
10025 | return; | |
10026 | ||
47926f60 KH |
10027 | case BFD_RELOC_VTABLE_INHERIT: |
10028 | case BFD_RELOC_VTABLE_ENTRY: | |
10029 | fixP->fx_done = 0; | |
94f592af | 10030 | return; |
47926f60 KH |
10031 | |
10032 | default: | |
10033 | break; | |
10034 | } | |
10035 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 10036 | *valP = value; |
f86103b7 | 10037 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 10038 | |
3e73aa7c | 10039 | /* Are we finished with this relocation now? */ |
c6682705 | 10040 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 10041 | fixP->fx_done = 1; |
fbeb56a4 DK |
10042 | #if defined (OBJ_COFF) && defined (TE_PE) |
10043 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
10044 | { | |
10045 | fixP->fx_done = 0; | |
10046 | /* Remember value for tc_gen_reloc. */ | |
10047 | fixP->fx_addnumber = value; | |
10048 | /* Clear out the frag for now. */ | |
10049 | value = 0; | |
10050 | } | |
10051 | #endif | |
3e73aa7c JH |
10052 | else if (use_rela_relocations) |
10053 | { | |
10054 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
10055 | /* Remember value for tc_gen_reloc. */ |
10056 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
10057 | value = 0; |
10058 | } | |
f86103b7 | 10059 | |
94f592af | 10060 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 10061 | } |
252b5132 | 10062 | \f |
6d4af3c2 | 10063 | const char * |
499ac353 | 10064 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 10065 | { |
499ac353 NC |
10066 | /* This outputs the LITTLENUMs in REVERSE order; |
10067 | in accord with the bigendian 386. */ | |
10068 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
10069 | } |
10070 | \f | |
2d545b82 | 10071 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 10072 | |
252b5132 | 10073 | static char * |
e3bb37b5 | 10074 | output_invalid (int c) |
252b5132 | 10075 | { |
3882b010 | 10076 | if (ISPRINT (c)) |
f9f21a03 L |
10077 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
10078 | "'%c'", c); | |
252b5132 | 10079 | else |
f9f21a03 | 10080 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 10081 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
10082 | return output_invalid_buf; |
10083 | } | |
10084 | ||
af6bdddf | 10085 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
10086 | |
10087 | static const reg_entry * | |
4d1bb795 | 10088 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 10089 | { |
af6bdddf AM |
10090 | char *s = reg_string; |
10091 | char *p; | |
252b5132 RH |
10092 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
10093 | const reg_entry *r; | |
10094 | ||
10095 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
10096 | if (*s == REGISTER_PREFIX) | |
10097 | ++s; | |
10098 | ||
10099 | if (is_space_char (*s)) | |
10100 | ++s; | |
10101 | ||
10102 | p = reg_name_given; | |
af6bdddf | 10103 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
10104 | { |
10105 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
10106 | return (const reg_entry *) NULL; |
10107 | s++; | |
252b5132 RH |
10108 | } |
10109 | ||
6588847e DN |
10110 | /* For naked regs, make sure that we are not dealing with an identifier. |
10111 | This prevents confusing an identifier like `eax_var' with register | |
10112 | `eax'. */ | |
10113 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
10114 | return (const reg_entry *) NULL; | |
10115 | ||
af6bdddf | 10116 | *end_op = s; |
252b5132 RH |
10117 | |
10118 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
10119 | ||
5f47d35b | 10120 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 10121 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 10122 | { |
5f47d35b AM |
10123 | if (is_space_char (*s)) |
10124 | ++s; | |
10125 | if (*s == '(') | |
10126 | { | |
af6bdddf | 10127 | ++s; |
5f47d35b AM |
10128 | if (is_space_char (*s)) |
10129 | ++s; | |
10130 | if (*s >= '0' && *s <= '7') | |
10131 | { | |
db557034 | 10132 | int fpr = *s - '0'; |
af6bdddf | 10133 | ++s; |
5f47d35b AM |
10134 | if (is_space_char (*s)) |
10135 | ++s; | |
10136 | if (*s == ')') | |
10137 | { | |
10138 | *end_op = s + 1; | |
1e9cc1c2 | 10139 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
10140 | know (r); |
10141 | return r + fpr; | |
5f47d35b | 10142 | } |
5f47d35b | 10143 | } |
47926f60 | 10144 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
10145 | return (const reg_entry *) NULL; |
10146 | } | |
10147 | } | |
10148 | ||
a60de03c JB |
10149 | if (r == NULL || allow_pseudo_reg) |
10150 | return r; | |
10151 | ||
0dfbf9d7 | 10152 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
10153 | return (const reg_entry *) NULL; |
10154 | ||
dc821c5f | 10155 | if ((r->reg_type.bitfield.dword |
192dc9c6 JB |
10156 | || r->reg_type.bitfield.sreg3 |
10157 | || r->reg_type.bitfield.control | |
10158 | || r->reg_type.bitfield.debug | |
10159 | || r->reg_type.bitfield.test) | |
10160 | && !cpu_arch_flags.bitfield.cpui386) | |
10161 | return (const reg_entry *) NULL; | |
10162 | ||
ca0d63fe | 10163 | if (r->reg_type.bitfield.tbyte |
309d3373 JB |
10164 | && !cpu_arch_flags.bitfield.cpu8087 |
10165 | && !cpu_arch_flags.bitfield.cpu287 | |
10166 | && !cpu_arch_flags.bitfield.cpu387) | |
10167 | return (const reg_entry *) NULL; | |
10168 | ||
1848e567 | 10169 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx) |
192dc9c6 JB |
10170 | return (const reg_entry *) NULL; |
10171 | ||
1b54b8d7 | 10172 | if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm) |
192dc9c6 JB |
10173 | return (const reg_entry *) NULL; |
10174 | ||
1b54b8d7 | 10175 | if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm) |
40f12533 L |
10176 | return (const reg_entry *) NULL; |
10177 | ||
1b54b8d7 | 10178 | if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm) |
1848e567 L |
10179 | return (const reg_entry *) NULL; |
10180 | ||
10181 | if (r->reg_type.bitfield.regmask | |
10182 | && !cpu_arch_flags.bitfield.cpuregmask) | |
43234a1e L |
10183 | return (const reg_entry *) NULL; |
10184 | ||
db51cc60 | 10185 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
a60de03c | 10186 | if (!allow_index_reg |
db51cc60 L |
10187 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) |
10188 | return (const reg_entry *) NULL; | |
10189 | ||
43234a1e L |
10190 | /* Upper 16 vector register is only available with VREX in 64bit |
10191 | mode. */ | |
10192 | if ((r->reg_flags & RegVRex)) | |
10193 | { | |
86fa6981 L |
10194 | if (i.vec_encoding == vex_encoding_default) |
10195 | i.vec_encoding = vex_encoding_evex; | |
10196 | ||
43234a1e | 10197 | if (!cpu_arch_flags.bitfield.cpuvrex |
86fa6981 | 10198 | || i.vec_encoding != vex_encoding_evex |
43234a1e L |
10199 | || flag_code != CODE_64BIT) |
10200 | return (const reg_entry *) NULL; | |
43234a1e L |
10201 | } |
10202 | ||
a60de03c | 10203 | if (((r->reg_flags & (RegRex64 | RegRex)) |
dc821c5f | 10204 | || r->reg_type.bitfield.qword) |
40fb9820 | 10205 | && (!cpu_arch_flags.bitfield.cpulm |
0dfbf9d7 | 10206 | || !operand_type_equal (&r->reg_type, &control)) |
1ae00879 | 10207 | && flag_code != CODE_64BIT) |
20f0a1fc | 10208 | return (const reg_entry *) NULL; |
1ae00879 | 10209 | |
b7240065 JB |
10210 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
10211 | return (const reg_entry *) NULL; | |
10212 | ||
252b5132 RH |
10213 | return r; |
10214 | } | |
4d1bb795 JB |
10215 | |
10216 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
10217 | ||
10218 | static const reg_entry * | |
10219 | parse_register (char *reg_string, char **end_op) | |
10220 | { | |
10221 | const reg_entry *r; | |
10222 | ||
10223 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
10224 | r = parse_real_register (reg_string, end_op); | |
10225 | else | |
10226 | r = NULL; | |
10227 | if (!r) | |
10228 | { | |
10229 | char *save = input_line_pointer; | |
10230 | char c; | |
10231 | symbolS *symbolP; | |
10232 | ||
10233 | input_line_pointer = reg_string; | |
d02603dc | 10234 | c = get_symbol_name (®_string); |
4d1bb795 JB |
10235 | symbolP = symbol_find (reg_string); |
10236 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
10237 | { | |
10238 | const expressionS *e = symbol_get_value_expression (symbolP); | |
10239 | ||
0398aac5 | 10240 | know (e->X_op == O_register); |
4eed87de | 10241 | know (e->X_add_number >= 0 |
c3fe08fa | 10242 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 10243 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 10244 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 10245 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
10246 | *end_op = input_line_pointer; |
10247 | } | |
10248 | *input_line_pointer = c; | |
10249 | input_line_pointer = save; | |
10250 | } | |
10251 | return r; | |
10252 | } | |
10253 | ||
10254 | int | |
10255 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
10256 | { | |
10257 | const reg_entry *r; | |
10258 | char *end = input_line_pointer; | |
10259 | ||
10260 | *end = *nextcharP; | |
10261 | r = parse_register (name, &input_line_pointer); | |
10262 | if (r && end <= input_line_pointer) | |
10263 | { | |
10264 | *nextcharP = *input_line_pointer; | |
10265 | *input_line_pointer = 0; | |
10266 | e->X_op = O_register; | |
10267 | e->X_add_number = r - i386_regtab; | |
10268 | return 1; | |
10269 | } | |
10270 | input_line_pointer = end; | |
10271 | *end = 0; | |
ee86248c | 10272 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
10273 | } |
10274 | ||
10275 | void | |
10276 | md_operand (expressionS *e) | |
10277 | { | |
ee86248c JB |
10278 | char *end; |
10279 | const reg_entry *r; | |
4d1bb795 | 10280 | |
ee86248c JB |
10281 | switch (*input_line_pointer) |
10282 | { | |
10283 | case REGISTER_PREFIX: | |
10284 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
10285 | if (r) |
10286 | { | |
10287 | e->X_op = O_register; | |
10288 | e->X_add_number = r - i386_regtab; | |
10289 | input_line_pointer = end; | |
10290 | } | |
ee86248c JB |
10291 | break; |
10292 | ||
10293 | case '[': | |
9c2799c2 | 10294 | gas_assert (intel_syntax); |
ee86248c JB |
10295 | end = input_line_pointer++; |
10296 | expression (e); | |
10297 | if (*input_line_pointer == ']') | |
10298 | { | |
10299 | ++input_line_pointer; | |
10300 | e->X_op_symbol = make_expr_symbol (e); | |
10301 | e->X_add_symbol = NULL; | |
10302 | e->X_add_number = 0; | |
10303 | e->X_op = O_index; | |
10304 | } | |
10305 | else | |
10306 | { | |
10307 | e->X_op = O_absent; | |
10308 | input_line_pointer = end; | |
10309 | } | |
10310 | break; | |
4d1bb795 JB |
10311 | } |
10312 | } | |
10313 | ||
252b5132 | 10314 | \f |
4cc782b5 | 10315 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 10316 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 10317 | #else |
b6f8c7c4 | 10318 | const char *md_shortopts = "qnO::"; |
252b5132 | 10319 | #endif |
6e0b89ee | 10320 | |
3e73aa7c | 10321 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
10322 | #define OPTION_64 (OPTION_MD_BASE + 1) |
10323 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
10324 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
10325 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
10326 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
10327 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
10328 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
10329 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 10330 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 10331 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 10332 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
10333 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
10334 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
10335 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 10336 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
10337 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
10338 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 10339 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 10340 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 10341 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 10342 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
10343 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
10344 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 10345 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b3b91714 | 10346 | |
99ad8390 NC |
10347 | struct option md_longopts[] = |
10348 | { | |
3e73aa7c | 10349 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 10350 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 10351 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 10352 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
10353 | #endif |
10354 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 10355 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 10356 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
6e0b89ee | 10357 | #endif |
b3b91714 | 10358 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
10359 | {"march", required_argument, NULL, OPTION_MARCH}, |
10360 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
10361 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
10362 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
10363 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
10364 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 10365 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 10366 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 10367 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 10368 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
7e8b059b | 10369 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
10370 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
10371 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
10372 | # if defined (TE_PE) || defined (TE_PEP) |
10373 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
10374 | #endif | |
d1982f93 | 10375 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 10376 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 10377 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 10378 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
5db04b09 L |
10379 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
10380 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
10381 | {NULL, no_argument, NULL, 0} |
10382 | }; | |
10383 | size_t md_longopts_size = sizeof (md_longopts); | |
10384 | ||
10385 | int | |
17b9d67d | 10386 | md_parse_option (int c, const char *arg) |
252b5132 | 10387 | { |
91d6fa6a | 10388 | unsigned int j; |
293f5f65 | 10389 | char *arch, *next, *saved; |
9103f4f4 | 10390 | |
252b5132 RH |
10391 | switch (c) |
10392 | { | |
12b55ccc L |
10393 | case 'n': |
10394 | optimize_align_code = 0; | |
10395 | break; | |
10396 | ||
a38cf1db AM |
10397 | case 'q': |
10398 | quiet_warnings = 1; | |
252b5132 RH |
10399 | break; |
10400 | ||
10401 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
10402 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
10403 | should be emitted or not. FIXME: Not implemented. */ | |
10404 | case 'Q': | |
252b5132 RH |
10405 | break; |
10406 | ||
10407 | /* -V: SVR4 argument to print version ID. */ | |
10408 | case 'V': | |
10409 | print_version_id (); | |
10410 | break; | |
10411 | ||
a38cf1db AM |
10412 | /* -k: Ignore for FreeBSD compatibility. */ |
10413 | case 'k': | |
252b5132 | 10414 | break; |
4cc782b5 ILT |
10415 | |
10416 | case 's': | |
10417 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 10418 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 10419 | break; |
8dcea932 L |
10420 | |
10421 | case OPTION_MSHARED: | |
10422 | shared = 1; | |
10423 | break; | |
99ad8390 | 10424 | #endif |
321098a5 | 10425 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 10426 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
10427 | case OPTION_64: |
10428 | { | |
10429 | const char **list, **l; | |
10430 | ||
3e73aa7c JH |
10431 | list = bfd_target_list (); |
10432 | for (l = list; *l != NULL; l++) | |
8620418b | 10433 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
10434 | || strcmp (*l, "coff-x86-64") == 0 |
10435 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
10436 | || strcmp (*l, "pei-x86-64") == 0 |
10437 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
10438 | { |
10439 | default_arch = "x86_64"; | |
10440 | break; | |
10441 | } | |
3e73aa7c | 10442 | if (*l == NULL) |
2b5d6a91 | 10443 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
10444 | free (list); |
10445 | } | |
10446 | break; | |
10447 | #endif | |
252b5132 | 10448 | |
351f65ca | 10449 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 10450 | case OPTION_X32: |
351f65ca L |
10451 | if (IS_ELF) |
10452 | { | |
10453 | const char **list, **l; | |
10454 | ||
10455 | list = bfd_target_list (); | |
10456 | for (l = list; *l != NULL; l++) | |
10457 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
10458 | { | |
10459 | default_arch = "x86_64:32"; | |
10460 | break; | |
10461 | } | |
10462 | if (*l == NULL) | |
2b5d6a91 | 10463 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
10464 | free (list); |
10465 | } | |
10466 | else | |
10467 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
10468 | break; | |
10469 | #endif | |
10470 | ||
6e0b89ee AM |
10471 | case OPTION_32: |
10472 | default_arch = "i386"; | |
10473 | break; | |
10474 | ||
b3b91714 AM |
10475 | case OPTION_DIVIDE: |
10476 | #ifdef SVR4_COMMENT_CHARS | |
10477 | { | |
10478 | char *n, *t; | |
10479 | const char *s; | |
10480 | ||
add39d23 | 10481 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
10482 | t = n; |
10483 | for (s = i386_comment_chars; *s != '\0'; s++) | |
10484 | if (*s != '/') | |
10485 | *t++ = *s; | |
10486 | *t = '\0'; | |
10487 | i386_comment_chars = n; | |
10488 | } | |
10489 | #endif | |
10490 | break; | |
10491 | ||
9103f4f4 | 10492 | case OPTION_MARCH: |
293f5f65 L |
10493 | saved = xstrdup (arg); |
10494 | arch = saved; | |
10495 | /* Allow -march=+nosse. */ | |
10496 | if (*arch == '+') | |
10497 | arch++; | |
6305a203 | 10498 | do |
9103f4f4 | 10499 | { |
6305a203 | 10500 | if (*arch == '.') |
2b5d6a91 | 10501 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
10502 | next = strchr (arch, '+'); |
10503 | if (next) | |
10504 | *next++ = '\0'; | |
91d6fa6a | 10505 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 10506 | { |
91d6fa6a | 10507 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 10508 | { |
6305a203 | 10509 | /* Processor. */ |
1ded5609 JB |
10510 | if (! cpu_arch[j].flags.bitfield.cpui386) |
10511 | continue; | |
10512 | ||
91d6fa6a | 10513 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 10514 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
10515 | cpu_arch_flags = cpu_arch[j].flags; |
10516 | cpu_arch_isa = cpu_arch[j].type; | |
10517 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
10518 | if (!cpu_arch_tune_set) |
10519 | { | |
10520 | cpu_arch_tune = cpu_arch_isa; | |
10521 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
10522 | } | |
10523 | break; | |
10524 | } | |
91d6fa6a NC |
10525 | else if (*cpu_arch [j].name == '.' |
10526 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 10527 | { |
33eaf5de | 10528 | /* ISA extension. */ |
6305a203 | 10529 | i386_cpu_flags flags; |
309d3373 | 10530 | |
293f5f65 L |
10531 | flags = cpu_flags_or (cpu_arch_flags, |
10532 | cpu_arch[j].flags); | |
81486035 | 10533 | |
5b64d091 | 10534 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
10535 | { |
10536 | if (cpu_sub_arch_name) | |
10537 | { | |
10538 | char *name = cpu_sub_arch_name; | |
10539 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 10540 | cpu_arch[j].name, |
1bf57e9f | 10541 | (const char *) NULL); |
6305a203 L |
10542 | free (name); |
10543 | } | |
10544 | else | |
91d6fa6a | 10545 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 10546 | cpu_arch_flags = flags; |
a586129e | 10547 | cpu_arch_isa_flags = flags; |
6305a203 | 10548 | } |
0089dace L |
10549 | else |
10550 | cpu_arch_isa_flags | |
10551 | = cpu_flags_or (cpu_arch_isa_flags, | |
10552 | cpu_arch[j].flags); | |
6305a203 | 10553 | break; |
ccc9c027 | 10554 | } |
9103f4f4 | 10555 | } |
6305a203 | 10556 | |
293f5f65 L |
10557 | if (j >= ARRAY_SIZE (cpu_arch)) |
10558 | { | |
33eaf5de | 10559 | /* Disable an ISA extension. */ |
293f5f65 L |
10560 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
10561 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
10562 | { | |
10563 | i386_cpu_flags flags; | |
10564 | ||
10565 | flags = cpu_flags_and_not (cpu_arch_flags, | |
10566 | cpu_noarch[j].flags); | |
10567 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
10568 | { | |
10569 | if (cpu_sub_arch_name) | |
10570 | { | |
10571 | char *name = cpu_sub_arch_name; | |
10572 | cpu_sub_arch_name = concat (arch, | |
10573 | (const char *) NULL); | |
10574 | free (name); | |
10575 | } | |
10576 | else | |
10577 | cpu_sub_arch_name = xstrdup (arch); | |
10578 | cpu_arch_flags = flags; | |
10579 | cpu_arch_isa_flags = flags; | |
10580 | } | |
10581 | break; | |
10582 | } | |
10583 | ||
10584 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
10585 | j = ARRAY_SIZE (cpu_arch); | |
10586 | } | |
10587 | ||
91d6fa6a | 10588 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 10589 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
10590 | |
10591 | arch = next; | |
9103f4f4 | 10592 | } |
293f5f65 L |
10593 | while (next != NULL); |
10594 | free (saved); | |
9103f4f4 L |
10595 | break; |
10596 | ||
10597 | case OPTION_MTUNE: | |
10598 | if (*arg == '.') | |
2b5d6a91 | 10599 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 10600 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 10601 | { |
91d6fa6a | 10602 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 10603 | { |
ccc9c027 | 10604 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
10605 | cpu_arch_tune = cpu_arch [j].type; |
10606 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
10607 | break; |
10608 | } | |
10609 | } | |
91d6fa6a | 10610 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 10611 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
10612 | break; |
10613 | ||
1efbbeb4 L |
10614 | case OPTION_MMNEMONIC: |
10615 | if (strcasecmp (arg, "att") == 0) | |
10616 | intel_mnemonic = 0; | |
10617 | else if (strcasecmp (arg, "intel") == 0) | |
10618 | intel_mnemonic = 1; | |
10619 | else | |
2b5d6a91 | 10620 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
10621 | break; |
10622 | ||
10623 | case OPTION_MSYNTAX: | |
10624 | if (strcasecmp (arg, "att") == 0) | |
10625 | intel_syntax = 0; | |
10626 | else if (strcasecmp (arg, "intel") == 0) | |
10627 | intel_syntax = 1; | |
10628 | else | |
2b5d6a91 | 10629 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
10630 | break; |
10631 | ||
10632 | case OPTION_MINDEX_REG: | |
10633 | allow_index_reg = 1; | |
10634 | break; | |
10635 | ||
10636 | case OPTION_MNAKED_REG: | |
10637 | allow_naked_reg = 1; | |
10638 | break; | |
10639 | ||
c0f3af97 L |
10640 | case OPTION_MSSE2AVX: |
10641 | sse2avx = 1; | |
10642 | break; | |
10643 | ||
daf50ae7 L |
10644 | case OPTION_MSSE_CHECK: |
10645 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 10646 | sse_check = check_error; |
daf50ae7 | 10647 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 10648 | sse_check = check_warning; |
daf50ae7 | 10649 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 10650 | sse_check = check_none; |
daf50ae7 | 10651 | else |
2b5d6a91 | 10652 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
10653 | break; |
10654 | ||
7bab8ab5 JB |
10655 | case OPTION_MOPERAND_CHECK: |
10656 | if (strcasecmp (arg, "error") == 0) | |
10657 | operand_check = check_error; | |
10658 | else if (strcasecmp (arg, "warning") == 0) | |
10659 | operand_check = check_warning; | |
10660 | else if (strcasecmp (arg, "none") == 0) | |
10661 | operand_check = check_none; | |
10662 | else | |
10663 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
10664 | break; | |
10665 | ||
539f890d L |
10666 | case OPTION_MAVXSCALAR: |
10667 | if (strcasecmp (arg, "128") == 0) | |
10668 | avxscalar = vex128; | |
10669 | else if (strcasecmp (arg, "256") == 0) | |
10670 | avxscalar = vex256; | |
10671 | else | |
2b5d6a91 | 10672 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
10673 | break; |
10674 | ||
7e8b059b L |
10675 | case OPTION_MADD_BND_PREFIX: |
10676 | add_bnd_prefix = 1; | |
10677 | break; | |
10678 | ||
43234a1e L |
10679 | case OPTION_MEVEXLIG: |
10680 | if (strcmp (arg, "128") == 0) | |
10681 | evexlig = evexl128; | |
10682 | else if (strcmp (arg, "256") == 0) | |
10683 | evexlig = evexl256; | |
10684 | else if (strcmp (arg, "512") == 0) | |
10685 | evexlig = evexl512; | |
10686 | else | |
10687 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
10688 | break; | |
10689 | ||
d3d3c6db IT |
10690 | case OPTION_MEVEXRCIG: |
10691 | if (strcmp (arg, "rne") == 0) | |
10692 | evexrcig = rne; | |
10693 | else if (strcmp (arg, "rd") == 0) | |
10694 | evexrcig = rd; | |
10695 | else if (strcmp (arg, "ru") == 0) | |
10696 | evexrcig = ru; | |
10697 | else if (strcmp (arg, "rz") == 0) | |
10698 | evexrcig = rz; | |
10699 | else | |
10700 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
10701 | break; | |
10702 | ||
43234a1e L |
10703 | case OPTION_MEVEXWIG: |
10704 | if (strcmp (arg, "0") == 0) | |
10705 | evexwig = evexw0; | |
10706 | else if (strcmp (arg, "1") == 0) | |
10707 | evexwig = evexw1; | |
10708 | else | |
10709 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
10710 | break; | |
10711 | ||
167ad85b TG |
10712 | # if defined (TE_PE) || defined (TE_PEP) |
10713 | case OPTION_MBIG_OBJ: | |
10714 | use_big_obj = 1; | |
10715 | break; | |
10716 | #endif | |
10717 | ||
d1982f93 | 10718 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
10719 | if (strcasecmp (arg, "yes") == 0) |
10720 | omit_lock_prefix = 1; | |
10721 | else if (strcasecmp (arg, "no") == 0) | |
10722 | omit_lock_prefix = 0; | |
10723 | else | |
10724 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
10725 | break; | |
10726 | ||
e4e00185 AS |
10727 | case OPTION_MFENCE_AS_LOCK_ADD: |
10728 | if (strcasecmp (arg, "yes") == 0) | |
10729 | avoid_fence = 1; | |
10730 | else if (strcasecmp (arg, "no") == 0) | |
10731 | avoid_fence = 0; | |
10732 | else | |
10733 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
10734 | break; | |
10735 | ||
0cb4071e L |
10736 | case OPTION_MRELAX_RELOCATIONS: |
10737 | if (strcasecmp (arg, "yes") == 0) | |
10738 | generate_relax_relocations = 1; | |
10739 | else if (strcasecmp (arg, "no") == 0) | |
10740 | generate_relax_relocations = 0; | |
10741 | else | |
10742 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
10743 | break; | |
10744 | ||
5db04b09 | 10745 | case OPTION_MAMD64: |
e89c5eaa | 10746 | intel64 = 0; |
5db04b09 L |
10747 | break; |
10748 | ||
10749 | case OPTION_MINTEL64: | |
e89c5eaa | 10750 | intel64 = 1; |
5db04b09 L |
10751 | break; |
10752 | ||
b6f8c7c4 L |
10753 | case 'O': |
10754 | if (arg == NULL) | |
10755 | { | |
10756 | optimize = 1; | |
10757 | /* Turn off -Os. */ | |
10758 | optimize_for_space = 0; | |
10759 | } | |
10760 | else if (*arg == 's') | |
10761 | { | |
10762 | optimize_for_space = 1; | |
10763 | /* Turn on all encoding optimizations. */ | |
10764 | optimize = -1; | |
10765 | } | |
10766 | else | |
10767 | { | |
10768 | optimize = atoi (arg); | |
10769 | /* Turn off -Os. */ | |
10770 | optimize_for_space = 0; | |
10771 | } | |
10772 | break; | |
10773 | ||
252b5132 RH |
10774 | default: |
10775 | return 0; | |
10776 | } | |
10777 | return 1; | |
10778 | } | |
10779 | ||
8a2c8fef L |
10780 | #define MESSAGE_TEMPLATE \ |
10781 | " " | |
10782 | ||
293f5f65 L |
10783 | static char * |
10784 | output_message (FILE *stream, char *p, char *message, char *start, | |
10785 | int *left_p, const char *name, int len) | |
10786 | { | |
10787 | int size = sizeof (MESSAGE_TEMPLATE); | |
10788 | int left = *left_p; | |
10789 | ||
10790 | /* Reserve 2 spaces for ", " or ",\0" */ | |
10791 | left -= len + 2; | |
10792 | ||
10793 | /* Check if there is any room. */ | |
10794 | if (left >= 0) | |
10795 | { | |
10796 | if (p != start) | |
10797 | { | |
10798 | *p++ = ','; | |
10799 | *p++ = ' '; | |
10800 | } | |
10801 | p = mempcpy (p, name, len); | |
10802 | } | |
10803 | else | |
10804 | { | |
10805 | /* Output the current message now and start a new one. */ | |
10806 | *p++ = ','; | |
10807 | *p = '\0'; | |
10808 | fprintf (stream, "%s\n", message); | |
10809 | p = start; | |
10810 | left = size - (start - message) - len - 2; | |
10811 | ||
10812 | gas_assert (left >= 0); | |
10813 | ||
10814 | p = mempcpy (p, name, len); | |
10815 | } | |
10816 | ||
10817 | *left_p = left; | |
10818 | return p; | |
10819 | } | |
10820 | ||
8a2c8fef | 10821 | static void |
1ded5609 | 10822 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
10823 | { |
10824 | static char message[] = MESSAGE_TEMPLATE; | |
10825 | char *start = message + 27; | |
10826 | char *p; | |
10827 | int size = sizeof (MESSAGE_TEMPLATE); | |
10828 | int left; | |
10829 | const char *name; | |
10830 | int len; | |
10831 | unsigned int j; | |
10832 | ||
10833 | p = start; | |
10834 | left = size - (start - message); | |
10835 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
10836 | { | |
10837 | /* Should it be skipped? */ | |
10838 | if (cpu_arch [j].skip) | |
10839 | continue; | |
10840 | ||
10841 | name = cpu_arch [j].name; | |
10842 | len = cpu_arch [j].len; | |
10843 | if (*name == '.') | |
10844 | { | |
10845 | /* It is an extension. Skip if we aren't asked to show it. */ | |
10846 | if (ext) | |
10847 | { | |
10848 | name++; | |
10849 | len--; | |
10850 | } | |
10851 | else | |
10852 | continue; | |
10853 | } | |
10854 | else if (ext) | |
10855 | { | |
10856 | /* It is an processor. Skip if we show only extension. */ | |
10857 | continue; | |
10858 | } | |
1ded5609 JB |
10859 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
10860 | { | |
10861 | /* It is an impossible processor - skip. */ | |
10862 | continue; | |
10863 | } | |
8a2c8fef | 10864 | |
293f5f65 | 10865 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
10866 | } |
10867 | ||
293f5f65 L |
10868 | /* Display disabled extensions. */ |
10869 | if (ext) | |
10870 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
10871 | { | |
10872 | name = cpu_noarch [j].name; | |
10873 | len = cpu_noarch [j].len; | |
10874 | p = output_message (stream, p, message, start, &left, name, | |
10875 | len); | |
10876 | } | |
10877 | ||
8a2c8fef L |
10878 | *p = '\0'; |
10879 | fprintf (stream, "%s\n", message); | |
10880 | } | |
10881 | ||
252b5132 | 10882 | void |
8a2c8fef | 10883 | md_show_usage (FILE *stream) |
252b5132 | 10884 | { |
4cc782b5 ILT |
10885 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10886 | fprintf (stream, _("\ | |
a38cf1db AM |
10887 | -Q ignored\n\ |
10888 | -V print assembler version number\n\ | |
b3b91714 AM |
10889 | -k ignored\n")); |
10890 | #endif | |
10891 | fprintf (stream, _("\ | |
12b55ccc | 10892 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
10893 | -q quieten some warnings\n")); |
10894 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
10895 | fprintf (stream, _("\ | |
a38cf1db | 10896 | -s ignored\n")); |
b3b91714 | 10897 | #endif |
321098a5 L |
10898 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
10899 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 10900 | fprintf (stream, _("\ |
570561f7 | 10901 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 10902 | #endif |
b3b91714 AM |
10903 | #ifdef SVR4_COMMENT_CHARS |
10904 | fprintf (stream, _("\ | |
10905 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
10906 | #else |
10907 | fprintf (stream, _("\ | |
b3b91714 | 10908 | --divide ignored\n")); |
4cc782b5 | 10909 | #endif |
9103f4f4 | 10910 | fprintf (stream, _("\ |
6305a203 | 10911 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 10912 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 10913 | show_arch (stream, 0, 1); |
8a2c8fef L |
10914 | fprintf (stream, _("\ |
10915 | EXTENSION is combination of:\n")); | |
1ded5609 | 10916 | show_arch (stream, 1, 0); |
6305a203 | 10917 | fprintf (stream, _("\ |
8a2c8fef | 10918 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 10919 | show_arch (stream, 0, 0); |
ba104c83 | 10920 | fprintf (stream, _("\ |
c0f3af97 L |
10921 | -msse2avx encode SSE instructions with VEX prefix\n")); |
10922 | fprintf (stream, _("\ | |
daf50ae7 L |
10923 | -msse-check=[none|error|warning]\n\ |
10924 | check SSE instructions\n")); | |
10925 | fprintf (stream, _("\ | |
7bab8ab5 JB |
10926 | -moperand-check=[none|error|warning]\n\ |
10927 | check operand combinations for validity\n")); | |
10928 | fprintf (stream, _("\ | |
539f890d L |
10929 | -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\ |
10930 | length\n")); | |
10931 | fprintf (stream, _("\ | |
43234a1e L |
10932 | -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\ |
10933 | length\n")); | |
10934 | fprintf (stream, _("\ | |
10935 | -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\ | |
10936 | for EVEX.W bit ignored instructions\n")); | |
10937 | fprintf (stream, _("\ | |
d3d3c6db IT |
10938 | -mevexrcig=[rne|rd|ru|rz]\n\ |
10939 | encode EVEX instructions with specific EVEX.RC value\n\ | |
10940 | for SAE-only ignored instructions\n")); | |
10941 | fprintf (stream, _("\ | |
ba104c83 L |
10942 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); |
10943 | fprintf (stream, _("\ | |
10944 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); | |
10945 | fprintf (stream, _("\ | |
10946 | -mindex-reg support pseudo index registers\n")); | |
10947 | fprintf (stream, _("\ | |
10948 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
10949 | fprintf (stream, _("\ | |
7e8b059b | 10950 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
8dcea932 L |
10951 | fprintf (stream, _("\ |
10952 | -mshared disable branch optimization for shared code\n")); | |
167ad85b TG |
10953 | # if defined (TE_PE) || defined (TE_PEP) |
10954 | fprintf (stream, _("\ | |
10955 | -mbig-obj generate big object files\n")); | |
10956 | #endif | |
d022bddd IT |
10957 | fprintf (stream, _("\ |
10958 | -momit-lock-prefix=[no|yes]\n\ | |
10959 | strip all lock prefixes\n")); | |
5db04b09 | 10960 | fprintf (stream, _("\ |
e4e00185 AS |
10961 | -mfence-as-lock-add=[no|yes]\n\ |
10962 | encode lfence, mfence and sfence as\n\ | |
10963 | lock addl $0x0, (%%{re}sp)\n")); | |
10964 | fprintf (stream, _("\ | |
0cb4071e L |
10965 | -mrelax-relocations=[no|yes]\n\ |
10966 | generate relax relocations\n")); | |
10967 | fprintf (stream, _("\ | |
5db04b09 L |
10968 | -mamd64 accept only AMD64 ISA\n")); |
10969 | fprintf (stream, _("\ | |
10970 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
10971 | } |
10972 | ||
3e73aa7c | 10973 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 10974 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 10975 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
10976 | |
10977 | /* Pick the target format to use. */ | |
10978 | ||
47926f60 | 10979 | const char * |
e3bb37b5 | 10980 | i386_target_format (void) |
252b5132 | 10981 | { |
351f65ca L |
10982 | if (!strncmp (default_arch, "x86_64", 6)) |
10983 | { | |
10984 | update_code_flag (CODE_64BIT, 1); | |
10985 | if (default_arch[6] == '\0') | |
7f56bc95 | 10986 | x86_elf_abi = X86_64_ABI; |
351f65ca | 10987 | else |
7f56bc95 | 10988 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 10989 | } |
3e73aa7c | 10990 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 10991 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
10992 | else if (!strcmp (default_arch, "iamcu")) |
10993 | { | |
10994 | update_code_flag (CODE_32BIT, 1); | |
10995 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
10996 | { | |
10997 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
10998 | cpu_arch_name = "iamcu"; | |
10999 | cpu_sub_arch_name = NULL; | |
11000 | cpu_arch_flags = iamcu_flags; | |
11001 | cpu_arch_isa = PROCESSOR_IAMCU; | |
11002 | cpu_arch_isa_flags = iamcu_flags; | |
11003 | if (!cpu_arch_tune_set) | |
11004 | { | |
11005 | cpu_arch_tune = cpu_arch_isa; | |
11006 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
11007 | } | |
11008 | } | |
8d471ec1 | 11009 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
11010 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
11011 | cpu_arch_name); | |
11012 | } | |
3e73aa7c | 11013 | else |
2b5d6a91 | 11014 | as_fatal (_("unknown architecture")); |
89507696 JB |
11015 | |
11016 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
11017 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11018 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
11019 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11020 | ||
252b5132 RH |
11021 | switch (OUTPUT_FLAVOR) |
11022 | { | |
9384f2ff | 11023 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 11024 | case bfd_target_aout_flavour: |
47926f60 | 11025 | return AOUT_TARGET_FORMAT; |
4c63da97 | 11026 | #endif |
9384f2ff AM |
11027 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
11028 | # if defined (TE_PE) || defined (TE_PEP) | |
11029 | case bfd_target_coff_flavour: | |
167ad85b TG |
11030 | if (flag_code == CODE_64BIT) |
11031 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
11032 | else | |
11033 | return "pe-i386"; | |
9384f2ff | 11034 | # elif defined (TE_GO32) |
0561d57c JK |
11035 | case bfd_target_coff_flavour: |
11036 | return "coff-go32"; | |
9384f2ff | 11037 | # else |
252b5132 RH |
11038 | case bfd_target_coff_flavour: |
11039 | return "coff-i386"; | |
9384f2ff | 11040 | # endif |
4c63da97 | 11041 | #endif |
3e73aa7c | 11042 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 11043 | case bfd_target_elf_flavour: |
3e73aa7c | 11044 | { |
351f65ca L |
11045 | const char *format; |
11046 | ||
11047 | switch (x86_elf_abi) | |
4fa24527 | 11048 | { |
351f65ca L |
11049 | default: |
11050 | format = ELF_TARGET_FORMAT; | |
11051 | break; | |
7f56bc95 | 11052 | case X86_64_ABI: |
351f65ca | 11053 | use_rela_relocations = 1; |
4fa24527 | 11054 | object_64bit = 1; |
351f65ca L |
11055 | format = ELF_TARGET_FORMAT64; |
11056 | break; | |
7f56bc95 | 11057 | case X86_64_X32_ABI: |
4fa24527 | 11058 | use_rela_relocations = 1; |
351f65ca | 11059 | object_64bit = 1; |
862be3fb | 11060 | disallow_64bit_reloc = 1; |
351f65ca L |
11061 | format = ELF_TARGET_FORMAT32; |
11062 | break; | |
4fa24527 | 11063 | } |
3632d14b | 11064 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 11065 | { |
7f56bc95 | 11066 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
11067 | as_fatal (_("Intel L1OM is 64bit only")); |
11068 | return ELF_TARGET_L1OM_FORMAT; | |
11069 | } | |
b49f93f6 | 11070 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
11071 | { |
11072 | if (x86_elf_abi != X86_64_ABI) | |
11073 | as_fatal (_("Intel K1OM is 64bit only")); | |
11074 | return ELF_TARGET_K1OM_FORMAT; | |
11075 | } | |
81486035 L |
11076 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
11077 | { | |
11078 | if (x86_elf_abi != I386_ABI) | |
11079 | as_fatal (_("Intel MCU is 32bit only")); | |
11080 | return ELF_TARGET_IAMCU_FORMAT; | |
11081 | } | |
8a9036a4 | 11082 | else |
351f65ca | 11083 | return format; |
3e73aa7c | 11084 | } |
e57f8c65 TG |
11085 | #endif |
11086 | #if defined (OBJ_MACH_O) | |
11087 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
11088 | if (flag_code == CODE_64BIT) |
11089 | { | |
11090 | use_rela_relocations = 1; | |
11091 | object_64bit = 1; | |
11092 | return "mach-o-x86-64"; | |
11093 | } | |
11094 | else | |
11095 | return "mach-o-i386"; | |
4c63da97 | 11096 | #endif |
252b5132 RH |
11097 | default: |
11098 | abort (); | |
11099 | return NULL; | |
11100 | } | |
11101 | } | |
11102 | ||
47926f60 | 11103 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 11104 | \f |
252b5132 | 11105 | symbolS * |
7016a5d5 | 11106 | md_undefined_symbol (char *name) |
252b5132 | 11107 | { |
18dc2407 ILT |
11108 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
11109 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
11110 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
11111 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
11112 | { |
11113 | if (!GOT_symbol) | |
11114 | { | |
11115 | if (symbol_find (name)) | |
11116 | as_bad (_("GOT already in symbol table")); | |
11117 | GOT_symbol = symbol_new (name, undefined_section, | |
11118 | (valueT) 0, &zero_address_frag); | |
11119 | }; | |
11120 | return GOT_symbol; | |
11121 | } | |
252b5132 RH |
11122 | return 0; |
11123 | } | |
11124 | ||
11125 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 11126 | |
252b5132 | 11127 | valueT |
7016a5d5 | 11128 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 11129 | { |
4c63da97 AM |
11130 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
11131 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
11132 | { | |
11133 | /* For a.out, force the section size to be aligned. If we don't do | |
11134 | this, BFD will align it for us, but it will not write out the | |
11135 | final bytes of the section. This may be a bug in BFD, but it is | |
11136 | easier to fix it here since that is how the other a.out targets | |
11137 | work. */ | |
11138 | int align; | |
11139 | ||
11140 | align = bfd_get_section_alignment (stdoutput, segment); | |
8d3842cd | 11141 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 11142 | } |
252b5132 RH |
11143 | #endif |
11144 | ||
11145 | return size; | |
11146 | } | |
11147 | ||
11148 | /* On the i386, PC-relative offsets are relative to the start of the | |
11149 | next instruction. That is, the address of the offset, plus its | |
11150 | size, since the offset is always the last part of the insn. */ | |
11151 | ||
11152 | long | |
e3bb37b5 | 11153 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
11154 | { |
11155 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
11156 | } | |
11157 | ||
11158 | #ifndef I386COFF | |
11159 | ||
11160 | static void | |
e3bb37b5 | 11161 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 11162 | { |
29b0f896 | 11163 | int temp; |
252b5132 | 11164 | |
8a75718c JB |
11165 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11166 | if (IS_ELF) | |
11167 | obj_elf_section_change_hook (); | |
11168 | #endif | |
252b5132 RH |
11169 | temp = get_absolute_expression (); |
11170 | subseg_set (bss_section, (subsegT) temp); | |
11171 | demand_empty_rest_of_line (); | |
11172 | } | |
11173 | ||
11174 | #endif | |
11175 | ||
252b5132 | 11176 | void |
e3bb37b5 | 11177 | i386_validate_fix (fixS *fixp) |
252b5132 | 11178 | { |
02a86693 | 11179 | if (fixp->fx_subsy) |
252b5132 | 11180 | { |
02a86693 | 11181 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 11182 | { |
02a86693 L |
11183 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
11184 | { | |
11185 | if (!object_64bit) | |
11186 | abort (); | |
11187 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11188 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
11189 | fixp->fx_r_type = (fixp->fx_tcbit |
11190 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
11191 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
11192 | else |
11193 | #endif | |
11194 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
11195 | } | |
d6ab8113 | 11196 | else |
02a86693 L |
11197 | { |
11198 | if (!object_64bit) | |
11199 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
11200 | else | |
11201 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
11202 | } | |
11203 | fixp->fx_subsy = 0; | |
23df1078 | 11204 | } |
252b5132 | 11205 | } |
02a86693 L |
11206 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11207 | else if (!object_64bit) | |
11208 | { | |
11209 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
11210 | && fixp->fx_tcbit2) | |
11211 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
11212 | } | |
11213 | #endif | |
252b5132 RH |
11214 | } |
11215 | ||
252b5132 | 11216 | arelent * |
7016a5d5 | 11217 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
11218 | { |
11219 | arelent *rel; | |
11220 | bfd_reloc_code_real_type code; | |
11221 | ||
11222 | switch (fixp->fx_r_type) | |
11223 | { | |
8ce3d284 | 11224 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
11225 | case BFD_RELOC_SIZE32: |
11226 | case BFD_RELOC_SIZE64: | |
11227 | if (S_IS_DEFINED (fixp->fx_addsy) | |
11228 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
11229 | { | |
11230 | /* Resolve size relocation against local symbol to size of | |
11231 | the symbol plus addend. */ | |
11232 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
11233 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
11234 | && !fits_in_unsigned_long (value)) | |
11235 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11236 | _("symbol size computation overflow")); | |
11237 | fixp->fx_addsy = NULL; | |
11238 | fixp->fx_subsy = NULL; | |
11239 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
11240 | return NULL; | |
11241 | } | |
8ce3d284 | 11242 | #endif |
1a0670f3 | 11243 | /* Fall through. */ |
8fd4256d | 11244 | |
3e73aa7c JH |
11245 | case BFD_RELOC_X86_64_PLT32: |
11246 | case BFD_RELOC_X86_64_GOT32: | |
11247 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
11248 | case BFD_RELOC_X86_64_GOTPCRELX: |
11249 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
11250 | case BFD_RELOC_386_PLT32: |
11251 | case BFD_RELOC_386_GOT32: | |
02a86693 | 11252 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
11253 | case BFD_RELOC_386_GOTOFF: |
11254 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
11255 | case BFD_RELOC_386_TLS_GD: |
11256 | case BFD_RELOC_386_TLS_LDM: | |
11257 | case BFD_RELOC_386_TLS_LDO_32: | |
11258 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
11259 | case BFD_RELOC_386_TLS_IE: |
11260 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
11261 | case BFD_RELOC_386_TLS_LE_32: |
11262 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
11263 | case BFD_RELOC_386_TLS_GOTDESC: |
11264 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
11265 | case BFD_RELOC_X86_64_TLSGD: |
11266 | case BFD_RELOC_X86_64_TLSLD: | |
11267 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 11268 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
11269 | case BFD_RELOC_X86_64_GOTTPOFF: |
11270 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
11271 | case BFD_RELOC_X86_64_TPOFF64: |
11272 | case BFD_RELOC_X86_64_GOTOFF64: | |
11273 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
11274 | case BFD_RELOC_X86_64_GOT64: |
11275 | case BFD_RELOC_X86_64_GOTPCREL64: | |
11276 | case BFD_RELOC_X86_64_GOTPC64: | |
11277 | case BFD_RELOC_X86_64_GOTPLT64: | |
11278 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
11279 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
11280 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
11281 | case BFD_RELOC_RVA: |
11282 | case BFD_RELOC_VTABLE_ENTRY: | |
11283 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
11284 | #ifdef TE_PE |
11285 | case BFD_RELOC_32_SECREL: | |
11286 | #endif | |
252b5132 RH |
11287 | code = fixp->fx_r_type; |
11288 | break; | |
dbbaec26 L |
11289 | case BFD_RELOC_X86_64_32S: |
11290 | if (!fixp->fx_pcrel) | |
11291 | { | |
11292 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
11293 | code = fixp->fx_r_type; | |
11294 | break; | |
11295 | } | |
1a0670f3 | 11296 | /* Fall through. */ |
252b5132 | 11297 | default: |
93382f6d | 11298 | if (fixp->fx_pcrel) |
252b5132 | 11299 | { |
93382f6d AM |
11300 | switch (fixp->fx_size) |
11301 | { | |
11302 | default: | |
b091f402 AM |
11303 | as_bad_where (fixp->fx_file, fixp->fx_line, |
11304 | _("can not do %d byte pc-relative relocation"), | |
11305 | fixp->fx_size); | |
93382f6d AM |
11306 | code = BFD_RELOC_32_PCREL; |
11307 | break; | |
11308 | case 1: code = BFD_RELOC_8_PCREL; break; | |
11309 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 11310 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
11311 | #ifdef BFD64 |
11312 | case 8: code = BFD_RELOC_64_PCREL; break; | |
11313 | #endif | |
93382f6d AM |
11314 | } |
11315 | } | |
11316 | else | |
11317 | { | |
11318 | switch (fixp->fx_size) | |
11319 | { | |
11320 | default: | |
b091f402 AM |
11321 | as_bad_where (fixp->fx_file, fixp->fx_line, |
11322 | _("can not do %d byte relocation"), | |
11323 | fixp->fx_size); | |
93382f6d AM |
11324 | code = BFD_RELOC_32; |
11325 | break; | |
11326 | case 1: code = BFD_RELOC_8; break; | |
11327 | case 2: code = BFD_RELOC_16; break; | |
11328 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 11329 | #ifdef BFD64 |
3e73aa7c | 11330 | case 8: code = BFD_RELOC_64; break; |
937149dd | 11331 | #endif |
93382f6d | 11332 | } |
252b5132 RH |
11333 | } |
11334 | break; | |
11335 | } | |
252b5132 | 11336 | |
d182319b JB |
11337 | if ((code == BFD_RELOC_32 |
11338 | || code == BFD_RELOC_32_PCREL | |
11339 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
11340 | && GOT_symbol |
11341 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 11342 | { |
4fa24527 | 11343 | if (!object_64bit) |
d6ab8113 JB |
11344 | code = BFD_RELOC_386_GOTPC; |
11345 | else | |
11346 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 11347 | } |
7b81dfbb AJ |
11348 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
11349 | && GOT_symbol | |
11350 | && fixp->fx_addsy == GOT_symbol) | |
11351 | { | |
11352 | code = BFD_RELOC_X86_64_GOTPC64; | |
11353 | } | |
252b5132 | 11354 | |
add39d23 TS |
11355 | rel = XNEW (arelent); |
11356 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 11357 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
11358 | |
11359 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 11360 | |
3e73aa7c JH |
11361 | if (!use_rela_relocations) |
11362 | { | |
11363 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
11364 | vtable entry to be used in the relocation's section offset. */ | |
11365 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11366 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
11367 | #if defined (OBJ_COFF) && defined (TE_PE) |
11368 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
11369 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
11370 | else | |
11371 | #endif | |
c6682705 | 11372 | rel->addend = 0; |
3e73aa7c JH |
11373 | } |
11374 | /* Use the rela in 64bit mode. */ | |
252b5132 | 11375 | else |
3e73aa7c | 11376 | { |
862be3fb L |
11377 | if (disallow_64bit_reloc) |
11378 | switch (code) | |
11379 | { | |
862be3fb L |
11380 | case BFD_RELOC_X86_64_DTPOFF64: |
11381 | case BFD_RELOC_X86_64_TPOFF64: | |
11382 | case BFD_RELOC_64_PCREL: | |
11383 | case BFD_RELOC_X86_64_GOTOFF64: | |
11384 | case BFD_RELOC_X86_64_GOT64: | |
11385 | case BFD_RELOC_X86_64_GOTPCREL64: | |
11386 | case BFD_RELOC_X86_64_GOTPC64: | |
11387 | case BFD_RELOC_X86_64_GOTPLT64: | |
11388 | case BFD_RELOC_X86_64_PLTOFF64: | |
11389 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11390 | _("cannot represent relocation type %s in x32 mode"), | |
11391 | bfd_get_reloc_code_name (code)); | |
11392 | break; | |
11393 | default: | |
11394 | break; | |
11395 | } | |
11396 | ||
062cd5e7 AS |
11397 | if (!fixp->fx_pcrel) |
11398 | rel->addend = fixp->fx_offset; | |
11399 | else | |
11400 | switch (code) | |
11401 | { | |
11402 | case BFD_RELOC_X86_64_PLT32: | |
11403 | case BFD_RELOC_X86_64_GOT32: | |
11404 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
11405 | case BFD_RELOC_X86_64_GOTPCRELX: |
11406 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
11407 | case BFD_RELOC_X86_64_TLSGD: |
11408 | case BFD_RELOC_X86_64_TLSLD: | |
11409 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
11410 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
11411 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
11412 | rel->addend = fixp->fx_offset - fixp->fx_size; |
11413 | break; | |
11414 | default: | |
11415 | rel->addend = (section->vma | |
11416 | - fixp->fx_size | |
11417 | + fixp->fx_addnumber | |
11418 | + md_pcrel_from (fixp)); | |
11419 | break; | |
11420 | } | |
3e73aa7c JH |
11421 | } |
11422 | ||
252b5132 RH |
11423 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
11424 | if (rel->howto == NULL) | |
11425 | { | |
11426 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 11427 | _("cannot represent relocation type %s"), |
252b5132 RH |
11428 | bfd_get_reloc_code_name (code)); |
11429 | /* Set howto to a garbage value so that we can keep going. */ | |
11430 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 11431 | gas_assert (rel->howto != NULL); |
252b5132 RH |
11432 | } |
11433 | ||
11434 | return rel; | |
11435 | } | |
11436 | ||
ee86248c | 11437 | #include "tc-i386-intel.c" |
54cfded0 | 11438 | |
a60de03c JB |
11439 | void |
11440 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 11441 | { |
a60de03c JB |
11442 | int saved_naked_reg; |
11443 | char saved_register_dot; | |
54cfded0 | 11444 | |
a60de03c JB |
11445 | saved_naked_reg = allow_naked_reg; |
11446 | allow_naked_reg = 1; | |
11447 | saved_register_dot = register_chars['.']; | |
11448 | register_chars['.'] = '.'; | |
11449 | allow_pseudo_reg = 1; | |
11450 | expression_and_evaluate (exp); | |
11451 | allow_pseudo_reg = 0; | |
11452 | register_chars['.'] = saved_register_dot; | |
11453 | allow_naked_reg = saved_naked_reg; | |
11454 | ||
e96d56a1 | 11455 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 11456 | { |
a60de03c JB |
11457 | if ((addressT) exp->X_add_number < i386_regtab_size) |
11458 | { | |
11459 | exp->X_op = O_constant; | |
11460 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
11461 | .dw2_regnum[flag_code >> 1]; | |
11462 | } | |
11463 | else | |
11464 | exp->X_op = O_illegal; | |
54cfded0 | 11465 | } |
54cfded0 AM |
11466 | } |
11467 | ||
11468 | void | |
11469 | tc_x86_frame_initial_instructions (void) | |
11470 | { | |
a60de03c JB |
11471 | static unsigned int sp_regno[2]; |
11472 | ||
11473 | if (!sp_regno[flag_code >> 1]) | |
11474 | { | |
11475 | char *saved_input = input_line_pointer; | |
11476 | char sp[][4] = {"esp", "rsp"}; | |
11477 | expressionS exp; | |
a4447b93 | 11478 | |
a60de03c JB |
11479 | input_line_pointer = sp[flag_code >> 1]; |
11480 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 11481 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
11482 | sp_regno[flag_code >> 1] = exp.X_add_number; |
11483 | input_line_pointer = saved_input; | |
11484 | } | |
a4447b93 | 11485 | |
61ff971f L |
11486 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
11487 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 11488 | } |
d2b2c203 | 11489 | |
d7921315 L |
11490 | int |
11491 | x86_dwarf2_addr_size (void) | |
11492 | { | |
11493 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
11494 | if (x86_elf_abi == X86_64_X32_ABI) | |
11495 | return 4; | |
11496 | #endif | |
11497 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
11498 | } | |
11499 | ||
d2b2c203 DJ |
11500 | int |
11501 | i386_elf_section_type (const char *str, size_t len) | |
11502 | { | |
11503 | if (flag_code == CODE_64BIT | |
11504 | && len == sizeof ("unwind") - 1 | |
11505 | && strncmp (str, "unwind", 6) == 0) | |
11506 | return SHT_X86_64_UNWIND; | |
11507 | ||
11508 | return -1; | |
11509 | } | |
bb41ade5 | 11510 | |
ad5fec3b EB |
11511 | #ifdef TE_SOLARIS |
11512 | void | |
11513 | i386_solaris_fix_up_eh_frame (segT sec) | |
11514 | { | |
11515 | if (flag_code == CODE_64BIT) | |
11516 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
11517 | } | |
11518 | #endif | |
11519 | ||
bb41ade5 AM |
11520 | #ifdef TE_PE |
11521 | void | |
11522 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
11523 | { | |
91d6fa6a | 11524 | expressionS exp; |
bb41ade5 | 11525 | |
91d6fa6a NC |
11526 | exp.X_op = O_secrel; |
11527 | exp.X_add_symbol = symbol; | |
11528 | exp.X_add_number = 0; | |
11529 | emit_expr (&exp, size); | |
bb41ade5 AM |
11530 | } |
11531 | #endif | |
3b22753a L |
11532 | |
11533 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11534 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
11535 | ||
01e1a5bc | 11536 | bfd_vma |
6d4af3c2 | 11537 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
11538 | { |
11539 | if (flag_code == CODE_64BIT) | |
11540 | { | |
11541 | if (letter == 'l') | |
11542 | return SHF_X86_64_LARGE; | |
11543 | ||
8f3bae45 | 11544 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 11545 | } |
3b22753a | 11546 | else |
8f3bae45 | 11547 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
11548 | return -1; |
11549 | } | |
11550 | ||
01e1a5bc | 11551 | bfd_vma |
3b22753a L |
11552 | x86_64_section_word (char *str, size_t len) |
11553 | { | |
8620418b | 11554 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
11555 | return SHF_X86_64_LARGE; |
11556 | ||
11557 | return -1; | |
11558 | } | |
11559 | ||
11560 | static void | |
11561 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
11562 | { | |
11563 | if (flag_code != CODE_64BIT) | |
11564 | { | |
11565 | s_comm_internal (0, elf_common_parse); | |
11566 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
11567 | } | |
11568 | else | |
11569 | { | |
11570 | static segT lbss_section; | |
11571 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
11572 | asection *saved_bss_section = bss_section; | |
11573 | ||
11574 | if (lbss_section == NULL) | |
11575 | { | |
11576 | flagword applicable; | |
11577 | segT seg = now_seg; | |
11578 | subsegT subseg = now_subseg; | |
11579 | ||
11580 | /* The .lbss section is for local .largecomm symbols. */ | |
11581 | lbss_section = subseg_new (".lbss", 0); | |
11582 | applicable = bfd_applicable_section_flags (stdoutput); | |
11583 | bfd_set_section_flags (stdoutput, lbss_section, | |
11584 | applicable & SEC_ALLOC); | |
11585 | seg_info (lbss_section)->bss = 1; | |
11586 | ||
11587 | subseg_set (seg, subseg); | |
11588 | } | |
11589 | ||
11590 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
11591 | bss_section = lbss_section; | |
11592 | ||
11593 | s_comm_internal (0, elf_common_parse); | |
11594 | ||
11595 | elf_com_section_ptr = saved_com_section_ptr; | |
11596 | bss_section = saved_bss_section; | |
11597 | } | |
11598 | } | |
11599 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |