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2012-01-06 Tristan Gingold <gingold@adacore.com>
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
d382c579
TG		 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
4 2012
47926f60 5 Free Software Foundation, Inc.
252b5132
RH		 6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
ec2655a6 11 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 02110-1301, USA. */
252b5132 23
47926f60
KH		 24/* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 26 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
252b5132 30
252b5132 31#include "as.h"
3882b010 32#include "safe-ctype.h"
252b5132 33#include "subsegs.h"
316e2c05 34#include "dwarf2dbg.h"
54cfded0 35#include "dw2gencfi.h"
d2b2c203 36#include "elf/x86-64.h"
40fb9820 37#include "opcodes/i386-init.h"
252b5132 38
252b5132
RH		 39#ifndef REGISTER_WARNINGS
40#define REGISTER_WARNINGS 1
41#endif
42
c3332e24 43#ifndef INFER_ADDR_PREFIX
eecb386c 44#define INFER_ADDR_PREFIX 1
c3332e24
AM		 45#endif
46
29b0f896
AM		 47#ifndef DEFAULT_ARCH
48#define DEFAULT_ARCH "i386"
246fcdee 49#endif
252b5132 50
edde18a5
AM		 51#ifndef INLINE
52#if __GNUC__ >= 2
53#define INLINE __inline__
54#else
55#define INLINE
56#endif
57#endif
58
6305a203
L		 59/* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 63 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 64#define WAIT_PREFIX 0
65#define SEG_PREFIX 1
66#define ADDR_PREFIX 2
67#define DATA_PREFIX 3
c32fa91d
L		 68#define REP_PREFIX 4
69#define LOCK_PREFIX 5
70#define REX_PREFIX 6 /* must come last. */
71#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 72
73/* we define the syntax here (modulo base,index,scale syntax) */
74#define REGISTER_PREFIX '%'
75#define IMMEDIATE_PREFIX '$'
76#define ABSOLUTE_PREFIX '*'
77
78/* these are the instruction mnemonic suffixes in AT&T syntax or
79 memory operand size in Intel syntax. */
80#define WORD_MNEM_SUFFIX 'w'
81#define BYTE_MNEM_SUFFIX 'b'
82#define SHORT_MNEM_SUFFIX 's'
83#define LONG_MNEM_SUFFIX 'l'
84#define QWORD_MNEM_SUFFIX 'q'
85#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 86#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
22109423 136 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 137}
138arch_entry;
139
78f12dd3 140static void update_code_flag (int, int);
e3bb37b5
L		 141static void set_code_flag (int);
142static void set_16bit_gcc_code_flag (int);
143static void set_intel_syntax (int);
1efbbeb4 144static void set_intel_mnemonic (int);
db51cc60 145static void set_allow_index_reg (int);
cb19c032 146static void set_sse_check (int);
e3bb37b5 147static void set_cpu_arch (int);
6482c264 148#ifdef TE_PE
e3bb37b5 149static void pe_directive_secrel (int);
6482c264 150#endif
e3bb37b5
L		 151static void signed_cons (int);
152static char *output_invalid (int c);
ee86248c
JB		 153static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
154 const char *);
155static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
156 const char *);
a7619375 157static int i386_att_operand (char *);
e3bb37b5 158static int i386_intel_operand (char *, int);
ee86248c
JB		 159static int i386_intel_simplify (expressionS *);
160static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 161static const reg_entry *parse_register (char *, char **);
162static char *parse_insn (char *, char *);
163static char *parse_operands (char *, const char *);
164static void swap_operands (void);
4d456e3d 165static void swap_2_operands (int, int);
e3bb37b5
L		 166static void optimize_imm (void);
167static void optimize_disp (void);
d3ce72d0 168static const insn_template *match_template (void);
e3bb37b5
L		 169static int check_string (void);
170static int process_suffix (void);
171static int check_byte_reg (void);
172static int check_long_reg (void);
173static int check_qword_reg (void);
174static int check_word_reg (void);
175static int finalize_imm (void);
176static int process_operands (void);
177static const seg_entry *build_modrm_byte (void);
178static void output_insn (void);
179static void output_imm (fragS *, offsetT);
180static void output_disp (fragS *, offsetT);
29b0f896 181#ifndef I386COFF
e3bb37b5 182static void s_bss (int);
252b5132 183#endif
17d4e2a2
L		 184#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185static void handle_large_common (int small ATTRIBUTE_UNUSED);
186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
c0f3af97
L		 190/* VEX prefix. */
191typedef struct
192{
193 /* VEX prefix is either 2 byte or 3 byte. */
194 unsigned char bytes[3];
195 unsigned int length;
196 /* Destination or source register specifier. */
197 const reg_entry *register_specifier;
198} vex_prefix;
199
252b5132 200/* 'md_assemble ()' gathers together information and puts it into a
47926f60 201 i386_insn. */
252b5132 202
520dc8e8
AM		 203union i386_op
204 {
205 expressionS *disps;
206 expressionS *imms;
207 const reg_entry *regs;
208 };
209
a65babc9
L		 210enum i386_error
211 {
86e026a4 212 operand_size_mismatch,
a65babc9
L		 213 operand_type_mismatch,
214 register_type_mismatch,
215 number_of_operands_mismatch,
216 invalid_instruction_suffix,
217 bad_imm4,
218 old_gcc_only,
219 unsupported_with_intel_mnemonic,
220 unsupported_syntax,
6c30d220
L		 221 unsupported,
222 invalid_vsib_address,
223 unsupported_vector_index_register
a65babc9
L		 224 };
225
252b5132
RH		 226struct _i386_insn
227 {
47926f60 228 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 229 insn_template tm;
252b5132 230
7d5e4556
L		 231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
252b5132
RH		 233 char suffix;
234
47926f60 235 /* OPERANDS gives the number of given operands. */
252b5132
RH		 236 unsigned int operands;
237
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
47926f60 240 operands. */
252b5132
RH		 241 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
242
243 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 244 use OP[i] for the corresponding operand. */
40fb9820 245 i386_operand_type types[MAX_OPERANDS];
252b5132 246
520dc8e8
AM		 247 /* Displacement expression, immediate expression, or register for each
248 operand. */
249 union i386_op op[MAX_OPERANDS];
252b5132 250
3e73aa7c
JH		 251 /* Flags for operands. */
252 unsigned int flags[MAX_OPERANDS];
253#define Operand_PCrel 1
254
252b5132 255 /* Relocation type for operand */
f86103b7 256 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 257
252b5132
RH		 258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry *base_reg;
261 const reg_entry *index_reg;
262 unsigned int log2_scale_factor;
263
264 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 265 explicit segment overrides are given. */
ce8a8b2f 266 const seg_entry *seg[2];
252b5132
RH		 267
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes;
271 unsigned char prefix[MAX_PREFIXES];
272
273 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 274 addressing modes of this insn are encoded. */
252b5132 275 modrm_byte rm;
3e73aa7c 276 rex_byte rex;
252b5132 277 sib_byte sib;
c0f3af97 278 vex_prefix vex;
b6169b20
L		 279
280 /* Swap operand in encoding. */
4473e004 281 unsigned int swap_operand;
891edac4 282
f8a5c266
L		 283 /* Force 32bit displacement in encoding. */
284 unsigned int disp32_encoding;
285
891edac4 286 /* Error message. */
a65babc9 287 enum i386_error error;
252b5132
RH		 288 };
289
290typedef struct _i386_insn i386_insn;
291
292/* List of chars besides those in app.c:symbol_chars that can start an
293 operand. Used to prevent the scrubber eating vital white-space. */
32137342 294const char extra_symbol_chars[] = "*%-(["
252b5132 295#ifdef LEX_AT
32137342
NC		 296 "@"
297#endif
298#ifdef LEX_QM
299 "?"
252b5132 300#endif
32137342 301 ;
252b5132 302
29b0f896
AM		 303#if (defined (TE_I386AIX) \
304 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 305 && !defined (TE_GNU) \
29b0f896 306 && !defined (TE_LINUX) \
32137342 307 && !defined (TE_NETWARE) \
29b0f896 308 && !defined (TE_FreeBSD) \
5b806d27 309 && !defined (TE_DragonFly) \
29b0f896 310 && !defined (TE_NetBSD)))
252b5132 311/* This array holds the chars that always start a comment. If the
b3b91714
AM		 312 pre-processor is disabled, these aren't very useful. The option
313 --divide will remove '/' from this list. */
314const char *i386_comment_chars = "#/";
315#define SVR4_COMMENT_CHARS 1
252b5132 316#define PREFIX_SEPARATOR '\\'
252b5132 317
b3b91714
AM		 318#else
319const char *i386_comment_chars = "#";
320#define PREFIX_SEPARATOR '/'
321#endif
322
252b5132
RH		 323/* This array holds the chars that only start a comment at the beginning of
324 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 325 .line and .file directives will appear in the pre-processed output.
326 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 327 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 328 #NO_APP at the beginning of its output.
329 Also note that comments started like this one will always work if
252b5132 330 '/' isn't otherwise defined. */
b3b91714 331const char line_comment_chars[] = "#/";
252b5132 332
63a0b638 333const char line_separator_chars[] = ";";
252b5132 334
ce8a8b2f
AM		 335/* Chars that can be used to separate mant from exp in floating point
336 nums. */
252b5132
RH		 337const char EXP_CHARS[] = "eE";
338
ce8a8b2f
AM		 339/* Chars that mean this number is a floating point constant
340 As in 0f12.456
341 or 0d1.2345e12. */
252b5132
RH		 342const char FLT_CHARS[] = "fFdDxX";
343
ce8a8b2f 344/* Tables for lexical analysis. */
252b5132
RH		 345static char mnemonic_chars[256];
346static char register_chars[256];
347static char operand_chars[256];
348static char identifier_chars[256];
349static char digit_chars[256];
350
ce8a8b2f 351/* Lexical macros. */
252b5132
RH		 352#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
353#define is_operand_char(x) (operand_chars[(unsigned char) x])
354#define is_register_char(x) (register_chars[(unsigned char) x])
355#define is_space_char(x) ((x) == ' ')
356#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
357#define is_digit_char(x) (digit_chars[(unsigned char) x])
358
0234cb7c 359/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 360static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
361
362/* md_assemble() always leaves the strings it's passed unaltered. To
363 effect this we maintain a stack of saved characters that we've smashed
364 with '\0's (indicating end of strings for various sub-fields of the
47926f60 365 assembler instruction). */
252b5132 366static char save_stack[32];
ce8a8b2f 367static char *save_stack_p;
252b5132
RH		 368#define END_STRING_AND_SAVE(s) \
369 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
370#define RESTORE_END_STRING(s) \
371 do { *(s) = *--save_stack_p; } while (0)
372
47926f60 373/* The instruction we're assembling. */
252b5132
RH		 374static i386_insn i;
375
376/* Possible templates for current insn. */
377static const templates *current_templates;
378
31b2323c
L		 379/* Per instruction expressionS buffers: max displacements & immediates. */
380static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
381static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 382
47926f60 383/* Current operand we are working on. */
ee86248c 384static int this_operand = -1;
252b5132 385
3e73aa7c
JH		 386/* We support four different modes. FLAG_CODE variable is used to distinguish
387 these. */
388
389enum flag_code {
390 CODE_32BIT,
391 CODE_16BIT,
392 CODE_64BIT };
393
394static enum flag_code flag_code;
4fa24527 395static unsigned int object_64bit;
862be3fb 396static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 397static int use_rela_relocations = 0;
398
7af8ed2d
NC		 399#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
400 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
401 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
402
351f65ca
L		 403/* The ELF ABI to use. */
404enum x86_elf_abi
405{
406 I386_ABI,
7f56bc95
L		 407 X86_64_ABI,
408 X86_64_X32_ABI
351f65ca
L		 409};
410
411static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 412#endif
351f65ca 413
3e73aa7c 414/* The names used to print error messages. */
b77a7acd 415static const char *flag_code_names[] =
3e73aa7c
JH		 416 {
417 "32",
418 "16",
419 "64"
420 };
252b5132 421
47926f60
KH		 422/* 1 for intel syntax,
423 0 if att syntax. */
424static int intel_syntax = 0;
252b5132 425
1efbbeb4
L		 426/* 1 for intel mnemonic,
427 0 if att mnemonic. */
428static int intel_mnemonic = !SYSV386_COMPAT;
429
5209009a 430/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 431static int old_gcc = OLDGCC_COMPAT;
432
a60de03c
JB		 433/* 1 if pseudo registers are permitted. */
434static int allow_pseudo_reg = 0;
435
47926f60
KH		 436/* 1 if register prefix % not required. */
437static int allow_naked_reg = 0;
252b5132 438
ba104c83 439/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 440static int allow_index_reg = 0;
441
daf50ae7
L		 442static enum
443 {
444 sse_check_none = 0,
445 sse_check_warning,
446 sse_check_error
447 }
448sse_check;
449
2ca3ace5
L		 450/* Register prefix used for error message. */
451static const char *register_prefix = "%";
452
47926f60
KH		 453/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
454 leave, push, and pop instructions so that gcc has the same stack
455 frame as in 32 bit mode. */
456static char stackop_size = '\0';
eecb386c 457
12b55ccc
L		 458/* Non-zero to optimize code alignment. */
459int optimize_align_code = 1;
460
47926f60
KH		 461/* Non-zero to quieten some warnings. */
462static int quiet_warnings = 0;
a38cf1db 463
47926f60
KH		 464/* CPU name. */
465static const char *cpu_arch_name = NULL;
6305a203 466static char *cpu_sub_arch_name = NULL;
a38cf1db 467
47926f60 468/* CPU feature flags. */
40fb9820
L		 469static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
470
ccc9c027
L		 471/* If we have selected a cpu we are generating instructions for. */
472static int cpu_arch_tune_set = 0;
473
9103f4f4 474/* Cpu we are generating instructions for. */
fbf3f584 475enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 476
477/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 478static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 479
ccc9c027 480/* CPU instruction set architecture used. */
fbf3f584 481enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 482
9103f4f4 483/* CPU feature flags of instruction set architecture used. */
fbf3f584 484i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 485
fddf5b5b
AM		 486/* If set, conditional jumps are not automatically promoted to handle
487 larger than a byte offset. */
488static unsigned int no_cond_jump_promotion = 0;
489
c0f3af97
L		 490/* Encode SSE instructions with VEX prefix. */
491static unsigned int sse2avx;
492
539f890d
L		 493/* Encode scalar AVX instructions with specific vector length. */
494static enum
495 {
496 vex128 = 0,
497 vex256
498 } avxscalar;
499
29b0f896 500/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 501static symbolS *GOT_symbol;
29b0f896 502
a4447b93
RH		 503/* The dwarf2 return column, adjusted for 32 or 64 bit. */
504unsigned int x86_dwarf2_return_column;
505
506/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
507int x86_cie_data_alignment;
508
252b5132 509/* Interface to relax_segment.
fddf5b5b
AM		 510 There are 3 major relax states for 386 jump insns because the
511 different types of jumps add different sizes to frags when we're
512 figuring out what sort of jump to choose to reach a given label. */
252b5132 513
47926f60 514/* Types. */
93c2a809
AM		 515#define UNCOND_JUMP 0
516#define COND_JUMP 1
517#define COND_JUMP86 2
fddf5b5b 518
47926f60 519/* Sizes. */
252b5132
RH		 520#define CODE16 1
521#define SMALL 0
29b0f896 522#define SMALL16 (SMALL | CODE16)
252b5132 523#define BIG 2
29b0f896 524#define BIG16 (BIG | CODE16)
252b5132
RH		 525
526#ifndef INLINE
527#ifdef __GNUC__
528#define INLINE __inline__
529#else
530#define INLINE
531#endif
532#endif
533
fddf5b5b
AM		 534#define ENCODE_RELAX_STATE(type, size) \
535 ((relax_substateT) (((type) << 2) | (size)))
536#define TYPE_FROM_RELAX_STATE(s) \
537 ((s) >> 2)
538#define DISP_SIZE_FROM_RELAX_STATE(s) \
539 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 540
541/* This table is used by relax_frag to promote short jumps to long
542 ones where necessary. SMALL (short) jumps may be promoted to BIG
543 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
544 don't allow a short jump in a 32 bit code segment to be promoted to
545 a 16 bit offset jump because it's slower (requires data size
546 prefix), and doesn't work, unless the destination is in the bottom
547 64k of the code segment (The top 16 bits of eip are zeroed). */
548
549const relax_typeS md_relax_table[] =
550{
24eab124
AM		 551 /* The fields are:
552 1) most positive reach of this state,
553 2) most negative reach of this state,
93c2a809 554 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 555 4) which index into the table to try if we can't fit into this one. */
252b5132 556
fddf5b5b 557 /* UNCOND_JUMP states. */
93c2a809
AM		 558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
559 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
560 /* dword jmp adds 4 bytes to frag:
561 0 extra opcode bytes, 4 displacement bytes. */
252b5132 562 {0, 0, 4, 0},
93c2a809
AM		 563 /* word jmp adds 2 byte2 to frag:
564 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 565 {0, 0, 2, 0},
566
93c2a809
AM		 567 /* COND_JUMP states. */
568 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
569 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
570 /* dword conditionals adds 5 bytes to frag:
571 1 extra opcode byte, 4 displacement bytes. */
572 {0, 0, 5, 0},
fddf5b5b 573 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 574 1 extra opcode byte, 2 displacement bytes. */
575 {0, 0, 3, 0},
576
577 /* COND_JUMP86 states. */
578 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
579 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
580 /* dword conditionals adds 5 bytes to frag:
581 1 extra opcode byte, 4 displacement bytes. */
582 {0, 0, 5, 0},
583 /* word conditionals add 4 bytes to frag:
584 1 displacement byte and a 3 byte long branch insn. */
585 {0, 0, 4, 0}
252b5132
RH		 586};
587
9103f4f4
L		 588static const arch_entry cpu_arch[] =
589{
89507696
JB		 590 /* Do not replace the first two entries - i386_target_format()
591 relies on them being there in this order. */
8a2c8fef 592 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 593 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 594 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 595 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 596 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 597 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 598 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 599 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 600 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 601 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 602 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 603 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 604 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 605 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 606 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 607 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 608 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 609 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 610 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 611 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 612 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 613 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 614 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 615 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 616 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 617 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 618 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 619 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 620 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 621 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 622 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 623 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 624 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 625 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 626 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 627 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 628 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 629 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 630 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 631 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 632 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 633 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 634 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 635 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 636 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
637 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 638 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 639 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 640 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 641 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 642 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 643 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 644 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 645 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 646 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 647 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 648 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 649 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 650 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 651 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 652 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 653 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 654 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 655 CPU_BDVER2_FLAGS, 0, 0 },
8a2c8fef 656 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 657 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 658 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 659 CPU_287_FLAGS, 0, 0 },
8a2c8fef 660 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 661 CPU_387_FLAGS, 0, 0 },
8a2c8fef 662 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 663 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 664 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 665 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 666 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 667 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 668 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 669 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 670 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 671 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 672 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 673 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 674 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 675 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 676 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 677 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 678 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 679 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 680 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 681 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 682 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 683 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 684 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 685 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 686 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
687 CPU_AVX2_FLAGS, 0, 0 },
8a2c8fef 688 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 689 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 690 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 691 CPU_VMX_FLAGS, 0, 0 },
8a2c8fef 692 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 693 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 694 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 695 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 696 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 697 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 698 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 699 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 700 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 701 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 702 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 703 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 704 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 705 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 706 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 707 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 708 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 709 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 710 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
711 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 712 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 713 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 714 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 715 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 716 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 717 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 718 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 719 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 720 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 721 CPU_MOVBE_FLAGS, 0, 0 },
8a2c8fef 722 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 723 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 724 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
725 CPU_LZCNT_FLAGS, 0, 0 },
726 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
727 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 728 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 729 CPU_CLFLUSH_FLAGS, 0, 0 },
730 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
731 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 732 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 733 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 734 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 735 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 736 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 737 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 738 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 739 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 740 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 741 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 742 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 743 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 744 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 745 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 746 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 747 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 748 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 749 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 750 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
751 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 752 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
753 CPU_TBM_FLAGS, 0, 0 },
e413e4e9
AM		 754};
755
704209c0 756#ifdef I386COFF
a6c24e68
NC		 757/* Like s_lcomm_internal in gas/read.c but the alignment string
758 is allowed to be optional. */
759
760static symbolS *
761pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
762{
763 addressT align = 0;
764
765 SKIP_WHITESPACE ();
766
7ab9ffdd 767 if (needs_align
a6c24e68
NC		 768 && *input_line_pointer == ',')
769 {
770 align = parse_align (needs_align - 1);
7ab9ffdd 771
a6c24e68
NC		 772 if (align == (addressT) -1)
773 return NULL;
774 }
775 else
776 {
777 if (size >= 8)
778 align = 3;
779 else if (size >= 4)
780 align = 2;
781 else if (size >= 2)
782 align = 1;
783 else
784 align = 0;
785 }
786
787 bss_alloc (symbolP, size, align);
788 return symbolP;
789}
790
704209c0 791static void
a6c24e68
NC		 792pe_lcomm (int needs_align)
793{
794 s_comm_internal (needs_align * 2, pe_lcomm_internal);
795}
704209c0 796#endif
a6c24e68 797
29b0f896
AM		 798const pseudo_typeS md_pseudo_table[] =
799{
800#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
801 {"align", s_align_bytes, 0},
802#else
803 {"align", s_align_ptwo, 0},
804#endif
805 {"arch", set_cpu_arch, 0},
806#ifndef I386COFF
807 {"bss", s_bss, 0},
a6c24e68
NC		 808#else
809 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 810#endif
811 {"ffloat", float_cons, 'f'},
812 {"dfloat", float_cons, 'd'},
813 {"tfloat", float_cons, 'x'},
814 {"value", cons, 2},
d182319b 815 {"slong", signed_cons, 4},
29b0f896
AM		 816 {"noopt", s_ignore, 0},
817 {"optim", s_ignore, 0},
818 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
819 {"code16", set_code_flag, CODE_16BIT},
820 {"code32", set_code_flag, CODE_32BIT},
821 {"code64", set_code_flag, CODE_64BIT},
822 {"intel_syntax", set_intel_syntax, 1},
823 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 824 {"intel_mnemonic", set_intel_mnemonic, 1},
825 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 826 {"allow_index_reg", set_allow_index_reg, 1},
827 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 828 {"sse_check", set_sse_check, 0},
3b22753a
L		 829#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
830 {"largecomm", handle_large_common, 0},
07a53e5c 831#else
e3bb37b5 832 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 833 {"loc", dwarf2_directive_loc, 0},
834 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 835#endif
6482c264
NC		 836#ifdef TE_PE
837 {"secrel32", pe_directive_secrel, 0},
838#endif
29b0f896
AM		 839 {0, 0, 0}
840};
841
842/* For interface with expression (). */
843extern char *input_line_pointer;
844
845/* Hash table for instruction mnemonic lookup. */
846static struct hash_control *op_hash;
847
848/* Hash table for register lookup. */
849static struct hash_control *reg_hash;
850\f
252b5132 851void
e3bb37b5 852i386_align_code (fragS *fragP, int count)
252b5132 853{
ce8a8b2f
AM		 854 /* Various efficient no-op patterns for aligning code labels.
855 Note: Don't try to assemble the instructions in the comments.
856 0L and 0w are not legal. */
252b5132
RH		 857 static const char f32_1[] =
858 {0x90}; /* nop */
859 static const char f32_2[] =
ccc9c027 860 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 861 static const char f32_3[] =
862 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
863 static const char f32_4[] =
864 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
865 static const char f32_5[] =
866 {0x90, /* nop */
867 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
868 static const char f32_6[] =
869 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
870 static const char f32_7[] =
871 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
872 static const char f32_8[] =
873 {0x90, /* nop */
874 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
875 static const char f32_9[] =
876 {0x89,0xf6, /* movl %esi,%esi */
877 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
878 static const char f32_10[] =
879 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
880 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
881 static const char f32_11[] =
882 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
883 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
884 static const char f32_12[] =
885 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
886 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
887 static const char f32_13[] =
888 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
889 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
890 static const char f32_14[] =
891 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
892 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 893 static const char f16_3[] =
894 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 895 static const char f16_4[] =
896 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
897 static const char f16_5[] =
898 {0x90, /* nop */
899 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
900 static const char f16_6[] =
901 {0x89,0xf6, /* mov %si,%si */
902 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
903 static const char f16_7[] =
904 {0x8d,0x74,0x00, /* lea 0(%si),%si */
905 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
906 static const char f16_8[] =
907 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
908 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 909 static const char jump_31[] =
910 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
911 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
912 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
913 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 914 static const char *const f32_patt[] = {
915 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 916 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 917 };
918 static const char *const f16_patt[] = {
76bc74dc 919 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 920 };
ccc9c027
L		 921 /* nopl (%[re]ax) */
922 static const char alt_3[] =
923 {0x0f,0x1f,0x00};
924 /* nopl 0(%[re]ax) */
925 static const char alt_4[] =
926 {0x0f,0x1f,0x40,0x00};
927 /* nopl 0(%[re]ax,%[re]ax,1) */
928 static const char alt_5[] =
929 {0x0f,0x1f,0x44,0x00,0x00};
930 /* nopw 0(%[re]ax,%[re]ax,1) */
931 static const char alt_6[] =
932 {0x66,0x0f,0x1f,0x44,0x00,0x00};
933 /* nopl 0L(%[re]ax) */
934 static const char alt_7[] =
935 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
936 /* nopl 0L(%[re]ax,%[re]ax,1) */
937 static const char alt_8[] =
938 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
939 /* nopw 0L(%[re]ax,%[re]ax,1) */
940 static const char alt_9[] =
941 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
942 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
943 static const char alt_10[] =
944 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
945 /* data16
946 nopw %cs:0L(%[re]ax,%[re]ax,1) */
947 static const char alt_long_11[] =
948 {0x66,
949 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
950 /* data16
951 data16
952 nopw %cs:0L(%[re]ax,%[re]ax,1) */
953 static const char alt_long_12[] =
954 {0x66,
955 0x66,
956 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
957 /* data16
958 data16
959 data16
960 nopw %cs:0L(%[re]ax,%[re]ax,1) */
961 static const char alt_long_13[] =
962 {0x66,
963 0x66,
964 0x66,
965 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
966 /* data16
967 data16
968 data16
969 data16
970 nopw %cs:0L(%[re]ax,%[re]ax,1) */
971 static const char alt_long_14[] =
972 {0x66,
973 0x66,
974 0x66,
975 0x66,
976 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
977 /* data16
978 data16
979 data16
980 data16
981 data16
982 nopw %cs:0L(%[re]ax,%[re]ax,1) */
983 static const char alt_long_15[] =
984 {0x66,
985 0x66,
986 0x66,
987 0x66,
988 0x66,
989 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
990 /* nopl 0(%[re]ax,%[re]ax,1)
991 nopw 0(%[re]ax,%[re]ax,1) */
992 static const char alt_short_11[] =
993 {0x0f,0x1f,0x44,0x00,0x00,
994 0x66,0x0f,0x1f,0x44,0x00,0x00};
995 /* nopw 0(%[re]ax,%[re]ax,1)
996 nopw 0(%[re]ax,%[re]ax,1) */
997 static const char alt_short_12[] =
998 {0x66,0x0f,0x1f,0x44,0x00,0x00,
999 0x66,0x0f,0x1f,0x44,0x00,0x00};
1000 /* nopw 0(%[re]ax,%[re]ax,1)
1001 nopl 0L(%[re]ax) */
1002 static const char alt_short_13[] =
1003 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1004 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1005 /* nopl 0L(%[re]ax)
1006 nopl 0L(%[re]ax) */
1007 static const char alt_short_14[] =
1008 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1009 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1010 /* nopl 0L(%[re]ax)
1011 nopl 0L(%[re]ax,%[re]ax,1) */
1012 static const char alt_short_15[] =
1013 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1014 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1015 static const char *const alt_short_patt[] = {
1016 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1017 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1018 alt_short_14, alt_short_15
1019 };
1020 static const char *const alt_long_patt[] = {
1021 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1022 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1023 alt_long_14, alt_long_15
1024 };
252b5132 1025
76bc74dc
L		 1026 /* Only align for at least a positive non-zero boundary. */
1027 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1028 return;
3e73aa7c 1029
ccc9c027
L		 1030 /* We need to decide which NOP sequence to use for 32bit and
1031 64bit. When -mtune= is used:
4eed87de 1032
76bc74dc
L		 1033 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1034 PROCESSOR_GENERIC32, f32_patt will be used.
1035 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1036 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1037 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1038 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
8aedb9fe 1039 PROCESSOR_AMDFAM10, and PROCESSOR_BD, alt_short_patt
69dd9865 1040 will be used.
ccc9c027 1041
76bc74dc 1042 When -mtune= isn't used, alt_long_patt will be used if
22109423 1043 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1044 be used.
ccc9c027
L		 1045
1046 When -march= or .arch is used, we can't use anything beyond
1047 cpu_arch_isa_flags. */
1048
1049 if (flag_code == CODE_16BIT)
1050 {
ccc9c027 1051 if (count > 8)
33fef721 1052 {
76bc74dc
L		 1053 memcpy (fragP->fr_literal + fragP->fr_fix,
1054 jump_31, count);
1055 /* Adjust jump offset. */
1056 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1057 }
76bc74dc
L		 1058 else
1059 memcpy (fragP->fr_literal + fragP->fr_fix,
1060 f16_patt[count - 1], count);
252b5132 1061 }
33fef721 1062 else
ccc9c027
L		 1063 {
1064 const char *const *patt = NULL;
1065
fbf3f584 1066 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1067 {
1068 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1069 switch (cpu_arch_tune)
1070 {
1071 case PROCESSOR_UNKNOWN:
1072 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1073 optimize with nops. */
1074 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1075 patt = alt_long_patt;
ccc9c027
L		 1076 else
1077 patt = f32_patt;
1078 break;
ccc9c027
L		 1079 case PROCESSOR_PENTIUM4:
1080 case PROCESSOR_NOCONA:
ef05d495 1081 case PROCESSOR_CORE:
76bc74dc 1082 case PROCESSOR_CORE2:
bd5295b2 1083 case PROCESSOR_COREI7:
3632d14b 1084 case PROCESSOR_L1OM:
7a9068fe 1085 case PROCESSOR_K1OM:
76bc74dc
L		 1086 case PROCESSOR_GENERIC64:
1087 patt = alt_long_patt;
1088 break;
ccc9c027
L		 1089 case PROCESSOR_K6:
1090 case PROCESSOR_ATHLON:
1091 case PROCESSOR_K8:
4eed87de 1092 case PROCESSOR_AMDFAM10:
8aedb9fe 1093 case PROCESSOR_BD:
ccc9c027
L		 1094 patt = alt_short_patt;
1095 break;
76bc74dc 1096 case PROCESSOR_I386:
ccc9c027
L		 1097 case PROCESSOR_I486:
1098 case PROCESSOR_PENTIUM:
2dde1948 1099 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1100 case PROCESSOR_GENERIC32:
1101 patt = f32_patt;
1102 break;
4eed87de 1103 }
ccc9c027
L		 1104 }
1105 else
1106 {
fbf3f584 1107 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1108 {
1109 case PROCESSOR_UNKNOWN:
e6a14101 1110 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1111 PROCESSOR_UNKNOWN. */
1112 abort ();
1113 break;
1114
76bc74dc 1115 case PROCESSOR_I386:
ccc9c027
L		 1116 case PROCESSOR_I486:
1117 case PROCESSOR_PENTIUM:
ccc9c027
L		 1118 case PROCESSOR_K6:
1119 case PROCESSOR_ATHLON:
1120 case PROCESSOR_K8:
4eed87de 1121 case PROCESSOR_AMDFAM10:
8aedb9fe 1122 case PROCESSOR_BD:
ccc9c027
L		 1123 case PROCESSOR_GENERIC32:
1124 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1125 with nops. */
1126 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1127 patt = alt_short_patt;
1128 else
1129 patt = f32_patt;
1130 break;
76bc74dc
L		 1131 case PROCESSOR_PENTIUMPRO:
1132 case PROCESSOR_PENTIUM4:
1133 case PROCESSOR_NOCONA:
1134 case PROCESSOR_CORE:
ef05d495 1135 case PROCESSOR_CORE2:
bd5295b2 1136 case PROCESSOR_COREI7:
3632d14b 1137 case PROCESSOR_L1OM:
7a9068fe 1138 case PROCESSOR_K1OM:
22109423 1139 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1140 patt = alt_long_patt;
1141 else
1142 patt = f32_patt;
1143 break;
1144 case PROCESSOR_GENERIC64:
76bc74dc 1145 patt = alt_long_patt;
ccc9c027 1146 break;
4eed87de 1147 }
ccc9c027
L		 1148 }
1149
76bc74dc
L		 1150 if (patt == f32_patt)
1151 {
1152 /* If the padding is less than 15 bytes, we use the normal
1153 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1154 its offset. */
1155 int limit;
76ba9986 1156
711eedef
L		 1157 /* For 64bit, the limit is 3 bytes. */
1158 if (flag_code == CODE_64BIT
1159 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1160 limit = 3;
1161 else
1162 limit = 15;
1163 if (count < limit)
76bc74dc
L		 1164 memcpy (fragP->fr_literal + fragP->fr_fix,
1165 patt[count - 1], count);
1166 else
1167 {
1168 memcpy (fragP->fr_literal + fragP->fr_fix,
1169 jump_31, count);
1170 /* Adjust jump offset. */
1171 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1172 }
1173 }
1174 else
1175 {
1176 /* Maximum length of an instruction is 15 byte. If the
1177 padding is greater than 15 bytes and we don't use jump,
1178 we have to break it into smaller pieces. */
1179 int padding = count;
1180 while (padding > 15)
1181 {
1182 padding -= 15;
1183 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1184 patt [14], 15);
1185 }
1186
1187 if (padding)
1188 memcpy (fragP->fr_literal + fragP->fr_fix,
1189 patt [padding - 1], padding);
1190 }
ccc9c027 1191 }
33fef721 1192 fragP->fr_var = count;
252b5132
RH		 1193}
1194
c6fb90c8 1195static INLINE int
0dfbf9d7 1196operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1197{
0dfbf9d7 1198 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1199 {
1200 case 3:
0dfbf9d7 1201 if (x->array[2])
c6fb90c8
L		 1202 return 0;
1203 case 2:
0dfbf9d7 1204 if (x->array[1])
c6fb90c8
L		 1205 return 0;
1206 case 1:
0dfbf9d7 1207 return !x->array[0];
c6fb90c8
L		 1208 default:
1209 abort ();
1210 }
40fb9820
L		 1211}
1212
c6fb90c8 1213static INLINE void
0dfbf9d7 1214operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1215{
0dfbf9d7 1216 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1217 {
1218 case 3:
0dfbf9d7 1219 x->array[2] = v;
c6fb90c8 1220 case 2:
0dfbf9d7 1221 x->array[1] = v;
c6fb90c8 1222 case 1:
0dfbf9d7 1223 x->array[0] = v;
c6fb90c8
L		 1224 break;
1225 default:
1226 abort ();
1227 }
1228}
40fb9820 1229
c6fb90c8 1230static INLINE int
0dfbf9d7
L		 1231operand_type_equal (const union i386_operand_type *x,
1232 const union i386_operand_type *y)
c6fb90c8 1233{
0dfbf9d7 1234 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1235 {
1236 case 3:
0dfbf9d7 1237 if (x->array[2] != y->array[2])
c6fb90c8
L		 1238 return 0;
1239 case 2:
0dfbf9d7 1240 if (x->array[1] != y->array[1])
c6fb90c8
L		 1241 return 0;
1242 case 1:
0dfbf9d7 1243 return x->array[0] == y->array[0];
c6fb90c8
L		 1244 break;
1245 default:
1246 abort ();
1247 }
1248}
40fb9820 1249
0dfbf9d7
L		 1250static INLINE int
1251cpu_flags_all_zero (const union i386_cpu_flags *x)
1252{
1253 switch (ARRAY_SIZE(x->array))
1254 {
1255 case 3:
1256 if (x->array[2])
1257 return 0;
1258 case 2:
1259 if (x->array[1])
1260 return 0;
1261 case 1:
1262 return !x->array[0];
1263 default:
1264 abort ();
1265 }
1266}
1267
1268static INLINE void
1269cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1270{
1271 switch (ARRAY_SIZE(x->array))
1272 {
1273 case 3:
1274 x->array[2] = v;
1275 case 2:
1276 x->array[1] = v;
1277 case 1:
1278 x->array[0] = v;
1279 break;
1280 default:
1281 abort ();
1282 }
1283}
1284
1285static INLINE int
1286cpu_flags_equal (const union i386_cpu_flags *x,
1287 const union i386_cpu_flags *y)
1288{
1289 switch (ARRAY_SIZE(x->array))
1290 {
1291 case 3:
1292 if (x->array[2] != y->array[2])
1293 return 0;
1294 case 2:
1295 if (x->array[1] != y->array[1])
1296 return 0;
1297 case 1:
1298 return x->array[0] == y->array[0];
1299 break;
1300 default:
1301 abort ();
1302 }
1303}
c6fb90c8
L		 1304
1305static INLINE int
1306cpu_flags_check_cpu64 (i386_cpu_flags f)
1307{
1308 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1309 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1310}
1311
c6fb90c8
L		 1312static INLINE i386_cpu_flags
1313cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1314{
c6fb90c8
L		 1315 switch (ARRAY_SIZE (x.array))
1316 {
1317 case 3:
1318 x.array [2] &= y.array [2];
1319 case 2:
1320 x.array [1] &= y.array [1];
1321 case 1:
1322 x.array [0] &= y.array [0];
1323 break;
1324 default:
1325 abort ();
1326 }
1327 return x;
1328}
40fb9820 1329
c6fb90c8
L		 1330static INLINE i386_cpu_flags
1331cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1332{
c6fb90c8 1333 switch (ARRAY_SIZE (x.array))
40fb9820 1334 {
c6fb90c8
L		 1335 case 3:
1336 x.array [2] |= y.array [2];
1337 case 2:
1338 x.array [1] |= y.array [1];
1339 case 1:
1340 x.array [0] |= y.array [0];
40fb9820
L		 1341 break;
1342 default:
1343 abort ();
1344 }
40fb9820
L		 1345 return x;
1346}
1347
309d3373
JB		 1348static INLINE i386_cpu_flags
1349cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1350{
1351 switch (ARRAY_SIZE (x.array))
1352 {
1353 case 3:
1354 x.array [2] &= ~y.array [2];
1355 case 2:
1356 x.array [1] &= ~y.array [1];
1357 case 1:
1358 x.array [0] &= ~y.array [0];
1359 break;
1360 default:
1361 abort ();
1362 }
1363 return x;
1364}
1365
c0f3af97
L		 1366#define CPU_FLAGS_ARCH_MATCH 0x1
1367#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1368#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1369#define CPU_FLAGS_PCLMUL_MATCH 0x8
1370#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1371
a5ff0eb2 1372#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1373 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1374 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1375#define CPU_FLAGS_PERFECT_MATCH \
1376 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1377
1378/* Return CPU flags match bits. */
3629bb00 1379
40fb9820 1380static int
d3ce72d0 1381cpu_flags_match (const insn_template *t)
40fb9820 1382{
c0f3af97
L		 1383 i386_cpu_flags x = t->cpu_flags;
1384 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1385
1386 x.bitfield.cpu64 = 0;
1387 x.bitfield.cpuno64 = 0;
1388
0dfbf9d7 1389 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1390 {
1391 /* This instruction is available on all archs. */
1392 match |= CPU_FLAGS_32BIT_MATCH;
1393 }
3629bb00
L		 1394 else
1395 {
c0f3af97 1396 /* This instruction is available only on some archs. */
3629bb00
L		 1397 i386_cpu_flags cpu = cpu_arch_flags;
1398
1399 cpu.bitfield.cpu64 = 0;
1400 cpu.bitfield.cpuno64 = 0;
1401 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1402 if (!cpu_flags_all_zero (&cpu))
1403 {
a5ff0eb2
L		 1404 if (x.bitfield.cpuavx)
1405 {
ce2f5b3c 1406 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1407 if (cpu.bitfield.cpuavx)
1408 {
1409 /* Check SSE2AVX. */
1410 if (!t->opcode_modifier.sse2avx|| sse2avx)
1411 {
1412 match |= (CPU_FLAGS_ARCH_MATCH
1413 | CPU_FLAGS_AVX_MATCH);
1414 /* Check AES. */
1415 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1416 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1417 /* Check PCLMUL. */
1418 if (!x.bitfield.cpupclmul
1419 || cpu.bitfield.cpupclmul)
1420 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1421 }
1422 }
1423 else
1424 match |= CPU_FLAGS_ARCH_MATCH;
1425 }
1426 else
c0f3af97
L		 1427 match |= CPU_FLAGS_32BIT_MATCH;
1428 }
3629bb00 1429 }
c0f3af97 1430 return match;
40fb9820
L		 1431}
1432
c6fb90c8
L		 1433static INLINE i386_operand_type
1434operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1435{
c6fb90c8
L		 1436 switch (ARRAY_SIZE (x.array))
1437 {
1438 case 3:
1439 x.array [2] &= y.array [2];
1440 case 2:
1441 x.array [1] &= y.array [1];
1442 case 1:
1443 x.array [0] &= y.array [0];
1444 break;
1445 default:
1446 abort ();
1447 }
1448 return x;
40fb9820
L		 1449}
1450
c6fb90c8
L		 1451static INLINE i386_operand_type
1452operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1453{
c6fb90c8 1454 switch (ARRAY_SIZE (x.array))
40fb9820 1455 {
c6fb90c8
L		 1456 case 3:
1457 x.array [2] |= y.array [2];
1458 case 2:
1459 x.array [1] |= y.array [1];
1460 case 1:
1461 x.array [0] |= y.array [0];
40fb9820
L		 1462 break;
1463 default:
1464 abort ();
1465 }
c6fb90c8
L		 1466 return x;
1467}
40fb9820 1468
c6fb90c8
L		 1469static INLINE i386_operand_type
1470operand_type_xor (i386_operand_type x, i386_operand_type y)
1471{
1472 switch (ARRAY_SIZE (x.array))
1473 {
1474 case 3:
1475 x.array [2] ^= y.array [2];
1476 case 2:
1477 x.array [1] ^= y.array [1];
1478 case 1:
1479 x.array [0] ^= y.array [0];
1480 break;
1481 default:
1482 abort ();
1483 }
40fb9820
L		 1484 return x;
1485}
1486
1487static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1488static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1489static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1490static const i386_operand_type inoutportreg
1491 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1492static const i386_operand_type reg16_inoutportreg
1493 = OPERAND_TYPE_REG16_INOUTPORTREG;
1494static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1495static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1496static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1497static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1498static const i386_operand_type anydisp
1499 = OPERAND_TYPE_ANYDISP;
40fb9820 1500static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1501static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1502static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1503static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1504static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1505static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1506static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1507static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1508static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1509static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1510static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1511static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1512
1513enum operand_type
1514{
1515 reg,
40fb9820
L		 1516 imm,
1517 disp,
1518 anymem
1519};
1520
c6fb90c8 1521static INLINE int
40fb9820
L		 1522operand_type_check (i386_operand_type t, enum operand_type c)
1523{
1524 switch (c)
1525 {
1526 case reg:
1527 return (t.bitfield.reg8
1528 || t.bitfield.reg16
1529 || t.bitfield.reg32
1530 || t.bitfield.reg64);
1531
40fb9820
L		 1532 case imm:
1533 return (t.bitfield.imm8
1534 || t.bitfield.imm8s
1535 || t.bitfield.imm16
1536 || t.bitfield.imm32
1537 || t.bitfield.imm32s
1538 || t.bitfield.imm64);
1539
1540 case disp:
1541 return (t.bitfield.disp8
1542 || t.bitfield.disp16
1543 || t.bitfield.disp32
1544 || t.bitfield.disp32s
1545 || t.bitfield.disp64);
1546
1547 case anymem:
1548 return (t.bitfield.disp8
1549 || t.bitfield.disp16
1550 || t.bitfield.disp32
1551 || t.bitfield.disp32s
1552 || t.bitfield.disp64
1553 || t.bitfield.baseindex);
1554
1555 default:
1556 abort ();
1557 }
2cfe26b6
AM		 1558
1559 return 0;
40fb9820
L		 1560}
1561
5c07affc
L		 1562/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1563 operand J for instruction template T. */
1564
1565static INLINE int
d3ce72d0 1566match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1567{
1568 return !((i.types[j].bitfield.byte
1569 && !t->operand_types[j].bitfield.byte)
1570 || (i.types[j].bitfield.word
1571 && !t->operand_types[j].bitfield.word)
1572 || (i.types[j].bitfield.dword
1573 && !t->operand_types[j].bitfield.dword)
1574 || (i.types[j].bitfield.qword
1575 && !t->operand_types[j].bitfield.qword));
1576}
1577
1578/* Return 1 if there is no conflict in any size on operand J for
1579 instruction template T. */
1580
1581static INLINE int
d3ce72d0 1582match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1583{
1584 return (match_reg_size (t, j)
1585 && !((i.types[j].bitfield.unspecified
1586 && !t->operand_types[j].bitfield.unspecified)
1587 || (i.types[j].bitfield.fword
1588 && !t->operand_types[j].bitfield.fword)
1589 || (i.types[j].bitfield.tbyte
1590 && !t->operand_types[j].bitfield.tbyte)
1591 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1592 && !t->operand_types[j].bitfield.xmmword)
1593 || (i.types[j].bitfield.ymmword
1594 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1595}
1596
1597/* Return 1 if there is no size conflict on any operands for
1598 instruction template T. */
1599
1600static INLINE int
d3ce72d0 1601operand_size_match (const insn_template *t)
5c07affc
L		 1602{
1603 unsigned int j;
1604 int match = 1;
1605
1606 /* Don't check jump instructions. */
1607 if (t->opcode_modifier.jump
1608 || t->opcode_modifier.jumpbyte
1609 || t->opcode_modifier.jumpdword
1610 || t->opcode_modifier.jumpintersegment)
1611 return match;
1612
1613 /* Check memory and accumulator operand size. */
1614 for (j = 0; j < i.operands; j++)
1615 {
1616 if (t->operand_types[j].bitfield.anysize)
1617 continue;
1618
1619 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1620 {
1621 match = 0;
1622 break;
1623 }
1624
1625 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1626 {
1627 match = 0;
1628 break;
1629 }
1630 }
1631
891edac4 1632 if (match)
5c07affc 1633 return match;
891edac4
L		 1634 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1635 {
1636mismatch:
86e026a4 1637 i.error = operand_size_mismatch;
891edac4
L		 1638 return 0;
1639 }
5c07affc
L		 1640
1641 /* Check reverse. */
9c2799c2 1642 gas_assert (i.operands == 2);
5c07affc
L		 1643
1644 match = 1;
1645 for (j = 0; j < 2; j++)
1646 {
1647 if (t->operand_types[j].bitfield.acc
1648 && !match_reg_size (t, j ? 0 : 1))
891edac4 1649 goto mismatch;
5c07affc
L		 1650
1651 if (i.types[j].bitfield.mem
1652 && !match_mem_size (t, j ? 0 : 1))
891edac4 1653 goto mismatch;
5c07affc
L		 1654 }
1655
1656 return match;
1657}
1658
c6fb90c8 1659static INLINE int
40fb9820
L		 1660operand_type_match (i386_operand_type overlap,
1661 i386_operand_type given)
1662{
1663 i386_operand_type temp = overlap;
1664
1665 temp.bitfield.jumpabsolute = 0;
7d5e4556 1666 temp.bitfield.unspecified = 0;
5c07affc
L		 1667 temp.bitfield.byte = 0;
1668 temp.bitfield.word = 0;
1669 temp.bitfield.dword = 0;
1670 temp.bitfield.fword = 0;
1671 temp.bitfield.qword = 0;
1672 temp.bitfield.tbyte = 0;
1673 temp.bitfield.xmmword = 0;
c0f3af97 1674 temp.bitfield.ymmword = 0;
0dfbf9d7 1675 if (operand_type_all_zero (&temp))
891edac4 1676 goto mismatch;
40fb9820 1677
891edac4
L		 1678 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1679 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1680 return 1;
1681
1682mismatch:
a65babc9 1683 i.error = operand_type_mismatch;
891edac4 1684 return 0;
40fb9820
L		 1685}
1686
7d5e4556 1687/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1688 unless the expected operand type register overlap is null.
1689 Note that Acc in a template matches every size of reg. */
1690
c6fb90c8 1691static INLINE int
40fb9820
L		 1692operand_type_register_match (i386_operand_type m0,
1693 i386_operand_type g0,
1694 i386_operand_type t0,
1695 i386_operand_type m1,
1696 i386_operand_type g1,
1697 i386_operand_type t1)
1698{
1699 if (!operand_type_check (g0, reg))
1700 return 1;
1701
1702 if (!operand_type_check (g1, reg))
1703 return 1;
1704
1705 if (g0.bitfield.reg8 == g1.bitfield.reg8
1706 && g0.bitfield.reg16 == g1.bitfield.reg16
1707 && g0.bitfield.reg32 == g1.bitfield.reg32
1708 && g0.bitfield.reg64 == g1.bitfield.reg64)
1709 return 1;
1710
1711 if (m0.bitfield.acc)
1712 {
1713 t0.bitfield.reg8 = 1;
1714 t0.bitfield.reg16 = 1;
1715 t0.bitfield.reg32 = 1;
1716 t0.bitfield.reg64 = 1;
1717 }
1718
1719 if (m1.bitfield.acc)
1720 {
1721 t1.bitfield.reg8 = 1;
1722 t1.bitfield.reg16 = 1;
1723 t1.bitfield.reg32 = 1;
1724 t1.bitfield.reg64 = 1;
1725 }
1726
891edac4
L		 1727 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1728 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1729 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1730 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1731 return 1;
1732
a65babc9 1733 i.error = register_type_mismatch;
891edac4
L		 1734
1735 return 0;
40fb9820
L		 1736}
1737
252b5132 1738static INLINE unsigned int
40fb9820 1739mode_from_disp_size (i386_operand_type t)
252b5132 1740{
40fb9820
L		 1741 if (t.bitfield.disp8)
1742 return 1;
1743 else if (t.bitfield.disp16
1744 || t.bitfield.disp32
1745 || t.bitfield.disp32s)
1746 return 2;
1747 else
1748 return 0;
252b5132
RH		 1749}
1750
1751static INLINE int
e3bb37b5 1752fits_in_signed_byte (offsetT num)
252b5132
RH		 1753{
1754 return (num >= -128) && (num <= 127);
47926f60 1755}
252b5132
RH		 1756
1757static INLINE int
e3bb37b5 1758fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1759{
1760 return (num & 0xff) == num;
47926f60 1761}
252b5132
RH		 1762
1763static INLINE int
e3bb37b5 1764fits_in_unsigned_word (offsetT num)
252b5132
RH		 1765{
1766 return (num & 0xffff) == num;
47926f60 1767}
252b5132
RH		 1768
1769static INLINE int
e3bb37b5 1770fits_in_signed_word (offsetT num)
252b5132
RH		 1771{
1772 return (-32768 <= num) && (num <= 32767);
47926f60 1773}
2a962e6d 1774
3e73aa7c 1775static INLINE int
e3bb37b5 1776fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1777{
1778#ifndef BFD64
1779 return 1;
1780#else
1781 return (!(((offsetT) -1 << 31) & num)
1782 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1783#endif
1784} /* fits_in_signed_long() */
2a962e6d 1785
3e73aa7c 1786static INLINE int
e3bb37b5 1787fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1788{
1789#ifndef BFD64
1790 return 1;
1791#else
1792 return (num & (((offsetT) 2 << 31) - 1)) == num;
1793#endif
1794} /* fits_in_unsigned_long() */
252b5132 1795
a683cc34
SP		 1796static INLINE int
1797fits_in_imm4 (offsetT num)
1798{
1799 return (num & 0xf) == num;
1800}
1801
40fb9820 1802static i386_operand_type
e3bb37b5 1803smallest_imm_type (offsetT num)
252b5132 1804{
40fb9820 1805 i386_operand_type t;
7ab9ffdd 1806
0dfbf9d7 1807 operand_type_set (&t, 0);
40fb9820
L		 1808 t.bitfield.imm64 = 1;
1809
1810 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1811 {
1812 /* This code is disabled on the 486 because all the Imm1 forms
1813 in the opcode table are slower on the i486. They're the
1814 versions with the implicitly specified single-position
1815 displacement, which has another syntax if you really want to
1816 use that form. */
40fb9820
L		 1817 t.bitfield.imm1 = 1;
1818 t.bitfield.imm8 = 1;
1819 t.bitfield.imm8s = 1;
1820 t.bitfield.imm16 = 1;
1821 t.bitfield.imm32 = 1;
1822 t.bitfield.imm32s = 1;
1823 }
1824 else if (fits_in_signed_byte (num))
1825 {
1826 t.bitfield.imm8 = 1;
1827 t.bitfield.imm8s = 1;
1828 t.bitfield.imm16 = 1;
1829 t.bitfield.imm32 = 1;
1830 t.bitfield.imm32s = 1;
1831 }
1832 else if (fits_in_unsigned_byte (num))
1833 {
1834 t.bitfield.imm8 = 1;
1835 t.bitfield.imm16 = 1;
1836 t.bitfield.imm32 = 1;
1837 t.bitfield.imm32s = 1;
1838 }
1839 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1840 {
1841 t.bitfield.imm16 = 1;
1842 t.bitfield.imm32 = 1;
1843 t.bitfield.imm32s = 1;
1844 }
1845 else if (fits_in_signed_long (num))
1846 {
1847 t.bitfield.imm32 = 1;
1848 t.bitfield.imm32s = 1;
1849 }
1850 else if (fits_in_unsigned_long (num))
1851 t.bitfield.imm32 = 1;
1852
1853 return t;
47926f60 1854}
252b5132 1855
847f7ad4 1856static offsetT
e3bb37b5 1857offset_in_range (offsetT val, int size)
847f7ad4 1858{
508866be 1859 addressT mask;
ba2adb93 1860
847f7ad4
AM		 1861 switch (size)
1862 {
508866be
L		 1863 case 1: mask = ((addressT) 1 << 8) - 1; break;
1864 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1865 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1866#ifdef BFD64
1867 case 8: mask = ((addressT) 2 << 63) - 1; break;
1868#endif
47926f60 1869 default: abort ();
847f7ad4
AM		 1870 }
1871
9de868bf
L		 1872#ifdef BFD64
1873 /* If BFD64, sign extend val for 32bit address mode. */
1874 if (flag_code != CODE_64BIT
1875 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1876 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1877 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1878#endif
ba2adb93 1879
47926f60 1880 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1881 {
1882 char buf1[40], buf2[40];
1883
1884 sprint_value (buf1, val);
1885 sprint_value (buf2, val & mask);
1886 as_warn (_("%s shortened to %s"), buf1, buf2);
1887 }
1888 return val & mask;
1889}
1890
c32fa91d
L		 1891enum PREFIX_GROUP
1892{
1893 PREFIX_EXIST = 0,
1894 PREFIX_LOCK,
1895 PREFIX_REP,
1896 PREFIX_OTHER
1897};
1898
1899/* Returns
1900 a. PREFIX_EXIST if attempting to add a prefix where one from the
1901 same class already exists.
1902 b. PREFIX_LOCK if lock prefix is added.
1903 c. PREFIX_REP if rep/repne prefix is added.
1904 d. PREFIX_OTHER if other prefix is added.
1905 */
1906
1907static enum PREFIX_GROUP
e3bb37b5 1908add_prefix (unsigned int prefix)
252b5132 1909{
c32fa91d 1910 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1911 unsigned int q;
252b5132 1912
29b0f896
AM		 1913 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1914 && flag_code == CODE_64BIT)
b1905489 1915 {
161a04f6
L		 1916 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1917 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1918 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1919 ret = PREFIX_EXIST;
b1905489
JB		 1920 q = REX_PREFIX;
1921 }
3e73aa7c 1922 else
b1905489
JB		 1923 {
1924 switch (prefix)
1925 {
1926 default:
1927 abort ();
1928
1929 case CS_PREFIX_OPCODE:
1930 case DS_PREFIX_OPCODE:
1931 case ES_PREFIX_OPCODE:
1932 case FS_PREFIX_OPCODE:
1933 case GS_PREFIX_OPCODE:
1934 case SS_PREFIX_OPCODE:
1935 q = SEG_PREFIX;
1936 break;
1937
1938 case REPNE_PREFIX_OPCODE:
1939 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1940 q = REP_PREFIX;
1941 ret = PREFIX_REP;
1942 break;
1943
b1905489 1944 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1945 q = LOCK_PREFIX;
1946 ret = PREFIX_LOCK;
b1905489
JB		 1947 break;
1948
1949 case FWAIT_OPCODE:
1950 q = WAIT_PREFIX;
1951 break;
1952
1953 case ADDR_PREFIX_OPCODE:
1954 q = ADDR_PREFIX;
1955 break;
1956
1957 case DATA_PREFIX_OPCODE:
1958 q = DATA_PREFIX;
1959 break;
1960 }
1961 if (i.prefix[q] != 0)
c32fa91d 1962 ret = PREFIX_EXIST;
b1905489 1963 }
252b5132 1964
b1905489 1965 if (ret)
252b5132 1966 {
b1905489
JB		 1967 if (!i.prefix[q])
1968 ++i.prefixes;
1969 i.prefix[q] |= prefix;
252b5132 1970 }
b1905489
JB		 1971 else
1972 as_bad (_("same type of prefix used twice"));
252b5132 1973
252b5132
RH		 1974 return ret;
1975}
1976
1977static void
78f12dd3 1978update_code_flag (int value, int check)
eecb386c 1979{
78f12dd3
L		 1980 PRINTF_LIKE ((*as_error));
1981
1e9cc1c2 1982 flag_code = (enum flag_code) value;
40fb9820
L		 1983 if (flag_code == CODE_64BIT)
1984 {
1985 cpu_arch_flags.bitfield.cpu64 = 1;
1986 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1987 }
1988 else
1989 {
1990 cpu_arch_flags.bitfield.cpu64 = 0;
1991 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1992 }
1993 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 1994 {
78f12dd3
L		 1995 if (check)
1996 as_error = as_fatal;
1997 else
1998 as_error = as_bad;
1999 (*as_error) (_("64bit mode not supported on `%s'."),
2000 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2001 }
40fb9820 2002 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2003 {
78f12dd3
L		 2004 if (check)
2005 as_error = as_fatal;
2006 else
2007 as_error = as_bad;
2008 (*as_error) (_("32bit mode not supported on `%s'."),
2009 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2010 }
eecb386c
AM		 2011 stackop_size = '\0';
2012}
2013
78f12dd3
L		 2014static void
2015set_code_flag (int value)
2016{
2017 update_code_flag (value, 0);
2018}
2019
eecb386c 2020static void
e3bb37b5 2021set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2022{
1e9cc1c2 2023 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2024 if (flag_code != CODE_16BIT)
2025 abort ();
2026 cpu_arch_flags.bitfield.cpu64 = 0;
2027 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2028 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2029}
2030
2031static void
e3bb37b5 2032set_intel_syntax (int syntax_flag)
252b5132
RH		 2033{
2034 /* Find out if register prefixing is specified. */
2035 int ask_naked_reg = 0;
2036
2037 SKIP_WHITESPACE ();
29b0f896 2038 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2039 {
2040 char *string = input_line_pointer;
2041 int e = get_symbol_end ();
2042
47926f60 2043 if (strcmp (string, "prefix") == 0)
252b5132 2044 ask_naked_reg = 1;
47926f60 2045 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2046 ask_naked_reg = -1;
2047 else
d0b47220 2048 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2049 *input_line_pointer = e;
2050 }
2051 demand_empty_rest_of_line ();
c3332e24 2052
252b5132
RH		 2053 intel_syntax = syntax_flag;
2054
2055 if (ask_naked_reg == 0)
f86103b7
AM		 2056 allow_naked_reg = (intel_syntax
2057 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2058 else
2059 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2060
ee86248c 2061 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2062
e4a3b5a4 2063 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2064 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2065 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2066}
2067
1efbbeb4
L		 2068static void
2069set_intel_mnemonic (int mnemonic_flag)
2070{
e1d4d893 2071 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2072}
2073
db51cc60
L		 2074static void
2075set_allow_index_reg (int flag)
2076{
2077 allow_index_reg = flag;
2078}
2079
cb19c032
L		 2080static void
2081set_sse_check (int dummy ATTRIBUTE_UNUSED)
2082{
2083 SKIP_WHITESPACE ();
2084
2085 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2086 {
2087 char *string = input_line_pointer;
2088 int e = get_symbol_end ();
2089
2090 if (strcmp (string, "none") == 0)
2091 sse_check = sse_check_none;
2092 else if (strcmp (string, "warning") == 0)
2093 sse_check = sse_check_warning;
2094 else if (strcmp (string, "error") == 0)
2095 sse_check = sse_check_error;
2096 else
2097 as_bad (_("bad argument to sse_check directive."));
2098 *input_line_pointer = e;
2099 }
2100 else
2101 as_bad (_("missing argument for sse_check directive"));
2102
2103 demand_empty_rest_of_line ();
2104}
2105
8a9036a4
L		 2106static void
2107check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2108 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2109{
2110#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2111 static const char *arch;
2112
2113 /* Intel LIOM is only supported on ELF. */
2114 if (!IS_ELF)
2115 return;
2116
2117 if (!arch)
2118 {
2119 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2120 use default_arch. */
2121 arch = cpu_arch_name;
2122 if (!arch)
2123 arch = default_arch;
2124 }
2125
3632d14b 2126 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2127 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2128 || new_flag.bitfield.cpul1om)
8a9036a4 2129 return;
76ba9986 2130
7a9068fe
L		 2131 /* If we are targeting Intel K1OM, we must enable it. */
2132 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2133 || new_flag.bitfield.cpuk1om)
2134 return;
2135
8a9036a4
L		 2136 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2137#endif
2138}
2139
e413e4e9 2140static void
e3bb37b5 2141set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2142{
47926f60 2143 SKIP_WHITESPACE ();
e413e4e9 2144
29b0f896 2145 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2146 {
2147 char *string = input_line_pointer;
2148 int e = get_symbol_end ();
91d6fa6a 2149 unsigned int j;
40fb9820 2150 i386_cpu_flags flags;
e413e4e9 2151
91d6fa6a 2152 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2153 {
91d6fa6a 2154 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2155 {
91d6fa6a 2156 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2157
5c6af06e
JB		 2158 if (*string != '.')
2159 {
91d6fa6a 2160 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2161 cpu_sub_arch_name = NULL;
91d6fa6a 2162 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2163 if (flag_code == CODE_64BIT)
2164 {
2165 cpu_arch_flags.bitfield.cpu64 = 1;
2166 cpu_arch_flags.bitfield.cpuno64 = 0;
2167 }
2168 else
2169 {
2170 cpu_arch_flags.bitfield.cpu64 = 0;
2171 cpu_arch_flags.bitfield.cpuno64 = 1;
2172 }
91d6fa6a
NC		 2173 cpu_arch_isa = cpu_arch[j].type;
2174 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2175 if (!cpu_arch_tune_set)
2176 {
2177 cpu_arch_tune = cpu_arch_isa;
2178 cpu_arch_tune_flags = cpu_arch_isa_flags;
2179 }
5c6af06e
JB		 2180 break;
2181 }
40fb9820 2182
22109423 2183 if (!cpu_arch[j].negated)
309d3373 2184 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2185 cpu_arch[j].flags);
309d3373
JB		 2186 else
2187 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2188 cpu_arch[j].flags);
0dfbf9d7 2189 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2190 {
6305a203
L		 2191 if (cpu_sub_arch_name)
2192 {
2193 char *name = cpu_sub_arch_name;
2194 cpu_sub_arch_name = concat (name,
91d6fa6a 2195 cpu_arch[j].name,
1bf57e9f 2196 (const char *) NULL);
6305a203
L		 2197 free (name);
2198 }
2199 else
91d6fa6a 2200 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2201 cpu_arch_flags = flags;
a586129e 2202 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2203 }
2204 *input_line_pointer = e;
2205 demand_empty_rest_of_line ();
2206 return;
e413e4e9
AM		 2207 }
2208 }
91d6fa6a 2209 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2210 as_bad (_("no such architecture: `%s'"), string);
2211
2212 *input_line_pointer = e;
2213 }
2214 else
2215 as_bad (_("missing cpu architecture"));
2216
fddf5b5b
AM		 2217 no_cond_jump_promotion = 0;
2218 if (*input_line_pointer == ','
29b0f896 2219 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2220 {
2221 char *string = ++input_line_pointer;
2222 int e = get_symbol_end ();
2223
2224 if (strcmp (string, "nojumps") == 0)
2225 no_cond_jump_promotion = 1;
2226 else if (strcmp (string, "jumps") == 0)
2227 ;
2228 else
2229 as_bad (_("no such architecture modifier: `%s'"), string);
2230
2231 *input_line_pointer = e;
2232 }
2233
e413e4e9
AM		 2234 demand_empty_rest_of_line ();
2235}
2236
8a9036a4
L		 2237enum bfd_architecture
2238i386_arch (void)
2239{
3632d14b 2240 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2241 {
2242 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2243 || flag_code != CODE_64BIT)
2244 as_fatal (_("Intel L1OM is 64bit ELF only"));
2245 return bfd_arch_l1om;
2246 }
7a9068fe
L		 2247 else if (cpu_arch_isa == PROCESSOR_K1OM)
2248 {
2249 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2250 || flag_code != CODE_64BIT)
2251 as_fatal (_("Intel K1OM is 64bit ELF only"));
2252 return bfd_arch_k1om;
2253 }
8a9036a4
L		 2254 else
2255 return bfd_arch_i386;
2256}
2257
b9d79e03 2258unsigned long
7016a5d5 2259i386_mach (void)
b9d79e03 2260{
351f65ca 2261 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2262 {
3632d14b 2263 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2264 {
351f65ca
L		 2265 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2266 || default_arch[6] != '\0')
8a9036a4
L		 2267 as_fatal (_("Intel L1OM is 64bit ELF only"));
2268 return bfd_mach_l1om;
2269 }
7a9068fe
L		 2270 else if (cpu_arch_isa == PROCESSOR_K1OM)
2271 {
2272 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2273 || default_arch[6] != '\0')
2274 as_fatal (_("Intel K1OM is 64bit ELF only"));
2275 return bfd_mach_k1om;
2276 }
351f65ca 2277 else if (default_arch[6] == '\0')
8a9036a4 2278 return bfd_mach_x86_64;
351f65ca
L		 2279 else
2280 return bfd_mach_x64_32;
8a9036a4 2281 }
b9d79e03
JH		 2282 else if (!strcmp (default_arch, "i386"))
2283 return bfd_mach_i386_i386;
2284 else
2b5d6a91 2285 as_fatal (_("unknown architecture"));
b9d79e03 2286}
b9d79e03 2287\f
252b5132 2288void
7016a5d5 2289md_begin (void)
252b5132
RH		 2290{
2291 const char *hash_err;
2292
47926f60 2293 /* Initialize op_hash hash table. */
252b5132
RH		 2294 op_hash = hash_new ();
2295
2296 {
d3ce72d0 2297 const insn_template *optab;
29b0f896 2298 templates *core_optab;
252b5132 2299
47926f60
KH		 2300 /* Setup for loop. */
2301 optab = i386_optab;
252b5132
RH		 2302 core_optab = (templates *) xmalloc (sizeof (templates));
2303 core_optab->start = optab;
2304
2305 while (1)
2306 {
2307 ++optab;
2308 if (optab->name == NULL
2309 || strcmp (optab->name, (optab - 1)->name) != 0)
2310 {
2311 /* different name --> ship out current template list;
47926f60 2312 add to hash table; & begin anew. */
252b5132
RH		 2313 core_optab->end = optab;
2314 hash_err = hash_insert (op_hash,
2315 (optab - 1)->name,
5a49b8ac 2316 (void *) core_optab);
252b5132
RH		 2317 if (hash_err)
2318 {
2b5d6a91 2319 as_fatal (_("internal Error: Can't hash %s: %s"),
252b5132
RH		 2320 (optab - 1)->name,
2321 hash_err);
2322 }
2323 if (optab->name == NULL)
2324 break;
2325 core_optab = (templates *) xmalloc (sizeof (templates));
2326 core_optab->start = optab;
2327 }
2328 }
2329 }
2330
47926f60 2331 /* Initialize reg_hash hash table. */
252b5132
RH		 2332 reg_hash = hash_new ();
2333 {
29b0f896 2334 const reg_entry *regtab;
c3fe08fa 2335 unsigned int regtab_size = i386_regtab_size;
252b5132 2336
c3fe08fa 2337 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2338 {
5a49b8ac 2339 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2340 if (hash_err)
2b5d6a91 2341 as_fatal (_("internal Error: Can't hash %s: %s"),
3e73aa7c
JH		 2342 regtab->reg_name,
2343 hash_err);
252b5132
RH		 2344 }
2345 }
2346
47926f60 2347 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2348 {
29b0f896
AM		 2349 int c;
2350 char *p;
252b5132
RH		 2351
2352 for (c = 0; c < 256; c++)
2353 {
3882b010 2354 if (ISDIGIT (c))
252b5132
RH		 2355 {
2356 digit_chars[c] = c;
2357 mnemonic_chars[c] = c;
2358 register_chars[c] = c;
2359 operand_chars[c] = c;
2360 }
3882b010 2361 else if (ISLOWER (c))
252b5132
RH		 2362 {
2363 mnemonic_chars[c] = c;
2364 register_chars[c] = c;
2365 operand_chars[c] = c;
2366 }
3882b010 2367 else if (ISUPPER (c))
252b5132 2368 {
3882b010 2369 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2370 register_chars[c] = mnemonic_chars[c];
2371 operand_chars[c] = c;
2372 }
2373
3882b010 2374 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2375 identifier_chars[c] = c;
2376 else if (c >= 128)
2377 {
2378 identifier_chars[c] = c;
2379 operand_chars[c] = c;
2380 }
2381 }
2382
2383#ifdef LEX_AT
2384 identifier_chars['@'] = '@';
32137342
NC		 2385#endif
2386#ifdef LEX_QM
2387 identifier_chars['?'] = '?';
2388 operand_chars['?'] = '?';
252b5132 2389#endif
252b5132 2390 digit_chars['-'] = '-';
c0f3af97 2391 mnemonic_chars['_'] = '_';
791fe849 2392 mnemonic_chars['-'] = '-';
0003779b 2393 mnemonic_chars['.'] = '.';
252b5132
RH		 2394 identifier_chars['_'] = '_';
2395 identifier_chars['.'] = '.';
2396
2397 for (p = operand_special_chars; *p != '\0'; p++)
2398 operand_chars[(unsigned char) *p] = *p;
2399 }
2400
2401#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2402 if (IS_ELF)
252b5132
RH		 2403 {
2404 record_alignment (text_section, 2);
2405 record_alignment (data_section, 2);
2406 record_alignment (bss_section, 2);
2407 }
2408#endif
a4447b93
RH		 2409
2410 if (flag_code == CODE_64BIT)
2411 {
ca19b261
KT		 2412#if defined (OBJ_COFF) && defined (TE_PE)
2413 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2414 ? 32 : 16);
2415#else
a4447b93 2416 x86_dwarf2_return_column = 16;
ca19b261 2417#endif
61ff971f 2418 x86_cie_data_alignment = -8;
a4447b93
RH		 2419 }
2420 else
2421 {
2422 x86_dwarf2_return_column = 8;
2423 x86_cie_data_alignment = -4;
2424 }
252b5132
RH		 2425}
2426
2427void
e3bb37b5 2428i386_print_statistics (FILE *file)
252b5132
RH		 2429{
2430 hash_print_statistics (file, "i386 opcode", op_hash);
2431 hash_print_statistics (file, "i386 register", reg_hash);
2432}
2433\f
252b5132
RH		 2434#ifdef DEBUG386
2435
ce8a8b2f 2436/* Debugging routines for md_assemble. */
d3ce72d0 2437static void pte (insn_template *);
40fb9820 2438static void pt (i386_operand_type);
e3bb37b5
L		 2439static void pe (expressionS *);
2440static void ps (symbolS *);
252b5132
RH		 2441
2442static void
e3bb37b5 2443pi (char *line, i386_insn *x)
252b5132 2444{
09137c09 2445 unsigned int j;
252b5132
RH		 2446
2447 fprintf (stdout, "%s: template ", line);
2448 pte (&x->tm);
09f131f2
JH		 2449 fprintf (stdout, " address: base %s index %s scale %x\n",
2450 x->base_reg ? x->base_reg->reg_name : "none",
2451 x->index_reg ? x->index_reg->reg_name : "none",
2452 x->log2_scale_factor);
2453 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2454 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2455 fprintf (stdout, " sib: base %x index %x scale %x\n",
2456 x->sib.base, x->sib.index, x->sib.scale);
2457 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2458 (x->rex & REX_W) != 0,
2459 (x->rex & REX_R) != 0,
2460 (x->rex & REX_X) != 0,
2461 (x->rex & REX_B) != 0);
09137c09 2462 for (j = 0; j < x->operands; j++)
252b5132 2463 {
09137c09
SP		 2464 fprintf (stdout, " #%d: ", j + 1);
2465 pt (x->types[j]);
252b5132 2466 fprintf (stdout, "\n");
09137c09
SP		 2467 if (x->types[j].bitfield.reg8
2468 || x->types[j].bitfield.reg16
2469 || x->types[j].bitfield.reg32
2470 || x->types[j].bitfield.reg64
2471 || x->types[j].bitfield.regmmx
2472 || x->types[j].bitfield.regxmm
2473 || x->types[j].bitfield.regymm
2474 || x->types[j].bitfield.sreg2
2475 || x->types[j].bitfield.sreg3
2476 || x->types[j].bitfield.control
2477 || x->types[j].bitfield.debug
2478 || x->types[j].bitfield.test)
2479 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2480 if (operand_type_check (x->types[j], imm))
2481 pe (x->op[j].imms);
2482 if (operand_type_check (x->types[j], disp))
2483 pe (x->op[j].disps);
252b5132
RH		 2484 }
2485}
2486
2487static void
d3ce72d0 2488pte (insn_template *t)
252b5132 2489{
09137c09 2490 unsigned int j;
252b5132 2491 fprintf (stdout, " %d operands ", t->operands);
47926f60 2492 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2493 if (t->extension_opcode != None)
2494 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2495 if (t->opcode_modifier.d)
252b5132 2496 fprintf (stdout, "D");
40fb9820 2497 if (t->opcode_modifier.w)
252b5132
RH		 2498 fprintf (stdout, "W");
2499 fprintf (stdout, "\n");
09137c09 2500 for (j = 0; j < t->operands; j++)
252b5132 2501 {
09137c09
SP		 2502 fprintf (stdout, " #%d type ", j + 1);
2503 pt (t->operand_types[j]);
252b5132
RH		 2504 fprintf (stdout, "\n");
2505 }
2506}
2507
2508static void
e3bb37b5 2509pe (expressionS *e)
252b5132 2510{
24eab124 2511 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2512 fprintf (stdout, " add_number %ld (%lx)\n",
2513 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2514 if (e->X_add_symbol)
2515 {
2516 fprintf (stdout, " add_symbol ");
2517 ps (e->X_add_symbol);
2518 fprintf (stdout, "\n");
2519 }
2520 if (e->X_op_symbol)
2521 {
2522 fprintf (stdout, " op_symbol ");
2523 ps (e->X_op_symbol);
2524 fprintf (stdout, "\n");
2525 }
2526}
2527
2528static void
e3bb37b5 2529ps (symbolS *s)
252b5132
RH		 2530{
2531 fprintf (stdout, "%s type %s%s",
2532 S_GET_NAME (s),
2533 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2534 segment_name (S_GET_SEGMENT (s)));
2535}
2536
7b81dfbb 2537static struct type_name
252b5132 2538 {
40fb9820
L		 2539 i386_operand_type mask;
2540 const char *name;
252b5132 2541 }
7b81dfbb 2542const type_names[] =
252b5132 2543{
40fb9820
L		 2544 { OPERAND_TYPE_REG8, "r8" },
2545 { OPERAND_TYPE_REG16, "r16" },
2546 { OPERAND_TYPE_REG32, "r32" },
2547 { OPERAND_TYPE_REG64, "r64" },
2548 { OPERAND_TYPE_IMM8, "i8" },
2549 { OPERAND_TYPE_IMM8, "i8s" },
2550 { OPERAND_TYPE_IMM16, "i16" },
2551 { OPERAND_TYPE_IMM32, "i32" },
2552 { OPERAND_TYPE_IMM32S, "i32s" },
2553 { OPERAND_TYPE_IMM64, "i64" },
2554 { OPERAND_TYPE_IMM1, "i1" },
2555 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2556 { OPERAND_TYPE_DISP8, "d8" },
2557 { OPERAND_TYPE_DISP16, "d16" },
2558 { OPERAND_TYPE_DISP32, "d32" },
2559 { OPERAND_TYPE_DISP32S, "d32s" },
2560 { OPERAND_TYPE_DISP64, "d64" },
2561 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2562 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2563 { OPERAND_TYPE_CONTROL, "control reg" },
2564 { OPERAND_TYPE_TEST, "test reg" },
2565 { OPERAND_TYPE_DEBUG, "debug reg" },
2566 { OPERAND_TYPE_FLOATREG, "FReg" },
2567 { OPERAND_TYPE_FLOATACC, "FAcc" },
2568 { OPERAND_TYPE_SREG2, "SReg2" },
2569 { OPERAND_TYPE_SREG3, "SReg3" },
2570 { OPERAND_TYPE_ACC, "Acc" },
2571 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2572 { OPERAND_TYPE_REGMMX, "rMMX" },
2573 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2574 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2575 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2576};
2577
2578static void
40fb9820 2579pt (i386_operand_type t)
252b5132 2580{
40fb9820 2581 unsigned int j;
c6fb90c8 2582 i386_operand_type a;
252b5132 2583
40fb9820 2584 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2585 {
2586 a = operand_type_and (t, type_names[j].mask);
0349dc08 2587 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2588 fprintf (stdout, "%s, ", type_names[j].name);
2589 }
252b5132
RH		 2590 fflush (stdout);
2591}
2592
2593#endif /* DEBUG386 */
2594\f
252b5132 2595static bfd_reloc_code_real_type
3956db08 2596reloc (unsigned int size,
64e74474
AM		 2597 int pcrel,
2598 int sign,
2599 bfd_reloc_code_real_type other)
252b5132 2600{
47926f60 2601 if (other != NO_RELOC)
3956db08 2602 {
91d6fa6a 2603 reloc_howto_type *rel;
3956db08
JB		 2604
2605 if (size == 8)
2606 switch (other)
2607 {
64e74474
AM		 2608 case BFD_RELOC_X86_64_GOT32:
2609 return BFD_RELOC_X86_64_GOT64;
2610 break;
2611 case BFD_RELOC_X86_64_PLTOFF64:
2612 return BFD_RELOC_X86_64_PLTOFF64;
2613 break;
2614 case BFD_RELOC_X86_64_GOTPC32:
2615 other = BFD_RELOC_X86_64_GOTPC64;
2616 break;
2617 case BFD_RELOC_X86_64_GOTPCREL:
2618 other = BFD_RELOC_X86_64_GOTPCREL64;
2619 break;
2620 case BFD_RELOC_X86_64_TPOFF32:
2621 other = BFD_RELOC_X86_64_TPOFF64;
2622 break;
2623 case BFD_RELOC_X86_64_DTPOFF32:
2624 other = BFD_RELOC_X86_64_DTPOFF64;
2625 break;
2626 default:
2627 break;
3956db08 2628 }
e05278af
JB		 2629
2630 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2631 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2632 sign = -1;
2633
91d6fa6a
NC		 2634 rel = bfd_reloc_type_lookup (stdoutput, other);
2635 if (!rel)
3956db08 2636 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2637 else if (size != bfd_get_reloc_size (rel))
3956db08 2638 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2639 bfd_get_reloc_size (rel),
3956db08 2640 size);
91d6fa6a 2641 else if (pcrel && !rel->pc_relative)
3956db08 2642 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2643 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2644 && !sign)
91d6fa6a 2645 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2646 && sign > 0))
3956db08
JB		 2647 as_bad (_("relocated field and relocation type differ in signedness"));
2648 else
2649 return other;
2650 return NO_RELOC;
2651 }
252b5132
RH		 2652
2653 if (pcrel)
2654 {
3e73aa7c 2655 if (!sign)
3956db08 2656 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2657 switch (size)
2658 {
2659 case 1: return BFD_RELOC_8_PCREL;
2660 case 2: return BFD_RELOC_16_PCREL;
2661 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2662 case 8: return BFD_RELOC_64_PCREL;
252b5132 2663 }
3956db08 2664 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2665 }
2666 else
2667 {
3956db08 2668 if (sign > 0)
e5cb08ac 2669 switch (size)
3e73aa7c
JH		 2670 {
2671 case 4: return BFD_RELOC_X86_64_32S;
2672 }
2673 else
2674 switch (size)
2675 {
2676 case 1: return BFD_RELOC_8;
2677 case 2: return BFD_RELOC_16;
2678 case 4: return BFD_RELOC_32;
2679 case 8: return BFD_RELOC_64;
2680 }
3956db08
JB		 2681 as_bad (_("cannot do %s %u byte relocation"),
2682 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2683 }
2684
0cc9e1d3 2685 return NO_RELOC;
252b5132
RH		 2686}
2687
47926f60
KH		 2688/* Here we decide which fixups can be adjusted to make them relative to
2689 the beginning of the section instead of the symbol. Basically we need
2690 to make sure that the dynamic relocations are done correctly, so in
2691 some cases we force the original symbol to be used. */
2692
252b5132 2693int
e3bb37b5 2694tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2695{
6d249963 2696#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2697 if (!IS_ELF)
31312f95
AM		 2698 return 1;
2699
a161fe53
AM		 2700 /* Don't adjust pc-relative references to merge sections in 64-bit
2701 mode. */
2702 if (use_rela_relocations
2703 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2704 && fixP->fx_pcrel)
252b5132 2705 return 0;
31312f95 2706
8d01d9a9
AJ		 2707 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2708 and changed later by validate_fix. */
2709 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2710 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2711 return 0;
2712
ce8a8b2f 2713 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2714 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2715 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2716 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2717 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2718 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2719 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2720 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2721 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2722 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2723 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2724 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2725 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2726 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2727 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2728 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2729 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2730 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2731 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2732 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2733 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2734 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2735 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2736 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2737 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2738 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2739 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2740 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2741 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2742 return 0;
31312f95 2743#endif
252b5132
RH		 2744 return 1;
2745}
252b5132 2746
b4cac588 2747static int
e3bb37b5 2748intel_float_operand (const char *mnemonic)
252b5132 2749{
9306ca4a
JB		 2750 /* Note that the value returned is meaningful only for opcodes with (memory)
2751 operands, hence the code here is free to improperly handle opcodes that
2752 have no operands (for better performance and smaller code). */
2753
2754 if (mnemonic[0] != 'f')
2755 return 0; /* non-math */
2756
2757 switch (mnemonic[1])
2758 {
2759 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2760 the fs segment override prefix not currently handled because no
2761 call path can make opcodes without operands get here */
2762 case 'i':
2763 return 2 /* integer op */;
2764 case 'l':
2765 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2766 return 3; /* fldcw/fldenv */
2767 break;
2768 case 'n':
2769 if (mnemonic[2] != 'o' /* fnop */)
2770 return 3; /* non-waiting control op */
2771 break;
2772 case 'r':
2773 if (mnemonic[2] == 's')
2774 return 3; /* frstor/frstpm */
2775 break;
2776 case 's':
2777 if (mnemonic[2] == 'a')
2778 return 3; /* fsave */
2779 if (mnemonic[2] == 't')
2780 {
2781 switch (mnemonic[3])
2782 {
2783 case 'c': /* fstcw */
2784 case 'd': /* fstdw */
2785 case 'e': /* fstenv */
2786 case 's': /* fsts[gw] */
2787 return 3;
2788 }
2789 }
2790 break;
2791 case 'x':
2792 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2793 return 0; /* fxsave/fxrstor are not really math ops */
2794 break;
2795 }
252b5132 2796
9306ca4a 2797 return 1;
252b5132
RH		 2798}
2799
c0f3af97
L		 2800/* Build the VEX prefix. */
2801
2802static void
d3ce72d0 2803build_vex_prefix (const insn_template *t)
c0f3af97
L		 2804{
2805 unsigned int register_specifier;
2806 unsigned int implied_prefix;
2807 unsigned int vector_length;
2808
2809 /* Check register specifier. */
2810 if (i.vex.register_specifier)
2811 {
2812 register_specifier = i.vex.register_specifier->reg_num;
2813 if ((i.vex.register_specifier->reg_flags & RegRex))
2814 register_specifier += 8;
2815 register_specifier = ~register_specifier & 0xf;
2816 }
2817 else
2818 register_specifier = 0xf;
2819
fa99fab2
L		 2820 /* Use 2-byte VEX prefix by swappping destination and source
2821 operand. */
2822 if (!i.swap_operand
2823 && i.operands == i.reg_operands
7f399153 2824 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2825 && i.tm.opcode_modifier.s
2826 && i.rex == REX_B)
2827 {
2828 unsigned int xchg = i.operands - 1;
2829 union i386_op temp_op;
2830 i386_operand_type temp_type;
2831
2832 temp_type = i.types[xchg];
2833 i.types[xchg] = i.types[0];
2834 i.types[0] = temp_type;
2835 temp_op = i.op[xchg];
2836 i.op[xchg] = i.op[0];
2837 i.op[0] = temp_op;
2838
9c2799c2 2839 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2840
2841 i.rex = REX_R;
2842 xchg = i.rm.regmem;
2843 i.rm.regmem = i.rm.reg;
2844 i.rm.reg = xchg;
2845
2846 /* Use the next insn. */
2847 i.tm = t[1];
2848 }
2849
539f890d
L		 2850 if (i.tm.opcode_modifier.vex == VEXScalar)
2851 vector_length = avxscalar;
2852 else
2853 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2854
2855 switch ((i.tm.base_opcode >> 8) & 0xff)
2856 {
2857 case 0:
2858 implied_prefix = 0;
2859 break;
2860 case DATA_PREFIX_OPCODE:
2861 implied_prefix = 1;
2862 break;
2863 case REPE_PREFIX_OPCODE:
2864 implied_prefix = 2;
2865 break;
2866 case REPNE_PREFIX_OPCODE:
2867 implied_prefix = 3;
2868 break;
2869 default:
2870 abort ();
2871 }
2872
2873 /* Use 2-byte VEX prefix if possible. */
7f399153 2874 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 2875 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 2876 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2877 {
2878 /* 2-byte VEX prefix. */
2879 unsigned int r;
2880
2881 i.vex.length = 2;
2882 i.vex.bytes[0] = 0xc5;
2883
2884 /* Check the REX.R bit. */
2885 r = (i.rex & REX_R) ? 0 : 1;
2886 i.vex.bytes[1] = (r << 7
2887 | register_specifier << 3
2888 | vector_length << 2
2889 | implied_prefix);
2890 }
2891 else
2892 {
2893 /* 3-byte VEX prefix. */
2894 unsigned int m, w;
2895
f88c9eb0 2896 i.vex.length = 3;
f88c9eb0 2897
7f399153 2898 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2899 {
7f399153
L		 2900 case VEX0F:
2901 m = 0x1;
80de6e00 2902 i.vex.bytes[0] = 0xc4;
7f399153
L		 2903 break;
2904 case VEX0F38:
2905 m = 0x2;
80de6e00 2906 i.vex.bytes[0] = 0xc4;
7f399153
L		 2907 break;
2908 case VEX0F3A:
2909 m = 0x3;
80de6e00 2910 i.vex.bytes[0] = 0xc4;
7f399153
L		 2911 break;
2912 case XOP08:
5dd85c99
SP		 2913 m = 0x8;
2914 i.vex.bytes[0] = 0x8f;
7f399153
L		 2915 break;
2916 case XOP09:
f88c9eb0
SP		 2917 m = 0x9;
2918 i.vex.bytes[0] = 0x8f;
7f399153
L		 2919 break;
2920 case XOP0A:
f88c9eb0
SP		 2921 m = 0xa;
2922 i.vex.bytes[0] = 0x8f;
7f399153
L		 2923 break;
2924 default:
2925 abort ();
f88c9eb0 2926 }
c0f3af97 2927
c0f3af97
L		 2928 /* The high 3 bits of the second VEX byte are 1's compliment
2929 of RXB bits from REX. */
2930 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2931
2932 /* Check the REX.W bit. */
2933 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2934 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2935 {
2936 if (w)
2937 abort ();
2938
1ef99a7b 2939 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2940 w = 1;
2941 }
2942
2943 i.vex.bytes[2] = (w << 7
2944 | register_specifier << 3
2945 | vector_length << 2
2946 | implied_prefix);
2947 }
2948}
2949
65da13b5
L		 2950static void
2951process_immext (void)
2952{
2953 expressionS *exp;
2954
2955 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2956 {
1fed0ba1
L		 2957 /* SSE3 Instructions have the fixed operands with an opcode
2958 suffix which is coded in the same place as an 8-bit immediate
2959 field would be. Here we check those operands and remove them
2960 afterwards. */
65da13b5
L		 2961 unsigned int x;
2962
2963 for (x = 0; x < i.operands; x++)
2964 if (i.op[x].regs->reg_num != x)
2965 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2966 register_prefix, i.op[x].regs->reg_name, x + 1,
2967 i.tm.name);
2968
2969 i.operands = 0;
65da13b5
L		 2970 }
2971
c0f3af97 2972 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2973 which is coded in the same place as an 8-bit immediate field
2974 would be. Here we fake an 8-bit immediate operand from the
2975 opcode suffix stored in tm.extension_opcode.
2976
c1e679ec 2977 AVX instructions also use this encoding, for some of
c0f3af97 2978 3 argument instructions. */
65da13b5 2979
9c2799c2 2980 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2981 && (i.operands <= 2
2982 || (i.tm.opcode_modifier.vex
2983 && i.operands <= 4)));
65da13b5
L		 2984
2985 exp = &im_expressions[i.imm_operands++];
2986 i.op[i.operands].imms = exp;
2987 i.types[i.operands] = imm8;
2988 i.operands++;
2989 exp->X_op = O_constant;
2990 exp->X_add_number = i.tm.extension_opcode;
2991 i.tm.extension_opcode = None;
2992}
2993
252b5132
RH		 2994/* This is the guts of the machine-dependent assembler. LINE points to a
2995 machine dependent instruction. This function is supposed to emit
2996 the frags/bytes it assembles to. */
2997
2998void
65da13b5 2999md_assemble (char *line)
252b5132 3000{
40fb9820 3001 unsigned int j;
252b5132 3002 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3003 const insn_template *t;
252b5132 3004
47926f60 3005 /* Initialize globals. */
252b5132
RH		 3006 memset (&i, '\0', sizeof (i));
3007 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3008 i.reloc[j] = NO_RELOC;
252b5132
RH		 3009 memset (disp_expressions, '\0', sizeof (disp_expressions));
3010 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3011 save_stack_p = save_stack;
252b5132
RH		 3012
3013 /* First parse an instruction mnemonic & call i386_operand for the operands.
3014 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3015 start of a (possibly prefixed) mnemonic. */
252b5132 3016
29b0f896
AM		 3017 line = parse_insn (line, mnemonic);
3018 if (line == NULL)
3019 return;
252b5132 3020
29b0f896 3021 line = parse_operands (line, mnemonic);
ee86248c 3022 this_operand = -1;
29b0f896
AM		 3023 if (line == NULL)
3024 return;
252b5132 3025
29b0f896
AM		 3026 /* Now we've parsed the mnemonic into a set of templates, and have the
3027 operands at hand. */
3028
3029 /* All intel opcodes have reversed operands except for "bound" and
3030 "enter". We also don't reverse intersegment "jmp" and "call"
3031 instructions with 2 immediate operands so that the immediate segment
050dfa73 3032 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3033 if (intel_syntax
3034 && i.operands > 1
29b0f896 3035 && (strcmp (mnemonic, "bound") != 0)
30123838 3036 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3037 && !(operand_type_check (i.types[0], imm)
3038 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3039 swap_operands ();
3040
ec56d5c0
JB		 3041 /* The order of the immediates should be reversed
3042 for 2 immediates extrq and insertq instructions */
3043 if (i.imm_operands == 2
3044 && (strcmp (mnemonic, "extrq") == 0
3045 || strcmp (mnemonic, "insertq") == 0))
3046 swap_2_operands (0, 1);
3047
29b0f896
AM		 3048 if (i.imm_operands)
3049 optimize_imm ();
3050
b300c311
L		 3051 /* Don't optimize displacement for movabs since it only takes 64bit
3052 displacement. */
3053 if (i.disp_operands
862be3fb
L		 3054 && !i.disp32_encoding
3055 && (flag_code != CODE_64BIT
3056 || strcmp (mnemonic, "movabs") != 0))
3057 optimize_disp ();
29b0f896
AM		 3058
3059 /* Next, we find a template that matches the given insn,
3060 making sure the overlap of the given operands types is consistent
3061 with the template operand types. */
252b5132 3062
fa99fab2 3063 if (!(t = match_template ()))
29b0f896 3064 return;
252b5132 3065
daf50ae7 3066 if (sse_check != sse_check_none
81f8a913 3067 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3068 && (i.tm.cpu_flags.bitfield.cpusse
3069 || i.tm.cpu_flags.bitfield.cpusse2
3070 || i.tm.cpu_flags.bitfield.cpusse3
3071 || i.tm.cpu_flags.bitfield.cpussse3
3072 || i.tm.cpu_flags.bitfield.cpusse4_1
3073 || i.tm.cpu_flags.bitfield.cpusse4_2))
3074 {
3075 (sse_check == sse_check_warning
3076 ? as_warn
3077 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3078 }
3079
321fd21e
L		 3080 /* Zap movzx and movsx suffix. The suffix has been set from
3081 "word ptr" or "byte ptr" on the source operand in Intel syntax
3082 or extracted from mnemonic in AT&T syntax. But we'll use
3083 the destination register to choose the suffix for encoding. */
3084 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3085 {
321fd21e
L		 3086 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3087 there is no suffix, the default will be byte extension. */
3088 if (i.reg_operands != 2
3089 && !i.suffix
7ab9ffdd 3090 && intel_syntax)
321fd21e
L		 3091 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3092
3093 i.suffix = 0;
cd61ebfe 3094 }
24eab124 3095
40fb9820 3096 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3097 if (!add_prefix (FWAIT_OPCODE))
3098 return;
252b5132 3099
c1ba0266
L		 3100 /* Check for lock without a lockable instruction. Destination operand
3101 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3102 if (i.prefix[LOCK_PREFIX]
3103 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3104 || i.mem_operands == 0
3105 || (i.tm.base_opcode != 0x86
3106 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3107 {
3108 as_bad (_("expecting lockable instruction after `lock'"));
3109 return;
3110 }
3111
29b0f896 3112 /* Check string instruction segment overrides. */
40fb9820 3113 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3114 {
3115 if (!check_string ())
5dd0794d 3116 return;
fc0763e6 3117 i.disp_operands = 0;
29b0f896 3118 }
5dd0794d 3119
29b0f896
AM		 3120 if (!process_suffix ())
3121 return;
e413e4e9 3122
bc0844ae
L		 3123 /* Update operand types. */
3124 for (j = 0; j < i.operands; j++)
3125 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3126
29b0f896
AM		 3127 /* Make still unresolved immediate matches conform to size of immediate
3128 given in i.suffix. */
3129 if (!finalize_imm ())
3130 return;
252b5132 3131
40fb9820 3132 if (i.types[0].bitfield.imm1)
29b0f896 3133 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3134
9afe6eb8
L		 3135 /* We only need to check those implicit registers for instructions
3136 with 3 operands or less. */
3137 if (i.operands <= 3)
3138 for (j = 0; j < i.operands; j++)
3139 if (i.types[j].bitfield.inoutportreg
3140 || i.types[j].bitfield.shiftcount
3141 || i.types[j].bitfield.acc
3142 || i.types[j].bitfield.floatacc)
3143 i.reg_operands--;
40fb9820 3144
c0f3af97
L		 3145 /* ImmExt should be processed after SSE2AVX. */
3146 if (!i.tm.opcode_modifier.sse2avx
3147 && i.tm.opcode_modifier.immext)
65da13b5 3148 process_immext ();
252b5132 3149
29b0f896
AM		 3150 /* For insns with operands there are more diddles to do to the opcode. */
3151 if (i.operands)
3152 {
3153 if (!process_operands ())
3154 return;
3155 }
40fb9820 3156 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3157 {
3158 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3159 as_warn (_("translating to `%sp'"), i.tm.name);
3160 }
252b5132 3161
c0f3af97 3162 if (i.tm.opcode_modifier.vex)
fa99fab2 3163 build_vex_prefix (t);
c0f3af97 3164
5dd85c99
SP		 3165 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3166 instructions may define INT_OPCODE as well, so avoid this corner
3167 case for those instructions that use MODRM. */
3168 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3169 && !i.tm.opcode_modifier.modrm
3170 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3171 {
3172 i.tm.base_opcode = INT3_OPCODE;
3173 i.imm_operands = 0;
3174 }
252b5132 3175
40fb9820
L		 3176 if ((i.tm.opcode_modifier.jump
3177 || i.tm.opcode_modifier.jumpbyte
3178 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3179 && i.op[0].disps->X_op == O_constant)
3180 {
3181 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3182 the absolute address given by the constant. Since ix86 jumps and
3183 calls are pc relative, we need to generate a reloc. */
3184 i.op[0].disps->X_add_symbol = &abs_symbol;
3185 i.op[0].disps->X_op = O_symbol;
3186 }
252b5132 3187
40fb9820 3188 if (i.tm.opcode_modifier.rex64)
161a04f6 3189 i.rex |= REX_W;
252b5132 3190
29b0f896
AM		 3191 /* For 8 bit registers we need an empty rex prefix. Also if the
3192 instruction already has a prefix, we need to convert old
3193 registers to new ones. */
773f551c 3194
40fb9820 3195 if ((i.types[0].bitfield.reg8
29b0f896 3196 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3197 || (i.types[1].bitfield.reg8
29b0f896 3198 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3199 || ((i.types[0].bitfield.reg8
3200 || i.types[1].bitfield.reg8)
29b0f896
AM		 3201 && i.rex != 0))
3202 {
3203 int x;
726c5dcd 3204
29b0f896
AM		 3205 i.rex |= REX_OPCODE;
3206 for (x = 0; x < 2; x++)
3207 {
3208 /* Look for 8 bit operand that uses old registers. */
40fb9820 3209 if (i.types[x].bitfield.reg8
29b0f896 3210 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3211 {
29b0f896
AM		 3212 /* In case it is "hi" register, give up. */
3213 if (i.op[x].regs->reg_num > 3)
a540244d 3214 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3215 "instruction requiring REX prefix."),
a540244d 3216 register_prefix, i.op[x].regs->reg_name);
773f551c 3217
29b0f896
AM		 3218 /* Otherwise it is equivalent to the extended register.
3219 Since the encoding doesn't change this is merely
3220 cosmetic cleanup for debug output. */
3221
3222 i.op[x].regs = i.op[x].regs + 8;
773f551c 3223 }
29b0f896
AM		 3224 }
3225 }
773f551c 3226
7ab9ffdd 3227 if (i.rex != 0)
29b0f896
AM		 3228 add_prefix (REX_OPCODE | i.rex);
3229
3230 /* We are ready to output the insn. */
3231 output_insn ();
3232}
3233
3234static char *
e3bb37b5 3235parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3236{
3237 char *l = line;
3238 char *token_start = l;
3239 char *mnem_p;
5c6af06e 3240 int supported;
d3ce72d0 3241 const insn_template *t;
b6169b20 3242 char *dot_p = NULL;
29b0f896
AM		 3243
3244 /* Non-zero if we found a prefix only acceptable with string insns. */
3245 const char *expecting_string_instruction = NULL;
45288df1 3246
29b0f896
AM		 3247 while (1)
3248 {
3249 mnem_p = mnemonic;
3250 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3251 {
b6169b20
L		 3252 if (*mnem_p == '.')
3253 dot_p = mnem_p;
29b0f896
AM		 3254 mnem_p++;
3255 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3256 {
29b0f896
AM		 3257 as_bad (_("no such instruction: `%s'"), token_start);
3258 return NULL;
3259 }
3260 l++;
3261 }
3262 if (!is_space_char (*l)
3263 && *l != END_OF_INSN
e44823cf
JB		 3264 && (intel_syntax
3265 || (*l != PREFIX_SEPARATOR
3266 && *l != ',')))
29b0f896
AM		 3267 {
3268 as_bad (_("invalid character %s in mnemonic"),
3269 output_invalid (*l));
3270 return NULL;
3271 }
3272 if (token_start == l)
3273 {
e44823cf 3274 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3275 as_bad (_("expecting prefix; got nothing"));
3276 else
3277 as_bad (_("expecting mnemonic; got nothing"));
3278 return NULL;
3279 }
45288df1 3280
29b0f896 3281 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3282 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3283
29b0f896
AM		 3284 if (*l != END_OF_INSN
3285 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3286 && current_templates
40fb9820 3287 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3288 {
c6fb90c8 3289 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3290 {
3291 as_bad ((flag_code != CODE_64BIT
3292 ? _("`%s' is only supported in 64-bit mode")
3293 : _("`%s' is not supported in 64-bit mode")),
3294 current_templates->start->name);
3295 return NULL;
3296 }
29b0f896
AM		 3297 /* If we are in 16-bit mode, do not allow addr16 or data16.
3298 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3299 if ((current_templates->start->opcode_modifier.size16
3300 || current_templates->start->opcode_modifier.size32)
29b0f896 3301 && flag_code != CODE_64BIT
40fb9820 3302 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3303 ^ (flag_code == CODE_16BIT)))
3304 {
3305 as_bad (_("redundant %s prefix"),
3306 current_templates->start->name);
3307 return NULL;
45288df1 3308 }
29b0f896
AM		 3309 /* Add prefix, checking for repeated prefixes. */
3310 switch (add_prefix (current_templates->start->base_opcode))
3311 {
c32fa91d 3312 case PREFIX_EXIST:
29b0f896 3313 return NULL;
c32fa91d 3314 case PREFIX_REP:
29b0f896
AM		 3315 expecting_string_instruction = current_templates->start->name;
3316 break;
c32fa91d
L		 3317 default:
3318 break;
29b0f896
AM		 3319 }
3320 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3321 token_start = ++l;
3322 }
3323 else
3324 break;
3325 }
45288df1 3326
30a55f88 3327 if (!current_templates)
b6169b20 3328 {
f8a5c266
L		 3329 /* Check if we should swap operand or force 32bit displacement in
3330 encoding. */
30a55f88
L		 3331 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3332 i.swap_operand = 1;
f8a5c266
L		 3333 else if (mnem_p - 4 == dot_p
3334 && dot_p[1] == 'd'
3335 && dot_p[2] == '3'
3336 && dot_p[3] == '2')
3337 i.disp32_encoding = 1;
30a55f88
L		 3338 else
3339 goto check_suffix;
3340 mnem_p = dot_p;
3341 *dot_p = '\0';
d3ce72d0 3342 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3343 }
3344
29b0f896
AM		 3345 if (!current_templates)
3346 {
b6169b20 3347check_suffix:
29b0f896
AM		 3348 /* See if we can get a match by trimming off a suffix. */
3349 switch (mnem_p[-1])
3350 {
3351 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3352 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3353 i.suffix = SHORT_MNEM_SUFFIX;
3354 else
29b0f896
AM		 3355 case BYTE_MNEM_SUFFIX:
3356 case QWORD_MNEM_SUFFIX:
3357 i.suffix = mnem_p[-1];
3358 mnem_p[-1] = '\0';
d3ce72d0
NC		 3359 current_templates = (const templates *) hash_find (op_hash,
3360 mnemonic);
29b0f896
AM		 3361 break;
3362 case SHORT_MNEM_SUFFIX:
3363 case LONG_MNEM_SUFFIX:
3364 if (!intel_syntax)
3365 {
3366 i.suffix = mnem_p[-1];
3367 mnem_p[-1] = '\0';
d3ce72d0
NC		 3368 current_templates = (const templates *) hash_find (op_hash,
3369 mnemonic);
29b0f896
AM		 3370 }
3371 break;
252b5132 3372
29b0f896
AM		 3373 /* Intel Syntax. */
3374 case 'd':
3375 if (intel_syntax)
3376 {
9306ca4a 3377 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3378 i.suffix = SHORT_MNEM_SUFFIX;
3379 else
3380 i.suffix = LONG_MNEM_SUFFIX;
3381 mnem_p[-1] = '\0';
d3ce72d0
NC		 3382 current_templates = (const templates *) hash_find (op_hash,
3383 mnemonic);
29b0f896
AM		 3384 }
3385 break;
3386 }
3387 if (!current_templates)
3388 {
3389 as_bad (_("no such instruction: `%s'"), token_start);
3390 return NULL;
3391 }
3392 }
252b5132 3393
40fb9820
L		 3394 if (current_templates->start->opcode_modifier.jump
3395 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3396 {
3397 /* Check for a branch hint. We allow ",pt" and ",pn" for
3398 predict taken and predict not taken respectively.
3399 I'm not sure that branch hints actually do anything on loop
3400 and jcxz insns (JumpByte) for current Pentium4 chips. They
3401 may work in the future and it doesn't hurt to accept them
3402 now. */
3403 if (l[0] == ',' && l[1] == 'p')
3404 {
3405 if (l[2] == 't')
3406 {
3407 if (!add_prefix (DS_PREFIX_OPCODE))
3408 return NULL;
3409 l += 3;
3410 }
3411 else if (l[2] == 'n')
3412 {
3413 if (!add_prefix (CS_PREFIX_OPCODE))
3414 return NULL;
3415 l += 3;
3416 }
3417 }
3418 }
3419 /* Any other comma loses. */
3420 if (*l == ',')
3421 {
3422 as_bad (_("invalid character %s in mnemonic"),
3423 output_invalid (*l));
3424 return NULL;
3425 }
252b5132 3426
29b0f896 3427 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3428 supported = 0;
3429 for (t = current_templates->start; t < current_templates->end; ++t)
3430 {
c0f3af97
L		 3431 supported |= cpu_flags_match (t);
3432 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3433 goto skip;
5c6af06e 3434 }
3629bb00 3435
c0f3af97 3436 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3437 {
3438 as_bad (flag_code == CODE_64BIT
3439 ? _("`%s' is not supported in 64-bit mode")
3440 : _("`%s' is only supported in 64-bit mode"),
3441 current_templates->start->name);
3442 return NULL;
3443 }
c0f3af97 3444 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3445 {
3629bb00 3446 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3447 current_templates->start->name,
41aacd83 3448 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3449 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3450 return NULL;
29b0f896 3451 }
3629bb00
L		 3452
3453skip:
3454 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3455 && (flag_code != CODE_16BIT))
29b0f896
AM		 3456 {
3457 as_warn (_("use .code16 to ensure correct addressing mode"));
3458 }
252b5132 3459
29b0f896 3460 /* Check for rep/repne without a string instruction. */
f41bbced 3461 if (expecting_string_instruction)
29b0f896 3462 {
f41bbced
JB		 3463 static templates override;
3464
3465 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3466 if (t->opcode_modifier.isstring)
f41bbced
JB		 3467 break;
3468 if (t >= current_templates->end)
3469 {
3470 as_bad (_("expecting string instruction after `%s'"),
64e74474 3471 expecting_string_instruction);
f41bbced
JB		 3472 return NULL;
3473 }
3474 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3475 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3476 break;
3477 override.end = t;
3478 current_templates = &override;
29b0f896 3479 }
252b5132 3480
29b0f896
AM		 3481 return l;
3482}
252b5132 3483
29b0f896 3484static char *
e3bb37b5 3485parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3486{
3487 char *token_start;
3138f287 3488
29b0f896
AM		 3489 /* 1 if operand is pending after ','. */
3490 unsigned int expecting_operand = 0;
252b5132 3491
29b0f896
AM		 3492 /* Non-zero if operand parens not balanced. */
3493 unsigned int paren_not_balanced;
3494
3495 while (*l != END_OF_INSN)
3496 {
3497 /* Skip optional white space before operand. */
3498 if (is_space_char (*l))
3499 ++l;
3500 if (!is_operand_char (*l) && *l != END_OF_INSN)
3501 {
3502 as_bad (_("invalid character %s before operand %d"),
3503 output_invalid (*l),
3504 i.operands + 1);
3505 return NULL;
3506 }
3507 token_start = l; /* after white space */
3508 paren_not_balanced = 0;
3509 while (paren_not_balanced || *l != ',')
3510 {
3511 if (*l == END_OF_INSN)
3512 {
3513 if (paren_not_balanced)
3514 {
3515 if (!intel_syntax)
3516 as_bad (_("unbalanced parenthesis in operand %d."),
3517 i.operands + 1);
3518 else
3519 as_bad (_("unbalanced brackets in operand %d."),
3520 i.operands + 1);
3521 return NULL;
3522 }
3523 else
3524 break; /* we are done */
3525 }
3526 else if (!is_operand_char (*l) && !is_space_char (*l))
3527 {
3528 as_bad (_("invalid character %s in operand %d"),
3529 output_invalid (*l),
3530 i.operands + 1);
3531 return NULL;
3532 }
3533 if (!intel_syntax)
3534 {
3535 if (*l == '(')
3536 ++paren_not_balanced;
3537 if (*l == ')')
3538 --paren_not_balanced;
3539 }
3540 else
3541 {
3542 if (*l == '[')
3543 ++paren_not_balanced;
3544 if (*l == ']')
3545 --paren_not_balanced;
3546 }
3547 l++;
3548 }
3549 if (l != token_start)
3550 { /* Yes, we've read in another operand. */
3551 unsigned int operand_ok;
3552 this_operand = i.operands++;
7d5e4556 3553 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3554 if (i.operands > MAX_OPERANDS)
3555 {
3556 as_bad (_("spurious operands; (%d operands/instruction max)"),
3557 MAX_OPERANDS);
3558 return NULL;
3559 }
3560 /* Now parse operand adding info to 'i' as we go along. */
3561 END_STRING_AND_SAVE (l);
3562
3563 if (intel_syntax)
3564 operand_ok =
3565 i386_intel_operand (token_start,
3566 intel_float_operand (mnemonic));
3567 else
a7619375 3568 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3569
3570 RESTORE_END_STRING (l);
3571 if (!operand_ok)
3572 return NULL;
3573 }
3574 else
3575 {
3576 if (expecting_operand)
3577 {
3578 expecting_operand_after_comma:
3579 as_bad (_("expecting operand after ','; got nothing"));
3580 return NULL;
3581 }
3582 if (*l == ',')
3583 {
3584 as_bad (_("expecting operand before ','; got nothing"));
3585 return NULL;
3586 }
3587 }
7f3f1ea2 3588
29b0f896
AM		 3589 /* Now *l must be either ',' or END_OF_INSN. */
3590 if (*l == ',')
3591 {
3592 if (*++l == END_OF_INSN)
3593 {
3594 /* Just skip it, if it's \n complain. */
3595 goto expecting_operand_after_comma;
3596 }
3597 expecting_operand = 1;
3598 }
3599 }
3600 return l;
3601}
7f3f1ea2 3602
050dfa73 3603static void
4d456e3d 3604swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3605{
3606 union i386_op temp_op;
40fb9820 3607 i386_operand_type temp_type;
050dfa73 3608 enum bfd_reloc_code_real temp_reloc;
4eed87de 3609
050dfa73
MM		 3610 temp_type = i.types[xchg2];
3611 i.types[xchg2] = i.types[xchg1];
3612 i.types[xchg1] = temp_type;
3613 temp_op = i.op[xchg2];
3614 i.op[xchg2] = i.op[xchg1];
3615 i.op[xchg1] = temp_op;
3616 temp_reloc = i.reloc[xchg2];
3617 i.reloc[xchg2] = i.reloc[xchg1];
3618 i.reloc[xchg1] = temp_reloc;
3619}
3620
29b0f896 3621static void
e3bb37b5 3622swap_operands (void)
29b0f896 3623{
b7c61d9a 3624 switch (i.operands)
050dfa73 3625 {
c0f3af97 3626 case 5:
b7c61d9a 3627 case 4:
4d456e3d 3628 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3629 case 3:
3630 case 2:
4d456e3d 3631 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3632 break;
3633 default:
3634 abort ();
29b0f896 3635 }
29b0f896
AM		 3636
3637 if (i.mem_operands == 2)
3638 {
3639 const seg_entry *temp_seg;
3640 temp_seg = i.seg[0];
3641 i.seg[0] = i.seg[1];
3642 i.seg[1] = temp_seg;
3643 }
3644}
252b5132 3645
29b0f896
AM		 3646/* Try to ensure constant immediates are represented in the smallest
3647 opcode possible. */
3648static void
e3bb37b5 3649optimize_imm (void)
29b0f896
AM		 3650{
3651 char guess_suffix = 0;
3652 int op;
252b5132 3653
29b0f896
AM		 3654 if (i.suffix)
3655 guess_suffix = i.suffix;
3656 else if (i.reg_operands)
3657 {
3658 /* Figure out a suffix from the last register operand specified.
3659 We can't do this properly yet, ie. excluding InOutPortReg,
3660 but the following works for instructions with immediates.
3661 In any case, we can't set i.suffix yet. */
3662 for (op = i.operands; --op >= 0;)
40fb9820 3663 if (i.types[op].bitfield.reg8)
7ab9ffdd 3664 {
40fb9820
L		 3665 guess_suffix = BYTE_MNEM_SUFFIX;
3666 break;
3667 }
3668 else if (i.types[op].bitfield.reg16)
252b5132 3669 {
40fb9820
L		 3670 guess_suffix = WORD_MNEM_SUFFIX;
3671 break;
3672 }
3673 else if (i.types[op].bitfield.reg32)
3674 {
3675 guess_suffix = LONG_MNEM_SUFFIX;
3676 break;
3677 }
3678 else if (i.types[op].bitfield.reg64)
3679 {
3680 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3681 break;
252b5132 3682 }
29b0f896
AM		 3683 }
3684 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3685 guess_suffix = WORD_MNEM_SUFFIX;
3686
3687 for (op = i.operands; --op >= 0;)
40fb9820 3688 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3689 {
3690 switch (i.op[op].imms->X_op)
252b5132 3691 {
29b0f896
AM		 3692 case O_constant:
3693 /* If a suffix is given, this operand may be shortened. */
3694 switch (guess_suffix)
252b5132 3695 {
29b0f896 3696 case LONG_MNEM_SUFFIX:
40fb9820
L		 3697 i.types[op].bitfield.imm32 = 1;
3698 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3699 break;
3700 case WORD_MNEM_SUFFIX:
40fb9820
L		 3701 i.types[op].bitfield.imm16 = 1;
3702 i.types[op].bitfield.imm32 = 1;
3703 i.types[op].bitfield.imm32s = 1;
3704 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3705 break;
3706 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3707 i.types[op].bitfield.imm8 = 1;
3708 i.types[op].bitfield.imm8s = 1;
3709 i.types[op].bitfield.imm16 = 1;
3710 i.types[op].bitfield.imm32 = 1;
3711 i.types[op].bitfield.imm32s = 1;
3712 i.types[op].bitfield.imm64 = 1;
29b0f896 3713 break;
252b5132 3714 }
252b5132 3715
29b0f896
AM		 3716 /* If this operand is at most 16 bits, convert it
3717 to a signed 16 bit number before trying to see
3718 whether it will fit in an even smaller size.
3719 This allows a 16-bit operand such as $0xffe0 to
3720 be recognised as within Imm8S range. */
40fb9820 3721 if ((i.types[op].bitfield.imm16)
29b0f896 3722 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3723 {
29b0f896
AM		 3724 i.op[op].imms->X_add_number =
3725 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3726 }
40fb9820 3727 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3728 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3729 == 0))
3730 {
3731 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3732 ^ ((offsetT) 1 << 31))
3733 - ((offsetT) 1 << 31));
3734 }
40fb9820 3735 i.types[op]
c6fb90c8
L		 3736 = operand_type_or (i.types[op],
3737 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3738
29b0f896
AM		 3739 /* We must avoid matching of Imm32 templates when 64bit
3740 only immediate is available. */
3741 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3742 i.types[op].bitfield.imm32 = 0;
29b0f896 3743 break;
252b5132 3744
29b0f896
AM		 3745 case O_absent:
3746 case O_register:
3747 abort ();
3748
3749 /* Symbols and expressions. */
3750 default:
9cd96992
JB		 3751 /* Convert symbolic operand to proper sizes for matching, but don't
3752 prevent matching a set of insns that only supports sizes other
3753 than those matching the insn suffix. */
3754 {
40fb9820 3755 i386_operand_type mask, allowed;
d3ce72d0 3756 const insn_template *t;
9cd96992 3757
0dfbf9d7
L		 3758 operand_type_set (&mask, 0);
3759 operand_type_set (&allowed, 0);
40fb9820 3760
4eed87de
AM		 3761 for (t = current_templates->start;
3762 t < current_templates->end;
3763 ++t)
c6fb90c8
L		 3764 allowed = operand_type_or (allowed,
3765 t->operand_types[op]);
9cd96992
JB		 3766 switch (guess_suffix)
3767 {
3768 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3769 mask.bitfield.imm64 = 1;
3770 mask.bitfield.imm32s = 1;
9cd96992
JB		 3771 break;
3772 case LONG_MNEM_SUFFIX:
40fb9820 3773 mask.bitfield.imm32 = 1;
9cd96992
JB		 3774 break;
3775 case WORD_MNEM_SUFFIX:
40fb9820 3776 mask.bitfield.imm16 = 1;
9cd96992
JB		 3777 break;
3778 case BYTE_MNEM_SUFFIX:
40fb9820 3779 mask.bitfield.imm8 = 1;
9cd96992
JB		 3780 break;
3781 default:
9cd96992
JB		 3782 break;
3783 }
c6fb90c8 3784 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3785 if (!operand_type_all_zero (&allowed))
c6fb90c8 3786 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3787 }
29b0f896 3788 break;
252b5132 3789 }
29b0f896
AM		 3790 }
3791}
47926f60 3792
29b0f896
AM		 3793/* Try to use the smallest displacement type too. */
3794static void
e3bb37b5 3795optimize_disp (void)
29b0f896
AM		 3796{
3797 int op;
3e73aa7c 3798
29b0f896 3799 for (op = i.operands; --op >= 0;)
40fb9820 3800 if (operand_type_check (i.types[op], disp))
252b5132 3801 {
b300c311 3802 if (i.op[op].disps->X_op == O_constant)
252b5132 3803 {
91d6fa6a 3804 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3805
40fb9820 3806 if (i.types[op].bitfield.disp16
91d6fa6a 3807 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3808 {
3809 /* If this operand is at most 16 bits, convert
3810 to a signed 16 bit number and don't use 64bit
3811 displacement. */
91d6fa6a 3812 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3813 i.types[op].bitfield.disp64 = 0;
b300c311 3814 }
40fb9820 3815 if (i.types[op].bitfield.disp32
91d6fa6a 3816 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3817 {
3818 /* If this operand is at most 32 bits, convert
3819 to a signed 32 bit number and don't use 64bit
3820 displacement. */
91d6fa6a
NC		 3821 op_disp &= (((offsetT) 2 << 31) - 1);
3822 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3823 i.types[op].bitfield.disp64 = 0;
b300c311 3824 }
91d6fa6a 3825 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3826 {
40fb9820
L		 3827 i.types[op].bitfield.disp8 = 0;
3828 i.types[op].bitfield.disp16 = 0;
3829 i.types[op].bitfield.disp32 = 0;
3830 i.types[op].bitfield.disp32s = 0;
3831 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3832 i.op[op].disps = 0;
3833 i.disp_operands--;
3834 }
3835 else if (flag_code == CODE_64BIT)
3836 {
91d6fa6a 3837 if (fits_in_signed_long (op_disp))
28a9d8f5 3838 {
40fb9820
L		 3839 i.types[op].bitfield.disp64 = 0;
3840 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3841 }
0e1147d9 3842 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3843 && fits_in_unsigned_long (op_disp))
40fb9820 3844 i.types[op].bitfield.disp32 = 1;
b300c311 3845 }
40fb9820
L		 3846 if ((i.types[op].bitfield.disp32
3847 || i.types[op].bitfield.disp32s
3848 || i.types[op].bitfield.disp16)
91d6fa6a 3849 && fits_in_signed_byte (op_disp))
40fb9820 3850 i.types[op].bitfield.disp8 = 1;
252b5132 3851 }
67a4f2b7
AO		 3852 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3853 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3854 {
3855 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3856 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3857 i.types[op].bitfield.disp8 = 0;
3858 i.types[op].bitfield.disp16 = 0;
3859 i.types[op].bitfield.disp32 = 0;
3860 i.types[op].bitfield.disp32s = 0;
3861 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3862 }
3863 else
b300c311 3864 /* We only support 64bit displacement on constants. */
40fb9820 3865 i.types[op].bitfield.disp64 = 0;
252b5132 3866 }
29b0f896
AM		 3867}
3868
6c30d220
L		 3869/* Check if operands are valid for the instruction. */
3870
3871static int
3872check_VecOperands (const insn_template *t)
3873{
3874 /* Without VSIB byte, we can't have a vector register for index. */
3875 if (!t->opcode_modifier.vecsib
3876 && i.index_reg
3877 && (i.index_reg->reg_type.bitfield.regxmm
3878 || i.index_reg->reg_type.bitfield.regymm))
3879 {
3880 i.error = unsupported_vector_index_register;
3881 return 1;
3882 }
3883
3884 /* For VSIB byte, we need a vector register for index and no PC
3885 relative addressing is allowed. */
3886 if (t->opcode_modifier.vecsib
3887 && (!i.index_reg
3888 || !((t->opcode_modifier.vecsib == VecSIB128
3889 && i.index_reg->reg_type.bitfield.regxmm)
3890 || (t->opcode_modifier.vecsib == VecSIB256
3891 && i.index_reg->reg_type.bitfield.regymm))
3892 || (i.base_reg && i.base_reg->reg_num == RegRip)))
3893 {
3894 i.error = invalid_vsib_address;
3895 return 1;
3896 }
3897
3898 return 0;
3899}
3900
43f3e2ee 3901/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 3902 operand types. */
3903
3904static int
3905VEX_check_operands (const insn_template *t)
3906{
3907 if (!t->opcode_modifier.vex)
3908 return 0;
3909
3910 /* Only check VEX_Imm4, which must be the first operand. */
3911 if (t->operand_types[0].bitfield.vec_imm4)
3912 {
3913 if (i.op[0].imms->X_op != O_constant
3914 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 3915 {
a65babc9 3916 i.error = bad_imm4;
891edac4
L		 3917 return 1;
3918 }
a683cc34
SP		 3919
3920 /* Turn off Imm8 so that update_imm won't complain. */
3921 i.types[0] = vec_imm4;
3922 }
3923
3924 return 0;
3925}
3926
d3ce72d0 3927static const insn_template *
e3bb37b5 3928match_template (void)
29b0f896
AM		 3929{
3930 /* Points to template once we've found it. */
d3ce72d0 3931 const insn_template *t;
40fb9820 3932 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3933 i386_operand_type overlap4;
29b0f896 3934 unsigned int found_reverse_match;
40fb9820
L		 3935 i386_opcode_modifier suffix_check;
3936 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3937 int addr_prefix_disp;
a5c311ca 3938 unsigned int j;
3629bb00 3939 unsigned int found_cpu_match;
45664ddb 3940 unsigned int check_register;
29b0f896 3941
c0f3af97
L		 3942#if MAX_OPERANDS != 5
3943# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3944#endif
3945
29b0f896 3946 found_reverse_match = 0;
539e75ad 3947 addr_prefix_disp = -1;
40fb9820
L		 3948
3949 memset (&suffix_check, 0, sizeof (suffix_check));
3950 if (i.suffix == BYTE_MNEM_SUFFIX)
3951 suffix_check.no_bsuf = 1;
3952 else if (i.suffix == WORD_MNEM_SUFFIX)
3953 suffix_check.no_wsuf = 1;
3954 else if (i.suffix == SHORT_MNEM_SUFFIX)
3955 suffix_check.no_ssuf = 1;
3956 else if (i.suffix == LONG_MNEM_SUFFIX)
3957 suffix_check.no_lsuf = 1;
3958 else if (i.suffix == QWORD_MNEM_SUFFIX)
3959 suffix_check.no_qsuf = 1;
3960 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3961 suffix_check.no_ldsuf = 1;
29b0f896 3962
01559ecc
L		 3963 /* Must have right number of operands. */
3964 i.error = number_of_operands_mismatch;
3965
45aa61fe 3966 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3967 {
539e75ad
L		 3968 addr_prefix_disp = -1;
3969
29b0f896
AM		 3970 if (i.operands != t->operands)
3971 continue;
3972
50aecf8c 3973 /* Check processor support. */
a65babc9 3974 i.error = unsupported;
c0f3af97
L		 3975 found_cpu_match = (cpu_flags_match (t)
3976 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3977 if (!found_cpu_match)
3978 continue;
3979
e1d4d893 3980 /* Check old gcc support. */
a65babc9 3981 i.error = old_gcc_only;
e1d4d893
L		 3982 if (!old_gcc && t->opcode_modifier.oldgcc)
3983 continue;
3984
3985 /* Check AT&T mnemonic. */
a65babc9 3986 i.error = unsupported_with_intel_mnemonic;
e1d4d893 3987 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3988 continue;
3989
891edac4 3990 /* Check AT&T/Intel syntax. */
a65babc9 3991 i.error = unsupported_syntax;
5c07affc
L		 3992 if ((intel_syntax && t->opcode_modifier.attsyntax)
3993 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3994 continue;
3995
20592a94 3996 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 3997 i.error = invalid_instruction_suffix;
567e4e96
L		 3998 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3999 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4000 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4001 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4002 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4003 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4004 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4005 continue;
4006
5c07affc 4007 if (!operand_size_match (t))
7d5e4556 4008 continue;
539e75ad 4009
5c07affc
L		 4010 for (j = 0; j < MAX_OPERANDS; j++)
4011 operand_types[j] = t->operand_types[j];
4012
45aa61fe
AM		 4013 /* In general, don't allow 64-bit operands in 32-bit mode. */
4014 if (i.suffix == QWORD_MNEM_SUFFIX
4015 && flag_code != CODE_64BIT
4016 && (intel_syntax
40fb9820 4017 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4018 && !intel_float_operand (t->name))
4019 : intel_float_operand (t->name) != 2)
40fb9820 4020 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 4021 && !operand_types[0].bitfield.regxmm
4022 && !operand_types[0].bitfield.regymm)
40fb9820 4023 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 4024 && !!operand_types[t->operands > 1].bitfield.regxmm
4025 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 4026 && (t->base_opcode != 0x0fc7
4027 || t->extension_opcode != 1 /* cmpxchg8b */))
4028 continue;
4029
192dc9c6
JB		 4030 /* In general, don't allow 32-bit operands on pre-386. */
4031 else if (i.suffix == LONG_MNEM_SUFFIX
4032 && !cpu_arch_flags.bitfield.cpui386
4033 && (intel_syntax
4034 ? (!t->opcode_modifier.ignoresize
4035 && !intel_float_operand (t->name))
4036 : intel_float_operand (t->name) != 2)
4037 && ((!operand_types[0].bitfield.regmmx
4038 && !operand_types[0].bitfield.regxmm)
4039 || (!operand_types[t->operands > 1].bitfield.regmmx
4040 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4041 continue;
4042
29b0f896 4043 /* Do not verify operands when there are none. */
50aecf8c 4044 else
29b0f896 4045 {
c6fb90c8 4046 if (!t->operands)
2dbab7d5
L		 4047 /* We've found a match; break out of loop. */
4048 break;
29b0f896 4049 }
252b5132 4050
539e75ad
L		 4051 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4052 into Disp32/Disp16/Disp32 operand. */
4053 if (i.prefix[ADDR_PREFIX] != 0)
4054 {
40fb9820 4055 /* There should be only one Disp operand. */
539e75ad
L		 4056 switch (flag_code)
4057 {
4058 case CODE_16BIT:
40fb9820
L		 4059 for (j = 0; j < MAX_OPERANDS; j++)
4060 {
4061 if (operand_types[j].bitfield.disp16)
4062 {
4063 addr_prefix_disp = j;
4064 operand_types[j].bitfield.disp32 = 1;
4065 operand_types[j].bitfield.disp16 = 0;
4066 break;
4067 }
4068 }
539e75ad
L		 4069 break;
4070 case CODE_32BIT:
40fb9820
L		 4071 for (j = 0; j < MAX_OPERANDS; j++)
4072 {
4073 if (operand_types[j].bitfield.disp32)
4074 {
4075 addr_prefix_disp = j;
4076 operand_types[j].bitfield.disp32 = 0;
4077 operand_types[j].bitfield.disp16 = 1;
4078 break;
4079 }
4080 }
539e75ad
L		 4081 break;
4082 case CODE_64BIT:
40fb9820
L		 4083 for (j = 0; j < MAX_OPERANDS; j++)
4084 {
4085 if (operand_types[j].bitfield.disp64)
4086 {
4087 addr_prefix_disp = j;
4088 operand_types[j].bitfield.disp64 = 0;
4089 operand_types[j].bitfield.disp32 = 1;
4090 break;
4091 }
4092 }
539e75ad
L		 4093 break;
4094 }
539e75ad
L		 4095 }
4096
56ffb741
L		 4097 /* We check register size if needed. */
4098 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4099 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4100 switch (t->operands)
4101 {
4102 case 1:
40fb9820 4103 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4104 continue;
4105 break;
4106 case 2:
8b38ad71
L		 4107 /* xchg %eax, %eax is a special case. It is an aliase for nop
4108 only in 32bit mode and we can use opcode 0x90. In 64bit
4109 mode, we can't use 0x90 for xchg %eax, %eax since it should
4110 zero-extend %eax to %rax. */
4111 if (flag_code == CODE_64BIT
4112 && t->base_opcode == 0x90
0dfbf9d7
L		 4113 && operand_type_equal (&i.types [0], &acc32)
4114 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4115 continue;
b6169b20
L		 4116 if (i.swap_operand)
4117 {
4118 /* If we swap operand in encoding, we either match
4119 the next one or reverse direction of operands. */
4120 if (t->opcode_modifier.s)
4121 continue;
4122 else if (t->opcode_modifier.d)
4123 goto check_reverse;
4124 }
4125
29b0f896 4126 case 3:
fa99fab2
L		 4127 /* If we swap operand in encoding, we match the next one. */
4128 if (i.swap_operand && t->opcode_modifier.s)
4129 continue;
f48ff2ae 4130 case 4:
c0f3af97 4131 case 5:
c6fb90c8 4132 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4133 if (!operand_type_match (overlap0, i.types[0])
4134 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4135 || (check_register
4136 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4137 operand_types[0],
4138 overlap1, i.types[1],
4139 operand_types[1])))
29b0f896
AM		 4140 {
4141 /* Check if other direction is valid ... */
40fb9820 4142 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4143 continue;
4144
b6169b20 4145check_reverse:
29b0f896 4146 /* Try reversing direction of operands. */
c6fb90c8
L		 4147 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4148 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4149 if (!operand_type_match (overlap0, i.types[0])
4150 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4151 || (check_register
4152 && !operand_type_register_match (overlap0,
4153 i.types[0],
4154 operand_types[1],
4155 overlap1,
4156 i.types[1],
4157 operand_types[0])))
29b0f896
AM		 4158 {
4159 /* Does not match either direction. */
4160 continue;
4161 }
4162 /* found_reverse_match holds which of D or FloatDR
4163 we've found. */
40fb9820 4164 if (t->opcode_modifier.d)
8a2ed489 4165 found_reverse_match = Opcode_D;
40fb9820 4166 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4167 found_reverse_match = Opcode_FloatD;
4168 else
4169 found_reverse_match = 0;
40fb9820 4170 if (t->opcode_modifier.floatr)
8a2ed489 4171 found_reverse_match |= Opcode_FloatR;
29b0f896 4172 }
f48ff2ae 4173 else
29b0f896 4174 {
f48ff2ae 4175 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4176 switch (t->operands)
4177 {
c0f3af97
L		 4178 case 5:
4179 overlap4 = operand_type_and (i.types[4],
4180 operand_types[4]);
d1cbb4db 4181 case 4:
c6fb90c8
L		 4182 overlap3 = operand_type_and (i.types[3],
4183 operand_types[3]);
d1cbb4db 4184 case 3:
c6fb90c8
L		 4185 overlap2 = operand_type_and (i.types[2],
4186 operand_types[2]);
d1cbb4db
L		 4187 break;
4188 }
29b0f896 4189
f48ff2ae
L		 4190 switch (t->operands)
4191 {
c0f3af97
L		 4192 case 5:
4193 if (!operand_type_match (overlap4, i.types[4])
4194 || !operand_type_register_match (overlap3,
4195 i.types[3],
4196 operand_types[3],
4197 overlap4,
4198 i.types[4],
4199 operand_types[4]))
4200 continue;
f48ff2ae 4201 case 4:
40fb9820 4202 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4203 || (check_register
4204 && !operand_type_register_match (overlap2,
4205 i.types[2],
4206 operand_types[2],
4207 overlap3,
4208 i.types[3],
4209 operand_types[3])))
f48ff2ae
L		 4210 continue;
4211 case 3:
4212 /* Here we make use of the fact that there are no
4213 reverse match 3 operand instructions, and all 3
4214 operand instructions only need to be checked for
4215 register consistency between operands 2 and 3. */
40fb9820 4216 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4217 || (check_register
4218 && !operand_type_register_match (overlap1,
4219 i.types[1],
4220 operand_types[1],
4221 overlap2,
4222 i.types[2],
4223 operand_types[2])))
f48ff2ae
L		 4224 continue;
4225 break;
4226 }
29b0f896 4227 }
f48ff2ae 4228 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4229 slip through to break. */
4230 }
3629bb00 4231 if (!found_cpu_match)
29b0f896
AM		 4232 {
4233 found_reverse_match = 0;
4234 continue;
4235 }
c0f3af97 4236
6c30d220
L		 4237 /* Check if vector operands are valid. */
4238 if (check_VecOperands (t))
4239 continue;
4240
a683cc34
SP		 4241 /* Check if VEX operands are valid. */
4242 if (VEX_check_operands (t))
4243 continue;
4244
29b0f896
AM		 4245 /* We've found a match; break out of loop. */
4246 break;
4247 }
4248
4249 if (t == current_templates->end)
4250 {
4251 /* We found no match. */
a65babc9
L		 4252 const char *err_msg;
4253 switch (i.error)
4254 {
4255 default:
4256 abort ();
86e026a4 4257 case operand_size_mismatch:
a65babc9
L		 4258 err_msg = _("operand size mismatch");
4259 break;
4260 case operand_type_mismatch:
4261 err_msg = _("operand type mismatch");
4262 break;
4263 case register_type_mismatch:
4264 err_msg = _("register type mismatch");
4265 break;
4266 case number_of_operands_mismatch:
4267 err_msg = _("number of operands mismatch");
4268 break;
4269 case invalid_instruction_suffix:
4270 err_msg = _("invalid instruction suffix");
4271 break;
4272 case bad_imm4:
4273 err_msg = _("Imm4 isn't the first operand");
4274 break;
4275 case old_gcc_only:
4276 err_msg = _("only supported with old gcc");
4277 break;
4278 case unsupported_with_intel_mnemonic:
4279 err_msg = _("unsupported with Intel mnemonic");
4280 break;
4281 case unsupported_syntax:
4282 err_msg = _("unsupported syntax");
4283 break;
4284 case unsupported:
4285 err_msg = _("unsupported");
4286 break;
6c30d220
L		 4287 case invalid_vsib_address:
4288 err_msg = _("invalid VSIB address");
4289 break;
4290 case unsupported_vector_index_register:
4291 err_msg = _("unsupported vector index register");
4292 break;
a65babc9
L		 4293 }
4294 as_bad (_("%s for `%s'"), err_msg,
891edac4 4295 current_templates->start->name);
fa99fab2 4296 return NULL;
29b0f896 4297 }
252b5132 4298
29b0f896
AM		 4299 if (!quiet_warnings)
4300 {
4301 if (!intel_syntax
40fb9820
L		 4302 && (i.types[0].bitfield.jumpabsolute
4303 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4304 {
4305 as_warn (_("indirect %s without `*'"), t->name);
4306 }
4307
40fb9820
L		 4308 if (t->opcode_modifier.isprefix
4309 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4310 {
4311 /* Warn them that a data or address size prefix doesn't
4312 affect assembly of the next line of code. */
4313 as_warn (_("stand-alone `%s' prefix"), t->name);
4314 }
4315 }
4316
4317 /* Copy the template we found. */
4318 i.tm = *t;
539e75ad
L		 4319
4320 if (addr_prefix_disp != -1)
4321 i.tm.operand_types[addr_prefix_disp]
4322 = operand_types[addr_prefix_disp];
4323
29b0f896
AM		 4324 if (found_reverse_match)
4325 {
4326 /* If we found a reverse match we must alter the opcode
4327 direction bit. found_reverse_match holds bits to change
4328 (different for int & float insns). */
4329
4330 i.tm.base_opcode ^= found_reverse_match;
4331
539e75ad
L		 4332 i.tm.operand_types[0] = operand_types[1];
4333 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4334 }
4335
fa99fab2 4336 return t;
29b0f896
AM		 4337}
4338
4339static int
e3bb37b5 4340check_string (void)
29b0f896 4341{
40fb9820
L		 4342 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4343 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4344 {
4345 if (i.seg[0] != NULL && i.seg[0] != &es)
4346 {
a87af027 4347 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4348 i.tm.name,
a87af027
JB		 4349 mem_op + 1,
4350 register_prefix);
29b0f896
AM		 4351 return 0;
4352 }
4353 /* There's only ever one segment override allowed per instruction.
4354 This instruction possibly has a legal segment override on the
4355 second operand, so copy the segment to where non-string
4356 instructions store it, allowing common code. */
4357 i.seg[0] = i.seg[1];
4358 }
40fb9820 4359 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4360 {
4361 if (i.seg[1] != NULL && i.seg[1] != &es)
4362 {
a87af027 4363 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4364 i.tm.name,
a87af027
JB		 4365 mem_op + 2,
4366 register_prefix);
29b0f896
AM		 4367 return 0;
4368 }
4369 }
4370 return 1;
4371}
4372
4373static int
543613e9 4374process_suffix (void)
29b0f896
AM		 4375{
4376 /* If matched instruction specifies an explicit instruction mnemonic
4377 suffix, use it. */
40fb9820
L		 4378 if (i.tm.opcode_modifier.size16)
4379 i.suffix = WORD_MNEM_SUFFIX;
4380 else if (i.tm.opcode_modifier.size32)
4381 i.suffix = LONG_MNEM_SUFFIX;
4382 else if (i.tm.opcode_modifier.size64)
4383 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4384 else if (i.reg_operands)
4385 {
4386 /* If there's no instruction mnemonic suffix we try to invent one
4387 based on register operands. */
4388 if (!i.suffix)
4389 {
4390 /* We take i.suffix from the last register operand specified,
4391 Destination register type is more significant than source
381d071f
L		 4392 register type. crc32 in SSE4.2 prefers source register
4393 type. */
4394 if (i.tm.base_opcode == 0xf20f38f1)
4395 {
40fb9820
L		 4396 if (i.types[0].bitfield.reg16)
4397 i.suffix = WORD_MNEM_SUFFIX;
4398 else if (i.types[0].bitfield.reg32)
4399 i.suffix = LONG_MNEM_SUFFIX;
4400 else if (i.types[0].bitfield.reg64)
4401 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4402 }
9344ff29 4403 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4404 {
40fb9820 4405 if (i.types[0].bitfield.reg8)
20592a94
L		 4406 i.suffix = BYTE_MNEM_SUFFIX;
4407 }
381d071f
L		 4408
4409 if (!i.suffix)
4410 {
4411 int op;
4412
20592a94
L		 4413 if (i.tm.base_opcode == 0xf20f38f1
4414 || i.tm.base_opcode == 0xf20f38f0)
4415 {
4416 /* We have to know the operand size for crc32. */
4417 as_bad (_("ambiguous memory operand size for `%s`"),
4418 i.tm.name);
4419 return 0;
4420 }
4421
381d071f 4422 for (op = i.operands; --op >= 0;)
40fb9820 4423 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4424 {
40fb9820
L		 4425 if (i.types[op].bitfield.reg8)
4426 {
4427 i.suffix = BYTE_MNEM_SUFFIX;
4428 break;
4429 }
4430 else if (i.types[op].bitfield.reg16)
4431 {
4432 i.suffix = WORD_MNEM_SUFFIX;
4433 break;
4434 }
4435 else if (i.types[op].bitfield.reg32)
4436 {
4437 i.suffix = LONG_MNEM_SUFFIX;
4438 break;
4439 }
4440 else if (i.types[op].bitfield.reg64)
4441 {
4442 i.suffix = QWORD_MNEM_SUFFIX;
4443 break;
4444 }
381d071f
L		 4445 }
4446 }
29b0f896
AM		 4447 }
4448 else if (i.suffix == BYTE_MNEM_SUFFIX)
4449 {
2eb952a4
L		 4450 if (intel_syntax
4451 && i.tm.opcode_modifier.ignoresize
4452 && i.tm.opcode_modifier.no_bsuf)
4453 i.suffix = 0;
4454 else if (!check_byte_reg ())
29b0f896
AM		 4455 return 0;
4456 }
4457 else if (i.suffix == LONG_MNEM_SUFFIX)
4458 {
2eb952a4
L		 4459 if (intel_syntax
4460 && i.tm.opcode_modifier.ignoresize
4461 && i.tm.opcode_modifier.no_lsuf)
4462 i.suffix = 0;
4463 else if (!check_long_reg ())
29b0f896
AM		 4464 return 0;
4465 }
4466 else if (i.suffix == QWORD_MNEM_SUFFIX)
4467 {
955e1e6a
L		 4468 if (intel_syntax
4469 && i.tm.opcode_modifier.ignoresize
4470 && i.tm.opcode_modifier.no_qsuf)
4471 i.suffix = 0;
4472 else if (!check_qword_reg ())
29b0f896
AM		 4473 return 0;
4474 }
4475 else if (i.suffix == WORD_MNEM_SUFFIX)
4476 {
2eb952a4
L		 4477 if (intel_syntax
4478 && i.tm.opcode_modifier.ignoresize
4479 && i.tm.opcode_modifier.no_wsuf)
4480 i.suffix = 0;
4481 else if (!check_word_reg ())
29b0f896
AM		 4482 return 0;
4483 }
c0f3af97
L		 4484 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4485 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4486 {
c0f3af97 4487 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4488 should check if it is a valid suffix. */
4489 }
40fb9820 4490 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4491 /* Do nothing if the instruction is going to ignore the prefix. */
4492 ;
4493 else
4494 abort ();
4495 }
40fb9820 4496 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4497 && !i.suffix
4498 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4499 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4500 {
4501 i.suffix = stackop_size;
4502 }
9306ca4a
JB		 4503 else if (intel_syntax
4504 && !i.suffix
40fb9820
L		 4505 && (i.tm.operand_types[0].bitfield.jumpabsolute
4506 || i.tm.opcode_modifier.jumpbyte
4507 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4508 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4509 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4510 {
4511 switch (flag_code)
4512 {
4513 case CODE_64BIT:
40fb9820 4514 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4515 {
4516 i.suffix = QWORD_MNEM_SUFFIX;
4517 break;
4518 }
4519 case CODE_32BIT:
40fb9820 4520 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4521 i.suffix = LONG_MNEM_SUFFIX;
4522 break;
4523 case CODE_16BIT:
40fb9820 4524 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4525 i.suffix = WORD_MNEM_SUFFIX;
4526 break;
4527 }
4528 }
252b5132 4529
9306ca4a 4530 if (!i.suffix)
29b0f896 4531 {
9306ca4a
JB		 4532 if (!intel_syntax)
4533 {
40fb9820 4534 if (i.tm.opcode_modifier.w)
9306ca4a 4535 {
4eed87de
AM		 4536 as_bad (_("no instruction mnemonic suffix given and "
4537 "no register operands; can't size instruction"));
9306ca4a
JB		 4538 return 0;
4539 }
4540 }
4541 else
4542 {
40fb9820 4543 unsigned int suffixes;
7ab9ffdd 4544
40fb9820
L		 4545 suffixes = !i.tm.opcode_modifier.no_bsuf;
4546 if (!i.tm.opcode_modifier.no_wsuf)
4547 suffixes |= 1 << 1;
4548 if (!i.tm.opcode_modifier.no_lsuf)
4549 suffixes |= 1 << 2;
fc4adea1 4550 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4551 suffixes |= 1 << 3;
4552 if (!i.tm.opcode_modifier.no_ssuf)
4553 suffixes |= 1 << 4;
4554 if (!i.tm.opcode_modifier.no_qsuf)
4555 suffixes |= 1 << 5;
4556
4557 /* There are more than suffix matches. */
4558 if (i.tm.opcode_modifier.w
9306ca4a 4559 || ((suffixes & (suffixes - 1))
40fb9820
L		 4560 && !i.tm.opcode_modifier.defaultsize
4561 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4562 {
4563 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4564 return 0;
4565 }
4566 }
29b0f896 4567 }
252b5132 4568
9306ca4a
JB		 4569 /* Change the opcode based on the operand size given by i.suffix;
4570 We don't need to change things for byte insns. */
4571
582d5edd
L		 4572 if (i.suffix
4573 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4574 && i.suffix != XMMWORD_MNEM_SUFFIX
4575 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4576 {
4577 /* It's not a byte, select word/dword operation. */
40fb9820 4578 if (i.tm.opcode_modifier.w)
29b0f896 4579 {
40fb9820 4580 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4581 i.tm.base_opcode |= 8;
4582 else
4583 i.tm.base_opcode |= 1;
4584 }
0f3f3d8b 4585
29b0f896
AM		 4586 /* Now select between word & dword operations via the operand
4587 size prefix, except for instructions that will ignore this
4588 prefix anyway. */
ca61edf2 4589 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4590 {
ca61edf2
L		 4591 /* The address size override prefix changes the size of the
4592 first operand. */
40fb9820
L		 4593 if ((flag_code == CODE_32BIT
4594 && i.op->regs[0].reg_type.bitfield.reg16)
4595 || (flag_code != CODE_32BIT
4596 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4597 if (!add_prefix (ADDR_PREFIX_OPCODE))
4598 return 0;
4599 }
4600 else if (i.suffix != QWORD_MNEM_SUFFIX
4601 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4602 && !i.tm.opcode_modifier.ignoresize
4603 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4604 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4605 || (flag_code == CODE_64BIT
40fb9820 4606 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4607 {
4608 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4609
40fb9820 4610 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4611 prefix = ADDR_PREFIX_OPCODE;
252b5132 4612
29b0f896
AM		 4613 if (!add_prefix (prefix))
4614 return 0;
24eab124 4615 }
252b5132 4616
29b0f896
AM		 4617 /* Set mode64 for an operand. */
4618 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4619 && flag_code == CODE_64BIT
40fb9820 4620 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4621 {
4622 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4623 need rex64. cmpxchg8b is also a special case. */
4624 if (! (i.operands == 2
4625 && i.tm.base_opcode == 0x90
4626 && i.tm.extension_opcode == None
0dfbf9d7
L		 4627 && operand_type_equal (&i.types [0], &acc64)
4628 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4629 && ! (i.operands == 1
4630 && i.tm.base_opcode == 0xfc7
4631 && i.tm.extension_opcode == 1
40fb9820
L		 4632 && !operand_type_check (i.types [0], reg)
4633 && operand_type_check (i.types [0], anymem)))
f6bee062 4634 i.rex |= REX_W;
46e883c5 4635 }
3e73aa7c 4636
29b0f896
AM		 4637 /* Size floating point instruction. */
4638 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4639 if (i.tm.opcode_modifier.floatmf)
543613e9 4640 i.tm.base_opcode ^= 4;
29b0f896 4641 }
7ecd2f8b 4642
29b0f896
AM		 4643 return 1;
4644}
3e73aa7c 4645
29b0f896 4646static int
543613e9 4647check_byte_reg (void)
29b0f896
AM		 4648{
4649 int op;
543613e9 4650
29b0f896
AM		 4651 for (op = i.operands; --op >= 0;)
4652 {
4653 /* If this is an eight bit register, it's OK. If it's the 16 or
4654 32 bit version of an eight bit register, we will just use the
4655 low portion, and that's OK too. */
40fb9820 4656 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4657 continue;
4658
9344ff29
L		 4659 /* crc32 doesn't generate this warning. */
4660 if (i.tm.base_opcode == 0xf20f38f0)
4661 continue;
4662
40fb9820
L		 4663 if ((i.types[op].bitfield.reg16
4664 || i.types[op].bitfield.reg32
4665 || i.types[op].bitfield.reg64)
4666 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4667 {
4668 /* Prohibit these changes in the 64bit mode, since the
4669 lowering is more complicated. */
4670 if (flag_code == CODE_64BIT
40fb9820 4671 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4672 {
2b5d6a91 4673 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4674 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4675 i.suffix);
4676 return 0;
4677 }
4678#if REGISTER_WARNINGS
4679 if (!quiet_warnings
40fb9820 4680 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4681 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4682 register_prefix,
40fb9820 4683 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4684 ? REGNAM_AL - REGNAM_AX
4685 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4686 register_prefix,
29b0f896
AM		 4687 i.op[op].regs->reg_name,
4688 i.suffix);
4689#endif
4690 continue;
4691 }
4692 /* Any other register is bad. */
40fb9820
L		 4693 if (i.types[op].bitfield.reg16
4694 || i.types[op].bitfield.reg32
4695 || i.types[op].bitfield.reg64
4696 || i.types[op].bitfield.regmmx
4697 || i.types[op].bitfield.regxmm
c0f3af97 4698 || i.types[op].bitfield.regymm
40fb9820
L		 4699 || i.types[op].bitfield.sreg2
4700 || i.types[op].bitfield.sreg3
4701 || i.types[op].bitfield.control
4702 || i.types[op].bitfield.debug
4703 || i.types[op].bitfield.test
4704 || i.types[op].bitfield.floatreg
4705 || i.types[op].bitfield.floatacc)
29b0f896 4706 {
a540244d
L		 4707 as_bad (_("`%s%s' not allowed with `%s%c'"),
4708 register_prefix,
29b0f896
AM		 4709 i.op[op].regs->reg_name,
4710 i.tm.name,
4711 i.suffix);
4712 return 0;
4713 }
4714 }
4715 return 1;
4716}
4717
4718static int
e3bb37b5 4719check_long_reg (void)
29b0f896
AM		 4720{
4721 int op;
4722
4723 for (op = i.operands; --op >= 0;)
4724 /* Reject eight bit registers, except where the template requires
4725 them. (eg. movzb) */
40fb9820
L		 4726 if (i.types[op].bitfield.reg8
4727 && (i.tm.operand_types[op].bitfield.reg16
4728 || i.tm.operand_types[op].bitfield.reg32
4729 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4730 {
a540244d
L		 4731 as_bad (_("`%s%s' not allowed with `%s%c'"),
4732 register_prefix,
29b0f896
AM		 4733 i.op[op].regs->reg_name,
4734 i.tm.name,
4735 i.suffix);
4736 return 0;
4737 }
4738 /* Warn if the e prefix on a general reg is missing. */
4739 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4740 && i.types[op].bitfield.reg16
4741 && (i.tm.operand_types[op].bitfield.reg32
4742 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4743 {
4744 /* Prohibit these changes in the 64bit mode, since the
4745 lowering is more complicated. */
4746 if (flag_code == CODE_64BIT)
252b5132 4747 {
2b5d6a91 4748 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4749 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4750 i.suffix);
4751 return 0;
252b5132 4752 }
29b0f896
AM		 4753#if REGISTER_WARNINGS
4754 else
a540244d
L		 4755 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4756 register_prefix,
29b0f896 4757 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4758 register_prefix,
29b0f896
AM		 4759 i.op[op].regs->reg_name,
4760 i.suffix);
4761#endif
252b5132 4762 }
29b0f896 4763 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4764 else if (i.types[op].bitfield.reg64
4765 && (i.tm.operand_types[op].bitfield.reg32
4766 || i.tm.operand_types[op].bitfield.acc))
252b5132 4767 {
34828aad 4768 if (intel_syntax
ca61edf2 4769 && i.tm.opcode_modifier.toqword
40fb9820 4770 && !i.types[0].bitfield.regxmm)
34828aad 4771 {
ca61edf2 4772 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4773 i.suffix = QWORD_MNEM_SUFFIX;
4774 }
4775 else
4776 {
2b5d6a91 4777 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4778 register_prefix, i.op[op].regs->reg_name,
4779 i.suffix);
4780 return 0;
4781 }
29b0f896
AM		 4782 }
4783 return 1;
4784}
252b5132 4785
29b0f896 4786static int
e3bb37b5 4787check_qword_reg (void)
29b0f896
AM		 4788{
4789 int op;
252b5132 4790
29b0f896
AM		 4791 for (op = i.operands; --op >= 0; )
4792 /* Reject eight bit registers, except where the template requires
4793 them. (eg. movzb) */
40fb9820
L		 4794 if (i.types[op].bitfield.reg8
4795 && (i.tm.operand_types[op].bitfield.reg16
4796 || i.tm.operand_types[op].bitfield.reg32
4797 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4798 {
a540244d
L		 4799 as_bad (_("`%s%s' not allowed with `%s%c'"),
4800 register_prefix,
29b0f896
AM		 4801 i.op[op].regs->reg_name,
4802 i.tm.name,
4803 i.suffix);
4804 return 0;
4805 }
4806 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4807 else if ((i.types[op].bitfield.reg16
4808 || i.types[op].bitfield.reg32)
4809 && (i.tm.operand_types[op].bitfield.reg32
4810 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4811 {
4812 /* Prohibit these changes in the 64bit mode, since the
4813 lowering is more complicated. */
34828aad 4814 if (intel_syntax
ca61edf2 4815 && i.tm.opcode_modifier.todword
40fb9820 4816 && !i.types[0].bitfield.regxmm)
34828aad 4817 {
ca61edf2 4818 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4819 i.suffix = LONG_MNEM_SUFFIX;
4820 }
4821 else
4822 {
2b5d6a91 4823 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4824 register_prefix, i.op[op].regs->reg_name,
4825 i.suffix);
4826 return 0;
4827 }
252b5132 4828 }
29b0f896
AM		 4829 return 1;
4830}
252b5132 4831
29b0f896 4832static int
e3bb37b5 4833check_word_reg (void)
29b0f896
AM		 4834{
4835 int op;
4836 for (op = i.operands; --op >= 0;)
4837 /* Reject eight bit registers, except where the template requires
4838 them. (eg. movzb) */
40fb9820
L		 4839 if (i.types[op].bitfield.reg8
4840 && (i.tm.operand_types[op].bitfield.reg16
4841 || i.tm.operand_types[op].bitfield.reg32
4842 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4843 {
a540244d
L		 4844 as_bad (_("`%s%s' not allowed with `%s%c'"),
4845 register_prefix,
29b0f896
AM		 4846 i.op[op].regs->reg_name,
4847 i.tm.name,
4848 i.suffix);
4849 return 0;
4850 }
4851 /* Warn if the e prefix on a general reg is present. */
4852 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4853 && i.types[op].bitfield.reg32
4854 && (i.tm.operand_types[op].bitfield.reg16
4855 || i.tm.operand_types[op].bitfield.acc))
252b5132 4856 {
29b0f896
AM		 4857 /* Prohibit these changes in the 64bit mode, since the
4858 lowering is more complicated. */
4859 if (flag_code == CODE_64BIT)
252b5132 4860 {
2b5d6a91 4861 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4862 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4863 i.suffix);
4864 return 0;
252b5132 4865 }
29b0f896
AM		 4866 else
4867#if REGISTER_WARNINGS
a540244d
L		 4868 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4869 register_prefix,
29b0f896 4870 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4871 register_prefix,
29b0f896
AM		 4872 i.op[op].regs->reg_name,
4873 i.suffix);
4874#endif
4875 }
4876 return 1;
4877}
252b5132 4878
29b0f896 4879static int
40fb9820 4880update_imm (unsigned int j)
29b0f896 4881{
bc0844ae 4882 i386_operand_type overlap = i.types[j];
40fb9820
L		 4883 if ((overlap.bitfield.imm8
4884 || overlap.bitfield.imm8s
4885 || overlap.bitfield.imm16
4886 || overlap.bitfield.imm32
4887 || overlap.bitfield.imm32s
4888 || overlap.bitfield.imm64)
0dfbf9d7
L		 4889 && !operand_type_equal (&overlap, &imm8)
4890 && !operand_type_equal (&overlap, &imm8s)
4891 && !operand_type_equal (&overlap, &imm16)
4892 && !operand_type_equal (&overlap, &imm32)
4893 && !operand_type_equal (&overlap, &imm32s)
4894 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4895 {
4896 if (i.suffix)
4897 {
40fb9820
L		 4898 i386_operand_type temp;
4899
0dfbf9d7 4900 operand_type_set (&temp, 0);
7ab9ffdd 4901 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4902 {
4903 temp.bitfield.imm8 = overlap.bitfield.imm8;
4904 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4905 }
4906 else if (i.suffix == WORD_MNEM_SUFFIX)
4907 temp.bitfield.imm16 = overlap.bitfield.imm16;
4908 else if (i.suffix == QWORD_MNEM_SUFFIX)
4909 {
4910 temp.bitfield.imm64 = overlap.bitfield.imm64;
4911 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4912 }
4913 else
4914 temp.bitfield.imm32 = overlap.bitfield.imm32;
4915 overlap = temp;
29b0f896 4916 }
0dfbf9d7
L		 4917 else if (operand_type_equal (&overlap, &imm16_32_32s)
4918 || operand_type_equal (&overlap, &imm16_32)
4919 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4920 {
40fb9820 4921 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4922 overlap = imm16;
40fb9820 4923 else
65da13b5 4924 overlap = imm32s;
29b0f896 4925 }
0dfbf9d7
L		 4926 if (!operand_type_equal (&overlap, &imm8)
4927 && !operand_type_equal (&overlap, &imm8s)
4928 && !operand_type_equal (&overlap, &imm16)
4929 && !operand_type_equal (&overlap, &imm32)
4930 && !operand_type_equal (&overlap, &imm32s)
4931 && !operand_type_equal (&overlap, &imm64))
29b0f896 4932 {
4eed87de
AM		 4933 as_bad (_("no instruction mnemonic suffix given; "
4934 "can't determine immediate size"));
29b0f896
AM		 4935 return 0;
4936 }
4937 }
40fb9820 4938 i.types[j] = overlap;
29b0f896 4939
40fb9820
L		 4940 return 1;
4941}
4942
4943static int
4944finalize_imm (void)
4945{
bc0844ae 4946 unsigned int j, n;
29b0f896 4947
bc0844ae
L		 4948 /* Update the first 2 immediate operands. */
4949 n = i.operands > 2 ? 2 : i.operands;
4950 if (n)
4951 {
4952 for (j = 0; j < n; j++)
4953 if (update_imm (j) == 0)
4954 return 0;
40fb9820 4955
bc0844ae
L		 4956 /* The 3rd operand can't be immediate operand. */
4957 gas_assert (operand_type_check (i.types[2], imm) == 0);
4958 }
29b0f896
AM		 4959
4960 return 1;
4961}
4962
c0f3af97
L		 4963static int
4964bad_implicit_operand (int xmm)
4965{
91d6fa6a
NC		 4966 const char *ireg = xmm ? "xmm0" : "ymm0";
4967
c0f3af97
L		 4968 if (intel_syntax)
4969 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4970 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4971 else
4972 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4973 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4974 return 0;
4975}
4976
29b0f896 4977static int
e3bb37b5 4978process_operands (void)
29b0f896
AM		 4979{
4980 /* Default segment register this instruction will use for memory
4981 accesses. 0 means unknown. This is only for optimizing out
4982 unnecessary segment overrides. */
4983 const seg_entry *default_seg = 0;
4984
2426c15f 4985 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4986 {
91d6fa6a
NC		 4987 unsigned int dupl = i.operands;
4988 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4989 unsigned int j;
4990
c0f3af97 4991 /* The destination must be an xmm register. */
9c2799c2 4992 gas_assert (i.reg_operands
91d6fa6a 4993 && MAX_OPERANDS > dupl
7ab9ffdd 4994 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4995
4996 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4997 {
c0f3af97 4998 /* The first operand is implicit and must be xmm0. */
9c2799c2 4999 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 5000 if (i.op[0].regs->reg_num != 0)
5001 return bad_implicit_operand (1);
5002
8cd7925b 5003 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5004 {
5005 /* Keep xmm0 for instructions with VEX prefix and 3
5006 sources. */
5007 goto duplicate;
5008 }
e2ec9d29 5009 else
c0f3af97
L		 5010 {
5011 /* We remove the first xmm0 and keep the number of
5012 operands unchanged, which in fact duplicates the
5013 destination. */
5014 for (j = 1; j < i.operands; j++)
5015 {
5016 i.op[j - 1] = i.op[j];
5017 i.types[j - 1] = i.types[j];
5018 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5019 }
5020 }
5021 }
5022 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5023 {
91d6fa6a 5024 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5025 && (i.tm.opcode_modifier.vexsources
5026 == VEX3SOURCES));
c0f3af97
L		 5027
5028 /* Add the implicit xmm0 for instructions with VEX prefix
5029 and 3 sources. */
5030 for (j = i.operands; j > 0; j--)
5031 {
5032 i.op[j] = i.op[j - 1];
5033 i.types[j] = i.types[j - 1];
5034 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5035 }
5036 i.op[0].regs
5037 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5038 i.types[0] = regxmm;
c0f3af97
L		 5039 i.tm.operand_types[0] = regxmm;
5040
5041 i.operands += 2;
5042 i.reg_operands += 2;
5043 i.tm.operands += 2;
5044
91d6fa6a 5045 dupl++;
c0f3af97 5046 dest++;
91d6fa6a
NC		 5047 i.op[dupl] = i.op[dest];
5048 i.types[dupl] = i.types[dest];
5049 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5050 }
c0f3af97
L		 5051 else
5052 {
5053duplicate:
5054 i.operands++;
5055 i.reg_operands++;
5056 i.tm.operands++;
5057
91d6fa6a
NC		 5058 i.op[dupl] = i.op[dest];
5059 i.types[dupl] = i.types[dest];
5060 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5061 }
5062
5063 if (i.tm.opcode_modifier.immext)
5064 process_immext ();
5065 }
5066 else if (i.tm.opcode_modifier.firstxmm0)
5067 {
5068 unsigned int j;
5069
5070 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 5071 gas_assert (i.reg_operands
7ab9ffdd
L		 5072 && (operand_type_equal (&i.types[0], &regxmm)
5073 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 5074 if (i.op[0].regs->reg_num != 0)
5075 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5076
5077 for (j = 1; j < i.operands; j++)
5078 {
5079 i.op[j - 1] = i.op[j];
5080 i.types[j - 1] = i.types[j];
5081
5082 /* We need to adjust fields in i.tm since they are used by
5083 build_modrm_byte. */
5084 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5085 }
5086
e2ec9d29
L		 5087 i.operands--;
5088 i.reg_operands--;
e2ec9d29
L		 5089 i.tm.operands--;
5090 }
5091 else if (i.tm.opcode_modifier.regkludge)
5092 {
5093 /* The imul $imm, %reg instruction is converted into
5094 imul $imm, %reg, %reg, and the clr %reg instruction
5095 is converted into xor %reg, %reg. */
5096
5097 unsigned int first_reg_op;
5098
5099 if (operand_type_check (i.types[0], reg))
5100 first_reg_op = 0;
5101 else
5102 first_reg_op = 1;
5103 /* Pretend we saw the extra register operand. */
9c2799c2 5104 gas_assert (i.reg_operands == 1
7ab9ffdd 5105 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5106 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5107 i.types[first_reg_op + 1] = i.types[first_reg_op];
5108 i.operands++;
5109 i.reg_operands++;
29b0f896
AM		 5110 }
5111
40fb9820 5112 if (i.tm.opcode_modifier.shortform)
29b0f896 5113 {
40fb9820
L		 5114 if (i.types[0].bitfield.sreg2
5115 || i.types[0].bitfield.sreg3)
29b0f896 5116 {
4eed87de
AM		 5117 if (i.tm.base_opcode == POP_SEG_SHORT
5118 && i.op[0].regs->reg_num == 1)
29b0f896 5119 {
a87af027 5120 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5121 return 0;
29b0f896 5122 }
4eed87de
AM		 5123 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5124 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5125 i.rex |= REX_B;
4eed87de
AM		 5126 }
5127 else
5128 {
7ab9ffdd 5129 /* The register or float register operand is in operand
85f10a01 5130 0 or 1. */
40fb9820 5131 unsigned int op;
7ab9ffdd
L		 5132
5133 if (i.types[0].bitfield.floatreg
5134 || operand_type_check (i.types[0], reg))
5135 op = 0;
5136 else
5137 op = 1;
4eed87de
AM		 5138 /* Register goes in low 3 bits of opcode. */
5139 i.tm.base_opcode |= i.op[op].regs->reg_num;
5140 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5141 i.rex |= REX_B;
40fb9820 5142 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5143 {
4eed87de
AM		 5144 /* Warn about some common errors, but press on regardless.
5145 The first case can be generated by gcc (<= 2.8.1). */
5146 if (i.operands == 2)
5147 {
5148 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5149 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5150 register_prefix, i.op[!intel_syntax].regs->reg_name,
5151 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5152 }
5153 else
5154 {
5155 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5156 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5157 register_prefix, i.op[0].regs->reg_name);
4eed87de 5158 }
29b0f896
AM		 5159 }
5160 }
5161 }
40fb9820 5162 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5163 {
5164 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5165 must be put into the modrm byte). Now, we make the modrm and
5166 index base bytes based on all the info we've collected. */
29b0f896
AM		 5167
5168 default_seg = build_modrm_byte ();
5169 }
8a2ed489 5170 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5171 {
5172 default_seg = &ds;
5173 }
40fb9820 5174 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5175 {
5176 /* For the string instructions that allow a segment override
5177 on one of their operands, the default segment is ds. */
5178 default_seg = &ds;
5179 }
5180
75178d9d
L		 5181 if (i.tm.base_opcode == 0x8d /* lea */
5182 && i.seg[0]
5183 && !quiet_warnings)
30123838 5184 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5185
5186 /* If a segment was explicitly specified, and the specified segment
5187 is not the default, use an opcode prefix to select it. If we
5188 never figured out what the default segment is, then default_seg
5189 will be zero at this point, and the specified segment prefix will
5190 always be used. */
29b0f896
AM		 5191 if ((i.seg[0]) && (i.seg[0] != default_seg))
5192 {
5193 if (!add_prefix (i.seg[0]->seg_prefix))
5194 return 0;
5195 }
5196 return 1;
5197}
5198
5199static const seg_entry *
e3bb37b5 5200build_modrm_byte (void)
29b0f896
AM		 5201{
5202 const seg_entry *default_seg = 0;
c0f3af97 5203 unsigned int source, dest;
8cd7925b 5204 int vex_3_sources;
c0f3af97
L		 5205
5206 /* The first operand of instructions with VEX prefix and 3 sources
5207 must be VEX_Imm4. */
8cd7925b 5208 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5209 if (vex_3_sources)
5210 {
91d6fa6a 5211 unsigned int nds, reg_slot;
4c2c6516 5212 expressionS *exp;
c0f3af97 5213
922d8de8 5214 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5215 && i.tm.opcode_modifier.immext)
5216 {
5217 dest = i.operands - 2;
5218 gas_assert (dest == 3);
5219 }
922d8de8 5220 else
a683cc34 5221 dest = i.operands - 1;
c0f3af97 5222 nds = dest - 1;
922d8de8 5223
a683cc34
SP		 5224 /* There are 2 kinds of instructions:
5225 1. 5 operands: 4 register operands or 3 register operands
5226 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5227 VexW0 or VexW1. The destination must be either XMM or YMM
5228 register.
5229 2. 4 operands: 4 register operands or 3 register operands
5230 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5231 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5232 || (i.reg_operands == 3 && i.mem_operands == 1))
5233 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5234 && (i.tm.opcode_modifier.veximmext
5235 || (i.imm_operands == 1
5236 && i.types[0].bitfield.vec_imm4
5237 && (i.tm.opcode_modifier.vexw == VEXW0
5238 || i.tm.opcode_modifier.vexw == VEXW1)
5239 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5240 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5241
5242 if (i.imm_operands == 0)
5243 {
5244 /* When there is no immediate operand, generate an 8bit
5245 immediate operand to encode the first operand. */
5246 exp = &im_expressions[i.imm_operands++];
5247 i.op[i.operands].imms = exp;
5248 i.types[i.operands] = imm8;
5249 i.operands++;
5250 /* If VexW1 is set, the first operand is the source and
5251 the second operand is encoded in the immediate operand. */
5252 if (i.tm.opcode_modifier.vexw == VEXW1)
5253 {
5254 source = 0;
5255 reg_slot = 1;
5256 }
5257 else
5258 {
5259 source = 1;
5260 reg_slot = 0;
5261 }
5262
5263 /* FMA swaps REG and NDS. */
5264 if (i.tm.cpu_flags.bitfield.cpufma)
5265 {
5266 unsigned int tmp;
5267 tmp = reg_slot;
5268 reg_slot = nds;
5269 nds = tmp;
5270 }
5271
24981e7b
L		 5272 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5273 &regxmm)
a683cc34
SP		 5274 || operand_type_equal (&i.tm.operand_types[reg_slot],
5275 &regymm));
5276 exp->X_op = O_constant;
5277 exp->X_add_number
5278 = ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5279 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5280 << 4);
a683cc34 5281 }
922d8de8 5282 else
a683cc34
SP		 5283 {
5284 unsigned int imm_slot;
5285
5286 if (i.tm.opcode_modifier.vexw == VEXW0)
5287 {
5288 /* If VexW0 is set, the third operand is the source and
5289 the second operand is encoded in the immediate
5290 operand. */
5291 source = 2;
5292 reg_slot = 1;
5293 }
5294 else
5295 {
5296 /* VexW1 is set, the second operand is the source and
5297 the third operand is encoded in the immediate
5298 operand. */
5299 source = 1;
5300 reg_slot = 2;
5301 }
5302
5303 if (i.tm.opcode_modifier.immext)
5304 {
5305 /* When ImmExt is set, the immdiate byte is the last
5306 operand. */
5307 imm_slot = i.operands - 1;
5308 source--;
5309 reg_slot--;
5310 }
5311 else
5312 {
5313 imm_slot = 0;
5314
5315 /* Turn on Imm8 so that output_imm will generate it. */
5316 i.types[imm_slot].bitfield.imm8 = 1;
5317 }
5318
24981e7b
L		 5319 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5320 &regxmm)
5321 || operand_type_equal (&i.tm.operand_types[reg_slot],
5322 &regymm));
a683cc34
SP		 5323 i.op[imm_slot].imms->X_add_number
5324 |= ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5325 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5326 << 4);
a683cc34
SP		 5327 }
5328
5329 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5330 || operand_type_equal (&i.tm.operand_types[nds],
5331 &regymm));
dae39acc 5332 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5333 }
5334 else
5335 source = dest = 0;
29b0f896
AM		 5336
5337 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5338 implicit registers do not count. If there are 3 register
5339 operands, it must be a instruction with VexNDS. For a
5340 instruction with VexNDD, the destination register is encoded
5341 in VEX prefix. If there are 4 register operands, it must be
5342 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5343 if (i.mem_operands == 0
5344 && ((i.reg_operands == 2
2426c15f 5345 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5346 || (i.reg_operands == 3
2426c15f 5347 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5348 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5349 {
cab737b9
L		 5350 switch (i.operands)
5351 {
5352 case 2:
5353 source = 0;
5354 break;
5355 case 3:
c81128dc
L		 5356 /* When there are 3 operands, one of them may be immediate,
5357 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5358 the first operand must be shift count register (cl) or it
5359 is an instruction with VexNDS. */
9c2799c2 5360 gas_assert (i.imm_operands == 1
7ab9ffdd 5361 || (i.imm_operands == 0
2426c15f 5362 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5363 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5364 if (operand_type_check (i.types[0], imm)
5365 || i.types[0].bitfield.shiftcount)
5366 source = 1;
5367 else
5368 source = 0;
cab737b9
L		 5369 break;
5370 case 4:
368d64cc
L		 5371 /* When there are 4 operands, the first two must be 8bit
5372 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5373 one.
5374
5375 For instructions with VexNDS, if the first operand
5376 an imm8, the source operand is the 2nd one. If the last
5377 operand is imm8, the source operand is the first one. */
9c2799c2 5378 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5379 && i.types[0].bitfield.imm8
5380 && i.types[1].bitfield.imm8)
2426c15f 5381 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5382 && i.imm_operands == 1
5383 && (i.types[0].bitfield.imm8
5384 || i.types[i.operands - 1].bitfield.imm8)));
9f2670f2
L		 5385 if (i.imm_operands == 2)
5386 source = 2;
5387 else
c0f3af97
L		 5388 {
5389 if (i.types[0].bitfield.imm8)
5390 source = 1;
5391 else
5392 source = 0;
5393 }
c0f3af97
L		 5394 break;
5395 case 5:
cab737b9
L		 5396 break;
5397 default:
5398 abort ();
5399 }
5400
c0f3af97
L		 5401 if (!vex_3_sources)
5402 {
5403 dest = source + 1;
5404
2426c15f 5405 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5406 {
5407 /* For instructions with VexNDS, the register-only
f12dc422
L		 5408 source operand must be 32/64bit integer, XMM or
5409 YMM register. It is encoded in VEX prefix. We
5410 need to clear RegMem bit before calling
5411 operand_type_equal. */
5412
5413 i386_operand_type op;
5414 unsigned int vvvv;
5415
5416 /* Check register-only source operand when two source
5417 operands are swapped. */
5418 if (!i.tm.operand_types[source].bitfield.baseindex
5419 && i.tm.operand_types[dest].bitfield.baseindex)
5420 {
5421 vvvv = source;
5422 source = dest;
5423 }
5424 else
5425 vvvv = dest;
5426
5427 op = i.tm.operand_types[vvvv];
fa99fab2 5428 op.bitfield.regmem = 0;
c0f3af97 5429 if ((dest + 1) >= i.operands
f12dc422
L		 5430 || (op.bitfield.reg32 != 1
5431 && !op.bitfield.reg64 != 1
5432 && !operand_type_equal (&op, &regxmm)
fa99fab2 5433 && !operand_type_equal (&op, &regymm)))
c0f3af97 5434 abort ();
f12dc422 5435 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 5436 dest++;
5437 }
5438 }
29b0f896
AM		 5439
5440 i.rm.mode = 3;
5441 /* One of the register operands will be encoded in the i.tm.reg
5442 field, the other in the combined i.tm.mode and i.tm.regmem
5443 fields. If no form of this instruction supports a memory
5444 destination operand, then we assume the source operand may
5445 sometimes be a memory operand and so we need to store the
5446 destination in the i.rm.reg field. */
40fb9820
L		 5447 if (!i.tm.operand_types[dest].bitfield.regmem
5448 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5449 {
5450 i.rm.reg = i.op[dest].regs->reg_num;
5451 i.rm.regmem = i.op[source].regs->reg_num;
5452 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5453 i.rex |= REX_R;
29b0f896 5454 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5455 i.rex |= REX_B;
29b0f896
AM		 5456 }
5457 else
5458 {
5459 i.rm.reg = i.op[source].regs->reg_num;
5460 i.rm.regmem = i.op[dest].regs->reg_num;
5461 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5462 i.rex |= REX_B;
29b0f896 5463 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5464 i.rex |= REX_R;
29b0f896 5465 }
161a04f6 5466 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5467 {
40fb9820
L		 5468 if (!i.types[0].bitfield.control
5469 && !i.types[1].bitfield.control)
c4a530c5 5470 abort ();
161a04f6 5471 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5472 add_prefix (LOCK_PREFIX_OPCODE);
5473 }
29b0f896
AM		 5474 }
5475 else
5476 { /* If it's not 2 reg operands... */
c0f3af97
L		 5477 unsigned int mem;
5478
29b0f896
AM		 5479 if (i.mem_operands)
5480 {
5481 unsigned int fake_zero_displacement = 0;
99018f42 5482 unsigned int op;
4eed87de 5483
7ab9ffdd
L		 5484 for (op = 0; op < i.operands; op++)
5485 if (operand_type_check (i.types[op], anymem))
5486 break;
7ab9ffdd 5487 gas_assert (op < i.operands);
29b0f896 5488
6c30d220
L		 5489 if (i.tm.opcode_modifier.vecsib)
5490 {
5491 if (i.index_reg->reg_num == RegEiz
5492 || i.index_reg->reg_num == RegRiz)
5493 abort ();
5494
5495 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5496 if (!i.base_reg)
5497 {
5498 i.sib.base = NO_BASE_REGISTER;
5499 i.sib.scale = i.log2_scale_factor;
5500 i.types[op].bitfield.disp8 = 0;
5501 i.types[op].bitfield.disp16 = 0;
5502 i.types[op].bitfield.disp64 = 0;
5503 if (flag_code != CODE_64BIT)
5504 {
5505 /* Must be 32 bit */
5506 i.types[op].bitfield.disp32 = 1;
5507 i.types[op].bitfield.disp32s = 0;
5508 }
5509 else
5510 {
5511 i.types[op].bitfield.disp32 = 0;
5512 i.types[op].bitfield.disp32s = 1;
5513 }
5514 }
5515 i.sib.index = i.index_reg->reg_num;
5516 if ((i.index_reg->reg_flags & RegRex) != 0)
5517 i.rex |= REX_X;
5518 }
5519
29b0f896
AM		 5520 default_seg = &ds;
5521
5522 if (i.base_reg == 0)
5523 {
5524 i.rm.mode = 0;
5525 if (!i.disp_operands)
6c30d220
L		 5526 {
5527 fake_zero_displacement = 1;
5528 /* Instructions with VSIB byte need 32bit displacement
5529 if there is no base register. */
5530 if (i.tm.opcode_modifier.vecsib)
5531 i.types[op].bitfield.disp32 = 1;
5532 }
29b0f896
AM		 5533 if (i.index_reg == 0)
5534 {
6c30d220 5535 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5536 /* Operand is just <disp> */
20f0a1fc 5537 if (flag_code == CODE_64BIT)
29b0f896
AM		 5538 {
5539 /* 64bit mode overwrites the 32bit absolute
5540 addressing by RIP relative addressing and
5541 absolute addressing is encoded by one of the
5542 redundant SIB forms. */
5543 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5544 i.sib.base = NO_BASE_REGISTER;
5545 i.sib.index = NO_INDEX_REGISTER;
fc225355 5546 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5547 ? disp32s : disp32);
20f0a1fc 5548 }
fc225355
L		 5549 else if ((flag_code == CODE_16BIT)
5550 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5551 {
5552 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5553 i.types[op] = disp16;
20f0a1fc
NC		 5554 }
5555 else
5556 {
5557 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5558 i.types[op] = disp32;
29b0f896
AM		 5559 }
5560 }
6c30d220 5561 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5562 {
6c30d220 5563 /* !i.base_reg && i.index_reg */
db51cc60
L		 5564 if (i.index_reg->reg_num == RegEiz
5565 || i.index_reg->reg_num == RegRiz)
5566 i.sib.index = NO_INDEX_REGISTER;
5567 else
5568 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5569 i.sib.base = NO_BASE_REGISTER;
5570 i.sib.scale = i.log2_scale_factor;
5571 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5572 i.types[op].bitfield.disp8 = 0;
5573 i.types[op].bitfield.disp16 = 0;
5574 i.types[op].bitfield.disp64 = 0;
29b0f896 5575 if (flag_code != CODE_64BIT)
40fb9820
L		 5576 {
5577 /* Must be 32 bit */
5578 i.types[op].bitfield.disp32 = 1;
5579 i.types[op].bitfield.disp32s = 0;
5580 }
29b0f896 5581 else
40fb9820
L		 5582 {
5583 i.types[op].bitfield.disp32 = 0;
5584 i.types[op].bitfield.disp32s = 1;
5585 }
29b0f896 5586 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5587 i.rex |= REX_X;
29b0f896
AM		 5588 }
5589 }
5590 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5591 else if (i.base_reg->reg_num == RegRip ||
5592 i.base_reg->reg_num == RegEip)
29b0f896 5593 {
6c30d220 5594 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5595 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5596 i.types[op].bitfield.disp8 = 0;
5597 i.types[op].bitfield.disp16 = 0;
5598 i.types[op].bitfield.disp32 = 0;
5599 i.types[op].bitfield.disp32s = 1;
5600 i.types[op].bitfield.disp64 = 0;
71903a11 5601 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5602 if (! i.disp_operands)
5603 fake_zero_displacement = 1;
29b0f896 5604 }
40fb9820 5605 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 5606 {
6c30d220 5607 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5608 switch (i.base_reg->reg_num)
5609 {
5610 case 3: /* (%bx) */
5611 if (i.index_reg == 0)
5612 i.rm.regmem = 7;
5613 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5614 i.rm.regmem = i.index_reg->reg_num - 6;
5615 break;
5616 case 5: /* (%bp) */
5617 default_seg = &ss;
5618 if (i.index_reg == 0)
5619 {
5620 i.rm.regmem = 6;
40fb9820 5621 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5622 {
5623 /* fake (%bp) into 0(%bp) */
40fb9820 5624 i.types[op].bitfield.disp8 = 1;
252b5132 5625 fake_zero_displacement = 1;
29b0f896
AM		 5626 }
5627 }
5628 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5629 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5630 break;
5631 default: /* (%si) -> 4 or (%di) -> 5 */
5632 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5633 }
5634 i.rm.mode = mode_from_disp_size (i.types[op]);
5635 }
5636 else /* i.base_reg and 32/64 bit mode */
5637 {
5638 if (flag_code == CODE_64BIT
40fb9820
L		 5639 && operand_type_check (i.types[op], disp))
5640 {
5641 i386_operand_type temp;
0dfbf9d7 5642 operand_type_set (&temp, 0);
40fb9820
L		 5643 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5644 i.types[op] = temp;
5645 if (i.prefix[ADDR_PREFIX] == 0)
5646 i.types[op].bitfield.disp32s = 1;
5647 else
5648 i.types[op].bitfield.disp32 = 1;
5649 }
20f0a1fc 5650
6c30d220
L		 5651 if (!i.tm.opcode_modifier.vecsib)
5652 i.rm.regmem = i.base_reg->reg_num;
29b0f896 5653 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5654 i.rex |= REX_B;
29b0f896
AM		 5655 i.sib.base = i.base_reg->reg_num;
5656 /* x86-64 ignores REX prefix bit here to avoid decoder
5657 complications. */
5658 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5659 {
5660 default_seg = &ss;
5661 if (i.disp_operands == 0)
5662 {
5663 fake_zero_displacement = 1;
40fb9820 5664 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5665 }
5666 }
5667 else if (i.base_reg->reg_num == ESP_REG_NUM)
5668 {
5669 default_seg = &ss;
5670 }
5671 i.sib.scale = i.log2_scale_factor;
5672 if (i.index_reg == 0)
5673 {
6c30d220 5674 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5675 /* <disp>(%esp) becomes two byte modrm with no index
5676 register. We've already stored the code for esp
5677 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5678 Any base register besides %esp will not use the
5679 extra modrm byte. */
5680 i.sib.index = NO_INDEX_REGISTER;
29b0f896 5681 }
6c30d220 5682 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5683 {
db51cc60
L		 5684 if (i.index_reg->reg_num == RegEiz
5685 || i.index_reg->reg_num == RegRiz)
5686 i.sib.index = NO_INDEX_REGISTER;
5687 else
5688 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5689 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5690 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5691 i.rex |= REX_X;
29b0f896 5692 }
67a4f2b7
AO		 5693
5694 if (i.disp_operands
5695 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5696 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5697 i.rm.mode = 0;
5698 else
5699 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5700 }
252b5132 5701
29b0f896
AM		 5702 if (fake_zero_displacement)
5703 {
5704 /* Fakes a zero displacement assuming that i.types[op]
5705 holds the correct displacement size. */
5706 expressionS *exp;
5707
9c2799c2 5708 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5709 exp = &disp_expressions[i.disp_operands++];
5710 i.op[op].disps = exp;
5711 exp->X_op = O_constant;
5712 exp->X_add_number = 0;
5713 exp->X_add_symbol = (symbolS *) 0;
5714 exp->X_op_symbol = (symbolS *) 0;
5715 }
c0f3af97
L		 5716
5717 mem = op;
29b0f896 5718 }
c0f3af97
L		 5719 else
5720 mem = ~0;
252b5132 5721
8c43a48b 5722 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5723 {
5724 if (operand_type_check (i.types[0], imm))
5725 i.vex.register_specifier = NULL;
5726 else
5727 {
5728 /* VEX.vvvv encodes one of the sources when the first
5729 operand is not an immediate. */
1ef99a7b 5730 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5731 i.vex.register_specifier = i.op[0].regs;
5732 else
5733 i.vex.register_specifier = i.op[1].regs;
5734 }
5735
5736 /* Destination is a XMM register encoded in the ModRM.reg
5737 and VEX.R bit. */
5738 i.rm.reg = i.op[2].regs->reg_num;
5739 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5740 i.rex |= REX_R;
5741
5742 /* ModRM.rm and VEX.B encodes the other source. */
5743 if (!i.mem_operands)
5744 {
5745 i.rm.mode = 3;
5746
1ef99a7b 5747 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5748 i.rm.regmem = i.op[1].regs->reg_num;
5749 else
5750 i.rm.regmem = i.op[0].regs->reg_num;
5751
5752 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5753 i.rex |= REX_B;
5754 }
5755 }
2426c15f 5756 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5757 {
5758 i.vex.register_specifier = i.op[2].regs;
5759 if (!i.mem_operands)
5760 {
5761 i.rm.mode = 3;
5762 i.rm.regmem = i.op[1].regs->reg_num;
5763 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5764 i.rex |= REX_B;
5765 }
5766 }
29b0f896
AM		 5767 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5768 (if any) based on i.tm.extension_opcode. Again, we must be
5769 careful to make sure that segment/control/debug/test/MMX
5770 registers are coded into the i.rm.reg field. */
f88c9eb0 5771 else if (i.reg_operands)
29b0f896 5772 {
99018f42 5773 unsigned int op;
7ab9ffdd
L		 5774 unsigned int vex_reg = ~0;
5775
5776 for (op = 0; op < i.operands; op++)
5777 if (i.types[op].bitfield.reg8
5778 || i.types[op].bitfield.reg16
5779 || i.types[op].bitfield.reg32
5780 || i.types[op].bitfield.reg64
5781 || i.types[op].bitfield.regmmx
5782 || i.types[op].bitfield.regxmm
5783 || i.types[op].bitfield.regymm
5784 || i.types[op].bitfield.sreg2
5785 || i.types[op].bitfield.sreg3
5786 || i.types[op].bitfield.control
5787 || i.types[op].bitfield.debug
5788 || i.types[op].bitfield.test)
5789 break;
c0209578 5790
7ab9ffdd
L		 5791 if (vex_3_sources)
5792 op = dest;
2426c15f 5793 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5794 {
5795 /* For instructions with VexNDS, the register-only
5796 source operand is encoded in VEX prefix. */
5797 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5798
7ab9ffdd 5799 if (op > mem)
c0f3af97 5800 {
7ab9ffdd
L		 5801 vex_reg = op++;
5802 gas_assert (op < i.operands);
c0f3af97
L		 5803 }
5804 else
c0f3af97 5805 {
f12dc422
L		 5806 /* Check register-only source operand when two source
5807 operands are swapped. */
5808 if (!i.tm.operand_types[op].bitfield.baseindex
5809 && i.tm.operand_types[op + 1].bitfield.baseindex)
5810 {
5811 vex_reg = op;
5812 op += 2;
5813 gas_assert (mem == (vex_reg + 1)
5814 && op < i.operands);
5815 }
5816 else
5817 {
5818 vex_reg = op + 1;
5819 gas_assert (vex_reg < i.operands);
5820 }
c0f3af97 5821 }
7ab9ffdd 5822 }
2426c15f 5823 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 5824 {
f12dc422 5825 /* For instructions with VexNDD, the register destination
7ab9ffdd 5826 is encoded in VEX prefix. */
f12dc422
L		 5827 if (i.mem_operands == 0)
5828 {
5829 /* There is no memory operand. */
5830 gas_assert ((op + 2) == i.operands);
5831 vex_reg = op + 1;
5832 }
5833 else
5834 {
5835 /* There are only 2 operands. */
5836 gas_assert (op < 2 && i.operands == 2);
5837 vex_reg = 1;
5838 }
7ab9ffdd
L		 5839 }
5840 else
5841 gas_assert (op < i.operands);
99018f42 5842
7ab9ffdd
L		 5843 if (vex_reg != (unsigned int) ~0)
5844 {
f12dc422 5845 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 5846
f12dc422
L		 5847 if (type->bitfield.reg32 != 1
5848 && type->bitfield.reg64 != 1
5849 && !operand_type_equal (type, &regxmm)
5850 && !operand_type_equal (type, &regymm))
7ab9ffdd 5851 abort ();
f88c9eb0 5852
7ab9ffdd
L		 5853 i.vex.register_specifier = i.op[vex_reg].regs;
5854 }
5855
1b9f0c97
L		 5856 /* Don't set OP operand twice. */
5857 if (vex_reg != op)
7ab9ffdd 5858 {
1b9f0c97
L		 5859 /* If there is an extension opcode to put here, the
5860 register number must be put into the regmem field. */
5861 if (i.tm.extension_opcode != None)
5862 {
5863 i.rm.regmem = i.op[op].regs->reg_num;
5864 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5865 i.rex |= REX_B;
5866 }
5867 else
5868 {
5869 i.rm.reg = i.op[op].regs->reg_num;
5870 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5871 i.rex |= REX_R;
5872 }
7ab9ffdd 5873 }
252b5132 5874
29b0f896
AM		 5875 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5876 must set it to 3 to indicate this is a register operand
5877 in the regmem field. */
5878 if (!i.mem_operands)
5879 i.rm.mode = 3;
5880 }
252b5132 5881
29b0f896 5882 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5883 if (i.tm.extension_opcode != None)
29b0f896
AM		 5884 i.rm.reg = i.tm.extension_opcode;
5885 }
5886 return default_seg;
5887}
252b5132 5888
29b0f896 5889static void
e3bb37b5 5890output_branch (void)
29b0f896
AM		 5891{
5892 char *p;
f8a5c266 5893 int size;
29b0f896
AM		 5894 int code16;
5895 int prefix;
5896 relax_substateT subtype;
5897 symbolS *sym;
5898 offsetT off;
5899
f8a5c266
L		 5900 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
5901 size = i.disp32_encoding ? BIG : SMALL;
29b0f896
AM		 5902
5903 prefix = 0;
5904 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5905 {
29b0f896
AM		 5906 prefix = 1;
5907 i.prefixes -= 1;
5908 code16 ^= CODE16;
252b5132 5909 }
29b0f896
AM		 5910 /* Pentium4 branch hints. */
5911 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5912 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5913 {
29b0f896
AM		 5914 prefix++;
5915 i.prefixes--;
5916 }
5917 if (i.prefix[REX_PREFIX] != 0)
5918 {
5919 prefix++;
5920 i.prefixes--;
2f66722d
AM		 5921 }
5922
29b0f896
AM		 5923 if (i.prefixes != 0 && !intel_syntax)
5924 as_warn (_("skipping prefixes on this instruction"));
5925
5926 /* It's always a symbol; End frag & setup for relax.
5927 Make sure there is enough room in this frag for the largest
5928 instruction we may generate in md_convert_frag. This is 2
5929 bytes for the opcode and room for the prefix and largest
5930 displacement. */
5931 frag_grow (prefix + 2 + 4);
5932 /* Prefix and 1 opcode byte go in fr_fix. */
5933 p = frag_more (prefix + 1);
5934 if (i.prefix[DATA_PREFIX] != 0)
5935 *p++ = DATA_PREFIX_OPCODE;
5936 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5937 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5938 *p++ = i.prefix[SEG_PREFIX];
5939 if (i.prefix[REX_PREFIX] != 0)
5940 *p++ = i.prefix[REX_PREFIX];
5941 *p = i.tm.base_opcode;
5942
5943 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 5944 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 5945 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 5946 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 5947 else
f8a5c266 5948 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 5949 subtype |= code16;
3e73aa7c 5950
29b0f896
AM		 5951 sym = i.op[0].disps->X_add_symbol;
5952 off = i.op[0].disps->X_add_number;
3e73aa7c 5953
29b0f896
AM		 5954 if (i.op[0].disps->X_op != O_constant
5955 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5956 {
29b0f896
AM		 5957 /* Handle complex expressions. */
5958 sym = make_expr_symbol (i.op[0].disps);
5959 off = 0;
5960 }
3e73aa7c 5961
29b0f896
AM		 5962 /* 1 possible extra opcode + 4 byte displacement go in var part.
5963 Pass reloc in fr_var. */
5964 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5965}
3e73aa7c 5966
29b0f896 5967static void
e3bb37b5 5968output_jump (void)
29b0f896
AM		 5969{
5970 char *p;
5971 int size;
3e02c1cc 5972 fixS *fixP;
29b0f896 5973
40fb9820 5974 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5975 {
5976 /* This is a loop or jecxz type instruction. */
5977 size = 1;
5978 if (i.prefix[ADDR_PREFIX] != 0)
5979 {
5980 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5981 i.prefixes -= 1;
5982 }
5983 /* Pentium4 branch hints. */
5984 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5985 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5986 {
5987 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5988 i.prefixes--;
3e73aa7c
JH		 5989 }
5990 }
29b0f896
AM		 5991 else
5992 {
5993 int code16;
3e73aa7c 5994
29b0f896
AM		 5995 code16 = 0;
5996 if (flag_code == CODE_16BIT)
5997 code16 = CODE16;
3e73aa7c 5998
29b0f896
AM		 5999 if (i.prefix[DATA_PREFIX] != 0)
6000 {
6001 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6002 i.prefixes -= 1;
6003 code16 ^= CODE16;
6004 }
252b5132 6005
29b0f896
AM		 6006 size = 4;
6007 if (code16)
6008 size = 2;
6009 }
9fcc94b6 6010
29b0f896
AM		 6011 if (i.prefix[REX_PREFIX] != 0)
6012 {
6013 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6014 i.prefixes -= 1;
6015 }
252b5132 6016
29b0f896
AM		 6017 if (i.prefixes != 0 && !intel_syntax)
6018 as_warn (_("skipping prefixes on this instruction"));
e0890092 6019
29b0f896
AM		 6020 p = frag_more (1 + size);
6021 *p++ = i.tm.base_opcode;
e0890092 6022
3e02c1cc
AM		 6023 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6024 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
6025
6026 /* All jumps handled here are signed, but don't use a signed limit
6027 check for 32 and 16 bit jumps as we want to allow wrap around at
6028 4G and 64k respectively. */
6029 if (size == 1)
6030 fixP->fx_signed = 1;
29b0f896 6031}
e0890092 6032
29b0f896 6033static void
e3bb37b5 6034output_interseg_jump (void)
29b0f896
AM		 6035{
6036 char *p;
6037 int size;
6038 int prefix;
6039 int code16;
252b5132 6040
29b0f896
AM		 6041 code16 = 0;
6042 if (flag_code == CODE_16BIT)
6043 code16 = CODE16;
a217f122 6044
29b0f896
AM		 6045 prefix = 0;
6046 if (i.prefix[DATA_PREFIX] != 0)
6047 {
6048 prefix = 1;
6049 i.prefixes -= 1;
6050 code16 ^= CODE16;
6051 }
6052 if (i.prefix[REX_PREFIX] != 0)
6053 {
6054 prefix++;
6055 i.prefixes -= 1;
6056 }
252b5132 6057
29b0f896
AM		 6058 size = 4;
6059 if (code16)
6060 size = 2;
252b5132 6061
29b0f896
AM		 6062 if (i.prefixes != 0 && !intel_syntax)
6063 as_warn (_("skipping prefixes on this instruction"));
252b5132 6064
29b0f896
AM		 6065 /* 1 opcode; 2 segment; offset */
6066 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6067
29b0f896
AM		 6068 if (i.prefix[DATA_PREFIX] != 0)
6069 *p++ = DATA_PREFIX_OPCODE;
252b5132 6070
29b0f896
AM		 6071 if (i.prefix[REX_PREFIX] != 0)
6072 *p++ = i.prefix[REX_PREFIX];
252b5132 6073
29b0f896
AM		 6074 *p++ = i.tm.base_opcode;
6075 if (i.op[1].imms->X_op == O_constant)
6076 {
6077 offsetT n = i.op[1].imms->X_add_number;
252b5132 6078
29b0f896
AM		 6079 if (size == 2
6080 && !fits_in_unsigned_word (n)
6081 && !fits_in_signed_word (n))
6082 {
6083 as_bad (_("16-bit jump out of range"));
6084 return;
6085 }
6086 md_number_to_chars (p, n, size);
6087 }
6088 else
6089 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6090 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
6091 if (i.op[0].imms->X_op != O_constant)
6092 as_bad (_("can't handle non absolute segment in `%s'"),
6093 i.tm.name);
6094 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6095}
a217f122 6096
29b0f896 6097static void
e3bb37b5 6098output_insn (void)
29b0f896 6099{
2bbd9c25
JJ		 6100 fragS *insn_start_frag;
6101 offsetT insn_start_off;
6102
29b0f896
AM		 6103 /* Tie dwarf2 debug info to the address at the start of the insn.
6104 We can't do this after the insn has been output as the current
6105 frag may have been closed off. eg. by frag_var. */
6106 dwarf2_emit_insn (0);
6107
2bbd9c25
JJ		 6108 insn_start_frag = frag_now;
6109 insn_start_off = frag_now_fix ();
6110
29b0f896 6111 /* Output jumps. */
40fb9820 6112 if (i.tm.opcode_modifier.jump)
29b0f896 6113 output_branch ();
40fb9820
L		 6114 else if (i.tm.opcode_modifier.jumpbyte
6115 || i.tm.opcode_modifier.jumpdword)
29b0f896 6116 output_jump ();
40fb9820 6117 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6118 output_interseg_jump ();
6119 else
6120 {
6121 /* Output normal instructions here. */
6122 char *p;
6123 unsigned char *q;
47465058 6124 unsigned int j;
331d2d0d 6125 unsigned int prefix;
4dffcebc 6126
c0f3af97
L		 6127 /* Since the VEX prefix contains the implicit prefix, we don't
6128 need the explicit prefix. */
6129 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 6130 {
c0f3af97 6131 switch (i.tm.opcode_length)
bc4bd9ab 6132 {
c0f3af97
L		 6133 case 3:
6134 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6135 {
c0f3af97
L		 6136 prefix = (i.tm.base_opcode >> 24) & 0xff;
6137 goto check_prefix;
6138 }
6139 break;
6140 case 2:
6141 if ((i.tm.base_opcode & 0xff0000) != 0)
6142 {
6143 prefix = (i.tm.base_opcode >> 16) & 0xff;
6144 if (i.tm.cpu_flags.bitfield.cpupadlock)
6145 {
4dffcebc 6146check_prefix:
c0f3af97 6147 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6148 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6149 != REPE_PREFIX_OPCODE))
6150 add_prefix (prefix);
6151 }
6152 else
4dffcebc
L		 6153 add_prefix (prefix);
6154 }
c0f3af97
L		 6155 break;
6156 case 1:
6157 break;
6158 default:
6159 abort ();
bc4bd9ab 6160 }
c0f3af97
L		 6161
6162 /* The prefix bytes. */
6163 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6164 if (*q)
6165 FRAG_APPEND_1_CHAR (*q);
0f10071e 6166 }
252b5132 6167
c0f3af97
L		 6168 if (i.tm.opcode_modifier.vex)
6169 {
6170 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6171 if (*q)
6172 switch (j)
6173 {
6174 case REX_PREFIX:
6175 /* REX byte is encoded in VEX prefix. */
6176 break;
6177 case SEG_PREFIX:
6178 case ADDR_PREFIX:
6179 FRAG_APPEND_1_CHAR (*q);
6180 break;
6181 default:
6182 /* There should be no other prefixes for instructions
6183 with VEX prefix. */
6184 abort ();
6185 }
6186
6187 /* Now the VEX prefix. */
6188 p = frag_more (i.vex.length);
6189 for (j = 0; j < i.vex.length; j++)
6190 p[j] = i.vex.bytes[j];
6191 }
252b5132 6192
29b0f896 6193 /* Now the opcode; be careful about word order here! */
4dffcebc 6194 if (i.tm.opcode_length == 1)
29b0f896
AM		 6195 {
6196 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6197 }
6198 else
6199 {
4dffcebc 6200 switch (i.tm.opcode_length)
331d2d0d 6201 {
4dffcebc 6202 case 3:
331d2d0d
L		 6203 p = frag_more (3);
6204 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6205 break;
6206 case 2:
6207 p = frag_more (2);
6208 break;
6209 default:
6210 abort ();
6211 break;
331d2d0d 6212 }
0f10071e 6213
29b0f896
AM		 6214 /* Put out high byte first: can't use md_number_to_chars! */
6215 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6216 *p = i.tm.base_opcode & 0xff;
6217 }
3e73aa7c 6218
29b0f896 6219 /* Now the modrm byte and sib byte (if present). */
40fb9820 6220 if (i.tm.opcode_modifier.modrm)
29b0f896 6221 {
4a3523fa
L		 6222 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6223 | i.rm.reg << 3
6224 | i.rm.mode << 6));
29b0f896
AM		 6225 /* If i.rm.regmem == ESP (4)
6226 && i.rm.mode != (Register mode)
6227 && not 16 bit
6228 ==> need second modrm byte. */
6229 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6230 && i.rm.mode != 3
40fb9820 6231 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6232 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6233 | i.sib.index << 3
6234 | i.sib.scale << 6));
29b0f896 6235 }
3e73aa7c 6236
29b0f896 6237 if (i.disp_operands)
2bbd9c25 6238 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6239
29b0f896 6240 if (i.imm_operands)
2bbd9c25 6241 output_imm (insn_start_frag, insn_start_off);
29b0f896 6242 }
252b5132 6243
29b0f896
AM		 6244#ifdef DEBUG386
6245 if (flag_debug)
6246 {
7b81dfbb 6247 pi ("" /*line*/, &i);
29b0f896
AM		 6248 }
6249#endif /* DEBUG386 */
6250}
252b5132 6251
e205caa7
L		 6252/* Return the size of the displacement operand N. */
6253
6254static int
6255disp_size (unsigned int n)
6256{
6257 int size = 4;
40fb9820
L		 6258 if (i.types[n].bitfield.disp64)
6259 size = 8;
6260 else if (i.types[n].bitfield.disp8)
6261 size = 1;
6262 else if (i.types[n].bitfield.disp16)
6263 size = 2;
e205caa7
L		 6264 return size;
6265}
6266
6267/* Return the size of the immediate operand N. */
6268
6269static int
6270imm_size (unsigned int n)
6271{
6272 int size = 4;
40fb9820
L		 6273 if (i.types[n].bitfield.imm64)
6274 size = 8;
6275 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6276 size = 1;
6277 else if (i.types[n].bitfield.imm16)
6278 size = 2;
e205caa7
L		 6279 return size;
6280}
6281
29b0f896 6282static void
64e74474 6283output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6284{
6285 char *p;
6286 unsigned int n;
252b5132 6287
29b0f896
AM		 6288 for (n = 0; n < i.operands; n++)
6289 {
40fb9820 6290 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6291 {
6292 if (i.op[n].disps->X_op == O_constant)
6293 {
e205caa7 6294 int size = disp_size (n);
29b0f896 6295 offsetT val;
252b5132 6296
29b0f896
AM		 6297 val = offset_in_range (i.op[n].disps->X_add_number,
6298 size);
6299 p = frag_more (size);
6300 md_number_to_chars (p, val, size);
6301 }
6302 else
6303 {
f86103b7 6304 enum bfd_reloc_code_real reloc_type;
e205caa7 6305 int size = disp_size (n);
40fb9820 6306 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6307 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6308
e205caa7 6309 /* We can't have 8 bit displacement here. */
9c2799c2 6310 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6311
29b0f896
AM		 6312 /* The PC relative address is computed relative
6313 to the instruction boundary, so in case immediate
6314 fields follows, we need to adjust the value. */
6315 if (pcrel && i.imm_operands)
6316 {
29b0f896 6317 unsigned int n1;
e205caa7 6318 int sz = 0;
252b5132 6319
29b0f896 6320 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6321 if (operand_type_check (i.types[n1], imm))
252b5132 6322 {
e205caa7
L		 6323 /* Only one immediate is allowed for PC
6324 relative address. */
9c2799c2 6325 gas_assert (sz == 0);
e205caa7
L		 6326 sz = imm_size (n1);
6327 i.op[n].disps->X_add_number -= sz;
252b5132 6328 }
29b0f896 6329 /* We should find the immediate. */
9c2799c2 6330 gas_assert (sz != 0);
29b0f896 6331 }
520dc8e8 6332
29b0f896 6333 p = frag_more (size);
2bbd9c25 6334 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6335 if (GOT_symbol
2bbd9c25 6336 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6337 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6338 || reloc_type == BFD_RELOC_X86_64_32S
6339 || (reloc_type == BFD_RELOC_64
6340 && object_64bit))
d6ab8113
JB		 6341 && (i.op[n].disps->X_op == O_symbol
6342 || (i.op[n].disps->X_op == O_add
6343 && ((symbol_get_value_expression
6344 (i.op[n].disps->X_op_symbol)->X_op)
6345 == O_subtract))))
6346 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6347 {
6348 offsetT add;
6349
6350 if (insn_start_frag == frag_now)
6351 add = (p - frag_now->fr_literal) - insn_start_off;
6352 else
6353 {
6354 fragS *fr;
6355
6356 add = insn_start_frag->fr_fix - insn_start_off;
6357 for (fr = insn_start_frag->fr_next;
6358 fr && fr != frag_now; fr = fr->fr_next)
6359 add += fr->fr_fix;
6360 add += p - frag_now->fr_literal;
6361 }
6362
4fa24527 6363 if (!object_64bit)
7b81dfbb
AJ		 6364 {
6365 reloc_type = BFD_RELOC_386_GOTPC;
6366 i.op[n].imms->X_add_number += add;
6367 }
6368 else if (reloc_type == BFD_RELOC_64)
6369 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6370 else
7b81dfbb
AJ		 6371 /* Don't do the adjustment for x86-64, as there
6372 the pcrel addressing is relative to the _next_
6373 insn, and that is taken care of in other code. */
d6ab8113 6374 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6375 }
062cd5e7 6376 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6377 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6378 }
6379 }
6380 }
6381}
252b5132 6382
29b0f896 6383static void
64e74474 6384output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6385{
6386 char *p;
6387 unsigned int n;
252b5132 6388
29b0f896
AM		 6389 for (n = 0; n < i.operands; n++)
6390 {
40fb9820 6391 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6392 {
6393 if (i.op[n].imms->X_op == O_constant)
6394 {
e205caa7 6395 int size = imm_size (n);
29b0f896 6396 offsetT val;
b4cac588 6397
29b0f896
AM		 6398 val = offset_in_range (i.op[n].imms->X_add_number,
6399 size);
6400 p = frag_more (size);
6401 md_number_to_chars (p, val, size);
6402 }
6403 else
6404 {
6405 /* Not absolute_section.
6406 Need a 32-bit fixup (don't support 8bit
6407 non-absolute imms). Try to support other
6408 sizes ... */
f86103b7 6409 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6410 int size = imm_size (n);
6411 int sign;
29b0f896 6412
40fb9820 6413 if (i.types[n].bitfield.imm32s
a7d61044 6414 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6415 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6416 sign = 1;
e205caa7
L		 6417 else
6418 sign = 0;
520dc8e8 6419
29b0f896
AM		 6420 p = frag_more (size);
6421 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6422
2bbd9c25
JJ		 6423 /* This is tough to explain. We end up with this one if we
6424 * have operands that look like
6425 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6426 * obtain the absolute address of the GOT, and it is strongly
6427 * preferable from a performance point of view to avoid using
6428 * a runtime relocation for this. The actual sequence of
6429 * instructions often look something like:
6430 *
6431 * call .L66
6432 * .L66:
6433 * popl %ebx
6434 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6435 *
6436 * The call and pop essentially return the absolute address
6437 * of the label .L66 and store it in %ebx. The linker itself
6438 * will ultimately change the first operand of the addl so
6439 * that %ebx points to the GOT, but to keep things simple, the
6440 * .o file must have this operand set so that it generates not
6441 * the absolute address of .L66, but the absolute address of
6442 * itself. This allows the linker itself simply treat a GOTPC
6443 * relocation as asking for a pcrel offset to the GOT to be
6444 * added in, and the addend of the relocation is stored in the
6445 * operand field for the instruction itself.
6446 *
6447 * Our job here is to fix the operand so that it would add
6448 * the correct offset so that %ebx would point to itself. The
6449 * thing that is tricky is that .-.L66 will point to the
6450 * beginning of the instruction, so we need to further modify
6451 * the operand so that it will point to itself. There are
6452 * other cases where you have something like:
6453 *
6454 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6455 *
6456 * and here no correction would be required. Internally in
6457 * the assembler we treat operands of this form as not being
6458 * pcrel since the '.' is explicitly mentioned, and I wonder
6459 * whether it would simplify matters to do it this way. Who
6460 * knows. In earlier versions of the PIC patches, the
6461 * pcrel_adjust field was used to store the correction, but
6462 * since the expression is not pcrel, I felt it would be
6463 * confusing to do it this way. */
6464
d6ab8113 6465 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6466 || reloc_type == BFD_RELOC_X86_64_32S
6467 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6468 && GOT_symbol
6469 && GOT_symbol == i.op[n].imms->X_add_symbol
6470 && (i.op[n].imms->X_op == O_symbol
6471 || (i.op[n].imms->X_op == O_add
6472 && ((symbol_get_value_expression
6473 (i.op[n].imms->X_op_symbol)->X_op)
6474 == O_subtract))))
6475 {
2bbd9c25
JJ		 6476 offsetT add;
6477
6478 if (insn_start_frag == frag_now)
6479 add = (p - frag_now->fr_literal) - insn_start_off;
6480 else
6481 {
6482 fragS *fr;
6483
6484 add = insn_start_frag->fr_fix - insn_start_off;
6485 for (fr = insn_start_frag->fr_next;
6486 fr && fr != frag_now; fr = fr->fr_next)
6487 add += fr->fr_fix;
6488 add += p - frag_now->fr_literal;
6489 }
6490
4fa24527 6491 if (!object_64bit)
d6ab8113 6492 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6493 else if (size == 4)
d6ab8113 6494 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6495 else if (size == 8)
6496 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6497 i.op[n].imms->X_add_number += add;
29b0f896 6498 }
29b0f896
AM		 6499 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6500 i.op[n].imms, 0, reloc_type);
6501 }
6502 }
6503 }
252b5132
RH		 6504}
6505\f
d182319b
JB		 6506/* x86_cons_fix_new is called via the expression parsing code when a
6507 reloc is needed. We use this hook to get the correct .got reloc. */
6508static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6509static int cons_sign = -1;
6510
6511void
e3bb37b5 6512x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6513 expressionS *exp)
d182319b
JB		 6514{
6515 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6516
6517 got_reloc = NO_RELOC;
6518
6519#ifdef TE_PE
6520 if (exp->X_op == O_secrel)
6521 {
6522 exp->X_op = O_symbol;
6523 r = BFD_RELOC_32_SECREL;
6524 }
6525#endif
6526
6527 fix_new_exp (frag, off, len, exp, 0, r);
6528}
6529
d382c579
TG		 6530#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
6531 || defined (LEX_AT)
718ddfc0
JB		 6532# define lex_got(reloc, adjust, types) NULL
6533#else
f3c180ae
AM		 6534/* Parse operands of the form
6535 <symbol>@GOTOFF+<nnn>
6536 and similar .plt or .got references.
6537
6538 If we find one, set up the correct relocation in RELOC and copy the
6539 input string, minus the `@GOTOFF' into a malloc'd buffer for
6540 parsing by the calling routine. Return this buffer, and if ADJUST
6541 is non-null set it to the length of the string we removed from the
6542 input line. Otherwise return NULL. */
6543static char *
91d6fa6a 6544lex_got (enum bfd_reloc_code_real *rel,
64e74474 6545 int *adjust,
40fb9820 6546 i386_operand_type *types)
f3c180ae 6547{
7b81dfbb
AJ		 6548 /* Some of the relocations depend on the size of what field is to
6549 be relocated. But in our callers i386_immediate and i386_displacement
6550 we don't yet know the operand size (this will be set by insn
6551 matching). Hence we record the word32 relocation here,
6552 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6553 static const struct {
6554 const char *str;
cff8d58a 6555 int len;
4fa24527 6556 const enum bfd_reloc_code_real rel[2];
40fb9820 6557 const i386_operand_type types64;
f3c180ae 6558 } gotrel[] = {
cff8d58a
L		 6559 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6560 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6561 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6562 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6563 BFD_RELOC_X86_64_PLT32 },
40fb9820 6564 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6565 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6566 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6567 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6568 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6569 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6570 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6571 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6572 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6573 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6574 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6575 BFD_RELOC_X86_64_TLSGD },
40fb9820 6576 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6577 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6578 _dummy_first_bfd_reloc_code_real },
40fb9820 6579 OPERAND_TYPE_NONE },
cff8d58a
L		 6580 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6581 BFD_RELOC_X86_64_TLSLD },
40fb9820 6582 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6583 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6584 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6585 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6586 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6587 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6588 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6589 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6590 _dummy_first_bfd_reloc_code_real },
40fb9820 6591 OPERAND_TYPE_NONE },
cff8d58a
L		 6592 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6593 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6594 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6595 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6596 _dummy_first_bfd_reloc_code_real },
40fb9820 6597 OPERAND_TYPE_NONE },
cff8d58a
L		 6598 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6599 _dummy_first_bfd_reloc_code_real },
40fb9820 6600 OPERAND_TYPE_NONE },
cff8d58a
L		 6601 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6602 BFD_RELOC_X86_64_GOT32 },
40fb9820 6603 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6604 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6605 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6606 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6607 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6608 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6609 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6610 };
6611 char *cp;
6612 unsigned int j;
6613
d382c579 6614#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 6615 if (!IS_ELF)
6616 return NULL;
d382c579 6617#endif
718ddfc0 6618
f3c180ae 6619 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6620 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6621 return NULL;
6622
47465058 6623 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6624 {
cff8d58a 6625 int len = gotrel[j].len;
28f81592 6626 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6627 {
4fa24527 6628 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6629 {
28f81592
AM		 6630 int first, second;
6631 char *tmpbuf, *past_reloc;
f3c180ae 6632
91d6fa6a 6633 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6634 if (adjust)
6635 *adjust = len;
f3c180ae 6636
3956db08
JB		 6637 if (types)
6638 {
6639 if (flag_code != CODE_64BIT)
40fb9820
L		 6640 {
6641 types->bitfield.imm32 = 1;
6642 types->bitfield.disp32 = 1;
6643 }
3956db08
JB		 6644 else
6645 *types = gotrel[j].types64;
6646 }
6647
f3c180ae
AM		 6648 if (GOT_symbol == NULL)
6649 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6650
28f81592 6651 /* The length of the first part of our input line. */
f3c180ae 6652 first = cp - input_line_pointer;
28f81592
AM		 6653
6654 /* The second part goes from after the reloc token until
67c11a9b 6655 (and including) an end_of_line char or comma. */
28f81592 6656 past_reloc = cp + 1 + len;
67c11a9b
AM		 6657 cp = past_reloc;
6658 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6659 ++cp;
6660 second = cp + 1 - past_reloc;
28f81592
AM		 6661
6662 /* Allocate and copy string. The trailing NUL shouldn't
6663 be necessary, but be safe. */
1e9cc1c2 6664 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6665 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6666 if (second != 0 && *past_reloc != ' ')
6667 /* Replace the relocation token with ' ', so that
6668 errors like foo@GOTOFF1 will be detected. */
6669 tmpbuf[first++] = ' ';
6670 memcpy (tmpbuf + first, past_reloc, second);
6671 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6672 return tmpbuf;
6673 }
6674
4fa24527
JB		 6675 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6676 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6677 return NULL;
6678 }
6679 }
6680
6681 /* Might be a symbol version string. Don't as_bad here. */
6682 return NULL;
6683}
4e4f7c87 6684#endif
f3c180ae 6685
f3c180ae 6686void
e3bb37b5 6687x86_cons (expressionS *exp, int size)
f3c180ae 6688{
ee86248c
JB		 6689 intel_syntax = -intel_syntax;
6690
3c7b9c2c 6691 exp->X_md = 0;
4fa24527 6692 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6693 {
6694 /* Handle @GOTOFF and the like in an expression. */
6695 char *save;
6696 char *gotfree_input_line;
4a57f2cf 6697 int adjust = 0;
f3c180ae
AM		 6698
6699 save = input_line_pointer;
3956db08 6700 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6701 if (gotfree_input_line)
6702 input_line_pointer = gotfree_input_line;
6703
6704 expression (exp);
6705
6706 if (gotfree_input_line)
6707 {
6708 /* expression () has merrily parsed up to the end of line,
6709 or a comma - in the wrong buffer. Transfer how far
6710 input_line_pointer has moved to the right buffer. */
6711 input_line_pointer = (save
6712 + (input_line_pointer - gotfree_input_line)
6713 + adjust);
6714 free (gotfree_input_line);
3992d3b7
AM		 6715 if (exp->X_op == O_constant
6716 || exp->X_op == O_absent
6717 || exp->X_op == O_illegal
0398aac5 6718 || exp->X_op == O_register
3992d3b7
AM		 6719 || exp->X_op == O_big)
6720 {
6721 char c = *input_line_pointer;
6722 *input_line_pointer = 0;
6723 as_bad (_("missing or invalid expression `%s'"), save);
6724 *input_line_pointer = c;
6725 }
f3c180ae
AM		 6726 }
6727 }
6728 else
6729 expression (exp);
ee86248c
JB		 6730
6731 intel_syntax = -intel_syntax;
6732
6733 if (intel_syntax)
6734 i386_intel_simplify (exp);
f3c180ae 6735}
f3c180ae 6736
9f32dd5b
L		 6737static void
6738signed_cons (int size)
6482c264 6739{
d182319b
JB		 6740 if (flag_code == CODE_64BIT)
6741 cons_sign = 1;
6742 cons (size);
6743 cons_sign = -1;
6482c264
NC		 6744}
6745
d182319b 6746#ifdef TE_PE
6482c264 6747static void
7016a5d5 6748pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 6749{
6750 expressionS exp;
6751
6752 do
6753 {
6754 expression (&exp);
6755 if (exp.X_op == O_symbol)
6756 exp.X_op = O_secrel;
6757
6758 emit_expr (&exp, 4);
6759 }
6760 while (*input_line_pointer++ == ',');
6761
6762 input_line_pointer--;
6763 demand_empty_rest_of_line ();
6764}
6482c264
NC		 6765#endif
6766
252b5132 6767static int
70e41ade 6768i386_immediate (char *imm_start)
252b5132
RH		 6769{
6770 char *save_input_line_pointer;
f3c180ae 6771 char *gotfree_input_line;
252b5132 6772 segT exp_seg = 0;
47926f60 6773 expressionS *exp;
40fb9820
L		 6774 i386_operand_type types;
6775
0dfbf9d7 6776 operand_type_set (&types, ~0);
252b5132
RH		 6777
6778 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6779 {
31b2323c
L		 6780 as_bad (_("at most %d immediate operands are allowed"),
6781 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6782 return 0;
6783 }
6784
6785 exp = &im_expressions[i.imm_operands++];
520dc8e8 6786 i.op[this_operand].imms = exp;
252b5132
RH		 6787
6788 if (is_space_char (*imm_start))
6789 ++imm_start;
6790
6791 save_input_line_pointer = input_line_pointer;
6792 input_line_pointer = imm_start;
6793
3956db08 6794 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6795 if (gotfree_input_line)
6796 input_line_pointer = gotfree_input_line;
252b5132
RH		 6797
6798 exp_seg = expression (exp);
6799
83183c0c 6800 SKIP_WHITESPACE ();
252b5132 6801 if (*input_line_pointer)
f3c180ae 6802 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6803
6804 input_line_pointer = save_input_line_pointer;
f3c180ae 6805 if (gotfree_input_line)
ee86248c
JB		 6806 {
6807 free (gotfree_input_line);
6808
6809 if (exp->X_op == O_constant || exp->X_op == O_register)
6810 exp->X_op = O_illegal;
6811 }
6812
6813 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6814}
252b5132 6815
ee86248c
JB		 6816static int
6817i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6818 i386_operand_type types, const char *imm_start)
6819{
6820 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6821 {
313c53d1
L		 6822 if (imm_start)
6823 as_bad (_("missing or invalid immediate expression `%s'"),
6824 imm_start);
3992d3b7 6825 return 0;
252b5132 6826 }
3e73aa7c 6827 else if (exp->X_op == O_constant)
252b5132 6828 {
47926f60 6829 /* Size it properly later. */
40fb9820 6830 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 6831 /* If not 64bit, sign extend val. */
6832 if (flag_code != CODE_64BIT
4eed87de
AM		 6833 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6834 exp->X_add_number
6835 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6836 }
4c63da97 6837#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6838 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6839 && exp_seg != absolute_section
47926f60 6840 && exp_seg != text_section
24eab124
AM		 6841 && exp_seg != data_section
6842 && exp_seg != bss_section
6843 && exp_seg != undefined_section
f86103b7 6844 && !bfd_is_com_section (exp_seg))
252b5132 6845 {
d0b47220 6846 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6847 return 0;
6848 }
6849#endif
bb8f5920
L		 6850 else if (!intel_syntax && exp->X_op == O_register)
6851 {
313c53d1
L		 6852 if (imm_start)
6853 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6854 return 0;
6855 }
252b5132
RH		 6856 else
6857 {
6858 /* This is an address. The size of the address will be
24eab124 6859 determined later, depending on destination register,
3e73aa7c 6860 suffix, or the default for the section. */
40fb9820
L		 6861 i.types[this_operand].bitfield.imm8 = 1;
6862 i.types[this_operand].bitfield.imm16 = 1;
6863 i.types[this_operand].bitfield.imm32 = 1;
6864 i.types[this_operand].bitfield.imm32s = 1;
6865 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6866 i.types[this_operand] = operand_type_and (i.types[this_operand],
6867 types);
252b5132
RH		 6868 }
6869
6870 return 1;
6871}
6872
551c1ca1 6873static char *
e3bb37b5 6874i386_scale (char *scale)
252b5132 6875{
551c1ca1
AM		 6876 offsetT val;
6877 char *save = input_line_pointer;
252b5132 6878
551c1ca1
AM		 6879 input_line_pointer = scale;
6880 val = get_absolute_expression ();
6881
6882 switch (val)
252b5132 6883 {
551c1ca1 6884 case 1:
252b5132
RH		 6885 i.log2_scale_factor = 0;
6886 break;
551c1ca1 6887 case 2:
252b5132
RH		 6888 i.log2_scale_factor = 1;
6889 break;
551c1ca1 6890 case 4:
252b5132
RH		 6891 i.log2_scale_factor = 2;
6892 break;
551c1ca1 6893 case 8:
252b5132
RH		 6894 i.log2_scale_factor = 3;
6895 break;
6896 default:
a724f0f4
JB		 6897 {
6898 char sep = *input_line_pointer;
6899
6900 *input_line_pointer = '\0';
6901 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6902 scale);
6903 *input_line_pointer = sep;
6904 input_line_pointer = save;
6905 return NULL;
6906 }
252b5132 6907 }
29b0f896 6908 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6909 {
6910 as_warn (_("scale factor of %d without an index register"),
24eab124 6911 1 << i.log2_scale_factor);
252b5132 6912 i.log2_scale_factor = 0;
252b5132 6913 }
551c1ca1
AM		 6914 scale = input_line_pointer;
6915 input_line_pointer = save;
6916 return scale;
252b5132
RH		 6917}
6918
252b5132 6919static int
e3bb37b5 6920i386_displacement (char *disp_start, char *disp_end)
252b5132 6921{
29b0f896 6922 expressionS *exp;
252b5132
RH		 6923 segT exp_seg = 0;
6924 char *save_input_line_pointer;
f3c180ae 6925 char *gotfree_input_line;
40fb9820
L		 6926 int override;
6927 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6928 int ret;
252b5132 6929
31b2323c
L		 6930 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6931 {
6932 as_bad (_("at most %d displacement operands are allowed"),
6933 MAX_MEMORY_OPERANDS);
6934 return 0;
6935 }
6936
0dfbf9d7 6937 operand_type_set (&bigdisp, 0);
40fb9820
L		 6938 if ((i.types[this_operand].bitfield.jumpabsolute)
6939 || (!current_templates->start->opcode_modifier.jump
6940 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6941 {
40fb9820 6942 bigdisp.bitfield.disp32 = 1;
e05278af 6943 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6944 if (flag_code == CODE_64BIT)
6945 {
6946 if (!override)
6947 {
6948 bigdisp.bitfield.disp32s = 1;
6949 bigdisp.bitfield.disp64 = 1;
6950 }
6951 }
6952 else if ((flag_code == CODE_16BIT) ^ override)
6953 {
6954 bigdisp.bitfield.disp32 = 0;
6955 bigdisp.bitfield.disp16 = 1;
6956 }
e05278af
JB		 6957 }
6958 else
6959 {
6960 /* For PC-relative branches, the width of the displacement
6961 is dependent upon data size, not address size. */
e05278af 6962 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6963 if (flag_code == CODE_64BIT)
6964 {
6965 if (override || i.suffix == WORD_MNEM_SUFFIX)
6966 bigdisp.bitfield.disp16 = 1;
6967 else
6968 {
6969 bigdisp.bitfield.disp32 = 1;
6970 bigdisp.bitfield.disp32s = 1;
6971 }
6972 }
6973 else
e05278af
JB		 6974 {
6975 if (!override)
6976 override = (i.suffix == (flag_code != CODE_16BIT
6977 ? WORD_MNEM_SUFFIX
6978 : LONG_MNEM_SUFFIX));
40fb9820
L		 6979 bigdisp.bitfield.disp32 = 1;
6980 if ((flag_code == CODE_16BIT) ^ override)
6981 {
6982 bigdisp.bitfield.disp32 = 0;
6983 bigdisp.bitfield.disp16 = 1;
6984 }
e05278af 6985 }
e05278af 6986 }
c6fb90c8
L		 6987 i.types[this_operand] = operand_type_or (i.types[this_operand],
6988 bigdisp);
252b5132
RH		 6989
6990 exp = &disp_expressions[i.disp_operands];
520dc8e8 6991 i.op[this_operand].disps = exp;
252b5132
RH		 6992 i.disp_operands++;
6993 save_input_line_pointer = input_line_pointer;
6994 input_line_pointer = disp_start;
6995 END_STRING_AND_SAVE (disp_end);
6996
6997#ifndef GCC_ASM_O_HACK
6998#define GCC_ASM_O_HACK 0
6999#endif
7000#if GCC_ASM_O_HACK
7001 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 7002 if (i.types[this_operand].bitfield.baseIndex
24eab124 7003 && displacement_string_end[-1] == '+')
252b5132
RH		 7004 {
7005 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 7006 constraint within gcc asm statements.
7007 For instance:
7008
7009 #define _set_tssldt_desc(n,addr,limit,type) \
7010 __asm__ __volatile__ ( \
7011 "movw %w2,%0\n\t" \
7012 "movw %w1,2+%0\n\t" \
7013 "rorl $16,%1\n\t" \
7014 "movb %b1,4+%0\n\t" \
7015 "movb %4,5+%0\n\t" \
7016 "movb $0,6+%0\n\t" \
7017 "movb %h1,7+%0\n\t" \
7018 "rorl $16,%1" \
7019 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
7020
7021 This works great except that the output assembler ends
7022 up looking a bit weird if it turns out that there is
7023 no offset. You end up producing code that looks like:
7024
7025 #APP
7026 movw $235,(%eax)
7027 movw %dx,2+(%eax)
7028 rorl $16,%edx
7029 movb %dl,4+(%eax)
7030 movb $137,5+(%eax)
7031 movb $0,6+(%eax)
7032 movb %dh,7+(%eax)
7033 rorl $16,%edx
7034 #NO_APP
7035
47926f60 7036 So here we provide the missing zero. */
24eab124
AM		 7037
7038 *displacement_string_end = '0';
252b5132
RH		 7039 }
7040#endif
3956db08 7041 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7042 if (gotfree_input_line)
7043 input_line_pointer = gotfree_input_line;
252b5132 7044
24eab124 7045 exp_seg = expression (exp);
252b5132 7046
636c26b0
AM		 7047 SKIP_WHITESPACE ();
7048 if (*input_line_pointer)
7049 as_bad (_("junk `%s' after expression"), input_line_pointer);
7050#if GCC_ASM_O_HACK
7051 RESTORE_END_STRING (disp_end + 1);
7052#endif
636c26b0 7053 input_line_pointer = save_input_line_pointer;
636c26b0 7054 if (gotfree_input_line)
ee86248c
JB		 7055 {
7056 free (gotfree_input_line);
7057
7058 if (exp->X_op == O_constant || exp->X_op == O_register)
7059 exp->X_op = O_illegal;
7060 }
7061
7062 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
7063
7064 RESTORE_END_STRING (disp_end);
7065
7066 return ret;
7067}
7068
7069static int
7070i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7071 i386_operand_type types, const char *disp_start)
7072{
7073 i386_operand_type bigdisp;
7074 int ret = 1;
636c26b0 7075
24eab124
AM		 7076 /* We do this to make sure that the section symbol is in
7077 the symbol table. We will ultimately change the relocation
47926f60 7078 to be relative to the beginning of the section. */
1ae12ab7 7079 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 7080 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
7081 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 7082 {
636c26b0 7083 if (exp->X_op != O_symbol)
3992d3b7 7084 goto inv_disp;
636c26b0 7085
e5cb08ac 7086 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 7087 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
7088 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 7089 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 7090 exp->X_op = O_subtract;
7091 exp->X_op_symbol = GOT_symbol;
1ae12ab7 7092 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 7093 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 7094 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
7095 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 7096 else
29b0f896 7097 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 7098 }
252b5132 7099
3992d3b7
AM		 7100 else if (exp->X_op == O_absent
7101 || exp->X_op == O_illegal
ee86248c 7102 || exp->X_op == O_big)
2daf4fd8 7103 {
3992d3b7
AM		 7104 inv_disp:
7105 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 7106 disp_start);
3992d3b7 7107 ret = 0;
2daf4fd8
AM		 7108 }
7109
0e1147d9
L		 7110 else if (flag_code == CODE_64BIT
7111 && !i.prefix[ADDR_PREFIX]
7112 && exp->X_op == O_constant)
7113 {
7114 /* Since displacement is signed extended to 64bit, don't allow
7115 disp32 and turn off disp32s if they are out of range. */
7116 i.types[this_operand].bitfield.disp32 = 0;
7117 if (!fits_in_signed_long (exp->X_add_number))
7118 {
7119 i.types[this_operand].bitfield.disp32s = 0;
7120 if (i.types[this_operand].bitfield.baseindex)
7121 {
7122 as_bad (_("0x%lx out range of signed 32bit displacement"),
7123 (long) exp->X_add_number);
7124 ret = 0;
7125 }
7126 }
7127 }
7128
4c63da97 7129#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 7130 else if (exp->X_op != O_constant
7131 && OUTPUT_FLAVOR == bfd_target_aout_flavour
7132 && exp_seg != absolute_section
7133 && exp_seg != text_section
7134 && exp_seg != data_section
7135 && exp_seg != bss_section
7136 && exp_seg != undefined_section
7137 && !bfd_is_com_section (exp_seg))
24eab124 7138 {
d0b47220 7139 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 7140 ret = 0;
24eab124 7141 }
252b5132 7142#endif
3956db08 7143
40fb9820
L		 7144 /* Check if this is a displacement only operand. */
7145 bigdisp = i.types[this_operand];
7146 bigdisp.bitfield.disp8 = 0;
7147 bigdisp.bitfield.disp16 = 0;
7148 bigdisp.bitfield.disp32 = 0;
7149 bigdisp.bitfield.disp32s = 0;
7150 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 7151 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 7152 i.types[this_operand] = operand_type_and (i.types[this_operand],
7153 types);
3956db08 7154
3992d3b7 7155 return ret;
252b5132
RH		 7156}
7157
eecb386c 7158/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 7159 Return 1 on success, 0 on a failure. */
7160
252b5132 7161static int
e3bb37b5 7162i386_index_check (const char *operand_string)
252b5132 7163{
3e73aa7c 7164 int ok;
fc0763e6 7165 const char *kind = "base/index";
24eab124 7166#if INFER_ADDR_PREFIX
eecb386c
AM		 7167 int fudged = 0;
7168
24eab124
AM		 7169 tryprefix:
7170#endif
3e73aa7c 7171 ok = 1;
fc0763e6
JB		 7172 if (current_templates->start->opcode_modifier.isstring
7173 && !current_templates->start->opcode_modifier.immext
7174 && (current_templates->end[-1].opcode_modifier.isstring
7175 || i.mem_operands))
7176 {
7177 /* Memory operands of string insns are special in that they only allow
7178 a single register (rDI, rSI, or rBX) as their memory address. */
7179 unsigned int expected;
7180
7181 kind = "string address";
7182
7183 if (current_templates->start->opcode_modifier.w)
7184 {
7185 i386_operand_type type = current_templates->end[-1].operand_types[0];
7186
7187 if (!type.bitfield.baseindex
7188 || ((!i.mem_operands != !intel_syntax)
7189 && current_templates->end[-1].operand_types[1]
7190 .bitfield.baseindex))
7191 type = current_templates->end[-1].operand_types[1];
7192 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
7193 }
7194 else
7195 expected = 3 /* rBX */;
7196
7197 if (!i.base_reg || i.index_reg
7198 || operand_type_check (i.types[this_operand], disp))
7199 ok = -1;
7200 else if (!(flag_code == CODE_64BIT
7201 ? i.prefix[ADDR_PREFIX]
7202 ? i.base_reg->reg_type.bitfield.reg32
7203 : i.base_reg->reg_type.bitfield.reg64
7204 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7205 ? i.base_reg->reg_type.bitfield.reg32
7206 : i.base_reg->reg_type.bitfield.reg16))
7207 ok = 0;
7208 else if (i.base_reg->reg_num != expected)
7209 ok = -1;
7210
7211 if (ok < 0)
7212 {
7213 unsigned int j;
7214
7215 for (j = 0; j < i386_regtab_size; ++j)
7216 if ((flag_code == CODE_64BIT
7217 ? i.prefix[ADDR_PREFIX]
7218 ? i386_regtab[j].reg_type.bitfield.reg32
7219 : i386_regtab[j].reg_type.bitfield.reg64
7220 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7221 ? i386_regtab[j].reg_type.bitfield.reg32
7222 : i386_regtab[j].reg_type.bitfield.reg16)
7223 && i386_regtab[j].reg_num == expected)
7224 break;
9c2799c2 7225 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7226 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7227 operand_string,
7228 intel_syntax ? '[' : '(',
7229 register_prefix,
7230 i386_regtab[j].reg_name,
7231 intel_syntax ? ']' : ')');
7232 ok = 1;
7233 }
7234 }
7235 else if (flag_code == CODE_64BIT)
64e74474 7236 {
64e74474 7237 if ((i.base_reg
40fb9820
L		 7238 && ((i.prefix[ADDR_PREFIX] == 0
7239 && !i.base_reg->reg_type.bitfield.reg64)
7240 || (i.prefix[ADDR_PREFIX]
7241 && !i.base_reg->reg_type.bitfield.reg32))
7242 && (i.index_reg
9a04903e
JB		 7243 || i.base_reg->reg_num !=
7244 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7245 || (i.index_reg
6c30d220
L		 7246 && !(i.index_reg->reg_type.bitfield.regxmm
7247 || i.index_reg->reg_type.bitfield.regymm)
40fb9820
L		 7248 && (!i.index_reg->reg_type.bitfield.baseindex
7249 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7250 && i.index_reg->reg_num != RegRiz
7251 && !i.index_reg->reg_type.bitfield.reg64
7252 )
40fb9820 7253 || (i.prefix[ADDR_PREFIX]
db51cc60 7254 && i.index_reg->reg_num != RegEiz
40fb9820 7255 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7256 ok = 0;
3e73aa7c
JH		 7257 }
7258 else
7259 {
7260 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7261 {
7262 /* 16bit checks. */
7263 if ((i.base_reg
40fb9820
L		 7264 && (!i.base_reg->reg_type.bitfield.reg16
7265 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7266 || (i.index_reg
40fb9820
L		 7267 && (!i.index_reg->reg_type.bitfield.reg16
7268 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7269 || !(i.base_reg
7270 && i.base_reg->reg_num < 6
7271 && i.index_reg->reg_num >= 6
7272 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7273 ok = 0;
7274 }
7275 else
e5cb08ac 7276 {
3e73aa7c
JH		 7277 /* 32bit checks. */
7278 if ((i.base_reg
40fb9820 7279 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7280 || (i.index_reg
6c30d220
L		 7281 && !i.index_reg->reg_type.bitfield.regxmm
7282 && !i.index_reg->reg_type.bitfield.regymm
db51cc60
L		 7283 && ((!i.index_reg->reg_type.bitfield.reg32
7284 && i.index_reg->reg_num != RegEiz)
40fb9820 7285 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7286 ok = 0;
3e73aa7c
JH		 7287 }
7288 }
7289 if (!ok)
24eab124
AM		 7290 {
7291#if INFER_ADDR_PREFIX
fc0763e6 7292 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7293 {
7294 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7295 i.prefixes += 1;
b23bac36
AM		 7296 /* Change the size of any displacement too. At most one of
7297 Disp16 or Disp32 is set.
7298 FIXME. There doesn't seem to be any real need for separate
7299 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7300 Removing them would probably clean up the code quite a lot. */
4eed87de 7301 if (flag_code != CODE_64BIT
40fb9820
L		 7302 && (i.types[this_operand].bitfield.disp16
7303 || i.types[this_operand].bitfield.disp32))
7304 i.types[this_operand]
c6fb90c8 7305 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7306 fudged = 1;
24eab124
AM		 7307 goto tryprefix;
7308 }
eecb386c 7309 if (fudged)
fc0763e6
JB		 7310 as_bad (_("`%s' is not a valid %s expression"),
7311 operand_string,
7312 kind);
eecb386c 7313 else
c388dee8 7314#endif
fc0763e6 7315 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7316 operand_string,
fc0763e6
JB		 7317 flag_code_names[i.prefix[ADDR_PREFIX]
7318 ? flag_code == CODE_32BIT
7319 ? CODE_16BIT
7320 : CODE_32BIT
7321 : flag_code],
7322 kind);
24eab124 7323 }
20f0a1fc 7324 return ok;
24eab124 7325}
252b5132 7326
fc0763e6 7327/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7328 on error. */
252b5132 7329
252b5132 7330static int
a7619375 7331i386_att_operand (char *operand_string)
252b5132 7332{
af6bdddf
AM		 7333 const reg_entry *r;
7334 char *end_op;
24eab124 7335 char *op_string = operand_string;
252b5132 7336
24eab124 7337 if (is_space_char (*op_string))
252b5132
RH		 7338 ++op_string;
7339
24eab124 7340 /* We check for an absolute prefix (differentiating,
47926f60 7341 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7342 if (*op_string == ABSOLUTE_PREFIX)
7343 {
7344 ++op_string;
7345 if (is_space_char (*op_string))
7346 ++op_string;
40fb9820 7347 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7348 }
252b5132 7349
47926f60 7350 /* Check if operand is a register. */
4d1bb795 7351 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7352 {
40fb9820
L		 7353 i386_operand_type temp;
7354
24eab124
AM		 7355 /* Check for a segment override by searching for ':' after a
7356 segment register. */
7357 op_string = end_op;
7358 if (is_space_char (*op_string))
7359 ++op_string;
40fb9820
L		 7360 if (*op_string == ':'
7361 && (r->reg_type.bitfield.sreg2
7362 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7363 {
7364 switch (r->reg_num)
7365 {
7366 case 0:
7367 i.seg[i.mem_operands] = &es;
7368 break;
7369 case 1:
7370 i.seg[i.mem_operands] = &cs;
7371 break;
7372 case 2:
7373 i.seg[i.mem_operands] = &ss;
7374 break;
7375 case 3:
7376 i.seg[i.mem_operands] = &ds;
7377 break;
7378 case 4:
7379 i.seg[i.mem_operands] = &fs;
7380 break;
7381 case 5:
7382 i.seg[i.mem_operands] = &gs;
7383 break;
7384 }
252b5132 7385
24eab124 7386 /* Skip the ':' and whitespace. */
252b5132
RH		 7387 ++op_string;
7388 if (is_space_char (*op_string))
24eab124 7389 ++op_string;
252b5132 7390
24eab124
AM		 7391 if (!is_digit_char (*op_string)
7392 && !is_identifier_char (*op_string)
7393 && *op_string != '('
7394 && *op_string != ABSOLUTE_PREFIX)
7395 {
7396 as_bad (_("bad memory operand `%s'"), op_string);
7397 return 0;
7398 }
47926f60 7399 /* Handle case of %es:*foo. */
24eab124
AM		 7400 if (*op_string == ABSOLUTE_PREFIX)
7401 {
7402 ++op_string;
7403 if (is_space_char (*op_string))
7404 ++op_string;
40fb9820 7405 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7406 }
7407 goto do_memory_reference;
7408 }
7409 if (*op_string)
7410 {
d0b47220 7411 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7412 return 0;
7413 }
40fb9820
L		 7414 temp = r->reg_type;
7415 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7416 i.types[this_operand] = operand_type_or (i.types[this_operand],
7417 temp);
7d5e4556 7418 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7419 i.op[this_operand].regs = r;
24eab124
AM		 7420 i.reg_operands++;
7421 }
af6bdddf
AM		 7422 else if (*op_string == REGISTER_PREFIX)
7423 {
7424 as_bad (_("bad register name `%s'"), op_string);
7425 return 0;
7426 }
24eab124 7427 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7428 {
24eab124 7429 ++op_string;
40fb9820 7430 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7431 {
d0b47220 7432 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7433 return 0;
7434 }
7435 if (!i386_immediate (op_string))
7436 return 0;
7437 }
7438 else if (is_digit_char (*op_string)
7439 || is_identifier_char (*op_string)
e5cb08ac 7440 || *op_string == '(')
24eab124 7441 {
47926f60 7442 /* This is a memory reference of some sort. */
af6bdddf 7443 char *base_string;
252b5132 7444
47926f60 7445 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7446 char *displacement_string_start;
7447 char *displacement_string_end;
252b5132 7448
24eab124 7449 do_memory_reference:
24eab124 7450 if ((i.mem_operands == 1
40fb9820 7451 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7452 || i.mem_operands == 2)
7453 {
7454 as_bad (_("too many memory references for `%s'"),
7455 current_templates->start->name);
7456 return 0;
7457 }
252b5132 7458
24eab124
AM		 7459 /* Check for base index form. We detect the base index form by
7460 looking for an ')' at the end of the operand, searching
7461 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7462 after the '('. */
af6bdddf 7463 base_string = op_string + strlen (op_string);
c3332e24 7464
af6bdddf
AM		 7465 --base_string;
7466 if (is_space_char (*base_string))
7467 --base_string;
252b5132 7468
47926f60 7469 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7470 displacement_string_start = op_string;
7471 displacement_string_end = base_string + 1;
252b5132 7472
24eab124
AM		 7473 if (*base_string == ')')
7474 {
af6bdddf 7475 char *temp_string;
24eab124
AM		 7476 unsigned int parens_balanced = 1;
7477 /* We've already checked that the number of left & right ()'s are
47926f60 7478 equal, so this loop will not be infinite. */
24eab124
AM		 7479 do
7480 {
7481 base_string--;
7482 if (*base_string == ')')
7483 parens_balanced++;
7484 if (*base_string == '(')
7485 parens_balanced--;
7486 }
7487 while (parens_balanced);
c3332e24 7488
af6bdddf 7489 temp_string = base_string;
c3332e24 7490
24eab124 7491 /* Skip past '(' and whitespace. */
252b5132
RH		 7492 ++base_string;
7493 if (is_space_char (*base_string))
24eab124 7494 ++base_string;
252b5132 7495
af6bdddf 7496 if (*base_string == ','
4eed87de
AM		 7497 || ((i.base_reg = parse_register (base_string, &end_op))
7498 != NULL))
252b5132 7499 {
af6bdddf 7500 displacement_string_end = temp_string;
252b5132 7501
40fb9820 7502 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7503
af6bdddf 7504 if (i.base_reg)
24eab124 7505 {
24eab124
AM		 7506 base_string = end_op;
7507 if (is_space_char (*base_string))
7508 ++base_string;
af6bdddf
AM		 7509 }
7510
7511 /* There may be an index reg or scale factor here. */
7512 if (*base_string == ',')
7513 {
7514 ++base_string;
7515 if (is_space_char (*base_string))
7516 ++base_string;
7517
4eed87de
AM		 7518 if ((i.index_reg = parse_register (base_string, &end_op))
7519 != NULL)
24eab124 7520 {
af6bdddf 7521 base_string = end_op;
24eab124
AM		 7522 if (is_space_char (*base_string))
7523 ++base_string;
af6bdddf
AM		 7524 if (*base_string == ',')
7525 {
7526 ++base_string;
7527 if (is_space_char (*base_string))
7528 ++base_string;
7529 }
e5cb08ac 7530 else if (*base_string != ')')
af6bdddf 7531 {
4eed87de
AM		 7532 as_bad (_("expecting `,' or `)' "
7533 "after index register in `%s'"),
af6bdddf
AM		 7534 operand_string);
7535 return 0;
7536 }
24eab124 7537 }
af6bdddf 7538 else if (*base_string == REGISTER_PREFIX)
24eab124 7539 {
af6bdddf 7540 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7541 return 0;
7542 }
252b5132 7543
47926f60 7544 /* Check for scale factor. */
551c1ca1 7545 if (*base_string != ')')
af6bdddf 7546 {
551c1ca1
AM		 7547 char *end_scale = i386_scale (base_string);
7548
7549 if (!end_scale)
af6bdddf 7550 return 0;
24eab124 7551
551c1ca1 7552 base_string = end_scale;
af6bdddf
AM		 7553 if (is_space_char (*base_string))
7554 ++base_string;
7555 if (*base_string != ')')
7556 {
4eed87de
AM		 7557 as_bad (_("expecting `)' "
7558 "after scale factor in `%s'"),
af6bdddf
AM		 7559 operand_string);
7560 return 0;
7561 }
7562 }
7563 else if (!i.index_reg)
24eab124 7564 {
4eed87de
AM		 7565 as_bad (_("expecting index register or scale factor "
7566 "after `,'; got '%c'"),
af6bdddf 7567 *base_string);
24eab124
AM		 7568 return 0;
7569 }
7570 }
af6bdddf 7571 else if (*base_string != ')')
24eab124 7572 {
4eed87de
AM		 7573 as_bad (_("expecting `,' or `)' "
7574 "after base register in `%s'"),
af6bdddf 7575 operand_string);
24eab124
AM		 7576 return 0;
7577 }
c3332e24 7578 }
af6bdddf 7579 else if (*base_string == REGISTER_PREFIX)
c3332e24 7580 {
af6bdddf 7581 as_bad (_("bad register name `%s'"), base_string);
24eab124 7582 return 0;
c3332e24 7583 }
24eab124
AM		 7584 }
7585
7586 /* If there's an expression beginning the operand, parse it,
7587 assuming displacement_string_start and
7588 displacement_string_end are meaningful. */
7589 if (displacement_string_start != displacement_string_end)
7590 {
7591 if (!i386_displacement (displacement_string_start,
7592 displacement_string_end))
7593 return 0;
7594 }
7595
7596 /* Special case for (%dx) while doing input/output op. */
7597 if (i.base_reg
0dfbf9d7
L		 7598 && operand_type_equal (&i.base_reg->reg_type,
7599 &reg16_inoutportreg)
24eab124
AM		 7600 && i.index_reg == 0
7601 && i.log2_scale_factor == 0
7602 && i.seg[i.mem_operands] == 0
40fb9820 7603 && !operand_type_check (i.types[this_operand], disp))
24eab124 7604 {
65da13b5 7605 i.types[this_operand] = inoutportreg;
24eab124
AM		 7606 return 1;
7607 }
7608
eecb386c
AM		 7609 if (i386_index_check (operand_string) == 0)
7610 return 0;
5c07affc 7611 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7612 i.mem_operands++;
7613 }
7614 else
ce8a8b2f
AM		 7615 {
7616 /* It's not a memory operand; argh! */
24eab124
AM		 7617 as_bad (_("invalid char %s beginning operand %d `%s'"),
7618 output_invalid (*op_string),
7619 this_operand + 1,
7620 op_string);
7621 return 0;
7622 }
47926f60 7623 return 1; /* Normal return. */
252b5132
RH		 7624}
7625\f
ee7fcc42
AM		 7626/* md_estimate_size_before_relax()
7627
7628 Called just before relax() for rs_machine_dependent frags. The x86
7629 assembler uses these frags to handle variable size jump
7630 instructions.
7631
7632 Any symbol that is now undefined will not become defined.
7633 Return the correct fr_subtype in the frag.
7634 Return the initial "guess for variable size of frag" to caller.
7635 The guess is actually the growth beyond the fixed part. Whatever
7636 we do to grow the fixed or variable part contributes to our
7637 returned value. */
7638
252b5132 7639int
7016a5d5 7640md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 7641{
252b5132 7642 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7643 check for un-relaxable symbols. On an ELF system, we can't relax
7644 an externally visible symbol, because it may be overridden by a
7645 shared library. */
7646 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7647#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7648 || (IS_ELF
31312f95 7649 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7650 || S_IS_WEAK (fragP->fr_symbol)
7651 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7652 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7653#endif
7654#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7655 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7656 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7657#endif
7658 )
252b5132 7659 {
b98ef147
AM		 7660 /* Symbol is undefined in this segment, or we need to keep a
7661 reloc so that weak symbols can be overridden. */
7662 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7663 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7664 unsigned char *opcode;
7665 int old_fr_fix;
f6af82bd 7666
ee7fcc42 7667 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7668 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7669 else if (size == 2)
f6af82bd
AM		 7670 reloc_type = BFD_RELOC_16_PCREL;
7671 else
7672 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7673
ee7fcc42
AM		 7674 old_fr_fix = fragP->fr_fix;
7675 opcode = (unsigned char *) fragP->fr_opcode;
7676
fddf5b5b 7677 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7678 {
fddf5b5b
AM		 7679 case UNCOND_JUMP:
7680 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7681 opcode[0] = 0xe9;
252b5132 7682 fragP->fr_fix += size;
062cd5e7
AS		 7683 fix_new (fragP, old_fr_fix, size,
7684 fragP->fr_symbol,
7685 fragP->fr_offset, 1,
7686 reloc_type);
252b5132
RH		 7687 break;
7688
fddf5b5b 7689 case COND_JUMP86:
412167cb
AM		 7690 if (size == 2
7691 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7692 {
7693 /* Negate the condition, and branch past an
7694 unconditional jump. */
7695 opcode[0] ^= 1;
7696 opcode[1] = 3;
7697 /* Insert an unconditional jump. */
7698 opcode[2] = 0xe9;
7699 /* We added two extra opcode bytes, and have a two byte
7700 offset. */
7701 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7702 fix_new (fragP, old_fr_fix + 2, 2,
7703 fragP->fr_symbol,
7704 fragP->fr_offset, 1,
7705 reloc_type);
fddf5b5b
AM		 7706 break;
7707 }
7708 /* Fall through. */
7709
7710 case COND_JUMP:
412167cb
AM		 7711 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7712 {
3e02c1cc
AM		 7713 fixS *fixP;
7714
412167cb 7715 fragP->fr_fix += 1;
3e02c1cc
AM		 7716 fixP = fix_new (fragP, old_fr_fix, 1,
7717 fragP->fr_symbol,
7718 fragP->fr_offset, 1,
7719 BFD_RELOC_8_PCREL);
7720 fixP->fx_signed = 1;
412167cb
AM		 7721 break;
7722 }
93c2a809 7723
24eab124 7724 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7725 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7726 opcode[1] = opcode[0] + 0x10;
f6af82bd 7727 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7728 /* We've added an opcode byte. */
7729 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7730 fix_new (fragP, old_fr_fix + 1, size,
7731 fragP->fr_symbol,
7732 fragP->fr_offset, 1,
7733 reloc_type);
252b5132 7734 break;
fddf5b5b
AM		 7735
7736 default:
7737 BAD_CASE (fragP->fr_subtype);
7738 break;
252b5132
RH		 7739 }
7740 frag_wane (fragP);
ee7fcc42 7741 return fragP->fr_fix - old_fr_fix;
252b5132 7742 }
93c2a809 7743
93c2a809
AM		 7744 /* Guess size depending on current relax state. Initially the relax
7745 state will correspond to a short jump and we return 1, because
7746 the variable part of the frag (the branch offset) is one byte
7747 long. However, we can relax a section more than once and in that
7748 case we must either set fr_subtype back to the unrelaxed state,
7749 or return the value for the appropriate branch. */
7750 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7751}
7752
47926f60
KH		 7753/* Called after relax() is finished.
7754
7755 In: Address of frag.
7756 fr_type == rs_machine_dependent.
7757 fr_subtype is what the address relaxed to.
7758
7759 Out: Any fixSs and constants are set up.
7760 Caller will turn frag into a ".space 0". */
7761
252b5132 7762void
7016a5d5
TG		 7763md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
7764 fragS *fragP)
252b5132 7765{
29b0f896 7766 unsigned char *opcode;
252b5132 7767 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7768 offsetT target_address;
7769 offsetT opcode_address;
252b5132 7770 unsigned int extension = 0;
847f7ad4 7771 offsetT displacement_from_opcode_start;
252b5132
RH		 7772
7773 opcode = (unsigned char *) fragP->fr_opcode;
7774
47926f60 7775 /* Address we want to reach in file space. */
252b5132 7776 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7777
47926f60 7778 /* Address opcode resides at in file space. */
252b5132
RH		 7779 opcode_address = fragP->fr_address + fragP->fr_fix;
7780
47926f60 7781 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7782 displacement_from_opcode_start = target_address - opcode_address;
7783
fddf5b5b 7784 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7785 {
47926f60
KH		 7786 /* Don't have to change opcode. */
7787 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7788 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7789 }
7790 else
7791 {
7792 if (no_cond_jump_promotion
7793 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7794 as_warn_where (fragP->fr_file, fragP->fr_line,
7795 _("long jump required"));
252b5132 7796
fddf5b5b
AM		 7797 switch (fragP->fr_subtype)
7798 {
7799 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7800 extension = 4; /* 1 opcode + 4 displacement */
7801 opcode[0] = 0xe9;
7802 where_to_put_displacement = &opcode[1];
7803 break;
252b5132 7804
fddf5b5b
AM		 7805 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7806 extension = 2; /* 1 opcode + 2 displacement */
7807 opcode[0] = 0xe9;
7808 where_to_put_displacement = &opcode[1];
7809 break;
252b5132 7810
fddf5b5b
AM		 7811 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7812 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7813 extension = 5; /* 2 opcode + 4 displacement */
7814 opcode[1] = opcode[0] + 0x10;
7815 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7816 where_to_put_displacement = &opcode[2];
7817 break;
252b5132 7818
fddf5b5b
AM		 7819 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7820 extension = 3; /* 2 opcode + 2 displacement */
7821 opcode[1] = opcode[0] + 0x10;
7822 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7823 where_to_put_displacement = &opcode[2];
7824 break;
252b5132 7825
fddf5b5b
AM		 7826 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7827 extension = 4;
7828 opcode[0] ^= 1;
7829 opcode[1] = 3;
7830 opcode[2] = 0xe9;
7831 where_to_put_displacement = &opcode[3];
7832 break;
7833
7834 default:
7835 BAD_CASE (fragP->fr_subtype);
7836 break;
7837 }
252b5132 7838 }
fddf5b5b 7839
7b81dfbb
AJ		 7840 /* If size if less then four we are sure that the operand fits,
7841 but if it's 4, then it could be that the displacement is larger
7842 then -/+ 2GB. */
7843 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7844 && object_64bit
7845 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7846 + ((addressT) 1 << 31))
7847 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7848 {
7849 as_bad_where (fragP->fr_file, fragP->fr_line,
7850 _("jump target out of range"));
7851 /* Make us emit 0. */
7852 displacement_from_opcode_start = extension;
7853 }
47926f60 7854 /* Now put displacement after opcode. */
252b5132
RH		 7855 md_number_to_chars ((char *) where_to_put_displacement,
7856 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7857 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7858 fragP->fr_fix += extension;
7859}
7860\f
7016a5d5 7861/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 7862 by our caller that we have all the info we need to fix it up.
7863
7016a5d5
TG		 7864 Parameter valP is the pointer to the value of the bits.
7865
252b5132
RH		 7866 On the 386, immediates, displacements, and data pointers are all in
7867 the same (little-endian) format, so we don't need to care about which
7868 we are handling. */
7869
94f592af 7870void
7016a5d5 7871md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 7872{
94f592af 7873 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7874 valueT value = *valP;
252b5132 7875
f86103b7 7876#if !defined (TE_Mach)
93382f6d
AM		 7877 if (fixP->fx_pcrel)
7878 {
7879 switch (fixP->fx_r_type)
7880 {
5865bb77
ILT		 7881 default:
7882 break;
7883
d6ab8113
JB		 7884 case BFD_RELOC_64:
7885 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7886 break;
93382f6d 7887 case BFD_RELOC_32:
ae8887b5 7888 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7889 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7890 break;
7891 case BFD_RELOC_16:
7892 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7893 break;
7894 case BFD_RELOC_8:
7895 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7896 break;
7897 }
7898 }
252b5132 7899
a161fe53 7900 if (fixP->fx_addsy != NULL
31312f95 7901 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7902 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7903 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7904 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7905 && !use_rela_relocations)
252b5132 7906 {
31312f95
AM		 7907 /* This is a hack. There should be a better way to handle this.
7908 This covers for the fact that bfd_install_relocation will
7909 subtract the current location (for partial_inplace, PC relative
7910 relocations); see more below. */
252b5132 7911#ifndef OBJ_AOUT
718ddfc0 7912 if (IS_ELF
252b5132
RH		 7913#ifdef TE_PE
7914 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7915#endif
7916 )
7917 value += fixP->fx_where + fixP->fx_frag->fr_address;
7918#endif
7919#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7920 if (IS_ELF)
252b5132 7921 {
6539b54b 7922 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7923
6539b54b 7924 if ((sym_seg == seg
2f66722d 7925 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7926 && sym_seg != absolute_section))
af65af87 7927 && !generic_force_reloc (fixP))
2f66722d
AM		 7928 {
7929 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7930 bfd_install_relocation subtracts them out again. I think
7931 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7932 it. FIXME. */
7933 value += fixP->fx_where + fixP->fx_frag->fr_address;
7934 }
252b5132
RH		 7935 }
7936#endif
7937#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7938 /* For some reason, the PE format does not store a
7939 section address offset for a PC relative symbol. */
7940 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7941 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7942 value += md_pcrel_from (fixP);
7943#endif
7944 }
fbeb56a4
DK		 7945#if defined (OBJ_COFF) && defined (TE_PE)
7946 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7947 {
7948 value -= S_GET_VALUE (fixP->fx_addsy);
7949 }
7950#endif
252b5132
RH		 7951
7952 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7953 and we must not disappoint it. */
252b5132 7954#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7955 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7956 switch (fixP->fx_r_type)
7957 {
7958 case BFD_RELOC_386_PLT32:
3e73aa7c 7959 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7960 /* Make the jump instruction point to the address of the operand. At
7961 runtime we merely add the offset to the actual PLT entry. */
7962 value = -4;
7963 break;
31312f95 7964
13ae64f3
JJ		 7965 case BFD_RELOC_386_TLS_GD:
7966 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7967 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7968 case BFD_RELOC_386_TLS_IE:
7969 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7970 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7971 case BFD_RELOC_X86_64_TLSGD:
7972 case BFD_RELOC_X86_64_TLSLD:
7973 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7974 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7975 value = 0; /* Fully resolved at runtime. No addend. */
7976 /* Fallthrough */
7977 case BFD_RELOC_386_TLS_LE:
7978 case BFD_RELOC_386_TLS_LDO_32:
7979 case BFD_RELOC_386_TLS_LE_32:
7980 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7981 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7982 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7983 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7984 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7985 break;
7986
67a4f2b7
AO		 7987 case BFD_RELOC_386_TLS_DESC_CALL:
7988 case BFD_RELOC_X86_64_TLSDESC_CALL:
7989 value = 0; /* Fully resolved at runtime. No addend. */
7990 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7991 fixP->fx_done = 0;
7992 return;
7993
00f7efb6
JJ		 7994 case BFD_RELOC_386_GOT32:
7995 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7996 value = 0; /* Fully resolved at runtime. No addend. */
7997 break;
47926f60
KH		 7998
7999 case BFD_RELOC_VTABLE_INHERIT:
8000 case BFD_RELOC_VTABLE_ENTRY:
8001 fixP->fx_done = 0;
94f592af 8002 return;
47926f60
KH		 8003
8004 default:
8005 break;
8006 }
8007#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 8008 *valP = value;
f86103b7 8009#endif /* !defined (TE_Mach) */
3e73aa7c 8010
3e73aa7c 8011 /* Are we finished with this relocation now? */
c6682705 8012 if (fixP->fx_addsy == NULL)
3e73aa7c 8013 fixP->fx_done = 1;
fbeb56a4
DK		 8014#if defined (OBJ_COFF) && defined (TE_PE)
8015 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
8016 {
8017 fixP->fx_done = 0;
8018 /* Remember value for tc_gen_reloc. */
8019 fixP->fx_addnumber = value;
8020 /* Clear out the frag for now. */
8021 value = 0;
8022 }
8023#endif
3e73aa7c
JH		 8024 else if (use_rela_relocations)
8025 {
8026 fixP->fx_no_overflow = 1;
062cd5e7
AS		 8027 /* Remember value for tc_gen_reloc. */
8028 fixP->fx_addnumber = value;
3e73aa7c
JH		 8029 value = 0;
8030 }
f86103b7 8031
94f592af 8032 md_number_to_chars (p, value, fixP->fx_size);
252b5132 8033}
252b5132 8034\f
252b5132 8035char *
499ac353 8036md_atof (int type, char *litP, int *sizeP)
252b5132 8037{
499ac353
NC		 8038 /* This outputs the LITTLENUMs in REVERSE order;
8039 in accord with the bigendian 386. */
8040 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 8041}
8042\f
2d545b82 8043static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 8044
252b5132 8045static char *
e3bb37b5 8046output_invalid (int c)
252b5132 8047{
3882b010 8048 if (ISPRINT (c))
f9f21a03
L		 8049 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
8050 "'%c'", c);
252b5132 8051 else
f9f21a03 8052 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 8053 "(0x%x)", (unsigned char) c);
252b5132
RH		 8054 return output_invalid_buf;
8055}
8056
af6bdddf 8057/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 8058
8059static const reg_entry *
4d1bb795 8060parse_real_register (char *reg_string, char **end_op)
252b5132 8061{
af6bdddf
AM		 8062 char *s = reg_string;
8063 char *p;
252b5132
RH		 8064 char reg_name_given[MAX_REG_NAME_SIZE + 1];
8065 const reg_entry *r;
8066
8067 /* Skip possible REGISTER_PREFIX and possible whitespace. */
8068 if (*s == REGISTER_PREFIX)
8069 ++s;
8070
8071 if (is_space_char (*s))
8072 ++s;
8073
8074 p = reg_name_given;
af6bdddf 8075 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 8076 {
8077 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 8078 return (const reg_entry *) NULL;
8079 s++;
252b5132
RH		 8080 }
8081
6588847e
DN		 8082 /* For naked regs, make sure that we are not dealing with an identifier.
8083 This prevents confusing an identifier like `eax_var' with register
8084 `eax'. */
8085 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
8086 return (const reg_entry *) NULL;
8087
af6bdddf 8088 *end_op = s;
252b5132
RH		 8089
8090 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
8091
5f47d35b 8092 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 8093 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 8094 {
5f47d35b
AM		 8095 if (is_space_char (*s))
8096 ++s;
8097 if (*s == '(')
8098 {
af6bdddf 8099 ++s;
5f47d35b
AM		 8100 if (is_space_char (*s))
8101 ++s;
8102 if (*s >= '0' && *s <= '7')
8103 {
db557034 8104 int fpr = *s - '0';
af6bdddf 8105 ++s;
5f47d35b
AM		 8106 if (is_space_char (*s))
8107 ++s;
8108 if (*s == ')')
8109 {
8110 *end_op = s + 1;
1e9cc1c2 8111 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 8112 know (r);
8113 return r + fpr;
5f47d35b 8114 }
5f47d35b 8115 }
47926f60 8116 /* We have "%st(" then garbage. */
5f47d35b
AM		 8117 return (const reg_entry *) NULL;
8118 }
8119 }
8120
a60de03c
JB		 8121 if (r == NULL || allow_pseudo_reg)
8122 return r;
8123
0dfbf9d7 8124 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 8125 return (const reg_entry *) NULL;
8126
192dc9c6
JB		 8127 if ((r->reg_type.bitfield.reg32
8128 || r->reg_type.bitfield.sreg3
8129 || r->reg_type.bitfield.control
8130 || r->reg_type.bitfield.debug
8131 || r->reg_type.bitfield.test)
8132 && !cpu_arch_flags.bitfield.cpui386)
8133 return (const reg_entry *) NULL;
8134
309d3373
JB		 8135 if (r->reg_type.bitfield.floatreg
8136 && !cpu_arch_flags.bitfield.cpu8087
8137 && !cpu_arch_flags.bitfield.cpu287
8138 && !cpu_arch_flags.bitfield.cpu387)
8139 return (const reg_entry *) NULL;
8140
192dc9c6
JB		 8141 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
8142 return (const reg_entry *) NULL;
8143
8144 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
8145 return (const reg_entry *) NULL;
8146
40f12533
L		 8147 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
8148 return (const reg_entry *) NULL;
8149
db51cc60 8150 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 8151 if (!allow_index_reg
db51cc60
L		 8152 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
8153 return (const reg_entry *) NULL;
8154
a60de03c
JB		 8155 if (((r->reg_flags & (RegRex64 | RegRex))
8156 || r->reg_type.bitfield.reg64)
40fb9820 8157 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 8158 || !operand_type_equal (&r->reg_type, &control))
1ae00879 8159 && flag_code != CODE_64BIT)
20f0a1fc 8160 return (const reg_entry *) NULL;
1ae00879 8161
b7240065
JB		 8162 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
8163 return (const reg_entry *) NULL;
8164
252b5132
RH		 8165 return r;
8166}
4d1bb795
JB		 8167
8168/* REG_STRING starts *before* REGISTER_PREFIX. */
8169
8170static const reg_entry *
8171parse_register (char *reg_string, char **end_op)
8172{
8173 const reg_entry *r;
8174
8175 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
8176 r = parse_real_register (reg_string, end_op);
8177 else
8178 r = NULL;
8179 if (!r)
8180 {
8181 char *save = input_line_pointer;
8182 char c;
8183 symbolS *symbolP;
8184
8185 input_line_pointer = reg_string;
8186 c = get_symbol_end ();
8187 symbolP = symbol_find (reg_string);
8188 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
8189 {
8190 const expressionS *e = symbol_get_value_expression (symbolP);
8191
0398aac5 8192 know (e->X_op == O_register);
4eed87de 8193 know (e->X_add_number >= 0
c3fe08fa 8194 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 8195 r = i386_regtab + e->X_add_number;
8196 *end_op = input_line_pointer;
8197 }
8198 *input_line_pointer = c;
8199 input_line_pointer = save;
8200 }
8201 return r;
8202}
8203
8204int
8205i386_parse_name (char *name, expressionS *e, char *nextcharP)
8206{
8207 const reg_entry *r;
8208 char *end = input_line_pointer;
8209
8210 *end = *nextcharP;
8211 r = parse_register (name, &input_line_pointer);
8212 if (r && end <= input_line_pointer)
8213 {
8214 *nextcharP = *input_line_pointer;
8215 *input_line_pointer = 0;
8216 e->X_op = O_register;
8217 e->X_add_number = r - i386_regtab;
8218 return 1;
8219 }
8220 input_line_pointer = end;
8221 *end = 0;
ee86248c 8222 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8223}
8224
8225void
8226md_operand (expressionS *e)
8227{
ee86248c
JB		 8228 char *end;
8229 const reg_entry *r;
4d1bb795 8230
ee86248c
JB		 8231 switch (*input_line_pointer)
8232 {
8233 case REGISTER_PREFIX:
8234 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8235 if (r)
8236 {
8237 e->X_op = O_register;
8238 e->X_add_number = r - i386_regtab;
8239 input_line_pointer = end;
8240 }
ee86248c
JB		 8241 break;
8242
8243 case '[':
9c2799c2 8244 gas_assert (intel_syntax);
ee86248c
JB		 8245 end = input_line_pointer++;
8246 expression (e);
8247 if (*input_line_pointer == ']')
8248 {
8249 ++input_line_pointer;
8250 e->X_op_symbol = make_expr_symbol (e);
8251 e->X_add_symbol = NULL;
8252 e->X_add_number = 0;
8253 e->X_op = O_index;
8254 }
8255 else
8256 {
8257 e->X_op = O_absent;
8258 input_line_pointer = end;
8259 }
8260 break;
4d1bb795
JB		 8261 }
8262}
8263
252b5132 8264\f
4cc782b5 8265#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8266const char *md_shortopts = "kVQ:sqn";
252b5132 8267#else
12b55ccc 8268const char *md_shortopts = "qn";
252b5132 8269#endif
6e0b89ee 8270
3e73aa7c 8271#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8272#define OPTION_64 (OPTION_MD_BASE + 1)
8273#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8274#define OPTION_MARCH (OPTION_MD_BASE + 3)
8275#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8276#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8277#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8278#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8279#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8280#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8281#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8282#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
40a9833c 8283#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
570561f7 8284#define OPTION_X32 (OPTION_MD_BASE + 13)
b3b91714 8285
99ad8390
NC		 8286struct option md_longopts[] =
8287{
3e73aa7c 8288 {"32", no_argument, NULL, OPTION_32},
321098a5 8289#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 8290 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 8291 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 8292#endif
8293#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8294 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 8295#endif
b3b91714 8296 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8297 {"march", required_argument, NULL, OPTION_MARCH},
8298 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8299 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8300 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8301 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8302 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8303 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8304 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8305 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
539f890d 8306 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8307 {NULL, no_argument, NULL, 0}
8308};
8309size_t md_longopts_size = sizeof (md_longopts);
8310
8311int
9103f4f4 8312md_parse_option (int c, char *arg)
252b5132 8313{
91d6fa6a 8314 unsigned int j;
6305a203 8315 char *arch, *next;
9103f4f4 8316
252b5132
RH		 8317 switch (c)
8318 {
12b55ccc
L		 8319 case 'n':
8320 optimize_align_code = 0;
8321 break;
8322
a38cf1db
AM		 8323 case 'q':
8324 quiet_warnings = 1;
252b5132
RH		 8325 break;
8326
8327#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8328 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8329 should be emitted or not. FIXME: Not implemented. */
8330 case 'Q':
252b5132
RH		 8331 break;
8332
8333 /* -V: SVR4 argument to print version ID. */
8334 case 'V':
8335 print_version_id ();
8336 break;
8337
a38cf1db
AM		 8338 /* -k: Ignore for FreeBSD compatibility. */
8339 case 'k':
252b5132 8340 break;
4cc782b5
ILT		 8341
8342 case 's':
8343 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8344 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8345 break;
99ad8390 8346#endif
321098a5 8347#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 8348 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 8349 case OPTION_64:
8350 {
8351 const char **list, **l;
8352
3e73aa7c
JH		 8353 list = bfd_target_list ();
8354 for (l = list; *l != NULL; l++)
8620418b 8355 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8356 || strcmp (*l, "coff-x86-64") == 0
8357 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 8358 || strcmp (*l, "pei-x86-64") == 0
8359 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 8360 {
8361 default_arch = "x86_64";
8362 break;
8363 }
3e73aa7c 8364 if (*l == NULL)
2b5d6a91 8365 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 8366 free (list);
8367 }
8368 break;
8369#endif
252b5132 8370
351f65ca 8371#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8372 case OPTION_X32:
351f65ca
L		 8373 if (IS_ELF)
8374 {
8375 const char **list, **l;
8376
8377 list = bfd_target_list ();
8378 for (l = list; *l != NULL; l++)
8379 if (CONST_STRNEQ (*l, "elf32-x86-64"))
8380 {
8381 default_arch = "x86_64:32";
8382 break;
8383 }
8384 if (*l == NULL)
2b5d6a91 8385 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 8386 free (list);
8387 }
8388 else
8389 as_fatal (_("32bit x86_64 is only supported for ELF"));
8390 break;
8391#endif
8392
6e0b89ee
AM		 8393 case OPTION_32:
8394 default_arch = "i386";
8395 break;
8396
b3b91714
AM		 8397 case OPTION_DIVIDE:
8398#ifdef SVR4_COMMENT_CHARS
8399 {
8400 char *n, *t;
8401 const char *s;
8402
8403 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8404 t = n;
8405 for (s = i386_comment_chars; *s != '\0'; s++)
8406 if (*s != '/')
8407 *t++ = *s;
8408 *t = '\0';
8409 i386_comment_chars = n;
8410 }
8411#endif
8412 break;
8413
9103f4f4 8414 case OPTION_MARCH:
6305a203
L		 8415 arch = xstrdup (arg);
8416 do
9103f4f4 8417 {
6305a203 8418 if (*arch == '.')
2b5d6a91 8419 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8420 next = strchr (arch, '+');
8421 if (next)
8422 *next++ = '\0';
91d6fa6a 8423 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8424 {
91d6fa6a 8425 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8426 {
6305a203 8427 /* Processor. */
1ded5609
JB		 8428 if (! cpu_arch[j].flags.bitfield.cpui386)
8429 continue;
8430
91d6fa6a 8431 cpu_arch_name = cpu_arch[j].name;
6305a203 8432 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8433 cpu_arch_flags = cpu_arch[j].flags;
8434 cpu_arch_isa = cpu_arch[j].type;
8435 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8436 if (!cpu_arch_tune_set)
8437 {
8438 cpu_arch_tune = cpu_arch_isa;
8439 cpu_arch_tune_flags = cpu_arch_isa_flags;
8440 }
8441 break;
8442 }
91d6fa6a
NC		 8443 else if (*cpu_arch [j].name == '.'
8444 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8445 {
8446 /* ISA entension. */
8447 i386_cpu_flags flags;
309d3373 8448
49021df2 8449 if (!cpu_arch[j].negated)
309d3373 8450 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8451 cpu_arch[j].flags);
309d3373
JB		 8452 else
8453 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 8454 cpu_arch[j].flags);
0dfbf9d7 8455 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8456 {
8457 if (cpu_sub_arch_name)
8458 {
8459 char *name = cpu_sub_arch_name;
8460 cpu_sub_arch_name = concat (name,
91d6fa6a 8461 cpu_arch[j].name,
1bf57e9f 8462 (const char *) NULL);
6305a203
L		 8463 free (name);
8464 }
8465 else
91d6fa6a 8466 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 8467 cpu_arch_flags = flags;
a586129e 8468 cpu_arch_isa_flags = flags;
6305a203
L		 8469 }
8470 break;
ccc9c027 8471 }
9103f4f4 8472 }
6305a203 8473
91d6fa6a 8474 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8475 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8476
8477 arch = next;
9103f4f4 8478 }
6305a203 8479 while (next != NULL );
9103f4f4
L		 8480 break;
8481
8482 case OPTION_MTUNE:
8483 if (*arg == '.')
2b5d6a91 8484 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 8485 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8486 {
91d6fa6a 8487 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8488 {
ccc9c027 8489 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8490 cpu_arch_tune = cpu_arch [j].type;
8491 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8492 break;
8493 }
8494 }
91d6fa6a 8495 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8496 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 8497 break;
8498
1efbbeb4
L		 8499 case OPTION_MMNEMONIC:
8500 if (strcasecmp (arg, "att") == 0)
8501 intel_mnemonic = 0;
8502 else if (strcasecmp (arg, "intel") == 0)
8503 intel_mnemonic = 1;
8504 else
2b5d6a91 8505 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 8506 break;
8507
8508 case OPTION_MSYNTAX:
8509 if (strcasecmp (arg, "att") == 0)
8510 intel_syntax = 0;
8511 else if (strcasecmp (arg, "intel") == 0)
8512 intel_syntax = 1;
8513 else
2b5d6a91 8514 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 8515 break;
8516
8517 case OPTION_MINDEX_REG:
8518 allow_index_reg = 1;
8519 break;
8520
8521 case OPTION_MNAKED_REG:
8522 allow_naked_reg = 1;
8523 break;
8524
8525 case OPTION_MOLD_GCC:
8526 old_gcc = 1;
1efbbeb4
L		 8527 break;
8528
c0f3af97
L		 8529 case OPTION_MSSE2AVX:
8530 sse2avx = 1;
8531 break;
8532
daf50ae7
L		 8533 case OPTION_MSSE_CHECK:
8534 if (strcasecmp (arg, "error") == 0)
8535 sse_check = sse_check_error;
8536 else if (strcasecmp (arg, "warning") == 0)
8537 sse_check = sse_check_warning;
8538 else if (strcasecmp (arg, "none") == 0)
8539 sse_check = sse_check_none;
8540 else
2b5d6a91 8541 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 8542 break;
8543
539f890d
L		 8544 case OPTION_MAVXSCALAR:
8545 if (strcasecmp (arg, "128") == 0)
8546 avxscalar = vex128;
8547 else if (strcasecmp (arg, "256") == 0)
8548 avxscalar = vex256;
8549 else
2b5d6a91 8550 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 8551 break;
8552
252b5132
RH		 8553 default:
8554 return 0;
8555 }
8556 return 1;
8557}
8558
8a2c8fef
L		 8559#define MESSAGE_TEMPLATE \
8560" "
8561
8562static void
1ded5609 8563show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8564{
8565 static char message[] = MESSAGE_TEMPLATE;
8566 char *start = message + 27;
8567 char *p;
8568 int size = sizeof (MESSAGE_TEMPLATE);
8569 int left;
8570 const char *name;
8571 int len;
8572 unsigned int j;
8573
8574 p = start;
8575 left = size - (start - message);
8576 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8577 {
8578 /* Should it be skipped? */
8579 if (cpu_arch [j].skip)
8580 continue;
8581
8582 name = cpu_arch [j].name;
8583 len = cpu_arch [j].len;
8584 if (*name == '.')
8585 {
8586 /* It is an extension. Skip if we aren't asked to show it. */
8587 if (ext)
8588 {
8589 name++;
8590 len--;
8591 }
8592 else
8593 continue;
8594 }
8595 else if (ext)
8596 {
8597 /* It is an processor. Skip if we show only extension. */
8598 continue;
8599 }
1ded5609
JB		 8600 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8601 {
8602 /* It is an impossible processor - skip. */
8603 continue;
8604 }
8a2c8fef
L		 8605
8606 /* Reserve 2 spaces for ", " or ",\0" */
8607 left -= len + 2;
8608
8609 /* Check if there is any room. */
8610 if (left >= 0)
8611 {
8612 if (p != start)
8613 {
8614 *p++ = ',';
8615 *p++ = ' ';
8616 }
8617 p = mempcpy (p, name, len);
8618 }
8619 else
8620 {
8621 /* Output the current message now and start a new one. */
8622 *p++ = ',';
8623 *p = '\0';
8624 fprintf (stream, "%s\n", message);
8625 p = start;
8626 left = size - (start - message) - len - 2;
8627
8628 gas_assert (left >= 0);
8629
8630 p = mempcpy (p, name, len);
8631 }
8632 }
8633
8634 *p = '\0';
8635 fprintf (stream, "%s\n", message);
8636}
8637
252b5132 8638void
8a2c8fef 8639md_show_usage (FILE *stream)
252b5132 8640{
4cc782b5
ILT		 8641#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8642 fprintf (stream, _("\
a38cf1db
AM		 8643 -Q ignored\n\
8644 -V print assembler version number\n\
b3b91714
AM		 8645 -k ignored\n"));
8646#endif
8647 fprintf (stream, _("\
12b55ccc 8648 -n Do not optimize code alignment\n\
b3b91714
AM		 8649 -q quieten some warnings\n"));
8650#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8651 fprintf (stream, _("\
a38cf1db 8652 -s ignored\n"));
b3b91714 8653#endif
321098a5
L		 8654#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8655 || defined (TE_PE) || defined (TE_PEP))
751d281c 8656 fprintf (stream, _("\
570561f7 8657 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 8658#endif
b3b91714
AM		 8659#ifdef SVR4_COMMENT_CHARS
8660 fprintf (stream, _("\
8661 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8662#else
8663 fprintf (stream, _("\
b3b91714 8664 --divide ignored\n"));
4cc782b5 8665#endif
9103f4f4 8666 fprintf (stream, _("\
6305a203 8667 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8668 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8669 show_arch (stream, 0, 1);
8a2c8fef
L		 8670 fprintf (stream, _("\
8671 EXTENSION is combination of:\n"));
1ded5609 8672 show_arch (stream, 1, 0);
6305a203 8673 fprintf (stream, _("\
8a2c8fef 8674 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8675 show_arch (stream, 0, 0);
ba104c83 8676 fprintf (stream, _("\
c0f3af97
L		 8677 -msse2avx encode SSE instructions with VEX prefix\n"));
8678 fprintf (stream, _("\
daf50ae7
L		 8679 -msse-check=[none|error|warning]\n\
8680 check SSE instructions\n"));
8681 fprintf (stream, _("\
539f890d
L		 8682 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8683 length\n"));
8684 fprintf (stream, _("\
ba104c83
L		 8685 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8686 fprintf (stream, _("\
8687 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8688 fprintf (stream, _("\
8689 -mindex-reg support pseudo index registers\n"));
8690 fprintf (stream, _("\
8691 -mnaked-reg don't require `%%' prefix for registers\n"));
8692 fprintf (stream, _("\
8693 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8694}
8695
3e73aa7c 8696#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8697 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8698 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8699
8700/* Pick the target format to use. */
8701
47926f60 8702const char *
e3bb37b5 8703i386_target_format (void)
252b5132 8704{
351f65ca
L		 8705 if (!strncmp (default_arch, "x86_64", 6))
8706 {
8707 update_code_flag (CODE_64BIT, 1);
8708 if (default_arch[6] == '\0')
7f56bc95 8709 x86_elf_abi = X86_64_ABI;
351f65ca 8710 else
7f56bc95 8711 x86_elf_abi = X86_64_X32_ABI;
351f65ca 8712 }
3e73aa7c 8713 else if (!strcmp (default_arch, "i386"))
78f12dd3 8714 update_code_flag (CODE_32BIT, 1);
3e73aa7c 8715 else
2b5d6a91 8716 as_fatal (_("unknown architecture"));
89507696
JB		 8717
8718 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8719 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8720 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8721 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8722
252b5132
RH		 8723 switch (OUTPUT_FLAVOR)
8724 {
9384f2ff 8725#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8726 case bfd_target_aout_flavour:
47926f60 8727 return AOUT_TARGET_FORMAT;
4c63da97 8728#endif
9384f2ff
AM		 8729#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8730# if defined (TE_PE) || defined (TE_PEP)
8731 case bfd_target_coff_flavour:
8732 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8733# elif defined (TE_GO32)
0561d57c
JK		 8734 case bfd_target_coff_flavour:
8735 return "coff-go32";
9384f2ff 8736# else
252b5132
RH		 8737 case bfd_target_coff_flavour:
8738 return "coff-i386";
9384f2ff 8739# endif
4c63da97 8740#endif
3e73aa7c 8741#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8742 case bfd_target_elf_flavour:
3e73aa7c 8743 {
351f65ca
L		 8744 const char *format;
8745
8746 switch (x86_elf_abi)
4fa24527 8747 {
351f65ca
L		 8748 default:
8749 format = ELF_TARGET_FORMAT;
8750 break;
7f56bc95 8751 case X86_64_ABI:
351f65ca 8752 use_rela_relocations = 1;
4fa24527 8753 object_64bit = 1;
351f65ca
L		 8754 format = ELF_TARGET_FORMAT64;
8755 break;
7f56bc95 8756 case X86_64_X32_ABI:
4fa24527 8757 use_rela_relocations = 1;
351f65ca 8758 object_64bit = 1;
862be3fb 8759 disallow_64bit_reloc = 1;
351f65ca
L		 8760 format = ELF_TARGET_FORMAT32;
8761 break;
4fa24527 8762 }
3632d14b 8763 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 8764 {
7f56bc95 8765 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 8766 as_fatal (_("Intel L1OM is 64bit only"));
8767 return ELF_TARGET_L1OM_FORMAT;
8768 }
7a9068fe
L		 8769 if (cpu_arch_isa == PROCESSOR_K1OM)
8770 {
8771 if (x86_elf_abi != X86_64_ABI)
8772 as_fatal (_("Intel K1OM is 64bit only"));
8773 return ELF_TARGET_K1OM_FORMAT;
8774 }
8a9036a4 8775 else
351f65ca 8776 return format;
3e73aa7c 8777 }
e57f8c65
TG		 8778#endif
8779#if defined (OBJ_MACH_O)
8780 case bfd_target_mach_o_flavour:
d382c579
TG		 8781 if (flag_code == CODE_64BIT)
8782 {
8783 use_rela_relocations = 1;
8784 object_64bit = 1;
8785 return "mach-o-x86-64";
8786 }
8787 else
8788 return "mach-o-i386";
4c63da97 8789#endif
252b5132
RH		 8790 default:
8791 abort ();
8792 return NULL;
8793 }
8794}
8795
47926f60 8796#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8797
8798#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8799void
8800i386_elf_emit_arch_note (void)
a847613f 8801{
718ddfc0 8802 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8803 {
8804 char *p;
8805 asection *seg = now_seg;
8806 subsegT subseg = now_subseg;
8807 Elf_Internal_Note i_note;
8808 Elf_External_Note e_note;
8809 asection *note_secp;
8810 int len;
8811
8812 /* Create the .note section. */
8813 note_secp = subseg_new (".note", 0);
8814 bfd_set_section_flags (stdoutput,
8815 note_secp,
8816 SEC_HAS_CONTENTS | SEC_READONLY);
8817
8818 /* Process the arch string. */
8819 len = strlen (cpu_arch_name);
8820
8821 i_note.namesz = len + 1;
8822 i_note.descsz = 0;
8823 i_note.type = NT_ARCH;
8824 p = frag_more (sizeof (e_note.namesz));
8825 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8826 p = frag_more (sizeof (e_note.descsz));
8827 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8828 p = frag_more (sizeof (e_note.type));
8829 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8830 p = frag_more (len + 1);
8831 strcpy (p, cpu_arch_name);
8832
8833 frag_align (2, 0, 0);
8834
8835 subseg_set (seg, subseg);
8836 }
8837}
8838#endif
252b5132 8839\f
252b5132 8840symbolS *
7016a5d5 8841md_undefined_symbol (char *name)
252b5132 8842{
18dc2407
ILT		 8843 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8844 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8845 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8846 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8847 {
8848 if (!GOT_symbol)
8849 {
8850 if (symbol_find (name))
8851 as_bad (_("GOT already in symbol table"));
8852 GOT_symbol = symbol_new (name, undefined_section,
8853 (valueT) 0, &zero_address_frag);
8854 };
8855 return GOT_symbol;
8856 }
252b5132
RH		 8857 return 0;
8858}
8859
8860/* Round up a section size to the appropriate boundary. */
47926f60 8861
252b5132 8862valueT
7016a5d5 8863md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 8864{
4c63da97
AM		 8865#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8866 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8867 {
8868 /* For a.out, force the section size to be aligned. If we don't do
8869 this, BFD will align it for us, but it will not write out the
8870 final bytes of the section. This may be a bug in BFD, but it is
8871 easier to fix it here since that is how the other a.out targets
8872 work. */
8873 int align;
8874
8875 align = bfd_get_section_alignment (stdoutput, segment);
8876 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8877 }
252b5132
RH		 8878#endif
8879
8880 return size;
8881}
8882
8883/* On the i386, PC-relative offsets are relative to the start of the
8884 next instruction. That is, the address of the offset, plus its
8885 size, since the offset is always the last part of the insn. */
8886
8887long
e3bb37b5 8888md_pcrel_from (fixS *fixP)
252b5132
RH		 8889{
8890 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8891}
8892
8893#ifndef I386COFF
8894
8895static void
e3bb37b5 8896s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8897{
29b0f896 8898 int temp;
252b5132 8899
8a75718c
JB		 8900#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8901 if (IS_ELF)
8902 obj_elf_section_change_hook ();
8903#endif
252b5132
RH		 8904 temp = get_absolute_expression ();
8905 subseg_set (bss_section, (subsegT) temp);
8906 demand_empty_rest_of_line ();
8907}
8908
8909#endif
8910
252b5132 8911void
e3bb37b5 8912i386_validate_fix (fixS *fixp)
252b5132
RH		 8913{
8914 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8915 {
23df1078
JH		 8916 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8917 {
4fa24527 8918 if (!object_64bit)
23df1078
JH		 8919 abort ();
8920 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8921 }
8922 else
8923 {
4fa24527 8924 if (!object_64bit)
d6ab8113
JB		 8925 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8926 else
8927 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8928 }
252b5132
RH		 8929 fixp->fx_subsy = 0;
8930 }
8931}
8932
252b5132 8933arelent *
7016a5d5 8934tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 8935{
8936 arelent *rel;
8937 bfd_reloc_code_real_type code;
8938
8939 switch (fixp->fx_r_type)
8940 {
3e73aa7c
JH		 8941 case BFD_RELOC_X86_64_PLT32:
8942 case BFD_RELOC_X86_64_GOT32:
8943 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8944 case BFD_RELOC_386_PLT32:
8945 case BFD_RELOC_386_GOT32:
8946 case BFD_RELOC_386_GOTOFF:
8947 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8948 case BFD_RELOC_386_TLS_GD:
8949 case BFD_RELOC_386_TLS_LDM:
8950 case BFD_RELOC_386_TLS_LDO_32:
8951 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8952 case BFD_RELOC_386_TLS_IE:
8953 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8954 case BFD_RELOC_386_TLS_LE_32:
8955 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8956 case BFD_RELOC_386_TLS_GOTDESC:
8957 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8958 case BFD_RELOC_X86_64_TLSGD:
8959 case BFD_RELOC_X86_64_TLSLD:
8960 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8961 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8962 case BFD_RELOC_X86_64_GOTTPOFF:
8963 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8964 case BFD_RELOC_X86_64_TPOFF64:
8965 case BFD_RELOC_X86_64_GOTOFF64:
8966 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8967 case BFD_RELOC_X86_64_GOT64:
8968 case BFD_RELOC_X86_64_GOTPCREL64:
8969 case BFD_RELOC_X86_64_GOTPC64:
8970 case BFD_RELOC_X86_64_GOTPLT64:
8971 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8972 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8973 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8974 case BFD_RELOC_RVA:
8975 case BFD_RELOC_VTABLE_ENTRY:
8976 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8977#ifdef TE_PE
8978 case BFD_RELOC_32_SECREL:
8979#endif
252b5132
RH		 8980 code = fixp->fx_r_type;
8981 break;
dbbaec26
L		 8982 case BFD_RELOC_X86_64_32S:
8983 if (!fixp->fx_pcrel)
8984 {
8985 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8986 code = fixp->fx_r_type;
8987 break;
8988 }
252b5132 8989 default:
93382f6d 8990 if (fixp->fx_pcrel)
252b5132 8991 {
93382f6d
AM		 8992 switch (fixp->fx_size)
8993 {
8994 default:
b091f402
AM		 8995 as_bad_where (fixp->fx_file, fixp->fx_line,
8996 _("can not do %d byte pc-relative relocation"),
8997 fixp->fx_size);
93382f6d
AM		 8998 code = BFD_RELOC_32_PCREL;
8999 break;
9000 case 1: code = BFD_RELOC_8_PCREL; break;
9001 case 2: code = BFD_RELOC_16_PCREL; break;
9002 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 9003#ifdef BFD64
9004 case 8: code = BFD_RELOC_64_PCREL; break;
9005#endif
93382f6d
AM		 9006 }
9007 }
9008 else
9009 {
9010 switch (fixp->fx_size)
9011 {
9012 default:
b091f402
AM		 9013 as_bad_where (fixp->fx_file, fixp->fx_line,
9014 _("can not do %d byte relocation"),
9015 fixp->fx_size);
93382f6d
AM		 9016 code = BFD_RELOC_32;
9017 break;
9018 case 1: code = BFD_RELOC_8; break;
9019 case 2: code = BFD_RELOC_16; break;
9020 case 4: code = BFD_RELOC_32; break;
937149dd 9021#ifdef BFD64
3e73aa7c 9022 case 8: code = BFD_RELOC_64; break;
937149dd 9023#endif
93382f6d 9024 }
252b5132
RH		 9025 }
9026 break;
9027 }
252b5132 9028
d182319b
JB		 9029 if ((code == BFD_RELOC_32
9030 || code == BFD_RELOC_32_PCREL
9031 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 9032 && GOT_symbol
9033 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 9034 {
4fa24527 9035 if (!object_64bit)
d6ab8113
JB		 9036 code = BFD_RELOC_386_GOTPC;
9037 else
9038 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 9039 }
7b81dfbb
AJ		 9040 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
9041 && GOT_symbol
9042 && fixp->fx_addsy == GOT_symbol)
9043 {
9044 code = BFD_RELOC_X86_64_GOTPC64;
9045 }
252b5132
RH		 9046
9047 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 9048 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9049 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 9050
9051 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 9052
3e73aa7c
JH		 9053 if (!use_rela_relocations)
9054 {
9055 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
9056 vtable entry to be used in the relocation's section offset. */
9057 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
9058 rel->address = fixp->fx_offset;
fbeb56a4
DK		 9059#if defined (OBJ_COFF) && defined (TE_PE)
9060 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
9061 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
9062 else
9063#endif
c6682705 9064 rel->addend = 0;
3e73aa7c
JH		 9065 }
9066 /* Use the rela in 64bit mode. */
252b5132 9067 else
3e73aa7c 9068 {
862be3fb
L		 9069 if (disallow_64bit_reloc)
9070 switch (code)
9071 {
862be3fb
L		 9072 case BFD_RELOC_X86_64_DTPOFF64:
9073 case BFD_RELOC_X86_64_TPOFF64:
9074 case BFD_RELOC_64_PCREL:
9075 case BFD_RELOC_X86_64_GOTOFF64:
9076 case BFD_RELOC_X86_64_GOT64:
9077 case BFD_RELOC_X86_64_GOTPCREL64:
9078 case BFD_RELOC_X86_64_GOTPC64:
9079 case BFD_RELOC_X86_64_GOTPLT64:
9080 case BFD_RELOC_X86_64_PLTOFF64:
9081 as_bad_where (fixp->fx_file, fixp->fx_line,
9082 _("cannot represent relocation type %s in x32 mode"),
9083 bfd_get_reloc_code_name (code));
9084 break;
9085 default:
9086 break;
9087 }
9088
062cd5e7
AS		 9089 if (!fixp->fx_pcrel)
9090 rel->addend = fixp->fx_offset;
9091 else
9092 switch (code)
9093 {
9094 case BFD_RELOC_X86_64_PLT32:
9095 case BFD_RELOC_X86_64_GOT32:
9096 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 9097 case BFD_RELOC_X86_64_TLSGD:
9098 case BFD_RELOC_X86_64_TLSLD:
9099 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 9100 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9101 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 9102 rel->addend = fixp->fx_offset - fixp->fx_size;
9103 break;
9104 default:
9105 rel->addend = (section->vma
9106 - fixp->fx_size
9107 + fixp->fx_addnumber
9108 + md_pcrel_from (fixp));
9109 break;
9110 }
3e73aa7c
JH		 9111 }
9112
252b5132
RH		 9113 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
9114 if (rel->howto == NULL)
9115 {
9116 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 9117 _("cannot represent relocation type %s"),
252b5132
RH		 9118 bfd_get_reloc_code_name (code));
9119 /* Set howto to a garbage value so that we can keep going. */
9120 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 9121 gas_assert (rel->howto != NULL);
252b5132
RH		 9122 }
9123
9124 return rel;
9125}
9126
ee86248c 9127#include "tc-i386-intel.c"
54cfded0 9128
a60de03c
JB		 9129void
9130tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9131{
a60de03c
JB		 9132 int saved_naked_reg;
9133 char saved_register_dot;
54cfded0 9134
a60de03c
JB		 9135 saved_naked_reg = allow_naked_reg;
9136 allow_naked_reg = 1;
9137 saved_register_dot = register_chars['.'];
9138 register_chars['.'] = '.';
9139 allow_pseudo_reg = 1;
9140 expression_and_evaluate (exp);
9141 allow_pseudo_reg = 0;
9142 register_chars['.'] = saved_register_dot;
9143 allow_naked_reg = saved_naked_reg;
9144
e96d56a1 9145 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9146 {
a60de03c
JB		 9147 if ((addressT) exp->X_add_number < i386_regtab_size)
9148 {
9149 exp->X_op = O_constant;
9150 exp->X_add_number = i386_regtab[exp->X_add_number]
9151 .dw2_regnum[flag_code >> 1];
9152 }
9153 else
9154 exp->X_op = O_illegal;
54cfded0 9155 }
54cfded0
AM		 9156}
9157
9158void
9159tc_x86_frame_initial_instructions (void)
9160{
a60de03c
JB		 9161 static unsigned int sp_regno[2];
9162
9163 if (!sp_regno[flag_code >> 1])
9164 {
9165 char *saved_input = input_line_pointer;
9166 char sp[][4] = {"esp", "rsp"};
9167 expressionS exp;
a4447b93 9168
a60de03c
JB		 9169 input_line_pointer = sp[flag_code >> 1];
9170 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 9171 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 9172 sp_regno[flag_code >> 1] = exp.X_add_number;
9173 input_line_pointer = saved_input;
9174 }
a4447b93 9175
61ff971f
L		 9176 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
9177 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9178}
d2b2c203 9179
d7921315
L		 9180int
9181x86_dwarf2_addr_size (void)
9182{
9183#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9184 if (x86_elf_abi == X86_64_X32_ABI)
9185 return 4;
9186#endif
9187 return bfd_arch_bits_per_address (stdoutput) / 8;
9188}
9189
d2b2c203
DJ		 9190int
9191i386_elf_section_type (const char *str, size_t len)
9192{
9193 if (flag_code == CODE_64BIT
9194 && len == sizeof ("unwind") - 1
9195 && strncmp (str, "unwind", 6) == 0)
9196 return SHT_X86_64_UNWIND;
9197
9198 return -1;
9199}
bb41ade5 9200
ad5fec3b
EB		 9201#ifdef TE_SOLARIS
9202void
9203i386_solaris_fix_up_eh_frame (segT sec)
9204{
9205 if (flag_code == CODE_64BIT)
9206 elf_section_type (sec) = SHT_X86_64_UNWIND;
9207}
9208#endif
9209
bb41ade5
AM		 9210#ifdef TE_PE
9211void
9212tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9213{
91d6fa6a 9214 expressionS exp;
bb41ade5 9215
91d6fa6a
NC		 9216 exp.X_op = O_secrel;
9217 exp.X_add_symbol = symbol;
9218 exp.X_add_number = 0;
9219 emit_expr (&exp, size);
bb41ade5
AM		 9220}
9221#endif
3b22753a
L		 9222
9223#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9224/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9225
01e1a5bc 9226bfd_vma
3b22753a
L		 9227x86_64_section_letter (int letter, char **ptr_msg)
9228{
9229 if (flag_code == CODE_64BIT)
9230 {
9231 if (letter == 'l')
9232 return SHF_X86_64_LARGE;
9233
8f3bae45 9234 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9235 }
3b22753a 9236 else
8f3bae45 9237 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9238 return -1;
9239}
9240
01e1a5bc 9241bfd_vma
3b22753a
L		 9242x86_64_section_word (char *str, size_t len)
9243{
8620418b 9244 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9245 return SHF_X86_64_LARGE;
9246
9247 return -1;
9248}
9249
9250static void
9251handle_large_common (int small ATTRIBUTE_UNUSED)
9252{
9253 if (flag_code != CODE_64BIT)
9254 {
9255 s_comm_internal (0, elf_common_parse);
9256 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9257 }
9258 else
9259 {
9260 static segT lbss_section;
9261 asection *saved_com_section_ptr = elf_com_section_ptr;
9262 asection *saved_bss_section = bss_section;
9263
9264 if (lbss_section == NULL)
9265 {
9266 flagword applicable;
9267 segT seg = now_seg;
9268 subsegT subseg = now_subseg;
9269
9270 /* The .lbss section is for local .largecomm symbols. */
9271 lbss_section = subseg_new (".lbss", 0);
9272 applicable = bfd_applicable_section_flags (stdoutput);
9273 bfd_set_section_flags (stdoutput, lbss_section,
9274 applicable & SEC_ALLOC);
9275 seg_info (lbss_section)->bss = 1;
9276
9277 subseg_set (seg, subseg);
9278 }
9279
9280 elf_com_section_ptr = &_bfd_elf_large_com_section;
9281 bss_section = lbss_section;
9282
9283 s_comm_internal (0, elf_common_parse);
9284
9285 elf_com_section_ptr = saved_com_section_ptr;
9286 bss_section = saved_bss_section;
9287 }
9288}
9289#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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