Commit | Line | Data |
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252b5132 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
4c63da97 | 2 | Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000 |
47926f60 | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
21 | ||
47926f60 KH |
22 | /* Intel 80386 machine specific gas. |
23 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
24 | Bugs & suggestions are completely welcome. This is free software. | |
25 | Please help us make it better. */ | |
252b5132 RH |
26 | |
27 | #include <ctype.h> | |
28 | ||
29 | #include "as.h" | |
30 | #include "subsegs.h" | |
316e2c05 | 31 | #include "dwarf2dbg.h" |
252b5132 RH |
32 | #include "opcode/i386.h" |
33 | ||
252b5132 RH |
34 | #ifndef REGISTER_WARNINGS |
35 | #define REGISTER_WARNINGS 1 | |
36 | #endif | |
37 | ||
c3332e24 | 38 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 39 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
40 | #endif |
41 | ||
252b5132 RH |
42 | #ifndef SCALE1_WHEN_NO_INDEX |
43 | /* Specifying a scale factor besides 1 when there is no index is | |
44 | futile. eg. `mov (%ebx,2),%al' does exactly the same as | |
45 | `mov (%ebx),%al'. To slavishly follow what the programmer | |
46 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ | |
47 | #define SCALE1_WHEN_NO_INDEX 1 | |
48 | #endif | |
49 | ||
50 | #define true 1 | |
51 | #define false 0 | |
52 | ||
53 | static unsigned int mode_from_disp_size PARAMS ((unsigned int)); | |
847f7ad4 AM |
54 | static int fits_in_signed_byte PARAMS ((offsetT)); |
55 | static int fits_in_unsigned_byte PARAMS ((offsetT)); | |
56 | static int fits_in_unsigned_word PARAMS ((offsetT)); | |
57 | static int fits_in_signed_word PARAMS ((offsetT)); | |
58 | static int smallest_imm_type PARAMS ((offsetT)); | |
59 | static offsetT offset_in_range PARAMS ((offsetT, int)); | |
252b5132 RH |
60 | static int add_prefix PARAMS ((unsigned int)); |
61 | static void set_16bit_code_flag PARAMS ((int)); | |
47926f60 | 62 | static void set_16bit_gcc_code_flag PARAMS ((int)); |
252b5132 | 63 | static void set_intel_syntax PARAMS ((int)); |
e413e4e9 | 64 | static void set_cpu_arch PARAMS ((int)); |
252b5132 RH |
65 | |
66 | #ifdef BFD_ASSEMBLER | |
67 | static bfd_reloc_code_real_type reloc | |
68 | PARAMS ((int, int, bfd_reloc_code_real_type)); | |
69 | #endif | |
70 | ||
71 | /* 'md_assemble ()' gathers together information and puts it into a | |
47926f60 | 72 | i386_insn. */ |
252b5132 | 73 | |
520dc8e8 AM |
74 | union i386_op |
75 | { | |
76 | expressionS *disps; | |
77 | expressionS *imms; | |
78 | const reg_entry *regs; | |
79 | }; | |
80 | ||
252b5132 RH |
81 | struct _i386_insn |
82 | { | |
47926f60 | 83 | /* TM holds the template for the insn were currently assembling. */ |
252b5132 RH |
84 | template tm; |
85 | ||
86 | /* SUFFIX holds the instruction mnemonic suffix if given. | |
87 | (e.g. 'l' for 'movl') */ | |
88 | char suffix; | |
89 | ||
47926f60 | 90 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
91 | unsigned int operands; |
92 | ||
93 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
94 | of given register, displacement, memory operands and immediate | |
47926f60 | 95 | operands. */ |
252b5132 RH |
96 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
97 | ||
98 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 99 | use OP[i] for the corresponding operand. */ |
252b5132 RH |
100 | unsigned int types[MAX_OPERANDS]; |
101 | ||
520dc8e8 AM |
102 | /* Displacement expression, immediate expression, or register for each |
103 | operand. */ | |
104 | union i386_op op[MAX_OPERANDS]; | |
252b5132 RH |
105 | |
106 | /* Relocation type for operand */ | |
107 | #ifdef BFD_ASSEMBLER | |
108 | enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS]; | |
109 | #else | |
110 | int disp_reloc[MAX_OPERANDS]; | |
111 | #endif | |
112 | ||
252b5132 RH |
113 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
114 | the base index byte below. */ | |
115 | const reg_entry *base_reg; | |
116 | const reg_entry *index_reg; | |
117 | unsigned int log2_scale_factor; | |
118 | ||
119 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 120 | explicit segment overrides are given. */ |
ce8a8b2f | 121 | const seg_entry *seg[2]; |
252b5132 RH |
122 | |
123 | /* PREFIX holds all the given prefix opcodes (usually null). | |
124 | PREFIXES is the number of prefix opcodes. */ | |
125 | unsigned int prefixes; | |
126 | unsigned char prefix[MAX_PREFIXES]; | |
127 | ||
128 | /* RM and SIB are the modrm byte and the sib byte where the | |
129 | addressing modes of this insn are encoded. */ | |
130 | ||
131 | modrm_byte rm; | |
132 | sib_byte sib; | |
133 | }; | |
134 | ||
135 | typedef struct _i386_insn i386_insn; | |
136 | ||
137 | /* List of chars besides those in app.c:symbol_chars that can start an | |
138 | operand. Used to prevent the scrubber eating vital white-space. */ | |
139 | #ifdef LEX_AT | |
140 | const char extra_symbol_chars[] = "*%-(@"; | |
141 | #else | |
142 | const char extra_symbol_chars[] = "*%-("; | |
143 | #endif | |
144 | ||
145 | /* This array holds the chars that always start a comment. If the | |
ce8a8b2f | 146 | pre-processor is disabled, these aren't very useful. */ |
60bcf0fa | 147 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) |
252b5132 RH |
148 | /* Putting '/' here makes it impossible to use the divide operator. |
149 | However, we need it for compatibility with SVR4 systems. */ | |
150 | const char comment_chars[] = "#/"; | |
151 | #define PREFIX_SEPARATOR '\\' | |
152 | #else | |
153 | const char comment_chars[] = "#"; | |
154 | #define PREFIX_SEPARATOR '/' | |
155 | #endif | |
156 | ||
157 | /* This array holds the chars that only start a comment at the beginning of | |
158 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
159 | .line and .file directives will appear in the pre-processed output. |
160 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 161 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
162 | #NO_APP at the beginning of its output. |
163 | Also note that comments started like this one will always work if | |
252b5132 | 164 | '/' isn't otherwise defined. */ |
60bcf0fa | 165 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) |
252b5132 RH |
166 | const char line_comment_chars[] = ""; |
167 | #else | |
168 | const char line_comment_chars[] = "/"; | |
169 | #endif | |
170 | ||
63a0b638 | 171 | const char line_separator_chars[] = ";"; |
252b5132 | 172 | |
ce8a8b2f AM |
173 | /* Chars that can be used to separate mant from exp in floating point |
174 | nums. */ | |
252b5132 RH |
175 | const char EXP_CHARS[] = "eE"; |
176 | ||
ce8a8b2f AM |
177 | /* Chars that mean this number is a floating point constant |
178 | As in 0f12.456 | |
179 | or 0d1.2345e12. */ | |
252b5132 RH |
180 | const char FLT_CHARS[] = "fFdDxX"; |
181 | ||
ce8a8b2f | 182 | /* Tables for lexical analysis. */ |
252b5132 RH |
183 | static char mnemonic_chars[256]; |
184 | static char register_chars[256]; | |
185 | static char operand_chars[256]; | |
186 | static char identifier_chars[256]; | |
187 | static char digit_chars[256]; | |
188 | ||
ce8a8b2f | 189 | /* Lexical macros. */ |
252b5132 RH |
190 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
191 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
192 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
193 | #define is_space_char(x) ((x) == ' ') | |
194 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
195 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
196 | ||
ce8a8b2f | 197 | /* All non-digit non-letter charcters that may occur in an operand. */ |
252b5132 RH |
198 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
199 | ||
200 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
201 | effect this we maintain a stack of saved characters that we've smashed | |
202 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 203 | assembler instruction). */ |
252b5132 | 204 | static char save_stack[32]; |
ce8a8b2f | 205 | static char *save_stack_p; |
252b5132 RH |
206 | #define END_STRING_AND_SAVE(s) \ |
207 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
208 | #define RESTORE_END_STRING(s) \ | |
209 | do { *(s) = *--save_stack_p; } while (0) | |
210 | ||
47926f60 | 211 | /* The instruction we're assembling. */ |
252b5132 RH |
212 | static i386_insn i; |
213 | ||
214 | /* Possible templates for current insn. */ | |
215 | static const templates *current_templates; | |
216 | ||
47926f60 | 217 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ |
252b5132 RH |
218 | static expressionS disp_expressions[2], im_expressions[2]; |
219 | ||
47926f60 KH |
220 | /* Current operand we are working on. */ |
221 | static int this_operand; | |
252b5132 | 222 | |
47926f60 KH |
223 | /* 1 if we're writing 16-bit code, |
224 | 0 if 32-bit. */ | |
225 | static int flag_16bit_code; | |
252b5132 | 226 | |
47926f60 KH |
227 | /* 1 for intel syntax, |
228 | 0 if att syntax. */ | |
229 | static int intel_syntax = 0; | |
252b5132 | 230 | |
47926f60 KH |
231 | /* 1 if register prefix % not required. */ |
232 | static int allow_naked_reg = 0; | |
252b5132 | 233 | |
47926f60 KH |
234 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
235 | leave, push, and pop instructions so that gcc has the same stack | |
236 | frame as in 32 bit mode. */ | |
237 | static char stackop_size = '\0'; | |
eecb386c | 238 | |
47926f60 KH |
239 | /* Non-zero to quieten some warnings. */ |
240 | static int quiet_warnings = 0; | |
a38cf1db | 241 | |
47926f60 KH |
242 | /* CPU name. */ |
243 | static const char *cpu_arch_name = NULL; | |
a38cf1db | 244 | |
47926f60 KH |
245 | /* CPU feature flags. */ |
246 | static unsigned int cpu_arch_flags = 0; | |
a38cf1db | 247 | |
252b5132 RH |
248 | /* Interface to relax_segment. |
249 | There are 2 relax states for 386 jump insns: one for conditional & | |
a217f122 AM |
250 | one for unconditional jumps. This is because these two types of |
251 | jumps add different sizes to frags when we're figuring out what | |
252b5132 RH |
252 | sort of jump to choose to reach a given label. */ |
253 | ||
47926f60 | 254 | /* Types. */ |
ce8a8b2f AM |
255 | #define COND_JUMP 1 |
256 | #define UNCOND_JUMP 2 | |
47926f60 | 257 | /* Sizes. */ |
252b5132 RH |
258 | #define CODE16 1 |
259 | #define SMALL 0 | |
260 | #define SMALL16 (SMALL|CODE16) | |
261 | #define BIG 2 | |
262 | #define BIG16 (BIG|CODE16) | |
263 | ||
264 | #ifndef INLINE | |
265 | #ifdef __GNUC__ | |
266 | #define INLINE __inline__ | |
267 | #else | |
268 | #define INLINE | |
269 | #endif | |
270 | #endif | |
271 | ||
272 | #define ENCODE_RELAX_STATE(type,size) \ | |
bc805888 | 273 | ((relax_substateT) ((type<<2) | (size))) |
252b5132 RH |
274 | #define SIZE_FROM_RELAX_STATE(s) \ |
275 | ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) ) | |
276 | ||
277 | /* This table is used by relax_frag to promote short jumps to long | |
278 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
279 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
280 | don't allow a short jump in a 32 bit code segment to be promoted to | |
281 | a 16 bit offset jump because it's slower (requires data size | |
282 | prefix), and doesn't work, unless the destination is in the bottom | |
283 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
284 | ||
285 | const relax_typeS md_relax_table[] = | |
286 | { | |
24eab124 AM |
287 | /* The fields are: |
288 | 1) most positive reach of this state, | |
289 | 2) most negative reach of this state, | |
290 | 3) how many bytes this mode will add to the size of the current frag | |
ce8a8b2f | 291 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 RH |
292 | {1, 1, 0, 0}, |
293 | {1, 1, 0, 0}, | |
294 | {1, 1, 0, 0}, | |
295 | {1, 1, 0, 0}, | |
296 | ||
297 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
298 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
299 | /* dword conditionals adds 4 bytes to frag: | |
300 | 1 extra opcode byte, 3 extra displacement bytes. */ | |
301 | {0, 0, 4, 0}, | |
302 | /* word conditionals add 2 bytes to frag: | |
303 | 1 extra opcode byte, 1 extra displacement byte. */ | |
304 | {0, 0, 2, 0}, | |
305 | ||
306 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, | |
307 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
308 | /* dword jmp adds 3 bytes to frag: | |
309 | 0 extra opcode bytes, 3 extra displacement bytes. */ | |
310 | {0, 0, 3, 0}, | |
311 | /* word jmp adds 1 byte to frag: | |
312 | 0 extra opcode bytes, 1 extra displacement byte. */ | |
313 | {0, 0, 1, 0} | |
314 | ||
315 | }; | |
316 | ||
e413e4e9 AM |
317 | static const arch_entry cpu_arch[] = { |
318 | {"i8086", Cpu086 }, | |
319 | {"i186", Cpu086|Cpu186 }, | |
320 | {"i286", Cpu086|Cpu186|Cpu286 }, | |
321 | {"i386", Cpu086|Cpu186|Cpu286|Cpu386 }, | |
322 | {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 }, | |
323 | {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
324 | {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
325 | {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
326 | {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
327 | {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX|Cpu3dnow }, | |
328 | {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|Cpu3dnow }, | |
329 | {NULL, 0 } | |
330 | }; | |
331 | ||
252b5132 RH |
332 | void |
333 | i386_align_code (fragP, count) | |
334 | fragS *fragP; | |
335 | int count; | |
336 | { | |
ce8a8b2f AM |
337 | /* Various efficient no-op patterns for aligning code labels. |
338 | Note: Don't try to assemble the instructions in the comments. | |
339 | 0L and 0w are not legal. */ | |
252b5132 RH |
340 | static const char f32_1[] = |
341 | {0x90}; /* nop */ | |
342 | static const char f32_2[] = | |
343 | {0x89,0xf6}; /* movl %esi,%esi */ | |
344 | static const char f32_3[] = | |
345 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
346 | static const char f32_4[] = | |
347 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
348 | static const char f32_5[] = | |
349 | {0x90, /* nop */ | |
350 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
351 | static const char f32_6[] = | |
352 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
353 | static const char f32_7[] = | |
354 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
355 | static const char f32_8[] = | |
356 | {0x90, /* nop */ | |
357 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
358 | static const char f32_9[] = | |
359 | {0x89,0xf6, /* movl %esi,%esi */ | |
360 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
361 | static const char f32_10[] = | |
362 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
363 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
364 | static const char f32_11[] = | |
365 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
366 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
367 | static const char f32_12[] = | |
368 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
369 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
370 | static const char f32_13[] = | |
371 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
372 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
373 | static const char f32_14[] = | |
374 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
375 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
376 | static const char f32_15[] = | |
377 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
378 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
c3332e24 AM |
379 | static const char f16_3[] = |
380 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
381 | static const char f16_4[] = |
382 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
383 | static const char f16_5[] = | |
384 | {0x90, /* nop */ | |
385 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
386 | static const char f16_6[] = | |
387 | {0x89,0xf6, /* mov %si,%si */ | |
388 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
389 | static const char f16_7[] = | |
390 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
391 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
392 | static const char f16_8[] = | |
393 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
394 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
395 | static const char *const f32_patt[] = { | |
396 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
397 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
398 | }; | |
399 | static const char *const f16_patt[] = { | |
c3332e24 | 400 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, |
252b5132 RH |
401 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 |
402 | }; | |
403 | ||
404 | if (count > 0 && count <= 15) | |
405 | { | |
406 | if (flag_16bit_code) | |
407 | { | |
47926f60 KH |
408 | memcpy (fragP->fr_literal + fragP->fr_fix, |
409 | f16_patt[count - 1], count); | |
410 | if (count > 8) | |
411 | /* Adjust jump offset. */ | |
252b5132 RH |
412 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; |
413 | } | |
414 | else | |
47926f60 KH |
415 | memcpy (fragP->fr_literal + fragP->fr_fix, |
416 | f32_patt[count - 1], count); | |
252b5132 RH |
417 | fragP->fr_var = count; |
418 | } | |
419 | } | |
420 | ||
421 | static char *output_invalid PARAMS ((int c)); | |
422 | static int i386_operand PARAMS ((char *operand_string)); | |
423 | static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); | |
424 | static const reg_entry *parse_register PARAMS ((char *reg_string, | |
425 | char **end_op)); | |
426 | ||
427 | #ifndef I386COFF | |
428 | static void s_bss PARAMS ((int)); | |
429 | #endif | |
430 | ||
ce8a8b2f | 431 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
252b5132 RH |
432 | |
433 | static INLINE unsigned int | |
434 | mode_from_disp_size (t) | |
435 | unsigned int t; | |
436 | { | |
47926f60 | 437 | return (t & Disp8) ? 1 : (t & (Disp16 | Disp32)) ? 2 : 0; |
252b5132 RH |
438 | } |
439 | ||
440 | static INLINE int | |
441 | fits_in_signed_byte (num) | |
847f7ad4 | 442 | offsetT num; |
252b5132 RH |
443 | { |
444 | return (num >= -128) && (num <= 127); | |
47926f60 | 445 | } |
252b5132 RH |
446 | |
447 | static INLINE int | |
448 | fits_in_unsigned_byte (num) | |
847f7ad4 | 449 | offsetT num; |
252b5132 RH |
450 | { |
451 | return (num & 0xff) == num; | |
47926f60 | 452 | } |
252b5132 RH |
453 | |
454 | static INLINE int | |
455 | fits_in_unsigned_word (num) | |
847f7ad4 | 456 | offsetT num; |
252b5132 RH |
457 | { |
458 | return (num & 0xffff) == num; | |
47926f60 | 459 | } |
252b5132 RH |
460 | |
461 | static INLINE int | |
462 | fits_in_signed_word (num) | |
847f7ad4 | 463 | offsetT num; |
252b5132 RH |
464 | { |
465 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 466 | } |
252b5132 RH |
467 | |
468 | static int | |
469 | smallest_imm_type (num) | |
847f7ad4 | 470 | offsetT num; |
252b5132 | 471 | { |
e413e4e9 | 472 | if (cpu_arch_flags != 0 |
47926f60 | 473 | && cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486)) |
e413e4e9 AM |
474 | { |
475 | /* This code is disabled on the 486 because all the Imm1 forms | |
476 | in the opcode table are slower on the i486. They're the | |
477 | versions with the implicitly specified single-position | |
478 | displacement, which has another syntax if you really want to | |
479 | use that form. */ | |
480 | if (num == 1) | |
481 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32; | |
482 | } | |
252b5132 RH |
483 | return (fits_in_signed_byte (num) |
484 | ? (Imm8S | Imm8 | Imm16 | Imm32) | |
485 | : fits_in_unsigned_byte (num) | |
486 | ? (Imm8 | Imm16 | Imm32) | |
487 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
488 | ? (Imm16 | Imm32) | |
489 | : (Imm32)); | |
47926f60 | 490 | } |
252b5132 | 491 | |
847f7ad4 AM |
492 | static offsetT |
493 | offset_in_range (val, size) | |
494 | offsetT val; | |
495 | int size; | |
496 | { | |
508866be | 497 | addressT mask; |
ba2adb93 | 498 | |
847f7ad4 AM |
499 | switch (size) |
500 | { | |
508866be L |
501 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
502 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 503 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
47926f60 | 504 | default: abort (); |
847f7ad4 AM |
505 | } |
506 | ||
ba2adb93 | 507 | /* If BFD64, sign extend val. */ |
47926f60 | 508 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
508866be | 509 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); |
ba2adb93 | 510 | |
47926f60 | 511 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
512 | { |
513 | char buf1[40], buf2[40]; | |
514 | ||
515 | sprint_value (buf1, val); | |
516 | sprint_value (buf2, val & mask); | |
517 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
518 | } | |
519 | return val & mask; | |
520 | } | |
521 | ||
252b5132 RH |
522 | /* Returns 0 if attempting to add a prefix where one from the same |
523 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
524 | added. */ | |
525 | static int | |
526 | add_prefix (prefix) | |
527 | unsigned int prefix; | |
528 | { | |
529 | int ret = 1; | |
530 | int q; | |
531 | ||
532 | switch (prefix) | |
533 | { | |
534 | default: | |
535 | abort (); | |
536 | ||
537 | case CS_PREFIX_OPCODE: | |
538 | case DS_PREFIX_OPCODE: | |
539 | case ES_PREFIX_OPCODE: | |
540 | case FS_PREFIX_OPCODE: | |
541 | case GS_PREFIX_OPCODE: | |
542 | case SS_PREFIX_OPCODE: | |
543 | q = SEG_PREFIX; | |
544 | break; | |
545 | ||
546 | case REPNE_PREFIX_OPCODE: | |
547 | case REPE_PREFIX_OPCODE: | |
548 | ret = 2; | |
549 | /* fall thru */ | |
550 | case LOCK_PREFIX_OPCODE: | |
551 | q = LOCKREP_PREFIX; | |
552 | break; | |
553 | ||
554 | case FWAIT_OPCODE: | |
555 | q = WAIT_PREFIX; | |
556 | break; | |
557 | ||
558 | case ADDR_PREFIX_OPCODE: | |
559 | q = ADDR_PREFIX; | |
560 | break; | |
561 | ||
562 | case DATA_PREFIX_OPCODE: | |
563 | q = DATA_PREFIX; | |
564 | break; | |
565 | } | |
566 | ||
567 | if (i.prefix[q]) | |
568 | { | |
569 | as_bad (_("same type of prefix used twice")); | |
570 | return 0; | |
571 | } | |
572 | ||
573 | i.prefixes += 1; | |
574 | i.prefix[q] = prefix; | |
575 | return ret; | |
576 | } | |
577 | ||
578 | static void | |
579 | set_16bit_code_flag (new_16bit_code_flag) | |
eecb386c AM |
580 | int new_16bit_code_flag; |
581 | { | |
582 | flag_16bit_code = new_16bit_code_flag; | |
583 | stackop_size = '\0'; | |
584 | } | |
585 | ||
586 | static void | |
587 | set_16bit_gcc_code_flag (new_16bit_code_flag) | |
588 | int new_16bit_code_flag; | |
252b5132 RH |
589 | { |
590 | flag_16bit_code = new_16bit_code_flag; | |
eecb386c | 591 | stackop_size = new_16bit_code_flag ? 'l' : '\0'; |
252b5132 RH |
592 | } |
593 | ||
594 | static void | |
595 | set_intel_syntax (syntax_flag) | |
eecb386c | 596 | int syntax_flag; |
252b5132 RH |
597 | { |
598 | /* Find out if register prefixing is specified. */ | |
599 | int ask_naked_reg = 0; | |
600 | ||
601 | SKIP_WHITESPACE (); | |
602 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
603 | { | |
604 | char *string = input_line_pointer; | |
605 | int e = get_symbol_end (); | |
606 | ||
47926f60 | 607 | if (strcmp (string, "prefix") == 0) |
252b5132 | 608 | ask_naked_reg = 1; |
47926f60 | 609 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
610 | ask_naked_reg = -1; |
611 | else | |
d0b47220 | 612 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
613 | *input_line_pointer = e; |
614 | } | |
615 | demand_empty_rest_of_line (); | |
c3332e24 | 616 | |
252b5132 RH |
617 | intel_syntax = syntax_flag; |
618 | ||
619 | if (ask_naked_reg == 0) | |
620 | { | |
621 | #ifdef BFD_ASSEMBLER | |
622 | allow_naked_reg = (intel_syntax | |
24eab124 | 623 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); |
252b5132 | 624 | #else |
47926f60 KH |
625 | /* Conservative default. */ |
626 | allow_naked_reg = 0; | |
252b5132 RH |
627 | #endif |
628 | } | |
629 | else | |
630 | allow_naked_reg = (ask_naked_reg < 0); | |
631 | } | |
632 | ||
e413e4e9 AM |
633 | static void |
634 | set_cpu_arch (dummy) | |
47926f60 | 635 | int dummy ATTRIBUTE_UNUSED; |
e413e4e9 | 636 | { |
47926f60 | 637 | SKIP_WHITESPACE (); |
e413e4e9 AM |
638 | |
639 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
640 | { | |
641 | char *string = input_line_pointer; | |
642 | int e = get_symbol_end (); | |
643 | int i; | |
644 | ||
645 | for (i = 0; cpu_arch[i].name; i++) | |
646 | { | |
647 | if (strcmp (string, cpu_arch[i].name) == 0) | |
648 | { | |
649 | cpu_arch_name = cpu_arch[i].name; | |
650 | cpu_arch_flags = cpu_arch[i].flags; | |
651 | break; | |
652 | } | |
653 | } | |
654 | if (!cpu_arch[i].name) | |
655 | as_bad (_("no such architecture: `%s'"), string); | |
656 | ||
657 | *input_line_pointer = e; | |
658 | } | |
659 | else | |
660 | as_bad (_("missing cpu architecture")); | |
661 | ||
662 | demand_empty_rest_of_line (); | |
663 | } | |
664 | ||
252b5132 RH |
665 | const pseudo_typeS md_pseudo_table[] = |
666 | { | |
252b5132 RH |
667 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
668 | {"align", s_align_bytes, 0}, | |
669 | #else | |
670 | {"align", s_align_ptwo, 0}, | |
e413e4e9 AM |
671 | #endif |
672 | {"arch", set_cpu_arch, 0}, | |
673 | #ifndef I386COFF | |
674 | {"bss", s_bss, 0}, | |
252b5132 RH |
675 | #endif |
676 | {"ffloat", float_cons, 'f'}, | |
677 | {"dfloat", float_cons, 'd'}, | |
678 | {"tfloat", float_cons, 'x'}, | |
679 | {"value", cons, 2}, | |
680 | {"noopt", s_ignore, 0}, | |
681 | {"optim", s_ignore, 0}, | |
eecb386c | 682 | {"code16gcc", set_16bit_gcc_code_flag, 1}, |
252b5132 RH |
683 | {"code16", set_16bit_code_flag, 1}, |
684 | {"code32", set_16bit_code_flag, 0}, | |
685 | {"intel_syntax", set_intel_syntax, 1}, | |
686 | {"att_syntax", set_intel_syntax, 0}, | |
316e2c05 RH |
687 | {"file", dwarf2_directive_file, 0}, |
688 | {"loc", dwarf2_directive_loc, 0}, | |
252b5132 RH |
689 | {0, 0, 0} |
690 | }; | |
691 | ||
47926f60 | 692 | /* For interface with expression (). */ |
252b5132 RH |
693 | extern char *input_line_pointer; |
694 | ||
47926f60 | 695 | /* Hash table for instruction mnemonic lookup. */ |
252b5132 | 696 | static struct hash_control *op_hash; |
47926f60 KH |
697 | |
698 | /* Hash table for register lookup. */ | |
252b5132 RH |
699 | static struct hash_control *reg_hash; |
700 | \f | |
252b5132 RH |
701 | void |
702 | md_begin () | |
703 | { | |
704 | const char *hash_err; | |
705 | ||
47926f60 | 706 | /* Initialize op_hash hash table. */ |
252b5132 RH |
707 | op_hash = hash_new (); |
708 | ||
709 | { | |
710 | register const template *optab; | |
711 | register templates *core_optab; | |
712 | ||
47926f60 KH |
713 | /* Setup for loop. */ |
714 | optab = i386_optab; | |
252b5132 RH |
715 | core_optab = (templates *) xmalloc (sizeof (templates)); |
716 | core_optab->start = optab; | |
717 | ||
718 | while (1) | |
719 | { | |
720 | ++optab; | |
721 | if (optab->name == NULL | |
722 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
723 | { | |
724 | /* different name --> ship out current template list; | |
47926f60 | 725 | add to hash table; & begin anew. */ |
252b5132 RH |
726 | core_optab->end = optab; |
727 | hash_err = hash_insert (op_hash, | |
728 | (optab - 1)->name, | |
729 | (PTR) core_optab); | |
730 | if (hash_err) | |
731 | { | |
732 | hash_error: | |
733 | as_fatal (_("Internal Error: Can't hash %s: %s"), | |
734 | (optab - 1)->name, | |
735 | hash_err); | |
736 | } | |
737 | if (optab->name == NULL) | |
738 | break; | |
739 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
740 | core_optab->start = optab; | |
741 | } | |
742 | } | |
743 | } | |
744 | ||
47926f60 | 745 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
746 | reg_hash = hash_new (); |
747 | { | |
748 | register const reg_entry *regtab; | |
749 | ||
750 | for (regtab = i386_regtab; | |
751 | regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); | |
752 | regtab++) | |
753 | { | |
754 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); | |
755 | if (hash_err) | |
756 | goto hash_error; | |
757 | } | |
758 | } | |
759 | ||
47926f60 | 760 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 RH |
761 | { |
762 | register int c; | |
763 | register char *p; | |
764 | ||
765 | for (c = 0; c < 256; c++) | |
766 | { | |
767 | if (isdigit (c)) | |
768 | { | |
769 | digit_chars[c] = c; | |
770 | mnemonic_chars[c] = c; | |
771 | register_chars[c] = c; | |
772 | operand_chars[c] = c; | |
773 | } | |
774 | else if (islower (c)) | |
775 | { | |
776 | mnemonic_chars[c] = c; | |
777 | register_chars[c] = c; | |
778 | operand_chars[c] = c; | |
779 | } | |
780 | else if (isupper (c)) | |
781 | { | |
782 | mnemonic_chars[c] = tolower (c); | |
783 | register_chars[c] = mnemonic_chars[c]; | |
784 | operand_chars[c] = c; | |
785 | } | |
786 | ||
787 | if (isalpha (c) || isdigit (c)) | |
788 | identifier_chars[c] = c; | |
789 | else if (c >= 128) | |
790 | { | |
791 | identifier_chars[c] = c; | |
792 | operand_chars[c] = c; | |
793 | } | |
794 | } | |
795 | ||
796 | #ifdef LEX_AT | |
797 | identifier_chars['@'] = '@'; | |
798 | #endif | |
252b5132 RH |
799 | digit_chars['-'] = '-'; |
800 | identifier_chars['_'] = '_'; | |
801 | identifier_chars['.'] = '.'; | |
802 | ||
803 | for (p = operand_special_chars; *p != '\0'; p++) | |
804 | operand_chars[(unsigned char) *p] = *p; | |
805 | } | |
806 | ||
807 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
808 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
809 | { | |
810 | record_alignment (text_section, 2); | |
811 | record_alignment (data_section, 2); | |
812 | record_alignment (bss_section, 2); | |
813 | } | |
814 | #endif | |
815 | } | |
816 | ||
817 | void | |
818 | i386_print_statistics (file) | |
819 | FILE *file; | |
820 | { | |
821 | hash_print_statistics (file, "i386 opcode", op_hash); | |
822 | hash_print_statistics (file, "i386 register", reg_hash); | |
823 | } | |
824 | \f | |
252b5132 RH |
825 | #ifdef DEBUG386 |
826 | ||
ce8a8b2f | 827 | /* Debugging routines for md_assemble. */ |
252b5132 RH |
828 | static void pi PARAMS ((char *, i386_insn *)); |
829 | static void pte PARAMS ((template *)); | |
830 | static void pt PARAMS ((unsigned int)); | |
831 | static void pe PARAMS ((expressionS *)); | |
832 | static void ps PARAMS ((symbolS *)); | |
833 | ||
834 | static void | |
835 | pi (line, x) | |
836 | char *line; | |
837 | i386_insn *x; | |
838 | { | |
839 | register template *p; | |
840 | int i; | |
841 | ||
842 | fprintf (stdout, "%s: template ", line); | |
843 | pte (&x->tm); | |
844 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x", | |
845 | x->rm.mode, x->rm.reg, x->rm.regmem); | |
846 | fprintf (stdout, " base %x index %x scale %x\n", | |
847 | x->bi.base, x->bi.index, x->bi.scale); | |
848 | for (i = 0; i < x->operands; i++) | |
849 | { | |
850 | fprintf (stdout, " #%d: ", i + 1); | |
851 | pt (x->types[i]); | |
852 | fprintf (stdout, "\n"); | |
853 | if (x->types[i] | |
3f4438ab | 854 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) |
520dc8e8 | 855 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
252b5132 | 856 | if (x->types[i] & Imm) |
520dc8e8 | 857 | pe (x->op[i].imms); |
252b5132 | 858 | if (x->types[i] & Disp) |
520dc8e8 | 859 | pe (x->op[i].disps); |
252b5132 RH |
860 | } |
861 | } | |
862 | ||
863 | static void | |
864 | pte (t) | |
865 | template *t; | |
866 | { | |
867 | int i; | |
868 | fprintf (stdout, " %d operands ", t->operands); | |
47926f60 | 869 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
870 | if (t->extension_opcode != None) |
871 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
872 | if (t->opcode_modifier & D) | |
873 | fprintf (stdout, "D"); | |
874 | if (t->opcode_modifier & W) | |
875 | fprintf (stdout, "W"); | |
876 | fprintf (stdout, "\n"); | |
877 | for (i = 0; i < t->operands; i++) | |
878 | { | |
879 | fprintf (stdout, " #%d type ", i + 1); | |
880 | pt (t->operand_types[i]); | |
881 | fprintf (stdout, "\n"); | |
882 | } | |
883 | } | |
884 | ||
885 | static void | |
886 | pe (e) | |
887 | expressionS *e; | |
888 | { | |
24eab124 | 889 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
890 | fprintf (stdout, " add_number %ld (%lx)\n", |
891 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
892 | if (e->X_add_symbol) |
893 | { | |
894 | fprintf (stdout, " add_symbol "); | |
895 | ps (e->X_add_symbol); | |
896 | fprintf (stdout, "\n"); | |
897 | } | |
898 | if (e->X_op_symbol) | |
899 | { | |
900 | fprintf (stdout, " op_symbol "); | |
901 | ps (e->X_op_symbol); | |
902 | fprintf (stdout, "\n"); | |
903 | } | |
904 | } | |
905 | ||
906 | static void | |
907 | ps (s) | |
908 | symbolS *s; | |
909 | { | |
910 | fprintf (stdout, "%s type %s%s", | |
911 | S_GET_NAME (s), | |
912 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
913 | segment_name (S_GET_SEGMENT (s))); | |
914 | } | |
915 | ||
916 | struct type_name | |
917 | { | |
918 | unsigned int mask; | |
919 | char *tname; | |
920 | } | |
921 | ||
922 | type_names[] = | |
923 | { | |
924 | { Reg8, "r8" }, | |
925 | { Reg16, "r16" }, | |
926 | { Reg32, "r32" }, | |
927 | { Imm8, "i8" }, | |
928 | { Imm8S, "i8s" }, | |
929 | { Imm16, "i16" }, | |
930 | { Imm32, "i32" }, | |
931 | { Imm1, "i1" }, | |
932 | { BaseIndex, "BaseIndex" }, | |
933 | { Disp8, "d8" }, | |
934 | { Disp16, "d16" }, | |
935 | { Disp32, "d32" }, | |
936 | { InOutPortReg, "InOutPortReg" }, | |
937 | { ShiftCount, "ShiftCount" }, | |
938 | { Control, "control reg" }, | |
939 | { Test, "test reg" }, | |
940 | { Debug, "debug reg" }, | |
941 | { FloatReg, "FReg" }, | |
942 | { FloatAcc, "FAcc" }, | |
943 | { SReg2, "SReg2" }, | |
944 | { SReg3, "SReg3" }, | |
945 | { Acc, "Acc" }, | |
946 | { JumpAbsolute, "Jump Absolute" }, | |
947 | { RegMMX, "rMMX" }, | |
3f4438ab | 948 | { RegXMM, "rXMM" }, |
252b5132 RH |
949 | { EsSeg, "es" }, |
950 | { 0, "" } | |
951 | }; | |
952 | ||
953 | static void | |
954 | pt (t) | |
955 | unsigned int t; | |
956 | { | |
957 | register struct type_name *ty; | |
958 | ||
959 | if (t == Unknown) | |
960 | { | |
961 | fprintf (stdout, _("Unknown")); | |
962 | } | |
963 | else | |
964 | { | |
965 | for (ty = type_names; ty->mask; ty++) | |
966 | if (t & ty->mask) | |
967 | fprintf (stdout, "%s, ", ty->tname); | |
968 | } | |
969 | fflush (stdout); | |
970 | } | |
971 | ||
972 | #endif /* DEBUG386 */ | |
973 | \f | |
974 | int | |
975 | tc_i386_force_relocation (fixp) | |
976 | struct fix *fixp; | |
977 | { | |
978 | #ifdef BFD_ASSEMBLER | |
979 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
980 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
981 | return 1; | |
982 | return 0; | |
983 | #else | |
ce8a8b2f | 984 | /* For COFF. */ |
f6af82bd | 985 | return fixp->fx_r_type == 7; |
252b5132 RH |
986 | #endif |
987 | } | |
988 | ||
989 | #ifdef BFD_ASSEMBLER | |
990 | static bfd_reloc_code_real_type reloc | |
991 | PARAMS ((int, int, bfd_reloc_code_real_type)); | |
992 | ||
993 | static bfd_reloc_code_real_type | |
994 | reloc (size, pcrel, other) | |
995 | int size; | |
996 | int pcrel; | |
997 | bfd_reloc_code_real_type other; | |
998 | { | |
47926f60 KH |
999 | if (other != NO_RELOC) |
1000 | return other; | |
252b5132 RH |
1001 | |
1002 | if (pcrel) | |
1003 | { | |
1004 | switch (size) | |
1005 | { | |
1006 | case 1: return BFD_RELOC_8_PCREL; | |
1007 | case 2: return BFD_RELOC_16_PCREL; | |
1008 | case 4: return BFD_RELOC_32_PCREL; | |
1009 | } | |
d0b47220 | 1010 | as_bad (_("can not do %d byte pc-relative relocation"), size); |
252b5132 RH |
1011 | } |
1012 | else | |
1013 | { | |
1014 | switch (size) | |
1015 | { | |
1016 | case 1: return BFD_RELOC_8; | |
1017 | case 2: return BFD_RELOC_16; | |
1018 | case 4: return BFD_RELOC_32; | |
1019 | } | |
d0b47220 | 1020 | as_bad (_("can not do %d byte relocation"), size); |
252b5132 RH |
1021 | } |
1022 | ||
1023 | return BFD_RELOC_NONE; | |
1024 | } | |
1025 | ||
47926f60 KH |
1026 | /* Here we decide which fixups can be adjusted to make them relative to |
1027 | the beginning of the section instead of the symbol. Basically we need | |
1028 | to make sure that the dynamic relocations are done correctly, so in | |
1029 | some cases we force the original symbol to be used. */ | |
1030 | ||
252b5132 | 1031 | int |
c0c949c7 | 1032 | tc_i386_fix_adjustable (fixP) |
47926f60 | 1033 | fixS *fixP; |
252b5132 | 1034 | { |
6d249963 | 1035 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
79d292aa ILT |
1036 | /* Prevent all adjustments to global symbols, or else dynamic |
1037 | linking will not work correctly. */ | |
b98ef147 AM |
1038 | if (S_IS_EXTERNAL (fixP->fx_addsy) |
1039 | || S_IS_WEAK (fixP->fx_addsy)) | |
252b5132 RH |
1040 | return 0; |
1041 | #endif | |
ce8a8b2f | 1042 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
1043 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
1044 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
1045 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
1046 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1047 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1048 | return 0; | |
1049 | return 1; | |
1050 | } | |
1051 | #else | |
1052 | #define reloc(SIZE,PCREL,OTHER) 0 | |
1053 | #define BFD_RELOC_16 0 | |
1054 | #define BFD_RELOC_32 0 | |
1055 | #define BFD_RELOC_16_PCREL 0 | |
1056 | #define BFD_RELOC_32_PCREL 0 | |
1057 | #define BFD_RELOC_386_PLT32 0 | |
1058 | #define BFD_RELOC_386_GOT32 0 | |
1059 | #define BFD_RELOC_386_GOTOFF 0 | |
1060 | #endif | |
1061 | ||
47926f60 | 1062 | static int intel_float_operand PARAMS ((char *mnemonic)); |
b4cac588 AM |
1063 | |
1064 | static int | |
252b5132 RH |
1065 | intel_float_operand (mnemonic) |
1066 | char *mnemonic; | |
1067 | { | |
47926f60 | 1068 | if (mnemonic[0] == 'f' && mnemonic[1] == 'i') |
cc5ca5ce | 1069 | return 2; |
252b5132 RH |
1070 | |
1071 | if (mnemonic[0] == 'f') | |
1072 | return 1; | |
1073 | ||
1074 | return 0; | |
1075 | } | |
1076 | ||
1077 | /* This is the guts of the machine-dependent assembler. LINE points to a | |
1078 | machine dependent instruction. This function is supposed to emit | |
1079 | the frags/bytes it assembles to. */ | |
1080 | ||
1081 | void | |
1082 | md_assemble (line) | |
1083 | char *line; | |
1084 | { | |
47926f60 | 1085 | /* Points to template once we've found it. */ |
252b5132 RH |
1086 | const template *t; |
1087 | ||
1088 | /* Count the size of the instruction generated. */ | |
1089 | int insn_size = 0; | |
1090 | ||
1091 | int j; | |
1092 | ||
1093 | char mnemonic[MAX_MNEM_SIZE]; | |
1094 | ||
47926f60 | 1095 | /* Initialize globals. */ |
252b5132 RH |
1096 | memset (&i, '\0', sizeof (i)); |
1097 | for (j = 0; j < MAX_OPERANDS; j++) | |
1098 | i.disp_reloc[j] = NO_RELOC; | |
1099 | memset (disp_expressions, '\0', sizeof (disp_expressions)); | |
1100 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 1101 | save_stack_p = save_stack; |
252b5132 RH |
1102 | |
1103 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
1104 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 1105 | start of a (possibly prefixed) mnemonic. */ |
252b5132 RH |
1106 | { |
1107 | char *l = line; | |
1108 | char *token_start = l; | |
1109 | char *mnem_p; | |
1110 | ||
47926f60 | 1111 | /* Non-zero if we found a prefix only acceptable with string insns. */ |
252b5132 RH |
1112 | const char *expecting_string_instruction = NULL; |
1113 | ||
1114 | while (1) | |
1115 | { | |
1116 | mnem_p = mnemonic; | |
1117 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
1118 | { | |
1119 | mnem_p++; | |
1120 | if (mnem_p >= mnemonic + sizeof (mnemonic)) | |
1121 | { | |
e413e4e9 | 1122 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1123 | return; |
1124 | } | |
1125 | l++; | |
1126 | } | |
1127 | if (!is_space_char (*l) | |
1128 | && *l != END_OF_INSN | |
1129 | && *l != PREFIX_SEPARATOR) | |
1130 | { | |
1131 | as_bad (_("invalid character %s in mnemonic"), | |
1132 | output_invalid (*l)); | |
1133 | return; | |
1134 | } | |
1135 | if (token_start == l) | |
1136 | { | |
1137 | if (*l == PREFIX_SEPARATOR) | |
1138 | as_bad (_("expecting prefix; got nothing")); | |
1139 | else | |
1140 | as_bad (_("expecting mnemonic; got nothing")); | |
1141 | return; | |
1142 | } | |
1143 | ||
1144 | /* Look up instruction (or prefix) via hash table. */ | |
1145 | current_templates = hash_find (op_hash, mnemonic); | |
1146 | ||
1147 | if (*l != END_OF_INSN | |
1148 | && (! is_space_char (*l) || l[1] != END_OF_INSN) | |
1149 | && current_templates | |
1150 | && (current_templates->start->opcode_modifier & IsPrefix)) | |
1151 | { | |
1152 | /* If we are in 16-bit mode, do not allow addr16 or data16. | |
1153 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
1154 | if ((current_templates->start->opcode_modifier & (Size16 | Size32)) | |
1155 | && (((current_templates->start->opcode_modifier & Size32) != 0) | |
1156 | ^ flag_16bit_code)) | |
1157 | { | |
1158 | as_bad (_("redundant %s prefix"), | |
1159 | current_templates->start->name); | |
1160 | return; | |
1161 | } | |
1162 | /* Add prefix, checking for repeated prefixes. */ | |
1163 | switch (add_prefix (current_templates->start->base_opcode)) | |
1164 | { | |
1165 | case 0: | |
1166 | return; | |
1167 | case 2: | |
47926f60 | 1168 | expecting_string_instruction = current_templates->start->name; |
252b5132 RH |
1169 | break; |
1170 | } | |
1171 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
1172 | token_start = ++l; | |
1173 | } | |
1174 | else | |
1175 | break; | |
1176 | } | |
1177 | ||
1178 | if (!current_templates) | |
1179 | { | |
24eab124 | 1180 | /* See if we can get a match by trimming off a suffix. */ |
252b5132 RH |
1181 | switch (mnem_p[-1]) |
1182 | { | |
252b5132 RH |
1183 | case WORD_MNEM_SUFFIX: |
1184 | case BYTE_MNEM_SUFFIX: | |
252b5132 RH |
1185 | i.suffix = mnem_p[-1]; |
1186 | mnem_p[-1] = '\0'; | |
1187 | current_templates = hash_find (op_hash, mnemonic); | |
24eab124 | 1188 | break; |
f16b83df JH |
1189 | case SHORT_MNEM_SUFFIX: |
1190 | case LONG_MNEM_SUFFIX: | |
1191 | if (!intel_syntax) | |
1192 | { | |
1193 | i.suffix = mnem_p[-1]; | |
1194 | mnem_p[-1] = '\0'; | |
1195 | current_templates = hash_find (op_hash, mnemonic); | |
1196 | } | |
1197 | break; | |
24eab124 | 1198 | |
ce8a8b2f | 1199 | /* Intel Syntax. */ |
f16b83df | 1200 | case 'd': |
24eab124 AM |
1201 | if (intel_syntax) |
1202 | { | |
f16b83df JH |
1203 | if (intel_float_operand (mnemonic)) |
1204 | i.suffix = SHORT_MNEM_SUFFIX; | |
1205 | else | |
1206 | i.suffix = LONG_MNEM_SUFFIX; | |
24eab124 AM |
1207 | mnem_p[-1] = '\0'; |
1208 | current_templates = hash_find (op_hash, mnemonic); | |
24eab124 | 1209 | } |
f16b83df | 1210 | break; |
252b5132 RH |
1211 | } |
1212 | if (!current_templates) | |
1213 | { | |
e413e4e9 | 1214 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1215 | return; |
1216 | } | |
1217 | } | |
1218 | ||
e413e4e9 AM |
1219 | /* Check if instruction is supported on specified architecture. */ |
1220 | if (cpu_arch_flags != 0) | |
1221 | { | |
47926f60 | 1222 | if (current_templates->start->cpu_flags & ~cpu_arch_flags) |
e413e4e9 AM |
1223 | { |
1224 | as_warn (_("`%s' is not supported on `%s'"), | |
1225 | current_templates->start->name, cpu_arch_name); | |
1226 | } | |
47926f60 | 1227 | else if ((Cpu386 & ~cpu_arch_flags) && !flag_16bit_code) |
e413e4e9 AM |
1228 | { |
1229 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
1230 | } | |
1231 | } | |
1232 | ||
ce8a8b2f | 1233 | /* Check for rep/repne without a string instruction. */ |
252b5132 RH |
1234 | if (expecting_string_instruction |
1235 | && !(current_templates->start->opcode_modifier & IsString)) | |
1236 | { | |
1237 | as_bad (_("expecting string instruction after `%s'"), | |
1238 | expecting_string_instruction); | |
1239 | return; | |
1240 | } | |
1241 | ||
47926f60 | 1242 | /* There may be operands to parse. */ |
252b5132 RH |
1243 | if (*l != END_OF_INSN) |
1244 | { | |
47926f60 | 1245 | /* 1 if operand is pending after ','. */ |
252b5132 RH |
1246 | unsigned int expecting_operand = 0; |
1247 | ||
47926f60 | 1248 | /* Non-zero if operand parens not balanced. */ |
252b5132 RH |
1249 | unsigned int paren_not_balanced; |
1250 | ||
1251 | do | |
1252 | { | |
ce8a8b2f | 1253 | /* Skip optional white space before operand. */ |
252b5132 RH |
1254 | if (is_space_char (*l)) |
1255 | ++l; | |
1256 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
1257 | { | |
1258 | as_bad (_("invalid character %s before operand %d"), | |
1259 | output_invalid (*l), | |
1260 | i.operands + 1); | |
1261 | return; | |
1262 | } | |
1263 | token_start = l; /* after white space */ | |
1264 | paren_not_balanced = 0; | |
1265 | while (paren_not_balanced || *l != ',') | |
1266 | { | |
1267 | if (*l == END_OF_INSN) | |
1268 | { | |
1269 | if (paren_not_balanced) | |
1270 | { | |
24eab124 | 1271 | if (!intel_syntax) |
252b5132 RH |
1272 | as_bad (_("unbalanced parenthesis in operand %d."), |
1273 | i.operands + 1); | |
24eab124 | 1274 | else |
252b5132 RH |
1275 | as_bad (_("unbalanced brackets in operand %d."), |
1276 | i.operands + 1); | |
1277 | return; | |
1278 | } | |
1279 | else | |
1280 | break; /* we are done */ | |
1281 | } | |
1282 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
1283 | { | |
1284 | as_bad (_("invalid character %s in operand %d"), | |
1285 | output_invalid (*l), | |
1286 | i.operands + 1); | |
1287 | return; | |
1288 | } | |
24eab124 AM |
1289 | if (!intel_syntax) |
1290 | { | |
252b5132 RH |
1291 | if (*l == '(') |
1292 | ++paren_not_balanced; | |
1293 | if (*l == ')') | |
1294 | --paren_not_balanced; | |
24eab124 AM |
1295 | } |
1296 | else | |
1297 | { | |
252b5132 RH |
1298 | if (*l == '[') |
1299 | ++paren_not_balanced; | |
1300 | if (*l == ']') | |
1301 | --paren_not_balanced; | |
24eab124 | 1302 | } |
252b5132 RH |
1303 | l++; |
1304 | } | |
1305 | if (l != token_start) | |
47926f60 | 1306 | { /* Yes, we've read in another operand. */ |
252b5132 RH |
1307 | unsigned int operand_ok; |
1308 | this_operand = i.operands++; | |
1309 | if (i.operands > MAX_OPERANDS) | |
1310 | { | |
1311 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
1312 | MAX_OPERANDS); | |
1313 | return; | |
1314 | } | |
47926f60 | 1315 | /* Now parse operand adding info to 'i' as we go along. */ |
252b5132 RH |
1316 | END_STRING_AND_SAVE (l); |
1317 | ||
24eab124 | 1318 | if (intel_syntax) |
47926f60 KH |
1319 | operand_ok = |
1320 | i386_intel_operand (token_start, | |
1321 | intel_float_operand (mnemonic)); | |
24eab124 AM |
1322 | else |
1323 | operand_ok = i386_operand (token_start); | |
252b5132 | 1324 | |
ce8a8b2f | 1325 | RESTORE_END_STRING (l); |
252b5132 RH |
1326 | if (!operand_ok) |
1327 | return; | |
1328 | } | |
1329 | else | |
1330 | { | |
1331 | if (expecting_operand) | |
1332 | { | |
1333 | expecting_operand_after_comma: | |
1334 | as_bad (_("expecting operand after ','; got nothing")); | |
1335 | return; | |
1336 | } | |
1337 | if (*l == ',') | |
1338 | { | |
1339 | as_bad (_("expecting operand before ','; got nothing")); | |
1340 | return; | |
1341 | } | |
1342 | } | |
1343 | ||
ce8a8b2f | 1344 | /* Now *l must be either ',' or END_OF_INSN. */ |
252b5132 RH |
1345 | if (*l == ',') |
1346 | { | |
1347 | if (*++l == END_OF_INSN) | |
ce8a8b2f AM |
1348 | { |
1349 | /* Just skip it, if it's \n complain. */ | |
252b5132 RH |
1350 | goto expecting_operand_after_comma; |
1351 | } | |
1352 | expecting_operand = 1; | |
1353 | } | |
1354 | } | |
ce8a8b2f | 1355 | while (*l != END_OF_INSN); |
252b5132 RH |
1356 | } |
1357 | } | |
1358 | ||
1359 | /* Now we've parsed the mnemonic into a set of templates, and have the | |
1360 | operands at hand. | |
1361 | ||
1362 | Next, we find a template that matches the given insn, | |
1363 | making sure the overlap of the given operands types is consistent | |
47926f60 | 1364 | with the template operand types. */ |
252b5132 RH |
1365 | |
1366 | #define MATCH(overlap, given, template) \ | |
3138f287 AM |
1367 | ((overlap & ~JumpAbsolute) \ |
1368 | && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute))) | |
252b5132 RH |
1369 | |
1370 | /* If given types r0 and r1 are registers they must be of the same type | |
1371 | unless the expected operand type register overlap is null. | |
1372 | Note that Acc in a template matches every size of reg. */ | |
1373 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ | |
1374 | ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \ | |
1375 | ((g0) & Reg) == ((g1) & Reg) || \ | |
1376 | ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) | |
1377 | ||
1378 | { | |
1379 | register unsigned int overlap0, overlap1; | |
252b5132 RH |
1380 | unsigned int overlap2; |
1381 | unsigned int found_reverse_match; | |
1382 | int suffix_check; | |
1383 | ||
cc5ca5ce AM |
1384 | /* All intel opcodes have reversed operands except for "bound" and |
1385 | "enter". We also don't reverse intersegment "jmp" and "call" | |
1386 | instructions with 2 immediate operands so that the immediate segment | |
1387 | precedes the offset, as it does when in AT&T mode. "enter" and the | |
1388 | intersegment "jmp" and "call" instructions are the only ones that | |
1389 | have two immediate operands. */ | |
520dc8e8 | 1390 | if (intel_syntax && i.operands > 1 |
cc5ca5ce AM |
1391 | && (strcmp (mnemonic, "bound") != 0) |
1392 | && !((i.types[0] & Imm) && (i.types[1] & Imm))) | |
252b5132 | 1393 | { |
520dc8e8 | 1394 | union i386_op temp_op; |
24eab124 | 1395 | unsigned int temp_type; |
76a0ddac DN |
1396 | #ifdef BFD_ASSEMBLER |
1397 | enum bfd_reloc_code_real temp_disp_reloc; | |
1398 | #else | |
1399 | int temp_disp_reloc; | |
1400 | #endif | |
24eab124 | 1401 | int xchg1 = 0; |
ab9da554 | 1402 | int xchg2 = 0; |
252b5132 | 1403 | |
24eab124 AM |
1404 | if (i.operands == 2) |
1405 | { | |
1406 | xchg1 = 0; | |
1407 | xchg2 = 1; | |
1408 | } | |
1409 | else if (i.operands == 3) | |
1410 | { | |
1411 | xchg1 = 0; | |
1412 | xchg2 = 2; | |
1413 | } | |
520dc8e8 AM |
1414 | temp_type = i.types[xchg2]; |
1415 | i.types[xchg2] = i.types[xchg1]; | |
1416 | i.types[xchg1] = temp_type; | |
1417 | temp_op = i.op[xchg2]; | |
1418 | i.op[xchg2] = i.op[xchg1]; | |
1419 | i.op[xchg1] = temp_op; | |
76a0ddac DN |
1420 | temp_disp_reloc = i.disp_reloc[xchg2]; |
1421 | i.disp_reloc[xchg2] = i.disp_reloc[xchg1]; | |
1422 | i.disp_reloc[xchg1] = temp_disp_reloc; | |
36bf8ab9 AM |
1423 | |
1424 | if (i.mem_operands == 2) | |
1425 | { | |
1426 | const seg_entry *temp_seg; | |
1427 | temp_seg = i.seg[0]; | |
1428 | i.seg[0] = i.seg[1]; | |
1429 | i.seg[1] = temp_seg; | |
1430 | } | |
24eab124 | 1431 | } |
773f551c AM |
1432 | |
1433 | if (i.imm_operands) | |
1434 | { | |
1435 | /* Try to ensure constant immediates are represented in the smallest | |
1436 | opcode possible. */ | |
1437 | char guess_suffix = 0; | |
1438 | int op; | |
1439 | ||
1440 | if (i.suffix) | |
1441 | guess_suffix = i.suffix; | |
1442 | else if (i.reg_operands) | |
1443 | { | |
1444 | /* Figure out a suffix from the last register operand specified. | |
1445 | We can't do this properly yet, ie. excluding InOutPortReg, | |
1446 | but the following works for instructions with immediates. | |
1447 | In any case, we can't set i.suffix yet. */ | |
47926f60 | 1448 | for (op = i.operands; --op >= 0;) |
773f551c AM |
1449 | if (i.types[op] & Reg) |
1450 | { | |
1451 | if (i.types[op] & Reg8) | |
1452 | guess_suffix = BYTE_MNEM_SUFFIX; | |
1453 | else if (i.types[op] & Reg16) | |
1454 | guess_suffix = WORD_MNEM_SUFFIX; | |
1455 | break; | |
1456 | } | |
1457 | } | |
726c5dcd AM |
1458 | else if (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) |
1459 | guess_suffix = WORD_MNEM_SUFFIX; | |
1460 | ||
47926f60 | 1461 | for (op = i.operands; --op >= 0;) |
773f551c AM |
1462 | if ((i.types[op] & Imm) |
1463 | && i.op[op].imms->X_op == O_constant) | |
1464 | { | |
1465 | /* If a suffix is given, this operand may be shortened. */ | |
1466 | switch (guess_suffix) | |
1467 | { | |
1468 | case WORD_MNEM_SUFFIX: | |
1469 | i.types[op] |= Imm16; | |
1470 | break; | |
1471 | case BYTE_MNEM_SUFFIX: | |
1472 | i.types[op] |= Imm16 | Imm8 | Imm8S; | |
1473 | break; | |
1474 | } | |
1475 | ||
1476 | /* If this operand is at most 16 bits, convert it to a | |
1477 | signed 16 bit number before trying to see whether it will | |
1478 | fit in an even smaller size. This allows a 16-bit operand | |
1479 | such as $0xffe0 to be recognised as within Imm8S range. */ | |
1480 | if ((i.types[op] & Imm16) | |
1481 | && (i.op[op].imms->X_add_number & ~(offsetT)0xffff) == 0) | |
1482 | { | |
1483 | i.op[op].imms->X_add_number = | |
1484 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
1485 | } | |
1486 | i.types[op] |= smallest_imm_type ((long) i.op[op].imms->X_add_number); | |
1487 | } | |
1488 | } | |
1489 | ||
45288df1 AM |
1490 | if (i.disp_operands) |
1491 | { | |
1492 | /* Try to use the smallest displacement type too. */ | |
1493 | int op; | |
1494 | ||
47926f60 | 1495 | for (op = i.operands; --op >= 0;) |
45288df1 AM |
1496 | if ((i.types[op] & Disp) |
1497 | && i.op[op].imms->X_op == O_constant) | |
1498 | { | |
1499 | offsetT disp = i.op[op].disps->X_add_number; | |
1500 | ||
1501 | if (i.types[op] & Disp16) | |
1502 | { | |
1503 | /* We know this operand is at most 16 bits, so | |
1504 | convert to a signed 16 bit number before trying | |
1505 | to see whether it will fit in an even smaller | |
1506 | size. */ | |
47926f60 | 1507 | |
45288df1 AM |
1508 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); |
1509 | } | |
1510 | if (fits_in_signed_byte (disp)) | |
1511 | i.types[op] |= Disp8; | |
1512 | } | |
1513 | } | |
1514 | ||
252b5132 RH |
1515 | overlap0 = 0; |
1516 | overlap1 = 0; | |
1517 | overlap2 = 0; | |
1518 | found_reverse_match = 0; | |
1519 | suffix_check = (i.suffix == BYTE_MNEM_SUFFIX | |
1520 | ? No_bSuf | |
1521 | : (i.suffix == WORD_MNEM_SUFFIX | |
1522 | ? No_wSuf | |
1523 | : (i.suffix == SHORT_MNEM_SUFFIX | |
1524 | ? No_sSuf | |
1525 | : (i.suffix == LONG_MNEM_SUFFIX | |
24eab124 | 1526 | ? No_lSuf |
f16b83df | 1527 | : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0))))); |
252b5132 RH |
1528 | |
1529 | for (t = current_templates->start; | |
1530 | t < current_templates->end; | |
1531 | t++) | |
1532 | { | |
47926f60 | 1533 | /* Must have right number of operands. */ |
252b5132 RH |
1534 | if (i.operands != t->operands) |
1535 | continue; | |
1536 | ||
7f3f1ea2 AM |
1537 | /* Check the suffix, except for some instructions in intel mode. */ |
1538 | if ((t->opcode_modifier & suffix_check) | |
fa2255cb DN |
1539 | && !(intel_syntax |
1540 | && (t->opcode_modifier & IgnoreSize)) | |
7f3f1ea2 AM |
1541 | && !(intel_syntax |
1542 | && t->base_opcode == 0xd9 | |
ce8a8b2f AM |
1543 | && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */ |
1544 | || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */ | |
24eab124 | 1545 | continue; |
252b5132 RH |
1546 | |
1547 | else if (!t->operands) | |
47926f60 KH |
1548 | /* 0 operands always matches. */ |
1549 | break; | |
252b5132 RH |
1550 | |
1551 | overlap0 = i.types[0] & t->operand_types[0]; | |
1552 | switch (t->operands) | |
1553 | { | |
1554 | case 1: | |
1555 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])) | |
1556 | continue; | |
1557 | break; | |
1558 | case 2: | |
1559 | case 3: | |
1560 | overlap1 = i.types[1] & t->operand_types[1]; | |
1561 | if (!MATCH (overlap0, i.types[0], t->operand_types[0]) | |
1562 | || !MATCH (overlap1, i.types[1], t->operand_types[1]) | |
1563 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1564 | t->operand_types[0], | |
1565 | overlap1, i.types[1], | |
1566 | t->operand_types[1])) | |
1567 | { | |
47926f60 | 1568 | /* Check if other direction is valid ... */ |
252b5132 RH |
1569 | if ((t->opcode_modifier & (D|FloatD)) == 0) |
1570 | continue; | |
1571 | ||
47926f60 | 1572 | /* Try reversing direction of operands. */ |
252b5132 RH |
1573 | overlap0 = i.types[0] & t->operand_types[1]; |
1574 | overlap1 = i.types[1] & t->operand_types[0]; | |
1575 | if (!MATCH (overlap0, i.types[0], t->operand_types[1]) | |
1576 | || !MATCH (overlap1, i.types[1], t->operand_types[0]) | |
1577 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1578 | t->operand_types[1], | |
1579 | overlap1, i.types[1], | |
1580 | t->operand_types[0])) | |
1581 | { | |
47926f60 | 1582 | /* Does not match either direction. */ |
252b5132 RH |
1583 | continue; |
1584 | } | |
1585 | /* found_reverse_match holds which of D or FloatDR | |
1586 | we've found. */ | |
1587 | found_reverse_match = t->opcode_modifier & (D|FloatDR); | |
1588 | break; | |
1589 | } | |
47926f60 | 1590 | /* Found a forward 2 operand match here. */ |
252b5132 RH |
1591 | if (t->operands == 3) |
1592 | { | |
1593 | /* Here we make use of the fact that there are no | |
1594 | reverse match 3 operand instructions, and all 3 | |
1595 | operand instructions only need to be checked for | |
1596 | register consistency between operands 2 and 3. */ | |
1597 | overlap2 = i.types[2] & t->operand_types[2]; | |
1598 | if (!MATCH (overlap2, i.types[2], t->operand_types[2]) | |
1599 | || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], | |
1600 | t->operand_types[1], | |
1601 | overlap2, i.types[2], | |
24eab124 | 1602 | t->operand_types[2])) |
252b5132 | 1603 | |
24eab124 | 1604 | continue; |
252b5132 | 1605 | } |
47926f60 | 1606 | /* Found either forward/reverse 2 or 3 operand match here: |
ce8a8b2f | 1607 | slip through to break. */ |
252b5132 | 1608 | } |
47926f60 KH |
1609 | /* We've found a match; break out of loop. */ |
1610 | break; | |
ce8a8b2f | 1611 | } |
252b5132 | 1612 | if (t == current_templates->end) |
47926f60 KH |
1613 | { |
1614 | /* We found no match. */ | |
252b5132 RH |
1615 | as_bad (_("suffix or operands invalid for `%s'"), |
1616 | current_templates->start->name); | |
1617 | return; | |
1618 | } | |
1619 | ||
a38cf1db | 1620 | if (!quiet_warnings) |
3138f287 | 1621 | { |
a38cf1db AM |
1622 | if (!intel_syntax |
1623 | && ((i.types[0] & JumpAbsolute) | |
1624 | != (t->operand_types[0] & JumpAbsolute))) | |
1625 | { | |
1626 | as_warn (_("indirect %s without `*'"), t->name); | |
1627 | } | |
3138f287 | 1628 | |
a38cf1db AM |
1629 | if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) |
1630 | == (IsPrefix|IgnoreSize)) | |
1631 | { | |
1632 | /* Warn them that a data or address size prefix doesn't | |
1633 | affect assembly of the next line of code. */ | |
1634 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
1635 | } | |
252b5132 RH |
1636 | } |
1637 | ||
1638 | /* Copy the template we found. */ | |
1639 | i.tm = *t; | |
1640 | if (found_reverse_match) | |
1641 | { | |
7f3f1ea2 AM |
1642 | /* If we found a reverse match we must alter the opcode |
1643 | direction bit. found_reverse_match holds bits to change | |
1644 | (different for int & float insns). */ | |
1645 | ||
1646 | i.tm.base_opcode ^= found_reverse_match; | |
1647 | ||
252b5132 RH |
1648 | i.tm.operand_types[0] = t->operand_types[1]; |
1649 | i.tm.operand_types[1] = t->operand_types[0]; | |
1650 | } | |
1651 | ||
d0b47220 AM |
1652 | /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ |
1653 | if (SYSV386_COMPAT | |
7f3f1ea2 AM |
1654 | && intel_syntax |
1655 | && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) | |
1656 | i.tm.base_opcode ^= FloatR; | |
252b5132 RH |
1657 | |
1658 | if (i.tm.opcode_modifier & FWait) | |
1659 | if (! add_prefix (FWAIT_OPCODE)) | |
1660 | return; | |
1661 | ||
ce8a8b2f | 1662 | /* Check string instruction segment overrides. */ |
252b5132 RH |
1663 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) |
1664 | { | |
1665 | int mem_op = (i.types[0] & AnyMem) ? 0 : 1; | |
1666 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) | |
1667 | { | |
1668 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
1669 | { | |
1670 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1671 | i.tm.name, | |
1672 | mem_op + 1); | |
1673 | return; | |
1674 | } | |
1675 | /* There's only ever one segment override allowed per instruction. | |
1676 | This instruction possibly has a legal segment override on the | |
1677 | second operand, so copy the segment to where non-string | |
1678 | instructions store it, allowing common code. */ | |
1679 | i.seg[0] = i.seg[1]; | |
1680 | } | |
1681 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) | |
1682 | { | |
1683 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
1684 | { | |
1685 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1686 | i.tm.name, | |
1687 | mem_op + 2); | |
1688 | return; | |
1689 | } | |
1690 | } | |
1691 | } | |
1692 | ||
1693 | /* If matched instruction specifies an explicit instruction mnemonic | |
1694 | suffix, use it. */ | |
1695 | if (i.tm.opcode_modifier & (Size16 | Size32)) | |
1696 | { | |
1697 | if (i.tm.opcode_modifier & Size16) | |
1698 | i.suffix = WORD_MNEM_SUFFIX; | |
1699 | else | |
add0c677 | 1700 | i.suffix = LONG_MNEM_SUFFIX; |
252b5132 RH |
1701 | } |
1702 | else if (i.reg_operands) | |
1703 | { | |
1704 | /* If there's no instruction mnemonic suffix we try to invent one | |
47926f60 | 1705 | based on register operands. */ |
252b5132 RH |
1706 | if (!i.suffix) |
1707 | { | |
1708 | /* We take i.suffix from the last register operand specified, | |
1709 | Destination register type is more significant than source | |
1710 | register type. */ | |
1711 | int op; | |
47926f60 | 1712 | for (op = i.operands; --op >= 0;) |
cc5ca5ce AM |
1713 | if ((i.types[op] & Reg) |
1714 | && !(i.tm.operand_types[op] & InOutPortReg)) | |
252b5132 RH |
1715 | { |
1716 | i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : | |
1717 | (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : | |
add0c677 | 1718 | LONG_MNEM_SUFFIX); |
252b5132 RH |
1719 | break; |
1720 | } | |
1721 | } | |
1722 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
1723 | { | |
1724 | int op; | |
47926f60 | 1725 | for (op = i.operands; --op >= 0;) |
252b5132 RH |
1726 | { |
1727 | /* If this is an eight bit register, it's OK. If it's | |
1728 | the 16 or 32 bit version of an eight bit register, | |
47926f60 | 1729 | we will just use the low portion, and that's OK too. */ |
252b5132 RH |
1730 | if (i.types[op] & Reg8) |
1731 | continue; | |
1732 | ||
47926f60 | 1733 | /* movzx and movsx should not generate this warning. */ |
24eab124 AM |
1734 | if (intel_syntax |
1735 | && (i.tm.base_opcode == 0xfb7 | |
1736 | || i.tm.base_opcode == 0xfb6 | |
1737 | || i.tm.base_opcode == 0xfbe | |
1738 | || i.tm.base_opcode == 0xfbf)) | |
1739 | continue; | |
252b5132 | 1740 | |
520dc8e8 | 1741 | if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4 |
252b5132 RH |
1742 | #if 0 |
1743 | /* Check that the template allows eight bit regs | |
1744 | This kills insns such as `orb $1,%edx', which | |
1745 | maybe should be allowed. */ | |
1746 | && (i.tm.operand_types[op] & (Reg8|InOutPortReg)) | |
1747 | #endif | |
1748 | ) | |
1749 | { | |
1750 | #if REGISTER_WARNINGS | |
a38cf1db AM |
1751 | if (!quiet_warnings |
1752 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
252b5132 | 1753 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), |
520dc8e8 AM |
1754 | (i.op[op].regs - (i.types[op] & Reg16 ? 8 : 16))->reg_name, |
1755 | i.op[op].regs->reg_name, | |
252b5132 RH |
1756 | i.suffix); |
1757 | #endif | |
1758 | continue; | |
1759 | } | |
ce8a8b2f | 1760 | /* Any other register is bad. */ |
3f4438ab AM |
1761 | if (i.types[op] & (Reg | RegMMX | RegXMM |
1762 | | SReg2 | SReg3 | |
1763 | | Control | Debug | Test | |
1764 | | FloatReg | FloatAcc)) | |
252b5132 RH |
1765 | { |
1766 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 1767 | i.op[op].regs->reg_name, |
252b5132 RH |
1768 | i.tm.name, |
1769 | i.suffix); | |
1770 | return; | |
1771 | } | |
1772 | } | |
1773 | } | |
add0c677 | 1774 | else if (i.suffix == LONG_MNEM_SUFFIX) |
252b5132 RH |
1775 | { |
1776 | int op; | |
47926f60 KH |
1777 | |
1778 | for (op = i.operands; --op >= 0;) | |
252b5132 RH |
1779 | /* Reject eight bit registers, except where the template |
1780 | requires them. (eg. movzb) */ | |
1781 | if ((i.types[op] & Reg8) != 0 | |
47926f60 | 1782 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) |
252b5132 RH |
1783 | { |
1784 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 1785 | i.op[op].regs->reg_name, |
252b5132 RH |
1786 | i.tm.name, |
1787 | i.suffix); | |
1788 | return; | |
1789 | } | |
1790 | #if REGISTER_WARNINGS | |
1791 | /* Warn if the e prefix on a general reg is missing. */ | |
a38cf1db AM |
1792 | else if (!quiet_warnings |
1793 | && (i.types[op] & Reg16) != 0 | |
252b5132 RH |
1794 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) |
1795 | { | |
1796 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
520dc8e8 AM |
1797 | (i.op[op].regs + 8)->reg_name, |
1798 | i.op[op].regs->reg_name, | |
252b5132 RH |
1799 | i.suffix); |
1800 | } | |
1801 | #endif | |
1802 | } | |
1803 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
1804 | { | |
1805 | int op; | |
47926f60 | 1806 | for (op = i.operands; --op >= 0;) |
252b5132 RH |
1807 | /* Reject eight bit registers, except where the template |
1808 | requires them. (eg. movzb) */ | |
1809 | if ((i.types[op] & Reg8) != 0 | |
1810 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
1811 | { | |
1812 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 1813 | i.op[op].regs->reg_name, |
252b5132 RH |
1814 | i.tm.name, |
1815 | i.suffix); | |
1816 | return; | |
1817 | } | |
1818 | #if REGISTER_WARNINGS | |
1819 | /* Warn if the e prefix on a general reg is present. */ | |
a38cf1db AM |
1820 | else if (!quiet_warnings |
1821 | && (i.types[op] & Reg32) != 0 | |
252b5132 RH |
1822 | && (i.tm.operand_types[op] & (Reg16|Acc)) != 0) |
1823 | { | |
1824 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
520dc8e8 AM |
1825 | (i.op[op].regs - 8)->reg_name, |
1826 | i.op[op].regs->reg_name, | |
252b5132 RH |
1827 | i.suffix); |
1828 | } | |
1829 | #endif | |
1830 | } | |
fa2255cb DN |
1831 | else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize)) |
1832 | /* Do nothing if the instruction is going to ignore the prefix. */ | |
1833 | ; | |
252b5132 | 1834 | else |
47926f60 | 1835 | abort (); |
252b5132 | 1836 | } |
eecb386c AM |
1837 | else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix) |
1838 | { | |
1839 | i.suffix = stackop_size; | |
1840 | } | |
252b5132 RH |
1841 | |
1842 | /* Make still unresolved immediate matches conform to size of immediate | |
1843 | given in i.suffix. Note: overlap2 cannot be an immediate! */ | |
1844 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32)) | |
1845 | && overlap0 != Imm8 && overlap0 != Imm8S | |
1846 | && overlap0 != Imm16 && overlap0 != Imm32) | |
1847 | { | |
1848 | if (i.suffix) | |
1849 | { | |
24eab124 AM |
1850 | overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
1851 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); | |
252b5132 RH |
1852 | } |
1853 | else if (overlap0 == (Imm16 | Imm32)) | |
1854 | { | |
24eab124 | 1855 | overlap0 = |
252b5132 RH |
1856 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; |
1857 | } | |
1858 | else | |
1859 | { | |
1860 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); | |
1861 | return; | |
1862 | } | |
1863 | } | |
1864 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32)) | |
1865 | && overlap1 != Imm8 && overlap1 != Imm8S | |
1866 | && overlap1 != Imm16 && overlap1 != Imm32) | |
1867 | { | |
1868 | if (i.suffix) | |
1869 | { | |
24eab124 AM |
1870 | overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
1871 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); | |
252b5132 RH |
1872 | } |
1873 | else if (overlap1 == (Imm16 | Imm32)) | |
1874 | { | |
24eab124 | 1875 | overlap1 = |
252b5132 RH |
1876 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; |
1877 | } | |
1878 | else | |
1879 | { | |
1880 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); | |
1881 | return; | |
1882 | } | |
1883 | } | |
1884 | assert ((overlap2 & Imm) == 0); | |
1885 | ||
1886 | i.types[0] = overlap0; | |
1887 | if (overlap0 & ImplicitRegister) | |
1888 | i.reg_operands--; | |
1889 | if (overlap0 & Imm1) | |
ce8a8b2f | 1890 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 RH |
1891 | |
1892 | i.types[1] = overlap1; | |
1893 | if (overlap1 & ImplicitRegister) | |
1894 | i.reg_operands--; | |
1895 | ||
1896 | i.types[2] = overlap2; | |
1897 | if (overlap2 & ImplicitRegister) | |
1898 | i.reg_operands--; | |
1899 | ||
1900 | /* Finalize opcode. First, we change the opcode based on the operand | |
1901 | size given by i.suffix: We need not change things for byte insns. */ | |
1902 | ||
1903 | if (!i.suffix && (i.tm.opcode_modifier & W)) | |
1904 | { | |
1905 | as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); | |
1906 | return; | |
1907 | } | |
1908 | ||
ce8a8b2f | 1909 | /* For movzx and movsx, need to check the register type. */ |
252b5132 | 1910 | if (intel_syntax |
24eab124 | 1911 | && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)) |
252b5132 | 1912 | if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX) |
24eab124 AM |
1913 | { |
1914 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
252b5132 | 1915 | |
520dc8e8 | 1916 | if ((i.op[1].regs->reg_type & Reg16) != 0) |
24eab124 AM |
1917 | if (!add_prefix (prefix)) |
1918 | return; | |
1919 | } | |
252b5132 RH |
1920 | |
1921 | if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
1922 | { | |
1923 | /* It's not a byte, select word/dword operation. */ | |
1924 | if (i.tm.opcode_modifier & W) | |
1925 | { | |
1926 | if (i.tm.opcode_modifier & ShortForm) | |
1927 | i.tm.base_opcode |= 8; | |
1928 | else | |
1929 | i.tm.base_opcode |= 1; | |
1930 | } | |
1931 | /* Now select between word & dword operations via the operand | |
1932 | size prefix, except for instructions that will ignore this | |
1933 | prefix anyway. */ | |
f16b83df | 1934 | if ((i.suffix == LONG_MNEM_SUFFIX) == flag_16bit_code |
252b5132 RH |
1935 | && !(i.tm.opcode_modifier & IgnoreSize)) |
1936 | { | |
1937 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
1938 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ | |
1939 | prefix = ADDR_PREFIX_OPCODE; | |
1940 | ||
1941 | if (! add_prefix (prefix)) | |
1942 | return; | |
1943 | } | |
1944 | /* Size floating point instruction. */ | |
f16b83df | 1945 | if (i.suffix == LONG_MNEM_SUFFIX) |
252b5132 RH |
1946 | { |
1947 | if (i.tm.opcode_modifier & FloatMF) | |
1948 | i.tm.base_opcode ^= 4; | |
1949 | } | |
252b5132 RH |
1950 | } |
1951 | ||
3f4438ab | 1952 | if (i.tm.opcode_modifier & ImmExt) |
252b5132 | 1953 | { |
3f4438ab AM |
1954 | /* These AMD 3DNow! and Intel Katmai New Instructions have an |
1955 | opcode suffix which is coded in the same place as an 8-bit | |
1956 | immediate field would be. Here we fake an 8-bit immediate | |
1957 | operand from the opcode suffix stored in tm.extension_opcode. */ | |
252b5132 RH |
1958 | |
1959 | expressionS *exp; | |
1960 | ||
47926f60 | 1961 | assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); |
252b5132 RH |
1962 | |
1963 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 1964 | i.op[i.operands].imms = exp; |
252b5132 RH |
1965 | i.types[i.operands++] = Imm8; |
1966 | exp->X_op = O_constant; | |
1967 | exp->X_add_number = i.tm.extension_opcode; | |
1968 | i.tm.extension_opcode = None; | |
1969 | } | |
1970 | ||
47926f60 | 1971 | /* For insns with operands there are more diddles to do to the opcode. */ |
252b5132 RH |
1972 | if (i.operands) |
1973 | { | |
24eab124 | 1974 | /* Default segment register this instruction will use |
252b5132 RH |
1975 | for memory accesses. 0 means unknown. |
1976 | This is only for optimizing out unnecessary segment overrides. */ | |
1977 | const seg_entry *default_seg = 0; | |
1978 | ||
252b5132 RH |
1979 | /* The imul $imm, %reg instruction is converted into |
1980 | imul $imm, %reg, %reg, and the clr %reg instruction | |
1981 | is converted into xor %reg, %reg. */ | |
1982 | if (i.tm.opcode_modifier & regKludge) | |
1983 | { | |
1984 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; | |
47926f60 KH |
1985 | /* Pretend we saw the extra register operand. */ |
1986 | assert (i.op[first_reg_op + 1].regs == 0); | |
1987 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; | |
1988 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
252b5132 RH |
1989 | i.reg_operands = 2; |
1990 | } | |
1991 | ||
1992 | if (i.tm.opcode_modifier & ShortForm) | |
1993 | { | |
47926f60 | 1994 | /* The register or float register operand is in operand 0 or 1. */ |
252b5132 | 1995 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; |
47926f60 | 1996 | /* Register goes in low 3 bits of opcode. */ |
520dc8e8 | 1997 | i.tm.base_opcode |= i.op[op].regs->reg_num; |
a38cf1db | 1998 | if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 RH |
1999 | { |
2000 | /* Warn about some common errors, but press on regardless. | |
2001 | The first case can be generated by gcc (<= 2.8.1). */ | |
2002 | if (i.operands == 2) | |
2003 | { | |
47926f60 | 2004 | /* Reversed arguments on faddp, fsubp, etc. */ |
252b5132 | 2005 | as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, |
520dc8e8 AM |
2006 | i.op[1].regs->reg_name, |
2007 | i.op[0].regs->reg_name); | |
252b5132 RH |
2008 | } |
2009 | else | |
2010 | { | |
47926f60 | 2011 | /* Extraneous `l' suffix on fp insn. */ |
252b5132 | 2012 | as_warn (_("translating to `%s %%%s'"), i.tm.name, |
520dc8e8 | 2013 | i.op[0].regs->reg_name); |
252b5132 RH |
2014 | } |
2015 | } | |
2016 | } | |
2017 | else if (i.tm.opcode_modifier & Modrm) | |
2018 | { | |
2019 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
2020 | must be put into the modrm byte). | |
2021 | Now, we make the modrm & index base bytes based on all the | |
47926f60 | 2022 | info we've collected. */ |
252b5132 RH |
2023 | |
2024 | /* i.reg_operands MUST be the number of real register operands; | |
47926f60 | 2025 | implicit registers do not count. */ |
252b5132 RH |
2026 | if (i.reg_operands == 2) |
2027 | { | |
2028 | unsigned int source, dest; | |
2029 | source = ((i.types[0] | |
3f4438ab AM |
2030 | & (Reg | RegMMX | RegXMM |
2031 | | SReg2 | SReg3 | |
2032 | | Control | Debug | Test)) | |
252b5132 RH |
2033 | ? 0 : 1); |
2034 | dest = source + 1; | |
2035 | ||
252b5132 | 2036 | i.rm.mode = 3; |
3f4438ab AM |
2037 | /* One of the register operands will be encoded in the |
2038 | i.tm.reg field, the other in the combined i.tm.mode | |
2039 | and i.tm.regmem fields. If no form of this | |
2040 | instruction supports a memory destination operand, | |
2041 | then we assume the source operand may sometimes be | |
2042 | a memory operand and so we need to store the | |
2043 | destination in the i.rm.reg field. */ | |
2044 | if ((i.tm.operand_types[dest] & AnyMem) == 0) | |
252b5132 | 2045 | { |
520dc8e8 AM |
2046 | i.rm.reg = i.op[dest].regs->reg_num; |
2047 | i.rm.regmem = i.op[source].regs->reg_num; | |
252b5132 RH |
2048 | } |
2049 | else | |
2050 | { | |
520dc8e8 AM |
2051 | i.rm.reg = i.op[source].regs->reg_num; |
2052 | i.rm.regmem = i.op[dest].regs->reg_num; | |
252b5132 RH |
2053 | } |
2054 | } | |
2055 | else | |
47926f60 | 2056 | { /* If it's not 2 reg operands... */ |
252b5132 RH |
2057 | if (i.mem_operands) |
2058 | { | |
2059 | unsigned int fake_zero_displacement = 0; | |
2060 | unsigned int op = ((i.types[0] & AnyMem) | |
2061 | ? 0 | |
2062 | : (i.types[1] & AnyMem) ? 1 : 2); | |
2063 | ||
2064 | default_seg = &ds; | |
2065 | ||
2066 | if (! i.base_reg) | |
2067 | { | |
2068 | i.rm.mode = 0; | |
2069 | if (! i.disp_operands) | |
2070 | fake_zero_displacement = 1; | |
2071 | if (! i.index_reg) | |
2072 | { | |
47926f60 | 2073 | /* Operand is just <disp> */ |
252b5132 RH |
2074 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) |
2075 | { | |
2076 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2077 | i.types[op] &= ~Disp; | |
2078 | i.types[op] |= Disp16; | |
2079 | } | |
2080 | else | |
2081 | { | |
2082 | i.rm.regmem = NO_BASE_REGISTER; | |
2083 | i.types[op] &= ~Disp; | |
2084 | i.types[op] |= Disp32; | |
2085 | } | |
2086 | } | |
47926f60 | 2087 | else /* ! i.base_reg && i.index_reg */ |
252b5132 RH |
2088 | { |
2089 | i.sib.index = i.index_reg->reg_num; | |
2090 | i.sib.base = NO_BASE_REGISTER; | |
2091 | i.sib.scale = i.log2_scale_factor; | |
2092 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2093 | i.types[op] &= ~Disp; | |
47926f60 | 2094 | i.types[op] |= Disp32; /* Must be 32 bit. */ |
252b5132 RH |
2095 | } |
2096 | } | |
2097 | else if (i.base_reg->reg_type & Reg16) | |
2098 | { | |
2099 | switch (i.base_reg->reg_num) | |
2100 | { | |
47926f60 | 2101 | case 3: /* (%bx) */ |
252b5132 RH |
2102 | if (! i.index_reg) |
2103 | i.rm.regmem = 7; | |
47926f60 | 2104 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ |
252b5132 RH |
2105 | i.rm.regmem = i.index_reg->reg_num - 6; |
2106 | break; | |
47926f60 | 2107 | case 5: /* (%bp) */ |
252b5132 RH |
2108 | default_seg = &ss; |
2109 | if (! i.index_reg) | |
2110 | { | |
2111 | i.rm.regmem = 6; | |
2112 | if ((i.types[op] & Disp) == 0) | |
2113 | { | |
47926f60 | 2114 | /* fake (%bp) into 0(%bp) */ |
252b5132 RH |
2115 | i.types[op] |= Disp8; |
2116 | fake_zero_displacement = 1; | |
2117 | } | |
2118 | } | |
47926f60 | 2119 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ |
252b5132 RH |
2120 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; |
2121 | break; | |
47926f60 | 2122 | default: /* (%si) -> 4 or (%di) -> 5 */ |
252b5132 RH |
2123 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; |
2124 | } | |
2125 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2126 | } | |
47926f60 | 2127 | else /* i.base_reg and 32 bit mode */ |
252b5132 RH |
2128 | { |
2129 | i.rm.regmem = i.base_reg->reg_num; | |
2130 | i.sib.base = i.base_reg->reg_num; | |
2131 | if (i.base_reg->reg_num == EBP_REG_NUM) | |
2132 | { | |
2133 | default_seg = &ss; | |
2134 | if (i.disp_operands == 0) | |
2135 | { | |
2136 | fake_zero_displacement = 1; | |
2137 | i.types[op] |= Disp8; | |
2138 | } | |
2139 | } | |
2140 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
2141 | { | |
2142 | default_seg = &ss; | |
2143 | } | |
2144 | i.sib.scale = i.log2_scale_factor; | |
2145 | if (! i.index_reg) | |
2146 | { | |
2147 | /* <disp>(%esp) becomes two byte modrm | |
2148 | with no index register. We've already | |
2149 | stored the code for esp in i.rm.regmem | |
2150 | ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any | |
2151 | base register besides %esp will not use | |
2152 | the extra modrm byte. */ | |
2153 | i.sib.index = NO_INDEX_REGISTER; | |
2154 | #if ! SCALE1_WHEN_NO_INDEX | |
2155 | /* Another case where we force the second | |
2156 | modrm byte. */ | |
2157 | if (i.log2_scale_factor) | |
2158 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2159 | #endif | |
2160 | } | |
2161 | else | |
2162 | { | |
2163 | i.sib.index = i.index_reg->reg_num; | |
2164 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2165 | } | |
2166 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2167 | } | |
2168 | ||
2169 | if (fake_zero_displacement) | |
2170 | { | |
2171 | /* Fakes a zero displacement assuming that i.types[op] | |
47926f60 | 2172 | holds the correct displacement size. */ |
b4cac588 AM |
2173 | expressionS *exp; |
2174 | ||
520dc8e8 | 2175 | assert (i.op[op].disps == 0); |
252b5132 | 2176 | exp = &disp_expressions[i.disp_operands++]; |
520dc8e8 | 2177 | i.op[op].disps = exp; |
252b5132 RH |
2178 | exp->X_op = O_constant; |
2179 | exp->X_add_number = 0; | |
2180 | exp->X_add_symbol = (symbolS *) 0; | |
2181 | exp->X_op_symbol = (symbolS *) 0; | |
2182 | } | |
2183 | } | |
2184 | ||
2185 | /* Fill in i.rm.reg or i.rm.regmem field with register | |
2186 | operand (if any) based on i.tm.extension_opcode. | |
2187 | Again, we must be careful to make sure that | |
2188 | segment/control/debug/test/MMX registers are coded | |
47926f60 | 2189 | into the i.rm.reg field. */ |
252b5132 RH |
2190 | if (i.reg_operands) |
2191 | { | |
2192 | unsigned int op = | |
2193 | ((i.types[0] | |
3f4438ab AM |
2194 | & (Reg | RegMMX | RegXMM |
2195 | | SReg2 | SReg3 | |
2196 | | Control | Debug | Test)) | |
252b5132 RH |
2197 | ? 0 |
2198 | : ((i.types[1] | |
3f4438ab AM |
2199 | & (Reg | RegMMX | RegXMM |
2200 | | SReg2 | SReg3 | |
2201 | | Control | Debug | Test)) | |
252b5132 RH |
2202 | ? 1 |
2203 | : 2)); | |
2204 | /* If there is an extension opcode to put here, the | |
47926f60 | 2205 | register number must be put into the regmem field. */ |
252b5132 | 2206 | if (i.tm.extension_opcode != None) |
520dc8e8 | 2207 | i.rm.regmem = i.op[op].regs->reg_num; |
252b5132 | 2208 | else |
520dc8e8 | 2209 | i.rm.reg = i.op[op].regs->reg_num; |
252b5132 RH |
2210 | |
2211 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 | |
2212 | we must set it to 3 to indicate this is a register | |
2213 | operand in the regmem field. */ | |
2214 | if (!i.mem_operands) | |
2215 | i.rm.mode = 3; | |
2216 | } | |
2217 | ||
47926f60 | 2218 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
252b5132 RH |
2219 | if (i.tm.extension_opcode != None) |
2220 | i.rm.reg = i.tm.extension_opcode; | |
2221 | } | |
2222 | } | |
2223 | else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) | |
2224 | { | |
47926f60 KH |
2225 | if (i.tm.base_opcode == POP_SEG_SHORT |
2226 | && i.op[0].regs->reg_num == 1) | |
252b5132 RH |
2227 | { |
2228 | as_bad (_("you can't `pop %%cs'")); | |
2229 | return; | |
2230 | } | |
520dc8e8 | 2231 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
252b5132 RH |
2232 | } |
2233 | else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32) | |
2234 | { | |
2235 | default_seg = &ds; | |
2236 | } | |
2237 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
2238 | { | |
2239 | /* For the string instructions that allow a segment override | |
2240 | on one of their operands, the default segment is ds. */ | |
2241 | default_seg = &ds; | |
2242 | } | |
2243 | ||
2244 | /* If a segment was explicitly specified, | |
2245 | and the specified segment is not the default, | |
2246 | use an opcode prefix to select it. | |
2247 | If we never figured out what the default segment is, | |
2248 | then default_seg will be zero at this point, | |
2249 | and the specified segment prefix will always be used. */ | |
2250 | if ((i.seg[0]) && (i.seg[0] != default_seg)) | |
2251 | { | |
2252 | if (! add_prefix (i.seg[0]->seg_prefix)) | |
2253 | return; | |
2254 | } | |
2255 | } | |
a38cf1db | 2256 | else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 | 2257 | { |
24eab124 AM |
2258 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ |
2259 | as_warn (_("translating to `%sp'"), i.tm.name); | |
252b5132 RH |
2260 | } |
2261 | } | |
2262 | ||
47926f60 | 2263 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
520dc8e8 | 2264 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) |
252b5132 RH |
2265 | { |
2266 | i.tm.base_opcode = INT3_OPCODE; | |
2267 | i.imm_operands = 0; | |
2268 | } | |
2269 | ||
2f66722d | 2270 | if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) |
520dc8e8 | 2271 | && i.op[0].disps->X_op == O_constant) |
2f66722d AM |
2272 | { |
2273 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
2274 | the absolute address given by the constant. Since ix86 jumps and | |
2275 | calls are pc relative, we need to generate a reloc. */ | |
520dc8e8 AM |
2276 | i.op[0].disps->X_add_symbol = &abs_symbol; |
2277 | i.op[0].disps->X_op = O_symbol; | |
2f66722d AM |
2278 | } |
2279 | ||
47926f60 | 2280 | /* We are ready to output the insn. */ |
252b5132 RH |
2281 | { |
2282 | register char *p; | |
2283 | ||
47926f60 | 2284 | /* Output jumps. */ |
252b5132 RH |
2285 | if (i.tm.opcode_modifier & Jump) |
2286 | { | |
a217f122 AM |
2287 | int size; |
2288 | int code16; | |
2289 | int prefix; | |
252b5132 | 2290 | |
a217f122 AM |
2291 | code16 = 0; |
2292 | if (flag_16bit_code) | |
2293 | code16 = CODE16; | |
2294 | ||
2295 | prefix = 0; | |
2296 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2297 | { |
a217f122 | 2298 | prefix = 1; |
252b5132 | 2299 | i.prefixes -= 1; |
a217f122 | 2300 | code16 ^= CODE16; |
252b5132 | 2301 | } |
252b5132 | 2302 | |
a217f122 AM |
2303 | size = 4; |
2304 | if (code16) | |
2305 | size = 2; | |
2306 | ||
2307 | if (i.prefixes != 0 && !intel_syntax) | |
252b5132 RH |
2308 | as_warn (_("skipping prefixes on this instruction")); |
2309 | ||
2f66722d AM |
2310 | /* It's always a symbol; End frag & setup for relax. |
2311 | Make sure there is enough room in this frag for the largest | |
2312 | instruction we may generate in md_convert_frag. This is 2 | |
2313 | bytes for the opcode and room for the prefix and largest | |
2314 | displacement. */ | |
2315 | frag_grow (prefix + 2 + size); | |
2316 | insn_size += prefix + 1; | |
2317 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
2318 | p = frag_more (prefix + 1); | |
2319 | if (prefix) | |
2320 | *p++ = DATA_PREFIX_OPCODE; | |
2321 | *p = i.tm.base_opcode; | |
ee7fcc42 AM |
2322 | /* 1 possible extra opcode + displacement go in var part. |
2323 | Pass reloc in fr_var. */ | |
2f66722d AM |
2324 | frag_var (rs_machine_dependent, |
2325 | 1 + size, | |
ee7fcc42 | 2326 | i.disp_reloc[0], |
2f66722d AM |
2327 | ((unsigned char) *p == JUMP_PC_RELATIVE |
2328 | ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16 | |
2329 | : ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16), | |
520dc8e8 AM |
2330 | i.op[0].disps->X_add_symbol, |
2331 | i.op[0].disps->X_add_number, | |
2f66722d | 2332 | p); |
252b5132 RH |
2333 | } |
2334 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) | |
2335 | { | |
a217f122 | 2336 | int size; |
252b5132 | 2337 | |
a217f122 | 2338 | if (i.tm.opcode_modifier & JumpByte) |
252b5132 | 2339 | { |
a217f122 AM |
2340 | /* This is a loop or jecxz type instruction. */ |
2341 | size = 1; | |
252b5132 RH |
2342 | if (i.prefix[ADDR_PREFIX]) |
2343 | { | |
2344 | insn_size += 1; | |
2345 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
2346 | i.prefixes -= 1; | |
2347 | } | |
2348 | } | |
2349 | else | |
2350 | { | |
a217f122 AM |
2351 | int code16; |
2352 | ||
2353 | code16 = 0; | |
2354 | if (flag_16bit_code) | |
2355 | code16 = CODE16; | |
252b5132 RH |
2356 | |
2357 | if (i.prefix[DATA_PREFIX]) | |
2358 | { | |
2359 | insn_size += 1; | |
2360 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
2361 | i.prefixes -= 1; | |
a217f122 | 2362 | code16 ^= CODE16; |
252b5132 | 2363 | } |
252b5132 | 2364 | |
a217f122 | 2365 | size = 4; |
252b5132 RH |
2366 | if (code16) |
2367 | size = 2; | |
2368 | } | |
2369 | ||
a217f122 | 2370 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2371 | as_warn (_("skipping prefixes on this instruction")); |
2372 | ||
2373 | if (fits_in_unsigned_byte (i.tm.base_opcode)) | |
2374 | { | |
2375 | insn_size += 1 + size; | |
2376 | p = frag_more (1 + size); | |
2377 | } | |
2378 | else | |
2379 | { | |
47926f60 | 2380 | /* Opcode can be at most two bytes. */ |
a217f122 | 2381 | insn_size += 2 + size; |
252b5132 RH |
2382 | p = frag_more (2 + size); |
2383 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
2384 | } | |
2385 | *p++ = i.tm.base_opcode & 0xff; | |
2386 | ||
2f66722d | 2387 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
520dc8e8 | 2388 | i.op[0].disps, 1, reloc (size, 1, i.disp_reloc[0])); |
252b5132 RH |
2389 | } |
2390 | else if (i.tm.opcode_modifier & JumpInterSegment) | |
2391 | { | |
2392 | int size; | |
a217f122 AM |
2393 | int prefix; |
2394 | int code16; | |
252b5132 | 2395 | |
a217f122 AM |
2396 | code16 = 0; |
2397 | if (flag_16bit_code) | |
2398 | code16 = CODE16; | |
2399 | ||
2400 | prefix = 0; | |
2401 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2402 | { |
a217f122 | 2403 | prefix = 1; |
252b5132 | 2404 | i.prefixes -= 1; |
a217f122 | 2405 | code16 ^= CODE16; |
252b5132 | 2406 | } |
252b5132 RH |
2407 | |
2408 | size = 4; | |
252b5132 | 2409 | if (code16) |
f6af82bd | 2410 | size = 2; |
252b5132 | 2411 | |
a217f122 | 2412 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2413 | as_warn (_("skipping prefixes on this instruction")); |
2414 | ||
47926f60 KH |
2415 | /* 1 opcode; 2 segment; offset */ |
2416 | insn_size += prefix + 1 + 2 + size; | |
252b5132 RH |
2417 | p = frag_more (prefix + 1 + 2 + size); |
2418 | if (prefix) | |
2419 | *p++ = DATA_PREFIX_OPCODE; | |
2420 | *p++ = i.tm.base_opcode; | |
520dc8e8 | 2421 | if (i.op[1].imms->X_op == O_constant) |
252b5132 | 2422 | { |
847f7ad4 | 2423 | offsetT n = i.op[1].imms->X_add_number; |
252b5132 | 2424 | |
773f551c AM |
2425 | if (size == 2 |
2426 | && !fits_in_unsigned_word (n) | |
2427 | && !fits_in_signed_word (n)) | |
252b5132 RH |
2428 | { |
2429 | as_bad (_("16-bit jump out of range")); | |
2430 | return; | |
2431 | } | |
847f7ad4 | 2432 | md_number_to_chars (p, n, size); |
252b5132 RH |
2433 | } |
2434 | else | |
2435 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
520dc8e8 AM |
2436 | i.op[1].imms, 0, reloc (size, 0, i.disp_reloc[0])); |
2437 | if (i.op[0].imms->X_op != O_constant) | |
252b5132 RH |
2438 | as_bad (_("can't handle non absolute segment in `%s'"), |
2439 | i.tm.name); | |
520dc8e8 | 2440 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); |
252b5132 RH |
2441 | } |
2442 | else | |
2443 | { | |
47926f60 | 2444 | /* Output normal instructions here. */ |
252b5132 RH |
2445 | unsigned char *q; |
2446 | ||
47926f60 | 2447 | /* The prefix bytes. */ |
252b5132 RH |
2448 | for (q = i.prefix; |
2449 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); | |
2450 | q++) | |
2451 | { | |
2452 | if (*q) | |
2453 | { | |
2454 | insn_size += 1; | |
2455 | p = frag_more (1); | |
2456 | md_number_to_chars (p, (valueT) *q, 1); | |
2457 | } | |
2458 | } | |
2459 | ||
47926f60 | 2460 | /* Now the opcode; be careful about word order here! */ |
252b5132 RH |
2461 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
2462 | { | |
2463 | insn_size += 1; | |
2464 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
2465 | } | |
2466 | else if (fits_in_unsigned_word (i.tm.base_opcode)) | |
2467 | { | |
2468 | insn_size += 2; | |
2469 | p = frag_more (2); | |
47926f60 | 2470 | /* Put out high byte first: can't use md_number_to_chars! */ |
252b5132 RH |
2471 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
2472 | *p = i.tm.base_opcode & 0xff; | |
2473 | } | |
2474 | else | |
47926f60 | 2475 | { /* Opcode is either 3 or 4 bytes. */ |
252b5132 RH |
2476 | if (i.tm.base_opcode & 0xff000000) |
2477 | { | |
2478 | insn_size += 4; | |
2479 | p = frag_more (4); | |
2480 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
2481 | } | |
2482 | else | |
2483 | { | |
2484 | insn_size += 3; | |
2485 | p = frag_more (3); | |
2486 | } | |
2487 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
2488 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
2489 | *p = (i.tm.base_opcode) & 0xff; | |
2490 | } | |
2491 | ||
2492 | /* Now the modrm byte and sib byte (if present). */ | |
2493 | if (i.tm.opcode_modifier & Modrm) | |
2494 | { | |
2495 | insn_size += 1; | |
2496 | p = frag_more (1); | |
2497 | md_number_to_chars (p, | |
2498 | (valueT) (i.rm.regmem << 0 | |
2499 | | i.rm.reg << 3 | |
2500 | | i.rm.mode << 6), | |
2501 | 1); | |
2502 | /* If i.rm.regmem == ESP (4) | |
2503 | && i.rm.mode != (Register mode) | |
2504 | && not 16 bit | |
2505 | ==> need second modrm byte. */ | |
2506 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
2507 | && i.rm.mode != 3 | |
2508 | && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) | |
2509 | { | |
2510 | insn_size += 1; | |
2511 | p = frag_more (1); | |
2512 | md_number_to_chars (p, | |
2513 | (valueT) (i.sib.base << 0 | |
2514 | | i.sib.index << 3 | |
2515 | | i.sib.scale << 6), | |
2516 | 1); | |
2517 | } | |
2518 | } | |
2519 | ||
2520 | if (i.disp_operands) | |
2521 | { | |
2522 | register unsigned int n; | |
2523 | ||
2524 | for (n = 0; n < i.operands; n++) | |
2525 | { | |
520dc8e8 | 2526 | if (i.types[n] & Disp) |
252b5132 | 2527 | { |
520dc8e8 | 2528 | if (i.op[n].disps->X_op == O_constant) |
252b5132 | 2529 | { |
847f7ad4 AM |
2530 | int size; |
2531 | offsetT val; | |
b4cac588 | 2532 | |
847f7ad4 | 2533 | size = 4; |
b4cac588 | 2534 | if (i.types[n] & (Disp8 | Disp16)) |
252b5132 | 2535 | { |
b4cac588 | 2536 | size = 2; |
b4cac588 | 2537 | if (i.types[n] & Disp8) |
847f7ad4 | 2538 | size = 1; |
252b5132 | 2539 | } |
847f7ad4 AM |
2540 | val = offset_in_range (i.op[n].disps->X_add_number, |
2541 | size); | |
b4cac588 AM |
2542 | insn_size += size; |
2543 | p = frag_more (size); | |
847f7ad4 | 2544 | md_number_to_chars (p, val, size); |
252b5132 | 2545 | } |
252b5132 | 2546 | else |
520dc8e8 AM |
2547 | { |
2548 | int size = 4; | |
2549 | ||
2550 | if (i.types[n] & Disp16) | |
2551 | size = 2; | |
2552 | ||
2553 | insn_size += size; | |
2554 | p = frag_more (size); | |
2555 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
2556 | i.op[n].disps, 0, | |
2557 | reloc (size, 0, i.disp_reloc[n])); | |
252b5132 RH |
2558 | } |
2559 | } | |
2560 | } | |
ce8a8b2f | 2561 | } |
252b5132 | 2562 | |
47926f60 | 2563 | /* Output immediate. */ |
252b5132 RH |
2564 | if (i.imm_operands) |
2565 | { | |
2566 | register unsigned int n; | |
2567 | ||
2568 | for (n = 0; n < i.operands; n++) | |
2569 | { | |
520dc8e8 | 2570 | if (i.types[n] & Imm) |
252b5132 | 2571 | { |
520dc8e8 | 2572 | if (i.op[n].imms->X_op == O_constant) |
252b5132 | 2573 | { |
847f7ad4 AM |
2574 | int size; |
2575 | offsetT val; | |
b4cac588 | 2576 | |
847f7ad4 | 2577 | size = 4; |
b4cac588 | 2578 | if (i.types[n] & (Imm8 | Imm8S | Imm16)) |
252b5132 | 2579 | { |
b4cac588 | 2580 | size = 2; |
b4cac588 | 2581 | if (i.types[n] & (Imm8 | Imm8S)) |
847f7ad4 | 2582 | size = 1; |
252b5132 | 2583 | } |
847f7ad4 AM |
2584 | val = offset_in_range (i.op[n].imms->X_add_number, |
2585 | size); | |
b4cac588 AM |
2586 | insn_size += size; |
2587 | p = frag_more (size); | |
847f7ad4 | 2588 | md_number_to_chars (p, val, size); |
252b5132 RH |
2589 | } |
2590 | else | |
ce8a8b2f AM |
2591 | { |
2592 | /* Not absolute_section. | |
2593 | Need a 32-bit fixup (don't support 8bit | |
520dc8e8 | 2594 | non-absolute imms). Try to support other |
47926f60 | 2595 | sizes ... */ |
f6af82bd AM |
2596 | #ifdef BFD_ASSEMBLER |
2597 | enum bfd_reloc_code_real reloc_type; | |
2598 | #else | |
2599 | int reloc_type; | |
2600 | #endif | |
520dc8e8 | 2601 | int size = 4; |
252b5132 | 2602 | |
520dc8e8 | 2603 | if (i.types[n] & Imm16) |
252b5132 | 2604 | size = 2; |
520dc8e8 AM |
2605 | else if (i.types[n] & (Imm8 | Imm8S)) |
2606 | size = 1; | |
2607 | ||
252b5132 RH |
2608 | insn_size += size; |
2609 | p = frag_more (size); | |
f6af82bd | 2610 | reloc_type = reloc (size, 0, i.disp_reloc[0]); |
252b5132 | 2611 | #ifdef BFD_ASSEMBLER |
f6af82bd | 2612 | if (reloc_type == BFD_RELOC_32 |
252b5132 | 2613 | && GOT_symbol |
520dc8e8 AM |
2614 | && GOT_symbol == i.op[n].imms->X_add_symbol |
2615 | && (i.op[n].imms->X_op == O_symbol | |
2616 | || (i.op[n].imms->X_op == O_add | |
49309057 | 2617 | && ((symbol_get_value_expression |
520dc8e8 | 2618 | (i.op[n].imms->X_op_symbol)->X_op) |
252b5132 RH |
2619 | == O_subtract)))) |
2620 | { | |
f6af82bd | 2621 | reloc_type = BFD_RELOC_386_GOTPC; |
520dc8e8 | 2622 | i.op[n].imms->X_add_number += 3; |
252b5132 RH |
2623 | } |
2624 | #endif | |
2625 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
520dc8e8 | 2626 | i.op[n].imms, 0, reloc_type); |
252b5132 RH |
2627 | } |
2628 | } | |
2629 | } | |
ce8a8b2f | 2630 | } |
252b5132 RH |
2631 | } |
2632 | ||
e346e481 RH |
2633 | dwarf2_emit_insn (insn_size); |
2634 | ||
252b5132 RH |
2635 | #ifdef DEBUG386 |
2636 | if (flag_debug) | |
2637 | { | |
2638 | pi (line, &i); | |
2639 | } | |
47926f60 | 2640 | #endif /* DEBUG386 */ |
252b5132 RH |
2641 | } |
2642 | } | |
2643 | \f | |
252b5132 RH |
2644 | static int i386_immediate PARAMS ((char *)); |
2645 | ||
2646 | static int | |
2647 | i386_immediate (imm_start) | |
2648 | char *imm_start; | |
2649 | { | |
2650 | char *save_input_line_pointer; | |
2651 | segT exp_seg = 0; | |
47926f60 | 2652 | expressionS *exp; |
252b5132 RH |
2653 | |
2654 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
2655 | { | |
d0b47220 | 2656 | as_bad (_("only 1 or 2 immediate operands are allowed")); |
252b5132 RH |
2657 | return 0; |
2658 | } | |
2659 | ||
2660 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 2661 | i.op[this_operand].imms = exp; |
252b5132 RH |
2662 | |
2663 | if (is_space_char (*imm_start)) | |
2664 | ++imm_start; | |
2665 | ||
2666 | save_input_line_pointer = input_line_pointer; | |
2667 | input_line_pointer = imm_start; | |
2668 | ||
2669 | #ifndef LEX_AT | |
24eab124 | 2670 | { |
47926f60 KH |
2671 | /* We can have operands of the form |
2672 | <symbol>@GOTOFF+<nnn> | |
2673 | Take the easy way out here and copy everything | |
2674 | into a temporary buffer... */ | |
24eab124 AM |
2675 | register char *cp; |
2676 | ||
2677 | cp = strchr (input_line_pointer, '@'); | |
2678 | if (cp != NULL) | |
2679 | { | |
2680 | char *tmpbuf; | |
2681 | int len = 0; | |
2682 | int first; | |
2683 | ||
47926f60 | 2684 | /* GOT relocations are not supported in 16 bit mode. */ |
24eab124 AM |
2685 | if (flag_16bit_code) |
2686 | as_bad (_("GOT relocations not supported in 16 bit mode")); | |
2687 | ||
2688 | if (GOT_symbol == NULL) | |
2689 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
2690 | ||
2691 | if (strncmp (cp + 1, "PLT", 3) == 0) | |
2692 | { | |
2693 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
2694 | len = 3; | |
2695 | } | |
2696 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) | |
2697 | { | |
2698 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; | |
2699 | len = 6; | |
2700 | } | |
2701 | else if (strncmp (cp + 1, "GOT", 3) == 0) | |
2702 | { | |
2703 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; | |
2704 | len = 3; | |
2705 | } | |
2706 | else | |
d0b47220 | 2707 | as_bad (_("bad reloc specifier in expression")); |
24eab124 AM |
2708 | |
2709 | /* Replace the relocation token with ' ', so that errors like | |
2710 | foo@GOTOFF1 will be detected. */ | |
2711 | first = cp - input_line_pointer; | |
47926f60 | 2712 | tmpbuf = (char *) alloca (strlen (input_line_pointer)); |
24eab124 AM |
2713 | memcpy (tmpbuf, input_line_pointer, first); |
2714 | tmpbuf[first] = ' '; | |
2715 | strcpy (tmpbuf + first + 1, cp + 1 + len); | |
2716 | input_line_pointer = tmpbuf; | |
2717 | } | |
2718 | } | |
252b5132 RH |
2719 | #endif |
2720 | ||
2721 | exp_seg = expression (exp); | |
2722 | ||
83183c0c | 2723 | SKIP_WHITESPACE (); |
252b5132 | 2724 | if (*input_line_pointer) |
d0b47220 | 2725 | as_bad (_("ignoring junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
2726 | |
2727 | input_line_pointer = save_input_line_pointer; | |
2728 | ||
2daf4fd8 | 2729 | if (exp->X_op == O_absent || exp->X_op == O_big) |
252b5132 | 2730 | { |
47926f60 | 2731 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 2732 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
24eab124 | 2733 | imm_start); |
252b5132 RH |
2734 | exp->X_op = O_constant; |
2735 | exp->X_add_number = 0; | |
2736 | exp->X_add_symbol = (symbolS *) 0; | |
2737 | exp->X_op_symbol = (symbolS *) 0; | |
252b5132 | 2738 | } |
2daf4fd8 AM |
2739 | |
2740 | if (exp->X_op == O_constant) | |
252b5132 | 2741 | { |
47926f60 KH |
2742 | /* Size it properly later. */ |
2743 | i.types[this_operand] |= Imm32; | |
252b5132 | 2744 | } |
4c63da97 | 2745 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
47926f60 | 2746 | else if (1 |
4c63da97 | 2747 | #ifdef BFD_ASSEMBLER |
47926f60 | 2748 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
4c63da97 | 2749 | #endif |
47926f60 | 2750 | && exp_seg != text_section |
24eab124 AM |
2751 | && exp_seg != data_section |
2752 | && exp_seg != bss_section | |
2753 | && exp_seg != undefined_section | |
252b5132 | 2754 | #ifdef BFD_ASSEMBLER |
24eab124 | 2755 | && !bfd_is_com_section (exp_seg) |
252b5132 | 2756 | #endif |
24eab124 | 2757 | ) |
252b5132 | 2758 | { |
4c63da97 | 2759 | #ifdef BFD_ASSEMBLER |
d0b47220 | 2760 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 2761 | #else |
d0b47220 | 2762 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 2763 | #endif |
252b5132 RH |
2764 | return 0; |
2765 | } | |
2766 | #endif | |
2767 | else | |
2768 | { | |
2769 | /* This is an address. The size of the address will be | |
24eab124 AM |
2770 | determined later, depending on destination register, |
2771 | suffix, or the default for the section. We exclude | |
2772 | Imm8S here so that `push $foo' and other instructions | |
2773 | with an Imm8S form will use Imm16 or Imm32. */ | |
252b5132 RH |
2774 | i.types[this_operand] |= (Imm8 | Imm16 | Imm32); |
2775 | } | |
2776 | ||
2777 | return 1; | |
2778 | } | |
2779 | ||
2780 | static int i386_scale PARAMS ((char *)); | |
2781 | ||
2782 | static int | |
2783 | i386_scale (scale) | |
2784 | char *scale; | |
2785 | { | |
2786 | if (!isdigit (*scale)) | |
2787 | goto bad_scale; | |
2788 | ||
2789 | switch (*scale) | |
2790 | { | |
2791 | case '0': | |
2792 | case '1': | |
2793 | i.log2_scale_factor = 0; | |
2794 | break; | |
2795 | case '2': | |
2796 | i.log2_scale_factor = 1; | |
2797 | break; | |
2798 | case '4': | |
2799 | i.log2_scale_factor = 2; | |
2800 | break; | |
2801 | case '8': | |
2802 | i.log2_scale_factor = 3; | |
2803 | break; | |
2804 | default: | |
2805 | bad_scale: | |
2806 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
24eab124 | 2807 | scale); |
252b5132 RH |
2808 | return 0; |
2809 | } | |
2810 | if (i.log2_scale_factor != 0 && ! i.index_reg) | |
2811 | { | |
2812 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 2813 | 1 << i.log2_scale_factor); |
252b5132 RH |
2814 | #if SCALE1_WHEN_NO_INDEX |
2815 | i.log2_scale_factor = 0; | |
2816 | #endif | |
2817 | } | |
2818 | return 1; | |
2819 | } | |
2820 | ||
2821 | static int i386_displacement PARAMS ((char *, char *)); | |
2822 | ||
2823 | static int | |
2824 | i386_displacement (disp_start, disp_end) | |
2825 | char *disp_start; | |
2826 | char *disp_end; | |
2827 | { | |
2828 | register expressionS *exp; | |
2829 | segT exp_seg = 0; | |
2830 | char *save_input_line_pointer; | |
2831 | int bigdisp = Disp32; | |
2832 | ||
252b5132 RH |
2833 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) |
2834 | bigdisp = Disp16; | |
2835 | i.types[this_operand] |= bigdisp; | |
2836 | ||
2837 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 2838 | i.op[this_operand].disps = exp; |
252b5132 RH |
2839 | i.disp_operands++; |
2840 | save_input_line_pointer = input_line_pointer; | |
2841 | input_line_pointer = disp_start; | |
2842 | END_STRING_AND_SAVE (disp_end); | |
2843 | ||
2844 | #ifndef GCC_ASM_O_HACK | |
2845 | #define GCC_ASM_O_HACK 0 | |
2846 | #endif | |
2847 | #if GCC_ASM_O_HACK | |
2848 | END_STRING_AND_SAVE (disp_end + 1); | |
2849 | if ((i.types[this_operand] & BaseIndex) != 0 | |
24eab124 | 2850 | && displacement_string_end[-1] == '+') |
252b5132 RH |
2851 | { |
2852 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
2853 | constraint within gcc asm statements. |
2854 | For instance: | |
2855 | ||
2856 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
2857 | __asm__ __volatile__ ( \ | |
2858 | "movw %w2,%0\n\t" \ | |
2859 | "movw %w1,2+%0\n\t" \ | |
2860 | "rorl $16,%1\n\t" \ | |
2861 | "movb %b1,4+%0\n\t" \ | |
2862 | "movb %4,5+%0\n\t" \ | |
2863 | "movb $0,6+%0\n\t" \ | |
2864 | "movb %h1,7+%0\n\t" \ | |
2865 | "rorl $16,%1" \ | |
2866 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
2867 | ||
2868 | This works great except that the output assembler ends | |
2869 | up looking a bit weird if it turns out that there is | |
2870 | no offset. You end up producing code that looks like: | |
2871 | ||
2872 | #APP | |
2873 | movw $235,(%eax) | |
2874 | movw %dx,2+(%eax) | |
2875 | rorl $16,%edx | |
2876 | movb %dl,4+(%eax) | |
2877 | movb $137,5+(%eax) | |
2878 | movb $0,6+(%eax) | |
2879 | movb %dh,7+(%eax) | |
2880 | rorl $16,%edx | |
2881 | #NO_APP | |
2882 | ||
47926f60 | 2883 | So here we provide the missing zero. */ |
24eab124 AM |
2884 | |
2885 | *displacement_string_end = '0'; | |
252b5132 RH |
2886 | } |
2887 | #endif | |
2888 | #ifndef LEX_AT | |
24eab124 | 2889 | { |
47926f60 KH |
2890 | /* We can have operands of the form |
2891 | <symbol>@GOTOFF+<nnn> | |
2892 | Take the easy way out here and copy everything | |
2893 | into a temporary buffer... */ | |
24eab124 AM |
2894 | register char *cp; |
2895 | ||
2896 | cp = strchr (input_line_pointer, '@'); | |
2897 | if (cp != NULL) | |
2898 | { | |
2899 | char *tmpbuf; | |
2900 | int len = 0; | |
2901 | int first; | |
2902 | ||
47926f60 | 2903 | /* GOT relocations are not supported in 16 bit mode. */ |
24eab124 AM |
2904 | if (flag_16bit_code) |
2905 | as_bad (_("GOT relocations not supported in 16 bit mode")); | |
2906 | ||
2907 | if (GOT_symbol == NULL) | |
2908 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
2909 | ||
2910 | if (strncmp (cp + 1, "PLT", 3) == 0) | |
2911 | { | |
2912 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
2913 | len = 3; | |
2914 | } | |
2915 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) | |
2916 | { | |
2917 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; | |
2918 | len = 6; | |
2919 | } | |
2920 | else if (strncmp (cp + 1, "GOT", 3) == 0) | |
2921 | { | |
2922 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; | |
2923 | len = 3; | |
2924 | } | |
2925 | else | |
d0b47220 | 2926 | as_bad (_("bad reloc specifier in expression")); |
24eab124 AM |
2927 | |
2928 | /* Replace the relocation token with ' ', so that errors like | |
2929 | foo@GOTOFF1 will be detected. */ | |
2930 | first = cp - input_line_pointer; | |
47926f60 | 2931 | tmpbuf = (char *) alloca (strlen (input_line_pointer)); |
24eab124 AM |
2932 | memcpy (tmpbuf, input_line_pointer, first); |
2933 | tmpbuf[first] = ' '; | |
2934 | strcpy (tmpbuf + first + 1, cp + 1 + len); | |
2935 | input_line_pointer = tmpbuf; | |
2936 | } | |
2937 | } | |
252b5132 RH |
2938 | #endif |
2939 | ||
24eab124 | 2940 | exp_seg = expression (exp); |
252b5132 RH |
2941 | |
2942 | #ifdef BFD_ASSEMBLER | |
24eab124 AM |
2943 | /* We do this to make sure that the section symbol is in |
2944 | the symbol table. We will ultimately change the relocation | |
47926f60 | 2945 | to be relative to the beginning of the section. */ |
24eab124 AM |
2946 | if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF) |
2947 | { | |
2948 | if (S_IS_LOCAL(exp->X_add_symbol) | |
2949 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) | |
2950 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
2951 | assert (exp->X_op == O_symbol); | |
2952 | exp->X_op = O_subtract; | |
2953 | exp->X_op_symbol = GOT_symbol; | |
2954 | i.disp_reloc[this_operand] = BFD_RELOC_32; | |
2955 | } | |
252b5132 RH |
2956 | #endif |
2957 | ||
24eab124 AM |
2958 | SKIP_WHITESPACE (); |
2959 | if (*input_line_pointer) | |
d0b47220 | 2960 | as_bad (_("ignoring junk `%s' after expression"), |
24eab124 | 2961 | input_line_pointer); |
252b5132 | 2962 | #if GCC_ASM_O_HACK |
24eab124 | 2963 | RESTORE_END_STRING (disp_end + 1); |
252b5132 | 2964 | #endif |
24eab124 AM |
2965 | RESTORE_END_STRING (disp_end); |
2966 | input_line_pointer = save_input_line_pointer; | |
2967 | ||
2daf4fd8 AM |
2968 | if (exp->X_op == O_absent || exp->X_op == O_big) |
2969 | { | |
47926f60 | 2970 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 2971 | as_bad (_("missing or invalid displacement expression `%s' taken as 0"), |
2daf4fd8 AM |
2972 | disp_start); |
2973 | exp->X_op = O_constant; | |
2974 | exp->X_add_number = 0; | |
2975 | exp->X_add_symbol = (symbolS *) 0; | |
2976 | exp->X_op_symbol = (symbolS *) 0; | |
2977 | } | |
2978 | ||
4c63da97 | 2979 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
45288df1 | 2980 | if (exp->X_op != O_constant |
4c63da97 | 2981 | #ifdef BFD_ASSEMBLER |
45288df1 | 2982 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
4c63da97 | 2983 | #endif |
45288df1 AM |
2984 | && exp_seg != text_section |
2985 | && exp_seg != data_section | |
2986 | && exp_seg != bss_section | |
2987 | && exp_seg != undefined_section) | |
24eab124 | 2988 | { |
4c63da97 | 2989 | #ifdef BFD_ASSEMBLER |
d0b47220 | 2990 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 2991 | #else |
d0b47220 | 2992 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 2993 | #endif |
24eab124 AM |
2994 | return 0; |
2995 | } | |
252b5132 RH |
2996 | #endif |
2997 | return 1; | |
2998 | } | |
2999 | ||
eecb386c | 3000 | static int i386_index_check PARAMS((const char *)); |
252b5132 | 3001 | |
eecb386c | 3002 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
3003 | Return 1 on success, 0 on a failure. */ |
3004 | ||
252b5132 | 3005 | static int |
eecb386c AM |
3006 | i386_index_check (operand_string) |
3007 | const char *operand_string; | |
252b5132 | 3008 | { |
24eab124 | 3009 | #if INFER_ADDR_PREFIX |
eecb386c AM |
3010 | int fudged = 0; |
3011 | ||
24eab124 AM |
3012 | tryprefix: |
3013 | #endif | |
d0b47220 | 3014 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) |
47926f60 | 3015 | /* 16 bit mode checks. */ |
d0b47220 AM |
3016 | ? ((i.base_reg |
3017 | && ((i.base_reg->reg_type & (Reg16|BaseIndex)) | |
3018 | != (Reg16|BaseIndex))) | |
3019 | || (i.index_reg | |
3020 | && (((i.index_reg->reg_type & (Reg16|BaseIndex)) | |
3021 | != (Reg16|BaseIndex)) | |
3022 | || ! (i.base_reg | |
3023 | && i.base_reg->reg_num < 6 | |
3024 | && i.index_reg->reg_num >= 6 | |
3025 | && i.log2_scale_factor == 0)))) | |
47926f60 | 3026 | /* 32 bit mode checks. */ |
d0b47220 AM |
3027 | : ((i.base_reg |
3028 | && (i.base_reg->reg_type & Reg32) == 0) | |
3029 | || (i.index_reg | |
3030 | && ((i.index_reg->reg_type & (Reg32|BaseIndex)) | |
3031 | != (Reg32|BaseIndex))))) | |
24eab124 AM |
3032 | { |
3033 | #if INFER_ADDR_PREFIX | |
eecb386c | 3034 | if (i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0') |
24eab124 AM |
3035 | { |
3036 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
3037 | i.prefixes += 1; | |
b23bac36 AM |
3038 | /* Change the size of any displacement too. At most one of |
3039 | Disp16 or Disp32 is set. | |
3040 | FIXME. There doesn't seem to be any real need for separate | |
3041 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 3042 | Removing them would probably clean up the code quite a lot. */ |
b23bac36 AM |
3043 | if (i.types[this_operand] & (Disp16|Disp32)) |
3044 | i.types[this_operand] ^= (Disp16|Disp32); | |
eecb386c | 3045 | fudged = 1; |
24eab124 AM |
3046 | goto tryprefix; |
3047 | } | |
eecb386c AM |
3048 | if (fudged) |
3049 | as_bad (_("`%s' is not a valid base/index expression"), | |
3050 | operand_string); | |
3051 | else | |
c388dee8 | 3052 | #endif |
eecb386c AM |
3053 | as_bad (_("`%s' is not a valid %s bit base/index expression"), |
3054 | operand_string, | |
3055 | flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) ? "16" : "32"); | |
3056 | return 0; | |
24eab124 AM |
3057 | } |
3058 | return 1; | |
3059 | } | |
252b5132 | 3060 | |
252b5132 | 3061 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero |
47926f60 | 3062 | on error. */ |
252b5132 | 3063 | |
252b5132 RH |
3064 | static int |
3065 | i386_operand (operand_string) | |
3066 | char *operand_string; | |
3067 | { | |
af6bdddf AM |
3068 | const reg_entry *r; |
3069 | char *end_op; | |
24eab124 | 3070 | char *op_string = operand_string; |
252b5132 | 3071 | |
24eab124 | 3072 | if (is_space_char (*op_string)) |
252b5132 RH |
3073 | ++op_string; |
3074 | ||
24eab124 | 3075 | /* We check for an absolute prefix (differentiating, |
47926f60 | 3076 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
3077 | if (*op_string == ABSOLUTE_PREFIX) |
3078 | { | |
3079 | ++op_string; | |
3080 | if (is_space_char (*op_string)) | |
3081 | ++op_string; | |
3082 | i.types[this_operand] |= JumpAbsolute; | |
3083 | } | |
252b5132 | 3084 | |
47926f60 | 3085 | /* Check if operand is a register. */ |
af6bdddf AM |
3086 | if ((*op_string == REGISTER_PREFIX || allow_naked_reg) |
3087 | && (r = parse_register (op_string, &end_op)) != NULL) | |
24eab124 | 3088 | { |
24eab124 AM |
3089 | /* Check for a segment override by searching for ':' after a |
3090 | segment register. */ | |
3091 | op_string = end_op; | |
3092 | if (is_space_char (*op_string)) | |
3093 | ++op_string; | |
3094 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
3095 | { | |
3096 | switch (r->reg_num) | |
3097 | { | |
3098 | case 0: | |
3099 | i.seg[i.mem_operands] = &es; | |
3100 | break; | |
3101 | case 1: | |
3102 | i.seg[i.mem_operands] = &cs; | |
3103 | break; | |
3104 | case 2: | |
3105 | i.seg[i.mem_operands] = &ss; | |
3106 | break; | |
3107 | case 3: | |
3108 | i.seg[i.mem_operands] = &ds; | |
3109 | break; | |
3110 | case 4: | |
3111 | i.seg[i.mem_operands] = &fs; | |
3112 | break; | |
3113 | case 5: | |
3114 | i.seg[i.mem_operands] = &gs; | |
3115 | break; | |
3116 | } | |
252b5132 | 3117 | |
24eab124 | 3118 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
3119 | ++op_string; |
3120 | if (is_space_char (*op_string)) | |
24eab124 | 3121 | ++op_string; |
252b5132 | 3122 | |
24eab124 AM |
3123 | if (!is_digit_char (*op_string) |
3124 | && !is_identifier_char (*op_string) | |
3125 | && *op_string != '(' | |
3126 | && *op_string != ABSOLUTE_PREFIX) | |
3127 | { | |
3128 | as_bad (_("bad memory operand `%s'"), op_string); | |
3129 | return 0; | |
3130 | } | |
47926f60 | 3131 | /* Handle case of %es:*foo. */ |
24eab124 AM |
3132 | if (*op_string == ABSOLUTE_PREFIX) |
3133 | { | |
3134 | ++op_string; | |
3135 | if (is_space_char (*op_string)) | |
3136 | ++op_string; | |
3137 | i.types[this_operand] |= JumpAbsolute; | |
3138 | } | |
3139 | goto do_memory_reference; | |
3140 | } | |
3141 | if (*op_string) | |
3142 | { | |
d0b47220 | 3143 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
3144 | return 0; |
3145 | } | |
3146 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
520dc8e8 | 3147 | i.op[this_operand].regs = r; |
24eab124 AM |
3148 | i.reg_operands++; |
3149 | } | |
af6bdddf AM |
3150 | else if (*op_string == REGISTER_PREFIX) |
3151 | { | |
3152 | as_bad (_("bad register name `%s'"), op_string); | |
3153 | return 0; | |
3154 | } | |
24eab124 | 3155 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 3156 | { |
24eab124 AM |
3157 | ++op_string; |
3158 | if (i.types[this_operand] & JumpAbsolute) | |
3159 | { | |
d0b47220 | 3160 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
3161 | return 0; |
3162 | } | |
3163 | if (!i386_immediate (op_string)) | |
3164 | return 0; | |
3165 | } | |
3166 | else if (is_digit_char (*op_string) | |
3167 | || is_identifier_char (*op_string) | |
3168 | || *op_string == '(' ) | |
3169 | { | |
47926f60 | 3170 | /* This is a memory reference of some sort. */ |
af6bdddf | 3171 | char *base_string; |
252b5132 | 3172 | |
47926f60 | 3173 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
3174 | char *displacement_string_start; |
3175 | char *displacement_string_end; | |
252b5132 | 3176 | |
24eab124 | 3177 | do_memory_reference: |
24eab124 AM |
3178 | if ((i.mem_operands == 1 |
3179 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
3180 | || i.mem_operands == 2) | |
3181 | { | |
3182 | as_bad (_("too many memory references for `%s'"), | |
3183 | current_templates->start->name); | |
3184 | return 0; | |
3185 | } | |
252b5132 | 3186 | |
24eab124 AM |
3187 | /* Check for base index form. We detect the base index form by |
3188 | looking for an ')' at the end of the operand, searching | |
3189 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
3190 | after the '('. */ | |
af6bdddf | 3191 | base_string = op_string + strlen (op_string); |
c3332e24 | 3192 | |
af6bdddf AM |
3193 | --base_string; |
3194 | if (is_space_char (*base_string)) | |
3195 | --base_string; | |
252b5132 | 3196 | |
47926f60 | 3197 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
3198 | displacement_string_start = op_string; |
3199 | displacement_string_end = base_string + 1; | |
252b5132 | 3200 | |
24eab124 AM |
3201 | if (*base_string == ')') |
3202 | { | |
af6bdddf | 3203 | char *temp_string; |
24eab124 AM |
3204 | unsigned int parens_balanced = 1; |
3205 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 3206 | equal, so this loop will not be infinite. */ |
24eab124 AM |
3207 | do |
3208 | { | |
3209 | base_string--; | |
3210 | if (*base_string == ')') | |
3211 | parens_balanced++; | |
3212 | if (*base_string == '(') | |
3213 | parens_balanced--; | |
3214 | } | |
3215 | while (parens_balanced); | |
c3332e24 | 3216 | |
af6bdddf | 3217 | temp_string = base_string; |
c3332e24 | 3218 | |
24eab124 | 3219 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
3220 | ++base_string; |
3221 | if (is_space_char (*base_string)) | |
24eab124 | 3222 | ++base_string; |
252b5132 | 3223 | |
af6bdddf AM |
3224 | if (*base_string == ',' |
3225 | || ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3226 | && (i.base_reg = parse_register (base_string, &end_op)) != NULL)) | |
252b5132 | 3227 | { |
af6bdddf | 3228 | displacement_string_end = temp_string; |
252b5132 | 3229 | |
af6bdddf | 3230 | i.types[this_operand] |= BaseIndex; |
252b5132 | 3231 | |
af6bdddf | 3232 | if (i.base_reg) |
24eab124 | 3233 | { |
24eab124 AM |
3234 | base_string = end_op; |
3235 | if (is_space_char (*base_string)) | |
3236 | ++base_string; | |
af6bdddf AM |
3237 | } |
3238 | ||
3239 | /* There may be an index reg or scale factor here. */ | |
3240 | if (*base_string == ',') | |
3241 | { | |
3242 | ++base_string; | |
3243 | if (is_space_char (*base_string)) | |
3244 | ++base_string; | |
3245 | ||
3246 | if ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3247 | && (i.index_reg = parse_register (base_string, &end_op)) != NULL) | |
24eab124 | 3248 | { |
af6bdddf | 3249 | base_string = end_op; |
24eab124 AM |
3250 | if (is_space_char (*base_string)) |
3251 | ++base_string; | |
af6bdddf AM |
3252 | if (*base_string == ',') |
3253 | { | |
3254 | ++base_string; | |
3255 | if (is_space_char (*base_string)) | |
3256 | ++base_string; | |
3257 | } | |
3258 | else if (*base_string != ')' ) | |
3259 | { | |
3260 | as_bad (_("expecting `,' or `)' after index register in `%s'"), | |
3261 | operand_string); | |
3262 | return 0; | |
3263 | } | |
24eab124 | 3264 | } |
af6bdddf | 3265 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 3266 | { |
af6bdddf | 3267 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
3268 | return 0; |
3269 | } | |
252b5132 | 3270 | |
47926f60 | 3271 | /* Check for scale factor. */ |
af6bdddf AM |
3272 | if (isdigit ((unsigned char) *base_string)) |
3273 | { | |
3274 | if (!i386_scale (base_string)) | |
3275 | return 0; | |
24eab124 | 3276 | |
af6bdddf AM |
3277 | ++base_string; |
3278 | if (is_space_char (*base_string)) | |
3279 | ++base_string; | |
3280 | if (*base_string != ')') | |
3281 | { | |
3282 | as_bad (_("expecting `)' after scale factor in `%s'"), | |
3283 | operand_string); | |
3284 | return 0; | |
3285 | } | |
3286 | } | |
3287 | else if (!i.index_reg) | |
24eab124 | 3288 | { |
af6bdddf AM |
3289 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
3290 | *base_string); | |
24eab124 AM |
3291 | return 0; |
3292 | } | |
3293 | } | |
af6bdddf | 3294 | else if (*base_string != ')') |
24eab124 | 3295 | { |
af6bdddf AM |
3296 | as_bad (_("expecting `,' or `)' after base register in `%s'"), |
3297 | operand_string); | |
24eab124 AM |
3298 | return 0; |
3299 | } | |
c3332e24 | 3300 | } |
af6bdddf | 3301 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 3302 | { |
af6bdddf | 3303 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 3304 | return 0; |
c3332e24 | 3305 | } |
24eab124 AM |
3306 | } |
3307 | ||
3308 | /* If there's an expression beginning the operand, parse it, | |
3309 | assuming displacement_string_start and | |
3310 | displacement_string_end are meaningful. */ | |
3311 | if (displacement_string_start != displacement_string_end) | |
3312 | { | |
3313 | if (!i386_displacement (displacement_string_start, | |
3314 | displacement_string_end)) | |
3315 | return 0; | |
3316 | } | |
3317 | ||
3318 | /* Special case for (%dx) while doing input/output op. */ | |
3319 | if (i.base_reg | |
3320 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) | |
3321 | && i.index_reg == 0 | |
3322 | && i.log2_scale_factor == 0 | |
3323 | && i.seg[i.mem_operands] == 0 | |
3324 | && (i.types[this_operand] & Disp) == 0) | |
3325 | { | |
3326 | i.types[this_operand] = InOutPortReg; | |
3327 | return 1; | |
3328 | } | |
3329 | ||
eecb386c AM |
3330 | if (i386_index_check (operand_string) == 0) |
3331 | return 0; | |
24eab124 AM |
3332 | i.mem_operands++; |
3333 | } | |
3334 | else | |
ce8a8b2f AM |
3335 | { |
3336 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
3337 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
3338 | output_invalid (*op_string), | |
3339 | this_operand + 1, | |
3340 | op_string); | |
3341 | return 0; | |
3342 | } | |
47926f60 | 3343 | return 1; /* Normal return. */ |
252b5132 RH |
3344 | } |
3345 | \f | |
ee7fcc42 AM |
3346 | /* md_estimate_size_before_relax() |
3347 | ||
3348 | Called just before relax() for rs_machine_dependent frags. The x86 | |
3349 | assembler uses these frags to handle variable size jump | |
3350 | instructions. | |
3351 | ||
3352 | Any symbol that is now undefined will not become defined. | |
3353 | Return the correct fr_subtype in the frag. | |
3354 | Return the initial "guess for variable size of frag" to caller. | |
3355 | The guess is actually the growth beyond the fixed part. Whatever | |
3356 | we do to grow the fixed or variable part contributes to our | |
3357 | returned value. */ | |
3358 | ||
252b5132 RH |
3359 | int |
3360 | md_estimate_size_before_relax (fragP, segment) | |
3361 | register fragS *fragP; | |
3362 | register segT segment; | |
3363 | { | |
252b5132 | 3364 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
3365 | check for un-relaxable symbols. On an ELF system, we can't relax |
3366 | an externally visible symbol, because it may be overridden by a | |
3367 | shared library. */ | |
3368 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 3369 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b98ef147 AM |
3370 | || S_IS_EXTERNAL (fragP->fr_symbol) |
3371 | || S_IS_WEAK (fragP->fr_symbol) | |
3372 | #endif | |
3373 | ) | |
252b5132 | 3374 | { |
b98ef147 AM |
3375 | /* Symbol is undefined in this segment, or we need to keep a |
3376 | reloc so that weak symbols can be overridden. */ | |
3377 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f6af82bd AM |
3378 | #ifdef BFD_ASSEMBLER |
3379 | enum bfd_reloc_code_real reloc_type; | |
3380 | #else | |
3381 | int reloc_type; | |
3382 | #endif | |
ee7fcc42 AM |
3383 | unsigned char *opcode; |
3384 | int old_fr_fix; | |
f6af82bd | 3385 | |
ee7fcc42 AM |
3386 | if (fragP->fr_var != NO_RELOC) |
3387 | reloc_type = fragP->fr_var; | |
b98ef147 | 3388 | else if (size == 2) |
f6af82bd AM |
3389 | reloc_type = BFD_RELOC_16_PCREL; |
3390 | else | |
3391 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 3392 | |
ee7fcc42 AM |
3393 | old_fr_fix = fragP->fr_fix; |
3394 | opcode = (unsigned char *) fragP->fr_opcode; | |
3395 | ||
252b5132 RH |
3396 | switch (opcode[0]) |
3397 | { | |
47926f60 KH |
3398 | case JUMP_PC_RELATIVE: |
3399 | /* Make jmp (0xeb) a dword displacement jump. */ | |
47926f60 | 3400 | opcode[0] = 0xe9; |
252b5132 RH |
3401 | fragP->fr_fix += size; |
3402 | fix_new (fragP, old_fr_fix, size, | |
3403 | fragP->fr_symbol, | |
3404 | fragP->fr_offset, 1, | |
f6af82bd | 3405 | reloc_type); |
252b5132 RH |
3406 | break; |
3407 | ||
3408 | default: | |
24eab124 | 3409 | /* This changes the byte-displacement jump 0x7N |
f6af82bd | 3410 | to the dword-displacement jump 0x0f,0x8N. */ |
252b5132 | 3411 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 3412 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
3413 | /* We've added an opcode byte. */ |
3414 | fragP->fr_fix += 1 + size; | |
252b5132 RH |
3415 | fix_new (fragP, old_fr_fix + 1, size, |
3416 | fragP->fr_symbol, | |
3417 | fragP->fr_offset, 1, | |
f6af82bd | 3418 | reloc_type); |
252b5132 RH |
3419 | break; |
3420 | } | |
3421 | frag_wane (fragP); | |
ee7fcc42 | 3422 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 3423 | } |
47926f60 KH |
3424 | /* Guess a short jump. */ |
3425 | return 1; | |
ee7fcc42 AM |
3426 | } |
3427 | ||
47926f60 KH |
3428 | /* Called after relax() is finished. |
3429 | ||
3430 | In: Address of frag. | |
3431 | fr_type == rs_machine_dependent. | |
3432 | fr_subtype is what the address relaxed to. | |
3433 | ||
3434 | Out: Any fixSs and constants are set up. | |
3435 | Caller will turn frag into a ".space 0". */ | |
3436 | ||
252b5132 RH |
3437 | #ifndef BFD_ASSEMBLER |
3438 | void | |
3439 | md_convert_frag (headers, sec, fragP) | |
a04b544b ILT |
3440 | object_headers *headers ATTRIBUTE_UNUSED; |
3441 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
3442 | register fragS *fragP; |
3443 | #else | |
3444 | void | |
3445 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
3446 | bfd *abfd ATTRIBUTE_UNUSED; |
3447 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
3448 | register fragS *fragP; |
3449 | #endif | |
3450 | { | |
3451 | register unsigned char *opcode; | |
3452 | unsigned char *where_to_put_displacement = NULL; | |
847f7ad4 AM |
3453 | offsetT target_address; |
3454 | offsetT opcode_address; | |
252b5132 | 3455 | unsigned int extension = 0; |
847f7ad4 | 3456 | offsetT displacement_from_opcode_start; |
252b5132 RH |
3457 | |
3458 | opcode = (unsigned char *) fragP->fr_opcode; | |
3459 | ||
47926f60 | 3460 | /* Address we want to reach in file space. */ |
252b5132 | 3461 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
47926f60 KH |
3462 | #ifdef BFD_ASSEMBLER |
3463 | /* Not needed otherwise? */ | |
49309057 | 3464 | target_address += symbol_get_frag (fragP->fr_symbol)->fr_address; |
252b5132 RH |
3465 | #endif |
3466 | ||
47926f60 | 3467 | /* Address opcode resides at in file space. */ |
252b5132 RH |
3468 | opcode_address = fragP->fr_address + fragP->fr_fix; |
3469 | ||
47926f60 | 3470 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
3471 | displacement_from_opcode_start = target_address - opcode_address; |
3472 | ||
3473 | switch (fragP->fr_subtype) | |
3474 | { | |
3475 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL): | |
3476 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL16): | |
3477 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL): | |
3478 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL16): | |
47926f60 KH |
3479 | /* Don't have to change opcode. */ |
3480 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 RH |
3481 | where_to_put_displacement = &opcode[1]; |
3482 | break; | |
3483 | ||
3484 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): | |
47926f60 | 3485 | extension = 5; /* 2 opcode + 4 displacement */ |
252b5132 RH |
3486 | opcode[1] = opcode[0] + 0x10; |
3487 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
3488 | where_to_put_displacement = &opcode[2]; | |
3489 | break; | |
3490 | ||
3491 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
47926f60 | 3492 | extension = 4; /* 1 opcode + 4 displacement */ |
252b5132 RH |
3493 | opcode[0] = 0xe9; |
3494 | where_to_put_displacement = &opcode[1]; | |
3495 | break; | |
3496 | ||
3497 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): | |
47926f60 | 3498 | extension = 3; /* 2 opcode + 2 displacement */ |
252b5132 RH |
3499 | opcode[1] = opcode[0] + 0x10; |
3500 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
3501 | where_to_put_displacement = &opcode[2]; | |
3502 | break; | |
3503 | ||
3504 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): | |
47926f60 | 3505 | extension = 2; /* 1 opcode + 2 displacement */ |
252b5132 RH |
3506 | opcode[0] = 0xe9; |
3507 | where_to_put_displacement = &opcode[1]; | |
3508 | break; | |
3509 | ||
3510 | default: | |
3511 | BAD_CASE (fragP->fr_subtype); | |
3512 | break; | |
3513 | } | |
47926f60 | 3514 | /* Now put displacement after opcode. */ |
252b5132 RH |
3515 | md_number_to_chars ((char *) where_to_put_displacement, |
3516 | (valueT) (displacement_from_opcode_start - extension), | |
3517 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
3518 | fragP->fr_fix += extension; | |
3519 | } | |
3520 | \f | |
47926f60 KH |
3521 | /* Size of byte displacement jmp. */ |
3522 | int md_short_jump_size = 2; | |
3523 | ||
3524 | /* Size of dword displacement jmp. */ | |
3525 | int md_long_jump_size = 5; | |
252b5132 | 3526 | |
47926f60 KH |
3527 | /* Size of relocation record. */ |
3528 | const int md_reloc_size = 8; | |
252b5132 RH |
3529 | |
3530 | void | |
3531 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
3532 | char *ptr; | |
3533 | addressT from_addr, to_addr; | |
ab9da554 ILT |
3534 | fragS *frag ATTRIBUTE_UNUSED; |
3535 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 3536 | { |
847f7ad4 | 3537 | offsetT offset; |
252b5132 RH |
3538 | |
3539 | offset = to_addr - (from_addr + 2); | |
47926f60 KH |
3540 | /* Opcode for byte-disp jump. */ |
3541 | md_number_to_chars (ptr, (valueT) 0xeb, 1); | |
252b5132 RH |
3542 | md_number_to_chars (ptr + 1, (valueT) offset, 1); |
3543 | } | |
3544 | ||
3545 | void | |
3546 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
3547 | char *ptr; | |
3548 | addressT from_addr, to_addr; | |
a38cf1db AM |
3549 | fragS *frag ATTRIBUTE_UNUSED; |
3550 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 3551 | { |
847f7ad4 | 3552 | offsetT offset; |
252b5132 | 3553 | |
a38cf1db AM |
3554 | offset = to_addr - (from_addr + 5); |
3555 | md_number_to_chars (ptr, (valueT) 0xe9, 1); | |
3556 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
252b5132 RH |
3557 | } |
3558 | \f | |
3559 | /* Apply a fixup (fixS) to segment data, once it has been determined | |
3560 | by our caller that we have all the info we need to fix it up. | |
3561 | ||
3562 | On the 386, immediates, displacements, and data pointers are all in | |
3563 | the same (little-endian) format, so we don't need to care about which | |
3564 | we are handling. */ | |
3565 | ||
3566 | int | |
3567 | md_apply_fix3 (fixP, valp, seg) | |
47926f60 KH |
3568 | /* The fix we're to put in. */ |
3569 | fixS *fixP; | |
3570 | ||
3571 | /* Pointer to the value of the bits. */ | |
3572 | valueT *valp; | |
3573 | ||
3574 | /* Segment fix is from. */ | |
3575 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 RH |
3576 | { |
3577 | register char *p = fixP->fx_where + fixP->fx_frag->fr_literal; | |
3578 | valueT value = *valp; | |
3579 | ||
e1b283bb | 3580 | #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) |
93382f6d AM |
3581 | if (fixP->fx_pcrel) |
3582 | { | |
3583 | switch (fixP->fx_r_type) | |
3584 | { | |
5865bb77 ILT |
3585 | default: |
3586 | break; | |
3587 | ||
93382f6d AM |
3588 | case BFD_RELOC_32: |
3589 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
3590 | break; | |
3591 | case BFD_RELOC_16: | |
3592 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
3593 | break; | |
3594 | case BFD_RELOC_8: | |
3595 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
3596 | break; | |
3597 | } | |
3598 | } | |
252b5132 | 3599 | |
0723899b ILT |
3600 | /* This is a hack. There should be a better way to handle this. |
3601 | This covers for the fact that bfd_install_relocation will | |
3602 | subtract the current location (for partial_inplace, PC relative | |
3603 | relocations); see more below. */ | |
93382f6d AM |
3604 | if ((fixP->fx_r_type == BFD_RELOC_32_PCREL |
3605 | || fixP->fx_r_type == BFD_RELOC_16_PCREL | |
3606 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
3607 | && fixP->fx_addsy) | |
252b5132 RH |
3608 | { |
3609 | #ifndef OBJ_AOUT | |
3610 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
3611 | #ifdef TE_PE | |
3612 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3613 | #endif | |
3614 | ) | |
3615 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
3616 | #endif | |
3617 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2f66722d | 3618 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
252b5132 | 3619 | { |
2f66722d AM |
3620 | segT fseg = S_GET_SEGMENT (fixP->fx_addsy); |
3621 | ||
3622 | if ((fseg == seg | |
3623 | || (symbol_section_p (fixP->fx_addsy) | |
3624 | && fseg != absolute_section)) | |
3625 | && ! S_IS_EXTERNAL (fixP->fx_addsy) | |
3626 | && ! S_IS_WEAK (fixP->fx_addsy) | |
3627 | && S_IS_DEFINED (fixP->fx_addsy) | |
3628 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
3629 | { | |
3630 | /* Yes, we add the values in twice. This is because | |
3631 | bfd_perform_relocation subtracts them out again. I think | |
3632 | bfd_perform_relocation is broken, but I don't dare change | |
3633 | it. FIXME. */ | |
3634 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
3635 | } | |
252b5132 RH |
3636 | } |
3637 | #endif | |
3638 | #if defined (OBJ_COFF) && defined (TE_PE) | |
3639 | /* For some reason, the PE format does not store a section | |
24eab124 | 3640 | address offset for a PC relative symbol. */ |
252b5132 RH |
3641 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) |
3642 | value += md_pcrel_from (fixP); | |
3643 | #endif | |
3644 | } | |
3645 | ||
3646 | /* Fix a few things - the dynamic linker expects certain values here, | |
47926f60 | 3647 | and we must not dissappoint it. */ |
252b5132 RH |
3648 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3649 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
3650 | && fixP->fx_addsy) | |
47926f60 KH |
3651 | switch (fixP->fx_r_type) |
3652 | { | |
3653 | case BFD_RELOC_386_PLT32: | |
3654 | /* Make the jump instruction point to the address of the operand. At | |
3655 | runtime we merely add the offset to the actual PLT entry. */ | |
3656 | value = -4; | |
3657 | break; | |
3658 | case BFD_RELOC_386_GOTPC: | |
3659 | ||
3660 | /* This is tough to explain. We end up with this one if we have | |
252b5132 RH |
3661 | * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal |
3662 | * here is to obtain the absolute address of the GOT, and it is strongly | |
3663 | * preferable from a performance point of view to avoid using a runtime | |
c3332e24 | 3664 | * relocation for this. The actual sequence of instructions often look |
252b5132 | 3665 | * something like: |
c3332e24 | 3666 | * |
24eab124 | 3667 | * call .L66 |
252b5132 | 3668 | * .L66: |
24eab124 AM |
3669 | * popl %ebx |
3670 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
c3332e24 | 3671 | * |
24eab124 | 3672 | * The call and pop essentially return the absolute address of |
252b5132 RH |
3673 | * the label .L66 and store it in %ebx. The linker itself will |
3674 | * ultimately change the first operand of the addl so that %ebx points to | |
3675 | * the GOT, but to keep things simple, the .o file must have this operand | |
3676 | * set so that it generates not the absolute address of .L66, but the | |
3677 | * absolute address of itself. This allows the linker itself simply | |
3678 | * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be | |
3679 | * added in, and the addend of the relocation is stored in the operand | |
3680 | * field for the instruction itself. | |
c3332e24 | 3681 | * |
24eab124 | 3682 | * Our job here is to fix the operand so that it would add the correct |
252b5132 RH |
3683 | * offset so that %ebx would point to itself. The thing that is tricky is |
3684 | * that .-.L66 will point to the beginning of the instruction, so we need | |
3685 | * to further modify the operand so that it will point to itself. | |
3686 | * There are other cases where you have something like: | |
c3332e24 | 3687 | * |
24eab124 | 3688 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] |
c3332e24 | 3689 | * |
252b5132 | 3690 | * and here no correction would be required. Internally in the assembler |
c3332e24 | 3691 | * we treat operands of this form as not being pcrel since the '.' is |
252b5132 RH |
3692 | * explicitly mentioned, and I wonder whether it would simplify matters |
3693 | * to do it this way. Who knows. In earlier versions of the PIC patches, | |
3694 | * the pcrel_adjust field was used to store the correction, but since the | |
47926f60 KH |
3695 | * expression is not pcrel, I felt it would be confusing to do it this |
3696 | * way. */ | |
3697 | ||
3698 | value -= 1; | |
3699 | break; | |
3700 | case BFD_RELOC_386_GOT32: | |
3701 | value = 0; /* Fully resolved at runtime. No addend. */ | |
3702 | break; | |
3703 | case BFD_RELOC_386_GOTOFF: | |
3704 | break; | |
3705 | ||
3706 | case BFD_RELOC_VTABLE_INHERIT: | |
3707 | case BFD_RELOC_VTABLE_ENTRY: | |
3708 | fixP->fx_done = 0; | |
3709 | return 1; | |
3710 | ||
3711 | default: | |
3712 | break; | |
3713 | } | |
3714 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
93382f6d | 3715 | *valp = value; |
47926f60 | 3716 | #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */ |
252b5132 RH |
3717 | md_number_to_chars (p, value, fixP->fx_size); |
3718 | ||
3719 | return 1; | |
3720 | } | |
252b5132 | 3721 | \f |
252b5132 RH |
3722 | #define MAX_LITTLENUMS 6 |
3723 | ||
47926f60 KH |
3724 | /* Turn the string pointed to by litP into a floating point constant |
3725 | of type TYPE, and emit the appropriate bytes. The number of | |
3726 | LITTLENUMS emitted is stored in *SIZEP. An error message is | |
3727 | returned, or NULL on OK. */ | |
3728 | ||
252b5132 RH |
3729 | char * |
3730 | md_atof (type, litP, sizeP) | |
2ab9b79e | 3731 | int type; |
252b5132 RH |
3732 | char *litP; |
3733 | int *sizeP; | |
3734 | { | |
3735 | int prec; | |
3736 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
3737 | LITTLENUM_TYPE *wordP; | |
3738 | char *t; | |
3739 | ||
3740 | switch (type) | |
3741 | { | |
3742 | case 'f': | |
3743 | case 'F': | |
3744 | prec = 2; | |
3745 | break; | |
3746 | ||
3747 | case 'd': | |
3748 | case 'D': | |
3749 | prec = 4; | |
3750 | break; | |
3751 | ||
3752 | case 'x': | |
3753 | case 'X': | |
3754 | prec = 5; | |
3755 | break; | |
3756 | ||
3757 | default: | |
3758 | *sizeP = 0; | |
3759 | return _("Bad call to md_atof ()"); | |
3760 | } | |
3761 | t = atof_ieee (input_line_pointer, type, words); | |
3762 | if (t) | |
3763 | input_line_pointer = t; | |
3764 | ||
3765 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
3766 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with | |
3767 | the bigendian 386. */ | |
3768 | for (wordP = words + prec - 1; prec--;) | |
3769 | { | |
3770 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); | |
3771 | litP += sizeof (LITTLENUM_TYPE); | |
3772 | } | |
3773 | return 0; | |
3774 | } | |
3775 | \f | |
3776 | char output_invalid_buf[8]; | |
3777 | ||
252b5132 RH |
3778 | static char * |
3779 | output_invalid (c) | |
3780 | int c; | |
3781 | { | |
3782 | if (isprint (c)) | |
3783 | sprintf (output_invalid_buf, "'%c'", c); | |
3784 | else | |
3785 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
3786 | return output_invalid_buf; | |
3787 | } | |
3788 | ||
af6bdddf | 3789 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
3790 | |
3791 | static const reg_entry * | |
3792 | parse_register (reg_string, end_op) | |
3793 | char *reg_string; | |
3794 | char **end_op; | |
3795 | { | |
af6bdddf AM |
3796 | char *s = reg_string; |
3797 | char *p; | |
252b5132 RH |
3798 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
3799 | const reg_entry *r; | |
3800 | ||
3801 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
3802 | if (*s == REGISTER_PREFIX) | |
3803 | ++s; | |
3804 | ||
3805 | if (is_space_char (*s)) | |
3806 | ++s; | |
3807 | ||
3808 | p = reg_name_given; | |
af6bdddf | 3809 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
3810 | { |
3811 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
3812 | return (const reg_entry *) NULL; |
3813 | s++; | |
252b5132 RH |
3814 | } |
3815 | ||
6588847e DN |
3816 | /* For naked regs, make sure that we are not dealing with an identifier. |
3817 | This prevents confusing an identifier like `eax_var' with register | |
3818 | `eax'. */ | |
3819 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
3820 | return (const reg_entry *) NULL; | |
3821 | ||
af6bdddf | 3822 | *end_op = s; |
252b5132 RH |
3823 | |
3824 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
3825 | ||
5f47d35b | 3826 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 3827 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 3828 | { |
5f47d35b AM |
3829 | if (is_space_char (*s)) |
3830 | ++s; | |
3831 | if (*s == '(') | |
3832 | { | |
af6bdddf | 3833 | ++s; |
5f47d35b AM |
3834 | if (is_space_char (*s)) |
3835 | ++s; | |
3836 | if (*s >= '0' && *s <= '7') | |
3837 | { | |
3838 | r = &i386_float_regtab[*s - '0']; | |
af6bdddf | 3839 | ++s; |
5f47d35b AM |
3840 | if (is_space_char (*s)) |
3841 | ++s; | |
3842 | if (*s == ')') | |
3843 | { | |
3844 | *end_op = s + 1; | |
3845 | return r; | |
3846 | } | |
5f47d35b | 3847 | } |
47926f60 | 3848 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
3849 | return (const reg_entry *) NULL; |
3850 | } | |
3851 | } | |
3852 | ||
252b5132 RH |
3853 | return r; |
3854 | } | |
3855 | \f | |
4cc782b5 | 3856 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
65172ab8 | 3857 | const char *md_shortopts = "kVQ:sq"; |
252b5132 | 3858 | #else |
65172ab8 | 3859 | const char *md_shortopts = "q"; |
252b5132 RH |
3860 | #endif |
3861 | struct option md_longopts[] = { | |
3862 | {NULL, no_argument, NULL, 0} | |
3863 | }; | |
3864 | size_t md_longopts_size = sizeof (md_longopts); | |
3865 | ||
3866 | int | |
3867 | md_parse_option (c, arg) | |
3868 | int c; | |
ab9da554 | 3869 | char *arg ATTRIBUTE_UNUSED; |
252b5132 RH |
3870 | { |
3871 | switch (c) | |
3872 | { | |
a38cf1db AM |
3873 | case 'q': |
3874 | quiet_warnings = 1; | |
252b5132 RH |
3875 | break; |
3876 | ||
3877 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
3878 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
3879 | should be emitted or not. FIXME: Not implemented. */ | |
3880 | case 'Q': | |
252b5132 RH |
3881 | break; |
3882 | ||
3883 | /* -V: SVR4 argument to print version ID. */ | |
3884 | case 'V': | |
3885 | print_version_id (); | |
3886 | break; | |
3887 | ||
a38cf1db AM |
3888 | /* -k: Ignore for FreeBSD compatibility. */ |
3889 | case 'k': | |
252b5132 | 3890 | break; |
4cc782b5 ILT |
3891 | |
3892 | case 's': | |
3893 | /* -s: On i386 Solaris, this tells the native assembler to use | |
3894 | .stab instead of .stab.excl. We always use .stab anyhow. */ | |
3895 | break; | |
252b5132 RH |
3896 | #endif |
3897 | ||
3898 | default: | |
3899 | return 0; | |
3900 | } | |
3901 | return 1; | |
3902 | } | |
3903 | ||
3904 | void | |
3905 | md_show_usage (stream) | |
3906 | FILE *stream; | |
3907 | { | |
4cc782b5 ILT |
3908 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3909 | fprintf (stream, _("\ | |
a38cf1db AM |
3910 | -Q ignored\n\ |
3911 | -V print assembler version number\n\ | |
3912 | -k ignored\n\ | |
3913 | -q quieten some warnings\n\ | |
3914 | -s ignored\n")); | |
3915 | #else | |
3916 | fprintf (stream, _("\ | |
3917 | -q quieten some warnings\n")); | |
4cc782b5 | 3918 | #endif |
252b5132 RH |
3919 | } |
3920 | ||
3921 | #ifdef BFD_ASSEMBLER | |
4c63da97 AM |
3922 | #if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \ |
3923 | || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \ | |
3924 | || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT))) | |
252b5132 RH |
3925 | |
3926 | /* Pick the target format to use. */ | |
3927 | ||
47926f60 | 3928 | const char * |
252b5132 RH |
3929 | i386_target_format () |
3930 | { | |
3931 | switch (OUTPUT_FLAVOR) | |
3932 | { | |
4c63da97 AM |
3933 | #ifdef OBJ_MAYBE_AOUT |
3934 | case bfd_target_aout_flavour: | |
47926f60 | 3935 | return AOUT_TARGET_FORMAT; |
4c63da97 AM |
3936 | #endif |
3937 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
3938 | case bfd_target_coff_flavour: |
3939 | return "coff-i386"; | |
4c63da97 AM |
3940 | #endif |
3941 | #ifdef OBJ_MAYBE_ELF | |
252b5132 RH |
3942 | case bfd_target_elf_flavour: |
3943 | return "elf32-i386"; | |
4c63da97 | 3944 | #endif |
252b5132 RH |
3945 | default: |
3946 | abort (); | |
3947 | return NULL; | |
3948 | } | |
3949 | } | |
3950 | ||
47926f60 KH |
3951 | #endif /* OBJ_MAYBE_ more than one */ |
3952 | #endif /* BFD_ASSEMBLER */ | |
252b5132 | 3953 | \f |
252b5132 RH |
3954 | symbolS * |
3955 | md_undefined_symbol (name) | |
3956 | char *name; | |
3957 | { | |
18dc2407 ILT |
3958 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
3959 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
3960 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
3961 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
3962 | { |
3963 | if (!GOT_symbol) | |
3964 | { | |
3965 | if (symbol_find (name)) | |
3966 | as_bad (_("GOT already in symbol table")); | |
3967 | GOT_symbol = symbol_new (name, undefined_section, | |
3968 | (valueT) 0, &zero_address_frag); | |
3969 | }; | |
3970 | return GOT_symbol; | |
3971 | } | |
252b5132 RH |
3972 | return 0; |
3973 | } | |
3974 | ||
3975 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 3976 | |
252b5132 RH |
3977 | valueT |
3978 | md_section_align (segment, size) | |
ab9da554 | 3979 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
3980 | valueT size; |
3981 | { | |
252b5132 | 3982 | #ifdef BFD_ASSEMBLER |
4c63da97 AM |
3983 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3984 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
3985 | { | |
3986 | /* For a.out, force the section size to be aligned. If we don't do | |
3987 | this, BFD will align it for us, but it will not write out the | |
3988 | final bytes of the section. This may be a bug in BFD, but it is | |
3989 | easier to fix it here since that is how the other a.out targets | |
3990 | work. */ | |
3991 | int align; | |
3992 | ||
3993 | align = bfd_get_section_alignment (stdoutput, segment); | |
3994 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
3995 | } | |
252b5132 RH |
3996 | #endif |
3997 | #endif | |
3998 | ||
3999 | return size; | |
4000 | } | |
4001 | ||
4002 | /* On the i386, PC-relative offsets are relative to the start of the | |
4003 | next instruction. That is, the address of the offset, plus its | |
4004 | size, since the offset is always the last part of the insn. */ | |
4005 | ||
4006 | long | |
4007 | md_pcrel_from (fixP) | |
4008 | fixS *fixP; | |
4009 | { | |
4010 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
4011 | } | |
4012 | ||
4013 | #ifndef I386COFF | |
4014 | ||
4015 | static void | |
4016 | s_bss (ignore) | |
ab9da554 | 4017 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
4018 | { |
4019 | register int temp; | |
4020 | ||
4021 | temp = get_absolute_expression (); | |
4022 | subseg_set (bss_section, (subsegT) temp); | |
4023 | demand_empty_rest_of_line (); | |
4024 | } | |
4025 | ||
4026 | #endif | |
4027 | ||
252b5132 RH |
4028 | #ifdef BFD_ASSEMBLER |
4029 | ||
4030 | void | |
4031 | i386_validate_fix (fixp) | |
4032 | fixS *fixp; | |
4033 | { | |
4034 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
4035 | { | |
4036 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
4037 | fixp->fx_subsy = 0; | |
4038 | } | |
4039 | } | |
4040 | ||
252b5132 RH |
4041 | arelent * |
4042 | tc_gen_reloc (section, fixp) | |
ab9da554 | 4043 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
4044 | fixS *fixp; |
4045 | { | |
4046 | arelent *rel; | |
4047 | bfd_reloc_code_real_type code; | |
4048 | ||
4049 | switch (fixp->fx_r_type) | |
4050 | { | |
4051 | case BFD_RELOC_386_PLT32: | |
4052 | case BFD_RELOC_386_GOT32: | |
4053 | case BFD_RELOC_386_GOTOFF: | |
4054 | case BFD_RELOC_386_GOTPC: | |
4055 | case BFD_RELOC_RVA: | |
4056 | case BFD_RELOC_VTABLE_ENTRY: | |
4057 | case BFD_RELOC_VTABLE_INHERIT: | |
4058 | code = fixp->fx_r_type; | |
4059 | break; | |
4060 | default: | |
93382f6d | 4061 | if (fixp->fx_pcrel) |
252b5132 | 4062 | { |
93382f6d AM |
4063 | switch (fixp->fx_size) |
4064 | { | |
4065 | default: | |
d0b47220 | 4066 | as_bad (_("can not do %d byte pc-relative relocation"), |
93382f6d AM |
4067 | fixp->fx_size); |
4068 | code = BFD_RELOC_32_PCREL; | |
4069 | break; | |
4070 | case 1: code = BFD_RELOC_8_PCREL; break; | |
4071 | case 2: code = BFD_RELOC_16_PCREL; break; | |
4072 | case 4: code = BFD_RELOC_32_PCREL; break; | |
4073 | } | |
4074 | } | |
4075 | else | |
4076 | { | |
4077 | switch (fixp->fx_size) | |
4078 | { | |
4079 | default: | |
d0b47220 | 4080 | as_bad (_("can not do %d byte relocation"), fixp->fx_size); |
93382f6d AM |
4081 | code = BFD_RELOC_32; |
4082 | break; | |
4083 | case 1: code = BFD_RELOC_8; break; | |
4084 | case 2: code = BFD_RELOC_16; break; | |
4085 | case 4: code = BFD_RELOC_32; break; | |
4086 | } | |
252b5132 RH |
4087 | } |
4088 | break; | |
4089 | } | |
252b5132 RH |
4090 | |
4091 | if (code == BFD_RELOC_32 | |
4092 | && GOT_symbol | |
4093 | && fixp->fx_addsy == GOT_symbol) | |
4094 | code = BFD_RELOC_386_GOTPC; | |
4095 | ||
4096 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
4097 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
4098 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
4099 | |
4100 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
4101 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
4102 | vtable entry to be used in the relocation's section offset. */ | |
4103 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
4104 | rel->address = fixp->fx_offset; | |
4105 | ||
4106 | if (fixp->fx_pcrel) | |
4107 | rel->addend = fixp->fx_addnumber; | |
4108 | else | |
4109 | rel->addend = 0; | |
4110 | ||
4111 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); | |
4112 | if (rel->howto == NULL) | |
4113 | { | |
4114 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 4115 | _("cannot represent relocation type %s"), |
252b5132 RH |
4116 | bfd_get_reloc_code_name (code)); |
4117 | /* Set howto to a garbage value so that we can keep going. */ | |
4118 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
4119 | assert (rel->howto != NULL); | |
4120 | } | |
4121 | ||
4122 | return rel; | |
4123 | } | |
4124 | ||
47926f60 | 4125 | #else /* ! BFD_ASSEMBLER */ |
252b5132 RH |
4126 | |
4127 | #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) | |
4128 | void | |
4129 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) | |
4130 | char *where; | |
4131 | fixS *fixP; | |
4132 | relax_addressT segment_address_in_file; | |
4133 | { | |
47926f60 KH |
4134 | /* In: length of relocation (or of address) in chars: 1, 2 or 4. |
4135 | Out: GNU LD relocation length code: 0, 1, or 2. */ | |
252b5132 | 4136 | |
47926f60 | 4137 | static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 }; |
252b5132 RH |
4138 | long r_symbolnum; |
4139 | ||
4140 | know (fixP->fx_addsy != NULL); | |
4141 | ||
4142 | md_number_to_chars (where, | |
4143 | (valueT) (fixP->fx_frag->fr_address | |
4144 | + fixP->fx_where - segment_address_in_file), | |
4145 | 4); | |
4146 | ||
4147 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) | |
4148 | ? S_GET_TYPE (fixP->fx_addsy) | |
4149 | : fixP->fx_addsy->sy_number); | |
4150 | ||
4151 | where[6] = (r_symbolnum >> 16) & 0x0ff; | |
4152 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
4153 | where[4] = r_symbolnum & 0x0ff; | |
4154 | where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) | |
4155 | | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) | |
4156 | | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); | |
4157 | } | |
4158 | ||
47926f60 | 4159 | #endif /* OBJ_AOUT or OBJ_BOUT. */ |
252b5132 RH |
4160 | |
4161 | #if defined (I386COFF) | |
4162 | ||
4163 | short | |
4164 | tc_coff_fix2rtype (fixP) | |
4165 | fixS *fixP; | |
4166 | { | |
4167 | if (fixP->fx_r_type == R_IMAGEBASE) | |
4168 | return R_IMAGEBASE; | |
4169 | ||
4170 | return (fixP->fx_pcrel ? | |
4171 | (fixP->fx_size == 1 ? R_PCRBYTE : | |
4172 | fixP->fx_size == 2 ? R_PCRWORD : | |
4173 | R_PCRLONG) : | |
4174 | (fixP->fx_size == 1 ? R_RELBYTE : | |
4175 | fixP->fx_size == 2 ? R_RELWORD : | |
4176 | R_DIR32)); | |
4177 | } | |
4178 | ||
4179 | int | |
4180 | tc_coff_sizemachdep (frag) | |
4181 | fragS *frag; | |
4182 | { | |
4183 | if (frag->fr_next) | |
4184 | return (frag->fr_next->fr_address - frag->fr_address); | |
4185 | else | |
4186 | return 0; | |
4187 | } | |
4188 | ||
47926f60 | 4189 | #endif /* I386COFF */ |
252b5132 | 4190 | |
47926f60 | 4191 | #endif /* ! BFD_ASSEMBLER */ |
64a0c779 DN |
4192 | \f |
4193 | /* Parse operands using Intel syntax. This implements a recursive descent | |
4194 | parser based on the BNF grammar published in Appendix B of the MASM 6.1 | |
4195 | Programmer's Guide. | |
4196 | ||
4197 | FIXME: We do not recognize the full operand grammar defined in the MASM | |
4198 | documentation. In particular, all the structure/union and | |
4199 | high-level macro operands are missing. | |
4200 | ||
4201 | Uppercase words are terminals, lower case words are non-terminals. | |
4202 | Objects surrounded by double brackets '[[' ']]' are optional. Vertical | |
4203 | bars '|' denote choices. Most grammar productions are implemented in | |
4204 | functions called 'intel_<production>'. | |
4205 | ||
4206 | Initial production is 'expr'. | |
4207 | ||
64a0c779 DN |
4208 | addOp + | - |
4209 | ||
4210 | alpha [a-zA-Z] | |
4211 | ||
4212 | byteRegister AL | AH | BL | BH | CL | CH | DL | DH | |
4213 | ||
4214 | constant digits [[ radixOverride ]] | |
4215 | ||
4216 | dataType BYTE | WORD | DWORD | QWORD | XWORD | |
4217 | ||
4218 | digits decdigit | |
4219 | | digits decdigit | |
4220 | | digits hexdigit | |
4221 | ||
4222 | decdigit [0-9] | |
4223 | ||
4224 | e05 e05 addOp e06 | |
4225 | | e06 | |
4226 | ||
4227 | e06 e06 mulOp e09 | |
4228 | | e09 | |
4229 | ||
4230 | e09 OFFSET e10 | |
4231 | | e09 PTR e10 | |
4232 | | e09 : e10 | |
4233 | | e10 | |
4234 | ||
4235 | e10 e10 [ expr ] | |
4236 | | e11 | |
4237 | ||
4238 | e11 ( expr ) | |
4239 | | [ expr ] | |
4240 | | constant | |
4241 | | dataType | |
4242 | | id | |
4243 | | $ | |
4244 | | register | |
4245 | ||
4246 | => expr SHORT e05 | |
4247 | | e05 | |
4248 | ||
4249 | gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX | |
4250 | | BP | EBP | SP | ESP | DI | EDI | SI | ESI | |
4251 | ||
4252 | hexdigit a | b | c | d | e | f | |
4253 | | A | B | C | D | E | F | |
4254 | ||
4255 | id alpha | |
4256 | | id alpha | |
4257 | | id decdigit | |
4258 | ||
4259 | mulOp * | / | MOD | |
4260 | ||
4261 | quote " | ' | |
4262 | ||
4263 | register specialRegister | |
4264 | | gpRegister | |
4265 | | byteRegister | |
4266 | ||
4267 | segmentRegister CS | DS | ES | FS | GS | SS | |
4268 | ||
4269 | specialRegister CR0 | CR2 | CR3 | |
4270 | | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 | |
4271 | | TR3 | TR4 | TR5 | TR6 | TR7 | |
4272 | ||
64a0c779 DN |
4273 | We simplify the grammar in obvious places (e.g., register parsing is |
4274 | done by calling parse_register) and eliminate immediate left recursion | |
4275 | to implement a recursive-descent parser. | |
4276 | ||
4277 | expr SHORT e05 | |
4278 | | e05 | |
4279 | ||
4280 | e05 e06 e05' | |
4281 | ||
4282 | e05' addOp e06 e05' | |
4283 | | Empty | |
4284 | ||
4285 | e06 e09 e06' | |
4286 | ||
4287 | e06' mulOp e09 e06' | |
4288 | | Empty | |
4289 | ||
4290 | e09 OFFSET e10 e09' | |
4291 | | e10 e09' | |
4292 | ||
4293 | e09' PTR e10 e09' | |
4294 | | : e10 e09' | |
4295 | | Empty | |
4296 | ||
4297 | e10 e11 e10' | |
4298 | ||
4299 | e10' [ expr ] e10' | |
4300 | | Empty | |
4301 | ||
4302 | e11 ( expr ) | |
4303 | | [ expr ] | |
4304 | | BYTE | |
4305 | | WORD | |
4306 | | DWORD | |
4307 | | QWORD | |
4308 | | XWORD | |
4309 | | . | |
4310 | | $ | |
4311 | | register | |
4312 | | id | |
4313 | | constant */ | |
4314 | ||
4315 | /* Parsing structure for the intel syntax parser. Used to implement the | |
4316 | semantic actions for the operand grammar. */ | |
4317 | struct intel_parser_s | |
4318 | { | |
4319 | char *op_string; /* The string being parsed. */ | |
4320 | int got_a_float; /* Whether the operand is a float. */ | |
4a1805b1 | 4321 | int op_modifier; /* Operand modifier. */ |
64a0c779 DN |
4322 | int is_mem; /* 1 if operand is memory reference. */ |
4323 | const reg_entry *reg; /* Last register reference found. */ | |
4324 | char *disp; /* Displacement string being built. */ | |
4325 | }; | |
4326 | ||
4327 | static struct intel_parser_s intel_parser; | |
4328 | ||
4329 | /* Token structure for parsing intel syntax. */ | |
4330 | struct intel_token | |
4331 | { | |
4332 | int code; /* Token code. */ | |
4333 | const reg_entry *reg; /* Register entry for register tokens. */ | |
4334 | char *str; /* String representation. */ | |
4335 | }; | |
4336 | ||
4337 | static struct intel_token cur_token, prev_token; | |
4338 | ||
50705ef4 AM |
4339 | |
4340 | /* Token codes for the intel parser. Since T_SHORT is already used | |
4341 | by COFF, undefine it first to prevent a warning. */ | |
64a0c779 DN |
4342 | #define T_NIL -1 |
4343 | #define T_CONST 1 | |
4344 | #define T_REG 2 | |
4345 | #define T_BYTE 3 | |
4346 | #define T_WORD 4 | |
4347 | #define T_DWORD 5 | |
4348 | #define T_QWORD 6 | |
4349 | #define T_XWORD 7 | |
50705ef4 | 4350 | #undef T_SHORT |
64a0c779 DN |
4351 | #define T_SHORT 8 |
4352 | #define T_OFFSET 9 | |
4353 | #define T_PTR 10 | |
4354 | #define T_ID 11 | |
4355 | ||
4356 | /* Prototypes for intel parser functions. */ | |
4357 | static int intel_match_token PARAMS ((int code)); | |
cce0cbdc DN |
4358 | static void intel_get_token PARAMS ((void)); |
4359 | static void intel_putback_token PARAMS ((void)); | |
4360 | static int intel_expr PARAMS ((void)); | |
4361 | static int intel_e05 PARAMS ((void)); | |
4362 | static int intel_e05_1 PARAMS ((void)); | |
4363 | static int intel_e06 PARAMS ((void)); | |
4364 | static int intel_e06_1 PARAMS ((void)); | |
4365 | static int intel_e09 PARAMS ((void)); | |
4366 | static int intel_e09_1 PARAMS ((void)); | |
4367 | static int intel_e10 PARAMS ((void)); | |
4368 | static int intel_e10_1 PARAMS ((void)); | |
4369 | static int intel_e11 PARAMS ((void)); | |
64a0c779 | 4370 | |
64a0c779 DN |
4371 | static int |
4372 | i386_intel_operand (operand_string, got_a_float) | |
4373 | char *operand_string; | |
4374 | int got_a_float; | |
4375 | { | |
4376 | int ret; | |
4377 | char *p; | |
4378 | ||
4379 | /* Initialize token holders. */ | |
4380 | cur_token.code = prev_token.code = T_NIL; | |
4381 | cur_token.reg = prev_token.reg = NULL; | |
4382 | cur_token.str = prev_token.str = NULL; | |
4383 | ||
4384 | /* Initialize parser structure. */ | |
4385 | p = intel_parser.op_string = (char *)malloc (strlen (operand_string) + 1); | |
4386 | if (p == NULL) | |
4387 | abort (); | |
4388 | strcpy (intel_parser.op_string, operand_string); | |
4389 | intel_parser.got_a_float = got_a_float; | |
4390 | intel_parser.op_modifier = -1; | |
4391 | intel_parser.is_mem = 0; | |
4392 | intel_parser.reg = NULL; | |
4393 | intel_parser.disp = (char *)malloc (strlen (operand_string) + 1); | |
4394 | if (intel_parser.disp == NULL) | |
4395 | abort (); | |
4396 | intel_parser.disp[0] = '\0'; | |
4397 | ||
4398 | /* Read the first token and start the parser. */ | |
4399 | intel_get_token (); | |
4400 | ret = intel_expr (); | |
4401 | ||
4402 | if (ret) | |
4403 | { | |
4404 | /* If we found a memory reference, hand it over to i386_displacement | |
4405 | to fill in the rest of the operand fields. */ | |
4406 | if (intel_parser.is_mem) | |
4407 | { | |
4408 | if ((i.mem_operands == 1 | |
4409 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
4410 | || i.mem_operands == 2) | |
4411 | { | |
4412 | as_bad (_("too many memory references for '%s'"), | |
4413 | current_templates->start->name); | |
4414 | ret = 0; | |
4415 | } | |
4416 | else | |
4417 | { | |
4418 | char *s = intel_parser.disp; | |
4419 | i.mem_operands++; | |
4420 | ||
4421 | /* Add the displacement expression. */ | |
4422 | if (*s != '\0') | |
4423 | ret = i386_displacement (s, s + strlen (s)) | |
4424 | && i386_index_check (s); | |
4425 | } | |
4426 | } | |
4427 | ||
4428 | /* Constant and OFFSET expressions are handled by i386_immediate. */ | |
4429 | else if (intel_parser.op_modifier == OFFSET_FLAT | |
4430 | || intel_parser.reg == NULL) | |
4431 | ret = i386_immediate (intel_parser.disp); | |
4432 | } | |
4433 | ||
4434 | free (p); | |
4435 | free (intel_parser.disp); | |
4436 | ||
4437 | return ret; | |
4438 | } | |
4439 | ||
64a0c779 DN |
4440 | /* expr SHORT e05 |
4441 | | e05 */ | |
4442 | static int | |
4443 | intel_expr () | |
4444 | { | |
4445 | /* expr SHORT e05 */ | |
4446 | if (cur_token.code == T_SHORT) | |
4447 | { | |
4448 | intel_parser.op_modifier = SHORT; | |
4449 | intel_match_token (T_SHORT); | |
4450 | ||
4451 | return (intel_e05 ()); | |
4452 | } | |
4453 | ||
4454 | /* expr e05 */ | |
4455 | else | |
4456 | return intel_e05 (); | |
4457 | } | |
4458 | ||
64a0c779 DN |
4459 | /* e05 e06 e05' |
4460 | ||
4a1805b1 | 4461 | e05' addOp e06 e05' |
64a0c779 DN |
4462 | | Empty */ |
4463 | static int | |
4464 | intel_e05 () | |
4465 | { | |
4466 | return (intel_e06 () && intel_e05_1 ()); | |
4467 | } | |
4468 | ||
4469 | static int | |
4470 | intel_e05_1 () | |
4471 | { | |
4472 | /* e05' addOp e06 e05' */ | |
4473 | if (cur_token.code == '+' || cur_token.code == '-') | |
4474 | { | |
4475 | strcat (intel_parser.disp, cur_token.str); | |
4476 | intel_match_token (cur_token.code); | |
4477 | ||
4478 | return (intel_e06 () && intel_e05_1 ()); | |
4479 | } | |
4480 | ||
4481 | /* e05' Empty */ | |
4482 | else | |
4483 | return 1; | |
4a1805b1 | 4484 | } |
64a0c779 DN |
4485 | |
4486 | /* e06 e09 e06' | |
4487 | ||
4488 | e06' mulOp e09 e06' | |
4489 | | Empty */ | |
4490 | static int | |
4491 | intel_e06 () | |
4492 | { | |
4493 | return (intel_e09 () && intel_e06_1 ()); | |
4494 | } | |
4495 | ||
4496 | static int | |
4497 | intel_e06_1 () | |
4498 | { | |
4499 | /* e06' mulOp e09 e06' */ | |
4500 | if (cur_token.code == '*' || cur_token.code == '/') | |
4501 | { | |
4502 | strcat (intel_parser.disp, cur_token.str); | |
4503 | intel_match_token (cur_token.code); | |
4504 | ||
4505 | return (intel_e09 () && intel_e06_1 ()); | |
4506 | } | |
4a1805b1 | 4507 | |
64a0c779 | 4508 | /* e06' Empty */ |
4a1805b1 | 4509 | else |
64a0c779 DN |
4510 | return 1; |
4511 | } | |
4512 | ||
64a0c779 DN |
4513 | /* e09 OFFSET e10 e09' |
4514 | | e10 e09' | |
4515 | ||
4516 | e09' PTR e10 e09' | |
4517 | | : e10 e09' | |
4518 | | Empty */ | |
4519 | static int | |
4520 | intel_e09 () | |
4521 | { | |
4522 | /* e09 OFFSET e10 e09' */ | |
4523 | if (cur_token.code == T_OFFSET) | |
4524 | { | |
4525 | intel_parser.is_mem = 0; | |
4526 | intel_parser.op_modifier = OFFSET_FLAT; | |
4527 | intel_match_token (T_OFFSET); | |
4528 | ||
4529 | return (intel_e10 () && intel_e09_1 ()); | |
4530 | } | |
4531 | ||
4532 | /* e09 e10 e09' */ | |
4533 | else | |
4534 | return (intel_e10 () && intel_e09_1 ()); | |
4535 | } | |
4536 | ||
4537 | static int | |
4538 | intel_e09_1 () | |
4539 | { | |
4540 | /* e09' PTR e10 e09' */ | |
4541 | if (cur_token.code == T_PTR) | |
4542 | { | |
4543 | if (prev_token.code == T_BYTE) | |
4544 | i.suffix = BYTE_MNEM_SUFFIX; | |
4545 | ||
4546 | else if (prev_token.code == T_WORD) | |
4547 | { | |
4548 | if (intel_parser.got_a_float == 2) /* "fi..." */ | |
4549 | i.suffix = SHORT_MNEM_SUFFIX; | |
4550 | else | |
4551 | i.suffix = WORD_MNEM_SUFFIX; | |
4552 | } | |
4553 | ||
4554 | else if (prev_token.code == T_DWORD) | |
4555 | { | |
4556 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
4557 | i.suffix = SHORT_MNEM_SUFFIX; | |
4558 | else | |
4559 | i.suffix = LONG_MNEM_SUFFIX; | |
4560 | } | |
4561 | ||
4562 | else if (prev_token.code == T_QWORD) | |
f16b83df JH |
4563 | { |
4564 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
4565 | i.suffix = LONG_MNEM_SUFFIX; | |
4566 | else | |
4567 | { | |
4568 | as_bad (_("operand modifier `%s' supported only for i387 operations\n"), | |
4569 | prev_token.str); | |
4570 | return 0; | |
4571 | } | |
4572 | } | |
64a0c779 DN |
4573 | |
4574 | else if (prev_token.code == T_XWORD) | |
4575 | i.suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
4576 | ||
4577 | else | |
4578 | { | |
4579 | as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str); | |
4580 | return 0; | |
4581 | } | |
4582 | ||
4583 | intel_match_token (T_PTR); | |
4584 | ||
4585 | return (intel_e10 () && intel_e09_1 ()); | |
4586 | } | |
4587 | ||
4588 | /* e09 : e10 e09' */ | |
4589 | else if (cur_token.code == ':') | |
4590 | { | |
4591 | intel_parser.is_mem = 1; | |
4592 | ||
4593 | return (intel_match_token (':') && intel_e10 () && intel_e09_1 ()); | |
4594 | } | |
4595 | ||
4596 | /* e09' Empty */ | |
4597 | else | |
4598 | return 1; | |
4599 | } | |
4600 | ||
4601 | /* e10 e11 e10' | |
4602 | ||
4603 | e10' [ expr ] e10' | |
4604 | | Empty */ | |
4605 | static int | |
4606 | intel_e10 () | |
4607 | { | |
4608 | return (intel_e11 () && intel_e10_1 ()); | |
4609 | } | |
4610 | ||
4611 | static int | |
4612 | intel_e10_1 () | |
4613 | { | |
4614 | /* e10' [ expr ] e10' */ | |
4615 | if (cur_token.code == '[') | |
4616 | { | |
4617 | intel_match_token ('['); | |
4618 | intel_parser.is_mem = 1; | |
4a1805b1 | 4619 | |
64a0c779 DN |
4620 | /* Add a '+' to the displacement string if necessary. */ |
4621 | if (*intel_parser.disp != '\0') | |
4622 | strcat (intel_parser.disp, "+"); | |
4623 | ||
4624 | return (intel_expr () && intel_match_token (']') && intel_e10_1 ()); | |
4625 | } | |
4626 | ||
4627 | /* e10' Empty */ | |
4628 | else | |
4629 | return 1; | |
4630 | } | |
4631 | ||
64a0c779 DN |
4632 | /* e11 ( expr ) |
4633 | | [ expr ] | |
4634 | | BYTE | |
4635 | | WORD | |
4636 | | DWORD | |
4637 | | QWORD | |
4638 | | XWORD | |
4a1805b1 | 4639 | | $ |
64a0c779 DN |
4640 | | . |
4641 | | register | |
4642 | | id | |
4643 | | constant */ | |
4644 | static int | |
4645 | intel_e11 () | |
4646 | { | |
4647 | /* e11 ( expr ) */ | |
4648 | if (cur_token.code == '(') | |
4649 | { | |
4650 | intel_match_token ('('); | |
4651 | strcat (intel_parser.disp, "("); | |
4652 | ||
4653 | if (intel_expr () && intel_match_token (')')) | |
4654 | { | |
4655 | strcat (intel_parser.disp, ")"); | |
4656 | return 1; | |
4657 | } | |
4658 | else | |
4659 | return 0; | |
4660 | } | |
4661 | ||
4662 | /* e11 [ expr ] */ | |
4663 | else if (cur_token.code == '[') | |
4664 | { | |
4665 | intel_match_token ('['); | |
4666 | intel_parser.is_mem = 1; | |
4a1805b1 | 4667 | |
64a0c779 DN |
4668 | /* Operands for jump/call inside brackets denote absolute addresses. */ |
4669 | if (current_templates->start->opcode_modifier & Jump | |
4670 | || current_templates->start->opcode_modifier & JumpDword | |
4671 | || current_templates->start->opcode_modifier & JumpByte | |
4672 | || current_templates->start->opcode_modifier & JumpInterSegment) | |
4673 | i.types[this_operand] |= JumpAbsolute; | |
4674 | ||
4675 | /* Add a '+' to the displacement string if necessary. */ | |
4676 | if (*intel_parser.disp != '\0') | |
4677 | strcat (intel_parser.disp, "+"); | |
4678 | ||
4679 | return (intel_expr () && intel_match_token (']')); | |
4680 | } | |
4681 | ||
4a1805b1 | 4682 | /* e11 BYTE |
64a0c779 DN |
4683 | | WORD |
4684 | | DWORD | |
4685 | | QWORD | |
4686 | | XWORD */ | |
4687 | else if (cur_token.code == T_BYTE | |
4688 | || cur_token.code == T_WORD | |
4689 | || cur_token.code == T_DWORD | |
4690 | || cur_token.code == T_QWORD | |
4691 | || cur_token.code == T_XWORD) | |
4692 | { | |
4693 | intel_match_token (cur_token.code); | |
4694 | ||
4695 | return 1; | |
4696 | } | |
4697 | ||
4698 | /* e11 $ | |
4699 | | . */ | |
4700 | else if (cur_token.code == '$' || cur_token.code == '.') | |
4701 | { | |
4702 | strcat (intel_parser.disp, cur_token.str); | |
4703 | intel_match_token (cur_token.code); | |
4704 | intel_parser.is_mem = 1; | |
4705 | ||
4706 | return 1; | |
4707 | } | |
4708 | ||
4709 | /* e11 register */ | |
4710 | else if (cur_token.code == T_REG) | |
4711 | { | |
4712 | const reg_entry *reg = intel_parser.reg = cur_token.reg; | |
4713 | ||
4714 | intel_match_token (T_REG); | |
4715 | ||
4716 | /* Check for segment change. */ | |
4717 | if (cur_token.code == ':') | |
4718 | { | |
4719 | if (reg->reg_type & (SReg2 | SReg3)) | |
4720 | { | |
4721 | switch (reg->reg_num) | |
4722 | { | |
4723 | case 0: | |
4724 | i.seg[i.mem_operands] = &es; | |
4725 | break; | |
4726 | case 1: | |
4727 | i.seg[i.mem_operands] = &cs; | |
4728 | break; | |
4729 | case 2: | |
4730 | i.seg[i.mem_operands] = &ss; | |
4731 | break; | |
4732 | case 3: | |
4733 | i.seg[i.mem_operands] = &ds; | |
4734 | break; | |
4735 | case 4: | |
4736 | i.seg[i.mem_operands] = &fs; | |
4737 | break; | |
4738 | case 5: | |
4739 | i.seg[i.mem_operands] = &gs; | |
4740 | break; | |
4741 | } | |
4742 | } | |
4743 | else | |
4744 | { | |
4745 | as_bad (_("`%s' is not a valid segment register"), reg->reg_name); | |
4746 | return 0; | |
4747 | } | |
4748 | } | |
4749 | ||
4750 | /* Not a segment register. Check for register scaling. */ | |
4751 | else if (cur_token.code == '*') | |
4752 | { | |
4753 | if (!intel_parser.is_mem) | |
4754 | { | |
4755 | as_bad (_("Register scaling only allowed in memory operands.")); | |
4756 | return 0; | |
4757 | } | |
4758 | ||
4a1805b1 | 4759 | /* What follows must be a valid scale. */ |
64a0c779 DN |
4760 | if (intel_match_token ('*') |
4761 | && strchr ("01248", *cur_token.str)) | |
4762 | { | |
4763 | i.index_reg = reg; | |
4764 | i.types[this_operand] |= BaseIndex; | |
4765 | ||
4766 | /* Set the scale after setting the register (otherwise, | |
4767 | i386_scale will complain) */ | |
4768 | i386_scale (cur_token.str); | |
4769 | intel_match_token (T_CONST); | |
4770 | } | |
4771 | else | |
4772 | { | |
4773 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
4774 | cur_token.str); | |
4775 | return 0; | |
4776 | } | |
4777 | } | |
4778 | ||
4779 | /* No scaling. If this is a memory operand, the register is either a | |
4780 | base register (first occurrence) or an index register (second | |
4781 | occurrence). */ | |
4782 | else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3))) | |
4783 | { | |
4784 | if (i.base_reg && i.index_reg) | |
4785 | { | |
4786 | as_bad (_("Too many register references in memory operand.\n")); | |
4787 | return 0; | |
4788 | } | |
4789 | ||
4790 | if (i.base_reg == NULL) | |
4791 | i.base_reg = reg; | |
4792 | else | |
4793 | i.index_reg = reg; | |
4794 | ||
4795 | i.types[this_operand] |= BaseIndex; | |
4796 | } | |
4797 | ||
4798 | /* Offset modifier. Add the register to the displacement string to be | |
4799 | parsed as an immediate expression after we're done. */ | |
4800 | else if (intel_parser.op_modifier == OFFSET_FLAT) | |
4801 | strcat (intel_parser.disp, reg->reg_name); | |
4a1805b1 | 4802 | |
64a0c779 DN |
4803 | /* It's neither base nor index nor offset. */ |
4804 | else | |
4805 | { | |
4806 | i.types[this_operand] |= reg->reg_type & ~BaseIndex; | |
4807 | i.op[this_operand].regs = reg; | |
4808 | i.reg_operands++; | |
4809 | } | |
4810 | ||
4811 | /* Since registers are not part of the displacement string (except | |
4812 | when we're parsing offset operands), we may need to remove any | |
4813 | preceding '+' from the displacement string. */ | |
4814 | if (*intel_parser.disp != '\0' | |
4815 | && intel_parser.op_modifier != OFFSET_FLAT) | |
4816 | { | |
4817 | char *s = intel_parser.disp; | |
4818 | s += strlen (s) - 1; | |
4819 | if (*s == '+') | |
4820 | *s = '\0'; | |
4821 | } | |
4822 | ||
4823 | return 1; | |
4824 | } | |
4a1805b1 | 4825 | |
64a0c779 DN |
4826 | /* e11 id */ |
4827 | else if (cur_token.code == T_ID) | |
4828 | { | |
4829 | /* Add the identifier to the displacement string. */ | |
4830 | strcat (intel_parser.disp, cur_token.str); | |
4831 | intel_match_token (T_ID); | |
4832 | ||
4833 | /* The identifier represents a memory reference only if it's not | |
4834 | preceded by an offset modifier. */ | |
4835 | if (intel_parser.op_modifier != OFFSET_FLAT | |
4836 | && intel_parser.op_modifier != FLAT) | |
4837 | intel_parser.is_mem = 1; | |
4838 | ||
4839 | return 1; | |
4840 | } | |
4841 | ||
4842 | /* e11 constant */ | |
4843 | else if (cur_token.code == T_CONST | |
4844 | || cur_token.code == '-' | |
4845 | || cur_token.code == '+') | |
4846 | { | |
4847 | char *save_str; | |
4848 | ||
4849 | /* Allow constants that start with `+' or `-'. */ | |
4850 | if (cur_token.code == '-' || cur_token.code == '+') | |
4851 | { | |
4852 | strcat (intel_parser.disp, cur_token.str); | |
4853 | intel_match_token (cur_token.code); | |
4854 | if (cur_token.code != T_CONST) | |
4855 | { | |
4856 | as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"), | |
4857 | cur_token.str); | |
4858 | return 0; | |
4859 | } | |
4860 | } | |
4861 | ||
4862 | save_str = (char *)malloc (strlen (cur_token.str) + 1); | |
4863 | if (save_str == NULL) | |
bc805888 | 4864 | abort (); |
64a0c779 DN |
4865 | strcpy (save_str, cur_token.str); |
4866 | ||
4867 | /* Get the next token to check for register scaling. */ | |
4868 | intel_match_token (cur_token.code); | |
4869 | ||
4870 | /* Check if this constant is a scaling factor for an index register. */ | |
4871 | if (cur_token.code == '*') | |
4872 | { | |
4873 | if (intel_match_token ('*') && cur_token.code == T_REG) | |
4874 | { | |
4875 | if (!intel_parser.is_mem) | |
4876 | { | |
4877 | as_bad (_("Register scaling only allowed in memory operands.")); | |
4878 | return 0; | |
4879 | } | |
4880 | ||
4a1805b1 | 4881 | /* The constant is followed by `* reg', so it must be |
64a0c779 DN |
4882 | a valid scale. */ |
4883 | if (strchr ("01248", *save_str)) | |
4884 | { | |
4885 | i.index_reg = cur_token.reg; | |
4886 | i.types[this_operand] |= BaseIndex; | |
4887 | ||
4888 | /* Set the scale after setting the register (otherwise, | |
4889 | i386_scale will complain) */ | |
4890 | i386_scale (save_str); | |
4891 | intel_match_token (T_REG); | |
4892 | ||
4893 | /* Since registers are not part of the displacement | |
4894 | string, we may need to remove any preceding '+' from | |
4895 | the displacement string. */ | |
4896 | if (*intel_parser.disp != '\0') | |
4897 | { | |
4898 | char *s = intel_parser.disp; | |
4899 | s += strlen (s) - 1; | |
4900 | if (*s == '+') | |
4901 | *s = '\0'; | |
4902 | } | |
4903 | ||
4904 | free (save_str); | |
4905 | ||
4906 | return 1; | |
4907 | } | |
4908 | else | |
4909 | return 0; | |
4910 | } | |
4911 | ||
4912 | /* The constant was not used for register scaling. Since we have | |
4913 | already consumed the token following `*' we now need to put it | |
4914 | back in the stream. */ | |
4915 | else | |
4916 | intel_putback_token (); | |
4917 | } | |
4918 | ||
4919 | /* Add the constant to the displacement string. */ | |
4920 | strcat (intel_parser.disp, save_str); | |
4921 | free (save_str); | |
4922 | ||
4923 | return 1; | |
4924 | } | |
4925 | ||
64a0c779 DN |
4926 | as_bad (_("Unrecognized token '%s'"), cur_token.str); |
4927 | return 0; | |
4928 | } | |
4929 | ||
64a0c779 DN |
4930 | /* Match the given token against cur_token. If they match, read the next |
4931 | token from the operand string. */ | |
4932 | static int | |
4933 | intel_match_token (code) | |
4934 | int code; | |
4935 | { | |
4936 | if (cur_token.code == code) | |
4937 | { | |
4938 | intel_get_token (); | |
4939 | return 1; | |
4940 | } | |
4941 | else | |
4942 | { | |
4943 | as_bad (_("Unexpected token `%s'\n"), cur_token.str); | |
4944 | return 0; | |
4945 | } | |
4946 | } | |
4947 | ||
64a0c779 DN |
4948 | /* Read a new token from intel_parser.op_string and store it in cur_token. */ |
4949 | static void | |
4950 | intel_get_token () | |
4951 | { | |
4952 | char *end_op; | |
4953 | const reg_entry *reg; | |
4954 | struct intel_token new_token; | |
4955 | ||
4956 | new_token.code = T_NIL; | |
4957 | new_token.reg = NULL; | |
4958 | new_token.str = NULL; | |
4959 | ||
4a1805b1 | 4960 | /* Free the memory allocated to the previous token and move |
64a0c779 DN |
4961 | cur_token to prev_token. */ |
4962 | if (prev_token.str) | |
4963 | free (prev_token.str); | |
4964 | ||
4965 | prev_token = cur_token; | |
4966 | ||
4967 | /* Skip whitespace. */ | |
4968 | while (is_space_char (*intel_parser.op_string)) | |
4969 | intel_parser.op_string++; | |
4970 | ||
4971 | /* Return an empty token if we find nothing else on the line. */ | |
4972 | if (*intel_parser.op_string == '\0') | |
4973 | { | |
4974 | cur_token = new_token; | |
4975 | return; | |
4976 | } | |
4977 | ||
4978 | /* The new token cannot be larger than the remainder of the operand | |
4979 | string. */ | |
4980 | new_token.str = (char *)malloc (strlen (intel_parser.op_string) + 1); | |
4981 | if (new_token.str == NULL) | |
bc805888 | 4982 | abort (); |
64a0c779 DN |
4983 | new_token.str[0] = '\0'; |
4984 | ||
4985 | if (strchr ("0123456789", *intel_parser.op_string)) | |
4986 | { | |
4987 | char *p = new_token.str; | |
4988 | char *q = intel_parser.op_string; | |
4989 | new_token.code = T_CONST; | |
4990 | ||
4991 | /* Allow any kind of identifier char to encompass floating point and | |
4992 | hexadecimal numbers. */ | |
4993 | while (is_identifier_char (*q)) | |
4994 | *p++ = *q++; | |
4995 | *p = '\0'; | |
4996 | ||
4997 | /* Recognize special symbol names [0-9][bf]. */ | |
4998 | if (strlen (intel_parser.op_string) == 2 | |
4a1805b1 | 4999 | && (intel_parser.op_string[1] == 'b' |
64a0c779 DN |
5000 | || intel_parser.op_string[1] == 'f')) |
5001 | new_token.code = T_ID; | |
5002 | } | |
5003 | ||
5004 | else if (strchr ("+-/*:[]()", *intel_parser.op_string)) | |
5005 | { | |
5006 | new_token.code = *intel_parser.op_string; | |
5007 | new_token.str[0] = *intel_parser.op_string; | |
5008 | new_token.str[1] = '\0'; | |
5009 | } | |
5010 | ||
5011 | else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg) | |
5012 | && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)) | |
5013 | { | |
5014 | new_token.code = T_REG; | |
5015 | new_token.reg = reg; | |
5016 | ||
5017 | if (*intel_parser.op_string == REGISTER_PREFIX) | |
5018 | { | |
5019 | new_token.str[0] = REGISTER_PREFIX; | |
5020 | new_token.str[1] = '\0'; | |
5021 | } | |
5022 | ||
5023 | strcat (new_token.str, reg->reg_name); | |
5024 | } | |
5025 | ||
5026 | else if (is_identifier_char (*intel_parser.op_string)) | |
5027 | { | |
5028 | char *p = new_token.str; | |
5029 | char *q = intel_parser.op_string; | |
5030 | ||
5031 | /* A '.' or '$' followed by an identifier char is an identifier. | |
5032 | Otherwise, it's operator '.' followed by an expression. */ | |
5033 | if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) | |
5034 | { | |
5035 | new_token.code = *q; | |
5036 | new_token.str[0] = *q; | |
5037 | new_token.str[1] = '\0'; | |
5038 | } | |
5039 | else | |
5040 | { | |
5041 | while (is_identifier_char (*q) || *q == '@') | |
5042 | *p++ = *q++; | |
5043 | *p = '\0'; | |
5044 | ||
5045 | if (strcasecmp (new_token.str, "BYTE") == 0) | |
5046 | new_token.code = T_BYTE; | |
5047 | ||
5048 | else if (strcasecmp (new_token.str, "WORD") == 0) | |
5049 | new_token.code = T_WORD; | |
5050 | ||
5051 | else if (strcasecmp (new_token.str, "DWORD") == 0) | |
5052 | new_token.code = T_DWORD; | |
5053 | ||
5054 | else if (strcasecmp (new_token.str, "QWORD") == 0) | |
5055 | new_token.code = T_QWORD; | |
5056 | ||
5057 | else if (strcasecmp (new_token.str, "XWORD") == 0) | |
5058 | new_token.code = T_XWORD; | |
5059 | ||
5060 | else if (strcasecmp (new_token.str, "PTR") == 0) | |
5061 | new_token.code = T_PTR; | |
5062 | ||
5063 | else if (strcasecmp (new_token.str, "SHORT") == 0) | |
5064 | new_token.code = T_SHORT; | |
5065 | ||
5066 | else if (strcasecmp (new_token.str, "OFFSET") == 0) | |
5067 | { | |
5068 | new_token.code = T_OFFSET; | |
5069 | ||
5070 | /* ??? This is not mentioned in the MASM grammar but gcc | |
5071 | makes use of it with -mintel-syntax. OFFSET may be | |
5072 | followed by FLAT: */ | |
5073 | if (strncasecmp (q, " FLAT:", 6) == 0) | |
5074 | strcat (new_token.str, " FLAT:"); | |
5075 | } | |
5076 | ||
5077 | /* ??? This is not mentioned in the MASM grammar. */ | |
5078 | else if (strcasecmp (new_token.str, "FLAT") == 0) | |
5079 | new_token.code = T_OFFSET; | |
5080 | ||
5081 | else | |
5082 | new_token.code = T_ID; | |
5083 | } | |
5084 | } | |
5085 | ||
5086 | else | |
5087 | as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string); | |
5088 | ||
5089 | intel_parser.op_string += strlen (new_token.str); | |
5090 | cur_token = new_token; | |
5091 | } | |
5092 | ||
64a0c779 DN |
5093 | /* Put cur_token back into the token stream and make cur_token point to |
5094 | prev_token. */ | |
5095 | static void | |
5096 | intel_putback_token () | |
5097 | { | |
5098 | intel_parser.op_string -= strlen (cur_token.str); | |
5099 | free (cur_token.str); | |
5100 | cur_token = prev_token; | |
4a1805b1 | 5101 | |
64a0c779 DN |
5102 | /* Forget prev_token. */ |
5103 | prev_token.code = T_NIL; | |
5104 | prev_token.reg = NULL; | |
5105 | prev_token.str = NULL; | |
5106 | } |