Commit | Line | Data |
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fecd2382 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
dddc8a82 ILT |
2 | Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 1998 |
3 | Free Software Foundation. | |
355afbcd | 4 | |
a39116f1 | 5 | This file is part of GAS, the GNU Assembler. |
355afbcd | 6 | |
a39116f1 RP |
7 | GAS is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
355afbcd | 11 | |
a39116f1 RP |
12 | GAS is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
355afbcd | 16 | |
a39116f1 | 17 | You should have received a copy of the GNU General Public License |
e592f0e6 ILT |
18 | along with GAS; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
fecd2382 | 21 | |
fecd2382 RP |
22 | /* |
23 | Intel 80386 machine specific gas. | |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
25 | Bugs & suggestions are completely welcome. This is free software. | |
26 | Please help us make it better. | |
a39116f1 | 27 | */ |
fecd2382 | 28 | |
4b77b129 ILT |
29 | #include <ctype.h> |
30 | ||
fecd2382 | 31 | #include "as.h" |
0877841d | 32 | #include "subsegs.h" |
a39116f1 | 33 | #include "opcode/i386.h" |
fecd2382 | 34 | |
f0b37b4a KR |
35 | #ifndef TC_RELOC |
36 | #define TC_RELOC(X,Y) (Y) | |
37 | #endif | |
38 | ||
73a8be66 ILT |
39 | #ifndef REGISTER_WARNINGS |
40 | #define REGISTER_WARNINGS 1 | |
41 | #endif | |
42 | ||
ec1e6bb8 ILT |
43 | #ifndef SCALE1_WHEN_NO_INDEX |
44 | /* Specifying a scale factor besides 1 when there is no index is | |
45 | futile. eg. `mov (%ebx,2),%al' does exactly the same as | |
46 | `mov (%ebx),%al'. To slavishly follow what the programmer | |
47 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ | |
48 | #define SCALE1_WHEN_NO_INDEX 1 | |
49 | #endif | |
50 | ||
61c49d66 | 51 | static unsigned int mode_from_disp_size PARAMS ((unsigned int)); |
f59fb6ca ILT |
52 | static int fits_in_signed_byte PARAMS ((long)); |
53 | static int fits_in_unsigned_byte PARAMS ((long)); | |
54 | static int fits_in_unsigned_word PARAMS ((long)); | |
55 | static int fits_in_signed_word PARAMS ((long)); | |
56 | static int smallest_imm_type PARAMS ((long)); | |
73a8be66 | 57 | static int add_prefix PARAMS ((unsigned int)); |
f59fb6ca ILT |
58 | static void set_16bit_code_flag PARAMS ((int)); |
59 | #ifdef BFD_ASSEMBLER | |
60 | static bfd_reloc_code_real_type reloc | |
61 | PARAMS ((int, int, bfd_reloc_code_real_type)); | |
62 | #endif | |
63 | ||
fecd2382 RP |
64 | /* 'md_assemble ()' gathers together information and puts it into a |
65 | i386_insn. */ | |
66 | ||
3c8df4ba | 67 | struct _i386_insn |
355afbcd KR |
68 | { |
69 | /* TM holds the template for the insn were currently assembling. */ | |
70 | template tm; | |
73a8be66 | 71 | |
668f52e0 ILT |
72 | /* SUFFIX holds the instruction mnemonic suffix if given. |
73 | (e.g. 'l' for 'movl') */ | |
355afbcd | 74 | char suffix; |
73a8be66 | 75 | |
355afbcd KR |
76 | /* Operands are coded with OPERANDS, TYPES, DISPS, IMMS, and REGS. */ |
77 | ||
78 | /* OPERANDS gives the number of given operands. */ | |
79 | unsigned int operands; | |
80 | ||
49864cfa KR |
81 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number |
82 | of given register, displacement, memory operands and immediate | |
83 | operands. */ | |
355afbcd KR |
84 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
85 | ||
86 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
49864cfa KR |
87 | search through DISPS [i] & IMMS [i] & REGS [i] for the required |
88 | operand. */ | |
355afbcd KR |
89 | unsigned int types[MAX_OPERANDS]; |
90 | ||
91 | /* Displacements (if given) for each operand. */ | |
92 | expressionS *disps[MAX_OPERANDS]; | |
93 | ||
f0b37b4a KR |
94 | /* Relocation type for operand */ |
95 | #ifdef BFD_ASSEMBLER | |
96 | enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS]; | |
97 | #else | |
98 | int disp_reloc[MAX_OPERANDS]; | |
99 | #endif | |
100 | ||
355afbcd KR |
101 | /* Immediate operands (if given) for each operand. */ |
102 | expressionS *imms[MAX_OPERANDS]; | |
103 | ||
104 | /* Register operands (if given) for each operand. */ | |
73a8be66 | 105 | const reg_entry *regs[MAX_OPERANDS]; |
355afbcd KR |
106 | |
107 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode | |
49864cfa | 108 | the base index byte below. */ |
73a8be66 ILT |
109 | const reg_entry *base_reg; |
110 | const reg_entry *index_reg; | |
355afbcd KR |
111 | unsigned int log2_scale_factor; |
112 | ||
4498e3d6 ILT |
113 | /* SEG gives the seg_entries of this insn. They are zero unless |
114 | explicit segment overrides are given. */ | |
115 | const seg_entry *seg[2]; /* segments for memory operands (if given) */ | |
355afbcd KR |
116 | |
117 | /* PREFIX holds all the given prefix opcodes (usually null). | |
ec1e6bb8 | 118 | PREFIXES is the number of prefix opcodes. */ |
355afbcd | 119 | unsigned int prefixes; |
ec1e6bb8 | 120 | unsigned char prefix[MAX_PREFIXES]; |
355afbcd | 121 | |
0351b70c | 122 | /* RM and SIB are the modrm byte and the sib byte where the |
73a8be66 | 123 | addressing modes of this insn are encoded. */ |
355afbcd KR |
124 | |
125 | modrm_byte rm; | |
0351b70c | 126 | sib_byte sib; |
3c8df4ba | 127 | }; |
355afbcd | 128 | |
3c8df4ba | 129 | typedef struct _i386_insn i386_insn; |
fecd2382 | 130 | |
4edc93e9 ILT |
131 | /* List of chars besides those in app.c:symbol_chars that can start an |
132 | operand. Used to prevent the scrubber eating vital white-space. */ | |
133 | #ifdef LEX_AT | |
134 | const char extra_symbol_chars[] = "*%-(@"; | |
135 | #else | |
136 | const char extra_symbol_chars[] = "*%-("; | |
137 | #endif | |
138 | ||
a39116f1 RP |
139 | /* This array holds the chars that always start a comment. If the |
140 | pre-processor is disabled, these aren't very useful */ | |
4edc93e9 ILT |
141 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX)) |
142 | /* Putting '/' here makes it impossible to use the divide operator. | |
143 | However, we need it for compatibility with SVR4 systems. */ | |
49864cfa | 144 | const char comment_chars[] = "#/"; |
0351b70c | 145 | #define PREFIX_SEPARATOR '\\' |
49864cfa | 146 | #else |
a39116f1 | 147 | const char comment_chars[] = "#"; |
0351b70c | 148 | #define PREFIX_SEPARATOR '/' |
49864cfa | 149 | #endif |
fecd2382 | 150 | |
a39116f1 RP |
151 | /* This array holds the chars that only start a comment at the beginning of |
152 | a line. If the line seems to have the form '# 123 filename' | |
153 | .line and .file directives will appear in the pre-processed output */ | |
154 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
155 | first line of the input file. This is because the compiler outputs | |
156 | #NO_APP at the beginning of its output. */ | |
157 | /* Also note that comments started like this one will always work if | |
f3d817d8 | 158 | '/' isn't otherwise defined. */ |
4edc93e9 | 159 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX)) |
ad660eb1 | 160 | const char line_comment_chars[] = ""; |
7b23213f KR |
161 | #else |
162 | const char line_comment_chars[] = "/"; | |
163 | #endif | |
0351b70c | 164 | |
355afbcd | 165 | const char line_separator_chars[] = ""; |
fecd2382 | 166 | |
a39116f1 RP |
167 | /* Chars that can be used to separate mant from exp in floating point nums */ |
168 | const char EXP_CHARS[] = "eE"; | |
fecd2382 | 169 | |
a39116f1 RP |
170 | /* Chars that mean this number is a floating point constant */ |
171 | /* As in 0f12.456 */ | |
172 | /* or 0d1.2345e12 */ | |
173 | const char FLT_CHARS[] = "fFdDxX"; | |
fecd2382 RP |
174 | |
175 | /* tables for lexical analysis */ | |
668f52e0 | 176 | static char mnemonic_chars[256]; |
fecd2382 RP |
177 | static char register_chars[256]; |
178 | static char operand_chars[256]; | |
fecd2382 RP |
179 | static char identifier_chars[256]; |
180 | static char digit_chars[256]; | |
181 | ||
182 | /* lexical macros */ | |
668f52e0 | 183 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
fecd2382 RP |
184 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) |
185 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
4edc93e9 | 186 | #define is_space_char(x) ((x) == ' ') |
fecd2382 RP |
187 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) |
188 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
189 | ||
190 | /* put here all non-digit non-letter charcters that may occur in an operand */ | |
f0b37b4a | 191 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
fecd2382 | 192 | |
fecd2382 RP |
193 | /* md_assemble() always leaves the strings it's passed unaltered. To |
194 | effect this we maintain a stack of saved characters that we've smashed | |
195 | with '\0's (indicating end of strings for various sub-fields of the | |
196 | assembler instruction). */ | |
197 | static char save_stack[32]; | |
198 | static char *save_stack_p; /* stack pointer */ | |
aa56747a ILT |
199 | #define END_STRING_AND_SAVE(s) \ |
200 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
201 | #define RESTORE_END_STRING(s) \ | |
202 | do { *(s) = *--save_stack_p; } while (0) | |
355afbcd KR |
203 | |
204 | /* The instruction we're assembling. */ | |
205 | static i386_insn i; | |
fecd2382 | 206 | |
4498e3d6 | 207 | /* Possible templates for current insn. */ |
0351b70c | 208 | static const templates *current_templates; |
4498e3d6 | 209 | |
fecd2382 RP |
210 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ |
211 | static expressionS disp_expressions[2], im_expressions[2]; | |
212 | ||
fecd2382 RP |
213 | static int this_operand; /* current operand we are working on */ |
214 | ||
ade614d5 KR |
215 | static int flag_do_long_jump; /* FIXME what does this do? */ |
216 | ||
c54c7aac KR |
217 | static int flag_16bit_code; /* 1 if we're writing 16-bit code, 0 if 32-bit */ |
218 | ||
3c8df4ba KR |
219 | /* Interface to relax_segment. |
220 | There are 2 relax states for 386 jump insns: one for conditional & | |
221 | one for unconditional jumps. This is because the these two types | |
222 | of jumps add different sizes to frags when we're figuring out what | |
223 | sort of jump to choose to reach a given label. */ | |
fecd2382 RP |
224 | |
225 | /* types */ | |
226 | #define COND_JUMP 1 /* conditional jump */ | |
227 | #define UNCOND_JUMP 2 /* unconditional jump */ | |
228 | /* sizes */ | |
0351b70c ILT |
229 | #define CODE16 1 |
230 | #define SMALL 0 | |
231 | #define SMALL16 (SMALL|CODE16) | |
232 | #define BIG 2 | |
233 | #define BIG16 (BIG|CODE16) | |
fecd2382 | 234 | |
3c8df4ba KR |
235 | #ifndef INLINE |
236 | #ifdef __GNUC__ | |
237 | #define INLINE __inline__ | |
238 | #else | |
239 | #define INLINE | |
240 | #endif | |
241 | #endif | |
242 | ||
ad660eb1 ILT |
243 | #define ENCODE_RELAX_STATE(type,size) \ |
244 | ((relax_substateT)((type<<2) | (size))) | |
fecd2382 | 245 | #define SIZE_FROM_RELAX_STATE(s) \ |
0351b70c ILT |
246 | ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) ) |
247 | ||
248 | /* This table is used by relax_frag to promote short jumps to long | |
249 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
250 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
251 | don't allow a short jump in a 32 bit code segment to be promoted to | |
252 | a 16 bit offset jump because it's slower (requires data size | |
253 | prefix), and doesn't work, unless the destination is in the bottom | |
254 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
fecd2382 | 255 | |
355afbcd KR |
256 | const relax_typeS md_relax_table[] = |
257 | { | |
49864cfa KR |
258 | /* The fields are: |
259 | 1) most positive reach of this state, | |
260 | 2) most negative reach of this state, | |
261 | 3) how many bytes this mode will add to the size of the current frag | |
262 | 4) which index into the table to try if we can't fit into this one. | |
263 | */ | |
355afbcd KR |
264 | {1, 1, 0, 0}, |
265 | {1, 1, 0, 0}, | |
266 | {1, 1, 0, 0}, | |
267 | {1, 1, 0, 0}, | |
268 | ||
0351b70c ILT |
269 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, |
270 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
3c8df4ba | 271 | /* dword conditionals adds 4 bytes to frag: |
0351b70c | 272 | 1 extra opcode byte, 3 extra displacement bytes. */ |
355afbcd | 273 | {0, 0, 4, 0}, |
0351b70c ILT |
274 | /* word conditionals add 2 bytes to frag: |
275 | 1 extra opcode byte, 1 extra displacement byte. */ | |
276 | {0, 0, 2, 0}, | |
355afbcd | 277 | |
0351b70c ILT |
278 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
279 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
3c8df4ba | 280 | /* dword jmp adds 3 bytes to frag: |
0351b70c | 281 | 0 extra opcode bytes, 3 extra displacement bytes. */ |
355afbcd | 282 | {0, 0, 3, 0}, |
0351b70c ILT |
283 | /* word jmp adds 1 byte to frag: |
284 | 0 extra opcode bytes, 1 extra displacement byte. */ | |
285 | {0, 0, 1, 0} | |
355afbcd | 286 | |
fecd2382 RP |
287 | }; |
288 | ||
3ea36b53 ILT |
289 | |
290 | void | |
291 | i386_align_code (fragP, count) | |
292 | fragS *fragP; | |
293 | int count; | |
294 | { | |
295 | /* Various efficient no-op patterns for aligning code labels. */ | |
fb50cd4e ILT |
296 | /* Note: Don't try to assemble the instructions in the comments. */ |
297 | /* 0L and 0w are not legal */ | |
298 | static const char f32_1[] = | |
299 | {0x90}; /* nop */ | |
300 | static const char f32_2[] = | |
301 | {0x89,0xf6}; /* movl %esi,%esi */ | |
302 | static const char f32_3[] = | |
303 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
304 | static const char f32_4[] = | |
305 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
306 | static const char f32_5[] = | |
307 | {0x90, /* nop */ | |
308 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
309 | static const char f32_6[] = | |
310 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
311 | static const char f32_7[] = | |
312 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
313 | static const char f32_8[] = | |
314 | {0x90, /* nop */ | |
315 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
316 | static const char f32_9[] = | |
317 | {0x89,0xf6, /* movl %esi,%esi */ | |
318 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
319 | static const char f32_10[] = | |
320 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
321 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
322 | static const char f32_11[] = | |
323 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
324 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
325 | static const char f32_12[] = | |
326 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
327 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
328 | static const char f32_13[] = | |
329 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
330 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
331 | static const char f32_14[] = | |
332 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
333 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
334 | static const char f32_15[] = | |
335 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
336 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
337 | static const char f16_4[] = | |
388fa5c6 | 338 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
fb50cd4e ILT |
339 | static const char f16_5[] = |
340 | {0x90, /* nop */ | |
388fa5c6 | 341 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
fb50cd4e ILT |
342 | static const char f16_6[] = |
343 | {0x89,0xf6, /* mov %si,%si */ | |
344 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
345 | static const char f16_7[] = | |
388fa5c6 | 346 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ |
fb50cd4e ILT |
347 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
348 | static const char f16_8[] = | |
388fa5c6 | 349 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ |
fb50cd4e | 350 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
3ea36b53 ILT |
351 | static const char *const f32_patt[] = { |
352 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
353 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
354 | }; | |
355 | static const char *const f16_patt[] = { | |
356 | f32_1, f32_2, f32_3, f16_4, f16_5, f16_6, f16_7, f16_8, | |
357 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 | |
358 | }; | |
359 | ||
360 | if (count > 0 && count <= 15) | |
361 | { | |
362 | if (flag_16bit_code) | |
363 | { | |
364 | memcpy(fragP->fr_literal + fragP->fr_fix, | |
365 | f16_patt[count - 1], count); | |
366 | if (count > 8) /* adjust jump offset */ | |
367 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
368 | } | |
369 | else | |
370 | memcpy(fragP->fr_literal + fragP->fr_fix, | |
371 | f32_patt[count - 1], count); | |
372 | fragP->fr_var = count; | |
373 | } | |
374 | } | |
375 | ||
49864cfa KR |
376 | static char *output_invalid PARAMS ((int c)); |
377 | static int i386_operand PARAMS ((char *operand_string)); | |
4edc93e9 ILT |
378 | static const reg_entry *parse_register PARAMS ((char *reg_string, |
379 | char **end_op)); | |
49864cfa | 380 | #ifndef I386COFF |
ad660eb1 | 381 | static void s_bss PARAMS ((int)); |
49864cfa | 382 | #endif |
fecd2382 | 383 | |
4498e3d6 | 384 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
f0b37b4a | 385 | |
61c49d66 | 386 | static INLINE unsigned int |
49864cfa | 387 | mode_from_disp_size (t) |
61c49d66 | 388 | unsigned int t; |
49864cfa | 389 | { |
73a8be66 | 390 | return (t & Disp8) ? 1 : (t & (Disp16|Disp32)) ? 2 : 0; |
3c8df4ba | 391 | } |
49864cfa | 392 | |
3c8df4ba | 393 | static INLINE int |
49864cfa KR |
394 | fits_in_signed_byte (num) |
395 | long num; | |
396 | { | |
3c8df4ba | 397 | return (num >= -128) && (num <= 127); |
49864cfa KR |
398 | } /* fits_in_signed_byte() */ |
399 | ||
3c8df4ba | 400 | static INLINE int |
49864cfa KR |
401 | fits_in_unsigned_byte (num) |
402 | long num; | |
403 | { | |
3c8df4ba | 404 | return (num & 0xff) == num; |
49864cfa KR |
405 | } /* fits_in_unsigned_byte() */ |
406 | ||
3c8df4ba | 407 | static INLINE int |
49864cfa KR |
408 | fits_in_unsigned_word (num) |
409 | long num; | |
410 | { | |
3c8df4ba | 411 | return (num & 0xffff) == num; |
49864cfa KR |
412 | } /* fits_in_unsigned_word() */ |
413 | ||
3c8df4ba | 414 | static INLINE int |
49864cfa KR |
415 | fits_in_signed_word (num) |
416 | long num; | |
417 | { | |
3c8df4ba | 418 | return (-32768 <= num) && (num <= 32767); |
49864cfa KR |
419 | } /* fits_in_signed_word() */ |
420 | ||
421 | static int | |
422 | smallest_imm_type (num) | |
423 | long num; | |
424 | { | |
f3d817d8 DM |
425 | #if 0 |
426 | /* This code is disabled because all the Imm1 forms in the opcode table | |
427 | are slower on the i486, and they're the versions with the implicitly | |
428 | specified single-position displacement, which has another syntax if | |
429 | you really want to use that form. If you really prefer to have the | |
430 | one-byte-shorter Imm1 form despite these problems, re-enable this | |
431 | code. */ | |
432 | if (num == 1) | |
433 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32; | |
434 | #endif | |
435 | return (fits_in_signed_byte (num) | |
3c8df4ba KR |
436 | ? (Imm8S | Imm8 | Imm16 | Imm32) |
437 | : fits_in_unsigned_byte (num) | |
438 | ? (Imm8 | Imm16 | Imm32) | |
439 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
440 | ? (Imm16 | Imm32) | |
441 | : (Imm32)); | |
49864cfa | 442 | } /* smallest_imm_type() */ |
fecd2382 | 443 | |
aa56747a ILT |
444 | /* Returns 0 if attempting to add a prefix where one from the same |
445 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
446 | added. */ | |
4498e3d6 | 447 | static int |
aa56747a | 448 | add_prefix (prefix) |
73a8be66 | 449 | unsigned int prefix; |
4498e3d6 | 450 | { |
aa56747a | 451 | int ret = 1; |
4498e3d6 ILT |
452 | int q; |
453 | ||
aa56747a | 454 | switch (prefix) |
4498e3d6 | 455 | { |
73a8be66 ILT |
456 | default: |
457 | abort (); | |
458 | ||
aa56747a ILT |
459 | case CS_PREFIX_OPCODE: |
460 | case DS_PREFIX_OPCODE: | |
461 | case ES_PREFIX_OPCODE: | |
462 | case FS_PREFIX_OPCODE: | |
463 | case GS_PREFIX_OPCODE: | |
464 | case SS_PREFIX_OPCODE: | |
465 | q = SEG_PREFIX; | |
466 | break; | |
4498e3d6 | 467 | |
0351b70c ILT |
468 | case REPNE_PREFIX_OPCODE: |
469 | case REPE_PREFIX_OPCODE: | |
aa56747a ILT |
470 | ret = 2; |
471 | /* fall thru */ | |
472 | case LOCK_PREFIX_OPCODE: | |
473 | q = LOCKREP_PREFIX; | |
474 | break; | |
4498e3d6 | 475 | |
aa56747a ILT |
476 | case FWAIT_OPCODE: |
477 | q = WAIT_PREFIX; | |
478 | break; | |
4498e3d6 | 479 | |
aa56747a ILT |
480 | case ADDR_PREFIX_OPCODE: |
481 | q = ADDR_PREFIX; | |
482 | break; | |
483 | ||
73a8be66 | 484 | case DATA_PREFIX_OPCODE: |
aa56747a | 485 | q = DATA_PREFIX; |
73a8be66 | 486 | break; |
4498e3d6 ILT |
487 | } |
488 | ||
aa56747a | 489 | if (i.prefix[q]) |
4498e3d6 | 490 | { |
aa56747a | 491 | as_bad (_("same type of prefix used twice")); |
4498e3d6 ILT |
492 | return 0; |
493 | } | |
494 | ||
aa56747a ILT |
495 | i.prefixes += 1; |
496 | i.prefix[q] = prefix; | |
497 | return ret; | |
4498e3d6 ILT |
498 | } |
499 | ||
f59fb6ca ILT |
500 | static void |
501 | set_16bit_code_flag (new_16bit_code_flag) | |
c54c7aac KR |
502 | int new_16bit_code_flag; |
503 | { | |
504 | flag_16bit_code = new_16bit_code_flag; | |
505 | } | |
506 | ||
355afbcd KR |
507 | const pseudo_typeS md_pseudo_table[] = |
508 | { | |
49864cfa | 509 | #ifndef I386COFF |
355afbcd | 510 | {"bss", s_bss, 0}, |
49864cfa | 511 | #endif |
02bdbd8b | 512 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
355afbcd | 513 | {"align", s_align_bytes, 0}, |
49864cfa KR |
514 | #else |
515 | {"align", s_align_ptwo, 0}, | |
516 | #endif | |
355afbcd KR |
517 | {"ffloat", float_cons, 'f'}, |
518 | {"dfloat", float_cons, 'd'}, | |
519 | {"tfloat", float_cons, 'x'}, | |
520 | {"value", cons, 2}, | |
49864cfa KR |
521 | {"noopt", s_ignore, 0}, |
522 | {"optim", s_ignore, 0}, | |
c54c7aac KR |
523 | {"code16", set_16bit_code_flag, 1}, |
524 | {"code32", set_16bit_code_flag, 0}, | |
355afbcd | 525 | {0, 0, 0} |
fecd2382 RP |
526 | }; |
527 | ||
528 | /* for interface with expression () */ | |
355afbcd | 529 | extern char *input_line_pointer; |
fecd2382 | 530 | |
668f52e0 | 531 | /* hash table for instruction mnemonic lookup */ |
f3d817d8 | 532 | static struct hash_control *op_hash; |
fecd2382 | 533 | /* hash table for register lookup */ |
f3d817d8 | 534 | static struct hash_control *reg_hash; |
fecd2382 | 535 | \f |
355afbcd KR |
536 | |
537 | void | |
538 | md_begin () | |
fecd2382 | 539 | { |
ad660eb1 | 540 | const char *hash_err; |
355afbcd | 541 | |
355afbcd | 542 | /* initialize op_hash hash table */ |
f3d817d8 | 543 | op_hash = hash_new (); |
355afbcd KR |
544 | |
545 | { | |
546 | register const template *optab; | |
547 | register templates *core_optab; | |
355afbcd KR |
548 | |
549 | optab = i386_optab; /* setup for loop */ | |
355afbcd | 550 | core_optab = (templates *) xmalloc (sizeof (templates)); |
0351b70c | 551 | core_optab->start = optab; |
355afbcd | 552 | |
0351b70c | 553 | while (1) |
355afbcd | 554 | { |
0351b70c ILT |
555 | ++optab; |
556 | if (optab->name == NULL | |
557 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
355afbcd KR |
558 | { |
559 | /* different name --> ship out current template list; | |
49864cfa | 560 | add to hash table; & begin anew */ |
0351b70c ILT |
561 | core_optab->end = optab; |
562 | hash_err = hash_insert (op_hash, | |
563 | (optab - 1)->name, | |
564 | (PTR) core_optab); | |
ad660eb1 | 565 | if (hash_err) |
355afbcd KR |
566 | { |
567 | hash_error: | |
0351b70c ILT |
568 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
569 | (optab - 1)->name, | |
3c8df4ba | 570 | hash_err); |
355afbcd | 571 | } |
0351b70c ILT |
572 | if (optab->name == NULL) |
573 | break; | |
355afbcd | 574 | core_optab = (templates *) xmalloc (sizeof (templates)); |
0351b70c | 575 | core_optab->start = optab; |
355afbcd KR |
576 | } |
577 | } | |
578 | } | |
579 | ||
580 | /* initialize reg_hash hash table */ | |
581 | reg_hash = hash_new (); | |
582 | { | |
583 | register const reg_entry *regtab; | |
584 | ||
0351b70c ILT |
585 | for (regtab = i386_regtab; |
586 | regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); | |
587 | regtab++) | |
355afbcd | 588 | { |
ad660eb1 ILT |
589 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); |
590 | if (hash_err) | |
355afbcd KR |
591 | goto hash_error; |
592 | } | |
593 | } | |
594 | ||
668f52e0 | 595 | /* fill in lexical tables: mnemonic_chars, operand_chars. */ |
355afbcd | 596 | { |
ad660eb1 ILT |
597 | register int c; |
598 | register char *p; | |
355afbcd KR |
599 | |
600 | for (c = 0; c < 256; c++) | |
601 | { | |
0351b70c | 602 | if (isdigit (c)) |
355afbcd | 603 | { |
0351b70c | 604 | digit_chars[c] = c; |
668f52e0 | 605 | mnemonic_chars[c] = c; |
355afbcd | 606 | register_chars[c] = c; |
0351b70c | 607 | operand_chars[c] = c; |
355afbcd | 608 | } |
0351b70c | 609 | else if (islower (c)) |
355afbcd | 610 | { |
668f52e0 | 611 | mnemonic_chars[c] = c; |
0351b70c ILT |
612 | register_chars[c] = c; |
613 | operand_chars[c] = c; | |
355afbcd | 614 | } |
0351b70c | 615 | else if (isupper (c)) |
355afbcd | 616 | { |
668f52e0 ILT |
617 | mnemonic_chars[c] = tolower (c); |
618 | register_chars[c] = mnemonic_chars[c]; | |
0351b70c | 619 | operand_chars[c] = c; |
355afbcd KR |
620 | } |
621 | ||
0351b70c | 622 | if (isalpha (c) || isdigit (c)) |
355afbcd | 623 | identifier_chars[c] = c; |
668f52e0 ILT |
624 | else if (c >= 128) |
625 | { | |
626 | identifier_chars[c] = c; | |
627 | operand_chars[c] = c; | |
628 | } | |
0351b70c | 629 | } |
355afbcd | 630 | |
30355216 | 631 | #ifdef LEX_AT |
0351b70c | 632 | identifier_chars['@'] = '@'; |
30355216 | 633 | #endif |
0351b70c ILT |
634 | register_chars[')'] = ')'; |
635 | register_chars['('] = '('; | |
636 | digit_chars['-'] = '-'; | |
637 | identifier_chars['_'] = '_'; | |
638 | identifier_chars['.'] = '.'; | |
ad660eb1 ILT |
639 | |
640 | for (p = operand_special_chars; *p != '\0'; p++) | |
641 | operand_chars[(unsigned char) *p] = *p; | |
355afbcd | 642 | } |
ad660eb1 | 643 | |
590c50d8 ILT |
644 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
645 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
646 | { | |
647 | record_alignment (text_section, 2); | |
648 | record_alignment (data_section, 2); | |
649 | record_alignment (bss_section, 2); | |
650 | } | |
ad660eb1 | 651 | #endif |
fecd2382 | 652 | } |
3ea36b53 ILT |
653 | |
654 | void | |
655 | i386_print_statistics (file) | |
656 | FILE *file; | |
657 | { | |
658 | hash_print_statistics (file, "i386 opcode", op_hash); | |
659 | hash_print_statistics (file, "i386 register", reg_hash); | |
3ea36b53 | 660 | } |
fecd2382 | 661 | \f |
355afbcd | 662 | |
fecd2382 RP |
663 | #ifdef DEBUG386 |
664 | ||
665 | /* debugging routines for md_assemble */ | |
ad660eb1 ILT |
666 | static void pi PARAMS ((char *, i386_insn *)); |
667 | static void pte PARAMS ((template *)); | |
668 | static void pt PARAMS ((unsigned int)); | |
669 | static void pe PARAMS ((expressionS *)); | |
670 | static void ps PARAMS ((symbolS *)); | |
fecd2382 | 671 | |
355afbcd KR |
672 | static void |
673 | pi (line, x) | |
674 | char *line; | |
675 | i386_insn *x; | |
fecd2382 | 676 | { |
355afbcd KR |
677 | register template *p; |
678 | int i; | |
679 | ||
680 | fprintf (stdout, "%s: template ", line); | |
681 | pte (&x->tm); | |
682 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x", | |
683 | x->rm.mode, x->rm.reg, x->rm.regmem); | |
684 | fprintf (stdout, " base %x index %x scale %x\n", | |
685 | x->bi.base, x->bi.index, x->bi.scale); | |
686 | for (i = 0; i < x->operands; i++) | |
687 | { | |
688 | fprintf (stdout, " #%d: ", i + 1); | |
689 | pt (x->types[i]); | |
690 | fprintf (stdout, "\n"); | |
a52f90a4 ILT |
691 | if (x->types[i] |
692 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX)) | |
355afbcd KR |
693 | fprintf (stdout, "%s\n", x->regs[i]->reg_name); |
694 | if (x->types[i] & Imm) | |
695 | pe (x->imms[i]); | |
73a8be66 | 696 | if (x->types[i] & Disp) |
355afbcd KR |
697 | pe (x->disps[i]); |
698 | } | |
fecd2382 RP |
699 | } |
700 | ||
355afbcd KR |
701 | static void |
702 | pte (t) | |
703 | template *t; | |
fecd2382 | 704 | { |
355afbcd KR |
705 | int i; |
706 | fprintf (stdout, " %d operands ", t->operands); | |
707 | fprintf (stdout, "opcode %x ", | |
708 | t->base_opcode); | |
709 | if (t->extension_opcode != None) | |
710 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
711 | if (t->opcode_modifier & D) | |
712 | fprintf (stdout, "D"); | |
713 | if (t->opcode_modifier & W) | |
714 | fprintf (stdout, "W"); | |
715 | fprintf (stdout, "\n"); | |
716 | for (i = 0; i < t->operands; i++) | |
717 | { | |
718 | fprintf (stdout, " #%d type ", i + 1); | |
719 | pt (t->operand_types[i]); | |
720 | fprintf (stdout, "\n"); | |
721 | } | |
fecd2382 RP |
722 | } |
723 | ||
355afbcd KR |
724 | static void |
725 | pe (e) | |
726 | expressionS *e; | |
fecd2382 | 727 | { |
5ac34ac3 | 728 | fprintf (stdout, " operation %d\n", e->X_op); |
355afbcd KR |
729 | fprintf (stdout, " add_number %d (%x)\n", |
730 | e->X_add_number, e->X_add_number); | |
731 | if (e->X_add_symbol) | |
732 | { | |
733 | fprintf (stdout, " add_symbol "); | |
734 | ps (e->X_add_symbol); | |
735 | fprintf (stdout, "\n"); | |
736 | } | |
5ac34ac3 | 737 | if (e->X_op_symbol) |
355afbcd | 738 | { |
5ac34ac3 ILT |
739 | fprintf (stdout, " op_symbol "); |
740 | ps (e->X_op_symbol); | |
355afbcd KR |
741 | fprintf (stdout, "\n"); |
742 | } | |
fecd2382 RP |
743 | } |
744 | ||
355afbcd KR |
745 | static void |
746 | ps (s) | |
747 | symbolS *s; | |
fecd2382 | 748 | { |
355afbcd KR |
749 | fprintf (stdout, "%s type %s%s", |
750 | S_GET_NAME (s), | |
751 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
752 | segment_name (S_GET_SEGMENT (s))); | |
fecd2382 RP |
753 | } |
754 | ||
355afbcd KR |
755 | struct type_name |
756 | { | |
757 | unsigned int mask; | |
758 | char *tname; | |
759 | } | |
760 | ||
761 | type_names[] = | |
762 | { | |
763 | { Reg8, "r8" }, | |
764 | { Reg16, "r16" }, | |
765 | { Reg32, "r32" }, | |
766 | { Imm8, "i8" }, | |
767 | { Imm8S, "i8s" }, | |
768 | { Imm16, "i16" }, | |
769 | { Imm32, "i32" }, | |
73a8be66 | 770 | { Imm1, "i1" }, |
355afbcd | 771 | { BaseIndex, "BaseIndex" }, |
355afbcd KR |
772 | { Disp8, "d8" }, |
773 | { Disp16, "d16" }, | |
774 | { Disp32, "d32" }, | |
355afbcd KR |
775 | { InOutPortReg, "InOutPortReg" }, |
776 | { ShiftCount, "ShiftCount" }, | |
355afbcd KR |
777 | { Control, "control reg" }, |
778 | { Test, "test reg" }, | |
4498e3d6 | 779 | { Debug, "debug reg" }, |
355afbcd KR |
780 | { FloatReg, "FReg" }, |
781 | { FloatAcc, "FAcc" }, | |
73a8be66 ILT |
782 | { SReg2, "SReg2" }, |
783 | { SReg3, "SReg3" }, | |
784 | { Acc, "Acc" }, | |
355afbcd | 785 | { JumpAbsolute, "Jump Absolute" }, |
454b0ccd | 786 | { RegMMX, "rMMX" }, |
4498e3d6 | 787 | { EsSeg, "es" }, |
355afbcd | 788 | { 0, "" } |
fecd2382 RP |
789 | }; |
790 | ||
355afbcd KR |
791 | static void |
792 | pt (t) | |
793 | unsigned int t; | |
fecd2382 | 794 | { |
355afbcd KR |
795 | register struct type_name *ty; |
796 | ||
797 | if (t == Unknown) | |
798 | { | |
48401fcf | 799 | fprintf (stdout, _("Unknown")); |
355afbcd KR |
800 | } |
801 | else | |
802 | { | |
803 | for (ty = type_names; ty->mask; ty++) | |
804 | if (t & ty->mask) | |
805 | fprintf (stdout, "%s, ", ty->tname); | |
806 | } | |
807 | fflush (stdout); | |
fecd2382 RP |
808 | } |
809 | ||
810 | #endif /* DEBUG386 */ | |
811 | \f | |
a1624e3f RH |
812 | int |
813 | tc_i386_force_relocation (fixp) | |
814 | struct fix *fixp; | |
815 | { | |
816 | #ifdef BFD_ASSEMBLER | |
817 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
818 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
819 | return 1; | |
820 | return 0; | |
821 | #else | |
822 | /* For COFF */ | |
823 | return fixp->fx_r_type==7; | |
824 | #endif | |
825 | } | |
826 | ||
49864cfa KR |
827 | #ifdef BFD_ASSEMBLER |
828 | static bfd_reloc_code_real_type | |
f0b37b4a | 829 | reloc (size, pcrel, other) |
49864cfa KR |
830 | int size; |
831 | int pcrel; | |
f0b37b4a | 832 | bfd_reloc_code_real_type other; |
49864cfa | 833 | { |
f0b37b4a KR |
834 | if (other != NO_RELOC) return other; |
835 | ||
49864cfa | 836 | if (pcrel) |
0351b70c ILT |
837 | { |
838 | switch (size) | |
839 | { | |
840 | case 1: return BFD_RELOC_8_PCREL; | |
841 | case 2: return BFD_RELOC_16_PCREL; | |
842 | case 4: return BFD_RELOC_32_PCREL; | |
843 | } | |
844 | as_bad (_("Can not do %d byte pc-relative relocation"), size); | |
845 | } | |
48401fcf | 846 | else |
0351b70c ILT |
847 | { |
848 | switch (size) | |
849 | { | |
850 | case 1: return BFD_RELOC_8; | |
851 | case 2: return BFD_RELOC_16; | |
852 | case 4: return BFD_RELOC_32; | |
853 | } | |
854 | as_bad (_("Can not do %d byte relocation"), size); | |
855 | } | |
48401fcf | 856 | |
ad660eb1 | 857 | return BFD_RELOC_NONE; |
49864cfa | 858 | } |
49864cfa | 859 | |
f0b37b4a KR |
860 | /* |
861 | * Here we decide which fixups can be adjusted to make them relative to | |
862 | * the beginning of the section instead of the symbol. Basically we need | |
863 | * to make sure that the dynamic relocations are done correctly, so in | |
864 | * some cases we force the original symbol to be used. | |
865 | */ | |
0877841d | 866 | int |
f0b37b4a KR |
867 | tc_i386_fix_adjustable(fixP) |
868 | fixS * fixP; | |
869 | { | |
76fb6d2f | 870 | #ifdef OBJ_ELF |
c54c7aac | 871 | /* Prevent all adjustments to global symbols. */ |
0877841d | 872 | if (S_IS_EXTERN (fixP->fx_addsy)) |
c54c7aac | 873 | return 0; |
0b476c53 ILT |
874 | if (S_IS_WEAK (fixP->fx_addsy)) |
875 | return 0; | |
a1624e3f | 876 | #endif |
c54c7aac | 877 | /* adjust_reloc_syms doesn't know about the GOT */ |
0877841d ILT |
878 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
879 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
a1624e3f RH |
880 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
881 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
882 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c54c7aac | 883 | return 0; |
c54c7aac | 884 | return 1; |
f0b37b4a | 885 | } |
454b0ccd ILT |
886 | #else |
887 | #define reloc(SIZE,PCREL,OTHER) 0 | |
0351b70c | 888 | #define BFD_RELOC_16 0 |
454b0ccd | 889 | #define BFD_RELOC_32 0 |
0351b70c | 890 | #define BFD_RELOC_16_PCREL 0 |
454b0ccd ILT |
891 | #define BFD_RELOC_32_PCREL 0 |
892 | #define BFD_RELOC_386_PLT32 0 | |
893 | #define BFD_RELOC_386_GOT32 0 | |
894 | #define BFD_RELOC_386_GOTOFF 0 | |
895 | #endif | |
f0b37b4a | 896 | |
49864cfa | 897 | /* This is the guts of the machine-dependent assembler. LINE points to a |
3c8df4ba | 898 | machine dependent instruction. This function is supposed to emit |
49864cfa | 899 | the frags/bytes it assembles to. */ |
f0b37b4a | 900 | |
355afbcd KR |
901 | void |
902 | md_assemble (line) | |
903 | char *line; | |
fecd2382 | 904 | { |
227b6b55 ILT |
905 | /* Points to template once we've found it. */ |
906 | const template *t; | |
355afbcd | 907 | |
ad660eb1 ILT |
908 | /* Count the size of the instruction generated. */ |
909 | int insn_size = 0; | |
910 | ||
f0b37b4a KR |
911 | int j; |
912 | ||
355afbcd KR |
913 | /* Initialize globals. */ |
914 | memset (&i, '\0', sizeof (i)); | |
f0b37b4a KR |
915 | for (j = 0; j < MAX_OPERANDS; j++) |
916 | i.disp_reloc[j] = NO_RELOC; | |
355afbcd KR |
917 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
918 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
919 | save_stack_p = save_stack; /* reset stack pointer */ | |
920 | ||
668f52e0 | 921 | /* First parse an instruction mnemonic & call i386_operand for the operands. |
49864cfa | 922 | We assume that the scrubber has arranged it so that line[0] is the valid |
668f52e0 | 923 | start of a (possibly prefixed) mnemonic. */ |
355afbcd | 924 | { |
668f52e0 | 925 | char mnemonic[MAX_MNEM_SIZE]; |
f3d817d8 | 926 | char *l = line; |
0351b70c | 927 | char *token_start = l; |
668f52e0 | 928 | char *mnem_p; |
355afbcd | 929 | |
4498e3d6 ILT |
930 | /* Non-zero if we found a prefix only acceptable with string insns. */ |
931 | const char *expecting_string_instruction = NULL; | |
355afbcd | 932 | |
0351b70c | 933 | while (1) |
355afbcd | 934 | { |
668f52e0 ILT |
935 | mnem_p = mnemonic; |
936 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
355afbcd | 937 | { |
668f52e0 ILT |
938 | mnem_p++; |
939 | if (mnem_p >= mnemonic + sizeof (mnemonic)) | |
0351b70c ILT |
940 | { |
941 | as_bad (_("no such 386 instruction: `%s'"), token_start); | |
942 | return; | |
943 | } | |
944 | l++; | |
355afbcd | 945 | } |
0351b70c ILT |
946 | if (!is_space_char (*l) |
947 | && *l != END_OF_INSN | |
948 | && *l != PREFIX_SEPARATOR) | |
355afbcd | 949 | { |
668f52e0 | 950 | as_bad (_("invalid character %s in mnemonic"), |
0351b70c ILT |
951 | output_invalid (*l)); |
952 | return; | |
355afbcd | 953 | } |
0351b70c | 954 | if (token_start == l) |
f3d817d8 | 955 | { |
0351b70c ILT |
956 | if (*l == PREFIX_SEPARATOR) |
957 | as_bad (_("expecting prefix; got nothing")); | |
958 | else | |
668f52e0 | 959 | as_bad (_("expecting mnemonic; got nothing")); |
0351b70c ILT |
960 | return; |
961 | } | |
355afbcd | 962 | |
0351b70c | 963 | /* Look up instruction (or prefix) via hash table. */ |
668f52e0 | 964 | current_templates = hash_find (op_hash, mnemonic); |
0351b70c ILT |
965 | |
966 | if (*l != END_OF_INSN | |
61c49d66 | 967 | && (! is_space_char (*l) || l[1] != END_OF_INSN) |
0351b70c | 968 | && current_templates |
284f02bb | 969 | && (current_templates->start->opcode_modifier & IsPrefix)) |
0351b70c | 970 | { |
284f02bb ILT |
971 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
972 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
973 | if ((current_templates->start->opcode_modifier & (Size16 | Size32)) | |
974 | && (((current_templates->start->opcode_modifier & Size32) != 0) | |
975 | ^ flag_16bit_code)) | |
976 | { | |
977 | as_bad (_("redundant %s prefix"), | |
978 | current_templates->start->name); | |
979 | return; | |
980 | } | |
0351b70c ILT |
981 | /* Add prefix, checking for repeated prefixes. */ |
982 | switch (add_prefix (current_templates->start->base_opcode)) | |
4498e3d6 | 983 | { |
73a8be66 ILT |
984 | case 0: |
985 | return; | |
aa56747a | 986 | case 2: |
0351b70c ILT |
987 | expecting_string_instruction = |
988 | current_templates->start->name; | |
aa56747a | 989 | break; |
355afbcd | 990 | } |
4498e3d6 | 991 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ |
355afbcd KR |
992 | token_start = ++l; |
993 | } | |
0351b70c ILT |
994 | else |
995 | break; | |
355afbcd KR |
996 | } |
997 | ||
355afbcd KR |
998 | if (!current_templates) |
999 | { | |
0351b70c | 1000 | /* See if we can get a match by trimming off a suffix. */ |
668f52e0 | 1001 | switch (mnem_p[-1]) |
355afbcd | 1002 | { |
668f52e0 ILT |
1003 | case DWORD_MNEM_SUFFIX: |
1004 | case WORD_MNEM_SUFFIX: | |
1005 | case BYTE_MNEM_SUFFIX: | |
1006 | case SHORT_MNEM_SUFFIX: | |
1007 | #if LONG_MNEM_SUFFIX != DWORD_MNEM_SUFFIX | |
1008 | case LONG_MNEM_SUFFIX: | |
73a8be66 | 1009 | #endif |
668f52e0 ILT |
1010 | i.suffix = mnem_p[-1]; |
1011 | mnem_p[-1] = '\0'; | |
1012 | current_templates = hash_find (op_hash, mnemonic); | |
355afbcd KR |
1013 | } |
1014 | if (!current_templates) | |
1015 | { | |
48401fcf | 1016 | as_bad (_("no such 386 instruction: `%s'"), token_start); |
355afbcd KR |
1017 | return; |
1018 | } | |
1019 | } | |
355afbcd KR |
1020 | |
1021 | /* check for rep/repne without a string instruction */ | |
73a8be66 ILT |
1022 | if (expecting_string_instruction |
1023 | && !(current_templates->start->opcode_modifier & IsString)) | |
355afbcd | 1024 | { |
48401fcf | 1025 | as_bad (_("expecting string instruction after `%s'"), |
4498e3d6 | 1026 | expecting_string_instruction); |
355afbcd KR |
1027 | return; |
1028 | } | |
1029 | ||
1030 | /* There may be operands to parse. */ | |
4498e3d6 | 1031 | if (*l != END_OF_INSN) |
355afbcd KR |
1032 | { |
1033 | /* parse operands */ | |
0351b70c ILT |
1034 | |
1035 | /* 1 if operand is pending after ','. */ | |
1036 | unsigned int expecting_operand = 0; | |
1037 | ||
1038 | /* Non-zero if operand parens not balanced. */ | |
1039 | unsigned int paren_not_balanced; | |
1040 | ||
355afbcd KR |
1041 | do |
1042 | { | |
1043 | /* skip optional white space before operand */ | |
4edc93e9 ILT |
1044 | if (is_space_char (*l)) |
1045 | ++l; | |
1046 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
355afbcd | 1047 | { |
4edc93e9 ILT |
1048 | as_bad (_("invalid character %s before operand %d"), |
1049 | output_invalid (*l), | |
1050 | i.operands + 1); | |
1051 | return; | |
355afbcd KR |
1052 | } |
1053 | token_start = l; /* after white space */ | |
0b476c53 ILT |
1054 | paren_not_balanced = 0; |
1055 | while (paren_not_balanced || *l != ',') | |
355afbcd KR |
1056 | { |
1057 | if (*l == END_OF_INSN) | |
1058 | { | |
0b476c53 | 1059 | if (paren_not_balanced) |
355afbcd | 1060 | { |
48401fcf | 1061 | as_bad (_("unbalanced parenthesis in operand %d."), |
aa56747a | 1062 | i.operands + 1); |
355afbcd KR |
1063 | return; |
1064 | } | |
1065 | else | |
1066 | break; /* we are done */ | |
1067 | } | |
ad660eb1 | 1068 | else if (!is_operand_char (*l) && !is_space_char (*l)) |
355afbcd | 1069 | { |
48401fcf | 1070 | as_bad (_("invalid character %s in operand %d"), |
aa56747a ILT |
1071 | output_invalid (*l), |
1072 | i.operands + 1); | |
355afbcd KR |
1073 | return; |
1074 | } | |
1075 | if (*l == '(') | |
0b476c53 | 1076 | ++paren_not_balanced; |
355afbcd | 1077 | if (*l == ')') |
0b476c53 | 1078 | --paren_not_balanced; |
355afbcd KR |
1079 | l++; |
1080 | } | |
1081 | if (l != token_start) | |
1082 | { /* yes, we've read in another operand */ | |
1083 | unsigned int operand_ok; | |
1084 | this_operand = i.operands++; | |
1085 | if (i.operands > MAX_OPERANDS) | |
1086 | { | |
48401fcf | 1087 | as_bad (_("spurious operands; (%d operands/instruction max)"), |
355afbcd KR |
1088 | MAX_OPERANDS); |
1089 | return; | |
1090 | } | |
1091 | /* now parse operand adding info to 'i' as we go along */ | |
1092 | END_STRING_AND_SAVE (l); | |
1093 | operand_ok = i386_operand (token_start); | |
1094 | RESTORE_END_STRING (l); /* restore old contents */ | |
1095 | if (!operand_ok) | |
1096 | return; | |
1097 | } | |
1098 | else | |
1099 | { | |
1100 | if (expecting_operand) | |
1101 | { | |
1102 | expecting_operand_after_comma: | |
48401fcf | 1103 | as_bad (_("expecting operand after ','; got nothing")); |
355afbcd KR |
1104 | return; |
1105 | } | |
1106 | if (*l == ',') | |
1107 | { | |
48401fcf | 1108 | as_bad (_("expecting operand before ','; got nothing")); |
355afbcd KR |
1109 | return; |
1110 | } | |
1111 | } | |
1112 | ||
1113 | /* now *l must be either ',' or END_OF_INSN */ | |
1114 | if (*l == ',') | |
1115 | { | |
1116 | if (*++l == END_OF_INSN) | |
1117 | { /* just skip it, if it's \n complain */ | |
1118 | goto expecting_operand_after_comma; | |
1119 | } | |
1120 | expecting_operand = 1; | |
1121 | } | |
1122 | } | |
1123 | while (*l != END_OF_INSN); /* until we get end of insn */ | |
1124 | } | |
1125 | } | |
1126 | ||
668f52e0 | 1127 | /* Now we've parsed the mnemonic into a set of templates, and have the |
c5dd66a1 KR |
1128 | operands at hand. |
1129 | ||
1130 | Next, we find a template that matches the given insn, | |
1131 | making sure the overlap of the given operands types is consistent | |
1132 | with the template operand types. */ | |
355afbcd | 1133 | |
73a8be66 ILT |
1134 | #define MATCH(overlap, given, template) \ |
1135 | ((overlap) \ | |
0351b70c ILT |
1136 | && ((given) & BaseIndex) == ((overlap) & BaseIndex) \ |
1137 | && ((given) & JumpAbsolute) == ((template) & JumpAbsolute)) | |
73a8be66 ILT |
1138 | |
1139 | /* If given types r0 and r1 are registers they must be of the same type | |
1140 | unless the expected operand type register overlap is null. | |
1141 | Note that Acc in a template matches every size of reg. */ | |
1142 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ | |
1143 | ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \ | |
1144 | ((g0) & Reg) == ((g1) & Reg) || \ | |
1145 | ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) | |
1146 | ||
355afbcd KR |
1147 | { |
1148 | register unsigned int overlap0, overlap1; | |
1149 | expressionS *exp; | |
1150 | unsigned int overlap2; | |
1151 | unsigned int found_reverse_match; | |
73a8be66 ILT |
1152 | int suffix_check; |
1153 | ||
1154 | overlap0 = 0; | |
1155 | overlap1 = 0; | |
1156 | overlap2 = 0; | |
1157 | found_reverse_match = 0; | |
668f52e0 | 1158 | suffix_check = (i.suffix == BYTE_MNEM_SUFFIX |
73a8be66 | 1159 | ? No_bSuf |
668f52e0 | 1160 | : (i.suffix == WORD_MNEM_SUFFIX |
73a8be66 | 1161 | ? No_wSuf |
668f52e0 | 1162 | : (i.suffix == SHORT_MNEM_SUFFIX |
73a8be66 | 1163 | ? No_sSuf |
668f52e0 | 1164 | : (i.suffix == LONG_MNEM_SUFFIX ? No_lSuf : 0)))); |
355afbcd | 1165 | |
355afbcd KR |
1166 | for (t = current_templates->start; |
1167 | t < current_templates->end; | |
1168 | t++) | |
1169 | { | |
73a8be66 ILT |
1170 | /* Must have right number of operands, and must not have |
1171 | disallowed suffix. */ | |
1172 | if (i.operands != t->operands || (t->opcode_modifier & suffix_check)) | |
355afbcd KR |
1173 | continue; |
1174 | else if (!t->operands) | |
1175 | break; /* 0 operands always matches */ | |
1176 | ||
1177 | overlap0 = i.types[0] & t->operand_types[0]; | |
1178 | switch (t->operands) | |
1179 | { | |
1180 | case 1: | |
73a8be66 | 1181 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])) |
355afbcd KR |
1182 | continue; |
1183 | break; | |
1184 | case 2: | |
1185 | case 3: | |
1186 | overlap1 = i.types[1] & t->operand_types[1]; | |
73a8be66 ILT |
1187 | if (!MATCH (overlap0, i.types[0], t->operand_types[0]) |
1188 | || !MATCH (overlap1, i.types[1], t->operand_types[1]) | |
1189 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1190 | t->operand_types[0], | |
1191 | overlap1, i.types[1], | |
1192 | t->operand_types[1])) | |
542e1629 | 1193 | { |
355afbcd KR |
1194 | |
1195 | /* check if other direction is valid ... */ | |
73a8be66 | 1196 | if ((t->opcode_modifier & (D|FloatD)) == 0) |
355afbcd KR |
1197 | continue; |
1198 | ||
1199 | /* try reversing direction of operands */ | |
1200 | overlap0 = i.types[0] & t->operand_types[1]; | |
1201 | overlap1 = i.types[1] & t->operand_types[0]; | |
73a8be66 ILT |
1202 | if (!MATCH (overlap0, i.types[0], t->operand_types[1]) |
1203 | || !MATCH (overlap1, i.types[1], t->operand_types[0]) | |
1204 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1205 | t->operand_types[1], | |
1206 | overlap1, i.types[1], | |
1207 | t->operand_types[0])) | |
355afbcd KR |
1208 | { |
1209 | /* does not match either direction */ | |
1210 | continue; | |
1211 | } | |
73a8be66 ILT |
1212 | /* found_reverse_match holds which of D or FloatDR |
1213 | we've found. */ | |
1214 | found_reverse_match = t->opcode_modifier & (D|FloatDR); | |
1215 | break; | |
1216 | } | |
1217 | /* found a forward 2 operand match here */ | |
355afbcd KR |
1218 | if (t->operands == 3) |
1219 | { | |
73a8be66 ILT |
1220 | /* Here we make use of the fact that there are no |
1221 | reverse match 3 operand instructions, and all 3 | |
1222 | operand instructions only need to be checked for | |
1223 | register consistency between operands 2 and 3. */ | |
355afbcd | 1224 | overlap2 = i.types[2] & t->operand_types[2]; |
73a8be66 ILT |
1225 | if (!MATCH (overlap2, i.types[2], t->operand_types[2]) |
1226 | || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], | |
1227 | t->operand_types[1], | |
1228 | overlap2, i.types[2], | |
1229 | t->operand_types[2])) | |
355afbcd KR |
1230 | continue; |
1231 | } | |
1232 | /* found either forward/reverse 2 or 3 operand match here: | |
c5dd66a1 | 1233 | slip through to break */ |
355afbcd KR |
1234 | } |
1235 | break; /* we've found a match; break out of loop */ | |
1236 | } /* for (t = ... */ | |
1237 | if (t == current_templates->end) | |
1238 | { /* we found no match */ | |
48401fcf | 1239 | as_bad (_("suffix or operands invalid for `%s'"), |
4498e3d6 | 1240 | current_templates->start->name); |
355afbcd KR |
1241 | return; |
1242 | } | |
1243 | ||
61c49d66 ILT |
1244 | if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) == (IsPrefix|IgnoreSize)) |
1245 | { | |
1246 | /* Warn them that a data or address size prefix doesn't affect | |
1247 | assembly of the next line of code. */ | |
1248 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
1249 | } | |
1250 | ||
4498e3d6 | 1251 | /* Copy the template we found. */ |
f3d817d8 | 1252 | i.tm = *t; |
227b6b55 ILT |
1253 | if (found_reverse_match) |
1254 | { | |
1255 | i.tm.operand_types[0] = t->operand_types[1]; | |
1256 | i.tm.operand_types[1] = t->operand_types[0]; | |
1257 | } | |
355afbcd | 1258 | |
73a8be66 ILT |
1259 | if (i.tm.opcode_modifier & FWait) |
1260 | if (! add_prefix (FWAIT_OPCODE)) | |
1261 | return; | |
1262 | ||
4498e3d6 ILT |
1263 | /* Check string instruction segment overrides */ |
1264 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) | |
1265 | { | |
73a8be66 | 1266 | int mem_op = (i.types[0] & AnyMem) ? 0 : 1; |
8081c2be | 1267 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) |
4498e3d6 | 1268 | { |
73a8be66 | 1269 | if (i.seg[0] != NULL && i.seg[0] != &es) |
4498e3d6 | 1270 | { |
aa56747a ILT |
1271 | as_bad (_("`%s' operand %d must use `%%es' segment"), |
1272 | i.tm.name, | |
1273 | mem_op + 1); | |
4498e3d6 ILT |
1274 | return; |
1275 | } | |
1276 | /* There's only ever one segment override allowed per instruction. | |
1277 | This instruction possibly has a legal segment override on the | |
1278 | second operand, so copy the segment to where non-string | |
1279 | instructions store it, allowing common code. */ | |
1280 | i.seg[0] = i.seg[1]; | |
1281 | } | |
8081c2be | 1282 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) |
4498e3d6 | 1283 | { |
73a8be66 | 1284 | if (i.seg[1] != NULL && i.seg[1] != &es) |
4498e3d6 | 1285 | { |
aa56747a ILT |
1286 | as_bad (_("`%s' operand %d must use `%%es' segment"), |
1287 | i.tm.name, | |
1288 | mem_op + 2); | |
4498e3d6 ILT |
1289 | return; |
1290 | } | |
1291 | } | |
1292 | } | |
1293 | ||
668f52e0 ILT |
1294 | /* If matched instruction specifies an explicit instruction mnemonic |
1295 | suffix, use it. */ | |
284f02bb | 1296 | if (i.tm.opcode_modifier & (Size16 | Size32)) |
c54c7aac | 1297 | { |
284f02bb | 1298 | if (i.tm.opcode_modifier & Size16) |
668f52e0 | 1299 | i.suffix = WORD_MNEM_SUFFIX; |
c54c7aac | 1300 | else |
668f52e0 | 1301 | i.suffix = DWORD_MNEM_SUFFIX; |
c54c7aac | 1302 | } |
73a8be66 | 1303 | else if (i.reg_operands) |
355afbcd | 1304 | { |
668f52e0 ILT |
1305 | /* If there's no instruction mnemonic suffix we try to invent one |
1306 | based on register operands. */ | |
73a8be66 | 1307 | if (!i.suffix) |
3ea36b53 | 1308 | { |
73a8be66 ILT |
1309 | /* We take i.suffix from the last register operand specified, |
1310 | Destination register type is more significant than source | |
1311 | register type. */ | |
1312 | int op; | |
1313 | for (op = i.operands; --op >= 0; ) | |
1314 | if (i.types[op] & Reg) | |
1315 | { | |
668f52e0 ILT |
1316 | i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : |
1317 | (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : | |
1318 | DWORD_MNEM_SUFFIX); | |
73a8be66 ILT |
1319 | break; |
1320 | } | |
1321 | } | |
668f52e0 | 1322 | else if (i.suffix == BYTE_MNEM_SUFFIX) |
73a8be66 ILT |
1323 | { |
1324 | int op; | |
1325 | for (op = i.operands; --op >= 0; ) | |
1326 | { | |
1327 | /* If this is an eight bit register, it's OK. If it's | |
1328 | the 16 or 32 bit version of an eight bit register, | |
1329 | we will just use the low portion, and that's OK too. */ | |
1330 | if (i.types[op] & Reg8) | |
1331 | continue; | |
1332 | if ((i.types[op] & WordReg) && i.regs[op]->reg_num < 4 | |
1333 | #if 0 | |
1334 | /* Check that the template allows eight bit regs | |
1335 | This kills insns such as `orb $1,%edx', which | |
1336 | maybe should be allowed. */ | |
1337 | && (i.tm.operand_types[op] & (Reg8|InOutPortReg)) | |
1338 | #endif | |
1339 | ) | |
1340 | { | |
1341 | #if REGISTER_WARNINGS | |
1342 | if ((i.tm.operand_types[op] & InOutPortReg) == 0) | |
1343 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
1344 | (i.regs[op] - (i.types[op] & Reg16 ? 8 : 16))->reg_name, | |
1345 | i.regs[op]->reg_name, | |
1346 | i.suffix); | |
1347 | #endif | |
1348 | continue; | |
1349 | } | |
1350 | /* Any other register is bad */ | |
1351 | if (i.types[op] & (Reg | RegMMX | Control | Debug | Test | |
1352 | | FloatReg | FloatAcc | SReg2 | SReg3)) | |
1353 | { | |
1354 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
1355 | i.regs[op]->reg_name, | |
1356 | i.tm.name, | |
1357 | i.suffix); | |
1358 | return; | |
1359 | } | |
1360 | } | |
3ea36b53 | 1361 | } |
668f52e0 | 1362 | else if (i.suffix == DWORD_MNEM_SUFFIX) |
73a8be66 ILT |
1363 | { |
1364 | int op; | |
1365 | for (op = i.operands; --op >= 0; ) | |
1366 | /* Reject eight bit registers, except where the template | |
1367 | requires them. (eg. movzb) */ | |
1368 | if ((i.types[op] & Reg8) != 0 | |
1369 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
1370 | { | |
1371 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
1372 | i.regs[op]->reg_name, | |
1373 | i.tm.name, | |
1374 | i.suffix); | |
1375 | return; | |
1376 | } | |
1377 | #if REGISTER_WARNINGS | |
1378 | /* Warn if the e prefix on a general reg is missing. */ | |
1379 | else if ((i.types[op] & Reg16) != 0 | |
1380 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) | |
1381 | { | |
1382 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
1383 | (i.regs[op] + 8)->reg_name, | |
1384 | i.regs[op]->reg_name, | |
1385 | i.suffix); | |
1386 | } | |
1387 | #endif | |
1388 | } | |
668f52e0 | 1389 | else if (i.suffix == WORD_MNEM_SUFFIX) |
73a8be66 ILT |
1390 | { |
1391 | int op; | |
1392 | for (op = i.operands; --op >= 0; ) | |
1393 | /* Reject eight bit registers, except where the template | |
1394 | requires them. (eg. movzb) */ | |
1395 | if ((i.types[op] & Reg8) != 0 | |
1396 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
1397 | { | |
1398 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
1399 | i.regs[op]->reg_name, | |
1400 | i.tm.name, | |
1401 | i.suffix); | |
1402 | return; | |
1403 | } | |
1404 | #if REGISTER_WARNINGS | |
1405 | /* Warn if the e prefix on a general reg is present. */ | |
1406 | else if ((i.types[op] & Reg32) != 0 | |
1407 | && (i.tm.operand_types[op] & (Reg16|Acc)) != 0) | |
1408 | { | |
1409 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
1410 | (i.regs[op] - 8)->reg_name, | |
1411 | i.regs[op]->reg_name, | |
1412 | i.suffix); | |
1413 | } | |
1414 | #endif | |
1415 | } | |
1416 | else | |
1417 | abort(); | |
3ea36b53 | 1418 | } |
355afbcd KR |
1419 | |
1420 | /* Make still unresolved immediate matches conform to size of immediate | |
5819d632 | 1421 | given in i.suffix. Note: overlap2 cannot be an immediate! */ |
355afbcd KR |
1422 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32)) |
1423 | && overlap0 != Imm8 && overlap0 != Imm8S | |
1424 | && overlap0 != Imm16 && overlap0 != Imm32) | |
1425 | { | |
0351b70c ILT |
1426 | if (i.suffix) |
1427 | { | |
668f52e0 ILT |
1428 | overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
1429 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); | |
0351b70c ILT |
1430 | } |
1431 | else if (overlap0 == (Imm16 | Imm32)) | |
1432 | { | |
1433 | overlap0 = | |
1434 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; | |
1435 | } | |
1436 | else | |
355afbcd | 1437 | { |
668f52e0 | 1438 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); |
355afbcd KR |
1439 | return; |
1440 | } | |
355afbcd KR |
1441 | } |
1442 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32)) | |
1443 | && overlap1 != Imm8 && overlap1 != Imm8S | |
1444 | && overlap1 != Imm16 && overlap1 != Imm32) | |
1445 | { | |
0351b70c ILT |
1446 | if (i.suffix) |
1447 | { | |
668f52e0 ILT |
1448 | overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
1449 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); | |
0351b70c ILT |
1450 | } |
1451 | else if (overlap1 == (Imm16 | Imm32)) | |
1452 | { | |
1453 | overlap1 = | |
1454 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; | |
1455 | } | |
1456 | else | |
355afbcd | 1457 | { |
668f52e0 | 1458 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); |
355afbcd KR |
1459 | return; |
1460 | } | |
355afbcd | 1461 | } |
5819d632 | 1462 | assert ((overlap2 & Imm) == 0); |
355afbcd KR |
1463 | |
1464 | i.types[0] = overlap0; | |
355afbcd KR |
1465 | if (overlap0 & ImplicitRegister) |
1466 | i.reg_operands--; | |
0351b70c ILT |
1467 | if (overlap0 & Imm1) |
1468 | i.imm_operands = 0; /* kludge for shift insns */ | |
1469 | ||
1470 | i.types[1] = overlap1; | |
355afbcd KR |
1471 | if (overlap1 & ImplicitRegister) |
1472 | i.reg_operands--; | |
0351b70c ILT |
1473 | |
1474 | i.types[2] = overlap2; | |
355afbcd KR |
1475 | if (overlap2 & ImplicitRegister) |
1476 | i.reg_operands--; | |
355afbcd | 1477 | |
355afbcd | 1478 | /* Finalize opcode. First, we change the opcode based on the operand |
668f52e0 | 1479 | size given by i.suffix: We need not change things for byte insns. */ |
355afbcd | 1480 | |
227b6b55 | 1481 | if (!i.suffix && (i.tm.opcode_modifier & W)) |
355afbcd | 1482 | { |
668f52e0 | 1483 | as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); |
355afbcd KR |
1484 | return; |
1485 | } | |
1486 | ||
668f52e0 | 1487 | if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) |
355afbcd | 1488 | { |
668f52e0 | 1489 | /* It's not a byte, select word/dword operation. */ |
227b6b55 | 1490 | if (i.tm.opcode_modifier & W) |
73a8be66 ILT |
1491 | { |
1492 | if (i.tm.opcode_modifier & ShortForm) | |
1493 | i.tm.base_opcode |= 8; | |
1494 | else | |
1495 | i.tm.base_opcode |= 1; | |
1496 | } | |
8c927202 | 1497 | /* Now select between word & dword operations via the operand |
73a8be66 ILT |
1498 | size prefix, except for instructions that will ignore this |
1499 | prefix anyway. */ | |
668f52e0 ILT |
1500 | if ((i.suffix == DWORD_MNEM_SUFFIX |
1501 | || i.suffix == LONG_MNEM_SUFFIX) == flag_16bit_code | |
284f02bb | 1502 | && !(i.tm.opcode_modifier & IgnoreSize)) |
355afbcd | 1503 | { |
73a8be66 | 1504 | unsigned int prefix = DATA_PREFIX_OPCODE; |
aa56747a ILT |
1505 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ |
1506 | prefix = ADDR_PREFIX_OPCODE; | |
1507 | ||
1508 | if (! add_prefix (prefix)) | |
4498e3d6 | 1509 | return; |
355afbcd | 1510 | } |
73a8be66 | 1511 | /* Size floating point instruction. */ |
668f52e0 | 1512 | if (i.suffix == LONG_MNEM_SUFFIX) |
73a8be66 ILT |
1513 | { |
1514 | if (i.tm.opcode_modifier & FloatMF) | |
1515 | i.tm.base_opcode ^= 4; | |
1516 | } | |
355afbcd KR |
1517 | } |
1518 | ||
f5003e7d ILT |
1519 | if (i.tm.base_opcode == AMD_3DNOW_OPCODE) |
1520 | { | |
1521 | /* These AMD specific instructions have an opcode suffix which | |
1522 | is coded in the same place as an 8-bit immediate field | |
1523 | would be. Here we fake an 8-bit immediate operand from the | |
668f52e0 | 1524 | opcode suffix stored in tm.extension_opcode. */ |
f5003e7d ILT |
1525 | |
1526 | expressionS *exp; | |
1527 | ||
1528 | assert(i.imm_operands == 0 && i.operands <= 2); | |
1529 | ||
1530 | exp = &im_expressions[i.imm_operands++]; | |
1531 | i.imms[i.operands] = exp; | |
1532 | i.types[i.operands++] = Imm8; | |
1533 | exp->X_op = O_constant; | |
1534 | exp->X_add_number = i.tm.extension_opcode; | |
1535 | i.tm.extension_opcode = None; | |
1536 | } | |
1537 | ||
355afbcd KR |
1538 | /* For insns with operands there are more diddles to do to the opcode. */ |
1539 | if (i.operands) | |
1540 | { | |
c54c7aac KR |
1541 | /* Default segment register this instruction will use |
1542 | for memory accesses. 0 means unknown. | |
1543 | This is only for optimizing out unnecessary segment overrides. */ | |
1544 | const seg_entry *default_seg = 0; | |
1545 | ||
aa56747a ILT |
1546 | /* If we found a reverse match we must alter the opcode |
1547 | direction bit. found_reverse_match holds bits to change | |
1548 | (different for int & float insns). */ | |
355afbcd | 1549 | |
4498e3d6 | 1550 | i.tm.base_opcode ^= found_reverse_match; |
355afbcd | 1551 | |
c5dd66a1 | 1552 | /* The imul $imm, %reg instruction is converted into |
4498e3d6 ILT |
1553 | imul $imm, %reg, %reg, and the clr %reg instruction |
1554 | is converted into xor %reg, %reg. */ | |
1555 | if (i.tm.opcode_modifier & regKludge) | |
2fb44892 | 1556 | { |
4498e3d6 ILT |
1557 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; |
1558 | /* Pretend we saw the extra register operand. */ | |
1559 | i.regs[first_reg_op+1] = i.regs[first_reg_op]; | |
2fb44892 ILT |
1560 | i.reg_operands = 2; |
1561 | } | |
1562 | ||
227b6b55 | 1563 | if (i.tm.opcode_modifier & ShortForm) |
355afbcd KR |
1564 | { |
1565 | /* The register or float register operand is in operand 0 or 1. */ | |
ad660eb1 | 1566 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; |
355afbcd | 1567 | /* Register goes in low 3 bits of opcode. */ |
227b6b55 | 1568 | i.tm.base_opcode |= i.regs[op]->reg_num; |
73a8be66 ILT |
1569 | if ((i.tm.opcode_modifier & Ugh) != 0) |
1570 | { | |
1571 | /* Warn about some common errors, but press on regardless. | |
1572 | The first case can be generated by gcc (<= 2.8.1). */ | |
1573 | if (i.operands == 2) | |
1574 | { | |
1575 | /* reversed arguments on faddp, fsubp, etc. */ | |
1576 | as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, | |
1577 | i.regs[1]->reg_name, | |
1578 | i.regs[0]->reg_name); | |
1579 | } | |
1580 | else | |
1581 | { | |
1582 | /* extraneous `l' suffix on fp insn */ | |
1583 | as_warn (_("translating to `%s %%%s'"), i.tm.name, | |
1584 | i.regs[0]->reg_name); | |
1585 | } | |
1586 | } | |
355afbcd | 1587 | } |
227b6b55 | 1588 | else if (i.tm.opcode_modifier & Modrm) |
355afbcd | 1589 | { |
227b6b55 ILT |
1590 | /* The opcode is completed (modulo i.tm.extension_opcode which |
1591 | must be put into the modrm byte). | |
1592 | Now, we make the modrm & index base bytes based on all the | |
1593 | info we've collected. */ | |
355afbcd KR |
1594 | |
1595 | /* i.reg_operands MUST be the number of real register operands; | |
c5dd66a1 | 1596 | implicit registers do not count. */ |
355afbcd KR |
1597 | if (i.reg_operands == 2) |
1598 | { | |
1599 | unsigned int source, dest; | |
454b0ccd ILT |
1600 | source = ((i.types[0] |
1601 | & (Reg | |
1602 | | SReg2 | |
1603 | | SReg3 | |
1604 | | Control | |
1605 | | Debug | |
1606 | | Test | |
1607 | | RegMMX)) | |
1608 | ? 0 : 1); | |
355afbcd | 1609 | dest = source + 1; |
4498e3d6 ILT |
1610 | |
1611 | /* Certain instructions expect the destination to be | |
1612 | in the i.rm.reg field. This is by far the | |
1613 | exceptional case. For these instructions, if the | |
1614 | source operand is a register, we must reverse the | |
1615 | i.rm.reg and i.rm.regmem fields. We accomplish | |
1616 | this by pretending that the two register operands | |
1617 | were given in the reverse order. */ | |
1618 | if (i.tm.opcode_modifier & ReverseRegRegmem) | |
1619 | { | |
73a8be66 | 1620 | const reg_entry *tmp = i.regs[source]; |
4498e3d6 ILT |
1621 | i.regs[source] = i.regs[dest]; |
1622 | i.regs[dest] = tmp; | |
1623 | } | |
1624 | ||
355afbcd | 1625 | i.rm.mode = 3; |
c5dd66a1 | 1626 | /* We must be careful to make sure that all |
454b0ccd | 1627 | segment/control/test/debug/MMX registers go into |
4498e3d6 | 1628 | the i.rm.reg field (despite whether they are |
454b0ccd ILT |
1629 | source or destination operands). */ |
1630 | if (i.regs[dest]->reg_type | |
1631 | & (SReg2 | SReg3 | Control | Debug | Test | RegMMX)) | |
355afbcd KR |
1632 | { |
1633 | i.rm.reg = i.regs[dest]->reg_num; | |
1634 | i.rm.regmem = i.regs[source]->reg_num; | |
1635 | } | |
1636 | else | |
1637 | { | |
1638 | i.rm.reg = i.regs[source]->reg_num; | |
1639 | i.rm.regmem = i.regs[dest]->reg_num; | |
1640 | } | |
1641 | } | |
1642 | else | |
1643 | { /* if it's not 2 reg operands... */ | |
1644 | if (i.mem_operands) | |
1645 | { | |
1646 | unsigned int fake_zero_displacement = 0; | |
73a8be66 | 1647 | unsigned int op = ((i.types[0] & AnyMem) |
4498e3d6 | 1648 | ? 0 |
73a8be66 | 1649 | : (i.types[1] & AnyMem) ? 1 : 2); |
355afbcd | 1650 | |
ec1e6bb8 | 1651 | default_seg = &ds; |
355afbcd | 1652 | |
ec1e6bb8 | 1653 | if (! i.base_reg) |
355afbcd | 1654 | { |
ec1e6bb8 ILT |
1655 | i.rm.mode = 0; |
1656 | if (! i.disp_operands) | |
1657 | fake_zero_displacement = 1; | |
1658 | if (! i.index_reg) | |
355afbcd | 1659 | { |
ec1e6bb8 | 1660 | /* Operand is just <disp> */ |
0351b70c ILT |
1661 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) |
1662 | { | |
1663 | i.rm.regmem = NO_BASE_REGISTER_16; | |
1664 | i.types[op] &= ~Disp; | |
1665 | i.types[op] |= Disp16; | |
1666 | } | |
1667 | else | |
1668 | { | |
1669 | i.rm.regmem = NO_BASE_REGISTER; | |
1670 | i.types[op] &= ~Disp; | |
1671 | i.types[op] |= Disp32; | |
1672 | } | |
355afbcd | 1673 | } |
0351b70c | 1674 | else /* ! i.base_reg && i.index_reg */ |
355afbcd | 1675 | { |
0351b70c ILT |
1676 | i.sib.index = i.index_reg->reg_num; |
1677 | i.sib.base = NO_BASE_REGISTER; | |
1678 | i.sib.scale = i.log2_scale_factor; | |
ec1e6bb8 ILT |
1679 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
1680 | i.types[op] &= ~Disp; | |
1681 | i.types[op] |= Disp32; /* Must be 32 bit */ | |
355afbcd KR |
1682 | } |
1683 | } | |
0351b70c ILT |
1684 | else if (i.base_reg->reg_type & Reg16) |
1685 | { | |
1686 | switch (i.base_reg->reg_num) | |
1687 | { | |
1688 | case 3: /* (%bx) */ | |
1689 | if (! i.index_reg) | |
1690 | i.rm.regmem = 7; | |
1691 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
1692 | i.rm.regmem = i.index_reg->reg_num - 6; | |
1693 | break; | |
1694 | case 5: /* (%bp) */ | |
1695 | default_seg = &ss; | |
1696 | if (! i.index_reg) | |
1697 | { | |
1698 | i.rm.regmem = 6; | |
1699 | if ((i.types[op] & Disp) == 0) | |
1700 | { | |
1701 | /* fake (%bp) into 0(%bp) */ | |
1702 | i.types[op] |= Disp8; | |
1703 | fake_zero_displacement = 1; | |
1704 | } | |
1705 | } | |
1706 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
1707 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
1708 | break; | |
1709 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
1710 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
1711 | } | |
1712 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
1713 | } | |
1714 | else /* i.base_reg and 32 bit mode */ | |
355afbcd | 1715 | { |
355afbcd | 1716 | i.rm.regmem = i.base_reg->reg_num; |
0351b70c | 1717 | i.sib.base = i.base_reg->reg_num; |
ec1e6bb8 | 1718 | if (i.base_reg->reg_num == EBP_REG_NUM) |
355afbcd | 1719 | { |
ec1e6bb8 ILT |
1720 | default_seg = &ss; |
1721 | if (i.disp_operands == 0) | |
1722 | { | |
355afbcd | 1723 | fake_zero_displacement = 1; |
ad660eb1 | 1724 | i.types[op] |= Disp8; |
355afbcd KR |
1725 | } |
1726 | } | |
ec1e6bb8 ILT |
1727 | else if (i.base_reg->reg_num == ESP_REG_NUM) |
1728 | { | |
1729 | default_seg = &ss; | |
1730 | } | |
0351b70c | 1731 | i.sib.scale = i.log2_scale_factor; |
ec1e6bb8 ILT |
1732 | if (! i.index_reg) |
1733 | { | |
1734 | /* <disp>(%esp) becomes two byte modrm | |
1735 | with no index register. We've already | |
1736 | stored the code for esp in i.rm.regmem | |
1737 | ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any | |
1738 | base register besides %esp will not use | |
1739 | the extra modrm byte. */ | |
0351b70c | 1740 | i.sib.index = NO_INDEX_REGISTER; |
ec1e6bb8 ILT |
1741 | #if ! SCALE1_WHEN_NO_INDEX |
1742 | /* Another case where we force the second | |
1743 | modrm byte. */ | |
1744 | if (i.log2_scale_factor) | |
1745 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
1746 | #endif | |
1747 | } | |
1748 | else | |
1749 | { | |
0351b70c | 1750 | i.sib.index = i.index_reg->reg_num; |
ec1e6bb8 ILT |
1751 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
1752 | } | |
1753 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
355afbcd | 1754 | } |
ec1e6bb8 | 1755 | |
355afbcd KR |
1756 | if (fake_zero_displacement) |
1757 | { | |
ad660eb1 | 1758 | /* Fakes a zero displacement assuming that i.types[op] |
c5dd66a1 | 1759 | holds the correct displacement size. */ |
355afbcd | 1760 | exp = &disp_expressions[i.disp_operands++]; |
ad660eb1 | 1761 | i.disps[op] = exp; |
5ac34ac3 | 1762 | exp->X_op = O_constant; |
355afbcd KR |
1763 | exp->X_add_number = 0; |
1764 | exp->X_add_symbol = (symbolS *) 0; | |
5ac34ac3 | 1765 | exp->X_op_symbol = (symbolS *) 0; |
355afbcd | 1766 | } |
355afbcd KR |
1767 | } |
1768 | ||
454b0ccd | 1769 | /* Fill in i.rm.reg or i.rm.regmem field with register |
227b6b55 ILT |
1770 | operand (if any) based on i.tm.extension_opcode. |
1771 | Again, we must be careful to make sure that | |
1772 | segment/control/debug/test/MMX registers are coded | |
1773 | into the i.rm.reg field. */ | |
355afbcd KR |
1774 | if (i.reg_operands) |
1775 | { | |
ad660eb1 | 1776 | unsigned int op = |
454b0ccd ILT |
1777 | ((i.types[0] |
1778 | & (Reg | SReg2 | SReg3 | Control | Debug | |
1779 | | Test | RegMMX)) | |
1780 | ? 0 | |
1781 | : ((i.types[1] | |
1782 | & (Reg | SReg2 | SReg3 | Control | Debug | |
1783 | | Test | RegMMX)) | |
1784 | ? 1 | |
1785 | : 2)); | |
c5dd66a1 KR |
1786 | /* If there is an extension opcode to put here, the |
1787 | register number must be put into the regmem field. */ | |
227b6b55 | 1788 | if (i.tm.extension_opcode != None) |
ad660eb1 | 1789 | i.rm.regmem = i.regs[op]->reg_num; |
355afbcd | 1790 | else |
ad660eb1 | 1791 | i.rm.reg = i.regs[op]->reg_num; |
355afbcd KR |
1792 | |
1793 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 | |
c5dd66a1 | 1794 | we must set it to 3 to indicate this is a register |
4498e3d6 | 1795 | operand in the regmem field. */ |
355afbcd KR |
1796 | if (!i.mem_operands) |
1797 | i.rm.mode = 3; | |
1798 | } | |
1799 | ||
1800 | /* Fill in i.rm.reg field with extension opcode (if any). */ | |
227b6b55 ILT |
1801 | if (i.tm.extension_opcode != None) |
1802 | i.rm.reg = i.tm.extension_opcode; | |
355afbcd | 1803 | } |
c54c7aac | 1804 | } |
73a8be66 | 1805 | else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) |
4498e3d6 ILT |
1806 | { |
1807 | if (i.tm.base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1) | |
1808 | { | |
73a8be66 | 1809 | as_bad (_("you can't `pop %%cs'")); |
4498e3d6 ILT |
1810 | return; |
1811 | } | |
1812 | i.tm.base_opcode |= (i.regs[0]->reg_num << 3); | |
1813 | } | |
73a8be66 | 1814 | else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32) |
4498e3d6 | 1815 | { |
4498e3d6 ILT |
1816 | default_seg = &ds; |
1817 | } | |
1818 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
1819 | { | |
1820 | /* For the string instructions that allow a segment override | |
1821 | on one of their operands, the default segment is ds. */ | |
1822 | default_seg = &ds; | |
1823 | } | |
c54c7aac | 1824 | |
c54c7aac KR |
1825 | /* If a segment was explicitly specified, |
1826 | and the specified segment is not the default, | |
1827 | use an opcode prefix to select it. | |
1828 | If we never figured out what the default segment is, | |
1829 | then default_seg will be zero at this point, | |
1830 | and the specified segment prefix will always be used. */ | |
4498e3d6 | 1831 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
c54c7aac | 1832 | { |
aa56747a | 1833 | if (! add_prefix (i.seg[0]->seg_prefix)) |
4498e3d6 | 1834 | return; |
355afbcd KR |
1835 | } |
1836 | } | |
73a8be66 ILT |
1837 | else if ((i.tm.opcode_modifier & Ugh) != 0) |
1838 | { | |
1839 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc */ | |
1840 | as_warn (_("translating to `%sp'"), i.tm.name); | |
1841 | } | |
355afbcd KR |
1842 | } |
1843 | ||
1844 | /* Handle conversion of 'int $3' --> special int3 insn. */ | |
227b6b55 | 1845 | if (i.tm.base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3) |
355afbcd | 1846 | { |
227b6b55 | 1847 | i.tm.base_opcode = INT3_OPCODE; |
355afbcd KR |
1848 | i.imm_operands = 0; |
1849 | } | |
1850 | ||
1851 | /* We are ready to output the insn. */ | |
1852 | { | |
1853 | register char *p; | |
1854 | ||
1855 | /* Output jumps. */ | |
227b6b55 | 1856 | if (i.tm.opcode_modifier & Jump) |
355afbcd | 1857 | { |
61c49d66 | 1858 | long n = (long) i.disps[0]->X_add_number; |
0351b70c ILT |
1859 | int prefix = (i.prefix[DATA_PREFIX] != 0); |
1860 | int code16 = 0; | |
1861 | ||
1862 | if (prefix) | |
1863 | { | |
1864 | i.prefixes -= 1; | |
1865 | code16 = CODE16; | |
1866 | } | |
1867 | if (flag_16bit_code) | |
1868 | code16 ^= CODE16; | |
355afbcd | 1869 | |
4498e3d6 | 1870 | if (i.prefixes != 0) |
aa56747a | 1871 | as_warn (_("skipping prefixes on this instruction")); |
4498e3d6 | 1872 | |
5ac34ac3 | 1873 | if (i.disps[0]->X_op == O_constant) |
355afbcd | 1874 | { |
355afbcd KR |
1875 | if (fits_in_signed_byte (n)) |
1876 | { | |
ad660eb1 | 1877 | insn_size += 2; |
0351b70c | 1878 | p = frag_more (2); |
227b6b55 | 1879 | p[0] = i.tm.base_opcode; |
355afbcd | 1880 | p[1] = n; |
355afbcd | 1881 | } |
355afbcd | 1882 | else |
0351b70c | 1883 | { |
4498e3d6 | 1884 | /* Use 16-bit jumps only for 16-bit code, |
c54c7aac | 1885 | because text segments are limited to 64K anyway; |
4498e3d6 ILT |
1886 | Use 32-bit jumps for 32-bit code, because they're faster, |
1887 | and a 16-bit jump will clear the top 16 bits of %eip. */ | |
0351b70c ILT |
1888 | int jmp_size = code16 ? 2 : 4; |
1889 | if (code16 && !fits_in_signed_word (n)) | |
c54c7aac | 1890 | { |
48401fcf | 1891 | as_bad (_("16-bit jump out of range")); |
c54c7aac KR |
1892 | return; |
1893 | } | |
1894 | ||
227b6b55 | 1895 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) |
355afbcd KR |
1896 | { /* pace */ |
1897 | /* unconditional jump */ | |
0351b70c ILT |
1898 | insn_size += prefix + 1 + jmp_size; |
1899 | p = frag_more (prefix + 1 + jmp_size); | |
1900 | if (prefix) | |
1901 | *p++ = DATA_PREFIX_OPCODE; | |
1902 | *p++ = (char) 0xe9; | |
1903 | md_number_to_chars (p, (valueT) n, jmp_size); | |
355afbcd KR |
1904 | } |
1905 | else | |
1906 | { | |
1907 | /* conditional jump */ | |
0351b70c ILT |
1908 | insn_size += prefix + 2 + jmp_size; |
1909 | p = frag_more (prefix + 2 + jmp_size); | |
1910 | if (prefix) | |
1911 | *p++ = DATA_PREFIX_OPCODE; | |
1912 | *p++ = TWO_BYTE_OPCODE_ESCAPE; | |
1913 | *p++ = i.tm.base_opcode + 0x10; | |
1914 | md_number_to_chars (p, (valueT) n, jmp_size); | |
355afbcd KR |
1915 | } |
1916 | } | |
49864cfa KR |
1917 | } |
1918 | else | |
1919 | { | |
0351b70c | 1920 | int size = code16 ? 2 : 4; |
c54c7aac | 1921 | |
355afbcd | 1922 | /* It's a symbol; end frag & setup for relax. |
49864cfa KR |
1923 | Make sure there are more than 6 chars left in the current frag; |
1924 | if not we'll have to start a new one. */ | |
0351b70c ILT |
1925 | frag_grow (prefix + 1 + 2 + size); |
1926 | insn_size += 1 + prefix; | |
1927 | p = frag_more (1 + prefix); | |
1928 | if (prefix) | |
1929 | *p++ = DATA_PREFIX_OPCODE; | |
1930 | *p = i.tm.base_opcode; | |
355afbcd | 1931 | frag_var (rs_machine_dependent, |
0351b70c | 1932 | prefix + 2 + size, /* 2 opcode/prefix + displacement */ |
355afbcd KR |
1933 | 1, |
1934 | ((unsigned char) *p == JUMP_PC_RELATIVE | |
0351b70c ILT |
1935 | ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16 |
1936 | : ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16), | |
355afbcd | 1937 | i.disps[0]->X_add_symbol, |
f59fb6ca | 1938 | (offsetT) n, p); |
355afbcd KR |
1939 | } |
1940 | } | |
227b6b55 | 1941 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) |
355afbcd | 1942 | { |
227b6b55 | 1943 | int size = (i.tm.opcode_modifier & JumpByte) ? 1 : 4; |
61c49d66 | 1944 | long n = (long) i.disps[0]->X_add_number; |
c54c7aac | 1945 | |
aa56747a | 1946 | if (size == 1) /* then this is a loop or jecxz type instruction */ |
c54c7aac | 1947 | { |
aa56747a | 1948 | if (i.prefix[ADDR_PREFIX]) |
c54c7aac | 1949 | { |
0351b70c | 1950 | insn_size += 1; |
aa56747a | 1951 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); |
0351b70c ILT |
1952 | i.prefixes -= 1; |
1953 | } | |
1954 | } | |
1955 | else | |
1956 | { | |
1957 | int code16 = 0; | |
1958 | ||
1959 | if (i.prefix[DATA_PREFIX]) | |
1960 | { | |
aa56747a | 1961 | insn_size += 1; |
0351b70c | 1962 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); |
73a8be66 | 1963 | i.prefixes -= 1; |
0351b70c | 1964 | code16 = CODE16; |
c54c7aac | 1965 | } |
0351b70c ILT |
1966 | if (flag_16bit_code) |
1967 | code16 ^= CODE16; | |
1968 | ||
1969 | if (code16) | |
1970 | size = 2; | |
c54c7aac KR |
1971 | } |
1972 | ||
aa56747a ILT |
1973 | if (i.prefixes != 0) |
1974 | as_warn (_("skipping prefixes on this instruction")); | |
1975 | ||
227b6b55 | 1976 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
355afbcd | 1977 | { |
0351b70c ILT |
1978 | insn_size += 1 + size; |
1979 | p = frag_more (1 + size); | |
355afbcd KR |
1980 | } |
1981 | else | |
1982 | { | |
0351b70c ILT |
1983 | insn_size += 2 + size; /* opcode can be at most two bytes */ |
1984 | p = frag_more (2 + size); | |
227b6b55 | 1985 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
355afbcd | 1986 | } |
0351b70c | 1987 | *p++ = i.tm.base_opcode & 0xff; |
355afbcd | 1988 | |
5ac34ac3 | 1989 | if (i.disps[0]->X_op == O_constant) |
355afbcd | 1990 | { |
355afbcd KR |
1991 | if (size == 1 && !fits_in_signed_byte (n)) |
1992 | { | |
61c49d66 | 1993 | as_bad (_("`%s' only takes byte displacement; %ld shortened to %d"), |
73a8be66 | 1994 | i.tm.name, n, *p); |
355afbcd | 1995 | } |
0351b70c ILT |
1996 | else if (size == 2 && !fits_in_signed_word (n)) |
1997 | { | |
1998 | as_bad (_("16-bit jump out of range")); | |
1999 | return; | |
2000 | } | |
2001 | md_number_to_chars (p, (valueT) n, size); | |
49864cfa KR |
2002 | } |
2003 | else | |
2004 | { | |
5ac34ac3 | 2005 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
f0b37b4a KR |
2006 | i.disps[0], 1, reloc (size, 1, i.disp_reloc[0])); |
2007 | ||
355afbcd KR |
2008 | } |
2009 | } | |
227b6b55 | 2010 | else if (i.tm.opcode_modifier & JumpInterSegment) |
355afbcd | 2011 | { |
0351b70c ILT |
2012 | int size; |
2013 | int reloc_type; | |
2014 | int prefix = i.prefix[DATA_PREFIX] != 0; | |
2015 | int code16 = 0; | |
4498e3d6 | 2016 | |
0351b70c ILT |
2017 | if (prefix) |
2018 | { | |
2019 | code16 = CODE16; | |
2020 | i.prefixes -= 1; | |
2021 | } | |
c54c7aac | 2022 | if (flag_16bit_code) |
0351b70c ILT |
2023 | code16 ^= CODE16; |
2024 | ||
2025 | size = 4; | |
2026 | reloc_type = BFD_RELOC_32; | |
2027 | if (code16) | |
c54c7aac | 2028 | { |
0351b70c ILT |
2029 | size = 2; |
2030 | reloc_type = BFD_RELOC_16; | |
c54c7aac KR |
2031 | } |
2032 | ||
0351b70c ILT |
2033 | if (i.prefixes != 0) |
2034 | as_warn (_("skipping prefixes on this instruction")); | |
2035 | ||
2036 | insn_size += prefix + 1 + 2 + size; /* 1 opcode; 2 segment; offset */ | |
2037 | p = frag_more (prefix + 1 + 2 + size); | |
2038 | if (prefix) | |
2039 | *p++ = DATA_PREFIX_OPCODE; | |
2040 | *p++ = i.tm.base_opcode; | |
5ac34ac3 | 2041 | if (i.imms[1]->X_op == O_constant) |
0351b70c | 2042 | { |
61c49d66 ILT |
2043 | long n = (long) i.imms[1]->X_add_number; |
2044 | ||
0351b70c ILT |
2045 | if (size == 2 && !fits_in_unsigned_word (n)) |
2046 | { | |
2047 | as_bad (_("16-bit jump out of range")); | |
2048 | return; | |
2049 | } | |
2050 | md_number_to_chars (p, (valueT) n, size); | |
2051 | } | |
355afbcd | 2052 | else |
0351b70c ILT |
2053 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
2054 | i.imms[1], 0, reloc_type); | |
5ac34ac3 | 2055 | if (i.imms[0]->X_op != O_constant) |
0351b70c ILT |
2056 | as_bad (_("can't handle non absolute segment in `%s'"), |
2057 | i.tm.name); | |
2058 | md_number_to_chars (p + size, (valueT) i.imms[0]->X_add_number, 2); | |
355afbcd KR |
2059 | } |
2060 | else | |
2061 | { | |
2062 | /* Output normal instructions here. */ | |
2063 | unsigned char *q; | |
2064 | ||
4498e3d6 | 2065 | /* The prefix bytes. */ |
aa56747a ILT |
2066 | for (q = i.prefix; |
2067 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); | |
2068 | q++) | |
355afbcd | 2069 | { |
aa56747a ILT |
2070 | if (*q) |
2071 | { | |
aa56747a | 2072 | insn_size += 1; |
0351b70c | 2073 | p = frag_more (1); |
aa56747a ILT |
2074 | md_number_to_chars (p, (valueT) *q, 1); |
2075 | } | |
355afbcd KR |
2076 | } |
2077 | ||
2078 | /* Now the opcode; be careful about word order here! */ | |
227b6b55 | 2079 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
355afbcd | 2080 | { |
ad660eb1 | 2081 | insn_size += 1; |
0351b70c | 2082 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); |
355afbcd | 2083 | } |
227b6b55 | 2084 | else if (fits_in_unsigned_word (i.tm.base_opcode)) |
355afbcd | 2085 | { |
ad660eb1 | 2086 | insn_size += 2; |
0351b70c | 2087 | p = frag_more (2); |
355afbcd | 2088 | /* put out high byte first: can't use md_number_to_chars! */ |
227b6b55 ILT |
2089 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
2090 | *p = i.tm.base_opcode & 0xff; | |
355afbcd KR |
2091 | } |
2092 | else | |
2093 | { /* opcode is either 3 or 4 bytes */ | |
227b6b55 | 2094 | if (i.tm.base_opcode & 0xff000000) |
355afbcd | 2095 | { |
ad660eb1 | 2096 | insn_size += 4; |
0351b70c | 2097 | p = frag_more (4); |
227b6b55 | 2098 | *p++ = (i.tm.base_opcode >> 24) & 0xff; |
355afbcd KR |
2099 | } |
2100 | else | |
ad660eb1 | 2101 | { |
ad660eb1 | 2102 | insn_size += 3; |
0351b70c | 2103 | p = frag_more (3); |
ad660eb1 | 2104 | } |
227b6b55 ILT |
2105 | *p++ = (i.tm.base_opcode >> 16) & 0xff; |
2106 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
2107 | *p = (i.tm.base_opcode) & 0xff; | |
355afbcd KR |
2108 | } |
2109 | ||
0351b70c | 2110 | /* Now the modrm byte and sib byte (if present). */ |
227b6b55 | 2111 | if (i.tm.opcode_modifier & Modrm) |
355afbcd | 2112 | { |
ad660eb1 | 2113 | insn_size += 1; |
0351b70c | 2114 | p = frag_more (1); |
ad660eb1 ILT |
2115 | md_number_to_chars (p, |
2116 | (valueT) (i.rm.regmem << 0 | |
2117 | | i.rm.reg << 3 | |
2118 | | i.rm.mode << 6), | |
2119 | 1); | |
73a8be66 ILT |
2120 | /* If i.rm.regmem == ESP (4) |
2121 | && i.rm.mode != (Register mode) | |
0351b70c | 2122 | && not 16 bit |
73a8be66 | 2123 | ==> need second modrm byte. */ |
ec1e6bb8 | 2124 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING |
0351b70c ILT |
2125 | && i.rm.mode != 3 |
2126 | && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) | |
355afbcd | 2127 | { |
ad660eb1 | 2128 | insn_size += 1; |
0351b70c ILT |
2129 | p = frag_more (1); |
2130 | md_number_to_chars (p, | |
2131 | (valueT) (i.sib.base << 0 | |
2132 | | i.sib.index << 3 | |
2133 | | i.sib.scale << 6), | |
ad660eb1 | 2134 | 1); |
355afbcd KR |
2135 | } |
2136 | } | |
2137 | ||
2138 | if (i.disp_operands) | |
2139 | { | |
2140 | register unsigned int n; | |
2141 | ||
2142 | for (n = 0; n < i.operands; n++) | |
2143 | { | |
2144 | if (i.disps[n]) | |
2145 | { | |
5ac34ac3 | 2146 | if (i.disps[n]->X_op == O_constant) |
355afbcd | 2147 | { |
73a8be66 | 2148 | if (i.types[n] & Disp8) |
355afbcd | 2149 | { |
ad660eb1 | 2150 | insn_size += 1; |
0351b70c | 2151 | p = frag_more (1); |
ad660eb1 ILT |
2152 | md_number_to_chars (p, |
2153 | (valueT) i.disps[n]->X_add_number, | |
2154 | 1); | |
355afbcd | 2155 | } |
73a8be66 | 2156 | else if (i.types[n] & Disp16) |
355afbcd | 2157 | { |
ad660eb1 | 2158 | insn_size += 2; |
0351b70c | 2159 | p = frag_more (2); |
ad660eb1 ILT |
2160 | md_number_to_chars (p, |
2161 | (valueT) i.disps[n]->X_add_number, | |
2162 | 2); | |
355afbcd KR |
2163 | } |
2164 | else | |
73a8be66 | 2165 | { /* Disp32 */ |
ad660eb1 | 2166 | insn_size += 4; |
0351b70c | 2167 | p = frag_more (4); |
ad660eb1 ILT |
2168 | md_number_to_chars (p, |
2169 | (valueT) i.disps[n]->X_add_number, | |
2170 | 4); | |
355afbcd KR |
2171 | } |
2172 | } | |
0351b70c ILT |
2173 | else if (i.types[n] & Disp32) |
2174 | { | |
ad660eb1 | 2175 | insn_size += 4; |
0351b70c | 2176 | p = frag_more (4); |
5ac34ac3 | 2177 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, |
0351b70c ILT |
2178 | i.disps[n], 0, |
2179 | TC_RELOC (i.disp_reloc[n], BFD_RELOC_32)); | |
2180 | } | |
2181 | else | |
2182 | { /* must be Disp16 */ | |
2183 | insn_size += 2; | |
2184 | p = frag_more (2); | |
2185 | fix_new_exp (frag_now, p - frag_now->fr_literal, 2, | |
2186 | i.disps[n], 0, | |
2187 | TC_RELOC (i.disp_reloc[n], BFD_RELOC_16)); | |
355afbcd KR |
2188 | } |
2189 | } | |
2190 | } | |
2191 | } /* end displacement output */ | |
2192 | ||
2193 | /* output immediate */ | |
2194 | if (i.imm_operands) | |
2195 | { | |
2196 | register unsigned int n; | |
2197 | ||
2198 | for (n = 0; n < i.operands; n++) | |
2199 | { | |
2200 | if (i.imms[n]) | |
2201 | { | |
5ac34ac3 | 2202 | if (i.imms[n]->X_op == O_constant) |
355afbcd KR |
2203 | { |
2204 | if (i.types[n] & (Imm8 | Imm8S)) | |
2205 | { | |
ad660eb1 | 2206 | insn_size += 1; |
0351b70c | 2207 | p = frag_more (1); |
ad660eb1 ILT |
2208 | md_number_to_chars (p, |
2209 | (valueT) i.imms[n]->X_add_number, | |
2210 | 1); | |
355afbcd KR |
2211 | } |
2212 | else if (i.types[n] & Imm16) | |
2213 | { | |
ad660eb1 | 2214 | insn_size += 2; |
0351b70c | 2215 | p = frag_more (2); |
ad660eb1 ILT |
2216 | md_number_to_chars (p, |
2217 | (valueT) i.imms[n]->X_add_number, | |
2218 | 2); | |
355afbcd KR |
2219 | } |
2220 | else | |
2221 | { | |
ad660eb1 | 2222 | insn_size += 4; |
0351b70c | 2223 | p = frag_more (4); |
ad660eb1 ILT |
2224 | md_number_to_chars (p, |
2225 | (valueT) i.imms[n]->X_add_number, | |
2226 | 4); | |
355afbcd KR |
2227 | } |
2228 | } | |
2229 | else | |
49864cfa | 2230 | { /* not absolute_section */ |
f0b37b4a KR |
2231 | /* Need a 32-bit fixup (don't support 8bit |
2232 | non-absolute ims). Try to support other | |
2233 | sizes ... */ | |
2234 | int r_type; | |
355afbcd | 2235 | int size; |
f0b37b4a KR |
2236 | int pcrel = 0; |
2237 | ||
355afbcd KR |
2238 | if (i.types[n] & (Imm8 | Imm8S)) |
2239 | size = 1; | |
2240 | else if (i.types[n] & Imm16) | |
2241 | size = 2; | |
2242 | else | |
2243 | size = 4; | |
ad660eb1 | 2244 | insn_size += size; |
0351b70c ILT |
2245 | p = frag_more (size); |
2246 | r_type = reloc (size, 0, i.disp_reloc[0]); | |
f0b37b4a | 2247 | #ifdef BFD_ASSEMBLER |
c54c7aac | 2248 | if (r_type == BFD_RELOC_32 |
f0b37b4a | 2249 | && GOT_symbol |
0877841d ILT |
2250 | && GOT_symbol == i.imms[n]->X_add_symbol |
2251 | && (i.imms[n]->X_op == O_symbol | |
2252 | || (i.imms[n]->X_op == O_add | |
2253 | && (i.imms[n]->X_op_symbol->sy_value.X_op | |
2254 | == O_subtract)))) | |
f0b37b4a KR |
2255 | { |
2256 | r_type = BFD_RELOC_386_GOTPC; | |
2257 | i.imms[n]->X_add_number += 3; | |
2258 | } | |
2259 | #endif | |
5ac34ac3 | 2260 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
f0b37b4a | 2261 | i.imms[n], pcrel, r_type); |
355afbcd KR |
2262 | } |
2263 | } | |
2264 | } | |
2265 | } /* end immediate output */ | |
2266 | } | |
2267 | ||
fecd2382 | 2268 | #ifdef DEBUG386 |
ade614d5 | 2269 | if (flag_debug) |
355afbcd KR |
2270 | { |
2271 | pi (line, &i); | |
2272 | } | |
fecd2382 | 2273 | #endif /* DEBUG386 */ |
355afbcd | 2274 | } |
fecd2382 RP |
2275 | } |
2276 | \f | |
2277 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero | |
2278 | on error. */ | |
2279 | ||
355afbcd KR |
2280 | static int |
2281 | i386_operand (operand_string) | |
2282 | char *operand_string; | |
fecd2382 | 2283 | { |
355afbcd KR |
2284 | register char *op_string = operand_string; |
2285 | ||
355afbcd | 2286 | /* We check for an absolute prefix (differentiating, |
3c8df4ba | 2287 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
355afbcd KR |
2288 | if (*op_string == ABSOLUTE_PREFIX) |
2289 | { | |
4edc93e9 ILT |
2290 | ++op_string; |
2291 | if (is_space_char (*op_string)) | |
2292 | ++op_string; | |
355afbcd KR |
2293 | i.types[this_operand] |= JumpAbsolute; |
2294 | } | |
2295 | ||
2296 | /* Check if operand is a register. */ | |
2297 | if (*op_string == REGISTER_PREFIX) | |
2298 | { | |
0351b70c | 2299 | register const reg_entry *r; |
4edc93e9 ILT |
2300 | char *end_op; |
2301 | ||
2302 | r = parse_register (op_string, &end_op); | |
2303 | if (r == NULL) | |
2304 | return 0; | |
2305 | /* Check for a segment override by searching for ':' after a | |
2306 | segment register. */ | |
2307 | op_string = end_op; | |
2308 | if (is_space_char (*op_string)) | |
2309 | ++op_string; | |
7540e470 | 2310 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) |
355afbcd | 2311 | { |
7540e470 | 2312 | switch (r->reg_num) |
355afbcd | 2313 | { |
7540e470 ILT |
2314 | case 0: |
2315 | i.seg[i.mem_operands] = &es; | |
2316 | break; | |
2317 | case 1: | |
2318 | i.seg[i.mem_operands] = &cs; | |
2319 | break; | |
2320 | case 2: | |
2321 | i.seg[i.mem_operands] = &ss; | |
2322 | break; | |
2323 | case 3: | |
2324 | i.seg[i.mem_operands] = &ds; | |
2325 | break; | |
2326 | case 4: | |
2327 | i.seg[i.mem_operands] = &fs; | |
2328 | break; | |
2329 | case 5: | |
2330 | i.seg[i.mem_operands] = &gs; | |
2331 | break; | |
2332 | } | |
4edc93e9 | 2333 | |
7540e470 ILT |
2334 | /* Skip the ':' and whitespace. */ |
2335 | ++op_string; | |
2336 | if (is_space_char (*op_string)) | |
2337 | ++op_string; | |
2338 | ||
2339 | /* Pretend given string starts here. */ | |
2340 | operand_string = op_string; | |
2341 | if (!is_digit_char (*op_string) | |
2342 | && !is_identifier_char (*op_string) | |
2343 | && *op_string != '(' | |
2344 | && *op_string != ABSOLUTE_PREFIX) | |
2345 | { | |
2346 | as_bad (_("bad memory operand `%s'"), op_string); | |
2347 | return 0; | |
2348 | } | |
2349 | /* Handle case of %es:*foo. */ | |
2350 | if (*op_string == ABSOLUTE_PREFIX) | |
2351 | { | |
4edc93e9 ILT |
2352 | ++op_string; |
2353 | if (is_space_char (*op_string)) | |
2354 | ++op_string; | |
7540e470 | 2355 | i.types[this_operand] |= JumpAbsolute; |
355afbcd | 2356 | } |
7540e470 ILT |
2357 | goto do_memory_reference; |
2358 | } | |
2359 | if (*op_string) | |
2360 | { | |
2361 | as_bad (_("Junk `%s' after register"), op_string); | |
2362 | return 0; | |
355afbcd | 2363 | } |
ec1e6bb8 | 2364 | i.types[this_operand] |= r->reg_type & ~BaseIndex; |
355afbcd KR |
2365 | i.regs[this_operand] = r; |
2366 | i.reg_operands++; | |
2367 | } | |
2368 | else if (*op_string == IMMEDIATE_PREFIX) | |
2369 | { /* ... or an immediate */ | |
2370 | char *save_input_line_pointer; | |
49864cfa | 2371 | segT exp_seg = 0; |
355afbcd KR |
2372 | expressionS *exp; |
2373 | ||
2374 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
2375 | { | |
48401fcf | 2376 | as_bad (_("only 1 or 2 immediate operands are allowed")); |
355afbcd KR |
2377 | return 0; |
2378 | } | |
542e1629 | 2379 | |
355afbcd KR |
2380 | exp = &im_expressions[i.imm_operands++]; |
2381 | i.imms[this_operand] = exp; | |
4edc93e9 ILT |
2382 | |
2383 | ++op_string; | |
2384 | if (is_space_char (*op_string)) | |
2385 | ++op_string; | |
2386 | ||
355afbcd | 2387 | save_input_line_pointer = input_line_pointer; |
4edc93e9 | 2388 | input_line_pointer = op_string; |
355afbcd | 2389 | exp_seg = expression (exp); |
388fa5c6 | 2390 | if (*input_line_pointer != '\0') |
dddc8a82 ILT |
2391 | { |
2392 | /* This should be as_bad, but some versions of gcc, up to | |
2393 | about 2.8 and egcs 1.01, generate a bogus @GOTOFF(%ebx) | |
2394 | in certain cases. Oddly, the code in question turns out | |
2395 | to work correctly anyhow, so we make this just a warning | |
2396 | until those versions of gcc are obsolete. */ | |
48401fcf | 2397 | as_warn (_("unrecognized characters `%s' in expression"), |
dddc8a82 ILT |
2398 | input_line_pointer); |
2399 | } | |
355afbcd KR |
2400 | input_line_pointer = save_input_line_pointer; |
2401 | ||
7b23213f | 2402 | if (exp->X_op == O_absent) |
355afbcd | 2403 | { |
49864cfa | 2404 | /* missing or bad expr becomes absolute 0 */ |
48401fcf | 2405 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
355afbcd | 2406 | operand_string); |
5ac34ac3 | 2407 | exp->X_op = O_constant; |
355afbcd KR |
2408 | exp->X_add_number = 0; |
2409 | exp->X_add_symbol = (symbolS *) 0; | |
5ac34ac3 | 2410 | exp->X_op_symbol = (symbolS *) 0; |
355afbcd | 2411 | i.types[this_operand] |= Imm; |
49864cfa | 2412 | } |
7b23213f | 2413 | else if (exp->X_op == O_constant) |
49864cfa | 2414 | { |
ad660eb1 | 2415 | i.types[this_operand] |= |
0351b70c | 2416 | smallest_imm_type ((long) exp->X_add_number); |
61c49d66 ILT |
2417 | |
2418 | /* If a suffix is given, this operand may be shortened. */ | |
2419 | switch (i.suffix) | |
2420 | { | |
668f52e0 | 2421 | case WORD_MNEM_SUFFIX: |
61c49d66 ILT |
2422 | i.types[this_operand] |= Imm16; |
2423 | break; | |
668f52e0 | 2424 | case BYTE_MNEM_SUFFIX: |
61c49d66 ILT |
2425 | i.types[this_operand] |= Imm16 | Imm8 | Imm8S; |
2426 | break; | |
2427 | } | |
49864cfa | 2428 | } |
7b23213f | 2429 | #ifdef OBJ_AOUT |
49864cfa KR |
2430 | else if (exp_seg != text_section |
2431 | && exp_seg != data_section | |
2432 | && exp_seg != bss_section | |
2433 | && exp_seg != undefined_section | |
2434 | #ifdef BFD_ASSEMBLER | |
2435 | && ! bfd_is_com_section (exp_seg) | |
2436 | #endif | |
2437 | ) | |
2438 | { | |
355afbcd | 2439 | seg_unimplemented: |
61c49d66 | 2440 | as_bad (_("Unimplemented segment type %d in operand"), exp_seg); |
355afbcd KR |
2441 | return 0; |
2442 | } | |
49864cfa KR |
2443 | #endif |
2444 | else | |
2445 | { | |
5819d632 ILT |
2446 | /* This is an address. The size of the address will be |
2447 | determined later, depending on destination register, | |
2448 | suffix, or the default for the section. We exclude | |
2449 | Imm8S here so that `push $foo' and other instructions | |
2450 | with an Imm8S form will use Imm16 or Imm32. */ | |
2451 | i.types[this_operand] |= (Imm8 | Imm16 | Imm32); | |
355afbcd KR |
2452 | } |
2453 | } | |
2454 | else if (is_digit_char (*op_string) || is_identifier_char (*op_string) | |
2455 | || *op_string == '(') | |
2456 | { | |
2457 | /* This is a memory reference of some sort. */ | |
0351b70c | 2458 | char *end_of_operand_string; |
355afbcd | 2459 | register char *base_string; |
ec1e6bb8 | 2460 | int found_base_index_form; |
355afbcd | 2461 | |
0351b70c ILT |
2462 | /* Start and end of displacement string expression (if found). */ |
2463 | char *displacement_string_start; | |
2464 | char *displacement_string_end; | |
2465 | ||
355afbcd | 2466 | do_memory_reference: |
4498e3d6 ILT |
2467 | if ((i.mem_operands == 1 |
2468 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
2469 | || i.mem_operands == 2) | |
355afbcd | 2470 | { |
48401fcf | 2471 | as_bad (_("too many memory references for `%s'"), |
4498e3d6 | 2472 | current_templates->start->name); |
355afbcd KR |
2473 | return 0; |
2474 | } | |
355afbcd | 2475 | |
49864cfa KR |
2476 | /* Check for base index form. We detect the base index form by |
2477 | looking for an ')' at the end of the operand, searching | |
2478 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
4edc93e9 | 2479 | after the '('. */ |
355afbcd | 2480 | found_base_index_form = 0; |
0351b70c | 2481 | end_of_operand_string = op_string + strlen (op_string); |
4edc93e9 ILT |
2482 | |
2483 | --end_of_operand_string; | |
2484 | if (is_space_char (*end_of_operand_string)) | |
2485 | --end_of_operand_string; | |
2486 | ||
2487 | base_string = end_of_operand_string; | |
355afbcd KR |
2488 | if (*base_string == ')') |
2489 | { | |
0b476c53 | 2490 | unsigned int parens_balanced = 1; |
49864cfa KR |
2491 | /* We've already checked that the number of left & right ()'s are |
2492 | equal, so this loop will not be infinite. */ | |
355afbcd KR |
2493 | do |
2494 | { | |
2495 | base_string--; | |
2496 | if (*base_string == ')') | |
0b476c53 | 2497 | parens_balanced++; |
355afbcd | 2498 | if (*base_string == '(') |
0b476c53 | 2499 | parens_balanced--; |
355afbcd | 2500 | } |
0b476c53 | 2501 | while (parens_balanced); |
4edc93e9 ILT |
2502 | |
2503 | /* If there is a displacement set-up for it to be parsed later. */ | |
2504 | displacement_string_start = op_string; | |
2505 | displacement_string_end = base_string; | |
2506 | ||
2507 | /* Skip past '(' and whitespace. */ | |
2508 | ++base_string; | |
2509 | if (is_space_char (*base_string)) | |
2510 | ++base_string; | |
2511 | ||
355afbcd KR |
2512 | if (*base_string == REGISTER_PREFIX || *base_string == ',') |
2513 | found_base_index_form = 1; | |
2514 | } | |
2515 | ||
2516 | /* If we can't parse a base index register expression, we've found | |
49864cfa KR |
2517 | a pure displacement expression. We set up displacement_string_start |
2518 | and displacement_string_end for the code below. */ | |
355afbcd KR |
2519 | if (!found_base_index_form) |
2520 | { | |
2521 | displacement_string_start = op_string; | |
4edc93e9 | 2522 | displacement_string_end = end_of_operand_string + 1; |
355afbcd KR |
2523 | } |
2524 | else | |
2525 | { | |
355afbcd KR |
2526 | i.types[this_operand] |= BaseIndex; |
2527 | ||
355afbcd KR |
2528 | /* Find base register (if any). */ |
2529 | if (*base_string != ',') | |
2530 | { | |
4edc93e9 ILT |
2531 | char *end_op; |
2532 | ||
2533 | /* Trim off the closing ')' so that parse_register won't | |
2534 | see it. */ | |
2535 | END_STRING_AND_SAVE (end_of_operand_string); | |
2536 | i.base_reg = parse_register (base_string, &end_op); | |
4edc93e9 | 2537 | RESTORE_END_STRING (end_of_operand_string); |
61c49d66 ILT |
2538 | |
2539 | if (i.base_reg == NULL) | |
2540 | return 0; | |
2541 | ||
4edc93e9 ILT |
2542 | base_string = end_op; |
2543 | if (is_space_char (*base_string)) | |
2544 | ++base_string; | |
355afbcd KR |
2545 | } |
2546 | ||
4edc93e9 ILT |
2547 | /* There may be an index reg or scale factor here. */ |
2548 | if (*base_string == ',') | |
355afbcd | 2549 | { |
4edc93e9 ILT |
2550 | ++base_string; |
2551 | if (is_space_char (*base_string)) | |
2552 | ++base_string; | |
355afbcd | 2553 | |
4edc93e9 | 2554 | if (*base_string == REGISTER_PREFIX) |
355afbcd | 2555 | { |
4edc93e9 ILT |
2556 | char *end_op; |
2557 | ||
2558 | END_STRING_AND_SAVE (end_of_operand_string); | |
2559 | i.index_reg = parse_register (base_string, &end_op); | |
2560 | RESTORE_END_STRING (end_of_operand_string); | |
2561 | ||
2562 | if (i.index_reg == NULL) | |
2563 | return 0; | |
2564 | ||
2565 | base_string = end_op; | |
2566 | if (is_space_char (*base_string)) | |
2567 | ++base_string; | |
2568 | if (*base_string == ',') | |
2569 | { | |
2570 | ++base_string; | |
2571 | if (is_space_char (*base_string)) | |
2572 | ++base_string; | |
2573 | } | |
2574 | else if (*base_string != ')') | |
2575 | { | |
2576 | as_bad (_("expecting `,' or `)' after index register in `%s'"), | |
2577 | operand_string); | |
2578 | return 0; | |
2579 | } | |
a39116f1 | 2580 | } |
355afbcd | 2581 | |
4edc93e9 ILT |
2582 | /* Check for scale factor. */ |
2583 | if (isdigit ((unsigned char) *base_string)) | |
ec1e6bb8 | 2584 | { |
4edc93e9 ILT |
2585 | if (isdigit ((unsigned char) base_string[1])) |
2586 | goto bad_scale; /* must be 1 digit scale */ | |
2587 | switch (*base_string) | |
2588 | { | |
2589 | case '1': | |
2590 | i.log2_scale_factor = 0; | |
2591 | break; | |
2592 | case '2': | |
2593 | i.log2_scale_factor = 1; | |
2594 | break; | |
2595 | case '4': | |
2596 | i.log2_scale_factor = 2; | |
2597 | break; | |
2598 | case '8': | |
2599 | i.log2_scale_factor = 3; | |
2600 | break; | |
2601 | default: | |
2602 | bad_scale: | |
2603 | as_bad (_("expecting scale factor of 1, 2, 4 or 8; got `%s'"), | |
2604 | base_string); | |
2605 | return 0; | |
2606 | } | |
2607 | ||
2608 | ++base_string; | |
2609 | if (is_space_char (*base_string)) | |
2610 | ++base_string; | |
2611 | if (*base_string != ')') | |
2612 | { | |
2613 | as_bad (_("expecting `)' after scale factor in `%s'"), | |
2614 | operand_string); | |
2615 | return 0; | |
2616 | } | |
2617 | if (i.log2_scale_factor != 0 && ! i.index_reg) | |
2618 | { | |
2619 | as_warn (_("scale factor of %d without an index register"), | |
2620 | 1 << i.log2_scale_factor); | |
ec1e6bb8 | 2621 | #if SCALE1_WHEN_NO_INDEX |
4edc93e9 | 2622 | i.log2_scale_factor = 0; |
ec1e6bb8 | 2623 | #endif |
4edc93e9 | 2624 | } |
ec1e6bb8 | 2625 | } |
4edc93e9 | 2626 | else if (!i.index_reg) |
355afbcd | 2627 | { |
48401fcf | 2628 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
4edc93e9 | 2629 | *base_string); |
355afbcd | 2630 | return 0; |
a39116f1 | 2631 | } |
355afbcd | 2632 | } |
4edc93e9 ILT |
2633 | else if (*base_string != ')') |
2634 | { | |
2635 | as_bad (_("expecting `,' or `)' after base register in `%s'"), | |
2636 | operand_string); | |
2637 | return 0; | |
2638 | } | |
355afbcd KR |
2639 | } |
2640 | ||
2641 | /* If there's an expression begining the operand, parse it, | |
4edc93e9 ILT |
2642 | assuming displacement_string_start and |
2643 | displacement_string_end are meaningful. */ | |
2644 | if (displacement_string_start != displacement_string_end) | |
355afbcd KR |
2645 | { |
2646 | register expressionS *exp; | |
49864cfa | 2647 | segT exp_seg = 0; |
355afbcd | 2648 | char *save_input_line_pointer; |
0351b70c ILT |
2649 | int bigdisp = Disp32; |
2650 | ||
2651 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) | |
2652 | bigdisp = Disp16; | |
2653 | i.types[this_operand] |= bigdisp; | |
aa56747a | 2654 | |
355afbcd KR |
2655 | exp = &disp_expressions[i.disp_operands]; |
2656 | i.disps[this_operand] = exp; | |
f0b37b4a | 2657 | i.disp_reloc[this_operand] = NO_RELOC; |
355afbcd KR |
2658 | i.disp_operands++; |
2659 | save_input_line_pointer = input_line_pointer; | |
2660 | input_line_pointer = displacement_string_start; | |
2661 | END_STRING_AND_SAVE (displacement_string_end); | |
0351b70c ILT |
2662 | #ifndef GCC_ASM_O_HACK |
2663 | #define GCC_ASM_O_HACK 0 | |
2664 | #endif | |
2665 | #if GCC_ASM_O_HACK | |
2666 | END_STRING_AND_SAVE (displacement_string_end + 1); | |
2667 | if ((i.types[this_operand] & BaseIndex) != 0 | |
2668 | && displacement_string_end[-1] == '+') | |
2669 | { | |
2670 | /* This hack is to avoid a warning when using the "o" | |
2671 | constraint within gcc asm statements. | |
2672 | For instance: | |
2673 | ||
2674 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
2675 | __asm__ __volatile__ ( \ | |
2676 | "movw %w2,%0\n\t" \ | |
2677 | "movw %w1,2+%0\n\t" \ | |
2678 | "rorl $16,%1\n\t" \ | |
2679 | "movb %b1,4+%0\n\t" \ | |
2680 | "movb %4,5+%0\n\t" \ | |
2681 | "movb $0,6+%0\n\t" \ | |
2682 | "movb %h1,7+%0\n\t" \ | |
2683 | "rorl $16,%1" \ | |
2684 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
2685 | ||
2686 | This works great except that the output assembler ends | |
2687 | up looking a bit weird if it turns out that there is | |
2688 | no offset. You end up producing code that looks like: | |
2689 | ||
2690 | #APP | |
2691 | movw $235,(%eax) | |
2692 | movw %dx,2+(%eax) | |
2693 | rorl $16,%edx | |
2694 | movb %dl,4+(%eax) | |
2695 | movb $137,5+(%eax) | |
2696 | movb $0,6+(%eax) | |
2697 | movb %dh,7+(%eax) | |
2698 | rorl $16,%edx | |
2699 | #NO_APP | |
2700 | ||
2701 | So here we provide the missing zero. | |
2702 | */ | |
a52f90a4 | 2703 | |
0351b70c ILT |
2704 | *displacement_string_end = '0'; |
2705 | } | |
2706 | #endif | |
30355216 | 2707 | #ifndef LEX_AT |
f0b37b4a KR |
2708 | { |
2709 | /* | |
2710 | * We can have operands of the form | |
2711 | * <symbol>@GOTOFF+<nnn> | |
2712 | * Take the easy way out here and copy everything | |
2713 | * into a temporary buffer... | |
2714 | */ | |
2715 | register char *cp; | |
a52f90a4 ILT |
2716 | |
2717 | cp = strchr (input_line_pointer, '@'); | |
2718 | if (cp != NULL) | |
2719 | { | |
2720 | char *tmpbuf; | |
2721 | ||
2722 | if (GOT_symbol == NULL) | |
2723 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
2724 | ||
2725 | tmpbuf = (char *) alloca ((cp - input_line_pointer) + 20); | |
2726 | ||
2727 | if (strncmp (cp + 1, "PLT", 3) == 0) | |
2728 | { | |
2729 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
2730 | *cp = '\0'; | |
2731 | strcpy (tmpbuf, input_line_pointer); | |
2732 | strcat (tmpbuf, cp + 1 + 3); | |
2733 | *cp = '@'; | |
2734 | } | |
2735 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) | |
2736 | { | |
2737 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; | |
2738 | *cp = '\0'; | |
2739 | strcpy (tmpbuf, input_line_pointer); | |
2740 | strcat (tmpbuf, cp + 1 + 6); | |
2741 | *cp = '@'; | |
2742 | } | |
2743 | else if (strncmp (cp + 1, "GOT", 3) == 0) | |
2744 | { | |
2745 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; | |
2746 | *cp = '\0'; | |
2747 | strcpy (tmpbuf, input_line_pointer); | |
2748 | strcat (tmpbuf, cp + 1 + 3); | |
2749 | *cp = '@'; | |
2750 | } | |
2751 | else | |
48401fcf | 2752 | as_bad (_("Bad reloc specifier `%s' in expression"), cp + 1); |
a52f90a4 | 2753 | |
0351b70c ILT |
2754 | /* GOT relocations are not supported in 16 bit mode */ |
2755 | if (flag_16bit_code) | |
2756 | as_bad (_("GOT relocations not supported in 16 bit mode")); | |
2757 | ||
a52f90a4 ILT |
2758 | input_line_pointer = tmpbuf; |
2759 | } | |
f0b37b4a | 2760 | } |
30355216 | 2761 | #endif |
a52f90a4 | 2762 | |
355afbcd | 2763 | exp_seg = expression (exp); |
f0b37b4a KR |
2764 | |
2765 | #ifdef BFD_ASSEMBLER | |
2766 | /* We do this to make sure that the section symbol is in | |
2767 | the symbol table. We will ultimately change the relocation | |
2768 | to be relative to the beginning of the section */ | |
c54c7aac KR |
2769 | if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF) |
2770 | { | |
2771 | if (S_IS_LOCAL(exp->X_add_symbol) | |
2772 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) | |
2773 | section_symbol(exp->X_add_symbol->bsym->section); | |
2774 | assert (exp->X_op == O_symbol); | |
2775 | exp->X_op = O_subtract; | |
2776 | exp->X_op_symbol = GOT_symbol; | |
2777 | i.disp_reloc[this_operand] = BFD_RELOC_32; | |
2778 | } | |
f0b37b4a KR |
2779 | #endif |
2780 | ||
355afbcd | 2781 | if (*input_line_pointer) |
48401fcf TT |
2782 | as_bad (_("Ignoring junk `%s' after expression"), |
2783 | input_line_pointer); | |
0351b70c ILT |
2784 | #if GCC_ASM_O_HACK |
2785 | RESTORE_END_STRING (displacement_string_end + 1); | |
2786 | #endif | |
355afbcd KR |
2787 | RESTORE_END_STRING (displacement_string_end); |
2788 | input_line_pointer = save_input_line_pointer; | |
73a8be66 ILT |
2789 | |
2790 | #if 0 /* this is handled in expr. */ | |
7b23213f | 2791 | if (exp->X_op == O_absent) |
355afbcd | 2792 | { |
355afbcd | 2793 | /* missing expr becomes absolute 0 */ |
48401fcf | 2794 | as_bad (_("missing or invalid displacement `%s' taken as 0"), |
355afbcd | 2795 | operand_string); |
5ac34ac3 | 2796 | exp->X_op = O_constant; |
355afbcd KR |
2797 | exp->X_add_number = 0; |
2798 | exp->X_add_symbol = (symbolS *) 0; | |
5ac34ac3 | 2799 | exp->X_op_symbol = (symbolS *) 0; |
0351b70c | 2800 | i.types[this_operand] |= Disp8; |
49864cfa | 2801 | } |
aa56747a ILT |
2802 | else |
2803 | #endif | |
2804 | if (exp->X_op == O_constant) | |
49864cfa | 2805 | { |
0351b70c ILT |
2806 | if (fits_in_signed_byte (exp->X_add_number)) |
2807 | i.types[this_operand] |= Disp8; | |
49864cfa | 2808 | } |
0351b70c ILT |
2809 | #ifdef OBJ_AOUT |
2810 | else if (exp_seg != text_section | |
2811 | && exp_seg != data_section | |
2812 | && exp_seg != bss_section | |
2813 | && exp_seg != undefined_section) | |
49864cfa | 2814 | { |
355afbcd KR |
2815 | goto seg_unimplemented; |
2816 | } | |
0351b70c | 2817 | #endif |
355afbcd KR |
2818 | } |
2819 | ||
ec1e6bb8 | 2820 | /* Special case for (%dx) while doing input/output op. */ |
73a8be66 ILT |
2821 | if (i.base_reg |
2822 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) | |
2823 | && i.index_reg == 0 | |
2824 | && i.log2_scale_factor == 0 | |
2825 | && i.seg[i.mem_operands] == 0 | |
2826 | && (i.types[this_operand] & Disp) == 0) | |
355afbcd | 2827 | { |
ec1e6bb8 | 2828 | i.types[this_operand] = InOutPortReg; |
49864cfa KR |
2829 | return 1; |
2830 | } | |
73a8be66 | 2831 | /* Make sure the memory operand we've been dealt is valid. */ |
0351b70c | 2832 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) |
355afbcd | 2833 | { |
0351b70c ILT |
2834 | if ((i.base_reg |
2835 | && ((i.base_reg->reg_type & (Reg16|BaseIndex)) | |
2836 | != (Reg16|BaseIndex))) | |
2837 | || (i.index_reg | |
2838 | && (((i.index_reg->reg_type & (Reg16|BaseIndex)) | |
2839 | != (Reg16|BaseIndex)) | |
2840 | || ! (i.base_reg | |
2841 | && i.base_reg->reg_num < 6 | |
2842 | && i.index_reg->reg_num >= 6 | |
2843 | && i.log2_scale_factor == 0)))) | |
2844 | { | |
2845 | as_bad (_("`%s' is not a valid %s bit base/index expression"), | |
2846 | operand_string, "16"); | |
2847 | return 0; | |
2848 | } | |
2849 | } | |
2850 | else | |
2851 | { | |
2852 | if ((i.base_reg | |
2853 | && (i.base_reg->reg_type & Reg32) == 0) | |
2854 | || (i.index_reg | |
2855 | && ((i.index_reg->reg_type & (Reg32|BaseIndex)) | |
2856 | != (Reg32|BaseIndex)))) | |
2857 | { | |
2858 | as_bad (_("`%s' is not a valid %s bit base/index expression"), | |
2859 | operand_string, "32"); | |
2860 | return 0; | |
2861 | } | |
fecd2382 | 2862 | } |
ec1e6bb8 | 2863 | i.mem_operands++; |
355afbcd KR |
2864 | } |
2865 | else | |
2866 | { /* it's not a memory operand; argh! */ | |
8081c2be | 2867 | as_bad (_("invalid char %s begining operand %d `%s'"), |
aa56747a ILT |
2868 | output_invalid (*op_string), |
2869 | this_operand + 1, | |
355afbcd KR |
2870 | op_string); |
2871 | return 0; | |
2872 | } | |
2873 | return 1; /* normal return */ | |
fecd2382 RP |
2874 | } |
2875 | \f | |
2876 | /* | |
2877 | * md_estimate_size_before_relax() | |
2878 | * | |
2879 | * Called just before relax(). | |
2880 | * Any symbol that is now undefined will not become defined. | |
2881 | * Return the correct fr_subtype in the frag. | |
2882 | * Return the initial "guess for fr_var" to caller. | |
2883 | * The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
2884 | * Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
2885 | * Although it may not be explicit in the frag, pretend fr_var starts with a | |
2886 | * 0 value. | |
2887 | */ | |
2888 | int | |
355afbcd KR |
2889 | md_estimate_size_before_relax (fragP, segment) |
2890 | register fragS *fragP; | |
2891 | register segT segment; | |
fecd2382 | 2892 | { |
355afbcd KR |
2893 | register unsigned char *opcode; |
2894 | register int old_fr_fix; | |
2895 | ||
2896 | old_fr_fix = fragP->fr_fix; | |
2897 | opcode = (unsigned char *) fragP->fr_opcode; | |
73a8be66 ILT |
2898 | /* We've already got fragP->fr_subtype right; all we have to do is |
2899 | check for un-relaxable symbols. */ | |
355afbcd KR |
2900 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) |
2901 | { | |
2902 | /* symbol is undefined in this segment */ | |
0351b70c ILT |
2903 | int code16 = fragP->fr_subtype & CODE16; |
2904 | int size = code16 ? 2 : 4; | |
2905 | int pcrel_reloc = code16 ? BFD_RELOC_16_PCREL : BFD_RELOC_32_PCREL; | |
2906 | ||
355afbcd KR |
2907 | switch (opcode[0]) |
2908 | { | |
2909 | case JUMP_PC_RELATIVE: /* make jmp (0xeb) a dword displacement jump */ | |
2910 | opcode[0] = 0xe9; /* dword disp jmp */ | |
0351b70c ILT |
2911 | fragP->fr_fix += size; |
2912 | fix_new (fragP, old_fr_fix, size, | |
73a8be66 | 2913 | fragP->fr_symbol, |
f0b37b4a KR |
2914 | fragP->fr_offset, 1, |
2915 | (GOT_symbol && /* Not quite right - we should switch on | |
2916 | presence of @PLT, but I cannot see how | |
2917 | to get to that from here. We should have | |
2918 | done this in md_assemble to really | |
2919 | get it right all of the time, but I | |
2920 | think it does not matter that much, as | |
2921 | this will be right most of the time. ERY*/ | |
0351b70c ILT |
2922 | S_GET_SEGMENT(fragP->fr_symbol) == undefined_section) |
2923 | ? BFD_RELOC_386_PLT32 : pcrel_reloc); | |
355afbcd KR |
2924 | break; |
2925 | ||
2926 | default: | |
2927 | /* This changes the byte-displacement jump 0x7N --> | |
a39116f1 | 2928 | the dword-displacement jump 0x0f8N */ |
355afbcd KR |
2929 | opcode[1] = opcode[0] + 0x10; |
2930 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; /* two-byte escape */ | |
0351b70c ILT |
2931 | fragP->fr_fix += 1 + size; /* we've added an opcode byte */ |
2932 | fix_new (fragP, old_fr_fix + 1, size, | |
355afbcd | 2933 | fragP->fr_symbol, |
0351b70c | 2934 | fragP->fr_offset, 1, |
f0b37b4a KR |
2935 | (GOT_symbol && /* Not quite right - we should switch on |
2936 | presence of @PLT, but I cannot see how | |
2937 | to get to that from here. ERY */ | |
0351b70c ILT |
2938 | S_GET_SEGMENT(fragP->fr_symbol) == undefined_section) |
2939 | ? BFD_RELOC_386_PLT32 : pcrel_reloc); | |
355afbcd | 2940 | break; |
a39116f1 | 2941 | } |
355afbcd KR |
2942 | frag_wane (fragP); |
2943 | } | |
2944 | return (fragP->fr_var + fragP->fr_fix - old_fr_fix); | |
fecd2382 RP |
2945 | } /* md_estimate_size_before_relax() */ |
2946 | \f | |
2947 | /* | |
2948 | * md_convert_frag(); | |
2949 | * | |
2950 | * Called after relax() is finished. | |
2951 | * In: Address of frag. | |
2952 | * fr_type == rs_machine_dependent. | |
2953 | * fr_subtype is what the address relaxed to. | |
2954 | * | |
2955 | * Out: Any fixSs and constants are set up. | |
2956 | * Caller will turn frag into a ".space 0". | |
2957 | */ | |
49864cfa | 2958 | #ifndef BFD_ASSEMBLER |
fecd2382 | 2959 | void |
3ea36b53 | 2960 | md_convert_frag (headers, sec, fragP) |
355afbcd | 2961 | object_headers *headers; |
3ea36b53 | 2962 | segT sec; |
355afbcd | 2963 | register fragS *fragP; |
49864cfa KR |
2964 | #else |
2965 | void | |
2966 | md_convert_frag (abfd, sec, fragP) | |
2967 | bfd *abfd; | |
2968 | segT sec; | |
2969 | register fragS *fragP; | |
2970 | #endif | |
fecd2382 | 2971 | { |
355afbcd KR |
2972 | register unsigned char *opcode; |
2973 | unsigned char *where_to_put_displacement = NULL; | |
2974 | unsigned int target_address; | |
2975 | unsigned int opcode_address; | |
2976 | unsigned int extension = 0; | |
2977 | int displacement_from_opcode_start; | |
2978 | ||
2979 | opcode = (unsigned char *) fragP->fr_opcode; | |
2980 | ||
2981 | /* Address we want to reach in file space. */ | |
2982 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
7b23213f KR |
2983 | #ifdef BFD_ASSEMBLER /* not needed otherwise? */ |
2984 | target_address += fragP->fr_symbol->sy_frag->fr_address; | |
2985 | #endif | |
355afbcd KR |
2986 | |
2987 | /* Address opcode resides at in file space. */ | |
2988 | opcode_address = fragP->fr_address + fragP->fr_fix; | |
2989 | ||
2990 | /* Displacement from opcode start to fill into instruction. */ | |
2991 | displacement_from_opcode_start = target_address - opcode_address; | |
2992 | ||
2993 | switch (fragP->fr_subtype) | |
2994 | { | |
0351b70c ILT |
2995 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL): |
2996 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL16): | |
2997 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL): | |
2998 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL16): | |
355afbcd KR |
2999 | /* don't have to change opcode */ |
3000 | extension = 1; /* 1 opcode + 1 displacement */ | |
3001 | where_to_put_displacement = &opcode[1]; | |
3002 | break; | |
3003 | ||
0351b70c ILT |
3004 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
3005 | extension = 5; /* 2 opcode + 4 displacement */ | |
3006 | opcode[1] = opcode[0] + 0x10; | |
3007 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
3008 | where_to_put_displacement = &opcode[2]; | |
355afbcd KR |
3009 | break; |
3010 | ||
0351b70c ILT |
3011 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): |
3012 | extension = 4; /* 1 opcode + 4 displacement */ | |
3013 | opcode[0] = 0xe9; | |
3014 | where_to_put_displacement = &opcode[1]; | |
355afbcd KR |
3015 | break; |
3016 | ||
0351b70c ILT |
3017 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
3018 | extension = 3; /* 2 opcode + 2 displacement */ | |
355afbcd KR |
3019 | opcode[1] = opcode[0] + 0x10; |
3020 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
355afbcd KR |
3021 | where_to_put_displacement = &opcode[2]; |
3022 | break; | |
3023 | ||
0351b70c ILT |
3024 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
3025 | extension = 2; /* 1 opcode + 2 displacement */ | |
355afbcd | 3026 | opcode[0] = 0xe9; |
355afbcd KR |
3027 | where_to_put_displacement = &opcode[1]; |
3028 | break; | |
3029 | ||
3030 | default: | |
3031 | BAD_CASE (fragP->fr_subtype); | |
3032 | break; | |
3033 | } | |
3034 | /* now put displacement after opcode */ | |
3035 | md_number_to_chars ((char *) where_to_put_displacement, | |
ad660eb1 | 3036 | (valueT) (displacement_from_opcode_start - extension), |
355afbcd KR |
3037 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
3038 | fragP->fr_fix += extension; | |
fecd2382 | 3039 | } |
fecd2382 | 3040 | \f |
355afbcd | 3041 | |
fecd2382 | 3042 | int md_short_jump_size = 2; /* size of byte displacement jmp */ |
355afbcd | 3043 | int md_long_jump_size = 5; /* size of dword displacement jmp */ |
49864cfa | 3044 | const int md_reloc_size = 8; /* Size of relocation record */ |
fecd2382 | 3045 | |
355afbcd KR |
3046 | void |
3047 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
3048 | char *ptr; | |
025b0302 | 3049 | addressT from_addr, to_addr; |
355afbcd KR |
3050 | fragS *frag; |
3051 | symbolS *to_symbol; | |
fecd2382 | 3052 | { |
355afbcd KR |
3053 | long offset; |
3054 | ||
3055 | offset = to_addr - (from_addr + 2); | |
ad660eb1 ILT |
3056 | md_number_to_chars (ptr, (valueT) 0xeb, 1); /* opcode for byte-disp jump */ |
3057 | md_number_to_chars (ptr + 1, (valueT) offset, 1); | |
fecd2382 RP |
3058 | } |
3059 | ||
355afbcd KR |
3060 | void |
3061 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
3062 | char *ptr; | |
025b0302 | 3063 | addressT from_addr, to_addr; |
355afbcd KR |
3064 | fragS *frag; |
3065 | symbolS *to_symbol; | |
fecd2382 | 3066 | { |
355afbcd KR |
3067 | long offset; |
3068 | ||
ade614d5 | 3069 | if (flag_do_long_jump) |
355afbcd KR |
3070 | { |
3071 | offset = to_addr - S_GET_VALUE (to_symbol); | |
ad660eb1 ILT |
3072 | md_number_to_chars (ptr, (valueT) 0xe9, 1);/* opcode for long jmp */ |
3073 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
355afbcd | 3074 | fix_new (frag, (ptr + 1) - frag->fr_literal, 4, |
7b23213f | 3075 | to_symbol, (offsetT) 0, 0, BFD_RELOC_32); |
355afbcd KR |
3076 | } |
3077 | else | |
3078 | { | |
3079 | offset = to_addr - (from_addr + 5); | |
ad660eb1 ILT |
3080 | md_number_to_chars (ptr, (valueT) 0xe9, 1); |
3081 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
355afbcd | 3082 | } |
fecd2382 RP |
3083 | } |
3084 | \f | |
fecd2382 | 3085 | /* Apply a fixup (fixS) to segment data, once it has been determined |
355afbcd KR |
3086 | by our caller that we have all the info we need to fix it up. |
3087 | ||
fecd2382 RP |
3088 | On the 386, immediates, displacements, and data pointers are all in |
3089 | the same (little-endian) format, so we don't need to care about which | |
3090 | we are handling. */ | |
3091 | ||
3ea36b53 ILT |
3092 | int |
3093 | md_apply_fix3 (fixP, valp, seg) | |
3094 | fixS *fixP; /* The fix we're to put in. */ | |
3095 | valueT *valp; /* Pointer to the value of the bits. */ | |
3096 | segT seg; /* Segment fix is from. */ | |
fecd2382 | 3097 | { |
355afbcd | 3098 | register char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
3ea36b53 | 3099 | valueT value = *valp; |
355afbcd | 3100 | |
388fa5c6 ILT |
3101 | if (fixP->fx_r_type == BFD_RELOC_32 && fixP->fx_pcrel) |
3102 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
3103 | ||
f3d817d8 | 3104 | #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) |
7b23213f KR |
3105 | /* |
3106 | * This is a hack. There should be a better way to | |
3107 | * handle this. | |
3108 | */ | |
3109 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL && fixP->fx_addsy) | |
3110 | { | |
0b476c53 | 3111 | #ifndef OBJ_AOUT |
76fb6d2f | 3112 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
f5003e7d ILT |
3113 | #ifdef TE_PE |
3114 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3115 | #endif | |
3116 | ) | |
590c50d8 | 3117 | value += fixP->fx_where + fixP->fx_frag->fr_address; |
0b476c53 | 3118 | #endif |
590c50d8 ILT |
3119 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3120 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
3121 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg | |
ec1e6bb8 ILT |
3122 | || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0) |
3123 | && ! S_IS_EXTERNAL (fixP->fx_addsy) | |
3124 | && ! S_IS_WEAK (fixP->fx_addsy) | |
3125 | && S_IS_DEFINED (fixP->fx_addsy) | |
3126 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
f3d817d8 DM |
3127 | { |
3128 | /* Yes, we add the values in twice. This is because | |
3129 | bfd_perform_relocation subtracts them out again. I think | |
3130 | bfd_perform_relocation is broken, but I don't dare change | |
3131 | it. FIXME. */ | |
3132 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
3133 | } | |
76fb6d2f ILT |
3134 | #endif |
3135 | #if defined (OBJ_COFF) && defined (TE_PE) | |
3136 | /* For some reason, the PE format does not store a section | |
3137 | address offset for a PC relative symbol. */ | |
3138 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
3139 | value += md_pcrel_from (fixP); | |
7b23213f | 3140 | #endif |
355afbcd | 3141 | } |
f0b37b4a KR |
3142 | |
3143 | /* Fix a few things - the dynamic linker expects certain values here, | |
3144 | and we must not dissappoint it. */ | |
590c50d8 ILT |
3145 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3146 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
3147 | && fixP->fx_addsy) | |
0351b70c | 3148 | switch (fixP->fx_r_type) { |
f0b37b4a KR |
3149 | case BFD_RELOC_386_PLT32: |
3150 | /* Make the jump instruction point to the address of the operand. At | |
3151 | runtime we merely add the offset to the actual PLT entry. */ | |
3152 | value = 0xfffffffc; | |
3153 | break; | |
3154 | case BFD_RELOC_386_GOTPC: | |
3155 | /* | |
3156 | * This is tough to explain. We end up with this one if we have | |
3157 | * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal | |
3158 | * here is to obtain the absolute address of the GOT, and it is strongly | |
3159 | * preferable from a performance point of view to avoid using a runtime | |
3160 | * relocation for this. The actual sequence of instructions often look | |
3161 | * something like: | |
3162 | * | |
3163 | * call .L66 | |
3164 | * .L66: | |
3165 | * popl %ebx | |
3166 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
3167 | * | |
3168 | * The call and pop essentially return the absolute address of | |
3169 | * the label .L66 and store it in %ebx. The linker itself will | |
3170 | * ultimately change the first operand of the addl so that %ebx points to | |
3171 | * the GOT, but to keep things simple, the .o file must have this operand | |
3172 | * set so that it generates not the absolute address of .L66, but the | |
3173 | * absolute address of itself. This allows the linker itself simply | |
3174 | * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be | |
3175 | * added in, and the addend of the relocation is stored in the operand | |
3176 | * field for the instruction itself. | |
3177 | * | |
3178 | * Our job here is to fix the operand so that it would add the correct | |
3179 | * offset so that %ebx would point to itself. The thing that is tricky is | |
3180 | * that .-.L66 will point to the beginning of the instruction, so we need | |
3181 | * to further modify the operand so that it will point to itself. | |
3182 | * There are other cases where you have something like: | |
3183 | * | |
3184 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
3185 | * | |
3186 | * and here no correction would be required. Internally in the assembler | |
3187 | * we treat operands of this form as not being pcrel since the '.' is | |
3188 | * explicitly mentioned, and I wonder whether it would simplify matters | |
3189 | * to do it this way. Who knows. In earlier versions of the PIC patches, | |
3190 | * the pcrel_adjust field was used to store the correction, but since the | |
3191 | * expression is not pcrel, I felt it would be confusing to do it this way. | |
3192 | */ | |
c54c7aac | 3193 | value -= 1; |
f0b37b4a KR |
3194 | break; |
3195 | case BFD_RELOC_386_GOT32: | |
3196 | value = 0; /* Fully resolved at runtime. No addend. */ | |
c54c7aac | 3197 | break; |
f0b37b4a | 3198 | case BFD_RELOC_386_GOTOFF: |
c54c7aac KR |
3199 | break; |
3200 | ||
a1624e3f RH |
3201 | case BFD_RELOC_VTABLE_INHERIT: |
3202 | case BFD_RELOC_VTABLE_ENTRY: | |
3203 | fixP->fx_done = 0; | |
3204 | return 1; | |
3205 | ||
f0b37b4a KR |
3206 | default: |
3207 | break; | |
3208 | } | |
3209 | #endif | |
3210 | ||
f3d817d8 DM |
3211 | #endif |
3212 | md_number_to_chars (p, value, fixP->fx_size); | |
fecd2382 | 3213 | |
49864cfa KR |
3214 | return 1; |
3215 | } | |
49864cfa | 3216 | |
ad660eb1 ILT |
3217 | #if 0 |
3218 | /* This is never used. */ | |
355afbcd KR |
3219 | long /* Knows about the byte order in a word. */ |
3220 | md_chars_to_number (con, nbytes) | |
3221 | unsigned char con[]; /* Low order byte 1st. */ | |
3222 | int nbytes; /* Number of bytes in the input. */ | |
fecd2382 | 3223 | { |
355afbcd KR |
3224 | long retval; |
3225 | for (retval = 0, con += nbytes - 1; nbytes--; con--) | |
3226 | { | |
3227 | retval <<= BITS_PER_CHAR; | |
3228 | retval |= *con; | |
3229 | } | |
3230 | return retval; | |
fecd2382 | 3231 | } |
ad660eb1 | 3232 | #endif /* 0 */ |
fecd2382 | 3233 | \f |
355afbcd | 3234 | |
fecd2382 RP |
3235 | #define MAX_LITTLENUMS 6 |
3236 | ||
3237 | /* Turn the string pointed to by litP into a floating point constant of type | |
3238 | type, and emit the appropriate bytes. The number of LITTLENUMS emitted | |
3c8df4ba | 3239 | is stored in *sizeP . An error message is returned, or NULL on OK. */ |
fecd2382 | 3240 | char * |
355afbcd KR |
3241 | md_atof (type, litP, sizeP) |
3242 | char type; | |
3243 | char *litP; | |
3244 | int *sizeP; | |
fecd2382 | 3245 | { |
355afbcd KR |
3246 | int prec; |
3247 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
3248 | LITTLENUM_TYPE *wordP; | |
3249 | char *t; | |
3250 | ||
3251 | switch (type) | |
3252 | { | |
3253 | case 'f': | |
3254 | case 'F': | |
3255 | prec = 2; | |
3256 | break; | |
3257 | ||
3258 | case 'd': | |
3259 | case 'D': | |
3260 | prec = 4; | |
3261 | break; | |
3262 | ||
3263 | case 'x': | |
3264 | case 'X': | |
3265 | prec = 5; | |
3266 | break; | |
3267 | ||
3268 | default: | |
3269 | *sizeP = 0; | |
48401fcf | 3270 | return _("Bad call to md_atof ()"); |
355afbcd KR |
3271 | } |
3272 | t = atof_ieee (input_line_pointer, type, words); | |
3273 | if (t) | |
3274 | input_line_pointer = t; | |
3275 | ||
3276 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
3c8df4ba KR |
3277 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with |
3278 | the bigendian 386. */ | |
355afbcd KR |
3279 | for (wordP = words + prec - 1; prec--;) |
3280 | { | |
ad660eb1 | 3281 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); |
355afbcd KR |
3282 | litP += sizeof (LITTLENUM_TYPE); |
3283 | } | |
49864cfa | 3284 | return 0; |
fecd2382 RP |
3285 | } |
3286 | \f | |
3287 | char output_invalid_buf[8]; | |
3288 | ||
355afbcd KR |
3289 | static char * |
3290 | output_invalid (c) | |
3291 | char c; | |
fecd2382 | 3292 | { |
355afbcd KR |
3293 | if (isprint (c)) |
3294 | sprintf (output_invalid_buf, "'%c'", c); | |
3295 | else | |
3296 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
3297 | return output_invalid_buf; | |
fecd2382 RP |
3298 | } |
3299 | ||
4edc93e9 ILT |
3300 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
3301 | ||
0351b70c | 3302 | static const reg_entry * |
4edc93e9 ILT |
3303 | parse_register (reg_string, end_op) |
3304 | char *reg_string; | |
3305 | char **end_op; | |
fecd2382 | 3306 | { |
4edc93e9 | 3307 | register char *s = reg_string; |
355afbcd | 3308 | register char *p; |
4edc93e9 ILT |
3309 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
3310 | const reg_entry *r; | |
3311 | ||
3312 | /* Skip REGISTER_PREFIX and possible whitespace. */ | |
3313 | ++s; | |
3314 | if (is_space_char (*s)) | |
3315 | ++s; | |
355afbcd | 3316 | |
0351b70c ILT |
3317 | p = reg_name_given; |
3318 | while ((*p++ = register_chars[(unsigned char) *s++]) != '\0') | |
355afbcd | 3319 | { |
355afbcd | 3320 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) |
4edc93e9 ILT |
3321 | { |
3322 | *p = '\0'; | |
3323 | as_bad (_("bad register name `%s'"), reg_name_given); | |
3324 | return (const reg_entry *) NULL; | |
3325 | } | |
355afbcd | 3326 | } |
4edc93e9 ILT |
3327 | |
3328 | *end_op = s - 1; | |
3329 | ||
3330 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
3331 | ||
3332 | if (r == NULL) | |
3333 | { | |
3334 | as_bad (_("bad register name `%s'"), reg_name_given); | |
3335 | return (const reg_entry *) NULL; | |
3336 | } | |
3337 | ||
3338 | return r; | |
fecd2382 | 3339 | } |
f3d817d8 | 3340 | \f |
ade614d5 | 3341 | #ifdef OBJ_ELF |
3ea36b53 | 3342 | CONST char *md_shortopts = "kmVQ:"; |
ade614d5 KR |
3343 | #else |
3344 | CONST char *md_shortopts = "m"; | |
3345 | #endif | |
f3d817d8 DM |
3346 | struct option md_longopts[] = { |
3347 | {NULL, no_argument, NULL, 0} | |
3348 | }; | |
0351b70c | 3349 | size_t md_longopts_size = sizeof (md_longopts); |
fecd2382 | 3350 | |
f3d817d8 DM |
3351 | int |
3352 | md_parse_option (c, arg) | |
3353 | int c; | |
3354 | char *arg; | |
3355 | { | |
ade614d5 KR |
3356 | switch (c) |
3357 | { | |
3358 | case 'm': | |
3359 | flag_do_long_jump = 1; | |
3360 | break; | |
3361 | ||
590c50d8 | 3362 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3ea36b53 ILT |
3363 | /* -k: Ignore for FreeBSD compatibility. */ |
3364 | case 'k': | |
3365 | break; | |
3366 | ||
ade614d5 KR |
3367 | /* -V: SVR4 argument to print version ID. */ |
3368 | case 'V': | |
3369 | print_version_id (); | |
3370 | break; | |
3371 | ||
3372 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
3373 | should be emitted or not. FIXME: Not implemented. */ | |
3374 | case 'Q': | |
3375 | break; | |
3376 | #endif | |
3377 | ||
3378 | default: | |
3379 | return 0; | |
3380 | } | |
3381 | return 1; | |
f3d817d8 | 3382 | } |
fecd2382 | 3383 | |
f3d817d8 DM |
3384 | void |
3385 | md_show_usage (stream) | |
3386 | FILE *stream; | |
3387 | { | |
48401fcf TT |
3388 | fprintf (stream, _("\ |
3389 | -m do long jump\n")); | |
f3d817d8 | 3390 | } |
fecd2382 | 3391 | |
590c50d8 ILT |
3392 | #ifdef BFD_ASSEMBLER |
3393 | #ifdef OBJ_MAYBE_ELF | |
3394 | #ifdef OBJ_MAYBE_COFF | |
3395 | ||
3396 | /* Pick the target format to use. */ | |
3397 | ||
3398 | const char * | |
3399 | i386_target_format () | |
3400 | { | |
3401 | switch (OUTPUT_FLAVOR) | |
3402 | { | |
3403 | case bfd_target_coff_flavour: | |
3404 | return "coff-i386"; | |
3405 | case bfd_target_elf_flavour: | |
3406 | return "elf32-i386"; | |
3407 | default: | |
3408 | abort (); | |
3409 | return NULL; | |
3410 | } | |
3411 | } | |
3412 | ||
3413 | #endif /* OBJ_MAYBE_COFF */ | |
3414 | #endif /* OBJ_MAYBE_ELF */ | |
3415 | #endif /* BFD_ASSEMBLER */ | |
3416 | \f | |
fecd2382 RP |
3417 | /* ARGSUSED */ |
3418 | symbolS * | |
355afbcd KR |
3419 | md_undefined_symbol (name) |
3420 | char *name; | |
fecd2382 | 3421 | { |
f0b37b4a KR |
3422 | if (*name == '_' && *(name+1) == 'G' |
3423 | && strcmp(name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
3424 | { | |
0351b70c | 3425 | if (!GOT_symbol) |
f0b37b4a | 3426 | { |
0351b70c | 3427 | if (symbol_find (name)) |
aa56747a | 3428 | as_bad (_("GOT already in symbol table")); |
0351b70c | 3429 | GOT_symbol = symbol_new (name, undefined_section, |
f0b37b4a KR |
3430 | (valueT) 0, &zero_address_frag); |
3431 | }; | |
3432 | return GOT_symbol; | |
3433 | } | |
355afbcd | 3434 | return 0; |
fecd2382 RP |
3435 | } |
3436 | ||
fecd2382 | 3437 | /* Round up a section size to the appropriate boundary. */ |
3c8df4ba | 3438 | valueT |
355afbcd KR |
3439 | md_section_align (segment, size) |
3440 | segT segment; | |
3c8df4ba | 3441 | valueT size; |
fecd2382 | 3442 | { |
91951af6 ILT |
3443 | #ifdef OBJ_AOUT |
3444 | #ifdef BFD_ASSEMBLER | |
3445 | /* For a.out, force the section size to be aligned. If we don't do | |
3446 | this, BFD will align it for us, but it will not write out the | |
3447 | final bytes of the section. This may be a bug in BFD, but it is | |
3448 | easier to fix it here since that is how the other a.out targets | |
3449 | work. */ | |
3450 | int align; | |
3451 | ||
3452 | align = bfd_get_section_alignment (stdoutput, segment); | |
3453 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
3454 | #endif | |
3455 | #endif | |
3456 | ||
3457 | return size; | |
fecd2382 RP |
3458 | } |
3459 | ||
4edc93e9 ILT |
3460 | /* On the i386, PC-relative offsets are relative to the start of the |
3461 | next instruction. That is, the address of the offset, plus its | |
3462 | size, since the offset is always the last part of the insn. */ | |
3463 | ||
fecd2382 | 3464 | long |
355afbcd KR |
3465 | md_pcrel_from (fixP) |
3466 | fixS *fixP; | |
fecd2382 | 3467 | { |
355afbcd | 3468 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
fecd2382 RP |
3469 | } |
3470 | ||
49864cfa | 3471 | #ifndef I386COFF |
542e1629 | 3472 | |
49864cfa | 3473 | static void |
ad660eb1 ILT |
3474 | s_bss (ignore) |
3475 | int ignore; | |
542e1629 | 3476 | { |
49864cfa | 3477 | register int temp; |
542e1629 | 3478 | |
49864cfa | 3479 | temp = get_absolute_expression (); |
49864cfa | 3480 | subseg_set (bss_section, (subsegT) temp); |
49864cfa KR |
3481 | demand_empty_rest_of_line (); |
3482 | } | |
542e1629 | 3483 | |
49864cfa | 3484 | #endif |
355afbcd | 3485 | |
542e1629 | 3486 | |
49864cfa | 3487 | #ifdef BFD_ASSEMBLER |
c54c7aac KR |
3488 | |
3489 | void | |
3490 | i386_validate_fix (fixp) | |
3491 | fixS *fixp; | |
3492 | { | |
3493 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
3494 | { | |
3495 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
3496 | fixp->fx_subsy = 0; | |
3497 | } | |
3498 | } | |
3499 | ||
f0b37b4a KR |
3500 | #define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) |
3501 | #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break | |
542e1629 | 3502 | |
49864cfa KR |
3503 | arelent * |
3504 | tc_gen_reloc (section, fixp) | |
3505 | asection *section; | |
3506 | fixS *fixp; | |
542e1629 | 3507 | { |
ad660eb1 | 3508 | arelent *rel; |
49864cfa | 3509 | bfd_reloc_code_real_type code; |
542e1629 | 3510 | |
73a8be66 | 3511 | switch (fixp->fx_r_type) |
49864cfa | 3512 | { |
f0b37b4a KR |
3513 | case BFD_RELOC_386_PLT32: |
3514 | case BFD_RELOC_386_GOT32: | |
3515 | case BFD_RELOC_386_GOTOFF: | |
3516 | case BFD_RELOC_386_GOTPC: | |
a52f90a4 | 3517 | case BFD_RELOC_RVA: |
a1624e3f RH |
3518 | case BFD_RELOC_VTABLE_ENTRY: |
3519 | case BFD_RELOC_VTABLE_INHERIT: | |
f0b37b4a KR |
3520 | code = fixp->fx_r_type; |
3521 | break; | |
3522 | default: | |
3523 | switch (F (fixp->fx_size, fixp->fx_pcrel)) | |
3524 | { | |
f0b37b4a KR |
3525 | MAP (1, 0, BFD_RELOC_8); |
3526 | MAP (2, 0, BFD_RELOC_16); | |
f0b37b4a | 3527 | MAP (4, 0, BFD_RELOC_32); |
f0b37b4a KR |
3528 | MAP (1, 1, BFD_RELOC_8_PCREL); |
3529 | MAP (2, 1, BFD_RELOC_16_PCREL); | |
f0b37b4a KR |
3530 | MAP (4, 1, BFD_RELOC_32_PCREL); |
3531 | default: | |
48401fcf TT |
3532 | if (fixp->fx_pcrel) |
3533 | as_bad (_("Can not do %d byte pc-relative relocation"), | |
3534 | fixp->fx_size); | |
3535 | else | |
3536 | as_bad (_("Can not do %d byte relocation"), fixp->fx_size); | |
73a8be66 ILT |
3537 | code = BFD_RELOC_32; |
3538 | break; | |
f0b37b4a | 3539 | } |
73a8be66 | 3540 | break; |
49864cfa | 3541 | } |
3c8df4ba KR |
3542 | #undef MAP |
3543 | #undef F | |
542e1629 | 3544 | |
f0b37b4a KR |
3545 | if (code == BFD_RELOC_32 |
3546 | && GOT_symbol | |
3547 | && fixp->fx_addsy == GOT_symbol) | |
3548 | code = BFD_RELOC_386_GOTPC; | |
3549 | ||
590c50d8 | 3550 | rel = (arelent *) xmalloc (sizeof (arelent)); |
ad660eb1 | 3551 | rel->sym_ptr_ptr = &fixp->fx_addsy->bsym; |
a1624e3f | 3552 | |
ad660eb1 | 3553 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; |
a1624e3f RH |
3554 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the |
3555 | vtable entry to be used in the relocation's section offset. */ | |
3556 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3557 | rel->address = fixp->fx_offset; | |
3558 | ||
49864cfa | 3559 | if (fixp->fx_pcrel) |
ad660eb1 | 3560 | rel->addend = fixp->fx_addnumber; |
49864cfa | 3561 | else |
ad660eb1 | 3562 | rel->addend = 0; |
355afbcd | 3563 | |
ad660eb1 | 3564 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
e592f0e6 | 3565 | if (rel->howto == NULL) |
ad660eb1 | 3566 | { |
e592f0e6 | 3567 | as_bad_where (fixp->fx_file, fixp->fx_line, |
48401fcf | 3568 | _("Cannot represent relocation type %s"), |
e592f0e6 ILT |
3569 | bfd_get_reloc_code_name (code)); |
3570 | /* Set howto to a garbage value so that we can keep going. */ | |
3571 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
3572 | assert (rel->howto != NULL); | |
ad660eb1 | 3573 | } |
49864cfa | 3574 | |
ad660eb1 | 3575 | return rel; |
49864cfa KR |
3576 | } |
3577 | ||
3578 | #else /* ! BFD_ASSEMBLER */ | |
3579 | ||
3580 | #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) | |
3581 | void | |
3582 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) | |
3583 | char *where; | |
3584 | fixS *fixP; | |
3585 | relax_addressT segment_address_in_file; | |
4b77b129 | 3586 | { |
49864cfa KR |
3587 | /* |
3588 | * In: length of relocation (or of address) in chars: 1, 2 or 4. | |
3589 | * Out: GNU LD relocation length code: 0, 1, or 2. | |
3590 | */ | |
4b77b129 | 3591 | |
3c8df4ba | 3592 | static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; |
49864cfa KR |
3593 | long r_symbolnum; |
3594 | ||
3595 | know (fixP->fx_addsy != NULL); | |
3596 | ||
3597 | md_number_to_chars (where, | |
ad660eb1 ILT |
3598 | (valueT) (fixP->fx_frag->fr_address |
3599 | + fixP->fx_where - segment_address_in_file), | |
49864cfa KR |
3600 | 4); |
3601 | ||
3602 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) | |
3603 | ? S_GET_TYPE (fixP->fx_addsy) | |
3604 | : fixP->fx_addsy->sy_number); | |
3605 | ||
3606 | where[6] = (r_symbolnum >> 16) & 0x0ff; | |
3607 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
3608 | where[4] = r_symbolnum & 0x0ff; | |
3609 | where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) | |
3610 | | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) | |
3611 | | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); | |
4b77b129 | 3612 | } |
355afbcd | 3613 | |
49864cfa | 3614 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
4b77b129 | 3615 | |
49864cfa | 3616 | #if defined (I386COFF) |
4b77b129 | 3617 | |
355afbcd KR |
3618 | short |
3619 | tc_coff_fix2rtype (fixP) | |
3620 | fixS *fixP; | |
4b77b129 | 3621 | { |
3ea36b53 ILT |
3622 | if (fixP->fx_r_type == R_IMAGEBASE) |
3623 | return R_IMAGEBASE; | |
3624 | ||
355afbcd KR |
3625 | return (fixP->fx_pcrel ? |
3626 | (fixP->fx_size == 1 ? R_PCRBYTE : | |
3627 | fixP->fx_size == 2 ? R_PCRWORD : | |
3628 | R_PCRLONG) : | |
3629 | (fixP->fx_size == 1 ? R_RELBYTE : | |
3630 | fixP->fx_size == 2 ? R_RELWORD : | |
3631 | R_DIR32)); | |
4b77b129 ILT |
3632 | } |
3633 | ||
49864cfa KR |
3634 | int |
3635 | tc_coff_sizemachdep (frag) | |
3636 | fragS *frag; | |
3637 | { | |
3638 | if (frag->fr_next) | |
3639 | return (frag->fr_next->fr_address - frag->fr_address); | |
3640 | else | |
3641 | return 0; | |
3642 | } | |
3643 | ||
3644 | #endif /* I386COFF */ | |
3645 | ||
3646 | #endif /* BFD_ASSEMBLER? */ | |
3ea36b53 | 3647 | \f |
fecd2382 | 3648 | /* end of tc-i386.c */ |