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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
219d1afa 2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
83b16ac6 176static const insn_template *match_template (char);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
a65babc9
L		 284 };
285
252b5132
RH		 286struct _i386_insn
287 {
47926f60 288 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 289 insn_template tm;
252b5132 290
7d5e4556
L		 291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
252b5132
RH		 293 char suffix;
294
47926f60 295 /* OPERANDS gives the number of given operands. */
252b5132
RH		 296 unsigned int operands;
297
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
47926f60 300 operands. */
252b5132
RH		 301 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
302
303 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 304 use OP[i] for the corresponding operand. */
40fb9820 305 i386_operand_type types[MAX_OPERANDS];
252b5132 306
520dc8e8
AM		 307 /* Displacement expression, immediate expression, or register for each
308 operand. */
309 union i386_op op[MAX_OPERANDS];
252b5132 310
3e73aa7c
JH		 311 /* Flags for operands. */
312 unsigned int flags[MAX_OPERANDS];
313#define Operand_PCrel 1
314
252b5132 315 /* Relocation type for operand */
f86103b7 316 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 317
252b5132
RH		 318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry *base_reg;
321 const reg_entry *index_reg;
322 unsigned int log2_scale_factor;
323
324 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 325 explicit segment overrides are given. */
ce8a8b2f 326 const seg_entry *seg[2];
252b5132 327
8325cc63
JB		 328 /* Copied first memory operand string, for re-checking. */
329 char *memop1_string;
330
252b5132
RH		 331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes;
334 unsigned char prefix[MAX_PREFIXES];
335
336 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 337 addressing modes of this insn are encoded. */
252b5132 338 modrm_byte rm;
3e73aa7c 339 rex_byte rex;
43234a1e 340 rex_byte vrex;
252b5132 341 sib_byte sib;
c0f3af97 342 vex_prefix vex;
b6169b20 343
43234a1e
L		 344 /* Masking attributes. */
345 struct Mask_Operation *mask;
346
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation *rounding;
349
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation *broadcast;
352
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift;
355
86fa6981
L		 356 /* Prefer load or store in encoding. */
357 enum
358 {
359 dir_encoding_default = 0,
360 dir_encoding_load,
361 dir_encoding_store
362 } dir_encoding;
891edac4 363
a501d77e
L		 364 /* Prefer 8bit or 32bit displacement in encoding. */
365 enum
366 {
367 disp_encoding_default = 0,
368 disp_encoding_8bit,
369 disp_encoding_32bit
370 } disp_encoding;
f8a5c266 371
86fa6981
L		 372 /* How to encode vector instructions. */
373 enum
374 {
375 vex_encoding_default = 0,
376 vex_encoding_vex2,
377 vex_encoding_vex3,
378 vex_encoding_evex
379 } vec_encoding;
380
d5de92cf
L		 381 /* REP prefix. */
382 const char *rep_prefix;
383
165de32a
L		 384 /* HLE prefix. */
385 const char *hle_prefix;
42164a71 386
7e8b059b
L		 387 /* Have BND prefix. */
388 const char *bnd_prefix;
389
04ef582a
L		 390 /* Have NOTRACK prefix. */
391 const char *notrack_prefix;
392
891edac4 393 /* Error message. */
a65babc9 394 enum i386_error error;
252b5132
RH		 395 };
396
397typedef struct _i386_insn i386_insn;
398
43234a1e
L		 399/* Link RC type with corresponding string, that'll be looked for in
400 asm. */
401struct RC_name
402{
403 enum rc_type type;
404 const char *name;
405 unsigned int len;
406};
407
408static const struct RC_name RC_NamesTable[] =
409{
410 { rne, STRING_COMMA_LEN ("rn-sae") },
411 { rd, STRING_COMMA_LEN ("rd-sae") },
412 { ru, STRING_COMMA_LEN ("ru-sae") },
413 { rz, STRING_COMMA_LEN ("rz-sae") },
414 { saeonly, STRING_COMMA_LEN ("sae") },
415};
416
252b5132
RH		 417/* List of chars besides those in app.c:symbol_chars that can start an
418 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 419const char extra_symbol_chars[] = "*%-([{}"
252b5132 420#ifdef LEX_AT
32137342
NC		 421 "@"
422#endif
423#ifdef LEX_QM
424 "?"
252b5132 425#endif
32137342 426 ;
252b5132 427
29b0f896
AM		 428#if (defined (TE_I386AIX) \
429 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 430 && !defined (TE_GNU) \
29b0f896 431 && !defined (TE_LINUX) \
8d63c93e
RM		 432 && !defined (TE_NACL) \
433 && !defined (TE_NETWARE) \
29b0f896 434 && !defined (TE_FreeBSD) \
5b806d27 435 && !defined (TE_DragonFly) \
29b0f896 436 && !defined (TE_NetBSD)))
252b5132 437/* This array holds the chars that always start a comment. If the
b3b91714
AM		 438 pre-processor is disabled, these aren't very useful. The option
439 --divide will remove '/' from this list. */
440const char *i386_comment_chars = "#/";
441#define SVR4_COMMENT_CHARS 1
252b5132 442#define PREFIX_SEPARATOR '\\'
252b5132 443
b3b91714
AM		 444#else
445const char *i386_comment_chars = "#";
446#define PREFIX_SEPARATOR '/'
447#endif
448
252b5132
RH		 449/* This array holds the chars that only start a comment at the beginning of
450 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 451 .line and .file directives will appear in the pre-processed output.
452 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 453 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 454 #NO_APP at the beginning of its output.
455 Also note that comments started like this one will always work if
252b5132 456 '/' isn't otherwise defined. */
b3b91714 457const char line_comment_chars[] = "#/";
252b5132 458
63a0b638 459const char line_separator_chars[] = ";";
252b5132 460
ce8a8b2f
AM		 461/* Chars that can be used to separate mant from exp in floating point
462 nums. */
252b5132
RH		 463const char EXP_CHARS[] = "eE";
464
ce8a8b2f
AM		 465/* Chars that mean this number is a floating point constant
466 As in 0f12.456
467 or 0d1.2345e12. */
252b5132
RH		 468const char FLT_CHARS[] = "fFdDxX";
469
ce8a8b2f 470/* Tables for lexical analysis. */
252b5132
RH		 471static char mnemonic_chars[256];
472static char register_chars[256];
473static char operand_chars[256];
474static char identifier_chars[256];
475static char digit_chars[256];
476
ce8a8b2f 477/* Lexical macros. */
252b5132
RH		 478#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
479#define is_operand_char(x) (operand_chars[(unsigned char) x])
480#define is_register_char(x) (register_chars[(unsigned char) x])
481#define is_space_char(x) ((x) == ' ')
482#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
483#define is_digit_char(x) (digit_chars[(unsigned char) x])
484
0234cb7c 485/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 486static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
487
488/* md_assemble() always leaves the strings it's passed unaltered. To
489 effect this we maintain a stack of saved characters that we've smashed
490 with '\0's (indicating end of strings for various sub-fields of the
47926f60 491 assembler instruction). */
252b5132 492static char save_stack[32];
ce8a8b2f 493static char *save_stack_p;
252b5132
RH		 494#define END_STRING_AND_SAVE(s) \
495 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
496#define RESTORE_END_STRING(s) \
497 do { *(s) = *--save_stack_p; } while (0)
498
47926f60 499/* The instruction we're assembling. */
252b5132
RH		 500static i386_insn i;
501
502/* Possible templates for current insn. */
503static const templates *current_templates;
504
31b2323c
L		 505/* Per instruction expressionS buffers: max displacements & immediates. */
506static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
507static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 508
47926f60 509/* Current operand we are working on. */
ee86248c 510static int this_operand = -1;
252b5132 511
3e73aa7c
JH		 512/* We support four different modes. FLAG_CODE variable is used to distinguish
513 these. */
514
515enum flag_code {
516 CODE_32BIT,
517 CODE_16BIT,
518 CODE_64BIT };
519
520static enum flag_code flag_code;
4fa24527 521static unsigned int object_64bit;
862be3fb 522static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 523static int use_rela_relocations = 0;
524
7af8ed2d
NC		 525#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
526 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
527 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
528
351f65ca
L		 529/* The ELF ABI to use. */
530enum x86_elf_abi
531{
532 I386_ABI,
7f56bc95
L		 533 X86_64_ABI,
534 X86_64_X32_ABI
351f65ca
L		 535};
536
537static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 538#endif
351f65ca 539
167ad85b
TG		 540#if defined (TE_PE) || defined (TE_PEP)
541/* Use big object file format. */
542static int use_big_obj = 0;
543#endif
544
8dcea932
L		 545#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
546/* 1 if generating code for a shared library. */
547static int shared = 0;
548#endif
549
47926f60
KH		 550/* 1 for intel syntax,
551 0 if att syntax. */
552static int intel_syntax = 0;
252b5132 553
e89c5eaa
L		 554/* 1 for Intel64 ISA,
555 0 if AMD64 ISA. */
556static int intel64;
557
1efbbeb4
L		 558/* 1 for intel mnemonic,
559 0 if att mnemonic. */
560static int intel_mnemonic = !SYSV386_COMPAT;
561
5209009a 562/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 563static int old_gcc = OLDGCC_COMPAT;
564
a60de03c
JB		 565/* 1 if pseudo registers are permitted. */
566static int allow_pseudo_reg = 0;
567
47926f60
KH		 568/* 1 if register prefix % not required. */
569static int allow_naked_reg = 0;
252b5132 570
33eaf5de 571/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 572 instructions supporting it, even if this prefix wasn't specified
573 explicitly. */
574static int add_bnd_prefix = 0;
575
ba104c83 576/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 577static int allow_index_reg = 0;
578
d022bddd
IT		 579/* 1 if the assembler should ignore LOCK prefix, even if it was
580 specified explicitly. */
581static int omit_lock_prefix = 0;
582
e4e00185
AS		 583/* 1 if the assembler should encode lfence, mfence, and sfence as
584 "lock addl $0, (%{re}sp)". */
585static int avoid_fence = 0;
586
0cb4071e
L		 587/* 1 if the assembler should generate relax relocations. */
588
589static int generate_relax_relocations
590 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
591
7bab8ab5 592static enum check_kind
daf50ae7 593 {
7bab8ab5
JB		 594 check_none = 0,
595 check_warning,
596 check_error
daf50ae7 597 }
7bab8ab5 598sse_check, operand_check = check_warning;
daf50ae7 599
2ca3ace5
L		 600/* Register prefix used for error message. */
601static const char *register_prefix = "%";
602
47926f60
KH		 603/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
604 leave, push, and pop instructions so that gcc has the same stack
605 frame as in 32 bit mode. */
606static char stackop_size = '\0';
eecb386c 607
12b55ccc
L		 608/* Non-zero to optimize code alignment. */
609int optimize_align_code = 1;
610
47926f60
KH		 611/* Non-zero to quieten some warnings. */
612static int quiet_warnings = 0;
a38cf1db 613
47926f60
KH		 614/* CPU name. */
615static const char *cpu_arch_name = NULL;
6305a203 616static char *cpu_sub_arch_name = NULL;
a38cf1db 617
47926f60 618/* CPU feature flags. */
40fb9820
L		 619static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
620
ccc9c027
L		 621/* If we have selected a cpu we are generating instructions for. */
622static int cpu_arch_tune_set = 0;
623
9103f4f4 624/* Cpu we are generating instructions for. */
fbf3f584 625enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 626
627/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 628static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 629
ccc9c027 630/* CPU instruction set architecture used. */
fbf3f584 631enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 632
9103f4f4 633/* CPU feature flags of instruction set architecture used. */
fbf3f584 634i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 635
fddf5b5b
AM		 636/* If set, conditional jumps are not automatically promoted to handle
637 larger than a byte offset. */
638static unsigned int no_cond_jump_promotion = 0;
639
c0f3af97
L		 640/* Encode SSE instructions with VEX prefix. */
641static unsigned int sse2avx;
642
539f890d
L		 643/* Encode scalar AVX instructions with specific vector length. */
644static enum
645 {
646 vex128 = 0,
647 vex256
648 } avxscalar;
649
43234a1e
L		 650/* Encode scalar EVEX LIG instructions with specific vector length. */
651static enum
652 {
653 evexl128 = 0,
654 evexl256,
655 evexl512
656 } evexlig;
657
658/* Encode EVEX WIG instructions with specific evex.w. */
659static enum
660 {
661 evexw0 = 0,
662 evexw1
663 } evexwig;
664
d3d3c6db
IT		 665/* Value to encode in EVEX RC bits, for SAE-only instructions. */
666static enum rc_type evexrcig = rne;
667
29b0f896 668/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 669static symbolS *GOT_symbol;
29b0f896 670
a4447b93
RH		 671/* The dwarf2 return column, adjusted for 32 or 64 bit. */
672unsigned int x86_dwarf2_return_column;
673
674/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
675int x86_cie_data_alignment;
676
252b5132 677/* Interface to relax_segment.
fddf5b5b
AM		 678 There are 3 major relax states for 386 jump insns because the
679 different types of jumps add different sizes to frags when we're
680 figuring out what sort of jump to choose to reach a given label. */
252b5132 681
47926f60 682/* Types. */
93c2a809
AM		 683#define UNCOND_JUMP 0
684#define COND_JUMP 1
685#define COND_JUMP86 2
fddf5b5b 686
47926f60 687/* Sizes. */
252b5132
RH		 688#define CODE16 1
689#define SMALL 0
29b0f896 690#define SMALL16 (SMALL | CODE16)
252b5132 691#define BIG 2
29b0f896 692#define BIG16 (BIG | CODE16)
252b5132
RH		 693
694#ifndef INLINE
695#ifdef __GNUC__
696#define INLINE __inline__
697#else
698#define INLINE
699#endif
700#endif
701
fddf5b5b
AM		 702#define ENCODE_RELAX_STATE(type, size) \
703 ((relax_substateT) (((type) << 2) | (size)))
704#define TYPE_FROM_RELAX_STATE(s) \
705 ((s) >> 2)
706#define DISP_SIZE_FROM_RELAX_STATE(s) \
707 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 708
709/* This table is used by relax_frag to promote short jumps to long
710 ones where necessary. SMALL (short) jumps may be promoted to BIG
711 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
712 don't allow a short jump in a 32 bit code segment to be promoted to
713 a 16 bit offset jump because it's slower (requires data size
714 prefix), and doesn't work, unless the destination is in the bottom
715 64k of the code segment (The top 16 bits of eip are zeroed). */
716
717const relax_typeS md_relax_table[] =
718{
24eab124
AM		 719 /* The fields are:
720 1) most positive reach of this state,
721 2) most negative reach of this state,
93c2a809 722 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 723 4) which index into the table to try if we can't fit into this one. */
252b5132 724
fddf5b5b 725 /* UNCOND_JUMP states. */
93c2a809
AM		 726 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
728 /* dword jmp adds 4 bytes to frag:
729 0 extra opcode bytes, 4 displacement bytes. */
252b5132 730 {0, 0, 4, 0},
93c2a809
AM		 731 /* word jmp adds 2 byte2 to frag:
732 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 733 {0, 0, 2, 0},
734
93c2a809
AM		 735 /* COND_JUMP states. */
736 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
738 /* dword conditionals adds 5 bytes to frag:
739 1 extra opcode byte, 4 displacement bytes. */
740 {0, 0, 5, 0},
fddf5b5b 741 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 742 1 extra opcode byte, 2 displacement bytes. */
743 {0, 0, 3, 0},
744
745 /* COND_JUMP86 states. */
746 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
748 /* dword conditionals adds 5 bytes to frag:
749 1 extra opcode byte, 4 displacement bytes. */
750 {0, 0, 5, 0},
751 /* word conditionals add 4 bytes to frag:
752 1 displacement byte and a 3 byte long branch insn. */
753 {0, 0, 4, 0}
252b5132
RH		 754};
755
9103f4f4
L		 756static const arch_entry cpu_arch[] =
757{
89507696
JB		 758 /* Do not replace the first two entries - i386_target_format()
759 relies on them being there in this order. */
8a2c8fef 760 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 761 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 762 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 763 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 765 CPU_NONE_FLAGS, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 767 CPU_I186_FLAGS, 0 },
8a2c8fef 768 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 769 CPU_I286_FLAGS, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 771 CPU_I386_FLAGS, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 773 CPU_I486_FLAGS, 0 },
8a2c8fef 774 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 775 CPU_I586_FLAGS, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 777 CPU_I686_FLAGS, 0 },
8a2c8fef 778 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 779 CPU_I586_FLAGS, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 781 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 782 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 783 CPU_P2_FLAGS, 0 },
8a2c8fef 784 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 785 CPU_P3_FLAGS, 0 },
8a2c8fef 786 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 787 CPU_P4_FLAGS, 0 },
8a2c8fef 788 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 789 CPU_CORE_FLAGS, 0 },
8a2c8fef 790 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 791 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 793 CPU_CORE_FLAGS, 1 },
8a2c8fef 794 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 795 CPU_CORE_FLAGS, 0 },
8a2c8fef 796 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 797 CPU_CORE2_FLAGS, 1 },
8a2c8fef 798 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 799 CPU_CORE2_FLAGS, 0 },
8a2c8fef 800 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 801 CPU_COREI7_FLAGS, 0 },
8a2c8fef 802 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 803 CPU_L1OM_FLAGS, 0 },
7a9068fe 804 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 805 CPU_K1OM_FLAGS, 0 },
81486035 806 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 807 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 808 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 809 CPU_K6_FLAGS, 0 },
8a2c8fef 810 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 811 CPU_K6_2_FLAGS, 0 },
8a2c8fef 812 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 813 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 814 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 815 CPU_K8_FLAGS, 1 },
8a2c8fef 816 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 817 CPU_K8_FLAGS, 0 },
8a2c8fef 818 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 819 CPU_K8_FLAGS, 0 },
8a2c8fef 820 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 821 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 822 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 823 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 824 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 825 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 826 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 827 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 828 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 829 CPU_BDVER4_FLAGS, 0 },
029f3522 830 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 831 CPU_ZNVER1_FLAGS, 0 },
7b458c12 832 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 833 CPU_BTVER1_FLAGS, 0 },
7b458c12 834 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 835 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 836 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 837 CPU_8087_FLAGS, 0 },
8a2c8fef 838 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 839 CPU_287_FLAGS, 0 },
8a2c8fef 840 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 841 CPU_387_FLAGS, 0 },
1848e567
L		 842 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
843 CPU_687_FLAGS, 0 },
8a2c8fef 844 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 845 CPU_MMX_FLAGS, 0 },
8a2c8fef 846 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 847 CPU_SSE_FLAGS, 0 },
8a2c8fef 848 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 849 CPU_SSE2_FLAGS, 0 },
8a2c8fef 850 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 851 CPU_SSE3_FLAGS, 0 },
8a2c8fef 852 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 853 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 854 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 855 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 856 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 857 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 858 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 859 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_AVX_FLAGS, 0 },
6c30d220 862 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_AVX2_FLAGS, 0 },
43234a1e 864 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 865 CPU_AVX512F_FLAGS, 0 },
43234a1e 866 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_AVX512CD_FLAGS, 0 },
43234a1e 868 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_AVX512ER_FLAGS, 0 },
43234a1e 870 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 872 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 874 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 876 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 878 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_VMX_FLAGS, 0 },
8729a6f6 880 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 882 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_SMX_FLAGS, 0 },
8a2c8fef 884 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 886 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 888 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 890 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_AES_FLAGS, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 898 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 900 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 902 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_F16C_FLAGS, 0 },
6c30d220 904 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_BMI2_FLAGS, 0 },
8a2c8fef 906 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_FMA_FLAGS, 0 },
8a2c8fef 908 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_FMA4_FLAGS, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_XOP_FLAGS, 0 },
8a2c8fef 912 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_LWP_FLAGS, 0 },
8a2c8fef 914 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_MOVBE_FLAGS, 0 },
60aa667e 916 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_CX16_FLAGS, 0 },
8a2c8fef 918 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_EPT_FLAGS, 0 },
6c30d220 920 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_LZCNT_FLAGS, 0 },
42164a71 922 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_HLE_FLAGS, 0 },
42164a71 924 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_RTM_FLAGS, 0 },
6c30d220 926 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 928 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_CLFLUSH_FLAGS, 0 },
22109423 930 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_NOP_FLAGS, 0 },
8a2c8fef 932 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 934 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 936 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 938 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 940 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 942 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_SVME_FLAGS, 1 },
8a2c8fef 944 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_SVME_FLAGS, 0 },
8a2c8fef 946 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 948 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_ABM_FLAGS, 0 },
87973e9f 950 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_BMI_FLAGS, 0 },
2a2a0f38 952 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_TBM_FLAGS, 0 },
e2e1fcde 954 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_ADX_FLAGS, 0 },
e2e1fcde 956 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 958 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_PRFCHW_FLAGS, 0 },
5c111e37 960 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_SMAP_FLAGS, 0 },
7e8b059b 962 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_MPX_FLAGS, 0 },
a0046408 964 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 965 CPU_SHA_FLAGS, 0 },
963f3586 966 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 967 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 968 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 969 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 970 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 971 CPU_SE1_FLAGS, 0 },
c5e7287a 972 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 973 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 974 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 975 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 976 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 977 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 978 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
979 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 980 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
981 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 982 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
983 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 984 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
985 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 986 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
987 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 988 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
989 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 990 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 991 CPU_CLZERO_FLAGS, 0 },
9916071f 992 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 993 CPU_MWAITX_FLAGS, 0 },
8eab4136 994 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 995 CPU_OSPKE_FLAGS, 0 },
8bc52696 996 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 997 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 998 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
999 CPU_PTWRITE_FLAGS, 0 },
d777820b
IT		 1000 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1001 CPU_IBT_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1003 CPU_SHSTK_FLAGS, 0 },
48521003
IT		 1004 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1005 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1006 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1007 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1008 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1009 CPU_VPCLMULQDQ_FLAGS, 0 },
3233d7d0
IT		 1010 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1011 CPU_WBNOINVD_FLAGS, 0 },
be3a8dca
IT		 1012 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1013 CPU_PCONFIG_FLAGS, 0 },
293f5f65
L		 1014};
1015
1016static const noarch_entry cpu_noarch[] =
1017{
1018 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1019 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1020 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1021 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1022 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1023 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1024 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1025 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1026 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1027 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1028 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1029 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1030 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1031 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1032 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1033 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1034 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1035 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1036 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1037 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1038 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1039 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1040 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1041 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1042 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1043 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1044 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1045 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1046 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
d777820b
IT		 1047 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1048 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
e413e4e9
AM		 1049};
1050
704209c0 1051#ifdef I386COFF
a6c24e68
NC		 1052/* Like s_lcomm_internal in gas/read.c but the alignment string
1053 is allowed to be optional. */
1054
1055static symbolS *
1056pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1057{
1058 addressT align = 0;
1059
1060 SKIP_WHITESPACE ();
1061
7ab9ffdd 1062 if (needs_align
a6c24e68
NC		 1063 && *input_line_pointer == ',')
1064 {
1065 align = parse_align (needs_align - 1);
7ab9ffdd 1066
a6c24e68
NC		 1067 if (align == (addressT) -1)
1068 return NULL;
1069 }
1070 else
1071 {
1072 if (size >= 8)
1073 align = 3;
1074 else if (size >= 4)
1075 align = 2;
1076 else if (size >= 2)
1077 align = 1;
1078 else
1079 align = 0;
1080 }
1081
1082 bss_alloc (symbolP, size, align);
1083 return symbolP;
1084}
1085
704209c0 1086static void
a6c24e68
NC		 1087pe_lcomm (int needs_align)
1088{
1089 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1090}
704209c0 1091#endif
a6c24e68 1092
29b0f896
AM		 1093const pseudo_typeS md_pseudo_table[] =
1094{
1095#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1096 {"align", s_align_bytes, 0},
1097#else
1098 {"align", s_align_ptwo, 0},
1099#endif
1100 {"arch", set_cpu_arch, 0},
1101#ifndef I386COFF
1102 {"bss", s_bss, 0},
a6c24e68
NC		 1103#else
1104 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1105#endif
1106 {"ffloat", float_cons, 'f'},
1107 {"dfloat", float_cons, 'd'},
1108 {"tfloat", float_cons, 'x'},
1109 {"value", cons, 2},
d182319b 1110 {"slong", signed_cons, 4},
29b0f896
AM		 1111 {"noopt", s_ignore, 0},
1112 {"optim", s_ignore, 0},
1113 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1114 {"code16", set_code_flag, CODE_16BIT},
1115 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1116#ifdef BFD64
29b0f896 1117 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1118#endif
29b0f896
AM		 1119 {"intel_syntax", set_intel_syntax, 1},
1120 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1121 {"intel_mnemonic", set_intel_mnemonic, 1},
1122 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1123 {"allow_index_reg", set_allow_index_reg, 1},
1124 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1125 {"sse_check", set_check, 0},
1126 {"operand_check", set_check, 1},
3b22753a
L		 1127#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1128 {"largecomm", handle_large_common, 0},
07a53e5c 1129#else
e3bb37b5 1130 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1131 {"loc", dwarf2_directive_loc, 0},
1132 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1133#endif
6482c264
NC		 1134#ifdef TE_PE
1135 {"secrel32", pe_directive_secrel, 0},
1136#endif
29b0f896
AM		 1137 {0, 0, 0}
1138};
1139
1140/* For interface with expression (). */
1141extern char *input_line_pointer;
1142
1143/* Hash table for instruction mnemonic lookup. */
1144static struct hash_control *op_hash;
1145
1146/* Hash table for register lookup. */
1147static struct hash_control *reg_hash;
1148\f
252b5132 1149void
e3bb37b5 1150i386_align_code (fragS *fragP, int count)
252b5132 1151{
ce8a8b2f
AM		 1152 /* Various efficient no-op patterns for aligning code labels.
1153 Note: Don't try to assemble the instructions in the comments.
1154 0L and 0w are not legal. */
bad6e36d 1155 static const unsigned char f32_1[] =
252b5132 1156 {0x90}; /* nop */
bad6e36d 1157 static const unsigned char f32_2[] =
ccc9c027 1158 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1159 static const unsigned char f32_3[] =
252b5132 1160 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1161 static const unsigned char f32_4[] =
252b5132 1162 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1163 static const unsigned char f32_5[] =
252b5132
RH		 1164 {0x90, /* nop */
1165 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1166 static const unsigned char f32_6[] =
252b5132 1167 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1168 static const unsigned char f32_7[] =
252b5132 1169 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1170 static const unsigned char f32_8[] =
252b5132
RH		 1171 {0x90, /* nop */
1172 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1173 static const unsigned char f32_9[] =
252b5132
RH		 1174 {0x89,0xf6, /* movl %esi,%esi */
1175 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1176 static const unsigned char f32_10[] =
252b5132
RH		 1177 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1178 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1179 static const unsigned char f32_11[] =
252b5132
RH		 1180 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1181 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1182 static const unsigned char f32_12[] =
252b5132
RH		 1183 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1184 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1185 static const unsigned char f32_13[] =
252b5132
RH		 1186 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1187 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1188 static const unsigned char f32_14[] =
252b5132
RH		 1189 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1190 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1191 static const unsigned char f16_3[] =
c3332e24 1192 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1193 static const unsigned char f16_4[] =
252b5132 1194 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1195 static const unsigned char f16_5[] =
252b5132
RH		 1196 {0x90, /* nop */
1197 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1198 static const unsigned char f16_6[] =
252b5132
RH		 1199 {0x89,0xf6, /* mov %si,%si */
1200 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1201 static const unsigned char f16_7[] =
252b5132
RH		 1202 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1203 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1204 static const unsigned char f16_8[] =
252b5132
RH		 1205 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1206 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1207 static const unsigned char jump_31[] =
76bc74dc
L		 1208 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1209 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1210 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1211 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1212 static const unsigned char *const f32_patt[] = {
252b5132 1213 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1214 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1215 };
bad6e36d 1216 static const unsigned char *const f16_patt[] = {
76bc74dc 1217 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1218 };
ccc9c027 1219 /* nopl (%[re]ax) */
bad6e36d 1220 static const unsigned char alt_3[] =
ccc9c027
L		 1221 {0x0f,0x1f,0x00};
1222 /* nopl 0(%[re]ax) */
bad6e36d 1223 static const unsigned char alt_4[] =
ccc9c027
L		 1224 {0x0f,0x1f,0x40,0x00};
1225 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1226 static const unsigned char alt_5[] =
ccc9c027
L		 1227 {0x0f,0x1f,0x44,0x00,0x00};
1228 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1229 static const unsigned char alt_6[] =
ccc9c027
L		 1230 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1231 /* nopl 0L(%[re]ax) */
bad6e36d 1232 static const unsigned char alt_7[] =
ccc9c027
L		 1233 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1234 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1235 static const unsigned char alt_8[] =
ccc9c027
L		 1236 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1237 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1238 static const unsigned char alt_9[] =
ccc9c027
L		 1239 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1240 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1241 static const unsigned char alt_10[] =
ccc9c027 1242 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1243 static const unsigned char *const alt_patt[] = {
ccc9c027 1244 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1245 alt_9, alt_10
ccc9c027 1246 };
252b5132 1247
76bc74dc
L		 1248 /* Only align for at least a positive non-zero boundary. */
1249 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1250 return;
3e73aa7c 1251
ccc9c027
L		 1252 /* We need to decide which NOP sequence to use for 32bit and
1253 64bit. When -mtune= is used:
4eed87de 1254
76bc74dc
L		 1255 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1256 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1257 2. For the rest, alt_patt will be used.
1258
1259 When -mtune= isn't used, alt_patt will be used if
22109423 1260 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1261 be used.
ccc9c027
L		 1262
1263 When -march= or .arch is used, we can't use anything beyond
1264 cpu_arch_isa_flags. */
1265
1266 if (flag_code == CODE_16BIT)
1267 {
ccc9c027 1268 if (count > 8)
33fef721 1269 {
76bc74dc
L		 1270 memcpy (fragP->fr_literal + fragP->fr_fix,
1271 jump_31, count);
1272 /* Adjust jump offset. */
1273 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1274 }
76bc74dc
L		 1275 else
1276 memcpy (fragP->fr_literal + fragP->fr_fix,
1277 f16_patt[count - 1], count);
252b5132 1278 }
33fef721 1279 else
ccc9c027 1280 {
bad6e36d 1281 const unsigned char *const *patt = NULL;
ccc9c027 1282
fbf3f584 1283 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1284 {
1285 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1286 switch (cpu_arch_tune)
1287 {
1288 case PROCESSOR_UNKNOWN:
1289 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1290 optimize with nops. */
1291 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1292 patt = alt_patt;
ccc9c027
L		 1293 else
1294 patt = f32_patt;
1295 break;
ccc9c027
L		 1296 case PROCESSOR_PENTIUM4:
1297 case PROCESSOR_NOCONA:
ef05d495 1298 case PROCESSOR_CORE:
76bc74dc 1299 case PROCESSOR_CORE2:
bd5295b2 1300 case PROCESSOR_COREI7:
3632d14b 1301 case PROCESSOR_L1OM:
7a9068fe 1302 case PROCESSOR_K1OM:
76bc74dc 1303 case PROCESSOR_GENERIC64:
ccc9c027
L		 1304 case PROCESSOR_K6:
1305 case PROCESSOR_ATHLON:
1306 case PROCESSOR_K8:
4eed87de 1307 case PROCESSOR_AMDFAM10:
8aedb9fe 1308 case PROCESSOR_BD:
029f3522 1309 case PROCESSOR_ZNVER:
7b458c12 1310 case PROCESSOR_BT:
80b8656c 1311 patt = alt_patt;
ccc9c027 1312 break;
76bc74dc 1313 case PROCESSOR_I386:
ccc9c027
L		 1314 case PROCESSOR_I486:
1315 case PROCESSOR_PENTIUM:
2dde1948 1316 case PROCESSOR_PENTIUMPRO:
81486035 1317 case PROCESSOR_IAMCU:
ccc9c027
L		 1318 case PROCESSOR_GENERIC32:
1319 patt = f32_patt;
1320 break;
4eed87de 1321 }
ccc9c027
L		 1322 }
1323 else
1324 {
fbf3f584 1325 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1326 {
1327 case PROCESSOR_UNKNOWN:
e6a14101 1328 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1329 PROCESSOR_UNKNOWN. */
1330 abort ();
1331 break;
1332
76bc74dc 1333 case PROCESSOR_I386:
ccc9c027
L		 1334 case PROCESSOR_I486:
1335 case PROCESSOR_PENTIUM:
81486035 1336 case PROCESSOR_IAMCU:
ccc9c027
L		 1337 case PROCESSOR_K6:
1338 case PROCESSOR_ATHLON:
1339 case PROCESSOR_K8:
4eed87de 1340 case PROCESSOR_AMDFAM10:
8aedb9fe 1341 case PROCESSOR_BD:
029f3522 1342 case PROCESSOR_ZNVER:
7b458c12 1343 case PROCESSOR_BT:
ccc9c027
L		 1344 case PROCESSOR_GENERIC32:
1345 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1346 with nops. */
1347 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1348 patt = alt_patt;
ccc9c027
L		 1349 else
1350 patt = f32_patt;
1351 break;
76bc74dc
L		 1352 case PROCESSOR_PENTIUMPRO:
1353 case PROCESSOR_PENTIUM4:
1354 case PROCESSOR_NOCONA:
1355 case PROCESSOR_CORE:
ef05d495 1356 case PROCESSOR_CORE2:
bd5295b2 1357 case PROCESSOR_COREI7:
3632d14b 1358 case PROCESSOR_L1OM:
7a9068fe 1359 case PROCESSOR_K1OM:
22109423 1360 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1361 patt = alt_patt;
ccc9c027
L		 1362 else
1363 patt = f32_patt;
1364 break;
1365 case PROCESSOR_GENERIC64:
80b8656c 1366 patt = alt_patt;
ccc9c027 1367 break;
4eed87de 1368 }
ccc9c027
L		 1369 }
1370
76bc74dc
L		 1371 if (patt == f32_patt)
1372 {
1373 /* If the padding is less than 15 bytes, we use the normal
1374 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1375 its offset. */
1376 int limit;
76ba9986 1377
711eedef
L		 1378 /* For 64bit, the limit is 3 bytes. */
1379 if (flag_code == CODE_64BIT
1380 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1381 limit = 3;
1382 else
1383 limit = 15;
1384 if (count < limit)
76bc74dc
L		 1385 memcpy (fragP->fr_literal + fragP->fr_fix,
1386 patt[count - 1], count);
1387 else
1388 {
1389 memcpy (fragP->fr_literal + fragP->fr_fix,
1390 jump_31, count);
1391 /* Adjust jump offset. */
1392 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1393 }
1394 }
1395 else
1396 {
80b8656c
L		 1397 /* Maximum length of an instruction is 10 byte. If the
1398 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1399 we have to break it into smaller pieces. */
1400 int padding = count;
80b8656c 1401 while (padding > 10)
76bc74dc 1402 {
80b8656c 1403 padding -= 10;
76bc74dc 1404 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1405 patt [9], 10);
76bc74dc
L		 1406 }
1407
1408 if (padding)
1409 memcpy (fragP->fr_literal + fragP->fr_fix,
1410 patt [padding - 1], padding);
1411 }
ccc9c027 1412 }
33fef721 1413 fragP->fr_var = count;
252b5132
RH		 1414}
1415
c6fb90c8 1416static INLINE int
0dfbf9d7 1417operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1418{
0dfbf9d7 1419 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1420 {
1421 case 3:
0dfbf9d7 1422 if (x->array[2])
c6fb90c8 1423 return 0;
1a0670f3 1424 /* Fall through. */
c6fb90c8 1425 case 2:
0dfbf9d7 1426 if (x->array[1])
c6fb90c8 1427 return 0;
1a0670f3 1428 /* Fall through. */
c6fb90c8 1429 case 1:
0dfbf9d7 1430 return !x->array[0];
c6fb90c8
L		 1431 default:
1432 abort ();
1433 }
40fb9820
L		 1434}
1435
c6fb90c8 1436static INLINE void
0dfbf9d7 1437operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1438{
0dfbf9d7 1439 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1440 {
1441 case 3:
0dfbf9d7 1442 x->array[2] = v;
1a0670f3 1443 /* Fall through. */
c6fb90c8 1444 case 2:
0dfbf9d7 1445 x->array[1] = v;
1a0670f3 1446 /* Fall through. */
c6fb90c8 1447 case 1:
0dfbf9d7 1448 x->array[0] = v;
1a0670f3 1449 /* Fall through. */
c6fb90c8
L		 1450 break;
1451 default:
1452 abort ();
1453 }
1454}
40fb9820 1455
c6fb90c8 1456static INLINE int
0dfbf9d7
L		 1457operand_type_equal (const union i386_operand_type *x,
1458 const union i386_operand_type *y)
c6fb90c8 1459{
0dfbf9d7 1460 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1461 {
1462 case 3:
0dfbf9d7 1463 if (x->array[2] != y->array[2])
c6fb90c8 1464 return 0;
1a0670f3 1465 /* Fall through. */
c6fb90c8 1466 case 2:
0dfbf9d7 1467 if (x->array[1] != y->array[1])
c6fb90c8 1468 return 0;
1a0670f3 1469 /* Fall through. */
c6fb90c8 1470 case 1:
0dfbf9d7 1471 return x->array[0] == y->array[0];
c6fb90c8
L		 1472 break;
1473 default:
1474 abort ();
1475 }
1476}
40fb9820 1477
0dfbf9d7
L		 1478static INLINE int
1479cpu_flags_all_zero (const union i386_cpu_flags *x)
1480{
1481 switch (ARRAY_SIZE(x->array))
1482 {
53467f57
IT		 1483 case 4:
1484 if (x->array[3])
1485 return 0;
1486 /* Fall through. */
0dfbf9d7
L		 1487 case 3:
1488 if (x->array[2])
1489 return 0;
1a0670f3 1490 /* Fall through. */
0dfbf9d7
L		 1491 case 2:
1492 if (x->array[1])
1493 return 0;
1a0670f3 1494 /* Fall through. */
0dfbf9d7
L		 1495 case 1:
1496 return !x->array[0];
1497 default:
1498 abort ();
1499 }
1500}
1501
0dfbf9d7
L		 1502static INLINE int
1503cpu_flags_equal (const union i386_cpu_flags *x,
1504 const union i386_cpu_flags *y)
1505{
1506 switch (ARRAY_SIZE(x->array))
1507 {
53467f57
IT		 1508 case 4:
1509 if (x->array[3] != y->array[3])
1510 return 0;
1511 /* Fall through. */
0dfbf9d7
L		 1512 case 3:
1513 if (x->array[2] != y->array[2])
1514 return 0;
1a0670f3 1515 /* Fall through. */
0dfbf9d7
L		 1516 case 2:
1517 if (x->array[1] != y->array[1])
1518 return 0;
1a0670f3 1519 /* Fall through. */
0dfbf9d7
L		 1520 case 1:
1521 return x->array[0] == y->array[0];
1522 break;
1523 default:
1524 abort ();
1525 }
1526}
c6fb90c8
L		 1527
1528static INLINE int
1529cpu_flags_check_cpu64 (i386_cpu_flags f)
1530{
1531 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1532 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1533}
1534
c6fb90c8
L		 1535static INLINE i386_cpu_flags
1536cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1537{
c6fb90c8
L		 1538 switch (ARRAY_SIZE (x.array))
1539 {
53467f57
IT		 1540 case 4:
1541 x.array [3] &= y.array [3];
1542 /* Fall through. */
c6fb90c8
L		 1543 case 3:
1544 x.array [2] &= y.array [2];
1a0670f3 1545 /* Fall through. */
c6fb90c8
L		 1546 case 2:
1547 x.array [1] &= y.array [1];
1a0670f3 1548 /* Fall through. */
c6fb90c8
L		 1549 case 1:
1550 x.array [0] &= y.array [0];
1551 break;
1552 default:
1553 abort ();
1554 }
1555 return x;
1556}
40fb9820 1557
c6fb90c8
L		 1558static INLINE i386_cpu_flags
1559cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1560{
c6fb90c8 1561 switch (ARRAY_SIZE (x.array))
40fb9820 1562 {
53467f57
IT		 1563 case 4:
1564 x.array [3] |= y.array [3];
1565 /* Fall through. */
c6fb90c8
L		 1566 case 3:
1567 x.array [2] |= y.array [2];
1a0670f3 1568 /* Fall through. */
c6fb90c8
L		 1569 case 2:
1570 x.array [1] |= y.array [1];
1a0670f3 1571 /* Fall through. */
c6fb90c8
L		 1572 case 1:
1573 x.array [0] |= y.array [0];
40fb9820
L		 1574 break;
1575 default:
1576 abort ();
1577 }
40fb9820
L		 1578 return x;
1579}
1580
309d3373
JB		 1581static INLINE i386_cpu_flags
1582cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1583{
1584 switch (ARRAY_SIZE (x.array))
1585 {
53467f57
IT		 1586 case 4:
1587 x.array [3] &= ~y.array [3];
1588 /* Fall through. */
309d3373
JB		 1589 case 3:
1590 x.array [2] &= ~y.array [2];
1a0670f3 1591 /* Fall through. */
309d3373
JB		 1592 case 2:
1593 x.array [1] &= ~y.array [1];
1a0670f3 1594 /* Fall through. */
309d3373
JB		 1595 case 1:
1596 x.array [0] &= ~y.array [0];
1597 break;
1598 default:
1599 abort ();
1600 }
1601 return x;
1602}
1603
c0f3af97
L		 1604#define CPU_FLAGS_ARCH_MATCH 0x1
1605#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1606#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1607#define CPU_FLAGS_PCLMUL_MATCH 0x8
1608#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1609
a5ff0eb2 1610#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1611 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1612 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1613#define CPU_FLAGS_PERFECT_MATCH \
1614 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1615
1616/* Return CPU flags match bits. */
3629bb00 1617
40fb9820 1618static int
d3ce72d0 1619cpu_flags_match (const insn_template *t)
40fb9820 1620{
c0f3af97
L		 1621 i386_cpu_flags x = t->cpu_flags;
1622 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1623
1624 x.bitfield.cpu64 = 0;
1625 x.bitfield.cpuno64 = 0;
1626
0dfbf9d7 1627 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1628 {
1629 /* This instruction is available on all archs. */
1630 match |= CPU_FLAGS_32BIT_MATCH;
1631 }
3629bb00
L		 1632 else
1633 {
c0f3af97 1634 /* This instruction is available only on some archs. */
3629bb00
L		 1635 i386_cpu_flags cpu = cpu_arch_flags;
1636
3629bb00 1637 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1638 if (!cpu_flags_all_zero (&cpu))
1639 {
a5ff0eb2
L		 1640 if (x.bitfield.cpuavx)
1641 {
ce2f5b3c 1642 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1643 if (cpu.bitfield.cpuavx)
1644 {
1645 /* Check SSE2AVX. */
1646 if (!t->opcode_modifier.sse2avx|| sse2avx)
1647 {
1648 match |= (CPU_FLAGS_ARCH_MATCH
1649 | CPU_FLAGS_AVX_MATCH);
1650 /* Check AES. */
1651 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1652 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1653 /* Check PCLMUL. */
1654 if (!x.bitfield.cpupclmul
1655 || cpu.bitfield.cpupclmul)
1656 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1657 }
1658 }
1659 else
1660 match |= CPU_FLAGS_ARCH_MATCH;
1661 }
73b090a9
L		 1662 else if (x.bitfield.cpuavx512vl)
1663 {
1664 /* Match AVX512VL. */
1665 if (cpu.bitfield.cpuavx512vl)
1666 {
1667 /* Need another match. */
1668 cpu.bitfield.cpuavx512vl = 0;
1669 if (!cpu_flags_all_zero (&cpu))
1670 match |= CPU_FLAGS_32BIT_MATCH;
1671 else
1672 match |= CPU_FLAGS_ARCH_MATCH;
1673 }
1674 else
1675 match |= CPU_FLAGS_ARCH_MATCH;
1676 }
a5ff0eb2 1677 else
c0f3af97
L		 1678 match |= CPU_FLAGS_32BIT_MATCH;
1679 }
3629bb00 1680 }
c0f3af97 1681 return match;
40fb9820
L		 1682}
1683
c6fb90c8
L		 1684static INLINE i386_operand_type
1685operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1686{
c6fb90c8
L		 1687 switch (ARRAY_SIZE (x.array))
1688 {
1689 case 3:
1690 x.array [2] &= y.array [2];
1a0670f3 1691 /* Fall through. */
c6fb90c8
L		 1692 case 2:
1693 x.array [1] &= y.array [1];
1a0670f3 1694 /* Fall through. */
c6fb90c8
L		 1695 case 1:
1696 x.array [0] &= y.array [0];
1697 break;
1698 default:
1699 abort ();
1700 }
1701 return x;
40fb9820
L		 1702}
1703
c6fb90c8
L		 1704static INLINE i386_operand_type
1705operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1706{
c6fb90c8 1707 switch (ARRAY_SIZE (x.array))
40fb9820 1708 {
c6fb90c8
L		 1709 case 3:
1710 x.array [2] |= y.array [2];
1a0670f3 1711 /* Fall through. */
c6fb90c8
L		 1712 case 2:
1713 x.array [1] |= y.array [1];
1a0670f3 1714 /* Fall through. */
c6fb90c8
L		 1715 case 1:
1716 x.array [0] |= y.array [0];
40fb9820
L		 1717 break;
1718 default:
1719 abort ();
1720 }
c6fb90c8
L		 1721 return x;
1722}
40fb9820 1723
c6fb90c8
L		 1724static INLINE i386_operand_type
1725operand_type_xor (i386_operand_type x, i386_operand_type y)
1726{
1727 switch (ARRAY_SIZE (x.array))
1728 {
1729 case 3:
1730 x.array [2] ^= y.array [2];
1a0670f3 1731 /* Fall through. */
c6fb90c8
L		 1732 case 2:
1733 x.array [1] ^= y.array [1];
1a0670f3 1734 /* Fall through. */
c6fb90c8
L		 1735 case 1:
1736 x.array [0] ^= y.array [0];
1737 break;
1738 default:
1739 abort ();
1740 }
40fb9820
L		 1741 return x;
1742}
1743
1744static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1745static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1746static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1747static const i386_operand_type inoutportreg
1748 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1749static const i386_operand_type reg16_inoutportreg
1750 = OPERAND_TYPE_REG16_INOUTPORTREG;
1751static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1752static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1753static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1754static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1755static const i386_operand_type anydisp
1756 = OPERAND_TYPE_ANYDISP;
40fb9820 1757static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
43234a1e 1758static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1759static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1760static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1761static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1762static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1763static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1764static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1765static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1766static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1767static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1768static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1769
1770enum operand_type
1771{
1772 reg,
40fb9820
L		 1773 imm,
1774 disp,
1775 anymem
1776};
1777
c6fb90c8 1778static INLINE int
40fb9820
L		 1779operand_type_check (i386_operand_type t, enum operand_type c)
1780{
1781 switch (c)
1782 {
1783 case reg:
dc821c5f 1784 return t.bitfield.reg;
40fb9820 1785
40fb9820
L		 1786 case imm:
1787 return (t.bitfield.imm8
1788 || t.bitfield.imm8s
1789 || t.bitfield.imm16
1790 || t.bitfield.imm32
1791 || t.bitfield.imm32s
1792 || t.bitfield.imm64);
1793
1794 case disp:
1795 return (t.bitfield.disp8
1796 || t.bitfield.disp16
1797 || t.bitfield.disp32
1798 || t.bitfield.disp32s
1799 || t.bitfield.disp64);
1800
1801 case anymem:
1802 return (t.bitfield.disp8
1803 || t.bitfield.disp16
1804 || t.bitfield.disp32
1805 || t.bitfield.disp32s
1806 || t.bitfield.disp64
1807 || t.bitfield.baseindex);
1808
1809 default:
1810 abort ();
1811 }
2cfe26b6
AM		 1812
1813 return 0;
40fb9820
L		 1814}
1815
ca0d63fe 1816/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
5c07affc
L		 1817 operand J for instruction template T. */
1818
1819static INLINE int
d3ce72d0 1820match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1821{
1822 return !((i.types[j].bitfield.byte
1823 && !t->operand_types[j].bitfield.byte)
1824 || (i.types[j].bitfield.word
1825 && !t->operand_types[j].bitfield.word)
1826 || (i.types[j].bitfield.dword
1827 && !t->operand_types[j].bitfield.dword)
1828 || (i.types[j].bitfield.qword
ca0d63fe
JB		 1829 && !t->operand_types[j].bitfield.qword)
1830 || (i.types[j].bitfield.tbyte
1831 && !t->operand_types[j].bitfield.tbyte));
5c07affc
L		 1832}
1833
1b54b8d7
JB		 1834/* Return 1 if there is no conflict in SIMD register on
1835 operand J for instruction template T. */
1836
1837static INLINE int
1838match_simd_size (const insn_template *t, unsigned int j)
1839{
1840 return !((i.types[j].bitfield.xmmword
1841 && !t->operand_types[j].bitfield.xmmword)
1842 || (i.types[j].bitfield.ymmword
1843 && !t->operand_types[j].bitfield.ymmword)
1844 || (i.types[j].bitfield.zmmword
1845 && !t->operand_types[j].bitfield.zmmword));
1846}
1847
5c07affc
L		 1848/* Return 1 if there is no conflict in any size on operand J for
1849 instruction template T. */
1850
1851static INLINE int
d3ce72d0 1852match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1853{
1854 return (match_reg_size (t, j)
1855 && !((i.types[j].bitfield.unspecified
af508cb9 1856 && !i.broadcast
5c07affc
L		 1857 && !t->operand_types[j].bitfield.unspecified)
1858 || (i.types[j].bitfield.fword
1859 && !t->operand_types[j].bitfield.fword)
1b54b8d7
JB		 1860 /* For scalar opcode templates to allow register and memory
1861 operands at the same time, some special casing is needed
1862 here. */
1863 || ((t->operand_types[j].bitfield.regsimd
1864 && !t->opcode_modifier.broadcast
1865 && (t->operand_types[j].bitfield.dword
1866 || t->operand_types[j].bitfield.qword))
1867 ? (i.types[j].bitfield.xmmword
1868 || i.types[j].bitfield.ymmword
1869 || i.types[j].bitfield.zmmword)
1870 : !match_simd_size(t, j))));
5c07affc
L		 1871}
1872
1873/* Return 1 if there is no size conflict on any operands for
1874 instruction template T. */
1875
1876static INLINE int
d3ce72d0 1877operand_size_match (const insn_template *t)
5c07affc
L		 1878{
1879 unsigned int j;
1880 int match = 1;
1881
1882 /* Don't check jump instructions. */
1883 if (t->opcode_modifier.jump
1884 || t->opcode_modifier.jumpbyte
1885 || t->opcode_modifier.jumpdword
1886 || t->opcode_modifier.jumpintersegment)
1887 return match;
1888
1889 /* Check memory and accumulator operand size. */
1890 for (j = 0; j < i.operands; j++)
1891 {
1b54b8d7
JB		 1892 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1893 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 1894 continue;
1895
1b54b8d7 1896 if (t->operand_types[j].bitfield.reg
dc821c5f 1897 && !match_reg_size (t, j))
5c07affc
L		 1898 {
1899 match = 0;
1900 break;
1901 }
1902
1b54b8d7
JB		 1903 if (t->operand_types[j].bitfield.regsimd
1904 && !match_simd_size (t, j))
1905 {
1906 match = 0;
1907 break;
1908 }
1909
1910 if (t->operand_types[j].bitfield.acc
1911 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1912 {
1913 match = 0;
1914 break;
1915 }
1916
5c07affc
L		 1917 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1918 {
1919 match = 0;
1920 break;
1921 }
1922 }
1923
891edac4 1924 if (match)
5c07affc 1925 return match;
891edac4
L		 1926 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1927 {
1928mismatch:
86e026a4 1929 i.error = operand_size_mismatch;
891edac4
L		 1930 return 0;
1931 }
5c07affc
L		 1932
1933 /* Check reverse. */
9c2799c2 1934 gas_assert (i.operands == 2);
5c07affc
L		 1935
1936 match = 1;
1937 for (j = 0; j < 2; j++)
1938 {
dc821c5f
JB		 1939 if ((t->operand_types[j].bitfield.reg
1940 || t->operand_types[j].bitfield.acc)
5c07affc 1941 && !match_reg_size (t, j ? 0 : 1))
891edac4 1942 goto mismatch;
5c07affc
L		 1943
1944 if (i.types[j].bitfield.mem
1945 && !match_mem_size (t, j ? 0 : 1))
891edac4 1946 goto mismatch;
5c07affc
L		 1947 }
1948
1949 return match;
1950}
1951
c6fb90c8 1952static INLINE int
40fb9820
L		 1953operand_type_match (i386_operand_type overlap,
1954 i386_operand_type given)
1955{
1956 i386_operand_type temp = overlap;
1957
1958 temp.bitfield.jumpabsolute = 0;
7d5e4556 1959 temp.bitfield.unspecified = 0;
5c07affc
L		 1960 temp.bitfield.byte = 0;
1961 temp.bitfield.word = 0;
1962 temp.bitfield.dword = 0;
1963 temp.bitfield.fword = 0;
1964 temp.bitfield.qword = 0;
1965 temp.bitfield.tbyte = 0;
1966 temp.bitfield.xmmword = 0;
c0f3af97 1967 temp.bitfield.ymmword = 0;
43234a1e 1968 temp.bitfield.zmmword = 0;
0dfbf9d7 1969 if (operand_type_all_zero (&temp))
891edac4 1970 goto mismatch;
40fb9820 1971
891edac4
L		 1972 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1973 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1974 return 1;
1975
1976mismatch:
a65babc9 1977 i.error = operand_type_mismatch;
891edac4 1978 return 0;
40fb9820
L		 1979}
1980
7d5e4556 1981/* If given types g0 and g1 are registers they must be of the same type
10c17abd
JB		 1982 unless the expected operand type register overlap is null.
1983 Memory operand size of certain SIMD instructions is also being checked
1984 here. */
40fb9820 1985
c6fb90c8 1986static INLINE int
dc821c5f 1987operand_type_register_match (i386_operand_type g0,
40fb9820 1988 i386_operand_type t0,
40fb9820
L		 1989 i386_operand_type g1,
1990 i386_operand_type t1)
1991{
10c17abd
JB		 1992 if (!g0.bitfield.reg
1993 && !g0.bitfield.regsimd
1994 && (!operand_type_check (g0, anymem)
1995 || g0.bitfield.unspecified
1996 || !t0.bitfield.regsimd))
40fb9820
L		 1997 return 1;
1998
10c17abd
JB		 1999 if (!g1.bitfield.reg
2000 && !g1.bitfield.regsimd
2001 && (!operand_type_check (g1, anymem)
2002 || g1.bitfield.unspecified
2003 || !t1.bitfield.regsimd))
40fb9820
L		 2004 return 1;
2005
dc821c5f
JB		 2006 if (g0.bitfield.byte == g1.bitfield.byte
2007 && g0.bitfield.word == g1.bitfield.word
2008 && g0.bitfield.dword == g1.bitfield.dword
10c17abd
JB		 2009 && g0.bitfield.qword == g1.bitfield.qword
2010 && g0.bitfield.xmmword == g1.bitfield.xmmword
2011 && g0.bitfield.ymmword == g1.bitfield.ymmword
2012 && g0.bitfield.zmmword == g1.bitfield.zmmword)
40fb9820
L		 2013 return 1;
2014
dc821c5f
JB		 2015 if (!(t0.bitfield.byte & t1.bitfield.byte)
2016 && !(t0.bitfield.word & t1.bitfield.word)
2017 && !(t0.bitfield.dword & t1.bitfield.dword)
10c17abd
JB		 2018 && !(t0.bitfield.qword & t1.bitfield.qword)
2019 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2020 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2021 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
891edac4
L		 2022 return 1;
2023
a65babc9 2024 i.error = register_type_mismatch;
891edac4
L		 2025
2026 return 0;
40fb9820
L		 2027}
2028
4c692bc7
JB		 2029static INLINE unsigned int
2030register_number (const reg_entry *r)
2031{
2032 unsigned int nr = r->reg_num;
2033
2034 if (r->reg_flags & RegRex)
2035 nr += 8;
2036
200cbe0f
L		 2037 if (r->reg_flags & RegVRex)
2038 nr += 16;
2039
4c692bc7
JB		 2040 return nr;
2041}
2042
252b5132 2043static INLINE unsigned int
40fb9820 2044mode_from_disp_size (i386_operand_type t)
252b5132 2045{
b5014f7a 2046 if (t.bitfield.disp8)
40fb9820
L		 2047 return 1;
2048 else if (t.bitfield.disp16
2049 || t.bitfield.disp32
2050 || t.bitfield.disp32s)
2051 return 2;
2052 else
2053 return 0;
252b5132
RH		 2054}
2055
2056static INLINE int
65879393 2057fits_in_signed_byte (addressT num)
252b5132 2058{
65879393 2059 return num + 0x80 <= 0xff;
47926f60 2060}
252b5132
RH		 2061
2062static INLINE int
65879393 2063fits_in_unsigned_byte (addressT num)
252b5132 2064{
65879393 2065 return num <= 0xff;
47926f60 2066}
252b5132
RH		 2067
2068static INLINE int
65879393 2069fits_in_unsigned_word (addressT num)
252b5132 2070{
65879393 2071 return num <= 0xffff;
47926f60 2072}
252b5132
RH		 2073
2074static INLINE int
65879393 2075fits_in_signed_word (addressT num)
252b5132 2076{
65879393 2077 return num + 0x8000 <= 0xffff;
47926f60 2078}
2a962e6d 2079
3e73aa7c 2080static INLINE int
65879393 2081fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2082{
2083#ifndef BFD64
2084 return 1;
2085#else
65879393 2086 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2087#endif
2088} /* fits_in_signed_long() */
2a962e6d 2089
3e73aa7c 2090static INLINE int
65879393 2091fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2092{
2093#ifndef BFD64
2094 return 1;
2095#else
65879393 2096 return num <= 0xffffffff;
3e73aa7c
JH		 2097#endif
2098} /* fits_in_unsigned_long() */
252b5132 2099
43234a1e 2100static INLINE int
b5014f7a 2101fits_in_disp8 (offsetT num)
43234a1e
L		 2102{
2103 int shift = i.memshift;
2104 unsigned int mask;
2105
2106 if (shift == -1)
2107 abort ();
2108
2109 mask = (1 << shift) - 1;
2110
2111 /* Return 0 if NUM isn't properly aligned. */
2112 if ((num & mask))
2113 return 0;
2114
2115 /* Check if NUM will fit in 8bit after shift. */
2116 return fits_in_signed_byte (num >> shift);
2117}
2118
a683cc34
SP		 2119static INLINE int
2120fits_in_imm4 (offsetT num)
2121{
2122 return (num & 0xf) == num;
2123}
2124
40fb9820 2125static i386_operand_type
e3bb37b5 2126smallest_imm_type (offsetT num)
252b5132 2127{
40fb9820 2128 i386_operand_type t;
7ab9ffdd 2129
0dfbf9d7 2130 operand_type_set (&t, 0);
40fb9820
L		 2131 t.bitfield.imm64 = 1;
2132
2133 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2134 {
2135 /* This code is disabled on the 486 because all the Imm1 forms
2136 in the opcode table are slower on the i486. They're the
2137 versions with the implicitly specified single-position
2138 displacement, which has another syntax if you really want to
2139 use that form. */
40fb9820
L		 2140 t.bitfield.imm1 = 1;
2141 t.bitfield.imm8 = 1;
2142 t.bitfield.imm8s = 1;
2143 t.bitfield.imm16 = 1;
2144 t.bitfield.imm32 = 1;
2145 t.bitfield.imm32s = 1;
2146 }
2147 else if (fits_in_signed_byte (num))
2148 {
2149 t.bitfield.imm8 = 1;
2150 t.bitfield.imm8s = 1;
2151 t.bitfield.imm16 = 1;
2152 t.bitfield.imm32 = 1;
2153 t.bitfield.imm32s = 1;
2154 }
2155 else if (fits_in_unsigned_byte (num))
2156 {
2157 t.bitfield.imm8 = 1;
2158 t.bitfield.imm16 = 1;
2159 t.bitfield.imm32 = 1;
2160 t.bitfield.imm32s = 1;
2161 }
2162 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2163 {
2164 t.bitfield.imm16 = 1;
2165 t.bitfield.imm32 = 1;
2166 t.bitfield.imm32s = 1;
2167 }
2168 else if (fits_in_signed_long (num))
2169 {
2170 t.bitfield.imm32 = 1;
2171 t.bitfield.imm32s = 1;
2172 }
2173 else if (fits_in_unsigned_long (num))
2174 t.bitfield.imm32 = 1;
2175
2176 return t;
47926f60 2177}
252b5132 2178
847f7ad4 2179static offsetT
e3bb37b5 2180offset_in_range (offsetT val, int size)
847f7ad4 2181{
508866be 2182 addressT mask;
ba2adb93 2183
847f7ad4
AM		 2184 switch (size)
2185 {
508866be
L		 2186 case 1: mask = ((addressT) 1 << 8) - 1; break;
2187 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2188 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2189#ifdef BFD64
2190 case 8: mask = ((addressT) 2 << 63) - 1; break;
2191#endif
47926f60 2192 default: abort ();
847f7ad4
AM		 2193 }
2194
9de868bf
L		 2195#ifdef BFD64
2196 /* If BFD64, sign extend val for 32bit address mode. */
2197 if (flag_code != CODE_64BIT
2198 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2199 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2200 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2201#endif
ba2adb93 2202
47926f60 2203 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2204 {
2205 char buf1[40], buf2[40];
2206
2207 sprint_value (buf1, val);
2208 sprint_value (buf2, val & mask);
2209 as_warn (_("%s shortened to %s"), buf1, buf2);
2210 }
2211 return val & mask;
2212}
2213
c32fa91d
L		 2214enum PREFIX_GROUP
2215{
2216 PREFIX_EXIST = 0,
2217 PREFIX_LOCK,
2218 PREFIX_REP,
04ef582a 2219 PREFIX_DS,
c32fa91d
L		 2220 PREFIX_OTHER
2221};
2222
2223/* Returns
2224 a. PREFIX_EXIST if attempting to add a prefix where one from the
2225 same class already exists.
2226 b. PREFIX_LOCK if lock prefix is added.
2227 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2228 d. PREFIX_DS if ds prefix is added.
2229 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2230 */
2231
2232static enum PREFIX_GROUP
e3bb37b5 2233add_prefix (unsigned int prefix)
252b5132 2234{
c32fa91d 2235 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2236 unsigned int q;
252b5132 2237
29b0f896
AM		 2238 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2239 && flag_code == CODE_64BIT)
b1905489 2240 {
161a04f6
L		 2241 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2242 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2243 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2244 ret = PREFIX_EXIST;
b1905489
JB		 2245 q = REX_PREFIX;
2246 }
3e73aa7c 2247 else
b1905489
JB		 2248 {
2249 switch (prefix)
2250 {
2251 default:
2252 abort ();
2253
b1905489 2254 case DS_PREFIX_OPCODE:
04ef582a
L		 2255 ret = PREFIX_DS;
2256 /* Fall through. */
2257 case CS_PREFIX_OPCODE:
b1905489
JB		 2258 case ES_PREFIX_OPCODE:
2259 case FS_PREFIX_OPCODE:
2260 case GS_PREFIX_OPCODE:
2261 case SS_PREFIX_OPCODE:
2262 q = SEG_PREFIX;
2263 break;
2264
2265 case REPNE_PREFIX_OPCODE:
2266 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2267 q = REP_PREFIX;
2268 ret = PREFIX_REP;
2269 break;
2270
b1905489 2271 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2272 q = LOCK_PREFIX;
2273 ret = PREFIX_LOCK;
b1905489
JB		 2274 break;
2275
2276 case FWAIT_OPCODE:
2277 q = WAIT_PREFIX;
2278 break;
2279
2280 case ADDR_PREFIX_OPCODE:
2281 q = ADDR_PREFIX;
2282 break;
2283
2284 case DATA_PREFIX_OPCODE:
2285 q = DATA_PREFIX;
2286 break;
2287 }
2288 if (i.prefix[q] != 0)
c32fa91d 2289 ret = PREFIX_EXIST;
b1905489 2290 }
252b5132 2291
b1905489 2292 if (ret)
252b5132 2293 {
b1905489
JB		 2294 if (!i.prefix[q])
2295 ++i.prefixes;
2296 i.prefix[q] |= prefix;
252b5132 2297 }
b1905489
JB		 2298 else
2299 as_bad (_("same type of prefix used twice"));
252b5132 2300
252b5132
RH		 2301 return ret;
2302}
2303
2304static void
78f12dd3 2305update_code_flag (int value, int check)
eecb386c 2306{
78f12dd3
L		 2307 PRINTF_LIKE ((*as_error));
2308
1e9cc1c2 2309 flag_code = (enum flag_code) value;
40fb9820
L		 2310 if (flag_code == CODE_64BIT)
2311 {
2312 cpu_arch_flags.bitfield.cpu64 = 1;
2313 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2314 }
2315 else
2316 {
2317 cpu_arch_flags.bitfield.cpu64 = 0;
2318 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2319 }
2320 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2321 {
78f12dd3
L		 2322 if (check)
2323 as_error = as_fatal;
2324 else
2325 as_error = as_bad;
2326 (*as_error) (_("64bit mode not supported on `%s'."),
2327 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2328 }
40fb9820 2329 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2330 {
78f12dd3
L		 2331 if (check)
2332 as_error = as_fatal;
2333 else
2334 as_error = as_bad;
2335 (*as_error) (_("32bit mode not supported on `%s'."),
2336 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2337 }
eecb386c
AM		 2338 stackop_size = '\0';
2339}
2340
78f12dd3
L		 2341static void
2342set_code_flag (int value)
2343{
2344 update_code_flag (value, 0);
2345}
2346
eecb386c 2347static void
e3bb37b5 2348set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2349{
1e9cc1c2 2350 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2351 if (flag_code != CODE_16BIT)
2352 abort ();
2353 cpu_arch_flags.bitfield.cpu64 = 0;
2354 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2355 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2356}
2357
2358static void
e3bb37b5 2359set_intel_syntax (int syntax_flag)
252b5132
RH		 2360{
2361 /* Find out if register prefixing is specified. */
2362 int ask_naked_reg = 0;
2363
2364 SKIP_WHITESPACE ();
29b0f896 2365 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2366 {
d02603dc
NC		 2367 char *string;
2368 int e = get_symbol_name (&string);
252b5132 2369
47926f60 2370 if (strcmp (string, "prefix") == 0)
252b5132 2371 ask_naked_reg = 1;
47926f60 2372 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2373 ask_naked_reg = -1;
2374 else
d0b47220 2375 as_bad (_("bad argument to syntax directive."));
d02603dc 2376 (void) restore_line_pointer (e);
252b5132
RH		 2377 }
2378 demand_empty_rest_of_line ();
c3332e24 2379
252b5132
RH		 2380 intel_syntax = syntax_flag;
2381
2382 if (ask_naked_reg == 0)
f86103b7
AM		 2383 allow_naked_reg = (intel_syntax
2384 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2385 else
2386 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2387
ee86248c 2388 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2389
e4a3b5a4 2390 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2391 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2392 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2393}
2394
1efbbeb4
L		 2395static void
2396set_intel_mnemonic (int mnemonic_flag)
2397{
e1d4d893 2398 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2399}
2400
db51cc60
L		 2401static void
2402set_allow_index_reg (int flag)
2403{
2404 allow_index_reg = flag;
2405}
2406
cb19c032 2407static void
7bab8ab5 2408set_check (int what)
cb19c032 2409{
7bab8ab5
JB		 2410 enum check_kind *kind;
2411 const char *str;
2412
2413 if (what)
2414 {
2415 kind = &operand_check;
2416 str = "operand";
2417 }
2418 else
2419 {
2420 kind = &sse_check;
2421 str = "sse";
2422 }
2423
cb19c032
L		 2424 SKIP_WHITESPACE ();
2425
2426 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2427 {
d02603dc
NC		 2428 char *string;
2429 int e = get_symbol_name (&string);
cb19c032
L		 2430
2431 if (strcmp (string, "none") == 0)
7bab8ab5 2432 *kind = check_none;
cb19c032 2433 else if (strcmp (string, "warning") == 0)
7bab8ab5 2434 *kind = check_warning;
cb19c032 2435 else if (strcmp (string, "error") == 0)
7bab8ab5 2436 *kind = check_error;
cb19c032 2437 else
7bab8ab5 2438 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2439 (void) restore_line_pointer (e);
cb19c032
L		 2440 }
2441 else
7bab8ab5 2442 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2443
2444 demand_empty_rest_of_line ();
2445}
2446
8a9036a4
L		 2447static void
2448check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2449 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2450{
2451#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2452 static const char *arch;
2453
2454 /* Intel LIOM is only supported on ELF. */
2455 if (!IS_ELF)
2456 return;
2457
2458 if (!arch)
2459 {
2460 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2461 use default_arch. */
2462 arch = cpu_arch_name;
2463 if (!arch)
2464 arch = default_arch;
2465 }
2466
81486035
L		 2467 /* If we are targeting Intel MCU, we must enable it. */
2468 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2469 || new_flag.bitfield.cpuiamcu)
2470 return;
2471
3632d14b 2472 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2473 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2474 || new_flag.bitfield.cpul1om)
8a9036a4 2475 return;
76ba9986 2476
7a9068fe
L		 2477 /* If we are targeting Intel K1OM, we must enable it. */
2478 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2479 || new_flag.bitfield.cpuk1om)
2480 return;
2481
8a9036a4
L		 2482 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2483#endif
2484}
2485
e413e4e9 2486static void
e3bb37b5 2487set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2488{
47926f60 2489 SKIP_WHITESPACE ();
e413e4e9 2490
29b0f896 2491 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2492 {
d02603dc
NC		 2493 char *string;
2494 int e = get_symbol_name (&string);
91d6fa6a 2495 unsigned int j;
40fb9820 2496 i386_cpu_flags flags;
e413e4e9 2497
91d6fa6a 2498 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2499 {
91d6fa6a 2500 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2501 {
91d6fa6a 2502 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2503
5c6af06e
JB		 2504 if (*string != '.')
2505 {
91d6fa6a 2506 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2507 cpu_sub_arch_name = NULL;
91d6fa6a 2508 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2509 if (flag_code == CODE_64BIT)
2510 {
2511 cpu_arch_flags.bitfield.cpu64 = 1;
2512 cpu_arch_flags.bitfield.cpuno64 = 0;
2513 }
2514 else
2515 {
2516 cpu_arch_flags.bitfield.cpu64 = 0;
2517 cpu_arch_flags.bitfield.cpuno64 = 1;
2518 }
91d6fa6a
NC		 2519 cpu_arch_isa = cpu_arch[j].type;
2520 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2521 if (!cpu_arch_tune_set)
2522 {
2523 cpu_arch_tune = cpu_arch_isa;
2524 cpu_arch_tune_flags = cpu_arch_isa_flags;
2525 }
5c6af06e
JB		 2526 break;
2527 }
40fb9820 2528
293f5f65
L		 2529 flags = cpu_flags_or (cpu_arch_flags,
2530 cpu_arch[j].flags);
81486035 2531
5b64d091 2532 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2533 {
6305a203
L		 2534 if (cpu_sub_arch_name)
2535 {
2536 char *name = cpu_sub_arch_name;
2537 cpu_sub_arch_name = concat (name,
91d6fa6a 2538 cpu_arch[j].name,
1bf57e9f 2539 (const char *) NULL);
6305a203
L		 2540 free (name);
2541 }
2542 else
91d6fa6a 2543 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2544 cpu_arch_flags = flags;
a586129e 2545 cpu_arch_isa_flags = flags;
5c6af06e 2546 }
d02603dc 2547 (void) restore_line_pointer (e);
5c6af06e
JB		 2548 demand_empty_rest_of_line ();
2549 return;
e413e4e9
AM		 2550 }
2551 }
293f5f65
L		 2552
2553 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2554 {
33eaf5de 2555 /* Disable an ISA extension. */
293f5f65
L		 2556 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2557 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2558 {
2559 flags = cpu_flags_and_not (cpu_arch_flags,
2560 cpu_noarch[j].flags);
2561 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2562 {
2563 if (cpu_sub_arch_name)
2564 {
2565 char *name = cpu_sub_arch_name;
2566 cpu_sub_arch_name = concat (name, string,
2567 (const char *) NULL);
2568 free (name);
2569 }
2570 else
2571 cpu_sub_arch_name = xstrdup (string);
2572 cpu_arch_flags = flags;
2573 cpu_arch_isa_flags = flags;
2574 }
2575 (void) restore_line_pointer (e);
2576 demand_empty_rest_of_line ();
2577 return;
2578 }
2579
2580 j = ARRAY_SIZE (cpu_arch);
2581 }
2582
91d6fa6a 2583 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2584 as_bad (_("no such architecture: `%s'"), string);
2585
2586 *input_line_pointer = e;
2587 }
2588 else
2589 as_bad (_("missing cpu architecture"));
2590
fddf5b5b
AM		 2591 no_cond_jump_promotion = 0;
2592 if (*input_line_pointer == ','
29b0f896 2593 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2594 {
d02603dc
NC		 2595 char *string;
2596 char e;
2597
2598 ++input_line_pointer;
2599 e = get_symbol_name (&string);
fddf5b5b
AM		 2600
2601 if (strcmp (string, "nojumps") == 0)
2602 no_cond_jump_promotion = 1;
2603 else if (strcmp (string, "jumps") == 0)
2604 ;
2605 else
2606 as_bad (_("no such architecture modifier: `%s'"), string);
2607
d02603dc 2608 (void) restore_line_pointer (e);
fddf5b5b
AM		 2609 }
2610
e413e4e9
AM		 2611 demand_empty_rest_of_line ();
2612}
2613
8a9036a4
L		 2614enum bfd_architecture
2615i386_arch (void)
2616{
3632d14b 2617 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2618 {
2619 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2620 || flag_code != CODE_64BIT)
2621 as_fatal (_("Intel L1OM is 64bit ELF only"));
2622 return bfd_arch_l1om;
2623 }
7a9068fe
L		 2624 else if (cpu_arch_isa == PROCESSOR_K1OM)
2625 {
2626 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2627 || flag_code != CODE_64BIT)
2628 as_fatal (_("Intel K1OM is 64bit ELF only"));
2629 return bfd_arch_k1om;
2630 }
81486035
L		 2631 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2632 {
2633 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2634 || flag_code == CODE_64BIT)
2635 as_fatal (_("Intel MCU is 32bit ELF only"));
2636 return bfd_arch_iamcu;
2637 }
8a9036a4
L		 2638 else
2639 return bfd_arch_i386;
2640}
2641
b9d79e03 2642unsigned long
7016a5d5 2643i386_mach (void)
b9d79e03 2644{
351f65ca 2645 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2646 {
3632d14b 2647 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2648 {
351f65ca
L		 2649 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2650 || default_arch[6] != '\0')
8a9036a4
L		 2651 as_fatal (_("Intel L1OM is 64bit ELF only"));
2652 return bfd_mach_l1om;
2653 }
7a9068fe
L		 2654 else if (cpu_arch_isa == PROCESSOR_K1OM)
2655 {
2656 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2657 || default_arch[6] != '\0')
2658 as_fatal (_("Intel K1OM is 64bit ELF only"));
2659 return bfd_mach_k1om;
2660 }
351f65ca 2661 else if (default_arch[6] == '\0')
8a9036a4 2662 return bfd_mach_x86_64;
351f65ca
L		 2663 else
2664 return bfd_mach_x64_32;
8a9036a4 2665 }
5197d474
L		 2666 else if (!strcmp (default_arch, "i386")
2667 || !strcmp (default_arch, "iamcu"))
81486035
L		 2668 {
2669 if (cpu_arch_isa == PROCESSOR_IAMCU)
2670 {
2671 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2672 as_fatal (_("Intel MCU is 32bit ELF only"));
2673 return bfd_mach_i386_iamcu;
2674 }
2675 else
2676 return bfd_mach_i386_i386;
2677 }
b9d79e03 2678 else
2b5d6a91 2679 as_fatal (_("unknown architecture"));
b9d79e03 2680}
b9d79e03 2681\f
252b5132 2682void
7016a5d5 2683md_begin (void)
252b5132
RH		 2684{
2685 const char *hash_err;
2686
86fa6981
L		 2687 /* Support pseudo prefixes like {disp32}. */
2688 lex_type ['{'] = LEX_BEGIN_NAME;
2689
47926f60 2690 /* Initialize op_hash hash table. */
252b5132
RH		 2691 op_hash = hash_new ();
2692
2693 {
d3ce72d0 2694 const insn_template *optab;
29b0f896 2695 templates *core_optab;
252b5132 2696
47926f60
KH		 2697 /* Setup for loop. */
2698 optab = i386_optab;
add39d23 2699 core_optab = XNEW (templates);
252b5132
RH		 2700 core_optab->start = optab;
2701
2702 while (1)
2703 {
2704 ++optab;
2705 if (optab->name == NULL
2706 || strcmp (optab->name, (optab - 1)->name) != 0)
2707 {
2708 /* different name --> ship out current template list;
47926f60 2709 add to hash table; & begin anew. */
252b5132
RH		 2710 core_optab->end = optab;
2711 hash_err = hash_insert (op_hash,
2712 (optab - 1)->name,
5a49b8ac 2713 (void *) core_optab);
252b5132
RH		 2714 if (hash_err)
2715 {
b37df7c4 2716 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2717 (optab - 1)->name,
2718 hash_err);
2719 }
2720 if (optab->name == NULL)
2721 break;
add39d23 2722 core_optab = XNEW (templates);
252b5132
RH		 2723 core_optab->start = optab;
2724 }
2725 }
2726 }
2727
47926f60 2728 /* Initialize reg_hash hash table. */
252b5132
RH		 2729 reg_hash = hash_new ();
2730 {
29b0f896 2731 const reg_entry *regtab;
c3fe08fa 2732 unsigned int regtab_size = i386_regtab_size;
252b5132 2733
c3fe08fa 2734 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2735 {
5a49b8ac 2736 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2737 if (hash_err)
b37df7c4 2738 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2739 regtab->reg_name,
2740 hash_err);
252b5132
RH		 2741 }
2742 }
2743
47926f60 2744 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2745 {
29b0f896
AM		 2746 int c;
2747 char *p;
252b5132
RH		 2748
2749 for (c = 0; c < 256; c++)
2750 {
3882b010 2751 if (ISDIGIT (c))
252b5132
RH		 2752 {
2753 digit_chars[c] = c;
2754 mnemonic_chars[c] = c;
2755 register_chars[c] = c;
2756 operand_chars[c] = c;
2757 }
3882b010 2758 else if (ISLOWER (c))
252b5132
RH		 2759 {
2760 mnemonic_chars[c] = c;
2761 register_chars[c] = c;
2762 operand_chars[c] = c;
2763 }
3882b010 2764 else if (ISUPPER (c))
252b5132 2765 {
3882b010 2766 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2767 register_chars[c] = mnemonic_chars[c];
2768 operand_chars[c] = c;
2769 }
43234a1e 2770 else if (c == '{' || c == '}')
86fa6981
L		 2771 {
2772 mnemonic_chars[c] = c;
2773 operand_chars[c] = c;
2774 }
252b5132 2775
3882b010 2776 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2777 identifier_chars[c] = c;
2778 else if (c >= 128)
2779 {
2780 identifier_chars[c] = c;
2781 operand_chars[c] = c;
2782 }
2783 }
2784
2785#ifdef LEX_AT
2786 identifier_chars['@'] = '@';
32137342
NC		 2787#endif
2788#ifdef LEX_QM
2789 identifier_chars['?'] = '?';
2790 operand_chars['?'] = '?';
252b5132 2791#endif
252b5132 2792 digit_chars['-'] = '-';
c0f3af97 2793 mnemonic_chars['_'] = '_';
791fe849 2794 mnemonic_chars['-'] = '-';
0003779b 2795 mnemonic_chars['.'] = '.';
252b5132
RH		 2796 identifier_chars['_'] = '_';
2797 identifier_chars['.'] = '.';
2798
2799 for (p = operand_special_chars; *p != '\0'; p++)
2800 operand_chars[(unsigned char) *p] = *p;
2801 }
2802
a4447b93
RH		 2803 if (flag_code == CODE_64BIT)
2804 {
ca19b261
KT		 2805#if defined (OBJ_COFF) && defined (TE_PE)
2806 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2807 ? 32 : 16);
2808#else
a4447b93 2809 x86_dwarf2_return_column = 16;
ca19b261 2810#endif
61ff971f 2811 x86_cie_data_alignment = -8;
a4447b93
RH		 2812 }
2813 else
2814 {
2815 x86_dwarf2_return_column = 8;
2816 x86_cie_data_alignment = -4;
2817 }
252b5132
RH		 2818}
2819
2820void
e3bb37b5 2821i386_print_statistics (FILE *file)
252b5132
RH		 2822{
2823 hash_print_statistics (file, "i386 opcode", op_hash);
2824 hash_print_statistics (file, "i386 register", reg_hash);
2825}
2826\f
252b5132
RH		 2827#ifdef DEBUG386
2828
ce8a8b2f 2829/* Debugging routines for md_assemble. */
d3ce72d0 2830static void pte (insn_template *);
40fb9820 2831static void pt (i386_operand_type);
e3bb37b5
L		 2832static void pe (expressionS *);
2833static void ps (symbolS *);
252b5132
RH		 2834
2835static void
e3bb37b5 2836pi (char *line, i386_insn *x)
252b5132 2837{
09137c09 2838 unsigned int j;
252b5132
RH		 2839
2840 fprintf (stdout, "%s: template ", line);
2841 pte (&x->tm);
09f131f2
JH		 2842 fprintf (stdout, " address: base %s index %s scale %x\n",
2843 x->base_reg ? x->base_reg->reg_name : "none",
2844 x->index_reg ? x->index_reg->reg_name : "none",
2845 x->log2_scale_factor);
2846 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2847 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2848 fprintf (stdout, " sib: base %x index %x scale %x\n",
2849 x->sib.base, x->sib.index, x->sib.scale);
2850 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2851 (x->rex & REX_W) != 0,
2852 (x->rex & REX_R) != 0,
2853 (x->rex & REX_X) != 0,
2854 (x->rex & REX_B) != 0);
09137c09 2855 for (j = 0; j < x->operands; j++)
252b5132 2856 {
09137c09
SP		 2857 fprintf (stdout, " #%d: ", j + 1);
2858 pt (x->types[j]);
252b5132 2859 fprintf (stdout, "\n");
dc821c5f 2860 if (x->types[j].bitfield.reg
09137c09 2861 || x->types[j].bitfield.regmmx
1b54b8d7 2862 || x->types[j].bitfield.regsimd
09137c09
SP		 2863 || x->types[j].bitfield.sreg2
2864 || x->types[j].bitfield.sreg3
2865 || x->types[j].bitfield.control
2866 || x->types[j].bitfield.debug
2867 || x->types[j].bitfield.test)
2868 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2869 if (operand_type_check (x->types[j], imm))
2870 pe (x->op[j].imms);
2871 if (operand_type_check (x->types[j], disp))
2872 pe (x->op[j].disps);
252b5132
RH		 2873 }
2874}
2875
2876static void
d3ce72d0 2877pte (insn_template *t)
252b5132 2878{
09137c09 2879 unsigned int j;
252b5132 2880 fprintf (stdout, " %d operands ", t->operands);
47926f60 2881 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2882 if (t->extension_opcode != None)
2883 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2884 if (t->opcode_modifier.d)
252b5132 2885 fprintf (stdout, "D");
40fb9820 2886 if (t->opcode_modifier.w)
252b5132
RH		 2887 fprintf (stdout, "W");
2888 fprintf (stdout, "\n");
09137c09 2889 for (j = 0; j < t->operands; j++)
252b5132 2890 {
09137c09
SP		 2891 fprintf (stdout, " #%d type ", j + 1);
2892 pt (t->operand_types[j]);
252b5132
RH		 2893 fprintf (stdout, "\n");
2894 }
2895}
2896
2897static void
e3bb37b5 2898pe (expressionS *e)
252b5132 2899{
24eab124 2900 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2901 fprintf (stdout, " add_number %ld (%lx)\n",
2902 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2903 if (e->X_add_symbol)
2904 {
2905 fprintf (stdout, " add_symbol ");
2906 ps (e->X_add_symbol);
2907 fprintf (stdout, "\n");
2908 }
2909 if (e->X_op_symbol)
2910 {
2911 fprintf (stdout, " op_symbol ");
2912 ps (e->X_op_symbol);
2913 fprintf (stdout, "\n");
2914 }
2915}
2916
2917static void
e3bb37b5 2918ps (symbolS *s)
252b5132
RH		 2919{
2920 fprintf (stdout, "%s type %s%s",
2921 S_GET_NAME (s),
2922 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2923 segment_name (S_GET_SEGMENT (s)));
2924}
2925
7b81dfbb 2926static struct type_name
252b5132 2927 {
40fb9820
L		 2928 i386_operand_type mask;
2929 const char *name;
252b5132 2930 }
7b81dfbb 2931const type_names[] =
252b5132 2932{
40fb9820
L		 2933 { OPERAND_TYPE_REG8, "r8" },
2934 { OPERAND_TYPE_REG16, "r16" },
2935 { OPERAND_TYPE_REG32, "r32" },
2936 { OPERAND_TYPE_REG64, "r64" },
2937 { OPERAND_TYPE_IMM8, "i8" },
2938 { OPERAND_TYPE_IMM8, "i8s" },
2939 { OPERAND_TYPE_IMM16, "i16" },
2940 { OPERAND_TYPE_IMM32, "i32" },
2941 { OPERAND_TYPE_IMM32S, "i32s" },
2942 { OPERAND_TYPE_IMM64, "i64" },
2943 { OPERAND_TYPE_IMM1, "i1" },
2944 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2945 { OPERAND_TYPE_DISP8, "d8" },
2946 { OPERAND_TYPE_DISP16, "d16" },
2947 { OPERAND_TYPE_DISP32, "d32" },
2948 { OPERAND_TYPE_DISP32S, "d32s" },
2949 { OPERAND_TYPE_DISP64, "d64" },
2950 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2951 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2952 { OPERAND_TYPE_CONTROL, "control reg" },
2953 { OPERAND_TYPE_TEST, "test reg" },
2954 { OPERAND_TYPE_DEBUG, "debug reg" },
2955 { OPERAND_TYPE_FLOATREG, "FReg" },
2956 { OPERAND_TYPE_FLOATACC, "FAcc" },
2957 { OPERAND_TYPE_SREG2, "SReg2" },
2958 { OPERAND_TYPE_SREG3, "SReg3" },
2959 { OPERAND_TYPE_ACC, "Acc" },
2960 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2961 { OPERAND_TYPE_REGMMX, "rMMX" },
2962 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2963 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2964 { OPERAND_TYPE_REGZMM, "rZMM" },
2965 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2966 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2967};
2968
2969static void
40fb9820 2970pt (i386_operand_type t)
252b5132 2971{
40fb9820 2972 unsigned int j;
c6fb90c8 2973 i386_operand_type a;
252b5132 2974
40fb9820 2975 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2976 {
2977 a = operand_type_and (t, type_names[j].mask);
0349dc08 2978 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2979 fprintf (stdout, "%s, ", type_names[j].name);
2980 }
252b5132
RH		 2981 fflush (stdout);
2982}
2983
2984#endif /* DEBUG386 */
2985\f
252b5132 2986static bfd_reloc_code_real_type
3956db08 2987reloc (unsigned int size,
64e74474
AM		 2988 int pcrel,
2989 int sign,
2990 bfd_reloc_code_real_type other)
252b5132 2991{
47926f60 2992 if (other != NO_RELOC)
3956db08 2993 {
91d6fa6a 2994 reloc_howto_type *rel;
3956db08
JB		 2995
2996 if (size == 8)
2997 switch (other)
2998 {
64e74474
AM		 2999 case BFD_RELOC_X86_64_GOT32:
3000 return BFD_RELOC_X86_64_GOT64;
3001 break;
553d1284
L		 3002 case BFD_RELOC_X86_64_GOTPLT64:
3003 return BFD_RELOC_X86_64_GOTPLT64;
3004 break;
64e74474
AM		 3005 case BFD_RELOC_X86_64_PLTOFF64:
3006 return BFD_RELOC_X86_64_PLTOFF64;
3007 break;
3008 case BFD_RELOC_X86_64_GOTPC32:
3009 other = BFD_RELOC_X86_64_GOTPC64;
3010 break;
3011 case BFD_RELOC_X86_64_GOTPCREL:
3012 other = BFD_RELOC_X86_64_GOTPCREL64;
3013 break;
3014 case BFD_RELOC_X86_64_TPOFF32:
3015 other = BFD_RELOC_X86_64_TPOFF64;
3016 break;
3017 case BFD_RELOC_X86_64_DTPOFF32:
3018 other = BFD_RELOC_X86_64_DTPOFF64;
3019 break;
3020 default:
3021 break;
3956db08 3022 }
e05278af 3023
8ce3d284 3024#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3025 if (other == BFD_RELOC_SIZE32)
3026 {
3027 if (size == 8)
1ab668bf 3028 other = BFD_RELOC_SIZE64;
8fd4256d 3029 if (pcrel)
1ab668bf
AM		 3030 {
3031 as_bad (_("there are no pc-relative size relocations"));
3032 return NO_RELOC;
3033 }
8fd4256d 3034 }
8ce3d284 3035#endif
8fd4256d 3036
e05278af 3037 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3038 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3039 sign = -1;
3040
91d6fa6a
NC		 3041 rel = bfd_reloc_type_lookup (stdoutput, other);
3042 if (!rel)
3956db08 3043 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3044 else if (size != bfd_get_reloc_size (rel))
3956db08 3045 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3046 bfd_get_reloc_size (rel),
3956db08 3047 size);
91d6fa6a 3048 else if (pcrel && !rel->pc_relative)
3956db08 3049 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3050 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3051 && !sign)
91d6fa6a 3052 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3053 && sign > 0))
3956db08
JB		 3054 as_bad (_("relocated field and relocation type differ in signedness"));
3055 else
3056 return other;
3057 return NO_RELOC;
3058 }
252b5132
RH		 3059
3060 if (pcrel)
3061 {
3e73aa7c 3062 if (!sign)
3956db08 3063 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3064 switch (size)
3065 {
3066 case 1: return BFD_RELOC_8_PCREL;
3067 case 2: return BFD_RELOC_16_PCREL;
d258b828 3068 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3069 case 8: return BFD_RELOC_64_PCREL;
252b5132 3070 }
3956db08 3071 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3072 }
3073 else
3074 {
3956db08 3075 if (sign > 0)
e5cb08ac 3076 switch (size)
3e73aa7c
JH		 3077 {
3078 case 4: return BFD_RELOC_X86_64_32S;
3079 }
3080 else
3081 switch (size)
3082 {
3083 case 1: return BFD_RELOC_8;
3084 case 2: return BFD_RELOC_16;
3085 case 4: return BFD_RELOC_32;
3086 case 8: return BFD_RELOC_64;
3087 }
3956db08
JB		 3088 as_bad (_("cannot do %s %u byte relocation"),
3089 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3090 }
3091
0cc9e1d3 3092 return NO_RELOC;
252b5132
RH		 3093}
3094
47926f60
KH		 3095/* Here we decide which fixups can be adjusted to make them relative to
3096 the beginning of the section instead of the symbol. Basically we need
3097 to make sure that the dynamic relocations are done correctly, so in
3098 some cases we force the original symbol to be used. */
3099
252b5132 3100int
e3bb37b5 3101tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3102{
6d249963 3103#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3104 if (!IS_ELF)
31312f95
AM		 3105 return 1;
3106
a161fe53
AM		 3107 /* Don't adjust pc-relative references to merge sections in 64-bit
3108 mode. */
3109 if (use_rela_relocations
3110 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3111 && fixP->fx_pcrel)
252b5132 3112 return 0;
31312f95 3113
8d01d9a9
AJ		 3114 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3115 and changed later by validate_fix. */
3116 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3117 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3118 return 0;
3119
8fd4256d
L		 3120 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3121 for size relocations. */
3122 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3123 || fixP->fx_r_type == BFD_RELOC_SIZE64
3124 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3125 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3126 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3127 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3128 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3129 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3130 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3131 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3132 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3133 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3134 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3135 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3136 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3137 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3138 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3139 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3140 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3141 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3142 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3143 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3144 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3145 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3146 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3147 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3148 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3149 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3150 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3151 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3152 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3153 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3154 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3155 return 0;
31312f95 3156#endif
252b5132
RH		 3157 return 1;
3158}
252b5132 3159
b4cac588 3160static int
e3bb37b5 3161intel_float_operand (const char *mnemonic)
252b5132 3162{
9306ca4a
JB		 3163 /* Note that the value returned is meaningful only for opcodes with (memory)
3164 operands, hence the code here is free to improperly handle opcodes that
3165 have no operands (for better performance and smaller code). */
3166
3167 if (mnemonic[0] != 'f')
3168 return 0; /* non-math */
3169
3170 switch (mnemonic[1])
3171 {
3172 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3173 the fs segment override prefix not currently handled because no
3174 call path can make opcodes without operands get here */
3175 case 'i':
3176 return 2 /* integer op */;
3177 case 'l':
3178 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3179 return 3; /* fldcw/fldenv */
3180 break;
3181 case 'n':
3182 if (mnemonic[2] != 'o' /* fnop */)
3183 return 3; /* non-waiting control op */
3184 break;
3185 case 'r':
3186 if (mnemonic[2] == 's')
3187 return 3; /* frstor/frstpm */
3188 break;
3189 case 's':
3190 if (mnemonic[2] == 'a')
3191 return 3; /* fsave */
3192 if (mnemonic[2] == 't')
3193 {
3194 switch (mnemonic[3])
3195 {
3196 case 'c': /* fstcw */
3197 case 'd': /* fstdw */
3198 case 'e': /* fstenv */
3199 case 's': /* fsts[gw] */
3200 return 3;
3201 }
3202 }
3203 break;
3204 case 'x':
3205 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3206 return 0; /* fxsave/fxrstor are not really math ops */
3207 break;
3208 }
252b5132 3209
9306ca4a 3210 return 1;
252b5132
RH		 3211}
3212
c0f3af97
L		 3213/* Build the VEX prefix. */
3214
3215static void
d3ce72d0 3216build_vex_prefix (const insn_template *t)
c0f3af97
L		 3217{
3218 unsigned int register_specifier;
3219 unsigned int implied_prefix;
3220 unsigned int vector_length;
3221
3222 /* Check register specifier. */
3223 if (i.vex.register_specifier)
43234a1e
L		 3224 {
3225 register_specifier =
3226 ~register_number (i.vex.register_specifier) & 0xf;
3227 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3228 }
c0f3af97
L		 3229 else
3230 register_specifier = 0xf;
3231
33eaf5de 3232 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3233 operand. */
86fa6981
L		 3234 if (i.vec_encoding != vex_encoding_vex3
3235 && i.dir_encoding == dir_encoding_default
fa99fab2 3236 && i.operands == i.reg_operands
7f399153 3237 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3238 && i.tm.opcode_modifier.load
fa99fab2
L		 3239 && i.rex == REX_B)
3240 {
3241 unsigned int xchg = i.operands - 1;
3242 union i386_op temp_op;
3243 i386_operand_type temp_type;
3244
3245 temp_type = i.types[xchg];
3246 i.types[xchg] = i.types[0];
3247 i.types[0] = temp_type;
3248 temp_op = i.op[xchg];
3249 i.op[xchg] = i.op[0];
3250 i.op[0] = temp_op;
3251
9c2799c2 3252 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3253
3254 i.rex = REX_R;
3255 xchg = i.rm.regmem;
3256 i.rm.regmem = i.rm.reg;
3257 i.rm.reg = xchg;
3258
3259 /* Use the next insn. */
3260 i.tm = t[1];
3261 }
3262
539f890d
L		 3263 if (i.tm.opcode_modifier.vex == VEXScalar)
3264 vector_length = avxscalar;
10c17abd
JB		 3265 else if (i.tm.opcode_modifier.vex == VEX256)
3266 vector_length = 1;
539f890d 3267 else
10c17abd
JB		 3268 {
3269 unsigned int op;
3270
3271 vector_length = 0;
3272 for (op = 0; op < t->operands; ++op)
3273 if (t->operand_types[op].bitfield.xmmword
3274 && t->operand_types[op].bitfield.ymmword
3275 && i.types[op].bitfield.ymmword)
3276 {
3277 vector_length = 1;
3278 break;
3279 }
3280 }
c0f3af97
L		 3281
3282 switch ((i.tm.base_opcode >> 8) & 0xff)
3283 {
3284 case 0:
3285 implied_prefix = 0;
3286 break;
3287 case DATA_PREFIX_OPCODE:
3288 implied_prefix = 1;
3289 break;
3290 case REPE_PREFIX_OPCODE:
3291 implied_prefix = 2;
3292 break;
3293 case REPNE_PREFIX_OPCODE:
3294 implied_prefix = 3;
3295 break;
3296 default:
3297 abort ();
3298 }
3299
3300 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3301 if (i.vec_encoding != vex_encoding_vex3
3302 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3303 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3304 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3305 {
3306 /* 2-byte VEX prefix. */
3307 unsigned int r;
3308
3309 i.vex.length = 2;
3310 i.vex.bytes[0] = 0xc5;
3311
3312 /* Check the REX.R bit. */
3313 r = (i.rex & REX_R) ? 0 : 1;
3314 i.vex.bytes[1] = (r << 7
3315 | register_specifier << 3
3316 | vector_length << 2
3317 | implied_prefix);
3318 }
3319 else
3320 {
3321 /* 3-byte VEX prefix. */
3322 unsigned int m, w;
3323
f88c9eb0 3324 i.vex.length = 3;
f88c9eb0 3325
7f399153 3326 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3327 {
7f399153
L		 3328 case VEX0F:
3329 m = 0x1;
80de6e00 3330 i.vex.bytes[0] = 0xc4;
7f399153
L		 3331 break;
3332 case VEX0F38:
3333 m = 0x2;
80de6e00 3334 i.vex.bytes[0] = 0xc4;
7f399153
L		 3335 break;
3336 case VEX0F3A:
3337 m = 0x3;
80de6e00 3338 i.vex.bytes[0] = 0xc4;
7f399153
L		 3339 break;
3340 case XOP08:
5dd85c99
SP		 3341 m = 0x8;
3342 i.vex.bytes[0] = 0x8f;
7f399153
L		 3343 break;
3344 case XOP09:
f88c9eb0
SP		 3345 m = 0x9;
3346 i.vex.bytes[0] = 0x8f;
7f399153
L		 3347 break;
3348 case XOP0A:
f88c9eb0
SP		 3349 m = 0xa;
3350 i.vex.bytes[0] = 0x8f;
7f399153
L		 3351 break;
3352 default:
3353 abort ();
f88c9eb0 3354 }
c0f3af97 3355
c0f3af97
L		 3356 /* The high 3 bits of the second VEX byte are 1's compliment
3357 of RXB bits from REX. */
3358 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3359
3360 /* Check the REX.W bit. */
3361 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3362 if (i.tm.opcode_modifier.vexw == VEXW1)
3363 w = 1;
c0f3af97
L		 3364
3365 i.vex.bytes[2] = (w << 7
3366 | register_specifier << 3
3367 | vector_length << 2
3368 | implied_prefix);
3369 }
3370}
3371
43234a1e
L		 3372/* Build the EVEX prefix. */
3373
3374static void
3375build_evex_prefix (void)
3376{
3377 unsigned int register_specifier;
3378 unsigned int implied_prefix;
3379 unsigned int m, w;
3380 rex_byte vrex_used = 0;
3381
3382 /* Check register specifier. */
3383 if (i.vex.register_specifier)
3384 {
3385 gas_assert ((i.vrex & REX_X) == 0);
3386
3387 register_specifier = i.vex.register_specifier->reg_num;
3388 if ((i.vex.register_specifier->reg_flags & RegRex))
3389 register_specifier += 8;
3390 /* The upper 16 registers are encoded in the fourth byte of the
3391 EVEX prefix. */
3392 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3393 i.vex.bytes[3] = 0x8;
3394 register_specifier = ~register_specifier & 0xf;
3395 }
3396 else
3397 {
3398 register_specifier = 0xf;
3399
3400 /* Encode upper 16 vector index register in the fourth byte of
3401 the EVEX prefix. */
3402 if (!(i.vrex & REX_X))
3403 i.vex.bytes[3] = 0x8;
3404 else
3405 vrex_used |= REX_X;
3406 }
3407
3408 switch ((i.tm.base_opcode >> 8) & 0xff)
3409 {
3410 case 0:
3411 implied_prefix = 0;
3412 break;
3413 case DATA_PREFIX_OPCODE:
3414 implied_prefix = 1;
3415 break;
3416 case REPE_PREFIX_OPCODE:
3417 implied_prefix = 2;
3418 break;
3419 case REPNE_PREFIX_OPCODE:
3420 implied_prefix = 3;
3421 break;
3422 default:
3423 abort ();
3424 }
3425
3426 /* 4 byte EVEX prefix. */
3427 i.vex.length = 4;
3428 i.vex.bytes[0] = 0x62;
3429
3430 /* mmmm bits. */
3431 switch (i.tm.opcode_modifier.vexopcode)
3432 {
3433 case VEX0F:
3434 m = 1;
3435 break;
3436 case VEX0F38:
3437 m = 2;
3438 break;
3439 case VEX0F3A:
3440 m = 3;
3441 break;
3442 default:
3443 abort ();
3444 break;
3445 }
3446
3447 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3448 bits from REX. */
3449 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3450
3451 /* The fifth bit of the second EVEX byte is 1's compliment of the
3452 REX_R bit in VREX. */
3453 if (!(i.vrex & REX_R))
3454 i.vex.bytes[1] |= 0x10;
3455 else
3456 vrex_used |= REX_R;
3457
3458 if ((i.reg_operands + i.imm_operands) == i.operands)
3459 {
3460 /* When all operands are registers, the REX_X bit in REX is not
3461 used. We reuse it to encode the upper 16 registers, which is
3462 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3463 as 1's compliment. */
3464 if ((i.vrex & REX_B))
3465 {
3466 vrex_used |= REX_B;
3467 i.vex.bytes[1] &= ~0x40;
3468 }
3469 }
3470
3471 /* EVEX instructions shouldn't need the REX prefix. */
3472 i.vrex &= ~vrex_used;
3473 gas_assert (i.vrex == 0);
3474
3475 /* Check the REX.W bit. */
3476 w = (i.rex & REX_W) ? 1 : 0;
3477 if (i.tm.opcode_modifier.vexw)
3478 {
3479 if (i.tm.opcode_modifier.vexw == VEXW1)
3480 w = 1;
3481 }
3482 /* If w is not set it means we are dealing with WIG instruction. */
3483 else if (!w)
3484 {
3485 if (evexwig == evexw1)
3486 w = 1;
3487 }
3488
3489 /* Encode the U bit. */
3490 implied_prefix |= 0x4;
3491
3492 /* The third byte of the EVEX prefix. */
3493 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3494
3495 /* The fourth byte of the EVEX prefix. */
3496 /* The zeroing-masking bit. */
3497 if (i.mask && i.mask->zeroing)
3498 i.vex.bytes[3] |= 0x80;
3499
3500 /* Don't always set the broadcast bit if there is no RC. */
3501 if (!i.rounding)
3502 {
3503 /* Encode the vector length. */
3504 unsigned int vec_length;
3505
3506 switch (i.tm.opcode_modifier.evex)
3507 {
3508 case EVEXLIG: /* LL' is ignored */
3509 vec_length = evexlig << 5;
3510 break;
3511 case EVEX128:
3512 vec_length = 0 << 5;
3513 break;
3514 case EVEX256:
3515 vec_length = 1 << 5;
3516 break;
3517 case EVEX512:
3518 vec_length = 2 << 5;
3519 break;
3520 default:
3521 abort ();
3522 break;
3523 }
3524 i.vex.bytes[3] |= vec_length;
3525 /* Encode the broadcast bit. */
3526 if (i.broadcast)
3527 i.vex.bytes[3] |= 0x10;
3528 }
3529 else
3530 {
3531 if (i.rounding->type != saeonly)
3532 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3533 else
d3d3c6db 3534 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3535 }
3536
3537 if (i.mask && i.mask->mask)
3538 i.vex.bytes[3] |= i.mask->mask->reg_num;
3539}
3540
65da13b5
L		 3541static void
3542process_immext (void)
3543{
3544 expressionS *exp;
3545
4c692bc7
JB		 3546 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3547 && i.operands > 0)
65da13b5 3548 {
4c692bc7
JB		 3549 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3550 with an opcode suffix which is coded in the same place as an
3551 8-bit immediate field would be.
3552 Here we check those operands and remove them afterwards. */
65da13b5
L		 3553 unsigned int x;
3554
3555 for (x = 0; x < i.operands; x++)
4c692bc7 3556 if (register_number (i.op[x].regs) != x)
65da13b5 3557 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3558 register_prefix, i.op[x].regs->reg_name, x + 1,
3559 i.tm.name);
3560
3561 i.operands = 0;
65da13b5
L		 3562 }
3563
9916071f
AP		 3564 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3565 {
3566 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3567 suffix which is coded in the same place as an 8-bit immediate
3568 field would be.
3569 Here we check those operands and remove them afterwards. */
3570 unsigned int x;
3571
3572 if (i.operands != 3)
3573 abort();
3574
3575 for (x = 0; x < 2; x++)
3576 if (register_number (i.op[x].regs) != x)
3577 goto bad_register_operand;
3578
3579 /* Check for third operand for mwaitx/monitorx insn. */
3580 if (register_number (i.op[x].regs)
3581 != (x + (i.tm.extension_opcode == 0xfb)))
3582 {
3583bad_register_operand:
3584 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3585 register_prefix, i.op[x].regs->reg_name, x+1,
3586 i.tm.name);
3587 }
3588
3589 i.operands = 0;
3590 }
3591
c0f3af97 3592 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3593 which is coded in the same place as an 8-bit immediate field
3594 would be. Here we fake an 8-bit immediate operand from the
3595 opcode suffix stored in tm.extension_opcode.
3596
c1e679ec 3597 AVX instructions also use this encoding, for some of
c0f3af97 3598 3 argument instructions. */
65da13b5 3599
43234a1e 3600 gas_assert (i.imm_operands <= 1
7ab9ffdd 3601 && (i.operands <= 2
43234a1e
L		 3602 || ((i.tm.opcode_modifier.vex
3603 || i.tm.opcode_modifier.evex)
7ab9ffdd 3604 && i.operands <= 4)));
65da13b5
L		 3605
3606 exp = &im_expressions[i.imm_operands++];
3607 i.op[i.operands].imms = exp;
3608 i.types[i.operands] = imm8;
3609 i.operands++;
3610 exp->X_op = O_constant;
3611 exp->X_add_number = i.tm.extension_opcode;
3612 i.tm.extension_opcode = None;
3613}
3614
42164a71
L		 3615
3616static int
3617check_hle (void)
3618{
3619 switch (i.tm.opcode_modifier.hleprefixok)
3620 {
3621 default:
3622 abort ();
82c2def5 3623 case HLEPrefixNone:
165de32a
L		 3624 as_bad (_("invalid instruction `%s' after `%s'"),
3625 i.tm.name, i.hle_prefix);
42164a71 3626 return 0;
82c2def5 3627 case HLEPrefixLock:
42164a71
L		 3628 if (i.prefix[LOCK_PREFIX])
3629 return 1;
165de32a 3630 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3631 return 0;
82c2def5 3632 case HLEPrefixAny:
42164a71 3633 return 1;
82c2def5 3634 case HLEPrefixRelease:
42164a71
L		 3635 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3636 {
3637 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3638 i.tm.name);
3639 return 0;
3640 }
3641 if (i.mem_operands == 0
3642 || !operand_type_check (i.types[i.operands - 1], anymem))
3643 {
3644 as_bad (_("memory destination needed for instruction `%s'"
3645 " after `xrelease'"), i.tm.name);
3646 return 0;
3647 }
3648 return 1;
3649 }
3650}
3651
252b5132
RH		 3652/* This is the guts of the machine-dependent assembler. LINE points to a
3653 machine dependent instruction. This function is supposed to emit
3654 the frags/bytes it assembles to. */
3655
3656void
65da13b5 3657md_assemble (char *line)
252b5132 3658{
40fb9820 3659 unsigned int j;
83b16ac6 3660 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3661 const insn_template *t;
252b5132 3662
47926f60 3663 /* Initialize globals. */
252b5132
RH		 3664 memset (&i, '\0', sizeof (i));
3665 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3666 i.reloc[j] = NO_RELOC;
252b5132
RH		 3667 memset (disp_expressions, '\0', sizeof (disp_expressions));
3668 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3669 save_stack_p = save_stack;
252b5132
RH		 3670
3671 /* First parse an instruction mnemonic & call i386_operand for the operands.
3672 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3673 start of a (possibly prefixed) mnemonic. */
252b5132 3674
29b0f896
AM		 3675 line = parse_insn (line, mnemonic);
3676 if (line == NULL)
3677 return;
83b16ac6 3678 mnem_suffix = i.suffix;
252b5132 3679
29b0f896 3680 line = parse_operands (line, mnemonic);
ee86248c 3681 this_operand = -1;
8325cc63
JB		 3682 xfree (i.memop1_string);
3683 i.memop1_string = NULL;
29b0f896
AM		 3684 if (line == NULL)
3685 return;
252b5132 3686
29b0f896
AM		 3687 /* Now we've parsed the mnemonic into a set of templates, and have the
3688 operands at hand. */
3689
3690 /* All intel opcodes have reversed operands except for "bound" and
3691 "enter". We also don't reverse intersegment "jmp" and "call"
3692 instructions with 2 immediate operands so that the immediate segment
050dfa73 3693 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3694 if (intel_syntax
3695 && i.operands > 1
29b0f896 3696 && (strcmp (mnemonic, "bound") != 0)
30123838 3697 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3698 && !(operand_type_check (i.types[0], imm)
3699 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3700 swap_operands ();
3701
ec56d5c0
JB		 3702 /* The order of the immediates should be reversed
3703 for 2 immediates extrq and insertq instructions */
3704 if (i.imm_operands == 2
3705 && (strcmp (mnemonic, "extrq") == 0
3706 || strcmp (mnemonic, "insertq") == 0))
3707 swap_2_operands (0, 1);
3708
29b0f896
AM		 3709 if (i.imm_operands)
3710 optimize_imm ();
3711
b300c311
L		 3712 /* Don't optimize displacement for movabs since it only takes 64bit
3713 displacement. */
3714 if (i.disp_operands
a501d77e 3715 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3716 && (flag_code != CODE_64BIT
3717 || strcmp (mnemonic, "movabs") != 0))
3718 optimize_disp ();
29b0f896
AM		 3719
3720 /* Next, we find a template that matches the given insn,
3721 making sure the overlap of the given operands types is consistent
3722 with the template operand types. */
252b5132 3723
83b16ac6 3724 if (!(t = match_template (mnem_suffix)))
29b0f896 3725 return;
252b5132 3726
7bab8ab5 3727 if (sse_check != check_none
81f8a913 3728 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3729 && (i.tm.cpu_flags.bitfield.cpusse
3730 || i.tm.cpu_flags.bitfield.cpusse2
3731 || i.tm.cpu_flags.bitfield.cpusse3
3732 || i.tm.cpu_flags.bitfield.cpussse3
3733 || i.tm.cpu_flags.bitfield.cpusse4_1
3734 || i.tm.cpu_flags.bitfield.cpusse4_2))
3735 {
7bab8ab5 3736 (sse_check == check_warning
daf50ae7
L		 3737 ? as_warn
3738 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3739 }
3740
321fd21e
L		 3741 /* Zap movzx and movsx suffix. The suffix has been set from
3742 "word ptr" or "byte ptr" on the source operand in Intel syntax
3743 or extracted from mnemonic in AT&T syntax. But we'll use
3744 the destination register to choose the suffix for encoding. */
3745 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3746 {
321fd21e
L		 3747 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3748 there is no suffix, the default will be byte extension. */
3749 if (i.reg_operands != 2
3750 && !i.suffix
7ab9ffdd 3751 && intel_syntax)
321fd21e
L		 3752 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3753
3754 i.suffix = 0;
cd61ebfe 3755 }
24eab124 3756
40fb9820 3757 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3758 if (!add_prefix (FWAIT_OPCODE))
3759 return;
252b5132 3760
d5de92cf
L		 3761 /* Check if REP prefix is OK. */
3762 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3763 {
3764 as_bad (_("invalid instruction `%s' after `%s'"),
3765 i.tm.name, i.rep_prefix);
3766 return;
3767 }
3768
c1ba0266
L		 3769 /* Check for lock without a lockable instruction. Destination operand
3770 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3771 if (i.prefix[LOCK_PREFIX]
3772 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3773 || i.mem_operands == 0
3774 || (i.tm.base_opcode != 0x86
3775 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3776 {
3777 as_bad (_("expecting lockable instruction after `lock'"));
3778 return;
3779 }
3780
42164a71 3781 /* Check if HLE prefix is OK. */
165de32a 3782 if (i.hle_prefix && !check_hle ())
42164a71
L		 3783 return;
3784
7e8b059b
L		 3785 /* Check BND prefix. */
3786 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3787 as_bad (_("expecting valid branch instruction after `bnd'"));
3788
04ef582a 3789 /* Check NOTRACK prefix. */
9fef80d6
L		 3790 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
3791 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 3792
327e8c42
JB		 3793 if (i.tm.cpu_flags.bitfield.cpumpx)
3794 {
3795 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3796 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3797 else if (flag_code != CODE_16BIT
3798 ? i.prefix[ADDR_PREFIX]
3799 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3800 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3801 }
7e8b059b
L		 3802
3803 /* Insert BND prefix. */
3804 if (add_bnd_prefix
3805 && i.tm.opcode_modifier.bndprefixok
3806 && !i.prefix[BND_PREFIX])
3807 add_prefix (BND_PREFIX_OPCODE);
3808
29b0f896 3809 /* Check string instruction segment overrides. */
40fb9820 3810 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3811 {
3812 if (!check_string ())
5dd0794d 3813 return;
fc0763e6 3814 i.disp_operands = 0;
29b0f896 3815 }
5dd0794d 3816
29b0f896
AM		 3817 if (!process_suffix ())
3818 return;
e413e4e9 3819
bc0844ae
L		 3820 /* Update operand types. */
3821 for (j = 0; j < i.operands; j++)
3822 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3823
29b0f896
AM		 3824 /* Make still unresolved immediate matches conform to size of immediate
3825 given in i.suffix. */
3826 if (!finalize_imm ())
3827 return;
252b5132 3828
40fb9820 3829 if (i.types[0].bitfield.imm1)
29b0f896 3830 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3831
9afe6eb8
L		 3832 /* We only need to check those implicit registers for instructions
3833 with 3 operands or less. */
3834 if (i.operands <= 3)
3835 for (j = 0; j < i.operands; j++)
3836 if (i.types[j].bitfield.inoutportreg
3837 || i.types[j].bitfield.shiftcount
1b54b8d7 3838 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 3839 i.reg_operands--;
40fb9820 3840
c0f3af97
L		 3841 /* ImmExt should be processed after SSE2AVX. */
3842 if (!i.tm.opcode_modifier.sse2avx
3843 && i.tm.opcode_modifier.immext)
65da13b5 3844 process_immext ();
252b5132 3845
29b0f896
AM		 3846 /* For insns with operands there are more diddles to do to the opcode. */
3847 if (i.operands)
3848 {
3849 if (!process_operands ())
3850 return;
3851 }
40fb9820 3852 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3853 {
3854 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3855 as_warn (_("translating to `%sp'"), i.tm.name);
3856 }
252b5132 3857
9e5e5283
L		 3858 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3859 {
3860 if (flag_code == CODE_16BIT)
3861 {
3862 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3863 i.tm.name);
3864 return;
3865 }
c0f3af97 3866
9e5e5283
L		 3867 if (i.tm.opcode_modifier.vex)
3868 build_vex_prefix (t);
3869 else
3870 build_evex_prefix ();
3871 }
43234a1e 3872
5dd85c99
SP		 3873 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3874 instructions may define INT_OPCODE as well, so avoid this corner
3875 case for those instructions that use MODRM. */
3876 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3877 && !i.tm.opcode_modifier.modrm
3878 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3879 {
3880 i.tm.base_opcode = INT3_OPCODE;
3881 i.imm_operands = 0;
3882 }
252b5132 3883
40fb9820
L		 3884 if ((i.tm.opcode_modifier.jump
3885 || i.tm.opcode_modifier.jumpbyte
3886 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3887 && i.op[0].disps->X_op == O_constant)
3888 {
3889 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3890 the absolute address given by the constant. Since ix86 jumps and
3891 calls are pc relative, we need to generate a reloc. */
3892 i.op[0].disps->X_add_symbol = &abs_symbol;
3893 i.op[0].disps->X_op = O_symbol;
3894 }
252b5132 3895
40fb9820 3896 if (i.tm.opcode_modifier.rex64)
161a04f6 3897 i.rex |= REX_W;
252b5132 3898
29b0f896
AM		 3899 /* For 8 bit registers we need an empty rex prefix. Also if the
3900 instruction already has a prefix, we need to convert old
3901 registers to new ones. */
773f551c 3902
dc821c5f 3903 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 3904 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 3905 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 3906 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 3907 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
3908 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 3909 && i.rex != 0))
3910 {
3911 int x;
726c5dcd 3912
29b0f896
AM		 3913 i.rex |= REX_OPCODE;
3914 for (x = 0; x < 2; x++)
3915 {
3916 /* Look for 8 bit operand that uses old registers. */
dc821c5f 3917 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 3918 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3919 {
29b0f896
AM		 3920 /* In case it is "hi" register, give up. */
3921 if (i.op[x].regs->reg_num > 3)
a540244d 3922 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3923 "instruction requiring REX prefix."),
a540244d 3924 register_prefix, i.op[x].regs->reg_name);
773f551c 3925
29b0f896
AM		 3926 /* Otherwise it is equivalent to the extended register.
3927 Since the encoding doesn't change this is merely
3928 cosmetic cleanup for debug output. */
3929
3930 i.op[x].regs = i.op[x].regs + 8;
773f551c 3931 }
29b0f896
AM		 3932 }
3933 }
773f551c 3934
7ab9ffdd 3935 if (i.rex != 0)
29b0f896
AM		 3936 add_prefix (REX_OPCODE | i.rex);
3937
3938 /* We are ready to output the insn. */
3939 output_insn ();
3940}
3941
3942static char *
e3bb37b5 3943parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3944{
3945 char *l = line;
3946 char *token_start = l;
3947 char *mnem_p;
5c6af06e 3948 int supported;
d3ce72d0 3949 const insn_template *t;
b6169b20 3950 char *dot_p = NULL;
29b0f896 3951
29b0f896
AM		 3952 while (1)
3953 {
3954 mnem_p = mnemonic;
3955 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3956 {
b6169b20
L		 3957 if (*mnem_p == '.')
3958 dot_p = mnem_p;
29b0f896
AM		 3959 mnem_p++;
3960 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3961 {
29b0f896
AM		 3962 as_bad (_("no such instruction: `%s'"), token_start);
3963 return NULL;
3964 }
3965 l++;
3966 }
3967 if (!is_space_char (*l)
3968 && *l != END_OF_INSN
e44823cf
JB		 3969 && (intel_syntax
3970 || (*l != PREFIX_SEPARATOR
3971 && *l != ',')))
29b0f896
AM		 3972 {
3973 as_bad (_("invalid character %s in mnemonic"),
3974 output_invalid (*l));
3975 return NULL;
3976 }
3977 if (token_start == l)
3978 {
e44823cf 3979 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3980 as_bad (_("expecting prefix; got nothing"));
3981 else
3982 as_bad (_("expecting mnemonic; got nothing"));
3983 return NULL;
3984 }
45288df1 3985
29b0f896 3986 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3987 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3988
29b0f896
AM		 3989 if (*l != END_OF_INSN
3990 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3991 && current_templates
40fb9820 3992 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3993 {
c6fb90c8 3994 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3995 {
3996 as_bad ((flag_code != CODE_64BIT
3997 ? _("`%s' is only supported in 64-bit mode")
3998 : _("`%s' is not supported in 64-bit mode")),
3999 current_templates->start->name);
4000 return NULL;
4001 }
29b0f896
AM		 4002 /* If we are in 16-bit mode, do not allow addr16 or data16.
4003 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 4004 if ((current_templates->start->opcode_modifier.size16
4005 || current_templates->start->opcode_modifier.size32)
29b0f896 4006 && flag_code != CODE_64BIT
40fb9820 4007 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 4008 ^ (flag_code == CODE_16BIT)))
4009 {
4010 as_bad (_("redundant %s prefix"),
4011 current_templates->start->name);
4012 return NULL;
45288df1 4013 }
86fa6981 4014 if (current_templates->start->opcode_length == 0)
29b0f896 4015 {
86fa6981
L		 4016 /* Handle pseudo prefixes. */
4017 switch (current_templates->start->base_opcode)
4018 {
4019 case 0x0:
4020 /* {disp8} */
4021 i.disp_encoding = disp_encoding_8bit;
4022 break;
4023 case 0x1:
4024 /* {disp32} */
4025 i.disp_encoding = disp_encoding_32bit;
4026 break;
4027 case 0x2:
4028 /* {load} */
4029 i.dir_encoding = dir_encoding_load;
4030 break;
4031 case 0x3:
4032 /* {store} */
4033 i.dir_encoding = dir_encoding_store;
4034 break;
4035 case 0x4:
4036 /* {vex2} */
4037 i.vec_encoding = vex_encoding_vex2;
4038 break;
4039 case 0x5:
4040 /* {vex3} */
4041 i.vec_encoding = vex_encoding_vex3;
4042 break;
4043 case 0x6:
4044 /* {evex} */
4045 i.vec_encoding = vex_encoding_evex;
4046 break;
4047 default:
4048 abort ();
4049 }
4050 }
4051 else
4052 {
4053 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4054 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4055 {
4e9ac44a
L		 4056 case PREFIX_EXIST:
4057 return NULL;
4058 case PREFIX_DS:
d777820b 4059 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4e9ac44a
L		 4060 i.notrack_prefix = current_templates->start->name;
4061 break;
4062 case PREFIX_REP:
4063 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4064 i.hle_prefix = current_templates->start->name;
4065 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4066 i.bnd_prefix = current_templates->start->name;
4067 else
4068 i.rep_prefix = current_templates->start->name;
4069 break;
4070 default:
4071 break;
86fa6981 4072 }
29b0f896
AM		 4073 }
4074 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4075 token_start = ++l;
4076 }
4077 else
4078 break;
4079 }
45288df1 4080
30a55f88 4081 if (!current_templates)
b6169b20 4082 {
f8a5c266
L		 4083 /* Check if we should swap operand or force 32bit displacement in
4084 encoding. */
30a55f88 4085 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4086 i.dir_encoding = dir_encoding_store;
8d63c93e 4087 else if (mnem_p - 3 == dot_p
a501d77e
L		 4088 && dot_p[1] == 'd'
4089 && dot_p[2] == '8')
4090 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4091 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4092 && dot_p[1] == 'd'
4093 && dot_p[2] == '3'
4094 && dot_p[3] == '2')
a501d77e 4095 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4096 else
4097 goto check_suffix;
4098 mnem_p = dot_p;
4099 *dot_p = '\0';
d3ce72d0 4100 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4101 }
4102
29b0f896
AM		 4103 if (!current_templates)
4104 {
b6169b20 4105check_suffix:
29b0f896
AM		 4106 /* See if we can get a match by trimming off a suffix. */
4107 switch (mnem_p[-1])
4108 {
4109 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4110 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4111 i.suffix = SHORT_MNEM_SUFFIX;
4112 else
1a0670f3 4113 /* Fall through. */
29b0f896
AM		 4114 case BYTE_MNEM_SUFFIX:
4115 case QWORD_MNEM_SUFFIX:
4116 i.suffix = mnem_p[-1];
4117 mnem_p[-1] = '\0';
d3ce72d0
NC		 4118 current_templates = (const templates *) hash_find (op_hash,
4119 mnemonic);
29b0f896
AM		 4120 break;
4121 case SHORT_MNEM_SUFFIX:
4122 case LONG_MNEM_SUFFIX:
4123 if (!intel_syntax)
4124 {
4125 i.suffix = mnem_p[-1];
4126 mnem_p[-1] = '\0';
d3ce72d0
NC		 4127 current_templates = (const templates *) hash_find (op_hash,
4128 mnemonic);
29b0f896
AM		 4129 }
4130 break;
252b5132 4131
29b0f896
AM		 4132 /* Intel Syntax. */
4133 case 'd':
4134 if (intel_syntax)
4135 {
9306ca4a 4136 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4137 i.suffix = SHORT_MNEM_SUFFIX;
4138 else
4139 i.suffix = LONG_MNEM_SUFFIX;
4140 mnem_p[-1] = '\0';
d3ce72d0
NC		 4141 current_templates = (const templates *) hash_find (op_hash,
4142 mnemonic);
29b0f896
AM		 4143 }
4144 break;
4145 }
4146 if (!current_templates)
4147 {
4148 as_bad (_("no such instruction: `%s'"), token_start);
4149 return NULL;
4150 }
4151 }
252b5132 4152
40fb9820
L		 4153 if (current_templates->start->opcode_modifier.jump
4154 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4155 {
4156 /* Check for a branch hint. We allow ",pt" and ",pn" for
4157 predict taken and predict not taken respectively.
4158 I'm not sure that branch hints actually do anything on loop
4159 and jcxz insns (JumpByte) for current Pentium4 chips. They
4160 may work in the future and it doesn't hurt to accept them
4161 now. */
4162 if (l[0] == ',' && l[1] == 'p')
4163 {
4164 if (l[2] == 't')
4165 {
4166 if (!add_prefix (DS_PREFIX_OPCODE))
4167 return NULL;
4168 l += 3;
4169 }
4170 else if (l[2] == 'n')
4171 {
4172 if (!add_prefix (CS_PREFIX_OPCODE))
4173 return NULL;
4174 l += 3;
4175 }
4176 }
4177 }
4178 /* Any other comma loses. */
4179 if (*l == ',')
4180 {
4181 as_bad (_("invalid character %s in mnemonic"),
4182 output_invalid (*l));
4183 return NULL;
4184 }
252b5132 4185
29b0f896 4186 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4187 supported = 0;
4188 for (t = current_templates->start; t < current_templates->end; ++t)
4189 {
c0f3af97
L		 4190 supported |= cpu_flags_match (t);
4191 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 4192 goto skip;
5c6af06e 4193 }
3629bb00 4194
c0f3af97 4195 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4196 {
4197 as_bad (flag_code == CODE_64BIT
4198 ? _("`%s' is not supported in 64-bit mode")
4199 : _("`%s' is only supported in 64-bit mode"),
4200 current_templates->start->name);
4201 return NULL;
4202 }
c0f3af97 4203 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4204 {
3629bb00 4205 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4206 current_templates->start->name,
41aacd83 4207 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4208 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4209 return NULL;
29b0f896 4210 }
3629bb00
L		 4211
4212skip:
4213 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4214 && (flag_code != CODE_16BIT))
29b0f896
AM		 4215 {
4216 as_warn (_("use .code16 to ensure correct addressing mode"));
4217 }
252b5132 4218
29b0f896
AM		 4219 return l;
4220}
252b5132 4221
29b0f896 4222static char *
e3bb37b5 4223parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4224{
4225 char *token_start;
3138f287 4226
29b0f896
AM		 4227 /* 1 if operand is pending after ','. */
4228 unsigned int expecting_operand = 0;
252b5132 4229
29b0f896
AM		 4230 /* Non-zero if operand parens not balanced. */
4231 unsigned int paren_not_balanced;
4232
4233 while (*l != END_OF_INSN)
4234 {
4235 /* Skip optional white space before operand. */
4236 if (is_space_char (*l))
4237 ++l;
d02603dc 4238 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4239 {
4240 as_bad (_("invalid character %s before operand %d"),
4241 output_invalid (*l),
4242 i.operands + 1);
4243 return NULL;
4244 }
d02603dc 4245 token_start = l; /* After white space. */
29b0f896
AM		 4246 paren_not_balanced = 0;
4247 while (paren_not_balanced || *l != ',')
4248 {
4249 if (*l == END_OF_INSN)
4250 {
4251 if (paren_not_balanced)
4252 {
4253 if (!intel_syntax)
4254 as_bad (_("unbalanced parenthesis in operand %d."),
4255 i.operands + 1);
4256 else
4257 as_bad (_("unbalanced brackets in operand %d."),
4258 i.operands + 1);
4259 return NULL;
4260 }
4261 else
4262 break; /* we are done */
4263 }
d02603dc 4264 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4265 {
4266 as_bad (_("invalid character %s in operand %d"),
4267 output_invalid (*l),
4268 i.operands + 1);
4269 return NULL;
4270 }
4271 if (!intel_syntax)
4272 {
4273 if (*l == '(')
4274 ++paren_not_balanced;
4275 if (*l == ')')
4276 --paren_not_balanced;
4277 }
4278 else
4279 {
4280 if (*l == '[')
4281 ++paren_not_balanced;
4282 if (*l == ']')
4283 --paren_not_balanced;
4284 }
4285 l++;
4286 }
4287 if (l != token_start)
4288 { /* Yes, we've read in another operand. */
4289 unsigned int operand_ok;
4290 this_operand = i.operands++;
4291 if (i.operands > MAX_OPERANDS)
4292 {
4293 as_bad (_("spurious operands; (%d operands/instruction max)"),
4294 MAX_OPERANDS);
4295 return NULL;
4296 }
9d46ce34 4297 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4298 /* Now parse operand adding info to 'i' as we go along. */
4299 END_STRING_AND_SAVE (l);
4300
4301 if (intel_syntax)
4302 operand_ok =
4303 i386_intel_operand (token_start,
4304 intel_float_operand (mnemonic));
4305 else
a7619375 4306 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4307
4308 RESTORE_END_STRING (l);
4309 if (!operand_ok)
4310 return NULL;
4311 }
4312 else
4313 {
4314 if (expecting_operand)
4315 {
4316 expecting_operand_after_comma:
4317 as_bad (_("expecting operand after ','; got nothing"));
4318 return NULL;
4319 }
4320 if (*l == ',')
4321 {
4322 as_bad (_("expecting operand before ','; got nothing"));
4323 return NULL;
4324 }
4325 }
7f3f1ea2 4326
29b0f896
AM		 4327 /* Now *l must be either ',' or END_OF_INSN. */
4328 if (*l == ',')
4329 {
4330 if (*++l == END_OF_INSN)
4331 {
4332 /* Just skip it, if it's \n complain. */
4333 goto expecting_operand_after_comma;
4334 }
4335 expecting_operand = 1;
4336 }
4337 }
4338 return l;
4339}
7f3f1ea2 4340
050dfa73 4341static void
4d456e3d 4342swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4343{
4344 union i386_op temp_op;
40fb9820 4345 i386_operand_type temp_type;
050dfa73 4346 enum bfd_reloc_code_real temp_reloc;
4eed87de 4347
050dfa73
MM		 4348 temp_type = i.types[xchg2];
4349 i.types[xchg2] = i.types[xchg1];
4350 i.types[xchg1] = temp_type;
4351 temp_op = i.op[xchg2];
4352 i.op[xchg2] = i.op[xchg1];
4353 i.op[xchg1] = temp_op;
4354 temp_reloc = i.reloc[xchg2];
4355 i.reloc[xchg2] = i.reloc[xchg1];
4356 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4357
4358 if (i.mask)
4359 {
4360 if (i.mask->operand == xchg1)
4361 i.mask->operand = xchg2;
4362 else if (i.mask->operand == xchg2)
4363 i.mask->operand = xchg1;
4364 }
4365 if (i.broadcast)
4366 {
4367 if (i.broadcast->operand == xchg1)
4368 i.broadcast->operand = xchg2;
4369 else if (i.broadcast->operand == xchg2)
4370 i.broadcast->operand = xchg1;
4371 }
4372 if (i.rounding)
4373 {
4374 if (i.rounding->operand == xchg1)
4375 i.rounding->operand = xchg2;
4376 else if (i.rounding->operand == xchg2)
4377 i.rounding->operand = xchg1;
4378 }
050dfa73
MM		 4379}
4380
29b0f896 4381static void
e3bb37b5 4382swap_operands (void)
29b0f896 4383{
b7c61d9a 4384 switch (i.operands)
050dfa73 4385 {
c0f3af97 4386 case 5:
b7c61d9a 4387 case 4:
4d456e3d 4388 swap_2_operands (1, i.operands - 2);
1a0670f3 4389 /* Fall through. */
b7c61d9a
L		 4390 case 3:
4391 case 2:
4d456e3d 4392 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4393 break;
4394 default:
4395 abort ();
29b0f896 4396 }
29b0f896
AM		 4397
4398 if (i.mem_operands == 2)
4399 {
4400 const seg_entry *temp_seg;
4401 temp_seg = i.seg[0];
4402 i.seg[0] = i.seg[1];
4403 i.seg[1] = temp_seg;
4404 }
4405}
252b5132 4406
29b0f896
AM		 4407/* Try to ensure constant immediates are represented in the smallest
4408 opcode possible. */
4409static void
e3bb37b5 4410optimize_imm (void)
29b0f896
AM		 4411{
4412 char guess_suffix = 0;
4413 int op;
252b5132 4414
29b0f896
AM		 4415 if (i.suffix)
4416 guess_suffix = i.suffix;
4417 else if (i.reg_operands)
4418 {
4419 /* Figure out a suffix from the last register operand specified.
4420 We can't do this properly yet, ie. excluding InOutPortReg,
4421 but the following works for instructions with immediates.
4422 In any case, we can't set i.suffix yet. */
4423 for (op = i.operands; --op >= 0;)
dc821c5f 4424 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 4425 {
40fb9820
L		 4426 guess_suffix = BYTE_MNEM_SUFFIX;
4427 break;
4428 }
dc821c5f 4429 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 4430 {
40fb9820
L		 4431 guess_suffix = WORD_MNEM_SUFFIX;
4432 break;
4433 }
dc821c5f 4434 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 4435 {
4436 guess_suffix = LONG_MNEM_SUFFIX;
4437 break;
4438 }
dc821c5f 4439 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 4440 {
4441 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4442 break;
252b5132 4443 }
29b0f896
AM		 4444 }
4445 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4446 guess_suffix = WORD_MNEM_SUFFIX;
4447
4448 for (op = i.operands; --op >= 0;)
40fb9820 4449 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4450 {
4451 switch (i.op[op].imms->X_op)
252b5132 4452 {
29b0f896
AM		 4453 case O_constant:
4454 /* If a suffix is given, this operand may be shortened. */
4455 switch (guess_suffix)
252b5132 4456 {
29b0f896 4457 case LONG_MNEM_SUFFIX:
40fb9820
L		 4458 i.types[op].bitfield.imm32 = 1;
4459 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4460 break;
4461 case WORD_MNEM_SUFFIX:
40fb9820
L		 4462 i.types[op].bitfield.imm16 = 1;
4463 i.types[op].bitfield.imm32 = 1;
4464 i.types[op].bitfield.imm32s = 1;
4465 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4466 break;
4467 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4468 i.types[op].bitfield.imm8 = 1;
4469 i.types[op].bitfield.imm8s = 1;
4470 i.types[op].bitfield.imm16 = 1;
4471 i.types[op].bitfield.imm32 = 1;
4472 i.types[op].bitfield.imm32s = 1;
4473 i.types[op].bitfield.imm64 = 1;
29b0f896 4474 break;
252b5132 4475 }
252b5132 4476
29b0f896
AM		 4477 /* If this operand is at most 16 bits, convert it
4478 to a signed 16 bit number before trying to see
4479 whether it will fit in an even smaller size.
4480 This allows a 16-bit operand such as $0xffe0 to
4481 be recognised as within Imm8S range. */
40fb9820 4482 if ((i.types[op].bitfield.imm16)
29b0f896 4483 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4484 {
29b0f896
AM		 4485 i.op[op].imms->X_add_number =
4486 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4487 }
a28def75
L		 4488#ifdef BFD64
4489 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4490 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4491 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4492 == 0))
4493 {
4494 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4495 ^ ((offsetT) 1 << 31))
4496 - ((offsetT) 1 << 31));
4497 }
a28def75 4498#endif
40fb9820 4499 i.types[op]
c6fb90c8
L		 4500 = operand_type_or (i.types[op],
4501 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4502
29b0f896
AM		 4503 /* We must avoid matching of Imm32 templates when 64bit
4504 only immediate is available. */
4505 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4506 i.types[op].bitfield.imm32 = 0;
29b0f896 4507 break;
252b5132 4508
29b0f896
AM		 4509 case O_absent:
4510 case O_register:
4511 abort ();
4512
4513 /* Symbols and expressions. */
4514 default:
9cd96992
JB		 4515 /* Convert symbolic operand to proper sizes for matching, but don't
4516 prevent matching a set of insns that only supports sizes other
4517 than those matching the insn suffix. */
4518 {
40fb9820 4519 i386_operand_type mask, allowed;
d3ce72d0 4520 const insn_template *t;
9cd96992 4521
0dfbf9d7
L		 4522 operand_type_set (&mask, 0);
4523 operand_type_set (&allowed, 0);
40fb9820 4524
4eed87de
AM		 4525 for (t = current_templates->start;
4526 t < current_templates->end;
4527 ++t)
c6fb90c8
L		 4528 allowed = operand_type_or (allowed,
4529 t->operand_types[op]);
9cd96992
JB		 4530 switch (guess_suffix)
4531 {
4532 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4533 mask.bitfield.imm64 = 1;
4534 mask.bitfield.imm32s = 1;
9cd96992
JB		 4535 break;
4536 case LONG_MNEM_SUFFIX:
40fb9820 4537 mask.bitfield.imm32 = 1;
9cd96992
JB		 4538 break;
4539 case WORD_MNEM_SUFFIX:
40fb9820 4540 mask.bitfield.imm16 = 1;
9cd96992
JB		 4541 break;
4542 case BYTE_MNEM_SUFFIX:
40fb9820 4543 mask.bitfield.imm8 = 1;
9cd96992
JB		 4544 break;
4545 default:
9cd96992
JB		 4546 break;
4547 }
c6fb90c8 4548 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4549 if (!operand_type_all_zero (&allowed))
c6fb90c8 4550 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4551 }
29b0f896 4552 break;
252b5132 4553 }
29b0f896
AM		 4554 }
4555}
47926f60 4556
29b0f896
AM		 4557/* Try to use the smallest displacement type too. */
4558static void
e3bb37b5 4559optimize_disp (void)
29b0f896
AM		 4560{
4561 int op;
3e73aa7c 4562
29b0f896 4563 for (op = i.operands; --op >= 0;)
40fb9820 4564 if (operand_type_check (i.types[op], disp))
252b5132 4565 {
b300c311 4566 if (i.op[op].disps->X_op == O_constant)
252b5132 4567 {
91d6fa6a 4568 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4569
40fb9820 4570 if (i.types[op].bitfield.disp16
91d6fa6a 4571 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4572 {
4573 /* If this operand is at most 16 bits, convert
4574 to a signed 16 bit number and don't use 64bit
4575 displacement. */
91d6fa6a 4576 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4577 i.types[op].bitfield.disp64 = 0;
b300c311 4578 }
a28def75
L		 4579#ifdef BFD64
4580 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4581 if (i.types[op].bitfield.disp32
91d6fa6a 4582 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4583 {
4584 /* If this operand is at most 32 bits, convert
4585 to a signed 32 bit number and don't use 64bit
4586 displacement. */
91d6fa6a
NC		 4587 op_disp &= (((offsetT) 2 << 31) - 1);
4588 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4589 i.types[op].bitfield.disp64 = 0;
b300c311 4590 }
a28def75 4591#endif
91d6fa6a 4592 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4593 {
40fb9820
L		 4594 i.types[op].bitfield.disp8 = 0;
4595 i.types[op].bitfield.disp16 = 0;
4596 i.types[op].bitfield.disp32 = 0;
4597 i.types[op].bitfield.disp32s = 0;
4598 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4599 i.op[op].disps = 0;
4600 i.disp_operands--;
4601 }
4602 else if (flag_code == CODE_64BIT)
4603 {
91d6fa6a 4604 if (fits_in_signed_long (op_disp))
28a9d8f5 4605 {
40fb9820
L		 4606 i.types[op].bitfield.disp64 = 0;
4607 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4608 }
0e1147d9 4609 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4610 && fits_in_unsigned_long (op_disp))
40fb9820 4611 i.types[op].bitfield.disp32 = 1;
b300c311 4612 }
40fb9820
L		 4613 if ((i.types[op].bitfield.disp32
4614 || i.types[op].bitfield.disp32s
4615 || i.types[op].bitfield.disp16)
b5014f7a 4616 && fits_in_disp8 (op_disp))
40fb9820 4617 i.types[op].bitfield.disp8 = 1;
252b5132 4618 }
67a4f2b7
AO		 4619 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4620 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4621 {
4622 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4623 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4624 i.types[op].bitfield.disp8 = 0;
4625 i.types[op].bitfield.disp16 = 0;
4626 i.types[op].bitfield.disp32 = 0;
4627 i.types[op].bitfield.disp32s = 0;
4628 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4629 }
4630 else
b300c311 4631 /* We only support 64bit displacement on constants. */
40fb9820 4632 i.types[op].bitfield.disp64 = 0;
252b5132 4633 }
29b0f896
AM		 4634}
4635
6c30d220
L		 4636/* Check if operands are valid for the instruction. */
4637
4638static int
4639check_VecOperands (const insn_template *t)
4640{
43234a1e
L		 4641 unsigned int op;
4642
6c30d220
L		 4643 /* Without VSIB byte, we can't have a vector register for index. */
4644 if (!t->opcode_modifier.vecsib
4645 && i.index_reg
1b54b8d7
JB		 4646 && (i.index_reg->reg_type.bitfield.xmmword
4647 || i.index_reg->reg_type.bitfield.ymmword
4648 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 4649 {
4650 i.error = unsupported_vector_index_register;
4651 return 1;
4652 }
4653
ad8ecc81
MZ		 4654 /* Check if default mask is allowed. */
4655 if (t->opcode_modifier.nodefmask
4656 && (!i.mask || i.mask->mask->reg_num == 0))
4657 {
4658 i.error = no_default_mask;
4659 return 1;
4660 }
4661
7bab8ab5
JB		 4662 /* For VSIB byte, we need a vector register for index, and all vector
4663 registers must be distinct. */
4664 if (t->opcode_modifier.vecsib)
4665 {
4666 if (!i.index_reg
6c30d220 4667 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 4668 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 4669 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 4670 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 4671 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 4672 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 4673 {
4674 i.error = invalid_vsib_address;
4675 return 1;
4676 }
4677
43234a1e
L		 4678 gas_assert (i.reg_operands == 2 || i.mask);
4679 if (i.reg_operands == 2 && !i.mask)
4680 {
1b54b8d7
JB		 4681 gas_assert (i.types[0].bitfield.regsimd);
4682 gas_assert (i.types[0].bitfield.xmmword
4683 || i.types[0].bitfield.ymmword);
4684 gas_assert (i.types[2].bitfield.regsimd);
4685 gas_assert (i.types[2].bitfield.xmmword
4686 || i.types[2].bitfield.ymmword);
43234a1e
L		 4687 if (operand_check == check_none)
4688 return 0;
4689 if (register_number (i.op[0].regs)
4690 != register_number (i.index_reg)
4691 && register_number (i.op[2].regs)
4692 != register_number (i.index_reg)
4693 && register_number (i.op[0].regs)
4694 != register_number (i.op[2].regs))
4695 return 0;
4696 if (operand_check == check_error)
4697 {
4698 i.error = invalid_vector_register_set;
4699 return 1;
4700 }
4701 as_warn (_("mask, index, and destination registers should be distinct"));
4702 }
8444f82a
MZ		 4703 else if (i.reg_operands == 1 && i.mask)
4704 {
1b54b8d7
JB		 4705 if (i.types[1].bitfield.regsimd
4706 && (i.types[1].bitfield.xmmword
4707 || i.types[1].bitfield.ymmword
4708 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 4709 && (register_number (i.op[1].regs)
4710 == register_number (i.index_reg)))
4711 {
4712 if (operand_check == check_error)
4713 {
4714 i.error = invalid_vector_register_set;
4715 return 1;
4716 }
4717 if (operand_check != check_none)
4718 as_warn (_("index and destination registers should be distinct"));
4719 }
4720 }
43234a1e 4721 }
7bab8ab5 4722
43234a1e
L		 4723 /* Check if broadcast is supported by the instruction and is applied
4724 to the memory operand. */
4725 if (i.broadcast)
4726 {
4727 int broadcasted_opnd_size;
4728
4729 /* Check if specified broadcast is supported in this instruction,
4730 and it's applied to memory operand of DWORD or QWORD type,
4731 depending on VecESize. */
4732 if (i.broadcast->type != t->opcode_modifier.broadcast
4733 || !i.types[i.broadcast->operand].bitfield.mem
4734 || (t->opcode_modifier.vecesize == 0
4735 && !i.types[i.broadcast->operand].bitfield.dword
4736 && !i.types[i.broadcast->operand].bitfield.unspecified)
4737 || (t->opcode_modifier.vecesize == 1
4738 && !i.types[i.broadcast->operand].bitfield.qword
4739 && !i.types[i.broadcast->operand].bitfield.unspecified))
4740 goto bad_broadcast;
4741
4742 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4743 if (i.broadcast->type == BROADCAST_1TO16)
4744 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4745 else if (i.broadcast->type == BROADCAST_1TO8)
4746 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4747 else if (i.broadcast->type == BROADCAST_1TO4)
4748 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4749 else if (i.broadcast->type == BROADCAST_1TO2)
4750 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4751 else
4752 goto bad_broadcast;
4753
4754 if ((broadcasted_opnd_size == 256
4755 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4756 || (broadcasted_opnd_size == 512
4757 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4758 {
4759 bad_broadcast:
4760 i.error = unsupported_broadcast;
4761 return 1;
4762 }
4763 }
4764 /* If broadcast is supported in this instruction, we need to check if
4765 operand of one-element size isn't specified without broadcast. */
4766 else if (t->opcode_modifier.broadcast && i.mem_operands)
4767 {
4768 /* Find memory operand. */
4769 for (op = 0; op < i.operands; op++)
4770 if (operand_type_check (i.types[op], anymem))
4771 break;
4772 gas_assert (op < i.operands);
4773 /* Check size of the memory operand. */
4774 if ((t->opcode_modifier.vecesize == 0
4775 && i.types[op].bitfield.dword)
4776 || (t->opcode_modifier.vecesize == 1
4777 && i.types[op].bitfield.qword))
4778 {
4779 i.error = broadcast_needed;
4780 return 1;
4781 }
4782 }
4783
4784 /* Check if requested masking is supported. */
4785 if (i.mask
4786 && (!t->opcode_modifier.masking
4787 || (i.mask->zeroing
4788 && t->opcode_modifier.masking == MERGING_MASKING)))
4789 {
4790 i.error = unsupported_masking;
4791 return 1;
4792 }
4793
4794 /* Check if masking is applied to dest operand. */
4795 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4796 {
4797 i.error = mask_not_on_destination;
4798 return 1;
4799 }
4800
43234a1e
L		 4801 /* Check RC/SAE. */
4802 if (i.rounding)
4803 {
4804 if ((i.rounding->type != saeonly
4805 && !t->opcode_modifier.staticrounding)
4806 || (i.rounding->type == saeonly
4807 && (t->opcode_modifier.staticrounding
4808 || !t->opcode_modifier.sae)))
4809 {
4810 i.error = unsupported_rc_sae;
4811 return 1;
4812 }
4813 /* If the instruction has several immediate operands and one of
4814 them is rounding, the rounding operand should be the last
4815 immediate operand. */
4816 if (i.imm_operands > 1
4817 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4818 {
43234a1e 4819 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4820 return 1;
4821 }
6c30d220
L		 4822 }
4823
43234a1e 4824 /* Check vector Disp8 operand. */
b5014f7a
JB		 4825 if (t->opcode_modifier.disp8memshift
4826 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 4827 {
4828 if (i.broadcast)
4829 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4830 else
4831 i.memshift = t->opcode_modifier.disp8memshift;
4832
4833 for (op = 0; op < i.operands; op++)
4834 if (operand_type_check (i.types[op], disp)
4835 && i.op[op].disps->X_op == O_constant)
4836 {
b5014f7a 4837 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 4838 {
b5014f7a
JB		 4839 i.types[op].bitfield.disp8 = 1;
4840 return 0;
43234a1e 4841 }
b5014f7a 4842 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 4843 }
4844 }
b5014f7a
JB		 4845
4846 i.memshift = 0;
43234a1e 4847
6c30d220
L		 4848 return 0;
4849}
4850
43f3e2ee 4851/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4852 operand types. */
4853
4854static int
4855VEX_check_operands (const insn_template *t)
4856{
86fa6981 4857 if (i.vec_encoding == vex_encoding_evex)
43234a1e 4858 {
86fa6981
L		 4859 /* This instruction must be encoded with EVEX prefix. */
4860 if (!t->opcode_modifier.evex)
4861 {
4862 i.error = unsupported;
4863 return 1;
4864 }
4865 return 0;
43234a1e
L		 4866 }
4867
a683cc34 4868 if (!t->opcode_modifier.vex)
86fa6981
L		 4869 {
4870 /* This instruction template doesn't have VEX prefix. */
4871 if (i.vec_encoding != vex_encoding_default)
4872 {
4873 i.error = unsupported;
4874 return 1;
4875 }
4876 return 0;
4877 }
a683cc34
SP		 4878
4879 /* Only check VEX_Imm4, which must be the first operand. */
4880 if (t->operand_types[0].bitfield.vec_imm4)
4881 {
4882 if (i.op[0].imms->X_op != O_constant
4883 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4884 {
a65babc9 4885 i.error = bad_imm4;
891edac4
L		 4886 return 1;
4887 }
a683cc34
SP		 4888
4889 /* Turn off Imm8 so that update_imm won't complain. */
4890 i.types[0] = vec_imm4;
4891 }
4892
4893 return 0;
4894}
4895
d3ce72d0 4896static const insn_template *
83b16ac6 4897match_template (char mnem_suffix)
29b0f896
AM		 4898{
4899 /* Points to template once we've found it. */
d3ce72d0 4900 const insn_template *t;
40fb9820 4901 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4902 i386_operand_type overlap4;
29b0f896 4903 unsigned int found_reverse_match;
83b16ac6 4904 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 4905 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4906 int addr_prefix_disp;
a5c311ca 4907 unsigned int j;
3629bb00 4908 unsigned int found_cpu_match;
45664ddb 4909 unsigned int check_register;
5614d22c 4910 enum i386_error specific_error = 0;
29b0f896 4911
c0f3af97
L		 4912#if MAX_OPERANDS != 5
4913# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4914#endif
4915
29b0f896 4916 found_reverse_match = 0;
539e75ad 4917 addr_prefix_disp = -1;
40fb9820
L		 4918
4919 memset (&suffix_check, 0, sizeof (suffix_check));
4920 if (i.suffix == BYTE_MNEM_SUFFIX)
4921 suffix_check.no_bsuf = 1;
4922 else if (i.suffix == WORD_MNEM_SUFFIX)
4923 suffix_check.no_wsuf = 1;
4924 else if (i.suffix == SHORT_MNEM_SUFFIX)
4925 suffix_check.no_ssuf = 1;
4926 else if (i.suffix == LONG_MNEM_SUFFIX)
4927 suffix_check.no_lsuf = 1;
4928 else if (i.suffix == QWORD_MNEM_SUFFIX)
4929 suffix_check.no_qsuf = 1;
4930 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4931 suffix_check.no_ldsuf = 1;
29b0f896 4932
83b16ac6
JB		 4933 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4934 if (intel_syntax)
4935 {
4936 switch (mnem_suffix)
4937 {
4938 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4939 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4940 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4941 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4942 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4943 }
4944 }
4945
01559ecc
L		 4946 /* Must have right number of operands. */
4947 i.error = number_of_operands_mismatch;
4948
45aa61fe 4949 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4950 {
539e75ad
L		 4951 addr_prefix_disp = -1;
4952
29b0f896
AM		 4953 if (i.operands != t->operands)
4954 continue;
4955
50aecf8c 4956 /* Check processor support. */
a65babc9 4957 i.error = unsupported;
c0f3af97
L		 4958 found_cpu_match = (cpu_flags_match (t)
4959 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4960 if (!found_cpu_match)
4961 continue;
4962
e1d4d893 4963 /* Check old gcc support. */
a65babc9 4964 i.error = old_gcc_only;
e1d4d893
L		 4965 if (!old_gcc && t->opcode_modifier.oldgcc)
4966 continue;
4967
4968 /* Check AT&T mnemonic. */
a65babc9 4969 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4970 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4971 continue;
4972
e92bae62 4973 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 4974 i.error = unsupported_syntax;
5c07affc 4975 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 4976 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4977 || (intel64 && t->opcode_modifier.amd64)
4978 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 4979 continue;
4980
20592a94 4981 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4982 i.error = invalid_instruction_suffix;
567e4e96
L		 4983 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4984 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4985 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4986 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4987 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4988 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4989 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 4990 continue;
83b16ac6
JB		 4991 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4992 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4993 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4994 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4995 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4996 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4997 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4998 continue;
29b0f896 4999
5c07affc 5000 if (!operand_size_match (t))
7d5e4556 5001 continue;
539e75ad 5002
5c07affc
L		 5003 for (j = 0; j < MAX_OPERANDS; j++)
5004 operand_types[j] = t->operand_types[j];
5005
45aa61fe
AM		 5006 /* In general, don't allow 64-bit operands in 32-bit mode. */
5007 if (i.suffix == QWORD_MNEM_SUFFIX
5008 && flag_code != CODE_64BIT
5009 && (intel_syntax
40fb9820 5010 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 5011 && !intel_float_operand (t->name))
5012 : intel_float_operand (t->name) != 2)
40fb9820 5013 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5014 && !operand_types[0].bitfield.regsimd)
40fb9820 5015 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5016 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 5017 && (t->base_opcode != 0x0fc7
5018 || t->extension_opcode != 1 /* cmpxchg8b */))
5019 continue;
5020
192dc9c6
JB		 5021 /* In general, don't allow 32-bit operands on pre-386. */
5022 else if (i.suffix == LONG_MNEM_SUFFIX
5023 && !cpu_arch_flags.bitfield.cpui386
5024 && (intel_syntax
5025 ? (!t->opcode_modifier.ignoresize
5026 && !intel_float_operand (t->name))
5027 : intel_float_operand (t->name) != 2)
5028 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5029 && !operand_types[0].bitfield.regsimd)
192dc9c6 5030 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5031 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 5032 continue;
5033
29b0f896 5034 /* Do not verify operands when there are none. */
50aecf8c 5035 else
29b0f896 5036 {
c6fb90c8 5037 if (!t->operands)
2dbab7d5
L		 5038 /* We've found a match; break out of loop. */
5039 break;
29b0f896 5040 }
252b5132 5041
539e75ad
L		 5042 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5043 into Disp32/Disp16/Disp32 operand. */
5044 if (i.prefix[ADDR_PREFIX] != 0)
5045 {
40fb9820 5046 /* There should be only one Disp operand. */
539e75ad
L		 5047 switch (flag_code)
5048 {
5049 case CODE_16BIT:
40fb9820
L		 5050 for (j = 0; j < MAX_OPERANDS; j++)
5051 {
5052 if (operand_types[j].bitfield.disp16)
5053 {
5054 addr_prefix_disp = j;
5055 operand_types[j].bitfield.disp32 = 1;
5056 operand_types[j].bitfield.disp16 = 0;
5057 break;
5058 }
5059 }
539e75ad
L		 5060 break;
5061 case CODE_32BIT:
40fb9820
L		 5062 for (j = 0; j < MAX_OPERANDS; j++)
5063 {
5064 if (operand_types[j].bitfield.disp32)
5065 {
5066 addr_prefix_disp = j;
5067 operand_types[j].bitfield.disp32 = 0;
5068 operand_types[j].bitfield.disp16 = 1;
5069 break;
5070 }
5071 }
539e75ad
L		 5072 break;
5073 case CODE_64BIT:
40fb9820
L		 5074 for (j = 0; j < MAX_OPERANDS; j++)
5075 {
5076 if (operand_types[j].bitfield.disp64)
5077 {
5078 addr_prefix_disp = j;
5079 operand_types[j].bitfield.disp64 = 0;
5080 operand_types[j].bitfield.disp32 = 1;
5081 break;
5082 }
5083 }
539e75ad
L		 5084 break;
5085 }
539e75ad
L		 5086 }
5087
02a86693
L		 5088 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5089 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5090 continue;
5091
56ffb741
L		 5092 /* We check register size if needed. */
5093 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 5094 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5095 switch (t->operands)
5096 {
5097 case 1:
40fb9820 5098 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5099 continue;
5100 break;
5101 case 2:
33eaf5de 5102 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5103 only in 32bit mode and we can use opcode 0x90. In 64bit
5104 mode, we can't use 0x90 for xchg %eax, %eax since it should
5105 zero-extend %eax to %rax. */
5106 if (flag_code == CODE_64BIT
5107 && t->base_opcode == 0x90
0dfbf9d7
L		 5108 && operand_type_equal (&i.types [0], &acc32)
5109 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5110 continue;
86fa6981
L		 5111 /* If we want store form, we reverse direction of operands. */
5112 if (i.dir_encoding == dir_encoding_store
5113 && t->opcode_modifier.d)
5114 goto check_reverse;
1a0670f3 5115 /* Fall through. */
b6169b20 5116
29b0f896 5117 case 3:
86fa6981
L		 5118 /* If we want store form, we skip the current load. */
5119 if (i.dir_encoding == dir_encoding_store
5120 && i.mem_operands == 0
5121 && t->opcode_modifier.load)
fa99fab2 5122 continue;
1a0670f3 5123 /* Fall through. */
f48ff2ae 5124 case 4:
c0f3af97 5125 case 5:
c6fb90c8 5126 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5127 if (!operand_type_match (overlap0, i.types[0])
5128 || !operand_type_match (overlap1, i.types[1])
45664ddb 5129 || (check_register
dc821c5f 5130 && !operand_type_register_match (i.types[0],
40fb9820 5131 operand_types[0],
dc821c5f 5132 i.types[1],
40fb9820 5133 operand_types[1])))
29b0f896
AM		 5134 {
5135 /* Check if other direction is valid ... */
40fb9820 5136 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 5137 continue;
5138
b6169b20 5139check_reverse:
29b0f896 5140 /* Try reversing direction of operands. */
c6fb90c8
L		 5141 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5142 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5143 if (!operand_type_match (overlap0, i.types[0])
5144 || !operand_type_match (overlap1, i.types[1])
45664ddb 5145 || (check_register
dc821c5f 5146 && !operand_type_register_match (i.types[0],
45664ddb 5147 operand_types[1],
45664ddb
L		 5148 i.types[1],
5149 operand_types[0])))
29b0f896
AM		 5150 {
5151 /* Does not match either direction. */
5152 continue;
5153 }
5154 /* found_reverse_match holds which of D or FloatDR
5155 we've found. */
40fb9820 5156 if (t->opcode_modifier.d)
8a2ed489 5157 found_reverse_match = Opcode_D;
40fb9820 5158 else if (t->opcode_modifier.floatd)
8a2ed489
L		 5159 found_reverse_match = Opcode_FloatD;
5160 else
5161 found_reverse_match = 0;
40fb9820 5162 if (t->opcode_modifier.floatr)
8a2ed489 5163 found_reverse_match |= Opcode_FloatR;
29b0f896 5164 }
f48ff2ae 5165 else
29b0f896 5166 {
f48ff2ae 5167 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5168 switch (t->operands)
5169 {
c0f3af97
L		 5170 case 5:
5171 overlap4 = operand_type_and (i.types[4],
5172 operand_types[4]);
1a0670f3 5173 /* Fall through. */
d1cbb4db 5174 case 4:
c6fb90c8
L		 5175 overlap3 = operand_type_and (i.types[3],
5176 operand_types[3]);
1a0670f3 5177 /* Fall through. */
d1cbb4db 5178 case 3:
c6fb90c8
L		 5179 overlap2 = operand_type_and (i.types[2],
5180 operand_types[2]);
d1cbb4db
L		 5181 break;
5182 }
29b0f896 5183
f48ff2ae
L		 5184 switch (t->operands)
5185 {
c0f3af97
L		 5186 case 5:
5187 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5188 || !operand_type_register_match (i.types[3],
c0f3af97 5189 operand_types[3],
c0f3af97
L		 5190 i.types[4],
5191 operand_types[4]))
5192 continue;
1a0670f3 5193 /* Fall through. */
f48ff2ae 5194 case 4:
40fb9820 5195 if (!operand_type_match (overlap3, i.types[3])
45664ddb 5196 || (check_register
dc821c5f 5197 && !operand_type_register_match (i.types[2],
45664ddb 5198 operand_types[2],
45664ddb
L		 5199 i.types[3],
5200 operand_types[3])))
f48ff2ae 5201 continue;
1a0670f3 5202 /* Fall through. */
f48ff2ae
L		 5203 case 3:
5204 /* Here we make use of the fact that there are no
5205 reverse match 3 operand instructions, and all 3
5206 operand instructions only need to be checked for
5207 register consistency between operands 2 and 3. */
40fb9820 5208 if (!operand_type_match (overlap2, i.types[2])
45664ddb 5209 || (check_register
dc821c5f 5210 && !operand_type_register_match (i.types[1],
45664ddb 5211 operand_types[1],
45664ddb
L		 5212 i.types[2],
5213 operand_types[2])))
f48ff2ae
L		 5214 continue;
5215 break;
5216 }
29b0f896 5217 }
f48ff2ae 5218 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5219 slip through to break. */
5220 }
3629bb00 5221 if (!found_cpu_match)
29b0f896
AM		 5222 {
5223 found_reverse_match = 0;
5224 continue;
5225 }
c0f3af97 5226
5614d22c
JB		 5227 /* Check if vector and VEX operands are valid. */
5228 if (check_VecOperands (t) || VEX_check_operands (t))
5229 {
5230 specific_error = i.error;
5231 continue;
5232 }
a683cc34 5233
29b0f896
AM		 5234 /* We've found a match; break out of loop. */
5235 break;
5236 }
5237
5238 if (t == current_templates->end)
5239 {
5240 /* We found no match. */
a65babc9 5241 const char *err_msg;
5614d22c 5242 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5243 {
5244 default:
5245 abort ();
86e026a4 5246 case operand_size_mismatch:
a65babc9
L		 5247 err_msg = _("operand size mismatch");
5248 break;
5249 case operand_type_mismatch:
5250 err_msg = _("operand type mismatch");
5251 break;
5252 case register_type_mismatch:
5253 err_msg = _("register type mismatch");
5254 break;
5255 case number_of_operands_mismatch:
5256 err_msg = _("number of operands mismatch");
5257 break;
5258 case invalid_instruction_suffix:
5259 err_msg = _("invalid instruction suffix");
5260 break;
5261 case bad_imm4:
4a2608e3 5262 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5263 break;
5264 case old_gcc_only:
5265 err_msg = _("only supported with old gcc");
5266 break;
5267 case unsupported_with_intel_mnemonic:
5268 err_msg = _("unsupported with Intel mnemonic");
5269 break;
5270 case unsupported_syntax:
5271 err_msg = _("unsupported syntax");
5272 break;
5273 case unsupported:
35262a23 5274 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5275 current_templates->start->name);
5276 return NULL;
6c30d220
L		 5277 case invalid_vsib_address:
5278 err_msg = _("invalid VSIB address");
5279 break;
7bab8ab5
JB		 5280 case invalid_vector_register_set:
5281 err_msg = _("mask, index, and destination registers must be distinct");
5282 break;
6c30d220
L		 5283 case unsupported_vector_index_register:
5284 err_msg = _("unsupported vector index register");
5285 break;
43234a1e
L		 5286 case unsupported_broadcast:
5287 err_msg = _("unsupported broadcast");
5288 break;
5289 case broadcast_not_on_src_operand:
5290 err_msg = _("broadcast not on source memory operand");
5291 break;
5292 case broadcast_needed:
5293 err_msg = _("broadcast is needed for operand of such type");
5294 break;
5295 case unsupported_masking:
5296 err_msg = _("unsupported masking");
5297 break;
5298 case mask_not_on_destination:
5299 err_msg = _("mask not on destination operand");
5300 break;
5301 case no_default_mask:
5302 err_msg = _("default mask isn't allowed");
5303 break;
5304 case unsupported_rc_sae:
5305 err_msg = _("unsupported static rounding/sae");
5306 break;
5307 case rc_sae_operand_not_last_imm:
5308 if (intel_syntax)
5309 err_msg = _("RC/SAE operand must precede immediate operands");
5310 else
5311 err_msg = _("RC/SAE operand must follow immediate operands");
5312 break;
5313 case invalid_register_operand:
5314 err_msg = _("invalid register operand");
5315 break;
a65babc9
L		 5316 }
5317 as_bad (_("%s for `%s'"), err_msg,
891edac4 5318 current_templates->start->name);
fa99fab2 5319 return NULL;
29b0f896 5320 }
252b5132 5321
29b0f896
AM		 5322 if (!quiet_warnings)
5323 {
5324 if (!intel_syntax
40fb9820
L		 5325 && (i.types[0].bitfield.jumpabsolute
5326 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5327 {
5328 as_warn (_("indirect %s without `*'"), t->name);
5329 }
5330
40fb9820
L		 5331 if (t->opcode_modifier.isprefix
5332 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5333 {
5334 /* Warn them that a data or address size prefix doesn't
5335 affect assembly of the next line of code. */
5336 as_warn (_("stand-alone `%s' prefix"), t->name);
5337 }
5338 }
5339
5340 /* Copy the template we found. */
5341 i.tm = *t;
539e75ad
L		 5342
5343 if (addr_prefix_disp != -1)
5344 i.tm.operand_types[addr_prefix_disp]
5345 = operand_types[addr_prefix_disp];
5346
29b0f896
AM		 5347 if (found_reverse_match)
5348 {
5349 /* If we found a reverse match we must alter the opcode
5350 direction bit. found_reverse_match holds bits to change
5351 (different for int & float insns). */
5352
5353 i.tm.base_opcode ^= found_reverse_match;
5354
539e75ad
L		 5355 i.tm.operand_types[0] = operand_types[1];
5356 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5357 }
5358
fa99fab2 5359 return t;
29b0f896
AM		 5360}
5361
5362static int
e3bb37b5 5363check_string (void)
29b0f896 5364{
40fb9820
L		 5365 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5366 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5367 {
5368 if (i.seg[0] != NULL && i.seg[0] != &es)
5369 {
a87af027 5370 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5371 i.tm.name,
a87af027
JB		 5372 mem_op + 1,
5373 register_prefix);
29b0f896
AM		 5374 return 0;
5375 }
5376 /* There's only ever one segment override allowed per instruction.
5377 This instruction possibly has a legal segment override on the
5378 second operand, so copy the segment to where non-string
5379 instructions store it, allowing common code. */
5380 i.seg[0] = i.seg[1];
5381 }
40fb9820 5382 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5383 {
5384 if (i.seg[1] != NULL && i.seg[1] != &es)
5385 {
a87af027 5386 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5387 i.tm.name,
a87af027
JB		 5388 mem_op + 2,
5389 register_prefix);
29b0f896
AM		 5390 return 0;
5391 }
5392 }
5393 return 1;
5394}
5395
5396static int
543613e9 5397process_suffix (void)
29b0f896
AM		 5398{
5399 /* If matched instruction specifies an explicit instruction mnemonic
5400 suffix, use it. */
40fb9820
L		 5401 if (i.tm.opcode_modifier.size16)
5402 i.suffix = WORD_MNEM_SUFFIX;
5403 else if (i.tm.opcode_modifier.size32)
5404 i.suffix = LONG_MNEM_SUFFIX;
5405 else if (i.tm.opcode_modifier.size64)
5406 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5407 else if (i.reg_operands)
5408 {
5409 /* If there's no instruction mnemonic suffix we try to invent one
5410 based on register operands. */
5411 if (!i.suffix)
5412 {
5413 /* We take i.suffix from the last register operand specified,
5414 Destination register type is more significant than source
381d071f
L		 5415 register type. crc32 in SSE4.2 prefers source register
5416 type. */
5417 if (i.tm.base_opcode == 0xf20f38f1)
5418 {
dc821c5f 5419 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
40fb9820 5420 i.suffix = WORD_MNEM_SUFFIX;
dc821c5f 5421 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
40fb9820 5422 i.suffix = LONG_MNEM_SUFFIX;
dc821c5f 5423 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
40fb9820 5424 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5425 }
9344ff29 5426 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5427 {
dc821c5f 5428 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
20592a94
L		 5429 i.suffix = BYTE_MNEM_SUFFIX;
5430 }
381d071f
L		 5431
5432 if (!i.suffix)
5433 {
5434 int op;
5435
20592a94
L		 5436 if (i.tm.base_opcode == 0xf20f38f1
5437 || i.tm.base_opcode == 0xf20f38f0)
5438 {
5439 /* We have to know the operand size for crc32. */
5440 as_bad (_("ambiguous memory operand size for `%s`"),
5441 i.tm.name);
5442 return 0;
5443 }
5444
381d071f 5445 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 5446 if (!i.tm.operand_types[op].bitfield.inoutportreg
5447 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 5448 {
dc821c5f 5449 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
40fb9820
L		 5450 {
5451 i.suffix = BYTE_MNEM_SUFFIX;
5452 break;
5453 }
dc821c5f 5454 if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
40fb9820
L		 5455 {
5456 i.suffix = WORD_MNEM_SUFFIX;
5457 break;
5458 }
dc821c5f 5459 if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 5460 {
5461 i.suffix = LONG_MNEM_SUFFIX;
5462 break;
5463 }
dc821c5f 5464 if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 5465 {
5466 i.suffix = QWORD_MNEM_SUFFIX;
5467 break;
5468 }
381d071f
L		 5469 }
5470 }
29b0f896
AM		 5471 }
5472 else if (i.suffix == BYTE_MNEM_SUFFIX)
5473 {
2eb952a4
L		 5474 if (intel_syntax
5475 && i.tm.opcode_modifier.ignoresize
5476 && i.tm.opcode_modifier.no_bsuf)
5477 i.suffix = 0;
5478 else if (!check_byte_reg ())
29b0f896
AM		 5479 return 0;
5480 }
5481 else if (i.suffix == LONG_MNEM_SUFFIX)
5482 {
2eb952a4
L		 5483 if (intel_syntax
5484 && i.tm.opcode_modifier.ignoresize
5485 && i.tm.opcode_modifier.no_lsuf)
5486 i.suffix = 0;
5487 else if (!check_long_reg ())
29b0f896
AM		 5488 return 0;
5489 }
5490 else if (i.suffix == QWORD_MNEM_SUFFIX)
5491 {
955e1e6a
L		 5492 if (intel_syntax
5493 && i.tm.opcode_modifier.ignoresize
5494 && i.tm.opcode_modifier.no_qsuf)
5495 i.suffix = 0;
5496 else if (!check_qword_reg ())
29b0f896
AM		 5497 return 0;
5498 }
5499 else if (i.suffix == WORD_MNEM_SUFFIX)
5500 {
2eb952a4
L		 5501 if (intel_syntax
5502 && i.tm.opcode_modifier.ignoresize
5503 && i.tm.opcode_modifier.no_wsuf)
5504 i.suffix = 0;
5505 else if (!check_word_reg ())
29b0f896
AM		 5506 return 0;
5507 }
c0f3af97 5508 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5509 || i.suffix == YMMWORD_MNEM_SUFFIX
5510 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5511 {
43234a1e 5512 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5513 should check if it is a valid suffix. */
5514 }
40fb9820 5515 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5516 /* Do nothing if the instruction is going to ignore the prefix. */
5517 ;
5518 else
5519 abort ();
5520 }
40fb9820 5521 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5522 && !i.suffix
5523 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5524 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5525 {
5526 i.suffix = stackop_size;
5527 }
9306ca4a
JB		 5528 else if (intel_syntax
5529 && !i.suffix
40fb9820
L		 5530 && (i.tm.operand_types[0].bitfield.jumpabsolute
5531 || i.tm.opcode_modifier.jumpbyte
5532 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5533 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5534 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5535 {
5536 switch (flag_code)
5537 {
5538 case CODE_64BIT:
40fb9820 5539 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5540 {
5541 i.suffix = QWORD_MNEM_SUFFIX;
5542 break;
5543 }
1a0670f3 5544 /* Fall through. */
9306ca4a 5545 case CODE_32BIT:
40fb9820 5546 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5547 i.suffix = LONG_MNEM_SUFFIX;
5548 break;
5549 case CODE_16BIT:
40fb9820 5550 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5551 i.suffix = WORD_MNEM_SUFFIX;
5552 break;
5553 }
5554 }
252b5132 5555
9306ca4a 5556 if (!i.suffix)
29b0f896 5557 {
9306ca4a
JB		 5558 if (!intel_syntax)
5559 {
40fb9820 5560 if (i.tm.opcode_modifier.w)
9306ca4a 5561 {
4eed87de
AM		 5562 as_bad (_("no instruction mnemonic suffix given and "
5563 "no register operands; can't size instruction"));
9306ca4a
JB		 5564 return 0;
5565 }
5566 }
5567 else
5568 {
40fb9820 5569 unsigned int suffixes;
7ab9ffdd 5570
40fb9820
L		 5571 suffixes = !i.tm.opcode_modifier.no_bsuf;
5572 if (!i.tm.opcode_modifier.no_wsuf)
5573 suffixes |= 1 << 1;
5574 if (!i.tm.opcode_modifier.no_lsuf)
5575 suffixes |= 1 << 2;
fc4adea1 5576 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5577 suffixes |= 1 << 3;
5578 if (!i.tm.opcode_modifier.no_ssuf)
5579 suffixes |= 1 << 4;
c2b9da16 5580 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 5581 suffixes |= 1 << 5;
5582
5583 /* There are more than suffix matches. */
5584 if (i.tm.opcode_modifier.w
9306ca4a 5585 || ((suffixes & (suffixes - 1))
40fb9820
L		 5586 && !i.tm.opcode_modifier.defaultsize
5587 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5588 {
5589 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5590 return 0;
5591 }
5592 }
29b0f896 5593 }
252b5132 5594
9306ca4a
JB		 5595 /* Change the opcode based on the operand size given by i.suffix;
5596 We don't need to change things for byte insns. */
5597
582d5edd
L		 5598 if (i.suffix
5599 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5600 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5601 && i.suffix != YMMWORD_MNEM_SUFFIX
5602 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5603 {
5604 /* It's not a byte, select word/dword operation. */
40fb9820 5605 if (i.tm.opcode_modifier.w)
29b0f896 5606 {
40fb9820 5607 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5608 i.tm.base_opcode |= 8;
5609 else
5610 i.tm.base_opcode |= 1;
5611 }
0f3f3d8b 5612
29b0f896
AM		 5613 /* Now select between word & dword operations via the operand
5614 size prefix, except for instructions that will ignore this
5615 prefix anyway. */
ca61edf2 5616 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5617 {
ca61edf2
L		 5618 /* The address size override prefix changes the size of the
5619 first operand. */
40fb9820 5620 if ((flag_code == CODE_32BIT
dc821c5f 5621 && i.op->regs[0].reg_type.bitfield.word)
40fb9820 5622 || (flag_code != CODE_32BIT
dc821c5f 5623 && i.op->regs[0].reg_type.bitfield.dword))
cb712a9e
L		 5624 if (!add_prefix (ADDR_PREFIX_OPCODE))
5625 return 0;
5626 }
5627 else if (i.suffix != QWORD_MNEM_SUFFIX
5628 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5629 && !i.tm.opcode_modifier.ignoresize
5630 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5631 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5632 || (flag_code == CODE_64BIT
40fb9820 5633 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5634 {
5635 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5636
40fb9820 5637 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5638 prefix = ADDR_PREFIX_OPCODE;
252b5132 5639
29b0f896
AM		 5640 if (!add_prefix (prefix))
5641 return 0;
24eab124 5642 }
252b5132 5643
29b0f896
AM		 5644 /* Set mode64 for an operand. */
5645 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5646 && flag_code == CODE_64BIT
40fb9820 5647 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5648 {
5649 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5650 need rex64. cmpxchg8b is also a special case. */
5651 if (! (i.operands == 2
5652 && i.tm.base_opcode == 0x90
5653 && i.tm.extension_opcode == None
0dfbf9d7
L		 5654 && operand_type_equal (&i.types [0], &acc64)
5655 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5656 && ! (i.operands == 1
5657 && i.tm.base_opcode == 0xfc7
5658 && i.tm.extension_opcode == 1
40fb9820
L		 5659 && !operand_type_check (i.types [0], reg)
5660 && operand_type_check (i.types [0], anymem)))
f6bee062 5661 i.rex |= REX_W;
46e883c5 5662 }
3e73aa7c 5663
29b0f896
AM		 5664 /* Size floating point instruction. */
5665 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5666 if (i.tm.opcode_modifier.floatmf)
543613e9 5667 i.tm.base_opcode ^= 4;
29b0f896 5668 }
7ecd2f8b 5669
29b0f896
AM		 5670 return 1;
5671}
3e73aa7c 5672
29b0f896 5673static int
543613e9 5674check_byte_reg (void)
29b0f896
AM		 5675{
5676 int op;
543613e9 5677
29b0f896
AM		 5678 for (op = i.operands; --op >= 0;)
5679 {
dc821c5f
JB		 5680 /* Skip non-register operands. */
5681 if (!i.types[op].bitfield.reg)
5682 continue;
5683
29b0f896
AM		 5684 /* If this is an eight bit register, it's OK. If it's the 16 or
5685 32 bit version of an eight bit register, we will just use the
5686 low portion, and that's OK too. */
dc821c5f 5687 if (i.types[op].bitfield.byte)
29b0f896
AM		 5688 continue;
5689
5a819eb9
JB		 5690 /* I/O port address operands are OK too. */
5691 if (i.tm.operand_types[op].bitfield.inoutportreg)
5692 continue;
5693
9344ff29
L		 5694 /* crc32 doesn't generate this warning. */
5695 if (i.tm.base_opcode == 0xf20f38f0)
5696 continue;
5697
dc821c5f
JB		 5698 if ((i.types[op].bitfield.word
5699 || i.types[op].bitfield.dword
5700 || i.types[op].bitfield.qword)
5a819eb9
JB		 5701 && i.op[op].regs->reg_num < 4
5702 /* Prohibit these changes in 64bit mode, since the lowering
5703 would be more complicated. */
5704 && flag_code != CODE_64BIT)
29b0f896 5705 {
29b0f896 5706#if REGISTER_WARNINGS
5a819eb9 5707 if (!quiet_warnings)
a540244d
L		 5708 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5709 register_prefix,
dc821c5f 5710 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 5711 ? REGNAM_AL - REGNAM_AX
5712 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5713 register_prefix,
29b0f896
AM		 5714 i.op[op].regs->reg_name,
5715 i.suffix);
5716#endif
5717 continue;
5718 }
5719 /* Any other register is bad. */
dc821c5f 5720 if (i.types[op].bitfield.reg
40fb9820 5721 || i.types[op].bitfield.regmmx
1b54b8d7 5722 || i.types[op].bitfield.regsimd
40fb9820
L		 5723 || i.types[op].bitfield.sreg2
5724 || i.types[op].bitfield.sreg3
5725 || i.types[op].bitfield.control
5726 || i.types[op].bitfield.debug
ca0d63fe 5727 || i.types[op].bitfield.test)
29b0f896 5728 {
a540244d
L		 5729 as_bad (_("`%s%s' not allowed with `%s%c'"),
5730 register_prefix,
29b0f896
AM		 5731 i.op[op].regs->reg_name,
5732 i.tm.name,
5733 i.suffix);
5734 return 0;
5735 }
5736 }
5737 return 1;
5738}
5739
5740static int
e3bb37b5 5741check_long_reg (void)
29b0f896
AM		 5742{
5743 int op;
5744
5745 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 5746 /* Skip non-register operands. */
5747 if (!i.types[op].bitfield.reg)
5748 continue;
29b0f896
AM		 5749 /* Reject eight bit registers, except where the template requires
5750 them. (eg. movzb) */
dc821c5f
JB		 5751 else if (i.types[op].bitfield.byte
5752 && (i.tm.operand_types[op].bitfield.reg
5753 || i.tm.operand_types[op].bitfield.acc)
5754 && (i.tm.operand_types[op].bitfield.word
5755 || i.tm.operand_types[op].bitfield.dword))
29b0f896 5756 {
a540244d
L		 5757 as_bad (_("`%s%s' not allowed with `%s%c'"),
5758 register_prefix,
29b0f896
AM		 5759 i.op[op].regs->reg_name,
5760 i.tm.name,
5761 i.suffix);
5762 return 0;
5763 }
e4630f71 5764 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5765 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 5766 && i.types[op].bitfield.word
5767 && (i.tm.operand_types[op].bitfield.reg
5768 || i.tm.operand_types[op].bitfield.acc)
5769 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 5770 {
5771 /* Prohibit these changes in the 64bit mode, since the
5772 lowering is more complicated. */
5773 if (flag_code == CODE_64BIT)
252b5132 5774 {
2b5d6a91 5775 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5776 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5777 i.suffix);
5778 return 0;
252b5132 5779 }
29b0f896 5780#if REGISTER_WARNINGS
cecf1424
JB		 5781 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5782 register_prefix,
5783 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5784 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5785#endif
252b5132 5786 }
e4630f71 5787 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 5788 else if (i.types[op].bitfield.qword
5789 && (i.tm.operand_types[op].bitfield.reg
5790 || i.tm.operand_types[op].bitfield.acc)
5791 && i.tm.operand_types[op].bitfield.dword)
252b5132 5792 {
34828aad 5793 if (intel_syntax
ca61edf2 5794 && i.tm.opcode_modifier.toqword
1b54b8d7 5795 && !i.types[0].bitfield.regsimd)
34828aad 5796 {
ca61edf2 5797 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5798 i.suffix = QWORD_MNEM_SUFFIX;
5799 }
5800 else
5801 {
2b5d6a91 5802 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5803 register_prefix, i.op[op].regs->reg_name,
5804 i.suffix);
5805 return 0;
5806 }
29b0f896
AM		 5807 }
5808 return 1;
5809}
252b5132 5810
29b0f896 5811static int
e3bb37b5 5812check_qword_reg (void)
29b0f896
AM		 5813{
5814 int op;
252b5132 5815
29b0f896 5816 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 5817 /* Skip non-register operands. */
5818 if (!i.types[op].bitfield.reg)
5819 continue;
29b0f896
AM		 5820 /* Reject eight bit registers, except where the template requires
5821 them. (eg. movzb) */
dc821c5f
JB		 5822 else if (i.types[op].bitfield.byte
5823 && (i.tm.operand_types[op].bitfield.reg
5824 || i.tm.operand_types[op].bitfield.acc)
5825 && (i.tm.operand_types[op].bitfield.word
5826 || i.tm.operand_types[op].bitfield.dword))
29b0f896 5827 {
a540244d
L		 5828 as_bad (_("`%s%s' not allowed with `%s%c'"),
5829 register_prefix,
29b0f896
AM		 5830 i.op[op].regs->reg_name,
5831 i.tm.name,
5832 i.suffix);
5833 return 0;
5834 }
e4630f71 5835 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 5836 else if ((i.types[op].bitfield.word
5837 || i.types[op].bitfield.dword)
5838 && (i.tm.operand_types[op].bitfield.reg
5839 || i.tm.operand_types[op].bitfield.acc)
5840 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 5841 {
5842 /* Prohibit these changes in the 64bit mode, since the
5843 lowering is more complicated. */
34828aad 5844 if (intel_syntax
ca61edf2 5845 && i.tm.opcode_modifier.todword
1b54b8d7 5846 && !i.types[0].bitfield.regsimd)
34828aad 5847 {
ca61edf2 5848 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5849 i.suffix = LONG_MNEM_SUFFIX;
5850 }
5851 else
5852 {
2b5d6a91 5853 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5854 register_prefix, i.op[op].regs->reg_name,
5855 i.suffix);
5856 return 0;
5857 }
252b5132 5858 }
29b0f896
AM		 5859 return 1;
5860}
252b5132 5861
29b0f896 5862static int
e3bb37b5 5863check_word_reg (void)
29b0f896
AM		 5864{
5865 int op;
5866 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 5867 /* Skip non-register operands. */
5868 if (!i.types[op].bitfield.reg)
5869 continue;
29b0f896
AM		 5870 /* Reject eight bit registers, except where the template requires
5871 them. (eg. movzb) */
dc821c5f
JB		 5872 else if (i.types[op].bitfield.byte
5873 && (i.tm.operand_types[op].bitfield.reg
5874 || i.tm.operand_types[op].bitfield.acc)
5875 && (i.tm.operand_types[op].bitfield.word
5876 || i.tm.operand_types[op].bitfield.dword))
29b0f896 5877 {
a540244d
L		 5878 as_bad (_("`%s%s' not allowed with `%s%c'"),
5879 register_prefix,
29b0f896
AM		 5880 i.op[op].regs->reg_name,
5881 i.tm.name,
5882 i.suffix);
5883 return 0;
5884 }
e4630f71 5885 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5886 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 5887 && (i.types[op].bitfield.dword
5888 || i.types[op].bitfield.qword)
5889 && (i.tm.operand_types[op].bitfield.reg
5890 || i.tm.operand_types[op].bitfield.acc)
5891 && i.tm.operand_types[op].bitfield.word)
252b5132 5892 {
29b0f896
AM		 5893 /* Prohibit these changes in the 64bit mode, since the
5894 lowering is more complicated. */
5895 if (flag_code == CODE_64BIT)
252b5132 5896 {
2b5d6a91 5897 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5898 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5899 i.suffix);
5900 return 0;
252b5132 5901 }
29b0f896 5902#if REGISTER_WARNINGS
cecf1424
JB		 5903 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5904 register_prefix,
5905 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5906 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5907#endif
5908 }
5909 return 1;
5910}
252b5132 5911
29b0f896 5912static int
40fb9820 5913update_imm (unsigned int j)
29b0f896 5914{
bc0844ae 5915 i386_operand_type overlap = i.types[j];
40fb9820
L		 5916 if ((overlap.bitfield.imm8
5917 || overlap.bitfield.imm8s
5918 || overlap.bitfield.imm16
5919 || overlap.bitfield.imm32
5920 || overlap.bitfield.imm32s
5921 || overlap.bitfield.imm64)
0dfbf9d7
L		 5922 && !operand_type_equal (&overlap, &imm8)
5923 && !operand_type_equal (&overlap, &imm8s)
5924 && !operand_type_equal (&overlap, &imm16)
5925 && !operand_type_equal (&overlap, &imm32)
5926 && !operand_type_equal (&overlap, &imm32s)
5927 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5928 {
5929 if (i.suffix)
5930 {
40fb9820
L		 5931 i386_operand_type temp;
5932
0dfbf9d7 5933 operand_type_set (&temp, 0);
7ab9ffdd 5934 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5935 {
5936 temp.bitfield.imm8 = overlap.bitfield.imm8;
5937 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5938 }
5939 else if (i.suffix == WORD_MNEM_SUFFIX)
5940 temp.bitfield.imm16 = overlap.bitfield.imm16;
5941 else if (i.suffix == QWORD_MNEM_SUFFIX)
5942 {
5943 temp.bitfield.imm64 = overlap.bitfield.imm64;
5944 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5945 }
5946 else
5947 temp.bitfield.imm32 = overlap.bitfield.imm32;
5948 overlap = temp;
29b0f896 5949 }
0dfbf9d7
L		 5950 else if (operand_type_equal (&overlap, &imm16_32_32s)
5951 || operand_type_equal (&overlap, &imm16_32)
5952 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5953 {
40fb9820 5954 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5955 overlap = imm16;
40fb9820 5956 else
65da13b5 5957 overlap = imm32s;
29b0f896 5958 }
0dfbf9d7
L		 5959 if (!operand_type_equal (&overlap, &imm8)
5960 && !operand_type_equal (&overlap, &imm8s)
5961 && !operand_type_equal (&overlap, &imm16)
5962 && !operand_type_equal (&overlap, &imm32)
5963 && !operand_type_equal (&overlap, &imm32s)
5964 && !operand_type_equal (&overlap, &imm64))
29b0f896 5965 {
4eed87de
AM		 5966 as_bad (_("no instruction mnemonic suffix given; "
5967 "can't determine immediate size"));
29b0f896
AM		 5968 return 0;
5969 }
5970 }
40fb9820 5971 i.types[j] = overlap;
29b0f896 5972
40fb9820
L		 5973 return 1;
5974}
5975
5976static int
5977finalize_imm (void)
5978{
bc0844ae 5979 unsigned int j, n;
29b0f896 5980
bc0844ae
L		 5981 /* Update the first 2 immediate operands. */
5982 n = i.operands > 2 ? 2 : i.operands;
5983 if (n)
5984 {
5985 for (j = 0; j < n; j++)
5986 if (update_imm (j) == 0)
5987 return 0;
40fb9820 5988
bc0844ae
L		 5989 /* The 3rd operand can't be immediate operand. */
5990 gas_assert (operand_type_check (i.types[2], imm) == 0);
5991 }
29b0f896
AM		 5992
5993 return 1;
5994}
5995
5996static int
e3bb37b5 5997process_operands (void)
29b0f896
AM		 5998{
5999 /* Default segment register this instruction will use for memory
6000 accesses. 0 means unknown. This is only for optimizing out
6001 unnecessary segment overrides. */
6002 const seg_entry *default_seg = 0;
6003
2426c15f 6004 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 6005 {
91d6fa6a
NC		 6006 unsigned int dupl = i.operands;
6007 unsigned int dest = dupl - 1;
9fcfb3d7
L		 6008 unsigned int j;
6009
c0f3af97 6010 /* The destination must be an xmm register. */
9c2799c2 6011 gas_assert (i.reg_operands
91d6fa6a 6012 && MAX_OPERANDS > dupl
7ab9ffdd 6013 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 6014
1b54b8d7
JB		 6015 if (i.tm.operand_types[0].bitfield.acc
6016 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 6017 {
8cd7925b 6018 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6019 {
6020 /* Keep xmm0 for instructions with VEX prefix and 3
6021 sources. */
1b54b8d7
JB		 6022 i.tm.operand_types[0].bitfield.acc = 0;
6023 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 6024 goto duplicate;
6025 }
e2ec9d29 6026 else
c0f3af97
L		 6027 {
6028 /* We remove the first xmm0 and keep the number of
6029 operands unchanged, which in fact duplicates the
6030 destination. */
6031 for (j = 1; j < i.operands; j++)
6032 {
6033 i.op[j - 1] = i.op[j];
6034 i.types[j - 1] = i.types[j];
6035 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6036 }
6037 }
6038 }
6039 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6040 {
91d6fa6a 6041 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6042 && (i.tm.opcode_modifier.vexsources
6043 == VEX3SOURCES));
c0f3af97
L		 6044
6045 /* Add the implicit xmm0 for instructions with VEX prefix
6046 and 3 sources. */
6047 for (j = i.operands; j > 0; j--)
6048 {
6049 i.op[j] = i.op[j - 1];
6050 i.types[j] = i.types[j - 1];
6051 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6052 }
6053 i.op[0].regs
6054 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6055 i.types[0] = regxmm;
c0f3af97
L		 6056 i.tm.operand_types[0] = regxmm;
6057
6058 i.operands += 2;
6059 i.reg_operands += 2;
6060 i.tm.operands += 2;
6061
91d6fa6a 6062 dupl++;
c0f3af97 6063 dest++;
91d6fa6a
NC		 6064 i.op[dupl] = i.op[dest];
6065 i.types[dupl] = i.types[dest];
6066 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6067 }
c0f3af97
L		 6068 else
6069 {
6070duplicate:
6071 i.operands++;
6072 i.reg_operands++;
6073 i.tm.operands++;
6074
91d6fa6a
NC		 6075 i.op[dupl] = i.op[dest];
6076 i.types[dupl] = i.types[dest];
6077 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6078 }
6079
6080 if (i.tm.opcode_modifier.immext)
6081 process_immext ();
6082 }
1b54b8d7
JB		 6083 else if (i.tm.operand_types[0].bitfield.acc
6084 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6085 {
6086 unsigned int j;
6087
9fcfb3d7
L		 6088 for (j = 1; j < i.operands; j++)
6089 {
6090 i.op[j - 1] = i.op[j];
6091 i.types[j - 1] = i.types[j];
6092
6093 /* We need to adjust fields in i.tm since they are used by
6094 build_modrm_byte. */
6095 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6096 }
6097
e2ec9d29
L		 6098 i.operands--;
6099 i.reg_operands--;
e2ec9d29
L		 6100 i.tm.operands--;
6101 }
920d2ddc
IT		 6102 else if (i.tm.opcode_modifier.implicitquadgroup)
6103 {
6104 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10c17abd 6105 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
920d2ddc
IT		 6106 unsigned int regnum = register_number (i.op[1].regs);
6107 unsigned int first_reg_in_group = regnum & ~3;
6108 unsigned int last_reg_in_group = first_reg_in_group + 3;
6109 if (regnum != first_reg_in_group) {
6110 as_warn (_("the second source register `%s%s' implicitly denotes"
6111 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6112 register_prefix, i.op[1].regs->reg_name,
6113 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6114 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6115 i.tm.name);
6116 }
6117 }
e2ec9d29
L		 6118 else if (i.tm.opcode_modifier.regkludge)
6119 {
6120 /* The imul $imm, %reg instruction is converted into
6121 imul $imm, %reg, %reg, and the clr %reg instruction
6122 is converted into xor %reg, %reg. */
6123
6124 unsigned int first_reg_op;
6125
6126 if (operand_type_check (i.types[0], reg))
6127 first_reg_op = 0;
6128 else
6129 first_reg_op = 1;
6130 /* Pretend we saw the extra register operand. */
9c2799c2 6131 gas_assert (i.reg_operands == 1
7ab9ffdd 6132 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6133 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6134 i.types[first_reg_op + 1] = i.types[first_reg_op];
6135 i.operands++;
6136 i.reg_operands++;
29b0f896
AM		 6137 }
6138
40fb9820 6139 if (i.tm.opcode_modifier.shortform)
29b0f896 6140 {
40fb9820
L		 6141 if (i.types[0].bitfield.sreg2
6142 || i.types[0].bitfield.sreg3)
29b0f896 6143 {
4eed87de
AM		 6144 if (i.tm.base_opcode == POP_SEG_SHORT
6145 && i.op[0].regs->reg_num == 1)
29b0f896 6146 {
a87af027 6147 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6148 return 0;
29b0f896 6149 }
4eed87de
AM		 6150 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6151 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6152 i.rex |= REX_B;
4eed87de
AM		 6153 }
6154 else
6155 {
7ab9ffdd 6156 /* The register or float register operand is in operand
85f10a01 6157 0 or 1. */
40fb9820 6158 unsigned int op;
7ab9ffdd 6159
ca0d63fe 6160 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6161 || operand_type_check (i.types[0], reg))
6162 op = 0;
6163 else
6164 op = 1;
4eed87de
AM		 6165 /* Register goes in low 3 bits of opcode. */
6166 i.tm.base_opcode |= i.op[op].regs->reg_num;
6167 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6168 i.rex |= REX_B;
40fb9820 6169 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6170 {
4eed87de
AM		 6171 /* Warn about some common errors, but press on regardless.
6172 The first case can be generated by gcc (<= 2.8.1). */
6173 if (i.operands == 2)
6174 {
6175 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6176 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6177 register_prefix, i.op[!intel_syntax].regs->reg_name,
6178 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6179 }
6180 else
6181 {
6182 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6183 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6184 register_prefix, i.op[0].regs->reg_name);
4eed87de 6185 }
29b0f896
AM		 6186 }
6187 }
6188 }
40fb9820 6189 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6190 {
6191 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6192 must be put into the modrm byte). Now, we make the modrm and
6193 index base bytes based on all the info we've collected. */
29b0f896
AM		 6194
6195 default_seg = build_modrm_byte ();
6196 }
8a2ed489 6197 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6198 {
6199 default_seg = &ds;
6200 }
40fb9820 6201 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6202 {
6203 /* For the string instructions that allow a segment override
6204 on one of their operands, the default segment is ds. */
6205 default_seg = &ds;
6206 }
6207
75178d9d
L		 6208 if (i.tm.base_opcode == 0x8d /* lea */
6209 && i.seg[0]
6210 && !quiet_warnings)
30123838 6211 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6212
6213 /* If a segment was explicitly specified, and the specified segment
6214 is not the default, use an opcode prefix to select it. If we
6215 never figured out what the default segment is, then default_seg
6216 will be zero at this point, and the specified segment prefix will
6217 always be used. */
29b0f896
AM		 6218 if ((i.seg[0]) && (i.seg[0] != default_seg))
6219 {
6220 if (!add_prefix (i.seg[0]->seg_prefix))
6221 return 0;
6222 }
6223 return 1;
6224}
6225
6226static const seg_entry *
e3bb37b5 6227build_modrm_byte (void)
29b0f896
AM		 6228{
6229 const seg_entry *default_seg = 0;
c0f3af97 6230 unsigned int source, dest;
8cd7925b 6231 int vex_3_sources;
c0f3af97
L		 6232
6233 /* The first operand of instructions with VEX prefix and 3 sources
6234 must be VEX_Imm4. */
8cd7925b 6235 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6236 if (vex_3_sources)
6237 {
91d6fa6a 6238 unsigned int nds, reg_slot;
4c2c6516 6239 expressionS *exp;
c0f3af97 6240
922d8de8 6241 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6242 && i.tm.opcode_modifier.immext)
6243 {
6244 dest = i.operands - 2;
6245 gas_assert (dest == 3);
6246 }
922d8de8 6247 else
a683cc34 6248 dest = i.operands - 1;
c0f3af97 6249 nds = dest - 1;
922d8de8 6250
a683cc34
SP		 6251 /* There are 2 kinds of instructions:
6252 1. 5 operands: 4 register operands or 3 register operands
6253 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6254 VexW0 or VexW1. The destination must be either XMM, YMM or
6255 ZMM register.
a683cc34
SP		 6256 2. 4 operands: 4 register operands or 3 register operands
6257 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6258 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6259 || (i.reg_operands == 3 && i.mem_operands == 1))
6260 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6261 && (i.tm.opcode_modifier.veximmext
6262 || (i.imm_operands == 1
6263 && i.types[0].bitfield.vec_imm4
6264 && (i.tm.opcode_modifier.vexw == VEXW0
6265 || i.tm.opcode_modifier.vexw == VEXW1)
10c17abd 6266 && i.tm.operand_types[dest].bitfield.regsimd)));
a683cc34
SP		 6267
6268 if (i.imm_operands == 0)
6269 {
6270 /* When there is no immediate operand, generate an 8bit
6271 immediate operand to encode the first operand. */
6272 exp = &im_expressions[i.imm_operands++];
6273 i.op[i.operands].imms = exp;
6274 i.types[i.operands] = imm8;
6275 i.operands++;
6276 /* If VexW1 is set, the first operand is the source and
6277 the second operand is encoded in the immediate operand. */
6278 if (i.tm.opcode_modifier.vexw == VEXW1)
6279 {
6280 source = 0;
6281 reg_slot = 1;
6282 }
6283 else
6284 {
6285 source = 1;
6286 reg_slot = 0;
6287 }
6288
6289 /* FMA swaps REG and NDS. */
6290 if (i.tm.cpu_flags.bitfield.cpufma)
6291 {
6292 unsigned int tmp;
6293 tmp = reg_slot;
6294 reg_slot = nds;
6295 nds = tmp;
6296 }
6297
10c17abd 6298 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
a683cc34 6299 exp->X_op = O_constant;
4c692bc7 6300 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6301 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6302 }
922d8de8 6303 else
a683cc34
SP		 6304 {
6305 unsigned int imm_slot;
6306
6307 if (i.tm.opcode_modifier.vexw == VEXW0)
6308 {
6309 /* If VexW0 is set, the third operand is the source and
6310 the second operand is encoded in the immediate
6311 operand. */
6312 source = 2;
6313 reg_slot = 1;
6314 }
6315 else
6316 {
6317 /* VexW1 is set, the second operand is the source and
6318 the third operand is encoded in the immediate
6319 operand. */
6320 source = 1;
6321 reg_slot = 2;
6322 }
6323
6324 if (i.tm.opcode_modifier.immext)
6325 {
33eaf5de 6326 /* When ImmExt is set, the immediate byte is the last
a683cc34
SP		 6327 operand. */
6328 imm_slot = i.operands - 1;
6329 source--;
6330 reg_slot--;
6331 }
6332 else
6333 {
6334 imm_slot = 0;
6335
6336 /* Turn on Imm8 so that output_imm will generate it. */
6337 i.types[imm_slot].bitfield.imm8 = 1;
6338 }
6339
10c17abd 6340 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
a683cc34 6341 i.op[imm_slot].imms->X_add_number
4c692bc7 6342 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6343 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6344 }
6345
10c17abd 6346 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
dae39acc 6347 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6348 }
6349 else
6350 source = dest = 0;
29b0f896
AM		 6351
6352 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6353 implicit registers do not count. If there are 3 register
6354 operands, it must be a instruction with VexNDS. For a
6355 instruction with VexNDD, the destination register is encoded
6356 in VEX prefix. If there are 4 register operands, it must be
6357 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6358 if (i.mem_operands == 0
6359 && ((i.reg_operands == 2
2426c15f 6360 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6361 || (i.reg_operands == 3
2426c15f 6362 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6363 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6364 {
cab737b9
L		 6365 switch (i.operands)
6366 {
6367 case 2:
6368 source = 0;
6369 break;
6370 case 3:
c81128dc
L		 6371 /* When there are 3 operands, one of them may be immediate,
6372 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6373 the first operand must be shift count register (cl) or it
6374 is an instruction with VexNDS. */
9c2799c2 6375 gas_assert (i.imm_operands == 1
7ab9ffdd 6376 || (i.imm_operands == 0
2426c15f 6377 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6378 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6379 if (operand_type_check (i.types[0], imm)
6380 || i.types[0].bitfield.shiftcount)
6381 source = 1;
6382 else
6383 source = 0;
cab737b9
L		 6384 break;
6385 case 4:
368d64cc
L		 6386 /* When there are 4 operands, the first two must be 8bit
6387 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6388 one.
6389
6390 For instructions with VexNDS, if the first operand
6391 an imm8, the source operand is the 2nd one. If the last
6392 operand is imm8, the source operand is the first one. */
9c2799c2 6393 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6394 && i.types[0].bitfield.imm8
6395 && i.types[1].bitfield.imm8)
2426c15f 6396 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6397 && i.imm_operands == 1
6398 && (i.types[0].bitfield.imm8
43234a1e
L		 6399 || i.types[i.operands - 1].bitfield.imm8
6400 || i.rounding)));
9f2670f2
L		 6401 if (i.imm_operands == 2)
6402 source = 2;
6403 else
c0f3af97
L		 6404 {
6405 if (i.types[0].bitfield.imm8)
6406 source = 1;
6407 else
6408 source = 0;
6409 }
c0f3af97
L		 6410 break;
6411 case 5:
43234a1e
L		 6412 if (i.tm.opcode_modifier.evex)
6413 {
6414 /* For EVEX instructions, when there are 5 operands, the
6415 first one must be immediate operand. If the second one
6416 is immediate operand, the source operand is the 3th
6417 one. If the last one is immediate operand, the source
6418 operand is the 2nd one. */
6419 gas_assert (i.imm_operands == 2
6420 && i.tm.opcode_modifier.sae
6421 && operand_type_check (i.types[0], imm));
6422 if (operand_type_check (i.types[1], imm))
6423 source = 2;
6424 else if (operand_type_check (i.types[4], imm))
6425 source = 1;
6426 else
6427 abort ();
6428 }
cab737b9
L		 6429 break;
6430 default:
6431 abort ();
6432 }
6433
c0f3af97
L		 6434 if (!vex_3_sources)
6435 {
6436 dest = source + 1;
6437
43234a1e
L		 6438 /* RC/SAE operand could be between DEST and SRC. That happens
6439 when one operand is GPR and the other one is XMM/YMM/ZMM
6440 register. */
6441 if (i.rounding && i.rounding->operand == (int) dest)
6442 dest++;
6443
2426c15f 6444 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6445 {
43234a1e 6446 /* For instructions with VexNDS, the register-only source
c5d0745b 6447 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 6448 register. It is encoded in VEX prefix. We need to
6449 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6450
6451 i386_operand_type op;
6452 unsigned int vvvv;
6453
6454 /* Check register-only source operand when two source
6455 operands are swapped. */
6456 if (!i.tm.operand_types[source].bitfield.baseindex
6457 && i.tm.operand_types[dest].bitfield.baseindex)
6458 {
6459 vvvv = source;
6460 source = dest;
6461 }
6462 else
6463 vvvv = dest;
6464
6465 op = i.tm.operand_types[vvvv];
fa99fab2 6466 op.bitfield.regmem = 0;
c0f3af97 6467 if ((dest + 1) >= i.operands
dc821c5f
JB		 6468 || ((!op.bitfield.reg
6469 || (!op.bitfield.dword && !op.bitfield.qword))
10c17abd 6470 && !op.bitfield.regsimd
43234a1e 6471 && !operand_type_equal (&op, &regmask)))
c0f3af97 6472 abort ();
f12dc422 6473 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6474 dest++;
6475 }
6476 }
29b0f896
AM		 6477
6478 i.rm.mode = 3;
6479 /* One of the register operands will be encoded in the i.tm.reg
6480 field, the other in the combined i.tm.mode and i.tm.regmem
6481 fields. If no form of this instruction supports a memory
6482 destination operand, then we assume the source operand may
6483 sometimes be a memory operand and so we need to store the
6484 destination in the i.rm.reg field. */
40fb9820
L		 6485 if (!i.tm.operand_types[dest].bitfield.regmem
6486 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6487 {
6488 i.rm.reg = i.op[dest].regs->reg_num;
6489 i.rm.regmem = i.op[source].regs->reg_num;
6490 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6491 i.rex |= REX_R;
43234a1e
L		 6492 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6493 i.vrex |= REX_R;
29b0f896 6494 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6495 i.rex |= REX_B;
43234a1e
L		 6496 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6497 i.vrex |= REX_B;
29b0f896
AM		 6498 }
6499 else
6500 {
6501 i.rm.reg = i.op[source].regs->reg_num;
6502 i.rm.regmem = i.op[dest].regs->reg_num;
6503 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6504 i.rex |= REX_B;
43234a1e
L		 6505 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6506 i.vrex |= REX_B;
29b0f896 6507 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6508 i.rex |= REX_R;
43234a1e
L		 6509 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6510 i.vrex |= REX_R;
29b0f896 6511 }
161a04f6 6512 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6513 {
40fb9820
L		 6514 if (!i.types[0].bitfield.control
6515 && !i.types[1].bitfield.control)
c4a530c5 6516 abort ();
161a04f6 6517 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6518 add_prefix (LOCK_PREFIX_OPCODE);
6519 }
29b0f896
AM		 6520 }
6521 else
6522 { /* If it's not 2 reg operands... */
c0f3af97
L		 6523 unsigned int mem;
6524
29b0f896
AM		 6525 if (i.mem_operands)
6526 {
6527 unsigned int fake_zero_displacement = 0;
99018f42 6528 unsigned int op;
4eed87de 6529
7ab9ffdd
L		 6530 for (op = 0; op < i.operands; op++)
6531 if (operand_type_check (i.types[op], anymem))
6532 break;
7ab9ffdd 6533 gas_assert (op < i.operands);
29b0f896 6534
6c30d220
L		 6535 if (i.tm.opcode_modifier.vecsib)
6536 {
6537 if (i.index_reg->reg_num == RegEiz
6538 || i.index_reg->reg_num == RegRiz)
6539 abort ();
6540
6541 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6542 if (!i.base_reg)
6543 {
6544 i.sib.base = NO_BASE_REGISTER;
6545 i.sib.scale = i.log2_scale_factor;
6546 i.types[op].bitfield.disp8 = 0;
6547 i.types[op].bitfield.disp16 = 0;
6548 i.types[op].bitfield.disp64 = 0;
43083a50 6549 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 6550 {
6551 /* Must be 32 bit */
6552 i.types[op].bitfield.disp32 = 1;
6553 i.types[op].bitfield.disp32s = 0;
6554 }
6555 else
6556 {
6557 i.types[op].bitfield.disp32 = 0;
6558 i.types[op].bitfield.disp32s = 1;
6559 }
6560 }
6561 i.sib.index = i.index_reg->reg_num;
6562 if ((i.index_reg->reg_flags & RegRex) != 0)
6563 i.rex |= REX_X;
43234a1e
L		 6564 if ((i.index_reg->reg_flags & RegVRex) != 0)
6565 i.vrex |= REX_X;
6c30d220
L		 6566 }
6567
29b0f896
AM		 6568 default_seg = &ds;
6569
6570 if (i.base_reg == 0)
6571 {
6572 i.rm.mode = 0;
6573 if (!i.disp_operands)
9bb129e8 6574 fake_zero_displacement = 1;
29b0f896
AM		 6575 if (i.index_reg == 0)
6576 {
6c30d220 6577 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6578 /* Operand is just <disp> */
20f0a1fc 6579 if (flag_code == CODE_64BIT)
29b0f896
AM		 6580 {
6581 /* 64bit mode overwrites the 32bit absolute
6582 addressing by RIP relative addressing and
6583 absolute addressing is encoded by one of the
6584 redundant SIB forms. */
6585 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6586 i.sib.base = NO_BASE_REGISTER;
6587 i.sib.index = NO_INDEX_REGISTER;
fc225355 6588 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6589 ? disp32s : disp32);
20f0a1fc 6590 }
fc225355
L		 6591 else if ((flag_code == CODE_16BIT)
6592 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6593 {
6594 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6595 i.types[op] = disp16;
20f0a1fc
NC		 6596 }
6597 else
6598 {
6599 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6600 i.types[op] = disp32;
29b0f896
AM		 6601 }
6602 }
6c30d220 6603 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6604 {
6c30d220 6605 /* !i.base_reg && i.index_reg */
db51cc60
L		 6606 if (i.index_reg->reg_num == RegEiz
6607 || i.index_reg->reg_num == RegRiz)
6608 i.sib.index = NO_INDEX_REGISTER;
6609 else
6610 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6611 i.sib.base = NO_BASE_REGISTER;
6612 i.sib.scale = i.log2_scale_factor;
6613 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 6614 i.types[op].bitfield.disp8 = 0;
6615 i.types[op].bitfield.disp16 = 0;
6616 i.types[op].bitfield.disp64 = 0;
43083a50 6617 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 6618 {
6619 /* Must be 32 bit */
6620 i.types[op].bitfield.disp32 = 1;
6621 i.types[op].bitfield.disp32s = 0;
6622 }
29b0f896 6623 else
40fb9820
L		 6624 {
6625 i.types[op].bitfield.disp32 = 0;
6626 i.types[op].bitfield.disp32s = 1;
6627 }
29b0f896 6628 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6629 i.rex |= REX_X;
29b0f896
AM		 6630 }
6631 }
6632 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6633 else if (i.base_reg->reg_num == RegRip ||
6634 i.base_reg->reg_num == RegEip)
29b0f896 6635 {
6c30d220 6636 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6637 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6638 i.types[op].bitfield.disp8 = 0;
6639 i.types[op].bitfield.disp16 = 0;
6640 i.types[op].bitfield.disp32 = 0;
6641 i.types[op].bitfield.disp32s = 1;
6642 i.types[op].bitfield.disp64 = 0;
71903a11 6643 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6644 if (! i.disp_operands)
6645 fake_zero_displacement = 1;
29b0f896 6646 }
dc821c5f 6647 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 6648 {
6c30d220 6649 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6650 switch (i.base_reg->reg_num)
6651 {
6652 case 3: /* (%bx) */
6653 if (i.index_reg == 0)
6654 i.rm.regmem = 7;
6655 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6656 i.rm.regmem = i.index_reg->reg_num - 6;
6657 break;
6658 case 5: /* (%bp) */
6659 default_seg = &ss;
6660 if (i.index_reg == 0)
6661 {
6662 i.rm.regmem = 6;
40fb9820 6663 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6664 {
6665 /* fake (%bp) into 0(%bp) */
b5014f7a 6666 i.types[op].bitfield.disp8 = 1;
252b5132 6667 fake_zero_displacement = 1;
29b0f896
AM		 6668 }
6669 }
6670 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6671 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6672 break;
6673 default: /* (%si) -> 4 or (%di) -> 5 */
6674 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6675 }
6676 i.rm.mode = mode_from_disp_size (i.types[op]);
6677 }
6678 else /* i.base_reg and 32/64 bit mode */
6679 {
6680 if (flag_code == CODE_64BIT
40fb9820
L		 6681 && operand_type_check (i.types[op], disp))
6682 {
6683 i386_operand_type temp;
0dfbf9d7 6684 operand_type_set (&temp, 0);
40fb9820
L		 6685 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6686 i.types[op] = temp;
6687 if (i.prefix[ADDR_PREFIX] == 0)
6688 i.types[op].bitfield.disp32s = 1;
6689 else
6690 i.types[op].bitfield.disp32 = 1;
6691 }
20f0a1fc 6692
6c30d220
L		 6693 if (!i.tm.opcode_modifier.vecsib)
6694 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6695 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6696 i.rex |= REX_B;
29b0f896
AM		 6697 i.sib.base = i.base_reg->reg_num;
6698 /* x86-64 ignores REX prefix bit here to avoid decoder
6699 complications. */
848930b2
JB		 6700 if (!(i.base_reg->reg_flags & RegRex)
6701 && (i.base_reg->reg_num == EBP_REG_NUM
6702 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6703 default_seg = &ss;
848930b2 6704 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6705 {
848930b2 6706 fake_zero_displacement = 1;
b5014f7a 6707 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6708 }
6709 i.sib.scale = i.log2_scale_factor;
6710 if (i.index_reg == 0)
6711 {
6c30d220 6712 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6713 /* <disp>(%esp) becomes two byte modrm with no index
6714 register. We've already stored the code for esp
6715 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6716 Any base register besides %esp will not use the
6717 extra modrm byte. */
6718 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6719 }
6c30d220 6720 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6721 {
db51cc60
L		 6722 if (i.index_reg->reg_num == RegEiz
6723 || i.index_reg->reg_num == RegRiz)
6724 i.sib.index = NO_INDEX_REGISTER;
6725 else
6726 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6727 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6728 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6729 i.rex |= REX_X;
29b0f896 6730 }
67a4f2b7
AO		 6731
6732 if (i.disp_operands
6733 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6734 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6735 i.rm.mode = 0;
6736 else
a501d77e
L		 6737 {
6738 if (!fake_zero_displacement
6739 && !i.disp_operands
6740 && i.disp_encoding)
6741 {
6742 fake_zero_displacement = 1;
6743 if (i.disp_encoding == disp_encoding_8bit)
6744 i.types[op].bitfield.disp8 = 1;
6745 else
6746 i.types[op].bitfield.disp32 = 1;
6747 }
6748 i.rm.mode = mode_from_disp_size (i.types[op]);
6749 }
29b0f896 6750 }
252b5132 6751
29b0f896
AM		 6752 if (fake_zero_displacement)
6753 {
6754 /* Fakes a zero displacement assuming that i.types[op]
6755 holds the correct displacement size. */
6756 expressionS *exp;
6757
9c2799c2 6758 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6759 exp = &disp_expressions[i.disp_operands++];
6760 i.op[op].disps = exp;
6761 exp->X_op = O_constant;
6762 exp->X_add_number = 0;
6763 exp->X_add_symbol = (symbolS *) 0;
6764 exp->X_op_symbol = (symbolS *) 0;
6765 }
c0f3af97
L		 6766
6767 mem = op;
29b0f896 6768 }
c0f3af97
L		 6769 else
6770 mem = ~0;
252b5132 6771
8c43a48b 6772 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6773 {
6774 if (operand_type_check (i.types[0], imm))
6775 i.vex.register_specifier = NULL;
6776 else
6777 {
6778 /* VEX.vvvv encodes one of the sources when the first
6779 operand is not an immediate. */
1ef99a7b 6780 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6781 i.vex.register_specifier = i.op[0].regs;
6782 else
6783 i.vex.register_specifier = i.op[1].regs;
6784 }
6785
6786 /* Destination is a XMM register encoded in the ModRM.reg
6787 and VEX.R bit. */
6788 i.rm.reg = i.op[2].regs->reg_num;
6789 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6790 i.rex |= REX_R;
6791
6792 /* ModRM.rm and VEX.B encodes the other source. */
6793 if (!i.mem_operands)
6794 {
6795 i.rm.mode = 3;
6796
1ef99a7b 6797 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6798 i.rm.regmem = i.op[1].regs->reg_num;
6799 else
6800 i.rm.regmem = i.op[0].regs->reg_num;
6801
6802 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6803 i.rex |= REX_B;
6804 }
6805 }
2426c15f 6806 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6807 {
6808 i.vex.register_specifier = i.op[2].regs;
6809 if (!i.mem_operands)
6810 {
6811 i.rm.mode = 3;
6812 i.rm.regmem = i.op[1].regs->reg_num;
6813 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6814 i.rex |= REX_B;
6815 }
6816 }
29b0f896
AM		 6817 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6818 (if any) based on i.tm.extension_opcode. Again, we must be
6819 careful to make sure that segment/control/debug/test/MMX
6820 registers are coded into the i.rm.reg field. */
f88c9eb0 6821 else if (i.reg_operands)
29b0f896 6822 {
99018f42 6823 unsigned int op;
7ab9ffdd
L		 6824 unsigned int vex_reg = ~0;
6825
6826 for (op = 0; op < i.operands; op++)
dc821c5f 6827 if (i.types[op].bitfield.reg
7ab9ffdd 6828 || i.types[op].bitfield.regmmx
1b54b8d7 6829 || i.types[op].bitfield.regsimd
7e8b059b 6830 || i.types[op].bitfield.regbnd
43234a1e 6831 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6832 || i.types[op].bitfield.sreg2
6833 || i.types[op].bitfield.sreg3
6834 || i.types[op].bitfield.control
6835 || i.types[op].bitfield.debug
6836 || i.types[op].bitfield.test)
6837 break;
c0209578 6838
7ab9ffdd
L		 6839 if (vex_3_sources)
6840 op = dest;
2426c15f 6841 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6842 {
6843 /* For instructions with VexNDS, the register-only
6844 source operand is encoded in VEX prefix. */
6845 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6846
7ab9ffdd 6847 if (op > mem)
c0f3af97 6848 {
7ab9ffdd
L		 6849 vex_reg = op++;
6850 gas_assert (op < i.operands);
c0f3af97
L		 6851 }
6852 else
c0f3af97 6853 {
f12dc422
L		 6854 /* Check register-only source operand when two source
6855 operands are swapped. */
6856 if (!i.tm.operand_types[op].bitfield.baseindex
6857 && i.tm.operand_types[op + 1].bitfield.baseindex)
6858 {
6859 vex_reg = op;
6860 op += 2;
6861 gas_assert (mem == (vex_reg + 1)
6862 && op < i.operands);
6863 }
6864 else
6865 {
6866 vex_reg = op + 1;
6867 gas_assert (vex_reg < i.operands);
6868 }
c0f3af97 6869 }
7ab9ffdd 6870 }
2426c15f 6871 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6872 {
f12dc422 6873 /* For instructions with VexNDD, the register destination
7ab9ffdd 6874 is encoded in VEX prefix. */
f12dc422
L		 6875 if (i.mem_operands == 0)
6876 {
6877 /* There is no memory operand. */
6878 gas_assert ((op + 2) == i.operands);
6879 vex_reg = op + 1;
6880 }
6881 else
8d63c93e 6882 {
f12dc422
L		 6883 /* There are only 2 operands. */
6884 gas_assert (op < 2 && i.operands == 2);
6885 vex_reg = 1;
6886 }
7ab9ffdd
L		 6887 }
6888 else
6889 gas_assert (op < i.operands);
99018f42 6890
7ab9ffdd
L		 6891 if (vex_reg != (unsigned int) ~0)
6892 {
f12dc422 6893 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6894
dc821c5f
JB		 6895 if ((!type->bitfield.reg
6896 || (!type->bitfield.dword && !type->bitfield.qword))
10c17abd 6897 && !type->bitfield.regsimd
43234a1e 6898 && !operand_type_equal (type, &regmask))
7ab9ffdd 6899 abort ();
f88c9eb0 6900
7ab9ffdd
L		 6901 i.vex.register_specifier = i.op[vex_reg].regs;
6902 }
6903
1b9f0c97
L		 6904 /* Don't set OP operand twice. */
6905 if (vex_reg != op)
7ab9ffdd 6906 {
1b9f0c97
L		 6907 /* If there is an extension opcode to put here, the
6908 register number must be put into the regmem field. */
6909 if (i.tm.extension_opcode != None)
6910 {
6911 i.rm.regmem = i.op[op].regs->reg_num;
6912 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6913 i.rex |= REX_B;
43234a1e
L		 6914 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6915 i.vrex |= REX_B;
1b9f0c97
L		 6916 }
6917 else
6918 {
6919 i.rm.reg = i.op[op].regs->reg_num;
6920 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6921 i.rex |= REX_R;
43234a1e
L		 6922 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6923 i.vrex |= REX_R;
1b9f0c97 6924 }
7ab9ffdd 6925 }
252b5132 6926
29b0f896
AM		 6927 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6928 must set it to 3 to indicate this is a register operand
6929 in the regmem field. */
6930 if (!i.mem_operands)
6931 i.rm.mode = 3;
6932 }
252b5132 6933
29b0f896 6934 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6935 if (i.tm.extension_opcode != None)
29b0f896
AM		 6936 i.rm.reg = i.tm.extension_opcode;
6937 }
6938 return default_seg;
6939}
252b5132 6940
29b0f896 6941static void
e3bb37b5 6942output_branch (void)
29b0f896
AM		 6943{
6944 char *p;
f8a5c266 6945 int size;
29b0f896
AM		 6946 int code16;
6947 int prefix;
6948 relax_substateT subtype;
6949 symbolS *sym;
6950 offsetT off;
6951
f8a5c266 6952 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6953 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6954
6955 prefix = 0;
6956 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6957 {
29b0f896
AM		 6958 prefix = 1;
6959 i.prefixes -= 1;
6960 code16 ^= CODE16;
252b5132 6961 }
29b0f896
AM		 6962 /* Pentium4 branch hints. */
6963 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6964 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6965 {
29b0f896
AM		 6966 prefix++;
6967 i.prefixes--;
6968 }
6969 if (i.prefix[REX_PREFIX] != 0)
6970 {
6971 prefix++;
6972 i.prefixes--;
2f66722d
AM		 6973 }
6974
7e8b059b
L		 6975 /* BND prefixed jump. */
6976 if (i.prefix[BND_PREFIX] != 0)
6977 {
6978 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6979 i.prefixes -= 1;
6980 }
6981
29b0f896
AM		 6982 if (i.prefixes != 0 && !intel_syntax)
6983 as_warn (_("skipping prefixes on this instruction"));
6984
6985 /* It's always a symbol; End frag & setup for relax.
6986 Make sure there is enough room in this frag for the largest
6987 instruction we may generate in md_convert_frag. This is 2
6988 bytes for the opcode and room for the prefix and largest
6989 displacement. */
6990 frag_grow (prefix + 2 + 4);
6991 /* Prefix and 1 opcode byte go in fr_fix. */
6992 p = frag_more (prefix + 1);
6993 if (i.prefix[DATA_PREFIX] != 0)
6994 *p++ = DATA_PREFIX_OPCODE;
6995 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6996 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6997 *p++ = i.prefix[SEG_PREFIX];
6998 if (i.prefix[REX_PREFIX] != 0)
6999 *p++ = i.prefix[REX_PREFIX];
7000 *p = i.tm.base_opcode;
7001
7002 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7003 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7004 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7005 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7006 else
f8a5c266 7007 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7008 subtype |= code16;
3e73aa7c 7009
29b0f896
AM		 7010 sym = i.op[0].disps->X_add_symbol;
7011 off = i.op[0].disps->X_add_number;
3e73aa7c 7012
29b0f896
AM		 7013 if (i.op[0].disps->X_op != O_constant
7014 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7015 {
29b0f896
AM		 7016 /* Handle complex expressions. */
7017 sym = make_expr_symbol (i.op[0].disps);
7018 off = 0;
7019 }
3e73aa7c 7020
29b0f896
AM		 7021 /* 1 possible extra opcode + 4 byte displacement go in var part.
7022 Pass reloc in fr_var. */
d258b828 7023 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7024}
3e73aa7c 7025
29b0f896 7026static void
e3bb37b5 7027output_jump (void)
29b0f896
AM		 7028{
7029 char *p;
7030 int size;
3e02c1cc 7031 fixS *fixP;
29b0f896 7032
40fb9820 7033 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7034 {
7035 /* This is a loop or jecxz type instruction. */
7036 size = 1;
7037 if (i.prefix[ADDR_PREFIX] != 0)
7038 {
7039 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7040 i.prefixes -= 1;
7041 }
7042 /* Pentium4 branch hints. */
7043 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7044 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7045 {
7046 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7047 i.prefixes--;
3e73aa7c
JH		 7048 }
7049 }
29b0f896
AM		 7050 else
7051 {
7052 int code16;
3e73aa7c 7053
29b0f896
AM		 7054 code16 = 0;
7055 if (flag_code == CODE_16BIT)
7056 code16 = CODE16;
3e73aa7c 7057
29b0f896
AM		 7058 if (i.prefix[DATA_PREFIX] != 0)
7059 {
7060 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7061 i.prefixes -= 1;
7062 code16 ^= CODE16;
7063 }
252b5132 7064
29b0f896
AM		 7065 size = 4;
7066 if (code16)
7067 size = 2;
7068 }
9fcc94b6 7069
29b0f896
AM		 7070 if (i.prefix[REX_PREFIX] != 0)
7071 {
7072 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7073 i.prefixes -= 1;
7074 }
252b5132 7075
7e8b059b
L		 7076 /* BND prefixed jump. */
7077 if (i.prefix[BND_PREFIX] != 0)
7078 {
7079 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7080 i.prefixes -= 1;
7081 }
7082
29b0f896
AM		 7083 if (i.prefixes != 0 && !intel_syntax)
7084 as_warn (_("skipping prefixes on this instruction"));
e0890092 7085
42164a71
L		 7086 p = frag_more (i.tm.opcode_length + size);
7087 switch (i.tm.opcode_length)
7088 {
7089 case 2:
7090 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7091 /* Fall through. */
42164a71
L		 7092 case 1:
7093 *p++ = i.tm.base_opcode;
7094 break;
7095 default:
7096 abort ();
7097 }
e0890092 7098
3e02c1cc 7099 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7100 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 7101
7102 /* All jumps handled here are signed, but don't use a signed limit
7103 check for 32 and 16 bit jumps as we want to allow wrap around at
7104 4G and 64k respectively. */
7105 if (size == 1)
7106 fixP->fx_signed = 1;
29b0f896 7107}
e0890092 7108
29b0f896 7109static void
e3bb37b5 7110output_interseg_jump (void)
29b0f896
AM		 7111{
7112 char *p;
7113 int size;
7114 int prefix;
7115 int code16;
252b5132 7116
29b0f896
AM		 7117 code16 = 0;
7118 if (flag_code == CODE_16BIT)
7119 code16 = CODE16;
a217f122 7120
29b0f896
AM		 7121 prefix = 0;
7122 if (i.prefix[DATA_PREFIX] != 0)
7123 {
7124 prefix = 1;
7125 i.prefixes -= 1;
7126 code16 ^= CODE16;
7127 }
7128 if (i.prefix[REX_PREFIX] != 0)
7129 {
7130 prefix++;
7131 i.prefixes -= 1;
7132 }
252b5132 7133
29b0f896
AM		 7134 size = 4;
7135 if (code16)
7136 size = 2;
252b5132 7137
29b0f896
AM		 7138 if (i.prefixes != 0 && !intel_syntax)
7139 as_warn (_("skipping prefixes on this instruction"));
252b5132 7140
29b0f896
AM		 7141 /* 1 opcode; 2 segment; offset */
7142 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7143
29b0f896
AM		 7144 if (i.prefix[DATA_PREFIX] != 0)
7145 *p++ = DATA_PREFIX_OPCODE;
252b5132 7146
29b0f896
AM		 7147 if (i.prefix[REX_PREFIX] != 0)
7148 *p++ = i.prefix[REX_PREFIX];
252b5132 7149
29b0f896
AM		 7150 *p++ = i.tm.base_opcode;
7151 if (i.op[1].imms->X_op == O_constant)
7152 {
7153 offsetT n = i.op[1].imms->X_add_number;
252b5132 7154
29b0f896
AM		 7155 if (size == 2
7156 && !fits_in_unsigned_word (n)
7157 && !fits_in_signed_word (n))
7158 {
7159 as_bad (_("16-bit jump out of range"));
7160 return;
7161 }
7162 md_number_to_chars (p, n, size);
7163 }
7164 else
7165 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7166 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7167 if (i.op[0].imms->X_op != O_constant)
7168 as_bad (_("can't handle non absolute segment in `%s'"),
7169 i.tm.name);
7170 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7171}
a217f122 7172
29b0f896 7173static void
e3bb37b5 7174output_insn (void)
29b0f896 7175{
2bbd9c25
JJ		 7176 fragS *insn_start_frag;
7177 offsetT insn_start_off;
7178
29b0f896
AM		 7179 /* Tie dwarf2 debug info to the address at the start of the insn.
7180 We can't do this after the insn has been output as the current
7181 frag may have been closed off. eg. by frag_var. */
7182 dwarf2_emit_insn (0);
7183
2bbd9c25
JJ		 7184 insn_start_frag = frag_now;
7185 insn_start_off = frag_now_fix ();
7186
29b0f896 7187 /* Output jumps. */
40fb9820 7188 if (i.tm.opcode_modifier.jump)
29b0f896 7189 output_branch ();
40fb9820
L		 7190 else if (i.tm.opcode_modifier.jumpbyte
7191 || i.tm.opcode_modifier.jumpdword)
29b0f896 7192 output_jump ();
40fb9820 7193 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7194 output_interseg_jump ();
7195 else
7196 {
7197 /* Output normal instructions here. */
7198 char *p;
7199 unsigned char *q;
47465058 7200 unsigned int j;
331d2d0d 7201 unsigned int prefix;
4dffcebc 7202
e4e00185
AS		 7203 if (avoid_fence
7204 && i.tm.base_opcode == 0xfae
7205 && i.operands == 1
7206 && i.imm_operands == 1
7207 && (i.op[0].imms->X_add_number == 0xe8
7208 || i.op[0].imms->X_add_number == 0xf0
7209 || i.op[0].imms->X_add_number == 0xf8))
7210 {
7211 /* Encode lfence, mfence, and sfence as
7212 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7213 offsetT val = 0x240483f0ULL;
7214 p = frag_more (5);
7215 md_number_to_chars (p, val, 5);
7216 return;
7217 }
7218
d022bddd
IT		 7219 /* Some processors fail on LOCK prefix. This options makes
7220 assembler ignore LOCK prefix and serves as a workaround. */
7221 if (omit_lock_prefix)
7222 {
7223 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7224 return;
7225 i.prefix[LOCK_PREFIX] = 0;
7226 }
7227
43234a1e
L		 7228 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7229 don't need the explicit prefix. */
7230 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7231 {
c0f3af97 7232 switch (i.tm.opcode_length)
bc4bd9ab 7233 {
c0f3af97
L		 7234 case 3:
7235 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7236 {
c0f3af97
L		 7237 prefix = (i.tm.base_opcode >> 24) & 0xff;
7238 goto check_prefix;
7239 }
7240 break;
7241 case 2:
7242 if ((i.tm.base_opcode & 0xff0000) != 0)
7243 {
7244 prefix = (i.tm.base_opcode >> 16) & 0xff;
7245 if (i.tm.cpu_flags.bitfield.cpupadlock)
7246 {
4dffcebc 7247check_prefix:
c0f3af97 7248 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7249 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7250 != REPE_PREFIX_OPCODE))
7251 add_prefix (prefix);
7252 }
7253 else
4dffcebc
L		 7254 add_prefix (prefix);
7255 }
c0f3af97
L		 7256 break;
7257 case 1:
7258 break;
390c91cf
L		 7259 case 0:
7260 /* Check for pseudo prefixes. */
7261 as_bad_where (insn_start_frag->fr_file,
7262 insn_start_frag->fr_line,
7263 _("pseudo prefix without instruction"));
7264 return;
c0f3af97
L		 7265 default:
7266 abort ();
bc4bd9ab 7267 }
c0f3af97 7268
6d19a37a 7269#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7270 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7271 R_X86_64_GOTTPOFF relocation so that linker can safely
7272 perform IE->LE optimization. */
7273 if (x86_elf_abi == X86_64_X32_ABI
7274 && i.operands == 2
7275 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7276 && i.prefix[REX_PREFIX] == 0)
7277 add_prefix (REX_OPCODE);
6d19a37a 7278#endif
cf61b747 7279
c0f3af97
L		 7280 /* The prefix bytes. */
7281 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7282 if (*q)
7283 FRAG_APPEND_1_CHAR (*q);
0f10071e 7284 }
ae5c1c7b 7285 else
c0f3af97
L		 7286 {
7287 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7288 if (*q)
7289 switch (j)
7290 {
7291 case REX_PREFIX:
7292 /* REX byte is encoded in VEX prefix. */
7293 break;
7294 case SEG_PREFIX:
7295 case ADDR_PREFIX:
7296 FRAG_APPEND_1_CHAR (*q);
7297 break;
7298 default:
7299 /* There should be no other prefixes for instructions
7300 with VEX prefix. */
7301 abort ();
7302 }
7303
43234a1e
L		 7304 /* For EVEX instructions i.vrex should become 0 after
7305 build_evex_prefix. For VEX instructions upper 16 registers
7306 aren't available, so VREX should be 0. */
7307 if (i.vrex)
7308 abort ();
c0f3af97
L		 7309 /* Now the VEX prefix. */
7310 p = frag_more (i.vex.length);
7311 for (j = 0; j < i.vex.length; j++)
7312 p[j] = i.vex.bytes[j];
7313 }
252b5132 7314
29b0f896 7315 /* Now the opcode; be careful about word order here! */
4dffcebc 7316 if (i.tm.opcode_length == 1)
29b0f896
AM		 7317 {
7318 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7319 }
7320 else
7321 {
4dffcebc 7322 switch (i.tm.opcode_length)
331d2d0d 7323 {
43234a1e
L		 7324 case 4:
7325 p = frag_more (4);
7326 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7327 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7328 break;
4dffcebc 7329 case 3:
331d2d0d
L		 7330 p = frag_more (3);
7331 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7332 break;
7333 case 2:
7334 p = frag_more (2);
7335 break;
7336 default:
7337 abort ();
7338 break;
331d2d0d 7339 }
0f10071e 7340
29b0f896
AM		 7341 /* Put out high byte first: can't use md_number_to_chars! */
7342 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7343 *p = i.tm.base_opcode & 0xff;
7344 }
3e73aa7c 7345
29b0f896 7346 /* Now the modrm byte and sib byte (if present). */
40fb9820 7347 if (i.tm.opcode_modifier.modrm)
29b0f896 7348 {
4a3523fa
L		 7349 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7350 | i.rm.reg << 3
7351 | i.rm.mode << 6));
29b0f896
AM		 7352 /* If i.rm.regmem == ESP (4)
7353 && i.rm.mode != (Register mode)
7354 && not 16 bit
7355 ==> need second modrm byte. */
7356 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7357 && i.rm.mode != 3
dc821c5f 7358 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 7359 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7360 | i.sib.index << 3
7361 | i.sib.scale << 6));
29b0f896 7362 }
3e73aa7c 7363
29b0f896 7364 if (i.disp_operands)
2bbd9c25 7365 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7366
29b0f896 7367 if (i.imm_operands)
2bbd9c25 7368 output_imm (insn_start_frag, insn_start_off);
29b0f896 7369 }
252b5132 7370
29b0f896
AM		 7371#ifdef DEBUG386
7372 if (flag_debug)
7373 {
7b81dfbb 7374 pi ("" /*line*/, &i);
29b0f896
AM		 7375 }
7376#endif /* DEBUG386 */
7377}
252b5132 7378
e205caa7
L		 7379/* Return the size of the displacement operand N. */
7380
7381static int
7382disp_size (unsigned int n)
7383{
7384 int size = 4;
43234a1e 7385
b5014f7a 7386 if (i.types[n].bitfield.disp64)
40fb9820
L		 7387 size = 8;
7388 else if (i.types[n].bitfield.disp8)
7389 size = 1;
7390 else if (i.types[n].bitfield.disp16)
7391 size = 2;
e205caa7
L		 7392 return size;
7393}
7394
7395/* Return the size of the immediate operand N. */
7396
7397static int
7398imm_size (unsigned int n)
7399{
7400 int size = 4;
40fb9820
L		 7401 if (i.types[n].bitfield.imm64)
7402 size = 8;
7403 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7404 size = 1;
7405 else if (i.types[n].bitfield.imm16)
7406 size = 2;
e205caa7
L		 7407 return size;
7408}
7409
29b0f896 7410static void
64e74474 7411output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7412{
7413 char *p;
7414 unsigned int n;
252b5132 7415
29b0f896
AM		 7416 for (n = 0; n < i.operands; n++)
7417 {
b5014f7a 7418 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 7419 {
7420 if (i.op[n].disps->X_op == O_constant)
7421 {
e205caa7 7422 int size = disp_size (n);
43234a1e 7423 offsetT val = i.op[n].disps->X_add_number;
252b5132 7424
b5014f7a 7425 val = offset_in_range (val >> i.memshift, size);
29b0f896
AM		 7426 p = frag_more (size);
7427 md_number_to_chars (p, val, size);
7428 }
7429 else
7430 {
f86103b7 7431 enum bfd_reloc_code_real reloc_type;
e205caa7 7432 int size = disp_size (n);
40fb9820 7433 int sign = i.types[n].bitfield.disp32s;
29b0f896 7434 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7435 fixS *fixP;
29b0f896 7436
e205caa7 7437 /* We can't have 8 bit displacement here. */
9c2799c2 7438 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7439
29b0f896
AM		 7440 /* The PC relative address is computed relative
7441 to the instruction boundary, so in case immediate
7442 fields follows, we need to adjust the value. */
7443 if (pcrel && i.imm_operands)
7444 {
29b0f896 7445 unsigned int n1;
e205caa7 7446 int sz = 0;
252b5132 7447
29b0f896 7448 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7449 if (operand_type_check (i.types[n1], imm))
252b5132 7450 {
e205caa7
L		 7451 /* Only one immediate is allowed for PC
7452 relative address. */
9c2799c2 7453 gas_assert (sz == 0);
e205caa7
L		 7454 sz = imm_size (n1);
7455 i.op[n].disps->X_add_number -= sz;
252b5132 7456 }
29b0f896 7457 /* We should find the immediate. */
9c2799c2 7458 gas_assert (sz != 0);
29b0f896 7459 }
520dc8e8 7460
29b0f896 7461 p = frag_more (size);
d258b828 7462 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7463 if (GOT_symbol
2bbd9c25 7464 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7465 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7466 || reloc_type == BFD_RELOC_X86_64_32S
7467 || (reloc_type == BFD_RELOC_64
7468 && object_64bit))
d6ab8113
JB		 7469 && (i.op[n].disps->X_op == O_symbol
7470 || (i.op[n].disps->X_op == O_add
7471 && ((symbol_get_value_expression
7472 (i.op[n].disps->X_op_symbol)->X_op)
7473 == O_subtract))))
7474 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7475 {
7476 offsetT add;
7477
7478 if (insn_start_frag == frag_now)
7479 add = (p - frag_now->fr_literal) - insn_start_off;
7480 else
7481 {
7482 fragS *fr;
7483
7484 add = insn_start_frag->fr_fix - insn_start_off;
7485 for (fr = insn_start_frag->fr_next;
7486 fr && fr != frag_now; fr = fr->fr_next)
7487 add += fr->fr_fix;
7488 add += p - frag_now->fr_literal;
7489 }
7490
4fa24527 7491 if (!object_64bit)
7b81dfbb
AJ		 7492 {
7493 reloc_type = BFD_RELOC_386_GOTPC;
7494 i.op[n].imms->X_add_number += add;
7495 }
7496 else if (reloc_type == BFD_RELOC_64)
7497 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7498 else
7b81dfbb
AJ		 7499 /* Don't do the adjustment for x86-64, as there
7500 the pcrel addressing is relative to the _next_
7501 insn, and that is taken care of in other code. */
d6ab8113 7502 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7503 }
02a86693
L		 7504 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7505 size, i.op[n].disps, pcrel,
7506 reloc_type);
7507 /* Check for "call/jmp *mem", "mov mem, %reg",
7508 "test %reg, mem" and "binop mem, %reg" where binop
7509 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7510 instructions. Always generate R_386_GOT32X for
7511 "sym*GOT" operand in 32-bit mode. */
7512 if ((generate_relax_relocations
7513 || (!object_64bit
7514 && i.rm.mode == 0
7515 && i.rm.regmem == 5))
7516 && (i.rm.mode == 2
7517 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7518 && ((i.operands == 1
7519 && i.tm.base_opcode == 0xff
7520 && (i.rm.reg == 2 || i.rm.reg == 4))
7521 || (i.operands == 2
7522 && (i.tm.base_opcode == 0x8b
7523 || i.tm.base_opcode == 0x85
7524 || (i.tm.base_opcode & 0xc7) == 0x03))))
7525 {
7526 if (object_64bit)
7527 {
7528 fixP->fx_tcbit = i.rex != 0;
7529 if (i.base_reg
7530 && (i.base_reg->reg_num == RegRip
7531 || i.base_reg->reg_num == RegEip))
7532 fixP->fx_tcbit2 = 1;
7533 }
7534 else
7535 fixP->fx_tcbit2 = 1;
7536 }
29b0f896
AM		 7537 }
7538 }
7539 }
7540}
252b5132 7541
29b0f896 7542static void
64e74474 7543output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7544{
7545 char *p;
7546 unsigned int n;
252b5132 7547
29b0f896
AM		 7548 for (n = 0; n < i.operands; n++)
7549 {
43234a1e
L		 7550 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7551 if (i.rounding && (int) n == i.rounding->operand)
7552 continue;
7553
40fb9820 7554 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7555 {
7556 if (i.op[n].imms->X_op == O_constant)
7557 {
e205caa7 7558 int size = imm_size (n);
29b0f896 7559 offsetT val;
b4cac588 7560
29b0f896
AM		 7561 val = offset_in_range (i.op[n].imms->X_add_number,
7562 size);
7563 p = frag_more (size);
7564 md_number_to_chars (p, val, size);
7565 }
7566 else
7567 {
7568 /* Not absolute_section.
7569 Need a 32-bit fixup (don't support 8bit
7570 non-absolute imms). Try to support other
7571 sizes ... */
f86103b7 7572 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7573 int size = imm_size (n);
7574 int sign;
29b0f896 7575
40fb9820 7576 if (i.types[n].bitfield.imm32s
a7d61044 7577 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7578 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7579 sign = 1;
e205caa7
L		 7580 else
7581 sign = 0;
520dc8e8 7582
29b0f896 7583 p = frag_more (size);
d258b828 7584 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7585
2bbd9c25
JJ		 7586 /* This is tough to explain. We end up with this one if we
7587 * have operands that look like
7588 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7589 * obtain the absolute address of the GOT, and it is strongly
7590 * preferable from a performance point of view to avoid using
7591 * a runtime relocation for this. The actual sequence of
7592 * instructions often look something like:
7593 *
7594 * call .L66
7595 * .L66:
7596 * popl %ebx
7597 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7598 *
7599 * The call and pop essentially return the absolute address
7600 * of the label .L66 and store it in %ebx. The linker itself
7601 * will ultimately change the first operand of the addl so
7602 * that %ebx points to the GOT, but to keep things simple, the
7603 * .o file must have this operand set so that it generates not
7604 * the absolute address of .L66, but the absolute address of
7605 * itself. This allows the linker itself simply treat a GOTPC
7606 * relocation as asking for a pcrel offset to the GOT to be
7607 * added in, and the addend of the relocation is stored in the
7608 * operand field for the instruction itself.
7609 *
7610 * Our job here is to fix the operand so that it would add
7611 * the correct offset so that %ebx would point to itself. The
7612 * thing that is tricky is that .-.L66 will point to the
7613 * beginning of the instruction, so we need to further modify
7614 * the operand so that it will point to itself. There are
7615 * other cases where you have something like:
7616 *
7617 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7618 *
7619 * and here no correction would be required. Internally in
7620 * the assembler we treat operands of this form as not being
7621 * pcrel since the '.' is explicitly mentioned, and I wonder
7622 * whether it would simplify matters to do it this way. Who
7623 * knows. In earlier versions of the PIC patches, the
7624 * pcrel_adjust field was used to store the correction, but
7625 * since the expression is not pcrel, I felt it would be
7626 * confusing to do it this way. */
7627
d6ab8113 7628 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7629 || reloc_type == BFD_RELOC_X86_64_32S
7630 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7631 && GOT_symbol
7632 && GOT_symbol == i.op[n].imms->X_add_symbol
7633 && (i.op[n].imms->X_op == O_symbol
7634 || (i.op[n].imms->X_op == O_add
7635 && ((symbol_get_value_expression
7636 (i.op[n].imms->X_op_symbol)->X_op)
7637 == O_subtract))))
7638 {
2bbd9c25
JJ		 7639 offsetT add;
7640
7641 if (insn_start_frag == frag_now)
7642 add = (p - frag_now->fr_literal) - insn_start_off;
7643 else
7644 {
7645 fragS *fr;
7646
7647 add = insn_start_frag->fr_fix - insn_start_off;
7648 for (fr = insn_start_frag->fr_next;
7649 fr && fr != frag_now; fr = fr->fr_next)
7650 add += fr->fr_fix;
7651 add += p - frag_now->fr_literal;
7652 }
7653
4fa24527 7654 if (!object_64bit)
d6ab8113 7655 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7656 else if (size == 4)
d6ab8113 7657 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7658 else if (size == 8)
7659 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7660 i.op[n].imms->X_add_number += add;
29b0f896 7661 }
29b0f896
AM		 7662 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7663 i.op[n].imms, 0, reloc_type);
7664 }
7665 }
7666 }
252b5132
RH		 7667}
7668\f
d182319b
JB		 7669/* x86_cons_fix_new is called via the expression parsing code when a
7670 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7671static int cons_sign = -1;
7672
7673void
e3bb37b5 7674x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7675 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7676{
d258b828 7677 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7678
7679#ifdef TE_PE
7680 if (exp->X_op == O_secrel)
7681 {
7682 exp->X_op = O_symbol;
7683 r = BFD_RELOC_32_SECREL;
7684 }
7685#endif
7686
7687 fix_new_exp (frag, off, len, exp, 0, r);
7688}
7689
357d1bd8
L		 7690/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7691 purpose of the `.dc.a' internal pseudo-op. */
7692
7693int
7694x86_address_bytes (void)
7695{
7696 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7697 return 4;
7698 return stdoutput->arch_info->bits_per_address / 8;
7699}
7700
d382c579
TG		 7701#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7702 || defined (LEX_AT)
d258b828 7703# define lex_got(reloc, adjust, types) NULL
718ddfc0 7704#else
f3c180ae
AM		 7705/* Parse operands of the form
7706 <symbol>@GOTOFF+<nnn>
7707 and similar .plt or .got references.
7708
7709 If we find one, set up the correct relocation in RELOC and copy the
7710 input string, minus the `@GOTOFF' into a malloc'd buffer for
7711 parsing by the calling routine. Return this buffer, and if ADJUST
7712 is non-null set it to the length of the string we removed from the
7713 input line. Otherwise return NULL. */
7714static char *
91d6fa6a 7715lex_got (enum bfd_reloc_code_real *rel,
64e74474 7716 int *adjust,
d258b828 7717 i386_operand_type *types)
f3c180ae 7718{
7b81dfbb
AJ		 7719 /* Some of the relocations depend on the size of what field is to
7720 be relocated. But in our callers i386_immediate and i386_displacement
7721 we don't yet know the operand size (this will be set by insn
7722 matching). Hence we record the word32 relocation here,
7723 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7724 static const struct {
7725 const char *str;
cff8d58a 7726 int len;
4fa24527 7727 const enum bfd_reloc_code_real rel[2];
40fb9820 7728 const i386_operand_type types64;
f3c180ae 7729 } gotrel[] = {
8ce3d284 7730#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7731 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7732 BFD_RELOC_SIZE32 },
7733 OPERAND_TYPE_IMM32_64 },
8ce3d284 7734#endif
cff8d58a
L		 7735 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7736 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7737 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7738 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7739 BFD_RELOC_X86_64_PLT32 },
40fb9820 7740 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7741 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7742 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7743 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7744 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7745 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7746 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7747 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7748 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7749 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7750 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7751 BFD_RELOC_X86_64_TLSGD },
40fb9820 7752 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7753 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7754 _dummy_first_bfd_reloc_code_real },
40fb9820 7755 OPERAND_TYPE_NONE },
cff8d58a
L		 7756 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7757 BFD_RELOC_X86_64_TLSLD },
40fb9820 7758 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7759 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7760 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7761 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7762 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7763 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7764 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7765 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7766 _dummy_first_bfd_reloc_code_real },
40fb9820 7767 OPERAND_TYPE_NONE },
cff8d58a
L		 7768 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7769 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7770 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7771 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7772 _dummy_first_bfd_reloc_code_real },
40fb9820 7773 OPERAND_TYPE_NONE },
cff8d58a
L		 7774 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7775 _dummy_first_bfd_reloc_code_real },
40fb9820 7776 OPERAND_TYPE_NONE },
cff8d58a
L		 7777 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7778 BFD_RELOC_X86_64_GOT32 },
40fb9820 7779 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7780 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7781 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7782 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7783 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7784 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7785 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7786 };
7787 char *cp;
7788 unsigned int j;
7789
d382c579 7790#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7791 if (!IS_ELF)
7792 return NULL;
d382c579 7793#endif
718ddfc0 7794
f3c180ae 7795 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7796 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7797 return NULL;
7798
47465058 7799 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7800 {
cff8d58a 7801 int len = gotrel[j].len;
28f81592 7802 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7803 {
4fa24527 7804 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7805 {
28f81592
AM		 7806 int first, second;
7807 char *tmpbuf, *past_reloc;
f3c180ae 7808
91d6fa6a 7809 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7810
3956db08
JB		 7811 if (types)
7812 {
7813 if (flag_code != CODE_64BIT)
40fb9820
L		 7814 {
7815 types->bitfield.imm32 = 1;
7816 types->bitfield.disp32 = 1;
7817 }
3956db08
JB		 7818 else
7819 *types = gotrel[j].types64;
7820 }
7821
8fd4256d 7822 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7823 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7824
28f81592 7825 /* The length of the first part of our input line. */
f3c180ae 7826 first = cp - input_line_pointer;
28f81592
AM		 7827
7828 /* The second part goes from after the reloc token until
67c11a9b 7829 (and including) an end_of_line char or comma. */
28f81592 7830 past_reloc = cp + 1 + len;
67c11a9b
AM		 7831 cp = past_reloc;
7832 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7833 ++cp;
7834 second = cp + 1 - past_reloc;
28f81592
AM		 7835
7836 /* Allocate and copy string. The trailing NUL shouldn't
7837 be necessary, but be safe. */
add39d23 7838 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7839 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7840 if (second != 0 && *past_reloc != ' ')
7841 /* Replace the relocation token with ' ', so that
7842 errors like foo@GOTOFF1 will be detected. */
7843 tmpbuf[first++] = ' ';
af89796a
L		 7844 else
7845 /* Increment length by 1 if the relocation token is
7846 removed. */
7847 len++;
7848 if (adjust)
7849 *adjust = len;
0787a12d
AM		 7850 memcpy (tmpbuf + first, past_reloc, second);
7851 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7852 return tmpbuf;
7853 }
7854
4fa24527
JB		 7855 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7856 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7857 return NULL;
7858 }
7859 }
7860
7861 /* Might be a symbol version string. Don't as_bad here. */
7862 return NULL;
7863}
4e4f7c87 7864#endif
f3c180ae 7865
a988325c
NC		 7866#ifdef TE_PE
7867#ifdef lex_got
7868#undef lex_got
7869#endif
7870/* Parse operands of the form
7871 <symbol>@SECREL32+<nnn>
7872
7873 If we find one, set up the correct relocation in RELOC and copy the
7874 input string, minus the `@SECREL32' into a malloc'd buffer for
7875 parsing by the calling routine. Return this buffer, and if ADJUST
7876 is non-null set it to the length of the string we removed from the
34bca508
L		 7877 input line. Otherwise return NULL.
7878
a988325c
NC		 7879 This function is copied from the ELF version above adjusted for PE targets. */
7880
7881static char *
7882lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7883 int *adjust ATTRIBUTE_UNUSED,
d258b828 7884 i386_operand_type *types)
a988325c
NC		 7885{
7886 static const struct
7887 {
7888 const char *str;
7889 int len;
7890 const enum bfd_reloc_code_real rel[2];
7891 const i386_operand_type types64;
7892 }
7893 gotrel[] =
7894 {
7895 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7896 BFD_RELOC_32_SECREL },
7897 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7898 };
7899
7900 char *cp;
7901 unsigned j;
7902
7903 for (cp = input_line_pointer; *cp != '@'; cp++)
7904 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7905 return NULL;
7906
7907 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7908 {
7909 int len = gotrel[j].len;
7910
7911 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7912 {
7913 if (gotrel[j].rel[object_64bit] != 0)
7914 {
7915 int first, second;
7916 char *tmpbuf, *past_reloc;
7917
7918 *rel = gotrel[j].rel[object_64bit];
7919 if (adjust)
7920 *adjust = len;
7921
7922 if (types)
7923 {
7924 if (flag_code != CODE_64BIT)
7925 {
7926 types->bitfield.imm32 = 1;
7927 types->bitfield.disp32 = 1;
7928 }
7929 else
7930 *types = gotrel[j].types64;
7931 }
7932
7933 /* The length of the first part of our input line. */
7934 first = cp - input_line_pointer;
7935
7936 /* The second part goes from after the reloc token until
7937 (and including) an end_of_line char or comma. */
7938 past_reloc = cp + 1 + len;
7939 cp = past_reloc;
7940 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7941 ++cp;
7942 second = cp + 1 - past_reloc;
7943
7944 /* Allocate and copy string. The trailing NUL shouldn't
7945 be necessary, but be safe. */
add39d23 7946 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7947 memcpy (tmpbuf, input_line_pointer, first);
7948 if (second != 0 && *past_reloc != ' ')
7949 /* Replace the relocation token with ' ', so that
7950 errors like foo@SECLREL321 will be detected. */
7951 tmpbuf[first++] = ' ';
7952 memcpy (tmpbuf + first, past_reloc, second);
7953 tmpbuf[first + second] = '\0';
7954 return tmpbuf;
7955 }
7956
7957 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7958 gotrel[j].str, 1 << (5 + object_64bit));
7959 return NULL;
7960 }
7961 }
7962
7963 /* Might be a symbol version string. Don't as_bad here. */
7964 return NULL;
7965}
7966
7967#endif /* TE_PE */
7968
62ebcb5c 7969bfd_reloc_code_real_type
e3bb37b5 7970x86_cons (expressionS *exp, int size)
f3c180ae 7971{
62ebcb5c
AM		 7972 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7973
ee86248c
JB		 7974 intel_syntax = -intel_syntax;
7975
3c7b9c2c 7976 exp->X_md = 0;
4fa24527 7977 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7978 {
7979 /* Handle @GOTOFF and the like in an expression. */
7980 char *save;
7981 char *gotfree_input_line;
4a57f2cf 7982 int adjust = 0;
f3c180ae
AM		 7983
7984 save = input_line_pointer;
d258b828 7985 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7986 if (gotfree_input_line)
7987 input_line_pointer = gotfree_input_line;
7988
7989 expression (exp);
7990
7991 if (gotfree_input_line)
7992 {
7993 /* expression () has merrily parsed up to the end of line,
7994 or a comma - in the wrong buffer. Transfer how far
7995 input_line_pointer has moved to the right buffer. */
7996 input_line_pointer = (save
7997 + (input_line_pointer - gotfree_input_line)
7998 + adjust);
7999 free (gotfree_input_line);
3992d3b7
AM		 8000 if (exp->X_op == O_constant
8001 || exp->X_op == O_absent
8002 || exp->X_op == O_illegal
0398aac5 8003 || exp->X_op == O_register
3992d3b7
AM		 8004 || exp->X_op == O_big)
8005 {
8006 char c = *input_line_pointer;
8007 *input_line_pointer = 0;
8008 as_bad (_("missing or invalid expression `%s'"), save);
8009 *input_line_pointer = c;
8010 }
f3c180ae
AM		 8011 }
8012 }
8013 else
8014 expression (exp);
ee86248c
JB		 8015
8016 intel_syntax = -intel_syntax;
8017
8018 if (intel_syntax)
8019 i386_intel_simplify (exp);
62ebcb5c
AM		 8020
8021 return got_reloc;
f3c180ae 8022}
f3c180ae 8023
9f32dd5b
L		 8024static void
8025signed_cons (int size)
6482c264 8026{
d182319b
JB		 8027 if (flag_code == CODE_64BIT)
8028 cons_sign = 1;
8029 cons (size);
8030 cons_sign = -1;
6482c264
NC		 8031}
8032
d182319b 8033#ifdef TE_PE
6482c264 8034static void
7016a5d5 8035pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8036{
8037 expressionS exp;
8038
8039 do
8040 {
8041 expression (&exp);
8042 if (exp.X_op == O_symbol)
8043 exp.X_op = O_secrel;
8044
8045 emit_expr (&exp, 4);
8046 }
8047 while (*input_line_pointer++ == ',');
8048
8049 input_line_pointer--;
8050 demand_empty_rest_of_line ();
8051}
6482c264
NC		 8052#endif
8053
43234a1e
L		 8054/* Handle Vector operations. */
8055
8056static char *
8057check_VecOperations (char *op_string, char *op_end)
8058{
8059 const reg_entry *mask;
8060 const char *saved;
8061 char *end_op;
8062
8063 while (*op_string
8064 && (op_end == NULL || op_string < op_end))
8065 {
8066 saved = op_string;
8067 if (*op_string == '{')
8068 {
8069 op_string++;
8070
8071 /* Check broadcasts. */
8072 if (strncmp (op_string, "1to", 3) == 0)
8073 {
8074 int bcst_type;
8075
8076 if (i.broadcast)
8077 goto duplicated_vec_op;
8078
8079 op_string += 3;
8080 if (*op_string == '8')
8081 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 8082 else if (*op_string == '4')
8083 bcst_type = BROADCAST_1TO4;
8084 else if (*op_string == '2')
8085 bcst_type = BROADCAST_1TO2;
43234a1e
L		 8086 else if (*op_string == '1'
8087 && *(op_string+1) == '6')
8088 {
8089 bcst_type = BROADCAST_1TO16;
8090 op_string++;
8091 }
8092 else
8093 {
8094 as_bad (_("Unsupported broadcast: `%s'"), saved);
8095 return NULL;
8096 }
8097 op_string++;
8098
8099 broadcast_op.type = bcst_type;
8100 broadcast_op.operand = this_operand;
8101 i.broadcast = &broadcast_op;
8102 }
8103 /* Check masking operation. */
8104 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8105 {
8106 /* k0 can't be used for write mask. */
6d2cd6b2 8107 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 8108 {
6d2cd6b2
JB		 8109 as_bad (_("`%s%s' can't be used for write mask"),
8110 register_prefix, mask->reg_name);
43234a1e
L		 8111 return NULL;
8112 }
8113
8114 if (!i.mask)
8115 {
8116 mask_op.mask = mask;
8117 mask_op.zeroing = 0;
8118 mask_op.operand = this_operand;
8119 i.mask = &mask_op;
8120 }
8121 else
8122 {
8123 if (i.mask->mask)
8124 goto duplicated_vec_op;
8125
8126 i.mask->mask = mask;
8127
8128 /* Only "{z}" is allowed here. No need to check
8129 zeroing mask explicitly. */
8130 if (i.mask->operand != this_operand)
8131 {
8132 as_bad (_("invalid write mask `%s'"), saved);
8133 return NULL;
8134 }
8135 }
8136
8137 op_string = end_op;
8138 }
8139 /* Check zeroing-flag for masking operation. */
8140 else if (*op_string == 'z')
8141 {
8142 if (!i.mask)
8143 {
8144 mask_op.mask = NULL;
8145 mask_op.zeroing = 1;
8146 mask_op.operand = this_operand;
8147 i.mask = &mask_op;
8148 }
8149 else
8150 {
8151 if (i.mask->zeroing)
8152 {
8153 duplicated_vec_op:
8154 as_bad (_("duplicated `%s'"), saved);
8155 return NULL;
8156 }
8157
8158 i.mask->zeroing = 1;
8159
8160 /* Only "{%k}" is allowed here. No need to check mask
8161 register explicitly. */
8162 if (i.mask->operand != this_operand)
8163 {
8164 as_bad (_("invalid zeroing-masking `%s'"),
8165 saved);
8166 return NULL;
8167 }
8168 }
8169
8170 op_string++;
8171 }
8172 else
8173 goto unknown_vec_op;
8174
8175 if (*op_string != '}')
8176 {
8177 as_bad (_("missing `}' in `%s'"), saved);
8178 return NULL;
8179 }
8180 op_string++;
8181 continue;
8182 }
8183 unknown_vec_op:
8184 /* We don't know this one. */
8185 as_bad (_("unknown vector operation: `%s'"), saved);
8186 return NULL;
8187 }
8188
6d2cd6b2
JB		 8189 if (i.mask && i.mask->zeroing && !i.mask->mask)
8190 {
8191 as_bad (_("zeroing-masking only allowed with write mask"));
8192 return NULL;
8193 }
8194
43234a1e
L		 8195 return op_string;
8196}
8197
252b5132 8198static int
70e41ade 8199i386_immediate (char *imm_start)
252b5132
RH		 8200{
8201 char *save_input_line_pointer;
f3c180ae 8202 char *gotfree_input_line;
252b5132 8203 segT exp_seg = 0;
47926f60 8204 expressionS *exp;
40fb9820
L		 8205 i386_operand_type types;
8206
0dfbf9d7 8207 operand_type_set (&types, ~0);
252b5132
RH		 8208
8209 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8210 {
31b2323c
L		 8211 as_bad (_("at most %d immediate operands are allowed"),
8212 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8213 return 0;
8214 }
8215
8216 exp = &im_expressions[i.imm_operands++];
520dc8e8 8217 i.op[this_operand].imms = exp;
252b5132
RH		 8218
8219 if (is_space_char (*imm_start))
8220 ++imm_start;
8221
8222 save_input_line_pointer = input_line_pointer;
8223 input_line_pointer = imm_start;
8224
d258b828 8225 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8226 if (gotfree_input_line)
8227 input_line_pointer = gotfree_input_line;
252b5132
RH		 8228
8229 exp_seg = expression (exp);
8230
83183c0c 8231 SKIP_WHITESPACE ();
43234a1e
L		 8232
8233 /* Handle vector operations. */
8234 if (*input_line_pointer == '{')
8235 {
8236 input_line_pointer = check_VecOperations (input_line_pointer,
8237 NULL);
8238 if (input_line_pointer == NULL)
8239 return 0;
8240 }
8241
252b5132 8242 if (*input_line_pointer)
f3c180ae 8243 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8244
8245 input_line_pointer = save_input_line_pointer;
f3c180ae 8246 if (gotfree_input_line)
ee86248c
JB		 8247 {
8248 free (gotfree_input_line);
8249
8250 if (exp->X_op == O_constant || exp->X_op == O_register)
8251 exp->X_op = O_illegal;
8252 }
8253
8254 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8255}
252b5132 8256
ee86248c
JB		 8257static int
8258i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8259 i386_operand_type types, const char *imm_start)
8260{
8261 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8262 {
313c53d1
L		 8263 if (imm_start)
8264 as_bad (_("missing or invalid immediate expression `%s'"),
8265 imm_start);
3992d3b7 8266 return 0;
252b5132 8267 }
3e73aa7c 8268 else if (exp->X_op == O_constant)
252b5132 8269 {
47926f60 8270 /* Size it properly later. */
40fb9820 8271 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8272 /* If not 64bit, sign extend val. */
8273 if (flag_code != CODE_64BIT
4eed87de
AM		 8274 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8275 exp->X_add_number
8276 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8277 }
4c63da97 8278#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8279 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8280 && exp_seg != absolute_section
47926f60 8281 && exp_seg != text_section
24eab124
AM		 8282 && exp_seg != data_section
8283 && exp_seg != bss_section
8284 && exp_seg != undefined_section
f86103b7 8285 && !bfd_is_com_section (exp_seg))
252b5132 8286 {
d0b47220 8287 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8288 return 0;
8289 }
8290#endif
a841bdf5 8291 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8292 {
313c53d1
L		 8293 if (imm_start)
8294 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8295 return 0;
8296 }
252b5132
RH		 8297 else
8298 {
8299 /* This is an address. The size of the address will be
24eab124 8300 determined later, depending on destination register,
3e73aa7c 8301 suffix, or the default for the section. */
40fb9820
L		 8302 i.types[this_operand].bitfield.imm8 = 1;
8303 i.types[this_operand].bitfield.imm16 = 1;
8304 i.types[this_operand].bitfield.imm32 = 1;
8305 i.types[this_operand].bitfield.imm32s = 1;
8306 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8307 i.types[this_operand] = operand_type_and (i.types[this_operand],
8308 types);
252b5132
RH		 8309 }
8310
8311 return 1;
8312}
8313
551c1ca1 8314static char *
e3bb37b5 8315i386_scale (char *scale)
252b5132 8316{
551c1ca1
AM		 8317 offsetT val;
8318 char *save = input_line_pointer;
252b5132 8319
551c1ca1
AM		 8320 input_line_pointer = scale;
8321 val = get_absolute_expression ();
8322
8323 switch (val)
252b5132 8324 {
551c1ca1 8325 case 1:
252b5132
RH		 8326 i.log2_scale_factor = 0;
8327 break;
551c1ca1 8328 case 2:
252b5132
RH		 8329 i.log2_scale_factor = 1;
8330 break;
551c1ca1 8331 case 4:
252b5132
RH		 8332 i.log2_scale_factor = 2;
8333 break;
551c1ca1 8334 case 8:
252b5132
RH		 8335 i.log2_scale_factor = 3;
8336 break;
8337 default:
a724f0f4
JB		 8338 {
8339 char sep = *input_line_pointer;
8340
8341 *input_line_pointer = '\0';
8342 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8343 scale);
8344 *input_line_pointer = sep;
8345 input_line_pointer = save;
8346 return NULL;
8347 }
252b5132 8348 }
29b0f896 8349 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8350 {
8351 as_warn (_("scale factor of %d without an index register"),
24eab124 8352 1 << i.log2_scale_factor);
252b5132 8353 i.log2_scale_factor = 0;
252b5132 8354 }
551c1ca1
AM		 8355 scale = input_line_pointer;
8356 input_line_pointer = save;
8357 return scale;
252b5132
RH		 8358}
8359
252b5132 8360static int
e3bb37b5 8361i386_displacement (char *disp_start, char *disp_end)
252b5132 8362{
29b0f896 8363 expressionS *exp;
252b5132
RH		 8364 segT exp_seg = 0;
8365 char *save_input_line_pointer;
f3c180ae 8366 char *gotfree_input_line;
40fb9820
L		 8367 int override;
8368 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8369 int ret;
252b5132 8370
31b2323c
L		 8371 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8372 {
8373 as_bad (_("at most %d displacement operands are allowed"),
8374 MAX_MEMORY_OPERANDS);
8375 return 0;
8376 }
8377
0dfbf9d7 8378 operand_type_set (&bigdisp, 0);
40fb9820
L		 8379 if ((i.types[this_operand].bitfield.jumpabsolute)
8380 || (!current_templates->start->opcode_modifier.jump
8381 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8382 {
40fb9820 8383 bigdisp.bitfield.disp32 = 1;
e05278af 8384 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8385 if (flag_code == CODE_64BIT)
8386 {
8387 if (!override)
8388 {
8389 bigdisp.bitfield.disp32s = 1;
8390 bigdisp.bitfield.disp64 = 1;
8391 }
8392 }
8393 else if ((flag_code == CODE_16BIT) ^ override)
8394 {
8395 bigdisp.bitfield.disp32 = 0;
8396 bigdisp.bitfield.disp16 = 1;
8397 }
e05278af
JB		 8398 }
8399 else
8400 {
8401 /* For PC-relative branches, the width of the displacement
8402 is dependent upon data size, not address size. */
e05278af 8403 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8404 if (flag_code == CODE_64BIT)
8405 {
8406 if (override || i.suffix == WORD_MNEM_SUFFIX)
8407 bigdisp.bitfield.disp16 = 1;
8408 else
8409 {
8410 bigdisp.bitfield.disp32 = 1;
8411 bigdisp.bitfield.disp32s = 1;
8412 }
8413 }
8414 else
e05278af
JB		 8415 {
8416 if (!override)
8417 override = (i.suffix == (flag_code != CODE_16BIT
8418 ? WORD_MNEM_SUFFIX
8419 : LONG_MNEM_SUFFIX));
40fb9820
L		 8420 bigdisp.bitfield.disp32 = 1;
8421 if ((flag_code == CODE_16BIT) ^ override)
8422 {
8423 bigdisp.bitfield.disp32 = 0;
8424 bigdisp.bitfield.disp16 = 1;
8425 }
e05278af 8426 }
e05278af 8427 }
c6fb90c8
L		 8428 i.types[this_operand] = operand_type_or (i.types[this_operand],
8429 bigdisp);
252b5132
RH		 8430
8431 exp = &disp_expressions[i.disp_operands];
520dc8e8 8432 i.op[this_operand].disps = exp;
252b5132
RH		 8433 i.disp_operands++;
8434 save_input_line_pointer = input_line_pointer;
8435 input_line_pointer = disp_start;
8436 END_STRING_AND_SAVE (disp_end);
8437
8438#ifndef GCC_ASM_O_HACK
8439#define GCC_ASM_O_HACK 0
8440#endif
8441#if GCC_ASM_O_HACK
8442 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8443 if (i.types[this_operand].bitfield.baseIndex
24eab124 8444 && displacement_string_end[-1] == '+')
252b5132
RH		 8445 {
8446 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8447 constraint within gcc asm statements.
8448 For instance:
8449
8450 #define _set_tssldt_desc(n,addr,limit,type) \
8451 __asm__ __volatile__ ( \
8452 "movw %w2,%0\n\t" \
8453 "movw %w1,2+%0\n\t" \
8454 "rorl $16,%1\n\t" \
8455 "movb %b1,4+%0\n\t" \
8456 "movb %4,5+%0\n\t" \
8457 "movb $0,6+%0\n\t" \
8458 "movb %h1,7+%0\n\t" \
8459 "rorl $16,%1" \
8460 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8461
8462 This works great except that the output assembler ends
8463 up looking a bit weird if it turns out that there is
8464 no offset. You end up producing code that looks like:
8465
8466 #APP
8467 movw $235,(%eax)
8468 movw %dx,2+(%eax)
8469 rorl $16,%edx
8470 movb %dl,4+(%eax)
8471 movb $137,5+(%eax)
8472 movb $0,6+(%eax)
8473 movb %dh,7+(%eax)
8474 rorl $16,%edx
8475 #NO_APP
8476
47926f60 8477 So here we provide the missing zero. */
24eab124
AM		 8478
8479 *displacement_string_end = '0';
252b5132
RH		 8480 }
8481#endif
d258b828 8482 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8483 if (gotfree_input_line)
8484 input_line_pointer = gotfree_input_line;
252b5132 8485
24eab124 8486 exp_seg = expression (exp);
252b5132 8487
636c26b0
AM		 8488 SKIP_WHITESPACE ();
8489 if (*input_line_pointer)
8490 as_bad (_("junk `%s' after expression"), input_line_pointer);
8491#if GCC_ASM_O_HACK
8492 RESTORE_END_STRING (disp_end + 1);
8493#endif
636c26b0 8494 input_line_pointer = save_input_line_pointer;
636c26b0 8495 if (gotfree_input_line)
ee86248c
JB		 8496 {
8497 free (gotfree_input_line);
8498
8499 if (exp->X_op == O_constant || exp->X_op == O_register)
8500 exp->X_op = O_illegal;
8501 }
8502
8503 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8504
8505 RESTORE_END_STRING (disp_end);
8506
8507 return ret;
8508}
8509
8510static int
8511i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8512 i386_operand_type types, const char *disp_start)
8513{
8514 i386_operand_type bigdisp;
8515 int ret = 1;
636c26b0 8516
24eab124
AM		 8517 /* We do this to make sure that the section symbol is in
8518 the symbol table. We will ultimately change the relocation
47926f60 8519 to be relative to the beginning of the section. */
1ae12ab7 8520 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8521 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8522 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8523 {
636c26b0 8524 if (exp->X_op != O_symbol)
3992d3b7 8525 goto inv_disp;
636c26b0 8526
e5cb08ac 8527 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8528 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8529 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8530 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8531 exp->X_op = O_subtract;
8532 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8533 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8534 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8535 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8536 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8537 else
29b0f896 8538 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8539 }
252b5132 8540
3992d3b7
AM		 8541 else if (exp->X_op == O_absent
8542 || exp->X_op == O_illegal
ee86248c 8543 || exp->X_op == O_big)
2daf4fd8 8544 {
3992d3b7
AM		 8545 inv_disp:
8546 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8547 disp_start);
3992d3b7 8548 ret = 0;
2daf4fd8
AM		 8549 }
8550
0e1147d9
L		 8551 else if (flag_code == CODE_64BIT
8552 && !i.prefix[ADDR_PREFIX]
8553 && exp->X_op == O_constant)
8554 {
8555 /* Since displacement is signed extended to 64bit, don't allow
8556 disp32 and turn off disp32s if they are out of range. */
8557 i.types[this_operand].bitfield.disp32 = 0;
8558 if (!fits_in_signed_long (exp->X_add_number))
8559 {
8560 i.types[this_operand].bitfield.disp32s = 0;
8561 if (i.types[this_operand].bitfield.baseindex)
8562 {
8563 as_bad (_("0x%lx out range of signed 32bit displacement"),
8564 (long) exp->X_add_number);
8565 ret = 0;
8566 }
8567 }
8568 }
8569
4c63da97 8570#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8571 else if (exp->X_op != O_constant
8572 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8573 && exp_seg != absolute_section
8574 && exp_seg != text_section
8575 && exp_seg != data_section
8576 && exp_seg != bss_section
8577 && exp_seg != undefined_section
8578 && !bfd_is_com_section (exp_seg))
24eab124 8579 {
d0b47220 8580 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8581 ret = 0;
24eab124 8582 }
252b5132 8583#endif
3956db08 8584
40fb9820
L		 8585 /* Check if this is a displacement only operand. */
8586 bigdisp = i.types[this_operand];
8587 bigdisp.bitfield.disp8 = 0;
8588 bigdisp.bitfield.disp16 = 0;
8589 bigdisp.bitfield.disp32 = 0;
8590 bigdisp.bitfield.disp32s = 0;
8591 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8592 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8593 i.types[this_operand] = operand_type_and (i.types[this_operand],
8594 types);
3956db08 8595
3992d3b7 8596 return ret;
252b5132
RH		 8597}
8598
2abc2bec
JB		 8599/* Return the active addressing mode, taking address override and
8600 registers forming the address into consideration. Update the
8601 address override prefix if necessary. */
47926f60 8602
2abc2bec
JB		 8603static enum flag_code
8604i386_addressing_mode (void)
252b5132 8605{
be05d201
L		 8606 enum flag_code addr_mode;
8607
8608 if (i.prefix[ADDR_PREFIX])
8609 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8610 else
8611 {
8612 addr_mode = flag_code;
8613
24eab124 8614#if INFER_ADDR_PREFIX
be05d201
L		 8615 if (i.mem_operands == 0)
8616 {
8617 /* Infer address prefix from the first memory operand. */
8618 const reg_entry *addr_reg = i.base_reg;
8619
8620 if (addr_reg == NULL)
8621 addr_reg = i.index_reg;
eecb386c 8622
be05d201
L		 8623 if (addr_reg)
8624 {
8625 if (addr_reg->reg_num == RegEip
8626 || addr_reg->reg_num == RegEiz
dc821c5f 8627 || addr_reg->reg_type.bitfield.dword)
be05d201
L		 8628 addr_mode = CODE_32BIT;
8629 else if (flag_code != CODE_64BIT
dc821c5f 8630 && addr_reg->reg_type.bitfield.word)
be05d201
L		 8631 addr_mode = CODE_16BIT;
8632
8633 if (addr_mode != flag_code)
8634 {
8635 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8636 i.prefixes += 1;
8637 /* Change the size of any displacement too. At most one
8638 of Disp16 or Disp32 is set.
8639 FIXME. There doesn't seem to be any real need for
8640 separate Disp16 and Disp32 flags. The same goes for
8641 Imm16 and Imm32. Removing them would probably clean
8642 up the code quite a lot. */
8643 if (flag_code != CODE_64BIT
8644 && (i.types[this_operand].bitfield.disp16
8645 || i.types[this_operand].bitfield.disp32))
8646 i.types[this_operand]
8647 = operand_type_xor (i.types[this_operand], disp16_32);
8648 }
8649 }
8650 }
24eab124 8651#endif
be05d201
L		 8652 }
8653
2abc2bec
JB		 8654 return addr_mode;
8655}
8656
8657/* Make sure the memory operand we've been dealt is valid.
8658 Return 1 on success, 0 on a failure. */
8659
8660static int
8661i386_index_check (const char *operand_string)
8662{
8663 const char *kind = "base/index";
8664 enum flag_code addr_mode = i386_addressing_mode ();
8665
fc0763e6
JB		 8666 if (current_templates->start->opcode_modifier.isstring
8667 && !current_templates->start->opcode_modifier.immext
8668 && (current_templates->end[-1].opcode_modifier.isstring
8669 || i.mem_operands))
8670 {
8671 /* Memory operands of string insns are special in that they only allow
8672 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8673 const reg_entry *expected_reg;
8674 static const char *di_si[][2] =
8675 {
8676 { "esi", "edi" },
8677 { "si", "di" },
8678 { "rsi", "rdi" }
8679 };
8680 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8681
8682 kind = "string address";
8683
8325cc63 8684 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 8685 {
8686 i386_operand_type type = current_templates->end[-1].operand_types[0];
8687
8688 if (!type.bitfield.baseindex
8689 || ((!i.mem_operands != !intel_syntax)
8690 && current_templates->end[-1].operand_types[1]
8691 .bitfield.baseindex))
8692 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8693 expected_reg = hash_find (reg_hash,
8694 di_si[addr_mode][type.bitfield.esseg]);
8695
fc0763e6
JB		 8696 }
8697 else
be05d201 8698 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8699
be05d201
L		 8700 if (i.base_reg != expected_reg
8701 || i.index_reg
fc0763e6 8702 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8703 {
be05d201
L		 8704 /* The second memory operand must have the same size as
8705 the first one. */
8706 if (i.mem_operands
8707 && i.base_reg
8708 && !((addr_mode == CODE_64BIT
dc821c5f 8709 && i.base_reg->reg_type.bitfield.qword)
be05d201 8710 || (addr_mode == CODE_32BIT
dc821c5f
JB		 8711 ? i.base_reg->reg_type.bitfield.dword
8712 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 8713 goto bad_address;
8714
fc0763e6
JB		 8715 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8716 operand_string,
8717 intel_syntax ? '[' : '(',
8718 register_prefix,
be05d201 8719 expected_reg->reg_name,
fc0763e6 8720 intel_syntax ? ']' : ')');
be05d201 8721 return 1;
fc0763e6 8722 }
be05d201
L		 8723 else
8724 return 1;
8725
8726bad_address:
8727 as_bad (_("`%s' is not a valid %s expression"),
8728 operand_string, kind);
8729 return 0;
3e73aa7c
JH		 8730 }
8731 else
8732 {
be05d201
L		 8733 if (addr_mode != CODE_16BIT)
8734 {
8735 /* 32-bit/64-bit checks. */
8736 if ((i.base_reg
8737 && (addr_mode == CODE_64BIT
dc821c5f
JB		 8738 ? !i.base_reg->reg_type.bitfield.qword
8739 : !i.base_reg->reg_type.bitfield.dword)
be05d201
L		 8740 && (i.index_reg
8741 || (i.base_reg->reg_num
8742 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8743 || (i.index_reg
1b54b8d7
JB		 8744 && !i.index_reg->reg_type.bitfield.xmmword
8745 && !i.index_reg->reg_type.bitfield.ymmword
8746 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 8747 && ((addr_mode == CODE_64BIT
dc821c5f 8748 ? !(i.index_reg->reg_type.bitfield.qword
be05d201 8749 || i.index_reg->reg_num == RegRiz)
dc821c5f 8750 : !(i.index_reg->reg_type.bitfield.dword
be05d201
L		 8751 || i.index_reg->reg_num == RegEiz))
8752 || !i.index_reg->reg_type.bitfield.baseindex)))
8753 goto bad_address;
8178be5b
JB		 8754
8755 /* bndmk, bndldx, and bndstx have special restrictions. */
8756 if (current_templates->start->base_opcode == 0xf30f1b
8757 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8758 {
8759 /* They cannot use RIP-relative addressing. */
8760 if (i.base_reg && i.base_reg->reg_num == RegRip)
8761 {
8762 as_bad (_("`%s' cannot be used here"), operand_string);
8763 return 0;
8764 }
8765
8766 /* bndldx and bndstx ignore their scale factor. */
8767 if (current_templates->start->base_opcode != 0xf30f1b
8768 && i.log2_scale_factor)
8769 as_warn (_("register scaling is being ignored here"));
8770 }
be05d201
L		 8771 }
8772 else
3e73aa7c 8773 {
be05d201 8774 /* 16-bit checks. */
3e73aa7c 8775 if ((i.base_reg
dc821c5f 8776 && (!i.base_reg->reg_type.bitfield.word
40fb9820 8777 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8778 || (i.index_reg
dc821c5f 8779 && (!i.index_reg->reg_type.bitfield.word
40fb9820 8780 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8781 || !(i.base_reg
8782 && i.base_reg->reg_num < 6
8783 && i.index_reg->reg_num >= 6
8784 && i.log2_scale_factor == 0))))
be05d201 8785 goto bad_address;
3e73aa7c
JH		 8786 }
8787 }
be05d201 8788 return 1;
24eab124 8789}
252b5132 8790
43234a1e
L		 8791/* Handle vector immediates. */
8792
8793static int
8794RC_SAE_immediate (const char *imm_start)
8795{
8796 unsigned int match_found, j;
8797 const char *pstr = imm_start;
8798 expressionS *exp;
8799
8800 if (*pstr != '{')
8801 return 0;
8802
8803 pstr++;
8804 match_found = 0;
8805 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8806 {
8807 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8808 {
8809 if (!i.rounding)
8810 {
8811 rc_op.type = RC_NamesTable[j].type;
8812 rc_op.operand = this_operand;
8813 i.rounding = &rc_op;
8814 }
8815 else
8816 {
8817 as_bad (_("duplicated `%s'"), imm_start);
8818 return 0;
8819 }
8820 pstr += RC_NamesTable[j].len;
8821 match_found = 1;
8822 break;
8823 }
8824 }
8825 if (!match_found)
8826 return 0;
8827
8828 if (*pstr++ != '}')
8829 {
8830 as_bad (_("Missing '}': '%s'"), imm_start);
8831 return 0;
8832 }
8833 /* RC/SAE immediate string should contain nothing more. */;
8834 if (*pstr != 0)
8835 {
8836 as_bad (_("Junk after '}': '%s'"), imm_start);
8837 return 0;
8838 }
8839
8840 exp = &im_expressions[i.imm_operands++];
8841 i.op[this_operand].imms = exp;
8842
8843 exp->X_op = O_constant;
8844 exp->X_add_number = 0;
8845 exp->X_add_symbol = (symbolS *) 0;
8846 exp->X_op_symbol = (symbolS *) 0;
8847
8848 i.types[this_operand].bitfield.imm8 = 1;
8849 return 1;
8850}
8851
8325cc63
JB		 8852/* Only string instructions can have a second memory operand, so
8853 reduce current_templates to just those if it contains any. */
8854static int
8855maybe_adjust_templates (void)
8856{
8857 const insn_template *t;
8858
8859 gas_assert (i.mem_operands == 1);
8860
8861 for (t = current_templates->start; t < current_templates->end; ++t)
8862 if (t->opcode_modifier.isstring)
8863 break;
8864
8865 if (t < current_templates->end)
8866 {
8867 static templates aux_templates;
8868 bfd_boolean recheck;
8869
8870 aux_templates.start = t;
8871 for (; t < current_templates->end; ++t)
8872 if (!t->opcode_modifier.isstring)
8873 break;
8874 aux_templates.end = t;
8875
8876 /* Determine whether to re-check the first memory operand. */
8877 recheck = (aux_templates.start != current_templates->start
8878 || t != current_templates->end);
8879
8880 current_templates = &aux_templates;
8881
8882 if (recheck)
8883 {
8884 i.mem_operands = 0;
8885 if (i.memop1_string != NULL
8886 && i386_index_check (i.memop1_string) == 0)
8887 return 0;
8888 i.mem_operands = 1;
8889 }
8890 }
8891
8892 return 1;
8893}
8894
fc0763e6 8895/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8896 on error. */
252b5132 8897
252b5132 8898static int
a7619375 8899i386_att_operand (char *operand_string)
252b5132 8900{
af6bdddf
AM		 8901 const reg_entry *r;
8902 char *end_op;
24eab124 8903 char *op_string = operand_string;
252b5132 8904
24eab124 8905 if (is_space_char (*op_string))
252b5132
RH		 8906 ++op_string;
8907
24eab124 8908 /* We check for an absolute prefix (differentiating,
47926f60 8909 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8910 if (*op_string == ABSOLUTE_PREFIX)
8911 {
8912 ++op_string;
8913 if (is_space_char (*op_string))
8914 ++op_string;
40fb9820 8915 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8916 }
252b5132 8917
47926f60 8918 /* Check if operand is a register. */
4d1bb795 8919 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8920 {
40fb9820
L		 8921 i386_operand_type temp;
8922
24eab124
AM		 8923 /* Check for a segment override by searching for ':' after a
8924 segment register. */
8925 op_string = end_op;
8926 if (is_space_char (*op_string))
8927 ++op_string;
40fb9820
L		 8928 if (*op_string == ':'
8929 && (r->reg_type.bitfield.sreg2
8930 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8931 {
8932 switch (r->reg_num)
8933 {
8934 case 0:
8935 i.seg[i.mem_operands] = &es;
8936 break;
8937 case 1:
8938 i.seg[i.mem_operands] = &cs;
8939 break;
8940 case 2:
8941 i.seg[i.mem_operands] = &ss;
8942 break;
8943 case 3:
8944 i.seg[i.mem_operands] = &ds;
8945 break;
8946 case 4:
8947 i.seg[i.mem_operands] = &fs;
8948 break;
8949 case 5:
8950 i.seg[i.mem_operands] = &gs;
8951 break;
8952 }
252b5132 8953
24eab124 8954 /* Skip the ':' and whitespace. */
252b5132
RH		 8955 ++op_string;
8956 if (is_space_char (*op_string))
24eab124 8957 ++op_string;
252b5132 8958
24eab124
AM		 8959 if (!is_digit_char (*op_string)
8960 && !is_identifier_char (*op_string)
8961 && *op_string != '('
8962 && *op_string != ABSOLUTE_PREFIX)
8963 {
8964 as_bad (_("bad memory operand `%s'"), op_string);
8965 return 0;
8966 }
47926f60 8967 /* Handle case of %es:*foo. */
24eab124
AM		 8968 if (*op_string == ABSOLUTE_PREFIX)
8969 {
8970 ++op_string;
8971 if (is_space_char (*op_string))
8972 ++op_string;
40fb9820 8973 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8974 }
8975 goto do_memory_reference;
8976 }
43234a1e
L		 8977
8978 /* Handle vector operations. */
8979 if (*op_string == '{')
8980 {
8981 op_string = check_VecOperations (op_string, NULL);
8982 if (op_string == NULL)
8983 return 0;
8984 }
8985
24eab124
AM		 8986 if (*op_string)
8987 {
d0b47220 8988 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8989 return 0;
8990 }
40fb9820
L		 8991 temp = r->reg_type;
8992 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8993 i.types[this_operand] = operand_type_or (i.types[this_operand],
8994 temp);
7d5e4556 8995 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8996 i.op[this_operand].regs = r;
24eab124
AM		 8997 i.reg_operands++;
8998 }
af6bdddf
AM		 8999 else if (*op_string == REGISTER_PREFIX)
9000 {
9001 as_bad (_("bad register name `%s'"), op_string);
9002 return 0;
9003 }
24eab124 9004 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9005 {
24eab124 9006 ++op_string;
40fb9820 9007 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9008 {
d0b47220 9009 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9010 return 0;
9011 }
9012 if (!i386_immediate (op_string))
9013 return 0;
9014 }
43234a1e
L		 9015 else if (RC_SAE_immediate (operand_string))
9016 {
9017 /* If it is a RC or SAE immediate, do nothing. */
9018 ;
9019 }
24eab124
AM		 9020 else if (is_digit_char (*op_string)
9021 || is_identifier_char (*op_string)
d02603dc 9022 || *op_string == '"'
e5cb08ac 9023 || *op_string == '(')
24eab124 9024 {
47926f60 9025 /* This is a memory reference of some sort. */
af6bdddf 9026 char *base_string;
252b5132 9027
47926f60 9028 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9029 char *displacement_string_start;
9030 char *displacement_string_end;
43234a1e 9031 char *vop_start;
252b5132 9032
24eab124 9033 do_memory_reference:
8325cc63
JB		 9034 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9035 return 0;
24eab124 9036 if ((i.mem_operands == 1
40fb9820 9037 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9038 || i.mem_operands == 2)
9039 {
9040 as_bad (_("too many memory references for `%s'"),
9041 current_templates->start->name);
9042 return 0;
9043 }
252b5132 9044
24eab124
AM		 9045 /* Check for base index form. We detect the base index form by
9046 looking for an ')' at the end of the operand, searching
9047 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9048 after the '('. */
af6bdddf 9049 base_string = op_string + strlen (op_string);
c3332e24 9050
43234a1e
L		 9051 /* Handle vector operations. */
9052 vop_start = strchr (op_string, '{');
9053 if (vop_start && vop_start < base_string)
9054 {
9055 if (check_VecOperations (vop_start, base_string) == NULL)
9056 return 0;
9057 base_string = vop_start;
9058 }
9059
af6bdddf
AM		 9060 --base_string;
9061 if (is_space_char (*base_string))
9062 --base_string;
252b5132 9063
47926f60 9064 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9065 displacement_string_start = op_string;
9066 displacement_string_end = base_string + 1;
252b5132 9067
24eab124
AM		 9068 if (*base_string == ')')
9069 {
af6bdddf 9070 char *temp_string;
24eab124
AM		 9071 unsigned int parens_balanced = 1;
9072 /* We've already checked that the number of left & right ()'s are
47926f60 9073 equal, so this loop will not be infinite. */
24eab124
AM		 9074 do
9075 {
9076 base_string--;
9077 if (*base_string == ')')
9078 parens_balanced++;
9079 if (*base_string == '(')
9080 parens_balanced--;
9081 }
9082 while (parens_balanced);
c3332e24 9083
af6bdddf 9084 temp_string = base_string;
c3332e24 9085
24eab124 9086 /* Skip past '(' and whitespace. */
252b5132
RH		 9087 ++base_string;
9088 if (is_space_char (*base_string))
24eab124 9089 ++base_string;
252b5132 9090
af6bdddf 9091 if (*base_string == ','
4eed87de
AM		 9092 || ((i.base_reg = parse_register (base_string, &end_op))
9093 != NULL))
252b5132 9094 {
af6bdddf 9095 displacement_string_end = temp_string;
252b5132 9096
40fb9820 9097 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9098
af6bdddf 9099 if (i.base_reg)
24eab124 9100 {
24eab124
AM		 9101 base_string = end_op;
9102 if (is_space_char (*base_string))
9103 ++base_string;
af6bdddf
AM		 9104 }
9105
9106 /* There may be an index reg or scale factor here. */
9107 if (*base_string == ',')
9108 {
9109 ++base_string;
9110 if (is_space_char (*base_string))
9111 ++base_string;
9112
4eed87de
AM		 9113 if ((i.index_reg = parse_register (base_string, &end_op))
9114 != NULL)
24eab124 9115 {
af6bdddf 9116 base_string = end_op;
24eab124
AM		 9117 if (is_space_char (*base_string))
9118 ++base_string;
af6bdddf
AM		 9119 if (*base_string == ',')
9120 {
9121 ++base_string;
9122 if (is_space_char (*base_string))
9123 ++base_string;
9124 }
e5cb08ac 9125 else if (*base_string != ')')
af6bdddf 9126 {
4eed87de
AM		 9127 as_bad (_("expecting `,' or `)' "
9128 "after index register in `%s'"),
af6bdddf
AM		 9129 operand_string);
9130 return 0;
9131 }
24eab124 9132 }
af6bdddf 9133 else if (*base_string == REGISTER_PREFIX)
24eab124 9134 {
f76bf5e0
L		 9135 end_op = strchr (base_string, ',');
9136 if (end_op)
9137 *end_op = '\0';
af6bdddf 9138 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9139 return 0;
9140 }
252b5132 9141
47926f60 9142 /* Check for scale factor. */
551c1ca1 9143 if (*base_string != ')')
af6bdddf 9144 {
551c1ca1
AM		 9145 char *end_scale = i386_scale (base_string);
9146
9147 if (!end_scale)
af6bdddf 9148 return 0;
24eab124 9149
551c1ca1 9150 base_string = end_scale;
af6bdddf
AM		 9151 if (is_space_char (*base_string))
9152 ++base_string;
9153 if (*base_string != ')')
9154 {
4eed87de
AM		 9155 as_bad (_("expecting `)' "
9156 "after scale factor in `%s'"),
af6bdddf
AM		 9157 operand_string);
9158 return 0;
9159 }
9160 }
9161 else if (!i.index_reg)
24eab124 9162 {
4eed87de
AM		 9163 as_bad (_("expecting index register or scale factor "
9164 "after `,'; got '%c'"),
af6bdddf 9165 *base_string);
24eab124
AM		 9166 return 0;
9167 }
9168 }
af6bdddf 9169 else if (*base_string != ')')
24eab124 9170 {
4eed87de
AM		 9171 as_bad (_("expecting `,' or `)' "
9172 "after base register in `%s'"),
af6bdddf 9173 operand_string);
24eab124
AM		 9174 return 0;
9175 }
c3332e24 9176 }
af6bdddf 9177 else if (*base_string == REGISTER_PREFIX)
c3332e24 9178 {
f76bf5e0
L		 9179 end_op = strchr (base_string, ',');
9180 if (end_op)
9181 *end_op = '\0';
af6bdddf 9182 as_bad (_("bad register name `%s'"), base_string);
24eab124 9183 return 0;
c3332e24 9184 }
24eab124
AM		 9185 }
9186
9187 /* If there's an expression beginning the operand, parse it,
9188 assuming displacement_string_start and
9189 displacement_string_end are meaningful. */
9190 if (displacement_string_start != displacement_string_end)
9191 {
9192 if (!i386_displacement (displacement_string_start,
9193 displacement_string_end))
9194 return 0;
9195 }
9196
9197 /* Special case for (%dx) while doing input/output op. */
9198 if (i.base_reg
0dfbf9d7
L		 9199 && operand_type_equal (&i.base_reg->reg_type,
9200 &reg16_inoutportreg)
24eab124
AM		 9201 && i.index_reg == 0
9202 && i.log2_scale_factor == 0
9203 && i.seg[i.mem_operands] == 0
40fb9820 9204 && !operand_type_check (i.types[this_operand], disp))
24eab124 9205 {
65da13b5 9206 i.types[this_operand] = inoutportreg;
24eab124
AM		 9207 return 1;
9208 }
9209
eecb386c
AM		 9210 if (i386_index_check (operand_string) == 0)
9211 return 0;
5c07affc 9212 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9213 if (i.mem_operands == 0)
9214 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9215 i.mem_operands++;
9216 }
9217 else
ce8a8b2f
AM		 9218 {
9219 /* It's not a memory operand; argh! */
24eab124
AM		 9220 as_bad (_("invalid char %s beginning operand %d `%s'"),
9221 output_invalid (*op_string),
9222 this_operand + 1,
9223 op_string);
9224 return 0;
9225 }
47926f60 9226 return 1; /* Normal return. */
252b5132
RH		 9227}
9228\f
fa94de6b
RM		 9229/* Calculate the maximum variable size (i.e., excluding fr_fix)
9230 that an rs_machine_dependent frag may reach. */
9231
9232unsigned int
9233i386_frag_max_var (fragS *frag)
9234{
9235 /* The only relaxable frags are for jumps.
9236 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9237 gas_assert (frag->fr_type == rs_machine_dependent);
9238 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9239}
9240
b084df0b
L		 9241#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9242static int
8dcea932 9243elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9244{
9245 /* STT_GNU_IFUNC symbol must go through PLT. */
9246 if ((symbol_get_bfdsym (fr_symbol)->flags
9247 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9248 return 0;
9249
9250 if (!S_IS_EXTERNAL (fr_symbol))
9251 /* Symbol may be weak or local. */
9252 return !S_IS_WEAK (fr_symbol);
9253
8dcea932
L		 9254 /* Global symbols with non-default visibility can't be preempted. */
9255 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9256 return 1;
9257
9258 if (fr_var != NO_RELOC)
9259 switch ((enum bfd_reloc_code_real) fr_var)
9260 {
9261 case BFD_RELOC_386_PLT32:
9262 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9263 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9264 return 0;
9265 default:
9266 abort ();
9267 }
9268
b084df0b
L		 9269 /* Global symbols with default visibility in a shared library may be
9270 preempted by another definition. */
8dcea932 9271 return !shared;
b084df0b
L		 9272}
9273#endif
9274
ee7fcc42
AM		 9275/* md_estimate_size_before_relax()
9276
9277 Called just before relax() for rs_machine_dependent frags. The x86
9278 assembler uses these frags to handle variable size jump
9279 instructions.
9280
9281 Any symbol that is now undefined will not become defined.
9282 Return the correct fr_subtype in the frag.
9283 Return the initial "guess for variable size of frag" to caller.
9284 The guess is actually the growth beyond the fixed part. Whatever
9285 we do to grow the fixed or variable part contributes to our
9286 returned value. */
9287
252b5132 9288int
7016a5d5 9289md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9290{
252b5132 9291 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9292 check for un-relaxable symbols. On an ELF system, we can't relax
9293 an externally visible symbol, because it may be overridden by a
9294 shared library. */
9295 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9296#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9297 || (IS_ELF
8dcea932
L		 9298 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9299 fragP->fr_var))
fbeb56a4
DK		 9300#endif
9301#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9302 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9303 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9304#endif
9305 )
252b5132 9306 {
b98ef147
AM		 9307 /* Symbol is undefined in this segment, or we need to keep a
9308 reloc so that weak symbols can be overridden. */
9309 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9310 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9311 unsigned char *opcode;
9312 int old_fr_fix;
f6af82bd 9313
ee7fcc42 9314 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9315 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9316 else if (size == 2)
f6af82bd
AM		 9317 reloc_type = BFD_RELOC_16_PCREL;
9318 else
9319 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9320
ee7fcc42
AM		 9321 old_fr_fix = fragP->fr_fix;
9322 opcode = (unsigned char *) fragP->fr_opcode;
9323
fddf5b5b 9324 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9325 {
fddf5b5b
AM		 9326 case UNCOND_JUMP:
9327 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9328 opcode[0] = 0xe9;
252b5132 9329 fragP->fr_fix += size;
062cd5e7
AS		 9330 fix_new (fragP, old_fr_fix, size,
9331 fragP->fr_symbol,
9332 fragP->fr_offset, 1,
9333 reloc_type);
252b5132
RH		 9334 break;
9335
fddf5b5b 9336 case COND_JUMP86:
412167cb
AM		 9337 if (size == 2
9338 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9339 {
9340 /* Negate the condition, and branch past an
9341 unconditional jump. */
9342 opcode[0] ^= 1;
9343 opcode[1] = 3;
9344 /* Insert an unconditional jump. */
9345 opcode[2] = 0xe9;
9346 /* We added two extra opcode bytes, and have a two byte
9347 offset. */
9348 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9349 fix_new (fragP, old_fr_fix + 2, 2,
9350 fragP->fr_symbol,
9351 fragP->fr_offset, 1,
9352 reloc_type);
fddf5b5b
AM		 9353 break;
9354 }
9355 /* Fall through. */
9356
9357 case COND_JUMP:
412167cb
AM		 9358 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9359 {
3e02c1cc
AM		 9360 fixS *fixP;
9361
412167cb 9362 fragP->fr_fix += 1;
3e02c1cc
AM		 9363 fixP = fix_new (fragP, old_fr_fix, 1,
9364 fragP->fr_symbol,
9365 fragP->fr_offset, 1,
9366 BFD_RELOC_8_PCREL);
9367 fixP->fx_signed = 1;
412167cb
AM		 9368 break;
9369 }
93c2a809 9370
24eab124 9371 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9372 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9373 opcode[1] = opcode[0] + 0x10;
f6af82bd 9374 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9375 /* We've added an opcode byte. */
9376 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9377 fix_new (fragP, old_fr_fix + 1, size,
9378 fragP->fr_symbol,
9379 fragP->fr_offset, 1,
9380 reloc_type);
252b5132 9381 break;
fddf5b5b
AM		 9382
9383 default:
9384 BAD_CASE (fragP->fr_subtype);
9385 break;
252b5132
RH		 9386 }
9387 frag_wane (fragP);
ee7fcc42 9388 return fragP->fr_fix - old_fr_fix;
252b5132 9389 }
93c2a809 9390
93c2a809
AM		 9391 /* Guess size depending on current relax state. Initially the relax
9392 state will correspond to a short jump and we return 1, because
9393 the variable part of the frag (the branch offset) is one byte
9394 long. However, we can relax a section more than once and in that
9395 case we must either set fr_subtype back to the unrelaxed state,
9396 or return the value for the appropriate branch. */
9397 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9398}
9399
47926f60
KH		 9400/* Called after relax() is finished.
9401
9402 In: Address of frag.
9403 fr_type == rs_machine_dependent.
9404 fr_subtype is what the address relaxed to.
9405
9406 Out: Any fixSs and constants are set up.
9407 Caller will turn frag into a ".space 0". */
9408
252b5132 9409void
7016a5d5
TG		 9410md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9411 fragS *fragP)
252b5132 9412{
29b0f896 9413 unsigned char *opcode;
252b5132 9414 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9415 offsetT target_address;
9416 offsetT opcode_address;
252b5132 9417 unsigned int extension = 0;
847f7ad4 9418 offsetT displacement_from_opcode_start;
252b5132
RH		 9419
9420 opcode = (unsigned char *) fragP->fr_opcode;
9421
47926f60 9422 /* Address we want to reach in file space. */
252b5132 9423 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9424
47926f60 9425 /* Address opcode resides at in file space. */
252b5132
RH		 9426 opcode_address = fragP->fr_address + fragP->fr_fix;
9427
47926f60 9428 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9429 displacement_from_opcode_start = target_address - opcode_address;
9430
fddf5b5b 9431 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9432 {
47926f60
KH		 9433 /* Don't have to change opcode. */
9434 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9435 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9436 }
9437 else
9438 {
9439 if (no_cond_jump_promotion
9440 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9441 as_warn_where (fragP->fr_file, fragP->fr_line,
9442 _("long jump required"));
252b5132 9443
fddf5b5b
AM		 9444 switch (fragP->fr_subtype)
9445 {
9446 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9447 extension = 4; /* 1 opcode + 4 displacement */
9448 opcode[0] = 0xe9;
9449 where_to_put_displacement = &opcode[1];
9450 break;
252b5132 9451
fddf5b5b
AM		 9452 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9453 extension = 2; /* 1 opcode + 2 displacement */
9454 opcode[0] = 0xe9;
9455 where_to_put_displacement = &opcode[1];
9456 break;
252b5132 9457
fddf5b5b
AM		 9458 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9459 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9460 extension = 5; /* 2 opcode + 4 displacement */
9461 opcode[1] = opcode[0] + 0x10;
9462 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9463 where_to_put_displacement = &opcode[2];
9464 break;
252b5132 9465
fddf5b5b
AM		 9466 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9467 extension = 3; /* 2 opcode + 2 displacement */
9468 opcode[1] = opcode[0] + 0x10;
9469 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9470 where_to_put_displacement = &opcode[2];
9471 break;
252b5132 9472
fddf5b5b
AM		 9473 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9474 extension = 4;
9475 opcode[0] ^= 1;
9476 opcode[1] = 3;
9477 opcode[2] = 0xe9;
9478 where_to_put_displacement = &opcode[3];
9479 break;
9480
9481 default:
9482 BAD_CASE (fragP->fr_subtype);
9483 break;
9484 }
252b5132 9485 }
fddf5b5b 9486
7b81dfbb
AJ		 9487 /* If size if less then four we are sure that the operand fits,
9488 but if it's 4, then it could be that the displacement is larger
9489 then -/+ 2GB. */
9490 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9491 && object_64bit
9492 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9493 + ((addressT) 1 << 31))
9494 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9495 {
9496 as_bad_where (fragP->fr_file, fragP->fr_line,
9497 _("jump target out of range"));
9498 /* Make us emit 0. */
9499 displacement_from_opcode_start = extension;
9500 }
47926f60 9501 /* Now put displacement after opcode. */
252b5132
RH		 9502 md_number_to_chars ((char *) where_to_put_displacement,
9503 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9504 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9505 fragP->fr_fix += extension;
9506}
9507\f
7016a5d5 9508/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9509 by our caller that we have all the info we need to fix it up.
9510
7016a5d5
TG		 9511 Parameter valP is the pointer to the value of the bits.
9512
252b5132
RH		 9513 On the 386, immediates, displacements, and data pointers are all in
9514 the same (little-endian) format, so we don't need to care about which
9515 we are handling. */
9516
94f592af 9517void
7016a5d5 9518md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9519{
94f592af 9520 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9521 valueT value = *valP;
252b5132 9522
f86103b7 9523#if !defined (TE_Mach)
93382f6d
AM		 9524 if (fixP->fx_pcrel)
9525 {
9526 switch (fixP->fx_r_type)
9527 {
5865bb77
ILT		 9528 default:
9529 break;
9530
d6ab8113
JB		 9531 case BFD_RELOC_64:
9532 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9533 break;
93382f6d 9534 case BFD_RELOC_32:
ae8887b5 9535 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9536 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9537 break;
9538 case BFD_RELOC_16:
9539 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9540 break;
9541 case BFD_RELOC_8:
9542 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9543 break;
9544 }
9545 }
252b5132 9546
a161fe53 9547 if (fixP->fx_addsy != NULL
31312f95 9548 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9549 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9550 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9551 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9552 && !use_rela_relocations)
252b5132 9553 {
31312f95
AM		 9554 /* This is a hack. There should be a better way to handle this.
9555 This covers for the fact that bfd_install_relocation will
9556 subtract the current location (for partial_inplace, PC relative
9557 relocations); see more below. */
252b5132 9558#ifndef OBJ_AOUT
718ddfc0 9559 if (IS_ELF
252b5132
RH		 9560#ifdef TE_PE
9561 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9562#endif
9563 )
9564 value += fixP->fx_where + fixP->fx_frag->fr_address;
9565#endif
9566#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9567 if (IS_ELF)
252b5132 9568 {
6539b54b 9569 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9570
6539b54b 9571 if ((sym_seg == seg
2f66722d 9572 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9573 && sym_seg != absolute_section))
af65af87 9574 && !generic_force_reloc (fixP))
2f66722d
AM		 9575 {
9576 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9577 bfd_install_relocation subtracts them out again. I think
9578 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9579 it. FIXME. */
9580 value += fixP->fx_where + fixP->fx_frag->fr_address;
9581 }
252b5132
RH		 9582 }
9583#endif
9584#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9585 /* For some reason, the PE format does not store a
9586 section address offset for a PC relative symbol. */
9587 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9588 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9589 value += md_pcrel_from (fixP);
9590#endif
9591 }
fbeb56a4 9592#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9593 if (fixP->fx_addsy != NULL
9594 && S_IS_WEAK (fixP->fx_addsy)
9595 /* PR 16858: Do not modify weak function references. */
9596 && ! fixP->fx_pcrel)
fbeb56a4 9597 {
296a8689
NC		 9598#if !defined (TE_PEP)
9599 /* For x86 PE weak function symbols are neither PC-relative
9600 nor do they set S_IS_FUNCTION. So the only reliable way
9601 to detect them is to check the flags of their containing
9602 section. */
9603 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9604 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9605 ;
9606 else
9607#endif
fbeb56a4
DK		 9608 value -= S_GET_VALUE (fixP->fx_addsy);
9609 }
9610#endif
252b5132
RH		 9611
9612 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9613 and we must not disappoint it. */
252b5132 9614#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9615 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9616 switch (fixP->fx_r_type)
9617 {
9618 case BFD_RELOC_386_PLT32:
3e73aa7c 9619 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9620 /* Make the jump instruction point to the address of the operand. At
9621 runtime we merely add the offset to the actual PLT entry. */
9622 value = -4;
9623 break;
31312f95 9624
13ae64f3
JJ		 9625 case BFD_RELOC_386_TLS_GD:
9626 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9627 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9628 case BFD_RELOC_386_TLS_IE:
9629 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9630 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9631 case BFD_RELOC_X86_64_TLSGD:
9632 case BFD_RELOC_X86_64_TLSLD:
9633 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9634 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9635 value = 0; /* Fully resolved at runtime. No addend. */
9636 /* Fallthrough */
9637 case BFD_RELOC_386_TLS_LE:
9638 case BFD_RELOC_386_TLS_LDO_32:
9639 case BFD_RELOC_386_TLS_LE_32:
9640 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9641 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9642 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9643 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9644 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9645 break;
9646
67a4f2b7
AO		 9647 case BFD_RELOC_386_TLS_DESC_CALL:
9648 case BFD_RELOC_X86_64_TLSDESC_CALL:
9649 value = 0; /* Fully resolved at runtime. No addend. */
9650 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9651 fixP->fx_done = 0;
9652 return;
9653
47926f60
KH		 9654 case BFD_RELOC_VTABLE_INHERIT:
9655 case BFD_RELOC_VTABLE_ENTRY:
9656 fixP->fx_done = 0;
94f592af 9657 return;
47926f60
KH		 9658
9659 default:
9660 break;
9661 }
9662#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9663 *valP = value;
f86103b7 9664#endif /* !defined (TE_Mach) */
3e73aa7c 9665
3e73aa7c 9666 /* Are we finished with this relocation now? */
c6682705 9667 if (fixP->fx_addsy == NULL)
3e73aa7c 9668 fixP->fx_done = 1;
fbeb56a4
DK		 9669#if defined (OBJ_COFF) && defined (TE_PE)
9670 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9671 {
9672 fixP->fx_done = 0;
9673 /* Remember value for tc_gen_reloc. */
9674 fixP->fx_addnumber = value;
9675 /* Clear out the frag for now. */
9676 value = 0;
9677 }
9678#endif
3e73aa7c
JH		 9679 else if (use_rela_relocations)
9680 {
9681 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9682 /* Remember value for tc_gen_reloc. */
9683 fixP->fx_addnumber = value;
3e73aa7c
JH		 9684 value = 0;
9685 }
f86103b7 9686
94f592af 9687 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9688}
252b5132 9689\f
6d4af3c2 9690const char *
499ac353 9691md_atof (int type, char *litP, int *sizeP)
252b5132 9692{
499ac353
NC		 9693 /* This outputs the LITTLENUMs in REVERSE order;
9694 in accord with the bigendian 386. */
9695 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9696}
9697\f
2d545b82 9698static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9699
252b5132 9700static char *
e3bb37b5 9701output_invalid (int c)
252b5132 9702{
3882b010 9703 if (ISPRINT (c))
f9f21a03
L		 9704 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9705 "'%c'", c);
252b5132 9706 else
f9f21a03 9707 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9708 "(0x%x)", (unsigned char) c);
252b5132
RH		 9709 return output_invalid_buf;
9710}
9711
af6bdddf 9712/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9713
9714static const reg_entry *
4d1bb795 9715parse_real_register (char *reg_string, char **end_op)
252b5132 9716{
af6bdddf
AM		 9717 char *s = reg_string;
9718 char *p;
252b5132
RH		 9719 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9720 const reg_entry *r;
9721
9722 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9723 if (*s == REGISTER_PREFIX)
9724 ++s;
9725
9726 if (is_space_char (*s))
9727 ++s;
9728
9729 p = reg_name_given;
af6bdddf 9730 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9731 {
9732 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9733 return (const reg_entry *) NULL;
9734 s++;
252b5132
RH		 9735 }
9736
6588847e
DN		 9737 /* For naked regs, make sure that we are not dealing with an identifier.
9738 This prevents confusing an identifier like `eax_var' with register
9739 `eax'. */
9740 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9741 return (const reg_entry *) NULL;
9742
af6bdddf 9743 *end_op = s;
252b5132
RH		 9744
9745 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9746
5f47d35b 9747 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9748 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9749 {
5f47d35b
AM		 9750 if (is_space_char (*s))
9751 ++s;
9752 if (*s == '(')
9753 {
af6bdddf 9754 ++s;
5f47d35b
AM		 9755 if (is_space_char (*s))
9756 ++s;
9757 if (*s >= '0' && *s <= '7')
9758 {
db557034 9759 int fpr = *s - '0';
af6bdddf 9760 ++s;
5f47d35b
AM		 9761 if (is_space_char (*s))
9762 ++s;
9763 if (*s == ')')
9764 {
9765 *end_op = s + 1;
1e9cc1c2 9766 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9767 know (r);
9768 return r + fpr;
5f47d35b 9769 }
5f47d35b 9770 }
47926f60 9771 /* We have "%st(" then garbage. */
5f47d35b
AM		 9772 return (const reg_entry *) NULL;
9773 }
9774 }
9775
a60de03c
JB		 9776 if (r == NULL || allow_pseudo_reg)
9777 return r;
9778
0dfbf9d7 9779 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9780 return (const reg_entry *) NULL;
9781
dc821c5f 9782 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 9783 || r->reg_type.bitfield.sreg3
9784 || r->reg_type.bitfield.control
9785 || r->reg_type.bitfield.debug
9786 || r->reg_type.bitfield.test)
9787 && !cpu_arch_flags.bitfield.cpui386)
9788 return (const reg_entry *) NULL;
9789
ca0d63fe 9790 if (r->reg_type.bitfield.tbyte
309d3373
JB		 9791 && !cpu_arch_flags.bitfield.cpu8087
9792 && !cpu_arch_flags.bitfield.cpu287
9793 && !cpu_arch_flags.bitfield.cpu387)
9794 return (const reg_entry *) NULL;
9795
1848e567 9796 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 9797 return (const reg_entry *) NULL;
9798
1b54b8d7 9799 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 9800 return (const reg_entry *) NULL;
9801
1b54b8d7 9802 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 9803 return (const reg_entry *) NULL;
9804
1b54b8d7 9805 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
1848e567
L		 9806 return (const reg_entry *) NULL;
9807
9808 if (r->reg_type.bitfield.regmask
9809 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 9810 return (const reg_entry *) NULL;
9811
db51cc60 9812 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9813 if (!allow_index_reg
db51cc60
L		 9814 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9815 return (const reg_entry *) NULL;
9816
43234a1e
L		 9817 /* Upper 16 vector register is only available with VREX in 64bit
9818 mode. */
9819 if ((r->reg_flags & RegVRex))
9820 {
86fa6981
L		 9821 if (i.vec_encoding == vex_encoding_default)
9822 i.vec_encoding = vex_encoding_evex;
9823
43234a1e 9824 if (!cpu_arch_flags.bitfield.cpuvrex
86fa6981 9825 || i.vec_encoding != vex_encoding_evex
43234a1e
L		 9826 || flag_code != CODE_64BIT)
9827 return (const reg_entry *) NULL;
43234a1e
L		 9828 }
9829
a60de03c 9830 if (((r->reg_flags & (RegRex64 | RegRex))
dc821c5f 9831 || r->reg_type.bitfield.qword)
40fb9820 9832 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9833 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9834 && flag_code != CODE_64BIT)
20f0a1fc 9835 return (const reg_entry *) NULL;
1ae00879 9836
b7240065
JB		 9837 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9838 return (const reg_entry *) NULL;
9839
252b5132
RH		 9840 return r;
9841}
4d1bb795
JB		 9842
9843/* REG_STRING starts *before* REGISTER_PREFIX. */
9844
9845static const reg_entry *
9846parse_register (char *reg_string, char **end_op)
9847{
9848 const reg_entry *r;
9849
9850 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9851 r = parse_real_register (reg_string, end_op);
9852 else
9853 r = NULL;
9854 if (!r)
9855 {
9856 char *save = input_line_pointer;
9857 char c;
9858 symbolS *symbolP;
9859
9860 input_line_pointer = reg_string;
d02603dc 9861 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9862 symbolP = symbol_find (reg_string);
9863 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9864 {
9865 const expressionS *e = symbol_get_value_expression (symbolP);
9866
0398aac5 9867 know (e->X_op == O_register);
4eed87de 9868 know (e->X_add_number >= 0
c3fe08fa 9869 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9870 r = i386_regtab + e->X_add_number;
d3bb6b49 9871 if ((r->reg_flags & RegVRex))
86fa6981 9872 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 9873 *end_op = input_line_pointer;
9874 }
9875 *input_line_pointer = c;
9876 input_line_pointer = save;
9877 }
9878 return r;
9879}
9880
9881int
9882i386_parse_name (char *name, expressionS *e, char *nextcharP)
9883{
9884 const reg_entry *r;
9885 char *end = input_line_pointer;
9886
9887 *end = *nextcharP;
9888 r = parse_register (name, &input_line_pointer);
9889 if (r && end <= input_line_pointer)
9890 {
9891 *nextcharP = *input_line_pointer;
9892 *input_line_pointer = 0;
9893 e->X_op = O_register;
9894 e->X_add_number = r - i386_regtab;
9895 return 1;
9896 }
9897 input_line_pointer = end;
9898 *end = 0;
ee86248c 9899 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9900}
9901
9902void
9903md_operand (expressionS *e)
9904{
ee86248c
JB		 9905 char *end;
9906 const reg_entry *r;
4d1bb795 9907
ee86248c
JB		 9908 switch (*input_line_pointer)
9909 {
9910 case REGISTER_PREFIX:
9911 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9912 if (r)
9913 {
9914 e->X_op = O_register;
9915 e->X_add_number = r - i386_regtab;
9916 input_line_pointer = end;
9917 }
ee86248c
JB		 9918 break;
9919
9920 case '[':
9c2799c2 9921 gas_assert (intel_syntax);
ee86248c
JB		 9922 end = input_line_pointer++;
9923 expression (e);
9924 if (*input_line_pointer == ']')
9925 {
9926 ++input_line_pointer;
9927 e->X_op_symbol = make_expr_symbol (e);
9928 e->X_add_symbol = NULL;
9929 e->X_add_number = 0;
9930 e->X_op = O_index;
9931 }
9932 else
9933 {
9934 e->X_op = O_absent;
9935 input_line_pointer = end;
9936 }
9937 break;
4d1bb795
JB		 9938 }
9939}
9940
252b5132 9941\f
4cc782b5 9942#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9943const char *md_shortopts = "kVQ:sqn";
252b5132 9944#else
12b55ccc 9945const char *md_shortopts = "qn";
252b5132 9946#endif
6e0b89ee 9947
3e73aa7c 9948#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9949#define OPTION_64 (OPTION_MD_BASE + 1)
9950#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9951#define OPTION_MARCH (OPTION_MD_BASE + 3)
9952#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9953#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9954#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9955#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9956#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9957#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9958#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9959#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9960#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9961#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9962#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9963#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9964#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9965#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9966#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9967#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9968#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9969#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9970#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9971#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9972#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9973#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9974
99ad8390
NC		 9975struct option md_longopts[] =
9976{
3e73aa7c 9977 {"32", no_argument, NULL, OPTION_32},
321098a5 9978#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9979 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9980 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9981#endif
9982#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9983 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9984 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9985#endif
b3b91714 9986 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9987 {"march", required_argument, NULL, OPTION_MARCH},
9988 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9989 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9990 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9991 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9992 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9993 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9994 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9995 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9996 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9997 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9998 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9999 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10000 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10001# if defined (TE_PE) || defined (TE_PEP)
10002 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10003#endif
d1982f93 10004 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10005 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10006 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10007 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10008 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10009 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10010 {NULL, no_argument, NULL, 0}
10011};
10012size_t md_longopts_size = sizeof (md_longopts);
10013
10014int
17b9d67d 10015md_parse_option (int c, const char *arg)
252b5132 10016{
91d6fa6a 10017 unsigned int j;
293f5f65 10018 char *arch, *next, *saved;
9103f4f4 10019
252b5132
RH		 10020 switch (c)
10021 {
12b55ccc
L		 10022 case 'n':
10023 optimize_align_code = 0;
10024 break;
10025
a38cf1db
AM		 10026 case 'q':
10027 quiet_warnings = 1;
252b5132
RH		 10028 break;
10029
10030#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10031 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10032 should be emitted or not. FIXME: Not implemented. */
10033 case 'Q':
252b5132
RH		 10034 break;
10035
10036 /* -V: SVR4 argument to print version ID. */
10037 case 'V':
10038 print_version_id ();
10039 break;
10040
a38cf1db
AM		 10041 /* -k: Ignore for FreeBSD compatibility. */
10042 case 'k':
252b5132 10043 break;
4cc782b5
ILT		 10044
10045 case 's':
10046 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10047 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10048 break;
8dcea932
L		 10049
10050 case OPTION_MSHARED:
10051 shared = 1;
10052 break;
99ad8390 10053#endif
321098a5 10054#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10055 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10056 case OPTION_64:
10057 {
10058 const char **list, **l;
10059
3e73aa7c
JH		 10060 list = bfd_target_list ();
10061 for (l = list; *l != NULL; l++)
8620418b 10062 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10063 || strcmp (*l, "coff-x86-64") == 0
10064 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10065 || strcmp (*l, "pei-x86-64") == 0
10066 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10067 {
10068 default_arch = "x86_64";
10069 break;
10070 }
3e73aa7c 10071 if (*l == NULL)
2b5d6a91 10072 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10073 free (list);
10074 }
10075 break;
10076#endif
252b5132 10077
351f65ca 10078#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10079 case OPTION_X32:
351f65ca
L		 10080 if (IS_ELF)
10081 {
10082 const char **list, **l;
10083
10084 list = bfd_target_list ();
10085 for (l = list; *l != NULL; l++)
10086 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10087 {
10088 default_arch = "x86_64:32";
10089 break;
10090 }
10091 if (*l == NULL)
2b5d6a91 10092 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10093 free (list);
10094 }
10095 else
10096 as_fatal (_("32bit x86_64 is only supported for ELF"));
10097 break;
10098#endif
10099
6e0b89ee
AM		 10100 case OPTION_32:
10101 default_arch = "i386";
10102 break;
10103
b3b91714
AM		 10104 case OPTION_DIVIDE:
10105#ifdef SVR4_COMMENT_CHARS
10106 {
10107 char *n, *t;
10108 const char *s;
10109
add39d23 10110 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10111 t = n;
10112 for (s = i386_comment_chars; *s != '\0'; s++)
10113 if (*s != '/')
10114 *t++ = *s;
10115 *t = '\0';
10116 i386_comment_chars = n;
10117 }
10118#endif
10119 break;
10120
9103f4f4 10121 case OPTION_MARCH:
293f5f65
L		 10122 saved = xstrdup (arg);
10123 arch = saved;
10124 /* Allow -march=+nosse. */
10125 if (*arch == '+')
10126 arch++;
6305a203 10127 do
9103f4f4 10128 {
6305a203 10129 if (*arch == '.')
2b5d6a91 10130 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10131 next = strchr (arch, '+');
10132 if (next)
10133 *next++ = '\0';
91d6fa6a 10134 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10135 {
91d6fa6a 10136 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10137 {
6305a203 10138 /* Processor. */
1ded5609
JB		 10139 if (! cpu_arch[j].flags.bitfield.cpui386)
10140 continue;
10141
91d6fa6a 10142 cpu_arch_name = cpu_arch[j].name;
6305a203 10143 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10144 cpu_arch_flags = cpu_arch[j].flags;
10145 cpu_arch_isa = cpu_arch[j].type;
10146 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10147 if (!cpu_arch_tune_set)
10148 {
10149 cpu_arch_tune = cpu_arch_isa;
10150 cpu_arch_tune_flags = cpu_arch_isa_flags;
10151 }
10152 break;
10153 }
91d6fa6a
NC		 10154 else if (*cpu_arch [j].name == '.'
10155 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10156 {
33eaf5de 10157 /* ISA extension. */
6305a203 10158 i386_cpu_flags flags;
309d3373 10159
293f5f65
L		 10160 flags = cpu_flags_or (cpu_arch_flags,
10161 cpu_arch[j].flags);
81486035 10162
5b64d091 10163 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10164 {
10165 if (cpu_sub_arch_name)
10166 {
10167 char *name = cpu_sub_arch_name;
10168 cpu_sub_arch_name = concat (name,
91d6fa6a 10169 cpu_arch[j].name,
1bf57e9f 10170 (const char *) NULL);
6305a203
L		 10171 free (name);
10172 }
10173 else
91d6fa6a 10174 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10175 cpu_arch_flags = flags;
a586129e 10176 cpu_arch_isa_flags = flags;
6305a203
L		 10177 }
10178 break;
ccc9c027 10179 }
9103f4f4 10180 }
6305a203 10181
293f5f65
L		 10182 if (j >= ARRAY_SIZE (cpu_arch))
10183 {
33eaf5de 10184 /* Disable an ISA extension. */
293f5f65
L		 10185 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10186 if (strcmp (arch, cpu_noarch [j].name) == 0)
10187 {
10188 i386_cpu_flags flags;
10189
10190 flags = cpu_flags_and_not (cpu_arch_flags,
10191 cpu_noarch[j].flags);
10192 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10193 {
10194 if (cpu_sub_arch_name)
10195 {
10196 char *name = cpu_sub_arch_name;
10197 cpu_sub_arch_name = concat (arch,
10198 (const char *) NULL);
10199 free (name);
10200 }
10201 else
10202 cpu_sub_arch_name = xstrdup (arch);
10203 cpu_arch_flags = flags;
10204 cpu_arch_isa_flags = flags;
10205 }
10206 break;
10207 }
10208
10209 if (j >= ARRAY_SIZE (cpu_noarch))
10210 j = ARRAY_SIZE (cpu_arch);
10211 }
10212
91d6fa6a 10213 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10214 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10215
10216 arch = next;
9103f4f4 10217 }
293f5f65
L		 10218 while (next != NULL);
10219 free (saved);
9103f4f4
L		 10220 break;
10221
10222 case OPTION_MTUNE:
10223 if (*arg == '.')
2b5d6a91 10224 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10225 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10226 {
91d6fa6a 10227 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10228 {
ccc9c027 10229 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10230 cpu_arch_tune = cpu_arch [j].type;
10231 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10232 break;
10233 }
10234 }
91d6fa6a 10235 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10236 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10237 break;
10238
1efbbeb4
L		 10239 case OPTION_MMNEMONIC:
10240 if (strcasecmp (arg, "att") == 0)
10241 intel_mnemonic = 0;
10242 else if (strcasecmp (arg, "intel") == 0)
10243 intel_mnemonic = 1;
10244 else
2b5d6a91 10245 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10246 break;
10247
10248 case OPTION_MSYNTAX:
10249 if (strcasecmp (arg, "att") == 0)
10250 intel_syntax = 0;
10251 else if (strcasecmp (arg, "intel") == 0)
10252 intel_syntax = 1;
10253 else
2b5d6a91 10254 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10255 break;
10256
10257 case OPTION_MINDEX_REG:
10258 allow_index_reg = 1;
10259 break;
10260
10261 case OPTION_MNAKED_REG:
10262 allow_naked_reg = 1;
10263 break;
10264
10265 case OPTION_MOLD_GCC:
10266 old_gcc = 1;
1efbbeb4
L		 10267 break;
10268
c0f3af97
L		 10269 case OPTION_MSSE2AVX:
10270 sse2avx = 1;
10271 break;
10272
daf50ae7
L		 10273 case OPTION_MSSE_CHECK:
10274 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10275 sse_check = check_error;
daf50ae7 10276 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10277 sse_check = check_warning;
daf50ae7 10278 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10279 sse_check = check_none;
daf50ae7 10280 else
2b5d6a91 10281 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10282 break;
10283
7bab8ab5
JB		 10284 case OPTION_MOPERAND_CHECK:
10285 if (strcasecmp (arg, "error") == 0)
10286 operand_check = check_error;
10287 else if (strcasecmp (arg, "warning") == 0)
10288 operand_check = check_warning;
10289 else if (strcasecmp (arg, "none") == 0)
10290 operand_check = check_none;
10291 else
10292 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10293 break;
10294
539f890d
L		 10295 case OPTION_MAVXSCALAR:
10296 if (strcasecmp (arg, "128") == 0)
10297 avxscalar = vex128;
10298 else if (strcasecmp (arg, "256") == 0)
10299 avxscalar = vex256;
10300 else
2b5d6a91 10301 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10302 break;
10303
7e8b059b
L		 10304 case OPTION_MADD_BND_PREFIX:
10305 add_bnd_prefix = 1;
10306 break;
10307
43234a1e
L		 10308 case OPTION_MEVEXLIG:
10309 if (strcmp (arg, "128") == 0)
10310 evexlig = evexl128;
10311 else if (strcmp (arg, "256") == 0)
10312 evexlig = evexl256;
10313 else if (strcmp (arg, "512") == 0)
10314 evexlig = evexl512;
10315 else
10316 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10317 break;
10318
d3d3c6db
IT		 10319 case OPTION_MEVEXRCIG:
10320 if (strcmp (arg, "rne") == 0)
10321 evexrcig = rne;
10322 else if (strcmp (arg, "rd") == 0)
10323 evexrcig = rd;
10324 else if (strcmp (arg, "ru") == 0)
10325 evexrcig = ru;
10326 else if (strcmp (arg, "rz") == 0)
10327 evexrcig = rz;
10328 else
10329 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10330 break;
10331
43234a1e
L		 10332 case OPTION_MEVEXWIG:
10333 if (strcmp (arg, "0") == 0)
10334 evexwig = evexw0;
10335 else if (strcmp (arg, "1") == 0)
10336 evexwig = evexw1;
10337 else
10338 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10339 break;
10340
167ad85b
TG		 10341# if defined (TE_PE) || defined (TE_PEP)
10342 case OPTION_MBIG_OBJ:
10343 use_big_obj = 1;
10344 break;
10345#endif
10346
d1982f93 10347 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10348 if (strcasecmp (arg, "yes") == 0)
10349 omit_lock_prefix = 1;
10350 else if (strcasecmp (arg, "no") == 0)
10351 omit_lock_prefix = 0;
10352 else
10353 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10354 break;
10355
e4e00185
AS		 10356 case OPTION_MFENCE_AS_LOCK_ADD:
10357 if (strcasecmp (arg, "yes") == 0)
10358 avoid_fence = 1;
10359 else if (strcasecmp (arg, "no") == 0)
10360 avoid_fence = 0;
10361 else
10362 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10363 break;
10364
0cb4071e
L		 10365 case OPTION_MRELAX_RELOCATIONS:
10366 if (strcasecmp (arg, "yes") == 0)
10367 generate_relax_relocations = 1;
10368 else if (strcasecmp (arg, "no") == 0)
10369 generate_relax_relocations = 0;
10370 else
10371 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10372 break;
10373
5db04b09 10374 case OPTION_MAMD64:
e89c5eaa 10375 intel64 = 0;
5db04b09
L		 10376 break;
10377
10378 case OPTION_MINTEL64:
e89c5eaa 10379 intel64 = 1;
5db04b09
L		 10380 break;
10381
252b5132
RH		 10382 default:
10383 return 0;
10384 }
10385 return 1;
10386}
10387
8a2c8fef
L		 10388#define MESSAGE_TEMPLATE \
10389" "
10390
293f5f65
L		 10391static char *
10392output_message (FILE *stream, char *p, char *message, char *start,
10393 int *left_p, const char *name, int len)
10394{
10395 int size = sizeof (MESSAGE_TEMPLATE);
10396 int left = *left_p;
10397
10398 /* Reserve 2 spaces for ", " or ",\0" */
10399 left -= len + 2;
10400
10401 /* Check if there is any room. */
10402 if (left >= 0)
10403 {
10404 if (p != start)
10405 {
10406 *p++ = ',';
10407 *p++ = ' ';
10408 }
10409 p = mempcpy (p, name, len);
10410 }
10411 else
10412 {
10413 /* Output the current message now and start a new one. */
10414 *p++ = ',';
10415 *p = '\0';
10416 fprintf (stream, "%s\n", message);
10417 p = start;
10418 left = size - (start - message) - len - 2;
10419
10420 gas_assert (left >= 0);
10421
10422 p = mempcpy (p, name, len);
10423 }
10424
10425 *left_p = left;
10426 return p;
10427}
10428
8a2c8fef 10429static void
1ded5609 10430show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10431{
10432 static char message[] = MESSAGE_TEMPLATE;
10433 char *start = message + 27;
10434 char *p;
10435 int size = sizeof (MESSAGE_TEMPLATE);
10436 int left;
10437 const char *name;
10438 int len;
10439 unsigned int j;
10440
10441 p = start;
10442 left = size - (start - message);
10443 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10444 {
10445 /* Should it be skipped? */
10446 if (cpu_arch [j].skip)
10447 continue;
10448
10449 name = cpu_arch [j].name;
10450 len = cpu_arch [j].len;
10451 if (*name == '.')
10452 {
10453 /* It is an extension. Skip if we aren't asked to show it. */
10454 if (ext)
10455 {
10456 name++;
10457 len--;
10458 }
10459 else
10460 continue;
10461 }
10462 else if (ext)
10463 {
10464 /* It is an processor. Skip if we show only extension. */
10465 continue;
10466 }
1ded5609
JB		 10467 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10468 {
10469 /* It is an impossible processor - skip. */
10470 continue;
10471 }
8a2c8fef 10472
293f5f65 10473 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10474 }
10475
293f5f65
L		 10476 /* Display disabled extensions. */
10477 if (ext)
10478 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10479 {
10480 name = cpu_noarch [j].name;
10481 len = cpu_noarch [j].len;
10482 p = output_message (stream, p, message, start, &left, name,
10483 len);
10484 }
10485
8a2c8fef
L		 10486 *p = '\0';
10487 fprintf (stream, "%s\n", message);
10488}
10489
252b5132 10490void
8a2c8fef 10491md_show_usage (FILE *stream)
252b5132 10492{
4cc782b5
ILT		 10493#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10494 fprintf (stream, _("\
a38cf1db
AM		 10495 -Q ignored\n\
10496 -V print assembler version number\n\
b3b91714
AM		 10497 -k ignored\n"));
10498#endif
10499 fprintf (stream, _("\
12b55ccc 10500 -n Do not optimize code alignment\n\
b3b91714
AM		 10501 -q quieten some warnings\n"));
10502#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10503 fprintf (stream, _("\
a38cf1db 10504 -s ignored\n"));
b3b91714 10505#endif
321098a5
L		 10506#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10507 || defined (TE_PE) || defined (TE_PEP))
751d281c 10508 fprintf (stream, _("\
570561f7 10509 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10510#endif
b3b91714
AM		 10511#ifdef SVR4_COMMENT_CHARS
10512 fprintf (stream, _("\
10513 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10514#else
10515 fprintf (stream, _("\
b3b91714 10516 --divide ignored\n"));
4cc782b5 10517#endif
9103f4f4 10518 fprintf (stream, _("\
6305a203 10519 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10520 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10521 show_arch (stream, 0, 1);
8a2c8fef
L		 10522 fprintf (stream, _("\
10523 EXTENSION is combination of:\n"));
1ded5609 10524 show_arch (stream, 1, 0);
6305a203 10525 fprintf (stream, _("\
8a2c8fef 10526 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10527 show_arch (stream, 0, 0);
ba104c83 10528 fprintf (stream, _("\
c0f3af97
L		 10529 -msse2avx encode SSE instructions with VEX prefix\n"));
10530 fprintf (stream, _("\
daf50ae7
L		 10531 -msse-check=[none|error|warning]\n\
10532 check SSE instructions\n"));
10533 fprintf (stream, _("\
7bab8ab5
JB		 10534 -moperand-check=[none|error|warning]\n\
10535 check operand combinations for validity\n"));
10536 fprintf (stream, _("\
539f890d
L		 10537 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10538 length\n"));
10539 fprintf (stream, _("\
43234a1e
L		 10540 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10541 length\n"));
10542 fprintf (stream, _("\
10543 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10544 for EVEX.W bit ignored instructions\n"));
10545 fprintf (stream, _("\
d3d3c6db
IT		 10546 -mevexrcig=[rne|rd|ru|rz]\n\
10547 encode EVEX instructions with specific EVEX.RC value\n\
10548 for SAE-only ignored instructions\n"));
10549 fprintf (stream, _("\
ba104c83
L		 10550 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10551 fprintf (stream, _("\
10552 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10553 fprintf (stream, _("\
10554 -mindex-reg support pseudo index registers\n"));
10555 fprintf (stream, _("\
10556 -mnaked-reg don't require `%%' prefix for registers\n"));
10557 fprintf (stream, _("\
10558 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10559 fprintf (stream, _("\
10560 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10561 fprintf (stream, _("\
10562 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10563# if defined (TE_PE) || defined (TE_PEP)
10564 fprintf (stream, _("\
10565 -mbig-obj generate big object files\n"));
10566#endif
d022bddd
IT		 10567 fprintf (stream, _("\
10568 -momit-lock-prefix=[no|yes]\n\
10569 strip all lock prefixes\n"));
5db04b09 10570 fprintf (stream, _("\
e4e00185
AS		 10571 -mfence-as-lock-add=[no|yes]\n\
10572 encode lfence, mfence and sfence as\n\
10573 lock addl $0x0, (%%{re}sp)\n"));
10574 fprintf (stream, _("\
0cb4071e
L		 10575 -mrelax-relocations=[no|yes]\n\
10576 generate relax relocations\n"));
10577 fprintf (stream, _("\
5db04b09
L		 10578 -mamd64 accept only AMD64 ISA\n"));
10579 fprintf (stream, _("\
10580 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10581}
10582
3e73aa7c 10583#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10584 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10585 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10586
10587/* Pick the target format to use. */
10588
47926f60 10589const char *
e3bb37b5 10590i386_target_format (void)
252b5132 10591{
351f65ca
L		 10592 if (!strncmp (default_arch, "x86_64", 6))
10593 {
10594 update_code_flag (CODE_64BIT, 1);
10595 if (default_arch[6] == '\0')
7f56bc95 10596 x86_elf_abi = X86_64_ABI;
351f65ca 10597 else
7f56bc95 10598 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10599 }
3e73aa7c 10600 else if (!strcmp (default_arch, "i386"))
78f12dd3 10601 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10602 else if (!strcmp (default_arch, "iamcu"))
10603 {
10604 update_code_flag (CODE_32BIT, 1);
10605 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10606 {
10607 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10608 cpu_arch_name = "iamcu";
10609 cpu_sub_arch_name = NULL;
10610 cpu_arch_flags = iamcu_flags;
10611 cpu_arch_isa = PROCESSOR_IAMCU;
10612 cpu_arch_isa_flags = iamcu_flags;
10613 if (!cpu_arch_tune_set)
10614 {
10615 cpu_arch_tune = cpu_arch_isa;
10616 cpu_arch_tune_flags = cpu_arch_isa_flags;
10617 }
10618 }
8d471ec1 10619 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 10620 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10621 cpu_arch_name);
10622 }
3e73aa7c 10623 else
2b5d6a91 10624 as_fatal (_("unknown architecture"));
89507696
JB		 10625
10626 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10627 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10628 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10629 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10630
252b5132
RH		 10631 switch (OUTPUT_FLAVOR)
10632 {
9384f2ff 10633#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10634 case bfd_target_aout_flavour:
47926f60 10635 return AOUT_TARGET_FORMAT;
4c63da97 10636#endif
9384f2ff
AM		 10637#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10638# if defined (TE_PE) || defined (TE_PEP)
10639 case bfd_target_coff_flavour:
167ad85b
TG		 10640 if (flag_code == CODE_64BIT)
10641 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10642 else
10643 return "pe-i386";
9384f2ff 10644# elif defined (TE_GO32)
0561d57c
JK		 10645 case bfd_target_coff_flavour:
10646 return "coff-go32";
9384f2ff 10647# else
252b5132
RH		 10648 case bfd_target_coff_flavour:
10649 return "coff-i386";
9384f2ff 10650# endif
4c63da97 10651#endif
3e73aa7c 10652#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10653 case bfd_target_elf_flavour:
3e73aa7c 10654 {
351f65ca
L		 10655 const char *format;
10656
10657 switch (x86_elf_abi)
4fa24527 10658 {
351f65ca
L		 10659 default:
10660 format = ELF_TARGET_FORMAT;
10661 break;
7f56bc95 10662 case X86_64_ABI:
351f65ca 10663 use_rela_relocations = 1;
4fa24527 10664 object_64bit = 1;
351f65ca
L		 10665 format = ELF_TARGET_FORMAT64;
10666 break;
7f56bc95 10667 case X86_64_X32_ABI:
4fa24527 10668 use_rela_relocations = 1;
351f65ca 10669 object_64bit = 1;
862be3fb 10670 disallow_64bit_reloc = 1;
351f65ca
L		 10671 format = ELF_TARGET_FORMAT32;
10672 break;
4fa24527 10673 }
3632d14b 10674 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10675 {
7f56bc95 10676 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10677 as_fatal (_("Intel L1OM is 64bit only"));
10678 return ELF_TARGET_L1OM_FORMAT;
10679 }
b49f93f6 10680 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10681 {
10682 if (x86_elf_abi != X86_64_ABI)
10683 as_fatal (_("Intel K1OM is 64bit only"));
10684 return ELF_TARGET_K1OM_FORMAT;
10685 }
81486035
L		 10686 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10687 {
10688 if (x86_elf_abi != I386_ABI)
10689 as_fatal (_("Intel MCU is 32bit only"));
10690 return ELF_TARGET_IAMCU_FORMAT;
10691 }
8a9036a4 10692 else
351f65ca 10693 return format;
3e73aa7c 10694 }
e57f8c65
TG		 10695#endif
10696#if defined (OBJ_MACH_O)
10697 case bfd_target_mach_o_flavour:
d382c579
TG		 10698 if (flag_code == CODE_64BIT)
10699 {
10700 use_rela_relocations = 1;
10701 object_64bit = 1;
10702 return "mach-o-x86-64";
10703 }
10704 else
10705 return "mach-o-i386";
4c63da97 10706#endif
252b5132
RH		 10707 default:
10708 abort ();
10709 return NULL;
10710 }
10711}
10712
47926f60 10713#endif /* OBJ_MAYBE_ more than one */
252b5132 10714\f
252b5132 10715symbolS *
7016a5d5 10716md_undefined_symbol (char *name)
252b5132 10717{
18dc2407
ILT		 10718 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10719 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10720 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10721 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10722 {
10723 if (!GOT_symbol)
10724 {
10725 if (symbol_find (name))
10726 as_bad (_("GOT already in symbol table"));
10727 GOT_symbol = symbol_new (name, undefined_section,
10728 (valueT) 0, &zero_address_frag);
10729 };
10730 return GOT_symbol;
10731 }
252b5132
RH		 10732 return 0;
10733}
10734
10735/* Round up a section size to the appropriate boundary. */
47926f60 10736
252b5132 10737valueT
7016a5d5 10738md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10739{
4c63da97
AM		 10740#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10741 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10742 {
10743 /* For a.out, force the section size to be aligned. If we don't do
10744 this, BFD will align it for us, but it will not write out the
10745 final bytes of the section. This may be a bug in BFD, but it is
10746 easier to fix it here since that is how the other a.out targets
10747 work. */
10748 int align;
10749
10750 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10751 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10752 }
252b5132
RH		 10753#endif
10754
10755 return size;
10756}
10757
10758/* On the i386, PC-relative offsets are relative to the start of the
10759 next instruction. That is, the address of the offset, plus its
10760 size, since the offset is always the last part of the insn. */
10761
10762long
e3bb37b5 10763md_pcrel_from (fixS *fixP)
252b5132
RH		 10764{
10765 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10766}
10767
10768#ifndef I386COFF
10769
10770static void
e3bb37b5 10771s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10772{
29b0f896 10773 int temp;
252b5132 10774
8a75718c
JB		 10775#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10776 if (IS_ELF)
10777 obj_elf_section_change_hook ();
10778#endif
252b5132
RH		 10779 temp = get_absolute_expression ();
10780 subseg_set (bss_section, (subsegT) temp);
10781 demand_empty_rest_of_line ();
10782}
10783
10784#endif
10785
252b5132 10786void
e3bb37b5 10787i386_validate_fix (fixS *fixp)
252b5132 10788{
02a86693 10789 if (fixp->fx_subsy)
252b5132 10790 {
02a86693 10791 if (fixp->fx_subsy == GOT_symbol)
23df1078 10792 {
02a86693
L		 10793 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10794 {
10795 if (!object_64bit)
10796 abort ();
10797#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10798 if (fixp->fx_tcbit2)
56ceb5b5
L		 10799 fixp->fx_r_type = (fixp->fx_tcbit
10800 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10801 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10802 else
10803#endif
10804 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10805 }
d6ab8113 10806 else
02a86693
L		 10807 {
10808 if (!object_64bit)
10809 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10810 else
10811 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10812 }
10813 fixp->fx_subsy = 0;
23df1078 10814 }
252b5132 10815 }
02a86693
L		 10816#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10817 else if (!object_64bit)
10818 {
10819 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10820 && fixp->fx_tcbit2)
10821 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10822 }
10823#endif
252b5132
RH		 10824}
10825
252b5132 10826arelent *
7016a5d5 10827tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10828{
10829 arelent *rel;
10830 bfd_reloc_code_real_type code;
10831
10832 switch (fixp->fx_r_type)
10833 {
8ce3d284 10834#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10835 case BFD_RELOC_SIZE32:
10836 case BFD_RELOC_SIZE64:
10837 if (S_IS_DEFINED (fixp->fx_addsy)
10838 && !S_IS_EXTERNAL (fixp->fx_addsy))
10839 {
10840 /* Resolve size relocation against local symbol to size of
10841 the symbol plus addend. */
10842 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10843 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10844 && !fits_in_unsigned_long (value))
10845 as_bad_where (fixp->fx_file, fixp->fx_line,
10846 _("symbol size computation overflow"));
10847 fixp->fx_addsy = NULL;
10848 fixp->fx_subsy = NULL;
10849 md_apply_fix (fixp, (valueT *) &value, NULL);
10850 return NULL;
10851 }
8ce3d284 10852#endif
1a0670f3 10853 /* Fall through. */
8fd4256d 10854
3e73aa7c
JH		 10855 case BFD_RELOC_X86_64_PLT32:
10856 case BFD_RELOC_X86_64_GOT32:
10857 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10858 case BFD_RELOC_X86_64_GOTPCRELX:
10859 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10860 case BFD_RELOC_386_PLT32:
10861 case BFD_RELOC_386_GOT32:
02a86693 10862 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10863 case BFD_RELOC_386_GOTOFF:
10864 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10865 case BFD_RELOC_386_TLS_GD:
10866 case BFD_RELOC_386_TLS_LDM:
10867 case BFD_RELOC_386_TLS_LDO_32:
10868 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10869 case BFD_RELOC_386_TLS_IE:
10870 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10871 case BFD_RELOC_386_TLS_LE_32:
10872 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10873 case BFD_RELOC_386_TLS_GOTDESC:
10874 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10875 case BFD_RELOC_X86_64_TLSGD:
10876 case BFD_RELOC_X86_64_TLSLD:
10877 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10878 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10879 case BFD_RELOC_X86_64_GOTTPOFF:
10880 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10881 case BFD_RELOC_X86_64_TPOFF64:
10882 case BFD_RELOC_X86_64_GOTOFF64:
10883 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10884 case BFD_RELOC_X86_64_GOT64:
10885 case BFD_RELOC_X86_64_GOTPCREL64:
10886 case BFD_RELOC_X86_64_GOTPC64:
10887 case BFD_RELOC_X86_64_GOTPLT64:
10888 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10889 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10890 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10891 case BFD_RELOC_RVA:
10892 case BFD_RELOC_VTABLE_ENTRY:
10893 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10894#ifdef TE_PE
10895 case BFD_RELOC_32_SECREL:
10896#endif
252b5132
RH		 10897 code = fixp->fx_r_type;
10898 break;
dbbaec26
L		 10899 case BFD_RELOC_X86_64_32S:
10900 if (!fixp->fx_pcrel)
10901 {
10902 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10903 code = fixp->fx_r_type;
10904 break;
10905 }
1a0670f3 10906 /* Fall through. */
252b5132 10907 default:
93382f6d 10908 if (fixp->fx_pcrel)
252b5132 10909 {
93382f6d
AM		 10910 switch (fixp->fx_size)
10911 {
10912 default:
b091f402
AM		 10913 as_bad_where (fixp->fx_file, fixp->fx_line,
10914 _("can not do %d byte pc-relative relocation"),
10915 fixp->fx_size);
93382f6d
AM		 10916 code = BFD_RELOC_32_PCREL;
10917 break;
10918 case 1: code = BFD_RELOC_8_PCREL; break;
10919 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10920 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10921#ifdef BFD64
10922 case 8: code = BFD_RELOC_64_PCREL; break;
10923#endif
93382f6d
AM		 10924 }
10925 }
10926 else
10927 {
10928 switch (fixp->fx_size)
10929 {
10930 default:
b091f402
AM		 10931 as_bad_where (fixp->fx_file, fixp->fx_line,
10932 _("can not do %d byte relocation"),
10933 fixp->fx_size);
93382f6d
AM		 10934 code = BFD_RELOC_32;
10935 break;
10936 case 1: code = BFD_RELOC_8; break;
10937 case 2: code = BFD_RELOC_16; break;
10938 case 4: code = BFD_RELOC_32; break;
937149dd 10939#ifdef BFD64
3e73aa7c 10940 case 8: code = BFD_RELOC_64; break;
937149dd 10941#endif
93382f6d 10942 }
252b5132
RH		 10943 }
10944 break;
10945 }
252b5132 10946
d182319b
JB		 10947 if ((code == BFD_RELOC_32
10948 || code == BFD_RELOC_32_PCREL
10949 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10950 && GOT_symbol
10951 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10952 {
4fa24527 10953 if (!object_64bit)
d6ab8113
JB		 10954 code = BFD_RELOC_386_GOTPC;
10955 else
10956 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10957 }
7b81dfbb
AJ		 10958 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10959 && GOT_symbol
10960 && fixp->fx_addsy == GOT_symbol)
10961 {
10962 code = BFD_RELOC_X86_64_GOTPC64;
10963 }
252b5132 10964
add39d23
TS		 10965 rel = XNEW (arelent);
10966 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10967 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10968
10969 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10970
3e73aa7c
JH		 10971 if (!use_rela_relocations)
10972 {
10973 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10974 vtable entry to be used in the relocation's section offset. */
10975 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10976 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10977#if defined (OBJ_COFF) && defined (TE_PE)
10978 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10979 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10980 else
10981#endif
c6682705 10982 rel->addend = 0;
3e73aa7c
JH		 10983 }
10984 /* Use the rela in 64bit mode. */
252b5132 10985 else
3e73aa7c 10986 {
862be3fb
L		 10987 if (disallow_64bit_reloc)
10988 switch (code)
10989 {
862be3fb
L		 10990 case BFD_RELOC_X86_64_DTPOFF64:
10991 case BFD_RELOC_X86_64_TPOFF64:
10992 case BFD_RELOC_64_PCREL:
10993 case BFD_RELOC_X86_64_GOTOFF64:
10994 case BFD_RELOC_X86_64_GOT64:
10995 case BFD_RELOC_X86_64_GOTPCREL64:
10996 case BFD_RELOC_X86_64_GOTPC64:
10997 case BFD_RELOC_X86_64_GOTPLT64:
10998 case BFD_RELOC_X86_64_PLTOFF64:
10999 as_bad_where (fixp->fx_file, fixp->fx_line,
11000 _("cannot represent relocation type %s in x32 mode"),
11001 bfd_get_reloc_code_name (code));
11002 break;
11003 default:
11004 break;
11005 }
11006
062cd5e7
AS		 11007 if (!fixp->fx_pcrel)
11008 rel->addend = fixp->fx_offset;
11009 else
11010 switch (code)
11011 {
11012 case BFD_RELOC_X86_64_PLT32:
11013 case BFD_RELOC_X86_64_GOT32:
11014 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11015 case BFD_RELOC_X86_64_GOTPCRELX:
11016 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11017 case BFD_RELOC_X86_64_TLSGD:
11018 case BFD_RELOC_X86_64_TLSLD:
11019 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11020 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11021 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11022 rel->addend = fixp->fx_offset - fixp->fx_size;
11023 break;
11024 default:
11025 rel->addend = (section->vma
11026 - fixp->fx_size
11027 + fixp->fx_addnumber
11028 + md_pcrel_from (fixp));
11029 break;
11030 }
3e73aa7c
JH		 11031 }
11032
252b5132
RH		 11033 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11034 if (rel->howto == NULL)
11035 {
11036 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11037 _("cannot represent relocation type %s"),
252b5132
RH		 11038 bfd_get_reloc_code_name (code));
11039 /* Set howto to a garbage value so that we can keep going. */
11040 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11041 gas_assert (rel->howto != NULL);
252b5132
RH		 11042 }
11043
11044 return rel;
11045}
11046
ee86248c 11047#include "tc-i386-intel.c"
54cfded0 11048
a60de03c
JB		 11049void
11050tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11051{
a60de03c
JB		 11052 int saved_naked_reg;
11053 char saved_register_dot;
54cfded0 11054
a60de03c
JB		 11055 saved_naked_reg = allow_naked_reg;
11056 allow_naked_reg = 1;
11057 saved_register_dot = register_chars['.'];
11058 register_chars['.'] = '.';
11059 allow_pseudo_reg = 1;
11060 expression_and_evaluate (exp);
11061 allow_pseudo_reg = 0;
11062 register_chars['.'] = saved_register_dot;
11063 allow_naked_reg = saved_naked_reg;
11064
e96d56a1 11065 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11066 {
a60de03c
JB		 11067 if ((addressT) exp->X_add_number < i386_regtab_size)
11068 {
11069 exp->X_op = O_constant;
11070 exp->X_add_number = i386_regtab[exp->X_add_number]
11071 .dw2_regnum[flag_code >> 1];
11072 }
11073 else
11074 exp->X_op = O_illegal;
54cfded0 11075 }
54cfded0
AM		 11076}
11077
11078void
11079tc_x86_frame_initial_instructions (void)
11080{
a60de03c
JB		 11081 static unsigned int sp_regno[2];
11082
11083 if (!sp_regno[flag_code >> 1])
11084 {
11085 char *saved_input = input_line_pointer;
11086 char sp[][4] = {"esp", "rsp"};
11087 expressionS exp;
a4447b93 11088
a60de03c
JB		 11089 input_line_pointer = sp[flag_code >> 1];
11090 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11091 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11092 sp_regno[flag_code >> 1] = exp.X_add_number;
11093 input_line_pointer = saved_input;
11094 }
a4447b93 11095
61ff971f
L		 11096 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11097 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11098}
d2b2c203 11099
d7921315
L		 11100int
11101x86_dwarf2_addr_size (void)
11102{
11103#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11104 if (x86_elf_abi == X86_64_X32_ABI)
11105 return 4;
11106#endif
11107 return bfd_arch_bits_per_address (stdoutput) / 8;
11108}
11109
d2b2c203
DJ		 11110int
11111i386_elf_section_type (const char *str, size_t len)
11112{
11113 if (flag_code == CODE_64BIT
11114 && len == sizeof ("unwind") - 1
11115 && strncmp (str, "unwind", 6) == 0)
11116 return SHT_X86_64_UNWIND;
11117
11118 return -1;
11119}
bb41ade5 11120
ad5fec3b
EB		 11121#ifdef TE_SOLARIS
11122void
11123i386_solaris_fix_up_eh_frame (segT sec)
11124{
11125 if (flag_code == CODE_64BIT)
11126 elf_section_type (sec) = SHT_X86_64_UNWIND;
11127}
11128#endif
11129
bb41ade5
AM		 11130#ifdef TE_PE
11131void
11132tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11133{
91d6fa6a 11134 expressionS exp;
bb41ade5 11135
91d6fa6a
NC		 11136 exp.X_op = O_secrel;
11137 exp.X_add_symbol = symbol;
11138 exp.X_add_number = 0;
11139 emit_expr (&exp, size);
bb41ade5
AM		 11140}
11141#endif
3b22753a
L		 11142
11143#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11144/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11145
01e1a5bc 11146bfd_vma
6d4af3c2 11147x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11148{
11149 if (flag_code == CODE_64BIT)
11150 {
11151 if (letter == 'l')
11152 return SHF_X86_64_LARGE;
11153
8f3bae45 11154 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11155 }
3b22753a 11156 else
8f3bae45 11157 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11158 return -1;
11159}
11160
01e1a5bc 11161bfd_vma
3b22753a
L		 11162x86_64_section_word (char *str, size_t len)
11163{
8620418b 11164 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11165 return SHF_X86_64_LARGE;
11166
11167 return -1;
11168}
11169
11170static void
11171handle_large_common (int small ATTRIBUTE_UNUSED)
11172{
11173 if (flag_code != CODE_64BIT)
11174 {
11175 s_comm_internal (0, elf_common_parse);
11176 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11177 }
11178 else
11179 {
11180 static segT lbss_section;
11181 asection *saved_com_section_ptr = elf_com_section_ptr;
11182 asection *saved_bss_section = bss_section;
11183
11184 if (lbss_section == NULL)
11185 {
11186 flagword applicable;
11187 segT seg = now_seg;
11188 subsegT subseg = now_subseg;
11189
11190 /* The .lbss section is for local .largecomm symbols. */
11191 lbss_section = subseg_new (".lbss", 0);
11192 applicable = bfd_applicable_section_flags (stdoutput);
11193 bfd_set_section_flags (stdoutput, lbss_section,
11194 applicable & SEC_ALLOC);
11195 seg_info (lbss_section)->bss = 1;
11196
11197 subseg_set (seg, subseg);
11198 }
11199
11200 elf_com_section_ptr = &_bfd_elf_large_com_section;
11201 bss_section = lbss_section;
11202
11203 s_comm_internal (0, elf_common_parse);
11204
11205 elf_com_section_ptr = saved_com_section_ptr;
11206 bss_section = saved_bss_section;
11207 }
11208}
11209#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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