Commit | Line | Data |
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252b5132 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
4c63da97 | 2 | Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000 |
47926f60 | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
21 | ||
47926f60 KH |
22 | /* Intel 80386 machine specific gas. |
23 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
24 | Bugs & suggestions are completely welcome. This is free software. | |
25 | Please help us make it better. */ | |
252b5132 RH |
26 | |
27 | #include <ctype.h> | |
28 | ||
29 | #include "as.h" | |
30 | #include "subsegs.h" | |
31 | #include "opcode/i386.h" | |
32 | ||
252b5132 RH |
33 | #ifndef REGISTER_WARNINGS |
34 | #define REGISTER_WARNINGS 1 | |
35 | #endif | |
36 | ||
c3332e24 | 37 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 38 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
39 | #endif |
40 | ||
252b5132 RH |
41 | #ifndef SCALE1_WHEN_NO_INDEX |
42 | /* Specifying a scale factor besides 1 when there is no index is | |
43 | futile. eg. `mov (%ebx,2),%al' does exactly the same as | |
44 | `mov (%ebx),%al'. To slavishly follow what the programmer | |
45 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ | |
46 | #define SCALE1_WHEN_NO_INDEX 1 | |
47 | #endif | |
48 | ||
49 | #define true 1 | |
50 | #define false 0 | |
51 | ||
52 | static unsigned int mode_from_disp_size PARAMS ((unsigned int)); | |
847f7ad4 AM |
53 | static int fits_in_signed_byte PARAMS ((offsetT)); |
54 | static int fits_in_unsigned_byte PARAMS ((offsetT)); | |
55 | static int fits_in_unsigned_word PARAMS ((offsetT)); | |
56 | static int fits_in_signed_word PARAMS ((offsetT)); | |
57 | static int smallest_imm_type PARAMS ((offsetT)); | |
58 | static offsetT offset_in_range PARAMS ((offsetT, int)); | |
252b5132 RH |
59 | static int add_prefix PARAMS ((unsigned int)); |
60 | static void set_16bit_code_flag PARAMS ((int)); | |
47926f60 | 61 | static void set_16bit_gcc_code_flag PARAMS ((int)); |
252b5132 | 62 | static void set_intel_syntax PARAMS ((int)); |
e413e4e9 | 63 | static void set_cpu_arch PARAMS ((int)); |
252b5132 RH |
64 | |
65 | #ifdef BFD_ASSEMBLER | |
66 | static bfd_reloc_code_real_type reloc | |
67 | PARAMS ((int, int, bfd_reloc_code_real_type)); | |
68 | #endif | |
69 | ||
70 | /* 'md_assemble ()' gathers together information and puts it into a | |
47926f60 | 71 | i386_insn. */ |
252b5132 | 72 | |
520dc8e8 AM |
73 | union i386_op |
74 | { | |
75 | expressionS *disps; | |
76 | expressionS *imms; | |
77 | const reg_entry *regs; | |
78 | }; | |
79 | ||
252b5132 RH |
80 | struct _i386_insn |
81 | { | |
47926f60 | 82 | /* TM holds the template for the insn were currently assembling. */ |
252b5132 RH |
83 | template tm; |
84 | ||
85 | /* SUFFIX holds the instruction mnemonic suffix if given. | |
86 | (e.g. 'l' for 'movl') */ | |
87 | char suffix; | |
88 | ||
47926f60 | 89 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
90 | unsigned int operands; |
91 | ||
92 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
93 | of given register, displacement, memory operands and immediate | |
47926f60 | 94 | operands. */ |
252b5132 RH |
95 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
96 | ||
97 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 98 | use OP[i] for the corresponding operand. */ |
252b5132 RH |
99 | unsigned int types[MAX_OPERANDS]; |
100 | ||
520dc8e8 AM |
101 | /* Displacement expression, immediate expression, or register for each |
102 | operand. */ | |
103 | union i386_op op[MAX_OPERANDS]; | |
252b5132 RH |
104 | |
105 | /* Relocation type for operand */ | |
106 | #ifdef BFD_ASSEMBLER | |
107 | enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS]; | |
108 | #else | |
109 | int disp_reloc[MAX_OPERANDS]; | |
110 | #endif | |
111 | ||
252b5132 RH |
112 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
113 | the base index byte below. */ | |
114 | const reg_entry *base_reg; | |
115 | const reg_entry *index_reg; | |
116 | unsigned int log2_scale_factor; | |
117 | ||
118 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 119 | explicit segment overrides are given. */ |
252b5132 RH |
120 | const seg_entry *seg[2]; /* segments for memory operands (if given) */ |
121 | ||
122 | /* PREFIX holds all the given prefix opcodes (usually null). | |
123 | PREFIXES is the number of prefix opcodes. */ | |
124 | unsigned int prefixes; | |
125 | unsigned char prefix[MAX_PREFIXES]; | |
126 | ||
127 | /* RM and SIB are the modrm byte and the sib byte where the | |
128 | addressing modes of this insn are encoded. */ | |
129 | ||
130 | modrm_byte rm; | |
131 | sib_byte sib; | |
132 | }; | |
133 | ||
134 | typedef struct _i386_insn i386_insn; | |
135 | ||
136 | /* List of chars besides those in app.c:symbol_chars that can start an | |
137 | operand. Used to prevent the scrubber eating vital white-space. */ | |
138 | #ifdef LEX_AT | |
139 | const char extra_symbol_chars[] = "*%-(@"; | |
140 | #else | |
141 | const char extra_symbol_chars[] = "*%-("; | |
142 | #endif | |
143 | ||
144 | /* This array holds the chars that always start a comment. If the | |
145 | pre-processor is disabled, these aren't very useful */ | |
60bcf0fa | 146 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) |
252b5132 RH |
147 | /* Putting '/' here makes it impossible to use the divide operator. |
148 | However, we need it for compatibility with SVR4 systems. */ | |
149 | const char comment_chars[] = "#/"; | |
150 | #define PREFIX_SEPARATOR '\\' | |
151 | #else | |
152 | const char comment_chars[] = "#"; | |
153 | #define PREFIX_SEPARATOR '/' | |
154 | #endif | |
155 | ||
156 | /* This array holds the chars that only start a comment at the beginning of | |
157 | a line. If the line seems to have the form '# 123 filename' | |
158 | .line and .file directives will appear in the pre-processed output */ | |
159 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
160 | first line of the input file. This is because the compiler outputs | |
47926f60 | 161 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
162 | /* Also note that comments started like this one will always work if |
163 | '/' isn't otherwise defined. */ | |
60bcf0fa | 164 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) |
252b5132 RH |
165 | const char line_comment_chars[] = ""; |
166 | #else | |
167 | const char line_comment_chars[] = "/"; | |
168 | #endif | |
169 | ||
63a0b638 | 170 | const char line_separator_chars[] = ";"; |
252b5132 RH |
171 | |
172 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
173 | const char EXP_CHARS[] = "eE"; | |
174 | ||
175 | /* Chars that mean this number is a floating point constant */ | |
176 | /* As in 0f12.456 */ | |
177 | /* or 0d1.2345e12 */ | |
178 | const char FLT_CHARS[] = "fFdDxX"; | |
179 | ||
180 | /* tables for lexical analysis */ | |
181 | static char mnemonic_chars[256]; | |
182 | static char register_chars[256]; | |
183 | static char operand_chars[256]; | |
184 | static char identifier_chars[256]; | |
185 | static char digit_chars[256]; | |
186 | ||
187 | /* lexical macros */ | |
188 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) | |
189 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
190 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
191 | #define is_space_char(x) ((x) == ' ') | |
192 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
193 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
194 | ||
195 | /* put here all non-digit non-letter charcters that may occur in an operand */ | |
196 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; | |
197 | ||
198 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
199 | effect this we maintain a stack of saved characters that we've smashed | |
200 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 201 | assembler instruction). */ |
252b5132 RH |
202 | static char save_stack[32]; |
203 | static char *save_stack_p; /* stack pointer */ | |
204 | #define END_STRING_AND_SAVE(s) \ | |
205 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
206 | #define RESTORE_END_STRING(s) \ | |
207 | do { *(s) = *--save_stack_p; } while (0) | |
208 | ||
47926f60 | 209 | /* The instruction we're assembling. */ |
252b5132 RH |
210 | static i386_insn i; |
211 | ||
212 | /* Possible templates for current insn. */ | |
213 | static const templates *current_templates; | |
214 | ||
47926f60 | 215 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ |
252b5132 RH |
216 | static expressionS disp_expressions[2], im_expressions[2]; |
217 | ||
47926f60 KH |
218 | /* Current operand we are working on. */ |
219 | static int this_operand; | |
252b5132 | 220 | |
47926f60 KH |
221 | /* 1 if we're writing 16-bit code, |
222 | 0 if 32-bit. */ | |
223 | static int flag_16bit_code; | |
252b5132 | 224 | |
47926f60 KH |
225 | /* 1 for intel syntax, |
226 | 0 if att syntax. */ | |
227 | static int intel_syntax = 0; | |
252b5132 | 228 | |
47926f60 KH |
229 | /* 1 if register prefix % not required. */ |
230 | static int allow_naked_reg = 0; | |
252b5132 | 231 | |
47926f60 KH |
232 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
233 | leave, push, and pop instructions so that gcc has the same stack | |
234 | frame as in 32 bit mode. */ | |
235 | static char stackop_size = '\0'; | |
eecb386c | 236 | |
47926f60 KH |
237 | /* Non-zero to quieten some warnings. */ |
238 | static int quiet_warnings = 0; | |
a38cf1db | 239 | |
47926f60 KH |
240 | /* CPU name. */ |
241 | static const char *cpu_arch_name = NULL; | |
a38cf1db | 242 | |
47926f60 KH |
243 | /* CPU feature flags. */ |
244 | static unsigned int cpu_arch_flags = 0; | |
a38cf1db | 245 | |
252b5132 RH |
246 | /* Interface to relax_segment. |
247 | There are 2 relax states for 386 jump insns: one for conditional & | |
a217f122 AM |
248 | one for unconditional jumps. This is because these two types of |
249 | jumps add different sizes to frags when we're figuring out what | |
252b5132 RH |
250 | sort of jump to choose to reach a given label. */ |
251 | ||
47926f60 KH |
252 | /* Types. */ |
253 | #define COND_JUMP 1 /* Conditional jump. */ | |
254 | #define UNCOND_JUMP 2 /* Unconditional jump. */ | |
255 | /* Sizes. */ | |
252b5132 RH |
256 | #define CODE16 1 |
257 | #define SMALL 0 | |
258 | #define SMALL16 (SMALL|CODE16) | |
259 | #define BIG 2 | |
260 | #define BIG16 (BIG|CODE16) | |
261 | ||
262 | #ifndef INLINE | |
263 | #ifdef __GNUC__ | |
264 | #define INLINE __inline__ | |
265 | #else | |
266 | #define INLINE | |
267 | #endif | |
268 | #endif | |
269 | ||
270 | #define ENCODE_RELAX_STATE(type,size) \ | |
271 | ((relax_substateT)((type<<2) | (size))) | |
272 | #define SIZE_FROM_RELAX_STATE(s) \ | |
273 | ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) ) | |
274 | ||
275 | /* This table is used by relax_frag to promote short jumps to long | |
276 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
277 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
278 | don't allow a short jump in a 32 bit code segment to be promoted to | |
279 | a 16 bit offset jump because it's slower (requires data size | |
280 | prefix), and doesn't work, unless the destination is in the bottom | |
281 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
282 | ||
283 | const relax_typeS md_relax_table[] = | |
284 | { | |
24eab124 AM |
285 | /* The fields are: |
286 | 1) most positive reach of this state, | |
287 | 2) most negative reach of this state, | |
288 | 3) how many bytes this mode will add to the size of the current frag | |
289 | 4) which index into the table to try if we can't fit into this one. | |
290 | */ | |
252b5132 RH |
291 | {1, 1, 0, 0}, |
292 | {1, 1, 0, 0}, | |
293 | {1, 1, 0, 0}, | |
294 | {1, 1, 0, 0}, | |
295 | ||
296 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
297 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
298 | /* dword conditionals adds 4 bytes to frag: | |
299 | 1 extra opcode byte, 3 extra displacement bytes. */ | |
300 | {0, 0, 4, 0}, | |
301 | /* word conditionals add 2 bytes to frag: | |
302 | 1 extra opcode byte, 1 extra displacement byte. */ | |
303 | {0, 0, 2, 0}, | |
304 | ||
305 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, | |
306 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
307 | /* dword jmp adds 3 bytes to frag: | |
308 | 0 extra opcode bytes, 3 extra displacement bytes. */ | |
309 | {0, 0, 3, 0}, | |
310 | /* word jmp adds 1 byte to frag: | |
311 | 0 extra opcode bytes, 1 extra displacement byte. */ | |
312 | {0, 0, 1, 0} | |
313 | ||
314 | }; | |
315 | ||
e413e4e9 AM |
316 | static const arch_entry cpu_arch[] = { |
317 | {"i8086", Cpu086 }, | |
318 | {"i186", Cpu086|Cpu186 }, | |
319 | {"i286", Cpu086|Cpu186|Cpu286 }, | |
320 | {"i386", Cpu086|Cpu186|Cpu286|Cpu386 }, | |
321 | {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 }, | |
322 | {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
323 | {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
324 | {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
325 | {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
326 | {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX|Cpu3dnow }, | |
327 | {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|Cpu3dnow }, | |
328 | {NULL, 0 } | |
329 | }; | |
330 | ||
252b5132 RH |
331 | void |
332 | i386_align_code (fragP, count) | |
333 | fragS *fragP; | |
334 | int count; | |
335 | { | |
336 | /* Various efficient no-op patterns for aligning code labels. */ | |
47926f60 | 337 | /* Note: Don't try to assemble the instructions in the comments. */ |
252b5132 RH |
338 | /* 0L and 0w are not legal */ |
339 | static const char f32_1[] = | |
340 | {0x90}; /* nop */ | |
341 | static const char f32_2[] = | |
342 | {0x89,0xf6}; /* movl %esi,%esi */ | |
343 | static const char f32_3[] = | |
344 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
345 | static const char f32_4[] = | |
346 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
347 | static const char f32_5[] = | |
348 | {0x90, /* nop */ | |
349 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
350 | static const char f32_6[] = | |
351 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
352 | static const char f32_7[] = | |
353 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
354 | static const char f32_8[] = | |
355 | {0x90, /* nop */ | |
356 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
357 | static const char f32_9[] = | |
358 | {0x89,0xf6, /* movl %esi,%esi */ | |
359 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
360 | static const char f32_10[] = | |
361 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
362 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
363 | static const char f32_11[] = | |
364 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
365 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
366 | static const char f32_12[] = | |
367 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
368 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
369 | static const char f32_13[] = | |
370 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
371 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
372 | static const char f32_14[] = | |
373 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
374 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
375 | static const char f32_15[] = | |
376 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
377 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
c3332e24 AM |
378 | static const char f16_3[] = |
379 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
380 | static const char f16_4[] = |
381 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
382 | static const char f16_5[] = | |
383 | {0x90, /* nop */ | |
384 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
385 | static const char f16_6[] = | |
386 | {0x89,0xf6, /* mov %si,%si */ | |
387 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
388 | static const char f16_7[] = | |
389 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
390 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
391 | static const char f16_8[] = | |
392 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
393 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
394 | static const char *const f32_patt[] = { | |
395 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
396 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
397 | }; | |
398 | static const char *const f16_patt[] = { | |
c3332e24 | 399 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, |
252b5132 RH |
400 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 |
401 | }; | |
402 | ||
403 | if (count > 0 && count <= 15) | |
404 | { | |
405 | if (flag_16bit_code) | |
406 | { | |
47926f60 KH |
407 | memcpy (fragP->fr_literal + fragP->fr_fix, |
408 | f16_patt[count - 1], count); | |
409 | if (count > 8) | |
410 | /* Adjust jump offset. */ | |
252b5132 RH |
411 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; |
412 | } | |
413 | else | |
47926f60 KH |
414 | memcpy (fragP->fr_literal + fragP->fr_fix, |
415 | f32_patt[count - 1], count); | |
252b5132 RH |
416 | fragP->fr_var = count; |
417 | } | |
418 | } | |
419 | ||
420 | static char *output_invalid PARAMS ((int c)); | |
421 | static int i386_operand PARAMS ((char *operand_string)); | |
422 | static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); | |
423 | static const reg_entry *parse_register PARAMS ((char *reg_string, | |
424 | char **end_op)); | |
425 | ||
426 | #ifndef I386COFF | |
427 | static void s_bss PARAMS ((int)); | |
428 | #endif | |
429 | ||
430 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ | |
431 | ||
432 | static INLINE unsigned int | |
433 | mode_from_disp_size (t) | |
434 | unsigned int t; | |
435 | { | |
47926f60 | 436 | return (t & Disp8) ? 1 : (t & (Disp16 | Disp32)) ? 2 : 0; |
252b5132 RH |
437 | } |
438 | ||
439 | static INLINE int | |
440 | fits_in_signed_byte (num) | |
847f7ad4 | 441 | offsetT num; |
252b5132 RH |
442 | { |
443 | return (num >= -128) && (num <= 127); | |
47926f60 | 444 | } |
252b5132 RH |
445 | |
446 | static INLINE int | |
447 | fits_in_unsigned_byte (num) | |
847f7ad4 | 448 | offsetT num; |
252b5132 RH |
449 | { |
450 | return (num & 0xff) == num; | |
47926f60 | 451 | } |
252b5132 RH |
452 | |
453 | static INLINE int | |
454 | fits_in_unsigned_word (num) | |
847f7ad4 | 455 | offsetT num; |
252b5132 RH |
456 | { |
457 | return (num & 0xffff) == num; | |
47926f60 | 458 | } |
252b5132 RH |
459 | |
460 | static INLINE int | |
461 | fits_in_signed_word (num) | |
847f7ad4 | 462 | offsetT num; |
252b5132 RH |
463 | { |
464 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 465 | } |
252b5132 RH |
466 | |
467 | static int | |
468 | smallest_imm_type (num) | |
847f7ad4 | 469 | offsetT num; |
252b5132 | 470 | { |
e413e4e9 | 471 | if (cpu_arch_flags != 0 |
47926f60 | 472 | && cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486)) |
e413e4e9 AM |
473 | { |
474 | /* This code is disabled on the 486 because all the Imm1 forms | |
475 | in the opcode table are slower on the i486. They're the | |
476 | versions with the implicitly specified single-position | |
477 | displacement, which has another syntax if you really want to | |
478 | use that form. */ | |
479 | if (num == 1) | |
480 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32; | |
481 | } | |
252b5132 RH |
482 | return (fits_in_signed_byte (num) |
483 | ? (Imm8S | Imm8 | Imm16 | Imm32) | |
484 | : fits_in_unsigned_byte (num) | |
485 | ? (Imm8 | Imm16 | Imm32) | |
486 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
487 | ? (Imm16 | Imm32) | |
488 | : (Imm32)); | |
47926f60 | 489 | } |
252b5132 | 490 | |
847f7ad4 AM |
491 | static offsetT |
492 | offset_in_range (val, size) | |
493 | offsetT val; | |
494 | int size; | |
495 | { | |
508866be | 496 | addressT mask; |
ba2adb93 | 497 | |
847f7ad4 AM |
498 | switch (size) |
499 | { | |
508866be L |
500 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
501 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 502 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
47926f60 | 503 | default: abort (); |
847f7ad4 AM |
504 | } |
505 | ||
ba2adb93 | 506 | /* If BFD64, sign extend val. */ |
47926f60 | 507 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
508866be | 508 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); |
ba2adb93 | 509 | |
47926f60 | 510 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
511 | { |
512 | char buf1[40], buf2[40]; | |
513 | ||
514 | sprint_value (buf1, val); | |
515 | sprint_value (buf2, val & mask); | |
516 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
517 | } | |
518 | return val & mask; | |
519 | } | |
520 | ||
252b5132 RH |
521 | /* Returns 0 if attempting to add a prefix where one from the same |
522 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
523 | added. */ | |
524 | static int | |
525 | add_prefix (prefix) | |
526 | unsigned int prefix; | |
527 | { | |
528 | int ret = 1; | |
529 | int q; | |
530 | ||
531 | switch (prefix) | |
532 | { | |
533 | default: | |
534 | abort (); | |
535 | ||
536 | case CS_PREFIX_OPCODE: | |
537 | case DS_PREFIX_OPCODE: | |
538 | case ES_PREFIX_OPCODE: | |
539 | case FS_PREFIX_OPCODE: | |
540 | case GS_PREFIX_OPCODE: | |
541 | case SS_PREFIX_OPCODE: | |
542 | q = SEG_PREFIX; | |
543 | break; | |
544 | ||
545 | case REPNE_PREFIX_OPCODE: | |
546 | case REPE_PREFIX_OPCODE: | |
547 | ret = 2; | |
548 | /* fall thru */ | |
549 | case LOCK_PREFIX_OPCODE: | |
550 | q = LOCKREP_PREFIX; | |
551 | break; | |
552 | ||
553 | case FWAIT_OPCODE: | |
554 | q = WAIT_PREFIX; | |
555 | break; | |
556 | ||
557 | case ADDR_PREFIX_OPCODE: | |
558 | q = ADDR_PREFIX; | |
559 | break; | |
560 | ||
561 | case DATA_PREFIX_OPCODE: | |
562 | q = DATA_PREFIX; | |
563 | break; | |
564 | } | |
565 | ||
566 | if (i.prefix[q]) | |
567 | { | |
568 | as_bad (_("same type of prefix used twice")); | |
569 | return 0; | |
570 | } | |
571 | ||
572 | i.prefixes += 1; | |
573 | i.prefix[q] = prefix; | |
574 | return ret; | |
575 | } | |
576 | ||
577 | static void | |
578 | set_16bit_code_flag (new_16bit_code_flag) | |
eecb386c AM |
579 | int new_16bit_code_flag; |
580 | { | |
581 | flag_16bit_code = new_16bit_code_flag; | |
582 | stackop_size = '\0'; | |
583 | } | |
584 | ||
585 | static void | |
586 | set_16bit_gcc_code_flag (new_16bit_code_flag) | |
587 | int new_16bit_code_flag; | |
252b5132 RH |
588 | { |
589 | flag_16bit_code = new_16bit_code_flag; | |
eecb386c | 590 | stackop_size = new_16bit_code_flag ? 'l' : '\0'; |
252b5132 RH |
591 | } |
592 | ||
593 | static void | |
594 | set_intel_syntax (syntax_flag) | |
eecb386c | 595 | int syntax_flag; |
252b5132 RH |
596 | { |
597 | /* Find out if register prefixing is specified. */ | |
598 | int ask_naked_reg = 0; | |
599 | ||
600 | SKIP_WHITESPACE (); | |
601 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
602 | { | |
603 | char *string = input_line_pointer; | |
604 | int e = get_symbol_end (); | |
605 | ||
47926f60 | 606 | if (strcmp (string, "prefix") == 0) |
252b5132 | 607 | ask_naked_reg = 1; |
47926f60 | 608 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
609 | ask_naked_reg = -1; |
610 | else | |
d0b47220 | 611 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
612 | *input_line_pointer = e; |
613 | } | |
614 | demand_empty_rest_of_line (); | |
c3332e24 | 615 | |
252b5132 RH |
616 | intel_syntax = syntax_flag; |
617 | ||
618 | if (ask_naked_reg == 0) | |
619 | { | |
620 | #ifdef BFD_ASSEMBLER | |
621 | allow_naked_reg = (intel_syntax | |
24eab124 | 622 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); |
252b5132 | 623 | #else |
47926f60 KH |
624 | /* Conservative default. */ |
625 | allow_naked_reg = 0; | |
252b5132 RH |
626 | #endif |
627 | } | |
628 | else | |
629 | allow_naked_reg = (ask_naked_reg < 0); | |
630 | } | |
631 | ||
e413e4e9 AM |
632 | static void |
633 | set_cpu_arch (dummy) | |
47926f60 | 634 | int dummy ATTRIBUTE_UNUSED; |
e413e4e9 | 635 | { |
47926f60 | 636 | SKIP_WHITESPACE (); |
e413e4e9 AM |
637 | |
638 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
639 | { | |
640 | char *string = input_line_pointer; | |
641 | int e = get_symbol_end (); | |
642 | int i; | |
643 | ||
644 | for (i = 0; cpu_arch[i].name; i++) | |
645 | { | |
646 | if (strcmp (string, cpu_arch[i].name) == 0) | |
647 | { | |
648 | cpu_arch_name = cpu_arch[i].name; | |
649 | cpu_arch_flags = cpu_arch[i].flags; | |
650 | break; | |
651 | } | |
652 | } | |
653 | if (!cpu_arch[i].name) | |
654 | as_bad (_("no such architecture: `%s'"), string); | |
655 | ||
656 | *input_line_pointer = e; | |
657 | } | |
658 | else | |
659 | as_bad (_("missing cpu architecture")); | |
660 | ||
661 | demand_empty_rest_of_line (); | |
662 | } | |
663 | ||
252b5132 RH |
664 | const pseudo_typeS md_pseudo_table[] = |
665 | { | |
252b5132 RH |
666 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
667 | {"align", s_align_bytes, 0}, | |
668 | #else | |
669 | {"align", s_align_ptwo, 0}, | |
e413e4e9 AM |
670 | #endif |
671 | {"arch", set_cpu_arch, 0}, | |
672 | #ifndef I386COFF | |
673 | {"bss", s_bss, 0}, | |
252b5132 RH |
674 | #endif |
675 | {"ffloat", float_cons, 'f'}, | |
676 | {"dfloat", float_cons, 'd'}, | |
677 | {"tfloat", float_cons, 'x'}, | |
678 | {"value", cons, 2}, | |
679 | {"noopt", s_ignore, 0}, | |
680 | {"optim", s_ignore, 0}, | |
eecb386c | 681 | {"code16gcc", set_16bit_gcc_code_flag, 1}, |
252b5132 RH |
682 | {"code16", set_16bit_code_flag, 1}, |
683 | {"code32", set_16bit_code_flag, 0}, | |
684 | {"intel_syntax", set_intel_syntax, 1}, | |
685 | {"att_syntax", set_intel_syntax, 0}, | |
686 | {0, 0, 0} | |
687 | }; | |
688 | ||
47926f60 | 689 | /* For interface with expression (). */ |
252b5132 RH |
690 | extern char *input_line_pointer; |
691 | ||
47926f60 | 692 | /* Hash table for instruction mnemonic lookup. */ |
252b5132 | 693 | static struct hash_control *op_hash; |
47926f60 KH |
694 | |
695 | /* Hash table for register lookup. */ | |
252b5132 RH |
696 | static struct hash_control *reg_hash; |
697 | \f | |
252b5132 RH |
698 | void |
699 | md_begin () | |
700 | { | |
701 | const char *hash_err; | |
702 | ||
47926f60 | 703 | /* Initialize op_hash hash table. */ |
252b5132 RH |
704 | op_hash = hash_new (); |
705 | ||
706 | { | |
707 | register const template *optab; | |
708 | register templates *core_optab; | |
709 | ||
47926f60 KH |
710 | /* Setup for loop. */ |
711 | optab = i386_optab; | |
252b5132 RH |
712 | core_optab = (templates *) xmalloc (sizeof (templates)); |
713 | core_optab->start = optab; | |
714 | ||
715 | while (1) | |
716 | { | |
717 | ++optab; | |
718 | if (optab->name == NULL | |
719 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
720 | { | |
721 | /* different name --> ship out current template list; | |
47926f60 | 722 | add to hash table; & begin anew. */ |
252b5132 RH |
723 | core_optab->end = optab; |
724 | hash_err = hash_insert (op_hash, | |
725 | (optab - 1)->name, | |
726 | (PTR) core_optab); | |
727 | if (hash_err) | |
728 | { | |
729 | hash_error: | |
730 | as_fatal (_("Internal Error: Can't hash %s: %s"), | |
731 | (optab - 1)->name, | |
732 | hash_err); | |
733 | } | |
734 | if (optab->name == NULL) | |
735 | break; | |
736 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
737 | core_optab->start = optab; | |
738 | } | |
739 | } | |
740 | } | |
741 | ||
47926f60 | 742 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
743 | reg_hash = hash_new (); |
744 | { | |
745 | register const reg_entry *regtab; | |
746 | ||
747 | for (regtab = i386_regtab; | |
748 | regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); | |
749 | regtab++) | |
750 | { | |
751 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); | |
752 | if (hash_err) | |
753 | goto hash_error; | |
754 | } | |
755 | } | |
756 | ||
47926f60 | 757 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 RH |
758 | { |
759 | register int c; | |
760 | register char *p; | |
761 | ||
762 | for (c = 0; c < 256; c++) | |
763 | { | |
764 | if (isdigit (c)) | |
765 | { | |
766 | digit_chars[c] = c; | |
767 | mnemonic_chars[c] = c; | |
768 | register_chars[c] = c; | |
769 | operand_chars[c] = c; | |
770 | } | |
771 | else if (islower (c)) | |
772 | { | |
773 | mnemonic_chars[c] = c; | |
774 | register_chars[c] = c; | |
775 | operand_chars[c] = c; | |
776 | } | |
777 | else if (isupper (c)) | |
778 | { | |
779 | mnemonic_chars[c] = tolower (c); | |
780 | register_chars[c] = mnemonic_chars[c]; | |
781 | operand_chars[c] = c; | |
782 | } | |
783 | ||
784 | if (isalpha (c) || isdigit (c)) | |
785 | identifier_chars[c] = c; | |
786 | else if (c >= 128) | |
787 | { | |
788 | identifier_chars[c] = c; | |
789 | operand_chars[c] = c; | |
790 | } | |
791 | } | |
792 | ||
793 | #ifdef LEX_AT | |
794 | identifier_chars['@'] = '@'; | |
795 | #endif | |
252b5132 RH |
796 | digit_chars['-'] = '-'; |
797 | identifier_chars['_'] = '_'; | |
798 | identifier_chars['.'] = '.'; | |
799 | ||
800 | for (p = operand_special_chars; *p != '\0'; p++) | |
801 | operand_chars[(unsigned char) *p] = *p; | |
802 | } | |
803 | ||
804 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
805 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
806 | { | |
807 | record_alignment (text_section, 2); | |
808 | record_alignment (data_section, 2); | |
809 | record_alignment (bss_section, 2); | |
810 | } | |
811 | #endif | |
812 | } | |
813 | ||
814 | void | |
815 | i386_print_statistics (file) | |
816 | FILE *file; | |
817 | { | |
818 | hash_print_statistics (file, "i386 opcode", op_hash); | |
819 | hash_print_statistics (file, "i386 register", reg_hash); | |
820 | } | |
821 | \f | |
252b5132 RH |
822 | #ifdef DEBUG386 |
823 | ||
824 | /* debugging routines for md_assemble */ | |
825 | static void pi PARAMS ((char *, i386_insn *)); | |
826 | static void pte PARAMS ((template *)); | |
827 | static void pt PARAMS ((unsigned int)); | |
828 | static void pe PARAMS ((expressionS *)); | |
829 | static void ps PARAMS ((symbolS *)); | |
830 | ||
831 | static void | |
832 | pi (line, x) | |
833 | char *line; | |
834 | i386_insn *x; | |
835 | { | |
836 | register template *p; | |
837 | int i; | |
838 | ||
839 | fprintf (stdout, "%s: template ", line); | |
840 | pte (&x->tm); | |
841 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x", | |
842 | x->rm.mode, x->rm.reg, x->rm.regmem); | |
843 | fprintf (stdout, " base %x index %x scale %x\n", | |
844 | x->bi.base, x->bi.index, x->bi.scale); | |
845 | for (i = 0; i < x->operands; i++) | |
846 | { | |
847 | fprintf (stdout, " #%d: ", i + 1); | |
848 | pt (x->types[i]); | |
849 | fprintf (stdout, "\n"); | |
850 | if (x->types[i] | |
3f4438ab | 851 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) |
520dc8e8 | 852 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
252b5132 | 853 | if (x->types[i] & Imm) |
520dc8e8 | 854 | pe (x->op[i].imms); |
252b5132 | 855 | if (x->types[i] & Disp) |
520dc8e8 | 856 | pe (x->op[i].disps); |
252b5132 RH |
857 | } |
858 | } | |
859 | ||
860 | static void | |
861 | pte (t) | |
862 | template *t; | |
863 | { | |
864 | int i; | |
865 | fprintf (stdout, " %d operands ", t->operands); | |
47926f60 | 866 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
867 | if (t->extension_opcode != None) |
868 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
869 | if (t->opcode_modifier & D) | |
870 | fprintf (stdout, "D"); | |
871 | if (t->opcode_modifier & W) | |
872 | fprintf (stdout, "W"); | |
873 | fprintf (stdout, "\n"); | |
874 | for (i = 0; i < t->operands; i++) | |
875 | { | |
876 | fprintf (stdout, " #%d type ", i + 1); | |
877 | pt (t->operand_types[i]); | |
878 | fprintf (stdout, "\n"); | |
879 | } | |
880 | } | |
881 | ||
882 | static void | |
883 | pe (e) | |
884 | expressionS *e; | |
885 | { | |
24eab124 | 886 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
887 | fprintf (stdout, " add_number %ld (%lx)\n", |
888 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
889 | if (e->X_add_symbol) |
890 | { | |
891 | fprintf (stdout, " add_symbol "); | |
892 | ps (e->X_add_symbol); | |
893 | fprintf (stdout, "\n"); | |
894 | } | |
895 | if (e->X_op_symbol) | |
896 | { | |
897 | fprintf (stdout, " op_symbol "); | |
898 | ps (e->X_op_symbol); | |
899 | fprintf (stdout, "\n"); | |
900 | } | |
901 | } | |
902 | ||
903 | static void | |
904 | ps (s) | |
905 | symbolS *s; | |
906 | { | |
907 | fprintf (stdout, "%s type %s%s", | |
908 | S_GET_NAME (s), | |
909 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
910 | segment_name (S_GET_SEGMENT (s))); | |
911 | } | |
912 | ||
913 | struct type_name | |
914 | { | |
915 | unsigned int mask; | |
916 | char *tname; | |
917 | } | |
918 | ||
919 | type_names[] = | |
920 | { | |
921 | { Reg8, "r8" }, | |
922 | { Reg16, "r16" }, | |
923 | { Reg32, "r32" }, | |
924 | { Imm8, "i8" }, | |
925 | { Imm8S, "i8s" }, | |
926 | { Imm16, "i16" }, | |
927 | { Imm32, "i32" }, | |
928 | { Imm1, "i1" }, | |
929 | { BaseIndex, "BaseIndex" }, | |
930 | { Disp8, "d8" }, | |
931 | { Disp16, "d16" }, | |
932 | { Disp32, "d32" }, | |
933 | { InOutPortReg, "InOutPortReg" }, | |
934 | { ShiftCount, "ShiftCount" }, | |
935 | { Control, "control reg" }, | |
936 | { Test, "test reg" }, | |
937 | { Debug, "debug reg" }, | |
938 | { FloatReg, "FReg" }, | |
939 | { FloatAcc, "FAcc" }, | |
940 | { SReg2, "SReg2" }, | |
941 | { SReg3, "SReg3" }, | |
942 | { Acc, "Acc" }, | |
943 | { JumpAbsolute, "Jump Absolute" }, | |
944 | { RegMMX, "rMMX" }, | |
3f4438ab | 945 | { RegXMM, "rXMM" }, |
252b5132 RH |
946 | { EsSeg, "es" }, |
947 | { 0, "" } | |
948 | }; | |
949 | ||
950 | static void | |
951 | pt (t) | |
952 | unsigned int t; | |
953 | { | |
954 | register struct type_name *ty; | |
955 | ||
956 | if (t == Unknown) | |
957 | { | |
958 | fprintf (stdout, _("Unknown")); | |
959 | } | |
960 | else | |
961 | { | |
962 | for (ty = type_names; ty->mask; ty++) | |
963 | if (t & ty->mask) | |
964 | fprintf (stdout, "%s, ", ty->tname); | |
965 | } | |
966 | fflush (stdout); | |
967 | } | |
968 | ||
969 | #endif /* DEBUG386 */ | |
970 | \f | |
971 | int | |
972 | tc_i386_force_relocation (fixp) | |
973 | struct fix *fixp; | |
974 | { | |
975 | #ifdef BFD_ASSEMBLER | |
976 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
977 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
978 | return 1; | |
979 | return 0; | |
980 | #else | |
981 | /* For COFF */ | |
f6af82bd | 982 | return fixp->fx_r_type == 7; |
252b5132 RH |
983 | #endif |
984 | } | |
985 | ||
986 | #ifdef BFD_ASSEMBLER | |
987 | static bfd_reloc_code_real_type reloc | |
988 | PARAMS ((int, int, bfd_reloc_code_real_type)); | |
989 | ||
990 | static bfd_reloc_code_real_type | |
991 | reloc (size, pcrel, other) | |
992 | int size; | |
993 | int pcrel; | |
994 | bfd_reloc_code_real_type other; | |
995 | { | |
47926f60 KH |
996 | if (other != NO_RELOC) |
997 | return other; | |
252b5132 RH |
998 | |
999 | if (pcrel) | |
1000 | { | |
1001 | switch (size) | |
1002 | { | |
1003 | case 1: return BFD_RELOC_8_PCREL; | |
1004 | case 2: return BFD_RELOC_16_PCREL; | |
1005 | case 4: return BFD_RELOC_32_PCREL; | |
1006 | } | |
d0b47220 | 1007 | as_bad (_("can not do %d byte pc-relative relocation"), size); |
252b5132 RH |
1008 | } |
1009 | else | |
1010 | { | |
1011 | switch (size) | |
1012 | { | |
1013 | case 1: return BFD_RELOC_8; | |
1014 | case 2: return BFD_RELOC_16; | |
1015 | case 4: return BFD_RELOC_32; | |
1016 | } | |
d0b47220 | 1017 | as_bad (_("can not do %d byte relocation"), size); |
252b5132 RH |
1018 | } |
1019 | ||
1020 | return BFD_RELOC_NONE; | |
1021 | } | |
1022 | ||
47926f60 KH |
1023 | /* Here we decide which fixups can be adjusted to make them relative to |
1024 | the beginning of the section instead of the symbol. Basically we need | |
1025 | to make sure that the dynamic relocations are done correctly, so in | |
1026 | some cases we force the original symbol to be used. */ | |
1027 | ||
252b5132 | 1028 | int |
c0c949c7 | 1029 | tc_i386_fix_adjustable (fixP) |
47926f60 | 1030 | fixS *fixP; |
252b5132 | 1031 | { |
6d249963 | 1032 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
79d292aa ILT |
1033 | /* Prevent all adjustments to global symbols, or else dynamic |
1034 | linking will not work correctly. */ | |
b98ef147 AM |
1035 | if (S_IS_EXTERNAL (fixP->fx_addsy) |
1036 | || S_IS_WEAK (fixP->fx_addsy)) | |
252b5132 RH |
1037 | return 0; |
1038 | #endif | |
1039 | /* adjust_reloc_syms doesn't know about the GOT */ | |
1040 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
1041 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
1042 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
1043 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1044 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1045 | return 0; | |
1046 | return 1; | |
1047 | } | |
1048 | #else | |
1049 | #define reloc(SIZE,PCREL,OTHER) 0 | |
1050 | #define BFD_RELOC_16 0 | |
1051 | #define BFD_RELOC_32 0 | |
1052 | #define BFD_RELOC_16_PCREL 0 | |
1053 | #define BFD_RELOC_32_PCREL 0 | |
1054 | #define BFD_RELOC_386_PLT32 0 | |
1055 | #define BFD_RELOC_386_GOT32 0 | |
1056 | #define BFD_RELOC_386_GOTOFF 0 | |
1057 | #endif | |
1058 | ||
47926f60 | 1059 | static int intel_float_operand PARAMS ((char *mnemonic)); |
b4cac588 AM |
1060 | |
1061 | static int | |
252b5132 RH |
1062 | intel_float_operand (mnemonic) |
1063 | char *mnemonic; | |
1064 | { | |
47926f60 | 1065 | if (mnemonic[0] == 'f' && mnemonic[1] == 'i') |
cc5ca5ce | 1066 | return 2; |
252b5132 RH |
1067 | |
1068 | if (mnemonic[0] == 'f') | |
1069 | return 1; | |
1070 | ||
1071 | return 0; | |
1072 | } | |
1073 | ||
1074 | /* This is the guts of the machine-dependent assembler. LINE points to a | |
1075 | machine dependent instruction. This function is supposed to emit | |
1076 | the frags/bytes it assembles to. */ | |
1077 | ||
1078 | void | |
1079 | md_assemble (line) | |
1080 | char *line; | |
1081 | { | |
47926f60 | 1082 | /* Points to template once we've found it. */ |
252b5132 RH |
1083 | const template *t; |
1084 | ||
1085 | /* Count the size of the instruction generated. */ | |
1086 | int insn_size = 0; | |
1087 | ||
1088 | int j; | |
1089 | ||
1090 | char mnemonic[MAX_MNEM_SIZE]; | |
1091 | ||
47926f60 | 1092 | /* Initialize globals. */ |
252b5132 RH |
1093 | memset (&i, '\0', sizeof (i)); |
1094 | for (j = 0; j < MAX_OPERANDS; j++) | |
1095 | i.disp_reloc[j] = NO_RELOC; | |
1096 | memset (disp_expressions, '\0', sizeof (disp_expressions)); | |
1097 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
1098 | save_stack_p = save_stack; /* reset stack pointer */ | |
1099 | ||
1100 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
1101 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 1102 | start of a (possibly prefixed) mnemonic. */ |
252b5132 RH |
1103 | { |
1104 | char *l = line; | |
1105 | char *token_start = l; | |
1106 | char *mnem_p; | |
1107 | ||
47926f60 | 1108 | /* Non-zero if we found a prefix only acceptable with string insns. */ |
252b5132 RH |
1109 | const char *expecting_string_instruction = NULL; |
1110 | ||
1111 | while (1) | |
1112 | { | |
1113 | mnem_p = mnemonic; | |
1114 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
1115 | { | |
1116 | mnem_p++; | |
1117 | if (mnem_p >= mnemonic + sizeof (mnemonic)) | |
1118 | { | |
e413e4e9 | 1119 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1120 | return; |
1121 | } | |
1122 | l++; | |
1123 | } | |
1124 | if (!is_space_char (*l) | |
1125 | && *l != END_OF_INSN | |
1126 | && *l != PREFIX_SEPARATOR) | |
1127 | { | |
1128 | as_bad (_("invalid character %s in mnemonic"), | |
1129 | output_invalid (*l)); | |
1130 | return; | |
1131 | } | |
1132 | if (token_start == l) | |
1133 | { | |
1134 | if (*l == PREFIX_SEPARATOR) | |
1135 | as_bad (_("expecting prefix; got nothing")); | |
1136 | else | |
1137 | as_bad (_("expecting mnemonic; got nothing")); | |
1138 | return; | |
1139 | } | |
1140 | ||
1141 | /* Look up instruction (or prefix) via hash table. */ | |
1142 | current_templates = hash_find (op_hash, mnemonic); | |
1143 | ||
1144 | if (*l != END_OF_INSN | |
1145 | && (! is_space_char (*l) || l[1] != END_OF_INSN) | |
1146 | && current_templates | |
1147 | && (current_templates->start->opcode_modifier & IsPrefix)) | |
1148 | { | |
1149 | /* If we are in 16-bit mode, do not allow addr16 or data16. | |
1150 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
1151 | if ((current_templates->start->opcode_modifier & (Size16 | Size32)) | |
1152 | && (((current_templates->start->opcode_modifier & Size32) != 0) | |
1153 | ^ flag_16bit_code)) | |
1154 | { | |
1155 | as_bad (_("redundant %s prefix"), | |
1156 | current_templates->start->name); | |
1157 | return; | |
1158 | } | |
1159 | /* Add prefix, checking for repeated prefixes. */ | |
1160 | switch (add_prefix (current_templates->start->base_opcode)) | |
1161 | { | |
1162 | case 0: | |
1163 | return; | |
1164 | case 2: | |
47926f60 | 1165 | expecting_string_instruction = current_templates->start->name; |
252b5132 RH |
1166 | break; |
1167 | } | |
1168 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
1169 | token_start = ++l; | |
1170 | } | |
1171 | else | |
1172 | break; | |
1173 | } | |
1174 | ||
1175 | if (!current_templates) | |
1176 | { | |
24eab124 | 1177 | /* See if we can get a match by trimming off a suffix. */ |
252b5132 RH |
1178 | switch (mnem_p[-1]) |
1179 | { | |
252b5132 RH |
1180 | case WORD_MNEM_SUFFIX: |
1181 | case BYTE_MNEM_SUFFIX: | |
1182 | case SHORT_MNEM_SUFFIX: | |
252b5132 | 1183 | case LONG_MNEM_SUFFIX: |
252b5132 RH |
1184 | i.suffix = mnem_p[-1]; |
1185 | mnem_p[-1] = '\0'; | |
1186 | current_templates = hash_find (op_hash, mnemonic); | |
24eab124 AM |
1187 | break; |
1188 | ||
1189 | /* Intel Syntax */ | |
add0c677 | 1190 | case DWORD_MNEM_SUFFIX: |
24eab124 AM |
1191 | if (intel_syntax) |
1192 | { | |
1193 | i.suffix = mnem_p[-1]; | |
1194 | mnem_p[-1] = '\0'; | |
1195 | current_templates = hash_find (op_hash, mnemonic); | |
1196 | break; | |
1197 | } | |
252b5132 RH |
1198 | } |
1199 | if (!current_templates) | |
1200 | { | |
e413e4e9 | 1201 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1202 | return; |
1203 | } | |
1204 | } | |
1205 | ||
e413e4e9 AM |
1206 | /* Check if instruction is supported on specified architecture. */ |
1207 | if (cpu_arch_flags != 0) | |
1208 | { | |
47926f60 | 1209 | if (current_templates->start->cpu_flags & ~cpu_arch_flags) |
e413e4e9 AM |
1210 | { |
1211 | as_warn (_("`%s' is not supported on `%s'"), | |
1212 | current_templates->start->name, cpu_arch_name); | |
1213 | } | |
47926f60 | 1214 | else if ((Cpu386 & ~cpu_arch_flags) && !flag_16bit_code) |
e413e4e9 AM |
1215 | { |
1216 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
1217 | } | |
1218 | } | |
1219 | ||
252b5132 RH |
1220 | /* check for rep/repne without a string instruction */ |
1221 | if (expecting_string_instruction | |
1222 | && !(current_templates->start->opcode_modifier & IsString)) | |
1223 | { | |
1224 | as_bad (_("expecting string instruction after `%s'"), | |
1225 | expecting_string_instruction); | |
1226 | return; | |
1227 | } | |
1228 | ||
47926f60 | 1229 | /* There may be operands to parse. */ |
252b5132 RH |
1230 | if (*l != END_OF_INSN) |
1231 | { | |
1232 | /* parse operands */ | |
1233 | ||
47926f60 | 1234 | /* 1 if operand is pending after ','. */ |
252b5132 RH |
1235 | unsigned int expecting_operand = 0; |
1236 | ||
47926f60 | 1237 | /* Non-zero if operand parens not balanced. */ |
252b5132 RH |
1238 | unsigned int paren_not_balanced; |
1239 | ||
1240 | do | |
1241 | { | |
1242 | /* skip optional white space before operand */ | |
1243 | if (is_space_char (*l)) | |
1244 | ++l; | |
1245 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
1246 | { | |
1247 | as_bad (_("invalid character %s before operand %d"), | |
1248 | output_invalid (*l), | |
1249 | i.operands + 1); | |
1250 | return; | |
1251 | } | |
1252 | token_start = l; /* after white space */ | |
1253 | paren_not_balanced = 0; | |
1254 | while (paren_not_balanced || *l != ',') | |
1255 | { | |
1256 | if (*l == END_OF_INSN) | |
1257 | { | |
1258 | if (paren_not_balanced) | |
1259 | { | |
24eab124 | 1260 | if (!intel_syntax) |
252b5132 RH |
1261 | as_bad (_("unbalanced parenthesis in operand %d."), |
1262 | i.operands + 1); | |
24eab124 | 1263 | else |
252b5132 RH |
1264 | as_bad (_("unbalanced brackets in operand %d."), |
1265 | i.operands + 1); | |
1266 | return; | |
1267 | } | |
1268 | else | |
1269 | break; /* we are done */ | |
1270 | } | |
1271 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
1272 | { | |
1273 | as_bad (_("invalid character %s in operand %d"), | |
1274 | output_invalid (*l), | |
1275 | i.operands + 1); | |
1276 | return; | |
1277 | } | |
24eab124 AM |
1278 | if (!intel_syntax) |
1279 | { | |
252b5132 RH |
1280 | if (*l == '(') |
1281 | ++paren_not_balanced; | |
1282 | if (*l == ')') | |
1283 | --paren_not_balanced; | |
24eab124 AM |
1284 | } |
1285 | else | |
1286 | { | |
252b5132 RH |
1287 | if (*l == '[') |
1288 | ++paren_not_balanced; | |
1289 | if (*l == ']') | |
1290 | --paren_not_balanced; | |
24eab124 | 1291 | } |
252b5132 RH |
1292 | l++; |
1293 | } | |
1294 | if (l != token_start) | |
47926f60 | 1295 | { /* Yes, we've read in another operand. */ |
252b5132 RH |
1296 | unsigned int operand_ok; |
1297 | this_operand = i.operands++; | |
1298 | if (i.operands > MAX_OPERANDS) | |
1299 | { | |
1300 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
1301 | MAX_OPERANDS); | |
1302 | return; | |
1303 | } | |
47926f60 | 1304 | /* Now parse operand adding info to 'i' as we go along. */ |
252b5132 RH |
1305 | END_STRING_AND_SAVE (l); |
1306 | ||
24eab124 | 1307 | if (intel_syntax) |
47926f60 KH |
1308 | operand_ok = |
1309 | i386_intel_operand (token_start, | |
1310 | intel_float_operand (mnemonic)); | |
24eab124 AM |
1311 | else |
1312 | operand_ok = i386_operand (token_start); | |
252b5132 RH |
1313 | |
1314 | RESTORE_END_STRING (l); /* restore old contents */ | |
1315 | if (!operand_ok) | |
1316 | return; | |
1317 | } | |
1318 | else | |
1319 | { | |
1320 | if (expecting_operand) | |
1321 | { | |
1322 | expecting_operand_after_comma: | |
1323 | as_bad (_("expecting operand after ','; got nothing")); | |
1324 | return; | |
1325 | } | |
1326 | if (*l == ',') | |
1327 | { | |
1328 | as_bad (_("expecting operand before ','; got nothing")); | |
1329 | return; | |
1330 | } | |
1331 | } | |
1332 | ||
1333 | /* now *l must be either ',' or END_OF_INSN */ | |
1334 | if (*l == ',') | |
1335 | { | |
1336 | if (*++l == END_OF_INSN) | |
1337 | { /* just skip it, if it's \n complain */ | |
1338 | goto expecting_operand_after_comma; | |
1339 | } | |
1340 | expecting_operand = 1; | |
1341 | } | |
1342 | } | |
1343 | while (*l != END_OF_INSN); /* until we get end of insn */ | |
1344 | } | |
1345 | } | |
1346 | ||
1347 | /* Now we've parsed the mnemonic into a set of templates, and have the | |
1348 | operands at hand. | |
1349 | ||
1350 | Next, we find a template that matches the given insn, | |
1351 | making sure the overlap of the given operands types is consistent | |
47926f60 | 1352 | with the template operand types. */ |
252b5132 RH |
1353 | |
1354 | #define MATCH(overlap, given, template) \ | |
3138f287 AM |
1355 | ((overlap & ~JumpAbsolute) \ |
1356 | && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute))) | |
252b5132 RH |
1357 | |
1358 | /* If given types r0 and r1 are registers they must be of the same type | |
1359 | unless the expected operand type register overlap is null. | |
1360 | Note that Acc in a template matches every size of reg. */ | |
1361 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ | |
1362 | ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \ | |
1363 | ((g0) & Reg) == ((g1) & Reg) || \ | |
1364 | ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) | |
1365 | ||
1366 | { | |
1367 | register unsigned int overlap0, overlap1; | |
252b5132 RH |
1368 | unsigned int overlap2; |
1369 | unsigned int found_reverse_match; | |
1370 | int suffix_check; | |
1371 | ||
cc5ca5ce AM |
1372 | /* All intel opcodes have reversed operands except for "bound" and |
1373 | "enter". We also don't reverse intersegment "jmp" and "call" | |
1374 | instructions with 2 immediate operands so that the immediate segment | |
1375 | precedes the offset, as it does when in AT&T mode. "enter" and the | |
1376 | intersegment "jmp" and "call" instructions are the only ones that | |
1377 | have two immediate operands. */ | |
520dc8e8 | 1378 | if (intel_syntax && i.operands > 1 |
cc5ca5ce AM |
1379 | && (strcmp (mnemonic, "bound") != 0) |
1380 | && !((i.types[0] & Imm) && (i.types[1] & Imm))) | |
252b5132 | 1381 | { |
520dc8e8 | 1382 | union i386_op temp_op; |
24eab124 AM |
1383 | unsigned int temp_type; |
1384 | int xchg1 = 0; | |
ab9da554 | 1385 | int xchg2 = 0; |
252b5132 | 1386 | |
24eab124 AM |
1387 | if (i.operands == 2) |
1388 | { | |
1389 | xchg1 = 0; | |
1390 | xchg2 = 1; | |
1391 | } | |
1392 | else if (i.operands == 3) | |
1393 | { | |
1394 | xchg1 = 0; | |
1395 | xchg2 = 2; | |
1396 | } | |
520dc8e8 AM |
1397 | temp_type = i.types[xchg2]; |
1398 | i.types[xchg2] = i.types[xchg1]; | |
1399 | i.types[xchg1] = temp_type; | |
1400 | temp_op = i.op[xchg2]; | |
1401 | i.op[xchg2] = i.op[xchg1]; | |
1402 | i.op[xchg1] = temp_op; | |
36bf8ab9 AM |
1403 | |
1404 | if (i.mem_operands == 2) | |
1405 | { | |
1406 | const seg_entry *temp_seg; | |
1407 | temp_seg = i.seg[0]; | |
1408 | i.seg[0] = i.seg[1]; | |
1409 | i.seg[1] = temp_seg; | |
1410 | } | |
24eab124 | 1411 | } |
773f551c AM |
1412 | |
1413 | if (i.imm_operands) | |
1414 | { | |
1415 | /* Try to ensure constant immediates are represented in the smallest | |
1416 | opcode possible. */ | |
1417 | char guess_suffix = 0; | |
1418 | int op; | |
1419 | ||
1420 | if (i.suffix) | |
1421 | guess_suffix = i.suffix; | |
1422 | else if (i.reg_operands) | |
1423 | { | |
1424 | /* Figure out a suffix from the last register operand specified. | |
1425 | We can't do this properly yet, ie. excluding InOutPortReg, | |
1426 | but the following works for instructions with immediates. | |
1427 | In any case, we can't set i.suffix yet. */ | |
47926f60 | 1428 | for (op = i.operands; --op >= 0;) |
773f551c AM |
1429 | if (i.types[op] & Reg) |
1430 | { | |
1431 | if (i.types[op] & Reg8) | |
1432 | guess_suffix = BYTE_MNEM_SUFFIX; | |
1433 | else if (i.types[op] & Reg16) | |
1434 | guess_suffix = WORD_MNEM_SUFFIX; | |
1435 | break; | |
1436 | } | |
1437 | } | |
726c5dcd AM |
1438 | else if (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) |
1439 | guess_suffix = WORD_MNEM_SUFFIX; | |
1440 | ||
47926f60 | 1441 | for (op = i.operands; --op >= 0;) |
773f551c AM |
1442 | if ((i.types[op] & Imm) |
1443 | && i.op[op].imms->X_op == O_constant) | |
1444 | { | |
1445 | /* If a suffix is given, this operand may be shortened. */ | |
1446 | switch (guess_suffix) | |
1447 | { | |
1448 | case WORD_MNEM_SUFFIX: | |
1449 | i.types[op] |= Imm16; | |
1450 | break; | |
1451 | case BYTE_MNEM_SUFFIX: | |
1452 | i.types[op] |= Imm16 | Imm8 | Imm8S; | |
1453 | break; | |
1454 | } | |
1455 | ||
1456 | /* If this operand is at most 16 bits, convert it to a | |
1457 | signed 16 bit number before trying to see whether it will | |
1458 | fit in an even smaller size. This allows a 16-bit operand | |
1459 | such as $0xffe0 to be recognised as within Imm8S range. */ | |
1460 | if ((i.types[op] & Imm16) | |
1461 | && (i.op[op].imms->X_add_number & ~(offsetT)0xffff) == 0) | |
1462 | { | |
1463 | i.op[op].imms->X_add_number = | |
1464 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
1465 | } | |
1466 | i.types[op] |= smallest_imm_type ((long) i.op[op].imms->X_add_number); | |
1467 | } | |
1468 | } | |
1469 | ||
45288df1 AM |
1470 | if (i.disp_operands) |
1471 | { | |
1472 | /* Try to use the smallest displacement type too. */ | |
1473 | int op; | |
1474 | ||
47926f60 | 1475 | for (op = i.operands; --op >= 0;) |
45288df1 AM |
1476 | if ((i.types[op] & Disp) |
1477 | && i.op[op].imms->X_op == O_constant) | |
1478 | { | |
1479 | offsetT disp = i.op[op].disps->X_add_number; | |
1480 | ||
1481 | if (i.types[op] & Disp16) | |
1482 | { | |
1483 | /* We know this operand is at most 16 bits, so | |
1484 | convert to a signed 16 bit number before trying | |
1485 | to see whether it will fit in an even smaller | |
1486 | size. */ | |
47926f60 | 1487 | |
45288df1 AM |
1488 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); |
1489 | } | |
1490 | if (fits_in_signed_byte (disp)) | |
1491 | i.types[op] |= Disp8; | |
1492 | } | |
1493 | } | |
1494 | ||
252b5132 RH |
1495 | overlap0 = 0; |
1496 | overlap1 = 0; | |
1497 | overlap2 = 0; | |
1498 | found_reverse_match = 0; | |
1499 | suffix_check = (i.suffix == BYTE_MNEM_SUFFIX | |
1500 | ? No_bSuf | |
1501 | : (i.suffix == WORD_MNEM_SUFFIX | |
1502 | ? No_wSuf | |
1503 | : (i.suffix == SHORT_MNEM_SUFFIX | |
1504 | ? No_sSuf | |
1505 | : (i.suffix == LONG_MNEM_SUFFIX | |
24eab124 | 1506 | ? No_lSuf |
add0c677 | 1507 | : (i.suffix == DWORD_MNEM_SUFFIX |
24eab124 AM |
1508 | ? No_dSuf |
1509 | : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0)))))); | |
252b5132 RH |
1510 | |
1511 | for (t = current_templates->start; | |
1512 | t < current_templates->end; | |
1513 | t++) | |
1514 | { | |
47926f60 | 1515 | /* Must have right number of operands. */ |
252b5132 RH |
1516 | if (i.operands != t->operands) |
1517 | continue; | |
1518 | ||
7f3f1ea2 AM |
1519 | /* Check the suffix, except for some instructions in intel mode. */ |
1520 | if ((t->opcode_modifier & suffix_check) | |
1521 | && !(intel_syntax | |
1522 | && t->base_opcode == 0xd9 | |
1523 | && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */ | |
1524 | || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */ | |
24eab124 | 1525 | continue; |
252b5132 RH |
1526 | |
1527 | else if (!t->operands) | |
47926f60 KH |
1528 | /* 0 operands always matches. */ |
1529 | break; | |
252b5132 RH |
1530 | |
1531 | overlap0 = i.types[0] & t->operand_types[0]; | |
1532 | switch (t->operands) | |
1533 | { | |
1534 | case 1: | |
1535 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])) | |
1536 | continue; | |
1537 | break; | |
1538 | case 2: | |
1539 | case 3: | |
1540 | overlap1 = i.types[1] & t->operand_types[1]; | |
1541 | if (!MATCH (overlap0, i.types[0], t->operand_types[0]) | |
1542 | || !MATCH (overlap1, i.types[1], t->operand_types[1]) | |
1543 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1544 | t->operand_types[0], | |
1545 | overlap1, i.types[1], | |
1546 | t->operand_types[1])) | |
1547 | { | |
47926f60 | 1548 | /* Check if other direction is valid ... */ |
252b5132 RH |
1549 | if ((t->opcode_modifier & (D|FloatD)) == 0) |
1550 | continue; | |
1551 | ||
47926f60 | 1552 | /* Try reversing direction of operands. */ |
252b5132 RH |
1553 | overlap0 = i.types[0] & t->operand_types[1]; |
1554 | overlap1 = i.types[1] & t->operand_types[0]; | |
1555 | if (!MATCH (overlap0, i.types[0], t->operand_types[1]) | |
1556 | || !MATCH (overlap1, i.types[1], t->operand_types[0]) | |
1557 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1558 | t->operand_types[1], | |
1559 | overlap1, i.types[1], | |
1560 | t->operand_types[0])) | |
1561 | { | |
47926f60 | 1562 | /* Does not match either direction. */ |
252b5132 RH |
1563 | continue; |
1564 | } | |
1565 | /* found_reverse_match holds which of D or FloatDR | |
1566 | we've found. */ | |
1567 | found_reverse_match = t->opcode_modifier & (D|FloatDR); | |
1568 | break; | |
1569 | } | |
47926f60 | 1570 | /* Found a forward 2 operand match here. */ |
252b5132 RH |
1571 | if (t->operands == 3) |
1572 | { | |
1573 | /* Here we make use of the fact that there are no | |
1574 | reverse match 3 operand instructions, and all 3 | |
1575 | operand instructions only need to be checked for | |
1576 | register consistency between operands 2 and 3. */ | |
1577 | overlap2 = i.types[2] & t->operand_types[2]; | |
1578 | if (!MATCH (overlap2, i.types[2], t->operand_types[2]) | |
1579 | || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], | |
1580 | t->operand_types[1], | |
1581 | overlap2, i.types[2], | |
24eab124 | 1582 | t->operand_types[2])) |
252b5132 | 1583 | |
24eab124 | 1584 | continue; |
252b5132 | 1585 | } |
47926f60 | 1586 | /* Found either forward/reverse 2 or 3 operand match here: |
252b5132 RH |
1587 | slip through to break */ |
1588 | } | |
47926f60 KH |
1589 | /* We've found a match; break out of loop. */ |
1590 | break; | |
1591 | } /* for (t = ... */ | |
252b5132 | 1592 | if (t == current_templates->end) |
47926f60 KH |
1593 | { |
1594 | /* We found no match. */ | |
252b5132 RH |
1595 | as_bad (_("suffix or operands invalid for `%s'"), |
1596 | current_templates->start->name); | |
1597 | return; | |
1598 | } | |
1599 | ||
a38cf1db | 1600 | if (!quiet_warnings) |
3138f287 | 1601 | { |
a38cf1db AM |
1602 | if (!intel_syntax |
1603 | && ((i.types[0] & JumpAbsolute) | |
1604 | != (t->operand_types[0] & JumpAbsolute))) | |
1605 | { | |
1606 | as_warn (_("indirect %s without `*'"), t->name); | |
1607 | } | |
3138f287 | 1608 | |
a38cf1db AM |
1609 | if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) |
1610 | == (IsPrefix|IgnoreSize)) | |
1611 | { | |
1612 | /* Warn them that a data or address size prefix doesn't | |
1613 | affect assembly of the next line of code. */ | |
1614 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
1615 | } | |
252b5132 RH |
1616 | } |
1617 | ||
1618 | /* Copy the template we found. */ | |
1619 | i.tm = *t; | |
1620 | if (found_reverse_match) | |
1621 | { | |
7f3f1ea2 AM |
1622 | /* If we found a reverse match we must alter the opcode |
1623 | direction bit. found_reverse_match holds bits to change | |
1624 | (different for int & float insns). */ | |
1625 | ||
1626 | i.tm.base_opcode ^= found_reverse_match; | |
1627 | ||
252b5132 RH |
1628 | i.tm.operand_types[0] = t->operand_types[1]; |
1629 | i.tm.operand_types[1] = t->operand_types[0]; | |
1630 | } | |
1631 | ||
d0b47220 AM |
1632 | /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ |
1633 | if (SYSV386_COMPAT | |
7f3f1ea2 AM |
1634 | && intel_syntax |
1635 | && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) | |
1636 | i.tm.base_opcode ^= FloatR; | |
252b5132 RH |
1637 | |
1638 | if (i.tm.opcode_modifier & FWait) | |
1639 | if (! add_prefix (FWAIT_OPCODE)) | |
1640 | return; | |
1641 | ||
1642 | /* Check string instruction segment overrides */ | |
1643 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) | |
1644 | { | |
1645 | int mem_op = (i.types[0] & AnyMem) ? 0 : 1; | |
1646 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) | |
1647 | { | |
1648 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
1649 | { | |
1650 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1651 | i.tm.name, | |
1652 | mem_op + 1); | |
1653 | return; | |
1654 | } | |
1655 | /* There's only ever one segment override allowed per instruction. | |
1656 | This instruction possibly has a legal segment override on the | |
1657 | second operand, so copy the segment to where non-string | |
1658 | instructions store it, allowing common code. */ | |
1659 | i.seg[0] = i.seg[1]; | |
1660 | } | |
1661 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) | |
1662 | { | |
1663 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
1664 | { | |
1665 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1666 | i.tm.name, | |
1667 | mem_op + 2); | |
1668 | return; | |
1669 | } | |
1670 | } | |
1671 | } | |
1672 | ||
1673 | /* If matched instruction specifies an explicit instruction mnemonic | |
1674 | suffix, use it. */ | |
1675 | if (i.tm.opcode_modifier & (Size16 | Size32)) | |
1676 | { | |
1677 | if (i.tm.opcode_modifier & Size16) | |
1678 | i.suffix = WORD_MNEM_SUFFIX; | |
1679 | else | |
add0c677 | 1680 | i.suffix = LONG_MNEM_SUFFIX; |
252b5132 RH |
1681 | } |
1682 | else if (i.reg_operands) | |
1683 | { | |
1684 | /* If there's no instruction mnemonic suffix we try to invent one | |
47926f60 | 1685 | based on register operands. */ |
252b5132 RH |
1686 | if (!i.suffix) |
1687 | { | |
1688 | /* We take i.suffix from the last register operand specified, | |
1689 | Destination register type is more significant than source | |
1690 | register type. */ | |
1691 | int op; | |
47926f60 | 1692 | for (op = i.operands; --op >= 0;) |
cc5ca5ce AM |
1693 | if ((i.types[op] & Reg) |
1694 | && !(i.tm.operand_types[op] & InOutPortReg)) | |
252b5132 RH |
1695 | { |
1696 | i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : | |
1697 | (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : | |
add0c677 | 1698 | LONG_MNEM_SUFFIX); |
252b5132 RH |
1699 | break; |
1700 | } | |
1701 | } | |
1702 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
1703 | { | |
1704 | int op; | |
47926f60 | 1705 | for (op = i.operands; --op >= 0;) |
252b5132 RH |
1706 | { |
1707 | /* If this is an eight bit register, it's OK. If it's | |
1708 | the 16 or 32 bit version of an eight bit register, | |
47926f60 | 1709 | we will just use the low portion, and that's OK too. */ |
252b5132 RH |
1710 | if (i.types[op] & Reg8) |
1711 | continue; | |
1712 | ||
47926f60 | 1713 | /* movzx and movsx should not generate this warning. */ |
24eab124 AM |
1714 | if (intel_syntax |
1715 | && (i.tm.base_opcode == 0xfb7 | |
1716 | || i.tm.base_opcode == 0xfb6 | |
1717 | || i.tm.base_opcode == 0xfbe | |
1718 | || i.tm.base_opcode == 0xfbf)) | |
1719 | continue; | |
252b5132 | 1720 | |
520dc8e8 | 1721 | if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4 |
252b5132 RH |
1722 | #if 0 |
1723 | /* Check that the template allows eight bit regs | |
1724 | This kills insns such as `orb $1,%edx', which | |
1725 | maybe should be allowed. */ | |
1726 | && (i.tm.operand_types[op] & (Reg8|InOutPortReg)) | |
1727 | #endif | |
1728 | ) | |
1729 | { | |
1730 | #if REGISTER_WARNINGS | |
a38cf1db AM |
1731 | if (!quiet_warnings |
1732 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
252b5132 | 1733 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), |
520dc8e8 AM |
1734 | (i.op[op].regs - (i.types[op] & Reg16 ? 8 : 16))->reg_name, |
1735 | i.op[op].regs->reg_name, | |
252b5132 RH |
1736 | i.suffix); |
1737 | #endif | |
1738 | continue; | |
1739 | } | |
1740 | /* Any other register is bad */ | |
3f4438ab AM |
1741 | if (i.types[op] & (Reg | RegMMX | RegXMM |
1742 | | SReg2 | SReg3 | |
1743 | | Control | Debug | Test | |
1744 | | FloatReg | FloatAcc)) | |
252b5132 RH |
1745 | { |
1746 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 1747 | i.op[op].regs->reg_name, |
252b5132 RH |
1748 | i.tm.name, |
1749 | i.suffix); | |
1750 | return; | |
1751 | } | |
1752 | } | |
1753 | } | |
add0c677 | 1754 | else if (i.suffix == LONG_MNEM_SUFFIX) |
252b5132 RH |
1755 | { |
1756 | int op; | |
47926f60 KH |
1757 | |
1758 | for (op = i.operands; --op >= 0;) | |
252b5132 RH |
1759 | /* Reject eight bit registers, except where the template |
1760 | requires them. (eg. movzb) */ | |
1761 | if ((i.types[op] & Reg8) != 0 | |
47926f60 | 1762 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) |
252b5132 RH |
1763 | { |
1764 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 1765 | i.op[op].regs->reg_name, |
252b5132 RH |
1766 | i.tm.name, |
1767 | i.suffix); | |
1768 | return; | |
1769 | } | |
1770 | #if REGISTER_WARNINGS | |
1771 | /* Warn if the e prefix on a general reg is missing. */ | |
a38cf1db AM |
1772 | else if (!quiet_warnings |
1773 | && (i.types[op] & Reg16) != 0 | |
252b5132 RH |
1774 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) |
1775 | { | |
1776 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
520dc8e8 AM |
1777 | (i.op[op].regs + 8)->reg_name, |
1778 | i.op[op].regs->reg_name, | |
252b5132 RH |
1779 | i.suffix); |
1780 | } | |
1781 | #endif | |
1782 | } | |
1783 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
1784 | { | |
1785 | int op; | |
47926f60 | 1786 | for (op = i.operands; --op >= 0;) |
252b5132 RH |
1787 | /* Reject eight bit registers, except where the template |
1788 | requires them. (eg. movzb) */ | |
1789 | if ((i.types[op] & Reg8) != 0 | |
1790 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
1791 | { | |
1792 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 1793 | i.op[op].regs->reg_name, |
252b5132 RH |
1794 | i.tm.name, |
1795 | i.suffix); | |
1796 | return; | |
1797 | } | |
1798 | #if REGISTER_WARNINGS | |
1799 | /* Warn if the e prefix on a general reg is present. */ | |
a38cf1db AM |
1800 | else if (!quiet_warnings |
1801 | && (i.types[op] & Reg32) != 0 | |
252b5132 RH |
1802 | && (i.tm.operand_types[op] & (Reg16|Acc)) != 0) |
1803 | { | |
1804 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
520dc8e8 AM |
1805 | (i.op[op].regs - 8)->reg_name, |
1806 | i.op[op].regs->reg_name, | |
252b5132 RH |
1807 | i.suffix); |
1808 | } | |
1809 | #endif | |
1810 | } | |
1811 | else | |
47926f60 | 1812 | abort (); |
252b5132 | 1813 | } |
eecb386c AM |
1814 | else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix) |
1815 | { | |
1816 | i.suffix = stackop_size; | |
1817 | } | |
252b5132 RH |
1818 | |
1819 | /* Make still unresolved immediate matches conform to size of immediate | |
1820 | given in i.suffix. Note: overlap2 cannot be an immediate! */ | |
1821 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32)) | |
1822 | && overlap0 != Imm8 && overlap0 != Imm8S | |
1823 | && overlap0 != Imm16 && overlap0 != Imm32) | |
1824 | { | |
1825 | if (i.suffix) | |
1826 | { | |
24eab124 AM |
1827 | overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
1828 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); | |
252b5132 RH |
1829 | } |
1830 | else if (overlap0 == (Imm16 | Imm32)) | |
1831 | { | |
24eab124 | 1832 | overlap0 = |
252b5132 RH |
1833 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; |
1834 | } | |
1835 | else | |
1836 | { | |
1837 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); | |
1838 | return; | |
1839 | } | |
1840 | } | |
1841 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32)) | |
1842 | && overlap1 != Imm8 && overlap1 != Imm8S | |
1843 | && overlap1 != Imm16 && overlap1 != Imm32) | |
1844 | { | |
1845 | if (i.suffix) | |
1846 | { | |
24eab124 AM |
1847 | overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
1848 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); | |
252b5132 RH |
1849 | } |
1850 | else if (overlap1 == (Imm16 | Imm32)) | |
1851 | { | |
24eab124 | 1852 | overlap1 = |
252b5132 RH |
1853 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; |
1854 | } | |
1855 | else | |
1856 | { | |
1857 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); | |
1858 | return; | |
1859 | } | |
1860 | } | |
1861 | assert ((overlap2 & Imm) == 0); | |
1862 | ||
1863 | i.types[0] = overlap0; | |
1864 | if (overlap0 & ImplicitRegister) | |
1865 | i.reg_operands--; | |
1866 | if (overlap0 & Imm1) | |
1867 | i.imm_operands = 0; /* kludge for shift insns */ | |
1868 | ||
1869 | i.types[1] = overlap1; | |
1870 | if (overlap1 & ImplicitRegister) | |
1871 | i.reg_operands--; | |
1872 | ||
1873 | i.types[2] = overlap2; | |
1874 | if (overlap2 & ImplicitRegister) | |
1875 | i.reg_operands--; | |
1876 | ||
1877 | /* Finalize opcode. First, we change the opcode based on the operand | |
1878 | size given by i.suffix: We need not change things for byte insns. */ | |
1879 | ||
1880 | if (!i.suffix && (i.tm.opcode_modifier & W)) | |
1881 | { | |
1882 | as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); | |
1883 | return; | |
1884 | } | |
1885 | ||
1886 | /* For movzx and movsx, need to check the register type */ | |
1887 | if (intel_syntax | |
24eab124 | 1888 | && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)) |
252b5132 | 1889 | if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX) |
24eab124 AM |
1890 | { |
1891 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
252b5132 | 1892 | |
520dc8e8 | 1893 | if ((i.op[1].regs->reg_type & Reg16) != 0) |
24eab124 AM |
1894 | if (!add_prefix (prefix)) |
1895 | return; | |
1896 | } | |
252b5132 RH |
1897 | |
1898 | if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
1899 | { | |
1900 | /* It's not a byte, select word/dword operation. */ | |
1901 | if (i.tm.opcode_modifier & W) | |
1902 | { | |
1903 | if (i.tm.opcode_modifier & ShortForm) | |
1904 | i.tm.base_opcode |= 8; | |
1905 | else | |
1906 | i.tm.base_opcode |= 1; | |
1907 | } | |
1908 | /* Now select between word & dword operations via the operand | |
1909 | size prefix, except for instructions that will ignore this | |
1910 | prefix anyway. */ | |
add0c677 | 1911 | if (((intel_syntax && (i.suffix == DWORD_MNEM_SUFFIX)) |
252b5132 RH |
1912 | || i.suffix == LONG_MNEM_SUFFIX) == flag_16bit_code |
1913 | && !(i.tm.opcode_modifier & IgnoreSize)) | |
1914 | { | |
1915 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
1916 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ | |
1917 | prefix = ADDR_PREFIX_OPCODE; | |
1918 | ||
1919 | if (! add_prefix (prefix)) | |
1920 | return; | |
1921 | } | |
1922 | /* Size floating point instruction. */ | |
1923 | if (i.suffix == LONG_MNEM_SUFFIX | |
add0c677 | 1924 | || (intel_syntax && i.suffix == DWORD_MNEM_SUFFIX)) |
252b5132 RH |
1925 | { |
1926 | if (i.tm.opcode_modifier & FloatMF) | |
1927 | i.tm.base_opcode ^= 4; | |
1928 | } | |
252b5132 RH |
1929 | } |
1930 | ||
3f4438ab | 1931 | if (i.tm.opcode_modifier & ImmExt) |
252b5132 | 1932 | { |
3f4438ab AM |
1933 | /* These AMD 3DNow! and Intel Katmai New Instructions have an |
1934 | opcode suffix which is coded in the same place as an 8-bit | |
1935 | immediate field would be. Here we fake an 8-bit immediate | |
1936 | operand from the opcode suffix stored in tm.extension_opcode. */ | |
252b5132 RH |
1937 | |
1938 | expressionS *exp; | |
1939 | ||
47926f60 | 1940 | assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); |
252b5132 RH |
1941 | |
1942 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 1943 | i.op[i.operands].imms = exp; |
252b5132 RH |
1944 | i.types[i.operands++] = Imm8; |
1945 | exp->X_op = O_constant; | |
1946 | exp->X_add_number = i.tm.extension_opcode; | |
1947 | i.tm.extension_opcode = None; | |
1948 | } | |
1949 | ||
47926f60 | 1950 | /* For insns with operands there are more diddles to do to the opcode. */ |
252b5132 RH |
1951 | if (i.operands) |
1952 | { | |
24eab124 | 1953 | /* Default segment register this instruction will use |
252b5132 RH |
1954 | for memory accesses. 0 means unknown. |
1955 | This is only for optimizing out unnecessary segment overrides. */ | |
1956 | const seg_entry *default_seg = 0; | |
1957 | ||
252b5132 RH |
1958 | /* The imul $imm, %reg instruction is converted into |
1959 | imul $imm, %reg, %reg, and the clr %reg instruction | |
1960 | is converted into xor %reg, %reg. */ | |
1961 | if (i.tm.opcode_modifier & regKludge) | |
1962 | { | |
1963 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; | |
47926f60 KH |
1964 | /* Pretend we saw the extra register operand. */ |
1965 | assert (i.op[first_reg_op + 1].regs == 0); | |
1966 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; | |
1967 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
252b5132 RH |
1968 | i.reg_operands = 2; |
1969 | } | |
1970 | ||
1971 | if (i.tm.opcode_modifier & ShortForm) | |
1972 | { | |
47926f60 | 1973 | /* The register or float register operand is in operand 0 or 1. */ |
252b5132 | 1974 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; |
47926f60 | 1975 | /* Register goes in low 3 bits of opcode. */ |
520dc8e8 | 1976 | i.tm.base_opcode |= i.op[op].regs->reg_num; |
a38cf1db | 1977 | if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 RH |
1978 | { |
1979 | /* Warn about some common errors, but press on regardless. | |
1980 | The first case can be generated by gcc (<= 2.8.1). */ | |
1981 | if (i.operands == 2) | |
1982 | { | |
47926f60 | 1983 | /* Reversed arguments on faddp, fsubp, etc. */ |
252b5132 | 1984 | as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, |
520dc8e8 AM |
1985 | i.op[1].regs->reg_name, |
1986 | i.op[0].regs->reg_name); | |
252b5132 RH |
1987 | } |
1988 | else | |
1989 | { | |
47926f60 | 1990 | /* Extraneous `l' suffix on fp insn. */ |
252b5132 | 1991 | as_warn (_("translating to `%s %%%s'"), i.tm.name, |
520dc8e8 | 1992 | i.op[0].regs->reg_name); |
252b5132 RH |
1993 | } |
1994 | } | |
1995 | } | |
1996 | else if (i.tm.opcode_modifier & Modrm) | |
1997 | { | |
1998 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
1999 | must be put into the modrm byte). | |
2000 | Now, we make the modrm & index base bytes based on all the | |
47926f60 | 2001 | info we've collected. */ |
252b5132 RH |
2002 | |
2003 | /* i.reg_operands MUST be the number of real register operands; | |
47926f60 | 2004 | implicit registers do not count. */ |
252b5132 RH |
2005 | if (i.reg_operands == 2) |
2006 | { | |
2007 | unsigned int source, dest; | |
2008 | source = ((i.types[0] | |
3f4438ab AM |
2009 | & (Reg | RegMMX | RegXMM |
2010 | | SReg2 | SReg3 | |
2011 | | Control | Debug | Test)) | |
252b5132 RH |
2012 | ? 0 : 1); |
2013 | dest = source + 1; | |
2014 | ||
252b5132 | 2015 | i.rm.mode = 3; |
3f4438ab AM |
2016 | /* One of the register operands will be encoded in the |
2017 | i.tm.reg field, the other in the combined i.tm.mode | |
2018 | and i.tm.regmem fields. If no form of this | |
2019 | instruction supports a memory destination operand, | |
2020 | then we assume the source operand may sometimes be | |
2021 | a memory operand and so we need to store the | |
2022 | destination in the i.rm.reg field. */ | |
2023 | if ((i.tm.operand_types[dest] & AnyMem) == 0) | |
252b5132 | 2024 | { |
520dc8e8 AM |
2025 | i.rm.reg = i.op[dest].regs->reg_num; |
2026 | i.rm.regmem = i.op[source].regs->reg_num; | |
252b5132 RH |
2027 | } |
2028 | else | |
2029 | { | |
520dc8e8 AM |
2030 | i.rm.reg = i.op[source].regs->reg_num; |
2031 | i.rm.regmem = i.op[dest].regs->reg_num; | |
252b5132 RH |
2032 | } |
2033 | } | |
2034 | else | |
47926f60 | 2035 | { /* If it's not 2 reg operands... */ |
252b5132 RH |
2036 | if (i.mem_operands) |
2037 | { | |
2038 | unsigned int fake_zero_displacement = 0; | |
2039 | unsigned int op = ((i.types[0] & AnyMem) | |
2040 | ? 0 | |
2041 | : (i.types[1] & AnyMem) ? 1 : 2); | |
2042 | ||
2043 | default_seg = &ds; | |
2044 | ||
2045 | if (! i.base_reg) | |
2046 | { | |
2047 | i.rm.mode = 0; | |
2048 | if (! i.disp_operands) | |
2049 | fake_zero_displacement = 1; | |
2050 | if (! i.index_reg) | |
2051 | { | |
47926f60 | 2052 | /* Operand is just <disp> */ |
252b5132 RH |
2053 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) |
2054 | { | |
2055 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2056 | i.types[op] &= ~Disp; | |
2057 | i.types[op] |= Disp16; | |
2058 | } | |
2059 | else | |
2060 | { | |
2061 | i.rm.regmem = NO_BASE_REGISTER; | |
2062 | i.types[op] &= ~Disp; | |
2063 | i.types[op] |= Disp32; | |
2064 | } | |
2065 | } | |
47926f60 | 2066 | else /* ! i.base_reg && i.index_reg */ |
252b5132 RH |
2067 | { |
2068 | i.sib.index = i.index_reg->reg_num; | |
2069 | i.sib.base = NO_BASE_REGISTER; | |
2070 | i.sib.scale = i.log2_scale_factor; | |
2071 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2072 | i.types[op] &= ~Disp; | |
47926f60 | 2073 | i.types[op] |= Disp32; /* Must be 32 bit. */ |
252b5132 RH |
2074 | } |
2075 | } | |
2076 | else if (i.base_reg->reg_type & Reg16) | |
2077 | { | |
2078 | switch (i.base_reg->reg_num) | |
2079 | { | |
47926f60 | 2080 | case 3: /* (%bx) */ |
252b5132 RH |
2081 | if (! i.index_reg) |
2082 | i.rm.regmem = 7; | |
47926f60 | 2083 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ |
252b5132 RH |
2084 | i.rm.regmem = i.index_reg->reg_num - 6; |
2085 | break; | |
47926f60 | 2086 | case 5: /* (%bp) */ |
252b5132 RH |
2087 | default_seg = &ss; |
2088 | if (! i.index_reg) | |
2089 | { | |
2090 | i.rm.regmem = 6; | |
2091 | if ((i.types[op] & Disp) == 0) | |
2092 | { | |
47926f60 | 2093 | /* fake (%bp) into 0(%bp) */ |
252b5132 RH |
2094 | i.types[op] |= Disp8; |
2095 | fake_zero_displacement = 1; | |
2096 | } | |
2097 | } | |
47926f60 | 2098 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ |
252b5132 RH |
2099 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; |
2100 | break; | |
47926f60 | 2101 | default: /* (%si) -> 4 or (%di) -> 5 */ |
252b5132 RH |
2102 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; |
2103 | } | |
2104 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2105 | } | |
47926f60 | 2106 | else /* i.base_reg and 32 bit mode */ |
252b5132 RH |
2107 | { |
2108 | i.rm.regmem = i.base_reg->reg_num; | |
2109 | i.sib.base = i.base_reg->reg_num; | |
2110 | if (i.base_reg->reg_num == EBP_REG_NUM) | |
2111 | { | |
2112 | default_seg = &ss; | |
2113 | if (i.disp_operands == 0) | |
2114 | { | |
2115 | fake_zero_displacement = 1; | |
2116 | i.types[op] |= Disp8; | |
2117 | } | |
2118 | } | |
2119 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
2120 | { | |
2121 | default_seg = &ss; | |
2122 | } | |
2123 | i.sib.scale = i.log2_scale_factor; | |
2124 | if (! i.index_reg) | |
2125 | { | |
2126 | /* <disp>(%esp) becomes two byte modrm | |
2127 | with no index register. We've already | |
2128 | stored the code for esp in i.rm.regmem | |
2129 | ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any | |
2130 | base register besides %esp will not use | |
2131 | the extra modrm byte. */ | |
2132 | i.sib.index = NO_INDEX_REGISTER; | |
2133 | #if ! SCALE1_WHEN_NO_INDEX | |
2134 | /* Another case where we force the second | |
2135 | modrm byte. */ | |
2136 | if (i.log2_scale_factor) | |
2137 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2138 | #endif | |
2139 | } | |
2140 | else | |
2141 | { | |
2142 | i.sib.index = i.index_reg->reg_num; | |
2143 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2144 | } | |
2145 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2146 | } | |
2147 | ||
2148 | if (fake_zero_displacement) | |
2149 | { | |
2150 | /* Fakes a zero displacement assuming that i.types[op] | |
47926f60 | 2151 | holds the correct displacement size. */ |
b4cac588 AM |
2152 | expressionS *exp; |
2153 | ||
520dc8e8 | 2154 | assert (i.op[op].disps == 0); |
252b5132 | 2155 | exp = &disp_expressions[i.disp_operands++]; |
520dc8e8 | 2156 | i.op[op].disps = exp; |
252b5132 RH |
2157 | exp->X_op = O_constant; |
2158 | exp->X_add_number = 0; | |
2159 | exp->X_add_symbol = (symbolS *) 0; | |
2160 | exp->X_op_symbol = (symbolS *) 0; | |
2161 | } | |
2162 | } | |
2163 | ||
2164 | /* Fill in i.rm.reg or i.rm.regmem field with register | |
2165 | operand (if any) based on i.tm.extension_opcode. | |
2166 | Again, we must be careful to make sure that | |
2167 | segment/control/debug/test/MMX registers are coded | |
47926f60 | 2168 | into the i.rm.reg field. */ |
252b5132 RH |
2169 | if (i.reg_operands) |
2170 | { | |
2171 | unsigned int op = | |
2172 | ((i.types[0] | |
3f4438ab AM |
2173 | & (Reg | RegMMX | RegXMM |
2174 | | SReg2 | SReg3 | |
2175 | | Control | Debug | Test)) | |
252b5132 RH |
2176 | ? 0 |
2177 | : ((i.types[1] | |
3f4438ab AM |
2178 | & (Reg | RegMMX | RegXMM |
2179 | | SReg2 | SReg3 | |
2180 | | Control | Debug | Test)) | |
252b5132 RH |
2181 | ? 1 |
2182 | : 2)); | |
2183 | /* If there is an extension opcode to put here, the | |
47926f60 | 2184 | register number must be put into the regmem field. */ |
252b5132 | 2185 | if (i.tm.extension_opcode != None) |
520dc8e8 | 2186 | i.rm.regmem = i.op[op].regs->reg_num; |
252b5132 | 2187 | else |
520dc8e8 | 2188 | i.rm.reg = i.op[op].regs->reg_num; |
252b5132 RH |
2189 | |
2190 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 | |
2191 | we must set it to 3 to indicate this is a register | |
2192 | operand in the regmem field. */ | |
2193 | if (!i.mem_operands) | |
2194 | i.rm.mode = 3; | |
2195 | } | |
2196 | ||
47926f60 | 2197 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
252b5132 RH |
2198 | if (i.tm.extension_opcode != None) |
2199 | i.rm.reg = i.tm.extension_opcode; | |
2200 | } | |
2201 | } | |
2202 | else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) | |
2203 | { | |
47926f60 KH |
2204 | if (i.tm.base_opcode == POP_SEG_SHORT |
2205 | && i.op[0].regs->reg_num == 1) | |
252b5132 RH |
2206 | { |
2207 | as_bad (_("you can't `pop %%cs'")); | |
2208 | return; | |
2209 | } | |
520dc8e8 | 2210 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
252b5132 RH |
2211 | } |
2212 | else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32) | |
2213 | { | |
2214 | default_seg = &ds; | |
2215 | } | |
2216 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
2217 | { | |
2218 | /* For the string instructions that allow a segment override | |
2219 | on one of their operands, the default segment is ds. */ | |
2220 | default_seg = &ds; | |
2221 | } | |
2222 | ||
2223 | /* If a segment was explicitly specified, | |
2224 | and the specified segment is not the default, | |
2225 | use an opcode prefix to select it. | |
2226 | If we never figured out what the default segment is, | |
2227 | then default_seg will be zero at this point, | |
2228 | and the specified segment prefix will always be used. */ | |
2229 | if ((i.seg[0]) && (i.seg[0] != default_seg)) | |
2230 | { | |
2231 | if (! add_prefix (i.seg[0]->seg_prefix)) | |
2232 | return; | |
2233 | } | |
2234 | } | |
a38cf1db | 2235 | else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 | 2236 | { |
24eab124 AM |
2237 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ |
2238 | as_warn (_("translating to `%sp'"), i.tm.name); | |
252b5132 RH |
2239 | } |
2240 | } | |
2241 | ||
47926f60 | 2242 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
520dc8e8 | 2243 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) |
252b5132 RH |
2244 | { |
2245 | i.tm.base_opcode = INT3_OPCODE; | |
2246 | i.imm_operands = 0; | |
2247 | } | |
2248 | ||
2f66722d | 2249 | if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) |
520dc8e8 | 2250 | && i.op[0].disps->X_op == O_constant) |
2f66722d AM |
2251 | { |
2252 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
2253 | the absolute address given by the constant. Since ix86 jumps and | |
2254 | calls are pc relative, we need to generate a reloc. */ | |
520dc8e8 AM |
2255 | i.op[0].disps->X_add_symbol = &abs_symbol; |
2256 | i.op[0].disps->X_op = O_symbol; | |
2f66722d AM |
2257 | } |
2258 | ||
47926f60 | 2259 | /* We are ready to output the insn. */ |
252b5132 RH |
2260 | { |
2261 | register char *p; | |
2262 | ||
47926f60 | 2263 | /* Output jumps. */ |
252b5132 RH |
2264 | if (i.tm.opcode_modifier & Jump) |
2265 | { | |
a217f122 AM |
2266 | int size; |
2267 | int code16; | |
2268 | int prefix; | |
252b5132 | 2269 | |
a217f122 AM |
2270 | code16 = 0; |
2271 | if (flag_16bit_code) | |
2272 | code16 = CODE16; | |
2273 | ||
2274 | prefix = 0; | |
2275 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2276 | { |
a217f122 | 2277 | prefix = 1; |
252b5132 | 2278 | i.prefixes -= 1; |
a217f122 | 2279 | code16 ^= CODE16; |
252b5132 | 2280 | } |
252b5132 | 2281 | |
a217f122 AM |
2282 | size = 4; |
2283 | if (code16) | |
2284 | size = 2; | |
2285 | ||
2286 | if (i.prefixes != 0 && !intel_syntax) | |
252b5132 RH |
2287 | as_warn (_("skipping prefixes on this instruction")); |
2288 | ||
2f66722d AM |
2289 | /* It's always a symbol; End frag & setup for relax. |
2290 | Make sure there is enough room in this frag for the largest | |
2291 | instruction we may generate in md_convert_frag. This is 2 | |
2292 | bytes for the opcode and room for the prefix and largest | |
2293 | displacement. */ | |
2294 | frag_grow (prefix + 2 + size); | |
2295 | insn_size += prefix + 1; | |
2296 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
2297 | p = frag_more (prefix + 1); | |
2298 | if (prefix) | |
2299 | *p++ = DATA_PREFIX_OPCODE; | |
2300 | *p = i.tm.base_opcode; | |
ee7fcc42 AM |
2301 | /* 1 possible extra opcode + displacement go in var part. |
2302 | Pass reloc in fr_var. */ | |
2f66722d AM |
2303 | frag_var (rs_machine_dependent, |
2304 | 1 + size, | |
ee7fcc42 | 2305 | i.disp_reloc[0], |
2f66722d AM |
2306 | ((unsigned char) *p == JUMP_PC_RELATIVE |
2307 | ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16 | |
2308 | : ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16), | |
520dc8e8 AM |
2309 | i.op[0].disps->X_add_symbol, |
2310 | i.op[0].disps->X_add_number, | |
2f66722d | 2311 | p); |
252b5132 RH |
2312 | } |
2313 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) | |
2314 | { | |
a217f122 | 2315 | int size; |
252b5132 | 2316 | |
a217f122 | 2317 | if (i.tm.opcode_modifier & JumpByte) |
252b5132 | 2318 | { |
a217f122 AM |
2319 | /* This is a loop or jecxz type instruction. */ |
2320 | size = 1; | |
252b5132 RH |
2321 | if (i.prefix[ADDR_PREFIX]) |
2322 | { | |
2323 | insn_size += 1; | |
2324 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
2325 | i.prefixes -= 1; | |
2326 | } | |
2327 | } | |
2328 | else | |
2329 | { | |
a217f122 AM |
2330 | int code16; |
2331 | ||
2332 | code16 = 0; | |
2333 | if (flag_16bit_code) | |
2334 | code16 = CODE16; | |
252b5132 RH |
2335 | |
2336 | if (i.prefix[DATA_PREFIX]) | |
2337 | { | |
2338 | insn_size += 1; | |
2339 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
2340 | i.prefixes -= 1; | |
a217f122 | 2341 | code16 ^= CODE16; |
252b5132 | 2342 | } |
252b5132 | 2343 | |
a217f122 | 2344 | size = 4; |
252b5132 RH |
2345 | if (code16) |
2346 | size = 2; | |
2347 | } | |
2348 | ||
a217f122 | 2349 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2350 | as_warn (_("skipping prefixes on this instruction")); |
2351 | ||
2352 | if (fits_in_unsigned_byte (i.tm.base_opcode)) | |
2353 | { | |
2354 | insn_size += 1 + size; | |
2355 | p = frag_more (1 + size); | |
2356 | } | |
2357 | else | |
2358 | { | |
47926f60 | 2359 | /* Opcode can be at most two bytes. */ |
a217f122 | 2360 | insn_size += 2 + size; |
252b5132 RH |
2361 | p = frag_more (2 + size); |
2362 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
2363 | } | |
2364 | *p++ = i.tm.base_opcode & 0xff; | |
2365 | ||
2f66722d | 2366 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
520dc8e8 | 2367 | i.op[0].disps, 1, reloc (size, 1, i.disp_reloc[0])); |
252b5132 RH |
2368 | } |
2369 | else if (i.tm.opcode_modifier & JumpInterSegment) | |
2370 | { | |
2371 | int size; | |
a217f122 AM |
2372 | int prefix; |
2373 | int code16; | |
252b5132 | 2374 | |
a217f122 AM |
2375 | code16 = 0; |
2376 | if (flag_16bit_code) | |
2377 | code16 = CODE16; | |
2378 | ||
2379 | prefix = 0; | |
2380 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2381 | { |
a217f122 | 2382 | prefix = 1; |
252b5132 | 2383 | i.prefixes -= 1; |
a217f122 | 2384 | code16 ^= CODE16; |
252b5132 | 2385 | } |
252b5132 RH |
2386 | |
2387 | size = 4; | |
252b5132 | 2388 | if (code16) |
f6af82bd | 2389 | size = 2; |
252b5132 | 2390 | |
a217f122 | 2391 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2392 | as_warn (_("skipping prefixes on this instruction")); |
2393 | ||
47926f60 KH |
2394 | /* 1 opcode; 2 segment; offset */ |
2395 | insn_size += prefix + 1 + 2 + size; | |
252b5132 RH |
2396 | p = frag_more (prefix + 1 + 2 + size); |
2397 | if (prefix) | |
2398 | *p++ = DATA_PREFIX_OPCODE; | |
2399 | *p++ = i.tm.base_opcode; | |
520dc8e8 | 2400 | if (i.op[1].imms->X_op == O_constant) |
252b5132 | 2401 | { |
847f7ad4 | 2402 | offsetT n = i.op[1].imms->X_add_number; |
252b5132 | 2403 | |
773f551c AM |
2404 | if (size == 2 |
2405 | && !fits_in_unsigned_word (n) | |
2406 | && !fits_in_signed_word (n)) | |
252b5132 RH |
2407 | { |
2408 | as_bad (_("16-bit jump out of range")); | |
2409 | return; | |
2410 | } | |
847f7ad4 | 2411 | md_number_to_chars (p, n, size); |
252b5132 RH |
2412 | } |
2413 | else | |
2414 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
520dc8e8 AM |
2415 | i.op[1].imms, 0, reloc (size, 0, i.disp_reloc[0])); |
2416 | if (i.op[0].imms->X_op != O_constant) | |
252b5132 RH |
2417 | as_bad (_("can't handle non absolute segment in `%s'"), |
2418 | i.tm.name); | |
520dc8e8 | 2419 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); |
252b5132 RH |
2420 | } |
2421 | else | |
2422 | { | |
47926f60 | 2423 | /* Output normal instructions here. */ |
252b5132 RH |
2424 | unsigned char *q; |
2425 | ||
47926f60 | 2426 | /* The prefix bytes. */ |
252b5132 RH |
2427 | for (q = i.prefix; |
2428 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); | |
2429 | q++) | |
2430 | { | |
2431 | if (*q) | |
2432 | { | |
2433 | insn_size += 1; | |
2434 | p = frag_more (1); | |
2435 | md_number_to_chars (p, (valueT) *q, 1); | |
2436 | } | |
2437 | } | |
2438 | ||
47926f60 | 2439 | /* Now the opcode; be careful about word order here! */ |
252b5132 RH |
2440 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
2441 | { | |
2442 | insn_size += 1; | |
2443 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
2444 | } | |
2445 | else if (fits_in_unsigned_word (i.tm.base_opcode)) | |
2446 | { | |
2447 | insn_size += 2; | |
2448 | p = frag_more (2); | |
47926f60 | 2449 | /* Put out high byte first: can't use md_number_to_chars! */ |
252b5132 RH |
2450 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
2451 | *p = i.tm.base_opcode & 0xff; | |
2452 | } | |
2453 | else | |
47926f60 | 2454 | { /* Opcode is either 3 or 4 bytes. */ |
252b5132 RH |
2455 | if (i.tm.base_opcode & 0xff000000) |
2456 | { | |
2457 | insn_size += 4; | |
2458 | p = frag_more (4); | |
2459 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
2460 | } | |
2461 | else | |
2462 | { | |
2463 | insn_size += 3; | |
2464 | p = frag_more (3); | |
2465 | } | |
2466 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
2467 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
2468 | *p = (i.tm.base_opcode) & 0xff; | |
2469 | } | |
2470 | ||
2471 | /* Now the modrm byte and sib byte (if present). */ | |
2472 | if (i.tm.opcode_modifier & Modrm) | |
2473 | { | |
2474 | insn_size += 1; | |
2475 | p = frag_more (1); | |
2476 | md_number_to_chars (p, | |
2477 | (valueT) (i.rm.regmem << 0 | |
2478 | | i.rm.reg << 3 | |
2479 | | i.rm.mode << 6), | |
2480 | 1); | |
2481 | /* If i.rm.regmem == ESP (4) | |
2482 | && i.rm.mode != (Register mode) | |
2483 | && not 16 bit | |
2484 | ==> need second modrm byte. */ | |
2485 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
2486 | && i.rm.mode != 3 | |
2487 | && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) | |
2488 | { | |
2489 | insn_size += 1; | |
2490 | p = frag_more (1); | |
2491 | md_number_to_chars (p, | |
2492 | (valueT) (i.sib.base << 0 | |
2493 | | i.sib.index << 3 | |
2494 | | i.sib.scale << 6), | |
2495 | 1); | |
2496 | } | |
2497 | } | |
2498 | ||
2499 | if (i.disp_operands) | |
2500 | { | |
2501 | register unsigned int n; | |
2502 | ||
2503 | for (n = 0; n < i.operands; n++) | |
2504 | { | |
520dc8e8 | 2505 | if (i.types[n] & Disp) |
252b5132 | 2506 | { |
520dc8e8 | 2507 | if (i.op[n].disps->X_op == O_constant) |
252b5132 | 2508 | { |
847f7ad4 AM |
2509 | int size; |
2510 | offsetT val; | |
b4cac588 | 2511 | |
847f7ad4 | 2512 | size = 4; |
b4cac588 | 2513 | if (i.types[n] & (Disp8 | Disp16)) |
252b5132 | 2514 | { |
b4cac588 | 2515 | size = 2; |
b4cac588 | 2516 | if (i.types[n] & Disp8) |
847f7ad4 | 2517 | size = 1; |
252b5132 | 2518 | } |
847f7ad4 AM |
2519 | val = offset_in_range (i.op[n].disps->X_add_number, |
2520 | size); | |
b4cac588 AM |
2521 | insn_size += size; |
2522 | p = frag_more (size); | |
847f7ad4 | 2523 | md_number_to_chars (p, val, size); |
252b5132 | 2524 | } |
252b5132 | 2525 | else |
520dc8e8 AM |
2526 | { |
2527 | int size = 4; | |
2528 | ||
2529 | if (i.types[n] & Disp16) | |
2530 | size = 2; | |
2531 | ||
2532 | insn_size += size; | |
2533 | p = frag_more (size); | |
2534 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
2535 | i.op[n].disps, 0, | |
2536 | reloc (size, 0, i.disp_reloc[n])); | |
252b5132 RH |
2537 | } |
2538 | } | |
2539 | } | |
47926f60 | 2540 | } /* End displacement output. */ |
252b5132 | 2541 | |
47926f60 | 2542 | /* Output immediate. */ |
252b5132 RH |
2543 | if (i.imm_operands) |
2544 | { | |
2545 | register unsigned int n; | |
2546 | ||
2547 | for (n = 0; n < i.operands; n++) | |
2548 | { | |
520dc8e8 | 2549 | if (i.types[n] & Imm) |
252b5132 | 2550 | { |
520dc8e8 | 2551 | if (i.op[n].imms->X_op == O_constant) |
252b5132 | 2552 | { |
847f7ad4 AM |
2553 | int size; |
2554 | offsetT val; | |
b4cac588 | 2555 | |
847f7ad4 | 2556 | size = 4; |
b4cac588 | 2557 | if (i.types[n] & (Imm8 | Imm8S | Imm16)) |
252b5132 | 2558 | { |
b4cac588 | 2559 | size = 2; |
b4cac588 | 2560 | if (i.types[n] & (Imm8 | Imm8S)) |
847f7ad4 | 2561 | size = 1; |
252b5132 | 2562 | } |
847f7ad4 AM |
2563 | val = offset_in_range (i.op[n].imms->X_add_number, |
2564 | size); | |
b4cac588 AM |
2565 | insn_size += size; |
2566 | p = frag_more (size); | |
847f7ad4 | 2567 | md_number_to_chars (p, val, size); |
252b5132 RH |
2568 | } |
2569 | else | |
47926f60 | 2570 | { /* Not absolute_section. */ |
252b5132 | 2571 | /* Need a 32-bit fixup (don't support 8bit |
520dc8e8 | 2572 | non-absolute imms). Try to support other |
47926f60 | 2573 | sizes ... */ |
f6af82bd AM |
2574 | #ifdef BFD_ASSEMBLER |
2575 | enum bfd_reloc_code_real reloc_type; | |
2576 | #else | |
2577 | int reloc_type; | |
2578 | #endif | |
520dc8e8 | 2579 | int size = 4; |
252b5132 | 2580 | |
520dc8e8 | 2581 | if (i.types[n] & Imm16) |
252b5132 | 2582 | size = 2; |
520dc8e8 AM |
2583 | else if (i.types[n] & (Imm8 | Imm8S)) |
2584 | size = 1; | |
2585 | ||
252b5132 RH |
2586 | insn_size += size; |
2587 | p = frag_more (size); | |
f6af82bd | 2588 | reloc_type = reloc (size, 0, i.disp_reloc[0]); |
252b5132 | 2589 | #ifdef BFD_ASSEMBLER |
f6af82bd | 2590 | if (reloc_type == BFD_RELOC_32 |
252b5132 | 2591 | && GOT_symbol |
520dc8e8 AM |
2592 | && GOT_symbol == i.op[n].imms->X_add_symbol |
2593 | && (i.op[n].imms->X_op == O_symbol | |
2594 | || (i.op[n].imms->X_op == O_add | |
49309057 | 2595 | && ((symbol_get_value_expression |
520dc8e8 | 2596 | (i.op[n].imms->X_op_symbol)->X_op) |
252b5132 RH |
2597 | == O_subtract)))) |
2598 | { | |
f6af82bd | 2599 | reloc_type = BFD_RELOC_386_GOTPC; |
520dc8e8 | 2600 | i.op[n].imms->X_add_number += 3; |
252b5132 RH |
2601 | } |
2602 | #endif | |
2603 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
520dc8e8 | 2604 | i.op[n].imms, 0, reloc_type); |
252b5132 RH |
2605 | } |
2606 | } | |
2607 | } | |
47926f60 | 2608 | } /* end immediate output */ |
252b5132 RH |
2609 | } |
2610 | ||
2611 | #ifdef DEBUG386 | |
2612 | if (flag_debug) | |
2613 | { | |
2614 | pi (line, &i); | |
2615 | } | |
47926f60 | 2616 | #endif /* DEBUG386 */ |
252b5132 RH |
2617 | } |
2618 | } | |
2619 | \f | |
252b5132 RH |
2620 | static int i386_immediate PARAMS ((char *)); |
2621 | ||
2622 | static int | |
2623 | i386_immediate (imm_start) | |
2624 | char *imm_start; | |
2625 | { | |
2626 | char *save_input_line_pointer; | |
2627 | segT exp_seg = 0; | |
47926f60 | 2628 | expressionS *exp; |
252b5132 RH |
2629 | |
2630 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
2631 | { | |
d0b47220 | 2632 | as_bad (_("only 1 or 2 immediate operands are allowed")); |
252b5132 RH |
2633 | return 0; |
2634 | } | |
2635 | ||
2636 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 2637 | i.op[this_operand].imms = exp; |
252b5132 RH |
2638 | |
2639 | if (is_space_char (*imm_start)) | |
2640 | ++imm_start; | |
2641 | ||
2642 | save_input_line_pointer = input_line_pointer; | |
2643 | input_line_pointer = imm_start; | |
2644 | ||
2645 | #ifndef LEX_AT | |
24eab124 | 2646 | { |
47926f60 KH |
2647 | /* We can have operands of the form |
2648 | <symbol>@GOTOFF+<nnn> | |
2649 | Take the easy way out here and copy everything | |
2650 | into a temporary buffer... */ | |
24eab124 AM |
2651 | register char *cp; |
2652 | ||
2653 | cp = strchr (input_line_pointer, '@'); | |
2654 | if (cp != NULL) | |
2655 | { | |
2656 | char *tmpbuf; | |
2657 | int len = 0; | |
2658 | int first; | |
2659 | ||
47926f60 | 2660 | /* GOT relocations are not supported in 16 bit mode. */ |
24eab124 AM |
2661 | if (flag_16bit_code) |
2662 | as_bad (_("GOT relocations not supported in 16 bit mode")); | |
2663 | ||
2664 | if (GOT_symbol == NULL) | |
2665 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
2666 | ||
2667 | if (strncmp (cp + 1, "PLT", 3) == 0) | |
2668 | { | |
2669 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
2670 | len = 3; | |
2671 | } | |
2672 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) | |
2673 | { | |
2674 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; | |
2675 | len = 6; | |
2676 | } | |
2677 | else if (strncmp (cp + 1, "GOT", 3) == 0) | |
2678 | { | |
2679 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; | |
2680 | len = 3; | |
2681 | } | |
2682 | else | |
d0b47220 | 2683 | as_bad (_("bad reloc specifier in expression")); |
24eab124 AM |
2684 | |
2685 | /* Replace the relocation token with ' ', so that errors like | |
2686 | foo@GOTOFF1 will be detected. */ | |
2687 | first = cp - input_line_pointer; | |
47926f60 | 2688 | tmpbuf = (char *) alloca (strlen (input_line_pointer)); |
24eab124 AM |
2689 | memcpy (tmpbuf, input_line_pointer, first); |
2690 | tmpbuf[first] = ' '; | |
2691 | strcpy (tmpbuf + first + 1, cp + 1 + len); | |
2692 | input_line_pointer = tmpbuf; | |
2693 | } | |
2694 | } | |
252b5132 RH |
2695 | #endif |
2696 | ||
2697 | exp_seg = expression (exp); | |
2698 | ||
83183c0c | 2699 | SKIP_WHITESPACE (); |
252b5132 | 2700 | if (*input_line_pointer) |
d0b47220 | 2701 | as_bad (_("ignoring junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
2702 | |
2703 | input_line_pointer = save_input_line_pointer; | |
2704 | ||
2daf4fd8 | 2705 | if (exp->X_op == O_absent || exp->X_op == O_big) |
252b5132 | 2706 | { |
47926f60 | 2707 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 2708 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
24eab124 | 2709 | imm_start); |
252b5132 RH |
2710 | exp->X_op = O_constant; |
2711 | exp->X_add_number = 0; | |
2712 | exp->X_add_symbol = (symbolS *) 0; | |
2713 | exp->X_op_symbol = (symbolS *) 0; | |
252b5132 | 2714 | } |
2daf4fd8 AM |
2715 | |
2716 | if (exp->X_op == O_constant) | |
252b5132 | 2717 | { |
47926f60 KH |
2718 | /* Size it properly later. */ |
2719 | i.types[this_operand] |= Imm32; | |
252b5132 | 2720 | } |
4c63da97 | 2721 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
47926f60 | 2722 | else if (1 |
4c63da97 | 2723 | #ifdef BFD_ASSEMBLER |
47926f60 | 2724 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
4c63da97 | 2725 | #endif |
47926f60 | 2726 | && exp_seg != text_section |
24eab124 AM |
2727 | && exp_seg != data_section |
2728 | && exp_seg != bss_section | |
2729 | && exp_seg != undefined_section | |
252b5132 | 2730 | #ifdef BFD_ASSEMBLER |
24eab124 | 2731 | && !bfd_is_com_section (exp_seg) |
252b5132 | 2732 | #endif |
24eab124 | 2733 | ) |
252b5132 | 2734 | { |
4c63da97 | 2735 | #ifdef BFD_ASSEMBLER |
d0b47220 | 2736 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 2737 | #else |
d0b47220 | 2738 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 2739 | #endif |
252b5132 RH |
2740 | return 0; |
2741 | } | |
2742 | #endif | |
2743 | else | |
2744 | { | |
2745 | /* This is an address. The size of the address will be | |
24eab124 AM |
2746 | determined later, depending on destination register, |
2747 | suffix, or the default for the section. We exclude | |
2748 | Imm8S here so that `push $foo' and other instructions | |
2749 | with an Imm8S form will use Imm16 or Imm32. */ | |
252b5132 RH |
2750 | i.types[this_operand] |= (Imm8 | Imm16 | Imm32); |
2751 | } | |
2752 | ||
2753 | return 1; | |
2754 | } | |
2755 | ||
2756 | static int i386_scale PARAMS ((char *)); | |
2757 | ||
2758 | static int | |
2759 | i386_scale (scale) | |
2760 | char *scale; | |
2761 | { | |
2762 | if (!isdigit (*scale)) | |
2763 | goto bad_scale; | |
2764 | ||
2765 | switch (*scale) | |
2766 | { | |
2767 | case '0': | |
2768 | case '1': | |
2769 | i.log2_scale_factor = 0; | |
2770 | break; | |
2771 | case '2': | |
2772 | i.log2_scale_factor = 1; | |
2773 | break; | |
2774 | case '4': | |
2775 | i.log2_scale_factor = 2; | |
2776 | break; | |
2777 | case '8': | |
2778 | i.log2_scale_factor = 3; | |
2779 | break; | |
2780 | default: | |
2781 | bad_scale: | |
2782 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
24eab124 | 2783 | scale); |
252b5132 RH |
2784 | return 0; |
2785 | } | |
2786 | if (i.log2_scale_factor != 0 && ! i.index_reg) | |
2787 | { | |
2788 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 2789 | 1 << i.log2_scale_factor); |
252b5132 RH |
2790 | #if SCALE1_WHEN_NO_INDEX |
2791 | i.log2_scale_factor = 0; | |
2792 | #endif | |
2793 | } | |
2794 | return 1; | |
2795 | } | |
2796 | ||
2797 | static int i386_displacement PARAMS ((char *, char *)); | |
2798 | ||
2799 | static int | |
2800 | i386_displacement (disp_start, disp_end) | |
2801 | char *disp_start; | |
2802 | char *disp_end; | |
2803 | { | |
2804 | register expressionS *exp; | |
2805 | segT exp_seg = 0; | |
2806 | char *save_input_line_pointer; | |
2807 | int bigdisp = Disp32; | |
2808 | ||
252b5132 RH |
2809 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) |
2810 | bigdisp = Disp16; | |
2811 | i.types[this_operand] |= bigdisp; | |
2812 | ||
2813 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 2814 | i.op[this_operand].disps = exp; |
252b5132 RH |
2815 | i.disp_operands++; |
2816 | save_input_line_pointer = input_line_pointer; | |
2817 | input_line_pointer = disp_start; | |
2818 | END_STRING_AND_SAVE (disp_end); | |
2819 | ||
2820 | #ifndef GCC_ASM_O_HACK | |
2821 | #define GCC_ASM_O_HACK 0 | |
2822 | #endif | |
2823 | #if GCC_ASM_O_HACK | |
2824 | END_STRING_AND_SAVE (disp_end + 1); | |
2825 | if ((i.types[this_operand] & BaseIndex) != 0 | |
24eab124 | 2826 | && displacement_string_end[-1] == '+') |
252b5132 RH |
2827 | { |
2828 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
2829 | constraint within gcc asm statements. |
2830 | For instance: | |
2831 | ||
2832 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
2833 | __asm__ __volatile__ ( \ | |
2834 | "movw %w2,%0\n\t" \ | |
2835 | "movw %w1,2+%0\n\t" \ | |
2836 | "rorl $16,%1\n\t" \ | |
2837 | "movb %b1,4+%0\n\t" \ | |
2838 | "movb %4,5+%0\n\t" \ | |
2839 | "movb $0,6+%0\n\t" \ | |
2840 | "movb %h1,7+%0\n\t" \ | |
2841 | "rorl $16,%1" \ | |
2842 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
2843 | ||
2844 | This works great except that the output assembler ends | |
2845 | up looking a bit weird if it turns out that there is | |
2846 | no offset. You end up producing code that looks like: | |
2847 | ||
2848 | #APP | |
2849 | movw $235,(%eax) | |
2850 | movw %dx,2+(%eax) | |
2851 | rorl $16,%edx | |
2852 | movb %dl,4+(%eax) | |
2853 | movb $137,5+(%eax) | |
2854 | movb $0,6+(%eax) | |
2855 | movb %dh,7+(%eax) | |
2856 | rorl $16,%edx | |
2857 | #NO_APP | |
2858 | ||
47926f60 | 2859 | So here we provide the missing zero. */ |
24eab124 AM |
2860 | |
2861 | *displacement_string_end = '0'; | |
252b5132 RH |
2862 | } |
2863 | #endif | |
2864 | #ifndef LEX_AT | |
24eab124 | 2865 | { |
47926f60 KH |
2866 | /* We can have operands of the form |
2867 | <symbol>@GOTOFF+<nnn> | |
2868 | Take the easy way out here and copy everything | |
2869 | into a temporary buffer... */ | |
24eab124 AM |
2870 | register char *cp; |
2871 | ||
2872 | cp = strchr (input_line_pointer, '@'); | |
2873 | if (cp != NULL) | |
2874 | { | |
2875 | char *tmpbuf; | |
2876 | int len = 0; | |
2877 | int first; | |
2878 | ||
47926f60 | 2879 | /* GOT relocations are not supported in 16 bit mode. */ |
24eab124 AM |
2880 | if (flag_16bit_code) |
2881 | as_bad (_("GOT relocations not supported in 16 bit mode")); | |
2882 | ||
2883 | if (GOT_symbol == NULL) | |
2884 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
2885 | ||
2886 | if (strncmp (cp + 1, "PLT", 3) == 0) | |
2887 | { | |
2888 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
2889 | len = 3; | |
2890 | } | |
2891 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) | |
2892 | { | |
2893 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; | |
2894 | len = 6; | |
2895 | } | |
2896 | else if (strncmp (cp + 1, "GOT", 3) == 0) | |
2897 | { | |
2898 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; | |
2899 | len = 3; | |
2900 | } | |
2901 | else | |
d0b47220 | 2902 | as_bad (_("bad reloc specifier in expression")); |
24eab124 AM |
2903 | |
2904 | /* Replace the relocation token with ' ', so that errors like | |
2905 | foo@GOTOFF1 will be detected. */ | |
2906 | first = cp - input_line_pointer; | |
47926f60 | 2907 | tmpbuf = (char *) alloca (strlen (input_line_pointer)); |
24eab124 AM |
2908 | memcpy (tmpbuf, input_line_pointer, first); |
2909 | tmpbuf[first] = ' '; | |
2910 | strcpy (tmpbuf + first + 1, cp + 1 + len); | |
2911 | input_line_pointer = tmpbuf; | |
2912 | } | |
2913 | } | |
252b5132 RH |
2914 | #endif |
2915 | ||
24eab124 | 2916 | exp_seg = expression (exp); |
252b5132 RH |
2917 | |
2918 | #ifdef BFD_ASSEMBLER | |
24eab124 AM |
2919 | /* We do this to make sure that the section symbol is in |
2920 | the symbol table. We will ultimately change the relocation | |
47926f60 | 2921 | to be relative to the beginning of the section. */ |
24eab124 AM |
2922 | if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF) |
2923 | { | |
2924 | if (S_IS_LOCAL(exp->X_add_symbol) | |
2925 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) | |
2926 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
2927 | assert (exp->X_op == O_symbol); | |
2928 | exp->X_op = O_subtract; | |
2929 | exp->X_op_symbol = GOT_symbol; | |
2930 | i.disp_reloc[this_operand] = BFD_RELOC_32; | |
2931 | } | |
252b5132 RH |
2932 | #endif |
2933 | ||
24eab124 AM |
2934 | SKIP_WHITESPACE (); |
2935 | if (*input_line_pointer) | |
d0b47220 | 2936 | as_bad (_("ignoring junk `%s' after expression"), |
24eab124 | 2937 | input_line_pointer); |
252b5132 | 2938 | #if GCC_ASM_O_HACK |
24eab124 | 2939 | RESTORE_END_STRING (disp_end + 1); |
252b5132 | 2940 | #endif |
24eab124 AM |
2941 | RESTORE_END_STRING (disp_end); |
2942 | input_line_pointer = save_input_line_pointer; | |
2943 | ||
2daf4fd8 AM |
2944 | if (exp->X_op == O_absent || exp->X_op == O_big) |
2945 | { | |
47926f60 | 2946 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 2947 | as_bad (_("missing or invalid displacement expression `%s' taken as 0"), |
2daf4fd8 AM |
2948 | disp_start); |
2949 | exp->X_op = O_constant; | |
2950 | exp->X_add_number = 0; | |
2951 | exp->X_add_symbol = (symbolS *) 0; | |
2952 | exp->X_op_symbol = (symbolS *) 0; | |
2953 | } | |
2954 | ||
4c63da97 | 2955 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
45288df1 | 2956 | if (exp->X_op != O_constant |
4c63da97 | 2957 | #ifdef BFD_ASSEMBLER |
45288df1 | 2958 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
4c63da97 | 2959 | #endif |
45288df1 AM |
2960 | && exp_seg != text_section |
2961 | && exp_seg != data_section | |
2962 | && exp_seg != bss_section | |
2963 | && exp_seg != undefined_section) | |
24eab124 | 2964 | { |
4c63da97 | 2965 | #ifdef BFD_ASSEMBLER |
d0b47220 | 2966 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 2967 | #else |
d0b47220 | 2968 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 2969 | #endif |
24eab124 AM |
2970 | return 0; |
2971 | } | |
252b5132 RH |
2972 | #endif |
2973 | return 1; | |
2974 | } | |
2975 | ||
2976 | static int i386_operand_modifier PARAMS ((char **, int)); | |
2977 | ||
2978 | static int | |
2979 | i386_operand_modifier (op_string, got_a_float) | |
2980 | char **op_string; | |
2981 | int got_a_float; | |
2982 | { | |
24eab124 AM |
2983 | if (!strncasecmp (*op_string, "BYTE PTR", 8)) |
2984 | { | |
2985 | i.suffix = BYTE_MNEM_SUFFIX; | |
2986 | *op_string += 8; | |
2987 | return BYTE_PTR; | |
252b5132 | 2988 | |
24eab124 AM |
2989 | } |
2990 | else if (!strncasecmp (*op_string, "WORD PTR", 8)) | |
2991 | { | |
47926f60 | 2992 | if (got_a_float == 2) /* "fi..." */ |
cc5ca5ce AM |
2993 | i.suffix = SHORT_MNEM_SUFFIX; |
2994 | else | |
2995 | i.suffix = WORD_MNEM_SUFFIX; | |
24eab124 AM |
2996 | *op_string += 8; |
2997 | return WORD_PTR; | |
2998 | } | |
252b5132 | 2999 | |
24eab124 AM |
3000 | else if (!strncasecmp (*op_string, "DWORD PTR", 9)) |
3001 | { | |
47926f60 | 3002 | if (got_a_float == 1) /* "f..." */ |
24eab124 AM |
3003 | i.suffix = SHORT_MNEM_SUFFIX; |
3004 | else | |
add0c677 | 3005 | i.suffix = LONG_MNEM_SUFFIX; |
24eab124 AM |
3006 | *op_string += 9; |
3007 | return DWORD_PTR; | |
3008 | } | |
252b5132 | 3009 | |
24eab124 AM |
3010 | else if (!strncasecmp (*op_string, "QWORD PTR", 9)) |
3011 | { | |
add0c677 | 3012 | i.suffix = DWORD_MNEM_SUFFIX; |
24eab124 AM |
3013 | *op_string += 9; |
3014 | return QWORD_PTR; | |
3015 | } | |
252b5132 | 3016 | |
24eab124 AM |
3017 | else if (!strncasecmp (*op_string, "XWORD PTR", 9)) |
3018 | { | |
3019 | i.suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
3020 | *op_string += 9; | |
3021 | return XWORD_PTR; | |
3022 | } | |
252b5132 | 3023 | |
24eab124 AM |
3024 | else if (!strncasecmp (*op_string, "SHORT", 5)) |
3025 | { | |
3026 | *op_string += 5; | |
3027 | return SHORT; | |
3028 | } | |
252b5132 | 3029 | |
24eab124 AM |
3030 | else if (!strncasecmp (*op_string, "OFFSET FLAT:", 12)) |
3031 | { | |
3032 | *op_string += 12; | |
3033 | return OFFSET_FLAT; | |
3034 | } | |
252b5132 | 3035 | |
24eab124 AM |
3036 | else if (!strncasecmp (*op_string, "FLAT", 4)) |
3037 | { | |
3038 | *op_string += 4; | |
3039 | return FLAT; | |
3040 | } | |
252b5132 | 3041 | |
24eab124 | 3042 | else return NONE_FOUND; |
c3332e24 | 3043 | } |
252b5132 RH |
3044 | |
3045 | static char * build_displacement_string PARAMS ((int, char *)); | |
3046 | ||
3047 | static char * | |
3048 | build_displacement_string (initial_disp, op_string) | |
3049 | int initial_disp; | |
3050 | char *op_string; | |
3051 | { | |
3052 | char *temp_string = (char *) malloc (strlen (op_string) + 1); | |
3053 | char *end_of_operand_string; | |
3054 | char *tc; | |
3055 | char *temp_disp; | |
3056 | ||
3057 | temp_string[0] = '\0'; | |
3058 | tc = end_of_operand_string = strchr (op_string, '['); | |
36bf8ab9 | 3059 | if (initial_disp && !end_of_operand_string) |
252b5132 RH |
3060 | { |
3061 | strcpy (temp_string, op_string); | |
36bf8ab9 | 3062 | return temp_string; |
252b5132 RH |
3063 | } |
3064 | ||
47926f60 | 3065 | /* Build the whole displacement string. */ |
252b5132 RH |
3066 | if (initial_disp) |
3067 | { | |
3068 | strncpy (temp_string, op_string, end_of_operand_string - op_string); | |
3069 | temp_string[end_of_operand_string - op_string] = '\0'; | |
3070 | temp_disp = tc; | |
3071 | } | |
c3332e24 | 3072 | else |
252b5132 RH |
3073 | temp_disp = op_string; |
3074 | ||
3075 | while (*temp_disp != '\0') | |
3076 | { | |
af6bdddf | 3077 | char *end_op; |
252b5132 RH |
3078 | int add_minus = (*temp_disp == '-'); |
3079 | ||
3080 | if (*temp_disp == '+' || *temp_disp == '-' || *temp_disp == '[') | |
24eab124 | 3081 | temp_disp++; |
252b5132 RH |
3082 | |
3083 | if (is_space_char (*temp_disp)) | |
24eab124 | 3084 | temp_disp++; |
252b5132 | 3085 | |
47926f60 | 3086 | /* Don't consider registers. */ |
af6bdddf AM |
3087 | if ( !((*temp_disp == REGISTER_PREFIX || allow_naked_reg) |
3088 | && parse_register (temp_disp, &end_op)) ) | |
24eab124 AM |
3089 | { |
3090 | char *string_start = temp_disp; | |
3091 | ||
3092 | while (*temp_disp != ']' | |
3093 | && *temp_disp != '+' | |
3094 | && *temp_disp != '-' | |
3095 | && *temp_disp != '*') | |
3096 | ++temp_disp; | |
3097 | ||
3098 | if (add_minus) | |
3099 | strcat (temp_string, "-"); | |
3100 | else | |
3101 | strcat (temp_string, "+"); | |
3102 | ||
3103 | strncat (temp_string, string_start, temp_disp - string_start); | |
3104 | if (*temp_disp == '+' || *temp_disp == '-') | |
3105 | --temp_disp; | |
3106 | } | |
252b5132 RH |
3107 | |
3108 | while (*temp_disp != '\0' | |
24eab124 AM |
3109 | && *temp_disp != '+' |
3110 | && *temp_disp != '-') | |
3111 | ++temp_disp; | |
252b5132 RH |
3112 | } |
3113 | ||
3114 | return temp_string; | |
3115 | } | |
3116 | ||
3117 | static int i386_parse_seg PARAMS ((char *)); | |
3118 | ||
3119 | static int | |
3120 | i386_parse_seg (op_string) | |
3121 | char *op_string; | |
3122 | { | |
3123 | if (is_space_char (*op_string)) | |
3124 | ++op_string; | |
3125 | ||
47926f60 | 3126 | /* Should be one of es, cs, ss, ds fs or gs. */ |
252b5132 RH |
3127 | switch (*op_string++) |
3128 | { | |
3129 | case 'e': | |
3130 | i.seg[i.mem_operands] = &es; | |
3131 | break; | |
3132 | case 'c': | |
3133 | i.seg[i.mem_operands] = &cs; | |
3134 | break; | |
3135 | case 's': | |
3136 | i.seg[i.mem_operands] = &ss; | |
3137 | break; | |
3138 | case 'd': | |
3139 | i.seg[i.mem_operands] = &ds; | |
3140 | break; | |
3141 | case 'f': | |
3142 | i.seg[i.mem_operands] = &fs; | |
3143 | break; | |
3144 | case 'g': | |
3145 | i.seg[i.mem_operands] = &gs; | |
3146 | break; | |
3147 | default: | |
3148 | as_bad (_("bad segment name `%s'"), op_string); | |
3149 | return 0; | |
3150 | } | |
3151 | ||
3152 | if (*op_string++ != 's') | |
3153 | { | |
24eab124 AM |
3154 | as_bad (_("bad segment name `%s'"), op_string); |
3155 | return 0; | |
252b5132 RH |
3156 | } |
3157 | ||
3158 | if (is_space_char (*op_string)) | |
3159 | ++op_string; | |
3160 | ||
3161 | if (*op_string != ':') | |
3162 | { | |
24eab124 AM |
3163 | as_bad (_("bad segment name `%s'"), op_string); |
3164 | return 0; | |
252b5132 RH |
3165 | } |
3166 | ||
c3332e24 AM |
3167 | return 1; |
3168 | ||
252b5132 RH |
3169 | } |
3170 | ||
eecb386c | 3171 | static int i386_index_check PARAMS((const char *)); |
252b5132 | 3172 | |
eecb386c | 3173 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
3174 | Return 1 on success, 0 on a failure. */ |
3175 | ||
252b5132 | 3176 | static int |
eecb386c AM |
3177 | i386_index_check (operand_string) |
3178 | const char *operand_string; | |
252b5132 | 3179 | { |
24eab124 | 3180 | #if INFER_ADDR_PREFIX |
eecb386c AM |
3181 | int fudged = 0; |
3182 | ||
24eab124 AM |
3183 | tryprefix: |
3184 | #endif | |
d0b47220 | 3185 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) |
47926f60 | 3186 | /* 16 bit mode checks. */ |
d0b47220 AM |
3187 | ? ((i.base_reg |
3188 | && ((i.base_reg->reg_type & (Reg16|BaseIndex)) | |
3189 | != (Reg16|BaseIndex))) | |
3190 | || (i.index_reg | |
3191 | && (((i.index_reg->reg_type & (Reg16|BaseIndex)) | |
3192 | != (Reg16|BaseIndex)) | |
3193 | || ! (i.base_reg | |
3194 | && i.base_reg->reg_num < 6 | |
3195 | && i.index_reg->reg_num >= 6 | |
3196 | && i.log2_scale_factor == 0)))) | |
47926f60 | 3197 | /* 32 bit mode checks. */ |
d0b47220 AM |
3198 | : ((i.base_reg |
3199 | && (i.base_reg->reg_type & Reg32) == 0) | |
3200 | || (i.index_reg | |
3201 | && ((i.index_reg->reg_type & (Reg32|BaseIndex)) | |
3202 | != (Reg32|BaseIndex))))) | |
24eab124 AM |
3203 | { |
3204 | #if INFER_ADDR_PREFIX | |
eecb386c | 3205 | if (i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0') |
24eab124 AM |
3206 | { |
3207 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
3208 | i.prefixes += 1; | |
b23bac36 AM |
3209 | /* Change the size of any displacement too. At most one of |
3210 | Disp16 or Disp32 is set. | |
3211 | FIXME. There doesn't seem to be any real need for separate | |
3212 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 3213 | Removing them would probably clean up the code quite a lot. */ |
b23bac36 AM |
3214 | if (i.types[this_operand] & (Disp16|Disp32)) |
3215 | i.types[this_operand] ^= (Disp16|Disp32); | |
eecb386c | 3216 | fudged = 1; |
24eab124 AM |
3217 | goto tryprefix; |
3218 | } | |
eecb386c AM |
3219 | if (fudged) |
3220 | as_bad (_("`%s' is not a valid base/index expression"), | |
3221 | operand_string); | |
3222 | else | |
c388dee8 | 3223 | #endif |
eecb386c AM |
3224 | as_bad (_("`%s' is not a valid %s bit base/index expression"), |
3225 | operand_string, | |
3226 | flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) ? "16" : "32"); | |
3227 | return 0; | |
24eab124 AM |
3228 | } |
3229 | return 1; | |
3230 | } | |
252b5132 | 3231 | |
24eab124 AM |
3232 | static int i386_intel_memory_operand PARAMS ((char *)); |
3233 | ||
3234 | static int | |
3235 | i386_intel_memory_operand (operand_string) | |
3236 | char *operand_string; | |
3237 | { | |
3238 | char *op_string = operand_string; | |
252b5132 RH |
3239 | char *end_of_operand_string; |
3240 | ||
24eab124 AM |
3241 | if ((i.mem_operands == 1 |
3242 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
3243 | || i.mem_operands == 2) | |
252b5132 | 3244 | { |
24eab124 AM |
3245 | as_bad (_("too many memory references for `%s'"), |
3246 | current_templates->start->name); | |
3247 | return 0; | |
252b5132 RH |
3248 | } |
3249 | ||
36bf8ab9 | 3250 | /* First check for a segment override. */ |
252b5132 RH |
3251 | if (*op_string != '[') |
3252 | { | |
3253 | char *end_seg; | |
252b5132 RH |
3254 | |
3255 | end_seg = strchr (op_string, ':'); | |
3256 | if (end_seg) | |
24eab124 AM |
3257 | { |
3258 | if (!i386_parse_seg (op_string)) | |
3259 | return 0; | |
3260 | op_string = end_seg + 1; | |
3261 | } | |
36bf8ab9 | 3262 | } |
252b5132 | 3263 | |
47926f60 | 3264 | /* Look for displacement preceding open bracket. */ |
36bf8ab9 AM |
3265 | if (*op_string != '[') |
3266 | { | |
3267 | char *temp_string; | |
24eab124 | 3268 | |
36bf8ab9 | 3269 | if (i.disp_operands) |
24eab124 | 3270 | return 0; |
252b5132 | 3271 | |
36bf8ab9 AM |
3272 | temp_string = build_displacement_string (true, op_string); |
3273 | ||
3274 | if (!i386_displacement (temp_string, temp_string + strlen (temp_string))) | |
3275 | { | |
3276 | free (temp_string); | |
3277 | return 0; | |
3278 | } | |
3279 | free (temp_string); | |
3280 | ||
252b5132 RH |
3281 | end_of_operand_string = strchr (op_string, '['); |
3282 | if (!end_of_operand_string) | |
24eab124 | 3283 | end_of_operand_string = op_string + strlen (op_string); |
252b5132 RH |
3284 | |
3285 | if (is_space_char (*end_of_operand_string)) | |
24eab124 | 3286 | --end_of_operand_string; |
252b5132 RH |
3287 | |
3288 | op_string = end_of_operand_string; | |
24eab124 | 3289 | } |
252b5132 RH |
3290 | |
3291 | if (*op_string == '[') | |
3292 | { | |
3293 | ++op_string; | |
3294 | ||
3295 | /* Pick off each component and figure out where it belongs */ | |
3296 | ||
3297 | end_of_operand_string = op_string; | |
3298 | ||
3299 | while (*op_string != ']') | |
24eab124 | 3300 | { |
af6bdddf AM |
3301 | const reg_entry *temp_reg; |
3302 | char *end_op; | |
3303 | char *temp_string; | |
24eab124 AM |
3304 | |
3305 | while (*end_of_operand_string != '+' | |
3306 | && *end_of_operand_string != '-' | |
3307 | && *end_of_operand_string != '*' | |
3308 | && *end_of_operand_string != ']') | |
3309 | end_of_operand_string++; | |
3310 | ||
af6bdddf AM |
3311 | temp_string = op_string; |
3312 | if (*temp_string == '+') | |
24eab124 | 3313 | { |
af6bdddf | 3314 | ++temp_string; |
24eab124 AM |
3315 | if (is_space_char (*temp_string)) |
3316 | ++temp_string; | |
24eab124 AM |
3317 | } |
3318 | ||
af6bdddf AM |
3319 | if ((*temp_string == REGISTER_PREFIX || allow_naked_reg) |
3320 | && (temp_reg = parse_register (temp_string, &end_op)) != NULL) | |
24eab124 | 3321 | { |
24eab124 AM |
3322 | if (i.base_reg == NULL) |
3323 | i.base_reg = temp_reg; | |
3324 | else | |
3325 | i.index_reg = temp_reg; | |
3326 | ||
3327 | i.types[this_operand] |= BaseIndex; | |
24eab124 | 3328 | } |
af6bdddf | 3329 | else if (*temp_string == REGISTER_PREFIX) |
24eab124 | 3330 | { |
af6bdddf AM |
3331 | as_bad (_("bad register name `%s'"), temp_string); |
3332 | return 0; | |
3333 | } | |
3334 | else if (is_digit_char (*op_string) | |
3335 | || *op_string == '+' || *op_string == '-') | |
3336 | { | |
36bf8ab9 AM |
3337 | char *temp_str; |
3338 | ||
3339 | if (i.disp_operands != 0) | |
3340 | return 0; | |
3341 | ||
af6bdddf | 3342 | temp_string = build_displacement_string (false, op_string); |
24eab124 | 3343 | |
36bf8ab9 AM |
3344 | temp_str = temp_string; |
3345 | if (*temp_str == '+') | |
3346 | ++temp_str; | |
24eab124 | 3347 | |
36bf8ab9 AM |
3348 | if (!i386_displacement (temp_str, temp_str + strlen (temp_str))) |
3349 | { | |
3350 | free (temp_string); | |
3351 | return 0; | |
3352 | } | |
3353 | free (temp_string); | |
24eab124 AM |
3354 | |
3355 | ++op_string; | |
3356 | end_of_operand_string = op_string; | |
3357 | while (*end_of_operand_string != ']' | |
3358 | && *end_of_operand_string != '+' | |
3359 | && *end_of_operand_string != '-' | |
3360 | && *end_of_operand_string != '*') | |
3361 | ++end_of_operand_string; | |
3362 | } | |
3363 | else if (*op_string == '*') | |
3364 | { | |
3365 | ++op_string; | |
3366 | ||
3367 | if (i.base_reg && !i.index_reg) | |
3368 | { | |
3369 | i.index_reg = i.base_reg; | |
3370 | i.base_reg = 0; | |
3371 | } | |
3372 | ||
3373 | if (!i386_scale (op_string)) | |
3374 | return 0; | |
3375 | } | |
3376 | op_string = end_of_operand_string; | |
3377 | ++end_of_operand_string; | |
3378 | } | |
3379 | } | |
3380 | ||
eecb386c AM |
3381 | if (i386_index_check (operand_string) == 0) |
3382 | return 0; | |
252b5132 | 3383 | |
24eab124 | 3384 | i.mem_operands++; |
252b5132 RH |
3385 | return 1; |
3386 | } | |
3387 | ||
252b5132 RH |
3388 | static int |
3389 | i386_intel_operand (operand_string, got_a_float) | |
3390 | char *operand_string; | |
3391 | int got_a_float; | |
3392 | { | |
47926f60 | 3393 | const reg_entry *r; |
af6bdddf | 3394 | char *end_op; |
252b5132 RH |
3395 | char *op_string = operand_string; |
3396 | ||
3397 | int operand_modifier = i386_operand_modifier (&op_string, got_a_float); | |
3398 | if (is_space_char (*op_string)) | |
3399 | ++op_string; | |
3400 | ||
3401 | switch (operand_modifier) | |
3402 | { | |
3403 | case BYTE_PTR: | |
3404 | case WORD_PTR: | |
3405 | case DWORD_PTR: | |
3406 | case QWORD_PTR: | |
3407 | case XWORD_PTR: | |
252b5132 | 3408 | if (!i386_intel_memory_operand (op_string)) |
24eab124 | 3409 | return 0; |
252b5132 RH |
3410 | break; |
3411 | ||
3412 | case FLAT: | |
252b5132 RH |
3413 | case OFFSET_FLAT: |
3414 | if (!i386_immediate (op_string)) | |
24eab124 | 3415 | return 0; |
252b5132 RH |
3416 | break; |
3417 | ||
3418 | case SHORT: | |
252b5132 | 3419 | case NONE_FOUND: |
c3332e24 AM |
3420 | /* Should be register or immediate */ |
3421 | if (is_digit_char (*op_string) | |
3422 | && strchr (op_string, '[') == 0) | |
3423 | { | |
3424 | if (!i386_immediate (op_string)) | |
3425 | return 0; | |
3426 | } | |
af6bdddf AM |
3427 | else if ((*op_string == REGISTER_PREFIX || allow_naked_reg) |
3428 | && (r = parse_register (op_string, &end_op)) != NULL) | |
c3332e24 | 3429 | { |
c3332e24 AM |
3430 | /* Check for a segment override by searching for ':' after a |
3431 | segment register. */ | |
3432 | op_string = end_op; | |
3433 | if (is_space_char (*op_string)) | |
3434 | ++op_string; | |
3435 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
3436 | { | |
3437 | switch (r->reg_num) | |
3438 | { | |
3439 | case 0: | |
3440 | i.seg[i.mem_operands] = &es; | |
3441 | break; | |
3442 | case 1: | |
3443 | i.seg[i.mem_operands] = &cs; | |
3444 | break; | |
3445 | case 2: | |
3446 | i.seg[i.mem_operands] = &ss; | |
3447 | break; | |
3448 | case 3: | |
3449 | i.seg[i.mem_operands] = &ds; | |
3450 | break; | |
3451 | case 4: | |
3452 | i.seg[i.mem_operands] = &fs; | |
3453 | break; | |
3454 | case 5: | |
3455 | i.seg[i.mem_operands] = &gs; | |
3456 | break; | |
3457 | } | |
252b5132 | 3458 | |
c3332e24 AM |
3459 | } |
3460 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
520dc8e8 | 3461 | i.op[this_operand].regs = r; |
c3332e24 AM |
3462 | i.reg_operands++; |
3463 | } | |
af6bdddf | 3464 | else if (*op_string == REGISTER_PREFIX) |
c3332e24 | 3465 | { |
af6bdddf AM |
3466 | as_bad (_("bad register name `%s'"), op_string); |
3467 | return 0; | |
c3332e24 | 3468 | } |
af6bdddf AM |
3469 | else if (!i386_intel_memory_operand (op_string)) |
3470 | return 0; | |
3471 | ||
c3332e24 | 3472 | break; |
c3332e24 | 3473 | } /* end switch */ |
24eab124 | 3474 | |
252b5132 RH |
3475 | return 1; |
3476 | } | |
3477 | ||
3478 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero | |
47926f60 | 3479 | on error. */ |
252b5132 | 3480 | |
252b5132 RH |
3481 | static int |
3482 | i386_operand (operand_string) | |
3483 | char *operand_string; | |
3484 | { | |
af6bdddf AM |
3485 | const reg_entry *r; |
3486 | char *end_op; | |
24eab124 | 3487 | char *op_string = operand_string; |
252b5132 | 3488 | |
24eab124 | 3489 | if (is_space_char (*op_string)) |
252b5132 RH |
3490 | ++op_string; |
3491 | ||
24eab124 | 3492 | /* We check for an absolute prefix (differentiating, |
47926f60 | 3493 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
3494 | if (*op_string == ABSOLUTE_PREFIX) |
3495 | { | |
3496 | ++op_string; | |
3497 | if (is_space_char (*op_string)) | |
3498 | ++op_string; | |
3499 | i.types[this_operand] |= JumpAbsolute; | |
3500 | } | |
252b5132 | 3501 | |
47926f60 | 3502 | /* Check if operand is a register. */ |
af6bdddf AM |
3503 | if ((*op_string == REGISTER_PREFIX || allow_naked_reg) |
3504 | && (r = parse_register (op_string, &end_op)) != NULL) | |
24eab124 | 3505 | { |
24eab124 AM |
3506 | /* Check for a segment override by searching for ':' after a |
3507 | segment register. */ | |
3508 | op_string = end_op; | |
3509 | if (is_space_char (*op_string)) | |
3510 | ++op_string; | |
3511 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
3512 | { | |
3513 | switch (r->reg_num) | |
3514 | { | |
3515 | case 0: | |
3516 | i.seg[i.mem_operands] = &es; | |
3517 | break; | |
3518 | case 1: | |
3519 | i.seg[i.mem_operands] = &cs; | |
3520 | break; | |
3521 | case 2: | |
3522 | i.seg[i.mem_operands] = &ss; | |
3523 | break; | |
3524 | case 3: | |
3525 | i.seg[i.mem_operands] = &ds; | |
3526 | break; | |
3527 | case 4: | |
3528 | i.seg[i.mem_operands] = &fs; | |
3529 | break; | |
3530 | case 5: | |
3531 | i.seg[i.mem_operands] = &gs; | |
3532 | break; | |
3533 | } | |
252b5132 | 3534 | |
24eab124 | 3535 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
3536 | ++op_string; |
3537 | if (is_space_char (*op_string)) | |
24eab124 | 3538 | ++op_string; |
252b5132 | 3539 | |
24eab124 AM |
3540 | if (!is_digit_char (*op_string) |
3541 | && !is_identifier_char (*op_string) | |
3542 | && *op_string != '(' | |
3543 | && *op_string != ABSOLUTE_PREFIX) | |
3544 | { | |
3545 | as_bad (_("bad memory operand `%s'"), op_string); | |
3546 | return 0; | |
3547 | } | |
47926f60 | 3548 | /* Handle case of %es:*foo. */ |
24eab124 AM |
3549 | if (*op_string == ABSOLUTE_PREFIX) |
3550 | { | |
3551 | ++op_string; | |
3552 | if (is_space_char (*op_string)) | |
3553 | ++op_string; | |
3554 | i.types[this_operand] |= JumpAbsolute; | |
3555 | } | |
3556 | goto do_memory_reference; | |
3557 | } | |
3558 | if (*op_string) | |
3559 | { | |
d0b47220 | 3560 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
3561 | return 0; |
3562 | } | |
3563 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
520dc8e8 | 3564 | i.op[this_operand].regs = r; |
24eab124 AM |
3565 | i.reg_operands++; |
3566 | } | |
af6bdddf AM |
3567 | else if (*op_string == REGISTER_PREFIX) |
3568 | { | |
3569 | as_bad (_("bad register name `%s'"), op_string); | |
3570 | return 0; | |
3571 | } | |
24eab124 | 3572 | else if (*op_string == IMMEDIATE_PREFIX) |
47926f60 | 3573 | { /* ... or an immediate */ |
24eab124 AM |
3574 | ++op_string; |
3575 | if (i.types[this_operand] & JumpAbsolute) | |
3576 | { | |
d0b47220 | 3577 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
3578 | return 0; |
3579 | } | |
3580 | if (!i386_immediate (op_string)) | |
3581 | return 0; | |
3582 | } | |
3583 | else if (is_digit_char (*op_string) | |
3584 | || is_identifier_char (*op_string) | |
3585 | || *op_string == '(' ) | |
3586 | { | |
47926f60 | 3587 | /* This is a memory reference of some sort. */ |
af6bdddf | 3588 | char *base_string; |
252b5132 | 3589 | |
47926f60 | 3590 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
3591 | char *displacement_string_start; |
3592 | char *displacement_string_end; | |
252b5132 | 3593 | |
24eab124 | 3594 | do_memory_reference: |
24eab124 AM |
3595 | if ((i.mem_operands == 1 |
3596 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
3597 | || i.mem_operands == 2) | |
3598 | { | |
3599 | as_bad (_("too many memory references for `%s'"), | |
3600 | current_templates->start->name); | |
3601 | return 0; | |
3602 | } | |
252b5132 | 3603 | |
24eab124 AM |
3604 | /* Check for base index form. We detect the base index form by |
3605 | looking for an ')' at the end of the operand, searching | |
3606 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
3607 | after the '('. */ | |
af6bdddf | 3608 | base_string = op_string + strlen (op_string); |
c3332e24 | 3609 | |
af6bdddf AM |
3610 | --base_string; |
3611 | if (is_space_char (*base_string)) | |
3612 | --base_string; | |
252b5132 | 3613 | |
47926f60 | 3614 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
3615 | displacement_string_start = op_string; |
3616 | displacement_string_end = base_string + 1; | |
252b5132 | 3617 | |
24eab124 AM |
3618 | if (*base_string == ')') |
3619 | { | |
af6bdddf | 3620 | char *temp_string; |
24eab124 AM |
3621 | unsigned int parens_balanced = 1; |
3622 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 3623 | equal, so this loop will not be infinite. */ |
24eab124 AM |
3624 | do |
3625 | { | |
3626 | base_string--; | |
3627 | if (*base_string == ')') | |
3628 | parens_balanced++; | |
3629 | if (*base_string == '(') | |
3630 | parens_balanced--; | |
3631 | } | |
3632 | while (parens_balanced); | |
c3332e24 | 3633 | |
af6bdddf | 3634 | temp_string = base_string; |
c3332e24 | 3635 | |
24eab124 | 3636 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
3637 | ++base_string; |
3638 | if (is_space_char (*base_string)) | |
24eab124 | 3639 | ++base_string; |
252b5132 | 3640 | |
af6bdddf AM |
3641 | if (*base_string == ',' |
3642 | || ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3643 | && (i.base_reg = parse_register (base_string, &end_op)) != NULL)) | |
252b5132 | 3644 | { |
af6bdddf | 3645 | displacement_string_end = temp_string; |
252b5132 | 3646 | |
af6bdddf | 3647 | i.types[this_operand] |= BaseIndex; |
252b5132 | 3648 | |
af6bdddf | 3649 | if (i.base_reg) |
24eab124 | 3650 | { |
24eab124 AM |
3651 | base_string = end_op; |
3652 | if (is_space_char (*base_string)) | |
3653 | ++base_string; | |
af6bdddf AM |
3654 | } |
3655 | ||
3656 | /* There may be an index reg or scale factor here. */ | |
3657 | if (*base_string == ',') | |
3658 | { | |
3659 | ++base_string; | |
3660 | if (is_space_char (*base_string)) | |
3661 | ++base_string; | |
3662 | ||
3663 | if ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3664 | && (i.index_reg = parse_register (base_string, &end_op)) != NULL) | |
24eab124 | 3665 | { |
af6bdddf | 3666 | base_string = end_op; |
24eab124 AM |
3667 | if (is_space_char (*base_string)) |
3668 | ++base_string; | |
af6bdddf AM |
3669 | if (*base_string == ',') |
3670 | { | |
3671 | ++base_string; | |
3672 | if (is_space_char (*base_string)) | |
3673 | ++base_string; | |
3674 | } | |
3675 | else if (*base_string != ')' ) | |
3676 | { | |
3677 | as_bad (_("expecting `,' or `)' after index register in `%s'"), | |
3678 | operand_string); | |
3679 | return 0; | |
3680 | } | |
24eab124 | 3681 | } |
af6bdddf | 3682 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 3683 | { |
af6bdddf | 3684 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
3685 | return 0; |
3686 | } | |
252b5132 | 3687 | |
47926f60 | 3688 | /* Check for scale factor. */ |
af6bdddf AM |
3689 | if (isdigit ((unsigned char) *base_string)) |
3690 | { | |
3691 | if (!i386_scale (base_string)) | |
3692 | return 0; | |
24eab124 | 3693 | |
af6bdddf AM |
3694 | ++base_string; |
3695 | if (is_space_char (*base_string)) | |
3696 | ++base_string; | |
3697 | if (*base_string != ')') | |
3698 | { | |
3699 | as_bad (_("expecting `)' after scale factor in `%s'"), | |
3700 | operand_string); | |
3701 | return 0; | |
3702 | } | |
3703 | } | |
3704 | else if (!i.index_reg) | |
24eab124 | 3705 | { |
af6bdddf AM |
3706 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
3707 | *base_string); | |
24eab124 AM |
3708 | return 0; |
3709 | } | |
3710 | } | |
af6bdddf | 3711 | else if (*base_string != ')') |
24eab124 | 3712 | { |
af6bdddf AM |
3713 | as_bad (_("expecting `,' or `)' after base register in `%s'"), |
3714 | operand_string); | |
24eab124 AM |
3715 | return 0; |
3716 | } | |
c3332e24 | 3717 | } |
af6bdddf | 3718 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 3719 | { |
af6bdddf | 3720 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 3721 | return 0; |
c3332e24 | 3722 | } |
24eab124 AM |
3723 | } |
3724 | ||
3725 | /* If there's an expression beginning the operand, parse it, | |
3726 | assuming displacement_string_start and | |
3727 | displacement_string_end are meaningful. */ | |
3728 | if (displacement_string_start != displacement_string_end) | |
3729 | { | |
3730 | if (!i386_displacement (displacement_string_start, | |
3731 | displacement_string_end)) | |
3732 | return 0; | |
3733 | } | |
3734 | ||
3735 | /* Special case for (%dx) while doing input/output op. */ | |
3736 | if (i.base_reg | |
3737 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) | |
3738 | && i.index_reg == 0 | |
3739 | && i.log2_scale_factor == 0 | |
3740 | && i.seg[i.mem_operands] == 0 | |
3741 | && (i.types[this_operand] & Disp) == 0) | |
3742 | { | |
3743 | i.types[this_operand] = InOutPortReg; | |
3744 | return 1; | |
3745 | } | |
3746 | ||
eecb386c AM |
3747 | if (i386_index_check (operand_string) == 0) |
3748 | return 0; | |
24eab124 AM |
3749 | i.mem_operands++; |
3750 | } | |
3751 | else | |
47926f60 | 3752 | { /* It's not a memory operand; argh! */ |
24eab124 AM |
3753 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
3754 | output_invalid (*op_string), | |
3755 | this_operand + 1, | |
3756 | op_string); | |
3757 | return 0; | |
3758 | } | |
47926f60 | 3759 | return 1; /* Normal return. */ |
252b5132 RH |
3760 | } |
3761 | \f | |
ee7fcc42 AM |
3762 | /* md_estimate_size_before_relax() |
3763 | ||
3764 | Called just before relax() for rs_machine_dependent frags. The x86 | |
3765 | assembler uses these frags to handle variable size jump | |
3766 | instructions. | |
3767 | ||
3768 | Any symbol that is now undefined will not become defined. | |
3769 | Return the correct fr_subtype in the frag. | |
3770 | Return the initial "guess for variable size of frag" to caller. | |
3771 | The guess is actually the growth beyond the fixed part. Whatever | |
3772 | we do to grow the fixed or variable part contributes to our | |
3773 | returned value. */ | |
3774 | ||
252b5132 RH |
3775 | int |
3776 | md_estimate_size_before_relax (fragP, segment) | |
3777 | register fragS *fragP; | |
3778 | register segT segment; | |
3779 | { | |
252b5132 | 3780 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
3781 | check for un-relaxable symbols. On an ELF system, we can't relax |
3782 | an externally visible symbol, because it may be overridden by a | |
3783 | shared library. */ | |
3784 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 3785 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b98ef147 AM |
3786 | || S_IS_EXTERNAL (fragP->fr_symbol) |
3787 | || S_IS_WEAK (fragP->fr_symbol) | |
3788 | #endif | |
3789 | ) | |
252b5132 | 3790 | { |
b98ef147 AM |
3791 | /* Symbol is undefined in this segment, or we need to keep a |
3792 | reloc so that weak symbols can be overridden. */ | |
3793 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f6af82bd AM |
3794 | #ifdef BFD_ASSEMBLER |
3795 | enum bfd_reloc_code_real reloc_type; | |
3796 | #else | |
3797 | int reloc_type; | |
3798 | #endif | |
ee7fcc42 AM |
3799 | unsigned char *opcode; |
3800 | int old_fr_fix; | |
f6af82bd | 3801 | |
ee7fcc42 AM |
3802 | if (fragP->fr_var != NO_RELOC) |
3803 | reloc_type = fragP->fr_var; | |
b98ef147 | 3804 | else if (size == 2) |
f6af82bd AM |
3805 | reloc_type = BFD_RELOC_16_PCREL; |
3806 | else | |
3807 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 3808 | |
ee7fcc42 AM |
3809 | old_fr_fix = fragP->fr_fix; |
3810 | opcode = (unsigned char *) fragP->fr_opcode; | |
3811 | ||
252b5132 RH |
3812 | switch (opcode[0]) |
3813 | { | |
47926f60 KH |
3814 | case JUMP_PC_RELATIVE: |
3815 | /* Make jmp (0xeb) a dword displacement jump. */ | |
3816 | /* dword disp jmp */ | |
3817 | opcode[0] = 0xe9; | |
252b5132 RH |
3818 | fragP->fr_fix += size; |
3819 | fix_new (fragP, old_fr_fix, size, | |
3820 | fragP->fr_symbol, | |
3821 | fragP->fr_offset, 1, | |
f6af82bd | 3822 | reloc_type); |
252b5132 RH |
3823 | break; |
3824 | ||
3825 | default: | |
24eab124 | 3826 | /* This changes the byte-displacement jump 0x7N |
f6af82bd | 3827 | to the dword-displacement jump 0x0f,0x8N. */ |
252b5132 | 3828 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 3829 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
3830 | /* We've added an opcode byte. */ |
3831 | fragP->fr_fix += 1 + size; | |
252b5132 RH |
3832 | fix_new (fragP, old_fr_fix + 1, size, |
3833 | fragP->fr_symbol, | |
3834 | fragP->fr_offset, 1, | |
f6af82bd | 3835 | reloc_type); |
252b5132 RH |
3836 | break; |
3837 | } | |
3838 | frag_wane (fragP); | |
ee7fcc42 | 3839 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 3840 | } |
47926f60 KH |
3841 | /* Guess a short jump. */ |
3842 | return 1; | |
ee7fcc42 AM |
3843 | } |
3844 | ||
47926f60 KH |
3845 | /* Called after relax() is finished. |
3846 | ||
3847 | In: Address of frag. | |
3848 | fr_type == rs_machine_dependent. | |
3849 | fr_subtype is what the address relaxed to. | |
3850 | ||
3851 | Out: Any fixSs and constants are set up. | |
3852 | Caller will turn frag into a ".space 0". */ | |
3853 | ||
252b5132 RH |
3854 | #ifndef BFD_ASSEMBLER |
3855 | void | |
3856 | md_convert_frag (headers, sec, fragP) | |
a04b544b ILT |
3857 | object_headers *headers ATTRIBUTE_UNUSED; |
3858 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
3859 | register fragS *fragP; |
3860 | #else | |
3861 | void | |
3862 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
3863 | bfd *abfd ATTRIBUTE_UNUSED; |
3864 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
3865 | register fragS *fragP; |
3866 | #endif | |
3867 | { | |
3868 | register unsigned char *opcode; | |
3869 | unsigned char *where_to_put_displacement = NULL; | |
847f7ad4 AM |
3870 | offsetT target_address; |
3871 | offsetT opcode_address; | |
252b5132 | 3872 | unsigned int extension = 0; |
847f7ad4 | 3873 | offsetT displacement_from_opcode_start; |
252b5132 RH |
3874 | |
3875 | opcode = (unsigned char *) fragP->fr_opcode; | |
3876 | ||
47926f60 | 3877 | /* Address we want to reach in file space. */ |
252b5132 | 3878 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
47926f60 KH |
3879 | #ifdef BFD_ASSEMBLER |
3880 | /* Not needed otherwise? */ | |
49309057 | 3881 | target_address += symbol_get_frag (fragP->fr_symbol)->fr_address; |
252b5132 RH |
3882 | #endif |
3883 | ||
47926f60 | 3884 | /* Address opcode resides at in file space. */ |
252b5132 RH |
3885 | opcode_address = fragP->fr_address + fragP->fr_fix; |
3886 | ||
47926f60 | 3887 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
3888 | displacement_from_opcode_start = target_address - opcode_address; |
3889 | ||
3890 | switch (fragP->fr_subtype) | |
3891 | { | |
3892 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL): | |
3893 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL16): | |
3894 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL): | |
3895 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL16): | |
47926f60 KH |
3896 | /* Don't have to change opcode. */ |
3897 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 RH |
3898 | where_to_put_displacement = &opcode[1]; |
3899 | break; | |
3900 | ||
3901 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): | |
47926f60 | 3902 | extension = 5; /* 2 opcode + 4 displacement */ |
252b5132 RH |
3903 | opcode[1] = opcode[0] + 0x10; |
3904 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
3905 | where_to_put_displacement = &opcode[2]; | |
3906 | break; | |
3907 | ||
3908 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
47926f60 | 3909 | extension = 4; /* 1 opcode + 4 displacement */ |
252b5132 RH |
3910 | opcode[0] = 0xe9; |
3911 | where_to_put_displacement = &opcode[1]; | |
3912 | break; | |
3913 | ||
3914 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): | |
47926f60 | 3915 | extension = 3; /* 2 opcode + 2 displacement */ |
252b5132 RH |
3916 | opcode[1] = opcode[0] + 0x10; |
3917 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
3918 | where_to_put_displacement = &opcode[2]; | |
3919 | break; | |
3920 | ||
3921 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): | |
47926f60 | 3922 | extension = 2; /* 1 opcode + 2 displacement */ |
252b5132 RH |
3923 | opcode[0] = 0xe9; |
3924 | where_to_put_displacement = &opcode[1]; | |
3925 | break; | |
3926 | ||
3927 | default: | |
3928 | BAD_CASE (fragP->fr_subtype); | |
3929 | break; | |
3930 | } | |
47926f60 | 3931 | /* Now put displacement after opcode. */ |
252b5132 RH |
3932 | md_number_to_chars ((char *) where_to_put_displacement, |
3933 | (valueT) (displacement_from_opcode_start - extension), | |
3934 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
3935 | fragP->fr_fix += extension; | |
3936 | } | |
3937 | \f | |
47926f60 KH |
3938 | /* Size of byte displacement jmp. */ |
3939 | int md_short_jump_size = 2; | |
3940 | ||
3941 | /* Size of dword displacement jmp. */ | |
3942 | int md_long_jump_size = 5; | |
252b5132 | 3943 | |
47926f60 KH |
3944 | /* Size of relocation record. */ |
3945 | const int md_reloc_size = 8; | |
252b5132 RH |
3946 | |
3947 | void | |
3948 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
3949 | char *ptr; | |
3950 | addressT from_addr, to_addr; | |
ab9da554 ILT |
3951 | fragS *frag ATTRIBUTE_UNUSED; |
3952 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 3953 | { |
847f7ad4 | 3954 | offsetT offset; |
252b5132 RH |
3955 | |
3956 | offset = to_addr - (from_addr + 2); | |
47926f60 KH |
3957 | /* Opcode for byte-disp jump. */ |
3958 | md_number_to_chars (ptr, (valueT) 0xeb, 1); | |
252b5132 RH |
3959 | md_number_to_chars (ptr + 1, (valueT) offset, 1); |
3960 | } | |
3961 | ||
3962 | void | |
3963 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
3964 | char *ptr; | |
3965 | addressT from_addr, to_addr; | |
a38cf1db AM |
3966 | fragS *frag ATTRIBUTE_UNUSED; |
3967 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 3968 | { |
847f7ad4 | 3969 | offsetT offset; |
252b5132 | 3970 | |
a38cf1db AM |
3971 | offset = to_addr - (from_addr + 5); |
3972 | md_number_to_chars (ptr, (valueT) 0xe9, 1); | |
3973 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
252b5132 RH |
3974 | } |
3975 | \f | |
3976 | /* Apply a fixup (fixS) to segment data, once it has been determined | |
3977 | by our caller that we have all the info we need to fix it up. | |
3978 | ||
3979 | On the 386, immediates, displacements, and data pointers are all in | |
3980 | the same (little-endian) format, so we don't need to care about which | |
3981 | we are handling. */ | |
3982 | ||
3983 | int | |
3984 | md_apply_fix3 (fixP, valp, seg) | |
47926f60 KH |
3985 | /* The fix we're to put in. */ |
3986 | fixS *fixP; | |
3987 | ||
3988 | /* Pointer to the value of the bits. */ | |
3989 | valueT *valp; | |
3990 | ||
3991 | /* Segment fix is from. */ | |
3992 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 RH |
3993 | { |
3994 | register char *p = fixP->fx_where + fixP->fx_frag->fr_literal; | |
3995 | valueT value = *valp; | |
3996 | ||
e1b283bb | 3997 | #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) |
93382f6d AM |
3998 | if (fixP->fx_pcrel) |
3999 | { | |
4000 | switch (fixP->fx_r_type) | |
4001 | { | |
5865bb77 ILT |
4002 | default: |
4003 | break; | |
4004 | ||
93382f6d AM |
4005 | case BFD_RELOC_32: |
4006 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
4007 | break; | |
4008 | case BFD_RELOC_16: | |
4009 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
4010 | break; | |
4011 | case BFD_RELOC_8: | |
4012 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
4013 | break; | |
4014 | } | |
4015 | } | |
252b5132 | 4016 | |
0723899b ILT |
4017 | /* This is a hack. There should be a better way to handle this. |
4018 | This covers for the fact that bfd_install_relocation will | |
4019 | subtract the current location (for partial_inplace, PC relative | |
4020 | relocations); see more below. */ | |
93382f6d AM |
4021 | if ((fixP->fx_r_type == BFD_RELOC_32_PCREL |
4022 | || fixP->fx_r_type == BFD_RELOC_16_PCREL | |
4023 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
4024 | && fixP->fx_addsy) | |
252b5132 RH |
4025 | { |
4026 | #ifndef OBJ_AOUT | |
4027 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4028 | #ifdef TE_PE | |
4029 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
4030 | #endif | |
4031 | ) | |
4032 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4033 | #endif | |
4034 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2f66722d | 4035 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
252b5132 | 4036 | { |
2f66722d AM |
4037 | segT fseg = S_GET_SEGMENT (fixP->fx_addsy); |
4038 | ||
4039 | if ((fseg == seg | |
4040 | || (symbol_section_p (fixP->fx_addsy) | |
4041 | && fseg != absolute_section)) | |
4042 | && ! S_IS_EXTERNAL (fixP->fx_addsy) | |
4043 | && ! S_IS_WEAK (fixP->fx_addsy) | |
4044 | && S_IS_DEFINED (fixP->fx_addsy) | |
4045 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
4046 | { | |
4047 | /* Yes, we add the values in twice. This is because | |
4048 | bfd_perform_relocation subtracts them out again. I think | |
4049 | bfd_perform_relocation is broken, but I don't dare change | |
4050 | it. FIXME. */ | |
4051 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4052 | } | |
252b5132 RH |
4053 | } |
4054 | #endif | |
4055 | #if defined (OBJ_COFF) && defined (TE_PE) | |
4056 | /* For some reason, the PE format does not store a section | |
24eab124 | 4057 | address offset for a PC relative symbol. */ |
252b5132 RH |
4058 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) |
4059 | value += md_pcrel_from (fixP); | |
4060 | #endif | |
4061 | } | |
4062 | ||
4063 | /* Fix a few things - the dynamic linker expects certain values here, | |
47926f60 | 4064 | and we must not dissappoint it. */ |
252b5132 RH |
4065 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4066 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4067 | && fixP->fx_addsy) | |
47926f60 KH |
4068 | switch (fixP->fx_r_type) |
4069 | { | |
4070 | case BFD_RELOC_386_PLT32: | |
4071 | /* Make the jump instruction point to the address of the operand. At | |
4072 | runtime we merely add the offset to the actual PLT entry. */ | |
4073 | value = -4; | |
4074 | break; | |
4075 | case BFD_RELOC_386_GOTPC: | |
4076 | ||
4077 | /* This is tough to explain. We end up with this one if we have | |
252b5132 RH |
4078 | * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal |
4079 | * here is to obtain the absolute address of the GOT, and it is strongly | |
4080 | * preferable from a performance point of view to avoid using a runtime | |
c3332e24 | 4081 | * relocation for this. The actual sequence of instructions often look |
252b5132 | 4082 | * something like: |
c3332e24 | 4083 | * |
24eab124 | 4084 | * call .L66 |
252b5132 | 4085 | * .L66: |
24eab124 AM |
4086 | * popl %ebx |
4087 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
c3332e24 | 4088 | * |
24eab124 | 4089 | * The call and pop essentially return the absolute address of |
252b5132 RH |
4090 | * the label .L66 and store it in %ebx. The linker itself will |
4091 | * ultimately change the first operand of the addl so that %ebx points to | |
4092 | * the GOT, but to keep things simple, the .o file must have this operand | |
4093 | * set so that it generates not the absolute address of .L66, but the | |
4094 | * absolute address of itself. This allows the linker itself simply | |
4095 | * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be | |
4096 | * added in, and the addend of the relocation is stored in the operand | |
4097 | * field for the instruction itself. | |
c3332e24 | 4098 | * |
24eab124 | 4099 | * Our job here is to fix the operand so that it would add the correct |
252b5132 RH |
4100 | * offset so that %ebx would point to itself. The thing that is tricky is |
4101 | * that .-.L66 will point to the beginning of the instruction, so we need | |
4102 | * to further modify the operand so that it will point to itself. | |
4103 | * There are other cases where you have something like: | |
c3332e24 | 4104 | * |
24eab124 | 4105 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] |
c3332e24 | 4106 | * |
252b5132 | 4107 | * and here no correction would be required. Internally in the assembler |
c3332e24 | 4108 | * we treat operands of this form as not being pcrel since the '.' is |
252b5132 RH |
4109 | * explicitly mentioned, and I wonder whether it would simplify matters |
4110 | * to do it this way. Who knows. In earlier versions of the PIC patches, | |
4111 | * the pcrel_adjust field was used to store the correction, but since the | |
47926f60 KH |
4112 | * expression is not pcrel, I felt it would be confusing to do it this |
4113 | * way. */ | |
4114 | ||
4115 | value -= 1; | |
4116 | break; | |
4117 | case BFD_RELOC_386_GOT32: | |
4118 | value = 0; /* Fully resolved at runtime. No addend. */ | |
4119 | break; | |
4120 | case BFD_RELOC_386_GOTOFF: | |
4121 | break; | |
4122 | ||
4123 | case BFD_RELOC_VTABLE_INHERIT: | |
4124 | case BFD_RELOC_VTABLE_ENTRY: | |
4125 | fixP->fx_done = 0; | |
4126 | return 1; | |
4127 | ||
4128 | default: | |
4129 | break; | |
4130 | } | |
4131 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
93382f6d | 4132 | *valp = value; |
47926f60 | 4133 | #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */ |
252b5132 RH |
4134 | md_number_to_chars (p, value, fixP->fx_size); |
4135 | ||
4136 | return 1; | |
4137 | } | |
252b5132 | 4138 | \f |
252b5132 RH |
4139 | #define MAX_LITTLENUMS 6 |
4140 | ||
47926f60 KH |
4141 | /* Turn the string pointed to by litP into a floating point constant |
4142 | of type TYPE, and emit the appropriate bytes. The number of | |
4143 | LITTLENUMS emitted is stored in *SIZEP. An error message is | |
4144 | returned, or NULL on OK. */ | |
4145 | ||
252b5132 RH |
4146 | char * |
4147 | md_atof (type, litP, sizeP) | |
2ab9b79e | 4148 | int type; |
252b5132 RH |
4149 | char *litP; |
4150 | int *sizeP; | |
4151 | { | |
4152 | int prec; | |
4153 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4154 | LITTLENUM_TYPE *wordP; | |
4155 | char *t; | |
4156 | ||
4157 | switch (type) | |
4158 | { | |
4159 | case 'f': | |
4160 | case 'F': | |
4161 | prec = 2; | |
4162 | break; | |
4163 | ||
4164 | case 'd': | |
4165 | case 'D': | |
4166 | prec = 4; | |
4167 | break; | |
4168 | ||
4169 | case 'x': | |
4170 | case 'X': | |
4171 | prec = 5; | |
4172 | break; | |
4173 | ||
4174 | default: | |
4175 | *sizeP = 0; | |
4176 | return _("Bad call to md_atof ()"); | |
4177 | } | |
4178 | t = atof_ieee (input_line_pointer, type, words); | |
4179 | if (t) | |
4180 | input_line_pointer = t; | |
4181 | ||
4182 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
4183 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with | |
4184 | the bigendian 386. */ | |
4185 | for (wordP = words + prec - 1; prec--;) | |
4186 | { | |
4187 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); | |
4188 | litP += sizeof (LITTLENUM_TYPE); | |
4189 | } | |
4190 | return 0; | |
4191 | } | |
4192 | \f | |
4193 | char output_invalid_buf[8]; | |
4194 | ||
252b5132 RH |
4195 | static char * |
4196 | output_invalid (c) | |
4197 | int c; | |
4198 | { | |
4199 | if (isprint (c)) | |
4200 | sprintf (output_invalid_buf, "'%c'", c); | |
4201 | else | |
4202 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
4203 | return output_invalid_buf; | |
4204 | } | |
4205 | ||
af6bdddf | 4206 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
4207 | |
4208 | static const reg_entry * | |
4209 | parse_register (reg_string, end_op) | |
4210 | char *reg_string; | |
4211 | char **end_op; | |
4212 | { | |
af6bdddf AM |
4213 | char *s = reg_string; |
4214 | char *p; | |
252b5132 RH |
4215 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
4216 | const reg_entry *r; | |
4217 | ||
4218 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
4219 | if (*s == REGISTER_PREFIX) | |
4220 | ++s; | |
4221 | ||
4222 | if (is_space_char (*s)) | |
4223 | ++s; | |
4224 | ||
4225 | p = reg_name_given; | |
af6bdddf | 4226 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
4227 | { |
4228 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
4229 | return (const reg_entry *) NULL; |
4230 | s++; | |
252b5132 RH |
4231 | } |
4232 | ||
af6bdddf | 4233 | *end_op = s; |
252b5132 RH |
4234 | |
4235 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
4236 | ||
5f47d35b | 4237 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 4238 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 4239 | { |
5f47d35b AM |
4240 | if (is_space_char (*s)) |
4241 | ++s; | |
4242 | if (*s == '(') | |
4243 | { | |
af6bdddf | 4244 | ++s; |
5f47d35b AM |
4245 | if (is_space_char (*s)) |
4246 | ++s; | |
4247 | if (*s >= '0' && *s <= '7') | |
4248 | { | |
4249 | r = &i386_float_regtab[*s - '0']; | |
af6bdddf | 4250 | ++s; |
5f47d35b AM |
4251 | if (is_space_char (*s)) |
4252 | ++s; | |
4253 | if (*s == ')') | |
4254 | { | |
4255 | *end_op = s + 1; | |
4256 | return r; | |
4257 | } | |
5f47d35b | 4258 | } |
47926f60 | 4259 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
4260 | return (const reg_entry *) NULL; |
4261 | } | |
4262 | } | |
4263 | ||
252b5132 RH |
4264 | return r; |
4265 | } | |
4266 | \f | |
4cc782b5 | 4267 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
65172ab8 | 4268 | const char *md_shortopts = "kVQ:sq"; |
252b5132 | 4269 | #else |
65172ab8 | 4270 | const char *md_shortopts = "q"; |
252b5132 RH |
4271 | #endif |
4272 | struct option md_longopts[] = { | |
4273 | {NULL, no_argument, NULL, 0} | |
4274 | }; | |
4275 | size_t md_longopts_size = sizeof (md_longopts); | |
4276 | ||
4277 | int | |
4278 | md_parse_option (c, arg) | |
4279 | int c; | |
ab9da554 | 4280 | char *arg ATTRIBUTE_UNUSED; |
252b5132 RH |
4281 | { |
4282 | switch (c) | |
4283 | { | |
a38cf1db AM |
4284 | case 'q': |
4285 | quiet_warnings = 1; | |
252b5132 RH |
4286 | break; |
4287 | ||
4288 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
4289 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
4290 | should be emitted or not. FIXME: Not implemented. */ | |
4291 | case 'Q': | |
252b5132 RH |
4292 | break; |
4293 | ||
4294 | /* -V: SVR4 argument to print version ID. */ | |
4295 | case 'V': | |
4296 | print_version_id (); | |
4297 | break; | |
4298 | ||
a38cf1db AM |
4299 | /* -k: Ignore for FreeBSD compatibility. */ |
4300 | case 'k': | |
252b5132 | 4301 | break; |
4cc782b5 ILT |
4302 | |
4303 | case 's': | |
4304 | /* -s: On i386 Solaris, this tells the native assembler to use | |
4305 | .stab instead of .stab.excl. We always use .stab anyhow. */ | |
4306 | break; | |
252b5132 RH |
4307 | #endif |
4308 | ||
4309 | default: | |
4310 | return 0; | |
4311 | } | |
4312 | return 1; | |
4313 | } | |
4314 | ||
4315 | void | |
4316 | md_show_usage (stream) | |
4317 | FILE *stream; | |
4318 | { | |
4cc782b5 ILT |
4319 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4320 | fprintf (stream, _("\ | |
a38cf1db AM |
4321 | -Q ignored\n\ |
4322 | -V print assembler version number\n\ | |
4323 | -k ignored\n\ | |
4324 | -q quieten some warnings\n\ | |
4325 | -s ignored\n")); | |
4326 | #else | |
4327 | fprintf (stream, _("\ | |
4328 | -q quieten some warnings\n")); | |
4cc782b5 | 4329 | #endif |
252b5132 RH |
4330 | } |
4331 | ||
4332 | #ifdef BFD_ASSEMBLER | |
4c63da97 AM |
4333 | #if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \ |
4334 | || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \ | |
4335 | || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT))) | |
252b5132 RH |
4336 | |
4337 | /* Pick the target format to use. */ | |
4338 | ||
47926f60 | 4339 | const char * |
252b5132 RH |
4340 | i386_target_format () |
4341 | { | |
4342 | switch (OUTPUT_FLAVOR) | |
4343 | { | |
4c63da97 AM |
4344 | #ifdef OBJ_MAYBE_AOUT |
4345 | case bfd_target_aout_flavour: | |
47926f60 | 4346 | return AOUT_TARGET_FORMAT; |
4c63da97 AM |
4347 | #endif |
4348 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
4349 | case bfd_target_coff_flavour: |
4350 | return "coff-i386"; | |
4c63da97 AM |
4351 | #endif |
4352 | #ifdef OBJ_MAYBE_ELF | |
252b5132 RH |
4353 | case bfd_target_elf_flavour: |
4354 | return "elf32-i386"; | |
4c63da97 | 4355 | #endif |
252b5132 RH |
4356 | default: |
4357 | abort (); | |
4358 | return NULL; | |
4359 | } | |
4360 | } | |
4361 | ||
47926f60 KH |
4362 | #endif /* OBJ_MAYBE_ more than one */ |
4363 | #endif /* BFD_ASSEMBLER */ | |
252b5132 | 4364 | \f |
252b5132 RH |
4365 | symbolS * |
4366 | md_undefined_symbol (name) | |
4367 | char *name; | |
4368 | { | |
18dc2407 ILT |
4369 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
4370 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
4371 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
4372 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
4373 | { |
4374 | if (!GOT_symbol) | |
4375 | { | |
4376 | if (symbol_find (name)) | |
4377 | as_bad (_("GOT already in symbol table")); | |
4378 | GOT_symbol = symbol_new (name, undefined_section, | |
4379 | (valueT) 0, &zero_address_frag); | |
4380 | }; | |
4381 | return GOT_symbol; | |
4382 | } | |
252b5132 RH |
4383 | return 0; |
4384 | } | |
4385 | ||
4386 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 4387 | |
252b5132 RH |
4388 | valueT |
4389 | md_section_align (segment, size) | |
ab9da554 | 4390 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
4391 | valueT size; |
4392 | { | |
252b5132 | 4393 | #ifdef BFD_ASSEMBLER |
4c63da97 AM |
4394 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
4395 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
4396 | { | |
4397 | /* For a.out, force the section size to be aligned. If we don't do | |
4398 | this, BFD will align it for us, but it will not write out the | |
4399 | final bytes of the section. This may be a bug in BFD, but it is | |
4400 | easier to fix it here since that is how the other a.out targets | |
4401 | work. */ | |
4402 | int align; | |
4403 | ||
4404 | align = bfd_get_section_alignment (stdoutput, segment); | |
4405 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
4406 | } | |
252b5132 RH |
4407 | #endif |
4408 | #endif | |
4409 | ||
4410 | return size; | |
4411 | } | |
4412 | ||
4413 | /* On the i386, PC-relative offsets are relative to the start of the | |
4414 | next instruction. That is, the address of the offset, plus its | |
4415 | size, since the offset is always the last part of the insn. */ | |
4416 | ||
4417 | long | |
4418 | md_pcrel_from (fixP) | |
4419 | fixS *fixP; | |
4420 | { | |
4421 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
4422 | } | |
4423 | ||
4424 | #ifndef I386COFF | |
4425 | ||
4426 | static void | |
4427 | s_bss (ignore) | |
ab9da554 | 4428 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
4429 | { |
4430 | register int temp; | |
4431 | ||
4432 | temp = get_absolute_expression (); | |
4433 | subseg_set (bss_section, (subsegT) temp); | |
4434 | demand_empty_rest_of_line (); | |
4435 | } | |
4436 | ||
4437 | #endif | |
4438 | ||
252b5132 RH |
4439 | #ifdef BFD_ASSEMBLER |
4440 | ||
4441 | void | |
4442 | i386_validate_fix (fixp) | |
4443 | fixS *fixp; | |
4444 | { | |
4445 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
4446 | { | |
4447 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
4448 | fixp->fx_subsy = 0; | |
4449 | } | |
4450 | } | |
4451 | ||
252b5132 RH |
4452 | arelent * |
4453 | tc_gen_reloc (section, fixp) | |
ab9da554 | 4454 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
4455 | fixS *fixp; |
4456 | { | |
4457 | arelent *rel; | |
4458 | bfd_reloc_code_real_type code; | |
4459 | ||
4460 | switch (fixp->fx_r_type) | |
4461 | { | |
4462 | case BFD_RELOC_386_PLT32: | |
4463 | case BFD_RELOC_386_GOT32: | |
4464 | case BFD_RELOC_386_GOTOFF: | |
4465 | case BFD_RELOC_386_GOTPC: | |
4466 | case BFD_RELOC_RVA: | |
4467 | case BFD_RELOC_VTABLE_ENTRY: | |
4468 | case BFD_RELOC_VTABLE_INHERIT: | |
4469 | code = fixp->fx_r_type; | |
4470 | break; | |
4471 | default: | |
93382f6d | 4472 | if (fixp->fx_pcrel) |
252b5132 | 4473 | { |
93382f6d AM |
4474 | switch (fixp->fx_size) |
4475 | { | |
4476 | default: | |
d0b47220 | 4477 | as_bad (_("can not do %d byte pc-relative relocation"), |
93382f6d AM |
4478 | fixp->fx_size); |
4479 | code = BFD_RELOC_32_PCREL; | |
4480 | break; | |
4481 | case 1: code = BFD_RELOC_8_PCREL; break; | |
4482 | case 2: code = BFD_RELOC_16_PCREL; break; | |
4483 | case 4: code = BFD_RELOC_32_PCREL; break; | |
4484 | } | |
4485 | } | |
4486 | else | |
4487 | { | |
4488 | switch (fixp->fx_size) | |
4489 | { | |
4490 | default: | |
d0b47220 | 4491 | as_bad (_("can not do %d byte relocation"), fixp->fx_size); |
93382f6d AM |
4492 | code = BFD_RELOC_32; |
4493 | break; | |
4494 | case 1: code = BFD_RELOC_8; break; | |
4495 | case 2: code = BFD_RELOC_16; break; | |
4496 | case 4: code = BFD_RELOC_32; break; | |
4497 | } | |
252b5132 RH |
4498 | } |
4499 | break; | |
4500 | } | |
252b5132 RH |
4501 | |
4502 | if (code == BFD_RELOC_32 | |
4503 | && GOT_symbol | |
4504 | && fixp->fx_addsy == GOT_symbol) | |
4505 | code = BFD_RELOC_386_GOTPC; | |
4506 | ||
4507 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
4508 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
4509 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
4510 | |
4511 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
4512 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
4513 | vtable entry to be used in the relocation's section offset. */ | |
4514 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
4515 | rel->address = fixp->fx_offset; | |
4516 | ||
4517 | if (fixp->fx_pcrel) | |
4518 | rel->addend = fixp->fx_addnumber; | |
4519 | else | |
4520 | rel->addend = 0; | |
4521 | ||
4522 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); | |
4523 | if (rel->howto == NULL) | |
4524 | { | |
4525 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 4526 | _("cannot represent relocation type %s"), |
252b5132 RH |
4527 | bfd_get_reloc_code_name (code)); |
4528 | /* Set howto to a garbage value so that we can keep going. */ | |
4529 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
4530 | assert (rel->howto != NULL); | |
4531 | } | |
4532 | ||
4533 | return rel; | |
4534 | } | |
4535 | ||
47926f60 | 4536 | #else /* ! BFD_ASSEMBLER */ |
252b5132 RH |
4537 | |
4538 | #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) | |
4539 | void | |
4540 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) | |
4541 | char *where; | |
4542 | fixS *fixP; | |
4543 | relax_addressT segment_address_in_file; | |
4544 | { | |
47926f60 KH |
4545 | /* In: length of relocation (or of address) in chars: 1, 2 or 4. |
4546 | Out: GNU LD relocation length code: 0, 1, or 2. */ | |
252b5132 | 4547 | |
47926f60 | 4548 | static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 }; |
252b5132 RH |
4549 | long r_symbolnum; |
4550 | ||
4551 | know (fixP->fx_addsy != NULL); | |
4552 | ||
4553 | md_number_to_chars (where, | |
4554 | (valueT) (fixP->fx_frag->fr_address | |
4555 | + fixP->fx_where - segment_address_in_file), | |
4556 | 4); | |
4557 | ||
4558 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) | |
4559 | ? S_GET_TYPE (fixP->fx_addsy) | |
4560 | : fixP->fx_addsy->sy_number); | |
4561 | ||
4562 | where[6] = (r_symbolnum >> 16) & 0x0ff; | |
4563 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
4564 | where[4] = r_symbolnum & 0x0ff; | |
4565 | where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) | |
4566 | | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) | |
4567 | | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); | |
4568 | } | |
4569 | ||
47926f60 | 4570 | #endif /* OBJ_AOUT or OBJ_BOUT. */ |
252b5132 RH |
4571 | |
4572 | #if defined (I386COFF) | |
4573 | ||
4574 | short | |
4575 | tc_coff_fix2rtype (fixP) | |
4576 | fixS *fixP; | |
4577 | { | |
4578 | if (fixP->fx_r_type == R_IMAGEBASE) | |
4579 | return R_IMAGEBASE; | |
4580 | ||
4581 | return (fixP->fx_pcrel ? | |
4582 | (fixP->fx_size == 1 ? R_PCRBYTE : | |
4583 | fixP->fx_size == 2 ? R_PCRWORD : | |
4584 | R_PCRLONG) : | |
4585 | (fixP->fx_size == 1 ? R_RELBYTE : | |
4586 | fixP->fx_size == 2 ? R_RELWORD : | |
4587 | R_DIR32)); | |
4588 | } | |
4589 | ||
4590 | int | |
4591 | tc_coff_sizemachdep (frag) | |
4592 | fragS *frag; | |
4593 | { | |
4594 | if (frag->fr_next) | |
4595 | return (frag->fr_next->fr_address - frag->fr_address); | |
4596 | else | |
4597 | return 0; | |
4598 | } | |
4599 | ||
47926f60 | 4600 | #endif /* I386COFF */ |
252b5132 | 4601 | |
47926f60 | 4602 | #endif /* ! BFD_ASSEMBLER */ |