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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
2571583a | 2 | Copyright (C) 1989-2017 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
252b5132 RH |
36 | #ifndef REGISTER_WARNINGS |
37 | #define REGISTER_WARNINGS 1 | |
38 | #endif | |
39 | ||
c3332e24 | 40 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 41 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
42 | #endif |
43 | ||
29b0f896 AM |
44 | #ifndef DEFAULT_ARCH |
45 | #define DEFAULT_ARCH "i386" | |
246fcdee | 46 | #endif |
252b5132 | 47 | |
edde18a5 AM |
48 | #ifndef INLINE |
49 | #if __GNUC__ >= 2 | |
50 | #define INLINE __inline__ | |
51 | #else | |
52 | #define INLINE | |
53 | #endif | |
54 | #endif | |
55 | ||
6305a203 L |
56 | /* Prefixes will be emitted in the order defined below. |
57 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
58 | instruction, and so must come before any prefixes. | |
59 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 60 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
61 | #define WAIT_PREFIX 0 |
62 | #define SEG_PREFIX 1 | |
63 | #define ADDR_PREFIX 2 | |
64 | #define DATA_PREFIX 3 | |
c32fa91d | 65 | #define REP_PREFIX 4 |
42164a71 | 66 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 67 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 68 | #define LOCK_PREFIX 5 |
04ef582a L |
69 | /* Only one of NOTRACK_PREFIX and SEG_PREFIX can be used at the same |
70 | time. */ | |
71 | #define NOTRACK_PREFIX 6 | |
72 | #define REX_PREFIX 7 /* must come last. */ | |
73 | #define MAX_PREFIXES 8 /* max prefixes per opcode */ | |
6305a203 L |
74 | |
75 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
76 | #define REGISTER_PREFIX '%' | |
77 | #define IMMEDIATE_PREFIX '$' | |
78 | #define ABSOLUTE_PREFIX '*' | |
79 | ||
80 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
81 | memory operand size in Intel syntax. */ | |
82 | #define WORD_MNEM_SUFFIX 'w' | |
83 | #define BYTE_MNEM_SUFFIX 'b' | |
84 | #define SHORT_MNEM_SUFFIX 's' | |
85 | #define LONG_MNEM_SUFFIX 'l' | |
86 | #define QWORD_MNEM_SUFFIX 'q' | |
87 | #define XMMWORD_MNEM_SUFFIX 'x' | |
c0f3af97 | 88 | #define YMMWORD_MNEM_SUFFIX 'y' |
43234a1e | 89 | #define ZMMWORD_MNEM_SUFFIX 'z' |
6305a203 L |
90 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
91 | in instructions. */ | |
92 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
93 | ||
94 | #define END_OF_INSN '\0' | |
95 | ||
96 | /* | |
97 | 'templates' is for grouping together 'template' structures for opcodes | |
98 | of the same name. This is only used for storing the insns in the grand | |
99 | ole hash table of insns. | |
100 | The templates themselves start at START and range up to (but not including) | |
101 | END. | |
102 | */ | |
103 | typedef struct | |
104 | { | |
d3ce72d0 NC |
105 | const insn_template *start; |
106 | const insn_template *end; | |
6305a203 L |
107 | } |
108 | templates; | |
109 | ||
110 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
111 | typedef struct | |
112 | { | |
113 | unsigned int regmem; /* codes register or memory operand */ | |
114 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
115 | unsigned int mode; /* how to interpret regmem & reg */ | |
116 | } | |
117 | modrm_byte; | |
118 | ||
119 | /* x86-64 extension prefix. */ | |
120 | typedef int rex_byte; | |
121 | ||
6305a203 L |
122 | /* 386 opcode byte to code indirect addressing. */ |
123 | typedef struct | |
124 | { | |
125 | unsigned base; | |
126 | unsigned index; | |
127 | unsigned scale; | |
128 | } | |
129 | sib_byte; | |
130 | ||
6305a203 L |
131 | /* x86 arch names, types and features */ |
132 | typedef struct | |
133 | { | |
134 | const char *name; /* arch name */ | |
8a2c8fef | 135 | unsigned int len; /* arch string length */ |
6305a203 L |
136 | enum processor_type type; /* arch type */ |
137 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 138 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
139 | } |
140 | arch_entry; | |
141 | ||
293f5f65 L |
142 | /* Used to turn off indicated flags. */ |
143 | typedef struct | |
144 | { | |
145 | const char *name; /* arch name */ | |
146 | unsigned int len; /* arch string length */ | |
147 | i386_cpu_flags flags; /* cpu feature flags */ | |
148 | } | |
149 | noarch_entry; | |
150 | ||
78f12dd3 | 151 | static void update_code_flag (int, int); |
e3bb37b5 L |
152 | static void set_code_flag (int); |
153 | static void set_16bit_gcc_code_flag (int); | |
154 | static void set_intel_syntax (int); | |
1efbbeb4 | 155 | static void set_intel_mnemonic (int); |
db51cc60 | 156 | static void set_allow_index_reg (int); |
7bab8ab5 | 157 | static void set_check (int); |
e3bb37b5 | 158 | static void set_cpu_arch (int); |
6482c264 | 159 | #ifdef TE_PE |
e3bb37b5 | 160 | static void pe_directive_secrel (int); |
6482c264 | 161 | #endif |
e3bb37b5 L |
162 | static void signed_cons (int); |
163 | static char *output_invalid (int c); | |
ee86248c JB |
164 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
165 | const char *); | |
166 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
167 | const char *); | |
a7619375 | 168 | static int i386_att_operand (char *); |
e3bb37b5 | 169 | static int i386_intel_operand (char *, int); |
ee86248c JB |
170 | static int i386_intel_simplify (expressionS *); |
171 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
172 | static const reg_entry *parse_register (char *, char **); |
173 | static char *parse_insn (char *, char *); | |
174 | static char *parse_operands (char *, const char *); | |
175 | static void swap_operands (void); | |
4d456e3d | 176 | static void swap_2_operands (int, int); |
e3bb37b5 L |
177 | static void optimize_imm (void); |
178 | static void optimize_disp (void); | |
83b16ac6 | 179 | static const insn_template *match_template (char); |
e3bb37b5 L |
180 | static int check_string (void); |
181 | static int process_suffix (void); | |
182 | static int check_byte_reg (void); | |
183 | static int check_long_reg (void); | |
184 | static int check_qword_reg (void); | |
185 | static int check_word_reg (void); | |
186 | static int finalize_imm (void); | |
187 | static int process_operands (void); | |
188 | static const seg_entry *build_modrm_byte (void); | |
189 | static void output_insn (void); | |
190 | static void output_imm (fragS *, offsetT); | |
191 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 192 | #ifndef I386COFF |
e3bb37b5 | 193 | static void s_bss (int); |
252b5132 | 194 | #endif |
17d4e2a2 L |
195 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
196 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
197 | #endif | |
252b5132 | 198 | |
a847613f | 199 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 200 | |
43234a1e L |
201 | /* This struct describes rounding control and SAE in the instruction. */ |
202 | struct RC_Operation | |
203 | { | |
204 | enum rc_type | |
205 | { | |
206 | rne = 0, | |
207 | rd, | |
208 | ru, | |
209 | rz, | |
210 | saeonly | |
211 | } type; | |
212 | int operand; | |
213 | }; | |
214 | ||
215 | static struct RC_Operation rc_op; | |
216 | ||
217 | /* The struct describes masking, applied to OPERAND in the instruction. | |
218 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
219 | whether merging or zeroing mask is used. */ | |
220 | struct Mask_Operation | |
221 | { | |
222 | const reg_entry *mask; | |
223 | unsigned int zeroing; | |
224 | /* The operand where this operation is associated. */ | |
225 | int operand; | |
226 | }; | |
227 | ||
228 | static struct Mask_Operation mask_op; | |
229 | ||
230 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
231 | broadcast factor. */ | |
232 | struct Broadcast_Operation | |
233 | { | |
234 | /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */ | |
235 | int type; | |
236 | ||
237 | /* Index of broadcasted operand. */ | |
238 | int operand; | |
239 | }; | |
240 | ||
241 | static struct Broadcast_Operation broadcast_op; | |
242 | ||
c0f3af97 L |
243 | /* VEX prefix. */ |
244 | typedef struct | |
245 | { | |
43234a1e L |
246 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
247 | unsigned char bytes[4]; | |
c0f3af97 L |
248 | unsigned int length; |
249 | /* Destination or source register specifier. */ | |
250 | const reg_entry *register_specifier; | |
251 | } vex_prefix; | |
252 | ||
252b5132 | 253 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 254 | i386_insn. */ |
252b5132 | 255 | |
520dc8e8 AM |
256 | union i386_op |
257 | { | |
258 | expressionS *disps; | |
259 | expressionS *imms; | |
260 | const reg_entry *regs; | |
261 | }; | |
262 | ||
a65babc9 L |
263 | enum i386_error |
264 | { | |
86e026a4 | 265 | operand_size_mismatch, |
a65babc9 L |
266 | operand_type_mismatch, |
267 | register_type_mismatch, | |
268 | number_of_operands_mismatch, | |
269 | invalid_instruction_suffix, | |
270 | bad_imm4, | |
271 | old_gcc_only, | |
272 | unsupported_with_intel_mnemonic, | |
273 | unsupported_syntax, | |
6c30d220 L |
274 | unsupported, |
275 | invalid_vsib_address, | |
7bab8ab5 | 276 | invalid_vector_register_set, |
43234a1e L |
277 | unsupported_vector_index_register, |
278 | unsupported_broadcast, | |
279 | broadcast_not_on_src_operand, | |
280 | broadcast_needed, | |
281 | unsupported_masking, | |
282 | mask_not_on_destination, | |
283 | no_default_mask, | |
284 | unsupported_rc_sae, | |
285 | rc_sae_operand_not_last_imm, | |
286 | invalid_register_operand, | |
287 | try_vector_disp8 | |
a65babc9 L |
288 | }; |
289 | ||
252b5132 RH |
290 | struct _i386_insn |
291 | { | |
47926f60 | 292 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 293 | insn_template tm; |
252b5132 | 294 | |
7d5e4556 L |
295 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
296 | or qword, if given. */ | |
252b5132 RH |
297 | char suffix; |
298 | ||
47926f60 | 299 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
300 | unsigned int operands; |
301 | ||
302 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
303 | of given register, displacement, memory operands and immediate | |
47926f60 | 304 | operands. */ |
252b5132 RH |
305 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
306 | ||
307 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 308 | use OP[i] for the corresponding operand. */ |
40fb9820 | 309 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 310 | |
520dc8e8 AM |
311 | /* Displacement expression, immediate expression, or register for each |
312 | operand. */ | |
313 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 314 | |
3e73aa7c JH |
315 | /* Flags for operands. */ |
316 | unsigned int flags[MAX_OPERANDS]; | |
317 | #define Operand_PCrel 1 | |
318 | ||
252b5132 | 319 | /* Relocation type for operand */ |
f86103b7 | 320 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 321 | |
252b5132 RH |
322 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
323 | the base index byte below. */ | |
324 | const reg_entry *base_reg; | |
325 | const reg_entry *index_reg; | |
326 | unsigned int log2_scale_factor; | |
327 | ||
328 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 329 | explicit segment overrides are given. */ |
ce8a8b2f | 330 | const seg_entry *seg[2]; |
252b5132 | 331 | |
8325cc63 JB |
332 | /* Copied first memory operand string, for re-checking. */ |
333 | char *memop1_string; | |
334 | ||
252b5132 RH |
335 | /* PREFIX holds all the given prefix opcodes (usually null). |
336 | PREFIXES is the number of prefix opcodes. */ | |
337 | unsigned int prefixes; | |
338 | unsigned char prefix[MAX_PREFIXES]; | |
339 | ||
340 | /* RM and SIB are the modrm byte and the sib byte where the | |
c1e679ec | 341 | addressing modes of this insn are encoded. */ |
252b5132 | 342 | modrm_byte rm; |
3e73aa7c | 343 | rex_byte rex; |
43234a1e | 344 | rex_byte vrex; |
252b5132 | 345 | sib_byte sib; |
c0f3af97 | 346 | vex_prefix vex; |
b6169b20 | 347 | |
43234a1e L |
348 | /* Masking attributes. */ |
349 | struct Mask_Operation *mask; | |
350 | ||
351 | /* Rounding control and SAE attributes. */ | |
352 | struct RC_Operation *rounding; | |
353 | ||
354 | /* Broadcasting attributes. */ | |
355 | struct Broadcast_Operation *broadcast; | |
356 | ||
357 | /* Compressed disp8*N attribute. */ | |
358 | unsigned int memshift; | |
359 | ||
86fa6981 L |
360 | /* Prefer load or store in encoding. */ |
361 | enum | |
362 | { | |
363 | dir_encoding_default = 0, | |
364 | dir_encoding_load, | |
365 | dir_encoding_store | |
366 | } dir_encoding; | |
891edac4 | 367 | |
a501d77e L |
368 | /* Prefer 8bit or 32bit displacement in encoding. */ |
369 | enum | |
370 | { | |
371 | disp_encoding_default = 0, | |
372 | disp_encoding_8bit, | |
373 | disp_encoding_32bit | |
374 | } disp_encoding; | |
f8a5c266 | 375 | |
86fa6981 L |
376 | /* How to encode vector instructions. */ |
377 | enum | |
378 | { | |
379 | vex_encoding_default = 0, | |
380 | vex_encoding_vex2, | |
381 | vex_encoding_vex3, | |
382 | vex_encoding_evex | |
383 | } vec_encoding; | |
384 | ||
d5de92cf L |
385 | /* REP prefix. */ |
386 | const char *rep_prefix; | |
387 | ||
165de32a L |
388 | /* HLE prefix. */ |
389 | const char *hle_prefix; | |
42164a71 | 390 | |
7e8b059b L |
391 | /* Have BND prefix. */ |
392 | const char *bnd_prefix; | |
393 | ||
04ef582a L |
394 | /* Have NOTRACK prefix. */ |
395 | const char *notrack_prefix; | |
396 | ||
891edac4 | 397 | /* Error message. */ |
a65babc9 | 398 | enum i386_error error; |
252b5132 RH |
399 | }; |
400 | ||
401 | typedef struct _i386_insn i386_insn; | |
402 | ||
43234a1e L |
403 | /* Link RC type with corresponding string, that'll be looked for in |
404 | asm. */ | |
405 | struct RC_name | |
406 | { | |
407 | enum rc_type type; | |
408 | const char *name; | |
409 | unsigned int len; | |
410 | }; | |
411 | ||
412 | static const struct RC_name RC_NamesTable[] = | |
413 | { | |
414 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
415 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
416 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
417 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
418 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
419 | }; | |
420 | ||
252b5132 RH |
421 | /* List of chars besides those in app.c:symbol_chars that can start an |
422 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 423 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 424 | #ifdef LEX_AT |
32137342 NC |
425 | "@" |
426 | #endif | |
427 | #ifdef LEX_QM | |
428 | "?" | |
252b5132 | 429 | #endif |
32137342 | 430 | ; |
252b5132 | 431 | |
29b0f896 AM |
432 | #if (defined (TE_I386AIX) \ |
433 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 434 | && !defined (TE_GNU) \ |
29b0f896 | 435 | && !defined (TE_LINUX) \ |
8d63c93e RM |
436 | && !defined (TE_NACL) \ |
437 | && !defined (TE_NETWARE) \ | |
29b0f896 | 438 | && !defined (TE_FreeBSD) \ |
5b806d27 | 439 | && !defined (TE_DragonFly) \ |
29b0f896 | 440 | && !defined (TE_NetBSD))) |
252b5132 | 441 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
442 | pre-processor is disabled, these aren't very useful. The option |
443 | --divide will remove '/' from this list. */ | |
444 | const char *i386_comment_chars = "#/"; | |
445 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 446 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 447 | |
b3b91714 AM |
448 | #else |
449 | const char *i386_comment_chars = "#"; | |
450 | #define PREFIX_SEPARATOR '/' | |
451 | #endif | |
452 | ||
252b5132 RH |
453 | /* This array holds the chars that only start a comment at the beginning of |
454 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
455 | .line and .file directives will appear in the pre-processed output. |
456 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 457 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
458 | #NO_APP at the beginning of its output. |
459 | Also note that comments started like this one will always work if | |
252b5132 | 460 | '/' isn't otherwise defined. */ |
b3b91714 | 461 | const char line_comment_chars[] = "#/"; |
252b5132 | 462 | |
63a0b638 | 463 | const char line_separator_chars[] = ";"; |
252b5132 | 464 | |
ce8a8b2f AM |
465 | /* Chars that can be used to separate mant from exp in floating point |
466 | nums. */ | |
252b5132 RH |
467 | const char EXP_CHARS[] = "eE"; |
468 | ||
ce8a8b2f AM |
469 | /* Chars that mean this number is a floating point constant |
470 | As in 0f12.456 | |
471 | or 0d1.2345e12. */ | |
252b5132 RH |
472 | const char FLT_CHARS[] = "fFdDxX"; |
473 | ||
ce8a8b2f | 474 | /* Tables for lexical analysis. */ |
252b5132 RH |
475 | static char mnemonic_chars[256]; |
476 | static char register_chars[256]; | |
477 | static char operand_chars[256]; | |
478 | static char identifier_chars[256]; | |
479 | static char digit_chars[256]; | |
480 | ||
ce8a8b2f | 481 | /* Lexical macros. */ |
252b5132 RH |
482 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
483 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
484 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
485 | #define is_space_char(x) ((x) == ' ') | |
486 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
487 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
488 | ||
0234cb7c | 489 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
490 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
491 | ||
492 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
493 | effect this we maintain a stack of saved characters that we've smashed | |
494 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 495 | assembler instruction). */ |
252b5132 | 496 | static char save_stack[32]; |
ce8a8b2f | 497 | static char *save_stack_p; |
252b5132 RH |
498 | #define END_STRING_AND_SAVE(s) \ |
499 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
500 | #define RESTORE_END_STRING(s) \ | |
501 | do { *(s) = *--save_stack_p; } while (0) | |
502 | ||
47926f60 | 503 | /* The instruction we're assembling. */ |
252b5132 RH |
504 | static i386_insn i; |
505 | ||
506 | /* Possible templates for current insn. */ | |
507 | static const templates *current_templates; | |
508 | ||
31b2323c L |
509 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
510 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
511 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 512 | |
47926f60 | 513 | /* Current operand we are working on. */ |
ee86248c | 514 | static int this_operand = -1; |
252b5132 | 515 | |
3e73aa7c JH |
516 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
517 | these. */ | |
518 | ||
519 | enum flag_code { | |
520 | CODE_32BIT, | |
521 | CODE_16BIT, | |
522 | CODE_64BIT }; | |
523 | ||
524 | static enum flag_code flag_code; | |
4fa24527 | 525 | static unsigned int object_64bit; |
862be3fb | 526 | static unsigned int disallow_64bit_reloc; |
3e73aa7c JH |
527 | static int use_rela_relocations = 0; |
528 | ||
7af8ed2d NC |
529 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
530 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
531 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
532 | ||
351f65ca L |
533 | /* The ELF ABI to use. */ |
534 | enum x86_elf_abi | |
535 | { | |
536 | I386_ABI, | |
7f56bc95 L |
537 | X86_64_ABI, |
538 | X86_64_X32_ABI | |
351f65ca L |
539 | }; |
540 | ||
541 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 542 | #endif |
351f65ca | 543 | |
167ad85b TG |
544 | #if defined (TE_PE) || defined (TE_PEP) |
545 | /* Use big object file format. */ | |
546 | static int use_big_obj = 0; | |
547 | #endif | |
548 | ||
8dcea932 L |
549 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
550 | /* 1 if generating code for a shared library. */ | |
551 | static int shared = 0; | |
552 | #endif | |
553 | ||
47926f60 KH |
554 | /* 1 for intel syntax, |
555 | 0 if att syntax. */ | |
556 | static int intel_syntax = 0; | |
252b5132 | 557 | |
e89c5eaa L |
558 | /* 1 for Intel64 ISA, |
559 | 0 if AMD64 ISA. */ | |
560 | static int intel64; | |
561 | ||
1efbbeb4 L |
562 | /* 1 for intel mnemonic, |
563 | 0 if att mnemonic. */ | |
564 | static int intel_mnemonic = !SYSV386_COMPAT; | |
565 | ||
5209009a | 566 | /* 1 if support old (<= 2.8.1) versions of gcc. */ |
1efbbeb4 L |
567 | static int old_gcc = OLDGCC_COMPAT; |
568 | ||
a60de03c JB |
569 | /* 1 if pseudo registers are permitted. */ |
570 | static int allow_pseudo_reg = 0; | |
571 | ||
47926f60 KH |
572 | /* 1 if register prefix % not required. */ |
573 | static int allow_naked_reg = 0; | |
252b5132 | 574 | |
33eaf5de | 575 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
576 | instructions supporting it, even if this prefix wasn't specified |
577 | explicitly. */ | |
578 | static int add_bnd_prefix = 0; | |
579 | ||
ba104c83 | 580 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
581 | static int allow_index_reg = 0; |
582 | ||
d022bddd IT |
583 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
584 | specified explicitly. */ | |
585 | static int omit_lock_prefix = 0; | |
586 | ||
e4e00185 AS |
587 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
588 | "lock addl $0, (%{re}sp)". */ | |
589 | static int avoid_fence = 0; | |
590 | ||
0cb4071e L |
591 | /* 1 if the assembler should generate relax relocations. */ |
592 | ||
593 | static int generate_relax_relocations | |
594 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
595 | ||
7bab8ab5 | 596 | static enum check_kind |
daf50ae7 | 597 | { |
7bab8ab5 JB |
598 | check_none = 0, |
599 | check_warning, | |
600 | check_error | |
daf50ae7 | 601 | } |
7bab8ab5 | 602 | sse_check, operand_check = check_warning; |
daf50ae7 | 603 | |
2ca3ace5 L |
604 | /* Register prefix used for error message. */ |
605 | static const char *register_prefix = "%"; | |
606 | ||
47926f60 KH |
607 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
608 | leave, push, and pop instructions so that gcc has the same stack | |
609 | frame as in 32 bit mode. */ | |
610 | static char stackop_size = '\0'; | |
eecb386c | 611 | |
12b55ccc L |
612 | /* Non-zero to optimize code alignment. */ |
613 | int optimize_align_code = 1; | |
614 | ||
47926f60 KH |
615 | /* Non-zero to quieten some warnings. */ |
616 | static int quiet_warnings = 0; | |
a38cf1db | 617 | |
47926f60 KH |
618 | /* CPU name. */ |
619 | static const char *cpu_arch_name = NULL; | |
6305a203 | 620 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 621 | |
47926f60 | 622 | /* CPU feature flags. */ |
40fb9820 L |
623 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
624 | ||
ccc9c027 L |
625 | /* If we have selected a cpu we are generating instructions for. */ |
626 | static int cpu_arch_tune_set = 0; | |
627 | ||
9103f4f4 | 628 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 629 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
630 | |
631 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 632 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 633 | |
ccc9c027 | 634 | /* CPU instruction set architecture used. */ |
fbf3f584 | 635 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 636 | |
9103f4f4 | 637 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 638 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 639 | |
fddf5b5b AM |
640 | /* If set, conditional jumps are not automatically promoted to handle |
641 | larger than a byte offset. */ | |
642 | static unsigned int no_cond_jump_promotion = 0; | |
643 | ||
c0f3af97 L |
644 | /* Encode SSE instructions with VEX prefix. */ |
645 | static unsigned int sse2avx; | |
646 | ||
539f890d L |
647 | /* Encode scalar AVX instructions with specific vector length. */ |
648 | static enum | |
649 | { | |
650 | vex128 = 0, | |
651 | vex256 | |
652 | } avxscalar; | |
653 | ||
43234a1e L |
654 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
655 | static enum | |
656 | { | |
657 | evexl128 = 0, | |
658 | evexl256, | |
659 | evexl512 | |
660 | } evexlig; | |
661 | ||
662 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
663 | static enum | |
664 | { | |
665 | evexw0 = 0, | |
666 | evexw1 | |
667 | } evexwig; | |
668 | ||
d3d3c6db IT |
669 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
670 | static enum rc_type evexrcig = rne; | |
671 | ||
29b0f896 | 672 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 673 | static symbolS *GOT_symbol; |
29b0f896 | 674 | |
a4447b93 RH |
675 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
676 | unsigned int x86_dwarf2_return_column; | |
677 | ||
678 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
679 | int x86_cie_data_alignment; | |
680 | ||
252b5132 | 681 | /* Interface to relax_segment. |
fddf5b5b AM |
682 | There are 3 major relax states for 386 jump insns because the |
683 | different types of jumps add different sizes to frags when we're | |
684 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 685 | |
47926f60 | 686 | /* Types. */ |
93c2a809 AM |
687 | #define UNCOND_JUMP 0 |
688 | #define COND_JUMP 1 | |
689 | #define COND_JUMP86 2 | |
fddf5b5b | 690 | |
47926f60 | 691 | /* Sizes. */ |
252b5132 RH |
692 | #define CODE16 1 |
693 | #define SMALL 0 | |
29b0f896 | 694 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 695 | #define BIG 2 |
29b0f896 | 696 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
697 | |
698 | #ifndef INLINE | |
699 | #ifdef __GNUC__ | |
700 | #define INLINE __inline__ | |
701 | #else | |
702 | #define INLINE | |
703 | #endif | |
704 | #endif | |
705 | ||
fddf5b5b AM |
706 | #define ENCODE_RELAX_STATE(type, size) \ |
707 | ((relax_substateT) (((type) << 2) | (size))) | |
708 | #define TYPE_FROM_RELAX_STATE(s) \ | |
709 | ((s) >> 2) | |
710 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
711 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
712 | |
713 | /* This table is used by relax_frag to promote short jumps to long | |
714 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
715 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
716 | don't allow a short jump in a 32 bit code segment to be promoted to | |
717 | a 16 bit offset jump because it's slower (requires data size | |
718 | prefix), and doesn't work, unless the destination is in the bottom | |
719 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
720 | ||
721 | const relax_typeS md_relax_table[] = | |
722 | { | |
24eab124 AM |
723 | /* The fields are: |
724 | 1) most positive reach of this state, | |
725 | 2) most negative reach of this state, | |
93c2a809 | 726 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 727 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 728 | |
fddf5b5b | 729 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
730 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
731 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
732 | /* dword jmp adds 4 bytes to frag: | |
733 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 734 | {0, 0, 4, 0}, |
93c2a809 AM |
735 | /* word jmp adds 2 byte2 to frag: |
736 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
737 | {0, 0, 2, 0}, |
738 | ||
93c2a809 AM |
739 | /* COND_JUMP states. */ |
740 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
741 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
742 | /* dword conditionals adds 5 bytes to frag: | |
743 | 1 extra opcode byte, 4 displacement bytes. */ | |
744 | {0, 0, 5, 0}, | |
fddf5b5b | 745 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
746 | 1 extra opcode byte, 2 displacement bytes. */ |
747 | {0, 0, 3, 0}, | |
748 | ||
749 | /* COND_JUMP86 states. */ | |
750 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
751 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
752 | /* dword conditionals adds 5 bytes to frag: | |
753 | 1 extra opcode byte, 4 displacement bytes. */ | |
754 | {0, 0, 5, 0}, | |
755 | /* word conditionals add 4 bytes to frag: | |
756 | 1 displacement byte and a 3 byte long branch insn. */ | |
757 | {0, 0, 4, 0} | |
252b5132 RH |
758 | }; |
759 | ||
9103f4f4 L |
760 | static const arch_entry cpu_arch[] = |
761 | { | |
89507696 JB |
762 | /* Do not replace the first two entries - i386_target_format() |
763 | relies on them being there in this order. */ | |
8a2c8fef | 764 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 765 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 766 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 767 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 768 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 769 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 770 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 771 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 772 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 773 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 774 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 775 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 776 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 777 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 778 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 779 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 780 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 781 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 782 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 783 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 784 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 785 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 786 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 787 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 788 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 789 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 790 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 791 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 792 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 793 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 794 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 795 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 796 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 797 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 798 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 799 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 800 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 801 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 802 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 803 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 804 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 805 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 806 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 807 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 808 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 809 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 810 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 811 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 812 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 813 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 814 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 815 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 816 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 817 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 818 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 819 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 820 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 821 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 822 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 823 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 824 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 825 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 826 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 827 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 828 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 829 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 830 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 831 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 832 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 833 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 834 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 835 | CPU_ZNVER1_FLAGS, 0 }, |
7b458c12 | 836 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 837 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 838 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 839 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 840 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 841 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 842 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 843 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 844 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 845 | CPU_387_FLAGS, 0 }, |
1848e567 L |
846 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
847 | CPU_687_FLAGS, 0 }, | |
8a2c8fef | 848 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 849 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 850 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 851 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 852 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 853 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 854 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 855 | CPU_SSE3_FLAGS, 0 }, |
8a2c8fef | 856 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 857 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 858 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 859 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 860 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 861 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 862 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 863 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 864 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 865 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 866 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 867 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 868 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 869 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 870 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 871 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 872 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 873 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 874 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 875 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 876 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 877 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 878 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 879 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 880 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 881 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 882 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 883 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 884 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 885 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 886 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 887 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 888 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 889 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 890 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 891 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 892 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 893 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 894 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 895 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 896 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 897 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 898 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 899 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 900 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 901 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 902 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 903 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 904 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 905 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 906 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 907 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 908 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 909 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 910 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 911 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 912 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 913 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 914 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 915 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 916 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 917 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 918 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 919 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 920 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 921 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 922 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 923 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 924 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 925 | CPU_LZCNT_FLAGS, 0 }, |
42164a71 | 926 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 927 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 928 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 929 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 930 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 931 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 932 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 933 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 934 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 935 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 936 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 937 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 938 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 939 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 940 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 941 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 942 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 943 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 944 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 945 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 946 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 947 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 948 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 949 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 950 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 951 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 952 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 953 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 954 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 955 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 956 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 957 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 958 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 959 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 960 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 961 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 962 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 963 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 964 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 965 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 966 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 967 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 968 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 969 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 970 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 971 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 972 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 973 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 974 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 975 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 976 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 977 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 978 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 979 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 980 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 981 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
982 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
983 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
984 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
985 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
986 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
987 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
029f3522 | 988 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 989 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 990 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 991 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 992 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 993 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 994 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 995 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
996 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
997 | CPU_PTWRITE_FLAGS, 0 }, | |
603555e5 L |
998 | { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN, |
999 | CPU_CET_FLAGS, 0 }, | |
293f5f65 L |
1000 | }; |
1001 | ||
1002 | static const noarch_entry cpu_noarch[] = | |
1003 | { | |
1004 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1005 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1006 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1007 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
293f5f65 L |
1008 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1009 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1010 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1011 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
1012 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, | |
1013 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1014 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
1015 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, | |
293f5f65 | 1016 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1017 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1018 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1019 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1020 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1021 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1022 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1023 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1024 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1025 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1026 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1027 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1028 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1029 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
e413e4e9 AM |
1030 | }; |
1031 | ||
704209c0 | 1032 | #ifdef I386COFF |
a6c24e68 NC |
1033 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1034 | is allowed to be optional. */ | |
1035 | ||
1036 | static symbolS * | |
1037 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1038 | { | |
1039 | addressT align = 0; | |
1040 | ||
1041 | SKIP_WHITESPACE (); | |
1042 | ||
7ab9ffdd | 1043 | if (needs_align |
a6c24e68 NC |
1044 | && *input_line_pointer == ',') |
1045 | { | |
1046 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1047 | |
a6c24e68 NC |
1048 | if (align == (addressT) -1) |
1049 | return NULL; | |
1050 | } | |
1051 | else | |
1052 | { | |
1053 | if (size >= 8) | |
1054 | align = 3; | |
1055 | else if (size >= 4) | |
1056 | align = 2; | |
1057 | else if (size >= 2) | |
1058 | align = 1; | |
1059 | else | |
1060 | align = 0; | |
1061 | } | |
1062 | ||
1063 | bss_alloc (symbolP, size, align); | |
1064 | return symbolP; | |
1065 | } | |
1066 | ||
704209c0 | 1067 | static void |
a6c24e68 NC |
1068 | pe_lcomm (int needs_align) |
1069 | { | |
1070 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1071 | } | |
704209c0 | 1072 | #endif |
a6c24e68 | 1073 | |
29b0f896 AM |
1074 | const pseudo_typeS md_pseudo_table[] = |
1075 | { | |
1076 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1077 | {"align", s_align_bytes, 0}, | |
1078 | #else | |
1079 | {"align", s_align_ptwo, 0}, | |
1080 | #endif | |
1081 | {"arch", set_cpu_arch, 0}, | |
1082 | #ifndef I386COFF | |
1083 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1084 | #else |
1085 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1086 | #endif |
1087 | {"ffloat", float_cons, 'f'}, | |
1088 | {"dfloat", float_cons, 'd'}, | |
1089 | {"tfloat", float_cons, 'x'}, | |
1090 | {"value", cons, 2}, | |
d182319b | 1091 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1092 | {"noopt", s_ignore, 0}, |
1093 | {"optim", s_ignore, 0}, | |
1094 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1095 | {"code16", set_code_flag, CODE_16BIT}, | |
1096 | {"code32", set_code_flag, CODE_32BIT}, | |
1097 | {"code64", set_code_flag, CODE_64BIT}, | |
1098 | {"intel_syntax", set_intel_syntax, 1}, | |
1099 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1100 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1101 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1102 | {"allow_index_reg", set_allow_index_reg, 1}, |
1103 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1104 | {"sse_check", set_check, 0}, |
1105 | {"operand_check", set_check, 1}, | |
3b22753a L |
1106 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1107 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1108 | #else |
e3bb37b5 | 1109 | {"file", (void (*) (int)) dwarf2_directive_file, 0}, |
07a53e5c RH |
1110 | {"loc", dwarf2_directive_loc, 0}, |
1111 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1112 | #endif |
6482c264 NC |
1113 | #ifdef TE_PE |
1114 | {"secrel32", pe_directive_secrel, 0}, | |
1115 | #endif | |
29b0f896 AM |
1116 | {0, 0, 0} |
1117 | }; | |
1118 | ||
1119 | /* For interface with expression (). */ | |
1120 | extern char *input_line_pointer; | |
1121 | ||
1122 | /* Hash table for instruction mnemonic lookup. */ | |
1123 | static struct hash_control *op_hash; | |
1124 | ||
1125 | /* Hash table for register lookup. */ | |
1126 | static struct hash_control *reg_hash; | |
1127 | \f | |
252b5132 | 1128 | void |
e3bb37b5 | 1129 | i386_align_code (fragS *fragP, int count) |
252b5132 | 1130 | { |
ce8a8b2f AM |
1131 | /* Various efficient no-op patterns for aligning code labels. |
1132 | Note: Don't try to assemble the instructions in the comments. | |
1133 | 0L and 0w are not legal. */ | |
bad6e36d | 1134 | static const unsigned char f32_1[] = |
252b5132 | 1135 | {0x90}; /* nop */ |
bad6e36d | 1136 | static const unsigned char f32_2[] = |
ccc9c027 | 1137 | {0x66,0x90}; /* xchg %ax,%ax */ |
bad6e36d | 1138 | static const unsigned char f32_3[] = |
252b5132 | 1139 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ |
bad6e36d | 1140 | static const unsigned char f32_4[] = |
252b5132 | 1141 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ |
bad6e36d | 1142 | static const unsigned char f32_5[] = |
252b5132 RH |
1143 | {0x90, /* nop */ |
1144 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
bad6e36d | 1145 | static const unsigned char f32_6[] = |
252b5132 | 1146 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ |
bad6e36d | 1147 | static const unsigned char f32_7[] = |
252b5132 | 1148 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ |
bad6e36d | 1149 | static const unsigned char f32_8[] = |
252b5132 RH |
1150 | {0x90, /* nop */ |
1151 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
bad6e36d | 1152 | static const unsigned char f32_9[] = |
252b5132 RH |
1153 | {0x89,0xf6, /* movl %esi,%esi */ |
1154 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1155 | static const unsigned char f32_10[] = |
252b5132 RH |
1156 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ |
1157 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1158 | static const unsigned char f32_11[] = |
252b5132 RH |
1159 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ |
1160 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1161 | static const unsigned char f32_12[] = |
252b5132 RH |
1162 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ |
1163 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
bad6e36d | 1164 | static const unsigned char f32_13[] = |
252b5132 RH |
1165 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ |
1166 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1167 | static const unsigned char f32_14[] = |
252b5132 RH |
1168 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ |
1169 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1170 | static const unsigned char f16_3[] = |
c3332e24 | 1171 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ |
bad6e36d | 1172 | static const unsigned char f16_4[] = |
252b5132 | 1173 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
bad6e36d | 1174 | static const unsigned char f16_5[] = |
252b5132 RH |
1175 | {0x90, /* nop */ |
1176 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
bad6e36d | 1177 | static const unsigned char f16_6[] = |
252b5132 RH |
1178 | {0x89,0xf6, /* mov %si,%si */ |
1179 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
bad6e36d | 1180 | static const unsigned char f16_7[] = |
252b5132 RH |
1181 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ |
1182 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
bad6e36d | 1183 | static const unsigned char f16_8[] = |
252b5132 RH |
1184 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ |
1185 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
bad6e36d | 1186 | static const unsigned char jump_31[] = |
76bc74dc L |
1187 | {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ |
1188 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
1189 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
1190 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
bad6e36d | 1191 | static const unsigned char *const f32_patt[] = { |
252b5132 | 1192 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, |
76bc74dc | 1193 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 |
252b5132 | 1194 | }; |
bad6e36d | 1195 | static const unsigned char *const f16_patt[] = { |
76bc74dc | 1196 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 |
252b5132 | 1197 | }; |
ccc9c027 | 1198 | /* nopl (%[re]ax) */ |
bad6e36d | 1199 | static const unsigned char alt_3[] = |
ccc9c027 L |
1200 | {0x0f,0x1f,0x00}; |
1201 | /* nopl 0(%[re]ax) */ | |
bad6e36d | 1202 | static const unsigned char alt_4[] = |
ccc9c027 L |
1203 | {0x0f,0x1f,0x40,0x00}; |
1204 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1205 | static const unsigned char alt_5[] = |
ccc9c027 L |
1206 | {0x0f,0x1f,0x44,0x00,0x00}; |
1207 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1208 | static const unsigned char alt_6[] = |
ccc9c027 L |
1209 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; |
1210 | /* nopl 0L(%[re]ax) */ | |
bad6e36d | 1211 | static const unsigned char alt_7[] = |
ccc9c027 L |
1212 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; |
1213 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1214 | static const unsigned char alt_8[] = |
ccc9c027 L |
1215 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
1216 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1217 | static const unsigned char alt_9[] = |
ccc9c027 L |
1218 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
1219 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1220 | static const unsigned char alt_10[] = |
ccc9c027 | 1221 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
bad6e36d | 1222 | static const unsigned char *const alt_patt[] = { |
ccc9c027 | 1223 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, |
80b8656c | 1224 | alt_9, alt_10 |
ccc9c027 | 1225 | }; |
252b5132 | 1226 | |
76bc74dc L |
1227 | /* Only align for at least a positive non-zero boundary. */ |
1228 | if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) | |
33fef721 | 1229 | return; |
3e73aa7c | 1230 | |
ccc9c027 L |
1231 | /* We need to decide which NOP sequence to use for 32bit and |
1232 | 64bit. When -mtune= is used: | |
4eed87de | 1233 | |
76bc74dc L |
1234 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1235 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1236 | 2. For the rest, alt_patt will be used. |
1237 | ||
1238 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1239 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1240 | be used. |
ccc9c027 L |
1241 | |
1242 | When -march= or .arch is used, we can't use anything beyond | |
1243 | cpu_arch_isa_flags. */ | |
1244 | ||
1245 | if (flag_code == CODE_16BIT) | |
1246 | { | |
ccc9c027 | 1247 | if (count > 8) |
33fef721 | 1248 | { |
76bc74dc L |
1249 | memcpy (fragP->fr_literal + fragP->fr_fix, |
1250 | jump_31, count); | |
1251 | /* Adjust jump offset. */ | |
1252 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
252b5132 | 1253 | } |
76bc74dc L |
1254 | else |
1255 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1256 | f16_patt[count - 1], count); | |
252b5132 | 1257 | } |
33fef721 | 1258 | else |
ccc9c027 | 1259 | { |
bad6e36d | 1260 | const unsigned char *const *patt = NULL; |
ccc9c027 | 1261 | |
fbf3f584 | 1262 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1263 | { |
1264 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1265 | switch (cpu_arch_tune) | |
1266 | { | |
1267 | case PROCESSOR_UNKNOWN: | |
1268 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1269 | optimize with nops. */ |
1270 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1271 | patt = alt_patt; |
ccc9c027 L |
1272 | else |
1273 | patt = f32_patt; | |
1274 | break; | |
ccc9c027 L |
1275 | case PROCESSOR_PENTIUM4: |
1276 | case PROCESSOR_NOCONA: | |
ef05d495 | 1277 | case PROCESSOR_CORE: |
76bc74dc | 1278 | case PROCESSOR_CORE2: |
bd5295b2 | 1279 | case PROCESSOR_COREI7: |
3632d14b | 1280 | case PROCESSOR_L1OM: |
7a9068fe | 1281 | case PROCESSOR_K1OM: |
76bc74dc | 1282 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1283 | case PROCESSOR_K6: |
1284 | case PROCESSOR_ATHLON: | |
1285 | case PROCESSOR_K8: | |
4eed87de | 1286 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1287 | case PROCESSOR_BD: |
029f3522 | 1288 | case PROCESSOR_ZNVER: |
7b458c12 | 1289 | case PROCESSOR_BT: |
80b8656c | 1290 | patt = alt_patt; |
ccc9c027 | 1291 | break; |
76bc74dc | 1292 | case PROCESSOR_I386: |
ccc9c027 L |
1293 | case PROCESSOR_I486: |
1294 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1295 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1296 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1297 | case PROCESSOR_GENERIC32: |
1298 | patt = f32_patt; | |
1299 | break; | |
4eed87de | 1300 | } |
ccc9c027 L |
1301 | } |
1302 | else | |
1303 | { | |
fbf3f584 | 1304 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1305 | { |
1306 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1307 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1308 | PROCESSOR_UNKNOWN. */ |
1309 | abort (); | |
1310 | break; | |
1311 | ||
76bc74dc | 1312 | case PROCESSOR_I386: |
ccc9c027 L |
1313 | case PROCESSOR_I486: |
1314 | case PROCESSOR_PENTIUM: | |
81486035 | 1315 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1316 | case PROCESSOR_K6: |
1317 | case PROCESSOR_ATHLON: | |
1318 | case PROCESSOR_K8: | |
4eed87de | 1319 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1320 | case PROCESSOR_BD: |
029f3522 | 1321 | case PROCESSOR_ZNVER: |
7b458c12 | 1322 | case PROCESSOR_BT: |
ccc9c027 L |
1323 | case PROCESSOR_GENERIC32: |
1324 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1325 | with nops. */ |
1326 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1327 | patt = alt_patt; |
ccc9c027 L |
1328 | else |
1329 | patt = f32_patt; | |
1330 | break; | |
76bc74dc L |
1331 | case PROCESSOR_PENTIUMPRO: |
1332 | case PROCESSOR_PENTIUM4: | |
1333 | case PROCESSOR_NOCONA: | |
1334 | case PROCESSOR_CORE: | |
ef05d495 | 1335 | case PROCESSOR_CORE2: |
bd5295b2 | 1336 | case PROCESSOR_COREI7: |
3632d14b | 1337 | case PROCESSOR_L1OM: |
7a9068fe | 1338 | case PROCESSOR_K1OM: |
22109423 | 1339 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1340 | patt = alt_patt; |
ccc9c027 L |
1341 | else |
1342 | patt = f32_patt; | |
1343 | break; | |
1344 | case PROCESSOR_GENERIC64: | |
80b8656c | 1345 | patt = alt_patt; |
ccc9c027 | 1346 | break; |
4eed87de | 1347 | } |
ccc9c027 L |
1348 | } |
1349 | ||
76bc74dc L |
1350 | if (patt == f32_patt) |
1351 | { | |
1352 | /* If the padding is less than 15 bytes, we use the normal | |
1353 | ones. Otherwise, we use a jump instruction and adjust | |
711eedef L |
1354 | its offset. */ |
1355 | int limit; | |
76ba9986 | 1356 | |
711eedef L |
1357 | /* For 64bit, the limit is 3 bytes. */ |
1358 | if (flag_code == CODE_64BIT | |
1359 | && fragP->tc_frag_data.isa_flags.bitfield.cpulm) | |
1360 | limit = 3; | |
1361 | else | |
1362 | limit = 15; | |
1363 | if (count < limit) | |
76bc74dc L |
1364 | memcpy (fragP->fr_literal + fragP->fr_fix, |
1365 | patt[count - 1], count); | |
1366 | else | |
1367 | { | |
1368 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1369 | jump_31, count); | |
1370 | /* Adjust jump offset. */ | |
1371 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
1372 | } | |
1373 | } | |
1374 | else | |
1375 | { | |
80b8656c L |
1376 | /* Maximum length of an instruction is 10 byte. If the |
1377 | padding is greater than 10 bytes and we don't use jump, | |
76bc74dc L |
1378 | we have to break it into smaller pieces. */ |
1379 | int padding = count; | |
80b8656c | 1380 | while (padding > 10) |
76bc74dc | 1381 | { |
80b8656c | 1382 | padding -= 10; |
76bc74dc | 1383 | memcpy (fragP->fr_literal + fragP->fr_fix + padding, |
80b8656c | 1384 | patt [9], 10); |
76bc74dc L |
1385 | } |
1386 | ||
1387 | if (padding) | |
1388 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1389 | patt [padding - 1], padding); | |
1390 | } | |
ccc9c027 | 1391 | } |
33fef721 | 1392 | fragP->fr_var = count; |
252b5132 RH |
1393 | } |
1394 | ||
c6fb90c8 | 1395 | static INLINE int |
0dfbf9d7 | 1396 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1397 | { |
0dfbf9d7 | 1398 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1399 | { |
1400 | case 3: | |
0dfbf9d7 | 1401 | if (x->array[2]) |
c6fb90c8 | 1402 | return 0; |
1a0670f3 | 1403 | /* Fall through. */ |
c6fb90c8 | 1404 | case 2: |
0dfbf9d7 | 1405 | if (x->array[1]) |
c6fb90c8 | 1406 | return 0; |
1a0670f3 | 1407 | /* Fall through. */ |
c6fb90c8 | 1408 | case 1: |
0dfbf9d7 | 1409 | return !x->array[0]; |
c6fb90c8 L |
1410 | default: |
1411 | abort (); | |
1412 | } | |
40fb9820 L |
1413 | } |
1414 | ||
c6fb90c8 | 1415 | static INLINE void |
0dfbf9d7 | 1416 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1417 | { |
0dfbf9d7 | 1418 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1419 | { |
1420 | case 3: | |
0dfbf9d7 | 1421 | x->array[2] = v; |
1a0670f3 | 1422 | /* Fall through. */ |
c6fb90c8 | 1423 | case 2: |
0dfbf9d7 | 1424 | x->array[1] = v; |
1a0670f3 | 1425 | /* Fall through. */ |
c6fb90c8 | 1426 | case 1: |
0dfbf9d7 | 1427 | x->array[0] = v; |
1a0670f3 | 1428 | /* Fall through. */ |
c6fb90c8 L |
1429 | break; |
1430 | default: | |
1431 | abort (); | |
1432 | } | |
1433 | } | |
40fb9820 | 1434 | |
c6fb90c8 | 1435 | static INLINE int |
0dfbf9d7 L |
1436 | operand_type_equal (const union i386_operand_type *x, |
1437 | const union i386_operand_type *y) | |
c6fb90c8 | 1438 | { |
0dfbf9d7 | 1439 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1440 | { |
1441 | case 3: | |
0dfbf9d7 | 1442 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1443 | return 0; |
1a0670f3 | 1444 | /* Fall through. */ |
c6fb90c8 | 1445 | case 2: |
0dfbf9d7 | 1446 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1447 | return 0; |
1a0670f3 | 1448 | /* Fall through. */ |
c6fb90c8 | 1449 | case 1: |
0dfbf9d7 | 1450 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1451 | break; |
1452 | default: | |
1453 | abort (); | |
1454 | } | |
1455 | } | |
40fb9820 | 1456 | |
0dfbf9d7 L |
1457 | static INLINE int |
1458 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1459 | { | |
1460 | switch (ARRAY_SIZE(x->array)) | |
1461 | { | |
1462 | case 3: | |
1463 | if (x->array[2]) | |
1464 | return 0; | |
1a0670f3 | 1465 | /* Fall through. */ |
0dfbf9d7 L |
1466 | case 2: |
1467 | if (x->array[1]) | |
1468 | return 0; | |
1a0670f3 | 1469 | /* Fall through. */ |
0dfbf9d7 L |
1470 | case 1: |
1471 | return !x->array[0]; | |
1472 | default: | |
1473 | abort (); | |
1474 | } | |
1475 | } | |
1476 | ||
0dfbf9d7 L |
1477 | static INLINE int |
1478 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1479 | const union i386_cpu_flags *y) | |
1480 | { | |
1481 | switch (ARRAY_SIZE(x->array)) | |
1482 | { | |
1483 | case 3: | |
1484 | if (x->array[2] != y->array[2]) | |
1485 | return 0; | |
1a0670f3 | 1486 | /* Fall through. */ |
0dfbf9d7 L |
1487 | case 2: |
1488 | if (x->array[1] != y->array[1]) | |
1489 | return 0; | |
1a0670f3 | 1490 | /* Fall through. */ |
0dfbf9d7 L |
1491 | case 1: |
1492 | return x->array[0] == y->array[0]; | |
1493 | break; | |
1494 | default: | |
1495 | abort (); | |
1496 | } | |
1497 | } | |
c6fb90c8 L |
1498 | |
1499 | static INLINE int | |
1500 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1501 | { | |
1502 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1503 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1504 | } |
1505 | ||
c6fb90c8 L |
1506 | static INLINE i386_cpu_flags |
1507 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1508 | { |
c6fb90c8 L |
1509 | switch (ARRAY_SIZE (x.array)) |
1510 | { | |
1511 | case 3: | |
1512 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1513 | /* Fall through. */ |
c6fb90c8 L |
1514 | case 2: |
1515 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1516 | /* Fall through. */ |
c6fb90c8 L |
1517 | case 1: |
1518 | x.array [0] &= y.array [0]; | |
1519 | break; | |
1520 | default: | |
1521 | abort (); | |
1522 | } | |
1523 | return x; | |
1524 | } | |
40fb9820 | 1525 | |
c6fb90c8 L |
1526 | static INLINE i386_cpu_flags |
1527 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1528 | { |
c6fb90c8 | 1529 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1530 | { |
c6fb90c8 L |
1531 | case 3: |
1532 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1533 | /* Fall through. */ |
c6fb90c8 L |
1534 | case 2: |
1535 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1536 | /* Fall through. */ |
c6fb90c8 L |
1537 | case 1: |
1538 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1539 | break; |
1540 | default: | |
1541 | abort (); | |
1542 | } | |
40fb9820 L |
1543 | return x; |
1544 | } | |
1545 | ||
309d3373 JB |
1546 | static INLINE i386_cpu_flags |
1547 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1548 | { | |
1549 | switch (ARRAY_SIZE (x.array)) | |
1550 | { | |
1551 | case 3: | |
1552 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1553 | /* Fall through. */ |
309d3373 JB |
1554 | case 2: |
1555 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1556 | /* Fall through. */ |
309d3373 JB |
1557 | case 1: |
1558 | x.array [0] &= ~y.array [0]; | |
1559 | break; | |
1560 | default: | |
1561 | abort (); | |
1562 | } | |
1563 | return x; | |
1564 | } | |
1565 | ||
c0f3af97 L |
1566 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1567 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
a5ff0eb2 | 1568 | #define CPU_FLAGS_AES_MATCH 0x4 |
ce2f5b3c L |
1569 | #define CPU_FLAGS_PCLMUL_MATCH 0x8 |
1570 | #define CPU_FLAGS_AVX_MATCH 0x10 | |
c0f3af97 | 1571 | |
a5ff0eb2 | 1572 | #define CPU_FLAGS_32BIT_MATCH \ |
ce2f5b3c L |
1573 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \ |
1574 | | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH) | |
c0f3af97 L |
1575 | #define CPU_FLAGS_PERFECT_MATCH \ |
1576 | (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) | |
1577 | ||
1578 | /* Return CPU flags match bits. */ | |
3629bb00 | 1579 | |
40fb9820 | 1580 | static int |
d3ce72d0 | 1581 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1582 | { |
c0f3af97 L |
1583 | i386_cpu_flags x = t->cpu_flags; |
1584 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1585 | |
1586 | x.bitfield.cpu64 = 0; | |
1587 | x.bitfield.cpuno64 = 0; | |
1588 | ||
0dfbf9d7 | 1589 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1590 | { |
1591 | /* This instruction is available on all archs. */ | |
1592 | match |= CPU_FLAGS_32BIT_MATCH; | |
1593 | } | |
3629bb00 L |
1594 | else |
1595 | { | |
c0f3af97 | 1596 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1597 | i386_cpu_flags cpu = cpu_arch_flags; |
1598 | ||
3629bb00 | 1599 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1600 | if (!cpu_flags_all_zero (&cpu)) |
1601 | { | |
a5ff0eb2 L |
1602 | if (x.bitfield.cpuavx) |
1603 | { | |
ce2f5b3c | 1604 | /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */ |
a5ff0eb2 L |
1605 | if (cpu.bitfield.cpuavx) |
1606 | { | |
1607 | /* Check SSE2AVX. */ | |
1608 | if (!t->opcode_modifier.sse2avx|| sse2avx) | |
1609 | { | |
1610 | match |= (CPU_FLAGS_ARCH_MATCH | |
1611 | | CPU_FLAGS_AVX_MATCH); | |
1612 | /* Check AES. */ | |
1613 | if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
1614 | match |= CPU_FLAGS_AES_MATCH; | |
ce2f5b3c L |
1615 | /* Check PCLMUL. */ |
1616 | if (!x.bitfield.cpupclmul | |
1617 | || cpu.bitfield.cpupclmul) | |
1618 | match |= CPU_FLAGS_PCLMUL_MATCH; | |
a5ff0eb2 L |
1619 | } |
1620 | } | |
1621 | else | |
1622 | match |= CPU_FLAGS_ARCH_MATCH; | |
1623 | } | |
73b090a9 L |
1624 | else if (x.bitfield.cpuavx512vl) |
1625 | { | |
1626 | /* Match AVX512VL. */ | |
1627 | if (cpu.bitfield.cpuavx512vl) | |
1628 | { | |
1629 | /* Need another match. */ | |
1630 | cpu.bitfield.cpuavx512vl = 0; | |
1631 | if (!cpu_flags_all_zero (&cpu)) | |
1632 | match |= CPU_FLAGS_32BIT_MATCH; | |
1633 | else | |
1634 | match |= CPU_FLAGS_ARCH_MATCH; | |
1635 | } | |
1636 | else | |
1637 | match |= CPU_FLAGS_ARCH_MATCH; | |
1638 | } | |
a5ff0eb2 | 1639 | else |
c0f3af97 L |
1640 | match |= CPU_FLAGS_32BIT_MATCH; |
1641 | } | |
3629bb00 | 1642 | } |
c0f3af97 | 1643 | return match; |
40fb9820 L |
1644 | } |
1645 | ||
c6fb90c8 L |
1646 | static INLINE i386_operand_type |
1647 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1648 | { |
c6fb90c8 L |
1649 | switch (ARRAY_SIZE (x.array)) |
1650 | { | |
1651 | case 3: | |
1652 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1653 | /* Fall through. */ |
c6fb90c8 L |
1654 | case 2: |
1655 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1656 | /* Fall through. */ |
c6fb90c8 L |
1657 | case 1: |
1658 | x.array [0] &= y.array [0]; | |
1659 | break; | |
1660 | default: | |
1661 | abort (); | |
1662 | } | |
1663 | return x; | |
40fb9820 L |
1664 | } |
1665 | ||
c6fb90c8 L |
1666 | static INLINE i386_operand_type |
1667 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1668 | { |
c6fb90c8 | 1669 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1670 | { |
c6fb90c8 L |
1671 | case 3: |
1672 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1673 | /* Fall through. */ |
c6fb90c8 L |
1674 | case 2: |
1675 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1676 | /* Fall through. */ |
c6fb90c8 L |
1677 | case 1: |
1678 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1679 | break; |
1680 | default: | |
1681 | abort (); | |
1682 | } | |
c6fb90c8 L |
1683 | return x; |
1684 | } | |
40fb9820 | 1685 | |
c6fb90c8 L |
1686 | static INLINE i386_operand_type |
1687 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1688 | { | |
1689 | switch (ARRAY_SIZE (x.array)) | |
1690 | { | |
1691 | case 3: | |
1692 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 1693 | /* Fall through. */ |
c6fb90c8 L |
1694 | case 2: |
1695 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 1696 | /* Fall through. */ |
c6fb90c8 L |
1697 | case 1: |
1698 | x.array [0] ^= y.array [0]; | |
1699 | break; | |
1700 | default: | |
1701 | abort (); | |
1702 | } | |
40fb9820 L |
1703 | return x; |
1704 | } | |
1705 | ||
1706 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1707 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
1708 | static const i386_operand_type control = OPERAND_TYPE_CONTROL; | |
65da13b5 L |
1709 | static const i386_operand_type inoutportreg |
1710 | = OPERAND_TYPE_INOUTPORTREG; | |
40fb9820 L |
1711 | static const i386_operand_type reg16_inoutportreg |
1712 | = OPERAND_TYPE_REG16_INOUTPORTREG; | |
1713 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; | |
1714 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1715 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1716 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1717 | static const i386_operand_type anydisp | |
1718 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1719 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
c0f3af97 | 1720 | static const i386_operand_type regymm = OPERAND_TYPE_REGYMM; |
43234a1e L |
1721 | static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM; |
1722 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; | |
40fb9820 L |
1723 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1724 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1725 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1726 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1727 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1728 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1729 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1730 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1731 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
a683cc34 | 1732 | static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; |
40fb9820 L |
1733 | |
1734 | enum operand_type | |
1735 | { | |
1736 | reg, | |
40fb9820 L |
1737 | imm, |
1738 | disp, | |
1739 | anymem | |
1740 | }; | |
1741 | ||
c6fb90c8 | 1742 | static INLINE int |
40fb9820 L |
1743 | operand_type_check (i386_operand_type t, enum operand_type c) |
1744 | { | |
1745 | switch (c) | |
1746 | { | |
1747 | case reg: | |
1748 | return (t.bitfield.reg8 | |
1749 | || t.bitfield.reg16 | |
1750 | || t.bitfield.reg32 | |
1751 | || t.bitfield.reg64); | |
1752 | ||
40fb9820 L |
1753 | case imm: |
1754 | return (t.bitfield.imm8 | |
1755 | || t.bitfield.imm8s | |
1756 | || t.bitfield.imm16 | |
1757 | || t.bitfield.imm32 | |
1758 | || t.bitfield.imm32s | |
1759 | || t.bitfield.imm64); | |
1760 | ||
1761 | case disp: | |
1762 | return (t.bitfield.disp8 | |
1763 | || t.bitfield.disp16 | |
1764 | || t.bitfield.disp32 | |
1765 | || t.bitfield.disp32s | |
1766 | || t.bitfield.disp64); | |
1767 | ||
1768 | case anymem: | |
1769 | return (t.bitfield.disp8 | |
1770 | || t.bitfield.disp16 | |
1771 | || t.bitfield.disp32 | |
1772 | || t.bitfield.disp32s | |
1773 | || t.bitfield.disp64 | |
1774 | || t.bitfield.baseindex); | |
1775 | ||
1776 | default: | |
1777 | abort (); | |
1778 | } | |
2cfe26b6 AM |
1779 | |
1780 | return 0; | |
40fb9820 L |
1781 | } |
1782 | ||
5c07affc L |
1783 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on |
1784 | operand J for instruction template T. */ | |
1785 | ||
1786 | static INLINE int | |
d3ce72d0 | 1787 | match_reg_size (const insn_template *t, unsigned int j) |
5c07affc L |
1788 | { |
1789 | return !((i.types[j].bitfield.byte | |
1790 | && !t->operand_types[j].bitfield.byte) | |
1791 | || (i.types[j].bitfield.word | |
1792 | && !t->operand_types[j].bitfield.word) | |
1793 | || (i.types[j].bitfield.dword | |
1794 | && !t->operand_types[j].bitfield.dword) | |
1795 | || (i.types[j].bitfield.qword | |
1796 | && !t->operand_types[j].bitfield.qword)); | |
1797 | } | |
1798 | ||
1799 | /* Return 1 if there is no conflict in any size on operand J for | |
1800 | instruction template T. */ | |
1801 | ||
1802 | static INLINE int | |
d3ce72d0 | 1803 | match_mem_size (const insn_template *t, unsigned int j) |
5c07affc L |
1804 | { |
1805 | return (match_reg_size (t, j) | |
1806 | && !((i.types[j].bitfield.unspecified | |
af508cb9 | 1807 | && !i.broadcast |
5c07affc L |
1808 | && !t->operand_types[j].bitfield.unspecified) |
1809 | || (i.types[j].bitfield.fword | |
1810 | && !t->operand_types[j].bitfield.fword) | |
1811 | || (i.types[j].bitfield.tbyte | |
1812 | && !t->operand_types[j].bitfield.tbyte) | |
1813 | || (i.types[j].bitfield.xmmword | |
c0f3af97 L |
1814 | && !t->operand_types[j].bitfield.xmmword) |
1815 | || (i.types[j].bitfield.ymmword | |
43234a1e L |
1816 | && !t->operand_types[j].bitfield.ymmword) |
1817 | || (i.types[j].bitfield.zmmword | |
1818 | && !t->operand_types[j].bitfield.zmmword))); | |
5c07affc L |
1819 | } |
1820 | ||
1821 | /* Return 1 if there is no size conflict on any operands for | |
1822 | instruction template T. */ | |
1823 | ||
1824 | static INLINE int | |
d3ce72d0 | 1825 | operand_size_match (const insn_template *t) |
5c07affc L |
1826 | { |
1827 | unsigned int j; | |
1828 | int match = 1; | |
1829 | ||
1830 | /* Don't check jump instructions. */ | |
1831 | if (t->opcode_modifier.jump | |
1832 | || t->opcode_modifier.jumpbyte | |
1833 | || t->opcode_modifier.jumpdword | |
1834 | || t->opcode_modifier.jumpintersegment) | |
1835 | return match; | |
1836 | ||
1837 | /* Check memory and accumulator operand size. */ | |
1838 | for (j = 0; j < i.operands; j++) | |
1839 | { | |
1840 | if (t->operand_types[j].bitfield.anysize) | |
1841 | continue; | |
1842 | ||
1843 | if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j)) | |
1844 | { | |
1845 | match = 0; | |
1846 | break; | |
1847 | } | |
1848 | ||
1849 | if (i.types[j].bitfield.mem && !match_mem_size (t, j)) | |
1850 | { | |
1851 | match = 0; | |
1852 | break; | |
1853 | } | |
1854 | } | |
1855 | ||
891edac4 | 1856 | if (match) |
5c07affc | 1857 | return match; |
891edac4 L |
1858 | else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
1859 | { | |
1860 | mismatch: | |
86e026a4 | 1861 | i.error = operand_size_mismatch; |
891edac4 L |
1862 | return 0; |
1863 | } | |
5c07affc L |
1864 | |
1865 | /* Check reverse. */ | |
9c2799c2 | 1866 | gas_assert (i.operands == 2); |
5c07affc L |
1867 | |
1868 | match = 1; | |
1869 | for (j = 0; j < 2; j++) | |
1870 | { | |
1871 | if (t->operand_types[j].bitfield.acc | |
1872 | && !match_reg_size (t, j ? 0 : 1)) | |
891edac4 | 1873 | goto mismatch; |
5c07affc L |
1874 | |
1875 | if (i.types[j].bitfield.mem | |
1876 | && !match_mem_size (t, j ? 0 : 1)) | |
891edac4 | 1877 | goto mismatch; |
5c07affc L |
1878 | } |
1879 | ||
1880 | return match; | |
1881 | } | |
1882 | ||
c6fb90c8 | 1883 | static INLINE int |
40fb9820 L |
1884 | operand_type_match (i386_operand_type overlap, |
1885 | i386_operand_type given) | |
1886 | { | |
1887 | i386_operand_type temp = overlap; | |
1888 | ||
1889 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 1890 | temp.bitfield.unspecified = 0; |
5c07affc L |
1891 | temp.bitfield.byte = 0; |
1892 | temp.bitfield.word = 0; | |
1893 | temp.bitfield.dword = 0; | |
1894 | temp.bitfield.fword = 0; | |
1895 | temp.bitfield.qword = 0; | |
1896 | temp.bitfield.tbyte = 0; | |
1897 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 1898 | temp.bitfield.ymmword = 0; |
43234a1e | 1899 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 1900 | if (operand_type_all_zero (&temp)) |
891edac4 | 1901 | goto mismatch; |
40fb9820 | 1902 | |
891edac4 L |
1903 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
1904 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) | |
1905 | return 1; | |
1906 | ||
1907 | mismatch: | |
a65babc9 | 1908 | i.error = operand_type_mismatch; |
891edac4 | 1909 | return 0; |
40fb9820 L |
1910 | } |
1911 | ||
7d5e4556 | 1912 | /* If given types g0 and g1 are registers they must be of the same type |
40fb9820 L |
1913 | unless the expected operand type register overlap is null. |
1914 | Note that Acc in a template matches every size of reg. */ | |
1915 | ||
c6fb90c8 | 1916 | static INLINE int |
40fb9820 L |
1917 | operand_type_register_match (i386_operand_type m0, |
1918 | i386_operand_type g0, | |
1919 | i386_operand_type t0, | |
1920 | i386_operand_type m1, | |
1921 | i386_operand_type g1, | |
1922 | i386_operand_type t1) | |
1923 | { | |
1924 | if (!operand_type_check (g0, reg)) | |
1925 | return 1; | |
1926 | ||
1927 | if (!operand_type_check (g1, reg)) | |
1928 | return 1; | |
1929 | ||
1930 | if (g0.bitfield.reg8 == g1.bitfield.reg8 | |
1931 | && g0.bitfield.reg16 == g1.bitfield.reg16 | |
1932 | && g0.bitfield.reg32 == g1.bitfield.reg32 | |
1933 | && g0.bitfield.reg64 == g1.bitfield.reg64) | |
1934 | return 1; | |
1935 | ||
1936 | if (m0.bitfield.acc) | |
1937 | { | |
1938 | t0.bitfield.reg8 = 1; | |
1939 | t0.bitfield.reg16 = 1; | |
1940 | t0.bitfield.reg32 = 1; | |
1941 | t0.bitfield.reg64 = 1; | |
1942 | } | |
1943 | ||
1944 | if (m1.bitfield.acc) | |
1945 | { | |
1946 | t1.bitfield.reg8 = 1; | |
1947 | t1.bitfield.reg16 = 1; | |
1948 | t1.bitfield.reg32 = 1; | |
1949 | t1.bitfield.reg64 = 1; | |
1950 | } | |
1951 | ||
891edac4 L |
1952 | if (!(t0.bitfield.reg8 & t1.bitfield.reg8) |
1953 | && !(t0.bitfield.reg16 & t1.bitfield.reg16) | |
1954 | && !(t0.bitfield.reg32 & t1.bitfield.reg32) | |
1955 | && !(t0.bitfield.reg64 & t1.bitfield.reg64)) | |
1956 | return 1; | |
1957 | ||
a65babc9 | 1958 | i.error = register_type_mismatch; |
891edac4 L |
1959 | |
1960 | return 0; | |
40fb9820 L |
1961 | } |
1962 | ||
4c692bc7 JB |
1963 | static INLINE unsigned int |
1964 | register_number (const reg_entry *r) | |
1965 | { | |
1966 | unsigned int nr = r->reg_num; | |
1967 | ||
1968 | if (r->reg_flags & RegRex) | |
1969 | nr += 8; | |
1970 | ||
200cbe0f L |
1971 | if (r->reg_flags & RegVRex) |
1972 | nr += 16; | |
1973 | ||
4c692bc7 JB |
1974 | return nr; |
1975 | } | |
1976 | ||
252b5132 | 1977 | static INLINE unsigned int |
40fb9820 | 1978 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 1979 | { |
43234a1e | 1980 | if (t.bitfield.disp8 || t.bitfield.vec_disp8) |
40fb9820 L |
1981 | return 1; |
1982 | else if (t.bitfield.disp16 | |
1983 | || t.bitfield.disp32 | |
1984 | || t.bitfield.disp32s) | |
1985 | return 2; | |
1986 | else | |
1987 | return 0; | |
252b5132 RH |
1988 | } |
1989 | ||
1990 | static INLINE int | |
65879393 | 1991 | fits_in_signed_byte (addressT num) |
252b5132 | 1992 | { |
65879393 | 1993 | return num + 0x80 <= 0xff; |
47926f60 | 1994 | } |
252b5132 RH |
1995 | |
1996 | static INLINE int | |
65879393 | 1997 | fits_in_unsigned_byte (addressT num) |
252b5132 | 1998 | { |
65879393 | 1999 | return num <= 0xff; |
47926f60 | 2000 | } |
252b5132 RH |
2001 | |
2002 | static INLINE int | |
65879393 | 2003 | fits_in_unsigned_word (addressT num) |
252b5132 | 2004 | { |
65879393 | 2005 | return num <= 0xffff; |
47926f60 | 2006 | } |
252b5132 RH |
2007 | |
2008 | static INLINE int | |
65879393 | 2009 | fits_in_signed_word (addressT num) |
252b5132 | 2010 | { |
65879393 | 2011 | return num + 0x8000 <= 0xffff; |
47926f60 | 2012 | } |
2a962e6d | 2013 | |
3e73aa7c | 2014 | static INLINE int |
65879393 | 2015 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2016 | { |
2017 | #ifndef BFD64 | |
2018 | return 1; | |
2019 | #else | |
65879393 | 2020 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2021 | #endif |
2022 | } /* fits_in_signed_long() */ | |
2a962e6d | 2023 | |
3e73aa7c | 2024 | static INLINE int |
65879393 | 2025 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2026 | { |
2027 | #ifndef BFD64 | |
2028 | return 1; | |
2029 | #else | |
65879393 | 2030 | return num <= 0xffffffff; |
3e73aa7c JH |
2031 | #endif |
2032 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2033 | |
43234a1e L |
2034 | static INLINE int |
2035 | fits_in_vec_disp8 (offsetT num) | |
2036 | { | |
2037 | int shift = i.memshift; | |
2038 | unsigned int mask; | |
2039 | ||
2040 | if (shift == -1) | |
2041 | abort (); | |
2042 | ||
2043 | mask = (1 << shift) - 1; | |
2044 | ||
2045 | /* Return 0 if NUM isn't properly aligned. */ | |
2046 | if ((num & mask)) | |
2047 | return 0; | |
2048 | ||
2049 | /* Check if NUM will fit in 8bit after shift. */ | |
2050 | return fits_in_signed_byte (num >> shift); | |
2051 | } | |
2052 | ||
a683cc34 SP |
2053 | static INLINE int |
2054 | fits_in_imm4 (offsetT num) | |
2055 | { | |
2056 | return (num & 0xf) == num; | |
2057 | } | |
2058 | ||
40fb9820 | 2059 | static i386_operand_type |
e3bb37b5 | 2060 | smallest_imm_type (offsetT num) |
252b5132 | 2061 | { |
40fb9820 | 2062 | i386_operand_type t; |
7ab9ffdd | 2063 | |
0dfbf9d7 | 2064 | operand_type_set (&t, 0); |
40fb9820 L |
2065 | t.bitfield.imm64 = 1; |
2066 | ||
2067 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2068 | { |
2069 | /* This code is disabled on the 486 because all the Imm1 forms | |
2070 | in the opcode table are slower on the i486. They're the | |
2071 | versions with the implicitly specified single-position | |
2072 | displacement, which has another syntax if you really want to | |
2073 | use that form. */ | |
40fb9820 L |
2074 | t.bitfield.imm1 = 1; |
2075 | t.bitfield.imm8 = 1; | |
2076 | t.bitfield.imm8s = 1; | |
2077 | t.bitfield.imm16 = 1; | |
2078 | t.bitfield.imm32 = 1; | |
2079 | t.bitfield.imm32s = 1; | |
2080 | } | |
2081 | else if (fits_in_signed_byte (num)) | |
2082 | { | |
2083 | t.bitfield.imm8 = 1; | |
2084 | t.bitfield.imm8s = 1; | |
2085 | t.bitfield.imm16 = 1; | |
2086 | t.bitfield.imm32 = 1; | |
2087 | t.bitfield.imm32s = 1; | |
2088 | } | |
2089 | else if (fits_in_unsigned_byte (num)) | |
2090 | { | |
2091 | t.bitfield.imm8 = 1; | |
2092 | t.bitfield.imm16 = 1; | |
2093 | t.bitfield.imm32 = 1; | |
2094 | t.bitfield.imm32s = 1; | |
2095 | } | |
2096 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2097 | { | |
2098 | t.bitfield.imm16 = 1; | |
2099 | t.bitfield.imm32 = 1; | |
2100 | t.bitfield.imm32s = 1; | |
2101 | } | |
2102 | else if (fits_in_signed_long (num)) | |
2103 | { | |
2104 | t.bitfield.imm32 = 1; | |
2105 | t.bitfield.imm32s = 1; | |
2106 | } | |
2107 | else if (fits_in_unsigned_long (num)) | |
2108 | t.bitfield.imm32 = 1; | |
2109 | ||
2110 | return t; | |
47926f60 | 2111 | } |
252b5132 | 2112 | |
847f7ad4 | 2113 | static offsetT |
e3bb37b5 | 2114 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2115 | { |
508866be | 2116 | addressT mask; |
ba2adb93 | 2117 | |
847f7ad4 AM |
2118 | switch (size) |
2119 | { | |
508866be L |
2120 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2121 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2122 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2123 | #ifdef BFD64 |
2124 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2125 | #endif | |
47926f60 | 2126 | default: abort (); |
847f7ad4 AM |
2127 | } |
2128 | ||
9de868bf L |
2129 | #ifdef BFD64 |
2130 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2131 | if (flag_code != CODE_64BIT | |
2132 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2133 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2134 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2135 | #endif |
ba2adb93 | 2136 | |
47926f60 | 2137 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2138 | { |
2139 | char buf1[40], buf2[40]; | |
2140 | ||
2141 | sprint_value (buf1, val); | |
2142 | sprint_value (buf2, val & mask); | |
2143 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2144 | } | |
2145 | return val & mask; | |
2146 | } | |
2147 | ||
c32fa91d L |
2148 | enum PREFIX_GROUP |
2149 | { | |
2150 | PREFIX_EXIST = 0, | |
2151 | PREFIX_LOCK, | |
2152 | PREFIX_REP, | |
04ef582a | 2153 | PREFIX_DS, |
c32fa91d L |
2154 | PREFIX_OTHER |
2155 | }; | |
2156 | ||
2157 | /* Returns | |
2158 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2159 | same class already exists. | |
2160 | b. PREFIX_LOCK if lock prefix is added. | |
2161 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2162 | d. PREFIX_DS if ds prefix is added. |
2163 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2164 | */ |
2165 | ||
2166 | static enum PREFIX_GROUP | |
e3bb37b5 | 2167 | add_prefix (unsigned int prefix) |
252b5132 | 2168 | { |
c32fa91d | 2169 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2170 | unsigned int q; |
252b5132 | 2171 | |
29b0f896 AM |
2172 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2173 | && flag_code == CODE_64BIT) | |
b1905489 | 2174 | { |
161a04f6 L |
2175 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
2176 | || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) | |
2177 | && (prefix & (REX_R | REX_X | REX_B)))) | |
c32fa91d | 2178 | ret = PREFIX_EXIST; |
b1905489 JB |
2179 | q = REX_PREFIX; |
2180 | } | |
3e73aa7c | 2181 | else |
b1905489 JB |
2182 | { |
2183 | switch (prefix) | |
2184 | { | |
2185 | default: | |
2186 | abort (); | |
2187 | ||
b1905489 | 2188 | case DS_PREFIX_OPCODE: |
04ef582a L |
2189 | ret = PREFIX_DS; |
2190 | /* Fall through. */ | |
2191 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2192 | case ES_PREFIX_OPCODE: |
2193 | case FS_PREFIX_OPCODE: | |
2194 | case GS_PREFIX_OPCODE: | |
2195 | case SS_PREFIX_OPCODE: | |
2196 | q = SEG_PREFIX; | |
2197 | break; | |
2198 | ||
2199 | case REPNE_PREFIX_OPCODE: | |
2200 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2201 | q = REP_PREFIX; |
2202 | ret = PREFIX_REP; | |
2203 | break; | |
2204 | ||
b1905489 | 2205 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2206 | q = LOCK_PREFIX; |
2207 | ret = PREFIX_LOCK; | |
b1905489 JB |
2208 | break; |
2209 | ||
2210 | case FWAIT_OPCODE: | |
2211 | q = WAIT_PREFIX; | |
2212 | break; | |
2213 | ||
2214 | case ADDR_PREFIX_OPCODE: | |
2215 | q = ADDR_PREFIX; | |
2216 | break; | |
2217 | ||
2218 | case DATA_PREFIX_OPCODE: | |
2219 | q = DATA_PREFIX; | |
2220 | break; | |
2221 | } | |
2222 | if (i.prefix[q] != 0) | |
c32fa91d | 2223 | ret = PREFIX_EXIST; |
b1905489 | 2224 | } |
252b5132 | 2225 | |
b1905489 | 2226 | if (ret) |
252b5132 | 2227 | { |
b1905489 JB |
2228 | if (!i.prefix[q]) |
2229 | ++i.prefixes; | |
2230 | i.prefix[q] |= prefix; | |
252b5132 | 2231 | } |
b1905489 JB |
2232 | else |
2233 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2234 | |
252b5132 RH |
2235 | return ret; |
2236 | } | |
2237 | ||
2238 | static void | |
78f12dd3 | 2239 | update_code_flag (int value, int check) |
eecb386c | 2240 | { |
78f12dd3 L |
2241 | PRINTF_LIKE ((*as_error)); |
2242 | ||
1e9cc1c2 | 2243 | flag_code = (enum flag_code) value; |
40fb9820 L |
2244 | if (flag_code == CODE_64BIT) |
2245 | { | |
2246 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2247 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2248 | } |
2249 | else | |
2250 | { | |
2251 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2252 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2253 | } |
2254 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2255 | { |
78f12dd3 L |
2256 | if (check) |
2257 | as_error = as_fatal; | |
2258 | else | |
2259 | as_error = as_bad; | |
2260 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2261 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2262 | } |
40fb9820 | 2263 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2264 | { |
78f12dd3 L |
2265 | if (check) |
2266 | as_error = as_fatal; | |
2267 | else | |
2268 | as_error = as_bad; | |
2269 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2270 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2271 | } |
eecb386c AM |
2272 | stackop_size = '\0'; |
2273 | } | |
2274 | ||
78f12dd3 L |
2275 | static void |
2276 | set_code_flag (int value) | |
2277 | { | |
2278 | update_code_flag (value, 0); | |
2279 | } | |
2280 | ||
eecb386c | 2281 | static void |
e3bb37b5 | 2282 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2283 | { |
1e9cc1c2 | 2284 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2285 | if (flag_code != CODE_16BIT) |
2286 | abort (); | |
2287 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2288 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2289 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2290 | } |
2291 | ||
2292 | static void | |
e3bb37b5 | 2293 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2294 | { |
2295 | /* Find out if register prefixing is specified. */ | |
2296 | int ask_naked_reg = 0; | |
2297 | ||
2298 | SKIP_WHITESPACE (); | |
29b0f896 | 2299 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2300 | { |
d02603dc NC |
2301 | char *string; |
2302 | int e = get_symbol_name (&string); | |
252b5132 | 2303 | |
47926f60 | 2304 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2305 | ask_naked_reg = 1; |
47926f60 | 2306 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2307 | ask_naked_reg = -1; |
2308 | else | |
d0b47220 | 2309 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2310 | (void) restore_line_pointer (e); |
252b5132 RH |
2311 | } |
2312 | demand_empty_rest_of_line (); | |
c3332e24 | 2313 | |
252b5132 RH |
2314 | intel_syntax = syntax_flag; |
2315 | ||
2316 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2317 | allow_naked_reg = (intel_syntax |
2318 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2319 | else |
2320 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2321 | |
ee86248c | 2322 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2323 | |
e4a3b5a4 | 2324 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2325 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2326 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2327 | } |
2328 | ||
1efbbeb4 L |
2329 | static void |
2330 | set_intel_mnemonic (int mnemonic_flag) | |
2331 | { | |
e1d4d893 | 2332 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2333 | } |
2334 | ||
db51cc60 L |
2335 | static void |
2336 | set_allow_index_reg (int flag) | |
2337 | { | |
2338 | allow_index_reg = flag; | |
2339 | } | |
2340 | ||
cb19c032 | 2341 | static void |
7bab8ab5 | 2342 | set_check (int what) |
cb19c032 | 2343 | { |
7bab8ab5 JB |
2344 | enum check_kind *kind; |
2345 | const char *str; | |
2346 | ||
2347 | if (what) | |
2348 | { | |
2349 | kind = &operand_check; | |
2350 | str = "operand"; | |
2351 | } | |
2352 | else | |
2353 | { | |
2354 | kind = &sse_check; | |
2355 | str = "sse"; | |
2356 | } | |
2357 | ||
cb19c032 L |
2358 | SKIP_WHITESPACE (); |
2359 | ||
2360 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2361 | { | |
d02603dc NC |
2362 | char *string; |
2363 | int e = get_symbol_name (&string); | |
cb19c032 L |
2364 | |
2365 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2366 | *kind = check_none; |
cb19c032 | 2367 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2368 | *kind = check_warning; |
cb19c032 | 2369 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2370 | *kind = check_error; |
cb19c032 | 2371 | else |
7bab8ab5 | 2372 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2373 | (void) restore_line_pointer (e); |
cb19c032 L |
2374 | } |
2375 | else | |
7bab8ab5 | 2376 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2377 | |
2378 | demand_empty_rest_of_line (); | |
2379 | } | |
2380 | ||
8a9036a4 L |
2381 | static void |
2382 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2383 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2384 | { |
2385 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2386 | static const char *arch; | |
2387 | ||
2388 | /* Intel LIOM is only supported on ELF. */ | |
2389 | if (!IS_ELF) | |
2390 | return; | |
2391 | ||
2392 | if (!arch) | |
2393 | { | |
2394 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2395 | use default_arch. */ | |
2396 | arch = cpu_arch_name; | |
2397 | if (!arch) | |
2398 | arch = default_arch; | |
2399 | } | |
2400 | ||
81486035 L |
2401 | /* If we are targeting Intel MCU, we must enable it. */ |
2402 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2403 | || new_flag.bitfield.cpuiamcu) | |
2404 | return; | |
2405 | ||
3632d14b | 2406 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2407 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2408 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2409 | return; |
76ba9986 | 2410 | |
7a9068fe L |
2411 | /* If we are targeting Intel K1OM, we must enable it. */ |
2412 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2413 | || new_flag.bitfield.cpuk1om) | |
2414 | return; | |
2415 | ||
8a9036a4 L |
2416 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2417 | #endif | |
2418 | } | |
2419 | ||
e413e4e9 | 2420 | static void |
e3bb37b5 | 2421 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2422 | { |
47926f60 | 2423 | SKIP_WHITESPACE (); |
e413e4e9 | 2424 | |
29b0f896 | 2425 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2426 | { |
d02603dc NC |
2427 | char *string; |
2428 | int e = get_symbol_name (&string); | |
91d6fa6a | 2429 | unsigned int j; |
40fb9820 | 2430 | i386_cpu_flags flags; |
e413e4e9 | 2431 | |
91d6fa6a | 2432 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2433 | { |
91d6fa6a | 2434 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2435 | { |
91d6fa6a | 2436 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2437 | |
5c6af06e JB |
2438 | if (*string != '.') |
2439 | { | |
91d6fa6a | 2440 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2441 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2442 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2443 | if (flag_code == CODE_64BIT) |
2444 | { | |
2445 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2446 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2447 | } | |
2448 | else | |
2449 | { | |
2450 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2451 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2452 | } | |
91d6fa6a NC |
2453 | cpu_arch_isa = cpu_arch[j].type; |
2454 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2455 | if (!cpu_arch_tune_set) |
2456 | { | |
2457 | cpu_arch_tune = cpu_arch_isa; | |
2458 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2459 | } | |
5c6af06e JB |
2460 | break; |
2461 | } | |
40fb9820 | 2462 | |
293f5f65 L |
2463 | flags = cpu_flags_or (cpu_arch_flags, |
2464 | cpu_arch[j].flags); | |
81486035 | 2465 | |
5b64d091 | 2466 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2467 | { |
6305a203 L |
2468 | if (cpu_sub_arch_name) |
2469 | { | |
2470 | char *name = cpu_sub_arch_name; | |
2471 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2472 | cpu_arch[j].name, |
1bf57e9f | 2473 | (const char *) NULL); |
6305a203 L |
2474 | free (name); |
2475 | } | |
2476 | else | |
91d6fa6a | 2477 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2478 | cpu_arch_flags = flags; |
a586129e | 2479 | cpu_arch_isa_flags = flags; |
5c6af06e | 2480 | } |
d02603dc | 2481 | (void) restore_line_pointer (e); |
5c6af06e JB |
2482 | demand_empty_rest_of_line (); |
2483 | return; | |
e413e4e9 AM |
2484 | } |
2485 | } | |
293f5f65 L |
2486 | |
2487 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2488 | { | |
33eaf5de | 2489 | /* Disable an ISA extension. */ |
293f5f65 L |
2490 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2491 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2492 | { | |
2493 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2494 | cpu_noarch[j].flags); | |
2495 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2496 | { | |
2497 | if (cpu_sub_arch_name) | |
2498 | { | |
2499 | char *name = cpu_sub_arch_name; | |
2500 | cpu_sub_arch_name = concat (name, string, | |
2501 | (const char *) NULL); | |
2502 | free (name); | |
2503 | } | |
2504 | else | |
2505 | cpu_sub_arch_name = xstrdup (string); | |
2506 | cpu_arch_flags = flags; | |
2507 | cpu_arch_isa_flags = flags; | |
2508 | } | |
2509 | (void) restore_line_pointer (e); | |
2510 | demand_empty_rest_of_line (); | |
2511 | return; | |
2512 | } | |
2513 | ||
2514 | j = ARRAY_SIZE (cpu_arch); | |
2515 | } | |
2516 | ||
91d6fa6a | 2517 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2518 | as_bad (_("no such architecture: `%s'"), string); |
2519 | ||
2520 | *input_line_pointer = e; | |
2521 | } | |
2522 | else | |
2523 | as_bad (_("missing cpu architecture")); | |
2524 | ||
fddf5b5b AM |
2525 | no_cond_jump_promotion = 0; |
2526 | if (*input_line_pointer == ',' | |
29b0f896 | 2527 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2528 | { |
d02603dc NC |
2529 | char *string; |
2530 | char e; | |
2531 | ||
2532 | ++input_line_pointer; | |
2533 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2534 | |
2535 | if (strcmp (string, "nojumps") == 0) | |
2536 | no_cond_jump_promotion = 1; | |
2537 | else if (strcmp (string, "jumps") == 0) | |
2538 | ; | |
2539 | else | |
2540 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2541 | ||
d02603dc | 2542 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2543 | } |
2544 | ||
e413e4e9 AM |
2545 | demand_empty_rest_of_line (); |
2546 | } | |
2547 | ||
8a9036a4 L |
2548 | enum bfd_architecture |
2549 | i386_arch (void) | |
2550 | { | |
3632d14b | 2551 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2552 | { |
2553 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2554 | || flag_code != CODE_64BIT) | |
2555 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2556 | return bfd_arch_l1om; | |
2557 | } | |
7a9068fe L |
2558 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2559 | { | |
2560 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2561 | || flag_code != CODE_64BIT) | |
2562 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2563 | return bfd_arch_k1om; | |
2564 | } | |
81486035 L |
2565 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2566 | { | |
2567 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2568 | || flag_code == CODE_64BIT) | |
2569 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2570 | return bfd_arch_iamcu; | |
2571 | } | |
8a9036a4 L |
2572 | else |
2573 | return bfd_arch_i386; | |
2574 | } | |
2575 | ||
b9d79e03 | 2576 | unsigned long |
7016a5d5 | 2577 | i386_mach (void) |
b9d79e03 | 2578 | { |
351f65ca | 2579 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2580 | { |
3632d14b | 2581 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2582 | { |
351f65ca L |
2583 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2584 | || default_arch[6] != '\0') | |
8a9036a4 L |
2585 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2586 | return bfd_mach_l1om; | |
2587 | } | |
7a9068fe L |
2588 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2589 | { | |
2590 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2591 | || default_arch[6] != '\0') | |
2592 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2593 | return bfd_mach_k1om; | |
2594 | } | |
351f65ca | 2595 | else if (default_arch[6] == '\0') |
8a9036a4 | 2596 | return bfd_mach_x86_64; |
351f65ca L |
2597 | else |
2598 | return bfd_mach_x64_32; | |
8a9036a4 | 2599 | } |
5197d474 L |
2600 | else if (!strcmp (default_arch, "i386") |
2601 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2602 | { |
2603 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2604 | { | |
2605 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2606 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2607 | return bfd_mach_i386_iamcu; | |
2608 | } | |
2609 | else | |
2610 | return bfd_mach_i386_i386; | |
2611 | } | |
b9d79e03 | 2612 | else |
2b5d6a91 | 2613 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2614 | } |
b9d79e03 | 2615 | \f |
252b5132 | 2616 | void |
7016a5d5 | 2617 | md_begin (void) |
252b5132 RH |
2618 | { |
2619 | const char *hash_err; | |
2620 | ||
86fa6981 L |
2621 | /* Support pseudo prefixes like {disp32}. */ |
2622 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2623 | ||
47926f60 | 2624 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2625 | op_hash = hash_new (); |
2626 | ||
2627 | { | |
d3ce72d0 | 2628 | const insn_template *optab; |
29b0f896 | 2629 | templates *core_optab; |
252b5132 | 2630 | |
47926f60 KH |
2631 | /* Setup for loop. */ |
2632 | optab = i386_optab; | |
add39d23 | 2633 | core_optab = XNEW (templates); |
252b5132 RH |
2634 | core_optab->start = optab; |
2635 | ||
2636 | while (1) | |
2637 | { | |
2638 | ++optab; | |
2639 | if (optab->name == NULL | |
2640 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2641 | { | |
2642 | /* different name --> ship out current template list; | |
47926f60 | 2643 | add to hash table; & begin anew. */ |
252b5132 RH |
2644 | core_optab->end = optab; |
2645 | hash_err = hash_insert (op_hash, | |
2646 | (optab - 1)->name, | |
5a49b8ac | 2647 | (void *) core_optab); |
252b5132 RH |
2648 | if (hash_err) |
2649 | { | |
b37df7c4 | 2650 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
2651 | (optab - 1)->name, |
2652 | hash_err); | |
2653 | } | |
2654 | if (optab->name == NULL) | |
2655 | break; | |
add39d23 | 2656 | core_optab = XNEW (templates); |
252b5132 RH |
2657 | core_optab->start = optab; |
2658 | } | |
2659 | } | |
2660 | } | |
2661 | ||
47926f60 | 2662 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2663 | reg_hash = hash_new (); |
2664 | { | |
29b0f896 | 2665 | const reg_entry *regtab; |
c3fe08fa | 2666 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2667 | |
c3fe08fa | 2668 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2669 | { |
5a49b8ac | 2670 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2671 | if (hash_err) |
b37df7c4 | 2672 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
2673 | regtab->reg_name, |
2674 | hash_err); | |
252b5132 RH |
2675 | } |
2676 | } | |
2677 | ||
47926f60 | 2678 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2679 | { |
29b0f896 AM |
2680 | int c; |
2681 | char *p; | |
252b5132 RH |
2682 | |
2683 | for (c = 0; c < 256; c++) | |
2684 | { | |
3882b010 | 2685 | if (ISDIGIT (c)) |
252b5132 RH |
2686 | { |
2687 | digit_chars[c] = c; | |
2688 | mnemonic_chars[c] = c; | |
2689 | register_chars[c] = c; | |
2690 | operand_chars[c] = c; | |
2691 | } | |
3882b010 | 2692 | else if (ISLOWER (c)) |
252b5132 RH |
2693 | { |
2694 | mnemonic_chars[c] = c; | |
2695 | register_chars[c] = c; | |
2696 | operand_chars[c] = c; | |
2697 | } | |
3882b010 | 2698 | else if (ISUPPER (c)) |
252b5132 | 2699 | { |
3882b010 | 2700 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2701 | register_chars[c] = mnemonic_chars[c]; |
2702 | operand_chars[c] = c; | |
2703 | } | |
43234a1e | 2704 | else if (c == '{' || c == '}') |
86fa6981 L |
2705 | { |
2706 | mnemonic_chars[c] = c; | |
2707 | operand_chars[c] = c; | |
2708 | } | |
252b5132 | 2709 | |
3882b010 | 2710 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2711 | identifier_chars[c] = c; |
2712 | else if (c >= 128) | |
2713 | { | |
2714 | identifier_chars[c] = c; | |
2715 | operand_chars[c] = c; | |
2716 | } | |
2717 | } | |
2718 | ||
2719 | #ifdef LEX_AT | |
2720 | identifier_chars['@'] = '@'; | |
32137342 NC |
2721 | #endif |
2722 | #ifdef LEX_QM | |
2723 | identifier_chars['?'] = '?'; | |
2724 | operand_chars['?'] = '?'; | |
252b5132 | 2725 | #endif |
252b5132 | 2726 | digit_chars['-'] = '-'; |
c0f3af97 | 2727 | mnemonic_chars['_'] = '_'; |
791fe849 | 2728 | mnemonic_chars['-'] = '-'; |
0003779b | 2729 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2730 | identifier_chars['_'] = '_'; |
2731 | identifier_chars['.'] = '.'; | |
2732 | ||
2733 | for (p = operand_special_chars; *p != '\0'; p++) | |
2734 | operand_chars[(unsigned char) *p] = *p; | |
2735 | } | |
2736 | ||
a4447b93 RH |
2737 | if (flag_code == CODE_64BIT) |
2738 | { | |
ca19b261 KT |
2739 | #if defined (OBJ_COFF) && defined (TE_PE) |
2740 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
2741 | ? 32 : 16); | |
2742 | #else | |
a4447b93 | 2743 | x86_dwarf2_return_column = 16; |
ca19b261 | 2744 | #endif |
61ff971f | 2745 | x86_cie_data_alignment = -8; |
a4447b93 RH |
2746 | } |
2747 | else | |
2748 | { | |
2749 | x86_dwarf2_return_column = 8; | |
2750 | x86_cie_data_alignment = -4; | |
2751 | } | |
252b5132 RH |
2752 | } |
2753 | ||
2754 | void | |
e3bb37b5 | 2755 | i386_print_statistics (FILE *file) |
252b5132 RH |
2756 | { |
2757 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2758 | hash_print_statistics (file, "i386 register", reg_hash); | |
2759 | } | |
2760 | \f | |
252b5132 RH |
2761 | #ifdef DEBUG386 |
2762 | ||
ce8a8b2f | 2763 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 2764 | static void pte (insn_template *); |
40fb9820 | 2765 | static void pt (i386_operand_type); |
e3bb37b5 L |
2766 | static void pe (expressionS *); |
2767 | static void ps (symbolS *); | |
252b5132 RH |
2768 | |
2769 | static void | |
e3bb37b5 | 2770 | pi (char *line, i386_insn *x) |
252b5132 | 2771 | { |
09137c09 | 2772 | unsigned int j; |
252b5132 RH |
2773 | |
2774 | fprintf (stdout, "%s: template ", line); | |
2775 | pte (&x->tm); | |
09f131f2 JH |
2776 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2777 | x->base_reg ? x->base_reg->reg_name : "none", | |
2778 | x->index_reg ? x->index_reg->reg_name : "none", | |
2779 | x->log2_scale_factor); | |
2780 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 2781 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
2782 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
2783 | x->sib.base, x->sib.index, x->sib.scale); | |
2784 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
2785 | (x->rex & REX_W) != 0, |
2786 | (x->rex & REX_R) != 0, | |
2787 | (x->rex & REX_X) != 0, | |
2788 | (x->rex & REX_B) != 0); | |
09137c09 | 2789 | for (j = 0; j < x->operands; j++) |
252b5132 | 2790 | { |
09137c09 SP |
2791 | fprintf (stdout, " #%d: ", j + 1); |
2792 | pt (x->types[j]); | |
252b5132 | 2793 | fprintf (stdout, "\n"); |
09137c09 SP |
2794 | if (x->types[j].bitfield.reg8 |
2795 | || x->types[j].bitfield.reg16 | |
2796 | || x->types[j].bitfield.reg32 | |
2797 | || x->types[j].bitfield.reg64 | |
2798 | || x->types[j].bitfield.regmmx | |
2799 | || x->types[j].bitfield.regxmm | |
2800 | || x->types[j].bitfield.regymm | |
43234a1e | 2801 | || x->types[j].bitfield.regzmm |
09137c09 SP |
2802 | || x->types[j].bitfield.sreg2 |
2803 | || x->types[j].bitfield.sreg3 | |
2804 | || x->types[j].bitfield.control | |
2805 | || x->types[j].bitfield.debug | |
2806 | || x->types[j].bitfield.test) | |
2807 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); | |
2808 | if (operand_type_check (x->types[j], imm)) | |
2809 | pe (x->op[j].imms); | |
2810 | if (operand_type_check (x->types[j], disp)) | |
2811 | pe (x->op[j].disps); | |
252b5132 RH |
2812 | } |
2813 | } | |
2814 | ||
2815 | static void | |
d3ce72d0 | 2816 | pte (insn_template *t) |
252b5132 | 2817 | { |
09137c09 | 2818 | unsigned int j; |
252b5132 | 2819 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 2820 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
2821 | if (t->extension_opcode != None) |
2822 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 2823 | if (t->opcode_modifier.d) |
252b5132 | 2824 | fprintf (stdout, "D"); |
40fb9820 | 2825 | if (t->opcode_modifier.w) |
252b5132 RH |
2826 | fprintf (stdout, "W"); |
2827 | fprintf (stdout, "\n"); | |
09137c09 | 2828 | for (j = 0; j < t->operands; j++) |
252b5132 | 2829 | { |
09137c09 SP |
2830 | fprintf (stdout, " #%d type ", j + 1); |
2831 | pt (t->operand_types[j]); | |
252b5132 RH |
2832 | fprintf (stdout, "\n"); |
2833 | } | |
2834 | } | |
2835 | ||
2836 | static void | |
e3bb37b5 | 2837 | pe (expressionS *e) |
252b5132 | 2838 | { |
24eab124 | 2839 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
2840 | fprintf (stdout, " add_number %ld (%lx)\n", |
2841 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
2842 | if (e->X_add_symbol) |
2843 | { | |
2844 | fprintf (stdout, " add_symbol "); | |
2845 | ps (e->X_add_symbol); | |
2846 | fprintf (stdout, "\n"); | |
2847 | } | |
2848 | if (e->X_op_symbol) | |
2849 | { | |
2850 | fprintf (stdout, " op_symbol "); | |
2851 | ps (e->X_op_symbol); | |
2852 | fprintf (stdout, "\n"); | |
2853 | } | |
2854 | } | |
2855 | ||
2856 | static void | |
e3bb37b5 | 2857 | ps (symbolS *s) |
252b5132 RH |
2858 | { |
2859 | fprintf (stdout, "%s type %s%s", | |
2860 | S_GET_NAME (s), | |
2861 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
2862 | segment_name (S_GET_SEGMENT (s))); | |
2863 | } | |
2864 | ||
7b81dfbb | 2865 | static struct type_name |
252b5132 | 2866 | { |
40fb9820 L |
2867 | i386_operand_type mask; |
2868 | const char *name; | |
252b5132 | 2869 | } |
7b81dfbb | 2870 | const type_names[] = |
252b5132 | 2871 | { |
40fb9820 L |
2872 | { OPERAND_TYPE_REG8, "r8" }, |
2873 | { OPERAND_TYPE_REG16, "r16" }, | |
2874 | { OPERAND_TYPE_REG32, "r32" }, | |
2875 | { OPERAND_TYPE_REG64, "r64" }, | |
2876 | { OPERAND_TYPE_IMM8, "i8" }, | |
2877 | { OPERAND_TYPE_IMM8, "i8s" }, | |
2878 | { OPERAND_TYPE_IMM16, "i16" }, | |
2879 | { OPERAND_TYPE_IMM32, "i32" }, | |
2880 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
2881 | { OPERAND_TYPE_IMM64, "i64" }, | |
2882 | { OPERAND_TYPE_IMM1, "i1" }, | |
2883 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
2884 | { OPERAND_TYPE_DISP8, "d8" }, | |
2885 | { OPERAND_TYPE_DISP16, "d16" }, | |
2886 | { OPERAND_TYPE_DISP32, "d32" }, | |
2887 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
2888 | { OPERAND_TYPE_DISP64, "d64" }, | |
43234a1e | 2889 | { OPERAND_TYPE_VEC_DISP8, "Vector d8" }, |
40fb9820 L |
2890 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, |
2891 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
2892 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
2893 | { OPERAND_TYPE_TEST, "test reg" }, | |
2894 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
2895 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
2896 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
2897 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
2898 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
2899 | { OPERAND_TYPE_ACC, "Acc" }, | |
2900 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
2901 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
2902 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 2903 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
2904 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
2905 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
40fb9820 | 2906 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
2907 | }; |
2908 | ||
2909 | static void | |
40fb9820 | 2910 | pt (i386_operand_type t) |
252b5132 | 2911 | { |
40fb9820 | 2912 | unsigned int j; |
c6fb90c8 | 2913 | i386_operand_type a; |
252b5132 | 2914 | |
40fb9820 | 2915 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
2916 | { |
2917 | a = operand_type_and (t, type_names[j].mask); | |
0349dc08 | 2918 | if (!operand_type_all_zero (&a)) |
c6fb90c8 L |
2919 | fprintf (stdout, "%s, ", type_names[j].name); |
2920 | } | |
252b5132 RH |
2921 | fflush (stdout); |
2922 | } | |
2923 | ||
2924 | #endif /* DEBUG386 */ | |
2925 | \f | |
252b5132 | 2926 | static bfd_reloc_code_real_type |
3956db08 | 2927 | reloc (unsigned int size, |
64e74474 AM |
2928 | int pcrel, |
2929 | int sign, | |
2930 | bfd_reloc_code_real_type other) | |
252b5132 | 2931 | { |
47926f60 | 2932 | if (other != NO_RELOC) |
3956db08 | 2933 | { |
91d6fa6a | 2934 | reloc_howto_type *rel; |
3956db08 JB |
2935 | |
2936 | if (size == 8) | |
2937 | switch (other) | |
2938 | { | |
64e74474 AM |
2939 | case BFD_RELOC_X86_64_GOT32: |
2940 | return BFD_RELOC_X86_64_GOT64; | |
2941 | break; | |
553d1284 L |
2942 | case BFD_RELOC_X86_64_GOTPLT64: |
2943 | return BFD_RELOC_X86_64_GOTPLT64; | |
2944 | break; | |
64e74474 AM |
2945 | case BFD_RELOC_X86_64_PLTOFF64: |
2946 | return BFD_RELOC_X86_64_PLTOFF64; | |
2947 | break; | |
2948 | case BFD_RELOC_X86_64_GOTPC32: | |
2949 | other = BFD_RELOC_X86_64_GOTPC64; | |
2950 | break; | |
2951 | case BFD_RELOC_X86_64_GOTPCREL: | |
2952 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
2953 | break; | |
2954 | case BFD_RELOC_X86_64_TPOFF32: | |
2955 | other = BFD_RELOC_X86_64_TPOFF64; | |
2956 | break; | |
2957 | case BFD_RELOC_X86_64_DTPOFF32: | |
2958 | other = BFD_RELOC_X86_64_DTPOFF64; | |
2959 | break; | |
2960 | default: | |
2961 | break; | |
3956db08 | 2962 | } |
e05278af | 2963 | |
8ce3d284 | 2964 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
2965 | if (other == BFD_RELOC_SIZE32) |
2966 | { | |
2967 | if (size == 8) | |
1ab668bf | 2968 | other = BFD_RELOC_SIZE64; |
8fd4256d | 2969 | if (pcrel) |
1ab668bf AM |
2970 | { |
2971 | as_bad (_("there are no pc-relative size relocations")); | |
2972 | return NO_RELOC; | |
2973 | } | |
8fd4256d | 2974 | } |
8ce3d284 | 2975 | #endif |
8fd4256d | 2976 | |
e05278af | 2977 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 2978 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
2979 | sign = -1; |
2980 | ||
91d6fa6a NC |
2981 | rel = bfd_reloc_type_lookup (stdoutput, other); |
2982 | if (!rel) | |
3956db08 | 2983 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 2984 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 2985 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 2986 | bfd_get_reloc_size (rel), |
3956db08 | 2987 | size); |
91d6fa6a | 2988 | else if (pcrel && !rel->pc_relative) |
3956db08 | 2989 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 2990 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 2991 | && !sign) |
91d6fa6a | 2992 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 2993 | && sign > 0)) |
3956db08 JB |
2994 | as_bad (_("relocated field and relocation type differ in signedness")); |
2995 | else | |
2996 | return other; | |
2997 | return NO_RELOC; | |
2998 | } | |
252b5132 RH |
2999 | |
3000 | if (pcrel) | |
3001 | { | |
3e73aa7c | 3002 | if (!sign) |
3956db08 | 3003 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3004 | switch (size) |
3005 | { | |
3006 | case 1: return BFD_RELOC_8_PCREL; | |
3007 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3008 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3009 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3010 | } |
3956db08 | 3011 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3012 | } |
3013 | else | |
3014 | { | |
3956db08 | 3015 | if (sign > 0) |
e5cb08ac | 3016 | switch (size) |
3e73aa7c JH |
3017 | { |
3018 | case 4: return BFD_RELOC_X86_64_32S; | |
3019 | } | |
3020 | else | |
3021 | switch (size) | |
3022 | { | |
3023 | case 1: return BFD_RELOC_8; | |
3024 | case 2: return BFD_RELOC_16; | |
3025 | case 4: return BFD_RELOC_32; | |
3026 | case 8: return BFD_RELOC_64; | |
3027 | } | |
3956db08 JB |
3028 | as_bad (_("cannot do %s %u byte relocation"), |
3029 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3030 | } |
3031 | ||
0cc9e1d3 | 3032 | return NO_RELOC; |
252b5132 RH |
3033 | } |
3034 | ||
47926f60 KH |
3035 | /* Here we decide which fixups can be adjusted to make them relative to |
3036 | the beginning of the section instead of the symbol. Basically we need | |
3037 | to make sure that the dynamic relocations are done correctly, so in | |
3038 | some cases we force the original symbol to be used. */ | |
3039 | ||
252b5132 | 3040 | int |
e3bb37b5 | 3041 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3042 | { |
6d249963 | 3043 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3044 | if (!IS_ELF) |
31312f95 AM |
3045 | return 1; |
3046 | ||
a161fe53 AM |
3047 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3048 | mode. */ | |
3049 | if (use_rela_relocations | |
3050 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3051 | && fixP->fx_pcrel) | |
252b5132 | 3052 | return 0; |
31312f95 | 3053 | |
8d01d9a9 AJ |
3054 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3055 | and changed later by validate_fix. */ | |
3056 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3057 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3058 | return 0; | |
3059 | ||
8fd4256d L |
3060 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3061 | for size relocations. */ | |
3062 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3063 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3064 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 RH |
3065 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
3066 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
02a86693 | 3067 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3068 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3069 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3070 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3071 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3072 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3073 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3074 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3075 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3076 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3077 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
3078 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
3079 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 3080 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3081 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3082 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3083 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3084 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3085 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3086 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3087 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3088 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3089 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3090 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3091 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3092 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3093 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3094 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3095 | return 0; | |
31312f95 | 3096 | #endif |
252b5132 RH |
3097 | return 1; |
3098 | } | |
252b5132 | 3099 | |
b4cac588 | 3100 | static int |
e3bb37b5 | 3101 | intel_float_operand (const char *mnemonic) |
252b5132 | 3102 | { |
9306ca4a JB |
3103 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3104 | operands, hence the code here is free to improperly handle opcodes that | |
3105 | have no operands (for better performance and smaller code). */ | |
3106 | ||
3107 | if (mnemonic[0] != 'f') | |
3108 | return 0; /* non-math */ | |
3109 | ||
3110 | switch (mnemonic[1]) | |
3111 | { | |
3112 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3113 | the fs segment override prefix not currently handled because no | |
3114 | call path can make opcodes without operands get here */ | |
3115 | case 'i': | |
3116 | return 2 /* integer op */; | |
3117 | case 'l': | |
3118 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3119 | return 3; /* fldcw/fldenv */ | |
3120 | break; | |
3121 | case 'n': | |
3122 | if (mnemonic[2] != 'o' /* fnop */) | |
3123 | return 3; /* non-waiting control op */ | |
3124 | break; | |
3125 | case 'r': | |
3126 | if (mnemonic[2] == 's') | |
3127 | return 3; /* frstor/frstpm */ | |
3128 | break; | |
3129 | case 's': | |
3130 | if (mnemonic[2] == 'a') | |
3131 | return 3; /* fsave */ | |
3132 | if (mnemonic[2] == 't') | |
3133 | { | |
3134 | switch (mnemonic[3]) | |
3135 | { | |
3136 | case 'c': /* fstcw */ | |
3137 | case 'd': /* fstdw */ | |
3138 | case 'e': /* fstenv */ | |
3139 | case 's': /* fsts[gw] */ | |
3140 | return 3; | |
3141 | } | |
3142 | } | |
3143 | break; | |
3144 | case 'x': | |
3145 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3146 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3147 | break; | |
3148 | } | |
252b5132 | 3149 | |
9306ca4a | 3150 | return 1; |
252b5132 RH |
3151 | } |
3152 | ||
c0f3af97 L |
3153 | /* Build the VEX prefix. */ |
3154 | ||
3155 | static void | |
d3ce72d0 | 3156 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3157 | { |
3158 | unsigned int register_specifier; | |
3159 | unsigned int implied_prefix; | |
3160 | unsigned int vector_length; | |
3161 | ||
3162 | /* Check register specifier. */ | |
3163 | if (i.vex.register_specifier) | |
43234a1e L |
3164 | { |
3165 | register_specifier = | |
3166 | ~register_number (i.vex.register_specifier) & 0xf; | |
3167 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3168 | } | |
c0f3af97 L |
3169 | else |
3170 | register_specifier = 0xf; | |
3171 | ||
33eaf5de | 3172 | /* Use 2-byte VEX prefix by swapping destination and source |
fa99fab2 | 3173 | operand. */ |
86fa6981 L |
3174 | if (i.vec_encoding != vex_encoding_vex3 |
3175 | && i.dir_encoding == dir_encoding_default | |
fa99fab2 | 3176 | && i.operands == i.reg_operands |
7f399153 | 3177 | && i.tm.opcode_modifier.vexopcode == VEX0F |
86fa6981 | 3178 | && i.tm.opcode_modifier.load |
fa99fab2 L |
3179 | && i.rex == REX_B) |
3180 | { | |
3181 | unsigned int xchg = i.operands - 1; | |
3182 | union i386_op temp_op; | |
3183 | i386_operand_type temp_type; | |
3184 | ||
3185 | temp_type = i.types[xchg]; | |
3186 | i.types[xchg] = i.types[0]; | |
3187 | i.types[0] = temp_type; | |
3188 | temp_op = i.op[xchg]; | |
3189 | i.op[xchg] = i.op[0]; | |
3190 | i.op[0] = temp_op; | |
3191 | ||
9c2799c2 | 3192 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3193 | |
3194 | i.rex = REX_R; | |
3195 | xchg = i.rm.regmem; | |
3196 | i.rm.regmem = i.rm.reg; | |
3197 | i.rm.reg = xchg; | |
3198 | ||
3199 | /* Use the next insn. */ | |
3200 | i.tm = t[1]; | |
3201 | } | |
3202 | ||
539f890d L |
3203 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3204 | vector_length = avxscalar; | |
3205 | else | |
3206 | vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0; | |
c0f3af97 L |
3207 | |
3208 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3209 | { | |
3210 | case 0: | |
3211 | implied_prefix = 0; | |
3212 | break; | |
3213 | case DATA_PREFIX_OPCODE: | |
3214 | implied_prefix = 1; | |
3215 | break; | |
3216 | case REPE_PREFIX_OPCODE: | |
3217 | implied_prefix = 2; | |
3218 | break; | |
3219 | case REPNE_PREFIX_OPCODE: | |
3220 | implied_prefix = 3; | |
3221 | break; | |
3222 | default: | |
3223 | abort (); | |
3224 | } | |
3225 | ||
3226 | /* Use 2-byte VEX prefix if possible. */ | |
86fa6981 L |
3227 | if (i.vec_encoding != vex_encoding_vex3 |
3228 | && i.tm.opcode_modifier.vexopcode == VEX0F | |
04251de0 | 3229 | && i.tm.opcode_modifier.vexw != VEXW1 |
c0f3af97 L |
3230 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3231 | { | |
3232 | /* 2-byte VEX prefix. */ | |
3233 | unsigned int r; | |
3234 | ||
3235 | i.vex.length = 2; | |
3236 | i.vex.bytes[0] = 0xc5; | |
3237 | ||
3238 | /* Check the REX.R bit. */ | |
3239 | r = (i.rex & REX_R) ? 0 : 1; | |
3240 | i.vex.bytes[1] = (r << 7 | |
3241 | | register_specifier << 3 | |
3242 | | vector_length << 2 | |
3243 | | implied_prefix); | |
3244 | } | |
3245 | else | |
3246 | { | |
3247 | /* 3-byte VEX prefix. */ | |
3248 | unsigned int m, w; | |
3249 | ||
f88c9eb0 | 3250 | i.vex.length = 3; |
f88c9eb0 | 3251 | |
7f399153 | 3252 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3253 | { |
7f399153 L |
3254 | case VEX0F: |
3255 | m = 0x1; | |
80de6e00 | 3256 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3257 | break; |
3258 | case VEX0F38: | |
3259 | m = 0x2; | |
80de6e00 | 3260 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3261 | break; |
3262 | case VEX0F3A: | |
3263 | m = 0x3; | |
80de6e00 | 3264 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3265 | break; |
3266 | case XOP08: | |
5dd85c99 SP |
3267 | m = 0x8; |
3268 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3269 | break; |
3270 | case XOP09: | |
f88c9eb0 SP |
3271 | m = 0x9; |
3272 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3273 | break; |
3274 | case XOP0A: | |
f88c9eb0 SP |
3275 | m = 0xa; |
3276 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3277 | break; |
3278 | default: | |
3279 | abort (); | |
f88c9eb0 | 3280 | } |
c0f3af97 | 3281 | |
c0f3af97 L |
3282 | /* The high 3 bits of the second VEX byte are 1's compliment |
3283 | of RXB bits from REX. */ | |
3284 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3285 | ||
3286 | /* Check the REX.W bit. */ | |
3287 | w = (i.rex & REX_W) ? 1 : 0; | |
b28d1bda IT |
3288 | if (i.tm.opcode_modifier.vexw == VEXW1) |
3289 | w = 1; | |
c0f3af97 L |
3290 | |
3291 | i.vex.bytes[2] = (w << 7 | |
3292 | | register_specifier << 3 | |
3293 | | vector_length << 2 | |
3294 | | implied_prefix); | |
3295 | } | |
3296 | } | |
3297 | ||
43234a1e L |
3298 | /* Build the EVEX prefix. */ |
3299 | ||
3300 | static void | |
3301 | build_evex_prefix (void) | |
3302 | { | |
3303 | unsigned int register_specifier; | |
3304 | unsigned int implied_prefix; | |
3305 | unsigned int m, w; | |
3306 | rex_byte vrex_used = 0; | |
3307 | ||
3308 | /* Check register specifier. */ | |
3309 | if (i.vex.register_specifier) | |
3310 | { | |
3311 | gas_assert ((i.vrex & REX_X) == 0); | |
3312 | ||
3313 | register_specifier = i.vex.register_specifier->reg_num; | |
3314 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3315 | register_specifier += 8; | |
3316 | /* The upper 16 registers are encoded in the fourth byte of the | |
3317 | EVEX prefix. */ | |
3318 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3319 | i.vex.bytes[3] = 0x8; | |
3320 | register_specifier = ~register_specifier & 0xf; | |
3321 | } | |
3322 | else | |
3323 | { | |
3324 | register_specifier = 0xf; | |
3325 | ||
3326 | /* Encode upper 16 vector index register in the fourth byte of | |
3327 | the EVEX prefix. */ | |
3328 | if (!(i.vrex & REX_X)) | |
3329 | i.vex.bytes[3] = 0x8; | |
3330 | else | |
3331 | vrex_used |= REX_X; | |
3332 | } | |
3333 | ||
3334 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3335 | { | |
3336 | case 0: | |
3337 | implied_prefix = 0; | |
3338 | break; | |
3339 | case DATA_PREFIX_OPCODE: | |
3340 | implied_prefix = 1; | |
3341 | break; | |
3342 | case REPE_PREFIX_OPCODE: | |
3343 | implied_prefix = 2; | |
3344 | break; | |
3345 | case REPNE_PREFIX_OPCODE: | |
3346 | implied_prefix = 3; | |
3347 | break; | |
3348 | default: | |
3349 | abort (); | |
3350 | } | |
3351 | ||
3352 | /* 4 byte EVEX prefix. */ | |
3353 | i.vex.length = 4; | |
3354 | i.vex.bytes[0] = 0x62; | |
3355 | ||
3356 | /* mmmm bits. */ | |
3357 | switch (i.tm.opcode_modifier.vexopcode) | |
3358 | { | |
3359 | case VEX0F: | |
3360 | m = 1; | |
3361 | break; | |
3362 | case VEX0F38: | |
3363 | m = 2; | |
3364 | break; | |
3365 | case VEX0F3A: | |
3366 | m = 3; | |
3367 | break; | |
3368 | default: | |
3369 | abort (); | |
3370 | break; | |
3371 | } | |
3372 | ||
3373 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3374 | bits from REX. */ | |
3375 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3376 | ||
3377 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3378 | REX_R bit in VREX. */ | |
3379 | if (!(i.vrex & REX_R)) | |
3380 | i.vex.bytes[1] |= 0x10; | |
3381 | else | |
3382 | vrex_used |= REX_R; | |
3383 | ||
3384 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3385 | { | |
3386 | /* When all operands are registers, the REX_X bit in REX is not | |
3387 | used. We reuse it to encode the upper 16 registers, which is | |
3388 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3389 | as 1's compliment. */ | |
3390 | if ((i.vrex & REX_B)) | |
3391 | { | |
3392 | vrex_used |= REX_B; | |
3393 | i.vex.bytes[1] &= ~0x40; | |
3394 | } | |
3395 | } | |
3396 | ||
3397 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3398 | i.vrex &= ~vrex_used; | |
3399 | gas_assert (i.vrex == 0); | |
3400 | ||
3401 | /* Check the REX.W bit. */ | |
3402 | w = (i.rex & REX_W) ? 1 : 0; | |
3403 | if (i.tm.opcode_modifier.vexw) | |
3404 | { | |
3405 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
3406 | w = 1; | |
3407 | } | |
3408 | /* If w is not set it means we are dealing with WIG instruction. */ | |
3409 | else if (!w) | |
3410 | { | |
3411 | if (evexwig == evexw1) | |
3412 | w = 1; | |
3413 | } | |
3414 | ||
3415 | /* Encode the U bit. */ | |
3416 | implied_prefix |= 0x4; | |
3417 | ||
3418 | /* The third byte of the EVEX prefix. */ | |
3419 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3420 | ||
3421 | /* The fourth byte of the EVEX prefix. */ | |
3422 | /* The zeroing-masking bit. */ | |
3423 | if (i.mask && i.mask->zeroing) | |
3424 | i.vex.bytes[3] |= 0x80; | |
3425 | ||
3426 | /* Don't always set the broadcast bit if there is no RC. */ | |
3427 | if (!i.rounding) | |
3428 | { | |
3429 | /* Encode the vector length. */ | |
3430 | unsigned int vec_length; | |
3431 | ||
3432 | switch (i.tm.opcode_modifier.evex) | |
3433 | { | |
3434 | case EVEXLIG: /* LL' is ignored */ | |
3435 | vec_length = evexlig << 5; | |
3436 | break; | |
3437 | case EVEX128: | |
3438 | vec_length = 0 << 5; | |
3439 | break; | |
3440 | case EVEX256: | |
3441 | vec_length = 1 << 5; | |
3442 | break; | |
3443 | case EVEX512: | |
3444 | vec_length = 2 << 5; | |
3445 | break; | |
3446 | default: | |
3447 | abort (); | |
3448 | break; | |
3449 | } | |
3450 | i.vex.bytes[3] |= vec_length; | |
3451 | /* Encode the broadcast bit. */ | |
3452 | if (i.broadcast) | |
3453 | i.vex.bytes[3] |= 0x10; | |
3454 | } | |
3455 | else | |
3456 | { | |
3457 | if (i.rounding->type != saeonly) | |
3458 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3459 | else | |
d3d3c6db | 3460 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3461 | } |
3462 | ||
3463 | if (i.mask && i.mask->mask) | |
3464 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3465 | } | |
3466 | ||
65da13b5 L |
3467 | static void |
3468 | process_immext (void) | |
3469 | { | |
3470 | expressionS *exp; | |
3471 | ||
4c692bc7 JB |
3472 | if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) |
3473 | && i.operands > 0) | |
65da13b5 | 3474 | { |
4c692bc7 JB |
3475 | /* MONITOR/MWAIT as well as SVME instructions have fixed operands |
3476 | with an opcode suffix which is coded in the same place as an | |
3477 | 8-bit immediate field would be. | |
3478 | Here we check those operands and remove them afterwards. */ | |
65da13b5 L |
3479 | unsigned int x; |
3480 | ||
3481 | for (x = 0; x < i.operands; x++) | |
4c692bc7 | 3482 | if (register_number (i.op[x].regs) != x) |
65da13b5 | 3483 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
1fed0ba1 L |
3484 | register_prefix, i.op[x].regs->reg_name, x + 1, |
3485 | i.tm.name); | |
3486 | ||
3487 | i.operands = 0; | |
65da13b5 L |
3488 | } |
3489 | ||
9916071f AP |
3490 | if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0) |
3491 | { | |
3492 | /* MONITORX/MWAITX instructions have fixed operands with an opcode | |
3493 | suffix which is coded in the same place as an 8-bit immediate | |
3494 | field would be. | |
3495 | Here we check those operands and remove them afterwards. */ | |
3496 | unsigned int x; | |
3497 | ||
3498 | if (i.operands != 3) | |
3499 | abort(); | |
3500 | ||
3501 | for (x = 0; x < 2; x++) | |
3502 | if (register_number (i.op[x].regs) != x) | |
3503 | goto bad_register_operand; | |
3504 | ||
3505 | /* Check for third operand for mwaitx/monitorx insn. */ | |
3506 | if (register_number (i.op[x].regs) | |
3507 | != (x + (i.tm.extension_opcode == 0xfb))) | |
3508 | { | |
3509 | bad_register_operand: | |
3510 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
3511 | register_prefix, i.op[x].regs->reg_name, x+1, | |
3512 | i.tm.name); | |
3513 | } | |
3514 | ||
3515 | i.operands = 0; | |
3516 | } | |
3517 | ||
c0f3af97 | 3518 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3519 | which is coded in the same place as an 8-bit immediate field |
3520 | would be. Here we fake an 8-bit immediate operand from the | |
3521 | opcode suffix stored in tm.extension_opcode. | |
3522 | ||
c1e679ec | 3523 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3524 | 3 argument instructions. */ |
65da13b5 | 3525 | |
43234a1e | 3526 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3527 | && (i.operands <= 2 |
43234a1e L |
3528 | || ((i.tm.opcode_modifier.vex |
3529 | || i.tm.opcode_modifier.evex) | |
7ab9ffdd | 3530 | && i.operands <= 4))); |
65da13b5 L |
3531 | |
3532 | exp = &im_expressions[i.imm_operands++]; | |
3533 | i.op[i.operands].imms = exp; | |
3534 | i.types[i.operands] = imm8; | |
3535 | i.operands++; | |
3536 | exp->X_op = O_constant; | |
3537 | exp->X_add_number = i.tm.extension_opcode; | |
3538 | i.tm.extension_opcode = None; | |
3539 | } | |
3540 | ||
42164a71 L |
3541 | |
3542 | static int | |
3543 | check_hle (void) | |
3544 | { | |
3545 | switch (i.tm.opcode_modifier.hleprefixok) | |
3546 | { | |
3547 | default: | |
3548 | abort (); | |
82c2def5 | 3549 | case HLEPrefixNone: |
165de32a L |
3550 | as_bad (_("invalid instruction `%s' after `%s'"), |
3551 | i.tm.name, i.hle_prefix); | |
42164a71 | 3552 | return 0; |
82c2def5 | 3553 | case HLEPrefixLock: |
42164a71 L |
3554 | if (i.prefix[LOCK_PREFIX]) |
3555 | return 1; | |
165de32a | 3556 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3557 | return 0; |
82c2def5 | 3558 | case HLEPrefixAny: |
42164a71 | 3559 | return 1; |
82c2def5 | 3560 | case HLEPrefixRelease: |
42164a71 L |
3561 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3562 | { | |
3563 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3564 | i.tm.name); | |
3565 | return 0; | |
3566 | } | |
3567 | if (i.mem_operands == 0 | |
3568 | || !operand_type_check (i.types[i.operands - 1], anymem)) | |
3569 | { | |
3570 | as_bad (_("memory destination needed for instruction `%s'" | |
3571 | " after `xrelease'"), i.tm.name); | |
3572 | return 0; | |
3573 | } | |
3574 | return 1; | |
3575 | } | |
3576 | } | |
3577 | ||
252b5132 RH |
3578 | /* This is the guts of the machine-dependent assembler. LINE points to a |
3579 | machine dependent instruction. This function is supposed to emit | |
3580 | the frags/bytes it assembles to. */ | |
3581 | ||
3582 | void | |
65da13b5 | 3583 | md_assemble (char *line) |
252b5132 | 3584 | { |
40fb9820 | 3585 | unsigned int j; |
83b16ac6 | 3586 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 3587 | const insn_template *t; |
252b5132 | 3588 | |
47926f60 | 3589 | /* Initialize globals. */ |
252b5132 RH |
3590 | memset (&i, '\0', sizeof (i)); |
3591 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 3592 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
3593 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
3594 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 3595 | save_stack_p = save_stack; |
252b5132 RH |
3596 | |
3597 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
3598 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 3599 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 3600 | |
29b0f896 AM |
3601 | line = parse_insn (line, mnemonic); |
3602 | if (line == NULL) | |
3603 | return; | |
83b16ac6 | 3604 | mnem_suffix = i.suffix; |
252b5132 | 3605 | |
29b0f896 | 3606 | line = parse_operands (line, mnemonic); |
ee86248c | 3607 | this_operand = -1; |
8325cc63 JB |
3608 | xfree (i.memop1_string); |
3609 | i.memop1_string = NULL; | |
29b0f896 AM |
3610 | if (line == NULL) |
3611 | return; | |
252b5132 | 3612 | |
29b0f896 AM |
3613 | /* Now we've parsed the mnemonic into a set of templates, and have the |
3614 | operands at hand. */ | |
3615 | ||
3616 | /* All intel opcodes have reversed operands except for "bound" and | |
3617 | "enter". We also don't reverse intersegment "jmp" and "call" | |
3618 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 3619 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
3620 | if (intel_syntax |
3621 | && i.operands > 1 | |
29b0f896 | 3622 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 3623 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
3624 | && !(operand_type_check (i.types[0], imm) |
3625 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
3626 | swap_operands (); |
3627 | ||
ec56d5c0 JB |
3628 | /* The order of the immediates should be reversed |
3629 | for 2 immediates extrq and insertq instructions */ | |
3630 | if (i.imm_operands == 2 | |
3631 | && (strcmp (mnemonic, "extrq") == 0 | |
3632 | || strcmp (mnemonic, "insertq") == 0)) | |
3633 | swap_2_operands (0, 1); | |
3634 | ||
29b0f896 AM |
3635 | if (i.imm_operands) |
3636 | optimize_imm (); | |
3637 | ||
b300c311 L |
3638 | /* Don't optimize displacement for movabs since it only takes 64bit |
3639 | displacement. */ | |
3640 | if (i.disp_operands | |
a501d77e | 3641 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
3642 | && (flag_code != CODE_64BIT |
3643 | || strcmp (mnemonic, "movabs") != 0)) | |
3644 | optimize_disp (); | |
29b0f896 AM |
3645 | |
3646 | /* Next, we find a template that matches the given insn, | |
3647 | making sure the overlap of the given operands types is consistent | |
3648 | with the template operand types. */ | |
252b5132 | 3649 | |
83b16ac6 | 3650 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 3651 | return; |
252b5132 | 3652 | |
7bab8ab5 | 3653 | if (sse_check != check_none |
81f8a913 | 3654 | && !i.tm.opcode_modifier.noavx |
daf50ae7 L |
3655 | && (i.tm.cpu_flags.bitfield.cpusse |
3656 | || i.tm.cpu_flags.bitfield.cpusse2 | |
3657 | || i.tm.cpu_flags.bitfield.cpusse3 | |
3658 | || i.tm.cpu_flags.bitfield.cpussse3 | |
3659 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
3660 | || i.tm.cpu_flags.bitfield.cpusse4_2)) | |
3661 | { | |
7bab8ab5 | 3662 | (sse_check == check_warning |
daf50ae7 L |
3663 | ? as_warn |
3664 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
3665 | } | |
3666 | ||
321fd21e L |
3667 | /* Zap movzx and movsx suffix. The suffix has been set from |
3668 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
3669 | or extracted from mnemonic in AT&T syntax. But we'll use | |
3670 | the destination register to choose the suffix for encoding. */ | |
3671 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 3672 | { |
321fd21e L |
3673 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
3674 | there is no suffix, the default will be byte extension. */ | |
3675 | if (i.reg_operands != 2 | |
3676 | && !i.suffix | |
7ab9ffdd | 3677 | && intel_syntax) |
321fd21e L |
3678 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
3679 | ||
3680 | i.suffix = 0; | |
cd61ebfe | 3681 | } |
24eab124 | 3682 | |
40fb9820 | 3683 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
3684 | if (!add_prefix (FWAIT_OPCODE)) |
3685 | return; | |
252b5132 | 3686 | |
d5de92cf L |
3687 | /* Check if REP prefix is OK. */ |
3688 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
3689 | { | |
3690 | as_bad (_("invalid instruction `%s' after `%s'"), | |
3691 | i.tm.name, i.rep_prefix); | |
3692 | return; | |
3693 | } | |
3694 | ||
c1ba0266 L |
3695 | /* Check for lock without a lockable instruction. Destination operand |
3696 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
3697 | if (i.prefix[LOCK_PREFIX] |
3698 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
3699 | || i.mem_operands == 0 |
3700 | || (i.tm.base_opcode != 0x86 | |
3701 | && !operand_type_check (i.types[i.operands - 1], anymem)))) | |
c32fa91d L |
3702 | { |
3703 | as_bad (_("expecting lockable instruction after `lock'")); | |
3704 | return; | |
3705 | } | |
3706 | ||
42164a71 | 3707 | /* Check if HLE prefix is OK. */ |
165de32a | 3708 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
3709 | return; |
3710 | ||
7e8b059b L |
3711 | /* Check BND prefix. */ |
3712 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
3713 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
3714 | ||
04ef582a | 3715 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
3716 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
3717 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 3718 | |
327e8c42 JB |
3719 | if (i.tm.cpu_flags.bitfield.cpumpx) |
3720 | { | |
3721 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
3722 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
3723 | else if (flag_code != CODE_16BIT | |
3724 | ? i.prefix[ADDR_PREFIX] | |
3725 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
3726 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
3727 | } | |
7e8b059b L |
3728 | |
3729 | /* Insert BND prefix. */ | |
3730 | if (add_bnd_prefix | |
3731 | && i.tm.opcode_modifier.bndprefixok | |
3732 | && !i.prefix[BND_PREFIX]) | |
3733 | add_prefix (BND_PREFIX_OPCODE); | |
3734 | ||
29b0f896 | 3735 | /* Check string instruction segment overrides. */ |
40fb9820 | 3736 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
3737 | { |
3738 | if (!check_string ()) | |
5dd0794d | 3739 | return; |
fc0763e6 | 3740 | i.disp_operands = 0; |
29b0f896 | 3741 | } |
5dd0794d | 3742 | |
29b0f896 AM |
3743 | if (!process_suffix ()) |
3744 | return; | |
e413e4e9 | 3745 | |
bc0844ae L |
3746 | /* Update operand types. */ |
3747 | for (j = 0; j < i.operands; j++) | |
3748 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
3749 | ||
29b0f896 AM |
3750 | /* Make still unresolved immediate matches conform to size of immediate |
3751 | given in i.suffix. */ | |
3752 | if (!finalize_imm ()) | |
3753 | return; | |
252b5132 | 3754 | |
40fb9820 | 3755 | if (i.types[0].bitfield.imm1) |
29b0f896 | 3756 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 3757 | |
9afe6eb8 L |
3758 | /* We only need to check those implicit registers for instructions |
3759 | with 3 operands or less. */ | |
3760 | if (i.operands <= 3) | |
3761 | for (j = 0; j < i.operands; j++) | |
3762 | if (i.types[j].bitfield.inoutportreg | |
3763 | || i.types[j].bitfield.shiftcount | |
3764 | || i.types[j].bitfield.acc | |
3765 | || i.types[j].bitfield.floatacc) | |
3766 | i.reg_operands--; | |
40fb9820 | 3767 | |
c0f3af97 L |
3768 | /* ImmExt should be processed after SSE2AVX. */ |
3769 | if (!i.tm.opcode_modifier.sse2avx | |
3770 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 3771 | process_immext (); |
252b5132 | 3772 | |
29b0f896 AM |
3773 | /* For insns with operands there are more diddles to do to the opcode. */ |
3774 | if (i.operands) | |
3775 | { | |
3776 | if (!process_operands ()) | |
3777 | return; | |
3778 | } | |
40fb9820 | 3779 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
3780 | { |
3781 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
3782 | as_warn (_("translating to `%sp'"), i.tm.name); | |
3783 | } | |
252b5132 | 3784 | |
9e5e5283 L |
3785 | if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex) |
3786 | { | |
3787 | if (flag_code == CODE_16BIT) | |
3788 | { | |
3789 | as_bad (_("instruction `%s' isn't supported in 16-bit mode."), | |
3790 | i.tm.name); | |
3791 | return; | |
3792 | } | |
c0f3af97 | 3793 | |
9e5e5283 L |
3794 | if (i.tm.opcode_modifier.vex) |
3795 | build_vex_prefix (t); | |
3796 | else | |
3797 | build_evex_prefix (); | |
3798 | } | |
43234a1e | 3799 | |
5dd85c99 SP |
3800 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
3801 | instructions may define INT_OPCODE as well, so avoid this corner | |
3802 | case for those instructions that use MODRM. */ | |
3803 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
3804 | && !i.tm.opcode_modifier.modrm |
3805 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
3806 | { |
3807 | i.tm.base_opcode = INT3_OPCODE; | |
3808 | i.imm_operands = 0; | |
3809 | } | |
252b5132 | 3810 | |
40fb9820 L |
3811 | if ((i.tm.opcode_modifier.jump |
3812 | || i.tm.opcode_modifier.jumpbyte | |
3813 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
3814 | && i.op[0].disps->X_op == O_constant) |
3815 | { | |
3816 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
3817 | the absolute address given by the constant. Since ix86 jumps and | |
3818 | calls are pc relative, we need to generate a reloc. */ | |
3819 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
3820 | i.op[0].disps->X_op = O_symbol; | |
3821 | } | |
252b5132 | 3822 | |
40fb9820 | 3823 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 3824 | i.rex |= REX_W; |
252b5132 | 3825 | |
29b0f896 AM |
3826 | /* For 8 bit registers we need an empty rex prefix. Also if the |
3827 | instruction already has a prefix, we need to convert old | |
3828 | registers to new ones. */ | |
773f551c | 3829 | |
40fb9820 | 3830 | if ((i.types[0].bitfield.reg8 |
29b0f896 | 3831 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
40fb9820 | 3832 | || (i.types[1].bitfield.reg8 |
29b0f896 | 3833 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
40fb9820 L |
3834 | || ((i.types[0].bitfield.reg8 |
3835 | || i.types[1].bitfield.reg8) | |
29b0f896 AM |
3836 | && i.rex != 0)) |
3837 | { | |
3838 | int x; | |
726c5dcd | 3839 | |
29b0f896 AM |
3840 | i.rex |= REX_OPCODE; |
3841 | for (x = 0; x < 2; x++) | |
3842 | { | |
3843 | /* Look for 8 bit operand that uses old registers. */ | |
40fb9820 | 3844 | if (i.types[x].bitfield.reg8 |
29b0f896 | 3845 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 3846 | { |
29b0f896 AM |
3847 | /* In case it is "hi" register, give up. */ |
3848 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 3849 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 3850 | "instruction requiring REX prefix."), |
a540244d | 3851 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 3852 | |
29b0f896 AM |
3853 | /* Otherwise it is equivalent to the extended register. |
3854 | Since the encoding doesn't change this is merely | |
3855 | cosmetic cleanup for debug output. */ | |
3856 | ||
3857 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 3858 | } |
29b0f896 AM |
3859 | } |
3860 | } | |
773f551c | 3861 | |
7ab9ffdd | 3862 | if (i.rex != 0) |
29b0f896 AM |
3863 | add_prefix (REX_OPCODE | i.rex); |
3864 | ||
3865 | /* We are ready to output the insn. */ | |
3866 | output_insn (); | |
3867 | } | |
3868 | ||
3869 | static char * | |
e3bb37b5 | 3870 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
3871 | { |
3872 | char *l = line; | |
3873 | char *token_start = l; | |
3874 | char *mnem_p; | |
5c6af06e | 3875 | int supported; |
d3ce72d0 | 3876 | const insn_template *t; |
b6169b20 | 3877 | char *dot_p = NULL; |
29b0f896 | 3878 | |
29b0f896 AM |
3879 | while (1) |
3880 | { | |
3881 | mnem_p = mnemonic; | |
3882 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
3883 | { | |
b6169b20 L |
3884 | if (*mnem_p == '.') |
3885 | dot_p = mnem_p; | |
29b0f896 AM |
3886 | mnem_p++; |
3887 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 3888 | { |
29b0f896 AM |
3889 | as_bad (_("no such instruction: `%s'"), token_start); |
3890 | return NULL; | |
3891 | } | |
3892 | l++; | |
3893 | } | |
3894 | if (!is_space_char (*l) | |
3895 | && *l != END_OF_INSN | |
e44823cf JB |
3896 | && (intel_syntax |
3897 | || (*l != PREFIX_SEPARATOR | |
3898 | && *l != ','))) | |
29b0f896 AM |
3899 | { |
3900 | as_bad (_("invalid character %s in mnemonic"), | |
3901 | output_invalid (*l)); | |
3902 | return NULL; | |
3903 | } | |
3904 | if (token_start == l) | |
3905 | { | |
e44823cf | 3906 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
3907 | as_bad (_("expecting prefix; got nothing")); |
3908 | else | |
3909 | as_bad (_("expecting mnemonic; got nothing")); | |
3910 | return NULL; | |
3911 | } | |
45288df1 | 3912 | |
29b0f896 | 3913 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 3914 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 3915 | |
29b0f896 AM |
3916 | if (*l != END_OF_INSN |
3917 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
3918 | && current_templates | |
40fb9820 | 3919 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 3920 | { |
c6fb90c8 | 3921 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
3922 | { |
3923 | as_bad ((flag_code != CODE_64BIT | |
3924 | ? _("`%s' is only supported in 64-bit mode") | |
3925 | : _("`%s' is not supported in 64-bit mode")), | |
3926 | current_templates->start->name); | |
3927 | return NULL; | |
3928 | } | |
29b0f896 AM |
3929 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
3930 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
3931 | if ((current_templates->start->opcode_modifier.size16 |
3932 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 3933 | && flag_code != CODE_64BIT |
40fb9820 | 3934 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
3935 | ^ (flag_code == CODE_16BIT))) |
3936 | { | |
3937 | as_bad (_("redundant %s prefix"), | |
3938 | current_templates->start->name); | |
3939 | return NULL; | |
45288df1 | 3940 | } |
86fa6981 | 3941 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 3942 | { |
86fa6981 L |
3943 | /* Handle pseudo prefixes. */ |
3944 | switch (current_templates->start->base_opcode) | |
3945 | { | |
3946 | case 0x0: | |
3947 | /* {disp8} */ | |
3948 | i.disp_encoding = disp_encoding_8bit; | |
3949 | break; | |
3950 | case 0x1: | |
3951 | /* {disp32} */ | |
3952 | i.disp_encoding = disp_encoding_32bit; | |
3953 | break; | |
3954 | case 0x2: | |
3955 | /* {load} */ | |
3956 | i.dir_encoding = dir_encoding_load; | |
3957 | break; | |
3958 | case 0x3: | |
3959 | /* {store} */ | |
3960 | i.dir_encoding = dir_encoding_store; | |
3961 | break; | |
3962 | case 0x4: | |
3963 | /* {vex2} */ | |
3964 | i.vec_encoding = vex_encoding_vex2; | |
3965 | break; | |
3966 | case 0x5: | |
3967 | /* {vex3} */ | |
3968 | i.vec_encoding = vex_encoding_vex3; | |
3969 | break; | |
3970 | case 0x6: | |
3971 | /* {evex} */ | |
3972 | i.vec_encoding = vex_encoding_evex; | |
3973 | break; | |
3974 | default: | |
3975 | abort (); | |
3976 | } | |
3977 | } | |
3978 | else | |
3979 | { | |
3980 | /* Add prefix, checking for repeated prefixes. */ | |
04ef582a L |
3981 | enum PREFIX_GROUP p |
3982 | = add_prefix (current_templates->start->base_opcode); | |
3983 | if (p == PREFIX_DS | |
3984 | && current_templates->start->cpu_flags.bitfield.cpucet) | |
86fa6981 | 3985 | { |
04ef582a L |
3986 | i.notrack_prefix = current_templates->start->name; |
3987 | /* Move NOTRACK_PREFIX_OPCODE to NOTRACK_PREFIX slot so | |
3988 | that it is placed before others. */ | |
3989 | i.prefix[SEG_PREFIX] = 0; | |
3990 | i.prefix[NOTRACK_PREFIX] = NOTRACK_PREFIX_OPCODE; | |
3991 | } | |
3992 | else | |
3993 | { | |
3994 | switch (p) | |
3995 | { | |
3996 | case PREFIX_EXIST: | |
3997 | return NULL; | |
3998 | case PREFIX_REP: | |
3999 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
4000 | i.hle_prefix = current_templates->start->name; | |
4001 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
4002 | i.bnd_prefix = current_templates->start->name; | |
4003 | else | |
4004 | i.rep_prefix = current_templates->start->name; | |
4005 | break; | |
4006 | default: | |
4007 | break; | |
4008 | } | |
4009 | ||
4010 | if (i.notrack_prefix != NULL) | |
4011 | { | |
4012 | /* There must be no other prefixes after NOTRACK | |
4013 | prefix. */ | |
4014 | as_bad (_("expecting no other prefixes after `notrack'")); | |
4015 | return NULL; | |
4016 | } | |
86fa6981 | 4017 | } |
29b0f896 AM |
4018 | } |
4019 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
4020 | token_start = ++l; | |
4021 | } | |
4022 | else | |
4023 | break; | |
4024 | } | |
45288df1 | 4025 | |
30a55f88 | 4026 | if (!current_templates) |
b6169b20 | 4027 | { |
f8a5c266 L |
4028 | /* Check if we should swap operand or force 32bit displacement in |
4029 | encoding. */ | |
30a55f88 | 4030 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
86fa6981 | 4031 | i.dir_encoding = dir_encoding_store; |
8d63c93e | 4032 | else if (mnem_p - 3 == dot_p |
a501d77e L |
4033 | && dot_p[1] == 'd' |
4034 | && dot_p[2] == '8') | |
4035 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 4036 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
4037 | && dot_p[1] == 'd' |
4038 | && dot_p[2] == '3' | |
4039 | && dot_p[3] == '2') | |
a501d77e | 4040 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
4041 | else |
4042 | goto check_suffix; | |
4043 | mnem_p = dot_p; | |
4044 | *dot_p = '\0'; | |
d3ce72d0 | 4045 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
4046 | } |
4047 | ||
29b0f896 AM |
4048 | if (!current_templates) |
4049 | { | |
b6169b20 | 4050 | check_suffix: |
29b0f896 AM |
4051 | /* See if we can get a match by trimming off a suffix. */ |
4052 | switch (mnem_p[-1]) | |
4053 | { | |
4054 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
4055 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
4056 | i.suffix = SHORT_MNEM_SUFFIX; | |
4057 | else | |
1a0670f3 | 4058 | /* Fall through. */ |
29b0f896 AM |
4059 | case BYTE_MNEM_SUFFIX: |
4060 | case QWORD_MNEM_SUFFIX: | |
4061 | i.suffix = mnem_p[-1]; | |
4062 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4063 | current_templates = (const templates *) hash_find (op_hash, |
4064 | mnemonic); | |
29b0f896 AM |
4065 | break; |
4066 | case SHORT_MNEM_SUFFIX: | |
4067 | case LONG_MNEM_SUFFIX: | |
4068 | if (!intel_syntax) | |
4069 | { | |
4070 | i.suffix = mnem_p[-1]; | |
4071 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4072 | current_templates = (const templates *) hash_find (op_hash, |
4073 | mnemonic); | |
29b0f896 AM |
4074 | } |
4075 | break; | |
252b5132 | 4076 | |
29b0f896 AM |
4077 | /* Intel Syntax. */ |
4078 | case 'd': | |
4079 | if (intel_syntax) | |
4080 | { | |
9306ca4a | 4081 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
4082 | i.suffix = SHORT_MNEM_SUFFIX; |
4083 | else | |
4084 | i.suffix = LONG_MNEM_SUFFIX; | |
4085 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4086 | current_templates = (const templates *) hash_find (op_hash, |
4087 | mnemonic); | |
29b0f896 AM |
4088 | } |
4089 | break; | |
4090 | } | |
4091 | if (!current_templates) | |
4092 | { | |
4093 | as_bad (_("no such instruction: `%s'"), token_start); | |
4094 | return NULL; | |
4095 | } | |
4096 | } | |
252b5132 | 4097 | |
40fb9820 L |
4098 | if (current_templates->start->opcode_modifier.jump |
4099 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
4100 | { |
4101 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4102 | predict taken and predict not taken respectively. | |
4103 | I'm not sure that branch hints actually do anything on loop | |
4104 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4105 | may work in the future and it doesn't hurt to accept them | |
4106 | now. */ | |
4107 | if (l[0] == ',' && l[1] == 'p') | |
4108 | { | |
4109 | if (l[2] == 't') | |
4110 | { | |
4111 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4112 | return NULL; | |
4113 | l += 3; | |
4114 | } | |
4115 | else if (l[2] == 'n') | |
4116 | { | |
4117 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4118 | return NULL; | |
4119 | l += 3; | |
4120 | } | |
4121 | } | |
4122 | } | |
4123 | /* Any other comma loses. */ | |
4124 | if (*l == ',') | |
4125 | { | |
4126 | as_bad (_("invalid character %s in mnemonic"), | |
4127 | output_invalid (*l)); | |
4128 | return NULL; | |
4129 | } | |
252b5132 | 4130 | |
29b0f896 | 4131 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4132 | supported = 0; |
4133 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4134 | { | |
c0f3af97 L |
4135 | supported |= cpu_flags_match (t); |
4136 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
3629bb00 | 4137 | goto skip; |
5c6af06e | 4138 | } |
3629bb00 | 4139 | |
c0f3af97 | 4140 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5c6af06e JB |
4141 | { |
4142 | as_bad (flag_code == CODE_64BIT | |
4143 | ? _("`%s' is not supported in 64-bit mode") | |
4144 | : _("`%s' is only supported in 64-bit mode"), | |
4145 | current_templates->start->name); | |
4146 | return NULL; | |
4147 | } | |
c0f3af97 | 4148 | if (supported != CPU_FLAGS_PERFECT_MATCH) |
29b0f896 | 4149 | { |
3629bb00 | 4150 | as_bad (_("`%s' is not supported on `%s%s'"), |
7ab9ffdd | 4151 | current_templates->start->name, |
41aacd83 | 4152 | cpu_arch_name ? cpu_arch_name : default_arch, |
3629bb00 L |
4153 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); |
4154 | return NULL; | |
29b0f896 | 4155 | } |
3629bb00 L |
4156 | |
4157 | skip: | |
4158 | if (!cpu_arch_flags.bitfield.cpui386 | |
40fb9820 | 4159 | && (flag_code != CODE_16BIT)) |
29b0f896 AM |
4160 | { |
4161 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
4162 | } | |
252b5132 | 4163 | |
29b0f896 AM |
4164 | return l; |
4165 | } | |
252b5132 | 4166 | |
29b0f896 | 4167 | static char * |
e3bb37b5 | 4168 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4169 | { |
4170 | char *token_start; | |
3138f287 | 4171 | |
29b0f896 AM |
4172 | /* 1 if operand is pending after ','. */ |
4173 | unsigned int expecting_operand = 0; | |
252b5132 | 4174 | |
29b0f896 AM |
4175 | /* Non-zero if operand parens not balanced. */ |
4176 | unsigned int paren_not_balanced; | |
4177 | ||
4178 | while (*l != END_OF_INSN) | |
4179 | { | |
4180 | /* Skip optional white space before operand. */ | |
4181 | if (is_space_char (*l)) | |
4182 | ++l; | |
d02603dc | 4183 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4184 | { |
4185 | as_bad (_("invalid character %s before operand %d"), | |
4186 | output_invalid (*l), | |
4187 | i.operands + 1); | |
4188 | return NULL; | |
4189 | } | |
d02603dc | 4190 | token_start = l; /* After white space. */ |
29b0f896 AM |
4191 | paren_not_balanced = 0; |
4192 | while (paren_not_balanced || *l != ',') | |
4193 | { | |
4194 | if (*l == END_OF_INSN) | |
4195 | { | |
4196 | if (paren_not_balanced) | |
4197 | { | |
4198 | if (!intel_syntax) | |
4199 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4200 | i.operands + 1); | |
4201 | else | |
4202 | as_bad (_("unbalanced brackets in operand %d."), | |
4203 | i.operands + 1); | |
4204 | return NULL; | |
4205 | } | |
4206 | else | |
4207 | break; /* we are done */ | |
4208 | } | |
d02603dc | 4209 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4210 | { |
4211 | as_bad (_("invalid character %s in operand %d"), | |
4212 | output_invalid (*l), | |
4213 | i.operands + 1); | |
4214 | return NULL; | |
4215 | } | |
4216 | if (!intel_syntax) | |
4217 | { | |
4218 | if (*l == '(') | |
4219 | ++paren_not_balanced; | |
4220 | if (*l == ')') | |
4221 | --paren_not_balanced; | |
4222 | } | |
4223 | else | |
4224 | { | |
4225 | if (*l == '[') | |
4226 | ++paren_not_balanced; | |
4227 | if (*l == ']') | |
4228 | --paren_not_balanced; | |
4229 | } | |
4230 | l++; | |
4231 | } | |
4232 | if (l != token_start) | |
4233 | { /* Yes, we've read in another operand. */ | |
4234 | unsigned int operand_ok; | |
4235 | this_operand = i.operands++; | |
4236 | if (i.operands > MAX_OPERANDS) | |
4237 | { | |
4238 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
4239 | MAX_OPERANDS); | |
4240 | return NULL; | |
4241 | } | |
9d46ce34 | 4242 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
4243 | /* Now parse operand adding info to 'i' as we go along. */ |
4244 | END_STRING_AND_SAVE (l); | |
4245 | ||
4246 | if (intel_syntax) | |
4247 | operand_ok = | |
4248 | i386_intel_operand (token_start, | |
4249 | intel_float_operand (mnemonic)); | |
4250 | else | |
a7619375 | 4251 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
4252 | |
4253 | RESTORE_END_STRING (l); | |
4254 | if (!operand_ok) | |
4255 | return NULL; | |
4256 | } | |
4257 | else | |
4258 | { | |
4259 | if (expecting_operand) | |
4260 | { | |
4261 | expecting_operand_after_comma: | |
4262 | as_bad (_("expecting operand after ','; got nothing")); | |
4263 | return NULL; | |
4264 | } | |
4265 | if (*l == ',') | |
4266 | { | |
4267 | as_bad (_("expecting operand before ','; got nothing")); | |
4268 | return NULL; | |
4269 | } | |
4270 | } | |
7f3f1ea2 | 4271 | |
29b0f896 AM |
4272 | /* Now *l must be either ',' or END_OF_INSN. */ |
4273 | if (*l == ',') | |
4274 | { | |
4275 | if (*++l == END_OF_INSN) | |
4276 | { | |
4277 | /* Just skip it, if it's \n complain. */ | |
4278 | goto expecting_operand_after_comma; | |
4279 | } | |
4280 | expecting_operand = 1; | |
4281 | } | |
4282 | } | |
4283 | return l; | |
4284 | } | |
7f3f1ea2 | 4285 | |
050dfa73 | 4286 | static void |
4d456e3d | 4287 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
4288 | { |
4289 | union i386_op temp_op; | |
40fb9820 | 4290 | i386_operand_type temp_type; |
050dfa73 | 4291 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 4292 | |
050dfa73 MM |
4293 | temp_type = i.types[xchg2]; |
4294 | i.types[xchg2] = i.types[xchg1]; | |
4295 | i.types[xchg1] = temp_type; | |
4296 | temp_op = i.op[xchg2]; | |
4297 | i.op[xchg2] = i.op[xchg1]; | |
4298 | i.op[xchg1] = temp_op; | |
4299 | temp_reloc = i.reloc[xchg2]; | |
4300 | i.reloc[xchg2] = i.reloc[xchg1]; | |
4301 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
4302 | |
4303 | if (i.mask) | |
4304 | { | |
4305 | if (i.mask->operand == xchg1) | |
4306 | i.mask->operand = xchg2; | |
4307 | else if (i.mask->operand == xchg2) | |
4308 | i.mask->operand = xchg1; | |
4309 | } | |
4310 | if (i.broadcast) | |
4311 | { | |
4312 | if (i.broadcast->operand == xchg1) | |
4313 | i.broadcast->operand = xchg2; | |
4314 | else if (i.broadcast->operand == xchg2) | |
4315 | i.broadcast->operand = xchg1; | |
4316 | } | |
4317 | if (i.rounding) | |
4318 | { | |
4319 | if (i.rounding->operand == xchg1) | |
4320 | i.rounding->operand = xchg2; | |
4321 | else if (i.rounding->operand == xchg2) | |
4322 | i.rounding->operand = xchg1; | |
4323 | } | |
050dfa73 MM |
4324 | } |
4325 | ||
29b0f896 | 4326 | static void |
e3bb37b5 | 4327 | swap_operands (void) |
29b0f896 | 4328 | { |
b7c61d9a | 4329 | switch (i.operands) |
050dfa73 | 4330 | { |
c0f3af97 | 4331 | case 5: |
b7c61d9a | 4332 | case 4: |
4d456e3d | 4333 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 4334 | /* Fall through. */ |
b7c61d9a L |
4335 | case 3: |
4336 | case 2: | |
4d456e3d | 4337 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
4338 | break; |
4339 | default: | |
4340 | abort (); | |
29b0f896 | 4341 | } |
29b0f896 AM |
4342 | |
4343 | if (i.mem_operands == 2) | |
4344 | { | |
4345 | const seg_entry *temp_seg; | |
4346 | temp_seg = i.seg[0]; | |
4347 | i.seg[0] = i.seg[1]; | |
4348 | i.seg[1] = temp_seg; | |
4349 | } | |
4350 | } | |
252b5132 | 4351 | |
29b0f896 AM |
4352 | /* Try to ensure constant immediates are represented in the smallest |
4353 | opcode possible. */ | |
4354 | static void | |
e3bb37b5 | 4355 | optimize_imm (void) |
29b0f896 AM |
4356 | { |
4357 | char guess_suffix = 0; | |
4358 | int op; | |
252b5132 | 4359 | |
29b0f896 AM |
4360 | if (i.suffix) |
4361 | guess_suffix = i.suffix; | |
4362 | else if (i.reg_operands) | |
4363 | { | |
4364 | /* Figure out a suffix from the last register operand specified. | |
4365 | We can't do this properly yet, ie. excluding InOutPortReg, | |
4366 | but the following works for instructions with immediates. | |
4367 | In any case, we can't set i.suffix yet. */ | |
4368 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 4369 | if (i.types[op].bitfield.reg8) |
7ab9ffdd | 4370 | { |
40fb9820 L |
4371 | guess_suffix = BYTE_MNEM_SUFFIX; |
4372 | break; | |
4373 | } | |
4374 | else if (i.types[op].bitfield.reg16) | |
252b5132 | 4375 | { |
40fb9820 L |
4376 | guess_suffix = WORD_MNEM_SUFFIX; |
4377 | break; | |
4378 | } | |
4379 | else if (i.types[op].bitfield.reg32) | |
4380 | { | |
4381 | guess_suffix = LONG_MNEM_SUFFIX; | |
4382 | break; | |
4383 | } | |
4384 | else if (i.types[op].bitfield.reg64) | |
4385 | { | |
4386 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 4387 | break; |
252b5132 | 4388 | } |
29b0f896 AM |
4389 | } |
4390 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
4391 | guess_suffix = WORD_MNEM_SUFFIX; | |
4392 | ||
4393 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 4394 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
4395 | { |
4396 | switch (i.op[op].imms->X_op) | |
252b5132 | 4397 | { |
29b0f896 AM |
4398 | case O_constant: |
4399 | /* If a suffix is given, this operand may be shortened. */ | |
4400 | switch (guess_suffix) | |
252b5132 | 4401 | { |
29b0f896 | 4402 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
4403 | i.types[op].bitfield.imm32 = 1; |
4404 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4405 | break; |
4406 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
4407 | i.types[op].bitfield.imm16 = 1; |
4408 | i.types[op].bitfield.imm32 = 1; | |
4409 | i.types[op].bitfield.imm32s = 1; | |
4410 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4411 | break; |
4412 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
4413 | i.types[op].bitfield.imm8 = 1; |
4414 | i.types[op].bitfield.imm8s = 1; | |
4415 | i.types[op].bitfield.imm16 = 1; | |
4416 | i.types[op].bitfield.imm32 = 1; | |
4417 | i.types[op].bitfield.imm32s = 1; | |
4418 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 4419 | break; |
252b5132 | 4420 | } |
252b5132 | 4421 | |
29b0f896 AM |
4422 | /* If this operand is at most 16 bits, convert it |
4423 | to a signed 16 bit number before trying to see | |
4424 | whether it will fit in an even smaller size. | |
4425 | This allows a 16-bit operand such as $0xffe0 to | |
4426 | be recognised as within Imm8S range. */ | |
40fb9820 | 4427 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 4428 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 4429 | { |
29b0f896 AM |
4430 | i.op[op].imms->X_add_number = |
4431 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
4432 | } | |
a28def75 L |
4433 | #ifdef BFD64 |
4434 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 4435 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
4436 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
4437 | == 0)) | |
4438 | { | |
4439 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
4440 | ^ ((offsetT) 1 << 31)) | |
4441 | - ((offsetT) 1 << 31)); | |
4442 | } | |
a28def75 | 4443 | #endif |
40fb9820 | 4444 | i.types[op] |
c6fb90c8 L |
4445 | = operand_type_or (i.types[op], |
4446 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 4447 | |
29b0f896 AM |
4448 | /* We must avoid matching of Imm32 templates when 64bit |
4449 | only immediate is available. */ | |
4450 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 4451 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 4452 | break; |
252b5132 | 4453 | |
29b0f896 AM |
4454 | case O_absent: |
4455 | case O_register: | |
4456 | abort (); | |
4457 | ||
4458 | /* Symbols and expressions. */ | |
4459 | default: | |
9cd96992 JB |
4460 | /* Convert symbolic operand to proper sizes for matching, but don't |
4461 | prevent matching a set of insns that only supports sizes other | |
4462 | than those matching the insn suffix. */ | |
4463 | { | |
40fb9820 | 4464 | i386_operand_type mask, allowed; |
d3ce72d0 | 4465 | const insn_template *t; |
9cd96992 | 4466 | |
0dfbf9d7 L |
4467 | operand_type_set (&mask, 0); |
4468 | operand_type_set (&allowed, 0); | |
40fb9820 | 4469 | |
4eed87de AM |
4470 | for (t = current_templates->start; |
4471 | t < current_templates->end; | |
4472 | ++t) | |
c6fb90c8 L |
4473 | allowed = operand_type_or (allowed, |
4474 | t->operand_types[op]); | |
9cd96992 JB |
4475 | switch (guess_suffix) |
4476 | { | |
4477 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
4478 | mask.bitfield.imm64 = 1; |
4479 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
4480 | break; |
4481 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 4482 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
4483 | break; |
4484 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 4485 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
4486 | break; |
4487 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 4488 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
4489 | break; |
4490 | default: | |
9cd96992 JB |
4491 | break; |
4492 | } | |
c6fb90c8 | 4493 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 4494 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 4495 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 4496 | } |
29b0f896 | 4497 | break; |
252b5132 | 4498 | } |
29b0f896 AM |
4499 | } |
4500 | } | |
47926f60 | 4501 | |
29b0f896 AM |
4502 | /* Try to use the smallest displacement type too. */ |
4503 | static void | |
e3bb37b5 | 4504 | optimize_disp (void) |
29b0f896 AM |
4505 | { |
4506 | int op; | |
3e73aa7c | 4507 | |
29b0f896 | 4508 | for (op = i.operands; --op >= 0;) |
40fb9820 | 4509 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 4510 | { |
b300c311 | 4511 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 4512 | { |
91d6fa6a | 4513 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 4514 | |
40fb9820 | 4515 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 4516 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
4517 | { |
4518 | /* If this operand is at most 16 bits, convert | |
4519 | to a signed 16 bit number and don't use 64bit | |
4520 | displacement. */ | |
91d6fa6a | 4521 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 4522 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 4523 | } |
a28def75 L |
4524 | #ifdef BFD64 |
4525 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 4526 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 4527 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
4528 | { |
4529 | /* If this operand is at most 32 bits, convert | |
4530 | to a signed 32 bit number and don't use 64bit | |
4531 | displacement. */ | |
91d6fa6a NC |
4532 | op_disp &= (((offsetT) 2 << 31) - 1); |
4533 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 4534 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 4535 | } |
a28def75 | 4536 | #endif |
91d6fa6a | 4537 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 4538 | { |
40fb9820 L |
4539 | i.types[op].bitfield.disp8 = 0; |
4540 | i.types[op].bitfield.disp16 = 0; | |
4541 | i.types[op].bitfield.disp32 = 0; | |
4542 | i.types[op].bitfield.disp32s = 0; | |
4543 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
4544 | i.op[op].disps = 0; |
4545 | i.disp_operands--; | |
4546 | } | |
4547 | else if (flag_code == CODE_64BIT) | |
4548 | { | |
91d6fa6a | 4549 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 4550 | { |
40fb9820 L |
4551 | i.types[op].bitfield.disp64 = 0; |
4552 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 4553 | } |
0e1147d9 | 4554 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 4555 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 4556 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 4557 | } |
40fb9820 L |
4558 | if ((i.types[op].bitfield.disp32 |
4559 | || i.types[op].bitfield.disp32s | |
4560 | || i.types[op].bitfield.disp16) | |
91d6fa6a | 4561 | && fits_in_signed_byte (op_disp)) |
40fb9820 | 4562 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 4563 | } |
67a4f2b7 AO |
4564 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
4565 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
4566 | { | |
4567 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
4568 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
4569 | i.types[op].bitfield.disp8 = 0; |
4570 | i.types[op].bitfield.disp16 = 0; | |
4571 | i.types[op].bitfield.disp32 = 0; | |
4572 | i.types[op].bitfield.disp32s = 0; | |
4573 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
4574 | } |
4575 | else | |
b300c311 | 4576 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 4577 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 4578 | } |
29b0f896 AM |
4579 | } |
4580 | ||
6c30d220 L |
4581 | /* Check if operands are valid for the instruction. */ |
4582 | ||
4583 | static int | |
4584 | check_VecOperands (const insn_template *t) | |
4585 | { | |
43234a1e L |
4586 | unsigned int op; |
4587 | ||
6c30d220 L |
4588 | /* Without VSIB byte, we can't have a vector register for index. */ |
4589 | if (!t->opcode_modifier.vecsib | |
4590 | && i.index_reg | |
4591 | && (i.index_reg->reg_type.bitfield.regxmm | |
43234a1e L |
4592 | || i.index_reg->reg_type.bitfield.regymm |
4593 | || i.index_reg->reg_type.bitfield.regzmm)) | |
6c30d220 L |
4594 | { |
4595 | i.error = unsupported_vector_index_register; | |
4596 | return 1; | |
4597 | } | |
4598 | ||
ad8ecc81 MZ |
4599 | /* Check if default mask is allowed. */ |
4600 | if (t->opcode_modifier.nodefmask | |
4601 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
4602 | { | |
4603 | i.error = no_default_mask; | |
4604 | return 1; | |
4605 | } | |
4606 | ||
7bab8ab5 JB |
4607 | /* For VSIB byte, we need a vector register for index, and all vector |
4608 | registers must be distinct. */ | |
4609 | if (t->opcode_modifier.vecsib) | |
4610 | { | |
4611 | if (!i.index_reg | |
6c30d220 L |
4612 | || !((t->opcode_modifier.vecsib == VecSIB128 |
4613 | && i.index_reg->reg_type.bitfield.regxmm) | |
4614 | || (t->opcode_modifier.vecsib == VecSIB256 | |
43234a1e L |
4615 | && i.index_reg->reg_type.bitfield.regymm) |
4616 | || (t->opcode_modifier.vecsib == VecSIB512 | |
4617 | && i.index_reg->reg_type.bitfield.regzmm))) | |
7bab8ab5 JB |
4618 | { |
4619 | i.error = invalid_vsib_address; | |
4620 | return 1; | |
4621 | } | |
4622 | ||
43234a1e L |
4623 | gas_assert (i.reg_operands == 2 || i.mask); |
4624 | if (i.reg_operands == 2 && !i.mask) | |
4625 | { | |
4626 | gas_assert (i.types[0].bitfield.regxmm | |
7c84a0ca | 4627 | || i.types[0].bitfield.regymm); |
43234a1e | 4628 | gas_assert (i.types[2].bitfield.regxmm |
7c84a0ca | 4629 | || i.types[2].bitfield.regymm); |
43234a1e L |
4630 | if (operand_check == check_none) |
4631 | return 0; | |
4632 | if (register_number (i.op[0].regs) | |
4633 | != register_number (i.index_reg) | |
4634 | && register_number (i.op[2].regs) | |
4635 | != register_number (i.index_reg) | |
4636 | && register_number (i.op[0].regs) | |
4637 | != register_number (i.op[2].regs)) | |
4638 | return 0; | |
4639 | if (operand_check == check_error) | |
4640 | { | |
4641 | i.error = invalid_vector_register_set; | |
4642 | return 1; | |
4643 | } | |
4644 | as_warn (_("mask, index, and destination registers should be distinct")); | |
4645 | } | |
8444f82a MZ |
4646 | else if (i.reg_operands == 1 && i.mask) |
4647 | { | |
4648 | if ((i.types[1].bitfield.regymm | |
4649 | || i.types[1].bitfield.regzmm) | |
4650 | && (register_number (i.op[1].regs) | |
4651 | == register_number (i.index_reg))) | |
4652 | { | |
4653 | if (operand_check == check_error) | |
4654 | { | |
4655 | i.error = invalid_vector_register_set; | |
4656 | return 1; | |
4657 | } | |
4658 | if (operand_check != check_none) | |
4659 | as_warn (_("index and destination registers should be distinct")); | |
4660 | } | |
4661 | } | |
43234a1e | 4662 | } |
7bab8ab5 | 4663 | |
43234a1e L |
4664 | /* Check if broadcast is supported by the instruction and is applied |
4665 | to the memory operand. */ | |
4666 | if (i.broadcast) | |
4667 | { | |
4668 | int broadcasted_opnd_size; | |
4669 | ||
4670 | /* Check if specified broadcast is supported in this instruction, | |
4671 | and it's applied to memory operand of DWORD or QWORD type, | |
4672 | depending on VecESize. */ | |
4673 | if (i.broadcast->type != t->opcode_modifier.broadcast | |
4674 | || !i.types[i.broadcast->operand].bitfield.mem | |
4675 | || (t->opcode_modifier.vecesize == 0 | |
4676 | && !i.types[i.broadcast->operand].bitfield.dword | |
4677 | && !i.types[i.broadcast->operand].bitfield.unspecified) | |
4678 | || (t->opcode_modifier.vecesize == 1 | |
4679 | && !i.types[i.broadcast->operand].bitfield.qword | |
4680 | && !i.types[i.broadcast->operand].bitfield.unspecified)) | |
4681 | goto bad_broadcast; | |
4682 | ||
4683 | broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32; | |
4684 | if (i.broadcast->type == BROADCAST_1TO16) | |
4685 | broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */ | |
4686 | else if (i.broadcast->type == BROADCAST_1TO8) | |
4687 | broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */ | |
b28d1bda IT |
4688 | else if (i.broadcast->type == BROADCAST_1TO4) |
4689 | broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */ | |
4690 | else if (i.broadcast->type == BROADCAST_1TO2) | |
4691 | broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */ | |
43234a1e L |
4692 | else |
4693 | goto bad_broadcast; | |
4694 | ||
4695 | if ((broadcasted_opnd_size == 256 | |
4696 | && !t->operand_types[i.broadcast->operand].bitfield.ymmword) | |
4697 | || (broadcasted_opnd_size == 512 | |
4698 | && !t->operand_types[i.broadcast->operand].bitfield.zmmword)) | |
4699 | { | |
4700 | bad_broadcast: | |
4701 | i.error = unsupported_broadcast; | |
4702 | return 1; | |
4703 | } | |
4704 | } | |
4705 | /* If broadcast is supported in this instruction, we need to check if | |
4706 | operand of one-element size isn't specified without broadcast. */ | |
4707 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
4708 | { | |
4709 | /* Find memory operand. */ | |
4710 | for (op = 0; op < i.operands; op++) | |
4711 | if (operand_type_check (i.types[op], anymem)) | |
4712 | break; | |
4713 | gas_assert (op < i.operands); | |
4714 | /* Check size of the memory operand. */ | |
4715 | if ((t->opcode_modifier.vecesize == 0 | |
4716 | && i.types[op].bitfield.dword) | |
4717 | || (t->opcode_modifier.vecesize == 1 | |
4718 | && i.types[op].bitfield.qword)) | |
4719 | { | |
4720 | i.error = broadcast_needed; | |
4721 | return 1; | |
4722 | } | |
4723 | } | |
4724 | ||
4725 | /* Check if requested masking is supported. */ | |
4726 | if (i.mask | |
4727 | && (!t->opcode_modifier.masking | |
4728 | || (i.mask->zeroing | |
4729 | && t->opcode_modifier.masking == MERGING_MASKING))) | |
4730 | { | |
4731 | i.error = unsupported_masking; | |
4732 | return 1; | |
4733 | } | |
4734 | ||
4735 | /* Check if masking is applied to dest operand. */ | |
4736 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
4737 | { | |
4738 | i.error = mask_not_on_destination; | |
4739 | return 1; | |
4740 | } | |
4741 | ||
43234a1e L |
4742 | /* Check RC/SAE. */ |
4743 | if (i.rounding) | |
4744 | { | |
4745 | if ((i.rounding->type != saeonly | |
4746 | && !t->opcode_modifier.staticrounding) | |
4747 | || (i.rounding->type == saeonly | |
4748 | && (t->opcode_modifier.staticrounding | |
4749 | || !t->opcode_modifier.sae))) | |
4750 | { | |
4751 | i.error = unsupported_rc_sae; | |
4752 | return 1; | |
4753 | } | |
4754 | /* If the instruction has several immediate operands and one of | |
4755 | them is rounding, the rounding operand should be the last | |
4756 | immediate operand. */ | |
4757 | if (i.imm_operands > 1 | |
4758 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 4759 | { |
43234a1e | 4760 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
4761 | return 1; |
4762 | } | |
6c30d220 L |
4763 | } |
4764 | ||
43234a1e L |
4765 | /* Check vector Disp8 operand. */ |
4766 | if (t->opcode_modifier.disp8memshift) | |
4767 | { | |
4768 | if (i.broadcast) | |
4769 | i.memshift = t->opcode_modifier.vecesize ? 3 : 2; | |
4770 | else | |
4771 | i.memshift = t->opcode_modifier.disp8memshift; | |
4772 | ||
4773 | for (op = 0; op < i.operands; op++) | |
4774 | if (operand_type_check (i.types[op], disp) | |
4775 | && i.op[op].disps->X_op == O_constant) | |
4776 | { | |
4777 | offsetT value = i.op[op].disps->X_add_number; | |
5be33403 L |
4778 | int vec_disp8_ok |
4779 | = (i.disp_encoding != disp_encoding_32bit | |
4780 | && fits_in_vec_disp8 (value)); | |
43234a1e L |
4781 | if (t->operand_types [op].bitfield.vec_disp8) |
4782 | { | |
4783 | if (vec_disp8_ok) | |
4784 | i.types[op].bitfield.vec_disp8 = 1; | |
4785 | else | |
4786 | { | |
4787 | /* Vector insn can only have Vec_Disp8/Disp32 in | |
4788 | 32/64bit modes, and Vec_Disp8/Disp16 in 16bit | |
4789 | mode. */ | |
4790 | i.types[op].bitfield.disp8 = 0; | |
4791 | if (flag_code != CODE_16BIT) | |
4792 | i.types[op].bitfield.disp16 = 0; | |
4793 | } | |
4794 | } | |
4795 | else if (flag_code != CODE_16BIT) | |
4796 | { | |
4797 | /* One form of this instruction supports vector Disp8. | |
4798 | Try vector Disp8 if we need to use Disp32. */ | |
4799 | if (vec_disp8_ok && !fits_in_signed_byte (value)) | |
4800 | { | |
4801 | i.error = try_vector_disp8; | |
4802 | return 1; | |
4803 | } | |
4804 | } | |
4805 | } | |
4806 | } | |
4807 | else | |
4808 | i.memshift = -1; | |
4809 | ||
6c30d220 L |
4810 | return 0; |
4811 | } | |
4812 | ||
43f3e2ee | 4813 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
4814 | operand types. */ |
4815 | ||
4816 | static int | |
4817 | VEX_check_operands (const insn_template *t) | |
4818 | { | |
86fa6981 | 4819 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 4820 | { |
86fa6981 L |
4821 | /* This instruction must be encoded with EVEX prefix. */ |
4822 | if (!t->opcode_modifier.evex) | |
4823 | { | |
4824 | i.error = unsupported; | |
4825 | return 1; | |
4826 | } | |
4827 | return 0; | |
43234a1e L |
4828 | } |
4829 | ||
a683cc34 | 4830 | if (!t->opcode_modifier.vex) |
86fa6981 L |
4831 | { |
4832 | /* This instruction template doesn't have VEX prefix. */ | |
4833 | if (i.vec_encoding != vex_encoding_default) | |
4834 | { | |
4835 | i.error = unsupported; | |
4836 | return 1; | |
4837 | } | |
4838 | return 0; | |
4839 | } | |
a683cc34 SP |
4840 | |
4841 | /* Only check VEX_Imm4, which must be the first operand. */ | |
4842 | if (t->operand_types[0].bitfield.vec_imm4) | |
4843 | { | |
4844 | if (i.op[0].imms->X_op != O_constant | |
4845 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 4846 | { |
a65babc9 | 4847 | i.error = bad_imm4; |
891edac4 L |
4848 | return 1; |
4849 | } | |
a683cc34 SP |
4850 | |
4851 | /* Turn off Imm8 so that update_imm won't complain. */ | |
4852 | i.types[0] = vec_imm4; | |
4853 | } | |
4854 | ||
4855 | return 0; | |
4856 | } | |
4857 | ||
d3ce72d0 | 4858 | static const insn_template * |
83b16ac6 | 4859 | match_template (char mnem_suffix) |
29b0f896 AM |
4860 | { |
4861 | /* Points to template once we've found it. */ | |
d3ce72d0 | 4862 | const insn_template *t; |
40fb9820 | 4863 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 4864 | i386_operand_type overlap4; |
29b0f896 | 4865 | unsigned int found_reverse_match; |
83b16ac6 | 4866 | i386_opcode_modifier suffix_check, mnemsuf_check; |
40fb9820 | 4867 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 4868 | int addr_prefix_disp; |
a5c311ca | 4869 | unsigned int j; |
3629bb00 | 4870 | unsigned int found_cpu_match; |
45664ddb | 4871 | unsigned int check_register; |
5614d22c | 4872 | enum i386_error specific_error = 0; |
29b0f896 | 4873 | |
c0f3af97 L |
4874 | #if MAX_OPERANDS != 5 |
4875 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
4876 | #endif |
4877 | ||
29b0f896 | 4878 | found_reverse_match = 0; |
539e75ad | 4879 | addr_prefix_disp = -1; |
40fb9820 L |
4880 | |
4881 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
4882 | if (i.suffix == BYTE_MNEM_SUFFIX) | |
4883 | suffix_check.no_bsuf = 1; | |
4884 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4885 | suffix_check.no_wsuf = 1; | |
4886 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
4887 | suffix_check.no_ssuf = 1; | |
4888 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
4889 | suffix_check.no_lsuf = 1; | |
4890 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4891 | suffix_check.no_qsuf = 1; | |
4892 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 4893 | suffix_check.no_ldsuf = 1; |
29b0f896 | 4894 | |
83b16ac6 JB |
4895 | memset (&mnemsuf_check, 0, sizeof (mnemsuf_check)); |
4896 | if (intel_syntax) | |
4897 | { | |
4898 | switch (mnem_suffix) | |
4899 | { | |
4900 | case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break; | |
4901 | case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break; | |
4902 | case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break; | |
4903 | case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break; | |
4904 | case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break; | |
4905 | } | |
4906 | } | |
4907 | ||
01559ecc L |
4908 | /* Must have right number of operands. */ |
4909 | i.error = number_of_operands_mismatch; | |
4910 | ||
45aa61fe | 4911 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 4912 | { |
539e75ad L |
4913 | addr_prefix_disp = -1; |
4914 | ||
29b0f896 AM |
4915 | if (i.operands != t->operands) |
4916 | continue; | |
4917 | ||
50aecf8c | 4918 | /* Check processor support. */ |
a65babc9 | 4919 | i.error = unsupported; |
c0f3af97 L |
4920 | found_cpu_match = (cpu_flags_match (t) |
4921 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
4922 | if (!found_cpu_match) |
4923 | continue; | |
4924 | ||
e1d4d893 | 4925 | /* Check old gcc support. */ |
a65babc9 | 4926 | i.error = old_gcc_only; |
e1d4d893 L |
4927 | if (!old_gcc && t->opcode_modifier.oldgcc) |
4928 | continue; | |
4929 | ||
4930 | /* Check AT&T mnemonic. */ | |
a65babc9 | 4931 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 4932 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
4933 | continue; |
4934 | ||
e92bae62 | 4935 | /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ |
a65babc9 | 4936 | i.error = unsupported_syntax; |
5c07affc | 4937 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
e92bae62 L |
4938 | || (!intel_syntax && t->opcode_modifier.intelsyntax) |
4939 | || (intel64 && t->opcode_modifier.amd64) | |
4940 | || (!intel64 && t->opcode_modifier.intel64)) | |
1efbbeb4 L |
4941 | continue; |
4942 | ||
20592a94 | 4943 | /* Check the suffix, except for some instructions in intel mode. */ |
a65babc9 | 4944 | i.error = invalid_instruction_suffix; |
567e4e96 L |
4945 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
4946 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
4947 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
4948 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
4949 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
4950 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
4951 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 | 4952 | continue; |
83b16ac6 JB |
4953 | /* In Intel mode all mnemonic suffixes must be explicitly allowed. */ |
4954 | if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf) | |
4955 | || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf) | |
4956 | || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf) | |
4957 | || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf) | |
4958 | || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf) | |
4959 | || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf)) | |
4960 | continue; | |
29b0f896 | 4961 | |
5c07affc | 4962 | if (!operand_size_match (t)) |
7d5e4556 | 4963 | continue; |
539e75ad | 4964 | |
5c07affc L |
4965 | for (j = 0; j < MAX_OPERANDS; j++) |
4966 | operand_types[j] = t->operand_types[j]; | |
4967 | ||
45aa61fe AM |
4968 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
4969 | if (i.suffix == QWORD_MNEM_SUFFIX | |
4970 | && flag_code != CODE_64BIT | |
4971 | && (intel_syntax | |
40fb9820 | 4972 | ? (!t->opcode_modifier.ignoresize |
45aa61fe AM |
4973 | && !intel_float_operand (t->name)) |
4974 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 4975 | && ((!operand_types[0].bitfield.regmmx |
c0f3af97 | 4976 | && !operand_types[0].bitfield.regxmm |
43234a1e L |
4977 | && !operand_types[0].bitfield.regymm |
4978 | && !operand_types[0].bitfield.regzmm) | |
40fb9820 | 4979 | || (!operand_types[t->operands > 1].bitfield.regmmx |
ac4eb736 AM |
4980 | && operand_types[t->operands > 1].bitfield.regxmm |
4981 | && operand_types[t->operands > 1].bitfield.regymm | |
4982 | && operand_types[t->operands > 1].bitfield.regzmm)) | |
45aa61fe AM |
4983 | && (t->base_opcode != 0x0fc7 |
4984 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
4985 | continue; | |
4986 | ||
192dc9c6 JB |
4987 | /* In general, don't allow 32-bit operands on pre-386. */ |
4988 | else if (i.suffix == LONG_MNEM_SUFFIX | |
4989 | && !cpu_arch_flags.bitfield.cpui386 | |
4990 | && (intel_syntax | |
4991 | ? (!t->opcode_modifier.ignoresize | |
4992 | && !intel_float_operand (t->name)) | |
4993 | : intel_float_operand (t->name) != 2) | |
4994 | && ((!operand_types[0].bitfield.regmmx | |
4995 | && !operand_types[0].bitfield.regxmm) | |
4996 | || (!operand_types[t->operands > 1].bitfield.regmmx | |
ac4eb736 | 4997 | && operand_types[t->operands > 1].bitfield.regxmm))) |
192dc9c6 JB |
4998 | continue; |
4999 | ||
29b0f896 | 5000 | /* Do not verify operands when there are none. */ |
50aecf8c | 5001 | else |
29b0f896 | 5002 | { |
c6fb90c8 | 5003 | if (!t->operands) |
2dbab7d5 L |
5004 | /* We've found a match; break out of loop. */ |
5005 | break; | |
29b0f896 | 5006 | } |
252b5132 | 5007 | |
539e75ad L |
5008 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
5009 | into Disp32/Disp16/Disp32 operand. */ | |
5010 | if (i.prefix[ADDR_PREFIX] != 0) | |
5011 | { | |
40fb9820 | 5012 | /* There should be only one Disp operand. */ |
539e75ad L |
5013 | switch (flag_code) |
5014 | { | |
5015 | case CODE_16BIT: | |
40fb9820 L |
5016 | for (j = 0; j < MAX_OPERANDS; j++) |
5017 | { | |
5018 | if (operand_types[j].bitfield.disp16) | |
5019 | { | |
5020 | addr_prefix_disp = j; | |
5021 | operand_types[j].bitfield.disp32 = 1; | |
5022 | operand_types[j].bitfield.disp16 = 0; | |
5023 | break; | |
5024 | } | |
5025 | } | |
539e75ad L |
5026 | break; |
5027 | case CODE_32BIT: | |
40fb9820 L |
5028 | for (j = 0; j < MAX_OPERANDS; j++) |
5029 | { | |
5030 | if (operand_types[j].bitfield.disp32) | |
5031 | { | |
5032 | addr_prefix_disp = j; | |
5033 | operand_types[j].bitfield.disp32 = 0; | |
5034 | operand_types[j].bitfield.disp16 = 1; | |
5035 | break; | |
5036 | } | |
5037 | } | |
539e75ad L |
5038 | break; |
5039 | case CODE_64BIT: | |
40fb9820 L |
5040 | for (j = 0; j < MAX_OPERANDS; j++) |
5041 | { | |
5042 | if (operand_types[j].bitfield.disp64) | |
5043 | { | |
5044 | addr_prefix_disp = j; | |
5045 | operand_types[j].bitfield.disp64 = 0; | |
5046 | operand_types[j].bitfield.disp32 = 1; | |
5047 | break; | |
5048 | } | |
5049 | } | |
539e75ad L |
5050 | break; |
5051 | } | |
539e75ad L |
5052 | } |
5053 | ||
02a86693 L |
5054 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
5055 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
5056 | continue; | |
5057 | ||
56ffb741 L |
5058 | /* We check register size if needed. */ |
5059 | check_register = t->opcode_modifier.checkregsize; | |
c6fb90c8 | 5060 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
5061 | switch (t->operands) |
5062 | { | |
5063 | case 1: | |
40fb9820 | 5064 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
5065 | continue; |
5066 | break; | |
5067 | case 2: | |
33eaf5de | 5068 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
5069 | only in 32bit mode and we can use opcode 0x90. In 64bit |
5070 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
5071 | zero-extend %eax to %rax. */ | |
5072 | if (flag_code == CODE_64BIT | |
5073 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
5074 | && operand_type_equal (&i.types [0], &acc32) |
5075 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 5076 | continue; |
86fa6981 L |
5077 | /* If we want store form, we reverse direction of operands. */ |
5078 | if (i.dir_encoding == dir_encoding_store | |
5079 | && t->opcode_modifier.d) | |
5080 | goto check_reverse; | |
1a0670f3 | 5081 | /* Fall through. */ |
b6169b20 | 5082 | |
29b0f896 | 5083 | case 3: |
86fa6981 L |
5084 | /* If we want store form, we skip the current load. */ |
5085 | if (i.dir_encoding == dir_encoding_store | |
5086 | && i.mem_operands == 0 | |
5087 | && t->opcode_modifier.load) | |
fa99fab2 | 5088 | continue; |
1a0670f3 | 5089 | /* Fall through. */ |
f48ff2ae | 5090 | case 4: |
c0f3af97 | 5091 | case 5: |
c6fb90c8 | 5092 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
5093 | if (!operand_type_match (overlap0, i.types[0]) |
5094 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
5095 | || (check_register |
5096 | && !operand_type_register_match (overlap0, i.types[0], | |
40fb9820 L |
5097 | operand_types[0], |
5098 | overlap1, i.types[1], | |
5099 | operand_types[1]))) | |
29b0f896 AM |
5100 | { |
5101 | /* Check if other direction is valid ... */ | |
40fb9820 | 5102 | if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
29b0f896 AM |
5103 | continue; |
5104 | ||
b6169b20 | 5105 | check_reverse: |
29b0f896 | 5106 | /* Try reversing direction of operands. */ |
c6fb90c8 L |
5107 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
5108 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
5109 | if (!operand_type_match (overlap0, i.types[0]) |
5110 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
5111 | || (check_register |
5112 | && !operand_type_register_match (overlap0, | |
5113 | i.types[0], | |
5114 | operand_types[1], | |
5115 | overlap1, | |
5116 | i.types[1], | |
5117 | operand_types[0]))) | |
29b0f896 AM |
5118 | { |
5119 | /* Does not match either direction. */ | |
5120 | continue; | |
5121 | } | |
5122 | /* found_reverse_match holds which of D or FloatDR | |
5123 | we've found. */ | |
40fb9820 | 5124 | if (t->opcode_modifier.d) |
8a2ed489 | 5125 | found_reverse_match = Opcode_D; |
40fb9820 | 5126 | else if (t->opcode_modifier.floatd) |
8a2ed489 L |
5127 | found_reverse_match = Opcode_FloatD; |
5128 | else | |
5129 | found_reverse_match = 0; | |
40fb9820 | 5130 | if (t->opcode_modifier.floatr) |
8a2ed489 | 5131 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 5132 | } |
f48ff2ae | 5133 | else |
29b0f896 | 5134 | { |
f48ff2ae | 5135 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
5136 | switch (t->operands) |
5137 | { | |
c0f3af97 L |
5138 | case 5: |
5139 | overlap4 = operand_type_and (i.types[4], | |
5140 | operand_types[4]); | |
1a0670f3 | 5141 | /* Fall through. */ |
d1cbb4db | 5142 | case 4: |
c6fb90c8 L |
5143 | overlap3 = operand_type_and (i.types[3], |
5144 | operand_types[3]); | |
1a0670f3 | 5145 | /* Fall through. */ |
d1cbb4db | 5146 | case 3: |
c6fb90c8 L |
5147 | overlap2 = operand_type_and (i.types[2], |
5148 | operand_types[2]); | |
d1cbb4db L |
5149 | break; |
5150 | } | |
29b0f896 | 5151 | |
f48ff2ae L |
5152 | switch (t->operands) |
5153 | { | |
c0f3af97 L |
5154 | case 5: |
5155 | if (!operand_type_match (overlap4, i.types[4]) | |
5156 | || !operand_type_register_match (overlap3, | |
5157 | i.types[3], | |
5158 | operand_types[3], | |
5159 | overlap4, | |
5160 | i.types[4], | |
5161 | operand_types[4])) | |
5162 | continue; | |
1a0670f3 | 5163 | /* Fall through. */ |
f48ff2ae | 5164 | case 4: |
40fb9820 | 5165 | if (!operand_type_match (overlap3, i.types[3]) |
45664ddb L |
5166 | || (check_register |
5167 | && !operand_type_register_match (overlap2, | |
5168 | i.types[2], | |
5169 | operand_types[2], | |
5170 | overlap3, | |
5171 | i.types[3], | |
5172 | operand_types[3]))) | |
f48ff2ae | 5173 | continue; |
1a0670f3 | 5174 | /* Fall through. */ |
f48ff2ae L |
5175 | case 3: |
5176 | /* Here we make use of the fact that there are no | |
5177 | reverse match 3 operand instructions, and all 3 | |
5178 | operand instructions only need to be checked for | |
5179 | register consistency between operands 2 and 3. */ | |
40fb9820 | 5180 | if (!operand_type_match (overlap2, i.types[2]) |
45664ddb L |
5181 | || (check_register |
5182 | && !operand_type_register_match (overlap1, | |
5183 | i.types[1], | |
5184 | operand_types[1], | |
5185 | overlap2, | |
5186 | i.types[2], | |
5187 | operand_types[2]))) | |
f48ff2ae L |
5188 | continue; |
5189 | break; | |
5190 | } | |
29b0f896 | 5191 | } |
f48ff2ae | 5192 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
5193 | slip through to break. */ |
5194 | } | |
3629bb00 | 5195 | if (!found_cpu_match) |
29b0f896 AM |
5196 | { |
5197 | found_reverse_match = 0; | |
5198 | continue; | |
5199 | } | |
c0f3af97 | 5200 | |
5614d22c JB |
5201 | /* Check if vector and VEX operands are valid. */ |
5202 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
5203 | { | |
5204 | specific_error = i.error; | |
5205 | continue; | |
5206 | } | |
a683cc34 | 5207 | |
29b0f896 AM |
5208 | /* We've found a match; break out of loop. */ |
5209 | break; | |
5210 | } | |
5211 | ||
5212 | if (t == current_templates->end) | |
5213 | { | |
5214 | /* We found no match. */ | |
a65babc9 | 5215 | const char *err_msg; |
5614d22c | 5216 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
5217 | { |
5218 | default: | |
5219 | abort (); | |
86e026a4 | 5220 | case operand_size_mismatch: |
a65babc9 L |
5221 | err_msg = _("operand size mismatch"); |
5222 | break; | |
5223 | case operand_type_mismatch: | |
5224 | err_msg = _("operand type mismatch"); | |
5225 | break; | |
5226 | case register_type_mismatch: | |
5227 | err_msg = _("register type mismatch"); | |
5228 | break; | |
5229 | case number_of_operands_mismatch: | |
5230 | err_msg = _("number of operands mismatch"); | |
5231 | break; | |
5232 | case invalid_instruction_suffix: | |
5233 | err_msg = _("invalid instruction suffix"); | |
5234 | break; | |
5235 | case bad_imm4: | |
4a2608e3 | 5236 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 L |
5237 | break; |
5238 | case old_gcc_only: | |
5239 | err_msg = _("only supported with old gcc"); | |
5240 | break; | |
5241 | case unsupported_with_intel_mnemonic: | |
5242 | err_msg = _("unsupported with Intel mnemonic"); | |
5243 | break; | |
5244 | case unsupported_syntax: | |
5245 | err_msg = _("unsupported syntax"); | |
5246 | break; | |
5247 | case unsupported: | |
35262a23 | 5248 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
5249 | current_templates->start->name); |
5250 | return NULL; | |
6c30d220 L |
5251 | case invalid_vsib_address: |
5252 | err_msg = _("invalid VSIB address"); | |
5253 | break; | |
7bab8ab5 JB |
5254 | case invalid_vector_register_set: |
5255 | err_msg = _("mask, index, and destination registers must be distinct"); | |
5256 | break; | |
6c30d220 L |
5257 | case unsupported_vector_index_register: |
5258 | err_msg = _("unsupported vector index register"); | |
5259 | break; | |
43234a1e L |
5260 | case unsupported_broadcast: |
5261 | err_msg = _("unsupported broadcast"); | |
5262 | break; | |
5263 | case broadcast_not_on_src_operand: | |
5264 | err_msg = _("broadcast not on source memory operand"); | |
5265 | break; | |
5266 | case broadcast_needed: | |
5267 | err_msg = _("broadcast is needed for operand of such type"); | |
5268 | break; | |
5269 | case unsupported_masking: | |
5270 | err_msg = _("unsupported masking"); | |
5271 | break; | |
5272 | case mask_not_on_destination: | |
5273 | err_msg = _("mask not on destination operand"); | |
5274 | break; | |
5275 | case no_default_mask: | |
5276 | err_msg = _("default mask isn't allowed"); | |
5277 | break; | |
5278 | case unsupported_rc_sae: | |
5279 | err_msg = _("unsupported static rounding/sae"); | |
5280 | break; | |
5281 | case rc_sae_operand_not_last_imm: | |
5282 | if (intel_syntax) | |
5283 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
5284 | else | |
5285 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
5286 | break; | |
5287 | case invalid_register_operand: | |
5288 | err_msg = _("invalid register operand"); | |
5289 | break; | |
a65babc9 L |
5290 | } |
5291 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 5292 | current_templates->start->name); |
fa99fab2 | 5293 | return NULL; |
29b0f896 | 5294 | } |
252b5132 | 5295 | |
29b0f896 AM |
5296 | if (!quiet_warnings) |
5297 | { | |
5298 | if (!intel_syntax | |
40fb9820 L |
5299 | && (i.types[0].bitfield.jumpabsolute |
5300 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
5301 | { |
5302 | as_warn (_("indirect %s without `*'"), t->name); | |
5303 | } | |
5304 | ||
40fb9820 L |
5305 | if (t->opcode_modifier.isprefix |
5306 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
5307 | { |
5308 | /* Warn them that a data or address size prefix doesn't | |
5309 | affect assembly of the next line of code. */ | |
5310 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
5311 | } | |
5312 | } | |
5313 | ||
5314 | /* Copy the template we found. */ | |
5315 | i.tm = *t; | |
539e75ad L |
5316 | |
5317 | if (addr_prefix_disp != -1) | |
5318 | i.tm.operand_types[addr_prefix_disp] | |
5319 | = operand_types[addr_prefix_disp]; | |
5320 | ||
29b0f896 AM |
5321 | if (found_reverse_match) |
5322 | { | |
5323 | /* If we found a reverse match we must alter the opcode | |
5324 | direction bit. found_reverse_match holds bits to change | |
5325 | (different for int & float insns). */ | |
5326 | ||
5327 | i.tm.base_opcode ^= found_reverse_match; | |
5328 | ||
539e75ad L |
5329 | i.tm.operand_types[0] = operand_types[1]; |
5330 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
5331 | } |
5332 | ||
fa99fab2 | 5333 | return t; |
29b0f896 AM |
5334 | } |
5335 | ||
5336 | static int | |
e3bb37b5 | 5337 | check_string (void) |
29b0f896 | 5338 | { |
40fb9820 L |
5339 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
5340 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
5341 | { |
5342 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
5343 | { | |
a87af027 | 5344 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 5345 | i.tm.name, |
a87af027 JB |
5346 | mem_op + 1, |
5347 | register_prefix); | |
29b0f896 AM |
5348 | return 0; |
5349 | } | |
5350 | /* There's only ever one segment override allowed per instruction. | |
5351 | This instruction possibly has a legal segment override on the | |
5352 | second operand, so copy the segment to where non-string | |
5353 | instructions store it, allowing common code. */ | |
5354 | i.seg[0] = i.seg[1]; | |
5355 | } | |
40fb9820 | 5356 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
5357 | { |
5358 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
5359 | { | |
a87af027 | 5360 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 5361 | i.tm.name, |
a87af027 JB |
5362 | mem_op + 2, |
5363 | register_prefix); | |
29b0f896 AM |
5364 | return 0; |
5365 | } | |
5366 | } | |
5367 | return 1; | |
5368 | } | |
5369 | ||
5370 | static int | |
543613e9 | 5371 | process_suffix (void) |
29b0f896 AM |
5372 | { |
5373 | /* If matched instruction specifies an explicit instruction mnemonic | |
5374 | suffix, use it. */ | |
40fb9820 L |
5375 | if (i.tm.opcode_modifier.size16) |
5376 | i.suffix = WORD_MNEM_SUFFIX; | |
5377 | else if (i.tm.opcode_modifier.size32) | |
5378 | i.suffix = LONG_MNEM_SUFFIX; | |
5379 | else if (i.tm.opcode_modifier.size64) | |
5380 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
5381 | else if (i.reg_operands) |
5382 | { | |
5383 | /* If there's no instruction mnemonic suffix we try to invent one | |
5384 | based on register operands. */ | |
5385 | if (!i.suffix) | |
5386 | { | |
5387 | /* We take i.suffix from the last register operand specified, | |
5388 | Destination register type is more significant than source | |
381d071f L |
5389 | register type. crc32 in SSE4.2 prefers source register |
5390 | type. */ | |
5391 | if (i.tm.base_opcode == 0xf20f38f1) | |
5392 | { | |
40fb9820 L |
5393 | if (i.types[0].bitfield.reg16) |
5394 | i.suffix = WORD_MNEM_SUFFIX; | |
5395 | else if (i.types[0].bitfield.reg32) | |
5396 | i.suffix = LONG_MNEM_SUFFIX; | |
5397 | else if (i.types[0].bitfield.reg64) | |
5398 | i.suffix = QWORD_MNEM_SUFFIX; | |
381d071f | 5399 | } |
9344ff29 | 5400 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 5401 | { |
40fb9820 | 5402 | if (i.types[0].bitfield.reg8) |
20592a94 L |
5403 | i.suffix = BYTE_MNEM_SUFFIX; |
5404 | } | |
381d071f L |
5405 | |
5406 | if (!i.suffix) | |
5407 | { | |
5408 | int op; | |
5409 | ||
20592a94 L |
5410 | if (i.tm.base_opcode == 0xf20f38f1 |
5411 | || i.tm.base_opcode == 0xf20f38f0) | |
5412 | { | |
5413 | /* We have to know the operand size for crc32. */ | |
5414 | as_bad (_("ambiguous memory operand size for `%s`"), | |
5415 | i.tm.name); | |
5416 | return 0; | |
5417 | } | |
5418 | ||
381d071f | 5419 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5420 | if (!i.tm.operand_types[op].bitfield.inoutportreg) |
381d071f | 5421 | { |
40fb9820 L |
5422 | if (i.types[op].bitfield.reg8) |
5423 | { | |
5424 | i.suffix = BYTE_MNEM_SUFFIX; | |
5425 | break; | |
5426 | } | |
5427 | else if (i.types[op].bitfield.reg16) | |
5428 | { | |
5429 | i.suffix = WORD_MNEM_SUFFIX; | |
5430 | break; | |
5431 | } | |
5432 | else if (i.types[op].bitfield.reg32) | |
5433 | { | |
5434 | i.suffix = LONG_MNEM_SUFFIX; | |
5435 | break; | |
5436 | } | |
5437 | else if (i.types[op].bitfield.reg64) | |
5438 | { | |
5439 | i.suffix = QWORD_MNEM_SUFFIX; | |
5440 | break; | |
5441 | } | |
381d071f L |
5442 | } |
5443 | } | |
29b0f896 AM |
5444 | } |
5445 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
5446 | { | |
2eb952a4 L |
5447 | if (intel_syntax |
5448 | && i.tm.opcode_modifier.ignoresize | |
5449 | && i.tm.opcode_modifier.no_bsuf) | |
5450 | i.suffix = 0; | |
5451 | else if (!check_byte_reg ()) | |
29b0f896 AM |
5452 | return 0; |
5453 | } | |
5454 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
5455 | { | |
2eb952a4 L |
5456 | if (intel_syntax |
5457 | && i.tm.opcode_modifier.ignoresize | |
5458 | && i.tm.opcode_modifier.no_lsuf) | |
5459 | i.suffix = 0; | |
5460 | else if (!check_long_reg ()) | |
29b0f896 AM |
5461 | return 0; |
5462 | } | |
5463 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5464 | { | |
955e1e6a L |
5465 | if (intel_syntax |
5466 | && i.tm.opcode_modifier.ignoresize | |
5467 | && i.tm.opcode_modifier.no_qsuf) | |
5468 | i.suffix = 0; | |
5469 | else if (!check_qword_reg ()) | |
29b0f896 AM |
5470 | return 0; |
5471 | } | |
5472 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5473 | { | |
2eb952a4 L |
5474 | if (intel_syntax |
5475 | && i.tm.opcode_modifier.ignoresize | |
5476 | && i.tm.opcode_modifier.no_wsuf) | |
5477 | i.suffix = 0; | |
5478 | else if (!check_word_reg ()) | |
29b0f896 AM |
5479 | return 0; |
5480 | } | |
c0f3af97 | 5481 | else if (i.suffix == XMMWORD_MNEM_SUFFIX |
43234a1e L |
5482 | || i.suffix == YMMWORD_MNEM_SUFFIX |
5483 | || i.suffix == ZMMWORD_MNEM_SUFFIX) | |
582d5edd | 5484 | { |
43234a1e | 5485 | /* Skip if the instruction has x/y/z suffix. match_template |
582d5edd L |
5486 | should check if it is a valid suffix. */ |
5487 | } | |
40fb9820 | 5488 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
5489 | /* Do nothing if the instruction is going to ignore the prefix. */ |
5490 | ; | |
5491 | else | |
5492 | abort (); | |
5493 | } | |
40fb9820 | 5494 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
5495 | && !i.suffix |
5496 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 5497 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
5498 | { |
5499 | i.suffix = stackop_size; | |
5500 | } | |
9306ca4a JB |
5501 | else if (intel_syntax |
5502 | && !i.suffix | |
40fb9820 L |
5503 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
5504 | || i.tm.opcode_modifier.jumpbyte | |
5505 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
5506 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
5507 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
5508 | { |
5509 | switch (flag_code) | |
5510 | { | |
5511 | case CODE_64BIT: | |
40fb9820 | 5512 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
5513 | { |
5514 | i.suffix = QWORD_MNEM_SUFFIX; | |
5515 | break; | |
5516 | } | |
1a0670f3 | 5517 | /* Fall through. */ |
9306ca4a | 5518 | case CODE_32BIT: |
40fb9820 | 5519 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
5520 | i.suffix = LONG_MNEM_SUFFIX; |
5521 | break; | |
5522 | case CODE_16BIT: | |
40fb9820 | 5523 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
5524 | i.suffix = WORD_MNEM_SUFFIX; |
5525 | break; | |
5526 | } | |
5527 | } | |
252b5132 | 5528 | |
9306ca4a | 5529 | if (!i.suffix) |
29b0f896 | 5530 | { |
9306ca4a JB |
5531 | if (!intel_syntax) |
5532 | { | |
40fb9820 | 5533 | if (i.tm.opcode_modifier.w) |
9306ca4a | 5534 | { |
4eed87de AM |
5535 | as_bad (_("no instruction mnemonic suffix given and " |
5536 | "no register operands; can't size instruction")); | |
9306ca4a JB |
5537 | return 0; |
5538 | } | |
5539 | } | |
5540 | else | |
5541 | { | |
40fb9820 | 5542 | unsigned int suffixes; |
7ab9ffdd | 5543 | |
40fb9820 L |
5544 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
5545 | if (!i.tm.opcode_modifier.no_wsuf) | |
5546 | suffixes |= 1 << 1; | |
5547 | if (!i.tm.opcode_modifier.no_lsuf) | |
5548 | suffixes |= 1 << 2; | |
fc4adea1 | 5549 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
5550 | suffixes |= 1 << 3; |
5551 | if (!i.tm.opcode_modifier.no_ssuf) | |
5552 | suffixes |= 1 << 4; | |
5553 | if (!i.tm.opcode_modifier.no_qsuf) | |
5554 | suffixes |= 1 << 5; | |
5555 | ||
5556 | /* There are more than suffix matches. */ | |
5557 | if (i.tm.opcode_modifier.w | |
9306ca4a | 5558 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
5559 | && !i.tm.opcode_modifier.defaultsize |
5560 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
5561 | { |
5562 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
5563 | return 0; | |
5564 | } | |
5565 | } | |
29b0f896 | 5566 | } |
252b5132 | 5567 | |
9306ca4a JB |
5568 | /* Change the opcode based on the operand size given by i.suffix; |
5569 | We don't need to change things for byte insns. */ | |
5570 | ||
582d5edd L |
5571 | if (i.suffix |
5572 | && i.suffix != BYTE_MNEM_SUFFIX | |
c0f3af97 | 5573 | && i.suffix != XMMWORD_MNEM_SUFFIX |
43234a1e L |
5574 | && i.suffix != YMMWORD_MNEM_SUFFIX |
5575 | && i.suffix != ZMMWORD_MNEM_SUFFIX) | |
29b0f896 AM |
5576 | { |
5577 | /* It's not a byte, select word/dword operation. */ | |
40fb9820 | 5578 | if (i.tm.opcode_modifier.w) |
29b0f896 | 5579 | { |
40fb9820 | 5580 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
5581 | i.tm.base_opcode |= 8; |
5582 | else | |
5583 | i.tm.base_opcode |= 1; | |
5584 | } | |
0f3f3d8b | 5585 | |
29b0f896 AM |
5586 | /* Now select between word & dword operations via the operand |
5587 | size prefix, except for instructions that will ignore this | |
5588 | prefix anyway. */ | |
ca61edf2 | 5589 | if (i.tm.opcode_modifier.addrprefixop0) |
cb712a9e | 5590 | { |
ca61edf2 L |
5591 | /* The address size override prefix changes the size of the |
5592 | first operand. */ | |
40fb9820 L |
5593 | if ((flag_code == CODE_32BIT |
5594 | && i.op->regs[0].reg_type.bitfield.reg16) | |
5595 | || (flag_code != CODE_32BIT | |
5596 | && i.op->regs[0].reg_type.bitfield.reg32)) | |
cb712a9e L |
5597 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
5598 | return 0; | |
5599 | } | |
5600 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
5601 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX | |
40fb9820 L |
5602 | && !i.tm.opcode_modifier.ignoresize |
5603 | && !i.tm.opcode_modifier.floatmf | |
cb712a9e L |
5604 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
5605 | || (flag_code == CODE_64BIT | |
40fb9820 | 5606 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
5607 | { |
5608 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 5609 | |
40fb9820 | 5610 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 5611 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 5612 | |
29b0f896 AM |
5613 | if (!add_prefix (prefix)) |
5614 | return 0; | |
24eab124 | 5615 | } |
252b5132 | 5616 | |
29b0f896 AM |
5617 | /* Set mode64 for an operand. */ |
5618 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 5619 | && flag_code == CODE_64BIT |
40fb9820 | 5620 | && !i.tm.opcode_modifier.norex64) |
46e883c5 L |
5621 | { |
5622 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
d9a5e5e5 L |
5623 | need rex64. cmpxchg8b is also a special case. */ |
5624 | if (! (i.operands == 2 | |
5625 | && i.tm.base_opcode == 0x90 | |
5626 | && i.tm.extension_opcode == None | |
0dfbf9d7 L |
5627 | && operand_type_equal (&i.types [0], &acc64) |
5628 | && operand_type_equal (&i.types [1], &acc64)) | |
d9a5e5e5 L |
5629 | && ! (i.operands == 1 |
5630 | && i.tm.base_opcode == 0xfc7 | |
5631 | && i.tm.extension_opcode == 1 | |
40fb9820 L |
5632 | && !operand_type_check (i.types [0], reg) |
5633 | && operand_type_check (i.types [0], anymem))) | |
f6bee062 | 5634 | i.rex |= REX_W; |
46e883c5 | 5635 | } |
3e73aa7c | 5636 | |
29b0f896 AM |
5637 | /* Size floating point instruction. */ |
5638 | if (i.suffix == LONG_MNEM_SUFFIX) | |
40fb9820 | 5639 | if (i.tm.opcode_modifier.floatmf) |
543613e9 | 5640 | i.tm.base_opcode ^= 4; |
29b0f896 | 5641 | } |
7ecd2f8b | 5642 | |
29b0f896 AM |
5643 | return 1; |
5644 | } | |
3e73aa7c | 5645 | |
29b0f896 | 5646 | static int |
543613e9 | 5647 | check_byte_reg (void) |
29b0f896 AM |
5648 | { |
5649 | int op; | |
543613e9 | 5650 | |
29b0f896 AM |
5651 | for (op = i.operands; --op >= 0;) |
5652 | { | |
5653 | /* If this is an eight bit register, it's OK. If it's the 16 or | |
5654 | 32 bit version of an eight bit register, we will just use the | |
5655 | low portion, and that's OK too. */ | |
40fb9820 | 5656 | if (i.types[op].bitfield.reg8) |
29b0f896 AM |
5657 | continue; |
5658 | ||
5a819eb9 JB |
5659 | /* I/O port address operands are OK too. */ |
5660 | if (i.tm.operand_types[op].bitfield.inoutportreg) | |
5661 | continue; | |
5662 | ||
9344ff29 L |
5663 | /* crc32 doesn't generate this warning. */ |
5664 | if (i.tm.base_opcode == 0xf20f38f0) | |
5665 | continue; | |
5666 | ||
40fb9820 L |
5667 | if ((i.types[op].bitfield.reg16 |
5668 | || i.types[op].bitfield.reg32 | |
5669 | || i.types[op].bitfield.reg64) | |
5a819eb9 JB |
5670 | && i.op[op].regs->reg_num < 4 |
5671 | /* Prohibit these changes in 64bit mode, since the lowering | |
5672 | would be more complicated. */ | |
5673 | && flag_code != CODE_64BIT) | |
29b0f896 | 5674 | { |
29b0f896 | 5675 | #if REGISTER_WARNINGS |
5a819eb9 | 5676 | if (!quiet_warnings) |
a540244d L |
5677 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
5678 | register_prefix, | |
40fb9820 | 5679 | (i.op[op].regs + (i.types[op].bitfield.reg16 |
29b0f896 AM |
5680 | ? REGNAM_AL - REGNAM_AX |
5681 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 5682 | register_prefix, |
29b0f896 AM |
5683 | i.op[op].regs->reg_name, |
5684 | i.suffix); | |
5685 | #endif | |
5686 | continue; | |
5687 | } | |
5688 | /* Any other register is bad. */ | |
40fb9820 L |
5689 | if (i.types[op].bitfield.reg16 |
5690 | || i.types[op].bitfield.reg32 | |
5691 | || i.types[op].bitfield.reg64 | |
5692 | || i.types[op].bitfield.regmmx | |
5693 | || i.types[op].bitfield.regxmm | |
c0f3af97 | 5694 | || i.types[op].bitfield.regymm |
43234a1e | 5695 | || i.types[op].bitfield.regzmm |
40fb9820 L |
5696 | || i.types[op].bitfield.sreg2 |
5697 | || i.types[op].bitfield.sreg3 | |
5698 | || i.types[op].bitfield.control | |
5699 | || i.types[op].bitfield.debug | |
5700 | || i.types[op].bitfield.test | |
5701 | || i.types[op].bitfield.floatreg | |
5702 | || i.types[op].bitfield.floatacc) | |
29b0f896 | 5703 | { |
a540244d L |
5704 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5705 | register_prefix, | |
29b0f896 AM |
5706 | i.op[op].regs->reg_name, |
5707 | i.tm.name, | |
5708 | i.suffix); | |
5709 | return 0; | |
5710 | } | |
5711 | } | |
5712 | return 1; | |
5713 | } | |
5714 | ||
5715 | static int | |
e3bb37b5 | 5716 | check_long_reg (void) |
29b0f896 AM |
5717 | { |
5718 | int op; | |
5719 | ||
5720 | for (op = i.operands; --op >= 0;) | |
5721 | /* Reject eight bit registers, except where the template requires | |
5722 | them. (eg. movzb) */ | |
40fb9820 L |
5723 | if (i.types[op].bitfield.reg8 |
5724 | && (i.tm.operand_types[op].bitfield.reg16 | |
5725 | || i.tm.operand_types[op].bitfield.reg32 | |
5726 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 5727 | { |
a540244d L |
5728 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5729 | register_prefix, | |
29b0f896 AM |
5730 | i.op[op].regs->reg_name, |
5731 | i.tm.name, | |
5732 | i.suffix); | |
5733 | return 0; | |
5734 | } | |
e4630f71 | 5735 | /* Warn if the e prefix on a general reg is missing. */ |
29b0f896 | 5736 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
40fb9820 L |
5737 | && i.types[op].bitfield.reg16 |
5738 | && (i.tm.operand_types[op].bitfield.reg32 | |
5739 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
5740 | { |
5741 | /* Prohibit these changes in the 64bit mode, since the | |
5742 | lowering is more complicated. */ | |
5743 | if (flag_code == CODE_64BIT) | |
252b5132 | 5744 | { |
2b5d6a91 | 5745 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 5746 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
5747 | i.suffix); |
5748 | return 0; | |
252b5132 | 5749 | } |
29b0f896 | 5750 | #if REGISTER_WARNINGS |
cecf1424 JB |
5751 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
5752 | register_prefix, | |
5753 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
5754 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 | 5755 | #endif |
252b5132 | 5756 | } |
e4630f71 | 5757 | /* Warn if the r prefix on a general reg is present. */ |
40fb9820 L |
5758 | else if (i.types[op].bitfield.reg64 |
5759 | && (i.tm.operand_types[op].bitfield.reg32 | |
5760 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 5761 | { |
34828aad | 5762 | if (intel_syntax |
ca61edf2 | 5763 | && i.tm.opcode_modifier.toqword |
40fb9820 | 5764 | && !i.types[0].bitfield.regxmm) |
34828aad | 5765 | { |
ca61edf2 | 5766 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
5767 | i.suffix = QWORD_MNEM_SUFFIX; |
5768 | } | |
5769 | else | |
5770 | { | |
2b5d6a91 | 5771 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
5772 | register_prefix, i.op[op].regs->reg_name, |
5773 | i.suffix); | |
5774 | return 0; | |
5775 | } | |
29b0f896 AM |
5776 | } |
5777 | return 1; | |
5778 | } | |
252b5132 | 5779 | |
29b0f896 | 5780 | static int |
e3bb37b5 | 5781 | check_qword_reg (void) |
29b0f896 AM |
5782 | { |
5783 | int op; | |
252b5132 | 5784 | |
29b0f896 AM |
5785 | for (op = i.operands; --op >= 0; ) |
5786 | /* Reject eight bit registers, except where the template requires | |
5787 | them. (eg. movzb) */ | |
40fb9820 L |
5788 | if (i.types[op].bitfield.reg8 |
5789 | && (i.tm.operand_types[op].bitfield.reg16 | |
5790 | || i.tm.operand_types[op].bitfield.reg32 | |
5791 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 5792 | { |
a540244d L |
5793 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5794 | register_prefix, | |
29b0f896 AM |
5795 | i.op[op].regs->reg_name, |
5796 | i.tm.name, | |
5797 | i.suffix); | |
5798 | return 0; | |
5799 | } | |
e4630f71 | 5800 | /* Warn if the r prefix on a general reg is missing. */ |
40fb9820 L |
5801 | else if ((i.types[op].bitfield.reg16 |
5802 | || i.types[op].bitfield.reg32) | |
33d0ab95 | 5803 | && (i.tm.operand_types[op].bitfield.reg64 |
40fb9820 | 5804 | || i.tm.operand_types[op].bitfield.acc)) |
29b0f896 AM |
5805 | { |
5806 | /* Prohibit these changes in the 64bit mode, since the | |
5807 | lowering is more complicated. */ | |
34828aad | 5808 | if (intel_syntax |
ca61edf2 | 5809 | && i.tm.opcode_modifier.todword |
40fb9820 | 5810 | && !i.types[0].bitfield.regxmm) |
34828aad | 5811 | { |
ca61edf2 | 5812 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
5813 | i.suffix = LONG_MNEM_SUFFIX; |
5814 | } | |
5815 | else | |
5816 | { | |
2b5d6a91 | 5817 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
5818 | register_prefix, i.op[op].regs->reg_name, |
5819 | i.suffix); | |
5820 | return 0; | |
5821 | } | |
252b5132 | 5822 | } |
29b0f896 AM |
5823 | return 1; |
5824 | } | |
252b5132 | 5825 | |
29b0f896 | 5826 | static int |
e3bb37b5 | 5827 | check_word_reg (void) |
29b0f896 AM |
5828 | { |
5829 | int op; | |
5830 | for (op = i.operands; --op >= 0;) | |
5831 | /* Reject eight bit registers, except where the template requires | |
5832 | them. (eg. movzb) */ | |
40fb9820 L |
5833 | if (i.types[op].bitfield.reg8 |
5834 | && (i.tm.operand_types[op].bitfield.reg16 | |
5835 | || i.tm.operand_types[op].bitfield.reg32 | |
5836 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 5837 | { |
a540244d L |
5838 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5839 | register_prefix, | |
29b0f896 AM |
5840 | i.op[op].regs->reg_name, |
5841 | i.tm.name, | |
5842 | i.suffix); | |
5843 | return 0; | |
5844 | } | |
e4630f71 | 5845 | /* Warn if the e or r prefix on a general reg is present. */ |
29b0f896 | 5846 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
e4630f71 JB |
5847 | && (i.types[op].bitfield.reg32 |
5848 | || i.types[op].bitfield.reg64) | |
40fb9820 L |
5849 | && (i.tm.operand_types[op].bitfield.reg16 |
5850 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 5851 | { |
29b0f896 AM |
5852 | /* Prohibit these changes in the 64bit mode, since the |
5853 | lowering is more complicated. */ | |
5854 | if (flag_code == CODE_64BIT) | |
252b5132 | 5855 | { |
2b5d6a91 | 5856 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 5857 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
5858 | i.suffix); |
5859 | return 0; | |
252b5132 | 5860 | } |
29b0f896 | 5861 | #if REGISTER_WARNINGS |
cecf1424 JB |
5862 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
5863 | register_prefix, | |
5864 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
5865 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 AM |
5866 | #endif |
5867 | } | |
5868 | return 1; | |
5869 | } | |
252b5132 | 5870 | |
29b0f896 | 5871 | static int |
40fb9820 | 5872 | update_imm (unsigned int j) |
29b0f896 | 5873 | { |
bc0844ae | 5874 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
5875 | if ((overlap.bitfield.imm8 |
5876 | || overlap.bitfield.imm8s | |
5877 | || overlap.bitfield.imm16 | |
5878 | || overlap.bitfield.imm32 | |
5879 | || overlap.bitfield.imm32s | |
5880 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
5881 | && !operand_type_equal (&overlap, &imm8) |
5882 | && !operand_type_equal (&overlap, &imm8s) | |
5883 | && !operand_type_equal (&overlap, &imm16) | |
5884 | && !operand_type_equal (&overlap, &imm32) | |
5885 | && !operand_type_equal (&overlap, &imm32s) | |
5886 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
5887 | { |
5888 | if (i.suffix) | |
5889 | { | |
40fb9820 L |
5890 | i386_operand_type temp; |
5891 | ||
0dfbf9d7 | 5892 | operand_type_set (&temp, 0); |
7ab9ffdd | 5893 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
5894 | { |
5895 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
5896 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
5897 | } | |
5898 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5899 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
5900 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5901 | { | |
5902 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
5903 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
5904 | } | |
5905 | else | |
5906 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
5907 | overlap = temp; | |
29b0f896 | 5908 | } |
0dfbf9d7 L |
5909 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
5910 | || operand_type_equal (&overlap, &imm16_32) | |
5911 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 5912 | { |
40fb9820 | 5913 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 5914 | overlap = imm16; |
40fb9820 | 5915 | else |
65da13b5 | 5916 | overlap = imm32s; |
29b0f896 | 5917 | } |
0dfbf9d7 L |
5918 | if (!operand_type_equal (&overlap, &imm8) |
5919 | && !operand_type_equal (&overlap, &imm8s) | |
5920 | && !operand_type_equal (&overlap, &imm16) | |
5921 | && !operand_type_equal (&overlap, &imm32) | |
5922 | && !operand_type_equal (&overlap, &imm32s) | |
5923 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 5924 | { |
4eed87de AM |
5925 | as_bad (_("no instruction mnemonic suffix given; " |
5926 | "can't determine immediate size")); | |
29b0f896 AM |
5927 | return 0; |
5928 | } | |
5929 | } | |
40fb9820 | 5930 | i.types[j] = overlap; |
29b0f896 | 5931 | |
40fb9820 L |
5932 | return 1; |
5933 | } | |
5934 | ||
5935 | static int | |
5936 | finalize_imm (void) | |
5937 | { | |
bc0844ae | 5938 | unsigned int j, n; |
29b0f896 | 5939 | |
bc0844ae L |
5940 | /* Update the first 2 immediate operands. */ |
5941 | n = i.operands > 2 ? 2 : i.operands; | |
5942 | if (n) | |
5943 | { | |
5944 | for (j = 0; j < n; j++) | |
5945 | if (update_imm (j) == 0) | |
5946 | return 0; | |
40fb9820 | 5947 | |
bc0844ae L |
5948 | /* The 3rd operand can't be immediate operand. */ |
5949 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
5950 | } | |
29b0f896 AM |
5951 | |
5952 | return 1; | |
5953 | } | |
5954 | ||
c0f3af97 L |
5955 | static int |
5956 | bad_implicit_operand (int xmm) | |
5957 | { | |
91d6fa6a NC |
5958 | const char *ireg = xmm ? "xmm0" : "ymm0"; |
5959 | ||
c0f3af97 L |
5960 | if (intel_syntax) |
5961 | as_bad (_("the last operand of `%s' must be `%s%s'"), | |
91d6fa6a | 5962 | i.tm.name, register_prefix, ireg); |
c0f3af97 L |
5963 | else |
5964 | as_bad (_("the first operand of `%s' must be `%s%s'"), | |
91d6fa6a | 5965 | i.tm.name, register_prefix, ireg); |
c0f3af97 L |
5966 | return 0; |
5967 | } | |
5968 | ||
29b0f896 | 5969 | static int |
e3bb37b5 | 5970 | process_operands (void) |
29b0f896 AM |
5971 | { |
5972 | /* Default segment register this instruction will use for memory | |
5973 | accesses. 0 means unknown. This is only for optimizing out | |
5974 | unnecessary segment overrides. */ | |
5975 | const seg_entry *default_seg = 0; | |
5976 | ||
2426c15f | 5977 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 5978 | { |
91d6fa6a NC |
5979 | unsigned int dupl = i.operands; |
5980 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
5981 | unsigned int j; |
5982 | ||
c0f3af97 | 5983 | /* The destination must be an xmm register. */ |
9c2799c2 | 5984 | gas_assert (i.reg_operands |
91d6fa6a | 5985 | && MAX_OPERANDS > dupl |
7ab9ffdd | 5986 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 L |
5987 | |
5988 | if (i.tm.opcode_modifier.firstxmm0) | |
e2ec9d29 | 5989 | { |
c0f3af97 | 5990 | /* The first operand is implicit and must be xmm0. */ |
9c2799c2 | 5991 | gas_assert (operand_type_equal (&i.types[0], ®xmm)); |
4c692bc7 | 5992 | if (register_number (i.op[0].regs) != 0) |
c0f3af97 L |
5993 | return bad_implicit_operand (1); |
5994 | ||
8cd7925b | 5995 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
5996 | { |
5997 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
5998 | sources. */ | |
5999 | goto duplicate; | |
6000 | } | |
e2ec9d29 | 6001 | else |
c0f3af97 L |
6002 | { |
6003 | /* We remove the first xmm0 and keep the number of | |
6004 | operands unchanged, which in fact duplicates the | |
6005 | destination. */ | |
6006 | for (j = 1; j < i.operands; j++) | |
6007 | { | |
6008 | i.op[j - 1] = i.op[j]; | |
6009 | i.types[j - 1] = i.types[j]; | |
6010 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
6011 | } | |
6012 | } | |
6013 | } | |
6014 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 6015 | { |
91d6fa6a | 6016 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
6017 | && (i.tm.opcode_modifier.vexsources |
6018 | == VEX3SOURCES)); | |
c0f3af97 L |
6019 | |
6020 | /* Add the implicit xmm0 for instructions with VEX prefix | |
6021 | and 3 sources. */ | |
6022 | for (j = i.operands; j > 0; j--) | |
6023 | { | |
6024 | i.op[j] = i.op[j - 1]; | |
6025 | i.types[j] = i.types[j - 1]; | |
6026 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
6027 | } | |
6028 | i.op[0].regs | |
6029 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 6030 | i.types[0] = regxmm; |
c0f3af97 L |
6031 | i.tm.operand_types[0] = regxmm; |
6032 | ||
6033 | i.operands += 2; | |
6034 | i.reg_operands += 2; | |
6035 | i.tm.operands += 2; | |
6036 | ||
91d6fa6a | 6037 | dupl++; |
c0f3af97 | 6038 | dest++; |
91d6fa6a NC |
6039 | i.op[dupl] = i.op[dest]; |
6040 | i.types[dupl] = i.types[dest]; | |
6041 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
e2ec9d29 | 6042 | } |
c0f3af97 L |
6043 | else |
6044 | { | |
6045 | duplicate: | |
6046 | i.operands++; | |
6047 | i.reg_operands++; | |
6048 | i.tm.operands++; | |
6049 | ||
91d6fa6a NC |
6050 | i.op[dupl] = i.op[dest]; |
6051 | i.types[dupl] = i.types[dest]; | |
6052 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
c0f3af97 L |
6053 | } |
6054 | ||
6055 | if (i.tm.opcode_modifier.immext) | |
6056 | process_immext (); | |
6057 | } | |
6058 | else if (i.tm.opcode_modifier.firstxmm0) | |
6059 | { | |
6060 | unsigned int j; | |
6061 | ||
43234a1e | 6062 | /* The first operand is implicit and must be xmm0/ymm0/zmm0. */ |
9c2799c2 | 6063 | gas_assert (i.reg_operands |
7ab9ffdd | 6064 | && (operand_type_equal (&i.types[0], ®xmm) |
43234a1e L |
6065 | || operand_type_equal (&i.types[0], ®ymm) |
6066 | || operand_type_equal (&i.types[0], ®zmm))); | |
4c692bc7 | 6067 | if (register_number (i.op[0].regs) != 0) |
c0f3af97 | 6068 | return bad_implicit_operand (i.types[0].bitfield.regxmm); |
9fcfb3d7 L |
6069 | |
6070 | for (j = 1; j < i.operands; j++) | |
6071 | { | |
6072 | i.op[j - 1] = i.op[j]; | |
6073 | i.types[j - 1] = i.types[j]; | |
6074 | ||
6075 | /* We need to adjust fields in i.tm since they are used by | |
6076 | build_modrm_byte. */ | |
6077 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
6078 | } | |
6079 | ||
e2ec9d29 L |
6080 | i.operands--; |
6081 | i.reg_operands--; | |
e2ec9d29 L |
6082 | i.tm.operands--; |
6083 | } | |
920d2ddc IT |
6084 | else if (i.tm.opcode_modifier.implicitquadgroup) |
6085 | { | |
6086 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ | |
6087 | gas_assert (i.operands >= 2 | |
6088 | && (operand_type_equal (&i.types[1], ®xmm) | |
6089 | || operand_type_equal (&i.types[1], ®ymm) | |
6090 | || operand_type_equal (&i.types[1], ®zmm))); | |
6091 | unsigned int regnum = register_number (i.op[1].regs); | |
6092 | unsigned int first_reg_in_group = regnum & ~3; | |
6093 | unsigned int last_reg_in_group = first_reg_in_group + 3; | |
6094 | if (regnum != first_reg_in_group) { | |
6095 | as_warn (_("the second source register `%s%s' implicitly denotes" | |
6096 | " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"), | |
6097 | register_prefix, i.op[1].regs->reg_name, | |
6098 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
6099 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
6100 | i.tm.name); | |
6101 | } | |
6102 | } | |
e2ec9d29 L |
6103 | else if (i.tm.opcode_modifier.regkludge) |
6104 | { | |
6105 | /* The imul $imm, %reg instruction is converted into | |
6106 | imul $imm, %reg, %reg, and the clr %reg instruction | |
6107 | is converted into xor %reg, %reg. */ | |
6108 | ||
6109 | unsigned int first_reg_op; | |
6110 | ||
6111 | if (operand_type_check (i.types[0], reg)) | |
6112 | first_reg_op = 0; | |
6113 | else | |
6114 | first_reg_op = 1; | |
6115 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 6116 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 6117 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
6118 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
6119 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
6120 | i.operands++; | |
6121 | i.reg_operands++; | |
29b0f896 AM |
6122 | } |
6123 | ||
40fb9820 | 6124 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 6125 | { |
40fb9820 L |
6126 | if (i.types[0].bitfield.sreg2 |
6127 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 6128 | { |
4eed87de AM |
6129 | if (i.tm.base_opcode == POP_SEG_SHORT |
6130 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 6131 | { |
a87af027 | 6132 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 6133 | return 0; |
29b0f896 | 6134 | } |
4eed87de AM |
6135 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
6136 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6137 | i.rex |= REX_B; |
4eed87de AM |
6138 | } |
6139 | else | |
6140 | { | |
7ab9ffdd | 6141 | /* The register or float register operand is in operand |
85f10a01 | 6142 | 0 or 1. */ |
40fb9820 | 6143 | unsigned int op; |
7ab9ffdd L |
6144 | |
6145 | if (i.types[0].bitfield.floatreg | |
6146 | || operand_type_check (i.types[0], reg)) | |
6147 | op = 0; | |
6148 | else | |
6149 | op = 1; | |
4eed87de AM |
6150 | /* Register goes in low 3 bits of opcode. */ |
6151 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
6152 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6153 | i.rex |= REX_B; |
40fb9820 | 6154 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 6155 | { |
4eed87de AM |
6156 | /* Warn about some common errors, but press on regardless. |
6157 | The first case can be generated by gcc (<= 2.8.1). */ | |
6158 | if (i.operands == 2) | |
6159 | { | |
6160 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d | 6161 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
d8a1b51e JB |
6162 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
6163 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
4eed87de AM |
6164 | } |
6165 | else | |
6166 | { | |
6167 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
6168 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
6169 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 6170 | } |
29b0f896 AM |
6171 | } |
6172 | } | |
6173 | } | |
40fb9820 | 6174 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
6175 | { |
6176 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
6177 | must be put into the modrm byte). Now, we make the modrm and |
6178 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
6179 | |
6180 | default_seg = build_modrm_byte (); | |
6181 | } | |
8a2ed489 | 6182 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
6183 | { |
6184 | default_seg = &ds; | |
6185 | } | |
40fb9820 | 6186 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
6187 | { |
6188 | /* For the string instructions that allow a segment override | |
6189 | on one of their operands, the default segment is ds. */ | |
6190 | default_seg = &ds; | |
6191 | } | |
6192 | ||
75178d9d L |
6193 | if (i.tm.base_opcode == 0x8d /* lea */ |
6194 | && i.seg[0] | |
6195 | && !quiet_warnings) | |
30123838 | 6196 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
6197 | |
6198 | /* If a segment was explicitly specified, and the specified segment | |
6199 | is not the default, use an opcode prefix to select it. If we | |
6200 | never figured out what the default segment is, then default_seg | |
6201 | will be zero at this point, and the specified segment prefix will | |
6202 | always be used. */ | |
29b0f896 AM |
6203 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
6204 | { | |
6205 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
6206 | return 0; | |
6207 | } | |
6208 | return 1; | |
6209 | } | |
6210 | ||
6211 | static const seg_entry * | |
e3bb37b5 | 6212 | build_modrm_byte (void) |
29b0f896 AM |
6213 | { |
6214 | const seg_entry *default_seg = 0; | |
c0f3af97 | 6215 | unsigned int source, dest; |
8cd7925b | 6216 | int vex_3_sources; |
c0f3af97 L |
6217 | |
6218 | /* The first operand of instructions with VEX prefix and 3 sources | |
6219 | must be VEX_Imm4. */ | |
8cd7925b | 6220 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
6221 | if (vex_3_sources) |
6222 | { | |
91d6fa6a | 6223 | unsigned int nds, reg_slot; |
4c2c6516 | 6224 | expressionS *exp; |
c0f3af97 | 6225 | |
922d8de8 | 6226 | if (i.tm.opcode_modifier.veximmext |
a683cc34 SP |
6227 | && i.tm.opcode_modifier.immext) |
6228 | { | |
6229 | dest = i.operands - 2; | |
6230 | gas_assert (dest == 3); | |
6231 | } | |
922d8de8 | 6232 | else |
a683cc34 | 6233 | dest = i.operands - 1; |
c0f3af97 | 6234 | nds = dest - 1; |
922d8de8 | 6235 | |
a683cc34 SP |
6236 | /* There are 2 kinds of instructions: |
6237 | 1. 5 operands: 4 register operands or 3 register operands | |
6238 | plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and | |
43234a1e L |
6239 | VexW0 or VexW1. The destination must be either XMM, YMM or |
6240 | ZMM register. | |
a683cc34 SP |
6241 | 2. 4 operands: 4 register operands or 3 register operands |
6242 | plus 1 memory operand, VexXDS, and VexImmExt */ | |
922d8de8 | 6243 | gas_assert ((i.reg_operands == 4 |
a683cc34 SP |
6244 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
6245 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
6246 | && (i.tm.opcode_modifier.veximmext | |
6247 | || (i.imm_operands == 1 | |
6248 | && i.types[0].bitfield.vec_imm4 | |
6249 | && (i.tm.opcode_modifier.vexw == VEXW0 | |
6250 | || i.tm.opcode_modifier.vexw == VEXW1) | |
6251 | && (operand_type_equal (&i.tm.operand_types[dest], ®xmm) | |
43234a1e L |
6252 | || operand_type_equal (&i.tm.operand_types[dest], ®ymm) |
6253 | || operand_type_equal (&i.tm.operand_types[dest], ®zmm))))); | |
a683cc34 SP |
6254 | |
6255 | if (i.imm_operands == 0) | |
6256 | { | |
6257 | /* When there is no immediate operand, generate an 8bit | |
6258 | immediate operand to encode the first operand. */ | |
6259 | exp = &im_expressions[i.imm_operands++]; | |
6260 | i.op[i.operands].imms = exp; | |
6261 | i.types[i.operands] = imm8; | |
6262 | i.operands++; | |
6263 | /* If VexW1 is set, the first operand is the source and | |
6264 | the second operand is encoded in the immediate operand. */ | |
6265 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
6266 | { | |
6267 | source = 0; | |
6268 | reg_slot = 1; | |
6269 | } | |
6270 | else | |
6271 | { | |
6272 | source = 1; | |
6273 | reg_slot = 0; | |
6274 | } | |
6275 | ||
6276 | /* FMA swaps REG and NDS. */ | |
6277 | if (i.tm.cpu_flags.bitfield.cpufma) | |
6278 | { | |
6279 | unsigned int tmp; | |
6280 | tmp = reg_slot; | |
6281 | reg_slot = nds; | |
6282 | nds = tmp; | |
6283 | } | |
6284 | ||
24981e7b L |
6285 | gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], |
6286 | ®xmm) | |
a683cc34 | 6287 | || operand_type_equal (&i.tm.operand_types[reg_slot], |
43234a1e L |
6288 | ®ymm) |
6289 | || operand_type_equal (&i.tm.operand_types[reg_slot], | |
6290 | ®zmm)); | |
a683cc34 | 6291 | exp->X_op = O_constant; |
4c692bc7 | 6292 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; |
43234a1e L |
6293 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
6294 | } | |
922d8de8 | 6295 | else |
a683cc34 SP |
6296 | { |
6297 | unsigned int imm_slot; | |
6298 | ||
6299 | if (i.tm.opcode_modifier.vexw == VEXW0) | |
6300 | { | |
6301 | /* If VexW0 is set, the third operand is the source and | |
6302 | the second operand is encoded in the immediate | |
6303 | operand. */ | |
6304 | source = 2; | |
6305 | reg_slot = 1; | |
6306 | } | |
6307 | else | |
6308 | { | |
6309 | /* VexW1 is set, the second operand is the source and | |
6310 | the third operand is encoded in the immediate | |
6311 | operand. */ | |
6312 | source = 1; | |
6313 | reg_slot = 2; | |
6314 | } | |
6315 | ||
6316 | if (i.tm.opcode_modifier.immext) | |
6317 | { | |
33eaf5de | 6318 | /* When ImmExt is set, the immediate byte is the last |
a683cc34 SP |
6319 | operand. */ |
6320 | imm_slot = i.operands - 1; | |
6321 | source--; | |
6322 | reg_slot--; | |
6323 | } | |
6324 | else | |
6325 | { | |
6326 | imm_slot = 0; | |
6327 | ||
6328 | /* Turn on Imm8 so that output_imm will generate it. */ | |
6329 | i.types[imm_slot].bitfield.imm8 = 1; | |
6330 | } | |
6331 | ||
24981e7b L |
6332 | gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], |
6333 | ®xmm) | |
6334 | || operand_type_equal (&i.tm.operand_types[reg_slot], | |
43234a1e L |
6335 | ®ymm) |
6336 | || operand_type_equal (&i.tm.operand_types[reg_slot], | |
6337 | ®zmm)); | |
a683cc34 | 6338 | i.op[imm_slot].imms->X_add_number |
4c692bc7 | 6339 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 6340 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
a683cc34 SP |
6341 | } |
6342 | ||
6343 | gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm) | |
6344 | || operand_type_equal (&i.tm.operand_types[nds], | |
43234a1e L |
6345 | ®ymm) |
6346 | || operand_type_equal (&i.tm.operand_types[nds], | |
6347 | ®zmm)); | |
dae39acc | 6348 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
6349 | } |
6350 | else | |
6351 | source = dest = 0; | |
29b0f896 AM |
6352 | |
6353 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
6354 | implicit registers do not count. If there are 3 register |
6355 | operands, it must be a instruction with VexNDS. For a | |
6356 | instruction with VexNDD, the destination register is encoded | |
6357 | in VEX prefix. If there are 4 register operands, it must be | |
6358 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
6359 | if (i.mem_operands == 0 |
6360 | && ((i.reg_operands == 2 | |
2426c15f | 6361 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 6362 | || (i.reg_operands == 3 |
2426c15f | 6363 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 6364 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 6365 | { |
cab737b9 L |
6366 | switch (i.operands) |
6367 | { | |
6368 | case 2: | |
6369 | source = 0; | |
6370 | break; | |
6371 | case 3: | |
c81128dc L |
6372 | /* When there are 3 operands, one of them may be immediate, |
6373 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
6374 | the first operand must be shift count register (cl) or it |
6375 | is an instruction with VexNDS. */ | |
9c2799c2 | 6376 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 6377 | || (i.imm_operands == 0 |
2426c15f | 6378 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd | 6379 | || i.types[0].bitfield.shiftcount))); |
40fb9820 L |
6380 | if (operand_type_check (i.types[0], imm) |
6381 | || i.types[0].bitfield.shiftcount) | |
6382 | source = 1; | |
6383 | else | |
6384 | source = 0; | |
cab737b9 L |
6385 | break; |
6386 | case 4: | |
368d64cc L |
6387 | /* When there are 4 operands, the first two must be 8bit |
6388 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
6389 | one. |
6390 | ||
6391 | For instructions with VexNDS, if the first operand | |
6392 | an imm8, the source operand is the 2nd one. If the last | |
6393 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 6394 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
6395 | && i.types[0].bitfield.imm8 |
6396 | && i.types[1].bitfield.imm8) | |
2426c15f | 6397 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
6398 | && i.imm_operands == 1 |
6399 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
6400 | || i.types[i.operands - 1].bitfield.imm8 |
6401 | || i.rounding))); | |
9f2670f2 L |
6402 | if (i.imm_operands == 2) |
6403 | source = 2; | |
6404 | else | |
c0f3af97 L |
6405 | { |
6406 | if (i.types[0].bitfield.imm8) | |
6407 | source = 1; | |
6408 | else | |
6409 | source = 0; | |
6410 | } | |
c0f3af97 L |
6411 | break; |
6412 | case 5: | |
43234a1e L |
6413 | if (i.tm.opcode_modifier.evex) |
6414 | { | |
6415 | /* For EVEX instructions, when there are 5 operands, the | |
6416 | first one must be immediate operand. If the second one | |
6417 | is immediate operand, the source operand is the 3th | |
6418 | one. If the last one is immediate operand, the source | |
6419 | operand is the 2nd one. */ | |
6420 | gas_assert (i.imm_operands == 2 | |
6421 | && i.tm.opcode_modifier.sae | |
6422 | && operand_type_check (i.types[0], imm)); | |
6423 | if (operand_type_check (i.types[1], imm)) | |
6424 | source = 2; | |
6425 | else if (operand_type_check (i.types[4], imm)) | |
6426 | source = 1; | |
6427 | else | |
6428 | abort (); | |
6429 | } | |
cab737b9 L |
6430 | break; |
6431 | default: | |
6432 | abort (); | |
6433 | } | |
6434 | ||
c0f3af97 L |
6435 | if (!vex_3_sources) |
6436 | { | |
6437 | dest = source + 1; | |
6438 | ||
43234a1e L |
6439 | /* RC/SAE operand could be between DEST and SRC. That happens |
6440 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
6441 | register. */ | |
6442 | if (i.rounding && i.rounding->operand == (int) dest) | |
6443 | dest++; | |
6444 | ||
2426c15f | 6445 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 6446 | { |
43234a1e L |
6447 | /* For instructions with VexNDS, the register-only source |
6448 | operand must be 32/64bit integer, XMM, YMM or ZMM | |
6449 | register. It is encoded in VEX prefix. We need to | |
6450 | clear RegMem bit before calling operand_type_equal. */ | |
f12dc422 L |
6451 | |
6452 | i386_operand_type op; | |
6453 | unsigned int vvvv; | |
6454 | ||
6455 | /* Check register-only source operand when two source | |
6456 | operands are swapped. */ | |
6457 | if (!i.tm.operand_types[source].bitfield.baseindex | |
6458 | && i.tm.operand_types[dest].bitfield.baseindex) | |
6459 | { | |
6460 | vvvv = source; | |
6461 | source = dest; | |
6462 | } | |
6463 | else | |
6464 | vvvv = dest; | |
6465 | ||
6466 | op = i.tm.operand_types[vvvv]; | |
fa99fab2 | 6467 | op.bitfield.regmem = 0; |
c0f3af97 | 6468 | if ((dest + 1) >= i.operands |
ac4eb736 AM |
6469 | || (!op.bitfield.reg32 |
6470 | && op.bitfield.reg64 | |
f12dc422 | 6471 | && !operand_type_equal (&op, ®xmm) |
43234a1e L |
6472 | && !operand_type_equal (&op, ®ymm) |
6473 | && !operand_type_equal (&op, ®zmm) | |
6474 | && !operand_type_equal (&op, ®mask))) | |
c0f3af97 | 6475 | abort (); |
f12dc422 | 6476 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
6477 | dest++; |
6478 | } | |
6479 | } | |
29b0f896 AM |
6480 | |
6481 | i.rm.mode = 3; | |
6482 | /* One of the register operands will be encoded in the i.tm.reg | |
6483 | field, the other in the combined i.tm.mode and i.tm.regmem | |
6484 | fields. If no form of this instruction supports a memory | |
6485 | destination operand, then we assume the source operand may | |
6486 | sometimes be a memory operand and so we need to store the | |
6487 | destination in the i.rm.reg field. */ | |
40fb9820 L |
6488 | if (!i.tm.operand_types[dest].bitfield.regmem |
6489 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
6490 | { |
6491 | i.rm.reg = i.op[dest].regs->reg_num; | |
6492 | i.rm.regmem = i.op[source].regs->reg_num; | |
6493 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6494 | i.rex |= REX_R; |
43234a1e L |
6495 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
6496 | i.vrex |= REX_R; | |
29b0f896 | 6497 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 6498 | i.rex |= REX_B; |
43234a1e L |
6499 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
6500 | i.vrex |= REX_B; | |
29b0f896 AM |
6501 | } |
6502 | else | |
6503 | { | |
6504 | i.rm.reg = i.op[source].regs->reg_num; | |
6505 | i.rm.regmem = i.op[dest].regs->reg_num; | |
6506 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6507 | i.rex |= REX_B; |
43234a1e L |
6508 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
6509 | i.vrex |= REX_B; | |
29b0f896 | 6510 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 6511 | i.rex |= REX_R; |
43234a1e L |
6512 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
6513 | i.vrex |= REX_R; | |
29b0f896 | 6514 | } |
161a04f6 | 6515 | if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) |
c4a530c5 | 6516 | { |
40fb9820 L |
6517 | if (!i.types[0].bitfield.control |
6518 | && !i.types[1].bitfield.control) | |
c4a530c5 | 6519 | abort (); |
161a04f6 | 6520 | i.rex &= ~(REX_R | REX_B); |
c4a530c5 JB |
6521 | add_prefix (LOCK_PREFIX_OPCODE); |
6522 | } | |
29b0f896 AM |
6523 | } |
6524 | else | |
6525 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
6526 | unsigned int mem; |
6527 | ||
29b0f896 AM |
6528 | if (i.mem_operands) |
6529 | { | |
6530 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 6531 | unsigned int op; |
4eed87de | 6532 | |
7ab9ffdd L |
6533 | for (op = 0; op < i.operands; op++) |
6534 | if (operand_type_check (i.types[op], anymem)) | |
6535 | break; | |
7ab9ffdd | 6536 | gas_assert (op < i.operands); |
29b0f896 | 6537 | |
6c30d220 L |
6538 | if (i.tm.opcode_modifier.vecsib) |
6539 | { | |
6540 | if (i.index_reg->reg_num == RegEiz | |
6541 | || i.index_reg->reg_num == RegRiz) | |
6542 | abort (); | |
6543 | ||
6544 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
6545 | if (!i.base_reg) | |
6546 | { | |
6547 | i.sib.base = NO_BASE_REGISTER; | |
6548 | i.sib.scale = i.log2_scale_factor; | |
43234a1e L |
6549 | /* No Vec_Disp8 if there is no base. */ |
6550 | i.types[op].bitfield.vec_disp8 = 0; | |
6c30d220 L |
6551 | i.types[op].bitfield.disp8 = 0; |
6552 | i.types[op].bitfield.disp16 = 0; | |
6553 | i.types[op].bitfield.disp64 = 0; | |
6554 | if (flag_code != CODE_64BIT) | |
6555 | { | |
6556 | /* Must be 32 bit */ | |
6557 | i.types[op].bitfield.disp32 = 1; | |
6558 | i.types[op].bitfield.disp32s = 0; | |
6559 | } | |
6560 | else | |
6561 | { | |
6562 | i.types[op].bitfield.disp32 = 0; | |
6563 | i.types[op].bitfield.disp32s = 1; | |
6564 | } | |
6565 | } | |
6566 | i.sib.index = i.index_reg->reg_num; | |
6567 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
6568 | i.rex |= REX_X; | |
43234a1e L |
6569 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
6570 | i.vrex |= REX_X; | |
6c30d220 L |
6571 | } |
6572 | ||
29b0f896 AM |
6573 | default_seg = &ds; |
6574 | ||
6575 | if (i.base_reg == 0) | |
6576 | { | |
6577 | i.rm.mode = 0; | |
6578 | if (!i.disp_operands) | |
6c30d220 L |
6579 | { |
6580 | fake_zero_displacement = 1; | |
6581 | /* Instructions with VSIB byte need 32bit displacement | |
6582 | if there is no base register. */ | |
6583 | if (i.tm.opcode_modifier.vecsib) | |
6584 | i.types[op].bitfield.disp32 = 1; | |
6585 | } | |
29b0f896 AM |
6586 | if (i.index_reg == 0) |
6587 | { | |
6c30d220 | 6588 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 6589 | /* Operand is just <disp> */ |
20f0a1fc | 6590 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
6591 | { |
6592 | /* 64bit mode overwrites the 32bit absolute | |
6593 | addressing by RIP relative addressing and | |
6594 | absolute addressing is encoded by one of the | |
6595 | redundant SIB forms. */ | |
6596 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
6597 | i.sib.base = NO_BASE_REGISTER; | |
6598 | i.sib.index = NO_INDEX_REGISTER; | |
fc225355 | 6599 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) |
40fb9820 | 6600 | ? disp32s : disp32); |
20f0a1fc | 6601 | } |
fc225355 L |
6602 | else if ((flag_code == CODE_16BIT) |
6603 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
6604 | { |
6605 | i.rm.regmem = NO_BASE_REGISTER_16; | |
40fb9820 | 6606 | i.types[op] = disp16; |
20f0a1fc NC |
6607 | } |
6608 | else | |
6609 | { | |
6610 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 | 6611 | i.types[op] = disp32; |
29b0f896 AM |
6612 | } |
6613 | } | |
6c30d220 | 6614 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 6615 | { |
6c30d220 | 6616 | /* !i.base_reg && i.index_reg */ |
db51cc60 L |
6617 | if (i.index_reg->reg_num == RegEiz |
6618 | || i.index_reg->reg_num == RegRiz) | |
6619 | i.sib.index = NO_INDEX_REGISTER; | |
6620 | else | |
6621 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
6622 | i.sib.base = NO_BASE_REGISTER; |
6623 | i.sib.scale = i.log2_scale_factor; | |
6624 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
43234a1e L |
6625 | /* No Vec_Disp8 if there is no base. */ |
6626 | i.types[op].bitfield.vec_disp8 = 0; | |
40fb9820 L |
6627 | i.types[op].bitfield.disp8 = 0; |
6628 | i.types[op].bitfield.disp16 = 0; | |
6629 | i.types[op].bitfield.disp64 = 0; | |
29b0f896 | 6630 | if (flag_code != CODE_64BIT) |
40fb9820 L |
6631 | { |
6632 | /* Must be 32 bit */ | |
6633 | i.types[op].bitfield.disp32 = 1; | |
6634 | i.types[op].bitfield.disp32s = 0; | |
6635 | } | |
29b0f896 | 6636 | else |
40fb9820 L |
6637 | { |
6638 | i.types[op].bitfield.disp32 = 0; | |
6639 | i.types[op].bitfield.disp32s = 1; | |
6640 | } | |
29b0f896 | 6641 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 6642 | i.rex |= REX_X; |
29b0f896 AM |
6643 | } |
6644 | } | |
6645 | /* RIP addressing for 64bit mode. */ | |
9a04903e JB |
6646 | else if (i.base_reg->reg_num == RegRip || |
6647 | i.base_reg->reg_num == RegEip) | |
29b0f896 | 6648 | { |
6c30d220 | 6649 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 6650 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
6651 | i.types[op].bitfield.disp8 = 0; |
6652 | i.types[op].bitfield.disp16 = 0; | |
6653 | i.types[op].bitfield.disp32 = 0; | |
6654 | i.types[op].bitfield.disp32s = 1; | |
6655 | i.types[op].bitfield.disp64 = 0; | |
43234a1e | 6656 | i.types[op].bitfield.vec_disp8 = 0; |
71903a11 | 6657 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
6658 | if (! i.disp_operands) |
6659 | fake_zero_displacement = 1; | |
29b0f896 | 6660 | } |
40fb9820 | 6661 | else if (i.base_reg->reg_type.bitfield.reg16) |
29b0f896 | 6662 | { |
6c30d220 | 6663 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
6664 | switch (i.base_reg->reg_num) |
6665 | { | |
6666 | case 3: /* (%bx) */ | |
6667 | if (i.index_reg == 0) | |
6668 | i.rm.regmem = 7; | |
6669 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
6670 | i.rm.regmem = i.index_reg->reg_num - 6; | |
6671 | break; | |
6672 | case 5: /* (%bp) */ | |
6673 | default_seg = &ss; | |
6674 | if (i.index_reg == 0) | |
6675 | { | |
6676 | i.rm.regmem = 6; | |
40fb9820 | 6677 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
6678 | { |
6679 | /* fake (%bp) into 0(%bp) */ | |
43234a1e L |
6680 | if (i.tm.operand_types[op].bitfield.vec_disp8) |
6681 | i.types[op].bitfield.vec_disp8 = 1; | |
6682 | else | |
6683 | i.types[op].bitfield.disp8 = 1; | |
252b5132 | 6684 | fake_zero_displacement = 1; |
29b0f896 AM |
6685 | } |
6686 | } | |
6687 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
6688 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
6689 | break; | |
6690 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
6691 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
6692 | } | |
6693 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
6694 | } | |
6695 | else /* i.base_reg and 32/64 bit mode */ | |
6696 | { | |
6697 | if (flag_code == CODE_64BIT | |
40fb9820 L |
6698 | && operand_type_check (i.types[op], disp)) |
6699 | { | |
6700 | i386_operand_type temp; | |
0dfbf9d7 | 6701 | operand_type_set (&temp, 0); |
40fb9820 | 6702 | temp.bitfield.disp8 = i.types[op].bitfield.disp8; |
43234a1e L |
6703 | temp.bitfield.vec_disp8 |
6704 | = i.types[op].bitfield.vec_disp8; | |
40fb9820 L |
6705 | i.types[op] = temp; |
6706 | if (i.prefix[ADDR_PREFIX] == 0) | |
6707 | i.types[op].bitfield.disp32s = 1; | |
6708 | else | |
6709 | i.types[op].bitfield.disp32 = 1; | |
6710 | } | |
20f0a1fc | 6711 | |
6c30d220 L |
6712 | if (!i.tm.opcode_modifier.vecsib) |
6713 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 6714 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 6715 | i.rex |= REX_B; |
29b0f896 AM |
6716 | i.sib.base = i.base_reg->reg_num; |
6717 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
6718 | complications. */ | |
848930b2 JB |
6719 | if (!(i.base_reg->reg_flags & RegRex) |
6720 | && (i.base_reg->reg_num == EBP_REG_NUM | |
6721 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 6722 | default_seg = &ss; |
848930b2 | 6723 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 6724 | { |
848930b2 | 6725 | fake_zero_displacement = 1; |
43234a1e L |
6726 | if (i.tm.operand_types [op].bitfield.vec_disp8) |
6727 | i.types[op].bitfield.vec_disp8 = 1; | |
6728 | else | |
6729 | i.types[op].bitfield.disp8 = 1; | |
29b0f896 AM |
6730 | } |
6731 | i.sib.scale = i.log2_scale_factor; | |
6732 | if (i.index_reg == 0) | |
6733 | { | |
6c30d220 | 6734 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
6735 | /* <disp>(%esp) becomes two byte modrm with no index |
6736 | register. We've already stored the code for esp | |
6737 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
6738 | Any base register besides %esp will not use the | |
6739 | extra modrm byte. */ | |
6740 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 6741 | } |
6c30d220 | 6742 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 6743 | { |
db51cc60 L |
6744 | if (i.index_reg->reg_num == RegEiz |
6745 | || i.index_reg->reg_num == RegRiz) | |
6746 | i.sib.index = NO_INDEX_REGISTER; | |
6747 | else | |
6748 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
6749 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
6750 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 6751 | i.rex |= REX_X; |
29b0f896 | 6752 | } |
67a4f2b7 AO |
6753 | |
6754 | if (i.disp_operands | |
6755 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
6756 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
6757 | i.rm.mode = 0; | |
6758 | else | |
a501d77e L |
6759 | { |
6760 | if (!fake_zero_displacement | |
6761 | && !i.disp_operands | |
6762 | && i.disp_encoding) | |
6763 | { | |
6764 | fake_zero_displacement = 1; | |
6765 | if (i.disp_encoding == disp_encoding_8bit) | |
6766 | i.types[op].bitfield.disp8 = 1; | |
6767 | else | |
6768 | i.types[op].bitfield.disp32 = 1; | |
6769 | } | |
6770 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
6771 | } | |
29b0f896 | 6772 | } |
252b5132 | 6773 | |
29b0f896 AM |
6774 | if (fake_zero_displacement) |
6775 | { | |
6776 | /* Fakes a zero displacement assuming that i.types[op] | |
6777 | holds the correct displacement size. */ | |
6778 | expressionS *exp; | |
6779 | ||
9c2799c2 | 6780 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
6781 | exp = &disp_expressions[i.disp_operands++]; |
6782 | i.op[op].disps = exp; | |
6783 | exp->X_op = O_constant; | |
6784 | exp->X_add_number = 0; | |
6785 | exp->X_add_symbol = (symbolS *) 0; | |
6786 | exp->X_op_symbol = (symbolS *) 0; | |
6787 | } | |
c0f3af97 L |
6788 | |
6789 | mem = op; | |
29b0f896 | 6790 | } |
c0f3af97 L |
6791 | else |
6792 | mem = ~0; | |
252b5132 | 6793 | |
8c43a48b | 6794 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
6795 | { |
6796 | if (operand_type_check (i.types[0], imm)) | |
6797 | i.vex.register_specifier = NULL; | |
6798 | else | |
6799 | { | |
6800 | /* VEX.vvvv encodes one of the sources when the first | |
6801 | operand is not an immediate. */ | |
1ef99a7b | 6802 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
6803 | i.vex.register_specifier = i.op[0].regs; |
6804 | else | |
6805 | i.vex.register_specifier = i.op[1].regs; | |
6806 | } | |
6807 | ||
6808 | /* Destination is a XMM register encoded in the ModRM.reg | |
6809 | and VEX.R bit. */ | |
6810 | i.rm.reg = i.op[2].regs->reg_num; | |
6811 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
6812 | i.rex |= REX_R; | |
6813 | ||
6814 | /* ModRM.rm and VEX.B encodes the other source. */ | |
6815 | if (!i.mem_operands) | |
6816 | { | |
6817 | i.rm.mode = 3; | |
6818 | ||
1ef99a7b | 6819 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
6820 | i.rm.regmem = i.op[1].regs->reg_num; |
6821 | else | |
6822 | i.rm.regmem = i.op[0].regs->reg_num; | |
6823 | ||
6824 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
6825 | i.rex |= REX_B; | |
6826 | } | |
6827 | } | |
2426c15f | 6828 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
6829 | { |
6830 | i.vex.register_specifier = i.op[2].regs; | |
6831 | if (!i.mem_operands) | |
6832 | { | |
6833 | i.rm.mode = 3; | |
6834 | i.rm.regmem = i.op[1].regs->reg_num; | |
6835 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
6836 | i.rex |= REX_B; | |
6837 | } | |
6838 | } | |
29b0f896 AM |
6839 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
6840 | (if any) based on i.tm.extension_opcode. Again, we must be | |
6841 | careful to make sure that segment/control/debug/test/MMX | |
6842 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 6843 | else if (i.reg_operands) |
29b0f896 | 6844 | { |
99018f42 | 6845 | unsigned int op; |
7ab9ffdd L |
6846 | unsigned int vex_reg = ~0; |
6847 | ||
6848 | for (op = 0; op < i.operands; op++) | |
6849 | if (i.types[op].bitfield.reg8 | |
6850 | || i.types[op].bitfield.reg16 | |
6851 | || i.types[op].bitfield.reg32 | |
6852 | || i.types[op].bitfield.reg64 | |
6853 | || i.types[op].bitfield.regmmx | |
6854 | || i.types[op].bitfield.regxmm | |
6855 | || i.types[op].bitfield.regymm | |
7e8b059b | 6856 | || i.types[op].bitfield.regbnd |
43234a1e L |
6857 | || i.types[op].bitfield.regzmm |
6858 | || i.types[op].bitfield.regmask | |
7ab9ffdd L |
6859 | || i.types[op].bitfield.sreg2 |
6860 | || i.types[op].bitfield.sreg3 | |
6861 | || i.types[op].bitfield.control | |
6862 | || i.types[op].bitfield.debug | |
6863 | || i.types[op].bitfield.test) | |
6864 | break; | |
c0209578 | 6865 | |
7ab9ffdd L |
6866 | if (vex_3_sources) |
6867 | op = dest; | |
2426c15f | 6868 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
6869 | { |
6870 | /* For instructions with VexNDS, the register-only | |
6871 | source operand is encoded in VEX prefix. */ | |
6872 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 6873 | |
7ab9ffdd | 6874 | if (op > mem) |
c0f3af97 | 6875 | { |
7ab9ffdd L |
6876 | vex_reg = op++; |
6877 | gas_assert (op < i.operands); | |
c0f3af97 L |
6878 | } |
6879 | else | |
c0f3af97 | 6880 | { |
f12dc422 L |
6881 | /* Check register-only source operand when two source |
6882 | operands are swapped. */ | |
6883 | if (!i.tm.operand_types[op].bitfield.baseindex | |
6884 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
6885 | { | |
6886 | vex_reg = op; | |
6887 | op += 2; | |
6888 | gas_assert (mem == (vex_reg + 1) | |
6889 | && op < i.operands); | |
6890 | } | |
6891 | else | |
6892 | { | |
6893 | vex_reg = op + 1; | |
6894 | gas_assert (vex_reg < i.operands); | |
6895 | } | |
c0f3af97 | 6896 | } |
7ab9ffdd | 6897 | } |
2426c15f | 6898 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 6899 | { |
f12dc422 | 6900 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 6901 | is encoded in VEX prefix. */ |
f12dc422 L |
6902 | if (i.mem_operands == 0) |
6903 | { | |
6904 | /* There is no memory operand. */ | |
6905 | gas_assert ((op + 2) == i.operands); | |
6906 | vex_reg = op + 1; | |
6907 | } | |
6908 | else | |
8d63c93e | 6909 | { |
f12dc422 L |
6910 | /* There are only 2 operands. */ |
6911 | gas_assert (op < 2 && i.operands == 2); | |
6912 | vex_reg = 1; | |
6913 | } | |
7ab9ffdd L |
6914 | } |
6915 | else | |
6916 | gas_assert (op < i.operands); | |
99018f42 | 6917 | |
7ab9ffdd L |
6918 | if (vex_reg != (unsigned int) ~0) |
6919 | { | |
f12dc422 | 6920 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 6921 | |
f12dc422 L |
6922 | if (type->bitfield.reg32 != 1 |
6923 | && type->bitfield.reg64 != 1 | |
6924 | && !operand_type_equal (type, ®xmm) | |
43234a1e L |
6925 | && !operand_type_equal (type, ®ymm) |
6926 | && !operand_type_equal (type, ®zmm) | |
6927 | && !operand_type_equal (type, ®mask)) | |
7ab9ffdd | 6928 | abort (); |
f88c9eb0 | 6929 | |
7ab9ffdd L |
6930 | i.vex.register_specifier = i.op[vex_reg].regs; |
6931 | } | |
6932 | ||
1b9f0c97 L |
6933 | /* Don't set OP operand twice. */ |
6934 | if (vex_reg != op) | |
7ab9ffdd | 6935 | { |
1b9f0c97 L |
6936 | /* If there is an extension opcode to put here, the |
6937 | register number must be put into the regmem field. */ | |
6938 | if (i.tm.extension_opcode != None) | |
6939 | { | |
6940 | i.rm.regmem = i.op[op].regs->reg_num; | |
6941 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
6942 | i.rex |= REX_B; | |
43234a1e L |
6943 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
6944 | i.vrex |= REX_B; | |
1b9f0c97 L |
6945 | } |
6946 | else | |
6947 | { | |
6948 | i.rm.reg = i.op[op].regs->reg_num; | |
6949 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
6950 | i.rex |= REX_R; | |
43234a1e L |
6951 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
6952 | i.vrex |= REX_R; | |
1b9f0c97 | 6953 | } |
7ab9ffdd | 6954 | } |
252b5132 | 6955 | |
29b0f896 AM |
6956 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
6957 | must set it to 3 to indicate this is a register operand | |
6958 | in the regmem field. */ | |
6959 | if (!i.mem_operands) | |
6960 | i.rm.mode = 3; | |
6961 | } | |
252b5132 | 6962 | |
29b0f896 | 6963 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 6964 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
6965 | i.rm.reg = i.tm.extension_opcode; |
6966 | } | |
6967 | return default_seg; | |
6968 | } | |
252b5132 | 6969 | |
29b0f896 | 6970 | static void |
e3bb37b5 | 6971 | output_branch (void) |
29b0f896 AM |
6972 | { |
6973 | char *p; | |
f8a5c266 | 6974 | int size; |
29b0f896 AM |
6975 | int code16; |
6976 | int prefix; | |
6977 | relax_substateT subtype; | |
6978 | symbolS *sym; | |
6979 | offsetT off; | |
6980 | ||
f8a5c266 | 6981 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 6982 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
6983 | |
6984 | prefix = 0; | |
6985 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 6986 | { |
29b0f896 AM |
6987 | prefix = 1; |
6988 | i.prefixes -= 1; | |
6989 | code16 ^= CODE16; | |
252b5132 | 6990 | } |
29b0f896 AM |
6991 | /* Pentium4 branch hints. */ |
6992 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
6993 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 6994 | { |
29b0f896 AM |
6995 | prefix++; |
6996 | i.prefixes--; | |
6997 | } | |
6998 | if (i.prefix[REX_PREFIX] != 0) | |
6999 | { | |
7000 | prefix++; | |
7001 | i.prefixes--; | |
2f66722d AM |
7002 | } |
7003 | ||
7e8b059b L |
7004 | /* BND prefixed jump. */ |
7005 | if (i.prefix[BND_PREFIX] != 0) | |
7006 | { | |
7007 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7008 | i.prefixes -= 1; | |
7009 | } | |
7010 | ||
29b0f896 AM |
7011 | if (i.prefixes != 0 && !intel_syntax) |
7012 | as_warn (_("skipping prefixes on this instruction")); | |
7013 | ||
7014 | /* It's always a symbol; End frag & setup for relax. | |
7015 | Make sure there is enough room in this frag for the largest | |
7016 | instruction we may generate in md_convert_frag. This is 2 | |
7017 | bytes for the opcode and room for the prefix and largest | |
7018 | displacement. */ | |
7019 | frag_grow (prefix + 2 + 4); | |
7020 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
7021 | p = frag_more (prefix + 1); | |
7022 | if (i.prefix[DATA_PREFIX] != 0) | |
7023 | *p++ = DATA_PREFIX_OPCODE; | |
7024 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
7025 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
7026 | *p++ = i.prefix[SEG_PREFIX]; | |
7027 | if (i.prefix[REX_PREFIX] != 0) | |
7028 | *p++ = i.prefix[REX_PREFIX]; | |
7029 | *p = i.tm.base_opcode; | |
7030 | ||
7031 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 7032 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 7033 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 7034 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 7035 | else |
f8a5c266 | 7036 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 7037 | subtype |= code16; |
3e73aa7c | 7038 | |
29b0f896 AM |
7039 | sym = i.op[0].disps->X_add_symbol; |
7040 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 7041 | |
29b0f896 AM |
7042 | if (i.op[0].disps->X_op != O_constant |
7043 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 7044 | { |
29b0f896 AM |
7045 | /* Handle complex expressions. */ |
7046 | sym = make_expr_symbol (i.op[0].disps); | |
7047 | off = 0; | |
7048 | } | |
3e73aa7c | 7049 | |
29b0f896 AM |
7050 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
7051 | Pass reloc in fr_var. */ | |
d258b828 | 7052 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 7053 | } |
3e73aa7c | 7054 | |
29b0f896 | 7055 | static void |
e3bb37b5 | 7056 | output_jump (void) |
29b0f896 AM |
7057 | { |
7058 | char *p; | |
7059 | int size; | |
3e02c1cc | 7060 | fixS *fixP; |
29b0f896 | 7061 | |
40fb9820 | 7062 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
7063 | { |
7064 | /* This is a loop or jecxz type instruction. */ | |
7065 | size = 1; | |
7066 | if (i.prefix[ADDR_PREFIX] != 0) | |
7067 | { | |
7068 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
7069 | i.prefixes -= 1; | |
7070 | } | |
7071 | /* Pentium4 branch hints. */ | |
7072 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7073 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
7074 | { | |
7075 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
7076 | i.prefixes--; | |
3e73aa7c JH |
7077 | } |
7078 | } | |
29b0f896 AM |
7079 | else |
7080 | { | |
7081 | int code16; | |
3e73aa7c | 7082 | |
29b0f896 AM |
7083 | code16 = 0; |
7084 | if (flag_code == CODE_16BIT) | |
7085 | code16 = CODE16; | |
3e73aa7c | 7086 | |
29b0f896 AM |
7087 | if (i.prefix[DATA_PREFIX] != 0) |
7088 | { | |
7089 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
7090 | i.prefixes -= 1; | |
7091 | code16 ^= CODE16; | |
7092 | } | |
252b5132 | 7093 | |
29b0f896 AM |
7094 | size = 4; |
7095 | if (code16) | |
7096 | size = 2; | |
7097 | } | |
9fcc94b6 | 7098 | |
29b0f896 AM |
7099 | if (i.prefix[REX_PREFIX] != 0) |
7100 | { | |
7101 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
7102 | i.prefixes -= 1; | |
7103 | } | |
252b5132 | 7104 | |
7e8b059b L |
7105 | /* BND prefixed jump. */ |
7106 | if (i.prefix[BND_PREFIX] != 0) | |
7107 | { | |
7108 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7109 | i.prefixes -= 1; | |
7110 | } | |
7111 | ||
29b0f896 AM |
7112 | if (i.prefixes != 0 && !intel_syntax) |
7113 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 7114 | |
42164a71 L |
7115 | p = frag_more (i.tm.opcode_length + size); |
7116 | switch (i.tm.opcode_length) | |
7117 | { | |
7118 | case 2: | |
7119 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 7120 | /* Fall through. */ |
42164a71 L |
7121 | case 1: |
7122 | *p++ = i.tm.base_opcode; | |
7123 | break; | |
7124 | default: | |
7125 | abort (); | |
7126 | } | |
e0890092 | 7127 | |
3e02c1cc | 7128 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
d258b828 | 7129 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); |
3e02c1cc AM |
7130 | |
7131 | /* All jumps handled here are signed, but don't use a signed limit | |
7132 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
7133 | 4G and 64k respectively. */ | |
7134 | if (size == 1) | |
7135 | fixP->fx_signed = 1; | |
29b0f896 | 7136 | } |
e0890092 | 7137 | |
29b0f896 | 7138 | static void |
e3bb37b5 | 7139 | output_interseg_jump (void) |
29b0f896 AM |
7140 | { |
7141 | char *p; | |
7142 | int size; | |
7143 | int prefix; | |
7144 | int code16; | |
252b5132 | 7145 | |
29b0f896 AM |
7146 | code16 = 0; |
7147 | if (flag_code == CODE_16BIT) | |
7148 | code16 = CODE16; | |
a217f122 | 7149 | |
29b0f896 AM |
7150 | prefix = 0; |
7151 | if (i.prefix[DATA_PREFIX] != 0) | |
7152 | { | |
7153 | prefix = 1; | |
7154 | i.prefixes -= 1; | |
7155 | code16 ^= CODE16; | |
7156 | } | |
7157 | if (i.prefix[REX_PREFIX] != 0) | |
7158 | { | |
7159 | prefix++; | |
7160 | i.prefixes -= 1; | |
7161 | } | |
252b5132 | 7162 | |
29b0f896 AM |
7163 | size = 4; |
7164 | if (code16) | |
7165 | size = 2; | |
252b5132 | 7166 | |
29b0f896 AM |
7167 | if (i.prefixes != 0 && !intel_syntax) |
7168 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 7169 | |
29b0f896 AM |
7170 | /* 1 opcode; 2 segment; offset */ |
7171 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 7172 | |
29b0f896 AM |
7173 | if (i.prefix[DATA_PREFIX] != 0) |
7174 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 7175 | |
29b0f896 AM |
7176 | if (i.prefix[REX_PREFIX] != 0) |
7177 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 7178 | |
29b0f896 AM |
7179 | *p++ = i.tm.base_opcode; |
7180 | if (i.op[1].imms->X_op == O_constant) | |
7181 | { | |
7182 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 7183 | |
29b0f896 AM |
7184 | if (size == 2 |
7185 | && !fits_in_unsigned_word (n) | |
7186 | && !fits_in_signed_word (n)) | |
7187 | { | |
7188 | as_bad (_("16-bit jump out of range")); | |
7189 | return; | |
7190 | } | |
7191 | md_number_to_chars (p, n, size); | |
7192 | } | |
7193 | else | |
7194 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 7195 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
7196 | if (i.op[0].imms->X_op != O_constant) |
7197 | as_bad (_("can't handle non absolute segment in `%s'"), | |
7198 | i.tm.name); | |
7199 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
7200 | } | |
a217f122 | 7201 | |
29b0f896 | 7202 | static void |
e3bb37b5 | 7203 | output_insn (void) |
29b0f896 | 7204 | { |
2bbd9c25 JJ |
7205 | fragS *insn_start_frag; |
7206 | offsetT insn_start_off; | |
7207 | ||
29b0f896 AM |
7208 | /* Tie dwarf2 debug info to the address at the start of the insn. |
7209 | We can't do this after the insn has been output as the current | |
7210 | frag may have been closed off. eg. by frag_var. */ | |
7211 | dwarf2_emit_insn (0); | |
7212 | ||
2bbd9c25 JJ |
7213 | insn_start_frag = frag_now; |
7214 | insn_start_off = frag_now_fix (); | |
7215 | ||
29b0f896 | 7216 | /* Output jumps. */ |
40fb9820 | 7217 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 7218 | output_branch (); |
40fb9820 L |
7219 | else if (i.tm.opcode_modifier.jumpbyte |
7220 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 7221 | output_jump (); |
40fb9820 | 7222 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
7223 | output_interseg_jump (); |
7224 | else | |
7225 | { | |
7226 | /* Output normal instructions here. */ | |
7227 | char *p; | |
7228 | unsigned char *q; | |
47465058 | 7229 | unsigned int j; |
331d2d0d | 7230 | unsigned int prefix; |
4dffcebc | 7231 | |
e4e00185 AS |
7232 | if (avoid_fence |
7233 | && i.tm.base_opcode == 0xfae | |
7234 | && i.operands == 1 | |
7235 | && i.imm_operands == 1 | |
7236 | && (i.op[0].imms->X_add_number == 0xe8 | |
7237 | || i.op[0].imms->X_add_number == 0xf0 | |
7238 | || i.op[0].imms->X_add_number == 0xf8)) | |
7239 | { | |
7240 | /* Encode lfence, mfence, and sfence as | |
7241 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
7242 | offsetT val = 0x240483f0ULL; | |
7243 | p = frag_more (5); | |
7244 | md_number_to_chars (p, val, 5); | |
7245 | return; | |
7246 | } | |
7247 | ||
d022bddd IT |
7248 | /* Some processors fail on LOCK prefix. This options makes |
7249 | assembler ignore LOCK prefix and serves as a workaround. */ | |
7250 | if (omit_lock_prefix) | |
7251 | { | |
7252 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
7253 | return; | |
7254 | i.prefix[LOCK_PREFIX] = 0; | |
7255 | } | |
7256 | ||
43234a1e L |
7257 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
7258 | don't need the explicit prefix. */ | |
7259 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 7260 | { |
c0f3af97 | 7261 | switch (i.tm.opcode_length) |
bc4bd9ab | 7262 | { |
c0f3af97 L |
7263 | case 3: |
7264 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 7265 | { |
c0f3af97 L |
7266 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
7267 | goto check_prefix; | |
7268 | } | |
7269 | break; | |
7270 | case 2: | |
7271 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
7272 | { | |
7273 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
7274 | if (i.tm.cpu_flags.bitfield.cpupadlock) | |
7275 | { | |
4dffcebc | 7276 | check_prefix: |
c0f3af97 | 7277 | if (prefix != REPE_PREFIX_OPCODE |
c32fa91d | 7278 | || (i.prefix[REP_PREFIX] |
c0f3af97 L |
7279 | != REPE_PREFIX_OPCODE)) |
7280 | add_prefix (prefix); | |
7281 | } | |
7282 | else | |
4dffcebc L |
7283 | add_prefix (prefix); |
7284 | } | |
c0f3af97 L |
7285 | break; |
7286 | case 1: | |
7287 | break; | |
7288 | default: | |
7289 | abort (); | |
bc4bd9ab | 7290 | } |
c0f3af97 | 7291 | |
6d19a37a | 7292 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
7293 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
7294 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
7295 | perform IE->LE optimization. */ | |
7296 | if (x86_elf_abi == X86_64_X32_ABI | |
7297 | && i.operands == 2 | |
7298 | && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF | |
7299 | && i.prefix[REX_PREFIX] == 0) | |
7300 | add_prefix (REX_OPCODE); | |
6d19a37a | 7301 | #endif |
cf61b747 | 7302 | |
c0f3af97 L |
7303 | /* The prefix bytes. */ |
7304 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
7305 | if (*q) | |
7306 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 7307 | } |
ae5c1c7b | 7308 | else |
c0f3af97 L |
7309 | { |
7310 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
7311 | if (*q) | |
7312 | switch (j) | |
7313 | { | |
7314 | case REX_PREFIX: | |
7315 | /* REX byte is encoded in VEX prefix. */ | |
7316 | break; | |
7317 | case SEG_PREFIX: | |
7318 | case ADDR_PREFIX: | |
7319 | FRAG_APPEND_1_CHAR (*q); | |
7320 | break; | |
7321 | default: | |
7322 | /* There should be no other prefixes for instructions | |
7323 | with VEX prefix. */ | |
7324 | abort (); | |
7325 | } | |
7326 | ||
43234a1e L |
7327 | /* For EVEX instructions i.vrex should become 0 after |
7328 | build_evex_prefix. For VEX instructions upper 16 registers | |
7329 | aren't available, so VREX should be 0. */ | |
7330 | if (i.vrex) | |
7331 | abort (); | |
c0f3af97 L |
7332 | /* Now the VEX prefix. */ |
7333 | p = frag_more (i.vex.length); | |
7334 | for (j = 0; j < i.vex.length; j++) | |
7335 | p[j] = i.vex.bytes[j]; | |
7336 | } | |
252b5132 | 7337 | |
29b0f896 | 7338 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 7339 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
7340 | { |
7341 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
7342 | } | |
7343 | else | |
7344 | { | |
4dffcebc | 7345 | switch (i.tm.opcode_length) |
331d2d0d | 7346 | { |
43234a1e L |
7347 | case 4: |
7348 | p = frag_more (4); | |
7349 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
7350 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
7351 | break; | |
4dffcebc | 7352 | case 3: |
331d2d0d L |
7353 | p = frag_more (3); |
7354 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
7355 | break; |
7356 | case 2: | |
7357 | p = frag_more (2); | |
7358 | break; | |
7359 | default: | |
7360 | abort (); | |
7361 | break; | |
331d2d0d | 7362 | } |
0f10071e | 7363 | |
29b0f896 AM |
7364 | /* Put out high byte first: can't use md_number_to_chars! */ |
7365 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
7366 | *p = i.tm.base_opcode & 0xff; | |
7367 | } | |
3e73aa7c | 7368 | |
29b0f896 | 7369 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 7370 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 7371 | { |
4a3523fa L |
7372 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
7373 | | i.rm.reg << 3 | |
7374 | | i.rm.mode << 6)); | |
29b0f896 AM |
7375 | /* If i.rm.regmem == ESP (4) |
7376 | && i.rm.mode != (Register mode) | |
7377 | && not 16 bit | |
7378 | ==> need second modrm byte. */ | |
7379 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
7380 | && i.rm.mode != 3 | |
40fb9820 | 7381 | && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16)) |
4a3523fa L |
7382 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
7383 | | i.sib.index << 3 | |
7384 | | i.sib.scale << 6)); | |
29b0f896 | 7385 | } |
3e73aa7c | 7386 | |
29b0f896 | 7387 | if (i.disp_operands) |
2bbd9c25 | 7388 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 7389 | |
29b0f896 | 7390 | if (i.imm_operands) |
2bbd9c25 | 7391 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 7392 | } |
252b5132 | 7393 | |
29b0f896 AM |
7394 | #ifdef DEBUG386 |
7395 | if (flag_debug) | |
7396 | { | |
7b81dfbb | 7397 | pi ("" /*line*/, &i); |
29b0f896 AM |
7398 | } |
7399 | #endif /* DEBUG386 */ | |
7400 | } | |
252b5132 | 7401 | |
e205caa7 L |
7402 | /* Return the size of the displacement operand N. */ |
7403 | ||
7404 | static int | |
7405 | disp_size (unsigned int n) | |
7406 | { | |
7407 | int size = 4; | |
43234a1e L |
7408 | |
7409 | /* Vec_Disp8 has to be 8bit. */ | |
7410 | if (i.types[n].bitfield.vec_disp8) | |
7411 | size = 1; | |
7412 | else if (i.types[n].bitfield.disp64) | |
40fb9820 L |
7413 | size = 8; |
7414 | else if (i.types[n].bitfield.disp8) | |
7415 | size = 1; | |
7416 | else if (i.types[n].bitfield.disp16) | |
7417 | size = 2; | |
e205caa7 L |
7418 | return size; |
7419 | } | |
7420 | ||
7421 | /* Return the size of the immediate operand N. */ | |
7422 | ||
7423 | static int | |
7424 | imm_size (unsigned int n) | |
7425 | { | |
7426 | int size = 4; | |
40fb9820 L |
7427 | if (i.types[n].bitfield.imm64) |
7428 | size = 8; | |
7429 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
7430 | size = 1; | |
7431 | else if (i.types[n].bitfield.imm16) | |
7432 | size = 2; | |
e205caa7 L |
7433 | return size; |
7434 | } | |
7435 | ||
29b0f896 | 7436 | static void |
64e74474 | 7437 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
7438 | { |
7439 | char *p; | |
7440 | unsigned int n; | |
252b5132 | 7441 | |
29b0f896 AM |
7442 | for (n = 0; n < i.operands; n++) |
7443 | { | |
43234a1e L |
7444 | if (i.types[n].bitfield.vec_disp8 |
7445 | || operand_type_check (i.types[n], disp)) | |
29b0f896 AM |
7446 | { |
7447 | if (i.op[n].disps->X_op == O_constant) | |
7448 | { | |
e205caa7 | 7449 | int size = disp_size (n); |
43234a1e | 7450 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 7451 | |
43234a1e L |
7452 | if (i.types[n].bitfield.vec_disp8) |
7453 | val >>= i.memshift; | |
7454 | val = offset_in_range (val, size); | |
29b0f896 AM |
7455 | p = frag_more (size); |
7456 | md_number_to_chars (p, val, size); | |
7457 | } | |
7458 | else | |
7459 | { | |
f86103b7 | 7460 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 7461 | int size = disp_size (n); |
40fb9820 | 7462 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 7463 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 7464 | fixS *fixP; |
29b0f896 | 7465 | |
e205caa7 | 7466 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 7467 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 7468 | |
29b0f896 AM |
7469 | /* The PC relative address is computed relative |
7470 | to the instruction boundary, so in case immediate | |
7471 | fields follows, we need to adjust the value. */ | |
7472 | if (pcrel && i.imm_operands) | |
7473 | { | |
29b0f896 | 7474 | unsigned int n1; |
e205caa7 | 7475 | int sz = 0; |
252b5132 | 7476 | |
29b0f896 | 7477 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 7478 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 7479 | { |
e205caa7 L |
7480 | /* Only one immediate is allowed for PC |
7481 | relative address. */ | |
9c2799c2 | 7482 | gas_assert (sz == 0); |
e205caa7 L |
7483 | sz = imm_size (n1); |
7484 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 7485 | } |
29b0f896 | 7486 | /* We should find the immediate. */ |
9c2799c2 | 7487 | gas_assert (sz != 0); |
29b0f896 | 7488 | } |
520dc8e8 | 7489 | |
29b0f896 | 7490 | p = frag_more (size); |
d258b828 | 7491 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 7492 | if (GOT_symbol |
2bbd9c25 | 7493 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 7494 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
7495 | || reloc_type == BFD_RELOC_X86_64_32S |
7496 | || (reloc_type == BFD_RELOC_64 | |
7497 | && object_64bit)) | |
d6ab8113 JB |
7498 | && (i.op[n].disps->X_op == O_symbol |
7499 | || (i.op[n].disps->X_op == O_add | |
7500 | && ((symbol_get_value_expression | |
7501 | (i.op[n].disps->X_op_symbol)->X_op) | |
7502 | == O_subtract)))) | |
7503 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
7504 | { |
7505 | offsetT add; | |
7506 | ||
7507 | if (insn_start_frag == frag_now) | |
7508 | add = (p - frag_now->fr_literal) - insn_start_off; | |
7509 | else | |
7510 | { | |
7511 | fragS *fr; | |
7512 | ||
7513 | add = insn_start_frag->fr_fix - insn_start_off; | |
7514 | for (fr = insn_start_frag->fr_next; | |
7515 | fr && fr != frag_now; fr = fr->fr_next) | |
7516 | add += fr->fr_fix; | |
7517 | add += p - frag_now->fr_literal; | |
7518 | } | |
7519 | ||
4fa24527 | 7520 | if (!object_64bit) |
7b81dfbb AJ |
7521 | { |
7522 | reloc_type = BFD_RELOC_386_GOTPC; | |
7523 | i.op[n].imms->X_add_number += add; | |
7524 | } | |
7525 | else if (reloc_type == BFD_RELOC_64) | |
7526 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 7527 | else |
7b81dfbb AJ |
7528 | /* Don't do the adjustment for x86-64, as there |
7529 | the pcrel addressing is relative to the _next_ | |
7530 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 7531 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 7532 | } |
02a86693 L |
7533 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
7534 | size, i.op[n].disps, pcrel, | |
7535 | reloc_type); | |
7536 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
7537 | "test %reg, mem" and "binop mem, %reg" where binop | |
7538 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
0cb4071e L |
7539 | instructions. Always generate R_386_GOT32X for |
7540 | "sym*GOT" operand in 32-bit mode. */ | |
7541 | if ((generate_relax_relocations | |
7542 | || (!object_64bit | |
7543 | && i.rm.mode == 0 | |
7544 | && i.rm.regmem == 5)) | |
7545 | && (i.rm.mode == 2 | |
7546 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
02a86693 L |
7547 | && ((i.operands == 1 |
7548 | && i.tm.base_opcode == 0xff | |
7549 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
7550 | || (i.operands == 2 | |
7551 | && (i.tm.base_opcode == 0x8b | |
7552 | || i.tm.base_opcode == 0x85 | |
7553 | || (i.tm.base_opcode & 0xc7) == 0x03)))) | |
7554 | { | |
7555 | if (object_64bit) | |
7556 | { | |
7557 | fixP->fx_tcbit = i.rex != 0; | |
7558 | if (i.base_reg | |
7559 | && (i.base_reg->reg_num == RegRip | |
7560 | || i.base_reg->reg_num == RegEip)) | |
7561 | fixP->fx_tcbit2 = 1; | |
7562 | } | |
7563 | else | |
7564 | fixP->fx_tcbit2 = 1; | |
7565 | } | |
29b0f896 AM |
7566 | } |
7567 | } | |
7568 | } | |
7569 | } | |
252b5132 | 7570 | |
29b0f896 | 7571 | static void |
64e74474 | 7572 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
7573 | { |
7574 | char *p; | |
7575 | unsigned int n; | |
252b5132 | 7576 | |
29b0f896 AM |
7577 | for (n = 0; n < i.operands; n++) |
7578 | { | |
43234a1e L |
7579 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
7580 | if (i.rounding && (int) n == i.rounding->operand) | |
7581 | continue; | |
7582 | ||
40fb9820 | 7583 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
7584 | { |
7585 | if (i.op[n].imms->X_op == O_constant) | |
7586 | { | |
e205caa7 | 7587 | int size = imm_size (n); |
29b0f896 | 7588 | offsetT val; |
b4cac588 | 7589 | |
29b0f896 AM |
7590 | val = offset_in_range (i.op[n].imms->X_add_number, |
7591 | size); | |
7592 | p = frag_more (size); | |
7593 | md_number_to_chars (p, val, size); | |
7594 | } | |
7595 | else | |
7596 | { | |
7597 | /* Not absolute_section. | |
7598 | Need a 32-bit fixup (don't support 8bit | |
7599 | non-absolute imms). Try to support other | |
7600 | sizes ... */ | |
f86103b7 | 7601 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
7602 | int size = imm_size (n); |
7603 | int sign; | |
29b0f896 | 7604 | |
40fb9820 | 7605 | if (i.types[n].bitfield.imm32s |
a7d61044 | 7606 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 7607 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 7608 | sign = 1; |
e205caa7 L |
7609 | else |
7610 | sign = 0; | |
520dc8e8 | 7611 | |
29b0f896 | 7612 | p = frag_more (size); |
d258b828 | 7613 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 7614 | |
2bbd9c25 JJ |
7615 | /* This is tough to explain. We end up with this one if we |
7616 | * have operands that look like | |
7617 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
7618 | * obtain the absolute address of the GOT, and it is strongly | |
7619 | * preferable from a performance point of view to avoid using | |
7620 | * a runtime relocation for this. The actual sequence of | |
7621 | * instructions often look something like: | |
7622 | * | |
7623 | * call .L66 | |
7624 | * .L66: | |
7625 | * popl %ebx | |
7626 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
7627 | * | |
7628 | * The call and pop essentially return the absolute address | |
7629 | * of the label .L66 and store it in %ebx. The linker itself | |
7630 | * will ultimately change the first operand of the addl so | |
7631 | * that %ebx points to the GOT, but to keep things simple, the | |
7632 | * .o file must have this operand set so that it generates not | |
7633 | * the absolute address of .L66, but the absolute address of | |
7634 | * itself. This allows the linker itself simply treat a GOTPC | |
7635 | * relocation as asking for a pcrel offset to the GOT to be | |
7636 | * added in, and the addend of the relocation is stored in the | |
7637 | * operand field for the instruction itself. | |
7638 | * | |
7639 | * Our job here is to fix the operand so that it would add | |
7640 | * the correct offset so that %ebx would point to itself. The | |
7641 | * thing that is tricky is that .-.L66 will point to the | |
7642 | * beginning of the instruction, so we need to further modify | |
7643 | * the operand so that it will point to itself. There are | |
7644 | * other cases where you have something like: | |
7645 | * | |
7646 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
7647 | * | |
7648 | * and here no correction would be required. Internally in | |
7649 | * the assembler we treat operands of this form as not being | |
7650 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
7651 | * whether it would simplify matters to do it this way. Who | |
7652 | * knows. In earlier versions of the PIC patches, the | |
7653 | * pcrel_adjust field was used to store the correction, but | |
7654 | * since the expression is not pcrel, I felt it would be | |
7655 | * confusing to do it this way. */ | |
7656 | ||
d6ab8113 | 7657 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
7658 | || reloc_type == BFD_RELOC_X86_64_32S |
7659 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
7660 | && GOT_symbol |
7661 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
7662 | && (i.op[n].imms->X_op == O_symbol | |
7663 | || (i.op[n].imms->X_op == O_add | |
7664 | && ((symbol_get_value_expression | |
7665 | (i.op[n].imms->X_op_symbol)->X_op) | |
7666 | == O_subtract)))) | |
7667 | { | |
2bbd9c25 JJ |
7668 | offsetT add; |
7669 | ||
7670 | if (insn_start_frag == frag_now) | |
7671 | add = (p - frag_now->fr_literal) - insn_start_off; | |
7672 | else | |
7673 | { | |
7674 | fragS *fr; | |
7675 | ||
7676 | add = insn_start_frag->fr_fix - insn_start_off; | |
7677 | for (fr = insn_start_frag->fr_next; | |
7678 | fr && fr != frag_now; fr = fr->fr_next) | |
7679 | add += fr->fr_fix; | |
7680 | add += p - frag_now->fr_literal; | |
7681 | } | |
7682 | ||
4fa24527 | 7683 | if (!object_64bit) |
d6ab8113 | 7684 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 7685 | else if (size == 4) |
d6ab8113 | 7686 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
7687 | else if (size == 8) |
7688 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 7689 | i.op[n].imms->X_add_number += add; |
29b0f896 | 7690 | } |
29b0f896 AM |
7691 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
7692 | i.op[n].imms, 0, reloc_type); | |
7693 | } | |
7694 | } | |
7695 | } | |
252b5132 RH |
7696 | } |
7697 | \f | |
d182319b JB |
7698 | /* x86_cons_fix_new is called via the expression parsing code when a |
7699 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
7700 | static int cons_sign = -1; |
7701 | ||
7702 | void | |
e3bb37b5 | 7703 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 7704 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 7705 | { |
d258b828 | 7706 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
7707 | |
7708 | #ifdef TE_PE | |
7709 | if (exp->X_op == O_secrel) | |
7710 | { | |
7711 | exp->X_op = O_symbol; | |
7712 | r = BFD_RELOC_32_SECREL; | |
7713 | } | |
7714 | #endif | |
7715 | ||
7716 | fix_new_exp (frag, off, len, exp, 0, r); | |
7717 | } | |
7718 | ||
357d1bd8 L |
7719 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
7720 | purpose of the `.dc.a' internal pseudo-op. */ | |
7721 | ||
7722 | int | |
7723 | x86_address_bytes (void) | |
7724 | { | |
7725 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
7726 | return 4; | |
7727 | return stdoutput->arch_info->bits_per_address / 8; | |
7728 | } | |
7729 | ||
d382c579 TG |
7730 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
7731 | || defined (LEX_AT) | |
d258b828 | 7732 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 7733 | #else |
f3c180ae AM |
7734 | /* Parse operands of the form |
7735 | <symbol>@GOTOFF+<nnn> | |
7736 | and similar .plt or .got references. | |
7737 | ||
7738 | If we find one, set up the correct relocation in RELOC and copy the | |
7739 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
7740 | parsing by the calling routine. Return this buffer, and if ADJUST | |
7741 | is non-null set it to the length of the string we removed from the | |
7742 | input line. Otherwise return NULL. */ | |
7743 | static char * | |
91d6fa6a | 7744 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 7745 | int *adjust, |
d258b828 | 7746 | i386_operand_type *types) |
f3c180ae | 7747 | { |
7b81dfbb AJ |
7748 | /* Some of the relocations depend on the size of what field is to |
7749 | be relocated. But in our callers i386_immediate and i386_displacement | |
7750 | we don't yet know the operand size (this will be set by insn | |
7751 | matching). Hence we record the word32 relocation here, | |
7752 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
7753 | static const struct { |
7754 | const char *str; | |
cff8d58a | 7755 | int len; |
4fa24527 | 7756 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 7757 | const i386_operand_type types64; |
f3c180ae | 7758 | } gotrel[] = { |
8ce3d284 | 7759 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
7760 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
7761 | BFD_RELOC_SIZE32 }, | |
7762 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 7763 | #endif |
cff8d58a L |
7764 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
7765 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 7766 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
7767 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
7768 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 7769 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7770 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
7771 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 7772 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
7773 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
7774 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 7775 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
7776 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
7777 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 7778 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7779 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
7780 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 7781 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7782 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
7783 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7784 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7785 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
7786 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 7787 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7788 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
7789 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 7790 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7791 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
7792 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 7793 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
7794 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
7795 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7796 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7797 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
7798 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 7799 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
7800 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
7801 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7802 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7803 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
7804 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7805 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7806 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
7807 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 7808 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
7809 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
7810 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 7811 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7812 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
7813 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 7814 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
7815 | }; |
7816 | char *cp; | |
7817 | unsigned int j; | |
7818 | ||
d382c579 | 7819 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
7820 | if (!IS_ELF) |
7821 | return NULL; | |
d382c579 | 7822 | #endif |
718ddfc0 | 7823 | |
f3c180ae | 7824 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 7825 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
7826 | return NULL; |
7827 | ||
47465058 | 7828 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 7829 | { |
cff8d58a | 7830 | int len = gotrel[j].len; |
28f81592 | 7831 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 7832 | { |
4fa24527 | 7833 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 7834 | { |
28f81592 AM |
7835 | int first, second; |
7836 | char *tmpbuf, *past_reloc; | |
f3c180ae | 7837 | |
91d6fa6a | 7838 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 7839 | |
3956db08 JB |
7840 | if (types) |
7841 | { | |
7842 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
7843 | { |
7844 | types->bitfield.imm32 = 1; | |
7845 | types->bitfield.disp32 = 1; | |
7846 | } | |
3956db08 JB |
7847 | else |
7848 | *types = gotrel[j].types64; | |
7849 | } | |
7850 | ||
8fd4256d | 7851 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
7852 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
7853 | ||
28f81592 | 7854 | /* The length of the first part of our input line. */ |
f3c180ae | 7855 | first = cp - input_line_pointer; |
28f81592 AM |
7856 | |
7857 | /* The second part goes from after the reloc token until | |
67c11a9b | 7858 | (and including) an end_of_line char or comma. */ |
28f81592 | 7859 | past_reloc = cp + 1 + len; |
67c11a9b AM |
7860 | cp = past_reloc; |
7861 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
7862 | ++cp; | |
7863 | second = cp + 1 - past_reloc; | |
28f81592 AM |
7864 | |
7865 | /* Allocate and copy string. The trailing NUL shouldn't | |
7866 | be necessary, but be safe. */ | |
add39d23 | 7867 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 7868 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
7869 | if (second != 0 && *past_reloc != ' ') |
7870 | /* Replace the relocation token with ' ', so that | |
7871 | errors like foo@GOTOFF1 will be detected. */ | |
7872 | tmpbuf[first++] = ' '; | |
af89796a L |
7873 | else |
7874 | /* Increment length by 1 if the relocation token is | |
7875 | removed. */ | |
7876 | len++; | |
7877 | if (adjust) | |
7878 | *adjust = len; | |
0787a12d AM |
7879 | memcpy (tmpbuf + first, past_reloc, second); |
7880 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
7881 | return tmpbuf; |
7882 | } | |
7883 | ||
4fa24527 JB |
7884 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
7885 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
7886 | return NULL; |
7887 | } | |
7888 | } | |
7889 | ||
7890 | /* Might be a symbol version string. Don't as_bad here. */ | |
7891 | return NULL; | |
7892 | } | |
4e4f7c87 | 7893 | #endif |
f3c180ae | 7894 | |
a988325c NC |
7895 | #ifdef TE_PE |
7896 | #ifdef lex_got | |
7897 | #undef lex_got | |
7898 | #endif | |
7899 | /* Parse operands of the form | |
7900 | <symbol>@SECREL32+<nnn> | |
7901 | ||
7902 | If we find one, set up the correct relocation in RELOC and copy the | |
7903 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
7904 | parsing by the calling routine. Return this buffer, and if ADJUST | |
7905 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
7906 | input line. Otherwise return NULL. |
7907 | ||
a988325c NC |
7908 | This function is copied from the ELF version above adjusted for PE targets. */ |
7909 | ||
7910 | static char * | |
7911 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
7912 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 7913 | i386_operand_type *types) |
a988325c NC |
7914 | { |
7915 | static const struct | |
7916 | { | |
7917 | const char *str; | |
7918 | int len; | |
7919 | const enum bfd_reloc_code_real rel[2]; | |
7920 | const i386_operand_type types64; | |
7921 | } | |
7922 | gotrel[] = | |
7923 | { | |
7924 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
7925 | BFD_RELOC_32_SECREL }, | |
7926 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
7927 | }; | |
7928 | ||
7929 | char *cp; | |
7930 | unsigned j; | |
7931 | ||
7932 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
7933 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
7934 | return NULL; | |
7935 | ||
7936 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
7937 | { | |
7938 | int len = gotrel[j].len; | |
7939 | ||
7940 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
7941 | { | |
7942 | if (gotrel[j].rel[object_64bit] != 0) | |
7943 | { | |
7944 | int first, second; | |
7945 | char *tmpbuf, *past_reloc; | |
7946 | ||
7947 | *rel = gotrel[j].rel[object_64bit]; | |
7948 | if (adjust) | |
7949 | *adjust = len; | |
7950 | ||
7951 | if (types) | |
7952 | { | |
7953 | if (flag_code != CODE_64BIT) | |
7954 | { | |
7955 | types->bitfield.imm32 = 1; | |
7956 | types->bitfield.disp32 = 1; | |
7957 | } | |
7958 | else | |
7959 | *types = gotrel[j].types64; | |
7960 | } | |
7961 | ||
7962 | /* The length of the first part of our input line. */ | |
7963 | first = cp - input_line_pointer; | |
7964 | ||
7965 | /* The second part goes from after the reloc token until | |
7966 | (and including) an end_of_line char or comma. */ | |
7967 | past_reloc = cp + 1 + len; | |
7968 | cp = past_reloc; | |
7969 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
7970 | ++cp; | |
7971 | second = cp + 1 - past_reloc; | |
7972 | ||
7973 | /* Allocate and copy string. The trailing NUL shouldn't | |
7974 | be necessary, but be safe. */ | |
add39d23 | 7975 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
7976 | memcpy (tmpbuf, input_line_pointer, first); |
7977 | if (second != 0 && *past_reloc != ' ') | |
7978 | /* Replace the relocation token with ' ', so that | |
7979 | errors like foo@SECLREL321 will be detected. */ | |
7980 | tmpbuf[first++] = ' '; | |
7981 | memcpy (tmpbuf + first, past_reloc, second); | |
7982 | tmpbuf[first + second] = '\0'; | |
7983 | return tmpbuf; | |
7984 | } | |
7985 | ||
7986 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
7987 | gotrel[j].str, 1 << (5 + object_64bit)); | |
7988 | return NULL; | |
7989 | } | |
7990 | } | |
7991 | ||
7992 | /* Might be a symbol version string. Don't as_bad here. */ | |
7993 | return NULL; | |
7994 | } | |
7995 | ||
7996 | #endif /* TE_PE */ | |
7997 | ||
62ebcb5c | 7998 | bfd_reloc_code_real_type |
e3bb37b5 | 7999 | x86_cons (expressionS *exp, int size) |
f3c180ae | 8000 | { |
62ebcb5c AM |
8001 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
8002 | ||
ee86248c JB |
8003 | intel_syntax = -intel_syntax; |
8004 | ||
3c7b9c2c | 8005 | exp->X_md = 0; |
4fa24527 | 8006 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
8007 | { |
8008 | /* Handle @GOTOFF and the like in an expression. */ | |
8009 | char *save; | |
8010 | char *gotfree_input_line; | |
4a57f2cf | 8011 | int adjust = 0; |
f3c180ae AM |
8012 | |
8013 | save = input_line_pointer; | |
d258b828 | 8014 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
8015 | if (gotfree_input_line) |
8016 | input_line_pointer = gotfree_input_line; | |
8017 | ||
8018 | expression (exp); | |
8019 | ||
8020 | if (gotfree_input_line) | |
8021 | { | |
8022 | /* expression () has merrily parsed up to the end of line, | |
8023 | or a comma - in the wrong buffer. Transfer how far | |
8024 | input_line_pointer has moved to the right buffer. */ | |
8025 | input_line_pointer = (save | |
8026 | + (input_line_pointer - gotfree_input_line) | |
8027 | + adjust); | |
8028 | free (gotfree_input_line); | |
3992d3b7 AM |
8029 | if (exp->X_op == O_constant |
8030 | || exp->X_op == O_absent | |
8031 | || exp->X_op == O_illegal | |
0398aac5 | 8032 | || exp->X_op == O_register |
3992d3b7 AM |
8033 | || exp->X_op == O_big) |
8034 | { | |
8035 | char c = *input_line_pointer; | |
8036 | *input_line_pointer = 0; | |
8037 | as_bad (_("missing or invalid expression `%s'"), save); | |
8038 | *input_line_pointer = c; | |
8039 | } | |
f3c180ae AM |
8040 | } |
8041 | } | |
8042 | else | |
8043 | expression (exp); | |
ee86248c JB |
8044 | |
8045 | intel_syntax = -intel_syntax; | |
8046 | ||
8047 | if (intel_syntax) | |
8048 | i386_intel_simplify (exp); | |
62ebcb5c AM |
8049 | |
8050 | return got_reloc; | |
f3c180ae | 8051 | } |
f3c180ae | 8052 | |
9f32dd5b L |
8053 | static void |
8054 | signed_cons (int size) | |
6482c264 | 8055 | { |
d182319b JB |
8056 | if (flag_code == CODE_64BIT) |
8057 | cons_sign = 1; | |
8058 | cons (size); | |
8059 | cons_sign = -1; | |
6482c264 NC |
8060 | } |
8061 | ||
d182319b | 8062 | #ifdef TE_PE |
6482c264 | 8063 | static void |
7016a5d5 | 8064 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
8065 | { |
8066 | expressionS exp; | |
8067 | ||
8068 | do | |
8069 | { | |
8070 | expression (&exp); | |
8071 | if (exp.X_op == O_symbol) | |
8072 | exp.X_op = O_secrel; | |
8073 | ||
8074 | emit_expr (&exp, 4); | |
8075 | } | |
8076 | while (*input_line_pointer++ == ','); | |
8077 | ||
8078 | input_line_pointer--; | |
8079 | demand_empty_rest_of_line (); | |
8080 | } | |
6482c264 NC |
8081 | #endif |
8082 | ||
43234a1e L |
8083 | /* Handle Vector operations. */ |
8084 | ||
8085 | static char * | |
8086 | check_VecOperations (char *op_string, char *op_end) | |
8087 | { | |
8088 | const reg_entry *mask; | |
8089 | const char *saved; | |
8090 | char *end_op; | |
8091 | ||
8092 | while (*op_string | |
8093 | && (op_end == NULL || op_string < op_end)) | |
8094 | { | |
8095 | saved = op_string; | |
8096 | if (*op_string == '{') | |
8097 | { | |
8098 | op_string++; | |
8099 | ||
8100 | /* Check broadcasts. */ | |
8101 | if (strncmp (op_string, "1to", 3) == 0) | |
8102 | { | |
8103 | int bcst_type; | |
8104 | ||
8105 | if (i.broadcast) | |
8106 | goto duplicated_vec_op; | |
8107 | ||
8108 | op_string += 3; | |
8109 | if (*op_string == '8') | |
8110 | bcst_type = BROADCAST_1TO8; | |
b28d1bda IT |
8111 | else if (*op_string == '4') |
8112 | bcst_type = BROADCAST_1TO4; | |
8113 | else if (*op_string == '2') | |
8114 | bcst_type = BROADCAST_1TO2; | |
43234a1e L |
8115 | else if (*op_string == '1' |
8116 | && *(op_string+1) == '6') | |
8117 | { | |
8118 | bcst_type = BROADCAST_1TO16; | |
8119 | op_string++; | |
8120 | } | |
8121 | else | |
8122 | { | |
8123 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
8124 | return NULL; | |
8125 | } | |
8126 | op_string++; | |
8127 | ||
8128 | broadcast_op.type = bcst_type; | |
8129 | broadcast_op.operand = this_operand; | |
8130 | i.broadcast = &broadcast_op; | |
8131 | } | |
8132 | /* Check masking operation. */ | |
8133 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
8134 | { | |
8135 | /* k0 can't be used for write mask. */ | |
8136 | if (mask->reg_num == 0) | |
8137 | { | |
8138 | as_bad (_("`%s' can't be used for write mask"), | |
8139 | op_string); | |
8140 | return NULL; | |
8141 | } | |
8142 | ||
8143 | if (!i.mask) | |
8144 | { | |
8145 | mask_op.mask = mask; | |
8146 | mask_op.zeroing = 0; | |
8147 | mask_op.operand = this_operand; | |
8148 | i.mask = &mask_op; | |
8149 | } | |
8150 | else | |
8151 | { | |
8152 | if (i.mask->mask) | |
8153 | goto duplicated_vec_op; | |
8154 | ||
8155 | i.mask->mask = mask; | |
8156 | ||
8157 | /* Only "{z}" is allowed here. No need to check | |
8158 | zeroing mask explicitly. */ | |
8159 | if (i.mask->operand != this_operand) | |
8160 | { | |
8161 | as_bad (_("invalid write mask `%s'"), saved); | |
8162 | return NULL; | |
8163 | } | |
8164 | } | |
8165 | ||
8166 | op_string = end_op; | |
8167 | } | |
8168 | /* Check zeroing-flag for masking operation. */ | |
8169 | else if (*op_string == 'z') | |
8170 | { | |
8171 | if (!i.mask) | |
8172 | { | |
8173 | mask_op.mask = NULL; | |
8174 | mask_op.zeroing = 1; | |
8175 | mask_op.operand = this_operand; | |
8176 | i.mask = &mask_op; | |
8177 | } | |
8178 | else | |
8179 | { | |
8180 | if (i.mask->zeroing) | |
8181 | { | |
8182 | duplicated_vec_op: | |
8183 | as_bad (_("duplicated `%s'"), saved); | |
8184 | return NULL; | |
8185 | } | |
8186 | ||
8187 | i.mask->zeroing = 1; | |
8188 | ||
8189 | /* Only "{%k}" is allowed here. No need to check mask | |
8190 | register explicitly. */ | |
8191 | if (i.mask->operand != this_operand) | |
8192 | { | |
8193 | as_bad (_("invalid zeroing-masking `%s'"), | |
8194 | saved); | |
8195 | return NULL; | |
8196 | } | |
8197 | } | |
8198 | ||
8199 | op_string++; | |
8200 | } | |
8201 | else | |
8202 | goto unknown_vec_op; | |
8203 | ||
8204 | if (*op_string != '}') | |
8205 | { | |
8206 | as_bad (_("missing `}' in `%s'"), saved); | |
8207 | return NULL; | |
8208 | } | |
8209 | op_string++; | |
8210 | continue; | |
8211 | } | |
8212 | unknown_vec_op: | |
8213 | /* We don't know this one. */ | |
8214 | as_bad (_("unknown vector operation: `%s'"), saved); | |
8215 | return NULL; | |
8216 | } | |
8217 | ||
8218 | return op_string; | |
8219 | } | |
8220 | ||
252b5132 | 8221 | static int |
70e41ade | 8222 | i386_immediate (char *imm_start) |
252b5132 RH |
8223 | { |
8224 | char *save_input_line_pointer; | |
f3c180ae | 8225 | char *gotfree_input_line; |
252b5132 | 8226 | segT exp_seg = 0; |
47926f60 | 8227 | expressionS *exp; |
40fb9820 L |
8228 | i386_operand_type types; |
8229 | ||
0dfbf9d7 | 8230 | operand_type_set (&types, ~0); |
252b5132 RH |
8231 | |
8232 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
8233 | { | |
31b2323c L |
8234 | as_bad (_("at most %d immediate operands are allowed"), |
8235 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
8236 | return 0; |
8237 | } | |
8238 | ||
8239 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 8240 | i.op[this_operand].imms = exp; |
252b5132 RH |
8241 | |
8242 | if (is_space_char (*imm_start)) | |
8243 | ++imm_start; | |
8244 | ||
8245 | save_input_line_pointer = input_line_pointer; | |
8246 | input_line_pointer = imm_start; | |
8247 | ||
d258b828 | 8248 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
8249 | if (gotfree_input_line) |
8250 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
8251 | |
8252 | exp_seg = expression (exp); | |
8253 | ||
83183c0c | 8254 | SKIP_WHITESPACE (); |
43234a1e L |
8255 | |
8256 | /* Handle vector operations. */ | |
8257 | if (*input_line_pointer == '{') | |
8258 | { | |
8259 | input_line_pointer = check_VecOperations (input_line_pointer, | |
8260 | NULL); | |
8261 | if (input_line_pointer == NULL) | |
8262 | return 0; | |
8263 | } | |
8264 | ||
252b5132 | 8265 | if (*input_line_pointer) |
f3c180ae | 8266 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
8267 | |
8268 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 8269 | if (gotfree_input_line) |
ee86248c JB |
8270 | { |
8271 | free (gotfree_input_line); | |
8272 | ||
8273 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
8274 | exp->X_op = O_illegal; | |
8275 | } | |
8276 | ||
8277 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
8278 | } | |
252b5132 | 8279 | |
ee86248c JB |
8280 | static int |
8281 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
8282 | i386_operand_type types, const char *imm_start) | |
8283 | { | |
8284 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 8285 | { |
313c53d1 L |
8286 | if (imm_start) |
8287 | as_bad (_("missing or invalid immediate expression `%s'"), | |
8288 | imm_start); | |
3992d3b7 | 8289 | return 0; |
252b5132 | 8290 | } |
3e73aa7c | 8291 | else if (exp->X_op == O_constant) |
252b5132 | 8292 | { |
47926f60 | 8293 | /* Size it properly later. */ |
40fb9820 | 8294 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
8295 | /* If not 64bit, sign extend val. */ |
8296 | if (flag_code != CODE_64BIT | |
4eed87de AM |
8297 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
8298 | exp->X_add_number | |
8299 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 8300 | } |
4c63da97 | 8301 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 8302 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 8303 | && exp_seg != absolute_section |
47926f60 | 8304 | && exp_seg != text_section |
24eab124 AM |
8305 | && exp_seg != data_section |
8306 | && exp_seg != bss_section | |
8307 | && exp_seg != undefined_section | |
f86103b7 | 8308 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 8309 | { |
d0b47220 | 8310 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
8311 | return 0; |
8312 | } | |
8313 | #endif | |
a841bdf5 | 8314 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 8315 | { |
313c53d1 L |
8316 | if (imm_start) |
8317 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
8318 | return 0; |
8319 | } | |
252b5132 RH |
8320 | else |
8321 | { | |
8322 | /* This is an address. The size of the address will be | |
24eab124 | 8323 | determined later, depending on destination register, |
3e73aa7c | 8324 | suffix, or the default for the section. */ |
40fb9820 L |
8325 | i.types[this_operand].bitfield.imm8 = 1; |
8326 | i.types[this_operand].bitfield.imm16 = 1; | |
8327 | i.types[this_operand].bitfield.imm32 = 1; | |
8328 | i.types[this_operand].bitfield.imm32s = 1; | |
8329 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
8330 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
8331 | types); | |
252b5132 RH |
8332 | } |
8333 | ||
8334 | return 1; | |
8335 | } | |
8336 | ||
551c1ca1 | 8337 | static char * |
e3bb37b5 | 8338 | i386_scale (char *scale) |
252b5132 | 8339 | { |
551c1ca1 AM |
8340 | offsetT val; |
8341 | char *save = input_line_pointer; | |
252b5132 | 8342 | |
551c1ca1 AM |
8343 | input_line_pointer = scale; |
8344 | val = get_absolute_expression (); | |
8345 | ||
8346 | switch (val) | |
252b5132 | 8347 | { |
551c1ca1 | 8348 | case 1: |
252b5132 RH |
8349 | i.log2_scale_factor = 0; |
8350 | break; | |
551c1ca1 | 8351 | case 2: |
252b5132 RH |
8352 | i.log2_scale_factor = 1; |
8353 | break; | |
551c1ca1 | 8354 | case 4: |
252b5132 RH |
8355 | i.log2_scale_factor = 2; |
8356 | break; | |
551c1ca1 | 8357 | case 8: |
252b5132 RH |
8358 | i.log2_scale_factor = 3; |
8359 | break; | |
8360 | default: | |
a724f0f4 JB |
8361 | { |
8362 | char sep = *input_line_pointer; | |
8363 | ||
8364 | *input_line_pointer = '\0'; | |
8365 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
8366 | scale); | |
8367 | *input_line_pointer = sep; | |
8368 | input_line_pointer = save; | |
8369 | return NULL; | |
8370 | } | |
252b5132 | 8371 | } |
29b0f896 | 8372 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
8373 | { |
8374 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 8375 | 1 << i.log2_scale_factor); |
252b5132 | 8376 | i.log2_scale_factor = 0; |
252b5132 | 8377 | } |
551c1ca1 AM |
8378 | scale = input_line_pointer; |
8379 | input_line_pointer = save; | |
8380 | return scale; | |
252b5132 RH |
8381 | } |
8382 | ||
252b5132 | 8383 | static int |
e3bb37b5 | 8384 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 8385 | { |
29b0f896 | 8386 | expressionS *exp; |
252b5132 RH |
8387 | segT exp_seg = 0; |
8388 | char *save_input_line_pointer; | |
f3c180ae | 8389 | char *gotfree_input_line; |
40fb9820 L |
8390 | int override; |
8391 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 8392 | int ret; |
252b5132 | 8393 | |
31b2323c L |
8394 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
8395 | { | |
8396 | as_bad (_("at most %d displacement operands are allowed"), | |
8397 | MAX_MEMORY_OPERANDS); | |
8398 | return 0; | |
8399 | } | |
8400 | ||
0dfbf9d7 | 8401 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
8402 | if ((i.types[this_operand].bitfield.jumpabsolute) |
8403 | || (!current_templates->start->opcode_modifier.jump | |
8404 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 8405 | { |
40fb9820 | 8406 | bigdisp.bitfield.disp32 = 1; |
e05278af | 8407 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
8408 | if (flag_code == CODE_64BIT) |
8409 | { | |
8410 | if (!override) | |
8411 | { | |
8412 | bigdisp.bitfield.disp32s = 1; | |
8413 | bigdisp.bitfield.disp64 = 1; | |
8414 | } | |
8415 | } | |
8416 | else if ((flag_code == CODE_16BIT) ^ override) | |
8417 | { | |
8418 | bigdisp.bitfield.disp32 = 0; | |
8419 | bigdisp.bitfield.disp16 = 1; | |
8420 | } | |
e05278af JB |
8421 | } |
8422 | else | |
8423 | { | |
8424 | /* For PC-relative branches, the width of the displacement | |
8425 | is dependent upon data size, not address size. */ | |
e05278af | 8426 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
8427 | if (flag_code == CODE_64BIT) |
8428 | { | |
8429 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
8430 | bigdisp.bitfield.disp16 = 1; | |
8431 | else | |
8432 | { | |
8433 | bigdisp.bitfield.disp32 = 1; | |
8434 | bigdisp.bitfield.disp32s = 1; | |
8435 | } | |
8436 | } | |
8437 | else | |
e05278af JB |
8438 | { |
8439 | if (!override) | |
8440 | override = (i.suffix == (flag_code != CODE_16BIT | |
8441 | ? WORD_MNEM_SUFFIX | |
8442 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
8443 | bigdisp.bitfield.disp32 = 1; |
8444 | if ((flag_code == CODE_16BIT) ^ override) | |
8445 | { | |
8446 | bigdisp.bitfield.disp32 = 0; | |
8447 | bigdisp.bitfield.disp16 = 1; | |
8448 | } | |
e05278af | 8449 | } |
e05278af | 8450 | } |
c6fb90c8 L |
8451 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
8452 | bigdisp); | |
252b5132 RH |
8453 | |
8454 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 8455 | i.op[this_operand].disps = exp; |
252b5132 RH |
8456 | i.disp_operands++; |
8457 | save_input_line_pointer = input_line_pointer; | |
8458 | input_line_pointer = disp_start; | |
8459 | END_STRING_AND_SAVE (disp_end); | |
8460 | ||
8461 | #ifndef GCC_ASM_O_HACK | |
8462 | #define GCC_ASM_O_HACK 0 | |
8463 | #endif | |
8464 | #if GCC_ASM_O_HACK | |
8465 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 8466 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 8467 | && displacement_string_end[-1] == '+') |
252b5132 RH |
8468 | { |
8469 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
8470 | constraint within gcc asm statements. |
8471 | For instance: | |
8472 | ||
8473 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
8474 | __asm__ __volatile__ ( \ | |
8475 | "movw %w2,%0\n\t" \ | |
8476 | "movw %w1,2+%0\n\t" \ | |
8477 | "rorl $16,%1\n\t" \ | |
8478 | "movb %b1,4+%0\n\t" \ | |
8479 | "movb %4,5+%0\n\t" \ | |
8480 | "movb $0,6+%0\n\t" \ | |
8481 | "movb %h1,7+%0\n\t" \ | |
8482 | "rorl $16,%1" \ | |
8483 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
8484 | ||
8485 | This works great except that the output assembler ends | |
8486 | up looking a bit weird if it turns out that there is | |
8487 | no offset. You end up producing code that looks like: | |
8488 | ||
8489 | #APP | |
8490 | movw $235,(%eax) | |
8491 | movw %dx,2+(%eax) | |
8492 | rorl $16,%edx | |
8493 | movb %dl,4+(%eax) | |
8494 | movb $137,5+(%eax) | |
8495 | movb $0,6+(%eax) | |
8496 | movb %dh,7+(%eax) | |
8497 | rorl $16,%edx | |
8498 | #NO_APP | |
8499 | ||
47926f60 | 8500 | So here we provide the missing zero. */ |
24eab124 AM |
8501 | |
8502 | *displacement_string_end = '0'; | |
252b5132 RH |
8503 | } |
8504 | #endif | |
d258b828 | 8505 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
8506 | if (gotfree_input_line) |
8507 | input_line_pointer = gotfree_input_line; | |
252b5132 | 8508 | |
24eab124 | 8509 | exp_seg = expression (exp); |
252b5132 | 8510 | |
636c26b0 AM |
8511 | SKIP_WHITESPACE (); |
8512 | if (*input_line_pointer) | |
8513 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
8514 | #if GCC_ASM_O_HACK | |
8515 | RESTORE_END_STRING (disp_end + 1); | |
8516 | #endif | |
636c26b0 | 8517 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 8518 | if (gotfree_input_line) |
ee86248c JB |
8519 | { |
8520 | free (gotfree_input_line); | |
8521 | ||
8522 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
8523 | exp->X_op = O_illegal; | |
8524 | } | |
8525 | ||
8526 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
8527 | ||
8528 | RESTORE_END_STRING (disp_end); | |
8529 | ||
8530 | return ret; | |
8531 | } | |
8532 | ||
8533 | static int | |
8534 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
8535 | i386_operand_type types, const char *disp_start) | |
8536 | { | |
8537 | i386_operand_type bigdisp; | |
8538 | int ret = 1; | |
636c26b0 | 8539 | |
24eab124 AM |
8540 | /* We do this to make sure that the section symbol is in |
8541 | the symbol table. We will ultimately change the relocation | |
47926f60 | 8542 | to be relative to the beginning of the section. */ |
1ae12ab7 | 8543 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
8544 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
8545 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 8546 | { |
636c26b0 | 8547 | if (exp->X_op != O_symbol) |
3992d3b7 | 8548 | goto inv_disp; |
636c26b0 | 8549 | |
e5cb08ac | 8550 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
8551 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
8552 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 8553 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
8554 | exp->X_op = O_subtract; |
8555 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 8556 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 8557 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
8558 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
8559 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 8560 | else |
29b0f896 | 8561 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 8562 | } |
252b5132 | 8563 | |
3992d3b7 AM |
8564 | else if (exp->X_op == O_absent |
8565 | || exp->X_op == O_illegal | |
ee86248c | 8566 | || exp->X_op == O_big) |
2daf4fd8 | 8567 | { |
3992d3b7 AM |
8568 | inv_disp: |
8569 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 8570 | disp_start); |
3992d3b7 | 8571 | ret = 0; |
2daf4fd8 AM |
8572 | } |
8573 | ||
0e1147d9 L |
8574 | else if (flag_code == CODE_64BIT |
8575 | && !i.prefix[ADDR_PREFIX] | |
8576 | && exp->X_op == O_constant) | |
8577 | { | |
8578 | /* Since displacement is signed extended to 64bit, don't allow | |
8579 | disp32 and turn off disp32s if they are out of range. */ | |
8580 | i.types[this_operand].bitfield.disp32 = 0; | |
8581 | if (!fits_in_signed_long (exp->X_add_number)) | |
8582 | { | |
8583 | i.types[this_operand].bitfield.disp32s = 0; | |
8584 | if (i.types[this_operand].bitfield.baseindex) | |
8585 | { | |
8586 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
8587 | (long) exp->X_add_number); | |
8588 | ret = 0; | |
8589 | } | |
8590 | } | |
8591 | } | |
8592 | ||
4c63da97 | 8593 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
8594 | else if (exp->X_op != O_constant |
8595 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
8596 | && exp_seg != absolute_section | |
8597 | && exp_seg != text_section | |
8598 | && exp_seg != data_section | |
8599 | && exp_seg != bss_section | |
8600 | && exp_seg != undefined_section | |
8601 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 8602 | { |
d0b47220 | 8603 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 8604 | ret = 0; |
24eab124 | 8605 | } |
252b5132 | 8606 | #endif |
3956db08 | 8607 | |
40fb9820 L |
8608 | /* Check if this is a displacement only operand. */ |
8609 | bigdisp = i.types[this_operand]; | |
8610 | bigdisp.bitfield.disp8 = 0; | |
8611 | bigdisp.bitfield.disp16 = 0; | |
8612 | bigdisp.bitfield.disp32 = 0; | |
8613 | bigdisp.bitfield.disp32s = 0; | |
8614 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 8615 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
8616 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
8617 | types); | |
3956db08 | 8618 | |
3992d3b7 | 8619 | return ret; |
252b5132 RH |
8620 | } |
8621 | ||
eecb386c | 8622 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
8623 | Return 1 on success, 0 on a failure. */ |
8624 | ||
252b5132 | 8625 | static int |
e3bb37b5 | 8626 | i386_index_check (const char *operand_string) |
252b5132 | 8627 | { |
fc0763e6 | 8628 | const char *kind = "base/index"; |
be05d201 L |
8629 | enum flag_code addr_mode; |
8630 | ||
8631 | if (i.prefix[ADDR_PREFIX]) | |
8632 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
8633 | else | |
8634 | { | |
8635 | addr_mode = flag_code; | |
8636 | ||
24eab124 | 8637 | #if INFER_ADDR_PREFIX |
be05d201 L |
8638 | if (i.mem_operands == 0) |
8639 | { | |
8640 | /* Infer address prefix from the first memory operand. */ | |
8641 | const reg_entry *addr_reg = i.base_reg; | |
8642 | ||
8643 | if (addr_reg == NULL) | |
8644 | addr_reg = i.index_reg; | |
eecb386c | 8645 | |
be05d201 L |
8646 | if (addr_reg) |
8647 | { | |
8648 | if (addr_reg->reg_num == RegEip | |
8649 | || addr_reg->reg_num == RegEiz | |
8650 | || addr_reg->reg_type.bitfield.reg32) | |
8651 | addr_mode = CODE_32BIT; | |
8652 | else if (flag_code != CODE_64BIT | |
8653 | && addr_reg->reg_type.bitfield.reg16) | |
8654 | addr_mode = CODE_16BIT; | |
8655 | ||
8656 | if (addr_mode != flag_code) | |
8657 | { | |
8658 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
8659 | i.prefixes += 1; | |
8660 | /* Change the size of any displacement too. At most one | |
8661 | of Disp16 or Disp32 is set. | |
8662 | FIXME. There doesn't seem to be any real need for | |
8663 | separate Disp16 and Disp32 flags. The same goes for | |
8664 | Imm16 and Imm32. Removing them would probably clean | |
8665 | up the code quite a lot. */ | |
8666 | if (flag_code != CODE_64BIT | |
8667 | && (i.types[this_operand].bitfield.disp16 | |
8668 | || i.types[this_operand].bitfield.disp32)) | |
8669 | i.types[this_operand] | |
8670 | = operand_type_xor (i.types[this_operand], disp16_32); | |
8671 | } | |
8672 | } | |
8673 | } | |
24eab124 | 8674 | #endif |
be05d201 L |
8675 | } |
8676 | ||
fc0763e6 JB |
8677 | if (current_templates->start->opcode_modifier.isstring |
8678 | && !current_templates->start->opcode_modifier.immext | |
8679 | && (current_templates->end[-1].opcode_modifier.isstring | |
8680 | || i.mem_operands)) | |
8681 | { | |
8682 | /* Memory operands of string insns are special in that they only allow | |
8683 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
8684 | const reg_entry *expected_reg; |
8685 | static const char *di_si[][2] = | |
8686 | { | |
8687 | { "esi", "edi" }, | |
8688 | { "si", "di" }, | |
8689 | { "rsi", "rdi" } | |
8690 | }; | |
8691 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
8692 | |
8693 | kind = "string address"; | |
8694 | ||
8325cc63 | 8695 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 JB |
8696 | { |
8697 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
8698 | ||
8699 | if (!type.bitfield.baseindex | |
8700 | || ((!i.mem_operands != !intel_syntax) | |
8701 | && current_templates->end[-1].operand_types[1] | |
8702 | .bitfield.baseindex)) | |
8703 | type = current_templates->end[-1].operand_types[1]; | |
be05d201 L |
8704 | expected_reg = hash_find (reg_hash, |
8705 | di_si[addr_mode][type.bitfield.esseg]); | |
8706 | ||
fc0763e6 JB |
8707 | } |
8708 | else | |
be05d201 | 8709 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 8710 | |
be05d201 L |
8711 | if (i.base_reg != expected_reg |
8712 | || i.index_reg | |
fc0763e6 | 8713 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 8714 | { |
be05d201 L |
8715 | /* The second memory operand must have the same size as |
8716 | the first one. */ | |
8717 | if (i.mem_operands | |
8718 | && i.base_reg | |
8719 | && !((addr_mode == CODE_64BIT | |
8720 | && i.base_reg->reg_type.bitfield.reg64) | |
8721 | || (addr_mode == CODE_32BIT | |
8722 | ? i.base_reg->reg_type.bitfield.reg32 | |
8723 | : i.base_reg->reg_type.bitfield.reg16))) | |
8724 | goto bad_address; | |
8725 | ||
fc0763e6 JB |
8726 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
8727 | operand_string, | |
8728 | intel_syntax ? '[' : '(', | |
8729 | register_prefix, | |
be05d201 | 8730 | expected_reg->reg_name, |
fc0763e6 | 8731 | intel_syntax ? ']' : ')'); |
be05d201 | 8732 | return 1; |
fc0763e6 | 8733 | } |
be05d201 L |
8734 | else |
8735 | return 1; | |
8736 | ||
8737 | bad_address: | |
8738 | as_bad (_("`%s' is not a valid %s expression"), | |
8739 | operand_string, kind); | |
8740 | return 0; | |
3e73aa7c JH |
8741 | } |
8742 | else | |
8743 | { | |
be05d201 L |
8744 | if (addr_mode != CODE_16BIT) |
8745 | { | |
8746 | /* 32-bit/64-bit checks. */ | |
8747 | if ((i.base_reg | |
8748 | && (addr_mode == CODE_64BIT | |
8749 | ? !i.base_reg->reg_type.bitfield.reg64 | |
8750 | : !i.base_reg->reg_type.bitfield.reg32) | |
8751 | && (i.index_reg | |
8752 | || (i.base_reg->reg_num | |
8753 | != (addr_mode == CODE_64BIT ? RegRip : RegEip)))) | |
8754 | || (i.index_reg | |
8755 | && !i.index_reg->reg_type.bitfield.regxmm | |
8756 | && !i.index_reg->reg_type.bitfield.regymm | |
43234a1e | 8757 | && !i.index_reg->reg_type.bitfield.regzmm |
be05d201 L |
8758 | && ((addr_mode == CODE_64BIT |
8759 | ? !(i.index_reg->reg_type.bitfield.reg64 | |
8760 | || i.index_reg->reg_num == RegRiz) | |
8761 | : !(i.index_reg->reg_type.bitfield.reg32 | |
8762 | || i.index_reg->reg_num == RegEiz)) | |
8763 | || !i.index_reg->reg_type.bitfield.baseindex))) | |
8764 | goto bad_address; | |
8178be5b JB |
8765 | |
8766 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
8767 | if (current_templates->start->base_opcode == 0xf30f1b | |
8768 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
8769 | { | |
8770 | /* They cannot use RIP-relative addressing. */ | |
8771 | if (i.base_reg && i.base_reg->reg_num == RegRip) | |
8772 | { | |
8773 | as_bad (_("`%s' cannot be used here"), operand_string); | |
8774 | return 0; | |
8775 | } | |
8776 | ||
8777 | /* bndldx and bndstx ignore their scale factor. */ | |
8778 | if (current_templates->start->base_opcode != 0xf30f1b | |
8779 | && i.log2_scale_factor) | |
8780 | as_warn (_("register scaling is being ignored here")); | |
8781 | } | |
be05d201 L |
8782 | } |
8783 | else | |
3e73aa7c | 8784 | { |
be05d201 | 8785 | /* 16-bit checks. */ |
3e73aa7c | 8786 | if ((i.base_reg |
40fb9820 L |
8787 | && (!i.base_reg->reg_type.bitfield.reg16 |
8788 | || !i.base_reg->reg_type.bitfield.baseindex)) | |
3e73aa7c | 8789 | || (i.index_reg |
40fb9820 L |
8790 | && (!i.index_reg->reg_type.bitfield.reg16 |
8791 | || !i.index_reg->reg_type.bitfield.baseindex | |
29b0f896 AM |
8792 | || !(i.base_reg |
8793 | && i.base_reg->reg_num < 6 | |
8794 | && i.index_reg->reg_num >= 6 | |
8795 | && i.log2_scale_factor == 0)))) | |
be05d201 | 8796 | goto bad_address; |
3e73aa7c JH |
8797 | } |
8798 | } | |
be05d201 | 8799 | return 1; |
24eab124 | 8800 | } |
252b5132 | 8801 | |
43234a1e L |
8802 | /* Handle vector immediates. */ |
8803 | ||
8804 | static int | |
8805 | RC_SAE_immediate (const char *imm_start) | |
8806 | { | |
8807 | unsigned int match_found, j; | |
8808 | const char *pstr = imm_start; | |
8809 | expressionS *exp; | |
8810 | ||
8811 | if (*pstr != '{') | |
8812 | return 0; | |
8813 | ||
8814 | pstr++; | |
8815 | match_found = 0; | |
8816 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
8817 | { | |
8818 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
8819 | { | |
8820 | if (!i.rounding) | |
8821 | { | |
8822 | rc_op.type = RC_NamesTable[j].type; | |
8823 | rc_op.operand = this_operand; | |
8824 | i.rounding = &rc_op; | |
8825 | } | |
8826 | else | |
8827 | { | |
8828 | as_bad (_("duplicated `%s'"), imm_start); | |
8829 | return 0; | |
8830 | } | |
8831 | pstr += RC_NamesTable[j].len; | |
8832 | match_found = 1; | |
8833 | break; | |
8834 | } | |
8835 | } | |
8836 | if (!match_found) | |
8837 | return 0; | |
8838 | ||
8839 | if (*pstr++ != '}') | |
8840 | { | |
8841 | as_bad (_("Missing '}': '%s'"), imm_start); | |
8842 | return 0; | |
8843 | } | |
8844 | /* RC/SAE immediate string should contain nothing more. */; | |
8845 | if (*pstr != 0) | |
8846 | { | |
8847 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
8848 | return 0; | |
8849 | } | |
8850 | ||
8851 | exp = &im_expressions[i.imm_operands++]; | |
8852 | i.op[this_operand].imms = exp; | |
8853 | ||
8854 | exp->X_op = O_constant; | |
8855 | exp->X_add_number = 0; | |
8856 | exp->X_add_symbol = (symbolS *) 0; | |
8857 | exp->X_op_symbol = (symbolS *) 0; | |
8858 | ||
8859 | i.types[this_operand].bitfield.imm8 = 1; | |
8860 | return 1; | |
8861 | } | |
8862 | ||
8325cc63 JB |
8863 | /* Only string instructions can have a second memory operand, so |
8864 | reduce current_templates to just those if it contains any. */ | |
8865 | static int | |
8866 | maybe_adjust_templates (void) | |
8867 | { | |
8868 | const insn_template *t; | |
8869 | ||
8870 | gas_assert (i.mem_operands == 1); | |
8871 | ||
8872 | for (t = current_templates->start; t < current_templates->end; ++t) | |
8873 | if (t->opcode_modifier.isstring) | |
8874 | break; | |
8875 | ||
8876 | if (t < current_templates->end) | |
8877 | { | |
8878 | static templates aux_templates; | |
8879 | bfd_boolean recheck; | |
8880 | ||
8881 | aux_templates.start = t; | |
8882 | for (; t < current_templates->end; ++t) | |
8883 | if (!t->opcode_modifier.isstring) | |
8884 | break; | |
8885 | aux_templates.end = t; | |
8886 | ||
8887 | /* Determine whether to re-check the first memory operand. */ | |
8888 | recheck = (aux_templates.start != current_templates->start | |
8889 | || t != current_templates->end); | |
8890 | ||
8891 | current_templates = &aux_templates; | |
8892 | ||
8893 | if (recheck) | |
8894 | { | |
8895 | i.mem_operands = 0; | |
8896 | if (i.memop1_string != NULL | |
8897 | && i386_index_check (i.memop1_string) == 0) | |
8898 | return 0; | |
8899 | i.mem_operands = 1; | |
8900 | } | |
8901 | } | |
8902 | ||
8903 | return 1; | |
8904 | } | |
8905 | ||
fc0763e6 | 8906 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 8907 | on error. */ |
252b5132 | 8908 | |
252b5132 | 8909 | static int |
a7619375 | 8910 | i386_att_operand (char *operand_string) |
252b5132 | 8911 | { |
af6bdddf AM |
8912 | const reg_entry *r; |
8913 | char *end_op; | |
24eab124 | 8914 | char *op_string = operand_string; |
252b5132 | 8915 | |
24eab124 | 8916 | if (is_space_char (*op_string)) |
252b5132 RH |
8917 | ++op_string; |
8918 | ||
24eab124 | 8919 | /* We check for an absolute prefix (differentiating, |
47926f60 | 8920 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
8921 | if (*op_string == ABSOLUTE_PREFIX) |
8922 | { | |
8923 | ++op_string; | |
8924 | if (is_space_char (*op_string)) | |
8925 | ++op_string; | |
40fb9820 | 8926 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 8927 | } |
252b5132 | 8928 | |
47926f60 | 8929 | /* Check if operand is a register. */ |
4d1bb795 | 8930 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 8931 | { |
40fb9820 L |
8932 | i386_operand_type temp; |
8933 | ||
24eab124 AM |
8934 | /* Check for a segment override by searching for ':' after a |
8935 | segment register. */ | |
8936 | op_string = end_op; | |
8937 | if (is_space_char (*op_string)) | |
8938 | ++op_string; | |
40fb9820 L |
8939 | if (*op_string == ':' |
8940 | && (r->reg_type.bitfield.sreg2 | |
8941 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
8942 | { |
8943 | switch (r->reg_num) | |
8944 | { | |
8945 | case 0: | |
8946 | i.seg[i.mem_operands] = &es; | |
8947 | break; | |
8948 | case 1: | |
8949 | i.seg[i.mem_operands] = &cs; | |
8950 | break; | |
8951 | case 2: | |
8952 | i.seg[i.mem_operands] = &ss; | |
8953 | break; | |
8954 | case 3: | |
8955 | i.seg[i.mem_operands] = &ds; | |
8956 | break; | |
8957 | case 4: | |
8958 | i.seg[i.mem_operands] = &fs; | |
8959 | break; | |
8960 | case 5: | |
8961 | i.seg[i.mem_operands] = &gs; | |
8962 | break; | |
8963 | } | |
252b5132 | 8964 | |
24eab124 | 8965 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
8966 | ++op_string; |
8967 | if (is_space_char (*op_string)) | |
24eab124 | 8968 | ++op_string; |
252b5132 | 8969 | |
24eab124 AM |
8970 | if (!is_digit_char (*op_string) |
8971 | && !is_identifier_char (*op_string) | |
8972 | && *op_string != '(' | |
8973 | && *op_string != ABSOLUTE_PREFIX) | |
8974 | { | |
8975 | as_bad (_("bad memory operand `%s'"), op_string); | |
8976 | return 0; | |
8977 | } | |
47926f60 | 8978 | /* Handle case of %es:*foo. */ |
24eab124 AM |
8979 | if (*op_string == ABSOLUTE_PREFIX) |
8980 | { | |
8981 | ++op_string; | |
8982 | if (is_space_char (*op_string)) | |
8983 | ++op_string; | |
40fb9820 | 8984 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
8985 | } |
8986 | goto do_memory_reference; | |
8987 | } | |
43234a1e L |
8988 | |
8989 | /* Handle vector operations. */ | |
8990 | if (*op_string == '{') | |
8991 | { | |
8992 | op_string = check_VecOperations (op_string, NULL); | |
8993 | if (op_string == NULL) | |
8994 | return 0; | |
8995 | } | |
8996 | ||
24eab124 AM |
8997 | if (*op_string) |
8998 | { | |
d0b47220 | 8999 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
9000 | return 0; |
9001 | } | |
40fb9820 L |
9002 | temp = r->reg_type; |
9003 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
9004 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
9005 | temp); | |
7d5e4556 | 9006 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 9007 | i.op[this_operand].regs = r; |
24eab124 AM |
9008 | i.reg_operands++; |
9009 | } | |
af6bdddf AM |
9010 | else if (*op_string == REGISTER_PREFIX) |
9011 | { | |
9012 | as_bad (_("bad register name `%s'"), op_string); | |
9013 | return 0; | |
9014 | } | |
24eab124 | 9015 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 9016 | { |
24eab124 | 9017 | ++op_string; |
40fb9820 | 9018 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 9019 | { |
d0b47220 | 9020 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
9021 | return 0; |
9022 | } | |
9023 | if (!i386_immediate (op_string)) | |
9024 | return 0; | |
9025 | } | |
43234a1e L |
9026 | else if (RC_SAE_immediate (operand_string)) |
9027 | { | |
9028 | /* If it is a RC or SAE immediate, do nothing. */ | |
9029 | ; | |
9030 | } | |
24eab124 AM |
9031 | else if (is_digit_char (*op_string) |
9032 | || is_identifier_char (*op_string) | |
d02603dc | 9033 | || *op_string == '"' |
e5cb08ac | 9034 | || *op_string == '(') |
24eab124 | 9035 | { |
47926f60 | 9036 | /* This is a memory reference of some sort. */ |
af6bdddf | 9037 | char *base_string; |
252b5132 | 9038 | |
47926f60 | 9039 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
9040 | char *displacement_string_start; |
9041 | char *displacement_string_end; | |
43234a1e | 9042 | char *vop_start; |
252b5132 | 9043 | |
24eab124 | 9044 | do_memory_reference: |
8325cc63 JB |
9045 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
9046 | return 0; | |
24eab124 | 9047 | if ((i.mem_operands == 1 |
40fb9820 | 9048 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
9049 | || i.mem_operands == 2) |
9050 | { | |
9051 | as_bad (_("too many memory references for `%s'"), | |
9052 | current_templates->start->name); | |
9053 | return 0; | |
9054 | } | |
252b5132 | 9055 | |
24eab124 AM |
9056 | /* Check for base index form. We detect the base index form by |
9057 | looking for an ')' at the end of the operand, searching | |
9058 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
9059 | after the '('. */ | |
af6bdddf | 9060 | base_string = op_string + strlen (op_string); |
c3332e24 | 9061 | |
43234a1e L |
9062 | /* Handle vector operations. */ |
9063 | vop_start = strchr (op_string, '{'); | |
9064 | if (vop_start && vop_start < base_string) | |
9065 | { | |
9066 | if (check_VecOperations (vop_start, base_string) == NULL) | |
9067 | return 0; | |
9068 | base_string = vop_start; | |
9069 | } | |
9070 | ||
af6bdddf AM |
9071 | --base_string; |
9072 | if (is_space_char (*base_string)) | |
9073 | --base_string; | |
252b5132 | 9074 | |
47926f60 | 9075 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
9076 | displacement_string_start = op_string; |
9077 | displacement_string_end = base_string + 1; | |
252b5132 | 9078 | |
24eab124 AM |
9079 | if (*base_string == ')') |
9080 | { | |
af6bdddf | 9081 | char *temp_string; |
24eab124 AM |
9082 | unsigned int parens_balanced = 1; |
9083 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 9084 | equal, so this loop will not be infinite. */ |
24eab124 AM |
9085 | do |
9086 | { | |
9087 | base_string--; | |
9088 | if (*base_string == ')') | |
9089 | parens_balanced++; | |
9090 | if (*base_string == '(') | |
9091 | parens_balanced--; | |
9092 | } | |
9093 | while (parens_balanced); | |
c3332e24 | 9094 | |
af6bdddf | 9095 | temp_string = base_string; |
c3332e24 | 9096 | |
24eab124 | 9097 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
9098 | ++base_string; |
9099 | if (is_space_char (*base_string)) | |
24eab124 | 9100 | ++base_string; |
252b5132 | 9101 | |
af6bdddf | 9102 | if (*base_string == ',' |
4eed87de AM |
9103 | || ((i.base_reg = parse_register (base_string, &end_op)) |
9104 | != NULL)) | |
252b5132 | 9105 | { |
af6bdddf | 9106 | displacement_string_end = temp_string; |
252b5132 | 9107 | |
40fb9820 | 9108 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 9109 | |
af6bdddf | 9110 | if (i.base_reg) |
24eab124 | 9111 | { |
24eab124 AM |
9112 | base_string = end_op; |
9113 | if (is_space_char (*base_string)) | |
9114 | ++base_string; | |
af6bdddf AM |
9115 | } |
9116 | ||
9117 | /* There may be an index reg or scale factor here. */ | |
9118 | if (*base_string == ',') | |
9119 | { | |
9120 | ++base_string; | |
9121 | if (is_space_char (*base_string)) | |
9122 | ++base_string; | |
9123 | ||
4eed87de AM |
9124 | if ((i.index_reg = parse_register (base_string, &end_op)) |
9125 | != NULL) | |
24eab124 | 9126 | { |
af6bdddf | 9127 | base_string = end_op; |
24eab124 AM |
9128 | if (is_space_char (*base_string)) |
9129 | ++base_string; | |
af6bdddf AM |
9130 | if (*base_string == ',') |
9131 | { | |
9132 | ++base_string; | |
9133 | if (is_space_char (*base_string)) | |
9134 | ++base_string; | |
9135 | } | |
e5cb08ac | 9136 | else if (*base_string != ')') |
af6bdddf | 9137 | { |
4eed87de AM |
9138 | as_bad (_("expecting `,' or `)' " |
9139 | "after index register in `%s'"), | |
af6bdddf AM |
9140 | operand_string); |
9141 | return 0; | |
9142 | } | |
24eab124 | 9143 | } |
af6bdddf | 9144 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 9145 | { |
f76bf5e0 L |
9146 | end_op = strchr (base_string, ','); |
9147 | if (end_op) | |
9148 | *end_op = '\0'; | |
af6bdddf | 9149 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
9150 | return 0; |
9151 | } | |
252b5132 | 9152 | |
47926f60 | 9153 | /* Check for scale factor. */ |
551c1ca1 | 9154 | if (*base_string != ')') |
af6bdddf | 9155 | { |
551c1ca1 AM |
9156 | char *end_scale = i386_scale (base_string); |
9157 | ||
9158 | if (!end_scale) | |
af6bdddf | 9159 | return 0; |
24eab124 | 9160 | |
551c1ca1 | 9161 | base_string = end_scale; |
af6bdddf AM |
9162 | if (is_space_char (*base_string)) |
9163 | ++base_string; | |
9164 | if (*base_string != ')') | |
9165 | { | |
4eed87de AM |
9166 | as_bad (_("expecting `)' " |
9167 | "after scale factor in `%s'"), | |
af6bdddf AM |
9168 | operand_string); |
9169 | return 0; | |
9170 | } | |
9171 | } | |
9172 | else if (!i.index_reg) | |
24eab124 | 9173 | { |
4eed87de AM |
9174 | as_bad (_("expecting index register or scale factor " |
9175 | "after `,'; got '%c'"), | |
af6bdddf | 9176 | *base_string); |
24eab124 AM |
9177 | return 0; |
9178 | } | |
9179 | } | |
af6bdddf | 9180 | else if (*base_string != ')') |
24eab124 | 9181 | { |
4eed87de AM |
9182 | as_bad (_("expecting `,' or `)' " |
9183 | "after base register in `%s'"), | |
af6bdddf | 9184 | operand_string); |
24eab124 AM |
9185 | return 0; |
9186 | } | |
c3332e24 | 9187 | } |
af6bdddf | 9188 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 9189 | { |
f76bf5e0 L |
9190 | end_op = strchr (base_string, ','); |
9191 | if (end_op) | |
9192 | *end_op = '\0'; | |
af6bdddf | 9193 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 9194 | return 0; |
c3332e24 | 9195 | } |
24eab124 AM |
9196 | } |
9197 | ||
9198 | /* If there's an expression beginning the operand, parse it, | |
9199 | assuming displacement_string_start and | |
9200 | displacement_string_end are meaningful. */ | |
9201 | if (displacement_string_start != displacement_string_end) | |
9202 | { | |
9203 | if (!i386_displacement (displacement_string_start, | |
9204 | displacement_string_end)) | |
9205 | return 0; | |
9206 | } | |
9207 | ||
9208 | /* Special case for (%dx) while doing input/output op. */ | |
9209 | if (i.base_reg | |
0dfbf9d7 L |
9210 | && operand_type_equal (&i.base_reg->reg_type, |
9211 | ®16_inoutportreg) | |
24eab124 AM |
9212 | && i.index_reg == 0 |
9213 | && i.log2_scale_factor == 0 | |
9214 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 9215 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 9216 | { |
65da13b5 | 9217 | i.types[this_operand] = inoutportreg; |
24eab124 AM |
9218 | return 1; |
9219 | } | |
9220 | ||
eecb386c AM |
9221 | if (i386_index_check (operand_string) == 0) |
9222 | return 0; | |
5c07affc | 9223 | i.types[this_operand].bitfield.mem = 1; |
8325cc63 JB |
9224 | if (i.mem_operands == 0) |
9225 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
9226 | i.mem_operands++; |
9227 | } | |
9228 | else | |
ce8a8b2f AM |
9229 | { |
9230 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
9231 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
9232 | output_invalid (*op_string), | |
9233 | this_operand + 1, | |
9234 | op_string); | |
9235 | return 0; | |
9236 | } | |
47926f60 | 9237 | return 1; /* Normal return. */ |
252b5132 RH |
9238 | } |
9239 | \f | |
fa94de6b RM |
9240 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
9241 | that an rs_machine_dependent frag may reach. */ | |
9242 | ||
9243 | unsigned int | |
9244 | i386_frag_max_var (fragS *frag) | |
9245 | { | |
9246 | /* The only relaxable frags are for jumps. | |
9247 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
9248 | gas_assert (frag->fr_type == rs_machine_dependent); | |
9249 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
9250 | } | |
9251 | ||
b084df0b L |
9252 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9253 | static int | |
8dcea932 | 9254 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
9255 | { |
9256 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
9257 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
9258 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
9259 | return 0; | |
9260 | ||
9261 | if (!S_IS_EXTERNAL (fr_symbol)) | |
9262 | /* Symbol may be weak or local. */ | |
9263 | return !S_IS_WEAK (fr_symbol); | |
9264 | ||
8dcea932 L |
9265 | /* Global symbols with non-default visibility can't be preempted. */ |
9266 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
9267 | return 1; | |
9268 | ||
9269 | if (fr_var != NO_RELOC) | |
9270 | switch ((enum bfd_reloc_code_real) fr_var) | |
9271 | { | |
9272 | case BFD_RELOC_386_PLT32: | |
9273 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 9274 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
9275 | return 0; |
9276 | default: | |
9277 | abort (); | |
9278 | } | |
9279 | ||
b084df0b L |
9280 | /* Global symbols with default visibility in a shared library may be |
9281 | preempted by another definition. */ | |
8dcea932 | 9282 | return !shared; |
b084df0b L |
9283 | } |
9284 | #endif | |
9285 | ||
ee7fcc42 AM |
9286 | /* md_estimate_size_before_relax() |
9287 | ||
9288 | Called just before relax() for rs_machine_dependent frags. The x86 | |
9289 | assembler uses these frags to handle variable size jump | |
9290 | instructions. | |
9291 | ||
9292 | Any symbol that is now undefined will not become defined. | |
9293 | Return the correct fr_subtype in the frag. | |
9294 | Return the initial "guess for variable size of frag" to caller. | |
9295 | The guess is actually the growth beyond the fixed part. Whatever | |
9296 | we do to grow the fixed or variable part contributes to our | |
9297 | returned value. */ | |
9298 | ||
252b5132 | 9299 | int |
7016a5d5 | 9300 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 9301 | { |
252b5132 | 9302 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
9303 | check for un-relaxable symbols. On an ELF system, we can't relax |
9304 | an externally visible symbol, because it may be overridden by a | |
9305 | shared library. */ | |
9306 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 9307 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 9308 | || (IS_ELF |
8dcea932 L |
9309 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
9310 | fragP->fr_var)) | |
fbeb56a4 DK |
9311 | #endif |
9312 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 9313 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 9314 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
9315 | #endif |
9316 | ) | |
252b5132 | 9317 | { |
b98ef147 AM |
9318 | /* Symbol is undefined in this segment, or we need to keep a |
9319 | reloc so that weak symbols can be overridden. */ | |
9320 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 9321 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
9322 | unsigned char *opcode; |
9323 | int old_fr_fix; | |
f6af82bd | 9324 | |
ee7fcc42 | 9325 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 9326 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 9327 | else if (size == 2) |
f6af82bd AM |
9328 | reloc_type = BFD_RELOC_16_PCREL; |
9329 | else | |
9330 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 9331 | |
ee7fcc42 AM |
9332 | old_fr_fix = fragP->fr_fix; |
9333 | opcode = (unsigned char *) fragP->fr_opcode; | |
9334 | ||
fddf5b5b | 9335 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 9336 | { |
fddf5b5b AM |
9337 | case UNCOND_JUMP: |
9338 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 9339 | opcode[0] = 0xe9; |
252b5132 | 9340 | fragP->fr_fix += size; |
062cd5e7 AS |
9341 | fix_new (fragP, old_fr_fix, size, |
9342 | fragP->fr_symbol, | |
9343 | fragP->fr_offset, 1, | |
9344 | reloc_type); | |
252b5132 RH |
9345 | break; |
9346 | ||
fddf5b5b | 9347 | case COND_JUMP86: |
412167cb AM |
9348 | if (size == 2 |
9349 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
9350 | { |
9351 | /* Negate the condition, and branch past an | |
9352 | unconditional jump. */ | |
9353 | opcode[0] ^= 1; | |
9354 | opcode[1] = 3; | |
9355 | /* Insert an unconditional jump. */ | |
9356 | opcode[2] = 0xe9; | |
9357 | /* We added two extra opcode bytes, and have a two byte | |
9358 | offset. */ | |
9359 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
9360 | fix_new (fragP, old_fr_fix + 2, 2, |
9361 | fragP->fr_symbol, | |
9362 | fragP->fr_offset, 1, | |
9363 | reloc_type); | |
fddf5b5b AM |
9364 | break; |
9365 | } | |
9366 | /* Fall through. */ | |
9367 | ||
9368 | case COND_JUMP: | |
412167cb AM |
9369 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
9370 | { | |
3e02c1cc AM |
9371 | fixS *fixP; |
9372 | ||
412167cb | 9373 | fragP->fr_fix += 1; |
3e02c1cc AM |
9374 | fixP = fix_new (fragP, old_fr_fix, 1, |
9375 | fragP->fr_symbol, | |
9376 | fragP->fr_offset, 1, | |
9377 | BFD_RELOC_8_PCREL); | |
9378 | fixP->fx_signed = 1; | |
412167cb AM |
9379 | break; |
9380 | } | |
93c2a809 | 9381 | |
24eab124 | 9382 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 9383 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 9384 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 9385 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
9386 | /* We've added an opcode byte. */ |
9387 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
9388 | fix_new (fragP, old_fr_fix + 1, size, |
9389 | fragP->fr_symbol, | |
9390 | fragP->fr_offset, 1, | |
9391 | reloc_type); | |
252b5132 | 9392 | break; |
fddf5b5b AM |
9393 | |
9394 | default: | |
9395 | BAD_CASE (fragP->fr_subtype); | |
9396 | break; | |
252b5132 RH |
9397 | } |
9398 | frag_wane (fragP); | |
ee7fcc42 | 9399 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 9400 | } |
93c2a809 | 9401 | |
93c2a809 AM |
9402 | /* Guess size depending on current relax state. Initially the relax |
9403 | state will correspond to a short jump and we return 1, because | |
9404 | the variable part of the frag (the branch offset) is one byte | |
9405 | long. However, we can relax a section more than once and in that | |
9406 | case we must either set fr_subtype back to the unrelaxed state, | |
9407 | or return the value for the appropriate branch. */ | |
9408 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
9409 | } |
9410 | ||
47926f60 KH |
9411 | /* Called after relax() is finished. |
9412 | ||
9413 | In: Address of frag. | |
9414 | fr_type == rs_machine_dependent. | |
9415 | fr_subtype is what the address relaxed to. | |
9416 | ||
9417 | Out: Any fixSs and constants are set up. | |
9418 | Caller will turn frag into a ".space 0". */ | |
9419 | ||
252b5132 | 9420 | void |
7016a5d5 TG |
9421 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
9422 | fragS *fragP) | |
252b5132 | 9423 | { |
29b0f896 | 9424 | unsigned char *opcode; |
252b5132 | 9425 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
9426 | offsetT target_address; |
9427 | offsetT opcode_address; | |
252b5132 | 9428 | unsigned int extension = 0; |
847f7ad4 | 9429 | offsetT displacement_from_opcode_start; |
252b5132 RH |
9430 | |
9431 | opcode = (unsigned char *) fragP->fr_opcode; | |
9432 | ||
47926f60 | 9433 | /* Address we want to reach in file space. */ |
252b5132 | 9434 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 9435 | |
47926f60 | 9436 | /* Address opcode resides at in file space. */ |
252b5132 RH |
9437 | opcode_address = fragP->fr_address + fragP->fr_fix; |
9438 | ||
47926f60 | 9439 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
9440 | displacement_from_opcode_start = target_address - opcode_address; |
9441 | ||
fddf5b5b | 9442 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 9443 | { |
47926f60 KH |
9444 | /* Don't have to change opcode. */ |
9445 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 9446 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
9447 | } |
9448 | else | |
9449 | { | |
9450 | if (no_cond_jump_promotion | |
9451 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
9452 | as_warn_where (fragP->fr_file, fragP->fr_line, |
9453 | _("long jump required")); | |
252b5132 | 9454 | |
fddf5b5b AM |
9455 | switch (fragP->fr_subtype) |
9456 | { | |
9457 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
9458 | extension = 4; /* 1 opcode + 4 displacement */ | |
9459 | opcode[0] = 0xe9; | |
9460 | where_to_put_displacement = &opcode[1]; | |
9461 | break; | |
252b5132 | 9462 | |
fddf5b5b AM |
9463 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
9464 | extension = 2; /* 1 opcode + 2 displacement */ | |
9465 | opcode[0] = 0xe9; | |
9466 | where_to_put_displacement = &opcode[1]; | |
9467 | break; | |
252b5132 | 9468 | |
fddf5b5b AM |
9469 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
9470 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
9471 | extension = 5; /* 2 opcode + 4 displacement */ | |
9472 | opcode[1] = opcode[0] + 0x10; | |
9473 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
9474 | where_to_put_displacement = &opcode[2]; | |
9475 | break; | |
252b5132 | 9476 | |
fddf5b5b AM |
9477 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
9478 | extension = 3; /* 2 opcode + 2 displacement */ | |
9479 | opcode[1] = opcode[0] + 0x10; | |
9480 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
9481 | where_to_put_displacement = &opcode[2]; | |
9482 | break; | |
252b5132 | 9483 | |
fddf5b5b AM |
9484 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
9485 | extension = 4; | |
9486 | opcode[0] ^= 1; | |
9487 | opcode[1] = 3; | |
9488 | opcode[2] = 0xe9; | |
9489 | where_to_put_displacement = &opcode[3]; | |
9490 | break; | |
9491 | ||
9492 | default: | |
9493 | BAD_CASE (fragP->fr_subtype); | |
9494 | break; | |
9495 | } | |
252b5132 | 9496 | } |
fddf5b5b | 9497 | |
7b81dfbb AJ |
9498 | /* If size if less then four we are sure that the operand fits, |
9499 | but if it's 4, then it could be that the displacement is larger | |
9500 | then -/+ 2GB. */ | |
9501 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
9502 | && object_64bit | |
9503 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
9504 | + ((addressT) 1 << 31)) |
9505 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
9506 | { |
9507 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9508 | _("jump target out of range")); | |
9509 | /* Make us emit 0. */ | |
9510 | displacement_from_opcode_start = extension; | |
9511 | } | |
47926f60 | 9512 | /* Now put displacement after opcode. */ |
252b5132 RH |
9513 | md_number_to_chars ((char *) where_to_put_displacement, |
9514 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 9515 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
9516 | fragP->fr_fix += extension; |
9517 | } | |
9518 | \f | |
7016a5d5 | 9519 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
9520 | by our caller that we have all the info we need to fix it up. |
9521 | ||
7016a5d5 TG |
9522 | Parameter valP is the pointer to the value of the bits. |
9523 | ||
252b5132 RH |
9524 | On the 386, immediates, displacements, and data pointers are all in |
9525 | the same (little-endian) format, so we don't need to care about which | |
9526 | we are handling. */ | |
9527 | ||
94f592af | 9528 | void |
7016a5d5 | 9529 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 9530 | { |
94f592af | 9531 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 9532 | valueT value = *valP; |
252b5132 | 9533 | |
f86103b7 | 9534 | #if !defined (TE_Mach) |
93382f6d AM |
9535 | if (fixP->fx_pcrel) |
9536 | { | |
9537 | switch (fixP->fx_r_type) | |
9538 | { | |
5865bb77 ILT |
9539 | default: |
9540 | break; | |
9541 | ||
d6ab8113 JB |
9542 | case BFD_RELOC_64: |
9543 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
9544 | break; | |
93382f6d | 9545 | case BFD_RELOC_32: |
ae8887b5 | 9546 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
9547 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
9548 | break; | |
9549 | case BFD_RELOC_16: | |
9550 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
9551 | break; | |
9552 | case BFD_RELOC_8: | |
9553 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
9554 | break; | |
9555 | } | |
9556 | } | |
252b5132 | 9557 | |
a161fe53 | 9558 | if (fixP->fx_addsy != NULL |
31312f95 | 9559 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 9560 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 9561 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 9562 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 9563 | && !use_rela_relocations) |
252b5132 | 9564 | { |
31312f95 AM |
9565 | /* This is a hack. There should be a better way to handle this. |
9566 | This covers for the fact that bfd_install_relocation will | |
9567 | subtract the current location (for partial_inplace, PC relative | |
9568 | relocations); see more below. */ | |
252b5132 | 9569 | #ifndef OBJ_AOUT |
718ddfc0 | 9570 | if (IS_ELF |
252b5132 RH |
9571 | #ifdef TE_PE |
9572 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
9573 | #endif | |
9574 | ) | |
9575 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
9576 | #endif | |
9577 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 9578 | if (IS_ELF) |
252b5132 | 9579 | { |
6539b54b | 9580 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 9581 | |
6539b54b | 9582 | if ((sym_seg == seg |
2f66722d | 9583 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 9584 | && sym_seg != absolute_section)) |
af65af87 | 9585 | && !generic_force_reloc (fixP)) |
2f66722d AM |
9586 | { |
9587 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
9588 | bfd_install_relocation subtracts them out again. I think |
9589 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
9590 | it. FIXME. */ |
9591 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
9592 | } | |
252b5132 RH |
9593 | } |
9594 | #endif | |
9595 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
9596 | /* For some reason, the PE format does not store a |
9597 | section address offset for a PC relative symbol. */ | |
9598 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 9599 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
9600 | value += md_pcrel_from (fixP); |
9601 | #endif | |
9602 | } | |
fbeb56a4 | 9603 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
9604 | if (fixP->fx_addsy != NULL |
9605 | && S_IS_WEAK (fixP->fx_addsy) | |
9606 | /* PR 16858: Do not modify weak function references. */ | |
9607 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 9608 | { |
296a8689 NC |
9609 | #if !defined (TE_PEP) |
9610 | /* For x86 PE weak function symbols are neither PC-relative | |
9611 | nor do they set S_IS_FUNCTION. So the only reliable way | |
9612 | to detect them is to check the flags of their containing | |
9613 | section. */ | |
9614 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
9615 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
9616 | ; | |
9617 | else | |
9618 | #endif | |
fbeb56a4 DK |
9619 | value -= S_GET_VALUE (fixP->fx_addsy); |
9620 | } | |
9621 | #endif | |
252b5132 RH |
9622 | |
9623 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 9624 | and we must not disappoint it. */ |
252b5132 | 9625 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 9626 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
9627 | switch (fixP->fx_r_type) |
9628 | { | |
9629 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 9630 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
9631 | /* Make the jump instruction point to the address of the operand. At |
9632 | runtime we merely add the offset to the actual PLT entry. */ | |
9633 | value = -4; | |
9634 | break; | |
31312f95 | 9635 | |
13ae64f3 JJ |
9636 | case BFD_RELOC_386_TLS_GD: |
9637 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 9638 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
9639 | case BFD_RELOC_386_TLS_IE: |
9640 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 9641 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
9642 | case BFD_RELOC_X86_64_TLSGD: |
9643 | case BFD_RELOC_X86_64_TLSLD: | |
9644 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 9645 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
9646 | value = 0; /* Fully resolved at runtime. No addend. */ |
9647 | /* Fallthrough */ | |
9648 | case BFD_RELOC_386_TLS_LE: | |
9649 | case BFD_RELOC_386_TLS_LDO_32: | |
9650 | case BFD_RELOC_386_TLS_LE_32: | |
9651 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 9652 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 9653 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 9654 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
9655 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
9656 | break; | |
9657 | ||
67a4f2b7 AO |
9658 | case BFD_RELOC_386_TLS_DESC_CALL: |
9659 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
9660 | value = 0; /* Fully resolved at runtime. No addend. */ | |
9661 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
9662 | fixP->fx_done = 0; | |
9663 | return; | |
9664 | ||
47926f60 KH |
9665 | case BFD_RELOC_VTABLE_INHERIT: |
9666 | case BFD_RELOC_VTABLE_ENTRY: | |
9667 | fixP->fx_done = 0; | |
94f592af | 9668 | return; |
47926f60 KH |
9669 | |
9670 | default: | |
9671 | break; | |
9672 | } | |
9673 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 9674 | *valP = value; |
f86103b7 | 9675 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 9676 | |
3e73aa7c | 9677 | /* Are we finished with this relocation now? */ |
c6682705 | 9678 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 9679 | fixP->fx_done = 1; |
fbeb56a4 DK |
9680 | #if defined (OBJ_COFF) && defined (TE_PE) |
9681 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
9682 | { | |
9683 | fixP->fx_done = 0; | |
9684 | /* Remember value for tc_gen_reloc. */ | |
9685 | fixP->fx_addnumber = value; | |
9686 | /* Clear out the frag for now. */ | |
9687 | value = 0; | |
9688 | } | |
9689 | #endif | |
3e73aa7c JH |
9690 | else if (use_rela_relocations) |
9691 | { | |
9692 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
9693 | /* Remember value for tc_gen_reloc. */ |
9694 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
9695 | value = 0; |
9696 | } | |
f86103b7 | 9697 | |
94f592af | 9698 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 9699 | } |
252b5132 | 9700 | \f |
6d4af3c2 | 9701 | const char * |
499ac353 | 9702 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 9703 | { |
499ac353 NC |
9704 | /* This outputs the LITTLENUMs in REVERSE order; |
9705 | in accord with the bigendian 386. */ | |
9706 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
9707 | } |
9708 | \f | |
2d545b82 | 9709 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 9710 | |
252b5132 | 9711 | static char * |
e3bb37b5 | 9712 | output_invalid (int c) |
252b5132 | 9713 | { |
3882b010 | 9714 | if (ISPRINT (c)) |
f9f21a03 L |
9715 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
9716 | "'%c'", c); | |
252b5132 | 9717 | else |
f9f21a03 | 9718 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 9719 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
9720 | return output_invalid_buf; |
9721 | } | |
9722 | ||
af6bdddf | 9723 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
9724 | |
9725 | static const reg_entry * | |
4d1bb795 | 9726 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 9727 | { |
af6bdddf AM |
9728 | char *s = reg_string; |
9729 | char *p; | |
252b5132 RH |
9730 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
9731 | const reg_entry *r; | |
9732 | ||
9733 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
9734 | if (*s == REGISTER_PREFIX) | |
9735 | ++s; | |
9736 | ||
9737 | if (is_space_char (*s)) | |
9738 | ++s; | |
9739 | ||
9740 | p = reg_name_given; | |
af6bdddf | 9741 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
9742 | { |
9743 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
9744 | return (const reg_entry *) NULL; |
9745 | s++; | |
252b5132 RH |
9746 | } |
9747 | ||
6588847e DN |
9748 | /* For naked regs, make sure that we are not dealing with an identifier. |
9749 | This prevents confusing an identifier like `eax_var' with register | |
9750 | `eax'. */ | |
9751 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
9752 | return (const reg_entry *) NULL; | |
9753 | ||
af6bdddf | 9754 | *end_op = s; |
252b5132 RH |
9755 | |
9756 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
9757 | ||
5f47d35b | 9758 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 9759 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 9760 | { |
5f47d35b AM |
9761 | if (is_space_char (*s)) |
9762 | ++s; | |
9763 | if (*s == '(') | |
9764 | { | |
af6bdddf | 9765 | ++s; |
5f47d35b AM |
9766 | if (is_space_char (*s)) |
9767 | ++s; | |
9768 | if (*s >= '0' && *s <= '7') | |
9769 | { | |
db557034 | 9770 | int fpr = *s - '0'; |
af6bdddf | 9771 | ++s; |
5f47d35b AM |
9772 | if (is_space_char (*s)) |
9773 | ++s; | |
9774 | if (*s == ')') | |
9775 | { | |
9776 | *end_op = s + 1; | |
1e9cc1c2 | 9777 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
9778 | know (r); |
9779 | return r + fpr; | |
5f47d35b | 9780 | } |
5f47d35b | 9781 | } |
47926f60 | 9782 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
9783 | return (const reg_entry *) NULL; |
9784 | } | |
9785 | } | |
9786 | ||
a60de03c JB |
9787 | if (r == NULL || allow_pseudo_reg) |
9788 | return r; | |
9789 | ||
0dfbf9d7 | 9790 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
9791 | return (const reg_entry *) NULL; |
9792 | ||
192dc9c6 JB |
9793 | if ((r->reg_type.bitfield.reg32 |
9794 | || r->reg_type.bitfield.sreg3 | |
9795 | || r->reg_type.bitfield.control | |
9796 | || r->reg_type.bitfield.debug | |
9797 | || r->reg_type.bitfield.test) | |
9798 | && !cpu_arch_flags.bitfield.cpui386) | |
9799 | return (const reg_entry *) NULL; | |
9800 | ||
309d3373 JB |
9801 | if (r->reg_type.bitfield.floatreg |
9802 | && !cpu_arch_flags.bitfield.cpu8087 | |
9803 | && !cpu_arch_flags.bitfield.cpu287 | |
9804 | && !cpu_arch_flags.bitfield.cpu387) | |
9805 | return (const reg_entry *) NULL; | |
9806 | ||
1848e567 | 9807 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx) |
192dc9c6 JB |
9808 | return (const reg_entry *) NULL; |
9809 | ||
1848e567 | 9810 | if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm) |
192dc9c6 JB |
9811 | return (const reg_entry *) NULL; |
9812 | ||
1848e567 | 9813 | if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm) |
40f12533 L |
9814 | return (const reg_entry *) NULL; |
9815 | ||
1848e567 L |
9816 | if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm) |
9817 | return (const reg_entry *) NULL; | |
9818 | ||
9819 | if (r->reg_type.bitfield.regmask | |
9820 | && !cpu_arch_flags.bitfield.cpuregmask) | |
43234a1e L |
9821 | return (const reg_entry *) NULL; |
9822 | ||
db51cc60 | 9823 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
a60de03c | 9824 | if (!allow_index_reg |
db51cc60 L |
9825 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) |
9826 | return (const reg_entry *) NULL; | |
9827 | ||
43234a1e L |
9828 | /* Upper 16 vector register is only available with VREX in 64bit |
9829 | mode. */ | |
9830 | if ((r->reg_flags & RegVRex)) | |
9831 | { | |
86fa6981 L |
9832 | if (i.vec_encoding == vex_encoding_default) |
9833 | i.vec_encoding = vex_encoding_evex; | |
9834 | ||
43234a1e | 9835 | if (!cpu_arch_flags.bitfield.cpuvrex |
86fa6981 | 9836 | || i.vec_encoding != vex_encoding_evex |
43234a1e L |
9837 | || flag_code != CODE_64BIT) |
9838 | return (const reg_entry *) NULL; | |
43234a1e L |
9839 | } |
9840 | ||
a60de03c JB |
9841 | if (((r->reg_flags & (RegRex64 | RegRex)) |
9842 | || r->reg_type.bitfield.reg64) | |
40fb9820 | 9843 | && (!cpu_arch_flags.bitfield.cpulm |
0dfbf9d7 | 9844 | || !operand_type_equal (&r->reg_type, &control)) |
1ae00879 | 9845 | && flag_code != CODE_64BIT) |
20f0a1fc | 9846 | return (const reg_entry *) NULL; |
1ae00879 | 9847 | |
b7240065 JB |
9848 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
9849 | return (const reg_entry *) NULL; | |
9850 | ||
252b5132 RH |
9851 | return r; |
9852 | } | |
4d1bb795 JB |
9853 | |
9854 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
9855 | ||
9856 | static const reg_entry * | |
9857 | parse_register (char *reg_string, char **end_op) | |
9858 | { | |
9859 | const reg_entry *r; | |
9860 | ||
9861 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
9862 | r = parse_real_register (reg_string, end_op); | |
9863 | else | |
9864 | r = NULL; | |
9865 | if (!r) | |
9866 | { | |
9867 | char *save = input_line_pointer; | |
9868 | char c; | |
9869 | symbolS *symbolP; | |
9870 | ||
9871 | input_line_pointer = reg_string; | |
d02603dc | 9872 | c = get_symbol_name (®_string); |
4d1bb795 JB |
9873 | symbolP = symbol_find (reg_string); |
9874 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
9875 | { | |
9876 | const expressionS *e = symbol_get_value_expression (symbolP); | |
9877 | ||
0398aac5 | 9878 | know (e->X_op == O_register); |
4eed87de | 9879 | know (e->X_add_number >= 0 |
c3fe08fa | 9880 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 9881 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 9882 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 9883 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
9884 | *end_op = input_line_pointer; |
9885 | } | |
9886 | *input_line_pointer = c; | |
9887 | input_line_pointer = save; | |
9888 | } | |
9889 | return r; | |
9890 | } | |
9891 | ||
9892 | int | |
9893 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
9894 | { | |
9895 | const reg_entry *r; | |
9896 | char *end = input_line_pointer; | |
9897 | ||
9898 | *end = *nextcharP; | |
9899 | r = parse_register (name, &input_line_pointer); | |
9900 | if (r && end <= input_line_pointer) | |
9901 | { | |
9902 | *nextcharP = *input_line_pointer; | |
9903 | *input_line_pointer = 0; | |
9904 | e->X_op = O_register; | |
9905 | e->X_add_number = r - i386_regtab; | |
9906 | return 1; | |
9907 | } | |
9908 | input_line_pointer = end; | |
9909 | *end = 0; | |
ee86248c | 9910 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
9911 | } |
9912 | ||
9913 | void | |
9914 | md_operand (expressionS *e) | |
9915 | { | |
ee86248c JB |
9916 | char *end; |
9917 | const reg_entry *r; | |
4d1bb795 | 9918 | |
ee86248c JB |
9919 | switch (*input_line_pointer) |
9920 | { | |
9921 | case REGISTER_PREFIX: | |
9922 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
9923 | if (r) |
9924 | { | |
9925 | e->X_op = O_register; | |
9926 | e->X_add_number = r - i386_regtab; | |
9927 | input_line_pointer = end; | |
9928 | } | |
ee86248c JB |
9929 | break; |
9930 | ||
9931 | case '[': | |
9c2799c2 | 9932 | gas_assert (intel_syntax); |
ee86248c JB |
9933 | end = input_line_pointer++; |
9934 | expression (e); | |
9935 | if (*input_line_pointer == ']') | |
9936 | { | |
9937 | ++input_line_pointer; | |
9938 | e->X_op_symbol = make_expr_symbol (e); | |
9939 | e->X_add_symbol = NULL; | |
9940 | e->X_add_number = 0; | |
9941 | e->X_op = O_index; | |
9942 | } | |
9943 | else | |
9944 | { | |
9945 | e->X_op = O_absent; | |
9946 | input_line_pointer = end; | |
9947 | } | |
9948 | break; | |
4d1bb795 JB |
9949 | } |
9950 | } | |
9951 | ||
252b5132 | 9952 | \f |
4cc782b5 | 9953 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 9954 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 9955 | #else |
12b55ccc | 9956 | const char *md_shortopts = "qn"; |
252b5132 | 9957 | #endif |
6e0b89ee | 9958 | |
3e73aa7c | 9959 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
9960 | #define OPTION_64 (OPTION_MD_BASE + 1) |
9961 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
9962 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
9963 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
9964 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
9965 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
9966 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
9967 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
9968 | #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) | |
c0f3af97 | 9969 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 9970 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
9971 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
9972 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
9973 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 9974 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
9975 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
9976 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 9977 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 9978 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 9979 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 9980 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
9981 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
9982 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 9983 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
0cb4071e | 9984 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25) |
b3b91714 | 9985 | |
99ad8390 NC |
9986 | struct option md_longopts[] = |
9987 | { | |
3e73aa7c | 9988 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 9989 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 9990 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 9991 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
9992 | #endif |
9993 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 9994 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 9995 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
6e0b89ee | 9996 | #endif |
b3b91714 | 9997 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
9998 | {"march", required_argument, NULL, OPTION_MARCH}, |
9999 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
10000 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
10001 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
10002 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
10003 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
10004 | {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, | |
c0f3af97 | 10005 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 10006 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 10007 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 10008 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
7e8b059b | 10009 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
10010 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
10011 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
10012 | # if defined (TE_PE) || defined (TE_PEP) |
10013 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
10014 | #endif | |
d1982f93 | 10015 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 10016 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 10017 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 10018 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
5db04b09 L |
10019 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
10020 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
10021 | {NULL, no_argument, NULL, 0} |
10022 | }; | |
10023 | size_t md_longopts_size = sizeof (md_longopts); | |
10024 | ||
10025 | int | |
17b9d67d | 10026 | md_parse_option (int c, const char *arg) |
252b5132 | 10027 | { |
91d6fa6a | 10028 | unsigned int j; |
293f5f65 | 10029 | char *arch, *next, *saved; |
9103f4f4 | 10030 | |
252b5132 RH |
10031 | switch (c) |
10032 | { | |
12b55ccc L |
10033 | case 'n': |
10034 | optimize_align_code = 0; | |
10035 | break; | |
10036 | ||
a38cf1db AM |
10037 | case 'q': |
10038 | quiet_warnings = 1; | |
252b5132 RH |
10039 | break; |
10040 | ||
10041 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
10042 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
10043 | should be emitted or not. FIXME: Not implemented. */ | |
10044 | case 'Q': | |
252b5132 RH |
10045 | break; |
10046 | ||
10047 | /* -V: SVR4 argument to print version ID. */ | |
10048 | case 'V': | |
10049 | print_version_id (); | |
10050 | break; | |
10051 | ||
a38cf1db AM |
10052 | /* -k: Ignore for FreeBSD compatibility. */ |
10053 | case 'k': | |
252b5132 | 10054 | break; |
4cc782b5 ILT |
10055 | |
10056 | case 's': | |
10057 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 10058 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 10059 | break; |
8dcea932 L |
10060 | |
10061 | case OPTION_MSHARED: | |
10062 | shared = 1; | |
10063 | break; | |
99ad8390 | 10064 | #endif |
321098a5 | 10065 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 10066 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
10067 | case OPTION_64: |
10068 | { | |
10069 | const char **list, **l; | |
10070 | ||
3e73aa7c JH |
10071 | list = bfd_target_list (); |
10072 | for (l = list; *l != NULL; l++) | |
8620418b | 10073 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
10074 | || strcmp (*l, "coff-x86-64") == 0 |
10075 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
10076 | || strcmp (*l, "pei-x86-64") == 0 |
10077 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
10078 | { |
10079 | default_arch = "x86_64"; | |
10080 | break; | |
10081 | } | |
3e73aa7c | 10082 | if (*l == NULL) |
2b5d6a91 | 10083 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
10084 | free (list); |
10085 | } | |
10086 | break; | |
10087 | #endif | |
252b5132 | 10088 | |
351f65ca | 10089 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 10090 | case OPTION_X32: |
351f65ca L |
10091 | if (IS_ELF) |
10092 | { | |
10093 | const char **list, **l; | |
10094 | ||
10095 | list = bfd_target_list (); | |
10096 | for (l = list; *l != NULL; l++) | |
10097 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
10098 | { | |
10099 | default_arch = "x86_64:32"; | |
10100 | break; | |
10101 | } | |
10102 | if (*l == NULL) | |
2b5d6a91 | 10103 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
10104 | free (list); |
10105 | } | |
10106 | else | |
10107 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
10108 | break; | |
10109 | #endif | |
10110 | ||
6e0b89ee AM |
10111 | case OPTION_32: |
10112 | default_arch = "i386"; | |
10113 | break; | |
10114 | ||
b3b91714 AM |
10115 | case OPTION_DIVIDE: |
10116 | #ifdef SVR4_COMMENT_CHARS | |
10117 | { | |
10118 | char *n, *t; | |
10119 | const char *s; | |
10120 | ||
add39d23 | 10121 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
10122 | t = n; |
10123 | for (s = i386_comment_chars; *s != '\0'; s++) | |
10124 | if (*s != '/') | |
10125 | *t++ = *s; | |
10126 | *t = '\0'; | |
10127 | i386_comment_chars = n; | |
10128 | } | |
10129 | #endif | |
10130 | break; | |
10131 | ||
9103f4f4 | 10132 | case OPTION_MARCH: |
293f5f65 L |
10133 | saved = xstrdup (arg); |
10134 | arch = saved; | |
10135 | /* Allow -march=+nosse. */ | |
10136 | if (*arch == '+') | |
10137 | arch++; | |
6305a203 | 10138 | do |
9103f4f4 | 10139 | { |
6305a203 | 10140 | if (*arch == '.') |
2b5d6a91 | 10141 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
10142 | next = strchr (arch, '+'); |
10143 | if (next) | |
10144 | *next++ = '\0'; | |
91d6fa6a | 10145 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 10146 | { |
91d6fa6a | 10147 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 10148 | { |
6305a203 | 10149 | /* Processor. */ |
1ded5609 JB |
10150 | if (! cpu_arch[j].flags.bitfield.cpui386) |
10151 | continue; | |
10152 | ||
91d6fa6a | 10153 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 10154 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
10155 | cpu_arch_flags = cpu_arch[j].flags; |
10156 | cpu_arch_isa = cpu_arch[j].type; | |
10157 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
10158 | if (!cpu_arch_tune_set) |
10159 | { | |
10160 | cpu_arch_tune = cpu_arch_isa; | |
10161 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
10162 | } | |
10163 | break; | |
10164 | } | |
91d6fa6a NC |
10165 | else if (*cpu_arch [j].name == '.' |
10166 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 10167 | { |
33eaf5de | 10168 | /* ISA extension. */ |
6305a203 | 10169 | i386_cpu_flags flags; |
309d3373 | 10170 | |
293f5f65 L |
10171 | flags = cpu_flags_or (cpu_arch_flags, |
10172 | cpu_arch[j].flags); | |
81486035 | 10173 | |
5b64d091 | 10174 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
10175 | { |
10176 | if (cpu_sub_arch_name) | |
10177 | { | |
10178 | char *name = cpu_sub_arch_name; | |
10179 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 10180 | cpu_arch[j].name, |
1bf57e9f | 10181 | (const char *) NULL); |
6305a203 L |
10182 | free (name); |
10183 | } | |
10184 | else | |
91d6fa6a | 10185 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 10186 | cpu_arch_flags = flags; |
a586129e | 10187 | cpu_arch_isa_flags = flags; |
6305a203 L |
10188 | } |
10189 | break; | |
ccc9c027 | 10190 | } |
9103f4f4 | 10191 | } |
6305a203 | 10192 | |
293f5f65 L |
10193 | if (j >= ARRAY_SIZE (cpu_arch)) |
10194 | { | |
33eaf5de | 10195 | /* Disable an ISA extension. */ |
293f5f65 L |
10196 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
10197 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
10198 | { | |
10199 | i386_cpu_flags flags; | |
10200 | ||
10201 | flags = cpu_flags_and_not (cpu_arch_flags, | |
10202 | cpu_noarch[j].flags); | |
10203 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
10204 | { | |
10205 | if (cpu_sub_arch_name) | |
10206 | { | |
10207 | char *name = cpu_sub_arch_name; | |
10208 | cpu_sub_arch_name = concat (arch, | |
10209 | (const char *) NULL); | |
10210 | free (name); | |
10211 | } | |
10212 | else | |
10213 | cpu_sub_arch_name = xstrdup (arch); | |
10214 | cpu_arch_flags = flags; | |
10215 | cpu_arch_isa_flags = flags; | |
10216 | } | |
10217 | break; | |
10218 | } | |
10219 | ||
10220 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
10221 | j = ARRAY_SIZE (cpu_arch); | |
10222 | } | |
10223 | ||
91d6fa6a | 10224 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 10225 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
10226 | |
10227 | arch = next; | |
9103f4f4 | 10228 | } |
293f5f65 L |
10229 | while (next != NULL); |
10230 | free (saved); | |
9103f4f4 L |
10231 | break; |
10232 | ||
10233 | case OPTION_MTUNE: | |
10234 | if (*arg == '.') | |
2b5d6a91 | 10235 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 10236 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 10237 | { |
91d6fa6a | 10238 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 10239 | { |
ccc9c027 | 10240 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
10241 | cpu_arch_tune = cpu_arch [j].type; |
10242 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
10243 | break; |
10244 | } | |
10245 | } | |
91d6fa6a | 10246 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 10247 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
10248 | break; |
10249 | ||
1efbbeb4 L |
10250 | case OPTION_MMNEMONIC: |
10251 | if (strcasecmp (arg, "att") == 0) | |
10252 | intel_mnemonic = 0; | |
10253 | else if (strcasecmp (arg, "intel") == 0) | |
10254 | intel_mnemonic = 1; | |
10255 | else | |
2b5d6a91 | 10256 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
10257 | break; |
10258 | ||
10259 | case OPTION_MSYNTAX: | |
10260 | if (strcasecmp (arg, "att") == 0) | |
10261 | intel_syntax = 0; | |
10262 | else if (strcasecmp (arg, "intel") == 0) | |
10263 | intel_syntax = 1; | |
10264 | else | |
2b5d6a91 | 10265 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
10266 | break; |
10267 | ||
10268 | case OPTION_MINDEX_REG: | |
10269 | allow_index_reg = 1; | |
10270 | break; | |
10271 | ||
10272 | case OPTION_MNAKED_REG: | |
10273 | allow_naked_reg = 1; | |
10274 | break; | |
10275 | ||
10276 | case OPTION_MOLD_GCC: | |
10277 | old_gcc = 1; | |
1efbbeb4 L |
10278 | break; |
10279 | ||
c0f3af97 L |
10280 | case OPTION_MSSE2AVX: |
10281 | sse2avx = 1; | |
10282 | break; | |
10283 | ||
daf50ae7 L |
10284 | case OPTION_MSSE_CHECK: |
10285 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 10286 | sse_check = check_error; |
daf50ae7 | 10287 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 10288 | sse_check = check_warning; |
daf50ae7 | 10289 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 10290 | sse_check = check_none; |
daf50ae7 | 10291 | else |
2b5d6a91 | 10292 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
10293 | break; |
10294 | ||
7bab8ab5 JB |
10295 | case OPTION_MOPERAND_CHECK: |
10296 | if (strcasecmp (arg, "error") == 0) | |
10297 | operand_check = check_error; | |
10298 | else if (strcasecmp (arg, "warning") == 0) | |
10299 | operand_check = check_warning; | |
10300 | else if (strcasecmp (arg, "none") == 0) | |
10301 | operand_check = check_none; | |
10302 | else | |
10303 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
10304 | break; | |
10305 | ||
539f890d L |
10306 | case OPTION_MAVXSCALAR: |
10307 | if (strcasecmp (arg, "128") == 0) | |
10308 | avxscalar = vex128; | |
10309 | else if (strcasecmp (arg, "256") == 0) | |
10310 | avxscalar = vex256; | |
10311 | else | |
2b5d6a91 | 10312 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
10313 | break; |
10314 | ||
7e8b059b L |
10315 | case OPTION_MADD_BND_PREFIX: |
10316 | add_bnd_prefix = 1; | |
10317 | break; | |
10318 | ||
43234a1e L |
10319 | case OPTION_MEVEXLIG: |
10320 | if (strcmp (arg, "128") == 0) | |
10321 | evexlig = evexl128; | |
10322 | else if (strcmp (arg, "256") == 0) | |
10323 | evexlig = evexl256; | |
10324 | else if (strcmp (arg, "512") == 0) | |
10325 | evexlig = evexl512; | |
10326 | else | |
10327 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
10328 | break; | |
10329 | ||
d3d3c6db IT |
10330 | case OPTION_MEVEXRCIG: |
10331 | if (strcmp (arg, "rne") == 0) | |
10332 | evexrcig = rne; | |
10333 | else if (strcmp (arg, "rd") == 0) | |
10334 | evexrcig = rd; | |
10335 | else if (strcmp (arg, "ru") == 0) | |
10336 | evexrcig = ru; | |
10337 | else if (strcmp (arg, "rz") == 0) | |
10338 | evexrcig = rz; | |
10339 | else | |
10340 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
10341 | break; | |
10342 | ||
43234a1e L |
10343 | case OPTION_MEVEXWIG: |
10344 | if (strcmp (arg, "0") == 0) | |
10345 | evexwig = evexw0; | |
10346 | else if (strcmp (arg, "1") == 0) | |
10347 | evexwig = evexw1; | |
10348 | else | |
10349 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
10350 | break; | |
10351 | ||
167ad85b TG |
10352 | # if defined (TE_PE) || defined (TE_PEP) |
10353 | case OPTION_MBIG_OBJ: | |
10354 | use_big_obj = 1; | |
10355 | break; | |
10356 | #endif | |
10357 | ||
d1982f93 | 10358 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
10359 | if (strcasecmp (arg, "yes") == 0) |
10360 | omit_lock_prefix = 1; | |
10361 | else if (strcasecmp (arg, "no") == 0) | |
10362 | omit_lock_prefix = 0; | |
10363 | else | |
10364 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
10365 | break; | |
10366 | ||
e4e00185 AS |
10367 | case OPTION_MFENCE_AS_LOCK_ADD: |
10368 | if (strcasecmp (arg, "yes") == 0) | |
10369 | avoid_fence = 1; | |
10370 | else if (strcasecmp (arg, "no") == 0) | |
10371 | avoid_fence = 0; | |
10372 | else | |
10373 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
10374 | break; | |
10375 | ||
0cb4071e L |
10376 | case OPTION_MRELAX_RELOCATIONS: |
10377 | if (strcasecmp (arg, "yes") == 0) | |
10378 | generate_relax_relocations = 1; | |
10379 | else if (strcasecmp (arg, "no") == 0) | |
10380 | generate_relax_relocations = 0; | |
10381 | else | |
10382 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
10383 | break; | |
10384 | ||
5db04b09 | 10385 | case OPTION_MAMD64: |
e89c5eaa | 10386 | intel64 = 0; |
5db04b09 L |
10387 | break; |
10388 | ||
10389 | case OPTION_MINTEL64: | |
e89c5eaa | 10390 | intel64 = 1; |
5db04b09 L |
10391 | break; |
10392 | ||
252b5132 RH |
10393 | default: |
10394 | return 0; | |
10395 | } | |
10396 | return 1; | |
10397 | } | |
10398 | ||
8a2c8fef L |
10399 | #define MESSAGE_TEMPLATE \ |
10400 | " " | |
10401 | ||
293f5f65 L |
10402 | static char * |
10403 | output_message (FILE *stream, char *p, char *message, char *start, | |
10404 | int *left_p, const char *name, int len) | |
10405 | { | |
10406 | int size = sizeof (MESSAGE_TEMPLATE); | |
10407 | int left = *left_p; | |
10408 | ||
10409 | /* Reserve 2 spaces for ", " or ",\0" */ | |
10410 | left -= len + 2; | |
10411 | ||
10412 | /* Check if there is any room. */ | |
10413 | if (left >= 0) | |
10414 | { | |
10415 | if (p != start) | |
10416 | { | |
10417 | *p++ = ','; | |
10418 | *p++ = ' '; | |
10419 | } | |
10420 | p = mempcpy (p, name, len); | |
10421 | } | |
10422 | else | |
10423 | { | |
10424 | /* Output the current message now and start a new one. */ | |
10425 | *p++ = ','; | |
10426 | *p = '\0'; | |
10427 | fprintf (stream, "%s\n", message); | |
10428 | p = start; | |
10429 | left = size - (start - message) - len - 2; | |
10430 | ||
10431 | gas_assert (left >= 0); | |
10432 | ||
10433 | p = mempcpy (p, name, len); | |
10434 | } | |
10435 | ||
10436 | *left_p = left; | |
10437 | return p; | |
10438 | } | |
10439 | ||
8a2c8fef | 10440 | static void |
1ded5609 | 10441 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
10442 | { |
10443 | static char message[] = MESSAGE_TEMPLATE; | |
10444 | char *start = message + 27; | |
10445 | char *p; | |
10446 | int size = sizeof (MESSAGE_TEMPLATE); | |
10447 | int left; | |
10448 | const char *name; | |
10449 | int len; | |
10450 | unsigned int j; | |
10451 | ||
10452 | p = start; | |
10453 | left = size - (start - message); | |
10454 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
10455 | { | |
10456 | /* Should it be skipped? */ | |
10457 | if (cpu_arch [j].skip) | |
10458 | continue; | |
10459 | ||
10460 | name = cpu_arch [j].name; | |
10461 | len = cpu_arch [j].len; | |
10462 | if (*name == '.') | |
10463 | { | |
10464 | /* It is an extension. Skip if we aren't asked to show it. */ | |
10465 | if (ext) | |
10466 | { | |
10467 | name++; | |
10468 | len--; | |
10469 | } | |
10470 | else | |
10471 | continue; | |
10472 | } | |
10473 | else if (ext) | |
10474 | { | |
10475 | /* It is an processor. Skip if we show only extension. */ | |
10476 | continue; | |
10477 | } | |
1ded5609 JB |
10478 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
10479 | { | |
10480 | /* It is an impossible processor - skip. */ | |
10481 | continue; | |
10482 | } | |
8a2c8fef | 10483 | |
293f5f65 | 10484 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
10485 | } |
10486 | ||
293f5f65 L |
10487 | /* Display disabled extensions. */ |
10488 | if (ext) | |
10489 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
10490 | { | |
10491 | name = cpu_noarch [j].name; | |
10492 | len = cpu_noarch [j].len; | |
10493 | p = output_message (stream, p, message, start, &left, name, | |
10494 | len); | |
10495 | } | |
10496 | ||
8a2c8fef L |
10497 | *p = '\0'; |
10498 | fprintf (stream, "%s\n", message); | |
10499 | } | |
10500 | ||
252b5132 | 10501 | void |
8a2c8fef | 10502 | md_show_usage (FILE *stream) |
252b5132 | 10503 | { |
4cc782b5 ILT |
10504 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10505 | fprintf (stream, _("\ | |
a38cf1db AM |
10506 | -Q ignored\n\ |
10507 | -V print assembler version number\n\ | |
b3b91714 AM |
10508 | -k ignored\n")); |
10509 | #endif | |
10510 | fprintf (stream, _("\ | |
12b55ccc | 10511 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
10512 | -q quieten some warnings\n")); |
10513 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
10514 | fprintf (stream, _("\ | |
a38cf1db | 10515 | -s ignored\n")); |
b3b91714 | 10516 | #endif |
321098a5 L |
10517 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
10518 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 10519 | fprintf (stream, _("\ |
570561f7 | 10520 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 10521 | #endif |
b3b91714 AM |
10522 | #ifdef SVR4_COMMENT_CHARS |
10523 | fprintf (stream, _("\ | |
10524 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
10525 | #else |
10526 | fprintf (stream, _("\ | |
b3b91714 | 10527 | --divide ignored\n")); |
4cc782b5 | 10528 | #endif |
9103f4f4 | 10529 | fprintf (stream, _("\ |
6305a203 | 10530 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 10531 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 10532 | show_arch (stream, 0, 1); |
8a2c8fef L |
10533 | fprintf (stream, _("\ |
10534 | EXTENSION is combination of:\n")); | |
1ded5609 | 10535 | show_arch (stream, 1, 0); |
6305a203 | 10536 | fprintf (stream, _("\ |
8a2c8fef | 10537 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 10538 | show_arch (stream, 0, 0); |
ba104c83 | 10539 | fprintf (stream, _("\ |
c0f3af97 L |
10540 | -msse2avx encode SSE instructions with VEX prefix\n")); |
10541 | fprintf (stream, _("\ | |
daf50ae7 L |
10542 | -msse-check=[none|error|warning]\n\ |
10543 | check SSE instructions\n")); | |
10544 | fprintf (stream, _("\ | |
7bab8ab5 JB |
10545 | -moperand-check=[none|error|warning]\n\ |
10546 | check operand combinations for validity\n")); | |
10547 | fprintf (stream, _("\ | |
539f890d L |
10548 | -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\ |
10549 | length\n")); | |
10550 | fprintf (stream, _("\ | |
43234a1e L |
10551 | -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\ |
10552 | length\n")); | |
10553 | fprintf (stream, _("\ | |
10554 | -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\ | |
10555 | for EVEX.W bit ignored instructions\n")); | |
10556 | fprintf (stream, _("\ | |
d3d3c6db IT |
10557 | -mevexrcig=[rne|rd|ru|rz]\n\ |
10558 | encode EVEX instructions with specific EVEX.RC value\n\ | |
10559 | for SAE-only ignored instructions\n")); | |
10560 | fprintf (stream, _("\ | |
ba104c83 L |
10561 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); |
10562 | fprintf (stream, _("\ | |
10563 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); | |
10564 | fprintf (stream, _("\ | |
10565 | -mindex-reg support pseudo index registers\n")); | |
10566 | fprintf (stream, _("\ | |
10567 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
10568 | fprintf (stream, _("\ | |
10569 | -mold-gcc support old (<= 2.8.1) versions of gcc\n")); | |
7e8b059b L |
10570 | fprintf (stream, _("\ |
10571 | -madd-bnd-prefix add BND prefix for all valid branches\n")); | |
8dcea932 L |
10572 | fprintf (stream, _("\ |
10573 | -mshared disable branch optimization for shared code\n")); | |
167ad85b TG |
10574 | # if defined (TE_PE) || defined (TE_PEP) |
10575 | fprintf (stream, _("\ | |
10576 | -mbig-obj generate big object files\n")); | |
10577 | #endif | |
d022bddd IT |
10578 | fprintf (stream, _("\ |
10579 | -momit-lock-prefix=[no|yes]\n\ | |
10580 | strip all lock prefixes\n")); | |
5db04b09 | 10581 | fprintf (stream, _("\ |
e4e00185 AS |
10582 | -mfence-as-lock-add=[no|yes]\n\ |
10583 | encode lfence, mfence and sfence as\n\ | |
10584 | lock addl $0x0, (%%{re}sp)\n")); | |
10585 | fprintf (stream, _("\ | |
0cb4071e L |
10586 | -mrelax-relocations=[no|yes]\n\ |
10587 | generate relax relocations\n")); | |
10588 | fprintf (stream, _("\ | |
5db04b09 L |
10589 | -mamd64 accept only AMD64 ISA\n")); |
10590 | fprintf (stream, _("\ | |
10591 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
10592 | } |
10593 | ||
3e73aa7c | 10594 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 10595 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 10596 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
10597 | |
10598 | /* Pick the target format to use. */ | |
10599 | ||
47926f60 | 10600 | const char * |
e3bb37b5 | 10601 | i386_target_format (void) |
252b5132 | 10602 | { |
351f65ca L |
10603 | if (!strncmp (default_arch, "x86_64", 6)) |
10604 | { | |
10605 | update_code_flag (CODE_64BIT, 1); | |
10606 | if (default_arch[6] == '\0') | |
7f56bc95 | 10607 | x86_elf_abi = X86_64_ABI; |
351f65ca | 10608 | else |
7f56bc95 | 10609 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 10610 | } |
3e73aa7c | 10611 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 10612 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
10613 | else if (!strcmp (default_arch, "iamcu")) |
10614 | { | |
10615 | update_code_flag (CODE_32BIT, 1); | |
10616 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
10617 | { | |
10618 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
10619 | cpu_arch_name = "iamcu"; | |
10620 | cpu_sub_arch_name = NULL; | |
10621 | cpu_arch_flags = iamcu_flags; | |
10622 | cpu_arch_isa = PROCESSOR_IAMCU; | |
10623 | cpu_arch_isa_flags = iamcu_flags; | |
10624 | if (!cpu_arch_tune_set) | |
10625 | { | |
10626 | cpu_arch_tune = cpu_arch_isa; | |
10627 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
10628 | } | |
10629 | } | |
8d471ec1 | 10630 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
10631 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
10632 | cpu_arch_name); | |
10633 | } | |
3e73aa7c | 10634 | else |
2b5d6a91 | 10635 | as_fatal (_("unknown architecture")); |
89507696 JB |
10636 | |
10637 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
10638 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
10639 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
10640 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
10641 | ||
252b5132 RH |
10642 | switch (OUTPUT_FLAVOR) |
10643 | { | |
9384f2ff | 10644 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 10645 | case bfd_target_aout_flavour: |
47926f60 | 10646 | return AOUT_TARGET_FORMAT; |
4c63da97 | 10647 | #endif |
9384f2ff AM |
10648 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
10649 | # if defined (TE_PE) || defined (TE_PEP) | |
10650 | case bfd_target_coff_flavour: | |
167ad85b TG |
10651 | if (flag_code == CODE_64BIT) |
10652 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
10653 | else | |
10654 | return "pe-i386"; | |
9384f2ff | 10655 | # elif defined (TE_GO32) |
0561d57c JK |
10656 | case bfd_target_coff_flavour: |
10657 | return "coff-go32"; | |
9384f2ff | 10658 | # else |
252b5132 RH |
10659 | case bfd_target_coff_flavour: |
10660 | return "coff-i386"; | |
9384f2ff | 10661 | # endif |
4c63da97 | 10662 | #endif |
3e73aa7c | 10663 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 10664 | case bfd_target_elf_flavour: |
3e73aa7c | 10665 | { |
351f65ca L |
10666 | const char *format; |
10667 | ||
10668 | switch (x86_elf_abi) | |
4fa24527 | 10669 | { |
351f65ca L |
10670 | default: |
10671 | format = ELF_TARGET_FORMAT; | |
10672 | break; | |
7f56bc95 | 10673 | case X86_64_ABI: |
351f65ca | 10674 | use_rela_relocations = 1; |
4fa24527 | 10675 | object_64bit = 1; |
351f65ca L |
10676 | format = ELF_TARGET_FORMAT64; |
10677 | break; | |
7f56bc95 | 10678 | case X86_64_X32_ABI: |
4fa24527 | 10679 | use_rela_relocations = 1; |
351f65ca | 10680 | object_64bit = 1; |
862be3fb | 10681 | disallow_64bit_reloc = 1; |
351f65ca L |
10682 | format = ELF_TARGET_FORMAT32; |
10683 | break; | |
4fa24527 | 10684 | } |
3632d14b | 10685 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 10686 | { |
7f56bc95 | 10687 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
10688 | as_fatal (_("Intel L1OM is 64bit only")); |
10689 | return ELF_TARGET_L1OM_FORMAT; | |
10690 | } | |
b49f93f6 | 10691 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
10692 | { |
10693 | if (x86_elf_abi != X86_64_ABI) | |
10694 | as_fatal (_("Intel K1OM is 64bit only")); | |
10695 | return ELF_TARGET_K1OM_FORMAT; | |
10696 | } | |
81486035 L |
10697 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
10698 | { | |
10699 | if (x86_elf_abi != I386_ABI) | |
10700 | as_fatal (_("Intel MCU is 32bit only")); | |
10701 | return ELF_TARGET_IAMCU_FORMAT; | |
10702 | } | |
8a9036a4 | 10703 | else |
351f65ca | 10704 | return format; |
3e73aa7c | 10705 | } |
e57f8c65 TG |
10706 | #endif |
10707 | #if defined (OBJ_MACH_O) | |
10708 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
10709 | if (flag_code == CODE_64BIT) |
10710 | { | |
10711 | use_rela_relocations = 1; | |
10712 | object_64bit = 1; | |
10713 | return "mach-o-x86-64"; | |
10714 | } | |
10715 | else | |
10716 | return "mach-o-i386"; | |
4c63da97 | 10717 | #endif |
252b5132 RH |
10718 | default: |
10719 | abort (); | |
10720 | return NULL; | |
10721 | } | |
10722 | } | |
10723 | ||
47926f60 | 10724 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 10725 | \f |
252b5132 | 10726 | symbolS * |
7016a5d5 | 10727 | md_undefined_symbol (char *name) |
252b5132 | 10728 | { |
18dc2407 ILT |
10729 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
10730 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
10731 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
10732 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
10733 | { |
10734 | if (!GOT_symbol) | |
10735 | { | |
10736 | if (symbol_find (name)) | |
10737 | as_bad (_("GOT already in symbol table")); | |
10738 | GOT_symbol = symbol_new (name, undefined_section, | |
10739 | (valueT) 0, &zero_address_frag); | |
10740 | }; | |
10741 | return GOT_symbol; | |
10742 | } | |
252b5132 RH |
10743 | return 0; |
10744 | } | |
10745 | ||
10746 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 10747 | |
252b5132 | 10748 | valueT |
7016a5d5 | 10749 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 10750 | { |
4c63da97 AM |
10751 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
10752 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
10753 | { | |
10754 | /* For a.out, force the section size to be aligned. If we don't do | |
10755 | this, BFD will align it for us, but it will not write out the | |
10756 | final bytes of the section. This may be a bug in BFD, but it is | |
10757 | easier to fix it here since that is how the other a.out targets | |
10758 | work. */ | |
10759 | int align; | |
10760 | ||
10761 | align = bfd_get_section_alignment (stdoutput, segment); | |
8d3842cd | 10762 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 10763 | } |
252b5132 RH |
10764 | #endif |
10765 | ||
10766 | return size; | |
10767 | } | |
10768 | ||
10769 | /* On the i386, PC-relative offsets are relative to the start of the | |
10770 | next instruction. That is, the address of the offset, plus its | |
10771 | size, since the offset is always the last part of the insn. */ | |
10772 | ||
10773 | long | |
e3bb37b5 | 10774 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
10775 | { |
10776 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
10777 | } | |
10778 | ||
10779 | #ifndef I386COFF | |
10780 | ||
10781 | static void | |
e3bb37b5 | 10782 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 10783 | { |
29b0f896 | 10784 | int temp; |
252b5132 | 10785 | |
8a75718c JB |
10786 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10787 | if (IS_ELF) | |
10788 | obj_elf_section_change_hook (); | |
10789 | #endif | |
252b5132 RH |
10790 | temp = get_absolute_expression (); |
10791 | subseg_set (bss_section, (subsegT) temp); | |
10792 | demand_empty_rest_of_line (); | |
10793 | } | |
10794 | ||
10795 | #endif | |
10796 | ||
252b5132 | 10797 | void |
e3bb37b5 | 10798 | i386_validate_fix (fixS *fixp) |
252b5132 | 10799 | { |
02a86693 | 10800 | if (fixp->fx_subsy) |
252b5132 | 10801 | { |
02a86693 | 10802 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 10803 | { |
02a86693 L |
10804 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
10805 | { | |
10806 | if (!object_64bit) | |
10807 | abort (); | |
10808 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
10809 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
10810 | fixp->fx_r_type = (fixp->fx_tcbit |
10811 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
10812 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
10813 | else |
10814 | #endif | |
10815 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
10816 | } | |
d6ab8113 | 10817 | else |
02a86693 L |
10818 | { |
10819 | if (!object_64bit) | |
10820 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
10821 | else | |
10822 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
10823 | } | |
10824 | fixp->fx_subsy = 0; | |
23df1078 | 10825 | } |
252b5132 | 10826 | } |
02a86693 L |
10827 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10828 | else if (!object_64bit) | |
10829 | { | |
10830 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
10831 | && fixp->fx_tcbit2) | |
10832 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
10833 | } | |
10834 | #endif | |
252b5132 RH |
10835 | } |
10836 | ||
252b5132 | 10837 | arelent * |
7016a5d5 | 10838 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
10839 | { |
10840 | arelent *rel; | |
10841 | bfd_reloc_code_real_type code; | |
10842 | ||
10843 | switch (fixp->fx_r_type) | |
10844 | { | |
8ce3d284 | 10845 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
10846 | case BFD_RELOC_SIZE32: |
10847 | case BFD_RELOC_SIZE64: | |
10848 | if (S_IS_DEFINED (fixp->fx_addsy) | |
10849 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
10850 | { | |
10851 | /* Resolve size relocation against local symbol to size of | |
10852 | the symbol plus addend. */ | |
10853 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
10854 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
10855 | && !fits_in_unsigned_long (value)) | |
10856 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
10857 | _("symbol size computation overflow")); | |
10858 | fixp->fx_addsy = NULL; | |
10859 | fixp->fx_subsy = NULL; | |
10860 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
10861 | return NULL; | |
10862 | } | |
8ce3d284 | 10863 | #endif |
1a0670f3 | 10864 | /* Fall through. */ |
8fd4256d | 10865 | |
3e73aa7c JH |
10866 | case BFD_RELOC_X86_64_PLT32: |
10867 | case BFD_RELOC_X86_64_GOT32: | |
10868 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
10869 | case BFD_RELOC_X86_64_GOTPCRELX: |
10870 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
10871 | case BFD_RELOC_386_PLT32: |
10872 | case BFD_RELOC_386_GOT32: | |
02a86693 | 10873 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
10874 | case BFD_RELOC_386_GOTOFF: |
10875 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
10876 | case BFD_RELOC_386_TLS_GD: |
10877 | case BFD_RELOC_386_TLS_LDM: | |
10878 | case BFD_RELOC_386_TLS_LDO_32: | |
10879 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
10880 | case BFD_RELOC_386_TLS_IE: |
10881 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
10882 | case BFD_RELOC_386_TLS_LE_32: |
10883 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
10884 | case BFD_RELOC_386_TLS_GOTDESC: |
10885 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
10886 | case BFD_RELOC_X86_64_TLSGD: |
10887 | case BFD_RELOC_X86_64_TLSLD: | |
10888 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 10889 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
10890 | case BFD_RELOC_X86_64_GOTTPOFF: |
10891 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
10892 | case BFD_RELOC_X86_64_TPOFF64: |
10893 | case BFD_RELOC_X86_64_GOTOFF64: | |
10894 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
10895 | case BFD_RELOC_X86_64_GOT64: |
10896 | case BFD_RELOC_X86_64_GOTPCREL64: | |
10897 | case BFD_RELOC_X86_64_GOTPC64: | |
10898 | case BFD_RELOC_X86_64_GOTPLT64: | |
10899 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
10900 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
10901 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
10902 | case BFD_RELOC_RVA: |
10903 | case BFD_RELOC_VTABLE_ENTRY: | |
10904 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
10905 | #ifdef TE_PE |
10906 | case BFD_RELOC_32_SECREL: | |
10907 | #endif | |
252b5132 RH |
10908 | code = fixp->fx_r_type; |
10909 | break; | |
dbbaec26 L |
10910 | case BFD_RELOC_X86_64_32S: |
10911 | if (!fixp->fx_pcrel) | |
10912 | { | |
10913 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
10914 | code = fixp->fx_r_type; | |
10915 | break; | |
10916 | } | |
1a0670f3 | 10917 | /* Fall through. */ |
252b5132 | 10918 | default: |
93382f6d | 10919 | if (fixp->fx_pcrel) |
252b5132 | 10920 | { |
93382f6d AM |
10921 | switch (fixp->fx_size) |
10922 | { | |
10923 | default: | |
b091f402 AM |
10924 | as_bad_where (fixp->fx_file, fixp->fx_line, |
10925 | _("can not do %d byte pc-relative relocation"), | |
10926 | fixp->fx_size); | |
93382f6d AM |
10927 | code = BFD_RELOC_32_PCREL; |
10928 | break; | |
10929 | case 1: code = BFD_RELOC_8_PCREL; break; | |
10930 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 10931 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
10932 | #ifdef BFD64 |
10933 | case 8: code = BFD_RELOC_64_PCREL; break; | |
10934 | #endif | |
93382f6d AM |
10935 | } |
10936 | } | |
10937 | else | |
10938 | { | |
10939 | switch (fixp->fx_size) | |
10940 | { | |
10941 | default: | |
b091f402 AM |
10942 | as_bad_where (fixp->fx_file, fixp->fx_line, |
10943 | _("can not do %d byte relocation"), | |
10944 | fixp->fx_size); | |
93382f6d AM |
10945 | code = BFD_RELOC_32; |
10946 | break; | |
10947 | case 1: code = BFD_RELOC_8; break; | |
10948 | case 2: code = BFD_RELOC_16; break; | |
10949 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 10950 | #ifdef BFD64 |
3e73aa7c | 10951 | case 8: code = BFD_RELOC_64; break; |
937149dd | 10952 | #endif |
93382f6d | 10953 | } |
252b5132 RH |
10954 | } |
10955 | break; | |
10956 | } | |
252b5132 | 10957 | |
d182319b JB |
10958 | if ((code == BFD_RELOC_32 |
10959 | || code == BFD_RELOC_32_PCREL | |
10960 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
10961 | && GOT_symbol |
10962 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 10963 | { |
4fa24527 | 10964 | if (!object_64bit) |
d6ab8113 JB |
10965 | code = BFD_RELOC_386_GOTPC; |
10966 | else | |
10967 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 10968 | } |
7b81dfbb AJ |
10969 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
10970 | && GOT_symbol | |
10971 | && fixp->fx_addsy == GOT_symbol) | |
10972 | { | |
10973 | code = BFD_RELOC_X86_64_GOTPC64; | |
10974 | } | |
252b5132 | 10975 | |
add39d23 TS |
10976 | rel = XNEW (arelent); |
10977 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 10978 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
10979 | |
10980 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 10981 | |
3e73aa7c JH |
10982 | if (!use_rela_relocations) |
10983 | { | |
10984 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
10985 | vtable entry to be used in the relocation's section offset. */ | |
10986 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
10987 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
10988 | #if defined (OBJ_COFF) && defined (TE_PE) |
10989 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
10990 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
10991 | else | |
10992 | #endif | |
c6682705 | 10993 | rel->addend = 0; |
3e73aa7c JH |
10994 | } |
10995 | /* Use the rela in 64bit mode. */ | |
252b5132 | 10996 | else |
3e73aa7c | 10997 | { |
862be3fb L |
10998 | if (disallow_64bit_reloc) |
10999 | switch (code) | |
11000 | { | |
862be3fb L |
11001 | case BFD_RELOC_X86_64_DTPOFF64: |
11002 | case BFD_RELOC_X86_64_TPOFF64: | |
11003 | case BFD_RELOC_64_PCREL: | |
11004 | case BFD_RELOC_X86_64_GOTOFF64: | |
11005 | case BFD_RELOC_X86_64_GOT64: | |
11006 | case BFD_RELOC_X86_64_GOTPCREL64: | |
11007 | case BFD_RELOC_X86_64_GOTPC64: | |
11008 | case BFD_RELOC_X86_64_GOTPLT64: | |
11009 | case BFD_RELOC_X86_64_PLTOFF64: | |
11010 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11011 | _("cannot represent relocation type %s in x32 mode"), | |
11012 | bfd_get_reloc_code_name (code)); | |
11013 | break; | |
11014 | default: | |
11015 | break; | |
11016 | } | |
11017 | ||
062cd5e7 AS |
11018 | if (!fixp->fx_pcrel) |
11019 | rel->addend = fixp->fx_offset; | |
11020 | else | |
11021 | switch (code) | |
11022 | { | |
11023 | case BFD_RELOC_X86_64_PLT32: | |
11024 | case BFD_RELOC_X86_64_GOT32: | |
11025 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
11026 | case BFD_RELOC_X86_64_GOTPCRELX: |
11027 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
11028 | case BFD_RELOC_X86_64_TLSGD: |
11029 | case BFD_RELOC_X86_64_TLSLD: | |
11030 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
11031 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
11032 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
11033 | rel->addend = fixp->fx_offset - fixp->fx_size; |
11034 | break; | |
11035 | default: | |
11036 | rel->addend = (section->vma | |
11037 | - fixp->fx_size | |
11038 | + fixp->fx_addnumber | |
11039 | + md_pcrel_from (fixp)); | |
11040 | break; | |
11041 | } | |
3e73aa7c JH |
11042 | } |
11043 | ||
252b5132 RH |
11044 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
11045 | if (rel->howto == NULL) | |
11046 | { | |
11047 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 11048 | _("cannot represent relocation type %s"), |
252b5132 RH |
11049 | bfd_get_reloc_code_name (code)); |
11050 | /* Set howto to a garbage value so that we can keep going. */ | |
11051 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 11052 | gas_assert (rel->howto != NULL); |
252b5132 RH |
11053 | } |
11054 | ||
11055 | return rel; | |
11056 | } | |
11057 | ||
ee86248c | 11058 | #include "tc-i386-intel.c" |
54cfded0 | 11059 | |
a60de03c JB |
11060 | void |
11061 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 11062 | { |
a60de03c JB |
11063 | int saved_naked_reg; |
11064 | char saved_register_dot; | |
54cfded0 | 11065 | |
a60de03c JB |
11066 | saved_naked_reg = allow_naked_reg; |
11067 | allow_naked_reg = 1; | |
11068 | saved_register_dot = register_chars['.']; | |
11069 | register_chars['.'] = '.'; | |
11070 | allow_pseudo_reg = 1; | |
11071 | expression_and_evaluate (exp); | |
11072 | allow_pseudo_reg = 0; | |
11073 | register_chars['.'] = saved_register_dot; | |
11074 | allow_naked_reg = saved_naked_reg; | |
11075 | ||
e96d56a1 | 11076 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 11077 | { |
a60de03c JB |
11078 | if ((addressT) exp->X_add_number < i386_regtab_size) |
11079 | { | |
11080 | exp->X_op = O_constant; | |
11081 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
11082 | .dw2_regnum[flag_code >> 1]; | |
11083 | } | |
11084 | else | |
11085 | exp->X_op = O_illegal; | |
54cfded0 | 11086 | } |
54cfded0 AM |
11087 | } |
11088 | ||
11089 | void | |
11090 | tc_x86_frame_initial_instructions (void) | |
11091 | { | |
a60de03c JB |
11092 | static unsigned int sp_regno[2]; |
11093 | ||
11094 | if (!sp_regno[flag_code >> 1]) | |
11095 | { | |
11096 | char *saved_input = input_line_pointer; | |
11097 | char sp[][4] = {"esp", "rsp"}; | |
11098 | expressionS exp; | |
a4447b93 | 11099 | |
a60de03c JB |
11100 | input_line_pointer = sp[flag_code >> 1]; |
11101 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 11102 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
11103 | sp_regno[flag_code >> 1] = exp.X_add_number; |
11104 | input_line_pointer = saved_input; | |
11105 | } | |
a4447b93 | 11106 | |
61ff971f L |
11107 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
11108 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 11109 | } |
d2b2c203 | 11110 | |
d7921315 L |
11111 | int |
11112 | x86_dwarf2_addr_size (void) | |
11113 | { | |
11114 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
11115 | if (x86_elf_abi == X86_64_X32_ABI) | |
11116 | return 4; | |
11117 | #endif | |
11118 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
11119 | } | |
11120 | ||
d2b2c203 DJ |
11121 | int |
11122 | i386_elf_section_type (const char *str, size_t len) | |
11123 | { | |
11124 | if (flag_code == CODE_64BIT | |
11125 | && len == sizeof ("unwind") - 1 | |
11126 | && strncmp (str, "unwind", 6) == 0) | |
11127 | return SHT_X86_64_UNWIND; | |
11128 | ||
11129 | return -1; | |
11130 | } | |
bb41ade5 | 11131 | |
ad5fec3b EB |
11132 | #ifdef TE_SOLARIS |
11133 | void | |
11134 | i386_solaris_fix_up_eh_frame (segT sec) | |
11135 | { | |
11136 | if (flag_code == CODE_64BIT) | |
11137 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
11138 | } | |
11139 | #endif | |
11140 | ||
bb41ade5 AM |
11141 | #ifdef TE_PE |
11142 | void | |
11143 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
11144 | { | |
91d6fa6a | 11145 | expressionS exp; |
bb41ade5 | 11146 | |
91d6fa6a NC |
11147 | exp.X_op = O_secrel; |
11148 | exp.X_add_symbol = symbol; | |
11149 | exp.X_add_number = 0; | |
11150 | emit_expr (&exp, size); | |
bb41ade5 AM |
11151 | } |
11152 | #endif | |
3b22753a L |
11153 | |
11154 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11155 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
11156 | ||
01e1a5bc | 11157 | bfd_vma |
6d4af3c2 | 11158 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
11159 | { |
11160 | if (flag_code == CODE_64BIT) | |
11161 | { | |
11162 | if (letter == 'l') | |
11163 | return SHF_X86_64_LARGE; | |
11164 | ||
8f3bae45 | 11165 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 11166 | } |
3b22753a | 11167 | else |
8f3bae45 | 11168 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
11169 | return -1; |
11170 | } | |
11171 | ||
01e1a5bc | 11172 | bfd_vma |
3b22753a L |
11173 | x86_64_section_word (char *str, size_t len) |
11174 | { | |
8620418b | 11175 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
11176 | return SHF_X86_64_LARGE; |
11177 | ||
11178 | return -1; | |
11179 | } | |
11180 | ||
11181 | static void | |
11182 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
11183 | { | |
11184 | if (flag_code != CODE_64BIT) | |
11185 | { | |
11186 | s_comm_internal (0, elf_common_parse); | |
11187 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
11188 | } | |
11189 | else | |
11190 | { | |
11191 | static segT lbss_section; | |
11192 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
11193 | asection *saved_bss_section = bss_section; | |
11194 | ||
11195 | if (lbss_section == NULL) | |
11196 | { | |
11197 | flagword applicable; | |
11198 | segT seg = now_seg; | |
11199 | subsegT subseg = now_subseg; | |
11200 | ||
11201 | /* The .lbss section is for local .largecomm symbols. */ | |
11202 | lbss_section = subseg_new (".lbss", 0); | |
11203 | applicable = bfd_applicable_section_flags (stdoutput); | |
11204 | bfd_set_section_flags (stdoutput, lbss_section, | |
11205 | applicable & SEC_ALLOC); | |
11206 | seg_info (lbss_section)->bss = 1; | |
11207 | ||
11208 | subseg_set (seg, subseg); | |
11209 | } | |
11210 | ||
11211 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
11212 | bss_section = lbss_section; | |
11213 | ||
11214 | s_comm_internal (0, elf_common_parse); | |
11215 | ||
11216 | elf_com_section_ptr = saved_com_section_ptr; | |
11217 | bss_section = saved_bss_section; | |
11218 | } | |
11219 | } | |
11220 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |