Commit | Line | Data |
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fecd2382 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
dddc8a82 ILT |
2 | Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 1998 |
3 | Free Software Foundation. | |
355afbcd | 4 | |
a39116f1 | 5 | This file is part of GAS, the GNU Assembler. |
355afbcd | 6 | |
a39116f1 RP |
7 | GAS is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
355afbcd | 11 | |
a39116f1 RP |
12 | GAS is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
355afbcd | 16 | |
a39116f1 | 17 | You should have received a copy of the GNU General Public License |
e592f0e6 ILT |
18 | along with GAS; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
fecd2382 | 21 | |
fecd2382 RP |
22 | /* |
23 | Intel 80386 machine specific gas. | |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
25 | Bugs & suggestions are completely welcome. This is free software. | |
26 | Please help us make it better. | |
a39116f1 | 27 | */ |
fecd2382 | 28 | |
4b77b129 ILT |
29 | #include <ctype.h> |
30 | ||
fecd2382 | 31 | #include "as.h" |
0877841d | 32 | #include "subsegs.h" |
a39116f1 | 33 | #include "opcode/i386.h" |
fecd2382 | 34 | |
f0b37b4a KR |
35 | #ifndef TC_RELOC |
36 | #define TC_RELOC(X,Y) (Y) | |
37 | #endif | |
38 | ||
73a8be66 ILT |
39 | #ifndef REGISTER_WARNINGS |
40 | #define REGISTER_WARNINGS 1 | |
41 | #endif | |
42 | ||
ec1e6bb8 ILT |
43 | #ifndef SCALE1_WHEN_NO_INDEX |
44 | /* Specifying a scale factor besides 1 when there is no index is | |
45 | futile. eg. `mov (%ebx,2),%al' does exactly the same as | |
46 | `mov (%ebx),%al'. To slavishly follow what the programmer | |
47 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ | |
48 | #define SCALE1_WHEN_NO_INDEX 1 | |
49 | #endif | |
50 | ||
61c49d66 | 51 | static unsigned int mode_from_disp_size PARAMS ((unsigned int)); |
f59fb6ca ILT |
52 | static int fits_in_signed_byte PARAMS ((long)); |
53 | static int fits_in_unsigned_byte PARAMS ((long)); | |
54 | static int fits_in_unsigned_word PARAMS ((long)); | |
55 | static int fits_in_signed_word PARAMS ((long)); | |
56 | static int smallest_imm_type PARAMS ((long)); | |
73a8be66 | 57 | static int add_prefix PARAMS ((unsigned int)); |
f59fb6ca ILT |
58 | static void set_16bit_code_flag PARAMS ((int)); |
59 | #ifdef BFD_ASSEMBLER | |
60 | static bfd_reloc_code_real_type reloc | |
61 | PARAMS ((int, int, bfd_reloc_code_real_type)); | |
62 | #endif | |
63 | ||
fecd2382 RP |
64 | /* 'md_assemble ()' gathers together information and puts it into a |
65 | i386_insn. */ | |
66 | ||
3c8df4ba | 67 | struct _i386_insn |
355afbcd KR |
68 | { |
69 | /* TM holds the template for the insn were currently assembling. */ | |
70 | template tm; | |
73a8be66 | 71 | |
355afbcd KR |
72 | /* SUFFIX holds the opcode suffix (e.g. 'l' for 'movl') if given. */ |
73 | char suffix; | |
73a8be66 | 74 | |
355afbcd KR |
75 | /* Operands are coded with OPERANDS, TYPES, DISPS, IMMS, and REGS. */ |
76 | ||
77 | /* OPERANDS gives the number of given operands. */ | |
78 | unsigned int operands; | |
79 | ||
49864cfa KR |
80 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number |
81 | of given register, displacement, memory operands and immediate | |
82 | operands. */ | |
355afbcd KR |
83 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
84 | ||
85 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
49864cfa KR |
86 | search through DISPS [i] & IMMS [i] & REGS [i] for the required |
87 | operand. */ | |
355afbcd KR |
88 | unsigned int types[MAX_OPERANDS]; |
89 | ||
90 | /* Displacements (if given) for each operand. */ | |
91 | expressionS *disps[MAX_OPERANDS]; | |
92 | ||
f0b37b4a KR |
93 | /* Relocation type for operand */ |
94 | #ifdef BFD_ASSEMBLER | |
95 | enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS]; | |
96 | #else | |
97 | int disp_reloc[MAX_OPERANDS]; | |
98 | #endif | |
99 | ||
355afbcd KR |
100 | /* Immediate operands (if given) for each operand. */ |
101 | expressionS *imms[MAX_OPERANDS]; | |
102 | ||
103 | /* Register operands (if given) for each operand. */ | |
73a8be66 | 104 | const reg_entry *regs[MAX_OPERANDS]; |
355afbcd KR |
105 | |
106 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode | |
49864cfa | 107 | the base index byte below. */ |
73a8be66 ILT |
108 | const reg_entry *base_reg; |
109 | const reg_entry *index_reg; | |
355afbcd KR |
110 | unsigned int log2_scale_factor; |
111 | ||
4498e3d6 ILT |
112 | /* SEG gives the seg_entries of this insn. They are zero unless |
113 | explicit segment overrides are given. */ | |
114 | const seg_entry *seg[2]; /* segments for memory operands (if given) */ | |
355afbcd KR |
115 | |
116 | /* PREFIX holds all the given prefix opcodes (usually null). | |
ec1e6bb8 | 117 | PREFIXES is the number of prefix opcodes. */ |
355afbcd | 118 | unsigned int prefixes; |
ec1e6bb8 | 119 | unsigned char prefix[MAX_PREFIXES]; |
355afbcd | 120 | |
0351b70c | 121 | /* RM and SIB are the modrm byte and the sib byte where the |
73a8be66 | 122 | addressing modes of this insn are encoded. */ |
355afbcd KR |
123 | |
124 | modrm_byte rm; | |
0351b70c | 125 | sib_byte sib; |
3c8df4ba | 126 | }; |
355afbcd | 127 | |
3c8df4ba | 128 | typedef struct _i386_insn i386_insn; |
fecd2382 | 129 | |
4edc93e9 ILT |
130 | /* List of chars besides those in app.c:symbol_chars that can start an |
131 | operand. Used to prevent the scrubber eating vital white-space. */ | |
132 | #ifdef LEX_AT | |
133 | const char extra_symbol_chars[] = "*%-(@"; | |
134 | #else | |
135 | const char extra_symbol_chars[] = "*%-("; | |
136 | #endif | |
137 | ||
a39116f1 RP |
138 | /* This array holds the chars that always start a comment. If the |
139 | pre-processor is disabled, these aren't very useful */ | |
4edc93e9 ILT |
140 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX)) |
141 | /* Putting '/' here makes it impossible to use the divide operator. | |
142 | However, we need it for compatibility with SVR4 systems. */ | |
49864cfa | 143 | const char comment_chars[] = "#/"; |
0351b70c | 144 | #define PREFIX_SEPARATOR '\\' |
49864cfa | 145 | #else |
a39116f1 | 146 | const char comment_chars[] = "#"; |
0351b70c | 147 | #define PREFIX_SEPARATOR '/' |
49864cfa | 148 | #endif |
fecd2382 | 149 | |
a39116f1 RP |
150 | /* This array holds the chars that only start a comment at the beginning of |
151 | a line. If the line seems to have the form '# 123 filename' | |
152 | .line and .file directives will appear in the pre-processed output */ | |
153 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
154 | first line of the input file. This is because the compiler outputs | |
155 | #NO_APP at the beginning of its output. */ | |
156 | /* Also note that comments started like this one will always work if | |
f3d817d8 | 157 | '/' isn't otherwise defined. */ |
4edc93e9 | 158 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX)) |
ad660eb1 | 159 | const char line_comment_chars[] = ""; |
7b23213f KR |
160 | #else |
161 | const char line_comment_chars[] = "/"; | |
162 | #endif | |
0351b70c | 163 | |
355afbcd | 164 | const char line_separator_chars[] = ""; |
fecd2382 | 165 | |
a39116f1 RP |
166 | /* Chars that can be used to separate mant from exp in floating point nums */ |
167 | const char EXP_CHARS[] = "eE"; | |
fecd2382 | 168 | |
a39116f1 RP |
169 | /* Chars that mean this number is a floating point constant */ |
170 | /* As in 0f12.456 */ | |
171 | /* or 0d1.2345e12 */ | |
172 | const char FLT_CHARS[] = "fFdDxX"; | |
fecd2382 RP |
173 | |
174 | /* tables for lexical analysis */ | |
175 | static char opcode_chars[256]; | |
176 | static char register_chars[256]; | |
177 | static char operand_chars[256]; | |
fecd2382 RP |
178 | static char identifier_chars[256]; |
179 | static char digit_chars[256]; | |
180 | ||
181 | /* lexical macros */ | |
182 | #define is_opcode_char(x) (opcode_chars[(unsigned char) x]) | |
183 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
184 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
4edc93e9 | 185 | #define is_space_char(x) ((x) == ' ') |
fecd2382 RP |
186 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) |
187 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
188 | ||
189 | /* put here all non-digit non-letter charcters that may occur in an operand */ | |
f0b37b4a | 190 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
fecd2382 | 191 | |
fecd2382 RP |
192 | /* md_assemble() always leaves the strings it's passed unaltered. To |
193 | effect this we maintain a stack of saved characters that we've smashed | |
194 | with '\0's (indicating end of strings for various sub-fields of the | |
195 | assembler instruction). */ | |
196 | static char save_stack[32]; | |
197 | static char *save_stack_p; /* stack pointer */ | |
aa56747a ILT |
198 | #define END_STRING_AND_SAVE(s) \ |
199 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
200 | #define RESTORE_END_STRING(s) \ | |
201 | do { *(s) = *--save_stack_p; } while (0) | |
355afbcd KR |
202 | |
203 | /* The instruction we're assembling. */ | |
204 | static i386_insn i; | |
fecd2382 | 205 | |
4498e3d6 | 206 | /* Possible templates for current insn. */ |
0351b70c | 207 | static const templates *current_templates; |
4498e3d6 | 208 | |
fecd2382 RP |
209 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ |
210 | static expressionS disp_expressions[2], im_expressions[2]; | |
211 | ||
fecd2382 RP |
212 | static int this_operand; /* current operand we are working on */ |
213 | ||
ade614d5 KR |
214 | static int flag_do_long_jump; /* FIXME what does this do? */ |
215 | ||
c54c7aac KR |
216 | static int flag_16bit_code; /* 1 if we're writing 16-bit code, 0 if 32-bit */ |
217 | ||
3c8df4ba KR |
218 | /* Interface to relax_segment. |
219 | There are 2 relax states for 386 jump insns: one for conditional & | |
220 | one for unconditional jumps. This is because the these two types | |
221 | of jumps add different sizes to frags when we're figuring out what | |
222 | sort of jump to choose to reach a given label. */ | |
fecd2382 RP |
223 | |
224 | /* types */ | |
225 | #define COND_JUMP 1 /* conditional jump */ | |
226 | #define UNCOND_JUMP 2 /* unconditional jump */ | |
227 | /* sizes */ | |
0351b70c ILT |
228 | #define CODE16 1 |
229 | #define SMALL 0 | |
230 | #define SMALL16 (SMALL|CODE16) | |
231 | #define BIG 2 | |
232 | #define BIG16 (BIG|CODE16) | |
fecd2382 | 233 | |
3c8df4ba KR |
234 | #ifndef INLINE |
235 | #ifdef __GNUC__ | |
236 | #define INLINE __inline__ | |
237 | #else | |
238 | #define INLINE | |
239 | #endif | |
240 | #endif | |
241 | ||
ad660eb1 ILT |
242 | #define ENCODE_RELAX_STATE(type,size) \ |
243 | ((relax_substateT)((type<<2) | (size))) | |
fecd2382 | 244 | #define SIZE_FROM_RELAX_STATE(s) \ |
0351b70c ILT |
245 | ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) ) |
246 | ||
247 | /* This table is used by relax_frag to promote short jumps to long | |
248 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
249 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
250 | don't allow a short jump in a 32 bit code segment to be promoted to | |
251 | a 16 bit offset jump because it's slower (requires data size | |
252 | prefix), and doesn't work, unless the destination is in the bottom | |
253 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
fecd2382 | 254 | |
355afbcd KR |
255 | const relax_typeS md_relax_table[] = |
256 | { | |
49864cfa KR |
257 | /* The fields are: |
258 | 1) most positive reach of this state, | |
259 | 2) most negative reach of this state, | |
260 | 3) how many bytes this mode will add to the size of the current frag | |
261 | 4) which index into the table to try if we can't fit into this one. | |
262 | */ | |
355afbcd KR |
263 | {1, 1, 0, 0}, |
264 | {1, 1, 0, 0}, | |
265 | {1, 1, 0, 0}, | |
266 | {1, 1, 0, 0}, | |
267 | ||
0351b70c ILT |
268 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, |
269 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
3c8df4ba | 270 | /* dword conditionals adds 4 bytes to frag: |
0351b70c | 271 | 1 extra opcode byte, 3 extra displacement bytes. */ |
355afbcd | 272 | {0, 0, 4, 0}, |
0351b70c ILT |
273 | /* word conditionals add 2 bytes to frag: |
274 | 1 extra opcode byte, 1 extra displacement byte. */ | |
275 | {0, 0, 2, 0}, | |
355afbcd | 276 | |
0351b70c ILT |
277 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
278 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
3c8df4ba | 279 | /* dword jmp adds 3 bytes to frag: |
0351b70c | 280 | 0 extra opcode bytes, 3 extra displacement bytes. */ |
355afbcd | 281 | {0, 0, 3, 0}, |
0351b70c ILT |
282 | /* word jmp adds 1 byte to frag: |
283 | 0 extra opcode bytes, 1 extra displacement byte. */ | |
284 | {0, 0, 1, 0} | |
355afbcd | 285 | |
fecd2382 RP |
286 | }; |
287 | ||
3ea36b53 ILT |
288 | |
289 | void | |
290 | i386_align_code (fragP, count) | |
291 | fragS *fragP; | |
292 | int count; | |
293 | { | |
294 | /* Various efficient no-op patterns for aligning code labels. */ | |
fb50cd4e ILT |
295 | /* Note: Don't try to assemble the instructions in the comments. */ |
296 | /* 0L and 0w are not legal */ | |
297 | static const char f32_1[] = | |
298 | {0x90}; /* nop */ | |
299 | static const char f32_2[] = | |
300 | {0x89,0xf6}; /* movl %esi,%esi */ | |
301 | static const char f32_3[] = | |
302 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
303 | static const char f32_4[] = | |
304 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
305 | static const char f32_5[] = | |
306 | {0x90, /* nop */ | |
307 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
308 | static const char f32_6[] = | |
309 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
310 | static const char f32_7[] = | |
311 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
312 | static const char f32_8[] = | |
313 | {0x90, /* nop */ | |
314 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
315 | static const char f32_9[] = | |
316 | {0x89,0xf6, /* movl %esi,%esi */ | |
317 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
318 | static const char f32_10[] = | |
319 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
320 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
321 | static const char f32_11[] = | |
322 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
323 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
324 | static const char f32_12[] = | |
325 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
326 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
327 | static const char f32_13[] = | |
328 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
329 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
330 | static const char f32_14[] = | |
331 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
332 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
333 | static const char f32_15[] = | |
334 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
335 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
336 | static const char f16_4[] = | |
388fa5c6 | 337 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
fb50cd4e ILT |
338 | static const char f16_5[] = |
339 | {0x90, /* nop */ | |
388fa5c6 | 340 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
fb50cd4e ILT |
341 | static const char f16_6[] = |
342 | {0x89,0xf6, /* mov %si,%si */ | |
343 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
344 | static const char f16_7[] = | |
388fa5c6 | 345 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ |
fb50cd4e ILT |
346 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
347 | static const char f16_8[] = | |
388fa5c6 | 348 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ |
fb50cd4e | 349 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
3ea36b53 ILT |
350 | static const char *const f32_patt[] = { |
351 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
352 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
353 | }; | |
354 | static const char *const f16_patt[] = { | |
355 | f32_1, f32_2, f32_3, f16_4, f16_5, f16_6, f16_7, f16_8, | |
356 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 | |
357 | }; | |
358 | ||
359 | if (count > 0 && count <= 15) | |
360 | { | |
361 | if (flag_16bit_code) | |
362 | { | |
363 | memcpy(fragP->fr_literal + fragP->fr_fix, | |
364 | f16_patt[count - 1], count); | |
365 | if (count > 8) /* adjust jump offset */ | |
366 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
367 | } | |
368 | else | |
369 | memcpy(fragP->fr_literal + fragP->fr_fix, | |
370 | f32_patt[count - 1], count); | |
371 | fragP->fr_var = count; | |
372 | } | |
373 | } | |
374 | ||
49864cfa KR |
375 | static char *output_invalid PARAMS ((int c)); |
376 | static int i386_operand PARAMS ((char *operand_string)); | |
4edc93e9 ILT |
377 | static const reg_entry *parse_register PARAMS ((char *reg_string, |
378 | char **end_op)); | |
49864cfa | 379 | #ifndef I386COFF |
ad660eb1 | 380 | static void s_bss PARAMS ((int)); |
49864cfa | 381 | #endif |
fecd2382 | 382 | |
4498e3d6 | 383 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
f0b37b4a | 384 | |
61c49d66 | 385 | static INLINE unsigned int |
49864cfa | 386 | mode_from_disp_size (t) |
61c49d66 | 387 | unsigned int t; |
49864cfa | 388 | { |
73a8be66 | 389 | return (t & Disp8) ? 1 : (t & (Disp16|Disp32)) ? 2 : 0; |
3c8df4ba | 390 | } |
49864cfa | 391 | |
3c8df4ba | 392 | static INLINE int |
49864cfa KR |
393 | fits_in_signed_byte (num) |
394 | long num; | |
395 | { | |
3c8df4ba | 396 | return (num >= -128) && (num <= 127); |
49864cfa KR |
397 | } /* fits_in_signed_byte() */ |
398 | ||
3c8df4ba | 399 | static INLINE int |
49864cfa KR |
400 | fits_in_unsigned_byte (num) |
401 | long num; | |
402 | { | |
3c8df4ba | 403 | return (num & 0xff) == num; |
49864cfa KR |
404 | } /* fits_in_unsigned_byte() */ |
405 | ||
3c8df4ba | 406 | static INLINE int |
49864cfa KR |
407 | fits_in_unsigned_word (num) |
408 | long num; | |
409 | { | |
3c8df4ba | 410 | return (num & 0xffff) == num; |
49864cfa KR |
411 | } /* fits_in_unsigned_word() */ |
412 | ||
3c8df4ba | 413 | static INLINE int |
49864cfa KR |
414 | fits_in_signed_word (num) |
415 | long num; | |
416 | { | |
3c8df4ba | 417 | return (-32768 <= num) && (num <= 32767); |
49864cfa KR |
418 | } /* fits_in_signed_word() */ |
419 | ||
420 | static int | |
421 | smallest_imm_type (num) | |
422 | long num; | |
423 | { | |
f3d817d8 DM |
424 | #if 0 |
425 | /* This code is disabled because all the Imm1 forms in the opcode table | |
426 | are slower on the i486, and they're the versions with the implicitly | |
427 | specified single-position displacement, which has another syntax if | |
428 | you really want to use that form. If you really prefer to have the | |
429 | one-byte-shorter Imm1 form despite these problems, re-enable this | |
430 | code. */ | |
431 | if (num == 1) | |
432 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32; | |
433 | #endif | |
434 | return (fits_in_signed_byte (num) | |
3c8df4ba KR |
435 | ? (Imm8S | Imm8 | Imm16 | Imm32) |
436 | : fits_in_unsigned_byte (num) | |
437 | ? (Imm8 | Imm16 | Imm32) | |
438 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
439 | ? (Imm16 | Imm32) | |
440 | : (Imm32)); | |
49864cfa | 441 | } /* smallest_imm_type() */ |
fecd2382 | 442 | |
aa56747a ILT |
443 | /* Returns 0 if attempting to add a prefix where one from the same |
444 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
445 | added. */ | |
4498e3d6 | 446 | static int |
aa56747a | 447 | add_prefix (prefix) |
73a8be66 | 448 | unsigned int prefix; |
4498e3d6 | 449 | { |
aa56747a | 450 | int ret = 1; |
4498e3d6 ILT |
451 | int q; |
452 | ||
aa56747a | 453 | switch (prefix) |
4498e3d6 | 454 | { |
73a8be66 ILT |
455 | default: |
456 | abort (); | |
457 | ||
aa56747a ILT |
458 | case CS_PREFIX_OPCODE: |
459 | case DS_PREFIX_OPCODE: | |
460 | case ES_PREFIX_OPCODE: | |
461 | case FS_PREFIX_OPCODE: | |
462 | case GS_PREFIX_OPCODE: | |
463 | case SS_PREFIX_OPCODE: | |
464 | q = SEG_PREFIX; | |
465 | break; | |
4498e3d6 | 466 | |
0351b70c ILT |
467 | case REPNE_PREFIX_OPCODE: |
468 | case REPE_PREFIX_OPCODE: | |
aa56747a ILT |
469 | ret = 2; |
470 | /* fall thru */ | |
471 | case LOCK_PREFIX_OPCODE: | |
472 | q = LOCKREP_PREFIX; | |
473 | break; | |
4498e3d6 | 474 | |
aa56747a ILT |
475 | case FWAIT_OPCODE: |
476 | q = WAIT_PREFIX; | |
477 | break; | |
4498e3d6 | 478 | |
aa56747a ILT |
479 | case ADDR_PREFIX_OPCODE: |
480 | q = ADDR_PREFIX; | |
481 | break; | |
482 | ||
73a8be66 | 483 | case DATA_PREFIX_OPCODE: |
aa56747a | 484 | q = DATA_PREFIX; |
73a8be66 | 485 | break; |
4498e3d6 ILT |
486 | } |
487 | ||
aa56747a | 488 | if (i.prefix[q]) |
4498e3d6 | 489 | { |
aa56747a | 490 | as_bad (_("same type of prefix used twice")); |
4498e3d6 ILT |
491 | return 0; |
492 | } | |
493 | ||
aa56747a ILT |
494 | i.prefixes += 1; |
495 | i.prefix[q] = prefix; | |
496 | return ret; | |
4498e3d6 ILT |
497 | } |
498 | ||
f59fb6ca ILT |
499 | static void |
500 | set_16bit_code_flag (new_16bit_code_flag) | |
c54c7aac KR |
501 | int new_16bit_code_flag; |
502 | { | |
503 | flag_16bit_code = new_16bit_code_flag; | |
504 | } | |
505 | ||
355afbcd KR |
506 | const pseudo_typeS md_pseudo_table[] = |
507 | { | |
49864cfa | 508 | #ifndef I386COFF |
355afbcd | 509 | {"bss", s_bss, 0}, |
49864cfa | 510 | #endif |
02bdbd8b | 511 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
355afbcd | 512 | {"align", s_align_bytes, 0}, |
49864cfa KR |
513 | #else |
514 | {"align", s_align_ptwo, 0}, | |
515 | #endif | |
355afbcd KR |
516 | {"ffloat", float_cons, 'f'}, |
517 | {"dfloat", float_cons, 'd'}, | |
518 | {"tfloat", float_cons, 'x'}, | |
519 | {"value", cons, 2}, | |
49864cfa KR |
520 | {"noopt", s_ignore, 0}, |
521 | {"optim", s_ignore, 0}, | |
c54c7aac KR |
522 | {"code16", set_16bit_code_flag, 1}, |
523 | {"code32", set_16bit_code_flag, 0}, | |
355afbcd | 524 | {0, 0, 0} |
fecd2382 RP |
525 | }; |
526 | ||
527 | /* for interface with expression () */ | |
355afbcd | 528 | extern char *input_line_pointer; |
fecd2382 | 529 | |
fecd2382 | 530 | /* hash table for opcode lookup */ |
f3d817d8 | 531 | static struct hash_control *op_hash; |
fecd2382 | 532 | /* hash table for register lookup */ |
f3d817d8 | 533 | static struct hash_control *reg_hash; |
fecd2382 | 534 | \f |
355afbcd KR |
535 | |
536 | void | |
537 | md_begin () | |
fecd2382 | 538 | { |
ad660eb1 | 539 | const char *hash_err; |
355afbcd | 540 | |
355afbcd | 541 | /* initialize op_hash hash table */ |
f3d817d8 | 542 | op_hash = hash_new (); |
355afbcd KR |
543 | |
544 | { | |
545 | register const template *optab; | |
546 | register templates *core_optab; | |
355afbcd KR |
547 | |
548 | optab = i386_optab; /* setup for loop */ | |
355afbcd | 549 | core_optab = (templates *) xmalloc (sizeof (templates)); |
0351b70c | 550 | core_optab->start = optab; |
355afbcd | 551 | |
0351b70c | 552 | while (1) |
355afbcd | 553 | { |
0351b70c ILT |
554 | ++optab; |
555 | if (optab->name == NULL | |
556 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
355afbcd KR |
557 | { |
558 | /* different name --> ship out current template list; | |
49864cfa | 559 | add to hash table; & begin anew */ |
0351b70c ILT |
560 | core_optab->end = optab; |
561 | hash_err = hash_insert (op_hash, | |
562 | (optab - 1)->name, | |
563 | (PTR) core_optab); | |
ad660eb1 | 564 | if (hash_err) |
355afbcd KR |
565 | { |
566 | hash_error: | |
0351b70c ILT |
567 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
568 | (optab - 1)->name, | |
3c8df4ba | 569 | hash_err); |
355afbcd | 570 | } |
0351b70c ILT |
571 | if (optab->name == NULL) |
572 | break; | |
355afbcd | 573 | core_optab = (templates *) xmalloc (sizeof (templates)); |
0351b70c | 574 | core_optab->start = optab; |
355afbcd KR |
575 | } |
576 | } | |
577 | } | |
578 | ||
579 | /* initialize reg_hash hash table */ | |
580 | reg_hash = hash_new (); | |
581 | { | |
582 | register const reg_entry *regtab; | |
583 | ||
0351b70c ILT |
584 | for (regtab = i386_regtab; |
585 | regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); | |
586 | regtab++) | |
355afbcd | 587 | { |
ad660eb1 ILT |
588 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); |
589 | if (hash_err) | |
355afbcd KR |
590 | goto hash_error; |
591 | } | |
592 | } | |
593 | ||
4edc93e9 | 594 | /* fill in lexical tables: opcode_chars, operand_chars. */ |
355afbcd | 595 | { |
ad660eb1 ILT |
596 | register int c; |
597 | register char *p; | |
355afbcd KR |
598 | |
599 | for (c = 0; c < 256; c++) | |
600 | { | |
0351b70c | 601 | if (isdigit (c)) |
355afbcd | 602 | { |
0351b70c | 603 | digit_chars[c] = c; |
355afbcd KR |
604 | opcode_chars[c] = c; |
605 | register_chars[c] = c; | |
0351b70c | 606 | operand_chars[c] = c; |
355afbcd | 607 | } |
0351b70c | 608 | else if (islower (c)) |
355afbcd KR |
609 | { |
610 | opcode_chars[c] = c; | |
0351b70c ILT |
611 | register_chars[c] = c; |
612 | operand_chars[c] = c; | |
355afbcd | 613 | } |
0351b70c | 614 | else if (isupper (c)) |
355afbcd | 615 | { |
0351b70c ILT |
616 | opcode_chars[c] = tolower (c); |
617 | register_chars[c] = opcode_chars[c]; | |
618 | operand_chars[c] = c; | |
355afbcd KR |
619 | } |
620 | ||
0351b70c | 621 | if (isalpha (c) || isdigit (c)) |
355afbcd | 622 | identifier_chars[c] = c; |
0351b70c | 623 | } |
355afbcd | 624 | |
30355216 | 625 | #ifdef LEX_AT |
0351b70c | 626 | identifier_chars['@'] = '@'; |
30355216 | 627 | #endif |
0351b70c ILT |
628 | register_chars[')'] = ')'; |
629 | register_chars['('] = '('; | |
630 | digit_chars['-'] = '-'; | |
631 | identifier_chars['_'] = '_'; | |
632 | identifier_chars['.'] = '.'; | |
ad660eb1 ILT |
633 | |
634 | for (p = operand_special_chars; *p != '\0'; p++) | |
635 | operand_chars[(unsigned char) *p] = *p; | |
355afbcd | 636 | } |
ad660eb1 | 637 | |
590c50d8 ILT |
638 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
639 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
640 | { | |
641 | record_alignment (text_section, 2); | |
642 | record_alignment (data_section, 2); | |
643 | record_alignment (bss_section, 2); | |
644 | } | |
ad660eb1 | 645 | #endif |
fecd2382 | 646 | } |
3ea36b53 ILT |
647 | |
648 | void | |
649 | i386_print_statistics (file) | |
650 | FILE *file; | |
651 | { | |
652 | hash_print_statistics (file, "i386 opcode", op_hash); | |
653 | hash_print_statistics (file, "i386 register", reg_hash); | |
3ea36b53 | 654 | } |
fecd2382 | 655 | \f |
355afbcd | 656 | |
fecd2382 RP |
657 | #ifdef DEBUG386 |
658 | ||
659 | /* debugging routines for md_assemble */ | |
ad660eb1 ILT |
660 | static void pi PARAMS ((char *, i386_insn *)); |
661 | static void pte PARAMS ((template *)); | |
662 | static void pt PARAMS ((unsigned int)); | |
663 | static void pe PARAMS ((expressionS *)); | |
664 | static void ps PARAMS ((symbolS *)); | |
fecd2382 | 665 | |
355afbcd KR |
666 | static void |
667 | pi (line, x) | |
668 | char *line; | |
669 | i386_insn *x; | |
fecd2382 | 670 | { |
355afbcd KR |
671 | register template *p; |
672 | int i; | |
673 | ||
674 | fprintf (stdout, "%s: template ", line); | |
675 | pte (&x->tm); | |
676 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x", | |
677 | x->rm.mode, x->rm.reg, x->rm.regmem); | |
678 | fprintf (stdout, " base %x index %x scale %x\n", | |
679 | x->bi.base, x->bi.index, x->bi.scale); | |
680 | for (i = 0; i < x->operands; i++) | |
681 | { | |
682 | fprintf (stdout, " #%d: ", i + 1); | |
683 | pt (x->types[i]); | |
684 | fprintf (stdout, "\n"); | |
a52f90a4 ILT |
685 | if (x->types[i] |
686 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX)) | |
355afbcd KR |
687 | fprintf (stdout, "%s\n", x->regs[i]->reg_name); |
688 | if (x->types[i] & Imm) | |
689 | pe (x->imms[i]); | |
73a8be66 | 690 | if (x->types[i] & Disp) |
355afbcd KR |
691 | pe (x->disps[i]); |
692 | } | |
fecd2382 RP |
693 | } |
694 | ||
355afbcd KR |
695 | static void |
696 | pte (t) | |
697 | template *t; | |
fecd2382 | 698 | { |
355afbcd KR |
699 | int i; |
700 | fprintf (stdout, " %d operands ", t->operands); | |
701 | fprintf (stdout, "opcode %x ", | |
702 | t->base_opcode); | |
703 | if (t->extension_opcode != None) | |
704 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
705 | if (t->opcode_modifier & D) | |
706 | fprintf (stdout, "D"); | |
707 | if (t->opcode_modifier & W) | |
708 | fprintf (stdout, "W"); | |
709 | fprintf (stdout, "\n"); | |
710 | for (i = 0; i < t->operands; i++) | |
711 | { | |
712 | fprintf (stdout, " #%d type ", i + 1); | |
713 | pt (t->operand_types[i]); | |
714 | fprintf (stdout, "\n"); | |
715 | } | |
fecd2382 RP |
716 | } |
717 | ||
355afbcd KR |
718 | static void |
719 | pe (e) | |
720 | expressionS *e; | |
fecd2382 | 721 | { |
5ac34ac3 | 722 | fprintf (stdout, " operation %d\n", e->X_op); |
355afbcd KR |
723 | fprintf (stdout, " add_number %d (%x)\n", |
724 | e->X_add_number, e->X_add_number); | |
725 | if (e->X_add_symbol) | |
726 | { | |
727 | fprintf (stdout, " add_symbol "); | |
728 | ps (e->X_add_symbol); | |
729 | fprintf (stdout, "\n"); | |
730 | } | |
5ac34ac3 | 731 | if (e->X_op_symbol) |
355afbcd | 732 | { |
5ac34ac3 ILT |
733 | fprintf (stdout, " op_symbol "); |
734 | ps (e->X_op_symbol); | |
355afbcd KR |
735 | fprintf (stdout, "\n"); |
736 | } | |
fecd2382 RP |
737 | } |
738 | ||
355afbcd KR |
739 | static void |
740 | ps (s) | |
741 | symbolS *s; | |
fecd2382 | 742 | { |
355afbcd KR |
743 | fprintf (stdout, "%s type %s%s", |
744 | S_GET_NAME (s), | |
745 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
746 | segment_name (S_GET_SEGMENT (s))); | |
fecd2382 RP |
747 | } |
748 | ||
355afbcd KR |
749 | struct type_name |
750 | { | |
751 | unsigned int mask; | |
752 | char *tname; | |
753 | } | |
754 | ||
755 | type_names[] = | |
756 | { | |
757 | { Reg8, "r8" }, | |
758 | { Reg16, "r16" }, | |
759 | { Reg32, "r32" }, | |
760 | { Imm8, "i8" }, | |
761 | { Imm8S, "i8s" }, | |
762 | { Imm16, "i16" }, | |
763 | { Imm32, "i32" }, | |
73a8be66 | 764 | { Imm1, "i1" }, |
355afbcd | 765 | { BaseIndex, "BaseIndex" }, |
355afbcd KR |
766 | { Disp8, "d8" }, |
767 | { Disp16, "d16" }, | |
768 | { Disp32, "d32" }, | |
355afbcd KR |
769 | { InOutPortReg, "InOutPortReg" }, |
770 | { ShiftCount, "ShiftCount" }, | |
355afbcd KR |
771 | { Control, "control reg" }, |
772 | { Test, "test reg" }, | |
4498e3d6 | 773 | { Debug, "debug reg" }, |
355afbcd KR |
774 | { FloatReg, "FReg" }, |
775 | { FloatAcc, "FAcc" }, | |
73a8be66 ILT |
776 | { SReg2, "SReg2" }, |
777 | { SReg3, "SReg3" }, | |
778 | { Acc, "Acc" }, | |
355afbcd | 779 | { JumpAbsolute, "Jump Absolute" }, |
454b0ccd | 780 | { RegMMX, "rMMX" }, |
4498e3d6 | 781 | { EsSeg, "es" }, |
355afbcd | 782 | { 0, "" } |
fecd2382 RP |
783 | }; |
784 | ||
355afbcd KR |
785 | static void |
786 | pt (t) | |
787 | unsigned int t; | |
fecd2382 | 788 | { |
355afbcd KR |
789 | register struct type_name *ty; |
790 | ||
791 | if (t == Unknown) | |
792 | { | |
48401fcf | 793 | fprintf (stdout, _("Unknown")); |
355afbcd KR |
794 | } |
795 | else | |
796 | { | |
797 | for (ty = type_names; ty->mask; ty++) | |
798 | if (t & ty->mask) | |
799 | fprintf (stdout, "%s, ", ty->tname); | |
800 | } | |
801 | fflush (stdout); | |
fecd2382 RP |
802 | } |
803 | ||
804 | #endif /* DEBUG386 */ | |
805 | \f | |
a1624e3f RH |
806 | int |
807 | tc_i386_force_relocation (fixp) | |
808 | struct fix *fixp; | |
809 | { | |
810 | #ifdef BFD_ASSEMBLER | |
811 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
812 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
813 | return 1; | |
814 | return 0; | |
815 | #else | |
816 | /* For COFF */ | |
817 | return fixp->fx_r_type==7; | |
818 | #endif | |
819 | } | |
820 | ||
49864cfa KR |
821 | #ifdef BFD_ASSEMBLER |
822 | static bfd_reloc_code_real_type | |
f0b37b4a | 823 | reloc (size, pcrel, other) |
49864cfa KR |
824 | int size; |
825 | int pcrel; | |
f0b37b4a | 826 | bfd_reloc_code_real_type other; |
49864cfa | 827 | { |
f0b37b4a KR |
828 | if (other != NO_RELOC) return other; |
829 | ||
49864cfa | 830 | if (pcrel) |
0351b70c ILT |
831 | { |
832 | switch (size) | |
833 | { | |
834 | case 1: return BFD_RELOC_8_PCREL; | |
835 | case 2: return BFD_RELOC_16_PCREL; | |
836 | case 4: return BFD_RELOC_32_PCREL; | |
837 | } | |
838 | as_bad (_("Can not do %d byte pc-relative relocation"), size); | |
839 | } | |
48401fcf | 840 | else |
0351b70c ILT |
841 | { |
842 | switch (size) | |
843 | { | |
844 | case 1: return BFD_RELOC_8; | |
845 | case 2: return BFD_RELOC_16; | |
846 | case 4: return BFD_RELOC_32; | |
847 | } | |
848 | as_bad (_("Can not do %d byte relocation"), size); | |
849 | } | |
48401fcf | 850 | |
ad660eb1 | 851 | return BFD_RELOC_NONE; |
49864cfa | 852 | } |
49864cfa | 853 | |
f0b37b4a KR |
854 | /* |
855 | * Here we decide which fixups can be adjusted to make them relative to | |
856 | * the beginning of the section instead of the symbol. Basically we need | |
857 | * to make sure that the dynamic relocations are done correctly, so in | |
858 | * some cases we force the original symbol to be used. | |
859 | */ | |
0877841d | 860 | int |
f0b37b4a KR |
861 | tc_i386_fix_adjustable(fixP) |
862 | fixS * fixP; | |
863 | { | |
76fb6d2f | 864 | #ifdef OBJ_ELF |
c54c7aac | 865 | /* Prevent all adjustments to global symbols. */ |
0877841d | 866 | if (S_IS_EXTERN (fixP->fx_addsy)) |
c54c7aac | 867 | return 0; |
0b476c53 ILT |
868 | if (S_IS_WEAK (fixP->fx_addsy)) |
869 | return 0; | |
a1624e3f | 870 | #endif |
c54c7aac | 871 | /* adjust_reloc_syms doesn't know about the GOT */ |
0877841d ILT |
872 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
873 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
a1624e3f RH |
874 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
875 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
876 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c54c7aac | 877 | return 0; |
c54c7aac | 878 | return 1; |
f0b37b4a | 879 | } |
454b0ccd ILT |
880 | #else |
881 | #define reloc(SIZE,PCREL,OTHER) 0 | |
0351b70c | 882 | #define BFD_RELOC_16 0 |
454b0ccd | 883 | #define BFD_RELOC_32 0 |
0351b70c | 884 | #define BFD_RELOC_16_PCREL 0 |
454b0ccd ILT |
885 | #define BFD_RELOC_32_PCREL 0 |
886 | #define BFD_RELOC_386_PLT32 0 | |
887 | #define BFD_RELOC_386_GOT32 0 | |
888 | #define BFD_RELOC_386_GOTOFF 0 | |
889 | #endif | |
f0b37b4a | 890 | |
49864cfa | 891 | /* This is the guts of the machine-dependent assembler. LINE points to a |
3c8df4ba | 892 | machine dependent instruction. This function is supposed to emit |
49864cfa | 893 | the frags/bytes it assembles to. */ |
f0b37b4a | 894 | |
355afbcd KR |
895 | void |
896 | md_assemble (line) | |
897 | char *line; | |
fecd2382 | 898 | { |
227b6b55 ILT |
899 | /* Points to template once we've found it. */ |
900 | const template *t; | |
355afbcd | 901 | |
ad660eb1 ILT |
902 | /* Count the size of the instruction generated. */ |
903 | int insn_size = 0; | |
904 | ||
f0b37b4a KR |
905 | int j; |
906 | ||
355afbcd KR |
907 | /* Initialize globals. */ |
908 | memset (&i, '\0', sizeof (i)); | |
f0b37b4a KR |
909 | for (j = 0; j < MAX_OPERANDS; j++) |
910 | i.disp_reloc[j] = NO_RELOC; | |
355afbcd KR |
911 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
912 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
913 | save_stack_p = save_stack; /* reset stack pointer */ | |
914 | ||
227b6b55 | 915 | /* First parse an opcode & call i386_operand for the operands. |
49864cfa KR |
916 | We assume that the scrubber has arranged it so that line[0] is the valid |
917 | start of a (possibly prefixed) opcode. */ | |
355afbcd | 918 | { |
0351b70c | 919 | char opcode[MAX_OPCODE_SIZE]; |
f3d817d8 | 920 | char *l = line; |
0351b70c ILT |
921 | char *token_start = l; |
922 | char *opp; | |
355afbcd | 923 | |
4498e3d6 ILT |
924 | /* Non-zero if we found a prefix only acceptable with string insns. */ |
925 | const char *expecting_string_instruction = NULL; | |
355afbcd | 926 | |
0351b70c | 927 | while (1) |
355afbcd | 928 | { |
0351b70c ILT |
929 | opp = opcode; |
930 | while ((*opp = opcode_chars[(unsigned char) *l]) != 0) | |
355afbcd | 931 | { |
0351b70c ILT |
932 | opp++; |
933 | if (opp >= opcode + sizeof (opcode)) | |
934 | { | |
935 | as_bad (_("no such 386 instruction: `%s'"), token_start); | |
936 | return; | |
937 | } | |
938 | l++; | |
355afbcd | 939 | } |
0351b70c ILT |
940 | if (!is_space_char (*l) |
941 | && *l != END_OF_INSN | |
942 | && *l != PREFIX_SEPARATOR) | |
355afbcd | 943 | { |
0351b70c ILT |
944 | as_bad (_("invalid character %s in opcode"), |
945 | output_invalid (*l)); | |
946 | return; | |
355afbcd | 947 | } |
0351b70c | 948 | if (token_start == l) |
f3d817d8 | 949 | { |
0351b70c ILT |
950 | if (*l == PREFIX_SEPARATOR) |
951 | as_bad (_("expecting prefix; got nothing")); | |
952 | else | |
953 | as_bad (_("expecting opcode; got nothing")); | |
954 | return; | |
955 | } | |
355afbcd | 956 | |
0351b70c ILT |
957 | /* Look up instruction (or prefix) via hash table. */ |
958 | current_templates = hash_find (op_hash, opcode); | |
959 | ||
960 | if (*l != END_OF_INSN | |
61c49d66 | 961 | && (! is_space_char (*l) || l[1] != END_OF_INSN) |
0351b70c | 962 | && current_templates |
284f02bb | 963 | && (current_templates->start->opcode_modifier & IsPrefix)) |
0351b70c | 964 | { |
284f02bb ILT |
965 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
966 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
967 | if ((current_templates->start->opcode_modifier & (Size16 | Size32)) | |
968 | && (((current_templates->start->opcode_modifier & Size32) != 0) | |
969 | ^ flag_16bit_code)) | |
970 | { | |
971 | as_bad (_("redundant %s prefix"), | |
972 | current_templates->start->name); | |
973 | return; | |
974 | } | |
0351b70c ILT |
975 | /* Add prefix, checking for repeated prefixes. */ |
976 | switch (add_prefix (current_templates->start->base_opcode)) | |
4498e3d6 | 977 | { |
73a8be66 ILT |
978 | case 0: |
979 | return; | |
aa56747a | 980 | case 2: |
0351b70c ILT |
981 | expecting_string_instruction = |
982 | current_templates->start->name; | |
aa56747a | 983 | break; |
355afbcd | 984 | } |
4498e3d6 | 985 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ |
355afbcd KR |
986 | token_start = ++l; |
987 | } | |
0351b70c ILT |
988 | else |
989 | break; | |
355afbcd KR |
990 | } |
991 | ||
355afbcd KR |
992 | if (!current_templates) |
993 | { | |
0351b70c ILT |
994 | /* See if we can get a match by trimming off a suffix. */ |
995 | switch (opp[-1]) | |
355afbcd KR |
996 | { |
997 | case DWORD_OPCODE_SUFFIX: | |
998 | case WORD_OPCODE_SUFFIX: | |
999 | case BYTE_OPCODE_SUFFIX: | |
73a8be66 ILT |
1000 | case SHORT_OPCODE_SUFFIX: |
1001 | #if LONG_OPCODE_SUFFIX != DWORD_OPCODE_SUFFIX | |
1002 | case LONG_OPCODE_SUFFIX: | |
1003 | #endif | |
0351b70c ILT |
1004 | i.suffix = opp[-1]; |
1005 | opp[-1] = '\0'; | |
1006 | current_templates = hash_find (op_hash, opcode); | |
355afbcd KR |
1007 | } |
1008 | if (!current_templates) | |
1009 | { | |
48401fcf | 1010 | as_bad (_("no such 386 instruction: `%s'"), token_start); |
355afbcd KR |
1011 | return; |
1012 | } | |
1013 | } | |
355afbcd KR |
1014 | |
1015 | /* check for rep/repne without a string instruction */ | |
73a8be66 ILT |
1016 | if (expecting_string_instruction |
1017 | && !(current_templates->start->opcode_modifier & IsString)) | |
355afbcd | 1018 | { |
48401fcf | 1019 | as_bad (_("expecting string instruction after `%s'"), |
4498e3d6 | 1020 | expecting_string_instruction); |
355afbcd KR |
1021 | return; |
1022 | } | |
1023 | ||
1024 | /* There may be operands to parse. */ | |
4498e3d6 | 1025 | if (*l != END_OF_INSN) |
355afbcd KR |
1026 | { |
1027 | /* parse operands */ | |
0351b70c ILT |
1028 | |
1029 | /* 1 if operand is pending after ','. */ | |
1030 | unsigned int expecting_operand = 0; | |
1031 | ||
1032 | /* Non-zero if operand parens not balanced. */ | |
1033 | unsigned int paren_not_balanced; | |
1034 | ||
355afbcd KR |
1035 | do |
1036 | { | |
1037 | /* skip optional white space before operand */ | |
4edc93e9 ILT |
1038 | if (is_space_char (*l)) |
1039 | ++l; | |
1040 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
355afbcd | 1041 | { |
4edc93e9 ILT |
1042 | as_bad (_("invalid character %s before operand %d"), |
1043 | output_invalid (*l), | |
1044 | i.operands + 1); | |
1045 | return; | |
355afbcd KR |
1046 | } |
1047 | token_start = l; /* after white space */ | |
0b476c53 ILT |
1048 | paren_not_balanced = 0; |
1049 | while (paren_not_balanced || *l != ',') | |
355afbcd KR |
1050 | { |
1051 | if (*l == END_OF_INSN) | |
1052 | { | |
0b476c53 | 1053 | if (paren_not_balanced) |
355afbcd | 1054 | { |
48401fcf | 1055 | as_bad (_("unbalanced parenthesis in operand %d."), |
aa56747a | 1056 | i.operands + 1); |
355afbcd KR |
1057 | return; |
1058 | } | |
1059 | else | |
1060 | break; /* we are done */ | |
1061 | } | |
ad660eb1 | 1062 | else if (!is_operand_char (*l) && !is_space_char (*l)) |
355afbcd | 1063 | { |
48401fcf | 1064 | as_bad (_("invalid character %s in operand %d"), |
aa56747a ILT |
1065 | output_invalid (*l), |
1066 | i.operands + 1); | |
355afbcd KR |
1067 | return; |
1068 | } | |
1069 | if (*l == '(') | |
0b476c53 | 1070 | ++paren_not_balanced; |
355afbcd | 1071 | if (*l == ')') |
0b476c53 | 1072 | --paren_not_balanced; |
355afbcd KR |
1073 | l++; |
1074 | } | |
1075 | if (l != token_start) | |
1076 | { /* yes, we've read in another operand */ | |
1077 | unsigned int operand_ok; | |
1078 | this_operand = i.operands++; | |
1079 | if (i.operands > MAX_OPERANDS) | |
1080 | { | |
48401fcf | 1081 | as_bad (_("spurious operands; (%d operands/instruction max)"), |
355afbcd KR |
1082 | MAX_OPERANDS); |
1083 | return; | |
1084 | } | |
1085 | /* now parse operand adding info to 'i' as we go along */ | |
1086 | END_STRING_AND_SAVE (l); | |
1087 | operand_ok = i386_operand (token_start); | |
1088 | RESTORE_END_STRING (l); /* restore old contents */ | |
1089 | if (!operand_ok) | |
1090 | return; | |
1091 | } | |
1092 | else | |
1093 | { | |
1094 | if (expecting_operand) | |
1095 | { | |
1096 | expecting_operand_after_comma: | |
48401fcf | 1097 | as_bad (_("expecting operand after ','; got nothing")); |
355afbcd KR |
1098 | return; |
1099 | } | |
1100 | if (*l == ',') | |
1101 | { | |
48401fcf | 1102 | as_bad (_("expecting operand before ','; got nothing")); |
355afbcd KR |
1103 | return; |
1104 | } | |
1105 | } | |
1106 | ||
1107 | /* now *l must be either ',' or END_OF_INSN */ | |
1108 | if (*l == ',') | |
1109 | { | |
1110 | if (*++l == END_OF_INSN) | |
1111 | { /* just skip it, if it's \n complain */ | |
1112 | goto expecting_operand_after_comma; | |
1113 | } | |
1114 | expecting_operand = 1; | |
1115 | } | |
1116 | } | |
1117 | while (*l != END_OF_INSN); /* until we get end of insn */ | |
1118 | } | |
1119 | } | |
1120 | ||
1121 | /* Now we've parsed the opcode into a set of templates, and have the | |
c5dd66a1 KR |
1122 | operands at hand. |
1123 | ||
1124 | Next, we find a template that matches the given insn, | |
1125 | making sure the overlap of the given operands types is consistent | |
1126 | with the template operand types. */ | |
355afbcd | 1127 | |
73a8be66 ILT |
1128 | #define MATCH(overlap, given, template) \ |
1129 | ((overlap) \ | |
0351b70c ILT |
1130 | && ((given) & BaseIndex) == ((overlap) & BaseIndex) \ |
1131 | && ((given) & JumpAbsolute) == ((template) & JumpAbsolute)) | |
73a8be66 ILT |
1132 | |
1133 | /* If given types r0 and r1 are registers they must be of the same type | |
1134 | unless the expected operand type register overlap is null. | |
1135 | Note that Acc in a template matches every size of reg. */ | |
1136 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ | |
1137 | ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \ | |
1138 | ((g0) & Reg) == ((g1) & Reg) || \ | |
1139 | ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) | |
1140 | ||
355afbcd KR |
1141 | { |
1142 | register unsigned int overlap0, overlap1; | |
1143 | expressionS *exp; | |
1144 | unsigned int overlap2; | |
1145 | unsigned int found_reverse_match; | |
73a8be66 ILT |
1146 | int suffix_check; |
1147 | ||
1148 | overlap0 = 0; | |
1149 | overlap1 = 0; | |
1150 | overlap2 = 0; | |
1151 | found_reverse_match = 0; | |
1152 | suffix_check = (i.suffix == BYTE_OPCODE_SUFFIX | |
1153 | ? No_bSuf | |
1154 | : (i.suffix == WORD_OPCODE_SUFFIX | |
1155 | ? No_wSuf | |
1156 | : (i.suffix == SHORT_OPCODE_SUFFIX | |
1157 | ? No_sSuf | |
1158 | : (i.suffix == LONG_OPCODE_SUFFIX ? No_lSuf : 0)))); | |
355afbcd | 1159 | |
355afbcd KR |
1160 | for (t = current_templates->start; |
1161 | t < current_templates->end; | |
1162 | t++) | |
1163 | { | |
73a8be66 ILT |
1164 | /* Must have right number of operands, and must not have |
1165 | disallowed suffix. */ | |
1166 | if (i.operands != t->operands || (t->opcode_modifier & suffix_check)) | |
355afbcd KR |
1167 | continue; |
1168 | else if (!t->operands) | |
1169 | break; /* 0 operands always matches */ | |
1170 | ||
1171 | overlap0 = i.types[0] & t->operand_types[0]; | |
1172 | switch (t->operands) | |
1173 | { | |
1174 | case 1: | |
73a8be66 | 1175 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])) |
355afbcd KR |
1176 | continue; |
1177 | break; | |
1178 | case 2: | |
1179 | case 3: | |
1180 | overlap1 = i.types[1] & t->operand_types[1]; | |
73a8be66 ILT |
1181 | if (!MATCH (overlap0, i.types[0], t->operand_types[0]) |
1182 | || !MATCH (overlap1, i.types[1], t->operand_types[1]) | |
1183 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1184 | t->operand_types[0], | |
1185 | overlap1, i.types[1], | |
1186 | t->operand_types[1])) | |
542e1629 | 1187 | { |
355afbcd KR |
1188 | |
1189 | /* check if other direction is valid ... */ | |
73a8be66 | 1190 | if ((t->opcode_modifier & (D|FloatD)) == 0) |
355afbcd KR |
1191 | continue; |
1192 | ||
1193 | /* try reversing direction of operands */ | |
1194 | overlap0 = i.types[0] & t->operand_types[1]; | |
1195 | overlap1 = i.types[1] & t->operand_types[0]; | |
73a8be66 ILT |
1196 | if (!MATCH (overlap0, i.types[0], t->operand_types[1]) |
1197 | || !MATCH (overlap1, i.types[1], t->operand_types[0]) | |
1198 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1199 | t->operand_types[1], | |
1200 | overlap1, i.types[1], | |
1201 | t->operand_types[0])) | |
355afbcd KR |
1202 | { |
1203 | /* does not match either direction */ | |
1204 | continue; | |
1205 | } | |
73a8be66 ILT |
1206 | /* found_reverse_match holds which of D or FloatDR |
1207 | we've found. */ | |
1208 | found_reverse_match = t->opcode_modifier & (D|FloatDR); | |
1209 | break; | |
1210 | } | |
1211 | /* found a forward 2 operand match here */ | |
355afbcd KR |
1212 | if (t->operands == 3) |
1213 | { | |
73a8be66 ILT |
1214 | /* Here we make use of the fact that there are no |
1215 | reverse match 3 operand instructions, and all 3 | |
1216 | operand instructions only need to be checked for | |
1217 | register consistency between operands 2 and 3. */ | |
355afbcd | 1218 | overlap2 = i.types[2] & t->operand_types[2]; |
73a8be66 ILT |
1219 | if (!MATCH (overlap2, i.types[2], t->operand_types[2]) |
1220 | || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], | |
1221 | t->operand_types[1], | |
1222 | overlap2, i.types[2], | |
1223 | t->operand_types[2])) | |
355afbcd KR |
1224 | continue; |
1225 | } | |
1226 | /* found either forward/reverse 2 or 3 operand match here: | |
c5dd66a1 | 1227 | slip through to break */ |
355afbcd KR |
1228 | } |
1229 | break; /* we've found a match; break out of loop */ | |
1230 | } /* for (t = ... */ | |
1231 | if (t == current_templates->end) | |
1232 | { /* we found no match */ | |
48401fcf | 1233 | as_bad (_("suffix or operands invalid for `%s'"), |
4498e3d6 | 1234 | current_templates->start->name); |
355afbcd KR |
1235 | return; |
1236 | } | |
1237 | ||
61c49d66 ILT |
1238 | if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) == (IsPrefix|IgnoreSize)) |
1239 | { | |
1240 | /* Warn them that a data or address size prefix doesn't affect | |
1241 | assembly of the next line of code. */ | |
1242 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
1243 | } | |
1244 | ||
4498e3d6 | 1245 | /* Copy the template we found. */ |
f3d817d8 | 1246 | i.tm = *t; |
227b6b55 ILT |
1247 | if (found_reverse_match) |
1248 | { | |
1249 | i.tm.operand_types[0] = t->operand_types[1]; | |
1250 | i.tm.operand_types[1] = t->operand_types[0]; | |
1251 | } | |
355afbcd | 1252 | |
73a8be66 ILT |
1253 | if (i.tm.opcode_modifier & FWait) |
1254 | if (! add_prefix (FWAIT_OPCODE)) | |
1255 | return; | |
1256 | ||
4498e3d6 ILT |
1257 | /* Check string instruction segment overrides */ |
1258 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) | |
1259 | { | |
73a8be66 | 1260 | int mem_op = (i.types[0] & AnyMem) ? 0 : 1; |
8081c2be | 1261 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) |
4498e3d6 | 1262 | { |
73a8be66 | 1263 | if (i.seg[0] != NULL && i.seg[0] != &es) |
4498e3d6 | 1264 | { |
aa56747a ILT |
1265 | as_bad (_("`%s' operand %d must use `%%es' segment"), |
1266 | i.tm.name, | |
1267 | mem_op + 1); | |
4498e3d6 ILT |
1268 | return; |
1269 | } | |
1270 | /* There's only ever one segment override allowed per instruction. | |
1271 | This instruction possibly has a legal segment override on the | |
1272 | second operand, so copy the segment to where non-string | |
1273 | instructions store it, allowing common code. */ | |
1274 | i.seg[0] = i.seg[1]; | |
1275 | } | |
8081c2be | 1276 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) |
4498e3d6 | 1277 | { |
73a8be66 | 1278 | if (i.seg[1] != NULL && i.seg[1] != &es) |
4498e3d6 | 1279 | { |
aa56747a ILT |
1280 | as_bad (_("`%s' operand %d must use `%%es' segment"), |
1281 | i.tm.name, | |
1282 | mem_op + 2); | |
4498e3d6 ILT |
1283 | return; |
1284 | } | |
1285 | } | |
1286 | } | |
1287 | ||
73a8be66 ILT |
1288 | /* If matched instruction specifies an explicit opcode suffix, use |
1289 | it. */ | |
284f02bb | 1290 | if (i.tm.opcode_modifier & (Size16 | Size32)) |
c54c7aac | 1291 | { |
284f02bb | 1292 | if (i.tm.opcode_modifier & Size16) |
c54c7aac KR |
1293 | i.suffix = WORD_OPCODE_SUFFIX; |
1294 | else | |
1295 | i.suffix = DWORD_OPCODE_SUFFIX; | |
1296 | } | |
73a8be66 | 1297 | else if (i.reg_operands) |
355afbcd | 1298 | { |
73a8be66 ILT |
1299 | /* If there's no opcode suffix we try to invent one based on |
1300 | register operands. */ | |
1301 | if (!i.suffix) | |
3ea36b53 | 1302 | { |
73a8be66 ILT |
1303 | /* We take i.suffix from the last register operand specified, |
1304 | Destination register type is more significant than source | |
1305 | register type. */ | |
1306 | int op; | |
1307 | for (op = i.operands; --op >= 0; ) | |
1308 | if (i.types[op] & Reg) | |
1309 | { | |
1310 | i.suffix = ((i.types[op] & Reg8) ? BYTE_OPCODE_SUFFIX : | |
1311 | (i.types[op] & Reg16) ? WORD_OPCODE_SUFFIX : | |
1312 | DWORD_OPCODE_SUFFIX); | |
1313 | break; | |
1314 | } | |
1315 | } | |
1316 | else if (i.suffix == BYTE_OPCODE_SUFFIX) | |
1317 | { | |
1318 | int op; | |
1319 | for (op = i.operands; --op >= 0; ) | |
1320 | { | |
1321 | /* If this is an eight bit register, it's OK. If it's | |
1322 | the 16 or 32 bit version of an eight bit register, | |
1323 | we will just use the low portion, and that's OK too. */ | |
1324 | if (i.types[op] & Reg8) | |
1325 | continue; | |
1326 | if ((i.types[op] & WordReg) && i.regs[op]->reg_num < 4 | |
1327 | #if 0 | |
1328 | /* Check that the template allows eight bit regs | |
1329 | This kills insns such as `orb $1,%edx', which | |
1330 | maybe should be allowed. */ | |
1331 | && (i.tm.operand_types[op] & (Reg8|InOutPortReg)) | |
1332 | #endif | |
1333 | ) | |
1334 | { | |
1335 | #if REGISTER_WARNINGS | |
1336 | if ((i.tm.operand_types[op] & InOutPortReg) == 0) | |
1337 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
1338 | (i.regs[op] - (i.types[op] & Reg16 ? 8 : 16))->reg_name, | |
1339 | i.regs[op]->reg_name, | |
1340 | i.suffix); | |
1341 | #endif | |
1342 | continue; | |
1343 | } | |
1344 | /* Any other register is bad */ | |
1345 | if (i.types[op] & (Reg | RegMMX | Control | Debug | Test | |
1346 | | FloatReg | FloatAcc | SReg2 | SReg3)) | |
1347 | { | |
1348 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
1349 | i.regs[op]->reg_name, | |
1350 | i.tm.name, | |
1351 | i.suffix); | |
1352 | return; | |
1353 | } | |
1354 | } | |
3ea36b53 | 1355 | } |
73a8be66 ILT |
1356 | else if (i.suffix == DWORD_OPCODE_SUFFIX) |
1357 | { | |
1358 | int op; | |
1359 | for (op = i.operands; --op >= 0; ) | |
1360 | /* Reject eight bit registers, except where the template | |
1361 | requires them. (eg. movzb) */ | |
1362 | if ((i.types[op] & Reg8) != 0 | |
1363 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
1364 | { | |
1365 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
1366 | i.regs[op]->reg_name, | |
1367 | i.tm.name, | |
1368 | i.suffix); | |
1369 | return; | |
1370 | } | |
1371 | #if REGISTER_WARNINGS | |
1372 | /* Warn if the e prefix on a general reg is missing. */ | |
1373 | else if ((i.types[op] & Reg16) != 0 | |
1374 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) | |
1375 | { | |
1376 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
1377 | (i.regs[op] + 8)->reg_name, | |
1378 | i.regs[op]->reg_name, | |
1379 | i.suffix); | |
1380 | } | |
1381 | #endif | |
1382 | } | |
1383 | else if (i.suffix == WORD_OPCODE_SUFFIX) | |
1384 | { | |
1385 | int op; | |
1386 | for (op = i.operands; --op >= 0; ) | |
1387 | /* Reject eight bit registers, except where the template | |
1388 | requires them. (eg. movzb) */ | |
1389 | if ((i.types[op] & Reg8) != 0 | |
1390 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
1391 | { | |
1392 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
1393 | i.regs[op]->reg_name, | |
1394 | i.tm.name, | |
1395 | i.suffix); | |
1396 | return; | |
1397 | } | |
1398 | #if REGISTER_WARNINGS | |
1399 | /* Warn if the e prefix on a general reg is present. */ | |
1400 | else if ((i.types[op] & Reg32) != 0 | |
1401 | && (i.tm.operand_types[op] & (Reg16|Acc)) != 0) | |
1402 | { | |
1403 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
1404 | (i.regs[op] - 8)->reg_name, | |
1405 | i.regs[op]->reg_name, | |
1406 | i.suffix); | |
1407 | } | |
1408 | #endif | |
1409 | } | |
1410 | else | |
1411 | abort(); | |
3ea36b53 | 1412 | } |
355afbcd KR |
1413 | |
1414 | /* Make still unresolved immediate matches conform to size of immediate | |
5819d632 | 1415 | given in i.suffix. Note: overlap2 cannot be an immediate! */ |
355afbcd KR |
1416 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32)) |
1417 | && overlap0 != Imm8 && overlap0 != Imm8S | |
1418 | && overlap0 != Imm16 && overlap0 != Imm32) | |
1419 | { | |
0351b70c ILT |
1420 | if (i.suffix) |
1421 | { | |
1422 | overlap0 &= (i.suffix == BYTE_OPCODE_SUFFIX ? (Imm8 | Imm8S) : | |
1423 | (i.suffix == WORD_OPCODE_SUFFIX ? Imm16 : Imm32)); | |
1424 | } | |
1425 | else if (overlap0 == (Imm16 | Imm32)) | |
1426 | { | |
1427 | overlap0 = | |
1428 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; | |
1429 | } | |
1430 | else | |
355afbcd | 1431 | { |
48401fcf | 1432 | as_bad (_("no opcode suffix given; can't determine immediate size")); |
355afbcd KR |
1433 | return; |
1434 | } | |
355afbcd KR |
1435 | } |
1436 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32)) | |
1437 | && overlap1 != Imm8 && overlap1 != Imm8S | |
1438 | && overlap1 != Imm16 && overlap1 != Imm32) | |
1439 | { | |
0351b70c ILT |
1440 | if (i.suffix) |
1441 | { | |
1442 | overlap1 &= (i.suffix == BYTE_OPCODE_SUFFIX ? (Imm8 | Imm8S) : | |
1443 | (i.suffix == WORD_OPCODE_SUFFIX ? Imm16 : Imm32)); | |
1444 | } | |
1445 | else if (overlap1 == (Imm16 | Imm32)) | |
1446 | { | |
1447 | overlap1 = | |
1448 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; | |
1449 | } | |
1450 | else | |
355afbcd | 1451 | { |
48401fcf | 1452 | as_bad (_("no opcode suffix given; can't determine immediate size")); |
355afbcd KR |
1453 | return; |
1454 | } | |
355afbcd | 1455 | } |
5819d632 | 1456 | assert ((overlap2 & Imm) == 0); |
355afbcd KR |
1457 | |
1458 | i.types[0] = overlap0; | |
355afbcd KR |
1459 | if (overlap0 & ImplicitRegister) |
1460 | i.reg_operands--; | |
0351b70c ILT |
1461 | if (overlap0 & Imm1) |
1462 | i.imm_operands = 0; /* kludge for shift insns */ | |
1463 | ||
1464 | i.types[1] = overlap1; | |
355afbcd KR |
1465 | if (overlap1 & ImplicitRegister) |
1466 | i.reg_operands--; | |
0351b70c ILT |
1467 | |
1468 | i.types[2] = overlap2; | |
355afbcd KR |
1469 | if (overlap2 & ImplicitRegister) |
1470 | i.reg_operands--; | |
355afbcd | 1471 | |
355afbcd | 1472 | /* Finalize opcode. First, we change the opcode based on the operand |
c5dd66a1 KR |
1473 | size given by i.suffix: we never have to change things for byte insns, |
1474 | or when no opcode suffix is need to size the operands. */ | |
355afbcd | 1475 | |
227b6b55 | 1476 | if (!i.suffix && (i.tm.opcode_modifier & W)) |
355afbcd | 1477 | { |
48401fcf | 1478 | as_bad (_("no opcode suffix given and no register operands; can't size instruction")); |
355afbcd KR |
1479 | return; |
1480 | } | |
1481 | ||
1482 | if (i.suffix && i.suffix != BYTE_OPCODE_SUFFIX) | |
1483 | { | |
1484 | /* Select between byte and word/dword operations. */ | |
227b6b55 | 1485 | if (i.tm.opcode_modifier & W) |
73a8be66 ILT |
1486 | { |
1487 | if (i.tm.opcode_modifier & ShortForm) | |
1488 | i.tm.base_opcode |= 8; | |
1489 | else | |
1490 | i.tm.base_opcode |= 1; | |
1491 | } | |
8c927202 | 1492 | /* Now select between word & dword operations via the operand |
73a8be66 ILT |
1493 | size prefix, except for instructions that will ignore this |
1494 | prefix anyway. */ | |
1495 | if ((i.suffix == DWORD_OPCODE_SUFFIX | |
1496 | || i.suffix == LONG_OPCODE_SUFFIX) == flag_16bit_code | |
284f02bb | 1497 | && !(i.tm.opcode_modifier & IgnoreSize)) |
355afbcd | 1498 | { |
73a8be66 | 1499 | unsigned int prefix = DATA_PREFIX_OPCODE; |
aa56747a ILT |
1500 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ |
1501 | prefix = ADDR_PREFIX_OPCODE; | |
1502 | ||
1503 | if (! add_prefix (prefix)) | |
4498e3d6 | 1504 | return; |
355afbcd | 1505 | } |
73a8be66 ILT |
1506 | /* Size floating point instruction. */ |
1507 | if (i.suffix == LONG_OPCODE_SUFFIX) | |
1508 | { | |
1509 | if (i.tm.opcode_modifier & FloatMF) | |
1510 | i.tm.base_opcode ^= 4; | |
1511 | } | |
355afbcd KR |
1512 | } |
1513 | ||
1514 | /* For insns with operands there are more diddles to do to the opcode. */ | |
1515 | if (i.operands) | |
1516 | { | |
c54c7aac KR |
1517 | /* Default segment register this instruction will use |
1518 | for memory accesses. 0 means unknown. | |
1519 | This is only for optimizing out unnecessary segment overrides. */ | |
1520 | const seg_entry *default_seg = 0; | |
1521 | ||
aa56747a ILT |
1522 | /* If we found a reverse match we must alter the opcode |
1523 | direction bit. found_reverse_match holds bits to change | |
1524 | (different for int & float insns). */ | |
355afbcd | 1525 | |
4498e3d6 | 1526 | i.tm.base_opcode ^= found_reverse_match; |
355afbcd | 1527 | |
c5dd66a1 | 1528 | /* The imul $imm, %reg instruction is converted into |
4498e3d6 ILT |
1529 | imul $imm, %reg, %reg, and the clr %reg instruction |
1530 | is converted into xor %reg, %reg. */ | |
1531 | if (i.tm.opcode_modifier & regKludge) | |
2fb44892 | 1532 | { |
4498e3d6 ILT |
1533 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; |
1534 | /* Pretend we saw the extra register operand. */ | |
1535 | i.regs[first_reg_op+1] = i.regs[first_reg_op]; | |
2fb44892 ILT |
1536 | i.reg_operands = 2; |
1537 | } | |
1538 | ||
227b6b55 | 1539 | if (i.tm.opcode_modifier & ShortForm) |
355afbcd KR |
1540 | { |
1541 | /* The register or float register operand is in operand 0 or 1. */ | |
ad660eb1 | 1542 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; |
355afbcd | 1543 | /* Register goes in low 3 bits of opcode. */ |
227b6b55 | 1544 | i.tm.base_opcode |= i.regs[op]->reg_num; |
73a8be66 ILT |
1545 | if ((i.tm.opcode_modifier & Ugh) != 0) |
1546 | { | |
1547 | /* Warn about some common errors, but press on regardless. | |
1548 | The first case can be generated by gcc (<= 2.8.1). */ | |
1549 | if (i.operands == 2) | |
1550 | { | |
1551 | /* reversed arguments on faddp, fsubp, etc. */ | |
1552 | as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, | |
1553 | i.regs[1]->reg_name, | |
1554 | i.regs[0]->reg_name); | |
1555 | } | |
1556 | else | |
1557 | { | |
1558 | /* extraneous `l' suffix on fp insn */ | |
1559 | as_warn (_("translating to `%s %%%s'"), i.tm.name, | |
1560 | i.regs[0]->reg_name); | |
1561 | } | |
1562 | } | |
355afbcd | 1563 | } |
227b6b55 | 1564 | else if (i.tm.opcode_modifier & Modrm) |
355afbcd | 1565 | { |
227b6b55 ILT |
1566 | /* The opcode is completed (modulo i.tm.extension_opcode which |
1567 | must be put into the modrm byte). | |
1568 | Now, we make the modrm & index base bytes based on all the | |
1569 | info we've collected. */ | |
355afbcd KR |
1570 | |
1571 | /* i.reg_operands MUST be the number of real register operands; | |
c5dd66a1 | 1572 | implicit registers do not count. */ |
355afbcd KR |
1573 | if (i.reg_operands == 2) |
1574 | { | |
1575 | unsigned int source, dest; | |
454b0ccd ILT |
1576 | source = ((i.types[0] |
1577 | & (Reg | |
1578 | | SReg2 | |
1579 | | SReg3 | |
1580 | | Control | |
1581 | | Debug | |
1582 | | Test | |
1583 | | RegMMX)) | |
1584 | ? 0 : 1); | |
355afbcd | 1585 | dest = source + 1; |
4498e3d6 ILT |
1586 | |
1587 | /* Certain instructions expect the destination to be | |
1588 | in the i.rm.reg field. This is by far the | |
1589 | exceptional case. For these instructions, if the | |
1590 | source operand is a register, we must reverse the | |
1591 | i.rm.reg and i.rm.regmem fields. We accomplish | |
1592 | this by pretending that the two register operands | |
1593 | were given in the reverse order. */ | |
1594 | if (i.tm.opcode_modifier & ReverseRegRegmem) | |
1595 | { | |
73a8be66 | 1596 | const reg_entry *tmp = i.regs[source]; |
4498e3d6 ILT |
1597 | i.regs[source] = i.regs[dest]; |
1598 | i.regs[dest] = tmp; | |
1599 | } | |
1600 | ||
355afbcd | 1601 | i.rm.mode = 3; |
c5dd66a1 | 1602 | /* We must be careful to make sure that all |
454b0ccd | 1603 | segment/control/test/debug/MMX registers go into |
4498e3d6 | 1604 | the i.rm.reg field (despite whether they are |
454b0ccd ILT |
1605 | source or destination operands). */ |
1606 | if (i.regs[dest]->reg_type | |
1607 | & (SReg2 | SReg3 | Control | Debug | Test | RegMMX)) | |
355afbcd KR |
1608 | { |
1609 | i.rm.reg = i.regs[dest]->reg_num; | |
1610 | i.rm.regmem = i.regs[source]->reg_num; | |
1611 | } | |
1612 | else | |
1613 | { | |
1614 | i.rm.reg = i.regs[source]->reg_num; | |
1615 | i.rm.regmem = i.regs[dest]->reg_num; | |
1616 | } | |
1617 | } | |
1618 | else | |
1619 | { /* if it's not 2 reg operands... */ | |
1620 | if (i.mem_operands) | |
1621 | { | |
1622 | unsigned int fake_zero_displacement = 0; | |
73a8be66 | 1623 | unsigned int op = ((i.types[0] & AnyMem) |
4498e3d6 | 1624 | ? 0 |
73a8be66 | 1625 | : (i.types[1] & AnyMem) ? 1 : 2); |
355afbcd | 1626 | |
ec1e6bb8 | 1627 | default_seg = &ds; |
355afbcd | 1628 | |
ec1e6bb8 | 1629 | if (! i.base_reg) |
355afbcd | 1630 | { |
ec1e6bb8 ILT |
1631 | i.rm.mode = 0; |
1632 | if (! i.disp_operands) | |
1633 | fake_zero_displacement = 1; | |
1634 | if (! i.index_reg) | |
355afbcd | 1635 | { |
ec1e6bb8 | 1636 | /* Operand is just <disp> */ |
0351b70c ILT |
1637 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) |
1638 | { | |
1639 | i.rm.regmem = NO_BASE_REGISTER_16; | |
1640 | i.types[op] &= ~Disp; | |
1641 | i.types[op] |= Disp16; | |
1642 | } | |
1643 | else | |
1644 | { | |
1645 | i.rm.regmem = NO_BASE_REGISTER; | |
1646 | i.types[op] &= ~Disp; | |
1647 | i.types[op] |= Disp32; | |
1648 | } | |
355afbcd | 1649 | } |
0351b70c | 1650 | else /* ! i.base_reg && i.index_reg */ |
355afbcd | 1651 | { |
0351b70c ILT |
1652 | i.sib.index = i.index_reg->reg_num; |
1653 | i.sib.base = NO_BASE_REGISTER; | |
1654 | i.sib.scale = i.log2_scale_factor; | |
ec1e6bb8 ILT |
1655 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
1656 | i.types[op] &= ~Disp; | |
1657 | i.types[op] |= Disp32; /* Must be 32 bit */ | |
355afbcd KR |
1658 | } |
1659 | } | |
0351b70c ILT |
1660 | else if (i.base_reg->reg_type & Reg16) |
1661 | { | |
1662 | switch (i.base_reg->reg_num) | |
1663 | { | |
1664 | case 3: /* (%bx) */ | |
1665 | if (! i.index_reg) | |
1666 | i.rm.regmem = 7; | |
1667 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
1668 | i.rm.regmem = i.index_reg->reg_num - 6; | |
1669 | break; | |
1670 | case 5: /* (%bp) */ | |
1671 | default_seg = &ss; | |
1672 | if (! i.index_reg) | |
1673 | { | |
1674 | i.rm.regmem = 6; | |
1675 | if ((i.types[op] & Disp) == 0) | |
1676 | { | |
1677 | /* fake (%bp) into 0(%bp) */ | |
1678 | i.types[op] |= Disp8; | |
1679 | fake_zero_displacement = 1; | |
1680 | } | |
1681 | } | |
1682 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
1683 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
1684 | break; | |
1685 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
1686 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
1687 | } | |
1688 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
1689 | } | |
1690 | else /* i.base_reg and 32 bit mode */ | |
355afbcd | 1691 | { |
355afbcd | 1692 | i.rm.regmem = i.base_reg->reg_num; |
0351b70c | 1693 | i.sib.base = i.base_reg->reg_num; |
ec1e6bb8 | 1694 | if (i.base_reg->reg_num == EBP_REG_NUM) |
355afbcd | 1695 | { |
ec1e6bb8 ILT |
1696 | default_seg = &ss; |
1697 | if (i.disp_operands == 0) | |
1698 | { | |
355afbcd | 1699 | fake_zero_displacement = 1; |
ad660eb1 | 1700 | i.types[op] |= Disp8; |
355afbcd KR |
1701 | } |
1702 | } | |
ec1e6bb8 ILT |
1703 | else if (i.base_reg->reg_num == ESP_REG_NUM) |
1704 | { | |
1705 | default_seg = &ss; | |
1706 | } | |
0351b70c | 1707 | i.sib.scale = i.log2_scale_factor; |
ec1e6bb8 ILT |
1708 | if (! i.index_reg) |
1709 | { | |
1710 | /* <disp>(%esp) becomes two byte modrm | |
1711 | with no index register. We've already | |
1712 | stored the code for esp in i.rm.regmem | |
1713 | ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any | |
1714 | base register besides %esp will not use | |
1715 | the extra modrm byte. */ | |
0351b70c | 1716 | i.sib.index = NO_INDEX_REGISTER; |
ec1e6bb8 ILT |
1717 | #if ! SCALE1_WHEN_NO_INDEX |
1718 | /* Another case where we force the second | |
1719 | modrm byte. */ | |
1720 | if (i.log2_scale_factor) | |
1721 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
1722 | #endif | |
1723 | } | |
1724 | else | |
1725 | { | |
0351b70c | 1726 | i.sib.index = i.index_reg->reg_num; |
ec1e6bb8 ILT |
1727 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
1728 | } | |
1729 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
355afbcd | 1730 | } |
ec1e6bb8 | 1731 | |
355afbcd KR |
1732 | if (fake_zero_displacement) |
1733 | { | |
ad660eb1 | 1734 | /* Fakes a zero displacement assuming that i.types[op] |
c5dd66a1 | 1735 | holds the correct displacement size. */ |
355afbcd | 1736 | exp = &disp_expressions[i.disp_operands++]; |
ad660eb1 | 1737 | i.disps[op] = exp; |
5ac34ac3 | 1738 | exp->X_op = O_constant; |
355afbcd KR |
1739 | exp->X_add_number = 0; |
1740 | exp->X_add_symbol = (symbolS *) 0; | |
5ac34ac3 | 1741 | exp->X_op_symbol = (symbolS *) 0; |
355afbcd | 1742 | } |
355afbcd KR |
1743 | } |
1744 | ||
454b0ccd | 1745 | /* Fill in i.rm.reg or i.rm.regmem field with register |
227b6b55 ILT |
1746 | operand (if any) based on i.tm.extension_opcode. |
1747 | Again, we must be careful to make sure that | |
1748 | segment/control/debug/test/MMX registers are coded | |
1749 | into the i.rm.reg field. */ | |
355afbcd KR |
1750 | if (i.reg_operands) |
1751 | { | |
ad660eb1 | 1752 | unsigned int op = |
454b0ccd ILT |
1753 | ((i.types[0] |
1754 | & (Reg | SReg2 | SReg3 | Control | Debug | |
1755 | | Test | RegMMX)) | |
1756 | ? 0 | |
1757 | : ((i.types[1] | |
1758 | & (Reg | SReg2 | SReg3 | Control | Debug | |
1759 | | Test | RegMMX)) | |
1760 | ? 1 | |
1761 | : 2)); | |
c5dd66a1 KR |
1762 | /* If there is an extension opcode to put here, the |
1763 | register number must be put into the regmem field. */ | |
227b6b55 | 1764 | if (i.tm.extension_opcode != None) |
ad660eb1 | 1765 | i.rm.regmem = i.regs[op]->reg_num; |
355afbcd | 1766 | else |
ad660eb1 | 1767 | i.rm.reg = i.regs[op]->reg_num; |
355afbcd KR |
1768 | |
1769 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 | |
c5dd66a1 | 1770 | we must set it to 3 to indicate this is a register |
4498e3d6 | 1771 | operand in the regmem field. */ |
355afbcd KR |
1772 | if (!i.mem_operands) |
1773 | i.rm.mode = 3; | |
1774 | } | |
1775 | ||
1776 | /* Fill in i.rm.reg field with extension opcode (if any). */ | |
227b6b55 ILT |
1777 | if (i.tm.extension_opcode != None) |
1778 | i.rm.reg = i.tm.extension_opcode; | |
355afbcd | 1779 | } |
c54c7aac | 1780 | } |
73a8be66 | 1781 | else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) |
4498e3d6 ILT |
1782 | { |
1783 | if (i.tm.base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1) | |
1784 | { | |
73a8be66 | 1785 | as_bad (_("you can't `pop %%cs'")); |
4498e3d6 ILT |
1786 | return; |
1787 | } | |
1788 | i.tm.base_opcode |= (i.regs[0]->reg_num << 3); | |
1789 | } | |
73a8be66 | 1790 | else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32) |
4498e3d6 | 1791 | { |
4498e3d6 ILT |
1792 | default_seg = &ds; |
1793 | } | |
1794 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
1795 | { | |
1796 | /* For the string instructions that allow a segment override | |
1797 | on one of their operands, the default segment is ds. */ | |
1798 | default_seg = &ds; | |
1799 | } | |
c54c7aac | 1800 | |
c54c7aac KR |
1801 | /* If a segment was explicitly specified, |
1802 | and the specified segment is not the default, | |
1803 | use an opcode prefix to select it. | |
1804 | If we never figured out what the default segment is, | |
1805 | then default_seg will be zero at this point, | |
1806 | and the specified segment prefix will always be used. */ | |
4498e3d6 | 1807 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
c54c7aac | 1808 | { |
aa56747a | 1809 | if (! add_prefix (i.seg[0]->seg_prefix)) |
4498e3d6 | 1810 | return; |
355afbcd KR |
1811 | } |
1812 | } | |
73a8be66 ILT |
1813 | else if ((i.tm.opcode_modifier & Ugh) != 0) |
1814 | { | |
1815 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc */ | |
1816 | as_warn (_("translating to `%sp'"), i.tm.name); | |
1817 | } | |
355afbcd KR |
1818 | } |
1819 | ||
1820 | /* Handle conversion of 'int $3' --> special int3 insn. */ | |
227b6b55 | 1821 | if (i.tm.base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3) |
355afbcd | 1822 | { |
227b6b55 | 1823 | i.tm.base_opcode = INT3_OPCODE; |
355afbcd KR |
1824 | i.imm_operands = 0; |
1825 | } | |
1826 | ||
1827 | /* We are ready to output the insn. */ | |
1828 | { | |
1829 | register char *p; | |
1830 | ||
1831 | /* Output jumps. */ | |
227b6b55 | 1832 | if (i.tm.opcode_modifier & Jump) |
355afbcd | 1833 | { |
61c49d66 | 1834 | long n = (long) i.disps[0]->X_add_number; |
0351b70c ILT |
1835 | int prefix = (i.prefix[DATA_PREFIX] != 0); |
1836 | int code16 = 0; | |
1837 | ||
1838 | if (prefix) | |
1839 | { | |
1840 | i.prefixes -= 1; | |
1841 | code16 = CODE16; | |
1842 | } | |
1843 | if (flag_16bit_code) | |
1844 | code16 ^= CODE16; | |
355afbcd | 1845 | |
4498e3d6 | 1846 | if (i.prefixes != 0) |
aa56747a | 1847 | as_warn (_("skipping prefixes on this instruction")); |
4498e3d6 | 1848 | |
5ac34ac3 | 1849 | if (i.disps[0]->X_op == O_constant) |
355afbcd | 1850 | { |
355afbcd KR |
1851 | if (fits_in_signed_byte (n)) |
1852 | { | |
ad660eb1 | 1853 | insn_size += 2; |
0351b70c | 1854 | p = frag_more (2); |
227b6b55 | 1855 | p[0] = i.tm.base_opcode; |
355afbcd | 1856 | p[1] = n; |
355afbcd | 1857 | } |
355afbcd | 1858 | else |
0351b70c | 1859 | { |
4498e3d6 | 1860 | /* Use 16-bit jumps only for 16-bit code, |
c54c7aac | 1861 | because text segments are limited to 64K anyway; |
4498e3d6 ILT |
1862 | Use 32-bit jumps for 32-bit code, because they're faster, |
1863 | and a 16-bit jump will clear the top 16 bits of %eip. */ | |
0351b70c ILT |
1864 | int jmp_size = code16 ? 2 : 4; |
1865 | if (code16 && !fits_in_signed_word (n)) | |
c54c7aac | 1866 | { |
48401fcf | 1867 | as_bad (_("16-bit jump out of range")); |
c54c7aac KR |
1868 | return; |
1869 | } | |
1870 | ||
227b6b55 | 1871 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) |
355afbcd KR |
1872 | { /* pace */ |
1873 | /* unconditional jump */ | |
0351b70c ILT |
1874 | insn_size += prefix + 1 + jmp_size; |
1875 | p = frag_more (prefix + 1 + jmp_size); | |
1876 | if (prefix) | |
1877 | *p++ = DATA_PREFIX_OPCODE; | |
1878 | *p++ = (char) 0xe9; | |
1879 | md_number_to_chars (p, (valueT) n, jmp_size); | |
355afbcd KR |
1880 | } |
1881 | else | |
1882 | { | |
1883 | /* conditional jump */ | |
0351b70c ILT |
1884 | insn_size += prefix + 2 + jmp_size; |
1885 | p = frag_more (prefix + 2 + jmp_size); | |
1886 | if (prefix) | |
1887 | *p++ = DATA_PREFIX_OPCODE; | |
1888 | *p++ = TWO_BYTE_OPCODE_ESCAPE; | |
1889 | *p++ = i.tm.base_opcode + 0x10; | |
1890 | md_number_to_chars (p, (valueT) n, jmp_size); | |
355afbcd KR |
1891 | } |
1892 | } | |
49864cfa KR |
1893 | } |
1894 | else | |
1895 | { | |
0351b70c | 1896 | int size = code16 ? 2 : 4; |
c54c7aac | 1897 | |
355afbcd | 1898 | /* It's a symbol; end frag & setup for relax. |
49864cfa KR |
1899 | Make sure there are more than 6 chars left in the current frag; |
1900 | if not we'll have to start a new one. */ | |
0351b70c ILT |
1901 | frag_grow (prefix + 1 + 2 + size); |
1902 | insn_size += 1 + prefix; | |
1903 | p = frag_more (1 + prefix); | |
1904 | if (prefix) | |
1905 | *p++ = DATA_PREFIX_OPCODE; | |
1906 | *p = i.tm.base_opcode; | |
355afbcd | 1907 | frag_var (rs_machine_dependent, |
0351b70c | 1908 | prefix + 2 + size, /* 2 opcode/prefix + displacement */ |
355afbcd KR |
1909 | 1, |
1910 | ((unsigned char) *p == JUMP_PC_RELATIVE | |
0351b70c ILT |
1911 | ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16 |
1912 | : ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16), | |
355afbcd | 1913 | i.disps[0]->X_add_symbol, |
f59fb6ca | 1914 | (offsetT) n, p); |
355afbcd KR |
1915 | } |
1916 | } | |
227b6b55 | 1917 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) |
355afbcd | 1918 | { |
227b6b55 | 1919 | int size = (i.tm.opcode_modifier & JumpByte) ? 1 : 4; |
61c49d66 | 1920 | long n = (long) i.disps[0]->X_add_number; |
c54c7aac | 1921 | |
aa56747a | 1922 | if (size == 1) /* then this is a loop or jecxz type instruction */ |
c54c7aac | 1923 | { |
aa56747a | 1924 | if (i.prefix[ADDR_PREFIX]) |
c54c7aac | 1925 | { |
0351b70c | 1926 | insn_size += 1; |
aa56747a | 1927 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); |
0351b70c ILT |
1928 | i.prefixes -= 1; |
1929 | } | |
1930 | } | |
1931 | else | |
1932 | { | |
1933 | int code16 = 0; | |
1934 | ||
1935 | if (i.prefix[DATA_PREFIX]) | |
1936 | { | |
aa56747a | 1937 | insn_size += 1; |
0351b70c | 1938 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); |
73a8be66 | 1939 | i.prefixes -= 1; |
0351b70c | 1940 | code16 = CODE16; |
c54c7aac | 1941 | } |
0351b70c ILT |
1942 | if (flag_16bit_code) |
1943 | code16 ^= CODE16; | |
1944 | ||
1945 | if (code16) | |
1946 | size = 2; | |
c54c7aac KR |
1947 | } |
1948 | ||
aa56747a ILT |
1949 | if (i.prefixes != 0) |
1950 | as_warn (_("skipping prefixes on this instruction")); | |
1951 | ||
227b6b55 | 1952 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
355afbcd | 1953 | { |
0351b70c ILT |
1954 | insn_size += 1 + size; |
1955 | p = frag_more (1 + size); | |
355afbcd KR |
1956 | } |
1957 | else | |
1958 | { | |
0351b70c ILT |
1959 | insn_size += 2 + size; /* opcode can be at most two bytes */ |
1960 | p = frag_more (2 + size); | |
227b6b55 | 1961 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
355afbcd | 1962 | } |
0351b70c | 1963 | *p++ = i.tm.base_opcode & 0xff; |
355afbcd | 1964 | |
5ac34ac3 | 1965 | if (i.disps[0]->X_op == O_constant) |
355afbcd | 1966 | { |
355afbcd KR |
1967 | if (size == 1 && !fits_in_signed_byte (n)) |
1968 | { | |
61c49d66 | 1969 | as_bad (_("`%s' only takes byte displacement; %ld shortened to %d"), |
73a8be66 | 1970 | i.tm.name, n, *p); |
355afbcd | 1971 | } |
0351b70c ILT |
1972 | else if (size == 2 && !fits_in_signed_word (n)) |
1973 | { | |
1974 | as_bad (_("16-bit jump out of range")); | |
1975 | return; | |
1976 | } | |
1977 | md_number_to_chars (p, (valueT) n, size); | |
49864cfa KR |
1978 | } |
1979 | else | |
1980 | { | |
5ac34ac3 | 1981 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
f0b37b4a KR |
1982 | i.disps[0], 1, reloc (size, 1, i.disp_reloc[0])); |
1983 | ||
355afbcd KR |
1984 | } |
1985 | } | |
227b6b55 | 1986 | else if (i.tm.opcode_modifier & JumpInterSegment) |
355afbcd | 1987 | { |
0351b70c ILT |
1988 | int size; |
1989 | int reloc_type; | |
1990 | int prefix = i.prefix[DATA_PREFIX] != 0; | |
1991 | int code16 = 0; | |
4498e3d6 | 1992 | |
0351b70c ILT |
1993 | if (prefix) |
1994 | { | |
1995 | code16 = CODE16; | |
1996 | i.prefixes -= 1; | |
1997 | } | |
c54c7aac | 1998 | if (flag_16bit_code) |
0351b70c ILT |
1999 | code16 ^= CODE16; |
2000 | ||
2001 | size = 4; | |
2002 | reloc_type = BFD_RELOC_32; | |
2003 | if (code16) | |
c54c7aac | 2004 | { |
0351b70c ILT |
2005 | size = 2; |
2006 | reloc_type = BFD_RELOC_16; | |
c54c7aac KR |
2007 | } |
2008 | ||
0351b70c ILT |
2009 | if (i.prefixes != 0) |
2010 | as_warn (_("skipping prefixes on this instruction")); | |
2011 | ||
2012 | insn_size += prefix + 1 + 2 + size; /* 1 opcode; 2 segment; offset */ | |
2013 | p = frag_more (prefix + 1 + 2 + size); | |
2014 | if (prefix) | |
2015 | *p++ = DATA_PREFIX_OPCODE; | |
2016 | *p++ = i.tm.base_opcode; | |
5ac34ac3 | 2017 | if (i.imms[1]->X_op == O_constant) |
0351b70c | 2018 | { |
61c49d66 ILT |
2019 | long n = (long) i.imms[1]->X_add_number; |
2020 | ||
0351b70c ILT |
2021 | if (size == 2 && !fits_in_unsigned_word (n)) |
2022 | { | |
2023 | as_bad (_("16-bit jump out of range")); | |
2024 | return; | |
2025 | } | |
2026 | md_number_to_chars (p, (valueT) n, size); | |
2027 | } | |
355afbcd | 2028 | else |
0351b70c ILT |
2029 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
2030 | i.imms[1], 0, reloc_type); | |
5ac34ac3 | 2031 | if (i.imms[0]->X_op != O_constant) |
0351b70c ILT |
2032 | as_bad (_("can't handle non absolute segment in `%s'"), |
2033 | i.tm.name); | |
2034 | md_number_to_chars (p + size, (valueT) i.imms[0]->X_add_number, 2); | |
355afbcd KR |
2035 | } |
2036 | else | |
2037 | { | |
2038 | /* Output normal instructions here. */ | |
2039 | unsigned char *q; | |
2040 | ||
4498e3d6 | 2041 | /* The prefix bytes. */ |
aa56747a ILT |
2042 | for (q = i.prefix; |
2043 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); | |
2044 | q++) | |
355afbcd | 2045 | { |
aa56747a ILT |
2046 | if (*q) |
2047 | { | |
aa56747a | 2048 | insn_size += 1; |
0351b70c | 2049 | p = frag_more (1); |
aa56747a ILT |
2050 | md_number_to_chars (p, (valueT) *q, 1); |
2051 | } | |
355afbcd KR |
2052 | } |
2053 | ||
2054 | /* Now the opcode; be careful about word order here! */ | |
227b6b55 | 2055 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
355afbcd | 2056 | { |
ad660eb1 | 2057 | insn_size += 1; |
0351b70c | 2058 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); |
355afbcd | 2059 | } |
227b6b55 | 2060 | else if (fits_in_unsigned_word (i.tm.base_opcode)) |
355afbcd | 2061 | { |
ad660eb1 | 2062 | insn_size += 2; |
0351b70c | 2063 | p = frag_more (2); |
355afbcd | 2064 | /* put out high byte first: can't use md_number_to_chars! */ |
227b6b55 ILT |
2065 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
2066 | *p = i.tm.base_opcode & 0xff; | |
355afbcd KR |
2067 | } |
2068 | else | |
2069 | { /* opcode is either 3 or 4 bytes */ | |
227b6b55 | 2070 | if (i.tm.base_opcode & 0xff000000) |
355afbcd | 2071 | { |
ad660eb1 | 2072 | insn_size += 4; |
0351b70c | 2073 | p = frag_more (4); |
227b6b55 | 2074 | *p++ = (i.tm.base_opcode >> 24) & 0xff; |
355afbcd KR |
2075 | } |
2076 | else | |
ad660eb1 | 2077 | { |
ad660eb1 | 2078 | insn_size += 3; |
0351b70c | 2079 | p = frag_more (3); |
ad660eb1 | 2080 | } |
227b6b55 ILT |
2081 | *p++ = (i.tm.base_opcode >> 16) & 0xff; |
2082 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
2083 | *p = (i.tm.base_opcode) & 0xff; | |
355afbcd KR |
2084 | } |
2085 | ||
0351b70c | 2086 | /* Now the modrm byte and sib byte (if present). */ |
227b6b55 | 2087 | if (i.tm.opcode_modifier & Modrm) |
355afbcd | 2088 | { |
ad660eb1 | 2089 | insn_size += 1; |
0351b70c | 2090 | p = frag_more (1); |
ad660eb1 ILT |
2091 | md_number_to_chars (p, |
2092 | (valueT) (i.rm.regmem << 0 | |
2093 | | i.rm.reg << 3 | |
2094 | | i.rm.mode << 6), | |
2095 | 1); | |
73a8be66 ILT |
2096 | /* If i.rm.regmem == ESP (4) |
2097 | && i.rm.mode != (Register mode) | |
0351b70c | 2098 | && not 16 bit |
73a8be66 | 2099 | ==> need second modrm byte. */ |
ec1e6bb8 | 2100 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING |
0351b70c ILT |
2101 | && i.rm.mode != 3 |
2102 | && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) | |
355afbcd | 2103 | { |
ad660eb1 | 2104 | insn_size += 1; |
0351b70c ILT |
2105 | p = frag_more (1); |
2106 | md_number_to_chars (p, | |
2107 | (valueT) (i.sib.base << 0 | |
2108 | | i.sib.index << 3 | |
2109 | | i.sib.scale << 6), | |
ad660eb1 | 2110 | 1); |
355afbcd KR |
2111 | } |
2112 | } | |
2113 | ||
2114 | if (i.disp_operands) | |
2115 | { | |
2116 | register unsigned int n; | |
2117 | ||
2118 | for (n = 0; n < i.operands; n++) | |
2119 | { | |
2120 | if (i.disps[n]) | |
2121 | { | |
5ac34ac3 | 2122 | if (i.disps[n]->X_op == O_constant) |
355afbcd | 2123 | { |
73a8be66 | 2124 | if (i.types[n] & Disp8) |
355afbcd | 2125 | { |
ad660eb1 | 2126 | insn_size += 1; |
0351b70c | 2127 | p = frag_more (1); |
ad660eb1 ILT |
2128 | md_number_to_chars (p, |
2129 | (valueT) i.disps[n]->X_add_number, | |
2130 | 1); | |
355afbcd | 2131 | } |
73a8be66 | 2132 | else if (i.types[n] & Disp16) |
355afbcd | 2133 | { |
ad660eb1 | 2134 | insn_size += 2; |
0351b70c | 2135 | p = frag_more (2); |
ad660eb1 ILT |
2136 | md_number_to_chars (p, |
2137 | (valueT) i.disps[n]->X_add_number, | |
2138 | 2); | |
355afbcd KR |
2139 | } |
2140 | else | |
73a8be66 | 2141 | { /* Disp32 */ |
ad660eb1 | 2142 | insn_size += 4; |
0351b70c | 2143 | p = frag_more (4); |
ad660eb1 ILT |
2144 | md_number_to_chars (p, |
2145 | (valueT) i.disps[n]->X_add_number, | |
2146 | 4); | |
355afbcd KR |
2147 | } |
2148 | } | |
0351b70c ILT |
2149 | else if (i.types[n] & Disp32) |
2150 | { | |
ad660eb1 | 2151 | insn_size += 4; |
0351b70c | 2152 | p = frag_more (4); |
5ac34ac3 | 2153 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, |
0351b70c ILT |
2154 | i.disps[n], 0, |
2155 | TC_RELOC (i.disp_reloc[n], BFD_RELOC_32)); | |
2156 | } | |
2157 | else | |
2158 | { /* must be Disp16 */ | |
2159 | insn_size += 2; | |
2160 | p = frag_more (2); | |
2161 | fix_new_exp (frag_now, p - frag_now->fr_literal, 2, | |
2162 | i.disps[n], 0, | |
2163 | TC_RELOC (i.disp_reloc[n], BFD_RELOC_16)); | |
355afbcd KR |
2164 | } |
2165 | } | |
2166 | } | |
2167 | } /* end displacement output */ | |
2168 | ||
2169 | /* output immediate */ | |
2170 | if (i.imm_operands) | |
2171 | { | |
2172 | register unsigned int n; | |
2173 | ||
2174 | for (n = 0; n < i.operands; n++) | |
2175 | { | |
2176 | if (i.imms[n]) | |
2177 | { | |
5ac34ac3 | 2178 | if (i.imms[n]->X_op == O_constant) |
355afbcd KR |
2179 | { |
2180 | if (i.types[n] & (Imm8 | Imm8S)) | |
2181 | { | |
ad660eb1 | 2182 | insn_size += 1; |
0351b70c | 2183 | p = frag_more (1); |
ad660eb1 ILT |
2184 | md_number_to_chars (p, |
2185 | (valueT) i.imms[n]->X_add_number, | |
2186 | 1); | |
355afbcd KR |
2187 | } |
2188 | else if (i.types[n] & Imm16) | |
2189 | { | |
ad660eb1 | 2190 | insn_size += 2; |
0351b70c | 2191 | p = frag_more (2); |
ad660eb1 ILT |
2192 | md_number_to_chars (p, |
2193 | (valueT) i.imms[n]->X_add_number, | |
2194 | 2); | |
355afbcd KR |
2195 | } |
2196 | else | |
2197 | { | |
ad660eb1 | 2198 | insn_size += 4; |
0351b70c | 2199 | p = frag_more (4); |
ad660eb1 ILT |
2200 | md_number_to_chars (p, |
2201 | (valueT) i.imms[n]->X_add_number, | |
2202 | 4); | |
355afbcd KR |
2203 | } |
2204 | } | |
2205 | else | |
49864cfa | 2206 | { /* not absolute_section */ |
f0b37b4a KR |
2207 | /* Need a 32-bit fixup (don't support 8bit |
2208 | non-absolute ims). Try to support other | |
2209 | sizes ... */ | |
2210 | int r_type; | |
355afbcd | 2211 | int size; |
f0b37b4a KR |
2212 | int pcrel = 0; |
2213 | ||
355afbcd KR |
2214 | if (i.types[n] & (Imm8 | Imm8S)) |
2215 | size = 1; | |
2216 | else if (i.types[n] & Imm16) | |
2217 | size = 2; | |
2218 | else | |
2219 | size = 4; | |
ad660eb1 | 2220 | insn_size += size; |
0351b70c ILT |
2221 | p = frag_more (size); |
2222 | r_type = reloc (size, 0, i.disp_reloc[0]); | |
f0b37b4a | 2223 | #ifdef BFD_ASSEMBLER |
c54c7aac | 2224 | if (r_type == BFD_RELOC_32 |
f0b37b4a | 2225 | && GOT_symbol |
0877841d ILT |
2226 | && GOT_symbol == i.imms[n]->X_add_symbol |
2227 | && (i.imms[n]->X_op == O_symbol | |
2228 | || (i.imms[n]->X_op == O_add | |
2229 | && (i.imms[n]->X_op_symbol->sy_value.X_op | |
2230 | == O_subtract)))) | |
f0b37b4a KR |
2231 | { |
2232 | r_type = BFD_RELOC_386_GOTPC; | |
2233 | i.imms[n]->X_add_number += 3; | |
2234 | } | |
2235 | #endif | |
5ac34ac3 | 2236 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
f0b37b4a | 2237 | i.imms[n], pcrel, r_type); |
355afbcd KR |
2238 | } |
2239 | } | |
2240 | } | |
2241 | } /* end immediate output */ | |
2242 | } | |
2243 | ||
fecd2382 | 2244 | #ifdef DEBUG386 |
ade614d5 | 2245 | if (flag_debug) |
355afbcd KR |
2246 | { |
2247 | pi (line, &i); | |
2248 | } | |
fecd2382 | 2249 | #endif /* DEBUG386 */ |
355afbcd | 2250 | } |
fecd2382 RP |
2251 | } |
2252 | \f | |
2253 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero | |
2254 | on error. */ | |
2255 | ||
355afbcd KR |
2256 | static int |
2257 | i386_operand (operand_string) | |
2258 | char *operand_string; | |
fecd2382 | 2259 | { |
355afbcd KR |
2260 | register char *op_string = operand_string; |
2261 | ||
355afbcd | 2262 | /* We check for an absolute prefix (differentiating, |
3c8df4ba | 2263 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
355afbcd KR |
2264 | if (*op_string == ABSOLUTE_PREFIX) |
2265 | { | |
4edc93e9 ILT |
2266 | ++op_string; |
2267 | if (is_space_char (*op_string)) | |
2268 | ++op_string; | |
355afbcd KR |
2269 | i.types[this_operand] |= JumpAbsolute; |
2270 | } | |
2271 | ||
2272 | /* Check if operand is a register. */ | |
2273 | if (*op_string == REGISTER_PREFIX) | |
2274 | { | |
0351b70c | 2275 | register const reg_entry *r; |
4edc93e9 ILT |
2276 | char *end_op; |
2277 | ||
2278 | r = parse_register (op_string, &end_op); | |
2279 | if (r == NULL) | |
2280 | return 0; | |
2281 | /* Check for a segment override by searching for ':' after a | |
2282 | segment register. */ | |
2283 | op_string = end_op; | |
2284 | if (is_space_char (*op_string)) | |
2285 | ++op_string; | |
de1d28b6 | 2286 | if (*op_string) |
355afbcd | 2287 | { |
de1d28b6 | 2288 | if (r->reg_type & (SReg2 | SReg3)) |
355afbcd | 2289 | { |
de1d28b6 RH |
2290 | switch (r->reg_num) |
2291 | { | |
2292 | case 0: | |
2293 | i.seg[i.mem_operands] = &es; | |
2294 | break; | |
2295 | case 1: | |
2296 | i.seg[i.mem_operands] = &cs; | |
2297 | break; | |
2298 | case 2: | |
2299 | i.seg[i.mem_operands] = &ss; | |
2300 | break; | |
2301 | case 3: | |
2302 | i.seg[i.mem_operands] = &ds; | |
2303 | break; | |
2304 | case 4: | |
2305 | i.seg[i.mem_operands] = &fs; | |
2306 | break; | |
2307 | case 5: | |
2308 | i.seg[i.mem_operands] = &gs; | |
2309 | break; | |
2310 | } | |
4edc93e9 | 2311 | |
de1d28b6 | 2312 | /* Skip the ':' and whitespace. */ |
4edc93e9 ILT |
2313 | ++op_string; |
2314 | if (is_space_char (*op_string)) | |
2315 | ++op_string; | |
de1d28b6 RH |
2316 | |
2317 | /* Pretend given string starts here. */ | |
2318 | operand_string = op_string; | |
2319 | if (!is_digit_char (*op_string) | |
2320 | && !is_identifier_char (*op_string) | |
2321 | && *op_string != '(' | |
2322 | && *op_string != ABSOLUTE_PREFIX) | |
2323 | { | |
2324 | as_bad (_("bad memory operand `%s'"), op_string); | |
2325 | return 0; | |
2326 | } | |
2327 | /* Handle case of %es:*foo. */ | |
2328 | if (*op_string == ABSOLUTE_PREFIX) | |
2329 | { | |
2330 | ++op_string; | |
2331 | if (is_space_char (*op_string)) | |
2332 | ++op_string; | |
2333 | i.types[this_operand] |= JumpAbsolute; | |
2334 | } | |
2335 | goto do_memory_reference; | |
2336 | } | |
2337 | else | |
2338 | { | |
2339 | as_bad (_("bad segment prefix `%c%s'"), | |
2340 | REGISTER_PREFIX, r->reg_name); | |
2341 | return 0; | |
355afbcd | 2342 | } |
355afbcd | 2343 | } |
ec1e6bb8 | 2344 | i.types[this_operand] |= r->reg_type & ~BaseIndex; |
355afbcd KR |
2345 | i.regs[this_operand] = r; |
2346 | i.reg_operands++; | |
2347 | } | |
2348 | else if (*op_string == IMMEDIATE_PREFIX) | |
2349 | { /* ... or an immediate */ | |
2350 | char *save_input_line_pointer; | |
49864cfa | 2351 | segT exp_seg = 0; |
355afbcd KR |
2352 | expressionS *exp; |
2353 | ||
2354 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
2355 | { | |
48401fcf | 2356 | as_bad (_("only 1 or 2 immediate operands are allowed")); |
355afbcd KR |
2357 | return 0; |
2358 | } | |
542e1629 | 2359 | |
355afbcd KR |
2360 | exp = &im_expressions[i.imm_operands++]; |
2361 | i.imms[this_operand] = exp; | |
4edc93e9 ILT |
2362 | |
2363 | ++op_string; | |
2364 | if (is_space_char (*op_string)) | |
2365 | ++op_string; | |
2366 | ||
355afbcd | 2367 | save_input_line_pointer = input_line_pointer; |
4edc93e9 | 2368 | input_line_pointer = op_string; |
355afbcd | 2369 | exp_seg = expression (exp); |
388fa5c6 | 2370 | if (*input_line_pointer != '\0') |
dddc8a82 ILT |
2371 | { |
2372 | /* This should be as_bad, but some versions of gcc, up to | |
2373 | about 2.8 and egcs 1.01, generate a bogus @GOTOFF(%ebx) | |
2374 | in certain cases. Oddly, the code in question turns out | |
2375 | to work correctly anyhow, so we make this just a warning | |
2376 | until those versions of gcc are obsolete. */ | |
48401fcf | 2377 | as_warn (_("unrecognized characters `%s' in expression"), |
dddc8a82 ILT |
2378 | input_line_pointer); |
2379 | } | |
355afbcd KR |
2380 | input_line_pointer = save_input_line_pointer; |
2381 | ||
7b23213f | 2382 | if (exp->X_op == O_absent) |
355afbcd | 2383 | { |
49864cfa | 2384 | /* missing or bad expr becomes absolute 0 */ |
48401fcf | 2385 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
355afbcd | 2386 | operand_string); |
5ac34ac3 | 2387 | exp->X_op = O_constant; |
355afbcd KR |
2388 | exp->X_add_number = 0; |
2389 | exp->X_add_symbol = (symbolS *) 0; | |
5ac34ac3 | 2390 | exp->X_op_symbol = (symbolS *) 0; |
355afbcd | 2391 | i.types[this_operand] |= Imm; |
49864cfa | 2392 | } |
7b23213f | 2393 | else if (exp->X_op == O_constant) |
49864cfa | 2394 | { |
ad660eb1 | 2395 | i.types[this_operand] |= |
0351b70c | 2396 | smallest_imm_type ((long) exp->X_add_number); |
61c49d66 ILT |
2397 | |
2398 | /* If a suffix is given, this operand may be shortened. */ | |
2399 | switch (i.suffix) | |
2400 | { | |
2401 | case WORD_OPCODE_SUFFIX: | |
2402 | i.types[this_operand] |= Imm16; | |
2403 | break; | |
2404 | case BYTE_OPCODE_SUFFIX: | |
2405 | i.types[this_operand] |= Imm16 | Imm8 | Imm8S; | |
2406 | break; | |
2407 | } | |
49864cfa | 2408 | } |
7b23213f | 2409 | #ifdef OBJ_AOUT |
49864cfa KR |
2410 | else if (exp_seg != text_section |
2411 | && exp_seg != data_section | |
2412 | && exp_seg != bss_section | |
2413 | && exp_seg != undefined_section | |
2414 | #ifdef BFD_ASSEMBLER | |
2415 | && ! bfd_is_com_section (exp_seg) | |
2416 | #endif | |
2417 | ) | |
2418 | { | |
355afbcd | 2419 | seg_unimplemented: |
61c49d66 | 2420 | as_bad (_("Unimplemented segment type %d in operand"), exp_seg); |
355afbcd KR |
2421 | return 0; |
2422 | } | |
49864cfa KR |
2423 | #endif |
2424 | else | |
2425 | { | |
5819d632 ILT |
2426 | /* This is an address. The size of the address will be |
2427 | determined later, depending on destination register, | |
2428 | suffix, or the default for the section. We exclude | |
2429 | Imm8S here so that `push $foo' and other instructions | |
2430 | with an Imm8S form will use Imm16 or Imm32. */ | |
2431 | i.types[this_operand] |= (Imm8 | Imm16 | Imm32); | |
355afbcd KR |
2432 | } |
2433 | } | |
2434 | else if (is_digit_char (*op_string) || is_identifier_char (*op_string) | |
2435 | || *op_string == '(') | |
2436 | { | |
2437 | /* This is a memory reference of some sort. */ | |
0351b70c | 2438 | char *end_of_operand_string; |
355afbcd | 2439 | register char *base_string; |
ec1e6bb8 | 2440 | int found_base_index_form; |
355afbcd | 2441 | |
0351b70c ILT |
2442 | /* Start and end of displacement string expression (if found). */ |
2443 | char *displacement_string_start; | |
2444 | char *displacement_string_end; | |
2445 | ||
355afbcd | 2446 | do_memory_reference: |
4498e3d6 ILT |
2447 | if ((i.mem_operands == 1 |
2448 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
2449 | || i.mem_operands == 2) | |
355afbcd | 2450 | { |
48401fcf | 2451 | as_bad (_("too many memory references for `%s'"), |
4498e3d6 | 2452 | current_templates->start->name); |
355afbcd KR |
2453 | return 0; |
2454 | } | |
355afbcd | 2455 | |
49864cfa KR |
2456 | /* Check for base index form. We detect the base index form by |
2457 | looking for an ')' at the end of the operand, searching | |
2458 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
4edc93e9 | 2459 | after the '('. */ |
355afbcd | 2460 | found_base_index_form = 0; |
0351b70c | 2461 | end_of_operand_string = op_string + strlen (op_string); |
4edc93e9 ILT |
2462 | |
2463 | --end_of_operand_string; | |
2464 | if (is_space_char (*end_of_operand_string)) | |
2465 | --end_of_operand_string; | |
2466 | ||
2467 | base_string = end_of_operand_string; | |
355afbcd KR |
2468 | if (*base_string == ')') |
2469 | { | |
0b476c53 | 2470 | unsigned int parens_balanced = 1; |
49864cfa KR |
2471 | /* We've already checked that the number of left & right ()'s are |
2472 | equal, so this loop will not be infinite. */ | |
355afbcd KR |
2473 | do |
2474 | { | |
2475 | base_string--; | |
2476 | if (*base_string == ')') | |
0b476c53 | 2477 | parens_balanced++; |
355afbcd | 2478 | if (*base_string == '(') |
0b476c53 | 2479 | parens_balanced--; |
355afbcd | 2480 | } |
0b476c53 | 2481 | while (parens_balanced); |
4edc93e9 ILT |
2482 | |
2483 | /* If there is a displacement set-up for it to be parsed later. */ | |
2484 | displacement_string_start = op_string; | |
2485 | displacement_string_end = base_string; | |
2486 | ||
2487 | /* Skip past '(' and whitespace. */ | |
2488 | ++base_string; | |
2489 | if (is_space_char (*base_string)) | |
2490 | ++base_string; | |
2491 | ||
355afbcd KR |
2492 | if (*base_string == REGISTER_PREFIX || *base_string == ',') |
2493 | found_base_index_form = 1; | |
2494 | } | |
2495 | ||
2496 | /* If we can't parse a base index register expression, we've found | |
49864cfa KR |
2497 | a pure displacement expression. We set up displacement_string_start |
2498 | and displacement_string_end for the code below. */ | |
355afbcd KR |
2499 | if (!found_base_index_form) |
2500 | { | |
2501 | displacement_string_start = op_string; | |
4edc93e9 | 2502 | displacement_string_end = end_of_operand_string + 1; |
355afbcd KR |
2503 | } |
2504 | else | |
2505 | { | |
355afbcd KR |
2506 | i.types[this_operand] |= BaseIndex; |
2507 | ||
355afbcd KR |
2508 | /* Find base register (if any). */ |
2509 | if (*base_string != ',') | |
2510 | { | |
4edc93e9 ILT |
2511 | char *end_op; |
2512 | ||
2513 | /* Trim off the closing ')' so that parse_register won't | |
2514 | see it. */ | |
2515 | END_STRING_AND_SAVE (end_of_operand_string); | |
2516 | i.base_reg = parse_register (base_string, &end_op); | |
4edc93e9 | 2517 | RESTORE_END_STRING (end_of_operand_string); |
61c49d66 ILT |
2518 | |
2519 | if (i.base_reg == NULL) | |
2520 | return 0; | |
2521 | ||
4edc93e9 ILT |
2522 | base_string = end_op; |
2523 | if (is_space_char (*base_string)) | |
2524 | ++base_string; | |
355afbcd KR |
2525 | } |
2526 | ||
4edc93e9 ILT |
2527 | /* There may be an index reg or scale factor here. */ |
2528 | if (*base_string == ',') | |
355afbcd | 2529 | { |
4edc93e9 ILT |
2530 | ++base_string; |
2531 | if (is_space_char (*base_string)) | |
2532 | ++base_string; | |
355afbcd | 2533 | |
4edc93e9 | 2534 | if (*base_string == REGISTER_PREFIX) |
355afbcd | 2535 | { |
4edc93e9 ILT |
2536 | char *end_op; |
2537 | ||
2538 | END_STRING_AND_SAVE (end_of_operand_string); | |
2539 | i.index_reg = parse_register (base_string, &end_op); | |
2540 | RESTORE_END_STRING (end_of_operand_string); | |
2541 | ||
2542 | if (i.index_reg == NULL) | |
2543 | return 0; | |
2544 | ||
2545 | base_string = end_op; | |
2546 | if (is_space_char (*base_string)) | |
2547 | ++base_string; | |
2548 | if (*base_string == ',') | |
2549 | { | |
2550 | ++base_string; | |
2551 | if (is_space_char (*base_string)) | |
2552 | ++base_string; | |
2553 | } | |
2554 | else if (*base_string != ')') | |
2555 | { | |
2556 | as_bad (_("expecting `,' or `)' after index register in `%s'"), | |
2557 | operand_string); | |
2558 | return 0; | |
2559 | } | |
a39116f1 | 2560 | } |
355afbcd | 2561 | |
4edc93e9 ILT |
2562 | /* Check for scale factor. */ |
2563 | if (isdigit ((unsigned char) *base_string)) | |
ec1e6bb8 | 2564 | { |
4edc93e9 ILT |
2565 | if (isdigit ((unsigned char) base_string[1])) |
2566 | goto bad_scale; /* must be 1 digit scale */ | |
2567 | switch (*base_string) | |
2568 | { | |
2569 | case '1': | |
2570 | i.log2_scale_factor = 0; | |
2571 | break; | |
2572 | case '2': | |
2573 | i.log2_scale_factor = 1; | |
2574 | break; | |
2575 | case '4': | |
2576 | i.log2_scale_factor = 2; | |
2577 | break; | |
2578 | case '8': | |
2579 | i.log2_scale_factor = 3; | |
2580 | break; | |
2581 | default: | |
2582 | bad_scale: | |
2583 | as_bad (_("expecting scale factor of 1, 2, 4 or 8; got `%s'"), | |
2584 | base_string); | |
2585 | return 0; | |
2586 | } | |
2587 | ||
2588 | ++base_string; | |
2589 | if (is_space_char (*base_string)) | |
2590 | ++base_string; | |
2591 | if (*base_string != ')') | |
2592 | { | |
2593 | as_bad (_("expecting `)' after scale factor in `%s'"), | |
2594 | operand_string); | |
2595 | return 0; | |
2596 | } | |
2597 | if (i.log2_scale_factor != 0 && ! i.index_reg) | |
2598 | { | |
2599 | as_warn (_("scale factor of %d without an index register"), | |
2600 | 1 << i.log2_scale_factor); | |
ec1e6bb8 | 2601 | #if SCALE1_WHEN_NO_INDEX |
4edc93e9 | 2602 | i.log2_scale_factor = 0; |
ec1e6bb8 | 2603 | #endif |
4edc93e9 | 2604 | } |
ec1e6bb8 | 2605 | } |
4edc93e9 | 2606 | else if (!i.index_reg) |
355afbcd | 2607 | { |
48401fcf | 2608 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
4edc93e9 | 2609 | *base_string); |
355afbcd | 2610 | return 0; |
a39116f1 | 2611 | } |
355afbcd | 2612 | } |
4edc93e9 ILT |
2613 | else if (*base_string != ')') |
2614 | { | |
2615 | as_bad (_("expecting `,' or `)' after base register in `%s'"), | |
2616 | operand_string); | |
2617 | return 0; | |
2618 | } | |
355afbcd KR |
2619 | } |
2620 | ||
2621 | /* If there's an expression begining the operand, parse it, | |
4edc93e9 ILT |
2622 | assuming displacement_string_start and |
2623 | displacement_string_end are meaningful. */ | |
2624 | if (displacement_string_start != displacement_string_end) | |
355afbcd KR |
2625 | { |
2626 | register expressionS *exp; | |
49864cfa | 2627 | segT exp_seg = 0; |
355afbcd | 2628 | char *save_input_line_pointer; |
0351b70c ILT |
2629 | int bigdisp = Disp32; |
2630 | ||
2631 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) | |
2632 | bigdisp = Disp16; | |
2633 | i.types[this_operand] |= bigdisp; | |
aa56747a | 2634 | |
355afbcd KR |
2635 | exp = &disp_expressions[i.disp_operands]; |
2636 | i.disps[this_operand] = exp; | |
f0b37b4a | 2637 | i.disp_reloc[this_operand] = NO_RELOC; |
355afbcd KR |
2638 | i.disp_operands++; |
2639 | save_input_line_pointer = input_line_pointer; | |
2640 | input_line_pointer = displacement_string_start; | |
2641 | END_STRING_AND_SAVE (displacement_string_end); | |
0351b70c ILT |
2642 | #ifndef GCC_ASM_O_HACK |
2643 | #define GCC_ASM_O_HACK 0 | |
2644 | #endif | |
2645 | #if GCC_ASM_O_HACK | |
2646 | END_STRING_AND_SAVE (displacement_string_end + 1); | |
2647 | if ((i.types[this_operand] & BaseIndex) != 0 | |
2648 | && displacement_string_end[-1] == '+') | |
2649 | { | |
2650 | /* This hack is to avoid a warning when using the "o" | |
2651 | constraint within gcc asm statements. | |
2652 | For instance: | |
2653 | ||
2654 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
2655 | __asm__ __volatile__ ( \ | |
2656 | "movw %w2,%0\n\t" \ | |
2657 | "movw %w1,2+%0\n\t" \ | |
2658 | "rorl $16,%1\n\t" \ | |
2659 | "movb %b1,4+%0\n\t" \ | |
2660 | "movb %4,5+%0\n\t" \ | |
2661 | "movb $0,6+%0\n\t" \ | |
2662 | "movb %h1,7+%0\n\t" \ | |
2663 | "rorl $16,%1" \ | |
2664 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
2665 | ||
2666 | This works great except that the output assembler ends | |
2667 | up looking a bit weird if it turns out that there is | |
2668 | no offset. You end up producing code that looks like: | |
2669 | ||
2670 | #APP | |
2671 | movw $235,(%eax) | |
2672 | movw %dx,2+(%eax) | |
2673 | rorl $16,%edx | |
2674 | movb %dl,4+(%eax) | |
2675 | movb $137,5+(%eax) | |
2676 | movb $0,6+(%eax) | |
2677 | movb %dh,7+(%eax) | |
2678 | rorl $16,%edx | |
2679 | #NO_APP | |
2680 | ||
2681 | So here we provide the missing zero. | |
2682 | */ | |
a52f90a4 | 2683 | |
0351b70c ILT |
2684 | *displacement_string_end = '0'; |
2685 | } | |
2686 | #endif | |
30355216 | 2687 | #ifndef LEX_AT |
f0b37b4a KR |
2688 | { |
2689 | /* | |
2690 | * We can have operands of the form | |
2691 | * <symbol>@GOTOFF+<nnn> | |
2692 | * Take the easy way out here and copy everything | |
2693 | * into a temporary buffer... | |
2694 | */ | |
2695 | register char *cp; | |
a52f90a4 ILT |
2696 | |
2697 | cp = strchr (input_line_pointer, '@'); | |
2698 | if (cp != NULL) | |
2699 | { | |
2700 | char *tmpbuf; | |
2701 | ||
2702 | if (GOT_symbol == NULL) | |
2703 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
2704 | ||
2705 | tmpbuf = (char *) alloca ((cp - input_line_pointer) + 20); | |
2706 | ||
2707 | if (strncmp (cp + 1, "PLT", 3) == 0) | |
2708 | { | |
2709 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
2710 | *cp = '\0'; | |
2711 | strcpy (tmpbuf, input_line_pointer); | |
2712 | strcat (tmpbuf, cp + 1 + 3); | |
2713 | *cp = '@'; | |
2714 | } | |
2715 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) | |
2716 | { | |
2717 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; | |
2718 | *cp = '\0'; | |
2719 | strcpy (tmpbuf, input_line_pointer); | |
2720 | strcat (tmpbuf, cp + 1 + 6); | |
2721 | *cp = '@'; | |
2722 | } | |
2723 | else if (strncmp (cp + 1, "GOT", 3) == 0) | |
2724 | { | |
2725 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; | |
2726 | *cp = '\0'; | |
2727 | strcpy (tmpbuf, input_line_pointer); | |
2728 | strcat (tmpbuf, cp + 1 + 3); | |
2729 | *cp = '@'; | |
2730 | } | |
2731 | else | |
48401fcf | 2732 | as_bad (_("Bad reloc specifier `%s' in expression"), cp + 1); |
a52f90a4 | 2733 | |
0351b70c ILT |
2734 | /* GOT relocations are not supported in 16 bit mode */ |
2735 | if (flag_16bit_code) | |
2736 | as_bad (_("GOT relocations not supported in 16 bit mode")); | |
2737 | ||
a52f90a4 ILT |
2738 | input_line_pointer = tmpbuf; |
2739 | } | |
f0b37b4a | 2740 | } |
30355216 | 2741 | #endif |
a52f90a4 | 2742 | |
355afbcd | 2743 | exp_seg = expression (exp); |
f0b37b4a KR |
2744 | |
2745 | #ifdef BFD_ASSEMBLER | |
2746 | /* We do this to make sure that the section symbol is in | |
2747 | the symbol table. We will ultimately change the relocation | |
2748 | to be relative to the beginning of the section */ | |
c54c7aac KR |
2749 | if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF) |
2750 | { | |
2751 | if (S_IS_LOCAL(exp->X_add_symbol) | |
2752 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) | |
2753 | section_symbol(exp->X_add_symbol->bsym->section); | |
2754 | assert (exp->X_op == O_symbol); | |
2755 | exp->X_op = O_subtract; | |
2756 | exp->X_op_symbol = GOT_symbol; | |
2757 | i.disp_reloc[this_operand] = BFD_RELOC_32; | |
2758 | } | |
f0b37b4a KR |
2759 | #endif |
2760 | ||
355afbcd | 2761 | if (*input_line_pointer) |
48401fcf TT |
2762 | as_bad (_("Ignoring junk `%s' after expression"), |
2763 | input_line_pointer); | |
0351b70c ILT |
2764 | #if GCC_ASM_O_HACK |
2765 | RESTORE_END_STRING (displacement_string_end + 1); | |
2766 | #endif | |
355afbcd KR |
2767 | RESTORE_END_STRING (displacement_string_end); |
2768 | input_line_pointer = save_input_line_pointer; | |
73a8be66 ILT |
2769 | |
2770 | #if 0 /* this is handled in expr. */ | |
7b23213f | 2771 | if (exp->X_op == O_absent) |
355afbcd | 2772 | { |
355afbcd | 2773 | /* missing expr becomes absolute 0 */ |
48401fcf | 2774 | as_bad (_("missing or invalid displacement `%s' taken as 0"), |
355afbcd | 2775 | operand_string); |
5ac34ac3 | 2776 | exp->X_op = O_constant; |
355afbcd KR |
2777 | exp->X_add_number = 0; |
2778 | exp->X_add_symbol = (symbolS *) 0; | |
5ac34ac3 | 2779 | exp->X_op_symbol = (symbolS *) 0; |
0351b70c | 2780 | i.types[this_operand] |= Disp8; |
49864cfa | 2781 | } |
aa56747a ILT |
2782 | else |
2783 | #endif | |
2784 | if (exp->X_op == O_constant) | |
49864cfa | 2785 | { |
0351b70c ILT |
2786 | if (fits_in_signed_byte (exp->X_add_number)) |
2787 | i.types[this_operand] |= Disp8; | |
49864cfa | 2788 | } |
0351b70c ILT |
2789 | #ifdef OBJ_AOUT |
2790 | else if (exp_seg != text_section | |
2791 | && exp_seg != data_section | |
2792 | && exp_seg != bss_section | |
2793 | && exp_seg != undefined_section) | |
49864cfa | 2794 | { |
355afbcd KR |
2795 | goto seg_unimplemented; |
2796 | } | |
0351b70c | 2797 | #endif |
355afbcd KR |
2798 | } |
2799 | ||
ec1e6bb8 | 2800 | /* Special case for (%dx) while doing input/output op. */ |
73a8be66 ILT |
2801 | if (i.base_reg |
2802 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) | |
2803 | && i.index_reg == 0 | |
2804 | && i.log2_scale_factor == 0 | |
2805 | && i.seg[i.mem_operands] == 0 | |
2806 | && (i.types[this_operand] & Disp) == 0) | |
355afbcd | 2807 | { |
ec1e6bb8 | 2808 | i.types[this_operand] = InOutPortReg; |
49864cfa KR |
2809 | return 1; |
2810 | } | |
73a8be66 | 2811 | /* Make sure the memory operand we've been dealt is valid. */ |
0351b70c | 2812 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) |
355afbcd | 2813 | { |
0351b70c ILT |
2814 | if ((i.base_reg |
2815 | && ((i.base_reg->reg_type & (Reg16|BaseIndex)) | |
2816 | != (Reg16|BaseIndex))) | |
2817 | || (i.index_reg | |
2818 | && (((i.index_reg->reg_type & (Reg16|BaseIndex)) | |
2819 | != (Reg16|BaseIndex)) | |
2820 | || ! (i.base_reg | |
2821 | && i.base_reg->reg_num < 6 | |
2822 | && i.index_reg->reg_num >= 6 | |
2823 | && i.log2_scale_factor == 0)))) | |
2824 | { | |
2825 | as_bad (_("`%s' is not a valid %s bit base/index expression"), | |
2826 | operand_string, "16"); | |
2827 | return 0; | |
2828 | } | |
2829 | } | |
2830 | else | |
2831 | { | |
2832 | if ((i.base_reg | |
2833 | && (i.base_reg->reg_type & Reg32) == 0) | |
2834 | || (i.index_reg | |
2835 | && ((i.index_reg->reg_type & (Reg32|BaseIndex)) | |
2836 | != (Reg32|BaseIndex)))) | |
2837 | { | |
2838 | as_bad (_("`%s' is not a valid %s bit base/index expression"), | |
2839 | operand_string, "32"); | |
2840 | return 0; | |
2841 | } | |
fecd2382 | 2842 | } |
ec1e6bb8 | 2843 | i.mem_operands++; |
355afbcd KR |
2844 | } |
2845 | else | |
2846 | { /* it's not a memory operand; argh! */ | |
8081c2be | 2847 | as_bad (_("invalid char %s begining operand %d `%s'"), |
aa56747a ILT |
2848 | output_invalid (*op_string), |
2849 | this_operand + 1, | |
355afbcd KR |
2850 | op_string); |
2851 | return 0; | |
2852 | } | |
2853 | return 1; /* normal return */ | |
fecd2382 RP |
2854 | } |
2855 | \f | |
2856 | /* | |
2857 | * md_estimate_size_before_relax() | |
2858 | * | |
2859 | * Called just before relax(). | |
2860 | * Any symbol that is now undefined will not become defined. | |
2861 | * Return the correct fr_subtype in the frag. | |
2862 | * Return the initial "guess for fr_var" to caller. | |
2863 | * The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
2864 | * Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
2865 | * Although it may not be explicit in the frag, pretend fr_var starts with a | |
2866 | * 0 value. | |
2867 | */ | |
2868 | int | |
355afbcd KR |
2869 | md_estimate_size_before_relax (fragP, segment) |
2870 | register fragS *fragP; | |
2871 | register segT segment; | |
fecd2382 | 2872 | { |
355afbcd KR |
2873 | register unsigned char *opcode; |
2874 | register int old_fr_fix; | |
2875 | ||
2876 | old_fr_fix = fragP->fr_fix; | |
2877 | opcode = (unsigned char *) fragP->fr_opcode; | |
73a8be66 ILT |
2878 | /* We've already got fragP->fr_subtype right; all we have to do is |
2879 | check for un-relaxable symbols. */ | |
355afbcd KR |
2880 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) |
2881 | { | |
2882 | /* symbol is undefined in this segment */ | |
0351b70c ILT |
2883 | int code16 = fragP->fr_subtype & CODE16; |
2884 | int size = code16 ? 2 : 4; | |
2885 | int pcrel_reloc = code16 ? BFD_RELOC_16_PCREL : BFD_RELOC_32_PCREL; | |
2886 | ||
355afbcd KR |
2887 | switch (opcode[0]) |
2888 | { | |
2889 | case JUMP_PC_RELATIVE: /* make jmp (0xeb) a dword displacement jump */ | |
2890 | opcode[0] = 0xe9; /* dword disp jmp */ | |
0351b70c ILT |
2891 | fragP->fr_fix += size; |
2892 | fix_new (fragP, old_fr_fix, size, | |
73a8be66 | 2893 | fragP->fr_symbol, |
f0b37b4a KR |
2894 | fragP->fr_offset, 1, |
2895 | (GOT_symbol && /* Not quite right - we should switch on | |
2896 | presence of @PLT, but I cannot see how | |
2897 | to get to that from here. We should have | |
2898 | done this in md_assemble to really | |
2899 | get it right all of the time, but I | |
2900 | think it does not matter that much, as | |
2901 | this will be right most of the time. ERY*/ | |
0351b70c ILT |
2902 | S_GET_SEGMENT(fragP->fr_symbol) == undefined_section) |
2903 | ? BFD_RELOC_386_PLT32 : pcrel_reloc); | |
355afbcd KR |
2904 | break; |
2905 | ||
2906 | default: | |
2907 | /* This changes the byte-displacement jump 0x7N --> | |
a39116f1 | 2908 | the dword-displacement jump 0x0f8N */ |
355afbcd KR |
2909 | opcode[1] = opcode[0] + 0x10; |
2910 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; /* two-byte escape */ | |
0351b70c ILT |
2911 | fragP->fr_fix += 1 + size; /* we've added an opcode byte */ |
2912 | fix_new (fragP, old_fr_fix + 1, size, | |
355afbcd | 2913 | fragP->fr_symbol, |
0351b70c | 2914 | fragP->fr_offset, 1, |
f0b37b4a KR |
2915 | (GOT_symbol && /* Not quite right - we should switch on |
2916 | presence of @PLT, but I cannot see how | |
2917 | to get to that from here. ERY */ | |
0351b70c ILT |
2918 | S_GET_SEGMENT(fragP->fr_symbol) == undefined_section) |
2919 | ? BFD_RELOC_386_PLT32 : pcrel_reloc); | |
355afbcd | 2920 | break; |
a39116f1 | 2921 | } |
355afbcd KR |
2922 | frag_wane (fragP); |
2923 | } | |
2924 | return (fragP->fr_var + fragP->fr_fix - old_fr_fix); | |
fecd2382 RP |
2925 | } /* md_estimate_size_before_relax() */ |
2926 | \f | |
2927 | /* | |
2928 | * md_convert_frag(); | |
2929 | * | |
2930 | * Called after relax() is finished. | |
2931 | * In: Address of frag. | |
2932 | * fr_type == rs_machine_dependent. | |
2933 | * fr_subtype is what the address relaxed to. | |
2934 | * | |
2935 | * Out: Any fixSs and constants are set up. | |
2936 | * Caller will turn frag into a ".space 0". | |
2937 | */ | |
49864cfa | 2938 | #ifndef BFD_ASSEMBLER |
fecd2382 | 2939 | void |
3ea36b53 | 2940 | md_convert_frag (headers, sec, fragP) |
355afbcd | 2941 | object_headers *headers; |
3ea36b53 | 2942 | segT sec; |
355afbcd | 2943 | register fragS *fragP; |
49864cfa KR |
2944 | #else |
2945 | void | |
2946 | md_convert_frag (abfd, sec, fragP) | |
2947 | bfd *abfd; | |
2948 | segT sec; | |
2949 | register fragS *fragP; | |
2950 | #endif | |
fecd2382 | 2951 | { |
355afbcd KR |
2952 | register unsigned char *opcode; |
2953 | unsigned char *where_to_put_displacement = NULL; | |
2954 | unsigned int target_address; | |
2955 | unsigned int opcode_address; | |
2956 | unsigned int extension = 0; | |
2957 | int displacement_from_opcode_start; | |
2958 | ||
2959 | opcode = (unsigned char *) fragP->fr_opcode; | |
2960 | ||
2961 | /* Address we want to reach in file space. */ | |
2962 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
7b23213f KR |
2963 | #ifdef BFD_ASSEMBLER /* not needed otherwise? */ |
2964 | target_address += fragP->fr_symbol->sy_frag->fr_address; | |
2965 | #endif | |
355afbcd KR |
2966 | |
2967 | /* Address opcode resides at in file space. */ | |
2968 | opcode_address = fragP->fr_address + fragP->fr_fix; | |
2969 | ||
2970 | /* Displacement from opcode start to fill into instruction. */ | |
2971 | displacement_from_opcode_start = target_address - opcode_address; | |
2972 | ||
2973 | switch (fragP->fr_subtype) | |
2974 | { | |
0351b70c ILT |
2975 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL): |
2976 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL16): | |
2977 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL): | |
2978 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL16): | |
355afbcd KR |
2979 | /* don't have to change opcode */ |
2980 | extension = 1; /* 1 opcode + 1 displacement */ | |
2981 | where_to_put_displacement = &opcode[1]; | |
2982 | break; | |
2983 | ||
0351b70c ILT |
2984 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
2985 | extension = 5; /* 2 opcode + 4 displacement */ | |
2986 | opcode[1] = opcode[0] + 0x10; | |
2987 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
2988 | where_to_put_displacement = &opcode[2]; | |
355afbcd KR |
2989 | break; |
2990 | ||
0351b70c ILT |
2991 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): |
2992 | extension = 4; /* 1 opcode + 4 displacement */ | |
2993 | opcode[0] = 0xe9; | |
2994 | where_to_put_displacement = &opcode[1]; | |
355afbcd KR |
2995 | break; |
2996 | ||
0351b70c ILT |
2997 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
2998 | extension = 3; /* 2 opcode + 2 displacement */ | |
355afbcd KR |
2999 | opcode[1] = opcode[0] + 0x10; |
3000 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
355afbcd KR |
3001 | where_to_put_displacement = &opcode[2]; |
3002 | break; | |
3003 | ||
0351b70c ILT |
3004 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
3005 | extension = 2; /* 1 opcode + 2 displacement */ | |
355afbcd | 3006 | opcode[0] = 0xe9; |
355afbcd KR |
3007 | where_to_put_displacement = &opcode[1]; |
3008 | break; | |
3009 | ||
3010 | default: | |
3011 | BAD_CASE (fragP->fr_subtype); | |
3012 | break; | |
3013 | } | |
3014 | /* now put displacement after opcode */ | |
3015 | md_number_to_chars ((char *) where_to_put_displacement, | |
ad660eb1 | 3016 | (valueT) (displacement_from_opcode_start - extension), |
355afbcd KR |
3017 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
3018 | fragP->fr_fix += extension; | |
fecd2382 | 3019 | } |
fecd2382 | 3020 | \f |
355afbcd | 3021 | |
fecd2382 | 3022 | int md_short_jump_size = 2; /* size of byte displacement jmp */ |
355afbcd | 3023 | int md_long_jump_size = 5; /* size of dword displacement jmp */ |
49864cfa | 3024 | const int md_reloc_size = 8; /* Size of relocation record */ |
fecd2382 | 3025 | |
355afbcd KR |
3026 | void |
3027 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
3028 | char *ptr; | |
025b0302 | 3029 | addressT from_addr, to_addr; |
355afbcd KR |
3030 | fragS *frag; |
3031 | symbolS *to_symbol; | |
fecd2382 | 3032 | { |
355afbcd KR |
3033 | long offset; |
3034 | ||
3035 | offset = to_addr - (from_addr + 2); | |
ad660eb1 ILT |
3036 | md_number_to_chars (ptr, (valueT) 0xeb, 1); /* opcode for byte-disp jump */ |
3037 | md_number_to_chars (ptr + 1, (valueT) offset, 1); | |
fecd2382 RP |
3038 | } |
3039 | ||
355afbcd KR |
3040 | void |
3041 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
3042 | char *ptr; | |
025b0302 | 3043 | addressT from_addr, to_addr; |
355afbcd KR |
3044 | fragS *frag; |
3045 | symbolS *to_symbol; | |
fecd2382 | 3046 | { |
355afbcd KR |
3047 | long offset; |
3048 | ||
ade614d5 | 3049 | if (flag_do_long_jump) |
355afbcd KR |
3050 | { |
3051 | offset = to_addr - S_GET_VALUE (to_symbol); | |
ad660eb1 ILT |
3052 | md_number_to_chars (ptr, (valueT) 0xe9, 1);/* opcode for long jmp */ |
3053 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
355afbcd | 3054 | fix_new (frag, (ptr + 1) - frag->fr_literal, 4, |
7b23213f | 3055 | to_symbol, (offsetT) 0, 0, BFD_RELOC_32); |
355afbcd KR |
3056 | } |
3057 | else | |
3058 | { | |
3059 | offset = to_addr - (from_addr + 5); | |
ad660eb1 ILT |
3060 | md_number_to_chars (ptr, (valueT) 0xe9, 1); |
3061 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
355afbcd | 3062 | } |
fecd2382 RP |
3063 | } |
3064 | \f | |
fecd2382 | 3065 | /* Apply a fixup (fixS) to segment data, once it has been determined |
355afbcd KR |
3066 | by our caller that we have all the info we need to fix it up. |
3067 | ||
fecd2382 RP |
3068 | On the 386, immediates, displacements, and data pointers are all in |
3069 | the same (little-endian) format, so we don't need to care about which | |
3070 | we are handling. */ | |
3071 | ||
3ea36b53 ILT |
3072 | int |
3073 | md_apply_fix3 (fixP, valp, seg) | |
3074 | fixS *fixP; /* The fix we're to put in. */ | |
3075 | valueT *valp; /* Pointer to the value of the bits. */ | |
3076 | segT seg; /* Segment fix is from. */ | |
fecd2382 | 3077 | { |
355afbcd | 3078 | register char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
3ea36b53 | 3079 | valueT value = *valp; |
355afbcd | 3080 | |
388fa5c6 ILT |
3081 | if (fixP->fx_r_type == BFD_RELOC_32 && fixP->fx_pcrel) |
3082 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
3083 | ||
f3d817d8 | 3084 | #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) |
7b23213f KR |
3085 | /* |
3086 | * This is a hack. There should be a better way to | |
3087 | * handle this. | |
3088 | */ | |
3089 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL && fixP->fx_addsy) | |
3090 | { | |
0b476c53 | 3091 | #ifndef OBJ_AOUT |
76fb6d2f ILT |
3092 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
3093 | || OUTPUT_FLAVOR == bfd_target_coff_flavour) | |
590c50d8 | 3094 | value += fixP->fx_where + fixP->fx_frag->fr_address; |
0b476c53 | 3095 | #endif |
590c50d8 ILT |
3096 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3097 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
3098 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg | |
ec1e6bb8 ILT |
3099 | || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0) |
3100 | && ! S_IS_EXTERNAL (fixP->fx_addsy) | |
3101 | && ! S_IS_WEAK (fixP->fx_addsy) | |
3102 | && S_IS_DEFINED (fixP->fx_addsy) | |
3103 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
f3d817d8 DM |
3104 | { |
3105 | /* Yes, we add the values in twice. This is because | |
3106 | bfd_perform_relocation subtracts them out again. I think | |
3107 | bfd_perform_relocation is broken, but I don't dare change | |
3108 | it. FIXME. */ | |
3109 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
3110 | } | |
76fb6d2f ILT |
3111 | #endif |
3112 | #if defined (OBJ_COFF) && defined (TE_PE) | |
3113 | /* For some reason, the PE format does not store a section | |
3114 | address offset for a PC relative symbol. */ | |
3115 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
3116 | value += md_pcrel_from (fixP); | |
7b23213f | 3117 | #endif |
355afbcd | 3118 | } |
f0b37b4a KR |
3119 | |
3120 | /* Fix a few things - the dynamic linker expects certain values here, | |
3121 | and we must not dissappoint it. */ | |
590c50d8 ILT |
3122 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3123 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
3124 | && fixP->fx_addsy) | |
0351b70c | 3125 | switch (fixP->fx_r_type) { |
f0b37b4a KR |
3126 | case BFD_RELOC_386_PLT32: |
3127 | /* Make the jump instruction point to the address of the operand. At | |
3128 | runtime we merely add the offset to the actual PLT entry. */ | |
3129 | value = 0xfffffffc; | |
3130 | break; | |
3131 | case BFD_RELOC_386_GOTPC: | |
3132 | /* | |
3133 | * This is tough to explain. We end up with this one if we have | |
3134 | * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal | |
3135 | * here is to obtain the absolute address of the GOT, and it is strongly | |
3136 | * preferable from a performance point of view to avoid using a runtime | |
3137 | * relocation for this. The actual sequence of instructions often look | |
3138 | * something like: | |
3139 | * | |
3140 | * call .L66 | |
3141 | * .L66: | |
3142 | * popl %ebx | |
3143 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
3144 | * | |
3145 | * The call and pop essentially return the absolute address of | |
3146 | * the label .L66 and store it in %ebx. The linker itself will | |
3147 | * ultimately change the first operand of the addl so that %ebx points to | |
3148 | * the GOT, but to keep things simple, the .o file must have this operand | |
3149 | * set so that it generates not the absolute address of .L66, but the | |
3150 | * absolute address of itself. This allows the linker itself simply | |
3151 | * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be | |
3152 | * added in, and the addend of the relocation is stored in the operand | |
3153 | * field for the instruction itself. | |
3154 | * | |
3155 | * Our job here is to fix the operand so that it would add the correct | |
3156 | * offset so that %ebx would point to itself. The thing that is tricky is | |
3157 | * that .-.L66 will point to the beginning of the instruction, so we need | |
3158 | * to further modify the operand so that it will point to itself. | |
3159 | * There are other cases where you have something like: | |
3160 | * | |
3161 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
3162 | * | |
3163 | * and here no correction would be required. Internally in the assembler | |
3164 | * we treat operands of this form as not being pcrel since the '.' is | |
3165 | * explicitly mentioned, and I wonder whether it would simplify matters | |
3166 | * to do it this way. Who knows. In earlier versions of the PIC patches, | |
3167 | * the pcrel_adjust field was used to store the correction, but since the | |
3168 | * expression is not pcrel, I felt it would be confusing to do it this way. | |
3169 | */ | |
c54c7aac | 3170 | value -= 1; |
f0b37b4a KR |
3171 | break; |
3172 | case BFD_RELOC_386_GOT32: | |
3173 | value = 0; /* Fully resolved at runtime. No addend. */ | |
c54c7aac | 3174 | break; |
f0b37b4a | 3175 | case BFD_RELOC_386_GOTOFF: |
c54c7aac KR |
3176 | break; |
3177 | ||
a1624e3f RH |
3178 | case BFD_RELOC_VTABLE_INHERIT: |
3179 | case BFD_RELOC_VTABLE_ENTRY: | |
3180 | fixP->fx_done = 0; | |
3181 | return 1; | |
3182 | ||
f0b37b4a KR |
3183 | default: |
3184 | break; | |
3185 | } | |
3186 | #endif | |
3187 | ||
f3d817d8 DM |
3188 | #endif |
3189 | md_number_to_chars (p, value, fixP->fx_size); | |
fecd2382 | 3190 | |
49864cfa KR |
3191 | return 1; |
3192 | } | |
49864cfa | 3193 | |
ad660eb1 ILT |
3194 | #if 0 |
3195 | /* This is never used. */ | |
355afbcd KR |
3196 | long /* Knows about the byte order in a word. */ |
3197 | md_chars_to_number (con, nbytes) | |
3198 | unsigned char con[]; /* Low order byte 1st. */ | |
3199 | int nbytes; /* Number of bytes in the input. */ | |
fecd2382 | 3200 | { |
355afbcd KR |
3201 | long retval; |
3202 | for (retval = 0, con += nbytes - 1; nbytes--; con--) | |
3203 | { | |
3204 | retval <<= BITS_PER_CHAR; | |
3205 | retval |= *con; | |
3206 | } | |
3207 | return retval; | |
fecd2382 | 3208 | } |
ad660eb1 | 3209 | #endif /* 0 */ |
fecd2382 | 3210 | \f |
355afbcd | 3211 | |
fecd2382 RP |
3212 | #define MAX_LITTLENUMS 6 |
3213 | ||
3214 | /* Turn the string pointed to by litP into a floating point constant of type | |
3215 | type, and emit the appropriate bytes. The number of LITTLENUMS emitted | |
3c8df4ba | 3216 | is stored in *sizeP . An error message is returned, or NULL on OK. */ |
fecd2382 | 3217 | char * |
355afbcd KR |
3218 | md_atof (type, litP, sizeP) |
3219 | char type; | |
3220 | char *litP; | |
3221 | int *sizeP; | |
fecd2382 | 3222 | { |
355afbcd KR |
3223 | int prec; |
3224 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
3225 | LITTLENUM_TYPE *wordP; | |
3226 | char *t; | |
3227 | ||
3228 | switch (type) | |
3229 | { | |
3230 | case 'f': | |
3231 | case 'F': | |
3232 | prec = 2; | |
3233 | break; | |
3234 | ||
3235 | case 'd': | |
3236 | case 'D': | |
3237 | prec = 4; | |
3238 | break; | |
3239 | ||
3240 | case 'x': | |
3241 | case 'X': | |
3242 | prec = 5; | |
3243 | break; | |
3244 | ||
3245 | default: | |
3246 | *sizeP = 0; | |
48401fcf | 3247 | return _("Bad call to md_atof ()"); |
355afbcd KR |
3248 | } |
3249 | t = atof_ieee (input_line_pointer, type, words); | |
3250 | if (t) | |
3251 | input_line_pointer = t; | |
3252 | ||
3253 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
3c8df4ba KR |
3254 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with |
3255 | the bigendian 386. */ | |
355afbcd KR |
3256 | for (wordP = words + prec - 1; prec--;) |
3257 | { | |
ad660eb1 | 3258 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); |
355afbcd KR |
3259 | litP += sizeof (LITTLENUM_TYPE); |
3260 | } | |
49864cfa | 3261 | return 0; |
fecd2382 RP |
3262 | } |
3263 | \f | |
3264 | char output_invalid_buf[8]; | |
3265 | ||
355afbcd KR |
3266 | static char * |
3267 | output_invalid (c) | |
3268 | char c; | |
fecd2382 | 3269 | { |
355afbcd KR |
3270 | if (isprint (c)) |
3271 | sprintf (output_invalid_buf, "'%c'", c); | |
3272 | else | |
3273 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
3274 | return output_invalid_buf; | |
fecd2382 RP |
3275 | } |
3276 | ||
4edc93e9 ILT |
3277 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
3278 | ||
0351b70c | 3279 | static const reg_entry * |
4edc93e9 ILT |
3280 | parse_register (reg_string, end_op) |
3281 | char *reg_string; | |
3282 | char **end_op; | |
fecd2382 | 3283 | { |
4edc93e9 | 3284 | register char *s = reg_string; |
355afbcd | 3285 | register char *p; |
4edc93e9 ILT |
3286 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
3287 | const reg_entry *r; | |
3288 | ||
3289 | /* Skip REGISTER_PREFIX and possible whitespace. */ | |
3290 | ++s; | |
3291 | if (is_space_char (*s)) | |
3292 | ++s; | |
355afbcd | 3293 | |
0351b70c ILT |
3294 | p = reg_name_given; |
3295 | while ((*p++ = register_chars[(unsigned char) *s++]) != '\0') | |
355afbcd | 3296 | { |
355afbcd | 3297 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) |
4edc93e9 ILT |
3298 | { |
3299 | *p = '\0'; | |
3300 | as_bad (_("bad register name `%s'"), reg_name_given); | |
3301 | return (const reg_entry *) NULL; | |
3302 | } | |
355afbcd | 3303 | } |
4edc93e9 ILT |
3304 | |
3305 | *end_op = s - 1; | |
3306 | ||
3307 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
3308 | ||
3309 | if (r == NULL) | |
3310 | { | |
3311 | as_bad (_("bad register name `%s'"), reg_name_given); | |
3312 | return (const reg_entry *) NULL; | |
3313 | } | |
3314 | ||
3315 | return r; | |
fecd2382 | 3316 | } |
f3d817d8 | 3317 | \f |
ade614d5 | 3318 | #ifdef OBJ_ELF |
3ea36b53 | 3319 | CONST char *md_shortopts = "kmVQ:"; |
ade614d5 KR |
3320 | #else |
3321 | CONST char *md_shortopts = "m"; | |
3322 | #endif | |
f3d817d8 DM |
3323 | struct option md_longopts[] = { |
3324 | {NULL, no_argument, NULL, 0} | |
3325 | }; | |
0351b70c | 3326 | size_t md_longopts_size = sizeof (md_longopts); |
fecd2382 | 3327 | |
f3d817d8 DM |
3328 | int |
3329 | md_parse_option (c, arg) | |
3330 | int c; | |
3331 | char *arg; | |
3332 | { | |
ade614d5 KR |
3333 | switch (c) |
3334 | { | |
3335 | case 'm': | |
3336 | flag_do_long_jump = 1; | |
3337 | break; | |
3338 | ||
590c50d8 | 3339 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3ea36b53 ILT |
3340 | /* -k: Ignore for FreeBSD compatibility. */ |
3341 | case 'k': | |
3342 | break; | |
3343 | ||
ade614d5 KR |
3344 | /* -V: SVR4 argument to print version ID. */ |
3345 | case 'V': | |
3346 | print_version_id (); | |
3347 | break; | |
3348 | ||
3349 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
3350 | should be emitted or not. FIXME: Not implemented. */ | |
3351 | case 'Q': | |
3352 | break; | |
3353 | #endif | |
3354 | ||
3355 | default: | |
3356 | return 0; | |
3357 | } | |
3358 | return 1; | |
f3d817d8 | 3359 | } |
fecd2382 | 3360 | |
f3d817d8 DM |
3361 | void |
3362 | md_show_usage (stream) | |
3363 | FILE *stream; | |
3364 | { | |
48401fcf TT |
3365 | fprintf (stream, _("\ |
3366 | -m do long jump\n")); | |
f3d817d8 | 3367 | } |
fecd2382 | 3368 | |
590c50d8 ILT |
3369 | #ifdef BFD_ASSEMBLER |
3370 | #ifdef OBJ_MAYBE_ELF | |
3371 | #ifdef OBJ_MAYBE_COFF | |
3372 | ||
3373 | /* Pick the target format to use. */ | |
3374 | ||
3375 | const char * | |
3376 | i386_target_format () | |
3377 | { | |
3378 | switch (OUTPUT_FLAVOR) | |
3379 | { | |
3380 | case bfd_target_coff_flavour: | |
3381 | return "coff-i386"; | |
3382 | case bfd_target_elf_flavour: | |
3383 | return "elf32-i386"; | |
3384 | default: | |
3385 | abort (); | |
3386 | return NULL; | |
3387 | } | |
3388 | } | |
3389 | ||
3390 | #endif /* OBJ_MAYBE_COFF */ | |
3391 | #endif /* OBJ_MAYBE_ELF */ | |
3392 | #endif /* BFD_ASSEMBLER */ | |
3393 | \f | |
fecd2382 RP |
3394 | /* ARGSUSED */ |
3395 | symbolS * | |
355afbcd KR |
3396 | md_undefined_symbol (name) |
3397 | char *name; | |
fecd2382 | 3398 | { |
f0b37b4a KR |
3399 | if (*name == '_' && *(name+1) == 'G' |
3400 | && strcmp(name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
3401 | { | |
0351b70c | 3402 | if (!GOT_symbol) |
f0b37b4a | 3403 | { |
0351b70c | 3404 | if (symbol_find (name)) |
aa56747a | 3405 | as_bad (_("GOT already in symbol table")); |
0351b70c | 3406 | GOT_symbol = symbol_new (name, undefined_section, |
f0b37b4a KR |
3407 | (valueT) 0, &zero_address_frag); |
3408 | }; | |
3409 | return GOT_symbol; | |
3410 | } | |
355afbcd | 3411 | return 0; |
fecd2382 RP |
3412 | } |
3413 | ||
fecd2382 | 3414 | /* Round up a section size to the appropriate boundary. */ |
3c8df4ba | 3415 | valueT |
355afbcd KR |
3416 | md_section_align (segment, size) |
3417 | segT segment; | |
3c8df4ba | 3418 | valueT size; |
fecd2382 | 3419 | { |
91951af6 ILT |
3420 | #ifdef OBJ_AOUT |
3421 | #ifdef BFD_ASSEMBLER | |
3422 | /* For a.out, force the section size to be aligned. If we don't do | |
3423 | this, BFD will align it for us, but it will not write out the | |
3424 | final bytes of the section. This may be a bug in BFD, but it is | |
3425 | easier to fix it here since that is how the other a.out targets | |
3426 | work. */ | |
3427 | int align; | |
3428 | ||
3429 | align = bfd_get_section_alignment (stdoutput, segment); | |
3430 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
3431 | #endif | |
3432 | #endif | |
3433 | ||
3434 | return size; | |
fecd2382 RP |
3435 | } |
3436 | ||
4edc93e9 ILT |
3437 | /* On the i386, PC-relative offsets are relative to the start of the |
3438 | next instruction. That is, the address of the offset, plus its | |
3439 | size, since the offset is always the last part of the insn. */ | |
3440 | ||
fecd2382 | 3441 | long |
355afbcd KR |
3442 | md_pcrel_from (fixP) |
3443 | fixS *fixP; | |
fecd2382 | 3444 | { |
355afbcd | 3445 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
fecd2382 RP |
3446 | } |
3447 | ||
49864cfa | 3448 | #ifndef I386COFF |
542e1629 | 3449 | |
49864cfa | 3450 | static void |
ad660eb1 ILT |
3451 | s_bss (ignore) |
3452 | int ignore; | |
542e1629 | 3453 | { |
49864cfa | 3454 | register int temp; |
542e1629 | 3455 | |
49864cfa | 3456 | temp = get_absolute_expression (); |
49864cfa | 3457 | subseg_set (bss_section, (subsegT) temp); |
49864cfa KR |
3458 | demand_empty_rest_of_line (); |
3459 | } | |
542e1629 | 3460 | |
49864cfa | 3461 | #endif |
355afbcd | 3462 | |
542e1629 | 3463 | |
49864cfa | 3464 | #ifdef BFD_ASSEMBLER |
c54c7aac KR |
3465 | |
3466 | void | |
3467 | i386_validate_fix (fixp) | |
3468 | fixS *fixp; | |
3469 | { | |
3470 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
3471 | { | |
3472 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
3473 | fixp->fx_subsy = 0; | |
3474 | } | |
3475 | } | |
3476 | ||
f0b37b4a KR |
3477 | #define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) |
3478 | #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break | |
542e1629 | 3479 | |
49864cfa KR |
3480 | arelent * |
3481 | tc_gen_reloc (section, fixp) | |
3482 | asection *section; | |
3483 | fixS *fixp; | |
542e1629 | 3484 | { |
ad660eb1 | 3485 | arelent *rel; |
49864cfa | 3486 | bfd_reloc_code_real_type code; |
542e1629 | 3487 | |
73a8be66 | 3488 | switch (fixp->fx_r_type) |
49864cfa | 3489 | { |
f0b37b4a KR |
3490 | case BFD_RELOC_386_PLT32: |
3491 | case BFD_RELOC_386_GOT32: | |
3492 | case BFD_RELOC_386_GOTOFF: | |
3493 | case BFD_RELOC_386_GOTPC: | |
a52f90a4 | 3494 | case BFD_RELOC_RVA: |
a1624e3f RH |
3495 | case BFD_RELOC_VTABLE_ENTRY: |
3496 | case BFD_RELOC_VTABLE_INHERIT: | |
f0b37b4a KR |
3497 | code = fixp->fx_r_type; |
3498 | break; | |
3499 | default: | |
3500 | switch (F (fixp->fx_size, fixp->fx_pcrel)) | |
3501 | { | |
f0b37b4a KR |
3502 | MAP (1, 0, BFD_RELOC_8); |
3503 | MAP (2, 0, BFD_RELOC_16); | |
f0b37b4a | 3504 | MAP (4, 0, BFD_RELOC_32); |
f0b37b4a KR |
3505 | MAP (1, 1, BFD_RELOC_8_PCREL); |
3506 | MAP (2, 1, BFD_RELOC_16_PCREL); | |
f0b37b4a KR |
3507 | MAP (4, 1, BFD_RELOC_32_PCREL); |
3508 | default: | |
48401fcf TT |
3509 | if (fixp->fx_pcrel) |
3510 | as_bad (_("Can not do %d byte pc-relative relocation"), | |
3511 | fixp->fx_size); | |
3512 | else | |
3513 | as_bad (_("Can not do %d byte relocation"), fixp->fx_size); | |
73a8be66 ILT |
3514 | code = BFD_RELOC_32; |
3515 | break; | |
f0b37b4a | 3516 | } |
73a8be66 | 3517 | break; |
49864cfa | 3518 | } |
3c8df4ba KR |
3519 | #undef MAP |
3520 | #undef F | |
542e1629 | 3521 | |
f0b37b4a KR |
3522 | if (code == BFD_RELOC_32 |
3523 | && GOT_symbol | |
3524 | && fixp->fx_addsy == GOT_symbol) | |
3525 | code = BFD_RELOC_386_GOTPC; | |
3526 | ||
590c50d8 | 3527 | rel = (arelent *) xmalloc (sizeof (arelent)); |
ad660eb1 | 3528 | rel->sym_ptr_ptr = &fixp->fx_addsy->bsym; |
a1624e3f | 3529 | |
ad660eb1 | 3530 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; |
a1624e3f RH |
3531 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the |
3532 | vtable entry to be used in the relocation's section offset. */ | |
3533 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3534 | rel->address = fixp->fx_offset; | |
3535 | ||
49864cfa | 3536 | if (fixp->fx_pcrel) |
ad660eb1 | 3537 | rel->addend = fixp->fx_addnumber; |
49864cfa | 3538 | else |
ad660eb1 | 3539 | rel->addend = 0; |
355afbcd | 3540 | |
ad660eb1 | 3541 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
e592f0e6 | 3542 | if (rel->howto == NULL) |
ad660eb1 | 3543 | { |
e592f0e6 | 3544 | as_bad_where (fixp->fx_file, fixp->fx_line, |
48401fcf | 3545 | _("Cannot represent relocation type %s"), |
e592f0e6 ILT |
3546 | bfd_get_reloc_code_name (code)); |
3547 | /* Set howto to a garbage value so that we can keep going. */ | |
3548 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
3549 | assert (rel->howto != NULL); | |
ad660eb1 | 3550 | } |
49864cfa | 3551 | |
ad660eb1 | 3552 | return rel; |
49864cfa KR |
3553 | } |
3554 | ||
3555 | #else /* ! BFD_ASSEMBLER */ | |
3556 | ||
3557 | #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) | |
3558 | void | |
3559 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) | |
3560 | char *where; | |
3561 | fixS *fixP; | |
3562 | relax_addressT segment_address_in_file; | |
4b77b129 | 3563 | { |
49864cfa KR |
3564 | /* |
3565 | * In: length of relocation (or of address) in chars: 1, 2 or 4. | |
3566 | * Out: GNU LD relocation length code: 0, 1, or 2. | |
3567 | */ | |
4b77b129 | 3568 | |
3c8df4ba | 3569 | static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; |
49864cfa KR |
3570 | long r_symbolnum; |
3571 | ||
3572 | know (fixP->fx_addsy != NULL); | |
3573 | ||
3574 | md_number_to_chars (where, | |
ad660eb1 ILT |
3575 | (valueT) (fixP->fx_frag->fr_address |
3576 | + fixP->fx_where - segment_address_in_file), | |
49864cfa KR |
3577 | 4); |
3578 | ||
3579 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) | |
3580 | ? S_GET_TYPE (fixP->fx_addsy) | |
3581 | : fixP->fx_addsy->sy_number); | |
3582 | ||
3583 | where[6] = (r_symbolnum >> 16) & 0x0ff; | |
3584 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
3585 | where[4] = r_symbolnum & 0x0ff; | |
3586 | where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) | |
3587 | | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) | |
3588 | | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); | |
4b77b129 | 3589 | } |
355afbcd | 3590 | |
49864cfa | 3591 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
4b77b129 | 3592 | |
49864cfa | 3593 | #if defined (I386COFF) |
4b77b129 | 3594 | |
355afbcd KR |
3595 | short |
3596 | tc_coff_fix2rtype (fixP) | |
3597 | fixS *fixP; | |
4b77b129 | 3598 | { |
3ea36b53 ILT |
3599 | if (fixP->fx_r_type == R_IMAGEBASE) |
3600 | return R_IMAGEBASE; | |
3601 | ||
355afbcd KR |
3602 | return (fixP->fx_pcrel ? |
3603 | (fixP->fx_size == 1 ? R_PCRBYTE : | |
3604 | fixP->fx_size == 2 ? R_PCRWORD : | |
3605 | R_PCRLONG) : | |
3606 | (fixP->fx_size == 1 ? R_RELBYTE : | |
3607 | fixP->fx_size == 2 ? R_RELWORD : | |
3608 | R_DIR32)); | |
4b77b129 ILT |
3609 | } |
3610 | ||
49864cfa KR |
3611 | int |
3612 | tc_coff_sizemachdep (frag) | |
3613 | fragS *frag; | |
3614 | { | |
3615 | if (frag->fr_next) | |
3616 | return (frag->fr_next->fr_address - frag->fr_address); | |
3617 | else | |
3618 | return 0; | |
3619 | } | |
3620 | ||
3621 | #endif /* I386COFF */ | |
3622 | ||
3623 | #endif /* BFD_ASSEMBLER? */ | |
3ea36b53 | 3624 | \f |
fecd2382 | 3625 | /* end of tc-i386.c */ |