Commit | Line | Data |
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252b5132 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
f7e42eb4 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
ae6063d4 | 3 | 2000, 2001, 2002, 2003 |
47926f60 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
20 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
21 | 02111-1307, USA. */ | |
22 | ||
47926f60 KH |
23 | /* Intel 80386 machine specific gas. |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 25 | x86_64 support by Jan Hubicka (jh@suse.cz) |
47926f60 KH |
26 | Bugs & suggestions are completely welcome. This is free software. |
27 | Please help us make it better. */ | |
252b5132 | 28 | |
252b5132 | 29 | #include "as.h" |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | #include "subsegs.h" |
316e2c05 | 32 | #include "dwarf2dbg.h" |
54cfded0 | 33 | #include "dw2gencfi.h" |
252b5132 RH |
34 | #include "opcode/i386.h" |
35 | ||
252b5132 RH |
36 | #ifndef REGISTER_WARNINGS |
37 | #define REGISTER_WARNINGS 1 | |
38 | #endif | |
39 | ||
c3332e24 | 40 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 41 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
42 | #endif |
43 | ||
252b5132 RH |
44 | #ifndef SCALE1_WHEN_NO_INDEX |
45 | /* Specifying a scale factor besides 1 when there is no index is | |
46 | futile. eg. `mov (%ebx,2),%al' does exactly the same as | |
47 | `mov (%ebx),%al'. To slavishly follow what the programmer | |
48 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ | |
49 | #define SCALE1_WHEN_NO_INDEX 1 | |
50 | #endif | |
51 | ||
29b0f896 AM |
52 | #ifdef BFD_ASSEMBLER |
53 | #define RELOC_ENUM enum bfd_reloc_code_real | |
54 | #else | |
55 | #define RELOC_ENUM int | |
246fcdee | 56 | #endif |
29b0f896 AM |
57 | |
58 | #ifndef DEFAULT_ARCH | |
59 | #define DEFAULT_ARCH "i386" | |
246fcdee | 60 | #endif |
252b5132 | 61 | |
edde18a5 AM |
62 | #ifndef INLINE |
63 | #if __GNUC__ >= 2 | |
64 | #define INLINE __inline__ | |
65 | #else | |
66 | #define INLINE | |
67 | #endif | |
68 | #endif | |
69 | ||
29b0f896 AM |
70 | static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int)); |
71 | static INLINE int fits_in_signed_byte PARAMS ((offsetT)); | |
72 | static INLINE int fits_in_unsigned_byte PARAMS ((offsetT)); | |
73 | static INLINE int fits_in_unsigned_word PARAMS ((offsetT)); | |
74 | static INLINE int fits_in_signed_word PARAMS ((offsetT)); | |
75 | static INLINE int fits_in_unsigned_long PARAMS ((offsetT)); | |
76 | static INLINE int fits_in_signed_long PARAMS ((offsetT)); | |
847f7ad4 AM |
77 | static int smallest_imm_type PARAMS ((offsetT)); |
78 | static offsetT offset_in_range PARAMS ((offsetT, int)); | |
252b5132 | 79 | static int add_prefix PARAMS ((unsigned int)); |
3e73aa7c | 80 | static void set_code_flag PARAMS ((int)); |
47926f60 | 81 | static void set_16bit_gcc_code_flag PARAMS ((int)); |
252b5132 | 82 | static void set_intel_syntax PARAMS ((int)); |
e413e4e9 | 83 | static void set_cpu_arch PARAMS ((int)); |
29b0f896 AM |
84 | static char *output_invalid PARAMS ((int c)); |
85 | static int i386_operand PARAMS ((char *operand_string)); | |
86 | static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); | |
87 | static const reg_entry *parse_register PARAMS ((char *reg_string, | |
88 | char **end_op)); | |
89 | static char *parse_insn PARAMS ((char *, char *)); | |
90 | static char *parse_operands PARAMS ((char *, const char *)); | |
91 | static void swap_operands PARAMS ((void)); | |
92 | static void optimize_imm PARAMS ((void)); | |
93 | static void optimize_disp PARAMS ((void)); | |
94 | static int match_template PARAMS ((void)); | |
95 | static int check_string PARAMS ((void)); | |
96 | static int process_suffix PARAMS ((void)); | |
97 | static int check_byte_reg PARAMS ((void)); | |
98 | static int check_long_reg PARAMS ((void)); | |
99 | static int check_qword_reg PARAMS ((void)); | |
100 | static int check_word_reg PARAMS ((void)); | |
101 | static int finalize_imm PARAMS ((void)); | |
102 | static int process_operands PARAMS ((void)); | |
103 | static const seg_entry *build_modrm_byte PARAMS ((void)); | |
104 | static void output_insn PARAMS ((void)); | |
105 | static void output_branch PARAMS ((void)); | |
106 | static void output_jump PARAMS ((void)); | |
107 | static void output_interseg_jump PARAMS ((void)); | |
2bbd9c25 JJ |
108 | static void output_imm PARAMS ((fragS *insn_start_frag, |
109 | offsetT insn_start_off)); | |
110 | static void output_disp PARAMS ((fragS *insn_start_frag, | |
111 | offsetT insn_start_off)); | |
29b0f896 AM |
112 | #ifndef I386COFF |
113 | static void s_bss PARAMS ((int)); | |
252b5132 RH |
114 | #endif |
115 | ||
a847613f | 116 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 117 | |
252b5132 | 118 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 119 | i386_insn. */ |
252b5132 | 120 | |
520dc8e8 AM |
121 | union i386_op |
122 | { | |
123 | expressionS *disps; | |
124 | expressionS *imms; | |
125 | const reg_entry *regs; | |
126 | }; | |
127 | ||
252b5132 RH |
128 | struct _i386_insn |
129 | { | |
47926f60 | 130 | /* TM holds the template for the insn were currently assembling. */ |
252b5132 RH |
131 | template tm; |
132 | ||
133 | /* SUFFIX holds the instruction mnemonic suffix if given. | |
134 | (e.g. 'l' for 'movl') */ | |
135 | char suffix; | |
136 | ||
47926f60 | 137 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
138 | unsigned int operands; |
139 | ||
140 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
141 | of given register, displacement, memory operands and immediate | |
47926f60 | 142 | operands. */ |
252b5132 RH |
143 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
144 | ||
145 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 146 | use OP[i] for the corresponding operand. */ |
252b5132 RH |
147 | unsigned int types[MAX_OPERANDS]; |
148 | ||
520dc8e8 AM |
149 | /* Displacement expression, immediate expression, or register for each |
150 | operand. */ | |
151 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 152 | |
3e73aa7c JH |
153 | /* Flags for operands. */ |
154 | unsigned int flags[MAX_OPERANDS]; | |
155 | #define Operand_PCrel 1 | |
156 | ||
252b5132 | 157 | /* Relocation type for operand */ |
f3c180ae | 158 | RELOC_ENUM reloc[MAX_OPERANDS]; |
252b5132 | 159 | |
252b5132 RH |
160 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
161 | the base index byte below. */ | |
162 | const reg_entry *base_reg; | |
163 | const reg_entry *index_reg; | |
164 | unsigned int log2_scale_factor; | |
165 | ||
166 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 167 | explicit segment overrides are given. */ |
ce8a8b2f | 168 | const seg_entry *seg[2]; |
252b5132 RH |
169 | |
170 | /* PREFIX holds all the given prefix opcodes (usually null). | |
171 | PREFIXES is the number of prefix opcodes. */ | |
172 | unsigned int prefixes; | |
173 | unsigned char prefix[MAX_PREFIXES]; | |
174 | ||
175 | /* RM and SIB are the modrm byte and the sib byte where the | |
176 | addressing modes of this insn are encoded. */ | |
177 | ||
178 | modrm_byte rm; | |
3e73aa7c | 179 | rex_byte rex; |
252b5132 RH |
180 | sib_byte sib; |
181 | }; | |
182 | ||
183 | typedef struct _i386_insn i386_insn; | |
184 | ||
185 | /* List of chars besides those in app.c:symbol_chars that can start an | |
186 | operand. Used to prevent the scrubber eating vital white-space. */ | |
187 | #ifdef LEX_AT | |
200dbde8 | 188 | const char extra_symbol_chars[] = "*%-(@["; |
252b5132 | 189 | #else |
200dbde8 | 190 | const char extra_symbol_chars[] = "*%-(["; |
252b5132 RH |
191 | #endif |
192 | ||
29b0f896 AM |
193 | #if (defined (TE_I386AIX) \ |
194 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
195 | && !defined (TE_LINUX) \ | |
196 | && !defined (TE_FreeBSD) \ | |
197 | && !defined (TE_NetBSD))) | |
252b5132 | 198 | /* This array holds the chars that always start a comment. If the |
ce8a8b2f | 199 | pre-processor is disabled, these aren't very useful. */ |
252b5132 RH |
200 | const char comment_chars[] = "#/"; |
201 | #define PREFIX_SEPARATOR '\\' | |
252b5132 RH |
202 | |
203 | /* This array holds the chars that only start a comment at the beginning of | |
204 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
205 | .line and .file directives will appear in the pre-processed output. |
206 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 207 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
208 | #NO_APP at the beginning of its output. |
209 | Also note that comments started like this one will always work if | |
252b5132 | 210 | '/' isn't otherwise defined. */ |
0d9f6d04 | 211 | const char line_comment_chars[] = "#"; |
29b0f896 | 212 | |
252b5132 | 213 | #else |
29b0f896 AM |
214 | /* Putting '/' here makes it impossible to use the divide operator. |
215 | However, we need it for compatibility with SVR4 systems. */ | |
216 | const char comment_chars[] = "#"; | |
217 | #define PREFIX_SEPARATOR '/' | |
218 | ||
0d9f6d04 | 219 | const char line_comment_chars[] = "/#"; |
252b5132 RH |
220 | #endif |
221 | ||
63a0b638 | 222 | const char line_separator_chars[] = ";"; |
252b5132 | 223 | |
ce8a8b2f AM |
224 | /* Chars that can be used to separate mant from exp in floating point |
225 | nums. */ | |
252b5132 RH |
226 | const char EXP_CHARS[] = "eE"; |
227 | ||
ce8a8b2f AM |
228 | /* Chars that mean this number is a floating point constant |
229 | As in 0f12.456 | |
230 | or 0d1.2345e12. */ | |
252b5132 RH |
231 | const char FLT_CHARS[] = "fFdDxX"; |
232 | ||
ce8a8b2f | 233 | /* Tables for lexical analysis. */ |
252b5132 RH |
234 | static char mnemonic_chars[256]; |
235 | static char register_chars[256]; | |
236 | static char operand_chars[256]; | |
237 | static char identifier_chars[256]; | |
238 | static char digit_chars[256]; | |
239 | ||
ce8a8b2f | 240 | /* Lexical macros. */ |
252b5132 RH |
241 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
242 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
243 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
244 | #define is_space_char(x) ((x) == ' ') | |
245 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
246 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
247 | ||
ce8a8b2f | 248 | /* All non-digit non-letter charcters that may occur in an operand. */ |
252b5132 RH |
249 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
250 | ||
251 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
252 | effect this we maintain a stack of saved characters that we've smashed | |
253 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 254 | assembler instruction). */ |
252b5132 | 255 | static char save_stack[32]; |
ce8a8b2f | 256 | static char *save_stack_p; |
252b5132 RH |
257 | #define END_STRING_AND_SAVE(s) \ |
258 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
259 | #define RESTORE_END_STRING(s) \ | |
260 | do { *(s) = *--save_stack_p; } while (0) | |
261 | ||
47926f60 | 262 | /* The instruction we're assembling. */ |
252b5132 RH |
263 | static i386_insn i; |
264 | ||
265 | /* Possible templates for current insn. */ | |
266 | static const templates *current_templates; | |
267 | ||
47926f60 | 268 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ |
252b5132 RH |
269 | static expressionS disp_expressions[2], im_expressions[2]; |
270 | ||
47926f60 KH |
271 | /* Current operand we are working on. */ |
272 | static int this_operand; | |
252b5132 | 273 | |
3e73aa7c JH |
274 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
275 | these. */ | |
276 | ||
277 | enum flag_code { | |
278 | CODE_32BIT, | |
279 | CODE_16BIT, | |
280 | CODE_64BIT }; | |
f3c180ae | 281 | #define NUM_FLAG_CODE ((int) CODE_64BIT + 1) |
3e73aa7c JH |
282 | |
283 | static enum flag_code flag_code; | |
284 | static int use_rela_relocations = 0; | |
285 | ||
286 | /* The names used to print error messages. */ | |
b77a7acd | 287 | static const char *flag_code_names[] = |
3e73aa7c JH |
288 | { |
289 | "32", | |
290 | "16", | |
291 | "64" | |
292 | }; | |
252b5132 | 293 | |
47926f60 KH |
294 | /* 1 for intel syntax, |
295 | 0 if att syntax. */ | |
296 | static int intel_syntax = 0; | |
252b5132 | 297 | |
47926f60 KH |
298 | /* 1 if register prefix % not required. */ |
299 | static int allow_naked_reg = 0; | |
252b5132 | 300 | |
47926f60 KH |
301 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
302 | leave, push, and pop instructions so that gcc has the same stack | |
303 | frame as in 32 bit mode. */ | |
304 | static char stackop_size = '\0'; | |
eecb386c | 305 | |
12b55ccc L |
306 | /* Non-zero to optimize code alignment. */ |
307 | int optimize_align_code = 1; | |
308 | ||
47926f60 KH |
309 | /* Non-zero to quieten some warnings. */ |
310 | static int quiet_warnings = 0; | |
a38cf1db | 311 | |
47926f60 KH |
312 | /* CPU name. */ |
313 | static const char *cpu_arch_name = NULL; | |
a38cf1db | 314 | |
47926f60 | 315 | /* CPU feature flags. */ |
29b0f896 | 316 | static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64; |
a38cf1db | 317 | |
fddf5b5b AM |
318 | /* If set, conditional jumps are not automatically promoted to handle |
319 | larger than a byte offset. */ | |
320 | static unsigned int no_cond_jump_promotion = 0; | |
321 | ||
29b0f896 AM |
322 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
323 | symbolS *GOT_symbol; | |
324 | ||
a4447b93 RH |
325 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
326 | unsigned int x86_dwarf2_return_column; | |
327 | ||
328 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
329 | int x86_cie_data_alignment; | |
330 | ||
252b5132 | 331 | /* Interface to relax_segment. |
fddf5b5b AM |
332 | There are 3 major relax states for 386 jump insns because the |
333 | different types of jumps add different sizes to frags when we're | |
334 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 335 | |
47926f60 | 336 | /* Types. */ |
93c2a809 AM |
337 | #define UNCOND_JUMP 0 |
338 | #define COND_JUMP 1 | |
339 | #define COND_JUMP86 2 | |
fddf5b5b | 340 | |
47926f60 | 341 | /* Sizes. */ |
252b5132 RH |
342 | #define CODE16 1 |
343 | #define SMALL 0 | |
29b0f896 | 344 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 345 | #define BIG 2 |
29b0f896 | 346 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
347 | |
348 | #ifndef INLINE | |
349 | #ifdef __GNUC__ | |
350 | #define INLINE __inline__ | |
351 | #else | |
352 | #define INLINE | |
353 | #endif | |
354 | #endif | |
355 | ||
fddf5b5b AM |
356 | #define ENCODE_RELAX_STATE(type, size) \ |
357 | ((relax_substateT) (((type) << 2) | (size))) | |
358 | #define TYPE_FROM_RELAX_STATE(s) \ | |
359 | ((s) >> 2) | |
360 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
361 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
362 | |
363 | /* This table is used by relax_frag to promote short jumps to long | |
364 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
365 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
366 | don't allow a short jump in a 32 bit code segment to be promoted to | |
367 | a 16 bit offset jump because it's slower (requires data size | |
368 | prefix), and doesn't work, unless the destination is in the bottom | |
369 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
370 | ||
371 | const relax_typeS md_relax_table[] = | |
372 | { | |
24eab124 AM |
373 | /* The fields are: |
374 | 1) most positive reach of this state, | |
375 | 2) most negative reach of this state, | |
93c2a809 | 376 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 377 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 378 | |
fddf5b5b | 379 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
380 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
381 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
382 | /* dword jmp adds 4 bytes to frag: | |
383 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 384 | {0, 0, 4, 0}, |
93c2a809 AM |
385 | /* word jmp adds 2 byte2 to frag: |
386 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
387 | {0, 0, 2, 0}, |
388 | ||
93c2a809 AM |
389 | /* COND_JUMP states. */ |
390 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
391 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
392 | /* dword conditionals adds 5 bytes to frag: | |
393 | 1 extra opcode byte, 4 displacement bytes. */ | |
394 | {0, 0, 5, 0}, | |
fddf5b5b | 395 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
396 | 1 extra opcode byte, 2 displacement bytes. */ |
397 | {0, 0, 3, 0}, | |
398 | ||
399 | /* COND_JUMP86 states. */ | |
400 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
401 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
402 | /* dword conditionals adds 5 bytes to frag: | |
403 | 1 extra opcode byte, 4 displacement bytes. */ | |
404 | {0, 0, 5, 0}, | |
405 | /* word conditionals add 4 bytes to frag: | |
406 | 1 displacement byte and a 3 byte long branch insn. */ | |
407 | {0, 0, 4, 0} | |
252b5132 RH |
408 | }; |
409 | ||
e413e4e9 AM |
410 | static const arch_entry cpu_arch[] = { |
411 | {"i8086", Cpu086 }, | |
412 | {"i186", Cpu086|Cpu186 }, | |
413 | {"i286", Cpu086|Cpu186|Cpu286 }, | |
414 | {"i386", Cpu086|Cpu186|Cpu286|Cpu386 }, | |
415 | {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 }, | |
416 | {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
417 | {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
418 | {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
419 | {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
a167610d | 420 | {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 }, |
3e73aa7c JH |
421 | {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow }, |
422 | {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow }, | |
a167610d | 423 | {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 }, |
e413e4e9 AM |
424 | {NULL, 0 } |
425 | }; | |
426 | ||
29b0f896 AM |
427 | const pseudo_typeS md_pseudo_table[] = |
428 | { | |
429 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
430 | {"align", s_align_bytes, 0}, | |
431 | #else | |
432 | {"align", s_align_ptwo, 0}, | |
433 | #endif | |
434 | {"arch", set_cpu_arch, 0}, | |
435 | #ifndef I386COFF | |
436 | {"bss", s_bss, 0}, | |
437 | #endif | |
438 | {"ffloat", float_cons, 'f'}, | |
439 | {"dfloat", float_cons, 'd'}, | |
440 | {"tfloat", float_cons, 'x'}, | |
441 | {"value", cons, 2}, | |
442 | {"noopt", s_ignore, 0}, | |
443 | {"optim", s_ignore, 0}, | |
444 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
445 | {"code16", set_code_flag, CODE_16BIT}, | |
446 | {"code32", set_code_flag, CODE_32BIT}, | |
447 | {"code64", set_code_flag, CODE_64BIT}, | |
448 | {"intel_syntax", set_intel_syntax, 1}, | |
449 | {"att_syntax", set_intel_syntax, 0}, | |
c6682705 | 450 | {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0}, |
29b0f896 AM |
451 | {"loc", dwarf2_directive_loc, 0}, |
452 | {0, 0, 0} | |
453 | }; | |
454 | ||
455 | /* For interface with expression (). */ | |
456 | extern char *input_line_pointer; | |
457 | ||
458 | /* Hash table for instruction mnemonic lookup. */ | |
459 | static struct hash_control *op_hash; | |
460 | ||
461 | /* Hash table for register lookup. */ | |
462 | static struct hash_control *reg_hash; | |
463 | \f | |
252b5132 RH |
464 | void |
465 | i386_align_code (fragP, count) | |
466 | fragS *fragP; | |
467 | int count; | |
468 | { | |
ce8a8b2f AM |
469 | /* Various efficient no-op patterns for aligning code labels. |
470 | Note: Don't try to assemble the instructions in the comments. | |
471 | 0L and 0w are not legal. */ | |
252b5132 RH |
472 | static const char f32_1[] = |
473 | {0x90}; /* nop */ | |
474 | static const char f32_2[] = | |
475 | {0x89,0xf6}; /* movl %esi,%esi */ | |
476 | static const char f32_3[] = | |
477 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
478 | static const char f32_4[] = | |
479 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
480 | static const char f32_5[] = | |
481 | {0x90, /* nop */ | |
482 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
483 | static const char f32_6[] = | |
484 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
485 | static const char f32_7[] = | |
486 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
487 | static const char f32_8[] = | |
488 | {0x90, /* nop */ | |
489 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
490 | static const char f32_9[] = | |
491 | {0x89,0xf6, /* movl %esi,%esi */ | |
492 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
493 | static const char f32_10[] = | |
494 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
495 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
496 | static const char f32_11[] = | |
497 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
498 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
499 | static const char f32_12[] = | |
500 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
501 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
502 | static const char f32_13[] = | |
503 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
504 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
505 | static const char f32_14[] = | |
506 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
507 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
508 | static const char f32_15[] = | |
509 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
510 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
c3332e24 AM |
511 | static const char f16_3[] = |
512 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
513 | static const char f16_4[] = |
514 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
515 | static const char f16_5[] = | |
516 | {0x90, /* nop */ | |
517 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
518 | static const char f16_6[] = | |
519 | {0x89,0xf6, /* mov %si,%si */ | |
520 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
521 | static const char f16_7[] = | |
522 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
523 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
524 | static const char f16_8[] = | |
525 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
526 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
527 | static const char *const f32_patt[] = { | |
528 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
529 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
530 | }; | |
531 | static const char *const f16_patt[] = { | |
c3332e24 | 532 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, |
252b5132 RH |
533 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 |
534 | }; | |
535 | ||
33fef721 JH |
536 | if (count <= 0 || count > 15) |
537 | return; | |
3e73aa7c | 538 | |
33fef721 JH |
539 | /* The recommended way to pad 64bit code is to use NOPs preceded by |
540 | maximally four 0x66 prefixes. Balance the size of nops. */ | |
541 | if (flag_code == CODE_64BIT) | |
252b5132 | 542 | { |
33fef721 JH |
543 | int i; |
544 | int nnops = (count + 3) / 4; | |
545 | int len = count / nnops; | |
546 | int remains = count - nnops * len; | |
547 | int pos = 0; | |
548 | ||
549 | for (i = 0; i < remains; i++) | |
252b5132 | 550 | { |
33fef721 JH |
551 | memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len); |
552 | fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90; | |
553 | pos += len + 1; | |
554 | } | |
555 | for (; i < nnops; i++) | |
556 | { | |
557 | memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1); | |
558 | fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90; | |
559 | pos += len; | |
252b5132 | 560 | } |
252b5132 | 561 | } |
33fef721 JH |
562 | else |
563 | if (flag_code == CODE_16BIT) | |
564 | { | |
565 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
566 | f16_patt[count - 1], count); | |
567 | if (count > 8) | |
568 | /* Adjust jump offset. */ | |
569 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
570 | } | |
571 | else | |
572 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
573 | f32_patt[count - 1], count); | |
574 | fragP->fr_var = count; | |
252b5132 RH |
575 | } |
576 | ||
252b5132 RH |
577 | static INLINE unsigned int |
578 | mode_from_disp_size (t) | |
579 | unsigned int t; | |
580 | { | |
3e73aa7c | 581 | return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0; |
252b5132 RH |
582 | } |
583 | ||
584 | static INLINE int | |
585 | fits_in_signed_byte (num) | |
847f7ad4 | 586 | offsetT num; |
252b5132 RH |
587 | { |
588 | return (num >= -128) && (num <= 127); | |
47926f60 | 589 | } |
252b5132 RH |
590 | |
591 | static INLINE int | |
592 | fits_in_unsigned_byte (num) | |
847f7ad4 | 593 | offsetT num; |
252b5132 RH |
594 | { |
595 | return (num & 0xff) == num; | |
47926f60 | 596 | } |
252b5132 RH |
597 | |
598 | static INLINE int | |
599 | fits_in_unsigned_word (num) | |
847f7ad4 | 600 | offsetT num; |
252b5132 RH |
601 | { |
602 | return (num & 0xffff) == num; | |
47926f60 | 603 | } |
252b5132 RH |
604 | |
605 | static INLINE int | |
606 | fits_in_signed_word (num) | |
847f7ad4 | 607 | offsetT num; |
252b5132 RH |
608 | { |
609 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 610 | } |
3e73aa7c JH |
611 | static INLINE int |
612 | fits_in_signed_long (num) | |
613 | offsetT num ATTRIBUTE_UNUSED; | |
614 | { | |
615 | #ifndef BFD64 | |
616 | return 1; | |
617 | #else | |
618 | return (!(((offsetT) -1 << 31) & num) | |
619 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); | |
620 | #endif | |
621 | } /* fits_in_signed_long() */ | |
622 | static INLINE int | |
623 | fits_in_unsigned_long (num) | |
624 | offsetT num ATTRIBUTE_UNUSED; | |
625 | { | |
626 | #ifndef BFD64 | |
627 | return 1; | |
628 | #else | |
629 | return (num & (((offsetT) 2 << 31) - 1)) == num; | |
630 | #endif | |
631 | } /* fits_in_unsigned_long() */ | |
252b5132 RH |
632 | |
633 | static int | |
634 | smallest_imm_type (num) | |
847f7ad4 | 635 | offsetT num; |
252b5132 | 636 | { |
a847613f | 637 | if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)) |
e413e4e9 AM |
638 | { |
639 | /* This code is disabled on the 486 because all the Imm1 forms | |
640 | in the opcode table are slower on the i486. They're the | |
641 | versions with the implicitly specified single-position | |
642 | displacement, which has another syntax if you really want to | |
643 | use that form. */ | |
644 | if (num == 1) | |
3e73aa7c | 645 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64; |
e413e4e9 | 646 | } |
252b5132 | 647 | return (fits_in_signed_byte (num) |
3e73aa7c | 648 | ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64) |
252b5132 | 649 | : fits_in_unsigned_byte (num) |
3e73aa7c | 650 | ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64) |
252b5132 | 651 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) |
3e73aa7c JH |
652 | ? (Imm16 | Imm32 | Imm32S | Imm64) |
653 | : fits_in_signed_long (num) | |
654 | ? (Imm32 | Imm32S | Imm64) | |
655 | : fits_in_unsigned_long (num) | |
656 | ? (Imm32 | Imm64) | |
657 | : Imm64); | |
47926f60 | 658 | } |
252b5132 | 659 | |
847f7ad4 AM |
660 | static offsetT |
661 | offset_in_range (val, size) | |
662 | offsetT val; | |
663 | int size; | |
664 | { | |
508866be | 665 | addressT mask; |
ba2adb93 | 666 | |
847f7ad4 AM |
667 | switch (size) |
668 | { | |
508866be L |
669 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
670 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 671 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
672 | #ifdef BFD64 |
673 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
674 | #endif | |
47926f60 | 675 | default: abort (); |
847f7ad4 AM |
676 | } |
677 | ||
ba2adb93 | 678 | /* If BFD64, sign extend val. */ |
3e73aa7c JH |
679 | if (!use_rela_relocations) |
680 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) | |
681 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
ba2adb93 | 682 | |
47926f60 | 683 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
684 | { |
685 | char buf1[40], buf2[40]; | |
686 | ||
687 | sprint_value (buf1, val); | |
688 | sprint_value (buf2, val & mask); | |
689 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
690 | } | |
691 | return val & mask; | |
692 | } | |
693 | ||
252b5132 RH |
694 | /* Returns 0 if attempting to add a prefix where one from the same |
695 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
696 | added. */ | |
697 | static int | |
698 | add_prefix (prefix) | |
699 | unsigned int prefix; | |
700 | { | |
701 | int ret = 1; | |
702 | int q; | |
703 | ||
29b0f896 AM |
704 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
705 | && flag_code == CODE_64BIT) | |
3e73aa7c JH |
706 | q = REX_PREFIX; |
707 | else | |
708 | switch (prefix) | |
709 | { | |
710 | default: | |
711 | abort (); | |
712 | ||
713 | case CS_PREFIX_OPCODE: | |
714 | case DS_PREFIX_OPCODE: | |
715 | case ES_PREFIX_OPCODE: | |
716 | case FS_PREFIX_OPCODE: | |
717 | case GS_PREFIX_OPCODE: | |
718 | case SS_PREFIX_OPCODE: | |
719 | q = SEG_PREFIX; | |
720 | break; | |
252b5132 | 721 | |
3e73aa7c JH |
722 | case REPNE_PREFIX_OPCODE: |
723 | case REPE_PREFIX_OPCODE: | |
724 | ret = 2; | |
725 | /* fall thru */ | |
726 | case LOCK_PREFIX_OPCODE: | |
727 | q = LOCKREP_PREFIX; | |
728 | break; | |
252b5132 | 729 | |
3e73aa7c JH |
730 | case FWAIT_OPCODE: |
731 | q = WAIT_PREFIX; | |
732 | break; | |
252b5132 | 733 | |
3e73aa7c JH |
734 | case ADDR_PREFIX_OPCODE: |
735 | q = ADDR_PREFIX; | |
736 | break; | |
252b5132 | 737 | |
3e73aa7c JH |
738 | case DATA_PREFIX_OPCODE: |
739 | q = DATA_PREFIX; | |
740 | break; | |
741 | } | |
252b5132 | 742 | |
29b0f896 | 743 | if (i.prefix[q] != 0) |
252b5132 RH |
744 | { |
745 | as_bad (_("same type of prefix used twice")); | |
746 | return 0; | |
747 | } | |
748 | ||
749 | i.prefixes += 1; | |
750 | i.prefix[q] = prefix; | |
751 | return ret; | |
752 | } | |
753 | ||
754 | static void | |
3e73aa7c | 755 | set_code_flag (value) |
e5cb08ac | 756 | int value; |
eecb386c | 757 | { |
3e73aa7c JH |
758 | flag_code = value; |
759 | cpu_arch_flags &= ~(Cpu64 | CpuNo64); | |
760 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); | |
761 | if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer)) | |
762 | { | |
763 | as_bad (_("64bit mode not supported on this CPU.")); | |
764 | } | |
765 | if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386)) | |
766 | { | |
767 | as_bad (_("32bit mode not supported on this CPU.")); | |
768 | } | |
eecb386c AM |
769 | stackop_size = '\0'; |
770 | } | |
771 | ||
772 | static void | |
3e73aa7c JH |
773 | set_16bit_gcc_code_flag (new_code_flag) |
774 | int new_code_flag; | |
252b5132 | 775 | { |
3e73aa7c JH |
776 | flag_code = new_code_flag; |
777 | cpu_arch_flags &= ~(Cpu64 | CpuNo64); | |
778 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); | |
779 | stackop_size = 'l'; | |
252b5132 RH |
780 | } |
781 | ||
782 | static void | |
783 | set_intel_syntax (syntax_flag) | |
eecb386c | 784 | int syntax_flag; |
252b5132 RH |
785 | { |
786 | /* Find out if register prefixing is specified. */ | |
787 | int ask_naked_reg = 0; | |
788 | ||
789 | SKIP_WHITESPACE (); | |
29b0f896 | 790 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 RH |
791 | { |
792 | char *string = input_line_pointer; | |
793 | int e = get_symbol_end (); | |
794 | ||
47926f60 | 795 | if (strcmp (string, "prefix") == 0) |
252b5132 | 796 | ask_naked_reg = 1; |
47926f60 | 797 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
798 | ask_naked_reg = -1; |
799 | else | |
d0b47220 | 800 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
801 | *input_line_pointer = e; |
802 | } | |
803 | demand_empty_rest_of_line (); | |
c3332e24 | 804 | |
252b5132 RH |
805 | intel_syntax = syntax_flag; |
806 | ||
807 | if (ask_naked_reg == 0) | |
808 | { | |
809 | #ifdef BFD_ASSEMBLER | |
810 | allow_naked_reg = (intel_syntax | |
24eab124 | 811 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); |
252b5132 | 812 | #else |
47926f60 KH |
813 | /* Conservative default. */ |
814 | allow_naked_reg = 0; | |
252b5132 RH |
815 | #endif |
816 | } | |
817 | else | |
818 | allow_naked_reg = (ask_naked_reg < 0); | |
819 | } | |
820 | ||
e413e4e9 AM |
821 | static void |
822 | set_cpu_arch (dummy) | |
47926f60 | 823 | int dummy ATTRIBUTE_UNUSED; |
e413e4e9 | 824 | { |
47926f60 | 825 | SKIP_WHITESPACE (); |
e413e4e9 | 826 | |
29b0f896 | 827 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 AM |
828 | { |
829 | char *string = input_line_pointer; | |
830 | int e = get_symbol_end (); | |
831 | int i; | |
832 | ||
833 | for (i = 0; cpu_arch[i].name; i++) | |
834 | { | |
835 | if (strcmp (string, cpu_arch[i].name) == 0) | |
836 | { | |
837 | cpu_arch_name = cpu_arch[i].name; | |
fddf5b5b AM |
838 | cpu_arch_flags = (cpu_arch[i].flags |
839 | | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64)); | |
e413e4e9 AM |
840 | break; |
841 | } | |
842 | } | |
843 | if (!cpu_arch[i].name) | |
844 | as_bad (_("no such architecture: `%s'"), string); | |
845 | ||
846 | *input_line_pointer = e; | |
847 | } | |
848 | else | |
849 | as_bad (_("missing cpu architecture")); | |
850 | ||
fddf5b5b AM |
851 | no_cond_jump_promotion = 0; |
852 | if (*input_line_pointer == ',' | |
29b0f896 | 853 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b AM |
854 | { |
855 | char *string = ++input_line_pointer; | |
856 | int e = get_symbol_end (); | |
857 | ||
858 | if (strcmp (string, "nojumps") == 0) | |
859 | no_cond_jump_promotion = 1; | |
860 | else if (strcmp (string, "jumps") == 0) | |
861 | ; | |
862 | else | |
863 | as_bad (_("no such architecture modifier: `%s'"), string); | |
864 | ||
865 | *input_line_pointer = e; | |
866 | } | |
867 | ||
e413e4e9 AM |
868 | demand_empty_rest_of_line (); |
869 | } | |
870 | ||
b9d79e03 JH |
871 | #ifdef BFD_ASSEMBLER |
872 | unsigned long | |
873 | i386_mach () | |
874 | { | |
875 | if (!strcmp (default_arch, "x86_64")) | |
876 | return bfd_mach_x86_64; | |
877 | else if (!strcmp (default_arch, "i386")) | |
878 | return bfd_mach_i386_i386; | |
879 | else | |
880 | as_fatal (_("Unknown architecture")); | |
881 | } | |
882 | #endif | |
883 | \f | |
252b5132 RH |
884 | void |
885 | md_begin () | |
886 | { | |
887 | const char *hash_err; | |
888 | ||
47926f60 | 889 | /* Initialize op_hash hash table. */ |
252b5132 RH |
890 | op_hash = hash_new (); |
891 | ||
892 | { | |
29b0f896 AM |
893 | const template *optab; |
894 | templates *core_optab; | |
252b5132 | 895 | |
47926f60 KH |
896 | /* Setup for loop. */ |
897 | optab = i386_optab; | |
252b5132 RH |
898 | core_optab = (templates *) xmalloc (sizeof (templates)); |
899 | core_optab->start = optab; | |
900 | ||
901 | while (1) | |
902 | { | |
903 | ++optab; | |
904 | if (optab->name == NULL | |
905 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
906 | { | |
907 | /* different name --> ship out current template list; | |
47926f60 | 908 | add to hash table; & begin anew. */ |
252b5132 RH |
909 | core_optab->end = optab; |
910 | hash_err = hash_insert (op_hash, | |
911 | (optab - 1)->name, | |
912 | (PTR) core_optab); | |
913 | if (hash_err) | |
914 | { | |
252b5132 RH |
915 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
916 | (optab - 1)->name, | |
917 | hash_err); | |
918 | } | |
919 | if (optab->name == NULL) | |
920 | break; | |
921 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
922 | core_optab->start = optab; | |
923 | } | |
924 | } | |
925 | } | |
926 | ||
47926f60 | 927 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
928 | reg_hash = hash_new (); |
929 | { | |
29b0f896 | 930 | const reg_entry *regtab; |
252b5132 RH |
931 | |
932 | for (regtab = i386_regtab; | |
933 | regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); | |
934 | regtab++) | |
935 | { | |
936 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); | |
937 | if (hash_err) | |
3e73aa7c JH |
938 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
939 | regtab->reg_name, | |
940 | hash_err); | |
252b5132 RH |
941 | } |
942 | } | |
943 | ||
47926f60 | 944 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 945 | { |
29b0f896 AM |
946 | int c; |
947 | char *p; | |
252b5132 RH |
948 | |
949 | for (c = 0; c < 256; c++) | |
950 | { | |
3882b010 | 951 | if (ISDIGIT (c)) |
252b5132 RH |
952 | { |
953 | digit_chars[c] = c; | |
954 | mnemonic_chars[c] = c; | |
955 | register_chars[c] = c; | |
956 | operand_chars[c] = c; | |
957 | } | |
3882b010 | 958 | else if (ISLOWER (c)) |
252b5132 RH |
959 | { |
960 | mnemonic_chars[c] = c; | |
961 | register_chars[c] = c; | |
962 | operand_chars[c] = c; | |
963 | } | |
3882b010 | 964 | else if (ISUPPER (c)) |
252b5132 | 965 | { |
3882b010 | 966 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
967 | register_chars[c] = mnemonic_chars[c]; |
968 | operand_chars[c] = c; | |
969 | } | |
970 | ||
3882b010 | 971 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
972 | identifier_chars[c] = c; |
973 | else if (c >= 128) | |
974 | { | |
975 | identifier_chars[c] = c; | |
976 | operand_chars[c] = c; | |
977 | } | |
978 | } | |
979 | ||
980 | #ifdef LEX_AT | |
981 | identifier_chars['@'] = '@'; | |
982 | #endif | |
252b5132 RH |
983 | digit_chars['-'] = '-'; |
984 | identifier_chars['_'] = '_'; | |
985 | identifier_chars['.'] = '.'; | |
986 | ||
987 | for (p = operand_special_chars; *p != '\0'; p++) | |
988 | operand_chars[(unsigned char) *p] = *p; | |
989 | } | |
990 | ||
991 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
992 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
993 | { | |
994 | record_alignment (text_section, 2); | |
995 | record_alignment (data_section, 2); | |
996 | record_alignment (bss_section, 2); | |
997 | } | |
998 | #endif | |
a4447b93 RH |
999 | |
1000 | if (flag_code == CODE_64BIT) | |
1001 | { | |
1002 | x86_dwarf2_return_column = 16; | |
1003 | x86_cie_data_alignment = -8; | |
1004 | } | |
1005 | else | |
1006 | { | |
1007 | x86_dwarf2_return_column = 8; | |
1008 | x86_cie_data_alignment = -4; | |
1009 | } | |
252b5132 RH |
1010 | } |
1011 | ||
1012 | void | |
1013 | i386_print_statistics (file) | |
1014 | FILE *file; | |
1015 | { | |
1016 | hash_print_statistics (file, "i386 opcode", op_hash); | |
1017 | hash_print_statistics (file, "i386 register", reg_hash); | |
1018 | } | |
1019 | \f | |
252b5132 RH |
1020 | #ifdef DEBUG386 |
1021 | ||
ce8a8b2f | 1022 | /* Debugging routines for md_assemble. */ |
252b5132 RH |
1023 | static void pi PARAMS ((char *, i386_insn *)); |
1024 | static void pte PARAMS ((template *)); | |
1025 | static void pt PARAMS ((unsigned int)); | |
1026 | static void pe PARAMS ((expressionS *)); | |
1027 | static void ps PARAMS ((symbolS *)); | |
1028 | ||
1029 | static void | |
1030 | pi (line, x) | |
1031 | char *line; | |
1032 | i386_insn *x; | |
1033 | { | |
09f131f2 | 1034 | unsigned int i; |
252b5132 RH |
1035 | |
1036 | fprintf (stdout, "%s: template ", line); | |
1037 | pte (&x->tm); | |
09f131f2 JH |
1038 | fprintf (stdout, " address: base %s index %s scale %x\n", |
1039 | x->base_reg ? x->base_reg->reg_name : "none", | |
1040 | x->index_reg ? x->index_reg->reg_name : "none", | |
1041 | x->log2_scale_factor); | |
1042 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 1043 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
1044 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
1045 | x->sib.base, x->sib.index, x->sib.scale); | |
1046 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
29b0f896 AM |
1047 | (x->rex & REX_MODE64) != 0, |
1048 | (x->rex & REX_EXTX) != 0, | |
1049 | (x->rex & REX_EXTY) != 0, | |
1050 | (x->rex & REX_EXTZ) != 0); | |
252b5132 RH |
1051 | for (i = 0; i < x->operands; i++) |
1052 | { | |
1053 | fprintf (stdout, " #%d: ", i + 1); | |
1054 | pt (x->types[i]); | |
1055 | fprintf (stdout, "\n"); | |
1056 | if (x->types[i] | |
3f4438ab | 1057 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) |
520dc8e8 | 1058 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
252b5132 | 1059 | if (x->types[i] & Imm) |
520dc8e8 | 1060 | pe (x->op[i].imms); |
252b5132 | 1061 | if (x->types[i] & Disp) |
520dc8e8 | 1062 | pe (x->op[i].disps); |
252b5132 RH |
1063 | } |
1064 | } | |
1065 | ||
1066 | static void | |
1067 | pte (t) | |
1068 | template *t; | |
1069 | { | |
09f131f2 | 1070 | unsigned int i; |
252b5132 | 1071 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 1072 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
1073 | if (t->extension_opcode != None) |
1074 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
1075 | if (t->opcode_modifier & D) | |
1076 | fprintf (stdout, "D"); | |
1077 | if (t->opcode_modifier & W) | |
1078 | fprintf (stdout, "W"); | |
1079 | fprintf (stdout, "\n"); | |
1080 | for (i = 0; i < t->operands; i++) | |
1081 | { | |
1082 | fprintf (stdout, " #%d type ", i + 1); | |
1083 | pt (t->operand_types[i]); | |
1084 | fprintf (stdout, "\n"); | |
1085 | } | |
1086 | } | |
1087 | ||
1088 | static void | |
1089 | pe (e) | |
1090 | expressionS *e; | |
1091 | { | |
24eab124 | 1092 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
1093 | fprintf (stdout, " add_number %ld (%lx)\n", |
1094 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
1095 | if (e->X_add_symbol) |
1096 | { | |
1097 | fprintf (stdout, " add_symbol "); | |
1098 | ps (e->X_add_symbol); | |
1099 | fprintf (stdout, "\n"); | |
1100 | } | |
1101 | if (e->X_op_symbol) | |
1102 | { | |
1103 | fprintf (stdout, " op_symbol "); | |
1104 | ps (e->X_op_symbol); | |
1105 | fprintf (stdout, "\n"); | |
1106 | } | |
1107 | } | |
1108 | ||
1109 | static void | |
1110 | ps (s) | |
1111 | symbolS *s; | |
1112 | { | |
1113 | fprintf (stdout, "%s type %s%s", | |
1114 | S_GET_NAME (s), | |
1115 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
1116 | segment_name (S_GET_SEGMENT (s))); | |
1117 | } | |
1118 | ||
1119 | struct type_name | |
1120 | { | |
1121 | unsigned int mask; | |
1122 | char *tname; | |
1123 | } | |
1124 | ||
29b0f896 | 1125 | static const type_names[] = |
252b5132 RH |
1126 | { |
1127 | { Reg8, "r8" }, | |
1128 | { Reg16, "r16" }, | |
1129 | { Reg32, "r32" }, | |
09f131f2 | 1130 | { Reg64, "r64" }, |
252b5132 RH |
1131 | { Imm8, "i8" }, |
1132 | { Imm8S, "i8s" }, | |
1133 | { Imm16, "i16" }, | |
1134 | { Imm32, "i32" }, | |
09f131f2 JH |
1135 | { Imm32S, "i32s" }, |
1136 | { Imm64, "i64" }, | |
252b5132 RH |
1137 | { Imm1, "i1" }, |
1138 | { BaseIndex, "BaseIndex" }, | |
1139 | { Disp8, "d8" }, | |
1140 | { Disp16, "d16" }, | |
1141 | { Disp32, "d32" }, | |
09f131f2 JH |
1142 | { Disp32S, "d32s" }, |
1143 | { Disp64, "d64" }, | |
252b5132 RH |
1144 | { InOutPortReg, "InOutPortReg" }, |
1145 | { ShiftCount, "ShiftCount" }, | |
1146 | { Control, "control reg" }, | |
1147 | { Test, "test reg" }, | |
1148 | { Debug, "debug reg" }, | |
1149 | { FloatReg, "FReg" }, | |
1150 | { FloatAcc, "FAcc" }, | |
1151 | { SReg2, "SReg2" }, | |
1152 | { SReg3, "SReg3" }, | |
1153 | { Acc, "Acc" }, | |
1154 | { JumpAbsolute, "Jump Absolute" }, | |
1155 | { RegMMX, "rMMX" }, | |
3f4438ab | 1156 | { RegXMM, "rXMM" }, |
252b5132 RH |
1157 | { EsSeg, "es" }, |
1158 | { 0, "" } | |
1159 | }; | |
1160 | ||
1161 | static void | |
1162 | pt (t) | |
1163 | unsigned int t; | |
1164 | { | |
29b0f896 | 1165 | const struct type_name *ty; |
252b5132 | 1166 | |
09f131f2 JH |
1167 | for (ty = type_names; ty->mask; ty++) |
1168 | if (t & ty->mask) | |
1169 | fprintf (stdout, "%s, ", ty->tname); | |
252b5132 RH |
1170 | fflush (stdout); |
1171 | } | |
1172 | ||
1173 | #endif /* DEBUG386 */ | |
1174 | \f | |
252b5132 | 1175 | #ifdef BFD_ASSEMBLER |
29b0f896 AM |
1176 | static bfd_reloc_code_real_type reloc |
1177 | PARAMS ((int, int, int, bfd_reloc_code_real_type)); | |
252b5132 RH |
1178 | |
1179 | static bfd_reloc_code_real_type | |
3e73aa7c | 1180 | reloc (size, pcrel, sign, other) |
252b5132 RH |
1181 | int size; |
1182 | int pcrel; | |
3e73aa7c | 1183 | int sign; |
252b5132 RH |
1184 | bfd_reloc_code_real_type other; |
1185 | { | |
47926f60 KH |
1186 | if (other != NO_RELOC) |
1187 | return other; | |
252b5132 RH |
1188 | |
1189 | if (pcrel) | |
1190 | { | |
3e73aa7c | 1191 | if (!sign) |
e5cb08ac | 1192 | as_bad (_("There are no unsigned pc-relative relocations")); |
252b5132 RH |
1193 | switch (size) |
1194 | { | |
1195 | case 1: return BFD_RELOC_8_PCREL; | |
1196 | case 2: return BFD_RELOC_16_PCREL; | |
1197 | case 4: return BFD_RELOC_32_PCREL; | |
1198 | } | |
d0b47220 | 1199 | as_bad (_("can not do %d byte pc-relative relocation"), size); |
252b5132 RH |
1200 | } |
1201 | else | |
1202 | { | |
3e73aa7c | 1203 | if (sign) |
e5cb08ac | 1204 | switch (size) |
3e73aa7c JH |
1205 | { |
1206 | case 4: return BFD_RELOC_X86_64_32S; | |
1207 | } | |
1208 | else | |
1209 | switch (size) | |
1210 | { | |
1211 | case 1: return BFD_RELOC_8; | |
1212 | case 2: return BFD_RELOC_16; | |
1213 | case 4: return BFD_RELOC_32; | |
1214 | case 8: return BFD_RELOC_64; | |
1215 | } | |
1216 | as_bad (_("can not do %s %d byte relocation"), | |
1217 | sign ? "signed" : "unsigned", size); | |
252b5132 RH |
1218 | } |
1219 | ||
bfb32b52 | 1220 | abort (); |
252b5132 RH |
1221 | return BFD_RELOC_NONE; |
1222 | } | |
1223 | ||
47926f60 KH |
1224 | /* Here we decide which fixups can be adjusted to make them relative to |
1225 | the beginning of the section instead of the symbol. Basically we need | |
1226 | to make sure that the dynamic relocations are done correctly, so in | |
1227 | some cases we force the original symbol to be used. */ | |
1228 | ||
252b5132 | 1229 | int |
c0c949c7 | 1230 | tc_i386_fix_adjustable (fixP) |
31312f95 | 1231 | fixS *fixP ATTRIBUTE_UNUSED; |
252b5132 | 1232 | { |
6d249963 | 1233 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
31312f95 AM |
1234 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
1235 | return 1; | |
1236 | ||
a161fe53 AM |
1237 | /* Don't adjust pc-relative references to merge sections in 64-bit |
1238 | mode. */ | |
1239 | if (use_rela_relocations | |
1240 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
1241 | && fixP->fx_pcrel) | |
252b5132 | 1242 | return 0; |
31312f95 | 1243 | |
ce8a8b2f | 1244 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
1245 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
1246 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
1247 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
13ae64f3 JJ |
1248 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
1249 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
1250 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
1251 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
1252 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
1253 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
1254 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
1255 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
3e73aa7c JH |
1256 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
1257 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 1258 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
bffbf940 JJ |
1259 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
1260 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
1261 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
1262 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF | |
1263 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
252b5132 RH |
1264 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
1265 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1266 | return 0; | |
31312f95 | 1267 | #endif |
252b5132 RH |
1268 | return 1; |
1269 | } | |
1270 | #else | |
ec56dfb4 | 1271 | #define reloc(SIZE,PCREL,SIGN,OTHER) 0 |
c6682705 | 1272 | #define BFD_RELOC_8 0 |
ec56dfb4 L |
1273 | #define BFD_RELOC_16 0 |
1274 | #define BFD_RELOC_32 0 | |
c6682705 | 1275 | #define BFD_RELOC_8_PCREL 0 |
ec56dfb4 L |
1276 | #define BFD_RELOC_16_PCREL 0 |
1277 | #define BFD_RELOC_32_PCREL 0 | |
1278 | #define BFD_RELOC_386_PLT32 0 | |
1279 | #define BFD_RELOC_386_GOT32 0 | |
1280 | #define BFD_RELOC_386_GOTOFF 0 | |
13ae64f3 JJ |
1281 | #define BFD_RELOC_386_TLS_GD 0 |
1282 | #define BFD_RELOC_386_TLS_LDM 0 | |
1283 | #define BFD_RELOC_386_TLS_LDO_32 0 | |
1284 | #define BFD_RELOC_386_TLS_IE_32 0 | |
37e55690 JJ |
1285 | #define BFD_RELOC_386_TLS_IE 0 |
1286 | #define BFD_RELOC_386_TLS_GOTIE 0 | |
13ae64f3 JJ |
1287 | #define BFD_RELOC_386_TLS_LE_32 0 |
1288 | #define BFD_RELOC_386_TLS_LE 0 | |
ec56dfb4 L |
1289 | #define BFD_RELOC_X86_64_PLT32 0 |
1290 | #define BFD_RELOC_X86_64_GOT32 0 | |
1291 | #define BFD_RELOC_X86_64_GOTPCREL 0 | |
bffbf940 JJ |
1292 | #define BFD_RELOC_X86_64_TLSGD 0 |
1293 | #define BFD_RELOC_X86_64_TLSLD 0 | |
1294 | #define BFD_RELOC_X86_64_DTPOFF32 0 | |
1295 | #define BFD_RELOC_X86_64_GOTTPOFF 0 | |
1296 | #define BFD_RELOC_X86_64_TPOFF32 0 | |
252b5132 RH |
1297 | #endif |
1298 | ||
29b0f896 | 1299 | static int intel_float_operand PARAMS ((const char *mnemonic)); |
b4cac588 AM |
1300 | |
1301 | static int | |
252b5132 | 1302 | intel_float_operand (mnemonic) |
29b0f896 | 1303 | const char *mnemonic; |
252b5132 | 1304 | { |
47926f60 | 1305 | if (mnemonic[0] == 'f' && mnemonic[1] == 'i') |
cc5ca5ce | 1306 | return 2; |
252b5132 RH |
1307 | |
1308 | if (mnemonic[0] == 'f') | |
1309 | return 1; | |
1310 | ||
1311 | return 0; | |
1312 | } | |
1313 | ||
1314 | /* This is the guts of the machine-dependent assembler. LINE points to a | |
1315 | machine dependent instruction. This function is supposed to emit | |
1316 | the frags/bytes it assembles to. */ | |
1317 | ||
1318 | void | |
1319 | md_assemble (line) | |
1320 | char *line; | |
1321 | { | |
252b5132 | 1322 | int j; |
252b5132 RH |
1323 | char mnemonic[MAX_MNEM_SIZE]; |
1324 | ||
47926f60 | 1325 | /* Initialize globals. */ |
252b5132 RH |
1326 | memset (&i, '\0', sizeof (i)); |
1327 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 1328 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
1329 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
1330 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 1331 | save_stack_p = save_stack; |
252b5132 RH |
1332 | |
1333 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
1334 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 1335 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 1336 | |
29b0f896 AM |
1337 | line = parse_insn (line, mnemonic); |
1338 | if (line == NULL) | |
1339 | return; | |
252b5132 | 1340 | |
29b0f896 AM |
1341 | line = parse_operands (line, mnemonic); |
1342 | if (line == NULL) | |
1343 | return; | |
252b5132 | 1344 | |
29b0f896 AM |
1345 | /* Now we've parsed the mnemonic into a set of templates, and have the |
1346 | operands at hand. */ | |
1347 | ||
1348 | /* All intel opcodes have reversed operands except for "bound" and | |
1349 | "enter". We also don't reverse intersegment "jmp" and "call" | |
1350 | instructions with 2 immediate operands so that the immediate segment | |
1351 | precedes the offset, as it does when in AT&T mode. "enter" and the | |
1352 | intersegment "jmp" and "call" instructions are the only ones that | |
1353 | have two immediate operands. */ | |
1354 | if (intel_syntax && i.operands > 1 | |
1355 | && (strcmp (mnemonic, "bound") != 0) | |
1356 | && !((i.types[0] & Imm) && (i.types[1] & Imm))) | |
1357 | swap_operands (); | |
1358 | ||
1359 | if (i.imm_operands) | |
1360 | optimize_imm (); | |
1361 | ||
1362 | if (i.disp_operands) | |
1363 | optimize_disp (); | |
1364 | ||
1365 | /* Next, we find a template that matches the given insn, | |
1366 | making sure the overlap of the given operands types is consistent | |
1367 | with the template operand types. */ | |
252b5132 | 1368 | |
29b0f896 AM |
1369 | if (!match_template ()) |
1370 | return; | |
252b5132 | 1371 | |
cd61ebfe AM |
1372 | if (intel_syntax) |
1373 | { | |
1374 | /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ | |
1375 | if (SYSV386_COMPAT | |
1376 | && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) | |
1377 | i.tm.base_opcode ^= FloatR; | |
1378 | ||
1379 | /* Zap movzx and movsx suffix. The suffix may have been set from | |
1380 | "word ptr" or "byte ptr" on the source operand, but we'll use | |
1381 | the suffix later to choose the destination register. */ | |
1382 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
1383 | i.suffix = 0; | |
1384 | } | |
24eab124 | 1385 | |
29b0f896 AM |
1386 | if (i.tm.opcode_modifier & FWait) |
1387 | if (!add_prefix (FWAIT_OPCODE)) | |
1388 | return; | |
252b5132 | 1389 | |
29b0f896 AM |
1390 | /* Check string instruction segment overrides. */ |
1391 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) | |
1392 | { | |
1393 | if (!check_string ()) | |
5dd0794d | 1394 | return; |
29b0f896 | 1395 | } |
5dd0794d | 1396 | |
29b0f896 AM |
1397 | if (!process_suffix ()) |
1398 | return; | |
e413e4e9 | 1399 | |
29b0f896 AM |
1400 | /* Make still unresolved immediate matches conform to size of immediate |
1401 | given in i.suffix. */ | |
1402 | if (!finalize_imm ()) | |
1403 | return; | |
252b5132 | 1404 | |
29b0f896 AM |
1405 | if (i.types[0] & Imm1) |
1406 | i.imm_operands = 0; /* kludge for shift insns. */ | |
1407 | if (i.types[0] & ImplicitRegister) | |
1408 | i.reg_operands--; | |
1409 | if (i.types[1] & ImplicitRegister) | |
1410 | i.reg_operands--; | |
1411 | if (i.types[2] & ImplicitRegister) | |
1412 | i.reg_operands--; | |
252b5132 | 1413 | |
29b0f896 AM |
1414 | if (i.tm.opcode_modifier & ImmExt) |
1415 | { | |
ca164297 L |
1416 | if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0) |
1417 | { | |
1418 | /* These Intel Precott New Instructions have the fixed | |
1419 | operands with an opcode suffix which is coded in the same | |
1420 | place as an 8-bit immediate field would be. Here we check | |
1421 | those operands and remove them afterwards. */ | |
1422 | unsigned int x; | |
1423 | ||
1424 | for (x = 0; x < i.operands; x++) | |
1425 | if (i.op[x].regs->reg_num != x) | |
1426 | as_bad (_("can't use register '%%%s' as operand %d in '%s'."), | |
1427 | i.op[x].regs->reg_name, x + 1, i.tm.name); | |
1428 | i.operands = 0; | |
1429 | } | |
1430 | ||
29b0f896 AM |
1431 | /* These AMD 3DNow! and Intel Katmai New Instructions have an |
1432 | opcode suffix which is coded in the same place as an 8-bit | |
1433 | immediate field would be. Here we fake an 8-bit immediate | |
1434 | operand from the opcode suffix stored in tm.extension_opcode. */ | |
252b5132 | 1435 | |
29b0f896 | 1436 | expressionS *exp; |
252b5132 | 1437 | |
29b0f896 | 1438 | assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); |
252b5132 | 1439 | |
29b0f896 AM |
1440 | exp = &im_expressions[i.imm_operands++]; |
1441 | i.op[i.operands].imms = exp; | |
1442 | i.types[i.operands++] = Imm8; | |
1443 | exp->X_op = O_constant; | |
1444 | exp->X_add_number = i.tm.extension_opcode; | |
1445 | i.tm.extension_opcode = None; | |
1446 | } | |
252b5132 | 1447 | |
29b0f896 AM |
1448 | /* For insns with operands there are more diddles to do to the opcode. */ |
1449 | if (i.operands) | |
1450 | { | |
1451 | if (!process_operands ()) | |
1452 | return; | |
1453 | } | |
1454 | else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) | |
1455 | { | |
1456 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
1457 | as_warn (_("translating to `%sp'"), i.tm.name); | |
1458 | } | |
252b5132 | 1459 | |
29b0f896 AM |
1460 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
1461 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) | |
1462 | { | |
1463 | i.tm.base_opcode = INT3_OPCODE; | |
1464 | i.imm_operands = 0; | |
1465 | } | |
252b5132 | 1466 | |
29b0f896 AM |
1467 | if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) |
1468 | && i.op[0].disps->X_op == O_constant) | |
1469 | { | |
1470 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
1471 | the absolute address given by the constant. Since ix86 jumps and | |
1472 | calls are pc relative, we need to generate a reloc. */ | |
1473 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
1474 | i.op[0].disps->X_op = O_symbol; | |
1475 | } | |
252b5132 | 1476 | |
29b0f896 AM |
1477 | if ((i.tm.opcode_modifier & Rex64) != 0) |
1478 | i.rex |= REX_MODE64; | |
252b5132 | 1479 | |
29b0f896 AM |
1480 | /* For 8 bit registers we need an empty rex prefix. Also if the |
1481 | instruction already has a prefix, we need to convert old | |
1482 | registers to new ones. */ | |
773f551c | 1483 | |
29b0f896 AM |
1484 | if (((i.types[0] & Reg8) != 0 |
1485 | && (i.op[0].regs->reg_flags & RegRex64) != 0) | |
1486 | || ((i.types[1] & Reg8) != 0 | |
1487 | && (i.op[1].regs->reg_flags & RegRex64) != 0) | |
1488 | || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0) | |
1489 | && i.rex != 0)) | |
1490 | { | |
1491 | int x; | |
726c5dcd | 1492 | |
29b0f896 AM |
1493 | i.rex |= REX_OPCODE; |
1494 | for (x = 0; x < 2; x++) | |
1495 | { | |
1496 | /* Look for 8 bit operand that uses old registers. */ | |
1497 | if ((i.types[x] & Reg8) != 0 | |
1498 | && (i.op[x].regs->reg_flags & RegRex64) == 0) | |
773f551c | 1499 | { |
29b0f896 AM |
1500 | /* In case it is "hi" register, give up. */ |
1501 | if (i.op[x].regs->reg_num > 3) | |
1502 | as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"), | |
1503 | i.op[x].regs->reg_name); | |
773f551c | 1504 | |
29b0f896 AM |
1505 | /* Otherwise it is equivalent to the extended register. |
1506 | Since the encoding doesn't change this is merely | |
1507 | cosmetic cleanup for debug output. */ | |
1508 | ||
1509 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 1510 | } |
29b0f896 AM |
1511 | } |
1512 | } | |
773f551c | 1513 | |
29b0f896 AM |
1514 | if (i.rex != 0) |
1515 | add_prefix (REX_OPCODE | i.rex); | |
1516 | ||
1517 | /* We are ready to output the insn. */ | |
1518 | output_insn (); | |
1519 | } | |
1520 | ||
1521 | static char * | |
1522 | parse_insn (line, mnemonic) | |
1523 | char *line; | |
1524 | char *mnemonic; | |
1525 | { | |
1526 | char *l = line; | |
1527 | char *token_start = l; | |
1528 | char *mnem_p; | |
1529 | ||
1530 | /* Non-zero if we found a prefix only acceptable with string insns. */ | |
1531 | const char *expecting_string_instruction = NULL; | |
45288df1 | 1532 | |
29b0f896 AM |
1533 | while (1) |
1534 | { | |
1535 | mnem_p = mnemonic; | |
1536 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
1537 | { | |
1538 | mnem_p++; | |
1539 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 1540 | { |
29b0f896 AM |
1541 | as_bad (_("no such instruction: `%s'"), token_start); |
1542 | return NULL; | |
1543 | } | |
1544 | l++; | |
1545 | } | |
1546 | if (!is_space_char (*l) | |
1547 | && *l != END_OF_INSN | |
1548 | && *l != PREFIX_SEPARATOR | |
1549 | && *l != ',') | |
1550 | { | |
1551 | as_bad (_("invalid character %s in mnemonic"), | |
1552 | output_invalid (*l)); | |
1553 | return NULL; | |
1554 | } | |
1555 | if (token_start == l) | |
1556 | { | |
1557 | if (*l == PREFIX_SEPARATOR) | |
1558 | as_bad (_("expecting prefix; got nothing")); | |
1559 | else | |
1560 | as_bad (_("expecting mnemonic; got nothing")); | |
1561 | return NULL; | |
1562 | } | |
45288df1 | 1563 | |
29b0f896 AM |
1564 | /* Look up instruction (or prefix) via hash table. */ |
1565 | current_templates = hash_find (op_hash, mnemonic); | |
47926f60 | 1566 | |
29b0f896 AM |
1567 | if (*l != END_OF_INSN |
1568 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
1569 | && current_templates | |
1570 | && (current_templates->start->opcode_modifier & IsPrefix)) | |
1571 | { | |
1572 | /* If we are in 16-bit mode, do not allow addr16 or data16. | |
1573 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
1574 | if ((current_templates->start->opcode_modifier & (Size16 | Size32)) | |
1575 | && flag_code != CODE_64BIT | |
1576 | && (((current_templates->start->opcode_modifier & Size32) != 0) | |
1577 | ^ (flag_code == CODE_16BIT))) | |
1578 | { | |
1579 | as_bad (_("redundant %s prefix"), | |
1580 | current_templates->start->name); | |
1581 | return NULL; | |
45288df1 | 1582 | } |
29b0f896 AM |
1583 | /* Add prefix, checking for repeated prefixes. */ |
1584 | switch (add_prefix (current_templates->start->base_opcode)) | |
1585 | { | |
1586 | case 0: | |
1587 | return NULL; | |
1588 | case 2: | |
1589 | expecting_string_instruction = current_templates->start->name; | |
1590 | break; | |
1591 | } | |
1592 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
1593 | token_start = ++l; | |
1594 | } | |
1595 | else | |
1596 | break; | |
1597 | } | |
45288df1 | 1598 | |
29b0f896 AM |
1599 | if (!current_templates) |
1600 | { | |
1601 | /* See if we can get a match by trimming off a suffix. */ | |
1602 | switch (mnem_p[-1]) | |
1603 | { | |
1604 | case WORD_MNEM_SUFFIX: | |
1605 | case BYTE_MNEM_SUFFIX: | |
1606 | case QWORD_MNEM_SUFFIX: | |
1607 | i.suffix = mnem_p[-1]; | |
1608 | mnem_p[-1] = '\0'; | |
1609 | current_templates = hash_find (op_hash, mnemonic); | |
1610 | break; | |
1611 | case SHORT_MNEM_SUFFIX: | |
1612 | case LONG_MNEM_SUFFIX: | |
1613 | if (!intel_syntax) | |
1614 | { | |
1615 | i.suffix = mnem_p[-1]; | |
1616 | mnem_p[-1] = '\0'; | |
1617 | current_templates = hash_find (op_hash, mnemonic); | |
1618 | } | |
1619 | break; | |
252b5132 | 1620 | |
29b0f896 AM |
1621 | /* Intel Syntax. */ |
1622 | case 'd': | |
1623 | if (intel_syntax) | |
1624 | { | |
1625 | if (intel_float_operand (mnemonic)) | |
1626 | i.suffix = SHORT_MNEM_SUFFIX; | |
1627 | else | |
1628 | i.suffix = LONG_MNEM_SUFFIX; | |
1629 | mnem_p[-1] = '\0'; | |
1630 | current_templates = hash_find (op_hash, mnemonic); | |
1631 | } | |
1632 | break; | |
1633 | } | |
1634 | if (!current_templates) | |
1635 | { | |
1636 | as_bad (_("no such instruction: `%s'"), token_start); | |
1637 | return NULL; | |
1638 | } | |
1639 | } | |
252b5132 | 1640 | |
29b0f896 AM |
1641 | if (current_templates->start->opcode_modifier & (Jump | JumpByte)) |
1642 | { | |
1643 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
1644 | predict taken and predict not taken respectively. | |
1645 | I'm not sure that branch hints actually do anything on loop | |
1646 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
1647 | may work in the future and it doesn't hurt to accept them | |
1648 | now. */ | |
1649 | if (l[0] == ',' && l[1] == 'p') | |
1650 | { | |
1651 | if (l[2] == 't') | |
1652 | { | |
1653 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
1654 | return NULL; | |
1655 | l += 3; | |
1656 | } | |
1657 | else if (l[2] == 'n') | |
1658 | { | |
1659 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
1660 | return NULL; | |
1661 | l += 3; | |
1662 | } | |
1663 | } | |
1664 | } | |
1665 | /* Any other comma loses. */ | |
1666 | if (*l == ',') | |
1667 | { | |
1668 | as_bad (_("invalid character %s in mnemonic"), | |
1669 | output_invalid (*l)); | |
1670 | return NULL; | |
1671 | } | |
252b5132 | 1672 | |
29b0f896 AM |
1673 | /* Check if instruction is supported on specified architecture. */ |
1674 | if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64)) | |
1675 | & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))) | |
1676 | { | |
1677 | as_warn (_("`%s' is not supported on `%s'"), | |
1678 | current_templates->start->name, cpu_arch_name); | |
1679 | } | |
1680 | else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT)) | |
1681 | { | |
1682 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
1683 | } | |
252b5132 | 1684 | |
29b0f896 AM |
1685 | /* Check for rep/repne without a string instruction. */ |
1686 | if (expecting_string_instruction | |
1687 | && !(current_templates->start->opcode_modifier & IsString)) | |
1688 | { | |
1689 | as_bad (_("expecting string instruction after `%s'"), | |
1690 | expecting_string_instruction); | |
1691 | return NULL; | |
1692 | } | |
252b5132 | 1693 | |
29b0f896 AM |
1694 | return l; |
1695 | } | |
252b5132 | 1696 | |
29b0f896 AM |
1697 | static char * |
1698 | parse_operands (l, mnemonic) | |
1699 | char *l; | |
1700 | const char *mnemonic; | |
1701 | { | |
1702 | char *token_start; | |
3138f287 | 1703 | |
29b0f896 AM |
1704 | /* 1 if operand is pending after ','. */ |
1705 | unsigned int expecting_operand = 0; | |
252b5132 | 1706 | |
29b0f896 AM |
1707 | /* Non-zero if operand parens not balanced. */ |
1708 | unsigned int paren_not_balanced; | |
1709 | ||
1710 | while (*l != END_OF_INSN) | |
1711 | { | |
1712 | /* Skip optional white space before operand. */ | |
1713 | if (is_space_char (*l)) | |
1714 | ++l; | |
1715 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
1716 | { | |
1717 | as_bad (_("invalid character %s before operand %d"), | |
1718 | output_invalid (*l), | |
1719 | i.operands + 1); | |
1720 | return NULL; | |
1721 | } | |
1722 | token_start = l; /* after white space */ | |
1723 | paren_not_balanced = 0; | |
1724 | while (paren_not_balanced || *l != ',') | |
1725 | { | |
1726 | if (*l == END_OF_INSN) | |
1727 | { | |
1728 | if (paren_not_balanced) | |
1729 | { | |
1730 | if (!intel_syntax) | |
1731 | as_bad (_("unbalanced parenthesis in operand %d."), | |
1732 | i.operands + 1); | |
1733 | else | |
1734 | as_bad (_("unbalanced brackets in operand %d."), | |
1735 | i.operands + 1); | |
1736 | return NULL; | |
1737 | } | |
1738 | else | |
1739 | break; /* we are done */ | |
1740 | } | |
1741 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
1742 | { | |
1743 | as_bad (_("invalid character %s in operand %d"), | |
1744 | output_invalid (*l), | |
1745 | i.operands + 1); | |
1746 | return NULL; | |
1747 | } | |
1748 | if (!intel_syntax) | |
1749 | { | |
1750 | if (*l == '(') | |
1751 | ++paren_not_balanced; | |
1752 | if (*l == ')') | |
1753 | --paren_not_balanced; | |
1754 | } | |
1755 | else | |
1756 | { | |
1757 | if (*l == '[') | |
1758 | ++paren_not_balanced; | |
1759 | if (*l == ']') | |
1760 | --paren_not_balanced; | |
1761 | } | |
1762 | l++; | |
1763 | } | |
1764 | if (l != token_start) | |
1765 | { /* Yes, we've read in another operand. */ | |
1766 | unsigned int operand_ok; | |
1767 | this_operand = i.operands++; | |
1768 | if (i.operands > MAX_OPERANDS) | |
1769 | { | |
1770 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
1771 | MAX_OPERANDS); | |
1772 | return NULL; | |
1773 | } | |
1774 | /* Now parse operand adding info to 'i' as we go along. */ | |
1775 | END_STRING_AND_SAVE (l); | |
1776 | ||
1777 | if (intel_syntax) | |
1778 | operand_ok = | |
1779 | i386_intel_operand (token_start, | |
1780 | intel_float_operand (mnemonic)); | |
1781 | else | |
1782 | operand_ok = i386_operand (token_start); | |
1783 | ||
1784 | RESTORE_END_STRING (l); | |
1785 | if (!operand_ok) | |
1786 | return NULL; | |
1787 | } | |
1788 | else | |
1789 | { | |
1790 | if (expecting_operand) | |
1791 | { | |
1792 | expecting_operand_after_comma: | |
1793 | as_bad (_("expecting operand after ','; got nothing")); | |
1794 | return NULL; | |
1795 | } | |
1796 | if (*l == ',') | |
1797 | { | |
1798 | as_bad (_("expecting operand before ','; got nothing")); | |
1799 | return NULL; | |
1800 | } | |
1801 | } | |
7f3f1ea2 | 1802 | |
29b0f896 AM |
1803 | /* Now *l must be either ',' or END_OF_INSN. */ |
1804 | if (*l == ',') | |
1805 | { | |
1806 | if (*++l == END_OF_INSN) | |
1807 | { | |
1808 | /* Just skip it, if it's \n complain. */ | |
1809 | goto expecting_operand_after_comma; | |
1810 | } | |
1811 | expecting_operand = 1; | |
1812 | } | |
1813 | } | |
1814 | return l; | |
1815 | } | |
7f3f1ea2 | 1816 | |
29b0f896 AM |
1817 | static void |
1818 | swap_operands () | |
1819 | { | |
1820 | union i386_op temp_op; | |
1821 | unsigned int temp_type; | |
1822 | RELOC_ENUM temp_reloc; | |
1823 | int xchg1 = 0; | |
1824 | int xchg2 = 0; | |
252b5132 | 1825 | |
29b0f896 AM |
1826 | if (i.operands == 2) |
1827 | { | |
1828 | xchg1 = 0; | |
1829 | xchg2 = 1; | |
1830 | } | |
1831 | else if (i.operands == 3) | |
1832 | { | |
1833 | xchg1 = 0; | |
1834 | xchg2 = 2; | |
1835 | } | |
1836 | temp_type = i.types[xchg2]; | |
1837 | i.types[xchg2] = i.types[xchg1]; | |
1838 | i.types[xchg1] = temp_type; | |
1839 | temp_op = i.op[xchg2]; | |
1840 | i.op[xchg2] = i.op[xchg1]; | |
1841 | i.op[xchg1] = temp_op; | |
1842 | temp_reloc = i.reloc[xchg2]; | |
1843 | i.reloc[xchg2] = i.reloc[xchg1]; | |
1844 | i.reloc[xchg1] = temp_reloc; | |
1845 | ||
1846 | if (i.mem_operands == 2) | |
1847 | { | |
1848 | const seg_entry *temp_seg; | |
1849 | temp_seg = i.seg[0]; | |
1850 | i.seg[0] = i.seg[1]; | |
1851 | i.seg[1] = temp_seg; | |
1852 | } | |
1853 | } | |
252b5132 | 1854 | |
29b0f896 AM |
1855 | /* Try to ensure constant immediates are represented in the smallest |
1856 | opcode possible. */ | |
1857 | static void | |
1858 | optimize_imm () | |
1859 | { | |
1860 | char guess_suffix = 0; | |
1861 | int op; | |
252b5132 | 1862 | |
29b0f896 AM |
1863 | if (i.suffix) |
1864 | guess_suffix = i.suffix; | |
1865 | else if (i.reg_operands) | |
1866 | { | |
1867 | /* Figure out a suffix from the last register operand specified. | |
1868 | We can't do this properly yet, ie. excluding InOutPortReg, | |
1869 | but the following works for instructions with immediates. | |
1870 | In any case, we can't set i.suffix yet. */ | |
1871 | for (op = i.operands; --op >= 0;) | |
1872 | if (i.types[op] & Reg) | |
252b5132 | 1873 | { |
29b0f896 AM |
1874 | if (i.types[op] & Reg8) |
1875 | guess_suffix = BYTE_MNEM_SUFFIX; | |
1876 | else if (i.types[op] & Reg16) | |
1877 | guess_suffix = WORD_MNEM_SUFFIX; | |
1878 | else if (i.types[op] & Reg32) | |
1879 | guess_suffix = LONG_MNEM_SUFFIX; | |
1880 | else if (i.types[op] & Reg64) | |
1881 | guess_suffix = QWORD_MNEM_SUFFIX; | |
1882 | break; | |
252b5132 | 1883 | } |
29b0f896 AM |
1884 | } |
1885 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
1886 | guess_suffix = WORD_MNEM_SUFFIX; | |
1887 | ||
1888 | for (op = i.operands; --op >= 0;) | |
1889 | if (i.types[op] & Imm) | |
1890 | { | |
1891 | switch (i.op[op].imms->X_op) | |
252b5132 | 1892 | { |
29b0f896 AM |
1893 | case O_constant: |
1894 | /* If a suffix is given, this operand may be shortened. */ | |
1895 | switch (guess_suffix) | |
252b5132 | 1896 | { |
29b0f896 AM |
1897 | case LONG_MNEM_SUFFIX: |
1898 | i.types[op] |= Imm32 | Imm64; | |
1899 | break; | |
1900 | case WORD_MNEM_SUFFIX: | |
1901 | i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64; | |
1902 | break; | |
1903 | case BYTE_MNEM_SUFFIX: | |
1904 | i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64; | |
1905 | break; | |
252b5132 | 1906 | } |
252b5132 | 1907 | |
29b0f896 AM |
1908 | /* If this operand is at most 16 bits, convert it |
1909 | to a signed 16 bit number before trying to see | |
1910 | whether it will fit in an even smaller size. | |
1911 | This allows a 16-bit operand such as $0xffe0 to | |
1912 | be recognised as within Imm8S range. */ | |
1913 | if ((i.types[op] & Imm16) | |
1914 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) | |
252b5132 | 1915 | { |
29b0f896 AM |
1916 | i.op[op].imms->X_add_number = |
1917 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
1918 | } | |
1919 | if ((i.types[op] & Imm32) | |
1920 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) | |
1921 | == 0)) | |
1922 | { | |
1923 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
1924 | ^ ((offsetT) 1 << 31)) | |
1925 | - ((offsetT) 1 << 31)); | |
1926 | } | |
1927 | i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number); | |
252b5132 | 1928 | |
29b0f896 AM |
1929 | /* We must avoid matching of Imm32 templates when 64bit |
1930 | only immediate is available. */ | |
1931 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
1932 | i.types[op] &= ~Imm32; | |
1933 | break; | |
252b5132 | 1934 | |
29b0f896 AM |
1935 | case O_absent: |
1936 | case O_register: | |
1937 | abort (); | |
1938 | ||
1939 | /* Symbols and expressions. */ | |
1940 | default: | |
1941 | /* Convert symbolic operand to proper sizes for matching. */ | |
1942 | switch (guess_suffix) | |
1943 | { | |
1944 | case QWORD_MNEM_SUFFIX: | |
1945 | i.types[op] = Imm64 | Imm32S; | |
1946 | break; | |
1947 | case LONG_MNEM_SUFFIX: | |
1948 | i.types[op] = Imm32 | Imm64; | |
1949 | break; | |
1950 | case WORD_MNEM_SUFFIX: | |
1951 | i.types[op] = Imm16 | Imm32 | Imm64; | |
1952 | break; | |
1953 | break; | |
1954 | case BYTE_MNEM_SUFFIX: | |
1955 | i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32; | |
1956 | break; | |
1957 | break; | |
252b5132 | 1958 | } |
29b0f896 | 1959 | break; |
252b5132 | 1960 | } |
29b0f896 AM |
1961 | } |
1962 | } | |
47926f60 | 1963 | |
29b0f896 AM |
1964 | /* Try to use the smallest displacement type too. */ |
1965 | static void | |
1966 | optimize_disp () | |
1967 | { | |
1968 | int op; | |
3e73aa7c | 1969 | |
29b0f896 AM |
1970 | for (op = i.operands; --op >= 0;) |
1971 | if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant) | |
252b5132 | 1972 | { |
29b0f896 AM |
1973 | offsetT disp = i.op[op].disps->X_add_number; |
1974 | ||
1975 | if (i.types[op] & Disp16) | |
252b5132 | 1976 | { |
29b0f896 AM |
1977 | /* We know this operand is at most 16 bits, so |
1978 | convert to a signed 16 bit number before trying | |
1979 | to see whether it will fit in an even smaller | |
1980 | size. */ | |
1981 | ||
1982 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); | |
252b5132 | 1983 | } |
29b0f896 | 1984 | else if (i.types[op] & Disp32) |
252b5132 | 1985 | { |
29b0f896 AM |
1986 | /* We know this operand is at most 32 bits, so convert to a |
1987 | signed 32 bit number before trying to see whether it will | |
1988 | fit in an even smaller size. */ | |
1989 | disp &= (((offsetT) 2 << 31) - 1); | |
1990 | disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 1991 | } |
29b0f896 | 1992 | if (flag_code == CODE_64BIT) |
252b5132 | 1993 | { |
29b0f896 AM |
1994 | if (fits_in_signed_long (disp)) |
1995 | i.types[op] |= Disp32S; | |
1996 | if (fits_in_unsigned_long (disp)) | |
1997 | i.types[op] |= Disp32; | |
252b5132 | 1998 | } |
29b0f896 AM |
1999 | if ((i.types[op] & (Disp32 | Disp32S | Disp16)) |
2000 | && fits_in_signed_byte (disp)) | |
2001 | i.types[op] |= Disp8; | |
252b5132 | 2002 | } |
29b0f896 AM |
2003 | } |
2004 | ||
2005 | static int | |
2006 | match_template () | |
2007 | { | |
2008 | /* Points to template once we've found it. */ | |
2009 | const template *t; | |
2010 | unsigned int overlap0, overlap1, overlap2; | |
2011 | unsigned int found_reverse_match; | |
2012 | int suffix_check; | |
2013 | ||
2014 | #define MATCH(overlap, given, template) \ | |
2015 | ((overlap & ~JumpAbsolute) \ | |
2016 | && (((given) & (BaseIndex | JumpAbsolute)) \ | |
2017 | == ((overlap) & (BaseIndex | JumpAbsolute)))) | |
2018 | ||
2019 | /* If given types r0 and r1 are registers they must be of the same type | |
2020 | unless the expected operand type register overlap is null. | |
2021 | Note that Acc in a template matches every size of reg. */ | |
2022 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ | |
2023 | (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \ | |
2024 | || ((g0) & Reg) == ((g1) & Reg) \ | |
2025 | || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) | |
2026 | ||
2027 | overlap0 = 0; | |
2028 | overlap1 = 0; | |
2029 | overlap2 = 0; | |
2030 | found_reverse_match = 0; | |
2031 | suffix_check = (i.suffix == BYTE_MNEM_SUFFIX | |
2032 | ? No_bSuf | |
2033 | : (i.suffix == WORD_MNEM_SUFFIX | |
2034 | ? No_wSuf | |
2035 | : (i.suffix == SHORT_MNEM_SUFFIX | |
2036 | ? No_sSuf | |
2037 | : (i.suffix == LONG_MNEM_SUFFIX | |
2038 | ? No_lSuf | |
2039 | : (i.suffix == QWORD_MNEM_SUFFIX | |
2040 | ? No_qSuf | |
2041 | : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX | |
2042 | ? No_xSuf : 0)))))); | |
2043 | ||
2044 | for (t = current_templates->start; | |
2045 | t < current_templates->end; | |
2046 | t++) | |
2047 | { | |
2048 | /* Must have right number of operands. */ | |
2049 | if (i.operands != t->operands) | |
2050 | continue; | |
2051 | ||
2052 | /* Check the suffix, except for some instructions in intel mode. */ | |
2053 | if ((t->opcode_modifier & suffix_check) | |
2054 | && !(intel_syntax | |
2055 | && (t->opcode_modifier & IgnoreSize)) | |
2056 | && !(intel_syntax | |
2057 | && t->base_opcode == 0xd9 | |
2058 | && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */ | |
2059 | || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */ | |
2060 | continue; | |
2061 | ||
2062 | /* Do not verify operands when there are none. */ | |
2063 | else if (!t->operands) | |
2064 | { | |
2065 | if (t->cpu_flags & ~cpu_arch_flags) | |
2066 | continue; | |
2067 | /* We've found a match; break out of loop. */ | |
2068 | break; | |
2069 | } | |
252b5132 | 2070 | |
29b0f896 AM |
2071 | overlap0 = i.types[0] & t->operand_types[0]; |
2072 | switch (t->operands) | |
2073 | { | |
2074 | case 1: | |
2075 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])) | |
2076 | continue; | |
2077 | break; | |
2078 | case 2: | |
2079 | case 3: | |
2080 | overlap1 = i.types[1] & t->operand_types[1]; | |
2081 | if (!MATCH (overlap0, i.types[0], t->operand_types[0]) | |
2082 | || !MATCH (overlap1, i.types[1], t->operand_types[1]) | |
2083 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
2084 | t->operand_types[0], | |
2085 | overlap1, i.types[1], | |
2086 | t->operand_types[1])) | |
2087 | { | |
2088 | /* Check if other direction is valid ... */ | |
2089 | if ((t->opcode_modifier & (D | FloatD)) == 0) | |
2090 | continue; | |
2091 | ||
2092 | /* Try reversing direction of operands. */ | |
2093 | overlap0 = i.types[0] & t->operand_types[1]; | |
2094 | overlap1 = i.types[1] & t->operand_types[0]; | |
2095 | if (!MATCH (overlap0, i.types[0], t->operand_types[1]) | |
2096 | || !MATCH (overlap1, i.types[1], t->operand_types[0]) | |
2097 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
2098 | t->operand_types[1], | |
2099 | overlap1, i.types[1], | |
2100 | t->operand_types[0])) | |
2101 | { | |
2102 | /* Does not match either direction. */ | |
2103 | continue; | |
2104 | } | |
2105 | /* found_reverse_match holds which of D or FloatDR | |
2106 | we've found. */ | |
2107 | found_reverse_match = t->opcode_modifier & (D | FloatDR); | |
2108 | } | |
2109 | /* Found a forward 2 operand match here. */ | |
2110 | else if (t->operands == 3) | |
2111 | { | |
2112 | /* Here we make use of the fact that there are no | |
2113 | reverse match 3 operand instructions, and all 3 | |
2114 | operand instructions only need to be checked for | |
2115 | register consistency between operands 2 and 3. */ | |
2116 | overlap2 = i.types[2] & t->operand_types[2]; | |
2117 | if (!MATCH (overlap2, i.types[2], t->operand_types[2]) | |
2118 | || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], | |
2119 | t->operand_types[1], | |
2120 | overlap2, i.types[2], | |
2121 | t->operand_types[2])) | |
2122 | ||
2123 | continue; | |
2124 | } | |
2125 | /* Found either forward/reverse 2 or 3 operand match here: | |
2126 | slip through to break. */ | |
2127 | } | |
2128 | if (t->cpu_flags & ~cpu_arch_flags) | |
2129 | { | |
2130 | found_reverse_match = 0; | |
2131 | continue; | |
2132 | } | |
2133 | /* We've found a match; break out of loop. */ | |
2134 | break; | |
2135 | } | |
2136 | ||
2137 | if (t == current_templates->end) | |
2138 | { | |
2139 | /* We found no match. */ | |
2140 | as_bad (_("suffix or operands invalid for `%s'"), | |
2141 | current_templates->start->name); | |
2142 | return 0; | |
2143 | } | |
252b5132 | 2144 | |
29b0f896 AM |
2145 | if (!quiet_warnings) |
2146 | { | |
2147 | if (!intel_syntax | |
2148 | && ((i.types[0] & JumpAbsolute) | |
2149 | != (t->operand_types[0] & JumpAbsolute))) | |
2150 | { | |
2151 | as_warn (_("indirect %s without `*'"), t->name); | |
2152 | } | |
2153 | ||
2154 | if ((t->opcode_modifier & (IsPrefix | IgnoreSize)) | |
2155 | == (IsPrefix | IgnoreSize)) | |
2156 | { | |
2157 | /* Warn them that a data or address size prefix doesn't | |
2158 | affect assembly of the next line of code. */ | |
2159 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
2160 | } | |
2161 | } | |
2162 | ||
2163 | /* Copy the template we found. */ | |
2164 | i.tm = *t; | |
2165 | if (found_reverse_match) | |
2166 | { | |
2167 | /* If we found a reverse match we must alter the opcode | |
2168 | direction bit. found_reverse_match holds bits to change | |
2169 | (different for int & float insns). */ | |
2170 | ||
2171 | i.tm.base_opcode ^= found_reverse_match; | |
2172 | ||
2173 | i.tm.operand_types[0] = t->operand_types[1]; | |
2174 | i.tm.operand_types[1] = t->operand_types[0]; | |
2175 | } | |
2176 | ||
2177 | return 1; | |
2178 | } | |
2179 | ||
2180 | static int | |
2181 | check_string () | |
2182 | { | |
2183 | int mem_op = (i.types[0] & AnyMem) ? 0 : 1; | |
2184 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) | |
2185 | { | |
2186 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
2187 | { | |
2188 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
2189 | i.tm.name, | |
2190 | mem_op + 1); | |
2191 | return 0; | |
2192 | } | |
2193 | /* There's only ever one segment override allowed per instruction. | |
2194 | This instruction possibly has a legal segment override on the | |
2195 | second operand, so copy the segment to where non-string | |
2196 | instructions store it, allowing common code. */ | |
2197 | i.seg[0] = i.seg[1]; | |
2198 | } | |
2199 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) | |
2200 | { | |
2201 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
2202 | { | |
2203 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
2204 | i.tm.name, | |
2205 | mem_op + 2); | |
2206 | return 0; | |
2207 | } | |
2208 | } | |
2209 | return 1; | |
2210 | } | |
2211 | ||
2212 | static int | |
2213 | process_suffix () | |
2214 | { | |
2215 | /* If matched instruction specifies an explicit instruction mnemonic | |
2216 | suffix, use it. */ | |
2217 | if (i.tm.opcode_modifier & (Size16 | Size32 | Size64)) | |
2218 | { | |
2219 | if (i.tm.opcode_modifier & Size16) | |
2220 | i.suffix = WORD_MNEM_SUFFIX; | |
2221 | else if (i.tm.opcode_modifier & Size64) | |
2222 | i.suffix = QWORD_MNEM_SUFFIX; | |
2223 | else | |
2224 | i.suffix = LONG_MNEM_SUFFIX; | |
2225 | } | |
2226 | else if (i.reg_operands) | |
2227 | { | |
2228 | /* If there's no instruction mnemonic suffix we try to invent one | |
2229 | based on register operands. */ | |
2230 | if (!i.suffix) | |
2231 | { | |
2232 | /* We take i.suffix from the last register operand specified, | |
2233 | Destination register type is more significant than source | |
2234 | register type. */ | |
2235 | int op; | |
2236 | for (op = i.operands; --op >= 0;) | |
2237 | if ((i.types[op] & Reg) | |
2238 | && !(i.tm.operand_types[op] & InOutPortReg)) | |
2239 | { | |
2240 | i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : | |
2241 | (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : | |
2242 | (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX : | |
2243 | LONG_MNEM_SUFFIX); | |
2244 | break; | |
2245 | } | |
2246 | } | |
2247 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
2248 | { | |
2249 | if (!check_byte_reg ()) | |
2250 | return 0; | |
2251 | } | |
2252 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
2253 | { | |
2254 | if (!check_long_reg ()) | |
2255 | return 0; | |
2256 | } | |
2257 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
2258 | { | |
2259 | if (!check_qword_reg ()) | |
2260 | return 0; | |
2261 | } | |
2262 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
2263 | { | |
2264 | if (!check_word_reg ()) | |
2265 | return 0; | |
2266 | } | |
2267 | else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize)) | |
2268 | /* Do nothing if the instruction is going to ignore the prefix. */ | |
2269 | ; | |
2270 | else | |
2271 | abort (); | |
2272 | } | |
2273 | else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix) | |
2274 | { | |
2275 | i.suffix = stackop_size; | |
2276 | } | |
252b5132 | 2277 | |
29b0f896 AM |
2278 | /* Change the opcode based on the operand size given by i.suffix; |
2279 | We need not change things for byte insns. */ | |
252b5132 | 2280 | |
29b0f896 AM |
2281 | if (!i.suffix && (i.tm.opcode_modifier & W)) |
2282 | { | |
2283 | as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); | |
2284 | return 0; | |
2285 | } | |
252b5132 | 2286 | |
29b0f896 AM |
2287 | if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) |
2288 | { | |
2289 | /* It's not a byte, select word/dword operation. */ | |
2290 | if (i.tm.opcode_modifier & W) | |
2291 | { | |
2292 | if (i.tm.opcode_modifier & ShortForm) | |
2293 | i.tm.base_opcode |= 8; | |
2294 | else | |
2295 | i.tm.base_opcode |= 1; | |
2296 | } | |
0f3f3d8b | 2297 | |
29b0f896 AM |
2298 | /* Now select between word & dword operations via the operand |
2299 | size prefix, except for instructions that will ignore this | |
2300 | prefix anyway. */ | |
2301 | if (i.suffix != QWORD_MNEM_SUFFIX | |
9146926a AM |
2302 | && !(i.tm.opcode_modifier & IgnoreSize) |
2303 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) | |
2304 | || (flag_code == CODE_64BIT | |
2305 | && (i.tm.opcode_modifier & JumpByte)))) | |
24eab124 AM |
2306 | { |
2307 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
29b0f896 AM |
2308 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ |
2309 | prefix = ADDR_PREFIX_OPCODE; | |
252b5132 | 2310 | |
29b0f896 AM |
2311 | if (!add_prefix (prefix)) |
2312 | return 0; | |
24eab124 | 2313 | } |
252b5132 | 2314 | |
29b0f896 AM |
2315 | /* Set mode64 for an operand. */ |
2316 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 2317 | && flag_code == CODE_64BIT |
29b0f896 | 2318 | && (i.tm.opcode_modifier & NoRex64) == 0) |
9146926a | 2319 | i.rex |= REX_MODE64; |
3e73aa7c | 2320 | |
29b0f896 AM |
2321 | /* Size floating point instruction. */ |
2322 | if (i.suffix == LONG_MNEM_SUFFIX) | |
2323 | { | |
2324 | if (i.tm.opcode_modifier & FloatMF) | |
2325 | i.tm.base_opcode ^= 4; | |
2326 | } | |
2327 | } | |
7ecd2f8b | 2328 | |
29b0f896 AM |
2329 | return 1; |
2330 | } | |
3e73aa7c | 2331 | |
29b0f896 AM |
2332 | static int |
2333 | check_byte_reg () | |
2334 | { | |
2335 | int op; | |
2336 | for (op = i.operands; --op >= 0;) | |
2337 | { | |
2338 | /* If this is an eight bit register, it's OK. If it's the 16 or | |
2339 | 32 bit version of an eight bit register, we will just use the | |
2340 | low portion, and that's OK too. */ | |
2341 | if (i.types[op] & Reg8) | |
2342 | continue; | |
2343 | ||
2344 | /* movzx and movsx should not generate this warning. */ | |
2345 | if (intel_syntax | |
2346 | && (i.tm.base_opcode == 0xfb7 | |
2347 | || i.tm.base_opcode == 0xfb6 | |
2348 | || i.tm.base_opcode == 0x63 | |
2349 | || i.tm.base_opcode == 0xfbe | |
2350 | || i.tm.base_opcode == 0xfbf)) | |
2351 | continue; | |
2352 | ||
2353 | if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4 | |
2354 | #if 0 | |
2355 | /* Check that the template allows eight bit regs. This | |
2356 | kills insns such as `orb $1,%edx', which maybe should be | |
2357 | allowed. */ | |
2358 | && (i.tm.operand_types[op] & (Reg8 | InOutPortReg)) | |
2359 | #endif | |
2360 | ) | |
2361 | { | |
2362 | /* Prohibit these changes in the 64bit mode, since the | |
2363 | lowering is more complicated. */ | |
2364 | if (flag_code == CODE_64BIT | |
2365 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
2366 | { | |
0f3f3d8b | 2367 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), |
29b0f896 AM |
2368 | i.op[op].regs->reg_name, |
2369 | i.suffix); | |
2370 | return 0; | |
2371 | } | |
2372 | #if REGISTER_WARNINGS | |
2373 | if (!quiet_warnings | |
2374 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
2375 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
2376 | (i.op[op].regs + (i.types[op] & Reg16 | |
2377 | ? REGNAM_AL - REGNAM_AX | |
2378 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
2379 | i.op[op].regs->reg_name, | |
2380 | i.suffix); | |
2381 | #endif | |
2382 | continue; | |
2383 | } | |
2384 | /* Any other register is bad. */ | |
2385 | if (i.types[op] & (Reg | RegMMX | RegXMM | |
2386 | | SReg2 | SReg3 | |
2387 | | Control | Debug | Test | |
2388 | | FloatReg | FloatAcc)) | |
2389 | { | |
2390 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
2391 | i.op[op].regs->reg_name, | |
2392 | i.tm.name, | |
2393 | i.suffix); | |
2394 | return 0; | |
2395 | } | |
2396 | } | |
2397 | return 1; | |
2398 | } | |
2399 | ||
2400 | static int | |
2401 | check_long_reg () | |
2402 | { | |
2403 | int op; | |
2404 | ||
2405 | for (op = i.operands; --op >= 0;) | |
2406 | /* Reject eight bit registers, except where the template requires | |
2407 | them. (eg. movzb) */ | |
2408 | if ((i.types[op] & Reg8) != 0 | |
2409 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) | |
2410 | { | |
2411 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
2412 | i.op[op].regs->reg_name, | |
2413 | i.tm.name, | |
2414 | i.suffix); | |
2415 | return 0; | |
2416 | } | |
2417 | /* Warn if the e prefix on a general reg is missing. */ | |
2418 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
2419 | && (i.types[op] & Reg16) != 0 | |
2420 | && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) | |
2421 | { | |
2422 | /* Prohibit these changes in the 64bit mode, since the | |
2423 | lowering is more complicated. */ | |
2424 | if (flag_code == CODE_64BIT) | |
252b5132 | 2425 | { |
0f3f3d8b | 2426 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), |
29b0f896 AM |
2427 | i.op[op].regs->reg_name, |
2428 | i.suffix); | |
2429 | return 0; | |
252b5132 | 2430 | } |
29b0f896 AM |
2431 | #if REGISTER_WARNINGS |
2432 | else | |
2433 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
2434 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
2435 | i.op[op].regs->reg_name, | |
2436 | i.suffix); | |
2437 | #endif | |
252b5132 | 2438 | } |
29b0f896 AM |
2439 | /* Warn if the r prefix on a general reg is missing. */ |
2440 | else if ((i.types[op] & Reg64) != 0 | |
2441 | && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) | |
252b5132 | 2442 | { |
0f3f3d8b | 2443 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), |
29b0f896 AM |
2444 | i.op[op].regs->reg_name, |
2445 | i.suffix); | |
2446 | return 0; | |
2447 | } | |
2448 | return 1; | |
2449 | } | |
252b5132 | 2450 | |
29b0f896 AM |
2451 | static int |
2452 | check_qword_reg () | |
2453 | { | |
2454 | int op; | |
252b5132 | 2455 | |
29b0f896 AM |
2456 | for (op = i.operands; --op >= 0; ) |
2457 | /* Reject eight bit registers, except where the template requires | |
2458 | them. (eg. movzb) */ | |
2459 | if ((i.types[op] & Reg8) != 0 | |
2460 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) | |
2461 | { | |
2462 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
2463 | i.op[op].regs->reg_name, | |
2464 | i.tm.name, | |
2465 | i.suffix); | |
2466 | return 0; | |
2467 | } | |
2468 | /* Warn if the e prefix on a general reg is missing. */ | |
2469 | else if (((i.types[op] & Reg16) != 0 | |
2470 | || (i.types[op] & Reg32) != 0) | |
2471 | && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) | |
2472 | { | |
2473 | /* Prohibit these changes in the 64bit mode, since the | |
2474 | lowering is more complicated. */ | |
0f3f3d8b | 2475 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), |
29b0f896 AM |
2476 | i.op[op].regs->reg_name, |
2477 | i.suffix); | |
2478 | return 0; | |
252b5132 | 2479 | } |
29b0f896 AM |
2480 | return 1; |
2481 | } | |
252b5132 | 2482 | |
29b0f896 AM |
2483 | static int |
2484 | check_word_reg () | |
2485 | { | |
2486 | int op; | |
2487 | for (op = i.operands; --op >= 0;) | |
2488 | /* Reject eight bit registers, except where the template requires | |
2489 | them. (eg. movzb) */ | |
2490 | if ((i.types[op] & Reg8) != 0 | |
2491 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) | |
2492 | { | |
2493 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
2494 | i.op[op].regs->reg_name, | |
2495 | i.tm.name, | |
2496 | i.suffix); | |
2497 | return 0; | |
2498 | } | |
2499 | /* Warn if the e prefix on a general reg is present. */ | |
2500 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
2501 | && (i.types[op] & Reg32) != 0 | |
2502 | && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0) | |
252b5132 | 2503 | { |
29b0f896 AM |
2504 | /* Prohibit these changes in the 64bit mode, since the |
2505 | lowering is more complicated. */ | |
2506 | if (flag_code == CODE_64BIT) | |
252b5132 | 2507 | { |
0f3f3d8b | 2508 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), |
29b0f896 AM |
2509 | i.op[op].regs->reg_name, |
2510 | i.suffix); | |
2511 | return 0; | |
252b5132 | 2512 | } |
29b0f896 AM |
2513 | else |
2514 | #if REGISTER_WARNINGS | |
2515 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
2516 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
2517 | i.op[op].regs->reg_name, | |
2518 | i.suffix); | |
2519 | #endif | |
2520 | } | |
2521 | return 1; | |
2522 | } | |
252b5132 | 2523 | |
29b0f896 AM |
2524 | static int |
2525 | finalize_imm () | |
2526 | { | |
2527 | unsigned int overlap0, overlap1, overlap2; | |
2528 | ||
2529 | overlap0 = i.types[0] & i.tm.operand_types[0]; | |
2530 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S)) | |
2531 | && overlap0 != Imm8 && overlap0 != Imm8S | |
2532 | && overlap0 != Imm16 && overlap0 != Imm32S | |
2533 | && overlap0 != Imm32 && overlap0 != Imm64) | |
2534 | { | |
2535 | if (i.suffix) | |
2536 | { | |
2537 | overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX | |
2538 | ? Imm8 | Imm8S | |
2539 | : (i.suffix == WORD_MNEM_SUFFIX | |
2540 | ? Imm16 | |
2541 | : (i.suffix == QWORD_MNEM_SUFFIX | |
2542 | ? Imm64 | Imm32S | |
2543 | : Imm32))); | |
2544 | } | |
2545 | else if (overlap0 == (Imm16 | Imm32S | Imm32) | |
2546 | || overlap0 == (Imm16 | Imm32) | |
2547 | || overlap0 == (Imm16 | Imm32S)) | |
2548 | { | |
2549 | overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) | |
2550 | ? Imm16 : Imm32S); | |
2551 | } | |
2552 | if (overlap0 != Imm8 && overlap0 != Imm8S | |
2553 | && overlap0 != Imm16 && overlap0 != Imm32S | |
2554 | && overlap0 != Imm32 && overlap0 != Imm64) | |
2555 | { | |
2556 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); | |
2557 | return 0; | |
2558 | } | |
2559 | } | |
2560 | i.types[0] = overlap0; | |
2561 | ||
2562 | overlap1 = i.types[1] & i.tm.operand_types[1]; | |
2563 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32)) | |
2564 | && overlap1 != Imm8 && overlap1 != Imm8S | |
2565 | && overlap1 != Imm16 && overlap1 != Imm32S | |
2566 | && overlap1 != Imm32 && overlap1 != Imm64) | |
2567 | { | |
2568 | if (i.suffix) | |
2569 | { | |
2570 | overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX | |
2571 | ? Imm8 | Imm8S | |
2572 | : (i.suffix == WORD_MNEM_SUFFIX | |
2573 | ? Imm16 | |
2574 | : (i.suffix == QWORD_MNEM_SUFFIX | |
2575 | ? Imm64 | Imm32S | |
2576 | : Imm32))); | |
2577 | } | |
2578 | else if (overlap1 == (Imm16 | Imm32 | Imm32S) | |
2579 | || overlap1 == (Imm16 | Imm32) | |
2580 | || overlap1 == (Imm16 | Imm32S)) | |
2581 | { | |
2582 | overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) | |
2583 | ? Imm16 : Imm32S); | |
2584 | } | |
2585 | if (overlap1 != Imm8 && overlap1 != Imm8S | |
2586 | && overlap1 != Imm16 && overlap1 != Imm32S | |
2587 | && overlap1 != Imm32 && overlap1 != Imm64) | |
2588 | { | |
2589 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix); | |
2590 | return 0; | |
2591 | } | |
2592 | } | |
2593 | i.types[1] = overlap1; | |
2594 | ||
2595 | overlap2 = i.types[2] & i.tm.operand_types[2]; | |
2596 | assert ((overlap2 & Imm) == 0); | |
2597 | i.types[2] = overlap2; | |
2598 | ||
2599 | return 1; | |
2600 | } | |
2601 | ||
2602 | static int | |
2603 | process_operands () | |
2604 | { | |
2605 | /* Default segment register this instruction will use for memory | |
2606 | accesses. 0 means unknown. This is only for optimizing out | |
2607 | unnecessary segment overrides. */ | |
2608 | const seg_entry *default_seg = 0; | |
2609 | ||
2610 | /* The imul $imm, %reg instruction is converted into | |
2611 | imul $imm, %reg, %reg, and the clr %reg instruction | |
2612 | is converted into xor %reg, %reg. */ | |
2613 | if (i.tm.opcode_modifier & regKludge) | |
2614 | { | |
2615 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; | |
2616 | /* Pretend we saw the extra register operand. */ | |
2617 | assert (i.op[first_reg_op + 1].regs == 0); | |
2618 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; | |
2619 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
2620 | i.reg_operands = 2; | |
2621 | } | |
2622 | ||
2623 | if (i.tm.opcode_modifier & ShortForm) | |
2624 | { | |
2625 | /* The register or float register operand is in operand 0 or 1. */ | |
2626 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; | |
2627 | /* Register goes in low 3 bits of opcode. */ | |
2628 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
2629 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
2630 | i.rex |= REX_EXTZ; | |
2631 | if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) | |
2632 | { | |
2633 | /* Warn about some common errors, but press on regardless. | |
2634 | The first case can be generated by gcc (<= 2.8.1). */ | |
2635 | if (i.operands == 2) | |
2636 | { | |
2637 | /* Reversed arguments on faddp, fsubp, etc. */ | |
2638 | as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, | |
2639 | i.op[1].regs->reg_name, | |
2640 | i.op[0].regs->reg_name); | |
2641 | } | |
2642 | else | |
2643 | { | |
2644 | /* Extraneous `l' suffix on fp insn. */ | |
2645 | as_warn (_("translating to `%s %%%s'"), i.tm.name, | |
2646 | i.op[0].regs->reg_name); | |
2647 | } | |
2648 | } | |
2649 | } | |
2650 | else if (i.tm.opcode_modifier & Modrm) | |
2651 | { | |
2652 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
2653 | must be put into the modrm byte). Now, we make the modrm and |
2654 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
2655 | |
2656 | default_seg = build_modrm_byte (); | |
2657 | } | |
2658 | else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) | |
2659 | { | |
2660 | if (i.tm.base_opcode == POP_SEG_SHORT | |
2661 | && i.op[0].regs->reg_num == 1) | |
2662 | { | |
2663 | as_bad (_("you can't `pop %%cs'")); | |
2664 | return 0; | |
2665 | } | |
2666 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
2667 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
2668 | i.rex |= REX_EXTZ; | |
2669 | } | |
2670 | else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32) | |
2671 | { | |
2672 | default_seg = &ds; | |
2673 | } | |
2674 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
2675 | { | |
2676 | /* For the string instructions that allow a segment override | |
2677 | on one of their operands, the default segment is ds. */ | |
2678 | default_seg = &ds; | |
2679 | } | |
2680 | ||
52271982 AM |
2681 | if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings) |
2682 | as_warn (_("segment override on `lea' is ineffectual")); | |
2683 | ||
2684 | /* If a segment was explicitly specified, and the specified segment | |
2685 | is not the default, use an opcode prefix to select it. If we | |
2686 | never figured out what the default segment is, then default_seg | |
2687 | will be zero at this point, and the specified segment prefix will | |
2688 | always be used. */ | |
29b0f896 AM |
2689 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
2690 | { | |
2691 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
2692 | return 0; | |
2693 | } | |
2694 | return 1; | |
2695 | } | |
2696 | ||
2697 | static const seg_entry * | |
2698 | build_modrm_byte () | |
2699 | { | |
2700 | const seg_entry *default_seg = 0; | |
2701 | ||
2702 | /* i.reg_operands MUST be the number of real register operands; | |
2703 | implicit registers do not count. */ | |
2704 | if (i.reg_operands == 2) | |
2705 | { | |
2706 | unsigned int source, dest; | |
2707 | source = ((i.types[0] | |
2708 | & (Reg | RegMMX | RegXMM | |
2709 | | SReg2 | SReg3 | |
2710 | | Control | Debug | Test)) | |
2711 | ? 0 : 1); | |
2712 | dest = source + 1; | |
2713 | ||
2714 | i.rm.mode = 3; | |
2715 | /* One of the register operands will be encoded in the i.tm.reg | |
2716 | field, the other in the combined i.tm.mode and i.tm.regmem | |
2717 | fields. If no form of this instruction supports a memory | |
2718 | destination operand, then we assume the source operand may | |
2719 | sometimes be a memory operand and so we need to store the | |
2720 | destination in the i.rm.reg field. */ | |
2721 | if ((i.tm.operand_types[dest] & AnyMem) == 0) | |
2722 | { | |
2723 | i.rm.reg = i.op[dest].regs->reg_num; | |
2724 | i.rm.regmem = i.op[source].regs->reg_num; | |
2725 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
2726 | i.rex |= REX_EXTX; | |
2727 | if ((i.op[source].regs->reg_flags & RegRex) != 0) | |
2728 | i.rex |= REX_EXTZ; | |
2729 | } | |
2730 | else | |
2731 | { | |
2732 | i.rm.reg = i.op[source].regs->reg_num; | |
2733 | i.rm.regmem = i.op[dest].regs->reg_num; | |
2734 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
2735 | i.rex |= REX_EXTZ; | |
2736 | if ((i.op[source].regs->reg_flags & RegRex) != 0) | |
2737 | i.rex |= REX_EXTX; | |
2738 | } | |
2739 | } | |
2740 | else | |
2741 | { /* If it's not 2 reg operands... */ | |
2742 | if (i.mem_operands) | |
2743 | { | |
2744 | unsigned int fake_zero_displacement = 0; | |
2745 | unsigned int op = ((i.types[0] & AnyMem) | |
2746 | ? 0 | |
2747 | : (i.types[1] & AnyMem) ? 1 : 2); | |
2748 | ||
2749 | default_seg = &ds; | |
2750 | ||
2751 | if (i.base_reg == 0) | |
2752 | { | |
2753 | i.rm.mode = 0; | |
2754 | if (!i.disp_operands) | |
2755 | fake_zero_displacement = 1; | |
2756 | if (i.index_reg == 0) | |
2757 | { | |
2758 | /* Operand is just <disp> */ | |
2759 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0) | |
2760 | && (flag_code != CODE_64BIT)) | |
2761 | { | |
2762 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2763 | i.types[op] &= ~Disp; | |
2764 | i.types[op] |= Disp16; | |
2765 | } | |
2766 | else if (flag_code != CODE_64BIT | |
2767 | || (i.prefix[ADDR_PREFIX] != 0)) | |
2768 | { | |
2769 | i.rm.regmem = NO_BASE_REGISTER; | |
2770 | i.types[op] &= ~Disp; | |
2771 | i.types[op] |= Disp32; | |
2772 | } | |
2773 | else | |
2774 | { | |
2775 | /* 64bit mode overwrites the 32bit absolute | |
2776 | addressing by RIP relative addressing and | |
2777 | absolute addressing is encoded by one of the | |
2778 | redundant SIB forms. */ | |
2779 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2780 | i.sib.base = NO_BASE_REGISTER; | |
2781 | i.sib.index = NO_INDEX_REGISTER; | |
2782 | i.types[op] &= ~Disp; | |
2783 | i.types[op] |= Disp32S; | |
2784 | } | |
2785 | } | |
2786 | else /* !i.base_reg && i.index_reg */ | |
2787 | { | |
2788 | i.sib.index = i.index_reg->reg_num; | |
2789 | i.sib.base = NO_BASE_REGISTER; | |
2790 | i.sib.scale = i.log2_scale_factor; | |
2791 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2792 | i.types[op] &= ~Disp; | |
2793 | if (flag_code != CODE_64BIT) | |
2794 | i.types[op] |= Disp32; /* Must be 32 bit */ | |
2795 | else | |
2796 | i.types[op] |= Disp32S; | |
2797 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
2798 | i.rex |= REX_EXTY; | |
2799 | } | |
2800 | } | |
2801 | /* RIP addressing for 64bit mode. */ | |
2802 | else if (i.base_reg->reg_type == BaseIndex) | |
2803 | { | |
2804 | i.rm.regmem = NO_BASE_REGISTER; | |
2805 | i.types[op] &= ~Disp; | |
2806 | i.types[op] |= Disp32S; | |
2807 | i.flags[op] = Operand_PCrel; | |
2808 | } | |
2809 | else if (i.base_reg->reg_type & Reg16) | |
2810 | { | |
2811 | switch (i.base_reg->reg_num) | |
2812 | { | |
2813 | case 3: /* (%bx) */ | |
2814 | if (i.index_reg == 0) | |
2815 | i.rm.regmem = 7; | |
2816 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
2817 | i.rm.regmem = i.index_reg->reg_num - 6; | |
2818 | break; | |
2819 | case 5: /* (%bp) */ | |
2820 | default_seg = &ss; | |
2821 | if (i.index_reg == 0) | |
2822 | { | |
2823 | i.rm.regmem = 6; | |
2824 | if ((i.types[op] & Disp) == 0) | |
2825 | { | |
2826 | /* fake (%bp) into 0(%bp) */ | |
2827 | i.types[op] |= Disp8; | |
252b5132 | 2828 | fake_zero_displacement = 1; |
29b0f896 AM |
2829 | } |
2830 | } | |
2831 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
2832 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
2833 | break; | |
2834 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
2835 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
2836 | } | |
2837 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2838 | } | |
2839 | else /* i.base_reg and 32/64 bit mode */ | |
2840 | { | |
2841 | if (flag_code == CODE_64BIT | |
2842 | && (i.types[op] & Disp)) | |
2843 | { | |
2844 | if (i.types[op] & Disp8) | |
2845 | i.types[op] = Disp8 | Disp32S; | |
2846 | else | |
2847 | i.types[op] = Disp32S; | |
2848 | } | |
2849 | i.rm.regmem = i.base_reg->reg_num; | |
2850 | if ((i.base_reg->reg_flags & RegRex) != 0) | |
2851 | i.rex |= REX_EXTZ; | |
2852 | i.sib.base = i.base_reg->reg_num; | |
2853 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
2854 | complications. */ | |
2855 | if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) | |
2856 | { | |
2857 | default_seg = &ss; | |
2858 | if (i.disp_operands == 0) | |
2859 | { | |
2860 | fake_zero_displacement = 1; | |
2861 | i.types[op] |= Disp8; | |
2862 | } | |
2863 | } | |
2864 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
2865 | { | |
2866 | default_seg = &ss; | |
2867 | } | |
2868 | i.sib.scale = i.log2_scale_factor; | |
2869 | if (i.index_reg == 0) | |
2870 | { | |
2871 | /* <disp>(%esp) becomes two byte modrm with no index | |
2872 | register. We've already stored the code for esp | |
2873 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
2874 | Any base register besides %esp will not use the | |
2875 | extra modrm byte. */ | |
2876 | i.sib.index = NO_INDEX_REGISTER; | |
2877 | #if !SCALE1_WHEN_NO_INDEX | |
2878 | /* Another case where we force the second modrm byte. */ | |
2879 | if (i.log2_scale_factor) | |
2880 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
252b5132 | 2881 | #endif |
29b0f896 AM |
2882 | } |
2883 | else | |
2884 | { | |
2885 | i.sib.index = i.index_reg->reg_num; | |
2886 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2887 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
2888 | i.rex |= REX_EXTY; | |
2889 | } | |
2890 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2891 | } | |
252b5132 | 2892 | |
29b0f896 AM |
2893 | if (fake_zero_displacement) |
2894 | { | |
2895 | /* Fakes a zero displacement assuming that i.types[op] | |
2896 | holds the correct displacement size. */ | |
2897 | expressionS *exp; | |
2898 | ||
2899 | assert (i.op[op].disps == 0); | |
2900 | exp = &disp_expressions[i.disp_operands++]; | |
2901 | i.op[op].disps = exp; | |
2902 | exp->X_op = O_constant; | |
2903 | exp->X_add_number = 0; | |
2904 | exp->X_add_symbol = (symbolS *) 0; | |
2905 | exp->X_op_symbol = (symbolS *) 0; | |
2906 | } | |
2907 | } | |
252b5132 | 2908 | |
29b0f896 AM |
2909 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
2910 | (if any) based on i.tm.extension_opcode. Again, we must be | |
2911 | careful to make sure that segment/control/debug/test/MMX | |
2912 | registers are coded into the i.rm.reg field. */ | |
2913 | if (i.reg_operands) | |
2914 | { | |
2915 | unsigned int op = | |
2916 | ((i.types[0] | |
2917 | & (Reg | RegMMX | RegXMM | |
2918 | | SReg2 | SReg3 | |
2919 | | Control | Debug | Test)) | |
2920 | ? 0 | |
2921 | : ((i.types[1] | |
2922 | & (Reg | RegMMX | RegXMM | |
2923 | | SReg2 | SReg3 | |
2924 | | Control | Debug | Test)) | |
2925 | ? 1 | |
2926 | : 2)); | |
2927 | /* If there is an extension opcode to put here, the register | |
2928 | number must be put into the regmem field. */ | |
2929 | if (i.tm.extension_opcode != None) | |
2930 | { | |
2931 | i.rm.regmem = i.op[op].regs->reg_num; | |
2932 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
2933 | i.rex |= REX_EXTZ; | |
2934 | } | |
2935 | else | |
2936 | { | |
2937 | i.rm.reg = i.op[op].regs->reg_num; | |
2938 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
2939 | i.rex |= REX_EXTX; | |
2940 | } | |
252b5132 | 2941 | |
29b0f896 AM |
2942 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
2943 | must set it to 3 to indicate this is a register operand | |
2944 | in the regmem field. */ | |
2945 | if (!i.mem_operands) | |
2946 | i.rm.mode = 3; | |
2947 | } | |
252b5132 | 2948 | |
29b0f896 AM |
2949 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
2950 | if (i.tm.extension_opcode != None) | |
2951 | i.rm.reg = i.tm.extension_opcode; | |
2952 | } | |
2953 | return default_seg; | |
2954 | } | |
252b5132 | 2955 | |
29b0f896 AM |
2956 | static void |
2957 | output_branch () | |
2958 | { | |
2959 | char *p; | |
2960 | int code16; | |
2961 | int prefix; | |
2962 | relax_substateT subtype; | |
2963 | symbolS *sym; | |
2964 | offsetT off; | |
2965 | ||
2966 | code16 = 0; | |
2967 | if (flag_code == CODE_16BIT) | |
2968 | code16 = CODE16; | |
2969 | ||
2970 | prefix = 0; | |
2971 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 2972 | { |
29b0f896 AM |
2973 | prefix = 1; |
2974 | i.prefixes -= 1; | |
2975 | code16 ^= CODE16; | |
252b5132 | 2976 | } |
29b0f896 AM |
2977 | /* Pentium4 branch hints. */ |
2978 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
2979 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 2980 | { |
29b0f896 AM |
2981 | prefix++; |
2982 | i.prefixes--; | |
2983 | } | |
2984 | if (i.prefix[REX_PREFIX] != 0) | |
2985 | { | |
2986 | prefix++; | |
2987 | i.prefixes--; | |
2f66722d AM |
2988 | } |
2989 | ||
29b0f896 AM |
2990 | if (i.prefixes != 0 && !intel_syntax) |
2991 | as_warn (_("skipping prefixes on this instruction")); | |
2992 | ||
2993 | /* It's always a symbol; End frag & setup for relax. | |
2994 | Make sure there is enough room in this frag for the largest | |
2995 | instruction we may generate in md_convert_frag. This is 2 | |
2996 | bytes for the opcode and room for the prefix and largest | |
2997 | displacement. */ | |
2998 | frag_grow (prefix + 2 + 4); | |
2999 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
3000 | p = frag_more (prefix + 1); | |
3001 | if (i.prefix[DATA_PREFIX] != 0) | |
3002 | *p++ = DATA_PREFIX_OPCODE; | |
3003 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
3004 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
3005 | *p++ = i.prefix[SEG_PREFIX]; | |
3006 | if (i.prefix[REX_PREFIX] != 0) | |
3007 | *p++ = i.prefix[REX_PREFIX]; | |
3008 | *p = i.tm.base_opcode; | |
3009 | ||
3010 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
3011 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL); | |
3012 | else if ((cpu_arch_flags & Cpu386) != 0) | |
3013 | subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL); | |
3014 | else | |
3015 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL); | |
3016 | subtype |= code16; | |
3e73aa7c | 3017 | |
29b0f896 AM |
3018 | sym = i.op[0].disps->X_add_symbol; |
3019 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 3020 | |
29b0f896 AM |
3021 | if (i.op[0].disps->X_op != O_constant |
3022 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 3023 | { |
29b0f896 AM |
3024 | /* Handle complex expressions. */ |
3025 | sym = make_expr_symbol (i.op[0].disps); | |
3026 | off = 0; | |
3027 | } | |
3e73aa7c | 3028 | |
29b0f896 AM |
3029 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
3030 | Pass reloc in fr_var. */ | |
3031 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); | |
3032 | } | |
3e73aa7c | 3033 | |
29b0f896 AM |
3034 | static void |
3035 | output_jump () | |
3036 | { | |
3037 | char *p; | |
3038 | int size; | |
3e02c1cc | 3039 | fixS *fixP; |
29b0f896 AM |
3040 | |
3041 | if (i.tm.opcode_modifier & JumpByte) | |
3042 | { | |
3043 | /* This is a loop or jecxz type instruction. */ | |
3044 | size = 1; | |
3045 | if (i.prefix[ADDR_PREFIX] != 0) | |
3046 | { | |
3047 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
3048 | i.prefixes -= 1; | |
3049 | } | |
3050 | /* Pentium4 branch hints. */ | |
3051 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
3052 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
3053 | { | |
3054 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
3055 | i.prefixes--; | |
3e73aa7c JH |
3056 | } |
3057 | } | |
29b0f896 AM |
3058 | else |
3059 | { | |
3060 | int code16; | |
3e73aa7c | 3061 | |
29b0f896 AM |
3062 | code16 = 0; |
3063 | if (flag_code == CODE_16BIT) | |
3064 | code16 = CODE16; | |
3e73aa7c | 3065 | |
29b0f896 AM |
3066 | if (i.prefix[DATA_PREFIX] != 0) |
3067 | { | |
3068 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
3069 | i.prefixes -= 1; | |
3070 | code16 ^= CODE16; | |
3071 | } | |
252b5132 | 3072 | |
29b0f896 AM |
3073 | size = 4; |
3074 | if (code16) | |
3075 | size = 2; | |
3076 | } | |
9fcc94b6 | 3077 | |
29b0f896 AM |
3078 | if (i.prefix[REX_PREFIX] != 0) |
3079 | { | |
3080 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
3081 | i.prefixes -= 1; | |
3082 | } | |
252b5132 | 3083 | |
29b0f896 AM |
3084 | if (i.prefixes != 0 && !intel_syntax) |
3085 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 3086 | |
29b0f896 AM |
3087 | p = frag_more (1 + size); |
3088 | *p++ = i.tm.base_opcode; | |
e0890092 | 3089 | |
3e02c1cc AM |
3090 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
3091 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); | |
3092 | ||
3093 | /* All jumps handled here are signed, but don't use a signed limit | |
3094 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
3095 | 4G and 64k respectively. */ | |
3096 | if (size == 1) | |
3097 | fixP->fx_signed = 1; | |
29b0f896 | 3098 | } |
e0890092 | 3099 | |
29b0f896 AM |
3100 | static void |
3101 | output_interseg_jump () | |
3102 | { | |
3103 | char *p; | |
3104 | int size; | |
3105 | int prefix; | |
3106 | int code16; | |
252b5132 | 3107 | |
29b0f896 AM |
3108 | code16 = 0; |
3109 | if (flag_code == CODE_16BIT) | |
3110 | code16 = CODE16; | |
a217f122 | 3111 | |
29b0f896 AM |
3112 | prefix = 0; |
3113 | if (i.prefix[DATA_PREFIX] != 0) | |
3114 | { | |
3115 | prefix = 1; | |
3116 | i.prefixes -= 1; | |
3117 | code16 ^= CODE16; | |
3118 | } | |
3119 | if (i.prefix[REX_PREFIX] != 0) | |
3120 | { | |
3121 | prefix++; | |
3122 | i.prefixes -= 1; | |
3123 | } | |
252b5132 | 3124 | |
29b0f896 AM |
3125 | size = 4; |
3126 | if (code16) | |
3127 | size = 2; | |
252b5132 | 3128 | |
29b0f896 AM |
3129 | if (i.prefixes != 0 && !intel_syntax) |
3130 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 3131 | |
29b0f896 AM |
3132 | /* 1 opcode; 2 segment; offset */ |
3133 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 3134 | |
29b0f896 AM |
3135 | if (i.prefix[DATA_PREFIX] != 0) |
3136 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 3137 | |
29b0f896 AM |
3138 | if (i.prefix[REX_PREFIX] != 0) |
3139 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 3140 | |
29b0f896 AM |
3141 | *p++ = i.tm.base_opcode; |
3142 | if (i.op[1].imms->X_op == O_constant) | |
3143 | { | |
3144 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 3145 | |
29b0f896 AM |
3146 | if (size == 2 |
3147 | && !fits_in_unsigned_word (n) | |
3148 | && !fits_in_signed_word (n)) | |
3149 | { | |
3150 | as_bad (_("16-bit jump out of range")); | |
3151 | return; | |
3152 | } | |
3153 | md_number_to_chars (p, n, size); | |
3154 | } | |
3155 | else | |
3156 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
3157 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); | |
3158 | if (i.op[0].imms->X_op != O_constant) | |
3159 | as_bad (_("can't handle non absolute segment in `%s'"), | |
3160 | i.tm.name); | |
3161 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
3162 | } | |
a217f122 | 3163 | |
2bbd9c25 | 3164 | |
29b0f896 AM |
3165 | static void |
3166 | output_insn () | |
3167 | { | |
2bbd9c25 JJ |
3168 | fragS *insn_start_frag; |
3169 | offsetT insn_start_off; | |
3170 | ||
29b0f896 AM |
3171 | /* Tie dwarf2 debug info to the address at the start of the insn. |
3172 | We can't do this after the insn has been output as the current | |
3173 | frag may have been closed off. eg. by frag_var. */ | |
3174 | dwarf2_emit_insn (0); | |
3175 | ||
2bbd9c25 JJ |
3176 | insn_start_frag = frag_now; |
3177 | insn_start_off = frag_now_fix (); | |
3178 | ||
29b0f896 AM |
3179 | /* Output jumps. */ |
3180 | if (i.tm.opcode_modifier & Jump) | |
3181 | output_branch (); | |
3182 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) | |
3183 | output_jump (); | |
3184 | else if (i.tm.opcode_modifier & JumpInterSegment) | |
3185 | output_interseg_jump (); | |
3186 | else | |
3187 | { | |
3188 | /* Output normal instructions here. */ | |
3189 | char *p; | |
3190 | unsigned char *q; | |
252b5132 | 3191 | |
29b0f896 AM |
3192 | /* All opcodes on i386 have either 1 or 2 bytes. We may use third |
3193 | byte for the SSE instructions to specify a prefix they require. */ | |
3194 | if (i.tm.base_opcode & 0xff0000) | |
3195 | add_prefix ((i.tm.base_opcode >> 16) & 0xff); | |
252b5132 | 3196 | |
29b0f896 AM |
3197 | /* The prefix bytes. */ |
3198 | for (q = i.prefix; | |
3199 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); | |
3200 | q++) | |
3201 | { | |
3202 | if (*q) | |
3203 | { | |
3204 | p = frag_more (1); | |
3205 | md_number_to_chars (p, (valueT) *q, 1); | |
3206 | } | |
3207 | } | |
252b5132 | 3208 | |
29b0f896 AM |
3209 | /* Now the opcode; be careful about word order here! */ |
3210 | if (fits_in_unsigned_byte (i.tm.base_opcode)) | |
3211 | { | |
3212 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
3213 | } | |
3214 | else | |
3215 | { | |
3216 | p = frag_more (2); | |
3217 | /* Put out high byte first: can't use md_number_to_chars! */ | |
3218 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
3219 | *p = i.tm.base_opcode & 0xff; | |
3220 | } | |
3e73aa7c | 3221 | |
29b0f896 AM |
3222 | /* Now the modrm byte and sib byte (if present). */ |
3223 | if (i.tm.opcode_modifier & Modrm) | |
3224 | { | |
3225 | p = frag_more (1); | |
3226 | md_number_to_chars (p, | |
3227 | (valueT) (i.rm.regmem << 0 | |
3228 | | i.rm.reg << 3 | |
3229 | | i.rm.mode << 6), | |
3230 | 1); | |
3231 | /* If i.rm.regmem == ESP (4) | |
3232 | && i.rm.mode != (Register mode) | |
3233 | && not 16 bit | |
3234 | ==> need second modrm byte. */ | |
3235 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
3236 | && i.rm.mode != 3 | |
3237 | && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) | |
3238 | { | |
3239 | p = frag_more (1); | |
3240 | md_number_to_chars (p, | |
3241 | (valueT) (i.sib.base << 0 | |
3242 | | i.sib.index << 3 | |
3243 | | i.sib.scale << 6), | |
3244 | 1); | |
3245 | } | |
3246 | } | |
3e73aa7c | 3247 | |
29b0f896 | 3248 | if (i.disp_operands) |
2bbd9c25 | 3249 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 3250 | |
29b0f896 | 3251 | if (i.imm_operands) |
2bbd9c25 | 3252 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 3253 | } |
252b5132 | 3254 | |
29b0f896 AM |
3255 | #ifdef DEBUG386 |
3256 | if (flag_debug) | |
3257 | { | |
3258 | pi (line, &i); | |
3259 | } | |
3260 | #endif /* DEBUG386 */ | |
3261 | } | |
252b5132 | 3262 | |
29b0f896 | 3263 | static void |
2bbd9c25 JJ |
3264 | output_disp (insn_start_frag, insn_start_off) |
3265 | fragS *insn_start_frag; | |
3266 | offsetT insn_start_off; | |
29b0f896 AM |
3267 | { |
3268 | char *p; | |
3269 | unsigned int n; | |
252b5132 | 3270 | |
29b0f896 AM |
3271 | for (n = 0; n < i.operands; n++) |
3272 | { | |
3273 | if (i.types[n] & Disp) | |
3274 | { | |
3275 | if (i.op[n].disps->X_op == O_constant) | |
3276 | { | |
3277 | int size; | |
3278 | offsetT val; | |
252b5132 | 3279 | |
29b0f896 AM |
3280 | size = 4; |
3281 | if (i.types[n] & (Disp8 | Disp16 | Disp64)) | |
3282 | { | |
3283 | size = 2; | |
3284 | if (i.types[n] & Disp8) | |
3285 | size = 1; | |
3286 | if (i.types[n] & Disp64) | |
3287 | size = 8; | |
3288 | } | |
3289 | val = offset_in_range (i.op[n].disps->X_add_number, | |
3290 | size); | |
3291 | p = frag_more (size); | |
3292 | md_number_to_chars (p, val, size); | |
3293 | } | |
3294 | else | |
3295 | { | |
2bbd9c25 | 3296 | RELOC_ENUM reloc_type; |
29b0f896 AM |
3297 | int size = 4; |
3298 | int sign = 0; | |
3299 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; | |
3300 | ||
3301 | /* The PC relative address is computed relative | |
3302 | to the instruction boundary, so in case immediate | |
3303 | fields follows, we need to adjust the value. */ | |
3304 | if (pcrel && i.imm_operands) | |
3305 | { | |
3306 | int imm_size = 4; | |
3307 | unsigned int n1; | |
252b5132 | 3308 | |
29b0f896 AM |
3309 | for (n1 = 0; n1 < i.operands; n1++) |
3310 | if (i.types[n1] & Imm) | |
252b5132 | 3311 | { |
29b0f896 | 3312 | if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64)) |
252b5132 | 3313 | { |
29b0f896 AM |
3314 | imm_size = 2; |
3315 | if (i.types[n1] & (Imm8 | Imm8S)) | |
3316 | imm_size = 1; | |
3317 | if (i.types[n1] & Imm64) | |
3318 | imm_size = 8; | |
252b5132 | 3319 | } |
29b0f896 | 3320 | break; |
252b5132 | 3321 | } |
29b0f896 AM |
3322 | /* We should find the immediate. */ |
3323 | if (n1 == i.operands) | |
3324 | abort (); | |
3325 | i.op[n].disps->X_add_number -= imm_size; | |
3326 | } | |
520dc8e8 | 3327 | |
29b0f896 AM |
3328 | if (i.types[n] & Disp32S) |
3329 | sign = 1; | |
3e73aa7c | 3330 | |
29b0f896 AM |
3331 | if (i.types[n] & (Disp16 | Disp64)) |
3332 | { | |
3333 | size = 2; | |
3334 | if (i.types[n] & Disp64) | |
3335 | size = 8; | |
3336 | } | |
520dc8e8 | 3337 | |
29b0f896 | 3338 | p = frag_more (size); |
2bbd9c25 JJ |
3339 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
3340 | #ifdef BFD_ASSEMBLER | |
3341 | if (reloc_type == BFD_RELOC_32 | |
3342 | && GOT_symbol | |
3343 | && GOT_symbol == i.op[n].disps->X_add_symbol | |
3344 | && (i.op[n].disps->X_op == O_symbol | |
3345 | || (i.op[n].disps->X_op == O_add | |
3346 | && ((symbol_get_value_expression | |
3347 | (i.op[n].disps->X_op_symbol)->X_op) | |
3348 | == O_subtract)))) | |
3349 | { | |
3350 | offsetT add; | |
3351 | ||
3352 | if (insn_start_frag == frag_now) | |
3353 | add = (p - frag_now->fr_literal) - insn_start_off; | |
3354 | else | |
3355 | { | |
3356 | fragS *fr; | |
3357 | ||
3358 | add = insn_start_frag->fr_fix - insn_start_off; | |
3359 | for (fr = insn_start_frag->fr_next; | |
3360 | fr && fr != frag_now; fr = fr->fr_next) | |
3361 | add += fr->fr_fix; | |
3362 | add += p - frag_now->fr_literal; | |
3363 | } | |
3364 | ||
3365 | /* We don't support dynamic linking on x86-64 yet. */ | |
3366 | if (flag_code == CODE_64BIT) | |
3367 | abort (); | |
3368 | reloc_type = BFD_RELOC_386_GOTPC; | |
3369 | i.op[n].disps->X_add_number += add; | |
3370 | } | |
3371 | #endif | |
062cd5e7 | 3372 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
2bbd9c25 | 3373 | i.op[n].disps, pcrel, reloc_type); |
29b0f896 AM |
3374 | } |
3375 | } | |
3376 | } | |
3377 | } | |
252b5132 | 3378 | |
29b0f896 | 3379 | static void |
2bbd9c25 JJ |
3380 | output_imm (insn_start_frag, insn_start_off) |
3381 | fragS *insn_start_frag; | |
3382 | offsetT insn_start_off; | |
29b0f896 AM |
3383 | { |
3384 | char *p; | |
3385 | unsigned int n; | |
252b5132 | 3386 | |
29b0f896 AM |
3387 | for (n = 0; n < i.operands; n++) |
3388 | { | |
3389 | if (i.types[n] & Imm) | |
3390 | { | |
3391 | if (i.op[n].imms->X_op == O_constant) | |
3392 | { | |
3393 | int size; | |
3394 | offsetT val; | |
b4cac588 | 3395 | |
29b0f896 AM |
3396 | size = 4; |
3397 | if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) | |
3398 | { | |
3399 | size = 2; | |
3400 | if (i.types[n] & (Imm8 | Imm8S)) | |
3401 | size = 1; | |
3402 | else if (i.types[n] & Imm64) | |
3403 | size = 8; | |
3404 | } | |
3405 | val = offset_in_range (i.op[n].imms->X_add_number, | |
3406 | size); | |
3407 | p = frag_more (size); | |
3408 | md_number_to_chars (p, val, size); | |
3409 | } | |
3410 | else | |
3411 | { | |
3412 | /* Not absolute_section. | |
3413 | Need a 32-bit fixup (don't support 8bit | |
3414 | non-absolute imms). Try to support other | |
3415 | sizes ... */ | |
3416 | RELOC_ENUM reloc_type; | |
3417 | int size = 4; | |
3418 | int sign = 0; | |
3419 | ||
3420 | if ((i.types[n] & (Imm32S)) | |
3421 | && i.suffix == QWORD_MNEM_SUFFIX) | |
3422 | sign = 1; | |
3423 | if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) | |
3424 | { | |
3425 | size = 2; | |
3426 | if (i.types[n] & (Imm8 | Imm8S)) | |
3427 | size = 1; | |
3428 | if (i.types[n] & Imm64) | |
3429 | size = 8; | |
3430 | } | |
520dc8e8 | 3431 | |
29b0f896 AM |
3432 | p = frag_more (size); |
3433 | reloc_type = reloc (size, 0, sign, i.reloc[n]); | |
252b5132 | 3434 | #ifdef BFD_ASSEMBLER |
2bbd9c25 JJ |
3435 | /* This is tough to explain. We end up with this one if we |
3436 | * have operands that look like | |
3437 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
3438 | * obtain the absolute address of the GOT, and it is strongly | |
3439 | * preferable from a performance point of view to avoid using | |
3440 | * a runtime relocation for this. The actual sequence of | |
3441 | * instructions often look something like: | |
3442 | * | |
3443 | * call .L66 | |
3444 | * .L66: | |
3445 | * popl %ebx | |
3446 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
3447 | * | |
3448 | * The call and pop essentially return the absolute address | |
3449 | * of the label .L66 and store it in %ebx. The linker itself | |
3450 | * will ultimately change the first operand of the addl so | |
3451 | * that %ebx points to the GOT, but to keep things simple, the | |
3452 | * .o file must have this operand set so that it generates not | |
3453 | * the absolute address of .L66, but the absolute address of | |
3454 | * itself. This allows the linker itself simply treat a GOTPC | |
3455 | * relocation as asking for a pcrel offset to the GOT to be | |
3456 | * added in, and the addend of the relocation is stored in the | |
3457 | * operand field for the instruction itself. | |
3458 | * | |
3459 | * Our job here is to fix the operand so that it would add | |
3460 | * the correct offset so that %ebx would point to itself. The | |
3461 | * thing that is tricky is that .-.L66 will point to the | |
3462 | * beginning of the instruction, so we need to further modify | |
3463 | * the operand so that it will point to itself. There are | |
3464 | * other cases where you have something like: | |
3465 | * | |
3466 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
3467 | * | |
3468 | * and here no correction would be required. Internally in | |
3469 | * the assembler we treat operands of this form as not being | |
3470 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
3471 | * whether it would simplify matters to do it this way. Who | |
3472 | * knows. In earlier versions of the PIC patches, the | |
3473 | * pcrel_adjust field was used to store the correction, but | |
3474 | * since the expression is not pcrel, I felt it would be | |
3475 | * confusing to do it this way. */ | |
3476 | ||
29b0f896 AM |
3477 | if (reloc_type == BFD_RELOC_32 |
3478 | && GOT_symbol | |
3479 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
3480 | && (i.op[n].imms->X_op == O_symbol | |
3481 | || (i.op[n].imms->X_op == O_add | |
3482 | && ((symbol_get_value_expression | |
3483 | (i.op[n].imms->X_op_symbol)->X_op) | |
3484 | == O_subtract)))) | |
3485 | { | |
2bbd9c25 JJ |
3486 | offsetT add; |
3487 | ||
3488 | if (insn_start_frag == frag_now) | |
3489 | add = (p - frag_now->fr_literal) - insn_start_off; | |
3490 | else | |
3491 | { | |
3492 | fragS *fr; | |
3493 | ||
3494 | add = insn_start_frag->fr_fix - insn_start_off; | |
3495 | for (fr = insn_start_frag->fr_next; | |
3496 | fr && fr != frag_now; fr = fr->fr_next) | |
3497 | add += fr->fr_fix; | |
3498 | add += p - frag_now->fr_literal; | |
3499 | } | |
3500 | ||
29b0f896 AM |
3501 | /* We don't support dynamic linking on x86-64 yet. */ |
3502 | if (flag_code == CODE_64BIT) | |
3503 | abort (); | |
3504 | reloc_type = BFD_RELOC_386_GOTPC; | |
2bbd9c25 | 3505 | i.op[n].imms->X_add_number += add; |
29b0f896 | 3506 | } |
252b5132 | 3507 | #endif |
29b0f896 AM |
3508 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
3509 | i.op[n].imms, 0, reloc_type); | |
3510 | } | |
3511 | } | |
3512 | } | |
252b5132 RH |
3513 | } |
3514 | \f | |
f3c180ae AM |
3515 | #ifndef LEX_AT |
3516 | static char *lex_got PARAMS ((RELOC_ENUM *, int *)); | |
3517 | ||
3518 | /* Parse operands of the form | |
3519 | <symbol>@GOTOFF+<nnn> | |
3520 | and similar .plt or .got references. | |
3521 | ||
3522 | If we find one, set up the correct relocation in RELOC and copy the | |
3523 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
3524 | parsing by the calling routine. Return this buffer, and if ADJUST | |
3525 | is non-null set it to the length of the string we removed from the | |
3526 | input line. Otherwise return NULL. */ | |
3527 | static char * | |
3528 | lex_got (reloc, adjust) | |
3529 | RELOC_ENUM *reloc; | |
3530 | int *adjust; | |
3531 | { | |
3532 | static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" }; | |
3533 | static const struct { | |
3534 | const char *str; | |
3535 | const RELOC_ENUM rel[NUM_FLAG_CODE]; | |
3536 | } gotrel[] = { | |
13ae64f3 JJ |
3537 | { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } }, |
3538 | { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } }, | |
3539 | { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } }, | |
bffbf940 | 3540 | { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } }, |
13ae64f3 | 3541 | { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } }, |
bffbf940 JJ |
3542 | { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } }, |
3543 | { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } }, | |
3544 | { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } }, | |
13ae64f3 | 3545 | { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } }, |
bffbf940 | 3546 | { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } }, |
37e55690 JJ |
3547 | { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } }, |
3548 | { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } }, | |
13ae64f3 | 3549 | { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } } |
f3c180ae AM |
3550 | }; |
3551 | char *cp; | |
3552 | unsigned int j; | |
3553 | ||
3554 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
3555 | if (is_end_of_line[(unsigned char) *cp]) | |
3556 | return NULL; | |
3557 | ||
3558 | for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++) | |
3559 | { | |
3560 | int len; | |
3561 | ||
3562 | len = strlen (gotrel[j].str); | |
28f81592 | 3563 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae AM |
3564 | { |
3565 | if (gotrel[j].rel[(unsigned int) flag_code] != 0) | |
3566 | { | |
28f81592 AM |
3567 | int first, second; |
3568 | char *tmpbuf, *past_reloc; | |
f3c180ae AM |
3569 | |
3570 | *reloc = gotrel[j].rel[(unsigned int) flag_code]; | |
28f81592 AM |
3571 | if (adjust) |
3572 | *adjust = len; | |
f3c180ae AM |
3573 | |
3574 | if (GOT_symbol == NULL) | |
3575 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
3576 | ||
3577 | /* Replace the relocation token with ' ', so that | |
3578 | errors like foo@GOTOFF1 will be detected. */ | |
28f81592 AM |
3579 | |
3580 | /* The length of the first part of our input line. */ | |
f3c180ae | 3581 | first = cp - input_line_pointer; |
28f81592 AM |
3582 | |
3583 | /* The second part goes from after the reloc token until | |
3584 | (and including) an end_of_line char. Don't use strlen | |
3585 | here as the end_of_line char may not be a NUL. */ | |
3586 | past_reloc = cp + 1 + len; | |
3587 | for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; ) | |
3588 | ; | |
3589 | second = cp - past_reloc; | |
3590 | ||
3591 | /* Allocate and copy string. The trailing NUL shouldn't | |
3592 | be necessary, but be safe. */ | |
3593 | tmpbuf = xmalloc (first + second + 2); | |
f3c180ae AM |
3594 | memcpy (tmpbuf, input_line_pointer, first); |
3595 | tmpbuf[first] = ' '; | |
28f81592 AM |
3596 | memcpy (tmpbuf + first + 1, past_reloc, second); |
3597 | tmpbuf[first + second + 1] = '\0'; | |
f3c180ae AM |
3598 | return tmpbuf; |
3599 | } | |
3600 | ||
3601 | as_bad (_("@%s reloc is not supported in %s bit mode"), | |
3602 | gotrel[j].str, mode_name[(unsigned int) flag_code]); | |
3603 | return NULL; | |
3604 | } | |
3605 | } | |
3606 | ||
3607 | /* Might be a symbol version string. Don't as_bad here. */ | |
3608 | return NULL; | |
3609 | } | |
3610 | ||
3611 | /* x86_cons_fix_new is called via the expression parsing code when a | |
3612 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
3613 | static RELOC_ENUM got_reloc = NO_RELOC; | |
3614 | ||
3615 | void | |
3616 | x86_cons_fix_new (frag, off, len, exp) | |
3617 | fragS *frag; | |
3618 | unsigned int off; | |
3619 | unsigned int len; | |
3620 | expressionS *exp; | |
3621 | { | |
3622 | RELOC_ENUM r = reloc (len, 0, 0, got_reloc); | |
3623 | got_reloc = NO_RELOC; | |
3624 | fix_new_exp (frag, off, len, exp, 0, r); | |
3625 | } | |
3626 | ||
3627 | void | |
3628 | x86_cons (exp, size) | |
3629 | expressionS *exp; | |
3630 | int size; | |
3631 | { | |
3632 | if (size == 4) | |
3633 | { | |
3634 | /* Handle @GOTOFF and the like in an expression. */ | |
3635 | char *save; | |
3636 | char *gotfree_input_line; | |
3637 | int adjust; | |
3638 | ||
3639 | save = input_line_pointer; | |
3640 | gotfree_input_line = lex_got (&got_reloc, &adjust); | |
3641 | if (gotfree_input_line) | |
3642 | input_line_pointer = gotfree_input_line; | |
3643 | ||
3644 | expression (exp); | |
3645 | ||
3646 | if (gotfree_input_line) | |
3647 | { | |
3648 | /* expression () has merrily parsed up to the end of line, | |
3649 | or a comma - in the wrong buffer. Transfer how far | |
3650 | input_line_pointer has moved to the right buffer. */ | |
3651 | input_line_pointer = (save | |
3652 | + (input_line_pointer - gotfree_input_line) | |
3653 | + adjust); | |
3654 | free (gotfree_input_line); | |
3655 | } | |
3656 | } | |
3657 | else | |
3658 | expression (exp); | |
3659 | } | |
3660 | #endif | |
3661 | ||
252b5132 RH |
3662 | static int i386_immediate PARAMS ((char *)); |
3663 | ||
3664 | static int | |
3665 | i386_immediate (imm_start) | |
3666 | char *imm_start; | |
3667 | { | |
3668 | char *save_input_line_pointer; | |
f3c180ae AM |
3669 | #ifndef LEX_AT |
3670 | char *gotfree_input_line; | |
3671 | #endif | |
252b5132 | 3672 | segT exp_seg = 0; |
47926f60 | 3673 | expressionS *exp; |
252b5132 RH |
3674 | |
3675 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
3676 | { | |
d0b47220 | 3677 | as_bad (_("only 1 or 2 immediate operands are allowed")); |
252b5132 RH |
3678 | return 0; |
3679 | } | |
3680 | ||
3681 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 3682 | i.op[this_operand].imms = exp; |
252b5132 RH |
3683 | |
3684 | if (is_space_char (*imm_start)) | |
3685 | ++imm_start; | |
3686 | ||
3687 | save_input_line_pointer = input_line_pointer; | |
3688 | input_line_pointer = imm_start; | |
3689 | ||
3690 | #ifndef LEX_AT | |
f3c180ae AM |
3691 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); |
3692 | if (gotfree_input_line) | |
3693 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
3694 | #endif |
3695 | ||
3696 | exp_seg = expression (exp); | |
3697 | ||
83183c0c | 3698 | SKIP_WHITESPACE (); |
252b5132 | 3699 | if (*input_line_pointer) |
f3c180ae | 3700 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
3701 | |
3702 | input_line_pointer = save_input_line_pointer; | |
f3c180ae AM |
3703 | #ifndef LEX_AT |
3704 | if (gotfree_input_line) | |
3705 | free (gotfree_input_line); | |
3706 | #endif | |
252b5132 | 3707 | |
2daf4fd8 | 3708 | if (exp->X_op == O_absent || exp->X_op == O_big) |
252b5132 | 3709 | { |
47926f60 | 3710 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 3711 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
24eab124 | 3712 | imm_start); |
252b5132 RH |
3713 | exp->X_op = O_constant; |
3714 | exp->X_add_number = 0; | |
3715 | exp->X_add_symbol = (symbolS *) 0; | |
3716 | exp->X_op_symbol = (symbolS *) 0; | |
252b5132 | 3717 | } |
3e73aa7c | 3718 | else if (exp->X_op == O_constant) |
252b5132 | 3719 | { |
47926f60 | 3720 | /* Size it properly later. */ |
3e73aa7c JH |
3721 | i.types[this_operand] |= Imm64; |
3722 | /* If BFD64, sign extend val. */ | |
3723 | if (!use_rela_relocations) | |
3724 | if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) | |
3725 | exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 3726 | } |
4c63da97 | 3727 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
47926f60 | 3728 | else if (1 |
4c63da97 | 3729 | #ifdef BFD_ASSEMBLER |
47926f60 | 3730 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
4c63da97 | 3731 | #endif |
31312f95 | 3732 | && exp_seg != absolute_section |
47926f60 | 3733 | && exp_seg != text_section |
24eab124 AM |
3734 | && exp_seg != data_section |
3735 | && exp_seg != bss_section | |
3736 | && exp_seg != undefined_section | |
252b5132 | 3737 | #ifdef BFD_ASSEMBLER |
24eab124 | 3738 | && !bfd_is_com_section (exp_seg) |
252b5132 | 3739 | #endif |
24eab124 | 3740 | ) |
252b5132 | 3741 | { |
4c63da97 | 3742 | #ifdef BFD_ASSEMBLER |
d0b47220 | 3743 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 3744 | #else |
d0b47220 | 3745 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 3746 | #endif |
252b5132 RH |
3747 | return 0; |
3748 | } | |
3749 | #endif | |
3750 | else | |
3751 | { | |
3752 | /* This is an address. The size of the address will be | |
24eab124 | 3753 | determined later, depending on destination register, |
3e73aa7c JH |
3754 | suffix, or the default for the section. */ |
3755 | i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64; | |
252b5132 RH |
3756 | } |
3757 | ||
3758 | return 1; | |
3759 | } | |
3760 | ||
551c1ca1 | 3761 | static char *i386_scale PARAMS ((char *)); |
252b5132 | 3762 | |
551c1ca1 | 3763 | static char * |
252b5132 RH |
3764 | i386_scale (scale) |
3765 | char *scale; | |
3766 | { | |
551c1ca1 AM |
3767 | offsetT val; |
3768 | char *save = input_line_pointer; | |
252b5132 | 3769 | |
551c1ca1 AM |
3770 | input_line_pointer = scale; |
3771 | val = get_absolute_expression (); | |
3772 | ||
3773 | switch (val) | |
252b5132 | 3774 | { |
551c1ca1 AM |
3775 | case 0: |
3776 | case 1: | |
252b5132 RH |
3777 | i.log2_scale_factor = 0; |
3778 | break; | |
551c1ca1 | 3779 | case 2: |
252b5132 RH |
3780 | i.log2_scale_factor = 1; |
3781 | break; | |
551c1ca1 | 3782 | case 4: |
252b5132 RH |
3783 | i.log2_scale_factor = 2; |
3784 | break; | |
551c1ca1 | 3785 | case 8: |
252b5132 RH |
3786 | i.log2_scale_factor = 3; |
3787 | break; | |
3788 | default: | |
252b5132 | 3789 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), |
24eab124 | 3790 | scale); |
551c1ca1 AM |
3791 | input_line_pointer = save; |
3792 | return NULL; | |
252b5132 | 3793 | } |
29b0f896 | 3794 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
3795 | { |
3796 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 3797 | 1 << i.log2_scale_factor); |
252b5132 RH |
3798 | #if SCALE1_WHEN_NO_INDEX |
3799 | i.log2_scale_factor = 0; | |
3800 | #endif | |
3801 | } | |
551c1ca1 AM |
3802 | scale = input_line_pointer; |
3803 | input_line_pointer = save; | |
3804 | return scale; | |
252b5132 RH |
3805 | } |
3806 | ||
3807 | static int i386_displacement PARAMS ((char *, char *)); | |
3808 | ||
3809 | static int | |
3810 | i386_displacement (disp_start, disp_end) | |
3811 | char *disp_start; | |
3812 | char *disp_end; | |
3813 | { | |
29b0f896 | 3814 | expressionS *exp; |
252b5132 RH |
3815 | segT exp_seg = 0; |
3816 | char *save_input_line_pointer; | |
f3c180ae AM |
3817 | #ifndef LEX_AT |
3818 | char *gotfree_input_line; | |
3819 | #endif | |
252b5132 RH |
3820 | int bigdisp = Disp32; |
3821 | ||
3e73aa7c | 3822 | if (flag_code == CODE_64BIT) |
7ecd2f8b | 3823 | { |
29b0f896 AM |
3824 | if (i.prefix[ADDR_PREFIX] == 0) |
3825 | bigdisp = Disp64; | |
7ecd2f8b JH |
3826 | } |
3827 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
3828 | bigdisp = Disp16; | |
252b5132 RH |
3829 | i.types[this_operand] |= bigdisp; |
3830 | ||
3831 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 3832 | i.op[this_operand].disps = exp; |
252b5132 RH |
3833 | i.disp_operands++; |
3834 | save_input_line_pointer = input_line_pointer; | |
3835 | input_line_pointer = disp_start; | |
3836 | END_STRING_AND_SAVE (disp_end); | |
3837 | ||
3838 | #ifndef GCC_ASM_O_HACK | |
3839 | #define GCC_ASM_O_HACK 0 | |
3840 | #endif | |
3841 | #if GCC_ASM_O_HACK | |
3842 | END_STRING_AND_SAVE (disp_end + 1); | |
3843 | if ((i.types[this_operand] & BaseIndex) != 0 | |
24eab124 | 3844 | && displacement_string_end[-1] == '+') |
252b5132 RH |
3845 | { |
3846 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
3847 | constraint within gcc asm statements. |
3848 | For instance: | |
3849 | ||
3850 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
3851 | __asm__ __volatile__ ( \ | |
3852 | "movw %w2,%0\n\t" \ | |
3853 | "movw %w1,2+%0\n\t" \ | |
3854 | "rorl $16,%1\n\t" \ | |
3855 | "movb %b1,4+%0\n\t" \ | |
3856 | "movb %4,5+%0\n\t" \ | |
3857 | "movb $0,6+%0\n\t" \ | |
3858 | "movb %h1,7+%0\n\t" \ | |
3859 | "rorl $16,%1" \ | |
3860 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
3861 | ||
3862 | This works great except that the output assembler ends | |
3863 | up looking a bit weird if it turns out that there is | |
3864 | no offset. You end up producing code that looks like: | |
3865 | ||
3866 | #APP | |
3867 | movw $235,(%eax) | |
3868 | movw %dx,2+(%eax) | |
3869 | rorl $16,%edx | |
3870 | movb %dl,4+(%eax) | |
3871 | movb $137,5+(%eax) | |
3872 | movb $0,6+(%eax) | |
3873 | movb %dh,7+(%eax) | |
3874 | rorl $16,%edx | |
3875 | #NO_APP | |
3876 | ||
47926f60 | 3877 | So here we provide the missing zero. */ |
24eab124 AM |
3878 | |
3879 | *displacement_string_end = '0'; | |
252b5132 RH |
3880 | } |
3881 | #endif | |
3882 | #ifndef LEX_AT | |
f3c180ae AM |
3883 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); |
3884 | if (gotfree_input_line) | |
3885 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
3886 | #endif |
3887 | ||
24eab124 | 3888 | exp_seg = expression (exp); |
252b5132 | 3889 | |
636c26b0 AM |
3890 | SKIP_WHITESPACE (); |
3891 | if (*input_line_pointer) | |
3892 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
3893 | #if GCC_ASM_O_HACK | |
3894 | RESTORE_END_STRING (disp_end + 1); | |
3895 | #endif | |
3896 | RESTORE_END_STRING (disp_end); | |
3897 | input_line_pointer = save_input_line_pointer; | |
3898 | #ifndef LEX_AT | |
3899 | if (gotfree_input_line) | |
3900 | free (gotfree_input_line); | |
3901 | #endif | |
3902 | ||
252b5132 | 3903 | #ifdef BFD_ASSEMBLER |
24eab124 AM |
3904 | /* We do this to make sure that the section symbol is in |
3905 | the symbol table. We will ultimately change the relocation | |
47926f60 | 3906 | to be relative to the beginning of the section. */ |
1ae12ab7 AM |
3907 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
3908 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) | |
24eab124 | 3909 | { |
636c26b0 AM |
3910 | if (exp->X_op != O_symbol) |
3911 | { | |
3912 | as_bad (_("bad expression used with @%s"), | |
3913 | (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL | |
3914 | ? "GOTPCREL" | |
3915 | : "GOTOFF")); | |
3916 | return 0; | |
3917 | } | |
3918 | ||
e5cb08ac | 3919 | if (S_IS_LOCAL (exp->X_add_symbol) |
24eab124 AM |
3920 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) |
3921 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
24eab124 AM |
3922 | exp->X_op = O_subtract; |
3923 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 3924 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 3925 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
23df1078 | 3926 | else |
29b0f896 | 3927 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 3928 | } |
252b5132 RH |
3929 | #endif |
3930 | ||
2daf4fd8 AM |
3931 | if (exp->X_op == O_absent || exp->X_op == O_big) |
3932 | { | |
47926f60 | 3933 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 3934 | as_bad (_("missing or invalid displacement expression `%s' taken as 0"), |
2daf4fd8 AM |
3935 | disp_start); |
3936 | exp->X_op = O_constant; | |
3937 | exp->X_add_number = 0; | |
3938 | exp->X_add_symbol = (symbolS *) 0; | |
3939 | exp->X_op_symbol = (symbolS *) 0; | |
3940 | } | |
3941 | ||
4c63da97 | 3942 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
45288df1 | 3943 | if (exp->X_op != O_constant |
4c63da97 | 3944 | #ifdef BFD_ASSEMBLER |
45288df1 | 3945 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
4c63da97 | 3946 | #endif |
31312f95 | 3947 | && exp_seg != absolute_section |
45288df1 AM |
3948 | && exp_seg != text_section |
3949 | && exp_seg != data_section | |
3950 | && exp_seg != bss_section | |
31312f95 AM |
3951 | && exp_seg != undefined_section |
3952 | #ifdef BFD_ASSEMBLER | |
3953 | && !bfd_is_com_section (exp_seg) | |
3954 | #endif | |
3955 | ) | |
24eab124 | 3956 | { |
4c63da97 | 3957 | #ifdef BFD_ASSEMBLER |
d0b47220 | 3958 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 3959 | #else |
d0b47220 | 3960 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 3961 | #endif |
24eab124 AM |
3962 | return 0; |
3963 | } | |
252b5132 | 3964 | #endif |
3e73aa7c JH |
3965 | else if (flag_code == CODE_64BIT) |
3966 | i.types[this_operand] |= Disp32S | Disp32; | |
252b5132 RH |
3967 | return 1; |
3968 | } | |
3969 | ||
e5cb08ac | 3970 | static int i386_index_check PARAMS ((const char *)); |
252b5132 | 3971 | |
eecb386c | 3972 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
3973 | Return 1 on success, 0 on a failure. */ |
3974 | ||
252b5132 | 3975 | static int |
eecb386c AM |
3976 | i386_index_check (operand_string) |
3977 | const char *operand_string; | |
252b5132 | 3978 | { |
3e73aa7c | 3979 | int ok; |
24eab124 | 3980 | #if INFER_ADDR_PREFIX |
eecb386c AM |
3981 | int fudged = 0; |
3982 | ||
24eab124 AM |
3983 | tryprefix: |
3984 | #endif | |
3e73aa7c JH |
3985 | ok = 1; |
3986 | if (flag_code == CODE_64BIT) | |
3987 | { | |
7ecd2f8b JH |
3988 | if (i.prefix[ADDR_PREFIX] == 0) |
3989 | { | |
3990 | /* 64bit checks. */ | |
3991 | if ((i.base_reg | |
3992 | && ((i.base_reg->reg_type & Reg64) == 0) | |
3993 | && (i.base_reg->reg_type != BaseIndex | |
3994 | || i.index_reg)) | |
3995 | || (i.index_reg | |
29b0f896 AM |
3996 | && ((i.index_reg->reg_type & (Reg64 | BaseIndex)) |
3997 | != (Reg64 | BaseIndex)))) | |
7ecd2f8b JH |
3998 | ok = 0; |
3999 | } | |
4000 | else | |
4001 | { | |
4002 | /* 32bit checks. */ | |
4003 | if ((i.base_reg | |
4004 | && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32) | |
4005 | || (i.index_reg | |
29b0f896 AM |
4006 | && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex)) |
4007 | != (Reg32 | BaseIndex)))) | |
7ecd2f8b JH |
4008 | ok = 0; |
4009 | } | |
3e73aa7c JH |
4010 | } |
4011 | else | |
4012 | { | |
4013 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
4014 | { | |
4015 | /* 16bit checks. */ | |
4016 | if ((i.base_reg | |
29b0f896 AM |
4017 | && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex)) |
4018 | != (Reg16 | BaseIndex))) | |
3e73aa7c | 4019 | || (i.index_reg |
29b0f896 AM |
4020 | && (((i.index_reg->reg_type & (Reg16 | BaseIndex)) |
4021 | != (Reg16 | BaseIndex)) | |
4022 | || !(i.base_reg | |
4023 | && i.base_reg->reg_num < 6 | |
4024 | && i.index_reg->reg_num >= 6 | |
4025 | && i.log2_scale_factor == 0)))) | |
3e73aa7c JH |
4026 | ok = 0; |
4027 | } | |
4028 | else | |
e5cb08ac | 4029 | { |
3e73aa7c JH |
4030 | /* 32bit checks. */ |
4031 | if ((i.base_reg | |
4032 | && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32) | |
4033 | || (i.index_reg | |
29b0f896 AM |
4034 | && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex)) |
4035 | != (Reg32 | BaseIndex)))) | |
e5cb08ac | 4036 | ok = 0; |
3e73aa7c JH |
4037 | } |
4038 | } | |
4039 | if (!ok) | |
24eab124 AM |
4040 | { |
4041 | #if INFER_ADDR_PREFIX | |
3e73aa7c JH |
4042 | if (flag_code != CODE_64BIT |
4043 | && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0') | |
24eab124 AM |
4044 | { |
4045 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
4046 | i.prefixes += 1; | |
b23bac36 AM |
4047 | /* Change the size of any displacement too. At most one of |
4048 | Disp16 or Disp32 is set. | |
4049 | FIXME. There doesn't seem to be any real need for separate | |
4050 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 4051 | Removing them would probably clean up the code quite a lot. */ |
29b0f896 AM |
4052 | if (i.types[this_operand] & (Disp16 | Disp32)) |
4053 | i.types[this_operand] ^= (Disp16 | Disp32); | |
eecb386c | 4054 | fudged = 1; |
24eab124 AM |
4055 | goto tryprefix; |
4056 | } | |
eecb386c AM |
4057 | if (fudged) |
4058 | as_bad (_("`%s' is not a valid base/index expression"), | |
4059 | operand_string); | |
4060 | else | |
c388dee8 | 4061 | #endif |
eecb386c AM |
4062 | as_bad (_("`%s' is not a valid %s bit base/index expression"), |
4063 | operand_string, | |
3e73aa7c | 4064 | flag_code_names[flag_code]); |
eecb386c | 4065 | return 0; |
24eab124 AM |
4066 | } |
4067 | return 1; | |
4068 | } | |
252b5132 | 4069 | |
252b5132 | 4070 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero |
47926f60 | 4071 | on error. */ |
252b5132 | 4072 | |
252b5132 RH |
4073 | static int |
4074 | i386_operand (operand_string) | |
4075 | char *operand_string; | |
4076 | { | |
af6bdddf AM |
4077 | const reg_entry *r; |
4078 | char *end_op; | |
24eab124 | 4079 | char *op_string = operand_string; |
252b5132 | 4080 | |
24eab124 | 4081 | if (is_space_char (*op_string)) |
252b5132 RH |
4082 | ++op_string; |
4083 | ||
24eab124 | 4084 | /* We check for an absolute prefix (differentiating, |
47926f60 | 4085 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
4086 | if (*op_string == ABSOLUTE_PREFIX) |
4087 | { | |
4088 | ++op_string; | |
4089 | if (is_space_char (*op_string)) | |
4090 | ++op_string; | |
4091 | i.types[this_operand] |= JumpAbsolute; | |
4092 | } | |
252b5132 | 4093 | |
47926f60 | 4094 | /* Check if operand is a register. */ |
af6bdddf AM |
4095 | if ((*op_string == REGISTER_PREFIX || allow_naked_reg) |
4096 | && (r = parse_register (op_string, &end_op)) != NULL) | |
24eab124 | 4097 | { |
24eab124 AM |
4098 | /* Check for a segment override by searching for ':' after a |
4099 | segment register. */ | |
4100 | op_string = end_op; | |
4101 | if (is_space_char (*op_string)) | |
4102 | ++op_string; | |
4103 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
4104 | { | |
4105 | switch (r->reg_num) | |
4106 | { | |
4107 | case 0: | |
4108 | i.seg[i.mem_operands] = &es; | |
4109 | break; | |
4110 | case 1: | |
4111 | i.seg[i.mem_operands] = &cs; | |
4112 | break; | |
4113 | case 2: | |
4114 | i.seg[i.mem_operands] = &ss; | |
4115 | break; | |
4116 | case 3: | |
4117 | i.seg[i.mem_operands] = &ds; | |
4118 | break; | |
4119 | case 4: | |
4120 | i.seg[i.mem_operands] = &fs; | |
4121 | break; | |
4122 | case 5: | |
4123 | i.seg[i.mem_operands] = &gs; | |
4124 | break; | |
4125 | } | |
252b5132 | 4126 | |
24eab124 | 4127 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
4128 | ++op_string; |
4129 | if (is_space_char (*op_string)) | |
24eab124 | 4130 | ++op_string; |
252b5132 | 4131 | |
24eab124 AM |
4132 | if (!is_digit_char (*op_string) |
4133 | && !is_identifier_char (*op_string) | |
4134 | && *op_string != '(' | |
4135 | && *op_string != ABSOLUTE_PREFIX) | |
4136 | { | |
4137 | as_bad (_("bad memory operand `%s'"), op_string); | |
4138 | return 0; | |
4139 | } | |
47926f60 | 4140 | /* Handle case of %es:*foo. */ |
24eab124 AM |
4141 | if (*op_string == ABSOLUTE_PREFIX) |
4142 | { | |
4143 | ++op_string; | |
4144 | if (is_space_char (*op_string)) | |
4145 | ++op_string; | |
4146 | i.types[this_operand] |= JumpAbsolute; | |
4147 | } | |
4148 | goto do_memory_reference; | |
4149 | } | |
4150 | if (*op_string) | |
4151 | { | |
d0b47220 | 4152 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
4153 | return 0; |
4154 | } | |
4155 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
520dc8e8 | 4156 | i.op[this_operand].regs = r; |
24eab124 AM |
4157 | i.reg_operands++; |
4158 | } | |
af6bdddf AM |
4159 | else if (*op_string == REGISTER_PREFIX) |
4160 | { | |
4161 | as_bad (_("bad register name `%s'"), op_string); | |
4162 | return 0; | |
4163 | } | |
24eab124 | 4164 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 4165 | { |
24eab124 AM |
4166 | ++op_string; |
4167 | if (i.types[this_operand] & JumpAbsolute) | |
4168 | { | |
d0b47220 | 4169 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
4170 | return 0; |
4171 | } | |
4172 | if (!i386_immediate (op_string)) | |
4173 | return 0; | |
4174 | } | |
4175 | else if (is_digit_char (*op_string) | |
4176 | || is_identifier_char (*op_string) | |
e5cb08ac | 4177 | || *op_string == '(') |
24eab124 | 4178 | { |
47926f60 | 4179 | /* This is a memory reference of some sort. */ |
af6bdddf | 4180 | char *base_string; |
252b5132 | 4181 | |
47926f60 | 4182 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
4183 | char *displacement_string_start; |
4184 | char *displacement_string_end; | |
252b5132 | 4185 | |
24eab124 | 4186 | do_memory_reference: |
24eab124 AM |
4187 | if ((i.mem_operands == 1 |
4188 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
4189 | || i.mem_operands == 2) | |
4190 | { | |
4191 | as_bad (_("too many memory references for `%s'"), | |
4192 | current_templates->start->name); | |
4193 | return 0; | |
4194 | } | |
252b5132 | 4195 | |
24eab124 AM |
4196 | /* Check for base index form. We detect the base index form by |
4197 | looking for an ')' at the end of the operand, searching | |
4198 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
4199 | after the '('. */ | |
af6bdddf | 4200 | base_string = op_string + strlen (op_string); |
c3332e24 | 4201 | |
af6bdddf AM |
4202 | --base_string; |
4203 | if (is_space_char (*base_string)) | |
4204 | --base_string; | |
252b5132 | 4205 | |
47926f60 | 4206 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
4207 | displacement_string_start = op_string; |
4208 | displacement_string_end = base_string + 1; | |
252b5132 | 4209 | |
24eab124 AM |
4210 | if (*base_string == ')') |
4211 | { | |
af6bdddf | 4212 | char *temp_string; |
24eab124 AM |
4213 | unsigned int parens_balanced = 1; |
4214 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 4215 | equal, so this loop will not be infinite. */ |
24eab124 AM |
4216 | do |
4217 | { | |
4218 | base_string--; | |
4219 | if (*base_string == ')') | |
4220 | parens_balanced++; | |
4221 | if (*base_string == '(') | |
4222 | parens_balanced--; | |
4223 | } | |
4224 | while (parens_balanced); | |
c3332e24 | 4225 | |
af6bdddf | 4226 | temp_string = base_string; |
c3332e24 | 4227 | |
24eab124 | 4228 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
4229 | ++base_string; |
4230 | if (is_space_char (*base_string)) | |
24eab124 | 4231 | ++base_string; |
252b5132 | 4232 | |
af6bdddf AM |
4233 | if (*base_string == ',' |
4234 | || ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
4235 | && (i.base_reg = parse_register (base_string, &end_op)) != NULL)) | |
252b5132 | 4236 | { |
af6bdddf | 4237 | displacement_string_end = temp_string; |
252b5132 | 4238 | |
af6bdddf | 4239 | i.types[this_operand] |= BaseIndex; |
252b5132 | 4240 | |
af6bdddf | 4241 | if (i.base_reg) |
24eab124 | 4242 | { |
24eab124 AM |
4243 | base_string = end_op; |
4244 | if (is_space_char (*base_string)) | |
4245 | ++base_string; | |
af6bdddf AM |
4246 | } |
4247 | ||
4248 | /* There may be an index reg or scale factor here. */ | |
4249 | if (*base_string == ',') | |
4250 | { | |
4251 | ++base_string; | |
4252 | if (is_space_char (*base_string)) | |
4253 | ++base_string; | |
4254 | ||
4255 | if ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
4256 | && (i.index_reg = parse_register (base_string, &end_op)) != NULL) | |
24eab124 | 4257 | { |
af6bdddf | 4258 | base_string = end_op; |
24eab124 AM |
4259 | if (is_space_char (*base_string)) |
4260 | ++base_string; | |
af6bdddf AM |
4261 | if (*base_string == ',') |
4262 | { | |
4263 | ++base_string; | |
4264 | if (is_space_char (*base_string)) | |
4265 | ++base_string; | |
4266 | } | |
e5cb08ac | 4267 | else if (*base_string != ')') |
af6bdddf AM |
4268 | { |
4269 | as_bad (_("expecting `,' or `)' after index register in `%s'"), | |
4270 | operand_string); | |
4271 | return 0; | |
4272 | } | |
24eab124 | 4273 | } |
af6bdddf | 4274 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 4275 | { |
af6bdddf | 4276 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
4277 | return 0; |
4278 | } | |
252b5132 | 4279 | |
47926f60 | 4280 | /* Check for scale factor. */ |
551c1ca1 | 4281 | if (*base_string != ')') |
af6bdddf | 4282 | { |
551c1ca1 AM |
4283 | char *end_scale = i386_scale (base_string); |
4284 | ||
4285 | if (!end_scale) | |
af6bdddf | 4286 | return 0; |
24eab124 | 4287 | |
551c1ca1 | 4288 | base_string = end_scale; |
af6bdddf AM |
4289 | if (is_space_char (*base_string)) |
4290 | ++base_string; | |
4291 | if (*base_string != ')') | |
4292 | { | |
4293 | as_bad (_("expecting `)' after scale factor in `%s'"), | |
4294 | operand_string); | |
4295 | return 0; | |
4296 | } | |
4297 | } | |
4298 | else if (!i.index_reg) | |
24eab124 | 4299 | { |
af6bdddf AM |
4300 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
4301 | *base_string); | |
24eab124 AM |
4302 | return 0; |
4303 | } | |
4304 | } | |
af6bdddf | 4305 | else if (*base_string != ')') |
24eab124 | 4306 | { |
af6bdddf AM |
4307 | as_bad (_("expecting `,' or `)' after base register in `%s'"), |
4308 | operand_string); | |
24eab124 AM |
4309 | return 0; |
4310 | } | |
c3332e24 | 4311 | } |
af6bdddf | 4312 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 4313 | { |
af6bdddf | 4314 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 4315 | return 0; |
c3332e24 | 4316 | } |
24eab124 AM |
4317 | } |
4318 | ||
4319 | /* If there's an expression beginning the operand, parse it, | |
4320 | assuming displacement_string_start and | |
4321 | displacement_string_end are meaningful. */ | |
4322 | if (displacement_string_start != displacement_string_end) | |
4323 | { | |
4324 | if (!i386_displacement (displacement_string_start, | |
4325 | displacement_string_end)) | |
4326 | return 0; | |
4327 | } | |
4328 | ||
4329 | /* Special case for (%dx) while doing input/output op. */ | |
4330 | if (i.base_reg | |
4331 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) | |
4332 | && i.index_reg == 0 | |
4333 | && i.log2_scale_factor == 0 | |
4334 | && i.seg[i.mem_operands] == 0 | |
4335 | && (i.types[this_operand] & Disp) == 0) | |
4336 | { | |
4337 | i.types[this_operand] = InOutPortReg; | |
4338 | return 1; | |
4339 | } | |
4340 | ||
eecb386c AM |
4341 | if (i386_index_check (operand_string) == 0) |
4342 | return 0; | |
24eab124 AM |
4343 | i.mem_operands++; |
4344 | } | |
4345 | else | |
ce8a8b2f AM |
4346 | { |
4347 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
4348 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
4349 | output_invalid (*op_string), | |
4350 | this_operand + 1, | |
4351 | op_string); | |
4352 | return 0; | |
4353 | } | |
47926f60 | 4354 | return 1; /* Normal return. */ |
252b5132 RH |
4355 | } |
4356 | \f | |
ee7fcc42 AM |
4357 | /* md_estimate_size_before_relax() |
4358 | ||
4359 | Called just before relax() for rs_machine_dependent frags. The x86 | |
4360 | assembler uses these frags to handle variable size jump | |
4361 | instructions. | |
4362 | ||
4363 | Any symbol that is now undefined will not become defined. | |
4364 | Return the correct fr_subtype in the frag. | |
4365 | Return the initial "guess for variable size of frag" to caller. | |
4366 | The guess is actually the growth beyond the fixed part. Whatever | |
4367 | we do to grow the fixed or variable part contributes to our | |
4368 | returned value. */ | |
4369 | ||
252b5132 RH |
4370 | int |
4371 | md_estimate_size_before_relax (fragP, segment) | |
29b0f896 AM |
4372 | fragS *fragP; |
4373 | segT segment; | |
252b5132 | 4374 | { |
252b5132 | 4375 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
4376 | check for un-relaxable symbols. On an ELF system, we can't relax |
4377 | an externally visible symbol, because it may be overridden by a | |
4378 | shared library. */ | |
4379 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 4380 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
31312f95 AM |
4381 | || (OUTPUT_FLAVOR == bfd_target_elf_flavour |
4382 | && (S_IS_EXTERNAL (fragP->fr_symbol) | |
4383 | || S_IS_WEAK (fragP->fr_symbol))) | |
b98ef147 AM |
4384 | #endif |
4385 | ) | |
252b5132 | 4386 | { |
b98ef147 AM |
4387 | /* Symbol is undefined in this segment, or we need to keep a |
4388 | reloc so that weak symbols can be overridden. */ | |
4389 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f3c180ae | 4390 | RELOC_ENUM reloc_type; |
ee7fcc42 AM |
4391 | unsigned char *opcode; |
4392 | int old_fr_fix; | |
f6af82bd | 4393 | |
ee7fcc42 AM |
4394 | if (fragP->fr_var != NO_RELOC) |
4395 | reloc_type = fragP->fr_var; | |
b98ef147 | 4396 | else if (size == 2) |
f6af82bd AM |
4397 | reloc_type = BFD_RELOC_16_PCREL; |
4398 | else | |
4399 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 4400 | |
ee7fcc42 AM |
4401 | old_fr_fix = fragP->fr_fix; |
4402 | opcode = (unsigned char *) fragP->fr_opcode; | |
4403 | ||
fddf5b5b | 4404 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 4405 | { |
fddf5b5b AM |
4406 | case UNCOND_JUMP: |
4407 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 4408 | opcode[0] = 0xe9; |
252b5132 | 4409 | fragP->fr_fix += size; |
062cd5e7 AS |
4410 | fix_new (fragP, old_fr_fix, size, |
4411 | fragP->fr_symbol, | |
4412 | fragP->fr_offset, 1, | |
4413 | reloc_type); | |
252b5132 RH |
4414 | break; |
4415 | ||
fddf5b5b | 4416 | case COND_JUMP86: |
412167cb AM |
4417 | if (size == 2 |
4418 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
4419 | { |
4420 | /* Negate the condition, and branch past an | |
4421 | unconditional jump. */ | |
4422 | opcode[0] ^= 1; | |
4423 | opcode[1] = 3; | |
4424 | /* Insert an unconditional jump. */ | |
4425 | opcode[2] = 0xe9; | |
4426 | /* We added two extra opcode bytes, and have a two byte | |
4427 | offset. */ | |
4428 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
4429 | fix_new (fragP, old_fr_fix + 2, 2, |
4430 | fragP->fr_symbol, | |
4431 | fragP->fr_offset, 1, | |
4432 | reloc_type); | |
fddf5b5b AM |
4433 | break; |
4434 | } | |
4435 | /* Fall through. */ | |
4436 | ||
4437 | case COND_JUMP: | |
412167cb AM |
4438 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
4439 | { | |
3e02c1cc AM |
4440 | fixS *fixP; |
4441 | ||
412167cb | 4442 | fragP->fr_fix += 1; |
3e02c1cc AM |
4443 | fixP = fix_new (fragP, old_fr_fix, 1, |
4444 | fragP->fr_symbol, | |
4445 | fragP->fr_offset, 1, | |
4446 | BFD_RELOC_8_PCREL); | |
4447 | fixP->fx_signed = 1; | |
412167cb AM |
4448 | break; |
4449 | } | |
93c2a809 | 4450 | |
24eab124 | 4451 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 4452 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 4453 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 4454 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
4455 | /* We've added an opcode byte. */ |
4456 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
4457 | fix_new (fragP, old_fr_fix + 1, size, |
4458 | fragP->fr_symbol, | |
4459 | fragP->fr_offset, 1, | |
4460 | reloc_type); | |
252b5132 | 4461 | break; |
fddf5b5b AM |
4462 | |
4463 | default: | |
4464 | BAD_CASE (fragP->fr_subtype); | |
4465 | break; | |
252b5132 RH |
4466 | } |
4467 | frag_wane (fragP); | |
ee7fcc42 | 4468 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 4469 | } |
93c2a809 | 4470 | |
93c2a809 AM |
4471 | /* Guess size depending on current relax state. Initially the relax |
4472 | state will correspond to a short jump and we return 1, because | |
4473 | the variable part of the frag (the branch offset) is one byte | |
4474 | long. However, we can relax a section more than once and in that | |
4475 | case we must either set fr_subtype back to the unrelaxed state, | |
4476 | or return the value for the appropriate branch. */ | |
4477 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
4478 | } |
4479 | ||
47926f60 KH |
4480 | /* Called after relax() is finished. |
4481 | ||
4482 | In: Address of frag. | |
4483 | fr_type == rs_machine_dependent. | |
4484 | fr_subtype is what the address relaxed to. | |
4485 | ||
4486 | Out: Any fixSs and constants are set up. | |
4487 | Caller will turn frag into a ".space 0". */ | |
4488 | ||
252b5132 RH |
4489 | #ifndef BFD_ASSEMBLER |
4490 | void | |
4491 | md_convert_frag (headers, sec, fragP) | |
a04b544b ILT |
4492 | object_headers *headers ATTRIBUTE_UNUSED; |
4493 | segT sec ATTRIBUTE_UNUSED; | |
29b0f896 | 4494 | fragS *fragP; |
252b5132 RH |
4495 | #else |
4496 | void | |
4497 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
4498 | bfd *abfd ATTRIBUTE_UNUSED; |
4499 | segT sec ATTRIBUTE_UNUSED; | |
29b0f896 | 4500 | fragS *fragP; |
252b5132 RH |
4501 | #endif |
4502 | { | |
29b0f896 | 4503 | unsigned char *opcode; |
252b5132 | 4504 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
4505 | offsetT target_address; |
4506 | offsetT opcode_address; | |
252b5132 | 4507 | unsigned int extension = 0; |
847f7ad4 | 4508 | offsetT displacement_from_opcode_start; |
252b5132 RH |
4509 | |
4510 | opcode = (unsigned char *) fragP->fr_opcode; | |
4511 | ||
47926f60 | 4512 | /* Address we want to reach in file space. */ |
252b5132 | 4513 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 4514 | |
47926f60 | 4515 | /* Address opcode resides at in file space. */ |
252b5132 RH |
4516 | opcode_address = fragP->fr_address + fragP->fr_fix; |
4517 | ||
47926f60 | 4518 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
4519 | displacement_from_opcode_start = target_address - opcode_address; |
4520 | ||
fddf5b5b | 4521 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 4522 | { |
47926f60 KH |
4523 | /* Don't have to change opcode. */ |
4524 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 4525 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
4526 | } |
4527 | else | |
4528 | { | |
4529 | if (no_cond_jump_promotion | |
4530 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4531 | as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required")); | |
252b5132 | 4532 | |
fddf5b5b AM |
4533 | switch (fragP->fr_subtype) |
4534 | { | |
4535 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
4536 | extension = 4; /* 1 opcode + 4 displacement */ | |
4537 | opcode[0] = 0xe9; | |
4538 | where_to_put_displacement = &opcode[1]; | |
4539 | break; | |
252b5132 | 4540 | |
fddf5b5b AM |
4541 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
4542 | extension = 2; /* 1 opcode + 2 displacement */ | |
4543 | opcode[0] = 0xe9; | |
4544 | where_to_put_displacement = &opcode[1]; | |
4545 | break; | |
252b5132 | 4546 | |
fddf5b5b AM |
4547 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
4548 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
4549 | extension = 5; /* 2 opcode + 4 displacement */ | |
4550 | opcode[1] = opcode[0] + 0x10; | |
4551 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
4552 | where_to_put_displacement = &opcode[2]; | |
4553 | break; | |
252b5132 | 4554 | |
fddf5b5b AM |
4555 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
4556 | extension = 3; /* 2 opcode + 2 displacement */ | |
4557 | opcode[1] = opcode[0] + 0x10; | |
4558 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
4559 | where_to_put_displacement = &opcode[2]; | |
4560 | break; | |
252b5132 | 4561 | |
fddf5b5b AM |
4562 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
4563 | extension = 4; | |
4564 | opcode[0] ^= 1; | |
4565 | opcode[1] = 3; | |
4566 | opcode[2] = 0xe9; | |
4567 | where_to_put_displacement = &opcode[3]; | |
4568 | break; | |
4569 | ||
4570 | default: | |
4571 | BAD_CASE (fragP->fr_subtype); | |
4572 | break; | |
4573 | } | |
252b5132 | 4574 | } |
fddf5b5b | 4575 | |
47926f60 | 4576 | /* Now put displacement after opcode. */ |
252b5132 RH |
4577 | md_number_to_chars ((char *) where_to_put_displacement, |
4578 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 4579 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
4580 | fragP->fr_fix += extension; |
4581 | } | |
4582 | \f | |
47926f60 KH |
4583 | /* Size of byte displacement jmp. */ |
4584 | int md_short_jump_size = 2; | |
4585 | ||
4586 | /* Size of dword displacement jmp. */ | |
4587 | int md_long_jump_size = 5; | |
252b5132 | 4588 | |
47926f60 KH |
4589 | /* Size of relocation record. */ |
4590 | const int md_reloc_size = 8; | |
252b5132 RH |
4591 | |
4592 | void | |
4593 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
4594 | char *ptr; | |
4595 | addressT from_addr, to_addr; | |
ab9da554 ILT |
4596 | fragS *frag ATTRIBUTE_UNUSED; |
4597 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 4598 | { |
847f7ad4 | 4599 | offsetT offset; |
252b5132 RH |
4600 | |
4601 | offset = to_addr - (from_addr + 2); | |
47926f60 KH |
4602 | /* Opcode for byte-disp jump. */ |
4603 | md_number_to_chars (ptr, (valueT) 0xeb, 1); | |
252b5132 RH |
4604 | md_number_to_chars (ptr + 1, (valueT) offset, 1); |
4605 | } | |
4606 | ||
4607 | void | |
4608 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
4609 | char *ptr; | |
4610 | addressT from_addr, to_addr; | |
a38cf1db AM |
4611 | fragS *frag ATTRIBUTE_UNUSED; |
4612 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 4613 | { |
847f7ad4 | 4614 | offsetT offset; |
252b5132 | 4615 | |
a38cf1db AM |
4616 | offset = to_addr - (from_addr + 5); |
4617 | md_number_to_chars (ptr, (valueT) 0xe9, 1); | |
4618 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
252b5132 RH |
4619 | } |
4620 | \f | |
4621 | /* Apply a fixup (fixS) to segment data, once it has been determined | |
4622 | by our caller that we have all the info we need to fix it up. | |
4623 | ||
4624 | On the 386, immediates, displacements, and data pointers are all in | |
4625 | the same (little-endian) format, so we don't need to care about which | |
4626 | we are handling. */ | |
4627 | ||
94f592af NC |
4628 | void |
4629 | md_apply_fix3 (fixP, valP, seg) | |
47926f60 KH |
4630 | /* The fix we're to put in. */ |
4631 | fixS *fixP; | |
47926f60 | 4632 | /* Pointer to the value of the bits. */ |
c6682705 | 4633 | valueT *valP; |
47926f60 KH |
4634 | /* Segment fix is from. */ |
4635 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 | 4636 | { |
94f592af | 4637 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 4638 | valueT value = *valP; |
252b5132 | 4639 | |
e1b283bb | 4640 | #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) |
93382f6d AM |
4641 | if (fixP->fx_pcrel) |
4642 | { | |
4643 | switch (fixP->fx_r_type) | |
4644 | { | |
5865bb77 ILT |
4645 | default: |
4646 | break; | |
4647 | ||
93382f6d AM |
4648 | case BFD_RELOC_32: |
4649 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
4650 | break; | |
4651 | case BFD_RELOC_16: | |
4652 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
4653 | break; | |
4654 | case BFD_RELOC_8: | |
4655 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
4656 | break; | |
4657 | } | |
4658 | } | |
252b5132 | 4659 | |
a161fe53 | 4660 | if (fixP->fx_addsy != NULL |
31312f95 AM |
4661 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
4662 | || fixP->fx_r_type == BFD_RELOC_16_PCREL | |
4663 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
4664 | && !use_rela_relocations) | |
252b5132 | 4665 | { |
31312f95 AM |
4666 | /* This is a hack. There should be a better way to handle this. |
4667 | This covers for the fact that bfd_install_relocation will | |
4668 | subtract the current location (for partial_inplace, PC relative | |
4669 | relocations); see more below. */ | |
252b5132 RH |
4670 | #ifndef OBJ_AOUT |
4671 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4672 | #ifdef TE_PE | |
4673 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
4674 | #endif | |
4675 | ) | |
4676 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4677 | #endif | |
4678 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2f66722d | 4679 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
252b5132 | 4680 | { |
6539b54b | 4681 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 4682 | |
6539b54b | 4683 | if ((sym_seg == seg |
2f66722d | 4684 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 4685 | && sym_seg != absolute_section)) |
ae6063d4 | 4686 | && !generic_force_reloc (fixP)) |
2f66722d AM |
4687 | { |
4688 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
4689 | bfd_install_relocation subtracts them out again. I think |
4690 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
4691 | it. FIXME. */ |
4692 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4693 | } | |
252b5132 RH |
4694 | } |
4695 | #endif | |
4696 | #if defined (OBJ_COFF) && defined (TE_PE) | |
4697 | /* For some reason, the PE format does not store a section | |
24eab124 | 4698 | address offset for a PC relative symbol. */ |
252b5132 RH |
4699 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) |
4700 | value += md_pcrel_from (fixP); | |
4701 | #endif | |
4702 | } | |
4703 | ||
4704 | /* Fix a few things - the dynamic linker expects certain values here, | |
47926f60 | 4705 | and we must not dissappoint it. */ |
252b5132 RH |
4706 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4707 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4708 | && fixP->fx_addsy) | |
47926f60 KH |
4709 | switch (fixP->fx_r_type) |
4710 | { | |
4711 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 4712 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
4713 | /* Make the jump instruction point to the address of the operand. At |
4714 | runtime we merely add the offset to the actual PLT entry. */ | |
4715 | value = -4; | |
4716 | break; | |
31312f95 | 4717 | |
13ae64f3 JJ |
4718 | case BFD_RELOC_386_TLS_GD: |
4719 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 4720 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
4721 | case BFD_RELOC_386_TLS_IE: |
4722 | case BFD_RELOC_386_TLS_GOTIE: | |
bffbf940 JJ |
4723 | case BFD_RELOC_X86_64_TLSGD: |
4724 | case BFD_RELOC_X86_64_TLSLD: | |
4725 | case BFD_RELOC_X86_64_GOTTPOFF: | |
00f7efb6 JJ |
4726 | value = 0; /* Fully resolved at runtime. No addend. */ |
4727 | /* Fallthrough */ | |
4728 | case BFD_RELOC_386_TLS_LE: | |
4729 | case BFD_RELOC_386_TLS_LDO_32: | |
4730 | case BFD_RELOC_386_TLS_LE_32: | |
4731 | case BFD_RELOC_X86_64_DTPOFF32: | |
4732 | case BFD_RELOC_X86_64_TPOFF32: | |
4733 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
4734 | break; | |
4735 | ||
4736 | case BFD_RELOC_386_GOT32: | |
4737 | case BFD_RELOC_X86_64_GOT32: | |
47926f60 KH |
4738 | value = 0; /* Fully resolved at runtime. No addend. */ |
4739 | break; | |
47926f60 KH |
4740 | |
4741 | case BFD_RELOC_VTABLE_INHERIT: | |
4742 | case BFD_RELOC_VTABLE_ENTRY: | |
4743 | fixP->fx_done = 0; | |
94f592af | 4744 | return; |
47926f60 KH |
4745 | |
4746 | default: | |
4747 | break; | |
4748 | } | |
4749 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 4750 | *valP = value; |
47926f60 | 4751 | #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */ |
3e73aa7c | 4752 | |
3e73aa7c | 4753 | /* Are we finished with this relocation now? */ |
c6682705 | 4754 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 4755 | fixP->fx_done = 1; |
94f592af | 4756 | #ifdef BFD_ASSEMBLER |
3e73aa7c JH |
4757 | else if (use_rela_relocations) |
4758 | { | |
4759 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
4760 | /* Remember value for tc_gen_reloc. */ |
4761 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
4762 | value = 0; |
4763 | } | |
3e73aa7c | 4764 | #endif |
94f592af | 4765 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 4766 | } |
252b5132 | 4767 | \f |
252b5132 RH |
4768 | #define MAX_LITTLENUMS 6 |
4769 | ||
47926f60 KH |
4770 | /* Turn the string pointed to by litP into a floating point constant |
4771 | of type TYPE, and emit the appropriate bytes. The number of | |
4772 | LITTLENUMS emitted is stored in *SIZEP. An error message is | |
4773 | returned, or NULL on OK. */ | |
4774 | ||
252b5132 RH |
4775 | char * |
4776 | md_atof (type, litP, sizeP) | |
2ab9b79e | 4777 | int type; |
252b5132 RH |
4778 | char *litP; |
4779 | int *sizeP; | |
4780 | { | |
4781 | int prec; | |
4782 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4783 | LITTLENUM_TYPE *wordP; | |
4784 | char *t; | |
4785 | ||
4786 | switch (type) | |
4787 | { | |
4788 | case 'f': | |
4789 | case 'F': | |
4790 | prec = 2; | |
4791 | break; | |
4792 | ||
4793 | case 'd': | |
4794 | case 'D': | |
4795 | prec = 4; | |
4796 | break; | |
4797 | ||
4798 | case 'x': | |
4799 | case 'X': | |
4800 | prec = 5; | |
4801 | break; | |
4802 | ||
4803 | default: | |
4804 | *sizeP = 0; | |
4805 | return _("Bad call to md_atof ()"); | |
4806 | } | |
4807 | t = atof_ieee (input_line_pointer, type, words); | |
4808 | if (t) | |
4809 | input_line_pointer = t; | |
4810 | ||
4811 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
4812 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with | |
4813 | the bigendian 386. */ | |
4814 | for (wordP = words + prec - 1; prec--;) | |
4815 | { | |
4816 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); | |
4817 | litP += sizeof (LITTLENUM_TYPE); | |
4818 | } | |
4819 | return 0; | |
4820 | } | |
4821 | \f | |
4822 | char output_invalid_buf[8]; | |
4823 | ||
252b5132 RH |
4824 | static char * |
4825 | output_invalid (c) | |
4826 | int c; | |
4827 | { | |
3882b010 | 4828 | if (ISPRINT (c)) |
252b5132 RH |
4829 | sprintf (output_invalid_buf, "'%c'", c); |
4830 | else | |
4831 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
4832 | return output_invalid_buf; | |
4833 | } | |
4834 | ||
af6bdddf | 4835 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
4836 | |
4837 | static const reg_entry * | |
4838 | parse_register (reg_string, end_op) | |
4839 | char *reg_string; | |
4840 | char **end_op; | |
4841 | { | |
af6bdddf AM |
4842 | char *s = reg_string; |
4843 | char *p; | |
252b5132 RH |
4844 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
4845 | const reg_entry *r; | |
4846 | ||
4847 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
4848 | if (*s == REGISTER_PREFIX) | |
4849 | ++s; | |
4850 | ||
4851 | if (is_space_char (*s)) | |
4852 | ++s; | |
4853 | ||
4854 | p = reg_name_given; | |
af6bdddf | 4855 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
4856 | { |
4857 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
4858 | return (const reg_entry *) NULL; |
4859 | s++; | |
252b5132 RH |
4860 | } |
4861 | ||
6588847e DN |
4862 | /* For naked regs, make sure that we are not dealing with an identifier. |
4863 | This prevents confusing an identifier like `eax_var' with register | |
4864 | `eax'. */ | |
4865 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
4866 | return (const reg_entry *) NULL; | |
4867 | ||
af6bdddf | 4868 | *end_op = s; |
252b5132 RH |
4869 | |
4870 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
4871 | ||
5f47d35b | 4872 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 4873 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 4874 | { |
5f47d35b AM |
4875 | if (is_space_char (*s)) |
4876 | ++s; | |
4877 | if (*s == '(') | |
4878 | { | |
af6bdddf | 4879 | ++s; |
5f47d35b AM |
4880 | if (is_space_char (*s)) |
4881 | ++s; | |
4882 | if (*s >= '0' && *s <= '7') | |
4883 | { | |
4884 | r = &i386_float_regtab[*s - '0']; | |
af6bdddf | 4885 | ++s; |
5f47d35b AM |
4886 | if (is_space_char (*s)) |
4887 | ++s; | |
4888 | if (*s == ')') | |
4889 | { | |
4890 | *end_op = s + 1; | |
4891 | return r; | |
4892 | } | |
5f47d35b | 4893 | } |
47926f60 | 4894 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
4895 | return (const reg_entry *) NULL; |
4896 | } | |
4897 | } | |
4898 | ||
1ae00879 | 4899 | if (r != NULL |
29b0f896 | 4900 | && (r->reg_flags & (RegRex64 | RegRex)) != 0 |
1ae00879 AM |
4901 | && flag_code != CODE_64BIT) |
4902 | { | |
4903 | return (const reg_entry *) NULL; | |
4904 | } | |
4905 | ||
252b5132 RH |
4906 | return r; |
4907 | } | |
4908 | \f | |
4cc782b5 | 4909 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 4910 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 4911 | #else |
12b55ccc | 4912 | const char *md_shortopts = "qn"; |
252b5132 | 4913 | #endif |
6e0b89ee | 4914 | |
252b5132 | 4915 | struct option md_longopts[] = { |
3e73aa7c JH |
4916 | #define OPTION_32 (OPTION_MD_BASE + 0) |
4917 | {"32", no_argument, NULL, OPTION_32}, | |
6e0b89ee | 4918 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3e73aa7c JH |
4919 | #define OPTION_64 (OPTION_MD_BASE + 1) |
4920 | {"64", no_argument, NULL, OPTION_64}, | |
6e0b89ee | 4921 | #endif |
252b5132 RH |
4922 | {NULL, no_argument, NULL, 0} |
4923 | }; | |
4924 | size_t md_longopts_size = sizeof (md_longopts); | |
4925 | ||
4926 | int | |
4927 | md_parse_option (c, arg) | |
4928 | int c; | |
ab9da554 | 4929 | char *arg ATTRIBUTE_UNUSED; |
252b5132 RH |
4930 | { |
4931 | switch (c) | |
4932 | { | |
12b55ccc L |
4933 | case 'n': |
4934 | optimize_align_code = 0; | |
4935 | break; | |
4936 | ||
a38cf1db AM |
4937 | case 'q': |
4938 | quiet_warnings = 1; | |
252b5132 RH |
4939 | break; |
4940 | ||
4941 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
4942 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
4943 | should be emitted or not. FIXME: Not implemented. */ | |
4944 | case 'Q': | |
252b5132 RH |
4945 | break; |
4946 | ||
4947 | /* -V: SVR4 argument to print version ID. */ | |
4948 | case 'V': | |
4949 | print_version_id (); | |
4950 | break; | |
4951 | ||
a38cf1db AM |
4952 | /* -k: Ignore for FreeBSD compatibility. */ |
4953 | case 'k': | |
252b5132 | 4954 | break; |
4cc782b5 ILT |
4955 | |
4956 | case 's': | |
4957 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 4958 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 4959 | break; |
6e0b89ee | 4960 | |
3e73aa7c JH |
4961 | case OPTION_64: |
4962 | { | |
4963 | const char **list, **l; | |
4964 | ||
3e73aa7c JH |
4965 | list = bfd_target_list (); |
4966 | for (l = list; *l != NULL; l++) | |
6e0b89ee AM |
4967 | if (strcmp (*l, "elf64-x86-64") == 0) |
4968 | { | |
4969 | default_arch = "x86_64"; | |
4970 | break; | |
4971 | } | |
3e73aa7c | 4972 | if (*l == NULL) |
6e0b89ee | 4973 | as_fatal (_("No compiled in support for x86_64")); |
3e73aa7c JH |
4974 | free (list); |
4975 | } | |
4976 | break; | |
4977 | #endif | |
252b5132 | 4978 | |
6e0b89ee AM |
4979 | case OPTION_32: |
4980 | default_arch = "i386"; | |
4981 | break; | |
4982 | ||
252b5132 RH |
4983 | default: |
4984 | return 0; | |
4985 | } | |
4986 | return 1; | |
4987 | } | |
4988 | ||
4989 | void | |
4990 | md_show_usage (stream) | |
4991 | FILE *stream; | |
4992 | { | |
4cc782b5 ILT |
4993 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4994 | fprintf (stream, _("\ | |
a38cf1db AM |
4995 | -Q ignored\n\ |
4996 | -V print assembler version number\n\ | |
4997 | -k ignored\n\ | |
12b55ccc | 4998 | -n Do not optimize code alignment\n\ |
a38cf1db AM |
4999 | -q quieten some warnings\n\ |
5000 | -s ignored\n")); | |
5001 | #else | |
5002 | fprintf (stream, _("\ | |
12b55ccc | 5003 | -n Do not optimize code alignment\n\ |
a38cf1db | 5004 | -q quieten some warnings\n")); |
4cc782b5 | 5005 | #endif |
252b5132 RH |
5006 | } |
5007 | ||
5008 | #ifdef BFD_ASSEMBLER | |
3e73aa7c JH |
5009 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
5010 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
252b5132 RH |
5011 | |
5012 | /* Pick the target format to use. */ | |
5013 | ||
47926f60 | 5014 | const char * |
252b5132 RH |
5015 | i386_target_format () |
5016 | { | |
3e73aa7c JH |
5017 | if (!strcmp (default_arch, "x86_64")) |
5018 | set_code_flag (CODE_64BIT); | |
5019 | else if (!strcmp (default_arch, "i386")) | |
5020 | set_code_flag (CODE_32BIT); | |
5021 | else | |
5022 | as_fatal (_("Unknown architecture")); | |
252b5132 RH |
5023 | switch (OUTPUT_FLAVOR) |
5024 | { | |
4c63da97 AM |
5025 | #ifdef OBJ_MAYBE_AOUT |
5026 | case bfd_target_aout_flavour: | |
47926f60 | 5027 | return AOUT_TARGET_FORMAT; |
4c63da97 AM |
5028 | #endif |
5029 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
5030 | case bfd_target_coff_flavour: |
5031 | return "coff-i386"; | |
4c63da97 | 5032 | #endif |
3e73aa7c | 5033 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 5034 | case bfd_target_elf_flavour: |
3e73aa7c | 5035 | { |
e5cb08ac KH |
5036 | if (flag_code == CODE_64BIT) |
5037 | use_rela_relocations = 1; | |
4ada7262 | 5038 | return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT; |
3e73aa7c | 5039 | } |
4c63da97 | 5040 | #endif |
252b5132 RH |
5041 | default: |
5042 | abort (); | |
5043 | return NULL; | |
5044 | } | |
5045 | } | |
5046 | ||
47926f60 | 5047 | #endif /* OBJ_MAYBE_ more than one */ |
a847613f AM |
5048 | |
5049 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
5050 | void i386_elf_emit_arch_note () | |
5051 | { | |
5052 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
5053 | && cpu_arch_name != NULL) | |
5054 | { | |
5055 | char *p; | |
5056 | asection *seg = now_seg; | |
5057 | subsegT subseg = now_subseg; | |
5058 | Elf_Internal_Note i_note; | |
5059 | Elf_External_Note e_note; | |
5060 | asection *note_secp; | |
5061 | int len; | |
5062 | ||
5063 | /* Create the .note section. */ | |
5064 | note_secp = subseg_new (".note", 0); | |
5065 | bfd_set_section_flags (stdoutput, | |
5066 | note_secp, | |
5067 | SEC_HAS_CONTENTS | SEC_READONLY); | |
5068 | ||
5069 | /* Process the arch string. */ | |
5070 | len = strlen (cpu_arch_name); | |
5071 | ||
5072 | i_note.namesz = len + 1; | |
5073 | i_note.descsz = 0; | |
5074 | i_note.type = NT_ARCH; | |
5075 | p = frag_more (sizeof (e_note.namesz)); | |
5076 | md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); | |
5077 | p = frag_more (sizeof (e_note.descsz)); | |
5078 | md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); | |
5079 | p = frag_more (sizeof (e_note.type)); | |
5080 | md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); | |
5081 | p = frag_more (len + 1); | |
5082 | strcpy (p, cpu_arch_name); | |
5083 | ||
5084 | frag_align (2, 0, 0); | |
5085 | ||
5086 | subseg_set (seg, subseg); | |
5087 | } | |
5088 | } | |
5089 | #endif | |
47926f60 | 5090 | #endif /* BFD_ASSEMBLER */ |
252b5132 | 5091 | \f |
252b5132 RH |
5092 | symbolS * |
5093 | md_undefined_symbol (name) | |
5094 | char *name; | |
5095 | { | |
18dc2407 ILT |
5096 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
5097 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
5098 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
5099 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
5100 | { |
5101 | if (!GOT_symbol) | |
5102 | { | |
5103 | if (symbol_find (name)) | |
5104 | as_bad (_("GOT already in symbol table")); | |
5105 | GOT_symbol = symbol_new (name, undefined_section, | |
5106 | (valueT) 0, &zero_address_frag); | |
5107 | }; | |
5108 | return GOT_symbol; | |
5109 | } | |
252b5132 RH |
5110 | return 0; |
5111 | } | |
5112 | ||
5113 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 5114 | |
252b5132 RH |
5115 | valueT |
5116 | md_section_align (segment, size) | |
ab9da554 | 5117 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
5118 | valueT size; |
5119 | { | |
252b5132 | 5120 | #ifdef BFD_ASSEMBLER |
4c63da97 AM |
5121 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
5122 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
5123 | { | |
5124 | /* For a.out, force the section size to be aligned. If we don't do | |
5125 | this, BFD will align it for us, but it will not write out the | |
5126 | final bytes of the section. This may be a bug in BFD, but it is | |
5127 | easier to fix it here since that is how the other a.out targets | |
5128 | work. */ | |
5129 | int align; | |
5130 | ||
5131 | align = bfd_get_section_alignment (stdoutput, segment); | |
5132 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
5133 | } | |
252b5132 RH |
5134 | #endif |
5135 | #endif | |
5136 | ||
5137 | return size; | |
5138 | } | |
5139 | ||
5140 | /* On the i386, PC-relative offsets are relative to the start of the | |
5141 | next instruction. That is, the address of the offset, plus its | |
5142 | size, since the offset is always the last part of the insn. */ | |
5143 | ||
5144 | long | |
5145 | md_pcrel_from (fixP) | |
5146 | fixS *fixP; | |
5147 | { | |
5148 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
5149 | } | |
5150 | ||
5151 | #ifndef I386COFF | |
5152 | ||
5153 | static void | |
5154 | s_bss (ignore) | |
ab9da554 | 5155 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 5156 | { |
29b0f896 | 5157 | int temp; |
252b5132 RH |
5158 | |
5159 | temp = get_absolute_expression (); | |
5160 | subseg_set (bss_section, (subsegT) temp); | |
5161 | demand_empty_rest_of_line (); | |
5162 | } | |
5163 | ||
5164 | #endif | |
5165 | ||
252b5132 RH |
5166 | #ifdef BFD_ASSEMBLER |
5167 | ||
5168 | void | |
5169 | i386_validate_fix (fixp) | |
5170 | fixS *fixp; | |
5171 | { | |
5172 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
5173 | { | |
3e73aa7c | 5174 | /* GOTOFF relocation are nonsense in 64bit mode. */ |
23df1078 JH |
5175 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
5176 | { | |
5177 | if (flag_code != CODE_64BIT) | |
5178 | abort (); | |
5179 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
5180 | } | |
5181 | else | |
5182 | { | |
5183 | if (flag_code == CODE_64BIT) | |
5184 | abort (); | |
5185 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
5186 | } | |
252b5132 RH |
5187 | fixp->fx_subsy = 0; |
5188 | } | |
5189 | } | |
5190 | ||
252b5132 RH |
5191 | arelent * |
5192 | tc_gen_reloc (section, fixp) | |
ab9da554 | 5193 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
5194 | fixS *fixp; |
5195 | { | |
5196 | arelent *rel; | |
5197 | bfd_reloc_code_real_type code; | |
5198 | ||
5199 | switch (fixp->fx_r_type) | |
5200 | { | |
3e73aa7c JH |
5201 | case BFD_RELOC_X86_64_PLT32: |
5202 | case BFD_RELOC_X86_64_GOT32: | |
5203 | case BFD_RELOC_X86_64_GOTPCREL: | |
252b5132 RH |
5204 | case BFD_RELOC_386_PLT32: |
5205 | case BFD_RELOC_386_GOT32: | |
5206 | case BFD_RELOC_386_GOTOFF: | |
5207 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
5208 | case BFD_RELOC_386_TLS_GD: |
5209 | case BFD_RELOC_386_TLS_LDM: | |
5210 | case BFD_RELOC_386_TLS_LDO_32: | |
5211 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
5212 | case BFD_RELOC_386_TLS_IE: |
5213 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
5214 | case BFD_RELOC_386_TLS_LE_32: |
5215 | case BFD_RELOC_386_TLS_LE: | |
3e73aa7c | 5216 | case BFD_RELOC_X86_64_32S: |
bffbf940 JJ |
5217 | case BFD_RELOC_X86_64_TLSGD: |
5218 | case BFD_RELOC_X86_64_TLSLD: | |
5219 | case BFD_RELOC_X86_64_DTPOFF32: | |
5220 | case BFD_RELOC_X86_64_GOTTPOFF: | |
5221 | case BFD_RELOC_X86_64_TPOFF32: | |
252b5132 RH |
5222 | case BFD_RELOC_RVA: |
5223 | case BFD_RELOC_VTABLE_ENTRY: | |
5224 | case BFD_RELOC_VTABLE_INHERIT: | |
5225 | code = fixp->fx_r_type; | |
5226 | break; | |
5227 | default: | |
93382f6d | 5228 | if (fixp->fx_pcrel) |
252b5132 | 5229 | { |
93382f6d AM |
5230 | switch (fixp->fx_size) |
5231 | { | |
5232 | default: | |
b091f402 AM |
5233 | as_bad_where (fixp->fx_file, fixp->fx_line, |
5234 | _("can not do %d byte pc-relative relocation"), | |
5235 | fixp->fx_size); | |
93382f6d AM |
5236 | code = BFD_RELOC_32_PCREL; |
5237 | break; | |
5238 | case 1: code = BFD_RELOC_8_PCREL; break; | |
5239 | case 2: code = BFD_RELOC_16_PCREL; break; | |
5240 | case 4: code = BFD_RELOC_32_PCREL; break; | |
5241 | } | |
5242 | } | |
5243 | else | |
5244 | { | |
5245 | switch (fixp->fx_size) | |
5246 | { | |
5247 | default: | |
b091f402 AM |
5248 | as_bad_where (fixp->fx_file, fixp->fx_line, |
5249 | _("can not do %d byte relocation"), | |
5250 | fixp->fx_size); | |
93382f6d AM |
5251 | code = BFD_RELOC_32; |
5252 | break; | |
5253 | case 1: code = BFD_RELOC_8; break; | |
5254 | case 2: code = BFD_RELOC_16; break; | |
5255 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 5256 | #ifdef BFD64 |
3e73aa7c | 5257 | case 8: code = BFD_RELOC_64; break; |
937149dd | 5258 | #endif |
93382f6d | 5259 | } |
252b5132 RH |
5260 | } |
5261 | break; | |
5262 | } | |
252b5132 RH |
5263 | |
5264 | if (code == BFD_RELOC_32 | |
5265 | && GOT_symbol | |
5266 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c JH |
5267 | { |
5268 | /* We don't support GOTPC on 64bit targets. */ | |
5269 | if (flag_code == CODE_64BIT) | |
bfb32b52 | 5270 | abort (); |
3e73aa7c JH |
5271 | code = BFD_RELOC_386_GOTPC; |
5272 | } | |
252b5132 RH |
5273 | |
5274 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
5275 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
5276 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
5277 | |
5278 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
3e73aa7c JH |
5279 | if (!use_rela_relocations) |
5280 | { | |
5281 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
5282 | vtable entry to be used in the relocation's section offset. */ | |
5283 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5284 | rel->address = fixp->fx_offset; | |
252b5132 | 5285 | |
c6682705 | 5286 | rel->addend = 0; |
3e73aa7c JH |
5287 | } |
5288 | /* Use the rela in 64bit mode. */ | |
252b5132 | 5289 | else |
3e73aa7c | 5290 | { |
062cd5e7 AS |
5291 | if (!fixp->fx_pcrel) |
5292 | rel->addend = fixp->fx_offset; | |
5293 | else | |
5294 | switch (code) | |
5295 | { | |
5296 | case BFD_RELOC_X86_64_PLT32: | |
5297 | case BFD_RELOC_X86_64_GOT32: | |
5298 | case BFD_RELOC_X86_64_GOTPCREL: | |
bffbf940 JJ |
5299 | case BFD_RELOC_X86_64_TLSGD: |
5300 | case BFD_RELOC_X86_64_TLSLD: | |
5301 | case BFD_RELOC_X86_64_GOTTPOFF: | |
062cd5e7 AS |
5302 | rel->addend = fixp->fx_offset - fixp->fx_size; |
5303 | break; | |
5304 | default: | |
5305 | rel->addend = (section->vma | |
5306 | - fixp->fx_size | |
5307 | + fixp->fx_addnumber | |
5308 | + md_pcrel_from (fixp)); | |
5309 | break; | |
5310 | } | |
3e73aa7c JH |
5311 | } |
5312 | ||
252b5132 RH |
5313 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
5314 | if (rel->howto == NULL) | |
5315 | { | |
5316 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 5317 | _("cannot represent relocation type %s"), |
252b5132 RH |
5318 | bfd_get_reloc_code_name (code)); |
5319 | /* Set howto to a garbage value so that we can keep going. */ | |
5320 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
5321 | assert (rel->howto != NULL); | |
5322 | } | |
5323 | ||
5324 | return rel; | |
5325 | } | |
5326 | ||
29b0f896 | 5327 | #else /* !BFD_ASSEMBLER */ |
252b5132 RH |
5328 | |
5329 | #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) | |
5330 | void | |
5331 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) | |
5332 | char *where; | |
5333 | fixS *fixP; | |
5334 | relax_addressT segment_address_in_file; | |
5335 | { | |
47926f60 KH |
5336 | /* In: length of relocation (or of address) in chars: 1, 2 or 4. |
5337 | Out: GNU LD relocation length code: 0, 1, or 2. */ | |
252b5132 | 5338 | |
47926f60 | 5339 | static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 }; |
252b5132 RH |
5340 | long r_symbolnum; |
5341 | ||
5342 | know (fixP->fx_addsy != NULL); | |
5343 | ||
5344 | md_number_to_chars (where, | |
5345 | (valueT) (fixP->fx_frag->fr_address | |
5346 | + fixP->fx_where - segment_address_in_file), | |
5347 | 4); | |
5348 | ||
5349 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) | |
5350 | ? S_GET_TYPE (fixP->fx_addsy) | |
5351 | : fixP->fx_addsy->sy_number); | |
5352 | ||
5353 | where[6] = (r_symbolnum >> 16) & 0x0ff; | |
5354 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
5355 | where[4] = r_symbolnum & 0x0ff; | |
5356 | where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) | |
5357 | | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) | |
5358 | | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); | |
5359 | } | |
5360 | ||
47926f60 | 5361 | #endif /* OBJ_AOUT or OBJ_BOUT. */ |
252b5132 RH |
5362 | |
5363 | #if defined (I386COFF) | |
5364 | ||
5365 | short | |
5366 | tc_coff_fix2rtype (fixP) | |
5367 | fixS *fixP; | |
5368 | { | |
5369 | if (fixP->fx_r_type == R_IMAGEBASE) | |
5370 | return R_IMAGEBASE; | |
5371 | ||
5372 | return (fixP->fx_pcrel ? | |
5373 | (fixP->fx_size == 1 ? R_PCRBYTE : | |
5374 | fixP->fx_size == 2 ? R_PCRWORD : | |
5375 | R_PCRLONG) : | |
5376 | (fixP->fx_size == 1 ? R_RELBYTE : | |
5377 | fixP->fx_size == 2 ? R_RELWORD : | |
5378 | R_DIR32)); | |
5379 | } | |
5380 | ||
5381 | int | |
5382 | tc_coff_sizemachdep (frag) | |
5383 | fragS *frag; | |
5384 | { | |
5385 | if (frag->fr_next) | |
5386 | return (frag->fr_next->fr_address - frag->fr_address); | |
5387 | else | |
5388 | return 0; | |
5389 | } | |
5390 | ||
47926f60 | 5391 | #endif /* I386COFF */ |
252b5132 | 5392 | |
29b0f896 | 5393 | #endif /* !BFD_ASSEMBLER */ |
64a0c779 DN |
5394 | \f |
5395 | /* Parse operands using Intel syntax. This implements a recursive descent | |
5396 | parser based on the BNF grammar published in Appendix B of the MASM 6.1 | |
5397 | Programmer's Guide. | |
5398 | ||
5399 | FIXME: We do not recognize the full operand grammar defined in the MASM | |
5400 | documentation. In particular, all the structure/union and | |
5401 | high-level macro operands are missing. | |
5402 | ||
5403 | Uppercase words are terminals, lower case words are non-terminals. | |
5404 | Objects surrounded by double brackets '[[' ']]' are optional. Vertical | |
5405 | bars '|' denote choices. Most grammar productions are implemented in | |
5406 | functions called 'intel_<production>'. | |
5407 | ||
5408 | Initial production is 'expr'. | |
5409 | ||
64a0c779 DN |
5410 | addOp + | - |
5411 | ||
5412 | alpha [a-zA-Z] | |
5413 | ||
5414 | byteRegister AL | AH | BL | BH | CL | CH | DL | DH | |
5415 | ||
5416 | constant digits [[ radixOverride ]] | |
5417 | ||
5418 | dataType BYTE | WORD | DWORD | QWORD | XWORD | |
5419 | ||
5420 | digits decdigit | |
b77a7acd AJ |
5421 | | digits decdigit |
5422 | | digits hexdigit | |
64a0c779 DN |
5423 | |
5424 | decdigit [0-9] | |
5425 | ||
5426 | e05 e05 addOp e06 | |
b77a7acd | 5427 | | e06 |
64a0c779 DN |
5428 | |
5429 | e06 e06 mulOp e09 | |
b77a7acd | 5430 | | e09 |
64a0c779 DN |
5431 | |
5432 | e09 OFFSET e10 | |
5433 | | e09 PTR e10 | |
5434 | | e09 : e10 | |
5435 | | e10 | |
5436 | ||
5437 | e10 e10 [ expr ] | |
b77a7acd | 5438 | | e11 |
64a0c779 DN |
5439 | |
5440 | e11 ( expr ) | |
b77a7acd | 5441 | | [ expr ] |
64a0c779 DN |
5442 | | constant |
5443 | | dataType | |
5444 | | id | |
5445 | | $ | |
5446 | | register | |
5447 | ||
5448 | => expr SHORT e05 | |
b77a7acd | 5449 | | e05 |
64a0c779 DN |
5450 | |
5451 | gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX | |
b77a7acd | 5452 | | BP | EBP | SP | ESP | DI | EDI | SI | ESI |
64a0c779 DN |
5453 | |
5454 | hexdigit a | b | c | d | e | f | |
b77a7acd | 5455 | | A | B | C | D | E | F |
64a0c779 DN |
5456 | |
5457 | id alpha | |
b77a7acd | 5458 | | id alpha |
64a0c779 DN |
5459 | | id decdigit |
5460 | ||
5461 | mulOp * | / | MOD | |
5462 | ||
5463 | quote " | ' | |
5464 | ||
5465 | register specialRegister | |
b77a7acd | 5466 | | gpRegister |
64a0c779 DN |
5467 | | byteRegister |
5468 | ||
5469 | segmentRegister CS | DS | ES | FS | GS | SS | |
5470 | ||
5471 | specialRegister CR0 | CR2 | CR3 | |
b77a7acd | 5472 | | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 |
64a0c779 DN |
5473 | | TR3 | TR4 | TR5 | TR6 | TR7 |
5474 | ||
64a0c779 DN |
5475 | We simplify the grammar in obvious places (e.g., register parsing is |
5476 | done by calling parse_register) and eliminate immediate left recursion | |
5477 | to implement a recursive-descent parser. | |
5478 | ||
5479 | expr SHORT e05 | |
b77a7acd | 5480 | | e05 |
64a0c779 DN |
5481 | |
5482 | e05 e06 e05' | |
5483 | ||
5484 | e05' addOp e06 e05' | |
b77a7acd | 5485 | | Empty |
64a0c779 DN |
5486 | |
5487 | e06 e09 e06' | |
5488 | ||
5489 | e06' mulOp e09 e06' | |
b77a7acd | 5490 | | Empty |
64a0c779 DN |
5491 | |
5492 | e09 OFFSET e10 e09' | |
b77a7acd | 5493 | | e10 e09' |
64a0c779 DN |
5494 | |
5495 | e09' PTR e10 e09' | |
b77a7acd | 5496 | | : e10 e09' |
64a0c779 DN |
5497 | | Empty |
5498 | ||
5499 | e10 e11 e10' | |
5500 | ||
5501 | e10' [ expr ] e10' | |
b77a7acd | 5502 | | Empty |
64a0c779 DN |
5503 | |
5504 | e11 ( expr ) | |
b77a7acd | 5505 | | [ expr ] |
64a0c779 DN |
5506 | | BYTE |
5507 | | WORD | |
5508 | | DWORD | |
5509 | | QWORD | |
5510 | | XWORD | |
5511 | | . | |
5512 | | $ | |
5513 | | register | |
5514 | | id | |
5515 | | constant */ | |
5516 | ||
5517 | /* Parsing structure for the intel syntax parser. Used to implement the | |
5518 | semantic actions for the operand grammar. */ | |
5519 | struct intel_parser_s | |
5520 | { | |
5521 | char *op_string; /* The string being parsed. */ | |
5522 | int got_a_float; /* Whether the operand is a float. */ | |
4a1805b1 | 5523 | int op_modifier; /* Operand modifier. */ |
64a0c779 DN |
5524 | int is_mem; /* 1 if operand is memory reference. */ |
5525 | const reg_entry *reg; /* Last register reference found. */ | |
5526 | char *disp; /* Displacement string being built. */ | |
5527 | }; | |
5528 | ||
5529 | static struct intel_parser_s intel_parser; | |
5530 | ||
5531 | /* Token structure for parsing intel syntax. */ | |
5532 | struct intel_token | |
5533 | { | |
5534 | int code; /* Token code. */ | |
5535 | const reg_entry *reg; /* Register entry for register tokens. */ | |
5536 | char *str; /* String representation. */ | |
5537 | }; | |
5538 | ||
5539 | static struct intel_token cur_token, prev_token; | |
5540 | ||
50705ef4 AM |
5541 | /* Token codes for the intel parser. Since T_SHORT is already used |
5542 | by COFF, undefine it first to prevent a warning. */ | |
64a0c779 DN |
5543 | #define T_NIL -1 |
5544 | #define T_CONST 1 | |
5545 | #define T_REG 2 | |
5546 | #define T_BYTE 3 | |
5547 | #define T_WORD 4 | |
5548 | #define T_DWORD 5 | |
5549 | #define T_QWORD 6 | |
5550 | #define T_XWORD 7 | |
50705ef4 | 5551 | #undef T_SHORT |
64a0c779 DN |
5552 | #define T_SHORT 8 |
5553 | #define T_OFFSET 9 | |
5554 | #define T_PTR 10 | |
5555 | #define T_ID 11 | |
5556 | ||
5557 | /* Prototypes for intel parser functions. */ | |
5558 | static int intel_match_token PARAMS ((int code)); | |
cce0cbdc DN |
5559 | static void intel_get_token PARAMS ((void)); |
5560 | static void intel_putback_token PARAMS ((void)); | |
5561 | static int intel_expr PARAMS ((void)); | |
5562 | static int intel_e05 PARAMS ((void)); | |
5563 | static int intel_e05_1 PARAMS ((void)); | |
5564 | static int intel_e06 PARAMS ((void)); | |
5565 | static int intel_e06_1 PARAMS ((void)); | |
5566 | static int intel_e09 PARAMS ((void)); | |
5567 | static int intel_e09_1 PARAMS ((void)); | |
5568 | static int intel_e10 PARAMS ((void)); | |
5569 | static int intel_e10_1 PARAMS ((void)); | |
5570 | static int intel_e11 PARAMS ((void)); | |
64a0c779 | 5571 | |
64a0c779 DN |
5572 | static int |
5573 | i386_intel_operand (operand_string, got_a_float) | |
5574 | char *operand_string; | |
5575 | int got_a_float; | |
5576 | { | |
5577 | int ret; | |
5578 | char *p; | |
5579 | ||
5580 | /* Initialize token holders. */ | |
5581 | cur_token.code = prev_token.code = T_NIL; | |
5582 | cur_token.reg = prev_token.reg = NULL; | |
5583 | cur_token.str = prev_token.str = NULL; | |
5584 | ||
5585 | /* Initialize parser structure. */ | |
e5cb08ac | 5586 | p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1); |
64a0c779 DN |
5587 | if (p == NULL) |
5588 | abort (); | |
5589 | strcpy (intel_parser.op_string, operand_string); | |
5590 | intel_parser.got_a_float = got_a_float; | |
5591 | intel_parser.op_modifier = -1; | |
5592 | intel_parser.is_mem = 0; | |
5593 | intel_parser.reg = NULL; | |
e5cb08ac | 5594 | intel_parser.disp = (char *) malloc (strlen (operand_string) + 1); |
64a0c779 DN |
5595 | if (intel_parser.disp == NULL) |
5596 | abort (); | |
5597 | intel_parser.disp[0] = '\0'; | |
5598 | ||
5599 | /* Read the first token and start the parser. */ | |
5600 | intel_get_token (); | |
5601 | ret = intel_expr (); | |
5602 | ||
5603 | if (ret) | |
5604 | { | |
5605 | /* If we found a memory reference, hand it over to i386_displacement | |
5606 | to fill in the rest of the operand fields. */ | |
5607 | if (intel_parser.is_mem) | |
5608 | { | |
5609 | if ((i.mem_operands == 1 | |
5610 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
5611 | || i.mem_operands == 2) | |
5612 | { | |
5613 | as_bad (_("too many memory references for '%s'"), | |
5614 | current_templates->start->name); | |
5615 | ret = 0; | |
5616 | } | |
5617 | else | |
5618 | { | |
5619 | char *s = intel_parser.disp; | |
5620 | i.mem_operands++; | |
5621 | ||
5622 | /* Add the displacement expression. */ | |
5623 | if (*s != '\0') | |
5624 | ret = i386_displacement (s, s + strlen (s)) | |
5625 | && i386_index_check (s); | |
5626 | } | |
5627 | } | |
5628 | ||
5629 | /* Constant and OFFSET expressions are handled by i386_immediate. */ | |
5630 | else if (intel_parser.op_modifier == OFFSET_FLAT | |
5631 | || intel_parser.reg == NULL) | |
5632 | ret = i386_immediate (intel_parser.disp); | |
5633 | } | |
5634 | ||
5635 | free (p); | |
5636 | free (intel_parser.disp); | |
5637 | ||
5638 | return ret; | |
5639 | } | |
5640 | ||
64a0c779 | 5641 | /* expr SHORT e05 |
b77a7acd | 5642 | | e05 */ |
64a0c779 DN |
5643 | static int |
5644 | intel_expr () | |
5645 | { | |
5646 | /* expr SHORT e05 */ | |
5647 | if (cur_token.code == T_SHORT) | |
5648 | { | |
5649 | intel_parser.op_modifier = SHORT; | |
5650 | intel_match_token (T_SHORT); | |
5651 | ||
5652 | return (intel_e05 ()); | |
5653 | } | |
5654 | ||
5655 | /* expr e05 */ | |
5656 | else | |
5657 | return intel_e05 (); | |
5658 | } | |
5659 | ||
64a0c779 DN |
5660 | /* e05 e06 e05' |
5661 | ||
4a1805b1 | 5662 | e05' addOp e06 e05' |
64a0c779 DN |
5663 | | Empty */ |
5664 | static int | |
5665 | intel_e05 () | |
5666 | { | |
5667 | return (intel_e06 () && intel_e05_1 ()); | |
5668 | } | |
5669 | ||
5670 | static int | |
5671 | intel_e05_1 () | |
5672 | { | |
5673 | /* e05' addOp e06 e05' */ | |
5674 | if (cur_token.code == '+' || cur_token.code == '-') | |
5675 | { | |
5676 | strcat (intel_parser.disp, cur_token.str); | |
5677 | intel_match_token (cur_token.code); | |
5678 | ||
5679 | return (intel_e06 () && intel_e05_1 ()); | |
5680 | } | |
5681 | ||
5682 | /* e05' Empty */ | |
5683 | else | |
5684 | return 1; | |
4a1805b1 | 5685 | } |
64a0c779 DN |
5686 | |
5687 | /* e06 e09 e06' | |
5688 | ||
5689 | e06' mulOp e09 e06' | |
b77a7acd | 5690 | | Empty */ |
64a0c779 DN |
5691 | static int |
5692 | intel_e06 () | |
5693 | { | |
5694 | return (intel_e09 () && intel_e06_1 ()); | |
5695 | } | |
5696 | ||
5697 | static int | |
5698 | intel_e06_1 () | |
5699 | { | |
5700 | /* e06' mulOp e09 e06' */ | |
5701 | if (cur_token.code == '*' || cur_token.code == '/') | |
5702 | { | |
5703 | strcat (intel_parser.disp, cur_token.str); | |
5704 | intel_match_token (cur_token.code); | |
5705 | ||
5706 | return (intel_e09 () && intel_e06_1 ()); | |
5707 | } | |
4a1805b1 | 5708 | |
64a0c779 | 5709 | /* e06' Empty */ |
4a1805b1 | 5710 | else |
64a0c779 DN |
5711 | return 1; |
5712 | } | |
5713 | ||
64a0c779 | 5714 | /* e09 OFFSET e10 e09' |
b77a7acd | 5715 | | e10 e09' |
64a0c779 DN |
5716 | |
5717 | e09' PTR e10 e09' | |
b77a7acd | 5718 | | : e10 e09' |
64a0c779 DN |
5719 | | Empty */ |
5720 | static int | |
5721 | intel_e09 () | |
5722 | { | |
5723 | /* e09 OFFSET e10 e09' */ | |
5724 | if (cur_token.code == T_OFFSET) | |
5725 | { | |
5726 | intel_parser.is_mem = 0; | |
5727 | intel_parser.op_modifier = OFFSET_FLAT; | |
5728 | intel_match_token (T_OFFSET); | |
5729 | ||
5730 | return (intel_e10 () && intel_e09_1 ()); | |
5731 | } | |
5732 | ||
5733 | /* e09 e10 e09' */ | |
5734 | else | |
5735 | return (intel_e10 () && intel_e09_1 ()); | |
5736 | } | |
5737 | ||
5738 | static int | |
5739 | intel_e09_1 () | |
5740 | { | |
5741 | /* e09' PTR e10 e09' */ | |
5742 | if (cur_token.code == T_PTR) | |
5743 | { | |
5744 | if (prev_token.code == T_BYTE) | |
5745 | i.suffix = BYTE_MNEM_SUFFIX; | |
5746 | ||
5747 | else if (prev_token.code == T_WORD) | |
5748 | { | |
5749 | if (intel_parser.got_a_float == 2) /* "fi..." */ | |
5750 | i.suffix = SHORT_MNEM_SUFFIX; | |
5751 | else | |
5752 | i.suffix = WORD_MNEM_SUFFIX; | |
5753 | } | |
5754 | ||
5755 | else if (prev_token.code == T_DWORD) | |
5756 | { | |
5757 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
5758 | i.suffix = SHORT_MNEM_SUFFIX; | |
5759 | else | |
5760 | i.suffix = LONG_MNEM_SUFFIX; | |
5761 | } | |
5762 | ||
5763 | else if (prev_token.code == T_QWORD) | |
f16b83df JH |
5764 | { |
5765 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
5766 | i.suffix = LONG_MNEM_SUFFIX; | |
5767 | else | |
3e73aa7c | 5768 | i.suffix = QWORD_MNEM_SUFFIX; |
f16b83df | 5769 | } |
64a0c779 DN |
5770 | |
5771 | else if (prev_token.code == T_XWORD) | |
5772 | i.suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
5773 | ||
5774 | else | |
5775 | { | |
5776 | as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str); | |
5777 | return 0; | |
5778 | } | |
5779 | ||
5780 | intel_match_token (T_PTR); | |
5781 | ||
5782 | return (intel_e10 () && intel_e09_1 ()); | |
5783 | } | |
5784 | ||
5785 | /* e09 : e10 e09' */ | |
5786 | else if (cur_token.code == ':') | |
5787 | { | |
21d6c4af DN |
5788 | /* Mark as a memory operand only if it's not already known to be an |
5789 | offset expression. */ | |
5790 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5791 | intel_parser.is_mem = 1; | |
64a0c779 DN |
5792 | |
5793 | return (intel_match_token (':') && intel_e10 () && intel_e09_1 ()); | |
5794 | } | |
5795 | ||
5796 | /* e09' Empty */ | |
5797 | else | |
5798 | return 1; | |
5799 | } | |
5800 | ||
5801 | /* e10 e11 e10' | |
5802 | ||
5803 | e10' [ expr ] e10' | |
b77a7acd | 5804 | | Empty */ |
64a0c779 DN |
5805 | static int |
5806 | intel_e10 () | |
5807 | { | |
5808 | return (intel_e11 () && intel_e10_1 ()); | |
5809 | } | |
5810 | ||
5811 | static int | |
5812 | intel_e10_1 () | |
5813 | { | |
5814 | /* e10' [ expr ] e10' */ | |
5815 | if (cur_token.code == '[') | |
5816 | { | |
5817 | intel_match_token ('['); | |
21d6c4af DN |
5818 | |
5819 | /* Mark as a memory operand only if it's not already known to be an | |
5820 | offset expression. If it's an offset expression, we need to keep | |
5821 | the brace in. */ | |
5822 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5823 | intel_parser.is_mem = 1; | |
5824 | else | |
5825 | strcat (intel_parser.disp, "["); | |
4a1805b1 | 5826 | |
64a0c779 | 5827 | /* Add a '+' to the displacement string if necessary. */ |
21d6c4af DN |
5828 | if (*intel_parser.disp != '\0' |
5829 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
64a0c779 DN |
5830 | strcat (intel_parser.disp, "+"); |
5831 | ||
21d6c4af DN |
5832 | if (intel_expr () && intel_match_token (']')) |
5833 | { | |
5834 | /* Preserve brackets when the operand is an offset expression. */ | |
5835 | if (intel_parser.op_modifier == OFFSET_FLAT) | |
5836 | strcat (intel_parser.disp, "]"); | |
5837 | ||
5838 | return intel_e10_1 (); | |
5839 | } | |
5840 | else | |
5841 | return 0; | |
64a0c779 DN |
5842 | } |
5843 | ||
5844 | /* e10' Empty */ | |
5845 | else | |
5846 | return 1; | |
5847 | } | |
5848 | ||
64a0c779 | 5849 | /* e11 ( expr ) |
b77a7acd | 5850 | | [ expr ] |
64a0c779 DN |
5851 | | BYTE |
5852 | | WORD | |
5853 | | DWORD | |
5854 | | QWORD | |
5855 | | XWORD | |
4a1805b1 | 5856 | | $ |
64a0c779 DN |
5857 | | . |
5858 | | register | |
5859 | | id | |
5860 | | constant */ | |
5861 | static int | |
5862 | intel_e11 () | |
5863 | { | |
5864 | /* e11 ( expr ) */ | |
5865 | if (cur_token.code == '(') | |
5866 | { | |
5867 | intel_match_token ('('); | |
5868 | strcat (intel_parser.disp, "("); | |
5869 | ||
5870 | if (intel_expr () && intel_match_token (')')) | |
e5cb08ac KH |
5871 | { |
5872 | strcat (intel_parser.disp, ")"); | |
5873 | return 1; | |
5874 | } | |
64a0c779 DN |
5875 | else |
5876 | return 0; | |
5877 | } | |
5878 | ||
5879 | /* e11 [ expr ] */ | |
5880 | else if (cur_token.code == '[') | |
5881 | { | |
5882 | intel_match_token ('['); | |
21d6c4af DN |
5883 | |
5884 | /* Mark as a memory operand only if it's not already known to be an | |
5885 | offset expression. If it's an offset expression, we need to keep | |
5886 | the brace in. */ | |
5887 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5888 | intel_parser.is_mem = 1; | |
5889 | else | |
5890 | strcat (intel_parser.disp, "["); | |
4a1805b1 | 5891 | |
64a0c779 DN |
5892 | /* Operands for jump/call inside brackets denote absolute addresses. */ |
5893 | if (current_templates->start->opcode_modifier & Jump | |
5894 | || current_templates->start->opcode_modifier & JumpDword | |
5895 | || current_templates->start->opcode_modifier & JumpByte | |
5896 | || current_templates->start->opcode_modifier & JumpInterSegment) | |
5897 | i.types[this_operand] |= JumpAbsolute; | |
5898 | ||
5899 | /* Add a '+' to the displacement string if necessary. */ | |
21d6c4af DN |
5900 | if (*intel_parser.disp != '\0' |
5901 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
64a0c779 DN |
5902 | strcat (intel_parser.disp, "+"); |
5903 | ||
21d6c4af DN |
5904 | if (intel_expr () && intel_match_token (']')) |
5905 | { | |
5906 | /* Preserve brackets when the operand is an offset expression. */ | |
5907 | if (intel_parser.op_modifier == OFFSET_FLAT) | |
5908 | strcat (intel_parser.disp, "]"); | |
5909 | ||
5910 | return 1; | |
5911 | } | |
5912 | else | |
5913 | return 0; | |
64a0c779 DN |
5914 | } |
5915 | ||
4a1805b1 | 5916 | /* e11 BYTE |
64a0c779 DN |
5917 | | WORD |
5918 | | DWORD | |
5919 | | QWORD | |
5920 | | XWORD */ | |
5921 | else if (cur_token.code == T_BYTE | |
5922 | || cur_token.code == T_WORD | |
5923 | || cur_token.code == T_DWORD | |
5924 | || cur_token.code == T_QWORD | |
5925 | || cur_token.code == T_XWORD) | |
5926 | { | |
5927 | intel_match_token (cur_token.code); | |
5928 | ||
5929 | return 1; | |
5930 | } | |
5931 | ||
5932 | /* e11 $ | |
5933 | | . */ | |
5934 | else if (cur_token.code == '$' || cur_token.code == '.') | |
5935 | { | |
5936 | strcat (intel_parser.disp, cur_token.str); | |
5937 | intel_match_token (cur_token.code); | |
21d6c4af DN |
5938 | |
5939 | /* Mark as a memory operand only if it's not already known to be an | |
5940 | offset expression. */ | |
5941 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5942 | intel_parser.is_mem = 1; | |
64a0c779 DN |
5943 | |
5944 | return 1; | |
5945 | } | |
5946 | ||
5947 | /* e11 register */ | |
5948 | else if (cur_token.code == T_REG) | |
5949 | { | |
5950 | const reg_entry *reg = intel_parser.reg = cur_token.reg; | |
5951 | ||
5952 | intel_match_token (T_REG); | |
5953 | ||
5954 | /* Check for segment change. */ | |
5955 | if (cur_token.code == ':') | |
5956 | { | |
5957 | if (reg->reg_type & (SReg2 | SReg3)) | |
5958 | { | |
5959 | switch (reg->reg_num) | |
5960 | { | |
5961 | case 0: | |
5962 | i.seg[i.mem_operands] = &es; | |
5963 | break; | |
5964 | case 1: | |
5965 | i.seg[i.mem_operands] = &cs; | |
5966 | break; | |
5967 | case 2: | |
5968 | i.seg[i.mem_operands] = &ss; | |
5969 | break; | |
5970 | case 3: | |
5971 | i.seg[i.mem_operands] = &ds; | |
5972 | break; | |
5973 | case 4: | |
5974 | i.seg[i.mem_operands] = &fs; | |
5975 | break; | |
5976 | case 5: | |
5977 | i.seg[i.mem_operands] = &gs; | |
5978 | break; | |
5979 | } | |
5980 | } | |
5981 | else | |
5982 | { | |
5983 | as_bad (_("`%s' is not a valid segment register"), reg->reg_name); | |
5984 | return 0; | |
5985 | } | |
5986 | } | |
5987 | ||
5988 | /* Not a segment register. Check for register scaling. */ | |
5989 | else if (cur_token.code == '*') | |
5990 | { | |
5991 | if (!intel_parser.is_mem) | |
5992 | { | |
5993 | as_bad (_("Register scaling only allowed in memory operands.")); | |
5994 | return 0; | |
5995 | } | |
5996 | ||
4a1805b1 | 5997 | /* What follows must be a valid scale. */ |
64a0c779 DN |
5998 | if (intel_match_token ('*') |
5999 | && strchr ("01248", *cur_token.str)) | |
6000 | { | |
6001 | i.index_reg = reg; | |
6002 | i.types[this_operand] |= BaseIndex; | |
6003 | ||
6004 | /* Set the scale after setting the register (otherwise, | |
6005 | i386_scale will complain) */ | |
6006 | i386_scale (cur_token.str); | |
6007 | intel_match_token (T_CONST); | |
6008 | } | |
6009 | else | |
6010 | { | |
6011 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
6012 | cur_token.str); | |
6013 | return 0; | |
6014 | } | |
6015 | } | |
6016 | ||
6017 | /* No scaling. If this is a memory operand, the register is either a | |
6018 | base register (first occurrence) or an index register (second | |
6019 | occurrence). */ | |
6020 | else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3))) | |
6021 | { | |
6022 | if (i.base_reg && i.index_reg) | |
6023 | { | |
6024 | as_bad (_("Too many register references in memory operand.\n")); | |
6025 | return 0; | |
6026 | } | |
6027 | ||
6028 | if (i.base_reg == NULL) | |
6029 | i.base_reg = reg; | |
6030 | else | |
6031 | i.index_reg = reg; | |
6032 | ||
6033 | i.types[this_operand] |= BaseIndex; | |
6034 | } | |
6035 | ||
6036 | /* Offset modifier. Add the register to the displacement string to be | |
6037 | parsed as an immediate expression after we're done. */ | |
6038 | else if (intel_parser.op_modifier == OFFSET_FLAT) | |
6039 | strcat (intel_parser.disp, reg->reg_name); | |
4a1805b1 | 6040 | |
64a0c779 DN |
6041 | /* It's neither base nor index nor offset. */ |
6042 | else | |
6043 | { | |
6044 | i.types[this_operand] |= reg->reg_type & ~BaseIndex; | |
6045 | i.op[this_operand].regs = reg; | |
6046 | i.reg_operands++; | |
6047 | } | |
6048 | ||
6049 | /* Since registers are not part of the displacement string (except | |
6050 | when we're parsing offset operands), we may need to remove any | |
6051 | preceding '+' from the displacement string. */ | |
6052 | if (*intel_parser.disp != '\0' | |
6053 | && intel_parser.op_modifier != OFFSET_FLAT) | |
6054 | { | |
6055 | char *s = intel_parser.disp; | |
6056 | s += strlen (s) - 1; | |
6057 | if (*s == '+') | |
6058 | *s = '\0'; | |
6059 | } | |
6060 | ||
6061 | return 1; | |
6062 | } | |
4a1805b1 | 6063 | |
64a0c779 DN |
6064 | /* e11 id */ |
6065 | else if (cur_token.code == T_ID) | |
6066 | { | |
6067 | /* Add the identifier to the displacement string. */ | |
6068 | strcat (intel_parser.disp, cur_token.str); | |
6069 | intel_match_token (T_ID); | |
6070 | ||
6071 | /* The identifier represents a memory reference only if it's not | |
6072 | preceded by an offset modifier. */ | |
21d6c4af | 6073 | if (intel_parser.op_modifier != OFFSET_FLAT) |
64a0c779 DN |
6074 | intel_parser.is_mem = 1; |
6075 | ||
6076 | return 1; | |
6077 | } | |
6078 | ||
6079 | /* e11 constant */ | |
6080 | else if (cur_token.code == T_CONST | |
e5cb08ac | 6081 | || cur_token.code == '-' |
64a0c779 DN |
6082 | || cur_token.code == '+') |
6083 | { | |
6084 | char *save_str; | |
6085 | ||
6086 | /* Allow constants that start with `+' or `-'. */ | |
6087 | if (cur_token.code == '-' || cur_token.code == '+') | |
6088 | { | |
6089 | strcat (intel_parser.disp, cur_token.str); | |
6090 | intel_match_token (cur_token.code); | |
6091 | if (cur_token.code != T_CONST) | |
6092 | { | |
6093 | as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"), | |
6094 | cur_token.str); | |
6095 | return 0; | |
6096 | } | |
6097 | } | |
6098 | ||
e5cb08ac | 6099 | save_str = (char *) malloc (strlen (cur_token.str) + 1); |
64a0c779 | 6100 | if (save_str == NULL) |
bc805888 | 6101 | abort (); |
64a0c779 DN |
6102 | strcpy (save_str, cur_token.str); |
6103 | ||
6104 | /* Get the next token to check for register scaling. */ | |
6105 | intel_match_token (cur_token.code); | |
6106 | ||
6107 | /* Check if this constant is a scaling factor for an index register. */ | |
6108 | if (cur_token.code == '*') | |
6109 | { | |
6110 | if (intel_match_token ('*') && cur_token.code == T_REG) | |
6111 | { | |
6112 | if (!intel_parser.is_mem) | |
6113 | { | |
6114 | as_bad (_("Register scaling only allowed in memory operands.")); | |
6115 | return 0; | |
6116 | } | |
6117 | ||
4a1805b1 | 6118 | /* The constant is followed by `* reg', so it must be |
64a0c779 DN |
6119 | a valid scale. */ |
6120 | if (strchr ("01248", *save_str)) | |
6121 | { | |
6122 | i.index_reg = cur_token.reg; | |
6123 | i.types[this_operand] |= BaseIndex; | |
6124 | ||
6125 | /* Set the scale after setting the register (otherwise, | |
6126 | i386_scale will complain) */ | |
6127 | i386_scale (save_str); | |
6128 | intel_match_token (T_REG); | |
6129 | ||
6130 | /* Since registers are not part of the displacement | |
6131 | string, we may need to remove any preceding '+' from | |
6132 | the displacement string. */ | |
6133 | if (*intel_parser.disp != '\0') | |
6134 | { | |
6135 | char *s = intel_parser.disp; | |
6136 | s += strlen (s) - 1; | |
6137 | if (*s == '+') | |
6138 | *s = '\0'; | |
6139 | } | |
6140 | ||
6141 | free (save_str); | |
6142 | ||
6143 | return 1; | |
6144 | } | |
6145 | else | |
6146 | return 0; | |
6147 | } | |
6148 | ||
6149 | /* The constant was not used for register scaling. Since we have | |
6150 | already consumed the token following `*' we now need to put it | |
6151 | back in the stream. */ | |
6152 | else | |
6153 | intel_putback_token (); | |
6154 | } | |
6155 | ||
6156 | /* Add the constant to the displacement string. */ | |
6157 | strcat (intel_parser.disp, save_str); | |
6158 | free (save_str); | |
6159 | ||
6160 | return 1; | |
6161 | } | |
6162 | ||
64a0c779 DN |
6163 | as_bad (_("Unrecognized token '%s'"), cur_token.str); |
6164 | return 0; | |
6165 | } | |
6166 | ||
64a0c779 DN |
6167 | /* Match the given token against cur_token. If they match, read the next |
6168 | token from the operand string. */ | |
6169 | static int | |
6170 | intel_match_token (code) | |
e5cb08ac | 6171 | int code; |
64a0c779 DN |
6172 | { |
6173 | if (cur_token.code == code) | |
6174 | { | |
6175 | intel_get_token (); | |
6176 | return 1; | |
6177 | } | |
6178 | else | |
6179 | { | |
6180 | as_bad (_("Unexpected token `%s'\n"), cur_token.str); | |
6181 | return 0; | |
6182 | } | |
6183 | } | |
6184 | ||
64a0c779 DN |
6185 | /* Read a new token from intel_parser.op_string and store it in cur_token. */ |
6186 | static void | |
6187 | intel_get_token () | |
6188 | { | |
6189 | char *end_op; | |
6190 | const reg_entry *reg; | |
6191 | struct intel_token new_token; | |
6192 | ||
6193 | new_token.code = T_NIL; | |
6194 | new_token.reg = NULL; | |
6195 | new_token.str = NULL; | |
6196 | ||
4a1805b1 | 6197 | /* Free the memory allocated to the previous token and move |
64a0c779 DN |
6198 | cur_token to prev_token. */ |
6199 | if (prev_token.str) | |
6200 | free (prev_token.str); | |
6201 | ||
6202 | prev_token = cur_token; | |
6203 | ||
6204 | /* Skip whitespace. */ | |
6205 | while (is_space_char (*intel_parser.op_string)) | |
6206 | intel_parser.op_string++; | |
6207 | ||
6208 | /* Return an empty token if we find nothing else on the line. */ | |
6209 | if (*intel_parser.op_string == '\0') | |
6210 | { | |
6211 | cur_token = new_token; | |
6212 | return; | |
6213 | } | |
6214 | ||
6215 | /* The new token cannot be larger than the remainder of the operand | |
6216 | string. */ | |
e5cb08ac | 6217 | new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1); |
64a0c779 | 6218 | if (new_token.str == NULL) |
bc805888 | 6219 | abort (); |
64a0c779 DN |
6220 | new_token.str[0] = '\0'; |
6221 | ||
6222 | if (strchr ("0123456789", *intel_parser.op_string)) | |
6223 | { | |
6224 | char *p = new_token.str; | |
6225 | char *q = intel_parser.op_string; | |
6226 | new_token.code = T_CONST; | |
6227 | ||
6228 | /* Allow any kind of identifier char to encompass floating point and | |
6229 | hexadecimal numbers. */ | |
6230 | while (is_identifier_char (*q)) | |
6231 | *p++ = *q++; | |
6232 | *p = '\0'; | |
6233 | ||
6234 | /* Recognize special symbol names [0-9][bf]. */ | |
6235 | if (strlen (intel_parser.op_string) == 2 | |
4a1805b1 | 6236 | && (intel_parser.op_string[1] == 'b' |
64a0c779 DN |
6237 | || intel_parser.op_string[1] == 'f')) |
6238 | new_token.code = T_ID; | |
6239 | } | |
6240 | ||
6241 | else if (strchr ("+-/*:[]()", *intel_parser.op_string)) | |
6242 | { | |
6243 | new_token.code = *intel_parser.op_string; | |
6244 | new_token.str[0] = *intel_parser.op_string; | |
6245 | new_token.str[1] = '\0'; | |
6246 | } | |
6247 | ||
6248 | else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg) | |
6249 | && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)) | |
6250 | { | |
6251 | new_token.code = T_REG; | |
6252 | new_token.reg = reg; | |
6253 | ||
6254 | if (*intel_parser.op_string == REGISTER_PREFIX) | |
6255 | { | |
6256 | new_token.str[0] = REGISTER_PREFIX; | |
6257 | new_token.str[1] = '\0'; | |
6258 | } | |
6259 | ||
6260 | strcat (new_token.str, reg->reg_name); | |
6261 | } | |
6262 | ||
6263 | else if (is_identifier_char (*intel_parser.op_string)) | |
6264 | { | |
6265 | char *p = new_token.str; | |
6266 | char *q = intel_parser.op_string; | |
6267 | ||
6268 | /* A '.' or '$' followed by an identifier char is an identifier. | |
6269 | Otherwise, it's operator '.' followed by an expression. */ | |
6270 | if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) | |
6271 | { | |
6272 | new_token.code = *q; | |
6273 | new_token.str[0] = *q; | |
6274 | new_token.str[1] = '\0'; | |
6275 | } | |
6276 | else | |
6277 | { | |
6278 | while (is_identifier_char (*q) || *q == '@') | |
6279 | *p++ = *q++; | |
6280 | *p = '\0'; | |
6281 | ||
6282 | if (strcasecmp (new_token.str, "BYTE") == 0) | |
6283 | new_token.code = T_BYTE; | |
6284 | ||
6285 | else if (strcasecmp (new_token.str, "WORD") == 0) | |
6286 | new_token.code = T_WORD; | |
6287 | ||
6288 | else if (strcasecmp (new_token.str, "DWORD") == 0) | |
6289 | new_token.code = T_DWORD; | |
6290 | ||
6291 | else if (strcasecmp (new_token.str, "QWORD") == 0) | |
6292 | new_token.code = T_QWORD; | |
6293 | ||
6294 | else if (strcasecmp (new_token.str, "XWORD") == 0) | |
6295 | new_token.code = T_XWORD; | |
6296 | ||
6297 | else if (strcasecmp (new_token.str, "PTR") == 0) | |
6298 | new_token.code = T_PTR; | |
6299 | ||
6300 | else if (strcasecmp (new_token.str, "SHORT") == 0) | |
6301 | new_token.code = T_SHORT; | |
6302 | ||
6303 | else if (strcasecmp (new_token.str, "OFFSET") == 0) | |
6304 | { | |
6305 | new_token.code = T_OFFSET; | |
6306 | ||
6307 | /* ??? This is not mentioned in the MASM grammar but gcc | |
6308 | makes use of it with -mintel-syntax. OFFSET may be | |
6309 | followed by FLAT: */ | |
6310 | if (strncasecmp (q, " FLAT:", 6) == 0) | |
6311 | strcat (new_token.str, " FLAT:"); | |
6312 | } | |
6313 | ||
6314 | /* ??? This is not mentioned in the MASM grammar. */ | |
6315 | else if (strcasecmp (new_token.str, "FLAT") == 0) | |
6316 | new_token.code = T_OFFSET; | |
6317 | ||
6318 | else | |
6319 | new_token.code = T_ID; | |
6320 | } | |
6321 | } | |
6322 | ||
6323 | else | |
6324 | as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string); | |
6325 | ||
6326 | intel_parser.op_string += strlen (new_token.str); | |
6327 | cur_token = new_token; | |
6328 | } | |
6329 | ||
64a0c779 DN |
6330 | /* Put cur_token back into the token stream and make cur_token point to |
6331 | prev_token. */ | |
6332 | static void | |
6333 | intel_putback_token () | |
6334 | { | |
6335 | intel_parser.op_string -= strlen (cur_token.str); | |
6336 | free (cur_token.str); | |
6337 | cur_token = prev_token; | |
4a1805b1 | 6338 | |
64a0c779 DN |
6339 | /* Forget prev_token. */ |
6340 | prev_token.code = T_NIL; | |
6341 | prev_token.reg = NULL; | |
6342 | prev_token.str = NULL; | |
6343 | } | |
54cfded0 | 6344 | |
a4447b93 | 6345 | int |
54cfded0 AM |
6346 | tc_x86_regname_to_dw2regnum (const char *regname) |
6347 | { | |
6348 | unsigned int regnum; | |
6349 | unsigned int regnames_count; | |
6350 | char *regnames_32[] = | |
6351 | { | |
a4447b93 RH |
6352 | "eax", "ecx", "edx", "ebx", |
6353 | "esp", "ebp", "esi", "edi", | |
54cfded0 AM |
6354 | "eip" |
6355 | }; | |
6356 | char *regnames_64[] = | |
6357 | { | |
6358 | "rax", "rbx", "rcx", "rdx", | |
6359 | "rdi", "rsi", "rbp", "rsp", | |
6360 | "r8", "r9", "r10", "r11", | |
6361 | "r12", "r13", "r14", "r15", | |
6362 | "rip" | |
6363 | }; | |
6364 | char **regnames; | |
6365 | ||
6366 | if (flag_code == CODE_64BIT) | |
6367 | { | |
6368 | regnames = regnames_64; | |
6369 | regnames_count = sizeof (regnames_64); | |
6370 | } | |
6371 | else | |
6372 | { | |
6373 | regnames = regnames_32; | |
6374 | regnames_count = sizeof (regnames_32); | |
6375 | } | |
6376 | ||
6377 | for (regnum = 0; regnum < regnames_count; regnum++) | |
6378 | if (strcmp (regname, regnames[regnum]) == 0) | |
6379 | return regnum; | |
6380 | ||
54cfded0 AM |
6381 | return -1; |
6382 | } | |
6383 | ||
6384 | void | |
6385 | tc_x86_frame_initial_instructions (void) | |
6386 | { | |
a4447b93 RH |
6387 | static unsigned int sp_regno; |
6388 | ||
6389 | if (!sp_regno) | |
6390 | sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT | |
6391 | ? "rsp" : "esp"); | |
6392 | ||
6393 | cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment); | |
6394 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 6395 | } |