Commit | Line | Data |
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252b5132 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
f7e42eb4 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
0f10071e | 3 | 2000, 2001, 2002, 2003, 2004 |
47926f60 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
20 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
21 | 02111-1307, USA. */ | |
22 | ||
47926f60 KH |
23 | /* Intel 80386 machine specific gas. |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 25 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
27 | Bugs & suggestions are completely welcome. This is free software. |
28 | Please help us make it better. */ | |
252b5132 | 29 | |
252b5132 | 30 | #include "as.h" |
3882b010 | 31 | #include "safe-ctype.h" |
252b5132 | 32 | #include "subsegs.h" |
316e2c05 | 33 | #include "dwarf2dbg.h" |
54cfded0 | 34 | #include "dw2gencfi.h" |
252b5132 | 35 | #include "opcode/i386.h" |
d2b2c203 | 36 | #include "elf/x86-64.h" |
252b5132 | 37 | |
252b5132 RH |
38 | #ifndef REGISTER_WARNINGS |
39 | #define REGISTER_WARNINGS 1 | |
40 | #endif | |
41 | ||
c3332e24 | 42 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 43 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
44 | #endif |
45 | ||
252b5132 RH |
46 | #ifndef SCALE1_WHEN_NO_INDEX |
47 | /* Specifying a scale factor besides 1 when there is no index is | |
48 | futile. eg. `mov (%ebx,2),%al' does exactly the same as | |
49 | `mov (%ebx),%al'. To slavishly follow what the programmer | |
50 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ | |
51 | #define SCALE1_WHEN_NO_INDEX 1 | |
52 | #endif | |
53 | ||
29b0f896 AM |
54 | #ifndef DEFAULT_ARCH |
55 | #define DEFAULT_ARCH "i386" | |
246fcdee | 56 | #endif |
252b5132 | 57 | |
edde18a5 AM |
58 | #ifndef INLINE |
59 | #if __GNUC__ >= 2 | |
60 | #define INLINE __inline__ | |
61 | #else | |
62 | #define INLINE | |
63 | #endif | |
64 | #endif | |
65 | ||
29b0f896 AM |
66 | static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int)); |
67 | static INLINE int fits_in_signed_byte PARAMS ((offsetT)); | |
68 | static INLINE int fits_in_unsigned_byte PARAMS ((offsetT)); | |
69 | static INLINE int fits_in_unsigned_word PARAMS ((offsetT)); | |
70 | static INLINE int fits_in_signed_word PARAMS ((offsetT)); | |
71 | static INLINE int fits_in_unsigned_long PARAMS ((offsetT)); | |
72 | static INLINE int fits_in_signed_long PARAMS ((offsetT)); | |
847f7ad4 AM |
73 | static int smallest_imm_type PARAMS ((offsetT)); |
74 | static offsetT offset_in_range PARAMS ((offsetT, int)); | |
252b5132 | 75 | static int add_prefix PARAMS ((unsigned int)); |
3e73aa7c | 76 | static void set_code_flag PARAMS ((int)); |
47926f60 | 77 | static void set_16bit_gcc_code_flag PARAMS ((int)); |
252b5132 | 78 | static void set_intel_syntax PARAMS ((int)); |
e413e4e9 | 79 | static void set_cpu_arch PARAMS ((int)); |
6482c264 NC |
80 | #ifdef TE_PE |
81 | static void pe_directive_secrel PARAMS ((int)); | |
82 | #endif | |
29b0f896 AM |
83 | static char *output_invalid PARAMS ((int c)); |
84 | static int i386_operand PARAMS ((char *operand_string)); | |
85 | static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); | |
86 | static const reg_entry *parse_register PARAMS ((char *reg_string, | |
87 | char **end_op)); | |
88 | static char *parse_insn PARAMS ((char *, char *)); | |
89 | static char *parse_operands PARAMS ((char *, const char *)); | |
90 | static void swap_operands PARAMS ((void)); | |
91 | static void optimize_imm PARAMS ((void)); | |
92 | static void optimize_disp PARAMS ((void)); | |
93 | static int match_template PARAMS ((void)); | |
94 | static int check_string PARAMS ((void)); | |
95 | static int process_suffix PARAMS ((void)); | |
96 | static int check_byte_reg PARAMS ((void)); | |
97 | static int check_long_reg PARAMS ((void)); | |
98 | static int check_qword_reg PARAMS ((void)); | |
99 | static int check_word_reg PARAMS ((void)); | |
100 | static int finalize_imm PARAMS ((void)); | |
101 | static int process_operands PARAMS ((void)); | |
102 | static const seg_entry *build_modrm_byte PARAMS ((void)); | |
103 | static void output_insn PARAMS ((void)); | |
104 | static void output_branch PARAMS ((void)); | |
105 | static void output_jump PARAMS ((void)); | |
106 | static void output_interseg_jump PARAMS ((void)); | |
2bbd9c25 JJ |
107 | static void output_imm PARAMS ((fragS *insn_start_frag, |
108 | offsetT insn_start_off)); | |
109 | static void output_disp PARAMS ((fragS *insn_start_frag, | |
110 | offsetT insn_start_off)); | |
29b0f896 AM |
111 | #ifndef I386COFF |
112 | static void s_bss PARAMS ((int)); | |
252b5132 RH |
113 | #endif |
114 | ||
a847613f | 115 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 116 | |
252b5132 | 117 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 118 | i386_insn. */ |
252b5132 | 119 | |
520dc8e8 AM |
120 | union i386_op |
121 | { | |
122 | expressionS *disps; | |
123 | expressionS *imms; | |
124 | const reg_entry *regs; | |
125 | }; | |
126 | ||
252b5132 RH |
127 | struct _i386_insn |
128 | { | |
47926f60 | 129 | /* TM holds the template for the insn were currently assembling. */ |
252b5132 RH |
130 | template tm; |
131 | ||
132 | /* SUFFIX holds the instruction mnemonic suffix if given. | |
133 | (e.g. 'l' for 'movl') */ | |
134 | char suffix; | |
135 | ||
47926f60 | 136 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
137 | unsigned int operands; |
138 | ||
139 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
140 | of given register, displacement, memory operands and immediate | |
47926f60 | 141 | operands. */ |
252b5132 RH |
142 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
143 | ||
144 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 145 | use OP[i] for the corresponding operand. */ |
252b5132 RH |
146 | unsigned int types[MAX_OPERANDS]; |
147 | ||
520dc8e8 AM |
148 | /* Displacement expression, immediate expression, or register for each |
149 | operand. */ | |
150 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 151 | |
3e73aa7c JH |
152 | /* Flags for operands. */ |
153 | unsigned int flags[MAX_OPERANDS]; | |
154 | #define Operand_PCrel 1 | |
155 | ||
252b5132 | 156 | /* Relocation type for operand */ |
f86103b7 | 157 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 158 | |
252b5132 RH |
159 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
160 | the base index byte below. */ | |
161 | const reg_entry *base_reg; | |
162 | const reg_entry *index_reg; | |
163 | unsigned int log2_scale_factor; | |
164 | ||
165 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 166 | explicit segment overrides are given. */ |
ce8a8b2f | 167 | const seg_entry *seg[2]; |
252b5132 RH |
168 | |
169 | /* PREFIX holds all the given prefix opcodes (usually null). | |
170 | PREFIXES is the number of prefix opcodes. */ | |
171 | unsigned int prefixes; | |
172 | unsigned char prefix[MAX_PREFIXES]; | |
173 | ||
174 | /* RM and SIB are the modrm byte and the sib byte where the | |
175 | addressing modes of this insn are encoded. */ | |
176 | ||
177 | modrm_byte rm; | |
3e73aa7c | 178 | rex_byte rex; |
252b5132 RH |
179 | sib_byte sib; |
180 | }; | |
181 | ||
182 | typedef struct _i386_insn i386_insn; | |
183 | ||
184 | /* List of chars besides those in app.c:symbol_chars that can start an | |
185 | operand. Used to prevent the scrubber eating vital white-space. */ | |
32137342 | 186 | const char extra_symbol_chars[] = "*%-([" |
252b5132 | 187 | #ifdef LEX_AT |
32137342 NC |
188 | "@" |
189 | #endif | |
190 | #ifdef LEX_QM | |
191 | "?" | |
252b5132 | 192 | #endif |
32137342 | 193 | ; |
252b5132 | 194 | |
29b0f896 AM |
195 | #if (defined (TE_I386AIX) \ |
196 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
197 | && !defined (TE_LINUX) \ | |
32137342 | 198 | && !defined (TE_NETWARE) \ |
29b0f896 AM |
199 | && !defined (TE_FreeBSD) \ |
200 | && !defined (TE_NetBSD))) | |
252b5132 | 201 | /* This array holds the chars that always start a comment. If the |
ce8a8b2f | 202 | pre-processor is disabled, these aren't very useful. */ |
252b5132 RH |
203 | const char comment_chars[] = "#/"; |
204 | #define PREFIX_SEPARATOR '\\' | |
252b5132 RH |
205 | |
206 | /* This array holds the chars that only start a comment at the beginning of | |
207 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
208 | .line and .file directives will appear in the pre-processed output. |
209 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 210 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
211 | #NO_APP at the beginning of its output. |
212 | Also note that comments started like this one will always work if | |
252b5132 | 213 | '/' isn't otherwise defined. */ |
0d9f6d04 | 214 | const char line_comment_chars[] = "#"; |
29b0f896 | 215 | |
252b5132 | 216 | #else |
29b0f896 AM |
217 | /* Putting '/' here makes it impossible to use the divide operator. |
218 | However, we need it for compatibility with SVR4 systems. */ | |
219 | const char comment_chars[] = "#"; | |
220 | #define PREFIX_SEPARATOR '/' | |
221 | ||
0d9f6d04 | 222 | const char line_comment_chars[] = "/#"; |
252b5132 RH |
223 | #endif |
224 | ||
63a0b638 | 225 | const char line_separator_chars[] = ";"; |
252b5132 | 226 | |
ce8a8b2f AM |
227 | /* Chars that can be used to separate mant from exp in floating point |
228 | nums. */ | |
252b5132 RH |
229 | const char EXP_CHARS[] = "eE"; |
230 | ||
ce8a8b2f AM |
231 | /* Chars that mean this number is a floating point constant |
232 | As in 0f12.456 | |
233 | or 0d1.2345e12. */ | |
252b5132 RH |
234 | const char FLT_CHARS[] = "fFdDxX"; |
235 | ||
ce8a8b2f | 236 | /* Tables for lexical analysis. */ |
252b5132 RH |
237 | static char mnemonic_chars[256]; |
238 | static char register_chars[256]; | |
239 | static char operand_chars[256]; | |
240 | static char identifier_chars[256]; | |
241 | static char digit_chars[256]; | |
242 | ||
ce8a8b2f | 243 | /* Lexical macros. */ |
252b5132 RH |
244 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
245 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
246 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
247 | #define is_space_char(x) ((x) == ' ') | |
248 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
249 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
250 | ||
0234cb7c | 251 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
252 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
253 | ||
254 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
255 | effect this we maintain a stack of saved characters that we've smashed | |
256 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 257 | assembler instruction). */ |
252b5132 | 258 | static char save_stack[32]; |
ce8a8b2f | 259 | static char *save_stack_p; |
252b5132 RH |
260 | #define END_STRING_AND_SAVE(s) \ |
261 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
262 | #define RESTORE_END_STRING(s) \ | |
263 | do { *(s) = *--save_stack_p; } while (0) | |
264 | ||
47926f60 | 265 | /* The instruction we're assembling. */ |
252b5132 RH |
266 | static i386_insn i; |
267 | ||
268 | /* Possible templates for current insn. */ | |
269 | static const templates *current_templates; | |
270 | ||
47926f60 | 271 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ |
252b5132 RH |
272 | static expressionS disp_expressions[2], im_expressions[2]; |
273 | ||
47926f60 KH |
274 | /* Current operand we are working on. */ |
275 | static int this_operand; | |
252b5132 | 276 | |
3e73aa7c JH |
277 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
278 | these. */ | |
279 | ||
280 | enum flag_code { | |
281 | CODE_32BIT, | |
282 | CODE_16BIT, | |
283 | CODE_64BIT }; | |
f3c180ae | 284 | #define NUM_FLAG_CODE ((int) CODE_64BIT + 1) |
3e73aa7c JH |
285 | |
286 | static enum flag_code flag_code; | |
287 | static int use_rela_relocations = 0; | |
288 | ||
289 | /* The names used to print error messages. */ | |
b77a7acd | 290 | static const char *flag_code_names[] = |
3e73aa7c JH |
291 | { |
292 | "32", | |
293 | "16", | |
294 | "64" | |
295 | }; | |
252b5132 | 296 | |
47926f60 KH |
297 | /* 1 for intel syntax, |
298 | 0 if att syntax. */ | |
299 | static int intel_syntax = 0; | |
252b5132 | 300 | |
47926f60 KH |
301 | /* 1 if register prefix % not required. */ |
302 | static int allow_naked_reg = 0; | |
252b5132 | 303 | |
47926f60 KH |
304 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
305 | leave, push, and pop instructions so that gcc has the same stack | |
306 | frame as in 32 bit mode. */ | |
307 | static char stackop_size = '\0'; | |
eecb386c | 308 | |
12b55ccc L |
309 | /* Non-zero to optimize code alignment. */ |
310 | int optimize_align_code = 1; | |
311 | ||
47926f60 KH |
312 | /* Non-zero to quieten some warnings. */ |
313 | static int quiet_warnings = 0; | |
a38cf1db | 314 | |
47926f60 KH |
315 | /* CPU name. */ |
316 | static const char *cpu_arch_name = NULL; | |
a38cf1db | 317 | |
47926f60 | 318 | /* CPU feature flags. */ |
29b0f896 | 319 | static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64; |
a38cf1db | 320 | |
fddf5b5b AM |
321 | /* If set, conditional jumps are not automatically promoted to handle |
322 | larger than a byte offset. */ | |
323 | static unsigned int no_cond_jump_promotion = 0; | |
324 | ||
29b0f896 AM |
325 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
326 | symbolS *GOT_symbol; | |
327 | ||
a4447b93 RH |
328 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
329 | unsigned int x86_dwarf2_return_column; | |
330 | ||
331 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
332 | int x86_cie_data_alignment; | |
333 | ||
252b5132 | 334 | /* Interface to relax_segment. |
fddf5b5b AM |
335 | There are 3 major relax states for 386 jump insns because the |
336 | different types of jumps add different sizes to frags when we're | |
337 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 338 | |
47926f60 | 339 | /* Types. */ |
93c2a809 AM |
340 | #define UNCOND_JUMP 0 |
341 | #define COND_JUMP 1 | |
342 | #define COND_JUMP86 2 | |
fddf5b5b | 343 | |
47926f60 | 344 | /* Sizes. */ |
252b5132 RH |
345 | #define CODE16 1 |
346 | #define SMALL 0 | |
29b0f896 | 347 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 348 | #define BIG 2 |
29b0f896 | 349 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
350 | |
351 | #ifndef INLINE | |
352 | #ifdef __GNUC__ | |
353 | #define INLINE __inline__ | |
354 | #else | |
355 | #define INLINE | |
356 | #endif | |
357 | #endif | |
358 | ||
fddf5b5b AM |
359 | #define ENCODE_RELAX_STATE(type, size) \ |
360 | ((relax_substateT) (((type) << 2) | (size))) | |
361 | #define TYPE_FROM_RELAX_STATE(s) \ | |
362 | ((s) >> 2) | |
363 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
364 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
365 | |
366 | /* This table is used by relax_frag to promote short jumps to long | |
367 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
368 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
369 | don't allow a short jump in a 32 bit code segment to be promoted to | |
370 | a 16 bit offset jump because it's slower (requires data size | |
371 | prefix), and doesn't work, unless the destination is in the bottom | |
372 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
373 | ||
374 | const relax_typeS md_relax_table[] = | |
375 | { | |
24eab124 AM |
376 | /* The fields are: |
377 | 1) most positive reach of this state, | |
378 | 2) most negative reach of this state, | |
93c2a809 | 379 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 380 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 381 | |
fddf5b5b | 382 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
383 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
384 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
385 | /* dword jmp adds 4 bytes to frag: | |
386 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 387 | {0, 0, 4, 0}, |
93c2a809 AM |
388 | /* word jmp adds 2 byte2 to frag: |
389 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
390 | {0, 0, 2, 0}, |
391 | ||
93c2a809 AM |
392 | /* COND_JUMP states. */ |
393 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
394 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
395 | /* dword conditionals adds 5 bytes to frag: | |
396 | 1 extra opcode byte, 4 displacement bytes. */ | |
397 | {0, 0, 5, 0}, | |
fddf5b5b | 398 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
399 | 1 extra opcode byte, 2 displacement bytes. */ |
400 | {0, 0, 3, 0}, | |
401 | ||
402 | /* COND_JUMP86 states. */ | |
403 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
404 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
405 | /* dword conditionals adds 5 bytes to frag: | |
406 | 1 extra opcode byte, 4 displacement bytes. */ | |
407 | {0, 0, 5, 0}, | |
408 | /* word conditionals add 4 bytes to frag: | |
409 | 1 displacement byte and a 3 byte long branch insn. */ | |
410 | {0, 0, 4, 0} | |
252b5132 RH |
411 | }; |
412 | ||
e413e4e9 AM |
413 | static const arch_entry cpu_arch[] = { |
414 | {"i8086", Cpu086 }, | |
415 | {"i186", Cpu086|Cpu186 }, | |
416 | {"i286", Cpu086|Cpu186|Cpu286 }, | |
417 | {"i386", Cpu086|Cpu186|Cpu286|Cpu386 }, | |
418 | {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 }, | |
419 | {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
420 | {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
421 | {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
422 | {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
a167610d | 423 | {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 }, |
3e73aa7c JH |
424 | {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow }, |
425 | {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow }, | |
a167610d | 426 | {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 }, |
e413e4e9 AM |
427 | {NULL, 0 } |
428 | }; | |
429 | ||
29b0f896 AM |
430 | const pseudo_typeS md_pseudo_table[] = |
431 | { | |
432 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
433 | {"align", s_align_bytes, 0}, | |
434 | #else | |
435 | {"align", s_align_ptwo, 0}, | |
436 | #endif | |
437 | {"arch", set_cpu_arch, 0}, | |
438 | #ifndef I386COFF | |
439 | {"bss", s_bss, 0}, | |
440 | #endif | |
441 | {"ffloat", float_cons, 'f'}, | |
442 | {"dfloat", float_cons, 'd'}, | |
443 | {"tfloat", float_cons, 'x'}, | |
444 | {"value", cons, 2}, | |
445 | {"noopt", s_ignore, 0}, | |
446 | {"optim", s_ignore, 0}, | |
447 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
448 | {"code16", set_code_flag, CODE_16BIT}, | |
449 | {"code32", set_code_flag, CODE_32BIT}, | |
450 | {"code64", set_code_flag, CODE_64BIT}, | |
451 | {"intel_syntax", set_intel_syntax, 1}, | |
452 | {"att_syntax", set_intel_syntax, 0}, | |
c6682705 | 453 | {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0}, |
29b0f896 | 454 | {"loc", dwarf2_directive_loc, 0}, |
6482c264 NC |
455 | #ifdef TE_PE |
456 | {"secrel32", pe_directive_secrel, 0}, | |
457 | #endif | |
29b0f896 AM |
458 | {0, 0, 0} |
459 | }; | |
460 | ||
461 | /* For interface with expression (). */ | |
462 | extern char *input_line_pointer; | |
463 | ||
464 | /* Hash table for instruction mnemonic lookup. */ | |
465 | static struct hash_control *op_hash; | |
466 | ||
467 | /* Hash table for register lookup. */ | |
468 | static struct hash_control *reg_hash; | |
469 | \f | |
252b5132 RH |
470 | void |
471 | i386_align_code (fragP, count) | |
472 | fragS *fragP; | |
473 | int count; | |
474 | { | |
ce8a8b2f AM |
475 | /* Various efficient no-op patterns for aligning code labels. |
476 | Note: Don't try to assemble the instructions in the comments. | |
477 | 0L and 0w are not legal. */ | |
252b5132 RH |
478 | static const char f32_1[] = |
479 | {0x90}; /* nop */ | |
480 | static const char f32_2[] = | |
481 | {0x89,0xf6}; /* movl %esi,%esi */ | |
482 | static const char f32_3[] = | |
483 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
484 | static const char f32_4[] = | |
485 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
486 | static const char f32_5[] = | |
487 | {0x90, /* nop */ | |
488 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
489 | static const char f32_6[] = | |
490 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
491 | static const char f32_7[] = | |
492 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
493 | static const char f32_8[] = | |
494 | {0x90, /* nop */ | |
495 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
496 | static const char f32_9[] = | |
497 | {0x89,0xf6, /* movl %esi,%esi */ | |
498 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
499 | static const char f32_10[] = | |
500 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
501 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
502 | static const char f32_11[] = | |
503 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
504 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
505 | static const char f32_12[] = | |
506 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
507 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
508 | static const char f32_13[] = | |
509 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
510 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
511 | static const char f32_14[] = | |
512 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
513 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
514 | static const char f32_15[] = | |
515 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
516 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
c3332e24 AM |
517 | static const char f16_3[] = |
518 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
519 | static const char f16_4[] = |
520 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
521 | static const char f16_5[] = | |
522 | {0x90, /* nop */ | |
523 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
524 | static const char f16_6[] = | |
525 | {0x89,0xf6, /* mov %si,%si */ | |
526 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
527 | static const char f16_7[] = | |
528 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
529 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
530 | static const char f16_8[] = | |
531 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
532 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
533 | static const char *const f32_patt[] = { | |
534 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
535 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
536 | }; | |
537 | static const char *const f16_patt[] = { | |
c3332e24 | 538 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, |
252b5132 RH |
539 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 |
540 | }; | |
541 | ||
33fef721 JH |
542 | if (count <= 0 || count > 15) |
543 | return; | |
3e73aa7c | 544 | |
33fef721 JH |
545 | /* The recommended way to pad 64bit code is to use NOPs preceded by |
546 | maximally four 0x66 prefixes. Balance the size of nops. */ | |
547 | if (flag_code == CODE_64BIT) | |
252b5132 | 548 | { |
33fef721 JH |
549 | int i; |
550 | int nnops = (count + 3) / 4; | |
551 | int len = count / nnops; | |
552 | int remains = count - nnops * len; | |
553 | int pos = 0; | |
554 | ||
555 | for (i = 0; i < remains; i++) | |
252b5132 | 556 | { |
33fef721 JH |
557 | memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len); |
558 | fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90; | |
559 | pos += len + 1; | |
560 | } | |
561 | for (; i < nnops; i++) | |
562 | { | |
563 | memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1); | |
564 | fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90; | |
565 | pos += len; | |
252b5132 | 566 | } |
252b5132 | 567 | } |
33fef721 JH |
568 | else |
569 | if (flag_code == CODE_16BIT) | |
570 | { | |
571 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
572 | f16_patt[count - 1], count); | |
573 | if (count > 8) | |
574 | /* Adjust jump offset. */ | |
575 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
576 | } | |
577 | else | |
578 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
579 | f32_patt[count - 1], count); | |
580 | fragP->fr_var = count; | |
252b5132 RH |
581 | } |
582 | ||
252b5132 RH |
583 | static INLINE unsigned int |
584 | mode_from_disp_size (t) | |
585 | unsigned int t; | |
586 | { | |
3e73aa7c | 587 | return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0; |
252b5132 RH |
588 | } |
589 | ||
590 | static INLINE int | |
591 | fits_in_signed_byte (num) | |
847f7ad4 | 592 | offsetT num; |
252b5132 RH |
593 | { |
594 | return (num >= -128) && (num <= 127); | |
47926f60 | 595 | } |
252b5132 RH |
596 | |
597 | static INLINE int | |
598 | fits_in_unsigned_byte (num) | |
847f7ad4 | 599 | offsetT num; |
252b5132 RH |
600 | { |
601 | return (num & 0xff) == num; | |
47926f60 | 602 | } |
252b5132 RH |
603 | |
604 | static INLINE int | |
605 | fits_in_unsigned_word (num) | |
847f7ad4 | 606 | offsetT num; |
252b5132 RH |
607 | { |
608 | return (num & 0xffff) == num; | |
47926f60 | 609 | } |
252b5132 RH |
610 | |
611 | static INLINE int | |
612 | fits_in_signed_word (num) | |
847f7ad4 | 613 | offsetT num; |
252b5132 RH |
614 | { |
615 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 616 | } |
3e73aa7c JH |
617 | static INLINE int |
618 | fits_in_signed_long (num) | |
619 | offsetT num ATTRIBUTE_UNUSED; | |
620 | { | |
621 | #ifndef BFD64 | |
622 | return 1; | |
623 | #else | |
624 | return (!(((offsetT) -1 << 31) & num) | |
625 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); | |
626 | #endif | |
627 | } /* fits_in_signed_long() */ | |
628 | static INLINE int | |
629 | fits_in_unsigned_long (num) | |
630 | offsetT num ATTRIBUTE_UNUSED; | |
631 | { | |
632 | #ifndef BFD64 | |
633 | return 1; | |
634 | #else | |
635 | return (num & (((offsetT) 2 << 31) - 1)) == num; | |
636 | #endif | |
637 | } /* fits_in_unsigned_long() */ | |
252b5132 RH |
638 | |
639 | static int | |
640 | smallest_imm_type (num) | |
847f7ad4 | 641 | offsetT num; |
252b5132 | 642 | { |
a847613f | 643 | if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)) |
e413e4e9 AM |
644 | { |
645 | /* This code is disabled on the 486 because all the Imm1 forms | |
646 | in the opcode table are slower on the i486. They're the | |
647 | versions with the implicitly specified single-position | |
648 | displacement, which has another syntax if you really want to | |
649 | use that form. */ | |
650 | if (num == 1) | |
3e73aa7c | 651 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64; |
e413e4e9 | 652 | } |
252b5132 | 653 | return (fits_in_signed_byte (num) |
3e73aa7c | 654 | ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64) |
252b5132 | 655 | : fits_in_unsigned_byte (num) |
3e73aa7c | 656 | ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64) |
252b5132 | 657 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) |
3e73aa7c JH |
658 | ? (Imm16 | Imm32 | Imm32S | Imm64) |
659 | : fits_in_signed_long (num) | |
660 | ? (Imm32 | Imm32S | Imm64) | |
661 | : fits_in_unsigned_long (num) | |
662 | ? (Imm32 | Imm64) | |
663 | : Imm64); | |
47926f60 | 664 | } |
252b5132 | 665 | |
847f7ad4 AM |
666 | static offsetT |
667 | offset_in_range (val, size) | |
668 | offsetT val; | |
669 | int size; | |
670 | { | |
508866be | 671 | addressT mask; |
ba2adb93 | 672 | |
847f7ad4 AM |
673 | switch (size) |
674 | { | |
508866be L |
675 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
676 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 677 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
678 | #ifdef BFD64 |
679 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
680 | #endif | |
47926f60 | 681 | default: abort (); |
847f7ad4 AM |
682 | } |
683 | ||
ba2adb93 | 684 | /* If BFD64, sign extend val. */ |
3e73aa7c JH |
685 | if (!use_rela_relocations) |
686 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) | |
687 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
ba2adb93 | 688 | |
47926f60 | 689 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
690 | { |
691 | char buf1[40], buf2[40]; | |
692 | ||
693 | sprint_value (buf1, val); | |
694 | sprint_value (buf2, val & mask); | |
695 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
696 | } | |
697 | return val & mask; | |
698 | } | |
699 | ||
252b5132 RH |
700 | /* Returns 0 if attempting to add a prefix where one from the same |
701 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
702 | added. */ | |
703 | static int | |
704 | add_prefix (prefix) | |
705 | unsigned int prefix; | |
706 | { | |
707 | int ret = 1; | |
708 | int q; | |
709 | ||
29b0f896 AM |
710 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
711 | && flag_code == CODE_64BIT) | |
3e73aa7c JH |
712 | q = REX_PREFIX; |
713 | else | |
714 | switch (prefix) | |
715 | { | |
716 | default: | |
717 | abort (); | |
718 | ||
719 | case CS_PREFIX_OPCODE: | |
720 | case DS_PREFIX_OPCODE: | |
721 | case ES_PREFIX_OPCODE: | |
722 | case FS_PREFIX_OPCODE: | |
723 | case GS_PREFIX_OPCODE: | |
724 | case SS_PREFIX_OPCODE: | |
725 | q = SEG_PREFIX; | |
726 | break; | |
252b5132 | 727 | |
3e73aa7c JH |
728 | case REPNE_PREFIX_OPCODE: |
729 | case REPE_PREFIX_OPCODE: | |
730 | ret = 2; | |
731 | /* fall thru */ | |
732 | case LOCK_PREFIX_OPCODE: | |
733 | q = LOCKREP_PREFIX; | |
734 | break; | |
252b5132 | 735 | |
3e73aa7c JH |
736 | case FWAIT_OPCODE: |
737 | q = WAIT_PREFIX; | |
738 | break; | |
252b5132 | 739 | |
3e73aa7c JH |
740 | case ADDR_PREFIX_OPCODE: |
741 | q = ADDR_PREFIX; | |
742 | break; | |
252b5132 | 743 | |
3e73aa7c JH |
744 | case DATA_PREFIX_OPCODE: |
745 | q = DATA_PREFIX; | |
746 | break; | |
747 | } | |
252b5132 | 748 | |
29b0f896 | 749 | if (i.prefix[q] != 0) |
252b5132 RH |
750 | { |
751 | as_bad (_("same type of prefix used twice")); | |
752 | return 0; | |
753 | } | |
754 | ||
755 | i.prefixes += 1; | |
756 | i.prefix[q] = prefix; | |
757 | return ret; | |
758 | } | |
759 | ||
760 | static void | |
3e73aa7c | 761 | set_code_flag (value) |
e5cb08ac | 762 | int value; |
eecb386c | 763 | { |
3e73aa7c JH |
764 | flag_code = value; |
765 | cpu_arch_flags &= ~(Cpu64 | CpuNo64); | |
766 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); | |
767 | if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer)) | |
768 | { | |
769 | as_bad (_("64bit mode not supported on this CPU.")); | |
770 | } | |
771 | if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386)) | |
772 | { | |
773 | as_bad (_("32bit mode not supported on this CPU.")); | |
774 | } | |
eecb386c AM |
775 | stackop_size = '\0'; |
776 | } | |
777 | ||
778 | static void | |
3e73aa7c JH |
779 | set_16bit_gcc_code_flag (new_code_flag) |
780 | int new_code_flag; | |
252b5132 | 781 | { |
3e73aa7c JH |
782 | flag_code = new_code_flag; |
783 | cpu_arch_flags &= ~(Cpu64 | CpuNo64); | |
784 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); | |
9306ca4a | 785 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
786 | } |
787 | ||
788 | static void | |
789 | set_intel_syntax (syntax_flag) | |
eecb386c | 790 | int syntax_flag; |
252b5132 RH |
791 | { |
792 | /* Find out if register prefixing is specified. */ | |
793 | int ask_naked_reg = 0; | |
794 | ||
795 | SKIP_WHITESPACE (); | |
29b0f896 | 796 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 RH |
797 | { |
798 | char *string = input_line_pointer; | |
799 | int e = get_symbol_end (); | |
800 | ||
47926f60 | 801 | if (strcmp (string, "prefix") == 0) |
252b5132 | 802 | ask_naked_reg = 1; |
47926f60 | 803 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
804 | ask_naked_reg = -1; |
805 | else | |
d0b47220 | 806 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
807 | *input_line_pointer = e; |
808 | } | |
809 | demand_empty_rest_of_line (); | |
c3332e24 | 810 | |
252b5132 RH |
811 | intel_syntax = syntax_flag; |
812 | ||
813 | if (ask_naked_reg == 0) | |
f86103b7 AM |
814 | allow_naked_reg = (intel_syntax |
815 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
816 | else |
817 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a JB |
818 | |
819 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; | |
820 | identifier_chars['$'] = intel_syntax ? '$' : 0; | |
252b5132 RH |
821 | } |
822 | ||
e413e4e9 AM |
823 | static void |
824 | set_cpu_arch (dummy) | |
47926f60 | 825 | int dummy ATTRIBUTE_UNUSED; |
e413e4e9 | 826 | { |
47926f60 | 827 | SKIP_WHITESPACE (); |
e413e4e9 | 828 | |
29b0f896 | 829 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 AM |
830 | { |
831 | char *string = input_line_pointer; | |
832 | int e = get_symbol_end (); | |
833 | int i; | |
834 | ||
835 | for (i = 0; cpu_arch[i].name; i++) | |
836 | { | |
837 | if (strcmp (string, cpu_arch[i].name) == 0) | |
838 | { | |
839 | cpu_arch_name = cpu_arch[i].name; | |
fddf5b5b AM |
840 | cpu_arch_flags = (cpu_arch[i].flags |
841 | | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64)); | |
e413e4e9 AM |
842 | break; |
843 | } | |
844 | } | |
845 | if (!cpu_arch[i].name) | |
846 | as_bad (_("no such architecture: `%s'"), string); | |
847 | ||
848 | *input_line_pointer = e; | |
849 | } | |
850 | else | |
851 | as_bad (_("missing cpu architecture")); | |
852 | ||
fddf5b5b AM |
853 | no_cond_jump_promotion = 0; |
854 | if (*input_line_pointer == ',' | |
29b0f896 | 855 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b AM |
856 | { |
857 | char *string = ++input_line_pointer; | |
858 | int e = get_symbol_end (); | |
859 | ||
860 | if (strcmp (string, "nojumps") == 0) | |
861 | no_cond_jump_promotion = 1; | |
862 | else if (strcmp (string, "jumps") == 0) | |
863 | ; | |
864 | else | |
865 | as_bad (_("no such architecture modifier: `%s'"), string); | |
866 | ||
867 | *input_line_pointer = e; | |
868 | } | |
869 | ||
e413e4e9 AM |
870 | demand_empty_rest_of_line (); |
871 | } | |
872 | ||
b9d79e03 JH |
873 | unsigned long |
874 | i386_mach () | |
875 | { | |
876 | if (!strcmp (default_arch, "x86_64")) | |
877 | return bfd_mach_x86_64; | |
878 | else if (!strcmp (default_arch, "i386")) | |
879 | return bfd_mach_i386_i386; | |
880 | else | |
881 | as_fatal (_("Unknown architecture")); | |
882 | } | |
b9d79e03 | 883 | \f |
252b5132 RH |
884 | void |
885 | md_begin () | |
886 | { | |
887 | const char *hash_err; | |
888 | ||
47926f60 | 889 | /* Initialize op_hash hash table. */ |
252b5132 RH |
890 | op_hash = hash_new (); |
891 | ||
892 | { | |
29b0f896 AM |
893 | const template *optab; |
894 | templates *core_optab; | |
252b5132 | 895 | |
47926f60 KH |
896 | /* Setup for loop. */ |
897 | optab = i386_optab; | |
252b5132 RH |
898 | core_optab = (templates *) xmalloc (sizeof (templates)); |
899 | core_optab->start = optab; | |
900 | ||
901 | while (1) | |
902 | { | |
903 | ++optab; | |
904 | if (optab->name == NULL | |
905 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
906 | { | |
907 | /* different name --> ship out current template list; | |
47926f60 | 908 | add to hash table; & begin anew. */ |
252b5132 RH |
909 | core_optab->end = optab; |
910 | hash_err = hash_insert (op_hash, | |
911 | (optab - 1)->name, | |
912 | (PTR) core_optab); | |
913 | if (hash_err) | |
914 | { | |
252b5132 RH |
915 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
916 | (optab - 1)->name, | |
917 | hash_err); | |
918 | } | |
919 | if (optab->name == NULL) | |
920 | break; | |
921 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
922 | core_optab->start = optab; | |
923 | } | |
924 | } | |
925 | } | |
926 | ||
47926f60 | 927 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
928 | reg_hash = hash_new (); |
929 | { | |
29b0f896 | 930 | const reg_entry *regtab; |
252b5132 RH |
931 | |
932 | for (regtab = i386_regtab; | |
933 | regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); | |
934 | regtab++) | |
935 | { | |
936 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); | |
937 | if (hash_err) | |
3e73aa7c JH |
938 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
939 | regtab->reg_name, | |
940 | hash_err); | |
252b5132 RH |
941 | } |
942 | } | |
943 | ||
47926f60 | 944 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 945 | { |
29b0f896 AM |
946 | int c; |
947 | char *p; | |
252b5132 RH |
948 | |
949 | for (c = 0; c < 256; c++) | |
950 | { | |
3882b010 | 951 | if (ISDIGIT (c)) |
252b5132 RH |
952 | { |
953 | digit_chars[c] = c; | |
954 | mnemonic_chars[c] = c; | |
955 | register_chars[c] = c; | |
956 | operand_chars[c] = c; | |
957 | } | |
3882b010 | 958 | else if (ISLOWER (c)) |
252b5132 RH |
959 | { |
960 | mnemonic_chars[c] = c; | |
961 | register_chars[c] = c; | |
962 | operand_chars[c] = c; | |
963 | } | |
3882b010 | 964 | else if (ISUPPER (c)) |
252b5132 | 965 | { |
3882b010 | 966 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
967 | register_chars[c] = mnemonic_chars[c]; |
968 | operand_chars[c] = c; | |
969 | } | |
970 | ||
3882b010 | 971 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
972 | identifier_chars[c] = c; |
973 | else if (c >= 128) | |
974 | { | |
975 | identifier_chars[c] = c; | |
976 | operand_chars[c] = c; | |
977 | } | |
978 | } | |
979 | ||
980 | #ifdef LEX_AT | |
981 | identifier_chars['@'] = '@'; | |
32137342 NC |
982 | #endif |
983 | #ifdef LEX_QM | |
984 | identifier_chars['?'] = '?'; | |
985 | operand_chars['?'] = '?'; | |
252b5132 | 986 | #endif |
252b5132 RH |
987 | digit_chars['-'] = '-'; |
988 | identifier_chars['_'] = '_'; | |
989 | identifier_chars['.'] = '.'; | |
990 | ||
991 | for (p = operand_special_chars; *p != '\0'; p++) | |
992 | operand_chars[(unsigned char) *p] = *p; | |
993 | } | |
994 | ||
995 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
996 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
997 | { | |
998 | record_alignment (text_section, 2); | |
999 | record_alignment (data_section, 2); | |
1000 | record_alignment (bss_section, 2); | |
1001 | } | |
1002 | #endif | |
a4447b93 RH |
1003 | |
1004 | if (flag_code == CODE_64BIT) | |
1005 | { | |
1006 | x86_dwarf2_return_column = 16; | |
1007 | x86_cie_data_alignment = -8; | |
1008 | } | |
1009 | else | |
1010 | { | |
1011 | x86_dwarf2_return_column = 8; | |
1012 | x86_cie_data_alignment = -4; | |
1013 | } | |
252b5132 RH |
1014 | } |
1015 | ||
1016 | void | |
1017 | i386_print_statistics (file) | |
1018 | FILE *file; | |
1019 | { | |
1020 | hash_print_statistics (file, "i386 opcode", op_hash); | |
1021 | hash_print_statistics (file, "i386 register", reg_hash); | |
1022 | } | |
1023 | \f | |
252b5132 RH |
1024 | #ifdef DEBUG386 |
1025 | ||
ce8a8b2f | 1026 | /* Debugging routines for md_assemble. */ |
252b5132 RH |
1027 | static void pi PARAMS ((char *, i386_insn *)); |
1028 | static void pte PARAMS ((template *)); | |
1029 | static void pt PARAMS ((unsigned int)); | |
1030 | static void pe PARAMS ((expressionS *)); | |
1031 | static void ps PARAMS ((symbolS *)); | |
1032 | ||
1033 | static void | |
1034 | pi (line, x) | |
1035 | char *line; | |
1036 | i386_insn *x; | |
1037 | { | |
09f131f2 | 1038 | unsigned int i; |
252b5132 RH |
1039 | |
1040 | fprintf (stdout, "%s: template ", line); | |
1041 | pte (&x->tm); | |
09f131f2 JH |
1042 | fprintf (stdout, " address: base %s index %s scale %x\n", |
1043 | x->base_reg ? x->base_reg->reg_name : "none", | |
1044 | x->index_reg ? x->index_reg->reg_name : "none", | |
1045 | x->log2_scale_factor); | |
1046 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 1047 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
1048 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
1049 | x->sib.base, x->sib.index, x->sib.scale); | |
1050 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
29b0f896 AM |
1051 | (x->rex & REX_MODE64) != 0, |
1052 | (x->rex & REX_EXTX) != 0, | |
1053 | (x->rex & REX_EXTY) != 0, | |
1054 | (x->rex & REX_EXTZ) != 0); | |
252b5132 RH |
1055 | for (i = 0; i < x->operands; i++) |
1056 | { | |
1057 | fprintf (stdout, " #%d: ", i + 1); | |
1058 | pt (x->types[i]); | |
1059 | fprintf (stdout, "\n"); | |
1060 | if (x->types[i] | |
3f4438ab | 1061 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) |
520dc8e8 | 1062 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
252b5132 | 1063 | if (x->types[i] & Imm) |
520dc8e8 | 1064 | pe (x->op[i].imms); |
252b5132 | 1065 | if (x->types[i] & Disp) |
520dc8e8 | 1066 | pe (x->op[i].disps); |
252b5132 RH |
1067 | } |
1068 | } | |
1069 | ||
1070 | static void | |
1071 | pte (t) | |
1072 | template *t; | |
1073 | { | |
09f131f2 | 1074 | unsigned int i; |
252b5132 | 1075 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 1076 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
1077 | if (t->extension_opcode != None) |
1078 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
1079 | if (t->opcode_modifier & D) | |
1080 | fprintf (stdout, "D"); | |
1081 | if (t->opcode_modifier & W) | |
1082 | fprintf (stdout, "W"); | |
1083 | fprintf (stdout, "\n"); | |
1084 | for (i = 0; i < t->operands; i++) | |
1085 | { | |
1086 | fprintf (stdout, " #%d type ", i + 1); | |
1087 | pt (t->operand_types[i]); | |
1088 | fprintf (stdout, "\n"); | |
1089 | } | |
1090 | } | |
1091 | ||
1092 | static void | |
1093 | pe (e) | |
1094 | expressionS *e; | |
1095 | { | |
24eab124 | 1096 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
1097 | fprintf (stdout, " add_number %ld (%lx)\n", |
1098 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
1099 | if (e->X_add_symbol) |
1100 | { | |
1101 | fprintf (stdout, " add_symbol "); | |
1102 | ps (e->X_add_symbol); | |
1103 | fprintf (stdout, "\n"); | |
1104 | } | |
1105 | if (e->X_op_symbol) | |
1106 | { | |
1107 | fprintf (stdout, " op_symbol "); | |
1108 | ps (e->X_op_symbol); | |
1109 | fprintf (stdout, "\n"); | |
1110 | } | |
1111 | } | |
1112 | ||
1113 | static void | |
1114 | ps (s) | |
1115 | symbolS *s; | |
1116 | { | |
1117 | fprintf (stdout, "%s type %s%s", | |
1118 | S_GET_NAME (s), | |
1119 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
1120 | segment_name (S_GET_SEGMENT (s))); | |
1121 | } | |
1122 | ||
1123 | struct type_name | |
1124 | { | |
1125 | unsigned int mask; | |
1126 | char *tname; | |
1127 | } | |
1128 | ||
29b0f896 | 1129 | static const type_names[] = |
252b5132 RH |
1130 | { |
1131 | { Reg8, "r8" }, | |
1132 | { Reg16, "r16" }, | |
1133 | { Reg32, "r32" }, | |
09f131f2 | 1134 | { Reg64, "r64" }, |
252b5132 RH |
1135 | { Imm8, "i8" }, |
1136 | { Imm8S, "i8s" }, | |
1137 | { Imm16, "i16" }, | |
1138 | { Imm32, "i32" }, | |
09f131f2 JH |
1139 | { Imm32S, "i32s" }, |
1140 | { Imm64, "i64" }, | |
252b5132 RH |
1141 | { Imm1, "i1" }, |
1142 | { BaseIndex, "BaseIndex" }, | |
1143 | { Disp8, "d8" }, | |
1144 | { Disp16, "d16" }, | |
1145 | { Disp32, "d32" }, | |
09f131f2 JH |
1146 | { Disp32S, "d32s" }, |
1147 | { Disp64, "d64" }, | |
252b5132 RH |
1148 | { InOutPortReg, "InOutPortReg" }, |
1149 | { ShiftCount, "ShiftCount" }, | |
1150 | { Control, "control reg" }, | |
1151 | { Test, "test reg" }, | |
1152 | { Debug, "debug reg" }, | |
1153 | { FloatReg, "FReg" }, | |
1154 | { FloatAcc, "FAcc" }, | |
1155 | { SReg2, "SReg2" }, | |
1156 | { SReg3, "SReg3" }, | |
1157 | { Acc, "Acc" }, | |
1158 | { JumpAbsolute, "Jump Absolute" }, | |
1159 | { RegMMX, "rMMX" }, | |
3f4438ab | 1160 | { RegXMM, "rXMM" }, |
252b5132 RH |
1161 | { EsSeg, "es" }, |
1162 | { 0, "" } | |
1163 | }; | |
1164 | ||
1165 | static void | |
1166 | pt (t) | |
1167 | unsigned int t; | |
1168 | { | |
29b0f896 | 1169 | const struct type_name *ty; |
252b5132 | 1170 | |
09f131f2 JH |
1171 | for (ty = type_names; ty->mask; ty++) |
1172 | if (t & ty->mask) | |
1173 | fprintf (stdout, "%s, ", ty->tname); | |
252b5132 RH |
1174 | fflush (stdout); |
1175 | } | |
1176 | ||
1177 | #endif /* DEBUG386 */ | |
1178 | \f | |
29b0f896 AM |
1179 | static bfd_reloc_code_real_type reloc |
1180 | PARAMS ((int, int, int, bfd_reloc_code_real_type)); | |
252b5132 RH |
1181 | |
1182 | static bfd_reloc_code_real_type | |
3e73aa7c | 1183 | reloc (size, pcrel, sign, other) |
252b5132 RH |
1184 | int size; |
1185 | int pcrel; | |
3e73aa7c | 1186 | int sign; |
252b5132 RH |
1187 | bfd_reloc_code_real_type other; |
1188 | { | |
47926f60 KH |
1189 | if (other != NO_RELOC) |
1190 | return other; | |
252b5132 RH |
1191 | |
1192 | if (pcrel) | |
1193 | { | |
3e73aa7c | 1194 | if (!sign) |
e5cb08ac | 1195 | as_bad (_("There are no unsigned pc-relative relocations")); |
252b5132 RH |
1196 | switch (size) |
1197 | { | |
1198 | case 1: return BFD_RELOC_8_PCREL; | |
1199 | case 2: return BFD_RELOC_16_PCREL; | |
1200 | case 4: return BFD_RELOC_32_PCREL; | |
1201 | } | |
d0b47220 | 1202 | as_bad (_("can not do %d byte pc-relative relocation"), size); |
252b5132 RH |
1203 | } |
1204 | else | |
1205 | { | |
3e73aa7c | 1206 | if (sign) |
e5cb08ac | 1207 | switch (size) |
3e73aa7c JH |
1208 | { |
1209 | case 4: return BFD_RELOC_X86_64_32S; | |
1210 | } | |
1211 | else | |
1212 | switch (size) | |
1213 | { | |
1214 | case 1: return BFD_RELOC_8; | |
1215 | case 2: return BFD_RELOC_16; | |
1216 | case 4: return BFD_RELOC_32; | |
1217 | case 8: return BFD_RELOC_64; | |
1218 | } | |
1219 | as_bad (_("can not do %s %d byte relocation"), | |
1220 | sign ? "signed" : "unsigned", size); | |
252b5132 RH |
1221 | } |
1222 | ||
bfb32b52 | 1223 | abort (); |
252b5132 RH |
1224 | return BFD_RELOC_NONE; |
1225 | } | |
1226 | ||
47926f60 KH |
1227 | /* Here we decide which fixups can be adjusted to make them relative to |
1228 | the beginning of the section instead of the symbol. Basically we need | |
1229 | to make sure that the dynamic relocations are done correctly, so in | |
1230 | some cases we force the original symbol to be used. */ | |
1231 | ||
252b5132 | 1232 | int |
c0c949c7 | 1233 | tc_i386_fix_adjustable (fixP) |
31312f95 | 1234 | fixS *fixP ATTRIBUTE_UNUSED; |
252b5132 | 1235 | { |
6d249963 | 1236 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
31312f95 AM |
1237 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
1238 | return 1; | |
1239 | ||
a161fe53 AM |
1240 | /* Don't adjust pc-relative references to merge sections in 64-bit |
1241 | mode. */ | |
1242 | if (use_rela_relocations | |
1243 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
1244 | && fixP->fx_pcrel) | |
252b5132 | 1245 | return 0; |
31312f95 | 1246 | |
8d01d9a9 AJ |
1247 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
1248 | and changed later by validate_fix. */ | |
1249 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
1250 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
1251 | return 0; | |
1252 | ||
ce8a8b2f | 1253 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
1254 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
1255 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
1256 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
13ae64f3 JJ |
1257 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
1258 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
1259 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
1260 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
1261 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
1262 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
1263 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
1264 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
3e73aa7c JH |
1265 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
1266 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 1267 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
bffbf940 JJ |
1268 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
1269 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
1270 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
1271 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF | |
1272 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
252b5132 RH |
1273 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
1274 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1275 | return 0; | |
31312f95 | 1276 | #endif |
252b5132 RH |
1277 | return 1; |
1278 | } | |
252b5132 | 1279 | |
29b0f896 | 1280 | static int intel_float_operand PARAMS ((const char *mnemonic)); |
b4cac588 AM |
1281 | |
1282 | static int | |
252b5132 | 1283 | intel_float_operand (mnemonic) |
29b0f896 | 1284 | const char *mnemonic; |
252b5132 | 1285 | { |
9306ca4a JB |
1286 | /* Note that the value returned is meaningful only for opcodes with (memory) |
1287 | operands, hence the code here is free to improperly handle opcodes that | |
1288 | have no operands (for better performance and smaller code). */ | |
1289 | ||
1290 | if (mnemonic[0] != 'f') | |
1291 | return 0; /* non-math */ | |
1292 | ||
1293 | switch (mnemonic[1]) | |
1294 | { | |
1295 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
1296 | the fs segment override prefix not currently handled because no | |
1297 | call path can make opcodes without operands get here */ | |
1298 | case 'i': | |
1299 | return 2 /* integer op */; | |
1300 | case 'l': | |
1301 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
1302 | return 3; /* fldcw/fldenv */ | |
1303 | break; | |
1304 | case 'n': | |
1305 | if (mnemonic[2] != 'o' /* fnop */) | |
1306 | return 3; /* non-waiting control op */ | |
1307 | break; | |
1308 | case 'r': | |
1309 | if (mnemonic[2] == 's') | |
1310 | return 3; /* frstor/frstpm */ | |
1311 | break; | |
1312 | case 's': | |
1313 | if (mnemonic[2] == 'a') | |
1314 | return 3; /* fsave */ | |
1315 | if (mnemonic[2] == 't') | |
1316 | { | |
1317 | switch (mnemonic[3]) | |
1318 | { | |
1319 | case 'c': /* fstcw */ | |
1320 | case 'd': /* fstdw */ | |
1321 | case 'e': /* fstenv */ | |
1322 | case 's': /* fsts[gw] */ | |
1323 | return 3; | |
1324 | } | |
1325 | } | |
1326 | break; | |
1327 | case 'x': | |
1328 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
1329 | return 0; /* fxsave/fxrstor are not really math ops */ | |
1330 | break; | |
1331 | } | |
252b5132 | 1332 | |
9306ca4a | 1333 | return 1; |
252b5132 RH |
1334 | } |
1335 | ||
1336 | /* This is the guts of the machine-dependent assembler. LINE points to a | |
1337 | machine dependent instruction. This function is supposed to emit | |
1338 | the frags/bytes it assembles to. */ | |
1339 | ||
1340 | void | |
1341 | md_assemble (line) | |
1342 | char *line; | |
1343 | { | |
252b5132 | 1344 | int j; |
252b5132 RH |
1345 | char mnemonic[MAX_MNEM_SIZE]; |
1346 | ||
47926f60 | 1347 | /* Initialize globals. */ |
252b5132 RH |
1348 | memset (&i, '\0', sizeof (i)); |
1349 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 1350 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
1351 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
1352 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 1353 | save_stack_p = save_stack; |
252b5132 RH |
1354 | |
1355 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
1356 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 1357 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 1358 | |
29b0f896 AM |
1359 | line = parse_insn (line, mnemonic); |
1360 | if (line == NULL) | |
1361 | return; | |
252b5132 | 1362 | |
29b0f896 AM |
1363 | line = parse_operands (line, mnemonic); |
1364 | if (line == NULL) | |
1365 | return; | |
252b5132 | 1366 | |
29b0f896 AM |
1367 | /* Now we've parsed the mnemonic into a set of templates, and have the |
1368 | operands at hand. */ | |
1369 | ||
1370 | /* All intel opcodes have reversed operands except for "bound" and | |
1371 | "enter". We also don't reverse intersegment "jmp" and "call" | |
1372 | instructions with 2 immediate operands so that the immediate segment | |
1373 | precedes the offset, as it does when in AT&T mode. "enter" and the | |
1374 | intersegment "jmp" and "call" instructions are the only ones that | |
1375 | have two immediate operands. */ | |
1376 | if (intel_syntax && i.operands > 1 | |
1377 | && (strcmp (mnemonic, "bound") != 0) | |
1378 | && !((i.types[0] & Imm) && (i.types[1] & Imm))) | |
1379 | swap_operands (); | |
1380 | ||
1381 | if (i.imm_operands) | |
1382 | optimize_imm (); | |
1383 | ||
1384 | if (i.disp_operands) | |
1385 | optimize_disp (); | |
1386 | ||
1387 | /* Next, we find a template that matches the given insn, | |
1388 | making sure the overlap of the given operands types is consistent | |
1389 | with the template operand types. */ | |
252b5132 | 1390 | |
29b0f896 AM |
1391 | if (!match_template ()) |
1392 | return; | |
252b5132 | 1393 | |
cd61ebfe AM |
1394 | if (intel_syntax) |
1395 | { | |
1396 | /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ | |
1397 | if (SYSV386_COMPAT | |
1398 | && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) | |
1399 | i.tm.base_opcode ^= FloatR; | |
1400 | ||
1401 | /* Zap movzx and movsx suffix. The suffix may have been set from | |
1402 | "word ptr" or "byte ptr" on the source operand, but we'll use | |
1403 | the suffix later to choose the destination register. */ | |
1404 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
9306ca4a JB |
1405 | { |
1406 | if (i.reg_operands < 2 | |
1407 | && !i.suffix | |
1408 | && (~i.tm.opcode_modifier | |
1409 | & (No_bSuf | |
1410 | | No_wSuf | |
1411 | | No_lSuf | |
1412 | | No_sSuf | |
1413 | | No_xSuf | |
1414 | | No_qSuf))) | |
1415 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
1416 | ||
1417 | i.suffix = 0; | |
1418 | } | |
cd61ebfe | 1419 | } |
24eab124 | 1420 | |
29b0f896 AM |
1421 | if (i.tm.opcode_modifier & FWait) |
1422 | if (!add_prefix (FWAIT_OPCODE)) | |
1423 | return; | |
252b5132 | 1424 | |
29b0f896 AM |
1425 | /* Check string instruction segment overrides. */ |
1426 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) | |
1427 | { | |
1428 | if (!check_string ()) | |
5dd0794d | 1429 | return; |
29b0f896 | 1430 | } |
5dd0794d | 1431 | |
29b0f896 AM |
1432 | if (!process_suffix ()) |
1433 | return; | |
e413e4e9 | 1434 | |
29b0f896 AM |
1435 | /* Make still unresolved immediate matches conform to size of immediate |
1436 | given in i.suffix. */ | |
1437 | if (!finalize_imm ()) | |
1438 | return; | |
252b5132 | 1439 | |
29b0f896 AM |
1440 | if (i.types[0] & Imm1) |
1441 | i.imm_operands = 0; /* kludge for shift insns. */ | |
1442 | if (i.types[0] & ImplicitRegister) | |
1443 | i.reg_operands--; | |
1444 | if (i.types[1] & ImplicitRegister) | |
1445 | i.reg_operands--; | |
1446 | if (i.types[2] & ImplicitRegister) | |
1447 | i.reg_operands--; | |
252b5132 | 1448 | |
29b0f896 AM |
1449 | if (i.tm.opcode_modifier & ImmExt) |
1450 | { | |
02fc3089 L |
1451 | expressionS *exp; |
1452 | ||
ca164297 L |
1453 | if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0) |
1454 | { | |
67c1ffbe | 1455 | /* These Intel Prescott New Instructions have the fixed |
ca164297 L |
1456 | operands with an opcode suffix which is coded in the same |
1457 | place as an 8-bit immediate field would be. Here we check | |
1458 | those operands and remove them afterwards. */ | |
1459 | unsigned int x; | |
1460 | ||
a4622f40 | 1461 | for (x = 0; x < i.operands; x++) |
ca164297 L |
1462 | if (i.op[x].regs->reg_num != x) |
1463 | as_bad (_("can't use register '%%%s' as operand %d in '%s'."), | |
1464 | i.op[x].regs->reg_name, x + 1, i.tm.name); | |
1465 | i.operands = 0; | |
1466 | } | |
1467 | ||
29b0f896 AM |
1468 | /* These AMD 3DNow! and Intel Katmai New Instructions have an |
1469 | opcode suffix which is coded in the same place as an 8-bit | |
1470 | immediate field would be. Here we fake an 8-bit immediate | |
1471 | operand from the opcode suffix stored in tm.extension_opcode. */ | |
252b5132 | 1472 | |
29b0f896 | 1473 | assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); |
252b5132 | 1474 | |
29b0f896 AM |
1475 | exp = &im_expressions[i.imm_operands++]; |
1476 | i.op[i.operands].imms = exp; | |
1477 | i.types[i.operands++] = Imm8; | |
1478 | exp->X_op = O_constant; | |
1479 | exp->X_add_number = i.tm.extension_opcode; | |
1480 | i.tm.extension_opcode = None; | |
1481 | } | |
252b5132 | 1482 | |
29b0f896 AM |
1483 | /* For insns with operands there are more diddles to do to the opcode. */ |
1484 | if (i.operands) | |
1485 | { | |
1486 | if (!process_operands ()) | |
1487 | return; | |
1488 | } | |
1489 | else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) | |
1490 | { | |
1491 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
1492 | as_warn (_("translating to `%sp'"), i.tm.name); | |
1493 | } | |
252b5132 | 1494 | |
29b0f896 AM |
1495 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
1496 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) | |
1497 | { | |
1498 | i.tm.base_opcode = INT3_OPCODE; | |
1499 | i.imm_operands = 0; | |
1500 | } | |
252b5132 | 1501 | |
29b0f896 AM |
1502 | if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) |
1503 | && i.op[0].disps->X_op == O_constant) | |
1504 | { | |
1505 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
1506 | the absolute address given by the constant. Since ix86 jumps and | |
1507 | calls are pc relative, we need to generate a reloc. */ | |
1508 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
1509 | i.op[0].disps->X_op = O_symbol; | |
1510 | } | |
252b5132 | 1511 | |
29b0f896 AM |
1512 | if ((i.tm.opcode_modifier & Rex64) != 0) |
1513 | i.rex |= REX_MODE64; | |
252b5132 | 1514 | |
29b0f896 AM |
1515 | /* For 8 bit registers we need an empty rex prefix. Also if the |
1516 | instruction already has a prefix, we need to convert old | |
1517 | registers to new ones. */ | |
773f551c | 1518 | |
29b0f896 AM |
1519 | if (((i.types[0] & Reg8) != 0 |
1520 | && (i.op[0].regs->reg_flags & RegRex64) != 0) | |
1521 | || ((i.types[1] & Reg8) != 0 | |
1522 | && (i.op[1].regs->reg_flags & RegRex64) != 0) | |
1523 | || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0) | |
1524 | && i.rex != 0)) | |
1525 | { | |
1526 | int x; | |
726c5dcd | 1527 | |
29b0f896 AM |
1528 | i.rex |= REX_OPCODE; |
1529 | for (x = 0; x < 2; x++) | |
1530 | { | |
1531 | /* Look for 8 bit operand that uses old registers. */ | |
1532 | if ((i.types[x] & Reg8) != 0 | |
1533 | && (i.op[x].regs->reg_flags & RegRex64) == 0) | |
773f551c | 1534 | { |
29b0f896 AM |
1535 | /* In case it is "hi" register, give up. */ |
1536 | if (i.op[x].regs->reg_num > 3) | |
0477af35 | 1537 | as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."), |
29b0f896 | 1538 | i.op[x].regs->reg_name); |
773f551c | 1539 | |
29b0f896 AM |
1540 | /* Otherwise it is equivalent to the extended register. |
1541 | Since the encoding doesn't change this is merely | |
1542 | cosmetic cleanup for debug output. */ | |
1543 | ||
1544 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 1545 | } |
29b0f896 AM |
1546 | } |
1547 | } | |
773f551c | 1548 | |
29b0f896 AM |
1549 | if (i.rex != 0) |
1550 | add_prefix (REX_OPCODE | i.rex); | |
1551 | ||
1552 | /* We are ready to output the insn. */ | |
1553 | output_insn (); | |
1554 | } | |
1555 | ||
1556 | static char * | |
1557 | parse_insn (line, mnemonic) | |
1558 | char *line; | |
1559 | char *mnemonic; | |
1560 | { | |
1561 | char *l = line; | |
1562 | char *token_start = l; | |
1563 | char *mnem_p; | |
1564 | ||
1565 | /* Non-zero if we found a prefix only acceptable with string insns. */ | |
1566 | const char *expecting_string_instruction = NULL; | |
45288df1 | 1567 | |
29b0f896 AM |
1568 | while (1) |
1569 | { | |
1570 | mnem_p = mnemonic; | |
1571 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
1572 | { | |
1573 | mnem_p++; | |
1574 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 1575 | { |
29b0f896 AM |
1576 | as_bad (_("no such instruction: `%s'"), token_start); |
1577 | return NULL; | |
1578 | } | |
1579 | l++; | |
1580 | } | |
1581 | if (!is_space_char (*l) | |
1582 | && *l != END_OF_INSN | |
1583 | && *l != PREFIX_SEPARATOR | |
1584 | && *l != ',') | |
1585 | { | |
1586 | as_bad (_("invalid character %s in mnemonic"), | |
1587 | output_invalid (*l)); | |
1588 | return NULL; | |
1589 | } | |
1590 | if (token_start == l) | |
1591 | { | |
1592 | if (*l == PREFIX_SEPARATOR) | |
1593 | as_bad (_("expecting prefix; got nothing")); | |
1594 | else | |
1595 | as_bad (_("expecting mnemonic; got nothing")); | |
1596 | return NULL; | |
1597 | } | |
45288df1 | 1598 | |
29b0f896 AM |
1599 | /* Look up instruction (or prefix) via hash table. */ |
1600 | current_templates = hash_find (op_hash, mnemonic); | |
47926f60 | 1601 | |
29b0f896 AM |
1602 | if (*l != END_OF_INSN |
1603 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
1604 | && current_templates | |
1605 | && (current_templates->start->opcode_modifier & IsPrefix)) | |
1606 | { | |
1607 | /* If we are in 16-bit mode, do not allow addr16 or data16. | |
1608 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
1609 | if ((current_templates->start->opcode_modifier & (Size16 | Size32)) | |
1610 | && flag_code != CODE_64BIT | |
1611 | && (((current_templates->start->opcode_modifier & Size32) != 0) | |
1612 | ^ (flag_code == CODE_16BIT))) | |
1613 | { | |
1614 | as_bad (_("redundant %s prefix"), | |
1615 | current_templates->start->name); | |
1616 | return NULL; | |
45288df1 | 1617 | } |
29b0f896 AM |
1618 | /* Add prefix, checking for repeated prefixes. */ |
1619 | switch (add_prefix (current_templates->start->base_opcode)) | |
1620 | { | |
1621 | case 0: | |
1622 | return NULL; | |
1623 | case 2: | |
1624 | expecting_string_instruction = current_templates->start->name; | |
1625 | break; | |
1626 | } | |
1627 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
1628 | token_start = ++l; | |
1629 | } | |
1630 | else | |
1631 | break; | |
1632 | } | |
45288df1 | 1633 | |
29b0f896 AM |
1634 | if (!current_templates) |
1635 | { | |
1636 | /* See if we can get a match by trimming off a suffix. */ | |
1637 | switch (mnem_p[-1]) | |
1638 | { | |
1639 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
1640 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
1641 | i.suffix = SHORT_MNEM_SUFFIX; | |
1642 | else | |
29b0f896 AM |
1643 | case BYTE_MNEM_SUFFIX: |
1644 | case QWORD_MNEM_SUFFIX: | |
1645 | i.suffix = mnem_p[-1]; | |
1646 | mnem_p[-1] = '\0'; | |
1647 | current_templates = hash_find (op_hash, mnemonic); | |
1648 | break; | |
1649 | case SHORT_MNEM_SUFFIX: | |
1650 | case LONG_MNEM_SUFFIX: | |
1651 | if (!intel_syntax) | |
1652 | { | |
1653 | i.suffix = mnem_p[-1]; | |
1654 | mnem_p[-1] = '\0'; | |
1655 | current_templates = hash_find (op_hash, mnemonic); | |
1656 | } | |
1657 | break; | |
252b5132 | 1658 | |
29b0f896 AM |
1659 | /* Intel Syntax. */ |
1660 | case 'd': | |
1661 | if (intel_syntax) | |
1662 | { | |
9306ca4a | 1663 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
1664 | i.suffix = SHORT_MNEM_SUFFIX; |
1665 | else | |
1666 | i.suffix = LONG_MNEM_SUFFIX; | |
1667 | mnem_p[-1] = '\0'; | |
1668 | current_templates = hash_find (op_hash, mnemonic); | |
1669 | } | |
1670 | break; | |
1671 | } | |
1672 | if (!current_templates) | |
1673 | { | |
1674 | as_bad (_("no such instruction: `%s'"), token_start); | |
1675 | return NULL; | |
1676 | } | |
1677 | } | |
252b5132 | 1678 | |
29b0f896 AM |
1679 | if (current_templates->start->opcode_modifier & (Jump | JumpByte)) |
1680 | { | |
1681 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
1682 | predict taken and predict not taken respectively. | |
1683 | I'm not sure that branch hints actually do anything on loop | |
1684 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
1685 | may work in the future and it doesn't hurt to accept them | |
1686 | now. */ | |
1687 | if (l[0] == ',' && l[1] == 'p') | |
1688 | { | |
1689 | if (l[2] == 't') | |
1690 | { | |
1691 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
1692 | return NULL; | |
1693 | l += 3; | |
1694 | } | |
1695 | else if (l[2] == 'n') | |
1696 | { | |
1697 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
1698 | return NULL; | |
1699 | l += 3; | |
1700 | } | |
1701 | } | |
1702 | } | |
1703 | /* Any other comma loses. */ | |
1704 | if (*l == ',') | |
1705 | { | |
1706 | as_bad (_("invalid character %s in mnemonic"), | |
1707 | output_invalid (*l)); | |
1708 | return NULL; | |
1709 | } | |
252b5132 | 1710 | |
29b0f896 AM |
1711 | /* Check if instruction is supported on specified architecture. */ |
1712 | if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64)) | |
1713 | & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))) | |
1714 | { | |
1715 | as_warn (_("`%s' is not supported on `%s'"), | |
1716 | current_templates->start->name, cpu_arch_name); | |
1717 | } | |
1718 | else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT)) | |
1719 | { | |
1720 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
1721 | } | |
252b5132 | 1722 | |
29b0f896 AM |
1723 | /* Check for rep/repne without a string instruction. */ |
1724 | if (expecting_string_instruction | |
1725 | && !(current_templates->start->opcode_modifier & IsString)) | |
1726 | { | |
1727 | as_bad (_("expecting string instruction after `%s'"), | |
1728 | expecting_string_instruction); | |
1729 | return NULL; | |
1730 | } | |
252b5132 | 1731 | |
29b0f896 AM |
1732 | return l; |
1733 | } | |
252b5132 | 1734 | |
29b0f896 AM |
1735 | static char * |
1736 | parse_operands (l, mnemonic) | |
1737 | char *l; | |
1738 | const char *mnemonic; | |
1739 | { | |
1740 | char *token_start; | |
3138f287 | 1741 | |
29b0f896 AM |
1742 | /* 1 if operand is pending after ','. */ |
1743 | unsigned int expecting_operand = 0; | |
252b5132 | 1744 | |
29b0f896 AM |
1745 | /* Non-zero if operand parens not balanced. */ |
1746 | unsigned int paren_not_balanced; | |
1747 | ||
1748 | while (*l != END_OF_INSN) | |
1749 | { | |
1750 | /* Skip optional white space before operand. */ | |
1751 | if (is_space_char (*l)) | |
1752 | ++l; | |
1753 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
1754 | { | |
1755 | as_bad (_("invalid character %s before operand %d"), | |
1756 | output_invalid (*l), | |
1757 | i.operands + 1); | |
1758 | return NULL; | |
1759 | } | |
1760 | token_start = l; /* after white space */ | |
1761 | paren_not_balanced = 0; | |
1762 | while (paren_not_balanced || *l != ',') | |
1763 | { | |
1764 | if (*l == END_OF_INSN) | |
1765 | { | |
1766 | if (paren_not_balanced) | |
1767 | { | |
1768 | if (!intel_syntax) | |
1769 | as_bad (_("unbalanced parenthesis in operand %d."), | |
1770 | i.operands + 1); | |
1771 | else | |
1772 | as_bad (_("unbalanced brackets in operand %d."), | |
1773 | i.operands + 1); | |
1774 | return NULL; | |
1775 | } | |
1776 | else | |
1777 | break; /* we are done */ | |
1778 | } | |
1779 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
1780 | { | |
1781 | as_bad (_("invalid character %s in operand %d"), | |
1782 | output_invalid (*l), | |
1783 | i.operands + 1); | |
1784 | return NULL; | |
1785 | } | |
1786 | if (!intel_syntax) | |
1787 | { | |
1788 | if (*l == '(') | |
1789 | ++paren_not_balanced; | |
1790 | if (*l == ')') | |
1791 | --paren_not_balanced; | |
1792 | } | |
1793 | else | |
1794 | { | |
1795 | if (*l == '[') | |
1796 | ++paren_not_balanced; | |
1797 | if (*l == ']') | |
1798 | --paren_not_balanced; | |
1799 | } | |
1800 | l++; | |
1801 | } | |
1802 | if (l != token_start) | |
1803 | { /* Yes, we've read in another operand. */ | |
1804 | unsigned int operand_ok; | |
1805 | this_operand = i.operands++; | |
1806 | if (i.operands > MAX_OPERANDS) | |
1807 | { | |
1808 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
1809 | MAX_OPERANDS); | |
1810 | return NULL; | |
1811 | } | |
1812 | /* Now parse operand adding info to 'i' as we go along. */ | |
1813 | END_STRING_AND_SAVE (l); | |
1814 | ||
1815 | if (intel_syntax) | |
1816 | operand_ok = | |
1817 | i386_intel_operand (token_start, | |
1818 | intel_float_operand (mnemonic)); | |
1819 | else | |
1820 | operand_ok = i386_operand (token_start); | |
1821 | ||
1822 | RESTORE_END_STRING (l); | |
1823 | if (!operand_ok) | |
1824 | return NULL; | |
1825 | } | |
1826 | else | |
1827 | { | |
1828 | if (expecting_operand) | |
1829 | { | |
1830 | expecting_operand_after_comma: | |
1831 | as_bad (_("expecting operand after ','; got nothing")); | |
1832 | return NULL; | |
1833 | } | |
1834 | if (*l == ',') | |
1835 | { | |
1836 | as_bad (_("expecting operand before ','; got nothing")); | |
1837 | return NULL; | |
1838 | } | |
1839 | } | |
7f3f1ea2 | 1840 | |
29b0f896 AM |
1841 | /* Now *l must be either ',' or END_OF_INSN. */ |
1842 | if (*l == ',') | |
1843 | { | |
1844 | if (*++l == END_OF_INSN) | |
1845 | { | |
1846 | /* Just skip it, if it's \n complain. */ | |
1847 | goto expecting_operand_after_comma; | |
1848 | } | |
1849 | expecting_operand = 1; | |
1850 | } | |
1851 | } | |
1852 | return l; | |
1853 | } | |
7f3f1ea2 | 1854 | |
29b0f896 AM |
1855 | static void |
1856 | swap_operands () | |
1857 | { | |
1858 | union i386_op temp_op; | |
1859 | unsigned int temp_type; | |
f86103b7 | 1860 | enum bfd_reloc_code_real temp_reloc; |
29b0f896 AM |
1861 | int xchg1 = 0; |
1862 | int xchg2 = 0; | |
252b5132 | 1863 | |
29b0f896 AM |
1864 | if (i.operands == 2) |
1865 | { | |
1866 | xchg1 = 0; | |
1867 | xchg2 = 1; | |
1868 | } | |
1869 | else if (i.operands == 3) | |
1870 | { | |
1871 | xchg1 = 0; | |
1872 | xchg2 = 2; | |
1873 | } | |
1874 | temp_type = i.types[xchg2]; | |
1875 | i.types[xchg2] = i.types[xchg1]; | |
1876 | i.types[xchg1] = temp_type; | |
1877 | temp_op = i.op[xchg2]; | |
1878 | i.op[xchg2] = i.op[xchg1]; | |
1879 | i.op[xchg1] = temp_op; | |
1880 | temp_reloc = i.reloc[xchg2]; | |
1881 | i.reloc[xchg2] = i.reloc[xchg1]; | |
1882 | i.reloc[xchg1] = temp_reloc; | |
1883 | ||
1884 | if (i.mem_operands == 2) | |
1885 | { | |
1886 | const seg_entry *temp_seg; | |
1887 | temp_seg = i.seg[0]; | |
1888 | i.seg[0] = i.seg[1]; | |
1889 | i.seg[1] = temp_seg; | |
1890 | } | |
1891 | } | |
252b5132 | 1892 | |
29b0f896 AM |
1893 | /* Try to ensure constant immediates are represented in the smallest |
1894 | opcode possible. */ | |
1895 | static void | |
1896 | optimize_imm () | |
1897 | { | |
1898 | char guess_suffix = 0; | |
1899 | int op; | |
252b5132 | 1900 | |
29b0f896 AM |
1901 | if (i.suffix) |
1902 | guess_suffix = i.suffix; | |
1903 | else if (i.reg_operands) | |
1904 | { | |
1905 | /* Figure out a suffix from the last register operand specified. | |
1906 | We can't do this properly yet, ie. excluding InOutPortReg, | |
1907 | but the following works for instructions with immediates. | |
1908 | In any case, we can't set i.suffix yet. */ | |
1909 | for (op = i.operands; --op >= 0;) | |
1910 | if (i.types[op] & Reg) | |
252b5132 | 1911 | { |
29b0f896 AM |
1912 | if (i.types[op] & Reg8) |
1913 | guess_suffix = BYTE_MNEM_SUFFIX; | |
1914 | else if (i.types[op] & Reg16) | |
1915 | guess_suffix = WORD_MNEM_SUFFIX; | |
1916 | else if (i.types[op] & Reg32) | |
1917 | guess_suffix = LONG_MNEM_SUFFIX; | |
1918 | else if (i.types[op] & Reg64) | |
1919 | guess_suffix = QWORD_MNEM_SUFFIX; | |
1920 | break; | |
252b5132 | 1921 | } |
29b0f896 AM |
1922 | } |
1923 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
1924 | guess_suffix = WORD_MNEM_SUFFIX; | |
1925 | ||
1926 | for (op = i.operands; --op >= 0;) | |
1927 | if (i.types[op] & Imm) | |
1928 | { | |
1929 | switch (i.op[op].imms->X_op) | |
252b5132 | 1930 | { |
29b0f896 AM |
1931 | case O_constant: |
1932 | /* If a suffix is given, this operand may be shortened. */ | |
1933 | switch (guess_suffix) | |
252b5132 | 1934 | { |
29b0f896 AM |
1935 | case LONG_MNEM_SUFFIX: |
1936 | i.types[op] |= Imm32 | Imm64; | |
1937 | break; | |
1938 | case WORD_MNEM_SUFFIX: | |
1939 | i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64; | |
1940 | break; | |
1941 | case BYTE_MNEM_SUFFIX: | |
1942 | i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64; | |
1943 | break; | |
252b5132 | 1944 | } |
252b5132 | 1945 | |
29b0f896 AM |
1946 | /* If this operand is at most 16 bits, convert it |
1947 | to a signed 16 bit number before trying to see | |
1948 | whether it will fit in an even smaller size. | |
1949 | This allows a 16-bit operand such as $0xffe0 to | |
1950 | be recognised as within Imm8S range. */ | |
1951 | if ((i.types[op] & Imm16) | |
1952 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) | |
252b5132 | 1953 | { |
29b0f896 AM |
1954 | i.op[op].imms->X_add_number = |
1955 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
1956 | } | |
1957 | if ((i.types[op] & Imm32) | |
1958 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) | |
1959 | == 0)) | |
1960 | { | |
1961 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
1962 | ^ ((offsetT) 1 << 31)) | |
1963 | - ((offsetT) 1 << 31)); | |
1964 | } | |
1965 | i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number); | |
252b5132 | 1966 | |
29b0f896 AM |
1967 | /* We must avoid matching of Imm32 templates when 64bit |
1968 | only immediate is available. */ | |
1969 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
1970 | i.types[op] &= ~Imm32; | |
1971 | break; | |
252b5132 | 1972 | |
29b0f896 AM |
1973 | case O_absent: |
1974 | case O_register: | |
1975 | abort (); | |
1976 | ||
1977 | /* Symbols and expressions. */ | |
1978 | default: | |
1979 | /* Convert symbolic operand to proper sizes for matching. */ | |
1980 | switch (guess_suffix) | |
1981 | { | |
1982 | case QWORD_MNEM_SUFFIX: | |
1983 | i.types[op] = Imm64 | Imm32S; | |
1984 | break; | |
1985 | case LONG_MNEM_SUFFIX: | |
20f0a1fc | 1986 | i.types[op] = Imm32; |
29b0f896 AM |
1987 | break; |
1988 | case WORD_MNEM_SUFFIX: | |
20f0a1fc | 1989 | i.types[op] = Imm16; |
29b0f896 AM |
1990 | break; |
1991 | case BYTE_MNEM_SUFFIX: | |
20f0a1fc | 1992 | i.types[op] = Imm8 | Imm8S; |
29b0f896 | 1993 | break; |
252b5132 | 1994 | } |
29b0f896 | 1995 | break; |
252b5132 | 1996 | } |
29b0f896 AM |
1997 | } |
1998 | } | |
47926f60 | 1999 | |
29b0f896 AM |
2000 | /* Try to use the smallest displacement type too. */ |
2001 | static void | |
2002 | optimize_disp () | |
2003 | { | |
2004 | int op; | |
3e73aa7c | 2005 | |
29b0f896 AM |
2006 | for (op = i.operands; --op >= 0;) |
2007 | if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant) | |
252b5132 | 2008 | { |
29b0f896 AM |
2009 | offsetT disp = i.op[op].disps->X_add_number; |
2010 | ||
2011 | if (i.types[op] & Disp16) | |
252b5132 | 2012 | { |
29b0f896 AM |
2013 | /* We know this operand is at most 16 bits, so |
2014 | convert to a signed 16 bit number before trying | |
2015 | to see whether it will fit in an even smaller | |
2016 | size. */ | |
2017 | ||
2018 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); | |
252b5132 | 2019 | } |
29b0f896 | 2020 | else if (i.types[op] & Disp32) |
252b5132 | 2021 | { |
29b0f896 AM |
2022 | /* We know this operand is at most 32 bits, so convert to a |
2023 | signed 32 bit number before trying to see whether it will | |
2024 | fit in an even smaller size. */ | |
2025 | disp &= (((offsetT) 2 << 31) - 1); | |
2026 | disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 2027 | } |
29b0f896 | 2028 | if (flag_code == CODE_64BIT) |
252b5132 | 2029 | { |
29b0f896 AM |
2030 | if (fits_in_signed_long (disp)) |
2031 | i.types[op] |= Disp32S; | |
2032 | if (fits_in_unsigned_long (disp)) | |
2033 | i.types[op] |= Disp32; | |
252b5132 | 2034 | } |
29b0f896 AM |
2035 | if ((i.types[op] & (Disp32 | Disp32S | Disp16)) |
2036 | && fits_in_signed_byte (disp)) | |
2037 | i.types[op] |= Disp8; | |
252b5132 | 2038 | } |
29b0f896 AM |
2039 | } |
2040 | ||
2041 | static int | |
2042 | match_template () | |
2043 | { | |
2044 | /* Points to template once we've found it. */ | |
2045 | const template *t; | |
2046 | unsigned int overlap0, overlap1, overlap2; | |
2047 | unsigned int found_reverse_match; | |
2048 | int suffix_check; | |
2049 | ||
2050 | #define MATCH(overlap, given, template) \ | |
2051 | ((overlap & ~JumpAbsolute) \ | |
2052 | && (((given) & (BaseIndex | JumpAbsolute)) \ | |
2053 | == ((overlap) & (BaseIndex | JumpAbsolute)))) | |
2054 | ||
2055 | /* If given types r0 and r1 are registers they must be of the same type | |
2056 | unless the expected operand type register overlap is null. | |
2057 | Note that Acc in a template matches every size of reg. */ | |
2058 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ | |
2059 | (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \ | |
2060 | || ((g0) & Reg) == ((g1) & Reg) \ | |
2061 | || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) | |
2062 | ||
2063 | overlap0 = 0; | |
2064 | overlap1 = 0; | |
2065 | overlap2 = 0; | |
2066 | found_reverse_match = 0; | |
2067 | suffix_check = (i.suffix == BYTE_MNEM_SUFFIX | |
2068 | ? No_bSuf | |
2069 | : (i.suffix == WORD_MNEM_SUFFIX | |
2070 | ? No_wSuf | |
2071 | : (i.suffix == SHORT_MNEM_SUFFIX | |
2072 | ? No_sSuf | |
2073 | : (i.suffix == LONG_MNEM_SUFFIX | |
2074 | ? No_lSuf | |
2075 | : (i.suffix == QWORD_MNEM_SUFFIX | |
2076 | ? No_qSuf | |
2077 | : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX | |
2078 | ? No_xSuf : 0)))))); | |
2079 | ||
20f0a1fc NC |
2080 | t = current_templates->start; |
2081 | if (i.suffix == QWORD_MNEM_SUFFIX | |
2082 | && flag_code != CODE_64BIT | |
9306ca4a JB |
2083 | && (intel_syntax |
2084 | ? !(t->opcode_modifier & IgnoreSize) | |
2085 | && !intel_float_operand (t->name) | |
2086 | : intel_float_operand (t->name) != 2) | |
20f0a1fc NC |
2087 | && (!(t->operand_types[0] & (RegMMX | RegXMM)) |
2088 | || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM))) | |
2089 | && (t->base_opcode != 0x0fc7 | |
2090 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
2091 | t = current_templates->end; | |
2092 | for (; t < current_templates->end; t++) | |
29b0f896 AM |
2093 | { |
2094 | /* Must have right number of operands. */ | |
2095 | if (i.operands != t->operands) | |
2096 | continue; | |
2097 | ||
2098 | /* Check the suffix, except for some instructions in intel mode. */ | |
2099 | if ((t->opcode_modifier & suffix_check) | |
2100 | && !(intel_syntax | |
9306ca4a | 2101 | && (t->opcode_modifier & IgnoreSize))) |
29b0f896 AM |
2102 | continue; |
2103 | ||
2104 | /* Do not verify operands when there are none. */ | |
2105 | else if (!t->operands) | |
2106 | { | |
2107 | if (t->cpu_flags & ~cpu_arch_flags) | |
2108 | continue; | |
2109 | /* We've found a match; break out of loop. */ | |
2110 | break; | |
2111 | } | |
252b5132 | 2112 | |
29b0f896 AM |
2113 | overlap0 = i.types[0] & t->operand_types[0]; |
2114 | switch (t->operands) | |
2115 | { | |
2116 | case 1: | |
2117 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])) | |
2118 | continue; | |
2119 | break; | |
2120 | case 2: | |
2121 | case 3: | |
2122 | overlap1 = i.types[1] & t->operand_types[1]; | |
2123 | if (!MATCH (overlap0, i.types[0], t->operand_types[0]) | |
2124 | || !MATCH (overlap1, i.types[1], t->operand_types[1]) | |
2125 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
2126 | t->operand_types[0], | |
2127 | overlap1, i.types[1], | |
2128 | t->operand_types[1])) | |
2129 | { | |
2130 | /* Check if other direction is valid ... */ | |
2131 | if ((t->opcode_modifier & (D | FloatD)) == 0) | |
2132 | continue; | |
2133 | ||
2134 | /* Try reversing direction of operands. */ | |
2135 | overlap0 = i.types[0] & t->operand_types[1]; | |
2136 | overlap1 = i.types[1] & t->operand_types[0]; | |
2137 | if (!MATCH (overlap0, i.types[0], t->operand_types[1]) | |
2138 | || !MATCH (overlap1, i.types[1], t->operand_types[0]) | |
2139 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
2140 | t->operand_types[1], | |
2141 | overlap1, i.types[1], | |
2142 | t->operand_types[0])) | |
2143 | { | |
2144 | /* Does not match either direction. */ | |
2145 | continue; | |
2146 | } | |
2147 | /* found_reverse_match holds which of D or FloatDR | |
2148 | we've found. */ | |
2149 | found_reverse_match = t->opcode_modifier & (D | FloatDR); | |
2150 | } | |
2151 | /* Found a forward 2 operand match here. */ | |
2152 | else if (t->operands == 3) | |
2153 | { | |
2154 | /* Here we make use of the fact that there are no | |
2155 | reverse match 3 operand instructions, and all 3 | |
2156 | operand instructions only need to be checked for | |
2157 | register consistency between operands 2 and 3. */ | |
2158 | overlap2 = i.types[2] & t->operand_types[2]; | |
2159 | if (!MATCH (overlap2, i.types[2], t->operand_types[2]) | |
2160 | || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], | |
2161 | t->operand_types[1], | |
2162 | overlap2, i.types[2], | |
2163 | t->operand_types[2])) | |
2164 | ||
2165 | continue; | |
2166 | } | |
2167 | /* Found either forward/reverse 2 or 3 operand match here: | |
2168 | slip through to break. */ | |
2169 | } | |
2170 | if (t->cpu_flags & ~cpu_arch_flags) | |
2171 | { | |
2172 | found_reverse_match = 0; | |
2173 | continue; | |
2174 | } | |
2175 | /* We've found a match; break out of loop. */ | |
2176 | break; | |
2177 | } | |
2178 | ||
2179 | if (t == current_templates->end) | |
2180 | { | |
2181 | /* We found no match. */ | |
2182 | as_bad (_("suffix or operands invalid for `%s'"), | |
2183 | current_templates->start->name); | |
2184 | return 0; | |
2185 | } | |
252b5132 | 2186 | |
29b0f896 AM |
2187 | if (!quiet_warnings) |
2188 | { | |
2189 | if (!intel_syntax | |
2190 | && ((i.types[0] & JumpAbsolute) | |
2191 | != (t->operand_types[0] & JumpAbsolute))) | |
2192 | { | |
2193 | as_warn (_("indirect %s without `*'"), t->name); | |
2194 | } | |
2195 | ||
2196 | if ((t->opcode_modifier & (IsPrefix | IgnoreSize)) | |
2197 | == (IsPrefix | IgnoreSize)) | |
2198 | { | |
2199 | /* Warn them that a data or address size prefix doesn't | |
2200 | affect assembly of the next line of code. */ | |
2201 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
2202 | } | |
2203 | } | |
2204 | ||
2205 | /* Copy the template we found. */ | |
2206 | i.tm = *t; | |
2207 | if (found_reverse_match) | |
2208 | { | |
2209 | /* If we found a reverse match we must alter the opcode | |
2210 | direction bit. found_reverse_match holds bits to change | |
2211 | (different for int & float insns). */ | |
2212 | ||
2213 | i.tm.base_opcode ^= found_reverse_match; | |
2214 | ||
2215 | i.tm.operand_types[0] = t->operand_types[1]; | |
2216 | i.tm.operand_types[1] = t->operand_types[0]; | |
2217 | } | |
2218 | ||
2219 | return 1; | |
2220 | } | |
2221 | ||
2222 | static int | |
2223 | check_string () | |
2224 | { | |
2225 | int mem_op = (i.types[0] & AnyMem) ? 0 : 1; | |
2226 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) | |
2227 | { | |
2228 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
2229 | { | |
2230 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
2231 | i.tm.name, | |
2232 | mem_op + 1); | |
2233 | return 0; | |
2234 | } | |
2235 | /* There's only ever one segment override allowed per instruction. | |
2236 | This instruction possibly has a legal segment override on the | |
2237 | second operand, so copy the segment to where non-string | |
2238 | instructions store it, allowing common code. */ | |
2239 | i.seg[0] = i.seg[1]; | |
2240 | } | |
2241 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) | |
2242 | { | |
2243 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
2244 | { | |
2245 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
2246 | i.tm.name, | |
2247 | mem_op + 2); | |
2248 | return 0; | |
2249 | } | |
2250 | } | |
2251 | return 1; | |
2252 | } | |
2253 | ||
2254 | static int | |
543613e9 | 2255 | process_suffix (void) |
29b0f896 AM |
2256 | { |
2257 | /* If matched instruction specifies an explicit instruction mnemonic | |
2258 | suffix, use it. */ | |
2259 | if (i.tm.opcode_modifier & (Size16 | Size32 | Size64)) | |
2260 | { | |
2261 | if (i.tm.opcode_modifier & Size16) | |
2262 | i.suffix = WORD_MNEM_SUFFIX; | |
2263 | else if (i.tm.opcode_modifier & Size64) | |
2264 | i.suffix = QWORD_MNEM_SUFFIX; | |
2265 | else | |
2266 | i.suffix = LONG_MNEM_SUFFIX; | |
2267 | } | |
2268 | else if (i.reg_operands) | |
2269 | { | |
2270 | /* If there's no instruction mnemonic suffix we try to invent one | |
2271 | based on register operands. */ | |
2272 | if (!i.suffix) | |
2273 | { | |
2274 | /* We take i.suffix from the last register operand specified, | |
2275 | Destination register type is more significant than source | |
2276 | register type. */ | |
2277 | int op; | |
543613e9 | 2278 | |
29b0f896 AM |
2279 | for (op = i.operands; --op >= 0;) |
2280 | if ((i.types[op] & Reg) | |
2281 | && !(i.tm.operand_types[op] & InOutPortReg)) | |
2282 | { | |
2283 | i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : | |
2284 | (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : | |
2285 | (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX : | |
2286 | LONG_MNEM_SUFFIX); | |
2287 | break; | |
2288 | } | |
2289 | } | |
2290 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
2291 | { | |
2292 | if (!check_byte_reg ()) | |
2293 | return 0; | |
2294 | } | |
2295 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
2296 | { | |
2297 | if (!check_long_reg ()) | |
2298 | return 0; | |
2299 | } | |
2300 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
2301 | { | |
2302 | if (!check_qword_reg ()) | |
2303 | return 0; | |
2304 | } | |
2305 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
2306 | { | |
2307 | if (!check_word_reg ()) | |
2308 | return 0; | |
2309 | } | |
2310 | else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize)) | |
2311 | /* Do nothing if the instruction is going to ignore the prefix. */ | |
2312 | ; | |
2313 | else | |
2314 | abort (); | |
2315 | } | |
9306ca4a JB |
2316 | else if ((i.tm.opcode_modifier & DefaultSize) |
2317 | && !i.suffix | |
2318 | /* exclude fldenv/frstor/fsave/fstenv */ | |
2319 | && (i.tm.opcode_modifier & No_sSuf)) | |
29b0f896 AM |
2320 | { |
2321 | i.suffix = stackop_size; | |
543613e9 NC |
2322 | if (i.suffix == QWORD_MNEM_SUFFIX |
2323 | && (i.tm.opcode_modifier & No_qSuf)) | |
2324 | i.suffix = LONG_MNEM_SUFFIX; | |
29b0f896 | 2325 | } |
9306ca4a JB |
2326 | else if (intel_syntax |
2327 | && !i.suffix | |
2328 | && ((i.tm.operand_types[0] & JumpAbsolute) | |
2329 | || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment)) | |
2330 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ | |
2331 | && i.tm.extension_opcode <= 3))) | |
2332 | { | |
2333 | switch (flag_code) | |
2334 | { | |
2335 | case CODE_64BIT: | |
2336 | if (!(i.tm.opcode_modifier & No_qSuf)) | |
2337 | { | |
2338 | i.suffix = QWORD_MNEM_SUFFIX; | |
2339 | break; | |
2340 | } | |
2341 | case CODE_32BIT: | |
2342 | if (!(i.tm.opcode_modifier & No_lSuf)) | |
2343 | i.suffix = LONG_MNEM_SUFFIX; | |
2344 | break; | |
2345 | case CODE_16BIT: | |
2346 | if (!(i.tm.opcode_modifier & No_wSuf)) | |
2347 | i.suffix = WORD_MNEM_SUFFIX; | |
2348 | break; | |
2349 | } | |
2350 | } | |
252b5132 | 2351 | |
9306ca4a | 2352 | if (!i.suffix) |
29b0f896 | 2353 | { |
9306ca4a JB |
2354 | if (!intel_syntax) |
2355 | { | |
2356 | if (i.tm.opcode_modifier & W) | |
2357 | { | |
2358 | as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); | |
2359 | return 0; | |
2360 | } | |
2361 | } | |
2362 | else | |
2363 | { | |
2364 | unsigned int suffixes = ~i.tm.opcode_modifier | |
2365 | & (No_bSuf | |
2366 | | No_wSuf | |
2367 | | No_lSuf | |
2368 | | No_sSuf | |
2369 | | No_xSuf | |
2370 | | No_qSuf); | |
2371 | ||
2372 | if ((i.tm.opcode_modifier & W) | |
2373 | || ((suffixes & (suffixes - 1)) | |
2374 | && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize)))) | |
2375 | { | |
2376 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
2377 | return 0; | |
2378 | } | |
2379 | } | |
29b0f896 | 2380 | } |
252b5132 | 2381 | |
9306ca4a JB |
2382 | /* Change the opcode based on the operand size given by i.suffix; |
2383 | We don't need to change things for byte insns. */ | |
2384 | ||
29b0f896 AM |
2385 | if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) |
2386 | { | |
2387 | /* It's not a byte, select word/dword operation. */ | |
2388 | if (i.tm.opcode_modifier & W) | |
2389 | { | |
2390 | if (i.tm.opcode_modifier & ShortForm) | |
2391 | i.tm.base_opcode |= 8; | |
2392 | else | |
2393 | i.tm.base_opcode |= 1; | |
2394 | } | |
0f3f3d8b | 2395 | |
29b0f896 AM |
2396 | /* Now select between word & dword operations via the operand |
2397 | size prefix, except for instructions that will ignore this | |
2398 | prefix anyway. */ | |
2399 | if (i.suffix != QWORD_MNEM_SUFFIX | |
9306ca4a JB |
2400 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX |
2401 | && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF)) | |
9146926a AM |
2402 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
2403 | || (flag_code == CODE_64BIT | |
2404 | && (i.tm.opcode_modifier & JumpByte)))) | |
24eab124 AM |
2405 | { |
2406 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 2407 | |
29b0f896 AM |
2408 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ |
2409 | prefix = ADDR_PREFIX_OPCODE; | |
252b5132 | 2410 | |
29b0f896 AM |
2411 | if (!add_prefix (prefix)) |
2412 | return 0; | |
24eab124 | 2413 | } |
252b5132 | 2414 | |
29b0f896 AM |
2415 | /* Set mode64 for an operand. */ |
2416 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 2417 | && flag_code == CODE_64BIT |
29b0f896 | 2418 | && (i.tm.opcode_modifier & NoRex64) == 0) |
9146926a | 2419 | i.rex |= REX_MODE64; |
3e73aa7c | 2420 | |
29b0f896 AM |
2421 | /* Size floating point instruction. */ |
2422 | if (i.suffix == LONG_MNEM_SUFFIX) | |
543613e9 NC |
2423 | if (i.tm.opcode_modifier & FloatMF) |
2424 | i.tm.base_opcode ^= 4; | |
29b0f896 | 2425 | } |
7ecd2f8b | 2426 | |
29b0f896 AM |
2427 | return 1; |
2428 | } | |
3e73aa7c | 2429 | |
29b0f896 | 2430 | static int |
543613e9 | 2431 | check_byte_reg (void) |
29b0f896 AM |
2432 | { |
2433 | int op; | |
543613e9 | 2434 | |
29b0f896 AM |
2435 | for (op = i.operands; --op >= 0;) |
2436 | { | |
2437 | /* If this is an eight bit register, it's OK. If it's the 16 or | |
2438 | 32 bit version of an eight bit register, we will just use the | |
2439 | low portion, and that's OK too. */ | |
2440 | if (i.types[op] & Reg8) | |
2441 | continue; | |
2442 | ||
2443 | /* movzx and movsx should not generate this warning. */ | |
2444 | if (intel_syntax | |
2445 | && (i.tm.base_opcode == 0xfb7 | |
2446 | || i.tm.base_opcode == 0xfb6 | |
2447 | || i.tm.base_opcode == 0x63 | |
2448 | || i.tm.base_opcode == 0xfbe | |
2449 | || i.tm.base_opcode == 0xfbf)) | |
2450 | continue; | |
2451 | ||
2452 | if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4 | |
2453 | #if 0 | |
2454 | /* Check that the template allows eight bit regs. This | |
2455 | kills insns such as `orb $1,%edx', which maybe should be | |
2456 | allowed. */ | |
2457 | && (i.tm.operand_types[op] & (Reg8 | InOutPortReg)) | |
2458 | #endif | |
2459 | ) | |
2460 | { | |
2461 | /* Prohibit these changes in the 64bit mode, since the | |
2462 | lowering is more complicated. */ | |
2463 | if (flag_code == CODE_64BIT | |
2464 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
2465 | { | |
0f3f3d8b | 2466 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), |
29b0f896 AM |
2467 | i.op[op].regs->reg_name, |
2468 | i.suffix); | |
2469 | return 0; | |
2470 | } | |
2471 | #if REGISTER_WARNINGS | |
2472 | if (!quiet_warnings | |
2473 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
2474 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
2475 | (i.op[op].regs + (i.types[op] & Reg16 | |
2476 | ? REGNAM_AL - REGNAM_AX | |
2477 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
2478 | i.op[op].regs->reg_name, | |
2479 | i.suffix); | |
2480 | #endif | |
2481 | continue; | |
2482 | } | |
2483 | /* Any other register is bad. */ | |
2484 | if (i.types[op] & (Reg | RegMMX | RegXMM | |
2485 | | SReg2 | SReg3 | |
2486 | | Control | Debug | Test | |
2487 | | FloatReg | FloatAcc)) | |
2488 | { | |
2489 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
2490 | i.op[op].regs->reg_name, | |
2491 | i.tm.name, | |
2492 | i.suffix); | |
2493 | return 0; | |
2494 | } | |
2495 | } | |
2496 | return 1; | |
2497 | } | |
2498 | ||
2499 | static int | |
2500 | check_long_reg () | |
2501 | { | |
2502 | int op; | |
2503 | ||
2504 | for (op = i.operands; --op >= 0;) | |
2505 | /* Reject eight bit registers, except where the template requires | |
2506 | them. (eg. movzb) */ | |
2507 | if ((i.types[op] & Reg8) != 0 | |
2508 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) | |
2509 | { | |
2510 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
2511 | i.op[op].regs->reg_name, | |
2512 | i.tm.name, | |
2513 | i.suffix); | |
2514 | return 0; | |
2515 | } | |
2516 | /* Warn if the e prefix on a general reg is missing. */ | |
2517 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
2518 | && (i.types[op] & Reg16) != 0 | |
2519 | && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) | |
2520 | { | |
2521 | /* Prohibit these changes in the 64bit mode, since the | |
2522 | lowering is more complicated. */ | |
2523 | if (flag_code == CODE_64BIT) | |
252b5132 | 2524 | { |
0f3f3d8b | 2525 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), |
29b0f896 AM |
2526 | i.op[op].regs->reg_name, |
2527 | i.suffix); | |
2528 | return 0; | |
252b5132 | 2529 | } |
29b0f896 AM |
2530 | #if REGISTER_WARNINGS |
2531 | else | |
2532 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
2533 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
2534 | i.op[op].regs->reg_name, | |
2535 | i.suffix); | |
2536 | #endif | |
252b5132 | 2537 | } |
29b0f896 AM |
2538 | /* Warn if the r prefix on a general reg is missing. */ |
2539 | else if ((i.types[op] & Reg64) != 0 | |
2540 | && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) | |
252b5132 | 2541 | { |
0f3f3d8b | 2542 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), |
29b0f896 AM |
2543 | i.op[op].regs->reg_name, |
2544 | i.suffix); | |
2545 | return 0; | |
2546 | } | |
2547 | return 1; | |
2548 | } | |
252b5132 | 2549 | |
29b0f896 AM |
2550 | static int |
2551 | check_qword_reg () | |
2552 | { | |
2553 | int op; | |
252b5132 | 2554 | |
29b0f896 AM |
2555 | for (op = i.operands; --op >= 0; ) |
2556 | /* Reject eight bit registers, except where the template requires | |
2557 | them. (eg. movzb) */ | |
2558 | if ((i.types[op] & Reg8) != 0 | |
2559 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) | |
2560 | { | |
2561 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
2562 | i.op[op].regs->reg_name, | |
2563 | i.tm.name, | |
2564 | i.suffix); | |
2565 | return 0; | |
2566 | } | |
2567 | /* Warn if the e prefix on a general reg is missing. */ | |
2568 | else if (((i.types[op] & Reg16) != 0 | |
2569 | || (i.types[op] & Reg32) != 0) | |
2570 | && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) | |
2571 | { | |
2572 | /* Prohibit these changes in the 64bit mode, since the | |
2573 | lowering is more complicated. */ | |
0f3f3d8b | 2574 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), |
29b0f896 AM |
2575 | i.op[op].regs->reg_name, |
2576 | i.suffix); | |
2577 | return 0; | |
252b5132 | 2578 | } |
29b0f896 AM |
2579 | return 1; |
2580 | } | |
252b5132 | 2581 | |
29b0f896 AM |
2582 | static int |
2583 | check_word_reg () | |
2584 | { | |
2585 | int op; | |
2586 | for (op = i.operands; --op >= 0;) | |
2587 | /* Reject eight bit registers, except where the template requires | |
2588 | them. (eg. movzb) */ | |
2589 | if ((i.types[op] & Reg8) != 0 | |
2590 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) | |
2591 | { | |
2592 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
2593 | i.op[op].regs->reg_name, | |
2594 | i.tm.name, | |
2595 | i.suffix); | |
2596 | return 0; | |
2597 | } | |
2598 | /* Warn if the e prefix on a general reg is present. */ | |
2599 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
2600 | && (i.types[op] & Reg32) != 0 | |
2601 | && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0) | |
252b5132 | 2602 | { |
29b0f896 AM |
2603 | /* Prohibit these changes in the 64bit mode, since the |
2604 | lowering is more complicated. */ | |
2605 | if (flag_code == CODE_64BIT) | |
252b5132 | 2606 | { |
0f3f3d8b | 2607 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), |
29b0f896 AM |
2608 | i.op[op].regs->reg_name, |
2609 | i.suffix); | |
2610 | return 0; | |
252b5132 | 2611 | } |
29b0f896 AM |
2612 | else |
2613 | #if REGISTER_WARNINGS | |
2614 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
2615 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
2616 | i.op[op].regs->reg_name, | |
2617 | i.suffix); | |
2618 | #endif | |
2619 | } | |
2620 | return 1; | |
2621 | } | |
252b5132 | 2622 | |
29b0f896 AM |
2623 | static int |
2624 | finalize_imm () | |
2625 | { | |
2626 | unsigned int overlap0, overlap1, overlap2; | |
2627 | ||
2628 | overlap0 = i.types[0] & i.tm.operand_types[0]; | |
20f0a1fc | 2629 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64)) |
29b0f896 AM |
2630 | && overlap0 != Imm8 && overlap0 != Imm8S |
2631 | && overlap0 != Imm16 && overlap0 != Imm32S | |
2632 | && overlap0 != Imm32 && overlap0 != Imm64) | |
2633 | { | |
2634 | if (i.suffix) | |
2635 | { | |
2636 | overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX | |
2637 | ? Imm8 | Imm8S | |
2638 | : (i.suffix == WORD_MNEM_SUFFIX | |
2639 | ? Imm16 | |
2640 | : (i.suffix == QWORD_MNEM_SUFFIX | |
2641 | ? Imm64 | Imm32S | |
2642 | : Imm32))); | |
2643 | } | |
2644 | else if (overlap0 == (Imm16 | Imm32S | Imm32) | |
2645 | || overlap0 == (Imm16 | Imm32) | |
2646 | || overlap0 == (Imm16 | Imm32S)) | |
2647 | { | |
2648 | overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) | |
2649 | ? Imm16 : Imm32S); | |
2650 | } | |
2651 | if (overlap0 != Imm8 && overlap0 != Imm8S | |
2652 | && overlap0 != Imm16 && overlap0 != Imm32S | |
2653 | && overlap0 != Imm32 && overlap0 != Imm64) | |
2654 | { | |
2655 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); | |
2656 | return 0; | |
2657 | } | |
2658 | } | |
2659 | i.types[0] = overlap0; | |
2660 | ||
2661 | overlap1 = i.types[1] & i.tm.operand_types[1]; | |
2662 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32)) | |
2663 | && overlap1 != Imm8 && overlap1 != Imm8S | |
2664 | && overlap1 != Imm16 && overlap1 != Imm32S | |
2665 | && overlap1 != Imm32 && overlap1 != Imm64) | |
2666 | { | |
2667 | if (i.suffix) | |
2668 | { | |
2669 | overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX | |
2670 | ? Imm8 | Imm8S | |
2671 | : (i.suffix == WORD_MNEM_SUFFIX | |
2672 | ? Imm16 | |
2673 | : (i.suffix == QWORD_MNEM_SUFFIX | |
2674 | ? Imm64 | Imm32S | |
2675 | : Imm32))); | |
2676 | } | |
2677 | else if (overlap1 == (Imm16 | Imm32 | Imm32S) | |
2678 | || overlap1 == (Imm16 | Imm32) | |
2679 | || overlap1 == (Imm16 | Imm32S)) | |
2680 | { | |
2681 | overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) | |
2682 | ? Imm16 : Imm32S); | |
2683 | } | |
2684 | if (overlap1 != Imm8 && overlap1 != Imm8S | |
2685 | && overlap1 != Imm16 && overlap1 != Imm32S | |
2686 | && overlap1 != Imm32 && overlap1 != Imm64) | |
2687 | { | |
2688 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix); | |
2689 | return 0; | |
2690 | } | |
2691 | } | |
2692 | i.types[1] = overlap1; | |
2693 | ||
2694 | overlap2 = i.types[2] & i.tm.operand_types[2]; | |
2695 | assert ((overlap2 & Imm) == 0); | |
2696 | i.types[2] = overlap2; | |
2697 | ||
2698 | return 1; | |
2699 | } | |
2700 | ||
2701 | static int | |
2702 | process_operands () | |
2703 | { | |
2704 | /* Default segment register this instruction will use for memory | |
2705 | accesses. 0 means unknown. This is only for optimizing out | |
2706 | unnecessary segment overrides. */ | |
2707 | const seg_entry *default_seg = 0; | |
2708 | ||
2709 | /* The imul $imm, %reg instruction is converted into | |
2710 | imul $imm, %reg, %reg, and the clr %reg instruction | |
2711 | is converted into xor %reg, %reg. */ | |
2712 | if (i.tm.opcode_modifier & regKludge) | |
2713 | { | |
2714 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; | |
2715 | /* Pretend we saw the extra register operand. */ | |
2716 | assert (i.op[first_reg_op + 1].regs == 0); | |
2717 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; | |
2718 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
2719 | i.reg_operands = 2; | |
2720 | } | |
2721 | ||
2722 | if (i.tm.opcode_modifier & ShortForm) | |
2723 | { | |
2724 | /* The register or float register operand is in operand 0 or 1. */ | |
2725 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; | |
2726 | /* Register goes in low 3 bits of opcode. */ | |
2727 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
2728 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
2729 | i.rex |= REX_EXTZ; | |
2730 | if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) | |
2731 | { | |
2732 | /* Warn about some common errors, but press on regardless. | |
2733 | The first case can be generated by gcc (<= 2.8.1). */ | |
2734 | if (i.operands == 2) | |
2735 | { | |
2736 | /* Reversed arguments on faddp, fsubp, etc. */ | |
2737 | as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, | |
2738 | i.op[1].regs->reg_name, | |
2739 | i.op[0].regs->reg_name); | |
2740 | } | |
2741 | else | |
2742 | { | |
2743 | /* Extraneous `l' suffix on fp insn. */ | |
2744 | as_warn (_("translating to `%s %%%s'"), i.tm.name, | |
2745 | i.op[0].regs->reg_name); | |
2746 | } | |
2747 | } | |
2748 | } | |
2749 | else if (i.tm.opcode_modifier & Modrm) | |
2750 | { | |
2751 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
2752 | must be put into the modrm byte). Now, we make the modrm and |
2753 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
2754 | |
2755 | default_seg = build_modrm_byte (); | |
2756 | } | |
2757 | else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) | |
2758 | { | |
2759 | if (i.tm.base_opcode == POP_SEG_SHORT | |
2760 | && i.op[0].regs->reg_num == 1) | |
2761 | { | |
2762 | as_bad (_("you can't `pop %%cs'")); | |
2763 | return 0; | |
2764 | } | |
2765 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
2766 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
2767 | i.rex |= REX_EXTZ; | |
2768 | } | |
2769 | else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32) | |
2770 | { | |
2771 | default_seg = &ds; | |
2772 | } | |
2773 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
2774 | { | |
2775 | /* For the string instructions that allow a segment override | |
2776 | on one of their operands, the default segment is ds. */ | |
2777 | default_seg = &ds; | |
2778 | } | |
2779 | ||
52271982 AM |
2780 | if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings) |
2781 | as_warn (_("segment override on `lea' is ineffectual")); | |
2782 | ||
2783 | /* If a segment was explicitly specified, and the specified segment | |
2784 | is not the default, use an opcode prefix to select it. If we | |
2785 | never figured out what the default segment is, then default_seg | |
2786 | will be zero at this point, and the specified segment prefix will | |
2787 | always be used. */ | |
29b0f896 AM |
2788 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
2789 | { | |
2790 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
2791 | return 0; | |
2792 | } | |
2793 | return 1; | |
2794 | } | |
2795 | ||
2796 | static const seg_entry * | |
2797 | build_modrm_byte () | |
2798 | { | |
2799 | const seg_entry *default_seg = 0; | |
2800 | ||
2801 | /* i.reg_operands MUST be the number of real register operands; | |
2802 | implicit registers do not count. */ | |
2803 | if (i.reg_operands == 2) | |
2804 | { | |
2805 | unsigned int source, dest; | |
2806 | source = ((i.types[0] | |
2807 | & (Reg | RegMMX | RegXMM | |
2808 | | SReg2 | SReg3 | |
2809 | | Control | Debug | Test)) | |
2810 | ? 0 : 1); | |
2811 | dest = source + 1; | |
2812 | ||
2813 | i.rm.mode = 3; | |
2814 | /* One of the register operands will be encoded in the i.tm.reg | |
2815 | field, the other in the combined i.tm.mode and i.tm.regmem | |
2816 | fields. If no form of this instruction supports a memory | |
2817 | destination operand, then we assume the source operand may | |
2818 | sometimes be a memory operand and so we need to store the | |
2819 | destination in the i.rm.reg field. */ | |
2820 | if ((i.tm.operand_types[dest] & AnyMem) == 0) | |
2821 | { | |
2822 | i.rm.reg = i.op[dest].regs->reg_num; | |
2823 | i.rm.regmem = i.op[source].regs->reg_num; | |
2824 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
2825 | i.rex |= REX_EXTX; | |
2826 | if ((i.op[source].regs->reg_flags & RegRex) != 0) | |
2827 | i.rex |= REX_EXTZ; | |
2828 | } | |
2829 | else | |
2830 | { | |
2831 | i.rm.reg = i.op[source].regs->reg_num; | |
2832 | i.rm.regmem = i.op[dest].regs->reg_num; | |
2833 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
2834 | i.rex |= REX_EXTZ; | |
2835 | if ((i.op[source].regs->reg_flags & RegRex) != 0) | |
2836 | i.rex |= REX_EXTX; | |
2837 | } | |
2838 | } | |
2839 | else | |
2840 | { /* If it's not 2 reg operands... */ | |
2841 | if (i.mem_operands) | |
2842 | { | |
2843 | unsigned int fake_zero_displacement = 0; | |
2844 | unsigned int op = ((i.types[0] & AnyMem) | |
2845 | ? 0 | |
2846 | : (i.types[1] & AnyMem) ? 1 : 2); | |
2847 | ||
2848 | default_seg = &ds; | |
2849 | ||
2850 | if (i.base_reg == 0) | |
2851 | { | |
2852 | i.rm.mode = 0; | |
2853 | if (!i.disp_operands) | |
2854 | fake_zero_displacement = 1; | |
2855 | if (i.index_reg == 0) | |
2856 | { | |
2857 | /* Operand is just <disp> */ | |
20f0a1fc | 2858 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
2859 | { |
2860 | /* 64bit mode overwrites the 32bit absolute | |
2861 | addressing by RIP relative addressing and | |
2862 | absolute addressing is encoded by one of the | |
2863 | redundant SIB forms. */ | |
2864 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2865 | i.sib.base = NO_BASE_REGISTER; | |
2866 | i.sib.index = NO_INDEX_REGISTER; | |
20f0a1fc NC |
2867 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32); |
2868 | } | |
2869 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
2870 | { | |
2871 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2872 | i.types[op] = Disp16; | |
2873 | } | |
2874 | else | |
2875 | { | |
2876 | i.rm.regmem = NO_BASE_REGISTER; | |
2877 | i.types[op] = Disp32; | |
29b0f896 AM |
2878 | } |
2879 | } | |
2880 | else /* !i.base_reg && i.index_reg */ | |
2881 | { | |
2882 | i.sib.index = i.index_reg->reg_num; | |
2883 | i.sib.base = NO_BASE_REGISTER; | |
2884 | i.sib.scale = i.log2_scale_factor; | |
2885 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2886 | i.types[op] &= ~Disp; | |
2887 | if (flag_code != CODE_64BIT) | |
2888 | i.types[op] |= Disp32; /* Must be 32 bit */ | |
2889 | else | |
2890 | i.types[op] |= Disp32S; | |
2891 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
2892 | i.rex |= REX_EXTY; | |
2893 | } | |
2894 | } | |
2895 | /* RIP addressing for 64bit mode. */ | |
2896 | else if (i.base_reg->reg_type == BaseIndex) | |
2897 | { | |
2898 | i.rm.regmem = NO_BASE_REGISTER; | |
20f0a1fc | 2899 | i.types[op] &= ~ Disp; |
29b0f896 AM |
2900 | i.types[op] |= Disp32S; |
2901 | i.flags[op] = Operand_PCrel; | |
20f0a1fc NC |
2902 | if (! i.disp_operands) |
2903 | fake_zero_displacement = 1; | |
29b0f896 AM |
2904 | } |
2905 | else if (i.base_reg->reg_type & Reg16) | |
2906 | { | |
2907 | switch (i.base_reg->reg_num) | |
2908 | { | |
2909 | case 3: /* (%bx) */ | |
2910 | if (i.index_reg == 0) | |
2911 | i.rm.regmem = 7; | |
2912 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
2913 | i.rm.regmem = i.index_reg->reg_num - 6; | |
2914 | break; | |
2915 | case 5: /* (%bp) */ | |
2916 | default_seg = &ss; | |
2917 | if (i.index_reg == 0) | |
2918 | { | |
2919 | i.rm.regmem = 6; | |
2920 | if ((i.types[op] & Disp) == 0) | |
2921 | { | |
2922 | /* fake (%bp) into 0(%bp) */ | |
2923 | i.types[op] |= Disp8; | |
252b5132 | 2924 | fake_zero_displacement = 1; |
29b0f896 AM |
2925 | } |
2926 | } | |
2927 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
2928 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
2929 | break; | |
2930 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
2931 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
2932 | } | |
2933 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2934 | } | |
2935 | else /* i.base_reg and 32/64 bit mode */ | |
2936 | { | |
2937 | if (flag_code == CODE_64BIT | |
2938 | && (i.types[op] & Disp)) | |
20f0a1fc NC |
2939 | i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32); |
2940 | ||
29b0f896 AM |
2941 | i.rm.regmem = i.base_reg->reg_num; |
2942 | if ((i.base_reg->reg_flags & RegRex) != 0) | |
2943 | i.rex |= REX_EXTZ; | |
2944 | i.sib.base = i.base_reg->reg_num; | |
2945 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
2946 | complications. */ | |
2947 | if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) | |
2948 | { | |
2949 | default_seg = &ss; | |
2950 | if (i.disp_operands == 0) | |
2951 | { | |
2952 | fake_zero_displacement = 1; | |
2953 | i.types[op] |= Disp8; | |
2954 | } | |
2955 | } | |
2956 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
2957 | { | |
2958 | default_seg = &ss; | |
2959 | } | |
2960 | i.sib.scale = i.log2_scale_factor; | |
2961 | if (i.index_reg == 0) | |
2962 | { | |
2963 | /* <disp>(%esp) becomes two byte modrm with no index | |
2964 | register. We've already stored the code for esp | |
2965 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
2966 | Any base register besides %esp will not use the | |
2967 | extra modrm byte. */ | |
2968 | i.sib.index = NO_INDEX_REGISTER; | |
2969 | #if !SCALE1_WHEN_NO_INDEX | |
2970 | /* Another case where we force the second modrm byte. */ | |
2971 | if (i.log2_scale_factor) | |
2972 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
252b5132 | 2973 | #endif |
29b0f896 AM |
2974 | } |
2975 | else | |
2976 | { | |
2977 | i.sib.index = i.index_reg->reg_num; | |
2978 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2979 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
2980 | i.rex |= REX_EXTY; | |
2981 | } | |
2982 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2983 | } | |
252b5132 | 2984 | |
29b0f896 AM |
2985 | if (fake_zero_displacement) |
2986 | { | |
2987 | /* Fakes a zero displacement assuming that i.types[op] | |
2988 | holds the correct displacement size. */ | |
2989 | expressionS *exp; | |
2990 | ||
2991 | assert (i.op[op].disps == 0); | |
2992 | exp = &disp_expressions[i.disp_operands++]; | |
2993 | i.op[op].disps = exp; | |
2994 | exp->X_op = O_constant; | |
2995 | exp->X_add_number = 0; | |
2996 | exp->X_add_symbol = (symbolS *) 0; | |
2997 | exp->X_op_symbol = (symbolS *) 0; | |
2998 | } | |
2999 | } | |
252b5132 | 3000 | |
29b0f896 AM |
3001 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
3002 | (if any) based on i.tm.extension_opcode. Again, we must be | |
3003 | careful to make sure that segment/control/debug/test/MMX | |
3004 | registers are coded into the i.rm.reg field. */ | |
3005 | if (i.reg_operands) | |
3006 | { | |
3007 | unsigned int op = | |
3008 | ((i.types[0] | |
3009 | & (Reg | RegMMX | RegXMM | |
3010 | | SReg2 | SReg3 | |
3011 | | Control | Debug | Test)) | |
3012 | ? 0 | |
3013 | : ((i.types[1] | |
3014 | & (Reg | RegMMX | RegXMM | |
3015 | | SReg2 | SReg3 | |
3016 | | Control | Debug | Test)) | |
3017 | ? 1 | |
3018 | : 2)); | |
3019 | /* If there is an extension opcode to put here, the register | |
3020 | number must be put into the regmem field. */ | |
3021 | if (i.tm.extension_opcode != None) | |
3022 | { | |
3023 | i.rm.regmem = i.op[op].regs->reg_num; | |
3024 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
3025 | i.rex |= REX_EXTZ; | |
3026 | } | |
3027 | else | |
3028 | { | |
3029 | i.rm.reg = i.op[op].regs->reg_num; | |
3030 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
3031 | i.rex |= REX_EXTX; | |
3032 | } | |
252b5132 | 3033 | |
29b0f896 AM |
3034 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
3035 | must set it to 3 to indicate this is a register operand | |
3036 | in the regmem field. */ | |
3037 | if (!i.mem_operands) | |
3038 | i.rm.mode = 3; | |
3039 | } | |
252b5132 | 3040 | |
29b0f896 AM |
3041 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
3042 | if (i.tm.extension_opcode != None) | |
3043 | i.rm.reg = i.tm.extension_opcode; | |
3044 | } | |
3045 | return default_seg; | |
3046 | } | |
252b5132 | 3047 | |
29b0f896 AM |
3048 | static void |
3049 | output_branch () | |
3050 | { | |
3051 | char *p; | |
3052 | int code16; | |
3053 | int prefix; | |
3054 | relax_substateT subtype; | |
3055 | symbolS *sym; | |
3056 | offsetT off; | |
3057 | ||
3058 | code16 = 0; | |
3059 | if (flag_code == CODE_16BIT) | |
3060 | code16 = CODE16; | |
3061 | ||
3062 | prefix = 0; | |
3063 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 3064 | { |
29b0f896 AM |
3065 | prefix = 1; |
3066 | i.prefixes -= 1; | |
3067 | code16 ^= CODE16; | |
252b5132 | 3068 | } |
29b0f896 AM |
3069 | /* Pentium4 branch hints. */ |
3070 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
3071 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 3072 | { |
29b0f896 AM |
3073 | prefix++; |
3074 | i.prefixes--; | |
3075 | } | |
3076 | if (i.prefix[REX_PREFIX] != 0) | |
3077 | { | |
3078 | prefix++; | |
3079 | i.prefixes--; | |
2f66722d AM |
3080 | } |
3081 | ||
29b0f896 AM |
3082 | if (i.prefixes != 0 && !intel_syntax) |
3083 | as_warn (_("skipping prefixes on this instruction")); | |
3084 | ||
3085 | /* It's always a symbol; End frag & setup for relax. | |
3086 | Make sure there is enough room in this frag for the largest | |
3087 | instruction we may generate in md_convert_frag. This is 2 | |
3088 | bytes for the opcode and room for the prefix and largest | |
3089 | displacement. */ | |
3090 | frag_grow (prefix + 2 + 4); | |
3091 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
3092 | p = frag_more (prefix + 1); | |
3093 | if (i.prefix[DATA_PREFIX] != 0) | |
3094 | *p++ = DATA_PREFIX_OPCODE; | |
3095 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
3096 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
3097 | *p++ = i.prefix[SEG_PREFIX]; | |
3098 | if (i.prefix[REX_PREFIX] != 0) | |
3099 | *p++ = i.prefix[REX_PREFIX]; | |
3100 | *p = i.tm.base_opcode; | |
3101 | ||
3102 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
3103 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL); | |
3104 | else if ((cpu_arch_flags & Cpu386) != 0) | |
3105 | subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL); | |
3106 | else | |
3107 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL); | |
3108 | subtype |= code16; | |
3e73aa7c | 3109 | |
29b0f896 AM |
3110 | sym = i.op[0].disps->X_add_symbol; |
3111 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 3112 | |
29b0f896 AM |
3113 | if (i.op[0].disps->X_op != O_constant |
3114 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 3115 | { |
29b0f896 AM |
3116 | /* Handle complex expressions. */ |
3117 | sym = make_expr_symbol (i.op[0].disps); | |
3118 | off = 0; | |
3119 | } | |
3e73aa7c | 3120 | |
29b0f896 AM |
3121 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
3122 | Pass reloc in fr_var. */ | |
3123 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); | |
3124 | } | |
3e73aa7c | 3125 | |
29b0f896 AM |
3126 | static void |
3127 | output_jump () | |
3128 | { | |
3129 | char *p; | |
3130 | int size; | |
3e02c1cc | 3131 | fixS *fixP; |
29b0f896 AM |
3132 | |
3133 | if (i.tm.opcode_modifier & JumpByte) | |
3134 | { | |
3135 | /* This is a loop or jecxz type instruction. */ | |
3136 | size = 1; | |
3137 | if (i.prefix[ADDR_PREFIX] != 0) | |
3138 | { | |
3139 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
3140 | i.prefixes -= 1; | |
3141 | } | |
3142 | /* Pentium4 branch hints. */ | |
3143 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
3144 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
3145 | { | |
3146 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
3147 | i.prefixes--; | |
3e73aa7c JH |
3148 | } |
3149 | } | |
29b0f896 AM |
3150 | else |
3151 | { | |
3152 | int code16; | |
3e73aa7c | 3153 | |
29b0f896 AM |
3154 | code16 = 0; |
3155 | if (flag_code == CODE_16BIT) | |
3156 | code16 = CODE16; | |
3e73aa7c | 3157 | |
29b0f896 AM |
3158 | if (i.prefix[DATA_PREFIX] != 0) |
3159 | { | |
3160 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
3161 | i.prefixes -= 1; | |
3162 | code16 ^= CODE16; | |
3163 | } | |
252b5132 | 3164 | |
29b0f896 AM |
3165 | size = 4; |
3166 | if (code16) | |
3167 | size = 2; | |
3168 | } | |
9fcc94b6 | 3169 | |
29b0f896 AM |
3170 | if (i.prefix[REX_PREFIX] != 0) |
3171 | { | |
3172 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
3173 | i.prefixes -= 1; | |
3174 | } | |
252b5132 | 3175 | |
29b0f896 AM |
3176 | if (i.prefixes != 0 && !intel_syntax) |
3177 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 3178 | |
29b0f896 AM |
3179 | p = frag_more (1 + size); |
3180 | *p++ = i.tm.base_opcode; | |
e0890092 | 3181 | |
3e02c1cc AM |
3182 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
3183 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); | |
3184 | ||
3185 | /* All jumps handled here are signed, but don't use a signed limit | |
3186 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
3187 | 4G and 64k respectively. */ | |
3188 | if (size == 1) | |
3189 | fixP->fx_signed = 1; | |
29b0f896 | 3190 | } |
e0890092 | 3191 | |
29b0f896 AM |
3192 | static void |
3193 | output_interseg_jump () | |
3194 | { | |
3195 | char *p; | |
3196 | int size; | |
3197 | int prefix; | |
3198 | int code16; | |
252b5132 | 3199 | |
29b0f896 AM |
3200 | code16 = 0; |
3201 | if (flag_code == CODE_16BIT) | |
3202 | code16 = CODE16; | |
a217f122 | 3203 | |
29b0f896 AM |
3204 | prefix = 0; |
3205 | if (i.prefix[DATA_PREFIX] != 0) | |
3206 | { | |
3207 | prefix = 1; | |
3208 | i.prefixes -= 1; | |
3209 | code16 ^= CODE16; | |
3210 | } | |
3211 | if (i.prefix[REX_PREFIX] != 0) | |
3212 | { | |
3213 | prefix++; | |
3214 | i.prefixes -= 1; | |
3215 | } | |
252b5132 | 3216 | |
29b0f896 AM |
3217 | size = 4; |
3218 | if (code16) | |
3219 | size = 2; | |
252b5132 | 3220 | |
29b0f896 AM |
3221 | if (i.prefixes != 0 && !intel_syntax) |
3222 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 3223 | |
29b0f896 AM |
3224 | /* 1 opcode; 2 segment; offset */ |
3225 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 3226 | |
29b0f896 AM |
3227 | if (i.prefix[DATA_PREFIX] != 0) |
3228 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 3229 | |
29b0f896 AM |
3230 | if (i.prefix[REX_PREFIX] != 0) |
3231 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 3232 | |
29b0f896 AM |
3233 | *p++ = i.tm.base_opcode; |
3234 | if (i.op[1].imms->X_op == O_constant) | |
3235 | { | |
3236 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 3237 | |
29b0f896 AM |
3238 | if (size == 2 |
3239 | && !fits_in_unsigned_word (n) | |
3240 | && !fits_in_signed_word (n)) | |
3241 | { | |
3242 | as_bad (_("16-bit jump out of range")); | |
3243 | return; | |
3244 | } | |
3245 | md_number_to_chars (p, n, size); | |
3246 | } | |
3247 | else | |
3248 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
3249 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); | |
3250 | if (i.op[0].imms->X_op != O_constant) | |
3251 | as_bad (_("can't handle non absolute segment in `%s'"), | |
3252 | i.tm.name); | |
3253 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
3254 | } | |
a217f122 | 3255 | |
29b0f896 AM |
3256 | static void |
3257 | output_insn () | |
3258 | { | |
2bbd9c25 JJ |
3259 | fragS *insn_start_frag; |
3260 | offsetT insn_start_off; | |
3261 | ||
29b0f896 AM |
3262 | /* Tie dwarf2 debug info to the address at the start of the insn. |
3263 | We can't do this after the insn has been output as the current | |
3264 | frag may have been closed off. eg. by frag_var. */ | |
3265 | dwarf2_emit_insn (0); | |
3266 | ||
2bbd9c25 JJ |
3267 | insn_start_frag = frag_now; |
3268 | insn_start_off = frag_now_fix (); | |
3269 | ||
29b0f896 AM |
3270 | /* Output jumps. */ |
3271 | if (i.tm.opcode_modifier & Jump) | |
3272 | output_branch (); | |
3273 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) | |
3274 | output_jump (); | |
3275 | else if (i.tm.opcode_modifier & JumpInterSegment) | |
3276 | output_interseg_jump (); | |
3277 | else | |
3278 | { | |
3279 | /* Output normal instructions here. */ | |
3280 | char *p; | |
3281 | unsigned char *q; | |
252b5132 | 3282 | |
0f10071e ML |
3283 | /* All opcodes on i386 have either 1 or 2 bytes, PadLock instructions |
3284 | have 3 bytes. We may use one more higher byte to specify a prefix | |
3285 | the instruction requires. */ | |
3286 | if ((i.tm.cpu_flags & CpuPadLock) != 0 | |
3287 | && (i.tm.base_opcode & 0xff000000) != 0) | |
3288 | { | |
3289 | unsigned int prefix; | |
3290 | prefix = (i.tm.base_opcode >> 24) & 0xff; | |
3291 | ||
3292 | if (prefix != REPE_PREFIX_OPCODE | |
3293 | || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE) | |
3294 | add_prefix (prefix); | |
3295 | } | |
3296 | else | |
3297 | if ((i.tm.cpu_flags & CpuPadLock) == 0 | |
3298 | && (i.tm.base_opcode & 0xff0000) != 0) | |
3299 | add_prefix ((i.tm.base_opcode >> 16) & 0xff); | |
252b5132 | 3300 | |
29b0f896 AM |
3301 | /* The prefix bytes. */ |
3302 | for (q = i.prefix; | |
3303 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); | |
3304 | q++) | |
3305 | { | |
3306 | if (*q) | |
3307 | { | |
3308 | p = frag_more (1); | |
3309 | md_number_to_chars (p, (valueT) *q, 1); | |
3310 | } | |
3311 | } | |
252b5132 | 3312 | |
29b0f896 AM |
3313 | /* Now the opcode; be careful about word order here! */ |
3314 | if (fits_in_unsigned_byte (i.tm.base_opcode)) | |
3315 | { | |
3316 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
3317 | } | |
3318 | else | |
3319 | { | |
0f10071e ML |
3320 | if ((i.tm.cpu_flags & CpuPadLock) != 0) |
3321 | { | |
3322 | p = frag_more (3); | |
3323 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
3324 | } | |
3325 | else | |
3326 | p = frag_more (2); | |
3327 | ||
29b0f896 AM |
3328 | /* Put out high byte first: can't use md_number_to_chars! */ |
3329 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
3330 | *p = i.tm.base_opcode & 0xff; | |
3331 | } | |
3e73aa7c | 3332 | |
29b0f896 AM |
3333 | /* Now the modrm byte and sib byte (if present). */ |
3334 | if (i.tm.opcode_modifier & Modrm) | |
3335 | { | |
3336 | p = frag_more (1); | |
3337 | md_number_to_chars (p, | |
3338 | (valueT) (i.rm.regmem << 0 | |
3339 | | i.rm.reg << 3 | |
3340 | | i.rm.mode << 6), | |
3341 | 1); | |
3342 | /* If i.rm.regmem == ESP (4) | |
3343 | && i.rm.mode != (Register mode) | |
3344 | && not 16 bit | |
3345 | ==> need second modrm byte. */ | |
3346 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
3347 | && i.rm.mode != 3 | |
3348 | && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) | |
3349 | { | |
3350 | p = frag_more (1); | |
3351 | md_number_to_chars (p, | |
3352 | (valueT) (i.sib.base << 0 | |
3353 | | i.sib.index << 3 | |
3354 | | i.sib.scale << 6), | |
3355 | 1); | |
3356 | } | |
3357 | } | |
3e73aa7c | 3358 | |
29b0f896 | 3359 | if (i.disp_operands) |
2bbd9c25 | 3360 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 3361 | |
29b0f896 | 3362 | if (i.imm_operands) |
2bbd9c25 | 3363 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 3364 | } |
252b5132 | 3365 | |
29b0f896 AM |
3366 | #ifdef DEBUG386 |
3367 | if (flag_debug) | |
3368 | { | |
3369 | pi (line, &i); | |
3370 | } | |
3371 | #endif /* DEBUG386 */ | |
3372 | } | |
252b5132 | 3373 | |
29b0f896 | 3374 | static void |
2bbd9c25 JJ |
3375 | output_disp (insn_start_frag, insn_start_off) |
3376 | fragS *insn_start_frag; | |
3377 | offsetT insn_start_off; | |
29b0f896 AM |
3378 | { |
3379 | char *p; | |
3380 | unsigned int n; | |
252b5132 | 3381 | |
29b0f896 AM |
3382 | for (n = 0; n < i.operands; n++) |
3383 | { | |
3384 | if (i.types[n] & Disp) | |
3385 | { | |
3386 | if (i.op[n].disps->X_op == O_constant) | |
3387 | { | |
3388 | int size; | |
3389 | offsetT val; | |
252b5132 | 3390 | |
29b0f896 AM |
3391 | size = 4; |
3392 | if (i.types[n] & (Disp8 | Disp16 | Disp64)) | |
3393 | { | |
3394 | size = 2; | |
3395 | if (i.types[n] & Disp8) | |
3396 | size = 1; | |
3397 | if (i.types[n] & Disp64) | |
3398 | size = 8; | |
3399 | } | |
3400 | val = offset_in_range (i.op[n].disps->X_add_number, | |
3401 | size); | |
3402 | p = frag_more (size); | |
3403 | md_number_to_chars (p, val, size); | |
3404 | } | |
3405 | else | |
3406 | { | |
f86103b7 | 3407 | enum bfd_reloc_code_real reloc_type; |
29b0f896 AM |
3408 | int size = 4; |
3409 | int sign = 0; | |
3410 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; | |
3411 | ||
3412 | /* The PC relative address is computed relative | |
3413 | to the instruction boundary, so in case immediate | |
3414 | fields follows, we need to adjust the value. */ | |
3415 | if (pcrel && i.imm_operands) | |
3416 | { | |
3417 | int imm_size = 4; | |
3418 | unsigned int n1; | |
252b5132 | 3419 | |
29b0f896 AM |
3420 | for (n1 = 0; n1 < i.operands; n1++) |
3421 | if (i.types[n1] & Imm) | |
252b5132 | 3422 | { |
29b0f896 | 3423 | if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64)) |
252b5132 | 3424 | { |
29b0f896 AM |
3425 | imm_size = 2; |
3426 | if (i.types[n1] & (Imm8 | Imm8S)) | |
3427 | imm_size = 1; | |
3428 | if (i.types[n1] & Imm64) | |
3429 | imm_size = 8; | |
252b5132 | 3430 | } |
29b0f896 | 3431 | break; |
252b5132 | 3432 | } |
29b0f896 AM |
3433 | /* We should find the immediate. */ |
3434 | if (n1 == i.operands) | |
3435 | abort (); | |
3436 | i.op[n].disps->X_add_number -= imm_size; | |
3437 | } | |
520dc8e8 | 3438 | |
29b0f896 AM |
3439 | if (i.types[n] & Disp32S) |
3440 | sign = 1; | |
3e73aa7c | 3441 | |
29b0f896 AM |
3442 | if (i.types[n] & (Disp16 | Disp64)) |
3443 | { | |
3444 | size = 2; | |
3445 | if (i.types[n] & Disp64) | |
3446 | size = 8; | |
3447 | } | |
520dc8e8 | 3448 | |
29b0f896 | 3449 | p = frag_more (size); |
2bbd9c25 | 3450 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
2bbd9c25 JJ |
3451 | if (reloc_type == BFD_RELOC_32 |
3452 | && GOT_symbol | |
3453 | && GOT_symbol == i.op[n].disps->X_add_symbol | |
3454 | && (i.op[n].disps->X_op == O_symbol | |
3455 | || (i.op[n].disps->X_op == O_add | |
3456 | && ((symbol_get_value_expression | |
3457 | (i.op[n].disps->X_op_symbol)->X_op) | |
3458 | == O_subtract)))) | |
3459 | { | |
3460 | offsetT add; | |
3461 | ||
3462 | if (insn_start_frag == frag_now) | |
3463 | add = (p - frag_now->fr_literal) - insn_start_off; | |
3464 | else | |
3465 | { | |
3466 | fragS *fr; | |
3467 | ||
3468 | add = insn_start_frag->fr_fix - insn_start_off; | |
3469 | for (fr = insn_start_frag->fr_next; | |
3470 | fr && fr != frag_now; fr = fr->fr_next) | |
3471 | add += fr->fr_fix; | |
3472 | add += p - frag_now->fr_literal; | |
3473 | } | |
3474 | ||
3475 | /* We don't support dynamic linking on x86-64 yet. */ | |
3476 | if (flag_code == CODE_64BIT) | |
3477 | abort (); | |
3478 | reloc_type = BFD_RELOC_386_GOTPC; | |
3479 | i.op[n].disps->X_add_number += add; | |
3480 | } | |
062cd5e7 | 3481 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
2bbd9c25 | 3482 | i.op[n].disps, pcrel, reloc_type); |
29b0f896 AM |
3483 | } |
3484 | } | |
3485 | } | |
3486 | } | |
252b5132 | 3487 | |
29b0f896 | 3488 | static void |
2bbd9c25 JJ |
3489 | output_imm (insn_start_frag, insn_start_off) |
3490 | fragS *insn_start_frag; | |
3491 | offsetT insn_start_off; | |
29b0f896 AM |
3492 | { |
3493 | char *p; | |
3494 | unsigned int n; | |
252b5132 | 3495 | |
29b0f896 AM |
3496 | for (n = 0; n < i.operands; n++) |
3497 | { | |
3498 | if (i.types[n] & Imm) | |
3499 | { | |
3500 | if (i.op[n].imms->X_op == O_constant) | |
3501 | { | |
3502 | int size; | |
3503 | offsetT val; | |
b4cac588 | 3504 | |
29b0f896 AM |
3505 | size = 4; |
3506 | if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) | |
3507 | { | |
3508 | size = 2; | |
3509 | if (i.types[n] & (Imm8 | Imm8S)) | |
3510 | size = 1; | |
3511 | else if (i.types[n] & Imm64) | |
3512 | size = 8; | |
3513 | } | |
3514 | val = offset_in_range (i.op[n].imms->X_add_number, | |
3515 | size); | |
3516 | p = frag_more (size); | |
3517 | md_number_to_chars (p, val, size); | |
3518 | } | |
3519 | else | |
3520 | { | |
3521 | /* Not absolute_section. | |
3522 | Need a 32-bit fixup (don't support 8bit | |
3523 | non-absolute imms). Try to support other | |
3524 | sizes ... */ | |
f86103b7 | 3525 | enum bfd_reloc_code_real reloc_type; |
29b0f896 AM |
3526 | int size = 4; |
3527 | int sign = 0; | |
3528 | ||
3529 | if ((i.types[n] & (Imm32S)) | |
3530 | && i.suffix == QWORD_MNEM_SUFFIX) | |
3531 | sign = 1; | |
3532 | if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) | |
3533 | { | |
3534 | size = 2; | |
3535 | if (i.types[n] & (Imm8 | Imm8S)) | |
3536 | size = 1; | |
3537 | if (i.types[n] & Imm64) | |
3538 | size = 8; | |
3539 | } | |
520dc8e8 | 3540 | |
29b0f896 AM |
3541 | p = frag_more (size); |
3542 | reloc_type = reloc (size, 0, sign, i.reloc[n]); | |
f86103b7 | 3543 | |
2bbd9c25 JJ |
3544 | /* This is tough to explain. We end up with this one if we |
3545 | * have operands that look like | |
3546 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
3547 | * obtain the absolute address of the GOT, and it is strongly | |
3548 | * preferable from a performance point of view to avoid using | |
3549 | * a runtime relocation for this. The actual sequence of | |
3550 | * instructions often look something like: | |
3551 | * | |
3552 | * call .L66 | |
3553 | * .L66: | |
3554 | * popl %ebx | |
3555 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
3556 | * | |
3557 | * The call and pop essentially return the absolute address | |
3558 | * of the label .L66 and store it in %ebx. The linker itself | |
3559 | * will ultimately change the first operand of the addl so | |
3560 | * that %ebx points to the GOT, but to keep things simple, the | |
3561 | * .o file must have this operand set so that it generates not | |
3562 | * the absolute address of .L66, but the absolute address of | |
3563 | * itself. This allows the linker itself simply treat a GOTPC | |
3564 | * relocation as asking for a pcrel offset to the GOT to be | |
3565 | * added in, and the addend of the relocation is stored in the | |
3566 | * operand field for the instruction itself. | |
3567 | * | |
3568 | * Our job here is to fix the operand so that it would add | |
3569 | * the correct offset so that %ebx would point to itself. The | |
3570 | * thing that is tricky is that .-.L66 will point to the | |
3571 | * beginning of the instruction, so we need to further modify | |
3572 | * the operand so that it will point to itself. There are | |
3573 | * other cases where you have something like: | |
3574 | * | |
3575 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
3576 | * | |
3577 | * and here no correction would be required. Internally in | |
3578 | * the assembler we treat operands of this form as not being | |
3579 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
3580 | * whether it would simplify matters to do it this way. Who | |
3581 | * knows. In earlier versions of the PIC patches, the | |
3582 | * pcrel_adjust field was used to store the correction, but | |
3583 | * since the expression is not pcrel, I felt it would be | |
3584 | * confusing to do it this way. */ | |
3585 | ||
29b0f896 AM |
3586 | if (reloc_type == BFD_RELOC_32 |
3587 | && GOT_symbol | |
3588 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
3589 | && (i.op[n].imms->X_op == O_symbol | |
3590 | || (i.op[n].imms->X_op == O_add | |
3591 | && ((symbol_get_value_expression | |
3592 | (i.op[n].imms->X_op_symbol)->X_op) | |
3593 | == O_subtract)))) | |
3594 | { | |
2bbd9c25 JJ |
3595 | offsetT add; |
3596 | ||
3597 | if (insn_start_frag == frag_now) | |
3598 | add = (p - frag_now->fr_literal) - insn_start_off; | |
3599 | else | |
3600 | { | |
3601 | fragS *fr; | |
3602 | ||
3603 | add = insn_start_frag->fr_fix - insn_start_off; | |
3604 | for (fr = insn_start_frag->fr_next; | |
3605 | fr && fr != frag_now; fr = fr->fr_next) | |
3606 | add += fr->fr_fix; | |
3607 | add += p - frag_now->fr_literal; | |
3608 | } | |
3609 | ||
29b0f896 AM |
3610 | /* We don't support dynamic linking on x86-64 yet. */ |
3611 | if (flag_code == CODE_64BIT) | |
3612 | abort (); | |
3613 | reloc_type = BFD_RELOC_386_GOTPC; | |
2bbd9c25 | 3614 | i.op[n].imms->X_add_number += add; |
29b0f896 | 3615 | } |
29b0f896 AM |
3616 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
3617 | i.op[n].imms, 0, reloc_type); | |
3618 | } | |
3619 | } | |
3620 | } | |
252b5132 RH |
3621 | } |
3622 | \f | |
f3c180ae | 3623 | #ifndef LEX_AT |
f86103b7 | 3624 | static char *lex_got PARAMS ((enum bfd_reloc_code_real *, int *)); |
f3c180ae AM |
3625 | |
3626 | /* Parse operands of the form | |
3627 | <symbol>@GOTOFF+<nnn> | |
3628 | and similar .plt or .got references. | |
3629 | ||
3630 | If we find one, set up the correct relocation in RELOC and copy the | |
3631 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
3632 | parsing by the calling routine. Return this buffer, and if ADJUST | |
3633 | is non-null set it to the length of the string we removed from the | |
3634 | input line. Otherwise return NULL. */ | |
3635 | static char * | |
3636 | lex_got (reloc, adjust) | |
f86103b7 | 3637 | enum bfd_reloc_code_real *reloc; |
f3c180ae AM |
3638 | int *adjust; |
3639 | { | |
3640 | static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" }; | |
3641 | static const struct { | |
3642 | const char *str; | |
f86103b7 | 3643 | const enum bfd_reloc_code_real rel[NUM_FLAG_CODE]; |
f3c180ae | 3644 | } gotrel[] = { |
13ae64f3 JJ |
3645 | { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } }, |
3646 | { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } }, | |
3647 | { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } }, | |
bffbf940 | 3648 | { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } }, |
13ae64f3 | 3649 | { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } }, |
bffbf940 JJ |
3650 | { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } }, |
3651 | { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } }, | |
3652 | { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } }, | |
13ae64f3 | 3653 | { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } }, |
bffbf940 | 3654 | { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } }, |
37e55690 JJ |
3655 | { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } }, |
3656 | { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } }, | |
13ae64f3 | 3657 | { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } } |
f3c180ae AM |
3658 | }; |
3659 | char *cp; | |
3660 | unsigned int j; | |
3661 | ||
3662 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
3663 | if (is_end_of_line[(unsigned char) *cp]) | |
3664 | return NULL; | |
3665 | ||
3666 | for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++) | |
3667 | { | |
3668 | int len; | |
3669 | ||
3670 | len = strlen (gotrel[j].str); | |
28f81592 | 3671 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae AM |
3672 | { |
3673 | if (gotrel[j].rel[(unsigned int) flag_code] != 0) | |
3674 | { | |
28f81592 AM |
3675 | int first, second; |
3676 | char *tmpbuf, *past_reloc; | |
f3c180ae AM |
3677 | |
3678 | *reloc = gotrel[j].rel[(unsigned int) flag_code]; | |
28f81592 AM |
3679 | if (adjust) |
3680 | *adjust = len; | |
f3c180ae AM |
3681 | |
3682 | if (GOT_symbol == NULL) | |
3683 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
3684 | ||
3685 | /* Replace the relocation token with ' ', so that | |
3686 | errors like foo@GOTOFF1 will be detected. */ | |
28f81592 AM |
3687 | |
3688 | /* The length of the first part of our input line. */ | |
f3c180ae | 3689 | first = cp - input_line_pointer; |
28f81592 AM |
3690 | |
3691 | /* The second part goes from after the reloc token until | |
3692 | (and including) an end_of_line char. Don't use strlen | |
3693 | here as the end_of_line char may not be a NUL. */ | |
3694 | past_reloc = cp + 1 + len; | |
3695 | for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; ) | |
3696 | ; | |
3697 | second = cp - past_reloc; | |
3698 | ||
3699 | /* Allocate and copy string. The trailing NUL shouldn't | |
3700 | be necessary, but be safe. */ | |
3701 | tmpbuf = xmalloc (first + second + 2); | |
f3c180ae AM |
3702 | memcpy (tmpbuf, input_line_pointer, first); |
3703 | tmpbuf[first] = ' '; | |
28f81592 AM |
3704 | memcpy (tmpbuf + first + 1, past_reloc, second); |
3705 | tmpbuf[first + second + 1] = '\0'; | |
f3c180ae AM |
3706 | return tmpbuf; |
3707 | } | |
3708 | ||
3709 | as_bad (_("@%s reloc is not supported in %s bit mode"), | |
3710 | gotrel[j].str, mode_name[(unsigned int) flag_code]); | |
3711 | return NULL; | |
3712 | } | |
3713 | } | |
3714 | ||
3715 | /* Might be a symbol version string. Don't as_bad here. */ | |
3716 | return NULL; | |
3717 | } | |
3718 | ||
3719 | /* x86_cons_fix_new is called via the expression parsing code when a | |
3720 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
f86103b7 | 3721 | static enum bfd_reloc_code_real got_reloc = NO_RELOC; |
f3c180ae AM |
3722 | |
3723 | void | |
3724 | x86_cons_fix_new (frag, off, len, exp) | |
3725 | fragS *frag; | |
3726 | unsigned int off; | |
3727 | unsigned int len; | |
3728 | expressionS *exp; | |
3729 | { | |
f86103b7 | 3730 | enum bfd_reloc_code_real r = reloc (len, 0, 0, got_reloc); |
f3c180ae AM |
3731 | got_reloc = NO_RELOC; |
3732 | fix_new_exp (frag, off, len, exp, 0, r); | |
3733 | } | |
3734 | ||
3735 | void | |
3736 | x86_cons (exp, size) | |
3737 | expressionS *exp; | |
3738 | int size; | |
3739 | { | |
3740 | if (size == 4) | |
3741 | { | |
3742 | /* Handle @GOTOFF and the like in an expression. */ | |
3743 | char *save; | |
3744 | char *gotfree_input_line; | |
3745 | int adjust; | |
3746 | ||
3747 | save = input_line_pointer; | |
3748 | gotfree_input_line = lex_got (&got_reloc, &adjust); | |
3749 | if (gotfree_input_line) | |
3750 | input_line_pointer = gotfree_input_line; | |
3751 | ||
3752 | expression (exp); | |
3753 | ||
3754 | if (gotfree_input_line) | |
3755 | { | |
3756 | /* expression () has merrily parsed up to the end of line, | |
3757 | or a comma - in the wrong buffer. Transfer how far | |
3758 | input_line_pointer has moved to the right buffer. */ | |
3759 | input_line_pointer = (save | |
3760 | + (input_line_pointer - gotfree_input_line) | |
3761 | + adjust); | |
3762 | free (gotfree_input_line); | |
3763 | } | |
3764 | } | |
3765 | else | |
3766 | expression (exp); | |
3767 | } | |
3768 | #endif | |
3769 | ||
6482c264 NC |
3770 | #ifdef TE_PE |
3771 | ||
6482c264 NC |
3772 | void |
3773 | x86_pe_cons_fix_new (frag, off, len, exp) | |
3774 | fragS *frag; | |
3775 | unsigned int off; | |
3776 | unsigned int len; | |
3777 | expressionS *exp; | |
3778 | { | |
3779 | enum bfd_reloc_code_real r = reloc (len, 0, 0, NO_RELOC); | |
3780 | ||
3781 | if (exp->X_op == O_secrel) | |
3782 | { | |
3783 | exp->X_op = O_symbol; | |
3784 | r = BFD_RELOC_32_SECREL; | |
3785 | } | |
3786 | ||
3787 | fix_new_exp (frag, off, len, exp, 0, r); | |
3788 | } | |
3789 | ||
3790 | static void | |
3791 | pe_directive_secrel (dummy) | |
3792 | int dummy ATTRIBUTE_UNUSED; | |
3793 | { | |
3794 | expressionS exp; | |
3795 | ||
3796 | do | |
3797 | { | |
3798 | expression (&exp); | |
3799 | if (exp.X_op == O_symbol) | |
3800 | exp.X_op = O_secrel; | |
3801 | ||
3802 | emit_expr (&exp, 4); | |
3803 | } | |
3804 | while (*input_line_pointer++ == ','); | |
3805 | ||
3806 | input_line_pointer--; | |
3807 | demand_empty_rest_of_line (); | |
3808 | } | |
3809 | ||
3810 | #endif | |
3811 | ||
252b5132 RH |
3812 | static int i386_immediate PARAMS ((char *)); |
3813 | ||
3814 | static int | |
3815 | i386_immediate (imm_start) | |
3816 | char *imm_start; | |
3817 | { | |
3818 | char *save_input_line_pointer; | |
f3c180ae AM |
3819 | #ifndef LEX_AT |
3820 | char *gotfree_input_line; | |
3821 | #endif | |
252b5132 | 3822 | segT exp_seg = 0; |
47926f60 | 3823 | expressionS *exp; |
252b5132 RH |
3824 | |
3825 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
3826 | { | |
d0b47220 | 3827 | as_bad (_("only 1 or 2 immediate operands are allowed")); |
252b5132 RH |
3828 | return 0; |
3829 | } | |
3830 | ||
3831 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 3832 | i.op[this_operand].imms = exp; |
252b5132 RH |
3833 | |
3834 | if (is_space_char (*imm_start)) | |
3835 | ++imm_start; | |
3836 | ||
3837 | save_input_line_pointer = input_line_pointer; | |
3838 | input_line_pointer = imm_start; | |
3839 | ||
3840 | #ifndef LEX_AT | |
f3c180ae AM |
3841 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); |
3842 | if (gotfree_input_line) | |
3843 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
3844 | #endif |
3845 | ||
3846 | exp_seg = expression (exp); | |
3847 | ||
83183c0c | 3848 | SKIP_WHITESPACE (); |
252b5132 | 3849 | if (*input_line_pointer) |
f3c180ae | 3850 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
3851 | |
3852 | input_line_pointer = save_input_line_pointer; | |
f3c180ae AM |
3853 | #ifndef LEX_AT |
3854 | if (gotfree_input_line) | |
3855 | free (gotfree_input_line); | |
3856 | #endif | |
252b5132 | 3857 | |
2daf4fd8 | 3858 | if (exp->X_op == O_absent || exp->X_op == O_big) |
252b5132 | 3859 | { |
47926f60 | 3860 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 3861 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
24eab124 | 3862 | imm_start); |
252b5132 RH |
3863 | exp->X_op = O_constant; |
3864 | exp->X_add_number = 0; | |
3865 | exp->X_add_symbol = (symbolS *) 0; | |
3866 | exp->X_op_symbol = (symbolS *) 0; | |
252b5132 | 3867 | } |
3e73aa7c | 3868 | else if (exp->X_op == O_constant) |
252b5132 | 3869 | { |
47926f60 | 3870 | /* Size it properly later. */ |
3e73aa7c JH |
3871 | i.types[this_operand] |= Imm64; |
3872 | /* If BFD64, sign extend val. */ | |
3873 | if (!use_rela_relocations) | |
3874 | if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) | |
3875 | exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 3876 | } |
4c63da97 | 3877 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 3878 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 3879 | && exp_seg != absolute_section |
47926f60 | 3880 | && exp_seg != text_section |
24eab124 AM |
3881 | && exp_seg != data_section |
3882 | && exp_seg != bss_section | |
3883 | && exp_seg != undefined_section | |
f86103b7 | 3884 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 3885 | { |
d0b47220 | 3886 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
3887 | return 0; |
3888 | } | |
3889 | #endif | |
3890 | else | |
3891 | { | |
3892 | /* This is an address. The size of the address will be | |
24eab124 | 3893 | determined later, depending on destination register, |
3e73aa7c JH |
3894 | suffix, or the default for the section. */ |
3895 | i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64; | |
252b5132 RH |
3896 | } |
3897 | ||
3898 | return 1; | |
3899 | } | |
3900 | ||
551c1ca1 | 3901 | static char *i386_scale PARAMS ((char *)); |
252b5132 | 3902 | |
551c1ca1 | 3903 | static char * |
252b5132 RH |
3904 | i386_scale (scale) |
3905 | char *scale; | |
3906 | { | |
551c1ca1 AM |
3907 | offsetT val; |
3908 | char *save = input_line_pointer; | |
252b5132 | 3909 | |
551c1ca1 AM |
3910 | input_line_pointer = scale; |
3911 | val = get_absolute_expression (); | |
3912 | ||
3913 | switch (val) | |
252b5132 | 3914 | { |
551c1ca1 AM |
3915 | case 0: |
3916 | case 1: | |
252b5132 RH |
3917 | i.log2_scale_factor = 0; |
3918 | break; | |
551c1ca1 | 3919 | case 2: |
252b5132 RH |
3920 | i.log2_scale_factor = 1; |
3921 | break; | |
551c1ca1 | 3922 | case 4: |
252b5132 RH |
3923 | i.log2_scale_factor = 2; |
3924 | break; | |
551c1ca1 | 3925 | case 8: |
252b5132 RH |
3926 | i.log2_scale_factor = 3; |
3927 | break; | |
3928 | default: | |
252b5132 | 3929 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), |
24eab124 | 3930 | scale); |
551c1ca1 AM |
3931 | input_line_pointer = save; |
3932 | return NULL; | |
252b5132 | 3933 | } |
29b0f896 | 3934 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
3935 | { |
3936 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 3937 | 1 << i.log2_scale_factor); |
252b5132 RH |
3938 | #if SCALE1_WHEN_NO_INDEX |
3939 | i.log2_scale_factor = 0; | |
3940 | #endif | |
3941 | } | |
551c1ca1 AM |
3942 | scale = input_line_pointer; |
3943 | input_line_pointer = save; | |
3944 | return scale; | |
252b5132 RH |
3945 | } |
3946 | ||
3947 | static int i386_displacement PARAMS ((char *, char *)); | |
3948 | ||
3949 | static int | |
3950 | i386_displacement (disp_start, disp_end) | |
3951 | char *disp_start; | |
3952 | char *disp_end; | |
3953 | { | |
29b0f896 | 3954 | expressionS *exp; |
252b5132 RH |
3955 | segT exp_seg = 0; |
3956 | char *save_input_line_pointer; | |
f3c180ae AM |
3957 | #ifndef LEX_AT |
3958 | char *gotfree_input_line; | |
3959 | #endif | |
252b5132 RH |
3960 | int bigdisp = Disp32; |
3961 | ||
3e73aa7c | 3962 | if (flag_code == CODE_64BIT) |
7ecd2f8b | 3963 | { |
29b0f896 AM |
3964 | if (i.prefix[ADDR_PREFIX] == 0) |
3965 | bigdisp = Disp64; | |
7ecd2f8b JH |
3966 | } |
3967 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
3968 | bigdisp = Disp16; | |
252b5132 RH |
3969 | i.types[this_operand] |= bigdisp; |
3970 | ||
3971 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 3972 | i.op[this_operand].disps = exp; |
252b5132 RH |
3973 | i.disp_operands++; |
3974 | save_input_line_pointer = input_line_pointer; | |
3975 | input_line_pointer = disp_start; | |
3976 | END_STRING_AND_SAVE (disp_end); | |
3977 | ||
3978 | #ifndef GCC_ASM_O_HACK | |
3979 | #define GCC_ASM_O_HACK 0 | |
3980 | #endif | |
3981 | #if GCC_ASM_O_HACK | |
3982 | END_STRING_AND_SAVE (disp_end + 1); | |
3983 | if ((i.types[this_operand] & BaseIndex) != 0 | |
24eab124 | 3984 | && displacement_string_end[-1] == '+') |
252b5132 RH |
3985 | { |
3986 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
3987 | constraint within gcc asm statements. |
3988 | For instance: | |
3989 | ||
3990 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
3991 | __asm__ __volatile__ ( \ | |
3992 | "movw %w2,%0\n\t" \ | |
3993 | "movw %w1,2+%0\n\t" \ | |
3994 | "rorl $16,%1\n\t" \ | |
3995 | "movb %b1,4+%0\n\t" \ | |
3996 | "movb %4,5+%0\n\t" \ | |
3997 | "movb $0,6+%0\n\t" \ | |
3998 | "movb %h1,7+%0\n\t" \ | |
3999 | "rorl $16,%1" \ | |
4000 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
4001 | ||
4002 | This works great except that the output assembler ends | |
4003 | up looking a bit weird if it turns out that there is | |
4004 | no offset. You end up producing code that looks like: | |
4005 | ||
4006 | #APP | |
4007 | movw $235,(%eax) | |
4008 | movw %dx,2+(%eax) | |
4009 | rorl $16,%edx | |
4010 | movb %dl,4+(%eax) | |
4011 | movb $137,5+(%eax) | |
4012 | movb $0,6+(%eax) | |
4013 | movb %dh,7+(%eax) | |
4014 | rorl $16,%edx | |
4015 | #NO_APP | |
4016 | ||
47926f60 | 4017 | So here we provide the missing zero. */ |
24eab124 AM |
4018 | |
4019 | *displacement_string_end = '0'; | |
252b5132 RH |
4020 | } |
4021 | #endif | |
4022 | #ifndef LEX_AT | |
f3c180ae AM |
4023 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); |
4024 | if (gotfree_input_line) | |
4025 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
4026 | #endif |
4027 | ||
24eab124 | 4028 | exp_seg = expression (exp); |
252b5132 | 4029 | |
636c26b0 AM |
4030 | SKIP_WHITESPACE (); |
4031 | if (*input_line_pointer) | |
4032 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
4033 | #if GCC_ASM_O_HACK | |
4034 | RESTORE_END_STRING (disp_end + 1); | |
4035 | #endif | |
4036 | RESTORE_END_STRING (disp_end); | |
4037 | input_line_pointer = save_input_line_pointer; | |
4038 | #ifndef LEX_AT | |
4039 | if (gotfree_input_line) | |
4040 | free (gotfree_input_line); | |
4041 | #endif | |
4042 | ||
24eab124 AM |
4043 | /* We do this to make sure that the section symbol is in |
4044 | the symbol table. We will ultimately change the relocation | |
47926f60 | 4045 | to be relative to the beginning of the section. */ |
1ae12ab7 AM |
4046 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
4047 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) | |
24eab124 | 4048 | { |
636c26b0 AM |
4049 | if (exp->X_op != O_symbol) |
4050 | { | |
4051 | as_bad (_("bad expression used with @%s"), | |
4052 | (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL | |
4053 | ? "GOTPCREL" | |
4054 | : "GOTOFF")); | |
4055 | return 0; | |
4056 | } | |
4057 | ||
e5cb08ac | 4058 | if (S_IS_LOCAL (exp->X_add_symbol) |
24eab124 AM |
4059 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) |
4060 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
24eab124 AM |
4061 | exp->X_op = O_subtract; |
4062 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 4063 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 4064 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
23df1078 | 4065 | else |
29b0f896 | 4066 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 4067 | } |
252b5132 | 4068 | |
2daf4fd8 AM |
4069 | if (exp->X_op == O_absent || exp->X_op == O_big) |
4070 | { | |
47926f60 | 4071 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 4072 | as_bad (_("missing or invalid displacement expression `%s' taken as 0"), |
2daf4fd8 AM |
4073 | disp_start); |
4074 | exp->X_op = O_constant; | |
4075 | exp->X_add_number = 0; | |
4076 | exp->X_add_symbol = (symbolS *) 0; | |
4077 | exp->X_op_symbol = (symbolS *) 0; | |
4078 | } | |
4079 | ||
4c63da97 | 4080 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
45288df1 | 4081 | if (exp->X_op != O_constant |
45288df1 | 4082 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 4083 | && exp_seg != absolute_section |
45288df1 AM |
4084 | && exp_seg != text_section |
4085 | && exp_seg != data_section | |
4086 | && exp_seg != bss_section | |
31312f95 | 4087 | && exp_seg != undefined_section |
f86103b7 | 4088 | && !bfd_is_com_section (exp_seg)) |
24eab124 | 4089 | { |
d0b47220 | 4090 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
24eab124 AM |
4091 | return 0; |
4092 | } | |
252b5132 | 4093 | #endif |
3e73aa7c JH |
4094 | else if (flag_code == CODE_64BIT) |
4095 | i.types[this_operand] |= Disp32S | Disp32; | |
252b5132 RH |
4096 | return 1; |
4097 | } | |
4098 | ||
e5cb08ac | 4099 | static int i386_index_check PARAMS ((const char *)); |
252b5132 | 4100 | |
eecb386c | 4101 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
4102 | Return 1 on success, 0 on a failure. */ |
4103 | ||
252b5132 | 4104 | static int |
eecb386c AM |
4105 | i386_index_check (operand_string) |
4106 | const char *operand_string; | |
252b5132 | 4107 | { |
3e73aa7c | 4108 | int ok; |
24eab124 | 4109 | #if INFER_ADDR_PREFIX |
eecb386c AM |
4110 | int fudged = 0; |
4111 | ||
24eab124 AM |
4112 | tryprefix: |
4113 | #endif | |
3e73aa7c | 4114 | ok = 1; |
20f0a1fc NC |
4115 | if (flag_code == CODE_64BIT) |
4116 | { | |
4117 | unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32); | |
4118 | ||
4119 | if ((i.base_reg | |
4120 | && ((i.base_reg->reg_type & RegXX) == 0) | |
4121 | && (i.base_reg->reg_type != BaseIndex | |
4122 | || i.index_reg)) | |
4123 | || (i.index_reg | |
4124 | && ((i.index_reg->reg_type & (RegXX | BaseIndex)) | |
4125 | != (RegXX | BaseIndex)))) | |
4126 | ok = 0; | |
3e73aa7c JH |
4127 | } |
4128 | else | |
4129 | { | |
4130 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
4131 | { | |
4132 | /* 16bit checks. */ | |
4133 | if ((i.base_reg | |
29b0f896 AM |
4134 | && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex)) |
4135 | != (Reg16 | BaseIndex))) | |
3e73aa7c | 4136 | || (i.index_reg |
29b0f896 AM |
4137 | && (((i.index_reg->reg_type & (Reg16 | BaseIndex)) |
4138 | != (Reg16 | BaseIndex)) | |
4139 | || !(i.base_reg | |
4140 | && i.base_reg->reg_num < 6 | |
4141 | && i.index_reg->reg_num >= 6 | |
4142 | && i.log2_scale_factor == 0)))) | |
3e73aa7c JH |
4143 | ok = 0; |
4144 | } | |
4145 | else | |
e5cb08ac | 4146 | { |
3e73aa7c JH |
4147 | /* 32bit checks. */ |
4148 | if ((i.base_reg | |
4149 | && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32) | |
4150 | || (i.index_reg | |
29b0f896 AM |
4151 | && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex)) |
4152 | != (Reg32 | BaseIndex)))) | |
e5cb08ac | 4153 | ok = 0; |
3e73aa7c JH |
4154 | } |
4155 | } | |
4156 | if (!ok) | |
24eab124 AM |
4157 | { |
4158 | #if INFER_ADDR_PREFIX | |
20f0a1fc | 4159 | if (i.prefix[ADDR_PREFIX] == 0) |
24eab124 AM |
4160 | { |
4161 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
4162 | i.prefixes += 1; | |
b23bac36 AM |
4163 | /* Change the size of any displacement too. At most one of |
4164 | Disp16 or Disp32 is set. | |
4165 | FIXME. There doesn't seem to be any real need for separate | |
4166 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 4167 | Removing them would probably clean up the code quite a lot. */ |
20f0a1fc | 4168 | if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32))) |
29b0f896 | 4169 | i.types[this_operand] ^= (Disp16 | Disp32); |
eecb386c | 4170 | fudged = 1; |
24eab124 AM |
4171 | goto tryprefix; |
4172 | } | |
eecb386c AM |
4173 | if (fudged) |
4174 | as_bad (_("`%s' is not a valid base/index expression"), | |
4175 | operand_string); | |
4176 | else | |
c388dee8 | 4177 | #endif |
eecb386c AM |
4178 | as_bad (_("`%s' is not a valid %s bit base/index expression"), |
4179 | operand_string, | |
3e73aa7c | 4180 | flag_code_names[flag_code]); |
24eab124 | 4181 | } |
20f0a1fc | 4182 | return ok; |
24eab124 | 4183 | } |
252b5132 | 4184 | |
252b5132 | 4185 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero |
47926f60 | 4186 | on error. */ |
252b5132 | 4187 | |
252b5132 RH |
4188 | static int |
4189 | i386_operand (operand_string) | |
4190 | char *operand_string; | |
4191 | { | |
af6bdddf AM |
4192 | const reg_entry *r; |
4193 | char *end_op; | |
24eab124 | 4194 | char *op_string = operand_string; |
252b5132 | 4195 | |
24eab124 | 4196 | if (is_space_char (*op_string)) |
252b5132 RH |
4197 | ++op_string; |
4198 | ||
24eab124 | 4199 | /* We check for an absolute prefix (differentiating, |
47926f60 | 4200 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
4201 | if (*op_string == ABSOLUTE_PREFIX) |
4202 | { | |
4203 | ++op_string; | |
4204 | if (is_space_char (*op_string)) | |
4205 | ++op_string; | |
4206 | i.types[this_operand] |= JumpAbsolute; | |
4207 | } | |
252b5132 | 4208 | |
47926f60 | 4209 | /* Check if operand is a register. */ |
af6bdddf AM |
4210 | if ((*op_string == REGISTER_PREFIX || allow_naked_reg) |
4211 | && (r = parse_register (op_string, &end_op)) != NULL) | |
24eab124 | 4212 | { |
24eab124 AM |
4213 | /* Check for a segment override by searching for ':' after a |
4214 | segment register. */ | |
4215 | op_string = end_op; | |
4216 | if (is_space_char (*op_string)) | |
4217 | ++op_string; | |
4218 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
4219 | { | |
4220 | switch (r->reg_num) | |
4221 | { | |
4222 | case 0: | |
4223 | i.seg[i.mem_operands] = &es; | |
4224 | break; | |
4225 | case 1: | |
4226 | i.seg[i.mem_operands] = &cs; | |
4227 | break; | |
4228 | case 2: | |
4229 | i.seg[i.mem_operands] = &ss; | |
4230 | break; | |
4231 | case 3: | |
4232 | i.seg[i.mem_operands] = &ds; | |
4233 | break; | |
4234 | case 4: | |
4235 | i.seg[i.mem_operands] = &fs; | |
4236 | break; | |
4237 | case 5: | |
4238 | i.seg[i.mem_operands] = &gs; | |
4239 | break; | |
4240 | } | |
252b5132 | 4241 | |
24eab124 | 4242 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
4243 | ++op_string; |
4244 | if (is_space_char (*op_string)) | |
24eab124 | 4245 | ++op_string; |
252b5132 | 4246 | |
24eab124 AM |
4247 | if (!is_digit_char (*op_string) |
4248 | && !is_identifier_char (*op_string) | |
4249 | && *op_string != '(' | |
4250 | && *op_string != ABSOLUTE_PREFIX) | |
4251 | { | |
4252 | as_bad (_("bad memory operand `%s'"), op_string); | |
4253 | return 0; | |
4254 | } | |
47926f60 | 4255 | /* Handle case of %es:*foo. */ |
24eab124 AM |
4256 | if (*op_string == ABSOLUTE_PREFIX) |
4257 | { | |
4258 | ++op_string; | |
4259 | if (is_space_char (*op_string)) | |
4260 | ++op_string; | |
4261 | i.types[this_operand] |= JumpAbsolute; | |
4262 | } | |
4263 | goto do_memory_reference; | |
4264 | } | |
4265 | if (*op_string) | |
4266 | { | |
d0b47220 | 4267 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
4268 | return 0; |
4269 | } | |
4270 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
520dc8e8 | 4271 | i.op[this_operand].regs = r; |
24eab124 AM |
4272 | i.reg_operands++; |
4273 | } | |
af6bdddf AM |
4274 | else if (*op_string == REGISTER_PREFIX) |
4275 | { | |
4276 | as_bad (_("bad register name `%s'"), op_string); | |
4277 | return 0; | |
4278 | } | |
24eab124 | 4279 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 4280 | { |
24eab124 AM |
4281 | ++op_string; |
4282 | if (i.types[this_operand] & JumpAbsolute) | |
4283 | { | |
d0b47220 | 4284 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
4285 | return 0; |
4286 | } | |
4287 | if (!i386_immediate (op_string)) | |
4288 | return 0; | |
4289 | } | |
4290 | else if (is_digit_char (*op_string) | |
4291 | || is_identifier_char (*op_string) | |
e5cb08ac | 4292 | || *op_string == '(') |
24eab124 | 4293 | { |
47926f60 | 4294 | /* This is a memory reference of some sort. */ |
af6bdddf | 4295 | char *base_string; |
252b5132 | 4296 | |
47926f60 | 4297 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
4298 | char *displacement_string_start; |
4299 | char *displacement_string_end; | |
252b5132 | 4300 | |
24eab124 | 4301 | do_memory_reference: |
24eab124 AM |
4302 | if ((i.mem_operands == 1 |
4303 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
4304 | || i.mem_operands == 2) | |
4305 | { | |
4306 | as_bad (_("too many memory references for `%s'"), | |
4307 | current_templates->start->name); | |
4308 | return 0; | |
4309 | } | |
252b5132 | 4310 | |
24eab124 AM |
4311 | /* Check for base index form. We detect the base index form by |
4312 | looking for an ')' at the end of the operand, searching | |
4313 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
4314 | after the '('. */ | |
af6bdddf | 4315 | base_string = op_string + strlen (op_string); |
c3332e24 | 4316 | |
af6bdddf AM |
4317 | --base_string; |
4318 | if (is_space_char (*base_string)) | |
4319 | --base_string; | |
252b5132 | 4320 | |
47926f60 | 4321 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
4322 | displacement_string_start = op_string; |
4323 | displacement_string_end = base_string + 1; | |
252b5132 | 4324 | |
24eab124 AM |
4325 | if (*base_string == ')') |
4326 | { | |
af6bdddf | 4327 | char *temp_string; |
24eab124 AM |
4328 | unsigned int parens_balanced = 1; |
4329 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 4330 | equal, so this loop will not be infinite. */ |
24eab124 AM |
4331 | do |
4332 | { | |
4333 | base_string--; | |
4334 | if (*base_string == ')') | |
4335 | parens_balanced++; | |
4336 | if (*base_string == '(') | |
4337 | parens_balanced--; | |
4338 | } | |
4339 | while (parens_balanced); | |
c3332e24 | 4340 | |
af6bdddf | 4341 | temp_string = base_string; |
c3332e24 | 4342 | |
24eab124 | 4343 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
4344 | ++base_string; |
4345 | if (is_space_char (*base_string)) | |
24eab124 | 4346 | ++base_string; |
252b5132 | 4347 | |
af6bdddf AM |
4348 | if (*base_string == ',' |
4349 | || ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
4350 | && (i.base_reg = parse_register (base_string, &end_op)) != NULL)) | |
252b5132 | 4351 | { |
af6bdddf | 4352 | displacement_string_end = temp_string; |
252b5132 | 4353 | |
af6bdddf | 4354 | i.types[this_operand] |= BaseIndex; |
252b5132 | 4355 | |
af6bdddf | 4356 | if (i.base_reg) |
24eab124 | 4357 | { |
24eab124 AM |
4358 | base_string = end_op; |
4359 | if (is_space_char (*base_string)) | |
4360 | ++base_string; | |
af6bdddf AM |
4361 | } |
4362 | ||
4363 | /* There may be an index reg or scale factor here. */ | |
4364 | if (*base_string == ',') | |
4365 | { | |
4366 | ++base_string; | |
4367 | if (is_space_char (*base_string)) | |
4368 | ++base_string; | |
4369 | ||
4370 | if ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
4371 | && (i.index_reg = parse_register (base_string, &end_op)) != NULL) | |
24eab124 | 4372 | { |
af6bdddf | 4373 | base_string = end_op; |
24eab124 AM |
4374 | if (is_space_char (*base_string)) |
4375 | ++base_string; | |
af6bdddf AM |
4376 | if (*base_string == ',') |
4377 | { | |
4378 | ++base_string; | |
4379 | if (is_space_char (*base_string)) | |
4380 | ++base_string; | |
4381 | } | |
e5cb08ac | 4382 | else if (*base_string != ')') |
af6bdddf AM |
4383 | { |
4384 | as_bad (_("expecting `,' or `)' after index register in `%s'"), | |
4385 | operand_string); | |
4386 | return 0; | |
4387 | } | |
24eab124 | 4388 | } |
af6bdddf | 4389 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 4390 | { |
af6bdddf | 4391 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
4392 | return 0; |
4393 | } | |
252b5132 | 4394 | |
47926f60 | 4395 | /* Check for scale factor. */ |
551c1ca1 | 4396 | if (*base_string != ')') |
af6bdddf | 4397 | { |
551c1ca1 AM |
4398 | char *end_scale = i386_scale (base_string); |
4399 | ||
4400 | if (!end_scale) | |
af6bdddf | 4401 | return 0; |
24eab124 | 4402 | |
551c1ca1 | 4403 | base_string = end_scale; |
af6bdddf AM |
4404 | if (is_space_char (*base_string)) |
4405 | ++base_string; | |
4406 | if (*base_string != ')') | |
4407 | { | |
4408 | as_bad (_("expecting `)' after scale factor in `%s'"), | |
4409 | operand_string); | |
4410 | return 0; | |
4411 | } | |
4412 | } | |
4413 | else if (!i.index_reg) | |
24eab124 | 4414 | { |
af6bdddf AM |
4415 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
4416 | *base_string); | |
24eab124 AM |
4417 | return 0; |
4418 | } | |
4419 | } | |
af6bdddf | 4420 | else if (*base_string != ')') |
24eab124 | 4421 | { |
af6bdddf AM |
4422 | as_bad (_("expecting `,' or `)' after base register in `%s'"), |
4423 | operand_string); | |
24eab124 AM |
4424 | return 0; |
4425 | } | |
c3332e24 | 4426 | } |
af6bdddf | 4427 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 4428 | { |
af6bdddf | 4429 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 4430 | return 0; |
c3332e24 | 4431 | } |
24eab124 AM |
4432 | } |
4433 | ||
4434 | /* If there's an expression beginning the operand, parse it, | |
4435 | assuming displacement_string_start and | |
4436 | displacement_string_end are meaningful. */ | |
4437 | if (displacement_string_start != displacement_string_end) | |
4438 | { | |
4439 | if (!i386_displacement (displacement_string_start, | |
4440 | displacement_string_end)) | |
4441 | return 0; | |
4442 | } | |
4443 | ||
4444 | /* Special case for (%dx) while doing input/output op. */ | |
4445 | if (i.base_reg | |
4446 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) | |
4447 | && i.index_reg == 0 | |
4448 | && i.log2_scale_factor == 0 | |
4449 | && i.seg[i.mem_operands] == 0 | |
4450 | && (i.types[this_operand] & Disp) == 0) | |
4451 | { | |
4452 | i.types[this_operand] = InOutPortReg; | |
4453 | return 1; | |
4454 | } | |
4455 | ||
eecb386c AM |
4456 | if (i386_index_check (operand_string) == 0) |
4457 | return 0; | |
24eab124 AM |
4458 | i.mem_operands++; |
4459 | } | |
4460 | else | |
ce8a8b2f AM |
4461 | { |
4462 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
4463 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
4464 | output_invalid (*op_string), | |
4465 | this_operand + 1, | |
4466 | op_string); | |
4467 | return 0; | |
4468 | } | |
47926f60 | 4469 | return 1; /* Normal return. */ |
252b5132 RH |
4470 | } |
4471 | \f | |
ee7fcc42 AM |
4472 | /* md_estimate_size_before_relax() |
4473 | ||
4474 | Called just before relax() for rs_machine_dependent frags. The x86 | |
4475 | assembler uses these frags to handle variable size jump | |
4476 | instructions. | |
4477 | ||
4478 | Any symbol that is now undefined will not become defined. | |
4479 | Return the correct fr_subtype in the frag. | |
4480 | Return the initial "guess for variable size of frag" to caller. | |
4481 | The guess is actually the growth beyond the fixed part. Whatever | |
4482 | we do to grow the fixed or variable part contributes to our | |
4483 | returned value. */ | |
4484 | ||
252b5132 RH |
4485 | int |
4486 | md_estimate_size_before_relax (fragP, segment) | |
29b0f896 AM |
4487 | fragS *fragP; |
4488 | segT segment; | |
252b5132 | 4489 | { |
252b5132 | 4490 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
4491 | check for un-relaxable symbols. On an ELF system, we can't relax |
4492 | an externally visible symbol, because it may be overridden by a | |
4493 | shared library. */ | |
4494 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 4495 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
31312f95 AM |
4496 | || (OUTPUT_FLAVOR == bfd_target_elf_flavour |
4497 | && (S_IS_EXTERNAL (fragP->fr_symbol) | |
4498 | || S_IS_WEAK (fragP->fr_symbol))) | |
b98ef147 AM |
4499 | #endif |
4500 | ) | |
252b5132 | 4501 | { |
b98ef147 AM |
4502 | /* Symbol is undefined in this segment, or we need to keep a |
4503 | reloc so that weak symbols can be overridden. */ | |
4504 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 4505 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
4506 | unsigned char *opcode; |
4507 | int old_fr_fix; | |
f6af82bd | 4508 | |
ee7fcc42 AM |
4509 | if (fragP->fr_var != NO_RELOC) |
4510 | reloc_type = fragP->fr_var; | |
b98ef147 | 4511 | else if (size == 2) |
f6af82bd AM |
4512 | reloc_type = BFD_RELOC_16_PCREL; |
4513 | else | |
4514 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 4515 | |
ee7fcc42 AM |
4516 | old_fr_fix = fragP->fr_fix; |
4517 | opcode = (unsigned char *) fragP->fr_opcode; | |
4518 | ||
fddf5b5b | 4519 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 4520 | { |
fddf5b5b AM |
4521 | case UNCOND_JUMP: |
4522 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 4523 | opcode[0] = 0xe9; |
252b5132 | 4524 | fragP->fr_fix += size; |
062cd5e7 AS |
4525 | fix_new (fragP, old_fr_fix, size, |
4526 | fragP->fr_symbol, | |
4527 | fragP->fr_offset, 1, | |
4528 | reloc_type); | |
252b5132 RH |
4529 | break; |
4530 | ||
fddf5b5b | 4531 | case COND_JUMP86: |
412167cb AM |
4532 | if (size == 2 |
4533 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
4534 | { |
4535 | /* Negate the condition, and branch past an | |
4536 | unconditional jump. */ | |
4537 | opcode[0] ^= 1; | |
4538 | opcode[1] = 3; | |
4539 | /* Insert an unconditional jump. */ | |
4540 | opcode[2] = 0xe9; | |
4541 | /* We added two extra opcode bytes, and have a two byte | |
4542 | offset. */ | |
4543 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
4544 | fix_new (fragP, old_fr_fix + 2, 2, |
4545 | fragP->fr_symbol, | |
4546 | fragP->fr_offset, 1, | |
4547 | reloc_type); | |
fddf5b5b AM |
4548 | break; |
4549 | } | |
4550 | /* Fall through. */ | |
4551 | ||
4552 | case COND_JUMP: | |
412167cb AM |
4553 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
4554 | { | |
3e02c1cc AM |
4555 | fixS *fixP; |
4556 | ||
412167cb | 4557 | fragP->fr_fix += 1; |
3e02c1cc AM |
4558 | fixP = fix_new (fragP, old_fr_fix, 1, |
4559 | fragP->fr_symbol, | |
4560 | fragP->fr_offset, 1, | |
4561 | BFD_RELOC_8_PCREL); | |
4562 | fixP->fx_signed = 1; | |
412167cb AM |
4563 | break; |
4564 | } | |
93c2a809 | 4565 | |
24eab124 | 4566 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 4567 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 4568 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 4569 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
4570 | /* We've added an opcode byte. */ |
4571 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
4572 | fix_new (fragP, old_fr_fix + 1, size, |
4573 | fragP->fr_symbol, | |
4574 | fragP->fr_offset, 1, | |
4575 | reloc_type); | |
252b5132 | 4576 | break; |
fddf5b5b AM |
4577 | |
4578 | default: | |
4579 | BAD_CASE (fragP->fr_subtype); | |
4580 | break; | |
252b5132 RH |
4581 | } |
4582 | frag_wane (fragP); | |
ee7fcc42 | 4583 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 4584 | } |
93c2a809 | 4585 | |
93c2a809 AM |
4586 | /* Guess size depending on current relax state. Initially the relax |
4587 | state will correspond to a short jump and we return 1, because | |
4588 | the variable part of the frag (the branch offset) is one byte | |
4589 | long. However, we can relax a section more than once and in that | |
4590 | case we must either set fr_subtype back to the unrelaxed state, | |
4591 | or return the value for the appropriate branch. */ | |
4592 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
4593 | } |
4594 | ||
47926f60 KH |
4595 | /* Called after relax() is finished. |
4596 | ||
4597 | In: Address of frag. | |
4598 | fr_type == rs_machine_dependent. | |
4599 | fr_subtype is what the address relaxed to. | |
4600 | ||
4601 | Out: Any fixSs and constants are set up. | |
4602 | Caller will turn frag into a ".space 0". */ | |
4603 | ||
252b5132 RH |
4604 | void |
4605 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
4606 | bfd *abfd ATTRIBUTE_UNUSED; |
4607 | segT sec ATTRIBUTE_UNUSED; | |
29b0f896 | 4608 | fragS *fragP; |
252b5132 | 4609 | { |
29b0f896 | 4610 | unsigned char *opcode; |
252b5132 | 4611 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
4612 | offsetT target_address; |
4613 | offsetT opcode_address; | |
252b5132 | 4614 | unsigned int extension = 0; |
847f7ad4 | 4615 | offsetT displacement_from_opcode_start; |
252b5132 RH |
4616 | |
4617 | opcode = (unsigned char *) fragP->fr_opcode; | |
4618 | ||
47926f60 | 4619 | /* Address we want to reach in file space. */ |
252b5132 | 4620 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 4621 | |
47926f60 | 4622 | /* Address opcode resides at in file space. */ |
252b5132 RH |
4623 | opcode_address = fragP->fr_address + fragP->fr_fix; |
4624 | ||
47926f60 | 4625 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
4626 | displacement_from_opcode_start = target_address - opcode_address; |
4627 | ||
fddf5b5b | 4628 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 4629 | { |
47926f60 KH |
4630 | /* Don't have to change opcode. */ |
4631 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 4632 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
4633 | } |
4634 | else | |
4635 | { | |
4636 | if (no_cond_jump_promotion | |
4637 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4638 | as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required")); | |
252b5132 | 4639 | |
fddf5b5b AM |
4640 | switch (fragP->fr_subtype) |
4641 | { | |
4642 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
4643 | extension = 4; /* 1 opcode + 4 displacement */ | |
4644 | opcode[0] = 0xe9; | |
4645 | where_to_put_displacement = &opcode[1]; | |
4646 | break; | |
252b5132 | 4647 | |
fddf5b5b AM |
4648 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
4649 | extension = 2; /* 1 opcode + 2 displacement */ | |
4650 | opcode[0] = 0xe9; | |
4651 | where_to_put_displacement = &opcode[1]; | |
4652 | break; | |
252b5132 | 4653 | |
fddf5b5b AM |
4654 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
4655 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
4656 | extension = 5; /* 2 opcode + 4 displacement */ | |
4657 | opcode[1] = opcode[0] + 0x10; | |
4658 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
4659 | where_to_put_displacement = &opcode[2]; | |
4660 | break; | |
252b5132 | 4661 | |
fddf5b5b AM |
4662 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
4663 | extension = 3; /* 2 opcode + 2 displacement */ | |
4664 | opcode[1] = opcode[0] + 0x10; | |
4665 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
4666 | where_to_put_displacement = &opcode[2]; | |
4667 | break; | |
252b5132 | 4668 | |
fddf5b5b AM |
4669 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
4670 | extension = 4; | |
4671 | opcode[0] ^= 1; | |
4672 | opcode[1] = 3; | |
4673 | opcode[2] = 0xe9; | |
4674 | where_to_put_displacement = &opcode[3]; | |
4675 | break; | |
4676 | ||
4677 | default: | |
4678 | BAD_CASE (fragP->fr_subtype); | |
4679 | break; | |
4680 | } | |
252b5132 | 4681 | } |
fddf5b5b | 4682 | |
47926f60 | 4683 | /* Now put displacement after opcode. */ |
252b5132 RH |
4684 | md_number_to_chars ((char *) where_to_put_displacement, |
4685 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 4686 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
4687 | fragP->fr_fix += extension; |
4688 | } | |
4689 | \f | |
47926f60 KH |
4690 | /* Size of byte displacement jmp. */ |
4691 | int md_short_jump_size = 2; | |
4692 | ||
4693 | /* Size of dword displacement jmp. */ | |
4694 | int md_long_jump_size = 5; | |
252b5132 | 4695 | |
47926f60 KH |
4696 | /* Size of relocation record. */ |
4697 | const int md_reloc_size = 8; | |
252b5132 RH |
4698 | |
4699 | void | |
4700 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
4701 | char *ptr; | |
4702 | addressT from_addr, to_addr; | |
ab9da554 ILT |
4703 | fragS *frag ATTRIBUTE_UNUSED; |
4704 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 4705 | { |
847f7ad4 | 4706 | offsetT offset; |
252b5132 RH |
4707 | |
4708 | offset = to_addr - (from_addr + 2); | |
47926f60 KH |
4709 | /* Opcode for byte-disp jump. */ |
4710 | md_number_to_chars (ptr, (valueT) 0xeb, 1); | |
252b5132 RH |
4711 | md_number_to_chars (ptr + 1, (valueT) offset, 1); |
4712 | } | |
4713 | ||
4714 | void | |
4715 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
4716 | char *ptr; | |
4717 | addressT from_addr, to_addr; | |
a38cf1db AM |
4718 | fragS *frag ATTRIBUTE_UNUSED; |
4719 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 4720 | { |
847f7ad4 | 4721 | offsetT offset; |
252b5132 | 4722 | |
a38cf1db AM |
4723 | offset = to_addr - (from_addr + 5); |
4724 | md_number_to_chars (ptr, (valueT) 0xe9, 1); | |
4725 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
252b5132 RH |
4726 | } |
4727 | \f | |
4728 | /* Apply a fixup (fixS) to segment data, once it has been determined | |
4729 | by our caller that we have all the info we need to fix it up. | |
4730 | ||
4731 | On the 386, immediates, displacements, and data pointers are all in | |
4732 | the same (little-endian) format, so we don't need to care about which | |
4733 | we are handling. */ | |
4734 | ||
94f592af NC |
4735 | void |
4736 | md_apply_fix3 (fixP, valP, seg) | |
47926f60 KH |
4737 | /* The fix we're to put in. */ |
4738 | fixS *fixP; | |
47926f60 | 4739 | /* Pointer to the value of the bits. */ |
c6682705 | 4740 | valueT *valP; |
47926f60 KH |
4741 | /* Segment fix is from. */ |
4742 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 | 4743 | { |
94f592af | 4744 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 4745 | valueT value = *valP; |
252b5132 | 4746 | |
f86103b7 | 4747 | #if !defined (TE_Mach) |
93382f6d AM |
4748 | if (fixP->fx_pcrel) |
4749 | { | |
4750 | switch (fixP->fx_r_type) | |
4751 | { | |
5865bb77 ILT |
4752 | default: |
4753 | break; | |
4754 | ||
93382f6d AM |
4755 | case BFD_RELOC_32: |
4756 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
4757 | break; | |
4758 | case BFD_RELOC_16: | |
4759 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
4760 | break; | |
4761 | case BFD_RELOC_8: | |
4762 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
4763 | break; | |
4764 | } | |
4765 | } | |
252b5132 | 4766 | |
a161fe53 | 4767 | if (fixP->fx_addsy != NULL |
31312f95 AM |
4768 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
4769 | || fixP->fx_r_type == BFD_RELOC_16_PCREL | |
4770 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
4771 | && !use_rela_relocations) | |
252b5132 | 4772 | { |
31312f95 AM |
4773 | /* This is a hack. There should be a better way to handle this. |
4774 | This covers for the fact that bfd_install_relocation will | |
4775 | subtract the current location (for partial_inplace, PC relative | |
4776 | relocations); see more below. */ | |
252b5132 RH |
4777 | #ifndef OBJ_AOUT |
4778 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4779 | #ifdef TE_PE | |
4780 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
4781 | #endif | |
4782 | ) | |
4783 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4784 | #endif | |
4785 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2f66722d | 4786 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
252b5132 | 4787 | { |
6539b54b | 4788 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 4789 | |
6539b54b | 4790 | if ((sym_seg == seg |
2f66722d | 4791 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 4792 | && sym_seg != absolute_section)) |
ae6063d4 | 4793 | && !generic_force_reloc (fixP)) |
2f66722d AM |
4794 | { |
4795 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
4796 | bfd_install_relocation subtracts them out again. I think |
4797 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
4798 | it. FIXME. */ |
4799 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4800 | } | |
252b5132 RH |
4801 | } |
4802 | #endif | |
4803 | #if defined (OBJ_COFF) && defined (TE_PE) | |
4804 | /* For some reason, the PE format does not store a section | |
24eab124 | 4805 | address offset for a PC relative symbol. */ |
252b5132 RH |
4806 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) |
4807 | value += md_pcrel_from (fixP); | |
4808 | #endif | |
4809 | } | |
4810 | ||
4811 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 4812 | and we must not disappoint it. */ |
252b5132 RH |
4813 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4814 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4815 | && fixP->fx_addsy) | |
47926f60 KH |
4816 | switch (fixP->fx_r_type) |
4817 | { | |
4818 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 4819 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
4820 | /* Make the jump instruction point to the address of the operand. At |
4821 | runtime we merely add the offset to the actual PLT entry. */ | |
4822 | value = -4; | |
4823 | break; | |
31312f95 | 4824 | |
13ae64f3 JJ |
4825 | case BFD_RELOC_386_TLS_GD: |
4826 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 4827 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
4828 | case BFD_RELOC_386_TLS_IE: |
4829 | case BFD_RELOC_386_TLS_GOTIE: | |
bffbf940 JJ |
4830 | case BFD_RELOC_X86_64_TLSGD: |
4831 | case BFD_RELOC_X86_64_TLSLD: | |
4832 | case BFD_RELOC_X86_64_GOTTPOFF: | |
00f7efb6 JJ |
4833 | value = 0; /* Fully resolved at runtime. No addend. */ |
4834 | /* Fallthrough */ | |
4835 | case BFD_RELOC_386_TLS_LE: | |
4836 | case BFD_RELOC_386_TLS_LDO_32: | |
4837 | case BFD_RELOC_386_TLS_LE_32: | |
4838 | case BFD_RELOC_X86_64_DTPOFF32: | |
4839 | case BFD_RELOC_X86_64_TPOFF32: | |
4840 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
4841 | break; | |
4842 | ||
4843 | case BFD_RELOC_386_GOT32: | |
4844 | case BFD_RELOC_X86_64_GOT32: | |
47926f60 KH |
4845 | value = 0; /* Fully resolved at runtime. No addend. */ |
4846 | break; | |
47926f60 KH |
4847 | |
4848 | case BFD_RELOC_VTABLE_INHERIT: | |
4849 | case BFD_RELOC_VTABLE_ENTRY: | |
4850 | fixP->fx_done = 0; | |
94f592af | 4851 | return; |
47926f60 KH |
4852 | |
4853 | default: | |
4854 | break; | |
4855 | } | |
4856 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 4857 | *valP = value; |
f86103b7 | 4858 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 4859 | |
3e73aa7c | 4860 | /* Are we finished with this relocation now? */ |
c6682705 | 4861 | if (fixP->fx_addsy == NULL) |
3e73aa7c JH |
4862 | fixP->fx_done = 1; |
4863 | else if (use_rela_relocations) | |
4864 | { | |
4865 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
4866 | /* Remember value for tc_gen_reloc. */ |
4867 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
4868 | value = 0; |
4869 | } | |
f86103b7 | 4870 | |
94f592af | 4871 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 4872 | } |
252b5132 | 4873 | \f |
252b5132 RH |
4874 | #define MAX_LITTLENUMS 6 |
4875 | ||
47926f60 KH |
4876 | /* Turn the string pointed to by litP into a floating point constant |
4877 | of type TYPE, and emit the appropriate bytes. The number of | |
4878 | LITTLENUMS emitted is stored in *SIZEP. An error message is | |
4879 | returned, or NULL on OK. */ | |
4880 | ||
252b5132 RH |
4881 | char * |
4882 | md_atof (type, litP, sizeP) | |
2ab9b79e | 4883 | int type; |
252b5132 RH |
4884 | char *litP; |
4885 | int *sizeP; | |
4886 | { | |
4887 | int prec; | |
4888 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4889 | LITTLENUM_TYPE *wordP; | |
4890 | char *t; | |
4891 | ||
4892 | switch (type) | |
4893 | { | |
4894 | case 'f': | |
4895 | case 'F': | |
4896 | prec = 2; | |
4897 | break; | |
4898 | ||
4899 | case 'd': | |
4900 | case 'D': | |
4901 | prec = 4; | |
4902 | break; | |
4903 | ||
4904 | case 'x': | |
4905 | case 'X': | |
4906 | prec = 5; | |
4907 | break; | |
4908 | ||
4909 | default: | |
4910 | *sizeP = 0; | |
4911 | return _("Bad call to md_atof ()"); | |
4912 | } | |
4913 | t = atof_ieee (input_line_pointer, type, words); | |
4914 | if (t) | |
4915 | input_line_pointer = t; | |
4916 | ||
4917 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
4918 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with | |
4919 | the bigendian 386. */ | |
4920 | for (wordP = words + prec - 1; prec--;) | |
4921 | { | |
4922 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); | |
4923 | litP += sizeof (LITTLENUM_TYPE); | |
4924 | } | |
4925 | return 0; | |
4926 | } | |
4927 | \f | |
4928 | char output_invalid_buf[8]; | |
4929 | ||
252b5132 RH |
4930 | static char * |
4931 | output_invalid (c) | |
4932 | int c; | |
4933 | { | |
3882b010 | 4934 | if (ISPRINT (c)) |
252b5132 RH |
4935 | sprintf (output_invalid_buf, "'%c'", c); |
4936 | else | |
4937 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
4938 | return output_invalid_buf; | |
4939 | } | |
4940 | ||
af6bdddf | 4941 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
4942 | |
4943 | static const reg_entry * | |
4944 | parse_register (reg_string, end_op) | |
4945 | char *reg_string; | |
4946 | char **end_op; | |
4947 | { | |
af6bdddf AM |
4948 | char *s = reg_string; |
4949 | char *p; | |
252b5132 RH |
4950 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
4951 | const reg_entry *r; | |
4952 | ||
4953 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
4954 | if (*s == REGISTER_PREFIX) | |
4955 | ++s; | |
4956 | ||
4957 | if (is_space_char (*s)) | |
4958 | ++s; | |
4959 | ||
4960 | p = reg_name_given; | |
af6bdddf | 4961 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
4962 | { |
4963 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
4964 | return (const reg_entry *) NULL; |
4965 | s++; | |
252b5132 RH |
4966 | } |
4967 | ||
6588847e DN |
4968 | /* For naked regs, make sure that we are not dealing with an identifier. |
4969 | This prevents confusing an identifier like `eax_var' with register | |
4970 | `eax'. */ | |
4971 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
4972 | return (const reg_entry *) NULL; | |
4973 | ||
af6bdddf | 4974 | *end_op = s; |
252b5132 RH |
4975 | |
4976 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
4977 | ||
5f47d35b | 4978 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 4979 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 4980 | { |
5f47d35b AM |
4981 | if (is_space_char (*s)) |
4982 | ++s; | |
4983 | if (*s == '(') | |
4984 | { | |
af6bdddf | 4985 | ++s; |
5f47d35b AM |
4986 | if (is_space_char (*s)) |
4987 | ++s; | |
4988 | if (*s >= '0' && *s <= '7') | |
4989 | { | |
4990 | r = &i386_float_regtab[*s - '0']; | |
af6bdddf | 4991 | ++s; |
5f47d35b AM |
4992 | if (is_space_char (*s)) |
4993 | ++s; | |
4994 | if (*s == ')') | |
4995 | { | |
4996 | *end_op = s + 1; | |
4997 | return r; | |
4998 | } | |
5f47d35b | 4999 | } |
47926f60 | 5000 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
5001 | return (const reg_entry *) NULL; |
5002 | } | |
5003 | } | |
5004 | ||
1ae00879 | 5005 | if (r != NULL |
20f0a1fc | 5006 | && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0 |
1ae00879 | 5007 | && flag_code != CODE_64BIT) |
20f0a1fc | 5008 | return (const reg_entry *) NULL; |
1ae00879 | 5009 | |
252b5132 RH |
5010 | return r; |
5011 | } | |
5012 | \f | |
4cc782b5 | 5013 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 5014 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 5015 | #else |
12b55ccc | 5016 | const char *md_shortopts = "qn"; |
252b5132 | 5017 | #endif |
6e0b89ee | 5018 | |
252b5132 | 5019 | struct option md_longopts[] = { |
3e73aa7c JH |
5020 | #define OPTION_32 (OPTION_MD_BASE + 0) |
5021 | {"32", no_argument, NULL, OPTION_32}, | |
6e0b89ee | 5022 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3e73aa7c JH |
5023 | #define OPTION_64 (OPTION_MD_BASE + 1) |
5024 | {"64", no_argument, NULL, OPTION_64}, | |
6e0b89ee | 5025 | #endif |
252b5132 RH |
5026 | {NULL, no_argument, NULL, 0} |
5027 | }; | |
5028 | size_t md_longopts_size = sizeof (md_longopts); | |
5029 | ||
5030 | int | |
5031 | md_parse_option (c, arg) | |
5032 | int c; | |
ab9da554 | 5033 | char *arg ATTRIBUTE_UNUSED; |
252b5132 RH |
5034 | { |
5035 | switch (c) | |
5036 | { | |
12b55ccc L |
5037 | case 'n': |
5038 | optimize_align_code = 0; | |
5039 | break; | |
5040 | ||
a38cf1db AM |
5041 | case 'q': |
5042 | quiet_warnings = 1; | |
252b5132 RH |
5043 | break; |
5044 | ||
5045 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
5046 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
5047 | should be emitted or not. FIXME: Not implemented. */ | |
5048 | case 'Q': | |
252b5132 RH |
5049 | break; |
5050 | ||
5051 | /* -V: SVR4 argument to print version ID. */ | |
5052 | case 'V': | |
5053 | print_version_id (); | |
5054 | break; | |
5055 | ||
a38cf1db AM |
5056 | /* -k: Ignore for FreeBSD compatibility. */ |
5057 | case 'k': | |
252b5132 | 5058 | break; |
4cc782b5 ILT |
5059 | |
5060 | case 's': | |
5061 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 5062 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 5063 | break; |
6e0b89ee | 5064 | |
3e73aa7c JH |
5065 | case OPTION_64: |
5066 | { | |
5067 | const char **list, **l; | |
5068 | ||
3e73aa7c JH |
5069 | list = bfd_target_list (); |
5070 | for (l = list; *l != NULL; l++) | |
6e0b89ee AM |
5071 | if (strcmp (*l, "elf64-x86-64") == 0) |
5072 | { | |
5073 | default_arch = "x86_64"; | |
5074 | break; | |
5075 | } | |
3e73aa7c | 5076 | if (*l == NULL) |
6e0b89ee | 5077 | as_fatal (_("No compiled in support for x86_64")); |
3e73aa7c JH |
5078 | free (list); |
5079 | } | |
5080 | break; | |
5081 | #endif | |
252b5132 | 5082 | |
6e0b89ee AM |
5083 | case OPTION_32: |
5084 | default_arch = "i386"; | |
5085 | break; | |
5086 | ||
252b5132 RH |
5087 | default: |
5088 | return 0; | |
5089 | } | |
5090 | return 1; | |
5091 | } | |
5092 | ||
5093 | void | |
5094 | md_show_usage (stream) | |
5095 | FILE *stream; | |
5096 | { | |
4cc782b5 ILT |
5097 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
5098 | fprintf (stream, _("\ | |
a38cf1db AM |
5099 | -Q ignored\n\ |
5100 | -V print assembler version number\n\ | |
5101 | -k ignored\n\ | |
12b55ccc | 5102 | -n Do not optimize code alignment\n\ |
a38cf1db AM |
5103 | -q quieten some warnings\n\ |
5104 | -s ignored\n")); | |
5105 | #else | |
5106 | fprintf (stream, _("\ | |
12b55ccc | 5107 | -n Do not optimize code alignment\n\ |
a38cf1db | 5108 | -q quieten some warnings\n")); |
4cc782b5 | 5109 | #endif |
252b5132 RH |
5110 | } |
5111 | ||
3e73aa7c JH |
5112 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
5113 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
252b5132 RH |
5114 | |
5115 | /* Pick the target format to use. */ | |
5116 | ||
47926f60 | 5117 | const char * |
252b5132 RH |
5118 | i386_target_format () |
5119 | { | |
3e73aa7c JH |
5120 | if (!strcmp (default_arch, "x86_64")) |
5121 | set_code_flag (CODE_64BIT); | |
5122 | else if (!strcmp (default_arch, "i386")) | |
5123 | set_code_flag (CODE_32BIT); | |
5124 | else | |
5125 | as_fatal (_("Unknown architecture")); | |
252b5132 RH |
5126 | switch (OUTPUT_FLAVOR) |
5127 | { | |
4c63da97 AM |
5128 | #ifdef OBJ_MAYBE_AOUT |
5129 | case bfd_target_aout_flavour: | |
47926f60 | 5130 | return AOUT_TARGET_FORMAT; |
4c63da97 AM |
5131 | #endif |
5132 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
5133 | case bfd_target_coff_flavour: |
5134 | return "coff-i386"; | |
4c63da97 | 5135 | #endif |
3e73aa7c | 5136 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 5137 | case bfd_target_elf_flavour: |
3e73aa7c | 5138 | { |
e5cb08ac KH |
5139 | if (flag_code == CODE_64BIT) |
5140 | use_rela_relocations = 1; | |
4ada7262 | 5141 | return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT; |
3e73aa7c | 5142 | } |
4c63da97 | 5143 | #endif |
252b5132 RH |
5144 | default: |
5145 | abort (); | |
5146 | return NULL; | |
5147 | } | |
5148 | } | |
5149 | ||
47926f60 | 5150 | #endif /* OBJ_MAYBE_ more than one */ |
a847613f AM |
5151 | |
5152 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
5153 | void i386_elf_emit_arch_note () | |
5154 | { | |
5155 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
5156 | && cpu_arch_name != NULL) | |
5157 | { | |
5158 | char *p; | |
5159 | asection *seg = now_seg; | |
5160 | subsegT subseg = now_subseg; | |
5161 | Elf_Internal_Note i_note; | |
5162 | Elf_External_Note e_note; | |
5163 | asection *note_secp; | |
5164 | int len; | |
5165 | ||
5166 | /* Create the .note section. */ | |
5167 | note_secp = subseg_new (".note", 0); | |
5168 | bfd_set_section_flags (stdoutput, | |
5169 | note_secp, | |
5170 | SEC_HAS_CONTENTS | SEC_READONLY); | |
5171 | ||
5172 | /* Process the arch string. */ | |
5173 | len = strlen (cpu_arch_name); | |
5174 | ||
5175 | i_note.namesz = len + 1; | |
5176 | i_note.descsz = 0; | |
5177 | i_note.type = NT_ARCH; | |
5178 | p = frag_more (sizeof (e_note.namesz)); | |
5179 | md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); | |
5180 | p = frag_more (sizeof (e_note.descsz)); | |
5181 | md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); | |
5182 | p = frag_more (sizeof (e_note.type)); | |
5183 | md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); | |
5184 | p = frag_more (len + 1); | |
5185 | strcpy (p, cpu_arch_name); | |
5186 | ||
5187 | frag_align (2, 0, 0); | |
5188 | ||
5189 | subseg_set (seg, subseg); | |
5190 | } | |
5191 | } | |
5192 | #endif | |
252b5132 | 5193 | \f |
252b5132 RH |
5194 | symbolS * |
5195 | md_undefined_symbol (name) | |
5196 | char *name; | |
5197 | { | |
18dc2407 ILT |
5198 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
5199 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
5200 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
5201 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
5202 | { |
5203 | if (!GOT_symbol) | |
5204 | { | |
5205 | if (symbol_find (name)) | |
5206 | as_bad (_("GOT already in symbol table")); | |
5207 | GOT_symbol = symbol_new (name, undefined_section, | |
5208 | (valueT) 0, &zero_address_frag); | |
5209 | }; | |
5210 | return GOT_symbol; | |
5211 | } | |
252b5132 RH |
5212 | return 0; |
5213 | } | |
5214 | ||
5215 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 5216 | |
252b5132 RH |
5217 | valueT |
5218 | md_section_align (segment, size) | |
ab9da554 | 5219 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
5220 | valueT size; |
5221 | { | |
4c63da97 AM |
5222 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
5223 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
5224 | { | |
5225 | /* For a.out, force the section size to be aligned. If we don't do | |
5226 | this, BFD will align it for us, but it will not write out the | |
5227 | final bytes of the section. This may be a bug in BFD, but it is | |
5228 | easier to fix it here since that is how the other a.out targets | |
5229 | work. */ | |
5230 | int align; | |
5231 | ||
5232 | align = bfd_get_section_alignment (stdoutput, segment); | |
5233 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
5234 | } | |
252b5132 RH |
5235 | #endif |
5236 | ||
5237 | return size; | |
5238 | } | |
5239 | ||
5240 | /* On the i386, PC-relative offsets are relative to the start of the | |
5241 | next instruction. That is, the address of the offset, plus its | |
5242 | size, since the offset is always the last part of the insn. */ | |
5243 | ||
5244 | long | |
5245 | md_pcrel_from (fixP) | |
5246 | fixS *fixP; | |
5247 | { | |
5248 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
5249 | } | |
5250 | ||
5251 | #ifndef I386COFF | |
5252 | ||
5253 | static void | |
5254 | s_bss (ignore) | |
ab9da554 | 5255 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 5256 | { |
29b0f896 | 5257 | int temp; |
252b5132 RH |
5258 | |
5259 | temp = get_absolute_expression (); | |
5260 | subseg_set (bss_section, (subsegT) temp); | |
5261 | demand_empty_rest_of_line (); | |
5262 | } | |
5263 | ||
5264 | #endif | |
5265 | ||
252b5132 RH |
5266 | void |
5267 | i386_validate_fix (fixp) | |
5268 | fixS *fixp; | |
5269 | { | |
5270 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
5271 | { | |
3e73aa7c | 5272 | /* GOTOFF relocation are nonsense in 64bit mode. */ |
23df1078 JH |
5273 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
5274 | { | |
5275 | if (flag_code != CODE_64BIT) | |
5276 | abort (); | |
5277 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
5278 | } | |
5279 | else | |
5280 | { | |
5281 | if (flag_code == CODE_64BIT) | |
5282 | abort (); | |
5283 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
5284 | } | |
252b5132 RH |
5285 | fixp->fx_subsy = 0; |
5286 | } | |
5287 | } | |
5288 | ||
252b5132 RH |
5289 | arelent * |
5290 | tc_gen_reloc (section, fixp) | |
ab9da554 | 5291 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
5292 | fixS *fixp; |
5293 | { | |
5294 | arelent *rel; | |
5295 | bfd_reloc_code_real_type code; | |
5296 | ||
5297 | switch (fixp->fx_r_type) | |
5298 | { | |
3e73aa7c JH |
5299 | case BFD_RELOC_X86_64_PLT32: |
5300 | case BFD_RELOC_X86_64_GOT32: | |
5301 | case BFD_RELOC_X86_64_GOTPCREL: | |
252b5132 RH |
5302 | case BFD_RELOC_386_PLT32: |
5303 | case BFD_RELOC_386_GOT32: | |
5304 | case BFD_RELOC_386_GOTOFF: | |
5305 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
5306 | case BFD_RELOC_386_TLS_GD: |
5307 | case BFD_RELOC_386_TLS_LDM: | |
5308 | case BFD_RELOC_386_TLS_LDO_32: | |
5309 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
5310 | case BFD_RELOC_386_TLS_IE: |
5311 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
5312 | case BFD_RELOC_386_TLS_LE_32: |
5313 | case BFD_RELOC_386_TLS_LE: | |
3e73aa7c | 5314 | case BFD_RELOC_X86_64_32S: |
bffbf940 JJ |
5315 | case BFD_RELOC_X86_64_TLSGD: |
5316 | case BFD_RELOC_X86_64_TLSLD: | |
5317 | case BFD_RELOC_X86_64_DTPOFF32: | |
5318 | case BFD_RELOC_X86_64_GOTTPOFF: | |
5319 | case BFD_RELOC_X86_64_TPOFF32: | |
252b5132 RH |
5320 | case BFD_RELOC_RVA: |
5321 | case BFD_RELOC_VTABLE_ENTRY: | |
5322 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
5323 | #ifdef TE_PE |
5324 | case BFD_RELOC_32_SECREL: | |
5325 | #endif | |
252b5132 RH |
5326 | code = fixp->fx_r_type; |
5327 | break; | |
5328 | default: | |
93382f6d | 5329 | if (fixp->fx_pcrel) |
252b5132 | 5330 | { |
93382f6d AM |
5331 | switch (fixp->fx_size) |
5332 | { | |
5333 | default: | |
b091f402 AM |
5334 | as_bad_where (fixp->fx_file, fixp->fx_line, |
5335 | _("can not do %d byte pc-relative relocation"), | |
5336 | fixp->fx_size); | |
93382f6d AM |
5337 | code = BFD_RELOC_32_PCREL; |
5338 | break; | |
5339 | case 1: code = BFD_RELOC_8_PCREL; break; | |
5340 | case 2: code = BFD_RELOC_16_PCREL; break; | |
5341 | case 4: code = BFD_RELOC_32_PCREL; break; | |
5342 | } | |
5343 | } | |
5344 | else | |
5345 | { | |
5346 | switch (fixp->fx_size) | |
5347 | { | |
5348 | default: | |
b091f402 AM |
5349 | as_bad_where (fixp->fx_file, fixp->fx_line, |
5350 | _("can not do %d byte relocation"), | |
5351 | fixp->fx_size); | |
93382f6d AM |
5352 | code = BFD_RELOC_32; |
5353 | break; | |
5354 | case 1: code = BFD_RELOC_8; break; | |
5355 | case 2: code = BFD_RELOC_16; break; | |
5356 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 5357 | #ifdef BFD64 |
3e73aa7c | 5358 | case 8: code = BFD_RELOC_64; break; |
937149dd | 5359 | #endif |
93382f6d | 5360 | } |
252b5132 RH |
5361 | } |
5362 | break; | |
5363 | } | |
252b5132 RH |
5364 | |
5365 | if (code == BFD_RELOC_32 | |
5366 | && GOT_symbol | |
5367 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c JH |
5368 | { |
5369 | /* We don't support GOTPC on 64bit targets. */ | |
5370 | if (flag_code == CODE_64BIT) | |
bfb32b52 | 5371 | abort (); |
3e73aa7c JH |
5372 | code = BFD_RELOC_386_GOTPC; |
5373 | } | |
252b5132 RH |
5374 | |
5375 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
5376 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
5377 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
5378 | |
5379 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 CF |
5380 | |
5381 | #ifdef TE_PE | |
5382 | if (S_IS_WEAK (fixp->fx_addsy)) | |
5383 | rel->addend = rel->address - (*rel->sym_ptr_ptr)->value + 4; | |
5384 | else | |
5385 | #endif | |
3e73aa7c JH |
5386 | if (!use_rela_relocations) |
5387 | { | |
5388 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
5389 | vtable entry to be used in the relocation's section offset. */ | |
5390 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5391 | rel->address = fixp->fx_offset; | |
252b5132 | 5392 | |
c6682705 | 5393 | rel->addend = 0; |
3e73aa7c JH |
5394 | } |
5395 | /* Use the rela in 64bit mode. */ | |
252b5132 | 5396 | else |
3e73aa7c | 5397 | { |
062cd5e7 AS |
5398 | if (!fixp->fx_pcrel) |
5399 | rel->addend = fixp->fx_offset; | |
5400 | else | |
5401 | switch (code) | |
5402 | { | |
5403 | case BFD_RELOC_X86_64_PLT32: | |
5404 | case BFD_RELOC_X86_64_GOT32: | |
5405 | case BFD_RELOC_X86_64_GOTPCREL: | |
bffbf940 JJ |
5406 | case BFD_RELOC_X86_64_TLSGD: |
5407 | case BFD_RELOC_X86_64_TLSLD: | |
5408 | case BFD_RELOC_X86_64_GOTTPOFF: | |
062cd5e7 AS |
5409 | rel->addend = fixp->fx_offset - fixp->fx_size; |
5410 | break; | |
5411 | default: | |
5412 | rel->addend = (section->vma | |
5413 | - fixp->fx_size | |
5414 | + fixp->fx_addnumber | |
5415 | + md_pcrel_from (fixp)); | |
5416 | break; | |
5417 | } | |
3e73aa7c JH |
5418 | } |
5419 | ||
252b5132 RH |
5420 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
5421 | if (rel->howto == NULL) | |
5422 | { | |
5423 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 5424 | _("cannot represent relocation type %s"), |
252b5132 RH |
5425 | bfd_get_reloc_code_name (code)); |
5426 | /* Set howto to a garbage value so that we can keep going. */ | |
5427 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
5428 | assert (rel->howto != NULL); | |
5429 | } | |
5430 | ||
5431 | return rel; | |
5432 | } | |
5433 | ||
64a0c779 DN |
5434 | \f |
5435 | /* Parse operands using Intel syntax. This implements a recursive descent | |
5436 | parser based on the BNF grammar published in Appendix B of the MASM 6.1 | |
5437 | Programmer's Guide. | |
5438 | ||
5439 | FIXME: We do not recognize the full operand grammar defined in the MASM | |
5440 | documentation. In particular, all the structure/union and | |
5441 | high-level macro operands are missing. | |
5442 | ||
5443 | Uppercase words are terminals, lower case words are non-terminals. | |
5444 | Objects surrounded by double brackets '[[' ']]' are optional. Vertical | |
5445 | bars '|' denote choices. Most grammar productions are implemented in | |
5446 | functions called 'intel_<production>'. | |
5447 | ||
5448 | Initial production is 'expr'. | |
5449 | ||
9306ca4a | 5450 | addOp + | - |
64a0c779 DN |
5451 | |
5452 | alpha [a-zA-Z] | |
5453 | ||
9306ca4a JB |
5454 | binOp & | AND | \| | OR | ^ | XOR |
5455 | ||
64a0c779 DN |
5456 | byteRegister AL | AH | BL | BH | CL | CH | DL | DH |
5457 | ||
5458 | constant digits [[ radixOverride ]] | |
5459 | ||
9306ca4a | 5460 | dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD |
64a0c779 DN |
5461 | |
5462 | digits decdigit | |
b77a7acd AJ |
5463 | | digits decdigit |
5464 | | digits hexdigit | |
64a0c779 DN |
5465 | |
5466 | decdigit [0-9] | |
5467 | ||
9306ca4a JB |
5468 | e04 e04 addOp e05 |
5469 | | e05 | |
5470 | ||
5471 | e05 e05 binOp e06 | |
b77a7acd | 5472 | | e06 |
64a0c779 DN |
5473 | |
5474 | e06 e06 mulOp e09 | |
b77a7acd | 5475 | | e09 |
64a0c779 DN |
5476 | |
5477 | e09 OFFSET e10 | |
9306ca4a JB |
5478 | | ~ e10 |
5479 | | NOT e10 | |
64a0c779 DN |
5480 | | e09 PTR e10 |
5481 | | e09 : e10 | |
5482 | | e10 | |
5483 | ||
5484 | e10 e10 [ expr ] | |
b77a7acd | 5485 | | e11 |
64a0c779 DN |
5486 | |
5487 | e11 ( expr ) | |
b77a7acd | 5488 | | [ expr ] |
64a0c779 DN |
5489 | | constant |
5490 | | dataType | |
5491 | | id | |
5492 | | $ | |
5493 | | register | |
5494 | ||
9306ca4a JB |
5495 | => expr SHORT e04 |
5496 | | e04 | |
64a0c779 DN |
5497 | |
5498 | gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX | |
b77a7acd | 5499 | | BP | EBP | SP | ESP | DI | EDI | SI | ESI |
64a0c779 DN |
5500 | |
5501 | hexdigit a | b | c | d | e | f | |
b77a7acd | 5502 | | A | B | C | D | E | F |
64a0c779 DN |
5503 | |
5504 | id alpha | |
b77a7acd | 5505 | | id alpha |
64a0c779 DN |
5506 | | id decdigit |
5507 | ||
9306ca4a | 5508 | mulOp * | / | % | MOD | << | SHL | >> | SHR |
64a0c779 DN |
5509 | |
5510 | quote " | ' | |
5511 | ||
5512 | register specialRegister | |
b77a7acd | 5513 | | gpRegister |
64a0c779 DN |
5514 | | byteRegister |
5515 | ||
5516 | segmentRegister CS | DS | ES | FS | GS | SS | |
5517 | ||
9306ca4a | 5518 | specialRegister CR0 | CR2 | CR3 | CR4 |
b77a7acd | 5519 | | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 |
64a0c779 DN |
5520 | | TR3 | TR4 | TR5 | TR6 | TR7 |
5521 | ||
64a0c779 DN |
5522 | We simplify the grammar in obvious places (e.g., register parsing is |
5523 | done by calling parse_register) and eliminate immediate left recursion | |
5524 | to implement a recursive-descent parser. | |
5525 | ||
9306ca4a JB |
5526 | expr SHORT e04 |
5527 | | e04 | |
5528 | ||
5529 | e04 e05 e04' | |
5530 | ||
5531 | e04' addOp e05 e04' | |
5532 | | Empty | |
64a0c779 DN |
5533 | |
5534 | e05 e06 e05' | |
5535 | ||
9306ca4a | 5536 | e05' binOp e06 e05' |
b77a7acd | 5537 | | Empty |
64a0c779 DN |
5538 | |
5539 | e06 e09 e06' | |
5540 | ||
5541 | e06' mulOp e09 e06' | |
b77a7acd | 5542 | | Empty |
64a0c779 DN |
5543 | |
5544 | e09 OFFSET e10 e09' | |
9306ca4a JB |
5545 | | ~ e10 |
5546 | | NOT e10 | |
b77a7acd | 5547 | | e10 e09' |
64a0c779 DN |
5548 | |
5549 | e09' PTR e10 e09' | |
b77a7acd | 5550 | | : e10 e09' |
64a0c779 DN |
5551 | | Empty |
5552 | ||
5553 | e10 e11 e10' | |
5554 | ||
5555 | e10' [ expr ] e10' | |
b77a7acd | 5556 | | Empty |
64a0c779 DN |
5557 | |
5558 | e11 ( expr ) | |
b77a7acd | 5559 | | [ expr ] |
64a0c779 DN |
5560 | | BYTE |
5561 | | WORD | |
5562 | | DWORD | |
9306ca4a | 5563 | | FWORD |
64a0c779 | 5564 | | QWORD |
9306ca4a JB |
5565 | | TBYTE |
5566 | | OWORD | |
5567 | | XMMWORD | |
64a0c779 DN |
5568 | | . |
5569 | | $ | |
5570 | | register | |
5571 | | id | |
5572 | | constant */ | |
5573 | ||
5574 | /* Parsing structure for the intel syntax parser. Used to implement the | |
5575 | semantic actions for the operand grammar. */ | |
5576 | struct intel_parser_s | |
5577 | { | |
5578 | char *op_string; /* The string being parsed. */ | |
5579 | int got_a_float; /* Whether the operand is a float. */ | |
4a1805b1 | 5580 | int op_modifier; /* Operand modifier. */ |
64a0c779 DN |
5581 | int is_mem; /* 1 if operand is memory reference. */ |
5582 | const reg_entry *reg; /* Last register reference found. */ | |
5583 | char *disp; /* Displacement string being built. */ | |
5584 | }; | |
5585 | ||
5586 | static struct intel_parser_s intel_parser; | |
5587 | ||
5588 | /* Token structure for parsing intel syntax. */ | |
5589 | struct intel_token | |
5590 | { | |
5591 | int code; /* Token code. */ | |
5592 | const reg_entry *reg; /* Register entry for register tokens. */ | |
5593 | char *str; /* String representation. */ | |
5594 | }; | |
5595 | ||
5596 | static struct intel_token cur_token, prev_token; | |
5597 | ||
50705ef4 AM |
5598 | /* Token codes for the intel parser. Since T_SHORT is already used |
5599 | by COFF, undefine it first to prevent a warning. */ | |
64a0c779 DN |
5600 | #define T_NIL -1 |
5601 | #define T_CONST 1 | |
5602 | #define T_REG 2 | |
5603 | #define T_BYTE 3 | |
5604 | #define T_WORD 4 | |
9306ca4a JB |
5605 | #define T_DWORD 5 |
5606 | #define T_FWORD 6 | |
5607 | #define T_QWORD 7 | |
5608 | #define T_TBYTE 8 | |
5609 | #define T_XMMWORD 9 | |
50705ef4 | 5610 | #undef T_SHORT |
9306ca4a JB |
5611 | #define T_SHORT 10 |
5612 | #define T_OFFSET 11 | |
5613 | #define T_PTR 12 | |
5614 | #define T_ID 13 | |
5615 | #define T_SHL 14 | |
5616 | #define T_SHR 15 | |
64a0c779 DN |
5617 | |
5618 | /* Prototypes for intel parser functions. */ | |
5619 | static int intel_match_token PARAMS ((int code)); | |
cce0cbdc DN |
5620 | static void intel_get_token PARAMS ((void)); |
5621 | static void intel_putback_token PARAMS ((void)); | |
5622 | static int intel_expr PARAMS ((void)); | |
9306ca4a JB |
5623 | static int intel_e04 PARAMS ((void)); |
5624 | static int intel_e04_1 PARAMS ((void)); | |
cce0cbdc DN |
5625 | static int intel_e05 PARAMS ((void)); |
5626 | static int intel_e05_1 PARAMS ((void)); | |
5627 | static int intel_e06 PARAMS ((void)); | |
5628 | static int intel_e06_1 PARAMS ((void)); | |
5629 | static int intel_e09 PARAMS ((void)); | |
5630 | static int intel_e09_1 PARAMS ((void)); | |
5631 | static int intel_e10 PARAMS ((void)); | |
5632 | static int intel_e10_1 PARAMS ((void)); | |
5633 | static int intel_e11 PARAMS ((void)); | |
64a0c779 | 5634 | |
64a0c779 DN |
5635 | static int |
5636 | i386_intel_operand (operand_string, got_a_float) | |
5637 | char *operand_string; | |
5638 | int got_a_float; | |
5639 | { | |
5640 | int ret; | |
5641 | char *p; | |
5642 | ||
5643 | /* Initialize token holders. */ | |
5644 | cur_token.code = prev_token.code = T_NIL; | |
5645 | cur_token.reg = prev_token.reg = NULL; | |
5646 | cur_token.str = prev_token.str = NULL; | |
5647 | ||
5648 | /* Initialize parser structure. */ | |
e5cb08ac | 5649 | p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1); |
64a0c779 DN |
5650 | if (p == NULL) |
5651 | abort (); | |
5652 | strcpy (intel_parser.op_string, operand_string); | |
5653 | intel_parser.got_a_float = got_a_float; | |
5654 | intel_parser.op_modifier = -1; | |
5655 | intel_parser.is_mem = 0; | |
5656 | intel_parser.reg = NULL; | |
e5cb08ac | 5657 | intel_parser.disp = (char *) malloc (strlen (operand_string) + 1); |
64a0c779 DN |
5658 | if (intel_parser.disp == NULL) |
5659 | abort (); | |
5660 | intel_parser.disp[0] = '\0'; | |
5661 | ||
5662 | /* Read the first token and start the parser. */ | |
5663 | intel_get_token (); | |
5664 | ret = intel_expr (); | |
5665 | ||
5666 | if (ret) | |
5667 | { | |
9306ca4a JB |
5668 | if (cur_token.code != T_NIL) |
5669 | { | |
5670 | as_bad (_("invalid operand for '%s' ('%s' unexpected)"), | |
5671 | current_templates->start->name, cur_token.str); | |
5672 | ret = 0; | |
5673 | } | |
64a0c779 DN |
5674 | /* If we found a memory reference, hand it over to i386_displacement |
5675 | to fill in the rest of the operand fields. */ | |
9306ca4a | 5676 | else if (intel_parser.is_mem) |
64a0c779 DN |
5677 | { |
5678 | if ((i.mem_operands == 1 | |
5679 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
5680 | || i.mem_operands == 2) | |
5681 | { | |
5682 | as_bad (_("too many memory references for '%s'"), | |
5683 | current_templates->start->name); | |
5684 | ret = 0; | |
5685 | } | |
5686 | else | |
5687 | { | |
5688 | char *s = intel_parser.disp; | |
5689 | i.mem_operands++; | |
5690 | ||
5691 | /* Add the displacement expression. */ | |
5692 | if (*s != '\0') | |
a4622f40 AM |
5693 | ret = i386_displacement (s, s + strlen (s)); |
5694 | if (ret) | |
5695 | ret = i386_index_check (operand_string); | |
64a0c779 DN |
5696 | } |
5697 | } | |
5698 | ||
5699 | /* Constant and OFFSET expressions are handled by i386_immediate. */ | |
9306ca4a | 5700 | else if (intel_parser.op_modifier == T_OFFSET |
64a0c779 DN |
5701 | || intel_parser.reg == NULL) |
5702 | ret = i386_immediate (intel_parser.disp); | |
5703 | } | |
5704 | ||
5705 | free (p); | |
5706 | free (intel_parser.disp); | |
5707 | ||
5708 | return ret; | |
5709 | } | |
5710 | ||
9306ca4a JB |
5711 | /* expr SHORT e04 |
5712 | | e04 */ | |
64a0c779 DN |
5713 | static int |
5714 | intel_expr () | |
5715 | { | |
9306ca4a | 5716 | /* expr SHORT e04 */ |
64a0c779 DN |
5717 | if (cur_token.code == T_SHORT) |
5718 | { | |
9306ca4a | 5719 | intel_parser.op_modifier = T_SHORT; |
64a0c779 DN |
5720 | intel_match_token (T_SHORT); |
5721 | ||
9306ca4a JB |
5722 | return (intel_e04 ()); |
5723 | } | |
5724 | ||
5725 | /* expr e04 */ | |
5726 | else | |
5727 | return intel_e04 (); | |
5728 | } | |
5729 | ||
5730 | /* e04 e06 e04' | |
5731 | ||
5732 | e04' addOp e06 e04' | |
5733 | | Empty */ | |
5734 | static int | |
5735 | intel_e04 () | |
5736 | { | |
5737 | return (intel_e05 () && intel_e04_1 ()); | |
5738 | } | |
5739 | ||
5740 | static int | |
5741 | intel_e04_1 () | |
5742 | { | |
5743 | /* e04' addOp e05 e04' */ | |
5744 | if (cur_token.code == '+' || cur_token.code == '-') | |
5745 | { | |
5746 | char str[2]; | |
5747 | ||
5748 | str[0] = cur_token.code; | |
5749 | str[1] = 0; | |
5750 | strcat (intel_parser.disp, str); | |
5751 | intel_match_token (cur_token.code); | |
5752 | ||
5753 | return (intel_e05 () && intel_e04_1 ()); | |
64a0c779 DN |
5754 | } |
5755 | ||
9306ca4a | 5756 | /* e04' Empty */ |
64a0c779 | 5757 | else |
9306ca4a | 5758 | return 1; |
64a0c779 DN |
5759 | } |
5760 | ||
64a0c779 DN |
5761 | /* e05 e06 e05' |
5762 | ||
9306ca4a | 5763 | e05' binOp e06 e05' |
64a0c779 DN |
5764 | | Empty */ |
5765 | static int | |
5766 | intel_e05 () | |
5767 | { | |
5768 | return (intel_e06 () && intel_e05_1 ()); | |
5769 | } | |
5770 | ||
5771 | static int | |
5772 | intel_e05_1 () | |
5773 | { | |
9306ca4a JB |
5774 | /* e05' binOp e06 e05' */ |
5775 | if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^') | |
64a0c779 | 5776 | { |
9306ca4a JB |
5777 | char str[2]; |
5778 | ||
5779 | str[0] = cur_token.code; | |
5780 | str[1] = 0; | |
5781 | strcat (intel_parser.disp, str); | |
64a0c779 DN |
5782 | intel_match_token (cur_token.code); |
5783 | ||
5784 | return (intel_e06 () && intel_e05_1 ()); | |
5785 | } | |
5786 | ||
5787 | /* e05' Empty */ | |
5788 | else | |
5789 | return 1; | |
4a1805b1 | 5790 | } |
64a0c779 DN |
5791 | |
5792 | /* e06 e09 e06' | |
5793 | ||
5794 | e06' mulOp e09 e06' | |
b77a7acd | 5795 | | Empty */ |
64a0c779 DN |
5796 | static int |
5797 | intel_e06 () | |
5798 | { | |
5799 | return (intel_e09 () && intel_e06_1 ()); | |
5800 | } | |
5801 | ||
5802 | static int | |
5803 | intel_e06_1 () | |
5804 | { | |
5805 | /* e06' mulOp e09 e06' */ | |
9306ca4a | 5806 | if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%') |
64a0c779 | 5807 | { |
9306ca4a JB |
5808 | char str[2]; |
5809 | ||
5810 | str[0] = cur_token.code; | |
5811 | str[1] = 0; | |
5812 | strcat (intel_parser.disp, str); | |
5813 | intel_match_token (cur_token.code); | |
5814 | ||
5815 | return (intel_e09 () && intel_e06_1 ()); | |
5816 | } | |
5817 | else if (cur_token.code == T_SHL) | |
5818 | { | |
5819 | strcat (intel_parser.disp, "<<"); | |
5820 | intel_match_token (cur_token.code); | |
5821 | ||
5822 | return (intel_e09 () && intel_e06_1 ()); | |
5823 | } | |
5824 | else if (cur_token.code == T_SHR) | |
5825 | { | |
5826 | strcat (intel_parser.disp, ">>"); | |
64a0c779 DN |
5827 | intel_match_token (cur_token.code); |
5828 | ||
5829 | return (intel_e09 () && intel_e06_1 ()); | |
5830 | } | |
4a1805b1 | 5831 | |
64a0c779 | 5832 | /* e06' Empty */ |
4a1805b1 | 5833 | else |
64a0c779 DN |
5834 | return 1; |
5835 | } | |
5836 | ||
64a0c779 | 5837 | /* e09 OFFSET e10 e09' |
b77a7acd | 5838 | | e10 e09' |
64a0c779 | 5839 | |
9306ca4a JB |
5840 | e09 ~ e10 e09' |
5841 | | NOT e10 e09' | |
5842 | | e10 e09' | |
5843 | ||
64a0c779 | 5844 | e09' PTR e10 e09' |
b77a7acd | 5845 | | : e10 e09' |
64a0c779 DN |
5846 | | Empty */ |
5847 | static int | |
5848 | intel_e09 () | |
5849 | { | |
5850 | /* e09 OFFSET e10 e09' */ | |
5851 | if (cur_token.code == T_OFFSET) | |
5852 | { | |
5853 | intel_parser.is_mem = 0; | |
9306ca4a | 5854 | intel_parser.op_modifier = T_OFFSET; |
64a0c779 DN |
5855 | intel_match_token (T_OFFSET); |
5856 | ||
5857 | return (intel_e10 () && intel_e09_1 ()); | |
5858 | } | |
5859 | ||
9306ca4a JB |
5860 | /* e09 NOT e10 e09' */ |
5861 | else if (cur_token.code == '~') | |
5862 | { | |
5863 | char str[2]; | |
5864 | ||
5865 | str[0] = cur_token.code; | |
5866 | str[1] = 0; | |
5867 | strcat (intel_parser.disp, str); | |
5868 | intel_match_token (cur_token.code); | |
5869 | ||
5870 | return (intel_e10 () && intel_e09_1 ()); | |
5871 | } | |
5872 | ||
64a0c779 DN |
5873 | /* e09 e10 e09' */ |
5874 | else | |
5875 | return (intel_e10 () && intel_e09_1 ()); | |
5876 | } | |
5877 | ||
5878 | static int | |
5879 | intel_e09_1 () | |
5880 | { | |
5881 | /* e09' PTR e10 e09' */ | |
5882 | if (cur_token.code == T_PTR) | |
5883 | { | |
9306ca4a JB |
5884 | char suffix; |
5885 | ||
64a0c779 | 5886 | if (prev_token.code == T_BYTE) |
9306ca4a | 5887 | suffix = BYTE_MNEM_SUFFIX; |
64a0c779 DN |
5888 | |
5889 | else if (prev_token.code == T_WORD) | |
5890 | { | |
9306ca4a JB |
5891 | if (current_templates->start->name[0] == 'l' |
5892 | && current_templates->start->name[2] == 's' | |
5893 | && current_templates->start->name[3] == 0) | |
5894 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ | |
5895 | else if (intel_parser.got_a_float == 2) /* "fi..." */ | |
5896 | suffix = SHORT_MNEM_SUFFIX; | |
64a0c779 | 5897 | else |
9306ca4a | 5898 | suffix = WORD_MNEM_SUFFIX; |
64a0c779 DN |
5899 | } |
5900 | ||
5901 | else if (prev_token.code == T_DWORD) | |
5902 | { | |
9306ca4a JB |
5903 | if (current_templates->start->name[0] == 'l' |
5904 | && current_templates->start->name[2] == 's' | |
5905 | && current_templates->start->name[3] == 0) | |
5906 | suffix = WORD_MNEM_SUFFIX; | |
5907 | else if (flag_code == CODE_16BIT | |
5908 | && (current_templates->start->opcode_modifier | |
5909 | & (Jump|JumpDword|JumpInterSegment))) | |
5910 | suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
5911 | else if (intel_parser.got_a_float == 1) /* "f..." */ | |
5912 | suffix = SHORT_MNEM_SUFFIX; | |
64a0c779 | 5913 | else |
9306ca4a JB |
5914 | suffix = LONG_MNEM_SUFFIX; |
5915 | } | |
5916 | ||
5917 | else if (prev_token.code == T_FWORD) | |
5918 | { | |
5919 | if (current_templates->start->name[0] == 'l' | |
5920 | && current_templates->start->name[2] == 's' | |
5921 | && current_templates->start->name[3] == 0) | |
5922 | suffix = LONG_MNEM_SUFFIX; | |
5923 | else if (!intel_parser.got_a_float) | |
5924 | { | |
5925 | if (flag_code == CODE_16BIT) | |
5926 | add_prefix (DATA_PREFIX_OPCODE); | |
5927 | suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
5928 | } | |
5929 | else | |
5930 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ | |
64a0c779 DN |
5931 | } |
5932 | ||
5933 | else if (prev_token.code == T_QWORD) | |
f16b83df JH |
5934 | { |
5935 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
9306ca4a | 5936 | suffix = LONG_MNEM_SUFFIX; |
f16b83df | 5937 | else |
9306ca4a | 5938 | suffix = QWORD_MNEM_SUFFIX; |
f16b83df | 5939 | } |
64a0c779 | 5940 | |
9306ca4a JB |
5941 | else if (prev_token.code == T_TBYTE) |
5942 | { | |
5943 | if (intel_parser.got_a_float == 1) | |
5944 | suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
5945 | else | |
5946 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ | |
5947 | } | |
5948 | ||
5949 | else if (prev_token.code == T_XMMWORD) | |
5950 | { | |
5951 | /* XXX ignored for now, but accepted since gcc uses it */ | |
5952 | suffix = 0; | |
5953 | } | |
64a0c779 DN |
5954 | |
5955 | else | |
5956 | { | |
0477af35 | 5957 | as_bad (_("Unknown operand modifier `%s'"), prev_token.str); |
64a0c779 DN |
5958 | return 0; |
5959 | } | |
5960 | ||
9306ca4a JB |
5961 | if (current_templates->start->base_opcode == 0x8d /* lea */) |
5962 | ; | |
5963 | else if (!i.suffix) | |
5964 | i.suffix = suffix; | |
5965 | else if (i.suffix != suffix) | |
5966 | { | |
5967 | as_bad (_("Conflicting operand modifiers")); | |
5968 | return 0; | |
5969 | } | |
5970 | ||
64a0c779 DN |
5971 | intel_match_token (T_PTR); |
5972 | ||
5973 | return (intel_e10 () && intel_e09_1 ()); | |
5974 | } | |
5975 | ||
5976 | /* e09 : e10 e09' */ | |
5977 | else if (cur_token.code == ':') | |
5978 | { | |
21d6c4af DN |
5979 | /* Mark as a memory operand only if it's not already known to be an |
5980 | offset expression. */ | |
9306ca4a | 5981 | if (intel_parser.op_modifier != T_OFFSET) |
21d6c4af | 5982 | intel_parser.is_mem = 1; |
64a0c779 DN |
5983 | |
5984 | return (intel_match_token (':') && intel_e10 () && intel_e09_1 ()); | |
5985 | } | |
5986 | ||
5987 | /* e09' Empty */ | |
5988 | else | |
5989 | return 1; | |
5990 | } | |
5991 | ||
5992 | /* e10 e11 e10' | |
5993 | ||
5994 | e10' [ expr ] e10' | |
b77a7acd | 5995 | | Empty */ |
64a0c779 DN |
5996 | static int |
5997 | intel_e10 () | |
5998 | { | |
5999 | return (intel_e11 () && intel_e10_1 ()); | |
6000 | } | |
6001 | ||
6002 | static int | |
6003 | intel_e10_1 () | |
6004 | { | |
6005 | /* e10' [ expr ] e10' */ | |
6006 | if (cur_token.code == '[') | |
6007 | { | |
6008 | intel_match_token ('['); | |
21d6c4af DN |
6009 | |
6010 | /* Mark as a memory operand only if it's not already known to be an | |
6011 | offset expression. If it's an offset expression, we need to keep | |
6012 | the brace in. */ | |
9306ca4a | 6013 | if (intel_parser.op_modifier != T_OFFSET) |
21d6c4af DN |
6014 | intel_parser.is_mem = 1; |
6015 | else | |
6016 | strcat (intel_parser.disp, "["); | |
4a1805b1 | 6017 | |
64a0c779 | 6018 | /* Add a '+' to the displacement string if necessary. */ |
21d6c4af DN |
6019 | if (*intel_parser.disp != '\0' |
6020 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
64a0c779 DN |
6021 | strcat (intel_parser.disp, "+"); |
6022 | ||
21d6c4af DN |
6023 | if (intel_expr () && intel_match_token (']')) |
6024 | { | |
6025 | /* Preserve brackets when the operand is an offset expression. */ | |
9306ca4a | 6026 | if (intel_parser.op_modifier == T_OFFSET) |
21d6c4af DN |
6027 | strcat (intel_parser.disp, "]"); |
6028 | ||
6029 | return intel_e10_1 (); | |
6030 | } | |
6031 | else | |
6032 | return 0; | |
64a0c779 DN |
6033 | } |
6034 | ||
6035 | /* e10' Empty */ | |
6036 | else | |
6037 | return 1; | |
6038 | } | |
6039 | ||
64a0c779 | 6040 | /* e11 ( expr ) |
b77a7acd | 6041 | | [ expr ] |
64a0c779 DN |
6042 | | BYTE |
6043 | | WORD | |
6044 | | DWORD | |
9306ca4a | 6045 | | FWORD |
64a0c779 | 6046 | | QWORD |
9306ca4a JB |
6047 | | TBYTE |
6048 | | OWORD | |
6049 | | XMMWORD | |
4a1805b1 | 6050 | | $ |
64a0c779 DN |
6051 | | . |
6052 | | register | |
6053 | | id | |
6054 | | constant */ | |
6055 | static int | |
6056 | intel_e11 () | |
6057 | { | |
6058 | /* e11 ( expr ) */ | |
6059 | if (cur_token.code == '(') | |
6060 | { | |
6061 | intel_match_token ('('); | |
6062 | strcat (intel_parser.disp, "("); | |
6063 | ||
6064 | if (intel_expr () && intel_match_token (')')) | |
e5cb08ac KH |
6065 | { |
6066 | strcat (intel_parser.disp, ")"); | |
6067 | return 1; | |
6068 | } | |
64a0c779 DN |
6069 | else |
6070 | return 0; | |
6071 | } | |
6072 | ||
6073 | /* e11 [ expr ] */ | |
6074 | else if (cur_token.code == '[') | |
6075 | { | |
6076 | intel_match_token ('['); | |
21d6c4af DN |
6077 | |
6078 | /* Mark as a memory operand only if it's not already known to be an | |
6079 | offset expression. If it's an offset expression, we need to keep | |
6080 | the brace in. */ | |
9306ca4a | 6081 | if (intel_parser.op_modifier != T_OFFSET) |
21d6c4af DN |
6082 | intel_parser.is_mem = 1; |
6083 | else | |
6084 | strcat (intel_parser.disp, "["); | |
4a1805b1 | 6085 | |
64a0c779 | 6086 | /* Operands for jump/call inside brackets denote absolute addresses. */ |
9306ca4a JB |
6087 | if (current_templates->start->opcode_modifier |
6088 | & (Jump|JumpDword|JumpByte|JumpInterSegment)) | |
64a0c779 DN |
6089 | i.types[this_operand] |= JumpAbsolute; |
6090 | ||
6091 | /* Add a '+' to the displacement string if necessary. */ | |
21d6c4af DN |
6092 | if (*intel_parser.disp != '\0' |
6093 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
64a0c779 DN |
6094 | strcat (intel_parser.disp, "+"); |
6095 | ||
21d6c4af DN |
6096 | if (intel_expr () && intel_match_token (']')) |
6097 | { | |
6098 | /* Preserve brackets when the operand is an offset expression. */ | |
9306ca4a | 6099 | if (intel_parser.op_modifier == T_OFFSET) |
21d6c4af DN |
6100 | strcat (intel_parser.disp, "]"); |
6101 | ||
6102 | return 1; | |
6103 | } | |
6104 | else | |
6105 | return 0; | |
64a0c779 DN |
6106 | } |
6107 | ||
4a1805b1 | 6108 | /* e11 BYTE |
64a0c779 DN |
6109 | | WORD |
6110 | | DWORD | |
9306ca4a | 6111 | | FWORD |
64a0c779 | 6112 | | QWORD |
9306ca4a JB |
6113 | | TBYTE |
6114 | | OWORD | |
6115 | | XMMWORD */ | |
64a0c779 DN |
6116 | else if (cur_token.code == T_BYTE |
6117 | || cur_token.code == T_WORD | |
6118 | || cur_token.code == T_DWORD | |
9306ca4a | 6119 | || cur_token.code == T_FWORD |
64a0c779 | 6120 | || cur_token.code == T_QWORD |
9306ca4a JB |
6121 | || cur_token.code == T_TBYTE |
6122 | || cur_token.code == T_XMMWORD) | |
64a0c779 DN |
6123 | { |
6124 | intel_match_token (cur_token.code); | |
6125 | ||
6126 | return 1; | |
6127 | } | |
6128 | ||
6129 | /* e11 $ | |
6130 | | . */ | |
9306ca4a | 6131 | else if (cur_token.code == '.') |
64a0c779 DN |
6132 | { |
6133 | strcat (intel_parser.disp, cur_token.str); | |
6134 | intel_match_token (cur_token.code); | |
21d6c4af DN |
6135 | |
6136 | /* Mark as a memory operand only if it's not already known to be an | |
6137 | offset expression. */ | |
9306ca4a | 6138 | if (intel_parser.op_modifier != T_OFFSET) |
21d6c4af | 6139 | intel_parser.is_mem = 1; |
64a0c779 DN |
6140 | |
6141 | return 1; | |
6142 | } | |
6143 | ||
6144 | /* e11 register */ | |
6145 | else if (cur_token.code == T_REG) | |
6146 | { | |
6147 | const reg_entry *reg = intel_parser.reg = cur_token.reg; | |
6148 | ||
6149 | intel_match_token (T_REG); | |
6150 | ||
6151 | /* Check for segment change. */ | |
6152 | if (cur_token.code == ':') | |
6153 | { | |
6154 | if (reg->reg_type & (SReg2 | SReg3)) | |
6155 | { | |
6156 | switch (reg->reg_num) | |
6157 | { | |
6158 | case 0: | |
6159 | i.seg[i.mem_operands] = &es; | |
6160 | break; | |
6161 | case 1: | |
6162 | i.seg[i.mem_operands] = &cs; | |
6163 | break; | |
6164 | case 2: | |
6165 | i.seg[i.mem_operands] = &ss; | |
6166 | break; | |
6167 | case 3: | |
6168 | i.seg[i.mem_operands] = &ds; | |
6169 | break; | |
6170 | case 4: | |
6171 | i.seg[i.mem_operands] = &fs; | |
6172 | break; | |
6173 | case 5: | |
6174 | i.seg[i.mem_operands] = &gs; | |
6175 | break; | |
6176 | } | |
6177 | } | |
6178 | else | |
6179 | { | |
6180 | as_bad (_("`%s' is not a valid segment register"), reg->reg_name); | |
6181 | return 0; | |
6182 | } | |
6183 | } | |
6184 | ||
6185 | /* Not a segment register. Check for register scaling. */ | |
6186 | else if (cur_token.code == '*') | |
6187 | { | |
6188 | if (!intel_parser.is_mem) | |
6189 | { | |
6190 | as_bad (_("Register scaling only allowed in memory operands.")); | |
6191 | return 0; | |
6192 | } | |
6193 | ||
4a1805b1 | 6194 | /* What follows must be a valid scale. */ |
64a0c779 DN |
6195 | if (intel_match_token ('*') |
6196 | && strchr ("01248", *cur_token.str)) | |
6197 | { | |
6198 | i.index_reg = reg; | |
6199 | i.types[this_operand] |= BaseIndex; | |
6200 | ||
6201 | /* Set the scale after setting the register (otherwise, | |
6202 | i386_scale will complain) */ | |
6203 | i386_scale (cur_token.str); | |
6204 | intel_match_token (T_CONST); | |
6205 | } | |
6206 | else | |
6207 | { | |
6208 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
6209 | cur_token.str); | |
6210 | return 0; | |
6211 | } | |
6212 | } | |
6213 | ||
6214 | /* No scaling. If this is a memory operand, the register is either a | |
6215 | base register (first occurrence) or an index register (second | |
6216 | occurrence). */ | |
6217 | else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3))) | |
6218 | { | |
6219 | if (i.base_reg && i.index_reg) | |
6220 | { | |
0477af35 | 6221 | as_bad (_("Too many register references in memory operand.")); |
64a0c779 DN |
6222 | return 0; |
6223 | } | |
6224 | ||
6225 | if (i.base_reg == NULL) | |
6226 | i.base_reg = reg; | |
6227 | else | |
6228 | i.index_reg = reg; | |
6229 | ||
6230 | i.types[this_operand] |= BaseIndex; | |
6231 | } | |
6232 | ||
6233 | /* Offset modifier. Add the register to the displacement string to be | |
6234 | parsed as an immediate expression after we're done. */ | |
9306ca4a | 6235 | else if (intel_parser.op_modifier == T_OFFSET) |
64a0c779 | 6236 | strcat (intel_parser.disp, reg->reg_name); |
4a1805b1 | 6237 | |
64a0c779 DN |
6238 | /* It's neither base nor index nor offset. */ |
6239 | else | |
6240 | { | |
6241 | i.types[this_operand] |= reg->reg_type & ~BaseIndex; | |
6242 | i.op[this_operand].regs = reg; | |
6243 | i.reg_operands++; | |
6244 | } | |
6245 | ||
6246 | /* Since registers are not part of the displacement string (except | |
6247 | when we're parsing offset operands), we may need to remove any | |
6248 | preceding '+' from the displacement string. */ | |
6249 | if (*intel_parser.disp != '\0' | |
9306ca4a | 6250 | && intel_parser.op_modifier != T_OFFSET) |
64a0c779 DN |
6251 | { |
6252 | char *s = intel_parser.disp; | |
6253 | s += strlen (s) - 1; | |
6254 | if (*s == '+') | |
6255 | *s = '\0'; | |
6256 | } | |
6257 | ||
6258 | return 1; | |
6259 | } | |
4a1805b1 | 6260 | |
64a0c779 DN |
6261 | /* e11 id */ |
6262 | else if (cur_token.code == T_ID) | |
6263 | { | |
6264 | /* Add the identifier to the displacement string. */ | |
6265 | strcat (intel_parser.disp, cur_token.str); | |
64a0c779 DN |
6266 | |
6267 | /* The identifier represents a memory reference only if it's not | |
9306ca4a JB |
6268 | preceded by an offset modifier and if it's not an equate. */ |
6269 | if (intel_parser.op_modifier != T_OFFSET) | |
6270 | { | |
6271 | symbolS *symbolP; | |
6272 | ||
6273 | symbolP = symbol_find(cur_token.str); | |
6274 | if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section) | |
6275 | intel_parser.is_mem = 1; | |
6276 | } | |
64a0c779 | 6277 | |
9306ca4a | 6278 | intel_match_token (T_ID); |
64a0c779 DN |
6279 | return 1; |
6280 | } | |
6281 | ||
6282 | /* e11 constant */ | |
6283 | else if (cur_token.code == T_CONST | |
e5cb08ac | 6284 | || cur_token.code == '-' |
64a0c779 DN |
6285 | || cur_token.code == '+') |
6286 | { | |
6287 | char *save_str; | |
6288 | ||
6289 | /* Allow constants that start with `+' or `-'. */ | |
6290 | if (cur_token.code == '-' || cur_token.code == '+') | |
6291 | { | |
6292 | strcat (intel_parser.disp, cur_token.str); | |
6293 | intel_match_token (cur_token.code); | |
6294 | if (cur_token.code != T_CONST) | |
6295 | { | |
0477af35 | 6296 | as_bad (_("Syntax error. Expecting a constant. Got `%s'."), |
64a0c779 DN |
6297 | cur_token.str); |
6298 | return 0; | |
6299 | } | |
6300 | } | |
6301 | ||
e5cb08ac | 6302 | save_str = (char *) malloc (strlen (cur_token.str) + 1); |
64a0c779 | 6303 | if (save_str == NULL) |
bc805888 | 6304 | abort (); |
64a0c779 DN |
6305 | strcpy (save_str, cur_token.str); |
6306 | ||
6307 | /* Get the next token to check for register scaling. */ | |
6308 | intel_match_token (cur_token.code); | |
6309 | ||
6310 | /* Check if this constant is a scaling factor for an index register. */ | |
6311 | if (cur_token.code == '*') | |
6312 | { | |
6313 | if (intel_match_token ('*') && cur_token.code == T_REG) | |
6314 | { | |
6315 | if (!intel_parser.is_mem) | |
6316 | { | |
6317 | as_bad (_("Register scaling only allowed in memory operands.")); | |
6318 | return 0; | |
6319 | } | |
6320 | ||
4a1805b1 | 6321 | /* The constant is followed by `* reg', so it must be |
64a0c779 DN |
6322 | a valid scale. */ |
6323 | if (strchr ("01248", *save_str)) | |
6324 | { | |
6325 | i.index_reg = cur_token.reg; | |
6326 | i.types[this_operand] |= BaseIndex; | |
6327 | ||
6328 | /* Set the scale after setting the register (otherwise, | |
6329 | i386_scale will complain) */ | |
6330 | i386_scale (save_str); | |
6331 | intel_match_token (T_REG); | |
6332 | ||
6333 | /* Since registers are not part of the displacement | |
6334 | string, we may need to remove any preceding '+' from | |
6335 | the displacement string. */ | |
6336 | if (*intel_parser.disp != '\0') | |
6337 | { | |
6338 | char *s = intel_parser.disp; | |
6339 | s += strlen (s) - 1; | |
6340 | if (*s == '+') | |
6341 | *s = '\0'; | |
6342 | } | |
6343 | ||
6344 | free (save_str); | |
6345 | ||
6346 | return 1; | |
6347 | } | |
6348 | else | |
6349 | return 0; | |
6350 | } | |
6351 | ||
6352 | /* The constant was not used for register scaling. Since we have | |
6353 | already consumed the token following `*' we now need to put it | |
6354 | back in the stream. */ | |
6355 | else | |
6356 | intel_putback_token (); | |
6357 | } | |
6358 | ||
6359 | /* Add the constant to the displacement string. */ | |
6360 | strcat (intel_parser.disp, save_str); | |
6361 | free (save_str); | |
6362 | ||
6363 | return 1; | |
6364 | } | |
6365 | ||
64a0c779 DN |
6366 | as_bad (_("Unrecognized token '%s'"), cur_token.str); |
6367 | return 0; | |
6368 | } | |
6369 | ||
64a0c779 DN |
6370 | /* Match the given token against cur_token. If they match, read the next |
6371 | token from the operand string. */ | |
6372 | static int | |
6373 | intel_match_token (code) | |
e5cb08ac | 6374 | int code; |
64a0c779 DN |
6375 | { |
6376 | if (cur_token.code == code) | |
6377 | { | |
6378 | intel_get_token (); | |
6379 | return 1; | |
6380 | } | |
6381 | else | |
6382 | { | |
0477af35 | 6383 | as_bad (_("Unexpected token `%s'"), cur_token.str); |
64a0c779 DN |
6384 | return 0; |
6385 | } | |
6386 | } | |
6387 | ||
64a0c779 DN |
6388 | /* Read a new token from intel_parser.op_string and store it in cur_token. */ |
6389 | static void | |
6390 | intel_get_token () | |
6391 | { | |
6392 | char *end_op; | |
6393 | const reg_entry *reg; | |
6394 | struct intel_token new_token; | |
6395 | ||
6396 | new_token.code = T_NIL; | |
6397 | new_token.reg = NULL; | |
6398 | new_token.str = NULL; | |
6399 | ||
4a1805b1 | 6400 | /* Free the memory allocated to the previous token and move |
64a0c779 DN |
6401 | cur_token to prev_token. */ |
6402 | if (prev_token.str) | |
6403 | free (prev_token.str); | |
6404 | ||
6405 | prev_token = cur_token; | |
6406 | ||
6407 | /* Skip whitespace. */ | |
6408 | while (is_space_char (*intel_parser.op_string)) | |
6409 | intel_parser.op_string++; | |
6410 | ||
6411 | /* Return an empty token if we find nothing else on the line. */ | |
6412 | if (*intel_parser.op_string == '\0') | |
6413 | { | |
6414 | cur_token = new_token; | |
6415 | return; | |
6416 | } | |
6417 | ||
6418 | /* The new token cannot be larger than the remainder of the operand | |
6419 | string. */ | |
e5cb08ac | 6420 | new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1); |
64a0c779 | 6421 | if (new_token.str == NULL) |
bc805888 | 6422 | abort (); |
64a0c779 DN |
6423 | new_token.str[0] = '\0'; |
6424 | ||
6425 | if (strchr ("0123456789", *intel_parser.op_string)) | |
6426 | { | |
6427 | char *p = new_token.str; | |
6428 | char *q = intel_parser.op_string; | |
6429 | new_token.code = T_CONST; | |
6430 | ||
6431 | /* Allow any kind of identifier char to encompass floating point and | |
6432 | hexadecimal numbers. */ | |
6433 | while (is_identifier_char (*q)) | |
6434 | *p++ = *q++; | |
6435 | *p = '\0'; | |
6436 | ||
6437 | /* Recognize special symbol names [0-9][bf]. */ | |
6438 | if (strlen (intel_parser.op_string) == 2 | |
4a1805b1 | 6439 | && (intel_parser.op_string[1] == 'b' |
64a0c779 DN |
6440 | || intel_parser.op_string[1] == 'f')) |
6441 | new_token.code = T_ID; | |
6442 | } | |
6443 | ||
64a0c779 DN |
6444 | else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg) |
6445 | && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)) | |
6446 | { | |
6447 | new_token.code = T_REG; | |
6448 | new_token.reg = reg; | |
6449 | ||
6450 | if (*intel_parser.op_string == REGISTER_PREFIX) | |
6451 | { | |
6452 | new_token.str[0] = REGISTER_PREFIX; | |
6453 | new_token.str[1] = '\0'; | |
6454 | } | |
6455 | ||
6456 | strcat (new_token.str, reg->reg_name); | |
6457 | } | |
6458 | ||
6459 | else if (is_identifier_char (*intel_parser.op_string)) | |
6460 | { | |
6461 | char *p = new_token.str; | |
6462 | char *q = intel_parser.op_string; | |
6463 | ||
6464 | /* A '.' or '$' followed by an identifier char is an identifier. | |
6465 | Otherwise, it's operator '.' followed by an expression. */ | |
6466 | if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) | |
6467 | { | |
9306ca4a JB |
6468 | new_token.code = '.'; |
6469 | new_token.str[0] = '.'; | |
64a0c779 DN |
6470 | new_token.str[1] = '\0'; |
6471 | } | |
6472 | else | |
6473 | { | |
6474 | while (is_identifier_char (*q) || *q == '@') | |
6475 | *p++ = *q++; | |
6476 | *p = '\0'; | |
6477 | ||
9306ca4a JB |
6478 | if (strcasecmp (new_token.str, "NOT") == 0) |
6479 | new_token.code = '~'; | |
6480 | ||
6481 | else if (strcasecmp (new_token.str, "MOD") == 0) | |
6482 | new_token.code = '%'; | |
6483 | ||
6484 | else if (strcasecmp (new_token.str, "AND") == 0) | |
6485 | new_token.code = '&'; | |
6486 | ||
6487 | else if (strcasecmp (new_token.str, "OR") == 0) | |
6488 | new_token.code = '|'; | |
6489 | ||
6490 | else if (strcasecmp (new_token.str, "XOR") == 0) | |
6491 | new_token.code = '^'; | |
6492 | ||
6493 | else if (strcasecmp (new_token.str, "SHL") == 0) | |
6494 | new_token.code = T_SHL; | |
6495 | ||
6496 | else if (strcasecmp (new_token.str, "SHR") == 0) | |
6497 | new_token.code = T_SHR; | |
6498 | ||
6499 | else if (strcasecmp (new_token.str, "BYTE") == 0) | |
64a0c779 DN |
6500 | new_token.code = T_BYTE; |
6501 | ||
6502 | else if (strcasecmp (new_token.str, "WORD") == 0) | |
6503 | new_token.code = T_WORD; | |
6504 | ||
6505 | else if (strcasecmp (new_token.str, "DWORD") == 0) | |
6506 | new_token.code = T_DWORD; | |
6507 | ||
9306ca4a JB |
6508 | else if (strcasecmp (new_token.str, "FWORD") == 0) |
6509 | new_token.code = T_FWORD; | |
6510 | ||
64a0c779 DN |
6511 | else if (strcasecmp (new_token.str, "QWORD") == 0) |
6512 | new_token.code = T_QWORD; | |
6513 | ||
9306ca4a JB |
6514 | else if (strcasecmp (new_token.str, "TBYTE") == 0 |
6515 | /* XXX remove (gcc still uses it) */ | |
6516 | || strcasecmp (new_token.str, "XWORD") == 0) | |
6517 | new_token.code = T_TBYTE; | |
6518 | ||
6519 | else if (strcasecmp (new_token.str, "XMMWORD") == 0 | |
6520 | || strcasecmp (new_token.str, "OWORD") == 0) | |
6521 | new_token.code = T_XMMWORD; | |
64a0c779 DN |
6522 | |
6523 | else if (strcasecmp (new_token.str, "PTR") == 0) | |
6524 | new_token.code = T_PTR; | |
6525 | ||
6526 | else if (strcasecmp (new_token.str, "SHORT") == 0) | |
6527 | new_token.code = T_SHORT; | |
6528 | ||
6529 | else if (strcasecmp (new_token.str, "OFFSET") == 0) | |
6530 | { | |
6531 | new_token.code = T_OFFSET; | |
6532 | ||
6533 | /* ??? This is not mentioned in the MASM grammar but gcc | |
6534 | makes use of it with -mintel-syntax. OFFSET may be | |
6535 | followed by FLAT: */ | |
6536 | if (strncasecmp (q, " FLAT:", 6) == 0) | |
6537 | strcat (new_token.str, " FLAT:"); | |
6538 | } | |
6539 | ||
6540 | /* ??? This is not mentioned in the MASM grammar. */ | |
6541 | else if (strcasecmp (new_token.str, "FLAT") == 0) | |
6542 | new_token.code = T_OFFSET; | |
6543 | ||
6544 | else | |
6545 | new_token.code = T_ID; | |
6546 | } | |
6547 | } | |
6548 | ||
9306ca4a JB |
6549 | else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string)) |
6550 | { | |
6551 | new_token.code = *intel_parser.op_string; | |
6552 | new_token.str[0] = *intel_parser.op_string; | |
6553 | new_token.str[1] = '\0'; | |
6554 | } | |
6555 | ||
6556 | else if (strchr ("<>", *intel_parser.op_string) | |
6557 | && *intel_parser.op_string == *(intel_parser.op_string + 1)) | |
6558 | { | |
6559 | new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR; | |
6560 | new_token.str[0] = *intel_parser.op_string; | |
6561 | new_token.str[1] = *intel_parser.op_string; | |
6562 | new_token.str[2] = '\0'; | |
6563 | } | |
6564 | ||
64a0c779 | 6565 | else |
0477af35 | 6566 | as_bad (_("Unrecognized token `%s'"), intel_parser.op_string); |
64a0c779 DN |
6567 | |
6568 | intel_parser.op_string += strlen (new_token.str); | |
6569 | cur_token = new_token; | |
6570 | } | |
6571 | ||
64a0c779 DN |
6572 | /* Put cur_token back into the token stream and make cur_token point to |
6573 | prev_token. */ | |
6574 | static void | |
6575 | intel_putback_token () | |
6576 | { | |
6577 | intel_parser.op_string -= strlen (cur_token.str); | |
6578 | free (cur_token.str); | |
6579 | cur_token = prev_token; | |
4a1805b1 | 6580 | |
64a0c779 DN |
6581 | /* Forget prev_token. */ |
6582 | prev_token.code = T_NIL; | |
6583 | prev_token.reg = NULL; | |
6584 | prev_token.str = NULL; | |
6585 | } | |
54cfded0 | 6586 | |
a4447b93 | 6587 | int |
54cfded0 AM |
6588 | tc_x86_regname_to_dw2regnum (const char *regname) |
6589 | { | |
6590 | unsigned int regnum; | |
6591 | unsigned int regnames_count; | |
6592 | char *regnames_32[] = | |
6593 | { | |
a4447b93 RH |
6594 | "eax", "ecx", "edx", "ebx", |
6595 | "esp", "ebp", "esi", "edi", | |
54cfded0 AM |
6596 | "eip" |
6597 | }; | |
6598 | char *regnames_64[] = | |
6599 | { | |
6600 | "rax", "rbx", "rcx", "rdx", | |
6601 | "rdi", "rsi", "rbp", "rsp", | |
6602 | "r8", "r9", "r10", "r11", | |
6603 | "r12", "r13", "r14", "r15", | |
6604 | "rip" | |
6605 | }; | |
6606 | char **regnames; | |
6607 | ||
6608 | if (flag_code == CODE_64BIT) | |
6609 | { | |
6610 | regnames = regnames_64; | |
0cea6190 | 6611 | regnames_count = ARRAY_SIZE (regnames_64); |
54cfded0 AM |
6612 | } |
6613 | else | |
6614 | { | |
6615 | regnames = regnames_32; | |
0cea6190 | 6616 | regnames_count = ARRAY_SIZE (regnames_32); |
54cfded0 AM |
6617 | } |
6618 | ||
6619 | for (regnum = 0; regnum < regnames_count; regnum++) | |
6620 | if (strcmp (regname, regnames[regnum]) == 0) | |
6621 | return regnum; | |
6622 | ||
54cfded0 AM |
6623 | return -1; |
6624 | } | |
6625 | ||
6626 | void | |
6627 | tc_x86_frame_initial_instructions (void) | |
6628 | { | |
a4447b93 RH |
6629 | static unsigned int sp_regno; |
6630 | ||
6631 | if (!sp_regno) | |
6632 | sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT | |
6633 | ? "rsp" : "esp"); | |
6634 | ||
6635 | cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment); | |
6636 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 6637 | } |
d2b2c203 DJ |
6638 | |
6639 | int | |
6640 | i386_elf_section_type (const char *str, size_t len) | |
6641 | { | |
6642 | if (flag_code == CODE_64BIT | |
6643 | && len == sizeof ("unwind") - 1 | |
6644 | && strncmp (str, "unwind", 6) == 0) | |
6645 | return SHT_X86_64_UNWIND; | |
6646 | ||
6647 | return -1; | |
6648 | } | |
bb41ade5 AM |
6649 | |
6650 | #ifdef TE_PE | |
6651 | void | |
6652 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
6653 | { | |
6654 | expressionS expr; | |
6655 | ||
6656 | expr.X_op = O_secrel; | |
6657 | expr.X_add_symbol = symbol; | |
6658 | expr.X_add_number = 0; | |
6659 | emit_expr (&expr, size); | |
6660 | } | |
6661 | #endif |