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gas: sparc: fix relaxation of CALL instruction into branches in a.out targets
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
2571583a 2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
83b16ac6 176static const insn_template *match_template (char);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
a65babc9
L		 285 };
286
252b5132
RH		 287struct _i386_insn
288 {
47926f60 289 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 290 insn_template tm;
252b5132 291
7d5e4556
L		 292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
252b5132
RH		 294 char suffix;
295
47926f60 296 /* OPERANDS gives the number of given operands. */
252b5132
RH		 297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
47926f60 301 operands. */
252b5132
RH		 302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 305 use OP[i] for the corresponding operand. */
40fb9820 306 i386_operand_type types[MAX_OPERANDS];
252b5132 307
520dc8e8
AM		 308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
252b5132 311
3e73aa7c
JH		 312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314#define Operand_PCrel 1
315
252b5132 316 /* Relocation type for operand */
f86103b7 317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 318
252b5132
RH		 319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 326 explicit segment overrides are given. */
ce8a8b2f 327 const seg_entry *seg[2];
252b5132 328
8325cc63
JB		 329 /* Copied first memory operand string, for re-checking. */
330 char *memop1_string;
331
252b5132
RH		 332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes;
335 unsigned char prefix[MAX_PREFIXES];
336
337 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 338 addressing modes of this insn are encoded. */
252b5132 339 modrm_byte rm;
3e73aa7c 340 rex_byte rex;
43234a1e 341 rex_byte vrex;
252b5132 342 sib_byte sib;
c0f3af97 343 vex_prefix vex;
b6169b20 344
43234a1e
L		 345 /* Masking attributes. */
346 struct Mask_Operation *mask;
347
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation *rounding;
350
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation *broadcast;
353
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift;
356
86fa6981
L		 357 /* Prefer load or store in encoding. */
358 enum
359 {
360 dir_encoding_default = 0,
361 dir_encoding_load,
362 dir_encoding_store
363 } dir_encoding;
891edac4 364
a501d77e
L		 365 /* Prefer 8bit or 32bit displacement in encoding. */
366 enum
367 {
368 disp_encoding_default = 0,
369 disp_encoding_8bit,
370 disp_encoding_32bit
371 } disp_encoding;
f8a5c266 372
86fa6981
L		 373 /* How to encode vector instructions. */
374 enum
375 {
376 vex_encoding_default = 0,
377 vex_encoding_vex2,
378 vex_encoding_vex3,
379 vex_encoding_evex
380 } vec_encoding;
381
d5de92cf
L		 382 /* REP prefix. */
383 const char *rep_prefix;
384
165de32a
L		 385 /* HLE prefix. */
386 const char *hle_prefix;
42164a71 387
7e8b059b
L		 388 /* Have BND prefix. */
389 const char *bnd_prefix;
390
891edac4 391 /* Error message. */
a65babc9 392 enum i386_error error;
252b5132
RH		 393 };
394
395typedef struct _i386_insn i386_insn;
396
43234a1e
L		 397/* Link RC type with corresponding string, that'll be looked for in
398 asm. */
399struct RC_name
400{
401 enum rc_type type;
402 const char *name;
403 unsigned int len;
404};
405
406static const struct RC_name RC_NamesTable[] =
407{
408 { rne, STRING_COMMA_LEN ("rn-sae") },
409 { rd, STRING_COMMA_LEN ("rd-sae") },
410 { ru, STRING_COMMA_LEN ("ru-sae") },
411 { rz, STRING_COMMA_LEN ("rz-sae") },
412 { saeonly, STRING_COMMA_LEN ("sae") },
413};
414
252b5132
RH		 415/* List of chars besides those in app.c:symbol_chars that can start an
416 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 417const char extra_symbol_chars[] = "*%-([{}"
252b5132 418#ifdef LEX_AT
32137342
NC		 419 "@"
420#endif
421#ifdef LEX_QM
422 "?"
252b5132 423#endif
32137342 424 ;
252b5132 425
29b0f896
AM		 426#if (defined (TE_I386AIX) \
427 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 428 && !defined (TE_GNU) \
29b0f896 429 && !defined (TE_LINUX) \
8d63c93e
RM		 430 && !defined (TE_NACL) \
431 && !defined (TE_NETWARE) \
29b0f896 432 && !defined (TE_FreeBSD) \
5b806d27 433 && !defined (TE_DragonFly) \
29b0f896 434 && !defined (TE_NetBSD)))
252b5132 435/* This array holds the chars that always start a comment. If the
b3b91714
AM		 436 pre-processor is disabled, these aren't very useful. The option
437 --divide will remove '/' from this list. */
438const char *i386_comment_chars = "#/";
439#define SVR4_COMMENT_CHARS 1
252b5132 440#define PREFIX_SEPARATOR '\\'
252b5132 441
b3b91714
AM		 442#else
443const char *i386_comment_chars = "#";
444#define PREFIX_SEPARATOR '/'
445#endif
446
252b5132
RH		 447/* This array holds the chars that only start a comment at the beginning of
448 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 449 .line and .file directives will appear in the pre-processed output.
450 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 451 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 452 #NO_APP at the beginning of its output.
453 Also note that comments started like this one will always work if
252b5132 454 '/' isn't otherwise defined. */
b3b91714 455const char line_comment_chars[] = "#/";
252b5132 456
63a0b638 457const char line_separator_chars[] = ";";
252b5132 458
ce8a8b2f
AM		 459/* Chars that can be used to separate mant from exp in floating point
460 nums. */
252b5132
RH		 461const char EXP_CHARS[] = "eE";
462
ce8a8b2f
AM		 463/* Chars that mean this number is a floating point constant
464 As in 0f12.456
465 or 0d1.2345e12. */
252b5132
RH		 466const char FLT_CHARS[] = "fFdDxX";
467
ce8a8b2f 468/* Tables for lexical analysis. */
252b5132
RH		 469static char mnemonic_chars[256];
470static char register_chars[256];
471static char operand_chars[256];
472static char identifier_chars[256];
473static char digit_chars[256];
474
ce8a8b2f 475/* Lexical macros. */
252b5132
RH		 476#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
477#define is_operand_char(x) (operand_chars[(unsigned char) x])
478#define is_register_char(x) (register_chars[(unsigned char) x])
479#define is_space_char(x) ((x) == ' ')
480#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
481#define is_digit_char(x) (digit_chars[(unsigned char) x])
482
0234cb7c 483/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 484static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
485
486/* md_assemble() always leaves the strings it's passed unaltered. To
487 effect this we maintain a stack of saved characters that we've smashed
488 with '\0's (indicating end of strings for various sub-fields of the
47926f60 489 assembler instruction). */
252b5132 490static char save_stack[32];
ce8a8b2f 491static char *save_stack_p;
252b5132
RH		 492#define END_STRING_AND_SAVE(s) \
493 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
494#define RESTORE_END_STRING(s) \
495 do { *(s) = *--save_stack_p; } while (0)
496
47926f60 497/* The instruction we're assembling. */
252b5132
RH		 498static i386_insn i;
499
500/* Possible templates for current insn. */
501static const templates *current_templates;
502
31b2323c
L		 503/* Per instruction expressionS buffers: max displacements & immediates. */
504static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
505static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 506
47926f60 507/* Current operand we are working on. */
ee86248c 508static int this_operand = -1;
252b5132 509
3e73aa7c
JH		 510/* We support four different modes. FLAG_CODE variable is used to distinguish
511 these. */
512
513enum flag_code {
514 CODE_32BIT,
515 CODE_16BIT,
516 CODE_64BIT };
517
518static enum flag_code flag_code;
4fa24527 519static unsigned int object_64bit;
862be3fb 520static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 521static int use_rela_relocations = 0;
522
7af8ed2d
NC		 523#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
524 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
525 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
526
351f65ca
L		 527/* The ELF ABI to use. */
528enum x86_elf_abi
529{
530 I386_ABI,
7f56bc95
L		 531 X86_64_ABI,
532 X86_64_X32_ABI
351f65ca
L		 533};
534
535static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 536#endif
351f65ca 537
167ad85b
TG		 538#if defined (TE_PE) || defined (TE_PEP)
539/* Use big object file format. */
540static int use_big_obj = 0;
541#endif
542
8dcea932
L		 543#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
544/* 1 if generating code for a shared library. */
545static int shared = 0;
546#endif
547
47926f60
KH		 548/* 1 for intel syntax,
549 0 if att syntax. */
550static int intel_syntax = 0;
252b5132 551
e89c5eaa
L		 552/* 1 for Intel64 ISA,
553 0 if AMD64 ISA. */
554static int intel64;
555
1efbbeb4
L		 556/* 1 for intel mnemonic,
557 0 if att mnemonic. */
558static int intel_mnemonic = !SYSV386_COMPAT;
559
5209009a 560/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 561static int old_gcc = OLDGCC_COMPAT;
562
a60de03c
JB		 563/* 1 if pseudo registers are permitted. */
564static int allow_pseudo_reg = 0;
565
47926f60
KH		 566/* 1 if register prefix % not required. */
567static int allow_naked_reg = 0;
252b5132 568
33eaf5de 569/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 570 instructions supporting it, even if this prefix wasn't specified
571 explicitly. */
572static int add_bnd_prefix = 0;
573
ba104c83 574/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 575static int allow_index_reg = 0;
576
d022bddd
IT		 577/* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579static int omit_lock_prefix = 0;
580
e4e00185
AS		 581/* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583static int avoid_fence = 0;
584
0cb4071e
L		 585/* 1 if the assembler should generate relax relocations. */
586
587static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
589
7bab8ab5 590static enum check_kind
daf50ae7 591 {
7bab8ab5
JB		 592 check_none = 0,
593 check_warning,
594 check_error
daf50ae7 595 }
7bab8ab5 596sse_check, operand_check = check_warning;
daf50ae7 597
2ca3ace5
L		 598/* Register prefix used for error message. */
599static const char *register_prefix = "%";
600
47926f60
KH		 601/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
602 leave, push, and pop instructions so that gcc has the same stack
603 frame as in 32 bit mode. */
604static char stackop_size = '\0';
eecb386c 605
12b55ccc
L		 606/* Non-zero to optimize code alignment. */
607int optimize_align_code = 1;
608
47926f60
KH		 609/* Non-zero to quieten some warnings. */
610static int quiet_warnings = 0;
a38cf1db 611
47926f60
KH		 612/* CPU name. */
613static const char *cpu_arch_name = NULL;
6305a203 614static char *cpu_sub_arch_name = NULL;
a38cf1db 615
47926f60 616/* CPU feature flags. */
40fb9820
L		 617static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
618
ccc9c027
L		 619/* If we have selected a cpu we are generating instructions for. */
620static int cpu_arch_tune_set = 0;
621
9103f4f4 622/* Cpu we are generating instructions for. */
fbf3f584 623enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 624
625/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 626static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 627
ccc9c027 628/* CPU instruction set architecture used. */
fbf3f584 629enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 630
9103f4f4 631/* CPU feature flags of instruction set architecture used. */
fbf3f584 632i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 633
fddf5b5b
AM		 634/* If set, conditional jumps are not automatically promoted to handle
635 larger than a byte offset. */
636static unsigned int no_cond_jump_promotion = 0;
637
c0f3af97
L		 638/* Encode SSE instructions with VEX prefix. */
639static unsigned int sse2avx;
640
539f890d
L		 641/* Encode scalar AVX instructions with specific vector length. */
642static enum
643 {
644 vex128 = 0,
645 vex256
646 } avxscalar;
647
43234a1e
L		 648/* Encode scalar EVEX LIG instructions with specific vector length. */
649static enum
650 {
651 evexl128 = 0,
652 evexl256,
653 evexl512
654 } evexlig;
655
656/* Encode EVEX WIG instructions with specific evex.w. */
657static enum
658 {
659 evexw0 = 0,
660 evexw1
661 } evexwig;
662
d3d3c6db
IT		 663/* Value to encode in EVEX RC bits, for SAE-only instructions. */
664static enum rc_type evexrcig = rne;
665
29b0f896 666/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 667static symbolS *GOT_symbol;
29b0f896 668
a4447b93
RH		 669/* The dwarf2 return column, adjusted for 32 or 64 bit. */
670unsigned int x86_dwarf2_return_column;
671
672/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
673int x86_cie_data_alignment;
674
252b5132 675/* Interface to relax_segment.
fddf5b5b
AM		 676 There are 3 major relax states for 386 jump insns because the
677 different types of jumps add different sizes to frags when we're
678 figuring out what sort of jump to choose to reach a given label. */
252b5132 679
47926f60 680/* Types. */
93c2a809
AM		 681#define UNCOND_JUMP 0
682#define COND_JUMP 1
683#define COND_JUMP86 2
fddf5b5b 684
47926f60 685/* Sizes. */
252b5132
RH		 686#define CODE16 1
687#define SMALL 0
29b0f896 688#define SMALL16 (SMALL | CODE16)
252b5132 689#define BIG 2
29b0f896 690#define BIG16 (BIG | CODE16)
252b5132
RH		 691
692#ifndef INLINE
693#ifdef __GNUC__
694#define INLINE __inline__
695#else
696#define INLINE
697#endif
698#endif
699
fddf5b5b
AM		 700#define ENCODE_RELAX_STATE(type, size) \
701 ((relax_substateT) (((type) << 2) | (size)))
702#define TYPE_FROM_RELAX_STATE(s) \
703 ((s) >> 2)
704#define DISP_SIZE_FROM_RELAX_STATE(s) \
705 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 706
707/* This table is used by relax_frag to promote short jumps to long
708 ones where necessary. SMALL (short) jumps may be promoted to BIG
709 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
710 don't allow a short jump in a 32 bit code segment to be promoted to
711 a 16 bit offset jump because it's slower (requires data size
712 prefix), and doesn't work, unless the destination is in the bottom
713 64k of the code segment (The top 16 bits of eip are zeroed). */
714
715const relax_typeS md_relax_table[] =
716{
24eab124
AM		 717 /* The fields are:
718 1) most positive reach of this state,
719 2) most negative reach of this state,
93c2a809 720 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 721 4) which index into the table to try if we can't fit into this one. */
252b5132 722
fddf5b5b 723 /* UNCOND_JUMP states. */
93c2a809
AM		 724 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
725 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
726 /* dword jmp adds 4 bytes to frag:
727 0 extra opcode bytes, 4 displacement bytes. */
252b5132 728 {0, 0, 4, 0},
93c2a809
AM		 729 /* word jmp adds 2 byte2 to frag:
730 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 731 {0, 0, 2, 0},
732
93c2a809
AM		 733 /* COND_JUMP states. */
734 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
735 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
736 /* dword conditionals adds 5 bytes to frag:
737 1 extra opcode byte, 4 displacement bytes. */
738 {0, 0, 5, 0},
fddf5b5b 739 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 740 1 extra opcode byte, 2 displacement bytes. */
741 {0, 0, 3, 0},
742
743 /* COND_JUMP86 states. */
744 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
745 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
746 /* dword conditionals adds 5 bytes to frag:
747 1 extra opcode byte, 4 displacement bytes. */
748 {0, 0, 5, 0},
749 /* word conditionals add 4 bytes to frag:
750 1 displacement byte and a 3 byte long branch insn. */
751 {0, 0, 4, 0}
252b5132
RH		 752};
753
9103f4f4
L		 754static const arch_entry cpu_arch[] =
755{
89507696
JB		 756 /* Do not replace the first two entries - i386_target_format()
757 relies on them being there in this order. */
8a2c8fef 758 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 759 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 760 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 761 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 762 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 763 CPU_NONE_FLAGS, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 765 CPU_I186_FLAGS, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 767 CPU_I286_FLAGS, 0 },
8a2c8fef 768 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 769 CPU_I386_FLAGS, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 771 CPU_I486_FLAGS, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 773 CPU_I586_FLAGS, 0 },
8a2c8fef 774 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 775 CPU_I686_FLAGS, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 777 CPU_I586_FLAGS, 0 },
8a2c8fef 778 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 779 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 781 CPU_P2_FLAGS, 0 },
8a2c8fef 782 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 783 CPU_P3_FLAGS, 0 },
8a2c8fef 784 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 785 CPU_P4_FLAGS, 0 },
8a2c8fef 786 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 787 CPU_CORE_FLAGS, 0 },
8a2c8fef 788 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 789 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 790 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 791 CPU_CORE_FLAGS, 1 },
8a2c8fef 792 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 793 CPU_CORE_FLAGS, 0 },
8a2c8fef 794 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 795 CPU_CORE2_FLAGS, 1 },
8a2c8fef 796 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 797 CPU_CORE2_FLAGS, 0 },
8a2c8fef 798 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 799 CPU_COREI7_FLAGS, 0 },
8a2c8fef 800 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 801 CPU_L1OM_FLAGS, 0 },
7a9068fe 802 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 803 CPU_K1OM_FLAGS, 0 },
81486035 804 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 805 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 806 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 807 CPU_K6_FLAGS, 0 },
8a2c8fef 808 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 809 CPU_K6_2_FLAGS, 0 },
8a2c8fef 810 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 811 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 812 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 813 CPU_K8_FLAGS, 1 },
8a2c8fef 814 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 815 CPU_K8_FLAGS, 0 },
8a2c8fef 816 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 817 CPU_K8_FLAGS, 0 },
8a2c8fef 818 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 819 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 820 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 821 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 822 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 823 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 824 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 825 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 826 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 827 CPU_BDVER4_FLAGS, 0 },
029f3522 828 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 829 CPU_ZNVER1_FLAGS, 0 },
7b458c12 830 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 831 CPU_BTVER1_FLAGS, 0 },
7b458c12 832 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 833 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 834 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 835 CPU_8087_FLAGS, 0 },
8a2c8fef 836 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 837 CPU_287_FLAGS, 0 },
8a2c8fef 838 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 839 CPU_387_FLAGS, 0 },
1848e567
L		 840 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
841 CPU_687_FLAGS, 0 },
8a2c8fef 842 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 843 CPU_MMX_FLAGS, 0 },
8a2c8fef 844 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 845 CPU_SSE_FLAGS, 0 },
8a2c8fef 846 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 847 CPU_SSE2_FLAGS, 0 },
8a2c8fef 848 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 849 CPU_SSE3_FLAGS, 0 },
8a2c8fef 850 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 851 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 852 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 853 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 854 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 855 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 856 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 857 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 858 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 859 CPU_AVX_FLAGS, 0 },
6c30d220 860 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_AVX2_FLAGS, 0 },
43234a1e 862 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_AVX512F_FLAGS, 0 },
43234a1e 864 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 865 CPU_AVX512CD_FLAGS, 0 },
43234a1e 866 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_AVX512ER_FLAGS, 0 },
43234a1e 868 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 870 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 872 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 874 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 876 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_VMX_FLAGS, 0 },
8729a6f6 878 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 880 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_SMX_FLAGS, 0 },
8a2c8fef 882 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 884 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 886 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 888 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 890 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_AES_FLAGS, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 896 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 898 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 900 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_F16C_FLAGS, 0 },
6c30d220 902 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_BMI2_FLAGS, 0 },
8a2c8fef 904 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_FMA_FLAGS, 0 },
8a2c8fef 906 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_FMA4_FLAGS, 0 },
8a2c8fef 908 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_XOP_FLAGS, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_LWP_FLAGS, 0 },
8a2c8fef 912 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_MOVBE_FLAGS, 0 },
60aa667e 914 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_CX16_FLAGS, 0 },
8a2c8fef 916 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_EPT_FLAGS, 0 },
6c30d220 918 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_LZCNT_FLAGS, 0 },
42164a71 920 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_HLE_FLAGS, 0 },
42164a71 922 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_RTM_FLAGS, 0 },
6c30d220 924 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 926 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_CLFLUSH_FLAGS, 0 },
22109423 928 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_NOP_FLAGS, 0 },
8a2c8fef 930 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 932 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 934 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 936 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 938 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 940 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_SVME_FLAGS, 1 },
8a2c8fef 942 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_SVME_FLAGS, 0 },
8a2c8fef 944 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 946 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_ABM_FLAGS, 0 },
87973e9f 948 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_BMI_FLAGS, 0 },
2a2a0f38 950 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_TBM_FLAGS, 0 },
e2e1fcde 952 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_ADX_FLAGS, 0 },
e2e1fcde 954 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 956 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_PRFCHW_FLAGS, 0 },
5c111e37 958 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_SMAP_FLAGS, 0 },
7e8b059b 960 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_MPX_FLAGS, 0 },
a0046408 962 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_SHA_FLAGS, 0 },
963f3586 964 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 965 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 966 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 967 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 968 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 969 CPU_SE1_FLAGS, 0 },
c5e7287a 970 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 971 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 972 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 973 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 974 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 975 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 976 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
977 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 978 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
979 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 980 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
981 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
029f3522 982 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 983 CPU_CLZERO_FLAGS, 0 },
9916071f 984 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 985 CPU_MWAITX_FLAGS, 0 },
8eab4136 986 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 987 CPU_OSPKE_FLAGS, 0 },
8bc52696 988 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 989 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 990 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
991 CPU_PTWRITE_FLAGS, 0 },
603555e5
L		 992 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
993 CPU_CET_FLAGS, 0 },
293f5f65
L		 994};
995
996static const noarch_entry cpu_noarch[] =
997{
998 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 999 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1000 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1001 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1002 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1003 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1004 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1005 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1006 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1007 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1008 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1009 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1010 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1011 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1012 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1013 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1014 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1015 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1016 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1017 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1018 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1019 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1020 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1021 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1022 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1023 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
e413e4e9
AM		 1024};
1025
704209c0 1026#ifdef I386COFF
a6c24e68
NC		 1027/* Like s_lcomm_internal in gas/read.c but the alignment string
1028 is allowed to be optional. */
1029
1030static symbolS *
1031pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1032{
1033 addressT align = 0;
1034
1035 SKIP_WHITESPACE ();
1036
7ab9ffdd 1037 if (needs_align
a6c24e68
NC		 1038 && *input_line_pointer == ',')
1039 {
1040 align = parse_align (needs_align - 1);
7ab9ffdd 1041
a6c24e68
NC		 1042 if (align == (addressT) -1)
1043 return NULL;
1044 }
1045 else
1046 {
1047 if (size >= 8)
1048 align = 3;
1049 else if (size >= 4)
1050 align = 2;
1051 else if (size >= 2)
1052 align = 1;
1053 else
1054 align = 0;
1055 }
1056
1057 bss_alloc (symbolP, size, align);
1058 return symbolP;
1059}
1060
704209c0 1061static void
a6c24e68
NC		 1062pe_lcomm (int needs_align)
1063{
1064 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1065}
704209c0 1066#endif
a6c24e68 1067
29b0f896
AM		 1068const pseudo_typeS md_pseudo_table[] =
1069{
1070#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1071 {"align", s_align_bytes, 0},
1072#else
1073 {"align", s_align_ptwo, 0},
1074#endif
1075 {"arch", set_cpu_arch, 0},
1076#ifndef I386COFF
1077 {"bss", s_bss, 0},
a6c24e68
NC		 1078#else
1079 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1080#endif
1081 {"ffloat", float_cons, 'f'},
1082 {"dfloat", float_cons, 'd'},
1083 {"tfloat", float_cons, 'x'},
1084 {"value", cons, 2},
d182319b 1085 {"slong", signed_cons, 4},
29b0f896
AM		 1086 {"noopt", s_ignore, 0},
1087 {"optim", s_ignore, 0},
1088 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1089 {"code16", set_code_flag, CODE_16BIT},
1090 {"code32", set_code_flag, CODE_32BIT},
1091 {"code64", set_code_flag, CODE_64BIT},
1092 {"intel_syntax", set_intel_syntax, 1},
1093 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1094 {"intel_mnemonic", set_intel_mnemonic, 1},
1095 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1096 {"allow_index_reg", set_allow_index_reg, 1},
1097 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1098 {"sse_check", set_check, 0},
1099 {"operand_check", set_check, 1},
3b22753a
L		 1100#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1101 {"largecomm", handle_large_common, 0},
07a53e5c 1102#else
e3bb37b5 1103 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1104 {"loc", dwarf2_directive_loc, 0},
1105 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1106#endif
6482c264
NC		 1107#ifdef TE_PE
1108 {"secrel32", pe_directive_secrel, 0},
1109#endif
29b0f896
AM		 1110 {0, 0, 0}
1111};
1112
1113/* For interface with expression (). */
1114extern char *input_line_pointer;
1115
1116/* Hash table for instruction mnemonic lookup. */
1117static struct hash_control *op_hash;
1118
1119/* Hash table for register lookup. */
1120static struct hash_control *reg_hash;
1121\f
252b5132 1122void
e3bb37b5 1123i386_align_code (fragS *fragP, int count)
252b5132 1124{
ce8a8b2f
AM		 1125 /* Various efficient no-op patterns for aligning code labels.
1126 Note: Don't try to assemble the instructions in the comments.
1127 0L and 0w are not legal. */
bad6e36d 1128 static const unsigned char f32_1[] =
252b5132 1129 {0x90}; /* nop */
bad6e36d 1130 static const unsigned char f32_2[] =
ccc9c027 1131 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1132 static const unsigned char f32_3[] =
252b5132 1133 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1134 static const unsigned char f32_4[] =
252b5132 1135 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1136 static const unsigned char f32_5[] =
252b5132
RH		 1137 {0x90, /* nop */
1138 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1139 static const unsigned char f32_6[] =
252b5132 1140 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1141 static const unsigned char f32_7[] =
252b5132 1142 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1143 static const unsigned char f32_8[] =
252b5132
RH		 1144 {0x90, /* nop */
1145 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1146 static const unsigned char f32_9[] =
252b5132
RH		 1147 {0x89,0xf6, /* movl %esi,%esi */
1148 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1149 static const unsigned char f32_10[] =
252b5132
RH		 1150 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1151 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1152 static const unsigned char f32_11[] =
252b5132
RH		 1153 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1154 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1155 static const unsigned char f32_12[] =
252b5132
RH		 1156 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1157 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1158 static const unsigned char f32_13[] =
252b5132
RH		 1159 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1160 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1161 static const unsigned char f32_14[] =
252b5132
RH		 1162 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1163 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1164 static const unsigned char f16_3[] =
c3332e24 1165 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1166 static const unsigned char f16_4[] =
252b5132 1167 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1168 static const unsigned char f16_5[] =
252b5132
RH		 1169 {0x90, /* nop */
1170 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1171 static const unsigned char f16_6[] =
252b5132
RH		 1172 {0x89,0xf6, /* mov %si,%si */
1173 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1174 static const unsigned char f16_7[] =
252b5132
RH		 1175 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1176 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1177 static const unsigned char f16_8[] =
252b5132
RH		 1178 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1179 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1180 static const unsigned char jump_31[] =
76bc74dc
L		 1181 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1182 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1183 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1184 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1185 static const unsigned char *const f32_patt[] = {
252b5132 1186 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1187 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1188 };
bad6e36d 1189 static const unsigned char *const f16_patt[] = {
76bc74dc 1190 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1191 };
ccc9c027 1192 /* nopl (%[re]ax) */
bad6e36d 1193 static const unsigned char alt_3[] =
ccc9c027
L		 1194 {0x0f,0x1f,0x00};
1195 /* nopl 0(%[re]ax) */
bad6e36d 1196 static const unsigned char alt_4[] =
ccc9c027
L		 1197 {0x0f,0x1f,0x40,0x00};
1198 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1199 static const unsigned char alt_5[] =
ccc9c027
L		 1200 {0x0f,0x1f,0x44,0x00,0x00};
1201 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1202 static const unsigned char alt_6[] =
ccc9c027
L		 1203 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1204 /* nopl 0L(%[re]ax) */
bad6e36d 1205 static const unsigned char alt_7[] =
ccc9c027
L		 1206 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1207 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1208 static const unsigned char alt_8[] =
ccc9c027
L		 1209 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1210 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1211 static const unsigned char alt_9[] =
ccc9c027
L		 1212 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1213 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1214 static const unsigned char alt_10[] =
ccc9c027 1215 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1216 static const unsigned char *const alt_patt[] = {
ccc9c027 1217 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1218 alt_9, alt_10
ccc9c027 1219 };
252b5132 1220
76bc74dc
L		 1221 /* Only align for at least a positive non-zero boundary. */
1222 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1223 return;
3e73aa7c 1224
ccc9c027
L		 1225 /* We need to decide which NOP sequence to use for 32bit and
1226 64bit. When -mtune= is used:
4eed87de 1227
76bc74dc
L		 1228 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1229 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1230 2. For the rest, alt_patt will be used.
1231
1232 When -mtune= isn't used, alt_patt will be used if
22109423 1233 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1234 be used.
ccc9c027
L		 1235
1236 When -march= or .arch is used, we can't use anything beyond
1237 cpu_arch_isa_flags. */
1238
1239 if (flag_code == CODE_16BIT)
1240 {
ccc9c027 1241 if (count > 8)
33fef721 1242 {
76bc74dc
L		 1243 memcpy (fragP->fr_literal + fragP->fr_fix,
1244 jump_31, count);
1245 /* Adjust jump offset. */
1246 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1247 }
76bc74dc
L		 1248 else
1249 memcpy (fragP->fr_literal + fragP->fr_fix,
1250 f16_patt[count - 1], count);
252b5132 1251 }
33fef721 1252 else
ccc9c027 1253 {
bad6e36d 1254 const unsigned char *const *patt = NULL;
ccc9c027 1255
fbf3f584 1256 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1257 {
1258 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1259 switch (cpu_arch_tune)
1260 {
1261 case PROCESSOR_UNKNOWN:
1262 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1263 optimize with nops. */
1264 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1265 patt = alt_patt;
ccc9c027
L		 1266 else
1267 patt = f32_patt;
1268 break;
ccc9c027
L		 1269 case PROCESSOR_PENTIUM4:
1270 case PROCESSOR_NOCONA:
ef05d495 1271 case PROCESSOR_CORE:
76bc74dc 1272 case PROCESSOR_CORE2:
bd5295b2 1273 case PROCESSOR_COREI7:
3632d14b 1274 case PROCESSOR_L1OM:
7a9068fe 1275 case PROCESSOR_K1OM:
76bc74dc 1276 case PROCESSOR_GENERIC64:
ccc9c027
L		 1277 case PROCESSOR_K6:
1278 case PROCESSOR_ATHLON:
1279 case PROCESSOR_K8:
4eed87de 1280 case PROCESSOR_AMDFAM10:
8aedb9fe 1281 case PROCESSOR_BD:
029f3522 1282 case PROCESSOR_ZNVER:
7b458c12 1283 case PROCESSOR_BT:
80b8656c 1284 patt = alt_patt;
ccc9c027 1285 break;
76bc74dc 1286 case PROCESSOR_I386:
ccc9c027
L		 1287 case PROCESSOR_I486:
1288 case PROCESSOR_PENTIUM:
2dde1948 1289 case PROCESSOR_PENTIUMPRO:
81486035 1290 case PROCESSOR_IAMCU:
ccc9c027
L		 1291 case PROCESSOR_GENERIC32:
1292 patt = f32_patt;
1293 break;
4eed87de 1294 }
ccc9c027
L		 1295 }
1296 else
1297 {
fbf3f584 1298 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1299 {
1300 case PROCESSOR_UNKNOWN:
e6a14101 1301 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1302 PROCESSOR_UNKNOWN. */
1303 abort ();
1304 break;
1305
76bc74dc 1306 case PROCESSOR_I386:
ccc9c027
L		 1307 case PROCESSOR_I486:
1308 case PROCESSOR_PENTIUM:
81486035 1309 case PROCESSOR_IAMCU:
ccc9c027
L		 1310 case PROCESSOR_K6:
1311 case PROCESSOR_ATHLON:
1312 case PROCESSOR_K8:
4eed87de 1313 case PROCESSOR_AMDFAM10:
8aedb9fe 1314 case PROCESSOR_BD:
029f3522 1315 case PROCESSOR_ZNVER:
7b458c12 1316 case PROCESSOR_BT:
ccc9c027
L		 1317 case PROCESSOR_GENERIC32:
1318 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1319 with nops. */
1320 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1321 patt = alt_patt;
ccc9c027
L		 1322 else
1323 patt = f32_patt;
1324 break;
76bc74dc
L		 1325 case PROCESSOR_PENTIUMPRO:
1326 case PROCESSOR_PENTIUM4:
1327 case PROCESSOR_NOCONA:
1328 case PROCESSOR_CORE:
ef05d495 1329 case PROCESSOR_CORE2:
bd5295b2 1330 case PROCESSOR_COREI7:
3632d14b 1331 case PROCESSOR_L1OM:
7a9068fe 1332 case PROCESSOR_K1OM:
22109423 1333 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1334 patt = alt_patt;
ccc9c027
L		 1335 else
1336 patt = f32_patt;
1337 break;
1338 case PROCESSOR_GENERIC64:
80b8656c 1339 patt = alt_patt;
ccc9c027 1340 break;
4eed87de 1341 }
ccc9c027
L		 1342 }
1343
76bc74dc
L		 1344 if (patt == f32_patt)
1345 {
1346 /* If the padding is less than 15 bytes, we use the normal
1347 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1348 its offset. */
1349 int limit;
76ba9986 1350
711eedef
L		 1351 /* For 64bit, the limit is 3 bytes. */
1352 if (flag_code == CODE_64BIT
1353 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1354 limit = 3;
1355 else
1356 limit = 15;
1357 if (count < limit)
76bc74dc
L		 1358 memcpy (fragP->fr_literal + fragP->fr_fix,
1359 patt[count - 1], count);
1360 else
1361 {
1362 memcpy (fragP->fr_literal + fragP->fr_fix,
1363 jump_31, count);
1364 /* Adjust jump offset. */
1365 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1366 }
1367 }
1368 else
1369 {
80b8656c
L		 1370 /* Maximum length of an instruction is 10 byte. If the
1371 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1372 we have to break it into smaller pieces. */
1373 int padding = count;
80b8656c 1374 while (padding > 10)
76bc74dc 1375 {
80b8656c 1376 padding -= 10;
76bc74dc 1377 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1378 patt [9], 10);
76bc74dc
L		 1379 }
1380
1381 if (padding)
1382 memcpy (fragP->fr_literal + fragP->fr_fix,
1383 patt [padding - 1], padding);
1384 }
ccc9c027 1385 }
33fef721 1386 fragP->fr_var = count;
252b5132
RH		 1387}
1388
c6fb90c8 1389static INLINE int
0dfbf9d7 1390operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1391{
0dfbf9d7 1392 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1393 {
1394 case 3:
0dfbf9d7 1395 if (x->array[2])
c6fb90c8 1396 return 0;
1a0670f3 1397 /* Fall through. */
c6fb90c8 1398 case 2:
0dfbf9d7 1399 if (x->array[1])
c6fb90c8 1400 return 0;
1a0670f3 1401 /* Fall through. */
c6fb90c8 1402 case 1:
0dfbf9d7 1403 return !x->array[0];
c6fb90c8
L		 1404 default:
1405 abort ();
1406 }
40fb9820
L		 1407}
1408
c6fb90c8 1409static INLINE void
0dfbf9d7 1410operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1411{
0dfbf9d7 1412 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1413 {
1414 case 3:
0dfbf9d7 1415 x->array[2] = v;
1a0670f3 1416 /* Fall through. */
c6fb90c8 1417 case 2:
0dfbf9d7 1418 x->array[1] = v;
1a0670f3 1419 /* Fall through. */
c6fb90c8 1420 case 1:
0dfbf9d7 1421 x->array[0] = v;
1a0670f3 1422 /* Fall through. */
c6fb90c8
L		 1423 break;
1424 default:
1425 abort ();
1426 }
1427}
40fb9820 1428
c6fb90c8 1429static INLINE int
0dfbf9d7
L		 1430operand_type_equal (const union i386_operand_type *x,
1431 const union i386_operand_type *y)
c6fb90c8 1432{
0dfbf9d7 1433 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1434 {
1435 case 3:
0dfbf9d7 1436 if (x->array[2] != y->array[2])
c6fb90c8 1437 return 0;
1a0670f3 1438 /* Fall through. */
c6fb90c8 1439 case 2:
0dfbf9d7 1440 if (x->array[1] != y->array[1])
c6fb90c8 1441 return 0;
1a0670f3 1442 /* Fall through. */
c6fb90c8 1443 case 1:
0dfbf9d7 1444 return x->array[0] == y->array[0];
c6fb90c8
L		 1445 break;
1446 default:
1447 abort ();
1448 }
1449}
40fb9820 1450
0dfbf9d7
L		 1451static INLINE int
1452cpu_flags_all_zero (const union i386_cpu_flags *x)
1453{
1454 switch (ARRAY_SIZE(x->array))
1455 {
1456 case 3:
1457 if (x->array[2])
1458 return 0;
1a0670f3 1459 /* Fall through. */
0dfbf9d7
L		 1460 case 2:
1461 if (x->array[1])
1462 return 0;
1a0670f3 1463 /* Fall through. */
0dfbf9d7
L		 1464 case 1:
1465 return !x->array[0];
1466 default:
1467 abort ();
1468 }
1469}
1470
0dfbf9d7
L		 1471static INLINE int
1472cpu_flags_equal (const union i386_cpu_flags *x,
1473 const union i386_cpu_flags *y)
1474{
1475 switch (ARRAY_SIZE(x->array))
1476 {
1477 case 3:
1478 if (x->array[2] != y->array[2])
1479 return 0;
1a0670f3 1480 /* Fall through. */
0dfbf9d7
L		 1481 case 2:
1482 if (x->array[1] != y->array[1])
1483 return 0;
1a0670f3 1484 /* Fall through. */
0dfbf9d7
L		 1485 case 1:
1486 return x->array[0] == y->array[0];
1487 break;
1488 default:
1489 abort ();
1490 }
1491}
c6fb90c8
L		 1492
1493static INLINE int
1494cpu_flags_check_cpu64 (i386_cpu_flags f)
1495{
1496 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1497 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1498}
1499
c6fb90c8
L		 1500static INLINE i386_cpu_flags
1501cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1502{
c6fb90c8
L		 1503 switch (ARRAY_SIZE (x.array))
1504 {
1505 case 3:
1506 x.array [2] &= y.array [2];
1a0670f3 1507 /* Fall through. */
c6fb90c8
L		 1508 case 2:
1509 x.array [1] &= y.array [1];
1a0670f3 1510 /* Fall through. */
c6fb90c8
L		 1511 case 1:
1512 x.array [0] &= y.array [0];
1513 break;
1514 default:
1515 abort ();
1516 }
1517 return x;
1518}
40fb9820 1519
c6fb90c8
L		 1520static INLINE i386_cpu_flags
1521cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1522{
c6fb90c8 1523 switch (ARRAY_SIZE (x.array))
40fb9820 1524 {
c6fb90c8
L		 1525 case 3:
1526 x.array [2] |= y.array [2];
1a0670f3 1527 /* Fall through. */
c6fb90c8
L		 1528 case 2:
1529 x.array [1] |= y.array [1];
1a0670f3 1530 /* Fall through. */
c6fb90c8
L		 1531 case 1:
1532 x.array [0] |= y.array [0];
40fb9820
L		 1533 break;
1534 default:
1535 abort ();
1536 }
40fb9820
L		 1537 return x;
1538}
1539
309d3373
JB		 1540static INLINE i386_cpu_flags
1541cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1542{
1543 switch (ARRAY_SIZE (x.array))
1544 {
1545 case 3:
1546 x.array [2] &= ~y.array [2];
1a0670f3 1547 /* Fall through. */
309d3373
JB		 1548 case 2:
1549 x.array [1] &= ~y.array [1];
1a0670f3 1550 /* Fall through. */
309d3373
JB		 1551 case 1:
1552 x.array [0] &= ~y.array [0];
1553 break;
1554 default:
1555 abort ();
1556 }
1557 return x;
1558}
1559
c0f3af97
L		 1560#define CPU_FLAGS_ARCH_MATCH 0x1
1561#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1562#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1563#define CPU_FLAGS_PCLMUL_MATCH 0x8
1564#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1565
a5ff0eb2 1566#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1567 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1568 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1569#define CPU_FLAGS_PERFECT_MATCH \
1570 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1571
1572/* Return CPU flags match bits. */
3629bb00 1573
40fb9820 1574static int
d3ce72d0 1575cpu_flags_match (const insn_template *t)
40fb9820 1576{
c0f3af97
L		 1577 i386_cpu_flags x = t->cpu_flags;
1578 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1579
1580 x.bitfield.cpu64 = 0;
1581 x.bitfield.cpuno64 = 0;
1582
0dfbf9d7 1583 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1584 {
1585 /* This instruction is available on all archs. */
1586 match |= CPU_FLAGS_32BIT_MATCH;
1587 }
3629bb00
L		 1588 else
1589 {
c0f3af97 1590 /* This instruction is available only on some archs. */
3629bb00
L		 1591 i386_cpu_flags cpu = cpu_arch_flags;
1592
3629bb00 1593 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1594 if (!cpu_flags_all_zero (&cpu))
1595 {
a5ff0eb2
L		 1596 if (x.bitfield.cpuavx)
1597 {
ce2f5b3c 1598 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1599 if (cpu.bitfield.cpuavx)
1600 {
1601 /* Check SSE2AVX. */
1602 if (!t->opcode_modifier.sse2avx|| sse2avx)
1603 {
1604 match |= (CPU_FLAGS_ARCH_MATCH
1605 | CPU_FLAGS_AVX_MATCH);
1606 /* Check AES. */
1607 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1608 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1609 /* Check PCLMUL. */
1610 if (!x.bitfield.cpupclmul
1611 || cpu.bitfield.cpupclmul)
1612 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1613 }
1614 }
1615 else
1616 match |= CPU_FLAGS_ARCH_MATCH;
1617 }
73b090a9
L		 1618 else if (x.bitfield.cpuavx512vl)
1619 {
1620 /* Match AVX512VL. */
1621 if (cpu.bitfield.cpuavx512vl)
1622 {
1623 /* Need another match. */
1624 cpu.bitfield.cpuavx512vl = 0;
1625 if (!cpu_flags_all_zero (&cpu))
1626 match |= CPU_FLAGS_32BIT_MATCH;
1627 else
1628 match |= CPU_FLAGS_ARCH_MATCH;
1629 }
1630 else
1631 match |= CPU_FLAGS_ARCH_MATCH;
1632 }
a5ff0eb2 1633 else
c0f3af97
L		 1634 match |= CPU_FLAGS_32BIT_MATCH;
1635 }
3629bb00 1636 }
c0f3af97 1637 return match;
40fb9820
L		 1638}
1639
c6fb90c8
L		 1640static INLINE i386_operand_type
1641operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1642{
c6fb90c8
L		 1643 switch (ARRAY_SIZE (x.array))
1644 {
1645 case 3:
1646 x.array [2] &= y.array [2];
1a0670f3 1647 /* Fall through. */
c6fb90c8
L		 1648 case 2:
1649 x.array [1] &= y.array [1];
1a0670f3 1650 /* Fall through. */
c6fb90c8
L		 1651 case 1:
1652 x.array [0] &= y.array [0];
1653 break;
1654 default:
1655 abort ();
1656 }
1657 return x;
40fb9820
L		 1658}
1659
c6fb90c8
L		 1660static INLINE i386_operand_type
1661operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1662{
c6fb90c8 1663 switch (ARRAY_SIZE (x.array))
40fb9820 1664 {
c6fb90c8
L		 1665 case 3:
1666 x.array [2] |= y.array [2];
1a0670f3 1667 /* Fall through. */
c6fb90c8
L		 1668 case 2:
1669 x.array [1] |= y.array [1];
1a0670f3 1670 /* Fall through. */
c6fb90c8
L		 1671 case 1:
1672 x.array [0] |= y.array [0];
40fb9820
L		 1673 break;
1674 default:
1675 abort ();
1676 }
c6fb90c8
L		 1677 return x;
1678}
40fb9820 1679
c6fb90c8
L		 1680static INLINE i386_operand_type
1681operand_type_xor (i386_operand_type x, i386_operand_type y)
1682{
1683 switch (ARRAY_SIZE (x.array))
1684 {
1685 case 3:
1686 x.array [2] ^= y.array [2];
1a0670f3 1687 /* Fall through. */
c6fb90c8
L		 1688 case 2:
1689 x.array [1] ^= y.array [1];
1a0670f3 1690 /* Fall through. */
c6fb90c8
L		 1691 case 1:
1692 x.array [0] ^= y.array [0];
1693 break;
1694 default:
1695 abort ();
1696 }
40fb9820
L		 1697 return x;
1698}
1699
1700static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1701static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1702static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1703static const i386_operand_type inoutportreg
1704 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1705static const i386_operand_type reg16_inoutportreg
1706 = OPERAND_TYPE_REG16_INOUTPORTREG;
1707static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1708static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1709static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1710static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1711static const i386_operand_type anydisp
1712 = OPERAND_TYPE_ANYDISP;
40fb9820 1713static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1714static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1715static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1716static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1717static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1718static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1719static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1720static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1721static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1722static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1723static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1724static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1725static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1726static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1727
1728enum operand_type
1729{
1730 reg,
40fb9820
L		 1731 imm,
1732 disp,
1733 anymem
1734};
1735
c6fb90c8 1736static INLINE int
40fb9820
L		 1737operand_type_check (i386_operand_type t, enum operand_type c)
1738{
1739 switch (c)
1740 {
1741 case reg:
1742 return (t.bitfield.reg8
1743 || t.bitfield.reg16
1744 || t.bitfield.reg32
1745 || t.bitfield.reg64);
1746
40fb9820
L		 1747 case imm:
1748 return (t.bitfield.imm8
1749 || t.bitfield.imm8s
1750 || t.bitfield.imm16
1751 || t.bitfield.imm32
1752 || t.bitfield.imm32s
1753 || t.bitfield.imm64);
1754
1755 case disp:
1756 return (t.bitfield.disp8
1757 || t.bitfield.disp16
1758 || t.bitfield.disp32
1759 || t.bitfield.disp32s
1760 || t.bitfield.disp64);
1761
1762 case anymem:
1763 return (t.bitfield.disp8
1764 || t.bitfield.disp16
1765 || t.bitfield.disp32
1766 || t.bitfield.disp32s
1767 || t.bitfield.disp64
1768 || t.bitfield.baseindex);
1769
1770 default:
1771 abort ();
1772 }
2cfe26b6
AM		 1773
1774 return 0;
40fb9820
L		 1775}
1776
5c07affc
L		 1777/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1778 operand J for instruction template T. */
1779
1780static INLINE int
d3ce72d0 1781match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1782{
1783 return !((i.types[j].bitfield.byte
1784 && !t->operand_types[j].bitfield.byte)
1785 || (i.types[j].bitfield.word
1786 && !t->operand_types[j].bitfield.word)
1787 || (i.types[j].bitfield.dword
1788 && !t->operand_types[j].bitfield.dword)
1789 || (i.types[j].bitfield.qword
1790 && !t->operand_types[j].bitfield.qword));
1791}
1792
1793/* Return 1 if there is no conflict in any size on operand J for
1794 instruction template T. */
1795
1796static INLINE int
d3ce72d0 1797match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1798{
1799 return (match_reg_size (t, j)
1800 && !((i.types[j].bitfield.unspecified
af508cb9 1801 && !i.broadcast
5c07affc
L		 1802 && !t->operand_types[j].bitfield.unspecified)
1803 || (i.types[j].bitfield.fword
1804 && !t->operand_types[j].bitfield.fword)
1805 || (i.types[j].bitfield.tbyte
1806 && !t->operand_types[j].bitfield.tbyte)
1807 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1808 && !t->operand_types[j].bitfield.xmmword)
1809 || (i.types[j].bitfield.ymmword
43234a1e
L		 1810 && !t->operand_types[j].bitfield.ymmword)
1811 || (i.types[j].bitfield.zmmword
1812 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1813}
1814
1815/* Return 1 if there is no size conflict on any operands for
1816 instruction template T. */
1817
1818static INLINE int
d3ce72d0 1819operand_size_match (const insn_template *t)
5c07affc
L		 1820{
1821 unsigned int j;
1822 int match = 1;
1823
1824 /* Don't check jump instructions. */
1825 if (t->opcode_modifier.jump
1826 || t->opcode_modifier.jumpbyte
1827 || t->opcode_modifier.jumpdword
1828 || t->opcode_modifier.jumpintersegment)
1829 return match;
1830
1831 /* Check memory and accumulator operand size. */
1832 for (j = 0; j < i.operands; j++)
1833 {
1834 if (t->operand_types[j].bitfield.anysize)
1835 continue;
1836
1837 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1838 {
1839 match = 0;
1840 break;
1841 }
1842
1843 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1844 {
1845 match = 0;
1846 break;
1847 }
1848 }
1849
891edac4 1850 if (match)
5c07affc 1851 return match;
891edac4
L		 1852 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1853 {
1854mismatch:
86e026a4 1855 i.error = operand_size_mismatch;
891edac4
L		 1856 return 0;
1857 }
5c07affc
L		 1858
1859 /* Check reverse. */
9c2799c2 1860 gas_assert (i.operands == 2);
5c07affc
L		 1861
1862 match = 1;
1863 for (j = 0; j < 2; j++)
1864 {
1865 if (t->operand_types[j].bitfield.acc
1866 && !match_reg_size (t, j ? 0 : 1))
891edac4 1867 goto mismatch;
5c07affc
L		 1868
1869 if (i.types[j].bitfield.mem
1870 && !match_mem_size (t, j ? 0 : 1))
891edac4 1871 goto mismatch;
5c07affc
L		 1872 }
1873
1874 return match;
1875}
1876
c6fb90c8 1877static INLINE int
40fb9820
L		 1878operand_type_match (i386_operand_type overlap,
1879 i386_operand_type given)
1880{
1881 i386_operand_type temp = overlap;
1882
1883 temp.bitfield.jumpabsolute = 0;
7d5e4556 1884 temp.bitfield.unspecified = 0;
5c07affc
L		 1885 temp.bitfield.byte = 0;
1886 temp.bitfield.word = 0;
1887 temp.bitfield.dword = 0;
1888 temp.bitfield.fword = 0;
1889 temp.bitfield.qword = 0;
1890 temp.bitfield.tbyte = 0;
1891 temp.bitfield.xmmword = 0;
c0f3af97 1892 temp.bitfield.ymmword = 0;
43234a1e 1893 temp.bitfield.zmmword = 0;
0dfbf9d7 1894 if (operand_type_all_zero (&temp))
891edac4 1895 goto mismatch;
40fb9820 1896
891edac4
L		 1897 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1898 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1899 return 1;
1900
1901mismatch:
a65babc9 1902 i.error = operand_type_mismatch;
891edac4 1903 return 0;
40fb9820
L		 1904}
1905
7d5e4556 1906/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1907 unless the expected operand type register overlap is null.
1908 Note that Acc in a template matches every size of reg. */
1909
c6fb90c8 1910static INLINE int
40fb9820
L		 1911operand_type_register_match (i386_operand_type m0,
1912 i386_operand_type g0,
1913 i386_operand_type t0,
1914 i386_operand_type m1,
1915 i386_operand_type g1,
1916 i386_operand_type t1)
1917{
1918 if (!operand_type_check (g0, reg))
1919 return 1;
1920
1921 if (!operand_type_check (g1, reg))
1922 return 1;
1923
1924 if (g0.bitfield.reg8 == g1.bitfield.reg8
1925 && g0.bitfield.reg16 == g1.bitfield.reg16
1926 && g0.bitfield.reg32 == g1.bitfield.reg32
1927 && g0.bitfield.reg64 == g1.bitfield.reg64)
1928 return 1;
1929
1930 if (m0.bitfield.acc)
1931 {
1932 t0.bitfield.reg8 = 1;
1933 t0.bitfield.reg16 = 1;
1934 t0.bitfield.reg32 = 1;
1935 t0.bitfield.reg64 = 1;
1936 }
1937
1938 if (m1.bitfield.acc)
1939 {
1940 t1.bitfield.reg8 = 1;
1941 t1.bitfield.reg16 = 1;
1942 t1.bitfield.reg32 = 1;
1943 t1.bitfield.reg64 = 1;
1944 }
1945
891edac4
L		 1946 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1947 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1948 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1949 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1950 return 1;
1951
a65babc9 1952 i.error = register_type_mismatch;
891edac4
L		 1953
1954 return 0;
40fb9820
L		 1955}
1956
4c692bc7
JB		 1957static INLINE unsigned int
1958register_number (const reg_entry *r)
1959{
1960 unsigned int nr = r->reg_num;
1961
1962 if (r->reg_flags & RegRex)
1963 nr += 8;
1964
200cbe0f
L		 1965 if (r->reg_flags & RegVRex)
1966 nr += 16;
1967
4c692bc7
JB		 1968 return nr;
1969}
1970
252b5132 1971static INLINE unsigned int
40fb9820 1972mode_from_disp_size (i386_operand_type t)
252b5132 1973{
43234a1e 1974 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1975 return 1;
1976 else if (t.bitfield.disp16
1977 || t.bitfield.disp32
1978 || t.bitfield.disp32s)
1979 return 2;
1980 else
1981 return 0;
252b5132
RH		 1982}
1983
1984static INLINE int
65879393 1985fits_in_signed_byte (addressT num)
252b5132 1986{
65879393 1987 return num + 0x80 <= 0xff;
47926f60 1988}
252b5132
RH		 1989
1990static INLINE int
65879393 1991fits_in_unsigned_byte (addressT num)
252b5132 1992{
65879393 1993 return num <= 0xff;
47926f60 1994}
252b5132
RH		 1995
1996static INLINE int
65879393 1997fits_in_unsigned_word (addressT num)
252b5132 1998{
65879393 1999 return num <= 0xffff;
47926f60 2000}
252b5132
RH		 2001
2002static INLINE int
65879393 2003fits_in_signed_word (addressT num)
252b5132 2004{
65879393 2005 return num + 0x8000 <= 0xffff;
47926f60 2006}
2a962e6d 2007
3e73aa7c 2008static INLINE int
65879393 2009fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2010{
2011#ifndef BFD64
2012 return 1;
2013#else
65879393 2014 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2015#endif
2016} /* fits_in_signed_long() */
2a962e6d 2017
3e73aa7c 2018static INLINE int
65879393 2019fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2020{
2021#ifndef BFD64
2022 return 1;
2023#else
65879393 2024 return num <= 0xffffffff;
3e73aa7c
JH		 2025#endif
2026} /* fits_in_unsigned_long() */
252b5132 2027
43234a1e
L		 2028static INLINE int
2029fits_in_vec_disp8 (offsetT num)
2030{
2031 int shift = i.memshift;
2032 unsigned int mask;
2033
2034 if (shift == -1)
2035 abort ();
2036
2037 mask = (1 << shift) - 1;
2038
2039 /* Return 0 if NUM isn't properly aligned. */
2040 if ((num & mask))
2041 return 0;
2042
2043 /* Check if NUM will fit in 8bit after shift. */
2044 return fits_in_signed_byte (num >> shift);
2045}
2046
a683cc34
SP		 2047static INLINE int
2048fits_in_imm4 (offsetT num)
2049{
2050 return (num & 0xf) == num;
2051}
2052
40fb9820 2053static i386_operand_type
e3bb37b5 2054smallest_imm_type (offsetT num)
252b5132 2055{
40fb9820 2056 i386_operand_type t;
7ab9ffdd 2057
0dfbf9d7 2058 operand_type_set (&t, 0);
40fb9820
L		 2059 t.bitfield.imm64 = 1;
2060
2061 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2062 {
2063 /* This code is disabled on the 486 because all the Imm1 forms
2064 in the opcode table are slower on the i486. They're the
2065 versions with the implicitly specified single-position
2066 displacement, which has another syntax if you really want to
2067 use that form. */
40fb9820
L		 2068 t.bitfield.imm1 = 1;
2069 t.bitfield.imm8 = 1;
2070 t.bitfield.imm8s = 1;
2071 t.bitfield.imm16 = 1;
2072 t.bitfield.imm32 = 1;
2073 t.bitfield.imm32s = 1;
2074 }
2075 else if (fits_in_signed_byte (num))
2076 {
2077 t.bitfield.imm8 = 1;
2078 t.bitfield.imm8s = 1;
2079 t.bitfield.imm16 = 1;
2080 t.bitfield.imm32 = 1;
2081 t.bitfield.imm32s = 1;
2082 }
2083 else if (fits_in_unsigned_byte (num))
2084 {
2085 t.bitfield.imm8 = 1;
2086 t.bitfield.imm16 = 1;
2087 t.bitfield.imm32 = 1;
2088 t.bitfield.imm32s = 1;
2089 }
2090 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2091 {
2092 t.bitfield.imm16 = 1;
2093 t.bitfield.imm32 = 1;
2094 t.bitfield.imm32s = 1;
2095 }
2096 else if (fits_in_signed_long (num))
2097 {
2098 t.bitfield.imm32 = 1;
2099 t.bitfield.imm32s = 1;
2100 }
2101 else if (fits_in_unsigned_long (num))
2102 t.bitfield.imm32 = 1;
2103
2104 return t;
47926f60 2105}
252b5132 2106
847f7ad4 2107static offsetT
e3bb37b5 2108offset_in_range (offsetT val, int size)
847f7ad4 2109{
508866be 2110 addressT mask;
ba2adb93 2111
847f7ad4
AM		 2112 switch (size)
2113 {
508866be
L		 2114 case 1: mask = ((addressT) 1 << 8) - 1; break;
2115 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2116 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2117#ifdef BFD64
2118 case 8: mask = ((addressT) 2 << 63) - 1; break;
2119#endif
47926f60 2120 default: abort ();
847f7ad4
AM		 2121 }
2122
9de868bf
L		 2123#ifdef BFD64
2124 /* If BFD64, sign extend val for 32bit address mode. */
2125 if (flag_code != CODE_64BIT
2126 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2127 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2128 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2129#endif
ba2adb93 2130
47926f60 2131 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2132 {
2133 char buf1[40], buf2[40];
2134
2135 sprint_value (buf1, val);
2136 sprint_value (buf2, val & mask);
2137 as_warn (_("%s shortened to %s"), buf1, buf2);
2138 }
2139 return val & mask;
2140}
2141
c32fa91d
L		 2142enum PREFIX_GROUP
2143{
2144 PREFIX_EXIST = 0,
2145 PREFIX_LOCK,
2146 PREFIX_REP,
2147 PREFIX_OTHER
2148};
2149
2150/* Returns
2151 a. PREFIX_EXIST if attempting to add a prefix where one from the
2152 same class already exists.
2153 b. PREFIX_LOCK if lock prefix is added.
2154 c. PREFIX_REP if rep/repne prefix is added.
2155 d. PREFIX_OTHER if other prefix is added.
2156 */
2157
2158static enum PREFIX_GROUP
e3bb37b5 2159add_prefix (unsigned int prefix)
252b5132 2160{
c32fa91d 2161 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2162 unsigned int q;
252b5132 2163
29b0f896
AM		 2164 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2165 && flag_code == CODE_64BIT)
b1905489 2166 {
161a04f6
L		 2167 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2168 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2169 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2170 ret = PREFIX_EXIST;
b1905489
JB		 2171 q = REX_PREFIX;
2172 }
3e73aa7c 2173 else
b1905489
JB		 2174 {
2175 switch (prefix)
2176 {
2177 default:
2178 abort ();
2179
2180 case CS_PREFIX_OPCODE:
2181 case DS_PREFIX_OPCODE:
2182 case ES_PREFIX_OPCODE:
2183 case FS_PREFIX_OPCODE:
2184 case GS_PREFIX_OPCODE:
2185 case SS_PREFIX_OPCODE:
2186 q = SEG_PREFIX;
2187 break;
2188
2189 case REPNE_PREFIX_OPCODE:
2190 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2191 q = REP_PREFIX;
2192 ret = PREFIX_REP;
2193 break;
2194
b1905489 2195 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2196 q = LOCK_PREFIX;
2197 ret = PREFIX_LOCK;
b1905489
JB		 2198 break;
2199
2200 case FWAIT_OPCODE:
2201 q = WAIT_PREFIX;
2202 break;
2203
2204 case ADDR_PREFIX_OPCODE:
2205 q = ADDR_PREFIX;
2206 break;
2207
2208 case DATA_PREFIX_OPCODE:
2209 q = DATA_PREFIX;
2210 break;
2211 }
2212 if (i.prefix[q] != 0)
c32fa91d 2213 ret = PREFIX_EXIST;
b1905489 2214 }
252b5132 2215
b1905489 2216 if (ret)
252b5132 2217 {
b1905489
JB		 2218 if (!i.prefix[q])
2219 ++i.prefixes;
2220 i.prefix[q] |= prefix;
252b5132 2221 }
b1905489
JB		 2222 else
2223 as_bad (_("same type of prefix used twice"));
252b5132 2224
252b5132
RH		 2225 return ret;
2226}
2227
2228static void
78f12dd3 2229update_code_flag (int value, int check)
eecb386c 2230{
78f12dd3
L		 2231 PRINTF_LIKE ((*as_error));
2232
1e9cc1c2 2233 flag_code = (enum flag_code) value;
40fb9820
L		 2234 if (flag_code == CODE_64BIT)
2235 {
2236 cpu_arch_flags.bitfield.cpu64 = 1;
2237 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2238 }
2239 else
2240 {
2241 cpu_arch_flags.bitfield.cpu64 = 0;
2242 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2243 }
2244 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2245 {
78f12dd3
L		 2246 if (check)
2247 as_error = as_fatal;
2248 else
2249 as_error = as_bad;
2250 (*as_error) (_("64bit mode not supported on `%s'."),
2251 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2252 }
40fb9820 2253 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2254 {
78f12dd3
L		 2255 if (check)
2256 as_error = as_fatal;
2257 else
2258 as_error = as_bad;
2259 (*as_error) (_("32bit mode not supported on `%s'."),
2260 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2261 }
eecb386c
AM		 2262 stackop_size = '\0';
2263}
2264
78f12dd3
L		 2265static void
2266set_code_flag (int value)
2267{
2268 update_code_flag (value, 0);
2269}
2270
eecb386c 2271static void
e3bb37b5 2272set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2273{
1e9cc1c2 2274 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2275 if (flag_code != CODE_16BIT)
2276 abort ();
2277 cpu_arch_flags.bitfield.cpu64 = 0;
2278 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2279 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2280}
2281
2282static void
e3bb37b5 2283set_intel_syntax (int syntax_flag)
252b5132
RH		 2284{
2285 /* Find out if register prefixing is specified. */
2286 int ask_naked_reg = 0;
2287
2288 SKIP_WHITESPACE ();
29b0f896 2289 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2290 {
d02603dc
NC		 2291 char *string;
2292 int e = get_symbol_name (&string);
252b5132 2293
47926f60 2294 if (strcmp (string, "prefix") == 0)
252b5132 2295 ask_naked_reg = 1;
47926f60 2296 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2297 ask_naked_reg = -1;
2298 else
d0b47220 2299 as_bad (_("bad argument to syntax directive."));
d02603dc 2300 (void) restore_line_pointer (e);
252b5132
RH		 2301 }
2302 demand_empty_rest_of_line ();
c3332e24 2303
252b5132
RH		 2304 intel_syntax = syntax_flag;
2305
2306 if (ask_naked_reg == 0)
f86103b7
AM		 2307 allow_naked_reg = (intel_syntax
2308 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2309 else
2310 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2311
ee86248c 2312 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2313
e4a3b5a4 2314 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2315 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2316 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2317}
2318
1efbbeb4
L		 2319static void
2320set_intel_mnemonic (int mnemonic_flag)
2321{
e1d4d893 2322 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2323}
2324
db51cc60
L		 2325static void
2326set_allow_index_reg (int flag)
2327{
2328 allow_index_reg = flag;
2329}
2330
cb19c032 2331static void
7bab8ab5 2332set_check (int what)
cb19c032 2333{
7bab8ab5
JB		 2334 enum check_kind *kind;
2335 const char *str;
2336
2337 if (what)
2338 {
2339 kind = &operand_check;
2340 str = "operand";
2341 }
2342 else
2343 {
2344 kind = &sse_check;
2345 str = "sse";
2346 }
2347
cb19c032
L		 2348 SKIP_WHITESPACE ();
2349
2350 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2351 {
d02603dc
NC		 2352 char *string;
2353 int e = get_symbol_name (&string);
cb19c032
L		 2354
2355 if (strcmp (string, "none") == 0)
7bab8ab5 2356 *kind = check_none;
cb19c032 2357 else if (strcmp (string, "warning") == 0)
7bab8ab5 2358 *kind = check_warning;
cb19c032 2359 else if (strcmp (string, "error") == 0)
7bab8ab5 2360 *kind = check_error;
cb19c032 2361 else
7bab8ab5 2362 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2363 (void) restore_line_pointer (e);
cb19c032
L		 2364 }
2365 else
7bab8ab5 2366 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2367
2368 demand_empty_rest_of_line ();
2369}
2370
8a9036a4
L		 2371static void
2372check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2373 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2374{
2375#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2376 static const char *arch;
2377
2378 /* Intel LIOM is only supported on ELF. */
2379 if (!IS_ELF)
2380 return;
2381
2382 if (!arch)
2383 {
2384 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2385 use default_arch. */
2386 arch = cpu_arch_name;
2387 if (!arch)
2388 arch = default_arch;
2389 }
2390
81486035
L		 2391 /* If we are targeting Intel MCU, we must enable it. */
2392 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2393 || new_flag.bitfield.cpuiamcu)
2394 return;
2395
3632d14b 2396 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2397 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2398 || new_flag.bitfield.cpul1om)
8a9036a4 2399 return;
76ba9986 2400
7a9068fe
L		 2401 /* If we are targeting Intel K1OM, we must enable it. */
2402 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2403 || new_flag.bitfield.cpuk1om)
2404 return;
2405
8a9036a4
L		 2406 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2407#endif
2408}
2409
e413e4e9 2410static void
e3bb37b5 2411set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2412{
47926f60 2413 SKIP_WHITESPACE ();
e413e4e9 2414
29b0f896 2415 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2416 {
d02603dc
NC		 2417 char *string;
2418 int e = get_symbol_name (&string);
91d6fa6a 2419 unsigned int j;
40fb9820 2420 i386_cpu_flags flags;
e413e4e9 2421
91d6fa6a 2422 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2423 {
91d6fa6a 2424 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2425 {
91d6fa6a 2426 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2427
5c6af06e
JB		 2428 if (*string != '.')
2429 {
91d6fa6a 2430 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2431 cpu_sub_arch_name = NULL;
91d6fa6a 2432 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2433 if (flag_code == CODE_64BIT)
2434 {
2435 cpu_arch_flags.bitfield.cpu64 = 1;
2436 cpu_arch_flags.bitfield.cpuno64 = 0;
2437 }
2438 else
2439 {
2440 cpu_arch_flags.bitfield.cpu64 = 0;
2441 cpu_arch_flags.bitfield.cpuno64 = 1;
2442 }
91d6fa6a
NC		 2443 cpu_arch_isa = cpu_arch[j].type;
2444 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2445 if (!cpu_arch_tune_set)
2446 {
2447 cpu_arch_tune = cpu_arch_isa;
2448 cpu_arch_tune_flags = cpu_arch_isa_flags;
2449 }
5c6af06e
JB		 2450 break;
2451 }
40fb9820 2452
293f5f65
L		 2453 flags = cpu_flags_or (cpu_arch_flags,
2454 cpu_arch[j].flags);
81486035 2455
5b64d091 2456 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2457 {
6305a203
L		 2458 if (cpu_sub_arch_name)
2459 {
2460 char *name = cpu_sub_arch_name;
2461 cpu_sub_arch_name = concat (name,
91d6fa6a 2462 cpu_arch[j].name,
1bf57e9f 2463 (const char *) NULL);
6305a203
L		 2464 free (name);
2465 }
2466 else
91d6fa6a 2467 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2468 cpu_arch_flags = flags;
a586129e 2469 cpu_arch_isa_flags = flags;
5c6af06e 2470 }
d02603dc 2471 (void) restore_line_pointer (e);
5c6af06e
JB		 2472 demand_empty_rest_of_line ();
2473 return;
e413e4e9
AM		 2474 }
2475 }
293f5f65
L		 2476
2477 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2478 {
33eaf5de 2479 /* Disable an ISA extension. */
293f5f65
L		 2480 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2481 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2482 {
2483 flags = cpu_flags_and_not (cpu_arch_flags,
2484 cpu_noarch[j].flags);
2485 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2486 {
2487 if (cpu_sub_arch_name)
2488 {
2489 char *name = cpu_sub_arch_name;
2490 cpu_sub_arch_name = concat (name, string,
2491 (const char *) NULL);
2492 free (name);
2493 }
2494 else
2495 cpu_sub_arch_name = xstrdup (string);
2496 cpu_arch_flags = flags;
2497 cpu_arch_isa_flags = flags;
2498 }
2499 (void) restore_line_pointer (e);
2500 demand_empty_rest_of_line ();
2501 return;
2502 }
2503
2504 j = ARRAY_SIZE (cpu_arch);
2505 }
2506
91d6fa6a 2507 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2508 as_bad (_("no such architecture: `%s'"), string);
2509
2510 *input_line_pointer = e;
2511 }
2512 else
2513 as_bad (_("missing cpu architecture"));
2514
fddf5b5b
AM		 2515 no_cond_jump_promotion = 0;
2516 if (*input_line_pointer == ','
29b0f896 2517 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2518 {
d02603dc
NC		 2519 char *string;
2520 char e;
2521
2522 ++input_line_pointer;
2523 e = get_symbol_name (&string);
fddf5b5b
AM		 2524
2525 if (strcmp (string, "nojumps") == 0)
2526 no_cond_jump_promotion = 1;
2527 else if (strcmp (string, "jumps") == 0)
2528 ;
2529 else
2530 as_bad (_("no such architecture modifier: `%s'"), string);
2531
d02603dc 2532 (void) restore_line_pointer (e);
fddf5b5b
AM		 2533 }
2534
e413e4e9
AM		 2535 demand_empty_rest_of_line ();
2536}
2537
8a9036a4
L		 2538enum bfd_architecture
2539i386_arch (void)
2540{
3632d14b 2541 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2542 {
2543 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2544 || flag_code != CODE_64BIT)
2545 as_fatal (_("Intel L1OM is 64bit ELF only"));
2546 return bfd_arch_l1om;
2547 }
7a9068fe
L		 2548 else if (cpu_arch_isa == PROCESSOR_K1OM)
2549 {
2550 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2551 || flag_code != CODE_64BIT)
2552 as_fatal (_("Intel K1OM is 64bit ELF only"));
2553 return bfd_arch_k1om;
2554 }
81486035
L		 2555 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2556 {
2557 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2558 || flag_code == CODE_64BIT)
2559 as_fatal (_("Intel MCU is 32bit ELF only"));
2560 return bfd_arch_iamcu;
2561 }
8a9036a4
L		 2562 else
2563 return bfd_arch_i386;
2564}
2565
b9d79e03 2566unsigned long
7016a5d5 2567i386_mach (void)
b9d79e03 2568{
351f65ca 2569 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2570 {
3632d14b 2571 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2572 {
351f65ca
L		 2573 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2574 || default_arch[6] != '\0')
8a9036a4
L		 2575 as_fatal (_("Intel L1OM is 64bit ELF only"));
2576 return bfd_mach_l1om;
2577 }
7a9068fe
L		 2578 else if (cpu_arch_isa == PROCESSOR_K1OM)
2579 {
2580 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2581 || default_arch[6] != '\0')
2582 as_fatal (_("Intel K1OM is 64bit ELF only"));
2583 return bfd_mach_k1om;
2584 }
351f65ca 2585 else if (default_arch[6] == '\0')
8a9036a4 2586 return bfd_mach_x86_64;
351f65ca
L		 2587 else
2588 return bfd_mach_x64_32;
8a9036a4 2589 }
5197d474
L		 2590 else if (!strcmp (default_arch, "i386")
2591 || !strcmp (default_arch, "iamcu"))
81486035
L		 2592 {
2593 if (cpu_arch_isa == PROCESSOR_IAMCU)
2594 {
2595 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2596 as_fatal (_("Intel MCU is 32bit ELF only"));
2597 return bfd_mach_i386_iamcu;
2598 }
2599 else
2600 return bfd_mach_i386_i386;
2601 }
b9d79e03 2602 else
2b5d6a91 2603 as_fatal (_("unknown architecture"));
b9d79e03 2604}
b9d79e03 2605\f
252b5132 2606void
7016a5d5 2607md_begin (void)
252b5132
RH		 2608{
2609 const char *hash_err;
2610
86fa6981
L		 2611 /* Support pseudo prefixes like {disp32}. */
2612 lex_type ['{'] = LEX_BEGIN_NAME;
2613
47926f60 2614 /* Initialize op_hash hash table. */
252b5132
RH		 2615 op_hash = hash_new ();
2616
2617 {
d3ce72d0 2618 const insn_template *optab;
29b0f896 2619 templates *core_optab;
252b5132 2620
47926f60
KH		 2621 /* Setup for loop. */
2622 optab = i386_optab;
add39d23 2623 core_optab = XNEW (templates);
252b5132
RH		 2624 core_optab->start = optab;
2625
2626 while (1)
2627 {
2628 ++optab;
2629 if (optab->name == NULL
2630 || strcmp (optab->name, (optab - 1)->name) != 0)
2631 {
2632 /* different name --> ship out current template list;
47926f60 2633 add to hash table; & begin anew. */
252b5132
RH		 2634 core_optab->end = optab;
2635 hash_err = hash_insert (op_hash,
2636 (optab - 1)->name,
5a49b8ac 2637 (void *) core_optab);
252b5132
RH		 2638 if (hash_err)
2639 {
b37df7c4 2640 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2641 (optab - 1)->name,
2642 hash_err);
2643 }
2644 if (optab->name == NULL)
2645 break;
add39d23 2646 core_optab = XNEW (templates);
252b5132
RH		 2647 core_optab->start = optab;
2648 }
2649 }
2650 }
2651
47926f60 2652 /* Initialize reg_hash hash table. */
252b5132
RH		 2653 reg_hash = hash_new ();
2654 {
29b0f896 2655 const reg_entry *regtab;
c3fe08fa 2656 unsigned int regtab_size = i386_regtab_size;
252b5132 2657
c3fe08fa 2658 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2659 {
5a49b8ac 2660 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2661 if (hash_err)
b37df7c4 2662 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2663 regtab->reg_name,
2664 hash_err);
252b5132
RH		 2665 }
2666 }
2667
47926f60 2668 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2669 {
29b0f896
AM		 2670 int c;
2671 char *p;
252b5132
RH		 2672
2673 for (c = 0; c < 256; c++)
2674 {
3882b010 2675 if (ISDIGIT (c))
252b5132
RH		 2676 {
2677 digit_chars[c] = c;
2678 mnemonic_chars[c] = c;
2679 register_chars[c] = c;
2680 operand_chars[c] = c;
2681 }
3882b010 2682 else if (ISLOWER (c))
252b5132
RH		 2683 {
2684 mnemonic_chars[c] = c;
2685 register_chars[c] = c;
2686 operand_chars[c] = c;
2687 }
3882b010 2688 else if (ISUPPER (c))
252b5132 2689 {
3882b010 2690 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2691 register_chars[c] = mnemonic_chars[c];
2692 operand_chars[c] = c;
2693 }
43234a1e 2694 else if (c == '{' || c == '}')
86fa6981
L		 2695 {
2696 mnemonic_chars[c] = c;
2697 operand_chars[c] = c;
2698 }
252b5132 2699
3882b010 2700 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2701 identifier_chars[c] = c;
2702 else if (c >= 128)
2703 {
2704 identifier_chars[c] = c;
2705 operand_chars[c] = c;
2706 }
2707 }
2708
2709#ifdef LEX_AT
2710 identifier_chars['@'] = '@';
32137342
NC		 2711#endif
2712#ifdef LEX_QM
2713 identifier_chars['?'] = '?';
2714 operand_chars['?'] = '?';
252b5132 2715#endif
252b5132 2716 digit_chars['-'] = '-';
c0f3af97 2717 mnemonic_chars['_'] = '_';
791fe849 2718 mnemonic_chars['-'] = '-';
0003779b 2719 mnemonic_chars['.'] = '.';
252b5132
RH		 2720 identifier_chars['_'] = '_';
2721 identifier_chars['.'] = '.';
2722
2723 for (p = operand_special_chars; *p != '\0'; p++)
2724 operand_chars[(unsigned char) *p] = *p;
2725 }
2726
a4447b93
RH		 2727 if (flag_code == CODE_64BIT)
2728 {
ca19b261
KT		 2729#if defined (OBJ_COFF) && defined (TE_PE)
2730 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2731 ? 32 : 16);
2732#else
a4447b93 2733 x86_dwarf2_return_column = 16;
ca19b261 2734#endif
61ff971f 2735 x86_cie_data_alignment = -8;
a4447b93
RH		 2736 }
2737 else
2738 {
2739 x86_dwarf2_return_column = 8;
2740 x86_cie_data_alignment = -4;
2741 }
252b5132
RH		 2742}
2743
2744void
e3bb37b5 2745i386_print_statistics (FILE *file)
252b5132
RH		 2746{
2747 hash_print_statistics (file, "i386 opcode", op_hash);
2748 hash_print_statistics (file, "i386 register", reg_hash);
2749}
2750\f
252b5132
RH		 2751#ifdef DEBUG386
2752
ce8a8b2f 2753/* Debugging routines for md_assemble. */
d3ce72d0 2754static void pte (insn_template *);
40fb9820 2755static void pt (i386_operand_type);
e3bb37b5
L		 2756static void pe (expressionS *);
2757static void ps (symbolS *);
252b5132
RH		 2758
2759static void
e3bb37b5 2760pi (char *line, i386_insn *x)
252b5132 2761{
09137c09 2762 unsigned int j;
252b5132
RH		 2763
2764 fprintf (stdout, "%s: template ", line);
2765 pte (&x->tm);
09f131f2
JH		 2766 fprintf (stdout, " address: base %s index %s scale %x\n",
2767 x->base_reg ? x->base_reg->reg_name : "none",
2768 x->index_reg ? x->index_reg->reg_name : "none",
2769 x->log2_scale_factor);
2770 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2771 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2772 fprintf (stdout, " sib: base %x index %x scale %x\n",
2773 x->sib.base, x->sib.index, x->sib.scale);
2774 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2775 (x->rex & REX_W) != 0,
2776 (x->rex & REX_R) != 0,
2777 (x->rex & REX_X) != 0,
2778 (x->rex & REX_B) != 0);
09137c09 2779 for (j = 0; j < x->operands; j++)
252b5132 2780 {
09137c09
SP		 2781 fprintf (stdout, " #%d: ", j + 1);
2782 pt (x->types[j]);
252b5132 2783 fprintf (stdout, "\n");
09137c09
SP		 2784 if (x->types[j].bitfield.reg8
2785 || x->types[j].bitfield.reg16
2786 || x->types[j].bitfield.reg32
2787 || x->types[j].bitfield.reg64
2788 || x->types[j].bitfield.regmmx
2789 || x->types[j].bitfield.regxmm
2790 || x->types[j].bitfield.regymm
43234a1e 2791 || x->types[j].bitfield.regzmm
09137c09
SP		 2792 || x->types[j].bitfield.sreg2
2793 || x->types[j].bitfield.sreg3
2794 || x->types[j].bitfield.control
2795 || x->types[j].bitfield.debug
2796 || x->types[j].bitfield.test)
2797 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2798 if (operand_type_check (x->types[j], imm))
2799 pe (x->op[j].imms);
2800 if (operand_type_check (x->types[j], disp))
2801 pe (x->op[j].disps);
252b5132
RH		 2802 }
2803}
2804
2805static void
d3ce72d0 2806pte (insn_template *t)
252b5132 2807{
09137c09 2808 unsigned int j;
252b5132 2809 fprintf (stdout, " %d operands ", t->operands);
47926f60 2810 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2811 if (t->extension_opcode != None)
2812 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2813 if (t->opcode_modifier.d)
252b5132 2814 fprintf (stdout, "D");
40fb9820 2815 if (t->opcode_modifier.w)
252b5132
RH		 2816 fprintf (stdout, "W");
2817 fprintf (stdout, "\n");
09137c09 2818 for (j = 0; j < t->operands; j++)
252b5132 2819 {
09137c09
SP		 2820 fprintf (stdout, " #%d type ", j + 1);
2821 pt (t->operand_types[j]);
252b5132
RH		 2822 fprintf (stdout, "\n");
2823 }
2824}
2825
2826static void
e3bb37b5 2827pe (expressionS *e)
252b5132 2828{
24eab124 2829 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2830 fprintf (stdout, " add_number %ld (%lx)\n",
2831 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2832 if (e->X_add_symbol)
2833 {
2834 fprintf (stdout, " add_symbol ");
2835 ps (e->X_add_symbol);
2836 fprintf (stdout, "\n");
2837 }
2838 if (e->X_op_symbol)
2839 {
2840 fprintf (stdout, " op_symbol ");
2841 ps (e->X_op_symbol);
2842 fprintf (stdout, "\n");
2843 }
2844}
2845
2846static void
e3bb37b5 2847ps (symbolS *s)
252b5132
RH		 2848{
2849 fprintf (stdout, "%s type %s%s",
2850 S_GET_NAME (s),
2851 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2852 segment_name (S_GET_SEGMENT (s)));
2853}
2854
7b81dfbb 2855static struct type_name
252b5132 2856 {
40fb9820
L		 2857 i386_operand_type mask;
2858 const char *name;
252b5132 2859 }
7b81dfbb 2860const type_names[] =
252b5132 2861{
40fb9820
L		 2862 { OPERAND_TYPE_REG8, "r8" },
2863 { OPERAND_TYPE_REG16, "r16" },
2864 { OPERAND_TYPE_REG32, "r32" },
2865 { OPERAND_TYPE_REG64, "r64" },
2866 { OPERAND_TYPE_IMM8, "i8" },
2867 { OPERAND_TYPE_IMM8, "i8s" },
2868 { OPERAND_TYPE_IMM16, "i16" },
2869 { OPERAND_TYPE_IMM32, "i32" },
2870 { OPERAND_TYPE_IMM32S, "i32s" },
2871 { OPERAND_TYPE_IMM64, "i64" },
2872 { OPERAND_TYPE_IMM1, "i1" },
2873 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2874 { OPERAND_TYPE_DISP8, "d8" },
2875 { OPERAND_TYPE_DISP16, "d16" },
2876 { OPERAND_TYPE_DISP32, "d32" },
2877 { OPERAND_TYPE_DISP32S, "d32s" },
2878 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2879 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2880 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2881 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2882 { OPERAND_TYPE_CONTROL, "control reg" },
2883 { OPERAND_TYPE_TEST, "test reg" },
2884 { OPERAND_TYPE_DEBUG, "debug reg" },
2885 { OPERAND_TYPE_FLOATREG, "FReg" },
2886 { OPERAND_TYPE_FLOATACC, "FAcc" },
2887 { OPERAND_TYPE_SREG2, "SReg2" },
2888 { OPERAND_TYPE_SREG3, "SReg3" },
2889 { OPERAND_TYPE_ACC, "Acc" },
2890 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2891 { OPERAND_TYPE_REGMMX, "rMMX" },
2892 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2893 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2894 { OPERAND_TYPE_REGZMM, "rZMM" },
2895 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2896 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2897};
2898
2899static void
40fb9820 2900pt (i386_operand_type t)
252b5132 2901{
40fb9820 2902 unsigned int j;
c6fb90c8 2903 i386_operand_type a;
252b5132 2904
40fb9820 2905 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2906 {
2907 a = operand_type_and (t, type_names[j].mask);
0349dc08 2908 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2909 fprintf (stdout, "%s, ", type_names[j].name);
2910 }
252b5132
RH		 2911 fflush (stdout);
2912}
2913
2914#endif /* DEBUG386 */
2915\f
252b5132 2916static bfd_reloc_code_real_type
3956db08 2917reloc (unsigned int size,
64e74474
AM		 2918 int pcrel,
2919 int sign,
2920 bfd_reloc_code_real_type other)
252b5132 2921{
47926f60 2922 if (other != NO_RELOC)
3956db08 2923 {
91d6fa6a 2924 reloc_howto_type *rel;
3956db08
JB		 2925
2926 if (size == 8)
2927 switch (other)
2928 {
64e74474
AM		 2929 case BFD_RELOC_X86_64_GOT32:
2930 return BFD_RELOC_X86_64_GOT64;
2931 break;
553d1284
L		 2932 case BFD_RELOC_X86_64_GOTPLT64:
2933 return BFD_RELOC_X86_64_GOTPLT64;
2934 break;
64e74474
AM		 2935 case BFD_RELOC_X86_64_PLTOFF64:
2936 return BFD_RELOC_X86_64_PLTOFF64;
2937 break;
2938 case BFD_RELOC_X86_64_GOTPC32:
2939 other = BFD_RELOC_X86_64_GOTPC64;
2940 break;
2941 case BFD_RELOC_X86_64_GOTPCREL:
2942 other = BFD_RELOC_X86_64_GOTPCREL64;
2943 break;
2944 case BFD_RELOC_X86_64_TPOFF32:
2945 other = BFD_RELOC_X86_64_TPOFF64;
2946 break;
2947 case BFD_RELOC_X86_64_DTPOFF32:
2948 other = BFD_RELOC_X86_64_DTPOFF64;
2949 break;
2950 default:
2951 break;
3956db08 2952 }
e05278af 2953
8ce3d284 2954#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2955 if (other == BFD_RELOC_SIZE32)
2956 {
2957 if (size == 8)
1ab668bf 2958 other = BFD_RELOC_SIZE64;
8fd4256d 2959 if (pcrel)
1ab668bf
AM		 2960 {
2961 as_bad (_("there are no pc-relative size relocations"));
2962 return NO_RELOC;
2963 }
8fd4256d 2964 }
8ce3d284 2965#endif
8fd4256d 2966
e05278af 2967 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2968 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2969 sign = -1;
2970
91d6fa6a
NC		 2971 rel = bfd_reloc_type_lookup (stdoutput, other);
2972 if (!rel)
3956db08 2973 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2974 else if (size != bfd_get_reloc_size (rel))
3956db08 2975 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2976 bfd_get_reloc_size (rel),
3956db08 2977 size);
91d6fa6a 2978 else if (pcrel && !rel->pc_relative)
3956db08 2979 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2980 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2981 && !sign)
91d6fa6a 2982 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2983 && sign > 0))
3956db08
JB		 2984 as_bad (_("relocated field and relocation type differ in signedness"));
2985 else
2986 return other;
2987 return NO_RELOC;
2988 }
252b5132
RH		 2989
2990 if (pcrel)
2991 {
3e73aa7c 2992 if (!sign)
3956db08 2993 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2994 switch (size)
2995 {
2996 case 1: return BFD_RELOC_8_PCREL;
2997 case 2: return BFD_RELOC_16_PCREL;
d258b828 2998 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2999 case 8: return BFD_RELOC_64_PCREL;
252b5132 3000 }
3956db08 3001 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3002 }
3003 else
3004 {
3956db08 3005 if (sign > 0)
e5cb08ac 3006 switch (size)
3e73aa7c
JH		 3007 {
3008 case 4: return BFD_RELOC_X86_64_32S;
3009 }
3010 else
3011 switch (size)
3012 {
3013 case 1: return BFD_RELOC_8;
3014 case 2: return BFD_RELOC_16;
3015 case 4: return BFD_RELOC_32;
3016 case 8: return BFD_RELOC_64;
3017 }
3956db08
JB		 3018 as_bad (_("cannot do %s %u byte relocation"),
3019 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3020 }
3021
0cc9e1d3 3022 return NO_RELOC;
252b5132
RH		 3023}
3024
47926f60
KH		 3025/* Here we decide which fixups can be adjusted to make them relative to
3026 the beginning of the section instead of the symbol. Basically we need
3027 to make sure that the dynamic relocations are done correctly, so in
3028 some cases we force the original symbol to be used. */
3029
252b5132 3030int
e3bb37b5 3031tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3032{
6d249963 3033#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3034 if (!IS_ELF)
31312f95
AM		 3035 return 1;
3036
a161fe53
AM		 3037 /* Don't adjust pc-relative references to merge sections in 64-bit
3038 mode. */
3039 if (use_rela_relocations
3040 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3041 && fixP->fx_pcrel)
252b5132 3042 return 0;
31312f95 3043
8d01d9a9
AJ		 3044 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3045 and changed later by validate_fix. */
3046 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3047 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3048 return 0;
3049
8fd4256d
L		 3050 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3051 for size relocations. */
3052 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3053 || fixP->fx_r_type == BFD_RELOC_SIZE64
3054 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3055 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3056 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3057 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3058 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3059 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3060 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3061 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3062 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3063 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3064 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3065 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3066 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3067 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3068 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3069 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3070 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3071 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3072 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3073 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3074 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3075 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3076 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3077 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3078 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3079 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3080 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3081 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3082 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3083 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3084 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3085 return 0;
31312f95 3086#endif
252b5132
RH		 3087 return 1;
3088}
252b5132 3089
b4cac588 3090static int
e3bb37b5 3091intel_float_operand (const char *mnemonic)
252b5132 3092{
9306ca4a
JB		 3093 /* Note that the value returned is meaningful only for opcodes with (memory)
3094 operands, hence the code here is free to improperly handle opcodes that
3095 have no operands (for better performance and smaller code). */
3096
3097 if (mnemonic[0] != 'f')
3098 return 0; /* non-math */
3099
3100 switch (mnemonic[1])
3101 {
3102 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3103 the fs segment override prefix not currently handled because no
3104 call path can make opcodes without operands get here */
3105 case 'i':
3106 return 2 /* integer op */;
3107 case 'l':
3108 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3109 return 3; /* fldcw/fldenv */
3110 break;
3111 case 'n':
3112 if (mnemonic[2] != 'o' /* fnop */)
3113 return 3; /* non-waiting control op */
3114 break;
3115 case 'r':
3116 if (mnemonic[2] == 's')
3117 return 3; /* frstor/frstpm */
3118 break;
3119 case 's':
3120 if (mnemonic[2] == 'a')
3121 return 3; /* fsave */
3122 if (mnemonic[2] == 't')
3123 {
3124 switch (mnemonic[3])
3125 {
3126 case 'c': /* fstcw */
3127 case 'd': /* fstdw */
3128 case 'e': /* fstenv */
3129 case 's': /* fsts[gw] */
3130 return 3;
3131 }
3132 }
3133 break;
3134 case 'x':
3135 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3136 return 0; /* fxsave/fxrstor are not really math ops */
3137 break;
3138 }
252b5132 3139
9306ca4a 3140 return 1;
252b5132
RH		 3141}
3142
c0f3af97
L		 3143/* Build the VEX prefix. */
3144
3145static void
d3ce72d0 3146build_vex_prefix (const insn_template *t)
c0f3af97
L		 3147{
3148 unsigned int register_specifier;
3149 unsigned int implied_prefix;
3150 unsigned int vector_length;
3151
3152 /* Check register specifier. */
3153 if (i.vex.register_specifier)
43234a1e
L		 3154 {
3155 register_specifier =
3156 ~register_number (i.vex.register_specifier) & 0xf;
3157 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3158 }
c0f3af97
L		 3159 else
3160 register_specifier = 0xf;
3161
33eaf5de 3162 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3163 operand. */
86fa6981
L		 3164 if (i.vec_encoding != vex_encoding_vex3
3165 && i.dir_encoding == dir_encoding_default
fa99fab2 3166 && i.operands == i.reg_operands
7f399153 3167 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3168 && i.tm.opcode_modifier.load
fa99fab2
L		 3169 && i.rex == REX_B)
3170 {
3171 unsigned int xchg = i.operands - 1;
3172 union i386_op temp_op;
3173 i386_operand_type temp_type;
3174
3175 temp_type = i.types[xchg];
3176 i.types[xchg] = i.types[0];
3177 i.types[0] = temp_type;
3178 temp_op = i.op[xchg];
3179 i.op[xchg] = i.op[0];
3180 i.op[0] = temp_op;
3181
9c2799c2 3182 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3183
3184 i.rex = REX_R;
3185 xchg = i.rm.regmem;
3186 i.rm.regmem = i.rm.reg;
3187 i.rm.reg = xchg;
3188
3189 /* Use the next insn. */
3190 i.tm = t[1];
3191 }
3192
539f890d
L		 3193 if (i.tm.opcode_modifier.vex == VEXScalar)
3194 vector_length = avxscalar;
3195 else
3196 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3197
3198 switch ((i.tm.base_opcode >> 8) & 0xff)
3199 {
3200 case 0:
3201 implied_prefix = 0;
3202 break;
3203 case DATA_PREFIX_OPCODE:
3204 implied_prefix = 1;
3205 break;
3206 case REPE_PREFIX_OPCODE:
3207 implied_prefix = 2;
3208 break;
3209 case REPNE_PREFIX_OPCODE:
3210 implied_prefix = 3;
3211 break;
3212 default:
3213 abort ();
3214 }
3215
3216 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3217 if (i.vec_encoding != vex_encoding_vex3
3218 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3219 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3220 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3221 {
3222 /* 2-byte VEX prefix. */
3223 unsigned int r;
3224
3225 i.vex.length = 2;
3226 i.vex.bytes[0] = 0xc5;
3227
3228 /* Check the REX.R bit. */
3229 r = (i.rex & REX_R) ? 0 : 1;
3230 i.vex.bytes[1] = (r << 7
3231 | register_specifier << 3
3232 | vector_length << 2
3233 | implied_prefix);
3234 }
3235 else
3236 {
3237 /* 3-byte VEX prefix. */
3238 unsigned int m, w;
3239
f88c9eb0 3240 i.vex.length = 3;
f88c9eb0 3241
7f399153 3242 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3243 {
7f399153
L		 3244 case VEX0F:
3245 m = 0x1;
80de6e00 3246 i.vex.bytes[0] = 0xc4;
7f399153
L		 3247 break;
3248 case VEX0F38:
3249 m = 0x2;
80de6e00 3250 i.vex.bytes[0] = 0xc4;
7f399153
L		 3251 break;
3252 case VEX0F3A:
3253 m = 0x3;
80de6e00 3254 i.vex.bytes[0] = 0xc4;
7f399153
L		 3255 break;
3256 case XOP08:
5dd85c99
SP		 3257 m = 0x8;
3258 i.vex.bytes[0] = 0x8f;
7f399153
L		 3259 break;
3260 case XOP09:
f88c9eb0
SP		 3261 m = 0x9;
3262 i.vex.bytes[0] = 0x8f;
7f399153
L		 3263 break;
3264 case XOP0A:
f88c9eb0
SP		 3265 m = 0xa;
3266 i.vex.bytes[0] = 0x8f;
7f399153
L		 3267 break;
3268 default:
3269 abort ();
f88c9eb0 3270 }
c0f3af97 3271
c0f3af97
L		 3272 /* The high 3 bits of the second VEX byte are 1's compliment
3273 of RXB bits from REX. */
3274 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3275
3276 /* Check the REX.W bit. */
3277 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3278 if (i.tm.opcode_modifier.vexw == VEXW1)
3279 w = 1;
c0f3af97
L		 3280
3281 i.vex.bytes[2] = (w << 7
3282 | register_specifier << 3
3283 | vector_length << 2
3284 | implied_prefix);
3285 }
3286}
3287
43234a1e
L		 3288/* Build the EVEX prefix. */
3289
3290static void
3291build_evex_prefix (void)
3292{
3293 unsigned int register_specifier;
3294 unsigned int implied_prefix;
3295 unsigned int m, w;
3296 rex_byte vrex_used = 0;
3297
3298 /* Check register specifier. */
3299 if (i.vex.register_specifier)
3300 {
3301 gas_assert ((i.vrex & REX_X) == 0);
3302
3303 register_specifier = i.vex.register_specifier->reg_num;
3304 if ((i.vex.register_specifier->reg_flags & RegRex))
3305 register_specifier += 8;
3306 /* The upper 16 registers are encoded in the fourth byte of the
3307 EVEX prefix. */
3308 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3309 i.vex.bytes[3] = 0x8;
3310 register_specifier = ~register_specifier & 0xf;
3311 }
3312 else
3313 {
3314 register_specifier = 0xf;
3315
3316 /* Encode upper 16 vector index register in the fourth byte of
3317 the EVEX prefix. */
3318 if (!(i.vrex & REX_X))
3319 i.vex.bytes[3] = 0x8;
3320 else
3321 vrex_used |= REX_X;
3322 }
3323
3324 switch ((i.tm.base_opcode >> 8) & 0xff)
3325 {
3326 case 0:
3327 implied_prefix = 0;
3328 break;
3329 case DATA_PREFIX_OPCODE:
3330 implied_prefix = 1;
3331 break;
3332 case REPE_PREFIX_OPCODE:
3333 implied_prefix = 2;
3334 break;
3335 case REPNE_PREFIX_OPCODE:
3336 implied_prefix = 3;
3337 break;
3338 default:
3339 abort ();
3340 }
3341
3342 /* 4 byte EVEX prefix. */
3343 i.vex.length = 4;
3344 i.vex.bytes[0] = 0x62;
3345
3346 /* mmmm bits. */
3347 switch (i.tm.opcode_modifier.vexopcode)
3348 {
3349 case VEX0F:
3350 m = 1;
3351 break;
3352 case VEX0F38:
3353 m = 2;
3354 break;
3355 case VEX0F3A:
3356 m = 3;
3357 break;
3358 default:
3359 abort ();
3360 break;
3361 }
3362
3363 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3364 bits from REX. */
3365 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3366
3367 /* The fifth bit of the second EVEX byte is 1's compliment of the
3368 REX_R bit in VREX. */
3369 if (!(i.vrex & REX_R))
3370 i.vex.bytes[1] |= 0x10;
3371 else
3372 vrex_used |= REX_R;
3373
3374 if ((i.reg_operands + i.imm_operands) == i.operands)
3375 {
3376 /* When all operands are registers, the REX_X bit in REX is not
3377 used. We reuse it to encode the upper 16 registers, which is
3378 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3379 as 1's compliment. */
3380 if ((i.vrex & REX_B))
3381 {
3382 vrex_used |= REX_B;
3383 i.vex.bytes[1] &= ~0x40;
3384 }
3385 }
3386
3387 /* EVEX instructions shouldn't need the REX prefix. */
3388 i.vrex &= ~vrex_used;
3389 gas_assert (i.vrex == 0);
3390
3391 /* Check the REX.W bit. */
3392 w = (i.rex & REX_W) ? 1 : 0;
3393 if (i.tm.opcode_modifier.vexw)
3394 {
3395 if (i.tm.opcode_modifier.vexw == VEXW1)
3396 w = 1;
3397 }
3398 /* If w is not set it means we are dealing with WIG instruction. */
3399 else if (!w)
3400 {
3401 if (evexwig == evexw1)
3402 w = 1;
3403 }
3404
3405 /* Encode the U bit. */
3406 implied_prefix |= 0x4;
3407
3408 /* The third byte of the EVEX prefix. */
3409 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3410
3411 /* The fourth byte of the EVEX prefix. */
3412 /* The zeroing-masking bit. */
3413 if (i.mask && i.mask->zeroing)
3414 i.vex.bytes[3] |= 0x80;
3415
3416 /* Don't always set the broadcast bit if there is no RC. */
3417 if (!i.rounding)
3418 {
3419 /* Encode the vector length. */
3420 unsigned int vec_length;
3421
3422 switch (i.tm.opcode_modifier.evex)
3423 {
3424 case EVEXLIG: /* LL' is ignored */
3425 vec_length = evexlig << 5;
3426 break;
3427 case EVEX128:
3428 vec_length = 0 << 5;
3429 break;
3430 case EVEX256:
3431 vec_length = 1 << 5;
3432 break;
3433 case EVEX512:
3434 vec_length = 2 << 5;
3435 break;
3436 default:
3437 abort ();
3438 break;
3439 }
3440 i.vex.bytes[3] |= vec_length;
3441 /* Encode the broadcast bit. */
3442 if (i.broadcast)
3443 i.vex.bytes[3] |= 0x10;
3444 }
3445 else
3446 {
3447 if (i.rounding->type != saeonly)
3448 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3449 else
d3d3c6db 3450 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3451 }
3452
3453 if (i.mask && i.mask->mask)
3454 i.vex.bytes[3] |= i.mask->mask->reg_num;
3455}
3456
65da13b5
L		 3457static void
3458process_immext (void)
3459{
3460 expressionS *exp;
3461
4c692bc7
JB		 3462 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3463 && i.operands > 0)
65da13b5 3464 {
4c692bc7
JB		 3465 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3466 with an opcode suffix which is coded in the same place as an
3467 8-bit immediate field would be.
3468 Here we check those operands and remove them afterwards. */
65da13b5
L		 3469 unsigned int x;
3470
3471 for (x = 0; x < i.operands; x++)
4c692bc7 3472 if (register_number (i.op[x].regs) != x)
65da13b5 3473 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3474 register_prefix, i.op[x].regs->reg_name, x + 1,
3475 i.tm.name);
3476
3477 i.operands = 0;
65da13b5
L		 3478 }
3479
9916071f
AP		 3480 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3481 {
3482 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3483 suffix which is coded in the same place as an 8-bit immediate
3484 field would be.
3485 Here we check those operands and remove them afterwards. */
3486 unsigned int x;
3487
3488 if (i.operands != 3)
3489 abort();
3490
3491 for (x = 0; x < 2; x++)
3492 if (register_number (i.op[x].regs) != x)
3493 goto bad_register_operand;
3494
3495 /* Check for third operand for mwaitx/monitorx insn. */
3496 if (register_number (i.op[x].regs)
3497 != (x + (i.tm.extension_opcode == 0xfb)))
3498 {
3499bad_register_operand:
3500 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3501 register_prefix, i.op[x].regs->reg_name, x+1,
3502 i.tm.name);
3503 }
3504
3505 i.operands = 0;
3506 }
3507
c0f3af97 3508 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3509 which is coded in the same place as an 8-bit immediate field
3510 would be. Here we fake an 8-bit immediate operand from the
3511 opcode suffix stored in tm.extension_opcode.
3512
c1e679ec 3513 AVX instructions also use this encoding, for some of
c0f3af97 3514 3 argument instructions. */
65da13b5 3515
43234a1e 3516 gas_assert (i.imm_operands <= 1
7ab9ffdd 3517 && (i.operands <= 2
43234a1e
L		 3518 || ((i.tm.opcode_modifier.vex
3519 || i.tm.opcode_modifier.evex)
7ab9ffdd 3520 && i.operands <= 4)));
65da13b5
L		 3521
3522 exp = &im_expressions[i.imm_operands++];
3523 i.op[i.operands].imms = exp;
3524 i.types[i.operands] = imm8;
3525 i.operands++;
3526 exp->X_op = O_constant;
3527 exp->X_add_number = i.tm.extension_opcode;
3528 i.tm.extension_opcode = None;
3529}
3530
42164a71
L		 3531
3532static int
3533check_hle (void)
3534{
3535 switch (i.tm.opcode_modifier.hleprefixok)
3536 {
3537 default:
3538 abort ();
82c2def5 3539 case HLEPrefixNone:
165de32a
L		 3540 as_bad (_("invalid instruction `%s' after `%s'"),
3541 i.tm.name, i.hle_prefix);
42164a71 3542 return 0;
82c2def5 3543 case HLEPrefixLock:
42164a71
L		 3544 if (i.prefix[LOCK_PREFIX])
3545 return 1;
165de32a 3546 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3547 return 0;
82c2def5 3548 case HLEPrefixAny:
42164a71 3549 return 1;
82c2def5 3550 case HLEPrefixRelease:
42164a71
L		 3551 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3552 {
3553 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3554 i.tm.name);
3555 return 0;
3556 }
3557 if (i.mem_operands == 0
3558 || !operand_type_check (i.types[i.operands - 1], anymem))
3559 {
3560 as_bad (_("memory destination needed for instruction `%s'"
3561 " after `xrelease'"), i.tm.name);
3562 return 0;
3563 }
3564 return 1;
3565 }
3566}
3567
252b5132
RH		 3568/* This is the guts of the machine-dependent assembler. LINE points to a
3569 machine dependent instruction. This function is supposed to emit
3570 the frags/bytes it assembles to. */
3571
3572void
65da13b5 3573md_assemble (char *line)
252b5132 3574{
40fb9820 3575 unsigned int j;
83b16ac6 3576 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3577 const insn_template *t;
252b5132 3578
47926f60 3579 /* Initialize globals. */
252b5132
RH		 3580 memset (&i, '\0', sizeof (i));
3581 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3582 i.reloc[j] = NO_RELOC;
252b5132
RH		 3583 memset (disp_expressions, '\0', sizeof (disp_expressions));
3584 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3585 save_stack_p = save_stack;
252b5132
RH		 3586
3587 /* First parse an instruction mnemonic & call i386_operand for the operands.
3588 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3589 start of a (possibly prefixed) mnemonic. */
252b5132 3590
29b0f896
AM		 3591 line = parse_insn (line, mnemonic);
3592 if (line == NULL)
3593 return;
83b16ac6 3594 mnem_suffix = i.suffix;
252b5132 3595
29b0f896 3596 line = parse_operands (line, mnemonic);
ee86248c 3597 this_operand = -1;
8325cc63
JB		 3598 xfree (i.memop1_string);
3599 i.memop1_string = NULL;
29b0f896
AM		 3600 if (line == NULL)
3601 return;
252b5132 3602
29b0f896
AM		 3603 /* Now we've parsed the mnemonic into a set of templates, and have the
3604 operands at hand. */
3605
3606 /* All intel opcodes have reversed operands except for "bound" and
3607 "enter". We also don't reverse intersegment "jmp" and "call"
3608 instructions with 2 immediate operands so that the immediate segment
050dfa73 3609 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3610 if (intel_syntax
3611 && i.operands > 1
29b0f896 3612 && (strcmp (mnemonic, "bound") != 0)
30123838 3613 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3614 && !(operand_type_check (i.types[0], imm)
3615 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3616 swap_operands ();
3617
ec56d5c0
JB		 3618 /* The order of the immediates should be reversed
3619 for 2 immediates extrq and insertq instructions */
3620 if (i.imm_operands == 2
3621 && (strcmp (mnemonic, "extrq") == 0
3622 || strcmp (mnemonic, "insertq") == 0))
3623 swap_2_operands (0, 1);
3624
29b0f896
AM		 3625 if (i.imm_operands)
3626 optimize_imm ();
3627
b300c311
L		 3628 /* Don't optimize displacement for movabs since it only takes 64bit
3629 displacement. */
3630 if (i.disp_operands
a501d77e 3631 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3632 && (flag_code != CODE_64BIT
3633 || strcmp (mnemonic, "movabs") != 0))
3634 optimize_disp ();
29b0f896
AM		 3635
3636 /* Next, we find a template that matches the given insn,
3637 making sure the overlap of the given operands types is consistent
3638 with the template operand types. */
252b5132 3639
83b16ac6 3640 if (!(t = match_template (mnem_suffix)))
29b0f896 3641 return;
252b5132 3642
7bab8ab5 3643 if (sse_check != check_none
81f8a913 3644 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3645 && (i.tm.cpu_flags.bitfield.cpusse
3646 || i.tm.cpu_flags.bitfield.cpusse2
3647 || i.tm.cpu_flags.bitfield.cpusse3
3648 || i.tm.cpu_flags.bitfield.cpussse3
3649 || i.tm.cpu_flags.bitfield.cpusse4_1
3650 || i.tm.cpu_flags.bitfield.cpusse4_2))
3651 {
7bab8ab5 3652 (sse_check == check_warning
daf50ae7
L		 3653 ? as_warn
3654 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3655 }
3656
321fd21e
L		 3657 /* Zap movzx and movsx suffix. The suffix has been set from
3658 "word ptr" or "byte ptr" on the source operand in Intel syntax
3659 or extracted from mnemonic in AT&T syntax. But we'll use
3660 the destination register to choose the suffix for encoding. */
3661 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3662 {
321fd21e
L		 3663 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3664 there is no suffix, the default will be byte extension. */
3665 if (i.reg_operands != 2
3666 && !i.suffix
7ab9ffdd 3667 && intel_syntax)
321fd21e
L		 3668 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3669
3670 i.suffix = 0;
cd61ebfe 3671 }
24eab124 3672
40fb9820 3673 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3674 if (!add_prefix (FWAIT_OPCODE))
3675 return;
252b5132 3676
d5de92cf
L		 3677 /* Check if REP prefix is OK. */
3678 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3679 {
3680 as_bad (_("invalid instruction `%s' after `%s'"),
3681 i.tm.name, i.rep_prefix);
3682 return;
3683 }
3684
c1ba0266
L		 3685 /* Check for lock without a lockable instruction. Destination operand
3686 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3687 if (i.prefix[LOCK_PREFIX]
3688 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3689 || i.mem_operands == 0
3690 || (i.tm.base_opcode != 0x86
3691 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3692 {
3693 as_bad (_("expecting lockable instruction after `lock'"));
3694 return;
3695 }
3696
42164a71 3697 /* Check if HLE prefix is OK. */
165de32a 3698 if (i.hle_prefix && !check_hle ())
42164a71
L		 3699 return;
3700
7e8b059b
L		 3701 /* Check BND prefix. */
3702 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3703 as_bad (_("expecting valid branch instruction after `bnd'"));
3704
327e8c42
JB		 3705 if (i.tm.cpu_flags.bitfield.cpumpx)
3706 {
3707 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3708 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3709 else if (flag_code != CODE_16BIT
3710 ? i.prefix[ADDR_PREFIX]
3711 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3712 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3713 }
7e8b059b
L		 3714
3715 /* Insert BND prefix. */
3716 if (add_bnd_prefix
3717 && i.tm.opcode_modifier.bndprefixok
3718 && !i.prefix[BND_PREFIX])
3719 add_prefix (BND_PREFIX_OPCODE);
3720
29b0f896 3721 /* Check string instruction segment overrides. */
40fb9820 3722 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3723 {
3724 if (!check_string ())
5dd0794d 3725 return;
fc0763e6 3726 i.disp_operands = 0;
29b0f896 3727 }
5dd0794d 3728
29b0f896
AM		 3729 if (!process_suffix ())
3730 return;
e413e4e9 3731
bc0844ae
L		 3732 /* Update operand types. */
3733 for (j = 0; j < i.operands; j++)
3734 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3735
29b0f896
AM		 3736 /* Make still unresolved immediate matches conform to size of immediate
3737 given in i.suffix. */
3738 if (!finalize_imm ())
3739 return;
252b5132 3740
40fb9820 3741 if (i.types[0].bitfield.imm1)
29b0f896 3742 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3743
9afe6eb8
L		 3744 /* We only need to check those implicit registers for instructions
3745 with 3 operands or less. */
3746 if (i.operands <= 3)
3747 for (j = 0; j < i.operands; j++)
3748 if (i.types[j].bitfield.inoutportreg
3749 || i.types[j].bitfield.shiftcount
3750 || i.types[j].bitfield.acc
3751 || i.types[j].bitfield.floatacc)
3752 i.reg_operands--;
40fb9820 3753
c0f3af97
L		 3754 /* ImmExt should be processed after SSE2AVX. */
3755 if (!i.tm.opcode_modifier.sse2avx
3756 && i.tm.opcode_modifier.immext)
65da13b5 3757 process_immext ();
252b5132 3758
29b0f896
AM		 3759 /* For insns with operands there are more diddles to do to the opcode. */
3760 if (i.operands)
3761 {
3762 if (!process_operands ())
3763 return;
3764 }
40fb9820 3765 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3766 {
3767 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3768 as_warn (_("translating to `%sp'"), i.tm.name);
3769 }
252b5132 3770
9e5e5283
L		 3771 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3772 {
3773 if (flag_code == CODE_16BIT)
3774 {
3775 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3776 i.tm.name);
3777 return;
3778 }
c0f3af97 3779
9e5e5283
L		 3780 if (i.tm.opcode_modifier.vex)
3781 build_vex_prefix (t);
3782 else
3783 build_evex_prefix ();
3784 }
43234a1e 3785
5dd85c99
SP		 3786 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3787 instructions may define INT_OPCODE as well, so avoid this corner
3788 case for those instructions that use MODRM. */
3789 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3790 && !i.tm.opcode_modifier.modrm
3791 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3792 {
3793 i.tm.base_opcode = INT3_OPCODE;
3794 i.imm_operands = 0;
3795 }
252b5132 3796
40fb9820
L		 3797 if ((i.tm.opcode_modifier.jump
3798 || i.tm.opcode_modifier.jumpbyte
3799 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3800 && i.op[0].disps->X_op == O_constant)
3801 {
3802 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3803 the absolute address given by the constant. Since ix86 jumps and
3804 calls are pc relative, we need to generate a reloc. */
3805 i.op[0].disps->X_add_symbol = &abs_symbol;
3806 i.op[0].disps->X_op = O_symbol;
3807 }
252b5132 3808
40fb9820 3809 if (i.tm.opcode_modifier.rex64)
161a04f6 3810 i.rex |= REX_W;
252b5132 3811
29b0f896
AM		 3812 /* For 8 bit registers we need an empty rex prefix. Also if the
3813 instruction already has a prefix, we need to convert old
3814 registers to new ones. */
773f551c 3815
40fb9820 3816 if ((i.types[0].bitfield.reg8
29b0f896 3817 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3818 || (i.types[1].bitfield.reg8
29b0f896 3819 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3820 || ((i.types[0].bitfield.reg8
3821 || i.types[1].bitfield.reg8)
29b0f896
AM		 3822 && i.rex != 0))
3823 {
3824 int x;
726c5dcd 3825
29b0f896
AM		 3826 i.rex |= REX_OPCODE;
3827 for (x = 0; x < 2; x++)
3828 {
3829 /* Look for 8 bit operand that uses old registers. */
40fb9820 3830 if (i.types[x].bitfield.reg8
29b0f896 3831 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3832 {
29b0f896
AM		 3833 /* In case it is "hi" register, give up. */
3834 if (i.op[x].regs->reg_num > 3)
a540244d 3835 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3836 "instruction requiring REX prefix."),
a540244d 3837 register_prefix, i.op[x].regs->reg_name);
773f551c 3838
29b0f896
AM		 3839 /* Otherwise it is equivalent to the extended register.
3840 Since the encoding doesn't change this is merely
3841 cosmetic cleanup for debug output. */
3842
3843 i.op[x].regs = i.op[x].regs + 8;
773f551c 3844 }
29b0f896
AM		 3845 }
3846 }
773f551c 3847
7ab9ffdd 3848 if (i.rex != 0)
29b0f896
AM		 3849 add_prefix (REX_OPCODE | i.rex);
3850
3851 /* We are ready to output the insn. */
3852 output_insn ();
3853}
3854
3855static char *
e3bb37b5 3856parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3857{
3858 char *l = line;
3859 char *token_start = l;
3860 char *mnem_p;
5c6af06e 3861 int supported;
d3ce72d0 3862 const insn_template *t;
b6169b20 3863 char *dot_p = NULL;
29b0f896 3864
29b0f896
AM		 3865 while (1)
3866 {
3867 mnem_p = mnemonic;
3868 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3869 {
b6169b20
L		 3870 if (*mnem_p == '.')
3871 dot_p = mnem_p;
29b0f896
AM		 3872 mnem_p++;
3873 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3874 {
29b0f896
AM		 3875 as_bad (_("no such instruction: `%s'"), token_start);
3876 return NULL;
3877 }
3878 l++;
3879 }
3880 if (!is_space_char (*l)
3881 && *l != END_OF_INSN
e44823cf
JB		 3882 && (intel_syntax
3883 || (*l != PREFIX_SEPARATOR
3884 && *l != ',')))
29b0f896
AM		 3885 {
3886 as_bad (_("invalid character %s in mnemonic"),
3887 output_invalid (*l));
3888 return NULL;
3889 }
3890 if (token_start == l)
3891 {
e44823cf 3892 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3893 as_bad (_("expecting prefix; got nothing"));
3894 else
3895 as_bad (_("expecting mnemonic; got nothing"));
3896 return NULL;
3897 }
45288df1 3898
29b0f896 3899 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3900 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3901
29b0f896
AM		 3902 if (*l != END_OF_INSN
3903 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3904 && current_templates
40fb9820 3905 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3906 {
c6fb90c8 3907 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3908 {
3909 as_bad ((flag_code != CODE_64BIT
3910 ? _("`%s' is only supported in 64-bit mode")
3911 : _("`%s' is not supported in 64-bit mode")),
3912 current_templates->start->name);
3913 return NULL;
3914 }
29b0f896
AM		 3915 /* If we are in 16-bit mode, do not allow addr16 or data16.
3916 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3917 if ((current_templates->start->opcode_modifier.size16
3918 || current_templates->start->opcode_modifier.size32)
29b0f896 3919 && flag_code != CODE_64BIT
40fb9820 3920 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3921 ^ (flag_code == CODE_16BIT)))
3922 {
3923 as_bad (_("redundant %s prefix"),
3924 current_templates->start->name);
3925 return NULL;
45288df1 3926 }
86fa6981 3927 if (current_templates->start->opcode_length == 0)
29b0f896 3928 {
86fa6981
L		 3929 /* Handle pseudo prefixes. */
3930 switch (current_templates->start->base_opcode)
3931 {
3932 case 0x0:
3933 /* {disp8} */
3934 i.disp_encoding = disp_encoding_8bit;
3935 break;
3936 case 0x1:
3937 /* {disp32} */
3938 i.disp_encoding = disp_encoding_32bit;
3939 break;
3940 case 0x2:
3941 /* {load} */
3942 i.dir_encoding = dir_encoding_load;
3943 break;
3944 case 0x3:
3945 /* {store} */
3946 i.dir_encoding = dir_encoding_store;
3947 break;
3948 case 0x4:
3949 /* {vex2} */
3950 i.vec_encoding = vex_encoding_vex2;
3951 break;
3952 case 0x5:
3953 /* {vex3} */
3954 i.vec_encoding = vex_encoding_vex3;
3955 break;
3956 case 0x6:
3957 /* {evex} */
3958 i.vec_encoding = vex_encoding_evex;
3959 break;
3960 default:
3961 abort ();
3962 }
3963 }
3964 else
3965 {
3966 /* Add prefix, checking for repeated prefixes. */
3967 switch (add_prefix (current_templates->start->base_opcode))
3968 {
3969 case PREFIX_EXIST:
3970 return NULL;
3971 case PREFIX_REP:
3972 if (current_templates->start->cpu_flags.bitfield.cpuhle)
3973 i.hle_prefix = current_templates->start->name;
3974 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3975 i.bnd_prefix = current_templates->start->name;
3976 else
3977 i.rep_prefix = current_templates->start->name;
3978 break;
3979 default:
3980 break;
3981 }
29b0f896
AM		 3982 }
3983 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3984 token_start = ++l;
3985 }
3986 else
3987 break;
3988 }
45288df1 3989
30a55f88 3990 if (!current_templates)
b6169b20 3991 {
f8a5c266
L		 3992 /* Check if we should swap operand or force 32bit displacement in
3993 encoding. */
30a55f88 3994 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 3995 i.dir_encoding = dir_encoding_store;
8d63c93e 3996 else if (mnem_p - 3 == dot_p
a501d77e
L		 3997 && dot_p[1] == 'd'
3998 && dot_p[2] == '8')
3999 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4000 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4001 && dot_p[1] == 'd'
4002 && dot_p[2] == '3'
4003 && dot_p[3] == '2')
a501d77e 4004 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4005 else
4006 goto check_suffix;
4007 mnem_p = dot_p;
4008 *dot_p = '\0';
d3ce72d0 4009 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4010 }
4011
29b0f896
AM		 4012 if (!current_templates)
4013 {
b6169b20 4014check_suffix:
29b0f896
AM		 4015 /* See if we can get a match by trimming off a suffix. */
4016 switch (mnem_p[-1])
4017 {
4018 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4019 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4020 i.suffix = SHORT_MNEM_SUFFIX;
4021 else
1a0670f3 4022 /* Fall through. */
29b0f896
AM		 4023 case BYTE_MNEM_SUFFIX:
4024 case QWORD_MNEM_SUFFIX:
4025 i.suffix = mnem_p[-1];
4026 mnem_p[-1] = '\0';
d3ce72d0
NC		 4027 current_templates = (const templates *) hash_find (op_hash,
4028 mnemonic);
29b0f896
AM		 4029 break;
4030 case SHORT_MNEM_SUFFIX:
4031 case LONG_MNEM_SUFFIX:
4032 if (!intel_syntax)
4033 {
4034 i.suffix = mnem_p[-1];
4035 mnem_p[-1] = '\0';
d3ce72d0
NC		 4036 current_templates = (const templates *) hash_find (op_hash,
4037 mnemonic);
29b0f896
AM		 4038 }
4039 break;
252b5132 4040
29b0f896
AM		 4041 /* Intel Syntax. */
4042 case 'd':
4043 if (intel_syntax)
4044 {
9306ca4a 4045 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4046 i.suffix = SHORT_MNEM_SUFFIX;
4047 else
4048 i.suffix = LONG_MNEM_SUFFIX;
4049 mnem_p[-1] = '\0';
d3ce72d0
NC		 4050 current_templates = (const templates *) hash_find (op_hash,
4051 mnemonic);
29b0f896
AM		 4052 }
4053 break;
4054 }
4055 if (!current_templates)
4056 {
4057 as_bad (_("no such instruction: `%s'"), token_start);
4058 return NULL;
4059 }
4060 }
252b5132 4061
40fb9820
L		 4062 if (current_templates->start->opcode_modifier.jump
4063 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4064 {
4065 /* Check for a branch hint. We allow ",pt" and ",pn" for
4066 predict taken and predict not taken respectively.
4067 I'm not sure that branch hints actually do anything on loop
4068 and jcxz insns (JumpByte) for current Pentium4 chips. They
4069 may work in the future and it doesn't hurt to accept them
4070 now. */
4071 if (l[0] == ',' && l[1] == 'p')
4072 {
4073 if (l[2] == 't')
4074 {
4075 if (!add_prefix (DS_PREFIX_OPCODE))
4076 return NULL;
4077 l += 3;
4078 }
4079 else if (l[2] == 'n')
4080 {
4081 if (!add_prefix (CS_PREFIX_OPCODE))
4082 return NULL;
4083 l += 3;
4084 }
4085 }
4086 }
4087 /* Any other comma loses. */
4088 if (*l == ',')
4089 {
4090 as_bad (_("invalid character %s in mnemonic"),
4091 output_invalid (*l));
4092 return NULL;
4093 }
252b5132 4094
29b0f896 4095 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4096 supported = 0;
4097 for (t = current_templates->start; t < current_templates->end; ++t)
4098 {
c0f3af97
L		 4099 supported |= cpu_flags_match (t);
4100 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 4101 goto skip;
5c6af06e 4102 }
3629bb00 4103
c0f3af97 4104 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4105 {
4106 as_bad (flag_code == CODE_64BIT
4107 ? _("`%s' is not supported in 64-bit mode")
4108 : _("`%s' is only supported in 64-bit mode"),
4109 current_templates->start->name);
4110 return NULL;
4111 }
c0f3af97 4112 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4113 {
3629bb00 4114 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4115 current_templates->start->name,
41aacd83 4116 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4117 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4118 return NULL;
29b0f896 4119 }
3629bb00
L		 4120
4121skip:
4122 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4123 && (flag_code != CODE_16BIT))
29b0f896
AM		 4124 {
4125 as_warn (_("use .code16 to ensure correct addressing mode"));
4126 }
252b5132 4127
29b0f896
AM		 4128 return l;
4129}
252b5132 4130
29b0f896 4131static char *
e3bb37b5 4132parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4133{
4134 char *token_start;
3138f287 4135
29b0f896
AM		 4136 /* 1 if operand is pending after ','. */
4137 unsigned int expecting_operand = 0;
252b5132 4138
29b0f896
AM		 4139 /* Non-zero if operand parens not balanced. */
4140 unsigned int paren_not_balanced;
4141
4142 while (*l != END_OF_INSN)
4143 {
4144 /* Skip optional white space before operand. */
4145 if (is_space_char (*l))
4146 ++l;
d02603dc 4147 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4148 {
4149 as_bad (_("invalid character %s before operand %d"),
4150 output_invalid (*l),
4151 i.operands + 1);
4152 return NULL;
4153 }
d02603dc 4154 token_start = l; /* After white space. */
29b0f896
AM		 4155 paren_not_balanced = 0;
4156 while (paren_not_balanced || *l != ',')
4157 {
4158 if (*l == END_OF_INSN)
4159 {
4160 if (paren_not_balanced)
4161 {
4162 if (!intel_syntax)
4163 as_bad (_("unbalanced parenthesis in operand %d."),
4164 i.operands + 1);
4165 else
4166 as_bad (_("unbalanced brackets in operand %d."),
4167 i.operands + 1);
4168 return NULL;
4169 }
4170 else
4171 break; /* we are done */
4172 }
d02603dc 4173 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4174 {
4175 as_bad (_("invalid character %s in operand %d"),
4176 output_invalid (*l),
4177 i.operands + 1);
4178 return NULL;
4179 }
4180 if (!intel_syntax)
4181 {
4182 if (*l == '(')
4183 ++paren_not_balanced;
4184 if (*l == ')')
4185 --paren_not_balanced;
4186 }
4187 else
4188 {
4189 if (*l == '[')
4190 ++paren_not_balanced;
4191 if (*l == ']')
4192 --paren_not_balanced;
4193 }
4194 l++;
4195 }
4196 if (l != token_start)
4197 { /* Yes, we've read in another operand. */
4198 unsigned int operand_ok;
4199 this_operand = i.operands++;
4200 if (i.operands > MAX_OPERANDS)
4201 {
4202 as_bad (_("spurious operands; (%d operands/instruction max)"),
4203 MAX_OPERANDS);
4204 return NULL;
4205 }
9d46ce34 4206 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4207 /* Now parse operand adding info to 'i' as we go along. */
4208 END_STRING_AND_SAVE (l);
4209
4210 if (intel_syntax)
4211 operand_ok =
4212 i386_intel_operand (token_start,
4213 intel_float_operand (mnemonic));
4214 else
a7619375 4215 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4216
4217 RESTORE_END_STRING (l);
4218 if (!operand_ok)
4219 return NULL;
4220 }
4221 else
4222 {
4223 if (expecting_operand)
4224 {
4225 expecting_operand_after_comma:
4226 as_bad (_("expecting operand after ','; got nothing"));
4227 return NULL;
4228 }
4229 if (*l == ',')
4230 {
4231 as_bad (_("expecting operand before ','; got nothing"));
4232 return NULL;
4233 }
4234 }
7f3f1ea2 4235
29b0f896
AM		 4236 /* Now *l must be either ',' or END_OF_INSN. */
4237 if (*l == ',')
4238 {
4239 if (*++l == END_OF_INSN)
4240 {
4241 /* Just skip it, if it's \n complain. */
4242 goto expecting_operand_after_comma;
4243 }
4244 expecting_operand = 1;
4245 }
4246 }
4247 return l;
4248}
7f3f1ea2 4249
050dfa73 4250static void
4d456e3d 4251swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4252{
4253 union i386_op temp_op;
40fb9820 4254 i386_operand_type temp_type;
050dfa73 4255 enum bfd_reloc_code_real temp_reloc;
4eed87de 4256
050dfa73
MM		 4257 temp_type = i.types[xchg2];
4258 i.types[xchg2] = i.types[xchg1];
4259 i.types[xchg1] = temp_type;
4260 temp_op = i.op[xchg2];
4261 i.op[xchg2] = i.op[xchg1];
4262 i.op[xchg1] = temp_op;
4263 temp_reloc = i.reloc[xchg2];
4264 i.reloc[xchg2] = i.reloc[xchg1];
4265 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4266
4267 if (i.mask)
4268 {
4269 if (i.mask->operand == xchg1)
4270 i.mask->operand = xchg2;
4271 else if (i.mask->operand == xchg2)
4272 i.mask->operand = xchg1;
4273 }
4274 if (i.broadcast)
4275 {
4276 if (i.broadcast->operand == xchg1)
4277 i.broadcast->operand = xchg2;
4278 else if (i.broadcast->operand == xchg2)
4279 i.broadcast->operand = xchg1;
4280 }
4281 if (i.rounding)
4282 {
4283 if (i.rounding->operand == xchg1)
4284 i.rounding->operand = xchg2;
4285 else if (i.rounding->operand == xchg2)
4286 i.rounding->operand = xchg1;
4287 }
050dfa73
MM		 4288}
4289
29b0f896 4290static void
e3bb37b5 4291swap_operands (void)
29b0f896 4292{
b7c61d9a 4293 switch (i.operands)
050dfa73 4294 {
c0f3af97 4295 case 5:
b7c61d9a 4296 case 4:
4d456e3d 4297 swap_2_operands (1, i.operands - 2);
1a0670f3 4298 /* Fall through. */
b7c61d9a
L		 4299 case 3:
4300 case 2:
4d456e3d 4301 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4302 break;
4303 default:
4304 abort ();
29b0f896 4305 }
29b0f896
AM		 4306
4307 if (i.mem_operands == 2)
4308 {
4309 const seg_entry *temp_seg;
4310 temp_seg = i.seg[0];
4311 i.seg[0] = i.seg[1];
4312 i.seg[1] = temp_seg;
4313 }
4314}
252b5132 4315
29b0f896
AM		 4316/* Try to ensure constant immediates are represented in the smallest
4317 opcode possible. */
4318static void
e3bb37b5 4319optimize_imm (void)
29b0f896
AM		 4320{
4321 char guess_suffix = 0;
4322 int op;
252b5132 4323
29b0f896
AM		 4324 if (i.suffix)
4325 guess_suffix = i.suffix;
4326 else if (i.reg_operands)
4327 {
4328 /* Figure out a suffix from the last register operand specified.
4329 We can't do this properly yet, ie. excluding InOutPortReg,
4330 but the following works for instructions with immediates.
4331 In any case, we can't set i.suffix yet. */
4332 for (op = i.operands; --op >= 0;)
40fb9820 4333 if (i.types[op].bitfield.reg8)
7ab9ffdd 4334 {
40fb9820
L		 4335 guess_suffix = BYTE_MNEM_SUFFIX;
4336 break;
4337 }
4338 else if (i.types[op].bitfield.reg16)
252b5132 4339 {
40fb9820
L		 4340 guess_suffix = WORD_MNEM_SUFFIX;
4341 break;
4342 }
4343 else if (i.types[op].bitfield.reg32)
4344 {
4345 guess_suffix = LONG_MNEM_SUFFIX;
4346 break;
4347 }
4348 else if (i.types[op].bitfield.reg64)
4349 {
4350 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4351 break;
252b5132 4352 }
29b0f896
AM		 4353 }
4354 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4355 guess_suffix = WORD_MNEM_SUFFIX;
4356
4357 for (op = i.operands; --op >= 0;)
40fb9820 4358 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4359 {
4360 switch (i.op[op].imms->X_op)
252b5132 4361 {
29b0f896
AM		 4362 case O_constant:
4363 /* If a suffix is given, this operand may be shortened. */
4364 switch (guess_suffix)
252b5132 4365 {
29b0f896 4366 case LONG_MNEM_SUFFIX:
40fb9820
L		 4367 i.types[op].bitfield.imm32 = 1;
4368 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4369 break;
4370 case WORD_MNEM_SUFFIX:
40fb9820
L		 4371 i.types[op].bitfield.imm16 = 1;
4372 i.types[op].bitfield.imm32 = 1;
4373 i.types[op].bitfield.imm32s = 1;
4374 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4375 break;
4376 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4377 i.types[op].bitfield.imm8 = 1;
4378 i.types[op].bitfield.imm8s = 1;
4379 i.types[op].bitfield.imm16 = 1;
4380 i.types[op].bitfield.imm32 = 1;
4381 i.types[op].bitfield.imm32s = 1;
4382 i.types[op].bitfield.imm64 = 1;
29b0f896 4383 break;
252b5132 4384 }
252b5132 4385
29b0f896
AM		 4386 /* If this operand is at most 16 bits, convert it
4387 to a signed 16 bit number before trying to see
4388 whether it will fit in an even smaller size.
4389 This allows a 16-bit operand such as $0xffe0 to
4390 be recognised as within Imm8S range. */
40fb9820 4391 if ((i.types[op].bitfield.imm16)
29b0f896 4392 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4393 {
29b0f896
AM		 4394 i.op[op].imms->X_add_number =
4395 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4396 }
a28def75
L		 4397#ifdef BFD64
4398 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4399 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4400 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4401 == 0))
4402 {
4403 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4404 ^ ((offsetT) 1 << 31))
4405 - ((offsetT) 1 << 31));
4406 }
a28def75 4407#endif
40fb9820 4408 i.types[op]
c6fb90c8
L		 4409 = operand_type_or (i.types[op],
4410 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4411
29b0f896
AM		 4412 /* We must avoid matching of Imm32 templates when 64bit
4413 only immediate is available. */
4414 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4415 i.types[op].bitfield.imm32 = 0;
29b0f896 4416 break;
252b5132 4417
29b0f896
AM		 4418 case O_absent:
4419 case O_register:
4420 abort ();
4421
4422 /* Symbols and expressions. */
4423 default:
9cd96992
JB		 4424 /* Convert symbolic operand to proper sizes for matching, but don't
4425 prevent matching a set of insns that only supports sizes other
4426 than those matching the insn suffix. */
4427 {
40fb9820 4428 i386_operand_type mask, allowed;
d3ce72d0 4429 const insn_template *t;
9cd96992 4430
0dfbf9d7
L		 4431 operand_type_set (&mask, 0);
4432 operand_type_set (&allowed, 0);
40fb9820 4433
4eed87de
AM		 4434 for (t = current_templates->start;
4435 t < current_templates->end;
4436 ++t)
c6fb90c8
L		 4437 allowed = operand_type_or (allowed,
4438 t->operand_types[op]);
9cd96992
JB		 4439 switch (guess_suffix)
4440 {
4441 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4442 mask.bitfield.imm64 = 1;
4443 mask.bitfield.imm32s = 1;
9cd96992
JB		 4444 break;
4445 case LONG_MNEM_SUFFIX:
40fb9820 4446 mask.bitfield.imm32 = 1;
9cd96992
JB		 4447 break;
4448 case WORD_MNEM_SUFFIX:
40fb9820 4449 mask.bitfield.imm16 = 1;
9cd96992
JB		 4450 break;
4451 case BYTE_MNEM_SUFFIX:
40fb9820 4452 mask.bitfield.imm8 = 1;
9cd96992
JB		 4453 break;
4454 default:
9cd96992
JB		 4455 break;
4456 }
c6fb90c8 4457 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4458 if (!operand_type_all_zero (&allowed))
c6fb90c8 4459 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4460 }
29b0f896 4461 break;
252b5132 4462 }
29b0f896
AM		 4463 }
4464}
47926f60 4465
29b0f896
AM		 4466/* Try to use the smallest displacement type too. */
4467static void
e3bb37b5 4468optimize_disp (void)
29b0f896
AM		 4469{
4470 int op;
3e73aa7c 4471
29b0f896 4472 for (op = i.operands; --op >= 0;)
40fb9820 4473 if (operand_type_check (i.types[op], disp))
252b5132 4474 {
b300c311 4475 if (i.op[op].disps->X_op == O_constant)
252b5132 4476 {
91d6fa6a 4477 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4478
40fb9820 4479 if (i.types[op].bitfield.disp16
91d6fa6a 4480 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4481 {
4482 /* If this operand is at most 16 bits, convert
4483 to a signed 16 bit number and don't use 64bit
4484 displacement. */
91d6fa6a 4485 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4486 i.types[op].bitfield.disp64 = 0;
b300c311 4487 }
a28def75
L		 4488#ifdef BFD64
4489 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4490 if (i.types[op].bitfield.disp32
91d6fa6a 4491 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4492 {
4493 /* If this operand is at most 32 bits, convert
4494 to a signed 32 bit number and don't use 64bit
4495 displacement. */
91d6fa6a
NC		 4496 op_disp &= (((offsetT) 2 << 31) - 1);
4497 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4498 i.types[op].bitfield.disp64 = 0;
b300c311 4499 }
a28def75 4500#endif
91d6fa6a 4501 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4502 {
40fb9820
L		 4503 i.types[op].bitfield.disp8 = 0;
4504 i.types[op].bitfield.disp16 = 0;
4505 i.types[op].bitfield.disp32 = 0;
4506 i.types[op].bitfield.disp32s = 0;
4507 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4508 i.op[op].disps = 0;
4509 i.disp_operands--;
4510 }
4511 else if (flag_code == CODE_64BIT)
4512 {
91d6fa6a 4513 if (fits_in_signed_long (op_disp))
28a9d8f5 4514 {
40fb9820
L		 4515 i.types[op].bitfield.disp64 = 0;
4516 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4517 }
0e1147d9 4518 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4519 && fits_in_unsigned_long (op_disp))
40fb9820 4520 i.types[op].bitfield.disp32 = 1;
b300c311 4521 }
40fb9820
L		 4522 if ((i.types[op].bitfield.disp32
4523 || i.types[op].bitfield.disp32s
4524 || i.types[op].bitfield.disp16)
91d6fa6a 4525 && fits_in_signed_byte (op_disp))
40fb9820 4526 i.types[op].bitfield.disp8 = 1;
252b5132 4527 }
67a4f2b7
AO		 4528 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4529 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4530 {
4531 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4532 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4533 i.types[op].bitfield.disp8 = 0;
4534 i.types[op].bitfield.disp16 = 0;
4535 i.types[op].bitfield.disp32 = 0;
4536 i.types[op].bitfield.disp32s = 0;
4537 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4538 }
4539 else
b300c311 4540 /* We only support 64bit displacement on constants. */
40fb9820 4541 i.types[op].bitfield.disp64 = 0;
252b5132 4542 }
29b0f896
AM		 4543}
4544
6c30d220
L		 4545/* Check if operands are valid for the instruction. */
4546
4547static int
4548check_VecOperands (const insn_template *t)
4549{
43234a1e
L		 4550 unsigned int op;
4551
6c30d220
L		 4552 /* Without VSIB byte, we can't have a vector register for index. */
4553 if (!t->opcode_modifier.vecsib
4554 && i.index_reg
4555 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4556 || i.index_reg->reg_type.bitfield.regymm
4557 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4558 {
4559 i.error = unsupported_vector_index_register;
4560 return 1;
4561 }
4562
ad8ecc81
MZ		 4563 /* Check if default mask is allowed. */
4564 if (t->opcode_modifier.nodefmask
4565 && (!i.mask || i.mask->mask->reg_num == 0))
4566 {
4567 i.error = no_default_mask;
4568 return 1;
4569 }
4570
7bab8ab5
JB		 4571 /* For VSIB byte, we need a vector register for index, and all vector
4572 registers must be distinct. */
4573 if (t->opcode_modifier.vecsib)
4574 {
4575 if (!i.index_reg
6c30d220
L		 4576 || !((t->opcode_modifier.vecsib == VecSIB128
4577 && i.index_reg->reg_type.bitfield.regxmm)
4578 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4579 && i.index_reg->reg_type.bitfield.regymm)
4580 || (t->opcode_modifier.vecsib == VecSIB512
4581 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4582 {
4583 i.error = invalid_vsib_address;
4584 return 1;
4585 }
4586
43234a1e
L		 4587 gas_assert (i.reg_operands == 2 || i.mask);
4588 if (i.reg_operands == 2 && !i.mask)
4589 {
4590 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4591 || i.types[0].bitfield.regymm);
43234a1e 4592 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4593 || i.types[2].bitfield.regymm);
43234a1e
L		 4594 if (operand_check == check_none)
4595 return 0;
4596 if (register_number (i.op[0].regs)
4597 != register_number (i.index_reg)
4598 && register_number (i.op[2].regs)
4599 != register_number (i.index_reg)
4600 && register_number (i.op[0].regs)
4601 != register_number (i.op[2].regs))
4602 return 0;
4603 if (operand_check == check_error)
4604 {
4605 i.error = invalid_vector_register_set;
4606 return 1;
4607 }
4608 as_warn (_("mask, index, and destination registers should be distinct"));
4609 }
8444f82a
MZ		 4610 else if (i.reg_operands == 1 && i.mask)
4611 {
4612 if ((i.types[1].bitfield.regymm
4613 || i.types[1].bitfield.regzmm)
4614 && (register_number (i.op[1].regs)
4615 == register_number (i.index_reg)))
4616 {
4617 if (operand_check == check_error)
4618 {
4619 i.error = invalid_vector_register_set;
4620 return 1;
4621 }
4622 if (operand_check != check_none)
4623 as_warn (_("index and destination registers should be distinct"));
4624 }
4625 }
43234a1e 4626 }
7bab8ab5 4627
43234a1e
L		 4628 /* Check if broadcast is supported by the instruction and is applied
4629 to the memory operand. */
4630 if (i.broadcast)
4631 {
4632 int broadcasted_opnd_size;
4633
4634 /* Check if specified broadcast is supported in this instruction,
4635 and it's applied to memory operand of DWORD or QWORD type,
4636 depending on VecESize. */
4637 if (i.broadcast->type != t->opcode_modifier.broadcast
4638 || !i.types[i.broadcast->operand].bitfield.mem
4639 || (t->opcode_modifier.vecesize == 0
4640 && !i.types[i.broadcast->operand].bitfield.dword
4641 && !i.types[i.broadcast->operand].bitfield.unspecified)
4642 || (t->opcode_modifier.vecesize == 1
4643 && !i.types[i.broadcast->operand].bitfield.qword
4644 && !i.types[i.broadcast->operand].bitfield.unspecified))
4645 goto bad_broadcast;
4646
4647 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4648 if (i.broadcast->type == BROADCAST_1TO16)
4649 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4650 else if (i.broadcast->type == BROADCAST_1TO8)
4651 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4652 else if (i.broadcast->type == BROADCAST_1TO4)
4653 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4654 else if (i.broadcast->type == BROADCAST_1TO2)
4655 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4656 else
4657 goto bad_broadcast;
4658
4659 if ((broadcasted_opnd_size == 256
4660 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4661 || (broadcasted_opnd_size == 512
4662 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4663 {
4664 bad_broadcast:
4665 i.error = unsupported_broadcast;
4666 return 1;
4667 }
4668 }
4669 /* If broadcast is supported in this instruction, we need to check if
4670 operand of one-element size isn't specified without broadcast. */
4671 else if (t->opcode_modifier.broadcast && i.mem_operands)
4672 {
4673 /* Find memory operand. */
4674 for (op = 0; op < i.operands; op++)
4675 if (operand_type_check (i.types[op], anymem))
4676 break;
4677 gas_assert (op < i.operands);
4678 /* Check size of the memory operand. */
4679 if ((t->opcode_modifier.vecesize == 0
4680 && i.types[op].bitfield.dword)
4681 || (t->opcode_modifier.vecesize == 1
4682 && i.types[op].bitfield.qword))
4683 {
4684 i.error = broadcast_needed;
4685 return 1;
4686 }
4687 }
4688
4689 /* Check if requested masking is supported. */
4690 if (i.mask
4691 && (!t->opcode_modifier.masking
4692 || (i.mask->zeroing
4693 && t->opcode_modifier.masking == MERGING_MASKING)))
4694 {
4695 i.error = unsupported_masking;
4696 return 1;
4697 }
4698
4699 /* Check if masking is applied to dest operand. */
4700 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4701 {
4702 i.error = mask_not_on_destination;
4703 return 1;
4704 }
4705
43234a1e
L		 4706 /* Check RC/SAE. */
4707 if (i.rounding)
4708 {
4709 if ((i.rounding->type != saeonly
4710 && !t->opcode_modifier.staticrounding)
4711 || (i.rounding->type == saeonly
4712 && (t->opcode_modifier.staticrounding
4713 || !t->opcode_modifier.sae)))
4714 {
4715 i.error = unsupported_rc_sae;
4716 return 1;
4717 }
4718 /* If the instruction has several immediate operands and one of
4719 them is rounding, the rounding operand should be the last
4720 immediate operand. */
4721 if (i.imm_operands > 1
4722 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4723 {
43234a1e 4724 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4725 return 1;
4726 }
6c30d220
L		 4727 }
4728
43234a1e
L		 4729 /* Check vector Disp8 operand. */
4730 if (t->opcode_modifier.disp8memshift)
4731 {
4732 if (i.broadcast)
4733 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4734 else
4735 i.memshift = t->opcode_modifier.disp8memshift;
4736
4737 for (op = 0; op < i.operands; op++)
4738 if (operand_type_check (i.types[op], disp)
4739 && i.op[op].disps->X_op == O_constant)
4740 {
4741 offsetT value = i.op[op].disps->X_add_number;
5be33403
L		 4742 int vec_disp8_ok
4743 = (i.disp_encoding != disp_encoding_32bit
4744 && fits_in_vec_disp8 (value));
43234a1e
L		 4745 if (t->operand_types [op].bitfield.vec_disp8)
4746 {
4747 if (vec_disp8_ok)
4748 i.types[op].bitfield.vec_disp8 = 1;
4749 else
4750 {
4751 /* Vector insn can only have Vec_Disp8/Disp32 in
4752 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4753 mode. */
4754 i.types[op].bitfield.disp8 = 0;
4755 if (flag_code != CODE_16BIT)
4756 i.types[op].bitfield.disp16 = 0;
4757 }
4758 }
4759 else if (flag_code != CODE_16BIT)
4760 {
4761 /* One form of this instruction supports vector Disp8.
4762 Try vector Disp8 if we need to use Disp32. */
4763 if (vec_disp8_ok && !fits_in_signed_byte (value))
4764 {
4765 i.error = try_vector_disp8;
4766 return 1;
4767 }
4768 }
4769 }
4770 }
4771 else
4772 i.memshift = -1;
4773
6c30d220
L		 4774 return 0;
4775}
4776
43f3e2ee 4777/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4778 operand types. */
4779
4780static int
4781VEX_check_operands (const insn_template *t)
4782{
86fa6981 4783 if (i.vec_encoding == vex_encoding_evex)
43234a1e 4784 {
86fa6981
L		 4785 /* This instruction must be encoded with EVEX prefix. */
4786 if (!t->opcode_modifier.evex)
4787 {
4788 i.error = unsupported;
4789 return 1;
4790 }
4791 return 0;
43234a1e
L		 4792 }
4793
a683cc34 4794 if (!t->opcode_modifier.vex)
86fa6981
L		 4795 {
4796 /* This instruction template doesn't have VEX prefix. */
4797 if (i.vec_encoding != vex_encoding_default)
4798 {
4799 i.error = unsupported;
4800 return 1;
4801 }
4802 return 0;
4803 }
a683cc34
SP		 4804
4805 /* Only check VEX_Imm4, which must be the first operand. */
4806 if (t->operand_types[0].bitfield.vec_imm4)
4807 {
4808 if (i.op[0].imms->X_op != O_constant
4809 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4810 {
a65babc9 4811 i.error = bad_imm4;
891edac4
L		 4812 return 1;
4813 }
a683cc34
SP		 4814
4815 /* Turn off Imm8 so that update_imm won't complain. */
4816 i.types[0] = vec_imm4;
4817 }
4818
4819 return 0;
4820}
4821
d3ce72d0 4822static const insn_template *
83b16ac6 4823match_template (char mnem_suffix)
29b0f896
AM		 4824{
4825 /* Points to template once we've found it. */
d3ce72d0 4826 const insn_template *t;
40fb9820 4827 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4828 i386_operand_type overlap4;
29b0f896 4829 unsigned int found_reverse_match;
83b16ac6 4830 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 4831 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4832 int addr_prefix_disp;
a5c311ca 4833 unsigned int j;
3629bb00 4834 unsigned int found_cpu_match;
45664ddb 4835 unsigned int check_register;
5614d22c 4836 enum i386_error specific_error = 0;
29b0f896 4837
c0f3af97
L		 4838#if MAX_OPERANDS != 5
4839# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4840#endif
4841
29b0f896 4842 found_reverse_match = 0;
539e75ad 4843 addr_prefix_disp = -1;
40fb9820
L		 4844
4845 memset (&suffix_check, 0, sizeof (suffix_check));
4846 if (i.suffix == BYTE_MNEM_SUFFIX)
4847 suffix_check.no_bsuf = 1;
4848 else if (i.suffix == WORD_MNEM_SUFFIX)
4849 suffix_check.no_wsuf = 1;
4850 else if (i.suffix == SHORT_MNEM_SUFFIX)
4851 suffix_check.no_ssuf = 1;
4852 else if (i.suffix == LONG_MNEM_SUFFIX)
4853 suffix_check.no_lsuf = 1;
4854 else if (i.suffix == QWORD_MNEM_SUFFIX)
4855 suffix_check.no_qsuf = 1;
4856 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4857 suffix_check.no_ldsuf = 1;
29b0f896 4858
83b16ac6
JB		 4859 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4860 if (intel_syntax)
4861 {
4862 switch (mnem_suffix)
4863 {
4864 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4865 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4866 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4867 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4868 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4869 }
4870 }
4871
01559ecc
L		 4872 /* Must have right number of operands. */
4873 i.error = number_of_operands_mismatch;
4874
45aa61fe 4875 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4876 {
539e75ad
L		 4877 addr_prefix_disp = -1;
4878
29b0f896
AM		 4879 if (i.operands != t->operands)
4880 continue;
4881
50aecf8c 4882 /* Check processor support. */
a65babc9 4883 i.error = unsupported;
c0f3af97
L		 4884 found_cpu_match = (cpu_flags_match (t)
4885 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4886 if (!found_cpu_match)
4887 continue;
4888
e1d4d893 4889 /* Check old gcc support. */
a65babc9 4890 i.error = old_gcc_only;
e1d4d893
L		 4891 if (!old_gcc && t->opcode_modifier.oldgcc)
4892 continue;
4893
4894 /* Check AT&T mnemonic. */
a65babc9 4895 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4896 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4897 continue;
4898
e92bae62 4899 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 4900 i.error = unsupported_syntax;
5c07affc 4901 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 4902 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4903 || (intel64 && t->opcode_modifier.amd64)
4904 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 4905 continue;
4906
20592a94 4907 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4908 i.error = invalid_instruction_suffix;
567e4e96
L		 4909 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4910 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4911 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4912 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4913 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4914 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4915 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 4916 continue;
83b16ac6
JB		 4917 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4918 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4919 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4920 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4921 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4922 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4923 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4924 continue;
29b0f896 4925
5c07affc 4926 if (!operand_size_match (t))
7d5e4556 4927 continue;
539e75ad 4928
5c07affc
L		 4929 for (j = 0; j < MAX_OPERANDS; j++)
4930 operand_types[j] = t->operand_types[j];
4931
45aa61fe
AM		 4932 /* In general, don't allow 64-bit operands in 32-bit mode. */
4933 if (i.suffix == QWORD_MNEM_SUFFIX
4934 && flag_code != CODE_64BIT
4935 && (intel_syntax
40fb9820 4936 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4937 && !intel_float_operand (t->name))
4938 : intel_float_operand (t->name) != 2)
40fb9820 4939 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4940 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4941 && !operand_types[0].bitfield.regymm
4942 && !operand_types[0].bitfield.regzmm)
40fb9820 4943 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4944 && operand_types[t->operands > 1].bitfield.regxmm
4945 && operand_types[t->operands > 1].bitfield.regymm
4946 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4947 && (t->base_opcode != 0x0fc7
4948 || t->extension_opcode != 1 /* cmpxchg8b */))
4949 continue;
4950
192dc9c6
JB		 4951 /* In general, don't allow 32-bit operands on pre-386. */
4952 else if (i.suffix == LONG_MNEM_SUFFIX
4953 && !cpu_arch_flags.bitfield.cpui386
4954 && (intel_syntax
4955 ? (!t->opcode_modifier.ignoresize
4956 && !intel_float_operand (t->name))
4957 : intel_float_operand (t->name) != 2)
4958 && ((!operand_types[0].bitfield.regmmx
4959 && !operand_types[0].bitfield.regxmm)
4960 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4961 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4962 continue;
4963
29b0f896 4964 /* Do not verify operands when there are none. */
50aecf8c 4965 else
29b0f896 4966 {
c6fb90c8 4967 if (!t->operands)
2dbab7d5
L		 4968 /* We've found a match; break out of loop. */
4969 break;
29b0f896 4970 }
252b5132 4971
539e75ad
L		 4972 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4973 into Disp32/Disp16/Disp32 operand. */
4974 if (i.prefix[ADDR_PREFIX] != 0)
4975 {
40fb9820 4976 /* There should be only one Disp operand. */
539e75ad
L		 4977 switch (flag_code)
4978 {
4979 case CODE_16BIT:
40fb9820
L		 4980 for (j = 0; j < MAX_OPERANDS; j++)
4981 {
4982 if (operand_types[j].bitfield.disp16)
4983 {
4984 addr_prefix_disp = j;
4985 operand_types[j].bitfield.disp32 = 1;
4986 operand_types[j].bitfield.disp16 = 0;
4987 break;
4988 }
4989 }
539e75ad
L		 4990 break;
4991 case CODE_32BIT:
40fb9820
L		 4992 for (j = 0; j < MAX_OPERANDS; j++)
4993 {
4994 if (operand_types[j].bitfield.disp32)
4995 {
4996 addr_prefix_disp = j;
4997 operand_types[j].bitfield.disp32 = 0;
4998 operand_types[j].bitfield.disp16 = 1;
4999 break;
5000 }
5001 }
539e75ad
L		 5002 break;
5003 case CODE_64BIT:
40fb9820
L		 5004 for (j = 0; j < MAX_OPERANDS; j++)
5005 {
5006 if (operand_types[j].bitfield.disp64)
5007 {
5008 addr_prefix_disp = j;
5009 operand_types[j].bitfield.disp64 = 0;
5010 operand_types[j].bitfield.disp32 = 1;
5011 break;
5012 }
5013 }
539e75ad
L		 5014 break;
5015 }
539e75ad
L		 5016 }
5017
02a86693
L		 5018 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5019 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5020 continue;
5021
56ffb741
L		 5022 /* We check register size if needed. */
5023 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 5024 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5025 switch (t->operands)
5026 {
5027 case 1:
40fb9820 5028 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5029 continue;
5030 break;
5031 case 2:
33eaf5de 5032 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5033 only in 32bit mode and we can use opcode 0x90. In 64bit
5034 mode, we can't use 0x90 for xchg %eax, %eax since it should
5035 zero-extend %eax to %rax. */
5036 if (flag_code == CODE_64BIT
5037 && t->base_opcode == 0x90
0dfbf9d7
L		 5038 && operand_type_equal (&i.types [0], &acc32)
5039 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5040 continue;
86fa6981
L		 5041 /* If we want store form, we reverse direction of operands. */
5042 if (i.dir_encoding == dir_encoding_store
5043 && t->opcode_modifier.d)
5044 goto check_reverse;
1a0670f3 5045 /* Fall through. */
b6169b20 5046
29b0f896 5047 case 3:
86fa6981
L		 5048 /* If we want store form, we skip the current load. */
5049 if (i.dir_encoding == dir_encoding_store
5050 && i.mem_operands == 0
5051 && t->opcode_modifier.load)
fa99fab2 5052 continue;
1a0670f3 5053 /* Fall through. */
f48ff2ae 5054 case 4:
c0f3af97 5055 case 5:
c6fb90c8 5056 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5057 if (!operand_type_match (overlap0, i.types[0])
5058 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 5059 || (check_register
5060 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 5061 operand_types[0],
5062 overlap1, i.types[1],
5063 operand_types[1])))
29b0f896
AM		 5064 {
5065 /* Check if other direction is valid ... */
40fb9820 5066 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 5067 continue;
5068
b6169b20 5069check_reverse:
29b0f896 5070 /* Try reversing direction of operands. */
c6fb90c8
L		 5071 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5072 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5073 if (!operand_type_match (overlap0, i.types[0])
5074 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 5075 || (check_register
5076 && !operand_type_register_match (overlap0,
5077 i.types[0],
5078 operand_types[1],
5079 overlap1,
5080 i.types[1],
5081 operand_types[0])))
29b0f896
AM		 5082 {
5083 /* Does not match either direction. */
5084 continue;
5085 }
5086 /* found_reverse_match holds which of D or FloatDR
5087 we've found. */
40fb9820 5088 if (t->opcode_modifier.d)
8a2ed489 5089 found_reverse_match = Opcode_D;
40fb9820 5090 else if (t->opcode_modifier.floatd)
8a2ed489
L		 5091 found_reverse_match = Opcode_FloatD;
5092 else
5093 found_reverse_match = 0;
40fb9820 5094 if (t->opcode_modifier.floatr)
8a2ed489 5095 found_reverse_match |= Opcode_FloatR;
29b0f896 5096 }
f48ff2ae 5097 else
29b0f896 5098 {
f48ff2ae 5099 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5100 switch (t->operands)
5101 {
c0f3af97
L		 5102 case 5:
5103 overlap4 = operand_type_and (i.types[4],
5104 operand_types[4]);
1a0670f3 5105 /* Fall through. */
d1cbb4db 5106 case 4:
c6fb90c8
L		 5107 overlap3 = operand_type_and (i.types[3],
5108 operand_types[3]);
1a0670f3 5109 /* Fall through. */
d1cbb4db 5110 case 3:
c6fb90c8
L		 5111 overlap2 = operand_type_and (i.types[2],
5112 operand_types[2]);
d1cbb4db
L		 5113 break;
5114 }
29b0f896 5115
f48ff2ae
L		 5116 switch (t->operands)
5117 {
c0f3af97
L		 5118 case 5:
5119 if (!operand_type_match (overlap4, i.types[4])
5120 || !operand_type_register_match (overlap3,
5121 i.types[3],
5122 operand_types[3],
5123 overlap4,
5124 i.types[4],
5125 operand_types[4]))
5126 continue;
1a0670f3 5127 /* Fall through. */
f48ff2ae 5128 case 4:
40fb9820 5129 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 5130 || (check_register
5131 && !operand_type_register_match (overlap2,
5132 i.types[2],
5133 operand_types[2],
5134 overlap3,
5135 i.types[3],
5136 operand_types[3])))
f48ff2ae 5137 continue;
1a0670f3 5138 /* Fall through. */
f48ff2ae
L		 5139 case 3:
5140 /* Here we make use of the fact that there are no
5141 reverse match 3 operand instructions, and all 3
5142 operand instructions only need to be checked for
5143 register consistency between operands 2 and 3. */
40fb9820 5144 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 5145 || (check_register
5146 && !operand_type_register_match (overlap1,
5147 i.types[1],
5148 operand_types[1],
5149 overlap2,
5150 i.types[2],
5151 operand_types[2])))
f48ff2ae
L		 5152 continue;
5153 break;
5154 }
29b0f896 5155 }
f48ff2ae 5156 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5157 slip through to break. */
5158 }
3629bb00 5159 if (!found_cpu_match)
29b0f896
AM		 5160 {
5161 found_reverse_match = 0;
5162 continue;
5163 }
c0f3af97 5164
5614d22c
JB		 5165 /* Check if vector and VEX operands are valid. */
5166 if (check_VecOperands (t) || VEX_check_operands (t))
5167 {
5168 specific_error = i.error;
5169 continue;
5170 }
a683cc34 5171
29b0f896
AM		 5172 /* We've found a match; break out of loop. */
5173 break;
5174 }
5175
5176 if (t == current_templates->end)
5177 {
5178 /* We found no match. */
a65babc9 5179 const char *err_msg;
5614d22c 5180 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5181 {
5182 default:
5183 abort ();
86e026a4 5184 case operand_size_mismatch:
a65babc9
L		 5185 err_msg = _("operand size mismatch");
5186 break;
5187 case operand_type_mismatch:
5188 err_msg = _("operand type mismatch");
5189 break;
5190 case register_type_mismatch:
5191 err_msg = _("register type mismatch");
5192 break;
5193 case number_of_operands_mismatch:
5194 err_msg = _("number of operands mismatch");
5195 break;
5196 case invalid_instruction_suffix:
5197 err_msg = _("invalid instruction suffix");
5198 break;
5199 case bad_imm4:
4a2608e3 5200 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5201 break;
5202 case old_gcc_only:
5203 err_msg = _("only supported with old gcc");
5204 break;
5205 case unsupported_with_intel_mnemonic:
5206 err_msg = _("unsupported with Intel mnemonic");
5207 break;
5208 case unsupported_syntax:
5209 err_msg = _("unsupported syntax");
5210 break;
5211 case unsupported:
35262a23 5212 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5213 current_templates->start->name);
5214 return NULL;
6c30d220
L		 5215 case invalid_vsib_address:
5216 err_msg = _("invalid VSIB address");
5217 break;
7bab8ab5
JB		 5218 case invalid_vector_register_set:
5219 err_msg = _("mask, index, and destination registers must be distinct");
5220 break;
6c30d220
L		 5221 case unsupported_vector_index_register:
5222 err_msg = _("unsupported vector index register");
5223 break;
43234a1e
L		 5224 case unsupported_broadcast:
5225 err_msg = _("unsupported broadcast");
5226 break;
5227 case broadcast_not_on_src_operand:
5228 err_msg = _("broadcast not on source memory operand");
5229 break;
5230 case broadcast_needed:
5231 err_msg = _("broadcast is needed for operand of such type");
5232 break;
5233 case unsupported_masking:
5234 err_msg = _("unsupported masking");
5235 break;
5236 case mask_not_on_destination:
5237 err_msg = _("mask not on destination operand");
5238 break;
5239 case no_default_mask:
5240 err_msg = _("default mask isn't allowed");
5241 break;
5242 case unsupported_rc_sae:
5243 err_msg = _("unsupported static rounding/sae");
5244 break;
5245 case rc_sae_operand_not_last_imm:
5246 if (intel_syntax)
5247 err_msg = _("RC/SAE operand must precede immediate operands");
5248 else
5249 err_msg = _("RC/SAE operand must follow immediate operands");
5250 break;
5251 case invalid_register_operand:
5252 err_msg = _("invalid register operand");
5253 break;
a65babc9
L		 5254 }
5255 as_bad (_("%s for `%s'"), err_msg,
891edac4 5256 current_templates->start->name);
fa99fab2 5257 return NULL;
29b0f896 5258 }
252b5132 5259
29b0f896
AM		 5260 if (!quiet_warnings)
5261 {
5262 if (!intel_syntax
40fb9820
L		 5263 && (i.types[0].bitfield.jumpabsolute
5264 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5265 {
5266 as_warn (_("indirect %s without `*'"), t->name);
5267 }
5268
40fb9820
L		 5269 if (t->opcode_modifier.isprefix
5270 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5271 {
5272 /* Warn them that a data or address size prefix doesn't
5273 affect assembly of the next line of code. */
5274 as_warn (_("stand-alone `%s' prefix"), t->name);
5275 }
5276 }
5277
5278 /* Copy the template we found. */
5279 i.tm = *t;
539e75ad
L		 5280
5281 if (addr_prefix_disp != -1)
5282 i.tm.operand_types[addr_prefix_disp]
5283 = operand_types[addr_prefix_disp];
5284
29b0f896
AM		 5285 if (found_reverse_match)
5286 {
5287 /* If we found a reverse match we must alter the opcode
5288 direction bit. found_reverse_match holds bits to change
5289 (different for int & float insns). */
5290
5291 i.tm.base_opcode ^= found_reverse_match;
5292
539e75ad
L		 5293 i.tm.operand_types[0] = operand_types[1];
5294 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5295 }
5296
fa99fab2 5297 return t;
29b0f896
AM		 5298}
5299
5300static int
e3bb37b5 5301check_string (void)
29b0f896 5302{
40fb9820
L		 5303 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5304 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5305 {
5306 if (i.seg[0] != NULL && i.seg[0] != &es)
5307 {
a87af027 5308 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5309 i.tm.name,
a87af027
JB		 5310 mem_op + 1,
5311 register_prefix);
29b0f896
AM		 5312 return 0;
5313 }
5314 /* There's only ever one segment override allowed per instruction.
5315 This instruction possibly has a legal segment override on the
5316 second operand, so copy the segment to where non-string
5317 instructions store it, allowing common code. */
5318 i.seg[0] = i.seg[1];
5319 }
40fb9820 5320 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5321 {
5322 if (i.seg[1] != NULL && i.seg[1] != &es)
5323 {
a87af027 5324 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5325 i.tm.name,
a87af027
JB		 5326 mem_op + 2,
5327 register_prefix);
29b0f896
AM		 5328 return 0;
5329 }
5330 }
5331 return 1;
5332}
5333
5334static int
543613e9 5335process_suffix (void)
29b0f896
AM		 5336{
5337 /* If matched instruction specifies an explicit instruction mnemonic
5338 suffix, use it. */
40fb9820
L		 5339 if (i.tm.opcode_modifier.size16)
5340 i.suffix = WORD_MNEM_SUFFIX;
5341 else if (i.tm.opcode_modifier.size32)
5342 i.suffix = LONG_MNEM_SUFFIX;
5343 else if (i.tm.opcode_modifier.size64)
5344 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5345 else if (i.reg_operands)
5346 {
5347 /* If there's no instruction mnemonic suffix we try to invent one
5348 based on register operands. */
5349 if (!i.suffix)
5350 {
5351 /* We take i.suffix from the last register operand specified,
5352 Destination register type is more significant than source
381d071f
L		 5353 register type. crc32 in SSE4.2 prefers source register
5354 type. */
5355 if (i.tm.base_opcode == 0xf20f38f1)
5356 {
40fb9820
L		 5357 if (i.types[0].bitfield.reg16)
5358 i.suffix = WORD_MNEM_SUFFIX;
5359 else if (i.types[0].bitfield.reg32)
5360 i.suffix = LONG_MNEM_SUFFIX;
5361 else if (i.types[0].bitfield.reg64)
5362 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5363 }
9344ff29 5364 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5365 {
40fb9820 5366 if (i.types[0].bitfield.reg8)
20592a94
L		 5367 i.suffix = BYTE_MNEM_SUFFIX;
5368 }
381d071f
L		 5369
5370 if (!i.suffix)
5371 {
5372 int op;
5373
20592a94
L		 5374 if (i.tm.base_opcode == 0xf20f38f1
5375 || i.tm.base_opcode == 0xf20f38f0)
5376 {
5377 /* We have to know the operand size for crc32. */
5378 as_bad (_("ambiguous memory operand size for `%s`"),
5379 i.tm.name);
5380 return 0;
5381 }
5382
381d071f 5383 for (op = i.operands; --op >= 0;)
40fb9820 5384 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5385 {
40fb9820
L		 5386 if (i.types[op].bitfield.reg8)
5387 {
5388 i.suffix = BYTE_MNEM_SUFFIX;
5389 break;
5390 }
5391 else if (i.types[op].bitfield.reg16)
5392 {
5393 i.suffix = WORD_MNEM_SUFFIX;
5394 break;
5395 }
5396 else if (i.types[op].bitfield.reg32)
5397 {
5398 i.suffix = LONG_MNEM_SUFFIX;
5399 break;
5400 }
5401 else if (i.types[op].bitfield.reg64)
5402 {
5403 i.suffix = QWORD_MNEM_SUFFIX;
5404 break;
5405 }
381d071f
L		 5406 }
5407 }
29b0f896
AM		 5408 }
5409 else if (i.suffix == BYTE_MNEM_SUFFIX)
5410 {
2eb952a4
L		 5411 if (intel_syntax
5412 && i.tm.opcode_modifier.ignoresize
5413 && i.tm.opcode_modifier.no_bsuf)
5414 i.suffix = 0;
5415 else if (!check_byte_reg ())
29b0f896
AM		 5416 return 0;
5417 }
5418 else if (i.suffix == LONG_MNEM_SUFFIX)
5419 {
2eb952a4
L		 5420 if (intel_syntax
5421 && i.tm.opcode_modifier.ignoresize
5422 && i.tm.opcode_modifier.no_lsuf)
5423 i.suffix = 0;
5424 else if (!check_long_reg ())
29b0f896
AM		 5425 return 0;
5426 }
5427 else if (i.suffix == QWORD_MNEM_SUFFIX)
5428 {
955e1e6a
L		 5429 if (intel_syntax
5430 && i.tm.opcode_modifier.ignoresize
5431 && i.tm.opcode_modifier.no_qsuf)
5432 i.suffix = 0;
5433 else if (!check_qword_reg ())
29b0f896
AM		 5434 return 0;
5435 }
5436 else if (i.suffix == WORD_MNEM_SUFFIX)
5437 {
2eb952a4
L		 5438 if (intel_syntax
5439 && i.tm.opcode_modifier.ignoresize
5440 && i.tm.opcode_modifier.no_wsuf)
5441 i.suffix = 0;
5442 else if (!check_word_reg ())
29b0f896
AM		 5443 return 0;
5444 }
c0f3af97 5445 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5446 || i.suffix == YMMWORD_MNEM_SUFFIX
5447 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5448 {
43234a1e 5449 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5450 should check if it is a valid suffix. */
5451 }
40fb9820 5452 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5453 /* Do nothing if the instruction is going to ignore the prefix. */
5454 ;
5455 else
5456 abort ();
5457 }
40fb9820 5458 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5459 && !i.suffix
5460 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5461 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5462 {
5463 i.suffix = stackop_size;
5464 }
9306ca4a
JB		 5465 else if (intel_syntax
5466 && !i.suffix
40fb9820
L		 5467 && (i.tm.operand_types[0].bitfield.jumpabsolute
5468 || i.tm.opcode_modifier.jumpbyte
5469 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5470 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5471 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5472 {
5473 switch (flag_code)
5474 {
5475 case CODE_64BIT:
40fb9820 5476 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5477 {
5478 i.suffix = QWORD_MNEM_SUFFIX;
5479 break;
5480 }
1a0670f3 5481 /* Fall through. */
9306ca4a 5482 case CODE_32BIT:
40fb9820 5483 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5484 i.suffix = LONG_MNEM_SUFFIX;
5485 break;
5486 case CODE_16BIT:
40fb9820 5487 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5488 i.suffix = WORD_MNEM_SUFFIX;
5489 break;
5490 }
5491 }
252b5132 5492
9306ca4a 5493 if (!i.suffix)
29b0f896 5494 {
9306ca4a
JB		 5495 if (!intel_syntax)
5496 {
40fb9820 5497 if (i.tm.opcode_modifier.w)
9306ca4a 5498 {
4eed87de
AM		 5499 as_bad (_("no instruction mnemonic suffix given and "
5500 "no register operands; can't size instruction"));
9306ca4a
JB		 5501 return 0;
5502 }
5503 }
5504 else
5505 {
40fb9820 5506 unsigned int suffixes;
7ab9ffdd 5507
40fb9820
L		 5508 suffixes = !i.tm.opcode_modifier.no_bsuf;
5509 if (!i.tm.opcode_modifier.no_wsuf)
5510 suffixes |= 1 << 1;
5511 if (!i.tm.opcode_modifier.no_lsuf)
5512 suffixes |= 1 << 2;
fc4adea1 5513 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5514 suffixes |= 1 << 3;
5515 if (!i.tm.opcode_modifier.no_ssuf)
5516 suffixes |= 1 << 4;
5517 if (!i.tm.opcode_modifier.no_qsuf)
5518 suffixes |= 1 << 5;
5519
5520 /* There are more than suffix matches. */
5521 if (i.tm.opcode_modifier.w
9306ca4a 5522 || ((suffixes & (suffixes - 1))
40fb9820
L		 5523 && !i.tm.opcode_modifier.defaultsize
5524 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5525 {
5526 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5527 return 0;
5528 }
5529 }
29b0f896 5530 }
252b5132 5531
9306ca4a
JB		 5532 /* Change the opcode based on the operand size given by i.suffix;
5533 We don't need to change things for byte insns. */
5534
582d5edd
L		 5535 if (i.suffix
5536 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5537 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5538 && i.suffix != YMMWORD_MNEM_SUFFIX
5539 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5540 {
5541 /* It's not a byte, select word/dword operation. */
40fb9820 5542 if (i.tm.opcode_modifier.w)
29b0f896 5543 {
40fb9820 5544 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5545 i.tm.base_opcode |= 8;
5546 else
5547 i.tm.base_opcode |= 1;
5548 }
0f3f3d8b 5549
29b0f896
AM		 5550 /* Now select between word & dword operations via the operand
5551 size prefix, except for instructions that will ignore this
5552 prefix anyway. */
ca61edf2 5553 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5554 {
ca61edf2
L		 5555 /* The address size override prefix changes the size of the
5556 first operand. */
40fb9820
L		 5557 if ((flag_code == CODE_32BIT
5558 && i.op->regs[0].reg_type.bitfield.reg16)
5559 || (flag_code != CODE_32BIT
5560 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5561 if (!add_prefix (ADDR_PREFIX_OPCODE))
5562 return 0;
5563 }
5564 else if (i.suffix != QWORD_MNEM_SUFFIX
5565 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5566 && !i.tm.opcode_modifier.ignoresize
5567 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5568 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5569 || (flag_code == CODE_64BIT
40fb9820 5570 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5571 {
5572 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5573
40fb9820 5574 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5575 prefix = ADDR_PREFIX_OPCODE;
252b5132 5576
29b0f896
AM		 5577 if (!add_prefix (prefix))
5578 return 0;
24eab124 5579 }
252b5132 5580
29b0f896
AM		 5581 /* Set mode64 for an operand. */
5582 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5583 && flag_code == CODE_64BIT
40fb9820 5584 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5585 {
5586 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5587 need rex64. cmpxchg8b is also a special case. */
5588 if (! (i.operands == 2
5589 && i.tm.base_opcode == 0x90
5590 && i.tm.extension_opcode == None
0dfbf9d7
L		 5591 && operand_type_equal (&i.types [0], &acc64)
5592 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5593 && ! (i.operands == 1
5594 && i.tm.base_opcode == 0xfc7
5595 && i.tm.extension_opcode == 1
40fb9820
L		 5596 && !operand_type_check (i.types [0], reg)
5597 && operand_type_check (i.types [0], anymem)))
f6bee062 5598 i.rex |= REX_W;
46e883c5 5599 }
3e73aa7c 5600
29b0f896
AM		 5601 /* Size floating point instruction. */
5602 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5603 if (i.tm.opcode_modifier.floatmf)
543613e9 5604 i.tm.base_opcode ^= 4;
29b0f896 5605 }
7ecd2f8b 5606
29b0f896
AM		 5607 return 1;
5608}
3e73aa7c 5609
29b0f896 5610static int
543613e9 5611check_byte_reg (void)
29b0f896
AM		 5612{
5613 int op;
543613e9 5614
29b0f896
AM		 5615 for (op = i.operands; --op >= 0;)
5616 {
5617 /* If this is an eight bit register, it's OK. If it's the 16 or
5618 32 bit version of an eight bit register, we will just use the
5619 low portion, and that's OK too. */
40fb9820 5620 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5621 continue;
5622
5a819eb9
JB		 5623 /* I/O port address operands are OK too. */
5624 if (i.tm.operand_types[op].bitfield.inoutportreg)
5625 continue;
5626
9344ff29
L		 5627 /* crc32 doesn't generate this warning. */
5628 if (i.tm.base_opcode == 0xf20f38f0)
5629 continue;
5630
40fb9820
L		 5631 if ((i.types[op].bitfield.reg16
5632 || i.types[op].bitfield.reg32
5633 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5634 && i.op[op].regs->reg_num < 4
5635 /* Prohibit these changes in 64bit mode, since the lowering
5636 would be more complicated. */
5637 && flag_code != CODE_64BIT)
29b0f896 5638 {
29b0f896 5639#if REGISTER_WARNINGS
5a819eb9 5640 if (!quiet_warnings)
a540244d
L		 5641 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5642 register_prefix,
40fb9820 5643 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5644 ? REGNAM_AL - REGNAM_AX
5645 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5646 register_prefix,
29b0f896
AM		 5647 i.op[op].regs->reg_name,
5648 i.suffix);
5649#endif
5650 continue;
5651 }
5652 /* Any other register is bad. */
40fb9820
L		 5653 if (i.types[op].bitfield.reg16
5654 || i.types[op].bitfield.reg32
5655 || i.types[op].bitfield.reg64
5656 || i.types[op].bitfield.regmmx
5657 || i.types[op].bitfield.regxmm
c0f3af97 5658 || i.types[op].bitfield.regymm
43234a1e 5659 || i.types[op].bitfield.regzmm
40fb9820
L		 5660 || i.types[op].bitfield.sreg2
5661 || i.types[op].bitfield.sreg3
5662 || i.types[op].bitfield.control
5663 || i.types[op].bitfield.debug
5664 || i.types[op].bitfield.test
5665 || i.types[op].bitfield.floatreg
5666 || i.types[op].bitfield.floatacc)
29b0f896 5667 {
a540244d
L		 5668 as_bad (_("`%s%s' not allowed with `%s%c'"),
5669 register_prefix,
29b0f896
AM		 5670 i.op[op].regs->reg_name,
5671 i.tm.name,
5672 i.suffix);
5673 return 0;
5674 }
5675 }
5676 return 1;
5677}
5678
5679static int
e3bb37b5 5680check_long_reg (void)
29b0f896
AM		 5681{
5682 int op;
5683
5684 for (op = i.operands; --op >= 0;)
5685 /* Reject eight bit registers, except where the template requires
5686 them. (eg. movzb) */
40fb9820
L		 5687 if (i.types[op].bitfield.reg8
5688 && (i.tm.operand_types[op].bitfield.reg16
5689 || i.tm.operand_types[op].bitfield.reg32
5690 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5691 {
a540244d
L		 5692 as_bad (_("`%s%s' not allowed with `%s%c'"),
5693 register_prefix,
29b0f896
AM		 5694 i.op[op].regs->reg_name,
5695 i.tm.name,
5696 i.suffix);
5697 return 0;
5698 }
e4630f71 5699 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5700 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5701 && i.types[op].bitfield.reg16
5702 && (i.tm.operand_types[op].bitfield.reg32
5703 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5704 {
5705 /* Prohibit these changes in the 64bit mode, since the
5706 lowering is more complicated. */
5707 if (flag_code == CODE_64BIT)
252b5132 5708 {
2b5d6a91 5709 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5710 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5711 i.suffix);
5712 return 0;
252b5132 5713 }
29b0f896 5714#if REGISTER_WARNINGS
cecf1424
JB		 5715 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5716 register_prefix,
5717 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5718 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5719#endif
252b5132 5720 }
e4630f71 5721 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5722 else if (i.types[op].bitfield.reg64
5723 && (i.tm.operand_types[op].bitfield.reg32
5724 || i.tm.operand_types[op].bitfield.acc))
252b5132 5725 {
34828aad 5726 if (intel_syntax
ca61edf2 5727 && i.tm.opcode_modifier.toqword
40fb9820 5728 && !i.types[0].bitfield.regxmm)
34828aad 5729 {
ca61edf2 5730 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5731 i.suffix = QWORD_MNEM_SUFFIX;
5732 }
5733 else
5734 {
2b5d6a91 5735 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5736 register_prefix, i.op[op].regs->reg_name,
5737 i.suffix);
5738 return 0;
5739 }
29b0f896
AM		 5740 }
5741 return 1;
5742}
252b5132 5743
29b0f896 5744static int
e3bb37b5 5745check_qword_reg (void)
29b0f896
AM		 5746{
5747 int op;
252b5132 5748
29b0f896
AM		 5749 for (op = i.operands; --op >= 0; )
5750 /* Reject eight bit registers, except where the template requires
5751 them. (eg. movzb) */
40fb9820
L		 5752 if (i.types[op].bitfield.reg8
5753 && (i.tm.operand_types[op].bitfield.reg16
5754 || i.tm.operand_types[op].bitfield.reg32
5755 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5756 {
a540244d
L		 5757 as_bad (_("`%s%s' not allowed with `%s%c'"),
5758 register_prefix,
29b0f896
AM		 5759 i.op[op].regs->reg_name,
5760 i.tm.name,
5761 i.suffix);
5762 return 0;
5763 }
e4630f71 5764 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5765 else if ((i.types[op].bitfield.reg16
5766 || i.types[op].bitfield.reg32)
33d0ab95 5767 && (i.tm.operand_types[op].bitfield.reg64
40fb9820 5768 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5769 {
5770 /* Prohibit these changes in the 64bit mode, since the
5771 lowering is more complicated. */
34828aad 5772 if (intel_syntax
ca61edf2 5773 && i.tm.opcode_modifier.todword
40fb9820 5774 && !i.types[0].bitfield.regxmm)
34828aad 5775 {
ca61edf2 5776 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5777 i.suffix = LONG_MNEM_SUFFIX;
5778 }
5779 else
5780 {
2b5d6a91 5781 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5782 register_prefix, i.op[op].regs->reg_name,
5783 i.suffix);
5784 return 0;
5785 }
252b5132 5786 }
29b0f896
AM		 5787 return 1;
5788}
252b5132 5789
29b0f896 5790static int
e3bb37b5 5791check_word_reg (void)
29b0f896
AM		 5792{
5793 int op;
5794 for (op = i.operands; --op >= 0;)
5795 /* Reject eight bit registers, except where the template requires
5796 them. (eg. movzb) */
40fb9820
L		 5797 if (i.types[op].bitfield.reg8
5798 && (i.tm.operand_types[op].bitfield.reg16
5799 || i.tm.operand_types[op].bitfield.reg32
5800 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5801 {
a540244d
L		 5802 as_bad (_("`%s%s' not allowed with `%s%c'"),
5803 register_prefix,
29b0f896
AM		 5804 i.op[op].regs->reg_name,
5805 i.tm.name,
5806 i.suffix);
5807 return 0;
5808 }
e4630f71 5809 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5810 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5811 && (i.types[op].bitfield.reg32
5812 || i.types[op].bitfield.reg64)
40fb9820
L		 5813 && (i.tm.operand_types[op].bitfield.reg16
5814 || i.tm.operand_types[op].bitfield.acc))
252b5132 5815 {
29b0f896
AM		 5816 /* Prohibit these changes in the 64bit mode, since the
5817 lowering is more complicated. */
5818 if (flag_code == CODE_64BIT)
252b5132 5819 {
2b5d6a91 5820 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5821 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5822 i.suffix);
5823 return 0;
252b5132 5824 }
29b0f896 5825#if REGISTER_WARNINGS
cecf1424
JB		 5826 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5827 register_prefix,
5828 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5829 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5830#endif
5831 }
5832 return 1;
5833}
252b5132 5834
29b0f896 5835static int
40fb9820 5836update_imm (unsigned int j)
29b0f896 5837{
bc0844ae 5838 i386_operand_type overlap = i.types[j];
40fb9820
L		 5839 if ((overlap.bitfield.imm8
5840 || overlap.bitfield.imm8s
5841 || overlap.bitfield.imm16
5842 || overlap.bitfield.imm32
5843 || overlap.bitfield.imm32s
5844 || overlap.bitfield.imm64)
0dfbf9d7
L		 5845 && !operand_type_equal (&overlap, &imm8)
5846 && !operand_type_equal (&overlap, &imm8s)
5847 && !operand_type_equal (&overlap, &imm16)
5848 && !operand_type_equal (&overlap, &imm32)
5849 && !operand_type_equal (&overlap, &imm32s)
5850 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5851 {
5852 if (i.suffix)
5853 {
40fb9820
L		 5854 i386_operand_type temp;
5855
0dfbf9d7 5856 operand_type_set (&temp, 0);
7ab9ffdd 5857 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5858 {
5859 temp.bitfield.imm8 = overlap.bitfield.imm8;
5860 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5861 }
5862 else if (i.suffix == WORD_MNEM_SUFFIX)
5863 temp.bitfield.imm16 = overlap.bitfield.imm16;
5864 else if (i.suffix == QWORD_MNEM_SUFFIX)
5865 {
5866 temp.bitfield.imm64 = overlap.bitfield.imm64;
5867 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5868 }
5869 else
5870 temp.bitfield.imm32 = overlap.bitfield.imm32;
5871 overlap = temp;
29b0f896 5872 }
0dfbf9d7
L		 5873 else if (operand_type_equal (&overlap, &imm16_32_32s)
5874 || operand_type_equal (&overlap, &imm16_32)
5875 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5876 {
40fb9820 5877 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5878 overlap = imm16;
40fb9820 5879 else
65da13b5 5880 overlap = imm32s;
29b0f896 5881 }
0dfbf9d7
L		 5882 if (!operand_type_equal (&overlap, &imm8)
5883 && !operand_type_equal (&overlap, &imm8s)
5884 && !operand_type_equal (&overlap, &imm16)
5885 && !operand_type_equal (&overlap, &imm32)
5886 && !operand_type_equal (&overlap, &imm32s)
5887 && !operand_type_equal (&overlap, &imm64))
29b0f896 5888 {
4eed87de
AM		 5889 as_bad (_("no instruction mnemonic suffix given; "
5890 "can't determine immediate size"));
29b0f896
AM		 5891 return 0;
5892 }
5893 }
40fb9820 5894 i.types[j] = overlap;
29b0f896 5895
40fb9820
L		 5896 return 1;
5897}
5898
5899static int
5900finalize_imm (void)
5901{
bc0844ae 5902 unsigned int j, n;
29b0f896 5903
bc0844ae
L		 5904 /* Update the first 2 immediate operands. */
5905 n = i.operands > 2 ? 2 : i.operands;
5906 if (n)
5907 {
5908 for (j = 0; j < n; j++)
5909 if (update_imm (j) == 0)
5910 return 0;
40fb9820 5911
bc0844ae
L		 5912 /* The 3rd operand can't be immediate operand. */
5913 gas_assert (operand_type_check (i.types[2], imm) == 0);
5914 }
29b0f896
AM		 5915
5916 return 1;
5917}
5918
c0f3af97
L		 5919static int
5920bad_implicit_operand (int xmm)
5921{
91d6fa6a
NC		 5922 const char *ireg = xmm ? "xmm0" : "ymm0";
5923
c0f3af97
L		 5924 if (intel_syntax)
5925 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5926 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5927 else
5928 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5929 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5930 return 0;
5931}
5932
29b0f896 5933static int
e3bb37b5 5934process_operands (void)
29b0f896
AM		 5935{
5936 /* Default segment register this instruction will use for memory
5937 accesses. 0 means unknown. This is only for optimizing out
5938 unnecessary segment overrides. */
5939 const seg_entry *default_seg = 0;
5940
2426c15f 5941 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5942 {
91d6fa6a
NC		 5943 unsigned int dupl = i.operands;
5944 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5945 unsigned int j;
5946
c0f3af97 5947 /* The destination must be an xmm register. */
9c2799c2 5948 gas_assert (i.reg_operands
91d6fa6a 5949 && MAX_OPERANDS > dupl
7ab9ffdd 5950 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5951
5952 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5953 {
c0f3af97 5954 /* The first operand is implicit and must be xmm0. */
9c2799c2 5955 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5956 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5957 return bad_implicit_operand (1);
5958
8cd7925b 5959 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5960 {
5961 /* Keep xmm0 for instructions with VEX prefix and 3
5962 sources. */
5963 goto duplicate;
5964 }
e2ec9d29 5965 else
c0f3af97
L		 5966 {
5967 /* We remove the first xmm0 and keep the number of
5968 operands unchanged, which in fact duplicates the
5969 destination. */
5970 for (j = 1; j < i.operands; j++)
5971 {
5972 i.op[j - 1] = i.op[j];
5973 i.types[j - 1] = i.types[j];
5974 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5975 }
5976 }
5977 }
5978 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5979 {
91d6fa6a 5980 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5981 && (i.tm.opcode_modifier.vexsources
5982 == VEX3SOURCES));
c0f3af97
L		 5983
5984 /* Add the implicit xmm0 for instructions with VEX prefix
5985 and 3 sources. */
5986 for (j = i.operands; j > 0; j--)
5987 {
5988 i.op[j] = i.op[j - 1];
5989 i.types[j] = i.types[j - 1];
5990 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5991 }
5992 i.op[0].regs
5993 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5994 i.types[0] = regxmm;
c0f3af97
L		 5995 i.tm.operand_types[0] = regxmm;
5996
5997 i.operands += 2;
5998 i.reg_operands += 2;
5999 i.tm.operands += 2;
6000
91d6fa6a 6001 dupl++;
c0f3af97 6002 dest++;
91d6fa6a
NC		 6003 i.op[dupl] = i.op[dest];
6004 i.types[dupl] = i.types[dest];
6005 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6006 }
c0f3af97
L		 6007 else
6008 {
6009duplicate:
6010 i.operands++;
6011 i.reg_operands++;
6012 i.tm.operands++;
6013
91d6fa6a
NC		 6014 i.op[dupl] = i.op[dest];
6015 i.types[dupl] = i.types[dest];
6016 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6017 }
6018
6019 if (i.tm.opcode_modifier.immext)
6020 process_immext ();
6021 }
6022 else if (i.tm.opcode_modifier.firstxmm0)
6023 {
6024 unsigned int j;
6025
43234a1e 6026 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 6027 gas_assert (i.reg_operands
7ab9ffdd 6028 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 6029 || operand_type_equal (&i.types[0], &regymm)
6030 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 6031 if (register_number (i.op[0].regs) != 0)
c0f3af97 6032 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 6033
6034 for (j = 1; j < i.operands; j++)
6035 {
6036 i.op[j - 1] = i.op[j];
6037 i.types[j - 1] = i.types[j];
6038
6039 /* We need to adjust fields in i.tm since they are used by
6040 build_modrm_byte. */
6041 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6042 }
6043
e2ec9d29
L		 6044 i.operands--;
6045 i.reg_operands--;
e2ec9d29
L		 6046 i.tm.operands--;
6047 }
920d2ddc
IT		 6048 else if (i.tm.opcode_modifier.implicitquadgroup)
6049 {
6050 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6051 gas_assert (i.operands >= 2
6052 && (operand_type_equal (&i.types[1], &regxmm)
6053 || operand_type_equal (&i.types[1], &regymm)
6054 || operand_type_equal (&i.types[1], &regzmm)));
6055 unsigned int regnum = register_number (i.op[1].regs);
6056 unsigned int first_reg_in_group = regnum & ~3;
6057 unsigned int last_reg_in_group = first_reg_in_group + 3;
6058 if (regnum != first_reg_in_group) {
6059 as_warn (_("the second source register `%s%s' implicitly denotes"
6060 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6061 register_prefix, i.op[1].regs->reg_name,
6062 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6063 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6064 i.tm.name);
6065 }
6066 }
e2ec9d29
L		 6067 else if (i.tm.opcode_modifier.regkludge)
6068 {
6069 /* The imul $imm, %reg instruction is converted into
6070 imul $imm, %reg, %reg, and the clr %reg instruction
6071 is converted into xor %reg, %reg. */
6072
6073 unsigned int first_reg_op;
6074
6075 if (operand_type_check (i.types[0], reg))
6076 first_reg_op = 0;
6077 else
6078 first_reg_op = 1;
6079 /* Pretend we saw the extra register operand. */
9c2799c2 6080 gas_assert (i.reg_operands == 1
7ab9ffdd 6081 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6082 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6083 i.types[first_reg_op + 1] = i.types[first_reg_op];
6084 i.operands++;
6085 i.reg_operands++;
29b0f896
AM		 6086 }
6087
40fb9820 6088 if (i.tm.opcode_modifier.shortform)
29b0f896 6089 {
40fb9820
L		 6090 if (i.types[0].bitfield.sreg2
6091 || i.types[0].bitfield.sreg3)
29b0f896 6092 {
4eed87de
AM		 6093 if (i.tm.base_opcode == POP_SEG_SHORT
6094 && i.op[0].regs->reg_num == 1)
29b0f896 6095 {
a87af027 6096 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6097 return 0;
29b0f896 6098 }
4eed87de
AM		 6099 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6100 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6101 i.rex |= REX_B;
4eed87de
AM		 6102 }
6103 else
6104 {
7ab9ffdd 6105 /* The register or float register operand is in operand
85f10a01 6106 0 or 1. */
40fb9820 6107 unsigned int op;
7ab9ffdd
L		 6108
6109 if (i.types[0].bitfield.floatreg
6110 || operand_type_check (i.types[0], reg))
6111 op = 0;
6112 else
6113 op = 1;
4eed87de
AM		 6114 /* Register goes in low 3 bits of opcode. */
6115 i.tm.base_opcode |= i.op[op].regs->reg_num;
6116 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6117 i.rex |= REX_B;
40fb9820 6118 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6119 {
4eed87de
AM		 6120 /* Warn about some common errors, but press on regardless.
6121 The first case can be generated by gcc (<= 2.8.1). */
6122 if (i.operands == 2)
6123 {
6124 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6125 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6126 register_prefix, i.op[!intel_syntax].regs->reg_name,
6127 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6128 }
6129 else
6130 {
6131 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6132 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6133 register_prefix, i.op[0].regs->reg_name);
4eed87de 6134 }
29b0f896
AM		 6135 }
6136 }
6137 }
40fb9820 6138 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6139 {
6140 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6141 must be put into the modrm byte). Now, we make the modrm and
6142 index base bytes based on all the info we've collected. */
29b0f896
AM		 6143
6144 default_seg = build_modrm_byte ();
6145 }
8a2ed489 6146 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6147 {
6148 default_seg = &ds;
6149 }
40fb9820 6150 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6151 {
6152 /* For the string instructions that allow a segment override
6153 on one of their operands, the default segment is ds. */
6154 default_seg = &ds;
6155 }
6156
75178d9d
L		 6157 if (i.tm.base_opcode == 0x8d /* lea */
6158 && i.seg[0]
6159 && !quiet_warnings)
30123838 6160 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6161
6162 /* If a segment was explicitly specified, and the specified segment
6163 is not the default, use an opcode prefix to select it. If we
6164 never figured out what the default segment is, then default_seg
6165 will be zero at this point, and the specified segment prefix will
6166 always be used. */
29b0f896
AM		 6167 if ((i.seg[0]) && (i.seg[0] != default_seg))
6168 {
6169 if (!add_prefix (i.seg[0]->seg_prefix))
6170 return 0;
6171 }
6172 return 1;
6173}
6174
6175static const seg_entry *
e3bb37b5 6176build_modrm_byte (void)
29b0f896
AM		 6177{
6178 const seg_entry *default_seg = 0;
c0f3af97 6179 unsigned int source, dest;
8cd7925b 6180 int vex_3_sources;
c0f3af97
L		 6181
6182 /* The first operand of instructions with VEX prefix and 3 sources
6183 must be VEX_Imm4. */
8cd7925b 6184 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6185 if (vex_3_sources)
6186 {
91d6fa6a 6187 unsigned int nds, reg_slot;
4c2c6516 6188 expressionS *exp;
c0f3af97 6189
922d8de8 6190 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6191 && i.tm.opcode_modifier.immext)
6192 {
6193 dest = i.operands - 2;
6194 gas_assert (dest == 3);
6195 }
922d8de8 6196 else
a683cc34 6197 dest = i.operands - 1;
c0f3af97 6198 nds = dest - 1;
922d8de8 6199
a683cc34
SP		 6200 /* There are 2 kinds of instructions:
6201 1. 5 operands: 4 register operands or 3 register operands
6202 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6203 VexW0 or VexW1. The destination must be either XMM, YMM or
6204 ZMM register.
a683cc34
SP		 6205 2. 4 operands: 4 register operands or 3 register operands
6206 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6207 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6208 || (i.reg_operands == 3 && i.mem_operands == 1))
6209 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6210 && (i.tm.opcode_modifier.veximmext
6211 || (i.imm_operands == 1
6212 && i.types[0].bitfield.vec_imm4
6213 && (i.tm.opcode_modifier.vexw == VEXW0
6214 || i.tm.opcode_modifier.vexw == VEXW1)
6215 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6216 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6217 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6218
6219 if (i.imm_operands == 0)
6220 {
6221 /* When there is no immediate operand, generate an 8bit
6222 immediate operand to encode the first operand. */
6223 exp = &im_expressions[i.imm_operands++];
6224 i.op[i.operands].imms = exp;
6225 i.types[i.operands] = imm8;
6226 i.operands++;
6227 /* If VexW1 is set, the first operand is the source and
6228 the second operand is encoded in the immediate operand. */
6229 if (i.tm.opcode_modifier.vexw == VEXW1)
6230 {
6231 source = 0;
6232 reg_slot = 1;
6233 }
6234 else
6235 {
6236 source = 1;
6237 reg_slot = 0;
6238 }
6239
6240 /* FMA swaps REG and NDS. */
6241 if (i.tm.cpu_flags.bitfield.cpufma)
6242 {
6243 unsigned int tmp;
6244 tmp = reg_slot;
6245 reg_slot = nds;
6246 nds = tmp;
6247 }
6248
24981e7b
L		 6249 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6250 &regxmm)
a683cc34 6251 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6252 &regymm)
6253 || operand_type_equal (&i.tm.operand_types[reg_slot],
6254 &regzmm));
a683cc34 6255 exp->X_op = O_constant;
4c692bc7 6256 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6257 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6258 }
922d8de8 6259 else
a683cc34
SP		 6260 {
6261 unsigned int imm_slot;
6262
6263 if (i.tm.opcode_modifier.vexw == VEXW0)
6264 {
6265 /* If VexW0 is set, the third operand is the source and
6266 the second operand is encoded in the immediate
6267 operand. */
6268 source = 2;
6269 reg_slot = 1;
6270 }
6271 else
6272 {
6273 /* VexW1 is set, the second operand is the source and
6274 the third operand is encoded in the immediate
6275 operand. */
6276 source = 1;
6277 reg_slot = 2;
6278 }
6279
6280 if (i.tm.opcode_modifier.immext)
6281 {
33eaf5de 6282 /* When ImmExt is set, the immediate byte is the last
a683cc34
SP		 6283 operand. */
6284 imm_slot = i.operands - 1;
6285 source--;
6286 reg_slot--;
6287 }
6288 else
6289 {
6290 imm_slot = 0;
6291
6292 /* Turn on Imm8 so that output_imm will generate it. */
6293 i.types[imm_slot].bitfield.imm8 = 1;
6294 }
6295
24981e7b
L		 6296 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6297 &regxmm)
6298 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6299 &regymm)
6300 || operand_type_equal (&i.tm.operand_types[reg_slot],
6301 &regzmm));
a683cc34 6302 i.op[imm_slot].imms->X_add_number
4c692bc7 6303 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6304 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6305 }
6306
6307 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6308 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6309 &regymm)
6310 || operand_type_equal (&i.tm.operand_types[nds],
6311 &regzmm));
dae39acc 6312 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6313 }
6314 else
6315 source = dest = 0;
29b0f896
AM		 6316
6317 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6318 implicit registers do not count. If there are 3 register
6319 operands, it must be a instruction with VexNDS. For a
6320 instruction with VexNDD, the destination register is encoded
6321 in VEX prefix. If there are 4 register operands, it must be
6322 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6323 if (i.mem_operands == 0
6324 && ((i.reg_operands == 2
2426c15f 6325 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6326 || (i.reg_operands == 3
2426c15f 6327 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6328 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6329 {
cab737b9
L		 6330 switch (i.operands)
6331 {
6332 case 2:
6333 source = 0;
6334 break;
6335 case 3:
c81128dc
L		 6336 /* When there are 3 operands, one of them may be immediate,
6337 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6338 the first operand must be shift count register (cl) or it
6339 is an instruction with VexNDS. */
9c2799c2 6340 gas_assert (i.imm_operands == 1
7ab9ffdd 6341 || (i.imm_operands == 0
2426c15f 6342 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6343 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6344 if (operand_type_check (i.types[0], imm)
6345 || i.types[0].bitfield.shiftcount)
6346 source = 1;
6347 else
6348 source = 0;
cab737b9
L		 6349 break;
6350 case 4:
368d64cc
L		 6351 /* When there are 4 operands, the first two must be 8bit
6352 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6353 one.
6354
6355 For instructions with VexNDS, if the first operand
6356 an imm8, the source operand is the 2nd one. If the last
6357 operand is imm8, the source operand is the first one. */
9c2799c2 6358 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6359 && i.types[0].bitfield.imm8
6360 && i.types[1].bitfield.imm8)
2426c15f 6361 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6362 && i.imm_operands == 1
6363 && (i.types[0].bitfield.imm8
43234a1e
L		 6364 || i.types[i.operands - 1].bitfield.imm8
6365 || i.rounding)));
9f2670f2
L		 6366 if (i.imm_operands == 2)
6367 source = 2;
6368 else
c0f3af97
L		 6369 {
6370 if (i.types[0].bitfield.imm8)
6371 source = 1;
6372 else
6373 source = 0;
6374 }
c0f3af97
L		 6375 break;
6376 case 5:
43234a1e
L		 6377 if (i.tm.opcode_modifier.evex)
6378 {
6379 /* For EVEX instructions, when there are 5 operands, the
6380 first one must be immediate operand. If the second one
6381 is immediate operand, the source operand is the 3th
6382 one. If the last one is immediate operand, the source
6383 operand is the 2nd one. */
6384 gas_assert (i.imm_operands == 2
6385 && i.tm.opcode_modifier.sae
6386 && operand_type_check (i.types[0], imm));
6387 if (operand_type_check (i.types[1], imm))
6388 source = 2;
6389 else if (operand_type_check (i.types[4], imm))
6390 source = 1;
6391 else
6392 abort ();
6393 }
cab737b9
L		 6394 break;
6395 default:
6396 abort ();
6397 }
6398
c0f3af97
L		 6399 if (!vex_3_sources)
6400 {
6401 dest = source + 1;
6402
43234a1e
L		 6403 /* RC/SAE operand could be between DEST and SRC. That happens
6404 when one operand is GPR and the other one is XMM/YMM/ZMM
6405 register. */
6406 if (i.rounding && i.rounding->operand == (int) dest)
6407 dest++;
6408
2426c15f 6409 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6410 {
43234a1e
L		 6411 /* For instructions with VexNDS, the register-only source
6412 operand must be 32/64bit integer, XMM, YMM or ZMM
6413 register. It is encoded in VEX prefix. We need to
6414 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6415
6416 i386_operand_type op;
6417 unsigned int vvvv;
6418
6419 /* Check register-only source operand when two source
6420 operands are swapped. */
6421 if (!i.tm.operand_types[source].bitfield.baseindex
6422 && i.tm.operand_types[dest].bitfield.baseindex)
6423 {
6424 vvvv = source;
6425 source = dest;
6426 }
6427 else
6428 vvvv = dest;
6429
6430 op = i.tm.operand_types[vvvv];
fa99fab2 6431 op.bitfield.regmem = 0;
c0f3af97 6432 if ((dest + 1) >= i.operands
ac4eb736
AM		 6433 || (!op.bitfield.reg32
6434 && op.bitfield.reg64
f12dc422 6435 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6436 && !operand_type_equal (&op, &regymm)
6437 && !operand_type_equal (&op, &regzmm)
6438 && !operand_type_equal (&op, &regmask)))
c0f3af97 6439 abort ();
f12dc422 6440 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6441 dest++;
6442 }
6443 }
29b0f896
AM		 6444
6445 i.rm.mode = 3;
6446 /* One of the register operands will be encoded in the i.tm.reg
6447 field, the other in the combined i.tm.mode and i.tm.regmem
6448 fields. If no form of this instruction supports a memory
6449 destination operand, then we assume the source operand may
6450 sometimes be a memory operand and so we need to store the
6451 destination in the i.rm.reg field. */
40fb9820
L		 6452 if (!i.tm.operand_types[dest].bitfield.regmem
6453 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6454 {
6455 i.rm.reg = i.op[dest].regs->reg_num;
6456 i.rm.regmem = i.op[source].regs->reg_num;
6457 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6458 i.rex |= REX_R;
43234a1e
L		 6459 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6460 i.vrex |= REX_R;
29b0f896 6461 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6462 i.rex |= REX_B;
43234a1e
L		 6463 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6464 i.vrex |= REX_B;
29b0f896
AM		 6465 }
6466 else
6467 {
6468 i.rm.reg = i.op[source].regs->reg_num;
6469 i.rm.regmem = i.op[dest].regs->reg_num;
6470 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6471 i.rex |= REX_B;
43234a1e
L		 6472 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6473 i.vrex |= REX_B;
29b0f896 6474 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6475 i.rex |= REX_R;
43234a1e
L		 6476 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6477 i.vrex |= REX_R;
29b0f896 6478 }
161a04f6 6479 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6480 {
40fb9820
L		 6481 if (!i.types[0].bitfield.control
6482 && !i.types[1].bitfield.control)
c4a530c5 6483 abort ();
161a04f6 6484 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6485 add_prefix (LOCK_PREFIX_OPCODE);
6486 }
29b0f896
AM		 6487 }
6488 else
6489 { /* If it's not 2 reg operands... */
c0f3af97
L		 6490 unsigned int mem;
6491
29b0f896
AM		 6492 if (i.mem_operands)
6493 {
6494 unsigned int fake_zero_displacement = 0;
99018f42 6495 unsigned int op;
4eed87de 6496
7ab9ffdd
L		 6497 for (op = 0; op < i.operands; op++)
6498 if (operand_type_check (i.types[op], anymem))
6499 break;
7ab9ffdd 6500 gas_assert (op < i.operands);
29b0f896 6501
6c30d220
L		 6502 if (i.tm.opcode_modifier.vecsib)
6503 {
6504 if (i.index_reg->reg_num == RegEiz
6505 || i.index_reg->reg_num == RegRiz)
6506 abort ();
6507
6508 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6509 if (!i.base_reg)
6510 {
6511 i.sib.base = NO_BASE_REGISTER;
6512 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6513 /* No Vec_Disp8 if there is no base. */
6514 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6515 i.types[op].bitfield.disp8 = 0;
6516 i.types[op].bitfield.disp16 = 0;
6517 i.types[op].bitfield.disp64 = 0;
6518 if (flag_code != CODE_64BIT)
6519 {
6520 /* Must be 32 bit */
6521 i.types[op].bitfield.disp32 = 1;
6522 i.types[op].bitfield.disp32s = 0;
6523 }
6524 else
6525 {
6526 i.types[op].bitfield.disp32 = 0;
6527 i.types[op].bitfield.disp32s = 1;
6528 }
6529 }
6530 i.sib.index = i.index_reg->reg_num;
6531 if ((i.index_reg->reg_flags & RegRex) != 0)
6532 i.rex |= REX_X;
43234a1e
L		 6533 if ((i.index_reg->reg_flags & RegVRex) != 0)
6534 i.vrex |= REX_X;
6c30d220
L		 6535 }
6536
29b0f896
AM		 6537 default_seg = &ds;
6538
6539 if (i.base_reg == 0)
6540 {
6541 i.rm.mode = 0;
6542 if (!i.disp_operands)
6c30d220
L		 6543 {
6544 fake_zero_displacement = 1;
6545 /* Instructions with VSIB byte need 32bit displacement
6546 if there is no base register. */
6547 if (i.tm.opcode_modifier.vecsib)
6548 i.types[op].bitfield.disp32 = 1;
6549 }
29b0f896
AM		 6550 if (i.index_reg == 0)
6551 {
6c30d220 6552 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6553 /* Operand is just <disp> */
20f0a1fc 6554 if (flag_code == CODE_64BIT)
29b0f896
AM		 6555 {
6556 /* 64bit mode overwrites the 32bit absolute
6557 addressing by RIP relative addressing and
6558 absolute addressing is encoded by one of the
6559 redundant SIB forms. */
6560 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6561 i.sib.base = NO_BASE_REGISTER;
6562 i.sib.index = NO_INDEX_REGISTER;
fc225355 6563 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6564 ? disp32s : disp32);
20f0a1fc 6565 }
fc225355
L		 6566 else if ((flag_code == CODE_16BIT)
6567 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6568 {
6569 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6570 i.types[op] = disp16;
20f0a1fc
NC		 6571 }
6572 else
6573 {
6574 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6575 i.types[op] = disp32;
29b0f896
AM		 6576 }
6577 }
6c30d220 6578 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6579 {
6c30d220 6580 /* !i.base_reg && i.index_reg */
db51cc60
L		 6581 if (i.index_reg->reg_num == RegEiz
6582 || i.index_reg->reg_num == RegRiz)
6583 i.sib.index = NO_INDEX_REGISTER;
6584 else
6585 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6586 i.sib.base = NO_BASE_REGISTER;
6587 i.sib.scale = i.log2_scale_factor;
6588 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6589 /* No Vec_Disp8 if there is no base. */
6590 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6591 i.types[op].bitfield.disp8 = 0;
6592 i.types[op].bitfield.disp16 = 0;
6593 i.types[op].bitfield.disp64 = 0;
29b0f896 6594 if (flag_code != CODE_64BIT)
40fb9820
L		 6595 {
6596 /* Must be 32 bit */
6597 i.types[op].bitfield.disp32 = 1;
6598 i.types[op].bitfield.disp32s = 0;
6599 }
29b0f896 6600 else
40fb9820
L		 6601 {
6602 i.types[op].bitfield.disp32 = 0;
6603 i.types[op].bitfield.disp32s = 1;
6604 }
29b0f896 6605 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6606 i.rex |= REX_X;
29b0f896
AM		 6607 }
6608 }
6609 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6610 else if (i.base_reg->reg_num == RegRip ||
6611 i.base_reg->reg_num == RegEip)
29b0f896 6612 {
6c30d220 6613 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6614 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6615 i.types[op].bitfield.disp8 = 0;
6616 i.types[op].bitfield.disp16 = 0;
6617 i.types[op].bitfield.disp32 = 0;
6618 i.types[op].bitfield.disp32s = 1;
6619 i.types[op].bitfield.disp64 = 0;
43234a1e 6620 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6621 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6622 if (! i.disp_operands)
6623 fake_zero_displacement = 1;
29b0f896 6624 }
40fb9820 6625 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6626 {
6c30d220 6627 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6628 switch (i.base_reg->reg_num)
6629 {
6630 case 3: /* (%bx) */
6631 if (i.index_reg == 0)
6632 i.rm.regmem = 7;
6633 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6634 i.rm.regmem = i.index_reg->reg_num - 6;
6635 break;
6636 case 5: /* (%bp) */
6637 default_seg = &ss;
6638 if (i.index_reg == 0)
6639 {
6640 i.rm.regmem = 6;
40fb9820 6641 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6642 {
6643 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6644 if (i.tm.operand_types[op].bitfield.vec_disp8)
6645 i.types[op].bitfield.vec_disp8 = 1;
6646 else
6647 i.types[op].bitfield.disp8 = 1;
252b5132 6648 fake_zero_displacement = 1;
29b0f896
AM		 6649 }
6650 }
6651 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6652 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6653 break;
6654 default: /* (%si) -> 4 or (%di) -> 5 */
6655 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6656 }
6657 i.rm.mode = mode_from_disp_size (i.types[op]);
6658 }
6659 else /* i.base_reg and 32/64 bit mode */
6660 {
6661 if (flag_code == CODE_64BIT
40fb9820
L		 6662 && operand_type_check (i.types[op], disp))
6663 {
6664 i386_operand_type temp;
0dfbf9d7 6665 operand_type_set (&temp, 0);
40fb9820 6666 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6667 temp.bitfield.vec_disp8
6668 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6669 i.types[op] = temp;
6670 if (i.prefix[ADDR_PREFIX] == 0)
6671 i.types[op].bitfield.disp32s = 1;
6672 else
6673 i.types[op].bitfield.disp32 = 1;
6674 }
20f0a1fc 6675
6c30d220
L		 6676 if (!i.tm.opcode_modifier.vecsib)
6677 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6678 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6679 i.rex |= REX_B;
29b0f896
AM		 6680 i.sib.base = i.base_reg->reg_num;
6681 /* x86-64 ignores REX prefix bit here to avoid decoder
6682 complications. */
848930b2
JB		 6683 if (!(i.base_reg->reg_flags & RegRex)
6684 && (i.base_reg->reg_num == EBP_REG_NUM
6685 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6686 default_seg = &ss;
848930b2 6687 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6688 {
848930b2 6689 fake_zero_displacement = 1;
43234a1e
L		 6690 if (i.tm.operand_types [op].bitfield.vec_disp8)
6691 i.types[op].bitfield.vec_disp8 = 1;
6692 else
6693 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6694 }
6695 i.sib.scale = i.log2_scale_factor;
6696 if (i.index_reg == 0)
6697 {
6c30d220 6698 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6699 /* <disp>(%esp) becomes two byte modrm with no index
6700 register. We've already stored the code for esp
6701 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6702 Any base register besides %esp will not use the
6703 extra modrm byte. */
6704 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6705 }
6c30d220 6706 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6707 {
db51cc60
L		 6708 if (i.index_reg->reg_num == RegEiz
6709 || i.index_reg->reg_num == RegRiz)
6710 i.sib.index = NO_INDEX_REGISTER;
6711 else
6712 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6713 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6714 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6715 i.rex |= REX_X;
29b0f896 6716 }
67a4f2b7
AO		 6717
6718 if (i.disp_operands
6719 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6720 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6721 i.rm.mode = 0;
6722 else
a501d77e
L		 6723 {
6724 if (!fake_zero_displacement
6725 && !i.disp_operands
6726 && i.disp_encoding)
6727 {
6728 fake_zero_displacement = 1;
6729 if (i.disp_encoding == disp_encoding_8bit)
6730 i.types[op].bitfield.disp8 = 1;
6731 else
6732 i.types[op].bitfield.disp32 = 1;
6733 }
6734 i.rm.mode = mode_from_disp_size (i.types[op]);
6735 }
29b0f896 6736 }
252b5132 6737
29b0f896
AM		 6738 if (fake_zero_displacement)
6739 {
6740 /* Fakes a zero displacement assuming that i.types[op]
6741 holds the correct displacement size. */
6742 expressionS *exp;
6743
9c2799c2 6744 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6745 exp = &disp_expressions[i.disp_operands++];
6746 i.op[op].disps = exp;
6747 exp->X_op = O_constant;
6748 exp->X_add_number = 0;
6749 exp->X_add_symbol = (symbolS *) 0;
6750 exp->X_op_symbol = (symbolS *) 0;
6751 }
c0f3af97
L		 6752
6753 mem = op;
29b0f896 6754 }
c0f3af97
L		 6755 else
6756 mem = ~0;
252b5132 6757
8c43a48b 6758 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6759 {
6760 if (operand_type_check (i.types[0], imm))
6761 i.vex.register_specifier = NULL;
6762 else
6763 {
6764 /* VEX.vvvv encodes one of the sources when the first
6765 operand is not an immediate. */
1ef99a7b 6766 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6767 i.vex.register_specifier = i.op[0].regs;
6768 else
6769 i.vex.register_specifier = i.op[1].regs;
6770 }
6771
6772 /* Destination is a XMM register encoded in the ModRM.reg
6773 and VEX.R bit. */
6774 i.rm.reg = i.op[2].regs->reg_num;
6775 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6776 i.rex |= REX_R;
6777
6778 /* ModRM.rm and VEX.B encodes the other source. */
6779 if (!i.mem_operands)
6780 {
6781 i.rm.mode = 3;
6782
1ef99a7b 6783 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6784 i.rm.regmem = i.op[1].regs->reg_num;
6785 else
6786 i.rm.regmem = i.op[0].regs->reg_num;
6787
6788 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6789 i.rex |= REX_B;
6790 }
6791 }
2426c15f 6792 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6793 {
6794 i.vex.register_specifier = i.op[2].regs;
6795 if (!i.mem_operands)
6796 {
6797 i.rm.mode = 3;
6798 i.rm.regmem = i.op[1].regs->reg_num;
6799 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6800 i.rex |= REX_B;
6801 }
6802 }
29b0f896
AM		 6803 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6804 (if any) based on i.tm.extension_opcode. Again, we must be
6805 careful to make sure that segment/control/debug/test/MMX
6806 registers are coded into the i.rm.reg field. */
f88c9eb0 6807 else if (i.reg_operands)
29b0f896 6808 {
99018f42 6809 unsigned int op;
7ab9ffdd
L		 6810 unsigned int vex_reg = ~0;
6811
6812 for (op = 0; op < i.operands; op++)
6813 if (i.types[op].bitfield.reg8
6814 || i.types[op].bitfield.reg16
6815 || i.types[op].bitfield.reg32
6816 || i.types[op].bitfield.reg64
6817 || i.types[op].bitfield.regmmx
6818 || i.types[op].bitfield.regxmm
6819 || i.types[op].bitfield.regymm
7e8b059b 6820 || i.types[op].bitfield.regbnd
43234a1e
L		 6821 || i.types[op].bitfield.regzmm
6822 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6823 || i.types[op].bitfield.sreg2
6824 || i.types[op].bitfield.sreg3
6825 || i.types[op].bitfield.control
6826 || i.types[op].bitfield.debug
6827 || i.types[op].bitfield.test)
6828 break;
c0209578 6829
7ab9ffdd
L		 6830 if (vex_3_sources)
6831 op = dest;
2426c15f 6832 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6833 {
6834 /* For instructions with VexNDS, the register-only
6835 source operand is encoded in VEX prefix. */
6836 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6837
7ab9ffdd 6838 if (op > mem)
c0f3af97 6839 {
7ab9ffdd
L		 6840 vex_reg = op++;
6841 gas_assert (op < i.operands);
c0f3af97
L		 6842 }
6843 else
c0f3af97 6844 {
f12dc422
L		 6845 /* Check register-only source operand when two source
6846 operands are swapped. */
6847 if (!i.tm.operand_types[op].bitfield.baseindex
6848 && i.tm.operand_types[op + 1].bitfield.baseindex)
6849 {
6850 vex_reg = op;
6851 op += 2;
6852 gas_assert (mem == (vex_reg + 1)
6853 && op < i.operands);
6854 }
6855 else
6856 {
6857 vex_reg = op + 1;
6858 gas_assert (vex_reg < i.operands);
6859 }
c0f3af97 6860 }
7ab9ffdd 6861 }
2426c15f 6862 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6863 {
f12dc422 6864 /* For instructions with VexNDD, the register destination
7ab9ffdd 6865 is encoded in VEX prefix. */
f12dc422
L		 6866 if (i.mem_operands == 0)
6867 {
6868 /* There is no memory operand. */
6869 gas_assert ((op + 2) == i.operands);
6870 vex_reg = op + 1;
6871 }
6872 else
8d63c93e 6873 {
f12dc422
L		 6874 /* There are only 2 operands. */
6875 gas_assert (op < 2 && i.operands == 2);
6876 vex_reg = 1;
6877 }
7ab9ffdd
L		 6878 }
6879 else
6880 gas_assert (op < i.operands);
99018f42 6881
7ab9ffdd
L		 6882 if (vex_reg != (unsigned int) ~0)
6883 {
f12dc422 6884 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6885
f12dc422
L		 6886 if (type->bitfield.reg32 != 1
6887 && type->bitfield.reg64 != 1
6888 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6889 && !operand_type_equal (type, &regymm)
6890 && !operand_type_equal (type, &regzmm)
6891 && !operand_type_equal (type, &regmask))
7ab9ffdd 6892 abort ();
f88c9eb0 6893
7ab9ffdd
L		 6894 i.vex.register_specifier = i.op[vex_reg].regs;
6895 }
6896
1b9f0c97
L		 6897 /* Don't set OP operand twice. */
6898 if (vex_reg != op)
7ab9ffdd 6899 {
1b9f0c97
L		 6900 /* If there is an extension opcode to put here, the
6901 register number must be put into the regmem field. */
6902 if (i.tm.extension_opcode != None)
6903 {
6904 i.rm.regmem = i.op[op].regs->reg_num;
6905 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6906 i.rex |= REX_B;
43234a1e
L		 6907 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6908 i.vrex |= REX_B;
1b9f0c97
L		 6909 }
6910 else
6911 {
6912 i.rm.reg = i.op[op].regs->reg_num;
6913 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6914 i.rex |= REX_R;
43234a1e
L		 6915 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6916 i.vrex |= REX_R;
1b9f0c97 6917 }
7ab9ffdd 6918 }
252b5132 6919
29b0f896
AM		 6920 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6921 must set it to 3 to indicate this is a register operand
6922 in the regmem field. */
6923 if (!i.mem_operands)
6924 i.rm.mode = 3;
6925 }
252b5132 6926
29b0f896 6927 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6928 if (i.tm.extension_opcode != None)
29b0f896
AM		 6929 i.rm.reg = i.tm.extension_opcode;
6930 }
6931 return default_seg;
6932}
252b5132 6933
29b0f896 6934static void
e3bb37b5 6935output_branch (void)
29b0f896
AM		 6936{
6937 char *p;
f8a5c266 6938 int size;
29b0f896
AM		 6939 int code16;
6940 int prefix;
6941 relax_substateT subtype;
6942 symbolS *sym;
6943 offsetT off;
6944
f8a5c266 6945 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6946 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6947
6948 prefix = 0;
6949 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6950 {
29b0f896
AM		 6951 prefix = 1;
6952 i.prefixes -= 1;
6953 code16 ^= CODE16;
252b5132 6954 }
29b0f896
AM		 6955 /* Pentium4 branch hints. */
6956 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6957 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6958 {
29b0f896
AM		 6959 prefix++;
6960 i.prefixes--;
6961 }
6962 if (i.prefix[REX_PREFIX] != 0)
6963 {
6964 prefix++;
6965 i.prefixes--;
2f66722d
AM		 6966 }
6967
7e8b059b
L		 6968 /* BND prefixed jump. */
6969 if (i.prefix[BND_PREFIX] != 0)
6970 {
6971 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6972 i.prefixes -= 1;
6973 }
6974
29b0f896
AM		 6975 if (i.prefixes != 0 && !intel_syntax)
6976 as_warn (_("skipping prefixes on this instruction"));
6977
6978 /* It's always a symbol; End frag & setup for relax.
6979 Make sure there is enough room in this frag for the largest
6980 instruction we may generate in md_convert_frag. This is 2
6981 bytes for the opcode and room for the prefix and largest
6982 displacement. */
6983 frag_grow (prefix + 2 + 4);
6984 /* Prefix and 1 opcode byte go in fr_fix. */
6985 p = frag_more (prefix + 1);
6986 if (i.prefix[DATA_PREFIX] != 0)
6987 *p++ = DATA_PREFIX_OPCODE;
6988 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6989 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6990 *p++ = i.prefix[SEG_PREFIX];
6991 if (i.prefix[REX_PREFIX] != 0)
6992 *p++ = i.prefix[REX_PREFIX];
6993 *p = i.tm.base_opcode;
6994
6995 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6996 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6997 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6998 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6999 else
f8a5c266 7000 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7001 subtype |= code16;
3e73aa7c 7002
29b0f896
AM		 7003 sym = i.op[0].disps->X_add_symbol;
7004 off = i.op[0].disps->X_add_number;
3e73aa7c 7005
29b0f896
AM		 7006 if (i.op[0].disps->X_op != O_constant
7007 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7008 {
29b0f896
AM		 7009 /* Handle complex expressions. */
7010 sym = make_expr_symbol (i.op[0].disps);
7011 off = 0;
7012 }
3e73aa7c 7013
29b0f896
AM		 7014 /* 1 possible extra opcode + 4 byte displacement go in var part.
7015 Pass reloc in fr_var. */
d258b828 7016 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7017}
3e73aa7c 7018
29b0f896 7019static void
e3bb37b5 7020output_jump (void)
29b0f896
AM		 7021{
7022 char *p;
7023 int size;
3e02c1cc 7024 fixS *fixP;
29b0f896 7025
40fb9820 7026 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7027 {
7028 /* This is a loop or jecxz type instruction. */
7029 size = 1;
7030 if (i.prefix[ADDR_PREFIX] != 0)
7031 {
7032 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7033 i.prefixes -= 1;
7034 }
7035 /* Pentium4 branch hints. */
7036 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7037 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7038 {
7039 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7040 i.prefixes--;
3e73aa7c
JH		 7041 }
7042 }
29b0f896
AM		 7043 else
7044 {
7045 int code16;
3e73aa7c 7046
29b0f896
AM		 7047 code16 = 0;
7048 if (flag_code == CODE_16BIT)
7049 code16 = CODE16;
3e73aa7c 7050
29b0f896
AM		 7051 if (i.prefix[DATA_PREFIX] != 0)
7052 {
7053 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7054 i.prefixes -= 1;
7055 code16 ^= CODE16;
7056 }
252b5132 7057
29b0f896
AM		 7058 size = 4;
7059 if (code16)
7060 size = 2;
7061 }
9fcc94b6 7062
29b0f896
AM		 7063 if (i.prefix[REX_PREFIX] != 0)
7064 {
7065 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7066 i.prefixes -= 1;
7067 }
252b5132 7068
7e8b059b
L		 7069 /* BND prefixed jump. */
7070 if (i.prefix[BND_PREFIX] != 0)
7071 {
7072 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7073 i.prefixes -= 1;
7074 }
7075
29b0f896
AM		 7076 if (i.prefixes != 0 && !intel_syntax)
7077 as_warn (_("skipping prefixes on this instruction"));
e0890092 7078
42164a71
L		 7079 p = frag_more (i.tm.opcode_length + size);
7080 switch (i.tm.opcode_length)
7081 {
7082 case 2:
7083 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7084 /* Fall through. */
42164a71
L		 7085 case 1:
7086 *p++ = i.tm.base_opcode;
7087 break;
7088 default:
7089 abort ();
7090 }
e0890092 7091
3e02c1cc 7092 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7093 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 7094
7095 /* All jumps handled here are signed, but don't use a signed limit
7096 check for 32 and 16 bit jumps as we want to allow wrap around at
7097 4G and 64k respectively. */
7098 if (size == 1)
7099 fixP->fx_signed = 1;
29b0f896 7100}
e0890092 7101
29b0f896 7102static void
e3bb37b5 7103output_interseg_jump (void)
29b0f896
AM		 7104{
7105 char *p;
7106 int size;
7107 int prefix;
7108 int code16;
252b5132 7109
29b0f896
AM		 7110 code16 = 0;
7111 if (flag_code == CODE_16BIT)
7112 code16 = CODE16;
a217f122 7113
29b0f896
AM		 7114 prefix = 0;
7115 if (i.prefix[DATA_PREFIX] != 0)
7116 {
7117 prefix = 1;
7118 i.prefixes -= 1;
7119 code16 ^= CODE16;
7120 }
7121 if (i.prefix[REX_PREFIX] != 0)
7122 {
7123 prefix++;
7124 i.prefixes -= 1;
7125 }
252b5132 7126
29b0f896
AM		 7127 size = 4;
7128 if (code16)
7129 size = 2;
252b5132 7130
29b0f896
AM		 7131 if (i.prefixes != 0 && !intel_syntax)
7132 as_warn (_("skipping prefixes on this instruction"));
252b5132 7133
29b0f896
AM		 7134 /* 1 opcode; 2 segment; offset */
7135 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7136
29b0f896
AM		 7137 if (i.prefix[DATA_PREFIX] != 0)
7138 *p++ = DATA_PREFIX_OPCODE;
252b5132 7139
29b0f896
AM		 7140 if (i.prefix[REX_PREFIX] != 0)
7141 *p++ = i.prefix[REX_PREFIX];
252b5132 7142
29b0f896
AM		 7143 *p++ = i.tm.base_opcode;
7144 if (i.op[1].imms->X_op == O_constant)
7145 {
7146 offsetT n = i.op[1].imms->X_add_number;
252b5132 7147
29b0f896
AM		 7148 if (size == 2
7149 && !fits_in_unsigned_word (n)
7150 && !fits_in_signed_word (n))
7151 {
7152 as_bad (_("16-bit jump out of range"));
7153 return;
7154 }
7155 md_number_to_chars (p, n, size);
7156 }
7157 else
7158 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7159 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7160 if (i.op[0].imms->X_op != O_constant)
7161 as_bad (_("can't handle non absolute segment in `%s'"),
7162 i.tm.name);
7163 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7164}
a217f122 7165
29b0f896 7166static void
e3bb37b5 7167output_insn (void)
29b0f896 7168{
2bbd9c25
JJ		 7169 fragS *insn_start_frag;
7170 offsetT insn_start_off;
7171
29b0f896
AM		 7172 /* Tie dwarf2 debug info to the address at the start of the insn.
7173 We can't do this after the insn has been output as the current
7174 frag may have been closed off. eg. by frag_var. */
7175 dwarf2_emit_insn (0);
7176
2bbd9c25
JJ		 7177 insn_start_frag = frag_now;
7178 insn_start_off = frag_now_fix ();
7179
29b0f896 7180 /* Output jumps. */
40fb9820 7181 if (i.tm.opcode_modifier.jump)
29b0f896 7182 output_branch ();
40fb9820
L		 7183 else if (i.tm.opcode_modifier.jumpbyte
7184 || i.tm.opcode_modifier.jumpdword)
29b0f896 7185 output_jump ();
40fb9820 7186 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7187 output_interseg_jump ();
7188 else
7189 {
7190 /* Output normal instructions here. */
7191 char *p;
7192 unsigned char *q;
47465058 7193 unsigned int j;
331d2d0d 7194 unsigned int prefix;
4dffcebc 7195
e4e00185
AS		 7196 if (avoid_fence
7197 && i.tm.base_opcode == 0xfae
7198 && i.operands == 1
7199 && i.imm_operands == 1
7200 && (i.op[0].imms->X_add_number == 0xe8
7201 || i.op[0].imms->X_add_number == 0xf0
7202 || i.op[0].imms->X_add_number == 0xf8))
7203 {
7204 /* Encode lfence, mfence, and sfence as
7205 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7206 offsetT val = 0x240483f0ULL;
7207 p = frag_more (5);
7208 md_number_to_chars (p, val, 5);
7209 return;
7210 }
7211
d022bddd
IT		 7212 /* Some processors fail on LOCK prefix. This options makes
7213 assembler ignore LOCK prefix and serves as a workaround. */
7214 if (omit_lock_prefix)
7215 {
7216 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7217 return;
7218 i.prefix[LOCK_PREFIX] = 0;
7219 }
7220
43234a1e
L		 7221 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7222 don't need the explicit prefix. */
7223 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7224 {
c0f3af97 7225 switch (i.tm.opcode_length)
bc4bd9ab 7226 {
c0f3af97
L		 7227 case 3:
7228 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7229 {
c0f3af97
L		 7230 prefix = (i.tm.base_opcode >> 24) & 0xff;
7231 goto check_prefix;
7232 }
7233 break;
7234 case 2:
7235 if ((i.tm.base_opcode & 0xff0000) != 0)
7236 {
7237 prefix = (i.tm.base_opcode >> 16) & 0xff;
7238 if (i.tm.cpu_flags.bitfield.cpupadlock)
7239 {
4dffcebc 7240check_prefix:
c0f3af97 7241 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7242 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7243 != REPE_PREFIX_OPCODE))
7244 add_prefix (prefix);
7245 }
7246 else
4dffcebc
L		 7247 add_prefix (prefix);
7248 }
c0f3af97
L		 7249 break;
7250 case 1:
7251 break;
7252 default:
7253 abort ();
bc4bd9ab 7254 }
c0f3af97 7255
6d19a37a 7256#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7257 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7258 R_X86_64_GOTTPOFF relocation so that linker can safely
7259 perform IE->LE optimization. */
7260 if (x86_elf_abi == X86_64_X32_ABI
7261 && i.operands == 2
7262 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7263 && i.prefix[REX_PREFIX] == 0)
7264 add_prefix (REX_OPCODE);
6d19a37a 7265#endif
cf61b747 7266
c0f3af97
L		 7267 /* The prefix bytes. */
7268 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7269 if (*q)
7270 FRAG_APPEND_1_CHAR (*q);
0f10071e 7271 }
ae5c1c7b 7272 else
c0f3af97
L		 7273 {
7274 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7275 if (*q)
7276 switch (j)
7277 {
7278 case REX_PREFIX:
7279 /* REX byte is encoded in VEX prefix. */
7280 break;
7281 case SEG_PREFIX:
7282 case ADDR_PREFIX:
7283 FRAG_APPEND_1_CHAR (*q);
7284 break;
7285 default:
7286 /* There should be no other prefixes for instructions
7287 with VEX prefix. */
7288 abort ();
7289 }
7290
43234a1e
L		 7291 /* For EVEX instructions i.vrex should become 0 after
7292 build_evex_prefix. For VEX instructions upper 16 registers
7293 aren't available, so VREX should be 0. */
7294 if (i.vrex)
7295 abort ();
c0f3af97
L		 7296 /* Now the VEX prefix. */
7297 p = frag_more (i.vex.length);
7298 for (j = 0; j < i.vex.length; j++)
7299 p[j] = i.vex.bytes[j];
7300 }
252b5132 7301
29b0f896 7302 /* Now the opcode; be careful about word order here! */
4dffcebc 7303 if (i.tm.opcode_length == 1)
29b0f896
AM		 7304 {
7305 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7306 }
7307 else
7308 {
4dffcebc 7309 switch (i.tm.opcode_length)
331d2d0d 7310 {
43234a1e
L		 7311 case 4:
7312 p = frag_more (4);
7313 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7314 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7315 break;
4dffcebc 7316 case 3:
331d2d0d
L		 7317 p = frag_more (3);
7318 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7319 break;
7320 case 2:
7321 p = frag_more (2);
7322 break;
7323 default:
7324 abort ();
7325 break;
331d2d0d 7326 }
0f10071e 7327
29b0f896
AM		 7328 /* Put out high byte first: can't use md_number_to_chars! */
7329 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7330 *p = i.tm.base_opcode & 0xff;
7331 }
3e73aa7c 7332
29b0f896 7333 /* Now the modrm byte and sib byte (if present). */
40fb9820 7334 if (i.tm.opcode_modifier.modrm)
29b0f896 7335 {
4a3523fa
L		 7336 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7337 | i.rm.reg << 3
7338 | i.rm.mode << 6));
29b0f896
AM		 7339 /* If i.rm.regmem == ESP (4)
7340 && i.rm.mode != (Register mode)
7341 && not 16 bit
7342 ==> need second modrm byte. */
7343 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7344 && i.rm.mode != 3
40fb9820 7345 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7346 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7347 | i.sib.index << 3
7348 | i.sib.scale << 6));
29b0f896 7349 }
3e73aa7c 7350
29b0f896 7351 if (i.disp_operands)
2bbd9c25 7352 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7353
29b0f896 7354 if (i.imm_operands)
2bbd9c25 7355 output_imm (insn_start_frag, insn_start_off);
29b0f896 7356 }
252b5132 7357
29b0f896
AM		 7358#ifdef DEBUG386
7359 if (flag_debug)
7360 {
7b81dfbb 7361 pi ("" /*line*/, &i);
29b0f896
AM		 7362 }
7363#endif /* DEBUG386 */
7364}
252b5132 7365
e205caa7
L		 7366/* Return the size of the displacement operand N. */
7367
7368static int
7369disp_size (unsigned int n)
7370{
7371 int size = 4;
43234a1e
L		 7372
7373 /* Vec_Disp8 has to be 8bit. */
7374 if (i.types[n].bitfield.vec_disp8)
7375 size = 1;
7376 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7377 size = 8;
7378 else if (i.types[n].bitfield.disp8)
7379 size = 1;
7380 else if (i.types[n].bitfield.disp16)
7381 size = 2;
e205caa7
L		 7382 return size;
7383}
7384
7385/* Return the size of the immediate operand N. */
7386
7387static int
7388imm_size (unsigned int n)
7389{
7390 int size = 4;
40fb9820
L		 7391 if (i.types[n].bitfield.imm64)
7392 size = 8;
7393 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7394 size = 1;
7395 else if (i.types[n].bitfield.imm16)
7396 size = 2;
e205caa7
L		 7397 return size;
7398}
7399
29b0f896 7400static void
64e74474 7401output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7402{
7403 char *p;
7404 unsigned int n;
252b5132 7405
29b0f896
AM		 7406 for (n = 0; n < i.operands; n++)
7407 {
43234a1e
L		 7408 if (i.types[n].bitfield.vec_disp8
7409 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7410 {
7411 if (i.op[n].disps->X_op == O_constant)
7412 {
e205caa7 7413 int size = disp_size (n);
43234a1e 7414 offsetT val = i.op[n].disps->X_add_number;
252b5132 7415
43234a1e
L		 7416 if (i.types[n].bitfield.vec_disp8)
7417 val >>= i.memshift;
7418 val = offset_in_range (val, size);
29b0f896
AM		 7419 p = frag_more (size);
7420 md_number_to_chars (p, val, size);
7421 }
7422 else
7423 {
f86103b7 7424 enum bfd_reloc_code_real reloc_type;
e205caa7 7425 int size = disp_size (n);
40fb9820 7426 int sign = i.types[n].bitfield.disp32s;
29b0f896 7427 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7428 fixS *fixP;
29b0f896 7429
e205caa7 7430 /* We can't have 8 bit displacement here. */
9c2799c2 7431 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7432
29b0f896
AM		 7433 /* The PC relative address is computed relative
7434 to the instruction boundary, so in case immediate
7435 fields follows, we need to adjust the value. */
7436 if (pcrel && i.imm_operands)
7437 {
29b0f896 7438 unsigned int n1;
e205caa7 7439 int sz = 0;
252b5132 7440
29b0f896 7441 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7442 if (operand_type_check (i.types[n1], imm))
252b5132 7443 {
e205caa7
L		 7444 /* Only one immediate is allowed for PC
7445 relative address. */
9c2799c2 7446 gas_assert (sz == 0);
e205caa7
L		 7447 sz = imm_size (n1);
7448 i.op[n].disps->X_add_number -= sz;
252b5132 7449 }
29b0f896 7450 /* We should find the immediate. */
9c2799c2 7451 gas_assert (sz != 0);
29b0f896 7452 }
520dc8e8 7453
29b0f896 7454 p = frag_more (size);
d258b828 7455 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7456 if (GOT_symbol
2bbd9c25 7457 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7458 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7459 || reloc_type == BFD_RELOC_X86_64_32S
7460 || (reloc_type == BFD_RELOC_64
7461 && object_64bit))
d6ab8113
JB		 7462 && (i.op[n].disps->X_op == O_symbol
7463 || (i.op[n].disps->X_op == O_add
7464 && ((symbol_get_value_expression
7465 (i.op[n].disps->X_op_symbol)->X_op)
7466 == O_subtract))))
7467 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7468 {
7469 offsetT add;
7470
7471 if (insn_start_frag == frag_now)
7472 add = (p - frag_now->fr_literal) - insn_start_off;
7473 else
7474 {
7475 fragS *fr;
7476
7477 add = insn_start_frag->fr_fix - insn_start_off;
7478 for (fr = insn_start_frag->fr_next;
7479 fr && fr != frag_now; fr = fr->fr_next)
7480 add += fr->fr_fix;
7481 add += p - frag_now->fr_literal;
7482 }
7483
4fa24527 7484 if (!object_64bit)
7b81dfbb
AJ		 7485 {
7486 reloc_type = BFD_RELOC_386_GOTPC;
7487 i.op[n].imms->X_add_number += add;
7488 }
7489 else if (reloc_type == BFD_RELOC_64)
7490 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7491 else
7b81dfbb
AJ		 7492 /* Don't do the adjustment for x86-64, as there
7493 the pcrel addressing is relative to the _next_
7494 insn, and that is taken care of in other code. */
d6ab8113 7495 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7496 }
02a86693
L		 7497 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7498 size, i.op[n].disps, pcrel,
7499 reloc_type);
7500 /* Check for "call/jmp *mem", "mov mem, %reg",
7501 "test %reg, mem" and "binop mem, %reg" where binop
7502 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7503 instructions. Always generate R_386_GOT32X for
7504 "sym*GOT" operand in 32-bit mode. */
7505 if ((generate_relax_relocations
7506 || (!object_64bit
7507 && i.rm.mode == 0
7508 && i.rm.regmem == 5))
7509 && (i.rm.mode == 2
7510 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7511 && ((i.operands == 1
7512 && i.tm.base_opcode == 0xff
7513 && (i.rm.reg == 2 || i.rm.reg == 4))
7514 || (i.operands == 2
7515 && (i.tm.base_opcode == 0x8b
7516 || i.tm.base_opcode == 0x85
7517 || (i.tm.base_opcode & 0xc7) == 0x03))))
7518 {
7519 if (object_64bit)
7520 {
7521 fixP->fx_tcbit = i.rex != 0;
7522 if (i.base_reg
7523 && (i.base_reg->reg_num == RegRip
7524 || i.base_reg->reg_num == RegEip))
7525 fixP->fx_tcbit2 = 1;
7526 }
7527 else
7528 fixP->fx_tcbit2 = 1;
7529 }
29b0f896
AM		 7530 }
7531 }
7532 }
7533}
252b5132 7534
29b0f896 7535static void
64e74474 7536output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7537{
7538 char *p;
7539 unsigned int n;
252b5132 7540
29b0f896
AM		 7541 for (n = 0; n < i.operands; n++)
7542 {
43234a1e
L		 7543 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7544 if (i.rounding && (int) n == i.rounding->operand)
7545 continue;
7546
40fb9820 7547 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7548 {
7549 if (i.op[n].imms->X_op == O_constant)
7550 {
e205caa7 7551 int size = imm_size (n);
29b0f896 7552 offsetT val;
b4cac588 7553
29b0f896
AM		 7554 val = offset_in_range (i.op[n].imms->X_add_number,
7555 size);
7556 p = frag_more (size);
7557 md_number_to_chars (p, val, size);
7558 }
7559 else
7560 {
7561 /* Not absolute_section.
7562 Need a 32-bit fixup (don't support 8bit
7563 non-absolute imms). Try to support other
7564 sizes ... */
f86103b7 7565 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7566 int size = imm_size (n);
7567 int sign;
29b0f896 7568
40fb9820 7569 if (i.types[n].bitfield.imm32s
a7d61044 7570 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7571 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7572 sign = 1;
e205caa7
L		 7573 else
7574 sign = 0;
520dc8e8 7575
29b0f896 7576 p = frag_more (size);
d258b828 7577 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7578
2bbd9c25
JJ		 7579 /* This is tough to explain. We end up with this one if we
7580 * have operands that look like
7581 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7582 * obtain the absolute address of the GOT, and it is strongly
7583 * preferable from a performance point of view to avoid using
7584 * a runtime relocation for this. The actual sequence of
7585 * instructions often look something like:
7586 *
7587 * call .L66
7588 * .L66:
7589 * popl %ebx
7590 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7591 *
7592 * The call and pop essentially return the absolute address
7593 * of the label .L66 and store it in %ebx. The linker itself
7594 * will ultimately change the first operand of the addl so
7595 * that %ebx points to the GOT, but to keep things simple, the
7596 * .o file must have this operand set so that it generates not
7597 * the absolute address of .L66, but the absolute address of
7598 * itself. This allows the linker itself simply treat a GOTPC
7599 * relocation as asking for a pcrel offset to the GOT to be
7600 * added in, and the addend of the relocation is stored in the
7601 * operand field for the instruction itself.
7602 *
7603 * Our job here is to fix the operand so that it would add
7604 * the correct offset so that %ebx would point to itself. The
7605 * thing that is tricky is that .-.L66 will point to the
7606 * beginning of the instruction, so we need to further modify
7607 * the operand so that it will point to itself. There are
7608 * other cases where you have something like:
7609 *
7610 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7611 *
7612 * and here no correction would be required. Internally in
7613 * the assembler we treat operands of this form as not being
7614 * pcrel since the '.' is explicitly mentioned, and I wonder
7615 * whether it would simplify matters to do it this way. Who
7616 * knows. In earlier versions of the PIC patches, the
7617 * pcrel_adjust field was used to store the correction, but
7618 * since the expression is not pcrel, I felt it would be
7619 * confusing to do it this way. */
7620
d6ab8113 7621 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7622 || reloc_type == BFD_RELOC_X86_64_32S
7623 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7624 && GOT_symbol
7625 && GOT_symbol == i.op[n].imms->X_add_symbol
7626 && (i.op[n].imms->X_op == O_symbol
7627 || (i.op[n].imms->X_op == O_add
7628 && ((symbol_get_value_expression
7629 (i.op[n].imms->X_op_symbol)->X_op)
7630 == O_subtract))))
7631 {
2bbd9c25
JJ		 7632 offsetT add;
7633
7634 if (insn_start_frag == frag_now)
7635 add = (p - frag_now->fr_literal) - insn_start_off;
7636 else
7637 {
7638 fragS *fr;
7639
7640 add = insn_start_frag->fr_fix - insn_start_off;
7641 for (fr = insn_start_frag->fr_next;
7642 fr && fr != frag_now; fr = fr->fr_next)
7643 add += fr->fr_fix;
7644 add += p - frag_now->fr_literal;
7645 }
7646
4fa24527 7647 if (!object_64bit)
d6ab8113 7648 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7649 else if (size == 4)
d6ab8113 7650 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7651 else if (size == 8)
7652 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7653 i.op[n].imms->X_add_number += add;
29b0f896 7654 }
29b0f896
AM		 7655 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7656 i.op[n].imms, 0, reloc_type);
7657 }
7658 }
7659 }
252b5132
RH		 7660}
7661\f
d182319b
JB		 7662/* x86_cons_fix_new is called via the expression parsing code when a
7663 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7664static int cons_sign = -1;
7665
7666void
e3bb37b5 7667x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7668 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7669{
d258b828 7670 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7671
7672#ifdef TE_PE
7673 if (exp->X_op == O_secrel)
7674 {
7675 exp->X_op = O_symbol;
7676 r = BFD_RELOC_32_SECREL;
7677 }
7678#endif
7679
7680 fix_new_exp (frag, off, len, exp, 0, r);
7681}
7682
357d1bd8
L		 7683/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7684 purpose of the `.dc.a' internal pseudo-op. */
7685
7686int
7687x86_address_bytes (void)
7688{
7689 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7690 return 4;
7691 return stdoutput->arch_info->bits_per_address / 8;
7692}
7693
d382c579
TG		 7694#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7695 || defined (LEX_AT)
d258b828 7696# define lex_got(reloc, adjust, types) NULL
718ddfc0 7697#else
f3c180ae
AM		 7698/* Parse operands of the form
7699 <symbol>@GOTOFF+<nnn>
7700 and similar .plt or .got references.
7701
7702 If we find one, set up the correct relocation in RELOC and copy the
7703 input string, minus the `@GOTOFF' into a malloc'd buffer for
7704 parsing by the calling routine. Return this buffer, and if ADJUST
7705 is non-null set it to the length of the string we removed from the
7706 input line. Otherwise return NULL. */
7707static char *
91d6fa6a 7708lex_got (enum bfd_reloc_code_real *rel,
64e74474 7709 int *adjust,
d258b828 7710 i386_operand_type *types)
f3c180ae 7711{
7b81dfbb
AJ		 7712 /* Some of the relocations depend on the size of what field is to
7713 be relocated. But in our callers i386_immediate and i386_displacement
7714 we don't yet know the operand size (this will be set by insn
7715 matching). Hence we record the word32 relocation here,
7716 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7717 static const struct {
7718 const char *str;
cff8d58a 7719 int len;
4fa24527 7720 const enum bfd_reloc_code_real rel[2];
40fb9820 7721 const i386_operand_type types64;
f3c180ae 7722 } gotrel[] = {
8ce3d284 7723#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7724 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7725 BFD_RELOC_SIZE32 },
7726 OPERAND_TYPE_IMM32_64 },
8ce3d284 7727#endif
cff8d58a
L		 7728 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7729 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7730 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7731 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7732 BFD_RELOC_X86_64_PLT32 },
40fb9820 7733 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7734 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7735 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7736 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7737 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7738 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7739 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7740 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7741 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7742 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7743 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7744 BFD_RELOC_X86_64_TLSGD },
40fb9820 7745 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7746 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7747 _dummy_first_bfd_reloc_code_real },
40fb9820 7748 OPERAND_TYPE_NONE },
cff8d58a
L		 7749 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7750 BFD_RELOC_X86_64_TLSLD },
40fb9820 7751 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7752 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7753 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7754 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7755 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7756 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7757 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7758 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7759 _dummy_first_bfd_reloc_code_real },
40fb9820 7760 OPERAND_TYPE_NONE },
cff8d58a
L		 7761 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7762 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7763 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7764 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7765 _dummy_first_bfd_reloc_code_real },
40fb9820 7766 OPERAND_TYPE_NONE },
cff8d58a
L		 7767 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7768 _dummy_first_bfd_reloc_code_real },
40fb9820 7769 OPERAND_TYPE_NONE },
cff8d58a
L		 7770 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7771 BFD_RELOC_X86_64_GOT32 },
40fb9820 7772 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7773 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7774 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7775 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7776 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7777 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7778 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7779 };
7780 char *cp;
7781 unsigned int j;
7782
d382c579 7783#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7784 if (!IS_ELF)
7785 return NULL;
d382c579 7786#endif
718ddfc0 7787
f3c180ae 7788 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7789 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7790 return NULL;
7791
47465058 7792 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7793 {
cff8d58a 7794 int len = gotrel[j].len;
28f81592 7795 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7796 {
4fa24527 7797 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7798 {
28f81592
AM		 7799 int first, second;
7800 char *tmpbuf, *past_reloc;
f3c180ae 7801
91d6fa6a 7802 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7803
3956db08
JB		 7804 if (types)
7805 {
7806 if (flag_code != CODE_64BIT)
40fb9820
L		 7807 {
7808 types->bitfield.imm32 = 1;
7809 types->bitfield.disp32 = 1;
7810 }
3956db08
JB		 7811 else
7812 *types = gotrel[j].types64;
7813 }
7814
8fd4256d 7815 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7816 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7817
28f81592 7818 /* The length of the first part of our input line. */
f3c180ae 7819 first = cp - input_line_pointer;
28f81592
AM		 7820
7821 /* The second part goes from after the reloc token until
67c11a9b 7822 (and including) an end_of_line char or comma. */
28f81592 7823 past_reloc = cp + 1 + len;
67c11a9b
AM		 7824 cp = past_reloc;
7825 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7826 ++cp;
7827 second = cp + 1 - past_reloc;
28f81592
AM		 7828
7829 /* Allocate and copy string. The trailing NUL shouldn't
7830 be necessary, but be safe. */
add39d23 7831 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7832 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7833 if (second != 0 && *past_reloc != ' ')
7834 /* Replace the relocation token with ' ', so that
7835 errors like foo@GOTOFF1 will be detected. */
7836 tmpbuf[first++] = ' ';
af89796a
L		 7837 else
7838 /* Increment length by 1 if the relocation token is
7839 removed. */
7840 len++;
7841 if (adjust)
7842 *adjust = len;
0787a12d
AM		 7843 memcpy (tmpbuf + first, past_reloc, second);
7844 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7845 return tmpbuf;
7846 }
7847
4fa24527
JB		 7848 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7849 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7850 return NULL;
7851 }
7852 }
7853
7854 /* Might be a symbol version string. Don't as_bad here. */
7855 return NULL;
7856}
4e4f7c87 7857#endif
f3c180ae 7858
a988325c
NC		 7859#ifdef TE_PE
7860#ifdef lex_got
7861#undef lex_got
7862#endif
7863/* Parse operands of the form
7864 <symbol>@SECREL32+<nnn>
7865
7866 If we find one, set up the correct relocation in RELOC and copy the
7867 input string, minus the `@SECREL32' into a malloc'd buffer for
7868 parsing by the calling routine. Return this buffer, and if ADJUST
7869 is non-null set it to the length of the string we removed from the
34bca508
L		 7870 input line. Otherwise return NULL.
7871
a988325c
NC		 7872 This function is copied from the ELF version above adjusted for PE targets. */
7873
7874static char *
7875lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7876 int *adjust ATTRIBUTE_UNUSED,
d258b828 7877 i386_operand_type *types)
a988325c
NC		 7878{
7879 static const struct
7880 {
7881 const char *str;
7882 int len;
7883 const enum bfd_reloc_code_real rel[2];
7884 const i386_operand_type types64;
7885 }
7886 gotrel[] =
7887 {
7888 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7889 BFD_RELOC_32_SECREL },
7890 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7891 };
7892
7893 char *cp;
7894 unsigned j;
7895
7896 for (cp = input_line_pointer; *cp != '@'; cp++)
7897 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7898 return NULL;
7899
7900 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7901 {
7902 int len = gotrel[j].len;
7903
7904 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7905 {
7906 if (gotrel[j].rel[object_64bit] != 0)
7907 {
7908 int first, second;
7909 char *tmpbuf, *past_reloc;
7910
7911 *rel = gotrel[j].rel[object_64bit];
7912 if (adjust)
7913 *adjust = len;
7914
7915 if (types)
7916 {
7917 if (flag_code != CODE_64BIT)
7918 {
7919 types->bitfield.imm32 = 1;
7920 types->bitfield.disp32 = 1;
7921 }
7922 else
7923 *types = gotrel[j].types64;
7924 }
7925
7926 /* The length of the first part of our input line. */
7927 first = cp - input_line_pointer;
7928
7929 /* The second part goes from after the reloc token until
7930 (and including) an end_of_line char or comma. */
7931 past_reloc = cp + 1 + len;
7932 cp = past_reloc;
7933 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7934 ++cp;
7935 second = cp + 1 - past_reloc;
7936
7937 /* Allocate and copy string. The trailing NUL shouldn't
7938 be necessary, but be safe. */
add39d23 7939 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7940 memcpy (tmpbuf, input_line_pointer, first);
7941 if (second != 0 && *past_reloc != ' ')
7942 /* Replace the relocation token with ' ', so that
7943 errors like foo@SECLREL321 will be detected. */
7944 tmpbuf[first++] = ' ';
7945 memcpy (tmpbuf + first, past_reloc, second);
7946 tmpbuf[first + second] = '\0';
7947 return tmpbuf;
7948 }
7949
7950 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7951 gotrel[j].str, 1 << (5 + object_64bit));
7952 return NULL;
7953 }
7954 }
7955
7956 /* Might be a symbol version string. Don't as_bad here. */
7957 return NULL;
7958}
7959
7960#endif /* TE_PE */
7961
62ebcb5c 7962bfd_reloc_code_real_type
e3bb37b5 7963x86_cons (expressionS *exp, int size)
f3c180ae 7964{
62ebcb5c
AM		 7965 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7966
ee86248c
JB		 7967 intel_syntax = -intel_syntax;
7968
3c7b9c2c 7969 exp->X_md = 0;
4fa24527 7970 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7971 {
7972 /* Handle @GOTOFF and the like in an expression. */
7973 char *save;
7974 char *gotfree_input_line;
4a57f2cf 7975 int adjust = 0;
f3c180ae
AM		 7976
7977 save = input_line_pointer;
d258b828 7978 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7979 if (gotfree_input_line)
7980 input_line_pointer = gotfree_input_line;
7981
7982 expression (exp);
7983
7984 if (gotfree_input_line)
7985 {
7986 /* expression () has merrily parsed up to the end of line,
7987 or a comma - in the wrong buffer. Transfer how far
7988 input_line_pointer has moved to the right buffer. */
7989 input_line_pointer = (save
7990 + (input_line_pointer - gotfree_input_line)
7991 + adjust);
7992 free (gotfree_input_line);
3992d3b7
AM		 7993 if (exp->X_op == O_constant
7994 || exp->X_op == O_absent
7995 || exp->X_op == O_illegal
0398aac5 7996 || exp->X_op == O_register
3992d3b7
AM		 7997 || exp->X_op == O_big)
7998 {
7999 char c = *input_line_pointer;
8000 *input_line_pointer = 0;
8001 as_bad (_("missing or invalid expression `%s'"), save);
8002 *input_line_pointer = c;
8003 }
f3c180ae
AM		 8004 }
8005 }
8006 else
8007 expression (exp);
ee86248c
JB		 8008
8009 intel_syntax = -intel_syntax;
8010
8011 if (intel_syntax)
8012 i386_intel_simplify (exp);
62ebcb5c
AM		 8013
8014 return got_reloc;
f3c180ae 8015}
f3c180ae 8016
9f32dd5b
L		 8017static void
8018signed_cons (int size)
6482c264 8019{
d182319b
JB		 8020 if (flag_code == CODE_64BIT)
8021 cons_sign = 1;
8022 cons (size);
8023 cons_sign = -1;
6482c264
NC		 8024}
8025
d182319b 8026#ifdef TE_PE
6482c264 8027static void
7016a5d5 8028pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8029{
8030 expressionS exp;
8031
8032 do
8033 {
8034 expression (&exp);
8035 if (exp.X_op == O_symbol)
8036 exp.X_op = O_secrel;
8037
8038 emit_expr (&exp, 4);
8039 }
8040 while (*input_line_pointer++ == ',');
8041
8042 input_line_pointer--;
8043 demand_empty_rest_of_line ();
8044}
6482c264
NC		 8045#endif
8046
43234a1e
L		 8047/* Handle Vector operations. */
8048
8049static char *
8050check_VecOperations (char *op_string, char *op_end)
8051{
8052 const reg_entry *mask;
8053 const char *saved;
8054 char *end_op;
8055
8056 while (*op_string
8057 && (op_end == NULL || op_string < op_end))
8058 {
8059 saved = op_string;
8060 if (*op_string == '{')
8061 {
8062 op_string++;
8063
8064 /* Check broadcasts. */
8065 if (strncmp (op_string, "1to", 3) == 0)
8066 {
8067 int bcst_type;
8068
8069 if (i.broadcast)
8070 goto duplicated_vec_op;
8071
8072 op_string += 3;
8073 if (*op_string == '8')
8074 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 8075 else if (*op_string == '4')
8076 bcst_type = BROADCAST_1TO4;
8077 else if (*op_string == '2')
8078 bcst_type = BROADCAST_1TO2;
43234a1e
L		 8079 else if (*op_string == '1'
8080 && *(op_string+1) == '6')
8081 {
8082 bcst_type = BROADCAST_1TO16;
8083 op_string++;
8084 }
8085 else
8086 {
8087 as_bad (_("Unsupported broadcast: `%s'"), saved);
8088 return NULL;
8089 }
8090 op_string++;
8091
8092 broadcast_op.type = bcst_type;
8093 broadcast_op.operand = this_operand;
8094 i.broadcast = &broadcast_op;
8095 }
8096 /* Check masking operation. */
8097 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8098 {
8099 /* k0 can't be used for write mask. */
8100 if (mask->reg_num == 0)
8101 {
8102 as_bad (_("`%s' can't be used for write mask"),
8103 op_string);
8104 return NULL;
8105 }
8106
8107 if (!i.mask)
8108 {
8109 mask_op.mask = mask;
8110 mask_op.zeroing = 0;
8111 mask_op.operand = this_operand;
8112 i.mask = &mask_op;
8113 }
8114 else
8115 {
8116 if (i.mask->mask)
8117 goto duplicated_vec_op;
8118
8119 i.mask->mask = mask;
8120
8121 /* Only "{z}" is allowed here. No need to check
8122 zeroing mask explicitly. */
8123 if (i.mask->operand != this_operand)
8124 {
8125 as_bad (_("invalid write mask `%s'"), saved);
8126 return NULL;
8127 }
8128 }
8129
8130 op_string = end_op;
8131 }
8132 /* Check zeroing-flag for masking operation. */
8133 else if (*op_string == 'z')
8134 {
8135 if (!i.mask)
8136 {
8137 mask_op.mask = NULL;
8138 mask_op.zeroing = 1;
8139 mask_op.operand = this_operand;
8140 i.mask = &mask_op;
8141 }
8142 else
8143 {
8144 if (i.mask->zeroing)
8145 {
8146 duplicated_vec_op:
8147 as_bad (_("duplicated `%s'"), saved);
8148 return NULL;
8149 }
8150
8151 i.mask->zeroing = 1;
8152
8153 /* Only "{%k}" is allowed here. No need to check mask
8154 register explicitly. */
8155 if (i.mask->operand != this_operand)
8156 {
8157 as_bad (_("invalid zeroing-masking `%s'"),
8158 saved);
8159 return NULL;
8160 }
8161 }
8162
8163 op_string++;
8164 }
8165 else
8166 goto unknown_vec_op;
8167
8168 if (*op_string != '}')
8169 {
8170 as_bad (_("missing `}' in `%s'"), saved);
8171 return NULL;
8172 }
8173 op_string++;
8174 continue;
8175 }
8176 unknown_vec_op:
8177 /* We don't know this one. */
8178 as_bad (_("unknown vector operation: `%s'"), saved);
8179 return NULL;
8180 }
8181
8182 return op_string;
8183}
8184
252b5132 8185static int
70e41ade 8186i386_immediate (char *imm_start)
252b5132
RH		 8187{
8188 char *save_input_line_pointer;
f3c180ae 8189 char *gotfree_input_line;
252b5132 8190 segT exp_seg = 0;
47926f60 8191 expressionS *exp;
40fb9820
L		 8192 i386_operand_type types;
8193
0dfbf9d7 8194 operand_type_set (&types, ~0);
252b5132
RH		 8195
8196 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8197 {
31b2323c
L		 8198 as_bad (_("at most %d immediate operands are allowed"),
8199 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8200 return 0;
8201 }
8202
8203 exp = &im_expressions[i.imm_operands++];
520dc8e8 8204 i.op[this_operand].imms = exp;
252b5132
RH		 8205
8206 if (is_space_char (*imm_start))
8207 ++imm_start;
8208
8209 save_input_line_pointer = input_line_pointer;
8210 input_line_pointer = imm_start;
8211
d258b828 8212 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8213 if (gotfree_input_line)
8214 input_line_pointer = gotfree_input_line;
252b5132
RH		 8215
8216 exp_seg = expression (exp);
8217
83183c0c 8218 SKIP_WHITESPACE ();
43234a1e
L		 8219
8220 /* Handle vector operations. */
8221 if (*input_line_pointer == '{')
8222 {
8223 input_line_pointer = check_VecOperations (input_line_pointer,
8224 NULL);
8225 if (input_line_pointer == NULL)
8226 return 0;
8227 }
8228
252b5132 8229 if (*input_line_pointer)
f3c180ae 8230 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8231
8232 input_line_pointer = save_input_line_pointer;
f3c180ae 8233 if (gotfree_input_line)
ee86248c
JB		 8234 {
8235 free (gotfree_input_line);
8236
8237 if (exp->X_op == O_constant || exp->X_op == O_register)
8238 exp->X_op = O_illegal;
8239 }
8240
8241 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8242}
252b5132 8243
ee86248c
JB		 8244static int
8245i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8246 i386_operand_type types, const char *imm_start)
8247{
8248 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8249 {
313c53d1
L		 8250 if (imm_start)
8251 as_bad (_("missing or invalid immediate expression `%s'"),
8252 imm_start);
3992d3b7 8253 return 0;
252b5132 8254 }
3e73aa7c 8255 else if (exp->X_op == O_constant)
252b5132 8256 {
47926f60 8257 /* Size it properly later. */
40fb9820 8258 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8259 /* If not 64bit, sign extend val. */
8260 if (flag_code != CODE_64BIT
4eed87de
AM		 8261 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8262 exp->X_add_number
8263 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8264 }
4c63da97 8265#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8266 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8267 && exp_seg != absolute_section
47926f60 8268 && exp_seg != text_section
24eab124
AM		 8269 && exp_seg != data_section
8270 && exp_seg != bss_section
8271 && exp_seg != undefined_section
f86103b7 8272 && !bfd_is_com_section (exp_seg))
252b5132 8273 {
d0b47220 8274 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8275 return 0;
8276 }
8277#endif
a841bdf5 8278 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8279 {
313c53d1
L		 8280 if (imm_start)
8281 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8282 return 0;
8283 }
252b5132
RH		 8284 else
8285 {
8286 /* This is an address. The size of the address will be
24eab124 8287 determined later, depending on destination register,
3e73aa7c 8288 suffix, or the default for the section. */
40fb9820
L		 8289 i.types[this_operand].bitfield.imm8 = 1;
8290 i.types[this_operand].bitfield.imm16 = 1;
8291 i.types[this_operand].bitfield.imm32 = 1;
8292 i.types[this_operand].bitfield.imm32s = 1;
8293 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8294 i.types[this_operand] = operand_type_and (i.types[this_operand],
8295 types);
252b5132
RH		 8296 }
8297
8298 return 1;
8299}
8300
551c1ca1 8301static char *
e3bb37b5 8302i386_scale (char *scale)
252b5132 8303{
551c1ca1
AM		 8304 offsetT val;
8305 char *save = input_line_pointer;
252b5132 8306
551c1ca1
AM		 8307 input_line_pointer = scale;
8308 val = get_absolute_expression ();
8309
8310 switch (val)
252b5132 8311 {
551c1ca1 8312 case 1:
252b5132
RH		 8313 i.log2_scale_factor = 0;
8314 break;
551c1ca1 8315 case 2:
252b5132
RH		 8316 i.log2_scale_factor = 1;
8317 break;
551c1ca1 8318 case 4:
252b5132
RH		 8319 i.log2_scale_factor = 2;
8320 break;
551c1ca1 8321 case 8:
252b5132
RH		 8322 i.log2_scale_factor = 3;
8323 break;
8324 default:
a724f0f4
JB		 8325 {
8326 char sep = *input_line_pointer;
8327
8328 *input_line_pointer = '\0';
8329 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8330 scale);
8331 *input_line_pointer = sep;
8332 input_line_pointer = save;
8333 return NULL;
8334 }
252b5132 8335 }
29b0f896 8336 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8337 {
8338 as_warn (_("scale factor of %d without an index register"),
24eab124 8339 1 << i.log2_scale_factor);
252b5132 8340 i.log2_scale_factor = 0;
252b5132 8341 }
551c1ca1
AM		 8342 scale = input_line_pointer;
8343 input_line_pointer = save;
8344 return scale;
252b5132
RH		 8345}
8346
252b5132 8347static int
e3bb37b5 8348i386_displacement (char *disp_start, char *disp_end)
252b5132 8349{
29b0f896 8350 expressionS *exp;
252b5132
RH		 8351 segT exp_seg = 0;
8352 char *save_input_line_pointer;
f3c180ae 8353 char *gotfree_input_line;
40fb9820
L		 8354 int override;
8355 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8356 int ret;
252b5132 8357
31b2323c
L		 8358 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8359 {
8360 as_bad (_("at most %d displacement operands are allowed"),
8361 MAX_MEMORY_OPERANDS);
8362 return 0;
8363 }
8364
0dfbf9d7 8365 operand_type_set (&bigdisp, 0);
40fb9820
L		 8366 if ((i.types[this_operand].bitfield.jumpabsolute)
8367 || (!current_templates->start->opcode_modifier.jump
8368 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8369 {
40fb9820 8370 bigdisp.bitfield.disp32 = 1;
e05278af 8371 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8372 if (flag_code == CODE_64BIT)
8373 {
8374 if (!override)
8375 {
8376 bigdisp.bitfield.disp32s = 1;
8377 bigdisp.bitfield.disp64 = 1;
8378 }
8379 }
8380 else if ((flag_code == CODE_16BIT) ^ override)
8381 {
8382 bigdisp.bitfield.disp32 = 0;
8383 bigdisp.bitfield.disp16 = 1;
8384 }
e05278af
JB		 8385 }
8386 else
8387 {
8388 /* For PC-relative branches, the width of the displacement
8389 is dependent upon data size, not address size. */
e05278af 8390 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8391 if (flag_code == CODE_64BIT)
8392 {
8393 if (override || i.suffix == WORD_MNEM_SUFFIX)
8394 bigdisp.bitfield.disp16 = 1;
8395 else
8396 {
8397 bigdisp.bitfield.disp32 = 1;
8398 bigdisp.bitfield.disp32s = 1;
8399 }
8400 }
8401 else
e05278af
JB		 8402 {
8403 if (!override)
8404 override = (i.suffix == (flag_code != CODE_16BIT
8405 ? WORD_MNEM_SUFFIX
8406 : LONG_MNEM_SUFFIX));
40fb9820
L		 8407 bigdisp.bitfield.disp32 = 1;
8408 if ((flag_code == CODE_16BIT) ^ override)
8409 {
8410 bigdisp.bitfield.disp32 = 0;
8411 bigdisp.bitfield.disp16 = 1;
8412 }
e05278af 8413 }
e05278af 8414 }
c6fb90c8
L		 8415 i.types[this_operand] = operand_type_or (i.types[this_operand],
8416 bigdisp);
252b5132
RH		 8417
8418 exp = &disp_expressions[i.disp_operands];
520dc8e8 8419 i.op[this_operand].disps = exp;
252b5132
RH		 8420 i.disp_operands++;
8421 save_input_line_pointer = input_line_pointer;
8422 input_line_pointer = disp_start;
8423 END_STRING_AND_SAVE (disp_end);
8424
8425#ifndef GCC_ASM_O_HACK
8426#define GCC_ASM_O_HACK 0
8427#endif
8428#if GCC_ASM_O_HACK
8429 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8430 if (i.types[this_operand].bitfield.baseIndex
24eab124 8431 && displacement_string_end[-1] == '+')
252b5132
RH		 8432 {
8433 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8434 constraint within gcc asm statements.
8435 For instance:
8436
8437 #define _set_tssldt_desc(n,addr,limit,type) \
8438 __asm__ __volatile__ ( \
8439 "movw %w2,%0\n\t" \
8440 "movw %w1,2+%0\n\t" \
8441 "rorl $16,%1\n\t" \
8442 "movb %b1,4+%0\n\t" \
8443 "movb %4,5+%0\n\t" \
8444 "movb $0,6+%0\n\t" \
8445 "movb %h1,7+%0\n\t" \
8446 "rorl $16,%1" \
8447 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8448
8449 This works great except that the output assembler ends
8450 up looking a bit weird if it turns out that there is
8451 no offset. You end up producing code that looks like:
8452
8453 #APP
8454 movw $235,(%eax)
8455 movw %dx,2+(%eax)
8456 rorl $16,%edx
8457 movb %dl,4+(%eax)
8458 movb $137,5+(%eax)
8459 movb $0,6+(%eax)
8460 movb %dh,7+(%eax)
8461 rorl $16,%edx
8462 #NO_APP
8463
47926f60 8464 So here we provide the missing zero. */
24eab124
AM		 8465
8466 *displacement_string_end = '0';
252b5132
RH		 8467 }
8468#endif
d258b828 8469 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8470 if (gotfree_input_line)
8471 input_line_pointer = gotfree_input_line;
252b5132 8472
24eab124 8473 exp_seg = expression (exp);
252b5132 8474
636c26b0
AM		 8475 SKIP_WHITESPACE ();
8476 if (*input_line_pointer)
8477 as_bad (_("junk `%s' after expression"), input_line_pointer);
8478#if GCC_ASM_O_HACK
8479 RESTORE_END_STRING (disp_end + 1);
8480#endif
636c26b0 8481 input_line_pointer = save_input_line_pointer;
636c26b0 8482 if (gotfree_input_line)
ee86248c
JB		 8483 {
8484 free (gotfree_input_line);
8485
8486 if (exp->X_op == O_constant || exp->X_op == O_register)
8487 exp->X_op = O_illegal;
8488 }
8489
8490 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8491
8492 RESTORE_END_STRING (disp_end);
8493
8494 return ret;
8495}
8496
8497static int
8498i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8499 i386_operand_type types, const char *disp_start)
8500{
8501 i386_operand_type bigdisp;
8502 int ret = 1;
636c26b0 8503
24eab124
AM		 8504 /* We do this to make sure that the section symbol is in
8505 the symbol table. We will ultimately change the relocation
47926f60 8506 to be relative to the beginning of the section. */
1ae12ab7 8507 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8508 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8509 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8510 {
636c26b0 8511 if (exp->X_op != O_symbol)
3992d3b7 8512 goto inv_disp;
636c26b0 8513
e5cb08ac 8514 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8515 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8516 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8517 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8518 exp->X_op = O_subtract;
8519 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8520 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8521 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8522 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8523 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8524 else
29b0f896 8525 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8526 }
252b5132 8527
3992d3b7
AM		 8528 else if (exp->X_op == O_absent
8529 || exp->X_op == O_illegal
ee86248c 8530 || exp->X_op == O_big)
2daf4fd8 8531 {
3992d3b7
AM		 8532 inv_disp:
8533 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8534 disp_start);
3992d3b7 8535 ret = 0;
2daf4fd8
AM		 8536 }
8537
0e1147d9
L		 8538 else if (flag_code == CODE_64BIT
8539 && !i.prefix[ADDR_PREFIX]
8540 && exp->X_op == O_constant)
8541 {
8542 /* Since displacement is signed extended to 64bit, don't allow
8543 disp32 and turn off disp32s if they are out of range. */
8544 i.types[this_operand].bitfield.disp32 = 0;
8545 if (!fits_in_signed_long (exp->X_add_number))
8546 {
8547 i.types[this_operand].bitfield.disp32s = 0;
8548 if (i.types[this_operand].bitfield.baseindex)
8549 {
8550 as_bad (_("0x%lx out range of signed 32bit displacement"),
8551 (long) exp->X_add_number);
8552 ret = 0;
8553 }
8554 }
8555 }
8556
4c63da97 8557#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8558 else if (exp->X_op != O_constant
8559 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8560 && exp_seg != absolute_section
8561 && exp_seg != text_section
8562 && exp_seg != data_section
8563 && exp_seg != bss_section
8564 && exp_seg != undefined_section
8565 && !bfd_is_com_section (exp_seg))
24eab124 8566 {
d0b47220 8567 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8568 ret = 0;
24eab124 8569 }
252b5132 8570#endif
3956db08 8571
40fb9820
L		 8572 /* Check if this is a displacement only operand. */
8573 bigdisp = i.types[this_operand];
8574 bigdisp.bitfield.disp8 = 0;
8575 bigdisp.bitfield.disp16 = 0;
8576 bigdisp.bitfield.disp32 = 0;
8577 bigdisp.bitfield.disp32s = 0;
8578 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8579 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8580 i.types[this_operand] = operand_type_and (i.types[this_operand],
8581 types);
3956db08 8582
3992d3b7 8583 return ret;
252b5132
RH		 8584}
8585
eecb386c 8586/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8587 Return 1 on success, 0 on a failure. */
8588
252b5132 8589static int
e3bb37b5 8590i386_index_check (const char *operand_string)
252b5132 8591{
fc0763e6 8592 const char *kind = "base/index";
be05d201
L		 8593 enum flag_code addr_mode;
8594
8595 if (i.prefix[ADDR_PREFIX])
8596 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8597 else
8598 {
8599 addr_mode = flag_code;
8600
24eab124 8601#if INFER_ADDR_PREFIX
be05d201
L		 8602 if (i.mem_operands == 0)
8603 {
8604 /* Infer address prefix from the first memory operand. */
8605 const reg_entry *addr_reg = i.base_reg;
8606
8607 if (addr_reg == NULL)
8608 addr_reg = i.index_reg;
eecb386c 8609
be05d201
L		 8610 if (addr_reg)
8611 {
8612 if (addr_reg->reg_num == RegEip
8613 || addr_reg->reg_num == RegEiz
8614 || addr_reg->reg_type.bitfield.reg32)
8615 addr_mode = CODE_32BIT;
8616 else if (flag_code != CODE_64BIT
8617 && addr_reg->reg_type.bitfield.reg16)
8618 addr_mode = CODE_16BIT;
8619
8620 if (addr_mode != flag_code)
8621 {
8622 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8623 i.prefixes += 1;
8624 /* Change the size of any displacement too. At most one
8625 of Disp16 or Disp32 is set.
8626 FIXME. There doesn't seem to be any real need for
8627 separate Disp16 and Disp32 flags. The same goes for
8628 Imm16 and Imm32. Removing them would probably clean
8629 up the code quite a lot. */
8630 if (flag_code != CODE_64BIT
8631 && (i.types[this_operand].bitfield.disp16
8632 || i.types[this_operand].bitfield.disp32))
8633 i.types[this_operand]
8634 = operand_type_xor (i.types[this_operand], disp16_32);
8635 }
8636 }
8637 }
24eab124 8638#endif
be05d201
L		 8639 }
8640
fc0763e6
JB		 8641 if (current_templates->start->opcode_modifier.isstring
8642 && !current_templates->start->opcode_modifier.immext
8643 && (current_templates->end[-1].opcode_modifier.isstring
8644 || i.mem_operands))
8645 {
8646 /* Memory operands of string insns are special in that they only allow
8647 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8648 const reg_entry *expected_reg;
8649 static const char *di_si[][2] =
8650 {
8651 { "esi", "edi" },
8652 { "si", "di" },
8653 { "rsi", "rdi" }
8654 };
8655 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8656
8657 kind = "string address";
8658
8325cc63 8659 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 8660 {
8661 i386_operand_type type = current_templates->end[-1].operand_types[0];
8662
8663 if (!type.bitfield.baseindex
8664 || ((!i.mem_operands != !intel_syntax)
8665 && current_templates->end[-1].operand_types[1]
8666 .bitfield.baseindex))
8667 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8668 expected_reg = hash_find (reg_hash,
8669 di_si[addr_mode][type.bitfield.esseg]);
8670
fc0763e6
JB		 8671 }
8672 else
be05d201 8673 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8674
be05d201
L		 8675 if (i.base_reg != expected_reg
8676 || i.index_reg
fc0763e6 8677 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8678 {
be05d201
L		 8679 /* The second memory operand must have the same size as
8680 the first one. */
8681 if (i.mem_operands
8682 && i.base_reg
8683 && !((addr_mode == CODE_64BIT
8684 && i.base_reg->reg_type.bitfield.reg64)
8685 || (addr_mode == CODE_32BIT
8686 ? i.base_reg->reg_type.bitfield.reg32
8687 : i.base_reg->reg_type.bitfield.reg16)))
8688 goto bad_address;
8689
fc0763e6
JB		 8690 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8691 operand_string,
8692 intel_syntax ? '[' : '(',
8693 register_prefix,
be05d201 8694 expected_reg->reg_name,
fc0763e6 8695 intel_syntax ? ']' : ')');
be05d201 8696 return 1;
fc0763e6 8697 }
be05d201
L		 8698 else
8699 return 1;
8700
8701bad_address:
8702 as_bad (_("`%s' is not a valid %s expression"),
8703 operand_string, kind);
8704 return 0;
3e73aa7c
JH		 8705 }
8706 else
8707 {
be05d201
L		 8708 if (addr_mode != CODE_16BIT)
8709 {
8710 /* 32-bit/64-bit checks. */
8711 if ((i.base_reg
8712 && (addr_mode == CODE_64BIT
8713 ? !i.base_reg->reg_type.bitfield.reg64
8714 : !i.base_reg->reg_type.bitfield.reg32)
8715 && (i.index_reg
8716 || (i.base_reg->reg_num
8717 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8718 || (i.index_reg
8719 && !i.index_reg->reg_type.bitfield.regxmm
8720 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8721 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8722 && ((addr_mode == CODE_64BIT
8723 ? !(i.index_reg->reg_type.bitfield.reg64
8724 || i.index_reg->reg_num == RegRiz)
8725 : !(i.index_reg->reg_type.bitfield.reg32
8726 || i.index_reg->reg_num == RegEiz))
8727 || !i.index_reg->reg_type.bitfield.baseindex)))
8728 goto bad_address;
8178be5b
JB		 8729
8730 /* bndmk, bndldx, and bndstx have special restrictions. */
8731 if (current_templates->start->base_opcode == 0xf30f1b
8732 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8733 {
8734 /* They cannot use RIP-relative addressing. */
8735 if (i.base_reg && i.base_reg->reg_num == RegRip)
8736 {
8737 as_bad (_("`%s' cannot be used here"), operand_string);
8738 return 0;
8739 }
8740
8741 /* bndldx and bndstx ignore their scale factor. */
8742 if (current_templates->start->base_opcode != 0xf30f1b
8743 && i.log2_scale_factor)
8744 as_warn (_("register scaling is being ignored here"));
8745 }
be05d201
L		 8746 }
8747 else
3e73aa7c 8748 {
be05d201 8749 /* 16-bit checks. */
3e73aa7c 8750 if ((i.base_reg
40fb9820
L		 8751 && (!i.base_reg->reg_type.bitfield.reg16
8752 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8753 || (i.index_reg
40fb9820
L		 8754 && (!i.index_reg->reg_type.bitfield.reg16
8755 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8756 || !(i.base_reg
8757 && i.base_reg->reg_num < 6
8758 && i.index_reg->reg_num >= 6
8759 && i.log2_scale_factor == 0))))
be05d201 8760 goto bad_address;
3e73aa7c
JH		 8761 }
8762 }
be05d201 8763 return 1;
24eab124 8764}
252b5132 8765
43234a1e
L		 8766/* Handle vector immediates. */
8767
8768static int
8769RC_SAE_immediate (const char *imm_start)
8770{
8771 unsigned int match_found, j;
8772 const char *pstr = imm_start;
8773 expressionS *exp;
8774
8775 if (*pstr != '{')
8776 return 0;
8777
8778 pstr++;
8779 match_found = 0;
8780 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8781 {
8782 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8783 {
8784 if (!i.rounding)
8785 {
8786 rc_op.type = RC_NamesTable[j].type;
8787 rc_op.operand = this_operand;
8788 i.rounding = &rc_op;
8789 }
8790 else
8791 {
8792 as_bad (_("duplicated `%s'"), imm_start);
8793 return 0;
8794 }
8795 pstr += RC_NamesTable[j].len;
8796 match_found = 1;
8797 break;
8798 }
8799 }
8800 if (!match_found)
8801 return 0;
8802
8803 if (*pstr++ != '}')
8804 {
8805 as_bad (_("Missing '}': '%s'"), imm_start);
8806 return 0;
8807 }
8808 /* RC/SAE immediate string should contain nothing more. */;
8809 if (*pstr != 0)
8810 {
8811 as_bad (_("Junk after '}': '%s'"), imm_start);
8812 return 0;
8813 }
8814
8815 exp = &im_expressions[i.imm_operands++];
8816 i.op[this_operand].imms = exp;
8817
8818 exp->X_op = O_constant;
8819 exp->X_add_number = 0;
8820 exp->X_add_symbol = (symbolS *) 0;
8821 exp->X_op_symbol = (symbolS *) 0;
8822
8823 i.types[this_operand].bitfield.imm8 = 1;
8824 return 1;
8825}
8826
8325cc63
JB		 8827/* Only string instructions can have a second memory operand, so
8828 reduce current_templates to just those if it contains any. */
8829static int
8830maybe_adjust_templates (void)
8831{
8832 const insn_template *t;
8833
8834 gas_assert (i.mem_operands == 1);
8835
8836 for (t = current_templates->start; t < current_templates->end; ++t)
8837 if (t->opcode_modifier.isstring)
8838 break;
8839
8840 if (t < current_templates->end)
8841 {
8842 static templates aux_templates;
8843 bfd_boolean recheck;
8844
8845 aux_templates.start = t;
8846 for (; t < current_templates->end; ++t)
8847 if (!t->opcode_modifier.isstring)
8848 break;
8849 aux_templates.end = t;
8850
8851 /* Determine whether to re-check the first memory operand. */
8852 recheck = (aux_templates.start != current_templates->start
8853 || t != current_templates->end);
8854
8855 current_templates = &aux_templates;
8856
8857 if (recheck)
8858 {
8859 i.mem_operands = 0;
8860 if (i.memop1_string != NULL
8861 && i386_index_check (i.memop1_string) == 0)
8862 return 0;
8863 i.mem_operands = 1;
8864 }
8865 }
8866
8867 return 1;
8868}
8869
fc0763e6 8870/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8871 on error. */
252b5132 8872
252b5132 8873static int
a7619375 8874i386_att_operand (char *operand_string)
252b5132 8875{
af6bdddf
AM		 8876 const reg_entry *r;
8877 char *end_op;
24eab124 8878 char *op_string = operand_string;
252b5132 8879
24eab124 8880 if (is_space_char (*op_string))
252b5132
RH		 8881 ++op_string;
8882
24eab124 8883 /* We check for an absolute prefix (differentiating,
47926f60 8884 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8885 if (*op_string == ABSOLUTE_PREFIX)
8886 {
8887 ++op_string;
8888 if (is_space_char (*op_string))
8889 ++op_string;
40fb9820 8890 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8891 }
252b5132 8892
47926f60 8893 /* Check if operand is a register. */
4d1bb795 8894 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8895 {
40fb9820
L		 8896 i386_operand_type temp;
8897
24eab124
AM		 8898 /* Check for a segment override by searching for ':' after a
8899 segment register. */
8900 op_string = end_op;
8901 if (is_space_char (*op_string))
8902 ++op_string;
40fb9820
L		 8903 if (*op_string == ':'
8904 && (r->reg_type.bitfield.sreg2
8905 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8906 {
8907 switch (r->reg_num)
8908 {
8909 case 0:
8910 i.seg[i.mem_operands] = &es;
8911 break;
8912 case 1:
8913 i.seg[i.mem_operands] = &cs;
8914 break;
8915 case 2:
8916 i.seg[i.mem_operands] = &ss;
8917 break;
8918 case 3:
8919 i.seg[i.mem_operands] = &ds;
8920 break;
8921 case 4:
8922 i.seg[i.mem_operands] = &fs;
8923 break;
8924 case 5:
8925 i.seg[i.mem_operands] = &gs;
8926 break;
8927 }
252b5132 8928
24eab124 8929 /* Skip the ':' and whitespace. */
252b5132
RH		 8930 ++op_string;
8931 if (is_space_char (*op_string))
24eab124 8932 ++op_string;
252b5132 8933
24eab124
AM		 8934 if (!is_digit_char (*op_string)
8935 && !is_identifier_char (*op_string)
8936 && *op_string != '('
8937 && *op_string != ABSOLUTE_PREFIX)
8938 {
8939 as_bad (_("bad memory operand `%s'"), op_string);
8940 return 0;
8941 }
47926f60 8942 /* Handle case of %es:*foo. */
24eab124
AM		 8943 if (*op_string == ABSOLUTE_PREFIX)
8944 {
8945 ++op_string;
8946 if (is_space_char (*op_string))
8947 ++op_string;
40fb9820 8948 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8949 }
8950 goto do_memory_reference;
8951 }
43234a1e
L		 8952
8953 /* Handle vector operations. */
8954 if (*op_string == '{')
8955 {
8956 op_string = check_VecOperations (op_string, NULL);
8957 if (op_string == NULL)
8958 return 0;
8959 }
8960
24eab124
AM		 8961 if (*op_string)
8962 {
d0b47220 8963 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8964 return 0;
8965 }
40fb9820
L		 8966 temp = r->reg_type;
8967 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8968 i.types[this_operand] = operand_type_or (i.types[this_operand],
8969 temp);
7d5e4556 8970 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8971 i.op[this_operand].regs = r;
24eab124
AM		 8972 i.reg_operands++;
8973 }
af6bdddf
AM		 8974 else if (*op_string == REGISTER_PREFIX)
8975 {
8976 as_bad (_("bad register name `%s'"), op_string);
8977 return 0;
8978 }
24eab124 8979 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8980 {
24eab124 8981 ++op_string;
40fb9820 8982 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8983 {
d0b47220 8984 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8985 return 0;
8986 }
8987 if (!i386_immediate (op_string))
8988 return 0;
8989 }
43234a1e
L		 8990 else if (RC_SAE_immediate (operand_string))
8991 {
8992 /* If it is a RC or SAE immediate, do nothing. */
8993 ;
8994 }
24eab124
AM		 8995 else if (is_digit_char (*op_string)
8996 || is_identifier_char (*op_string)
d02603dc 8997 || *op_string == '"'
e5cb08ac 8998 || *op_string == '(')
24eab124 8999 {
47926f60 9000 /* This is a memory reference of some sort. */
af6bdddf 9001 char *base_string;
252b5132 9002
47926f60 9003 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9004 char *displacement_string_start;
9005 char *displacement_string_end;
43234a1e 9006 char *vop_start;
252b5132 9007
24eab124 9008 do_memory_reference:
8325cc63
JB		 9009 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9010 return 0;
24eab124 9011 if ((i.mem_operands == 1
40fb9820 9012 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9013 || i.mem_operands == 2)
9014 {
9015 as_bad (_("too many memory references for `%s'"),
9016 current_templates->start->name);
9017 return 0;
9018 }
252b5132 9019
24eab124
AM		 9020 /* Check for base index form. We detect the base index form by
9021 looking for an ')' at the end of the operand, searching
9022 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9023 after the '('. */
af6bdddf 9024 base_string = op_string + strlen (op_string);
c3332e24 9025
43234a1e
L		 9026 /* Handle vector operations. */
9027 vop_start = strchr (op_string, '{');
9028 if (vop_start && vop_start < base_string)
9029 {
9030 if (check_VecOperations (vop_start, base_string) == NULL)
9031 return 0;
9032 base_string = vop_start;
9033 }
9034
af6bdddf
AM		 9035 --base_string;
9036 if (is_space_char (*base_string))
9037 --base_string;
252b5132 9038
47926f60 9039 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9040 displacement_string_start = op_string;
9041 displacement_string_end = base_string + 1;
252b5132 9042
24eab124
AM		 9043 if (*base_string == ')')
9044 {
af6bdddf 9045 char *temp_string;
24eab124
AM		 9046 unsigned int parens_balanced = 1;
9047 /* We've already checked that the number of left & right ()'s are
47926f60 9048 equal, so this loop will not be infinite. */
24eab124
AM		 9049 do
9050 {
9051 base_string--;
9052 if (*base_string == ')')
9053 parens_balanced++;
9054 if (*base_string == '(')
9055 parens_balanced--;
9056 }
9057 while (parens_balanced);
c3332e24 9058
af6bdddf 9059 temp_string = base_string;
c3332e24 9060
24eab124 9061 /* Skip past '(' and whitespace. */
252b5132
RH		 9062 ++base_string;
9063 if (is_space_char (*base_string))
24eab124 9064 ++base_string;
252b5132 9065
af6bdddf 9066 if (*base_string == ','
4eed87de
AM		 9067 || ((i.base_reg = parse_register (base_string, &end_op))
9068 != NULL))
252b5132 9069 {
af6bdddf 9070 displacement_string_end = temp_string;
252b5132 9071
40fb9820 9072 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9073
af6bdddf 9074 if (i.base_reg)
24eab124 9075 {
24eab124
AM		 9076 base_string = end_op;
9077 if (is_space_char (*base_string))
9078 ++base_string;
af6bdddf
AM		 9079 }
9080
9081 /* There may be an index reg or scale factor here. */
9082 if (*base_string == ',')
9083 {
9084 ++base_string;
9085 if (is_space_char (*base_string))
9086 ++base_string;
9087
4eed87de
AM		 9088 if ((i.index_reg = parse_register (base_string, &end_op))
9089 != NULL)
24eab124 9090 {
af6bdddf 9091 base_string = end_op;
24eab124
AM		 9092 if (is_space_char (*base_string))
9093 ++base_string;
af6bdddf
AM		 9094 if (*base_string == ',')
9095 {
9096 ++base_string;
9097 if (is_space_char (*base_string))
9098 ++base_string;
9099 }
e5cb08ac 9100 else if (*base_string != ')')
af6bdddf 9101 {
4eed87de
AM		 9102 as_bad (_("expecting `,' or `)' "
9103 "after index register in `%s'"),
af6bdddf
AM		 9104 operand_string);
9105 return 0;
9106 }
24eab124 9107 }
af6bdddf 9108 else if (*base_string == REGISTER_PREFIX)
24eab124 9109 {
f76bf5e0
L		 9110 end_op = strchr (base_string, ',');
9111 if (end_op)
9112 *end_op = '\0';
af6bdddf 9113 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9114 return 0;
9115 }
252b5132 9116
47926f60 9117 /* Check for scale factor. */
551c1ca1 9118 if (*base_string != ')')
af6bdddf 9119 {
551c1ca1
AM		 9120 char *end_scale = i386_scale (base_string);
9121
9122 if (!end_scale)
af6bdddf 9123 return 0;
24eab124 9124
551c1ca1 9125 base_string = end_scale;
af6bdddf
AM		 9126 if (is_space_char (*base_string))
9127 ++base_string;
9128 if (*base_string != ')')
9129 {
4eed87de
AM		 9130 as_bad (_("expecting `)' "
9131 "after scale factor in `%s'"),
af6bdddf
AM		 9132 operand_string);
9133 return 0;
9134 }
9135 }
9136 else if (!i.index_reg)
24eab124 9137 {
4eed87de
AM		 9138 as_bad (_("expecting index register or scale factor "
9139 "after `,'; got '%c'"),
af6bdddf 9140 *base_string);
24eab124
AM		 9141 return 0;
9142 }
9143 }
af6bdddf 9144 else if (*base_string != ')')
24eab124 9145 {
4eed87de
AM		 9146 as_bad (_("expecting `,' or `)' "
9147 "after base register in `%s'"),
af6bdddf 9148 operand_string);
24eab124
AM		 9149 return 0;
9150 }
c3332e24 9151 }
af6bdddf 9152 else if (*base_string == REGISTER_PREFIX)
c3332e24 9153 {
f76bf5e0
L		 9154 end_op = strchr (base_string, ',');
9155 if (end_op)
9156 *end_op = '\0';
af6bdddf 9157 as_bad (_("bad register name `%s'"), base_string);
24eab124 9158 return 0;
c3332e24 9159 }
24eab124
AM		 9160 }
9161
9162 /* If there's an expression beginning the operand, parse it,
9163 assuming displacement_string_start and
9164 displacement_string_end are meaningful. */
9165 if (displacement_string_start != displacement_string_end)
9166 {
9167 if (!i386_displacement (displacement_string_start,
9168 displacement_string_end))
9169 return 0;
9170 }
9171
9172 /* Special case for (%dx) while doing input/output op. */
9173 if (i.base_reg
0dfbf9d7
L		 9174 && operand_type_equal (&i.base_reg->reg_type,
9175 &reg16_inoutportreg)
24eab124
AM		 9176 && i.index_reg == 0
9177 && i.log2_scale_factor == 0
9178 && i.seg[i.mem_operands] == 0
40fb9820 9179 && !operand_type_check (i.types[this_operand], disp))
24eab124 9180 {
65da13b5 9181 i.types[this_operand] = inoutportreg;
24eab124
AM		 9182 return 1;
9183 }
9184
eecb386c
AM		 9185 if (i386_index_check (operand_string) == 0)
9186 return 0;
5c07affc 9187 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9188 if (i.mem_operands == 0)
9189 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9190 i.mem_operands++;
9191 }
9192 else
ce8a8b2f
AM		 9193 {
9194 /* It's not a memory operand; argh! */
24eab124
AM		 9195 as_bad (_("invalid char %s beginning operand %d `%s'"),
9196 output_invalid (*op_string),
9197 this_operand + 1,
9198 op_string);
9199 return 0;
9200 }
47926f60 9201 return 1; /* Normal return. */
252b5132
RH		 9202}
9203\f
fa94de6b
RM		 9204/* Calculate the maximum variable size (i.e., excluding fr_fix)
9205 that an rs_machine_dependent frag may reach. */
9206
9207unsigned int
9208i386_frag_max_var (fragS *frag)
9209{
9210 /* The only relaxable frags are for jumps.
9211 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9212 gas_assert (frag->fr_type == rs_machine_dependent);
9213 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9214}
9215
b084df0b
L		 9216#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9217static int
8dcea932 9218elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9219{
9220 /* STT_GNU_IFUNC symbol must go through PLT. */
9221 if ((symbol_get_bfdsym (fr_symbol)->flags
9222 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9223 return 0;
9224
9225 if (!S_IS_EXTERNAL (fr_symbol))
9226 /* Symbol may be weak or local. */
9227 return !S_IS_WEAK (fr_symbol);
9228
8dcea932
L		 9229 /* Global symbols with non-default visibility can't be preempted. */
9230 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9231 return 1;
9232
9233 if (fr_var != NO_RELOC)
9234 switch ((enum bfd_reloc_code_real) fr_var)
9235 {
9236 case BFD_RELOC_386_PLT32:
9237 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9238 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9239 return 0;
9240 default:
9241 abort ();
9242 }
9243
b084df0b
L		 9244 /* Global symbols with default visibility in a shared library may be
9245 preempted by another definition. */
8dcea932 9246 return !shared;
b084df0b
L		 9247}
9248#endif
9249
ee7fcc42
AM		 9250/* md_estimate_size_before_relax()
9251
9252 Called just before relax() for rs_machine_dependent frags. The x86
9253 assembler uses these frags to handle variable size jump
9254 instructions.
9255
9256 Any symbol that is now undefined will not become defined.
9257 Return the correct fr_subtype in the frag.
9258 Return the initial "guess for variable size of frag" to caller.
9259 The guess is actually the growth beyond the fixed part. Whatever
9260 we do to grow the fixed or variable part contributes to our
9261 returned value. */
9262
252b5132 9263int
7016a5d5 9264md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9265{
252b5132 9266 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9267 check for un-relaxable symbols. On an ELF system, we can't relax
9268 an externally visible symbol, because it may be overridden by a
9269 shared library. */
9270 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9271#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9272 || (IS_ELF
8dcea932
L		 9273 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9274 fragP->fr_var))
fbeb56a4
DK		 9275#endif
9276#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9277 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9278 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9279#endif
9280 )
252b5132 9281 {
b98ef147
AM		 9282 /* Symbol is undefined in this segment, or we need to keep a
9283 reloc so that weak symbols can be overridden. */
9284 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9285 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9286 unsigned char *opcode;
9287 int old_fr_fix;
f6af82bd 9288
ee7fcc42 9289 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9290 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9291 else if (size == 2)
f6af82bd
AM		 9292 reloc_type = BFD_RELOC_16_PCREL;
9293 else
9294 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9295
ee7fcc42
AM		 9296 old_fr_fix = fragP->fr_fix;
9297 opcode = (unsigned char *) fragP->fr_opcode;
9298
fddf5b5b 9299 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9300 {
fddf5b5b
AM		 9301 case UNCOND_JUMP:
9302 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9303 opcode[0] = 0xe9;
252b5132 9304 fragP->fr_fix += size;
062cd5e7
AS		 9305 fix_new (fragP, old_fr_fix, size,
9306 fragP->fr_symbol,
9307 fragP->fr_offset, 1,
9308 reloc_type);
252b5132
RH		 9309 break;
9310
fddf5b5b 9311 case COND_JUMP86:
412167cb
AM		 9312 if (size == 2
9313 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9314 {
9315 /* Negate the condition, and branch past an
9316 unconditional jump. */
9317 opcode[0] ^= 1;
9318 opcode[1] = 3;
9319 /* Insert an unconditional jump. */
9320 opcode[2] = 0xe9;
9321 /* We added two extra opcode bytes, and have a two byte
9322 offset. */
9323 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9324 fix_new (fragP, old_fr_fix + 2, 2,
9325 fragP->fr_symbol,
9326 fragP->fr_offset, 1,
9327 reloc_type);
fddf5b5b
AM		 9328 break;
9329 }
9330 /* Fall through. */
9331
9332 case COND_JUMP:
412167cb
AM		 9333 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9334 {
3e02c1cc
AM		 9335 fixS *fixP;
9336
412167cb 9337 fragP->fr_fix += 1;
3e02c1cc
AM		 9338 fixP = fix_new (fragP, old_fr_fix, 1,
9339 fragP->fr_symbol,
9340 fragP->fr_offset, 1,
9341 BFD_RELOC_8_PCREL);
9342 fixP->fx_signed = 1;
412167cb
AM		 9343 break;
9344 }
93c2a809 9345
24eab124 9346 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9347 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9348 opcode[1] = opcode[0] + 0x10;
f6af82bd 9349 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9350 /* We've added an opcode byte. */
9351 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9352 fix_new (fragP, old_fr_fix + 1, size,
9353 fragP->fr_symbol,
9354 fragP->fr_offset, 1,
9355 reloc_type);
252b5132 9356 break;
fddf5b5b
AM		 9357
9358 default:
9359 BAD_CASE (fragP->fr_subtype);
9360 break;
252b5132
RH		 9361 }
9362 frag_wane (fragP);
ee7fcc42 9363 return fragP->fr_fix - old_fr_fix;
252b5132 9364 }
93c2a809 9365
93c2a809
AM		 9366 /* Guess size depending on current relax state. Initially the relax
9367 state will correspond to a short jump and we return 1, because
9368 the variable part of the frag (the branch offset) is one byte
9369 long. However, we can relax a section more than once and in that
9370 case we must either set fr_subtype back to the unrelaxed state,
9371 or return the value for the appropriate branch. */
9372 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9373}
9374
47926f60
KH		 9375/* Called after relax() is finished.
9376
9377 In: Address of frag.
9378 fr_type == rs_machine_dependent.
9379 fr_subtype is what the address relaxed to.
9380
9381 Out: Any fixSs and constants are set up.
9382 Caller will turn frag into a ".space 0". */
9383
252b5132 9384void
7016a5d5
TG		 9385md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9386 fragS *fragP)
252b5132 9387{
29b0f896 9388 unsigned char *opcode;
252b5132 9389 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9390 offsetT target_address;
9391 offsetT opcode_address;
252b5132 9392 unsigned int extension = 0;
847f7ad4 9393 offsetT displacement_from_opcode_start;
252b5132
RH		 9394
9395 opcode = (unsigned char *) fragP->fr_opcode;
9396
47926f60 9397 /* Address we want to reach in file space. */
252b5132 9398 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9399
47926f60 9400 /* Address opcode resides at in file space. */
252b5132
RH		 9401 opcode_address = fragP->fr_address + fragP->fr_fix;
9402
47926f60 9403 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9404 displacement_from_opcode_start = target_address - opcode_address;
9405
fddf5b5b 9406 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9407 {
47926f60
KH		 9408 /* Don't have to change opcode. */
9409 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9410 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9411 }
9412 else
9413 {
9414 if (no_cond_jump_promotion
9415 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9416 as_warn_where (fragP->fr_file, fragP->fr_line,
9417 _("long jump required"));
252b5132 9418
fddf5b5b
AM		 9419 switch (fragP->fr_subtype)
9420 {
9421 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9422 extension = 4; /* 1 opcode + 4 displacement */
9423 opcode[0] = 0xe9;
9424 where_to_put_displacement = &opcode[1];
9425 break;
252b5132 9426
fddf5b5b
AM		 9427 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9428 extension = 2; /* 1 opcode + 2 displacement */
9429 opcode[0] = 0xe9;
9430 where_to_put_displacement = &opcode[1];
9431 break;
252b5132 9432
fddf5b5b
AM		 9433 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9434 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9435 extension = 5; /* 2 opcode + 4 displacement */
9436 opcode[1] = opcode[0] + 0x10;
9437 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9438 where_to_put_displacement = &opcode[2];
9439 break;
252b5132 9440
fddf5b5b
AM		 9441 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9442 extension = 3; /* 2 opcode + 2 displacement */
9443 opcode[1] = opcode[0] + 0x10;
9444 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9445 where_to_put_displacement = &opcode[2];
9446 break;
252b5132 9447
fddf5b5b
AM		 9448 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9449 extension = 4;
9450 opcode[0] ^= 1;
9451 opcode[1] = 3;
9452 opcode[2] = 0xe9;
9453 where_to_put_displacement = &opcode[3];
9454 break;
9455
9456 default:
9457 BAD_CASE (fragP->fr_subtype);
9458 break;
9459 }
252b5132 9460 }
fddf5b5b 9461
7b81dfbb
AJ		 9462 /* If size if less then four we are sure that the operand fits,
9463 but if it's 4, then it could be that the displacement is larger
9464 then -/+ 2GB. */
9465 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9466 && object_64bit
9467 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9468 + ((addressT) 1 << 31))
9469 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9470 {
9471 as_bad_where (fragP->fr_file, fragP->fr_line,
9472 _("jump target out of range"));
9473 /* Make us emit 0. */
9474 displacement_from_opcode_start = extension;
9475 }
47926f60 9476 /* Now put displacement after opcode. */
252b5132
RH		 9477 md_number_to_chars ((char *) where_to_put_displacement,
9478 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9479 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9480 fragP->fr_fix += extension;
9481}
9482\f
7016a5d5 9483/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9484 by our caller that we have all the info we need to fix it up.
9485
7016a5d5
TG		 9486 Parameter valP is the pointer to the value of the bits.
9487
252b5132
RH		 9488 On the 386, immediates, displacements, and data pointers are all in
9489 the same (little-endian) format, so we don't need to care about which
9490 we are handling. */
9491
94f592af 9492void
7016a5d5 9493md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9494{
94f592af 9495 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9496 valueT value = *valP;
252b5132 9497
f86103b7 9498#if !defined (TE_Mach)
93382f6d
AM		 9499 if (fixP->fx_pcrel)
9500 {
9501 switch (fixP->fx_r_type)
9502 {
5865bb77
ILT		 9503 default:
9504 break;
9505
d6ab8113
JB		 9506 case BFD_RELOC_64:
9507 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9508 break;
93382f6d 9509 case BFD_RELOC_32:
ae8887b5 9510 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9511 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9512 break;
9513 case BFD_RELOC_16:
9514 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9515 break;
9516 case BFD_RELOC_8:
9517 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9518 break;
9519 }
9520 }
252b5132 9521
a161fe53 9522 if (fixP->fx_addsy != NULL
31312f95 9523 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9524 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9525 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9526 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9527 && !use_rela_relocations)
252b5132 9528 {
31312f95
AM		 9529 /* This is a hack. There should be a better way to handle this.
9530 This covers for the fact that bfd_install_relocation will
9531 subtract the current location (for partial_inplace, PC relative
9532 relocations); see more below. */
252b5132 9533#ifndef OBJ_AOUT
718ddfc0 9534 if (IS_ELF
252b5132
RH		 9535#ifdef TE_PE
9536 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9537#endif
9538 )
9539 value += fixP->fx_where + fixP->fx_frag->fr_address;
9540#endif
9541#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9542 if (IS_ELF)
252b5132 9543 {
6539b54b 9544 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9545
6539b54b 9546 if ((sym_seg == seg
2f66722d 9547 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9548 && sym_seg != absolute_section))
af65af87 9549 && !generic_force_reloc (fixP))
2f66722d
AM		 9550 {
9551 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9552 bfd_install_relocation subtracts them out again. I think
9553 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9554 it. FIXME. */
9555 value += fixP->fx_where + fixP->fx_frag->fr_address;
9556 }
252b5132
RH		 9557 }
9558#endif
9559#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9560 /* For some reason, the PE format does not store a
9561 section address offset for a PC relative symbol. */
9562 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9563 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9564 value += md_pcrel_from (fixP);
9565#endif
9566 }
fbeb56a4 9567#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9568 if (fixP->fx_addsy != NULL
9569 && S_IS_WEAK (fixP->fx_addsy)
9570 /* PR 16858: Do not modify weak function references. */
9571 && ! fixP->fx_pcrel)
fbeb56a4 9572 {
296a8689
NC		 9573#if !defined (TE_PEP)
9574 /* For x86 PE weak function symbols are neither PC-relative
9575 nor do they set S_IS_FUNCTION. So the only reliable way
9576 to detect them is to check the flags of their containing
9577 section. */
9578 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9579 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9580 ;
9581 else
9582#endif
fbeb56a4
DK		 9583 value -= S_GET_VALUE (fixP->fx_addsy);
9584 }
9585#endif
252b5132
RH		 9586
9587 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9588 and we must not disappoint it. */
252b5132 9589#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9590 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9591 switch (fixP->fx_r_type)
9592 {
9593 case BFD_RELOC_386_PLT32:
3e73aa7c 9594 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9595 /* Make the jump instruction point to the address of the operand. At
9596 runtime we merely add the offset to the actual PLT entry. */
9597 value = -4;
9598 break;
31312f95 9599
13ae64f3
JJ		 9600 case BFD_RELOC_386_TLS_GD:
9601 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9602 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9603 case BFD_RELOC_386_TLS_IE:
9604 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9605 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9606 case BFD_RELOC_X86_64_TLSGD:
9607 case BFD_RELOC_X86_64_TLSLD:
9608 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9609 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9610 value = 0; /* Fully resolved at runtime. No addend. */
9611 /* Fallthrough */
9612 case BFD_RELOC_386_TLS_LE:
9613 case BFD_RELOC_386_TLS_LDO_32:
9614 case BFD_RELOC_386_TLS_LE_32:
9615 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9616 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9617 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9618 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9619 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9620 break;
9621
67a4f2b7
AO		 9622 case BFD_RELOC_386_TLS_DESC_CALL:
9623 case BFD_RELOC_X86_64_TLSDESC_CALL:
9624 value = 0; /* Fully resolved at runtime. No addend. */
9625 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9626 fixP->fx_done = 0;
9627 return;
9628
47926f60
KH		 9629 case BFD_RELOC_VTABLE_INHERIT:
9630 case BFD_RELOC_VTABLE_ENTRY:
9631 fixP->fx_done = 0;
94f592af 9632 return;
47926f60
KH		 9633
9634 default:
9635 break;
9636 }
9637#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9638 *valP = value;
f86103b7 9639#endif /* !defined (TE_Mach) */
3e73aa7c 9640
3e73aa7c 9641 /* Are we finished with this relocation now? */
c6682705 9642 if (fixP->fx_addsy == NULL)
3e73aa7c 9643 fixP->fx_done = 1;
fbeb56a4
DK		 9644#if defined (OBJ_COFF) && defined (TE_PE)
9645 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9646 {
9647 fixP->fx_done = 0;
9648 /* Remember value for tc_gen_reloc. */
9649 fixP->fx_addnumber = value;
9650 /* Clear out the frag for now. */
9651 value = 0;
9652 }
9653#endif
3e73aa7c
JH		 9654 else if (use_rela_relocations)
9655 {
9656 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9657 /* Remember value for tc_gen_reloc. */
9658 fixP->fx_addnumber = value;
3e73aa7c
JH		 9659 value = 0;
9660 }
f86103b7 9661
94f592af 9662 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9663}
252b5132 9664\f
6d4af3c2 9665const char *
499ac353 9666md_atof (int type, char *litP, int *sizeP)
252b5132 9667{
499ac353
NC		 9668 /* This outputs the LITTLENUMs in REVERSE order;
9669 in accord with the bigendian 386. */
9670 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9671}
9672\f
2d545b82 9673static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9674
252b5132 9675static char *
e3bb37b5 9676output_invalid (int c)
252b5132 9677{
3882b010 9678 if (ISPRINT (c))
f9f21a03
L		 9679 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9680 "'%c'", c);
252b5132 9681 else
f9f21a03 9682 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9683 "(0x%x)", (unsigned char) c);
252b5132
RH		 9684 return output_invalid_buf;
9685}
9686
af6bdddf 9687/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9688
9689static const reg_entry *
4d1bb795 9690parse_real_register (char *reg_string, char **end_op)
252b5132 9691{
af6bdddf
AM		 9692 char *s = reg_string;
9693 char *p;
252b5132
RH		 9694 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9695 const reg_entry *r;
9696
9697 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9698 if (*s == REGISTER_PREFIX)
9699 ++s;
9700
9701 if (is_space_char (*s))
9702 ++s;
9703
9704 p = reg_name_given;
af6bdddf 9705 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9706 {
9707 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9708 return (const reg_entry *) NULL;
9709 s++;
252b5132
RH		 9710 }
9711
6588847e
DN		 9712 /* For naked regs, make sure that we are not dealing with an identifier.
9713 This prevents confusing an identifier like `eax_var' with register
9714 `eax'. */
9715 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9716 return (const reg_entry *) NULL;
9717
af6bdddf 9718 *end_op = s;
252b5132
RH		 9719
9720 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9721
5f47d35b 9722 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9723 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9724 {
5f47d35b
AM		 9725 if (is_space_char (*s))
9726 ++s;
9727 if (*s == '(')
9728 {
af6bdddf 9729 ++s;
5f47d35b
AM		 9730 if (is_space_char (*s))
9731 ++s;
9732 if (*s >= '0' && *s <= '7')
9733 {
db557034 9734 int fpr = *s - '0';
af6bdddf 9735 ++s;
5f47d35b
AM		 9736 if (is_space_char (*s))
9737 ++s;
9738 if (*s == ')')
9739 {
9740 *end_op = s + 1;
1e9cc1c2 9741 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9742 know (r);
9743 return r + fpr;
5f47d35b 9744 }
5f47d35b 9745 }
47926f60 9746 /* We have "%st(" then garbage. */
5f47d35b
AM		 9747 return (const reg_entry *) NULL;
9748 }
9749 }
9750
a60de03c
JB		 9751 if (r == NULL || allow_pseudo_reg)
9752 return r;
9753
0dfbf9d7 9754 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9755 return (const reg_entry *) NULL;
9756
192dc9c6
JB		 9757 if ((r->reg_type.bitfield.reg32
9758 || r->reg_type.bitfield.sreg3
9759 || r->reg_type.bitfield.control
9760 || r->reg_type.bitfield.debug
9761 || r->reg_type.bitfield.test)
9762 && !cpu_arch_flags.bitfield.cpui386)
9763 return (const reg_entry *) NULL;
9764
309d3373
JB		 9765 if (r->reg_type.bitfield.floatreg
9766 && !cpu_arch_flags.bitfield.cpu8087
9767 && !cpu_arch_flags.bitfield.cpu287
9768 && !cpu_arch_flags.bitfield.cpu387)
9769 return (const reg_entry *) NULL;
9770
1848e567 9771 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 9772 return (const reg_entry *) NULL;
9773
1848e567 9774 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 9775 return (const reg_entry *) NULL;
9776
1848e567 9777 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 9778 return (const reg_entry *) NULL;
9779
1848e567
L		 9780 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
9781 return (const reg_entry *) NULL;
9782
9783 if (r->reg_type.bitfield.regmask
9784 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 9785 return (const reg_entry *) NULL;
9786
db51cc60 9787 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9788 if (!allow_index_reg
db51cc60
L		 9789 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9790 return (const reg_entry *) NULL;
9791
43234a1e
L		 9792 /* Upper 16 vector register is only available with VREX in 64bit
9793 mode. */
9794 if ((r->reg_flags & RegVRex))
9795 {
86fa6981
L		 9796 if (i.vec_encoding == vex_encoding_default)
9797 i.vec_encoding = vex_encoding_evex;
9798
43234a1e 9799 if (!cpu_arch_flags.bitfield.cpuvrex
86fa6981 9800 || i.vec_encoding != vex_encoding_evex
43234a1e
L		 9801 || flag_code != CODE_64BIT)
9802 return (const reg_entry *) NULL;
43234a1e
L		 9803 }
9804
a60de03c
JB		 9805 if (((r->reg_flags & (RegRex64 | RegRex))
9806 || r->reg_type.bitfield.reg64)
40fb9820 9807 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9808 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9809 && flag_code != CODE_64BIT)
20f0a1fc 9810 return (const reg_entry *) NULL;
1ae00879 9811
b7240065
JB		 9812 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9813 return (const reg_entry *) NULL;
9814
252b5132
RH		 9815 return r;
9816}
4d1bb795
JB		 9817
9818/* REG_STRING starts *before* REGISTER_PREFIX. */
9819
9820static const reg_entry *
9821parse_register (char *reg_string, char **end_op)
9822{
9823 const reg_entry *r;
9824
9825 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9826 r = parse_real_register (reg_string, end_op);
9827 else
9828 r = NULL;
9829 if (!r)
9830 {
9831 char *save = input_line_pointer;
9832 char c;
9833 symbolS *symbolP;
9834
9835 input_line_pointer = reg_string;
d02603dc 9836 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9837 symbolP = symbol_find (reg_string);
9838 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9839 {
9840 const expressionS *e = symbol_get_value_expression (symbolP);
9841
0398aac5 9842 know (e->X_op == O_register);
4eed87de 9843 know (e->X_add_number >= 0
c3fe08fa 9844 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9845 r = i386_regtab + e->X_add_number;
d3bb6b49 9846 if ((r->reg_flags & RegVRex))
86fa6981 9847 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 9848 *end_op = input_line_pointer;
9849 }
9850 *input_line_pointer = c;
9851 input_line_pointer = save;
9852 }
9853 return r;
9854}
9855
9856int
9857i386_parse_name (char *name, expressionS *e, char *nextcharP)
9858{
9859 const reg_entry *r;
9860 char *end = input_line_pointer;
9861
9862 *end = *nextcharP;
9863 r = parse_register (name, &input_line_pointer);
9864 if (r && end <= input_line_pointer)
9865 {
9866 *nextcharP = *input_line_pointer;
9867 *input_line_pointer = 0;
9868 e->X_op = O_register;
9869 e->X_add_number = r - i386_regtab;
9870 return 1;
9871 }
9872 input_line_pointer = end;
9873 *end = 0;
ee86248c 9874 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9875}
9876
9877void
9878md_operand (expressionS *e)
9879{
ee86248c
JB		 9880 char *end;
9881 const reg_entry *r;
4d1bb795 9882
ee86248c
JB		 9883 switch (*input_line_pointer)
9884 {
9885 case REGISTER_PREFIX:
9886 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9887 if (r)
9888 {
9889 e->X_op = O_register;
9890 e->X_add_number = r - i386_regtab;
9891 input_line_pointer = end;
9892 }
ee86248c
JB		 9893 break;
9894
9895 case '[':
9c2799c2 9896 gas_assert (intel_syntax);
ee86248c
JB		 9897 end = input_line_pointer++;
9898 expression (e);
9899 if (*input_line_pointer == ']')
9900 {
9901 ++input_line_pointer;
9902 e->X_op_symbol = make_expr_symbol (e);
9903 e->X_add_symbol = NULL;
9904 e->X_add_number = 0;
9905 e->X_op = O_index;
9906 }
9907 else
9908 {
9909 e->X_op = O_absent;
9910 input_line_pointer = end;
9911 }
9912 break;
4d1bb795
JB		 9913 }
9914}
9915
252b5132 9916\f
4cc782b5 9917#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9918const char *md_shortopts = "kVQ:sqn";
252b5132 9919#else
12b55ccc 9920const char *md_shortopts = "qn";
252b5132 9921#endif
6e0b89ee 9922
3e73aa7c 9923#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9924#define OPTION_64 (OPTION_MD_BASE + 1)
9925#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9926#define OPTION_MARCH (OPTION_MD_BASE + 3)
9927#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9928#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9929#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9930#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9931#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9932#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9933#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9934#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9935#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9936#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9937#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9938#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9939#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9940#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9941#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9942#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9943#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9944#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9945#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9946#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9947#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9948#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9949
99ad8390
NC		 9950struct option md_longopts[] =
9951{
3e73aa7c 9952 {"32", no_argument, NULL, OPTION_32},
321098a5 9953#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9954 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9955 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9956#endif
9957#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9958 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9959 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9960#endif
b3b91714 9961 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9962 {"march", required_argument, NULL, OPTION_MARCH},
9963 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9964 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9965 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9966 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9967 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9968 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9969 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9970 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9971 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9972 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9973 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9974 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9975 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9976# if defined (TE_PE) || defined (TE_PEP)
9977 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9978#endif
d1982f93 9979 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 9980 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 9981 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 9982 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9983 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9984 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9985 {NULL, no_argument, NULL, 0}
9986};
9987size_t md_longopts_size = sizeof (md_longopts);
9988
9989int
17b9d67d 9990md_parse_option (int c, const char *arg)
252b5132 9991{
91d6fa6a 9992 unsigned int j;
293f5f65 9993 char *arch, *next, *saved;
9103f4f4 9994
252b5132
RH		 9995 switch (c)
9996 {
12b55ccc
L		 9997 case 'n':
9998 optimize_align_code = 0;
9999 break;
10000
a38cf1db
AM		 10001 case 'q':
10002 quiet_warnings = 1;
252b5132
RH		 10003 break;
10004
10005#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10006 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10007 should be emitted or not. FIXME: Not implemented. */
10008 case 'Q':
252b5132
RH		 10009 break;
10010
10011 /* -V: SVR4 argument to print version ID. */
10012 case 'V':
10013 print_version_id ();
10014 break;
10015
a38cf1db
AM		 10016 /* -k: Ignore for FreeBSD compatibility. */
10017 case 'k':
252b5132 10018 break;
4cc782b5
ILT		 10019
10020 case 's':
10021 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10022 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10023 break;
8dcea932
L		 10024
10025 case OPTION_MSHARED:
10026 shared = 1;
10027 break;
99ad8390 10028#endif
321098a5 10029#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10030 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10031 case OPTION_64:
10032 {
10033 const char **list, **l;
10034
3e73aa7c
JH		 10035 list = bfd_target_list ();
10036 for (l = list; *l != NULL; l++)
8620418b 10037 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10038 || strcmp (*l, "coff-x86-64") == 0
10039 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10040 || strcmp (*l, "pei-x86-64") == 0
10041 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10042 {
10043 default_arch = "x86_64";
10044 break;
10045 }
3e73aa7c 10046 if (*l == NULL)
2b5d6a91 10047 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10048 free (list);
10049 }
10050 break;
10051#endif
252b5132 10052
351f65ca 10053#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10054 case OPTION_X32:
351f65ca
L		 10055 if (IS_ELF)
10056 {
10057 const char **list, **l;
10058
10059 list = bfd_target_list ();
10060 for (l = list; *l != NULL; l++)
10061 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10062 {
10063 default_arch = "x86_64:32";
10064 break;
10065 }
10066 if (*l == NULL)
2b5d6a91 10067 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10068 free (list);
10069 }
10070 else
10071 as_fatal (_("32bit x86_64 is only supported for ELF"));
10072 break;
10073#endif
10074
6e0b89ee
AM		 10075 case OPTION_32:
10076 default_arch = "i386";
10077 break;
10078
b3b91714
AM		 10079 case OPTION_DIVIDE:
10080#ifdef SVR4_COMMENT_CHARS
10081 {
10082 char *n, *t;
10083 const char *s;
10084
add39d23 10085 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10086 t = n;
10087 for (s = i386_comment_chars; *s != '\0'; s++)
10088 if (*s != '/')
10089 *t++ = *s;
10090 *t = '\0';
10091 i386_comment_chars = n;
10092 }
10093#endif
10094 break;
10095
9103f4f4 10096 case OPTION_MARCH:
293f5f65
L		 10097 saved = xstrdup (arg);
10098 arch = saved;
10099 /* Allow -march=+nosse. */
10100 if (*arch == '+')
10101 arch++;
6305a203 10102 do
9103f4f4 10103 {
6305a203 10104 if (*arch == '.')
2b5d6a91 10105 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10106 next = strchr (arch, '+');
10107 if (next)
10108 *next++ = '\0';
91d6fa6a 10109 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10110 {
91d6fa6a 10111 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10112 {
6305a203 10113 /* Processor. */
1ded5609
JB		 10114 if (! cpu_arch[j].flags.bitfield.cpui386)
10115 continue;
10116
91d6fa6a 10117 cpu_arch_name = cpu_arch[j].name;
6305a203 10118 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10119 cpu_arch_flags = cpu_arch[j].flags;
10120 cpu_arch_isa = cpu_arch[j].type;
10121 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10122 if (!cpu_arch_tune_set)
10123 {
10124 cpu_arch_tune = cpu_arch_isa;
10125 cpu_arch_tune_flags = cpu_arch_isa_flags;
10126 }
10127 break;
10128 }
91d6fa6a
NC		 10129 else if (*cpu_arch [j].name == '.'
10130 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10131 {
33eaf5de 10132 /* ISA extension. */
6305a203 10133 i386_cpu_flags flags;
309d3373 10134
293f5f65
L		 10135 flags = cpu_flags_or (cpu_arch_flags,
10136 cpu_arch[j].flags);
81486035 10137
5b64d091 10138 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10139 {
10140 if (cpu_sub_arch_name)
10141 {
10142 char *name = cpu_sub_arch_name;
10143 cpu_sub_arch_name = concat (name,
91d6fa6a 10144 cpu_arch[j].name,
1bf57e9f 10145 (const char *) NULL);
6305a203
L		 10146 free (name);
10147 }
10148 else
91d6fa6a 10149 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10150 cpu_arch_flags = flags;
a586129e 10151 cpu_arch_isa_flags = flags;
6305a203
L		 10152 }
10153 break;
ccc9c027 10154 }
9103f4f4 10155 }
6305a203 10156
293f5f65
L		 10157 if (j >= ARRAY_SIZE (cpu_arch))
10158 {
33eaf5de 10159 /* Disable an ISA extension. */
293f5f65
L		 10160 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10161 if (strcmp (arch, cpu_noarch [j].name) == 0)
10162 {
10163 i386_cpu_flags flags;
10164
10165 flags = cpu_flags_and_not (cpu_arch_flags,
10166 cpu_noarch[j].flags);
10167 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10168 {
10169 if (cpu_sub_arch_name)
10170 {
10171 char *name = cpu_sub_arch_name;
10172 cpu_sub_arch_name = concat (arch,
10173 (const char *) NULL);
10174 free (name);
10175 }
10176 else
10177 cpu_sub_arch_name = xstrdup (arch);
10178 cpu_arch_flags = flags;
10179 cpu_arch_isa_flags = flags;
10180 }
10181 break;
10182 }
10183
10184 if (j >= ARRAY_SIZE (cpu_noarch))
10185 j = ARRAY_SIZE (cpu_arch);
10186 }
10187
91d6fa6a 10188 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10189 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10190
10191 arch = next;
9103f4f4 10192 }
293f5f65
L		 10193 while (next != NULL);
10194 free (saved);
9103f4f4
L		 10195 break;
10196
10197 case OPTION_MTUNE:
10198 if (*arg == '.')
2b5d6a91 10199 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10200 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10201 {
91d6fa6a 10202 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10203 {
ccc9c027 10204 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10205 cpu_arch_tune = cpu_arch [j].type;
10206 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10207 break;
10208 }
10209 }
91d6fa6a 10210 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10211 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10212 break;
10213
1efbbeb4
L		 10214 case OPTION_MMNEMONIC:
10215 if (strcasecmp (arg, "att") == 0)
10216 intel_mnemonic = 0;
10217 else if (strcasecmp (arg, "intel") == 0)
10218 intel_mnemonic = 1;
10219 else
2b5d6a91 10220 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10221 break;
10222
10223 case OPTION_MSYNTAX:
10224 if (strcasecmp (arg, "att") == 0)
10225 intel_syntax = 0;
10226 else if (strcasecmp (arg, "intel") == 0)
10227 intel_syntax = 1;
10228 else
2b5d6a91 10229 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10230 break;
10231
10232 case OPTION_MINDEX_REG:
10233 allow_index_reg = 1;
10234 break;
10235
10236 case OPTION_MNAKED_REG:
10237 allow_naked_reg = 1;
10238 break;
10239
10240 case OPTION_MOLD_GCC:
10241 old_gcc = 1;
1efbbeb4
L		 10242 break;
10243
c0f3af97
L		 10244 case OPTION_MSSE2AVX:
10245 sse2avx = 1;
10246 break;
10247
daf50ae7
L		 10248 case OPTION_MSSE_CHECK:
10249 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10250 sse_check = check_error;
daf50ae7 10251 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10252 sse_check = check_warning;
daf50ae7 10253 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10254 sse_check = check_none;
daf50ae7 10255 else
2b5d6a91 10256 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10257 break;
10258
7bab8ab5
JB		 10259 case OPTION_MOPERAND_CHECK:
10260 if (strcasecmp (arg, "error") == 0)
10261 operand_check = check_error;
10262 else if (strcasecmp (arg, "warning") == 0)
10263 operand_check = check_warning;
10264 else if (strcasecmp (arg, "none") == 0)
10265 operand_check = check_none;
10266 else
10267 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10268 break;
10269
539f890d
L		 10270 case OPTION_MAVXSCALAR:
10271 if (strcasecmp (arg, "128") == 0)
10272 avxscalar = vex128;
10273 else if (strcasecmp (arg, "256") == 0)
10274 avxscalar = vex256;
10275 else
2b5d6a91 10276 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10277 break;
10278
7e8b059b
L		 10279 case OPTION_MADD_BND_PREFIX:
10280 add_bnd_prefix = 1;
10281 break;
10282
43234a1e
L		 10283 case OPTION_MEVEXLIG:
10284 if (strcmp (arg, "128") == 0)
10285 evexlig = evexl128;
10286 else if (strcmp (arg, "256") == 0)
10287 evexlig = evexl256;
10288 else if (strcmp (arg, "512") == 0)
10289 evexlig = evexl512;
10290 else
10291 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10292 break;
10293
d3d3c6db
IT		 10294 case OPTION_MEVEXRCIG:
10295 if (strcmp (arg, "rne") == 0)
10296 evexrcig = rne;
10297 else if (strcmp (arg, "rd") == 0)
10298 evexrcig = rd;
10299 else if (strcmp (arg, "ru") == 0)
10300 evexrcig = ru;
10301 else if (strcmp (arg, "rz") == 0)
10302 evexrcig = rz;
10303 else
10304 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10305 break;
10306
43234a1e
L		 10307 case OPTION_MEVEXWIG:
10308 if (strcmp (arg, "0") == 0)
10309 evexwig = evexw0;
10310 else if (strcmp (arg, "1") == 0)
10311 evexwig = evexw1;
10312 else
10313 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10314 break;
10315
167ad85b
TG		 10316# if defined (TE_PE) || defined (TE_PEP)
10317 case OPTION_MBIG_OBJ:
10318 use_big_obj = 1;
10319 break;
10320#endif
10321
d1982f93 10322 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10323 if (strcasecmp (arg, "yes") == 0)
10324 omit_lock_prefix = 1;
10325 else if (strcasecmp (arg, "no") == 0)
10326 omit_lock_prefix = 0;
10327 else
10328 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10329 break;
10330
e4e00185
AS		 10331 case OPTION_MFENCE_AS_LOCK_ADD:
10332 if (strcasecmp (arg, "yes") == 0)
10333 avoid_fence = 1;
10334 else if (strcasecmp (arg, "no") == 0)
10335 avoid_fence = 0;
10336 else
10337 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10338 break;
10339
0cb4071e
L		 10340 case OPTION_MRELAX_RELOCATIONS:
10341 if (strcasecmp (arg, "yes") == 0)
10342 generate_relax_relocations = 1;
10343 else if (strcasecmp (arg, "no") == 0)
10344 generate_relax_relocations = 0;
10345 else
10346 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10347 break;
10348
5db04b09 10349 case OPTION_MAMD64:
e89c5eaa 10350 intel64 = 0;
5db04b09
L		 10351 break;
10352
10353 case OPTION_MINTEL64:
e89c5eaa 10354 intel64 = 1;
5db04b09
L		 10355 break;
10356
252b5132
RH		 10357 default:
10358 return 0;
10359 }
10360 return 1;
10361}
10362
8a2c8fef
L		 10363#define MESSAGE_TEMPLATE \
10364" "
10365
293f5f65
L		 10366static char *
10367output_message (FILE *stream, char *p, char *message, char *start,
10368 int *left_p, const char *name, int len)
10369{
10370 int size = sizeof (MESSAGE_TEMPLATE);
10371 int left = *left_p;
10372
10373 /* Reserve 2 spaces for ", " or ",\0" */
10374 left -= len + 2;
10375
10376 /* Check if there is any room. */
10377 if (left >= 0)
10378 {
10379 if (p != start)
10380 {
10381 *p++ = ',';
10382 *p++ = ' ';
10383 }
10384 p = mempcpy (p, name, len);
10385 }
10386 else
10387 {
10388 /* Output the current message now and start a new one. */
10389 *p++ = ',';
10390 *p = '\0';
10391 fprintf (stream, "%s\n", message);
10392 p = start;
10393 left = size - (start - message) - len - 2;
10394
10395 gas_assert (left >= 0);
10396
10397 p = mempcpy (p, name, len);
10398 }
10399
10400 *left_p = left;
10401 return p;
10402}
10403
8a2c8fef 10404static void
1ded5609 10405show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10406{
10407 static char message[] = MESSAGE_TEMPLATE;
10408 char *start = message + 27;
10409 char *p;
10410 int size = sizeof (MESSAGE_TEMPLATE);
10411 int left;
10412 const char *name;
10413 int len;
10414 unsigned int j;
10415
10416 p = start;
10417 left = size - (start - message);
10418 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10419 {
10420 /* Should it be skipped? */
10421 if (cpu_arch [j].skip)
10422 continue;
10423
10424 name = cpu_arch [j].name;
10425 len = cpu_arch [j].len;
10426 if (*name == '.')
10427 {
10428 /* It is an extension. Skip if we aren't asked to show it. */
10429 if (ext)
10430 {
10431 name++;
10432 len--;
10433 }
10434 else
10435 continue;
10436 }
10437 else if (ext)
10438 {
10439 /* It is an processor. Skip if we show only extension. */
10440 continue;
10441 }
1ded5609
JB		 10442 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10443 {
10444 /* It is an impossible processor - skip. */
10445 continue;
10446 }
8a2c8fef 10447
293f5f65 10448 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10449 }
10450
293f5f65
L		 10451 /* Display disabled extensions. */
10452 if (ext)
10453 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10454 {
10455 name = cpu_noarch [j].name;
10456 len = cpu_noarch [j].len;
10457 p = output_message (stream, p, message, start, &left, name,
10458 len);
10459 }
10460
8a2c8fef
L		 10461 *p = '\0';
10462 fprintf (stream, "%s\n", message);
10463}
10464
252b5132 10465void
8a2c8fef 10466md_show_usage (FILE *stream)
252b5132 10467{
4cc782b5
ILT		 10468#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10469 fprintf (stream, _("\
a38cf1db
AM		 10470 -Q ignored\n\
10471 -V print assembler version number\n\
b3b91714
AM		 10472 -k ignored\n"));
10473#endif
10474 fprintf (stream, _("\
12b55ccc 10475 -n Do not optimize code alignment\n\
b3b91714
AM		 10476 -q quieten some warnings\n"));
10477#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10478 fprintf (stream, _("\
a38cf1db 10479 -s ignored\n"));
b3b91714 10480#endif
321098a5
L		 10481#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10482 || defined (TE_PE) || defined (TE_PEP))
751d281c 10483 fprintf (stream, _("\
570561f7 10484 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10485#endif
b3b91714
AM		 10486#ifdef SVR4_COMMENT_CHARS
10487 fprintf (stream, _("\
10488 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10489#else
10490 fprintf (stream, _("\
b3b91714 10491 --divide ignored\n"));
4cc782b5 10492#endif
9103f4f4 10493 fprintf (stream, _("\
6305a203 10494 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10495 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10496 show_arch (stream, 0, 1);
8a2c8fef
L		 10497 fprintf (stream, _("\
10498 EXTENSION is combination of:\n"));
1ded5609 10499 show_arch (stream, 1, 0);
6305a203 10500 fprintf (stream, _("\
8a2c8fef 10501 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10502 show_arch (stream, 0, 0);
ba104c83 10503 fprintf (stream, _("\
c0f3af97
L		 10504 -msse2avx encode SSE instructions with VEX prefix\n"));
10505 fprintf (stream, _("\
daf50ae7
L		 10506 -msse-check=[none|error|warning]\n\
10507 check SSE instructions\n"));
10508 fprintf (stream, _("\
7bab8ab5
JB		 10509 -moperand-check=[none|error|warning]\n\
10510 check operand combinations for validity\n"));
10511 fprintf (stream, _("\
539f890d
L		 10512 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10513 length\n"));
10514 fprintf (stream, _("\
43234a1e
L		 10515 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10516 length\n"));
10517 fprintf (stream, _("\
10518 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10519 for EVEX.W bit ignored instructions\n"));
10520 fprintf (stream, _("\
d3d3c6db
IT		 10521 -mevexrcig=[rne|rd|ru|rz]\n\
10522 encode EVEX instructions with specific EVEX.RC value\n\
10523 for SAE-only ignored instructions\n"));
10524 fprintf (stream, _("\
ba104c83
L		 10525 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10526 fprintf (stream, _("\
10527 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10528 fprintf (stream, _("\
10529 -mindex-reg support pseudo index registers\n"));
10530 fprintf (stream, _("\
10531 -mnaked-reg don't require `%%' prefix for registers\n"));
10532 fprintf (stream, _("\
10533 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10534 fprintf (stream, _("\
10535 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10536 fprintf (stream, _("\
10537 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10538# if defined (TE_PE) || defined (TE_PEP)
10539 fprintf (stream, _("\
10540 -mbig-obj generate big object files\n"));
10541#endif
d022bddd
IT		 10542 fprintf (stream, _("\
10543 -momit-lock-prefix=[no|yes]\n\
10544 strip all lock prefixes\n"));
5db04b09 10545 fprintf (stream, _("\
e4e00185
AS		 10546 -mfence-as-lock-add=[no|yes]\n\
10547 encode lfence, mfence and sfence as\n\
10548 lock addl $0x0, (%%{re}sp)\n"));
10549 fprintf (stream, _("\
0cb4071e
L		 10550 -mrelax-relocations=[no|yes]\n\
10551 generate relax relocations\n"));
10552 fprintf (stream, _("\
5db04b09
L		 10553 -mamd64 accept only AMD64 ISA\n"));
10554 fprintf (stream, _("\
10555 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10556}
10557
3e73aa7c 10558#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10559 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10560 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10561
10562/* Pick the target format to use. */
10563
47926f60 10564const char *
e3bb37b5 10565i386_target_format (void)
252b5132 10566{
351f65ca
L		 10567 if (!strncmp (default_arch, "x86_64", 6))
10568 {
10569 update_code_flag (CODE_64BIT, 1);
10570 if (default_arch[6] == '\0')
7f56bc95 10571 x86_elf_abi = X86_64_ABI;
351f65ca 10572 else
7f56bc95 10573 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10574 }
3e73aa7c 10575 else if (!strcmp (default_arch, "i386"))
78f12dd3 10576 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10577 else if (!strcmp (default_arch, "iamcu"))
10578 {
10579 update_code_flag (CODE_32BIT, 1);
10580 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10581 {
10582 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10583 cpu_arch_name = "iamcu";
10584 cpu_sub_arch_name = NULL;
10585 cpu_arch_flags = iamcu_flags;
10586 cpu_arch_isa = PROCESSOR_IAMCU;
10587 cpu_arch_isa_flags = iamcu_flags;
10588 if (!cpu_arch_tune_set)
10589 {
10590 cpu_arch_tune = cpu_arch_isa;
10591 cpu_arch_tune_flags = cpu_arch_isa_flags;
10592 }
10593 }
8d471ec1 10594 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 10595 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10596 cpu_arch_name);
10597 }
3e73aa7c 10598 else
2b5d6a91 10599 as_fatal (_("unknown architecture"));
89507696
JB		 10600
10601 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10602 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10603 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10604 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10605
252b5132
RH		 10606 switch (OUTPUT_FLAVOR)
10607 {
9384f2ff 10608#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10609 case bfd_target_aout_flavour:
47926f60 10610 return AOUT_TARGET_FORMAT;
4c63da97 10611#endif
9384f2ff
AM		 10612#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10613# if defined (TE_PE) || defined (TE_PEP)
10614 case bfd_target_coff_flavour:
167ad85b
TG		 10615 if (flag_code == CODE_64BIT)
10616 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10617 else
10618 return "pe-i386";
9384f2ff 10619# elif defined (TE_GO32)
0561d57c
JK		 10620 case bfd_target_coff_flavour:
10621 return "coff-go32";
9384f2ff 10622# else
252b5132
RH		 10623 case bfd_target_coff_flavour:
10624 return "coff-i386";
9384f2ff 10625# endif
4c63da97 10626#endif
3e73aa7c 10627#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10628 case bfd_target_elf_flavour:
3e73aa7c 10629 {
351f65ca
L		 10630 const char *format;
10631
10632 switch (x86_elf_abi)
4fa24527 10633 {
351f65ca
L		 10634 default:
10635 format = ELF_TARGET_FORMAT;
10636 break;
7f56bc95 10637 case X86_64_ABI:
351f65ca 10638 use_rela_relocations = 1;
4fa24527 10639 object_64bit = 1;
351f65ca
L		 10640 format = ELF_TARGET_FORMAT64;
10641 break;
7f56bc95 10642 case X86_64_X32_ABI:
4fa24527 10643 use_rela_relocations = 1;
351f65ca 10644 object_64bit = 1;
862be3fb 10645 disallow_64bit_reloc = 1;
351f65ca
L		 10646 format = ELF_TARGET_FORMAT32;
10647 break;
4fa24527 10648 }
3632d14b 10649 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10650 {
7f56bc95 10651 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10652 as_fatal (_("Intel L1OM is 64bit only"));
10653 return ELF_TARGET_L1OM_FORMAT;
10654 }
b49f93f6 10655 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10656 {
10657 if (x86_elf_abi != X86_64_ABI)
10658 as_fatal (_("Intel K1OM is 64bit only"));
10659 return ELF_TARGET_K1OM_FORMAT;
10660 }
81486035
L		 10661 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10662 {
10663 if (x86_elf_abi != I386_ABI)
10664 as_fatal (_("Intel MCU is 32bit only"));
10665 return ELF_TARGET_IAMCU_FORMAT;
10666 }
8a9036a4 10667 else
351f65ca 10668 return format;
3e73aa7c 10669 }
e57f8c65
TG		 10670#endif
10671#if defined (OBJ_MACH_O)
10672 case bfd_target_mach_o_flavour:
d382c579
TG		 10673 if (flag_code == CODE_64BIT)
10674 {
10675 use_rela_relocations = 1;
10676 object_64bit = 1;
10677 return "mach-o-x86-64";
10678 }
10679 else
10680 return "mach-o-i386";
4c63da97 10681#endif
252b5132
RH		 10682 default:
10683 abort ();
10684 return NULL;
10685 }
10686}
10687
47926f60 10688#endif /* OBJ_MAYBE_ more than one */
252b5132 10689\f
252b5132 10690symbolS *
7016a5d5 10691md_undefined_symbol (char *name)
252b5132 10692{
18dc2407
ILT		 10693 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10694 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10695 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10696 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10697 {
10698 if (!GOT_symbol)
10699 {
10700 if (symbol_find (name))
10701 as_bad (_("GOT already in symbol table"));
10702 GOT_symbol = symbol_new (name, undefined_section,
10703 (valueT) 0, &zero_address_frag);
10704 };
10705 return GOT_symbol;
10706 }
252b5132
RH		 10707 return 0;
10708}
10709
10710/* Round up a section size to the appropriate boundary. */
47926f60 10711
252b5132 10712valueT
7016a5d5 10713md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10714{
4c63da97
AM		 10715#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10716 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10717 {
10718 /* For a.out, force the section size to be aligned. If we don't do
10719 this, BFD will align it for us, but it will not write out the
10720 final bytes of the section. This may be a bug in BFD, but it is
10721 easier to fix it here since that is how the other a.out targets
10722 work. */
10723 int align;
10724
10725 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10726 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10727 }
252b5132
RH		 10728#endif
10729
10730 return size;
10731}
10732
10733/* On the i386, PC-relative offsets are relative to the start of the
10734 next instruction. That is, the address of the offset, plus its
10735 size, since the offset is always the last part of the insn. */
10736
10737long
e3bb37b5 10738md_pcrel_from (fixS *fixP)
252b5132
RH		 10739{
10740 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10741}
10742
10743#ifndef I386COFF
10744
10745static void
e3bb37b5 10746s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10747{
29b0f896 10748 int temp;
252b5132 10749
8a75718c
JB		 10750#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10751 if (IS_ELF)
10752 obj_elf_section_change_hook ();
10753#endif
252b5132
RH		 10754 temp = get_absolute_expression ();
10755 subseg_set (bss_section, (subsegT) temp);
10756 demand_empty_rest_of_line ();
10757}
10758
10759#endif
10760
252b5132 10761void
e3bb37b5 10762i386_validate_fix (fixS *fixp)
252b5132 10763{
02a86693 10764 if (fixp->fx_subsy)
252b5132 10765 {
02a86693 10766 if (fixp->fx_subsy == GOT_symbol)
23df1078 10767 {
02a86693
L		 10768 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10769 {
10770 if (!object_64bit)
10771 abort ();
10772#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10773 if (fixp->fx_tcbit2)
56ceb5b5
L		 10774 fixp->fx_r_type = (fixp->fx_tcbit
10775 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10776 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10777 else
10778#endif
10779 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10780 }
d6ab8113 10781 else
02a86693
L		 10782 {
10783 if (!object_64bit)
10784 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10785 else
10786 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10787 }
10788 fixp->fx_subsy = 0;
23df1078 10789 }
252b5132 10790 }
02a86693
L		 10791#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10792 else if (!object_64bit)
10793 {
10794 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10795 && fixp->fx_tcbit2)
10796 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10797 }
10798#endif
252b5132
RH		 10799}
10800
252b5132 10801arelent *
7016a5d5 10802tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10803{
10804 arelent *rel;
10805 bfd_reloc_code_real_type code;
10806
10807 switch (fixp->fx_r_type)
10808 {
8ce3d284 10809#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10810 case BFD_RELOC_SIZE32:
10811 case BFD_RELOC_SIZE64:
10812 if (S_IS_DEFINED (fixp->fx_addsy)
10813 && !S_IS_EXTERNAL (fixp->fx_addsy))
10814 {
10815 /* Resolve size relocation against local symbol to size of
10816 the symbol plus addend. */
10817 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10818 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10819 && !fits_in_unsigned_long (value))
10820 as_bad_where (fixp->fx_file, fixp->fx_line,
10821 _("symbol size computation overflow"));
10822 fixp->fx_addsy = NULL;
10823 fixp->fx_subsy = NULL;
10824 md_apply_fix (fixp, (valueT *) &value, NULL);
10825 return NULL;
10826 }
8ce3d284 10827#endif
1a0670f3 10828 /* Fall through. */
8fd4256d 10829
3e73aa7c
JH		 10830 case BFD_RELOC_X86_64_PLT32:
10831 case BFD_RELOC_X86_64_GOT32:
10832 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10833 case BFD_RELOC_X86_64_GOTPCRELX:
10834 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10835 case BFD_RELOC_386_PLT32:
10836 case BFD_RELOC_386_GOT32:
02a86693 10837 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10838 case BFD_RELOC_386_GOTOFF:
10839 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10840 case BFD_RELOC_386_TLS_GD:
10841 case BFD_RELOC_386_TLS_LDM:
10842 case BFD_RELOC_386_TLS_LDO_32:
10843 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10844 case BFD_RELOC_386_TLS_IE:
10845 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10846 case BFD_RELOC_386_TLS_LE_32:
10847 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10848 case BFD_RELOC_386_TLS_GOTDESC:
10849 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10850 case BFD_RELOC_X86_64_TLSGD:
10851 case BFD_RELOC_X86_64_TLSLD:
10852 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10853 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10854 case BFD_RELOC_X86_64_GOTTPOFF:
10855 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10856 case BFD_RELOC_X86_64_TPOFF64:
10857 case BFD_RELOC_X86_64_GOTOFF64:
10858 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10859 case BFD_RELOC_X86_64_GOT64:
10860 case BFD_RELOC_X86_64_GOTPCREL64:
10861 case BFD_RELOC_X86_64_GOTPC64:
10862 case BFD_RELOC_X86_64_GOTPLT64:
10863 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10864 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10865 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10866 case BFD_RELOC_RVA:
10867 case BFD_RELOC_VTABLE_ENTRY:
10868 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10869#ifdef TE_PE
10870 case BFD_RELOC_32_SECREL:
10871#endif
252b5132
RH		 10872 code = fixp->fx_r_type;
10873 break;
dbbaec26
L		 10874 case BFD_RELOC_X86_64_32S:
10875 if (!fixp->fx_pcrel)
10876 {
10877 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10878 code = fixp->fx_r_type;
10879 break;
10880 }
1a0670f3 10881 /* Fall through. */
252b5132 10882 default:
93382f6d 10883 if (fixp->fx_pcrel)
252b5132 10884 {
93382f6d
AM		 10885 switch (fixp->fx_size)
10886 {
10887 default:
b091f402
AM		 10888 as_bad_where (fixp->fx_file, fixp->fx_line,
10889 _("can not do %d byte pc-relative relocation"),
10890 fixp->fx_size);
93382f6d
AM		 10891 code = BFD_RELOC_32_PCREL;
10892 break;
10893 case 1: code = BFD_RELOC_8_PCREL; break;
10894 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10895 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10896#ifdef BFD64
10897 case 8: code = BFD_RELOC_64_PCREL; break;
10898#endif
93382f6d
AM		 10899 }
10900 }
10901 else
10902 {
10903 switch (fixp->fx_size)
10904 {
10905 default:
b091f402
AM		 10906 as_bad_where (fixp->fx_file, fixp->fx_line,
10907 _("can not do %d byte relocation"),
10908 fixp->fx_size);
93382f6d
AM		 10909 code = BFD_RELOC_32;
10910 break;
10911 case 1: code = BFD_RELOC_8; break;
10912 case 2: code = BFD_RELOC_16; break;
10913 case 4: code = BFD_RELOC_32; break;
937149dd 10914#ifdef BFD64
3e73aa7c 10915 case 8: code = BFD_RELOC_64; break;
937149dd 10916#endif
93382f6d 10917 }
252b5132
RH		 10918 }
10919 break;
10920 }
252b5132 10921
d182319b
JB		 10922 if ((code == BFD_RELOC_32
10923 || code == BFD_RELOC_32_PCREL
10924 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10925 && GOT_symbol
10926 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10927 {
4fa24527 10928 if (!object_64bit)
d6ab8113
JB		 10929 code = BFD_RELOC_386_GOTPC;
10930 else
10931 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10932 }
7b81dfbb
AJ		 10933 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10934 && GOT_symbol
10935 && fixp->fx_addsy == GOT_symbol)
10936 {
10937 code = BFD_RELOC_X86_64_GOTPC64;
10938 }
252b5132 10939
add39d23
TS		 10940 rel = XNEW (arelent);
10941 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10942 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10943
10944 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10945
3e73aa7c
JH		 10946 if (!use_rela_relocations)
10947 {
10948 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10949 vtable entry to be used in the relocation's section offset. */
10950 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10951 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10952#if defined (OBJ_COFF) && defined (TE_PE)
10953 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10954 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10955 else
10956#endif
c6682705 10957 rel->addend = 0;
3e73aa7c
JH		 10958 }
10959 /* Use the rela in 64bit mode. */
252b5132 10960 else
3e73aa7c 10961 {
862be3fb
L		 10962 if (disallow_64bit_reloc)
10963 switch (code)
10964 {
862be3fb
L		 10965 case BFD_RELOC_X86_64_DTPOFF64:
10966 case BFD_RELOC_X86_64_TPOFF64:
10967 case BFD_RELOC_64_PCREL:
10968 case BFD_RELOC_X86_64_GOTOFF64:
10969 case BFD_RELOC_X86_64_GOT64:
10970 case BFD_RELOC_X86_64_GOTPCREL64:
10971 case BFD_RELOC_X86_64_GOTPC64:
10972 case BFD_RELOC_X86_64_GOTPLT64:
10973 case BFD_RELOC_X86_64_PLTOFF64:
10974 as_bad_where (fixp->fx_file, fixp->fx_line,
10975 _("cannot represent relocation type %s in x32 mode"),
10976 bfd_get_reloc_code_name (code));
10977 break;
10978 default:
10979 break;
10980 }
10981
062cd5e7
AS		 10982 if (!fixp->fx_pcrel)
10983 rel->addend = fixp->fx_offset;
10984 else
10985 switch (code)
10986 {
10987 case BFD_RELOC_X86_64_PLT32:
10988 case BFD_RELOC_X86_64_GOT32:
10989 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10990 case BFD_RELOC_X86_64_GOTPCRELX:
10991 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 10992 case BFD_RELOC_X86_64_TLSGD:
10993 case BFD_RELOC_X86_64_TLSLD:
10994 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10995 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10996 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10997 rel->addend = fixp->fx_offset - fixp->fx_size;
10998 break;
10999 default:
11000 rel->addend = (section->vma
11001 - fixp->fx_size
11002 + fixp->fx_addnumber
11003 + md_pcrel_from (fixp));
11004 break;
11005 }
3e73aa7c
JH		 11006 }
11007
252b5132
RH		 11008 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11009 if (rel->howto == NULL)
11010 {
11011 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11012 _("cannot represent relocation type %s"),
252b5132
RH		 11013 bfd_get_reloc_code_name (code));
11014 /* Set howto to a garbage value so that we can keep going. */
11015 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11016 gas_assert (rel->howto != NULL);
252b5132
RH		 11017 }
11018
11019 return rel;
11020}
11021
ee86248c 11022#include "tc-i386-intel.c"
54cfded0 11023
a60de03c
JB		 11024void
11025tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11026{
a60de03c
JB		 11027 int saved_naked_reg;
11028 char saved_register_dot;
54cfded0 11029
a60de03c
JB		 11030 saved_naked_reg = allow_naked_reg;
11031 allow_naked_reg = 1;
11032 saved_register_dot = register_chars['.'];
11033 register_chars['.'] = '.';
11034 allow_pseudo_reg = 1;
11035 expression_and_evaluate (exp);
11036 allow_pseudo_reg = 0;
11037 register_chars['.'] = saved_register_dot;
11038 allow_naked_reg = saved_naked_reg;
11039
e96d56a1 11040 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11041 {
a60de03c
JB		 11042 if ((addressT) exp->X_add_number < i386_regtab_size)
11043 {
11044 exp->X_op = O_constant;
11045 exp->X_add_number = i386_regtab[exp->X_add_number]
11046 .dw2_regnum[flag_code >> 1];
11047 }
11048 else
11049 exp->X_op = O_illegal;
54cfded0 11050 }
54cfded0
AM		 11051}
11052
11053void
11054tc_x86_frame_initial_instructions (void)
11055{
a60de03c
JB		 11056 static unsigned int sp_regno[2];
11057
11058 if (!sp_regno[flag_code >> 1])
11059 {
11060 char *saved_input = input_line_pointer;
11061 char sp[][4] = {"esp", "rsp"};
11062 expressionS exp;
a4447b93 11063
a60de03c
JB		 11064 input_line_pointer = sp[flag_code >> 1];
11065 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11066 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11067 sp_regno[flag_code >> 1] = exp.X_add_number;
11068 input_line_pointer = saved_input;
11069 }
a4447b93 11070
61ff971f
L		 11071 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11072 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11073}
d2b2c203 11074
d7921315
L		 11075int
11076x86_dwarf2_addr_size (void)
11077{
11078#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11079 if (x86_elf_abi == X86_64_X32_ABI)
11080 return 4;
11081#endif
11082 return bfd_arch_bits_per_address (stdoutput) / 8;
11083}
11084
d2b2c203
DJ		 11085int
11086i386_elf_section_type (const char *str, size_t len)
11087{
11088 if (flag_code == CODE_64BIT
11089 && len == sizeof ("unwind") - 1
11090 && strncmp (str, "unwind", 6) == 0)
11091 return SHT_X86_64_UNWIND;
11092
11093 return -1;
11094}
bb41ade5 11095
ad5fec3b
EB		 11096#ifdef TE_SOLARIS
11097void
11098i386_solaris_fix_up_eh_frame (segT sec)
11099{
11100 if (flag_code == CODE_64BIT)
11101 elf_section_type (sec) = SHT_X86_64_UNWIND;
11102}
11103#endif
11104
bb41ade5
AM		 11105#ifdef TE_PE
11106void
11107tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11108{
91d6fa6a 11109 expressionS exp;
bb41ade5 11110
91d6fa6a
NC		 11111 exp.X_op = O_secrel;
11112 exp.X_add_symbol = symbol;
11113 exp.X_add_number = 0;
11114 emit_expr (&exp, size);
bb41ade5
AM		 11115}
11116#endif
3b22753a
L		 11117
11118#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11119/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11120
01e1a5bc 11121bfd_vma
6d4af3c2 11122x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11123{
11124 if (flag_code == CODE_64BIT)
11125 {
11126 if (letter == 'l')
11127 return SHF_X86_64_LARGE;
11128
8f3bae45 11129 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11130 }
3b22753a 11131 else
8f3bae45 11132 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11133 return -1;
11134}
11135
01e1a5bc 11136bfd_vma
3b22753a
L		 11137x86_64_section_word (char *str, size_t len)
11138{
8620418b 11139 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11140 return SHF_X86_64_LARGE;
11141
11142 return -1;
11143}
11144
11145static void
11146handle_large_common (int small ATTRIBUTE_UNUSED)
11147{
11148 if (flag_code != CODE_64BIT)
11149 {
11150 s_comm_internal (0, elf_common_parse);
11151 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11152 }
11153 else
11154 {
11155 static segT lbss_section;
11156 asection *saved_com_section_ptr = elf_com_section_ptr;
11157 asection *saved_bss_section = bss_section;
11158
11159 if (lbss_section == NULL)
11160 {
11161 flagword applicable;
11162 segT seg = now_seg;
11163 subsegT subseg = now_subseg;
11164
11165 /* The .lbss section is for local .largecomm symbols. */
11166 lbss_section = subseg_new (".lbss", 0);
11167 applicable = bfd_applicable_section_flags (stdoutput);
11168 bfd_set_section_flags (stdoutput, lbss_section,
11169 applicable & SEC_ALLOC);
11170 seg_info (lbss_section)->bss = 1;
11171
11172 subseg_set (seg, subseg);
11173 }
11174
11175 elf_com_section_ptr = &_bfd_elf_large_com_section;
11176 bss_section = lbss_section;
11177
11178 s_comm_internal (0, elf_common_parse);
11179
11180 elf_com_section_ptr = saved_com_section_ptr;
11181 bss_section = saved_bss_section;
11182 }
11183}
11184#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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