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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
b3adc24a | 2 | Copyright (C) 1989-2020 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
41fd2579 L |
36 | #ifdef HAVE_LIMITS_H |
37 | #include <limits.h> | |
38 | #else | |
39 | #ifdef HAVE_SYS_PARAM_H | |
40 | #include <sys/param.h> | |
41 | #endif | |
42 | #ifndef INT_MAX | |
43 | #define INT_MAX (int) (((unsigned) (-1)) >> 1) | |
44 | #endif | |
45 | #endif | |
46 | ||
c3332e24 | 47 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 48 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
49 | #endif |
50 | ||
29b0f896 AM |
51 | #ifndef DEFAULT_ARCH |
52 | #define DEFAULT_ARCH "i386" | |
246fcdee | 53 | #endif |
252b5132 | 54 | |
edde18a5 AM |
55 | #ifndef INLINE |
56 | #if __GNUC__ >= 2 | |
57 | #define INLINE __inline__ | |
58 | #else | |
59 | #define INLINE | |
60 | #endif | |
61 | #endif | |
62 | ||
6305a203 L |
63 | /* Prefixes will be emitted in the order defined below. |
64 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
65 | instruction, and so must come before any prefixes. | |
66 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 67 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
68 | #define WAIT_PREFIX 0 |
69 | #define SEG_PREFIX 1 | |
70 | #define ADDR_PREFIX 2 | |
71 | #define DATA_PREFIX 3 | |
c32fa91d | 72 | #define REP_PREFIX 4 |
42164a71 | 73 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 74 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 75 | #define LOCK_PREFIX 5 |
4e9ac44a L |
76 | #define REX_PREFIX 6 /* must come last. */ |
77 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
78 | |
79 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
80 | #define REGISTER_PREFIX '%' | |
81 | #define IMMEDIATE_PREFIX '$' | |
82 | #define ABSOLUTE_PREFIX '*' | |
83 | ||
84 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
85 | memory operand size in Intel syntax. */ | |
86 | #define WORD_MNEM_SUFFIX 'w' | |
87 | #define BYTE_MNEM_SUFFIX 'b' | |
88 | #define SHORT_MNEM_SUFFIX 's' | |
89 | #define LONG_MNEM_SUFFIX 'l' | |
90 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
91 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
92 | in instructions. */ | |
93 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
94 | ||
95 | #define END_OF_INSN '\0' | |
96 | ||
79dec6b7 JB |
97 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
98 | #define commutative staticrounding | |
99 | ||
6305a203 L |
100 | /* |
101 | 'templates' is for grouping together 'template' structures for opcodes | |
102 | of the same name. This is only used for storing the insns in the grand | |
103 | ole hash table of insns. | |
104 | The templates themselves start at START and range up to (but not including) | |
105 | END. | |
106 | */ | |
107 | typedef struct | |
108 | { | |
d3ce72d0 NC |
109 | const insn_template *start; |
110 | const insn_template *end; | |
6305a203 L |
111 | } |
112 | templates; | |
113 | ||
114 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
115 | typedef struct | |
116 | { | |
117 | unsigned int regmem; /* codes register or memory operand */ | |
118 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
119 | unsigned int mode; /* how to interpret regmem & reg */ | |
120 | } | |
121 | modrm_byte; | |
122 | ||
123 | /* x86-64 extension prefix. */ | |
124 | typedef int rex_byte; | |
125 | ||
6305a203 L |
126 | /* 386 opcode byte to code indirect addressing. */ |
127 | typedef struct | |
128 | { | |
129 | unsigned base; | |
130 | unsigned index; | |
131 | unsigned scale; | |
132 | } | |
133 | sib_byte; | |
134 | ||
6305a203 L |
135 | /* x86 arch names, types and features */ |
136 | typedef struct | |
137 | { | |
138 | const char *name; /* arch name */ | |
8a2c8fef | 139 | unsigned int len; /* arch string length */ |
6305a203 L |
140 | enum processor_type type; /* arch type */ |
141 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 142 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
143 | } |
144 | arch_entry; | |
145 | ||
293f5f65 L |
146 | /* Used to turn off indicated flags. */ |
147 | typedef struct | |
148 | { | |
149 | const char *name; /* arch name */ | |
150 | unsigned int len; /* arch string length */ | |
151 | i386_cpu_flags flags; /* cpu feature flags */ | |
152 | } | |
153 | noarch_entry; | |
154 | ||
78f12dd3 | 155 | static void update_code_flag (int, int); |
e3bb37b5 L |
156 | static void set_code_flag (int); |
157 | static void set_16bit_gcc_code_flag (int); | |
158 | static void set_intel_syntax (int); | |
1efbbeb4 | 159 | static void set_intel_mnemonic (int); |
db51cc60 | 160 | static void set_allow_index_reg (int); |
7bab8ab5 | 161 | static void set_check (int); |
e3bb37b5 | 162 | static void set_cpu_arch (int); |
6482c264 | 163 | #ifdef TE_PE |
e3bb37b5 | 164 | static void pe_directive_secrel (int); |
6482c264 | 165 | #endif |
e3bb37b5 L |
166 | static void signed_cons (int); |
167 | static char *output_invalid (int c); | |
ee86248c JB |
168 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
169 | const char *); | |
170 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
171 | const char *); | |
a7619375 | 172 | static int i386_att_operand (char *); |
e3bb37b5 | 173 | static int i386_intel_operand (char *, int); |
ee86248c JB |
174 | static int i386_intel_simplify (expressionS *); |
175 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
176 | static const reg_entry *parse_register (char *, char **); |
177 | static char *parse_insn (char *, char *); | |
178 | static char *parse_operands (char *, const char *); | |
179 | static void swap_operands (void); | |
4d456e3d | 180 | static void swap_2_operands (int, int); |
48bcea9f | 181 | static enum flag_code i386_addressing_mode (void); |
e3bb37b5 L |
182 | static void optimize_imm (void); |
183 | static void optimize_disp (void); | |
83b16ac6 | 184 | static const insn_template *match_template (char); |
e3bb37b5 L |
185 | static int check_string (void); |
186 | static int process_suffix (void); | |
187 | static int check_byte_reg (void); | |
188 | static int check_long_reg (void); | |
189 | static int check_qword_reg (void); | |
190 | static int check_word_reg (void); | |
191 | static int finalize_imm (void); | |
192 | static int process_operands (void); | |
193 | static const seg_entry *build_modrm_byte (void); | |
194 | static void output_insn (void); | |
195 | static void output_imm (fragS *, offsetT); | |
196 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 197 | #ifndef I386COFF |
e3bb37b5 | 198 | static void s_bss (int); |
252b5132 | 199 | #endif |
17d4e2a2 L |
200 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
201 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
202 | |
203 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
204 | static unsigned int x86_isa_1_used; | |
205 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
206 | static unsigned int x86_feature_2_used; | |
207 | /* Generate x86 used ISA and feature properties. */ | |
208 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 209 | #endif |
252b5132 | 210 | |
a847613f | 211 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 212 | |
43234a1e L |
213 | /* This struct describes rounding control and SAE in the instruction. */ |
214 | struct RC_Operation | |
215 | { | |
216 | enum rc_type | |
217 | { | |
218 | rne = 0, | |
219 | rd, | |
220 | ru, | |
221 | rz, | |
222 | saeonly | |
223 | } type; | |
224 | int operand; | |
225 | }; | |
226 | ||
227 | static struct RC_Operation rc_op; | |
228 | ||
229 | /* The struct describes masking, applied to OPERAND in the instruction. | |
230 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
231 | whether merging or zeroing mask is used. */ | |
232 | struct Mask_Operation | |
233 | { | |
234 | const reg_entry *mask; | |
235 | unsigned int zeroing; | |
236 | /* The operand where this operation is associated. */ | |
237 | int operand; | |
238 | }; | |
239 | ||
240 | static struct Mask_Operation mask_op; | |
241 | ||
242 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
243 | broadcast factor. */ | |
244 | struct Broadcast_Operation | |
245 | { | |
8e6e0792 | 246 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ |
43234a1e L |
247 | int type; |
248 | ||
249 | /* Index of broadcasted operand. */ | |
250 | int operand; | |
4a1b91ea L |
251 | |
252 | /* Number of bytes to broadcast. */ | |
253 | int bytes; | |
43234a1e L |
254 | }; |
255 | ||
256 | static struct Broadcast_Operation broadcast_op; | |
257 | ||
c0f3af97 L |
258 | /* VEX prefix. */ |
259 | typedef struct | |
260 | { | |
43234a1e L |
261 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
262 | unsigned char bytes[4]; | |
c0f3af97 L |
263 | unsigned int length; |
264 | /* Destination or source register specifier. */ | |
265 | const reg_entry *register_specifier; | |
266 | } vex_prefix; | |
267 | ||
252b5132 | 268 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 269 | i386_insn. */ |
252b5132 | 270 | |
520dc8e8 AM |
271 | union i386_op |
272 | { | |
273 | expressionS *disps; | |
274 | expressionS *imms; | |
275 | const reg_entry *regs; | |
276 | }; | |
277 | ||
a65babc9 L |
278 | enum i386_error |
279 | { | |
86e026a4 | 280 | operand_size_mismatch, |
a65babc9 L |
281 | operand_type_mismatch, |
282 | register_type_mismatch, | |
283 | number_of_operands_mismatch, | |
284 | invalid_instruction_suffix, | |
285 | bad_imm4, | |
a65babc9 L |
286 | unsupported_with_intel_mnemonic, |
287 | unsupported_syntax, | |
6c30d220 L |
288 | unsupported, |
289 | invalid_vsib_address, | |
7bab8ab5 | 290 | invalid_vector_register_set, |
43234a1e L |
291 | unsupported_vector_index_register, |
292 | unsupported_broadcast, | |
43234a1e L |
293 | broadcast_needed, |
294 | unsupported_masking, | |
295 | mask_not_on_destination, | |
296 | no_default_mask, | |
297 | unsupported_rc_sae, | |
298 | rc_sae_operand_not_last_imm, | |
299 | invalid_register_operand, | |
a65babc9 L |
300 | }; |
301 | ||
252b5132 RH |
302 | struct _i386_insn |
303 | { | |
47926f60 | 304 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 305 | insn_template tm; |
252b5132 | 306 | |
7d5e4556 L |
307 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
308 | or qword, if given. */ | |
252b5132 RH |
309 | char suffix; |
310 | ||
47926f60 | 311 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
312 | unsigned int operands; |
313 | ||
314 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
315 | of given register, displacement, memory operands and immediate | |
47926f60 | 316 | operands. */ |
252b5132 RH |
317 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
318 | ||
319 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 320 | use OP[i] for the corresponding operand. */ |
40fb9820 | 321 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 322 | |
520dc8e8 AM |
323 | /* Displacement expression, immediate expression, or register for each |
324 | operand. */ | |
325 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 326 | |
3e73aa7c JH |
327 | /* Flags for operands. */ |
328 | unsigned int flags[MAX_OPERANDS]; | |
329 | #define Operand_PCrel 1 | |
c48dadc9 | 330 | #define Operand_Mem 2 |
3e73aa7c | 331 | |
252b5132 | 332 | /* Relocation type for operand */ |
f86103b7 | 333 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 334 | |
252b5132 RH |
335 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
336 | the base index byte below. */ | |
337 | const reg_entry *base_reg; | |
338 | const reg_entry *index_reg; | |
339 | unsigned int log2_scale_factor; | |
340 | ||
341 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 342 | explicit segment overrides are given. */ |
ce8a8b2f | 343 | const seg_entry *seg[2]; |
252b5132 | 344 | |
8325cc63 JB |
345 | /* Copied first memory operand string, for re-checking. */ |
346 | char *memop1_string; | |
347 | ||
252b5132 RH |
348 | /* PREFIX holds all the given prefix opcodes (usually null). |
349 | PREFIXES is the number of prefix opcodes. */ | |
350 | unsigned int prefixes; | |
351 | unsigned char prefix[MAX_PREFIXES]; | |
352 | ||
50128d0c JB |
353 | /* Register is in low 3 bits of opcode. */ |
354 | bfd_boolean short_form; | |
355 | ||
6f2f06be JB |
356 | /* The operand to a branch insn indicates an absolute branch. */ |
357 | bfd_boolean jumpabsolute; | |
358 | ||
b4a3a7b4 L |
359 | /* Has MMX register operands. */ |
360 | bfd_boolean has_regmmx; | |
361 | ||
362 | /* Has XMM register operands. */ | |
363 | bfd_boolean has_regxmm; | |
364 | ||
365 | /* Has YMM register operands. */ | |
366 | bfd_boolean has_regymm; | |
367 | ||
368 | /* Has ZMM register operands. */ | |
369 | bfd_boolean has_regzmm; | |
370 | ||
e379e5f3 L |
371 | /* Has GOTPC or TLS relocation. */ |
372 | bfd_boolean has_gotpc_tls_reloc; | |
373 | ||
252b5132 | 374 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 375 | addressing modes of this insn are encoded. */ |
252b5132 | 376 | modrm_byte rm; |
3e73aa7c | 377 | rex_byte rex; |
43234a1e | 378 | rex_byte vrex; |
252b5132 | 379 | sib_byte sib; |
c0f3af97 | 380 | vex_prefix vex; |
b6169b20 | 381 | |
43234a1e L |
382 | /* Masking attributes. */ |
383 | struct Mask_Operation *mask; | |
384 | ||
385 | /* Rounding control and SAE attributes. */ | |
386 | struct RC_Operation *rounding; | |
387 | ||
388 | /* Broadcasting attributes. */ | |
389 | struct Broadcast_Operation *broadcast; | |
390 | ||
391 | /* Compressed disp8*N attribute. */ | |
392 | unsigned int memshift; | |
393 | ||
86fa6981 L |
394 | /* Prefer load or store in encoding. */ |
395 | enum | |
396 | { | |
397 | dir_encoding_default = 0, | |
398 | dir_encoding_load, | |
64c49ab3 JB |
399 | dir_encoding_store, |
400 | dir_encoding_swap | |
86fa6981 | 401 | } dir_encoding; |
891edac4 | 402 | |
a501d77e L |
403 | /* Prefer 8bit or 32bit displacement in encoding. */ |
404 | enum | |
405 | { | |
406 | disp_encoding_default = 0, | |
407 | disp_encoding_8bit, | |
408 | disp_encoding_32bit | |
409 | } disp_encoding; | |
f8a5c266 | 410 | |
6b6b6807 L |
411 | /* Prefer the REX byte in encoding. */ |
412 | bfd_boolean rex_encoding; | |
413 | ||
b6f8c7c4 L |
414 | /* Disable instruction size optimization. */ |
415 | bfd_boolean no_optimize; | |
416 | ||
86fa6981 L |
417 | /* How to encode vector instructions. */ |
418 | enum | |
419 | { | |
420 | vex_encoding_default = 0, | |
42e04b36 | 421 | vex_encoding_vex, |
86fa6981 L |
422 | vex_encoding_vex3, |
423 | vex_encoding_evex | |
424 | } vec_encoding; | |
425 | ||
d5de92cf L |
426 | /* REP prefix. */ |
427 | const char *rep_prefix; | |
428 | ||
165de32a L |
429 | /* HLE prefix. */ |
430 | const char *hle_prefix; | |
42164a71 | 431 | |
7e8b059b L |
432 | /* Have BND prefix. */ |
433 | const char *bnd_prefix; | |
434 | ||
04ef582a L |
435 | /* Have NOTRACK prefix. */ |
436 | const char *notrack_prefix; | |
437 | ||
891edac4 | 438 | /* Error message. */ |
a65babc9 | 439 | enum i386_error error; |
252b5132 RH |
440 | }; |
441 | ||
442 | typedef struct _i386_insn i386_insn; | |
443 | ||
43234a1e L |
444 | /* Link RC type with corresponding string, that'll be looked for in |
445 | asm. */ | |
446 | struct RC_name | |
447 | { | |
448 | enum rc_type type; | |
449 | const char *name; | |
450 | unsigned int len; | |
451 | }; | |
452 | ||
453 | static const struct RC_name RC_NamesTable[] = | |
454 | { | |
455 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
456 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
457 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
458 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
459 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
460 | }; | |
461 | ||
252b5132 RH |
462 | /* List of chars besides those in app.c:symbol_chars that can start an |
463 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 464 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 465 | #ifdef LEX_AT |
32137342 NC |
466 | "@" |
467 | #endif | |
468 | #ifdef LEX_QM | |
469 | "?" | |
252b5132 | 470 | #endif |
32137342 | 471 | ; |
252b5132 | 472 | |
29b0f896 AM |
473 | #if (defined (TE_I386AIX) \ |
474 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 475 | && !defined (TE_GNU) \ |
29b0f896 | 476 | && !defined (TE_LINUX) \ |
8d63c93e | 477 | && !defined (TE_NACL) \ |
29b0f896 | 478 | && !defined (TE_FreeBSD) \ |
5b806d27 | 479 | && !defined (TE_DragonFly) \ |
29b0f896 | 480 | && !defined (TE_NetBSD))) |
252b5132 | 481 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
482 | pre-processor is disabled, these aren't very useful. The option |
483 | --divide will remove '/' from this list. */ | |
484 | const char *i386_comment_chars = "#/"; | |
485 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 486 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 487 | |
b3b91714 AM |
488 | #else |
489 | const char *i386_comment_chars = "#"; | |
490 | #define PREFIX_SEPARATOR '/' | |
491 | #endif | |
492 | ||
252b5132 RH |
493 | /* This array holds the chars that only start a comment at the beginning of |
494 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
495 | .line and .file directives will appear in the pre-processed output. |
496 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 497 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
498 | #NO_APP at the beginning of its output. |
499 | Also note that comments started like this one will always work if | |
252b5132 | 500 | '/' isn't otherwise defined. */ |
b3b91714 | 501 | const char line_comment_chars[] = "#/"; |
252b5132 | 502 | |
63a0b638 | 503 | const char line_separator_chars[] = ";"; |
252b5132 | 504 | |
ce8a8b2f AM |
505 | /* Chars that can be used to separate mant from exp in floating point |
506 | nums. */ | |
252b5132 RH |
507 | const char EXP_CHARS[] = "eE"; |
508 | ||
ce8a8b2f AM |
509 | /* Chars that mean this number is a floating point constant |
510 | As in 0f12.456 | |
511 | or 0d1.2345e12. */ | |
252b5132 RH |
512 | const char FLT_CHARS[] = "fFdDxX"; |
513 | ||
ce8a8b2f | 514 | /* Tables for lexical analysis. */ |
252b5132 RH |
515 | static char mnemonic_chars[256]; |
516 | static char register_chars[256]; | |
517 | static char operand_chars[256]; | |
518 | static char identifier_chars[256]; | |
519 | static char digit_chars[256]; | |
520 | ||
ce8a8b2f | 521 | /* Lexical macros. */ |
252b5132 RH |
522 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
523 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
524 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
525 | #define is_space_char(x) ((x) == ' ') | |
526 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
527 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
528 | ||
0234cb7c | 529 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
530 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
531 | ||
532 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
533 | effect this we maintain a stack of saved characters that we've smashed | |
534 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 535 | assembler instruction). */ |
252b5132 | 536 | static char save_stack[32]; |
ce8a8b2f | 537 | static char *save_stack_p; |
252b5132 RH |
538 | #define END_STRING_AND_SAVE(s) \ |
539 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
540 | #define RESTORE_END_STRING(s) \ | |
541 | do { *(s) = *--save_stack_p; } while (0) | |
542 | ||
47926f60 | 543 | /* The instruction we're assembling. */ |
252b5132 RH |
544 | static i386_insn i; |
545 | ||
546 | /* Possible templates for current insn. */ | |
547 | static const templates *current_templates; | |
548 | ||
31b2323c L |
549 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
550 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
551 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 552 | |
47926f60 | 553 | /* Current operand we are working on. */ |
ee86248c | 554 | static int this_operand = -1; |
252b5132 | 555 | |
3e73aa7c JH |
556 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
557 | these. */ | |
558 | ||
559 | enum flag_code { | |
560 | CODE_32BIT, | |
561 | CODE_16BIT, | |
562 | CODE_64BIT }; | |
563 | ||
564 | static enum flag_code flag_code; | |
4fa24527 | 565 | static unsigned int object_64bit; |
862be3fb | 566 | static unsigned int disallow_64bit_reloc; |
3e73aa7c | 567 | static int use_rela_relocations = 0; |
e379e5f3 L |
568 | /* __tls_get_addr/___tls_get_addr symbol for TLS. */ |
569 | static const char *tls_get_addr; | |
3e73aa7c | 570 | |
7af8ed2d NC |
571 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
572 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
573 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
574 | ||
351f65ca L |
575 | /* The ELF ABI to use. */ |
576 | enum x86_elf_abi | |
577 | { | |
578 | I386_ABI, | |
7f56bc95 L |
579 | X86_64_ABI, |
580 | X86_64_X32_ABI | |
351f65ca L |
581 | }; |
582 | ||
583 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 584 | #endif |
351f65ca | 585 | |
167ad85b TG |
586 | #if defined (TE_PE) || defined (TE_PEP) |
587 | /* Use big object file format. */ | |
588 | static int use_big_obj = 0; | |
589 | #endif | |
590 | ||
8dcea932 L |
591 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
592 | /* 1 if generating code for a shared library. */ | |
593 | static int shared = 0; | |
594 | #endif | |
595 | ||
47926f60 KH |
596 | /* 1 for intel syntax, |
597 | 0 if att syntax. */ | |
598 | static int intel_syntax = 0; | |
252b5132 | 599 | |
4b5aaf5f L |
600 | static enum x86_64_isa |
601 | { | |
602 | amd64 = 1, /* AMD64 ISA. */ | |
603 | intel64 /* Intel64 ISA. */ | |
604 | } isa64; | |
e89c5eaa | 605 | |
1efbbeb4 L |
606 | /* 1 for intel mnemonic, |
607 | 0 if att mnemonic. */ | |
608 | static int intel_mnemonic = !SYSV386_COMPAT; | |
609 | ||
a60de03c JB |
610 | /* 1 if pseudo registers are permitted. */ |
611 | static int allow_pseudo_reg = 0; | |
612 | ||
47926f60 KH |
613 | /* 1 if register prefix % not required. */ |
614 | static int allow_naked_reg = 0; | |
252b5132 | 615 | |
33eaf5de | 616 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
617 | instructions supporting it, even if this prefix wasn't specified |
618 | explicitly. */ | |
619 | static int add_bnd_prefix = 0; | |
620 | ||
ba104c83 | 621 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
622 | static int allow_index_reg = 0; |
623 | ||
d022bddd IT |
624 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
625 | specified explicitly. */ | |
626 | static int omit_lock_prefix = 0; | |
627 | ||
e4e00185 AS |
628 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
629 | "lock addl $0, (%{re}sp)". */ | |
630 | static int avoid_fence = 0; | |
631 | ||
e379e5f3 L |
632 | /* Type of the previous instruction. */ |
633 | static struct | |
634 | { | |
635 | segT seg; | |
636 | const char *file; | |
637 | const char *name; | |
638 | unsigned int line; | |
639 | enum last_insn_kind | |
640 | { | |
641 | last_insn_other = 0, | |
642 | last_insn_directive, | |
643 | last_insn_prefix | |
644 | } kind; | |
645 | } last_insn; | |
646 | ||
0cb4071e L |
647 | /* 1 if the assembler should generate relax relocations. */ |
648 | ||
649 | static int generate_relax_relocations | |
650 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
651 | ||
7bab8ab5 | 652 | static enum check_kind |
daf50ae7 | 653 | { |
7bab8ab5 JB |
654 | check_none = 0, |
655 | check_warning, | |
656 | check_error | |
daf50ae7 | 657 | } |
7bab8ab5 | 658 | sse_check, operand_check = check_warning; |
daf50ae7 | 659 | |
e379e5f3 L |
660 | /* Non-zero if branches should be aligned within power of 2 boundary. */ |
661 | static int align_branch_power = 0; | |
662 | ||
663 | /* Types of branches to align. */ | |
664 | enum align_branch_kind | |
665 | { | |
666 | align_branch_none = 0, | |
667 | align_branch_jcc = 1, | |
668 | align_branch_fused = 2, | |
669 | align_branch_jmp = 3, | |
670 | align_branch_call = 4, | |
671 | align_branch_indirect = 5, | |
672 | align_branch_ret = 6 | |
673 | }; | |
674 | ||
675 | /* Type bits of branches to align. */ | |
676 | enum align_branch_bit | |
677 | { | |
678 | align_branch_jcc_bit = 1 << align_branch_jcc, | |
679 | align_branch_fused_bit = 1 << align_branch_fused, | |
680 | align_branch_jmp_bit = 1 << align_branch_jmp, | |
681 | align_branch_call_bit = 1 << align_branch_call, | |
682 | align_branch_indirect_bit = 1 << align_branch_indirect, | |
683 | align_branch_ret_bit = 1 << align_branch_ret | |
684 | }; | |
685 | ||
686 | static unsigned int align_branch = (align_branch_jcc_bit | |
687 | | align_branch_fused_bit | |
688 | | align_branch_jmp_bit); | |
689 | ||
690 | /* The maximum padding size for fused jcc. CMP like instruction can | |
691 | be 9 bytes and jcc can be 6 bytes. Leave room just in case for | |
692 | prefixes. */ | |
693 | #define MAX_FUSED_JCC_PADDING_SIZE 20 | |
694 | ||
695 | /* The maximum number of prefixes added for an instruction. */ | |
696 | static unsigned int align_branch_prefix_size = 5; | |
697 | ||
b6f8c7c4 L |
698 | /* Optimization: |
699 | 1. Clear the REX_W bit with register operand if possible. | |
700 | 2. Above plus use 128bit vector instruction to clear the full vector | |
701 | register. | |
702 | */ | |
703 | static int optimize = 0; | |
704 | ||
705 | /* Optimization: | |
706 | 1. Clear the REX_W bit with register operand if possible. | |
707 | 2. Above plus use 128bit vector instruction to clear the full vector | |
708 | register. | |
709 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
710 | "testb $imm7,%r8". | |
711 | */ | |
712 | static int optimize_for_space = 0; | |
713 | ||
2ca3ace5 L |
714 | /* Register prefix used for error message. */ |
715 | static const char *register_prefix = "%"; | |
716 | ||
47926f60 KH |
717 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
718 | leave, push, and pop instructions so that gcc has the same stack | |
719 | frame as in 32 bit mode. */ | |
720 | static char stackop_size = '\0'; | |
eecb386c | 721 | |
12b55ccc L |
722 | /* Non-zero to optimize code alignment. */ |
723 | int optimize_align_code = 1; | |
724 | ||
47926f60 KH |
725 | /* Non-zero to quieten some warnings. */ |
726 | static int quiet_warnings = 0; | |
a38cf1db | 727 | |
47926f60 KH |
728 | /* CPU name. */ |
729 | static const char *cpu_arch_name = NULL; | |
6305a203 | 730 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 731 | |
47926f60 | 732 | /* CPU feature flags. */ |
40fb9820 L |
733 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
734 | ||
ccc9c027 L |
735 | /* If we have selected a cpu we are generating instructions for. */ |
736 | static int cpu_arch_tune_set = 0; | |
737 | ||
9103f4f4 | 738 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 739 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
740 | |
741 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 742 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 743 | |
ccc9c027 | 744 | /* CPU instruction set architecture used. */ |
fbf3f584 | 745 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 746 | |
9103f4f4 | 747 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 748 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 749 | |
fddf5b5b AM |
750 | /* If set, conditional jumps are not automatically promoted to handle |
751 | larger than a byte offset. */ | |
752 | static unsigned int no_cond_jump_promotion = 0; | |
753 | ||
c0f3af97 L |
754 | /* Encode SSE instructions with VEX prefix. */ |
755 | static unsigned int sse2avx; | |
756 | ||
539f890d L |
757 | /* Encode scalar AVX instructions with specific vector length. */ |
758 | static enum | |
759 | { | |
760 | vex128 = 0, | |
761 | vex256 | |
762 | } avxscalar; | |
763 | ||
03751133 L |
764 | /* Encode VEX WIG instructions with specific vex.w. */ |
765 | static enum | |
766 | { | |
767 | vexw0 = 0, | |
768 | vexw1 | |
769 | } vexwig; | |
770 | ||
43234a1e L |
771 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
772 | static enum | |
773 | { | |
774 | evexl128 = 0, | |
775 | evexl256, | |
776 | evexl512 | |
777 | } evexlig; | |
778 | ||
779 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
780 | static enum | |
781 | { | |
782 | evexw0 = 0, | |
783 | evexw1 | |
784 | } evexwig; | |
785 | ||
d3d3c6db IT |
786 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
787 | static enum rc_type evexrcig = rne; | |
788 | ||
29b0f896 | 789 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 790 | static symbolS *GOT_symbol; |
29b0f896 | 791 | |
a4447b93 RH |
792 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
793 | unsigned int x86_dwarf2_return_column; | |
794 | ||
795 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
796 | int x86_cie_data_alignment; | |
797 | ||
252b5132 | 798 | /* Interface to relax_segment. |
fddf5b5b AM |
799 | There are 3 major relax states for 386 jump insns because the |
800 | different types of jumps add different sizes to frags when we're | |
e379e5f3 L |
801 | figuring out what sort of jump to choose to reach a given label. |
802 | ||
803 | BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align | |
804 | branches which are handled by md_estimate_size_before_relax() and | |
805 | i386_generic_table_relax_frag(). */ | |
252b5132 | 806 | |
47926f60 | 807 | /* Types. */ |
93c2a809 AM |
808 | #define UNCOND_JUMP 0 |
809 | #define COND_JUMP 1 | |
810 | #define COND_JUMP86 2 | |
e379e5f3 L |
811 | #define BRANCH_PADDING 3 |
812 | #define BRANCH_PREFIX 4 | |
813 | #define FUSED_JCC_PADDING 5 | |
fddf5b5b | 814 | |
47926f60 | 815 | /* Sizes. */ |
252b5132 RH |
816 | #define CODE16 1 |
817 | #define SMALL 0 | |
29b0f896 | 818 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 819 | #define BIG 2 |
29b0f896 | 820 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
821 | |
822 | #ifndef INLINE | |
823 | #ifdef __GNUC__ | |
824 | #define INLINE __inline__ | |
825 | #else | |
826 | #define INLINE | |
827 | #endif | |
828 | #endif | |
829 | ||
fddf5b5b AM |
830 | #define ENCODE_RELAX_STATE(type, size) \ |
831 | ((relax_substateT) (((type) << 2) | (size))) | |
832 | #define TYPE_FROM_RELAX_STATE(s) \ | |
833 | ((s) >> 2) | |
834 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
835 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
836 | |
837 | /* This table is used by relax_frag to promote short jumps to long | |
838 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
839 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
840 | don't allow a short jump in a 32 bit code segment to be promoted to | |
841 | a 16 bit offset jump because it's slower (requires data size | |
842 | prefix), and doesn't work, unless the destination is in the bottom | |
843 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
844 | ||
845 | const relax_typeS md_relax_table[] = | |
846 | { | |
24eab124 AM |
847 | /* The fields are: |
848 | 1) most positive reach of this state, | |
849 | 2) most negative reach of this state, | |
93c2a809 | 850 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 851 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 852 | |
fddf5b5b | 853 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
854 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
855 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
856 | /* dword jmp adds 4 bytes to frag: | |
857 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 858 | {0, 0, 4, 0}, |
93c2a809 AM |
859 | /* word jmp adds 2 byte2 to frag: |
860 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
861 | {0, 0, 2, 0}, |
862 | ||
93c2a809 AM |
863 | /* COND_JUMP states. */ |
864 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
865 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
866 | /* dword conditionals adds 5 bytes to frag: | |
867 | 1 extra opcode byte, 4 displacement bytes. */ | |
868 | {0, 0, 5, 0}, | |
fddf5b5b | 869 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
870 | 1 extra opcode byte, 2 displacement bytes. */ |
871 | {0, 0, 3, 0}, | |
872 | ||
873 | /* COND_JUMP86 states. */ | |
874 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
875 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
876 | /* dword conditionals adds 5 bytes to frag: | |
877 | 1 extra opcode byte, 4 displacement bytes. */ | |
878 | {0, 0, 5, 0}, | |
879 | /* word conditionals add 4 bytes to frag: | |
880 | 1 displacement byte and a 3 byte long branch insn. */ | |
881 | {0, 0, 4, 0} | |
252b5132 RH |
882 | }; |
883 | ||
9103f4f4 L |
884 | static const arch_entry cpu_arch[] = |
885 | { | |
89507696 JB |
886 | /* Do not replace the first two entries - i386_target_format() |
887 | relies on them being there in this order. */ | |
8a2c8fef | 888 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 889 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 890 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 891 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 892 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 893 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 894 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 895 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 896 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 897 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 898 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 899 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 900 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 901 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 902 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 903 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 904 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 905 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 906 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 907 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 908 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 909 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 910 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 911 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 912 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 913 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 914 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 915 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 916 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 917 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 918 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 919 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 920 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 921 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 922 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 923 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 924 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 925 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 926 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 927 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 928 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 929 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 930 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 931 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 932 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 933 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 934 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 935 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 936 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 937 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 938 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 939 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 940 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 941 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 942 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 943 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 944 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 945 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 946 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 947 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 948 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 949 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 950 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 951 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 952 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 953 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 954 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 955 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 956 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 957 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 958 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 959 | CPU_ZNVER1_FLAGS, 0 }, |
a9660a6f AP |
960 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
961 | CPU_ZNVER2_FLAGS, 0 }, | |
7b458c12 | 962 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 963 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 964 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 965 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 966 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 967 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 968 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 969 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 970 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 971 | CPU_387_FLAGS, 0 }, |
1848e567 L |
972 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
973 | CPU_687_FLAGS, 0 }, | |
d871f3f4 L |
974 | { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN, |
975 | CPU_CMOV_FLAGS, 0 }, | |
976 | { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN, | |
977 | CPU_FXSR_FLAGS, 0 }, | |
8a2c8fef | 978 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 979 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 980 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 981 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 982 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 983 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 984 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 985 | CPU_SSE3_FLAGS, 0 }, |
8a2c8fef | 986 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 987 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 988 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 989 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 990 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 991 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 992 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 993 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 994 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 995 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 996 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 997 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 998 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 999 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 1000 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1001 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 1002 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 1003 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 1004 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 1005 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 1006 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 1007 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 1008 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1009 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 1010 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 1011 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 1012 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1013 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 1014 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 1015 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 1016 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1017 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 1018 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 1019 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 1020 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1021 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 1022 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 1023 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 1024 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 1025 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 1026 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 1027 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 1028 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1029 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 1030 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1031 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 1032 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 1033 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 1034 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1035 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 1036 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 1037 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 1038 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1039 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 1040 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1041 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 1042 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 1043 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 1044 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1045 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 1046 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1047 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 1048 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 1049 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 1050 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 1051 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 1052 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 1053 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 1054 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1055 | CPU_LZCNT_FLAGS, 0 }, |
42164a71 | 1056 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 1057 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 1058 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1059 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 1060 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1061 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 1062 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 1063 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 1064 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1065 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 1066 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 1067 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 1068 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1069 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 1070 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 1071 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 1072 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 1073 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 1074 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 1075 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 1076 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 1077 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 1078 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 1079 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 1080 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 1081 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 1082 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1083 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 1084 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1085 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 1086 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1087 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 1088 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1089 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 1090 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 1091 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 1092 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1093 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 1094 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 1095 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 1096 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1097 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 1098 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 1099 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 1100 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1101 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 1102 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1103 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 1104 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1105 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 1106 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 1107 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 1108 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1109 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 1110 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1111 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
1112 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
1113 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
1114 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
1115 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
1116 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
1117 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
1118 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1119 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1120 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1121 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1122 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1123 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 1124 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1125 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1126 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1127 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1128 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1129 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1130 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1131 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1132 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1133 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1134 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1135 | CPU_IBT_FLAGS, 0 }, | |
1136 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1137 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1138 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1139 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1140 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1141 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1142 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1143 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1144 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1145 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1146 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1147 | CPU_PCONFIG_FLAGS, 0 }, | |
de89d0a3 IT |
1148 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
1149 | CPU_WAITPKG_FLAGS, 0 }, | |
c48935d7 IT |
1150 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
1151 | CPU_CLDEMOTE_FLAGS, 0 }, | |
c0a30a9f L |
1152 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
1153 | CPU_MOVDIRI_FLAGS, 0 }, | |
1154 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, | |
1155 | CPU_MOVDIR64B_FLAGS, 0 }, | |
d6aab7a1 XG |
1156 | { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN, |
1157 | CPU_AVX512_BF16_FLAGS, 0 }, | |
9186c494 L |
1158 | { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN, |
1159 | CPU_AVX512_VP2INTERSECT_FLAGS, 0 }, | |
dd455cf5 L |
1160 | { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN, |
1161 | CPU_ENQCMD_FLAGS, 0 }, | |
142861df JB |
1162 | { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN, |
1163 | CPU_RDPRU_FLAGS, 0 }, | |
1164 | { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN, | |
1165 | CPU_MCOMMIT_FLAGS, 0 }, | |
293f5f65 L |
1166 | }; |
1167 | ||
1168 | static const noarch_entry cpu_noarch[] = | |
1169 | { | |
1170 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1171 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1172 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1173 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
d871f3f4 L |
1174 | { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS }, |
1175 | { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS }, | |
293f5f65 L |
1176 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1177 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1178 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1179 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
1180 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, | |
1181 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1182 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
7deea9aa | 1183 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_FLAGS }, |
293f5f65 | 1184 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1185 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1186 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1187 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1188 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1189 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1190 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1191 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1192 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1193 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1194 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1195 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1196 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1197 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1198 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1199 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1200 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1201 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1202 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
c0a30a9f L |
1203 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
1204 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, | |
d6aab7a1 | 1205 | { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS }, |
9186c494 | 1206 | { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS }, |
dd455cf5 | 1207 | { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS }, |
e413e4e9 AM |
1208 | }; |
1209 | ||
704209c0 | 1210 | #ifdef I386COFF |
a6c24e68 NC |
1211 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1212 | is allowed to be optional. */ | |
1213 | ||
1214 | static symbolS * | |
1215 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1216 | { | |
1217 | addressT align = 0; | |
1218 | ||
1219 | SKIP_WHITESPACE (); | |
1220 | ||
7ab9ffdd | 1221 | if (needs_align |
a6c24e68 NC |
1222 | && *input_line_pointer == ',') |
1223 | { | |
1224 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1225 | |
a6c24e68 NC |
1226 | if (align == (addressT) -1) |
1227 | return NULL; | |
1228 | } | |
1229 | else | |
1230 | { | |
1231 | if (size >= 8) | |
1232 | align = 3; | |
1233 | else if (size >= 4) | |
1234 | align = 2; | |
1235 | else if (size >= 2) | |
1236 | align = 1; | |
1237 | else | |
1238 | align = 0; | |
1239 | } | |
1240 | ||
1241 | bss_alloc (symbolP, size, align); | |
1242 | return symbolP; | |
1243 | } | |
1244 | ||
704209c0 | 1245 | static void |
a6c24e68 NC |
1246 | pe_lcomm (int needs_align) |
1247 | { | |
1248 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1249 | } | |
704209c0 | 1250 | #endif |
a6c24e68 | 1251 | |
29b0f896 AM |
1252 | const pseudo_typeS md_pseudo_table[] = |
1253 | { | |
1254 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1255 | {"align", s_align_bytes, 0}, | |
1256 | #else | |
1257 | {"align", s_align_ptwo, 0}, | |
1258 | #endif | |
1259 | {"arch", set_cpu_arch, 0}, | |
1260 | #ifndef I386COFF | |
1261 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1262 | #else |
1263 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1264 | #endif |
1265 | {"ffloat", float_cons, 'f'}, | |
1266 | {"dfloat", float_cons, 'd'}, | |
1267 | {"tfloat", float_cons, 'x'}, | |
1268 | {"value", cons, 2}, | |
d182319b | 1269 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1270 | {"noopt", s_ignore, 0}, |
1271 | {"optim", s_ignore, 0}, | |
1272 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1273 | {"code16", set_code_flag, CODE_16BIT}, | |
1274 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1275 | #ifdef BFD64 |
29b0f896 | 1276 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1277 | #endif |
29b0f896 AM |
1278 | {"intel_syntax", set_intel_syntax, 1}, |
1279 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1280 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1281 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1282 | {"allow_index_reg", set_allow_index_reg, 1}, |
1283 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1284 | {"sse_check", set_check, 0}, |
1285 | {"operand_check", set_check, 1}, | |
3b22753a L |
1286 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1287 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1288 | #else |
68d20676 | 1289 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1290 | {"loc", dwarf2_directive_loc, 0}, |
1291 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1292 | #endif |
6482c264 NC |
1293 | #ifdef TE_PE |
1294 | {"secrel32", pe_directive_secrel, 0}, | |
1295 | #endif | |
29b0f896 AM |
1296 | {0, 0, 0} |
1297 | }; | |
1298 | ||
1299 | /* For interface with expression (). */ | |
1300 | extern char *input_line_pointer; | |
1301 | ||
1302 | /* Hash table for instruction mnemonic lookup. */ | |
1303 | static struct hash_control *op_hash; | |
1304 | ||
1305 | /* Hash table for register lookup. */ | |
1306 | static struct hash_control *reg_hash; | |
1307 | \f | |
ce8a8b2f AM |
1308 | /* Various efficient no-op patterns for aligning code labels. |
1309 | Note: Don't try to assemble the instructions in the comments. | |
1310 | 0L and 0w are not legal. */ | |
62a02d25 L |
1311 | static const unsigned char f32_1[] = |
1312 | {0x90}; /* nop */ | |
1313 | static const unsigned char f32_2[] = | |
1314 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1315 | static const unsigned char f32_3[] = | |
1316 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1317 | static const unsigned char f32_4[] = | |
1318 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1319 | static const unsigned char f32_6[] = |
1320 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1321 | static const unsigned char f32_7[] = | |
1322 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1323 | static const unsigned char f16_3[] = |
3ae729d5 | 1324 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1325 | static const unsigned char f16_4[] = |
3ae729d5 L |
1326 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1327 | static const unsigned char jump_disp8[] = | |
1328 | {0xeb}; /* jmp disp8 */ | |
1329 | static const unsigned char jump32_disp32[] = | |
1330 | {0xe9}; /* jmp disp32 */ | |
1331 | static const unsigned char jump16_disp32[] = | |
1332 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1333 | /* 32-bit NOPs patterns. */ |
1334 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1335 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1336 | }; |
1337 | /* 16-bit NOPs patterns. */ | |
1338 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1339 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1340 | }; |
1341 | /* nopl (%[re]ax) */ | |
1342 | static const unsigned char alt_3[] = | |
1343 | {0x0f,0x1f,0x00}; | |
1344 | /* nopl 0(%[re]ax) */ | |
1345 | static const unsigned char alt_4[] = | |
1346 | {0x0f,0x1f,0x40,0x00}; | |
1347 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1348 | static const unsigned char alt_5[] = | |
1349 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1350 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1351 | static const unsigned char alt_6[] = | |
1352 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1353 | /* nopl 0L(%[re]ax) */ | |
1354 | static const unsigned char alt_7[] = | |
1355 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1356 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1357 | static const unsigned char alt_8[] = | |
1358 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1359 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1360 | static const unsigned char alt_9[] = | |
1361 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1362 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1363 | static const unsigned char alt_10[] = | |
1364 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1365 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1366 | static const unsigned char alt_11[] = | |
1367 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1368 | /* 32-bit and 64-bit NOPs patterns. */ |
1369 | static const unsigned char *const alt_patt[] = { | |
1370 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1371 | alt_9, alt_10, alt_11 |
62a02d25 L |
1372 | }; |
1373 | ||
1374 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1375 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1376 | ||
1377 | static void | |
1378 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1379 | int count, int max_single_nop_size) | |
1380 | ||
1381 | { | |
3ae729d5 L |
1382 | /* Place the longer NOP first. */ |
1383 | int last; | |
1384 | int offset; | |
3076e594 NC |
1385 | const unsigned char *nops; |
1386 | ||
1387 | if (max_single_nop_size < 1) | |
1388 | { | |
1389 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1390 | max_single_nop_size); | |
1391 | return; | |
1392 | } | |
1393 | ||
1394 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1395 | |
1396 | /* Use the smaller one if the requsted one isn't available. */ | |
1397 | if (nops == NULL) | |
62a02d25 | 1398 | { |
3ae729d5 L |
1399 | max_single_nop_size--; |
1400 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1401 | } |
1402 | ||
3ae729d5 L |
1403 | last = count % max_single_nop_size; |
1404 | ||
1405 | count -= last; | |
1406 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1407 | memcpy (where + offset, nops, max_single_nop_size); | |
1408 | ||
1409 | if (last) | |
1410 | { | |
1411 | nops = patt[last - 1]; | |
1412 | if (nops == NULL) | |
1413 | { | |
1414 | /* Use the smaller one plus one-byte NOP if the needed one | |
1415 | isn't available. */ | |
1416 | last--; | |
1417 | nops = patt[last - 1]; | |
1418 | memcpy (where + offset, nops, last); | |
1419 | where[offset + last] = *patt[0]; | |
1420 | } | |
1421 | else | |
1422 | memcpy (where + offset, nops, last); | |
1423 | } | |
62a02d25 L |
1424 | } |
1425 | ||
3ae729d5 L |
1426 | static INLINE int |
1427 | fits_in_imm7 (offsetT num) | |
1428 | { | |
1429 | return (num & 0x7f) == num; | |
1430 | } | |
1431 | ||
1432 | static INLINE int | |
1433 | fits_in_imm31 (offsetT num) | |
1434 | { | |
1435 | return (num & 0x7fffffff) == num; | |
1436 | } | |
62a02d25 L |
1437 | |
1438 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1439 | single NOP instruction LIMIT. */ | |
1440 | ||
1441 | void | |
3ae729d5 | 1442 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1443 | { |
3ae729d5 | 1444 | const unsigned char *const *patt = NULL; |
62a02d25 | 1445 | int max_single_nop_size; |
3ae729d5 L |
1446 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1447 | int max_number_of_nops; | |
62a02d25 | 1448 | |
3ae729d5 | 1449 | switch (fragP->fr_type) |
62a02d25 | 1450 | { |
3ae729d5 L |
1451 | case rs_fill_nop: |
1452 | case rs_align_code: | |
1453 | break; | |
e379e5f3 L |
1454 | case rs_machine_dependent: |
1455 | /* Allow NOP padding for jumps and calls. */ | |
1456 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
1457 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
1458 | break; | |
1459 | /* Fall through. */ | |
3ae729d5 | 1460 | default: |
62a02d25 L |
1461 | return; |
1462 | } | |
1463 | ||
ccc9c027 L |
1464 | /* We need to decide which NOP sequence to use for 32bit and |
1465 | 64bit. When -mtune= is used: | |
4eed87de | 1466 | |
76bc74dc L |
1467 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1468 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1469 | 2. For the rest, alt_patt will be used. |
1470 | ||
1471 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1472 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1473 | be used. |
ccc9c027 L |
1474 | |
1475 | When -march= or .arch is used, we can't use anything beyond | |
1476 | cpu_arch_isa_flags. */ | |
1477 | ||
1478 | if (flag_code == CODE_16BIT) | |
1479 | { | |
3ae729d5 L |
1480 | patt = f16_patt; |
1481 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1482 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1483 | max_number_of_nops = 2; | |
252b5132 | 1484 | } |
33fef721 | 1485 | else |
ccc9c027 | 1486 | { |
fbf3f584 | 1487 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1488 | { |
1489 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1490 | switch (cpu_arch_tune) | |
1491 | { | |
1492 | case PROCESSOR_UNKNOWN: | |
1493 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1494 | optimize with nops. */ |
1495 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1496 | patt = alt_patt; |
ccc9c027 L |
1497 | else |
1498 | patt = f32_patt; | |
1499 | break; | |
ccc9c027 L |
1500 | case PROCESSOR_PENTIUM4: |
1501 | case PROCESSOR_NOCONA: | |
ef05d495 | 1502 | case PROCESSOR_CORE: |
76bc74dc | 1503 | case PROCESSOR_CORE2: |
bd5295b2 | 1504 | case PROCESSOR_COREI7: |
3632d14b | 1505 | case PROCESSOR_L1OM: |
7a9068fe | 1506 | case PROCESSOR_K1OM: |
76bc74dc | 1507 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1508 | case PROCESSOR_K6: |
1509 | case PROCESSOR_ATHLON: | |
1510 | case PROCESSOR_K8: | |
4eed87de | 1511 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1512 | case PROCESSOR_BD: |
029f3522 | 1513 | case PROCESSOR_ZNVER: |
7b458c12 | 1514 | case PROCESSOR_BT: |
80b8656c | 1515 | patt = alt_patt; |
ccc9c027 | 1516 | break; |
76bc74dc | 1517 | case PROCESSOR_I386: |
ccc9c027 L |
1518 | case PROCESSOR_I486: |
1519 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1520 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1521 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1522 | case PROCESSOR_GENERIC32: |
1523 | patt = f32_patt; | |
1524 | break; | |
4eed87de | 1525 | } |
ccc9c027 L |
1526 | } |
1527 | else | |
1528 | { | |
fbf3f584 | 1529 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1530 | { |
1531 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1532 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1533 | PROCESSOR_UNKNOWN. */ |
1534 | abort (); | |
1535 | break; | |
1536 | ||
76bc74dc | 1537 | case PROCESSOR_I386: |
ccc9c027 L |
1538 | case PROCESSOR_I486: |
1539 | case PROCESSOR_PENTIUM: | |
81486035 | 1540 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1541 | case PROCESSOR_K6: |
1542 | case PROCESSOR_ATHLON: | |
1543 | case PROCESSOR_K8: | |
4eed87de | 1544 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1545 | case PROCESSOR_BD: |
029f3522 | 1546 | case PROCESSOR_ZNVER: |
7b458c12 | 1547 | case PROCESSOR_BT: |
ccc9c027 L |
1548 | case PROCESSOR_GENERIC32: |
1549 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1550 | with nops. */ |
1551 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1552 | patt = alt_patt; |
ccc9c027 L |
1553 | else |
1554 | patt = f32_patt; | |
1555 | break; | |
76bc74dc L |
1556 | case PROCESSOR_PENTIUMPRO: |
1557 | case PROCESSOR_PENTIUM4: | |
1558 | case PROCESSOR_NOCONA: | |
1559 | case PROCESSOR_CORE: | |
ef05d495 | 1560 | case PROCESSOR_CORE2: |
bd5295b2 | 1561 | case PROCESSOR_COREI7: |
3632d14b | 1562 | case PROCESSOR_L1OM: |
7a9068fe | 1563 | case PROCESSOR_K1OM: |
22109423 | 1564 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1565 | patt = alt_patt; |
ccc9c027 L |
1566 | else |
1567 | patt = f32_patt; | |
1568 | break; | |
1569 | case PROCESSOR_GENERIC64: | |
80b8656c | 1570 | patt = alt_patt; |
ccc9c027 | 1571 | break; |
4eed87de | 1572 | } |
ccc9c027 L |
1573 | } |
1574 | ||
76bc74dc L |
1575 | if (patt == f32_patt) |
1576 | { | |
3ae729d5 L |
1577 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1578 | /* Limit number of NOPs to 2 for older processors. */ | |
1579 | max_number_of_nops = 2; | |
76bc74dc L |
1580 | } |
1581 | else | |
1582 | { | |
3ae729d5 L |
1583 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1584 | /* Limit number of NOPs to 7 for newer processors. */ | |
1585 | max_number_of_nops = 7; | |
1586 | } | |
1587 | } | |
1588 | ||
1589 | if (limit == 0) | |
1590 | limit = max_single_nop_size; | |
1591 | ||
1592 | if (fragP->fr_type == rs_fill_nop) | |
1593 | { | |
1594 | /* Output NOPs for .nop directive. */ | |
1595 | if (limit > max_single_nop_size) | |
1596 | { | |
1597 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1598 | _("invalid single nop size: %d " | |
1599 | "(expect within [0, %d])"), | |
1600 | limit, max_single_nop_size); | |
1601 | return; | |
1602 | } | |
1603 | } | |
e379e5f3 | 1604 | else if (fragP->fr_type != rs_machine_dependent) |
3ae729d5 L |
1605 | fragP->fr_var = count; |
1606 | ||
1607 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1608 | { | |
1609 | /* Generate jump over NOPs. */ | |
1610 | offsetT disp = count - 2; | |
1611 | if (fits_in_imm7 (disp)) | |
1612 | { | |
1613 | /* Use "jmp disp8" if possible. */ | |
1614 | count = disp; | |
1615 | where[0] = jump_disp8[0]; | |
1616 | where[1] = count; | |
1617 | where += 2; | |
1618 | } | |
1619 | else | |
1620 | { | |
1621 | unsigned int size_of_jump; | |
1622 | ||
1623 | if (flag_code == CODE_16BIT) | |
1624 | { | |
1625 | where[0] = jump16_disp32[0]; | |
1626 | where[1] = jump16_disp32[1]; | |
1627 | size_of_jump = 2; | |
1628 | } | |
1629 | else | |
1630 | { | |
1631 | where[0] = jump32_disp32[0]; | |
1632 | size_of_jump = 1; | |
1633 | } | |
1634 | ||
1635 | count -= size_of_jump + 4; | |
1636 | if (!fits_in_imm31 (count)) | |
1637 | { | |
1638 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1639 | _("jump over nop padding out of range")); | |
1640 | return; | |
1641 | } | |
1642 | ||
1643 | md_number_to_chars (where + size_of_jump, count, 4); | |
1644 | where += size_of_jump + 4; | |
76bc74dc | 1645 | } |
ccc9c027 | 1646 | } |
3ae729d5 L |
1647 | |
1648 | /* Generate multiple NOPs. */ | |
1649 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1650 | } |
1651 | ||
c6fb90c8 | 1652 | static INLINE int |
0dfbf9d7 | 1653 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1654 | { |
0dfbf9d7 | 1655 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1656 | { |
1657 | case 3: | |
0dfbf9d7 | 1658 | if (x->array[2]) |
c6fb90c8 | 1659 | return 0; |
1a0670f3 | 1660 | /* Fall through. */ |
c6fb90c8 | 1661 | case 2: |
0dfbf9d7 | 1662 | if (x->array[1]) |
c6fb90c8 | 1663 | return 0; |
1a0670f3 | 1664 | /* Fall through. */ |
c6fb90c8 | 1665 | case 1: |
0dfbf9d7 | 1666 | return !x->array[0]; |
c6fb90c8 L |
1667 | default: |
1668 | abort (); | |
1669 | } | |
40fb9820 L |
1670 | } |
1671 | ||
c6fb90c8 | 1672 | static INLINE void |
0dfbf9d7 | 1673 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1674 | { |
0dfbf9d7 | 1675 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1676 | { |
1677 | case 3: | |
0dfbf9d7 | 1678 | x->array[2] = v; |
1a0670f3 | 1679 | /* Fall through. */ |
c6fb90c8 | 1680 | case 2: |
0dfbf9d7 | 1681 | x->array[1] = v; |
1a0670f3 | 1682 | /* Fall through. */ |
c6fb90c8 | 1683 | case 1: |
0dfbf9d7 | 1684 | x->array[0] = v; |
1a0670f3 | 1685 | /* Fall through. */ |
c6fb90c8 L |
1686 | break; |
1687 | default: | |
1688 | abort (); | |
1689 | } | |
bab6aec1 JB |
1690 | |
1691 | x->bitfield.class = ClassNone; | |
75e5731b | 1692 | x->bitfield.instance = InstanceNone; |
c6fb90c8 | 1693 | } |
40fb9820 | 1694 | |
c6fb90c8 | 1695 | static INLINE int |
0dfbf9d7 L |
1696 | operand_type_equal (const union i386_operand_type *x, |
1697 | const union i386_operand_type *y) | |
c6fb90c8 | 1698 | { |
0dfbf9d7 | 1699 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1700 | { |
1701 | case 3: | |
0dfbf9d7 | 1702 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1703 | return 0; |
1a0670f3 | 1704 | /* Fall through. */ |
c6fb90c8 | 1705 | case 2: |
0dfbf9d7 | 1706 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1707 | return 0; |
1a0670f3 | 1708 | /* Fall through. */ |
c6fb90c8 | 1709 | case 1: |
0dfbf9d7 | 1710 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1711 | break; |
1712 | default: | |
1713 | abort (); | |
1714 | } | |
1715 | } | |
40fb9820 | 1716 | |
0dfbf9d7 L |
1717 | static INLINE int |
1718 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1719 | { | |
1720 | switch (ARRAY_SIZE(x->array)) | |
1721 | { | |
53467f57 IT |
1722 | case 4: |
1723 | if (x->array[3]) | |
1724 | return 0; | |
1725 | /* Fall through. */ | |
0dfbf9d7 L |
1726 | case 3: |
1727 | if (x->array[2]) | |
1728 | return 0; | |
1a0670f3 | 1729 | /* Fall through. */ |
0dfbf9d7 L |
1730 | case 2: |
1731 | if (x->array[1]) | |
1732 | return 0; | |
1a0670f3 | 1733 | /* Fall through. */ |
0dfbf9d7 L |
1734 | case 1: |
1735 | return !x->array[0]; | |
1736 | default: | |
1737 | abort (); | |
1738 | } | |
1739 | } | |
1740 | ||
0dfbf9d7 L |
1741 | static INLINE int |
1742 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1743 | const union i386_cpu_flags *y) | |
1744 | { | |
1745 | switch (ARRAY_SIZE(x->array)) | |
1746 | { | |
53467f57 IT |
1747 | case 4: |
1748 | if (x->array[3] != y->array[3]) | |
1749 | return 0; | |
1750 | /* Fall through. */ | |
0dfbf9d7 L |
1751 | case 3: |
1752 | if (x->array[2] != y->array[2]) | |
1753 | return 0; | |
1a0670f3 | 1754 | /* Fall through. */ |
0dfbf9d7 L |
1755 | case 2: |
1756 | if (x->array[1] != y->array[1]) | |
1757 | return 0; | |
1a0670f3 | 1758 | /* Fall through. */ |
0dfbf9d7 L |
1759 | case 1: |
1760 | return x->array[0] == y->array[0]; | |
1761 | break; | |
1762 | default: | |
1763 | abort (); | |
1764 | } | |
1765 | } | |
c6fb90c8 L |
1766 | |
1767 | static INLINE int | |
1768 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1769 | { | |
1770 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1771 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1772 | } |
1773 | ||
c6fb90c8 L |
1774 | static INLINE i386_cpu_flags |
1775 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1776 | { |
c6fb90c8 L |
1777 | switch (ARRAY_SIZE (x.array)) |
1778 | { | |
53467f57 IT |
1779 | case 4: |
1780 | x.array [3] &= y.array [3]; | |
1781 | /* Fall through. */ | |
c6fb90c8 L |
1782 | case 3: |
1783 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1784 | /* Fall through. */ |
c6fb90c8 L |
1785 | case 2: |
1786 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1787 | /* Fall through. */ |
c6fb90c8 L |
1788 | case 1: |
1789 | x.array [0] &= y.array [0]; | |
1790 | break; | |
1791 | default: | |
1792 | abort (); | |
1793 | } | |
1794 | return x; | |
1795 | } | |
40fb9820 | 1796 | |
c6fb90c8 L |
1797 | static INLINE i386_cpu_flags |
1798 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1799 | { |
c6fb90c8 | 1800 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1801 | { |
53467f57 IT |
1802 | case 4: |
1803 | x.array [3] |= y.array [3]; | |
1804 | /* Fall through. */ | |
c6fb90c8 L |
1805 | case 3: |
1806 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1807 | /* Fall through. */ |
c6fb90c8 L |
1808 | case 2: |
1809 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1810 | /* Fall through. */ |
c6fb90c8 L |
1811 | case 1: |
1812 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1813 | break; |
1814 | default: | |
1815 | abort (); | |
1816 | } | |
40fb9820 L |
1817 | return x; |
1818 | } | |
1819 | ||
309d3373 JB |
1820 | static INLINE i386_cpu_flags |
1821 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1822 | { | |
1823 | switch (ARRAY_SIZE (x.array)) | |
1824 | { | |
53467f57 IT |
1825 | case 4: |
1826 | x.array [3] &= ~y.array [3]; | |
1827 | /* Fall through. */ | |
309d3373 JB |
1828 | case 3: |
1829 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1830 | /* Fall through. */ |
309d3373 JB |
1831 | case 2: |
1832 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1833 | /* Fall through. */ |
309d3373 JB |
1834 | case 1: |
1835 | x.array [0] &= ~y.array [0]; | |
1836 | break; | |
1837 | default: | |
1838 | abort (); | |
1839 | } | |
1840 | return x; | |
1841 | } | |
1842 | ||
6c0946d0 JB |
1843 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; |
1844 | ||
c0f3af97 L |
1845 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1846 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1847 | ||
c0f3af97 | 1848 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1849 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1850 | |
1851 | /* Return CPU flags match bits. */ | |
3629bb00 | 1852 | |
40fb9820 | 1853 | static int |
d3ce72d0 | 1854 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1855 | { |
c0f3af97 L |
1856 | i386_cpu_flags x = t->cpu_flags; |
1857 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1858 | |
1859 | x.bitfield.cpu64 = 0; | |
1860 | x.bitfield.cpuno64 = 0; | |
1861 | ||
0dfbf9d7 | 1862 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1863 | { |
1864 | /* This instruction is available on all archs. */ | |
db12e14e | 1865 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1866 | } |
3629bb00 L |
1867 | else |
1868 | { | |
c0f3af97 | 1869 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1870 | i386_cpu_flags cpu = cpu_arch_flags; |
1871 | ||
ab592e75 JB |
1872 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1873 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1874 | return match; | |
1875 | x.bitfield.cpuavx512vl = 0; | |
1876 | ||
3629bb00 | 1877 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1878 | if (!cpu_flags_all_zero (&cpu)) |
1879 | { | |
a5ff0eb2 L |
1880 | if (x.bitfield.cpuavx) |
1881 | { | |
929f69fa | 1882 | /* We need to check a few extra flags with AVX. */ |
b9d49817 JB |
1883 | if (cpu.bitfield.cpuavx |
1884 | && (!t->opcode_modifier.sse2avx || sse2avx) | |
1885 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
929f69fa | 1886 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1887 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1888 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1889 | } |
929f69fa JB |
1890 | else if (x.bitfield.cpuavx512f) |
1891 | { | |
1892 | /* We need to check a few extra flags with AVX512F. */ | |
1893 | if (cpu.bitfield.cpuavx512f | |
1894 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1895 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1896 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1897 | match |= CPU_FLAGS_ARCH_MATCH; | |
1898 | } | |
a5ff0eb2 | 1899 | else |
db12e14e | 1900 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1901 | } |
3629bb00 | 1902 | } |
c0f3af97 | 1903 | return match; |
40fb9820 L |
1904 | } |
1905 | ||
c6fb90c8 L |
1906 | static INLINE i386_operand_type |
1907 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1908 | { |
bab6aec1 JB |
1909 | if (x.bitfield.class != y.bitfield.class) |
1910 | x.bitfield.class = ClassNone; | |
75e5731b JB |
1911 | if (x.bitfield.instance != y.bitfield.instance) |
1912 | x.bitfield.instance = InstanceNone; | |
bab6aec1 | 1913 | |
c6fb90c8 L |
1914 | switch (ARRAY_SIZE (x.array)) |
1915 | { | |
1916 | case 3: | |
1917 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1918 | /* Fall through. */ |
c6fb90c8 L |
1919 | case 2: |
1920 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1921 | /* Fall through. */ |
c6fb90c8 L |
1922 | case 1: |
1923 | x.array [0] &= y.array [0]; | |
1924 | break; | |
1925 | default: | |
1926 | abort (); | |
1927 | } | |
1928 | return x; | |
40fb9820 L |
1929 | } |
1930 | ||
73053c1f JB |
1931 | static INLINE i386_operand_type |
1932 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1933 | { | |
bab6aec1 | 1934 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 1935 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 1936 | |
73053c1f JB |
1937 | switch (ARRAY_SIZE (x.array)) |
1938 | { | |
1939 | case 3: | |
1940 | x.array [2] &= ~y.array [2]; | |
1941 | /* Fall through. */ | |
1942 | case 2: | |
1943 | x.array [1] &= ~y.array [1]; | |
1944 | /* Fall through. */ | |
1945 | case 1: | |
1946 | x.array [0] &= ~y.array [0]; | |
1947 | break; | |
1948 | default: | |
1949 | abort (); | |
1950 | } | |
1951 | return x; | |
1952 | } | |
1953 | ||
c6fb90c8 L |
1954 | static INLINE i386_operand_type |
1955 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1956 | { |
bab6aec1 JB |
1957 | gas_assert (x.bitfield.class == ClassNone || |
1958 | y.bitfield.class == ClassNone || | |
1959 | x.bitfield.class == y.bitfield.class); | |
75e5731b JB |
1960 | gas_assert (x.bitfield.instance == InstanceNone || |
1961 | y.bitfield.instance == InstanceNone || | |
1962 | x.bitfield.instance == y.bitfield.instance); | |
bab6aec1 | 1963 | |
c6fb90c8 | 1964 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1965 | { |
c6fb90c8 L |
1966 | case 3: |
1967 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1968 | /* Fall through. */ |
c6fb90c8 L |
1969 | case 2: |
1970 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1971 | /* Fall through. */ |
c6fb90c8 L |
1972 | case 1: |
1973 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1974 | break; |
1975 | default: | |
1976 | abort (); | |
1977 | } | |
c6fb90c8 L |
1978 | return x; |
1979 | } | |
40fb9820 | 1980 | |
c6fb90c8 L |
1981 | static INLINE i386_operand_type |
1982 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1983 | { | |
bab6aec1 | 1984 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 1985 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 1986 | |
c6fb90c8 L |
1987 | switch (ARRAY_SIZE (x.array)) |
1988 | { | |
1989 | case 3: | |
1990 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 1991 | /* Fall through. */ |
c6fb90c8 L |
1992 | case 2: |
1993 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 1994 | /* Fall through. */ |
c6fb90c8 L |
1995 | case 1: |
1996 | x.array [0] ^= y.array [0]; | |
1997 | break; | |
1998 | default: | |
1999 | abort (); | |
2000 | } | |
40fb9820 L |
2001 | return x; |
2002 | } | |
2003 | ||
40fb9820 L |
2004 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
2005 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
2006 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
2007 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
bab6aec1 JB |
2008 | static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP; |
2009 | static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM; | |
40fb9820 | 2010 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 2011 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
2012 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
2013 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
2014 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
2015 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
2016 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
2017 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
2018 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
2019 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
2020 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
2021 | ||
2022 | enum operand_type | |
2023 | { | |
2024 | reg, | |
40fb9820 L |
2025 | imm, |
2026 | disp, | |
2027 | anymem | |
2028 | }; | |
2029 | ||
c6fb90c8 | 2030 | static INLINE int |
40fb9820 L |
2031 | operand_type_check (i386_operand_type t, enum operand_type c) |
2032 | { | |
2033 | switch (c) | |
2034 | { | |
2035 | case reg: | |
bab6aec1 | 2036 | return t.bitfield.class == Reg; |
40fb9820 | 2037 | |
40fb9820 L |
2038 | case imm: |
2039 | return (t.bitfield.imm8 | |
2040 | || t.bitfield.imm8s | |
2041 | || t.bitfield.imm16 | |
2042 | || t.bitfield.imm32 | |
2043 | || t.bitfield.imm32s | |
2044 | || t.bitfield.imm64); | |
2045 | ||
2046 | case disp: | |
2047 | return (t.bitfield.disp8 | |
2048 | || t.bitfield.disp16 | |
2049 | || t.bitfield.disp32 | |
2050 | || t.bitfield.disp32s | |
2051 | || t.bitfield.disp64); | |
2052 | ||
2053 | case anymem: | |
2054 | return (t.bitfield.disp8 | |
2055 | || t.bitfield.disp16 | |
2056 | || t.bitfield.disp32 | |
2057 | || t.bitfield.disp32s | |
2058 | || t.bitfield.disp64 | |
2059 | || t.bitfield.baseindex); | |
2060 | ||
2061 | default: | |
2062 | abort (); | |
2063 | } | |
2cfe26b6 AM |
2064 | |
2065 | return 0; | |
40fb9820 L |
2066 | } |
2067 | ||
7a54636a L |
2068 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
2069 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
2070 | |
2071 | static INLINE int | |
7a54636a L |
2072 | match_operand_size (const insn_template *t, unsigned int wanted, |
2073 | unsigned int given) | |
5c07affc | 2074 | { |
3ac21baa JB |
2075 | return !((i.types[given].bitfield.byte |
2076 | && !t->operand_types[wanted].bitfield.byte) | |
2077 | || (i.types[given].bitfield.word | |
2078 | && !t->operand_types[wanted].bitfield.word) | |
2079 | || (i.types[given].bitfield.dword | |
2080 | && !t->operand_types[wanted].bitfield.dword) | |
2081 | || (i.types[given].bitfield.qword | |
2082 | && !t->operand_types[wanted].bitfield.qword) | |
2083 | || (i.types[given].bitfield.tbyte | |
2084 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
2085 | } |
2086 | ||
dd40ce22 L |
2087 | /* Return 1 if there is no conflict in SIMD register between operand |
2088 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
2089 | |
2090 | static INLINE int | |
dd40ce22 L |
2091 | match_simd_size (const insn_template *t, unsigned int wanted, |
2092 | unsigned int given) | |
1b54b8d7 | 2093 | { |
3ac21baa JB |
2094 | return !((i.types[given].bitfield.xmmword |
2095 | && !t->operand_types[wanted].bitfield.xmmword) | |
2096 | || (i.types[given].bitfield.ymmword | |
2097 | && !t->operand_types[wanted].bitfield.ymmword) | |
2098 | || (i.types[given].bitfield.zmmword | |
2099 | && !t->operand_types[wanted].bitfield.zmmword)); | |
1b54b8d7 JB |
2100 | } |
2101 | ||
7a54636a L |
2102 | /* Return 1 if there is no conflict in any size between operand GIVEN |
2103 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
2104 | |
2105 | static INLINE int | |
dd40ce22 L |
2106 | match_mem_size (const insn_template *t, unsigned int wanted, |
2107 | unsigned int given) | |
5c07affc | 2108 | { |
7a54636a | 2109 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2110 | && !((i.types[given].bitfield.unspecified |
af508cb9 | 2111 | && !i.broadcast |
3ac21baa JB |
2112 | && !t->operand_types[wanted].bitfield.unspecified) |
2113 | || (i.types[given].bitfield.fword | |
2114 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2115 | /* For scalar opcode templates to allow register and memory |
2116 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2117 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2118 | down-conversion vpmov*. */ | |
3528c362 | 2119 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
1b54b8d7 | 2120 | && !t->opcode_modifier.broadcast |
3ac21baa JB |
2121 | && (t->operand_types[wanted].bitfield.byte |
2122 | || t->operand_types[wanted].bitfield.word | |
2123 | || t->operand_types[wanted].bitfield.dword | |
2124 | || t->operand_types[wanted].bitfield.qword)) | |
2125 | ? (i.types[given].bitfield.xmmword | |
2126 | || i.types[given].bitfield.ymmword | |
2127 | || i.types[given].bitfield.zmmword) | |
2128 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2129 | } |
2130 | ||
3ac21baa JB |
2131 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2132 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2133 | is no size conflict on any operands for the template with operands reversed | |
2134 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2135 | |
3ac21baa JB |
2136 | #define MATCH_STRAIGHT 1 |
2137 | #define MATCH_REVERSE 2 | |
2138 | ||
2139 | static INLINE unsigned int | |
d3ce72d0 | 2140 | operand_size_match (const insn_template *t) |
5c07affc | 2141 | { |
3ac21baa | 2142 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc | 2143 | |
0cfa3eb3 | 2144 | /* Don't check non-absolute jump instructions. */ |
5c07affc | 2145 | if (t->opcode_modifier.jump |
0cfa3eb3 | 2146 | && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
5c07affc L |
2147 | return match; |
2148 | ||
2149 | /* Check memory and accumulator operand size. */ | |
2150 | for (j = 0; j < i.operands; j++) | |
2151 | { | |
3528c362 JB |
2152 | if (i.types[j].bitfield.class != Reg |
2153 | && i.types[j].bitfield.class != RegSIMD | |
601e8564 | 2154 | && t->opcode_modifier.anysize) |
5c07affc L |
2155 | continue; |
2156 | ||
bab6aec1 | 2157 | if (t->operand_types[j].bitfield.class == Reg |
7a54636a | 2158 | && !match_operand_size (t, j, j)) |
5c07affc L |
2159 | { |
2160 | match = 0; | |
2161 | break; | |
2162 | } | |
2163 | ||
3528c362 | 2164 | if (t->operand_types[j].bitfield.class == RegSIMD |
3ac21baa | 2165 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2166 | { |
2167 | match = 0; | |
2168 | break; | |
2169 | } | |
2170 | ||
75e5731b | 2171 | if (t->operand_types[j].bitfield.instance == Accum |
7a54636a | 2172 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2173 | { |
2174 | match = 0; | |
2175 | break; | |
2176 | } | |
2177 | ||
c48dadc9 | 2178 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2179 | { |
2180 | match = 0; | |
2181 | break; | |
2182 | } | |
2183 | } | |
2184 | ||
3ac21baa | 2185 | if (!t->opcode_modifier.d) |
891edac4 L |
2186 | { |
2187 | mismatch: | |
3ac21baa JB |
2188 | if (!match) |
2189 | i.error = operand_size_mismatch; | |
2190 | return match; | |
891edac4 | 2191 | } |
5c07affc L |
2192 | |
2193 | /* Check reverse. */ | |
f5eb1d70 | 2194 | gas_assert (i.operands >= 2 && i.operands <= 3); |
5c07affc | 2195 | |
f5eb1d70 | 2196 | for (j = 0; j < i.operands; j++) |
5c07affc | 2197 | { |
f5eb1d70 JB |
2198 | unsigned int given = i.operands - j - 1; |
2199 | ||
bab6aec1 | 2200 | if (t->operand_types[j].bitfield.class == Reg |
f5eb1d70 | 2201 | && !match_operand_size (t, j, given)) |
891edac4 | 2202 | goto mismatch; |
5c07affc | 2203 | |
3528c362 | 2204 | if (t->operand_types[j].bitfield.class == RegSIMD |
f5eb1d70 | 2205 | && !match_simd_size (t, j, given)) |
dbbc8b7e JB |
2206 | goto mismatch; |
2207 | ||
75e5731b | 2208 | if (t->operand_types[j].bitfield.instance == Accum |
f5eb1d70 JB |
2209 | && (!match_operand_size (t, j, given) |
2210 | || !match_simd_size (t, j, given))) | |
dbbc8b7e JB |
2211 | goto mismatch; |
2212 | ||
f5eb1d70 | 2213 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
891edac4 | 2214 | goto mismatch; |
5c07affc L |
2215 | } |
2216 | ||
3ac21baa | 2217 | return match | MATCH_REVERSE; |
5c07affc L |
2218 | } |
2219 | ||
c6fb90c8 | 2220 | static INLINE int |
40fb9820 L |
2221 | operand_type_match (i386_operand_type overlap, |
2222 | i386_operand_type given) | |
2223 | { | |
2224 | i386_operand_type temp = overlap; | |
2225 | ||
7d5e4556 | 2226 | temp.bitfield.unspecified = 0; |
5c07affc L |
2227 | temp.bitfield.byte = 0; |
2228 | temp.bitfield.word = 0; | |
2229 | temp.bitfield.dword = 0; | |
2230 | temp.bitfield.fword = 0; | |
2231 | temp.bitfield.qword = 0; | |
2232 | temp.bitfield.tbyte = 0; | |
2233 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2234 | temp.bitfield.ymmword = 0; |
43234a1e | 2235 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 2236 | if (operand_type_all_zero (&temp)) |
891edac4 | 2237 | goto mismatch; |
40fb9820 | 2238 | |
6f2f06be | 2239 | if (given.bitfield.baseindex == overlap.bitfield.baseindex) |
891edac4 L |
2240 | return 1; |
2241 | ||
2242 | mismatch: | |
a65babc9 | 2243 | i.error = operand_type_mismatch; |
891edac4 | 2244 | return 0; |
40fb9820 L |
2245 | } |
2246 | ||
7d5e4556 | 2247 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd | 2248 | unless the expected operand type register overlap is null. |
5de4d9ef | 2249 | Some Intel syntax memory operand size checking also happens here. */ |
40fb9820 | 2250 | |
c6fb90c8 | 2251 | static INLINE int |
dc821c5f | 2252 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2253 | i386_operand_type t0, |
40fb9820 L |
2254 | i386_operand_type g1, |
2255 | i386_operand_type t1) | |
2256 | { | |
bab6aec1 | 2257 | if (g0.bitfield.class != Reg |
3528c362 | 2258 | && g0.bitfield.class != RegSIMD |
10c17abd JB |
2259 | && (!operand_type_check (g0, anymem) |
2260 | || g0.bitfield.unspecified | |
5de4d9ef JB |
2261 | || (t0.bitfield.class != Reg |
2262 | && t0.bitfield.class != RegSIMD))) | |
40fb9820 L |
2263 | return 1; |
2264 | ||
bab6aec1 | 2265 | if (g1.bitfield.class != Reg |
3528c362 | 2266 | && g1.bitfield.class != RegSIMD |
10c17abd JB |
2267 | && (!operand_type_check (g1, anymem) |
2268 | || g1.bitfield.unspecified | |
5de4d9ef JB |
2269 | || (t1.bitfield.class != Reg |
2270 | && t1.bitfield.class != RegSIMD))) | |
40fb9820 L |
2271 | return 1; |
2272 | ||
dc821c5f JB |
2273 | if (g0.bitfield.byte == g1.bitfield.byte |
2274 | && g0.bitfield.word == g1.bitfield.word | |
2275 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2276 | && g0.bitfield.qword == g1.bitfield.qword |
2277 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2278 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2279 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2280 | return 1; |
2281 | ||
dc821c5f JB |
2282 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2283 | && !(t0.bitfield.word & t1.bitfield.word) | |
2284 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2285 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2286 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2287 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2288 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2289 | return 1; |
2290 | ||
a65babc9 | 2291 | i.error = register_type_mismatch; |
891edac4 L |
2292 | |
2293 | return 0; | |
40fb9820 L |
2294 | } |
2295 | ||
4c692bc7 JB |
2296 | static INLINE unsigned int |
2297 | register_number (const reg_entry *r) | |
2298 | { | |
2299 | unsigned int nr = r->reg_num; | |
2300 | ||
2301 | if (r->reg_flags & RegRex) | |
2302 | nr += 8; | |
2303 | ||
200cbe0f L |
2304 | if (r->reg_flags & RegVRex) |
2305 | nr += 16; | |
2306 | ||
4c692bc7 JB |
2307 | return nr; |
2308 | } | |
2309 | ||
252b5132 | 2310 | static INLINE unsigned int |
40fb9820 | 2311 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2312 | { |
b5014f7a | 2313 | if (t.bitfield.disp8) |
40fb9820 L |
2314 | return 1; |
2315 | else if (t.bitfield.disp16 | |
2316 | || t.bitfield.disp32 | |
2317 | || t.bitfield.disp32s) | |
2318 | return 2; | |
2319 | else | |
2320 | return 0; | |
252b5132 RH |
2321 | } |
2322 | ||
2323 | static INLINE int | |
65879393 | 2324 | fits_in_signed_byte (addressT num) |
252b5132 | 2325 | { |
65879393 | 2326 | return num + 0x80 <= 0xff; |
47926f60 | 2327 | } |
252b5132 RH |
2328 | |
2329 | static INLINE int | |
65879393 | 2330 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2331 | { |
65879393 | 2332 | return num <= 0xff; |
47926f60 | 2333 | } |
252b5132 RH |
2334 | |
2335 | static INLINE int | |
65879393 | 2336 | fits_in_unsigned_word (addressT num) |
252b5132 | 2337 | { |
65879393 | 2338 | return num <= 0xffff; |
47926f60 | 2339 | } |
252b5132 RH |
2340 | |
2341 | static INLINE int | |
65879393 | 2342 | fits_in_signed_word (addressT num) |
252b5132 | 2343 | { |
65879393 | 2344 | return num + 0x8000 <= 0xffff; |
47926f60 | 2345 | } |
2a962e6d | 2346 | |
3e73aa7c | 2347 | static INLINE int |
65879393 | 2348 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2349 | { |
2350 | #ifndef BFD64 | |
2351 | return 1; | |
2352 | #else | |
65879393 | 2353 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2354 | #endif |
2355 | } /* fits_in_signed_long() */ | |
2a962e6d | 2356 | |
3e73aa7c | 2357 | static INLINE int |
65879393 | 2358 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2359 | { |
2360 | #ifndef BFD64 | |
2361 | return 1; | |
2362 | #else | |
65879393 | 2363 | return num <= 0xffffffff; |
3e73aa7c JH |
2364 | #endif |
2365 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2366 | |
43234a1e | 2367 | static INLINE int |
b5014f7a | 2368 | fits_in_disp8 (offsetT num) |
43234a1e L |
2369 | { |
2370 | int shift = i.memshift; | |
2371 | unsigned int mask; | |
2372 | ||
2373 | if (shift == -1) | |
2374 | abort (); | |
2375 | ||
2376 | mask = (1 << shift) - 1; | |
2377 | ||
2378 | /* Return 0 if NUM isn't properly aligned. */ | |
2379 | if ((num & mask)) | |
2380 | return 0; | |
2381 | ||
2382 | /* Check if NUM will fit in 8bit after shift. */ | |
2383 | return fits_in_signed_byte (num >> shift); | |
2384 | } | |
2385 | ||
a683cc34 SP |
2386 | static INLINE int |
2387 | fits_in_imm4 (offsetT num) | |
2388 | { | |
2389 | return (num & 0xf) == num; | |
2390 | } | |
2391 | ||
40fb9820 | 2392 | static i386_operand_type |
e3bb37b5 | 2393 | smallest_imm_type (offsetT num) |
252b5132 | 2394 | { |
40fb9820 | 2395 | i386_operand_type t; |
7ab9ffdd | 2396 | |
0dfbf9d7 | 2397 | operand_type_set (&t, 0); |
40fb9820 L |
2398 | t.bitfield.imm64 = 1; |
2399 | ||
2400 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2401 | { |
2402 | /* This code is disabled on the 486 because all the Imm1 forms | |
2403 | in the opcode table are slower on the i486. They're the | |
2404 | versions with the implicitly specified single-position | |
2405 | displacement, which has another syntax if you really want to | |
2406 | use that form. */ | |
40fb9820 L |
2407 | t.bitfield.imm1 = 1; |
2408 | t.bitfield.imm8 = 1; | |
2409 | t.bitfield.imm8s = 1; | |
2410 | t.bitfield.imm16 = 1; | |
2411 | t.bitfield.imm32 = 1; | |
2412 | t.bitfield.imm32s = 1; | |
2413 | } | |
2414 | else if (fits_in_signed_byte (num)) | |
2415 | { | |
2416 | t.bitfield.imm8 = 1; | |
2417 | t.bitfield.imm8s = 1; | |
2418 | t.bitfield.imm16 = 1; | |
2419 | t.bitfield.imm32 = 1; | |
2420 | t.bitfield.imm32s = 1; | |
2421 | } | |
2422 | else if (fits_in_unsigned_byte (num)) | |
2423 | { | |
2424 | t.bitfield.imm8 = 1; | |
2425 | t.bitfield.imm16 = 1; | |
2426 | t.bitfield.imm32 = 1; | |
2427 | t.bitfield.imm32s = 1; | |
2428 | } | |
2429 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2430 | { | |
2431 | t.bitfield.imm16 = 1; | |
2432 | t.bitfield.imm32 = 1; | |
2433 | t.bitfield.imm32s = 1; | |
2434 | } | |
2435 | else if (fits_in_signed_long (num)) | |
2436 | { | |
2437 | t.bitfield.imm32 = 1; | |
2438 | t.bitfield.imm32s = 1; | |
2439 | } | |
2440 | else if (fits_in_unsigned_long (num)) | |
2441 | t.bitfield.imm32 = 1; | |
2442 | ||
2443 | return t; | |
47926f60 | 2444 | } |
252b5132 | 2445 | |
847f7ad4 | 2446 | static offsetT |
e3bb37b5 | 2447 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2448 | { |
508866be | 2449 | addressT mask; |
ba2adb93 | 2450 | |
847f7ad4 AM |
2451 | switch (size) |
2452 | { | |
508866be L |
2453 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2454 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2455 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2456 | #ifdef BFD64 |
2457 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2458 | #endif | |
47926f60 | 2459 | default: abort (); |
847f7ad4 AM |
2460 | } |
2461 | ||
9de868bf L |
2462 | #ifdef BFD64 |
2463 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2464 | if (flag_code != CODE_64BIT | |
2465 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2466 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2467 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2468 | #endif |
ba2adb93 | 2469 | |
47926f60 | 2470 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2471 | { |
2472 | char buf1[40], buf2[40]; | |
2473 | ||
2474 | sprint_value (buf1, val); | |
2475 | sprint_value (buf2, val & mask); | |
2476 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2477 | } | |
2478 | return val & mask; | |
2479 | } | |
2480 | ||
c32fa91d L |
2481 | enum PREFIX_GROUP |
2482 | { | |
2483 | PREFIX_EXIST = 0, | |
2484 | PREFIX_LOCK, | |
2485 | PREFIX_REP, | |
04ef582a | 2486 | PREFIX_DS, |
c32fa91d L |
2487 | PREFIX_OTHER |
2488 | }; | |
2489 | ||
2490 | /* Returns | |
2491 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2492 | same class already exists. | |
2493 | b. PREFIX_LOCK if lock prefix is added. | |
2494 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2495 | d. PREFIX_DS if ds prefix is added. |
2496 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2497 | */ |
2498 | ||
2499 | static enum PREFIX_GROUP | |
e3bb37b5 | 2500 | add_prefix (unsigned int prefix) |
252b5132 | 2501 | { |
c32fa91d | 2502 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2503 | unsigned int q; |
252b5132 | 2504 | |
29b0f896 AM |
2505 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2506 | && flag_code == CODE_64BIT) | |
b1905489 | 2507 | { |
161a04f6 | 2508 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2509 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2510 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2511 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2512 | ret = PREFIX_EXIST; |
b1905489 JB |
2513 | q = REX_PREFIX; |
2514 | } | |
3e73aa7c | 2515 | else |
b1905489 JB |
2516 | { |
2517 | switch (prefix) | |
2518 | { | |
2519 | default: | |
2520 | abort (); | |
2521 | ||
b1905489 | 2522 | case DS_PREFIX_OPCODE: |
04ef582a L |
2523 | ret = PREFIX_DS; |
2524 | /* Fall through. */ | |
2525 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2526 | case ES_PREFIX_OPCODE: |
2527 | case FS_PREFIX_OPCODE: | |
2528 | case GS_PREFIX_OPCODE: | |
2529 | case SS_PREFIX_OPCODE: | |
2530 | q = SEG_PREFIX; | |
2531 | break; | |
2532 | ||
2533 | case REPNE_PREFIX_OPCODE: | |
2534 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2535 | q = REP_PREFIX; |
2536 | ret = PREFIX_REP; | |
2537 | break; | |
2538 | ||
b1905489 | 2539 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2540 | q = LOCK_PREFIX; |
2541 | ret = PREFIX_LOCK; | |
b1905489 JB |
2542 | break; |
2543 | ||
2544 | case FWAIT_OPCODE: | |
2545 | q = WAIT_PREFIX; | |
2546 | break; | |
2547 | ||
2548 | case ADDR_PREFIX_OPCODE: | |
2549 | q = ADDR_PREFIX; | |
2550 | break; | |
2551 | ||
2552 | case DATA_PREFIX_OPCODE: | |
2553 | q = DATA_PREFIX; | |
2554 | break; | |
2555 | } | |
2556 | if (i.prefix[q] != 0) | |
c32fa91d | 2557 | ret = PREFIX_EXIST; |
b1905489 | 2558 | } |
252b5132 | 2559 | |
b1905489 | 2560 | if (ret) |
252b5132 | 2561 | { |
b1905489 JB |
2562 | if (!i.prefix[q]) |
2563 | ++i.prefixes; | |
2564 | i.prefix[q] |= prefix; | |
252b5132 | 2565 | } |
b1905489 JB |
2566 | else |
2567 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2568 | |
252b5132 RH |
2569 | return ret; |
2570 | } | |
2571 | ||
2572 | static void | |
78f12dd3 | 2573 | update_code_flag (int value, int check) |
eecb386c | 2574 | { |
78f12dd3 L |
2575 | PRINTF_LIKE ((*as_error)); |
2576 | ||
1e9cc1c2 | 2577 | flag_code = (enum flag_code) value; |
40fb9820 L |
2578 | if (flag_code == CODE_64BIT) |
2579 | { | |
2580 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2581 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2582 | } |
2583 | else | |
2584 | { | |
2585 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2586 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2587 | } |
2588 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2589 | { |
78f12dd3 L |
2590 | if (check) |
2591 | as_error = as_fatal; | |
2592 | else | |
2593 | as_error = as_bad; | |
2594 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2595 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2596 | } |
40fb9820 | 2597 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2598 | { |
78f12dd3 L |
2599 | if (check) |
2600 | as_error = as_fatal; | |
2601 | else | |
2602 | as_error = as_bad; | |
2603 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2604 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2605 | } |
eecb386c AM |
2606 | stackop_size = '\0'; |
2607 | } | |
2608 | ||
78f12dd3 L |
2609 | static void |
2610 | set_code_flag (int value) | |
2611 | { | |
2612 | update_code_flag (value, 0); | |
2613 | } | |
2614 | ||
eecb386c | 2615 | static void |
e3bb37b5 | 2616 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2617 | { |
1e9cc1c2 | 2618 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2619 | if (flag_code != CODE_16BIT) |
2620 | abort (); | |
2621 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2622 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2623 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2624 | } |
2625 | ||
2626 | static void | |
e3bb37b5 | 2627 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2628 | { |
2629 | /* Find out if register prefixing is specified. */ | |
2630 | int ask_naked_reg = 0; | |
2631 | ||
2632 | SKIP_WHITESPACE (); | |
29b0f896 | 2633 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2634 | { |
d02603dc NC |
2635 | char *string; |
2636 | int e = get_symbol_name (&string); | |
252b5132 | 2637 | |
47926f60 | 2638 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2639 | ask_naked_reg = 1; |
47926f60 | 2640 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2641 | ask_naked_reg = -1; |
2642 | else | |
d0b47220 | 2643 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2644 | (void) restore_line_pointer (e); |
252b5132 RH |
2645 | } |
2646 | demand_empty_rest_of_line (); | |
c3332e24 | 2647 | |
252b5132 RH |
2648 | intel_syntax = syntax_flag; |
2649 | ||
2650 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2651 | allow_naked_reg = (intel_syntax |
2652 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2653 | else |
2654 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2655 | |
ee86248c | 2656 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2657 | |
e4a3b5a4 | 2658 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2659 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2660 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2661 | } |
2662 | ||
1efbbeb4 L |
2663 | static void |
2664 | set_intel_mnemonic (int mnemonic_flag) | |
2665 | { | |
e1d4d893 | 2666 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2667 | } |
2668 | ||
db51cc60 L |
2669 | static void |
2670 | set_allow_index_reg (int flag) | |
2671 | { | |
2672 | allow_index_reg = flag; | |
2673 | } | |
2674 | ||
cb19c032 | 2675 | static void |
7bab8ab5 | 2676 | set_check (int what) |
cb19c032 | 2677 | { |
7bab8ab5 JB |
2678 | enum check_kind *kind; |
2679 | const char *str; | |
2680 | ||
2681 | if (what) | |
2682 | { | |
2683 | kind = &operand_check; | |
2684 | str = "operand"; | |
2685 | } | |
2686 | else | |
2687 | { | |
2688 | kind = &sse_check; | |
2689 | str = "sse"; | |
2690 | } | |
2691 | ||
cb19c032 L |
2692 | SKIP_WHITESPACE (); |
2693 | ||
2694 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2695 | { | |
d02603dc NC |
2696 | char *string; |
2697 | int e = get_symbol_name (&string); | |
cb19c032 L |
2698 | |
2699 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2700 | *kind = check_none; |
cb19c032 | 2701 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2702 | *kind = check_warning; |
cb19c032 | 2703 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2704 | *kind = check_error; |
cb19c032 | 2705 | else |
7bab8ab5 | 2706 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2707 | (void) restore_line_pointer (e); |
cb19c032 L |
2708 | } |
2709 | else | |
7bab8ab5 | 2710 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2711 | |
2712 | demand_empty_rest_of_line (); | |
2713 | } | |
2714 | ||
8a9036a4 L |
2715 | static void |
2716 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2717 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2718 | { |
2719 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2720 | static const char *arch; | |
2721 | ||
2722 | /* Intel LIOM is only supported on ELF. */ | |
2723 | if (!IS_ELF) | |
2724 | return; | |
2725 | ||
2726 | if (!arch) | |
2727 | { | |
2728 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2729 | use default_arch. */ | |
2730 | arch = cpu_arch_name; | |
2731 | if (!arch) | |
2732 | arch = default_arch; | |
2733 | } | |
2734 | ||
81486035 L |
2735 | /* If we are targeting Intel MCU, we must enable it. */ |
2736 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2737 | || new_flag.bitfield.cpuiamcu) | |
2738 | return; | |
2739 | ||
3632d14b | 2740 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2741 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2742 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2743 | return; |
76ba9986 | 2744 | |
7a9068fe L |
2745 | /* If we are targeting Intel K1OM, we must enable it. */ |
2746 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2747 | || new_flag.bitfield.cpuk1om) | |
2748 | return; | |
2749 | ||
8a9036a4 L |
2750 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2751 | #endif | |
2752 | } | |
2753 | ||
e413e4e9 | 2754 | static void |
e3bb37b5 | 2755 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2756 | { |
47926f60 | 2757 | SKIP_WHITESPACE (); |
e413e4e9 | 2758 | |
29b0f896 | 2759 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2760 | { |
d02603dc NC |
2761 | char *string; |
2762 | int e = get_symbol_name (&string); | |
91d6fa6a | 2763 | unsigned int j; |
40fb9820 | 2764 | i386_cpu_flags flags; |
e413e4e9 | 2765 | |
91d6fa6a | 2766 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2767 | { |
91d6fa6a | 2768 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2769 | { |
91d6fa6a | 2770 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2771 | |
5c6af06e JB |
2772 | if (*string != '.') |
2773 | { | |
91d6fa6a | 2774 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2775 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2776 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2777 | if (flag_code == CODE_64BIT) |
2778 | { | |
2779 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2780 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2781 | } | |
2782 | else | |
2783 | { | |
2784 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2785 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2786 | } | |
91d6fa6a NC |
2787 | cpu_arch_isa = cpu_arch[j].type; |
2788 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2789 | if (!cpu_arch_tune_set) |
2790 | { | |
2791 | cpu_arch_tune = cpu_arch_isa; | |
2792 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2793 | } | |
5c6af06e JB |
2794 | break; |
2795 | } | |
40fb9820 | 2796 | |
293f5f65 L |
2797 | flags = cpu_flags_or (cpu_arch_flags, |
2798 | cpu_arch[j].flags); | |
81486035 | 2799 | |
5b64d091 | 2800 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2801 | { |
6305a203 L |
2802 | if (cpu_sub_arch_name) |
2803 | { | |
2804 | char *name = cpu_sub_arch_name; | |
2805 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2806 | cpu_arch[j].name, |
1bf57e9f | 2807 | (const char *) NULL); |
6305a203 L |
2808 | free (name); |
2809 | } | |
2810 | else | |
91d6fa6a | 2811 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2812 | cpu_arch_flags = flags; |
a586129e | 2813 | cpu_arch_isa_flags = flags; |
5c6af06e | 2814 | } |
0089dace L |
2815 | else |
2816 | cpu_arch_isa_flags | |
2817 | = cpu_flags_or (cpu_arch_isa_flags, | |
2818 | cpu_arch[j].flags); | |
d02603dc | 2819 | (void) restore_line_pointer (e); |
5c6af06e JB |
2820 | demand_empty_rest_of_line (); |
2821 | return; | |
e413e4e9 AM |
2822 | } |
2823 | } | |
293f5f65 L |
2824 | |
2825 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2826 | { | |
33eaf5de | 2827 | /* Disable an ISA extension. */ |
293f5f65 L |
2828 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2829 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2830 | { | |
2831 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2832 | cpu_noarch[j].flags); | |
2833 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2834 | { | |
2835 | if (cpu_sub_arch_name) | |
2836 | { | |
2837 | char *name = cpu_sub_arch_name; | |
2838 | cpu_sub_arch_name = concat (name, string, | |
2839 | (const char *) NULL); | |
2840 | free (name); | |
2841 | } | |
2842 | else | |
2843 | cpu_sub_arch_name = xstrdup (string); | |
2844 | cpu_arch_flags = flags; | |
2845 | cpu_arch_isa_flags = flags; | |
2846 | } | |
2847 | (void) restore_line_pointer (e); | |
2848 | demand_empty_rest_of_line (); | |
2849 | return; | |
2850 | } | |
2851 | ||
2852 | j = ARRAY_SIZE (cpu_arch); | |
2853 | } | |
2854 | ||
91d6fa6a | 2855 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2856 | as_bad (_("no such architecture: `%s'"), string); |
2857 | ||
2858 | *input_line_pointer = e; | |
2859 | } | |
2860 | else | |
2861 | as_bad (_("missing cpu architecture")); | |
2862 | ||
fddf5b5b AM |
2863 | no_cond_jump_promotion = 0; |
2864 | if (*input_line_pointer == ',' | |
29b0f896 | 2865 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2866 | { |
d02603dc NC |
2867 | char *string; |
2868 | char e; | |
2869 | ||
2870 | ++input_line_pointer; | |
2871 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2872 | |
2873 | if (strcmp (string, "nojumps") == 0) | |
2874 | no_cond_jump_promotion = 1; | |
2875 | else if (strcmp (string, "jumps") == 0) | |
2876 | ; | |
2877 | else | |
2878 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2879 | ||
d02603dc | 2880 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2881 | } |
2882 | ||
e413e4e9 AM |
2883 | demand_empty_rest_of_line (); |
2884 | } | |
2885 | ||
8a9036a4 L |
2886 | enum bfd_architecture |
2887 | i386_arch (void) | |
2888 | { | |
3632d14b | 2889 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2890 | { |
2891 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2892 | || flag_code != CODE_64BIT) | |
2893 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2894 | return bfd_arch_l1om; | |
2895 | } | |
7a9068fe L |
2896 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2897 | { | |
2898 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2899 | || flag_code != CODE_64BIT) | |
2900 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2901 | return bfd_arch_k1om; | |
2902 | } | |
81486035 L |
2903 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2904 | { | |
2905 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2906 | || flag_code == CODE_64BIT) | |
2907 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2908 | return bfd_arch_iamcu; | |
2909 | } | |
8a9036a4 L |
2910 | else |
2911 | return bfd_arch_i386; | |
2912 | } | |
2913 | ||
b9d79e03 | 2914 | unsigned long |
7016a5d5 | 2915 | i386_mach (void) |
b9d79e03 | 2916 | { |
351f65ca | 2917 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2918 | { |
3632d14b | 2919 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2920 | { |
351f65ca L |
2921 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2922 | || default_arch[6] != '\0') | |
8a9036a4 L |
2923 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2924 | return bfd_mach_l1om; | |
2925 | } | |
7a9068fe L |
2926 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2927 | { | |
2928 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2929 | || default_arch[6] != '\0') | |
2930 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2931 | return bfd_mach_k1om; | |
2932 | } | |
351f65ca | 2933 | else if (default_arch[6] == '\0') |
8a9036a4 | 2934 | return bfd_mach_x86_64; |
351f65ca L |
2935 | else |
2936 | return bfd_mach_x64_32; | |
8a9036a4 | 2937 | } |
5197d474 L |
2938 | else if (!strcmp (default_arch, "i386") |
2939 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2940 | { |
2941 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2942 | { | |
2943 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2944 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2945 | return bfd_mach_i386_iamcu; | |
2946 | } | |
2947 | else | |
2948 | return bfd_mach_i386_i386; | |
2949 | } | |
b9d79e03 | 2950 | else |
2b5d6a91 | 2951 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2952 | } |
b9d79e03 | 2953 | \f |
252b5132 | 2954 | void |
7016a5d5 | 2955 | md_begin (void) |
252b5132 RH |
2956 | { |
2957 | const char *hash_err; | |
2958 | ||
86fa6981 L |
2959 | /* Support pseudo prefixes like {disp32}. */ |
2960 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2961 | ||
47926f60 | 2962 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2963 | op_hash = hash_new (); |
2964 | ||
2965 | { | |
d3ce72d0 | 2966 | const insn_template *optab; |
29b0f896 | 2967 | templates *core_optab; |
252b5132 | 2968 | |
47926f60 KH |
2969 | /* Setup for loop. */ |
2970 | optab = i386_optab; | |
add39d23 | 2971 | core_optab = XNEW (templates); |
252b5132 RH |
2972 | core_optab->start = optab; |
2973 | ||
2974 | while (1) | |
2975 | { | |
2976 | ++optab; | |
2977 | if (optab->name == NULL | |
2978 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2979 | { | |
2980 | /* different name --> ship out current template list; | |
47926f60 | 2981 | add to hash table; & begin anew. */ |
252b5132 RH |
2982 | core_optab->end = optab; |
2983 | hash_err = hash_insert (op_hash, | |
2984 | (optab - 1)->name, | |
5a49b8ac | 2985 | (void *) core_optab); |
252b5132 RH |
2986 | if (hash_err) |
2987 | { | |
b37df7c4 | 2988 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
2989 | (optab - 1)->name, |
2990 | hash_err); | |
2991 | } | |
2992 | if (optab->name == NULL) | |
2993 | break; | |
add39d23 | 2994 | core_optab = XNEW (templates); |
252b5132 RH |
2995 | core_optab->start = optab; |
2996 | } | |
2997 | } | |
2998 | } | |
2999 | ||
47926f60 | 3000 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
3001 | reg_hash = hash_new (); |
3002 | { | |
29b0f896 | 3003 | const reg_entry *regtab; |
c3fe08fa | 3004 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 3005 | |
c3fe08fa | 3006 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 3007 | { |
5a49b8ac | 3008 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 3009 | if (hash_err) |
b37df7c4 | 3010 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
3011 | regtab->reg_name, |
3012 | hash_err); | |
252b5132 RH |
3013 | } |
3014 | } | |
3015 | ||
47926f60 | 3016 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 3017 | { |
29b0f896 AM |
3018 | int c; |
3019 | char *p; | |
252b5132 RH |
3020 | |
3021 | for (c = 0; c < 256; c++) | |
3022 | { | |
3882b010 | 3023 | if (ISDIGIT (c)) |
252b5132 RH |
3024 | { |
3025 | digit_chars[c] = c; | |
3026 | mnemonic_chars[c] = c; | |
3027 | register_chars[c] = c; | |
3028 | operand_chars[c] = c; | |
3029 | } | |
3882b010 | 3030 | else if (ISLOWER (c)) |
252b5132 RH |
3031 | { |
3032 | mnemonic_chars[c] = c; | |
3033 | register_chars[c] = c; | |
3034 | operand_chars[c] = c; | |
3035 | } | |
3882b010 | 3036 | else if (ISUPPER (c)) |
252b5132 | 3037 | { |
3882b010 | 3038 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
3039 | register_chars[c] = mnemonic_chars[c]; |
3040 | operand_chars[c] = c; | |
3041 | } | |
43234a1e | 3042 | else if (c == '{' || c == '}') |
86fa6981 L |
3043 | { |
3044 | mnemonic_chars[c] = c; | |
3045 | operand_chars[c] = c; | |
3046 | } | |
252b5132 | 3047 | |
3882b010 | 3048 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
3049 | identifier_chars[c] = c; |
3050 | else if (c >= 128) | |
3051 | { | |
3052 | identifier_chars[c] = c; | |
3053 | operand_chars[c] = c; | |
3054 | } | |
3055 | } | |
3056 | ||
3057 | #ifdef LEX_AT | |
3058 | identifier_chars['@'] = '@'; | |
32137342 NC |
3059 | #endif |
3060 | #ifdef LEX_QM | |
3061 | identifier_chars['?'] = '?'; | |
3062 | operand_chars['?'] = '?'; | |
252b5132 | 3063 | #endif |
252b5132 | 3064 | digit_chars['-'] = '-'; |
c0f3af97 | 3065 | mnemonic_chars['_'] = '_'; |
791fe849 | 3066 | mnemonic_chars['-'] = '-'; |
0003779b | 3067 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
3068 | identifier_chars['_'] = '_'; |
3069 | identifier_chars['.'] = '.'; | |
3070 | ||
3071 | for (p = operand_special_chars; *p != '\0'; p++) | |
3072 | operand_chars[(unsigned char) *p] = *p; | |
3073 | } | |
3074 | ||
a4447b93 RH |
3075 | if (flag_code == CODE_64BIT) |
3076 | { | |
ca19b261 KT |
3077 | #if defined (OBJ_COFF) && defined (TE_PE) |
3078 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3079 | ? 32 : 16); | |
3080 | #else | |
a4447b93 | 3081 | x86_dwarf2_return_column = 16; |
ca19b261 | 3082 | #endif |
61ff971f | 3083 | x86_cie_data_alignment = -8; |
a4447b93 RH |
3084 | } |
3085 | else | |
3086 | { | |
3087 | x86_dwarf2_return_column = 8; | |
3088 | x86_cie_data_alignment = -4; | |
3089 | } | |
e379e5f3 L |
3090 | |
3091 | /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it | |
3092 | can be turned into BRANCH_PREFIX frag. */ | |
3093 | if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE) | |
3094 | abort (); | |
252b5132 RH |
3095 | } |
3096 | ||
3097 | void | |
e3bb37b5 | 3098 | i386_print_statistics (FILE *file) |
252b5132 RH |
3099 | { |
3100 | hash_print_statistics (file, "i386 opcode", op_hash); | |
3101 | hash_print_statistics (file, "i386 register", reg_hash); | |
3102 | } | |
3103 | \f | |
252b5132 RH |
3104 | #ifdef DEBUG386 |
3105 | ||
ce8a8b2f | 3106 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 3107 | static void pte (insn_template *); |
40fb9820 | 3108 | static void pt (i386_operand_type); |
e3bb37b5 L |
3109 | static void pe (expressionS *); |
3110 | static void ps (symbolS *); | |
252b5132 RH |
3111 | |
3112 | static void | |
2c703856 | 3113 | pi (const char *line, i386_insn *x) |
252b5132 | 3114 | { |
09137c09 | 3115 | unsigned int j; |
252b5132 RH |
3116 | |
3117 | fprintf (stdout, "%s: template ", line); | |
3118 | pte (&x->tm); | |
09f131f2 JH |
3119 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3120 | x->base_reg ? x->base_reg->reg_name : "none", | |
3121 | x->index_reg ? x->index_reg->reg_name : "none", | |
3122 | x->log2_scale_factor); | |
3123 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3124 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3125 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3126 | x->sib.base, x->sib.index, x->sib.scale); | |
3127 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3128 | (x->rex & REX_W) != 0, |
3129 | (x->rex & REX_R) != 0, | |
3130 | (x->rex & REX_X) != 0, | |
3131 | (x->rex & REX_B) != 0); | |
09137c09 | 3132 | for (j = 0; j < x->operands; j++) |
252b5132 | 3133 | { |
09137c09 SP |
3134 | fprintf (stdout, " #%d: ", j + 1); |
3135 | pt (x->types[j]); | |
252b5132 | 3136 | fprintf (stdout, "\n"); |
bab6aec1 | 3137 | if (x->types[j].bitfield.class == Reg |
3528c362 JB |
3138 | || x->types[j].bitfield.class == RegMMX |
3139 | || x->types[j].bitfield.class == RegSIMD | |
00cee14f | 3140 | || x->types[j].bitfield.class == SReg |
4a5c67ed JB |
3141 | || x->types[j].bitfield.class == RegCR |
3142 | || x->types[j].bitfield.class == RegDR | |
3143 | || x->types[j].bitfield.class == RegTR) | |
09137c09 SP |
3144 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
3145 | if (operand_type_check (x->types[j], imm)) | |
3146 | pe (x->op[j].imms); | |
3147 | if (operand_type_check (x->types[j], disp)) | |
3148 | pe (x->op[j].disps); | |
252b5132 RH |
3149 | } |
3150 | } | |
3151 | ||
3152 | static void | |
d3ce72d0 | 3153 | pte (insn_template *t) |
252b5132 | 3154 | { |
09137c09 | 3155 | unsigned int j; |
252b5132 | 3156 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 3157 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3158 | if (t->extension_opcode != None) |
3159 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3160 | if (t->opcode_modifier.d) |
252b5132 | 3161 | fprintf (stdout, "D"); |
40fb9820 | 3162 | if (t->opcode_modifier.w) |
252b5132 RH |
3163 | fprintf (stdout, "W"); |
3164 | fprintf (stdout, "\n"); | |
09137c09 | 3165 | for (j = 0; j < t->operands; j++) |
252b5132 | 3166 | { |
09137c09 SP |
3167 | fprintf (stdout, " #%d type ", j + 1); |
3168 | pt (t->operand_types[j]); | |
252b5132 RH |
3169 | fprintf (stdout, "\n"); |
3170 | } | |
3171 | } | |
3172 | ||
3173 | static void | |
e3bb37b5 | 3174 | pe (expressionS *e) |
252b5132 | 3175 | { |
24eab124 | 3176 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
3177 | fprintf (stdout, " add_number %ld (%lx)\n", |
3178 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
3179 | if (e->X_add_symbol) |
3180 | { | |
3181 | fprintf (stdout, " add_symbol "); | |
3182 | ps (e->X_add_symbol); | |
3183 | fprintf (stdout, "\n"); | |
3184 | } | |
3185 | if (e->X_op_symbol) | |
3186 | { | |
3187 | fprintf (stdout, " op_symbol "); | |
3188 | ps (e->X_op_symbol); | |
3189 | fprintf (stdout, "\n"); | |
3190 | } | |
3191 | } | |
3192 | ||
3193 | static void | |
e3bb37b5 | 3194 | ps (symbolS *s) |
252b5132 RH |
3195 | { |
3196 | fprintf (stdout, "%s type %s%s", | |
3197 | S_GET_NAME (s), | |
3198 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3199 | segment_name (S_GET_SEGMENT (s))); | |
3200 | } | |
3201 | ||
7b81dfbb | 3202 | static struct type_name |
252b5132 | 3203 | { |
40fb9820 L |
3204 | i386_operand_type mask; |
3205 | const char *name; | |
252b5132 | 3206 | } |
7b81dfbb | 3207 | const type_names[] = |
252b5132 | 3208 | { |
40fb9820 L |
3209 | { OPERAND_TYPE_REG8, "r8" }, |
3210 | { OPERAND_TYPE_REG16, "r16" }, | |
3211 | { OPERAND_TYPE_REG32, "r32" }, | |
3212 | { OPERAND_TYPE_REG64, "r64" }, | |
2c703856 JB |
3213 | { OPERAND_TYPE_ACC8, "acc8" }, |
3214 | { OPERAND_TYPE_ACC16, "acc16" }, | |
3215 | { OPERAND_TYPE_ACC32, "acc32" }, | |
3216 | { OPERAND_TYPE_ACC64, "acc64" }, | |
40fb9820 L |
3217 | { OPERAND_TYPE_IMM8, "i8" }, |
3218 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3219 | { OPERAND_TYPE_IMM16, "i16" }, | |
3220 | { OPERAND_TYPE_IMM32, "i32" }, | |
3221 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3222 | { OPERAND_TYPE_IMM64, "i64" }, | |
3223 | { OPERAND_TYPE_IMM1, "i1" }, | |
3224 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3225 | { OPERAND_TYPE_DISP8, "d8" }, | |
3226 | { OPERAND_TYPE_DISP16, "d16" }, | |
3227 | { OPERAND_TYPE_DISP32, "d32" }, | |
3228 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3229 | { OPERAND_TYPE_DISP64, "d64" }, | |
3230 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3231 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3232 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3233 | { OPERAND_TYPE_TEST, "test reg" }, | |
3234 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3235 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3236 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
21df382b | 3237 | { OPERAND_TYPE_SREG, "SReg" }, |
40fb9820 L |
3238 | { OPERAND_TYPE_REGMMX, "rMMX" }, |
3239 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3240 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
3241 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
3242 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
252b5132 RH |
3243 | }; |
3244 | ||
3245 | static void | |
40fb9820 | 3246 | pt (i386_operand_type t) |
252b5132 | 3247 | { |
40fb9820 | 3248 | unsigned int j; |
c6fb90c8 | 3249 | i386_operand_type a; |
252b5132 | 3250 | |
40fb9820 | 3251 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3252 | { |
3253 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3254 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3255 | fprintf (stdout, "%s, ", type_names[j].name); |
3256 | } | |
252b5132 RH |
3257 | fflush (stdout); |
3258 | } | |
3259 | ||
3260 | #endif /* DEBUG386 */ | |
3261 | \f | |
252b5132 | 3262 | static bfd_reloc_code_real_type |
3956db08 | 3263 | reloc (unsigned int size, |
64e74474 AM |
3264 | int pcrel, |
3265 | int sign, | |
3266 | bfd_reloc_code_real_type other) | |
252b5132 | 3267 | { |
47926f60 | 3268 | if (other != NO_RELOC) |
3956db08 | 3269 | { |
91d6fa6a | 3270 | reloc_howto_type *rel; |
3956db08 JB |
3271 | |
3272 | if (size == 8) | |
3273 | switch (other) | |
3274 | { | |
64e74474 AM |
3275 | case BFD_RELOC_X86_64_GOT32: |
3276 | return BFD_RELOC_X86_64_GOT64; | |
3277 | break; | |
553d1284 L |
3278 | case BFD_RELOC_X86_64_GOTPLT64: |
3279 | return BFD_RELOC_X86_64_GOTPLT64; | |
3280 | break; | |
64e74474 AM |
3281 | case BFD_RELOC_X86_64_PLTOFF64: |
3282 | return BFD_RELOC_X86_64_PLTOFF64; | |
3283 | break; | |
3284 | case BFD_RELOC_X86_64_GOTPC32: | |
3285 | other = BFD_RELOC_X86_64_GOTPC64; | |
3286 | break; | |
3287 | case BFD_RELOC_X86_64_GOTPCREL: | |
3288 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3289 | break; | |
3290 | case BFD_RELOC_X86_64_TPOFF32: | |
3291 | other = BFD_RELOC_X86_64_TPOFF64; | |
3292 | break; | |
3293 | case BFD_RELOC_X86_64_DTPOFF32: | |
3294 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3295 | break; | |
3296 | default: | |
3297 | break; | |
3956db08 | 3298 | } |
e05278af | 3299 | |
8ce3d284 | 3300 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3301 | if (other == BFD_RELOC_SIZE32) |
3302 | { | |
3303 | if (size == 8) | |
1ab668bf | 3304 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3305 | if (pcrel) |
1ab668bf AM |
3306 | { |
3307 | as_bad (_("there are no pc-relative size relocations")); | |
3308 | return NO_RELOC; | |
3309 | } | |
8fd4256d | 3310 | } |
8ce3d284 | 3311 | #endif |
8fd4256d | 3312 | |
e05278af | 3313 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3314 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3315 | sign = -1; |
3316 | ||
91d6fa6a NC |
3317 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3318 | if (!rel) | |
3956db08 | 3319 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3320 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3321 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3322 | bfd_get_reloc_size (rel), |
3956db08 | 3323 | size); |
91d6fa6a | 3324 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3325 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3326 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3327 | && !sign) |
91d6fa6a | 3328 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3329 | && sign > 0)) |
3956db08 JB |
3330 | as_bad (_("relocated field and relocation type differ in signedness")); |
3331 | else | |
3332 | return other; | |
3333 | return NO_RELOC; | |
3334 | } | |
252b5132 RH |
3335 | |
3336 | if (pcrel) | |
3337 | { | |
3e73aa7c | 3338 | if (!sign) |
3956db08 | 3339 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3340 | switch (size) |
3341 | { | |
3342 | case 1: return BFD_RELOC_8_PCREL; | |
3343 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3344 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3345 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3346 | } |
3956db08 | 3347 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3348 | } |
3349 | else | |
3350 | { | |
3956db08 | 3351 | if (sign > 0) |
e5cb08ac | 3352 | switch (size) |
3e73aa7c JH |
3353 | { |
3354 | case 4: return BFD_RELOC_X86_64_32S; | |
3355 | } | |
3356 | else | |
3357 | switch (size) | |
3358 | { | |
3359 | case 1: return BFD_RELOC_8; | |
3360 | case 2: return BFD_RELOC_16; | |
3361 | case 4: return BFD_RELOC_32; | |
3362 | case 8: return BFD_RELOC_64; | |
3363 | } | |
3956db08 JB |
3364 | as_bad (_("cannot do %s %u byte relocation"), |
3365 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3366 | } |
3367 | ||
0cc9e1d3 | 3368 | return NO_RELOC; |
252b5132 RH |
3369 | } |
3370 | ||
47926f60 KH |
3371 | /* Here we decide which fixups can be adjusted to make them relative to |
3372 | the beginning of the section instead of the symbol. Basically we need | |
3373 | to make sure that the dynamic relocations are done correctly, so in | |
3374 | some cases we force the original symbol to be used. */ | |
3375 | ||
252b5132 | 3376 | int |
e3bb37b5 | 3377 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3378 | { |
6d249963 | 3379 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3380 | if (!IS_ELF) |
31312f95 AM |
3381 | return 1; |
3382 | ||
a161fe53 AM |
3383 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3384 | mode. */ | |
3385 | if (use_rela_relocations | |
3386 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3387 | && fixP->fx_pcrel) | |
252b5132 | 3388 | return 0; |
31312f95 | 3389 | |
8d01d9a9 AJ |
3390 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3391 | and changed later by validate_fix. */ | |
3392 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3393 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3394 | return 0; | |
3395 | ||
8fd4256d L |
3396 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3397 | for size relocations. */ | |
3398 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3399 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3400 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 RH |
3401 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
3402 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
02a86693 | 3403 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3404 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3405 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3406 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3407 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3408 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3409 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3410 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3411 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3412 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3413 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
3414 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
3415 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 3416 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3417 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3418 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3419 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3420 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3421 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3422 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3423 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3424 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3425 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3426 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3427 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3428 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3429 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3430 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3431 | return 0; | |
31312f95 | 3432 | #endif |
252b5132 RH |
3433 | return 1; |
3434 | } | |
252b5132 | 3435 | |
b4cac588 | 3436 | static int |
e3bb37b5 | 3437 | intel_float_operand (const char *mnemonic) |
252b5132 | 3438 | { |
9306ca4a JB |
3439 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3440 | operands, hence the code here is free to improperly handle opcodes that | |
3441 | have no operands (for better performance and smaller code). */ | |
3442 | ||
3443 | if (mnemonic[0] != 'f') | |
3444 | return 0; /* non-math */ | |
3445 | ||
3446 | switch (mnemonic[1]) | |
3447 | { | |
3448 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3449 | the fs segment override prefix not currently handled because no | |
3450 | call path can make opcodes without operands get here */ | |
3451 | case 'i': | |
3452 | return 2 /* integer op */; | |
3453 | case 'l': | |
3454 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3455 | return 3; /* fldcw/fldenv */ | |
3456 | break; | |
3457 | case 'n': | |
3458 | if (mnemonic[2] != 'o' /* fnop */) | |
3459 | return 3; /* non-waiting control op */ | |
3460 | break; | |
3461 | case 'r': | |
3462 | if (mnemonic[2] == 's') | |
3463 | return 3; /* frstor/frstpm */ | |
3464 | break; | |
3465 | case 's': | |
3466 | if (mnemonic[2] == 'a') | |
3467 | return 3; /* fsave */ | |
3468 | if (mnemonic[2] == 't') | |
3469 | { | |
3470 | switch (mnemonic[3]) | |
3471 | { | |
3472 | case 'c': /* fstcw */ | |
3473 | case 'd': /* fstdw */ | |
3474 | case 'e': /* fstenv */ | |
3475 | case 's': /* fsts[gw] */ | |
3476 | return 3; | |
3477 | } | |
3478 | } | |
3479 | break; | |
3480 | case 'x': | |
3481 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3482 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3483 | break; | |
3484 | } | |
252b5132 | 3485 | |
9306ca4a | 3486 | return 1; |
252b5132 RH |
3487 | } |
3488 | ||
c0f3af97 L |
3489 | /* Build the VEX prefix. */ |
3490 | ||
3491 | static void | |
d3ce72d0 | 3492 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3493 | { |
3494 | unsigned int register_specifier; | |
3495 | unsigned int implied_prefix; | |
3496 | unsigned int vector_length; | |
03751133 | 3497 | unsigned int w; |
c0f3af97 L |
3498 | |
3499 | /* Check register specifier. */ | |
3500 | if (i.vex.register_specifier) | |
43234a1e L |
3501 | { |
3502 | register_specifier = | |
3503 | ~register_number (i.vex.register_specifier) & 0xf; | |
3504 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3505 | } | |
c0f3af97 L |
3506 | else |
3507 | register_specifier = 0xf; | |
3508 | ||
79f0fa25 L |
3509 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3510 | if there are more than 1 register operand. */ | |
3511 | if (i.reg_operands > 1 | |
3512 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3513 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3514 | && i.operands == i.reg_operands |
dbbc8b7e | 3515 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
7f399153 | 3516 | && i.tm.opcode_modifier.vexopcode == VEX0F |
dbbc8b7e | 3517 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3518 | && i.rex == REX_B) |
3519 | { | |
3520 | unsigned int xchg = i.operands - 1; | |
3521 | union i386_op temp_op; | |
3522 | i386_operand_type temp_type; | |
3523 | ||
3524 | temp_type = i.types[xchg]; | |
3525 | i.types[xchg] = i.types[0]; | |
3526 | i.types[0] = temp_type; | |
3527 | temp_op = i.op[xchg]; | |
3528 | i.op[xchg] = i.op[0]; | |
3529 | i.op[0] = temp_op; | |
3530 | ||
9c2799c2 | 3531 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3532 | |
3533 | i.rex = REX_R; | |
3534 | xchg = i.rm.regmem; | |
3535 | i.rm.regmem = i.rm.reg; | |
3536 | i.rm.reg = xchg; | |
3537 | ||
dbbc8b7e JB |
3538 | if (i.tm.opcode_modifier.d) |
3539 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
3540 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
3541 | else /* Use the next insn. */ | |
3542 | i.tm = t[1]; | |
fa99fab2 L |
3543 | } |
3544 | ||
79dec6b7 JB |
3545 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
3546 | are no memory operands and at least 3 register ones. */ | |
3547 | if (i.reg_operands >= 3 | |
3548 | && i.vec_encoding != vex_encoding_vex3 | |
3549 | && i.reg_operands == i.operands - i.imm_operands | |
3550 | && i.tm.opcode_modifier.vex | |
3551 | && i.tm.opcode_modifier.commutative | |
3552 | && (i.tm.opcode_modifier.sse2avx || optimize > 1) | |
3553 | && i.rex == REX_B | |
3554 | && i.vex.register_specifier | |
3555 | && !(i.vex.register_specifier->reg_flags & RegRex)) | |
3556 | { | |
3557 | unsigned int xchg = i.operands - i.reg_operands; | |
3558 | union i386_op temp_op; | |
3559 | i386_operand_type temp_type; | |
3560 | ||
3561 | gas_assert (i.tm.opcode_modifier.vexopcode == VEX0F); | |
3562 | gas_assert (!i.tm.opcode_modifier.sae); | |
3563 | gas_assert (operand_type_equal (&i.types[i.operands - 2], | |
3564 | &i.types[i.operands - 3])); | |
3565 | gas_assert (i.rm.mode == 3); | |
3566 | ||
3567 | temp_type = i.types[xchg]; | |
3568 | i.types[xchg] = i.types[xchg + 1]; | |
3569 | i.types[xchg + 1] = temp_type; | |
3570 | temp_op = i.op[xchg]; | |
3571 | i.op[xchg] = i.op[xchg + 1]; | |
3572 | i.op[xchg + 1] = temp_op; | |
3573 | ||
3574 | i.rex = 0; | |
3575 | xchg = i.rm.regmem | 8; | |
3576 | i.rm.regmem = ~register_specifier & 0xf; | |
3577 | gas_assert (!(i.rm.regmem & 8)); | |
3578 | i.vex.register_specifier += xchg - i.rm.regmem; | |
3579 | register_specifier = ~xchg & 0xf; | |
3580 | } | |
3581 | ||
539f890d L |
3582 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3583 | vector_length = avxscalar; | |
10c17abd JB |
3584 | else if (i.tm.opcode_modifier.vex == VEX256) |
3585 | vector_length = 1; | |
539f890d | 3586 | else |
10c17abd | 3587 | { |
56522fc5 | 3588 | unsigned int op; |
10c17abd | 3589 | |
c7213af9 L |
3590 | /* Determine vector length from the last multi-length vector |
3591 | operand. */ | |
10c17abd | 3592 | vector_length = 0; |
56522fc5 | 3593 | for (op = t->operands; op--;) |
10c17abd JB |
3594 | if (t->operand_types[op].bitfield.xmmword |
3595 | && t->operand_types[op].bitfield.ymmword | |
3596 | && i.types[op].bitfield.ymmword) | |
3597 | { | |
3598 | vector_length = 1; | |
3599 | break; | |
3600 | } | |
3601 | } | |
c0f3af97 L |
3602 | |
3603 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3604 | { | |
3605 | case 0: | |
3606 | implied_prefix = 0; | |
3607 | break; | |
3608 | case DATA_PREFIX_OPCODE: | |
3609 | implied_prefix = 1; | |
3610 | break; | |
3611 | case REPE_PREFIX_OPCODE: | |
3612 | implied_prefix = 2; | |
3613 | break; | |
3614 | case REPNE_PREFIX_OPCODE: | |
3615 | implied_prefix = 3; | |
3616 | break; | |
3617 | default: | |
3618 | abort (); | |
3619 | } | |
3620 | ||
03751133 L |
3621 | /* Check the REX.W bit and VEXW. */ |
3622 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3623 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3624 | else if (i.tm.opcode_modifier.vexw) | |
3625 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3626 | else | |
931d03b7 | 3627 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3628 | |
c0f3af97 | 3629 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3630 | if (w == 0 |
3631 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3632 | && i.tm.opcode_modifier.vexopcode == VEX0F |
c0f3af97 L |
3633 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3634 | { | |
3635 | /* 2-byte VEX prefix. */ | |
3636 | unsigned int r; | |
3637 | ||
3638 | i.vex.length = 2; | |
3639 | i.vex.bytes[0] = 0xc5; | |
3640 | ||
3641 | /* Check the REX.R bit. */ | |
3642 | r = (i.rex & REX_R) ? 0 : 1; | |
3643 | i.vex.bytes[1] = (r << 7 | |
3644 | | register_specifier << 3 | |
3645 | | vector_length << 2 | |
3646 | | implied_prefix); | |
3647 | } | |
3648 | else | |
3649 | { | |
3650 | /* 3-byte VEX prefix. */ | |
03751133 | 3651 | unsigned int m; |
c0f3af97 | 3652 | |
f88c9eb0 | 3653 | i.vex.length = 3; |
f88c9eb0 | 3654 | |
7f399153 | 3655 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3656 | { |
7f399153 L |
3657 | case VEX0F: |
3658 | m = 0x1; | |
80de6e00 | 3659 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3660 | break; |
3661 | case VEX0F38: | |
3662 | m = 0x2; | |
80de6e00 | 3663 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3664 | break; |
3665 | case VEX0F3A: | |
3666 | m = 0x3; | |
80de6e00 | 3667 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3668 | break; |
3669 | case XOP08: | |
5dd85c99 SP |
3670 | m = 0x8; |
3671 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3672 | break; |
3673 | case XOP09: | |
f88c9eb0 SP |
3674 | m = 0x9; |
3675 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3676 | break; |
3677 | case XOP0A: | |
f88c9eb0 SP |
3678 | m = 0xa; |
3679 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3680 | break; |
3681 | default: | |
3682 | abort (); | |
f88c9eb0 | 3683 | } |
c0f3af97 | 3684 | |
c0f3af97 L |
3685 | /* The high 3 bits of the second VEX byte are 1's compliment |
3686 | of RXB bits from REX. */ | |
3687 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3688 | ||
c0f3af97 L |
3689 | i.vex.bytes[2] = (w << 7 |
3690 | | register_specifier << 3 | |
3691 | | vector_length << 2 | |
3692 | | implied_prefix); | |
3693 | } | |
3694 | } | |
3695 | ||
e771e7c9 JB |
3696 | static INLINE bfd_boolean |
3697 | is_evex_encoding (const insn_template *t) | |
3698 | { | |
7091c612 | 3699 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 | 3700 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
a80195f1 | 3701 | || t->opcode_modifier.sae; |
e771e7c9 JB |
3702 | } |
3703 | ||
7a8655d2 JB |
3704 | static INLINE bfd_boolean |
3705 | is_any_vex_encoding (const insn_template *t) | |
3706 | { | |
3707 | return t->opcode_modifier.vex || t->opcode_modifier.vexopcode | |
3708 | || is_evex_encoding (t); | |
3709 | } | |
3710 | ||
43234a1e L |
3711 | /* Build the EVEX prefix. */ |
3712 | ||
3713 | static void | |
3714 | build_evex_prefix (void) | |
3715 | { | |
3716 | unsigned int register_specifier; | |
3717 | unsigned int implied_prefix; | |
3718 | unsigned int m, w; | |
3719 | rex_byte vrex_used = 0; | |
3720 | ||
3721 | /* Check register specifier. */ | |
3722 | if (i.vex.register_specifier) | |
3723 | { | |
3724 | gas_assert ((i.vrex & REX_X) == 0); | |
3725 | ||
3726 | register_specifier = i.vex.register_specifier->reg_num; | |
3727 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3728 | register_specifier += 8; | |
3729 | /* The upper 16 registers are encoded in the fourth byte of the | |
3730 | EVEX prefix. */ | |
3731 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3732 | i.vex.bytes[3] = 0x8; | |
3733 | register_specifier = ~register_specifier & 0xf; | |
3734 | } | |
3735 | else | |
3736 | { | |
3737 | register_specifier = 0xf; | |
3738 | ||
3739 | /* Encode upper 16 vector index register in the fourth byte of | |
3740 | the EVEX prefix. */ | |
3741 | if (!(i.vrex & REX_X)) | |
3742 | i.vex.bytes[3] = 0x8; | |
3743 | else | |
3744 | vrex_used |= REX_X; | |
3745 | } | |
3746 | ||
3747 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3748 | { | |
3749 | case 0: | |
3750 | implied_prefix = 0; | |
3751 | break; | |
3752 | case DATA_PREFIX_OPCODE: | |
3753 | implied_prefix = 1; | |
3754 | break; | |
3755 | case REPE_PREFIX_OPCODE: | |
3756 | implied_prefix = 2; | |
3757 | break; | |
3758 | case REPNE_PREFIX_OPCODE: | |
3759 | implied_prefix = 3; | |
3760 | break; | |
3761 | default: | |
3762 | abort (); | |
3763 | } | |
3764 | ||
3765 | /* 4 byte EVEX prefix. */ | |
3766 | i.vex.length = 4; | |
3767 | i.vex.bytes[0] = 0x62; | |
3768 | ||
3769 | /* mmmm bits. */ | |
3770 | switch (i.tm.opcode_modifier.vexopcode) | |
3771 | { | |
3772 | case VEX0F: | |
3773 | m = 1; | |
3774 | break; | |
3775 | case VEX0F38: | |
3776 | m = 2; | |
3777 | break; | |
3778 | case VEX0F3A: | |
3779 | m = 3; | |
3780 | break; | |
3781 | default: | |
3782 | abort (); | |
3783 | break; | |
3784 | } | |
3785 | ||
3786 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3787 | bits from REX. */ | |
3788 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3789 | ||
3790 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3791 | REX_R bit in VREX. */ | |
3792 | if (!(i.vrex & REX_R)) | |
3793 | i.vex.bytes[1] |= 0x10; | |
3794 | else | |
3795 | vrex_used |= REX_R; | |
3796 | ||
3797 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3798 | { | |
3799 | /* When all operands are registers, the REX_X bit in REX is not | |
3800 | used. We reuse it to encode the upper 16 registers, which is | |
3801 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3802 | as 1's compliment. */ | |
3803 | if ((i.vrex & REX_B)) | |
3804 | { | |
3805 | vrex_used |= REX_B; | |
3806 | i.vex.bytes[1] &= ~0x40; | |
3807 | } | |
3808 | } | |
3809 | ||
3810 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3811 | i.vrex &= ~vrex_used; | |
3812 | gas_assert (i.vrex == 0); | |
3813 | ||
6865c043 L |
3814 | /* Check the REX.W bit and VEXW. */ |
3815 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3816 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3817 | else if (i.tm.opcode_modifier.vexw) | |
3818 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3819 | else | |
931d03b7 | 3820 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e L |
3821 | |
3822 | /* Encode the U bit. */ | |
3823 | implied_prefix |= 0x4; | |
3824 | ||
3825 | /* The third byte of the EVEX prefix. */ | |
3826 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3827 | ||
3828 | /* The fourth byte of the EVEX prefix. */ | |
3829 | /* The zeroing-masking bit. */ | |
3830 | if (i.mask && i.mask->zeroing) | |
3831 | i.vex.bytes[3] |= 0x80; | |
3832 | ||
3833 | /* Don't always set the broadcast bit if there is no RC. */ | |
3834 | if (!i.rounding) | |
3835 | { | |
3836 | /* Encode the vector length. */ | |
3837 | unsigned int vec_length; | |
3838 | ||
e771e7c9 JB |
3839 | if (!i.tm.opcode_modifier.evex |
3840 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3841 | { | |
56522fc5 | 3842 | unsigned int op; |
e771e7c9 | 3843 | |
c7213af9 L |
3844 | /* Determine vector length from the last multi-length vector |
3845 | operand. */ | |
e771e7c9 | 3846 | vec_length = 0; |
56522fc5 | 3847 | for (op = i.operands; op--;) |
e771e7c9 JB |
3848 | if (i.tm.operand_types[op].bitfield.xmmword |
3849 | + i.tm.operand_types[op].bitfield.ymmword | |
3850 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3851 | { | |
3852 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3853 | { |
3854 | i.tm.opcode_modifier.evex = EVEX512; | |
3855 | break; | |
3856 | } | |
e771e7c9 | 3857 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3858 | { |
3859 | i.tm.opcode_modifier.evex = EVEX256; | |
3860 | break; | |
3861 | } | |
e771e7c9 | 3862 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3863 | { |
3864 | i.tm.opcode_modifier.evex = EVEX128; | |
3865 | break; | |
3866 | } | |
625cbd7a JB |
3867 | else if (i.broadcast && (int) op == i.broadcast->operand) |
3868 | { | |
4a1b91ea | 3869 | switch (i.broadcast->bytes) |
625cbd7a JB |
3870 | { |
3871 | case 64: | |
3872 | i.tm.opcode_modifier.evex = EVEX512; | |
3873 | break; | |
3874 | case 32: | |
3875 | i.tm.opcode_modifier.evex = EVEX256; | |
3876 | break; | |
3877 | case 16: | |
3878 | i.tm.opcode_modifier.evex = EVEX128; | |
3879 | break; | |
3880 | default: | |
c7213af9 | 3881 | abort (); |
625cbd7a | 3882 | } |
c7213af9 | 3883 | break; |
625cbd7a | 3884 | } |
e771e7c9 | 3885 | } |
c7213af9 | 3886 | |
56522fc5 | 3887 | if (op >= MAX_OPERANDS) |
c7213af9 | 3888 | abort (); |
e771e7c9 JB |
3889 | } |
3890 | ||
43234a1e L |
3891 | switch (i.tm.opcode_modifier.evex) |
3892 | { | |
3893 | case EVEXLIG: /* LL' is ignored */ | |
3894 | vec_length = evexlig << 5; | |
3895 | break; | |
3896 | case EVEX128: | |
3897 | vec_length = 0 << 5; | |
3898 | break; | |
3899 | case EVEX256: | |
3900 | vec_length = 1 << 5; | |
3901 | break; | |
3902 | case EVEX512: | |
3903 | vec_length = 2 << 5; | |
3904 | break; | |
3905 | default: | |
3906 | abort (); | |
3907 | break; | |
3908 | } | |
3909 | i.vex.bytes[3] |= vec_length; | |
3910 | /* Encode the broadcast bit. */ | |
3911 | if (i.broadcast) | |
3912 | i.vex.bytes[3] |= 0x10; | |
3913 | } | |
3914 | else | |
3915 | { | |
3916 | if (i.rounding->type != saeonly) | |
3917 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3918 | else | |
d3d3c6db | 3919 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3920 | } |
3921 | ||
3922 | if (i.mask && i.mask->mask) | |
3923 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3924 | } | |
3925 | ||
65da13b5 L |
3926 | static void |
3927 | process_immext (void) | |
3928 | { | |
3929 | expressionS *exp; | |
3930 | ||
c0f3af97 | 3931 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3932 | which is coded in the same place as an 8-bit immediate field |
3933 | would be. Here we fake an 8-bit immediate operand from the | |
3934 | opcode suffix stored in tm.extension_opcode. | |
3935 | ||
c1e679ec | 3936 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3937 | 3 argument instructions. */ |
65da13b5 | 3938 | |
43234a1e | 3939 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3940 | && (i.operands <= 2 |
7a8655d2 | 3941 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 3942 | && i.operands <= 4))); |
65da13b5 L |
3943 | |
3944 | exp = &im_expressions[i.imm_operands++]; | |
3945 | i.op[i.operands].imms = exp; | |
3946 | i.types[i.operands] = imm8; | |
3947 | i.operands++; | |
3948 | exp->X_op = O_constant; | |
3949 | exp->X_add_number = i.tm.extension_opcode; | |
3950 | i.tm.extension_opcode = None; | |
3951 | } | |
3952 | ||
42164a71 L |
3953 | |
3954 | static int | |
3955 | check_hle (void) | |
3956 | { | |
3957 | switch (i.tm.opcode_modifier.hleprefixok) | |
3958 | { | |
3959 | default: | |
3960 | abort (); | |
82c2def5 | 3961 | case HLEPrefixNone: |
165de32a L |
3962 | as_bad (_("invalid instruction `%s' after `%s'"), |
3963 | i.tm.name, i.hle_prefix); | |
42164a71 | 3964 | return 0; |
82c2def5 | 3965 | case HLEPrefixLock: |
42164a71 L |
3966 | if (i.prefix[LOCK_PREFIX]) |
3967 | return 1; | |
165de32a | 3968 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3969 | return 0; |
82c2def5 | 3970 | case HLEPrefixAny: |
42164a71 | 3971 | return 1; |
82c2def5 | 3972 | case HLEPrefixRelease: |
42164a71 L |
3973 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3974 | { | |
3975 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3976 | i.tm.name); | |
3977 | return 0; | |
3978 | } | |
8dc0818e | 3979 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
42164a71 L |
3980 | { |
3981 | as_bad (_("memory destination needed for instruction `%s'" | |
3982 | " after `xrelease'"), i.tm.name); | |
3983 | return 0; | |
3984 | } | |
3985 | return 1; | |
3986 | } | |
3987 | } | |
3988 | ||
b6f8c7c4 L |
3989 | /* Try the shortest encoding by shortening operand size. */ |
3990 | ||
3991 | static void | |
3992 | optimize_encoding (void) | |
3993 | { | |
a0a1771e | 3994 | unsigned int j; |
b6f8c7c4 L |
3995 | |
3996 | if (optimize_for_space | |
72aea328 | 3997 | && !is_any_vex_encoding (&i.tm) |
b6f8c7c4 L |
3998 | && i.reg_operands == 1 |
3999 | && i.imm_operands == 1 | |
4000 | && !i.types[1].bitfield.byte | |
4001 | && i.op[0].imms->X_op == O_constant | |
4002 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
72aea328 | 4003 | && (i.tm.base_opcode == 0xa8 |
b6f8c7c4 L |
4004 | || (i.tm.base_opcode == 0xf6 |
4005 | && i.tm.extension_opcode == 0x0))) | |
4006 | { | |
4007 | /* Optimize: -Os: | |
4008 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
4009 | */ | |
4010 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
4011 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
4012 | { | |
4013 | i.types[1].bitfield.byte = 1; | |
4014 | /* Ignore the suffix. */ | |
4015 | i.suffix = 0; | |
7697afb6 JB |
4016 | /* Convert to byte registers. */ |
4017 | if (i.types[1].bitfield.word) | |
4018 | j = 16; | |
4019 | else if (i.types[1].bitfield.dword) | |
4020 | j = 32; | |
4021 | else | |
4022 | j = 48; | |
4023 | if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4) | |
4024 | j += 8; | |
4025 | i.op[1].regs -= j; | |
b6f8c7c4 L |
4026 | } |
4027 | } | |
4028 | else if (flag_code == CODE_64BIT | |
72aea328 | 4029 | && !is_any_vex_encoding (&i.tm) |
d3d50934 L |
4030 | && ((i.types[1].bitfield.qword |
4031 | && i.reg_operands == 1 | |
b6f8c7c4 L |
4032 | && i.imm_operands == 1 |
4033 | && i.op[0].imms->X_op == O_constant | |
507916b8 | 4034 | && ((i.tm.base_opcode == 0xb8 |
b6f8c7c4 L |
4035 | && i.tm.extension_opcode == None |
4036 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
4037 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
72aea328 JB |
4038 | && ((i.tm.base_opcode == 0x24 |
4039 | || i.tm.base_opcode == 0xa8) | |
b6f8c7c4 L |
4040 | || (i.tm.base_opcode == 0x80 |
4041 | && i.tm.extension_opcode == 0x4) | |
4042 | || ((i.tm.base_opcode == 0xf6 | |
507916b8 | 4043 | || (i.tm.base_opcode | 1) == 0xc7) |
b8364fa7 JB |
4044 | && i.tm.extension_opcode == 0x0))) |
4045 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
4046 | && i.tm.base_opcode == 0x83 | |
4047 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
4048 | || (i.types[0].bitfield.qword |
4049 | && ((i.reg_operands == 2 | |
4050 | && i.op[0].regs == i.op[1].regs | |
72aea328 JB |
4051 | && (i.tm.base_opcode == 0x30 |
4052 | || i.tm.base_opcode == 0x28)) | |
d3d50934 L |
4053 | || (i.reg_operands == 1 |
4054 | && i.operands == 1 | |
72aea328 | 4055 | && i.tm.base_opcode == 0x30))))) |
b6f8c7c4 L |
4056 | { |
4057 | /* Optimize: -O: | |
4058 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 4059 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
4060 | testq $imm31, %r64 -> testl $imm31, %r32 |
4061 | xorq %r64, %r64 -> xorl %r32, %r32 | |
4062 | subq %r64, %r64 -> subl %r32, %r32 | |
4063 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4064 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4065 | */ | |
4066 | i.tm.opcode_modifier.norex64 = 1; | |
507916b8 | 4067 | if (i.tm.base_opcode == 0xb8 || (i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4068 | { |
4069 | /* Handle | |
4070 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4071 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4072 | */ | |
4073 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
4074 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
4075 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
4076 | i.types[0].bitfield.imm32 = 1; | |
4077 | i.types[0].bitfield.imm32s = 0; | |
4078 | i.types[0].bitfield.imm64 = 0; | |
4079 | i.types[1].bitfield.dword = 1; | |
4080 | i.types[1].bitfield.qword = 0; | |
507916b8 | 4081 | if ((i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4082 | { |
4083 | /* Handle | |
4084 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4085 | */ | |
507916b8 | 4086 | i.tm.base_opcode = 0xb8; |
b6f8c7c4 | 4087 | i.tm.extension_opcode = None; |
507916b8 | 4088 | i.tm.opcode_modifier.w = 0; |
b6f8c7c4 L |
4089 | i.tm.opcode_modifier.modrm = 0; |
4090 | } | |
4091 | } | |
4092 | } | |
5641ec01 JB |
4093 | else if (optimize > 1 |
4094 | && !optimize_for_space | |
72aea328 | 4095 | && !is_any_vex_encoding (&i.tm) |
5641ec01 JB |
4096 | && i.reg_operands == 2 |
4097 | && i.op[0].regs == i.op[1].regs | |
4098 | && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8 | |
4099 | || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20) | |
4100 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) | |
4101 | { | |
4102 | /* Optimize: -O2: | |
4103 | andb %rN, %rN -> testb %rN, %rN | |
4104 | andw %rN, %rN -> testw %rN, %rN | |
4105 | andq %rN, %rN -> testq %rN, %rN | |
4106 | orb %rN, %rN -> testb %rN, %rN | |
4107 | orw %rN, %rN -> testw %rN, %rN | |
4108 | orq %rN, %rN -> testq %rN, %rN | |
4109 | ||
4110 | and outside of 64-bit mode | |
4111 | ||
4112 | andl %rN, %rN -> testl %rN, %rN | |
4113 | orl %rN, %rN -> testl %rN, %rN | |
4114 | */ | |
4115 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); | |
4116 | } | |
99112332 | 4117 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4118 | && i.op[0].regs == i.op[1].regs |
4119 | && !i.types[2].bitfield.xmmword | |
4120 | && (i.tm.opcode_modifier.vex | |
7a69eac3 | 4121 | || ((!i.mask || i.mask->zeroing) |
b6f8c7c4 | 4122 | && !i.rounding |
e771e7c9 | 4123 | && is_evex_encoding (&i.tm) |
80c34c38 | 4124 | && (i.vec_encoding != vex_encoding_evex |
dd22218c | 4125 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
80c34c38 | 4126 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
7091c612 | 4127 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4128 | && i.types[2].bitfield.ymmword)))) |
b6f8c7c4 L |
4129 | && ((i.tm.base_opcode == 0x55 |
4130 | || i.tm.base_opcode == 0x6655 | |
4131 | || i.tm.base_opcode == 0x66df | |
4132 | || i.tm.base_opcode == 0x57 | |
4133 | || i.tm.base_opcode == 0x6657 | |
8305403a L |
4134 | || i.tm.base_opcode == 0x66ef |
4135 | || i.tm.base_opcode == 0x66f8 | |
4136 | || i.tm.base_opcode == 0x66f9 | |
4137 | || i.tm.base_opcode == 0x66fa | |
1424ad86 JB |
4138 | || i.tm.base_opcode == 0x66fb |
4139 | || i.tm.base_opcode == 0x42 | |
4140 | || i.tm.base_opcode == 0x6642 | |
4141 | || i.tm.base_opcode == 0x47 | |
4142 | || i.tm.base_opcode == 0x6647) | |
b6f8c7c4 L |
4143 | && i.tm.extension_opcode == None)) |
4144 | { | |
99112332 | 4145 | /* Optimize: -O1: |
8305403a L |
4146 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4147 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4148 | EVEX VOP %zmmM, %zmmM, %zmmN |
4149 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4150 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4151 | EVEX VOP %ymmM, %ymmM, %ymmN |
4152 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4153 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4154 | VEX VOP %ymmM, %ymmM, %ymmN |
4155 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4156 | VOP, one of vpandn and vpxor: | |
4157 | VEX VOP %ymmM, %ymmM, %ymmN | |
4158 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4159 | VOP, one of vpandnd and vpandnq: | |
4160 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4161 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4162 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4163 | EVEX VOP %ymmM, %ymmM, %ymmN |
4164 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4165 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4166 | VOP, one of vpxord and vpxorq: |
4167 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4168 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4169 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4170 | EVEX VOP %ymmM, %ymmM, %ymmN |
4171 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4172 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4173 | VOP, one of kxord and kxorq: |
4174 | VEX VOP %kM, %kM, %kN | |
4175 | -> VEX kxorw %kM, %kM, %kN | |
4176 | VOP, one of kandnd and kandnq: | |
4177 | VEX VOP %kM, %kM, %kN | |
4178 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4179 | */ |
e771e7c9 | 4180 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4181 | { |
7b1d7ca1 | 4182 | if (i.vec_encoding != vex_encoding_evex) |
b6f8c7c4 L |
4183 | { |
4184 | i.tm.opcode_modifier.vex = VEX128; | |
4185 | i.tm.opcode_modifier.vexw = VEXW0; | |
4186 | i.tm.opcode_modifier.evex = 0; | |
4187 | } | |
7b1d7ca1 | 4188 | else if (optimize > 1) |
dd22218c L |
4189 | i.tm.opcode_modifier.evex = EVEX128; |
4190 | else | |
4191 | return; | |
b6f8c7c4 | 4192 | } |
f74a6307 | 4193 | else if (i.tm.operand_types[0].bitfield.class == RegMask) |
1424ad86 JB |
4194 | { |
4195 | i.tm.base_opcode &= 0xff; | |
4196 | i.tm.opcode_modifier.vexw = VEXW0; | |
4197 | } | |
b6f8c7c4 L |
4198 | else |
4199 | i.tm.opcode_modifier.vex = VEX128; | |
4200 | ||
4201 | if (i.tm.opcode_modifier.vex) | |
4202 | for (j = 0; j < 3; j++) | |
4203 | { | |
4204 | i.types[j].bitfield.xmmword = 1; | |
4205 | i.types[j].bitfield.ymmword = 0; | |
4206 | } | |
4207 | } | |
392a5972 | 4208 | else if (i.vec_encoding != vex_encoding_evex |
97ed31ae | 4209 | && !i.types[0].bitfield.zmmword |
392a5972 | 4210 | && !i.types[1].bitfield.zmmword |
97ed31ae | 4211 | && !i.mask |
a0a1771e | 4212 | && !i.broadcast |
97ed31ae | 4213 | && is_evex_encoding (&i.tm) |
392a5972 L |
4214 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f |
4215 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f | |
a0a1771e JB |
4216 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f |
4217 | || (i.tm.base_opcode & ~4) == 0x66db | |
4218 | || (i.tm.base_opcode & ~4) == 0x66eb) | |
97ed31ae L |
4219 | && i.tm.extension_opcode == None) |
4220 | { | |
4221 | /* Optimize: -O1: | |
4222 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4223 | vmovdqu32 and vmovdqu64: | |
4224 | EVEX VOP %xmmM, %xmmN | |
4225 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4226 | EVEX VOP %ymmM, %ymmN | |
4227 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4228 | EVEX VOP %xmmM, mem | |
4229 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4230 | EVEX VOP %ymmM, mem | |
4231 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4232 | EVEX VOP mem, %xmmN | |
4233 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4234 | EVEX VOP mem, %ymmN | |
4235 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
a0a1771e JB |
4236 | VOP, one of vpand, vpandn, vpor, vpxor: |
4237 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN | |
4238 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) | |
4239 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN | |
4240 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) | |
4241 | EVEX VOP{d,q} mem, %xmmM, %xmmN | |
4242 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) | |
4243 | EVEX VOP{d,q} mem, %ymmM, %ymmN | |
4244 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) | |
97ed31ae | 4245 | */ |
a0a1771e | 4246 | for (j = 0; j < i.operands; j++) |
392a5972 L |
4247 | if (operand_type_check (i.types[j], disp) |
4248 | && i.op[j].disps->X_op == O_constant) | |
4249 | { | |
4250 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4251 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4252 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4253 | int evex_disp8, vex_disp8; | |
4254 | unsigned int memshift = i.memshift; | |
4255 | offsetT n = i.op[j].disps->X_add_number; | |
4256 | ||
4257 | evex_disp8 = fits_in_disp8 (n); | |
4258 | i.memshift = 0; | |
4259 | vex_disp8 = fits_in_disp8 (n); | |
4260 | if (evex_disp8 != vex_disp8) | |
4261 | { | |
4262 | i.memshift = memshift; | |
4263 | return; | |
4264 | } | |
4265 | ||
4266 | i.types[j].bitfield.disp8 = vex_disp8; | |
4267 | break; | |
4268 | } | |
4269 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f) | |
4270 | i.tm.base_opcode ^= 0xf36f ^ 0xf26f; | |
97ed31ae L |
4271 | i.tm.opcode_modifier.vex |
4272 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4273 | i.tm.opcode_modifier.vexw = VEXW0; | |
79dec6b7 JB |
4274 | /* VPAND, VPOR, and VPXOR are commutative. */ |
4275 | if (i.reg_operands == 3 && i.tm.base_opcode != 0x66df) | |
4276 | i.tm.opcode_modifier.commutative = 1; | |
97ed31ae L |
4277 | i.tm.opcode_modifier.evex = 0; |
4278 | i.tm.opcode_modifier.masking = 0; | |
a0a1771e | 4279 | i.tm.opcode_modifier.broadcast = 0; |
97ed31ae L |
4280 | i.tm.opcode_modifier.disp8memshift = 0; |
4281 | i.memshift = 0; | |
a0a1771e JB |
4282 | if (j < i.operands) |
4283 | i.types[j].bitfield.disp8 | |
4284 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
97ed31ae | 4285 | } |
b6f8c7c4 L |
4286 | } |
4287 | ||
252b5132 RH |
4288 | /* This is the guts of the machine-dependent assembler. LINE points to a |
4289 | machine dependent instruction. This function is supposed to emit | |
4290 | the frags/bytes it assembles to. */ | |
4291 | ||
4292 | void | |
65da13b5 | 4293 | md_assemble (char *line) |
252b5132 | 4294 | { |
40fb9820 | 4295 | unsigned int j; |
83b16ac6 | 4296 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 4297 | const insn_template *t; |
252b5132 | 4298 | |
47926f60 | 4299 | /* Initialize globals. */ |
252b5132 RH |
4300 | memset (&i, '\0', sizeof (i)); |
4301 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 4302 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4303 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4304 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4305 | save_stack_p = save_stack; |
252b5132 RH |
4306 | |
4307 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4308 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4309 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4310 | |
29b0f896 AM |
4311 | line = parse_insn (line, mnemonic); |
4312 | if (line == NULL) | |
4313 | return; | |
83b16ac6 | 4314 | mnem_suffix = i.suffix; |
252b5132 | 4315 | |
29b0f896 | 4316 | line = parse_operands (line, mnemonic); |
ee86248c | 4317 | this_operand = -1; |
8325cc63 JB |
4318 | xfree (i.memop1_string); |
4319 | i.memop1_string = NULL; | |
29b0f896 AM |
4320 | if (line == NULL) |
4321 | return; | |
252b5132 | 4322 | |
29b0f896 AM |
4323 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4324 | operands at hand. */ | |
4325 | ||
4326 | /* All intel opcodes have reversed operands except for "bound" and | |
4327 | "enter". We also don't reverse intersegment "jmp" and "call" | |
4328 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 4329 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
4330 | if (intel_syntax |
4331 | && i.operands > 1 | |
29b0f896 | 4332 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 4333 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
4334 | && !(operand_type_check (i.types[0], imm) |
4335 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
4336 | swap_operands (); |
4337 | ||
ec56d5c0 JB |
4338 | /* The order of the immediates should be reversed |
4339 | for 2 immediates extrq and insertq instructions */ | |
4340 | if (i.imm_operands == 2 | |
4341 | && (strcmp (mnemonic, "extrq") == 0 | |
4342 | || strcmp (mnemonic, "insertq") == 0)) | |
4343 | swap_2_operands (0, 1); | |
4344 | ||
29b0f896 AM |
4345 | if (i.imm_operands) |
4346 | optimize_imm (); | |
4347 | ||
b300c311 L |
4348 | /* Don't optimize displacement for movabs since it only takes 64bit |
4349 | displacement. */ | |
4350 | if (i.disp_operands | |
a501d77e | 4351 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
4352 | && (flag_code != CODE_64BIT |
4353 | || strcmp (mnemonic, "movabs") != 0)) | |
4354 | optimize_disp (); | |
29b0f896 AM |
4355 | |
4356 | /* Next, we find a template that matches the given insn, | |
4357 | making sure the overlap of the given operands types is consistent | |
4358 | with the template operand types. */ | |
252b5132 | 4359 | |
83b16ac6 | 4360 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4361 | return; |
252b5132 | 4362 | |
7bab8ab5 | 4363 | if (sse_check != check_none |
81f8a913 | 4364 | && !i.tm.opcode_modifier.noavx |
6e3e5c9e | 4365 | && !i.tm.cpu_flags.bitfield.cpuavx |
569d50f1 | 4366 | && !i.tm.cpu_flags.bitfield.cpuavx512f |
daf50ae7 L |
4367 | && (i.tm.cpu_flags.bitfield.cpusse |
4368 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4369 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4370 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4371 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
6e3e5c9e | 4372 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
569d50f1 | 4373 | || i.tm.cpu_flags.bitfield.cpusse4a |
6e3e5c9e JB |
4374 | || i.tm.cpu_flags.bitfield.cpupclmul |
4375 | || i.tm.cpu_flags.bitfield.cpuaes | |
569d50f1 | 4376 | || i.tm.cpu_flags.bitfield.cpusha |
6e3e5c9e | 4377 | || i.tm.cpu_flags.bitfield.cpugfni)) |
daf50ae7 | 4378 | { |
7bab8ab5 | 4379 | (sse_check == check_warning |
daf50ae7 L |
4380 | ? as_warn |
4381 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4382 | } | |
4383 | ||
321fd21e L |
4384 | /* Zap movzx and movsx suffix. The suffix has been set from |
4385 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
4386 | or extracted from mnemonic in AT&T syntax. But we'll use | |
4387 | the destination register to choose the suffix for encoding. */ | |
4388 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 4389 | { |
321fd21e L |
4390 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
4391 | there is no suffix, the default will be byte extension. */ | |
4392 | if (i.reg_operands != 2 | |
4393 | && !i.suffix | |
7ab9ffdd | 4394 | && intel_syntax) |
321fd21e L |
4395 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
4396 | ||
4397 | i.suffix = 0; | |
cd61ebfe | 4398 | } |
24eab124 | 4399 | |
40fb9820 | 4400 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4401 | if (!add_prefix (FWAIT_OPCODE)) |
4402 | return; | |
252b5132 | 4403 | |
d5de92cf L |
4404 | /* Check if REP prefix is OK. */ |
4405 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
4406 | { | |
4407 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4408 | i.tm.name, i.rep_prefix); | |
4409 | return; | |
4410 | } | |
4411 | ||
c1ba0266 L |
4412 | /* Check for lock without a lockable instruction. Destination operand |
4413 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
4414 | if (i.prefix[LOCK_PREFIX] |
4415 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
4416 | || i.mem_operands == 0 |
4417 | || (i.tm.base_opcode != 0x86 | |
8dc0818e | 4418 | && !(i.flags[i.operands - 1] & Operand_Mem)))) |
c32fa91d L |
4419 | { |
4420 | as_bad (_("expecting lockable instruction after `lock'")); | |
4421 | return; | |
4422 | } | |
4423 | ||
7a8655d2 JB |
4424 | /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */ |
4425 | if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm)) | |
4426 | { | |
4427 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); | |
4428 | return; | |
4429 | } | |
4430 | ||
42164a71 | 4431 | /* Check if HLE prefix is OK. */ |
165de32a | 4432 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
4433 | return; |
4434 | ||
7e8b059b L |
4435 | /* Check BND prefix. */ |
4436 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
4437 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
4438 | ||
04ef582a | 4439 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
4440 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
4441 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 4442 | |
327e8c42 JB |
4443 | if (i.tm.cpu_flags.bitfield.cpumpx) |
4444 | { | |
4445 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4446 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
4447 | else if (flag_code != CODE_16BIT | |
4448 | ? i.prefix[ADDR_PREFIX] | |
4449 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
4450 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
4451 | } | |
7e8b059b L |
4452 | |
4453 | /* Insert BND prefix. */ | |
76d3a78a JB |
4454 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
4455 | { | |
4456 | if (!i.prefix[BND_PREFIX]) | |
4457 | add_prefix (BND_PREFIX_OPCODE); | |
4458 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
4459 | { | |
4460 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
4461 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
4462 | } | |
4463 | } | |
7e8b059b | 4464 | |
29b0f896 | 4465 | /* Check string instruction segment overrides. */ |
51c8edf6 | 4466 | if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0) |
29b0f896 | 4467 | { |
51c8edf6 | 4468 | gas_assert (i.mem_operands); |
29b0f896 | 4469 | if (!check_string ()) |
5dd0794d | 4470 | return; |
fc0763e6 | 4471 | i.disp_operands = 0; |
29b0f896 | 4472 | } |
5dd0794d | 4473 | |
b6f8c7c4 L |
4474 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
4475 | optimize_encoding (); | |
4476 | ||
29b0f896 AM |
4477 | if (!process_suffix ()) |
4478 | return; | |
e413e4e9 | 4479 | |
bc0844ae L |
4480 | /* Update operand types. */ |
4481 | for (j = 0; j < i.operands; j++) | |
4482 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
4483 | ||
29b0f896 AM |
4484 | /* Make still unresolved immediate matches conform to size of immediate |
4485 | given in i.suffix. */ | |
4486 | if (!finalize_imm ()) | |
4487 | return; | |
252b5132 | 4488 | |
40fb9820 | 4489 | if (i.types[0].bitfield.imm1) |
29b0f896 | 4490 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 4491 | |
9afe6eb8 L |
4492 | /* We only need to check those implicit registers for instructions |
4493 | with 3 operands or less. */ | |
4494 | if (i.operands <= 3) | |
4495 | for (j = 0; j < i.operands; j++) | |
75e5731b JB |
4496 | if (i.types[j].bitfield.instance != InstanceNone |
4497 | && !i.types[j].bitfield.xmmword) | |
9afe6eb8 | 4498 | i.reg_operands--; |
40fb9820 | 4499 | |
c0f3af97 L |
4500 | /* ImmExt should be processed after SSE2AVX. */ |
4501 | if (!i.tm.opcode_modifier.sse2avx | |
4502 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 4503 | process_immext (); |
252b5132 | 4504 | |
29b0f896 AM |
4505 | /* For insns with operands there are more diddles to do to the opcode. */ |
4506 | if (i.operands) | |
4507 | { | |
4508 | if (!process_operands ()) | |
4509 | return; | |
4510 | } | |
40fb9820 | 4511 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
4512 | { |
4513 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
4514 | as_warn (_("translating to `%sp'"), i.tm.name); | |
4515 | } | |
252b5132 | 4516 | |
7a8655d2 | 4517 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 4518 | { |
c1dc7af5 | 4519 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 4520 | { |
c1dc7af5 | 4521 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
9e5e5283 L |
4522 | i.tm.name); |
4523 | return; | |
4524 | } | |
c0f3af97 | 4525 | |
9e5e5283 L |
4526 | if (i.tm.opcode_modifier.vex) |
4527 | build_vex_prefix (t); | |
4528 | else | |
4529 | build_evex_prefix (); | |
4530 | } | |
43234a1e | 4531 | |
5dd85c99 SP |
4532 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
4533 | instructions may define INT_OPCODE as well, so avoid this corner | |
4534 | case for those instructions that use MODRM. */ | |
4535 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
4536 | && !i.tm.opcode_modifier.modrm |
4537 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
4538 | { |
4539 | i.tm.base_opcode = INT3_OPCODE; | |
4540 | i.imm_operands = 0; | |
4541 | } | |
252b5132 | 4542 | |
0cfa3eb3 JB |
4543 | if ((i.tm.opcode_modifier.jump == JUMP |
4544 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
4545 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 AM |
4546 | && i.op[0].disps->X_op == O_constant) |
4547 | { | |
4548 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
4549 | the absolute address given by the constant. Since ix86 jumps and | |
4550 | calls are pc relative, we need to generate a reloc. */ | |
4551 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
4552 | i.op[0].disps->X_op = O_symbol; | |
4553 | } | |
252b5132 | 4554 | |
40fb9820 | 4555 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 4556 | i.rex |= REX_W; |
252b5132 | 4557 | |
29b0f896 AM |
4558 | /* For 8 bit registers we need an empty rex prefix. Also if the |
4559 | instruction already has a prefix, we need to convert old | |
4560 | registers to new ones. */ | |
773f551c | 4561 | |
bab6aec1 | 4562 | if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte |
29b0f896 | 4563 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
bab6aec1 | 4564 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte |
29b0f896 | 4565 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
bab6aec1 JB |
4566 | || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte) |
4567 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
4568 | && i.rex != 0)) |
4569 | { | |
4570 | int x; | |
726c5dcd | 4571 | |
29b0f896 AM |
4572 | i.rex |= REX_OPCODE; |
4573 | for (x = 0; x < 2; x++) | |
4574 | { | |
4575 | /* Look for 8 bit operand that uses old registers. */ | |
bab6aec1 | 4576 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte |
29b0f896 | 4577 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 4578 | { |
3f93af61 | 4579 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
29b0f896 AM |
4580 | /* In case it is "hi" register, give up. */ |
4581 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 4582 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 4583 | "instruction requiring REX prefix."), |
a540244d | 4584 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 4585 | |
29b0f896 AM |
4586 | /* Otherwise it is equivalent to the extended register. |
4587 | Since the encoding doesn't change this is merely | |
4588 | cosmetic cleanup for debug output. */ | |
4589 | ||
4590 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 4591 | } |
29b0f896 AM |
4592 | } |
4593 | } | |
773f551c | 4594 | |
6b6b6807 L |
4595 | if (i.rex == 0 && i.rex_encoding) |
4596 | { | |
4597 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
3f93af61 | 4598 | that uses legacy register. If it is "hi" register, don't add |
6b6b6807 L |
4599 | the REX_OPCODE byte. */ |
4600 | int x; | |
4601 | for (x = 0; x < 2; x++) | |
bab6aec1 | 4602 | if (i.types[x].bitfield.class == Reg |
6b6b6807 L |
4603 | && i.types[x].bitfield.byte |
4604 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4605 | && i.op[x].regs->reg_num > 3) | |
4606 | { | |
3f93af61 | 4607 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
6b6b6807 L |
4608 | i.rex_encoding = FALSE; |
4609 | break; | |
4610 | } | |
4611 | ||
4612 | if (i.rex_encoding) | |
4613 | i.rex = REX_OPCODE; | |
4614 | } | |
4615 | ||
7ab9ffdd | 4616 | if (i.rex != 0) |
29b0f896 AM |
4617 | add_prefix (REX_OPCODE | i.rex); |
4618 | ||
4619 | /* We are ready to output the insn. */ | |
4620 | output_insn (); | |
e379e5f3 L |
4621 | |
4622 | last_insn.seg = now_seg; | |
4623 | ||
4624 | if (i.tm.opcode_modifier.isprefix) | |
4625 | { | |
4626 | last_insn.kind = last_insn_prefix; | |
4627 | last_insn.name = i.tm.name; | |
4628 | last_insn.file = as_where (&last_insn.line); | |
4629 | } | |
4630 | else | |
4631 | last_insn.kind = last_insn_other; | |
29b0f896 AM |
4632 | } |
4633 | ||
4634 | static char * | |
e3bb37b5 | 4635 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
4636 | { |
4637 | char *l = line; | |
4638 | char *token_start = l; | |
4639 | char *mnem_p; | |
5c6af06e | 4640 | int supported; |
d3ce72d0 | 4641 | const insn_template *t; |
b6169b20 | 4642 | char *dot_p = NULL; |
29b0f896 | 4643 | |
29b0f896 AM |
4644 | while (1) |
4645 | { | |
4646 | mnem_p = mnemonic; | |
4647 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
4648 | { | |
b6169b20 L |
4649 | if (*mnem_p == '.') |
4650 | dot_p = mnem_p; | |
29b0f896 AM |
4651 | mnem_p++; |
4652 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 4653 | { |
29b0f896 AM |
4654 | as_bad (_("no such instruction: `%s'"), token_start); |
4655 | return NULL; | |
4656 | } | |
4657 | l++; | |
4658 | } | |
4659 | if (!is_space_char (*l) | |
4660 | && *l != END_OF_INSN | |
e44823cf JB |
4661 | && (intel_syntax |
4662 | || (*l != PREFIX_SEPARATOR | |
4663 | && *l != ','))) | |
29b0f896 AM |
4664 | { |
4665 | as_bad (_("invalid character %s in mnemonic"), | |
4666 | output_invalid (*l)); | |
4667 | return NULL; | |
4668 | } | |
4669 | if (token_start == l) | |
4670 | { | |
e44823cf | 4671 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
4672 | as_bad (_("expecting prefix; got nothing")); |
4673 | else | |
4674 | as_bad (_("expecting mnemonic; got nothing")); | |
4675 | return NULL; | |
4676 | } | |
45288df1 | 4677 | |
29b0f896 | 4678 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 4679 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 4680 | |
29b0f896 AM |
4681 | if (*l != END_OF_INSN |
4682 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
4683 | && current_templates | |
40fb9820 | 4684 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 4685 | { |
c6fb90c8 | 4686 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
4687 | { |
4688 | as_bad ((flag_code != CODE_64BIT | |
4689 | ? _("`%s' is only supported in 64-bit mode") | |
4690 | : _("`%s' is not supported in 64-bit mode")), | |
4691 | current_templates->start->name); | |
4692 | return NULL; | |
4693 | } | |
29b0f896 AM |
4694 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
4695 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
673fe0f0 JB |
4696 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
4697 | || current_templates->start->opcode_modifier.size == SIZE32) | |
29b0f896 | 4698 | && flag_code != CODE_64BIT |
673fe0f0 | 4699 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
4700 | ^ (flag_code == CODE_16BIT))) |
4701 | { | |
4702 | as_bad (_("redundant %s prefix"), | |
4703 | current_templates->start->name); | |
4704 | return NULL; | |
45288df1 | 4705 | } |
86fa6981 | 4706 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 4707 | { |
86fa6981 L |
4708 | /* Handle pseudo prefixes. */ |
4709 | switch (current_templates->start->base_opcode) | |
4710 | { | |
4711 | case 0x0: | |
4712 | /* {disp8} */ | |
4713 | i.disp_encoding = disp_encoding_8bit; | |
4714 | break; | |
4715 | case 0x1: | |
4716 | /* {disp32} */ | |
4717 | i.disp_encoding = disp_encoding_32bit; | |
4718 | break; | |
4719 | case 0x2: | |
4720 | /* {load} */ | |
4721 | i.dir_encoding = dir_encoding_load; | |
4722 | break; | |
4723 | case 0x3: | |
4724 | /* {store} */ | |
4725 | i.dir_encoding = dir_encoding_store; | |
4726 | break; | |
4727 | case 0x4: | |
42e04b36 L |
4728 | /* {vex} */ |
4729 | i.vec_encoding = vex_encoding_vex; | |
86fa6981 L |
4730 | break; |
4731 | case 0x5: | |
4732 | /* {vex3} */ | |
4733 | i.vec_encoding = vex_encoding_vex3; | |
4734 | break; | |
4735 | case 0x6: | |
4736 | /* {evex} */ | |
4737 | i.vec_encoding = vex_encoding_evex; | |
4738 | break; | |
6b6b6807 L |
4739 | case 0x7: |
4740 | /* {rex} */ | |
4741 | i.rex_encoding = TRUE; | |
4742 | break; | |
b6f8c7c4 L |
4743 | case 0x8: |
4744 | /* {nooptimize} */ | |
4745 | i.no_optimize = TRUE; | |
4746 | break; | |
86fa6981 L |
4747 | default: |
4748 | abort (); | |
4749 | } | |
4750 | } | |
4751 | else | |
4752 | { | |
4753 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 4754 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 4755 | { |
4e9ac44a L |
4756 | case PREFIX_EXIST: |
4757 | return NULL; | |
4758 | case PREFIX_DS: | |
d777820b | 4759 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
4760 | i.notrack_prefix = current_templates->start->name; |
4761 | break; | |
4762 | case PREFIX_REP: | |
4763 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
4764 | i.hle_prefix = current_templates->start->name; | |
4765 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
4766 | i.bnd_prefix = current_templates->start->name; | |
4767 | else | |
4768 | i.rep_prefix = current_templates->start->name; | |
4769 | break; | |
4770 | default: | |
4771 | break; | |
86fa6981 | 4772 | } |
29b0f896 AM |
4773 | } |
4774 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
4775 | token_start = ++l; | |
4776 | } | |
4777 | else | |
4778 | break; | |
4779 | } | |
45288df1 | 4780 | |
30a55f88 | 4781 | if (!current_templates) |
b6169b20 | 4782 | { |
07d5e953 JB |
4783 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
4784 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 4785 | encoding. */ |
30a55f88 | 4786 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 4787 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 4788 | else if (mnem_p - 3 == dot_p |
a501d77e L |
4789 | && dot_p[1] == 'd' |
4790 | && dot_p[2] == '8') | |
4791 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 4792 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
4793 | && dot_p[1] == 'd' |
4794 | && dot_p[2] == '3' | |
4795 | && dot_p[3] == '2') | |
a501d77e | 4796 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
4797 | else |
4798 | goto check_suffix; | |
4799 | mnem_p = dot_p; | |
4800 | *dot_p = '\0'; | |
d3ce72d0 | 4801 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
4802 | } |
4803 | ||
29b0f896 AM |
4804 | if (!current_templates) |
4805 | { | |
b6169b20 | 4806 | check_suffix: |
1c529385 | 4807 | if (mnem_p > mnemonic) |
29b0f896 | 4808 | { |
1c529385 LH |
4809 | /* See if we can get a match by trimming off a suffix. */ |
4810 | switch (mnem_p[-1]) | |
29b0f896 | 4811 | { |
1c529385 LH |
4812 | case WORD_MNEM_SUFFIX: |
4813 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
4814 | i.suffix = SHORT_MNEM_SUFFIX; |
4815 | else | |
1c529385 LH |
4816 | /* Fall through. */ |
4817 | case BYTE_MNEM_SUFFIX: | |
4818 | case QWORD_MNEM_SUFFIX: | |
4819 | i.suffix = mnem_p[-1]; | |
29b0f896 | 4820 | mnem_p[-1] = '\0'; |
d3ce72d0 | 4821 | current_templates = (const templates *) hash_find (op_hash, |
1c529385 LH |
4822 | mnemonic); |
4823 | break; | |
4824 | case SHORT_MNEM_SUFFIX: | |
4825 | case LONG_MNEM_SUFFIX: | |
4826 | if (!intel_syntax) | |
4827 | { | |
4828 | i.suffix = mnem_p[-1]; | |
4829 | mnem_p[-1] = '\0'; | |
4830 | current_templates = (const templates *) hash_find (op_hash, | |
4831 | mnemonic); | |
4832 | } | |
4833 | break; | |
4834 | ||
4835 | /* Intel Syntax. */ | |
4836 | case 'd': | |
4837 | if (intel_syntax) | |
4838 | { | |
4839 | if (intel_float_operand (mnemonic) == 1) | |
4840 | i.suffix = SHORT_MNEM_SUFFIX; | |
4841 | else | |
4842 | i.suffix = LONG_MNEM_SUFFIX; | |
4843 | mnem_p[-1] = '\0'; | |
4844 | current_templates = (const templates *) hash_find (op_hash, | |
4845 | mnemonic); | |
4846 | } | |
4847 | break; | |
29b0f896 | 4848 | } |
29b0f896 | 4849 | } |
1c529385 | 4850 | |
29b0f896 AM |
4851 | if (!current_templates) |
4852 | { | |
4853 | as_bad (_("no such instruction: `%s'"), token_start); | |
4854 | return NULL; | |
4855 | } | |
4856 | } | |
252b5132 | 4857 | |
0cfa3eb3 JB |
4858 | if (current_templates->start->opcode_modifier.jump == JUMP |
4859 | || current_templates->start->opcode_modifier.jump == JUMP_BYTE) | |
29b0f896 AM |
4860 | { |
4861 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4862 | predict taken and predict not taken respectively. | |
4863 | I'm not sure that branch hints actually do anything on loop | |
4864 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4865 | may work in the future and it doesn't hurt to accept them | |
4866 | now. */ | |
4867 | if (l[0] == ',' && l[1] == 'p') | |
4868 | { | |
4869 | if (l[2] == 't') | |
4870 | { | |
4871 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4872 | return NULL; | |
4873 | l += 3; | |
4874 | } | |
4875 | else if (l[2] == 'n') | |
4876 | { | |
4877 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4878 | return NULL; | |
4879 | l += 3; | |
4880 | } | |
4881 | } | |
4882 | } | |
4883 | /* Any other comma loses. */ | |
4884 | if (*l == ',') | |
4885 | { | |
4886 | as_bad (_("invalid character %s in mnemonic"), | |
4887 | output_invalid (*l)); | |
4888 | return NULL; | |
4889 | } | |
252b5132 | 4890 | |
29b0f896 | 4891 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4892 | supported = 0; |
4893 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4894 | { | |
c0f3af97 L |
4895 | supported |= cpu_flags_match (t); |
4896 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
548d0ee6 JB |
4897 | { |
4898 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) | |
4899 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3629bb00 | 4900 | |
548d0ee6 JB |
4901 | return l; |
4902 | } | |
29b0f896 | 4903 | } |
3629bb00 | 4904 | |
548d0ee6 JB |
4905 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
4906 | as_bad (flag_code == CODE_64BIT | |
4907 | ? _("`%s' is not supported in 64-bit mode") | |
4908 | : _("`%s' is only supported in 64-bit mode"), | |
4909 | current_templates->start->name); | |
4910 | else | |
4911 | as_bad (_("`%s' is not supported on `%s%s'"), | |
4912 | current_templates->start->name, | |
4913 | cpu_arch_name ? cpu_arch_name : default_arch, | |
4914 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 4915 | |
548d0ee6 | 4916 | return NULL; |
29b0f896 | 4917 | } |
252b5132 | 4918 | |
29b0f896 | 4919 | static char * |
e3bb37b5 | 4920 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4921 | { |
4922 | char *token_start; | |
3138f287 | 4923 | |
29b0f896 AM |
4924 | /* 1 if operand is pending after ','. */ |
4925 | unsigned int expecting_operand = 0; | |
252b5132 | 4926 | |
29b0f896 AM |
4927 | /* Non-zero if operand parens not balanced. */ |
4928 | unsigned int paren_not_balanced; | |
4929 | ||
4930 | while (*l != END_OF_INSN) | |
4931 | { | |
4932 | /* Skip optional white space before operand. */ | |
4933 | if (is_space_char (*l)) | |
4934 | ++l; | |
d02603dc | 4935 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4936 | { |
4937 | as_bad (_("invalid character %s before operand %d"), | |
4938 | output_invalid (*l), | |
4939 | i.operands + 1); | |
4940 | return NULL; | |
4941 | } | |
d02603dc | 4942 | token_start = l; /* After white space. */ |
29b0f896 AM |
4943 | paren_not_balanced = 0; |
4944 | while (paren_not_balanced || *l != ',') | |
4945 | { | |
4946 | if (*l == END_OF_INSN) | |
4947 | { | |
4948 | if (paren_not_balanced) | |
4949 | { | |
4950 | if (!intel_syntax) | |
4951 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4952 | i.operands + 1); | |
4953 | else | |
4954 | as_bad (_("unbalanced brackets in operand %d."), | |
4955 | i.operands + 1); | |
4956 | return NULL; | |
4957 | } | |
4958 | else | |
4959 | break; /* we are done */ | |
4960 | } | |
d02603dc | 4961 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4962 | { |
4963 | as_bad (_("invalid character %s in operand %d"), | |
4964 | output_invalid (*l), | |
4965 | i.operands + 1); | |
4966 | return NULL; | |
4967 | } | |
4968 | if (!intel_syntax) | |
4969 | { | |
4970 | if (*l == '(') | |
4971 | ++paren_not_balanced; | |
4972 | if (*l == ')') | |
4973 | --paren_not_balanced; | |
4974 | } | |
4975 | else | |
4976 | { | |
4977 | if (*l == '[') | |
4978 | ++paren_not_balanced; | |
4979 | if (*l == ']') | |
4980 | --paren_not_balanced; | |
4981 | } | |
4982 | l++; | |
4983 | } | |
4984 | if (l != token_start) | |
4985 | { /* Yes, we've read in another operand. */ | |
4986 | unsigned int operand_ok; | |
4987 | this_operand = i.operands++; | |
4988 | if (i.operands > MAX_OPERANDS) | |
4989 | { | |
4990 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
4991 | MAX_OPERANDS); | |
4992 | return NULL; | |
4993 | } | |
9d46ce34 | 4994 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
4995 | /* Now parse operand adding info to 'i' as we go along. */ |
4996 | END_STRING_AND_SAVE (l); | |
4997 | ||
1286ab78 L |
4998 | if (i.mem_operands > 1) |
4999 | { | |
5000 | as_bad (_("too many memory references for `%s'"), | |
5001 | mnemonic); | |
5002 | return 0; | |
5003 | } | |
5004 | ||
29b0f896 AM |
5005 | if (intel_syntax) |
5006 | operand_ok = | |
5007 | i386_intel_operand (token_start, | |
5008 | intel_float_operand (mnemonic)); | |
5009 | else | |
a7619375 | 5010 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
5011 | |
5012 | RESTORE_END_STRING (l); | |
5013 | if (!operand_ok) | |
5014 | return NULL; | |
5015 | } | |
5016 | else | |
5017 | { | |
5018 | if (expecting_operand) | |
5019 | { | |
5020 | expecting_operand_after_comma: | |
5021 | as_bad (_("expecting operand after ','; got nothing")); | |
5022 | return NULL; | |
5023 | } | |
5024 | if (*l == ',') | |
5025 | { | |
5026 | as_bad (_("expecting operand before ','; got nothing")); | |
5027 | return NULL; | |
5028 | } | |
5029 | } | |
7f3f1ea2 | 5030 | |
29b0f896 AM |
5031 | /* Now *l must be either ',' or END_OF_INSN. */ |
5032 | if (*l == ',') | |
5033 | { | |
5034 | if (*++l == END_OF_INSN) | |
5035 | { | |
5036 | /* Just skip it, if it's \n complain. */ | |
5037 | goto expecting_operand_after_comma; | |
5038 | } | |
5039 | expecting_operand = 1; | |
5040 | } | |
5041 | } | |
5042 | return l; | |
5043 | } | |
7f3f1ea2 | 5044 | |
050dfa73 | 5045 | static void |
4d456e3d | 5046 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
5047 | { |
5048 | union i386_op temp_op; | |
40fb9820 | 5049 | i386_operand_type temp_type; |
c48dadc9 | 5050 | unsigned int temp_flags; |
050dfa73 | 5051 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 5052 | |
050dfa73 MM |
5053 | temp_type = i.types[xchg2]; |
5054 | i.types[xchg2] = i.types[xchg1]; | |
5055 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
5056 | |
5057 | temp_flags = i.flags[xchg2]; | |
5058 | i.flags[xchg2] = i.flags[xchg1]; | |
5059 | i.flags[xchg1] = temp_flags; | |
5060 | ||
050dfa73 MM |
5061 | temp_op = i.op[xchg2]; |
5062 | i.op[xchg2] = i.op[xchg1]; | |
5063 | i.op[xchg1] = temp_op; | |
c48dadc9 | 5064 | |
050dfa73 MM |
5065 | temp_reloc = i.reloc[xchg2]; |
5066 | i.reloc[xchg2] = i.reloc[xchg1]; | |
5067 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
5068 | |
5069 | if (i.mask) | |
5070 | { | |
5071 | if (i.mask->operand == xchg1) | |
5072 | i.mask->operand = xchg2; | |
5073 | else if (i.mask->operand == xchg2) | |
5074 | i.mask->operand = xchg1; | |
5075 | } | |
5076 | if (i.broadcast) | |
5077 | { | |
5078 | if (i.broadcast->operand == xchg1) | |
5079 | i.broadcast->operand = xchg2; | |
5080 | else if (i.broadcast->operand == xchg2) | |
5081 | i.broadcast->operand = xchg1; | |
5082 | } | |
5083 | if (i.rounding) | |
5084 | { | |
5085 | if (i.rounding->operand == xchg1) | |
5086 | i.rounding->operand = xchg2; | |
5087 | else if (i.rounding->operand == xchg2) | |
5088 | i.rounding->operand = xchg1; | |
5089 | } | |
050dfa73 MM |
5090 | } |
5091 | ||
29b0f896 | 5092 | static void |
e3bb37b5 | 5093 | swap_operands (void) |
29b0f896 | 5094 | { |
b7c61d9a | 5095 | switch (i.operands) |
050dfa73 | 5096 | { |
c0f3af97 | 5097 | case 5: |
b7c61d9a | 5098 | case 4: |
4d456e3d | 5099 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 5100 | /* Fall through. */ |
b7c61d9a L |
5101 | case 3: |
5102 | case 2: | |
4d456e3d | 5103 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
5104 | break; |
5105 | default: | |
5106 | abort (); | |
29b0f896 | 5107 | } |
29b0f896 AM |
5108 | |
5109 | if (i.mem_operands == 2) | |
5110 | { | |
5111 | const seg_entry *temp_seg; | |
5112 | temp_seg = i.seg[0]; | |
5113 | i.seg[0] = i.seg[1]; | |
5114 | i.seg[1] = temp_seg; | |
5115 | } | |
5116 | } | |
252b5132 | 5117 | |
29b0f896 AM |
5118 | /* Try to ensure constant immediates are represented in the smallest |
5119 | opcode possible. */ | |
5120 | static void | |
e3bb37b5 | 5121 | optimize_imm (void) |
29b0f896 AM |
5122 | { |
5123 | char guess_suffix = 0; | |
5124 | int op; | |
252b5132 | 5125 | |
29b0f896 AM |
5126 | if (i.suffix) |
5127 | guess_suffix = i.suffix; | |
5128 | else if (i.reg_operands) | |
5129 | { | |
5130 | /* Figure out a suffix from the last register operand specified. | |
75e5731b JB |
5131 | We can't do this properly yet, i.e. excluding special register |
5132 | instances, but the following works for instructions with | |
5133 | immediates. In any case, we can't set i.suffix yet. */ | |
29b0f896 | 5134 | for (op = i.operands; --op >= 0;) |
bab6aec1 JB |
5135 | if (i.types[op].bitfield.class != Reg) |
5136 | continue; | |
5137 | else if (i.types[op].bitfield.byte) | |
7ab9ffdd | 5138 | { |
40fb9820 L |
5139 | guess_suffix = BYTE_MNEM_SUFFIX; |
5140 | break; | |
5141 | } | |
bab6aec1 | 5142 | else if (i.types[op].bitfield.word) |
252b5132 | 5143 | { |
40fb9820 L |
5144 | guess_suffix = WORD_MNEM_SUFFIX; |
5145 | break; | |
5146 | } | |
bab6aec1 | 5147 | else if (i.types[op].bitfield.dword) |
40fb9820 L |
5148 | { |
5149 | guess_suffix = LONG_MNEM_SUFFIX; | |
5150 | break; | |
5151 | } | |
bab6aec1 | 5152 | else if (i.types[op].bitfield.qword) |
40fb9820 L |
5153 | { |
5154 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 5155 | break; |
252b5132 | 5156 | } |
29b0f896 AM |
5157 | } |
5158 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
5159 | guess_suffix = WORD_MNEM_SUFFIX; | |
5160 | ||
5161 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 5162 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
5163 | { |
5164 | switch (i.op[op].imms->X_op) | |
252b5132 | 5165 | { |
29b0f896 AM |
5166 | case O_constant: |
5167 | /* If a suffix is given, this operand may be shortened. */ | |
5168 | switch (guess_suffix) | |
252b5132 | 5169 | { |
29b0f896 | 5170 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
5171 | i.types[op].bitfield.imm32 = 1; |
5172 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5173 | break; |
5174 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
5175 | i.types[op].bitfield.imm16 = 1; |
5176 | i.types[op].bitfield.imm32 = 1; | |
5177 | i.types[op].bitfield.imm32s = 1; | |
5178 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5179 | break; |
5180 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
5181 | i.types[op].bitfield.imm8 = 1; |
5182 | i.types[op].bitfield.imm8s = 1; | |
5183 | i.types[op].bitfield.imm16 = 1; | |
5184 | i.types[op].bitfield.imm32 = 1; | |
5185 | i.types[op].bitfield.imm32s = 1; | |
5186 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 5187 | break; |
252b5132 | 5188 | } |
252b5132 | 5189 | |
29b0f896 AM |
5190 | /* If this operand is at most 16 bits, convert it |
5191 | to a signed 16 bit number before trying to see | |
5192 | whether it will fit in an even smaller size. | |
5193 | This allows a 16-bit operand such as $0xffe0 to | |
5194 | be recognised as within Imm8S range. */ | |
40fb9820 | 5195 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 5196 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 5197 | { |
29b0f896 AM |
5198 | i.op[op].imms->X_add_number = |
5199 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
5200 | } | |
a28def75 L |
5201 | #ifdef BFD64 |
5202 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 5203 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
5204 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
5205 | == 0)) | |
5206 | { | |
5207 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
5208 | ^ ((offsetT) 1 << 31)) | |
5209 | - ((offsetT) 1 << 31)); | |
5210 | } | |
a28def75 | 5211 | #endif |
40fb9820 | 5212 | i.types[op] |
c6fb90c8 L |
5213 | = operand_type_or (i.types[op], |
5214 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 5215 | |
29b0f896 AM |
5216 | /* We must avoid matching of Imm32 templates when 64bit |
5217 | only immediate is available. */ | |
5218 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 5219 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 5220 | break; |
252b5132 | 5221 | |
29b0f896 AM |
5222 | case O_absent: |
5223 | case O_register: | |
5224 | abort (); | |
5225 | ||
5226 | /* Symbols and expressions. */ | |
5227 | default: | |
9cd96992 JB |
5228 | /* Convert symbolic operand to proper sizes for matching, but don't |
5229 | prevent matching a set of insns that only supports sizes other | |
5230 | than those matching the insn suffix. */ | |
5231 | { | |
40fb9820 | 5232 | i386_operand_type mask, allowed; |
d3ce72d0 | 5233 | const insn_template *t; |
9cd96992 | 5234 | |
0dfbf9d7 L |
5235 | operand_type_set (&mask, 0); |
5236 | operand_type_set (&allowed, 0); | |
40fb9820 | 5237 | |
4eed87de AM |
5238 | for (t = current_templates->start; |
5239 | t < current_templates->end; | |
5240 | ++t) | |
bab6aec1 JB |
5241 | { |
5242 | allowed = operand_type_or (allowed, t->operand_types[op]); | |
5243 | allowed = operand_type_and (allowed, anyimm); | |
5244 | } | |
9cd96992 JB |
5245 | switch (guess_suffix) |
5246 | { | |
5247 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
5248 | mask.bitfield.imm64 = 1; |
5249 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
5250 | break; |
5251 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 5252 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
5253 | break; |
5254 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 5255 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
5256 | break; |
5257 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 5258 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
5259 | break; |
5260 | default: | |
9cd96992 JB |
5261 | break; |
5262 | } | |
c6fb90c8 | 5263 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 5264 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 5265 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 5266 | } |
29b0f896 | 5267 | break; |
252b5132 | 5268 | } |
29b0f896 AM |
5269 | } |
5270 | } | |
47926f60 | 5271 | |
29b0f896 AM |
5272 | /* Try to use the smallest displacement type too. */ |
5273 | static void | |
e3bb37b5 | 5274 | optimize_disp (void) |
29b0f896 AM |
5275 | { |
5276 | int op; | |
3e73aa7c | 5277 | |
29b0f896 | 5278 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5279 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 5280 | { |
b300c311 | 5281 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 5282 | { |
91d6fa6a | 5283 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 5284 | |
40fb9820 | 5285 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 5286 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
5287 | { |
5288 | /* If this operand is at most 16 bits, convert | |
5289 | to a signed 16 bit number and don't use 64bit | |
5290 | displacement. */ | |
91d6fa6a | 5291 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 5292 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5293 | } |
a28def75 L |
5294 | #ifdef BFD64 |
5295 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 5296 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 5297 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
5298 | { |
5299 | /* If this operand is at most 32 bits, convert | |
5300 | to a signed 32 bit number and don't use 64bit | |
5301 | displacement. */ | |
91d6fa6a NC |
5302 | op_disp &= (((offsetT) 2 << 31) - 1); |
5303 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 5304 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5305 | } |
a28def75 | 5306 | #endif |
91d6fa6a | 5307 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 5308 | { |
40fb9820 L |
5309 | i.types[op].bitfield.disp8 = 0; |
5310 | i.types[op].bitfield.disp16 = 0; | |
5311 | i.types[op].bitfield.disp32 = 0; | |
5312 | i.types[op].bitfield.disp32s = 0; | |
5313 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
5314 | i.op[op].disps = 0; |
5315 | i.disp_operands--; | |
5316 | } | |
5317 | else if (flag_code == CODE_64BIT) | |
5318 | { | |
91d6fa6a | 5319 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 5320 | { |
40fb9820 L |
5321 | i.types[op].bitfield.disp64 = 0; |
5322 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 5323 | } |
0e1147d9 | 5324 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 5325 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 5326 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 5327 | } |
40fb9820 L |
5328 | if ((i.types[op].bitfield.disp32 |
5329 | || i.types[op].bitfield.disp32s | |
5330 | || i.types[op].bitfield.disp16) | |
b5014f7a | 5331 | && fits_in_disp8 (op_disp)) |
40fb9820 | 5332 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5333 | } |
67a4f2b7 AO |
5334 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
5335 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
5336 | { | |
5337 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
5338 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
5339 | i.types[op].bitfield.disp8 = 0; |
5340 | i.types[op].bitfield.disp16 = 0; | |
5341 | i.types[op].bitfield.disp32 = 0; | |
5342 | i.types[op].bitfield.disp32s = 0; | |
5343 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
5344 | } |
5345 | else | |
b300c311 | 5346 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 5347 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 5348 | } |
29b0f896 AM |
5349 | } |
5350 | ||
4a1b91ea L |
5351 | /* Return 1 if there is a match in broadcast bytes between operand |
5352 | GIVEN and instruction template T. */ | |
5353 | ||
5354 | static INLINE int | |
5355 | match_broadcast_size (const insn_template *t, unsigned int given) | |
5356 | { | |
5357 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
5358 | && i.types[given].bitfield.byte) | |
5359 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
5360 | && i.types[given].bitfield.word) | |
5361 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
5362 | && i.types[given].bitfield.dword) | |
5363 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
5364 | && i.types[given].bitfield.qword)); | |
5365 | } | |
5366 | ||
6c30d220 L |
5367 | /* Check if operands are valid for the instruction. */ |
5368 | ||
5369 | static int | |
5370 | check_VecOperands (const insn_template *t) | |
5371 | { | |
43234a1e | 5372 | unsigned int op; |
e2195274 | 5373 | i386_cpu_flags cpu; |
e2195274 JB |
5374 | |
5375 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
5376 | any one operand are implicity requiring AVX512VL support if the actual | |
5377 | operand size is YMMword or XMMword. Since this function runs after | |
5378 | template matching, there's no need to check for YMMword/XMMword in | |
5379 | the template. */ | |
5380 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
5381 | if (!cpu_flags_all_zero (&cpu) | |
5382 | && !t->cpu_flags.bitfield.cpuavx512vl | |
5383 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
5384 | { | |
5385 | for (op = 0; op < t->operands; ++op) | |
5386 | { | |
5387 | if (t->operand_types[op].bitfield.zmmword | |
5388 | && (i.types[op].bitfield.ymmword | |
5389 | || i.types[op].bitfield.xmmword)) | |
5390 | { | |
5391 | i.error = unsupported; | |
5392 | return 1; | |
5393 | } | |
5394 | } | |
5395 | } | |
43234a1e | 5396 | |
6c30d220 L |
5397 | /* Without VSIB byte, we can't have a vector register for index. */ |
5398 | if (!t->opcode_modifier.vecsib | |
5399 | && i.index_reg | |
1b54b8d7 JB |
5400 | && (i.index_reg->reg_type.bitfield.xmmword |
5401 | || i.index_reg->reg_type.bitfield.ymmword | |
5402 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
5403 | { |
5404 | i.error = unsupported_vector_index_register; | |
5405 | return 1; | |
5406 | } | |
5407 | ||
ad8ecc81 MZ |
5408 | /* Check if default mask is allowed. */ |
5409 | if (t->opcode_modifier.nodefmask | |
5410 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
5411 | { | |
5412 | i.error = no_default_mask; | |
5413 | return 1; | |
5414 | } | |
5415 | ||
7bab8ab5 JB |
5416 | /* For VSIB byte, we need a vector register for index, and all vector |
5417 | registers must be distinct. */ | |
5418 | if (t->opcode_modifier.vecsib) | |
5419 | { | |
5420 | if (!i.index_reg | |
6c30d220 | 5421 | || !((t->opcode_modifier.vecsib == VecSIB128 |
1b54b8d7 | 5422 | && i.index_reg->reg_type.bitfield.xmmword) |
6c30d220 | 5423 | || (t->opcode_modifier.vecsib == VecSIB256 |
1b54b8d7 | 5424 | && i.index_reg->reg_type.bitfield.ymmword) |
43234a1e | 5425 | || (t->opcode_modifier.vecsib == VecSIB512 |
1b54b8d7 | 5426 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
5427 | { |
5428 | i.error = invalid_vsib_address; | |
5429 | return 1; | |
5430 | } | |
5431 | ||
43234a1e L |
5432 | gas_assert (i.reg_operands == 2 || i.mask); |
5433 | if (i.reg_operands == 2 && !i.mask) | |
5434 | { | |
3528c362 | 5435 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5436 | gas_assert (i.types[0].bitfield.xmmword |
5437 | || i.types[0].bitfield.ymmword); | |
3528c362 | 5438 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5439 | gas_assert (i.types[2].bitfield.xmmword |
5440 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
5441 | if (operand_check == check_none) |
5442 | return 0; | |
5443 | if (register_number (i.op[0].regs) | |
5444 | != register_number (i.index_reg) | |
5445 | && register_number (i.op[2].regs) | |
5446 | != register_number (i.index_reg) | |
5447 | && register_number (i.op[0].regs) | |
5448 | != register_number (i.op[2].regs)) | |
5449 | return 0; | |
5450 | if (operand_check == check_error) | |
5451 | { | |
5452 | i.error = invalid_vector_register_set; | |
5453 | return 1; | |
5454 | } | |
5455 | as_warn (_("mask, index, and destination registers should be distinct")); | |
5456 | } | |
8444f82a MZ |
5457 | else if (i.reg_operands == 1 && i.mask) |
5458 | { | |
3528c362 | 5459 | if (i.types[1].bitfield.class == RegSIMD |
1b54b8d7 JB |
5460 | && (i.types[1].bitfield.xmmword |
5461 | || i.types[1].bitfield.ymmword | |
5462 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
5463 | && (register_number (i.op[1].regs) |
5464 | == register_number (i.index_reg))) | |
5465 | { | |
5466 | if (operand_check == check_error) | |
5467 | { | |
5468 | i.error = invalid_vector_register_set; | |
5469 | return 1; | |
5470 | } | |
5471 | if (operand_check != check_none) | |
5472 | as_warn (_("index and destination registers should be distinct")); | |
5473 | } | |
5474 | } | |
43234a1e | 5475 | } |
7bab8ab5 | 5476 | |
43234a1e L |
5477 | /* Check if broadcast is supported by the instruction and is applied |
5478 | to the memory operand. */ | |
5479 | if (i.broadcast) | |
5480 | { | |
8e6e0792 | 5481 | i386_operand_type type, overlap; |
43234a1e L |
5482 | |
5483 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 5484 | and its broadcast bytes match the memory operand. */ |
32546502 | 5485 | op = i.broadcast->operand; |
8e6e0792 | 5486 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 5487 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 5488 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 5489 | && !match_broadcast_size (t, op))) |
43234a1e L |
5490 | { |
5491 | bad_broadcast: | |
5492 | i.error = unsupported_broadcast; | |
5493 | return 1; | |
5494 | } | |
8e6e0792 | 5495 | |
4a1b91ea L |
5496 | i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
5497 | * i.broadcast->type); | |
8e6e0792 | 5498 | operand_type_set (&type, 0); |
4a1b91ea | 5499 | switch (i.broadcast->bytes) |
8e6e0792 | 5500 | { |
4a1b91ea L |
5501 | case 2: |
5502 | type.bitfield.word = 1; | |
5503 | break; | |
5504 | case 4: | |
5505 | type.bitfield.dword = 1; | |
5506 | break; | |
8e6e0792 JB |
5507 | case 8: |
5508 | type.bitfield.qword = 1; | |
5509 | break; | |
5510 | case 16: | |
5511 | type.bitfield.xmmword = 1; | |
5512 | break; | |
5513 | case 32: | |
5514 | type.bitfield.ymmword = 1; | |
5515 | break; | |
5516 | case 64: | |
5517 | type.bitfield.zmmword = 1; | |
5518 | break; | |
5519 | default: | |
5520 | goto bad_broadcast; | |
5521 | } | |
5522 | ||
5523 | overlap = operand_type_and (type, t->operand_types[op]); | |
5524 | if (operand_type_all_zero (&overlap)) | |
5525 | goto bad_broadcast; | |
5526 | ||
5527 | if (t->opcode_modifier.checkregsize) | |
5528 | { | |
5529 | unsigned int j; | |
5530 | ||
e2195274 | 5531 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
5532 | for (j = 0; j < i.operands; ++j) |
5533 | { | |
5534 | if (j != op | |
5535 | && !operand_type_register_match(i.types[j], | |
5536 | t->operand_types[j], | |
5537 | type, | |
5538 | t->operand_types[op])) | |
5539 | goto bad_broadcast; | |
5540 | } | |
5541 | } | |
43234a1e L |
5542 | } |
5543 | /* If broadcast is supported in this instruction, we need to check if | |
5544 | operand of one-element size isn't specified without broadcast. */ | |
5545 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
5546 | { | |
5547 | /* Find memory operand. */ | |
5548 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 5549 | if (i.flags[op] & Operand_Mem) |
43234a1e L |
5550 | break; |
5551 | gas_assert (op < i.operands); | |
5552 | /* Check size of the memory operand. */ | |
4a1b91ea | 5553 | if (match_broadcast_size (t, op)) |
43234a1e L |
5554 | { |
5555 | i.error = broadcast_needed; | |
5556 | return 1; | |
5557 | } | |
5558 | } | |
c39e5b26 JB |
5559 | else |
5560 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
5561 | |
5562 | /* Check if requested masking is supported. */ | |
ae2387fe | 5563 | if (i.mask) |
43234a1e | 5564 | { |
ae2387fe JB |
5565 | switch (t->opcode_modifier.masking) |
5566 | { | |
5567 | case BOTH_MASKING: | |
5568 | break; | |
5569 | case MERGING_MASKING: | |
5570 | if (i.mask->zeroing) | |
5571 | { | |
5572 | case 0: | |
5573 | i.error = unsupported_masking; | |
5574 | return 1; | |
5575 | } | |
5576 | break; | |
5577 | case DYNAMIC_MASKING: | |
5578 | /* Memory destinations allow only merging masking. */ | |
5579 | if (i.mask->zeroing && i.mem_operands) | |
5580 | { | |
5581 | /* Find memory operand. */ | |
5582 | for (op = 0; op < i.operands; op++) | |
c48dadc9 | 5583 | if (i.flags[op] & Operand_Mem) |
ae2387fe JB |
5584 | break; |
5585 | gas_assert (op < i.operands); | |
5586 | if (op == i.operands - 1) | |
5587 | { | |
5588 | i.error = unsupported_masking; | |
5589 | return 1; | |
5590 | } | |
5591 | } | |
5592 | break; | |
5593 | default: | |
5594 | abort (); | |
5595 | } | |
43234a1e L |
5596 | } |
5597 | ||
5598 | /* Check if masking is applied to dest operand. */ | |
5599 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
5600 | { | |
5601 | i.error = mask_not_on_destination; | |
5602 | return 1; | |
5603 | } | |
5604 | ||
43234a1e L |
5605 | /* Check RC/SAE. */ |
5606 | if (i.rounding) | |
5607 | { | |
a80195f1 JB |
5608 | if (!t->opcode_modifier.sae |
5609 | || (i.rounding->type != saeonly && !t->opcode_modifier.staticrounding)) | |
43234a1e L |
5610 | { |
5611 | i.error = unsupported_rc_sae; | |
5612 | return 1; | |
5613 | } | |
5614 | /* If the instruction has several immediate operands and one of | |
5615 | them is rounding, the rounding operand should be the last | |
5616 | immediate operand. */ | |
5617 | if (i.imm_operands > 1 | |
5618 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 5619 | { |
43234a1e | 5620 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
5621 | return 1; |
5622 | } | |
6c30d220 L |
5623 | } |
5624 | ||
43234a1e | 5625 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
5626 | if (t->opcode_modifier.disp8memshift |
5627 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
5628 | { |
5629 | if (i.broadcast) | |
4a1b91ea | 5630 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 5631 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 5632 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
5633 | else |
5634 | { | |
5635 | const i386_operand_type *type = NULL; | |
5636 | ||
5637 | i.memshift = 0; | |
5638 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 5639 | if (i.flags[op] & Operand_Mem) |
7091c612 | 5640 | { |
4174bfff JB |
5641 | if (t->opcode_modifier.evex == EVEXLIG) |
5642 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
5643 | else if (t->operand_types[op].bitfield.xmmword | |
5644 | + t->operand_types[op].bitfield.ymmword | |
5645 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
5646 | type = &t->operand_types[op]; |
5647 | else if (!i.types[op].bitfield.unspecified) | |
5648 | type = &i.types[op]; | |
5649 | } | |
3528c362 | 5650 | else if (i.types[op].bitfield.class == RegSIMD |
4174bfff | 5651 | && t->opcode_modifier.evex != EVEXLIG) |
7091c612 JB |
5652 | { |
5653 | if (i.types[op].bitfield.zmmword) | |
5654 | i.memshift = 6; | |
5655 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
5656 | i.memshift = 5; | |
5657 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
5658 | i.memshift = 4; | |
5659 | } | |
5660 | ||
5661 | if (type) | |
5662 | { | |
5663 | if (type->bitfield.zmmword) | |
5664 | i.memshift = 6; | |
5665 | else if (type->bitfield.ymmword) | |
5666 | i.memshift = 5; | |
5667 | else if (type->bitfield.xmmword) | |
5668 | i.memshift = 4; | |
5669 | } | |
5670 | ||
5671 | /* For the check in fits_in_disp8(). */ | |
5672 | if (i.memshift == 0) | |
5673 | i.memshift = -1; | |
5674 | } | |
43234a1e L |
5675 | |
5676 | for (op = 0; op < i.operands; op++) | |
5677 | if (operand_type_check (i.types[op], disp) | |
5678 | && i.op[op].disps->X_op == O_constant) | |
5679 | { | |
b5014f7a | 5680 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 5681 | { |
b5014f7a JB |
5682 | i.types[op].bitfield.disp8 = 1; |
5683 | return 0; | |
43234a1e | 5684 | } |
b5014f7a | 5685 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
5686 | } |
5687 | } | |
b5014f7a JB |
5688 | |
5689 | i.memshift = 0; | |
43234a1e | 5690 | |
6c30d220 L |
5691 | return 0; |
5692 | } | |
5693 | ||
43f3e2ee | 5694 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
5695 | operand types. */ |
5696 | ||
5697 | static int | |
5698 | VEX_check_operands (const insn_template *t) | |
5699 | { | |
86fa6981 | 5700 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 5701 | { |
86fa6981 | 5702 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 5703 | if (!is_evex_encoding (t)) |
86fa6981 L |
5704 | { |
5705 | i.error = unsupported; | |
5706 | return 1; | |
5707 | } | |
5708 | return 0; | |
43234a1e L |
5709 | } |
5710 | ||
a683cc34 | 5711 | if (!t->opcode_modifier.vex) |
86fa6981 L |
5712 | { |
5713 | /* This instruction template doesn't have VEX prefix. */ | |
5714 | if (i.vec_encoding != vex_encoding_default) | |
5715 | { | |
5716 | i.error = unsupported; | |
5717 | return 1; | |
5718 | } | |
5719 | return 0; | |
5720 | } | |
a683cc34 | 5721 | |
9d3bf266 JB |
5722 | /* Check the special Imm4 cases; must be the first operand. */ |
5723 | if (t->cpu_flags.bitfield.cpuxop && t->operands == 5) | |
a683cc34 SP |
5724 | { |
5725 | if (i.op[0].imms->X_op != O_constant | |
5726 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 5727 | { |
a65babc9 | 5728 | i.error = bad_imm4; |
891edac4 L |
5729 | return 1; |
5730 | } | |
a683cc34 | 5731 | |
9d3bf266 JB |
5732 | /* Turn off Imm<N> so that update_imm won't complain. */ |
5733 | operand_type_set (&i.types[0], 0); | |
a683cc34 SP |
5734 | } |
5735 | ||
5736 | return 0; | |
5737 | } | |
5738 | ||
d3ce72d0 | 5739 | static const insn_template * |
83b16ac6 | 5740 | match_template (char mnem_suffix) |
29b0f896 AM |
5741 | { |
5742 | /* Points to template once we've found it. */ | |
d3ce72d0 | 5743 | const insn_template *t; |
40fb9820 | 5744 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 5745 | i386_operand_type overlap4; |
29b0f896 | 5746 | unsigned int found_reverse_match; |
dc2be329 | 5747 | i386_opcode_modifier suffix_check; |
40fb9820 | 5748 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 5749 | int addr_prefix_disp; |
45a4bb20 | 5750 | unsigned int j, size_match, check_register; |
5614d22c | 5751 | enum i386_error specific_error = 0; |
29b0f896 | 5752 | |
c0f3af97 L |
5753 | #if MAX_OPERANDS != 5 |
5754 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
5755 | #endif |
5756 | ||
29b0f896 | 5757 | found_reverse_match = 0; |
539e75ad | 5758 | addr_prefix_disp = -1; |
40fb9820 | 5759 | |
dc2be329 | 5760 | /* Prepare for mnemonic suffix check. */ |
40fb9820 | 5761 | memset (&suffix_check, 0, sizeof (suffix_check)); |
dc2be329 L |
5762 | switch (mnem_suffix) |
5763 | { | |
5764 | case BYTE_MNEM_SUFFIX: | |
5765 | suffix_check.no_bsuf = 1; | |
5766 | break; | |
5767 | case WORD_MNEM_SUFFIX: | |
5768 | suffix_check.no_wsuf = 1; | |
5769 | break; | |
5770 | case SHORT_MNEM_SUFFIX: | |
5771 | suffix_check.no_ssuf = 1; | |
5772 | break; | |
5773 | case LONG_MNEM_SUFFIX: | |
5774 | suffix_check.no_lsuf = 1; | |
5775 | break; | |
5776 | case QWORD_MNEM_SUFFIX: | |
5777 | suffix_check.no_qsuf = 1; | |
5778 | break; | |
5779 | default: | |
5780 | /* NB: In Intel syntax, normally we can check for memory operand | |
5781 | size when there is no mnemonic suffix. But jmp and call have | |
5782 | 2 different encodings with Dword memory operand size, one with | |
5783 | No_ldSuf and the other without. i.suffix is set to | |
5784 | LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */ | |
5785 | if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
5786 | suffix_check.no_ldsuf = 1; | |
83b16ac6 JB |
5787 | } |
5788 | ||
01559ecc L |
5789 | /* Must have right number of operands. */ |
5790 | i.error = number_of_operands_mismatch; | |
5791 | ||
45aa61fe | 5792 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 5793 | { |
539e75ad | 5794 | addr_prefix_disp = -1; |
dbbc8b7e | 5795 | found_reverse_match = 0; |
539e75ad | 5796 | |
29b0f896 AM |
5797 | if (i.operands != t->operands) |
5798 | continue; | |
5799 | ||
50aecf8c | 5800 | /* Check processor support. */ |
a65babc9 | 5801 | i.error = unsupported; |
45a4bb20 | 5802 | if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH) |
50aecf8c L |
5803 | continue; |
5804 | ||
e1d4d893 | 5805 | /* Check AT&T mnemonic. */ |
a65babc9 | 5806 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 5807 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
5808 | continue; |
5809 | ||
4b5aaf5f | 5810 | /* Check AT&T/Intel syntax. */ |
a65babc9 | 5811 | i.error = unsupported_syntax; |
5c07affc | 5812 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
4b5aaf5f | 5813 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) |
1efbbeb4 L |
5814 | continue; |
5815 | ||
4b5aaf5f L |
5816 | /* Check Intel64/AMD64 ISA. */ |
5817 | switch (isa64) | |
5818 | { | |
5819 | default: | |
5820 | /* Default: Don't accept Intel64. */ | |
5821 | if (t->opcode_modifier.isa64 == INTEL64) | |
5822 | continue; | |
5823 | break; | |
5824 | case amd64: | |
5825 | /* -mamd64: Don't accept Intel64 and Intel64 only. */ | |
5826 | if (t->opcode_modifier.isa64 >= INTEL64) | |
5827 | continue; | |
5828 | break; | |
5829 | case intel64: | |
5830 | /* -mintel64: Don't accept AMD64. */ | |
5990e377 | 5831 | if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT) |
4b5aaf5f L |
5832 | continue; |
5833 | break; | |
5834 | } | |
5835 | ||
dc2be329 | 5836 | /* Check the suffix. */ |
a65babc9 | 5837 | i.error = invalid_instruction_suffix; |
dc2be329 L |
5838 | if ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) |
5839 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
5840 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
5841 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
5842 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
5843 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)) | |
83b16ac6 | 5844 | continue; |
29b0f896 | 5845 | |
3ac21baa JB |
5846 | size_match = operand_size_match (t); |
5847 | if (!size_match) | |
7d5e4556 | 5848 | continue; |
539e75ad | 5849 | |
6f2f06be JB |
5850 | /* This is intentionally not |
5851 | ||
0cfa3eb3 | 5852 | if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)) |
6f2f06be JB |
5853 | |
5854 | as the case of a missing * on the operand is accepted (perhaps with | |
5855 | a warning, issued further down). */ | |
0cfa3eb3 | 5856 | if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
6f2f06be JB |
5857 | { |
5858 | i.error = operand_type_mismatch; | |
5859 | continue; | |
5860 | } | |
5861 | ||
5c07affc L |
5862 | for (j = 0; j < MAX_OPERANDS; j++) |
5863 | operand_types[j] = t->operand_types[j]; | |
5864 | ||
45aa61fe AM |
5865 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
5866 | if (i.suffix == QWORD_MNEM_SUFFIX | |
5867 | && flag_code != CODE_64BIT | |
5868 | && (intel_syntax | |
40fb9820 | 5869 | ? (!t->opcode_modifier.ignoresize |
625cbd7a | 5870 | && !t->opcode_modifier.broadcast |
45aa61fe AM |
5871 | && !intel_float_operand (t->name)) |
5872 | : intel_float_operand (t->name) != 2) | |
3528c362 JB |
5873 | && ((operand_types[0].bitfield.class != RegMMX |
5874 | && operand_types[0].bitfield.class != RegSIMD) | |
5875 | || (operand_types[t->operands > 1].bitfield.class != RegMMX | |
5876 | && operand_types[t->operands > 1].bitfield.class != RegSIMD)) | |
45aa61fe AM |
5877 | && (t->base_opcode != 0x0fc7 |
5878 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
5879 | continue; | |
5880 | ||
192dc9c6 JB |
5881 | /* In general, don't allow 32-bit operands on pre-386. */ |
5882 | else if (i.suffix == LONG_MNEM_SUFFIX | |
5883 | && !cpu_arch_flags.bitfield.cpui386 | |
5884 | && (intel_syntax | |
5885 | ? (!t->opcode_modifier.ignoresize | |
5886 | && !intel_float_operand (t->name)) | |
5887 | : intel_float_operand (t->name) != 2) | |
3528c362 JB |
5888 | && ((operand_types[0].bitfield.class != RegMMX |
5889 | && operand_types[0].bitfield.class != RegSIMD) | |
5890 | || (operand_types[t->operands > 1].bitfield.class != RegMMX | |
5891 | && operand_types[t->operands > 1].bitfield.class | |
5892 | != RegSIMD))) | |
192dc9c6 JB |
5893 | continue; |
5894 | ||
29b0f896 | 5895 | /* Do not verify operands when there are none. */ |
50aecf8c | 5896 | else |
29b0f896 | 5897 | { |
c6fb90c8 | 5898 | if (!t->operands) |
2dbab7d5 L |
5899 | /* We've found a match; break out of loop. */ |
5900 | break; | |
29b0f896 | 5901 | } |
252b5132 | 5902 | |
48bcea9f JB |
5903 | if (!t->opcode_modifier.jump |
5904 | || t->opcode_modifier.jump == JUMP_ABSOLUTE) | |
5905 | { | |
5906 | /* There should be only one Disp operand. */ | |
5907 | for (j = 0; j < MAX_OPERANDS; j++) | |
5908 | if (operand_type_check (operand_types[j], disp)) | |
539e75ad | 5909 | break; |
48bcea9f JB |
5910 | if (j < MAX_OPERANDS) |
5911 | { | |
5912 | bfd_boolean override = (i.prefix[ADDR_PREFIX] != 0); | |
5913 | ||
5914 | addr_prefix_disp = j; | |
5915 | ||
5916 | /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16 | |
5917 | operand into Disp32/Disp32/Disp16/Disp32 operand. */ | |
5918 | switch (flag_code) | |
40fb9820 | 5919 | { |
48bcea9f JB |
5920 | case CODE_16BIT: |
5921 | override = !override; | |
5922 | /* Fall through. */ | |
5923 | case CODE_32BIT: | |
5924 | if (operand_types[j].bitfield.disp32 | |
5925 | && operand_types[j].bitfield.disp16) | |
40fb9820 | 5926 | { |
48bcea9f JB |
5927 | operand_types[j].bitfield.disp16 = override; |
5928 | operand_types[j].bitfield.disp32 = !override; | |
40fb9820 | 5929 | } |
48bcea9f JB |
5930 | operand_types[j].bitfield.disp32s = 0; |
5931 | operand_types[j].bitfield.disp64 = 0; | |
5932 | break; | |
5933 | ||
5934 | case CODE_64BIT: | |
5935 | if (operand_types[j].bitfield.disp32s | |
5936 | || operand_types[j].bitfield.disp64) | |
40fb9820 | 5937 | { |
48bcea9f JB |
5938 | operand_types[j].bitfield.disp64 &= !override; |
5939 | operand_types[j].bitfield.disp32s &= !override; | |
5940 | operand_types[j].bitfield.disp32 = override; | |
40fb9820 | 5941 | } |
48bcea9f JB |
5942 | operand_types[j].bitfield.disp16 = 0; |
5943 | break; | |
40fb9820 | 5944 | } |
539e75ad | 5945 | } |
48bcea9f | 5946 | } |
539e75ad | 5947 | |
02a86693 L |
5948 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
5949 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
5950 | continue; | |
5951 | ||
56ffb741 | 5952 | /* We check register size if needed. */ |
e2195274 JB |
5953 | if (t->opcode_modifier.checkregsize) |
5954 | { | |
5955 | check_register = (1 << t->operands) - 1; | |
5956 | if (i.broadcast) | |
5957 | check_register &= ~(1 << i.broadcast->operand); | |
5958 | } | |
5959 | else | |
5960 | check_register = 0; | |
5961 | ||
c6fb90c8 | 5962 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
5963 | switch (t->operands) |
5964 | { | |
5965 | case 1: | |
40fb9820 | 5966 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
5967 | continue; |
5968 | break; | |
5969 | case 2: | |
33eaf5de | 5970 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
5971 | only in 32bit mode and we can use opcode 0x90. In 64bit |
5972 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
5973 | zero-extend %eax to %rax. */ | |
5974 | if (flag_code == CODE_64BIT | |
5975 | && t->base_opcode == 0x90 | |
75e5731b JB |
5976 | && i.types[0].bitfield.instance == Accum |
5977 | && i.types[0].bitfield.dword | |
5978 | && i.types[1].bitfield.instance == Accum | |
5979 | && i.types[1].bitfield.dword) | |
8b38ad71 | 5980 | continue; |
1212781b JB |
5981 | /* xrelease mov %eax, <disp> is another special case. It must not |
5982 | match the accumulator-only encoding of mov. */ | |
5983 | if (flag_code != CODE_64BIT | |
5984 | && i.hle_prefix | |
5985 | && t->base_opcode == 0xa0 | |
75e5731b | 5986 | && i.types[0].bitfield.instance == Accum |
8dc0818e | 5987 | && (i.flags[1] & Operand_Mem)) |
1212781b | 5988 | continue; |
f5eb1d70 JB |
5989 | /* Fall through. */ |
5990 | ||
5991 | case 3: | |
3ac21baa JB |
5992 | if (!(size_match & MATCH_STRAIGHT)) |
5993 | goto check_reverse; | |
64c49ab3 JB |
5994 | /* Reverse direction of operands if swapping is possible in the first |
5995 | place (operands need to be symmetric) and | |
5996 | - the load form is requested, and the template is a store form, | |
5997 | - the store form is requested, and the template is a load form, | |
5998 | - the non-default (swapped) form is requested. */ | |
5999 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
f5eb1d70 | 6000 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
6001 | && !operand_type_all_zero (&overlap1)) |
6002 | switch (i.dir_encoding) | |
6003 | { | |
6004 | case dir_encoding_load: | |
6005 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6006 | || t->opcode_modifier.regmem) |
64c49ab3 JB |
6007 | goto check_reverse; |
6008 | break; | |
6009 | ||
6010 | case dir_encoding_store: | |
6011 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6012 | && !t->opcode_modifier.regmem) |
64c49ab3 JB |
6013 | goto check_reverse; |
6014 | break; | |
6015 | ||
6016 | case dir_encoding_swap: | |
6017 | goto check_reverse; | |
6018 | ||
6019 | case dir_encoding_default: | |
6020 | break; | |
6021 | } | |
86fa6981 | 6022 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
6023 | if ((i.dir_encoding == dir_encoding_store |
6024 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
6025 | && i.mem_operands == 0 |
6026 | && t->opcode_modifier.load) | |
fa99fab2 | 6027 | continue; |
1a0670f3 | 6028 | /* Fall through. */ |
f48ff2ae | 6029 | case 4: |
c0f3af97 | 6030 | case 5: |
c6fb90c8 | 6031 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
6032 | if (!operand_type_match (overlap0, i.types[0]) |
6033 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 6034 | || ((check_register & 3) == 3 |
dc821c5f | 6035 | && !operand_type_register_match (i.types[0], |
40fb9820 | 6036 | operand_types[0], |
dc821c5f | 6037 | i.types[1], |
40fb9820 | 6038 | operand_types[1]))) |
29b0f896 AM |
6039 | { |
6040 | /* Check if other direction is valid ... */ | |
38e314eb | 6041 | if (!t->opcode_modifier.d) |
29b0f896 AM |
6042 | continue; |
6043 | ||
b6169b20 | 6044 | check_reverse: |
3ac21baa JB |
6045 | if (!(size_match & MATCH_REVERSE)) |
6046 | continue; | |
29b0f896 | 6047 | /* Try reversing direction of operands. */ |
f5eb1d70 JB |
6048 | overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]); |
6049 | overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]); | |
40fb9820 | 6050 | if (!operand_type_match (overlap0, i.types[0]) |
f5eb1d70 | 6051 | || !operand_type_match (overlap1, i.types[i.operands - 1]) |
45664ddb | 6052 | || (check_register |
dc821c5f | 6053 | && !operand_type_register_match (i.types[0], |
f5eb1d70 JB |
6054 | operand_types[i.operands - 1], |
6055 | i.types[i.operands - 1], | |
45664ddb | 6056 | operand_types[0]))) |
29b0f896 AM |
6057 | { |
6058 | /* Does not match either direction. */ | |
6059 | continue; | |
6060 | } | |
38e314eb | 6061 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 6062 | we've found. */ |
38e314eb JB |
6063 | if (!t->opcode_modifier.d) |
6064 | found_reverse_match = 0; | |
6065 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 | 6066 | found_reverse_match = Opcode_FloatD; |
dbbc8b7e | 6067 | else if (operand_types[0].bitfield.xmmword |
f5eb1d70 | 6068 | || operand_types[i.operands - 1].bitfield.xmmword |
3528c362 JB |
6069 | || operand_types[0].bitfield.class == RegMMX |
6070 | || operand_types[i.operands - 1].bitfield.class == RegMMX | |
dbbc8b7e JB |
6071 | || is_any_vex_encoding(t)) |
6072 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e | |
6073 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
8a2ed489 | 6074 | else |
38e314eb | 6075 | found_reverse_match = Opcode_D; |
40fb9820 | 6076 | if (t->opcode_modifier.floatr) |
8a2ed489 | 6077 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 6078 | } |
f48ff2ae | 6079 | else |
29b0f896 | 6080 | { |
f48ff2ae | 6081 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
6082 | switch (t->operands) |
6083 | { | |
c0f3af97 L |
6084 | case 5: |
6085 | overlap4 = operand_type_and (i.types[4], | |
6086 | operand_types[4]); | |
1a0670f3 | 6087 | /* Fall through. */ |
d1cbb4db | 6088 | case 4: |
c6fb90c8 L |
6089 | overlap3 = operand_type_and (i.types[3], |
6090 | operand_types[3]); | |
1a0670f3 | 6091 | /* Fall through. */ |
d1cbb4db | 6092 | case 3: |
c6fb90c8 L |
6093 | overlap2 = operand_type_and (i.types[2], |
6094 | operand_types[2]); | |
d1cbb4db L |
6095 | break; |
6096 | } | |
29b0f896 | 6097 | |
f48ff2ae L |
6098 | switch (t->operands) |
6099 | { | |
c0f3af97 L |
6100 | case 5: |
6101 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 6102 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 6103 | operand_types[3], |
c0f3af97 L |
6104 | i.types[4], |
6105 | operand_types[4])) | |
6106 | continue; | |
1a0670f3 | 6107 | /* Fall through. */ |
f48ff2ae | 6108 | case 4: |
40fb9820 | 6109 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
6110 | || ((check_register & 0xa) == 0xa |
6111 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
6112 | operand_types[1], |
6113 | i.types[3], | |
e2195274 JB |
6114 | operand_types[3])) |
6115 | || ((check_register & 0xc) == 0xc | |
6116 | && !operand_type_register_match (i.types[2], | |
6117 | operand_types[2], | |
6118 | i.types[3], | |
6119 | operand_types[3]))) | |
f48ff2ae | 6120 | continue; |
1a0670f3 | 6121 | /* Fall through. */ |
f48ff2ae L |
6122 | case 3: |
6123 | /* Here we make use of the fact that there are no | |
23e42951 | 6124 | reverse match 3 operand instructions. */ |
40fb9820 | 6125 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
6126 | || ((check_register & 5) == 5 |
6127 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
6128 | operand_types[0], |
6129 | i.types[2], | |
e2195274 JB |
6130 | operand_types[2])) |
6131 | || ((check_register & 6) == 6 | |
6132 | && !operand_type_register_match (i.types[1], | |
6133 | operand_types[1], | |
6134 | i.types[2], | |
6135 | operand_types[2]))) | |
f48ff2ae L |
6136 | continue; |
6137 | break; | |
6138 | } | |
29b0f896 | 6139 | } |
f48ff2ae | 6140 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
6141 | slip through to break. */ |
6142 | } | |
c0f3af97 | 6143 | |
5614d22c JB |
6144 | /* Check if vector and VEX operands are valid. */ |
6145 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
6146 | { | |
6147 | specific_error = i.error; | |
6148 | continue; | |
6149 | } | |
a683cc34 | 6150 | |
29b0f896 AM |
6151 | /* We've found a match; break out of loop. */ |
6152 | break; | |
6153 | } | |
6154 | ||
6155 | if (t == current_templates->end) | |
6156 | { | |
6157 | /* We found no match. */ | |
a65babc9 | 6158 | const char *err_msg; |
5614d22c | 6159 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
6160 | { |
6161 | default: | |
6162 | abort (); | |
86e026a4 | 6163 | case operand_size_mismatch: |
a65babc9 L |
6164 | err_msg = _("operand size mismatch"); |
6165 | break; | |
6166 | case operand_type_mismatch: | |
6167 | err_msg = _("operand type mismatch"); | |
6168 | break; | |
6169 | case register_type_mismatch: | |
6170 | err_msg = _("register type mismatch"); | |
6171 | break; | |
6172 | case number_of_operands_mismatch: | |
6173 | err_msg = _("number of operands mismatch"); | |
6174 | break; | |
6175 | case invalid_instruction_suffix: | |
6176 | err_msg = _("invalid instruction suffix"); | |
6177 | break; | |
6178 | case bad_imm4: | |
4a2608e3 | 6179 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 6180 | break; |
a65babc9 L |
6181 | case unsupported_with_intel_mnemonic: |
6182 | err_msg = _("unsupported with Intel mnemonic"); | |
6183 | break; | |
6184 | case unsupported_syntax: | |
6185 | err_msg = _("unsupported syntax"); | |
6186 | break; | |
6187 | case unsupported: | |
35262a23 | 6188 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
6189 | current_templates->start->name); |
6190 | return NULL; | |
6c30d220 L |
6191 | case invalid_vsib_address: |
6192 | err_msg = _("invalid VSIB address"); | |
6193 | break; | |
7bab8ab5 JB |
6194 | case invalid_vector_register_set: |
6195 | err_msg = _("mask, index, and destination registers must be distinct"); | |
6196 | break; | |
6c30d220 L |
6197 | case unsupported_vector_index_register: |
6198 | err_msg = _("unsupported vector index register"); | |
6199 | break; | |
43234a1e L |
6200 | case unsupported_broadcast: |
6201 | err_msg = _("unsupported broadcast"); | |
6202 | break; | |
43234a1e L |
6203 | case broadcast_needed: |
6204 | err_msg = _("broadcast is needed for operand of such type"); | |
6205 | break; | |
6206 | case unsupported_masking: | |
6207 | err_msg = _("unsupported masking"); | |
6208 | break; | |
6209 | case mask_not_on_destination: | |
6210 | err_msg = _("mask not on destination operand"); | |
6211 | break; | |
6212 | case no_default_mask: | |
6213 | err_msg = _("default mask isn't allowed"); | |
6214 | break; | |
6215 | case unsupported_rc_sae: | |
6216 | err_msg = _("unsupported static rounding/sae"); | |
6217 | break; | |
6218 | case rc_sae_operand_not_last_imm: | |
6219 | if (intel_syntax) | |
6220 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
6221 | else | |
6222 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
6223 | break; | |
6224 | case invalid_register_operand: | |
6225 | err_msg = _("invalid register operand"); | |
6226 | break; | |
a65babc9 L |
6227 | } |
6228 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 6229 | current_templates->start->name); |
fa99fab2 | 6230 | return NULL; |
29b0f896 | 6231 | } |
252b5132 | 6232 | |
29b0f896 AM |
6233 | if (!quiet_warnings) |
6234 | { | |
6235 | if (!intel_syntax | |
0cfa3eb3 | 6236 | && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))) |
6f2f06be | 6237 | as_warn (_("indirect %s without `*'"), t->name); |
29b0f896 | 6238 | |
40fb9820 L |
6239 | if (t->opcode_modifier.isprefix |
6240 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
6241 | { |
6242 | /* Warn them that a data or address size prefix doesn't | |
6243 | affect assembly of the next line of code. */ | |
6244 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
6245 | } | |
6246 | } | |
6247 | ||
6248 | /* Copy the template we found. */ | |
6249 | i.tm = *t; | |
539e75ad L |
6250 | |
6251 | if (addr_prefix_disp != -1) | |
6252 | i.tm.operand_types[addr_prefix_disp] | |
6253 | = operand_types[addr_prefix_disp]; | |
6254 | ||
29b0f896 AM |
6255 | if (found_reverse_match) |
6256 | { | |
dfd69174 JB |
6257 | /* If we found a reverse match we must alter the opcode direction |
6258 | bit and clear/flip the regmem modifier one. found_reverse_match | |
6259 | holds bits to change (different for int & float insns). */ | |
29b0f896 AM |
6260 | |
6261 | i.tm.base_opcode ^= found_reverse_match; | |
6262 | ||
f5eb1d70 JB |
6263 | i.tm.operand_types[0] = operand_types[i.operands - 1]; |
6264 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
dfd69174 JB |
6265 | |
6266 | /* Certain SIMD insns have their load forms specified in the opcode | |
6267 | table, and hence we need to _set_ RegMem instead of clearing it. | |
6268 | We need to avoid setting the bit though on insns like KMOVW. */ | |
6269 | i.tm.opcode_modifier.regmem | |
6270 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d | |
6271 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx | |
6272 | && !i.tm.opcode_modifier.regmem; | |
29b0f896 AM |
6273 | } |
6274 | ||
fa99fab2 | 6275 | return t; |
29b0f896 AM |
6276 | } |
6277 | ||
6278 | static int | |
e3bb37b5 | 6279 | check_string (void) |
29b0f896 | 6280 | { |
51c8edf6 JB |
6281 | unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0; |
6282 | unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0; | |
8dc0818e | 6283 | |
51c8edf6 | 6284 | if (i.seg[op] != NULL && i.seg[op] != &es) |
29b0f896 | 6285 | { |
51c8edf6 JB |
6286 | as_bad (_("`%s' operand %u must use `%ses' segment"), |
6287 | i.tm.name, | |
6288 | intel_syntax ? i.tm.operands - es_op : es_op + 1, | |
6289 | register_prefix); | |
6290 | return 0; | |
29b0f896 | 6291 | } |
51c8edf6 JB |
6292 | |
6293 | /* There's only ever one segment override allowed per instruction. | |
6294 | This instruction possibly has a legal segment override on the | |
6295 | second operand, so copy the segment to where non-string | |
6296 | instructions store it, allowing common code. */ | |
6297 | i.seg[op] = i.seg[1]; | |
6298 | ||
29b0f896 AM |
6299 | return 1; |
6300 | } | |
6301 | ||
6302 | static int | |
543613e9 | 6303 | process_suffix (void) |
29b0f896 AM |
6304 | { |
6305 | /* If matched instruction specifies an explicit instruction mnemonic | |
6306 | suffix, use it. */ | |
673fe0f0 | 6307 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 6308 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 6309 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 6310 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 6311 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 6312 | i.suffix = QWORD_MNEM_SUFFIX; |
13e600d0 JB |
6313 | else if (i.reg_operands |
6314 | && (i.operands > 1 || i.types[0].bitfield.class == Reg)) | |
29b0f896 AM |
6315 | { |
6316 | /* If there's no instruction mnemonic suffix we try to invent one | |
13e600d0 | 6317 | based on GPR operands. */ |
29b0f896 AM |
6318 | if (!i.suffix) |
6319 | { | |
6320 | /* We take i.suffix from the last register operand specified, | |
6321 | Destination register type is more significant than source | |
381d071f L |
6322 | register type. crc32 in SSE4.2 prefers source register |
6323 | type. */ | |
1a035124 | 6324 | unsigned int op = i.tm.base_opcode != 0xf20f38f0 ? i.operands : 1; |
20592a94 | 6325 | |
1a035124 JB |
6326 | while (op--) |
6327 | if (i.tm.operand_types[op].bitfield.instance == InstanceNone | |
6328 | || i.tm.operand_types[op].bitfield.instance == Accum) | |
6329 | { | |
6330 | if (i.types[op].bitfield.class != Reg) | |
6331 | continue; | |
6332 | if (i.types[op].bitfield.byte) | |
6333 | i.suffix = BYTE_MNEM_SUFFIX; | |
6334 | else if (i.types[op].bitfield.word) | |
6335 | i.suffix = WORD_MNEM_SUFFIX; | |
6336 | else if (i.types[op].bitfield.dword) | |
6337 | i.suffix = LONG_MNEM_SUFFIX; | |
6338 | else if (i.types[op].bitfield.qword) | |
6339 | i.suffix = QWORD_MNEM_SUFFIX; | |
6340 | else | |
6341 | continue; | |
6342 | break; | |
6343 | } | |
29b0f896 AM |
6344 | } |
6345 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
6346 | { | |
2eb952a4 L |
6347 | if (intel_syntax |
6348 | && i.tm.opcode_modifier.ignoresize | |
6349 | && i.tm.opcode_modifier.no_bsuf) | |
6350 | i.suffix = 0; | |
6351 | else if (!check_byte_reg ()) | |
29b0f896 AM |
6352 | return 0; |
6353 | } | |
6354 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
6355 | { | |
2eb952a4 L |
6356 | if (intel_syntax |
6357 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6358 | && i.tm.opcode_modifier.no_lsuf |
6359 | && !i.tm.opcode_modifier.todword | |
6360 | && !i.tm.opcode_modifier.toqword) | |
2eb952a4 L |
6361 | i.suffix = 0; |
6362 | else if (!check_long_reg ()) | |
29b0f896 AM |
6363 | return 0; |
6364 | } | |
6365 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6366 | { | |
955e1e6a L |
6367 | if (intel_syntax |
6368 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6369 | && i.tm.opcode_modifier.no_qsuf |
6370 | && !i.tm.opcode_modifier.todword | |
6371 | && !i.tm.opcode_modifier.toqword) | |
955e1e6a L |
6372 | i.suffix = 0; |
6373 | else if (!check_qword_reg ()) | |
29b0f896 AM |
6374 | return 0; |
6375 | } | |
6376 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6377 | { | |
2eb952a4 L |
6378 | if (intel_syntax |
6379 | && i.tm.opcode_modifier.ignoresize | |
6380 | && i.tm.opcode_modifier.no_wsuf) | |
6381 | i.suffix = 0; | |
6382 | else if (!check_word_reg ()) | |
29b0f896 AM |
6383 | return 0; |
6384 | } | |
40fb9820 | 6385 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
6386 | /* Do nothing if the instruction is going to ignore the prefix. */ |
6387 | ; | |
6388 | else | |
6389 | abort (); | |
6390 | } | |
62b3f548 | 6391 | else if (i.tm.opcode_modifier.defaultsize && !i.suffix) |
29b0f896 | 6392 | { |
13e600d0 JB |
6393 | i.suffix = stackop_size; |
6394 | if (stackop_size == LONG_MNEM_SUFFIX) | |
06f74c5c L |
6395 | { |
6396 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
6397 | .code16gcc directive to support 16-bit mode with | |
6398 | 32-bit address. For IRET without a suffix, generate | |
6399 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
6400 | handler. */ | |
13e600d0 JB |
6401 | if (i.tm.base_opcode == 0xcf) |
6402 | { | |
6403 | i.suffix = WORD_MNEM_SUFFIX; | |
6404 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
6405 | } | |
6406 | /* Warn about changed behavior for segment register push/pop. */ | |
6407 | else if ((i.tm.base_opcode | 1) == 0x07) | |
6408 | as_warn (_("generating 32-bit `%s', unlike earlier gas versions"), | |
6409 | i.tm.name); | |
06f74c5c | 6410 | } |
29b0f896 | 6411 | } |
c006a730 | 6412 | else if (!i.suffix |
0cfa3eb3 JB |
6413 | && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE |
6414 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
6415 | || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT | |
64e74474 AM |
6416 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
6417 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
6418 | { |
6419 | switch (flag_code) | |
6420 | { | |
6421 | case CODE_64BIT: | |
40fb9820 | 6422 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
6423 | { |
6424 | i.suffix = QWORD_MNEM_SUFFIX; | |
6425 | break; | |
6426 | } | |
1a0670f3 | 6427 | /* Fall through. */ |
9306ca4a | 6428 | case CODE_32BIT: |
40fb9820 | 6429 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
6430 | i.suffix = LONG_MNEM_SUFFIX; |
6431 | break; | |
6432 | case CODE_16BIT: | |
40fb9820 | 6433 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
6434 | i.suffix = WORD_MNEM_SUFFIX; |
6435 | break; | |
6436 | } | |
6437 | } | |
252b5132 | 6438 | |
c006a730 | 6439 | if (!i.suffix |
873494c8 JB |
6440 | && (!i.tm.opcode_modifier.defaultsize |
6441 | /* Also cover lret/retf/iret in 64-bit mode. */ | |
6442 | || (flag_code == CODE_64BIT | |
6443 | && !i.tm.opcode_modifier.no_lsuf | |
6444 | && !i.tm.opcode_modifier.no_qsuf)) | |
62b3f548 JB |
6445 | && !i.tm.opcode_modifier.ignoresize |
6446 | /* Accept FLDENV et al without suffix. */ | |
6447 | && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) | |
29b0f896 | 6448 | { |
6c0946d0 | 6449 | unsigned int suffixes, evex = 0; |
c006a730 JB |
6450 | |
6451 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
6452 | if (!i.tm.opcode_modifier.no_wsuf) | |
6453 | suffixes |= 1 << 1; | |
6454 | if (!i.tm.opcode_modifier.no_lsuf) | |
6455 | suffixes |= 1 << 2; | |
6456 | if (!i.tm.opcode_modifier.no_ldsuf) | |
6457 | suffixes |= 1 << 3; | |
6458 | if (!i.tm.opcode_modifier.no_ssuf) | |
6459 | suffixes |= 1 << 4; | |
6460 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) | |
6461 | suffixes |= 1 << 5; | |
6462 | ||
6c0946d0 JB |
6463 | /* For [XYZ]MMWORD operands inspect operand sizes. While generally |
6464 | also suitable for AT&T syntax mode, it was requested that this be | |
6465 | restricted to just Intel syntax. */ | |
6466 | if (intel_syntax) | |
6467 | { | |
6468 | i386_cpu_flags cpu = cpu_flags_and (i.tm.cpu_flags, avx512); | |
6469 | ||
6470 | if (!cpu_flags_all_zero (&cpu) && !i.broadcast) | |
6471 | { | |
6472 | unsigned int op; | |
6473 | ||
6474 | for (op = 0; op < i.tm.operands; ++op) | |
6475 | { | |
6476 | if (!cpu_arch_flags.bitfield.cpuavx512vl) | |
6477 | { | |
6478 | if (i.tm.operand_types[op].bitfield.ymmword) | |
6479 | i.tm.operand_types[op].bitfield.xmmword = 0; | |
6480 | if (i.tm.operand_types[op].bitfield.zmmword) | |
6481 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
6482 | if (!i.tm.opcode_modifier.evex | |
6483 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
6484 | i.tm.opcode_modifier.evex = EVEX512; | |
6485 | } | |
6486 | ||
6487 | if (i.tm.operand_types[op].bitfield.xmmword | |
6488 | + i.tm.operand_types[op].bitfield.ymmword | |
6489 | + i.tm.operand_types[op].bitfield.zmmword < 2) | |
6490 | continue; | |
6491 | ||
6492 | /* Any properly sized operand disambiguates the insn. */ | |
6493 | if (i.types[op].bitfield.xmmword | |
6494 | || i.types[op].bitfield.ymmword | |
6495 | || i.types[op].bitfield.zmmword) | |
6496 | { | |
6497 | suffixes &= ~(7 << 6); | |
6498 | evex = 0; | |
6499 | break; | |
6500 | } | |
6501 | ||
6502 | if ((i.flags[op] & Operand_Mem) | |
6503 | && i.tm.operand_types[op].bitfield.unspecified) | |
6504 | { | |
6505 | if (i.tm.operand_types[op].bitfield.xmmword) | |
6506 | suffixes |= 1 << 6; | |
6507 | if (i.tm.operand_types[op].bitfield.ymmword) | |
6508 | suffixes |= 1 << 7; | |
6509 | if (i.tm.operand_types[op].bitfield.zmmword) | |
6510 | suffixes |= 1 << 8; | |
6511 | evex = EVEX512; | |
6512 | } | |
6513 | } | |
6514 | } | |
6515 | } | |
6516 | ||
6517 | /* Are multiple suffixes / operand sizes allowed? */ | |
c006a730 | 6518 | if (suffixes & (suffixes - 1)) |
9306ca4a | 6519 | { |
873494c8 JB |
6520 | if (intel_syntax |
6521 | && (!i.tm.opcode_modifier.defaultsize | |
6522 | || operand_check == check_error)) | |
9306ca4a | 6523 | { |
c006a730 | 6524 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
9306ca4a JB |
6525 | return 0; |
6526 | } | |
c006a730 | 6527 | if (operand_check == check_error) |
9306ca4a | 6528 | { |
c006a730 JB |
6529 | as_bad (_("no instruction mnemonic suffix given and " |
6530 | "no register operands; can't size `%s'"), i.tm.name); | |
9306ca4a JB |
6531 | return 0; |
6532 | } | |
c006a730 | 6533 | if (operand_check == check_warning) |
873494c8 JB |
6534 | as_warn (_("%s; using default for `%s'"), |
6535 | intel_syntax | |
6536 | ? _("ambiguous operand size") | |
6537 | : _("no instruction mnemonic suffix given and " | |
6538 | "no register operands"), | |
6539 | i.tm.name); | |
c006a730 JB |
6540 | |
6541 | if (i.tm.opcode_modifier.floatmf) | |
6542 | i.suffix = SHORT_MNEM_SUFFIX; | |
6c0946d0 JB |
6543 | else if (evex) |
6544 | i.tm.opcode_modifier.evex = evex; | |
c006a730 JB |
6545 | else if (flag_code == CODE_16BIT) |
6546 | i.suffix = WORD_MNEM_SUFFIX; | |
1a035124 | 6547 | else if (!i.tm.opcode_modifier.no_lsuf) |
c006a730 | 6548 | i.suffix = LONG_MNEM_SUFFIX; |
1a035124 JB |
6549 | else |
6550 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a | 6551 | } |
29b0f896 | 6552 | } |
252b5132 | 6553 | |
50128d0c JB |
6554 | if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3) |
6555 | i.short_form = (i.tm.operand_types[0].bitfield.class == Reg) | |
6556 | != (i.tm.operand_types[1].bitfield.class == Reg); | |
6557 | ||
d2224064 JB |
6558 | /* Change the opcode based on the operand size given by i.suffix. */ |
6559 | switch (i.suffix) | |
29b0f896 | 6560 | { |
d2224064 JB |
6561 | /* Size floating point instruction. */ |
6562 | case LONG_MNEM_SUFFIX: | |
6563 | if (i.tm.opcode_modifier.floatmf) | |
6564 | { | |
6565 | i.tm.base_opcode ^= 4; | |
6566 | break; | |
6567 | } | |
6568 | /* fall through */ | |
6569 | case WORD_MNEM_SUFFIX: | |
6570 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 6571 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 6572 | if (i.tm.opcode_modifier.w) |
29b0f896 | 6573 | { |
50128d0c | 6574 | if (i.short_form) |
29b0f896 AM |
6575 | i.tm.base_opcode |= 8; |
6576 | else | |
6577 | i.tm.base_opcode |= 1; | |
6578 | } | |
d2224064 JB |
6579 | /* fall through */ |
6580 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
6581 | /* Now select between word & dword operations via the operand |
6582 | size prefix, except for instructions that will ignore this | |
6583 | prefix anyway. */ | |
75c0a438 | 6584 | if (i.reg_operands > 0 |
bab6aec1 | 6585 | && i.types[0].bitfield.class == Reg |
75c0a438 | 6586 | && i.tm.opcode_modifier.addrprefixopreg |
474da251 | 6587 | && (i.tm.operand_types[0].bitfield.instance == Accum |
75c0a438 | 6588 | || i.operands == 1)) |
cb712a9e | 6589 | { |
ca61edf2 L |
6590 | /* The address size override prefix changes the size of the |
6591 | first operand. */ | |
40fb9820 | 6592 | if ((flag_code == CODE_32BIT |
75c0a438 | 6593 | && i.op[0].regs->reg_type.bitfield.word) |
40fb9820 | 6594 | || (flag_code != CODE_32BIT |
75c0a438 | 6595 | && i.op[0].regs->reg_type.bitfield.dword)) |
cb712a9e L |
6596 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
6597 | return 0; | |
6598 | } | |
6599 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
40fb9820 L |
6600 | && !i.tm.opcode_modifier.ignoresize |
6601 | && !i.tm.opcode_modifier.floatmf | |
a38d7118 | 6602 | && !is_any_vex_encoding (&i.tm) |
cb712a9e L |
6603 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
6604 | || (flag_code == CODE_64BIT | |
0cfa3eb3 | 6605 | && i.tm.opcode_modifier.jump == JUMP_BYTE))) |
24eab124 AM |
6606 | { |
6607 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 6608 | |
0cfa3eb3 | 6609 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */ |
29b0f896 | 6610 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 6611 | |
29b0f896 AM |
6612 | if (!add_prefix (prefix)) |
6613 | return 0; | |
24eab124 | 6614 | } |
252b5132 | 6615 | |
29b0f896 AM |
6616 | /* Set mode64 for an operand. */ |
6617 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 6618 | && flag_code == CODE_64BIT |
d2224064 | 6619 | && !i.tm.opcode_modifier.norex64 |
46e883c5 | 6620 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
6621 | need rex64. */ |
6622 | && ! (i.operands == 2 | |
6623 | && i.tm.base_opcode == 0x90 | |
6624 | && i.tm.extension_opcode == None | |
75e5731b JB |
6625 | && i.types[0].bitfield.instance == Accum |
6626 | && i.types[0].bitfield.qword | |
6627 | && i.types[1].bitfield.instance == Accum | |
6628 | && i.types[1].bitfield.qword)) | |
d2224064 | 6629 | i.rex |= REX_W; |
3e73aa7c | 6630 | |
d2224064 | 6631 | break; |
29b0f896 | 6632 | } |
7ecd2f8b | 6633 | |
c0a30a9f L |
6634 | if (i.reg_operands != 0 |
6635 | && i.operands > 1 | |
6636 | && i.tm.opcode_modifier.addrprefixopreg | |
474da251 | 6637 | && i.tm.operand_types[0].bitfield.instance != Accum) |
c0a30a9f L |
6638 | { |
6639 | /* Check invalid register operand when the address size override | |
6640 | prefix changes the size of register operands. */ | |
6641 | unsigned int op; | |
6642 | enum { need_word, need_dword, need_qword } need; | |
6643 | ||
6644 | if (flag_code == CODE_32BIT) | |
6645 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
6646 | else | |
6647 | { | |
6648 | if (i.prefix[ADDR_PREFIX]) | |
6649 | need = need_dword; | |
6650 | else | |
6651 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
6652 | } | |
6653 | ||
6654 | for (op = 0; op < i.operands; op++) | |
bab6aec1 | 6655 | if (i.types[op].bitfield.class == Reg |
c0a30a9f L |
6656 | && ((need == need_word |
6657 | && !i.op[op].regs->reg_type.bitfield.word) | |
6658 | || (need == need_dword | |
6659 | && !i.op[op].regs->reg_type.bitfield.dword) | |
6660 | || (need == need_qword | |
6661 | && !i.op[op].regs->reg_type.bitfield.qword))) | |
6662 | { | |
6663 | as_bad (_("invalid register operand size for `%s'"), | |
6664 | i.tm.name); | |
6665 | return 0; | |
6666 | } | |
6667 | } | |
6668 | ||
29b0f896 AM |
6669 | return 1; |
6670 | } | |
3e73aa7c | 6671 | |
29b0f896 | 6672 | static int |
543613e9 | 6673 | check_byte_reg (void) |
29b0f896 AM |
6674 | { |
6675 | int op; | |
543613e9 | 6676 | |
29b0f896 AM |
6677 | for (op = i.operands; --op >= 0;) |
6678 | { | |
dc821c5f | 6679 | /* Skip non-register operands. */ |
bab6aec1 | 6680 | if (i.types[op].bitfield.class != Reg) |
dc821c5f JB |
6681 | continue; |
6682 | ||
29b0f896 AM |
6683 | /* If this is an eight bit register, it's OK. If it's the 16 or |
6684 | 32 bit version of an eight bit register, we will just use the | |
6685 | low portion, and that's OK too. */ | |
dc821c5f | 6686 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
6687 | continue; |
6688 | ||
5a819eb9 | 6689 | /* I/O port address operands are OK too. */ |
75e5731b JB |
6690 | if (i.tm.operand_types[op].bitfield.instance == RegD |
6691 | && i.tm.operand_types[op].bitfield.word) | |
5a819eb9 JB |
6692 | continue; |
6693 | ||
9706160a JB |
6694 | /* crc32 only wants its source operand checked here. */ |
6695 | if (i.tm.base_opcode == 0xf20f38f0 && op) | |
9344ff29 L |
6696 | continue; |
6697 | ||
29b0f896 | 6698 | /* Any other register is bad. */ |
bab6aec1 | 6699 | if (i.types[op].bitfield.class == Reg |
3528c362 JB |
6700 | || i.types[op].bitfield.class == RegMMX |
6701 | || i.types[op].bitfield.class == RegSIMD | |
00cee14f | 6702 | || i.types[op].bitfield.class == SReg |
4a5c67ed JB |
6703 | || i.types[op].bitfield.class == RegCR |
6704 | || i.types[op].bitfield.class == RegDR | |
6705 | || i.types[op].bitfield.class == RegTR) | |
29b0f896 | 6706 | { |
a540244d L |
6707 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6708 | register_prefix, | |
29b0f896 AM |
6709 | i.op[op].regs->reg_name, |
6710 | i.tm.name, | |
6711 | i.suffix); | |
6712 | return 0; | |
6713 | } | |
6714 | } | |
6715 | return 1; | |
6716 | } | |
6717 | ||
6718 | static int | |
e3bb37b5 | 6719 | check_long_reg (void) |
29b0f896 AM |
6720 | { |
6721 | int op; | |
6722 | ||
6723 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 6724 | /* Skip non-register operands. */ |
bab6aec1 | 6725 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6726 | continue; |
29b0f896 AM |
6727 | /* Reject eight bit registers, except where the template requires |
6728 | them. (eg. movzb) */ | |
dc821c5f | 6729 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6730 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6731 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6732 | && (i.tm.operand_types[op].bitfield.word |
6733 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6734 | { |
a540244d L |
6735 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6736 | register_prefix, | |
29b0f896 AM |
6737 | i.op[op].regs->reg_name, |
6738 | i.tm.name, | |
6739 | i.suffix); | |
6740 | return 0; | |
6741 | } | |
be4c5e58 L |
6742 | /* Error if the e prefix on a general reg is missing. */ |
6743 | else if (i.types[op].bitfield.word | |
bab6aec1 | 6744 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6745 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6746 | && i.tm.operand_types[op].bitfield.dword) |
29b0f896 | 6747 | { |
be4c5e58 L |
6748 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
6749 | register_prefix, i.op[op].regs->reg_name, | |
6750 | i.suffix); | |
6751 | return 0; | |
252b5132 | 6752 | } |
e4630f71 | 6753 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f | 6754 | else if (i.types[op].bitfield.qword |
bab6aec1 | 6755 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6756 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6757 | && i.tm.operand_types[op].bitfield.dword) |
252b5132 | 6758 | { |
34828aad | 6759 | if (intel_syntax |
bc31405e L |
6760 | && (i.tm.opcode_modifier.toqword |
6761 | /* Also convert to QWORD for MOVSXD. */ | |
6762 | || i.tm.base_opcode == 0x63) | |
3528c362 | 6763 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 6764 | { |
ca61edf2 | 6765 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
6766 | i.suffix = QWORD_MNEM_SUFFIX; |
6767 | } | |
6768 | else | |
6769 | { | |
2b5d6a91 | 6770 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6771 | register_prefix, i.op[op].regs->reg_name, |
6772 | i.suffix); | |
6773 | return 0; | |
6774 | } | |
29b0f896 AM |
6775 | } |
6776 | return 1; | |
6777 | } | |
252b5132 | 6778 | |
29b0f896 | 6779 | static int |
e3bb37b5 | 6780 | check_qword_reg (void) |
29b0f896 AM |
6781 | { |
6782 | int op; | |
252b5132 | 6783 | |
29b0f896 | 6784 | for (op = i.operands; --op >= 0; ) |
dc821c5f | 6785 | /* Skip non-register operands. */ |
bab6aec1 | 6786 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6787 | continue; |
29b0f896 AM |
6788 | /* Reject eight bit registers, except where the template requires |
6789 | them. (eg. movzb) */ | |
dc821c5f | 6790 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6791 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6792 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6793 | && (i.tm.operand_types[op].bitfield.word |
6794 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6795 | { |
a540244d L |
6796 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6797 | register_prefix, | |
29b0f896 AM |
6798 | i.op[op].regs->reg_name, |
6799 | i.tm.name, | |
6800 | i.suffix); | |
6801 | return 0; | |
6802 | } | |
e4630f71 | 6803 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
6804 | else if ((i.types[op].bitfield.word |
6805 | || i.types[op].bitfield.dword) | |
bab6aec1 | 6806 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6807 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6808 | && i.tm.operand_types[op].bitfield.qword) |
29b0f896 AM |
6809 | { |
6810 | /* Prohibit these changes in the 64bit mode, since the | |
6811 | lowering is more complicated. */ | |
34828aad | 6812 | if (intel_syntax |
ca61edf2 | 6813 | && i.tm.opcode_modifier.todword |
3528c362 | 6814 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 6815 | { |
ca61edf2 | 6816 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
6817 | i.suffix = LONG_MNEM_SUFFIX; |
6818 | } | |
6819 | else | |
6820 | { | |
2b5d6a91 | 6821 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6822 | register_prefix, i.op[op].regs->reg_name, |
6823 | i.suffix); | |
6824 | return 0; | |
6825 | } | |
252b5132 | 6826 | } |
29b0f896 AM |
6827 | return 1; |
6828 | } | |
252b5132 | 6829 | |
29b0f896 | 6830 | static int |
e3bb37b5 | 6831 | check_word_reg (void) |
29b0f896 AM |
6832 | { |
6833 | int op; | |
6834 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 6835 | /* Skip non-register operands. */ |
bab6aec1 | 6836 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6837 | continue; |
29b0f896 AM |
6838 | /* Reject eight bit registers, except where the template requires |
6839 | them. (eg. movzb) */ | |
dc821c5f | 6840 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6841 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6842 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6843 | && (i.tm.operand_types[op].bitfield.word |
6844 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6845 | { |
a540244d L |
6846 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6847 | register_prefix, | |
29b0f896 AM |
6848 | i.op[op].regs->reg_name, |
6849 | i.tm.name, | |
6850 | i.suffix); | |
6851 | return 0; | |
6852 | } | |
9706160a JB |
6853 | /* Error if the e or r prefix on a general reg is present. */ |
6854 | else if ((i.types[op].bitfield.dword | |
dc821c5f | 6855 | || i.types[op].bitfield.qword) |
bab6aec1 | 6856 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6857 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6858 | && i.tm.operand_types[op].bitfield.word) |
252b5132 | 6859 | { |
9706160a JB |
6860 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
6861 | register_prefix, i.op[op].regs->reg_name, | |
6862 | i.suffix); | |
6863 | return 0; | |
29b0f896 AM |
6864 | } |
6865 | return 1; | |
6866 | } | |
252b5132 | 6867 | |
29b0f896 | 6868 | static int |
40fb9820 | 6869 | update_imm (unsigned int j) |
29b0f896 | 6870 | { |
bc0844ae | 6871 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
6872 | if ((overlap.bitfield.imm8 |
6873 | || overlap.bitfield.imm8s | |
6874 | || overlap.bitfield.imm16 | |
6875 | || overlap.bitfield.imm32 | |
6876 | || overlap.bitfield.imm32s | |
6877 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
6878 | && !operand_type_equal (&overlap, &imm8) |
6879 | && !operand_type_equal (&overlap, &imm8s) | |
6880 | && !operand_type_equal (&overlap, &imm16) | |
6881 | && !operand_type_equal (&overlap, &imm32) | |
6882 | && !operand_type_equal (&overlap, &imm32s) | |
6883 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
6884 | { |
6885 | if (i.suffix) | |
6886 | { | |
40fb9820 L |
6887 | i386_operand_type temp; |
6888 | ||
0dfbf9d7 | 6889 | operand_type_set (&temp, 0); |
7ab9ffdd | 6890 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
6891 | { |
6892 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
6893 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
6894 | } | |
6895 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6896 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
6897 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6898 | { | |
6899 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
6900 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
6901 | } | |
6902 | else | |
6903 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
6904 | overlap = temp; | |
29b0f896 | 6905 | } |
0dfbf9d7 L |
6906 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
6907 | || operand_type_equal (&overlap, &imm16_32) | |
6908 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 6909 | { |
40fb9820 | 6910 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 6911 | overlap = imm16; |
40fb9820 | 6912 | else |
65da13b5 | 6913 | overlap = imm32s; |
29b0f896 | 6914 | } |
0dfbf9d7 L |
6915 | if (!operand_type_equal (&overlap, &imm8) |
6916 | && !operand_type_equal (&overlap, &imm8s) | |
6917 | && !operand_type_equal (&overlap, &imm16) | |
6918 | && !operand_type_equal (&overlap, &imm32) | |
6919 | && !operand_type_equal (&overlap, &imm32s) | |
6920 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 6921 | { |
4eed87de AM |
6922 | as_bad (_("no instruction mnemonic suffix given; " |
6923 | "can't determine immediate size")); | |
29b0f896 AM |
6924 | return 0; |
6925 | } | |
6926 | } | |
40fb9820 | 6927 | i.types[j] = overlap; |
29b0f896 | 6928 | |
40fb9820 L |
6929 | return 1; |
6930 | } | |
6931 | ||
6932 | static int | |
6933 | finalize_imm (void) | |
6934 | { | |
bc0844ae | 6935 | unsigned int j, n; |
29b0f896 | 6936 | |
bc0844ae L |
6937 | /* Update the first 2 immediate operands. */ |
6938 | n = i.operands > 2 ? 2 : i.operands; | |
6939 | if (n) | |
6940 | { | |
6941 | for (j = 0; j < n; j++) | |
6942 | if (update_imm (j) == 0) | |
6943 | return 0; | |
40fb9820 | 6944 | |
bc0844ae L |
6945 | /* The 3rd operand can't be immediate operand. */ |
6946 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
6947 | } | |
29b0f896 AM |
6948 | |
6949 | return 1; | |
6950 | } | |
6951 | ||
6952 | static int | |
e3bb37b5 | 6953 | process_operands (void) |
29b0f896 AM |
6954 | { |
6955 | /* Default segment register this instruction will use for memory | |
6956 | accesses. 0 means unknown. This is only for optimizing out | |
6957 | unnecessary segment overrides. */ | |
6958 | const seg_entry *default_seg = 0; | |
6959 | ||
2426c15f | 6960 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 6961 | { |
91d6fa6a NC |
6962 | unsigned int dupl = i.operands; |
6963 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
6964 | unsigned int j; |
6965 | ||
c0f3af97 | 6966 | /* The destination must be an xmm register. */ |
9c2799c2 | 6967 | gas_assert (i.reg_operands |
91d6fa6a | 6968 | && MAX_OPERANDS > dupl |
7ab9ffdd | 6969 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 6970 | |
75e5731b | 6971 | if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 6972 | && i.tm.operand_types[0].bitfield.xmmword) |
e2ec9d29 | 6973 | { |
8cd7925b | 6974 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
6975 | { |
6976 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
6977 | sources. */ | |
75e5731b | 6978 | i.tm.operand_types[0].bitfield.instance = InstanceNone; |
3528c362 | 6979 | i.tm.operand_types[0].bitfield.class = RegSIMD; |
c0f3af97 L |
6980 | goto duplicate; |
6981 | } | |
e2ec9d29 | 6982 | else |
c0f3af97 L |
6983 | { |
6984 | /* We remove the first xmm0 and keep the number of | |
6985 | operands unchanged, which in fact duplicates the | |
6986 | destination. */ | |
6987 | for (j = 1; j < i.operands; j++) | |
6988 | { | |
6989 | i.op[j - 1] = i.op[j]; | |
6990 | i.types[j - 1] = i.types[j]; | |
6991 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
8dc0818e | 6992 | i.flags[j - 1] = i.flags[j]; |
c0f3af97 L |
6993 | } |
6994 | } | |
6995 | } | |
6996 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 6997 | { |
91d6fa6a | 6998 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
6999 | && (i.tm.opcode_modifier.vexsources |
7000 | == VEX3SOURCES)); | |
c0f3af97 L |
7001 | |
7002 | /* Add the implicit xmm0 for instructions with VEX prefix | |
7003 | and 3 sources. */ | |
7004 | for (j = i.operands; j > 0; j--) | |
7005 | { | |
7006 | i.op[j] = i.op[j - 1]; | |
7007 | i.types[j] = i.types[j - 1]; | |
7008 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
8dc0818e | 7009 | i.flags[j] = i.flags[j - 1]; |
c0f3af97 L |
7010 | } |
7011 | i.op[0].regs | |
7012 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 7013 | i.types[0] = regxmm; |
c0f3af97 L |
7014 | i.tm.operand_types[0] = regxmm; |
7015 | ||
7016 | i.operands += 2; | |
7017 | i.reg_operands += 2; | |
7018 | i.tm.operands += 2; | |
7019 | ||
91d6fa6a | 7020 | dupl++; |
c0f3af97 | 7021 | dest++; |
91d6fa6a NC |
7022 | i.op[dupl] = i.op[dest]; |
7023 | i.types[dupl] = i.types[dest]; | |
7024 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7025 | i.flags[dupl] = i.flags[dest]; |
e2ec9d29 | 7026 | } |
c0f3af97 L |
7027 | else |
7028 | { | |
7029 | duplicate: | |
7030 | i.operands++; | |
7031 | i.reg_operands++; | |
7032 | i.tm.operands++; | |
7033 | ||
91d6fa6a NC |
7034 | i.op[dupl] = i.op[dest]; |
7035 | i.types[dupl] = i.types[dest]; | |
7036 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7037 | i.flags[dupl] = i.flags[dest]; |
c0f3af97 L |
7038 | } |
7039 | ||
7040 | if (i.tm.opcode_modifier.immext) | |
7041 | process_immext (); | |
7042 | } | |
75e5731b | 7043 | else if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7044 | && i.tm.operand_types[0].bitfield.xmmword) |
c0f3af97 L |
7045 | { |
7046 | unsigned int j; | |
7047 | ||
9fcfb3d7 L |
7048 | for (j = 1; j < i.operands; j++) |
7049 | { | |
7050 | i.op[j - 1] = i.op[j]; | |
7051 | i.types[j - 1] = i.types[j]; | |
7052 | ||
7053 | /* We need to adjust fields in i.tm since they are used by | |
7054 | build_modrm_byte. */ | |
7055 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
8dc0818e JB |
7056 | |
7057 | i.flags[j - 1] = i.flags[j]; | |
9fcfb3d7 L |
7058 | } |
7059 | ||
e2ec9d29 L |
7060 | i.operands--; |
7061 | i.reg_operands--; | |
e2ec9d29 L |
7062 | i.tm.operands--; |
7063 | } | |
920d2ddc IT |
7064 | else if (i.tm.opcode_modifier.implicitquadgroup) |
7065 | { | |
a477a8c4 JB |
7066 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
7067 | ||
920d2ddc | 7068 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
3528c362 | 7069 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
a477a8c4 JB |
7070 | regnum = register_number (i.op[1].regs); |
7071 | first_reg_in_group = regnum & ~3; | |
7072 | last_reg_in_group = first_reg_in_group + 3; | |
7073 | if (regnum != first_reg_in_group) | |
7074 | as_warn (_("source register `%s%s' implicitly denotes" | |
7075 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
7076 | register_prefix, i.op[1].regs->reg_name, | |
7077 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
7078 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
7079 | i.tm.name); | |
7080 | } | |
e2ec9d29 L |
7081 | else if (i.tm.opcode_modifier.regkludge) |
7082 | { | |
7083 | /* The imul $imm, %reg instruction is converted into | |
7084 | imul $imm, %reg, %reg, and the clr %reg instruction | |
7085 | is converted into xor %reg, %reg. */ | |
7086 | ||
7087 | unsigned int first_reg_op; | |
7088 | ||
7089 | if (operand_type_check (i.types[0], reg)) | |
7090 | first_reg_op = 0; | |
7091 | else | |
7092 | first_reg_op = 1; | |
7093 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 7094 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 7095 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
7096 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
7097 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
7098 | i.operands++; | |
7099 | i.reg_operands++; | |
29b0f896 AM |
7100 | } |
7101 | ||
85b80b0f | 7102 | if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
7103 | { |
7104 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
7105 | must be put into the modrm byte). Now, we make the modrm and |
7106 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
7107 | |
7108 | default_seg = build_modrm_byte (); | |
7109 | } | |
00cee14f | 7110 | else if (i.types[0].bitfield.class == SReg) |
85b80b0f JB |
7111 | { |
7112 | if (flag_code != CODE_64BIT | |
7113 | ? i.tm.base_opcode == POP_SEG_SHORT | |
7114 | && i.op[0].regs->reg_num == 1 | |
7115 | : (i.tm.base_opcode | 1) == POP_SEG386_SHORT | |
7116 | && i.op[0].regs->reg_num < 4) | |
7117 | { | |
7118 | as_bad (_("you can't `%s %s%s'"), | |
7119 | i.tm.name, register_prefix, i.op[0].regs->reg_name); | |
7120 | return 0; | |
7121 | } | |
7122 | if ( i.op[0].regs->reg_num > 3 && i.tm.opcode_length == 1 ) | |
7123 | { | |
7124 | i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT; | |
7125 | i.tm.opcode_length = 2; | |
7126 | } | |
7127 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
7128 | } | |
8a2ed489 | 7129 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
7130 | { |
7131 | default_seg = &ds; | |
7132 | } | |
40fb9820 | 7133 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
7134 | { |
7135 | /* For the string instructions that allow a segment override | |
7136 | on one of their operands, the default segment is ds. */ | |
7137 | default_seg = &ds; | |
7138 | } | |
50128d0c | 7139 | else if (i.short_form) |
85b80b0f JB |
7140 | { |
7141 | /* The register or float register operand is in operand | |
7142 | 0 or 1. */ | |
bab6aec1 | 7143 | unsigned int op = i.tm.operand_types[0].bitfield.class != Reg; |
85b80b0f JB |
7144 | |
7145 | /* Register goes in low 3 bits of opcode. */ | |
7146 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
7147 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7148 | i.rex |= REX_B; | |
7149 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) | |
7150 | { | |
7151 | /* Warn about some common errors, but press on regardless. | |
7152 | The first case can be generated by gcc (<= 2.8.1). */ | |
7153 | if (i.operands == 2) | |
7154 | { | |
7155 | /* Reversed arguments on faddp, fsubp, etc. */ | |
7156 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, | |
7157 | register_prefix, i.op[!intel_syntax].regs->reg_name, | |
7158 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
7159 | } | |
7160 | else | |
7161 | { | |
7162 | /* Extraneous `l' suffix on fp insn. */ | |
7163 | as_warn (_("translating to `%s %s%s'"), i.tm.name, | |
7164 | register_prefix, i.op[0].regs->reg_name); | |
7165 | } | |
7166 | } | |
7167 | } | |
29b0f896 | 7168 | |
75178d9d L |
7169 | if (i.tm.base_opcode == 0x8d /* lea */ |
7170 | && i.seg[0] | |
7171 | && !quiet_warnings) | |
30123838 | 7172 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
7173 | |
7174 | /* If a segment was explicitly specified, and the specified segment | |
7175 | is not the default, use an opcode prefix to select it. If we | |
7176 | never figured out what the default segment is, then default_seg | |
7177 | will be zero at this point, and the specified segment prefix will | |
7178 | always be used. */ | |
29b0f896 AM |
7179 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
7180 | { | |
7181 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
7182 | return 0; | |
7183 | } | |
7184 | return 1; | |
7185 | } | |
7186 | ||
7187 | static const seg_entry * | |
e3bb37b5 | 7188 | build_modrm_byte (void) |
29b0f896 AM |
7189 | { |
7190 | const seg_entry *default_seg = 0; | |
c0f3af97 | 7191 | unsigned int source, dest; |
8cd7925b | 7192 | int vex_3_sources; |
c0f3af97 | 7193 | |
8cd7925b | 7194 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
7195 | if (vex_3_sources) |
7196 | { | |
91d6fa6a | 7197 | unsigned int nds, reg_slot; |
4c2c6516 | 7198 | expressionS *exp; |
c0f3af97 | 7199 | |
6b8d3588 | 7200 | dest = i.operands - 1; |
c0f3af97 | 7201 | nds = dest - 1; |
922d8de8 | 7202 | |
a683cc34 | 7203 | /* There are 2 kinds of instructions: |
bed3d976 | 7204 | 1. 5 operands: 4 register operands or 3 register operands |
9d3bf266 | 7205 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
bed3d976 | 7206 | VexW0 or VexW1. The destination must be either XMM, YMM or |
43234a1e | 7207 | ZMM register. |
bed3d976 | 7208 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 7209 | plus 1 memory operand, with VexXDS. */ |
922d8de8 | 7210 | gas_assert ((i.reg_operands == 4 |
bed3d976 JB |
7211 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
7212 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
dcd7e323 | 7213 | && i.tm.opcode_modifier.vexw |
3528c362 | 7214 | && i.tm.operand_types[dest].bitfield.class == RegSIMD); |
a683cc34 | 7215 | |
48db9223 JB |
7216 | /* If VexW1 is set, the first non-immediate operand is the source and |
7217 | the second non-immediate one is encoded in the immediate operand. */ | |
7218 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
7219 | { | |
7220 | source = i.imm_operands; | |
7221 | reg_slot = i.imm_operands + 1; | |
7222 | } | |
7223 | else | |
7224 | { | |
7225 | source = i.imm_operands + 1; | |
7226 | reg_slot = i.imm_operands; | |
7227 | } | |
7228 | ||
a683cc34 | 7229 | if (i.imm_operands == 0) |
bed3d976 JB |
7230 | { |
7231 | /* When there is no immediate operand, generate an 8bit | |
7232 | immediate operand to encode the first operand. */ | |
7233 | exp = &im_expressions[i.imm_operands++]; | |
7234 | i.op[i.operands].imms = exp; | |
7235 | i.types[i.operands] = imm8; | |
7236 | i.operands++; | |
7237 | ||
3528c362 | 7238 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
bed3d976 JB |
7239 | exp->X_op = O_constant; |
7240 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
7241 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
7242 | } | |
922d8de8 | 7243 | else |
bed3d976 | 7244 | { |
9d3bf266 JB |
7245 | gas_assert (i.imm_operands == 1); |
7246 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); | |
7247 | gas_assert (!i.tm.opcode_modifier.immext); | |
a683cc34 | 7248 | |
9d3bf266 JB |
7249 | /* Turn on Imm8 again so that output_imm will generate it. */ |
7250 | i.types[0].bitfield.imm8 = 1; | |
bed3d976 | 7251 | |
3528c362 | 7252 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
9d3bf266 | 7253 | i.op[0].imms->X_add_number |
bed3d976 | 7254 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 7255 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 7256 | } |
a683cc34 | 7257 | |
3528c362 | 7258 | gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD); |
dae39acc | 7259 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
7260 | } |
7261 | else | |
7262 | source = dest = 0; | |
29b0f896 AM |
7263 | |
7264 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
7265 | implicit registers do not count. If there are 3 register |
7266 | operands, it must be a instruction with VexNDS. For a | |
7267 | instruction with VexNDD, the destination register is encoded | |
7268 | in VEX prefix. If there are 4 register operands, it must be | |
7269 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
7270 | if (i.mem_operands == 0 |
7271 | && ((i.reg_operands == 2 | |
2426c15f | 7272 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 7273 | || (i.reg_operands == 3 |
2426c15f | 7274 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 7275 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 7276 | { |
cab737b9 L |
7277 | switch (i.operands) |
7278 | { | |
7279 | case 2: | |
7280 | source = 0; | |
7281 | break; | |
7282 | case 3: | |
c81128dc L |
7283 | /* When there are 3 operands, one of them may be immediate, |
7284 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
7285 | the first operand must be shift count register (cl) or it |
7286 | is an instruction with VexNDS. */ | |
9c2799c2 | 7287 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 7288 | || (i.imm_operands == 0 |
2426c15f | 7289 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
75e5731b JB |
7290 | || (i.types[0].bitfield.instance == RegC |
7291 | && i.types[0].bitfield.byte)))); | |
40fb9820 | 7292 | if (operand_type_check (i.types[0], imm) |
75e5731b JB |
7293 | || (i.types[0].bitfield.instance == RegC |
7294 | && i.types[0].bitfield.byte)) | |
40fb9820 L |
7295 | source = 1; |
7296 | else | |
7297 | source = 0; | |
cab737b9 L |
7298 | break; |
7299 | case 4: | |
368d64cc L |
7300 | /* When there are 4 operands, the first two must be 8bit |
7301 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
7302 | one. |
7303 | ||
7304 | For instructions with VexNDS, if the first operand | |
7305 | an imm8, the source operand is the 2nd one. If the last | |
7306 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 7307 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
7308 | && i.types[0].bitfield.imm8 |
7309 | && i.types[1].bitfield.imm8) | |
2426c15f | 7310 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
7311 | && i.imm_operands == 1 |
7312 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
7313 | || i.types[i.operands - 1].bitfield.imm8 |
7314 | || i.rounding))); | |
9f2670f2 L |
7315 | if (i.imm_operands == 2) |
7316 | source = 2; | |
7317 | else | |
c0f3af97 L |
7318 | { |
7319 | if (i.types[0].bitfield.imm8) | |
7320 | source = 1; | |
7321 | else | |
7322 | source = 0; | |
7323 | } | |
c0f3af97 L |
7324 | break; |
7325 | case 5: | |
e771e7c9 | 7326 | if (is_evex_encoding (&i.tm)) |
43234a1e L |
7327 | { |
7328 | /* For EVEX instructions, when there are 5 operands, the | |
7329 | first one must be immediate operand. If the second one | |
7330 | is immediate operand, the source operand is the 3th | |
7331 | one. If the last one is immediate operand, the source | |
7332 | operand is the 2nd one. */ | |
7333 | gas_assert (i.imm_operands == 2 | |
7334 | && i.tm.opcode_modifier.sae | |
7335 | && operand_type_check (i.types[0], imm)); | |
7336 | if (operand_type_check (i.types[1], imm)) | |
7337 | source = 2; | |
7338 | else if (operand_type_check (i.types[4], imm)) | |
7339 | source = 1; | |
7340 | else | |
7341 | abort (); | |
7342 | } | |
cab737b9 L |
7343 | break; |
7344 | default: | |
7345 | abort (); | |
7346 | } | |
7347 | ||
c0f3af97 L |
7348 | if (!vex_3_sources) |
7349 | { | |
7350 | dest = source + 1; | |
7351 | ||
43234a1e L |
7352 | /* RC/SAE operand could be between DEST and SRC. That happens |
7353 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
7354 | register. */ | |
7355 | if (i.rounding && i.rounding->operand == (int) dest) | |
7356 | dest++; | |
7357 | ||
2426c15f | 7358 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 7359 | { |
43234a1e | 7360 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 7361 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
dfd69174 | 7362 | register. It is encoded in VEX prefix. */ |
f12dc422 L |
7363 | |
7364 | i386_operand_type op; | |
7365 | unsigned int vvvv; | |
7366 | ||
7367 | /* Check register-only source operand when two source | |
7368 | operands are swapped. */ | |
7369 | if (!i.tm.operand_types[source].bitfield.baseindex | |
7370 | && i.tm.operand_types[dest].bitfield.baseindex) | |
7371 | { | |
7372 | vvvv = source; | |
7373 | source = dest; | |
7374 | } | |
7375 | else | |
7376 | vvvv = dest; | |
7377 | ||
7378 | op = i.tm.operand_types[vvvv]; | |
c0f3af97 | 7379 | if ((dest + 1) >= i.operands |
bab6aec1 | 7380 | || ((op.bitfield.class != Reg |
dc821c5f | 7381 | || (!op.bitfield.dword && !op.bitfield.qword)) |
3528c362 | 7382 | && op.bitfield.class != RegSIMD |
43234a1e | 7383 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 7384 | abort (); |
f12dc422 | 7385 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
7386 | dest++; |
7387 | } | |
7388 | } | |
29b0f896 AM |
7389 | |
7390 | i.rm.mode = 3; | |
dfd69174 JB |
7391 | /* One of the register operands will be encoded in the i.rm.reg |
7392 | field, the other in the combined i.rm.mode and i.rm.regmem | |
29b0f896 AM |
7393 | fields. If no form of this instruction supports a memory |
7394 | destination operand, then we assume the source operand may | |
7395 | sometimes be a memory operand and so we need to store the | |
7396 | destination in the i.rm.reg field. */ | |
dfd69174 | 7397 | if (!i.tm.opcode_modifier.regmem |
40fb9820 | 7398 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) |
29b0f896 AM |
7399 | { |
7400 | i.rm.reg = i.op[dest].regs->reg_num; | |
7401 | i.rm.regmem = i.op[source].regs->reg_num; | |
3528c362 JB |
7402 | if (i.op[dest].regs->reg_type.bitfield.class == RegMMX |
7403 | || i.op[source].regs->reg_type.bitfield.class == RegMMX) | |
b4a3a7b4 | 7404 | i.has_regmmx = TRUE; |
3528c362 JB |
7405 | else if (i.op[dest].regs->reg_type.bitfield.class == RegSIMD |
7406 | || i.op[source].regs->reg_type.bitfield.class == RegSIMD) | |
b4a3a7b4 L |
7407 | { |
7408 | if (i.types[dest].bitfield.zmmword | |
7409 | || i.types[source].bitfield.zmmword) | |
7410 | i.has_regzmm = TRUE; | |
7411 | else if (i.types[dest].bitfield.ymmword | |
7412 | || i.types[source].bitfield.ymmword) | |
7413 | i.has_regymm = TRUE; | |
7414 | else | |
7415 | i.has_regxmm = TRUE; | |
7416 | } | |
29b0f896 | 7417 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7418 | i.rex |= REX_R; |
43234a1e L |
7419 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7420 | i.vrex |= REX_R; | |
29b0f896 | 7421 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7422 | i.rex |= REX_B; |
43234a1e L |
7423 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7424 | i.vrex |= REX_B; | |
29b0f896 AM |
7425 | } |
7426 | else | |
7427 | { | |
7428 | i.rm.reg = i.op[source].regs->reg_num; | |
7429 | i.rm.regmem = i.op[dest].regs->reg_num; | |
7430 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 7431 | i.rex |= REX_B; |
43234a1e L |
7432 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7433 | i.vrex |= REX_B; | |
29b0f896 | 7434 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7435 | i.rex |= REX_R; |
43234a1e L |
7436 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7437 | i.vrex |= REX_R; | |
29b0f896 | 7438 | } |
e0c7f900 | 7439 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 7440 | { |
4a5c67ed | 7441 | if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR) |
c4a530c5 | 7442 | abort (); |
e0c7f900 | 7443 | i.rex &= ~REX_R; |
c4a530c5 JB |
7444 | add_prefix (LOCK_PREFIX_OPCODE); |
7445 | } | |
29b0f896 AM |
7446 | } |
7447 | else | |
7448 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
7449 | unsigned int mem; |
7450 | ||
29b0f896 AM |
7451 | if (i.mem_operands) |
7452 | { | |
7453 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 7454 | unsigned int op; |
4eed87de | 7455 | |
7ab9ffdd | 7456 | for (op = 0; op < i.operands; op++) |
8dc0818e | 7457 | if (i.flags[op] & Operand_Mem) |
7ab9ffdd | 7458 | break; |
7ab9ffdd | 7459 | gas_assert (op < i.operands); |
29b0f896 | 7460 | |
6c30d220 L |
7461 | if (i.tm.opcode_modifier.vecsib) |
7462 | { | |
e968fc9b | 7463 | if (i.index_reg->reg_num == RegIZ) |
6c30d220 L |
7464 | abort (); |
7465 | ||
7466 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7467 | if (!i.base_reg) | |
7468 | { | |
7469 | i.sib.base = NO_BASE_REGISTER; | |
7470 | i.sib.scale = i.log2_scale_factor; | |
7471 | i.types[op].bitfield.disp8 = 0; | |
7472 | i.types[op].bitfield.disp16 = 0; | |
7473 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7474 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
7475 | { |
7476 | /* Must be 32 bit */ | |
7477 | i.types[op].bitfield.disp32 = 1; | |
7478 | i.types[op].bitfield.disp32s = 0; | |
7479 | } | |
7480 | else | |
7481 | { | |
7482 | i.types[op].bitfield.disp32 = 0; | |
7483 | i.types[op].bitfield.disp32s = 1; | |
7484 | } | |
7485 | } | |
7486 | i.sib.index = i.index_reg->reg_num; | |
7487 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
7488 | i.rex |= REX_X; | |
43234a1e L |
7489 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
7490 | i.vrex |= REX_X; | |
6c30d220 L |
7491 | } |
7492 | ||
29b0f896 AM |
7493 | default_seg = &ds; |
7494 | ||
7495 | if (i.base_reg == 0) | |
7496 | { | |
7497 | i.rm.mode = 0; | |
7498 | if (!i.disp_operands) | |
9bb129e8 | 7499 | fake_zero_displacement = 1; |
29b0f896 AM |
7500 | if (i.index_reg == 0) |
7501 | { | |
73053c1f JB |
7502 | i386_operand_type newdisp; |
7503 | ||
6c30d220 | 7504 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7505 | /* Operand is just <disp> */ |
20f0a1fc | 7506 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
7507 | { |
7508 | /* 64bit mode overwrites the 32bit absolute | |
7509 | addressing by RIP relative addressing and | |
7510 | absolute addressing is encoded by one of the | |
7511 | redundant SIB forms. */ | |
7512 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7513 | i.sib.base = NO_BASE_REGISTER; | |
7514 | i.sib.index = NO_INDEX_REGISTER; | |
73053c1f | 7515 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
20f0a1fc | 7516 | } |
fc225355 L |
7517 | else if ((flag_code == CODE_16BIT) |
7518 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
7519 | { |
7520 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 7521 | newdisp = disp16; |
20f0a1fc NC |
7522 | } |
7523 | else | |
7524 | { | |
7525 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 7526 | newdisp = disp32; |
29b0f896 | 7527 | } |
73053c1f JB |
7528 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
7529 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 7530 | } |
6c30d220 | 7531 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7532 | { |
6c30d220 | 7533 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 7534 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7535 | i.sib.index = NO_INDEX_REGISTER; |
7536 | else | |
7537 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7538 | i.sib.base = NO_BASE_REGISTER; |
7539 | i.sib.scale = i.log2_scale_factor; | |
7540 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
7541 | i.types[op].bitfield.disp8 = 0; |
7542 | i.types[op].bitfield.disp16 = 0; | |
7543 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7544 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
7545 | { |
7546 | /* Must be 32 bit */ | |
7547 | i.types[op].bitfield.disp32 = 1; | |
7548 | i.types[op].bitfield.disp32s = 0; | |
7549 | } | |
29b0f896 | 7550 | else |
40fb9820 L |
7551 | { |
7552 | i.types[op].bitfield.disp32 = 0; | |
7553 | i.types[op].bitfield.disp32s = 1; | |
7554 | } | |
29b0f896 | 7555 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7556 | i.rex |= REX_X; |
29b0f896 AM |
7557 | } |
7558 | } | |
7559 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 7560 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 7561 | { |
6c30d220 | 7562 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7563 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
7564 | i.types[op].bitfield.disp8 = 0; |
7565 | i.types[op].bitfield.disp16 = 0; | |
7566 | i.types[op].bitfield.disp32 = 0; | |
7567 | i.types[op].bitfield.disp32s = 1; | |
7568 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 7569 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
7570 | if (! i.disp_operands) |
7571 | fake_zero_displacement = 1; | |
29b0f896 | 7572 | } |
dc821c5f | 7573 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 7574 | { |
6c30d220 | 7575 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7576 | switch (i.base_reg->reg_num) |
7577 | { | |
7578 | case 3: /* (%bx) */ | |
7579 | if (i.index_reg == 0) | |
7580 | i.rm.regmem = 7; | |
7581 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
7582 | i.rm.regmem = i.index_reg->reg_num - 6; | |
7583 | break; | |
7584 | case 5: /* (%bp) */ | |
7585 | default_seg = &ss; | |
7586 | if (i.index_reg == 0) | |
7587 | { | |
7588 | i.rm.regmem = 6; | |
40fb9820 | 7589 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
7590 | { |
7591 | /* fake (%bp) into 0(%bp) */ | |
b5014f7a | 7592 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 7593 | fake_zero_displacement = 1; |
29b0f896 AM |
7594 | } |
7595 | } | |
7596 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
7597 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
7598 | break; | |
7599 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
7600 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
7601 | } | |
7602 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7603 | } | |
7604 | else /* i.base_reg and 32/64 bit mode */ | |
7605 | { | |
7606 | if (flag_code == CODE_64BIT | |
40fb9820 L |
7607 | && operand_type_check (i.types[op], disp)) |
7608 | { | |
73053c1f JB |
7609 | i.types[op].bitfield.disp16 = 0; |
7610 | i.types[op].bitfield.disp64 = 0; | |
40fb9820 | 7611 | if (i.prefix[ADDR_PREFIX] == 0) |
73053c1f JB |
7612 | { |
7613 | i.types[op].bitfield.disp32 = 0; | |
7614 | i.types[op].bitfield.disp32s = 1; | |
7615 | } | |
40fb9820 | 7616 | else |
73053c1f JB |
7617 | { |
7618 | i.types[op].bitfield.disp32 = 1; | |
7619 | i.types[op].bitfield.disp32s = 0; | |
7620 | } | |
40fb9820 | 7621 | } |
20f0a1fc | 7622 | |
6c30d220 L |
7623 | if (!i.tm.opcode_modifier.vecsib) |
7624 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 7625 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7626 | i.rex |= REX_B; |
29b0f896 AM |
7627 | i.sib.base = i.base_reg->reg_num; |
7628 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
7629 | complications. */ | |
848930b2 JB |
7630 | if (!(i.base_reg->reg_flags & RegRex) |
7631 | && (i.base_reg->reg_num == EBP_REG_NUM | |
7632 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 7633 | default_seg = &ss; |
848930b2 | 7634 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 7635 | { |
848930b2 | 7636 | fake_zero_displacement = 1; |
b5014f7a | 7637 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
7638 | } |
7639 | i.sib.scale = i.log2_scale_factor; | |
7640 | if (i.index_reg == 0) | |
7641 | { | |
6c30d220 | 7642 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7643 | /* <disp>(%esp) becomes two byte modrm with no index |
7644 | register. We've already stored the code for esp | |
7645 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
7646 | Any base register besides %esp will not use the | |
7647 | extra modrm byte. */ | |
7648 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 7649 | } |
6c30d220 | 7650 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7651 | { |
e968fc9b | 7652 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7653 | i.sib.index = NO_INDEX_REGISTER; |
7654 | else | |
7655 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7656 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
7657 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 7658 | i.rex |= REX_X; |
29b0f896 | 7659 | } |
67a4f2b7 AO |
7660 | |
7661 | if (i.disp_operands | |
7662 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
7663 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
7664 | i.rm.mode = 0; | |
7665 | else | |
a501d77e L |
7666 | { |
7667 | if (!fake_zero_displacement | |
7668 | && !i.disp_operands | |
7669 | && i.disp_encoding) | |
7670 | { | |
7671 | fake_zero_displacement = 1; | |
7672 | if (i.disp_encoding == disp_encoding_8bit) | |
7673 | i.types[op].bitfield.disp8 = 1; | |
7674 | else | |
7675 | i.types[op].bitfield.disp32 = 1; | |
7676 | } | |
7677 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7678 | } | |
29b0f896 | 7679 | } |
252b5132 | 7680 | |
29b0f896 AM |
7681 | if (fake_zero_displacement) |
7682 | { | |
7683 | /* Fakes a zero displacement assuming that i.types[op] | |
7684 | holds the correct displacement size. */ | |
7685 | expressionS *exp; | |
7686 | ||
9c2799c2 | 7687 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
7688 | exp = &disp_expressions[i.disp_operands++]; |
7689 | i.op[op].disps = exp; | |
7690 | exp->X_op = O_constant; | |
7691 | exp->X_add_number = 0; | |
7692 | exp->X_add_symbol = (symbolS *) 0; | |
7693 | exp->X_op_symbol = (symbolS *) 0; | |
7694 | } | |
c0f3af97 L |
7695 | |
7696 | mem = op; | |
29b0f896 | 7697 | } |
c0f3af97 L |
7698 | else |
7699 | mem = ~0; | |
252b5132 | 7700 | |
8c43a48b | 7701 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
7702 | { |
7703 | if (operand_type_check (i.types[0], imm)) | |
7704 | i.vex.register_specifier = NULL; | |
7705 | else | |
7706 | { | |
7707 | /* VEX.vvvv encodes one of the sources when the first | |
7708 | operand is not an immediate. */ | |
1ef99a7b | 7709 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7710 | i.vex.register_specifier = i.op[0].regs; |
7711 | else | |
7712 | i.vex.register_specifier = i.op[1].regs; | |
7713 | } | |
7714 | ||
7715 | /* Destination is a XMM register encoded in the ModRM.reg | |
7716 | and VEX.R bit. */ | |
7717 | i.rm.reg = i.op[2].regs->reg_num; | |
7718 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
7719 | i.rex |= REX_R; | |
7720 | ||
7721 | /* ModRM.rm and VEX.B encodes the other source. */ | |
7722 | if (!i.mem_operands) | |
7723 | { | |
7724 | i.rm.mode = 3; | |
7725 | ||
1ef99a7b | 7726 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7727 | i.rm.regmem = i.op[1].regs->reg_num; |
7728 | else | |
7729 | i.rm.regmem = i.op[0].regs->reg_num; | |
7730 | ||
7731 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7732 | i.rex |= REX_B; | |
7733 | } | |
7734 | } | |
2426c15f | 7735 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
7736 | { |
7737 | i.vex.register_specifier = i.op[2].regs; | |
7738 | if (!i.mem_operands) | |
7739 | { | |
7740 | i.rm.mode = 3; | |
7741 | i.rm.regmem = i.op[1].regs->reg_num; | |
7742 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7743 | i.rex |= REX_B; | |
7744 | } | |
7745 | } | |
29b0f896 AM |
7746 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
7747 | (if any) based on i.tm.extension_opcode. Again, we must be | |
7748 | careful to make sure that segment/control/debug/test/MMX | |
7749 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 7750 | else if (i.reg_operands) |
29b0f896 | 7751 | { |
99018f42 | 7752 | unsigned int op; |
7ab9ffdd L |
7753 | unsigned int vex_reg = ~0; |
7754 | ||
7755 | for (op = 0; op < i.operands; op++) | |
b4a3a7b4 | 7756 | { |
bab6aec1 | 7757 | if (i.types[op].bitfield.class == Reg |
f74a6307 JB |
7758 | || i.types[op].bitfield.class == RegBND |
7759 | || i.types[op].bitfield.class == RegMask | |
00cee14f | 7760 | || i.types[op].bitfield.class == SReg |
4a5c67ed JB |
7761 | || i.types[op].bitfield.class == RegCR |
7762 | || i.types[op].bitfield.class == RegDR | |
7763 | || i.types[op].bitfield.class == RegTR) | |
b4a3a7b4 | 7764 | break; |
3528c362 | 7765 | if (i.types[op].bitfield.class == RegSIMD) |
b4a3a7b4 L |
7766 | { |
7767 | if (i.types[op].bitfield.zmmword) | |
7768 | i.has_regzmm = TRUE; | |
7769 | else if (i.types[op].bitfield.ymmword) | |
7770 | i.has_regymm = TRUE; | |
7771 | else | |
7772 | i.has_regxmm = TRUE; | |
7773 | break; | |
7774 | } | |
3528c362 | 7775 | if (i.types[op].bitfield.class == RegMMX) |
b4a3a7b4 L |
7776 | { |
7777 | i.has_regmmx = TRUE; | |
7778 | break; | |
7779 | } | |
7780 | } | |
c0209578 | 7781 | |
7ab9ffdd L |
7782 | if (vex_3_sources) |
7783 | op = dest; | |
2426c15f | 7784 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
7785 | { |
7786 | /* For instructions with VexNDS, the register-only | |
7787 | source operand is encoded in VEX prefix. */ | |
7788 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 7789 | |
7ab9ffdd | 7790 | if (op > mem) |
c0f3af97 | 7791 | { |
7ab9ffdd L |
7792 | vex_reg = op++; |
7793 | gas_assert (op < i.operands); | |
c0f3af97 L |
7794 | } |
7795 | else | |
c0f3af97 | 7796 | { |
f12dc422 L |
7797 | /* Check register-only source operand when two source |
7798 | operands are swapped. */ | |
7799 | if (!i.tm.operand_types[op].bitfield.baseindex | |
7800 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
7801 | { | |
7802 | vex_reg = op; | |
7803 | op += 2; | |
7804 | gas_assert (mem == (vex_reg + 1) | |
7805 | && op < i.operands); | |
7806 | } | |
7807 | else | |
7808 | { | |
7809 | vex_reg = op + 1; | |
7810 | gas_assert (vex_reg < i.operands); | |
7811 | } | |
c0f3af97 | 7812 | } |
7ab9ffdd | 7813 | } |
2426c15f | 7814 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 7815 | { |
f12dc422 | 7816 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 7817 | is encoded in VEX prefix. */ |
f12dc422 L |
7818 | if (i.mem_operands == 0) |
7819 | { | |
7820 | /* There is no memory operand. */ | |
7821 | gas_assert ((op + 2) == i.operands); | |
7822 | vex_reg = op + 1; | |
7823 | } | |
7824 | else | |
8d63c93e | 7825 | { |
ed438a93 JB |
7826 | /* There are only 2 non-immediate operands. */ |
7827 | gas_assert (op < i.imm_operands + 2 | |
7828 | && i.operands == i.imm_operands + 2); | |
7829 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 7830 | } |
7ab9ffdd L |
7831 | } |
7832 | else | |
7833 | gas_assert (op < i.operands); | |
99018f42 | 7834 | |
7ab9ffdd L |
7835 | if (vex_reg != (unsigned int) ~0) |
7836 | { | |
f12dc422 | 7837 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 7838 | |
bab6aec1 | 7839 | if ((type->bitfield.class != Reg |
dc821c5f | 7840 | || (!type->bitfield.dword && !type->bitfield.qword)) |
3528c362 | 7841 | && type->bitfield.class != RegSIMD |
43234a1e | 7842 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 7843 | abort (); |
f88c9eb0 | 7844 | |
7ab9ffdd L |
7845 | i.vex.register_specifier = i.op[vex_reg].regs; |
7846 | } | |
7847 | ||
1b9f0c97 L |
7848 | /* Don't set OP operand twice. */ |
7849 | if (vex_reg != op) | |
7ab9ffdd | 7850 | { |
1b9f0c97 L |
7851 | /* If there is an extension opcode to put here, the |
7852 | register number must be put into the regmem field. */ | |
7853 | if (i.tm.extension_opcode != None) | |
7854 | { | |
7855 | i.rm.regmem = i.op[op].regs->reg_num; | |
7856 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7857 | i.rex |= REX_B; | |
43234a1e L |
7858 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7859 | i.vrex |= REX_B; | |
1b9f0c97 L |
7860 | } |
7861 | else | |
7862 | { | |
7863 | i.rm.reg = i.op[op].regs->reg_num; | |
7864 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7865 | i.rex |= REX_R; | |
43234a1e L |
7866 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7867 | i.vrex |= REX_R; | |
1b9f0c97 | 7868 | } |
7ab9ffdd | 7869 | } |
252b5132 | 7870 | |
29b0f896 AM |
7871 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
7872 | must set it to 3 to indicate this is a register operand | |
7873 | in the regmem field. */ | |
7874 | if (!i.mem_operands) | |
7875 | i.rm.mode = 3; | |
7876 | } | |
252b5132 | 7877 | |
29b0f896 | 7878 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 7879 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
7880 | i.rm.reg = i.tm.extension_opcode; |
7881 | } | |
7882 | return default_seg; | |
7883 | } | |
252b5132 | 7884 | |
376cd056 JB |
7885 | static unsigned int |
7886 | flip_code16 (unsigned int code16) | |
7887 | { | |
7888 | gas_assert (i.tm.operands == 1); | |
7889 | ||
7890 | return !(i.prefix[REX_PREFIX] & REX_W) | |
7891 | && (code16 ? i.tm.operand_types[0].bitfield.disp32 | |
7892 | || i.tm.operand_types[0].bitfield.disp32s | |
7893 | : i.tm.operand_types[0].bitfield.disp16) | |
7894 | ? CODE16 : 0; | |
7895 | } | |
7896 | ||
29b0f896 | 7897 | static void |
e3bb37b5 | 7898 | output_branch (void) |
29b0f896 AM |
7899 | { |
7900 | char *p; | |
f8a5c266 | 7901 | int size; |
29b0f896 AM |
7902 | int code16; |
7903 | int prefix; | |
7904 | relax_substateT subtype; | |
7905 | symbolS *sym; | |
7906 | offsetT off; | |
7907 | ||
f8a5c266 | 7908 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 7909 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
7910 | |
7911 | prefix = 0; | |
7912 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 7913 | { |
29b0f896 AM |
7914 | prefix = 1; |
7915 | i.prefixes -= 1; | |
376cd056 | 7916 | code16 ^= flip_code16(code16); |
252b5132 | 7917 | } |
29b0f896 AM |
7918 | /* Pentium4 branch hints. */ |
7919 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7920 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 7921 | { |
29b0f896 AM |
7922 | prefix++; |
7923 | i.prefixes--; | |
7924 | } | |
7925 | if (i.prefix[REX_PREFIX] != 0) | |
7926 | { | |
7927 | prefix++; | |
7928 | i.prefixes--; | |
2f66722d AM |
7929 | } |
7930 | ||
7e8b059b L |
7931 | /* BND prefixed jump. */ |
7932 | if (i.prefix[BND_PREFIX] != 0) | |
7933 | { | |
6cb0a70e JB |
7934 | prefix++; |
7935 | i.prefixes--; | |
7e8b059b L |
7936 | } |
7937 | ||
f2810fe0 JB |
7938 | if (i.prefixes != 0) |
7939 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
29b0f896 AM |
7940 | |
7941 | /* It's always a symbol; End frag & setup for relax. | |
7942 | Make sure there is enough room in this frag for the largest | |
7943 | instruction we may generate in md_convert_frag. This is 2 | |
7944 | bytes for the opcode and room for the prefix and largest | |
7945 | displacement. */ | |
7946 | frag_grow (prefix + 2 + 4); | |
7947 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
7948 | p = frag_more (prefix + 1); | |
7949 | if (i.prefix[DATA_PREFIX] != 0) | |
7950 | *p++ = DATA_PREFIX_OPCODE; | |
7951 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
7952 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
7953 | *p++ = i.prefix[SEG_PREFIX]; | |
6cb0a70e JB |
7954 | if (i.prefix[BND_PREFIX] != 0) |
7955 | *p++ = BND_PREFIX_OPCODE; | |
29b0f896 AM |
7956 | if (i.prefix[REX_PREFIX] != 0) |
7957 | *p++ = i.prefix[REX_PREFIX]; | |
7958 | *p = i.tm.base_opcode; | |
7959 | ||
7960 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 7961 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 7962 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 7963 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 7964 | else |
f8a5c266 | 7965 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 7966 | subtype |= code16; |
3e73aa7c | 7967 | |
29b0f896 AM |
7968 | sym = i.op[0].disps->X_add_symbol; |
7969 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 7970 | |
29b0f896 AM |
7971 | if (i.op[0].disps->X_op != O_constant |
7972 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 7973 | { |
29b0f896 AM |
7974 | /* Handle complex expressions. */ |
7975 | sym = make_expr_symbol (i.op[0].disps); | |
7976 | off = 0; | |
7977 | } | |
3e73aa7c | 7978 | |
29b0f896 AM |
7979 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
7980 | Pass reloc in fr_var. */ | |
d258b828 | 7981 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 7982 | } |
3e73aa7c | 7983 | |
bd7ab16b L |
7984 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7985 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
7986 | symbol S. */ | |
7987 | ||
7988 | static bfd_boolean | |
7989 | need_plt32_p (symbolS *s) | |
7990 | { | |
7991 | /* PLT32 relocation is ELF only. */ | |
7992 | if (!IS_ELF) | |
7993 | return FALSE; | |
7994 | ||
a5def729 RO |
7995 | #ifdef TE_SOLARIS |
7996 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
7997 | krtld support it. */ | |
7998 | return FALSE; | |
7999 | #endif | |
8000 | ||
bd7ab16b L |
8001 | /* Since there is no need to prepare for PLT branch on x86-64, we |
8002 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
8003 | be used as a marker for 32-bit PC-relative branches. */ | |
8004 | if (!object_64bit) | |
8005 | return FALSE; | |
8006 | ||
8007 | /* Weak or undefined symbol need PLT32 relocation. */ | |
8008 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
8009 | return TRUE; | |
8010 | ||
8011 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
8012 | if (! S_IS_EXTERNAL (s)) | |
8013 | return FALSE; | |
8014 | ||
8015 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
8016 | non-default visibilities are treated as normal global symbol | |
8017 | so that PLT32 relocation can be used as a marker for 32-bit | |
8018 | PC-relative branches. It is useful for linker relaxation. */ | |
8019 | return TRUE; | |
8020 | } | |
8021 | #endif | |
8022 | ||
29b0f896 | 8023 | static void |
e3bb37b5 | 8024 | output_jump (void) |
29b0f896 AM |
8025 | { |
8026 | char *p; | |
8027 | int size; | |
3e02c1cc | 8028 | fixS *fixP; |
bd7ab16b | 8029 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 8030 | |
0cfa3eb3 | 8031 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) |
29b0f896 AM |
8032 | { |
8033 | /* This is a loop or jecxz type instruction. */ | |
8034 | size = 1; | |
8035 | if (i.prefix[ADDR_PREFIX] != 0) | |
8036 | { | |
8037 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
8038 | i.prefixes -= 1; | |
8039 | } | |
8040 | /* Pentium4 branch hints. */ | |
8041 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8042 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
8043 | { | |
8044 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
8045 | i.prefixes--; | |
3e73aa7c JH |
8046 | } |
8047 | } | |
29b0f896 AM |
8048 | else |
8049 | { | |
8050 | int code16; | |
3e73aa7c | 8051 | |
29b0f896 AM |
8052 | code16 = 0; |
8053 | if (flag_code == CODE_16BIT) | |
8054 | code16 = CODE16; | |
3e73aa7c | 8055 | |
29b0f896 AM |
8056 | if (i.prefix[DATA_PREFIX] != 0) |
8057 | { | |
8058 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
8059 | i.prefixes -= 1; | |
376cd056 | 8060 | code16 ^= flip_code16(code16); |
29b0f896 | 8061 | } |
252b5132 | 8062 | |
29b0f896 AM |
8063 | size = 4; |
8064 | if (code16) | |
8065 | size = 2; | |
8066 | } | |
9fcc94b6 | 8067 | |
6cb0a70e JB |
8068 | /* BND prefixed jump. */ |
8069 | if (i.prefix[BND_PREFIX] != 0) | |
29b0f896 | 8070 | { |
6cb0a70e | 8071 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); |
29b0f896 AM |
8072 | i.prefixes -= 1; |
8073 | } | |
252b5132 | 8074 | |
6cb0a70e | 8075 | if (i.prefix[REX_PREFIX] != 0) |
7e8b059b | 8076 | { |
6cb0a70e | 8077 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); |
7e8b059b L |
8078 | i.prefixes -= 1; |
8079 | } | |
8080 | ||
f2810fe0 JB |
8081 | if (i.prefixes != 0) |
8082 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
e0890092 | 8083 | |
42164a71 L |
8084 | p = frag_more (i.tm.opcode_length + size); |
8085 | switch (i.tm.opcode_length) | |
8086 | { | |
8087 | case 2: | |
8088 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 8089 | /* Fall through. */ |
42164a71 L |
8090 | case 1: |
8091 | *p++ = i.tm.base_opcode; | |
8092 | break; | |
8093 | default: | |
8094 | abort (); | |
8095 | } | |
e0890092 | 8096 | |
bd7ab16b L |
8097 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8098 | if (size == 4 | |
8099 | && jump_reloc == NO_RELOC | |
8100 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
8101 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
8102 | #endif | |
8103 | ||
8104 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
8105 | ||
3e02c1cc | 8106 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 8107 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc AM |
8108 | |
8109 | /* All jumps handled here are signed, but don't use a signed limit | |
8110 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
8111 | 4G and 64k respectively. */ | |
8112 | if (size == 1) | |
8113 | fixP->fx_signed = 1; | |
29b0f896 | 8114 | } |
e0890092 | 8115 | |
29b0f896 | 8116 | static void |
e3bb37b5 | 8117 | output_interseg_jump (void) |
29b0f896 AM |
8118 | { |
8119 | char *p; | |
8120 | int size; | |
8121 | int prefix; | |
8122 | int code16; | |
252b5132 | 8123 | |
29b0f896 AM |
8124 | code16 = 0; |
8125 | if (flag_code == CODE_16BIT) | |
8126 | code16 = CODE16; | |
a217f122 | 8127 | |
29b0f896 AM |
8128 | prefix = 0; |
8129 | if (i.prefix[DATA_PREFIX] != 0) | |
8130 | { | |
8131 | prefix = 1; | |
8132 | i.prefixes -= 1; | |
8133 | code16 ^= CODE16; | |
8134 | } | |
6cb0a70e JB |
8135 | |
8136 | gas_assert (!i.prefix[REX_PREFIX]); | |
252b5132 | 8137 | |
29b0f896 AM |
8138 | size = 4; |
8139 | if (code16) | |
8140 | size = 2; | |
252b5132 | 8141 | |
f2810fe0 JB |
8142 | if (i.prefixes != 0) |
8143 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
252b5132 | 8144 | |
29b0f896 AM |
8145 | /* 1 opcode; 2 segment; offset */ |
8146 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 8147 | |
29b0f896 AM |
8148 | if (i.prefix[DATA_PREFIX] != 0) |
8149 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 8150 | |
29b0f896 AM |
8151 | if (i.prefix[REX_PREFIX] != 0) |
8152 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 8153 | |
29b0f896 AM |
8154 | *p++ = i.tm.base_opcode; |
8155 | if (i.op[1].imms->X_op == O_constant) | |
8156 | { | |
8157 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 8158 | |
29b0f896 AM |
8159 | if (size == 2 |
8160 | && !fits_in_unsigned_word (n) | |
8161 | && !fits_in_signed_word (n)) | |
8162 | { | |
8163 | as_bad (_("16-bit jump out of range")); | |
8164 | return; | |
8165 | } | |
8166 | md_number_to_chars (p, n, size); | |
8167 | } | |
8168 | else | |
8169 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 8170 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
8171 | if (i.op[0].imms->X_op != O_constant) |
8172 | as_bad (_("can't handle non absolute segment in `%s'"), | |
8173 | i.tm.name); | |
8174 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
8175 | } | |
a217f122 | 8176 | |
b4a3a7b4 L |
8177 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8178 | void | |
8179 | x86_cleanup (void) | |
8180 | { | |
8181 | char *p; | |
8182 | asection *seg = now_seg; | |
8183 | subsegT subseg = now_subseg; | |
8184 | asection *sec; | |
8185 | unsigned int alignment, align_size_1; | |
8186 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
8187 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
8188 | unsigned int padding; | |
8189 | ||
8190 | if (!IS_ELF || !x86_used_note) | |
8191 | return; | |
8192 | ||
b4a3a7b4 L |
8193 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
8194 | ||
8195 | /* The .note.gnu.property section layout: | |
8196 | ||
8197 | Field Length Contents | |
8198 | ---- ---- ---- | |
8199 | n_namsz 4 4 | |
8200 | n_descsz 4 The note descriptor size | |
8201 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
8202 | n_name 4 "GNU" | |
8203 | n_desc n_descsz The program property array | |
8204 | .... .... .... | |
8205 | */ | |
8206 | ||
8207 | /* Create the .note.gnu.property section. */ | |
8208 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
fd361982 | 8209 | bfd_set_section_flags (sec, |
b4a3a7b4 L |
8210 | (SEC_ALLOC |
8211 | | SEC_LOAD | |
8212 | | SEC_DATA | |
8213 | | SEC_HAS_CONTENTS | |
8214 | | SEC_READONLY)); | |
8215 | ||
8216 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
8217 | { | |
8218 | align_size_1 = 7; | |
8219 | alignment = 3; | |
8220 | } | |
8221 | else | |
8222 | { | |
8223 | align_size_1 = 3; | |
8224 | alignment = 2; | |
8225 | } | |
8226 | ||
fd361982 | 8227 | bfd_set_section_alignment (sec, alignment); |
b4a3a7b4 L |
8228 | elf_section_type (sec) = SHT_NOTE; |
8229 | ||
8230 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size | |
8231 | + 4-byte data */ | |
8232 | isa_1_descsz_raw = 4 + 4 + 4; | |
8233 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
8234 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
8235 | ||
8236 | feature_2_descsz_raw = isa_1_descsz; | |
8237 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
8238 | + 4-byte data */ | |
8239 | feature_2_descsz_raw += 4 + 4 + 4; | |
8240 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
8241 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
8242 | & ~align_size_1); | |
8243 | ||
8244 | descsz = feature_2_descsz; | |
8245 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
8246 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
8247 | ||
8248 | /* Write n_namsz. */ | |
8249 | md_number_to_chars (p, (valueT) 4, 4); | |
8250 | ||
8251 | /* Write n_descsz. */ | |
8252 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
8253 | ||
8254 | /* Write n_type. */ | |
8255 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
8256 | ||
8257 | /* Write n_name. */ | |
8258 | memcpy (p + 4 * 3, "GNU", 4); | |
8259 | ||
8260 | /* Write 4-byte type. */ | |
8261 | md_number_to_chars (p + 4 * 4, | |
8262 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
8263 | ||
8264 | /* Write 4-byte data size. */ | |
8265 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
8266 | ||
8267 | /* Write 4-byte data. */ | |
8268 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
8269 | ||
8270 | /* Zero out paddings. */ | |
8271 | padding = isa_1_descsz - isa_1_descsz_raw; | |
8272 | if (padding) | |
8273 | memset (p + 4 * 7, 0, padding); | |
8274 | ||
8275 | /* Write 4-byte type. */ | |
8276 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
8277 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
8278 | ||
8279 | /* Write 4-byte data size. */ | |
8280 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
8281 | ||
8282 | /* Write 4-byte data. */ | |
8283 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
8284 | (valueT) x86_feature_2_used, 4); | |
8285 | ||
8286 | /* Zero out paddings. */ | |
8287 | padding = feature_2_descsz - feature_2_descsz_raw; | |
8288 | if (padding) | |
8289 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
8290 | ||
8291 | /* We probably can't restore the current segment, for there likely | |
8292 | isn't one yet... */ | |
8293 | if (seg && subseg) | |
8294 | subseg_set (seg, subseg); | |
8295 | } | |
8296 | #endif | |
8297 | ||
9c33702b JB |
8298 | static unsigned int |
8299 | encoding_length (const fragS *start_frag, offsetT start_off, | |
8300 | const char *frag_now_ptr) | |
8301 | { | |
8302 | unsigned int len = 0; | |
8303 | ||
8304 | if (start_frag != frag_now) | |
8305 | { | |
8306 | const fragS *fr = start_frag; | |
8307 | ||
8308 | do { | |
8309 | len += fr->fr_fix; | |
8310 | fr = fr->fr_next; | |
8311 | } while (fr && fr != frag_now); | |
8312 | } | |
8313 | ||
8314 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); | |
8315 | } | |
8316 | ||
e379e5f3 L |
8317 | /* Return 1 for test, and, cmp, add, sub, inc and dec which may |
8318 | be macro-fused with conditional jumps. */ | |
8319 | ||
8320 | static int | |
8321 | maybe_fused_with_jcc_p (void) | |
8322 | { | |
8323 | /* No RIP address. */ | |
8324 | if (i.base_reg && i.base_reg->reg_num == RegIP) | |
8325 | return 0; | |
8326 | ||
8327 | /* No VEX/EVEX encoding. */ | |
8328 | if (is_any_vex_encoding (&i.tm)) | |
8329 | return 0; | |
8330 | ||
8331 | /* and, add, sub with destination register. */ | |
8332 | if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25) | |
8333 | || i.tm.base_opcode <= 5 | |
8334 | || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d) | |
8335 | || ((i.tm.base_opcode | 3) == 0x83 | |
8336 | && ((i.tm.extension_opcode | 1) == 0x5 | |
8337 | || i.tm.extension_opcode == 0x0))) | |
8338 | return (i.types[1].bitfield.class == Reg | |
8339 | || i.types[1].bitfield.instance == Accum); | |
8340 | ||
8341 | /* test, cmp with any register. */ | |
8342 | if ((i.tm.base_opcode | 1) == 0x85 | |
8343 | || (i.tm.base_opcode | 1) == 0xa9 | |
8344 | || ((i.tm.base_opcode | 1) == 0xf7 | |
8345 | && i.tm.extension_opcode == 0) | |
8346 | || (i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d) | |
8347 | || ((i.tm.base_opcode | 3) == 0x83 | |
8348 | && (i.tm.extension_opcode == 0x7))) | |
8349 | return (i.types[0].bitfield.class == Reg | |
8350 | || i.types[0].bitfield.instance == Accum | |
8351 | || i.types[1].bitfield.class == Reg | |
8352 | || i.types[1].bitfield.instance == Accum); | |
8353 | ||
8354 | /* inc, dec with any register. */ | |
8355 | if ((i.tm.cpu_flags.bitfield.cpuno64 | |
8356 | && (i.tm.base_opcode | 0xf) == 0x4f) | |
8357 | || ((i.tm.base_opcode | 1) == 0xff | |
8358 | && i.tm.extension_opcode <= 0x1)) | |
8359 | return (i.types[0].bitfield.class == Reg | |
8360 | || i.types[0].bitfield.instance == Accum); | |
8361 | ||
8362 | return 0; | |
8363 | } | |
8364 | ||
8365 | /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */ | |
8366 | ||
8367 | static int | |
8368 | add_fused_jcc_padding_frag_p (void) | |
8369 | { | |
8370 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
8371 | if (!align_branch_power | |
8372 | || now_seg == absolute_section | |
8373 | || !cpu_arch_flags.bitfield.cpui386 | |
8374 | || !(align_branch & align_branch_fused_bit)) | |
8375 | return 0; | |
8376 | ||
8377 | if (maybe_fused_with_jcc_p ()) | |
8378 | { | |
8379 | if (last_insn.kind == last_insn_other | |
8380 | || last_insn.seg != now_seg) | |
8381 | return 1; | |
8382 | if (flag_debug) | |
8383 | as_warn_where (last_insn.file, last_insn.line, | |
8384 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8385 | last_insn.name, i.tm.name); | |
8386 | } | |
8387 | ||
8388 | return 0; | |
8389 | } | |
8390 | ||
8391 | /* Return 1 if a BRANCH_PREFIX frag should be generated. */ | |
8392 | ||
8393 | static int | |
8394 | add_branch_prefix_frag_p (void) | |
8395 | { | |
8396 | /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix | |
8397 | to PadLock instructions since they include prefixes in opcode. */ | |
8398 | if (!align_branch_power | |
8399 | || !align_branch_prefix_size | |
8400 | || now_seg == absolute_section | |
8401 | || i.tm.cpu_flags.bitfield.cpupadlock | |
8402 | || !cpu_arch_flags.bitfield.cpui386) | |
8403 | return 0; | |
8404 | ||
8405 | /* Don't add prefix if it is a prefix or there is no operand in case | |
8406 | that segment prefix is special. */ | |
8407 | if (!i.operands || i.tm.opcode_modifier.isprefix) | |
8408 | return 0; | |
8409 | ||
8410 | if (last_insn.kind == last_insn_other | |
8411 | || last_insn.seg != now_seg) | |
8412 | return 1; | |
8413 | ||
8414 | if (flag_debug) | |
8415 | as_warn_where (last_insn.file, last_insn.line, | |
8416 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8417 | last_insn.name, i.tm.name); | |
8418 | ||
8419 | return 0; | |
8420 | } | |
8421 | ||
8422 | /* Return 1 if a BRANCH_PADDING frag should be generated. */ | |
8423 | ||
8424 | static int | |
8425 | add_branch_padding_frag_p (enum align_branch_kind *branch_p) | |
8426 | { | |
8427 | int add_padding; | |
8428 | ||
8429 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
8430 | if (!align_branch_power | |
8431 | || now_seg == absolute_section | |
8432 | || !cpu_arch_flags.bitfield.cpui386) | |
8433 | return 0; | |
8434 | ||
8435 | add_padding = 0; | |
8436 | ||
8437 | /* Check for jcc and direct jmp. */ | |
8438 | if (i.tm.opcode_modifier.jump == JUMP) | |
8439 | { | |
8440 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) | |
8441 | { | |
8442 | *branch_p = align_branch_jmp; | |
8443 | add_padding = align_branch & align_branch_jmp_bit; | |
8444 | } | |
8445 | else | |
8446 | { | |
8447 | *branch_p = align_branch_jcc; | |
8448 | if ((align_branch & align_branch_jcc_bit)) | |
8449 | add_padding = 1; | |
8450 | } | |
8451 | } | |
8452 | else if (is_any_vex_encoding (&i.tm)) | |
8453 | return 0; | |
8454 | else if ((i.tm.base_opcode | 1) == 0xc3) | |
8455 | { | |
8456 | /* Near ret. */ | |
8457 | *branch_p = align_branch_ret; | |
8458 | if ((align_branch & align_branch_ret_bit)) | |
8459 | add_padding = 1; | |
8460 | } | |
8461 | else | |
8462 | { | |
8463 | /* Check for indirect jmp, direct and indirect calls. */ | |
8464 | if (i.tm.base_opcode == 0xe8) | |
8465 | { | |
8466 | /* Direct call. */ | |
8467 | *branch_p = align_branch_call; | |
8468 | if ((align_branch & align_branch_call_bit)) | |
8469 | add_padding = 1; | |
8470 | } | |
8471 | else if (i.tm.base_opcode == 0xff | |
8472 | && (i.tm.extension_opcode == 2 | |
8473 | || i.tm.extension_opcode == 4)) | |
8474 | { | |
8475 | /* Indirect call and jmp. */ | |
8476 | *branch_p = align_branch_indirect; | |
8477 | if ((align_branch & align_branch_indirect_bit)) | |
8478 | add_padding = 1; | |
8479 | } | |
8480 | ||
8481 | if (add_padding | |
8482 | && i.disp_operands | |
8483 | && tls_get_addr | |
8484 | && (i.op[0].disps->X_op == O_symbol | |
8485 | || (i.op[0].disps->X_op == O_subtract | |
8486 | && i.op[0].disps->X_op_symbol == GOT_symbol))) | |
8487 | { | |
8488 | symbolS *s = i.op[0].disps->X_add_symbol; | |
8489 | /* No padding to call to global or undefined tls_get_addr. */ | |
8490 | if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s)) | |
8491 | && strcmp (S_GET_NAME (s), tls_get_addr) == 0) | |
8492 | return 0; | |
8493 | } | |
8494 | } | |
8495 | ||
8496 | if (add_padding | |
8497 | && last_insn.kind != last_insn_other | |
8498 | && last_insn.seg == now_seg) | |
8499 | { | |
8500 | if (flag_debug) | |
8501 | as_warn_where (last_insn.file, last_insn.line, | |
8502 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8503 | last_insn.name, i.tm.name); | |
8504 | return 0; | |
8505 | } | |
8506 | ||
8507 | return add_padding; | |
8508 | } | |
8509 | ||
29b0f896 | 8510 | static void |
e3bb37b5 | 8511 | output_insn (void) |
29b0f896 | 8512 | { |
2bbd9c25 JJ |
8513 | fragS *insn_start_frag; |
8514 | offsetT insn_start_off; | |
e379e5f3 L |
8515 | fragS *fragP = NULL; |
8516 | enum align_branch_kind branch = align_branch_none; | |
2bbd9c25 | 8517 | |
b4a3a7b4 L |
8518 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8519 | if (IS_ELF && x86_used_note) | |
8520 | { | |
8521 | if (i.tm.cpu_flags.bitfield.cpucmov) | |
8522 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV; | |
8523 | if (i.tm.cpu_flags.bitfield.cpusse) | |
8524 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE; | |
8525 | if (i.tm.cpu_flags.bitfield.cpusse2) | |
8526 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2; | |
8527 | if (i.tm.cpu_flags.bitfield.cpusse3) | |
8528 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3; | |
8529 | if (i.tm.cpu_flags.bitfield.cpussse3) | |
8530 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3; | |
8531 | if (i.tm.cpu_flags.bitfield.cpusse4_1) | |
8532 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1; | |
8533 | if (i.tm.cpu_flags.bitfield.cpusse4_2) | |
8534 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2; | |
8535 | if (i.tm.cpu_flags.bitfield.cpuavx) | |
8536 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX; | |
8537 | if (i.tm.cpu_flags.bitfield.cpuavx2) | |
8538 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2; | |
8539 | if (i.tm.cpu_flags.bitfield.cpufma) | |
8540 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA; | |
8541 | if (i.tm.cpu_flags.bitfield.cpuavx512f) | |
8542 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F; | |
8543 | if (i.tm.cpu_flags.bitfield.cpuavx512cd) | |
8544 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD; | |
8545 | if (i.tm.cpu_flags.bitfield.cpuavx512er) | |
8546 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER; | |
8547 | if (i.tm.cpu_flags.bitfield.cpuavx512pf) | |
8548 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF; | |
8549 | if (i.tm.cpu_flags.bitfield.cpuavx512vl) | |
8550 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL; | |
8551 | if (i.tm.cpu_flags.bitfield.cpuavx512dq) | |
8552 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ; | |
8553 | if (i.tm.cpu_flags.bitfield.cpuavx512bw) | |
8554 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW; | |
8555 | if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps) | |
8556 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS; | |
8557 | if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw) | |
8558 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW; | |
8559 | if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg) | |
8560 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG; | |
8561 | if (i.tm.cpu_flags.bitfield.cpuavx512ifma) | |
8562 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA; | |
8563 | if (i.tm.cpu_flags.bitfield.cpuavx512vbmi) | |
8564 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI; | |
8565 | if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2) | |
8566 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2; | |
8567 | if (i.tm.cpu_flags.bitfield.cpuavx512_vnni) | |
8568 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI; | |
462cac58 L |
8569 | if (i.tm.cpu_flags.bitfield.cpuavx512_bf16) |
8570 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BF16; | |
b4a3a7b4 L |
8571 | |
8572 | if (i.tm.cpu_flags.bitfield.cpu8087 | |
8573 | || i.tm.cpu_flags.bitfield.cpu287 | |
8574 | || i.tm.cpu_flags.bitfield.cpu387 | |
8575 | || i.tm.cpu_flags.bitfield.cpu687 | |
8576 | || i.tm.cpu_flags.bitfield.cpufisttp) | |
8577 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; | |
319ff62c JB |
8578 | if (i.has_regmmx |
8579 | || i.tm.base_opcode == 0xf77 /* emms */ | |
8580 | || i.tm.base_opcode == 0xf0e /* femms */) | |
b4a3a7b4 L |
8581 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; |
8582 | if (i.has_regxmm) | |
8583 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; | |
8584 | if (i.has_regymm) | |
8585 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; | |
8586 | if (i.has_regzmm) | |
8587 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; | |
8588 | if (i.tm.cpu_flags.bitfield.cpufxsr) | |
8589 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; | |
8590 | if (i.tm.cpu_flags.bitfield.cpuxsave) | |
8591 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; | |
8592 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) | |
8593 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; | |
8594 | if (i.tm.cpu_flags.bitfield.cpuxsavec) | |
8595 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; | |
8596 | } | |
8597 | #endif | |
8598 | ||
29b0f896 AM |
8599 | /* Tie dwarf2 debug info to the address at the start of the insn. |
8600 | We can't do this after the insn has been output as the current | |
8601 | frag may have been closed off. eg. by frag_var. */ | |
8602 | dwarf2_emit_insn (0); | |
8603 | ||
2bbd9c25 JJ |
8604 | insn_start_frag = frag_now; |
8605 | insn_start_off = frag_now_fix (); | |
8606 | ||
e379e5f3 L |
8607 | if (add_branch_padding_frag_p (&branch)) |
8608 | { | |
8609 | char *p; | |
8610 | /* Branch can be 8 bytes. Leave some room for prefixes. */ | |
8611 | unsigned int max_branch_padding_size = 14; | |
8612 | ||
8613 | /* Align section to boundary. */ | |
8614 | record_alignment (now_seg, align_branch_power); | |
8615 | ||
8616 | /* Make room for padding. */ | |
8617 | frag_grow (max_branch_padding_size); | |
8618 | ||
8619 | /* Start of the padding. */ | |
8620 | p = frag_more (0); | |
8621 | ||
8622 | fragP = frag_now; | |
8623 | ||
8624 | frag_var (rs_machine_dependent, max_branch_padding_size, 0, | |
8625 | ENCODE_RELAX_STATE (BRANCH_PADDING, 0), | |
8626 | NULL, 0, p); | |
8627 | ||
8628 | fragP->tc_frag_data.branch_type = branch; | |
8629 | fragP->tc_frag_data.max_bytes = max_branch_padding_size; | |
8630 | } | |
8631 | ||
29b0f896 | 8632 | /* Output jumps. */ |
0cfa3eb3 | 8633 | if (i.tm.opcode_modifier.jump == JUMP) |
29b0f896 | 8634 | output_branch (); |
0cfa3eb3 JB |
8635 | else if (i.tm.opcode_modifier.jump == JUMP_BYTE |
8636 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 | 8637 | output_jump (); |
0cfa3eb3 | 8638 | else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT) |
29b0f896 AM |
8639 | output_interseg_jump (); |
8640 | else | |
8641 | { | |
8642 | /* Output normal instructions here. */ | |
8643 | char *p; | |
8644 | unsigned char *q; | |
47465058 | 8645 | unsigned int j; |
331d2d0d | 8646 | unsigned int prefix; |
4dffcebc | 8647 | |
e4e00185 | 8648 | if (avoid_fence |
c3949f43 JB |
8649 | && (i.tm.base_opcode == 0xfaee8 |
8650 | || i.tm.base_opcode == 0xfaef0 | |
8651 | || i.tm.base_opcode == 0xfaef8)) | |
e4e00185 AS |
8652 | { |
8653 | /* Encode lfence, mfence, and sfence as | |
8654 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
8655 | offsetT val = 0x240483f0ULL; | |
8656 | p = frag_more (5); | |
8657 | md_number_to_chars (p, val, 5); | |
8658 | return; | |
8659 | } | |
8660 | ||
d022bddd IT |
8661 | /* Some processors fail on LOCK prefix. This options makes |
8662 | assembler ignore LOCK prefix and serves as a workaround. */ | |
8663 | if (omit_lock_prefix) | |
8664 | { | |
8665 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
8666 | return; | |
8667 | i.prefix[LOCK_PREFIX] = 0; | |
8668 | } | |
8669 | ||
e379e5f3 L |
8670 | if (branch) |
8671 | /* Skip if this is a branch. */ | |
8672 | ; | |
8673 | else if (add_fused_jcc_padding_frag_p ()) | |
8674 | { | |
8675 | /* Make room for padding. */ | |
8676 | frag_grow (MAX_FUSED_JCC_PADDING_SIZE); | |
8677 | p = frag_more (0); | |
8678 | ||
8679 | fragP = frag_now; | |
8680 | ||
8681 | frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0, | |
8682 | ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0), | |
8683 | NULL, 0, p); | |
8684 | ||
8685 | fragP->tc_frag_data.branch_type = align_branch_fused; | |
8686 | fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE; | |
8687 | } | |
8688 | else if (add_branch_prefix_frag_p ()) | |
8689 | { | |
8690 | unsigned int max_prefix_size = align_branch_prefix_size; | |
8691 | ||
8692 | /* Make room for padding. */ | |
8693 | frag_grow (max_prefix_size); | |
8694 | p = frag_more (0); | |
8695 | ||
8696 | fragP = frag_now; | |
8697 | ||
8698 | frag_var (rs_machine_dependent, max_prefix_size, 0, | |
8699 | ENCODE_RELAX_STATE (BRANCH_PREFIX, 0), | |
8700 | NULL, 0, p); | |
8701 | ||
8702 | fragP->tc_frag_data.max_bytes = max_prefix_size; | |
8703 | } | |
8704 | ||
43234a1e L |
8705 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
8706 | don't need the explicit prefix. */ | |
8707 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 8708 | { |
c0f3af97 | 8709 | switch (i.tm.opcode_length) |
bc4bd9ab | 8710 | { |
c0f3af97 L |
8711 | case 3: |
8712 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 8713 | { |
c0f3af97 | 8714 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
c3949f43 JB |
8715 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
8716 | || prefix != REPE_PREFIX_OPCODE | |
8717 | || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) | |
8718 | add_prefix (prefix); | |
c0f3af97 L |
8719 | } |
8720 | break; | |
8721 | case 2: | |
8722 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
8723 | { | |
8724 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
c3949f43 | 8725 | add_prefix (prefix); |
4dffcebc | 8726 | } |
c0f3af97 L |
8727 | break; |
8728 | case 1: | |
8729 | break; | |
390c91cf L |
8730 | case 0: |
8731 | /* Check for pseudo prefixes. */ | |
8732 | as_bad_where (insn_start_frag->fr_file, | |
8733 | insn_start_frag->fr_line, | |
8734 | _("pseudo prefix without instruction")); | |
8735 | return; | |
c0f3af97 L |
8736 | default: |
8737 | abort (); | |
bc4bd9ab | 8738 | } |
c0f3af97 | 8739 | |
6d19a37a | 8740 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
8741 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
8742 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
14470f07 L |
8743 | perform IE->LE optimization. A dummy REX_OPCODE prefix |
8744 | is also needed for lea with R_X86_64_GOTPC32_TLSDESC | |
8745 | relocation for GDesc -> IE/LE optimization. */ | |
cf61b747 L |
8746 | if (x86_elf_abi == X86_64_X32_ABI |
8747 | && i.operands == 2 | |
14470f07 L |
8748 | && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF |
8749 | || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC) | |
cf61b747 L |
8750 | && i.prefix[REX_PREFIX] == 0) |
8751 | add_prefix (REX_OPCODE); | |
6d19a37a | 8752 | #endif |
cf61b747 | 8753 | |
c0f3af97 L |
8754 | /* The prefix bytes. */ |
8755 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
8756 | if (*q) | |
8757 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 8758 | } |
ae5c1c7b | 8759 | else |
c0f3af97 L |
8760 | { |
8761 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
8762 | if (*q) | |
8763 | switch (j) | |
8764 | { | |
8765 | case REX_PREFIX: | |
8766 | /* REX byte is encoded in VEX prefix. */ | |
8767 | break; | |
8768 | case SEG_PREFIX: | |
8769 | case ADDR_PREFIX: | |
8770 | FRAG_APPEND_1_CHAR (*q); | |
8771 | break; | |
8772 | default: | |
8773 | /* There should be no other prefixes for instructions | |
8774 | with VEX prefix. */ | |
8775 | abort (); | |
8776 | } | |
8777 | ||
43234a1e L |
8778 | /* For EVEX instructions i.vrex should become 0 after |
8779 | build_evex_prefix. For VEX instructions upper 16 registers | |
8780 | aren't available, so VREX should be 0. */ | |
8781 | if (i.vrex) | |
8782 | abort (); | |
c0f3af97 L |
8783 | /* Now the VEX prefix. */ |
8784 | p = frag_more (i.vex.length); | |
8785 | for (j = 0; j < i.vex.length; j++) | |
8786 | p[j] = i.vex.bytes[j]; | |
8787 | } | |
252b5132 | 8788 | |
29b0f896 | 8789 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 8790 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
8791 | { |
8792 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
8793 | } | |
8794 | else | |
8795 | { | |
4dffcebc | 8796 | switch (i.tm.opcode_length) |
331d2d0d | 8797 | { |
43234a1e L |
8798 | case 4: |
8799 | p = frag_more (4); | |
8800 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
8801 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
8802 | break; | |
4dffcebc | 8803 | case 3: |
331d2d0d L |
8804 | p = frag_more (3); |
8805 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
8806 | break; |
8807 | case 2: | |
8808 | p = frag_more (2); | |
8809 | break; | |
8810 | default: | |
8811 | abort (); | |
8812 | break; | |
331d2d0d | 8813 | } |
0f10071e | 8814 | |
29b0f896 AM |
8815 | /* Put out high byte first: can't use md_number_to_chars! */ |
8816 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
8817 | *p = i.tm.base_opcode & 0xff; | |
8818 | } | |
3e73aa7c | 8819 | |
29b0f896 | 8820 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 8821 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 8822 | { |
4a3523fa L |
8823 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
8824 | | i.rm.reg << 3 | |
8825 | | i.rm.mode << 6)); | |
29b0f896 AM |
8826 | /* If i.rm.regmem == ESP (4) |
8827 | && i.rm.mode != (Register mode) | |
8828 | && not 16 bit | |
8829 | ==> need second modrm byte. */ | |
8830 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
8831 | && i.rm.mode != 3 | |
dc821c5f | 8832 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
4a3523fa L |
8833 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
8834 | | i.sib.index << 3 | |
8835 | | i.sib.scale << 6)); | |
29b0f896 | 8836 | } |
3e73aa7c | 8837 | |
29b0f896 | 8838 | if (i.disp_operands) |
2bbd9c25 | 8839 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 8840 | |
29b0f896 | 8841 | if (i.imm_operands) |
2bbd9c25 | 8842 | output_imm (insn_start_frag, insn_start_off); |
9c33702b JB |
8843 | |
8844 | /* | |
8845 | * frag_now_fix () returning plain abs_section_offset when we're in the | |
8846 | * absolute section, and abs_section_offset not getting updated as data | |
8847 | * gets added to the frag breaks the logic below. | |
8848 | */ | |
8849 | if (now_seg != absolute_section) | |
8850 | { | |
8851 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); | |
8852 | if (j > 15) | |
8853 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), | |
8854 | j); | |
e379e5f3 L |
8855 | else if (fragP) |
8856 | { | |
8857 | /* NB: Don't add prefix with GOTPC relocation since | |
8858 | output_disp() above depends on the fixed encoding | |
8859 | length. Can't add prefix with TLS relocation since | |
8860 | it breaks TLS linker optimization. */ | |
8861 | unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j; | |
8862 | /* Prefix count on the current instruction. */ | |
8863 | unsigned int count = i.vex.length; | |
8864 | unsigned int k; | |
8865 | for (k = 0; k < ARRAY_SIZE (i.prefix); k++) | |
8866 | /* REX byte is encoded in VEX/EVEX prefix. */ | |
8867 | if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length)) | |
8868 | count++; | |
8869 | ||
8870 | /* Count prefixes for extended opcode maps. */ | |
8871 | if (!i.vex.length) | |
8872 | switch (i.tm.opcode_length) | |
8873 | { | |
8874 | case 3: | |
8875 | if (((i.tm.base_opcode >> 16) & 0xff) == 0xf) | |
8876 | { | |
8877 | count++; | |
8878 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
8879 | { | |
8880 | case 0x38: | |
8881 | case 0x3a: | |
8882 | count++; | |
8883 | break; | |
8884 | default: | |
8885 | break; | |
8886 | } | |
8887 | } | |
8888 | break; | |
8889 | case 2: | |
8890 | if (((i.tm.base_opcode >> 8) & 0xff) == 0xf) | |
8891 | count++; | |
8892 | break; | |
8893 | case 1: | |
8894 | break; | |
8895 | default: | |
8896 | abort (); | |
8897 | } | |
8898 | ||
8899 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
8900 | == BRANCH_PREFIX) | |
8901 | { | |
8902 | /* Set the maximum prefix size in BRANCH_PREFIX | |
8903 | frag. */ | |
8904 | if (fragP->tc_frag_data.max_bytes > max) | |
8905 | fragP->tc_frag_data.max_bytes = max; | |
8906 | if (fragP->tc_frag_data.max_bytes > count) | |
8907 | fragP->tc_frag_data.max_bytes -= count; | |
8908 | else | |
8909 | fragP->tc_frag_data.max_bytes = 0; | |
8910 | } | |
8911 | else | |
8912 | { | |
8913 | /* Remember the maximum prefix size in FUSED_JCC_PADDING | |
8914 | frag. */ | |
8915 | unsigned int max_prefix_size; | |
8916 | if (align_branch_prefix_size > max) | |
8917 | max_prefix_size = max; | |
8918 | else | |
8919 | max_prefix_size = align_branch_prefix_size; | |
8920 | if (max_prefix_size > count) | |
8921 | fragP->tc_frag_data.max_prefix_length | |
8922 | = max_prefix_size - count; | |
8923 | } | |
8924 | ||
8925 | /* Use existing segment prefix if possible. Use CS | |
8926 | segment prefix in 64-bit mode. In 32-bit mode, use SS | |
8927 | segment prefix with ESP/EBP base register and use DS | |
8928 | segment prefix without ESP/EBP base register. */ | |
8929 | if (i.prefix[SEG_PREFIX]) | |
8930 | fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX]; | |
8931 | else if (flag_code == CODE_64BIT) | |
8932 | fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE; | |
8933 | else if (i.base_reg | |
8934 | && (i.base_reg->reg_num == 4 | |
8935 | || i.base_reg->reg_num == 5)) | |
8936 | fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE; | |
8937 | else | |
8938 | fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE; | |
8939 | } | |
9c33702b | 8940 | } |
29b0f896 | 8941 | } |
252b5132 | 8942 | |
e379e5f3 L |
8943 | /* NB: Don't work with COND_JUMP86 without i386. */ |
8944 | if (align_branch_power | |
8945 | && now_seg != absolute_section | |
8946 | && cpu_arch_flags.bitfield.cpui386) | |
8947 | { | |
8948 | /* Terminate each frag so that we can add prefix and check for | |
8949 | fused jcc. */ | |
8950 | frag_wane (frag_now); | |
8951 | frag_new (0); | |
8952 | } | |
8953 | ||
29b0f896 AM |
8954 | #ifdef DEBUG386 |
8955 | if (flag_debug) | |
8956 | { | |
7b81dfbb | 8957 | pi ("" /*line*/, &i); |
29b0f896 AM |
8958 | } |
8959 | #endif /* DEBUG386 */ | |
8960 | } | |
252b5132 | 8961 | |
e205caa7 L |
8962 | /* Return the size of the displacement operand N. */ |
8963 | ||
8964 | static int | |
8965 | disp_size (unsigned int n) | |
8966 | { | |
8967 | int size = 4; | |
43234a1e | 8968 | |
b5014f7a | 8969 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
8970 | size = 8; |
8971 | else if (i.types[n].bitfield.disp8) | |
8972 | size = 1; | |
8973 | else if (i.types[n].bitfield.disp16) | |
8974 | size = 2; | |
e205caa7 L |
8975 | return size; |
8976 | } | |
8977 | ||
8978 | /* Return the size of the immediate operand N. */ | |
8979 | ||
8980 | static int | |
8981 | imm_size (unsigned int n) | |
8982 | { | |
8983 | int size = 4; | |
40fb9820 L |
8984 | if (i.types[n].bitfield.imm64) |
8985 | size = 8; | |
8986 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
8987 | size = 1; | |
8988 | else if (i.types[n].bitfield.imm16) | |
8989 | size = 2; | |
e205caa7 L |
8990 | return size; |
8991 | } | |
8992 | ||
29b0f896 | 8993 | static void |
64e74474 | 8994 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
8995 | { |
8996 | char *p; | |
8997 | unsigned int n; | |
252b5132 | 8998 | |
29b0f896 AM |
8999 | for (n = 0; n < i.operands; n++) |
9000 | { | |
b5014f7a | 9001 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
9002 | { |
9003 | if (i.op[n].disps->X_op == O_constant) | |
9004 | { | |
e205caa7 | 9005 | int size = disp_size (n); |
43234a1e | 9006 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 9007 | |
629cfaf1 JB |
9008 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
9009 | size); | |
29b0f896 AM |
9010 | p = frag_more (size); |
9011 | md_number_to_chars (p, val, size); | |
9012 | } | |
9013 | else | |
9014 | { | |
f86103b7 | 9015 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 9016 | int size = disp_size (n); |
40fb9820 | 9017 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 9018 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 9019 | fixS *fixP; |
29b0f896 | 9020 | |
e205caa7 | 9021 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 9022 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 9023 | |
29b0f896 AM |
9024 | /* The PC relative address is computed relative |
9025 | to the instruction boundary, so in case immediate | |
9026 | fields follows, we need to adjust the value. */ | |
9027 | if (pcrel && i.imm_operands) | |
9028 | { | |
29b0f896 | 9029 | unsigned int n1; |
e205caa7 | 9030 | int sz = 0; |
252b5132 | 9031 | |
29b0f896 | 9032 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 9033 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 9034 | { |
e205caa7 L |
9035 | /* Only one immediate is allowed for PC |
9036 | relative address. */ | |
9c2799c2 | 9037 | gas_assert (sz == 0); |
e205caa7 L |
9038 | sz = imm_size (n1); |
9039 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 9040 | } |
29b0f896 | 9041 | /* We should find the immediate. */ |
9c2799c2 | 9042 | gas_assert (sz != 0); |
29b0f896 | 9043 | } |
520dc8e8 | 9044 | |
29b0f896 | 9045 | p = frag_more (size); |
d258b828 | 9046 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 9047 | if (GOT_symbol |
2bbd9c25 | 9048 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 9049 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
9050 | || reloc_type == BFD_RELOC_X86_64_32S |
9051 | || (reloc_type == BFD_RELOC_64 | |
9052 | && object_64bit)) | |
d6ab8113 JB |
9053 | && (i.op[n].disps->X_op == O_symbol |
9054 | || (i.op[n].disps->X_op == O_add | |
9055 | && ((symbol_get_value_expression | |
9056 | (i.op[n].disps->X_op_symbol)->X_op) | |
9057 | == O_subtract)))) | |
9058 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 | 9059 | { |
4fa24527 | 9060 | if (!object_64bit) |
7b81dfbb AJ |
9061 | { |
9062 | reloc_type = BFD_RELOC_386_GOTPC; | |
e379e5f3 | 9063 | i.has_gotpc_tls_reloc = TRUE; |
d583596c JB |
9064 | i.op[n].imms->X_add_number += |
9065 | encoding_length (insn_start_frag, insn_start_off, p); | |
7b81dfbb AJ |
9066 | } |
9067 | else if (reloc_type == BFD_RELOC_64) | |
9068 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 9069 | else |
7b81dfbb AJ |
9070 | /* Don't do the adjustment for x86-64, as there |
9071 | the pcrel addressing is relative to the _next_ | |
9072 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 9073 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 9074 | } |
e379e5f3 L |
9075 | else if (align_branch_power) |
9076 | { | |
9077 | switch (reloc_type) | |
9078 | { | |
9079 | case BFD_RELOC_386_TLS_GD: | |
9080 | case BFD_RELOC_386_TLS_LDM: | |
9081 | case BFD_RELOC_386_TLS_IE: | |
9082 | case BFD_RELOC_386_TLS_IE_32: | |
9083 | case BFD_RELOC_386_TLS_GOTIE: | |
9084 | case BFD_RELOC_386_TLS_GOTDESC: | |
9085 | case BFD_RELOC_386_TLS_DESC_CALL: | |
9086 | case BFD_RELOC_X86_64_TLSGD: | |
9087 | case BFD_RELOC_X86_64_TLSLD: | |
9088 | case BFD_RELOC_X86_64_GOTTPOFF: | |
9089 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: | |
9090 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
9091 | i.has_gotpc_tls_reloc = TRUE; | |
9092 | default: | |
9093 | break; | |
9094 | } | |
9095 | } | |
02a86693 L |
9096 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
9097 | size, i.op[n].disps, pcrel, | |
9098 | reloc_type); | |
9099 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
9100 | "test %reg, mem" and "binop mem, %reg" where binop | |
9101 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
9102 | instructions without data prefix. Always generate |
9103 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
9104 | if (i.prefix[DATA_PREFIX] == 0 | |
9105 | && (generate_relax_relocations | |
9106 | || (!object_64bit | |
9107 | && i.rm.mode == 0 | |
9108 | && i.rm.regmem == 5)) | |
0cb4071e L |
9109 | && (i.rm.mode == 2 |
9110 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
2ae4c703 | 9111 | && !is_any_vex_encoding(&i.tm) |
02a86693 L |
9112 | && ((i.operands == 1 |
9113 | && i.tm.base_opcode == 0xff | |
9114 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
9115 | || (i.operands == 2 | |
9116 | && (i.tm.base_opcode == 0x8b | |
9117 | || i.tm.base_opcode == 0x85 | |
2ae4c703 | 9118 | || (i.tm.base_opcode & ~0x38) == 0x03)))) |
02a86693 L |
9119 | { |
9120 | if (object_64bit) | |
9121 | { | |
9122 | fixP->fx_tcbit = i.rex != 0; | |
9123 | if (i.base_reg | |
e968fc9b | 9124 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
9125 | fixP->fx_tcbit2 = 1; |
9126 | } | |
9127 | else | |
9128 | fixP->fx_tcbit2 = 1; | |
9129 | } | |
29b0f896 AM |
9130 | } |
9131 | } | |
9132 | } | |
9133 | } | |
252b5132 | 9134 | |
29b0f896 | 9135 | static void |
64e74474 | 9136 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
9137 | { |
9138 | char *p; | |
9139 | unsigned int n; | |
252b5132 | 9140 | |
29b0f896 AM |
9141 | for (n = 0; n < i.operands; n++) |
9142 | { | |
43234a1e L |
9143 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
9144 | if (i.rounding && (int) n == i.rounding->operand) | |
9145 | continue; | |
9146 | ||
40fb9820 | 9147 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
9148 | { |
9149 | if (i.op[n].imms->X_op == O_constant) | |
9150 | { | |
e205caa7 | 9151 | int size = imm_size (n); |
29b0f896 | 9152 | offsetT val; |
b4cac588 | 9153 | |
29b0f896 AM |
9154 | val = offset_in_range (i.op[n].imms->X_add_number, |
9155 | size); | |
9156 | p = frag_more (size); | |
9157 | md_number_to_chars (p, val, size); | |
9158 | } | |
9159 | else | |
9160 | { | |
9161 | /* Not absolute_section. | |
9162 | Need a 32-bit fixup (don't support 8bit | |
9163 | non-absolute imms). Try to support other | |
9164 | sizes ... */ | |
f86103b7 | 9165 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
9166 | int size = imm_size (n); |
9167 | int sign; | |
29b0f896 | 9168 | |
40fb9820 | 9169 | if (i.types[n].bitfield.imm32s |
a7d61044 | 9170 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 9171 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 9172 | sign = 1; |
e205caa7 L |
9173 | else |
9174 | sign = 0; | |
520dc8e8 | 9175 | |
29b0f896 | 9176 | p = frag_more (size); |
d258b828 | 9177 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 9178 | |
2bbd9c25 JJ |
9179 | /* This is tough to explain. We end up with this one if we |
9180 | * have operands that look like | |
9181 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
9182 | * obtain the absolute address of the GOT, and it is strongly | |
9183 | * preferable from a performance point of view to avoid using | |
9184 | * a runtime relocation for this. The actual sequence of | |
9185 | * instructions often look something like: | |
9186 | * | |
9187 | * call .L66 | |
9188 | * .L66: | |
9189 | * popl %ebx | |
9190 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
9191 | * | |
9192 | * The call and pop essentially return the absolute address | |
9193 | * of the label .L66 and store it in %ebx. The linker itself | |
9194 | * will ultimately change the first operand of the addl so | |
9195 | * that %ebx points to the GOT, but to keep things simple, the | |
9196 | * .o file must have this operand set so that it generates not | |
9197 | * the absolute address of .L66, but the absolute address of | |
9198 | * itself. This allows the linker itself simply treat a GOTPC | |
9199 | * relocation as asking for a pcrel offset to the GOT to be | |
9200 | * added in, and the addend of the relocation is stored in the | |
9201 | * operand field for the instruction itself. | |
9202 | * | |
9203 | * Our job here is to fix the operand so that it would add | |
9204 | * the correct offset so that %ebx would point to itself. The | |
9205 | * thing that is tricky is that .-.L66 will point to the | |
9206 | * beginning of the instruction, so we need to further modify | |
9207 | * the operand so that it will point to itself. There are | |
9208 | * other cases where you have something like: | |
9209 | * | |
9210 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
9211 | * | |
9212 | * and here no correction would be required. Internally in | |
9213 | * the assembler we treat operands of this form as not being | |
9214 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
9215 | * whether it would simplify matters to do it this way. Who | |
9216 | * knows. In earlier versions of the PIC patches, the | |
9217 | * pcrel_adjust field was used to store the correction, but | |
9218 | * since the expression is not pcrel, I felt it would be | |
9219 | * confusing to do it this way. */ | |
9220 | ||
d6ab8113 | 9221 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
9222 | || reloc_type == BFD_RELOC_X86_64_32S |
9223 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
9224 | && GOT_symbol |
9225 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
9226 | && (i.op[n].imms->X_op == O_symbol | |
9227 | || (i.op[n].imms->X_op == O_add | |
9228 | && ((symbol_get_value_expression | |
9229 | (i.op[n].imms->X_op_symbol)->X_op) | |
9230 | == O_subtract)))) | |
9231 | { | |
4fa24527 | 9232 | if (!object_64bit) |
d6ab8113 | 9233 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 9234 | else if (size == 4) |
d6ab8113 | 9235 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
9236 | else if (size == 8) |
9237 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
e379e5f3 | 9238 | i.has_gotpc_tls_reloc = TRUE; |
d583596c JB |
9239 | i.op[n].imms->X_add_number += |
9240 | encoding_length (insn_start_frag, insn_start_off, p); | |
29b0f896 | 9241 | } |
29b0f896 AM |
9242 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
9243 | i.op[n].imms, 0, reloc_type); | |
9244 | } | |
9245 | } | |
9246 | } | |
252b5132 RH |
9247 | } |
9248 | \f | |
d182319b JB |
9249 | /* x86_cons_fix_new is called via the expression parsing code when a |
9250 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
9251 | static int cons_sign = -1; |
9252 | ||
9253 | void | |
e3bb37b5 | 9254 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 9255 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 9256 | { |
d258b828 | 9257 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
9258 | |
9259 | #ifdef TE_PE | |
9260 | if (exp->X_op == O_secrel) | |
9261 | { | |
9262 | exp->X_op = O_symbol; | |
9263 | r = BFD_RELOC_32_SECREL; | |
9264 | } | |
9265 | #endif | |
9266 | ||
9267 | fix_new_exp (frag, off, len, exp, 0, r); | |
9268 | } | |
9269 | ||
357d1bd8 L |
9270 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
9271 | purpose of the `.dc.a' internal pseudo-op. */ | |
9272 | ||
9273 | int | |
9274 | x86_address_bytes (void) | |
9275 | { | |
9276 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
9277 | return 4; | |
9278 | return stdoutput->arch_info->bits_per_address / 8; | |
9279 | } | |
9280 | ||
d382c579 TG |
9281 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
9282 | || defined (LEX_AT) | |
d258b828 | 9283 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 9284 | #else |
f3c180ae AM |
9285 | /* Parse operands of the form |
9286 | <symbol>@GOTOFF+<nnn> | |
9287 | and similar .plt or .got references. | |
9288 | ||
9289 | If we find one, set up the correct relocation in RELOC and copy the | |
9290 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
9291 | parsing by the calling routine. Return this buffer, and if ADJUST | |
9292 | is non-null set it to the length of the string we removed from the | |
9293 | input line. Otherwise return NULL. */ | |
9294 | static char * | |
91d6fa6a | 9295 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 9296 | int *adjust, |
d258b828 | 9297 | i386_operand_type *types) |
f3c180ae | 9298 | { |
7b81dfbb AJ |
9299 | /* Some of the relocations depend on the size of what field is to |
9300 | be relocated. But in our callers i386_immediate and i386_displacement | |
9301 | we don't yet know the operand size (this will be set by insn | |
9302 | matching). Hence we record the word32 relocation here, | |
9303 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
9304 | static const struct { |
9305 | const char *str; | |
cff8d58a | 9306 | int len; |
4fa24527 | 9307 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 9308 | const i386_operand_type types64; |
f3c180ae | 9309 | } gotrel[] = { |
8ce3d284 | 9310 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
9311 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
9312 | BFD_RELOC_SIZE32 }, | |
9313 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 9314 | #endif |
cff8d58a L |
9315 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
9316 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 9317 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
9318 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
9319 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 9320 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9321 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
9322 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 9323 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
9324 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
9325 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 9326 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
9327 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
9328 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 9329 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9330 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
9331 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 9332 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9333 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
9334 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9335 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9336 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
9337 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 9338 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9339 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
9340 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 9341 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9342 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
9343 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 9344 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
9345 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
9346 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9347 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9348 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
9349 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 9350 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
9351 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
9352 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9353 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9354 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
9355 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9356 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9357 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
9358 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 9359 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
9360 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
9361 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 9362 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9363 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
9364 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 9365 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
9366 | }; |
9367 | char *cp; | |
9368 | unsigned int j; | |
9369 | ||
d382c579 | 9370 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
9371 | if (!IS_ELF) |
9372 | return NULL; | |
d382c579 | 9373 | #endif |
718ddfc0 | 9374 | |
f3c180ae | 9375 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 9376 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
9377 | return NULL; |
9378 | ||
47465058 | 9379 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 9380 | { |
cff8d58a | 9381 | int len = gotrel[j].len; |
28f81592 | 9382 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 9383 | { |
4fa24527 | 9384 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 9385 | { |
28f81592 AM |
9386 | int first, second; |
9387 | char *tmpbuf, *past_reloc; | |
f3c180ae | 9388 | |
91d6fa6a | 9389 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 9390 | |
3956db08 JB |
9391 | if (types) |
9392 | { | |
9393 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
9394 | { |
9395 | types->bitfield.imm32 = 1; | |
9396 | types->bitfield.disp32 = 1; | |
9397 | } | |
3956db08 JB |
9398 | else |
9399 | *types = gotrel[j].types64; | |
9400 | } | |
9401 | ||
8fd4256d | 9402 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
9403 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
9404 | ||
28f81592 | 9405 | /* The length of the first part of our input line. */ |
f3c180ae | 9406 | first = cp - input_line_pointer; |
28f81592 AM |
9407 | |
9408 | /* The second part goes from after the reloc token until | |
67c11a9b | 9409 | (and including) an end_of_line char or comma. */ |
28f81592 | 9410 | past_reloc = cp + 1 + len; |
67c11a9b AM |
9411 | cp = past_reloc; |
9412 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
9413 | ++cp; | |
9414 | second = cp + 1 - past_reloc; | |
28f81592 AM |
9415 | |
9416 | /* Allocate and copy string. The trailing NUL shouldn't | |
9417 | be necessary, but be safe. */ | |
add39d23 | 9418 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 9419 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
9420 | if (second != 0 && *past_reloc != ' ') |
9421 | /* Replace the relocation token with ' ', so that | |
9422 | errors like foo@GOTOFF1 will be detected. */ | |
9423 | tmpbuf[first++] = ' '; | |
af89796a L |
9424 | else |
9425 | /* Increment length by 1 if the relocation token is | |
9426 | removed. */ | |
9427 | len++; | |
9428 | if (adjust) | |
9429 | *adjust = len; | |
0787a12d AM |
9430 | memcpy (tmpbuf + first, past_reloc, second); |
9431 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
9432 | return tmpbuf; |
9433 | } | |
9434 | ||
4fa24527 JB |
9435 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
9436 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
9437 | return NULL; |
9438 | } | |
9439 | } | |
9440 | ||
9441 | /* Might be a symbol version string. Don't as_bad here. */ | |
9442 | return NULL; | |
9443 | } | |
4e4f7c87 | 9444 | #endif |
f3c180ae | 9445 | |
a988325c NC |
9446 | #ifdef TE_PE |
9447 | #ifdef lex_got | |
9448 | #undef lex_got | |
9449 | #endif | |
9450 | /* Parse operands of the form | |
9451 | <symbol>@SECREL32+<nnn> | |
9452 | ||
9453 | If we find one, set up the correct relocation in RELOC and copy the | |
9454 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
9455 | parsing by the calling routine. Return this buffer, and if ADJUST | |
9456 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
9457 | input line. Otherwise return NULL. |
9458 | ||
a988325c NC |
9459 | This function is copied from the ELF version above adjusted for PE targets. */ |
9460 | ||
9461 | static char * | |
9462 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
9463 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 9464 | i386_operand_type *types) |
a988325c NC |
9465 | { |
9466 | static const struct | |
9467 | { | |
9468 | const char *str; | |
9469 | int len; | |
9470 | const enum bfd_reloc_code_real rel[2]; | |
9471 | const i386_operand_type types64; | |
9472 | } | |
9473 | gotrel[] = | |
9474 | { | |
9475 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
9476 | BFD_RELOC_32_SECREL }, | |
9477 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
9478 | }; | |
9479 | ||
9480 | char *cp; | |
9481 | unsigned j; | |
9482 | ||
9483 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
9484 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
9485 | return NULL; | |
9486 | ||
9487 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
9488 | { | |
9489 | int len = gotrel[j].len; | |
9490 | ||
9491 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
9492 | { | |
9493 | if (gotrel[j].rel[object_64bit] != 0) | |
9494 | { | |
9495 | int first, second; | |
9496 | char *tmpbuf, *past_reloc; | |
9497 | ||
9498 | *rel = gotrel[j].rel[object_64bit]; | |
9499 | if (adjust) | |
9500 | *adjust = len; | |
9501 | ||
9502 | if (types) | |
9503 | { | |
9504 | if (flag_code != CODE_64BIT) | |
9505 | { | |
9506 | types->bitfield.imm32 = 1; | |
9507 | types->bitfield.disp32 = 1; | |
9508 | } | |
9509 | else | |
9510 | *types = gotrel[j].types64; | |
9511 | } | |
9512 | ||
9513 | /* The length of the first part of our input line. */ | |
9514 | first = cp - input_line_pointer; | |
9515 | ||
9516 | /* The second part goes from after the reloc token until | |
9517 | (and including) an end_of_line char or comma. */ | |
9518 | past_reloc = cp + 1 + len; | |
9519 | cp = past_reloc; | |
9520 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
9521 | ++cp; | |
9522 | second = cp + 1 - past_reloc; | |
9523 | ||
9524 | /* Allocate and copy string. The trailing NUL shouldn't | |
9525 | be necessary, but be safe. */ | |
add39d23 | 9526 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
9527 | memcpy (tmpbuf, input_line_pointer, first); |
9528 | if (second != 0 && *past_reloc != ' ') | |
9529 | /* Replace the relocation token with ' ', so that | |
9530 | errors like foo@SECLREL321 will be detected. */ | |
9531 | tmpbuf[first++] = ' '; | |
9532 | memcpy (tmpbuf + first, past_reloc, second); | |
9533 | tmpbuf[first + second] = '\0'; | |
9534 | return tmpbuf; | |
9535 | } | |
9536 | ||
9537 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
9538 | gotrel[j].str, 1 << (5 + object_64bit)); | |
9539 | return NULL; | |
9540 | } | |
9541 | } | |
9542 | ||
9543 | /* Might be a symbol version string. Don't as_bad here. */ | |
9544 | return NULL; | |
9545 | } | |
9546 | ||
9547 | #endif /* TE_PE */ | |
9548 | ||
62ebcb5c | 9549 | bfd_reloc_code_real_type |
e3bb37b5 | 9550 | x86_cons (expressionS *exp, int size) |
f3c180ae | 9551 | { |
62ebcb5c AM |
9552 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
9553 | ||
ee86248c JB |
9554 | intel_syntax = -intel_syntax; |
9555 | ||
3c7b9c2c | 9556 | exp->X_md = 0; |
4fa24527 | 9557 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
9558 | { |
9559 | /* Handle @GOTOFF and the like in an expression. */ | |
9560 | char *save; | |
9561 | char *gotfree_input_line; | |
4a57f2cf | 9562 | int adjust = 0; |
f3c180ae AM |
9563 | |
9564 | save = input_line_pointer; | |
d258b828 | 9565 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
9566 | if (gotfree_input_line) |
9567 | input_line_pointer = gotfree_input_line; | |
9568 | ||
9569 | expression (exp); | |
9570 | ||
9571 | if (gotfree_input_line) | |
9572 | { | |
9573 | /* expression () has merrily parsed up to the end of line, | |
9574 | or a comma - in the wrong buffer. Transfer how far | |
9575 | input_line_pointer has moved to the right buffer. */ | |
9576 | input_line_pointer = (save | |
9577 | + (input_line_pointer - gotfree_input_line) | |
9578 | + adjust); | |
9579 | free (gotfree_input_line); | |
3992d3b7 AM |
9580 | if (exp->X_op == O_constant |
9581 | || exp->X_op == O_absent | |
9582 | || exp->X_op == O_illegal | |
0398aac5 | 9583 | || exp->X_op == O_register |
3992d3b7 AM |
9584 | || exp->X_op == O_big) |
9585 | { | |
9586 | char c = *input_line_pointer; | |
9587 | *input_line_pointer = 0; | |
9588 | as_bad (_("missing or invalid expression `%s'"), save); | |
9589 | *input_line_pointer = c; | |
9590 | } | |
b9519cfe L |
9591 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
9592 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
9593 | && exp->X_op != O_symbol) | |
9594 | { | |
9595 | char c = *input_line_pointer; | |
9596 | *input_line_pointer = 0; | |
9597 | as_bad (_("invalid PLT expression `%s'"), save); | |
9598 | *input_line_pointer = c; | |
9599 | } | |
f3c180ae AM |
9600 | } |
9601 | } | |
9602 | else | |
9603 | expression (exp); | |
ee86248c JB |
9604 | |
9605 | intel_syntax = -intel_syntax; | |
9606 | ||
9607 | if (intel_syntax) | |
9608 | i386_intel_simplify (exp); | |
62ebcb5c AM |
9609 | |
9610 | return got_reloc; | |
f3c180ae | 9611 | } |
f3c180ae | 9612 | |
9f32dd5b L |
9613 | static void |
9614 | signed_cons (int size) | |
6482c264 | 9615 | { |
d182319b JB |
9616 | if (flag_code == CODE_64BIT) |
9617 | cons_sign = 1; | |
9618 | cons (size); | |
9619 | cons_sign = -1; | |
6482c264 NC |
9620 | } |
9621 | ||
d182319b | 9622 | #ifdef TE_PE |
6482c264 | 9623 | static void |
7016a5d5 | 9624 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
9625 | { |
9626 | expressionS exp; | |
9627 | ||
9628 | do | |
9629 | { | |
9630 | expression (&exp); | |
9631 | if (exp.X_op == O_symbol) | |
9632 | exp.X_op = O_secrel; | |
9633 | ||
9634 | emit_expr (&exp, 4); | |
9635 | } | |
9636 | while (*input_line_pointer++ == ','); | |
9637 | ||
9638 | input_line_pointer--; | |
9639 | demand_empty_rest_of_line (); | |
9640 | } | |
6482c264 NC |
9641 | #endif |
9642 | ||
43234a1e L |
9643 | /* Handle Vector operations. */ |
9644 | ||
9645 | static char * | |
9646 | check_VecOperations (char *op_string, char *op_end) | |
9647 | { | |
9648 | const reg_entry *mask; | |
9649 | const char *saved; | |
9650 | char *end_op; | |
9651 | ||
9652 | while (*op_string | |
9653 | && (op_end == NULL || op_string < op_end)) | |
9654 | { | |
9655 | saved = op_string; | |
9656 | if (*op_string == '{') | |
9657 | { | |
9658 | op_string++; | |
9659 | ||
9660 | /* Check broadcasts. */ | |
9661 | if (strncmp (op_string, "1to", 3) == 0) | |
9662 | { | |
9663 | int bcst_type; | |
9664 | ||
9665 | if (i.broadcast) | |
9666 | goto duplicated_vec_op; | |
9667 | ||
9668 | op_string += 3; | |
9669 | if (*op_string == '8') | |
8e6e0792 | 9670 | bcst_type = 8; |
b28d1bda | 9671 | else if (*op_string == '4') |
8e6e0792 | 9672 | bcst_type = 4; |
b28d1bda | 9673 | else if (*op_string == '2') |
8e6e0792 | 9674 | bcst_type = 2; |
43234a1e L |
9675 | else if (*op_string == '1' |
9676 | && *(op_string+1) == '6') | |
9677 | { | |
8e6e0792 | 9678 | bcst_type = 16; |
43234a1e L |
9679 | op_string++; |
9680 | } | |
9681 | else | |
9682 | { | |
9683 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
9684 | return NULL; | |
9685 | } | |
9686 | op_string++; | |
9687 | ||
9688 | broadcast_op.type = bcst_type; | |
9689 | broadcast_op.operand = this_operand; | |
1f75763a | 9690 | broadcast_op.bytes = 0; |
43234a1e L |
9691 | i.broadcast = &broadcast_op; |
9692 | } | |
9693 | /* Check masking operation. */ | |
9694 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
9695 | { | |
9696 | /* k0 can't be used for write mask. */ | |
f74a6307 | 9697 | if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num) |
43234a1e | 9698 | { |
6d2cd6b2 JB |
9699 | as_bad (_("`%s%s' can't be used for write mask"), |
9700 | register_prefix, mask->reg_name); | |
43234a1e L |
9701 | return NULL; |
9702 | } | |
9703 | ||
9704 | if (!i.mask) | |
9705 | { | |
9706 | mask_op.mask = mask; | |
9707 | mask_op.zeroing = 0; | |
9708 | mask_op.operand = this_operand; | |
9709 | i.mask = &mask_op; | |
9710 | } | |
9711 | else | |
9712 | { | |
9713 | if (i.mask->mask) | |
9714 | goto duplicated_vec_op; | |
9715 | ||
9716 | i.mask->mask = mask; | |
9717 | ||
9718 | /* Only "{z}" is allowed here. No need to check | |
9719 | zeroing mask explicitly. */ | |
9720 | if (i.mask->operand != this_operand) | |
9721 | { | |
9722 | as_bad (_("invalid write mask `%s'"), saved); | |
9723 | return NULL; | |
9724 | } | |
9725 | } | |
9726 | ||
9727 | op_string = end_op; | |
9728 | } | |
9729 | /* Check zeroing-flag for masking operation. */ | |
9730 | else if (*op_string == 'z') | |
9731 | { | |
9732 | if (!i.mask) | |
9733 | { | |
9734 | mask_op.mask = NULL; | |
9735 | mask_op.zeroing = 1; | |
9736 | mask_op.operand = this_operand; | |
9737 | i.mask = &mask_op; | |
9738 | } | |
9739 | else | |
9740 | { | |
9741 | if (i.mask->zeroing) | |
9742 | { | |
9743 | duplicated_vec_op: | |
9744 | as_bad (_("duplicated `%s'"), saved); | |
9745 | return NULL; | |
9746 | } | |
9747 | ||
9748 | i.mask->zeroing = 1; | |
9749 | ||
9750 | /* Only "{%k}" is allowed here. No need to check mask | |
9751 | register explicitly. */ | |
9752 | if (i.mask->operand != this_operand) | |
9753 | { | |
9754 | as_bad (_("invalid zeroing-masking `%s'"), | |
9755 | saved); | |
9756 | return NULL; | |
9757 | } | |
9758 | } | |
9759 | ||
9760 | op_string++; | |
9761 | } | |
9762 | else | |
9763 | goto unknown_vec_op; | |
9764 | ||
9765 | if (*op_string != '}') | |
9766 | { | |
9767 | as_bad (_("missing `}' in `%s'"), saved); | |
9768 | return NULL; | |
9769 | } | |
9770 | op_string++; | |
0ba3a731 L |
9771 | |
9772 | /* Strip whitespace since the addition of pseudo prefixes | |
9773 | changed how the scrubber treats '{'. */ | |
9774 | if (is_space_char (*op_string)) | |
9775 | ++op_string; | |
9776 | ||
43234a1e L |
9777 | continue; |
9778 | } | |
9779 | unknown_vec_op: | |
9780 | /* We don't know this one. */ | |
9781 | as_bad (_("unknown vector operation: `%s'"), saved); | |
9782 | return NULL; | |
9783 | } | |
9784 | ||
6d2cd6b2 JB |
9785 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
9786 | { | |
9787 | as_bad (_("zeroing-masking only allowed with write mask")); | |
9788 | return NULL; | |
9789 | } | |
9790 | ||
43234a1e L |
9791 | return op_string; |
9792 | } | |
9793 | ||
252b5132 | 9794 | static int |
70e41ade | 9795 | i386_immediate (char *imm_start) |
252b5132 RH |
9796 | { |
9797 | char *save_input_line_pointer; | |
f3c180ae | 9798 | char *gotfree_input_line; |
252b5132 | 9799 | segT exp_seg = 0; |
47926f60 | 9800 | expressionS *exp; |
40fb9820 L |
9801 | i386_operand_type types; |
9802 | ||
0dfbf9d7 | 9803 | operand_type_set (&types, ~0); |
252b5132 RH |
9804 | |
9805 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
9806 | { | |
31b2323c L |
9807 | as_bad (_("at most %d immediate operands are allowed"), |
9808 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
9809 | return 0; |
9810 | } | |
9811 | ||
9812 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 9813 | i.op[this_operand].imms = exp; |
252b5132 RH |
9814 | |
9815 | if (is_space_char (*imm_start)) | |
9816 | ++imm_start; | |
9817 | ||
9818 | save_input_line_pointer = input_line_pointer; | |
9819 | input_line_pointer = imm_start; | |
9820 | ||
d258b828 | 9821 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9822 | if (gotfree_input_line) |
9823 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
9824 | |
9825 | exp_seg = expression (exp); | |
9826 | ||
83183c0c | 9827 | SKIP_WHITESPACE (); |
43234a1e L |
9828 | |
9829 | /* Handle vector operations. */ | |
9830 | if (*input_line_pointer == '{') | |
9831 | { | |
9832 | input_line_pointer = check_VecOperations (input_line_pointer, | |
9833 | NULL); | |
9834 | if (input_line_pointer == NULL) | |
9835 | return 0; | |
9836 | } | |
9837 | ||
252b5132 | 9838 | if (*input_line_pointer) |
f3c180ae | 9839 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
9840 | |
9841 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 9842 | if (gotfree_input_line) |
ee86248c JB |
9843 | { |
9844 | free (gotfree_input_line); | |
9845 | ||
9846 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9847 | exp->X_op = O_illegal; | |
9848 | } | |
9849 | ||
9850 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
9851 | } | |
252b5132 | 9852 | |
ee86248c JB |
9853 | static int |
9854 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9855 | i386_operand_type types, const char *imm_start) | |
9856 | { | |
9857 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 9858 | { |
313c53d1 L |
9859 | if (imm_start) |
9860 | as_bad (_("missing or invalid immediate expression `%s'"), | |
9861 | imm_start); | |
3992d3b7 | 9862 | return 0; |
252b5132 | 9863 | } |
3e73aa7c | 9864 | else if (exp->X_op == O_constant) |
252b5132 | 9865 | { |
47926f60 | 9866 | /* Size it properly later. */ |
40fb9820 | 9867 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
9868 | /* If not 64bit, sign extend val. */ |
9869 | if (flag_code != CODE_64BIT | |
4eed87de AM |
9870 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
9871 | exp->X_add_number | |
9872 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 9873 | } |
4c63da97 | 9874 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 9875 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 9876 | && exp_seg != absolute_section |
47926f60 | 9877 | && exp_seg != text_section |
24eab124 AM |
9878 | && exp_seg != data_section |
9879 | && exp_seg != bss_section | |
9880 | && exp_seg != undefined_section | |
f86103b7 | 9881 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 9882 | { |
d0b47220 | 9883 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
9884 | return 0; |
9885 | } | |
9886 | #endif | |
a841bdf5 | 9887 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 9888 | { |
313c53d1 L |
9889 | if (imm_start) |
9890 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
9891 | return 0; |
9892 | } | |
252b5132 RH |
9893 | else |
9894 | { | |
9895 | /* This is an address. The size of the address will be | |
24eab124 | 9896 | determined later, depending on destination register, |
3e73aa7c | 9897 | suffix, or the default for the section. */ |
40fb9820 L |
9898 | i.types[this_operand].bitfield.imm8 = 1; |
9899 | i.types[this_operand].bitfield.imm16 = 1; | |
9900 | i.types[this_operand].bitfield.imm32 = 1; | |
9901 | i.types[this_operand].bitfield.imm32s = 1; | |
9902 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
9903 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
9904 | types); | |
252b5132 RH |
9905 | } |
9906 | ||
9907 | return 1; | |
9908 | } | |
9909 | ||
551c1ca1 | 9910 | static char * |
e3bb37b5 | 9911 | i386_scale (char *scale) |
252b5132 | 9912 | { |
551c1ca1 AM |
9913 | offsetT val; |
9914 | char *save = input_line_pointer; | |
252b5132 | 9915 | |
551c1ca1 AM |
9916 | input_line_pointer = scale; |
9917 | val = get_absolute_expression (); | |
9918 | ||
9919 | switch (val) | |
252b5132 | 9920 | { |
551c1ca1 | 9921 | case 1: |
252b5132 RH |
9922 | i.log2_scale_factor = 0; |
9923 | break; | |
551c1ca1 | 9924 | case 2: |
252b5132 RH |
9925 | i.log2_scale_factor = 1; |
9926 | break; | |
551c1ca1 | 9927 | case 4: |
252b5132 RH |
9928 | i.log2_scale_factor = 2; |
9929 | break; | |
551c1ca1 | 9930 | case 8: |
252b5132 RH |
9931 | i.log2_scale_factor = 3; |
9932 | break; | |
9933 | default: | |
a724f0f4 JB |
9934 | { |
9935 | char sep = *input_line_pointer; | |
9936 | ||
9937 | *input_line_pointer = '\0'; | |
9938 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
9939 | scale); | |
9940 | *input_line_pointer = sep; | |
9941 | input_line_pointer = save; | |
9942 | return NULL; | |
9943 | } | |
252b5132 | 9944 | } |
29b0f896 | 9945 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
9946 | { |
9947 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 9948 | 1 << i.log2_scale_factor); |
252b5132 | 9949 | i.log2_scale_factor = 0; |
252b5132 | 9950 | } |
551c1ca1 AM |
9951 | scale = input_line_pointer; |
9952 | input_line_pointer = save; | |
9953 | return scale; | |
252b5132 RH |
9954 | } |
9955 | ||
252b5132 | 9956 | static int |
e3bb37b5 | 9957 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 9958 | { |
29b0f896 | 9959 | expressionS *exp; |
252b5132 RH |
9960 | segT exp_seg = 0; |
9961 | char *save_input_line_pointer; | |
f3c180ae | 9962 | char *gotfree_input_line; |
40fb9820 L |
9963 | int override; |
9964 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 9965 | int ret; |
252b5132 | 9966 | |
31b2323c L |
9967 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
9968 | { | |
9969 | as_bad (_("at most %d displacement operands are allowed"), | |
9970 | MAX_MEMORY_OPERANDS); | |
9971 | return 0; | |
9972 | } | |
9973 | ||
0dfbf9d7 | 9974 | operand_type_set (&bigdisp, 0); |
6f2f06be | 9975 | if (i.jumpabsolute |
48bcea9f | 9976 | || i.types[this_operand].bitfield.baseindex |
0cfa3eb3 JB |
9977 | || (current_templates->start->opcode_modifier.jump != JUMP |
9978 | && current_templates->start->opcode_modifier.jump != JUMP_DWORD)) | |
e05278af | 9979 | { |
48bcea9f | 9980 | i386_addressing_mode (); |
e05278af | 9981 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
9982 | if (flag_code == CODE_64BIT) |
9983 | { | |
9984 | if (!override) | |
9985 | { | |
9986 | bigdisp.bitfield.disp32s = 1; | |
9987 | bigdisp.bitfield.disp64 = 1; | |
9988 | } | |
48bcea9f JB |
9989 | else |
9990 | bigdisp.bitfield.disp32 = 1; | |
40fb9820 L |
9991 | } |
9992 | else if ((flag_code == CODE_16BIT) ^ override) | |
40fb9820 | 9993 | bigdisp.bitfield.disp16 = 1; |
48bcea9f JB |
9994 | else |
9995 | bigdisp.bitfield.disp32 = 1; | |
e05278af JB |
9996 | } |
9997 | else | |
9998 | { | |
376cd056 JB |
9999 | /* For PC-relative branches, the width of the displacement may be |
10000 | dependent upon data size, but is never dependent upon address size. | |
10001 | Also make sure to not unintentionally match against a non-PC-relative | |
10002 | branch template. */ | |
10003 | static templates aux_templates; | |
10004 | const insn_template *t = current_templates->start; | |
10005 | bfd_boolean has_intel64 = FALSE; | |
10006 | ||
10007 | aux_templates.start = t; | |
10008 | while (++t < current_templates->end) | |
10009 | { | |
10010 | if (t->opcode_modifier.jump | |
10011 | != current_templates->start->opcode_modifier.jump) | |
10012 | break; | |
4b5aaf5f | 10013 | if ((t->opcode_modifier.isa64 >= INTEL64)) |
376cd056 JB |
10014 | has_intel64 = TRUE; |
10015 | } | |
10016 | if (t < current_templates->end) | |
10017 | { | |
10018 | aux_templates.end = t; | |
10019 | current_templates = &aux_templates; | |
10020 | } | |
10021 | ||
e05278af | 10022 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
10023 | if (flag_code == CODE_64BIT) |
10024 | { | |
376cd056 JB |
10025 | if ((override || i.suffix == WORD_MNEM_SUFFIX) |
10026 | && (!intel64 || !has_intel64)) | |
40fb9820 L |
10027 | bigdisp.bitfield.disp16 = 1; |
10028 | else | |
48bcea9f | 10029 | bigdisp.bitfield.disp32s = 1; |
40fb9820 L |
10030 | } |
10031 | else | |
e05278af JB |
10032 | { |
10033 | if (!override) | |
10034 | override = (i.suffix == (flag_code != CODE_16BIT | |
10035 | ? WORD_MNEM_SUFFIX | |
10036 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
10037 | bigdisp.bitfield.disp32 = 1; |
10038 | if ((flag_code == CODE_16BIT) ^ override) | |
10039 | { | |
10040 | bigdisp.bitfield.disp32 = 0; | |
10041 | bigdisp.bitfield.disp16 = 1; | |
10042 | } | |
e05278af | 10043 | } |
e05278af | 10044 | } |
c6fb90c8 L |
10045 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10046 | bigdisp); | |
252b5132 RH |
10047 | |
10048 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 10049 | i.op[this_operand].disps = exp; |
252b5132 RH |
10050 | i.disp_operands++; |
10051 | save_input_line_pointer = input_line_pointer; | |
10052 | input_line_pointer = disp_start; | |
10053 | END_STRING_AND_SAVE (disp_end); | |
10054 | ||
10055 | #ifndef GCC_ASM_O_HACK | |
10056 | #define GCC_ASM_O_HACK 0 | |
10057 | #endif | |
10058 | #if GCC_ASM_O_HACK | |
10059 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 10060 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 10061 | && displacement_string_end[-1] == '+') |
252b5132 RH |
10062 | { |
10063 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
10064 | constraint within gcc asm statements. |
10065 | For instance: | |
10066 | ||
10067 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
10068 | __asm__ __volatile__ ( \ | |
10069 | "movw %w2,%0\n\t" \ | |
10070 | "movw %w1,2+%0\n\t" \ | |
10071 | "rorl $16,%1\n\t" \ | |
10072 | "movb %b1,4+%0\n\t" \ | |
10073 | "movb %4,5+%0\n\t" \ | |
10074 | "movb $0,6+%0\n\t" \ | |
10075 | "movb %h1,7+%0\n\t" \ | |
10076 | "rorl $16,%1" \ | |
10077 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
10078 | ||
10079 | This works great except that the output assembler ends | |
10080 | up looking a bit weird if it turns out that there is | |
10081 | no offset. You end up producing code that looks like: | |
10082 | ||
10083 | #APP | |
10084 | movw $235,(%eax) | |
10085 | movw %dx,2+(%eax) | |
10086 | rorl $16,%edx | |
10087 | movb %dl,4+(%eax) | |
10088 | movb $137,5+(%eax) | |
10089 | movb $0,6+(%eax) | |
10090 | movb %dh,7+(%eax) | |
10091 | rorl $16,%edx | |
10092 | #NO_APP | |
10093 | ||
47926f60 | 10094 | So here we provide the missing zero. */ |
24eab124 AM |
10095 | |
10096 | *displacement_string_end = '0'; | |
252b5132 RH |
10097 | } |
10098 | #endif | |
d258b828 | 10099 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
10100 | if (gotfree_input_line) |
10101 | input_line_pointer = gotfree_input_line; | |
252b5132 | 10102 | |
24eab124 | 10103 | exp_seg = expression (exp); |
252b5132 | 10104 | |
636c26b0 AM |
10105 | SKIP_WHITESPACE (); |
10106 | if (*input_line_pointer) | |
10107 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
10108 | #if GCC_ASM_O_HACK | |
10109 | RESTORE_END_STRING (disp_end + 1); | |
10110 | #endif | |
636c26b0 | 10111 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 10112 | if (gotfree_input_line) |
ee86248c JB |
10113 | { |
10114 | free (gotfree_input_line); | |
10115 | ||
10116 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
10117 | exp->X_op = O_illegal; | |
10118 | } | |
10119 | ||
10120 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
10121 | ||
10122 | RESTORE_END_STRING (disp_end); | |
10123 | ||
10124 | return ret; | |
10125 | } | |
10126 | ||
10127 | static int | |
10128 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
10129 | i386_operand_type types, const char *disp_start) | |
10130 | { | |
10131 | i386_operand_type bigdisp; | |
10132 | int ret = 1; | |
636c26b0 | 10133 | |
24eab124 AM |
10134 | /* We do this to make sure that the section symbol is in |
10135 | the symbol table. We will ultimately change the relocation | |
47926f60 | 10136 | to be relative to the beginning of the section. */ |
1ae12ab7 | 10137 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
10138 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
10139 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 10140 | { |
636c26b0 | 10141 | if (exp->X_op != O_symbol) |
3992d3b7 | 10142 | goto inv_disp; |
636c26b0 | 10143 | |
e5cb08ac | 10144 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
10145 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
10146 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 10147 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
10148 | exp->X_op = O_subtract; |
10149 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 10150 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 10151 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
10152 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
10153 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 10154 | else |
29b0f896 | 10155 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 10156 | } |
252b5132 | 10157 | |
3992d3b7 AM |
10158 | else if (exp->X_op == O_absent |
10159 | || exp->X_op == O_illegal | |
ee86248c | 10160 | || exp->X_op == O_big) |
2daf4fd8 | 10161 | { |
3992d3b7 AM |
10162 | inv_disp: |
10163 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 10164 | disp_start); |
3992d3b7 | 10165 | ret = 0; |
2daf4fd8 AM |
10166 | } |
10167 | ||
0e1147d9 L |
10168 | else if (flag_code == CODE_64BIT |
10169 | && !i.prefix[ADDR_PREFIX] | |
10170 | && exp->X_op == O_constant) | |
10171 | { | |
10172 | /* Since displacement is signed extended to 64bit, don't allow | |
10173 | disp32 and turn off disp32s if they are out of range. */ | |
10174 | i.types[this_operand].bitfield.disp32 = 0; | |
10175 | if (!fits_in_signed_long (exp->X_add_number)) | |
10176 | { | |
10177 | i.types[this_operand].bitfield.disp32s = 0; | |
10178 | if (i.types[this_operand].bitfield.baseindex) | |
10179 | { | |
10180 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
10181 | (long) exp->X_add_number); | |
10182 | ret = 0; | |
10183 | } | |
10184 | } | |
10185 | } | |
10186 | ||
4c63da97 | 10187 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
10188 | else if (exp->X_op != O_constant |
10189 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
10190 | && exp_seg != absolute_section | |
10191 | && exp_seg != text_section | |
10192 | && exp_seg != data_section | |
10193 | && exp_seg != bss_section | |
10194 | && exp_seg != undefined_section | |
10195 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 10196 | { |
d0b47220 | 10197 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 10198 | ret = 0; |
24eab124 | 10199 | } |
252b5132 | 10200 | #endif |
3956db08 | 10201 | |
48bcea9f JB |
10202 | if (current_templates->start->opcode_modifier.jump == JUMP_BYTE |
10203 | /* Constants get taken care of by optimize_disp(). */ | |
10204 | && exp->X_op != O_constant) | |
10205 | i.types[this_operand].bitfield.disp8 = 1; | |
10206 | ||
40fb9820 L |
10207 | /* Check if this is a displacement only operand. */ |
10208 | bigdisp = i.types[this_operand]; | |
10209 | bigdisp.bitfield.disp8 = 0; | |
10210 | bigdisp.bitfield.disp16 = 0; | |
10211 | bigdisp.bitfield.disp32 = 0; | |
10212 | bigdisp.bitfield.disp32s = 0; | |
10213 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 10214 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
10215 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
10216 | types); | |
3956db08 | 10217 | |
3992d3b7 | 10218 | return ret; |
252b5132 RH |
10219 | } |
10220 | ||
2abc2bec JB |
10221 | /* Return the active addressing mode, taking address override and |
10222 | registers forming the address into consideration. Update the | |
10223 | address override prefix if necessary. */ | |
47926f60 | 10224 | |
2abc2bec JB |
10225 | static enum flag_code |
10226 | i386_addressing_mode (void) | |
252b5132 | 10227 | { |
be05d201 L |
10228 | enum flag_code addr_mode; |
10229 | ||
10230 | if (i.prefix[ADDR_PREFIX]) | |
10231 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
10232 | else | |
10233 | { | |
10234 | addr_mode = flag_code; | |
10235 | ||
24eab124 | 10236 | #if INFER_ADDR_PREFIX |
be05d201 L |
10237 | if (i.mem_operands == 0) |
10238 | { | |
10239 | /* Infer address prefix from the first memory operand. */ | |
10240 | const reg_entry *addr_reg = i.base_reg; | |
10241 | ||
10242 | if (addr_reg == NULL) | |
10243 | addr_reg = i.index_reg; | |
eecb386c | 10244 | |
be05d201 L |
10245 | if (addr_reg) |
10246 | { | |
e968fc9b | 10247 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
10248 | addr_mode = CODE_32BIT; |
10249 | else if (flag_code != CODE_64BIT | |
dc821c5f | 10250 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
10251 | addr_mode = CODE_16BIT; |
10252 | ||
10253 | if (addr_mode != flag_code) | |
10254 | { | |
10255 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
10256 | i.prefixes += 1; | |
10257 | /* Change the size of any displacement too. At most one | |
10258 | of Disp16 or Disp32 is set. | |
10259 | FIXME. There doesn't seem to be any real need for | |
10260 | separate Disp16 and Disp32 flags. The same goes for | |
10261 | Imm16 and Imm32. Removing them would probably clean | |
10262 | up the code quite a lot. */ | |
10263 | if (flag_code != CODE_64BIT | |
10264 | && (i.types[this_operand].bitfield.disp16 | |
10265 | || i.types[this_operand].bitfield.disp32)) | |
10266 | i.types[this_operand] | |
10267 | = operand_type_xor (i.types[this_operand], disp16_32); | |
10268 | } | |
10269 | } | |
10270 | } | |
24eab124 | 10271 | #endif |
be05d201 L |
10272 | } |
10273 | ||
2abc2bec JB |
10274 | return addr_mode; |
10275 | } | |
10276 | ||
10277 | /* Make sure the memory operand we've been dealt is valid. | |
10278 | Return 1 on success, 0 on a failure. */ | |
10279 | ||
10280 | static int | |
10281 | i386_index_check (const char *operand_string) | |
10282 | { | |
10283 | const char *kind = "base/index"; | |
10284 | enum flag_code addr_mode = i386_addressing_mode (); | |
10285 | ||
fc0763e6 | 10286 | if (current_templates->start->opcode_modifier.isstring |
c3949f43 | 10287 | && !current_templates->start->cpu_flags.bitfield.cpupadlock |
fc0763e6 JB |
10288 | && (current_templates->end[-1].opcode_modifier.isstring |
10289 | || i.mem_operands)) | |
10290 | { | |
10291 | /* Memory operands of string insns are special in that they only allow | |
10292 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
10293 | const reg_entry *expected_reg; |
10294 | static const char *di_si[][2] = | |
10295 | { | |
10296 | { "esi", "edi" }, | |
10297 | { "si", "di" }, | |
10298 | { "rsi", "rdi" } | |
10299 | }; | |
10300 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
10301 | |
10302 | kind = "string address"; | |
10303 | ||
8325cc63 | 10304 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 | 10305 | { |
51c8edf6 JB |
10306 | int es_op = current_templates->end[-1].opcode_modifier.isstring |
10307 | - IS_STRING_ES_OP0; | |
10308 | int op = 0; | |
fc0763e6 | 10309 | |
51c8edf6 | 10310 | if (!current_templates->end[-1].operand_types[0].bitfield.baseindex |
fc0763e6 JB |
10311 | || ((!i.mem_operands != !intel_syntax) |
10312 | && current_templates->end[-1].operand_types[1] | |
10313 | .bitfield.baseindex)) | |
51c8edf6 JB |
10314 | op = 1; |
10315 | expected_reg = hash_find (reg_hash, di_si[addr_mode][op == es_op]); | |
fc0763e6 JB |
10316 | } |
10317 | else | |
be05d201 | 10318 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 10319 | |
be05d201 L |
10320 | if (i.base_reg != expected_reg |
10321 | || i.index_reg | |
fc0763e6 | 10322 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 10323 | { |
be05d201 L |
10324 | /* The second memory operand must have the same size as |
10325 | the first one. */ | |
10326 | if (i.mem_operands | |
10327 | && i.base_reg | |
10328 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 10329 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 10330 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
10331 | ? i.base_reg->reg_type.bitfield.dword |
10332 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
10333 | goto bad_address; |
10334 | ||
fc0763e6 JB |
10335 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
10336 | operand_string, | |
10337 | intel_syntax ? '[' : '(', | |
10338 | register_prefix, | |
be05d201 | 10339 | expected_reg->reg_name, |
fc0763e6 | 10340 | intel_syntax ? ']' : ')'); |
be05d201 | 10341 | return 1; |
fc0763e6 | 10342 | } |
be05d201 L |
10343 | else |
10344 | return 1; | |
10345 | ||
10346 | bad_address: | |
10347 | as_bad (_("`%s' is not a valid %s expression"), | |
10348 | operand_string, kind); | |
10349 | return 0; | |
3e73aa7c JH |
10350 | } |
10351 | else | |
10352 | { | |
be05d201 L |
10353 | if (addr_mode != CODE_16BIT) |
10354 | { | |
10355 | /* 32-bit/64-bit checks. */ | |
10356 | if ((i.base_reg | |
e968fc9b JB |
10357 | && ((addr_mode == CODE_64BIT |
10358 | ? !i.base_reg->reg_type.bitfield.qword | |
10359 | : !i.base_reg->reg_type.bitfield.dword) | |
10360 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
10361 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 10362 | || (i.index_reg |
1b54b8d7 JB |
10363 | && !i.index_reg->reg_type.bitfield.xmmword |
10364 | && !i.index_reg->reg_type.bitfield.ymmword | |
10365 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 10366 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
10367 | ? !i.index_reg->reg_type.bitfield.qword |
10368 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
10369 | || !i.index_reg->reg_type.bitfield.baseindex))) |
10370 | goto bad_address; | |
8178be5b JB |
10371 | |
10372 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
10373 | if (current_templates->start->base_opcode == 0xf30f1b | |
10374 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
10375 | { | |
10376 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 10377 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
10378 | { |
10379 | as_bad (_("`%s' cannot be used here"), operand_string); | |
10380 | return 0; | |
10381 | } | |
10382 | ||
10383 | /* bndldx and bndstx ignore their scale factor. */ | |
10384 | if (current_templates->start->base_opcode != 0xf30f1b | |
10385 | && i.log2_scale_factor) | |
10386 | as_warn (_("register scaling is being ignored here")); | |
10387 | } | |
be05d201 L |
10388 | } |
10389 | else | |
3e73aa7c | 10390 | { |
be05d201 | 10391 | /* 16-bit checks. */ |
3e73aa7c | 10392 | if ((i.base_reg |
dc821c5f | 10393 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 10394 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 10395 | || (i.index_reg |
dc821c5f | 10396 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 10397 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
10398 | || !(i.base_reg |
10399 | && i.base_reg->reg_num < 6 | |
10400 | && i.index_reg->reg_num >= 6 | |
10401 | && i.log2_scale_factor == 0)))) | |
be05d201 | 10402 | goto bad_address; |
3e73aa7c JH |
10403 | } |
10404 | } | |
be05d201 | 10405 | return 1; |
24eab124 | 10406 | } |
252b5132 | 10407 | |
43234a1e L |
10408 | /* Handle vector immediates. */ |
10409 | ||
10410 | static int | |
10411 | RC_SAE_immediate (const char *imm_start) | |
10412 | { | |
10413 | unsigned int match_found, j; | |
10414 | const char *pstr = imm_start; | |
10415 | expressionS *exp; | |
10416 | ||
10417 | if (*pstr != '{') | |
10418 | return 0; | |
10419 | ||
10420 | pstr++; | |
10421 | match_found = 0; | |
10422 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
10423 | { | |
10424 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
10425 | { | |
10426 | if (!i.rounding) | |
10427 | { | |
10428 | rc_op.type = RC_NamesTable[j].type; | |
10429 | rc_op.operand = this_operand; | |
10430 | i.rounding = &rc_op; | |
10431 | } | |
10432 | else | |
10433 | { | |
10434 | as_bad (_("duplicated `%s'"), imm_start); | |
10435 | return 0; | |
10436 | } | |
10437 | pstr += RC_NamesTable[j].len; | |
10438 | match_found = 1; | |
10439 | break; | |
10440 | } | |
10441 | } | |
10442 | if (!match_found) | |
10443 | return 0; | |
10444 | ||
10445 | if (*pstr++ != '}') | |
10446 | { | |
10447 | as_bad (_("Missing '}': '%s'"), imm_start); | |
10448 | return 0; | |
10449 | } | |
10450 | /* RC/SAE immediate string should contain nothing more. */; | |
10451 | if (*pstr != 0) | |
10452 | { | |
10453 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
10454 | return 0; | |
10455 | } | |
10456 | ||
10457 | exp = &im_expressions[i.imm_operands++]; | |
10458 | i.op[this_operand].imms = exp; | |
10459 | ||
10460 | exp->X_op = O_constant; | |
10461 | exp->X_add_number = 0; | |
10462 | exp->X_add_symbol = (symbolS *) 0; | |
10463 | exp->X_op_symbol = (symbolS *) 0; | |
10464 | ||
10465 | i.types[this_operand].bitfield.imm8 = 1; | |
10466 | return 1; | |
10467 | } | |
10468 | ||
8325cc63 JB |
10469 | /* Only string instructions can have a second memory operand, so |
10470 | reduce current_templates to just those if it contains any. */ | |
10471 | static int | |
10472 | maybe_adjust_templates (void) | |
10473 | { | |
10474 | const insn_template *t; | |
10475 | ||
10476 | gas_assert (i.mem_operands == 1); | |
10477 | ||
10478 | for (t = current_templates->start; t < current_templates->end; ++t) | |
10479 | if (t->opcode_modifier.isstring) | |
10480 | break; | |
10481 | ||
10482 | if (t < current_templates->end) | |
10483 | { | |
10484 | static templates aux_templates; | |
10485 | bfd_boolean recheck; | |
10486 | ||
10487 | aux_templates.start = t; | |
10488 | for (; t < current_templates->end; ++t) | |
10489 | if (!t->opcode_modifier.isstring) | |
10490 | break; | |
10491 | aux_templates.end = t; | |
10492 | ||
10493 | /* Determine whether to re-check the first memory operand. */ | |
10494 | recheck = (aux_templates.start != current_templates->start | |
10495 | || t != current_templates->end); | |
10496 | ||
10497 | current_templates = &aux_templates; | |
10498 | ||
10499 | if (recheck) | |
10500 | { | |
10501 | i.mem_operands = 0; | |
10502 | if (i.memop1_string != NULL | |
10503 | && i386_index_check (i.memop1_string) == 0) | |
10504 | return 0; | |
10505 | i.mem_operands = 1; | |
10506 | } | |
10507 | } | |
10508 | ||
10509 | return 1; | |
10510 | } | |
10511 | ||
fc0763e6 | 10512 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 10513 | on error. */ |
252b5132 | 10514 | |
252b5132 | 10515 | static int |
a7619375 | 10516 | i386_att_operand (char *operand_string) |
252b5132 | 10517 | { |
af6bdddf AM |
10518 | const reg_entry *r; |
10519 | char *end_op; | |
24eab124 | 10520 | char *op_string = operand_string; |
252b5132 | 10521 | |
24eab124 | 10522 | if (is_space_char (*op_string)) |
252b5132 RH |
10523 | ++op_string; |
10524 | ||
24eab124 | 10525 | /* We check for an absolute prefix (differentiating, |
47926f60 | 10526 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
10527 | if (*op_string == ABSOLUTE_PREFIX) |
10528 | { | |
10529 | ++op_string; | |
10530 | if (is_space_char (*op_string)) | |
10531 | ++op_string; | |
6f2f06be | 10532 | i.jumpabsolute = TRUE; |
24eab124 | 10533 | } |
252b5132 | 10534 | |
47926f60 | 10535 | /* Check if operand is a register. */ |
4d1bb795 | 10536 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 10537 | { |
40fb9820 L |
10538 | i386_operand_type temp; |
10539 | ||
24eab124 AM |
10540 | /* Check for a segment override by searching for ':' after a |
10541 | segment register. */ | |
10542 | op_string = end_op; | |
10543 | if (is_space_char (*op_string)) | |
10544 | ++op_string; | |
00cee14f | 10545 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
24eab124 AM |
10546 | { |
10547 | switch (r->reg_num) | |
10548 | { | |
10549 | case 0: | |
10550 | i.seg[i.mem_operands] = &es; | |
10551 | break; | |
10552 | case 1: | |
10553 | i.seg[i.mem_operands] = &cs; | |
10554 | break; | |
10555 | case 2: | |
10556 | i.seg[i.mem_operands] = &ss; | |
10557 | break; | |
10558 | case 3: | |
10559 | i.seg[i.mem_operands] = &ds; | |
10560 | break; | |
10561 | case 4: | |
10562 | i.seg[i.mem_operands] = &fs; | |
10563 | break; | |
10564 | case 5: | |
10565 | i.seg[i.mem_operands] = &gs; | |
10566 | break; | |
10567 | } | |
252b5132 | 10568 | |
24eab124 | 10569 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
10570 | ++op_string; |
10571 | if (is_space_char (*op_string)) | |
24eab124 | 10572 | ++op_string; |
252b5132 | 10573 | |
24eab124 AM |
10574 | if (!is_digit_char (*op_string) |
10575 | && !is_identifier_char (*op_string) | |
10576 | && *op_string != '(' | |
10577 | && *op_string != ABSOLUTE_PREFIX) | |
10578 | { | |
10579 | as_bad (_("bad memory operand `%s'"), op_string); | |
10580 | return 0; | |
10581 | } | |
47926f60 | 10582 | /* Handle case of %es:*foo. */ |
24eab124 AM |
10583 | if (*op_string == ABSOLUTE_PREFIX) |
10584 | { | |
10585 | ++op_string; | |
10586 | if (is_space_char (*op_string)) | |
10587 | ++op_string; | |
6f2f06be | 10588 | i.jumpabsolute = TRUE; |
24eab124 AM |
10589 | } |
10590 | goto do_memory_reference; | |
10591 | } | |
43234a1e L |
10592 | |
10593 | /* Handle vector operations. */ | |
10594 | if (*op_string == '{') | |
10595 | { | |
10596 | op_string = check_VecOperations (op_string, NULL); | |
10597 | if (op_string == NULL) | |
10598 | return 0; | |
10599 | } | |
10600 | ||
24eab124 AM |
10601 | if (*op_string) |
10602 | { | |
d0b47220 | 10603 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
10604 | return 0; |
10605 | } | |
40fb9820 L |
10606 | temp = r->reg_type; |
10607 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
10608 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10609 | temp); | |
7d5e4556 | 10610 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 10611 | i.op[this_operand].regs = r; |
24eab124 AM |
10612 | i.reg_operands++; |
10613 | } | |
af6bdddf AM |
10614 | else if (*op_string == REGISTER_PREFIX) |
10615 | { | |
10616 | as_bad (_("bad register name `%s'"), op_string); | |
10617 | return 0; | |
10618 | } | |
24eab124 | 10619 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 10620 | { |
24eab124 | 10621 | ++op_string; |
6f2f06be | 10622 | if (i.jumpabsolute) |
24eab124 | 10623 | { |
d0b47220 | 10624 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
10625 | return 0; |
10626 | } | |
10627 | if (!i386_immediate (op_string)) | |
10628 | return 0; | |
10629 | } | |
43234a1e L |
10630 | else if (RC_SAE_immediate (operand_string)) |
10631 | { | |
10632 | /* If it is a RC or SAE immediate, do nothing. */ | |
10633 | ; | |
10634 | } | |
24eab124 AM |
10635 | else if (is_digit_char (*op_string) |
10636 | || is_identifier_char (*op_string) | |
d02603dc | 10637 | || *op_string == '"' |
e5cb08ac | 10638 | || *op_string == '(') |
24eab124 | 10639 | { |
47926f60 | 10640 | /* This is a memory reference of some sort. */ |
af6bdddf | 10641 | char *base_string; |
252b5132 | 10642 | |
47926f60 | 10643 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
10644 | char *displacement_string_start; |
10645 | char *displacement_string_end; | |
43234a1e | 10646 | char *vop_start; |
252b5132 | 10647 | |
24eab124 | 10648 | do_memory_reference: |
8325cc63 JB |
10649 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
10650 | return 0; | |
24eab124 | 10651 | if ((i.mem_operands == 1 |
40fb9820 | 10652 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
10653 | || i.mem_operands == 2) |
10654 | { | |
10655 | as_bad (_("too many memory references for `%s'"), | |
10656 | current_templates->start->name); | |
10657 | return 0; | |
10658 | } | |
252b5132 | 10659 | |
24eab124 AM |
10660 | /* Check for base index form. We detect the base index form by |
10661 | looking for an ')' at the end of the operand, searching | |
10662 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
10663 | after the '('. */ | |
af6bdddf | 10664 | base_string = op_string + strlen (op_string); |
c3332e24 | 10665 | |
43234a1e L |
10666 | /* Handle vector operations. */ |
10667 | vop_start = strchr (op_string, '{'); | |
10668 | if (vop_start && vop_start < base_string) | |
10669 | { | |
10670 | if (check_VecOperations (vop_start, base_string) == NULL) | |
10671 | return 0; | |
10672 | base_string = vop_start; | |
10673 | } | |
10674 | ||
af6bdddf AM |
10675 | --base_string; |
10676 | if (is_space_char (*base_string)) | |
10677 | --base_string; | |
252b5132 | 10678 | |
47926f60 | 10679 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
10680 | displacement_string_start = op_string; |
10681 | displacement_string_end = base_string + 1; | |
252b5132 | 10682 | |
24eab124 AM |
10683 | if (*base_string == ')') |
10684 | { | |
af6bdddf | 10685 | char *temp_string; |
24eab124 AM |
10686 | unsigned int parens_balanced = 1; |
10687 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 10688 | equal, so this loop will not be infinite. */ |
24eab124 AM |
10689 | do |
10690 | { | |
10691 | base_string--; | |
10692 | if (*base_string == ')') | |
10693 | parens_balanced++; | |
10694 | if (*base_string == '(') | |
10695 | parens_balanced--; | |
10696 | } | |
10697 | while (parens_balanced); | |
c3332e24 | 10698 | |
af6bdddf | 10699 | temp_string = base_string; |
c3332e24 | 10700 | |
24eab124 | 10701 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
10702 | ++base_string; |
10703 | if (is_space_char (*base_string)) | |
24eab124 | 10704 | ++base_string; |
252b5132 | 10705 | |
af6bdddf | 10706 | if (*base_string == ',' |
4eed87de AM |
10707 | || ((i.base_reg = parse_register (base_string, &end_op)) |
10708 | != NULL)) | |
252b5132 | 10709 | { |
af6bdddf | 10710 | displacement_string_end = temp_string; |
252b5132 | 10711 | |
40fb9820 | 10712 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 10713 | |
af6bdddf | 10714 | if (i.base_reg) |
24eab124 | 10715 | { |
24eab124 AM |
10716 | base_string = end_op; |
10717 | if (is_space_char (*base_string)) | |
10718 | ++base_string; | |
af6bdddf AM |
10719 | } |
10720 | ||
10721 | /* There may be an index reg or scale factor here. */ | |
10722 | if (*base_string == ',') | |
10723 | { | |
10724 | ++base_string; | |
10725 | if (is_space_char (*base_string)) | |
10726 | ++base_string; | |
10727 | ||
4eed87de AM |
10728 | if ((i.index_reg = parse_register (base_string, &end_op)) |
10729 | != NULL) | |
24eab124 | 10730 | { |
af6bdddf | 10731 | base_string = end_op; |
24eab124 AM |
10732 | if (is_space_char (*base_string)) |
10733 | ++base_string; | |
af6bdddf AM |
10734 | if (*base_string == ',') |
10735 | { | |
10736 | ++base_string; | |
10737 | if (is_space_char (*base_string)) | |
10738 | ++base_string; | |
10739 | } | |
e5cb08ac | 10740 | else if (*base_string != ')') |
af6bdddf | 10741 | { |
4eed87de AM |
10742 | as_bad (_("expecting `,' or `)' " |
10743 | "after index register in `%s'"), | |
af6bdddf AM |
10744 | operand_string); |
10745 | return 0; | |
10746 | } | |
24eab124 | 10747 | } |
af6bdddf | 10748 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 10749 | { |
f76bf5e0 L |
10750 | end_op = strchr (base_string, ','); |
10751 | if (end_op) | |
10752 | *end_op = '\0'; | |
af6bdddf | 10753 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
10754 | return 0; |
10755 | } | |
252b5132 | 10756 | |
47926f60 | 10757 | /* Check for scale factor. */ |
551c1ca1 | 10758 | if (*base_string != ')') |
af6bdddf | 10759 | { |
551c1ca1 AM |
10760 | char *end_scale = i386_scale (base_string); |
10761 | ||
10762 | if (!end_scale) | |
af6bdddf | 10763 | return 0; |
24eab124 | 10764 | |
551c1ca1 | 10765 | base_string = end_scale; |
af6bdddf AM |
10766 | if (is_space_char (*base_string)) |
10767 | ++base_string; | |
10768 | if (*base_string != ')') | |
10769 | { | |
4eed87de AM |
10770 | as_bad (_("expecting `)' " |
10771 | "after scale factor in `%s'"), | |
af6bdddf AM |
10772 | operand_string); |
10773 | return 0; | |
10774 | } | |
10775 | } | |
10776 | else if (!i.index_reg) | |
24eab124 | 10777 | { |
4eed87de AM |
10778 | as_bad (_("expecting index register or scale factor " |
10779 | "after `,'; got '%c'"), | |
af6bdddf | 10780 | *base_string); |
24eab124 AM |
10781 | return 0; |
10782 | } | |
10783 | } | |
af6bdddf | 10784 | else if (*base_string != ')') |
24eab124 | 10785 | { |
4eed87de AM |
10786 | as_bad (_("expecting `,' or `)' " |
10787 | "after base register in `%s'"), | |
af6bdddf | 10788 | operand_string); |
24eab124 AM |
10789 | return 0; |
10790 | } | |
c3332e24 | 10791 | } |
af6bdddf | 10792 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 10793 | { |
f76bf5e0 L |
10794 | end_op = strchr (base_string, ','); |
10795 | if (end_op) | |
10796 | *end_op = '\0'; | |
af6bdddf | 10797 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 10798 | return 0; |
c3332e24 | 10799 | } |
24eab124 AM |
10800 | } |
10801 | ||
10802 | /* If there's an expression beginning the operand, parse it, | |
10803 | assuming displacement_string_start and | |
10804 | displacement_string_end are meaningful. */ | |
10805 | if (displacement_string_start != displacement_string_end) | |
10806 | { | |
10807 | if (!i386_displacement (displacement_string_start, | |
10808 | displacement_string_end)) | |
10809 | return 0; | |
10810 | } | |
10811 | ||
10812 | /* Special case for (%dx) while doing input/output op. */ | |
10813 | if (i.base_reg | |
75e5731b JB |
10814 | && i.base_reg->reg_type.bitfield.instance == RegD |
10815 | && i.base_reg->reg_type.bitfield.word | |
24eab124 AM |
10816 | && i.index_reg == 0 |
10817 | && i.log2_scale_factor == 0 | |
10818 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 10819 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 10820 | { |
2fb5be8d | 10821 | i.types[this_operand] = i.base_reg->reg_type; |
24eab124 AM |
10822 | return 1; |
10823 | } | |
10824 | ||
eecb386c AM |
10825 | if (i386_index_check (operand_string) == 0) |
10826 | return 0; | |
c48dadc9 | 10827 | i.flags[this_operand] |= Operand_Mem; |
8325cc63 JB |
10828 | if (i.mem_operands == 0) |
10829 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
10830 | i.mem_operands++; |
10831 | } | |
10832 | else | |
ce8a8b2f AM |
10833 | { |
10834 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
10835 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
10836 | output_invalid (*op_string), | |
10837 | this_operand + 1, | |
10838 | op_string); | |
10839 | return 0; | |
10840 | } | |
47926f60 | 10841 | return 1; /* Normal return. */ |
252b5132 RH |
10842 | } |
10843 | \f | |
fa94de6b RM |
10844 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
10845 | that an rs_machine_dependent frag may reach. */ | |
10846 | ||
10847 | unsigned int | |
10848 | i386_frag_max_var (fragS *frag) | |
10849 | { | |
10850 | /* The only relaxable frags are for jumps. | |
10851 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
10852 | gas_assert (frag->fr_type == rs_machine_dependent); | |
10853 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
10854 | } | |
10855 | ||
b084df0b L |
10856 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10857 | static int | |
8dcea932 | 10858 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
10859 | { |
10860 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
10861 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
10862 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
10863 | return 0; | |
10864 | ||
10865 | if (!S_IS_EXTERNAL (fr_symbol)) | |
10866 | /* Symbol may be weak or local. */ | |
10867 | return !S_IS_WEAK (fr_symbol); | |
10868 | ||
8dcea932 L |
10869 | /* Global symbols with non-default visibility can't be preempted. */ |
10870 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
10871 | return 1; | |
10872 | ||
10873 | if (fr_var != NO_RELOC) | |
10874 | switch ((enum bfd_reloc_code_real) fr_var) | |
10875 | { | |
10876 | case BFD_RELOC_386_PLT32: | |
10877 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 10878 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
10879 | return 0; |
10880 | default: | |
10881 | abort (); | |
10882 | } | |
10883 | ||
b084df0b L |
10884 | /* Global symbols with default visibility in a shared library may be |
10885 | preempted by another definition. */ | |
8dcea932 | 10886 | return !shared; |
b084df0b L |
10887 | } |
10888 | #endif | |
10889 | ||
e379e5f3 L |
10890 | /* Return the next non-empty frag. */ |
10891 | ||
10892 | static fragS * | |
10893 | i386_next_non_empty_frag (fragS *fragP) | |
10894 | { | |
10895 | /* There may be a frag with a ".fill 0" when there is no room in | |
10896 | the current frag for frag_grow in output_insn. */ | |
10897 | for (fragP = fragP->fr_next; | |
10898 | (fragP != NULL | |
10899 | && fragP->fr_type == rs_fill | |
10900 | && fragP->fr_fix == 0); | |
10901 | fragP = fragP->fr_next) | |
10902 | ; | |
10903 | return fragP; | |
10904 | } | |
10905 | ||
10906 | /* Return the next jcc frag after BRANCH_PADDING. */ | |
10907 | ||
10908 | static fragS * | |
10909 | i386_next_jcc_frag (fragS *fragP) | |
10910 | { | |
10911 | if (!fragP) | |
10912 | return NULL; | |
10913 | ||
10914 | if (fragP->fr_type == rs_machine_dependent | |
10915 | && (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
10916 | == BRANCH_PADDING)) | |
10917 | { | |
10918 | fragP = i386_next_non_empty_frag (fragP); | |
10919 | if (fragP->fr_type != rs_machine_dependent) | |
10920 | return NULL; | |
10921 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == COND_JUMP) | |
10922 | return fragP; | |
10923 | } | |
10924 | ||
10925 | return NULL; | |
10926 | } | |
10927 | ||
10928 | /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */ | |
10929 | ||
10930 | static void | |
10931 | i386_classify_machine_dependent_frag (fragS *fragP) | |
10932 | { | |
10933 | fragS *cmp_fragP; | |
10934 | fragS *pad_fragP; | |
10935 | fragS *branch_fragP; | |
10936 | fragS *next_fragP; | |
10937 | unsigned int max_prefix_length; | |
10938 | ||
10939 | if (fragP->tc_frag_data.classified) | |
10940 | return; | |
10941 | ||
10942 | /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert | |
10943 | FUSED_JCC_PADDING and merge BRANCH_PADDING. */ | |
10944 | for (next_fragP = fragP; | |
10945 | next_fragP != NULL; | |
10946 | next_fragP = next_fragP->fr_next) | |
10947 | { | |
10948 | next_fragP->tc_frag_data.classified = 1; | |
10949 | if (next_fragP->fr_type == rs_machine_dependent) | |
10950 | switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)) | |
10951 | { | |
10952 | case BRANCH_PADDING: | |
10953 | /* The BRANCH_PADDING frag must be followed by a branch | |
10954 | frag. */ | |
10955 | branch_fragP = i386_next_non_empty_frag (next_fragP); | |
10956 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
10957 | break; | |
10958 | case FUSED_JCC_PADDING: | |
10959 | /* Check if this is a fused jcc: | |
10960 | FUSED_JCC_PADDING | |
10961 | CMP like instruction | |
10962 | BRANCH_PADDING | |
10963 | COND_JUMP | |
10964 | */ | |
10965 | cmp_fragP = i386_next_non_empty_frag (next_fragP); | |
10966 | pad_fragP = i386_next_non_empty_frag (cmp_fragP); | |
10967 | branch_fragP = i386_next_jcc_frag (pad_fragP); | |
10968 | if (branch_fragP) | |
10969 | { | |
10970 | /* The BRANCH_PADDING frag is merged with the | |
10971 | FUSED_JCC_PADDING frag. */ | |
10972 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
10973 | /* CMP like instruction size. */ | |
10974 | next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix; | |
10975 | frag_wane (pad_fragP); | |
10976 | /* Skip to branch_fragP. */ | |
10977 | next_fragP = branch_fragP; | |
10978 | } | |
10979 | else if (next_fragP->tc_frag_data.max_prefix_length) | |
10980 | { | |
10981 | /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't | |
10982 | a fused jcc. */ | |
10983 | next_fragP->fr_subtype | |
10984 | = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0); | |
10985 | next_fragP->tc_frag_data.max_bytes | |
10986 | = next_fragP->tc_frag_data.max_prefix_length; | |
10987 | /* This will be updated in the BRANCH_PREFIX scan. */ | |
10988 | next_fragP->tc_frag_data.max_prefix_length = 0; | |
10989 | } | |
10990 | else | |
10991 | frag_wane (next_fragP); | |
10992 | break; | |
10993 | } | |
10994 | } | |
10995 | ||
10996 | /* Stop if there is no BRANCH_PREFIX. */ | |
10997 | if (!align_branch_prefix_size) | |
10998 | return; | |
10999 | ||
11000 | /* Scan for BRANCH_PREFIX. */ | |
11001 | for (; fragP != NULL; fragP = fragP->fr_next) | |
11002 | { | |
11003 | if (fragP->fr_type != rs_machine_dependent | |
11004 | || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
11005 | != BRANCH_PREFIX)) | |
11006 | continue; | |
11007 | ||
11008 | /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and | |
11009 | COND_JUMP_PREFIX. */ | |
11010 | max_prefix_length = 0; | |
11011 | for (next_fragP = fragP; | |
11012 | next_fragP != NULL; | |
11013 | next_fragP = next_fragP->fr_next) | |
11014 | { | |
11015 | if (next_fragP->fr_type == rs_fill) | |
11016 | /* Skip rs_fill frags. */ | |
11017 | continue; | |
11018 | else if (next_fragP->fr_type != rs_machine_dependent) | |
11019 | /* Stop for all other frags. */ | |
11020 | break; | |
11021 | ||
11022 | /* rs_machine_dependent frags. */ | |
11023 | if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11024 | == BRANCH_PREFIX) | |
11025 | { | |
11026 | /* Count BRANCH_PREFIX frags. */ | |
11027 | if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE) | |
11028 | { | |
11029 | max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE; | |
11030 | frag_wane (next_fragP); | |
11031 | } | |
11032 | else | |
11033 | max_prefix_length | |
11034 | += next_fragP->tc_frag_data.max_bytes; | |
11035 | } | |
11036 | else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11037 | == BRANCH_PADDING) | |
11038 | || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11039 | == FUSED_JCC_PADDING)) | |
11040 | { | |
11041 | /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */ | |
11042 | fragP->tc_frag_data.u.padding_fragP = next_fragP; | |
11043 | break; | |
11044 | } | |
11045 | else | |
11046 | /* Stop for other rs_machine_dependent frags. */ | |
11047 | break; | |
11048 | } | |
11049 | ||
11050 | fragP->tc_frag_data.max_prefix_length = max_prefix_length; | |
11051 | ||
11052 | /* Skip to the next frag. */ | |
11053 | fragP = next_fragP; | |
11054 | } | |
11055 | } | |
11056 | ||
11057 | /* Compute padding size for | |
11058 | ||
11059 | FUSED_JCC_PADDING | |
11060 | CMP like instruction | |
11061 | BRANCH_PADDING | |
11062 | COND_JUMP/UNCOND_JUMP | |
11063 | ||
11064 | or | |
11065 | ||
11066 | BRANCH_PADDING | |
11067 | COND_JUMP/UNCOND_JUMP | |
11068 | */ | |
11069 | ||
11070 | static int | |
11071 | i386_branch_padding_size (fragS *fragP, offsetT address) | |
11072 | { | |
11073 | unsigned int offset, size, padding_size; | |
11074 | fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP; | |
11075 | ||
11076 | /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */ | |
11077 | if (!address) | |
11078 | address = fragP->fr_address; | |
11079 | address += fragP->fr_fix; | |
11080 | ||
11081 | /* CMP like instrunction size. */ | |
11082 | size = fragP->tc_frag_data.cmp_size; | |
11083 | ||
11084 | /* The base size of the branch frag. */ | |
11085 | size += branch_fragP->fr_fix; | |
11086 | ||
11087 | /* Add opcode and displacement bytes for the rs_machine_dependent | |
11088 | branch frag. */ | |
11089 | if (branch_fragP->fr_type == rs_machine_dependent) | |
11090 | size += md_relax_table[branch_fragP->fr_subtype].rlx_length; | |
11091 | ||
11092 | /* Check if branch is within boundary and doesn't end at the last | |
11093 | byte. */ | |
11094 | offset = address & ((1U << align_branch_power) - 1); | |
11095 | if ((offset + size) >= (1U << align_branch_power)) | |
11096 | /* Padding needed to avoid crossing boundary. */ | |
11097 | padding_size = (1U << align_branch_power) - offset; | |
11098 | else | |
11099 | /* No padding needed. */ | |
11100 | padding_size = 0; | |
11101 | ||
11102 | /* The return value may be saved in tc_frag_data.length which is | |
11103 | unsigned byte. */ | |
11104 | if (!fits_in_unsigned_byte (padding_size)) | |
11105 | abort (); | |
11106 | ||
11107 | return padding_size; | |
11108 | } | |
11109 | ||
11110 | /* i386_generic_table_relax_frag() | |
11111 | ||
11112 | Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to | |
11113 | grow/shrink padding to align branch frags. Hand others to | |
11114 | relax_frag(). */ | |
11115 | ||
11116 | long | |
11117 | i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch) | |
11118 | { | |
11119 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
11120 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
11121 | { | |
11122 | long padding_size = i386_branch_padding_size (fragP, 0); | |
11123 | long grow = padding_size - fragP->tc_frag_data.length; | |
11124 | ||
11125 | /* When the BRANCH_PREFIX frag is used, the computed address | |
11126 | must match the actual address and there should be no padding. */ | |
11127 | if (fragP->tc_frag_data.padding_address | |
11128 | && (fragP->tc_frag_data.padding_address != fragP->fr_address | |
11129 | || padding_size)) | |
11130 | abort (); | |
11131 | ||
11132 | /* Update the padding size. */ | |
11133 | if (grow) | |
11134 | fragP->tc_frag_data.length = padding_size; | |
11135 | ||
11136 | return grow; | |
11137 | } | |
11138 | else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11139 | { | |
11140 | fragS *padding_fragP, *next_fragP; | |
11141 | long padding_size, left_size, last_size; | |
11142 | ||
11143 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
11144 | if (!padding_fragP) | |
11145 | /* Use the padding set by the leading BRANCH_PREFIX frag. */ | |
11146 | return (fragP->tc_frag_data.length | |
11147 | - fragP->tc_frag_data.last_length); | |
11148 | ||
11149 | /* Compute the relative address of the padding frag in the very | |
11150 | first time where the BRANCH_PREFIX frag sizes are zero. */ | |
11151 | if (!fragP->tc_frag_data.padding_address) | |
11152 | fragP->tc_frag_data.padding_address | |
11153 | = padding_fragP->fr_address - (fragP->fr_address - stretch); | |
11154 | ||
11155 | /* First update the last length from the previous interation. */ | |
11156 | left_size = fragP->tc_frag_data.prefix_length; | |
11157 | for (next_fragP = fragP; | |
11158 | next_fragP != padding_fragP; | |
11159 | next_fragP = next_fragP->fr_next) | |
11160 | if (next_fragP->fr_type == rs_machine_dependent | |
11161 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11162 | == BRANCH_PREFIX)) | |
11163 | { | |
11164 | if (left_size) | |
11165 | { | |
11166 | int max = next_fragP->tc_frag_data.max_bytes; | |
11167 | if (max) | |
11168 | { | |
11169 | int size; | |
11170 | if (max > left_size) | |
11171 | size = left_size; | |
11172 | else | |
11173 | size = max; | |
11174 | left_size -= size; | |
11175 | next_fragP->tc_frag_data.last_length = size; | |
11176 | } | |
11177 | } | |
11178 | else | |
11179 | next_fragP->tc_frag_data.last_length = 0; | |
11180 | } | |
11181 | ||
11182 | /* Check the padding size for the padding frag. */ | |
11183 | padding_size = i386_branch_padding_size | |
11184 | (padding_fragP, (fragP->fr_address | |
11185 | + fragP->tc_frag_data.padding_address)); | |
11186 | ||
11187 | last_size = fragP->tc_frag_data.prefix_length; | |
11188 | /* Check if there is change from the last interation. */ | |
11189 | if (padding_size == last_size) | |
11190 | { | |
11191 | /* Update the expected address of the padding frag. */ | |
11192 | padding_fragP->tc_frag_data.padding_address | |
11193 | = (fragP->fr_address + padding_size | |
11194 | + fragP->tc_frag_data.padding_address); | |
11195 | return 0; | |
11196 | } | |
11197 | ||
11198 | if (padding_size > fragP->tc_frag_data.max_prefix_length) | |
11199 | { | |
11200 | /* No padding if there is no sufficient room. Clear the | |
11201 | expected address of the padding frag. */ | |
11202 | padding_fragP->tc_frag_data.padding_address = 0; | |
11203 | padding_size = 0; | |
11204 | } | |
11205 | else | |
11206 | /* Store the expected address of the padding frag. */ | |
11207 | padding_fragP->tc_frag_data.padding_address | |
11208 | = (fragP->fr_address + padding_size | |
11209 | + fragP->tc_frag_data.padding_address); | |
11210 | ||
11211 | fragP->tc_frag_data.prefix_length = padding_size; | |
11212 | ||
11213 | /* Update the length for the current interation. */ | |
11214 | left_size = padding_size; | |
11215 | for (next_fragP = fragP; | |
11216 | next_fragP != padding_fragP; | |
11217 | next_fragP = next_fragP->fr_next) | |
11218 | if (next_fragP->fr_type == rs_machine_dependent | |
11219 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11220 | == BRANCH_PREFIX)) | |
11221 | { | |
11222 | if (left_size) | |
11223 | { | |
11224 | int max = next_fragP->tc_frag_data.max_bytes; | |
11225 | if (max) | |
11226 | { | |
11227 | int size; | |
11228 | if (max > left_size) | |
11229 | size = left_size; | |
11230 | else | |
11231 | size = max; | |
11232 | left_size -= size; | |
11233 | next_fragP->tc_frag_data.length = size; | |
11234 | } | |
11235 | } | |
11236 | else | |
11237 | next_fragP->tc_frag_data.length = 0; | |
11238 | } | |
11239 | ||
11240 | return (fragP->tc_frag_data.length | |
11241 | - fragP->tc_frag_data.last_length); | |
11242 | } | |
11243 | return relax_frag (segment, fragP, stretch); | |
11244 | } | |
11245 | ||
ee7fcc42 AM |
11246 | /* md_estimate_size_before_relax() |
11247 | ||
11248 | Called just before relax() for rs_machine_dependent frags. The x86 | |
11249 | assembler uses these frags to handle variable size jump | |
11250 | instructions. | |
11251 | ||
11252 | Any symbol that is now undefined will not become defined. | |
11253 | Return the correct fr_subtype in the frag. | |
11254 | Return the initial "guess for variable size of frag" to caller. | |
11255 | The guess is actually the growth beyond the fixed part. Whatever | |
11256 | we do to grow the fixed or variable part contributes to our | |
11257 | returned value. */ | |
11258 | ||
252b5132 | 11259 | int |
7016a5d5 | 11260 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 11261 | { |
e379e5f3 L |
11262 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
11263 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX | |
11264 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
11265 | { | |
11266 | i386_classify_machine_dependent_frag (fragP); | |
11267 | return fragP->tc_frag_data.length; | |
11268 | } | |
11269 | ||
252b5132 | 11270 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
11271 | check for un-relaxable symbols. On an ELF system, we can't relax |
11272 | an externally visible symbol, because it may be overridden by a | |
11273 | shared library. */ | |
11274 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 11275 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 11276 | || (IS_ELF |
8dcea932 L |
11277 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
11278 | fragP->fr_var)) | |
fbeb56a4 DK |
11279 | #endif |
11280 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 11281 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 11282 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
11283 | #endif |
11284 | ) | |
252b5132 | 11285 | { |
b98ef147 AM |
11286 | /* Symbol is undefined in this segment, or we need to keep a |
11287 | reloc so that weak symbols can be overridden. */ | |
11288 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 11289 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
11290 | unsigned char *opcode; |
11291 | int old_fr_fix; | |
f6af82bd | 11292 | |
ee7fcc42 | 11293 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 11294 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 11295 | else if (size == 2) |
f6af82bd | 11296 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
11297 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11298 | else if (need_plt32_p (fragP->fr_symbol)) | |
11299 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
11300 | #endif | |
f6af82bd AM |
11301 | else |
11302 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 11303 | |
ee7fcc42 AM |
11304 | old_fr_fix = fragP->fr_fix; |
11305 | opcode = (unsigned char *) fragP->fr_opcode; | |
11306 | ||
fddf5b5b | 11307 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 11308 | { |
fddf5b5b AM |
11309 | case UNCOND_JUMP: |
11310 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 11311 | opcode[0] = 0xe9; |
252b5132 | 11312 | fragP->fr_fix += size; |
062cd5e7 AS |
11313 | fix_new (fragP, old_fr_fix, size, |
11314 | fragP->fr_symbol, | |
11315 | fragP->fr_offset, 1, | |
11316 | reloc_type); | |
252b5132 RH |
11317 | break; |
11318 | ||
fddf5b5b | 11319 | case COND_JUMP86: |
412167cb AM |
11320 | if (size == 2 |
11321 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
11322 | { |
11323 | /* Negate the condition, and branch past an | |
11324 | unconditional jump. */ | |
11325 | opcode[0] ^= 1; | |
11326 | opcode[1] = 3; | |
11327 | /* Insert an unconditional jump. */ | |
11328 | opcode[2] = 0xe9; | |
11329 | /* We added two extra opcode bytes, and have a two byte | |
11330 | offset. */ | |
11331 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
11332 | fix_new (fragP, old_fr_fix + 2, 2, |
11333 | fragP->fr_symbol, | |
11334 | fragP->fr_offset, 1, | |
11335 | reloc_type); | |
fddf5b5b AM |
11336 | break; |
11337 | } | |
11338 | /* Fall through. */ | |
11339 | ||
11340 | case COND_JUMP: | |
412167cb AM |
11341 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
11342 | { | |
3e02c1cc AM |
11343 | fixS *fixP; |
11344 | ||
412167cb | 11345 | fragP->fr_fix += 1; |
3e02c1cc AM |
11346 | fixP = fix_new (fragP, old_fr_fix, 1, |
11347 | fragP->fr_symbol, | |
11348 | fragP->fr_offset, 1, | |
11349 | BFD_RELOC_8_PCREL); | |
11350 | fixP->fx_signed = 1; | |
412167cb AM |
11351 | break; |
11352 | } | |
93c2a809 | 11353 | |
24eab124 | 11354 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 11355 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 11356 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 11357 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
11358 | /* We've added an opcode byte. */ |
11359 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
11360 | fix_new (fragP, old_fr_fix + 1, size, |
11361 | fragP->fr_symbol, | |
11362 | fragP->fr_offset, 1, | |
11363 | reloc_type); | |
252b5132 | 11364 | break; |
fddf5b5b AM |
11365 | |
11366 | default: | |
11367 | BAD_CASE (fragP->fr_subtype); | |
11368 | break; | |
252b5132 RH |
11369 | } |
11370 | frag_wane (fragP); | |
ee7fcc42 | 11371 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 11372 | } |
93c2a809 | 11373 | |
93c2a809 AM |
11374 | /* Guess size depending on current relax state. Initially the relax |
11375 | state will correspond to a short jump and we return 1, because | |
11376 | the variable part of the frag (the branch offset) is one byte | |
11377 | long. However, we can relax a section more than once and in that | |
11378 | case we must either set fr_subtype back to the unrelaxed state, | |
11379 | or return the value for the appropriate branch. */ | |
11380 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
11381 | } |
11382 | ||
47926f60 KH |
11383 | /* Called after relax() is finished. |
11384 | ||
11385 | In: Address of frag. | |
11386 | fr_type == rs_machine_dependent. | |
11387 | fr_subtype is what the address relaxed to. | |
11388 | ||
11389 | Out: Any fixSs and constants are set up. | |
11390 | Caller will turn frag into a ".space 0". */ | |
11391 | ||
252b5132 | 11392 | void |
7016a5d5 TG |
11393 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
11394 | fragS *fragP) | |
252b5132 | 11395 | { |
29b0f896 | 11396 | unsigned char *opcode; |
252b5132 | 11397 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
11398 | offsetT target_address; |
11399 | offsetT opcode_address; | |
252b5132 | 11400 | unsigned int extension = 0; |
847f7ad4 | 11401 | offsetT displacement_from_opcode_start; |
252b5132 | 11402 | |
e379e5f3 L |
11403 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
11404 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING | |
11405 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11406 | { | |
11407 | /* Generate nop padding. */ | |
11408 | unsigned int size = fragP->tc_frag_data.length; | |
11409 | if (size) | |
11410 | { | |
11411 | if (size > fragP->tc_frag_data.max_bytes) | |
11412 | abort (); | |
11413 | ||
11414 | if (flag_debug) | |
11415 | { | |
11416 | const char *msg; | |
11417 | const char *branch = "branch"; | |
11418 | const char *prefix = ""; | |
11419 | fragS *padding_fragP; | |
11420 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
11421 | == BRANCH_PREFIX) | |
11422 | { | |
11423 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
11424 | switch (fragP->tc_frag_data.default_prefix) | |
11425 | { | |
11426 | default: | |
11427 | abort (); | |
11428 | break; | |
11429 | case CS_PREFIX_OPCODE: | |
11430 | prefix = " cs"; | |
11431 | break; | |
11432 | case DS_PREFIX_OPCODE: | |
11433 | prefix = " ds"; | |
11434 | break; | |
11435 | case ES_PREFIX_OPCODE: | |
11436 | prefix = " es"; | |
11437 | break; | |
11438 | case FS_PREFIX_OPCODE: | |
11439 | prefix = " fs"; | |
11440 | break; | |
11441 | case GS_PREFIX_OPCODE: | |
11442 | prefix = " gs"; | |
11443 | break; | |
11444 | case SS_PREFIX_OPCODE: | |
11445 | prefix = " ss"; | |
11446 | break; | |
11447 | } | |
11448 | if (padding_fragP) | |
11449 | msg = _("%s:%u: add %d%s at 0x%llx to align " | |
11450 | "%s within %d-byte boundary\n"); | |
11451 | else | |
11452 | msg = _("%s:%u: add additional %d%s at 0x%llx to " | |
11453 | "align %s within %d-byte boundary\n"); | |
11454 | } | |
11455 | else | |
11456 | { | |
11457 | padding_fragP = fragP; | |
11458 | msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align " | |
11459 | "%s within %d-byte boundary\n"); | |
11460 | } | |
11461 | ||
11462 | if (padding_fragP) | |
11463 | switch (padding_fragP->tc_frag_data.branch_type) | |
11464 | { | |
11465 | case align_branch_jcc: | |
11466 | branch = "jcc"; | |
11467 | break; | |
11468 | case align_branch_fused: | |
11469 | branch = "fused jcc"; | |
11470 | break; | |
11471 | case align_branch_jmp: | |
11472 | branch = "jmp"; | |
11473 | break; | |
11474 | case align_branch_call: | |
11475 | branch = "call"; | |
11476 | break; | |
11477 | case align_branch_indirect: | |
11478 | branch = "indiret branch"; | |
11479 | break; | |
11480 | case align_branch_ret: | |
11481 | branch = "ret"; | |
11482 | break; | |
11483 | default: | |
11484 | break; | |
11485 | } | |
11486 | ||
11487 | fprintf (stdout, msg, | |
11488 | fragP->fr_file, fragP->fr_line, size, prefix, | |
11489 | (long long) fragP->fr_address, branch, | |
11490 | 1 << align_branch_power); | |
11491 | } | |
11492 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11493 | memset (fragP->fr_opcode, | |
11494 | fragP->tc_frag_data.default_prefix, size); | |
11495 | else | |
11496 | i386_generate_nops (fragP, (char *) fragP->fr_opcode, | |
11497 | size, 0); | |
11498 | fragP->fr_fix += size; | |
11499 | } | |
11500 | return; | |
11501 | } | |
11502 | ||
252b5132 RH |
11503 | opcode = (unsigned char *) fragP->fr_opcode; |
11504 | ||
47926f60 | 11505 | /* Address we want to reach in file space. */ |
252b5132 | 11506 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 11507 | |
47926f60 | 11508 | /* Address opcode resides at in file space. */ |
252b5132 RH |
11509 | opcode_address = fragP->fr_address + fragP->fr_fix; |
11510 | ||
47926f60 | 11511 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
11512 | displacement_from_opcode_start = target_address - opcode_address; |
11513 | ||
fddf5b5b | 11514 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 11515 | { |
47926f60 KH |
11516 | /* Don't have to change opcode. */ |
11517 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 11518 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
11519 | } |
11520 | else | |
11521 | { | |
11522 | if (no_cond_jump_promotion | |
11523 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
11524 | as_warn_where (fragP->fr_file, fragP->fr_line, |
11525 | _("long jump required")); | |
252b5132 | 11526 | |
fddf5b5b AM |
11527 | switch (fragP->fr_subtype) |
11528 | { | |
11529 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
11530 | extension = 4; /* 1 opcode + 4 displacement */ | |
11531 | opcode[0] = 0xe9; | |
11532 | where_to_put_displacement = &opcode[1]; | |
11533 | break; | |
252b5132 | 11534 | |
fddf5b5b AM |
11535 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
11536 | extension = 2; /* 1 opcode + 2 displacement */ | |
11537 | opcode[0] = 0xe9; | |
11538 | where_to_put_displacement = &opcode[1]; | |
11539 | break; | |
252b5132 | 11540 | |
fddf5b5b AM |
11541 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
11542 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
11543 | extension = 5; /* 2 opcode + 4 displacement */ | |
11544 | opcode[1] = opcode[0] + 0x10; | |
11545 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
11546 | where_to_put_displacement = &opcode[2]; | |
11547 | break; | |
252b5132 | 11548 | |
fddf5b5b AM |
11549 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
11550 | extension = 3; /* 2 opcode + 2 displacement */ | |
11551 | opcode[1] = opcode[0] + 0x10; | |
11552 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
11553 | where_to_put_displacement = &opcode[2]; | |
11554 | break; | |
252b5132 | 11555 | |
fddf5b5b AM |
11556 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
11557 | extension = 4; | |
11558 | opcode[0] ^= 1; | |
11559 | opcode[1] = 3; | |
11560 | opcode[2] = 0xe9; | |
11561 | where_to_put_displacement = &opcode[3]; | |
11562 | break; | |
11563 | ||
11564 | default: | |
11565 | BAD_CASE (fragP->fr_subtype); | |
11566 | break; | |
11567 | } | |
252b5132 | 11568 | } |
fddf5b5b | 11569 | |
7b81dfbb AJ |
11570 | /* If size if less then four we are sure that the operand fits, |
11571 | but if it's 4, then it could be that the displacement is larger | |
11572 | then -/+ 2GB. */ | |
11573 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
11574 | && object_64bit | |
11575 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
11576 | + ((addressT) 1 << 31)) |
11577 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
11578 | { |
11579 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
11580 | _("jump target out of range")); | |
11581 | /* Make us emit 0. */ | |
11582 | displacement_from_opcode_start = extension; | |
11583 | } | |
47926f60 | 11584 | /* Now put displacement after opcode. */ |
252b5132 RH |
11585 | md_number_to_chars ((char *) where_to_put_displacement, |
11586 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 11587 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
11588 | fragP->fr_fix += extension; |
11589 | } | |
11590 | \f | |
7016a5d5 | 11591 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
11592 | by our caller that we have all the info we need to fix it up. |
11593 | ||
7016a5d5 TG |
11594 | Parameter valP is the pointer to the value of the bits. |
11595 | ||
252b5132 RH |
11596 | On the 386, immediates, displacements, and data pointers are all in |
11597 | the same (little-endian) format, so we don't need to care about which | |
11598 | we are handling. */ | |
11599 | ||
94f592af | 11600 | void |
7016a5d5 | 11601 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11602 | { |
94f592af | 11603 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 11604 | valueT value = *valP; |
252b5132 | 11605 | |
f86103b7 | 11606 | #if !defined (TE_Mach) |
93382f6d AM |
11607 | if (fixP->fx_pcrel) |
11608 | { | |
11609 | switch (fixP->fx_r_type) | |
11610 | { | |
5865bb77 ILT |
11611 | default: |
11612 | break; | |
11613 | ||
d6ab8113 JB |
11614 | case BFD_RELOC_64: |
11615 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
11616 | break; | |
93382f6d | 11617 | case BFD_RELOC_32: |
ae8887b5 | 11618 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
11619 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
11620 | break; | |
11621 | case BFD_RELOC_16: | |
11622 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
11623 | break; | |
11624 | case BFD_RELOC_8: | |
11625 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
11626 | break; | |
11627 | } | |
11628 | } | |
252b5132 | 11629 | |
a161fe53 | 11630 | if (fixP->fx_addsy != NULL |
31312f95 | 11631 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 11632 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 11633 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 11634 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 11635 | && !use_rela_relocations) |
252b5132 | 11636 | { |
31312f95 AM |
11637 | /* This is a hack. There should be a better way to handle this. |
11638 | This covers for the fact that bfd_install_relocation will | |
11639 | subtract the current location (for partial_inplace, PC relative | |
11640 | relocations); see more below. */ | |
252b5132 | 11641 | #ifndef OBJ_AOUT |
718ddfc0 | 11642 | if (IS_ELF |
252b5132 RH |
11643 | #ifdef TE_PE |
11644 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
11645 | #endif | |
11646 | ) | |
11647 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
11648 | #endif | |
11649 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 11650 | if (IS_ELF) |
252b5132 | 11651 | { |
6539b54b | 11652 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 11653 | |
6539b54b | 11654 | if ((sym_seg == seg |
2f66722d | 11655 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 11656 | && sym_seg != absolute_section)) |
af65af87 | 11657 | && !generic_force_reloc (fixP)) |
2f66722d AM |
11658 | { |
11659 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
11660 | bfd_install_relocation subtracts them out again. I think |
11661 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
11662 | it. FIXME. */ |
11663 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
11664 | } | |
252b5132 RH |
11665 | } |
11666 | #endif | |
11667 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
11668 | /* For some reason, the PE format does not store a |
11669 | section address offset for a PC relative symbol. */ | |
11670 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 11671 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
11672 | value += md_pcrel_from (fixP); |
11673 | #endif | |
11674 | } | |
fbeb56a4 | 11675 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
11676 | if (fixP->fx_addsy != NULL |
11677 | && S_IS_WEAK (fixP->fx_addsy) | |
11678 | /* PR 16858: Do not modify weak function references. */ | |
11679 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 11680 | { |
296a8689 NC |
11681 | #if !defined (TE_PEP) |
11682 | /* For x86 PE weak function symbols are neither PC-relative | |
11683 | nor do they set S_IS_FUNCTION. So the only reliable way | |
11684 | to detect them is to check the flags of their containing | |
11685 | section. */ | |
11686 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
11687 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
11688 | ; | |
11689 | else | |
11690 | #endif | |
fbeb56a4 DK |
11691 | value -= S_GET_VALUE (fixP->fx_addsy); |
11692 | } | |
11693 | #endif | |
252b5132 RH |
11694 | |
11695 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 11696 | and we must not disappoint it. */ |
252b5132 | 11697 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 11698 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
11699 | switch (fixP->fx_r_type) |
11700 | { | |
11701 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 11702 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
11703 | /* Make the jump instruction point to the address of the operand. |
11704 | At runtime we merely add the offset to the actual PLT entry. | |
11705 | NB: Subtract the offset size only for jump instructions. */ | |
11706 | if (fixP->fx_pcrel) | |
11707 | value = -4; | |
47926f60 | 11708 | break; |
31312f95 | 11709 | |
13ae64f3 JJ |
11710 | case BFD_RELOC_386_TLS_GD: |
11711 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 11712 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
11713 | case BFD_RELOC_386_TLS_IE: |
11714 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 11715 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
11716 | case BFD_RELOC_X86_64_TLSGD: |
11717 | case BFD_RELOC_X86_64_TLSLD: | |
11718 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 11719 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
11720 | value = 0; /* Fully resolved at runtime. No addend. */ |
11721 | /* Fallthrough */ | |
11722 | case BFD_RELOC_386_TLS_LE: | |
11723 | case BFD_RELOC_386_TLS_LDO_32: | |
11724 | case BFD_RELOC_386_TLS_LE_32: | |
11725 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 11726 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 11727 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 11728 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
11729 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
11730 | break; | |
11731 | ||
67a4f2b7 AO |
11732 | case BFD_RELOC_386_TLS_DESC_CALL: |
11733 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
11734 | value = 0; /* Fully resolved at runtime. No addend. */ | |
11735 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11736 | fixP->fx_done = 0; | |
11737 | return; | |
11738 | ||
47926f60 KH |
11739 | case BFD_RELOC_VTABLE_INHERIT: |
11740 | case BFD_RELOC_VTABLE_ENTRY: | |
11741 | fixP->fx_done = 0; | |
94f592af | 11742 | return; |
47926f60 KH |
11743 | |
11744 | default: | |
11745 | break; | |
11746 | } | |
11747 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 11748 | *valP = value; |
f86103b7 | 11749 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 11750 | |
3e73aa7c | 11751 | /* Are we finished with this relocation now? */ |
c6682705 | 11752 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 11753 | fixP->fx_done = 1; |
fbeb56a4 DK |
11754 | #if defined (OBJ_COFF) && defined (TE_PE) |
11755 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
11756 | { | |
11757 | fixP->fx_done = 0; | |
11758 | /* Remember value for tc_gen_reloc. */ | |
11759 | fixP->fx_addnumber = value; | |
11760 | /* Clear out the frag for now. */ | |
11761 | value = 0; | |
11762 | } | |
11763 | #endif | |
3e73aa7c JH |
11764 | else if (use_rela_relocations) |
11765 | { | |
11766 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
11767 | /* Remember value for tc_gen_reloc. */ |
11768 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
11769 | value = 0; |
11770 | } | |
f86103b7 | 11771 | |
94f592af | 11772 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 11773 | } |
252b5132 | 11774 | \f |
6d4af3c2 | 11775 | const char * |
499ac353 | 11776 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 11777 | { |
499ac353 NC |
11778 | /* This outputs the LITTLENUMs in REVERSE order; |
11779 | in accord with the bigendian 386. */ | |
11780 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
11781 | } |
11782 | \f | |
2d545b82 | 11783 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 11784 | |
252b5132 | 11785 | static char * |
e3bb37b5 | 11786 | output_invalid (int c) |
252b5132 | 11787 | { |
3882b010 | 11788 | if (ISPRINT (c)) |
f9f21a03 L |
11789 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
11790 | "'%c'", c); | |
252b5132 | 11791 | else |
f9f21a03 | 11792 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 11793 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
11794 | return output_invalid_buf; |
11795 | } | |
11796 | ||
af6bdddf | 11797 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
11798 | |
11799 | static const reg_entry * | |
4d1bb795 | 11800 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 11801 | { |
af6bdddf AM |
11802 | char *s = reg_string; |
11803 | char *p; | |
252b5132 RH |
11804 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
11805 | const reg_entry *r; | |
11806 | ||
11807 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
11808 | if (*s == REGISTER_PREFIX) | |
11809 | ++s; | |
11810 | ||
11811 | if (is_space_char (*s)) | |
11812 | ++s; | |
11813 | ||
11814 | p = reg_name_given; | |
af6bdddf | 11815 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
11816 | { |
11817 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
11818 | return (const reg_entry *) NULL; |
11819 | s++; | |
252b5132 RH |
11820 | } |
11821 | ||
6588847e DN |
11822 | /* For naked regs, make sure that we are not dealing with an identifier. |
11823 | This prevents confusing an identifier like `eax_var' with register | |
11824 | `eax'. */ | |
11825 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
11826 | return (const reg_entry *) NULL; | |
11827 | ||
af6bdddf | 11828 | *end_op = s; |
252b5132 RH |
11829 | |
11830 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
11831 | ||
5f47d35b | 11832 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 11833 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 11834 | { |
0e0eea78 JB |
11835 | if (!cpu_arch_flags.bitfield.cpu8087 |
11836 | && !cpu_arch_flags.bitfield.cpu287 | |
11837 | && !cpu_arch_flags.bitfield.cpu387) | |
11838 | return (const reg_entry *) NULL; | |
11839 | ||
5f47d35b AM |
11840 | if (is_space_char (*s)) |
11841 | ++s; | |
11842 | if (*s == '(') | |
11843 | { | |
af6bdddf | 11844 | ++s; |
5f47d35b AM |
11845 | if (is_space_char (*s)) |
11846 | ++s; | |
11847 | if (*s >= '0' && *s <= '7') | |
11848 | { | |
db557034 | 11849 | int fpr = *s - '0'; |
af6bdddf | 11850 | ++s; |
5f47d35b AM |
11851 | if (is_space_char (*s)) |
11852 | ++s; | |
11853 | if (*s == ')') | |
11854 | { | |
11855 | *end_op = s + 1; | |
1e9cc1c2 | 11856 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
11857 | know (r); |
11858 | return r + fpr; | |
5f47d35b | 11859 | } |
5f47d35b | 11860 | } |
47926f60 | 11861 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
11862 | return (const reg_entry *) NULL; |
11863 | } | |
11864 | } | |
11865 | ||
a60de03c JB |
11866 | if (r == NULL || allow_pseudo_reg) |
11867 | return r; | |
11868 | ||
0dfbf9d7 | 11869 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
11870 | return (const reg_entry *) NULL; |
11871 | ||
dc821c5f | 11872 | if ((r->reg_type.bitfield.dword |
00cee14f | 11873 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) |
4a5c67ed JB |
11874 | || r->reg_type.bitfield.class == RegCR |
11875 | || r->reg_type.bitfield.class == RegDR | |
11876 | || r->reg_type.bitfield.class == RegTR) | |
192dc9c6 JB |
11877 | && !cpu_arch_flags.bitfield.cpui386) |
11878 | return (const reg_entry *) NULL; | |
11879 | ||
3528c362 | 11880 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
192dc9c6 JB |
11881 | return (const reg_entry *) NULL; |
11882 | ||
6e041cf4 JB |
11883 | if (!cpu_arch_flags.bitfield.cpuavx512f) |
11884 | { | |
f74a6307 JB |
11885 | if (r->reg_type.bitfield.zmmword |
11886 | || r->reg_type.bitfield.class == RegMask) | |
6e041cf4 | 11887 | return (const reg_entry *) NULL; |
40f12533 | 11888 | |
6e041cf4 JB |
11889 | if (!cpu_arch_flags.bitfield.cpuavx) |
11890 | { | |
11891 | if (r->reg_type.bitfield.ymmword) | |
11892 | return (const reg_entry *) NULL; | |
1848e567 | 11893 | |
6e041cf4 JB |
11894 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) |
11895 | return (const reg_entry *) NULL; | |
11896 | } | |
11897 | } | |
43234a1e | 11898 | |
f74a6307 | 11899 | if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx) |
1adf7f56 JB |
11900 | return (const reg_entry *) NULL; |
11901 | ||
db51cc60 | 11902 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
e968fc9b | 11903 | if (!allow_index_reg && r->reg_num == RegIZ) |
db51cc60 L |
11904 | return (const reg_entry *) NULL; |
11905 | ||
1d3f8286 JB |
11906 | /* Upper 16 vector registers are only available with VREX in 64bit |
11907 | mode, and require EVEX encoding. */ | |
11908 | if (r->reg_flags & RegVRex) | |
43234a1e | 11909 | { |
e951d5ca | 11910 | if (!cpu_arch_flags.bitfield.cpuavx512f |
43234a1e L |
11911 | || flag_code != CODE_64BIT) |
11912 | return (const reg_entry *) NULL; | |
1d3f8286 JB |
11913 | |
11914 | i.vec_encoding = vex_encoding_evex; | |
43234a1e L |
11915 | } |
11916 | ||
4787f4a5 | 11917 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
4a5c67ed | 11918 | && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR) |
1ae00879 | 11919 | && flag_code != CODE_64BIT) |
20f0a1fc | 11920 | return (const reg_entry *) NULL; |
1ae00879 | 11921 | |
00cee14f JB |
11922 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat |
11923 | && !intel_syntax) | |
b7240065 JB |
11924 | return (const reg_entry *) NULL; |
11925 | ||
252b5132 RH |
11926 | return r; |
11927 | } | |
4d1bb795 JB |
11928 | |
11929 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
11930 | ||
11931 | static const reg_entry * | |
11932 | parse_register (char *reg_string, char **end_op) | |
11933 | { | |
11934 | const reg_entry *r; | |
11935 | ||
11936 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
11937 | r = parse_real_register (reg_string, end_op); | |
11938 | else | |
11939 | r = NULL; | |
11940 | if (!r) | |
11941 | { | |
11942 | char *save = input_line_pointer; | |
11943 | char c; | |
11944 | symbolS *symbolP; | |
11945 | ||
11946 | input_line_pointer = reg_string; | |
d02603dc | 11947 | c = get_symbol_name (®_string); |
4d1bb795 JB |
11948 | symbolP = symbol_find (reg_string); |
11949 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
11950 | { | |
11951 | const expressionS *e = symbol_get_value_expression (symbolP); | |
11952 | ||
0398aac5 | 11953 | know (e->X_op == O_register); |
4eed87de | 11954 | know (e->X_add_number >= 0 |
c3fe08fa | 11955 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 11956 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 11957 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 11958 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
11959 | *end_op = input_line_pointer; |
11960 | } | |
11961 | *input_line_pointer = c; | |
11962 | input_line_pointer = save; | |
11963 | } | |
11964 | return r; | |
11965 | } | |
11966 | ||
11967 | int | |
11968 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
11969 | { | |
11970 | const reg_entry *r; | |
11971 | char *end = input_line_pointer; | |
11972 | ||
11973 | *end = *nextcharP; | |
11974 | r = parse_register (name, &input_line_pointer); | |
11975 | if (r && end <= input_line_pointer) | |
11976 | { | |
11977 | *nextcharP = *input_line_pointer; | |
11978 | *input_line_pointer = 0; | |
11979 | e->X_op = O_register; | |
11980 | e->X_add_number = r - i386_regtab; | |
11981 | return 1; | |
11982 | } | |
11983 | input_line_pointer = end; | |
11984 | *end = 0; | |
ee86248c | 11985 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
11986 | } |
11987 | ||
11988 | void | |
11989 | md_operand (expressionS *e) | |
11990 | { | |
ee86248c JB |
11991 | char *end; |
11992 | const reg_entry *r; | |
4d1bb795 | 11993 | |
ee86248c JB |
11994 | switch (*input_line_pointer) |
11995 | { | |
11996 | case REGISTER_PREFIX: | |
11997 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
11998 | if (r) |
11999 | { | |
12000 | e->X_op = O_register; | |
12001 | e->X_add_number = r - i386_regtab; | |
12002 | input_line_pointer = end; | |
12003 | } | |
ee86248c JB |
12004 | break; |
12005 | ||
12006 | case '[': | |
9c2799c2 | 12007 | gas_assert (intel_syntax); |
ee86248c JB |
12008 | end = input_line_pointer++; |
12009 | expression (e); | |
12010 | if (*input_line_pointer == ']') | |
12011 | { | |
12012 | ++input_line_pointer; | |
12013 | e->X_op_symbol = make_expr_symbol (e); | |
12014 | e->X_add_symbol = NULL; | |
12015 | e->X_add_number = 0; | |
12016 | e->X_op = O_index; | |
12017 | } | |
12018 | else | |
12019 | { | |
12020 | e->X_op = O_absent; | |
12021 | input_line_pointer = end; | |
12022 | } | |
12023 | break; | |
4d1bb795 JB |
12024 | } |
12025 | } | |
12026 | ||
252b5132 | 12027 | \f |
4cc782b5 | 12028 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 12029 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 12030 | #else |
b6f8c7c4 | 12031 | const char *md_shortopts = "qnO::"; |
252b5132 | 12032 | #endif |
6e0b89ee | 12033 | |
3e73aa7c | 12034 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
12035 | #define OPTION_64 (OPTION_MD_BASE + 1) |
12036 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
12037 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
12038 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
12039 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
12040 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
12041 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
12042 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 12043 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 12044 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 12045 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
12046 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
12047 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
12048 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 12049 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
12050 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
12051 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 12052 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 12053 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 12054 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 12055 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
12056 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
12057 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 12058 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 12059 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 12060 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
e379e5f3 L |
12061 | #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27) |
12062 | #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28) | |
12063 | #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29) | |
76cf450b | 12064 | #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30) |
b3b91714 | 12065 | |
99ad8390 NC |
12066 | struct option md_longopts[] = |
12067 | { | |
3e73aa7c | 12068 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 12069 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 12070 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 12071 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
12072 | #endif |
12073 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 12074 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 12075 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 12076 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 12077 | #endif |
b3b91714 | 12078 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
12079 | {"march", required_argument, NULL, OPTION_MARCH}, |
12080 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
12081 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
12082 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
12083 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
12084 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 12085 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 12086 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 12087 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 12088 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 12089 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 12090 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
12091 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
12092 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
12093 | # if defined (TE_PE) || defined (TE_PEP) |
12094 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
12095 | #endif | |
d1982f93 | 12096 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 12097 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 12098 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 12099 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
e379e5f3 L |
12100 | {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY}, |
12101 | {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE}, | |
12102 | {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH}, | |
76cf450b | 12103 | {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES}, |
5db04b09 L |
12104 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
12105 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
12106 | {NULL, no_argument, NULL, 0} |
12107 | }; | |
12108 | size_t md_longopts_size = sizeof (md_longopts); | |
12109 | ||
12110 | int | |
17b9d67d | 12111 | md_parse_option (int c, const char *arg) |
252b5132 | 12112 | { |
91d6fa6a | 12113 | unsigned int j; |
e379e5f3 | 12114 | char *arch, *next, *saved, *type; |
9103f4f4 | 12115 | |
252b5132 RH |
12116 | switch (c) |
12117 | { | |
12b55ccc L |
12118 | case 'n': |
12119 | optimize_align_code = 0; | |
12120 | break; | |
12121 | ||
a38cf1db AM |
12122 | case 'q': |
12123 | quiet_warnings = 1; | |
252b5132 RH |
12124 | break; |
12125 | ||
12126 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
12127 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
12128 | should be emitted or not. FIXME: Not implemented. */ | |
12129 | case 'Q': | |
d4693039 JB |
12130 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
12131 | return 0; | |
252b5132 RH |
12132 | break; |
12133 | ||
12134 | /* -V: SVR4 argument to print version ID. */ | |
12135 | case 'V': | |
12136 | print_version_id (); | |
12137 | break; | |
12138 | ||
a38cf1db AM |
12139 | /* -k: Ignore for FreeBSD compatibility. */ |
12140 | case 'k': | |
252b5132 | 12141 | break; |
4cc782b5 ILT |
12142 | |
12143 | case 's': | |
12144 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 12145 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 12146 | break; |
8dcea932 L |
12147 | |
12148 | case OPTION_MSHARED: | |
12149 | shared = 1; | |
12150 | break; | |
b4a3a7b4 L |
12151 | |
12152 | case OPTION_X86_USED_NOTE: | |
12153 | if (strcasecmp (arg, "yes") == 0) | |
12154 | x86_used_note = 1; | |
12155 | else if (strcasecmp (arg, "no") == 0) | |
12156 | x86_used_note = 0; | |
12157 | else | |
12158 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
12159 | break; | |
12160 | ||
12161 | ||
99ad8390 | 12162 | #endif |
321098a5 | 12163 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 12164 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
12165 | case OPTION_64: |
12166 | { | |
12167 | const char **list, **l; | |
12168 | ||
3e73aa7c JH |
12169 | list = bfd_target_list (); |
12170 | for (l = list; *l != NULL; l++) | |
8620418b | 12171 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
12172 | || strcmp (*l, "coff-x86-64") == 0 |
12173 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
12174 | || strcmp (*l, "pei-x86-64") == 0 |
12175 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
12176 | { |
12177 | default_arch = "x86_64"; | |
12178 | break; | |
12179 | } | |
3e73aa7c | 12180 | if (*l == NULL) |
2b5d6a91 | 12181 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
12182 | free (list); |
12183 | } | |
12184 | break; | |
12185 | #endif | |
252b5132 | 12186 | |
351f65ca | 12187 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 12188 | case OPTION_X32: |
351f65ca L |
12189 | if (IS_ELF) |
12190 | { | |
12191 | const char **list, **l; | |
12192 | ||
12193 | list = bfd_target_list (); | |
12194 | for (l = list; *l != NULL; l++) | |
12195 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
12196 | { | |
12197 | default_arch = "x86_64:32"; | |
12198 | break; | |
12199 | } | |
12200 | if (*l == NULL) | |
2b5d6a91 | 12201 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
12202 | free (list); |
12203 | } | |
12204 | else | |
12205 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
12206 | break; | |
12207 | #endif | |
12208 | ||
6e0b89ee AM |
12209 | case OPTION_32: |
12210 | default_arch = "i386"; | |
12211 | break; | |
12212 | ||
b3b91714 AM |
12213 | case OPTION_DIVIDE: |
12214 | #ifdef SVR4_COMMENT_CHARS | |
12215 | { | |
12216 | char *n, *t; | |
12217 | const char *s; | |
12218 | ||
add39d23 | 12219 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
12220 | t = n; |
12221 | for (s = i386_comment_chars; *s != '\0'; s++) | |
12222 | if (*s != '/') | |
12223 | *t++ = *s; | |
12224 | *t = '\0'; | |
12225 | i386_comment_chars = n; | |
12226 | } | |
12227 | #endif | |
12228 | break; | |
12229 | ||
9103f4f4 | 12230 | case OPTION_MARCH: |
293f5f65 L |
12231 | saved = xstrdup (arg); |
12232 | arch = saved; | |
12233 | /* Allow -march=+nosse. */ | |
12234 | if (*arch == '+') | |
12235 | arch++; | |
6305a203 | 12236 | do |
9103f4f4 | 12237 | { |
6305a203 | 12238 | if (*arch == '.') |
2b5d6a91 | 12239 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
12240 | next = strchr (arch, '+'); |
12241 | if (next) | |
12242 | *next++ = '\0'; | |
91d6fa6a | 12243 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 12244 | { |
91d6fa6a | 12245 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 12246 | { |
6305a203 | 12247 | /* Processor. */ |
1ded5609 JB |
12248 | if (! cpu_arch[j].flags.bitfield.cpui386) |
12249 | continue; | |
12250 | ||
91d6fa6a | 12251 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 12252 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
12253 | cpu_arch_flags = cpu_arch[j].flags; |
12254 | cpu_arch_isa = cpu_arch[j].type; | |
12255 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
12256 | if (!cpu_arch_tune_set) |
12257 | { | |
12258 | cpu_arch_tune = cpu_arch_isa; | |
12259 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
12260 | } | |
12261 | break; | |
12262 | } | |
91d6fa6a NC |
12263 | else if (*cpu_arch [j].name == '.' |
12264 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 12265 | { |
33eaf5de | 12266 | /* ISA extension. */ |
6305a203 | 12267 | i386_cpu_flags flags; |
309d3373 | 12268 | |
293f5f65 L |
12269 | flags = cpu_flags_or (cpu_arch_flags, |
12270 | cpu_arch[j].flags); | |
81486035 | 12271 | |
5b64d091 | 12272 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
12273 | { |
12274 | if (cpu_sub_arch_name) | |
12275 | { | |
12276 | char *name = cpu_sub_arch_name; | |
12277 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 12278 | cpu_arch[j].name, |
1bf57e9f | 12279 | (const char *) NULL); |
6305a203 L |
12280 | free (name); |
12281 | } | |
12282 | else | |
91d6fa6a | 12283 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 12284 | cpu_arch_flags = flags; |
a586129e | 12285 | cpu_arch_isa_flags = flags; |
6305a203 | 12286 | } |
0089dace L |
12287 | else |
12288 | cpu_arch_isa_flags | |
12289 | = cpu_flags_or (cpu_arch_isa_flags, | |
12290 | cpu_arch[j].flags); | |
6305a203 | 12291 | break; |
ccc9c027 | 12292 | } |
9103f4f4 | 12293 | } |
6305a203 | 12294 | |
293f5f65 L |
12295 | if (j >= ARRAY_SIZE (cpu_arch)) |
12296 | { | |
33eaf5de | 12297 | /* Disable an ISA extension. */ |
293f5f65 L |
12298 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
12299 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
12300 | { | |
12301 | i386_cpu_flags flags; | |
12302 | ||
12303 | flags = cpu_flags_and_not (cpu_arch_flags, | |
12304 | cpu_noarch[j].flags); | |
12305 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
12306 | { | |
12307 | if (cpu_sub_arch_name) | |
12308 | { | |
12309 | char *name = cpu_sub_arch_name; | |
12310 | cpu_sub_arch_name = concat (arch, | |
12311 | (const char *) NULL); | |
12312 | free (name); | |
12313 | } | |
12314 | else | |
12315 | cpu_sub_arch_name = xstrdup (arch); | |
12316 | cpu_arch_flags = flags; | |
12317 | cpu_arch_isa_flags = flags; | |
12318 | } | |
12319 | break; | |
12320 | } | |
12321 | ||
12322 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
12323 | j = ARRAY_SIZE (cpu_arch); | |
12324 | } | |
12325 | ||
91d6fa6a | 12326 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 12327 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
12328 | |
12329 | arch = next; | |
9103f4f4 | 12330 | } |
293f5f65 L |
12331 | while (next != NULL); |
12332 | free (saved); | |
9103f4f4 L |
12333 | break; |
12334 | ||
12335 | case OPTION_MTUNE: | |
12336 | if (*arg == '.') | |
2b5d6a91 | 12337 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 12338 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 12339 | { |
91d6fa6a | 12340 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 12341 | { |
ccc9c027 | 12342 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
12343 | cpu_arch_tune = cpu_arch [j].type; |
12344 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
12345 | break; |
12346 | } | |
12347 | } | |
91d6fa6a | 12348 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 12349 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
12350 | break; |
12351 | ||
1efbbeb4 L |
12352 | case OPTION_MMNEMONIC: |
12353 | if (strcasecmp (arg, "att") == 0) | |
12354 | intel_mnemonic = 0; | |
12355 | else if (strcasecmp (arg, "intel") == 0) | |
12356 | intel_mnemonic = 1; | |
12357 | else | |
2b5d6a91 | 12358 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
12359 | break; |
12360 | ||
12361 | case OPTION_MSYNTAX: | |
12362 | if (strcasecmp (arg, "att") == 0) | |
12363 | intel_syntax = 0; | |
12364 | else if (strcasecmp (arg, "intel") == 0) | |
12365 | intel_syntax = 1; | |
12366 | else | |
2b5d6a91 | 12367 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
12368 | break; |
12369 | ||
12370 | case OPTION_MINDEX_REG: | |
12371 | allow_index_reg = 1; | |
12372 | break; | |
12373 | ||
12374 | case OPTION_MNAKED_REG: | |
12375 | allow_naked_reg = 1; | |
12376 | break; | |
12377 | ||
c0f3af97 L |
12378 | case OPTION_MSSE2AVX: |
12379 | sse2avx = 1; | |
12380 | break; | |
12381 | ||
daf50ae7 L |
12382 | case OPTION_MSSE_CHECK: |
12383 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 12384 | sse_check = check_error; |
daf50ae7 | 12385 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 12386 | sse_check = check_warning; |
daf50ae7 | 12387 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 12388 | sse_check = check_none; |
daf50ae7 | 12389 | else |
2b5d6a91 | 12390 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
12391 | break; |
12392 | ||
7bab8ab5 JB |
12393 | case OPTION_MOPERAND_CHECK: |
12394 | if (strcasecmp (arg, "error") == 0) | |
12395 | operand_check = check_error; | |
12396 | else if (strcasecmp (arg, "warning") == 0) | |
12397 | operand_check = check_warning; | |
12398 | else if (strcasecmp (arg, "none") == 0) | |
12399 | operand_check = check_none; | |
12400 | else | |
12401 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
12402 | break; | |
12403 | ||
539f890d L |
12404 | case OPTION_MAVXSCALAR: |
12405 | if (strcasecmp (arg, "128") == 0) | |
12406 | avxscalar = vex128; | |
12407 | else if (strcasecmp (arg, "256") == 0) | |
12408 | avxscalar = vex256; | |
12409 | else | |
2b5d6a91 | 12410 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
12411 | break; |
12412 | ||
03751133 L |
12413 | case OPTION_MVEXWIG: |
12414 | if (strcmp (arg, "0") == 0) | |
40c9c8de | 12415 | vexwig = vexw0; |
03751133 | 12416 | else if (strcmp (arg, "1") == 0) |
40c9c8de | 12417 | vexwig = vexw1; |
03751133 L |
12418 | else |
12419 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
12420 | break; | |
12421 | ||
7e8b059b L |
12422 | case OPTION_MADD_BND_PREFIX: |
12423 | add_bnd_prefix = 1; | |
12424 | break; | |
12425 | ||
43234a1e L |
12426 | case OPTION_MEVEXLIG: |
12427 | if (strcmp (arg, "128") == 0) | |
12428 | evexlig = evexl128; | |
12429 | else if (strcmp (arg, "256") == 0) | |
12430 | evexlig = evexl256; | |
12431 | else if (strcmp (arg, "512") == 0) | |
12432 | evexlig = evexl512; | |
12433 | else | |
12434 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
12435 | break; | |
12436 | ||
d3d3c6db IT |
12437 | case OPTION_MEVEXRCIG: |
12438 | if (strcmp (arg, "rne") == 0) | |
12439 | evexrcig = rne; | |
12440 | else if (strcmp (arg, "rd") == 0) | |
12441 | evexrcig = rd; | |
12442 | else if (strcmp (arg, "ru") == 0) | |
12443 | evexrcig = ru; | |
12444 | else if (strcmp (arg, "rz") == 0) | |
12445 | evexrcig = rz; | |
12446 | else | |
12447 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
12448 | break; | |
12449 | ||
43234a1e L |
12450 | case OPTION_MEVEXWIG: |
12451 | if (strcmp (arg, "0") == 0) | |
12452 | evexwig = evexw0; | |
12453 | else if (strcmp (arg, "1") == 0) | |
12454 | evexwig = evexw1; | |
12455 | else | |
12456 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
12457 | break; | |
12458 | ||
167ad85b TG |
12459 | # if defined (TE_PE) || defined (TE_PEP) |
12460 | case OPTION_MBIG_OBJ: | |
12461 | use_big_obj = 1; | |
12462 | break; | |
12463 | #endif | |
12464 | ||
d1982f93 | 12465 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
12466 | if (strcasecmp (arg, "yes") == 0) |
12467 | omit_lock_prefix = 1; | |
12468 | else if (strcasecmp (arg, "no") == 0) | |
12469 | omit_lock_prefix = 0; | |
12470 | else | |
12471 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
12472 | break; | |
12473 | ||
e4e00185 AS |
12474 | case OPTION_MFENCE_AS_LOCK_ADD: |
12475 | if (strcasecmp (arg, "yes") == 0) | |
12476 | avoid_fence = 1; | |
12477 | else if (strcasecmp (arg, "no") == 0) | |
12478 | avoid_fence = 0; | |
12479 | else | |
12480 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
12481 | break; | |
12482 | ||
0cb4071e L |
12483 | case OPTION_MRELAX_RELOCATIONS: |
12484 | if (strcasecmp (arg, "yes") == 0) | |
12485 | generate_relax_relocations = 1; | |
12486 | else if (strcasecmp (arg, "no") == 0) | |
12487 | generate_relax_relocations = 0; | |
12488 | else | |
12489 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
12490 | break; | |
12491 | ||
e379e5f3 L |
12492 | case OPTION_MALIGN_BRANCH_BOUNDARY: |
12493 | { | |
12494 | char *end; | |
12495 | long int align = strtoul (arg, &end, 0); | |
12496 | if (*end == '\0') | |
12497 | { | |
12498 | if (align == 0) | |
12499 | { | |
12500 | align_branch_power = 0; | |
12501 | break; | |
12502 | } | |
12503 | else if (align >= 16) | |
12504 | { | |
12505 | int align_power; | |
12506 | for (align_power = 0; | |
12507 | (align & 1) == 0; | |
12508 | align >>= 1, align_power++) | |
12509 | continue; | |
12510 | /* Limit alignment power to 31. */ | |
12511 | if (align == 1 && align_power < 32) | |
12512 | { | |
12513 | align_branch_power = align_power; | |
12514 | break; | |
12515 | } | |
12516 | } | |
12517 | } | |
12518 | as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg); | |
12519 | } | |
12520 | break; | |
12521 | ||
12522 | case OPTION_MALIGN_BRANCH_PREFIX_SIZE: | |
12523 | { | |
12524 | char *end; | |
12525 | int align = strtoul (arg, &end, 0); | |
12526 | /* Some processors only support 5 prefixes. */ | |
12527 | if (*end == '\0' && align >= 0 && align < 6) | |
12528 | { | |
12529 | align_branch_prefix_size = align; | |
12530 | break; | |
12531 | } | |
12532 | as_fatal (_("invalid -malign-branch-prefix-size= value: %s"), | |
12533 | arg); | |
12534 | } | |
12535 | break; | |
12536 | ||
12537 | case OPTION_MALIGN_BRANCH: | |
12538 | align_branch = 0; | |
12539 | saved = xstrdup (arg); | |
12540 | type = saved; | |
12541 | do | |
12542 | { | |
12543 | next = strchr (type, '+'); | |
12544 | if (next) | |
12545 | *next++ = '\0'; | |
12546 | if (strcasecmp (type, "jcc") == 0) | |
12547 | align_branch |= align_branch_jcc_bit; | |
12548 | else if (strcasecmp (type, "fused") == 0) | |
12549 | align_branch |= align_branch_fused_bit; | |
12550 | else if (strcasecmp (type, "jmp") == 0) | |
12551 | align_branch |= align_branch_jmp_bit; | |
12552 | else if (strcasecmp (type, "call") == 0) | |
12553 | align_branch |= align_branch_call_bit; | |
12554 | else if (strcasecmp (type, "ret") == 0) | |
12555 | align_branch |= align_branch_ret_bit; | |
12556 | else if (strcasecmp (type, "indirect") == 0) | |
12557 | align_branch |= align_branch_indirect_bit; | |
12558 | else | |
12559 | as_fatal (_("invalid -malign-branch= option: `%s'"), arg); | |
12560 | type = next; | |
12561 | } | |
12562 | while (next != NULL); | |
12563 | free (saved); | |
12564 | break; | |
12565 | ||
76cf450b L |
12566 | case OPTION_MBRANCHES_WITH_32B_BOUNDARIES: |
12567 | align_branch_power = 5; | |
12568 | align_branch_prefix_size = 5; | |
12569 | align_branch = (align_branch_jcc_bit | |
12570 | | align_branch_fused_bit | |
12571 | | align_branch_jmp_bit); | |
12572 | break; | |
12573 | ||
5db04b09 | 12574 | case OPTION_MAMD64: |
4b5aaf5f | 12575 | isa64 = amd64; |
5db04b09 L |
12576 | break; |
12577 | ||
12578 | case OPTION_MINTEL64: | |
4b5aaf5f | 12579 | isa64 = intel64; |
5db04b09 L |
12580 | break; |
12581 | ||
b6f8c7c4 L |
12582 | case 'O': |
12583 | if (arg == NULL) | |
12584 | { | |
12585 | optimize = 1; | |
12586 | /* Turn off -Os. */ | |
12587 | optimize_for_space = 0; | |
12588 | } | |
12589 | else if (*arg == 's') | |
12590 | { | |
12591 | optimize_for_space = 1; | |
12592 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 12593 | optimize = INT_MAX; |
b6f8c7c4 L |
12594 | } |
12595 | else | |
12596 | { | |
12597 | optimize = atoi (arg); | |
12598 | /* Turn off -Os. */ | |
12599 | optimize_for_space = 0; | |
12600 | } | |
12601 | break; | |
12602 | ||
252b5132 RH |
12603 | default: |
12604 | return 0; | |
12605 | } | |
12606 | return 1; | |
12607 | } | |
12608 | ||
8a2c8fef L |
12609 | #define MESSAGE_TEMPLATE \ |
12610 | " " | |
12611 | ||
293f5f65 L |
12612 | static char * |
12613 | output_message (FILE *stream, char *p, char *message, char *start, | |
12614 | int *left_p, const char *name, int len) | |
12615 | { | |
12616 | int size = sizeof (MESSAGE_TEMPLATE); | |
12617 | int left = *left_p; | |
12618 | ||
12619 | /* Reserve 2 spaces for ", " or ",\0" */ | |
12620 | left -= len + 2; | |
12621 | ||
12622 | /* Check if there is any room. */ | |
12623 | if (left >= 0) | |
12624 | { | |
12625 | if (p != start) | |
12626 | { | |
12627 | *p++ = ','; | |
12628 | *p++ = ' '; | |
12629 | } | |
12630 | p = mempcpy (p, name, len); | |
12631 | } | |
12632 | else | |
12633 | { | |
12634 | /* Output the current message now and start a new one. */ | |
12635 | *p++ = ','; | |
12636 | *p = '\0'; | |
12637 | fprintf (stream, "%s\n", message); | |
12638 | p = start; | |
12639 | left = size - (start - message) - len - 2; | |
12640 | ||
12641 | gas_assert (left >= 0); | |
12642 | ||
12643 | p = mempcpy (p, name, len); | |
12644 | } | |
12645 | ||
12646 | *left_p = left; | |
12647 | return p; | |
12648 | } | |
12649 | ||
8a2c8fef | 12650 | static void |
1ded5609 | 12651 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
12652 | { |
12653 | static char message[] = MESSAGE_TEMPLATE; | |
12654 | char *start = message + 27; | |
12655 | char *p; | |
12656 | int size = sizeof (MESSAGE_TEMPLATE); | |
12657 | int left; | |
12658 | const char *name; | |
12659 | int len; | |
12660 | unsigned int j; | |
12661 | ||
12662 | p = start; | |
12663 | left = size - (start - message); | |
12664 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
12665 | { | |
12666 | /* Should it be skipped? */ | |
12667 | if (cpu_arch [j].skip) | |
12668 | continue; | |
12669 | ||
12670 | name = cpu_arch [j].name; | |
12671 | len = cpu_arch [j].len; | |
12672 | if (*name == '.') | |
12673 | { | |
12674 | /* It is an extension. Skip if we aren't asked to show it. */ | |
12675 | if (ext) | |
12676 | { | |
12677 | name++; | |
12678 | len--; | |
12679 | } | |
12680 | else | |
12681 | continue; | |
12682 | } | |
12683 | else if (ext) | |
12684 | { | |
12685 | /* It is an processor. Skip if we show only extension. */ | |
12686 | continue; | |
12687 | } | |
1ded5609 JB |
12688 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
12689 | { | |
12690 | /* It is an impossible processor - skip. */ | |
12691 | continue; | |
12692 | } | |
8a2c8fef | 12693 | |
293f5f65 | 12694 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
12695 | } |
12696 | ||
293f5f65 L |
12697 | /* Display disabled extensions. */ |
12698 | if (ext) | |
12699 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
12700 | { | |
12701 | name = cpu_noarch [j].name; | |
12702 | len = cpu_noarch [j].len; | |
12703 | p = output_message (stream, p, message, start, &left, name, | |
12704 | len); | |
12705 | } | |
12706 | ||
8a2c8fef L |
12707 | *p = '\0'; |
12708 | fprintf (stream, "%s\n", message); | |
12709 | } | |
12710 | ||
252b5132 | 12711 | void |
8a2c8fef | 12712 | md_show_usage (FILE *stream) |
252b5132 | 12713 | { |
4cc782b5 ILT |
12714 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12715 | fprintf (stream, _("\ | |
d4693039 | 12716 | -Qy, -Qn ignored\n\ |
a38cf1db | 12717 | -V print assembler version number\n\ |
b3b91714 AM |
12718 | -k ignored\n")); |
12719 | #endif | |
12720 | fprintf (stream, _("\ | |
12b55ccc | 12721 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
12722 | -q quieten some warnings\n")); |
12723 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
12724 | fprintf (stream, _("\ | |
a38cf1db | 12725 | -s ignored\n")); |
b3b91714 | 12726 | #endif |
d7f449c0 L |
12727 | #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
12728 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 12729 | fprintf (stream, _("\ |
570561f7 | 12730 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 12731 | #endif |
b3b91714 AM |
12732 | #ifdef SVR4_COMMENT_CHARS |
12733 | fprintf (stream, _("\ | |
12734 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
12735 | #else |
12736 | fprintf (stream, _("\ | |
b3b91714 | 12737 | --divide ignored\n")); |
4cc782b5 | 12738 | #endif |
9103f4f4 | 12739 | fprintf (stream, _("\ |
6305a203 | 12740 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 12741 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 12742 | show_arch (stream, 0, 1); |
8a2c8fef L |
12743 | fprintf (stream, _("\ |
12744 | EXTENSION is combination of:\n")); | |
1ded5609 | 12745 | show_arch (stream, 1, 0); |
6305a203 | 12746 | fprintf (stream, _("\ |
8a2c8fef | 12747 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 12748 | show_arch (stream, 0, 0); |
ba104c83 | 12749 | fprintf (stream, _("\ |
c0f3af97 L |
12750 | -msse2avx encode SSE instructions with VEX prefix\n")); |
12751 | fprintf (stream, _("\ | |
7c5c05ef | 12752 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
12753 | check SSE instructions\n")); |
12754 | fprintf (stream, _("\ | |
7c5c05ef | 12755 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
12756 | check operand combinations for validity\n")); |
12757 | fprintf (stream, _("\ | |
7c5c05ef L |
12758 | -mavxscalar=[128|256] (default: 128)\n\ |
12759 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
12760 | length\n")); |
12761 | fprintf (stream, _("\ | |
03751133 L |
12762 | -mvexwig=[0|1] (default: 0)\n\ |
12763 | encode VEX instructions with specific VEX.W value\n\ | |
12764 | for VEX.W bit ignored instructions\n")); | |
12765 | fprintf (stream, _("\ | |
7c5c05ef L |
12766 | -mevexlig=[128|256|512] (default: 128)\n\ |
12767 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
12768 | length\n")); |
12769 | fprintf (stream, _("\ | |
7c5c05ef L |
12770 | -mevexwig=[0|1] (default: 0)\n\ |
12771 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
12772 | for EVEX.W bit ignored instructions\n")); |
12773 | fprintf (stream, _("\ | |
7c5c05ef | 12774 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
12775 | encode EVEX instructions with specific EVEX.RC value\n\ |
12776 | for SAE-only ignored instructions\n")); | |
12777 | fprintf (stream, _("\ | |
7c5c05ef L |
12778 | -mmnemonic=[att|intel] ")); |
12779 | if (SYSV386_COMPAT) | |
12780 | fprintf (stream, _("(default: att)\n")); | |
12781 | else | |
12782 | fprintf (stream, _("(default: intel)\n")); | |
12783 | fprintf (stream, _("\ | |
12784 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 12785 | fprintf (stream, _("\ |
7c5c05ef L |
12786 | -msyntax=[att|intel] (default: att)\n\ |
12787 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
12788 | fprintf (stream, _("\ |
12789 | -mindex-reg support pseudo index registers\n")); | |
12790 | fprintf (stream, _("\ | |
12791 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
12792 | fprintf (stream, _("\ | |
7e8b059b | 12793 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 12794 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
12795 | fprintf (stream, _("\ |
12796 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
12797 | fprintf (stream, _("\ |
12798 | -mx86-used-note=[no|yes] ")); | |
12799 | if (DEFAULT_X86_USED_NOTE) | |
12800 | fprintf (stream, _("(default: yes)\n")); | |
12801 | else | |
12802 | fprintf (stream, _("(default: no)\n")); | |
12803 | fprintf (stream, _("\ | |
12804 | generate x86 used ISA and feature properties\n")); | |
12805 | #endif | |
12806 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
12807 | fprintf (stream, _("\ |
12808 | -mbig-obj generate big object files\n")); | |
12809 | #endif | |
d022bddd | 12810 | fprintf (stream, _("\ |
7c5c05ef | 12811 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 12812 | strip all lock prefixes\n")); |
5db04b09 | 12813 | fprintf (stream, _("\ |
7c5c05ef | 12814 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
12815 | encode lfence, mfence and sfence as\n\ |
12816 | lock addl $0x0, (%%{re}sp)\n")); | |
12817 | fprintf (stream, _("\ | |
7c5c05ef L |
12818 | -mrelax-relocations=[no|yes] ")); |
12819 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
12820 | fprintf (stream, _("(default: yes)\n")); | |
12821 | else | |
12822 | fprintf (stream, _("(default: no)\n")); | |
12823 | fprintf (stream, _("\ | |
0cb4071e L |
12824 | generate relax relocations\n")); |
12825 | fprintf (stream, _("\ | |
e379e5f3 L |
12826 | -malign-branch-boundary=NUM (default: 0)\n\ |
12827 | align branches within NUM byte boundary\n")); | |
12828 | fprintf (stream, _("\ | |
12829 | -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\ | |
12830 | TYPE is combination of jcc, fused, jmp, call, ret,\n\ | |
12831 | indirect\n\ | |
12832 | specify types of branches to align\n")); | |
12833 | fprintf (stream, _("\ | |
12834 | -malign-branch-prefix-size=NUM (default: 5)\n\ | |
12835 | align branches with NUM prefixes per instruction\n")); | |
12836 | fprintf (stream, _("\ | |
76cf450b L |
12837 | -mbranches-within-32B-boundaries\n\ |
12838 | align branches within 32 byte boundary\n")); | |
12839 | fprintf (stream, _("\ | |
7c5c05ef | 12840 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
12841 | fprintf (stream, _("\ |
12842 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
12843 | } |
12844 | ||
3e73aa7c | 12845 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 12846 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 12847 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
12848 | |
12849 | /* Pick the target format to use. */ | |
12850 | ||
47926f60 | 12851 | const char * |
e3bb37b5 | 12852 | i386_target_format (void) |
252b5132 | 12853 | { |
351f65ca L |
12854 | if (!strncmp (default_arch, "x86_64", 6)) |
12855 | { | |
12856 | update_code_flag (CODE_64BIT, 1); | |
12857 | if (default_arch[6] == '\0') | |
7f56bc95 | 12858 | x86_elf_abi = X86_64_ABI; |
351f65ca | 12859 | else |
7f56bc95 | 12860 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 12861 | } |
3e73aa7c | 12862 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 12863 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
12864 | else if (!strcmp (default_arch, "iamcu")) |
12865 | { | |
12866 | update_code_flag (CODE_32BIT, 1); | |
12867 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
12868 | { | |
12869 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
12870 | cpu_arch_name = "iamcu"; | |
12871 | cpu_sub_arch_name = NULL; | |
12872 | cpu_arch_flags = iamcu_flags; | |
12873 | cpu_arch_isa = PROCESSOR_IAMCU; | |
12874 | cpu_arch_isa_flags = iamcu_flags; | |
12875 | if (!cpu_arch_tune_set) | |
12876 | { | |
12877 | cpu_arch_tune = cpu_arch_isa; | |
12878 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
12879 | } | |
12880 | } | |
8d471ec1 | 12881 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
12882 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
12883 | cpu_arch_name); | |
12884 | } | |
3e73aa7c | 12885 | else |
2b5d6a91 | 12886 | as_fatal (_("unknown architecture")); |
89507696 JB |
12887 | |
12888 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
12889 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
12890 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
12891 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
12892 | ||
252b5132 RH |
12893 | switch (OUTPUT_FLAVOR) |
12894 | { | |
9384f2ff | 12895 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 12896 | case bfd_target_aout_flavour: |
47926f60 | 12897 | return AOUT_TARGET_FORMAT; |
4c63da97 | 12898 | #endif |
9384f2ff AM |
12899 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
12900 | # if defined (TE_PE) || defined (TE_PEP) | |
12901 | case bfd_target_coff_flavour: | |
167ad85b TG |
12902 | if (flag_code == CODE_64BIT) |
12903 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
12904 | else | |
12905 | return "pe-i386"; | |
9384f2ff | 12906 | # elif defined (TE_GO32) |
0561d57c JK |
12907 | case bfd_target_coff_flavour: |
12908 | return "coff-go32"; | |
9384f2ff | 12909 | # else |
252b5132 RH |
12910 | case bfd_target_coff_flavour: |
12911 | return "coff-i386"; | |
9384f2ff | 12912 | # endif |
4c63da97 | 12913 | #endif |
3e73aa7c | 12914 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 12915 | case bfd_target_elf_flavour: |
3e73aa7c | 12916 | { |
351f65ca L |
12917 | const char *format; |
12918 | ||
12919 | switch (x86_elf_abi) | |
4fa24527 | 12920 | { |
351f65ca L |
12921 | default: |
12922 | format = ELF_TARGET_FORMAT; | |
e379e5f3 L |
12923 | #ifndef TE_SOLARIS |
12924 | tls_get_addr = "___tls_get_addr"; | |
12925 | #endif | |
351f65ca | 12926 | break; |
7f56bc95 | 12927 | case X86_64_ABI: |
351f65ca | 12928 | use_rela_relocations = 1; |
4fa24527 | 12929 | object_64bit = 1; |
e379e5f3 L |
12930 | #ifndef TE_SOLARIS |
12931 | tls_get_addr = "__tls_get_addr"; | |
12932 | #endif | |
351f65ca L |
12933 | format = ELF_TARGET_FORMAT64; |
12934 | break; | |
7f56bc95 | 12935 | case X86_64_X32_ABI: |
4fa24527 | 12936 | use_rela_relocations = 1; |
351f65ca | 12937 | object_64bit = 1; |
e379e5f3 L |
12938 | #ifndef TE_SOLARIS |
12939 | tls_get_addr = "__tls_get_addr"; | |
12940 | #endif | |
862be3fb | 12941 | disallow_64bit_reloc = 1; |
351f65ca L |
12942 | format = ELF_TARGET_FORMAT32; |
12943 | break; | |
4fa24527 | 12944 | } |
3632d14b | 12945 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 12946 | { |
7f56bc95 | 12947 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
12948 | as_fatal (_("Intel L1OM is 64bit only")); |
12949 | return ELF_TARGET_L1OM_FORMAT; | |
12950 | } | |
b49f93f6 | 12951 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
12952 | { |
12953 | if (x86_elf_abi != X86_64_ABI) | |
12954 | as_fatal (_("Intel K1OM is 64bit only")); | |
12955 | return ELF_TARGET_K1OM_FORMAT; | |
12956 | } | |
81486035 L |
12957 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
12958 | { | |
12959 | if (x86_elf_abi != I386_ABI) | |
12960 | as_fatal (_("Intel MCU is 32bit only")); | |
12961 | return ELF_TARGET_IAMCU_FORMAT; | |
12962 | } | |
8a9036a4 | 12963 | else |
351f65ca | 12964 | return format; |
3e73aa7c | 12965 | } |
e57f8c65 TG |
12966 | #endif |
12967 | #if defined (OBJ_MACH_O) | |
12968 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
12969 | if (flag_code == CODE_64BIT) |
12970 | { | |
12971 | use_rela_relocations = 1; | |
12972 | object_64bit = 1; | |
12973 | return "mach-o-x86-64"; | |
12974 | } | |
12975 | else | |
12976 | return "mach-o-i386"; | |
4c63da97 | 12977 | #endif |
252b5132 RH |
12978 | default: |
12979 | abort (); | |
12980 | return NULL; | |
12981 | } | |
12982 | } | |
12983 | ||
47926f60 | 12984 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 12985 | \f |
252b5132 | 12986 | symbolS * |
7016a5d5 | 12987 | md_undefined_symbol (char *name) |
252b5132 | 12988 | { |
18dc2407 ILT |
12989 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
12990 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
12991 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
12992 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
12993 | { |
12994 | if (!GOT_symbol) | |
12995 | { | |
12996 | if (symbol_find (name)) | |
12997 | as_bad (_("GOT already in symbol table")); | |
12998 | GOT_symbol = symbol_new (name, undefined_section, | |
12999 | (valueT) 0, &zero_address_frag); | |
13000 | }; | |
13001 | return GOT_symbol; | |
13002 | } | |
252b5132 RH |
13003 | return 0; |
13004 | } | |
13005 | ||
13006 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 13007 | |
252b5132 | 13008 | valueT |
7016a5d5 | 13009 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 13010 | { |
4c63da97 AM |
13011 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
13012 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
13013 | { | |
13014 | /* For a.out, force the section size to be aligned. If we don't do | |
13015 | this, BFD will align it for us, but it will not write out the | |
13016 | final bytes of the section. This may be a bug in BFD, but it is | |
13017 | easier to fix it here since that is how the other a.out targets | |
13018 | work. */ | |
13019 | int align; | |
13020 | ||
fd361982 | 13021 | align = bfd_section_alignment (segment); |
8d3842cd | 13022 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 13023 | } |
252b5132 RH |
13024 | #endif |
13025 | ||
13026 | return size; | |
13027 | } | |
13028 | ||
13029 | /* On the i386, PC-relative offsets are relative to the start of the | |
13030 | next instruction. That is, the address of the offset, plus its | |
13031 | size, since the offset is always the last part of the insn. */ | |
13032 | ||
13033 | long | |
e3bb37b5 | 13034 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
13035 | { |
13036 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
13037 | } | |
13038 | ||
13039 | #ifndef I386COFF | |
13040 | ||
13041 | static void | |
e3bb37b5 | 13042 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13043 | { |
29b0f896 | 13044 | int temp; |
252b5132 | 13045 | |
8a75718c JB |
13046 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13047 | if (IS_ELF) | |
13048 | obj_elf_section_change_hook (); | |
13049 | #endif | |
252b5132 RH |
13050 | temp = get_absolute_expression (); |
13051 | subseg_set (bss_section, (subsegT) temp); | |
13052 | demand_empty_rest_of_line (); | |
13053 | } | |
13054 | ||
13055 | #endif | |
13056 | ||
e379e5f3 L |
13057 | /* Remember constant directive. */ |
13058 | ||
13059 | void | |
13060 | i386_cons_align (int ignore ATTRIBUTE_UNUSED) | |
13061 | { | |
13062 | if (last_insn.kind != last_insn_directive | |
13063 | && (bfd_section_flags (now_seg) & SEC_CODE)) | |
13064 | { | |
13065 | last_insn.seg = now_seg; | |
13066 | last_insn.kind = last_insn_directive; | |
13067 | last_insn.name = "constant directive"; | |
13068 | last_insn.file = as_where (&last_insn.line); | |
13069 | } | |
13070 | } | |
13071 | ||
252b5132 | 13072 | void |
e3bb37b5 | 13073 | i386_validate_fix (fixS *fixp) |
252b5132 | 13074 | { |
02a86693 | 13075 | if (fixp->fx_subsy) |
252b5132 | 13076 | { |
02a86693 | 13077 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 13078 | { |
02a86693 L |
13079 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
13080 | { | |
13081 | if (!object_64bit) | |
13082 | abort (); | |
13083 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13084 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
13085 | fixp->fx_r_type = (fixp->fx_tcbit |
13086 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
13087 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
13088 | else |
13089 | #endif | |
13090 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
13091 | } | |
d6ab8113 | 13092 | else |
02a86693 L |
13093 | { |
13094 | if (!object_64bit) | |
13095 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
13096 | else | |
13097 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
13098 | } | |
13099 | fixp->fx_subsy = 0; | |
23df1078 | 13100 | } |
252b5132 | 13101 | } |
02a86693 L |
13102 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13103 | else if (!object_64bit) | |
13104 | { | |
13105 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
13106 | && fixp->fx_tcbit2) | |
13107 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
13108 | } | |
13109 | #endif | |
252b5132 RH |
13110 | } |
13111 | ||
252b5132 | 13112 | arelent * |
7016a5d5 | 13113 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13114 | { |
13115 | arelent *rel; | |
13116 | bfd_reloc_code_real_type code; | |
13117 | ||
13118 | switch (fixp->fx_r_type) | |
13119 | { | |
8ce3d284 | 13120 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
13121 | case BFD_RELOC_SIZE32: |
13122 | case BFD_RELOC_SIZE64: | |
13123 | if (S_IS_DEFINED (fixp->fx_addsy) | |
13124 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
13125 | { | |
13126 | /* Resolve size relocation against local symbol to size of | |
13127 | the symbol plus addend. */ | |
13128 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
13129 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
13130 | && !fits_in_unsigned_long (value)) | |
13131 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13132 | _("symbol size computation overflow")); | |
13133 | fixp->fx_addsy = NULL; | |
13134 | fixp->fx_subsy = NULL; | |
13135 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
13136 | return NULL; | |
13137 | } | |
8ce3d284 | 13138 | #endif |
1a0670f3 | 13139 | /* Fall through. */ |
8fd4256d | 13140 | |
3e73aa7c JH |
13141 | case BFD_RELOC_X86_64_PLT32: |
13142 | case BFD_RELOC_X86_64_GOT32: | |
13143 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
13144 | case BFD_RELOC_X86_64_GOTPCRELX: |
13145 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
13146 | case BFD_RELOC_386_PLT32: |
13147 | case BFD_RELOC_386_GOT32: | |
02a86693 | 13148 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
13149 | case BFD_RELOC_386_GOTOFF: |
13150 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
13151 | case BFD_RELOC_386_TLS_GD: |
13152 | case BFD_RELOC_386_TLS_LDM: | |
13153 | case BFD_RELOC_386_TLS_LDO_32: | |
13154 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
13155 | case BFD_RELOC_386_TLS_IE: |
13156 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
13157 | case BFD_RELOC_386_TLS_LE_32: |
13158 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
13159 | case BFD_RELOC_386_TLS_GOTDESC: |
13160 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
13161 | case BFD_RELOC_X86_64_TLSGD: |
13162 | case BFD_RELOC_X86_64_TLSLD: | |
13163 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 13164 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
13165 | case BFD_RELOC_X86_64_GOTTPOFF: |
13166 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
13167 | case BFD_RELOC_X86_64_TPOFF64: |
13168 | case BFD_RELOC_X86_64_GOTOFF64: | |
13169 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
13170 | case BFD_RELOC_X86_64_GOT64: |
13171 | case BFD_RELOC_X86_64_GOTPCREL64: | |
13172 | case BFD_RELOC_X86_64_GOTPC64: | |
13173 | case BFD_RELOC_X86_64_GOTPLT64: | |
13174 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
13175 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
13176 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
13177 | case BFD_RELOC_RVA: |
13178 | case BFD_RELOC_VTABLE_ENTRY: | |
13179 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
13180 | #ifdef TE_PE |
13181 | case BFD_RELOC_32_SECREL: | |
13182 | #endif | |
252b5132 RH |
13183 | code = fixp->fx_r_type; |
13184 | break; | |
dbbaec26 L |
13185 | case BFD_RELOC_X86_64_32S: |
13186 | if (!fixp->fx_pcrel) | |
13187 | { | |
13188 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
13189 | code = fixp->fx_r_type; | |
13190 | break; | |
13191 | } | |
1a0670f3 | 13192 | /* Fall through. */ |
252b5132 | 13193 | default: |
93382f6d | 13194 | if (fixp->fx_pcrel) |
252b5132 | 13195 | { |
93382f6d AM |
13196 | switch (fixp->fx_size) |
13197 | { | |
13198 | default: | |
b091f402 AM |
13199 | as_bad_where (fixp->fx_file, fixp->fx_line, |
13200 | _("can not do %d byte pc-relative relocation"), | |
13201 | fixp->fx_size); | |
93382f6d AM |
13202 | code = BFD_RELOC_32_PCREL; |
13203 | break; | |
13204 | case 1: code = BFD_RELOC_8_PCREL; break; | |
13205 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 13206 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
13207 | #ifdef BFD64 |
13208 | case 8: code = BFD_RELOC_64_PCREL; break; | |
13209 | #endif | |
93382f6d AM |
13210 | } |
13211 | } | |
13212 | else | |
13213 | { | |
13214 | switch (fixp->fx_size) | |
13215 | { | |
13216 | default: | |
b091f402 AM |
13217 | as_bad_where (fixp->fx_file, fixp->fx_line, |
13218 | _("can not do %d byte relocation"), | |
13219 | fixp->fx_size); | |
93382f6d AM |
13220 | code = BFD_RELOC_32; |
13221 | break; | |
13222 | case 1: code = BFD_RELOC_8; break; | |
13223 | case 2: code = BFD_RELOC_16; break; | |
13224 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 13225 | #ifdef BFD64 |
3e73aa7c | 13226 | case 8: code = BFD_RELOC_64; break; |
937149dd | 13227 | #endif |
93382f6d | 13228 | } |
252b5132 RH |
13229 | } |
13230 | break; | |
13231 | } | |
252b5132 | 13232 | |
d182319b JB |
13233 | if ((code == BFD_RELOC_32 |
13234 | || code == BFD_RELOC_32_PCREL | |
13235 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
13236 | && GOT_symbol |
13237 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 13238 | { |
4fa24527 | 13239 | if (!object_64bit) |
d6ab8113 JB |
13240 | code = BFD_RELOC_386_GOTPC; |
13241 | else | |
13242 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 13243 | } |
7b81dfbb AJ |
13244 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
13245 | && GOT_symbol | |
13246 | && fixp->fx_addsy == GOT_symbol) | |
13247 | { | |
13248 | code = BFD_RELOC_X86_64_GOTPC64; | |
13249 | } | |
252b5132 | 13250 | |
add39d23 TS |
13251 | rel = XNEW (arelent); |
13252 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 13253 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
13254 | |
13255 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 13256 | |
3e73aa7c JH |
13257 | if (!use_rela_relocations) |
13258 | { | |
13259 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
13260 | vtable entry to be used in the relocation's section offset. */ | |
13261 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13262 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
13263 | #if defined (OBJ_COFF) && defined (TE_PE) |
13264 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
13265 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
13266 | else | |
13267 | #endif | |
c6682705 | 13268 | rel->addend = 0; |
3e73aa7c JH |
13269 | } |
13270 | /* Use the rela in 64bit mode. */ | |
252b5132 | 13271 | else |
3e73aa7c | 13272 | { |
862be3fb L |
13273 | if (disallow_64bit_reloc) |
13274 | switch (code) | |
13275 | { | |
862be3fb L |
13276 | case BFD_RELOC_X86_64_DTPOFF64: |
13277 | case BFD_RELOC_X86_64_TPOFF64: | |
13278 | case BFD_RELOC_64_PCREL: | |
13279 | case BFD_RELOC_X86_64_GOTOFF64: | |
13280 | case BFD_RELOC_X86_64_GOT64: | |
13281 | case BFD_RELOC_X86_64_GOTPCREL64: | |
13282 | case BFD_RELOC_X86_64_GOTPC64: | |
13283 | case BFD_RELOC_X86_64_GOTPLT64: | |
13284 | case BFD_RELOC_X86_64_PLTOFF64: | |
13285 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13286 | _("cannot represent relocation type %s in x32 mode"), | |
13287 | bfd_get_reloc_code_name (code)); | |
13288 | break; | |
13289 | default: | |
13290 | break; | |
13291 | } | |
13292 | ||
062cd5e7 AS |
13293 | if (!fixp->fx_pcrel) |
13294 | rel->addend = fixp->fx_offset; | |
13295 | else | |
13296 | switch (code) | |
13297 | { | |
13298 | case BFD_RELOC_X86_64_PLT32: | |
13299 | case BFD_RELOC_X86_64_GOT32: | |
13300 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
13301 | case BFD_RELOC_X86_64_GOTPCRELX: |
13302 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
13303 | case BFD_RELOC_X86_64_TLSGD: |
13304 | case BFD_RELOC_X86_64_TLSLD: | |
13305 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
13306 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
13307 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
13308 | rel->addend = fixp->fx_offset - fixp->fx_size; |
13309 | break; | |
13310 | default: | |
13311 | rel->addend = (section->vma | |
13312 | - fixp->fx_size | |
13313 | + fixp->fx_addnumber | |
13314 | + md_pcrel_from (fixp)); | |
13315 | break; | |
13316 | } | |
3e73aa7c JH |
13317 | } |
13318 | ||
252b5132 RH |
13319 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
13320 | if (rel->howto == NULL) | |
13321 | { | |
13322 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 13323 | _("cannot represent relocation type %s"), |
252b5132 RH |
13324 | bfd_get_reloc_code_name (code)); |
13325 | /* Set howto to a garbage value so that we can keep going. */ | |
13326 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 13327 | gas_assert (rel->howto != NULL); |
252b5132 RH |
13328 | } |
13329 | ||
13330 | return rel; | |
13331 | } | |
13332 | ||
ee86248c | 13333 | #include "tc-i386-intel.c" |
54cfded0 | 13334 | |
a60de03c JB |
13335 | void |
13336 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 13337 | { |
a60de03c JB |
13338 | int saved_naked_reg; |
13339 | char saved_register_dot; | |
54cfded0 | 13340 | |
a60de03c JB |
13341 | saved_naked_reg = allow_naked_reg; |
13342 | allow_naked_reg = 1; | |
13343 | saved_register_dot = register_chars['.']; | |
13344 | register_chars['.'] = '.'; | |
13345 | allow_pseudo_reg = 1; | |
13346 | expression_and_evaluate (exp); | |
13347 | allow_pseudo_reg = 0; | |
13348 | register_chars['.'] = saved_register_dot; | |
13349 | allow_naked_reg = saved_naked_reg; | |
13350 | ||
e96d56a1 | 13351 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 13352 | { |
a60de03c JB |
13353 | if ((addressT) exp->X_add_number < i386_regtab_size) |
13354 | { | |
13355 | exp->X_op = O_constant; | |
13356 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
13357 | .dw2_regnum[flag_code >> 1]; | |
13358 | } | |
13359 | else | |
13360 | exp->X_op = O_illegal; | |
54cfded0 | 13361 | } |
54cfded0 AM |
13362 | } |
13363 | ||
13364 | void | |
13365 | tc_x86_frame_initial_instructions (void) | |
13366 | { | |
a60de03c JB |
13367 | static unsigned int sp_regno[2]; |
13368 | ||
13369 | if (!sp_regno[flag_code >> 1]) | |
13370 | { | |
13371 | char *saved_input = input_line_pointer; | |
13372 | char sp[][4] = {"esp", "rsp"}; | |
13373 | expressionS exp; | |
a4447b93 | 13374 | |
a60de03c JB |
13375 | input_line_pointer = sp[flag_code >> 1]; |
13376 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 13377 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
13378 | sp_regno[flag_code >> 1] = exp.X_add_number; |
13379 | input_line_pointer = saved_input; | |
13380 | } | |
a4447b93 | 13381 | |
61ff971f L |
13382 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
13383 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 13384 | } |
d2b2c203 | 13385 | |
d7921315 L |
13386 | int |
13387 | x86_dwarf2_addr_size (void) | |
13388 | { | |
13389 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
13390 | if (x86_elf_abi == X86_64_X32_ABI) | |
13391 | return 4; | |
13392 | #endif | |
13393 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
13394 | } | |
13395 | ||
d2b2c203 DJ |
13396 | int |
13397 | i386_elf_section_type (const char *str, size_t len) | |
13398 | { | |
13399 | if (flag_code == CODE_64BIT | |
13400 | && len == sizeof ("unwind") - 1 | |
13401 | && strncmp (str, "unwind", 6) == 0) | |
13402 | return SHT_X86_64_UNWIND; | |
13403 | ||
13404 | return -1; | |
13405 | } | |
bb41ade5 | 13406 | |
ad5fec3b EB |
13407 | #ifdef TE_SOLARIS |
13408 | void | |
13409 | i386_solaris_fix_up_eh_frame (segT sec) | |
13410 | { | |
13411 | if (flag_code == CODE_64BIT) | |
13412 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
13413 | } | |
13414 | #endif | |
13415 | ||
bb41ade5 AM |
13416 | #ifdef TE_PE |
13417 | void | |
13418 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
13419 | { | |
91d6fa6a | 13420 | expressionS exp; |
bb41ade5 | 13421 | |
91d6fa6a NC |
13422 | exp.X_op = O_secrel; |
13423 | exp.X_add_symbol = symbol; | |
13424 | exp.X_add_number = 0; | |
13425 | emit_expr (&exp, size); | |
bb41ade5 AM |
13426 | } |
13427 | #endif | |
3b22753a L |
13428 | |
13429 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13430 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
13431 | ||
01e1a5bc | 13432 | bfd_vma |
6d4af3c2 | 13433 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
13434 | { |
13435 | if (flag_code == CODE_64BIT) | |
13436 | { | |
13437 | if (letter == 'l') | |
13438 | return SHF_X86_64_LARGE; | |
13439 | ||
8f3bae45 | 13440 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 13441 | } |
3b22753a | 13442 | else |
8f3bae45 | 13443 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
13444 | return -1; |
13445 | } | |
13446 | ||
01e1a5bc | 13447 | bfd_vma |
3b22753a L |
13448 | x86_64_section_word (char *str, size_t len) |
13449 | { | |
8620418b | 13450 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
13451 | return SHF_X86_64_LARGE; |
13452 | ||
13453 | return -1; | |
13454 | } | |
13455 | ||
13456 | static void | |
13457 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
13458 | { | |
13459 | if (flag_code != CODE_64BIT) | |
13460 | { | |
13461 | s_comm_internal (0, elf_common_parse); | |
13462 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
13463 | } | |
13464 | else | |
13465 | { | |
13466 | static segT lbss_section; | |
13467 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
13468 | asection *saved_bss_section = bss_section; | |
13469 | ||
13470 | if (lbss_section == NULL) | |
13471 | { | |
13472 | flagword applicable; | |
13473 | segT seg = now_seg; | |
13474 | subsegT subseg = now_subseg; | |
13475 | ||
13476 | /* The .lbss section is for local .largecomm symbols. */ | |
13477 | lbss_section = subseg_new (".lbss", 0); | |
13478 | applicable = bfd_applicable_section_flags (stdoutput); | |
fd361982 | 13479 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
3b22753a L |
13480 | seg_info (lbss_section)->bss = 1; |
13481 | ||
13482 | subseg_set (seg, subseg); | |
13483 | } | |
13484 | ||
13485 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
13486 | bss_section = lbss_section; | |
13487 | ||
13488 | s_comm_internal (0, elf_common_parse); | |
13489 | ||
13490 | elf_com_section_ptr = saved_com_section_ptr; | |
13491 | bss_section = saved_bss_section; | |
13492 | } | |
13493 | } | |
13494 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |